diff --git a/.github/workflows/autogen.yml b/.github/workflows/autogen.yml index 3aedf04d5d..98947c2a6e 100644 --- a/.github/workflows/autogen.yml +++ b/.github/workflows/autogen.yml @@ -19,7 +19,7 @@ on: jobs: autogen: - name: Autogen + name: In-tree Autogen runs-on: ubuntu-24.04 timeout-minutes: 15 steps: @@ -31,66 +31,107 @@ jobs: opencl: 'true' amd: 'true' cuda: 'true' - webgpu: 'true' llvm: 'true' - pydeps: 'pyyaml mako' + webgpu: 'true' + mesa: 'true' + pydeps: 'clang>=20 pyyaml mako' - name: Install autogen support packages - run: sudo apt-get install -y --no-install-recommends llvm-14-dev libclang-14-dev llvm-20-dev + run: sudo apt-get install -y --no-install-recommends libclang-20-dev llvm-20-dev hip-dev libusb-1.0-0-dev - name: Verify OpenCL autogen run: | - cp tinygrad/runtime/autogen/opencl.py /tmp/opencl.py.bak - ./autogen_stubs.sh opencl + mv tinygrad/runtime/autogen/opencl.py /tmp/opencl.py.bak + python3 -c "from tinygrad.runtime.autogen import opencl" diff /tmp/opencl.py.bak tinygrad/runtime/autogen/opencl.py - name: Verify CUDA autogen run: | - cp tinygrad/runtime/autogen/cuda.py /tmp/cuda.py.bak - cp tinygrad/runtime/autogen/nv_gpu.py /tmp/nv_gpu.py.bak - ./autogen_stubs.sh cuda - ./autogen_stubs.sh nv + mv tinygrad/runtime/autogen/cuda.py /tmp/cuda.py.bak + mv tinygrad/runtime/autogen/nvrtc.py /tmp/nvrtc.py.bak + mv tinygrad/runtime/autogen/nvjitlink.py /tmp/nvjitlink.py.bak + mv tinygrad/runtime/autogen/nv_gpu.py /tmp/nv_gpu.py.bak + mv tinygrad/runtime/autogen/nv.py /tmp/nv.py.bak + python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_gpu, nv" diff /tmp/cuda.py.bak tinygrad/runtime/autogen/cuda.py + diff /tmp/nvrtc.py.bak tinygrad/runtime/autogen/nvrtc.py + diff /tmp/nvjitlink.py.bak tinygrad/runtime/autogen/nvjitlink.py diff /tmp/nv_gpu.py.bak tinygrad/runtime/autogen/nv_gpu.py + diff /tmp/nv.py.bak tinygrad/runtime/autogen/nv.py - name: Verify AMD autogen run: | - cp tinygrad/runtime/autogen/hsa.py /tmp/hsa.py.bak - cp tinygrad/runtime/autogen/kfd.py /tmp/kfd.py.bak - cp tinygrad/runtime/autogen/comgr.py /tmp/comgr.py.bak - cp tinygrad/runtime/autogen/amd_gpu.py /tmp/amd_gpu.py.bak - cp tinygrad/runtime/autogen/sqtt.py /tmp/sqtt.py.bak - ./autogen_stubs.sh hsa - ./autogen_stubs.sh kfd - ./autogen_stubs.sh comgr - ./autogen_stubs.sh amd - ./autogen_stubs.sh sqtt - diff /tmp/hsa.py.bak tinygrad/runtime/autogen/hsa.py - diff /tmp/kfd.py.bak tinygrad/runtime/autogen/kfd.py + mv tinygrad/runtime/autogen/comgr.py /tmp/comgr.py.bak + mv tinygrad/runtime/autogen/hsa.py /tmp/hsa.py.bak + mv tinygrad/runtime/autogen/hip.py /tmp/hip.py.bak + mv tinygrad/runtime/autogen/amd_gpu.py /tmp/amd_gpu.py.bak + mv tinygrad/runtime/autogen/sqtt.py /tmp/sqtt.py.bak + mv tinygrad/runtime/autogen/rocprof.py /tmp/rocprof.py.bak + mv tinygrad/runtime/autogen/am/am.py /tmp/am_am.py.bak + mv tinygrad/runtime/autogen/am/pm4_soc15.py /tmp/am_pm4_soc15.py.bak + mv tinygrad/runtime/autogen/am/pm4_nv.py /tmp/am_pm4_nv.py.bak + mv tinygrad/runtime/autogen/am/sdma_4_0_0.py /tmp/am_sdma_4_0_0.py.bak + mv tinygrad/runtime/autogen/am/sdma_5_0_0.py /tmp/am_sdma_5_0_0.py.bak + mv tinygrad/runtime/autogen/am/sdma_6_0_0.py /tmp/am_sdma_6_0_0.py.bak + mv tinygrad/runtime/autogen/am/smu_v13_0_0.py /tmp/am_smu_v13_0_0.py.bak + mv tinygrad/runtime/autogen/am/smu_v14_0_2.py /tmp/am_smu_v14_0_2.py.bak + python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof; from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v14_0_2" diff /tmp/comgr.py.bak tinygrad/runtime/autogen/comgr.py + diff /tmp/hsa.py.bak tinygrad/runtime/autogen/hsa.py + diff /tmp/hip.py.bak tinygrad/runtime/autogen/hip.py diff /tmp/amd_gpu.py.bak tinygrad/runtime/autogen/amd_gpu.py diff /tmp/sqtt.py.bak tinygrad/runtime/autogen/sqtt.py + diff /tmp/rocprof.py.bak tinygrad/runtime/autogen/rocprof.py + diff /tmp/am_am.py.bak tinygrad/runtime/autogen/am/am.py + diff /tmp/am_pm4_soc15.py.bak tinygrad/runtime/autogen/am/pm4_soc15.py + diff /tmp/am_pm4_nv.py.bak tinygrad/runtime/autogen/am/pm4_nv.py + diff /tmp/am_sdma_4_0_0.py.bak tinygrad/runtime/autogen/am/sdma_4_0_0.py + diff /tmp/am_sdma_5_0_0.py.bak tinygrad/runtime/autogen/am/sdma_5_0_0.py + diff /tmp/am_sdma_6_0_0.py.bak tinygrad/runtime/autogen/am/sdma_6_0_0.py + diff /tmp/am_smu_v13_0_0.py.bak tinygrad/runtime/autogen/am/smu_v13_0_0.py + diff /tmp/am_smu_v14_0_2.py.bak tinygrad/runtime/autogen/am/smu_v14_0_2.py - name: Verify Linux autogen run: | - cp tinygrad/runtime/autogen/io_uring.py /tmp/io_uring.py.bak - cp tinygrad/runtime/autogen/ib.py /tmp/ib.py.bak - ./autogen_stubs.sh io_uring - ./autogen_stubs.sh ib + mv tinygrad/runtime/autogen/libc.py /tmp/libc.py.bak + mv tinygrad/runtime/autogen/kfd.py /tmp/kfd.py.bak + mv tinygrad/runtime/autogen/io_uring.py /tmp/io_uring.py.bak + mv tinygrad/runtime/autogen/ib.py /tmp/ib.py.bak + mv tinygrad/runtime/autogen/pci.py /tmp/pci.py.bak + mv tinygrad/runtime/autogen/vfio.py /tmp/vfio.py.bak + python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio" + diff /tmp/libc.py.bak tinygrad/runtime/autogen/libc.py + diff /tmp/kfd.py.bak tinygrad/runtime/autogen/kfd.py diff /tmp/io_uring.py.bak tinygrad/runtime/autogen/io_uring.py diff /tmp/ib.py.bak tinygrad/runtime/autogen/ib.py - - name: Verify WebGPU autogen - run: | - cp tinygrad/runtime/autogen/webgpu.py /tmp/webgpu.py.bak - ./autogen_stubs.sh webgpu - diff /tmp/webgpu.py.bak tinygrad/runtime/autogen/webgpu.py + diff /tmp/pci.py.bak tinygrad/runtime/autogen/pci.py + diff /tmp/vfio.py.bak tinygrad/runtime/autogen/vfio.py - name: Verify LLVM autogen run: | - cp tinygrad/runtime/autogen/llvm.py /tmp/llvm.py.bak - ./autogen_stubs.sh llvm + mv tinygrad/runtime/autogen/llvm.py /tmp/llvm.py.bak + python3 -c "from tinygrad.runtime.autogen import llvm" diff /tmp/llvm.py.bak tinygrad/runtime/autogen/llvm.py + - name: Verify WebGPU autogen + run: | + mv tinygrad/runtime/autogen/webgpu.py /tmp/webgpu.py.bak + python3 -c "from tinygrad.runtime.autogen import webgpu" + diff /tmp/webgpu.py.bak tinygrad/runtime/autogen/webgpu.py + - name: Verify Qualcomm autogen + run: | + mv tinygrad/runtime/autogen/kgsl.py /tmp/kgsl.py.bak + mv tinygrad/runtime/autogen/adreno.py /tmp/adreno.py.bak + mv tinygrad/runtime/autogen/qcom_dsp.py /tmp/qcom_dsp.py.bak + python3 -c "from tinygrad.runtime.autogen import kgsl, adreno, qcom_dsp" + diff /tmp/kgsl.py.bak tinygrad/runtime/autogen/kgsl.py + diff /tmp/adreno.py.bak tinygrad/runtime/autogen/adreno.py + diff /tmp/qcom_dsp.py.bak tinygrad/runtime/autogen/qcom_dsp.py + - name: Verify libusb autogen + run: | + mv tinygrad/runtime/autogen/libusb.py /tmp/libusb.py.bak + python3 -c "from tinygrad.runtime.autogen import libusb" + diff /tmp/libusb.py.bak tinygrad/runtime/autogen/libusb.py - name: Verify mesa autogen run: | - cp tinygrad/runtime/autogen/mesa.py /tmp/mesa.py.bak - ./autogen_stubs.sh mesa + mv tinygrad/runtime/autogen/mesa.py /tmp/mesa.py.bak + python3 -c "from tinygrad.runtime.autogen import mesa" diff /tmp/mesa.py.bak tinygrad/runtime/autogen/mesa.py - autogen-ng: - name: In-tree Autogen + autogen-comgr-3: + name: In-tree Autogen (comgr 3) runs-on: ubuntu-24.04 timeout-minutes: 15 steps: @@ -101,9 +142,16 @@ jobs: with: pydeps: 'clang>=20' - name: Install autogen support packages - run: sudo apt-get install -y --no-install-recommends libclang-20-dev - - name: Verify Linux autogen run: | - mv tinygrad/runtime/autogen/libc.py /tmp/libc.py.bak - python3 -c "from tinygrad.runtime.autogen import libc" - diff /tmp/libc.py.bak tinygrad/runtime/autogen/libc.py + wget https://repo.radeon.com/rocm/rocm.gpg.key -O - | gpg --dearmor | sudo tee /etc/apt/keyrings/rocm.gpg > /dev/null + sudo tee /etc/apt/sources.list.d/rocm.list <> $BASE/hip.py - echo "hipGetDeviceProperties = hipGetDevicePropertiesR0600" >> $BASE/hip.py - fixup $BASE/hip.py - # we can trust HIP is always at /opt/rocm/lib - #sed -i "s\import ctypes\import ctypes, ctypes.util\g" $BASE/hip.py - #sed -i "s\ctypes.CDLL('/opt/rocm/lib/libhiprtc.so')\ctypes.CDLL(ctypes.util.find_library('hiprtc'))\g" $BASE/hip.py - #sed -i "s\ctypes.CDLL('/opt/rocm/lib/libamdhip64.so')\ctypes.CDLL(ctypes.util.find_library('amdhip64'))\g" $BASE/hip.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/hip.py - sed -i "s\'/opt/rocm/\os.getenv('ROCM_PATH', '/opt/rocm/')+'/\g" $BASE/hip.py - python3 -c "import tinygrad.runtime.autogen.hip" -} - -generate_comgr() { - clang2py /opt/rocm/include/amd_comgr/amd_comgr.h \ - --clang-args="-D__HIP_PLATFORM_AMD__ -I/opt/rocm/include -x c++" -o $BASE/comgr.py -l /opt/rocm/lib/libamd_comgr.so - fixup $BASE/comgr.py - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/comgr.py - patch_dlopen $BASE/comgr.py amd_comgr "'/opt/rocm/lib/libamd_comgr.so'" "os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so'" "'/usr/local/lib/libamd_comgr.dylib'" "'/opt/homebrew/lib/libamd_comgr.dylib'" - sed -i "s\ctypes.CDLL('/opt/rocm/lib/libamd_comgr.so')\_try_dlopen_amd_comgr()\g" $BASE/comgr.py - python3 -c "import tinygrad.runtime.autogen.comgr" -} - -generate_kfd() { - clang2py /usr/include/linux/kfd_ioctl.h -o $BASE/kfd.py -k cdefstum - - fixup $BASE/kfd.py - sed -i "s/import ctypes/import ctypes, os/g" $BASE/kfd.py - sed -i "s/import fcntl, functools/import functools/g" $BASE/kfd.py - sed -i "/import functools/a from tinygrad.runtime.support.hcq import FileIOInterface" $BASE/kfd.py - sed -i "s/def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, \*\*kwargs):/def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:FileIOInterface, \*\*kwargs):/g" $BASE/kfd.py - sed -i "s/fcntl.ioctl(__fd, (__idir<<30)/__fd.ioctl((__idir<<30)/g" $BASE/kfd.py - sed -i "s/!!/not not /g" $BASE/kfd.py - python3 -c "import tinygrad.runtime.autogen.kfd" -} - -generate_cuda() { - clang2py /usr/include/cuda.h --clang-args="-D__CUDA_API_VERSION_INTERNAL" -o $BASE/cuda.py -l /usr/lib/x86_64-linux-gnu/libcuda.so - sed -i "s\import ctypes\import ctypes, ctypes.util\g" $BASE/cuda.py - sed -i "s\ctypes.CDLL('/usr/lib/x86_64-linux-gnu/libcuda.so')\ctypes.CDLL(ctypes.util.find_library('cuda'))\g" $BASE/cuda.py - fixup $BASE/cuda.py - python3 -c "import tinygrad.runtime.autogen.cuda" -} - -generate_nvrtc() { - clang2py /usr/local/cuda/include/nvrtc.h /usr/local/cuda/include/nvJitLink.h -o $BASE/nvrtc.py -l /usr/local/cuda/lib64/libnvrtc.so -l /usr/local/cuda/lib64/libnvJitLink.so - sed -i "s\import ctypes\import ctypes, ctypes.util\g" $BASE/nvrtc.py - sed -i "s\ctypes.CDLL('/usr/local/cuda/lib64/libnvrtc.so')\ctypes.CDLL(ctypes.util.find_library('nvrtc'))\g" $BASE/nvrtc.py - sed -i "s\ctypes.CDLL('/usr/local/cuda/lib64/libnvJitLink.so')\ctypes.CDLL(ctypes.util.find_library('nvJitLink'))\g" $BASE/nvrtc.py - fixup $BASE/nvrtc.py - python3 -c "import tinygrad.runtime.autogen.nvrtc" -} - -generate_nv() { - NVKERN_COMMIT_HASH=81fe4fb417c8ac3b9bdcc1d56827d116743892a5 - NVKERN_SRC=/tmp/open-gpu-kernel-modules-$NVKERN_COMMIT_HASH - if [ ! -d "$NVKERN_SRC" ]; then - git clone https://github.com/NVIDIA/open-gpu-kernel-modules $NVKERN_SRC - pushd . - cd $NVKERN_SRC - git reset --hard $NVKERN_COMMIT_HASH - popd - fi - - clang2py -k cdefstum \ - extra/nv_gpu_driver/clc6c0qmd.h \ - extra/nv_gpu_driver/clcec0qmd.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl0000.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl0080.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl2080.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl2080_notification.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc56f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc86f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc96f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc761.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/cl83de.h \ - $NVKERN_SRC/src/nvidia/generated/g_allclasses.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clc6c0.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/class/clcdc0.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/clc6b5.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/clc9b5.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/uvm_ioctl.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/uvm_linux_ioctl.h \ - $NVKERN_SRC/kernel-open/nvidia-uvm/hwref/ampere/ga100/dev_fault.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv_escape.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-ioctl.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numbers.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/alloc/alloc_channel.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/nvos.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl0000/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl0080/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl2080/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl83de/*.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h \ - --clang-args="-include $NVKERN_SRC/src/common/sdk/nvidia/inc/nvtypes.h -I$NVKERN_SRC/src/common/inc -I$NVKERN_SRC/kernel-open/nvidia-uvm -I$NVKERN_SRC/kernel-open/common/inc -I$NVKERN_SRC/src/common/sdk/nvidia/inc -I$NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include -I$NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl" \ - -o $BASE/nv_gpu.py - fixup $BASE/nv_gpu.py - sed -i "s\(0000000001)\1\g" $BASE/nv_gpu.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/nv_gpu.py - sed -i 's/#\?\s\([A-Za-z0-9_]\+\) = MW ( \([0-9]\+\) : \([0-9]\+\) )/\1 = (\2 , \3)/' $BASE/nv_gpu.py # NVC6C0_QMDV03_00 processing - sed -i 's/#\sdef NVC6C0_QMD\([A-Za-z0-9_()]\+\):/def NVC6C0_QMD\1:/' $BASE/nv_gpu.py - sed -i 's/#\sdef NVCEC0_QMD\([A-Za-z0-9_()]\+\):/def NVCEC0_QMD\1:/' $BASE/nv_gpu.py - sed -E -i -n '/^def (NVCEC0_QMDV05_00_RELEASE)(_ENABLE)\(i\):/{p;s//\1'"0"'\2=\1\2(0)\n\1'"1"'\2=\1\2(1)/;H;b};p;${x;s/^\n//;p}' "$BASE/nv_gpu.py" - sed -i 's/#\s*return MW(\([0-9i()*+]\+\):\([0-9i()*+]\+\))/ return (\1 , \2)/' $BASE/nv_gpu.py - sed -i 's/#\?\s*\(.*\)\s*=\s*\(NV\)\?BIT\(32\)\?\s*(\s*\([0-9]\+\)\s*)/\1 = (1 << \4)/' $BASE/nv_gpu.py # name = BIT(x) -> name = (1 << x) - sed -i "s/UVM_\([A-Za-z0-9_]\+\) = \['i', '(', '\([0-9]\+\)', ')'\]/UVM_\1 = \2/" $BASE/nv_gpu.py # UVM_name = ['i', '(', '', ')'] -> UVM_name = - - # Parse status codes - sed -n '1i\ -nv_status_codes = {} -/^NV_STATUS_CODE/ { s/^NV_STATUS_CODE(\([^,]*\), *\([^,]*\), *"\([^"]*\)") *.*$/\1 = \2\nnv_status_codes[\1] = "\3"/; p }' $NVKERN_SRC/src/common/sdk/nvidia/inc/nvstatuscodes.h >> $BASE/nv_gpu.py - python3 -c "import tinygrad.runtime.autogen.nv_gpu" - - clang2py -k cdefstum \ - $NVKERN_SRC/src/nvidia/inc/kernel/gpu/fsp/kern_fsp_cot_payload.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_sr_meta.h \ - $NVKERN_SRC/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h \ - $NVKERN_SRC/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h \ - $NVKERN_SRC/src/common/uproc/os/common/include/libos_init_args.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc/rmRiscvUcode.h \ - $NVKERN_SRC/src/common/shared/msgq/inc/msgq/msgq_priv.h \ - $NVKERN_SRC/src/nvidia/inc/kernel/vgpu/rpc_headers.h \ - $NVKERN_SRC/src/nvidia/inc/kernel/vgpu/rpc_global_enums.h \ - $NVKERN_SRC/src/nvidia/generated/g_rpc-structures.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h \ - extra/nv_gpu_driver/g_rpc-message-header.h \ - extra/nv_gpu_driver/gsp_static_config.h \ - extra/nv_gpu_driver/vbios.h \ - extra/nv_gpu_driver/pci_exp_table.h \ - --clang-args="-DRPC_MESSAGE_STRUCTURES -DRPC_STRUCTURES -include $NVKERN_SRC/src/common/sdk/nvidia/inc/nvtypes.h -I$NVKERN_SRC/src/nvidia/generated -I$NVKERN_SRC/src/common/inc -I$NVKERN_SRC/src/nvidia/inc -I$NVKERN_SRC/src/nvidia/interface/ -I$NVKERN_SRC/src/nvidia/inc/kernel -I$NVKERN_SRC/src/nvidia/inc/libraries -I$NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc -I$NVKERN_SRC/kernel-open/nvidia-uvm -I$NVKERN_SRC/kernel-open/common/inc -I$NVKERN_SRC/src/common/sdk/nvidia/inc -I$NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include -I$NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl" \ - -o $BASE/nv/nv.py - - fixup $BASE/nv/nv.py - python3 -c "import tinygrad.runtime.autogen.nv.nv" -} - -generate_amd() { - # clang2py broken when pass -x c++ to prev headers - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - extra/hip_gpu_driver/nvd.h \ - extra/hip_gpu_driver/gc_11_0_0_offset.h \ - extra/hip_gpu_driver/sienna_cichlid_ip_offset.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/amd_gpu.py - - fixup $BASE/amd_gpu.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/amd_gpu.py - python3 -c "import tinygrad.runtime.autogen.amd_gpu" -} - -generate_hsa() { - clang2py \ - /opt/rocm/include/hsa/hsa.h \ - /opt/rocm/include/hsa/hsa_ext_amd.h \ - /opt/rocm/include/hsa/amd_hsa_signal.h \ - /opt/rocm/include/hsa/amd_hsa_queue.h \ - /opt/rocm/include/hsa/amd_hsa_kernel_code.h \ - /opt/rocm/include/hsa/hsa_ext_finalize.h /opt/rocm/include/hsa/hsa_ext_image.h \ - /opt/rocm/include/hsa/hsa_ven_amd_aqlprofile.h \ - --clang-args="-I/opt/rocm/include" \ - -o $BASE/hsa.py -l /opt/rocm/lib/libhsa-runtime64.so - - fixup $BASE/hsa.py - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/hsa.py - sed -i "s\ctypes.CDLL('/opt/rocm/lib/libhsa-runtime64.so')\ctypes.CDLL(os.getenv('ROCM_PATH')+'/lib/libhsa-runtime64.so' if os.getenv('ROCM_PATH') else ctypes.util.find_library('hsa-runtime64'))\g" $BASE/hsa.py - python3 -c "import tinygrad.runtime.autogen.hsa" -} - -generate_io_uring() { - clang2py -k cdefstum \ - /usr/include/liburing.h \ - /usr/include/linux/io_uring.h \ - -o $BASE/io_uring.py - - sed -r '/^#define __NR_io_uring/ s/^#define __(NR_io_uring[^ ]+) (.*)$/\1 = \2/; t; d' /usr/include/asm-generic/unistd.h >> $BASE/io_uring.py # io_uring syscalls numbers - fixup $BASE/io_uring.py -} - -generate_ib() { - clang2py -k cdefstum \ - /usr/include/infiniband/verbs.h \ - /usr/include/infiniband/verbs_api.h \ - /usr/include/infiniband/ib_user_ioctl_verbs.h \ - /usr/include/rdma/ib_user_verbs.h \ - -o $BASE/ib.py - - sed -i "s\import ctypes\import ctypes, ctypes.util\g" "$BASE/ib.py" - sed -i "s\FIXME_STUB\libibverbs\g" "$BASE/ib.py" - sed -i "s\FunctionFactoryStub()\ctypes.CDLL(ctypes.util.find_library('ibverbs'), use_errno=True)\g" "$BASE/ib.py" - - fixup $BASE/ib.py -} - -generate_llvm() { - INC="$(llvm-config-14 --includedir)" - clang2py -k cdefstum \ - $(find "$INC/llvm-c/" -type f -name '*.h' | sort) \ - "$INC/llvm/Config/Targets.def" \ - "$INC/llvm/Config/AsmPrinters.def" \ - "$INC/llvm/Config/AsmParsers.def" \ - "$INC/llvm/Config/Disassemblers.def" \ - --clang-args="$(llvm-config-14 --cflags)" \ - -o "$BASE/llvm.py" - - sed -i "s\import ctypes\import ctypes, tinygrad.runtime.support.llvm as llvm_support\g" "$BASE/llvm.py" - sed -i "s\FIXME_STUB\llvm\g" "$BASE/llvm.py" - sed -i "s\FunctionFactoryStub()\ctypes.CDLL(llvm_support.LLVM_PATH)\g" "$BASE/llvm.py" - - fixup "$BASE/llvm.py" -} - -generate_kgsl() { - clang2py extra/qcom_gpu_driver/msm_kgsl.h -o $BASE/kgsl.py -k cdefstum - fixup $BASE/kgsl.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/kgsl.py - sed -nE 's/#define ([A-Za-z0-9_]+)_SHIFT\s*[^\S\r\n]*[0-9]*$/def \1(val): return (val << \1_SHIFT) \& \1_MASK/p' extra/qcom_gpu_driver/msm_kgsl.h >> $BASE/kgsl.py - sed -i "s\fcntl.ioctl(__fd, (__idir<<30)\__fd.ioctl((__idir<<30)\g" $BASE/kgsl.py - python3 -c "import tinygrad.runtime.autogen.kgsl" -} - -generate_adreno() { - clang2py extra/qcom_gpu_driver/a6xx.xml.h -o $BASE/adreno.py -k cestum - sed -nE 's/#define ([A-Za-z0-9_]+)__SHIFT\s*[^\S\r\n]*[0-9]*$/def \1(val): return (val << \1__SHIFT) \& \1__MASK/p' extra/qcom_gpu_driver/a6xx.xml.h >> $BASE/adreno.py - fixup $BASE/adreno.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/adreno.py - python3 -c "import tinygrad.runtime.autogen.adreno" -} - -generate_qcom() { - clang2py -k cdefstum \ - extra/dsp/include/ion.h \ - extra/dsp/include/msm_ion.h \ - extra/dsp/include/adsprpc_shared.h \ - extra/dsp/include/remote_default.h \ - extra/dsp/include/apps_std.h \ - -o $BASE/qcom_dsp.py - - fixup $BASE/qcom_dsp.py - python3 -c "import tinygrad.runtime.autogen.qcom_dsp" -} - -generate_pci() { - clang2py -k cdefstum \ - /usr/include/linux/pci_regs.h \ - -o $BASE/pci.py - fixup $BASE/pci.py -} - -generate_vfio() { - clang2py -k cdefstum \ - /usr/include/linux/vfio.h \ - -o $BASE/vfio.py - fixup $BASE/vfio.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/vfio.py - sed -i "s\import fcntl, functools\import functools" $BASE/vfio.py - sed -i "s\import ctypes,os\a from tinygrad.runtime.support import FileIOInterface\g" $BASE/vfio.py - sed -i "s\fcntl.ioctl(__fd, (__idir<<30)\return __fd.ioctl((__idir<<30)\g" $BASE/vfio.py -} - -generate_am() { - AMKERN_COMMIT_HASH=ceb12c04e2b5b53ec0779362831f5ee40c4921e4 - AMKERN_SRC=/tmp/ROCK-Kernel-Driver-$AMKERN_COMMIT_HASH - if [ ! -d "$AMKERN_SRC" ]; then - git clone https://github.com/ROCm/ROCK-Kernel-Driver $AMKERN_SRC --depth 1 - fi - AMKERN_AMD=$AMKERN_SRC/drivers/gpu/drm/amd/ - AMKERN_INC=$AMKERN_AMD/include/ - - clang2py -k cdefstum \ - extra/amdpci/headers/v11_structs.h \ - extra/amdpci/headers/v12_structs.h \ - extra/amdpci/headers/amdgpu_vm.h \ - extra/amdpci/headers/discovery.h \ - extra/amdpci/headers/amdgpu_ucode.h \ - extra/amdpci/headers/psp_gfx_if.h \ - extra/amdpci/headers/amdgpu_psp.h \ - extra/amdpci/headers/amdgpu_irq.h \ - extra/amdpci/headers/amdgpu_doorbell.h \ - $AMKERN_INC/soc15_ih_clientid.h \ - --clang-args="-include stdint.h" \ - -o $BASE/am/am.py - fixup $BASE/am/am.py - sed -i "s\(int64_t)\ \g" $BASE/am/am.py - sed -i "s\AMDGPU_PTE_MTYPE_VG10(2)\AMDGPU_PTE_MTYPE_VG10(0, 2)\g" $BASE/am/am.py # incorrect parsing (TODO: remove when clang2py is gone). - - clang2py -k cdefstum \ - $AMKERN_AMD/amdkfd/kfd_pm4_headers_ai.h \ - $AMKERN_AMD/amdgpu/soc15d.h \ - -o $BASE/am/pm4_soc15.py - fixup $BASE/am/pm4_soc15.py - - clang2py -k cdefstum \ - $AMKERN_AMD/amdkfd/kfd_pm4_headers_ai.h \ - $AMKERN_AMD/amdgpu/nvd.h \ - -o $BASE/am/pm4_nv.py - fixup $BASE/am/pm4_nv.py - - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - $AMKERN_AMD/amdgpu/vega10_sdma_pkt_open.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/am/sdma_4_0_0.py - fixup $BASE/am/sdma_4_0_0.py - - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - $AMKERN_AMD/amdgpu/navi10_sdma_pkt_open.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/am/sdma_5_0_0.py - fixup $BASE/am/sdma_5_0_0.py - - clang2py -k cdefstum \ - extra/hip_gpu_driver/sdma_registers.h \ - $AMKERN_AMD/amdgpu/sdma_v6_0_0_pkt_open.h \ - --clang-args="-I/opt/rocm/include -x c++" \ - -o $BASE/am/sdma_6_0_0.py - fixup $BASE/am/sdma_6_0_0.py - - clang2py -k cdefstum \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h \ - extra/amdpci/headers/amdgpu_smu.h \ - -o $BASE/am/smu_v13_0_0.py - fixup $BASE/am/smu_v13_0_0.py - - clang2py -k cdefstum \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h \ - $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h \ - extra/amdpci/headers/amdgpu_smu.h \ - --clang-args="-include stdint.h" \ - -o $BASE/am/smu_v14_0_2.py - fixup $BASE/am/smu_v14_0_2.py -} - -generate_sqtt() { - clang2py -k cdefstum \ - extra/sqtt/sqtt.h \ - -o $BASE/sqtt.py - fixup $BASE/sqtt.py - sed -i "s\import ctypes\import ctypes, os\g" $BASE/sqtt.py - python3 -c "import tinygrad.runtime.autogen.sqtt" - - ROCPROF_COMMIT_HASH=dd0485100971522cc4cd8ae136bdda431061a04d - ROCPROF_SRC=/tmp/rocprof-trace-decoder-$ROCPROF_COMMIT_HASH - if [ ! -d "$ROCPROF_SRC" ]; then - git clone https://github.com/ROCm/rocprof-trace-decoder $ROCPROF_SRC - pushd . - cd $ROCPROF_SRC - git reset --hard $ROCPROF_COMMIT_HASH - popd - fi - - clang2py -k cdefstum \ - $ROCPROF_SRC/include/rocprof_trace_decoder.h \ - $ROCPROF_SRC/include/trace_decoder_instrument.h \ - $ROCPROF_SRC/include/trace_decoder_types.h \ - -o $BASE/rocprof.py - fixup $BASE/rocprof.py - sed -i '1s/^/# pylint: skip-file\n/' $BASE/rocprof.py - sed -i "s/import ctypes/import ctypes, ctypes.util/g" $BASE/rocprof.py - patch_dlopen $BASE/rocprof.py rocprof-trace-decoder "'/usr/local/lib/librocprof-trace-decoder.so'" "'/usr/local/lib/librocprof-trace-decoder.dylib'" - sed -i "s/def _try_dlopen_rocprof-trace-decoder():/def _try_dlopen_rocprof_trace_decoder():/g" $BASE/rocprof.py - sed -i "s|FunctionFactoryStub()|_try_dlopen_rocprof_trace_decoder()|g" $BASE/rocprof.py -} - -generate_webgpu() { - clang2py extra/webgpu/webgpu.h -o $BASE/webgpu.py - fixup $BASE/webgpu.py - sed -i "s/FIXME_STUB/webgpu/g" "$BASE/webgpu.py" - sed -i "s/FunctionFactoryStub()/ctypes.CDLL(webgpu_support.WEBGPU_PATH)/g" "$BASE/webgpu.py" - sed -i "s/import ctypes/import ctypes, tinygrad.runtime.support.webgpu as webgpu_support/g" "$BASE/webgpu.py" - python3 -c "import tinygrad.runtime.autogen.webgpu" -} - -generate_libusb() { - clang2py -k cdefstum \ - /usr/include/libusb-1.0/libusb.h \ - -o $BASE/libusb.py - - fixup $BASE/libusb.py - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/libusb.py - sed -i "s/FIXME_STUB/libusb/g" "$BASE/libusb.py" - sed -i "s/libusb_le16_to_cpu = libusb_cpu_to_le16//g" "$BASE/libusb.py" - sed -i "s/FunctionFactoryStub()/None if (lib_path:=os.getenv('LIBUSB_PATH', ctypes.util.find_library('usb-1.0'))) is None else ctypes.CDLL(lib_path)/g" "$BASE/libusb.py" - python3 -c "import tinygrad.runtime.autogen.libusb" -} - -generate_mesa() { - MESA_TAG="mesa-25.2.4" - MESA_SRC=/tmp/mesa-$MESA_TAG - TINYMESA_TAG=tinymesa-32dc66c - TINYMESA_DIR=/tmp/tinymesa-$MESA_TAG-$TINYMESA_TAG/ - TINYMESA_SO=$TINYMESA_DIR/libtinymesa_cpu.so - if [ ! -d "$MESA_SRC" ]; then - git clone --depth 1 --branch $MESA_TAG https://gitlab.freedesktop.org/mesa/mesa.git $MESA_SRC - pushd . - cd $MESA_SRC - git reset --hard $MESA_COMMIT_HASH - # clang 14 doesn't support packed enums - sed -i "s/enum \w\+ \(\w\+\);$/uint8_t \1;/" $MESA_SRC/src/nouveau/headers/nv_device_info.h - sed -i "s/enum \w\+ \(\w\+\);$/uint8_t \1;/" $MESA_SRC/src/nouveau/compiler/nak.h - sed -i "s/nir_instr_type \(\w\+\);/uint8_t \1;/" $MESA_SRC/src/compiler/nir/nir.h - mkdir -p gen/util/format - python3 src/util/format/u_format_table.py src/util/format/u_format.yaml --enums > gen/util/format/u_format_gen.h - python3 src/compiler/nir/nir_opcodes_h.py > gen/nir_opcodes.h - python3 src/compiler/nir/nir_intrinsics_h.py --outdir gen - python3 src/compiler/nir/nir_intrinsics_indices_h.py --outdir gen - python3 src/compiler/nir/nir_builder_opcodes_h.py > gen/nir_builder_opcodes.h - python3 src/compiler/nir/nir_intrinsics_h.py --outdir gen - python3 src/compiler/builtin_types_h.py gen/builtin_types.h - popd - fi - - if [ ! -d "$TINYMESA_DIR" ]; then - mkdir $TINYMESA_DIR - curl -L https://github.com/sirhcm/tinymesa/releases/download/$TINYMESA_TAG/libtinymesa_cpu-$MESA_TAG-linux-amd64.so -o $TINYMESA_SO - fi - - clang2py -k cdefstu \ - $MESA_SRC/src/compiler/nir/nir.h \ - $MESA_SRC/src/compiler/nir/nir_builder.h \ - $MESA_SRC/src/compiler/nir/nir_shader_compiler_options.h \ - $MESA_SRC/src/compiler/nir/nir_serialize.h \ - $MESA_SRC/gen/nir_intrinsics.h \ - $MESA_SRC/src/nouveau/headers/nv_device_info.h \ - $MESA_SRC/src/nouveau/compiler/nak.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_passmgr.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_misc.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_type.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_init.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_nir.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_struct.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_jit_types.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_flow.h \ - $MESA_SRC/src/gallium/auxiliary/gallivm/lp_bld_const.h \ - $MESA_SRC/src/compiler/glsl_types.h \ - $MESA_SRC/src/util/blob.h \ - $MESA_SRC/src/util/ralloc.h \ - --clang-args="-DHAVE_ENDIAN_H -DHAVE_STRUCT_TIMESPEC -DHAVE_PTHREAD -I$MESA_SRC/src -I$MESA_SRC/include -I$MESA_SRC/gen -I$MESA_SRC/src/compiler/nir -I$MESA_SRC/src/gallium/auxiliary -I$MESA_SRC/src/gallium/include -I$(llvm-config-20 --includedir)" \ - -l $TINYMESA_SO \ - -o $BASE/mesa.py - - LVP_NIR_OPTIONS=$(./extra/mesa/lvp_nir_options.sh $MESA_SRC) - - fixup $BASE/mesa.py - patch_dlopen $BASE/mesa.py tinymesa_cpu "(BASE:=os.getenv('MESA_PATH', f\"/usr{'/local/' if helpers.OSX else '/'}lib\"))+'/libtinymesa_cpu'+(EXT:='.dylib' if helpers.OSX else '.so')" "f'{BASE}/libtinymesa{EXT}'" "'/opt/homebrew/lib/libtinymesa_cpu.dylib'" "'/opt/homebrew/lib/libtinymesa.dylib'" - echo "lvp_nir_options = gzip.decompress(base64.b64decode('$LVP_NIR_OPTIONS'))" >> $BASE/mesa.py - sed -i "/in_dll/s/.*/try: &\nexcept (AttributeError, ValueError): pass/" $BASE/mesa.py - sed -i "s/import ctypes/import ctypes, ctypes.util, os, gzip, base64, subprocess, tinygrad.helpers as helpers/" $BASE/mesa.py - sed -i "s/ctypes.CDLL('.\+')/(dll := _try_dlopen_tinymesa_cpu())/" $BASE/mesa.py - echo "def __getattr__(nm): raise AttributeError('LLVMpipe requires tinymesa_cpu' if 'tinymesa_cpu' not in dll._name else f'attribute {nm} not found') if dll else FileNotFoundError(f'libtinymesa not found (MESA_PATH={BASE}). See https://github.com/sirhcm/tinymesa ($TINYMESA_TAG, $MESA_TAG)')" >> $BASE/mesa.py - sed -i "s/ctypes.glsl_base_type/glsl_base_type/" $BASE/mesa.py - # bitfield bug in clang2py - sed -i "s/('fp_fast_math', ctypes.c_bool, 9)/('fp_fast_math', ctypes.c_uint32, 9)/" $BASE/mesa.py - sed -i "s/('\(\w\+\)', pipe_shader_type, 8)/('\1', ctypes.c_ubyte)/" $BASE/mesa.py - sed -i "s/\([0-9]\+\)()/\1/" $BASE/mesa.py - sed -i '/struct_nir_builder._pack_ = 1 # source:False/d' "$BASE/mesa.py" - python3 -c "import tinygrad.runtime.autogen.mesa" -} - -if [ "$1" == "opencl" ]; then generate_opencl -elif [ "$1" == "hip" ]; then generate_hip -elif [ "$1" == "comgr" ]; then generate_comgr -elif [ "$1" == "cuda" ]; then generate_cuda -elif [ "$1" == "nvrtc" ]; then generate_nvrtc -elif [ "$1" == "hsa" ]; then generate_hsa -elif [ "$1" == "kfd" ]; then generate_kfd -elif [ "$1" == "nv" ]; then generate_nv -elif [ "$1" == "amd" ]; then generate_amd -elif [ "$1" == "am" ]; then generate_am -elif [ "$1" == "sqtt" ]; then generate_sqtt -elif [ "$1" == "qcom" ]; then generate_qcom -elif [ "$1" == "io_uring" ]; then generate_io_uring -elif [ "$1" == "ib" ]; then generate_ib -elif [ "$1" == "llvm" ]; then generate_llvm -elif [ "$1" == "kgsl" ]; then generate_kgsl -elif [ "$1" == "adreno" ]; then generate_adreno -elif [ "$1" == "pci" ]; then generate_pci -elif [ "$1" == "vfio" ]; then generate_vfio -elif [ "$1" == "webgpu" ]; then generate_webgpu -elif [ "$1" == "libusb" ]; then generate_libusb -elif [ "$1" == "mesa" ]; then generate_mesa -elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_am; generate_webgpu; generate_mesa -else echo "usage: $0 " -fi diff --git a/extra/mesa/lvp_nir_options.sh b/extra/mesa/lvp_nir_options.sh index 9634728a3c..aa1b45dc7c 100755 --- a/extra/mesa/lvp_nir_options.sh +++ b/extra/mesa/lvp_nir_options.sh @@ -19,5 +19,6 @@ trap 'rm -f "$TMP"' EXIT EOF sed -n '/struct nir_shader_compiler_options/,/^}/{p;/^}/q}' $1/src/gallium/drivers/llvmpipe/lp_screen.c echo "int main(void) { write(1, &gallivm_nir_options, sizeof(gallivm_nir_options)); }" -) | cc -x c -o $TMP - -I$1/src/compiler/nir -I$1/src -I$1/include && $TMP | gzip | base64 -w0 +) | cc -x c -o $TMP - -I$1/src/compiler/nir -I$1/src -I$1/include || exit 1 +printf 'lvp_nir_options = gzip.decompress(base64.b64decode("%s"))' $("$TMP" | gzip | base64 -w0) diff --git a/extra/nvJitLink.h b/extra/nvJitLink.h new file mode 100644 index 0000000000..7513eaa8cf --- /dev/null +++ b/extra/nvJitLink.h @@ -0,0 +1,53 @@ +/* + * NVIDIA_COPYRIGHT_BEGIN + * + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * NVIDIA CORPORATION and its licensors retain all intellectual property + * and proprietary rights in and to this software, related documentation + * and any modifications thereto. Any use, reproduction, disclosure or + * distribution of this software and related documentation without an express + * license agreement from NVIDIA CORPORATION is strictly prohibited. + * + * NVIDIA_COPYRIGHT_END + */ + +#include +#include + +typedef enum { + NVJITLINK_SUCCESS = 0, + NVJITLINK_ERROR_UNRECOGNIZED_OPTION, + NVJITLINK_ERROR_MISSING_ARCH, + NVJITLINK_ERROR_INVALID_INPUT, + NVJITLINK_ERROR_PTX_COMPILE, + NVJITLINK_ERROR_NVVM_COMPILE, + NVJITLINK_ERROR_INTERNAL +} nvJitLinkResult; + +typedef enum { + NVJITLINK_INPUT_NONE = 0, + NVJITLINK_INPUT_CUBIN = 1, + NVJITLINK_INPUT_PTX, + NVJITLINK_INPUT_LTOIR, + NVJITLINK_INPUT_FATBIN, + NVJITLINK_INPUT_OBJECT, + NVJITLINK_INPUT_LIBRARY +} nvJitLinkInputType; + +typedef struct nvJitLink* nvJitLinkHandle; + +nvJitLinkResult nvJitLinkCreate(nvJitLinkHandle *handle, uint32_t numOptions, const char **options); +nvJitLinkResult nvJitLinkDestroy(nvJitLinkHandle *handle); +nvJitLinkResult nvJitLinkAddData(nvJitLinkHandle handle, nvJitLinkInputType inputType, const void *data, size_t size, const char *name); +nvJitLinkResult nvJitLinkAddFile(nvJitLinkHandle handle, nvJitLinkInputType inputType, const char *fileName); +nvJitLinkResult nvJitLinkComplete(nvJitLinkHandle handle); +nvJitLinkResult nvJitLinkGetLinkedCubinSize(nvJitLinkHandle handle, size_t *size); +nvJitLinkResult nvJitLinkGetLinkedCubin(nvJitLinkHandle handle, void *cubin); +nvJitLinkResult nvJitLinkGetLinkedPtxSize(nvJitLinkHandle handle, size_t *size); +nvJitLinkResult nvJitLinkGetLinkedPtx(nvJitLinkHandle handle, char *ptx); +nvJitLinkResult nvJitLinkGetErrorLogSize(nvJitLinkHandle handle, size_t *size); +nvJitLinkResult nvJitLinkGetErrorLog(nvJitLinkHandle handle, char *log); +nvJitLinkResult nvJitLinkGetInfoLogSize(nvJitLinkHandle handle, size_t *size); +nvJitLinkResult nvJitLinkGetInfoLog(nvJitLinkHandle handle, char *log); +nvJitLinkResult nvJitLinkVersion(unsigned int *major, unsigned int *minor); diff --git a/extra/nv_gpu_driver/clcec0qmd.h b/extra/nv_gpu_driver/clcec0qmd.h index 4ee8a129c8..d3c985434f 100644 --- a/extra/nv_gpu_driver/clcec0qmd.h +++ b/extra/nv_gpu_driver/clcec0qmd.h @@ -65,6 +65,8 @@ #define NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME MW(271:256) #define NVCEC0_QMDV05_00_GRID_DEPTH_RESUME MW(287:272) #define NVCEC0_QMDV05_00_RELEASE_ENABLE(i) MW((288+(i)*16):(288+(i)*16)) +#define NVCEC0_QMDV05_00_RELEASE0_ENABLE NVCEC0_QMDV05_00_RELEASE_ENABLE(0) +#define NVCEC0_QMDV05_00_RELEASE1_ENABLE NVCEC0_QMDV05_00_RELEASE_ENABLE(1) #define NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE 0x00000000 #define NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE 0x00000001 #define NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE(i) MW((290+(i)*16):(289+(i)*16)) diff --git a/extra/nv_gpu_driver/nv_ioctl.py b/extra/nv_gpu_driver/nv_ioctl.py index 44a2a11f3e..3721693584 100644 --- a/extra/nv_gpu_driver/nv_ioctl.py +++ b/extra/nv_gpu_driver/nv_ioctl.py @@ -58,7 +58,7 @@ def install_hook(c_function, python_function): return orig_func # *** ioctl lib end *** -import tinygrad.runtime.autogen.nv_gpu as nv_gpu +from tinygrad.runtime.autogen import nv_gpu nvescs = {getattr(nv_gpu, x):x for x in dir(nv_gpu) if x.startswith("NV_ESC")} nvcmds = {getattr(nv_gpu, x):(x, getattr(nv_gpu, "struct_"+x+"_PARAMS", getattr(nv_gpu, "struct_"+x.replace("_CMD_", "_")+"_PARAMS", None))) for x in dir(nv_gpu) if \ x.startswith("NV") and x[6:].startswith("_CTRL_") and isinstance(getattr(nv_gpu, x), int)} @@ -272,4 +272,4 @@ def compare_launch_state(states, good_states): return True, "PASS" -# IOCTL=1 CUDA=1 CUDA_PTX=1 python3 test/test_ops.py TestOps.test_tiny_add \ No newline at end of file +# IOCTL=1 CUDA=1 CUDA_PTX=1 python3 test/test_ops.py TestOps.test_tiny_add diff --git a/extra/sqtt/rgptool.py b/extra/sqtt/rgptool.py index 4148a2ccc5..286a06e5d2 100755 --- a/extra/sqtt/rgptool.py +++ b/extra/sqtt/rgptool.py @@ -185,9 +185,7 @@ class RGP: magic_number=sqtt.SQTT_FILE_MAGIC_NUMBER, version_major=sqtt.SQTT_FILE_VERSION_MAJOR, version_minor=sqtt.SQTT_FILE_VERSION_MINOR, - flags=sqtt.struct_sqtt_file_header_flags( - _0=sqtt.union_sqtt_file_header_flags_0(value=1), - ), + flags=sqtt.struct_sqtt_file_header_flags(value=1,), chunk_offset=ctypes.sizeof(sqtt.struct_sqtt_file_header), ) chunks = [ @@ -265,7 +263,7 @@ class RGP: profiling_mode=sqtt.SQTT_PROFILING_MODE_PRESENT, instruction_trace_mode=sqtt.SQTT_INSTRUCTION_TRACE_FULL_FRAME if sqtt_itrace_enabled else sqtt.SQTT_INSTRUCTION_TRACE_DISABLED, instruction_trace_data=sqtt.union_sqtt_instruction_trace_data( - shader_engine_filter=sqtt.struct_sqtt_instruction_trace_data_shader_engine_filter(mask=sqtt_itrace_se_mask), + shader_engine_filter=sqtt.union_sqtt_instruction_trace_data_shader_engine_filter(mask=sqtt_itrace_se_mask), ), )), *flatten([( @@ -276,13 +274,11 @@ class RGP: ), shader_engine_index=sqtt_event.se, sqtt_version={11: sqtt.SQTT_VERSION_3_2, 12: sqtt.SQTT_VERSION_3_3}.get(gfx_ver), - _0=sqtt.union_sqtt_file_chunk_sqtt_desc_0( - v1=sqtt.struct_sqtt_file_chunk_sqtt_desc_0_v1( - instrumentation_spec_version=1, - instrumentation_api_version=0, - compute_unit_index=0, - ) - ), + v1=sqtt.struct_sqtt_file_chunk_sqtt_desc_0_v1( + instrumentation_spec_version=1, + instrumentation_api_version=0, + compute_unit_index=0, + ) )), RGPChunk(sqtt.struct_sqtt_file_chunk_sqtt_data( header=sqtt.struct_sqtt_file_chunk_header( diff --git a/pyproject.toml b/pyproject.toml index 4f4d0f8841..e60a294565 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -30,7 +30,6 @@ packages = [ 'tinygrad.runtime', 'tinygrad.runtime.autogen', 'tinygrad.runtime.autogen.am', - 'tinygrad.runtime.autogen.nv', 'tinygrad.runtime.graph', 'tinygrad.runtime.support', 'tinygrad.runtime.support.am', @@ -162,7 +161,6 @@ exclude = [ ".git/", "docs/", "extra/", - "tinygrad/runtime/autogen", "test/external/mlperf_resnet", "test/external/mlperf_unet3d", ] @@ -228,6 +226,7 @@ select = [ "F541", "F841", ] +"tinygrad/runtime/autogen/**/*.py" = ["E501", "F401", "E722", "E731", "F821", "A006"] [tool.ruff.format] exclude = ["*"] diff --git a/test/mockgpu/amd/amdgpu.py b/test/mockgpu/amd/amdgpu.py index b30a9db4b3..afa8b4d44b 100644 --- a/test/mockgpu/amd/amdgpu.py +++ b/test/mockgpu/amd/amdgpu.py @@ -33,7 +33,7 @@ remu = _try_dlopen_remu() def create_sdma_packets(): # TODO: clean up this, if we want to keep it structs = {} - for name,pkt in [(name,s) for name,s in amd_gpu.__dict__.items() if name.startswith("struct_SDMA_PKT_") and name.endswith("_TAG")]: + for name,pkt in [(name,s) for name,s in amd_gpu.__dict__.items() if name.startswith("rocr_AMD_SDMA_PKT_") and name.endswith("_TAG")]: names = set() fields = [] for pkt_fields in pkt._fields_: @@ -47,7 +47,7 @@ def create_sdma_packets(): # merge together 64-bit fields, otherwise just append them if fname.endswith("_63_32") and fields[-1][0].endswith("_31_0"): fields[-1] = tuple([fname[:-6], ctypes.c_ulong, 64]) else: fields.append(tuple([fname, *union_fields[1:]])) - new_name = name[16:-4].lower() + new_name = name[18:-4].lower() structs[new_name] = init_c_struct_t(tuple(fields)) assert ctypes.sizeof(structs[new_name]) == ctypes.sizeof(pkt), f"{ctypes.sizeof(structs[new_name])} != {ctypes.sizeof(pkt)}" return type("SDMA_PKTS", (object, ), structs) diff --git a/test/mockgpu/cuda/cuda.py b/test/mockgpu/cuda/cuda.py index daf8db6f94..6fd7498184 100644 --- a/test/mockgpu/cuda/cuda.py +++ b/test/mockgpu/cuda/cuda.py @@ -164,7 +164,7 @@ def cuStreamWaitEvent(stream: Any, event, flags: int) -> int: return orig_cuda.C def cuCtxSynchronize() -> int: return orig_cuda.CUDA_SUCCESS def cuGetErrorString(error: int, pStr) -> int: - error_str = orig_cuda.cudaError_enum__enumvalues.get(error, "Unknown CUDA error").encode() + error_str = orig_cuda.enum_cudaError_enum.get(error, "Unknown CUDA error").encode() buf = ctypes.create_string_buffer(error_str) # Set the pointer to point to our error string buffer pStr._obj.value = ctypes.cast(buf, ctypes.POINTER(ctypes.c_char)) diff --git a/test/mockgpu/nv/nvdriver.py b/test/mockgpu/nv/nvdriver.py index d7c330c600..f0f9be6540 100644 --- a/test/mockgpu/nv/nvdriver.py +++ b/test/mockgpu/nv/nvdriver.py @@ -1,5 +1,5 @@ import ctypes, mmap, collections, functools, os -import tinygrad.runtime.autogen.nv_gpu as nv_gpu +from tinygrad.runtime.autogen import nv_gpu from typing import Any from tinygrad.helpers import to_mv from test.mockgpu.driver import VirtDriver, VirtFileDesc, VirtFile @@ -254,4 +254,4 @@ class NVDriver(VirtDriver): for gpu in self.gpus.values(): for q in gpu.queues: if q.ctrl.GPGet != q.ctrl.GPPut: - any_progress |= q.execute() \ No newline at end of file + any_progress |= q.execute() diff --git a/test/mockgpu/nv/nvgpu.py b/test/mockgpu/nv/nvgpu.py index 6be5f00447..14c396bd18 100644 --- a/test/mockgpu/nv/nvgpu.py +++ b/test/mockgpu/nv/nvgpu.py @@ -1,5 +1,5 @@ import ctypes, time -import tinygrad.runtime.autogen.nv_gpu as nv_gpu +from tinygrad.runtime.autogen import nv_gpu from enum import Enum, auto from test.mockgpu.gpu import VirtGPU from test.mockgpu.helpers import _try_dlopen_gpuocelot diff --git a/tinygrad/helpers.py b/tinygrad/helpers.py index a780be1ccd..92e3add091 100644 --- a/tinygrad/helpers.py +++ b/tinygrad/helpers.py @@ -416,6 +416,7 @@ def to_mv(ptr:int, sz:int) -> memoryview: return memoryview((ctypes.c_uint8 * sz def mv_address(mv): return ctypes.addressof(ctypes.c_char.from_buffer(mv)) def to_char_p_p(options: list[bytes], to_type=ctypes.c_char): return (ctypes.POINTER(to_type) * len(options))(*[ctypes.cast(ctypes.create_string_buffer(o), ctypes.POINTER(to_type)) for o in options]) +def charptr(s:str|bytes): return ctypes.cast(ctypes.c_char_p(s if isinstance(s, bytes) else s.encode()), ctypes.POINTER(ctypes.c_char)) @functools.cache def init_c_struct_t(fields: tuple[tuple[str, type[ctypes._SimpleCData]], ...]): class CStruct(ctypes.Structure): diff --git a/tinygrad/renderer/nir.py b/tinygrad/renderer/nir.py index 8fcba798a5..527937a095 100644 --- a/tinygrad/renderer/nir.py +++ b/tinygrad/renderer/nir.py @@ -1,10 +1,10 @@ from typing import Callable, cast, Any from tinygrad.dtype import AddrSpace, DType, PtrDType, dtypes -from tinygrad.helpers import DEBUG, OSX, unwrap +from tinygrad.helpers import DEBUG, OSX, unwrap, charptr from tinygrad.renderer import Renderer from tinygrad.renderer.cstyle import CUDARenderer from tinygrad.uop.ops import GroupOp, Ops, UOp, PatternMatcher, UPat, range_str -import tinygrad.runtime.autogen.mesa as mesa +from tinygrad.runtime.autogen import mesa import base64, ctypes, ctypes.util, struct, functools, inspect def g(s:str): return getattr(mesa, s) @@ -51,7 +51,7 @@ def nir_instr(nc=1, bs=lambda: None, intrins=None, srcs=None, has_def=True, df=N instr = f(*args, **kwargs) if has_def: mesa.nir_def_init(instr.contents.instr, getattr(instr.contents, "def"), go(nc), go(bs)) for k, v in go(intrins or {}).items(): - idx = mesa.nir_intrinsic_infos[instr.contents.intrinsic].index_map[g(f"NIR_INTRINSIC_{k}")] + idx = mesa.nir_intrinsic_infos[instr.contents.intrinsic.value].index_map[g(f"NIR_INTRINSIC_{k}")] assert idx > 0 instr.contents.const_index[idx - 1] = go(v) for i, src in enumerate(go(srcs or [])): ctypes.cast(instr.contents.src, ctypes.POINTER(mesa.nir_src))[i] = go(src) @@ -177,7 +177,7 @@ class NIRRenderer(Renderer): elif u.op is Ops.AFTER: self.r[u] = self.r[u.src[0]] elif u.op == Ops.SINK: - if u.arg is not None: self.b.shader.contents.info.name = mesa.char_pointer_cast(u.arg.function_name) + if u.arg is not None: self.b.shader.contents.info.name = charptr(u.arg.function_name.encode()) elif u.op == Ops.DEFINE_LOCAL: self.r[u] = nimm(self.b, self.b.shader.contents.info.shared_size, dtypes.long) self.b.shader.contents.info.shared_size += u.dtype.nbytes() diff --git a/tinygrad/runtime/autogen/__init__.py b/tinygrad/runtime/autogen/__init__.py index 2e042bc387..b6c574b6bb 100644 --- a/tinygrad/runtime/autogen/__init__.py +++ b/tinygrad/runtime/autogen/__init__.py @@ -1,11 +1,22 @@ -import importlib, pathlib -from tinygrad.helpers import system +import glob, importlib, pathlib, subprocess, tarfile +from tinygrad.helpers import fetch, flatten, system root = (here:=pathlib.Path(__file__).parent).parents[2] +nv_src = "https://github.com/NVIDIA/open-gpu-kernel-modules/archive/81fe4fb417c8ac3b9bdcc1d56827d116743892a5.tar.gz" def load(name, dll, files, **kwargs): if not (f:=(root/(path:=kwargs.pop("path", __name__)).replace('.','/')/f"{name}.py")).exists(): - files = files() if callable(files) else files + files, kwargs['args'] = files() if callable(files) else files, args() if callable(args:=kwargs.get('args', [])) else args + if (tarball:=kwargs.pop('tarball', None)): + # dangerous for arbitrary urls! + with tarfile.open(fetch(tarball, gunzip=tarball.endswith("gz"))) as tf: + tf.extractall("/tmp") + base = f"/tmp/{tf.getnames()[0]}" + files, kwargs['args'] = [str(f).format(base) for f in files], [a.format(base) for a in kwargs.get('args', [])] + kwargs['anon_names'] = {k.format(base):v for k,v in kwargs.get('anon_names', {}).items()} + if (preprocess:=kwargs.pop('preprocess', None)): preprocess(base) + files = flatten(sorted(glob.glob(p, recursive=True)) if isinstance(p, str) and '*' in p else [p] for p in files) + kwargs['epilog'] = (epi(base) if tarball else epi()) if callable(epi:=kwargs.get('epilog', [])) else epi f.write_text(importlib.import_module("tinygrad.runtime.support.autogen").gen(dll, files, **kwargs)) return importlib.import_module(f"{path}.{name.replace('/', '.')}") @@ -14,4 +25,100 @@ def __getattr__(nm): case "libc": return load("libc", ["find_library('c')"], lambda: ( [i for i in system("dpkg -L libc6-dev").split() if 'sys/mman.h' in i or 'sys/syscall.h' in i] + ["/usr/include/string.h", "/usr/include/elf.h", "/usr/include/unistd.h", "/usr/include/asm-generic/mman-common.h"]), use_errno=True) + case "opencl": return load("opencl", ["find_library('OpenCL')"], ["/usr/include/CL/cl.h"]) + case "cuda": return load("cuda", ["find_library('cuda')"], ["/usr/include/cuda.h"], args=["-D__CUDA_API_VERSION_INTERNAL"], parse_macros=False) + case "nvrtc": return load("nvrtc", ["find_library('nvrtc')"], ["/usr/include/nvrtc.h"]) + case "nvjitlink": load("nvjitlink", ["find_library('nvJitLink')"], [root/"extra/nvJitLink.h"]) + case "kfd": return load("kfd", [], ["/usr/include/linux/kfd_ioctl.h"]) + case "nv_gpu": + return load("nv_gpu", [], [ + *[root/"extra/nv_gpu_driver"/s for s in ["clc6c0qmd.h","clcec0qmd.h"]], "{}/kernel-open/common/inc/nvmisc.h", + *[f"{{}}/src/common/sdk/nvidia/inc/class/cl{s}.h" for s in ["0000", "0080", "2080", "2080_notification", "c56f", "c86f", "c96f", "c761", + "83de", "c6c0", "cdc0"]], + *[f"{{}}/kernel-open/nvidia-uvm/{s}.h" for s in ["clc6b5", "clc9b5", "uvm_ioctl", "uvm_linux_ioctl", "hwref/ampere/ga100/dev_fault"]], + *[f"{{}}/src/nvidia/arch/nvalloc/unix/include/nv{s}.h" for s in ["_escape", "-ioctl", "-ioctl-numbers", + "-ioctl-numa", "-unix-nvos-params-wrappers"]], + *[f"{{}}/src/common/sdk/nvidia/inc/{s}.h" for s in ["alloc/alloc_channel", "nvos", "ctrl/ctrlc36f", "ctrl/ctrlcb33", + "ctrl/ctrla06c", "ctrl/ctrl90f1"]], + *[f"{{}}/src/common/sdk/nvidia/inc/ctrl/ctrl{s}/*.h" for s in ["0000", "0080", "2080", "83de"]], + "{}/kernel-open/common/inc/nvstatus.h", "{}/src/nvidia/generated/g_allclasses.h" + ], args=[ + "-include", "{}/src/common/sdk/nvidia/inc/nvtypes.h", "-I{}/src/common/inc", "-I{}/kernel-open/nvidia-uvm", "-I{}/kernel-open/common/inc", + "-I{}/src/common/sdk/nvidia/inc", "-I{}/src/nvidia/arch/nvalloc/unix/include", "-I{}/src/common/sdk/nvidia/inc/ctrl" + ], rules=[(r'MW\(([^:]+):(.+)\)',r'(\1, \2)')], tarball=nv_src, anon_names={"{}/kernel-open/common/inc/nvstatus.h:37":"nv_status_codes"}) + case "nv": return load("nv", [], [ + *[f"{{}}/src/nvidia/inc/kernel/gpu/{s}.h" for s in ["fsp/kern_fsp_cot_payload", "gsp/gsp_init_args"]], + *[f"{{}}/src/nvidia/arch/nvalloc/common/inc/{s}.h" for s in ["gsp/gspifpub", "gsp/gsp_fw_wpr_meta", "gsp/gsp_fw_sr_meta", "rmRiscvUcode", + "fsp/fsp_nvdm_format"]], + *[f"{{}}/src/nvidia/inc/kernel/vgpu/{s}.h" for s in ["rpc_headers", "rpc_global_enums"]], + "{}/src/common/uproc/os/common/include/libos_init_args.h", "{}/src/common/shared/msgq/inc/msgq/msgq_priv.h", + "{}/src/nvidia/generated/g_rpc-structures.h", root/"extra/nv_gpu_driver/g_rpc-message-header.h", root/"extra/nv_gpu_driver/gsp_static_config.h", + root/"extra/nv_gpu_driver/vbios.h", root/"extra/nv_gpu_driver/pci_exp_table.h" + ], args=[ + "-DRPC_MESSAGE_STRUCTURES", "-DRPC_STRUCTURES", "-include", "{}/src/common/sdk/nvidia/inc/nvtypes.h", "-I{}/src/nvidia/generated", + "-I{}/src/common/inc", "-I{}/src/nvidia/inc", "-I{}/src/nvidia/interface/", "-I{}/src/nvidia/inc/kernel", "-I{}/src/nvidia/inc/libraries", + "-I{}/src/nvidia/arch/nvalloc/common/inc", "-I{}/kernel-open/nvidia-uvm", "-I{}/kernel-open/common/inc", "-I{}/src/common/sdk/nvidia/inc", + "-I{}/src/nvidia/arch/nvalloc/unix/include", "-I{}/src/common/sdk/nvidia/inc/ctrl" + ], tarball=nv_src, anon_names={ + "{}/src/nvidia/inc/kernel/vgpu/rpc_global_enums.h:8": "rpc_fns", + "{}/src/nvidia/inc/kernel/vgpu/rpc_global_enums.h:244": "rpc_events" + }) + # this defines all syscall numbers. should probably unify linux autogen? + case "io_uring": return load("io_uring", [], ["/usr/include/liburing.h", "/usr/include/linux/io_uring.h", "/usr/include/asm-generic/unistd.h"], + rules=[('__NR', 'NR')]) + case "ib": return load("ib", ["ibverbs"], ["/usr/include/infiniband/verbs.h", "/usr/include/infiniband/verbs_api.h", + "/usr/include/infiniband/ib_user_ioctl_verbs.h","/usr/include/rdma/ib_user_verbs.h"], use_errno=True) + case "llvm": return load("llvm", ["LLVM_PATH"], lambda: [system("llvm-config-20 --includedir")+"/llvm-c/**/*.h"], + args=lambda: system("llvm-config-20 --cflags").split(), recsym=True, + prolog=["from tinygrad.runtime.support.llvm import LLVM_PATH"]) + case "pci": return load("pci", [], ["/usr/include/linux/pci_regs.h"]) + case "vfio": return load("vfio", [], ["/usr/include/linux/vfio.h"]) + # could add rule: WGPU_COMMA -> ',' + case "webgpu": + return load("webgpu", ["WEBGPU_PATH"], [root/"extra/webgpu/webgpu.h"], prolog=["from tinygrad.runtime.support.webgpu import WEBGPU_PATH"]) + case "libusb": return load("libusb", ["os.getenv('LIBUSB_PATH', find_library('usb-1.0'))"], ["/usr/include/libusb-1.0/libusb.h"]) + case "hip": return load("hip", ["os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libamdhip64.so'"], ["/opt/rocm/include/hip/hip_ext.h", + "/opt/rocm/include/hip/hiprtc.h", "/opt/rocm/include/hip/hip_runtime_api.h", "/opt/rocm/include/hip/driver_types.h"], + args=["-D__HIP_PLATFORM_AMD__", "-I/opt/rocm/include", "-x", "c++"]) + case "comgr" | "comgr_3": + try: use_3 = nm == "comgr_3" or int(system("dpkg-query -f '${version}' -W comgr")[1]) >= 3 + except FileNotFoundError: use_3 = nm == "comgr_3" + return load("comgr_3" if use_3 else "comgr", [ + "os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libamd_comgr.so'", "'/usr/local/lib/libamd_comgr.dylib'", "'/opt/homebrew/lib/libamd_comgr.dylib'" + ], ["/opt/rocm/include/amd_comgr/amd_comgr.h"], args=["-D__HIP_PLATFORM_AMD__", "-I/opt/rocm/include", "-x", "c++"]) + case "hsa": return load("hsa", ["os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libhsa-runtime64.so'", "find_library('hsa-runtime64')"], [ + f"/opt/rocm/include/hsa/{s}.h" for s in ["hsa", "hsa_ext_amd", "amd_hsa_signal", "amd_hsa_queue", "amd_hsa_kernel_code", "hsa_ext_finalize", + "hsa_ext_image", "hsa_ven_amd_aqlprofile"] ], args=["-I/opt/rocm/include"]) + case "amd_gpu": return load("amd_gpu", [], [root/f"extra/hip_gpu_driver/{s}.h" for s in ["sdma_registers", "nvd", "gc_11_0_0_offset", + "sienna_cichlid_ip_offset"]], + args=["-I/opt/rocm/include", "-x", "c++"]) + case "kgsl": return load("kgsl", [], [root/"extra/qcom_gpu_driver/msm_kgsl.h"], args=["-D__user="]) + case "adreno": return load("adreno", [], [root/"extra/qcom_gpu_driver/a6xx.xml.h"]) + case "qcom_dsp": + return load("qcom_dsp", [], [root/f"extra/dsp/include/{s}.h" for s in ["ion", "msm_ion", "adsprpc_shared", "remote_default", "apps_std"]]) + case "sqtt": return load("sqtt", [], [root/"extra/sqtt/sqtt.h"]) + case "rocprof": + return load("rocprof", ["find_library('rocprof-trace-decoder')", p:="'/usr/local/lib/rocprof-trace-decoder.so'", p.replace('so','dylib')], + [f"{{}}/include/{s}.h" for s in ["rocprof_trace_decoder", "trace_decoder_instrument", "trace_decoder_types"]], + tarball="https://github.com/ROCm/rocprof-trace-decoder/archive/dd0485100971522cc4cd8ae136bdda431061a04d.tar.gz") + case "mesa": return load("mesa", ["find_library('tinymesa_cpu')", + "(BASE:=os.getenv('MESA_PATH', f\"/usr{'/local/' if OSX else '/'}lib\"))+'/libtinymesa_cpu'+(EXT:='.dylib' if OSX else '.so')", + "f'{BASE}/libtinymesa{EXT}'", "'/opt/homebrew/lib/libtinymesa_cpu.dylib'", "'/opt/homebrew/lib/libtinymesa.dylib'"], [ + *[f"{{}}/src/compiler/nir/{s}.h" for s in ["nir", "nir_builder", "nir_shader_compiler_options", "nir_serialize"]], "{}/gen/nir_intrinsics.h", + *[f"{{}}/src/nouveau/{s}.h" for s in ["headers/nv_device_info", "compiler/nak"]], + *[f"{{}}/src/gallium/auxiliary/gallivm/lp_bld{s}.h" for s in ["", "_passmgr", "_misc", "_type", "_init", "_nir", "_struct", "_jit_types", + "_flow", "_const"]], + "{}/src/compiler/glsl_types.h", "{}/src/util/blob.h", "{}/src/util/ralloc.h"], args=lambda:[ + "-DHAVE_ENDIAN_H", "-DHAVE_STRUCT_TIMESPEC", "-DHAVE_PTHREAD", "-DHAVE_FUNC_ATTRIBUTE_PACKED", "-I{}/src", "-I{}/include", "-I{}/gen", + "-I{}/src/compiler/nir", "-I{}/src/gallium/auxiliary", "-I{}/src/gallium/include", f"-I{system('llvm-config-20 --includedir')}"], + preprocess=lambda path: subprocess.run("""mkdir -p gen/util/format +python3 src/util/format/u_format_table.py src/util/format/u_format.yaml --enums > gen/util/format/u_format_gen.h +python3 src/compiler/nir/nir_opcodes_h.py > gen/nir_opcodes.h +python3 src/compiler/nir/nir_intrinsics_h.py --outdir gen +python3 src/compiler/nir/nir_intrinsics_indices_h.py --outdir gen +python3 src/compiler/nir/nir_builder_opcodes_h.py > gen/nir_builder_opcodes.h +python3 src/compiler/nir/nir_intrinsics_h.py --outdir gen +python3 src/compiler/builtin_types_h.py gen/builtin_types.h""", cwd=path, shell=True, check=True), + tarball="https://gitlab.freedesktop.org/mesa/mesa/-/archive/mesa-25.2.4/mesa-25.2.4.tar.gz", + prolog=["import gzip, base64", "from tinygrad.helpers import OSX"], epilog=lambda path: [system(f"{root}/extra/mesa/lvp_nir_options.sh {path}")]) case _: raise AttributeError(f"no such autogen: {nm}") diff --git a/tinygrad/runtime/autogen/adreno.py b/tinygrad/runtime/autogen/adreno.py index 4228e021df..f34f825c35 100644 --- a/tinygrad/runtime/autogen/adreno.py +++ b/tinygrad/runtime/autogen/adreno.py @@ -1,17904 +1,7807 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - - - -A6XX_XML = True # macro -# def __struct_cast(X): # macro -# return (structX) -REG_CP_LOAD_STATE_0 = 0x00000000 # macro -CP_LOAD_STATE_0_DST_OFF__MASK = 0x0000ffff # macro -CP_LOAD_STATE_0_DST_OFF__SHIFT = 0 # macro -CP_LOAD_STATE_0_STATE_SRC__MASK = 0x00070000 # macro -CP_LOAD_STATE_0_STATE_SRC__SHIFT = 16 # macro -CP_LOAD_STATE_0_STATE_BLOCK__MASK = 0x00380000 # macro -CP_LOAD_STATE_0_STATE_BLOCK__SHIFT = 19 # macro -CP_LOAD_STATE_0_NUM_UNIT__MASK = 0xffc00000 # macro -CP_LOAD_STATE_0_NUM_UNIT__SHIFT = 22 # macro -REG_CP_LOAD_STATE_1 = 0x00000001 # macro -CP_LOAD_STATE_1_STATE_TYPE__MASK = 0x00000003 # macro -CP_LOAD_STATE_1_STATE_TYPE__SHIFT = 0 # macro -CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro -CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT = 2 # macro -REG_CP_LOAD_STATE4_0 = 0x00000000 # macro -CP_LOAD_STATE4_0_DST_OFF__MASK = 0x00003fff # macro -CP_LOAD_STATE4_0_DST_OFF__SHIFT = 0 # macro -CP_LOAD_STATE4_0_STATE_SRC__MASK = 0x00030000 # macro -CP_LOAD_STATE4_0_STATE_SRC__SHIFT = 16 # macro -CP_LOAD_STATE4_0_STATE_BLOCK__MASK = 0x003c0000 # macro -CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT = 18 # macro -CP_LOAD_STATE4_0_NUM_UNIT__MASK = 0xffc00000 # macro -CP_LOAD_STATE4_0_NUM_UNIT__SHIFT = 22 # macro -REG_CP_LOAD_STATE4_1 = 0x00000001 # macro -CP_LOAD_STATE4_1_STATE_TYPE__MASK = 0x00000003 # macro -CP_LOAD_STATE4_1_STATE_TYPE__SHIFT = 0 # macro -CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro -CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT = 2 # macro -REG_CP_LOAD_STATE4_2 = 0x00000002 # macro -CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff # macro -CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT = 0 # macro -REG_CP_LOAD_STATE6_0 = 0x00000000 # macro -CP_LOAD_STATE6_0_DST_OFF__MASK = 0x00003fff # macro -CP_LOAD_STATE6_0_DST_OFF__SHIFT = 0 # macro -CP_LOAD_STATE6_0_STATE_TYPE__MASK = 0x0000c000 # macro -CP_LOAD_STATE6_0_STATE_TYPE__SHIFT = 14 # macro -CP_LOAD_STATE6_0_STATE_SRC__MASK = 0x00030000 # macro -CP_LOAD_STATE6_0_STATE_SRC__SHIFT = 16 # macro -CP_LOAD_STATE6_0_STATE_BLOCK__MASK = 0x003c0000 # macro -CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT = 18 # macro -CP_LOAD_STATE6_0_NUM_UNIT__MASK = 0xffc00000 # macro -CP_LOAD_STATE6_0_NUM_UNIT__SHIFT = 22 # macro -REG_CP_LOAD_STATE6_1 = 0x00000001 # macro -CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro -CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT = 2 # macro -REG_CP_LOAD_STATE6_2 = 0x00000002 # macro -CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff # macro -CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT = 0 # macro -REG_CP_LOAD_STATE6_EXT_SRC_ADDR = 0x00000001 # macro -REG_CP_DRAW_INDX_0 = 0x00000000 # macro -CP_DRAW_INDX_0_VIZ_QUERY__MASK = 0xffffffff # macro -CP_DRAW_INDX_0_VIZ_QUERY__SHIFT = 0 # macro -REG_CP_DRAW_INDX_1 = 0x00000001 # macro -CP_DRAW_INDX_1_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_INDX_1_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_INDX_1_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_INDX_1_VIS_CULL__MASK = 0x00000600 # macro -CP_DRAW_INDX_1_VIS_CULL__SHIFT = 9 # macro -CP_DRAW_INDX_1_INDEX_SIZE__MASK = 0x00000800 # macro -CP_DRAW_INDX_1_INDEX_SIZE__SHIFT = 11 # macro -CP_DRAW_INDX_1_NOT_EOP = 0x00001000 # macro -CP_DRAW_INDX_1_SMALL_INDEX = 0x00002000 # macro -CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 # macro -CP_DRAW_INDX_1_NUM_INSTANCES__MASK = 0xff000000 # macro -CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT = 24 # macro -REG_CP_DRAW_INDX_2 = 0x00000002 # macro -CP_DRAW_INDX_2_NUM_INDICES__MASK = 0xffffffff # macro -CP_DRAW_INDX_2_NUM_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_3 = 0x00000003 # macro -CP_DRAW_INDX_3_INDX_BASE__MASK = 0xffffffff # macro -CP_DRAW_INDX_3_INDX_BASE__SHIFT = 0 # macro -REG_CP_DRAW_INDX_4 = 0x00000004 # macro -CP_DRAW_INDX_4_INDX_SIZE__MASK = 0xffffffff # macro -CP_DRAW_INDX_4_INDX_SIZE__SHIFT = 0 # macro -REG_CP_DRAW_INDX_2_0 = 0x00000000 # macro -CP_DRAW_INDX_2_0_VIZ_QUERY__MASK = 0xffffffff # macro -CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT = 0 # macro -REG_CP_DRAW_INDX_2_1 = 0x00000001 # macro -CP_DRAW_INDX_2_1_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_INDX_2_1_VIS_CULL__MASK = 0x00000600 # macro -CP_DRAW_INDX_2_1_VIS_CULL__SHIFT = 9 # macro -CP_DRAW_INDX_2_1_INDEX_SIZE__MASK = 0x00000800 # macro -CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT = 11 # macro -CP_DRAW_INDX_2_1_NOT_EOP = 0x00001000 # macro -CP_DRAW_INDX_2_1_SMALL_INDEX = 0x00002000 # macro -CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 # macro -CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK = 0xff000000 # macro -CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT = 24 # macro -REG_CP_DRAW_INDX_2_2 = 0x00000002 # macro -CP_DRAW_INDX_2_2_NUM_INDICES__MASK = 0xffffffff # macro -CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_0 = 0x00000000 # macro -CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK = 0x00000300 # macro -CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT = 8 # macro -CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK = 0x00000c00 # macro -CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT = 10 # macro -CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK = 0x00003000 # macro -CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT = 12 # macro -CP_DRAW_INDX_OFFSET_0_GS_ENABLE = 0x00010000 # macro -CP_DRAW_INDX_OFFSET_0_TESS_ENABLE = 0x00020000 # macro -REG_CP_DRAW_INDX_OFFSET_1 = 0x00000001 # macro -CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_2 = 0x00000002 # macro -CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_3 = 0x00000003 # macro -CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_4 = 0x00000004 # macro -A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_5 = 0x00000005 # macro -A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE = 0x00000004 # macro -REG_A5XX_CP_DRAW_INDX_OFFSET_6 = 0x00000006 # macro -A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_4 = 0x00000004 # macro -CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT = 0 # macro -REG_CP_DRAW_INDX_OFFSET_5 = 0x00000005 # macro -CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK = 0xffffffff # macro -CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT = 0 # macro -REG_A4XX_CP_DRAW_INDIRECT_0 = 0x00000000 # macro -A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f # macro -A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT = 0 # macro -A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 # macro -A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK = 0x00000300 # macro -A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT = 8 # macro -A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 # macro -A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT = 10 # macro -A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 # macro -A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT = 12 # macro -A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE = 0x00010000 # macro -A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE = 0x00020000 # macro -REG_A4XX_CP_DRAW_INDIRECT_1 = 0x00000001 # macro -A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDIRECT_1 = 0x00000001 # macro -A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDIRECT_2 = 0x00000002 # macro -A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDIRECT_INDIRECT = 0x00000001 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_0 = 0x00000000 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT = 0 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK = 0x00000300 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT = 8 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT = 10 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT = 12 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE = 0x00010000 # macro -A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE = 0x00020000 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 # macro -A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT = 0 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 # macro -A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT = 0 # macro -REG_A4XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 # macro -A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK = 0xffffffff # macro -A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 # macro -A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 # macro -A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE = 0x00000001 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 # macro -A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_4 = 0x00000004 # macro -A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_5 = 0x00000005 # macro -A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK = 0xffffffff # macro -A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT = 0 # macro -REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT = 0x00000004 # macro -REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 = 0x00000000 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK = 0x0000003f # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT = 0 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT = 6 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK = 0x00000300 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT = 8 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK = 0x00000c00 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT = 10 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK = 0x00003000 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT = 12 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE = 0x00010000 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE = 0x00020000 # macro -REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 = 0x00000001 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK = 0x0000000f # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT = 0 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK = 0x003fff00 # macro -A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT = 8 # macro -REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT = 0x00000002 # macro -REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 # macro -REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000005 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 # macro -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000008 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000005 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000007 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000008 # macro -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x0000000a # macro -REG_CP_DRAW_AUTO_0 = 0x00000000 # macro -CP_DRAW_AUTO_0_PRIM_TYPE__MASK = 0x0000003f # macro -CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT = 0 # macro -CP_DRAW_AUTO_0_SOURCE_SELECT__MASK = 0x000000c0 # macro -CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT = 6 # macro -CP_DRAW_AUTO_0_VIS_CULL__MASK = 0x00000300 # macro -CP_DRAW_AUTO_0_VIS_CULL__SHIFT = 8 # macro -CP_DRAW_AUTO_0_INDEX_SIZE__MASK = 0x00000c00 # macro -CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT = 10 # macro -CP_DRAW_AUTO_0_PATCH_TYPE__MASK = 0x00003000 # macro -CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT = 12 # macro -CP_DRAW_AUTO_0_GS_ENABLE = 0x00010000 # macro -CP_DRAW_AUTO_0_TESS_ENABLE = 0x00020000 # macro -REG_CP_DRAW_AUTO_1 = 0x00000001 # macro -CP_DRAW_AUTO_1_NUM_INSTANCES__MASK = 0xffffffff # macro -CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT = 0 # macro -REG_CP_DRAW_AUTO_NUM_VERTICES_BASE = 0x00000002 # macro -REG_CP_DRAW_AUTO_4 = 0x00000004 # macro -CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK = 0xffffffff # macro -CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT = 0 # macro -REG_CP_DRAW_AUTO_5 = 0x00000005 # macro -CP_DRAW_AUTO_5_STRIDE__MASK = 0xffffffff # macro -CP_DRAW_AUTO_5_STRIDE__SHIFT = 0 # macro -REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 = 0x00000000 # macro -CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE = 0x00000001 # macro -REG_CP_DRAW_PRED_ENABLE_LOCAL_0 = 0x00000000 # macro -CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE = 0x00000001 # macro -REG_CP_DRAW_PRED_SET_0 = 0x00000000 # macro -CP_DRAW_PRED_SET_0_SRC__MASK = 0x000000f0 # macro -CP_DRAW_PRED_SET_0_SRC__SHIFT = 4 # macro -CP_DRAW_PRED_SET_0_TEST__MASK = 0x00000100 # macro -CP_DRAW_PRED_SET_0_TEST__SHIFT = 8 # macro -REG_CP_DRAW_PRED_SET_MEM_ADDR = 0x00000001 # macro -# def REG_CP_SET_DRAW_STATE_(i0): # macro -# return (0x00000000+0x3*i0) -CP_SET_DRAW_STATE__0_COUNT__MASK = 0x0000ffff # macro -CP_SET_DRAW_STATE__0_COUNT__SHIFT = 0 # macro -CP_SET_DRAW_STATE__0_DIRTY = 0x00010000 # macro -CP_SET_DRAW_STATE__0_DISABLE = 0x00020000 # macro -CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS = 0x00040000 # macro -CP_SET_DRAW_STATE__0_LOAD_IMMED = 0x00080000 # macro -CP_SET_DRAW_STATE__0_BINNING = 0x00100000 # macro -CP_SET_DRAW_STATE__0_GMEM = 0x00200000 # macro -CP_SET_DRAW_STATE__0_SYSMEM = 0x00400000 # macro -CP_SET_DRAW_STATE__0_GROUP_ID__MASK = 0x1f000000 # macro -CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT = 24 # macro -CP_SET_DRAW_STATE__1_ADDR_LO__MASK = 0xffffffff # macro -CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT = 0 # macro -CP_SET_DRAW_STATE__2_ADDR_HI__MASK = 0xffffffff # macro -CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_0 = 0x00000000 # macro -REG_CP_SET_BIN_1 = 0x00000001 # macro -CP_SET_BIN_1_X1__MASK = 0x0000ffff # macro -CP_SET_BIN_1_X1__SHIFT = 0 # macro -CP_SET_BIN_1_Y1__MASK = 0xffff0000 # macro -CP_SET_BIN_1_Y1__SHIFT = 16 # macro -REG_CP_SET_BIN_2 = 0x00000002 # macro -CP_SET_BIN_2_X2__MASK = 0x0000ffff # macro -CP_SET_BIN_2_X2__SHIFT = 0 # macro -CP_SET_BIN_2_Y2__MASK = 0xffff0000 # macro -CP_SET_BIN_2_Y2__SHIFT = 16 # macro -REG_CP_SET_BIN_DATA_0 = 0x00000000 # macro -CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK = 0xffffffff # macro -CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA_1 = 0x00000001 # macro -CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK = 0xffffffff # macro -CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_0 = 0x00000000 # macro -CP_SET_BIN_DATA5_0_VSC_SIZE__MASK = 0x003f0000 # macro -CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT = 16 # macro -CP_SET_BIN_DATA5_0_VSC_N__MASK = 0x07c00000 # macro -CP_SET_BIN_DATA5_0_VSC_N__SHIFT = 22 # macro -REG_CP_SET_BIN_DATA5_1 = 0x00000001 # macro -CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_2 = 0x00000002 # macro -CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_3 = 0x00000003 # macro -CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_4 = 0x00000004 # macro -CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_5 = 0x00000005 # macro -CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_6 = 0x00000006 # macro -CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_7 = 0x00000007 # macro -REG_CP_SET_BIN_DATA5_9 = 0x00000009 # macro -REG_CP_SET_BIN_DATA5_OFFSET_0 = 0x00000000 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK = 0x003f0000 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT = 16 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK = 0x07c00000 # macro -CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT = 22 # macro -REG_CP_SET_BIN_DATA5_OFFSET_1 = 0x00000001 # macro -CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 # macro -CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT = 0 # macro -REG_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 # macro -CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK = 0xffffffff # macro -CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT = 0 # macro -REG_CP_REG_RMW_0 = 0x00000000 # macro -CP_REG_RMW_0_DST_REG__MASK = 0x0003ffff # macro -CP_REG_RMW_0_DST_REG__SHIFT = 0 # macro -CP_REG_RMW_0_ROTATE__MASK = 0x1f000000 # macro -CP_REG_RMW_0_ROTATE__SHIFT = 24 # macro -CP_REG_RMW_0_SRC1_ADD = 0x20000000 # macro -CP_REG_RMW_0_SRC1_IS_REG = 0x40000000 # macro -CP_REG_RMW_0_SRC0_IS_REG = 0x80000000 # macro -REG_CP_REG_RMW_1 = 0x00000001 # macro -CP_REG_RMW_1_SRC0__MASK = 0xffffffff # macro -CP_REG_RMW_1_SRC0__SHIFT = 0 # macro -REG_CP_REG_RMW_2 = 0x00000002 # macro -CP_REG_RMW_2_SRC1__MASK = 0xffffffff # macro -CP_REG_RMW_2_SRC1__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_0 = 0x00000000 # macro -CP_REG_TO_MEM_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_0_REG__SHIFT = 0 # macro -CP_REG_TO_MEM_0_CNT__MASK = 0x3ffc0000 # macro -CP_REG_TO_MEM_0_CNT__SHIFT = 18 # macro -CP_REG_TO_MEM_0_64B = 0x40000000 # macro -CP_REG_TO_MEM_0_ACCUMULATE = 0x80000000 # macro -REG_CP_REG_TO_MEM_1 = 0x00000001 # macro -CP_REG_TO_MEM_1_DEST__MASK = 0xffffffff # macro -CP_REG_TO_MEM_1_DEST__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_2 = 0x00000002 # macro -CP_REG_TO_MEM_2_DEST_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_2_DEST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_0 = 0x00000000 # macro -CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT = 0 # macro -CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK = 0x3ffc0000 # macro -CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT = 18 # macro -CP_REG_TO_MEM_OFFSET_REG_0_64B = 0x40000000 # macro -CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE = 0x80000000 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_1 = 0x00000001 # macro -CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_2 = 0x00000002 # macro -CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_REG_3 = 0x00000003 # macro -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT = 0 # macro -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH = 0x00080000 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_0 = 0x00000000 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT = 0 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK = 0x3ffc0000 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT = 18 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_64B = 0x40000000 # macro -CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE = 0x80000000 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_1 = 0x00000001 # macro -CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_2 = 0x00000002 # macro -CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_3 = 0x00000003 # macro -CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT = 0 # macro -REG_CP_REG_TO_MEM_OFFSET_MEM_4 = 0x00000004 # macro -CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK = 0xffffffff # macro -CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT = 0 # macro -REG_CP_MEM_TO_REG_0 = 0x00000000 # macro -CP_MEM_TO_REG_0_REG__MASK = 0x0003ffff # macro -CP_MEM_TO_REG_0_REG__SHIFT = 0 # macro -CP_MEM_TO_REG_0_CNT__MASK = 0x3ff80000 # macro -CP_MEM_TO_REG_0_CNT__SHIFT = 19 # macro -CP_MEM_TO_REG_0_SHIFT_BY_2 = 0x40000000 # macro -CP_MEM_TO_REG_0_UNK31 = 0x80000000 # macro -REG_CP_MEM_TO_REG_1 = 0x00000001 # macro -CP_MEM_TO_REG_1_SRC__MASK = 0xffffffff # macro -CP_MEM_TO_REG_1_SRC__SHIFT = 0 # macro -REG_CP_MEM_TO_REG_2 = 0x00000002 # macro -CP_MEM_TO_REG_2_SRC_HI__MASK = 0xffffffff # macro -CP_MEM_TO_REG_2_SRC_HI__SHIFT = 0 # macro -REG_CP_MEM_TO_MEM_0 = 0x00000000 # macro -CP_MEM_TO_MEM_0_NEG_A = 0x00000001 # macro -CP_MEM_TO_MEM_0_NEG_B = 0x00000002 # macro -CP_MEM_TO_MEM_0_NEG_C = 0x00000004 # macro -CP_MEM_TO_MEM_0_DOUBLE = 0x20000000 # macro -CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES = 0x40000000 # macro -CP_MEM_TO_MEM_0_UNK31 = 0x80000000 # macro -REG_CP_MEMCPY_0 = 0x00000000 # macro -CP_MEMCPY_0_DWORDS__MASK = 0xffffffff # macro -CP_MEMCPY_0_DWORDS__SHIFT = 0 # macro -REG_CP_MEMCPY_1 = 0x00000001 # macro -CP_MEMCPY_1_SRC_LO__MASK = 0xffffffff # macro -CP_MEMCPY_1_SRC_LO__SHIFT = 0 # macro -REG_CP_MEMCPY_2 = 0x00000002 # macro -CP_MEMCPY_2_SRC_HI__MASK = 0xffffffff # macro -CP_MEMCPY_2_SRC_HI__SHIFT = 0 # macro -REG_CP_MEMCPY_3 = 0x00000003 # macro -CP_MEMCPY_3_DST_LO__MASK = 0xffffffff # macro -CP_MEMCPY_3_DST_LO__SHIFT = 0 # macro -REG_CP_MEMCPY_4 = 0x00000004 # macro -CP_MEMCPY_4_DST_HI__MASK = 0xffffffff # macro -CP_MEMCPY_4_DST_HI__SHIFT = 0 # macro -REG_CP_REG_TO_SCRATCH_0 = 0x00000000 # macro -CP_REG_TO_SCRATCH_0_REG__MASK = 0x0003ffff # macro -CP_REG_TO_SCRATCH_0_REG__SHIFT = 0 # macro -CP_REG_TO_SCRATCH_0_SCRATCH__MASK = 0x00700000 # macro -CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT = 20 # macro -CP_REG_TO_SCRATCH_0_CNT__MASK = 0x07000000 # macro -CP_REG_TO_SCRATCH_0_CNT__SHIFT = 24 # macro -REG_CP_SCRATCH_TO_REG_0 = 0x00000000 # macro -CP_SCRATCH_TO_REG_0_REG__MASK = 0x0003ffff # macro -CP_SCRATCH_TO_REG_0_REG__SHIFT = 0 # macro -CP_SCRATCH_TO_REG_0_UNK18 = 0x00040000 # macro -CP_SCRATCH_TO_REG_0_SCRATCH__MASK = 0x00700000 # macro -CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT = 20 # macro -CP_SCRATCH_TO_REG_0_CNT__MASK = 0x07000000 # macro -CP_SCRATCH_TO_REG_0_CNT__SHIFT = 24 # macro -REG_CP_SCRATCH_WRITE_0 = 0x00000000 # macro -CP_SCRATCH_WRITE_0_SCRATCH__MASK = 0x00700000 # macro -CP_SCRATCH_WRITE_0_SCRATCH__SHIFT = 20 # macro -REG_CP_MEM_WRITE_0 = 0x00000000 # macro -CP_MEM_WRITE_0_ADDR_LO__MASK = 0xffffffff # macro -CP_MEM_WRITE_0_ADDR_LO__SHIFT = 0 # macro -REG_CP_MEM_WRITE_1 = 0x00000001 # macro -CP_MEM_WRITE_1_ADDR_HI__MASK = 0xffffffff # macro -CP_MEM_WRITE_1_ADDR_HI__SHIFT = 0 # macro -REG_CP_COND_WRITE_0 = 0x00000000 # macro -CP_COND_WRITE_0_FUNCTION__MASK = 0x00000007 # macro -CP_COND_WRITE_0_FUNCTION__SHIFT = 0 # macro -CP_COND_WRITE_0_POLL_MEMORY = 0x00000010 # macro -CP_COND_WRITE_0_WRITE_MEMORY = 0x00000100 # macro -REG_CP_COND_WRITE_1 = 0x00000001 # macro -CP_COND_WRITE_1_POLL_ADDR__MASK = 0xffffffff # macro -CP_COND_WRITE_1_POLL_ADDR__SHIFT = 0 # macro -REG_CP_COND_WRITE_2 = 0x00000002 # macro -CP_COND_WRITE_2_REF__MASK = 0xffffffff # macro -CP_COND_WRITE_2_REF__SHIFT = 0 # macro -REG_CP_COND_WRITE_3 = 0x00000003 # macro -CP_COND_WRITE_3_MASK__MASK = 0xffffffff # macro -CP_COND_WRITE_3_MASK__SHIFT = 0 # macro -REG_CP_COND_WRITE_4 = 0x00000004 # macro -CP_COND_WRITE_4_WRITE_ADDR__MASK = 0xffffffff # macro -CP_COND_WRITE_4_WRITE_ADDR__SHIFT = 0 # macro -REG_CP_COND_WRITE_5 = 0x00000005 # macro -CP_COND_WRITE_5_WRITE_DATA__MASK = 0xffffffff # macro -CP_COND_WRITE_5_WRITE_DATA__SHIFT = 0 # macro -REG_CP_COND_WRITE5_0 = 0x00000000 # macro -CP_COND_WRITE5_0_FUNCTION__MASK = 0x00000007 # macro -CP_COND_WRITE5_0_FUNCTION__SHIFT = 0 # macro -CP_COND_WRITE5_0_SIGNED_COMPARE = 0x00000008 # macro -CP_COND_WRITE5_0_POLL__MASK = 0x00000030 # macro -CP_COND_WRITE5_0_POLL__SHIFT = 4 # macro -CP_COND_WRITE5_0_WRITE_MEMORY = 0x00000100 # macro -REG_CP_COND_WRITE5_1 = 0x00000001 # macro -CP_COND_WRITE5_1_POLL_ADDR_LO__MASK = 0xffffffff # macro -CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT = 0 # macro -REG_CP_COND_WRITE5_2 = 0x00000002 # macro -CP_COND_WRITE5_2_POLL_ADDR_HI__MASK = 0xffffffff # macro -CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT = 0 # macro -REG_CP_COND_WRITE5_3 = 0x00000003 # macro -CP_COND_WRITE5_3_REF__MASK = 0xffffffff # macro -CP_COND_WRITE5_3_REF__SHIFT = 0 # macro -REG_CP_COND_WRITE5_4 = 0x00000004 # macro -CP_COND_WRITE5_4_MASK__MASK = 0xffffffff # macro -CP_COND_WRITE5_4_MASK__SHIFT = 0 # macro -REG_CP_COND_WRITE5_5 = 0x00000005 # macro -CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK = 0xffffffff # macro -CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT = 0 # macro -REG_CP_COND_WRITE5_6 = 0x00000006 # macro -CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK = 0xffffffff # macro -CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT = 0 # macro -REG_CP_COND_WRITE5_7 = 0x00000007 # macro -CP_COND_WRITE5_7_WRITE_DATA__MASK = 0xffffffff # macro -CP_COND_WRITE5_7_WRITE_DATA__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_0 = 0x00000000 # macro -CP_WAIT_MEM_GTE_0_RESERVED__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_0_RESERVED__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_1 = 0x00000001 # macro -CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_2 = 0x00000002 # macro -CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT = 0 # macro -REG_CP_WAIT_MEM_GTE_3 = 0x00000003 # macro -CP_WAIT_MEM_GTE_3_REF__MASK = 0xffffffff # macro -CP_WAIT_MEM_GTE_3_REF__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_0 = 0x00000000 # macro -CP_WAIT_REG_MEM_0_FUNCTION__MASK = 0x00000007 # macro -CP_WAIT_REG_MEM_0_FUNCTION__SHIFT = 0 # macro -CP_WAIT_REG_MEM_0_SIGNED_COMPARE = 0x00000008 # macro -CP_WAIT_REG_MEM_0_POLL__MASK = 0x00000030 # macro -CP_WAIT_REG_MEM_0_POLL__SHIFT = 4 # macro -CP_WAIT_REG_MEM_0_WRITE_MEMORY = 0x00000100 # macro -REG_CP_WAIT_REG_MEM_1 = 0x00000001 # macro -CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_2 = 0x00000002 # macro -CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_3 = 0x00000003 # macro -CP_WAIT_REG_MEM_3_REF__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_3_REF__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_4 = 0x00000004 # macro -CP_WAIT_REG_MEM_4_MASK__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_4_MASK__SHIFT = 0 # macro -REG_CP_WAIT_REG_MEM_5 = 0x00000005 # macro -CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK = 0xffffffff # macro -CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT = 0 # macro -REG_CP_WAIT_TWO_REGS_0 = 0x00000000 # macro -CP_WAIT_TWO_REGS_0_REG0__MASK = 0x0003ffff # macro -CP_WAIT_TWO_REGS_0_REG0__SHIFT = 0 # macro -REG_CP_WAIT_TWO_REGS_1 = 0x00000001 # macro -CP_WAIT_TWO_REGS_1_REG1__MASK = 0x0003ffff # macro -CP_WAIT_TWO_REGS_1_REG1__SHIFT = 0 # macro -REG_CP_WAIT_TWO_REGS_2 = 0x00000002 # macro -CP_WAIT_TWO_REGS_2_REF__MASK = 0xffffffff # macro -CP_WAIT_TWO_REGS_2_REF__SHIFT = 0 # macro -REG_CP_DISPATCH_COMPUTE_0 = 0x00000000 # macro -REG_CP_DISPATCH_COMPUTE_1 = 0x00000001 # macro -CP_DISPATCH_COMPUTE_1_X__MASK = 0xffffffff # macro -CP_DISPATCH_COMPUTE_1_X__SHIFT = 0 # macro -REG_CP_DISPATCH_COMPUTE_2 = 0x00000002 # macro -CP_DISPATCH_COMPUTE_2_Y__MASK = 0xffffffff # macro -CP_DISPATCH_COMPUTE_2_Y__SHIFT = 0 # macro -REG_CP_DISPATCH_COMPUTE_3 = 0x00000003 # macro -CP_DISPATCH_COMPUTE_3_Z__MASK = 0xffffffff # macro -CP_DISPATCH_COMPUTE_3_Z__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_0 = 0x00000000 # macro -CP_SET_RENDER_MODE_0_MODE__MASK = 0x000001ff # macro -CP_SET_RENDER_MODE_0_MODE__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_1 = 0x00000001 # macro -CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_2 = 0x00000002 # macro -CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_3 = 0x00000003 # macro -CP_SET_RENDER_MODE_3_VSC_ENABLE = 0x00000008 # macro -CP_SET_RENDER_MODE_3_GMEM_ENABLE = 0x00000010 # macro -REG_CP_SET_RENDER_MODE_4 = 0x00000004 # macro -REG_CP_SET_RENDER_MODE_5 = 0x00000005 # macro -CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_6 = 0x00000006 # macro -CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT = 0 # macro -REG_CP_SET_RENDER_MODE_7 = 0x00000007 # macro -CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK = 0xffffffff # macro -CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_0 = 0x00000000 # macro -CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_1 = 0x00000001 # macro -CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_2 = 0x00000002 # macro -REG_CP_COMPUTE_CHECKPOINT_3 = 0x00000003 # macro -REG_CP_COMPUTE_CHECKPOINT_4 = 0x00000004 # macro -CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_5 = 0x00000005 # macro -CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_6 = 0x00000006 # macro -CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK = 0xffffffff # macro -CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT = 0 # macro -REG_CP_COMPUTE_CHECKPOINT_7 = 0x00000007 # macro -REG_CP_PERFCOUNTER_ACTION_0 = 0x00000000 # macro -REG_CP_PERFCOUNTER_ACTION_1 = 0x00000001 # macro -CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK = 0xffffffff # macro -CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_PERFCOUNTER_ACTION_2 = 0x00000002 # macro -CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK = 0xffffffff # macro -CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_EVENT_WRITE_0 = 0x00000000 # macro -CP_EVENT_WRITE_0_EVENT__MASK = 0x000000ff # macro -CP_EVENT_WRITE_0_EVENT__SHIFT = 0 # macro -CP_EVENT_WRITE_0_TIMESTAMP = 0x40000000 # macro -CP_EVENT_WRITE_0_IRQ = 0x80000000 # macro -REG_CP_EVENT_WRITE_1 = 0x00000001 # macro -CP_EVENT_WRITE_1_ADDR_0_LO__MASK = 0xffffffff # macro -CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT = 0 # macro -REG_CP_EVENT_WRITE_2 = 0x00000002 # macro -CP_EVENT_WRITE_2_ADDR_0_HI__MASK = 0xffffffff # macro -CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT = 0 # macro -REG_CP_EVENT_WRITE_3 = 0x00000003 # macro -REG_CP_EVENT_WRITE7_0 = 0x00000000 # macro -CP_EVENT_WRITE7_0_EVENT__MASK = 0x000000ff # macro -CP_EVENT_WRITE7_0_EVENT__SHIFT = 0 # macro -CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT = 0x00001000 # macro -CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET = 0x00002000 # macro -CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF = 0x00004000 # macro -CP_EVENT_WRITE7_0_INC_BV_COUNT = 0x00010000 # macro -CP_EVENT_WRITE7_0_INC_BR_COUNT = 0x00020000 # macro -CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE = 0x00040000 # macro -CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE = 0x00080000 # macro -CP_EVENT_WRITE7_0_WRITE_SRC__MASK = 0x00700000 # macro -CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT = 20 # macro -CP_EVENT_WRITE7_0_WRITE_DST__MASK = 0x01000000 # macro -CP_EVENT_WRITE7_0_WRITE_DST__SHIFT = 24 # macro -CP_EVENT_WRITE7_0_WRITE_ENABLED = 0x08000000 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_1 = 0x00000001 # macro -EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT = 0 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_2 = 0x00000002 # macro -EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT = 0 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_3 = 0x00000003 # macro -EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 # macro -REG_EV_DST_RAM_CP_EVENT_WRITE7_4 = 0x00000004 # macro -EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff # macro -EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 # macro -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 = 0x00000001 # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK = 0xffffffff # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT = 0 # macro -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 = 0x00000003 # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 # macro -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 = 0x00000004 # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff # macro -EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 # macro -REG_CP_BLIT_0 = 0x00000000 # macro -CP_BLIT_0_OP__MASK = 0x0000000f # macro -CP_BLIT_0_OP__SHIFT = 0 # macro -REG_CP_BLIT_1 = 0x00000001 # macro -CP_BLIT_1_SRC_X1__MASK = 0x00003fff # macro -CP_BLIT_1_SRC_X1__SHIFT = 0 # macro -CP_BLIT_1_SRC_Y1__MASK = 0x3fff0000 # macro -CP_BLIT_1_SRC_Y1__SHIFT = 16 # macro -REG_CP_BLIT_2 = 0x00000002 # macro -CP_BLIT_2_SRC_X2__MASK = 0x00003fff # macro -CP_BLIT_2_SRC_X2__SHIFT = 0 # macro -CP_BLIT_2_SRC_Y2__MASK = 0x3fff0000 # macro -CP_BLIT_2_SRC_Y2__SHIFT = 16 # macro -REG_CP_BLIT_3 = 0x00000003 # macro -CP_BLIT_3_DST_X1__MASK = 0x00003fff # macro -CP_BLIT_3_DST_X1__SHIFT = 0 # macro -CP_BLIT_3_DST_Y1__MASK = 0x3fff0000 # macro -CP_BLIT_3_DST_Y1__SHIFT = 16 # macro -REG_CP_BLIT_4 = 0x00000004 # macro -CP_BLIT_4_DST_X2__MASK = 0x00003fff # macro -CP_BLIT_4_DST_X2__SHIFT = 0 # macro -CP_BLIT_4_DST_Y2__MASK = 0x3fff0000 # macro -CP_BLIT_4_DST_Y2__SHIFT = 16 # macro -REG_CP_EXEC_CS_0 = 0x00000000 # macro -REG_CP_EXEC_CS_1 = 0x00000001 # macro -CP_EXEC_CS_1_NGROUPS_X__MASK = 0xffffffff # macro -CP_EXEC_CS_1_NGROUPS_X__SHIFT = 0 # macro -REG_CP_EXEC_CS_2 = 0x00000002 # macro -CP_EXEC_CS_2_NGROUPS_Y__MASK = 0xffffffff # macro -CP_EXEC_CS_2_NGROUPS_Y__SHIFT = 0 # macro -REG_CP_EXEC_CS_3 = 0x00000003 # macro -CP_EXEC_CS_3_NGROUPS_Z__MASK = 0xffffffff # macro -CP_EXEC_CS_3_NGROUPS_Z__SHIFT = 0 # macro -REG_A4XX_CP_EXEC_CS_INDIRECT_0 = 0x00000000 # macro -REG_A4XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 # macro -A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK = 0xffffffff # macro -A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT = 0 # macro -REG_A4XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK = 0x00000ffc # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT = 2 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK = 0x003ff000 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT = 12 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK = 0xffc00000 # macro -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT = 22 # macro -REG_A5XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 # macro -A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK = 0xffffffff # macro -A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT = 0 # macro -REG_A5XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 # macro -A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK = 0xffffffff # macro -A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT = 0 # macro -REG_A5XX_CP_EXEC_CS_INDIRECT_3 = 0x00000003 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK = 0x00000ffc # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT = 2 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK = 0x003ff000 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT = 12 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK = 0xffc00000 # macro -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT = 22 # macro -REG_A6XX_CP_SET_MARKER_0 = 0x00000000 # macro -A6XX_CP_SET_MARKER_0_MODE__MASK = 0x000001ff # macro -A6XX_CP_SET_MARKER_0_MODE__SHIFT = 0 # macro -A6XX_CP_SET_MARKER_0_MARKER__MASK = 0x0000000f # macro -A6XX_CP_SET_MARKER_0_MARKER__SHIFT = 0 # macro -# def REG_A6XX_CP_SET_PSEUDO_REG_(i0): # macro -# return (0x00000000+0x3*i0) -A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK = 0x000007ff # macro -A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT = 0 # macro -A6XX_CP_SET_PSEUDO_REG__1_LO__MASK = 0xffffffff # macro -A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT = 0 # macro -A6XX_CP_SET_PSEUDO_REG__2_HI__MASK = 0xffffffff # macro -A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT = 0 # macro -REG_A6XX_CP_REG_TEST_0 = 0x00000000 # macro -A6XX_CP_REG_TEST_0_REG__MASK = 0x0003ffff # macro -A6XX_CP_REG_TEST_0_REG__SHIFT = 0 # macro -A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK = 0x0003ffff # macro -A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT = 0 # macro -A6XX_CP_REG_TEST_0_SOURCE__MASK = 0x00040000 # macro -A6XX_CP_REG_TEST_0_SOURCE__SHIFT = 18 # macro -A6XX_CP_REG_TEST_0_BIT__MASK = 0x01f00000 # macro -A6XX_CP_REG_TEST_0_BIT__SHIFT = 20 # macro -A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME = 0x02000000 # macro -A6XX_CP_REG_TEST_0_PRED_BIT__MASK = 0x7c000000 # macro -A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT = 26 # macro -A6XX_CP_REG_TEST_0_PRED_UPDATE = 0x80000000 # macro -REG_A6XX_CP_REG_TEST_PRED_MASK = 0x00000001 # macro -REG_A6XX_CP_REG_TEST_PRED_VAL = 0x00000002 # macro -REG_CP_COND_REG_EXEC_0 = 0x00000000 # macro -CP_COND_REG_EXEC_0_REG0__MASK = 0x0003ffff # macro -CP_COND_REG_EXEC_0_REG0__SHIFT = 0 # macro -CP_COND_REG_EXEC_0_PRED_BIT__MASK = 0x007c0000 # macro -CP_COND_REG_EXEC_0_PRED_BIT__SHIFT = 18 # macro -CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME = 0x00800000 # macro -CP_COND_REG_EXEC_0_ONCHIP_MEM = 0x01000000 # macro -CP_COND_REG_EXEC_0_BINNING = 0x02000000 # macro -CP_COND_REG_EXEC_0_GMEM = 0x04000000 # macro -CP_COND_REG_EXEC_0_SYSMEM = 0x08000000 # macro -CP_COND_REG_EXEC_0_BV = 0x02000000 # macro -CP_COND_REG_EXEC_0_BR = 0x04000000 # macro -CP_COND_REG_EXEC_0_LPAC = 0x08000000 # macro -CP_COND_REG_EXEC_0_MODE__MASK = 0xf0000000 # macro -CP_COND_REG_EXEC_0_MODE__SHIFT = 28 # macro -REG_PRED_TEST_CP_COND_REG_EXEC_1 = 0x00000001 # macro -PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro -PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro -REG_REG_COMPARE_CP_COND_REG_EXEC_1 = 0x00000001 # macro -REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK = 0x0003ffff # macro -REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT = 0 # macro -REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM = 0x01000000 # macro -REG_RENDER_MODE_CP_COND_REG_EXEC_1 = 0x00000001 # macro -RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro -RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro -REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 = 0x00000001 # macro -REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK = 0xffffffff # macro -REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT = 0 # macro -REG_THREAD_MODE_CP_COND_REG_EXEC_1 = 0x00000001 # macro -THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro -THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro -REG_CP_COND_REG_EXEC_2 = 0x00000002 # macro -CP_COND_REG_EXEC_2_DWORDS__MASK = 0x00ffffff # macro -CP_COND_REG_EXEC_2_DWORDS__SHIFT = 0 # macro -REG_CP_COND_EXEC_0 = 0x00000000 # macro -CP_COND_EXEC_0_ADDR0_LO__MASK = 0xffffffff # macro -CP_COND_EXEC_0_ADDR0_LO__SHIFT = 0 # macro -REG_CP_COND_EXEC_1 = 0x00000001 # macro -CP_COND_EXEC_1_ADDR0_HI__MASK = 0xffffffff # macro -CP_COND_EXEC_1_ADDR0_HI__SHIFT = 0 # macro -REG_CP_COND_EXEC_2 = 0x00000002 # macro -CP_COND_EXEC_2_ADDR1_LO__MASK = 0xffffffff # macro -CP_COND_EXEC_2_ADDR1_LO__SHIFT = 0 # macro -REG_CP_COND_EXEC_3 = 0x00000003 # macro -CP_COND_EXEC_3_ADDR1_HI__MASK = 0xffffffff # macro -CP_COND_EXEC_3_ADDR1_HI__SHIFT = 0 # macro -REG_CP_COND_EXEC_4 = 0x00000004 # macro -CP_COND_EXEC_4_REF__MASK = 0xffffffff # macro -CP_COND_EXEC_4_REF__SHIFT = 0 # macro -REG_CP_COND_EXEC_5 = 0x00000005 # macro -CP_COND_EXEC_5_DWORDS__MASK = 0xffffffff # macro -CP_COND_EXEC_5_DWORDS__SHIFT = 0 # macro -REG_CP_SET_CTXSWITCH_IB_0 = 0x00000000 # macro -CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK = 0xffffffff # macro -CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT = 0 # macro -REG_CP_SET_CTXSWITCH_IB_1 = 0x00000001 # macro -CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK = 0xffffffff # macro -CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT = 0 # macro -REG_CP_SET_CTXSWITCH_IB_2 = 0x00000002 # macro -CP_SET_CTXSWITCH_IB_2_DWORDS__MASK = 0x000fffff # macro -CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT = 0 # macro -CP_SET_CTXSWITCH_IB_2_TYPE__MASK = 0x00300000 # macro -CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT = 20 # macro -REG_CP_REG_WRITE_0 = 0x00000000 # macro -CP_REG_WRITE_0_TRACKER__MASK = 0x0000000f # macro -CP_REG_WRITE_0_TRACKER__SHIFT = 0 # macro -REG_CP_REG_WRITE_1 = 0x00000001 # macro -REG_CP_REG_WRITE_2 = 0x00000002 # macro -REG_CP_SMMU_TABLE_UPDATE_0 = 0x00000000 # macro -CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK = 0xffffffff # macro -CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT = 0 # macro -REG_CP_SMMU_TABLE_UPDATE_1 = 0x00000001 # macro -CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK = 0x0000ffff # macro -CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT = 0 # macro -CP_SMMU_TABLE_UPDATE_1_ASID__MASK = 0xffff0000 # macro -CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT = 16 # macro -REG_CP_SMMU_TABLE_UPDATE_2 = 0x00000002 # macro -CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK = 0xffffffff # macro -CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT = 0 # macro -REG_CP_SMMU_TABLE_UPDATE_3 = 0x00000003 # macro -CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK = 0xffffffff # macro -CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT = 0 # macro -REG_CP_START_BIN_BIN_COUNT = 0x00000000 # macro -REG_CP_START_BIN_PREFIX_ADDR = 0x00000001 # macro -REG_CP_START_BIN_PREFIX_DWORDS = 0x00000003 # macro -REG_CP_START_BIN_BODY_DWORDS = 0x00000004 # macro -REG_CP_WAIT_TIMESTAMP_0 = 0x00000000 # macro -CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK = 0x00000003 # macro -CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT = 0 # macro -CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK = 0x00000010 # macro -CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT = 4 # macro -REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR = 0x00000001 # macro -REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 = 0x00000001 # macro -REG_CP_WAIT_TIMESTAMP_SRC_0 = 0x00000003 # macro -REG_CP_WAIT_TIMESTAMP_SRC_1 = 0x00000004 # macro -REG_CP_BV_BR_COUNT_OPS_0 = 0x00000000 # macro -CP_BV_BR_COUNT_OPS_0_OP__MASK = 0x0000000f # macro -CP_BV_BR_COUNT_OPS_0_OP__SHIFT = 0 # macro -REG_CP_BV_BR_COUNT_OPS_1 = 0x00000001 # macro -CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK = 0x0000ffff # macro -CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT = 0 # macro -REG_CP_MODIFY_TIMESTAMP_0 = 0x00000000 # macro -CP_MODIFY_TIMESTAMP_0_ADD__MASK = 0x000000ff # macro -CP_MODIFY_TIMESTAMP_0_ADD__SHIFT = 0 # macro -CP_MODIFY_TIMESTAMP_0_OP__MASK = 0xf0000000 # macro -CP_MODIFY_TIMESTAMP_0_OP__SHIFT = 28 # macro -REG_CP_MEM_TO_SCRATCH_MEM_0 = 0x00000000 # macro -CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK = 0x0000003f # macro -CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT = 0 # macro -REG_CP_MEM_TO_SCRATCH_MEM_1 = 0x00000001 # macro -CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK = 0x0000003f # macro -CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT = 0 # macro -REG_CP_MEM_TO_SCRATCH_MEM_2 = 0x00000002 # macro -CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK = 0xffffffff # macro -CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT = 0 # macro -REG_CP_MEM_TO_SCRATCH_MEM_3 = 0x00000003 # macro -CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK = 0xffffffff # macro -CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT = 0 # macro -REG_CP_THREAD_CONTROL_0 = 0x00000000 # macro -CP_THREAD_CONTROL_0_THREAD__MASK = 0x00000003 # macro -CP_THREAD_CONTROL_0_THREAD__SHIFT = 0 # macro -CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE = 0x08000000 # macro -CP_THREAD_CONTROL_0_SYNC_THREADS = 0x80000000 # macro -REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE = 0x00000000 # macro -REG_CP_FIXED_STRIDE_DRAW_TABLE_2 = 0x00000002 # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK = 0x00000fff # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT = 0 # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK = 0xfff00000 # macro -CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT = 20 # macro -REG_CP_FIXED_STRIDE_DRAW_TABLE_3 = 0x00000003 # macro -CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK = 0xffffffff # macro -CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT = 0 # macro -REG_CP_RESET_CONTEXT_STATE_0 = 0x00000000 # macro -CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS = 0x00000001 # macro -CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE = 0x00000002 # macro -CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS = 0x00000004 # macro -REG_AXXX_CP_RB_BASE = 0x000001c0 # macro -REG_AXXX_CP_RB_CNTL = 0x000001c1 # macro -AXXX_CP_RB_CNTL_BUFSZ__MASK = 0x0000003f # macro -AXXX_CP_RB_CNTL_BUFSZ__SHIFT = 0 # macro -AXXX_CP_RB_CNTL_BLKSZ__MASK = 0x00003f00 # macro -AXXX_CP_RB_CNTL_BLKSZ__SHIFT = 8 # macro -AXXX_CP_RB_CNTL_BUF_SWAP__MASK = 0x00030000 # macro -AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT = 16 # macro -AXXX_CP_RB_CNTL_POLL_EN = 0x00100000 # macro -AXXX_CP_RB_CNTL_NO_UPDATE = 0x08000000 # macro -AXXX_CP_RB_CNTL_RPTR_WR_EN = 0x80000000 # macro -REG_AXXX_CP_RB_RPTR_ADDR = 0x000001c3 # macro -AXXX_CP_RB_RPTR_ADDR_SWAP__MASK = 0x00000003 # macro -AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT = 0 # macro -AXXX_CP_RB_RPTR_ADDR_ADDR__MASK = 0xfffffffc # macro -AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT = 2 # macro -REG_AXXX_CP_RB_RPTR = 0x000001c4 # macro -REG_AXXX_CP_RB_WPTR = 0x000001c5 # macro -REG_AXXX_CP_RB_WPTR_DELAY = 0x000001c6 # macro -REG_AXXX_CP_RB_RPTR_WR = 0x000001c7 # macro -REG_AXXX_CP_RB_WPTR_BASE = 0x000001c8 # macro -REG_AXXX_CP_QUEUE_THRESHOLDS = 0x000001d5 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK = 0x0000000f # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT = 0 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK = 0x00000f00 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT = 8 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK = 0x000f0000 # macro -AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT = 16 # macro -REG_AXXX_CP_MEQ_THRESHOLDS = 0x000001d6 # macro -AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK = 0x001f0000 # macro -AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT = 16 # macro -AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK = 0x1f000000 # macro -AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT = 24 # macro -REG_AXXX_CP_CSQ_AVAIL = 0x000001d7 # macro -AXXX_CP_CSQ_AVAIL_RING__MASK = 0x0000007f # macro -AXXX_CP_CSQ_AVAIL_RING__SHIFT = 0 # macro -AXXX_CP_CSQ_AVAIL_IB1__MASK = 0x00007f00 # macro -AXXX_CP_CSQ_AVAIL_IB1__SHIFT = 8 # macro -AXXX_CP_CSQ_AVAIL_IB2__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_AVAIL_IB2__SHIFT = 16 # macro -REG_AXXX_CP_STQ_AVAIL = 0x000001d8 # macro -AXXX_CP_STQ_AVAIL_ST__MASK = 0x0000007f # macro -AXXX_CP_STQ_AVAIL_ST__SHIFT = 0 # macro -REG_AXXX_CP_MEQ_AVAIL = 0x000001d9 # macro -AXXX_CP_MEQ_AVAIL_MEQ__MASK = 0x0000001f # macro -AXXX_CP_MEQ_AVAIL_MEQ__SHIFT = 0 # macro -REG_AXXX_SCRATCH_UMSK = 0x000001dc # macro -AXXX_SCRATCH_UMSK_UMSK__MASK = 0x000000ff # macro -AXXX_SCRATCH_UMSK_UMSK__SHIFT = 0 # macro -AXXX_SCRATCH_UMSK_SWAP__MASK = 0x00030000 # macro -AXXX_SCRATCH_UMSK_SWAP__SHIFT = 16 # macro -REG_AXXX_SCRATCH_ADDR = 0x000001dd # macro -REG_AXXX_CP_ME_RDADDR = 0x000001ea # macro -REG_AXXX_CP_STATE_DEBUG_INDEX = 0x000001ec # macro -REG_AXXX_CP_STATE_DEBUG_DATA = 0x000001ed # macro -REG_AXXX_CP_INT_CNTL = 0x000001f2 # macro -AXXX_CP_INT_CNTL_SW_INT_MASK = 0x00080000 # macro -AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK = 0x00800000 # macro -AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK = 0x01000000 # macro -AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK = 0x02000000 # macro -AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK = 0x04000000 # macro -AXXX_CP_INT_CNTL_IB_ERROR_MASK = 0x08000000 # macro -AXXX_CP_INT_CNTL_IB2_INT_MASK = 0x20000000 # macro -AXXX_CP_INT_CNTL_IB1_INT_MASK = 0x40000000 # macro -AXXX_CP_INT_CNTL_RB_INT_MASK = 0x80000000 # macro -REG_AXXX_CP_INT_STATUS = 0x000001f3 # macro -REG_AXXX_CP_INT_ACK = 0x000001f4 # macro -REG_AXXX_CP_ME_CNTL = 0x000001f6 # macro -AXXX_CP_ME_CNTL_BUSY = 0x20000000 # macro -AXXX_CP_ME_CNTL_HALT = 0x10000000 # macro -REG_AXXX_CP_ME_STATUS = 0x000001f7 # macro -REG_AXXX_CP_ME_RAM_WADDR = 0x000001f8 # macro -REG_AXXX_CP_ME_RAM_RADDR = 0x000001f9 # macro -REG_AXXX_CP_ME_RAM_DATA = 0x000001fa # macro -REG_AXXX_CP_DEBUG = 0x000001fc # macro -AXXX_CP_DEBUG_PREDICATE_DISABLE = 0x00800000 # macro -AXXX_CP_DEBUG_PROG_END_PTR_ENABLE = 0x01000000 # macro -AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE = 0x02000000 # macro -AXXX_CP_DEBUG_PREFETCH_PASS_NOPS = 0x04000000 # macro -AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE = 0x08000000 # macro -AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE = 0x10000000 # macro -AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL = 0x40000000 # macro -AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE = 0x80000000 # macro -REG_AXXX_CP_CSQ_RB_STAT = 0x000001fd # macro -AXXX_CP_CSQ_RB_STAT_RPTR__MASK = 0x0000007f # macro -AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT = 0 # macro -AXXX_CP_CSQ_RB_STAT_WPTR__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT = 16 # macro -REG_AXXX_CP_CSQ_IB1_STAT = 0x000001fe # macro -AXXX_CP_CSQ_IB1_STAT_RPTR__MASK = 0x0000007f # macro -AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT = 0 # macro -AXXX_CP_CSQ_IB1_STAT_WPTR__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT = 16 # macro -REG_AXXX_CP_CSQ_IB2_STAT = 0x000001ff # macro -AXXX_CP_CSQ_IB2_STAT_RPTR__MASK = 0x0000007f # macro -AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT = 0 # macro -AXXX_CP_CSQ_IB2_STAT_WPTR__MASK = 0x007f0000 # macro -AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT = 16 # macro -REG_AXXX_CP_NON_PREFETCH_CNTRS = 0x00000440 # macro -REG_AXXX_CP_STQ_ST_STAT = 0x00000443 # macro -REG_AXXX_CP_ST_BASE = 0x0000044d # macro -REG_AXXX_CP_ST_BUFSZ = 0x0000044e # macro -REG_AXXX_CP_MEQ_STAT = 0x0000044f # macro -REG_AXXX_CP_MIU_TAG_STAT = 0x00000452 # macro -REG_AXXX_CP_BIN_MASK_LO = 0x00000454 # macro -REG_AXXX_CP_BIN_MASK_HI = 0x00000455 # macro -REG_AXXX_CP_BIN_SELECT_LO = 0x00000456 # macro -REG_AXXX_CP_BIN_SELECT_HI = 0x00000457 # macro -REG_AXXX_CP_IB1_BASE = 0x00000458 # macro -REG_AXXX_CP_IB1_BUFSZ = 0x00000459 # macro -REG_AXXX_CP_IB2_BASE = 0x0000045a # macro -REG_AXXX_CP_IB2_BUFSZ = 0x0000045b # macro -REG_AXXX_CP_STAT = 0x0000047f # macro -AXXX_CP_STAT_CP_BUSY = 0x80000000 # macro -AXXX_CP_STAT_VS_EVENT_FIFO_BUSY = 0x40000000 # macro -AXXX_CP_STAT_PS_EVENT_FIFO_BUSY = 0x20000000 # macro -AXXX_CP_STAT_CF_EVENT_FIFO_BUSY = 0x10000000 # macro -AXXX_CP_STAT_RB_EVENT_FIFO_BUSY = 0x08000000 # macro -AXXX_CP_STAT_ME_BUSY = 0x04000000 # macro -AXXX_CP_STAT_MIU_WR_C_BUSY = 0x02000000 # macro -AXXX_CP_STAT_CP_3D_BUSY = 0x00800000 # macro -AXXX_CP_STAT_CP_NRT_BUSY = 0x00400000 # macro -AXXX_CP_STAT_RBIU_SCRATCH_BUSY = 0x00200000 # macro -AXXX_CP_STAT_RCIU_ME_BUSY = 0x00100000 # macro -AXXX_CP_STAT_RCIU_PFP_BUSY = 0x00080000 # macro -AXXX_CP_STAT_MEQ_RING_BUSY = 0x00040000 # macro -AXXX_CP_STAT_PFP_BUSY = 0x00020000 # macro -AXXX_CP_STAT_ST_QUEUE_BUSY = 0x00010000 # macro -AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY = 0x00002000 # macro -AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY = 0x00001000 # macro -AXXX_CP_STAT_RING_QUEUE_BUSY = 0x00000800 # macro -AXXX_CP_STAT_CSF_BUSY = 0x00000400 # macro -AXXX_CP_STAT_CSF_ST_BUSY = 0x00000200 # macro -AXXX_CP_STAT_EVENT_BUSY = 0x00000100 # macro -AXXX_CP_STAT_CSF_INDIRECT2_BUSY = 0x00000080 # macro -AXXX_CP_STAT_CSF_INDIRECTS_BUSY = 0x00000040 # macro -AXXX_CP_STAT_CSF_RING_BUSY = 0x00000020 # macro -AXXX_CP_STAT_RCIU_BUSY = 0x00000010 # macro -AXXX_CP_STAT_RBIU_BUSY = 0x00000008 # macro -AXXX_CP_STAT_MIU_RD_RETURN_BUSY = 0x00000004 # macro -AXXX_CP_STAT_MIU_RD_REQ_BUSY = 0x00000002 # macro -AXXX_CP_STAT_MIU_WR_BUSY = 0x00000001 # macro -REG_AXXX_CP_SCRATCH_REG0 = 0x00000578 # macro -REG_AXXX_CP_SCRATCH_REG1 = 0x00000579 # macro -REG_AXXX_CP_SCRATCH_REG2 = 0x0000057a # macro -REG_AXXX_CP_SCRATCH_REG3 = 0x0000057b # macro -REG_AXXX_CP_SCRATCH_REG4 = 0x0000057c # macro -REG_AXXX_CP_SCRATCH_REG5 = 0x0000057d # macro -REG_AXXX_CP_SCRATCH_REG6 = 0x0000057e # macro -REG_AXXX_CP_SCRATCH_REG7 = 0x0000057f # macro -REG_AXXX_CP_ME_VS_EVENT_SRC = 0x00000600 # macro -REG_AXXX_CP_ME_VS_EVENT_ADDR = 0x00000601 # macro -REG_AXXX_CP_ME_VS_EVENT_DATA = 0x00000602 # macro -REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM = 0x00000603 # macro -REG_AXXX_CP_ME_VS_EVENT_DATA_SWM = 0x00000604 # macro -REG_AXXX_CP_ME_PS_EVENT_SRC = 0x00000605 # macro -REG_AXXX_CP_ME_PS_EVENT_ADDR = 0x00000606 # macro -REG_AXXX_CP_ME_PS_EVENT_DATA = 0x00000607 # macro -REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM = 0x00000608 # macro -REG_AXXX_CP_ME_PS_EVENT_DATA_SWM = 0x00000609 # macro -REG_AXXX_CP_ME_CF_EVENT_SRC = 0x0000060a # macro -REG_AXXX_CP_ME_CF_EVENT_ADDR = 0x0000060b # macro -REG_AXXX_CP_ME_CF_EVENT_DATA = 0x0000060c # macro -REG_AXXX_CP_ME_NRT_ADDR = 0x0000060d # macro -REG_AXXX_CP_ME_NRT_DATA = 0x0000060e # macro -REG_AXXX_CP_ME_VS_FETCH_DONE_SRC = 0x00000612 # macro -REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR = 0x00000613 # macro -REG_AXXX_CP_ME_VS_FETCH_DONE_DATA = 0x00000614 # macro -A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE = 0x00000001 # macro -A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR = 0x00000002 # macro -A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 = 0x00000010 # macro -A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 = 0x00000020 # macro -A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW = 0x00000040 # macro -A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR = 0x00000080 # macro -A6XX_RBBM_INT_0_MASK_CP_SW = 0x00000100 # macro -A6XX_RBBM_INT_0_MASK_CP_HW_ERROR = 0x00000200 # macro -A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS = 0x00000400 # macro -A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS = 0x00000800 # macro -A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS = 0x00001000 # macro -A6XX_RBBM_INT_0_MASK_CP_IB2 = 0x00002000 # macro -A6XX_RBBM_INT_0_MASK_CP_IB1 = 0x00004000 # macro -A6XX_RBBM_INT_0_MASK_CP_RB = 0x00008000 # macro -A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT = 0x00008000 # macro -A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC = 0x00010000 # macro -A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS = 0x00020000 # macro -A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS = 0x00040000 # macro -A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS = 0x00100000 # macro -A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC = 0x00200000 # macro -A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW = 0x00400000 # macro -A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT = 0x00800000 # macro -A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS = 0x01000000 # macro -A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR = 0x02000000 # macro -A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 = 0x04000000 # macro -A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 = 0x08000000 # macro -A6XX_RBBM_INT_0_MASK_TSBWRITEERROR = 0x10000000 # macro -A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION = 0x20000000 # macro -A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ = 0x40000000 # macro -A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG = 0x80000000 # macro -A6XX_CP_INT_CP_OPCODE_ERROR = 0x00000001 # macro -A6XX_CP_INT_CP_UCODE_ERROR = 0x00000002 # macro -A6XX_CP_INT_CP_HW_FAULT_ERROR = 0x00000004 # macro -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR = 0x00000010 # macro -A6XX_CP_INT_CP_AHB_ERROR = 0x00000020 # macro -A6XX_CP_INT_CP_VSD_PARITY_ERROR = 0x00000040 # macro -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR = 0x00000080 # macro -A6XX_CP_INT_CP_OPCODE_ERROR_LPAC = 0x00000100 # macro -A6XX_CP_INT_CP_UCODE_ERROR_LPAC = 0x00000200 # macro -A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC = 0x00000400 # macro -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC = 0x00000800 # macro -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC = 0x00001000 # macro -A6XX_CP_INT_CP_OPCODE_ERROR_BV = 0x00002000 # macro -A6XX_CP_INT_CP_UCODE_ERROR_BV = 0x00004000 # macro -A6XX_CP_INT_CP_HW_FAULT_ERROR_BV = 0x00008000 # macro -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV = 0x00010000 # macro -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV = 0x00020000 # macro -REG_A6XX_CP_RB_BASE = 0x00000800 # macro -REG_A6XX_CP_RB_CNTL = 0x00000802 # macro -REG_A6XX_CP_RB_RPTR_ADDR = 0x00000804 # macro -REG_A6XX_CP_RB_RPTR = 0x00000806 # macro -REG_A6XX_CP_RB_WPTR = 0x00000807 # macro -REG_A6XX_CP_SQE_CNTL = 0x00000808 # macro -REG_A6XX_CP_CP2GMU_STATUS = 0x00000812 # macro -A6XX_CP_CP2GMU_STATUS_IFPC = 0x00000001 # macro -REG_A6XX_CP_HW_FAULT = 0x00000821 # macro -REG_A6XX_CP_INTERRUPT_STATUS = 0x00000823 # macro -REG_A6XX_CP_PROTECT_STATUS = 0x00000824 # macro -REG_A6XX_CP_STATUS_1 = 0x00000825 # macro -REG_A6XX_CP_SQE_INSTR_BASE = 0x00000830 # macro -REG_A6XX_CP_MISC_CNTL = 0x00000840 # macro -REG_A6XX_CP_APRIV_CNTL = 0x00000844 # macro -A6XX_CP_APRIV_CNTL_CDWRITE = 0x00000040 # macro -A6XX_CP_APRIV_CNTL_CDREAD = 0x00000020 # macro -A6XX_CP_APRIV_CNTL_RBRPWB = 0x00000008 # macro -A6XX_CP_APRIV_CNTL_RBPRIVLEVEL = 0x00000004 # macro -A6XX_CP_APRIV_CNTL_RBFETCH = 0x00000002 # macro -A6XX_CP_APRIV_CNTL_ICACHE = 0x00000001 # macro -REG_A6XX_CP_PREEMPT_THRESHOLD = 0x000008c0 # macro -REG_A6XX_CP_ROQ_THRESHOLDS_1 = 0x000008c1 # macro -A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK = 0x000000ff # macro -A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT = 0 # macro -A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK = 0x0000ff00 # macro -A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT = 8 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK = 0x00ff0000 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT = 16 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK = 0xff000000 # macro -A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT = 24 # macro -REG_A6XX_CP_ROQ_THRESHOLDS_2 = 0x000008c2 # macro -A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK = 0x000001ff # macro -A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT = 0 # macro -A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT = 16 # macro -REG_A6XX_CP_MEM_POOL_SIZE = 0x000008c3 # macro -REG_A6XX_CP_CHICKEN_DBG = 0x00000841 # macro -REG_A6XX_CP_ADDR_MODE_CNTL = 0x00000842 # macro -REG_A6XX_CP_DBG_ECO_CNTL = 0x00000843 # macro -REG_A6XX_CP_PROTECT_CNTL = 0x0000084f # macro -A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE = 0x00000008 # macro -A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN = 0x00000002 # macro -A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN = 0x00000001 # macro -# def REG_A6XX_CP_SCRATCH(i0): # macro -# return (0x00000883+0x1*i0) -# def REG_A6XX_CP_PROTECT(i0): # macro -# return (0x00000850+0x1*i0) -A6XX_CP_PROTECT_REG_BASE_ADDR__MASK = 0x0003ffff # macro -A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT = 0 # macro -A6XX_CP_PROTECT_REG_MASK_LEN__MASK = 0x7ffc0000 # macro -A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT = 18 # macro -A6XX_CP_PROTECT_REG_READ = 0x80000000 # macro -REG_A6XX_CP_CONTEXT_SWITCH_CNTL = 0x000008a0 # macro -REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO = 0x000008a1 # macro -REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR = 0x000008a3 # macro -REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR = 0x000008a5 # macro -REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR = 0x000008a7 # macro -REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS = 0x000008ab # macro -# def REG_A6XX_CP_PERFCTR_CP_SEL(i0): # macro -# return (0x000008d0+0x1*i0) -# def REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0): # macro -# return (0x000008e0+0x1*i0) -REG_A6XX_CP_CRASH_SCRIPT_BASE = 0x00000900 # macro -REG_A6XX_CP_CRASH_DUMP_CNTL = 0x00000902 # macro -REG_A6XX_CP_CRASH_DUMP_STATUS = 0x00000903 # macro -REG_A6XX_CP_SQE_STAT_ADDR = 0x00000908 # macro -REG_A6XX_CP_SQE_STAT_DATA = 0x00000909 # macro -REG_A6XX_CP_DRAW_STATE_ADDR = 0x0000090a # macro -REG_A6XX_CP_DRAW_STATE_DATA = 0x0000090b # macro -REG_A6XX_CP_ROQ_DBG_ADDR = 0x0000090c # macro -REG_A6XX_CP_ROQ_DBG_DATA = 0x0000090d # macro -REG_A6XX_CP_MEM_POOL_DBG_ADDR = 0x0000090e # macro -REG_A6XX_CP_MEM_POOL_DBG_DATA = 0x0000090f # macro -REG_A6XX_CP_SQE_UCODE_DBG_ADDR = 0x00000910 # macro -REG_A6XX_CP_SQE_UCODE_DBG_DATA = 0x00000911 # macro -REG_A6XX_CP_IB1_BASE = 0x00000928 # macro -REG_A6XX_CP_IB1_REM_SIZE = 0x0000092a # macro -REG_A6XX_CP_IB2_BASE = 0x0000092b # macro -REG_A6XX_CP_IB2_REM_SIZE = 0x0000092d # macro -REG_A6XX_CP_SDS_BASE = 0x0000092e # macro -REG_A6XX_CP_SDS_REM_SIZE = 0x00000930 # macro -REG_A6XX_CP_MRB_BASE = 0x00000931 # macro -REG_A6XX_CP_MRB_REM_SIZE = 0x00000933 # macro -REG_A6XX_CP_VSD_BASE = 0x00000934 # macro -REG_A6XX_CP_ROQ_RB_STAT = 0x00000939 # macro -A6XX_CP_ROQ_RB_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_RB_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_IB1_STAT = 0x0000093a # macro -A6XX_CP_ROQ_IB1_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_IB1_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_IB2_STAT = 0x0000093b # macro -A6XX_CP_ROQ_IB2_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_IB2_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_SDS_STAT = 0x0000093c # macro -A6XX_CP_ROQ_SDS_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_SDS_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_MRB_STAT = 0x0000093d # macro -A6XX_CP_ROQ_MRB_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_MRB_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_VSD_STAT = 0x0000093e # macro -A6XX_CP_ROQ_VSD_STAT_RPTR__MASK = 0x000003ff # macro -A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT = 0 # macro -A6XX_CP_ROQ_VSD_STAT_WPTR__MASK = 0x03ff0000 # macro -A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT = 16 # macro -REG_A6XX_CP_IB1_DWORDS = 0x00000943 # macro -REG_A6XX_CP_IB2_DWORDS = 0x00000944 # macro -REG_A6XX_CP_SDS_DWORDS = 0x00000945 # macro -REG_A6XX_CP_MRB_DWORDS = 0x00000946 # macro -REG_A6XX_CP_VSD_DWORDS = 0x00000947 # macro -REG_A6XX_CP_ROQ_AVAIL_RB = 0x00000948 # macro -A6XX_CP_ROQ_AVAIL_RB_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_IB1 = 0x00000949 # macro -A6XX_CP_ROQ_AVAIL_IB1_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_IB2 = 0x0000094a # macro -A6XX_CP_ROQ_AVAIL_IB2_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_SDS = 0x0000094b # macro -A6XX_CP_ROQ_AVAIL_SDS_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_MRB = 0x0000094c # macro -A6XX_CP_ROQ_AVAIL_MRB_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT = 16 # macro -REG_A6XX_CP_ROQ_AVAIL_VSD = 0x0000094d # macro -A6XX_CP_ROQ_AVAIL_VSD_REM__MASK = 0xffff0000 # macro -A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT = 16 # macro -REG_A6XX_CP_ALWAYS_ON_COUNTER = 0x00000980 # macro -REG_A6XX_CP_AHB_CNTL = 0x0000098d # macro -REG_A6XX_CP_APERTURE_CNTL_HOST = 0x00000a00 # macro -REG_A7XX_CP_APERTURE_CNTL_HOST = 0x00000a00 # macro -A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK = 0x00003000 # macro -A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT = 12 # macro -A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK = 0x00000700 # macro -A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT = 8 # macro -A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK = 0x00000030 # macro -A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT = 4 # macro -REG_A6XX_CP_APERTURE_CNTL_CD = 0x00000a03 # macro -REG_A7XX_CP_APERTURE_CNTL_CD = 0x00000a03 # macro -A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK = 0x00003000 # macro -A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT = 12 # macro -A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK = 0x00000700 # macro -A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT = 8 # macro -A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK = 0x00000030 # macro -A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT = 4 # macro -REG_A7XX_CP_BV_PROTECT_STATUS = 0x00000a61 # macro -REG_A7XX_CP_BV_HW_FAULT = 0x00000a64 # macro -REG_A7XX_CP_BV_DRAW_STATE_ADDR = 0x00000a81 # macro -REG_A7XX_CP_BV_DRAW_STATE_DATA = 0x00000a82 # macro -REG_A7XX_CP_BV_ROQ_DBG_ADDR = 0x00000a83 # macro -REG_A7XX_CP_BV_ROQ_DBG_DATA = 0x00000a84 # macro -REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR = 0x00000a85 # macro -REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA = 0x00000a86 # macro -REG_A7XX_CP_BV_SQE_STAT_ADDR = 0x00000a87 # macro -REG_A7XX_CP_BV_SQE_STAT_DATA = 0x00000a88 # macro -REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR = 0x00000a96 # macro -REG_A7XX_CP_BV_MEM_POOL_DBG_DATA = 0x00000a97 # macro -REG_A7XX_CP_BV_RB_RPTR_ADDR = 0x00000a98 # macro -REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR = 0x00000a9a # macro -REG_A7XX_CP_RESOURCE_TBL_DBG_DATA = 0x00000a9b # macro -REG_A7XX_CP_BV_APRIV_CNTL = 0x00000ad0 # macro -REG_A7XX_CP_BV_CHICKEN_DBG = 0x00000ada # macro -REG_A7XX_CP_LPAC_DRAW_STATE_ADDR = 0x00000b0a # macro -REG_A7XX_CP_LPAC_DRAW_STATE_DATA = 0x00000b0b # macro -REG_A7XX_CP_LPAC_ROQ_DBG_ADDR = 0x00000b0c # macro -REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR = 0x00000b27 # macro -REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA = 0x00000b28 # macro -REG_A7XX_CP_SQE_AC_STAT_ADDR = 0x00000b29 # macro -REG_A7XX_CP_SQE_AC_STAT_DATA = 0x00000b2a # macro -REG_A7XX_CP_LPAC_APRIV_CNTL = 0x00000b31 # macro -REG_A6XX_CP_LPAC_PROG_FIFO_SIZE = 0x00000b34 # macro -REG_A7XX_CP_LPAC_ROQ_DBG_DATA = 0x00000b35 # macro -REG_A7XX_CP_LPAC_FIFO_DBG_DATA = 0x00000b36 # macro -REG_A7XX_CP_LPAC_FIFO_DBG_ADDR = 0x00000b40 # macro -REG_A6XX_CP_LPAC_SQE_CNTL = 0x00000b81 # macro -REG_A6XX_CP_LPAC_SQE_INSTR_BASE = 0x00000b82 # macro -REG_A7XX_CP_AQE_INSTR_BASE_0 = 0x00000b70 # macro -REG_A7XX_CP_AQE_INSTR_BASE_1 = 0x00000b72 # macro -REG_A7XX_CP_AQE_APRIV_CNTL = 0x00000b78 # macro -REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 = 0x00000ba8 # macro -REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 = 0x00000ba9 # macro -REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 = 0x00000bac # macro -REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 = 0x00000bad # macro -REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 = 0x00000bb0 # macro -REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 = 0x00000bb1 # macro -REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 = 0x00000bb4 # macro -REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 = 0x00000bb5 # macro -REG_A7XX_CP_AQE_STAT_ADDR_0 = 0x00000bb8 # macro -REG_A7XX_CP_AQE_STAT_ADDR_1 = 0x00000bb9 # macro -REG_A7XX_CP_AQE_STAT_DATA_0 = 0x00000bbc # macro -REG_A7XX_CP_AQE_STAT_DATA_1 = 0x00000bbd # macro -REG_A6XX_VSC_ADDR_MODE_CNTL = 0x00000c01 # macro -REG_A6XX_RBBM_GPR0_CNTL = 0x00000018 # macro -REG_A6XX_RBBM_INT_0_STATUS = 0x00000201 # macro -REG_A6XX_RBBM_STATUS = 0x00000210 # macro -A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB = 0x00800000 # macro -A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP = 0x00400000 # macro -A6XX_RBBM_STATUS_HLSQ_BUSY = 0x00200000 # macro -A6XX_RBBM_STATUS_VSC_BUSY = 0x00100000 # macro -A6XX_RBBM_STATUS_TPL1_BUSY = 0x00080000 # macro -A6XX_RBBM_STATUS_SP_BUSY = 0x00040000 # macro -A6XX_RBBM_STATUS_UCHE_BUSY = 0x00020000 # macro -A6XX_RBBM_STATUS_VPC_BUSY = 0x00010000 # macro -A6XX_RBBM_STATUS_VFD_BUSY = 0x00008000 # macro -A6XX_RBBM_STATUS_TESS_BUSY = 0x00004000 # macro -A6XX_RBBM_STATUS_PC_VSD_BUSY = 0x00002000 # macro -A6XX_RBBM_STATUS_PC_DCALL_BUSY = 0x00001000 # macro -A6XX_RBBM_STATUS_COM_DCOM_BUSY = 0x00000800 # macro -A6XX_RBBM_STATUS_LRZ_BUSY = 0x00000400 # macro -A6XX_RBBM_STATUS_A2D_BUSY = 0x00000200 # macro -A6XX_RBBM_STATUS_CCU_BUSY = 0x00000100 # macro -A6XX_RBBM_STATUS_RB_BUSY = 0x00000080 # macro -A6XX_RBBM_STATUS_RAS_BUSY = 0x00000040 # macro -A6XX_RBBM_STATUS_TSE_BUSY = 0x00000020 # macro -A6XX_RBBM_STATUS_VBIF_BUSY = 0x00000010 # macro -A6XX_RBBM_STATUS_GFX_DBGC_BUSY = 0x00000008 # macro -A6XX_RBBM_STATUS_CP_BUSY = 0x00000004 # macro -A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER = 0x00000002 # macro -A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER = 0x00000001 # macro -REG_A6XX_RBBM_STATUS1 = 0x00000211 # macro -REG_A6XX_RBBM_STATUS2 = 0x00000212 # macro -REG_A6XX_RBBM_STATUS3 = 0x00000213 # macro -A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT = 0x01000000 # macro -REG_A6XX_RBBM_VBIF_GX_RESET_STATUS = 0x00000215 # macro -REG_A7XX_RBBM_CLOCK_MODE_CP = 0x00000260 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ = 0x00000284 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS = 0x00000285 # macro -REG_A7XX_RBBM_CLOCK_MODE2_GRAS = 0x00000286 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_VFD = 0x00000287 # macro -REG_A7XX_RBBM_CLOCK_MODE_BV_GPC = 0x00000288 # macro -REG_A7XX_RBBM_SW_FUSE_INT_STATUS = 0x000002c0 # macro -REG_A7XX_RBBM_SW_FUSE_INT_MASK = 0x000002c1 # macro -# def REG_A6XX_RBBM_PERFCTR_CP(i0): # macro -# return (0x00000400+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_RBBM(i0): # macro -# return (0x0000041c+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_PC(i0): # macro -# return (0x00000424+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_VFD(i0): # macro -# return (0x00000434+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_HLSQ(i0): # macro -# return (0x00000444+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_VPC(i0): # macro -# return (0x00000450+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_CCU(i0): # macro -# return (0x0000045c+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_TSE(i0): # macro -# return (0x00000466+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_RAS(i0): # macro -# return (0x0000046e+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_UCHE(i0): # macro -# return (0x00000476+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_TP(i0): # macro -# return (0x0000048e+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_SP(i0): # macro -# return (0x000004a6+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_RB(i0): # macro -# return (0x000004d6+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_VSC(i0): # macro -# return (0x000004e6+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_LRZ(i0): # macro -# return (0x000004ea+0x2*i0) -# def REG_A6XX_RBBM_PERFCTR_CMP(i0): # macro -# return (0x000004f2+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_CP(i0): # macro -# return (0x00000300+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_RBBM(i0): # macro -# return (0x0000031c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_PC(i0): # macro -# return (0x00000324+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_VFD(i0): # macro -# return (0x00000334+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_HLSQ(i0): # macro -# return (0x00000344+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_VPC(i0): # macro -# return (0x00000350+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_CCU(i0): # macro -# return (0x0000035c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_TSE(i0): # macro -# return (0x00000366+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_RAS(i0): # macro -# return (0x0000036e+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_UCHE(i0): # macro -# return (0x00000376+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_TP(i0): # macro -# return (0x0000038e+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_SP(i0): # macro -# return (0x000003a6+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_RB(i0): # macro -# return (0x000003d6+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_VSC(i0): # macro -# return (0x000003e6+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_LRZ(i0): # macro -# return (0x000003ea+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_CMP(i0): # macro -# return (0x000003f2+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_UFC(i0): # macro -# return (0x000003fa+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_HLSQ(i0): # macro -# return (0x00000410+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_CP(i0): # macro -# return (0x0000041c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_SP(i0): # macro -# return (0x0000042a+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_TP(i0): # macro -# return (0x00000442+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR2_UFC(i0): # macro -# return (0x0000044e+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_PC(i0): # macro -# return (0x00000460+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_VFD(i0): # macro -# return (0x00000470+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_VPC(i0): # macro -# return (0x00000480+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_TSE(i0): # macro -# return (0x0000048c+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_RAS(i0): # macro -# return (0x00000494+0x2*i0) -# def REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0): # macro -# return (0x0000049c+0x2*i0) -REG_A6XX_RBBM_PERFCTR_CNTL = 0x00000500 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 = 0x00000501 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 = 0x00000502 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 = 0x00000503 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 = 0x00000504 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO = 0x00000505 # macro -REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI = 0x00000506 # macro -# def REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0): # macro -# return (0x00000507+0x1*i0) -REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED = 0x0000050b # macro -REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD = 0x0000050e # macro -REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS = 0x0000050f # macro -REG_A6XX_RBBM_ISDB_CNT = 0x00000533 # macro -REG_A7XX_RBBM_NC_MODE_CNTL = 0x00000534 # macro -REG_A7XX_RBBM_SNAPSHOT_STATUS = 0x00000535 # macro -REG_A6XX_RBBM_PRIMCTR_0_LO = 0x00000540 # macro -REG_A6XX_RBBM_PRIMCTR_0_HI = 0x00000541 # macro -REG_A6XX_RBBM_PRIMCTR_1_LO = 0x00000542 # macro -REG_A6XX_RBBM_PRIMCTR_1_HI = 0x00000543 # macro -REG_A6XX_RBBM_PRIMCTR_2_LO = 0x00000544 # macro -REG_A6XX_RBBM_PRIMCTR_2_HI = 0x00000545 # macro -REG_A6XX_RBBM_PRIMCTR_3_LO = 0x00000546 # macro -REG_A6XX_RBBM_PRIMCTR_3_HI = 0x00000547 # macro -REG_A6XX_RBBM_PRIMCTR_4_LO = 0x00000548 # macro -REG_A6XX_RBBM_PRIMCTR_4_HI = 0x00000549 # macro -REG_A6XX_RBBM_PRIMCTR_5_LO = 0x0000054a # macro -REG_A6XX_RBBM_PRIMCTR_5_HI = 0x0000054b # macro -REG_A6XX_RBBM_PRIMCTR_6_LO = 0x0000054c # macro -REG_A6XX_RBBM_PRIMCTR_6_HI = 0x0000054d # macro -REG_A6XX_RBBM_PRIMCTR_7_LO = 0x0000054e # macro -REG_A6XX_RBBM_PRIMCTR_7_HI = 0x0000054f # macro -REG_A6XX_RBBM_PRIMCTR_8_LO = 0x00000550 # macro -REG_A6XX_RBBM_PRIMCTR_8_HI = 0x00000551 # macro -REG_A6XX_RBBM_PRIMCTR_9_LO = 0x00000552 # macro -REG_A6XX_RBBM_PRIMCTR_9_HI = 0x00000553 # macro -REG_A6XX_RBBM_PRIMCTR_10_LO = 0x00000554 # macro -REG_A6XX_RBBM_PRIMCTR_10_HI = 0x00000555 # macro -REG_A6XX_RBBM_SECVID_TRUST_CNTL = 0x0000f400 # macro -REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE = 0x0000f800 # macro -REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE = 0x0000f802 # macro -REG_A6XX_RBBM_SECVID_TSB_CNTL = 0x0000f803 # macro -REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL = 0x0000f810 # macro -REG_A7XX_RBBM_SECVID_TSB_STATUS = 0x0000fc00 # macro -REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL = 0x00000010 # macro -REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL = 0x00000011 # macro -REG_A6XX_RBBM_GBIF_HALT = 0x00000016 # macro -REG_A6XX_RBBM_GBIF_HALT_ACK = 0x00000017 # macro -REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD = 0x0000001c # macro -A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE = 0x00000001 # macro -REG_A7XX_RBBM_GBIF_HALT = 0x00000016 # macro -REG_A7XX_RBBM_GBIF_HALT_ACK = 0x00000017 # macro -REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL = 0x0000001f # macro -REG_A6XX_RBBM_INT_CLEAR_CMD = 0x00000037 # macro -REG_A6XX_RBBM_INT_0_MASK = 0x00000038 # macro -REG_A7XX_RBBM_INT_2_MASK = 0x0000003a # macro -REG_A6XX_RBBM_SP_HYST_CNT = 0x00000042 # macro -REG_A6XX_RBBM_SW_RESET_CMD = 0x00000043 # macro -REG_A6XX_RBBM_RAC_THRESHOLD_CNT = 0x00000044 # macro -REG_A6XX_RBBM_BLOCK_SW_RESET_CMD = 0x00000045 # macro -REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 = 0x00000046 # macro -REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL = 0x000000ad # macro -REG_A6XX_RBBM_CLOCK_CNTL = 0x000000ae # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP0 = 0x000000b0 # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP1 = 0x000000b1 # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP2 = 0x000000b2 # macro -REG_A6XX_RBBM_CLOCK_CNTL_SP3 = 0x000000b3 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP0 = 0x000000b4 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP1 = 0x000000b5 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP2 = 0x000000b6 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_SP3 = 0x000000b7 # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP0 = 0x000000b8 # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP1 = 0x000000b9 # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP2 = 0x000000ba # macro -REG_A6XX_RBBM_CLOCK_DELAY_SP3 = 0x000000bb # macro -REG_A6XX_RBBM_CLOCK_HYST_SP0 = 0x000000bc # macro -REG_A6XX_RBBM_CLOCK_HYST_SP1 = 0x000000bd # macro -REG_A6XX_RBBM_CLOCK_HYST_SP2 = 0x000000be # macro -REG_A6XX_RBBM_CLOCK_HYST_SP3 = 0x000000bf # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP0 = 0x000000c0 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP1 = 0x000000c1 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP2 = 0x000000c2 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TP3 = 0x000000c3 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP0 = 0x000000c4 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP1 = 0x000000c5 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP2 = 0x000000c6 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_TP3 = 0x000000c7 # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP0 = 0x000000c8 # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP1 = 0x000000c9 # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP2 = 0x000000ca # macro -REG_A6XX_RBBM_CLOCK_CNTL3_TP3 = 0x000000cb # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP0 = 0x000000cc # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP1 = 0x000000cd # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP2 = 0x000000ce # macro -REG_A6XX_RBBM_CLOCK_CNTL4_TP3 = 0x000000cf # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP0 = 0x000000d0 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP1 = 0x000000d1 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP2 = 0x000000d2 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TP3 = 0x000000d3 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP0 = 0x000000d4 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP1 = 0x000000d5 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP2 = 0x000000d6 # macro -REG_A6XX_RBBM_CLOCK_DELAY2_TP3 = 0x000000d7 # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP0 = 0x000000d8 # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP1 = 0x000000d9 # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP2 = 0x000000da # macro -REG_A6XX_RBBM_CLOCK_DELAY3_TP3 = 0x000000db # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP0 = 0x000000dc # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP1 = 0x000000dd # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP2 = 0x000000de # macro -REG_A6XX_RBBM_CLOCK_DELAY4_TP3 = 0x000000df # macro -REG_A6XX_RBBM_CLOCK_HYST_TP0 = 0x000000e0 # macro -REG_A6XX_RBBM_CLOCK_HYST_TP1 = 0x000000e1 # macro -REG_A6XX_RBBM_CLOCK_HYST_TP2 = 0x000000e2 # macro -REG_A6XX_RBBM_CLOCK_HYST_TP3 = 0x000000e3 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP0 = 0x000000e4 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP1 = 0x000000e5 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP2 = 0x000000e6 # macro -REG_A6XX_RBBM_CLOCK_HYST2_TP3 = 0x000000e7 # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP0 = 0x000000e8 # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP1 = 0x000000e9 # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP2 = 0x000000ea # macro -REG_A6XX_RBBM_CLOCK_HYST3_TP3 = 0x000000eb # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP0 = 0x000000ec # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP1 = 0x000000ed # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP2 = 0x000000ee # macro -REG_A6XX_RBBM_CLOCK_HYST4_TP3 = 0x000000ef # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB0 = 0x000000f0 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB1 = 0x000000f1 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB2 = 0x000000f2 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RB3 = 0x000000f3 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB0 = 0x000000f4 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB1 = 0x000000f5 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB2 = 0x000000f6 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RB3 = 0x000000f7 # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU0 = 0x000000f8 # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU1 = 0x000000f9 # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU2 = 0x000000fa # macro -REG_A6XX_RBBM_CLOCK_CNTL_CCU3 = 0x000000fb # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 = 0x00000100 # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 = 0x00000101 # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 = 0x00000102 # macro -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 = 0x00000103 # macro -REG_A6XX_RBBM_CLOCK_CNTL_RAC = 0x00000104 # macro -REG_A6XX_RBBM_CLOCK_CNTL2_RAC = 0x00000105 # macro -REG_A6XX_RBBM_CLOCK_DELAY_RAC = 0x00000106 # macro -REG_A6XX_RBBM_CLOCK_HYST_RAC = 0x00000107 # macro -REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM = 0x00000108 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM = 0x00000109 # macro -REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM = 0x0000010a # macro -REG_A6XX_RBBM_CLOCK_CNTL_UCHE = 0x0000010b # macro -REG_A6XX_RBBM_CLOCK_CNTL2_UCHE = 0x0000010c # macro -REG_A6XX_RBBM_CLOCK_CNTL3_UCHE = 0x0000010d # macro -REG_A6XX_RBBM_CLOCK_CNTL4_UCHE = 0x0000010e # macro -REG_A6XX_RBBM_CLOCK_DELAY_UCHE = 0x0000010f # macro -REG_A6XX_RBBM_CLOCK_HYST_UCHE = 0x00000110 # macro -REG_A6XX_RBBM_CLOCK_MODE_VFD = 0x00000111 # macro -REG_A6XX_RBBM_CLOCK_DELAY_VFD = 0x00000112 # macro -REG_A6XX_RBBM_CLOCK_HYST_VFD = 0x00000113 # macro -REG_A6XX_RBBM_CLOCK_MODE_GPC = 0x00000114 # macro -REG_A6XX_RBBM_CLOCK_DELAY_GPC = 0x00000115 # macro -REG_A6XX_RBBM_CLOCK_HYST_GPC = 0x00000116 # macro -REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 = 0x00000117 # macro -REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX = 0x00000118 # macro -REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX = 0x00000119 # macro -REG_A6XX_RBBM_CLOCK_HYST_GMU_GX = 0x0000011a # macro -REG_A6XX_RBBM_CLOCK_MODE_HLSQ = 0x0000011b # macro -REG_A6XX_RBBM_CLOCK_DELAY_HLSQ = 0x0000011c # macro -REG_A6XX_RBBM_CLOCK_HYST_HLSQ = 0x0000011d # macro -REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD = 0x0000011e # macro -REG_A7XX_RBBM_CGC_P2S_TRIG_CMD = 0x0000011f # macro -REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE = 0x00000120 # macro -REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE = 0x00000121 # macro -REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE = 0x00000122 # macro -REG_A7XX_RBBM_CGC_P2S_STATUS = 0x00000122 # macro -A7XX_RBBM_CGC_P2S_STATUS_TXDONE = 0x00000001 # macro -REG_A6XX_RBBM_CLOCK_CNTL_FCHE = 0x00000123 # macro -REG_A6XX_RBBM_CLOCK_DELAY_FCHE = 0x00000124 # macro -REG_A6XX_RBBM_CLOCK_HYST_FCHE = 0x00000125 # macro -REG_A6XX_RBBM_CLOCK_CNTL_MHUB = 0x00000126 # macro -REG_A6XX_RBBM_CLOCK_DELAY_MHUB = 0x00000127 # macro -REG_A6XX_RBBM_CLOCK_HYST_MHUB = 0x00000128 # macro -REG_A6XX_RBBM_CLOCK_DELAY_GLC = 0x00000129 # macro -REG_A6XX_RBBM_CLOCK_HYST_GLC = 0x0000012a # macro -REG_A6XX_RBBM_CLOCK_CNTL_GLC = 0x0000012b # macro -REG_A7XX_RBBM_CLOCK_HYST2_VFD = 0x0000012f # macro -REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL = 0x000005ff # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_A = 0x00000600 # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_B = 0x00000601 # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_C = 0x00000602 # macro -REG_A6XX_DBGC_CFG_DBGBUS_SEL_D = 0x00000603 # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK = 0x000000ff # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK = 0x0000ff00 # macro -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT = 8 # macro -REG_A6XX_DBGC_CFG_DBGBUS_CNTLT = 0x00000604 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 # macro -REG_A6XX_DBGC_CFG_DBGBUS_CNTLM = 0x00000605 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 # macro -A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000608 # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000609 # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000060a # macro -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000060b # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000060c # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000060d # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000060e # macro -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000060f # macro -REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000610 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 # macro -REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000611 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 # macro -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 # macro -REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000062f # macro -REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000630 # macro -# def REG_A6XX_VSC_PERFCTR_VSC_SEL(i0): # macro -# return (0x00000cd8+0x1*i0) -REG_A7XX_VSC_UNKNOWN_0CD8 = 0x00000cd8 # macro -A7XX_VSC_UNKNOWN_0CD8_BINNING = 0x00000001 # macro -REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE = 0x0000c800 # macro -REG_A6XX_HLSQ_DBG_READ_SEL = 0x0000d000 # macro -REG_A6XX_UCHE_ADDR_MODE_CNTL = 0x00000e00 # macro -REG_A6XX_UCHE_MODE_CNTL = 0x00000e01 # macro -REG_A6XX_UCHE_WRITE_RANGE_MAX = 0x00000e05 # macro -REG_A6XX_UCHE_WRITE_THRU_BASE = 0x00000e07 # macro -REG_A6XX_UCHE_TRAP_BASE = 0x00000e09 # macro -REG_A6XX_UCHE_GMEM_RANGE_MIN = 0x00000e0b # macro -REG_A6XX_UCHE_GMEM_RANGE_MAX = 0x00000e0d # macro -REG_A6XX_UCHE_CACHE_WAYS = 0x00000e17 # macro -REG_A6XX_UCHE_FILTER_CNTL = 0x00000e18 # macro -REG_A6XX_UCHE_CLIENT_PF = 0x00000e19 # macro -A6XX_UCHE_CLIENT_PF_PERFSEL__MASK = 0x000000ff # macro -A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT = 0 # macro -# def REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0): # macro -# return (0x00000e1c+0x1*i0) -REG_A6XX_UCHE_GBIF_GX_CONFIG = 0x00000e3a # macro -REG_A6XX_UCHE_CMDQ_CONFIG = 0x00000e3c # macro -REG_A6XX_VBIF_VERSION = 0x00003000 # macro -REG_A6XX_VBIF_CLKON = 0x00003001 # macro -A6XX_VBIF_CLKON_FORCE_ON_TESTBUS = 0x00000002 # macro -REG_A6XX_VBIF_GATE_OFF_WRREQ_EN = 0x0000302a # macro -REG_A6XX_VBIF_XIN_HALT_CTRL0 = 0x00003080 # macro -REG_A6XX_VBIF_XIN_HALT_CTRL1 = 0x00003081 # macro -REG_A6XX_VBIF_TEST_BUS_OUT_CTRL = 0x00003084 # macro -REG_A6XX_VBIF_TEST_BUS1_CTRL0 = 0x00003085 # macro -REG_A6XX_VBIF_TEST_BUS1_CTRL1 = 0x00003086 # macro -A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK = 0x0000000f # macro -A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT = 0 # macro -REG_A6XX_VBIF_TEST_BUS2_CTRL0 = 0x00003087 # macro -REG_A6XX_VBIF_TEST_BUS2_CTRL1 = 0x00003088 # macro -A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK = 0x000001ff # macro -A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT = 0 # macro -REG_A6XX_VBIF_TEST_BUS_OUT = 0x0000308c # macro -REG_A6XX_VBIF_PERF_CNT_SEL0 = 0x000030d0 # macro -REG_A6XX_VBIF_PERF_CNT_SEL1 = 0x000030d1 # macro -REG_A6XX_VBIF_PERF_CNT_SEL2 = 0x000030d2 # macro -REG_A6XX_VBIF_PERF_CNT_SEL3 = 0x000030d3 # macro -REG_A6XX_VBIF_PERF_CNT_LOW0 = 0x000030d8 # macro -REG_A6XX_VBIF_PERF_CNT_LOW1 = 0x000030d9 # macro -REG_A6XX_VBIF_PERF_CNT_LOW2 = 0x000030da # macro -REG_A6XX_VBIF_PERF_CNT_LOW3 = 0x000030db # macro -REG_A6XX_VBIF_PERF_CNT_HIGH0 = 0x000030e0 # macro -REG_A6XX_VBIF_PERF_CNT_HIGH1 = 0x000030e1 # macro -REG_A6XX_VBIF_PERF_CNT_HIGH2 = 0x000030e2 # macro -REG_A6XX_VBIF_PERF_CNT_HIGH3 = 0x000030e3 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_EN0 = 0x00003100 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_EN1 = 0x00003101 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_EN2 = 0x00003102 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 = 0x00003110 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 = 0x00003111 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 = 0x00003112 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 = 0x00003118 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 = 0x00003119 # macro -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 = 0x0000311a # macro -REG_A6XX_GBIF_SCACHE_CNTL0 = 0x00003c01 # macro -REG_A6XX_GBIF_SCACHE_CNTL1 = 0x00003c02 # macro -REG_A6XX_GBIF_QSB_SIDE0 = 0x00003c03 # macro -REG_A6XX_GBIF_QSB_SIDE1 = 0x00003c04 # macro -REG_A6XX_GBIF_QSB_SIDE2 = 0x00003c05 # macro -REG_A6XX_GBIF_QSB_SIDE3 = 0x00003c06 # macro -REG_A6XX_GBIF_HALT = 0x00003c45 # macro -REG_A6XX_GBIF_HALT_ACK = 0x00003c46 # macro -REG_A6XX_GBIF_PERF_PWR_CNT_EN = 0x00003cc0 # macro -REG_A6XX_GBIF_PERF_PWR_CNT_CLR = 0x00003cc1 # macro -REG_A6XX_GBIF_PERF_CNT_SEL = 0x00003cc2 # macro -REG_A6XX_GBIF_PERF_PWR_CNT_SEL = 0x00003cc3 # macro -REG_A6XX_GBIF_PERF_CNT_LOW0 = 0x00003cc4 # macro -REG_A6XX_GBIF_PERF_CNT_LOW1 = 0x00003cc5 # macro -REG_A6XX_GBIF_PERF_CNT_LOW2 = 0x00003cc6 # macro -REG_A6XX_GBIF_PERF_CNT_LOW3 = 0x00003cc7 # macro -REG_A6XX_GBIF_PERF_CNT_HIGH0 = 0x00003cc8 # macro -REG_A6XX_GBIF_PERF_CNT_HIGH1 = 0x00003cc9 # macro -REG_A6XX_GBIF_PERF_CNT_HIGH2 = 0x00003cca # macro -REG_A6XX_GBIF_PERF_CNT_HIGH3 = 0x00003ccb # macro -REG_A6XX_GBIF_PWR_CNT_LOW0 = 0x00003ccc # macro -REG_A6XX_GBIF_PWR_CNT_LOW1 = 0x00003ccd # macro -REG_A6XX_GBIF_PWR_CNT_LOW2 = 0x00003cce # macro -REG_A6XX_GBIF_PWR_CNT_HIGH0 = 0x00003ccf # macro -REG_A6XX_GBIF_PWR_CNT_HIGH1 = 0x00003cd0 # macro -REG_A6XX_GBIF_PWR_CNT_HIGH2 = 0x00003cd1 # macro -REG_A6XX_VSC_DBG_ECO_CNTL = 0x00000c00 # macro -REG_A6XX_VSC_BIN_SIZE = 0x00000c02 # macro -A6XX_VSC_BIN_SIZE_WIDTH__MASK = 0x000000ff # macro -A6XX_VSC_BIN_SIZE_WIDTH__SHIFT = 0 # macro -A6XX_VSC_BIN_SIZE_HEIGHT__MASK = 0x0001ff00 # macro -A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT = 8 # macro -REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS = 0x00000c03 # macro -REG_A6XX_VSC_BIN_COUNT = 0x00000c06 # macro -A6XX_VSC_BIN_COUNT_NX__MASK = 0x000007fe # macro -A6XX_VSC_BIN_COUNT_NX__SHIFT = 1 # macro -A6XX_VSC_BIN_COUNT_NY__MASK = 0x001ff800 # macro -A6XX_VSC_BIN_COUNT_NY__SHIFT = 11 # macro -# def REG_A6XX_VSC_PIPE_CONFIG(i0): # macro -# return (0x00000c10+0x1*i0) -A6XX_VSC_PIPE_CONFIG_REG_X__MASK = 0x000003ff # macro -A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT = 0 # macro -A6XX_VSC_PIPE_CONFIG_REG_Y__MASK = 0x000ffc00 # macro -A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT = 10 # macro -A6XX_VSC_PIPE_CONFIG_REG_W__MASK = 0x03f00000 # macro -A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT = 20 # macro -A6XX_VSC_PIPE_CONFIG_REG_H__MASK = 0xfc000000 # macro -A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT = 26 # macro -REG_A6XX_VSC_PRIM_STRM_ADDRESS = 0x00000c30 # macro -REG_A6XX_VSC_PRIM_STRM_PITCH = 0x00000c32 # macro -REG_A6XX_VSC_PRIM_STRM_LIMIT = 0x00000c33 # macro -REG_A6XX_VSC_DRAW_STRM_ADDRESS = 0x00000c34 # macro -REG_A6XX_VSC_DRAW_STRM_PITCH = 0x00000c36 # macro -REG_A6XX_VSC_DRAW_STRM_LIMIT = 0x00000c37 # macro -# def REG_A6XX_VSC_STATE(i0): # macro -# return (0x00000c38+0x1*i0) -# def REG_A6XX_VSC_PRIM_STRM_SIZE(i0): # macro -# return (0x00000c58+0x1*i0) -# def REG_A6XX_VSC_DRAW_STRM_SIZE(i0): # macro -# return (0x00000c78+0x1*i0) -REG_A7XX_VSC_UNKNOWN_0D08 = 0x00000d08 # macro -REG_A7XX_UCHE_UNKNOWN_0E10 = 0x00000e10 # macro -REG_A7XX_UCHE_UNKNOWN_0E11 = 0x00000e11 # macro -REG_A6XX_UCHE_UNKNOWN_0E12 = 0x00000e12 # macro -REG_A6XX_GRAS_CL_CNTL = 0x00008000 # macro -A6XX_GRAS_CL_CNTL_CLIP_DISABLE = 0x00000001 # macro -A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE = 0x00000002 # macro -A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE = 0x00000004 # macro -A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE = 0x00000020 # macro -A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z = 0x00000040 # macro -A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE = 0x00000080 # macro -A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE = 0x00000100 # macro -A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE = 0x00000200 # macro -REG_A6XX_GRAS_VS_CL_CNTL = 0x00008001 # macro -A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro -A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro -REG_A6XX_GRAS_DS_CL_CNTL = 0x00008002 # macro -A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro -A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro -REG_A6XX_GRAS_GS_CL_CNTL = 0x00008003 # macro -A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro -A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro -REG_A6XX_GRAS_MAX_LAYER_INDEX = 0x00008004 # macro -REG_A6XX_GRAS_CNTL = 0x00008005 # macro -A6XX_GRAS_CNTL_IJ_PERSP_PIXEL = 0x00000001 # macro -A6XX_GRAS_CNTL_IJ_PERSP_CENTROID = 0x00000002 # macro -A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE = 0x00000004 # macro -A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL = 0x00000008 # macro -A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID = 0x00000010 # macro -A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 # macro -A6XX_GRAS_CNTL_COORD_MASK__MASK = 0x000003c0 # macro -A6XX_GRAS_CNTL_COORD_MASK__SHIFT = 6 # macro -A6XX_GRAS_CNTL_UNK10 = 0x00000400 # macro -A6XX_GRAS_CNTL_UNK11 = 0x00000800 # macro -REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ = 0x00008006 # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK = 0x000001ff # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT = 0 # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK = 0x0007fc00 # macro -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT = 10 # macro -REG_A7XX_GRAS_UNKNOWN_8007 = 0x00008007 # macro -REG_A7XX_GRAS_UNKNOWN_8008 = 0x00008008 # macro -REG_A7XX_GRAS_UNKNOWN_8009 = 0x00008009 # macro -REG_A7XX_GRAS_UNKNOWN_800A = 0x0000800a # macro -REG_A7XX_GRAS_UNKNOWN_800B = 0x0000800b # macro -REG_A7XX_GRAS_UNKNOWN_800C = 0x0000800c # macro -# def REG_A6XX_GRAS_CL_VPORT(i0): # macro -# return (0x00008010+0x6*i0) -A6XX_GRAS_CL_VPORT_XOFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_XSCALE__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_XSCALE__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_YOFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_YSCALE__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_YSCALE__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_ZOFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT = 0 # macro -A6XX_GRAS_CL_VPORT_ZSCALE__MASK = 0xffffffff # macro -A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT = 0 # macro -# def REG_A6XX_GRAS_CL_Z_CLAMP(i0): # macro -# return (0x00008070+0x2*i0) -A6XX_GRAS_CL_Z_CLAMP_MIN__MASK = 0xffffffff # macro -A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT = 0 # macro -A6XX_GRAS_CL_Z_CLAMP_MAX__MASK = 0xffffffff # macro -A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_CNTL = 0x00008090 # macro -A6XX_GRAS_SU_CNTL_CULL_FRONT = 0x00000001 # macro -A6XX_GRAS_SU_CNTL_CULL_BACK = 0x00000002 # macro -A6XX_GRAS_SU_CNTL_FRONT_CW = 0x00000004 # macro -A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK = 0x000007f8 # macro -A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT = 3 # macro -A6XX_GRAS_SU_CNTL_POLY_OFFSET = 0x00000800 # macro -A6XX_GRAS_SU_CNTL_UNK12 = 0x00001000 # macro -A6XX_GRAS_SU_CNTL_LINE_MODE__MASK = 0x00002000 # macro -A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT = 13 # macro -A6XX_GRAS_SU_CNTL_UNK15__MASK = 0x00018000 # macro -A6XX_GRAS_SU_CNTL_UNK15__SHIFT = 15 # macro -A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE = 0x00020000 # macro -A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR = 0x00040000 # macro -A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR = 0x00080000 # macro -A6XX_GRAS_SU_CNTL_UNK20__MASK = 0x00700000 # macro -A6XX_GRAS_SU_CNTL_UNK20__SHIFT = 20 # macro -REG_A6XX_GRAS_SU_POINT_MINMAX = 0x00008091 # macro -A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK = 0x0000ffff # macro -A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT = 0 # macro -A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK = 0xffff0000 # macro -A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT = 16 # macro -REG_A6XX_GRAS_SU_POINT_SIZE = 0x00008092 # macro -A6XX_GRAS_SU_POINT_SIZE__MASK = 0x0000ffff # macro -A6XX_GRAS_SU_POINT_SIZE__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL = 0x00008094 # macro -A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 # macro -A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE = 0x00008095 # macro -A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK = 0xffffffff # macro -A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET = 0x00008096 # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK = 0xffffffff # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP = 0x00008097 # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK = 0xffffffff # macro -A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT = 0 # macro -REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO = 0x00008098 # macro -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 # macro -REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL = 0x00008099 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK = 0x00000006 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT = 1 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN = 0x00000008 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK = 0x00000030 # macro -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT = 4 # macro -REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL = 0x0000809a # macro -A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 = 0x00000001 # macro -A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN = 0x00000002 # macro -REG_A6XX_GRAS_VS_LAYER_CNTL = 0x0000809b # macro -A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro -A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro -REG_A6XX_GRAS_GS_LAYER_CNTL = 0x0000809c # macro -A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro -A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro -REG_A6XX_GRAS_DS_LAYER_CNTL = 0x0000809d # macro -A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro -A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro -REG_A6XX_GRAS_SC_CNTL = 0x000080a0 # macro -A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000007 # macro -A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 0 # macro -A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK = 0x00000018 # macro -A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT = 3 # macro -A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK = 0x00000020 # macro -A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT = 5 # macro -A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK = 0x000000c0 # macro -A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT = 6 # macro -A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK = 0x00000100 # macro -A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT = 8 # macro -A6XX_GRAS_SC_CNTL_UNK9 = 0x00000200 # macro -A6XX_GRAS_SC_CNTL_ROTATION__MASK = 0x00000c00 # macro -A6XX_GRAS_SC_CNTL_ROTATION__SHIFT = 10 # macro -A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN = 0x00001000 # macro -REG_A6XX_GRAS_BIN_CONTROL = 0x000080a1 # macro -A6XX_GRAS_BIN_CONTROL_BINW__MASK = 0x0000003f # macro -A6XX_GRAS_BIN_CONTROL_BINW__SHIFT = 0 # macro -A6XX_GRAS_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro -A6XX_GRAS_BIN_CONTROL_BINH__SHIFT = 8 # macro -A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro -A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro -A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro -A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 # macro -A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 # macro -A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro -A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro -A6XX_GRAS_BIN_CONTROL_UNK27 = 0x08000000 # macro -REG_A6XX_GRAS_RAS_MSAA_CNTL = 0x000080a2 # macro -A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_GRAS_RAS_MSAA_CNTL_UNK2 = 0x00000004 # macro -A6XX_GRAS_RAS_MSAA_CNTL_UNK3 = 0x00000008 # macro -REG_A6XX_GRAS_DEST_MSAA_CNTL = 0x000080a3 # macro -A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro -REG_A6XX_GRAS_SAMPLE_CONFIG = 0x000080a4 # macro -A6XX_GRAS_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro -A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro -REG_A6XX_GRAS_SAMPLE_LOCATION_0 = 0x000080a5 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_GRAS_SAMPLE_LOCATION_1 = 0x000080a6 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A7XX_GRAS_UNKNOWN_80A7 = 0x000080a7 # macro -REG_A6XX_GRAS_UNKNOWN_80AF = 0x000080af # macro -# def REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0): # macro -# return (0x000080b0+0x2*i0) -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT = 16 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT = 16 # macro -# def REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0): # macro -# return (0x000080d0+0x2*i0) -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT = 16 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK = 0x0000ffff # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK = 0xffff0000 # macro -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL = 0x000080f0 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK = 0x00003fff # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR = 0x000080f1 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK = 0x00003fff # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT = 16 # macro -REG_A7XX_GRAS_UNKNOWN_80F4 = 0x000080f4 # macro -REG_A7XX_GRAS_UNKNOWN_80F5 = 0x000080f5 # macro -REG_A7XX_GRAS_UNKNOWN_80F6 = 0x000080f6 # macro -REG_A7XX_GRAS_UNKNOWN_80F8 = 0x000080f8 # macro -REG_A7XX_GRAS_UNKNOWN_80F9 = 0x000080f9 # macro -REG_A7XX_GRAS_UNKNOWN_80FA = 0x000080fa # macro -REG_A6XX_GRAS_LRZ_CNTL = 0x00008100 # macro -A6XX_GRAS_LRZ_CNTL_ENABLE = 0x00000001 # macro -A6XX_GRAS_LRZ_CNTL_LRZ_WRITE = 0x00000002 # macro -A6XX_GRAS_LRZ_CNTL_GREATER = 0x00000004 # macro -A6XX_GRAS_LRZ_CNTL_FC_ENABLE = 0x00000008 # macro -A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE = 0x00000010 # macro -A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE = 0x00000020 # macro -A6XX_GRAS_LRZ_CNTL_DIR__MASK = 0x000000c0 # macro -A6XX_GRAS_LRZ_CNTL_DIR__SHIFT = 6 # macro -A6XX_GRAS_LRZ_CNTL_DIR_WRITE = 0x00000100 # macro -A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR = 0x00000200 # macro -A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK = 0x00003800 # macro -A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT = 11 # macro -REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL = 0x00008101 # macro -A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID = 0x00000001 # macro -A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000006 # macro -A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 1 # macro -REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 = 0x00008102 # macro -A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT = 0 # macro -REG_A6XX_GRAS_LRZ_BUFFER_BASE = 0x00008103 # macro -REG_A6XX_GRAS_LRZ_BUFFER_PITCH = 0x00008105 # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK = 0x000000ff # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 # macro -A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 # macro -REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE = 0x00008106 # macro -REG_A6XX_GRAS_SAMPLE_CNTL = 0x00008109 # macro -A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 # macro -REG_A6XX_GRAS_LRZ_DEPTH_VIEW = 0x0000810a # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK = 0x000007ff # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT = 0 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK = 0x07ff0000 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT = 16 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK = 0xf0000000 # macro -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT = 28 # macro -REG_A7XX_GRAS_LRZ_CNTL2 = 0x0000810b # macro -A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR = 0x00000001 # macro -A7XX_GRAS_LRZ_CNTL2_FC_ENABLE = 0x00000002 # macro -REG_A6XX_GRAS_UNKNOWN_8110 = 0x00008110 # macro -REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 = 0x00008111 # macro -A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK = 0xffffffff # macro -A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT = 0 # macro -REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO = 0x00008113 # macro -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 # macro -REG_A7XX_GRAS_UNKNOWN_8120 = 0x00008120 # macro -REG_A7XX_GRAS_UNKNOWN_8121 = 0x00008121 # macro -REG_A6XX_GRAS_2D_BLIT_CNTL = 0x00008400 # macro -A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 # macro -A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT = 0 # macro -A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT = 4 # macro -A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 # macro -A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 # macro -A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 # macro -A6XX_GRAS_2D_BLIT_CNTL_SCISSOR = 0x00010000 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT = 17 # macro -A6XX_GRAS_2D_BLIT_CNTL_D24S8 = 0x00080000 # macro -A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 # macro -A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT = 20 # macro -A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 # macro -A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT = 24 # macro -A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 # macro -A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 # macro -A6XX_GRAS_2D_BLIT_CNTL_UNK30 = 0x40000000 # macro -REG_A6XX_GRAS_2D_SRC_TL_X = 0x00008401 # macro -A6XX_GRAS_2D_SRC_TL_X__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_TL_X__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_SRC_BR_X = 0x00008402 # macro -A6XX_GRAS_2D_SRC_BR_X__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_BR_X__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_SRC_TL_Y = 0x00008403 # macro -A6XX_GRAS_2D_SRC_TL_Y__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_TL_Y__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_SRC_BR_Y = 0x00008404 # macro -A6XX_GRAS_2D_SRC_BR_Y__MASK = 0x01ffff00 # macro -A6XX_GRAS_2D_SRC_BR_Y__SHIFT = 8 # macro -REG_A6XX_GRAS_2D_DST_TL = 0x00008405 # macro -A6XX_GRAS_2D_DST_TL_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_DST_TL_X__SHIFT = 0 # macro -A6XX_GRAS_2D_DST_TL_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_DST_TL_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_2D_DST_BR = 0x00008406 # macro -A6XX_GRAS_2D_DST_BR_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_DST_BR_X__SHIFT = 0 # macro -A6XX_GRAS_2D_DST_BR_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_DST_BR_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_2D_UNKNOWN_8407 = 0x00008407 # macro -REG_A6XX_GRAS_2D_UNKNOWN_8408 = 0x00008408 # macro -REG_A6XX_GRAS_2D_UNKNOWN_8409 = 0x00008409 # macro -REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 = 0x0000840a # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT = 0 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 = 0x0000840b # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK = 0x00003fff # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT = 0 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK = 0x3fff0000 # macro -A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT = 16 # macro -REG_A6XX_GRAS_DBG_ECO_CNTL = 0x00008600 # macro -A6XX_GRAS_DBG_ECO_CNTL_UNK7 = 0x00000080 # macro -A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS = 0x00000800 # macro -REG_A6XX_GRAS_ADDR_MODE_CNTL = 0x00008601 # macro -REG_A7XX_GRAS_NC_MODE_CNTL = 0x00008602 # macro -# def REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0): # macro -# return (0x00008610+0x1*i0) -# def REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0): # macro -# return (0x00008614+0x1*i0) -# def REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0): # macro -# return (0x00008618+0x1*i0) -REG_A6XX_RB_BIN_CONTROL = 0x00008800 # macro -A6XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f # macro -A6XX_RB_BIN_CONTROL_BINW__SHIFT = 0 # macro -A6XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro -A6XX_RB_BIN_CONTROL_BINH__SHIFT = 8 # macro -A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro -A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro -A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro -A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 # macro -A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 # macro -A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro -A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro -REG_A7XX_RB_BIN_CONTROL = 0x00008800 # macro -A7XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f # macro -A7XX_RB_BIN_CONTROL_BINW__SHIFT = 0 # macro -A7XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro -A7XX_RB_BIN_CONTROL_BINH__SHIFT = 8 # macro -A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro -A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro -A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro -A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro -A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro -REG_A6XX_RB_RENDER_CNTL = 0x00008801 # macro -A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000038 # macro -A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 3 # macro -A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 # macro -A6XX_RB_RENDER_CNTL_BINNING = 0x00000080 # macro -A6XX_RB_RENDER_CNTL_UNK8__MASK = 0x00000700 # macro -A6XX_RB_RENDER_CNTL_UNK8__SHIFT = 8 # macro -A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 # macro -A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 # macro -A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 # macro -A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 # macro -A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 # macro -A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 # macro -A6XX_RB_RENDER_CNTL_FLAG_DEPTH = 0x00004000 # macro -A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK = 0x00ff0000 # macro -A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT = 16 # macro -REG_A7XX_RB_RENDER_CNTL = 0x00008801 # macro -A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 # macro -A7XX_RB_RENDER_CNTL_BINNING = 0x00000080 # macro -A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 # macro -A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 # macro -A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 # macro -A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 # macro -A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 # macro -A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 # macro -REG_A7XX_GRAS_SU_RENDER_CNTL = 0x00008116 # macro -A7XX_GRAS_SU_RENDER_CNTL_BINNING = 0x00000080 # macro -REG_A6XX_RB_RAS_MSAA_CNTL = 0x00008802 # macro -A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_RB_RAS_MSAA_CNTL_UNK2 = 0x00000004 # macro -A6XX_RB_RAS_MSAA_CNTL_UNK3 = 0x00000008 # macro -REG_A6XX_RB_DEST_MSAA_CNTL = 0x00008803 # macro -A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro -REG_A6XX_RB_SAMPLE_CONFIG = 0x00008804 # macro -A6XX_RB_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro -A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro -REG_A6XX_RB_SAMPLE_LOCATION_0 = 0x00008805 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_RB_SAMPLE_LOCATION_1 = 0x00008806 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_RB_RENDER_CONTROL0 = 0x00008809 # macro -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL = 0x00000001 # macro -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID = 0x00000002 # macro -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE = 0x00000004 # macro -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL = 0x00000008 # macro -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID = 0x00000010 # macro -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE = 0x00000020 # macro -A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK = 0x000003c0 # macro -A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT = 6 # macro -A6XX_RB_RENDER_CONTROL0_UNK10 = 0x00000400 # macro -REG_A6XX_RB_RENDER_CONTROL1 = 0x0000880a # macro -A6XX_RB_RENDER_CONTROL1_SAMPLEMASK = 0x00000001 # macro -A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE = 0x00000002 # macro -A6XX_RB_RENDER_CONTROL1_FACENESS = 0x00000004 # macro -A6XX_RB_RENDER_CONTROL1_SAMPLEID = 0x00000008 # macro -A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK = 0x00000030 # macro -A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT = 4 # macro -A6XX_RB_RENDER_CONTROL1_CENTERRHW = 0x00000040 # macro -A6XX_RB_RENDER_CONTROL1_LINELENGTHEN = 0x00000080 # macro -A6XX_RB_RENDER_CONTROL1_FOVEATION = 0x00000100 # macro -REG_A6XX_RB_FS_OUTPUT_CNTL0 = 0x0000880b # macro -A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 # macro -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z = 0x00000002 # macro -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK = 0x00000004 # macro -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF = 0x00000008 # macro -REG_A6XX_RB_FS_OUTPUT_CNTL1 = 0x0000880c # macro -A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f # macro -A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 # macro -REG_A6XX_RB_RENDER_COMPONENTS = 0x0000880d # macro -A6XX_RB_RENDER_COMPONENTS_RT0__MASK = 0x0000000f # macro -A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT = 0 # macro -A6XX_RB_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 # macro -A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT = 4 # macro -A6XX_RB_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 # macro -A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT = 8 # macro -A6XX_RB_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 # macro -A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT = 12 # macro -A6XX_RB_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 # macro -A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT = 16 # macro -A6XX_RB_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 # macro -A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT = 20 # macro -A6XX_RB_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 # macro -A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT = 24 # macro -A6XX_RB_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 # macro -A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT = 28 # macro -REG_A6XX_RB_DITHER_CNTL = 0x0000880e # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 # macro -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 # macro -REG_A6XX_RB_SRGB_CNTL = 0x0000880f # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT0 = 0x00000001 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT1 = 0x00000002 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT2 = 0x00000004 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT3 = 0x00000008 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT4 = 0x00000010 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT5 = 0x00000020 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT6 = 0x00000040 # macro -A6XX_RB_SRGB_CNTL_SRGB_MRT7 = 0x00000080 # macro -REG_A6XX_RB_SAMPLE_CNTL = 0x00008810 # macro -A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 # macro -REG_A6XX_RB_UNKNOWN_8811 = 0x00008811 # macro -REG_A7XX_RB_UNKNOWN_8812 = 0x00008812 # macro -REG_A6XX_RB_UNKNOWN_8818 = 0x00008818 # macro -REG_A6XX_RB_UNKNOWN_8819 = 0x00008819 # macro -REG_A6XX_RB_UNKNOWN_881A = 0x0000881a # macro -REG_A6XX_RB_UNKNOWN_881B = 0x0000881b # macro -REG_A6XX_RB_UNKNOWN_881C = 0x0000881c # macro -REG_A6XX_RB_UNKNOWN_881D = 0x0000881d # macro -REG_A6XX_RB_UNKNOWN_881E = 0x0000881e # macro -# def REG_A6XX_RB_MRT(i0): # macro -# return (0x00008820+0x8*i0) -A6XX_RB_MRT_CONTROL_BLEND = 0x00000001 # macro -A6XX_RB_MRT_CONTROL_BLEND2 = 0x00000002 # macro -A6XX_RB_MRT_CONTROL_ROP_ENABLE = 0x00000004 # macro -A6XX_RB_MRT_CONTROL_ROP_CODE__MASK = 0x00000078 # macro -A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT = 3 # macro -A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK = 0x00000780 # macro -A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT = 7 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK = 0x0000001f # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT = 0 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK = 0x000000e0 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT = 5 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK = 0x00001f00 # macro -A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT = 8 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK = 0x001f0000 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT = 16 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK = 0x00e00000 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT = 21 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK = 0x1f000000 # macro -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT = 24 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 # macro -A6XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 # macro -A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 # macro -A7XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 # macro -A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN = 0x00000800 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 # macro -A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 # macro -A6XX_RB_MRT_PITCH__MASK = 0xffffffff # macro -A6XX_RB_MRT_PITCH__SHIFT = 0 # macro -A6XX_RB_MRT_ARRAY_PITCH__MASK = 0xffffffff # macro -A6XX_RB_MRT_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_RED_F32 = 0x00008860 # macro -A6XX_RB_BLEND_RED_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_RED_F32__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_GREEN_F32 = 0x00008861 # macro -A6XX_RB_BLEND_GREEN_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_GREEN_F32__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_BLUE_F32 = 0x00008862 # macro -A6XX_RB_BLEND_BLUE_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_BLUE_F32__SHIFT = 0 # macro -REG_A6XX_RB_BLEND_ALPHA_F32 = 0x00008863 # macro -A6XX_RB_BLEND_ALPHA_F32__MASK = 0xffffffff # macro -A6XX_RB_BLEND_ALPHA_F32__SHIFT = 0 # macro -REG_A6XX_RB_ALPHA_CONTROL = 0x00008864 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK = 0x000000ff # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT = 0 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST = 0x00000100 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK = 0x00000e00 # macro -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT = 9 # macro -REG_A6XX_RB_BLEND_CNTL = 0x00008865 # macro -A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff # macro -A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 # macro -A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND = 0x00000100 # macro -A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 # macro -A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 # macro -A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE = 0x00000800 # macro -A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK = 0xffff0000 # macro -A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT = 16 # macro -REG_A6XX_RB_DEPTH_PLANE_CNTL = 0x00008870 # macro -A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 # macro -A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 # macro -REG_A6XX_RB_DEPTH_CNTL = 0x00008871 # macro -A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 # macro -A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE = 0x00000002 # macro -A6XX_RB_DEPTH_CNTL_ZFUNC__MASK = 0x0000001c # macro -A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT = 2 # macro -A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE = 0x00000020 # macro -A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE = 0x00000040 # macro -A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE = 0x00000080 # macro -REG_A6XX_GRAS_SU_DEPTH_CNTL = 0x00008114 # macro -A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 # macro -REG_A6XX_RB_DEPTH_BUFFER_INFO = 0x00008872 # macro -A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 # macro -A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 # macro -REG_A7XX_RB_DEPTH_BUFFER_INFO = 0x00008872 # macro -A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro -A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro -A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 # macro -A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 # macro -A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK = 0x00000060 # macro -A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT = 5 # macro -A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN = 0x00000080 # macro -REG_A6XX_RB_DEPTH_BUFFER_PITCH = 0x00008873 # macro -A6XX_RB_DEPTH_BUFFER_PITCH__MASK = 0x00003fff # macro -A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH = 0x00008874 # macro -A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK = 0x0fffffff # macro -A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_DEPTH_BUFFER_BASE = 0x00008875 # macro -REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM = 0x00008877 # macro -REG_A6XX_RB_Z_BOUNDS_MIN = 0x00008878 # macro -A6XX_RB_Z_BOUNDS_MIN__MASK = 0xffffffff # macro -A6XX_RB_Z_BOUNDS_MIN__SHIFT = 0 # macro -REG_A6XX_RB_Z_BOUNDS_MAX = 0x00008879 # macro -A6XX_RB_Z_BOUNDS_MAX__MASK = 0xffffffff # macro -A6XX_RB_Z_BOUNDS_MAX__SHIFT = 0 # macro -REG_A6XX_RB_STENCIL_CONTROL = 0x00008880 # macro -A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE = 0x00000001 # macro -A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF = 0x00000002 # macro -A6XX_RB_STENCIL_CONTROL_STENCIL_READ = 0x00000004 # macro -A6XX_RB_STENCIL_CONTROL_FUNC__MASK = 0x00000700 # macro -A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT = 8 # macro -A6XX_RB_STENCIL_CONTROL_FAIL__MASK = 0x00003800 # macro -A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT = 11 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS__MASK = 0x0001c000 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT = 14 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK = 0x000e0000 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT = 17 # macro -A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK = 0x00700000 # macro -A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT = 20 # macro -A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK = 0x03800000 # macro -A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT = 23 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK = 0x1c000000 # macro -A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT = 26 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK = 0xe0000000 # macro -A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT = 29 # macro -REG_A6XX_GRAS_SU_STENCIL_CNTL = 0x00008115 # macro -A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 # macro -REG_A6XX_RB_STENCIL_INFO = 0x00008881 # macro -A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 # macro -A6XX_RB_STENCIL_INFO_UNK1 = 0x00000002 # macro -REG_A7XX_RB_STENCIL_INFO = 0x00008881 # macro -A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 # macro -A7XX_RB_STENCIL_INFO_UNK1 = 0x00000002 # macro -A7XX_RB_STENCIL_INFO_TILEMODE__MASK = 0x0000000c # macro -A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT = 2 # macro -REG_A6XX_RB_STENCIL_BUFFER_PITCH = 0x00008882 # macro -A6XX_RB_STENCIL_BUFFER_PITCH__MASK = 0x00000fff # macro -A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH = 0x00008883 # macro -A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK = 0x00ffffff # macro -A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_STENCIL_BUFFER_BASE = 0x00008884 # macro -REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM = 0x00008886 # macro -REG_A6XX_RB_STENCILREF = 0x00008887 # macro -A6XX_RB_STENCILREF_REF__MASK = 0x000000ff # macro -A6XX_RB_STENCILREF_REF__SHIFT = 0 # macro -A6XX_RB_STENCILREF_BFREF__MASK = 0x0000ff00 # macro -A6XX_RB_STENCILREF_BFREF__SHIFT = 8 # macro -REG_A6XX_RB_STENCILMASK = 0x00008888 # macro -A6XX_RB_STENCILMASK_MASK__MASK = 0x000000ff # macro -A6XX_RB_STENCILMASK_MASK__SHIFT = 0 # macro -A6XX_RB_STENCILMASK_BFMASK__MASK = 0x0000ff00 # macro -A6XX_RB_STENCILMASK_BFMASK__SHIFT = 8 # macro -REG_A6XX_RB_STENCILWRMASK = 0x00008889 # macro -A6XX_RB_STENCILWRMASK_WRMASK__MASK = 0x000000ff # macro -A6XX_RB_STENCILWRMASK_WRMASK__SHIFT = 0 # macro -A6XX_RB_STENCILWRMASK_BFWRMASK__MASK = 0x0000ff00 # macro -A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT = 8 # macro -REG_A6XX_RB_WINDOW_OFFSET = 0x00008890 # macro -A6XX_RB_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A6XX_RB_WINDOW_OFFSET_X__SHIFT = 0 # macro -A6XX_RB_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A6XX_RB_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A6XX_RB_SAMPLE_COUNT_CONTROL = 0x00008891 # macro -A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE = 0x00000001 # macro -A6XX_RB_SAMPLE_COUNT_CONTROL_COPY = 0x00000002 # macro -REG_A6XX_RB_LRZ_CNTL = 0x00008898 # macro -A6XX_RB_LRZ_CNTL_ENABLE = 0x00000001 # macro -REG_A7XX_RB_UNKNOWN_8899 = 0x00008899 # macro -REG_A6XX_RB_Z_CLAMP_MIN = 0x000088c0 # macro -A6XX_RB_Z_CLAMP_MIN__MASK = 0xffffffff # macro -A6XX_RB_Z_CLAMP_MIN__SHIFT = 0 # macro -REG_A6XX_RB_Z_CLAMP_MAX = 0x000088c1 # macro -A6XX_RB_Z_CLAMP_MAX__MASK = 0xffffffff # macro -A6XX_RB_Z_CLAMP_MAX__SHIFT = 0 # macro -REG_A6XX_RB_UNKNOWN_88D0 = 0x000088d0 # macro -A6XX_RB_UNKNOWN_88D0_UNK0__MASK = 0x00001fff # macro -A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT = 0 # macro -A6XX_RB_UNKNOWN_88D0_UNK16__MASK = 0x07ff0000 # macro -A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT = 16 # macro -REG_A6XX_RB_BLIT_SCISSOR_TL = 0x000088d1 # macro -A6XX_RB_BLIT_SCISSOR_TL_X__MASK = 0x00003fff # macro -A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT = 0 # macro -A6XX_RB_BLIT_SCISSOR_TL_Y__MASK = 0x3fff0000 # macro -A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT = 16 # macro -REG_A6XX_RB_BLIT_SCISSOR_BR = 0x000088d2 # macro -A6XX_RB_BLIT_SCISSOR_BR_X__MASK = 0x00003fff # macro -A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT = 0 # macro -A6XX_RB_BLIT_SCISSOR_BR_Y__MASK = 0x3fff0000 # macro -A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT = 16 # macro -REG_A6XX_RB_BIN_CONTROL2 = 0x000088d3 # macro -A6XX_RB_BIN_CONTROL2_BINW__MASK = 0x0000003f # macro -A6XX_RB_BIN_CONTROL2_BINW__SHIFT = 0 # macro -A6XX_RB_BIN_CONTROL2_BINH__MASK = 0x00007f00 # macro -A6XX_RB_BIN_CONTROL2_BINH__SHIFT = 8 # macro -REG_A6XX_RB_WINDOW_OFFSET2 = 0x000088d4 # macro -A6XX_RB_WINDOW_OFFSET2_X__MASK = 0x00003fff # macro -A6XX_RB_WINDOW_OFFSET2_X__SHIFT = 0 # macro -A6XX_RB_WINDOW_OFFSET2_Y__MASK = 0x3fff0000 # macro -A6XX_RB_WINDOW_OFFSET2_Y__SHIFT = 16 # macro -REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL = 0x000088d5 # macro -A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK = 0x00000018 # macro -A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT = 3 # macro -REG_A6XX_RB_BLIT_BASE_GMEM = 0x000088d6 # macro -REG_A6XX_RB_BLIT_DST_INFO = 0x000088d7 # macro -A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK = 0x00000003 # macro -A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT = 0 # macro -A6XX_RB_BLIT_DST_INFO_FLAGS = 0x00000004 # macro -A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK = 0x00000018 # macro -A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT = 3 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK = 0x00000060 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT = 5 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK = 0x00007f80 # macro -A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT = 7 # macro -A6XX_RB_BLIT_DST_INFO_UNK15 = 0x00008000 # macro -REG_A6XX_RB_BLIT_DST = 0x000088d8 # macro -REG_A6XX_RB_BLIT_DST_PITCH = 0x000088da # macro -A6XX_RB_BLIT_DST_PITCH__MASK = 0x0000ffff # macro -A6XX_RB_BLIT_DST_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_BLIT_DST_ARRAY_PITCH = 0x000088db # macro -A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK = 0x1fffffff # macro -A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_BLIT_FLAG_DST = 0x000088dc # macro -REG_A6XX_RB_BLIT_FLAG_DST_PITCH = 0x000088de # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK = 0x000007ff # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 # macro -A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 = 0x000088df # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 = 0x000088e0 # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 = 0x000088e1 # macro -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 = 0x000088e2 # macro -REG_A6XX_RB_BLIT_INFO = 0x000088e3 # macro -A6XX_RB_BLIT_INFO_UNK0 = 0x00000001 # macro -A6XX_RB_BLIT_INFO_GMEM = 0x00000002 # macro -A6XX_RB_BLIT_INFO_SAMPLE_0 = 0x00000004 # macro -A6XX_RB_BLIT_INFO_DEPTH = 0x00000008 # macro -A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK = 0x000000f0 # macro -A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT = 4 # macro -A6XX_RB_BLIT_INFO_LAST__MASK = 0x00000300 # macro -A6XX_RB_BLIT_INFO_LAST__SHIFT = 8 # macro -A6XX_RB_BLIT_INFO_BUFFER_ID__MASK = 0x0000f000 # macro -A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT = 12 # macro -REG_A7XX_RB_UNKNOWN_88E4 = 0x000088e4 # macro -A7XX_RB_UNKNOWN_88E4_UNK0 = 0x00000001 # macro -REG_A7XX_RB_CCU_CNTL2 = 0x000088e5 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK = 0x00000001 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT = 0 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK = 0x00000004 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT = 2 # macro -A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK = 0x00000c00 # macro -A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT = 10 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK = 0x001ff000 # macro -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT = 12 # macro -A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK = 0x00600000 # macro -A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT = 21 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK = 0xff800000 # macro -A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT = 23 # macro -REG_A6XX_RB_UNKNOWN_88F0 = 0x000088f0 # macro -REG_A6XX_RB_UNK_FLAG_BUFFER_BASE = 0x000088f1 # macro -REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH = 0x000088f3 # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x00fff800 # macro -A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -REG_A6XX_RB_UNKNOWN_88F4 = 0x000088f4 # macro -REG_A7XX_RB_UNKNOWN_88F5 = 0x000088f5 # macro -REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE = 0x00008900 # macro -REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH = 0x00008902 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK = 0x0000007f # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK = 0x00000700 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT = 8 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 # macro -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -# def REG_A6XX_RB_MRT_FLAG_BUFFER(i0): # macro -# return (0x00008903+0x3*i0) -A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff # macro -A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro -A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffff800 # macro -A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro -REG_A6XX_RB_SAMPLE_COUNT_ADDR = 0x00008927 # macro -REG_A6XX_RB_UNKNOWN_8A00 = 0x00008a00 # macro -REG_A6XX_RB_UNKNOWN_8A10 = 0x00008a10 # macro -REG_A6XX_RB_UNKNOWN_8A20 = 0x00008a20 # macro -REG_A6XX_RB_UNKNOWN_8A30 = 0x00008a30 # macro -REG_A6XX_RB_2D_BLIT_CNTL = 0x00008c00 # macro -A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 # macro -A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT = 0 # macro -A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 # macro -A6XX_RB_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 # macro -A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT = 4 # macro -A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 # macro -A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 # macro -A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 # macro -A6XX_RB_2D_BLIT_CNTL_SCISSOR = 0x00010000 # macro -A6XX_RB_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 # macro -A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT = 17 # macro -A6XX_RB_2D_BLIT_CNTL_D24S8 = 0x00080000 # macro -A6XX_RB_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 # macro -A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT = 20 # macro -A6XX_RB_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 # macro -A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT = 24 # macro -A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 # macro -A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 # macro -A6XX_RB_2D_BLIT_CNTL_UNK30 = 0x40000000 # macro -REG_A6XX_RB_2D_UNKNOWN_8C01 = 0x00008c01 # macro -REG_A6XX_RB_2D_DST_INFO = 0x00008c17 # macro -A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_RB_2D_DST_INFO_TILE_MODE__MASK = 0x00000300 # macro -A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT = 8 # macro -A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro -A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT = 10 # macro -A6XX_RB_2D_DST_INFO_FLAGS = 0x00001000 # macro -A6XX_RB_2D_DST_INFO_SRGB = 0x00002000 # macro -A6XX_RB_2D_DST_INFO_SAMPLES__MASK = 0x0000c000 # macro -A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT = 14 # macro -A6XX_RB_2D_DST_INFO_FILTER = 0x00010000 # macro -A6XX_RB_2D_DST_INFO_UNK17 = 0x00020000 # macro -A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE = 0x00040000 # macro -A6XX_RB_2D_DST_INFO_UNK19 = 0x00080000 # macro -A6XX_RB_2D_DST_INFO_UNK20 = 0x00100000 # macro -A6XX_RB_2D_DST_INFO_UNK21 = 0x00200000 # macro -A6XX_RB_2D_DST_INFO_UNK22 = 0x00400000 # macro -A6XX_RB_2D_DST_INFO_UNK23__MASK = 0x07800000 # macro -A6XX_RB_2D_DST_INFO_UNK23__SHIFT = 23 # macro -A6XX_RB_2D_DST_INFO_UNK28 = 0x10000000 # macro -REG_A6XX_RB_2D_DST = 0x00008c18 # macro -REG_A6XX_RB_2D_DST_PITCH = 0x00008c1a # macro -A6XX_RB_2D_DST_PITCH__MASK = 0x0000ffff # macro -A6XX_RB_2D_DST_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_DST_PLANE1 = 0x00008c1b # macro -REG_A6XX_RB_2D_DST_PLANE_PITCH = 0x00008c1d # macro -A6XX_RB_2D_DST_PLANE_PITCH__MASK = 0x0000ffff # macro -A6XX_RB_2D_DST_PLANE_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_DST_PLANE2 = 0x00008c1e # macro -REG_A6XX_RB_2D_DST_FLAGS = 0x00008c20 # macro -REG_A6XX_RB_2D_DST_FLAGS_PITCH = 0x00008c22 # macro -A6XX_RB_2D_DST_FLAGS_PITCH__MASK = 0x000000ff # macro -A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_DST_FLAGS_PLANE = 0x00008c23 # macro -REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH = 0x00008c25 # macro -A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK = 0x000000ff # macro -A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT = 0 # macro -REG_A6XX_RB_2D_SRC_SOLID_C0 = 0x00008c2c # macro -REG_A6XX_RB_2D_SRC_SOLID_C1 = 0x00008c2d # macro -REG_A6XX_RB_2D_SRC_SOLID_C2 = 0x00008c2e # macro -REG_A6XX_RB_2D_SRC_SOLID_C3 = 0x00008c2f # macro -REG_A7XX_RB_UNKNOWN_8C34 = 0x00008c34 # macro -REG_A6XX_RB_UNKNOWN_8E01 = 0x00008e01 # macro -REG_A6XX_RB_DBG_ECO_CNTL = 0x00008e04 # macro -REG_A6XX_RB_ADDR_MODE_CNTL = 0x00008e05 # macro -REG_A7XX_RB_UNKNOWN_8E06 = 0x00008e06 # macro -REG_A6XX_RB_CCU_CNTL = 0x00008e07 # macro -A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 # macro -A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000080 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT = 7 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK = 0x00000200 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT = 9 # macro -A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 # macro -A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 # macro -A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT = 12 # macro -A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 # macro -A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK = 0xff800000 # macro -A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT = 23 # macro -REG_A7XX_RB_CCU_CNTL = 0x00008e07 # macro -A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 # macro -A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 # macro -REG_A6XX_RB_NC_MODE_CNTL = 0x00008e08 # macro -A6XX_RB_NC_MODE_CNTL_MODE = 0x00000001 # macro -A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 # macro -A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 # macro -A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 # macro -A6XX_RB_NC_MODE_CNTL_AMSBC = 0x00000010 # macro -A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000400 # macro -A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT = 10 # macro -A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR = 0x00000800 # macro -A6XX_RB_NC_MODE_CNTL_UNK12__MASK = 0x00003000 # macro -A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT = 12 # macro -REG_A7XX_RB_UNKNOWN_8E09 = 0x00008e09 # macro -# def REG_A6XX_RB_PERFCTR_RB_SEL(i0): # macro -# return (0x00008e10+0x1*i0) -# def REG_A6XX_RB_PERFCTR_CCU_SEL(i0): # macro -# return (0x00008e18+0x1*i0) -REG_A6XX_RB_CMP_DBG_ECO_CNTL = 0x00008e28 # macro -# def REG_A6XX_RB_PERFCTR_CMP_SEL(i0): # macro -# return (0x00008e2c+0x1*i0) -# def REG_A7XX_RB_PERFCTR_UFC_SEL(i0): # macro -# return (0x00008e30+0x1*i0) -REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST = 0x00008e3b # macro -REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD = 0x00008e3d # macro -REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE = 0x00008e50 # macro -REG_A6XX_RB_UNKNOWN_8E51 = 0x00008e51 # macro -REG_A7XX_RB_UNKNOWN_8E79 = 0x00008e79 # macro -REG_A6XX_VPC_GS_PARAM = 0x00009100 # macro -A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK = 0x000000ff # macro -A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT = 0 # macro -REG_A6XX_VPC_VS_CLIP_CNTL = 0x00009101 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_CLIP_CNTL = 0x00009102 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_CLIP_CNTL = 0x00009103 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_VS_CLIP_CNTL_V2 = 0x00009311 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_CLIP_CNTL_V2 = 0x00009312 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_CLIP_CNTL_V2 = 0x00009313 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro -REG_A6XX_VPC_VS_LAYER_CNTL = 0x00009104 # macro -A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_LAYER_CNTL = 0x00009105 # macro -A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_LAYER_CNTL = 0x00009106 # macro -A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_VS_LAYER_CNTL_V2 = 0x00009314 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_GS_LAYER_CNTL_V2 = 0x00009315 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_DS_LAYER_CNTL_V2 = 0x00009316 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro -A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro -REG_A6XX_VPC_UNKNOWN_9107 = 0x00009107 # macro -A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD = 0x00000001 # macro -A6XX_VPC_UNKNOWN_9107_UNK2 = 0x00000004 # macro -REG_A6XX_VPC_POLYGON_MODE = 0x00009108 # macro -A6XX_VPC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro -A6XX_VPC_POLYGON_MODE_MODE__SHIFT = 0 # macro -REG_A7XX_VPC_PRIMITIVE_CNTL_0 = 0x00009109 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 # macro -A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 # macro -REG_A7XX_VPC_PRIMITIVE_CNTL_5 = 0x0000910a # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 # macro -A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 # macro -REG_A7XX_VPC_MULTIVIEW_MASK = 0x0000910b # macro -REG_A7XX_VPC_MULTIVIEW_CNTL = 0x0000910c # macro -A7XX_VPC_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro -A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro -A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro -A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro -# def REG_A6XX_VPC_VARYING_INTERP(i0): # macro -# return (0x00009200+0x1*i0) -# def REG_A6XX_VPC_VARYING_PS_REPL(i0): # macro -# return (0x00009208+0x1*i0) -REG_A6XX_VPC_UNKNOWN_9210 = 0x00009210 # macro -REG_A6XX_VPC_UNKNOWN_9211 = 0x00009211 # macro -# def REG_A6XX_VPC_VAR(i0): # macro -# return (0x00009212+0x1*i0) -REG_A6XX_VPC_SO_CNTL = 0x00009216 # macro -A6XX_VPC_SO_CNTL_ADDR__MASK = 0x000000ff # macro -A6XX_VPC_SO_CNTL_ADDR__SHIFT = 0 # macro -A6XX_VPC_SO_CNTL_RESET = 0x00010000 # macro -REG_A6XX_VPC_SO_PROG = 0x00009217 # macro -A6XX_VPC_SO_PROG_A_BUF__MASK = 0x00000003 # macro -A6XX_VPC_SO_PROG_A_BUF__SHIFT = 0 # macro -A6XX_VPC_SO_PROG_A_OFF__MASK = 0x000007fc # macro -A6XX_VPC_SO_PROG_A_OFF__SHIFT = 2 # macro -A6XX_VPC_SO_PROG_A_EN = 0x00000800 # macro -A6XX_VPC_SO_PROG_B_BUF__MASK = 0x00003000 # macro -A6XX_VPC_SO_PROG_B_BUF__SHIFT = 12 # macro -A6XX_VPC_SO_PROG_B_OFF__MASK = 0x007fc000 # macro -A6XX_VPC_SO_PROG_B_OFF__SHIFT = 14 # macro -A6XX_VPC_SO_PROG_B_EN = 0x00800000 # macro -REG_A6XX_VPC_SO_STREAM_COUNTS = 0x00009218 # macro -# def REG_A6XX_VPC_SO(i0): # macro -# return (0x0000921a+0x7*i0) -REG_A6XX_VPC_POINT_COORD_INVERT = 0x00009236 # macro -A6XX_VPC_POINT_COORD_INVERT_INVERT = 0x00000001 # macro -REG_A6XX_VPC_UNKNOWN_9300 = 0x00009300 # macro -REG_A6XX_VPC_VS_PACK = 0x00009301 # macro -A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_VPC_VS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT = 8 # macro -A6XX_VPC_VS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_VS_PACK_PSIZELOC__SHIFT = 16 # macro -A6XX_VPC_VS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro -A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT = 24 # macro -REG_A6XX_VPC_GS_PACK = 0x00009302 # macro -A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_VPC_GS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT = 8 # macro -A6XX_VPC_GS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_GS_PACK_PSIZELOC__SHIFT = 16 # macro -A6XX_VPC_GS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro -A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT = 24 # macro -REG_A6XX_VPC_DS_PACK = 0x00009303 # macro -A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_VPC_DS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT = 8 # macro -A6XX_VPC_DS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro -A6XX_VPC_DS_PACK_PSIZELOC__SHIFT = 16 # macro -A6XX_VPC_DS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro -A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT = 24 # macro -REG_A6XX_VPC_CNTL_0 = 0x00009304 # macro -A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK = 0x000000ff # macro -A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT = 0 # macro -A6XX_VPC_CNTL_0_PRIMIDLOC__MASK = 0x0000ff00 # macro -A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT = 8 # macro -A6XX_VPC_CNTL_0_VARYING = 0x00010000 # macro -A6XX_VPC_CNTL_0_VIEWIDLOC__MASK = 0xff000000 # macro -A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT = 24 # macro -REG_A6XX_VPC_SO_STREAM_CNTL = 0x00009305 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK = 0x00000007 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT = 0 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK = 0x00000038 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT = 3 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK = 0x000001c0 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT = 6 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK = 0x00000e00 # macro -A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT = 9 # macro -A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 # macro -A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 # macro -REG_A6XX_VPC_SO_DISABLE = 0x00009306 # macro -A6XX_VPC_SO_DISABLE_DISABLE = 0x00000001 # macro -REG_A7XX_VPC_POLYGON_MODE2 = 0x00009307 # macro -A7XX_VPC_POLYGON_MODE2_MODE__MASK = 0x00000003 # macro -A7XX_VPC_POLYGON_MODE2_MODE__SHIFT = 0 # macro -REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM = 0x00009308 # macro -A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff # macro -A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 # macro -REG_A7XX_VPC_ATTR_BUF_BASE_GMEM = 0x00009309 # macro -A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK = 0xffffffff # macro -A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT = 0 # macro -REG_A7XX_PC_ATTR_BUF_SIZE_GMEM = 0x00009b09 # macro -A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff # macro -A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 # macro -REG_A6XX_VPC_DBG_ECO_CNTL = 0x00009600 # macro -REG_A6XX_VPC_ADDR_MODE_CNTL = 0x00009601 # macro -REG_A6XX_VPC_UNKNOWN_9602 = 0x00009602 # macro -REG_A6XX_VPC_UNKNOWN_9603 = 0x00009603 # macro -# def REG_A6XX_VPC_PERFCTR_VPC_SEL(i0): # macro -# return (0x00009604+0x1*i0) -# def REG_A7XX_VPC_PERFCTR_VPC_SEL(i0): # macro -# return (0x0000960b+0x1*i0) -REG_A6XX_PC_TESS_NUM_VERTEX = 0x00009800 # macro -REG_A6XX_PC_HS_INPUT_SIZE = 0x00009801 # macro -A6XX_PC_HS_INPUT_SIZE_SIZE__MASK = 0x000007ff # macro -A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT = 0 # macro -A6XX_PC_HS_INPUT_SIZE_UNK13 = 0x00002000 # macro -REG_A6XX_PC_TESS_CNTL = 0x00009802 # macro -A6XX_PC_TESS_CNTL_SPACING__MASK = 0x00000003 # macro -A6XX_PC_TESS_CNTL_SPACING__SHIFT = 0 # macro -A6XX_PC_TESS_CNTL_OUTPUT__MASK = 0x0000000c # macro -A6XX_PC_TESS_CNTL_OUTPUT__SHIFT = 2 # macro -REG_A6XX_PC_RESTART_INDEX = 0x00009803 # macro -REG_A6XX_PC_MODE_CNTL = 0x00009804 # macro -REG_A6XX_PC_POWER_CNTL = 0x00009805 # macro -REG_A6XX_PC_PS_CNTL = 0x00009806 # macro -A6XX_PC_PS_CNTL_PRIMITIVEIDEN = 0x00000001 # macro -REG_A6XX_PC_SO_STREAM_CNTL = 0x00009808 # macro -A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 # macro -A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 # macro -REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL = 0x0000980a # macro -A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 # macro -REG_A6XX_PC_DRAW_CMD = 0x00009840 # macro -A6XX_PC_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_PC_DRAW_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_PC_DISPATCH_CMD = 0x00009841 # macro -A6XX_PC_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_PC_EVENT_CMD = 0x00009842 # macro -A6XX_PC_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro -A6XX_PC_EVENT_CMD_STATE_ID__SHIFT = 16 # macro -A6XX_PC_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_PC_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A6XX_PC_MARKER = 0x00009880 # macro -REG_A6XX_PC_POLYGON_MODE = 0x00009981 # macro -A6XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro -A6XX_PC_POLYGON_MODE_MODE__SHIFT = 0 # macro -REG_A7XX_PC_POLYGON_MODE = 0x00009809 # macro -A7XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro -A7XX_PC_POLYGON_MODE_MODE__SHIFT = 0 # macro -REG_A6XX_PC_RASTER_CNTL = 0x00009980 # macro -A6XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 # macro -A6XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 # macro -A6XX_PC_RASTER_CNTL_DISCARD = 0x00000004 # macro -REG_A7XX_PC_RASTER_CNTL = 0x00009107 # macro -A7XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 # macro -A7XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 # macro -A7XX_PC_RASTER_CNTL_DISCARD = 0x00000004 # macro -REG_A7XX_PC_RASTER_CNTL_V2 = 0x00009317 # macro -A7XX_PC_RASTER_CNTL_V2_STREAM__MASK = 0x00000003 # macro -A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT = 0 # macro -A7XX_PC_RASTER_CNTL_V2_DISCARD = 0x00000004 # macro -REG_A7XX_PC_TESS_PARAM_SIZE = 0x00009885 # macro -REG_A7XX_PC_TESS_FACTOR_SIZE = 0x00009886 # macro -REG_A6XX_PC_PRIMITIVE_CNTL_0 = 0x00009b00 # macro -A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 # macro -A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 # macro -A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 # macro -A6XX_PC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 # macro -REG_A6XX_PC_VS_OUT_CNTL = 0x00009b01 # macro -A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_VS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_VS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_VS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_VS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_GS_OUT_CNTL = 0x00009b02 # macro -A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_GS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_GS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_GS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_GS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_HS_OUT_CNTL = 0x00009b03 # macro -A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_HS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_HS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_HS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_HS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_DS_OUT_CNTL = 0x00009b04 # macro -A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro -A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro -A6XX_PC_DS_OUT_CNTL_PSIZE = 0x00000100 # macro -A6XX_PC_DS_OUT_CNTL_LAYER = 0x00000200 # macro -A6XX_PC_DS_OUT_CNTL_VIEW = 0x00000400 # macro -A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro -A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro -A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro -A6XX_PC_DS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro -REG_A6XX_PC_PRIMITIVE_CNTL_5 = 0x00009b05 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 # macro -A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 # macro -A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 # macro -A6XX_PC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 # macro -REG_A6XX_PC_PRIMITIVE_CNTL_6 = 0x00009b06 # macro -A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK = 0x000007ff # macro -A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT = 0 # macro -REG_A6XX_PC_MULTIVIEW_CNTL = 0x00009b07 # macro -A6XX_PC_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro -A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro -A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro -A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro -REG_A6XX_PC_MULTIVIEW_MASK = 0x00009b08 # macro -REG_A6XX_PC_2D_EVENT_CMD = 0x00009c00 # macro -A6XX_PC_2D_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT = 0 # macro -A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 # macro -A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT = 8 # macro -REG_A6XX_PC_DBG_ECO_CNTL = 0x00009e00 # macro -REG_A6XX_PC_ADDR_MODE_CNTL = 0x00009e01 # macro -REG_A6XX_PC_DRAW_INDX_BASE = 0x00009e04 # macro -REG_A6XX_PC_DRAW_FIRST_INDX = 0x00009e06 # macro -REG_A6XX_PC_DRAW_MAX_INDICES = 0x00009e07 # macro -REG_A6XX_PC_TESSFACTOR_ADDR = 0x00009e08 # macro -REG_A7XX_PC_TESSFACTOR_ADDR = 0x00009810 # macro -REG_A6XX_PC_DRAW_INITIATOR = 0x00009e0b # macro -A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK = 0x0000003f # macro -A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT = 0 # macro -A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK = 0x000000c0 # macro -A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT = 6 # macro -A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK = 0x00000300 # macro -A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT = 8 # macro -A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK = 0x00000c00 # macro -A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT = 10 # macro -A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK = 0x00003000 # macro -A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT = 12 # macro -A6XX_PC_DRAW_INITIATOR_GS_ENABLE = 0x00010000 # macro -A6XX_PC_DRAW_INITIATOR_TESS_ENABLE = 0x00020000 # macro -REG_A6XX_PC_DRAW_NUM_INSTANCES = 0x00009e0c # macro -REG_A6XX_PC_DRAW_NUM_INDICES = 0x00009e0d # macro -REG_A6XX_PC_VSTREAM_CONTROL = 0x00009e11 # macro -A6XX_PC_VSTREAM_CONTROL_UNK0__MASK = 0x0000ffff # macro -A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT = 0 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK = 0x003f0000 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT = 16 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK = 0x07c00000 # macro -A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT = 22 # macro -REG_A6XX_PC_BIN_PRIM_STRM = 0x00009e12 # macro -REG_A6XX_PC_BIN_DRAW_STRM = 0x00009e14 # macro -REG_A6XX_PC_VISIBILITY_OVERRIDE = 0x00009e1c # macro -A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE = 0x00000001 # macro -REG_A7XX_PC_UNKNOWN_9E24 = 0x00009e24 # macro -# def REG_A6XX_PC_PERFCTR_PC_SEL(i0): # macro -# return (0x00009e34+0x1*i0) -# def REG_A7XX_PC_PERFCTR_PC_SEL(i0): # macro -# return (0x00009e42+0x1*i0) -REG_A6XX_PC_UNKNOWN_9E72 = 0x00009e72 # macro -REG_A6XX_VFD_CONTROL_0 = 0x0000a000 # macro -A6XX_VFD_CONTROL_0_FETCH_CNT__MASK = 0x0000003f # macro -A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT = 0 # macro -A6XX_VFD_CONTROL_0_DECODE_CNT__MASK = 0x00003f00 # macro -A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT = 8 # macro -REG_A6XX_VFD_CONTROL_1 = 0x0000a001 # macro -A6XX_VFD_CONTROL_1_REGID4VTX__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT = 0 # macro -A6XX_VFD_CONTROL_1_REGID4INST__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_1_REGID4INST__SHIFT = 8 # macro -A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK = 0x00ff0000 # macro -A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT = 16 # macro -A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK = 0xff000000 # macro -A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT = 24 # macro -REG_A6XX_VFD_CONTROL_2 = 0x0000a002 # macro -A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT = 0 # macro -A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT = 8 # macro -REG_A6XX_VFD_CONTROL_3 = 0x0000a003 # macro -A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT = 0 # macro -A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT = 8 # macro -A6XX_VFD_CONTROL_3_REGID_TESSX__MASK = 0x00ff0000 # macro -A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT = 16 # macro -A6XX_VFD_CONTROL_3_REGID_TESSY__MASK = 0xff000000 # macro -A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT = 24 # macro -REG_A6XX_VFD_CONTROL_4 = 0x0000a004 # macro -A6XX_VFD_CONTROL_4_UNK0__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_4_UNK0__SHIFT = 0 # macro -REG_A6XX_VFD_CONTROL_5 = 0x0000a005 # macro -A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK = 0x000000ff # macro -A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT = 0 # macro -A6XX_VFD_CONTROL_5_UNK8__MASK = 0x0000ff00 # macro -A6XX_VFD_CONTROL_5_UNK8__SHIFT = 8 # macro -REG_A6XX_VFD_CONTROL_6 = 0x0000a006 # macro -A6XX_VFD_CONTROL_6_PRIMID4PSEN = 0x00000001 # macro -REG_A6XX_VFD_MODE_CNTL = 0x0000a007 # macro -A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK = 0x00000007 # macro -A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT = 0 # macro -REG_A6XX_VFD_MULTIVIEW_CNTL = 0x0000a008 # macro -A6XX_VFD_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro -A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro -A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro -A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro -REG_A6XX_VFD_ADD_OFFSET = 0x0000a009 # macro -A6XX_VFD_ADD_OFFSET_VERTEX = 0x00000001 # macro -A6XX_VFD_ADD_OFFSET_INSTANCE = 0x00000002 # macro -REG_A6XX_VFD_INDEX_OFFSET = 0x0000a00e # macro -REG_A6XX_VFD_INSTANCE_START_OFFSET = 0x0000a00f # macro -# def REG_A6XX_VFD_FETCH(i0): # macro -# return (0x0000a010+0x4*i0) -# def REG_A6XX_VFD_DECODE(i0): # macro -# return (0x0000a090+0x2*i0) -A6XX_VFD_DECODE_INSTR_IDX__MASK = 0x0000001f # macro -A6XX_VFD_DECODE_INSTR_IDX__SHIFT = 0 # macro -A6XX_VFD_DECODE_INSTR_OFFSET__MASK = 0x0001ffe0 # macro -A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT = 5 # macro -A6XX_VFD_DECODE_INSTR_INSTANCED = 0x00020000 # macro -A6XX_VFD_DECODE_INSTR_FORMAT__MASK = 0x0ff00000 # macro -A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT = 20 # macro -A6XX_VFD_DECODE_INSTR_SWAP__MASK = 0x30000000 # macro -A6XX_VFD_DECODE_INSTR_SWAP__SHIFT = 28 # macro -A6XX_VFD_DECODE_INSTR_UNK30 = 0x40000000 # macro -A6XX_VFD_DECODE_INSTR_FLOAT = 0x80000000 # macro -# def REG_A6XX_VFD_DEST_CNTL(i0): # macro -# return (0x0000a0d0+0x1*i0) -A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK = 0x0000000f # macro -A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT = 0 # macro -A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK = 0x00000ff0 # macro -A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT = 4 # macro -REG_A6XX_VFD_POWER_CNTL = 0x0000a0f8 # macro -REG_A7XX_VFD_UNKNOWN_A600 = 0x0000a600 # macro -REG_A6XX_VFD_ADDR_MODE_CNTL = 0x0000a601 # macro -# def REG_A6XX_VFD_PERFCTR_VFD_SEL(i0): # macro -# return (0x0000a610+0x1*i0) -# def REG_A7XX_VFD_PERFCTR_VFD_SEL(i0): # macro -# return (0x0000a610+0x1*i0) -REG_A6XX_SP_VS_CTRL_REG0 = 0x0000a800 # macro -A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_VS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_VS_CTRL_REG0_MERGEDREGS = 0x00100000 # macro -A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE = 0x00200000 # macro -REG_A6XX_SP_VS_BRANCH_COND = 0x0000a801 # macro -REG_A6XX_SP_VS_PRIMITIVE_CNTL = 0x0000a802 # macro -A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro -A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro -A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro -A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro -# def REG_A6XX_SP_VS_OUT(i0): # macro -# return (0x0000a803+0x1*i0) -A6XX_SP_VS_OUT_REG_A_REGID__MASK = 0x000000ff # macro -A6XX_SP_VS_OUT_REG_A_REGID__SHIFT = 0 # macro -A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro -A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro -A6XX_SP_VS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_VS_OUT_REG_B_REGID__SHIFT = 16 # macro -A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro -A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro -# def REG_A6XX_SP_VS_VPC_DST(i0): # macro -# return (0x0000a813+0x1*i0) -A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro -A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro -REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET = 0x0000a81b # macro -REG_A6XX_SP_VS_OBJ_START = 0x0000a81c # macro -REG_A6XX_SP_VS_PVT_MEM_PARAM = 0x0000a81e # macro -A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_VS_PVT_MEM_ADDR = 0x0000a81f # macro -REG_A6XX_SP_VS_PVT_MEM_SIZE = 0x0000a821 # macro -A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_VS_TEX_COUNT = 0x0000a822 # macro -REG_A6XX_SP_VS_CONFIG = 0x0000a823 # macro -A6XX_SP_VS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_VS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_VS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_VS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_VS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_VS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_VS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_VS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_VS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_VS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_VS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_VS_INSTRLEN = 0x0000a824 # macro -REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET = 0x0000a825 # macro -A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_VS_VGPR_CONFIG = 0x0000a82d # macro -REG_A6XX_SP_HS_CTRL_REG0 = 0x0000a830 # macro -A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_HS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro -REG_A6XX_SP_HS_WAVE_INPUT_SIZE = 0x0000a831 # macro -REG_A6XX_SP_HS_BRANCH_COND = 0x0000a832 # macro -REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET = 0x0000a833 # macro -REG_A6XX_SP_HS_OBJ_START = 0x0000a834 # macro -REG_A6XX_SP_HS_PVT_MEM_PARAM = 0x0000a836 # macro -A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_HS_PVT_MEM_ADDR = 0x0000a837 # macro -REG_A6XX_SP_HS_PVT_MEM_SIZE = 0x0000a839 # macro -A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_HS_TEX_COUNT = 0x0000a83a # macro -REG_A6XX_SP_HS_CONFIG = 0x0000a83b # macro -A6XX_SP_HS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_HS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_HS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_HS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_HS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_HS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_HS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_HS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_HS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_HS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_HS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_HS_INSTRLEN = 0x0000a83c # macro -REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET = 0x0000a83d # macro -A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_HS_VGPR_CONFIG = 0x0000a82f # macro -REG_A6XX_SP_DS_CTRL_REG0 = 0x0000a840 # macro -A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_DS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro -REG_A6XX_SP_DS_BRANCH_COND = 0x0000a841 # macro -REG_A6XX_SP_DS_PRIMITIVE_CNTL = 0x0000a842 # macro -A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro -A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro -A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro -A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro -# def REG_A6XX_SP_DS_OUT(i0): # macro -# return (0x0000a843+0x1*i0) -A6XX_SP_DS_OUT_REG_A_REGID__MASK = 0x000000ff # macro -A6XX_SP_DS_OUT_REG_A_REGID__SHIFT = 0 # macro -A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro -A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro -A6XX_SP_DS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_DS_OUT_REG_B_REGID__SHIFT = 16 # macro -A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro -A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro -# def REG_A6XX_SP_DS_VPC_DST(i0): # macro -# return (0x0000a853+0x1*i0) -A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro -A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro -REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET = 0x0000a85b # macro -REG_A6XX_SP_DS_OBJ_START = 0x0000a85c # macro -REG_A6XX_SP_DS_PVT_MEM_PARAM = 0x0000a85e # macro -A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_DS_PVT_MEM_ADDR = 0x0000a85f # macro -REG_A6XX_SP_DS_PVT_MEM_SIZE = 0x0000a861 # macro -A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_DS_TEX_COUNT = 0x0000a862 # macro -REG_A6XX_SP_DS_CONFIG = 0x0000a863 # macro -A6XX_SP_DS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_DS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_DS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_DS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_DS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_DS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_DS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_DS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_DS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_DS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_DS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_DS_INSTRLEN = 0x0000a864 # macro -REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET = 0x0000a865 # macro -A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_DS_VGPR_CONFIG = 0x0000a868 # macro -REG_A6XX_SP_GS_CTRL_REG0 = 0x0000a870 # macro -A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_GS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro -REG_A6XX_SP_GS_PRIM_SIZE = 0x0000a871 # macro -REG_A6XX_SP_GS_BRANCH_COND = 0x0000a872 # macro -REG_A6XX_SP_GS_PRIMITIVE_CNTL = 0x0000a873 # macro -A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro -A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro -A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro -A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro -# def REG_A6XX_SP_GS_OUT(i0): # macro -# return (0x0000a874+0x1*i0) -A6XX_SP_GS_OUT_REG_A_REGID__MASK = 0x000000ff # macro -A6XX_SP_GS_OUT_REG_A_REGID__SHIFT = 0 # macro -A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro -A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro -A6XX_SP_GS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_GS_OUT_REG_B_REGID__SHIFT = 16 # macro -A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro -A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro -# def REG_A6XX_SP_GS_VPC_DST(i0): # macro -# return (0x0000a884+0x1*i0) -A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro -A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro -REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET = 0x0000a88c # macro -REG_A6XX_SP_GS_OBJ_START = 0x0000a88d # macro -REG_A6XX_SP_GS_PVT_MEM_PARAM = 0x0000a88f # macro -A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_GS_PVT_MEM_ADDR = 0x0000a890 # macro -REG_A6XX_SP_GS_PVT_MEM_SIZE = 0x0000a892 # macro -A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_GS_TEX_COUNT = 0x0000a893 # macro -REG_A6XX_SP_GS_CONFIG = 0x0000a894 # macro -A6XX_SP_GS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_GS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_GS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_GS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_GS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_GS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_GS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_GS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_GS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_GS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_GS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_GS_INSTRLEN = 0x0000a895 # macro -REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET = 0x0000a896 # macro -A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_GS_VGPR_CONFIG = 0x0000a899 # macro -REG_A6XX_SP_VS_TEX_SAMP = 0x0000a8a0 # macro -REG_A6XX_SP_HS_TEX_SAMP = 0x0000a8a2 # macro -REG_A6XX_SP_DS_TEX_SAMP = 0x0000a8a4 # macro -REG_A6XX_SP_GS_TEX_SAMP = 0x0000a8a6 # macro -REG_A6XX_SP_VS_TEX_CONST = 0x0000a8a8 # macro -REG_A6XX_SP_HS_TEX_CONST = 0x0000a8aa # macro -REG_A6XX_SP_DS_TEX_CONST = 0x0000a8ac # macro -REG_A6XX_SP_GS_TEX_CONST = 0x0000a8ae # macro -REG_A6XX_SP_FS_CTRL_REG0 = 0x0000a980 # macro -A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_FS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 # macro -A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT = 20 # macro -A6XX_SP_FS_CTRL_REG0_UNK21 = 0x00200000 # macro -A6XX_SP_FS_CTRL_REG0_VARYING = 0x00400000 # macro -A6XX_SP_FS_CTRL_REG0_LODPIXMASK = 0x00800000 # macro -A6XX_SP_FS_CTRL_REG0_UNK24 = 0x01000000 # macro -A6XX_SP_FS_CTRL_REG0_UNK25 = 0x02000000 # macro -A6XX_SP_FS_CTRL_REG0_PIXLODENABLE = 0x04000000 # macro -A6XX_SP_FS_CTRL_REG0_UNK27 = 0x08000000 # macro -A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE = 0x10000000 # macro -A6XX_SP_FS_CTRL_REG0_MERGEDREGS = 0x80000000 # macro -REG_A6XX_SP_FS_BRANCH_COND = 0x0000a981 # macro -REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET = 0x0000a982 # macro -REG_A6XX_SP_FS_OBJ_START = 0x0000a983 # macro -REG_A6XX_SP_FS_PVT_MEM_PARAM = 0x0000a985 # macro -A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_FS_PVT_MEM_ADDR = 0x0000a986 # macro -REG_A6XX_SP_FS_PVT_MEM_SIZE = 0x0000a988 # macro -A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_BLEND_CNTL = 0x0000a989 # macro -A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff # macro -A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 # macro -A6XX_SP_BLEND_CNTL_UNK8 = 0x00000100 # macro -A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 # macro -A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 # macro -REG_A6XX_SP_SRGB_CNTL = 0x0000a98a # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT0 = 0x00000001 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT1 = 0x00000002 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT2 = 0x00000004 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT3 = 0x00000008 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT4 = 0x00000010 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT5 = 0x00000020 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT6 = 0x00000040 # macro -A6XX_SP_SRGB_CNTL_SRGB_MRT7 = 0x00000080 # macro -REG_A6XX_SP_FS_RENDER_COMPONENTS = 0x0000a98b # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK = 0x0000000f # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT = 0 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT = 4 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT = 8 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT = 12 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT = 16 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT = 20 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT = 24 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 # macro -A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT = 28 # macro -REG_A6XX_SP_FS_OUTPUT_CNTL0 = 0x0000a98c # macro -A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 # macro -A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK = 0x0000ff00 # macro -A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT = 8 # macro -A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK = 0x00ff0000 # macro -A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT = 16 # macro -A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK = 0xff000000 # macro -A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT = 24 # macro -REG_A6XX_SP_FS_OUTPUT_CNTL1 = 0x0000a98d # macro -A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f # macro -A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 # macro -# def REG_A6XX_SP_FS_OUTPUT(i0): # macro -# return (0x0000a98e+0x1*i0) -A6XX_SP_FS_OUTPUT_REG_REGID__MASK = 0x000000ff # macro -A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT = 0 # macro -A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION = 0x00000100 # macro -# def REG_A6XX_SP_FS_MRT(i0): # macro -# return (0x0000a996+0x1*i0) -A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_SP_FS_MRT_REG_COLOR_SINT = 0x00000100 # macro -A6XX_SP_FS_MRT_REG_COLOR_UINT = 0x00000200 # macro -A6XX_SP_FS_MRT_REG_UNK10 = 0x00000400 # macro -REG_A6XX_SP_FS_PREFETCH_CNTL = 0x0000a99e # macro -A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK = 0x00000007 # macro -A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT = 0 # macro -A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE = 0x00000008 # macro -A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD = 0x00000010 # macro -A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT = 0x00000020 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK = 0x00007fc0 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT = 6 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK = 0x01ff0000 # macro -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT = 16 # macro -# def REG_A6XX_SP_FS_PREFETCH(i0): # macro -# return (0x0000a99f+0x1*i0) -A6XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f # macro -A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 # macro -A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000780 # macro -A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 # macro -A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x0000f800 # macro -A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 11 # macro -A6XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x003f0000 # macro -A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 16 # macro -A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x03c00000 # macro -A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 22 # macro -A6XX_SP_FS_PREFETCH_CMD_HALF = 0x04000000 # macro -A6XX_SP_FS_PREFETCH_CMD_UNK27 = 0x08000000 # macro -A6XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x10000000 # macro -A6XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0xe0000000 # macro -A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 29 # macro -# def REG_A7XX_SP_FS_PREFETCH(i0): # macro -# return (0x0000a99f+0x1*i0) -A7XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f # macro -A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 # macro -A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000380 # macro -A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 # macro -A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x00001c00 # macro -A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 10 # macro -A7XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x0007e000 # macro -A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 13 # macro -A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x00780000 # macro -A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 19 # macro -A7XX_SP_FS_PREFETCH_CMD_HALF = 0x00800000 # macro -A7XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x02000000 # macro -A7XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0x3c000000 # macro -A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 26 # macro -# def REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0): # macro -# return (0x0000a9a3+0x1*i0) -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK = 0x0000ffff # macro -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT = 0 # macro -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK = 0xffff0000 # macro -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT = 16 # macro -REG_A6XX_SP_FS_TEX_COUNT = 0x0000a9a7 # macro -REG_A6XX_SP_UNKNOWN_A9A8 = 0x0000a9a8 # macro -REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9a9 # macro -A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A6XX_SP_CS_CTRL_REG0 = 0x0000a9b0 # macro -A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro -A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro -A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro -A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro -A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro -A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro -A6XX_SP_CS_CTRL_REG0_UNK13 = 0x00002000 # macro -A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro -A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro -A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 # macro -A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT = 20 # macro -A6XX_SP_CS_CTRL_REG0_UNK21 = 0x00200000 # macro -A6XX_SP_CS_CTRL_REG0_UNK22 = 0x00400000 # macro -A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE = 0x00800000 # macro -A6XX_SP_CS_CTRL_REG0_MERGEDREGS = 0x80000000 # macro -REG_A6XX_SP_CS_UNKNOWN_A9B1 = 0x0000a9b1 # macro -A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK = 0x0000001f # macro -A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT = 0 # macro -A6XX_SP_CS_UNKNOWN_A9B1_UNK5 = 0x00000020 # macro -A6XX_SP_CS_UNKNOWN_A9B1_UNK6 = 0x00000040 # macro -REG_A6XX_SP_CS_BRANCH_COND = 0x0000a9b2 # macro -REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET = 0x0000a9b3 # macro -REG_A6XX_SP_CS_OBJ_START = 0x0000a9b4 # macro -REG_A6XX_SP_CS_PVT_MEM_PARAM = 0x0000a9b6 # macro -A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro -A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro -A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro -A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro -REG_A6XX_SP_CS_PVT_MEM_ADDR = 0x0000a9b7 # macro -REG_A6XX_SP_CS_PVT_MEM_SIZE = 0x0000a9b9 # macro -A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro -A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro -A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro -REG_A6XX_SP_CS_TEX_COUNT = 0x0000a9ba # macro -REG_A6XX_SP_CS_CONFIG = 0x0000a9bb # macro -A6XX_SP_CS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_CS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_CS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_CS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_CS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_CS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_CS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_CS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_CS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_CS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_CS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_CS_INSTRLEN = 0x0000a9bc # macro -REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9bd # macro -A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro -A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro -REG_A7XX_SP_CS_UNKNOWN_A9BE = 0x0000a9be # macro -REG_A7XX_SP_CS_VGPR_CONFIG = 0x0000a9c5 # macro -REG_A6XX_SP_CS_CNTL_0 = 0x0000a9c2 # macro -A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff # macro -A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 # macro -A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 # macro -A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 # macro -A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 # macro -A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 # macro -A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 # macro -A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 # macro -REG_A6XX_SP_CS_CNTL_1 = 0x0000a9c3 # macro -A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 # macro -A6XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro -A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro -A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 # macro -REG_A7XX_SP_CS_CNTL_1 = 0x0000a9c3 # macro -A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A7XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000100 # macro -A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 8 # macro -A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000200 # macro -A7XX_SP_CS_CNTL_1_UNK15 = 0x00008000 # macro -REG_A6XX_SP_FS_TEX_SAMP = 0x0000a9e0 # macro -REG_A6XX_SP_CS_TEX_SAMP = 0x0000a9e2 # macro -REG_A6XX_SP_FS_TEX_CONST = 0x0000a9e4 # macro -REG_A6XX_SP_CS_TEX_CONST = 0x0000a9e6 # macro -# def REG_A6XX_SP_CS_BINDLESS_BASE(i0): # macro -# return (0x0000a9e8+0x2*i0) -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -# def REG_A7XX_SP_CS_BINDLESS_BASE(i0): # macro -# return (0x0000a9e8+0x2*i0) -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_SP_CS_IBO = 0x0000a9f2 # macro -REG_A6XX_SP_CS_IBO_COUNT = 0x0000aa00 # macro -REG_A7XX_SP_FS_VGPR_CONFIG = 0x0000aa01 # macro -REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL = 0x0000aa02 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED = 0x00000001 # macro -REG_A7XX_SP_PS_ALIASED_COMPONENTS = 0x0000aa03 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK = 0x0000000f # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT = 0 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK = 0x000000f0 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT = 4 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK = 0x00000f00 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT = 8 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK = 0x0000f000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT = 12 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK = 0x000f0000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT = 16 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK = 0x00f00000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT = 20 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK = 0x0f000000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT = 24 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK = 0xf0000000 # macro -A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT = 28 # macro -REG_A6XX_SP_UNKNOWN_AAF2 = 0x0000aaf2 # macro -REG_A6XX_SP_MODE_CONTROL = 0x0000ab00 # macro -A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE = 0x00000001 # macro -A6XX_SP_MODE_CONTROL_ISAMMODE__MASK = 0x00000006 # macro -A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT = 1 # macro -A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE = 0x00000008 # macro -REG_A7XX_SP_UNKNOWN_AB01 = 0x0000ab01 # macro -REG_A7XX_SP_UNKNOWN_AB02 = 0x0000ab02 # macro -REG_A6XX_SP_FS_CONFIG = 0x0000ab04 # macro -A6XX_SP_FS_CONFIG_BINDLESS_TEX = 0x00000001 # macro -A6XX_SP_FS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro -A6XX_SP_FS_CONFIG_BINDLESS_IBO = 0x00000004 # macro -A6XX_SP_FS_CONFIG_BINDLESS_UBO = 0x00000008 # macro -A6XX_SP_FS_CONFIG_ENABLED = 0x00000100 # macro -A6XX_SP_FS_CONFIG_NTEX__MASK = 0x0001fe00 # macro -A6XX_SP_FS_CONFIG_NTEX__SHIFT = 9 # macro -A6XX_SP_FS_CONFIG_NSAMP__MASK = 0x003e0000 # macro -A6XX_SP_FS_CONFIG_NSAMP__SHIFT = 17 # macro -A6XX_SP_FS_CONFIG_NIBO__MASK = 0x1fc00000 # macro -A6XX_SP_FS_CONFIG_NIBO__SHIFT = 22 # macro -REG_A6XX_SP_FS_INSTRLEN = 0x0000ab05 # macro -# def REG_A6XX_SP_BINDLESS_BASE(i0): # macro -# return (0x0000ab10+0x2*i0) -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -# def REG_A7XX_SP_BINDLESS_BASE(i0): # macro -# return (0x0000ab0a+0x2*i0) -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_SP_IBO = 0x0000ab1a # macro -REG_A6XX_SP_IBO_COUNT = 0x0000ab20 # macro -REG_A7XX_SP_UNKNOWN_AB22 = 0x0000ab22 # macro -REG_A6XX_SP_2D_DST_FORMAT = 0x0000acc0 # macro -A6XX_SP_2D_DST_FORMAT_NORM = 0x00000001 # macro -A6XX_SP_2D_DST_FORMAT_SINT = 0x00000002 # macro -A6XX_SP_2D_DST_FORMAT_UINT = 0x00000004 # macro -A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 # macro -A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 # macro -A6XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 # macro -A6XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 # macro -A6XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 # macro -REG_A7XX_SP_2D_DST_FORMAT = 0x0000a9bf # macro -A7XX_SP_2D_DST_FORMAT_NORM = 0x00000001 # macro -A7XX_SP_2D_DST_FORMAT_SINT = 0x00000002 # macro -A7XX_SP_2D_DST_FORMAT_UINT = 0x00000004 # macro -A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 # macro -A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 # macro -A7XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 # macro -A7XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 # macro -A7XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 # macro -REG_A6XX_SP_DBG_ECO_CNTL = 0x0000ae00 # macro -REG_A6XX_SP_ADDR_MODE_CNTL = 0x0000ae01 # macro -REG_A6XX_SP_NC_MODE_CNTL = 0x0000ae02 # macro -REG_A6XX_SP_CHICKEN_BITS = 0x0000ae03 # macro -REG_A6XX_SP_FLOAT_CNTL = 0x0000ae04 # macro -A6XX_SP_FLOAT_CNTL_F16_NO_INF = 0x00000008 # macro -REG_A7XX_SP_UNKNOWN_AE06 = 0x0000ae06 # macro -REG_A7XX_SP_UNKNOWN_AE08 = 0x0000ae08 # macro -REG_A7XX_SP_UNKNOWN_AE09 = 0x0000ae09 # macro -REG_A7XX_SP_UNKNOWN_AE0A = 0x0000ae0a # macro -REG_A6XX_SP_PERFCTR_ENABLE = 0x0000ae0f # macro -A6XX_SP_PERFCTR_ENABLE_VS = 0x00000001 # macro -A6XX_SP_PERFCTR_ENABLE_HS = 0x00000002 # macro -A6XX_SP_PERFCTR_ENABLE_DS = 0x00000004 # macro -A6XX_SP_PERFCTR_ENABLE_GS = 0x00000008 # macro -A6XX_SP_PERFCTR_ENABLE_FS = 0x00000010 # macro -A6XX_SP_PERFCTR_ENABLE_CS = 0x00000020 # macro -# def REG_A6XX_SP_PERFCTR_SP_SEL(i0): # macro -# return (0x0000ae10+0x1*i0) -# def REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0): # macro -# return (0x0000ae60+0x1*i0) -REG_A7XX_SP_UNKNOWN_AE6A = 0x0000ae6a # macro -REG_A7XX_SP_UNKNOWN_AE6B = 0x0000ae6b # macro -REG_A7XX_SP_UNKNOWN_AE6C = 0x0000ae6c # macro -REG_A7XX_SP_READ_SEL = 0x0000ae6d # macro -A7XX_SP_READ_SEL_LOCATION__MASK = 0x000c0000 # macro -A7XX_SP_READ_SEL_LOCATION__SHIFT = 18 # macro -A7XX_SP_READ_SEL_PIPE__MASK = 0x00030000 # macro -A7XX_SP_READ_SEL_PIPE__SHIFT = 16 # macro -A7XX_SP_READ_SEL_STATETYPE__MASK = 0x0000ff00 # macro -A7XX_SP_READ_SEL_STATETYPE__SHIFT = 8 # macro -A7XX_SP_READ_SEL_USPTP__MASK = 0x000000f0 # macro -A7XX_SP_READ_SEL_USPTP__SHIFT = 4 # macro -A7XX_SP_READ_SEL_SPTP__MASK = 0x0000000f # macro -A7XX_SP_READ_SEL_SPTP__SHIFT = 0 # macro -REG_A7XX_SP_DBG_CNTL = 0x0000ae71 # macro -REG_A7XX_SP_UNKNOWN_AE73 = 0x0000ae73 # macro -# def REG_A7XX_SP_PERFCTR_SP_SEL(i0): # macro -# return (0x0000ae80+0x1*i0) -REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 # macro -REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR = 0x0000b180 # macro -REG_A6XX_SP_UNKNOWN_B182 = 0x0000b182 # macro -REG_A6XX_SP_UNKNOWN_B183 = 0x0000b183 # macro -REG_A6XX_SP_UNKNOWN_B190 = 0x0000b190 # macro -REG_A6XX_SP_UNKNOWN_B191 = 0x0000b191 # macro -REG_A6XX_SP_TP_RAS_MSAA_CNTL = 0x0000b300 # macro -A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK = 0x0000000c # macro -A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT = 2 # macro -REG_A6XX_SP_TP_DEST_MSAA_CNTL = 0x0000b301 # macro -A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro -A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro -A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro -REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR = 0x0000b302 # macro -REG_A6XX_SP_TP_SAMPLE_CONFIG = 0x0000b304 # macro -A6XX_SP_TP_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro -A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro -REG_A6XX_SP_TP_SAMPLE_LOCATION_0 = 0x0000b305 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_SP_TP_SAMPLE_LOCATION_1 = 0x0000b306 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro -REG_A6XX_SP_TP_WINDOW_OFFSET = 0x0000b307 # macro -A6XX_SP_TP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT = 0 # macro -A6XX_SP_TP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A6XX_SP_TP_MODE_CNTL = 0x0000b309 # macro -A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK = 0x00000003 # macro -A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT = 0 # macro -A6XX_SP_TP_MODE_CNTL_UNK3__MASK = 0x000000fc # macro -A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT = 2 # macro -REG_A7XX_SP_UNKNOWN_B310 = 0x0000b310 # macro -REG_A6XX_SP_PS_2D_SRC_INFO = 0x0000b4c0 # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 # macro -A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro -A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 # macro -A6XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 # macro -A6XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 # macro -A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 # macro -A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 # macro -A6XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 # macro -A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 # macro -A6XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 # macro -REG_A6XX_SP_PS_2D_SRC_SIZE = 0x0000b4c1 # macro -A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff # macro -A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 # macro -A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 # macro -A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 # macro -REG_A6XX_SP_PS_2D_SRC = 0x0000b4c2 # macro -REG_A6XX_SP_PS_2D_SRC_PITCH = 0x0000b4c4 # macro -A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff # macro -A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 # macro -A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 # macro -A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 # macro -REG_A7XX_SP_PS_2D_SRC_INFO = 0x0000b2c0 # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 # macro -A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 # macro -A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro -A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 # macro -A7XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 # macro -A7XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 # macro -A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 # macro -A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 # macro -A7XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 # macro -A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 # macro -A7XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 # macro -REG_A7XX_SP_PS_2D_SRC_SIZE = 0x0000b2c1 # macro -A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff # macro -A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 # macro -A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 # macro -A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 # macro -REG_A7XX_SP_PS_2D_SRC = 0x0000b2c2 # macro -REG_A7XX_SP_PS_2D_SRC_PITCH = 0x0000b2c4 # macro -A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff # macro -A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 # macro -A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 # macro -A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 # macro -REG_A6XX_SP_PS_2D_SRC_PLANE1 = 0x0000b4c5 # macro -REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b4c7 # macro -A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff # macro -A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 # macro -REG_A6XX_SP_PS_2D_SRC_PLANE2 = 0x0000b4c8 # macro -REG_A7XX_SP_PS_2D_SRC_PLANE1 = 0x0000b2c5 # macro -REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b2c7 # macro -A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff # macro -A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 # macro -REG_A7XX_SP_PS_2D_SRC_PLANE2 = 0x0000b2c8 # macro -REG_A6XX_SP_PS_2D_SRC_FLAGS = 0x0000b4ca # macro -REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b4cc # macro -A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff # macro -A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 # macro -REG_A7XX_SP_PS_2D_SRC_FLAGS = 0x0000b2ca # macro -REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b2cc # macro -A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff # macro -A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 # macro -REG_A6XX_SP_PS_UNKNOWN_B4CD = 0x0000b4cd # macro -REG_A6XX_SP_PS_UNKNOWN_B4CE = 0x0000b4ce # macro -REG_A6XX_SP_PS_UNKNOWN_B4CF = 0x0000b4cf # macro -REG_A6XX_SP_PS_UNKNOWN_B4D0 = 0x0000b4d0 # macro -REG_A6XX_SP_WINDOW_OFFSET = 0x0000b4d1 # macro -A6XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A6XX_SP_WINDOW_OFFSET_X__SHIFT = 0 # macro -A6XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A6XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A7XX_SP_PS_UNKNOWN_B4CD = 0x0000b2cd # macro -REG_A7XX_SP_PS_UNKNOWN_B4CE = 0x0000b2ce # macro -REG_A7XX_SP_PS_UNKNOWN_B4CF = 0x0000b2cf # macro -REG_A7XX_SP_PS_UNKNOWN_B4D0 = 0x0000b2d0 # macro -REG_A7XX_SP_PS_2D_WINDOW_OFFSET = 0x0000b2d1 # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT = 0 # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A7XX_SP_PS_UNKNOWN_B2D2 = 0x0000b2d2 # macro -REG_A7XX_SP_WINDOW_OFFSET = 0x0000ab21 # macro -A7XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro -A7XX_SP_WINDOW_OFFSET_X__SHIFT = 0 # macro -A7XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro -A7XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 # macro -REG_A6XX_TPL1_DBG_ECO_CNTL = 0x0000b600 # macro -REG_A6XX_TPL1_ADDR_MODE_CNTL = 0x0000b601 # macro -REG_A6XX_TPL1_DBG_ECO_CNTL1 = 0x0000b602 # macro -A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND = 0x00040000 # macro -REG_A6XX_TPL1_NC_MODE_CNTL = 0x0000b604 # macro -A6XX_TPL1_NC_MODE_CNTL_MODE = 0x00000001 # macro -A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 # macro -A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 # macro -A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 # macro -A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000010 # macro -A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT = 4 # macro -A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK = 0x000000c0 # macro -A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT = 6 # macro -REG_A6XX_TPL1_UNKNOWN_B605 = 0x0000b605 # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b # macro -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b # macro -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c # macro -# def REG_A6XX_TPL1_PERFCTR_TP_SEL(i0): # macro -# return (0x0000b610+0x1*i0) -# def REG_A7XX_TPL1_PERFCTR_TP_SEL(i0): # macro -# return (0x0000b610+0x1*i0) -REG_A6XX_HLSQ_VS_CNTL = 0x0000b800 # macro -A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_HS_CNTL = 0x0000b801 # macro -A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_DS_CNTL = 0x0000b802 # macro -A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_GS_CNTL = 0x0000b803 # macro -A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_VS_CNTL = 0x0000a827 # macro -A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_HS_CNTL = 0x0000a83f # macro -A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_DS_CNTL = 0x0000a867 # macro -A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_GS_CNTL = 0x0000a898 # macro -A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_FS_UNKNOWN_A9AA = 0x0000a9aa # macro -A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE = 0x00000001 # macro -REG_A7XX_HLSQ_UNKNOWN_A9AC = 0x0000a9ac # macro -REG_A7XX_HLSQ_UNKNOWN_A9AD = 0x0000a9ad # macro -REG_A7XX_HLSQ_UNKNOWN_A9AE = 0x0000a9ae # macro -A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK = 0x000000ff # macro -A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT = 0 # macro -A7XX_HLSQ_UNKNOWN_A9AE_UNK8 = 0x00000100 # macro -A7XX_HLSQ_UNKNOWN_A9AE_UNK9 = 0x00000200 # macro -REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD = 0x0000b820 # macro -REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR = 0x0000b821 # macro -REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA = 0x0000b823 # macro -REG_A6XX_HLSQ_FS_CNTL_0 = 0x0000b980 # macro -A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 # macro -A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 # macro -A6XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 # macro -A6XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc # macro -A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 # macro -REG_A6XX_HLSQ_UNKNOWN_B981 = 0x0000b981 # macro -REG_A6XX_HLSQ_CONTROL_1_REG = 0x0000b982 # macro -A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 # macro -A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 # macro -REG_A6XX_HLSQ_CONTROL_2_REG = 0x0000b983 # macro -A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 # macro -A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 # macro -A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 # macro -REG_A6XX_HLSQ_CONTROL_3_REG = 0x0000b984 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 # macro -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 # macro -REG_A6XX_HLSQ_CONTROL_4_REG = 0x0000b985 # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 # macro -A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 # macro -A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 # macro -A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 # macro -REG_A6XX_HLSQ_CONTROL_5_REG = 0x0000b986 # macro -A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff # macro -A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 # macro -A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 # macro -REG_A6XX_HLSQ_CS_CNTL = 0x0000b987 # macro -A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_FS_CNTL_0 = 0x0000a9c6 # macro -A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 # macro -A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 # macro -A7XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 # macro -A7XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc # macro -A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 # macro -REG_A7XX_HLSQ_CONTROL_1_REG = 0x0000a9c7 # macro -A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 # macro -A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 # macro -REG_A7XX_HLSQ_CONTROL_2_REG = 0x0000a9c8 # macro -A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 # macro -A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 # macro -A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 # macro -A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 # macro -REG_A7XX_HLSQ_CONTROL_3_REG = 0x0000a9c9 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 # macro -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 # macro -REG_A7XX_HLSQ_CONTROL_4_REG = 0x0000a9ca # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 # macro -A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 # macro -A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 # macro -A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 # macro -A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 # macro -REG_A7XX_HLSQ_CONTROL_5_REG = 0x0000a9cb # macro -A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff # macro -A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 # macro -A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 # macro -A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 # macro -REG_A7XX_HLSQ_CS_CNTL = 0x0000a9cd # macro -A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A6XX_HLSQ_CS_NDRANGE_0 = 0x0000b990 # macro -A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 # macro -A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 # macro -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 # macro -REG_A6XX_HLSQ_CS_NDRANGE_1 = 0x0000b991 # macro -A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_2 = 0x0000b992 # macro -A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_3 = 0x0000b993 # macro -A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_4 = 0x0000b994 # macro -A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_5 = 0x0000b995 # macro -A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_NDRANGE_6 = 0x0000b996 # macro -A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff # macro -A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 # macro -REG_A6XX_HLSQ_CS_CNTL_0 = 0x0000b997 # macro -A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff # macro -A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 # macro -A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 # macro -A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 # macro -A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 # macro -A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 # macro -REG_A6XX_HLSQ_CS_CNTL_1 = 0x0000b998 # macro -A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 # macro -A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro -A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro -A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 # macro -REG_A6XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000b999 # macro -REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000b99a # macro -REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000b99b # macro -REG_A7XX_HLSQ_CS_NDRANGE_0 = 0x0000a9d4 # macro -A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 # macro -A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 # macro -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 # macro -REG_A7XX_HLSQ_CS_NDRANGE_1 = 0x0000a9d5 # macro -A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_2 = 0x0000a9d6 # macro -A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_3 = 0x0000a9d7 # macro -A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_4 = 0x0000a9d8 # macro -A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_5 = 0x0000a9d9 # macro -A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_NDRANGE_6 = 0x0000a9da # macro -A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff # macro -A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 # macro -REG_A7XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000a9dc # macro -REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000a9dd # macro -REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000a9de # macro -REG_A7XX_HLSQ_CS_CNTL_1 = 0x0000a9db # macro -A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro -A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro -A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro -A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro -A7XX_HLSQ_CS_CNTL_1_UNK11 = 0x00000800 # macro -A7XX_HLSQ_CS_CNTL_1_UNK22 = 0x00400000 # macro -A7XX_HLSQ_CS_CNTL_1_UNK26 = 0x04000000 # macro -A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK = 0x78000000 # macro -A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT = 27 # macro -REG_A7XX_HLSQ_CS_LOCAL_SIZE = 0x0000a9df # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK = 0x00000ffc # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT = 2 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK = 0x003ff000 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT = 12 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK = 0xffc00000 # macro -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT = 22 # macro -REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD = 0x0000b9a0 # macro -REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR = 0x0000b9a1 # macro -REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA = 0x0000b9a3 # macro -# def REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0): # macro -# return (0x0000b9c0+0x2*i0) -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 = 0x0000b9d0 # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK = 0x0000001f # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT = 0 # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 = 0x00000020 # macro -A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 = 0x00000040 # macro -REG_A6XX_HLSQ_DRAW_CMD = 0x0000bb00 # macro -A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_HLSQ_DISPATCH_CMD = 0x0000bb01 # macro -A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro -A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro -REG_A6XX_HLSQ_EVENT_CMD = 0x0000bb02 # macro -A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro -A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 # macro -A6XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A6XX_HLSQ_INVALIDATE_CMD = 0x0000bb08 # macro -A6XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 # macro -A6XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 # macro -A6XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 # macro -A6XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 # macro -A6XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST = 0x00080000 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST = 0x00000100 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x00003e00 # macro -A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x0007c000 # macro -A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 14 # macro -REG_A7XX_HLSQ_DRAW_CMD = 0x0000ab1c # macro -A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro -A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 # macro -REG_A7XX_HLSQ_DISPATCH_CMD = 0x0000ab1d # macro -A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro -A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro -REG_A7XX_HLSQ_EVENT_CMD = 0x0000ab1e # macro -A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro -A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 # macro -A7XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A7XX_HLSQ_INVALIDATE_CMD = 0x0000ab1f # macro -A7XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 # macro -A7XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 # macro -A7XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 # macro -A7XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 # macro -A7XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 # macro -A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x0001fe00 # macro -A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 # macro -A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x01fe0000 # macro -A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 17 # macro -REG_A6XX_HLSQ_FS_CNTL = 0x0000bb10 # macro -A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 # macro -A6XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 # macro -A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -REG_A7XX_HLSQ_FS_CNTL = 0x0000ab03 # macro -A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff # macro -A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 # macro -A7XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 # macro -A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro -# def REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0): # macro -# return (0x0000ab40+0x1*i0) -REG_A6XX_HLSQ_SHARED_CONSTS = 0x0000bb11 # macro -A6XX_HLSQ_SHARED_CONSTS_ENABLE = 0x00000001 # macro -# def REG_A6XX_HLSQ_BINDLESS_BASE(i0): # macro -# return (0x0000bb20+0x2*i0) -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro -REG_A6XX_HLSQ_2D_EVENT_CMD = 0x0000bd80 # macro -A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 # macro -A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT = 8 # macro -A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK = 0x0000007f # macro -A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT = 0 # macro -REG_A6XX_HLSQ_UNKNOWN_BE00 = 0x0000be00 # macro -REG_A6XX_HLSQ_UNKNOWN_BE01 = 0x0000be01 # macro -REG_A6XX_HLSQ_DBG_ECO_CNTL = 0x0000be04 # macro -REG_A6XX_HLSQ_ADDR_MODE_CNTL = 0x0000be05 # macro -REG_A6XX_HLSQ_UNKNOWN_BE08 = 0x0000be08 # macro -# def REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0): # macro -# return (0x0000be10+0x1*i0) -REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 # macro -REG_A7XX_SP_AHB_READ_APERTURE = 0x0000c000 # macro -REG_A7XX_SP_UNKNOWN_0CE2 = 0x00000ce2 # macro -REG_A7XX_SP_UNKNOWN_0CE4 = 0x00000ce4 # macro -REG_A7XX_SP_UNKNOWN_0CE6 = 0x00000ce6 # macro -REG_A6XX_CP_EVENT_START = 0x0000d600 # macro -A6XX_CP_EVENT_START_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_EVENT_START_STATE_ID__SHIFT = 0 # macro -REG_A6XX_CP_EVENT_END = 0x0000d601 # macro -A6XX_CP_EVENT_END_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_EVENT_END_STATE_ID__SHIFT = 0 # macro -REG_A6XX_CP_2D_EVENT_START = 0x0000d700 # macro -A6XX_CP_2D_EVENT_START_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT = 0 # macro -REG_A6XX_CP_2D_EVENT_END = 0x0000d701 # macro -A6XX_CP_2D_EVENT_END_STATE_ID__MASK = 0x000000ff # macro -A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT = 0 # macro -REG_A6XX_TEX_SAMP_0 = 0x00000000 # macro -A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR = 0x00000001 # macro -A6XX_TEX_SAMP_0_XY_MAG__MASK = 0x00000006 # macro -A6XX_TEX_SAMP_0_XY_MAG__SHIFT = 1 # macro -A6XX_TEX_SAMP_0_XY_MIN__MASK = 0x00000018 # macro -A6XX_TEX_SAMP_0_XY_MIN__SHIFT = 3 # macro -A6XX_TEX_SAMP_0_WRAP_S__MASK = 0x000000e0 # macro -A6XX_TEX_SAMP_0_WRAP_S__SHIFT = 5 # macro -A6XX_TEX_SAMP_0_WRAP_T__MASK = 0x00000700 # macro -A6XX_TEX_SAMP_0_WRAP_T__SHIFT = 8 # macro -A6XX_TEX_SAMP_0_WRAP_R__MASK = 0x00003800 # macro -A6XX_TEX_SAMP_0_WRAP_R__SHIFT = 11 # macro -A6XX_TEX_SAMP_0_ANISO__MASK = 0x0001c000 # macro -A6XX_TEX_SAMP_0_ANISO__SHIFT = 14 # macro -A6XX_TEX_SAMP_0_LOD_BIAS__MASK = 0xfff80000 # macro -A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT = 19 # macro -REG_A6XX_TEX_SAMP_1 = 0x00000001 # macro -A6XX_TEX_SAMP_1_CLAMPENABLE = 0x00000001 # macro -A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK = 0x0000000e # macro -A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT = 1 # macro -A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF = 0x00000010 # macro -A6XX_TEX_SAMP_1_UNNORM_COORDS = 0x00000020 # macro -A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR = 0x00000040 # macro -A6XX_TEX_SAMP_1_MAX_LOD__MASK = 0x000fff00 # macro -A6XX_TEX_SAMP_1_MAX_LOD__SHIFT = 8 # macro -A6XX_TEX_SAMP_1_MIN_LOD__MASK = 0xfff00000 # macro -A6XX_TEX_SAMP_1_MIN_LOD__SHIFT = 20 # macro -REG_A6XX_TEX_SAMP_2 = 0x00000002 # macro -A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK = 0x00000003 # macro -A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT = 0 # macro -A6XX_TEX_SAMP_2_CHROMA_LINEAR = 0x00000020 # macro -A6XX_TEX_SAMP_2_BCOLOR__MASK = 0xffffff80 # macro -A6XX_TEX_SAMP_2_BCOLOR__SHIFT = 7 # macro -REG_A6XX_TEX_SAMP_3 = 0x00000003 # macro -REG_A6XX_TEX_CONST_0 = 0x00000000 # macro -A6XX_TEX_CONST_0_TILE_MODE__MASK = 0x00000003 # macro -A6XX_TEX_CONST_0_TILE_MODE__SHIFT = 0 # macro -A6XX_TEX_CONST_0_SRGB = 0x00000004 # macro -A6XX_TEX_CONST_0_SWIZ_X__MASK = 0x00000070 # macro -A6XX_TEX_CONST_0_SWIZ_X__SHIFT = 4 # macro -A6XX_TEX_CONST_0_SWIZ_Y__MASK = 0x00000380 # macro -A6XX_TEX_CONST_0_SWIZ_Y__SHIFT = 7 # macro -A6XX_TEX_CONST_0_SWIZ_Z__MASK = 0x00001c00 # macro -A6XX_TEX_CONST_0_SWIZ_Z__SHIFT = 10 # macro -A6XX_TEX_CONST_0_SWIZ_W__MASK = 0x0000e000 # macro -A6XX_TEX_CONST_0_SWIZ_W__SHIFT = 13 # macro -A6XX_TEX_CONST_0_MIPLVLS__MASK = 0x000f0000 # macro -A6XX_TEX_CONST_0_MIPLVLS__SHIFT = 16 # macro -A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X = 0x00010000 # macro -A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y = 0x00040000 # macro -A6XX_TEX_CONST_0_SAMPLES__MASK = 0x00300000 # macro -A6XX_TEX_CONST_0_SAMPLES__SHIFT = 20 # macro -A6XX_TEX_CONST_0_FMT__MASK = 0x3fc00000 # macro -A6XX_TEX_CONST_0_FMT__SHIFT = 22 # macro -A6XX_TEX_CONST_0_SWAP__MASK = 0xc0000000 # macro -A6XX_TEX_CONST_0_SWAP__SHIFT = 30 # macro -REG_A6XX_TEX_CONST_1 = 0x00000001 # macro -A6XX_TEX_CONST_1_WIDTH__MASK = 0x00007fff # macro -A6XX_TEX_CONST_1_WIDTH__SHIFT = 0 # macro -A6XX_TEX_CONST_1_HEIGHT__MASK = 0x3fff8000 # macro -A6XX_TEX_CONST_1_HEIGHT__SHIFT = 15 # macro -REG_A6XX_TEX_CONST_2 = 0x00000002 # macro -A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK = 0x0000fff0 # macro -A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT = 4 # macro -A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK = 0x003f0000 # macro -A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT = 16 # macro -A6XX_TEX_CONST_2_PITCHALIGN__MASK = 0x0000000f # macro -A6XX_TEX_CONST_2_PITCHALIGN__SHIFT = 0 # macro -A6XX_TEX_CONST_2_PITCH__MASK = 0x1fffff80 # macro -A6XX_TEX_CONST_2_PITCH__SHIFT = 7 # macro -A6XX_TEX_CONST_2_TYPE__MASK = 0xe0000000 # macro -A6XX_TEX_CONST_2_TYPE__SHIFT = 29 # macro -REG_A6XX_TEX_CONST_3 = 0x00000003 # macro -A6XX_TEX_CONST_3_ARRAY_PITCH__MASK = 0x007fffff # macro -A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT = 0 # macro -A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK = 0x07800000 # macro -A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT = 23 # macro -A6XX_TEX_CONST_3_TILE_ALL = 0x08000000 # macro -A6XX_TEX_CONST_3_FLAG = 0x10000000 # macro -REG_A6XX_TEX_CONST_4 = 0x00000004 # macro -A6XX_TEX_CONST_4_BASE_LO__MASK = 0xffffffe0 # macro -A6XX_TEX_CONST_4_BASE_LO__SHIFT = 5 # macro -REG_A6XX_TEX_CONST_5 = 0x00000005 # macro -A6XX_TEX_CONST_5_BASE_HI__MASK = 0x0001ffff # macro -A6XX_TEX_CONST_5_BASE_HI__SHIFT = 0 # macro -A6XX_TEX_CONST_5_DEPTH__MASK = 0x3ffe0000 # macro -A6XX_TEX_CONST_5_DEPTH__SHIFT = 17 # macro -REG_A6XX_TEX_CONST_6 = 0x00000006 # macro -A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK = 0x00000fff # macro -A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT = 0 # macro -A6XX_TEX_CONST_6_PLANE_PITCH__MASK = 0xffffff00 # macro -A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT = 8 # macro -REG_A6XX_TEX_CONST_7 = 0x00000007 # macro -A6XX_TEX_CONST_7_FLAG_LO__MASK = 0xffffffe0 # macro -A6XX_TEX_CONST_7_FLAG_LO__SHIFT = 5 # macro -REG_A6XX_TEX_CONST_8 = 0x00000008 # macro -A6XX_TEX_CONST_8_FLAG_HI__MASK = 0x0001ffff # macro -A6XX_TEX_CONST_8_FLAG_HI__SHIFT = 0 # macro -REG_A6XX_TEX_CONST_9 = 0x00000009 # macro -A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK = 0x0001ffff # macro -A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro -REG_A6XX_TEX_CONST_10 = 0x0000000a # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK = 0x0000007f # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT = 0 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK = 0x00000f00 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT = 8 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK = 0x0000f000 # macro -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT = 12 # macro -REG_A6XX_TEX_CONST_11 = 0x0000000b # macro -REG_A6XX_TEX_CONST_12 = 0x0000000c # macro -REG_A6XX_TEX_CONST_13 = 0x0000000d # macro -REG_A6XX_TEX_CONST_14 = 0x0000000e # macro -REG_A6XX_TEX_CONST_15 = 0x0000000f # macro -REG_A6XX_UBO_0 = 0x00000000 # macro -A6XX_UBO_0_BASE_LO__MASK = 0xffffffff # macro -A6XX_UBO_0_BASE_LO__SHIFT = 0 # macro -REG_A6XX_UBO_1 = 0x00000001 # macro -A6XX_UBO_1_BASE_HI__MASK = 0x0001ffff # macro -A6XX_UBO_1_BASE_HI__SHIFT = 0 # macro -A6XX_UBO_1_SIZE__MASK = 0xfffe0000 # macro -A6XX_UBO_1_SIZE__SHIFT = 17 # macro -REG_A6XX_PDC_GPU_ENABLE_PDC = 0x00001140 # macro -REG_A6XX_PDC_GPU_SEQ_START_ADDR = 0x00001148 # macro -REG_A6XX_PDC_GPU_TCS0_CONTROL = 0x00001540 # macro -REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK = 0x00001541 # macro -REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK = 0x00001542 # macro -REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID = 0x00001543 # macro -REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR = 0x00001544 # macro -REG_A6XX_PDC_GPU_TCS0_CMD0_DATA = 0x00001545 # macro -REG_A6XX_PDC_GPU_TCS1_CONTROL = 0x00001572 # macro -REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK = 0x00001573 # macro -REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK = 0x00001574 # macro -REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID = 0x00001575 # macro -REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR = 0x00001576 # macro -REG_A6XX_PDC_GPU_TCS1_CMD0_DATA = 0x00001577 # macro -REG_A6XX_PDC_GPU_TCS2_CONTROL = 0x000015a4 # macro -REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK = 0x000015a5 # macro -REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK = 0x000015a6 # macro -REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID = 0x000015a7 # macro -REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR = 0x000015a8 # macro -REG_A6XX_PDC_GPU_TCS2_CMD0_DATA = 0x000015a9 # macro -REG_A6XX_PDC_GPU_TCS3_CONTROL = 0x000015d6 # macro -REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK = 0x000015d7 # macro -REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK = 0x000015d8 # macro -REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID = 0x000015d9 # macro -REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR = 0x000015da # macro -REG_A6XX_PDC_GPU_TCS3_CMD0_DATA = 0x000015db # macro -REG_A6XX_PDC_GPU_SEQ_MEM_0 = 0x00000000 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A = 0x00000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK = 0x000000ff # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK = 0x0000ff00 # macro -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT = 8 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B = 0x00000001 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C = 0x00000002 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D = 0x00000003 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT = 0x00000004 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM = 0x00000005 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000008 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000009 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000000a # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000000b # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000000c # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000000d # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000000e # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000000f # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000010 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000011 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 # macro -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000002f # macro -REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000030 # macro -REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 = 0x00000001 # macro -REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 = 0x00000002 # macro -REG_A7XX_CX_MISC_TCM_RET_CNTL = 0x00000039 # macro -REG_A7XX_CX_MISC_SW_FUSE_VALUE = 0x00000400 # macro -A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND = 0x00000001 # macro -A7XX_CX_MISC_SW_FUSE_VALUE_LPAC = 0x00000002 # macro -A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING = 0x00000004 # macro - -# values for enumeration 'vgt_event_type' -vgt_event_type__enumvalues = { - 0: 'VS_DEALLOC', - 1: 'PS_DEALLOC', - 2: 'VS_DONE_TS', - 3: 'PS_DONE_TS', - 4: 'CACHE_FLUSH_TS', - 5: 'CONTEXT_DONE', - 6: 'CACHE_FLUSH', - 7: 'VIZQUERY_START', - 7: 'HLSQ_FLUSH', - 8: 'VIZQUERY_END', - 9: 'SC_WAIT_WC', - 9: 'WRITE_PRIMITIVE_COUNTS', - 11: 'START_PRIMITIVE_CTRS', - 12: 'STOP_PRIMITIVE_CTRS', - 13: 'RST_PIX_CNT', - 14: 'RST_VTX_CNT', - 15: 'TILE_FLUSH', - 16: 'STAT_EVENT', - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', - 21: 'ZPASS_DONE', - 22: 'CACHE_FLUSH_AND_INV_EVENT', - 22: 'RB_DONE_TS', - 23: 'PERFCOUNTER_START', - 24: 'PERFCOUNTER_STOP', - 27: 'VS_FETCH_DONE', - 28: 'FACENESS_FLUSH', - 8: 'WT_DONE_TS', - 13: 'START_FRAGMENT_CTRS', - 14: 'STOP_FRAGMENT_CTRS', - 15: 'START_COMPUTE_CTRS', - 16: 'STOP_COMPUTE_CTRS', - 17: 'FLUSH_SO_0', - 18: 'FLUSH_SO_1', - 19: 'FLUSH_SO_2', - 20: 'FLUSH_SO_3', - 24: 'PC_CCU_INVALIDATE_DEPTH', - 25: 'PC_CCU_INVALIDATE_COLOR', - 26: 'PC_CCU_RESOLVE_TS', - 28: 'PC_CCU_FLUSH_DEPTH_TS', - 29: 'PC_CCU_FLUSH_COLOR_TS', - 30: 'BLIT', - 36: 'LRZ_FLIP_BUFFER', - 37: 'LRZ_CLEAR', - 38: 'LRZ_FLUSH', - 39: 'BLIT_OP_FILL_2D', - 40: 'BLIT_OP_COPY_2D', - 40: 'UNK_40', - 42: 'BLIT_OP_SCALE_2D', - 43: 'CONTEXT_DONE_2D', - 44: 'UNK_2C', - 45: 'UNK_2D', - 49: 'CACHE_INVALIDATE', - 63: 'LABEL', - 1: 'DUMMY_EVENT', - 24: 'CCU_INVALIDATE_DEPTH', - 25: 'CCU_INVALIDATE_COLOR', - 26: 'CCU_RESOLVE_CLEAN', - 28: 'CCU_FLUSH_DEPTH', - 29: 'CCU_FLUSH_COLOR', - 30: 'CCU_RESOLVE', - 31: 'CCU_END_RESOLVE_GROUP', - 32: 'CCU_CLEAN_DEPTH', - 33: 'CCU_CLEAN_COLOR', - 48: 'CACHE_RESET', - 49: 'CACHE_CLEAN', - 50: 'CACHE_FLUSH7', - 51: 'CACHE_INVALIDATE7', -} -VS_DEALLOC = 0 -PS_DEALLOC = 1 -VS_DONE_TS = 2 -PS_DONE_TS = 3 -CACHE_FLUSH_TS = 4 -CONTEXT_DONE = 5 -CACHE_FLUSH = 6 -VIZQUERY_START = 7 -HLSQ_FLUSH = 7 -VIZQUERY_END = 8 -SC_WAIT_WC = 9 -WRITE_PRIMITIVE_COUNTS = 9 -START_PRIMITIVE_CTRS = 11 -STOP_PRIMITIVE_CTRS = 12 -RST_PIX_CNT = 13 -RST_VTX_CNT = 14 -TILE_FLUSH = 15 -STAT_EVENT = 16 -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -ZPASS_DONE = 21 -CACHE_FLUSH_AND_INV_EVENT = 22 -RB_DONE_TS = 22 -PERFCOUNTER_START = 23 -PERFCOUNTER_STOP = 24 -VS_FETCH_DONE = 27 -FACENESS_FLUSH = 28 -WT_DONE_TS = 8 -START_FRAGMENT_CTRS = 13 -STOP_FRAGMENT_CTRS = 14 -START_COMPUTE_CTRS = 15 -STOP_COMPUTE_CTRS = 16 -FLUSH_SO_0 = 17 -FLUSH_SO_1 = 18 -FLUSH_SO_2 = 19 -FLUSH_SO_3 = 20 -PC_CCU_INVALIDATE_DEPTH = 24 -PC_CCU_INVALIDATE_COLOR = 25 -PC_CCU_RESOLVE_TS = 26 -PC_CCU_FLUSH_DEPTH_TS = 28 -PC_CCU_FLUSH_COLOR_TS = 29 -BLIT = 30 -LRZ_FLIP_BUFFER = 36 -LRZ_CLEAR = 37 -LRZ_FLUSH = 38 -BLIT_OP_FILL_2D = 39 -BLIT_OP_COPY_2D = 40 -UNK_40 = 40 -BLIT_OP_SCALE_2D = 42 -CONTEXT_DONE_2D = 43 -UNK_2C = 44 -UNK_2D = 45 -CACHE_INVALIDATE = 49 -LABEL = 63 -DUMMY_EVENT = 1 -CCU_INVALIDATE_DEPTH = 24 -CCU_INVALIDATE_COLOR = 25 -CCU_RESOLVE_CLEAN = 26 -CCU_FLUSH_DEPTH = 28 -CCU_FLUSH_COLOR = 29 -CCU_RESOLVE = 30 -CCU_END_RESOLVE_GROUP = 31 -CCU_CLEAN_DEPTH = 32 -CCU_CLEAN_COLOR = 33 -CACHE_RESET = 48 -CACHE_CLEAN = 49 -CACHE_FLUSH7 = 50 -CACHE_INVALIDATE7 = 51 -vgt_event_type = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_primtype' -pc_di_primtype__enumvalues = { - 0: 'DI_PT_NONE', - 1: 'DI_PT_POINTLIST_PSIZE', - 2: 'DI_PT_LINELIST', - 3: 'DI_PT_LINESTRIP', - 4: 'DI_PT_TRILIST', - 5: 'DI_PT_TRIFAN', - 6: 'DI_PT_TRISTRIP', - 7: 'DI_PT_LINELOOP', - 8: 'DI_PT_RECTLIST', - 9: 'DI_PT_POINTLIST', - 10: 'DI_PT_LINE_ADJ', - 11: 'DI_PT_LINESTRIP_ADJ', - 12: 'DI_PT_TRI_ADJ', - 13: 'DI_PT_TRISTRIP_ADJ', - 31: 'DI_PT_PATCHES0', - 32: 'DI_PT_PATCHES1', - 33: 'DI_PT_PATCHES2', - 34: 'DI_PT_PATCHES3', - 35: 'DI_PT_PATCHES4', - 36: 'DI_PT_PATCHES5', - 37: 'DI_PT_PATCHES6', - 38: 'DI_PT_PATCHES7', - 39: 'DI_PT_PATCHES8', - 40: 'DI_PT_PATCHES9', - 41: 'DI_PT_PATCHES10', - 42: 'DI_PT_PATCHES11', - 43: 'DI_PT_PATCHES12', - 44: 'DI_PT_PATCHES13', - 45: 'DI_PT_PATCHES14', - 46: 'DI_PT_PATCHES15', - 47: 'DI_PT_PATCHES16', - 48: 'DI_PT_PATCHES17', - 49: 'DI_PT_PATCHES18', - 50: 'DI_PT_PATCHES19', - 51: 'DI_PT_PATCHES20', - 52: 'DI_PT_PATCHES21', - 53: 'DI_PT_PATCHES22', - 54: 'DI_PT_PATCHES23', - 55: 'DI_PT_PATCHES24', - 56: 'DI_PT_PATCHES25', - 57: 'DI_PT_PATCHES26', - 58: 'DI_PT_PATCHES27', - 59: 'DI_PT_PATCHES28', - 60: 'DI_PT_PATCHES29', - 61: 'DI_PT_PATCHES30', - 62: 'DI_PT_PATCHES31', -} -DI_PT_NONE = 0 -DI_PT_POINTLIST_PSIZE = 1 -DI_PT_LINELIST = 2 -DI_PT_LINESTRIP = 3 -DI_PT_TRILIST = 4 -DI_PT_TRIFAN = 5 -DI_PT_TRISTRIP = 6 -DI_PT_LINELOOP = 7 -DI_PT_RECTLIST = 8 -DI_PT_POINTLIST = 9 -DI_PT_LINE_ADJ = 10 -DI_PT_LINESTRIP_ADJ = 11 -DI_PT_TRI_ADJ = 12 -DI_PT_TRISTRIP_ADJ = 13 -DI_PT_PATCHES0 = 31 -DI_PT_PATCHES1 = 32 -DI_PT_PATCHES2 = 33 -DI_PT_PATCHES3 = 34 -DI_PT_PATCHES4 = 35 -DI_PT_PATCHES5 = 36 -DI_PT_PATCHES6 = 37 -DI_PT_PATCHES7 = 38 -DI_PT_PATCHES8 = 39 -DI_PT_PATCHES9 = 40 -DI_PT_PATCHES10 = 41 -DI_PT_PATCHES11 = 42 -DI_PT_PATCHES12 = 43 -DI_PT_PATCHES13 = 44 -DI_PT_PATCHES14 = 45 -DI_PT_PATCHES15 = 46 -DI_PT_PATCHES16 = 47 -DI_PT_PATCHES17 = 48 -DI_PT_PATCHES18 = 49 -DI_PT_PATCHES19 = 50 -DI_PT_PATCHES20 = 51 -DI_PT_PATCHES21 = 52 -DI_PT_PATCHES22 = 53 -DI_PT_PATCHES23 = 54 -DI_PT_PATCHES24 = 55 -DI_PT_PATCHES25 = 56 -DI_PT_PATCHES26 = 57 -DI_PT_PATCHES27 = 58 -DI_PT_PATCHES28 = 59 -DI_PT_PATCHES29 = 60 -DI_PT_PATCHES30 = 61 -DI_PT_PATCHES31 = 62 -pc_di_primtype = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_src_sel' -pc_di_src_sel__enumvalues = { - 0: 'DI_SRC_SEL_DMA', - 1: 'DI_SRC_SEL_IMMEDIATE', - 2: 'DI_SRC_SEL_AUTO_INDEX', - 3: 'DI_SRC_SEL_AUTO_XFB', -} -DI_SRC_SEL_DMA = 0 -DI_SRC_SEL_IMMEDIATE = 1 -DI_SRC_SEL_AUTO_INDEX = 2 -DI_SRC_SEL_AUTO_XFB = 3 -pc_di_src_sel = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_face_cull_sel' -pc_di_face_cull_sel__enumvalues = { - 0: 'DI_FACE_CULL_NONE', - 1: 'DI_FACE_CULL_FETCH', - 2: 'DI_FACE_BACKFACE_CULL', - 3: 'DI_FACE_FRONTFACE_CULL', -} -DI_FACE_CULL_NONE = 0 -DI_FACE_CULL_FETCH = 1 -DI_FACE_BACKFACE_CULL = 2 -DI_FACE_FRONTFACE_CULL = 3 -pc_di_face_cull_sel = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_index_size' -pc_di_index_size__enumvalues = { - 0: 'INDEX_SIZE_IGN', - 0: 'INDEX_SIZE_16_BIT', - 1: 'INDEX_SIZE_32_BIT', - 2: 'INDEX_SIZE_8_BIT', - 0: 'INDEX_SIZE_INVALID', -} -INDEX_SIZE_IGN = 0 -INDEX_SIZE_16_BIT = 0 -INDEX_SIZE_32_BIT = 1 -INDEX_SIZE_8_BIT = 2 -INDEX_SIZE_INVALID = 0 -pc_di_index_size = ctypes.c_uint32 # enum - -# values for enumeration 'pc_di_vis_cull_mode' -pc_di_vis_cull_mode__enumvalues = { - 0: 'IGNORE_VISIBILITY', - 1: 'USE_VISIBILITY', -} -IGNORE_VISIBILITY = 0 -USE_VISIBILITY = 1 -pc_di_vis_cull_mode = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_pm4_packet_type' -adreno_pm4_packet_type__enumvalues = { - 0: 'CP_TYPE0_PKT', - 1073741824: 'CP_TYPE1_PKT', - 2147483648: 'CP_TYPE2_PKT', - 3221225472: 'CP_TYPE3_PKT', - 1073741824: 'CP_TYPE4_PKT', - 1879048192: 'CP_TYPE7_PKT', -} -CP_TYPE0_PKT = 0 -CP_TYPE1_PKT = 1073741824 -CP_TYPE2_PKT = 2147483648 -CP_TYPE3_PKT = 3221225472 -CP_TYPE4_PKT = 1073741824 -CP_TYPE7_PKT = 1879048192 -adreno_pm4_packet_type = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_pm4_type3_packets' -adreno_pm4_type3_packets__enumvalues = { - 72: 'CP_ME_INIT', - 16: 'CP_NOP', - 28: 'CP_PREEMPT_ENABLE', - 30: 'CP_PREEMPT_TOKEN', - 63: 'CP_INDIRECT_BUFFER', - 87: 'CP_INDIRECT_BUFFER_CHAIN', - 55: 'CP_INDIRECT_BUFFER_PFD', - 38: 'CP_WAIT_FOR_IDLE', - 60: 'CP_WAIT_REG_MEM', - 82: 'CP_WAIT_REG_EQ', - 83: 'CP_WAIT_REG_GTE', - 92: 'CP_WAIT_UNTIL_READ', - 93: 'CP_WAIT_IB_PFD_COMPLETE', - 33: 'CP_REG_RMW', - 47: 'CP_SET_BIN_DATA', - 47: 'CP_SET_BIN_DATA5', - 62: 'CP_REG_TO_MEM', - 61: 'CP_MEM_WRITE', - 79: 'CP_MEM_WRITE_CNTR', - 68: 'CP_COND_EXEC', - 69: 'CP_COND_WRITE', - 69: 'CP_COND_WRITE5', - 70: 'CP_EVENT_WRITE', - 70: 'CP_EVENT_WRITE7', - 88: 'CP_EVENT_WRITE_SHD', - 89: 'CP_EVENT_WRITE_CFL', - 91: 'CP_EVENT_WRITE_ZPD', - 49: 'CP_RUN_OPENCL', - 34: 'CP_DRAW_INDX', - 54: 'CP_DRAW_INDX_2', - 52: 'CP_DRAW_INDX_BIN', - 53: 'CP_DRAW_INDX_2_BIN', - 35: 'CP_VIZ_QUERY', - 37: 'CP_SET_STATE', - 45: 'CP_SET_CONSTANT', - 39: 'CP_IM_LOAD', - 43: 'CP_IM_LOAD_IMMEDIATE', - 46: 'CP_LOAD_CONSTANT_CONTEXT', - 59: 'CP_INVALIDATE_STATE', - 74: 'CP_SET_SHADER_BASES', - 80: 'CP_SET_BIN_MASK', - 81: 'CP_SET_BIN_SELECT', - 94: 'CP_CONTEXT_UPDATE', - 64: 'CP_INTERRUPT', - 44: 'CP_IM_STORE', - 75: 'CP_SET_DRAW_INIT_FLAGS', - 95: 'CP_SET_PROTECTED_MODE', - 111: 'CP_BOOTSTRAP_UCODE', - 48: 'CP_LOAD_STATE', - 48: 'CP_LOAD_STATE4', - 58: 'CP_COND_INDIRECT_BUFFER_PFE', - 50: 'CP_COND_INDIRECT_BUFFER_PFD', - 63: 'CP_INDIRECT_BUFFER_PFE', - 76: 'CP_SET_BIN', - 113: 'CP_TEST_TWO_MEMS', - 120: 'CP_REG_WR_NO_CTXT', - 17: 'CP_RECORD_PFP_TIMESTAMP', - 102: 'CP_SET_SECURE_MODE', - 19: 'CP_WAIT_FOR_ME', - 67: 'CP_SET_DRAW_STATE', - 56: 'CP_DRAW_INDX_OFFSET', - 40: 'CP_DRAW_INDIRECT', - 41: 'CP_DRAW_INDX_INDIRECT', - 42: 'CP_DRAW_INDIRECT_MULTI', - 36: 'CP_DRAW_AUTO', - 25: 'CP_DRAW_PRED_ENABLE_GLOBAL', - 26: 'CP_DRAW_PRED_ENABLE_LOCAL', - 78: 'CP_DRAW_PRED_SET', - 116: 'CP_WIDE_REG_WRITE', - 77: 'CP_SCRATCH_TO_REG', - 74: 'CP_REG_TO_SCRATCH', - 18: 'CP_WAIT_MEM_WRITES', - 71: 'CP_COND_REG_EXEC', - 66: 'CP_MEM_TO_REG', - 65: 'CP_EXEC_CS_INDIRECT', - 51: 'CP_EXEC_CS', - 80: 'CP_PERFCOUNTER_ACTION', - 83: 'CP_SMMU_TABLE_UPDATE', - 101: 'CP_SET_MARKER', - 86: 'CP_SET_PSEUDO_REG', - 92: 'CP_CONTEXT_REG_BUNCH', - 28: 'CP_YIELD_ENABLE', - 29: 'CP_SKIP_IB2_ENABLE_GLOBAL', - 35: 'CP_SKIP_IB2_ENABLE_LOCAL', - 53: 'CP_SET_SUBDRAW_SIZE', - 98: 'CP_WHERE_AM_I', - 100: 'CP_SET_VISIBILITY_OVERRIDE', - 105: 'CP_PREEMPT_ENABLE_GLOBAL', - 106: 'CP_PREEMPT_ENABLE_LOCAL', - 107: 'CP_CONTEXT_SWITCH_YIELD', - 108: 'CP_SET_RENDER_MODE', - 110: 'CP_COMPUTE_CHECKPOINT', - 115: 'CP_MEM_TO_MEM', - 44: 'CP_BLIT', - 57: 'CP_REG_TEST', - 99: 'CP_SET_MODE', - 50: 'CP_LOAD_STATE6_GEOM', - 52: 'CP_LOAD_STATE6_FRAG', - 54: 'CP_LOAD_STATE6', - 23: 'IN_IB_PREFETCH_END', - 31: 'IN_SUBBLK_PREFETCH', - 32: 'IN_INSTR_PREFETCH', - 71: 'IN_INSTR_MATCH', - 73: 'IN_CONST_PREFETCH', - 85: 'IN_INCR_UPDT_STATE', - 86: 'IN_INCR_UPDT_CONST', - 87: 'IN_INCR_UPDT_INSTR', - 4: 'PKT4', - 10: 'IN_IB_END', - 11: 'IN_GMU_INTERRUPT', - 15: 'IN_PREEMPT', - 76: 'CP_SCRATCH_WRITE', - 116: 'CP_REG_TO_MEM_OFFSET_MEM', - 114: 'CP_REG_TO_MEM_OFFSET_REG', - 20: 'CP_WAIT_MEM_GTE', - 112: 'CP_WAIT_TWO_REGS', - 117: 'CP_MEMCPY', - 46: 'CP_SET_BIN_DATA5_OFFSET', - 45: 'CP_SET_UNK_BIN_DATA', - 84: 'CP_CONTEXT_SWITCH', - 85: 'CP_SET_CTXSWITCH_IB', - 109: 'CP_REG_WRITE', - 80: 'CP_START_BIN', - 81: 'CP_END_BIN', - 108: 'CP_PREEMPT_DISABLE', - 20: 'CP_WAIT_TIMESTAMP', - 21: 'CP_GLOBAL_TIMESTAMP', - 22: 'CP_LOCAL_TIMESTAMP', - 23: 'CP_THREAD_CONTROL', - 24: 'CP_RESOURCE_LIST', - 27: 'CP_BV_BR_COUNT_OPS', - 28: 'CP_MODIFY_TIMESTAMP', - 93: 'CP_CONTEXT_REG_BUNCH2', - 73: 'CP_MEM_TO_SCRATCH_MEM', - 127: 'CP_FIXED_STRIDE_DRAW_TABLE', - 31: 'CP_RESET_CONTEXT_STATE', - 58: 'CP_CCHE_INVALIDATE', -} -CP_ME_INIT = 72 -CP_NOP = 16 -CP_PREEMPT_ENABLE = 28 -CP_PREEMPT_TOKEN = 30 -CP_INDIRECT_BUFFER = 63 -CP_INDIRECT_BUFFER_CHAIN = 87 -CP_INDIRECT_BUFFER_PFD = 55 -CP_WAIT_FOR_IDLE = 38 -CP_WAIT_REG_MEM = 60 -CP_WAIT_REG_EQ = 82 -CP_WAIT_REG_GTE = 83 -CP_WAIT_UNTIL_READ = 92 -CP_WAIT_IB_PFD_COMPLETE = 93 -CP_REG_RMW = 33 -CP_SET_BIN_DATA = 47 -CP_SET_BIN_DATA5 = 47 -CP_REG_TO_MEM = 62 -CP_MEM_WRITE = 61 -CP_MEM_WRITE_CNTR = 79 -CP_COND_EXEC = 68 -CP_COND_WRITE = 69 -CP_COND_WRITE5 = 69 -CP_EVENT_WRITE = 70 -CP_EVENT_WRITE7 = 70 -CP_EVENT_WRITE_SHD = 88 -CP_EVENT_WRITE_CFL = 89 -CP_EVENT_WRITE_ZPD = 91 -CP_RUN_OPENCL = 49 -CP_DRAW_INDX = 34 -CP_DRAW_INDX_2 = 54 -CP_DRAW_INDX_BIN = 52 -CP_DRAW_INDX_2_BIN = 53 -CP_VIZ_QUERY = 35 -CP_SET_STATE = 37 -CP_SET_CONSTANT = 45 -CP_IM_LOAD = 39 -CP_IM_LOAD_IMMEDIATE = 43 -CP_LOAD_CONSTANT_CONTEXT = 46 -CP_INVALIDATE_STATE = 59 -CP_SET_SHADER_BASES = 74 -CP_SET_BIN_MASK = 80 -CP_SET_BIN_SELECT = 81 -CP_CONTEXT_UPDATE = 94 -CP_INTERRUPT = 64 -CP_IM_STORE = 44 -CP_SET_DRAW_INIT_FLAGS = 75 -CP_SET_PROTECTED_MODE = 95 -CP_BOOTSTRAP_UCODE = 111 -CP_LOAD_STATE = 48 -CP_LOAD_STATE4 = 48 -CP_COND_INDIRECT_BUFFER_PFE = 58 -CP_COND_INDIRECT_BUFFER_PFD = 50 -CP_INDIRECT_BUFFER_PFE = 63 -CP_SET_BIN = 76 -CP_TEST_TWO_MEMS = 113 -CP_REG_WR_NO_CTXT = 120 -CP_RECORD_PFP_TIMESTAMP = 17 -CP_SET_SECURE_MODE = 102 -CP_WAIT_FOR_ME = 19 -CP_SET_DRAW_STATE = 67 -CP_DRAW_INDX_OFFSET = 56 -CP_DRAW_INDIRECT = 40 -CP_DRAW_INDX_INDIRECT = 41 -CP_DRAW_INDIRECT_MULTI = 42 -CP_DRAW_AUTO = 36 -CP_DRAW_PRED_ENABLE_GLOBAL = 25 -CP_DRAW_PRED_ENABLE_LOCAL = 26 -CP_DRAW_PRED_SET = 78 -CP_WIDE_REG_WRITE = 116 -CP_SCRATCH_TO_REG = 77 -CP_REG_TO_SCRATCH = 74 -CP_WAIT_MEM_WRITES = 18 -CP_COND_REG_EXEC = 71 -CP_MEM_TO_REG = 66 -CP_EXEC_CS_INDIRECT = 65 -CP_EXEC_CS = 51 -CP_PERFCOUNTER_ACTION = 80 -CP_SMMU_TABLE_UPDATE = 83 -CP_SET_MARKER = 101 -CP_SET_PSEUDO_REG = 86 -CP_CONTEXT_REG_BUNCH = 92 -CP_YIELD_ENABLE = 28 -CP_SKIP_IB2_ENABLE_GLOBAL = 29 -CP_SKIP_IB2_ENABLE_LOCAL = 35 -CP_SET_SUBDRAW_SIZE = 53 -CP_WHERE_AM_I = 98 -CP_SET_VISIBILITY_OVERRIDE = 100 -CP_PREEMPT_ENABLE_GLOBAL = 105 -CP_PREEMPT_ENABLE_LOCAL = 106 -CP_CONTEXT_SWITCH_YIELD = 107 -CP_SET_RENDER_MODE = 108 -CP_COMPUTE_CHECKPOINT = 110 -CP_MEM_TO_MEM = 115 -CP_BLIT = 44 -CP_REG_TEST = 57 -CP_SET_MODE = 99 -CP_LOAD_STATE6_GEOM = 50 -CP_LOAD_STATE6_FRAG = 52 -CP_LOAD_STATE6 = 54 -IN_IB_PREFETCH_END = 23 -IN_SUBBLK_PREFETCH = 31 -IN_INSTR_PREFETCH = 32 -IN_INSTR_MATCH = 71 -IN_CONST_PREFETCH = 73 -IN_INCR_UPDT_STATE = 85 -IN_INCR_UPDT_CONST = 86 -IN_INCR_UPDT_INSTR = 87 -PKT4 = 4 -IN_IB_END = 10 -IN_GMU_INTERRUPT = 11 -IN_PREEMPT = 15 -CP_SCRATCH_WRITE = 76 -CP_REG_TO_MEM_OFFSET_MEM = 116 -CP_REG_TO_MEM_OFFSET_REG = 114 -CP_WAIT_MEM_GTE = 20 -CP_WAIT_TWO_REGS = 112 -CP_MEMCPY = 117 -CP_SET_BIN_DATA5_OFFSET = 46 -CP_SET_UNK_BIN_DATA = 45 -CP_CONTEXT_SWITCH = 84 -CP_SET_CTXSWITCH_IB = 85 -CP_REG_WRITE = 109 -CP_START_BIN = 80 -CP_END_BIN = 81 -CP_PREEMPT_DISABLE = 108 -CP_WAIT_TIMESTAMP = 20 -CP_GLOBAL_TIMESTAMP = 21 -CP_LOCAL_TIMESTAMP = 22 -CP_THREAD_CONTROL = 23 -CP_RESOURCE_LIST = 24 -CP_BV_BR_COUNT_OPS = 27 -CP_MODIFY_TIMESTAMP = 28 -CP_CONTEXT_REG_BUNCH2 = 93 -CP_MEM_TO_SCRATCH_MEM = 73 -CP_FIXED_STRIDE_DRAW_TABLE = 127 -CP_RESET_CONTEXT_STATE = 31 -CP_CCHE_INVALIDATE = 58 -adreno_pm4_type3_packets = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_state_block' -adreno_state_block__enumvalues = { - 0: 'SB_VERT_TEX', - 1: 'SB_VERT_MIPADDR', - 2: 'SB_FRAG_TEX', - 3: 'SB_FRAG_MIPADDR', - 4: 'SB_VERT_SHADER', - 5: 'SB_GEOM_SHADER', - 6: 'SB_FRAG_SHADER', - 7: 'SB_COMPUTE_SHADER', -} -SB_VERT_TEX = 0 -SB_VERT_MIPADDR = 1 -SB_FRAG_TEX = 2 -SB_FRAG_MIPADDR = 3 -SB_VERT_SHADER = 4 -SB_GEOM_SHADER = 5 -SB_FRAG_SHADER = 6 -SB_COMPUTE_SHADER = 7 -adreno_state_block = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_state_type' -adreno_state_type__enumvalues = { - 0: 'ST_SHADER', - 1: 'ST_CONSTANTS', -} -ST_SHADER = 0 -ST_CONSTANTS = 1 -adreno_state_type = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_state_src' -adreno_state_src__enumvalues = { - 0: 'SS_DIRECT', - 2: 'SS_INVALID_ALL_IC', - 3: 'SS_INVALID_PART_IC', - 4: 'SS_INDIRECT', - 5: 'SS_INDIRECT_TCM', - 6: 'SS_INDIRECT_STM', -} -SS_DIRECT = 0 -SS_INVALID_ALL_IC = 2 -SS_INVALID_PART_IC = 3 -SS_INDIRECT = 4 -SS_INDIRECT_TCM = 5 -SS_INDIRECT_STM = 6 -adreno_state_src = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_state_block' -a4xx_state_block__enumvalues = { - 0: 'SB4_VS_TEX', - 1: 'SB4_HS_TEX', - 2: 'SB4_DS_TEX', - 3: 'SB4_GS_TEX', - 4: 'SB4_FS_TEX', - 5: 'SB4_CS_TEX', - 8: 'SB4_VS_SHADER', - 9: 'SB4_HS_SHADER', - 10: 'SB4_DS_SHADER', - 11: 'SB4_GS_SHADER', - 12: 'SB4_FS_SHADER', - 13: 'SB4_CS_SHADER', - 14: 'SB4_SSBO', - 15: 'SB4_CS_SSBO', -} -SB4_VS_TEX = 0 -SB4_HS_TEX = 1 -SB4_DS_TEX = 2 -SB4_GS_TEX = 3 -SB4_FS_TEX = 4 -SB4_CS_TEX = 5 -SB4_VS_SHADER = 8 -SB4_HS_SHADER = 9 -SB4_DS_SHADER = 10 -SB4_GS_SHADER = 11 -SB4_FS_SHADER = 12 -SB4_CS_SHADER = 13 -SB4_SSBO = 14 -SB4_CS_SSBO = 15 -a4xx_state_block = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_state_type' -a4xx_state_type__enumvalues = { - 0: 'ST4_SHADER', - 1: 'ST4_CONSTANTS', - 2: 'ST4_UBO', -} -ST4_SHADER = 0 -ST4_CONSTANTS = 1 -ST4_UBO = 2 -a4xx_state_type = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_state_src' -a4xx_state_src__enumvalues = { - 0: 'SS4_DIRECT', - 2: 'SS4_INDIRECT', -} -SS4_DIRECT = 0 -SS4_INDIRECT = 2 -a4xx_state_src = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_state_block' -a6xx_state_block__enumvalues = { - 0: 'SB6_VS_TEX', - 1: 'SB6_HS_TEX', - 2: 'SB6_DS_TEX', - 3: 'SB6_GS_TEX', - 4: 'SB6_FS_TEX', - 5: 'SB6_CS_TEX', - 8: 'SB6_VS_SHADER', - 9: 'SB6_HS_SHADER', - 10: 'SB6_DS_SHADER', - 11: 'SB6_GS_SHADER', - 12: 'SB6_FS_SHADER', - 13: 'SB6_CS_SHADER', - 14: 'SB6_IBO', - 15: 'SB6_CS_IBO', -} -SB6_VS_TEX = 0 -SB6_HS_TEX = 1 -SB6_DS_TEX = 2 -SB6_GS_TEX = 3 -SB6_FS_TEX = 4 -SB6_CS_TEX = 5 -SB6_VS_SHADER = 8 -SB6_HS_SHADER = 9 -SB6_DS_SHADER = 10 -SB6_GS_SHADER = 11 -SB6_FS_SHADER = 12 -SB6_CS_SHADER = 13 -SB6_IBO = 14 -SB6_CS_IBO = 15 -a6xx_state_block = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_state_type' -a6xx_state_type__enumvalues = { - 0: 'ST6_SHADER', - 1: 'ST6_CONSTANTS', - 2: 'ST6_UBO', - 3: 'ST6_IBO', -} -ST6_SHADER = 0 -ST6_CONSTANTS = 1 -ST6_UBO = 2 -ST6_IBO = 3 -a6xx_state_type = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_state_src' -a6xx_state_src__enumvalues = { - 0: 'SS6_DIRECT', - 1: 'SS6_BINDLESS', - 2: 'SS6_INDIRECT', - 3: 'SS6_UBO', -} -SS6_DIRECT = 0 -SS6_BINDLESS = 1 -SS6_INDIRECT = 2 -SS6_UBO = 3 -a6xx_state_src = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_index_size' -a4xx_index_size__enumvalues = { - 0: 'INDEX4_SIZE_8_BIT', - 1: 'INDEX4_SIZE_16_BIT', - 2: 'INDEX4_SIZE_32_BIT', -} -INDEX4_SIZE_8_BIT = 0 -INDEX4_SIZE_16_BIT = 1 -INDEX4_SIZE_32_BIT = 2 -a4xx_index_size = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_patch_type' -a6xx_patch_type__enumvalues = { - 0: 'TESS_QUADS', - 1: 'TESS_TRIANGLES', - 2: 'TESS_ISOLINES', -} -TESS_QUADS = 0 -TESS_TRIANGLES = 1 -TESS_ISOLINES = 2 -a6xx_patch_type = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_draw_indirect_opcode' -a6xx_draw_indirect_opcode__enumvalues = { - 2: 'INDIRECT_OP_NORMAL', - 4: 'INDIRECT_OP_INDEXED', - 6: 'INDIRECT_OP_INDIRECT_COUNT', - 7: 'INDIRECT_OP_INDIRECT_COUNT_INDEXED', -} -INDIRECT_OP_NORMAL = 2 -INDIRECT_OP_INDEXED = 4 -INDIRECT_OP_INDIRECT_COUNT = 6 -INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7 -a6xx_draw_indirect_opcode = ctypes.c_uint32 # enum - -# values for enumeration 'cp_draw_pred_src' -cp_draw_pred_src__enumvalues = { - 5: 'PRED_SRC_MEM', -} -PRED_SRC_MEM = 5 -cp_draw_pred_src = ctypes.c_uint32 # enum - -# values for enumeration 'cp_draw_pred_test' -cp_draw_pred_test__enumvalues = { - 0: 'NE_0_PASS', - 1: 'EQ_0_PASS', -} -NE_0_PASS = 0 -EQ_0_PASS = 1 -cp_draw_pred_test = ctypes.c_uint32 # enum - -# values for enumeration 'cp_cond_function' -cp_cond_function__enumvalues = { - 0: 'WRITE_ALWAYS', - 1: 'WRITE_LT', - 2: 'WRITE_LE', - 3: 'WRITE_EQ', - 4: 'WRITE_NE', - 5: 'WRITE_GE', - 6: 'WRITE_GT', -} -WRITE_ALWAYS = 0 -WRITE_LT = 1 -WRITE_LE = 2 -WRITE_EQ = 3 -WRITE_NE = 4 -WRITE_GE = 5 -WRITE_GT = 6 -cp_cond_function = ctypes.c_uint32 # enum - -# values for enumeration 'poll_memory_type' -poll_memory_type__enumvalues = { - 0: 'POLL_REGISTER', - 1: 'POLL_MEMORY', - 2: 'POLL_SCRATCH', - 3: 'POLL_ON_CHIP', -} -POLL_REGISTER = 0 -POLL_MEMORY = 1 -POLL_SCRATCH = 2 -POLL_ON_CHIP = 3 -poll_memory_type = ctypes.c_uint32 # enum - -# values for enumeration 'render_mode_cmd' -render_mode_cmd__enumvalues = { - 1: 'BYPASS', - 2: 'BINNING', - 3: 'GMEM', - 5: 'BLIT2D', - 7: 'BLIT2DSCALE', - 8: 'END2D', -} -BYPASS = 1 -BINNING = 2 -GMEM = 3 -BLIT2D = 5 -BLIT2DSCALE = 7 -END2D = 8 -render_mode_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'event_write_src' -event_write_src__enumvalues = { - 0: 'EV_WRITE_USER_32B', - 1: 'EV_WRITE_USER_64B', - 2: 'EV_WRITE_TIMESTAMP_SUM', - 3: 'EV_WRITE_ALWAYSON', - 4: 'EV_WRITE_REGS_CONTENT', -} -EV_WRITE_USER_32B = 0 -EV_WRITE_USER_64B = 1 -EV_WRITE_TIMESTAMP_SUM = 2 -EV_WRITE_ALWAYSON = 3 -EV_WRITE_REGS_CONTENT = 4 -event_write_src = ctypes.c_uint32 # enum - -# values for enumeration 'event_write_dst' -event_write_dst__enumvalues = { - 0: 'EV_DST_RAM', - 1: 'EV_DST_ONCHIP', -} -EV_DST_RAM = 0 -EV_DST_ONCHIP = 1 -event_write_dst = ctypes.c_uint32 # enum - -# values for enumeration 'cp_blit_cmd' -cp_blit_cmd__enumvalues = { - 0: 'BLIT_OP_FILL', - 1: 'BLIT_OP_COPY', - 3: 'BLIT_OP_SCALE', -} -BLIT_OP_FILL = 0 -BLIT_OP_COPY = 1 -BLIT_OP_SCALE = 3 -cp_blit_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_marker' -a6xx_marker__enumvalues = { - 1: 'RM6_BYPASS', - 2: 'RM6_BINNING', - 4: 'RM6_GMEM', - 5: 'RM6_ENDVIS', - 6: 'RM6_RESOLVE', - 7: 'RM6_YIELD', - 8: 'RM6_COMPUTE', - 12: 'RM6_BLIT2DSCALE', - 13: 'RM6_IB1LIST_START', - 14: 'RM6_IB1LIST_END', - 256: 'RM6_IFPC_ENABLE', - 257: 'RM6_IFPC_DISABLE', -} -RM6_BYPASS = 1 -RM6_BINNING = 2 -RM6_GMEM = 4 -RM6_ENDVIS = 5 -RM6_RESOLVE = 6 -RM6_YIELD = 7 -RM6_COMPUTE = 8 -RM6_BLIT2DSCALE = 12 -RM6_IB1LIST_START = 13 -RM6_IB1LIST_END = 14 -RM6_IFPC_ENABLE = 256 -RM6_IFPC_DISABLE = 257 -a6xx_marker = ctypes.c_uint32 # enum - -# values for enumeration 'pseudo_reg' -pseudo_reg__enumvalues = { - 0: 'SMMU_INFO', - 1: 'NON_SECURE_SAVE_ADDR', - 2: 'SECURE_SAVE_ADDR', - 3: 'NON_PRIV_SAVE_ADDR', - 4: 'COUNTER', - 8: 'DRAW_STRM_ADDRESS', - 9: 'DRAW_STRM_SIZE_ADDRESS', - 10: 'PRIM_STRM_ADDRESS', - 11: 'UNK_STRM_ADDRESS', - 12: 'UNK_STRM_SIZE_ADDRESS', - 16: 'BINDLESS_BASE_0_ADDR', - 17: 'BINDLESS_BASE_1_ADDR', - 18: 'BINDLESS_BASE_2_ADDR', - 19: 'BINDLESS_BASE_3_ADDR', - 20: 'BINDLESS_BASE_4_ADDR', - 21: 'BINDLESS_BASE_5_ADDR', - 22: 'BINDLESS_BASE_6_ADDR', -} -SMMU_INFO = 0 -NON_SECURE_SAVE_ADDR = 1 -SECURE_SAVE_ADDR = 2 -NON_PRIV_SAVE_ADDR = 3 -COUNTER = 4 -DRAW_STRM_ADDRESS = 8 -DRAW_STRM_SIZE_ADDRESS = 9 -PRIM_STRM_ADDRESS = 10 -UNK_STRM_ADDRESS = 11 -UNK_STRM_SIZE_ADDRESS = 12 -BINDLESS_BASE_0_ADDR = 16 -BINDLESS_BASE_1_ADDR = 17 -BINDLESS_BASE_2_ADDR = 18 -BINDLESS_BASE_3_ADDR = 19 -BINDLESS_BASE_4_ADDR = 20 -BINDLESS_BASE_5_ADDR = 21 -BINDLESS_BASE_6_ADDR = 22 -pseudo_reg = ctypes.c_uint32 # enum - -# values for enumeration 'source_type' -source_type__enumvalues = { - 0: 'SOURCE_REG', - 1: 'SOURCE_SCRATCH_MEM', -} -SOURCE_REG = 0 -SOURCE_SCRATCH_MEM = 1 -source_type = ctypes.c_uint32 # enum - -# values for enumeration 'compare_mode' -compare_mode__enumvalues = { - 1: 'PRED_TEST', - 2: 'REG_COMPARE', - 3: 'RENDER_MODE', - 4: 'REG_COMPARE_IMM', - 5: 'THREAD_MODE', -} -PRED_TEST = 1 -REG_COMPARE = 2 -RENDER_MODE = 3 -REG_COMPARE_IMM = 4 -THREAD_MODE = 5 -compare_mode = ctypes.c_uint32 # enum - -# values for enumeration 'ctxswitch_ib' -ctxswitch_ib__enumvalues = { - 0: 'RESTORE_IB', - 1: 'YIELD_RESTORE_IB', - 2: 'SAVE_IB', - 3: 'RB_SAVE_IB', -} -RESTORE_IB = 0 -YIELD_RESTORE_IB = 1 -SAVE_IB = 2 -RB_SAVE_IB = 3 -ctxswitch_ib = ctypes.c_uint32 # enum - -# values for enumeration 'reg_tracker' -reg_tracker__enumvalues = { - 1: 'TRACK_CNTL_REG', - 2: 'TRACK_RENDER_CNTL', - 4: 'UNK_EVENT_WRITE', - 8: 'TRACK_LRZ', -} -TRACK_CNTL_REG = 1 -TRACK_RENDER_CNTL = 2 -UNK_EVENT_WRITE = 4 -TRACK_LRZ = 8 -reg_tracker = ctypes.c_uint32 # enum - -# values for enumeration 'ts_wait_value_src' -ts_wait_value_src__enumvalues = { - 0: 'TS_WAIT_GE_32B', - 1: 'TS_WAIT_GE_64B', - 2: 'TS_WAIT_GE_TIMESTAMP_SUM', -} -TS_WAIT_GE_32B = 0 -TS_WAIT_GE_64B = 1 -TS_WAIT_GE_TIMESTAMP_SUM = 2 -ts_wait_value_src = ctypes.c_uint32 # enum - -# values for enumeration 'ts_wait_type' -ts_wait_type__enumvalues = { - 0: 'TS_WAIT_RAM', - 1: 'TS_WAIT_ONCHIP', -} -TS_WAIT_RAM = 0 -TS_WAIT_ONCHIP = 1 -ts_wait_type = ctypes.c_uint32 # enum - -# values for enumeration 'pipe_count_op' -pipe_count_op__enumvalues = { - 1: 'PIPE_CLEAR_BV_BR', - 2: 'PIPE_SET_BR_OFFSET', - 3: 'PIPE_BR_WAIT_FOR_BV', - 4: 'PIPE_BV_WAIT_FOR_BR', -} -PIPE_CLEAR_BV_BR = 1 -PIPE_SET_BR_OFFSET = 2 -PIPE_BR_WAIT_FOR_BV = 3 -PIPE_BV_WAIT_FOR_BR = 4 -pipe_count_op = ctypes.c_uint32 # enum - -# values for enumeration 'timestamp_op' -timestamp_op__enumvalues = { - 0: 'MODIFY_TIMESTAMP_CLEAR', - 1: 'MODIFY_TIMESTAMP_ADD_GLOBAL', - 2: 'MODIFY_TIMESTAMP_ADD_LOCAL', -} -MODIFY_TIMESTAMP_CLEAR = 0 -MODIFY_TIMESTAMP_ADD_GLOBAL = 1 -MODIFY_TIMESTAMP_ADD_LOCAL = 2 -timestamp_op = ctypes.c_uint32 # enum - -# values for enumeration 'cp_thread' -cp_thread__enumvalues = { - 1: 'CP_SET_THREAD_BR', - 2: 'CP_SET_THREAD_BV', - 3: 'CP_SET_THREAD_BOTH', -} -CP_SET_THREAD_BR = 1 -CP_SET_THREAD_BV = 2 -CP_SET_THREAD_BOTH = 3 -cp_thread = ctypes.c_uint32 # enum - -# values for enumeration 'chip' -chip__enumvalues = { - 2: 'A2XX', - 3: 'A3XX', - 4: 'A4XX', - 5: 'A5XX', - 6: 'A6XX', - 7: 'A7XX', -} -A2XX = 2 -A3XX = 3 -A4XX = 4 -A5XX = 5 -A6XX = 6 -A7XX = 7 -chip = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_pa_su_sc_draw' -adreno_pa_su_sc_draw__enumvalues = { - 0: 'PC_DRAW_POINTS', - 1: 'PC_DRAW_LINES', - 2: 'PC_DRAW_TRIANGLES', -} -PC_DRAW_POINTS = 0 -PC_DRAW_LINES = 1 -PC_DRAW_TRIANGLES = 2 -adreno_pa_su_sc_draw = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_compare_func' -adreno_compare_func__enumvalues = { - 0: 'FUNC_NEVER', - 1: 'FUNC_LESS', - 2: 'FUNC_EQUAL', - 3: 'FUNC_LEQUAL', - 4: 'FUNC_GREATER', - 5: 'FUNC_NOTEQUAL', - 6: 'FUNC_GEQUAL', - 7: 'FUNC_ALWAYS', -} -FUNC_NEVER = 0 -FUNC_LESS = 1 -FUNC_EQUAL = 2 -FUNC_LEQUAL = 3 -FUNC_GREATER = 4 -FUNC_NOTEQUAL = 5 -FUNC_GEQUAL = 6 -FUNC_ALWAYS = 7 -adreno_compare_func = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_stencil_op' -adreno_stencil_op__enumvalues = { - 0: 'STENCIL_KEEP', - 1: 'STENCIL_ZERO', - 2: 'STENCIL_REPLACE', - 3: 'STENCIL_INCR_CLAMP', - 4: 'STENCIL_DECR_CLAMP', - 5: 'STENCIL_INVERT', - 6: 'STENCIL_INCR_WRAP', - 7: 'STENCIL_DECR_WRAP', -} -STENCIL_KEEP = 0 -STENCIL_ZERO = 1 -STENCIL_REPLACE = 2 -STENCIL_INCR_CLAMP = 3 -STENCIL_DECR_CLAMP = 4 -STENCIL_INVERT = 5 -STENCIL_INCR_WRAP = 6 -STENCIL_DECR_WRAP = 7 -adreno_stencil_op = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_blend_factor' -adreno_rb_blend_factor__enumvalues = { - 0: 'FACTOR_ZERO', - 1: 'FACTOR_ONE', - 4: 'FACTOR_SRC_COLOR', - 5: 'FACTOR_ONE_MINUS_SRC_COLOR', - 6: 'FACTOR_SRC_ALPHA', - 7: 'FACTOR_ONE_MINUS_SRC_ALPHA', - 8: 'FACTOR_DST_COLOR', - 9: 'FACTOR_ONE_MINUS_DST_COLOR', - 10: 'FACTOR_DST_ALPHA', - 11: 'FACTOR_ONE_MINUS_DST_ALPHA', - 12: 'FACTOR_CONSTANT_COLOR', - 13: 'FACTOR_ONE_MINUS_CONSTANT_COLOR', - 14: 'FACTOR_CONSTANT_ALPHA', - 15: 'FACTOR_ONE_MINUS_CONSTANT_ALPHA', - 16: 'FACTOR_SRC_ALPHA_SATURATE', - 20: 'FACTOR_SRC1_COLOR', - 21: 'FACTOR_ONE_MINUS_SRC1_COLOR', - 22: 'FACTOR_SRC1_ALPHA', - 23: 'FACTOR_ONE_MINUS_SRC1_ALPHA', -} -FACTOR_ZERO = 0 -FACTOR_ONE = 1 -FACTOR_SRC_COLOR = 4 -FACTOR_ONE_MINUS_SRC_COLOR = 5 -FACTOR_SRC_ALPHA = 6 -FACTOR_ONE_MINUS_SRC_ALPHA = 7 -FACTOR_DST_COLOR = 8 -FACTOR_ONE_MINUS_DST_COLOR = 9 -FACTOR_DST_ALPHA = 10 -FACTOR_ONE_MINUS_DST_ALPHA = 11 -FACTOR_CONSTANT_COLOR = 12 -FACTOR_ONE_MINUS_CONSTANT_COLOR = 13 -FACTOR_CONSTANT_ALPHA = 14 -FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15 -FACTOR_SRC_ALPHA_SATURATE = 16 -FACTOR_SRC1_COLOR = 20 -FACTOR_ONE_MINUS_SRC1_COLOR = 21 -FACTOR_SRC1_ALPHA = 22 -FACTOR_ONE_MINUS_SRC1_ALPHA = 23 -adreno_rb_blend_factor = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_surface_endian' -adreno_rb_surface_endian__enumvalues = { - 0: 'ENDIAN_NONE', - 1: 'ENDIAN_8IN16', - 2: 'ENDIAN_8IN32', - 3: 'ENDIAN_16IN32', - 4: 'ENDIAN_8IN64', - 5: 'ENDIAN_8IN128', -} -ENDIAN_NONE = 0 -ENDIAN_8IN16 = 1 -ENDIAN_8IN32 = 2 -ENDIAN_16IN32 = 3 -ENDIAN_8IN64 = 4 -ENDIAN_8IN128 = 5 -adreno_rb_surface_endian = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_dither_mode' -adreno_rb_dither_mode__enumvalues = { - 0: 'DITHER_DISABLE', - 1: 'DITHER_ALWAYS', - 2: 'DITHER_IF_ALPHA_OFF', -} -DITHER_DISABLE = 0 -DITHER_ALWAYS = 1 -DITHER_IF_ALPHA_OFF = 2 -adreno_rb_dither_mode = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_depth_format' -adreno_rb_depth_format__enumvalues = { - 0: 'DEPTHX_16', - 1: 'DEPTHX_24_8', - 2: 'DEPTHX_32', -} -DEPTHX_16 = 0 -DEPTHX_24_8 = 1 -DEPTHX_32 = 2 -adreno_rb_depth_format = ctypes.c_uint32 # enum - -# values for enumeration 'adreno_rb_copy_control_mode' -adreno_rb_copy_control_mode__enumvalues = { - 1: 'RB_COPY_RESOLVE', - 2: 'RB_COPY_CLEAR', - 5: 'RB_COPY_DEPTH_STENCIL', -} -RB_COPY_RESOLVE = 1 -RB_COPY_CLEAR = 2 -RB_COPY_DEPTH_STENCIL = 5 -adreno_rb_copy_control_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_rop_code' -a3xx_rop_code__enumvalues = { - 0: 'ROP_CLEAR', - 1: 'ROP_NOR', - 2: 'ROP_AND_INVERTED', - 3: 'ROP_COPY_INVERTED', - 4: 'ROP_AND_REVERSE', - 5: 'ROP_INVERT', - 6: 'ROP_XOR', - 7: 'ROP_NAND', - 8: 'ROP_AND', - 9: 'ROP_EQUIV', - 10: 'ROP_NOOP', - 11: 'ROP_OR_INVERTED', - 12: 'ROP_COPY', - 13: 'ROP_OR_REVERSE', - 14: 'ROP_OR', - 15: 'ROP_SET', -} -ROP_CLEAR = 0 -ROP_NOR = 1 -ROP_AND_INVERTED = 2 -ROP_COPY_INVERTED = 3 -ROP_AND_REVERSE = 4 -ROP_INVERT = 5 -ROP_XOR = 6 -ROP_NAND = 7 -ROP_AND = 8 -ROP_EQUIV = 9 -ROP_NOOP = 10 -ROP_OR_INVERTED = 11 -ROP_COPY = 12 -ROP_OR_REVERSE = 13 -ROP_OR = 14 -ROP_SET = 15 -a3xx_rop_code = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_render_mode' -a3xx_render_mode__enumvalues = { - 0: 'RB_RENDERING_PASS', - 1: 'RB_TILING_PASS', - 2: 'RB_RESOLVE_PASS', - 3: 'RB_COMPUTE_PASS', -} -RB_RENDERING_PASS = 0 -RB_TILING_PASS = 1 -RB_RESOLVE_PASS = 2 -RB_COMPUTE_PASS = 3 -a3xx_render_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_msaa_samples' -a3xx_msaa_samples__enumvalues = { - 0: 'MSAA_ONE', - 1: 'MSAA_TWO', - 2: 'MSAA_FOUR', - 3: 'MSAA_EIGHT', -} -MSAA_ONE = 0 -MSAA_TWO = 1 -MSAA_FOUR = 2 -MSAA_EIGHT = 3 -a3xx_msaa_samples = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_threadmode' -a3xx_threadmode__enumvalues = { - 0: 'MULTI', - 1: 'SINGLE', -} -MULTI = 0 -SINGLE = 1 -a3xx_threadmode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_instrbuffermode' -a3xx_instrbuffermode__enumvalues = { - 0: 'CACHE', - 1: 'BUFFER', -} -CACHE = 0 -BUFFER = 1 -a3xx_instrbuffermode = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_threadsize' -a3xx_threadsize__enumvalues = { - 0: 'TWO_QUADS', - 1: 'FOUR_QUADS', -} -TWO_QUADS = 0 -FOUR_QUADS = 1 -a3xx_threadsize = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_color_swap' -a3xx_color_swap__enumvalues = { - 0: 'WZYX', - 1: 'WXYZ', - 2: 'ZYXW', - 3: 'XYZW', -} -WZYX = 0 -WXYZ = 1 -ZYXW = 2 -XYZW = 3 -a3xx_color_swap = ctypes.c_uint32 # enum - -# values for enumeration 'a3xx_rb_blend_opcode' -a3xx_rb_blend_opcode__enumvalues = { - 0: 'BLEND_DST_PLUS_SRC', - 1: 'BLEND_SRC_MINUS_DST', - 2: 'BLEND_DST_MINUS_SRC', - 3: 'BLEND_MIN_DST_SRC', - 4: 'BLEND_MAX_DST_SRC', -} -BLEND_DST_PLUS_SRC = 0 -BLEND_SRC_MINUS_DST = 1 -BLEND_DST_MINUS_SRC = 2 -BLEND_MIN_DST_SRC = 3 -BLEND_MAX_DST_SRC = 4 -a3xx_rb_blend_opcode = ctypes.c_uint32 # enum - -# values for enumeration 'a4xx_tess_spacing' -a4xx_tess_spacing__enumvalues = { - 0: 'EQUAL_SPACING', - 2: 'ODD_SPACING', - 3: 'EVEN_SPACING', -} -EQUAL_SPACING = 0 -ODD_SPACING = 2 -EVEN_SPACING = 3 -a4xx_tess_spacing = ctypes.c_uint32 # enum - -# values for enumeration 'a5xx_address_mode' -a5xx_address_mode__enumvalues = { - 0: 'ADDR_32B', - 1: 'ADDR_64B', -} -ADDR_32B = 0 -ADDR_64B = 1 -a5xx_address_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a5xx_line_mode' -a5xx_line_mode__enumvalues = { - 0: 'BRESENHAM', - 1: 'RECTANGULAR', -} -BRESENHAM = 0 -RECTANGULAR = 1 -a5xx_line_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_prefetch_cmd' -a6xx_tex_prefetch_cmd__enumvalues = { - 0: 'TEX_PREFETCH_UNK0', - 1: 'TEX_PREFETCH_SAM', - 2: 'TEX_PREFETCH_GATHER4R', - 3: 'TEX_PREFETCH_GATHER4G', - 4: 'TEX_PREFETCH_GATHER4B', - 5: 'TEX_PREFETCH_GATHER4A', - 6: 'TEX_PREFETCH_UNK6', - 7: 'TEX_PREFETCH_UNK7', -} -TEX_PREFETCH_UNK0 = 0 -TEX_PREFETCH_SAM = 1 -TEX_PREFETCH_GATHER4R = 2 -TEX_PREFETCH_GATHER4G = 3 -TEX_PREFETCH_GATHER4B = 4 -TEX_PREFETCH_GATHER4A = 5 -TEX_PREFETCH_UNK6 = 6 -TEX_PREFETCH_UNK7 = 7 -a6xx_tex_prefetch_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tile_mode' -a6xx_tile_mode__enumvalues = { - 0: 'TILE6_LINEAR', - 2: 'TILE6_2', - 3: 'TILE6_3', -} -TILE6_LINEAR = 0 -TILE6_2 = 2 -TILE6_3 = 3 -a6xx_tile_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_format' -a6xx_format__enumvalues = { - 2: 'FMT6_A8_UNORM', - 3: 'FMT6_8_UNORM', - 4: 'FMT6_8_SNORM', - 5: 'FMT6_8_UINT', - 6: 'FMT6_8_SINT', - 8: 'FMT6_4_4_4_4_UNORM', - 10: 'FMT6_5_5_5_1_UNORM', - 12: 'FMT6_1_5_5_5_UNORM', - 14: 'FMT6_5_6_5_UNORM', - 15: 'FMT6_8_8_UNORM', - 16: 'FMT6_8_8_SNORM', - 17: 'FMT6_8_8_UINT', - 18: 'FMT6_8_8_SINT', - 19: 'FMT6_L8_A8_UNORM', - 21: 'FMT6_16_UNORM', - 22: 'FMT6_16_SNORM', - 23: 'FMT6_16_FLOAT', - 24: 'FMT6_16_UINT', - 25: 'FMT6_16_SINT', - 33: 'FMT6_8_8_8_UNORM', - 34: 'FMT6_8_8_8_SNORM', - 35: 'FMT6_8_8_8_UINT', - 36: 'FMT6_8_8_8_SINT', - 48: 'FMT6_8_8_8_8_UNORM', - 49: 'FMT6_8_8_8_X8_UNORM', - 50: 'FMT6_8_8_8_8_SNORM', - 51: 'FMT6_8_8_8_8_UINT', - 52: 'FMT6_8_8_8_8_SINT', - 53: 'FMT6_9_9_9_E5_FLOAT', - 54: 'FMT6_10_10_10_2_UNORM', - 55: 'FMT6_10_10_10_2_UNORM_DEST', - 57: 'FMT6_10_10_10_2_SNORM', - 58: 'FMT6_10_10_10_2_UINT', - 59: 'FMT6_10_10_10_2_SINT', - 66: 'FMT6_11_11_10_FLOAT', - 67: 'FMT6_16_16_UNORM', - 68: 'FMT6_16_16_SNORM', - 69: 'FMT6_16_16_FLOAT', - 70: 'FMT6_16_16_UINT', - 71: 'FMT6_16_16_SINT', - 72: 'FMT6_32_UNORM', - 73: 'FMT6_32_SNORM', - 74: 'FMT6_32_FLOAT', - 75: 'FMT6_32_UINT', - 76: 'FMT6_32_SINT', - 77: 'FMT6_32_FIXED', - 88: 'FMT6_16_16_16_UNORM', - 89: 'FMT6_16_16_16_SNORM', - 90: 'FMT6_16_16_16_FLOAT', - 91: 'FMT6_16_16_16_UINT', - 92: 'FMT6_16_16_16_SINT', - 96: 'FMT6_16_16_16_16_UNORM', - 97: 'FMT6_16_16_16_16_SNORM', - 98: 'FMT6_16_16_16_16_FLOAT', - 99: 'FMT6_16_16_16_16_UINT', - 100: 'FMT6_16_16_16_16_SINT', - 101: 'FMT6_32_32_UNORM', - 102: 'FMT6_32_32_SNORM', - 103: 'FMT6_32_32_FLOAT', - 104: 'FMT6_32_32_UINT', - 105: 'FMT6_32_32_SINT', - 106: 'FMT6_32_32_FIXED', - 112: 'FMT6_32_32_32_UNORM', - 113: 'FMT6_32_32_32_SNORM', - 114: 'FMT6_32_32_32_UINT', - 115: 'FMT6_32_32_32_SINT', - 116: 'FMT6_32_32_32_FLOAT', - 117: 'FMT6_32_32_32_FIXED', - 128: 'FMT6_32_32_32_32_UNORM', - 129: 'FMT6_32_32_32_32_SNORM', - 130: 'FMT6_32_32_32_32_FLOAT', - 131: 'FMT6_32_32_32_32_UINT', - 132: 'FMT6_32_32_32_32_SINT', - 133: 'FMT6_32_32_32_32_FIXED', - 140: 'FMT6_G8R8B8R8_422_UNORM', - 141: 'FMT6_R8G8R8B8_422_UNORM', - 142: 'FMT6_R8_G8B8_2PLANE_420_UNORM', - 143: 'FMT6_NV21', - 144: 'FMT6_R8_G8_B8_3PLANE_420_UNORM', - 145: 'FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', - 148: 'FMT6_NV12_Y', - 149: 'FMT6_NV12_UV', - 150: 'FMT6_NV12_VU', - 151: 'FMT6_NV12_4R', - 152: 'FMT6_NV12_4R_Y', - 153: 'FMT6_NV12_4R_UV', - 154: 'FMT6_P010', - 155: 'FMT6_P010_Y', - 156: 'FMT6_P010_UV', - 157: 'FMT6_TP10', - 158: 'FMT6_TP10_Y', - 159: 'FMT6_TP10_UV', - 160: 'FMT6_Z24_UNORM_S8_UINT', - 171: 'FMT6_ETC2_RG11_UNORM', - 172: 'FMT6_ETC2_RG11_SNORM', - 173: 'FMT6_ETC2_R11_UNORM', - 174: 'FMT6_ETC2_R11_SNORM', - 175: 'FMT6_ETC1', - 176: 'FMT6_ETC2_RGB8', - 177: 'FMT6_ETC2_RGBA8', - 178: 'FMT6_ETC2_RGB8A1', - 179: 'FMT6_DXT1', - 180: 'FMT6_DXT3', - 181: 'FMT6_DXT5', - 183: 'FMT6_RGTC1_UNORM', - 184: 'FMT6_RGTC1_SNORM', - 187: 'FMT6_RGTC2_UNORM', - 188: 'FMT6_RGTC2_SNORM', - 190: 'FMT6_BPTC_UFLOAT', - 191: 'FMT6_BPTC_FLOAT', - 192: 'FMT6_BPTC', - 193: 'FMT6_ASTC_4x4', - 194: 'FMT6_ASTC_5x4', - 195: 'FMT6_ASTC_5x5', - 196: 'FMT6_ASTC_6x5', - 197: 'FMT6_ASTC_6x6', - 198: 'FMT6_ASTC_8x5', - 199: 'FMT6_ASTC_8x6', - 200: 'FMT6_ASTC_8x8', - 201: 'FMT6_ASTC_10x5', - 202: 'FMT6_ASTC_10x6', - 203: 'FMT6_ASTC_10x8', - 204: 'FMT6_ASTC_10x10', - 205: 'FMT6_ASTC_12x10', - 206: 'FMT6_ASTC_12x12', - 234: 'FMT6_Z24_UINT_S8_UINT', - 255: 'FMT6_NONE', -} -FMT6_A8_UNORM = 2 -FMT6_8_UNORM = 3 -FMT6_8_SNORM = 4 -FMT6_8_UINT = 5 -FMT6_8_SINT = 6 -FMT6_4_4_4_4_UNORM = 8 -FMT6_5_5_5_1_UNORM = 10 -FMT6_1_5_5_5_UNORM = 12 -FMT6_5_6_5_UNORM = 14 -FMT6_8_8_UNORM = 15 -FMT6_8_8_SNORM = 16 -FMT6_8_8_UINT = 17 -FMT6_8_8_SINT = 18 -FMT6_L8_A8_UNORM = 19 -FMT6_16_UNORM = 21 -FMT6_16_SNORM = 22 -FMT6_16_FLOAT = 23 -FMT6_16_UINT = 24 -FMT6_16_SINT = 25 -FMT6_8_8_8_UNORM = 33 -FMT6_8_8_8_SNORM = 34 -FMT6_8_8_8_UINT = 35 -FMT6_8_8_8_SINT = 36 -FMT6_8_8_8_8_UNORM = 48 -FMT6_8_8_8_X8_UNORM = 49 -FMT6_8_8_8_8_SNORM = 50 -FMT6_8_8_8_8_UINT = 51 -FMT6_8_8_8_8_SINT = 52 -FMT6_9_9_9_E5_FLOAT = 53 -FMT6_10_10_10_2_UNORM = 54 -FMT6_10_10_10_2_UNORM_DEST = 55 -FMT6_10_10_10_2_SNORM = 57 -FMT6_10_10_10_2_UINT = 58 -FMT6_10_10_10_2_SINT = 59 -FMT6_11_11_10_FLOAT = 66 -FMT6_16_16_UNORM = 67 -FMT6_16_16_SNORM = 68 -FMT6_16_16_FLOAT = 69 -FMT6_16_16_UINT = 70 -FMT6_16_16_SINT = 71 -FMT6_32_UNORM = 72 -FMT6_32_SNORM = 73 -FMT6_32_FLOAT = 74 -FMT6_32_UINT = 75 -FMT6_32_SINT = 76 -FMT6_32_FIXED = 77 -FMT6_16_16_16_UNORM = 88 -FMT6_16_16_16_SNORM = 89 -FMT6_16_16_16_FLOAT = 90 -FMT6_16_16_16_UINT = 91 -FMT6_16_16_16_SINT = 92 -FMT6_16_16_16_16_UNORM = 96 -FMT6_16_16_16_16_SNORM = 97 -FMT6_16_16_16_16_FLOAT = 98 -FMT6_16_16_16_16_UINT = 99 -FMT6_16_16_16_16_SINT = 100 -FMT6_32_32_UNORM = 101 -FMT6_32_32_SNORM = 102 -FMT6_32_32_FLOAT = 103 -FMT6_32_32_UINT = 104 -FMT6_32_32_SINT = 105 -FMT6_32_32_FIXED = 106 -FMT6_32_32_32_UNORM = 112 -FMT6_32_32_32_SNORM = 113 -FMT6_32_32_32_UINT = 114 -FMT6_32_32_32_SINT = 115 -FMT6_32_32_32_FLOAT = 116 -FMT6_32_32_32_FIXED = 117 -FMT6_32_32_32_32_UNORM = 128 -FMT6_32_32_32_32_SNORM = 129 -FMT6_32_32_32_32_FLOAT = 130 -FMT6_32_32_32_32_UINT = 131 -FMT6_32_32_32_32_SINT = 132 -FMT6_32_32_32_32_FIXED = 133 -FMT6_G8R8B8R8_422_UNORM = 140 -FMT6_R8G8R8B8_422_UNORM = 141 -FMT6_R8_G8B8_2PLANE_420_UNORM = 142 -FMT6_NV21 = 143 -FMT6_R8_G8_B8_3PLANE_420_UNORM = 144 -FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145 -FMT6_NV12_Y = 148 -FMT6_NV12_UV = 149 -FMT6_NV12_VU = 150 -FMT6_NV12_4R = 151 -FMT6_NV12_4R_Y = 152 -FMT6_NV12_4R_UV = 153 -FMT6_P010 = 154 -FMT6_P010_Y = 155 -FMT6_P010_UV = 156 -FMT6_TP10 = 157 -FMT6_TP10_Y = 158 -FMT6_TP10_UV = 159 -FMT6_Z24_UNORM_S8_UINT = 160 -FMT6_ETC2_RG11_UNORM = 171 -FMT6_ETC2_RG11_SNORM = 172 -FMT6_ETC2_R11_UNORM = 173 -FMT6_ETC2_R11_SNORM = 174 -FMT6_ETC1 = 175 -FMT6_ETC2_RGB8 = 176 -FMT6_ETC2_RGBA8 = 177 -FMT6_ETC2_RGB8A1 = 178 -FMT6_DXT1 = 179 -FMT6_DXT3 = 180 -FMT6_DXT5 = 181 -FMT6_RGTC1_UNORM = 183 -FMT6_RGTC1_SNORM = 184 -FMT6_RGTC2_UNORM = 187 -FMT6_RGTC2_SNORM = 188 -FMT6_BPTC_UFLOAT = 190 -FMT6_BPTC_FLOAT = 191 -FMT6_BPTC = 192 -FMT6_ASTC_4x4 = 193 -FMT6_ASTC_5x4 = 194 -FMT6_ASTC_5x5 = 195 -FMT6_ASTC_6x5 = 196 -FMT6_ASTC_6x6 = 197 -FMT6_ASTC_8x5 = 198 -FMT6_ASTC_8x6 = 199 -FMT6_ASTC_8x8 = 200 -FMT6_ASTC_10x5 = 201 -FMT6_ASTC_10x6 = 202 -FMT6_ASTC_10x8 = 203 -FMT6_ASTC_10x10 = 204 -FMT6_ASTC_12x10 = 205 -FMT6_ASTC_12x12 = 206 -FMT6_Z24_UINT_S8_UINT = 234 -FMT6_NONE = 255 -a6xx_format = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_polygon_mode' -a6xx_polygon_mode__enumvalues = { - 1: 'POLYMODE6_POINTS', - 2: 'POLYMODE6_LINES', - 3: 'POLYMODE6_TRIANGLES', -} -POLYMODE6_POINTS = 1 -POLYMODE6_LINES = 2 -POLYMODE6_TRIANGLES = 3 -a6xx_polygon_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_depth_format' -a6xx_depth_format__enumvalues = { - 0: 'DEPTH6_NONE', - 1: 'DEPTH6_16', - 2: 'DEPTH6_24_8', - 4: 'DEPTH6_32', -} -DEPTH6_NONE = 0 -DEPTH6_16 = 1 -DEPTH6_24_8 = 2 -DEPTH6_32 = 4 -a6xx_depth_format = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_shader_id' -a6xx_shader_id__enumvalues = { - 9: 'A6XX_TP0_TMO_DATA', - 10: 'A6XX_TP0_SMO_DATA', - 11: 'A6XX_TP0_MIPMAP_BASE_DATA', - 25: 'A6XX_TP1_TMO_DATA', - 26: 'A6XX_TP1_SMO_DATA', - 27: 'A6XX_TP1_MIPMAP_BASE_DATA', - 41: 'A6XX_SP_INST_DATA', - 42: 'A6XX_SP_LB_0_DATA', - 43: 'A6XX_SP_LB_1_DATA', - 44: 'A6XX_SP_LB_2_DATA', - 45: 'A6XX_SP_LB_3_DATA', - 46: 'A6XX_SP_LB_4_DATA', - 47: 'A6XX_SP_LB_5_DATA', - 48: 'A6XX_SP_CB_BINDLESS_DATA', - 49: 'A6XX_SP_CB_LEGACY_DATA', - 50: 'A6XX_SP_UAV_DATA', - 51: 'A6XX_SP_INST_TAG', - 52: 'A6XX_SP_CB_BINDLESS_TAG', - 53: 'A6XX_SP_TMO_UMO_TAG', - 54: 'A6XX_SP_SMO_TAG', - 55: 'A6XX_SP_STATE_DATA', - 73: 'A6XX_HLSQ_CHUNK_CVS_RAM', - 74: 'A6XX_HLSQ_CHUNK_CPS_RAM', - 75: 'A6XX_HLSQ_CHUNK_CVS_RAM_TAG', - 76: 'A6XX_HLSQ_CHUNK_CPS_RAM_TAG', - 77: 'A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 78: 'A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', - 80: 'A6XX_HLSQ_CVS_MISC_RAM', - 81: 'A6XX_HLSQ_CPS_MISC_RAM', - 82: 'A6XX_HLSQ_INST_RAM', - 83: 'A6XX_HLSQ_GFX_CVS_CONST_RAM', - 84: 'A6XX_HLSQ_GFX_CPS_CONST_RAM', - 85: 'A6XX_HLSQ_CVS_MISC_RAM_TAG', - 86: 'A6XX_HLSQ_CPS_MISC_RAM_TAG', - 87: 'A6XX_HLSQ_INST_RAM_TAG', - 88: 'A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 89: 'A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 90: 'A6XX_HLSQ_PWR_REST_RAM', - 91: 'A6XX_HLSQ_PWR_REST_TAG', - 96: 'A6XX_HLSQ_DATAPATH_META', - 97: 'A6XX_HLSQ_FRONTEND_META', - 98: 'A6XX_HLSQ_INDIRECT_META', - 99: 'A6XX_HLSQ_BACKEND_META', - 112: 'A6XX_SP_LB_6_DATA', - 113: 'A6XX_SP_LB_7_DATA', - 115: 'A6XX_HLSQ_INST_RAM_1', -} -A6XX_TP0_TMO_DATA = 9 -A6XX_TP0_SMO_DATA = 10 -A6XX_TP0_MIPMAP_BASE_DATA = 11 -A6XX_TP1_TMO_DATA = 25 -A6XX_TP1_SMO_DATA = 26 -A6XX_TP1_MIPMAP_BASE_DATA = 27 -A6XX_SP_INST_DATA = 41 -A6XX_SP_LB_0_DATA = 42 -A6XX_SP_LB_1_DATA = 43 -A6XX_SP_LB_2_DATA = 44 -A6XX_SP_LB_3_DATA = 45 -A6XX_SP_LB_4_DATA = 46 -A6XX_SP_LB_5_DATA = 47 -A6XX_SP_CB_BINDLESS_DATA = 48 -A6XX_SP_CB_LEGACY_DATA = 49 -A6XX_SP_UAV_DATA = 50 -A6XX_SP_INST_TAG = 51 -A6XX_SP_CB_BINDLESS_TAG = 52 -A6XX_SP_TMO_UMO_TAG = 53 -A6XX_SP_SMO_TAG = 54 -A6XX_SP_STATE_DATA = 55 -A6XX_HLSQ_CHUNK_CVS_RAM = 73 -A6XX_HLSQ_CHUNK_CPS_RAM = 74 -A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75 -A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76 -A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77 -A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78 -A6XX_HLSQ_CVS_MISC_RAM = 80 -A6XX_HLSQ_CPS_MISC_RAM = 81 -A6XX_HLSQ_INST_RAM = 82 -A6XX_HLSQ_GFX_CVS_CONST_RAM = 83 -A6XX_HLSQ_GFX_CPS_CONST_RAM = 84 -A6XX_HLSQ_CVS_MISC_RAM_TAG = 85 -A6XX_HLSQ_CPS_MISC_RAM_TAG = 86 -A6XX_HLSQ_INST_RAM_TAG = 87 -A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88 -A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89 -A6XX_HLSQ_PWR_REST_RAM = 90 -A6XX_HLSQ_PWR_REST_TAG = 91 -A6XX_HLSQ_DATAPATH_META = 96 -A6XX_HLSQ_FRONTEND_META = 97 -A6XX_HLSQ_INDIRECT_META = 98 -A6XX_HLSQ_BACKEND_META = 99 -A6XX_SP_LB_6_DATA = 112 -A6XX_SP_LB_7_DATA = 113 -A6XX_HLSQ_INST_RAM_1 = 115 -a6xx_shader_id = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_statetype_id' -a7xx_statetype_id__enumvalues = { - 0: 'A7XX_TP0_NCTX_REG', - 1: 'A7XX_TP0_CTX0_3D_CVS_REG', - 2: 'A7XX_TP0_CTX0_3D_CPS_REG', - 3: 'A7XX_TP0_CTX1_3D_CVS_REG', - 4: 'A7XX_TP0_CTX1_3D_CPS_REG', - 5: 'A7XX_TP0_CTX2_3D_CPS_REG', - 6: 'A7XX_TP0_CTX3_3D_CPS_REG', - 9: 'A7XX_TP0_TMO_DATA', - 10: 'A7XX_TP0_SMO_DATA', - 11: 'A7XX_TP0_MIPMAP_BASE_DATA', - 32: 'A7XX_SP_NCTX_REG', - 33: 'A7XX_SP_CTX0_3D_CVS_REG', - 34: 'A7XX_SP_CTX0_3D_CPS_REG', - 35: 'A7XX_SP_CTX1_3D_CVS_REG', - 36: 'A7XX_SP_CTX1_3D_CPS_REG', - 37: 'A7XX_SP_CTX2_3D_CPS_REG', - 38: 'A7XX_SP_CTX3_3D_CPS_REG', - 39: 'A7XX_SP_INST_DATA', - 40: 'A7XX_SP_INST_DATA_1', - 41: 'A7XX_SP_LB_0_DATA', - 42: 'A7XX_SP_LB_1_DATA', - 43: 'A7XX_SP_LB_2_DATA', - 44: 'A7XX_SP_LB_3_DATA', - 45: 'A7XX_SP_LB_4_DATA', - 46: 'A7XX_SP_LB_5_DATA', - 47: 'A7XX_SP_LB_6_DATA', - 48: 'A7XX_SP_LB_7_DATA', - 49: 'A7XX_SP_CB_RAM', - 50: 'A7XX_SP_LB_13_DATA', - 51: 'A7XX_SP_LB_14_DATA', - 52: 'A7XX_SP_INST_TAG', - 53: 'A7XX_SP_INST_DATA_2', - 54: 'A7XX_SP_TMO_TAG', - 55: 'A7XX_SP_SMO_TAG', - 56: 'A7XX_SP_STATE_DATA', - 57: 'A7XX_SP_HWAVE_RAM', - 58: 'A7XX_SP_L0_INST_BUF', - 59: 'A7XX_SP_LB_8_DATA', - 60: 'A7XX_SP_LB_9_DATA', - 61: 'A7XX_SP_LB_10_DATA', - 62: 'A7XX_SP_LB_11_DATA', - 63: 'A7XX_SP_LB_12_DATA', - 64: 'A7XX_HLSQ_DATAPATH_DSTR_META', - 67: 'A7XX_HLSQ_L2STC_TAG_RAM', - 68: 'A7XX_HLSQ_L2STC_INFO_CMD', - 69: 'A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', - 70: 'A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', - 71: 'A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM', - 72: 'A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM', - 73: 'A7XX_HLSQ_CHUNK_CVS_RAM', - 74: 'A7XX_HLSQ_CHUNK_CPS_RAM', - 75: 'A7XX_HLSQ_CHUNK_CVS_RAM_TAG', - 76: 'A7XX_HLSQ_CHUNK_CPS_RAM_TAG', - 77: 'A7XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 78: 'A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', - 79: 'A7XX_HLSQ_CVS_MISC_RAM', - 80: 'A7XX_HLSQ_CPS_MISC_RAM', - 81: 'A7XX_HLSQ_CPS_MISC_RAM_1', - 82: 'A7XX_HLSQ_INST_RAM', - 83: 'A7XX_HLSQ_GFX_CVS_CONST_RAM', - 84: 'A7XX_HLSQ_GFX_CPS_CONST_RAM', - 85: 'A7XX_HLSQ_CVS_MISC_RAM_TAG', - 86: 'A7XX_HLSQ_CPS_MISC_RAM_TAG', - 87: 'A7XX_HLSQ_INST_RAM_TAG', - 88: 'A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 89: 'A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 90: 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM', - 91: 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG', - 92: 'A7XX_HLSQ_INST_RAM_1', - 93: 'A7XX_HLSQ_STPROC_META', - 94: 'A7XX_HLSQ_BV_BE_META', - 95: 'A7XX_HLSQ_INST_RAM_2', - 96: 'A7XX_HLSQ_DATAPATH_META', - 97: 'A7XX_HLSQ_FRONTEND_META', - 98: 'A7XX_HLSQ_INDIRECT_META', - 99: 'A7XX_HLSQ_BACKEND_META', -} -A7XX_TP0_NCTX_REG = 0 -A7XX_TP0_CTX0_3D_CVS_REG = 1 -A7XX_TP0_CTX0_3D_CPS_REG = 2 -A7XX_TP0_CTX1_3D_CVS_REG = 3 -A7XX_TP0_CTX1_3D_CPS_REG = 4 -A7XX_TP0_CTX2_3D_CPS_REG = 5 -A7XX_TP0_CTX3_3D_CPS_REG = 6 -A7XX_TP0_TMO_DATA = 9 -A7XX_TP0_SMO_DATA = 10 -A7XX_TP0_MIPMAP_BASE_DATA = 11 -A7XX_SP_NCTX_REG = 32 -A7XX_SP_CTX0_3D_CVS_REG = 33 -A7XX_SP_CTX0_3D_CPS_REG = 34 -A7XX_SP_CTX1_3D_CVS_REG = 35 -A7XX_SP_CTX1_3D_CPS_REG = 36 -A7XX_SP_CTX2_3D_CPS_REG = 37 -A7XX_SP_CTX3_3D_CPS_REG = 38 -A7XX_SP_INST_DATA = 39 -A7XX_SP_INST_DATA_1 = 40 -A7XX_SP_LB_0_DATA = 41 -A7XX_SP_LB_1_DATA = 42 -A7XX_SP_LB_2_DATA = 43 -A7XX_SP_LB_3_DATA = 44 -A7XX_SP_LB_4_DATA = 45 -A7XX_SP_LB_5_DATA = 46 -A7XX_SP_LB_6_DATA = 47 -A7XX_SP_LB_7_DATA = 48 -A7XX_SP_CB_RAM = 49 -A7XX_SP_LB_13_DATA = 50 -A7XX_SP_LB_14_DATA = 51 -A7XX_SP_INST_TAG = 52 -A7XX_SP_INST_DATA_2 = 53 -A7XX_SP_TMO_TAG = 54 -A7XX_SP_SMO_TAG = 55 -A7XX_SP_STATE_DATA = 56 -A7XX_SP_HWAVE_RAM = 57 -A7XX_SP_L0_INST_BUF = 58 -A7XX_SP_LB_8_DATA = 59 -A7XX_SP_LB_9_DATA = 60 -A7XX_SP_LB_10_DATA = 61 -A7XX_SP_LB_11_DATA = 62 -A7XX_SP_LB_12_DATA = 63 -A7XX_HLSQ_DATAPATH_DSTR_META = 64 -A7XX_HLSQ_L2STC_TAG_RAM = 67 -A7XX_HLSQ_L2STC_INFO_CMD = 68 -A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69 -A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70 -A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71 -A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72 -A7XX_HLSQ_CHUNK_CVS_RAM = 73 -A7XX_HLSQ_CHUNK_CPS_RAM = 74 -A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75 -A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76 -A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77 -A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78 -A7XX_HLSQ_CVS_MISC_RAM = 79 -A7XX_HLSQ_CPS_MISC_RAM = 80 -A7XX_HLSQ_CPS_MISC_RAM_1 = 81 -A7XX_HLSQ_INST_RAM = 82 -A7XX_HLSQ_GFX_CVS_CONST_RAM = 83 -A7XX_HLSQ_GFX_CPS_CONST_RAM = 84 -A7XX_HLSQ_CVS_MISC_RAM_TAG = 85 -A7XX_HLSQ_CPS_MISC_RAM_TAG = 86 -A7XX_HLSQ_INST_RAM_TAG = 87 -A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88 -A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89 -A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90 -A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91 -A7XX_HLSQ_INST_RAM_1 = 92 -A7XX_HLSQ_STPROC_META = 93 -A7XX_HLSQ_BV_BE_META = 94 -A7XX_HLSQ_INST_RAM_2 = 95 -A7XX_HLSQ_DATAPATH_META = 96 -A7XX_HLSQ_FRONTEND_META = 97 -A7XX_HLSQ_INDIRECT_META = 98 -A7XX_HLSQ_BACKEND_META = 99 -a7xx_statetype_id = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_debugbus_id' -a6xx_debugbus_id__enumvalues = { - 1: 'A6XX_DBGBUS_CP', - 2: 'A6XX_DBGBUS_RBBM', - 3: 'A6XX_DBGBUS_VBIF', - 4: 'A6XX_DBGBUS_HLSQ', - 5: 'A6XX_DBGBUS_UCHE', - 6: 'A6XX_DBGBUS_DPM', - 7: 'A6XX_DBGBUS_TESS', - 8: 'A6XX_DBGBUS_PC', - 9: 'A6XX_DBGBUS_VFDP', - 10: 'A6XX_DBGBUS_VPC', - 11: 'A6XX_DBGBUS_TSE', - 12: 'A6XX_DBGBUS_RAS', - 13: 'A6XX_DBGBUS_VSC', - 14: 'A6XX_DBGBUS_COM', - 16: 'A6XX_DBGBUS_LRZ', - 17: 'A6XX_DBGBUS_A2D', - 18: 'A6XX_DBGBUS_CCUFCHE', - 19: 'A6XX_DBGBUS_GMU_CX', - 20: 'A6XX_DBGBUS_RBP', - 21: 'A6XX_DBGBUS_DCS', - 22: 'A6XX_DBGBUS_DBGC', - 23: 'A6XX_DBGBUS_CX', - 24: 'A6XX_DBGBUS_GMU_GX', - 25: 'A6XX_DBGBUS_TPFCHE', - 26: 'A6XX_DBGBUS_GBIF_GX', - 29: 'A6XX_DBGBUS_GPC', - 30: 'A6XX_DBGBUS_LARC', - 31: 'A6XX_DBGBUS_HLSQ_SPTP', - 32: 'A6XX_DBGBUS_RB_0', - 33: 'A6XX_DBGBUS_RB_1', - 34: 'A6XX_DBGBUS_RB_2', - 36: 'A6XX_DBGBUS_UCHE_WRAPPER', - 40: 'A6XX_DBGBUS_CCU_0', - 41: 'A6XX_DBGBUS_CCU_1', - 42: 'A6XX_DBGBUS_CCU_2', - 56: 'A6XX_DBGBUS_VFD_0', - 57: 'A6XX_DBGBUS_VFD_1', - 58: 'A6XX_DBGBUS_VFD_2', - 59: 'A6XX_DBGBUS_VFD_3', - 60: 'A6XX_DBGBUS_VFD_4', - 61: 'A6XX_DBGBUS_VFD_5', - 64: 'A6XX_DBGBUS_SP_0', - 65: 'A6XX_DBGBUS_SP_1', - 66: 'A6XX_DBGBUS_SP_2', - 72: 'A6XX_DBGBUS_TPL1_0', - 73: 'A6XX_DBGBUS_TPL1_1', - 74: 'A6XX_DBGBUS_TPL1_2', - 75: 'A6XX_DBGBUS_TPL1_3', - 76: 'A6XX_DBGBUS_TPL1_4', - 77: 'A6XX_DBGBUS_TPL1_5', - 88: 'A6XX_DBGBUS_SPTP_0', - 89: 'A6XX_DBGBUS_SPTP_1', - 90: 'A6XX_DBGBUS_SPTP_2', - 91: 'A6XX_DBGBUS_SPTP_3', - 92: 'A6XX_DBGBUS_SPTP_4', - 93: 'A6XX_DBGBUS_SPTP_5', -} -A6XX_DBGBUS_CP = 1 -A6XX_DBGBUS_RBBM = 2 -A6XX_DBGBUS_VBIF = 3 -A6XX_DBGBUS_HLSQ = 4 -A6XX_DBGBUS_UCHE = 5 -A6XX_DBGBUS_DPM = 6 -A6XX_DBGBUS_TESS = 7 -A6XX_DBGBUS_PC = 8 -A6XX_DBGBUS_VFDP = 9 -A6XX_DBGBUS_VPC = 10 -A6XX_DBGBUS_TSE = 11 -A6XX_DBGBUS_RAS = 12 -A6XX_DBGBUS_VSC = 13 -A6XX_DBGBUS_COM = 14 -A6XX_DBGBUS_LRZ = 16 -A6XX_DBGBUS_A2D = 17 -A6XX_DBGBUS_CCUFCHE = 18 -A6XX_DBGBUS_GMU_CX = 19 -A6XX_DBGBUS_RBP = 20 -A6XX_DBGBUS_DCS = 21 -A6XX_DBGBUS_DBGC = 22 -A6XX_DBGBUS_CX = 23 -A6XX_DBGBUS_GMU_GX = 24 -A6XX_DBGBUS_TPFCHE = 25 -A6XX_DBGBUS_GBIF_GX = 26 -A6XX_DBGBUS_GPC = 29 -A6XX_DBGBUS_LARC = 30 -A6XX_DBGBUS_HLSQ_SPTP = 31 -A6XX_DBGBUS_RB_0 = 32 -A6XX_DBGBUS_RB_1 = 33 -A6XX_DBGBUS_RB_2 = 34 -A6XX_DBGBUS_UCHE_WRAPPER = 36 -A6XX_DBGBUS_CCU_0 = 40 -A6XX_DBGBUS_CCU_1 = 41 -A6XX_DBGBUS_CCU_2 = 42 -A6XX_DBGBUS_VFD_0 = 56 -A6XX_DBGBUS_VFD_1 = 57 -A6XX_DBGBUS_VFD_2 = 58 -A6XX_DBGBUS_VFD_3 = 59 -A6XX_DBGBUS_VFD_4 = 60 -A6XX_DBGBUS_VFD_5 = 61 -A6XX_DBGBUS_SP_0 = 64 -A6XX_DBGBUS_SP_1 = 65 -A6XX_DBGBUS_SP_2 = 66 -A6XX_DBGBUS_TPL1_0 = 72 -A6XX_DBGBUS_TPL1_1 = 73 -A6XX_DBGBUS_TPL1_2 = 74 -A6XX_DBGBUS_TPL1_3 = 75 -A6XX_DBGBUS_TPL1_4 = 76 -A6XX_DBGBUS_TPL1_5 = 77 -A6XX_DBGBUS_SPTP_0 = 88 -A6XX_DBGBUS_SPTP_1 = 89 -A6XX_DBGBUS_SPTP_2 = 90 -A6XX_DBGBUS_SPTP_3 = 91 -A6XX_DBGBUS_SPTP_4 = 92 -A6XX_DBGBUS_SPTP_5 = 93 -a6xx_debugbus_id = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_state_location' -a7xx_state_location__enumvalues = { - 0: 'A7XX_HLSQ_STATE', - 1: 'A7XX_HLSQ_DP', - 2: 'A7XX_SP_TOP', - 3: 'A7XX_USPTP', - 4: 'A7XX_HLSQ_DP_STR', -} -A7XX_HLSQ_STATE = 0 -A7XX_HLSQ_DP = 1 -A7XX_SP_TOP = 2 -A7XX_USPTP = 3 -A7XX_HLSQ_DP_STR = 4 -a7xx_state_location = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_pipe' -a7xx_pipe__enumvalues = { - 0: 'A7XX_PIPE_NONE', - 1: 'A7XX_PIPE_BR', - 2: 'A7XX_PIPE_BV', - 3: 'A7XX_PIPE_LPAC', -} -A7XX_PIPE_NONE = 0 -A7XX_PIPE_BR = 1 -A7XX_PIPE_BV = 2 -A7XX_PIPE_LPAC = 3 -a7xx_pipe = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cluster' -a7xx_cluster__enumvalues = { - 0: 'A7XX_CLUSTER_NONE', - 1: 'A7XX_CLUSTER_FE', - 2: 'A7XX_CLUSTER_SP_VS', - 3: 'A7XX_CLUSTER_PC_VS', - 4: 'A7XX_CLUSTER_GRAS', - 5: 'A7XX_CLUSTER_SP_PS', - 6: 'A7XX_CLUSTER_VPC_PS', - 7: 'A7XX_CLUSTER_PS', -} -A7XX_CLUSTER_NONE = 0 -A7XX_CLUSTER_FE = 1 -A7XX_CLUSTER_SP_VS = 2 -A7XX_CLUSTER_PC_VS = 3 -A7XX_CLUSTER_GRAS = 4 -A7XX_CLUSTER_SP_PS = 5 -A7XX_CLUSTER_VPC_PS = 6 -A7XX_CLUSTER_PS = 7 -a7xx_cluster = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_debugbus_id' -a7xx_debugbus_id__enumvalues = { - 1: 'A7XX_DBGBUS_CP_0_0', - 2: 'A7XX_DBGBUS_CP_0_1', - 3: 'A7XX_DBGBUS_RBBM', - 5: 'A7XX_DBGBUS_GBIF_GX', - 6: 'A7XX_DBGBUS_GBIF_CX', - 7: 'A7XX_DBGBUS_HLSQ', - 9: 'A7XX_DBGBUS_UCHE_0', - 10: 'A7XX_DBGBUS_UCHE_1', - 13: 'A7XX_DBGBUS_TESS_BR', - 14: 'A7XX_DBGBUS_TESS_BV', - 17: 'A7XX_DBGBUS_PC_BR', - 18: 'A7XX_DBGBUS_PC_BV', - 21: 'A7XX_DBGBUS_VFDP_BR', - 22: 'A7XX_DBGBUS_VFDP_BV', - 25: 'A7XX_DBGBUS_VPC_BR', - 26: 'A7XX_DBGBUS_VPC_BV', - 29: 'A7XX_DBGBUS_TSE_BR', - 30: 'A7XX_DBGBUS_TSE_BV', - 33: 'A7XX_DBGBUS_RAS_BR', - 34: 'A7XX_DBGBUS_RAS_BV', - 37: 'A7XX_DBGBUS_VSC', - 39: 'A7XX_DBGBUS_COM_0', - 43: 'A7XX_DBGBUS_LRZ_BR', - 44: 'A7XX_DBGBUS_LRZ_BV', - 47: 'A7XX_DBGBUS_UFC_0', - 48: 'A7XX_DBGBUS_UFC_1', - 55: 'A7XX_DBGBUS_GMU_GX', - 59: 'A7XX_DBGBUS_DBGC', - 60: 'A7XX_DBGBUS_CX', - 61: 'A7XX_DBGBUS_GMU_CX', - 62: 'A7XX_DBGBUS_GPC_BR', - 63: 'A7XX_DBGBUS_GPC_BV', - 66: 'A7XX_DBGBUS_LARC', - 68: 'A7XX_DBGBUS_HLSQ_SPTP', - 70: 'A7XX_DBGBUS_RB_0', - 71: 'A7XX_DBGBUS_RB_1', - 72: 'A7XX_DBGBUS_RB_2', - 73: 'A7XX_DBGBUS_RB_3', - 74: 'A7XX_DBGBUS_RB_4', - 75: 'A7XX_DBGBUS_RB_5', - 102: 'A7XX_DBGBUS_UCHE_WRAPPER', - 106: 'A7XX_DBGBUS_CCU_0', - 107: 'A7XX_DBGBUS_CCU_1', - 108: 'A7XX_DBGBUS_CCU_2', - 109: 'A7XX_DBGBUS_CCU_3', - 110: 'A7XX_DBGBUS_CCU_4', - 111: 'A7XX_DBGBUS_CCU_5', - 138: 'A7XX_DBGBUS_VFD_BR_0', - 139: 'A7XX_DBGBUS_VFD_BR_1', - 140: 'A7XX_DBGBUS_VFD_BR_2', - 141: 'A7XX_DBGBUS_VFD_BR_3', - 142: 'A7XX_DBGBUS_VFD_BR_4', - 143: 'A7XX_DBGBUS_VFD_BR_5', - 144: 'A7XX_DBGBUS_VFD_BR_6', - 145: 'A7XX_DBGBUS_VFD_BR_7', - 202: 'A7XX_DBGBUS_VFD_BV_0', - 203: 'A7XX_DBGBUS_VFD_BV_1', - 204: 'A7XX_DBGBUS_VFD_BV_2', - 205: 'A7XX_DBGBUS_VFD_BV_3', - 234: 'A7XX_DBGBUS_USP_0', - 235: 'A7XX_DBGBUS_USP_1', - 236: 'A7XX_DBGBUS_USP_2', - 237: 'A7XX_DBGBUS_USP_3', - 238: 'A7XX_DBGBUS_USP_4', - 239: 'A7XX_DBGBUS_USP_5', - 266: 'A7XX_DBGBUS_TP_0', - 267: 'A7XX_DBGBUS_TP_1', - 268: 'A7XX_DBGBUS_TP_2', - 269: 'A7XX_DBGBUS_TP_3', - 270: 'A7XX_DBGBUS_TP_4', - 271: 'A7XX_DBGBUS_TP_5', - 272: 'A7XX_DBGBUS_TP_6', - 273: 'A7XX_DBGBUS_TP_7', - 274: 'A7XX_DBGBUS_TP_8', - 275: 'A7XX_DBGBUS_TP_9', - 276: 'A7XX_DBGBUS_TP_10', - 277: 'A7XX_DBGBUS_TP_11', - 330: 'A7XX_DBGBUS_USPTP_0', - 331: 'A7XX_DBGBUS_USPTP_1', - 332: 'A7XX_DBGBUS_USPTP_2', - 333: 'A7XX_DBGBUS_USPTP_3', - 334: 'A7XX_DBGBUS_USPTP_4', - 335: 'A7XX_DBGBUS_USPTP_5', - 336: 'A7XX_DBGBUS_USPTP_6', - 337: 'A7XX_DBGBUS_USPTP_7', - 338: 'A7XX_DBGBUS_USPTP_8', - 339: 'A7XX_DBGBUS_USPTP_9', - 340: 'A7XX_DBGBUS_USPTP_10', - 341: 'A7XX_DBGBUS_USPTP_11', - 396: 'A7XX_DBGBUS_CCHE_0', - 397: 'A7XX_DBGBUS_CCHE_1', - 398: 'A7XX_DBGBUS_CCHE_2', - 408: 'A7XX_DBGBUS_VPC_DSTR_0', - 409: 'A7XX_DBGBUS_VPC_DSTR_1', - 410: 'A7XX_DBGBUS_VPC_DSTR_2', - 411: 'A7XX_DBGBUS_HLSQ_DP_STR_0', - 412: 'A7XX_DBGBUS_HLSQ_DP_STR_1', - 413: 'A7XX_DBGBUS_HLSQ_DP_STR_2', - 414: 'A7XX_DBGBUS_HLSQ_DP_STR_3', - 415: 'A7XX_DBGBUS_HLSQ_DP_STR_4', - 416: 'A7XX_DBGBUS_HLSQ_DP_STR_5', - 443: 'A7XX_DBGBUS_UFC_DSTR_0', - 444: 'A7XX_DBGBUS_UFC_DSTR_1', - 445: 'A7XX_DBGBUS_UFC_DSTR_2', - 446: 'A7XX_DBGBUS_CGC_SUBCORE', - 447: 'A7XX_DBGBUS_CGC_CORE', -} -A7XX_DBGBUS_CP_0_0 = 1 -A7XX_DBGBUS_CP_0_1 = 2 -A7XX_DBGBUS_RBBM = 3 -A7XX_DBGBUS_GBIF_GX = 5 -A7XX_DBGBUS_GBIF_CX = 6 -A7XX_DBGBUS_HLSQ = 7 -A7XX_DBGBUS_UCHE_0 = 9 -A7XX_DBGBUS_UCHE_1 = 10 -A7XX_DBGBUS_TESS_BR = 13 -A7XX_DBGBUS_TESS_BV = 14 -A7XX_DBGBUS_PC_BR = 17 -A7XX_DBGBUS_PC_BV = 18 -A7XX_DBGBUS_VFDP_BR = 21 -A7XX_DBGBUS_VFDP_BV = 22 -A7XX_DBGBUS_VPC_BR = 25 -A7XX_DBGBUS_VPC_BV = 26 -A7XX_DBGBUS_TSE_BR = 29 -A7XX_DBGBUS_TSE_BV = 30 -A7XX_DBGBUS_RAS_BR = 33 -A7XX_DBGBUS_RAS_BV = 34 -A7XX_DBGBUS_VSC = 37 -A7XX_DBGBUS_COM_0 = 39 -A7XX_DBGBUS_LRZ_BR = 43 -A7XX_DBGBUS_LRZ_BV = 44 -A7XX_DBGBUS_UFC_0 = 47 -A7XX_DBGBUS_UFC_1 = 48 -A7XX_DBGBUS_GMU_GX = 55 -A7XX_DBGBUS_DBGC = 59 -A7XX_DBGBUS_CX = 60 -A7XX_DBGBUS_GMU_CX = 61 -A7XX_DBGBUS_GPC_BR = 62 -A7XX_DBGBUS_GPC_BV = 63 -A7XX_DBGBUS_LARC = 66 -A7XX_DBGBUS_HLSQ_SPTP = 68 -A7XX_DBGBUS_RB_0 = 70 -A7XX_DBGBUS_RB_1 = 71 -A7XX_DBGBUS_RB_2 = 72 -A7XX_DBGBUS_RB_3 = 73 -A7XX_DBGBUS_RB_4 = 74 -A7XX_DBGBUS_RB_5 = 75 -A7XX_DBGBUS_UCHE_WRAPPER = 102 -A7XX_DBGBUS_CCU_0 = 106 -A7XX_DBGBUS_CCU_1 = 107 -A7XX_DBGBUS_CCU_2 = 108 -A7XX_DBGBUS_CCU_3 = 109 -A7XX_DBGBUS_CCU_4 = 110 -A7XX_DBGBUS_CCU_5 = 111 -A7XX_DBGBUS_VFD_BR_0 = 138 -A7XX_DBGBUS_VFD_BR_1 = 139 -A7XX_DBGBUS_VFD_BR_2 = 140 -A7XX_DBGBUS_VFD_BR_3 = 141 -A7XX_DBGBUS_VFD_BR_4 = 142 -A7XX_DBGBUS_VFD_BR_5 = 143 -A7XX_DBGBUS_VFD_BR_6 = 144 -A7XX_DBGBUS_VFD_BR_7 = 145 -A7XX_DBGBUS_VFD_BV_0 = 202 -A7XX_DBGBUS_VFD_BV_1 = 203 -A7XX_DBGBUS_VFD_BV_2 = 204 -A7XX_DBGBUS_VFD_BV_3 = 205 -A7XX_DBGBUS_USP_0 = 234 -A7XX_DBGBUS_USP_1 = 235 -A7XX_DBGBUS_USP_2 = 236 -A7XX_DBGBUS_USP_3 = 237 -A7XX_DBGBUS_USP_4 = 238 -A7XX_DBGBUS_USP_5 = 239 -A7XX_DBGBUS_TP_0 = 266 -A7XX_DBGBUS_TP_1 = 267 -A7XX_DBGBUS_TP_2 = 268 -A7XX_DBGBUS_TP_3 = 269 -A7XX_DBGBUS_TP_4 = 270 -A7XX_DBGBUS_TP_5 = 271 -A7XX_DBGBUS_TP_6 = 272 -A7XX_DBGBUS_TP_7 = 273 -A7XX_DBGBUS_TP_8 = 274 -A7XX_DBGBUS_TP_9 = 275 -A7XX_DBGBUS_TP_10 = 276 -A7XX_DBGBUS_TP_11 = 277 -A7XX_DBGBUS_USPTP_0 = 330 -A7XX_DBGBUS_USPTP_1 = 331 -A7XX_DBGBUS_USPTP_2 = 332 -A7XX_DBGBUS_USPTP_3 = 333 -A7XX_DBGBUS_USPTP_4 = 334 -A7XX_DBGBUS_USPTP_5 = 335 -A7XX_DBGBUS_USPTP_6 = 336 -A7XX_DBGBUS_USPTP_7 = 337 -A7XX_DBGBUS_USPTP_8 = 338 -A7XX_DBGBUS_USPTP_9 = 339 -A7XX_DBGBUS_USPTP_10 = 340 -A7XX_DBGBUS_USPTP_11 = 341 -A7XX_DBGBUS_CCHE_0 = 396 -A7XX_DBGBUS_CCHE_1 = 397 -A7XX_DBGBUS_CCHE_2 = 398 -A7XX_DBGBUS_VPC_DSTR_0 = 408 -A7XX_DBGBUS_VPC_DSTR_1 = 409 -A7XX_DBGBUS_VPC_DSTR_2 = 410 -A7XX_DBGBUS_HLSQ_DP_STR_0 = 411 -A7XX_DBGBUS_HLSQ_DP_STR_1 = 412 -A7XX_DBGBUS_HLSQ_DP_STR_2 = 413 -A7XX_DBGBUS_HLSQ_DP_STR_3 = 414 -A7XX_DBGBUS_HLSQ_DP_STR_4 = 415 -A7XX_DBGBUS_HLSQ_DP_STR_5 = 416 -A7XX_DBGBUS_UFC_DSTR_0 = 443 -A7XX_DBGBUS_UFC_DSTR_1 = 444 -A7XX_DBGBUS_UFC_DSTR_2 = 445 -A7XX_DBGBUS_CGC_SUBCORE = 446 -A7XX_DBGBUS_CGC_CORE = 447 -a7xx_debugbus_id = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_cp_perfcounter_select' -a6xx_cp_perfcounter_select__enumvalues = { - 0: 'PERF_CP_ALWAYS_COUNT', - 1: 'PERF_CP_BUSY_GFX_CORE_IDLE', - 2: 'PERF_CP_BUSY_CYCLES', - 3: 'PERF_CP_NUM_PREEMPTIONS', - 4: 'PERF_CP_PREEMPTION_REACTION_DELAY', - 5: 'PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 6: 'PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 7: 'PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', - 8: 'PERF_CP_PREDICATED_DRAWS_KILLED', - 9: 'PERF_CP_MODE_SWITCH', - 10: 'PERF_CP_ZPASS_DONE', - 11: 'PERF_CP_CONTEXT_DONE', - 12: 'PERF_CP_CACHE_FLUSH', - 13: 'PERF_CP_LONG_PREEMPTIONS', - 14: 'PERF_CP_SQE_I_CACHE_STARVE', - 15: 'PERF_CP_SQE_IDLE', - 16: 'PERF_CP_SQE_PM4_STARVE_RB_IB', - 17: 'PERF_CP_SQE_PM4_STARVE_SDS', - 18: 'PERF_CP_SQE_MRB_STARVE', - 19: 'PERF_CP_SQE_RRB_STARVE', - 20: 'PERF_CP_SQE_VSD_STARVE', - 21: 'PERF_CP_VSD_DECODE_STARVE', - 22: 'PERF_CP_SQE_PIPE_OUT_STALL', - 23: 'PERF_CP_SQE_SYNC_STALL', - 24: 'PERF_CP_SQE_PM4_WFI_STALL', - 25: 'PERF_CP_SQE_SYS_WFI_STALL', - 26: 'PERF_CP_SQE_T4_EXEC', - 27: 'PERF_CP_SQE_LOAD_STATE_EXEC', - 28: 'PERF_CP_SQE_SAVE_SDS_STATE', - 29: 'PERF_CP_SQE_DRAW_EXEC', - 30: 'PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', - 31: 'PERF_CP_SQE_EXEC_PROFILED', - 32: 'PERF_CP_MEMORY_POOL_EMPTY', - 33: 'PERF_CP_MEMORY_POOL_SYNC_STALL', - 34: 'PERF_CP_MEMORY_POOL_ABOVE_THRESH', - 35: 'PERF_CP_AHB_WR_STALL_PRE_DRAWS', - 36: 'PERF_CP_AHB_STALL_SQE_GMU', - 37: 'PERF_CP_AHB_STALL_SQE_WR_OTHER', - 38: 'PERF_CP_AHB_STALL_SQE_RD_OTHER', - 39: 'PERF_CP_CLUSTER0_EMPTY', - 40: 'PERF_CP_CLUSTER1_EMPTY', - 41: 'PERF_CP_CLUSTER2_EMPTY', - 42: 'PERF_CP_CLUSTER3_EMPTY', - 43: 'PERF_CP_CLUSTER4_EMPTY', - 44: 'PERF_CP_CLUSTER5_EMPTY', - 45: 'PERF_CP_PM4_DATA', - 46: 'PERF_CP_PM4_HEADERS', - 47: 'PERF_CP_VBIF_READ_BEATS', - 48: 'PERF_CP_VBIF_WRITE_BEATS', - 49: 'PERF_CP_SQE_INSTR_COUNTER', -} -PERF_CP_ALWAYS_COUNT = 0 -PERF_CP_BUSY_GFX_CORE_IDLE = 1 -PERF_CP_BUSY_CYCLES = 2 -PERF_CP_NUM_PREEMPTIONS = 3 -PERF_CP_PREEMPTION_REACTION_DELAY = 4 -PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5 -PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6 -PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7 -PERF_CP_PREDICATED_DRAWS_KILLED = 8 -PERF_CP_MODE_SWITCH = 9 -PERF_CP_ZPASS_DONE = 10 -PERF_CP_CONTEXT_DONE = 11 -PERF_CP_CACHE_FLUSH = 12 -PERF_CP_LONG_PREEMPTIONS = 13 -PERF_CP_SQE_I_CACHE_STARVE = 14 -PERF_CP_SQE_IDLE = 15 -PERF_CP_SQE_PM4_STARVE_RB_IB = 16 -PERF_CP_SQE_PM4_STARVE_SDS = 17 -PERF_CP_SQE_MRB_STARVE = 18 -PERF_CP_SQE_RRB_STARVE = 19 -PERF_CP_SQE_VSD_STARVE = 20 -PERF_CP_VSD_DECODE_STARVE = 21 -PERF_CP_SQE_PIPE_OUT_STALL = 22 -PERF_CP_SQE_SYNC_STALL = 23 -PERF_CP_SQE_PM4_WFI_STALL = 24 -PERF_CP_SQE_SYS_WFI_STALL = 25 -PERF_CP_SQE_T4_EXEC = 26 -PERF_CP_SQE_LOAD_STATE_EXEC = 27 -PERF_CP_SQE_SAVE_SDS_STATE = 28 -PERF_CP_SQE_DRAW_EXEC = 29 -PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30 -PERF_CP_SQE_EXEC_PROFILED = 31 -PERF_CP_MEMORY_POOL_EMPTY = 32 -PERF_CP_MEMORY_POOL_SYNC_STALL = 33 -PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34 -PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35 -PERF_CP_AHB_STALL_SQE_GMU = 36 -PERF_CP_AHB_STALL_SQE_WR_OTHER = 37 -PERF_CP_AHB_STALL_SQE_RD_OTHER = 38 -PERF_CP_CLUSTER0_EMPTY = 39 -PERF_CP_CLUSTER1_EMPTY = 40 -PERF_CP_CLUSTER2_EMPTY = 41 -PERF_CP_CLUSTER3_EMPTY = 42 -PERF_CP_CLUSTER4_EMPTY = 43 -PERF_CP_CLUSTER5_EMPTY = 44 -PERF_CP_PM4_DATA = 45 -PERF_CP_PM4_HEADERS = 46 -PERF_CP_VBIF_READ_BEATS = 47 -PERF_CP_VBIF_WRITE_BEATS = 48 -PERF_CP_SQE_INSTR_COUNTER = 49 -a6xx_cp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_rbbm_perfcounter_select' -a6xx_rbbm_perfcounter_select__enumvalues = { - 0: 'PERF_RBBM_ALWAYS_COUNT', - 1: 'PERF_RBBM_ALWAYS_ON', - 2: 'PERF_RBBM_TSE_BUSY', - 3: 'PERF_RBBM_RAS_BUSY', - 4: 'PERF_RBBM_PC_DCALL_BUSY', - 5: 'PERF_RBBM_PC_VSD_BUSY', - 6: 'PERF_RBBM_STATUS_MASKED', - 7: 'PERF_RBBM_COM_BUSY', - 8: 'PERF_RBBM_DCOM_BUSY', - 9: 'PERF_RBBM_VBIF_BUSY', - 10: 'PERF_RBBM_VSC_BUSY', - 11: 'PERF_RBBM_TESS_BUSY', - 12: 'PERF_RBBM_UCHE_BUSY', - 13: 'PERF_RBBM_HLSQ_BUSY', -} -PERF_RBBM_ALWAYS_COUNT = 0 -PERF_RBBM_ALWAYS_ON = 1 -PERF_RBBM_TSE_BUSY = 2 -PERF_RBBM_RAS_BUSY = 3 -PERF_RBBM_PC_DCALL_BUSY = 4 -PERF_RBBM_PC_VSD_BUSY = 5 -PERF_RBBM_STATUS_MASKED = 6 -PERF_RBBM_COM_BUSY = 7 -PERF_RBBM_DCOM_BUSY = 8 -PERF_RBBM_VBIF_BUSY = 9 -PERF_RBBM_VSC_BUSY = 10 -PERF_RBBM_TESS_BUSY = 11 -PERF_RBBM_UCHE_BUSY = 12 -PERF_RBBM_HLSQ_BUSY = 13 -a6xx_rbbm_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_pc_perfcounter_select' -a6xx_pc_perfcounter_select__enumvalues = { - 0: 'PERF_PC_BUSY_CYCLES', - 1: 'PERF_PC_WORKING_CYCLES', - 2: 'PERF_PC_STALL_CYCLES_VFD', - 3: 'PERF_PC_STALL_CYCLES_TSE', - 4: 'PERF_PC_STALL_CYCLES_VPC', - 5: 'PERF_PC_STALL_CYCLES_UCHE', - 6: 'PERF_PC_STALL_CYCLES_TESS', - 7: 'PERF_PC_STALL_CYCLES_TSE_ONLY', - 8: 'PERF_PC_STALL_CYCLES_VPC_ONLY', - 9: 'PERF_PC_PASS1_TF_STALL_CYCLES', - 10: 'PERF_PC_STARVE_CYCLES_FOR_INDEX', - 11: 'PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR', - 12: 'PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM', - 13: 'PERF_PC_STARVE_CYCLES_FOR_POSITION', - 14: 'PERF_PC_STARVE_CYCLES_DI', - 15: 'PERF_PC_VIS_STREAMS_LOADED', - 16: 'PERF_PC_INSTANCES', - 17: 'PERF_PC_VPC_PRIMITIVES', - 18: 'PERF_PC_DEAD_PRIM', - 19: 'PERF_PC_LIVE_PRIM', - 20: 'PERF_PC_VERTEX_HITS', - 21: 'PERF_PC_IA_VERTICES', - 22: 'PERF_PC_IA_PRIMITIVES', - 23: 'PERF_PC_GS_PRIMITIVES', - 24: 'PERF_PC_HS_INVOCATIONS', - 25: 'PERF_PC_DS_INVOCATIONS', - 26: 'PERF_PC_VS_INVOCATIONS', - 27: 'PERF_PC_GS_INVOCATIONS', - 28: 'PERF_PC_DS_PRIMITIVES', - 29: 'PERF_PC_VPC_POS_DATA_TRANSACTION', - 30: 'PERF_PC_3D_DRAWCALLS', - 31: 'PERF_PC_2D_DRAWCALLS', - 32: 'PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS', - 33: 'PERF_TESS_BUSY_CYCLES', - 34: 'PERF_TESS_WORKING_CYCLES', - 35: 'PERF_TESS_STALL_CYCLES_PC', - 36: 'PERF_TESS_STARVE_CYCLES_PC', - 37: 'PERF_PC_TSE_TRANSACTION', - 38: 'PERF_PC_TSE_VERTEX', - 39: 'PERF_PC_TESS_PC_UV_TRANS', - 40: 'PERF_PC_TESS_PC_UV_PATCHES', - 41: 'PERF_PC_TESS_FACTOR_TRANS', -} -PERF_PC_BUSY_CYCLES = 0 -PERF_PC_WORKING_CYCLES = 1 -PERF_PC_STALL_CYCLES_VFD = 2 -PERF_PC_STALL_CYCLES_TSE = 3 -PERF_PC_STALL_CYCLES_VPC = 4 -PERF_PC_STALL_CYCLES_UCHE = 5 -PERF_PC_STALL_CYCLES_TESS = 6 -PERF_PC_STALL_CYCLES_TSE_ONLY = 7 -PERF_PC_STALL_CYCLES_VPC_ONLY = 8 -PERF_PC_PASS1_TF_STALL_CYCLES = 9 -PERF_PC_STARVE_CYCLES_FOR_INDEX = 10 -PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11 -PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12 -PERF_PC_STARVE_CYCLES_FOR_POSITION = 13 -PERF_PC_STARVE_CYCLES_DI = 14 -PERF_PC_VIS_STREAMS_LOADED = 15 -PERF_PC_INSTANCES = 16 -PERF_PC_VPC_PRIMITIVES = 17 -PERF_PC_DEAD_PRIM = 18 -PERF_PC_LIVE_PRIM = 19 -PERF_PC_VERTEX_HITS = 20 -PERF_PC_IA_VERTICES = 21 -PERF_PC_IA_PRIMITIVES = 22 -PERF_PC_GS_PRIMITIVES = 23 -PERF_PC_HS_INVOCATIONS = 24 -PERF_PC_DS_INVOCATIONS = 25 -PERF_PC_VS_INVOCATIONS = 26 -PERF_PC_GS_INVOCATIONS = 27 -PERF_PC_DS_PRIMITIVES = 28 -PERF_PC_VPC_POS_DATA_TRANSACTION = 29 -PERF_PC_3D_DRAWCALLS = 30 -PERF_PC_2D_DRAWCALLS = 31 -PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32 -PERF_TESS_BUSY_CYCLES = 33 -PERF_TESS_WORKING_CYCLES = 34 -PERF_TESS_STALL_CYCLES_PC = 35 -PERF_TESS_STARVE_CYCLES_PC = 36 -PERF_PC_TSE_TRANSACTION = 37 -PERF_PC_TSE_VERTEX = 38 -PERF_PC_TESS_PC_UV_TRANS = 39 -PERF_PC_TESS_PC_UV_PATCHES = 40 -PERF_PC_TESS_FACTOR_TRANS = 41 -a6xx_pc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_vfd_perfcounter_select' -a6xx_vfd_perfcounter_select__enumvalues = { - 0: 'PERF_VFD_BUSY_CYCLES', - 1: 'PERF_VFD_STALL_CYCLES_UCHE', - 2: 'PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 3: 'PERF_VFD_STALL_CYCLES_SP_INFO', - 4: 'PERF_VFD_STALL_CYCLES_SP_ATTR', - 5: 'PERF_VFD_STARVE_CYCLES_UCHE', - 6: 'PERF_VFD_RBUFFER_FULL', - 7: 'PERF_VFD_ATTR_INFO_FIFO_FULL', - 8: 'PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 9: 'PERF_VFD_NUM_ATTRIBUTES', - 10: 'PERF_VFD_UPPER_SHADER_FIBERS', - 11: 'PERF_VFD_LOWER_SHADER_FIBERS', - 12: 'PERF_VFD_MODE_0_FIBERS', - 13: 'PERF_VFD_MODE_1_FIBERS', - 14: 'PERF_VFD_MODE_2_FIBERS', - 15: 'PERF_VFD_MODE_3_FIBERS', - 16: 'PERF_VFD_MODE_4_FIBERS', - 17: 'PERF_VFD_TOTAL_VERTICES', - 18: 'PERF_VFDP_STALL_CYCLES_VFD', - 19: 'PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 20: 'PERF_VFDP_STALL_CYCLES_VFD_PROG', - 21: 'PERF_VFDP_STARVE_CYCLES_PC', - 22: 'PERF_VFDP_VS_STAGE_WAVES', -} -PERF_VFD_BUSY_CYCLES = 0 -PERF_VFD_STALL_CYCLES_UCHE = 1 -PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2 -PERF_VFD_STALL_CYCLES_SP_INFO = 3 -PERF_VFD_STALL_CYCLES_SP_ATTR = 4 -PERF_VFD_STARVE_CYCLES_UCHE = 5 -PERF_VFD_RBUFFER_FULL = 6 -PERF_VFD_ATTR_INFO_FIFO_FULL = 7 -PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8 -PERF_VFD_NUM_ATTRIBUTES = 9 -PERF_VFD_UPPER_SHADER_FIBERS = 10 -PERF_VFD_LOWER_SHADER_FIBERS = 11 -PERF_VFD_MODE_0_FIBERS = 12 -PERF_VFD_MODE_1_FIBERS = 13 -PERF_VFD_MODE_2_FIBERS = 14 -PERF_VFD_MODE_3_FIBERS = 15 -PERF_VFD_MODE_4_FIBERS = 16 -PERF_VFD_TOTAL_VERTICES = 17 -PERF_VFDP_STALL_CYCLES_VFD = 18 -PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19 -PERF_VFDP_STALL_CYCLES_VFD_PROG = 20 -PERF_VFDP_STARVE_CYCLES_PC = 21 -PERF_VFDP_VS_STAGE_WAVES = 22 -a6xx_vfd_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_hlsq_perfcounter_select' -a6xx_hlsq_perfcounter_select__enumvalues = { - 0: 'PERF_HLSQ_BUSY_CYCLES', - 1: 'PERF_HLSQ_STALL_CYCLES_UCHE', - 2: 'PERF_HLSQ_STALL_CYCLES_SP_STATE', - 3: 'PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 4: 'PERF_HLSQ_UCHE_LATENCY_CYCLES', - 5: 'PERF_HLSQ_UCHE_LATENCY_COUNT', - 6: 'PERF_HLSQ_FS_STAGE_1X_WAVES', - 7: 'PERF_HLSQ_FS_STAGE_2X_WAVES', - 8: 'PERF_HLSQ_QUADS', - 9: 'PERF_HLSQ_CS_INVOCATIONS', - 10: 'PERF_HLSQ_COMPUTE_DRAWCALLS', - 11: 'PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 12: 'PERF_HLSQ_DUAL_FS_PROG_ACTIVE', - 13: 'PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 14: 'PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 15: 'PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 16: 'PERF_HLSQ_WAVE_PENDING_NO_QUAD', - 17: 'PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 18: 'PERF_HLSQ_STALL_CYCLES_VPC', - 19: 'PERF_HLSQ_PIXELS', - 20: 'PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC', -} -PERF_HLSQ_BUSY_CYCLES = 0 -PERF_HLSQ_STALL_CYCLES_UCHE = 1 -PERF_HLSQ_STALL_CYCLES_SP_STATE = 2 -PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3 -PERF_HLSQ_UCHE_LATENCY_CYCLES = 4 -PERF_HLSQ_UCHE_LATENCY_COUNT = 5 -PERF_HLSQ_FS_STAGE_1X_WAVES = 6 -PERF_HLSQ_FS_STAGE_2X_WAVES = 7 -PERF_HLSQ_QUADS = 8 -PERF_HLSQ_CS_INVOCATIONS = 9 -PERF_HLSQ_COMPUTE_DRAWCALLS = 10 -PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11 -PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12 -PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13 -PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14 -PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15 -PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16 -PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17 -PERF_HLSQ_STALL_CYCLES_VPC = 18 -PERF_HLSQ_PIXELS = 19 -PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20 -a6xx_hlsq_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_vpc_perfcounter_select' -a6xx_vpc_perfcounter_select__enumvalues = { - 0: 'PERF_VPC_BUSY_CYCLES', - 1: 'PERF_VPC_WORKING_CYCLES', - 2: 'PERF_VPC_STALL_CYCLES_UCHE', - 3: 'PERF_VPC_STALL_CYCLES_VFD_WACK', - 4: 'PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 5: 'PERF_VPC_STALL_CYCLES_PC', - 6: 'PERF_VPC_STALL_CYCLES_SP_LM', - 7: 'PERF_VPC_STARVE_CYCLES_SP', - 8: 'PERF_VPC_STARVE_CYCLES_LRZ', - 9: 'PERF_VPC_PC_PRIMITIVES', - 10: 'PERF_VPC_SP_COMPONENTS', - 11: 'PERF_VPC_STALL_CYCLES_VPCRAM_POS', - 12: 'PERF_VPC_LRZ_ASSIGN_PRIMITIVES', - 13: 'PERF_VPC_RB_VISIBLE_PRIMITIVES', - 14: 'PERF_VPC_LM_TRANSACTION', - 15: 'PERF_VPC_STREAMOUT_TRANSACTION', - 16: 'PERF_VPC_VS_BUSY_CYCLES', - 17: 'PERF_VPC_PS_BUSY_CYCLES', - 18: 'PERF_VPC_VS_WORKING_CYCLES', - 19: 'PERF_VPC_PS_WORKING_CYCLES', - 20: 'PERF_VPC_STARVE_CYCLES_RB', - 21: 'PERF_VPC_NUM_VPCRAM_READ_POS', - 22: 'PERF_VPC_WIT_FULL_CYCLES', - 23: 'PERF_VPC_VPCRAM_FULL_CYCLES', - 24: 'PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', - 25: 'PERF_VPC_NUM_VPCRAM_WRITE', - 26: 'PERF_VPC_NUM_VPCRAM_READ_SO', - 27: 'PERF_VPC_NUM_ATTR_REQ_LM', -} -PERF_VPC_BUSY_CYCLES = 0 -PERF_VPC_WORKING_CYCLES = 1 -PERF_VPC_STALL_CYCLES_UCHE = 2 -PERF_VPC_STALL_CYCLES_VFD_WACK = 3 -PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4 -PERF_VPC_STALL_CYCLES_PC = 5 -PERF_VPC_STALL_CYCLES_SP_LM = 6 -PERF_VPC_STARVE_CYCLES_SP = 7 -PERF_VPC_STARVE_CYCLES_LRZ = 8 -PERF_VPC_PC_PRIMITIVES = 9 -PERF_VPC_SP_COMPONENTS = 10 -PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11 -PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12 -PERF_VPC_RB_VISIBLE_PRIMITIVES = 13 -PERF_VPC_LM_TRANSACTION = 14 -PERF_VPC_STREAMOUT_TRANSACTION = 15 -PERF_VPC_VS_BUSY_CYCLES = 16 -PERF_VPC_PS_BUSY_CYCLES = 17 -PERF_VPC_VS_WORKING_CYCLES = 18 -PERF_VPC_PS_WORKING_CYCLES = 19 -PERF_VPC_STARVE_CYCLES_RB = 20 -PERF_VPC_NUM_VPCRAM_READ_POS = 21 -PERF_VPC_WIT_FULL_CYCLES = 22 -PERF_VPC_VPCRAM_FULL_CYCLES = 23 -PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24 -PERF_VPC_NUM_VPCRAM_WRITE = 25 -PERF_VPC_NUM_VPCRAM_READ_SO = 26 -PERF_VPC_NUM_ATTR_REQ_LM = 27 -a6xx_vpc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tse_perfcounter_select' -a6xx_tse_perfcounter_select__enumvalues = { - 0: 'PERF_TSE_BUSY_CYCLES', - 1: 'PERF_TSE_CLIPPING_CYCLES', - 2: 'PERF_TSE_STALL_CYCLES_RAS', - 3: 'PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE', - 4: 'PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', - 5: 'PERF_TSE_STARVE_CYCLES_PC', - 6: 'PERF_TSE_INPUT_PRIM', - 7: 'PERF_TSE_INPUT_NULL_PRIM', - 8: 'PERF_TSE_TRIVAL_REJ_PRIM', - 9: 'PERF_TSE_CLIPPED_PRIM', - 10: 'PERF_TSE_ZERO_AREA_PRIM', - 11: 'PERF_TSE_FACENESS_CULLED_PRIM', - 12: 'PERF_TSE_ZERO_PIXEL_PRIM', - 13: 'PERF_TSE_OUTPUT_NULL_PRIM', - 14: 'PERF_TSE_OUTPUT_VISIBLE_PRIM', - 15: 'PERF_TSE_CINVOCATION', - 16: 'PERF_TSE_CPRIMITIVES', - 17: 'PERF_TSE_2D_INPUT_PRIM', - 18: 'PERF_TSE_2D_ALIVE_CYCLES', - 19: 'PERF_TSE_CLIP_PLANES', -} -PERF_TSE_BUSY_CYCLES = 0 -PERF_TSE_CLIPPING_CYCLES = 1 -PERF_TSE_STALL_CYCLES_RAS = 2 -PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3 -PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4 -PERF_TSE_STARVE_CYCLES_PC = 5 -PERF_TSE_INPUT_PRIM = 6 -PERF_TSE_INPUT_NULL_PRIM = 7 -PERF_TSE_TRIVAL_REJ_PRIM = 8 -PERF_TSE_CLIPPED_PRIM = 9 -PERF_TSE_ZERO_AREA_PRIM = 10 -PERF_TSE_FACENESS_CULLED_PRIM = 11 -PERF_TSE_ZERO_PIXEL_PRIM = 12 -PERF_TSE_OUTPUT_NULL_PRIM = 13 -PERF_TSE_OUTPUT_VISIBLE_PRIM = 14 -PERF_TSE_CINVOCATION = 15 -PERF_TSE_CPRIMITIVES = 16 -PERF_TSE_2D_INPUT_PRIM = 17 -PERF_TSE_2D_ALIVE_CYCLES = 18 -PERF_TSE_CLIP_PLANES = 19 -a6xx_tse_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ras_perfcounter_select' -a6xx_ras_perfcounter_select__enumvalues = { - 0: 'PERF_RAS_BUSY_CYCLES', - 1: 'PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 2: 'PERF_RAS_STALL_CYCLES_LRZ', - 3: 'PERF_RAS_STARVE_CYCLES_TSE', - 4: 'PERF_RAS_SUPER_TILES', - 5: 'PERF_RAS_8X4_TILES', - 6: 'PERF_RAS_MASKGEN_ACTIVE', - 7: 'PERF_RAS_FULLY_COVERED_SUPER_TILES', - 8: 'PERF_RAS_FULLY_COVERED_8X4_TILES', - 9: 'PERF_RAS_PRIM_KILLED_INVISILBE', - 10: 'PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', - 11: 'PERF_RAS_LRZ_INTF_WORKING_CYCLES', - 12: 'PERF_RAS_BLOCKS', -} -PERF_RAS_BUSY_CYCLES = 0 -PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1 -PERF_RAS_STALL_CYCLES_LRZ = 2 -PERF_RAS_STARVE_CYCLES_TSE = 3 -PERF_RAS_SUPER_TILES = 4 -PERF_RAS_8X4_TILES = 5 -PERF_RAS_MASKGEN_ACTIVE = 6 -PERF_RAS_FULLY_COVERED_SUPER_TILES = 7 -PERF_RAS_FULLY_COVERED_8X4_TILES = 8 -PERF_RAS_PRIM_KILLED_INVISILBE = 9 -PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10 -PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11 -PERF_RAS_BLOCKS = 12 -a6xx_ras_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_uche_perfcounter_select' -a6xx_uche_perfcounter_select__enumvalues = { - 0: 'PERF_UCHE_BUSY_CYCLES', - 1: 'PERF_UCHE_STALL_CYCLES_ARBITER', - 2: 'PERF_UCHE_VBIF_LATENCY_CYCLES', - 3: 'PERF_UCHE_VBIF_LATENCY_SAMPLES', - 4: 'PERF_UCHE_VBIF_READ_BEATS_TP', - 5: 'PERF_UCHE_VBIF_READ_BEATS_VFD', - 6: 'PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 7: 'PERF_UCHE_VBIF_READ_BEATS_LRZ', - 8: 'PERF_UCHE_VBIF_READ_BEATS_SP', - 9: 'PERF_UCHE_READ_REQUESTS_TP', - 10: 'PERF_UCHE_READ_REQUESTS_VFD', - 11: 'PERF_UCHE_READ_REQUESTS_HLSQ', - 12: 'PERF_UCHE_READ_REQUESTS_LRZ', - 13: 'PERF_UCHE_READ_REQUESTS_SP', - 14: 'PERF_UCHE_WRITE_REQUESTS_LRZ', - 15: 'PERF_UCHE_WRITE_REQUESTS_SP', - 16: 'PERF_UCHE_WRITE_REQUESTS_VPC', - 17: 'PERF_UCHE_WRITE_REQUESTS_VSC', - 18: 'PERF_UCHE_EVICTS', - 19: 'PERF_UCHE_BANK_REQ0', - 20: 'PERF_UCHE_BANK_REQ1', - 21: 'PERF_UCHE_BANK_REQ2', - 22: 'PERF_UCHE_BANK_REQ3', - 23: 'PERF_UCHE_BANK_REQ4', - 24: 'PERF_UCHE_BANK_REQ5', - 25: 'PERF_UCHE_BANK_REQ6', - 26: 'PERF_UCHE_BANK_REQ7', - 27: 'PERF_UCHE_VBIF_READ_BEATS_CH0', - 28: 'PERF_UCHE_VBIF_READ_BEATS_CH1', - 29: 'PERF_UCHE_GMEM_READ_BEATS', - 30: 'PERF_UCHE_TPH_REF_FULL', - 31: 'PERF_UCHE_TPH_VICTIM_FULL', - 32: 'PERF_UCHE_TPH_EXT_FULL', - 33: 'PERF_UCHE_VBIF_STALL_WRITE_DATA', - 34: 'PERF_UCHE_DCMP_LATENCY_SAMPLES', - 35: 'PERF_UCHE_DCMP_LATENCY_CYCLES', - 36: 'PERF_UCHE_VBIF_READ_BEATS_PC', - 37: 'PERF_UCHE_READ_REQUESTS_PC', - 38: 'PERF_UCHE_RAM_READ_REQ', - 39: 'PERF_UCHE_RAM_WRITE_REQ', -} -PERF_UCHE_BUSY_CYCLES = 0 -PERF_UCHE_STALL_CYCLES_ARBITER = 1 -PERF_UCHE_VBIF_LATENCY_CYCLES = 2 -PERF_UCHE_VBIF_LATENCY_SAMPLES = 3 -PERF_UCHE_VBIF_READ_BEATS_TP = 4 -PERF_UCHE_VBIF_READ_BEATS_VFD = 5 -PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6 -PERF_UCHE_VBIF_READ_BEATS_LRZ = 7 -PERF_UCHE_VBIF_READ_BEATS_SP = 8 -PERF_UCHE_READ_REQUESTS_TP = 9 -PERF_UCHE_READ_REQUESTS_VFD = 10 -PERF_UCHE_READ_REQUESTS_HLSQ = 11 -PERF_UCHE_READ_REQUESTS_LRZ = 12 -PERF_UCHE_READ_REQUESTS_SP = 13 -PERF_UCHE_WRITE_REQUESTS_LRZ = 14 -PERF_UCHE_WRITE_REQUESTS_SP = 15 -PERF_UCHE_WRITE_REQUESTS_VPC = 16 -PERF_UCHE_WRITE_REQUESTS_VSC = 17 -PERF_UCHE_EVICTS = 18 -PERF_UCHE_BANK_REQ0 = 19 -PERF_UCHE_BANK_REQ1 = 20 -PERF_UCHE_BANK_REQ2 = 21 -PERF_UCHE_BANK_REQ3 = 22 -PERF_UCHE_BANK_REQ4 = 23 -PERF_UCHE_BANK_REQ5 = 24 -PERF_UCHE_BANK_REQ6 = 25 -PERF_UCHE_BANK_REQ7 = 26 -PERF_UCHE_VBIF_READ_BEATS_CH0 = 27 -PERF_UCHE_VBIF_READ_BEATS_CH1 = 28 -PERF_UCHE_GMEM_READ_BEATS = 29 -PERF_UCHE_TPH_REF_FULL = 30 -PERF_UCHE_TPH_VICTIM_FULL = 31 -PERF_UCHE_TPH_EXT_FULL = 32 -PERF_UCHE_VBIF_STALL_WRITE_DATA = 33 -PERF_UCHE_DCMP_LATENCY_SAMPLES = 34 -PERF_UCHE_DCMP_LATENCY_CYCLES = 35 -PERF_UCHE_VBIF_READ_BEATS_PC = 36 -PERF_UCHE_READ_REQUESTS_PC = 37 -PERF_UCHE_RAM_READ_REQ = 38 -PERF_UCHE_RAM_WRITE_REQ = 39 -a6xx_uche_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tp_perfcounter_select' -a6xx_tp_perfcounter_select__enumvalues = { - 0: 'PERF_TP_BUSY_CYCLES', - 1: 'PERF_TP_STALL_CYCLES_UCHE', - 2: 'PERF_TP_LATENCY_CYCLES', - 3: 'PERF_TP_LATENCY_TRANS', - 4: 'PERF_TP_FLAG_CACHE_REQUEST_SAMPLES', - 5: 'PERF_TP_FLAG_CACHE_REQUEST_LATENCY', - 6: 'PERF_TP_L1_CACHELINE_REQUESTS', - 7: 'PERF_TP_L1_CACHELINE_MISSES', - 8: 'PERF_TP_SP_TP_TRANS', - 9: 'PERF_TP_TP_SP_TRANS', - 10: 'PERF_TP_OUTPUT_PIXELS', - 11: 'PERF_TP_FILTER_WORKLOAD_16BIT', - 12: 'PERF_TP_FILTER_WORKLOAD_32BIT', - 13: 'PERF_TP_QUADS_RECEIVED', - 14: 'PERF_TP_QUADS_OFFSET', - 15: 'PERF_TP_QUADS_SHADOW', - 16: 'PERF_TP_QUADS_ARRAY', - 17: 'PERF_TP_QUADS_GRADIENT', - 18: 'PERF_TP_QUADS_1D', - 19: 'PERF_TP_QUADS_2D', - 20: 'PERF_TP_QUADS_BUFFER', - 21: 'PERF_TP_QUADS_3D', - 22: 'PERF_TP_QUADS_CUBE', - 23: 'PERF_TP_DIVERGENT_QUADS_RECEIVED', - 24: 'PERF_TP_PRT_NON_RESIDENT_EVENTS', - 25: 'PERF_TP_OUTPUT_PIXELS_POINT', - 26: 'PERF_TP_OUTPUT_PIXELS_BILINEAR', - 27: 'PERF_TP_OUTPUT_PIXELS_MIP', - 28: 'PERF_TP_OUTPUT_PIXELS_ANISO', - 29: 'PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 30: 'PERF_TP_FLAG_CACHE_REQUESTS', - 31: 'PERF_TP_FLAG_CACHE_MISSES', - 32: 'PERF_TP_L1_5_L2_REQUESTS', - 33: 'PERF_TP_2D_OUTPUT_PIXELS', - 34: 'PERF_TP_2D_OUTPUT_PIXELS_POINT', - 35: 'PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 36: 'PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 37: 'PERF_TP_2D_FILTER_WORKLOAD_32BIT', - 38: 'PERF_TP_TPA2TPC_TRANS', - 39: 'PERF_TP_L1_MISSES_ASTC_1TILE', - 40: 'PERF_TP_L1_MISSES_ASTC_2TILE', - 41: 'PERF_TP_L1_MISSES_ASTC_4TILE', - 42: 'PERF_TP_L1_5_L2_COMPRESS_REQS', - 43: 'PERF_TP_L1_5_L2_COMPRESS_MISS', - 44: 'PERF_TP_L1_BANK_CONFLICT', - 45: 'PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 46: 'PERF_TP_L1_5_MISS_LATENCY_TRANS', - 47: 'PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 48: 'PERF_TP_FRONTEND_WORKING_CYCLES', - 49: 'PERF_TP_L1_TAG_WORKING_CYCLES', - 50: 'PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 51: 'PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 52: 'PERF_TP_BACKEND_WORKING_CYCLES', - 53: 'PERF_TP_FLAG_CACHE_WORKING_CYCLES', - 54: 'PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 55: 'PERF_TP_STARVE_CYCLES_SP', - 56: 'PERF_TP_STARVE_CYCLES_UCHE', -} -PERF_TP_BUSY_CYCLES = 0 -PERF_TP_STALL_CYCLES_UCHE = 1 -PERF_TP_LATENCY_CYCLES = 2 -PERF_TP_LATENCY_TRANS = 3 -PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4 -PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5 -PERF_TP_L1_CACHELINE_REQUESTS = 6 -PERF_TP_L1_CACHELINE_MISSES = 7 -PERF_TP_SP_TP_TRANS = 8 -PERF_TP_TP_SP_TRANS = 9 -PERF_TP_OUTPUT_PIXELS = 10 -PERF_TP_FILTER_WORKLOAD_16BIT = 11 -PERF_TP_FILTER_WORKLOAD_32BIT = 12 -PERF_TP_QUADS_RECEIVED = 13 -PERF_TP_QUADS_OFFSET = 14 -PERF_TP_QUADS_SHADOW = 15 -PERF_TP_QUADS_ARRAY = 16 -PERF_TP_QUADS_GRADIENT = 17 -PERF_TP_QUADS_1D = 18 -PERF_TP_QUADS_2D = 19 -PERF_TP_QUADS_BUFFER = 20 -PERF_TP_QUADS_3D = 21 -PERF_TP_QUADS_CUBE = 22 -PERF_TP_DIVERGENT_QUADS_RECEIVED = 23 -PERF_TP_PRT_NON_RESIDENT_EVENTS = 24 -PERF_TP_OUTPUT_PIXELS_POINT = 25 -PERF_TP_OUTPUT_PIXELS_BILINEAR = 26 -PERF_TP_OUTPUT_PIXELS_MIP = 27 -PERF_TP_OUTPUT_PIXELS_ANISO = 28 -PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29 -PERF_TP_FLAG_CACHE_REQUESTS = 30 -PERF_TP_FLAG_CACHE_MISSES = 31 -PERF_TP_L1_5_L2_REQUESTS = 32 -PERF_TP_2D_OUTPUT_PIXELS = 33 -PERF_TP_2D_OUTPUT_PIXELS_POINT = 34 -PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35 -PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36 -PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37 -PERF_TP_TPA2TPC_TRANS = 38 -PERF_TP_L1_MISSES_ASTC_1TILE = 39 -PERF_TP_L1_MISSES_ASTC_2TILE = 40 -PERF_TP_L1_MISSES_ASTC_4TILE = 41 -PERF_TP_L1_5_L2_COMPRESS_REQS = 42 -PERF_TP_L1_5_L2_COMPRESS_MISS = 43 -PERF_TP_L1_BANK_CONFLICT = 44 -PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45 -PERF_TP_L1_5_MISS_LATENCY_TRANS = 46 -PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47 -PERF_TP_FRONTEND_WORKING_CYCLES = 48 -PERF_TP_L1_TAG_WORKING_CYCLES = 49 -PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50 -PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51 -PERF_TP_BACKEND_WORKING_CYCLES = 52 -PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53 -PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54 -PERF_TP_STARVE_CYCLES_SP = 55 -PERF_TP_STARVE_CYCLES_UCHE = 56 -a6xx_tp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_sp_perfcounter_select' -a6xx_sp_perfcounter_select__enumvalues = { - 0: 'PERF_SP_BUSY_CYCLES', - 1: 'PERF_SP_ALU_WORKING_CYCLES', - 2: 'PERF_SP_EFU_WORKING_CYCLES', - 3: 'PERF_SP_STALL_CYCLES_VPC', - 4: 'PERF_SP_STALL_CYCLES_TP', - 5: 'PERF_SP_STALL_CYCLES_UCHE', - 6: 'PERF_SP_STALL_CYCLES_RB', - 7: 'PERF_SP_NON_EXECUTION_CYCLES', - 8: 'PERF_SP_WAVE_CONTEXTS', - 9: 'PERF_SP_WAVE_CONTEXT_CYCLES', - 10: 'PERF_SP_FS_STAGE_WAVE_CYCLES', - 11: 'PERF_SP_FS_STAGE_WAVE_SAMPLES', - 12: 'PERF_SP_VS_STAGE_WAVE_CYCLES', - 13: 'PERF_SP_VS_STAGE_WAVE_SAMPLES', - 14: 'PERF_SP_FS_STAGE_DURATION_CYCLES', - 15: 'PERF_SP_VS_STAGE_DURATION_CYCLES', - 16: 'PERF_SP_WAVE_CTRL_CYCLES', - 17: 'PERF_SP_WAVE_LOAD_CYCLES', - 18: 'PERF_SP_WAVE_EMIT_CYCLES', - 19: 'PERF_SP_WAVE_NOP_CYCLES', - 20: 'PERF_SP_WAVE_WAIT_CYCLES', - 21: 'PERF_SP_WAVE_FETCH_CYCLES', - 22: 'PERF_SP_WAVE_IDLE_CYCLES', - 23: 'PERF_SP_WAVE_END_CYCLES', - 24: 'PERF_SP_WAVE_LONG_SYNC_CYCLES', - 25: 'PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 26: 'PERF_SP_WAVE_JOIN_CYCLES', - 27: 'PERF_SP_LM_LOAD_INSTRUCTIONS', - 28: 'PERF_SP_LM_STORE_INSTRUCTIONS', - 29: 'PERF_SP_LM_ATOMICS', - 30: 'PERF_SP_GM_LOAD_INSTRUCTIONS', - 31: 'PERF_SP_GM_STORE_INSTRUCTIONS', - 32: 'PERF_SP_GM_ATOMICS', - 33: 'PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 34: 'PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 35: 'PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 36: 'PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 37: 'PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 38: 'PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 39: 'PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 40: 'PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 41: 'PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 42: 'PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 43: 'PERF_SP_VS_INSTRUCTIONS', - 44: 'PERF_SP_FS_INSTRUCTIONS', - 45: 'PERF_SP_ADDR_LOCK_COUNT', - 46: 'PERF_SP_UCHE_READ_TRANS', - 47: 'PERF_SP_UCHE_WRITE_TRANS', - 48: 'PERF_SP_EXPORT_VPC_TRANS', - 49: 'PERF_SP_EXPORT_RB_TRANS', - 50: 'PERF_SP_PIXELS_KILLED', - 51: 'PERF_SP_ICL1_REQUESTS', - 52: 'PERF_SP_ICL1_MISSES', - 53: 'PERF_SP_HS_INSTRUCTIONS', - 54: 'PERF_SP_DS_INSTRUCTIONS', - 55: 'PERF_SP_GS_INSTRUCTIONS', - 56: 'PERF_SP_CS_INSTRUCTIONS', - 57: 'PERF_SP_GPR_READ', - 58: 'PERF_SP_GPR_WRITE', - 59: 'PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 60: 'PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 61: 'PERF_SP_LM_BANK_CONFLICTS', - 62: 'PERF_SP_TEX_CONTROL_WORKING_CYCLES', - 63: 'PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 64: 'PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 65: 'PERF_SP_LM_WORKING_CYCLES', - 66: 'PERF_SP_DISPATCHER_WORKING_CYCLES', - 67: 'PERF_SP_SEQUENCER_WORKING_CYCLES', - 68: 'PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 69: 'PERF_SP_STARVE_CYCLES_HLSQ', - 70: 'PERF_SP_NON_EXECUTION_LS_CYCLES', - 71: 'PERF_SP_WORKING_EU', - 72: 'PERF_SP_ANY_EU_WORKING', - 73: 'PERF_SP_WORKING_EU_FS_STAGE', - 74: 'PERF_SP_ANY_EU_WORKING_FS_STAGE', - 75: 'PERF_SP_WORKING_EU_VS_STAGE', - 76: 'PERF_SP_ANY_EU_WORKING_VS_STAGE', - 77: 'PERF_SP_WORKING_EU_CS_STAGE', - 78: 'PERF_SP_ANY_EU_WORKING_CS_STAGE', - 79: 'PERF_SP_GPR_READ_PREFETCH', - 80: 'PERF_SP_GPR_READ_CONFLICT', - 81: 'PERF_SP_GPR_WRITE_CONFLICT', - 82: 'PERF_SP_GM_LOAD_LATENCY_CYCLES', - 83: 'PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 84: 'PERF_SP_EXECUTABLE_WAVES', -} -PERF_SP_BUSY_CYCLES = 0 -PERF_SP_ALU_WORKING_CYCLES = 1 -PERF_SP_EFU_WORKING_CYCLES = 2 -PERF_SP_STALL_CYCLES_VPC = 3 -PERF_SP_STALL_CYCLES_TP = 4 -PERF_SP_STALL_CYCLES_UCHE = 5 -PERF_SP_STALL_CYCLES_RB = 6 -PERF_SP_NON_EXECUTION_CYCLES = 7 -PERF_SP_WAVE_CONTEXTS = 8 -PERF_SP_WAVE_CONTEXT_CYCLES = 9 -PERF_SP_FS_STAGE_WAVE_CYCLES = 10 -PERF_SP_FS_STAGE_WAVE_SAMPLES = 11 -PERF_SP_VS_STAGE_WAVE_CYCLES = 12 -PERF_SP_VS_STAGE_WAVE_SAMPLES = 13 -PERF_SP_FS_STAGE_DURATION_CYCLES = 14 -PERF_SP_VS_STAGE_DURATION_CYCLES = 15 -PERF_SP_WAVE_CTRL_CYCLES = 16 -PERF_SP_WAVE_LOAD_CYCLES = 17 -PERF_SP_WAVE_EMIT_CYCLES = 18 -PERF_SP_WAVE_NOP_CYCLES = 19 -PERF_SP_WAVE_WAIT_CYCLES = 20 -PERF_SP_WAVE_FETCH_CYCLES = 21 -PERF_SP_WAVE_IDLE_CYCLES = 22 -PERF_SP_WAVE_END_CYCLES = 23 -PERF_SP_WAVE_LONG_SYNC_CYCLES = 24 -PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25 -PERF_SP_WAVE_JOIN_CYCLES = 26 -PERF_SP_LM_LOAD_INSTRUCTIONS = 27 -PERF_SP_LM_STORE_INSTRUCTIONS = 28 -PERF_SP_LM_ATOMICS = 29 -PERF_SP_GM_LOAD_INSTRUCTIONS = 30 -PERF_SP_GM_STORE_INSTRUCTIONS = 31 -PERF_SP_GM_ATOMICS = 32 -PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33 -PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34 -PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35 -PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36 -PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37 -PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38 -PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39 -PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40 -PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41 -PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42 -PERF_SP_VS_INSTRUCTIONS = 43 -PERF_SP_FS_INSTRUCTIONS = 44 -PERF_SP_ADDR_LOCK_COUNT = 45 -PERF_SP_UCHE_READ_TRANS = 46 -PERF_SP_UCHE_WRITE_TRANS = 47 -PERF_SP_EXPORT_VPC_TRANS = 48 -PERF_SP_EXPORT_RB_TRANS = 49 -PERF_SP_PIXELS_KILLED = 50 -PERF_SP_ICL1_REQUESTS = 51 -PERF_SP_ICL1_MISSES = 52 -PERF_SP_HS_INSTRUCTIONS = 53 -PERF_SP_DS_INSTRUCTIONS = 54 -PERF_SP_GS_INSTRUCTIONS = 55 -PERF_SP_CS_INSTRUCTIONS = 56 -PERF_SP_GPR_READ = 57 -PERF_SP_GPR_WRITE = 58 -PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59 -PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60 -PERF_SP_LM_BANK_CONFLICTS = 61 -PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62 -PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63 -PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64 -PERF_SP_LM_WORKING_CYCLES = 65 -PERF_SP_DISPATCHER_WORKING_CYCLES = 66 -PERF_SP_SEQUENCER_WORKING_CYCLES = 67 -PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68 -PERF_SP_STARVE_CYCLES_HLSQ = 69 -PERF_SP_NON_EXECUTION_LS_CYCLES = 70 -PERF_SP_WORKING_EU = 71 -PERF_SP_ANY_EU_WORKING = 72 -PERF_SP_WORKING_EU_FS_STAGE = 73 -PERF_SP_ANY_EU_WORKING_FS_STAGE = 74 -PERF_SP_WORKING_EU_VS_STAGE = 75 -PERF_SP_ANY_EU_WORKING_VS_STAGE = 76 -PERF_SP_WORKING_EU_CS_STAGE = 77 -PERF_SP_ANY_EU_WORKING_CS_STAGE = 78 -PERF_SP_GPR_READ_PREFETCH = 79 -PERF_SP_GPR_READ_CONFLICT = 80 -PERF_SP_GPR_WRITE_CONFLICT = 81 -PERF_SP_GM_LOAD_LATENCY_CYCLES = 82 -PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83 -PERF_SP_EXECUTABLE_WAVES = 84 -a6xx_sp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_rb_perfcounter_select' -a6xx_rb_perfcounter_select__enumvalues = { - 0: 'PERF_RB_BUSY_CYCLES', - 1: 'PERF_RB_STALL_CYCLES_HLSQ', - 2: 'PERF_RB_STALL_CYCLES_FIFO0_FULL', - 3: 'PERF_RB_STALL_CYCLES_FIFO1_FULL', - 4: 'PERF_RB_STALL_CYCLES_FIFO2_FULL', - 5: 'PERF_RB_STARVE_CYCLES_SP', - 6: 'PERF_RB_STARVE_CYCLES_LRZ_TILE', - 7: 'PERF_RB_STARVE_CYCLES_CCU', - 8: 'PERF_RB_STARVE_CYCLES_Z_PLANE', - 9: 'PERF_RB_STARVE_CYCLES_BARY_PLANE', - 10: 'PERF_RB_Z_WORKLOAD', - 11: 'PERF_RB_HLSQ_ACTIVE', - 12: 'PERF_RB_Z_READ', - 13: 'PERF_RB_Z_WRITE', - 14: 'PERF_RB_C_READ', - 15: 'PERF_RB_C_WRITE', - 16: 'PERF_RB_TOTAL_PASS', - 17: 'PERF_RB_Z_PASS', - 18: 'PERF_RB_Z_FAIL', - 19: 'PERF_RB_S_FAIL', - 20: 'PERF_RB_BLENDED_FXP_COMPONENTS', - 21: 'PERF_RB_BLENDED_FP16_COMPONENTS', - 22: 'PERF_RB_PS_INVOCATIONS', - 23: 'PERF_RB_2D_ALIVE_CYCLES', - 24: 'PERF_RB_2D_STALL_CYCLES_A2D', - 25: 'PERF_RB_2D_STARVE_CYCLES_SRC', - 26: 'PERF_RB_2D_STARVE_CYCLES_SP', - 27: 'PERF_RB_2D_STARVE_CYCLES_DST', - 28: 'PERF_RB_2D_VALID_PIXELS', - 29: 'PERF_RB_3D_PIXELS', - 30: 'PERF_RB_BLENDER_WORKING_CYCLES', - 31: 'PERF_RB_ZPROC_WORKING_CYCLES', - 32: 'PERF_RB_CPROC_WORKING_CYCLES', - 33: 'PERF_RB_SAMPLER_WORKING_CYCLES', - 34: 'PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 35: 'PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 36: 'PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 37: 'PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 38: 'PERF_RB_STALL_CYCLES_VPC', - 39: 'PERF_RB_2D_INPUT_TRANS', - 40: 'PERF_RB_2D_OUTPUT_RB_DST_TRANS', - 41: 'PERF_RB_2D_OUTPUT_RB_SRC_TRANS', - 42: 'PERF_RB_BLENDED_FP32_COMPONENTS', - 43: 'PERF_RB_COLOR_PIX_TILES', - 44: 'PERF_RB_STALL_CYCLES_CCU', - 45: 'PERF_RB_EARLY_Z_ARB3_GRANT', - 46: 'PERF_RB_LATE_Z_ARB3_GRANT', - 47: 'PERF_RB_EARLY_Z_SKIP_GRANT', -} -PERF_RB_BUSY_CYCLES = 0 -PERF_RB_STALL_CYCLES_HLSQ = 1 -PERF_RB_STALL_CYCLES_FIFO0_FULL = 2 -PERF_RB_STALL_CYCLES_FIFO1_FULL = 3 -PERF_RB_STALL_CYCLES_FIFO2_FULL = 4 -PERF_RB_STARVE_CYCLES_SP = 5 -PERF_RB_STARVE_CYCLES_LRZ_TILE = 6 -PERF_RB_STARVE_CYCLES_CCU = 7 -PERF_RB_STARVE_CYCLES_Z_PLANE = 8 -PERF_RB_STARVE_CYCLES_BARY_PLANE = 9 -PERF_RB_Z_WORKLOAD = 10 -PERF_RB_HLSQ_ACTIVE = 11 -PERF_RB_Z_READ = 12 -PERF_RB_Z_WRITE = 13 -PERF_RB_C_READ = 14 -PERF_RB_C_WRITE = 15 -PERF_RB_TOTAL_PASS = 16 -PERF_RB_Z_PASS = 17 -PERF_RB_Z_FAIL = 18 -PERF_RB_S_FAIL = 19 -PERF_RB_BLENDED_FXP_COMPONENTS = 20 -PERF_RB_BLENDED_FP16_COMPONENTS = 21 -PERF_RB_PS_INVOCATIONS = 22 -PERF_RB_2D_ALIVE_CYCLES = 23 -PERF_RB_2D_STALL_CYCLES_A2D = 24 -PERF_RB_2D_STARVE_CYCLES_SRC = 25 -PERF_RB_2D_STARVE_CYCLES_SP = 26 -PERF_RB_2D_STARVE_CYCLES_DST = 27 -PERF_RB_2D_VALID_PIXELS = 28 -PERF_RB_3D_PIXELS = 29 -PERF_RB_BLENDER_WORKING_CYCLES = 30 -PERF_RB_ZPROC_WORKING_CYCLES = 31 -PERF_RB_CPROC_WORKING_CYCLES = 32 -PERF_RB_SAMPLER_WORKING_CYCLES = 33 -PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34 -PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35 -PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36 -PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37 -PERF_RB_STALL_CYCLES_VPC = 38 -PERF_RB_2D_INPUT_TRANS = 39 -PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40 -PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41 -PERF_RB_BLENDED_FP32_COMPONENTS = 42 -PERF_RB_COLOR_PIX_TILES = 43 -PERF_RB_STALL_CYCLES_CCU = 44 -PERF_RB_EARLY_Z_ARB3_GRANT = 45 -PERF_RB_LATE_Z_ARB3_GRANT = 46 -PERF_RB_EARLY_Z_SKIP_GRANT = 47 -a6xx_rb_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_vsc_perfcounter_select' -a6xx_vsc_perfcounter_select__enumvalues = { - 0: 'PERF_VSC_BUSY_CYCLES', - 1: 'PERF_VSC_WORKING_CYCLES', - 2: 'PERF_VSC_STALL_CYCLES_UCHE', - 3: 'PERF_VSC_EOT_NUM', - 4: 'PERF_VSC_INPUT_TILES', -} -PERF_VSC_BUSY_CYCLES = 0 -PERF_VSC_WORKING_CYCLES = 1 -PERF_VSC_STALL_CYCLES_UCHE = 2 -PERF_VSC_EOT_NUM = 3 -PERF_VSC_INPUT_TILES = 4 -a6xx_vsc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ccu_perfcounter_select' -a6xx_ccu_perfcounter_select__enumvalues = { - 0: 'PERF_CCU_BUSY_CYCLES', - 1: 'PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 2: 'PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 3: 'PERF_CCU_STARVE_CYCLES_FLAG_RETURN', - 4: 'PERF_CCU_DEPTH_BLOCKS', - 5: 'PERF_CCU_COLOR_BLOCKS', - 6: 'PERF_CCU_DEPTH_BLOCK_HIT', - 7: 'PERF_CCU_COLOR_BLOCK_HIT', - 8: 'PERF_CCU_PARTIAL_BLOCK_READ', - 9: 'PERF_CCU_GMEM_READ', - 10: 'PERF_CCU_GMEM_WRITE', - 11: 'PERF_CCU_DEPTH_READ_FLAG0_COUNT', - 12: 'PERF_CCU_DEPTH_READ_FLAG1_COUNT', - 13: 'PERF_CCU_DEPTH_READ_FLAG2_COUNT', - 14: 'PERF_CCU_DEPTH_READ_FLAG3_COUNT', - 15: 'PERF_CCU_DEPTH_READ_FLAG4_COUNT', - 16: 'PERF_CCU_DEPTH_READ_FLAG5_COUNT', - 17: 'PERF_CCU_DEPTH_READ_FLAG6_COUNT', - 18: 'PERF_CCU_DEPTH_READ_FLAG8_COUNT', - 19: 'PERF_CCU_COLOR_READ_FLAG0_COUNT', - 20: 'PERF_CCU_COLOR_READ_FLAG1_COUNT', - 21: 'PERF_CCU_COLOR_READ_FLAG2_COUNT', - 22: 'PERF_CCU_COLOR_READ_FLAG3_COUNT', - 23: 'PERF_CCU_COLOR_READ_FLAG4_COUNT', - 24: 'PERF_CCU_COLOR_READ_FLAG5_COUNT', - 25: 'PERF_CCU_COLOR_READ_FLAG6_COUNT', - 26: 'PERF_CCU_COLOR_READ_FLAG8_COUNT', - 27: 'PERF_CCU_2D_RD_REQ', - 28: 'PERF_CCU_2D_WR_REQ', -} -PERF_CCU_BUSY_CYCLES = 0 -PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1 -PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2 -PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3 -PERF_CCU_DEPTH_BLOCKS = 4 -PERF_CCU_COLOR_BLOCKS = 5 -PERF_CCU_DEPTH_BLOCK_HIT = 6 -PERF_CCU_COLOR_BLOCK_HIT = 7 -PERF_CCU_PARTIAL_BLOCK_READ = 8 -PERF_CCU_GMEM_READ = 9 -PERF_CCU_GMEM_WRITE = 10 -PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11 -PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12 -PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13 -PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14 -PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15 -PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16 -PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17 -PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18 -PERF_CCU_COLOR_READ_FLAG0_COUNT = 19 -PERF_CCU_COLOR_READ_FLAG1_COUNT = 20 -PERF_CCU_COLOR_READ_FLAG2_COUNT = 21 -PERF_CCU_COLOR_READ_FLAG3_COUNT = 22 -PERF_CCU_COLOR_READ_FLAG4_COUNT = 23 -PERF_CCU_COLOR_READ_FLAG5_COUNT = 24 -PERF_CCU_COLOR_READ_FLAG6_COUNT = 25 -PERF_CCU_COLOR_READ_FLAG8_COUNT = 26 -PERF_CCU_2D_RD_REQ = 27 -PERF_CCU_2D_WR_REQ = 28 -a6xx_ccu_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_lrz_perfcounter_select' -a6xx_lrz_perfcounter_select__enumvalues = { - 0: 'PERF_LRZ_BUSY_CYCLES', - 1: 'PERF_LRZ_STARVE_CYCLES_RAS', - 2: 'PERF_LRZ_STALL_CYCLES_RB', - 3: 'PERF_LRZ_STALL_CYCLES_VSC', - 4: 'PERF_LRZ_STALL_CYCLES_VPC', - 5: 'PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', - 6: 'PERF_LRZ_STALL_CYCLES_UCHE', - 7: 'PERF_LRZ_LRZ_READ', - 8: 'PERF_LRZ_LRZ_WRITE', - 9: 'PERF_LRZ_READ_LATENCY', - 10: 'PERF_LRZ_MERGE_CACHE_UPDATING', - 11: 'PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 12: 'PERF_LRZ_PRIM_KILLED_BY_LRZ', - 13: 'PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', - 14: 'PERF_LRZ_FULL_8X8_TILES', - 15: 'PERF_LRZ_PARTIAL_8X8_TILES', - 16: 'PERF_LRZ_TILE_KILLED', - 17: 'PERF_LRZ_TOTAL_PIXEL', - 18: 'PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 19: 'PERF_LRZ_FULLY_COVERED_TILES', - 20: 'PERF_LRZ_PARTIAL_COVERED_TILES', - 21: 'PERF_LRZ_FEEDBACK_ACCEPT', - 22: 'PERF_LRZ_FEEDBACK_DISCARD', - 23: 'PERF_LRZ_FEEDBACK_STALL', - 24: 'PERF_LRZ_STALL_CYCLES_RB_ZPLANE', - 25: 'PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 26: 'PERF_LRZ_STALL_CYCLES_VC', - 27: 'PERF_LRZ_RAS_MASK_TRANS', -} -PERF_LRZ_BUSY_CYCLES = 0 -PERF_LRZ_STARVE_CYCLES_RAS = 1 -PERF_LRZ_STALL_CYCLES_RB = 2 -PERF_LRZ_STALL_CYCLES_VSC = 3 -PERF_LRZ_STALL_CYCLES_VPC = 4 -PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5 -PERF_LRZ_STALL_CYCLES_UCHE = 6 -PERF_LRZ_LRZ_READ = 7 -PERF_LRZ_LRZ_WRITE = 8 -PERF_LRZ_READ_LATENCY = 9 -PERF_LRZ_MERGE_CACHE_UPDATING = 10 -PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11 -PERF_LRZ_PRIM_KILLED_BY_LRZ = 12 -PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13 -PERF_LRZ_FULL_8X8_TILES = 14 -PERF_LRZ_PARTIAL_8X8_TILES = 15 -PERF_LRZ_TILE_KILLED = 16 -PERF_LRZ_TOTAL_PIXEL = 17 -PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18 -PERF_LRZ_FULLY_COVERED_TILES = 19 -PERF_LRZ_PARTIAL_COVERED_TILES = 20 -PERF_LRZ_FEEDBACK_ACCEPT = 21 -PERF_LRZ_FEEDBACK_DISCARD = 22 -PERF_LRZ_FEEDBACK_STALL = 23 -PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24 -PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25 -PERF_LRZ_STALL_CYCLES_VC = 26 -PERF_LRZ_RAS_MASK_TRANS = 27 -a6xx_lrz_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_cmp_perfcounter_select' -a6xx_cmp_perfcounter_select__enumvalues = { - 0: 'PERF_CMPDECMP_STALL_CYCLES_ARB', - 1: 'PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 2: 'PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 3: 'PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 4: 'PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 5: 'PERF_CMPDECMP_VBIF_READ_REQUEST', - 6: 'PERF_CMPDECMP_VBIF_WRITE_REQUEST', - 7: 'PERF_CMPDECMP_VBIF_READ_DATA', - 8: 'PERF_CMPDECMP_VBIF_WRITE_DATA', - 9: 'PERF_CMPDECMP_FLAG_FETCH_CYCLES', - 10: 'PERF_CMPDECMP_FLAG_FETCH_SAMPLES', - 11: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 12: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 13: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 14: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 15: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 16: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 17: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 18: 'PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 19: 'PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 20: 'PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 21: 'PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 22: 'PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 23: 'PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 24: 'PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 25: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ', - 26: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR', - 27: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN', - 28: 'PERF_CMPDECMP_2D_RD_DATA', - 29: 'PERF_CMPDECMP_2D_WR_DATA', - 30: 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 31: 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 32: 'PERF_CMPDECMP_2D_OUTPUT_TRANS', - 33: 'PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 34: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 35: 'PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 36: 'PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 37: 'PERF_CMPDECMP_2D_BUSY_CYCLES', - 38: 'PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES', - 39: 'PERF_CMPDECMP_2D_PIXELS', -} -PERF_CMPDECMP_STALL_CYCLES_ARB = 0 -PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1 -PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2 -PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3 -PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4 -PERF_CMPDECMP_VBIF_READ_REQUEST = 5 -PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6 -PERF_CMPDECMP_VBIF_READ_DATA = 7 -PERF_CMPDECMP_VBIF_WRITE_DATA = 8 -PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9 -PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10 -PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11 -PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12 -PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13 -PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14 -PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15 -PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16 -PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17 -PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18 -PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19 -PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20 -PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21 -PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22 -PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23 -PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24 -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25 -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26 -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27 -PERF_CMPDECMP_2D_RD_DATA = 28 -PERF_CMPDECMP_2D_WR_DATA = 29 -PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30 -PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31 -PERF_CMPDECMP_2D_OUTPUT_TRANS = 32 -PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33 -PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34 -PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35 -PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36 -PERF_CMPDECMP_2D_BUSY_CYCLES = 37 -PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38 -PERF_CMPDECMP_2D_PIXELS = 39 -a6xx_cmp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_2d_ifmt' -a6xx_2d_ifmt__enumvalues = { - 16: 'R2D_UNORM8', - 7: 'R2D_INT32', - 6: 'R2D_INT16', - 5: 'R2D_INT8', - 4: 'R2D_FLOAT32', - 3: 'R2D_FLOAT16', - 1: 'R2D_UNORM8_SRGB', - 0: 'R2D_RAW', -} -R2D_UNORM8 = 16 -R2D_INT32 = 7 -R2D_INT16 = 6 -R2D_INT8 = 5 -R2D_FLOAT32 = 4 -R2D_FLOAT16 = 3 -R2D_UNORM8_SRGB = 1 -R2D_RAW = 0 -a6xx_2d_ifmt = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ztest_mode' -a6xx_ztest_mode__enumvalues = { - 0: 'A6XX_EARLY_Z', - 1: 'A6XX_LATE_Z', - 2: 'A6XX_EARLY_LRZ_LATE_Z', - 3: 'A6XX_INVALID_ZTEST', -} -A6XX_EARLY_Z = 0 -A6XX_LATE_Z = 1 -A6XX_EARLY_LRZ_LATE_Z = 2 -A6XX_INVALID_ZTEST = 3 -a6xx_ztest_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tess_spacing' -a6xx_tess_spacing__enumvalues = { - 0: 'TESS_EQUAL', - 2: 'TESS_FRACTIONAL_ODD', - 3: 'TESS_FRACTIONAL_EVEN', -} -TESS_EQUAL = 0 -TESS_FRACTIONAL_ODD = 2 -TESS_FRACTIONAL_EVEN = 3 -a6xx_tess_spacing = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tess_output' -a6xx_tess_output__enumvalues = { - 0: 'TESS_POINTS', - 1: 'TESS_LINES', - 2: 'TESS_CW_TRIS', - 3: 'TESS_CCW_TRIS', -} -TESS_POINTS = 0 -TESS_LINES = 1 -TESS_CW_TRIS = 2 -TESS_CCW_TRIS = 3 -a6xx_tess_output = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cp_perfcounter_select' -a7xx_cp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_CP_NEVER_COUNT', - 1: 'A7XX_PERF_CP_ALWAYS_COUNT', - 2: 'A7XX_PERF_CP_BUSY_GFX_CORE_IDLE', - 3: 'A7XX_PERF_CP_BUSY_CYCLES', - 4: 'A7XX_PERF_CP_NUM_PREEMPTIONS', - 5: 'A7XX_PERF_CP_PREEMPTION_REACTION_DELAY', - 6: 'A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 7: 'A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 8: 'A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', - 9: 'A7XX_PERF_CP_PREDICATED_DRAWS_KILLED', - 10: 'A7XX_PERF_CP_MODE_SWITCH', - 11: 'A7XX_PERF_CP_ZPASS_DONE', - 12: 'A7XX_PERF_CP_CONTEXT_DONE', - 13: 'A7XX_PERF_CP_CACHE_FLUSH', - 14: 'A7XX_PERF_CP_LONG_PREEMPTIONS', - 15: 'A7XX_PERF_CP_SQE_I_CACHE_STARVE', - 16: 'A7XX_PERF_CP_SQE_IDLE', - 17: 'A7XX_PERF_CP_SQE_PM4_STARVE_RB', - 18: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB1', - 19: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB2', - 20: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB3', - 21: 'A7XX_PERF_CP_SQE_PM4_STARVE_FSDT', - 22: 'A7XX_PERF_CP_SQE_PM4_STARVE_SDS', - 23: 'A7XX_PERF_CP_SQE_MRB_STARVE', - 24: 'A7XX_PERF_CP_SQE_RRB_STARVE', - 25: 'A7XX_PERF_CP_SQE_VSD_STARVE', - 26: 'A7XX_PERF_CP_VSD_DECODE_STARVE', - 27: 'A7XX_PERF_CP_SQE_PIPE_OUT_STALL', - 28: 'A7XX_PERF_CP_SQE_SYNC_STALL', - 29: 'A7XX_PERF_CP_SQE_PM4_WFI_STALL', - 30: 'A7XX_PERF_CP_SQE_SYS_WFI_STALL', - 31: 'A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', - 32: 'A7XX_PERF_CP_OUTPUT_BLOCKED', - 33: 'A7XX_PERF_CP_SQE_T4_EXEC', - 34: 'A7XX_PERF_CP_SQE_LOAD_STATE_EXEC', - 35: 'A7XX_PERF_CP_SQE_SAVE_SDS_STATE', - 36: 'A7XX_PERF_CP_SQE_DRAW_EXEC', - 37: 'A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', - 38: 'A7XX_PERF_CP_SQE_EXEC_PROFILED', - 39: 'A7XX_PERF_CP_MEMORY_POOL_EMPTY', - 40: 'A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', - 41: 'A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH', - 42: 'A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH', - 43: 'A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS', - 44: 'A7XX_PERF_CP_AHB_STALL_SQE_GMU', - 45: 'A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER', - 46: 'A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER', - 47: 'A7XX_PERF_CP_CLUSTER_FE_U_EMPTY', - 48: 'A7XX_PERF_CP_CLUSTER_FE_S_EMPTY', - 49: 'A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY', - 50: 'A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY', - 51: 'A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY', - 52: 'A7XX_PERF_CP_CLUSTER_GRAS_EMPTY', - 53: 'A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY', - 54: 'A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY', - 55: 'A7XX_PERF_CP_CLUSTER_PS_EMPTY', - 56: 'A7XX_PERF_CP_PM4_DATA', - 57: 'A7XX_PERF_CP_PM4_HEADERS', - 58: 'A7XX_PERF_CP_VBIF_READ_BEATS', - 59: 'A7XX_PERF_CP_VBIF_WRITE_BEATS', - 60: 'A7XX_PERF_CP_SQE_INSTR_COUNTER', - 61: 'A7XX_PERF_CP_CLUSTER_FE_US_FULL', - 62: 'A7XX_PERF_CP_CLUSTER_FE_S_FULL', - 63: 'A7XX_PERF_CP_CLUSTER_SP_VS_FULL', - 64: 'A7XX_PERF_CP_CLUSTER_VPC_US_FULL', - 65: 'A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', - 66: 'A7XX_PERF_CP_CLUSTER_GRAS_FULL', - 67: 'A7XX_PERF_CP_CLUSTER_SP_PS_FULL', - 68: 'A7XX_PERF_CP_CLUSTER_VPC_PS_FULL', - 69: 'A7XX_PERF_CP_CLUSTER_PS_FULL', - 70: 'A7XX_PERF_CP_ICACHE_MISSES', - 71: 'A7XX_PERF_CP_ICACHE_HITS', - 72: 'A7XX_PERF_CP_ICACHE_STALL', - 73: 'A7XX_PERF_CP_DCACHE_MISSES', - 74: 'A7XX_PERF_CP_DCACHE_HITS', - 75: 'A7XX_PERF_CP_DCACHE_STALLS', - 76: 'A7XX_PERF_CP_AQE_SQE_STALL', - 77: 'A7XX_PERF_CP_SQE_AQE_STARVE', - 78: 'A7XX_PERF_CP_ISR_CYCLES', - 79: 'A7XX_PERF_CP_SQE_MD8_STALL_CYCLES', - 80: 'A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES', - 81: 'A7XX_PERF_CP_AQE_NUM_AS_CHUNKS', - 82: 'A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', - 83: 'A7XX_PERF_CP_S_SKEW_BUFFER_FULL', - 84: 'A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH', -} -A7XX_PERF_CP_NEVER_COUNT = 0 -A7XX_PERF_CP_ALWAYS_COUNT = 1 -A7XX_PERF_CP_BUSY_GFX_CORE_IDLE = 2 -A7XX_PERF_CP_BUSY_CYCLES = 3 -A7XX_PERF_CP_NUM_PREEMPTIONS = 4 -A7XX_PERF_CP_PREEMPTION_REACTION_DELAY = 5 -A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 6 -A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME = 7 -A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 8 -A7XX_PERF_CP_PREDICATED_DRAWS_KILLED = 9 -A7XX_PERF_CP_MODE_SWITCH = 10 -A7XX_PERF_CP_ZPASS_DONE = 11 -A7XX_PERF_CP_CONTEXT_DONE = 12 -A7XX_PERF_CP_CACHE_FLUSH = 13 -A7XX_PERF_CP_LONG_PREEMPTIONS = 14 -A7XX_PERF_CP_SQE_I_CACHE_STARVE = 15 -A7XX_PERF_CP_SQE_IDLE = 16 -A7XX_PERF_CP_SQE_PM4_STARVE_RB = 17 -A7XX_PERF_CP_SQE_PM4_STARVE_IB1 = 18 -A7XX_PERF_CP_SQE_PM4_STARVE_IB2 = 19 -A7XX_PERF_CP_SQE_PM4_STARVE_IB3 = 20 -A7XX_PERF_CP_SQE_PM4_STARVE_FSDT = 21 -A7XX_PERF_CP_SQE_PM4_STARVE_SDS = 22 -A7XX_PERF_CP_SQE_MRB_STARVE = 23 -A7XX_PERF_CP_SQE_RRB_STARVE = 24 -A7XX_PERF_CP_SQE_VSD_STARVE = 25 -A7XX_PERF_CP_VSD_DECODE_STARVE = 26 -A7XX_PERF_CP_SQE_PIPE_OUT_STALL = 27 -A7XX_PERF_CP_SQE_SYNC_STALL = 28 -A7XX_PERF_CP_SQE_PM4_WFI_STALL = 29 -A7XX_PERF_CP_SQE_SYS_WFI_STALL = 30 -A7XX_PERF_CP_WAIT_ON_OTHER_PIPE = 31 -A7XX_PERF_CP_OUTPUT_BLOCKED = 32 -A7XX_PERF_CP_SQE_T4_EXEC = 33 -A7XX_PERF_CP_SQE_LOAD_STATE_EXEC = 34 -A7XX_PERF_CP_SQE_SAVE_SDS_STATE = 35 -A7XX_PERF_CP_SQE_DRAW_EXEC = 36 -A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 37 -A7XX_PERF_CP_SQE_EXEC_PROFILED = 38 -A7XX_PERF_CP_MEMORY_POOL_EMPTY = 39 -A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL = 40 -A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH = 41 -A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH = 42 -A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS = 43 -A7XX_PERF_CP_AHB_STALL_SQE_GMU = 44 -A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER = 45 -A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER = 46 -A7XX_PERF_CP_CLUSTER_FE_U_EMPTY = 47 -A7XX_PERF_CP_CLUSTER_FE_S_EMPTY = 48 -A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY = 49 -A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY = 50 -A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY = 51 -A7XX_PERF_CP_CLUSTER_GRAS_EMPTY = 52 -A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY = 53 -A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY = 54 -A7XX_PERF_CP_CLUSTER_PS_EMPTY = 55 -A7XX_PERF_CP_PM4_DATA = 56 -A7XX_PERF_CP_PM4_HEADERS = 57 -A7XX_PERF_CP_VBIF_READ_BEATS = 58 -A7XX_PERF_CP_VBIF_WRITE_BEATS = 59 -A7XX_PERF_CP_SQE_INSTR_COUNTER = 60 -A7XX_PERF_CP_CLUSTER_FE_US_FULL = 61 -A7XX_PERF_CP_CLUSTER_FE_S_FULL = 62 -A7XX_PERF_CP_CLUSTER_SP_VS_FULL = 63 -A7XX_PERF_CP_CLUSTER_VPC_US_FULL = 64 -A7XX_PERF_CP_CLUSTER_VPC_VS_FULL = 65 -A7XX_PERF_CP_CLUSTER_GRAS_FULL = 66 -A7XX_PERF_CP_CLUSTER_SP_PS_FULL = 67 -A7XX_PERF_CP_CLUSTER_VPC_PS_FULL = 68 -A7XX_PERF_CP_CLUSTER_PS_FULL = 69 -A7XX_PERF_CP_ICACHE_MISSES = 70 -A7XX_PERF_CP_ICACHE_HITS = 71 -A7XX_PERF_CP_ICACHE_STALL = 72 -A7XX_PERF_CP_DCACHE_MISSES = 73 -A7XX_PERF_CP_DCACHE_HITS = 74 -A7XX_PERF_CP_DCACHE_STALLS = 75 -A7XX_PERF_CP_AQE_SQE_STALL = 76 -A7XX_PERF_CP_SQE_AQE_STARVE = 77 -A7XX_PERF_CP_ISR_CYCLES = 78 -A7XX_PERF_CP_SQE_MD8_STALL_CYCLES = 79 -A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES = 80 -A7XX_PERF_CP_AQE_NUM_AS_CHUNKS = 81 -A7XX_PERF_CP_AQE_NUM_MS_CHUNKS = 82 -A7XX_PERF_CP_S_SKEW_BUFFER_FULL = 83 -A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH = 84 -a7xx_cp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_rbbm_perfcounter_select' -a7xx_rbbm_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_RBBM_NEVER_COUNT', - 1: 'A7XX_PERF_RBBM_US_ALWAYS_COUNT', - 2: 'A7XX_PERF_RBBM_US_ALWAYS_ON', - 3: 'A7XX_PERF_RBBM_US_STATUS_MASKED', - 4: 'A7XX_PERF_RBBM_US_PC_BUSY', - 5: 'A7XX_PERF_RBBM_US_COM_BUSY', - 6: 'A7XX_PERF_RBBM_US_DCOM_BUSY', - 7: 'A7XX_PERF_RBBM_US_VBIF_BUSY', - 8: 'A7XX_PERF_RBBM_US_VSC_BUSY', - 9: 'A7XX_PERF_RBBM_US_UCHE_BUSY', - 10: 'A7XX_PERF_RBBM_US_HLSQ_BUSY', - 11: 'A7XX_PERF_RBBM_S_HLSQ_BUSY', - 12: 'A7XX_PERF_RBBM_S_PC_BUSY', - 13: 'A7XX_PERF_RBBM_S_TESS_BUSY', - 14: 'A7XX_PERF_RBBM_S_TSEFE_BUSY', - 15: 'A7XX_PERF_RBBM_S_TSEBE_BUSY', - 16: 'A7XX_PERF_RBBM_S_RAS_BUSY', -} -A7XX_PERF_RBBM_NEVER_COUNT = 0 -A7XX_PERF_RBBM_US_ALWAYS_COUNT = 1 -A7XX_PERF_RBBM_US_ALWAYS_ON = 2 -A7XX_PERF_RBBM_US_STATUS_MASKED = 3 -A7XX_PERF_RBBM_US_PC_BUSY = 4 -A7XX_PERF_RBBM_US_COM_BUSY = 5 -A7XX_PERF_RBBM_US_DCOM_BUSY = 6 -A7XX_PERF_RBBM_US_VBIF_BUSY = 7 -A7XX_PERF_RBBM_US_VSC_BUSY = 8 -A7XX_PERF_RBBM_US_UCHE_BUSY = 9 -A7XX_PERF_RBBM_US_HLSQ_BUSY = 10 -A7XX_PERF_RBBM_S_HLSQ_BUSY = 11 -A7XX_PERF_RBBM_S_PC_BUSY = 12 -A7XX_PERF_RBBM_S_TESS_BUSY = 13 -A7XX_PERF_RBBM_S_TSEFE_BUSY = 14 -A7XX_PERF_RBBM_S_TSEBE_BUSY = 15 -A7XX_PERF_RBBM_S_RAS_BUSY = 16 -a7xx_rbbm_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_pc_perfcounter_select' -a7xx_pc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_PC_NEVER_COUNT', - 1: 'A7XX_PERF_PC_US_BUSY_CYCLES', - 2: 'A7XX_PERF_PC_US_WORKING_CYCLES', - 3: 'A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS', - 4: 'A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES', - 5: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX', - 6: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF', - 7: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM', - 8: 'A7XX_PERF_PC_US_STARVE_CYCLES_DI', - 9: 'A7XX_PERF_PC_US_VIS_STREAMS_LOADED', - 10: 'A7XX_PERF_PC_US_INSTANCES', - 11: 'A7XX_PERF_PC_US_DEAD_PRIM', - 12: 'A7XX_PERF_PC_US_SLICE_LIVE_PRIM', - 13: 'A7XX_PERF_PC_US_3D_DRAWCALLS', - 14: 'A7XX_PERF_PC_US_2D_DRAWCALLS', - 15: 'A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS', - 16: 'A7XX_PERF_PC_US_MESH_DRAWS', - 17: 'A7XX_PERF_PC_US_MESH_DEAD_DRAWS', - 18: 'A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS', - 19: 'A7XX_PERF_PC_US_MESH_DEAD_PRIM', - 20: 'A7XX_PERF_PC_US_MESH_LIVE_PRIM', - 21: 'A7XX_PERF_PC_US_MESH_PA_EN_PRIM', - 22: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM', - 23: 'A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW', - 24: 'A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX', - 25: 'A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE', - 26: 'A7XX_PERF_PC_US_PREDRAW_STALLS', - 27: 'A7XX_PERF_PC_US_DP0_INPUT_STALLS', - 28: 'A7XX_PERF_PC_US_DP1_INPUT_STALLS', - 29: 'A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD', - 30: 'A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD', - 31: 'A7XX_PERF_PC_US_PASSPAIR_STALL', - 32: 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE0', - 33: 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE1', - 34: 'A7XX_PERF_PC_US_UCHE_0_TRANS', - 35: 'A7XX_PERF_PC_US_UCHE_1_TRANS', - 36: 'A7XX_PERF_PC_US_BV_STALLED_BY_ATTR', - 37: 'A7XX_PERF_PC_US_BV_STARVED_BY_RARB', - 38: 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR', - 39: 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV', - 40: 'A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK', - 41: 'A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL', - 42: 'A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL', - 43: 'A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL', - 44: 'A7XX_PERF_PC_US_DP0_RARB_FULL', - 45: 'A7XX_PERF_PC_US_DP1_RARB_FULL', - 46: 'A7XX_PERF_PC_US_DP0_LIVE_PRIM', - 47: 'A7XX_PERF_PC_US_DP1_LIVE_PRIM', - 48: 'A7XX_PERF_PC_US_BV2BR_SWITCH', - 49: 'A7XX_PERF_PC_US_BR2BV_SWITCH', - 50: 'A7XX_PERF_PC_US_STALL_CYCLES_PC_S', - 51: 'A7XX_PERF_PC_RESERVED_51', - 52: 'A7XX_PERF_PC_RESERVED_52', - 53: 'A7XX_PERF_PC_RESERVED_53', - 54: 'A7XX_PERF_PC_RESERVED_54', - 55: 'A7XX_PERF_PC_RESERVED_55', - 56: 'A7XX_PERF_PC_RESERVED_56', - 57: 'A7XX_PERF_PC_RESERVED_57', - 58: 'A7XX_PERF_PC_RESERVED_58', - 59: 'A7XX_PERF_PC_RESERVED_59', - 60: 'A7XX_PERF_PC_S_BUSY_CYCLES', - 61: 'A7XX_PERF_PC_S_WORKING_CYCLES', - 62: 'A7XX_PERF_PC_S_STALL_CYCLES_VFD', - 63: 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE', - 64: 'A7XX_PERF_PC_S_STALL_CYCLES_TESS', - 65: 'A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY', - 66: 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY', - 67: 'A7XX_PERF_PC_S_VPC_PRIMITIVES', - 68: 'A7XX_PERF_PC_S_VERTEX_HITS', - 69: 'A7XX_PERF_PC_S_IA_VERTICES', - 70: 'A7XX_PERF_PC_S_IA_PRIMITIVES', - 71: 'A7XX_PERF_PC_S_HS_INVOCATIONS', - 72: 'A7XX_PERF_PC_S_DS_INVOCATIONS', - 73: 'A7XX_PERF_PC_S_VS_INVOCATIONS', - 74: 'A7XX_PERF_PC_S_GS_INVOCATIONS', - 75: 'A7XX_PERF_PC_S_DS_PRIMITIVES', - 76: 'A7XX_PERF_PC_S_TESS_BUSY_CYCLES', - 77: 'A7XX_PERF_PC_S_TESS_WORKING_CYCLES', - 78: 'A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC', - 79: 'A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC', - 80: 'A7XX_PERF_PC_S_TESS_SETUP_ACTIVE', - 81: 'A7XX_PERF_PC_S_TESS_PID_ACTIVE', - 82: 'A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE', - 83: 'A7XX_PERF_PC_S_TESS_FACTOR_TRANS', - 84: 'A7XX_PERF_PC_S_TESS_PC_UV_TRANS', - 85: 'A7XX_PERF_PC_S_TESS_PC_UV_PATCHES', - 86: 'A7XX_PERF_PC_S_MESH_VS_WAVES', -} -A7XX_PERF_PC_NEVER_COUNT = 0 -A7XX_PERF_PC_US_BUSY_CYCLES = 1 -A7XX_PERF_PC_US_WORKING_CYCLES = 2 -A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS = 3 -A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES = 4 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX = 5 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF = 6 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM = 7 -A7XX_PERF_PC_US_STARVE_CYCLES_DI = 8 -A7XX_PERF_PC_US_VIS_STREAMS_LOADED = 9 -A7XX_PERF_PC_US_INSTANCES = 10 -A7XX_PERF_PC_US_DEAD_PRIM = 11 -A7XX_PERF_PC_US_SLICE_LIVE_PRIM = 12 -A7XX_PERF_PC_US_3D_DRAWCALLS = 13 -A7XX_PERF_PC_US_2D_DRAWCALLS = 14 -A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS = 15 -A7XX_PERF_PC_US_MESH_DRAWS = 16 -A7XX_PERF_PC_US_MESH_DEAD_DRAWS = 17 -A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS = 18 -A7XX_PERF_PC_US_MESH_DEAD_PRIM = 19 -A7XX_PERF_PC_US_MESH_LIVE_PRIM = 20 -A7XX_PERF_PC_US_MESH_PA_EN_PRIM = 21 -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM = 22 -A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW = 23 -A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX = 24 -A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE = 25 -A7XX_PERF_PC_US_PREDRAW_STALLS = 26 -A7XX_PERF_PC_US_DP0_INPUT_STALLS = 27 -A7XX_PERF_PC_US_DP1_INPUT_STALLS = 28 -A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD = 29 -A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD = 30 -A7XX_PERF_PC_US_PASSPAIR_STALL = 31 -A7XX_PERF_PC_US_STALL_CYCLES_UCHE0 = 32 -A7XX_PERF_PC_US_STALL_CYCLES_UCHE1 = 33 -A7XX_PERF_PC_US_UCHE_0_TRANS = 34 -A7XX_PERF_PC_US_UCHE_1_TRANS = 35 -A7XX_PERF_PC_US_BV_STALLED_BY_ATTR = 36 -A7XX_PERF_PC_US_BV_STARVED_BY_RARB = 37 -A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR = 38 -A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV = 39 -A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK = 40 -A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL = 41 -A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL = 42 -A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL = 43 -A7XX_PERF_PC_US_DP0_RARB_FULL = 44 -A7XX_PERF_PC_US_DP1_RARB_FULL = 45 -A7XX_PERF_PC_US_DP0_LIVE_PRIM = 46 -A7XX_PERF_PC_US_DP1_LIVE_PRIM = 47 -A7XX_PERF_PC_US_BV2BR_SWITCH = 48 -A7XX_PERF_PC_US_BR2BV_SWITCH = 49 -A7XX_PERF_PC_US_STALL_CYCLES_PC_S = 50 -A7XX_PERF_PC_RESERVED_51 = 51 -A7XX_PERF_PC_RESERVED_52 = 52 -A7XX_PERF_PC_RESERVED_53 = 53 -A7XX_PERF_PC_RESERVED_54 = 54 -A7XX_PERF_PC_RESERVED_55 = 55 -A7XX_PERF_PC_RESERVED_56 = 56 -A7XX_PERF_PC_RESERVED_57 = 57 -A7XX_PERF_PC_RESERVED_58 = 58 -A7XX_PERF_PC_RESERVED_59 = 59 -A7XX_PERF_PC_S_BUSY_CYCLES = 60 -A7XX_PERF_PC_S_WORKING_CYCLES = 61 -A7XX_PERF_PC_S_STALL_CYCLES_VFD = 62 -A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE = 63 -A7XX_PERF_PC_S_STALL_CYCLES_TESS = 64 -A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY = 65 -A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY = 66 -A7XX_PERF_PC_S_VPC_PRIMITIVES = 67 -A7XX_PERF_PC_S_VERTEX_HITS = 68 -A7XX_PERF_PC_S_IA_VERTICES = 69 -A7XX_PERF_PC_S_IA_PRIMITIVES = 70 -A7XX_PERF_PC_S_HS_INVOCATIONS = 71 -A7XX_PERF_PC_S_DS_INVOCATIONS = 72 -A7XX_PERF_PC_S_VS_INVOCATIONS = 73 -A7XX_PERF_PC_S_GS_INVOCATIONS = 74 -A7XX_PERF_PC_S_DS_PRIMITIVES = 75 -A7XX_PERF_PC_S_TESS_BUSY_CYCLES = 76 -A7XX_PERF_PC_S_TESS_WORKING_CYCLES = 77 -A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC = 78 -A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC = 79 -A7XX_PERF_PC_S_TESS_SETUP_ACTIVE = 80 -A7XX_PERF_PC_S_TESS_PID_ACTIVE = 81 -A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE = 82 -A7XX_PERF_PC_S_TESS_FACTOR_TRANS = 83 -A7XX_PERF_PC_S_TESS_PC_UV_TRANS = 84 -A7XX_PERF_PC_S_TESS_PC_UV_PATCHES = 85 -A7XX_PERF_PC_S_MESH_VS_WAVES = 86 -a7xx_pc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_vfd_perfcounter_select' -a7xx_vfd_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_VFD_NEVER_COUNT', - 1: 'A7XX_PERF_VFD_BUSY_CYCLES', - 2: 'A7XX_PERF_VFD_STALL_CYCLES_UCHE', - 3: 'A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 4: 'A7XX_PERF_VFD_STALL_CYCLES_SP_INFO', - 5: 'A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR', - 6: 'A7XX_PERF_VFD_STARVE_CYCLES_UCHE', - 7: 'A7XX_PERF_VFD_RBUFFER_FULL', - 8: 'A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', - 9: 'A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 10: 'A7XX_PERF_VFD_NUM_ATTRIBUTES', - 11: 'A7XX_PERF_VFD_UPPER_SHADER_FIBERS', - 12: 'A7XX_PERF_VFD_LOWER_SHADER_FIBERS', - 13: 'A7XX_PERF_VFD_MODE_0_FIBERS', - 14: 'A7XX_PERF_VFD_MODE_1_FIBERS', - 15: 'A7XX_PERF_VFD_MODE_2_FIBERS', - 16: 'A7XX_PERF_VFD_MODE_3_FIBERS', - 17: 'A7XX_PERF_VFD_MODE_4_FIBERS', - 18: 'A7XX_PERF_VFD_TOTAL_VERTICES', - 19: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD', - 20: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 21: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG', - 22: 'A7XX_PERF_VFDP_STARVE_CYCLES_PC', - 23: 'A7XX_PERF_VFDP_VS_STAGE_WAVES', - 24: 'A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE', - 25: 'A7XX_PERF_VFD_STALL_CYCLES_CBSYNC', -} -A7XX_PERF_VFD_NEVER_COUNT = 0 -A7XX_PERF_VFD_BUSY_CYCLES = 1 -A7XX_PERF_VFD_STALL_CYCLES_UCHE = 2 -A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC = 3 -A7XX_PERF_VFD_STALL_CYCLES_SP_INFO = 4 -A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR = 5 -A7XX_PERF_VFD_STARVE_CYCLES_UCHE = 6 -A7XX_PERF_VFD_RBUFFER_FULL = 7 -A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL = 8 -A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES = 9 -A7XX_PERF_VFD_NUM_ATTRIBUTES = 10 -A7XX_PERF_VFD_UPPER_SHADER_FIBERS = 11 -A7XX_PERF_VFD_LOWER_SHADER_FIBERS = 12 -A7XX_PERF_VFD_MODE_0_FIBERS = 13 -A7XX_PERF_VFD_MODE_1_FIBERS = 14 -A7XX_PERF_VFD_MODE_2_FIBERS = 15 -A7XX_PERF_VFD_MODE_3_FIBERS = 16 -A7XX_PERF_VFD_MODE_4_FIBERS = 17 -A7XX_PERF_VFD_TOTAL_VERTICES = 18 -A7XX_PERF_VFDP_STALL_CYCLES_VFD = 19 -A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX = 20 -A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG = 21 -A7XX_PERF_VFDP_STARVE_CYCLES_PC = 22 -A7XX_PERF_VFDP_VS_STAGE_WAVES = 23 -A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE = 24 -A7XX_PERF_VFD_STALL_CYCLES_CBSYNC = 25 -a7xx_vfd_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_hlsq_perfcounter_select' -a7xx_hlsq_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_HLSQ_NEVER_COUNT', - 1: 'A7XX_PERF_HLSQ_BUSY_CYCLES', - 2: 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE', - 3: 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 4: 'A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES', - 5: 'A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT', - 6: 'A7XX_PERF_HLSQ_STALL_CYCLES_UCHE', - 7: 'A7XX_PERF_HLSQ_RESERVED_7', - 8: 'A7XX_PERF_HLSQ_RESERVED_8', - 9: 'A7XX_PERF_HLSQ_RESERVED_9', - 10: 'A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS', - 11: 'A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 12: 'A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE', - 13: 'A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 14: 'A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 15: 'A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 16: 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD', - 17: 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 18: 'A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE', - 19: 'A7XX_PERF_HLSQ_RESERVED_19', - 20: 'A7XX_PERF_HLSQ_RESERVED_20', - 21: 'A7XX_PERF_HLSQ_VSBR_STALL_CYCLES', - 22: 'A7XX_PERF_HLSQ_FS_STALL_CYCLES', - 23: 'A7XX_PERF_HLSQ_LPAC_STALL_CYCLES', - 24: 'A7XX_PERF_HLSQ_BV_STALL_CYCLES', - 25: 'A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES', - 26: 'A7XX_PERF_HLSQ_FS_DEREF_CYCLES', - 27: 'A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES', - 28: 'A7XX_PERF_HLSQ_BV_DEREF_CYCLES', - 29: 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES', - 30: 'A7XX_PERF_HLSQ_FS_S2W_CYCLES', - 31: 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES', - 32: 'A7XX_PERF_HLSQ_BV_S2W_CYCLES', - 33: 'A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W', - 34: 'A7XX_PERF_HLSQ_FS_WAIT_VS_S2W', - 35: 'A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W', - 36: 'A7XX_PERF_HLSQ_BV_WAIT_FS_S2W', - 37: 'A7XX_PERF_HLSQ_RESERVED_37', - 38: 'A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W', - 39: 'A7XX_PERF_HLSQ_FS_STARVING_SP', - 40: 'A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING', - 41: 'A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING', - 42: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS', - 43: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS', - 44: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS', - 45: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS', - 46: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV', - 47: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV', - 48: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC', - 49: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC', - 50: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS', - 51: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS', - 52: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV', - 53: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC', - 54: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS', - 55: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS', - 56: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV', - 57: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC', - 58: 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP', - 59: 'A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP', - 60: 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP', - 61: 'A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP', - 62: 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ', - 63: 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT', - 64: 'A7XX_PERF_HLSQ_L2STC_REQ_SP', - 65: 'A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT', - 66: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ', - 67: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT', - 68: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP', - 69: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT', - 70: 'A7XX_PERF_HLSQ_L2STC_REQ_UCHE', - 71: 'A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES', - 72: 'A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT', - 73: 'A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ', - 74: 'A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT', - 75: 'A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT', - 76: 'A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT', - 77: 'A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT', - 78: 'A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN', - 79: 'A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W', - 80: 'A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD', - 81: 'A7XX_PERF_HLSQ_STPROC_L0_INS_MISS', - 82: 'A7XX_PERF_HLSQ_STPROC_L0_INS_HIT', - 83: 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT', - 84: 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE', - 85: 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT', - 86: 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE', - 87: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ', - 88: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ', - 89: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING', - 90: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY', - 91: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY', - 92: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL', - 93: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL', - 94: 'A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI', - 95: 'A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI', - 96: 'A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI', - 97: 'A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI', - 98: 'A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI', - 99: 'A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI', - 100: 'A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI', - 101: 'A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI', - 102: 'A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI', - 103: 'A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI', - 104: 'A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI', - 105: 'A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI', - 106: 'A7XX_PERF_HLSQ_PRIMITIVE_COUNT', - 107: 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT', - 108: 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT', - 109: 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC', - 110: 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC', - 111: 'A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC', -} -A7XX_PERF_HLSQ_NEVER_COUNT = 0 -A7XX_PERF_HLSQ_BUSY_CYCLES = 1 -A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE = 2 -A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3 -A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES = 4 -A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT = 5 -A7XX_PERF_HLSQ_STALL_CYCLES_UCHE = 6 -A7XX_PERF_HLSQ_RESERVED_7 = 7 -A7XX_PERF_HLSQ_RESERVED_8 = 8 -A7XX_PERF_HLSQ_RESERVED_9 = 9 -A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS = 10 -A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11 -A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12 -A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13 -A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14 -A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15 -A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16 -A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17 -A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE = 18 -A7XX_PERF_HLSQ_RESERVED_19 = 19 -A7XX_PERF_HLSQ_RESERVED_20 = 20 -A7XX_PERF_HLSQ_VSBR_STALL_CYCLES = 21 -A7XX_PERF_HLSQ_FS_STALL_CYCLES = 22 -A7XX_PERF_HLSQ_LPAC_STALL_CYCLES = 23 -A7XX_PERF_HLSQ_BV_STALL_CYCLES = 24 -A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES = 25 -A7XX_PERF_HLSQ_FS_DEREF_CYCLES = 26 -A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES = 27 -A7XX_PERF_HLSQ_BV_DEREF_CYCLES = 28 -A7XX_PERF_HLSQ_VSBR_S2W_CYCLES = 29 -A7XX_PERF_HLSQ_FS_S2W_CYCLES = 30 -A7XX_PERF_HLSQ_LPAC_S2W_CYCLES = 31 -A7XX_PERF_HLSQ_BV_S2W_CYCLES = 32 -A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W = 33 -A7XX_PERF_HLSQ_FS_WAIT_VS_S2W = 34 -A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W = 35 -A7XX_PERF_HLSQ_BV_WAIT_FS_S2W = 36 -A7XX_PERF_HLSQ_RESERVED_37 = 37 -A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W = 38 -A7XX_PERF_HLSQ_FS_STARVING_SP = 39 -A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING = 40 -A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING = 41 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS = 42 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS = 43 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS = 44 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS = 45 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV = 46 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV = 47 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC = 48 -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC = 49 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS = 50 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS = 51 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV = 52 -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC = 53 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS = 54 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS = 55 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV = 56 -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC = 57 -A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP = 58 -A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP = 59 -A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP = 60 -A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP = 61 -A7XX_PERF_HLSQ_L2STC_REQ_HLSQ = 62 -A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT = 63 -A7XX_PERF_HLSQ_L2STC_REQ_SP = 64 -A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT = 65 -A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ = 66 -A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT = 67 -A7XX_PERF_HLSQ_L2STC_REQ_INS_SP = 68 -A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT = 69 -A7XX_PERF_HLSQ_L2STC_REQ_UCHE = 70 -A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES = 71 -A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT = 72 -A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ = 73 -A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT = 74 -A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT = 75 -A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT = 76 -A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT = 77 -A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN = 78 -A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W = 79 -A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD = 80 -A7XX_PERF_HLSQ_STPROC_L0_INS_MISS = 81 -A7XX_PERF_HLSQ_STPROC_L0_INS_HIT = 82 -A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT = 83 -A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE = 84 -A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT = 85 -A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE = 86 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ = 87 -A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ = 88 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING = 89 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY = 90 -A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY = 91 -A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL = 92 -A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL = 93 -A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI = 94 -A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI = 95 -A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI = 96 -A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI = 97 -A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI = 98 -A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI = 99 -A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI = 100 -A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI = 101 -A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI = 102 -A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI = 103 -A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI = 104 -A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI = 105 -A7XX_PERF_HLSQ_PRIMITIVE_COUNT = 106 -A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT = 107 -A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT = 108 -A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC = 109 -A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC = 110 -A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC = 111 -a7xx_hlsq_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_vpc_perfcounter_select' -a7xx_vpc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_VPC_NEVER_COUNT', - 1: 'A7XX_PERF_VPC_FE_BUSY_CYCLES', - 2: 'A7XX_PERF_VPC_FE_WORKING_CYCLES', - 3: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK', - 4: 'A7XX_PERF_VPC_FE_STARVE_CYCLES_SP', - 5: 'A7XX_PERF_VPC_FE_PC_PRIMITIVES', - 6: 'A7XX_PERF_VPC_FE_SP_COMPONENTS', - 7: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS', - 8: 'A7XX_PERF_VPC_FE_VS_BUSY_CYCLES', - 9: 'A7XX_PERF_VPC_FE_VS_WORKING_CYCLES', - 10: 'A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS', - 11: 'A7XX_PERF_VPC_FE_WIT_FULL_CYCLES', - 12: 'A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES', - 13: 'A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE', - 14: 'A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE', - 15: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US', - 16: 'A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES', - 17: 'A7XX_PERF_VPC_FE_GS_PRIMITIVES', - 18: 'A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS', - 19: 'A7XX_PERF_VPC_FE_STALL_CYCLES_CCU', - 20: 'A7XX_PERF_VPC_FE_NUM_WM_HIT', - 21: 'A7XX_PERF_VPC_FE_STALL_DQ_WACK', - 22: 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE', - 23: 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS', - 24: 'A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES', - 25: 'A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES', - 26: 'A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES', - 27: 'A7XX_PERF_VPC_FE_BOTTLENECK', - 28: 'A7XX_PERF_VPC_US_BUSY_CYCLES', - 29: 'A7XX_PERF_VPC_US_WORKING_CYCLES', - 30: 'A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE', - 31: 'A7XX_PERF_VPC_US_PTUS_FULL', - 32: 'A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT', - 33: 'A7XX_PERF_VPC_US_STALL_CYCLES_VSC', - 34: 'A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE', - 35: 'A7XX_PERF_VPC_US_STALL_CYCLES_UCHE', - 36: 'A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION', - 37: 'A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', - 38: 'A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD', - 39: 'A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS', - 40: 'A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER', - 41: 'A7XX_PERF_VPC_US_BOTTLENECK', - 42: 'A7XX_PERF_VPC_RESERVED_42', - 43: 'A7XX_PERF_VPC_RESERVED_43', - 44: 'A7XX_PERF_VPC_RESERVED_44', - 45: 'A7XX_PERF_VPC_BE_BUSY_CYCLES', - 46: 'A7XX_PERF_VPC_BE_WORKING_CYCLES', - 47: 'A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE', - 48: 'A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES', - 49: 'A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS', - 50: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ', - 51: 'A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES', - 52: 'A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES', - 53: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_RB', - 54: 'A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 55: 'A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM', - 56: 'A7XX_PERF_VPC_BE_NUM_PA_REQ', - 57: 'A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', - 58: 'A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM', - 59: 'A7XX_PERF_VPC_BE_LM_TRANSACTION', - 60: 'A7XX_PERF_VPC_BE_PS_BUSY_CYCLES', - 61: 'A7XX_PERF_VPC_BE_PS_WORKING_CYCLES', - 62: 'A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE', - 63: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE', - 64: 'A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END', - 65: 'A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL', - 66: 'A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ', - 67: 'A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK', - 68: 'A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS', - 69: 'A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR', - 70: 'A7XX_PERF_VPC_BE_BOTTLENECK', -} -A7XX_PERF_VPC_NEVER_COUNT = 0 -A7XX_PERF_VPC_FE_BUSY_CYCLES = 1 -A7XX_PERF_VPC_FE_WORKING_CYCLES = 2 -A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK = 3 -A7XX_PERF_VPC_FE_STARVE_CYCLES_SP = 4 -A7XX_PERF_VPC_FE_PC_PRIMITIVES = 5 -A7XX_PERF_VPC_FE_SP_COMPONENTS = 6 -A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS = 7 -A7XX_PERF_VPC_FE_VS_BUSY_CYCLES = 8 -A7XX_PERF_VPC_FE_VS_WORKING_CYCLES = 9 -A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS = 10 -A7XX_PERF_VPC_FE_WIT_FULL_CYCLES = 11 -A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES = 12 -A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE = 13 -A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE = 14 -A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US = 15 -A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES = 16 -A7XX_PERF_VPC_FE_GS_PRIMITIVES = 17 -A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS = 18 -A7XX_PERF_VPC_FE_STALL_CYCLES_CCU = 19 -A7XX_PERF_VPC_FE_NUM_WM_HIT = 20 -A7XX_PERF_VPC_FE_STALL_DQ_WACK = 21 -A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE = 22 -A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS = 23 -A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES = 24 -A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES = 25 -A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES = 26 -A7XX_PERF_VPC_FE_BOTTLENECK = 27 -A7XX_PERF_VPC_US_BUSY_CYCLES = 28 -A7XX_PERF_VPC_US_WORKING_CYCLES = 29 -A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE = 30 -A7XX_PERF_VPC_US_PTUS_FULL = 31 -A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT = 32 -A7XX_PERF_VPC_US_STALL_CYCLES_VSC = 33 -A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE = 34 -A7XX_PERF_VPC_US_STALL_CYCLES_UCHE = 35 -A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION = 36 -A7XX_PERF_VPC_US_NUM_GMEM_READ_SO = 37 -A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD = 38 -A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS = 39 -A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER = 40 -A7XX_PERF_VPC_US_BOTTLENECK = 41 -A7XX_PERF_VPC_RESERVED_42 = 42 -A7XX_PERF_VPC_RESERVED_43 = 43 -A7XX_PERF_VPC_RESERVED_44 = 44 -A7XX_PERF_VPC_BE_BUSY_CYCLES = 45 -A7XX_PERF_VPC_BE_WORKING_CYCLES = 46 -A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE = 47 -A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES = 48 -A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS = 49 -A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ = 50 -A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES = 51 -A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES = 52 -A7XX_PERF_VPC_BE_STARVE_CYCLES_RB = 53 -A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC = 54 -A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM = 55 -A7XX_PERF_VPC_BE_NUM_PA_REQ = 56 -A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT = 57 -A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM = 58 -A7XX_PERF_VPC_BE_LM_TRANSACTION = 59 -A7XX_PERF_VPC_BE_PS_BUSY_CYCLES = 60 -A7XX_PERF_VPC_BE_PS_WORKING_CYCLES = 61 -A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE = 62 -A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE = 63 -A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END = 64 -A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL = 65 -A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ = 66 -A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK = 67 -A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS = 68 -A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR = 69 -A7XX_PERF_VPC_BE_BOTTLENECK = 70 -a7xx_vpc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_tse_perfcounter_select' -a7xx_tse_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_TSE_NEVER_COUNT', - 1: 'A7XX_PERF_TSE_BE_BUSY_CYCLES', - 2: 'A7XX_PERF_TSE_BE_CLIPPING_CYCLES', - 3: 'A7XX_PERF_TSE_BE_STALL_CYCLES_RAS', - 4: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE', - 5: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE', - 6: 'A7XX_PERF_TSE_BE_STARVE_CYCLES_PC', - 7: 'A7XX_PERF_TSE_BE_INPUT_PRIM', - 8: 'A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', - 9: 'A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM', - 10: 'A7XX_PERF_TSE_BE_CLIPPED_PRIM', - 11: 'A7XX_PERF_TSE_BE_ZERO_AREA_PRIM', - 12: 'A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM', - 13: 'A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM', - 14: 'A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM', - 15: 'A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM', - 16: 'A7XX_PERF_TSE_BE_CINVOCATION', - 17: 'A7XX_PERF_TSE_BE_CPRIMITIVES', - 18: 'A7XX_PERF_TSE_BE_2D_INPUT_PRIM', - 19: 'A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES', - 20: 'A7XX_PERF_TSE_BE_CLIP_PLANES', - 21: 'A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM', - 22: 'A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS', - 23: 'A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 24: 'A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 25: 'A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM', - 26: 'A7XX_PERF_TSE_BE_VP_OUT_IS_NAN', - 27: 'A7XX_PERF_TSE_BE_EXCLUDED_PRIM', - 28: 'A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM', - 29: 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP', - 30: 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY', - 31: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP', - 32: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY', - 33: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR', - 34: 'A7XX_PERF_TSE_FE_BUSY_CYCLES', - 35: 'A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US', - 36: 'A7XX_PERF_TSE_FE_STARVE_CYCLES_PC', - 37: 'A7XX_PERF_TSE_FE_INPUT_PRIM', - 38: 'A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', - 39: 'A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM', - 40: 'A7XX_PERF_TSE_FE_ZERO_AREA_PRIM', - 41: 'A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM', - 42: 'A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', - 43: 'A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM', - 44: 'A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM', - 45: 'A7XX_PERF_TSE_FE_CINVOCATION', - 46: 'A7XX_PERF_TSE_FE_CPRIMITIVES', - 47: 'A7XX_PERF_TSE_FE_CLIP_PLANES', - 48: 'A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM', - 49: 'A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS', - 50: 'A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 51: 'A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 52: 'A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM', - 53: 'A7XX_PERF_TSE_FE_VP_OUT_IS_NAN', - 54: 'A7XX_PERF_TSE_FE_EXCLUDED_PRIM', - 55: 'A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM', - 56: 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP', - 57: 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY', - 58: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP', - 59: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY', - 60: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR', - 61: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM', -} -A7XX_PERF_TSE_NEVER_COUNT = 0 -A7XX_PERF_TSE_BE_BUSY_CYCLES = 1 -A7XX_PERF_TSE_BE_CLIPPING_CYCLES = 2 -A7XX_PERF_TSE_BE_STALL_CYCLES_RAS = 3 -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE = 4 -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE = 5 -A7XX_PERF_TSE_BE_STARVE_CYCLES_PC = 6 -A7XX_PERF_TSE_BE_INPUT_PRIM = 7 -A7XX_PERF_TSE_BE_INPUT_NULL_PRIM = 8 -A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM = 9 -A7XX_PERF_TSE_BE_CLIPPED_PRIM = 10 -A7XX_PERF_TSE_BE_ZERO_AREA_PRIM = 11 -A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM = 12 -A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM = 13 -A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM = 14 -A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM = 15 -A7XX_PERF_TSE_BE_CINVOCATION = 16 -A7XX_PERF_TSE_BE_CPRIMITIVES = 17 -A7XX_PERF_TSE_BE_2D_INPUT_PRIM = 18 -A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES = 19 -A7XX_PERF_TSE_BE_CLIP_PLANES = 20 -A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM = 21 -A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS = 22 -A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 23 -A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 24 -A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM = 25 -A7XX_PERF_TSE_BE_VP_OUT_IS_NAN = 26 -A7XX_PERF_TSE_BE_EXCLUDED_PRIM = 27 -A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM = 28 -A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP = 29 -A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY = 30 -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP = 31 -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY = 32 -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR = 33 -A7XX_PERF_TSE_FE_BUSY_CYCLES = 34 -A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US = 35 -A7XX_PERF_TSE_FE_STARVE_CYCLES_PC = 36 -A7XX_PERF_TSE_FE_INPUT_PRIM = 37 -A7XX_PERF_TSE_FE_INPUT_NULL_PRIM = 38 -A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM = 39 -A7XX_PERF_TSE_FE_ZERO_AREA_PRIM = 40 -A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM = 41 -A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM = 42 -A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM = 43 -A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM = 44 -A7XX_PERF_TSE_FE_CINVOCATION = 45 -A7XX_PERF_TSE_FE_CPRIMITIVES = 46 -A7XX_PERF_TSE_FE_CLIP_PLANES = 47 -A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM = 48 -A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS = 49 -A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 50 -A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 51 -A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM = 52 -A7XX_PERF_TSE_FE_VP_OUT_IS_NAN = 53 -A7XX_PERF_TSE_FE_EXCLUDED_PRIM = 54 -A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM = 55 -A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP = 56 -A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY = 57 -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP = 58 -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY = 59 -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR = 60 -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM = 61 -a7xx_tse_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_ras_perfcounter_select' -a7xx_ras_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_RAS_NEVER_COUNT', - 1: 'A7XX_PERF_RAS_BUSY_CYCLES', - 2: 'A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 3: 'A7XX_PERF_RAS_STALL_CYCLES_LRZ', - 4: 'A7XX_PERF_RAS_STARVE_CYCLES_TSE', - 5: 'A7XX_PERF_RAS_SUPER_TILES', - 6: 'A7XX_PERF_RAS_8X4_TILES', - 7: 'A7XX_PERF_RAS_MASKGEN_ACTIVE', - 8: 'A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES', - 9: 'A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES', - 10: 'A7XX_PERF_RAS_PRIM_KILLED_INVISILBE', - 11: 'A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', - 12: 'A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES', - 13: 'A7XX_PERF_RAS_BLOCKS', - 14: 'A7XX_PERF_RAS_FALSE_PARTIAL_STILE', - 15: 'A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY', - 16: 'A7XX_PERF_RAS_SLICE_BLOCK_EMPTY', - 17: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2', - 18: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2', - 19: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2', - 20: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2', - 21: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2', - 22: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2', - 23: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2', - 24: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2', - 25: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2', - 26: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2', - 27: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2', - 28: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2', - 29: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2', - 30: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2', - 31: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2', - 32: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2', -} -A7XX_PERF_RAS_NEVER_COUNT = 0 -A7XX_PERF_RAS_BUSY_CYCLES = 1 -A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 2 -A7XX_PERF_RAS_STALL_CYCLES_LRZ = 3 -A7XX_PERF_RAS_STARVE_CYCLES_TSE = 4 -A7XX_PERF_RAS_SUPER_TILES = 5 -A7XX_PERF_RAS_8X4_TILES = 6 -A7XX_PERF_RAS_MASKGEN_ACTIVE = 7 -A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES = 8 -A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES = 9 -A7XX_PERF_RAS_PRIM_KILLED_INVISILBE = 10 -A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 11 -A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES = 12 -A7XX_PERF_RAS_BLOCKS = 13 -A7XX_PERF_RAS_FALSE_PARTIAL_STILE = 14 -A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY = 15 -A7XX_PERF_RAS_SLICE_BLOCK_EMPTY = 16 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2 = 17 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2 = 18 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2 = 19 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2 = 20 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2 = 21 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2 = 22 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2 = 23 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2 = 24 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2 = 25 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2 = 26 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2 = 27 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2 = 28 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2 = 29 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2 = 30 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2 = 31 -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2 = 32 -a7xx_ras_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_uche_perfcounter_select' -a7xx_uche_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_UCHE_NEVER_COUNT', - 1: 'A7XX_PERF_UCHE_BUSY_CYCLES', - 2: 'A7XX_PERF_UCHE_STALL_CYCLES_ARBITER', - 3: 'A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA', - 4: 'A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP', - 5: 'A7XX_PERF_UCHE_STALL_CYCLES_DECMP', - 6: 'A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF', - 7: 'A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES', - 8: 'A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES', - 9: 'A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', - 10: 'A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES', - 11: 'A7XX_PERF_UCHE_READ_REQUESTS_SP', - 12: 'A7XX_PERF_UCHE_READ_REQUESTS_TP', - 13: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC', - 14: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF', - 15: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM', - 16: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD', - 17: 'A7XX_PERF_UCHE_READ_REQUESTS_VPC', - 18: 'A7XX_PERF_UCHE_READ_REQUESTS_HLSQ', - 19: 'A7XX_PERF_UCHE_READ_REQUESTS_LRZ', - 20: 'A7XX_PERF_UCHE_READ_REQUESTS_PC', - 21: 'A7XX_PERF_UCHE_WRITE_REQUESTS_SP', - 22: 'A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ', - 23: 'A7XX_PERF_UCHE_WRITE_REQUESTS_VPC', - 24: 'A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', - 25: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_SP', - 26: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_TP', - 27: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD', - 28: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC', - 29: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 30: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ', - 31: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_PC', - 32: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0', - 33: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1', - 34: 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0', - 35: 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1', - 36: 'A7XX_PERF_UCHE_GMEM_READ_BEATS', - 37: 'A7XX_PERF_UCHE_GMEM_WRITE_BEATS', - 38: 'A7XX_PERF_UCHE_UBWC_READ_BEATS', - 39: 'A7XX_PERF_UCHE_UBWC_WRITE_BEATS', - 40: 'A7XX_PERF_UCHE_EVICTS', - 41: 'A7XX_PERF_UCHE_BANK_REQ0', - 42: 'A7XX_PERF_UCHE_BANK_REQ1', - 43: 'A7XX_PERF_UCHE_BANK_REQ2', - 44: 'A7XX_PERF_UCHE_BANK_REQ3', - 45: 'A7XX_PERF_UCHE_BANK_REQ4', - 46: 'A7XX_PERF_UCHE_BANK_REQ5', - 47: 'A7XX_PERF_UCHE_BANK_REQ6', - 48: 'A7XX_PERF_UCHE_BANK_REQ7', - 49: 'A7XX_PERF_UCHE_TPH_REF_FULL', - 50: 'A7XX_PERF_UCHE_TPH_VICTIM_FULL', - 51: 'A7XX_PERF_UCHE_TPH_EXT_FULL', - 52: 'A7XX_PERF_UCHE_RAM_READ_REQ', - 53: 'A7XX_PERF_UCHE_RAM_WRITE_REQ', - 54: 'A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS', - 55: 'A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS', - 56: 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE', - 57: 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER', - 58: 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE', - 59: 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS', - 60: 'A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL', - 61: 'A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL', - 62: 'A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL', - 63: 'A7XX_PERF_UCHE_EVICTS_SP', - 64: 'A7XX_PERF_UCHE_EVICTS_LRZ', - 65: 'A7XX_PERF_UCHE_READ_REQUESTS_VPCUS', - 66: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV', - 67: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR', - 68: 'A7XX_PERF_BYPC_FULL', - 69: 'A7XX_PERF_BYPC_FULL_CCHE_STALL', - 70: 'A7XX_PERF_BYPC_VHUB_STALL', - 71: 'A7XX_PERF_BYPD_FULL', - 72: 'A7XX_PERF_BYPD_FULL_GBIF_STALL', - 73: 'A7XX_PERF_VHUB_PTABLE_FULL', - 74: 'A7XX_PERF_DHUB_PTABLE_FULL', - 75: 'A7XX_PERF_UCHE_RESERVED_75', - 76: 'A7XX_PERF_UCHE_RESERVED_76', - 77: 'A7XX_PERF_UCHE_RESERVED_77', - 78: 'A7XX_PERF_UCHE_RESERVED_78', - 79: 'A7XX_PERF_UCHE_RESERVED_79', - 80: 'A7XX_PERF_UCHE_RESERVED_80', - 81: 'A7XX_PERF_UCHE_RESERVED_81', - 82: 'A7XX_PERF_UCHE_RESERVED_82', - 83: 'A7XX_PERF_UCHE_RESERVED_83', - 84: 'A7XX_PERF_UCHE_RESERVED_84', - 85: 'A7XX_PERF_UCHE_RESERVED_85', - 86: 'A7XX_PERF_UCHE_RESERVED_86', - 87: 'A7XX_PERF_UCHE_RESERVED_87', - 88: 'A7XX_PERF_UCHE_RESERVED_88', - 89: 'A7XX_PERF_UCHE_RESERVED_89', - 90: 'A7XX_PERF_UCHE_RESERVED_90', - 91: 'A7XX_PERF_UCHE_RESERVED_91', - 92: 'A7XX_PERF_UCHE_RESERVED_92', - 93: 'A7XX_PERF_UCHE_RESERVED_93', - 94: 'A7XX_PERF_UCHE_RESERVED_94', - 95: 'A7XX_PERF_UCHE_RESERVED_95', - 96: 'A7XX_PERF_UCHE_RESERVED_96', - 97: 'A7XX_PERF_UCHE_RESERVED_97', - 98: 'A7XX_PERF_UCHE_RESERVED_98', - 99: 'A7XX_PERF_UCHE_RESERVED_99', - 100: 'A7XX_PERF_UCHE_RESERVED_100', - 101: 'A7XX_PERF_UCHE_RESERVED_101', - 102: 'A7XX_PERF_UCHE_RESERVED_102', - 103: 'A7XX_PERF_UCHE_RESERVED_103', - 104: 'A7XX_PERF_UCHE_RESERVED_104', - 105: 'A7XX_PERF_UCHE_RESERVED_105', - 106: 'A7XX_PERF_UCHE_RESERVED_106', - 107: 'A7XX_PERF_UCHE_RESERVED_107', - 108: 'A7XX_PERF_UCHE_RESERVED_108', - 109: 'A7XX_PERF_UCHE_RESERVED_109', - 110: 'A7XX_PERF_UCHE_RESERVED_110', - 111: 'A7XX_PERF_UCHE_RESERVED_111', - 112: 'A7XX_PERF_UCHE_RESERVED_112', - 113: 'A7XX_PERF_UCHE_RESERVED_113', - 114: 'A7XX_PERF_UCHE_RESERVED_114', - 115: 'A7XX_PERF_UCHE_RESERVED_115', - 116: 'A7XX_PERF_UCHE_RESERVED_116', - 117: 'A7XX_PERF_UCHE_RESERVED_117', - 118: 'A7XX_PERF_UCHE_RESERVED_118', - 119: 'A7XX_PERF_UCHE_RESERVED_119', - 120: 'A7XX_PERF_UCHE_RESERVED_120', - 121: 'A7XX_PERF_UCHE_RESERVED_121', - 122: 'A7XX_PERF_UCHE_RESERVED_122', - 123: 'A7XX_PERF_UCHE_RESERVED_123', - 124: 'A7XX_PERF_UCHE_RESERVED_124', - 125: 'A7XX_PERF_UCHE_RESERVED_125', - 126: 'A7XX_PERF_UCHE_RESERVED_126', - 127: 'A7XX_PERF_UCHE_RESERVED_127', - 128: 'A7XX_PERF_CCHE_BUSY_CYCLES', - 129: 'A7XX_PERF_CCHE_STALL_CYCLES_UCHE', - 130: 'A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA', - 131: 'A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES', - 132: 'A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES', - 133: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL', - 134: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC', - 135: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF', - 136: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM', - 137: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL', - 138: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC', - 139: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF', - 140: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM', - 141: 'A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL', - 142: 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM', - 143: 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF', - 144: 'A7XX_PERF_CCHE_READ_REQUESTS_LRZ', - 145: 'A7XX_PERF_CCHE_READ_REQUESTS_VPC', - 146: 'A7XX_PERF_CCHE_WRITE_REQUESTS_SP', - 147: 'A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ', - 148: 'A7XX_PERF_CCHE_READ_REQUESTS_GMEM', - 149: 'A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM', - 150: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_TP', - 151: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD', - 152: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_SP', - 153: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC', - 154: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ', - 155: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0', - 156: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1', - 157: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC', - 158: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_TP', - 159: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_SP', - 160: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD', - 161: 'A7XX_PERF_CCHE_BANK_REQ0', - 162: 'A7XX_PERF_CCHE_BANK_REQ1', - 163: 'A7XX_PERF_CCHE_BANK_REQ2', - 164: 'A7XX_PERF_CCHE_BANK_REQ3', - 165: 'A7XX_PERF_CCHE_BANK_REQ4', - 166: 'A7XX_PERF_CCHE_BANK_REQ5', - 167: 'A7XX_PERF_CCHE_BANK_REQ6', - 168: 'A7XX_PERF_CCHE_BANK_REQ7', - 169: 'A7XX_PERF_CCHE_BANK_REQ8', - 170: 'A7XX_PERF_CCHE_BANK_REQ9', - 171: 'A7XX_PERF_CCHE_BANK_REQ10', - 172: 'A7XX_PERF_CCHE_BANK_REQ11', - 173: 'A7XX_PERF_CCHE_BANK_REQ12', - 174: 'A7XX_PERF_CCHE_BANK_REQ13', - 175: 'A7XX_PERF_CCHE_BANK_REQ14', - 176: 'A7XX_PERF_CCHE_BANK_REQ15', - 177: 'A7XX_PERF_CCHE_GBANK_REQ0', - 178: 'A7XX_PERF_CCHE_GBANK_REQ1', - 179: 'A7XX_PERF_CCHE_GBANK_REQ2', - 180: 'A7XX_PERF_CCHE_GBANK_REQ3', - 181: 'A7XX_PERF_CCHE_TPH_REF_FULL', - 182: 'A7XX_PERF_CCHE_TPH_VICTIM_FULL', - 183: 'A7XX_PERF_CCHE_TPH_EXT_FULL', - 184: 'A7XX_PERF_CCHE_RAM_READ_REQ', - 185: 'A7XX_PERF_CCHE_RAM_WRITE_REQ', - 186: 'A7XX_PERF_CCHE_TPH_CONFLICT_CL', - 187: 'A7XX_PERF_CCHE_DBANK_CONFLICT', - 188: 'A7XX_PERF_CCHE_TPH_QUEUE_FULL', - 189: 'A7XX_PERF_CCHE_DPH_QUEUE_FULL', - 190: 'A7XX_PERF_CCHE_OPH_QUEUE_FULL', - 191: 'A7XX_PERF_CCHE_WACK_QUEUE_FULL', - 192: 'A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST', - 193: 'A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST', - 194: 'A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST', - 195: 'A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST', - 196: 'A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST', - 197: 'A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST', - 198: 'A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST', - 199: 'A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST', - 200: 'A7XX_PERF_CCHE_STALL_CYCLES_TP', -} -A7XX_PERF_UCHE_NEVER_COUNT = 0 -A7XX_PERF_UCHE_BUSY_CYCLES = 1 -A7XX_PERF_UCHE_STALL_CYCLES_ARBITER = 2 -A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA = 3 -A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP = 4 -A7XX_PERF_UCHE_STALL_CYCLES_DECMP = 5 -A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF = 6 -A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES = 7 -A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES = 8 -A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES = 9 -A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES = 10 -A7XX_PERF_UCHE_READ_REQUESTS_SP = 11 -A7XX_PERF_UCHE_READ_REQUESTS_TP = 12 -A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC = 13 -A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF = 14 -A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM = 15 -A7XX_PERF_UCHE_READ_REQUESTS_VFD = 16 -A7XX_PERF_UCHE_READ_REQUESTS_VPC = 17 -A7XX_PERF_UCHE_READ_REQUESTS_HLSQ = 18 -A7XX_PERF_UCHE_READ_REQUESTS_LRZ = 19 -A7XX_PERF_UCHE_READ_REQUESTS_PC = 20 -A7XX_PERF_UCHE_WRITE_REQUESTS_SP = 21 -A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ = 22 -A7XX_PERF_UCHE_WRITE_REQUESTS_VPC = 23 -A7XX_PERF_UCHE_WRITE_REQUESTS_VSC = 24 -A7XX_PERF_UCHE_VBIF_READ_BEATS_SP = 25 -A7XX_PERF_UCHE_VBIF_READ_BEATS_TP = 26 -A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD = 27 -A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC = 28 -A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ = 29 -A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ = 30 -A7XX_PERF_UCHE_VBIF_READ_BEATS_PC = 31 -A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0 = 32 -A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1 = 33 -A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0 = 34 -A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1 = 35 -A7XX_PERF_UCHE_GMEM_READ_BEATS = 36 -A7XX_PERF_UCHE_GMEM_WRITE_BEATS = 37 -A7XX_PERF_UCHE_UBWC_READ_BEATS = 38 -A7XX_PERF_UCHE_UBWC_WRITE_BEATS = 39 -A7XX_PERF_UCHE_EVICTS = 40 -A7XX_PERF_UCHE_BANK_REQ0 = 41 -A7XX_PERF_UCHE_BANK_REQ1 = 42 -A7XX_PERF_UCHE_BANK_REQ2 = 43 -A7XX_PERF_UCHE_BANK_REQ3 = 44 -A7XX_PERF_UCHE_BANK_REQ4 = 45 -A7XX_PERF_UCHE_BANK_REQ5 = 46 -A7XX_PERF_UCHE_BANK_REQ6 = 47 -A7XX_PERF_UCHE_BANK_REQ7 = 48 -A7XX_PERF_UCHE_TPH_REF_FULL = 49 -A7XX_PERF_UCHE_TPH_VICTIM_FULL = 50 -A7XX_PERF_UCHE_TPH_EXT_FULL = 51 -A7XX_PERF_UCHE_RAM_READ_REQ = 52 -A7XX_PERF_UCHE_RAM_WRITE_REQ = 53 -A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS = 54 -A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS = 55 -A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE = 56 -A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER = 57 -A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE = 58 -A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS = 59 -A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL = 60 -A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL = 61 -A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL = 62 -A7XX_PERF_UCHE_EVICTS_SP = 63 -A7XX_PERF_UCHE_EVICTS_LRZ = 64 -A7XX_PERF_UCHE_READ_REQUESTS_VPCUS = 65 -A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV = 66 -A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR = 67 -A7XX_PERF_BYPC_FULL = 68 -A7XX_PERF_BYPC_FULL_CCHE_STALL = 69 -A7XX_PERF_BYPC_VHUB_STALL = 70 -A7XX_PERF_BYPD_FULL = 71 -A7XX_PERF_BYPD_FULL_GBIF_STALL = 72 -A7XX_PERF_VHUB_PTABLE_FULL = 73 -A7XX_PERF_DHUB_PTABLE_FULL = 74 -A7XX_PERF_UCHE_RESERVED_75 = 75 -A7XX_PERF_UCHE_RESERVED_76 = 76 -A7XX_PERF_UCHE_RESERVED_77 = 77 -A7XX_PERF_UCHE_RESERVED_78 = 78 -A7XX_PERF_UCHE_RESERVED_79 = 79 -A7XX_PERF_UCHE_RESERVED_80 = 80 -A7XX_PERF_UCHE_RESERVED_81 = 81 -A7XX_PERF_UCHE_RESERVED_82 = 82 -A7XX_PERF_UCHE_RESERVED_83 = 83 -A7XX_PERF_UCHE_RESERVED_84 = 84 -A7XX_PERF_UCHE_RESERVED_85 = 85 -A7XX_PERF_UCHE_RESERVED_86 = 86 -A7XX_PERF_UCHE_RESERVED_87 = 87 -A7XX_PERF_UCHE_RESERVED_88 = 88 -A7XX_PERF_UCHE_RESERVED_89 = 89 -A7XX_PERF_UCHE_RESERVED_90 = 90 -A7XX_PERF_UCHE_RESERVED_91 = 91 -A7XX_PERF_UCHE_RESERVED_92 = 92 -A7XX_PERF_UCHE_RESERVED_93 = 93 -A7XX_PERF_UCHE_RESERVED_94 = 94 -A7XX_PERF_UCHE_RESERVED_95 = 95 -A7XX_PERF_UCHE_RESERVED_96 = 96 -A7XX_PERF_UCHE_RESERVED_97 = 97 -A7XX_PERF_UCHE_RESERVED_98 = 98 -A7XX_PERF_UCHE_RESERVED_99 = 99 -A7XX_PERF_UCHE_RESERVED_100 = 100 -A7XX_PERF_UCHE_RESERVED_101 = 101 -A7XX_PERF_UCHE_RESERVED_102 = 102 -A7XX_PERF_UCHE_RESERVED_103 = 103 -A7XX_PERF_UCHE_RESERVED_104 = 104 -A7XX_PERF_UCHE_RESERVED_105 = 105 -A7XX_PERF_UCHE_RESERVED_106 = 106 -A7XX_PERF_UCHE_RESERVED_107 = 107 -A7XX_PERF_UCHE_RESERVED_108 = 108 -A7XX_PERF_UCHE_RESERVED_109 = 109 -A7XX_PERF_UCHE_RESERVED_110 = 110 -A7XX_PERF_UCHE_RESERVED_111 = 111 -A7XX_PERF_UCHE_RESERVED_112 = 112 -A7XX_PERF_UCHE_RESERVED_113 = 113 -A7XX_PERF_UCHE_RESERVED_114 = 114 -A7XX_PERF_UCHE_RESERVED_115 = 115 -A7XX_PERF_UCHE_RESERVED_116 = 116 -A7XX_PERF_UCHE_RESERVED_117 = 117 -A7XX_PERF_UCHE_RESERVED_118 = 118 -A7XX_PERF_UCHE_RESERVED_119 = 119 -A7XX_PERF_UCHE_RESERVED_120 = 120 -A7XX_PERF_UCHE_RESERVED_121 = 121 -A7XX_PERF_UCHE_RESERVED_122 = 122 -A7XX_PERF_UCHE_RESERVED_123 = 123 -A7XX_PERF_UCHE_RESERVED_124 = 124 -A7XX_PERF_UCHE_RESERVED_125 = 125 -A7XX_PERF_UCHE_RESERVED_126 = 126 -A7XX_PERF_UCHE_RESERVED_127 = 127 -A7XX_PERF_CCHE_BUSY_CYCLES = 128 -A7XX_PERF_CCHE_STALL_CYCLES_UCHE = 129 -A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA = 130 -A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES = 131 -A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES = 132 -A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL = 133 -A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC = 134 -A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF = 135 -A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM = 136 -A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL = 137 -A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC = 138 -A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF = 139 -A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM = 140 -A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL = 141 -A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM = 142 -A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF = 143 -A7XX_PERF_CCHE_READ_REQUESTS_LRZ = 144 -A7XX_PERF_CCHE_READ_REQUESTS_VPC = 145 -A7XX_PERF_CCHE_WRITE_REQUESTS_SP = 146 -A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ = 147 -A7XX_PERF_CCHE_READ_REQUESTS_GMEM = 148 -A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM = 149 -A7XX_PERF_CCHE_UCHE_READ_BEATS_TP = 150 -A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD = 151 -A7XX_PERF_CCHE_UCHE_READ_BEATS_SP = 152 -A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC = 153 -A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ = 154 -A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0 = 155 -A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1 = 156 -A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC = 157 -A7XX_PERF_CCHE_GMEM_READ_BEATS_TP = 158 -A7XX_PERF_CCHE_GMEM_READ_BEATS_SP = 159 -A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD = 160 -A7XX_PERF_CCHE_BANK_REQ0 = 161 -A7XX_PERF_CCHE_BANK_REQ1 = 162 -A7XX_PERF_CCHE_BANK_REQ2 = 163 -A7XX_PERF_CCHE_BANK_REQ3 = 164 -A7XX_PERF_CCHE_BANK_REQ4 = 165 -A7XX_PERF_CCHE_BANK_REQ5 = 166 -A7XX_PERF_CCHE_BANK_REQ6 = 167 -A7XX_PERF_CCHE_BANK_REQ7 = 168 -A7XX_PERF_CCHE_BANK_REQ8 = 169 -A7XX_PERF_CCHE_BANK_REQ9 = 170 -A7XX_PERF_CCHE_BANK_REQ10 = 171 -A7XX_PERF_CCHE_BANK_REQ11 = 172 -A7XX_PERF_CCHE_BANK_REQ12 = 173 -A7XX_PERF_CCHE_BANK_REQ13 = 174 -A7XX_PERF_CCHE_BANK_REQ14 = 175 -A7XX_PERF_CCHE_BANK_REQ15 = 176 -A7XX_PERF_CCHE_GBANK_REQ0 = 177 -A7XX_PERF_CCHE_GBANK_REQ1 = 178 -A7XX_PERF_CCHE_GBANK_REQ2 = 179 -A7XX_PERF_CCHE_GBANK_REQ3 = 180 -A7XX_PERF_CCHE_TPH_REF_FULL = 181 -A7XX_PERF_CCHE_TPH_VICTIM_FULL = 182 -A7XX_PERF_CCHE_TPH_EXT_FULL = 183 -A7XX_PERF_CCHE_RAM_READ_REQ = 184 -A7XX_PERF_CCHE_RAM_WRITE_REQ = 185 -A7XX_PERF_CCHE_TPH_CONFLICT_CL = 186 -A7XX_PERF_CCHE_DBANK_CONFLICT = 187 -A7XX_PERF_CCHE_TPH_QUEUE_FULL = 188 -A7XX_PERF_CCHE_DPH_QUEUE_FULL = 189 -A7XX_PERF_CCHE_OPH_QUEUE_FULL = 190 -A7XX_PERF_CCHE_WACK_QUEUE_FULL = 191 -A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST = 192 -A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST = 193 -A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST = 194 -A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST = 195 -A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST = 196 -A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST = 197 -A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST = 198 -A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST = 199 -A7XX_PERF_CCHE_STALL_CYCLES_TP = 200 -a7xx_uche_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_tp_perfcounter_select' -a7xx_tp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_TP_NEVER_COUNT', - 1: 'A7XX_PERF_TP_BUSY_CYCLES', - 2: 'A7XX_PERF_TP_STALL_CYCLES_UCHE', - 3: 'A7XX_PERF_TP_LATENCY_CYCLES', - 4: 'A7XX_PERF_TP_LATENCY_TRANS', - 5: 'A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES', - 6: 'A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES', - 7: 'A7XX_PERF_TP_L1_CACHELINE_REQUESTS', - 8: 'A7XX_PERF_TP_L1_CACHELINE_MISSES', - 9: 'A7XX_PERF_TP_SP_TP_TRANS', - 10: 'A7XX_PERF_TP_TP_SP_TRANS', - 11: 'A7XX_PERF_TP_OUTPUT_PIXELS', - 12: 'A7XX_PERF_TP_FILTER_WORKLOAD_16BIT', - 13: 'A7XX_PERF_TP_FILTER_WORKLOAD_32BIT', - 14: 'A7XX_PERF_TP_QUADS_RECEIVED', - 15: 'A7XX_PERF_TP_QUADS_OFFSET', - 16: 'A7XX_PERF_TP_QUADS_SHADOW', - 17: 'A7XX_PERF_TP_QUADS_ARRAY', - 18: 'A7XX_PERF_TP_QUADS_GRADIENT', - 19: 'A7XX_PERF_TP_QUADS_1D', - 20: 'A7XX_PERF_TP_QUADS_2D', - 21: 'A7XX_PERF_TP_QUADS_BUFFER', - 22: 'A7XX_PERF_TP_QUADS_3D', - 23: 'A7XX_PERF_TP_QUADS_CUBE', - 24: 'A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED', - 25: 'A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', - 26: 'A7XX_PERF_TP_OUTPUT_PIXELS_POINT', - 27: 'A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR', - 28: 'A7XX_PERF_TP_OUTPUT_PIXELS_MIP', - 29: 'A7XX_PERF_TP_OUTPUT_PIXELS_ANISO', - 30: 'A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 31: 'A7XX_PERF_TP_FLAG_CACHE_REQUESTS', - 32: 'A7XX_PERF_TP_FLAG_CACHE_MISSES', - 33: 'A7XX_PERF_TP_L1_5_L2_REQUESTS', - 34: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS', - 35: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT', - 36: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 37: 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 38: 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT', - 39: 'A7XX_PERF_TP_TPA2TPC_TRANS', - 40: 'A7XX_PERF_TP_L1_MISSES_ASTC_1TILE', - 41: 'A7XX_PERF_TP_L1_MISSES_ASTC_2TILE', - 42: 'A7XX_PERF_TP_L1_MISSES_ASTC_4TILE', - 43: 'A7XX_PERF_TP_L1_5_COMPRESS_REQS', - 44: 'A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS', - 45: 'A7XX_PERF_TP_L1_BANK_CONFLICT', - 46: 'A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 47: 'A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS', - 48: 'A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 49: 'A7XX_PERF_TP_FRONTEND_WORKING_CYCLES', - 50: 'A7XX_PERF_TP_L1_TAG_WORKING_CYCLES', - 51: 'A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 52: 'A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 53: 'A7XX_PERF_TP_BACKEND_WORKING_CYCLES', - 54: 'A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 55: 'A7XX_PERF_TP_STARVE_CYCLES_SP', - 56: 'A7XX_PERF_TP_STARVE_CYCLES_UCHE', - 57: 'A7XX_PERF_TP_STALL_CYCLES_UFC', - 58: 'A7XX_PERF_TP_FORMAT_DECOMP_POINT', - 59: 'A7XX_PERF_TP_FILTER_POINT_FP16', - 60: 'A7XX_PERF_TP_FILTER_POINT_FP32', - 61: 'A7XX_PERF_TP_LATENCY_FIFO_FULL', - 62: 'A7XX_PERF_TP_RESERVED_62', - 63: 'A7XX_PERF_TP_RESERVED_63', - 64: 'A7XX_PERF_TP_RESERVED_64', - 65: 'A7XX_PERF_TP_RESERVED_65', - 66: 'A7XX_PERF_TP_RESERVED_66', - 67: 'A7XX_PERF_TP_RESERVED_67', - 68: 'A7XX_PERF_TP_RESERVED_68', - 69: 'A7XX_PERF_TP_RESERVED_69', - 70: 'A7XX_PERF_TP_RESERVED_70', - 71: 'A7XX_PERF_TP_RESERVED_71', - 72: 'A7XX_PERF_TP_RESERVED_72', - 73: 'A7XX_PERF_TP_RESERVED_73', - 74: 'A7XX_PERF_TP_RESERVED_74', - 75: 'A7XX_PERF_TP_RESERVED_75', - 76: 'A7XX_PERF_TP_RESERVED_76', - 77: 'A7XX_PERF_TP_RESERVED_77', - 78: 'A7XX_PERF_TP_RESERVED_78', - 79: 'A7XX_PERF_TP_RESERVED_79', - 80: 'A7XX_PERF_TP_RESERVED_80', - 81: 'A7XX_PERF_TP_RESERVED_81', - 82: 'A7XX_PERF_TP_RESERVED_82', - 83: 'A7XX_PERF_TP_RESERVED_83', - 84: 'A7XX_PERF_TP_RESERVED_84', - 85: 'A7XX_PERF_TP_RESERVED_85', - 86: 'A7XX_PERF_TP_RESERVED_86', - 87: 'A7XX_PERF_TP_RESERVED_87', - 88: 'A7XX_PERF_TP_RESERVED_88', - 89: 'A7XX_PERF_TP_RESERVED_89', - 90: 'A7XX_PERF_TP_RESERVED_90', - 91: 'A7XX_PERF_TP_RESERVED_91', - 92: 'A7XX_PERF_TP_RESERVED_92', - 93: 'A7XX_PERF_TP_RESERVED_93', - 94: 'A7XX_PERF_TP_RESERVED_94', - 95: 'A7XX_PERF_TP_RESERVED_95', - 96: 'A7XX_PERF_TP_RESERVED_96', - 97: 'A7XX_PERF_TP_RESERVED_97', - 98: 'A7XX_PERF_TP_RESERVED_98', - 99: 'A7XX_PERF_TP_RESERVED_99', - 100: 'A7XX_PERF_TP_RESERVED_100', - 101: 'A7XX_PERF_TP_RESERVED_101', - 102: 'A7XX_PERF_TP_RESERVED_102', - 103: 'A7XX_PERF_TP_RESERVED_103', - 104: 'A7XX_PERF_TP_RESERVED_104', - 105: 'A7XX_PERF_TP_RESERVED_105', - 106: 'A7XX_PERF_TP_RESERVED_106', - 107: 'A7XX_PERF_TP_RESERVED_107', - 108: 'A7XX_PERF_TP_RESERVED_108', - 109: 'A7XX_PERF_TP_RESERVED_109', - 110: 'A7XX_PERF_TP_RESERVED_110', - 111: 'A7XX_PERF_TP_RESERVED_111', - 112: 'A7XX_PERF_TP_RESERVED_112', - 113: 'A7XX_PERF_TP_RESERVED_113', - 114: 'A7XX_PERF_TP_RESERVED_114', - 115: 'A7XX_PERF_TP_RESERVED_115', - 116: 'A7XX_PERF_TP_RESERVED_116', - 117: 'A7XX_PERF_TP_RESERVED_117', - 118: 'A7XX_PERF_TP_RESERVED_118', - 119: 'A7XX_PERF_TP_RESERVED_119', - 120: 'A7XX_PERF_TP_RESERVED_120', - 121: 'A7XX_PERF_TP_RESERVED_121', - 122: 'A7XX_PERF_TP_RESERVED_122', - 123: 'A7XX_PERF_TP_RESERVED_123', - 124: 'A7XX_PERF_TP_RESERVED_124', - 125: 'A7XX_PERF_TP_RESERVED_125', - 126: 'A7XX_PERF_TP_RESERVED_126', - 127: 'A7XX_PERF_TP_RESERVED_127', - 128: 'A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR', - 129: 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16', - 130: 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16', - 131: 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32', - 132: 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32', -} -A7XX_PERF_TP_NEVER_COUNT = 0 -A7XX_PERF_TP_BUSY_CYCLES = 1 -A7XX_PERF_TP_STALL_CYCLES_UCHE = 2 -A7XX_PERF_TP_LATENCY_CYCLES = 3 -A7XX_PERF_TP_LATENCY_TRANS = 4 -A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES = 5 -A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES = 6 -A7XX_PERF_TP_L1_CACHELINE_REQUESTS = 7 -A7XX_PERF_TP_L1_CACHELINE_MISSES = 8 -A7XX_PERF_TP_SP_TP_TRANS = 9 -A7XX_PERF_TP_TP_SP_TRANS = 10 -A7XX_PERF_TP_OUTPUT_PIXELS = 11 -A7XX_PERF_TP_FILTER_WORKLOAD_16BIT = 12 -A7XX_PERF_TP_FILTER_WORKLOAD_32BIT = 13 -A7XX_PERF_TP_QUADS_RECEIVED = 14 -A7XX_PERF_TP_QUADS_OFFSET = 15 -A7XX_PERF_TP_QUADS_SHADOW = 16 -A7XX_PERF_TP_QUADS_ARRAY = 17 -A7XX_PERF_TP_QUADS_GRADIENT = 18 -A7XX_PERF_TP_QUADS_1D = 19 -A7XX_PERF_TP_QUADS_2D = 20 -A7XX_PERF_TP_QUADS_BUFFER = 21 -A7XX_PERF_TP_QUADS_3D = 22 -A7XX_PERF_TP_QUADS_CUBE = 23 -A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED = 24 -A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS = 25 -A7XX_PERF_TP_OUTPUT_PIXELS_POINT = 26 -A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR = 27 -A7XX_PERF_TP_OUTPUT_PIXELS_MIP = 28 -A7XX_PERF_TP_OUTPUT_PIXELS_ANISO = 29 -A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 30 -A7XX_PERF_TP_FLAG_CACHE_REQUESTS = 31 -A7XX_PERF_TP_FLAG_CACHE_MISSES = 32 -A7XX_PERF_TP_L1_5_L2_REQUESTS = 33 -A7XX_PERF_TP_2D_OUTPUT_PIXELS = 34 -A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT = 35 -A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 36 -A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT = 37 -A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT = 38 -A7XX_PERF_TP_TPA2TPC_TRANS = 39 -A7XX_PERF_TP_L1_MISSES_ASTC_1TILE = 40 -A7XX_PERF_TP_L1_MISSES_ASTC_2TILE = 41 -A7XX_PERF_TP_L1_MISSES_ASTC_4TILE = 42 -A7XX_PERF_TP_L1_5_COMPRESS_REQS = 43 -A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS = 44 -A7XX_PERF_TP_L1_BANK_CONFLICT = 45 -A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES = 46 -A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS = 47 -A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED = 48 -A7XX_PERF_TP_FRONTEND_WORKING_CYCLES = 49 -A7XX_PERF_TP_L1_TAG_WORKING_CYCLES = 50 -A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 51 -A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 52 -A7XX_PERF_TP_BACKEND_WORKING_CYCLES = 53 -A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54 -A7XX_PERF_TP_STARVE_CYCLES_SP = 55 -A7XX_PERF_TP_STARVE_CYCLES_UCHE = 56 -A7XX_PERF_TP_STALL_CYCLES_UFC = 57 -A7XX_PERF_TP_FORMAT_DECOMP_POINT = 58 -A7XX_PERF_TP_FILTER_POINT_FP16 = 59 -A7XX_PERF_TP_FILTER_POINT_FP32 = 60 -A7XX_PERF_TP_LATENCY_FIFO_FULL = 61 -A7XX_PERF_TP_RESERVED_62 = 62 -A7XX_PERF_TP_RESERVED_63 = 63 -A7XX_PERF_TP_RESERVED_64 = 64 -A7XX_PERF_TP_RESERVED_65 = 65 -A7XX_PERF_TP_RESERVED_66 = 66 -A7XX_PERF_TP_RESERVED_67 = 67 -A7XX_PERF_TP_RESERVED_68 = 68 -A7XX_PERF_TP_RESERVED_69 = 69 -A7XX_PERF_TP_RESERVED_70 = 70 -A7XX_PERF_TP_RESERVED_71 = 71 -A7XX_PERF_TP_RESERVED_72 = 72 -A7XX_PERF_TP_RESERVED_73 = 73 -A7XX_PERF_TP_RESERVED_74 = 74 -A7XX_PERF_TP_RESERVED_75 = 75 -A7XX_PERF_TP_RESERVED_76 = 76 -A7XX_PERF_TP_RESERVED_77 = 77 -A7XX_PERF_TP_RESERVED_78 = 78 -A7XX_PERF_TP_RESERVED_79 = 79 -A7XX_PERF_TP_RESERVED_80 = 80 -A7XX_PERF_TP_RESERVED_81 = 81 -A7XX_PERF_TP_RESERVED_82 = 82 -A7XX_PERF_TP_RESERVED_83 = 83 -A7XX_PERF_TP_RESERVED_84 = 84 -A7XX_PERF_TP_RESERVED_85 = 85 -A7XX_PERF_TP_RESERVED_86 = 86 -A7XX_PERF_TP_RESERVED_87 = 87 -A7XX_PERF_TP_RESERVED_88 = 88 -A7XX_PERF_TP_RESERVED_89 = 89 -A7XX_PERF_TP_RESERVED_90 = 90 -A7XX_PERF_TP_RESERVED_91 = 91 -A7XX_PERF_TP_RESERVED_92 = 92 -A7XX_PERF_TP_RESERVED_93 = 93 -A7XX_PERF_TP_RESERVED_94 = 94 -A7XX_PERF_TP_RESERVED_95 = 95 -A7XX_PERF_TP_RESERVED_96 = 96 -A7XX_PERF_TP_RESERVED_97 = 97 -A7XX_PERF_TP_RESERVED_98 = 98 -A7XX_PERF_TP_RESERVED_99 = 99 -A7XX_PERF_TP_RESERVED_100 = 100 -A7XX_PERF_TP_RESERVED_101 = 101 -A7XX_PERF_TP_RESERVED_102 = 102 -A7XX_PERF_TP_RESERVED_103 = 103 -A7XX_PERF_TP_RESERVED_104 = 104 -A7XX_PERF_TP_RESERVED_105 = 105 -A7XX_PERF_TP_RESERVED_106 = 106 -A7XX_PERF_TP_RESERVED_107 = 107 -A7XX_PERF_TP_RESERVED_108 = 108 -A7XX_PERF_TP_RESERVED_109 = 109 -A7XX_PERF_TP_RESERVED_110 = 110 -A7XX_PERF_TP_RESERVED_111 = 111 -A7XX_PERF_TP_RESERVED_112 = 112 -A7XX_PERF_TP_RESERVED_113 = 113 -A7XX_PERF_TP_RESERVED_114 = 114 -A7XX_PERF_TP_RESERVED_115 = 115 -A7XX_PERF_TP_RESERVED_116 = 116 -A7XX_PERF_TP_RESERVED_117 = 117 -A7XX_PERF_TP_RESERVED_118 = 118 -A7XX_PERF_TP_RESERVED_119 = 119 -A7XX_PERF_TP_RESERVED_120 = 120 -A7XX_PERF_TP_RESERVED_121 = 121 -A7XX_PERF_TP_RESERVED_122 = 122 -A7XX_PERF_TP_RESERVED_123 = 123 -A7XX_PERF_TP_RESERVED_124 = 124 -A7XX_PERF_TP_RESERVED_125 = 125 -A7XX_PERF_TP_RESERVED_126 = 126 -A7XX_PERF_TP_RESERVED_127 = 127 -A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR = 128 -A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16 = 129 -A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16 = 130 -A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32 = 131 -A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32 = 132 -a7xx_tp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_sp_perfcounter_select' -a7xx_sp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_SP_NEVER_COUNT', - 1: 'A7XX_PERF_SP_BUSY_CYCLES', - 2: 'A7XX_PERF_SP_ALU_WORKING_CYCLES', - 3: 'A7XX_PERF_SP_STALL_CYCLES_VPC_BE', - 4: 'A7XX_PERF_SP_STALL_CYCLES_TP', - 5: 'A7XX_PERF_SP_STALL_CYCLES_UCHE', - 6: 'A7XX_PERF_SP_STALL_CYCLES_RB', - 7: 'A7XX_PERF_SP_NON_EXECUTION_CYCLES', - 8: 'A7XX_PERF_SP_WAVE_CONTEXTS', - 9: 'A7XX_PERF_SP_WAVE_CONTEXT_CYCLES', - 10: 'A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES', - 11: 'A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES', - 12: 'A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES', - 13: 'A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES', - 14: 'A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES', - 15: 'A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES', - 16: 'A7XX_PERF_SP_WAVE_CTRL_CYCLES', - 17: 'A7XX_PERF_SP_WAVE_LOAD_CYCLES', - 18: 'A7XX_PERF_SP_WAVE_EMIT_CYCLES', - 19: 'A7XX_PERF_SP_WAVE_NOP_CYCLES', - 20: 'A7XX_PERF_SP_WAVE_WAIT_CYCLES', - 21: 'A7XX_PERF_SP_WAVE_FETCH_CYCLES', - 22: 'A7XX_PERF_SP_WAVE_IDLE_CYCLES', - 23: 'A7XX_PERF_SP_WAVE_END_CYCLES', - 24: 'A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES', - 25: 'A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 26: 'A7XX_PERF_SP_WAVE_JOIN_CYCLES', - 27: 'A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS', - 28: 'A7XX_PERF_SP_LM_STORE_INSTRUCTIONS', - 29: 'A7XX_PERF_SP_LM_ATOMICS', - 30: 'A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS', - 31: 'A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', - 32: 'A7XX_PERF_SP_GM_ATOMICS', - 33: 'A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 34: 'A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 35: 'A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 36: 'A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 37: 'A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 38: 'A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 39: 'A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 40: 'A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 41: 'A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 42: 'A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 43: 'A7XX_PERF_SP_VS_INSTRUCTIONS', - 44: 'A7XX_PERF_SP_FS_INSTRUCTIONS', - 45: 'A7XX_PERF_SP_ADDR_LOCK_COUNT', - 46: 'A7XX_PERF_SP_UCHE_READ_TRANS', - 47: 'A7XX_PERF_SP_UCHE_WRITE_TRANS', - 48: 'A7XX_PERF_SP_EXPORT_VPC_TRANS', - 49: 'A7XX_PERF_SP_EXPORT_RB_TRANS', - 50: 'A7XX_PERF_SP_PIXELS_KILLED', - 51: 'A7XX_PERF_SP_ICL1_REQUESTS', - 52: 'A7XX_PERF_SP_ICL1_MISSES', - 53: 'A7XX_PERF_SP_HS_INSTRUCTIONS', - 54: 'A7XX_PERF_SP_DS_INSTRUCTIONS', - 55: 'A7XX_PERF_SP_GS_INSTRUCTIONS', - 56: 'A7XX_PERF_SP_CS_INSTRUCTIONS', - 57: 'A7XX_PERF_SP_GPR_READ', - 58: 'A7XX_PERF_SP_GPR_WRITE', - 59: 'A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 60: 'A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 61: 'A7XX_PERF_SP_LM_BANK_CONFLICTS', - 62: 'A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES', - 63: 'A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 64: 'A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 65: 'A7XX_PERF_SP_LM_WORKING_CYCLES', - 66: 'A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES', - 67: 'A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES', - 68: 'A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 69: 'A7XX_PERF_SP_STARVE_CYCLES_HLSQ', - 70: 'A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES', - 71: 'A7XX_PERF_SP_WORKING_EU', - 72: 'A7XX_PERF_SP_ANY_EU_WORKING', - 73: 'A7XX_PERF_SP_WORKING_EU_FS_STAGE', - 74: 'A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE', - 75: 'A7XX_PERF_SP_WORKING_EU_VS_STAGE', - 76: 'A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE', - 77: 'A7XX_PERF_SP_WORKING_EU_CS_STAGE', - 78: 'A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE', - 79: 'A7XX_PERF_SP_GPR_READ_PREFETCH', - 80: 'A7XX_PERF_SP_GPR_READ_CONFLICT', - 81: 'A7XX_PERF_SP_GPR_WRITE_CONFLICT', - 82: 'A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES', - 83: 'A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 84: 'A7XX_PERF_SP_EXECUTABLE_WAVES', - 85: 'A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES', - 86: 'A7XX_PERF_SP_RESERVED_86', - 87: 'A7XX_PERF_SP_BYPASS_BUSY_CYCLES', - 88: 'A7XX_PERF_SP_ANY_EU_WORKING_LPAC', - 89: 'A7XX_PERF_SP_WAVE_ALU_CYCLES', - 90: 'A7XX_PERF_SP_WAVE_EFU_CYCLES', - 91: 'A7XX_PERF_SP_WAVE_INT_CYCLES', - 92: 'A7XX_PERF_SP_WAVE_CSP_CYCLES', - 93: 'A7XX_PERF_SP_EWAVE_CONTEXTS', - 94: 'A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES', - 95: 'A7XX_PERF_SP_LPAC_BUSY_CYCLES', - 96: 'A7XX_PERF_SP_LPAC_INSTRUCTIONS', - 97: 'A7XX_PERF_SP_FS_STAGE_1X_WAVES', - 98: 'A7XX_PERF_SP_FS_STAGE_2X_WAVES', - 99: 'A7XX_PERF_SP_QUADS', - 100: 'A7XX_PERF_SP_CS_INVOCATIONS', - 101: 'A7XX_PERF_SP_PIXELS', - 102: 'A7XX_PERF_SP_LPAC_DRAWCALLS', - 103: 'A7XX_PERF_SP_PI_WORKING_CYCLES', - 104: 'A7XX_PERF_SP_WAVE_INPUT_CYCLES', - 105: 'A7XX_PERF_SP_WAVE_OUTPUT_CYCLES', - 106: 'A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES', - 107: 'A7XX_PERF_SP_WAVE_HWAVE_SYNC', - 108: 'A7XX_PERF_SP_OUTPUT_3D_PIXELS', - 109: 'A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS', - 110: 'A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS', - 111: 'A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS', - 112: 'A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS', - 113: 'A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS', - 114: 'A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS', - 115: 'A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS', - 116: 'A7XX_PERF_SP_ALU_GPR_READ_CYCLES', - 117: 'A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES', - 118: 'A7XX_PERF_SP_LM_FULL_CYCLES', - 119: 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES', - 120: 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES', - 121: 'A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION', - 122: 'A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS', - 123: 'A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', - 124: 'A7XX_PERF_SP_RBRT_KICKOFF_DQUADS', - 125: 'A7XX_PERF_SP_RTU_BUSY_CYCLES', - 126: 'A7XX_PERF_SP_RTU_L0_HITS', - 127: 'A7XX_PERF_SP_RTU_L0_MISSES', - 128: 'A7XX_PERF_SP_RTU_L0_HIT_ON_MISS', - 129: 'A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE', - 130: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE', - 131: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE', - 132: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE', - 133: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA', - 134: 'A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT', - 135: 'A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT', - 136: 'A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE', - 137: 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0', - 138: 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO', - 139: 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES', - 140: 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES', - 141: 'A7XX_PERF_SP_STCHE_MISS_INC_VS', - 142: 'A7XX_PERF_SP_STCHE_MISS_INC_FS', - 143: 'A7XX_PERF_SP_STCHE_MISS_INC_BV', - 144: 'A7XX_PERF_SP_STCHE_MISS_INC_LPAC', - 145: 'A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS', - 146: 'A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', - 147: 'A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS', - 148: 'A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS', - 149: 'A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS', - 150: 'A7XX_PERF_SP_SCH_STALL_CYCLES_RTU', - 151: 'A7XX_PERF_SP_EFU_WORKING_CYCLES', - 152: 'A7XX_PERF_SP_BRANCH_TAKEN', - 153: 'A7XX_PERF_SP_BRANCH_NOT_TAKEN', - 154: 'A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT', - 155: 'A7XX_PERF_SP_BRANCH_INS_COUNT', - 156: 'A7XX_PERF_SP_PREDICT_TAKEN', - 157: 'A7XX_PERF_SP_PREDICT_NOT_TAKEN', - 158: 'A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT', - 159: 'A7XX_PERF_SP_PREDICT_INS_COUNT', - 160: 'A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', - 161: 'A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD', - 162: 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ', - 163: 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD', - 164: 'A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ', - 165: 'A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD', - 166: 'A7XX_PERF_SP_LB_READ_XFER_ALU', - 167: 'A7XX_PERF_SP_LB_ALU_READ_CONS', - 168: 'A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER', - 169: 'A7XX_PERF_SP_LB_WRITE_XFER_VPC', - 170: 'A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER', - 171: 'A7XX_PERF_SP_LB_LDST_RW_LM', - 172: 'A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED', - 173: 'A7XX_PERF_SP_LB_LDST_WRITE_CONS', - 174: 'A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED', - 175: 'A7XX_PERF_SP_GPR_READ_BANK', - 176: 'A7XX_PERF_SP_GPR_WRITE_BANK', - 177: 'A7XX_PERF_SP_VS_WAVE_REQ_PENDING', - 178: 'A7XX_PERF_SP_FS_WAVE_REQ_PENDING', - 179: 'A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', - 180: 'A7XX_PERF_SP_WAVE_SPLIT_CNT', - 181: 'A7XX_PERF_SP_FS_OOO_WAVE_ACC', -} -A7XX_PERF_SP_NEVER_COUNT = 0 -A7XX_PERF_SP_BUSY_CYCLES = 1 -A7XX_PERF_SP_ALU_WORKING_CYCLES = 2 -A7XX_PERF_SP_STALL_CYCLES_VPC_BE = 3 -A7XX_PERF_SP_STALL_CYCLES_TP = 4 -A7XX_PERF_SP_STALL_CYCLES_UCHE = 5 -A7XX_PERF_SP_STALL_CYCLES_RB = 6 -A7XX_PERF_SP_NON_EXECUTION_CYCLES = 7 -A7XX_PERF_SP_WAVE_CONTEXTS = 8 -A7XX_PERF_SP_WAVE_CONTEXT_CYCLES = 9 -A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES = 10 -A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES = 11 -A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES = 12 -A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES = 13 -A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES = 14 -A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES = 15 -A7XX_PERF_SP_WAVE_CTRL_CYCLES = 16 -A7XX_PERF_SP_WAVE_LOAD_CYCLES = 17 -A7XX_PERF_SP_WAVE_EMIT_CYCLES = 18 -A7XX_PERF_SP_WAVE_NOP_CYCLES = 19 -A7XX_PERF_SP_WAVE_WAIT_CYCLES = 20 -A7XX_PERF_SP_WAVE_FETCH_CYCLES = 21 -A7XX_PERF_SP_WAVE_IDLE_CYCLES = 22 -A7XX_PERF_SP_WAVE_END_CYCLES = 23 -A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES = 24 -A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25 -A7XX_PERF_SP_WAVE_JOIN_CYCLES = 26 -A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS = 27 -A7XX_PERF_SP_LM_STORE_INSTRUCTIONS = 28 -A7XX_PERF_SP_LM_ATOMICS = 29 -A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS = 30 -A7XX_PERF_SP_GM_STORE_INSTRUCTIONS = 31 -A7XX_PERF_SP_GM_ATOMICS = 32 -A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33 -A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34 -A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35 -A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36 -A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37 -A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38 -A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39 -A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40 -A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41 -A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42 -A7XX_PERF_SP_VS_INSTRUCTIONS = 43 -A7XX_PERF_SP_FS_INSTRUCTIONS = 44 -A7XX_PERF_SP_ADDR_LOCK_COUNT = 45 -A7XX_PERF_SP_UCHE_READ_TRANS = 46 -A7XX_PERF_SP_UCHE_WRITE_TRANS = 47 -A7XX_PERF_SP_EXPORT_VPC_TRANS = 48 -A7XX_PERF_SP_EXPORT_RB_TRANS = 49 -A7XX_PERF_SP_PIXELS_KILLED = 50 -A7XX_PERF_SP_ICL1_REQUESTS = 51 -A7XX_PERF_SP_ICL1_MISSES = 52 -A7XX_PERF_SP_HS_INSTRUCTIONS = 53 -A7XX_PERF_SP_DS_INSTRUCTIONS = 54 -A7XX_PERF_SP_GS_INSTRUCTIONS = 55 -A7XX_PERF_SP_CS_INSTRUCTIONS = 56 -A7XX_PERF_SP_GPR_READ = 57 -A7XX_PERF_SP_GPR_WRITE = 58 -A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59 -A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60 -A7XX_PERF_SP_LM_BANK_CONFLICTS = 61 -A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62 -A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63 -A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64 -A7XX_PERF_SP_LM_WORKING_CYCLES = 65 -A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES = 66 -A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES = 67 -A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68 -A7XX_PERF_SP_STARVE_CYCLES_HLSQ = 69 -A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES = 70 -A7XX_PERF_SP_WORKING_EU = 71 -A7XX_PERF_SP_ANY_EU_WORKING = 72 -A7XX_PERF_SP_WORKING_EU_FS_STAGE = 73 -A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE = 74 -A7XX_PERF_SP_WORKING_EU_VS_STAGE = 75 -A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE = 76 -A7XX_PERF_SP_WORKING_EU_CS_STAGE = 77 -A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE = 78 -A7XX_PERF_SP_GPR_READ_PREFETCH = 79 -A7XX_PERF_SP_GPR_READ_CONFLICT = 80 -A7XX_PERF_SP_GPR_WRITE_CONFLICT = 81 -A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES = 82 -A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83 -A7XX_PERF_SP_EXECUTABLE_WAVES = 84 -A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES = 85 -A7XX_PERF_SP_RESERVED_86 = 86 -A7XX_PERF_SP_BYPASS_BUSY_CYCLES = 87 -A7XX_PERF_SP_ANY_EU_WORKING_LPAC = 88 -A7XX_PERF_SP_WAVE_ALU_CYCLES = 89 -A7XX_PERF_SP_WAVE_EFU_CYCLES = 90 -A7XX_PERF_SP_WAVE_INT_CYCLES = 91 -A7XX_PERF_SP_WAVE_CSP_CYCLES = 92 -A7XX_PERF_SP_EWAVE_CONTEXTS = 93 -A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES = 94 -A7XX_PERF_SP_LPAC_BUSY_CYCLES = 95 -A7XX_PERF_SP_LPAC_INSTRUCTIONS = 96 -A7XX_PERF_SP_FS_STAGE_1X_WAVES = 97 -A7XX_PERF_SP_FS_STAGE_2X_WAVES = 98 -A7XX_PERF_SP_QUADS = 99 -A7XX_PERF_SP_CS_INVOCATIONS = 100 -A7XX_PERF_SP_PIXELS = 101 -A7XX_PERF_SP_LPAC_DRAWCALLS = 102 -A7XX_PERF_SP_PI_WORKING_CYCLES = 103 -A7XX_PERF_SP_WAVE_INPUT_CYCLES = 104 -A7XX_PERF_SP_WAVE_OUTPUT_CYCLES = 105 -A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES = 106 -A7XX_PERF_SP_WAVE_HWAVE_SYNC = 107 -A7XX_PERF_SP_OUTPUT_3D_PIXELS = 108 -A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS = 109 -A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS = 110 -A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS = 111 -A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS = 112 -A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS = 113 -A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS = 114 -A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS = 115 -A7XX_PERF_SP_ALU_GPR_READ_CYCLES = 116 -A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES = 117 -A7XX_PERF_SP_LM_FULL_CYCLES = 118 -A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES = 119 -A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES = 120 -A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION = 121 -A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS = 122 -A7XX_PERF_SP_RBRT_KICKOFF_FIBERS = 123 -A7XX_PERF_SP_RBRT_KICKOFF_DQUADS = 124 -A7XX_PERF_SP_RTU_BUSY_CYCLES = 125 -A7XX_PERF_SP_RTU_L0_HITS = 126 -A7XX_PERF_SP_RTU_L0_MISSES = 127 -A7XX_PERF_SP_RTU_L0_HIT_ON_MISS = 128 -A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE = 129 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE = 130 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE = 131 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE = 132 -A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA = 133 -A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT = 134 -A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT = 135 -A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE = 136 -A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0 = 137 -A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO = 138 -A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES = 139 -A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES = 140 -A7XX_PERF_SP_STCHE_MISS_INC_VS = 141 -A7XX_PERF_SP_STCHE_MISS_INC_FS = 142 -A7XX_PERF_SP_STCHE_MISS_INC_BV = 143 -A7XX_PERF_SP_STCHE_MISS_INC_LPAC = 144 -A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS = 145 -A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS = 146 -A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS = 147 -A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS = 148 -A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS = 149 -A7XX_PERF_SP_SCH_STALL_CYCLES_RTU = 150 -A7XX_PERF_SP_EFU_WORKING_CYCLES = 151 -A7XX_PERF_SP_BRANCH_TAKEN = 152 -A7XX_PERF_SP_BRANCH_NOT_TAKEN = 153 -A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT = 154 -A7XX_PERF_SP_BRANCH_INS_COUNT = 155 -A7XX_PERF_SP_PREDICT_TAKEN = 156 -A7XX_PERF_SP_PREDICT_NOT_TAKEN = 157 -A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT = 158 -A7XX_PERF_SP_PREDICT_INS_COUNT = 159 -A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ = 160 -A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD = 161 -A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ = 162 -A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD = 163 -A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ = 164 -A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD = 165 -A7XX_PERF_SP_LB_READ_XFER_ALU = 166 -A7XX_PERF_SP_LB_ALU_READ_CONS = 167 -A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER = 168 -A7XX_PERF_SP_LB_WRITE_XFER_VPC = 169 -A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER = 170 -A7XX_PERF_SP_LB_LDST_RW_LM = 171 -A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED = 172 -A7XX_PERF_SP_LB_LDST_WRITE_CONS = 173 -A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED = 174 -A7XX_PERF_SP_GPR_READ_BANK = 175 -A7XX_PERF_SP_GPR_WRITE_BANK = 176 -A7XX_PERF_SP_VS_WAVE_REQ_PENDING = 177 -A7XX_PERF_SP_FS_WAVE_REQ_PENDING = 178 -A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING = 179 -A7XX_PERF_SP_WAVE_SPLIT_CNT = 180 -A7XX_PERF_SP_FS_OOO_WAVE_ACC = 181 -a7xx_sp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_rb_perfcounter_select' -a7xx_rb_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_RB_NEVER_COUNT', - 1: 'A7XX_PERF_RB_BUSY_CYCLES', - 2: 'A7XX_PERF_RB_STALL_CYCLES_HLSQ', - 3: 'A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL', - 4: 'A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL', - 5: 'A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL', - 6: 'A7XX_PERF_RB_STARVE_CYCLES_SP', - 7: 'A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE', - 8: 'A7XX_PERF_RB_STARVE_CYCLES_CCU', - 9: 'A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', - 10: 'A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE', - 11: 'A7XX_PERF_RB_Z_WORKLOAD', - 12: 'A7XX_PERF_RB_HLSQ_ACTIVE', - 13: 'A7XX_PERF_RB_Z_READ', - 14: 'A7XX_PERF_RB_Z_WRITE', - 15: 'A7XX_PERF_RB_C_READ', - 16: 'A7XX_PERF_RB_C_WRITE', - 17: 'A7XX_PERF_RB_TOTAL_PASS', - 18: 'A7XX_PERF_RB_Z_PASS', - 19: 'A7XX_PERF_RB_Z_FAIL', - 20: 'A7XX_PERF_RB_S_FAIL', - 21: 'A7XX_PERF_RB_BLENDED_FXP_COMPONENTS', - 22: 'A7XX_PERF_RB_BLENDED_FP16_COMPONENTS', - 23: 'A7XX_PERF_RB_PS_INVOCATIONS', - 24: 'A7XX_PERF_RB_2D_ALIVE_CYCLES', - 25: 'A7XX_PERF_RB_2D_STARVE_CYCLES_SP', - 26: 'A7XX_PERF_RB_2D_VALID_PIXELS', - 27: 'A7XX_PERF_RB_3D_PIXELS', - 28: 'A7XX_PERF_RB_BLENDER_WORKING_CYCLES', - 29: 'A7XX_PERF_RB_ZPROC_WORKING_CYCLES', - 30: 'A7XX_PERF_RB_CPROC_WORKING_CYCLES', - 31: 'A7XX_PERF_RB_SAMPLER_WORKING_CYCLES', - 32: 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 33: 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 34: 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 35: 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 36: 'A7XX_PERF_RB_STALL_CYCLES_VPC_BE', - 37: 'A7XX_PERF_RB_BLENDED_FP32_COMPONENTS', - 38: 'A7XX_PERF_RB_COLOR_PIX_TILES', - 39: 'A7XX_PERF_RB_STALL_CYCLES_CCU', - 40: 'A7XX_PERF_RB_EARLY_Z_ARB3_GRANT', - 41: 'A7XX_PERF_RB_LATE_Z_ARB3_GRANT', - 42: 'A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', - 43: 'A7XX_PERF_RB_VRS_1X1_QUADS', - 44: 'A7XX_PERF_RB_VRS_2X1_QUADS', - 45: 'A7XX_PERF_RB_VRS_1X2_QUADS', - 46: 'A7XX_PERF_RB_VRS_2X2_QUADS', - 47: 'A7XX_PERF_RB_VRS_2X4_QUADS', - 48: 'A7XX_PERF_RB_VRS_4X2_QUADS', - 49: 'A7XX_PERF_RB_VRS_4X4_QUADS', -} -A7XX_PERF_RB_NEVER_COUNT = 0 -A7XX_PERF_RB_BUSY_CYCLES = 1 -A7XX_PERF_RB_STALL_CYCLES_HLSQ = 2 -A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL = 3 -A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL = 4 -A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL = 5 -A7XX_PERF_RB_STARVE_CYCLES_SP = 6 -A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE = 7 -A7XX_PERF_RB_STARVE_CYCLES_CCU = 8 -A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE = 9 -A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE = 10 -A7XX_PERF_RB_Z_WORKLOAD = 11 -A7XX_PERF_RB_HLSQ_ACTIVE = 12 -A7XX_PERF_RB_Z_READ = 13 -A7XX_PERF_RB_Z_WRITE = 14 -A7XX_PERF_RB_C_READ = 15 -A7XX_PERF_RB_C_WRITE = 16 -A7XX_PERF_RB_TOTAL_PASS = 17 -A7XX_PERF_RB_Z_PASS = 18 -A7XX_PERF_RB_Z_FAIL = 19 -A7XX_PERF_RB_S_FAIL = 20 -A7XX_PERF_RB_BLENDED_FXP_COMPONENTS = 21 -A7XX_PERF_RB_BLENDED_FP16_COMPONENTS = 22 -A7XX_PERF_RB_PS_INVOCATIONS = 23 -A7XX_PERF_RB_2D_ALIVE_CYCLES = 24 -A7XX_PERF_RB_2D_STARVE_CYCLES_SP = 25 -A7XX_PERF_RB_2D_VALID_PIXELS = 26 -A7XX_PERF_RB_3D_PIXELS = 27 -A7XX_PERF_RB_BLENDER_WORKING_CYCLES = 28 -A7XX_PERF_RB_ZPROC_WORKING_CYCLES = 29 -A7XX_PERF_RB_CPROC_WORKING_CYCLES = 30 -A7XX_PERF_RB_SAMPLER_WORKING_CYCLES = 31 -A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 32 -A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 33 -A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 34 -A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 35 -A7XX_PERF_RB_STALL_CYCLES_VPC_BE = 36 -A7XX_PERF_RB_BLENDED_FP32_COMPONENTS = 37 -A7XX_PERF_RB_COLOR_PIX_TILES = 38 -A7XX_PERF_RB_STALL_CYCLES_CCU = 39 -A7XX_PERF_RB_EARLY_Z_ARB3_GRANT = 40 -A7XX_PERF_RB_LATE_Z_ARB3_GRANT = 41 -A7XX_PERF_RB_EARLY_Z_SKIP_GRANT = 42 -A7XX_PERF_RB_VRS_1X1_QUADS = 43 -A7XX_PERF_RB_VRS_2X1_QUADS = 44 -A7XX_PERF_RB_VRS_1X2_QUADS = 45 -A7XX_PERF_RB_VRS_2X2_QUADS = 46 -A7XX_PERF_RB_VRS_2X4_QUADS = 47 -A7XX_PERF_RB_VRS_4X2_QUADS = 48 -A7XX_PERF_RB_VRS_4X4_QUADS = 49 -a7xx_rb_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_vsc_perfcounter_select' -a7xx_vsc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_VSC_NEVER_COUNT', - 1: 'A7XX_PERF_VSC_BUSY_CYCLES', - 2: 'A7XX_PERF_VSC_WORKING_CYCLES', - 3: 'A7XX_PERF_VSC_STALL_CYCLES_UCHE', - 4: 'A7XX_PERF_VSC_EOT_NUM', - 5: 'A7XX_PERF_VSC_INPUT_TILES', - 6: 'A7XX_PERF_VSC_TILE_COMP_TRAN', - 7: 'A7XX_PERF_VSC_TILE_BYPASS_TRAN', -} -A7XX_PERF_VSC_NEVER_COUNT = 0 -A7XX_PERF_VSC_BUSY_CYCLES = 1 -A7XX_PERF_VSC_WORKING_CYCLES = 2 -A7XX_PERF_VSC_STALL_CYCLES_UCHE = 3 -A7XX_PERF_VSC_EOT_NUM = 4 -A7XX_PERF_VSC_INPUT_TILES = 5 -A7XX_PERF_VSC_TILE_COMP_TRAN = 6 -A7XX_PERF_VSC_TILE_BYPASS_TRAN = 7 -a7xx_vsc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_ccu_perfcounter_select' -a7xx_ccu_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_CCU_NEVER_COUNT', - 1: 'A7XX_PERF_CCU_BUSY_CYCLES', - 2: 'A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 3: 'A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 4: 'A7XX_PERF_CCU_DEPTH_BLOCKS', - 5: 'A7XX_PERF_CCU_COLOR_BLOCKS', - 6: 'A7XX_PERF_CCU_DEPTH_BLOCK_HIT', - 7: 'A7XX_PERF_CCU_COLOR_BLOCK_HIT', - 8: 'A7XX_PERF_CCU_PARTIAL_BLOCK_READ', - 9: 'A7XX_PERF_CCU_GMEM_READ', - 10: 'A7XX_PERF_CCU_GMEM_WRITE', - 11: 'A7XX_PERF_CCU_2D_RD_REQ', - 12: 'A7XX_PERF_CCU_2D_WR_REQ', - 13: 'A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT', - 14: 'A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT', - 15: 'A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED', - 16: 'A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED', - 17: 'A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT', - 18: 'A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT', - 19: 'A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER', - 20: 'A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER', - 21: 'A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', - 22: 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA', - 23: 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL', - 24: 'A7XX_PERF_CCU_COLOR_EVB_STALL', - 25: 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C', - 26: 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z', - 27: 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C', - 28: 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z', - 29: 'A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES', - 30: 'A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE', - 31: 'A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE', - 32: 'A7XX_PERF_CCU_RESERVED_32', - 33: 'A7XX_PERF_CCU_RESERVED_33', - 34: 'A7XX_PERF_CCU_RESERVED_34', - 35: 'A7XX_PERF_CCU_RESERVED_35', - 36: 'A7XX_PERF_CCU_RESERVED_36', - 37: 'A7XX_PERF_CCU_RESERVED_37', - 38: 'A7XX_PERF_CCU_RESERVED_38', - 39: 'A7XX_PERF_CCU_RESERVED_39', - 40: 'A7XX_PERF_CCU_RESERVED_40', - 41: 'A7XX_PERF_CCU_RESERVED_41', - 42: 'A7XX_PERF_CCU_RESERVED_42', - 43: 'A7XX_PERF_CCU_RESERVED_43', - 44: 'A7XX_PERF_CCU_RESERVED_44', - 45: 'A7XX_PERF_CCU_RESERVED_45', - 46: 'A7XX_PERF_CCU_RESERVED_46', - 47: 'A7XX_PERF_CCU_RESERVED_47', - 48: 'A7XX_PERF_CCU_RESERVED_48', - 49: 'A7XX_PERF_CCU_RESERVED_49', - 50: 'A7XX_PERF_CCU_RESERVED_50', - 51: 'A7XX_PERF_CCU_RESERVED_51', - 52: 'A7XX_PERF_CCU_RESERVED_52', - 53: 'A7XX_PERF_CCU_RESERVED_53', - 54: 'A7XX_PERF_CCU_RESERVED_54', - 55: 'A7XX_PERF_CCU_RESERVED_55', - 56: 'A7XX_PERF_CCU_RESERVED_56', - 57: 'A7XX_PERF_CCU_RESERVED_57', - 58: 'A7XX_PERF_CCU_RESERVED_58', - 59: 'A7XX_PERF_CCU_RESERVED_59', - 60: 'A7XX_PERF_CCU_RESERVED_60', - 61: 'A7XX_PERF_CCU_RESERVED_61', - 62: 'A7XX_PERF_CCU_RESERVED_62', - 63: 'A7XX_PERF_CCU_RESERVED_63', - 64: 'A7XX_PERF_UFC_L0_TP_HINT_REQUESTS', - 65: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS', - 66: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY', - 67: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY', - 68: 'A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR', - 69: 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0', - 70: 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1', - 71: 'A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP', - 72: 'A7XX_PERF_UFC_L0_SP_REQUESTS', - 73: 'A7XX_PERF_UFC_L0_SP_FILTER_HIT', - 74: 'A7XX_PERF_UFC_L0_SP_FILTER_MISS', - 75: 'A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES', - 76: 'A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES', - 77: 'A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES', - 78: 'A7XX_PERF_CCU_RESERVED_78', - 79: 'A7XX_PERF_CCU_RESERVED_79', - 80: 'A7XX_PERF_CCU_RESERVED_80', - 81: 'A7XX_PERF_CCU_RESERVED_81', - 82: 'A7XX_PERF_CCU_RESERVED_82', - 83: 'A7XX_PERF_CCU_RESERVED_83', - 84: 'A7XX_PERF_CCU_RESERVED_84', - 85: 'A7XX_PERF_CCU_RESERVED_85', - 86: 'A7XX_PERF_CCU_RESERVED_86', - 87: 'A7XX_PERF_CCU_RESERVED_87', - 88: 'A7XX_PERF_CCU_RESERVED_88', - 89: 'A7XX_PERF_CCU_RESERVED_89', - 90: 'A7XX_PERF_CCU_RESERVED_90', - 91: 'A7XX_PERF_CCU_RESERVED_91', - 92: 'A7XX_PERF_CCU_RESERVED_92', - 93: 'A7XX_PERF_CCU_RESERVED_93', - 94: 'A7XX_PERF_CCU_RESERVED_94', - 95: 'A7XX_PERF_CCU_RESERVED_95', - 96: 'A7XX_PERF_CCU_RESERVED_96', - 97: 'A7XX_PERF_CCU_RESERVED_97', - 98: 'A7XX_PERF_CCU_RESERVED_98', - 99: 'A7XX_PERF_CCU_RESERVED_99', - 100: 'A7XX_PERF_CCU_RESERVED_100', - 101: 'A7XX_PERF_CCU_RESERVED_101', - 102: 'A7XX_PERF_CCU_RESERVED_102', - 103: 'A7XX_PERF_CCU_RESERVED_103', - 104: 'A7XX_PERF_CCU_RESERVED_104', - 105: 'A7XX_PERF_CCU_RESERVED_105', - 106: 'A7XX_PERF_CCU_RESERVED_106', - 107: 'A7XX_PERF_CCU_RESERVED_107', - 108: 'A7XX_PERF_CCU_RESERVED_108', - 109: 'A7XX_PERF_CCU_RESERVED_109', - 110: 'A7XX_PERF_CCU_RESERVED_110', - 111: 'A7XX_PERF_CCU_RESERVED_111', - 112: 'A7XX_PERF_CCU_RESERVED_112', - 113: 'A7XX_PERF_CCU_RESERVED_113', - 114: 'A7XX_PERF_CCU_RESERVED_114', - 115: 'A7XX_PERF_CCU_RESERVED_115', - 116: 'A7XX_PERF_CCU_RESERVED_116', - 117: 'A7XX_PERF_CCU_RESERVED_117', - 118: 'A7XX_PERF_CCU_RESERVED_118', - 119: 'A7XX_PERF_CCU_RESERVED_119', - 120: 'A7XX_PERF_CCU_RESERVED_120', - 121: 'A7XX_PERF_CCU_RESERVED_121', - 122: 'A7XX_PERF_CCU_RESERVED_122', - 123: 'A7XX_PERF_CCU_RESERVED_123', - 124: 'A7XX_PERF_CCU_RESERVED_124', - 125: 'A7XX_PERF_CCU_RESERVED_125', - 126: 'A7XX_PERF_CCU_RESERVED_126', - 127: 'A7XX_PERF_CCU_RESERVED_127', - 128: 'A7XX_PERF_CRE_RESOLVE_EVENTS', - 129: 'A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS', - 130: 'A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS', - 131: 'A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT', - 132: 'A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT', - 133: 'A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS', - 134: 'A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS', - 135: 'A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS', - 136: 'A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS', -} -A7XX_PERF_CCU_NEVER_COUNT = 0 -A7XX_PERF_CCU_BUSY_CYCLES = 1 -A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 2 -A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 3 -A7XX_PERF_CCU_DEPTH_BLOCKS = 4 -A7XX_PERF_CCU_COLOR_BLOCKS = 5 -A7XX_PERF_CCU_DEPTH_BLOCK_HIT = 6 -A7XX_PERF_CCU_COLOR_BLOCK_HIT = 7 -A7XX_PERF_CCU_PARTIAL_BLOCK_READ = 8 -A7XX_PERF_CCU_GMEM_READ = 9 -A7XX_PERF_CCU_GMEM_WRITE = 10 -A7XX_PERF_CCU_2D_RD_REQ = 11 -A7XX_PERF_CCU_2D_WR_REQ = 12 -A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT = 13 -A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT = 14 -A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED = 15 -A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED = 16 -A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT = 17 -A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT = 18 -A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER = 19 -A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER = 20 -A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ = 21 -A7XX_PERF_CCU_GMEM_COLOR_READ_4AA = 22 -A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL = 23 -A7XX_PERF_CCU_COLOR_EVB_STALL = 24 -A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C = 25 -A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z = 26 -A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C = 27 -A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z = 28 -A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES = 29 -A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE = 30 -A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE = 31 -A7XX_PERF_CCU_RESERVED_32 = 32 -A7XX_PERF_CCU_RESERVED_33 = 33 -A7XX_PERF_CCU_RESERVED_34 = 34 -A7XX_PERF_CCU_RESERVED_35 = 35 -A7XX_PERF_CCU_RESERVED_36 = 36 -A7XX_PERF_CCU_RESERVED_37 = 37 -A7XX_PERF_CCU_RESERVED_38 = 38 -A7XX_PERF_CCU_RESERVED_39 = 39 -A7XX_PERF_CCU_RESERVED_40 = 40 -A7XX_PERF_CCU_RESERVED_41 = 41 -A7XX_PERF_CCU_RESERVED_42 = 42 -A7XX_PERF_CCU_RESERVED_43 = 43 -A7XX_PERF_CCU_RESERVED_44 = 44 -A7XX_PERF_CCU_RESERVED_45 = 45 -A7XX_PERF_CCU_RESERVED_46 = 46 -A7XX_PERF_CCU_RESERVED_47 = 47 -A7XX_PERF_CCU_RESERVED_48 = 48 -A7XX_PERF_CCU_RESERVED_49 = 49 -A7XX_PERF_CCU_RESERVED_50 = 50 -A7XX_PERF_CCU_RESERVED_51 = 51 -A7XX_PERF_CCU_RESERVED_52 = 52 -A7XX_PERF_CCU_RESERVED_53 = 53 -A7XX_PERF_CCU_RESERVED_54 = 54 -A7XX_PERF_CCU_RESERVED_55 = 55 -A7XX_PERF_CCU_RESERVED_56 = 56 -A7XX_PERF_CCU_RESERVED_57 = 57 -A7XX_PERF_CCU_RESERVED_58 = 58 -A7XX_PERF_CCU_RESERVED_59 = 59 -A7XX_PERF_CCU_RESERVED_60 = 60 -A7XX_PERF_CCU_RESERVED_61 = 61 -A7XX_PERF_CCU_RESERVED_62 = 62 -A7XX_PERF_CCU_RESERVED_63 = 63 -A7XX_PERF_UFC_L0_TP_HINT_REQUESTS = 64 -A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS = 65 -A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY = 66 -A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY = 67 -A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR = 68 -A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0 = 69 -A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1 = 70 -A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP = 71 -A7XX_PERF_UFC_L0_SP_REQUESTS = 72 -A7XX_PERF_UFC_L0_SP_FILTER_HIT = 73 -A7XX_PERF_UFC_L0_SP_FILTER_MISS = 74 -A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES = 75 -A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES = 76 -A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES = 77 -A7XX_PERF_CCU_RESERVED_78 = 78 -A7XX_PERF_CCU_RESERVED_79 = 79 -A7XX_PERF_CCU_RESERVED_80 = 80 -A7XX_PERF_CCU_RESERVED_81 = 81 -A7XX_PERF_CCU_RESERVED_82 = 82 -A7XX_PERF_CCU_RESERVED_83 = 83 -A7XX_PERF_CCU_RESERVED_84 = 84 -A7XX_PERF_CCU_RESERVED_85 = 85 -A7XX_PERF_CCU_RESERVED_86 = 86 -A7XX_PERF_CCU_RESERVED_87 = 87 -A7XX_PERF_CCU_RESERVED_88 = 88 -A7XX_PERF_CCU_RESERVED_89 = 89 -A7XX_PERF_CCU_RESERVED_90 = 90 -A7XX_PERF_CCU_RESERVED_91 = 91 -A7XX_PERF_CCU_RESERVED_92 = 92 -A7XX_PERF_CCU_RESERVED_93 = 93 -A7XX_PERF_CCU_RESERVED_94 = 94 -A7XX_PERF_CCU_RESERVED_95 = 95 -A7XX_PERF_CCU_RESERVED_96 = 96 -A7XX_PERF_CCU_RESERVED_97 = 97 -A7XX_PERF_CCU_RESERVED_98 = 98 -A7XX_PERF_CCU_RESERVED_99 = 99 -A7XX_PERF_CCU_RESERVED_100 = 100 -A7XX_PERF_CCU_RESERVED_101 = 101 -A7XX_PERF_CCU_RESERVED_102 = 102 -A7XX_PERF_CCU_RESERVED_103 = 103 -A7XX_PERF_CCU_RESERVED_104 = 104 -A7XX_PERF_CCU_RESERVED_105 = 105 -A7XX_PERF_CCU_RESERVED_106 = 106 -A7XX_PERF_CCU_RESERVED_107 = 107 -A7XX_PERF_CCU_RESERVED_108 = 108 -A7XX_PERF_CCU_RESERVED_109 = 109 -A7XX_PERF_CCU_RESERVED_110 = 110 -A7XX_PERF_CCU_RESERVED_111 = 111 -A7XX_PERF_CCU_RESERVED_112 = 112 -A7XX_PERF_CCU_RESERVED_113 = 113 -A7XX_PERF_CCU_RESERVED_114 = 114 -A7XX_PERF_CCU_RESERVED_115 = 115 -A7XX_PERF_CCU_RESERVED_116 = 116 -A7XX_PERF_CCU_RESERVED_117 = 117 -A7XX_PERF_CCU_RESERVED_118 = 118 -A7XX_PERF_CCU_RESERVED_119 = 119 -A7XX_PERF_CCU_RESERVED_120 = 120 -A7XX_PERF_CCU_RESERVED_121 = 121 -A7XX_PERF_CCU_RESERVED_122 = 122 -A7XX_PERF_CCU_RESERVED_123 = 123 -A7XX_PERF_CCU_RESERVED_124 = 124 -A7XX_PERF_CCU_RESERVED_125 = 125 -A7XX_PERF_CCU_RESERVED_126 = 126 -A7XX_PERF_CCU_RESERVED_127 = 127 -A7XX_PERF_CRE_RESOLVE_EVENTS = 128 -A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS = 129 -A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS = 130 -A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT = 131 -A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT = 132 -A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS = 133 -A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS = 134 -A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS = 135 -A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS = 136 -a7xx_ccu_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_lrz_perfcounter_select' -a7xx_lrz_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_LRZ_NEVER_COUNT', - 1: 'A7XX_PERF_LRZ_BUSY_CYCLES', - 2: 'A7XX_PERF_LRZ_STARVE_CYCLES_RAS', - 3: 'A7XX_PERF_LRZ_STALL_CYCLES_RB', - 4: 'A7XX_PERF_LRZ_STALL_CYCLES_VSC', - 5: 'A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE', - 6: 'A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR', - 7: 'A7XX_PERF_LRZ_STALL_CYCLES_UCHE', - 8: 'A7XX_PERF_LRZ_LRZ_READ', - 9: 'A7XX_PERF_LRZ_LRZ_WRITE', - 10: 'A7XX_PERF_LRZ_READ_LATENCY', - 11: 'A7XX_PERF_LRZ_MERGE_CACHE_UPDATING', - 12: 'A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 13: 'A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ', - 14: 'A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', - 15: 'A7XX_PERF_LRZ_FULL_8X8_TILES', - 16: 'A7XX_PERF_LRZ_PARTIAL_8X8_TILES', - 17: 'A7XX_PERF_LRZ_TILE_KILLED', - 18: 'A7XX_PERF_LRZ_TOTAL_PIXEL', - 19: 'A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 20: 'A7XX_PERF_LRZ_FEEDBACK_ACCEPT', - 21: 'A7XX_PERF_LRZ_FEEDBACK_DISCARD', - 22: 'A7XX_PERF_LRZ_FEEDBACK_STALL', - 23: 'A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE', - 24: 'A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 25: 'A7XX_PERF_LRZ_RAS_MASK_TRANS', - 26: 'A7XX_PERF_LRZ_STALL_CYCLES_MVC', - 27: 'A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS', - 28: 'A7XX_PERF_LRZ_TILE_KILLED_BY_Z', - 29: 'A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH', - 30: 'A7XX_PERF_LRZ_NUM_FLOCK', -} -A7XX_PERF_LRZ_NEVER_COUNT = 0 -A7XX_PERF_LRZ_BUSY_CYCLES = 1 -A7XX_PERF_LRZ_STARVE_CYCLES_RAS = 2 -A7XX_PERF_LRZ_STALL_CYCLES_RB = 3 -A7XX_PERF_LRZ_STALL_CYCLES_VSC = 4 -A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE = 5 -A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR = 6 -A7XX_PERF_LRZ_STALL_CYCLES_UCHE = 7 -A7XX_PERF_LRZ_LRZ_READ = 8 -A7XX_PERF_LRZ_LRZ_WRITE = 9 -A7XX_PERF_LRZ_READ_LATENCY = 10 -A7XX_PERF_LRZ_MERGE_CACHE_UPDATING = 11 -A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 12 -A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ = 13 -A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 14 -A7XX_PERF_LRZ_FULL_8X8_TILES = 15 -A7XX_PERF_LRZ_PARTIAL_8X8_TILES = 16 -A7XX_PERF_LRZ_TILE_KILLED = 17 -A7XX_PERF_LRZ_TOTAL_PIXEL = 18 -A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 19 -A7XX_PERF_LRZ_FEEDBACK_ACCEPT = 20 -A7XX_PERF_LRZ_FEEDBACK_DISCARD = 21 -A7XX_PERF_LRZ_FEEDBACK_STALL = 22 -A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 23 -A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE = 24 -A7XX_PERF_LRZ_RAS_MASK_TRANS = 25 -A7XX_PERF_LRZ_STALL_CYCLES_MVC = 26 -A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS = 27 -A7XX_PERF_LRZ_TILE_KILLED_BY_Z = 28 -A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH = 29 -A7XX_PERF_LRZ_NUM_FLOCK = 30 -a7xx_lrz_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cmp_perfcounter_select' -a7xx_cmp_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_CMPDECMP_NEVER_COUNT', - 1: 'A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB', - 2: 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 3: 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 4: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 5: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 6: 'A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST', - 7: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST', - 8: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA', - 9: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA', - 10: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 11: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 12: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 13: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 14: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 15: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 16: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 17: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 18: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 19: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 20: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 21: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 22: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 23: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 24: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 25: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 26: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 27: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 28: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 29: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 30: 'A7XX_PERF_CMPDECMP_CDP_FILTER_HIT', - 31: 'A7XX_PERF_CMPDECMP_CDP_FILTER_MISS', - 32: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT', - 33: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT', - 34: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT', - 35: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT', - 36: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT', - 37: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT', - 38: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT', - 39: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT', - 40: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT', - 41: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT', - 42: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT', - 43: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT', - 44: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT', - 45: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT', - 46: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT', - 47: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT', -} -A7XX_PERF_CMPDECMP_NEVER_COUNT = 0 -A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB = 1 -A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 2 -A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 3 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU = 4 -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 5 -A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST = 6 -A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST = 7 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA = 8 -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA = 9 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 10 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 11 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 12 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 13 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 14 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 15 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 16 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 17 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 18 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 19 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 20 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 21 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 22 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 23 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 24 -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 25 -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 26 -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 27 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 28 -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 29 -A7XX_PERF_CMPDECMP_CDP_FILTER_HIT = 30 -A7XX_PERF_CMPDECMP_CDP_FILTER_MISS = 31 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT = 32 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT = 33 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT = 34 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT = 35 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT = 36 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT = 37 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT = 38 -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT = 39 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT = 40 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT = 41 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT = 42 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT = 43 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT = 44 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT = 45 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT = 46 -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT = 47 -a7xx_cmp_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_gbif_perfcounter_select' -a7xx_gbif_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_GBIF_NEVER_COUNT', - 1: 'A7XX_PERF_GBIF_RESERVED_1', - 2: 'A7XX_PERF_GBIF_RESERVED_2', - 3: 'A7XX_PERF_GBIF_RESERVED_3', - 4: 'A7XX_PERF_GBIF_RESERVED_4', - 5: 'A7XX_PERF_GBIF_RESERVED_5', - 6: 'A7XX_PERF_GBIF_RESERVED_6', - 7: 'A7XX_PERF_GBIF_RESERVED_7', - 8: 'A7XX_PERF_GBIF_RESERVED_8', - 9: 'A7XX_PERF_GBIF_RESERVED_9', - 10: 'A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL', - 11: 'A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL', - 12: 'A7XX_PERF_GBIF_RESERVED_12', - 13: 'A7XX_PERF_GBIF_RESERVED_13', - 14: 'A7XX_PERF_GBIF_RESERVED_14', - 15: 'A7XX_PERF_GBIF_RESERVED_15', - 16: 'A7XX_PERF_GBIF_RESERVED_16', - 17: 'A7XX_PERF_GBIF_RESERVED_17', - 18: 'A7XX_PERF_GBIF_RESERVED_18', - 19: 'A7XX_PERF_GBIF_RESERVED_19', - 20: 'A7XX_PERF_GBIF_RESERVED_20', - 21: 'A7XX_PERF_GBIF_RESERVED_21', - 22: 'A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL', - 23: 'A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL', - 24: 'A7XX_PERF_GBIF_RESERVED_24', - 25: 'A7XX_PERF_GBIF_RESERVED_25', - 26: 'A7XX_PERF_GBIF_RESERVED_26', - 27: 'A7XX_PERF_GBIF_RESERVED_27', - 28: 'A7XX_PERF_GBIF_RESERVED_28', - 29: 'A7XX_PERF_GBIF_RESERVED_29', - 30: 'A7XX_PERF_GBIF_RESERVED_30', - 31: 'A7XX_PERF_GBIF_RESERVED_31', - 32: 'A7XX_PERF_GBIF_RESERVED_32', - 33: 'A7XX_PERF_GBIF_RESERVED_33', - 34: 'A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL', - 35: 'A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL', - 36: 'A7XX_PERF_GBIF_RESERVED_36', - 37: 'A7XX_PERF_GBIF_RESERVED_37', - 38: 'A7XX_PERF_GBIF_RESERVED_38', - 39: 'A7XX_PERF_GBIF_RESERVED_39', - 40: 'A7XX_PERF_GBIF_RESERVED_40', - 41: 'A7XX_PERF_GBIF_RESERVED_41', - 42: 'A7XX_PERF_GBIF_RESERVED_42', - 43: 'A7XX_PERF_GBIF_RESERVED_43', - 44: 'A7XX_PERF_GBIF_RESERVED_44', - 45: 'A7XX_PERF_GBIF_RESERVED_45', - 46: 'A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL', - 47: 'A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL', - 48: 'A7XX_PERF_GBIF_RESERVED_48', - 49: 'A7XX_PERF_GBIF_RESERVED_49', - 50: 'A7XX_PERF_GBIF_RESERVED_50', - 51: 'A7XX_PERF_GBIF_RESERVED_51', - 52: 'A7XX_PERF_GBIF_RESERVED_52', - 53: 'A7XX_PERF_GBIF_RESERVED_53', - 54: 'A7XX_PERF_GBIF_RESERVED_54', - 55: 'A7XX_PERF_GBIF_RESERVED_55', - 56: 'A7XX_PERF_GBIF_RESERVED_56', - 57: 'A7XX_PERF_GBIF_RESERVED_57', - 58: 'A7XX_PERF_GBIF_RESERVED_58', - 59: 'A7XX_PERF_GBIF_RESERVED_59', - 60: 'A7XX_PERF_GBIF_RESERVED_60', - 61: 'A7XX_PERF_GBIF_RESERVED_61', - 62: 'A7XX_PERF_GBIF_RESERVED_62', - 63: 'A7XX_PERF_GBIF_RESERVED_63', - 64: 'A7XX_PERF_GBIF_RESERVED_64', - 65: 'A7XX_PERF_GBIF_RESERVED_65', - 66: 'A7XX_PERF_GBIF_RESERVED_66', - 67: 'A7XX_PERF_GBIF_RESERVED_67', - 68: 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL', - 69: 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL', - 70: 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL', - 71: 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL', - 72: 'A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF', - 73: 'A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF', - 74: 'A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF', - 75: 'A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF', - 76: 'A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF', - 77: 'A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF', - 78: 'A7XX_PERF_GBIF_RESERVED_78', - 79: 'A7XX_PERF_GBIF_RESERVED_79', - 80: 'A7XX_PERF_GBIF_RESERVED_80', - 81: 'A7XX_PERF_GBIF_RESERVED_81', - 82: 'A7XX_PERF_GBIF_RESERVED_82', - 83: 'A7XX_PERF_GBIF_RESERVED_83', - 84: 'A7XX_PERF_GBIF_RESERVED_84', - 85: 'A7XX_PERF_GBIF_RESERVED_85', - 86: 'A7XX_PERF_GBIF_RESERVED_86', - 87: 'A7XX_PERF_GBIF_RESERVED_87', - 88: 'A7XX_PERF_GBIF_RESERVED_88', - 89: 'A7XX_PERF_GBIF_RESERVED_89', - 90: 'A7XX_PERF_GBIF_RESERVED_90', - 91: 'A7XX_PERF_GBIF_RESERVED_91', - 92: 'A7XX_PERF_GBIF_RESERVED_92', - 93: 'A7XX_PERF_GBIF_RESERVED_93', - 94: 'A7XX_PERF_GBIF_RESERVED_94', - 95: 'A7XX_PERF_GBIF_RESERVED_95', - 96: 'A7XX_PERF_GBIF_RESERVED_96', - 97: 'A7XX_PERF_GBIF_RESERVED_97', - 98: 'A7XX_PERF_GBIF_RESERVED_98', - 99: 'A7XX_PERF_GBIF_RESERVED_99', - 100: 'A7XX_PERF_GBIF_RESERVED_100', - 101: 'A7XX_PERF_GBIF_RESERVED_101', - 102: 'A7XX_PERF_GBIF_RESERVED_102', - 103: 'A7XX_PERF_GBIF_RESERVED_103', - 104: 'A7XX_PERF_GBIF_RESERVED_104', - 105: 'A7XX_PERF_GBIF_RESERVED_105', - 106: 'A7XX_PERF_GBIF_RESERVED_106', - 107: 'A7XX_PERF_GBIF_RESERVED_107', - 108: 'A7XX_PERF_GBIF_RESERVED_108', - 109: 'A7XX_PERF_GBIF_RESERVED_109', - 110: 'A7XX_PERF_GBIF_RESERVED_110', - 111: 'A7XX_PERF_GBIF_RESERVED_111', - 112: 'A7XX_PERF_GBIF_RESERVED_112', - 113: 'A7XX_PERF_GBIF_RESERVED_113', - 114: 'A7XX_PERF_GBIF_RESERVED_114', - 115: 'A7XX_PERF_GBIF_RESERVED_115', - 116: 'A7XX_PERF_GBIF_RESERVED_116', - 117: 'A7XX_PERF_GBIF_RESERVED_117', - 118: 'A7XX_PERF_GBIF_RESERVED_118', - 119: 'A7XX_PERF_GBIF_RESERVED_119', - 120: 'A7XX_PERF_GBIF_RESERVED_120', - 121: 'A7XX_PERF_GBIF_RESERVED_121', - 122: 'A7XX_PERF_GBIF_RESERVED_122', - 123: 'A7XX_PERF_GBIF_RESERVED_123', - 124: 'A7XX_PERF_GBIF_RESERVED_124', - 125: 'A7XX_PERF_GBIF_RESERVED_125', - 126: 'A7XX_PERF_GBIF_RESERVED_126', - 127: 'A7XX_PERF_GBIF_RESERVED_127', - 128: 'A7XX_PERF_GBIF_RESERVED_128', - 129: 'A7XX_PERF_GBIF_RESERVED_129', - 130: 'A7XX_PERF_GBIF_RESERVED_130', - 131: 'A7XX_PERF_GBIF_RESERVED_131', - 132: 'A7XX_PERF_GBIF_RESERVED_132', - 133: 'A7XX_PERF_GBIF_RESERVED_133', - 134: 'A7XX_PERF_GBIF_RESERVED_134', - 135: 'A7XX_PERF_GBIF_RESERVED_135', - 136: 'A7XX_PERF_GBIF_RESERVED_136', - 137: 'A7XX_PERF_GBIF_RESERVED_137', - 138: 'A7XX_PERF_GBIF_RESERVED_138', - 139: 'A7XX_PERF_GBIF_RESERVED_139', - 140: 'A7XX_PERF_GBIF_RESERVED_140', - 141: 'A7XX_PERF_GBIF_RESERVED_141', - 142: 'A7XX_PERF_GBIF_RESERVED_142', - 143: 'A7XX_PERF_GBIF_RESERVED_143', - 144: 'A7XX_PERF_GBIF_RESERVED_144', - 145: 'A7XX_PERF_GBIF_RESERVED_145', - 146: 'A7XX_PERF_GBIF_RESERVED_146', - 147: 'A7XX_PERF_GBIF_RESERVED_147', - 148: 'A7XX_PERF_GBIF_RESERVED_148', - 149: 'A7XX_PERF_GBIF_RESERVED_149', - 150: 'A7XX_PERF_GBIF_RESERVED_150', - 151: 'A7XX_PERF_GBIF_RESERVED_151', - 152: 'A7XX_PERF_GBIF_RESERVED_152', - 153: 'A7XX_PERF_GBIF_RESERVED_153', - 154: 'A7XX_PERF_GBIF_RESERVED_154', - 155: 'A7XX_PERF_GBIF_RESERVED_155', - 156: 'A7XX_PERF_GBIF_RESERVED_156', - 157: 'A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS', - 158: 'A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS', - 159: 'A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS', - 160: 'A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL', - 161: 'A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL', -} -A7XX_PERF_GBIF_NEVER_COUNT = 0 -A7XX_PERF_GBIF_RESERVED_1 = 1 -A7XX_PERF_GBIF_RESERVED_2 = 2 -A7XX_PERF_GBIF_RESERVED_3 = 3 -A7XX_PERF_GBIF_RESERVED_4 = 4 -A7XX_PERF_GBIF_RESERVED_5 = 5 -A7XX_PERF_GBIF_RESERVED_6 = 6 -A7XX_PERF_GBIF_RESERVED_7 = 7 -A7XX_PERF_GBIF_RESERVED_8 = 8 -A7XX_PERF_GBIF_RESERVED_9 = 9 -A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL = 10 -A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL = 11 -A7XX_PERF_GBIF_RESERVED_12 = 12 -A7XX_PERF_GBIF_RESERVED_13 = 13 -A7XX_PERF_GBIF_RESERVED_14 = 14 -A7XX_PERF_GBIF_RESERVED_15 = 15 -A7XX_PERF_GBIF_RESERVED_16 = 16 -A7XX_PERF_GBIF_RESERVED_17 = 17 -A7XX_PERF_GBIF_RESERVED_18 = 18 -A7XX_PERF_GBIF_RESERVED_19 = 19 -A7XX_PERF_GBIF_RESERVED_20 = 20 -A7XX_PERF_GBIF_RESERVED_21 = 21 -A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL = 22 -A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL = 23 -A7XX_PERF_GBIF_RESERVED_24 = 24 -A7XX_PERF_GBIF_RESERVED_25 = 25 -A7XX_PERF_GBIF_RESERVED_26 = 26 -A7XX_PERF_GBIF_RESERVED_27 = 27 -A7XX_PERF_GBIF_RESERVED_28 = 28 -A7XX_PERF_GBIF_RESERVED_29 = 29 -A7XX_PERF_GBIF_RESERVED_30 = 30 -A7XX_PERF_GBIF_RESERVED_31 = 31 -A7XX_PERF_GBIF_RESERVED_32 = 32 -A7XX_PERF_GBIF_RESERVED_33 = 33 -A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL = 34 -A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL = 35 -A7XX_PERF_GBIF_RESERVED_36 = 36 -A7XX_PERF_GBIF_RESERVED_37 = 37 -A7XX_PERF_GBIF_RESERVED_38 = 38 -A7XX_PERF_GBIF_RESERVED_39 = 39 -A7XX_PERF_GBIF_RESERVED_40 = 40 -A7XX_PERF_GBIF_RESERVED_41 = 41 -A7XX_PERF_GBIF_RESERVED_42 = 42 -A7XX_PERF_GBIF_RESERVED_43 = 43 -A7XX_PERF_GBIF_RESERVED_44 = 44 -A7XX_PERF_GBIF_RESERVED_45 = 45 -A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL = 46 -A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL = 47 -A7XX_PERF_GBIF_RESERVED_48 = 48 -A7XX_PERF_GBIF_RESERVED_49 = 49 -A7XX_PERF_GBIF_RESERVED_50 = 50 -A7XX_PERF_GBIF_RESERVED_51 = 51 -A7XX_PERF_GBIF_RESERVED_52 = 52 -A7XX_PERF_GBIF_RESERVED_53 = 53 -A7XX_PERF_GBIF_RESERVED_54 = 54 -A7XX_PERF_GBIF_RESERVED_55 = 55 -A7XX_PERF_GBIF_RESERVED_56 = 56 -A7XX_PERF_GBIF_RESERVED_57 = 57 -A7XX_PERF_GBIF_RESERVED_58 = 58 -A7XX_PERF_GBIF_RESERVED_59 = 59 -A7XX_PERF_GBIF_RESERVED_60 = 60 -A7XX_PERF_GBIF_RESERVED_61 = 61 -A7XX_PERF_GBIF_RESERVED_62 = 62 -A7XX_PERF_GBIF_RESERVED_63 = 63 -A7XX_PERF_GBIF_RESERVED_64 = 64 -A7XX_PERF_GBIF_RESERVED_65 = 65 -A7XX_PERF_GBIF_RESERVED_66 = 66 -A7XX_PERF_GBIF_RESERVED_67 = 67 -A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL = 68 -A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL = 69 -A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL = 70 -A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL = 71 -A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF = 72 -A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF = 73 -A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF = 74 -A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF = 75 -A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF = 76 -A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF = 77 -A7XX_PERF_GBIF_RESERVED_78 = 78 -A7XX_PERF_GBIF_RESERVED_79 = 79 -A7XX_PERF_GBIF_RESERVED_80 = 80 -A7XX_PERF_GBIF_RESERVED_81 = 81 -A7XX_PERF_GBIF_RESERVED_82 = 82 -A7XX_PERF_GBIF_RESERVED_83 = 83 -A7XX_PERF_GBIF_RESERVED_84 = 84 -A7XX_PERF_GBIF_RESERVED_85 = 85 -A7XX_PERF_GBIF_RESERVED_86 = 86 -A7XX_PERF_GBIF_RESERVED_87 = 87 -A7XX_PERF_GBIF_RESERVED_88 = 88 -A7XX_PERF_GBIF_RESERVED_89 = 89 -A7XX_PERF_GBIF_RESERVED_90 = 90 -A7XX_PERF_GBIF_RESERVED_91 = 91 -A7XX_PERF_GBIF_RESERVED_92 = 92 -A7XX_PERF_GBIF_RESERVED_93 = 93 -A7XX_PERF_GBIF_RESERVED_94 = 94 -A7XX_PERF_GBIF_RESERVED_95 = 95 -A7XX_PERF_GBIF_RESERVED_96 = 96 -A7XX_PERF_GBIF_RESERVED_97 = 97 -A7XX_PERF_GBIF_RESERVED_98 = 98 -A7XX_PERF_GBIF_RESERVED_99 = 99 -A7XX_PERF_GBIF_RESERVED_100 = 100 -A7XX_PERF_GBIF_RESERVED_101 = 101 -A7XX_PERF_GBIF_RESERVED_102 = 102 -A7XX_PERF_GBIF_RESERVED_103 = 103 -A7XX_PERF_GBIF_RESERVED_104 = 104 -A7XX_PERF_GBIF_RESERVED_105 = 105 -A7XX_PERF_GBIF_RESERVED_106 = 106 -A7XX_PERF_GBIF_RESERVED_107 = 107 -A7XX_PERF_GBIF_RESERVED_108 = 108 -A7XX_PERF_GBIF_RESERVED_109 = 109 -A7XX_PERF_GBIF_RESERVED_110 = 110 -A7XX_PERF_GBIF_RESERVED_111 = 111 -A7XX_PERF_GBIF_RESERVED_112 = 112 -A7XX_PERF_GBIF_RESERVED_113 = 113 -A7XX_PERF_GBIF_RESERVED_114 = 114 -A7XX_PERF_GBIF_RESERVED_115 = 115 -A7XX_PERF_GBIF_RESERVED_116 = 116 -A7XX_PERF_GBIF_RESERVED_117 = 117 -A7XX_PERF_GBIF_RESERVED_118 = 118 -A7XX_PERF_GBIF_RESERVED_119 = 119 -A7XX_PERF_GBIF_RESERVED_120 = 120 -A7XX_PERF_GBIF_RESERVED_121 = 121 -A7XX_PERF_GBIF_RESERVED_122 = 122 -A7XX_PERF_GBIF_RESERVED_123 = 123 -A7XX_PERF_GBIF_RESERVED_124 = 124 -A7XX_PERF_GBIF_RESERVED_125 = 125 -A7XX_PERF_GBIF_RESERVED_126 = 126 -A7XX_PERF_GBIF_RESERVED_127 = 127 -A7XX_PERF_GBIF_RESERVED_128 = 128 -A7XX_PERF_GBIF_RESERVED_129 = 129 -A7XX_PERF_GBIF_RESERVED_130 = 130 -A7XX_PERF_GBIF_RESERVED_131 = 131 -A7XX_PERF_GBIF_RESERVED_132 = 132 -A7XX_PERF_GBIF_RESERVED_133 = 133 -A7XX_PERF_GBIF_RESERVED_134 = 134 -A7XX_PERF_GBIF_RESERVED_135 = 135 -A7XX_PERF_GBIF_RESERVED_136 = 136 -A7XX_PERF_GBIF_RESERVED_137 = 137 -A7XX_PERF_GBIF_RESERVED_138 = 138 -A7XX_PERF_GBIF_RESERVED_139 = 139 -A7XX_PERF_GBIF_RESERVED_140 = 140 -A7XX_PERF_GBIF_RESERVED_141 = 141 -A7XX_PERF_GBIF_RESERVED_142 = 142 -A7XX_PERF_GBIF_RESERVED_143 = 143 -A7XX_PERF_GBIF_RESERVED_144 = 144 -A7XX_PERF_GBIF_RESERVED_145 = 145 -A7XX_PERF_GBIF_RESERVED_146 = 146 -A7XX_PERF_GBIF_RESERVED_147 = 147 -A7XX_PERF_GBIF_RESERVED_148 = 148 -A7XX_PERF_GBIF_RESERVED_149 = 149 -A7XX_PERF_GBIF_RESERVED_150 = 150 -A7XX_PERF_GBIF_RESERVED_151 = 151 -A7XX_PERF_GBIF_RESERVED_152 = 152 -A7XX_PERF_GBIF_RESERVED_153 = 153 -A7XX_PERF_GBIF_RESERVED_154 = 154 -A7XX_PERF_GBIF_RESERVED_155 = 155 -A7XX_PERF_GBIF_RESERVED_156 = 156 -A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS = 157 -A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS = 158 -A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS = 159 -A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL = 160 -A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL = 161 -a7xx_gbif_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_ufc_perfcounter_select' -a7xx_ufc_perfcounter_select__enumvalues = { - 0: 'A7XX_PERF_UFC_NEVER_COUNT', - 1: 'A7XX_PERF_UFC_BUSY_CYCLES', - 2: 'A7XX_PERF_UFC_READ_DATA_VBIF', - 3: 'A7XX_PERF_UFC_WRITE_DATA_VBIF', - 4: 'A7XX_PERF_UFC_READ_REQUEST_VBIF', - 5: 'A7XX_PERF_UFC_WRITE_REQUEST_VBIF', - 6: 'A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH', - 7: 'A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH', - 8: 'A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH', - 9: 'A7XX_PERF_UFC_MAIN_HIT_UBWC_READ', - 10: 'A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE', - 11: 'A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH', - 12: 'A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH', - 13: 'A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH', - 14: 'A7XX_PERF_UFC_MAIN_MISS_UBWC_READ', - 15: 'A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE', - 16: 'A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY', - 17: 'A7XX_PERF_UFC_MAIN_UBWC_RD_RDY', - 18: 'A7XX_PERF_UFC_MAIN_TP_RD_NRDY', - 19: 'A7XX_PERF_UFC_MAIN_TP_RD_RDY', - 20: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD', - 21: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA', - 22: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA', - 23: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG', - 24: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN', - 25: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT', - 26: 'A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES', - 27: 'A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES', - 28: 'A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES', - 29: 'A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES', - 30: 'A7XX_PERF_UFC_EVICTION_STALLED_CYCLES', - 31: 'A7XX_PERF_UFC_LOCK_STALLED_CYCLES', - 32: 'A7XX_PERF_UFC_MISS_LATENCY_CYCLES', - 33: 'A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', - 34: 'A7XX_PERF_UFC_L1_CRE_REQUESTS', - 35: 'A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES', - 36: 'A7XX_PERF_UFC_L1_CRE_FILTER_HIT', - 37: 'A7XX_PERF_UFC_L1_CRE_FILTER_MISS', - 38: 'A7XX_PERF_UFC_L1_SP_REQUESTS', - 39: 'A7XX_PERF_UFC_L1_SP_STALLED_CYCLES', - 40: 'A7XX_PERF_UFC_L1_SP_FILTER_HIT', - 41: 'A7XX_PERF_UFC_L1_SP_FILTER_MISS', - 42: 'A7XX_PERF_UFC_L1_TP_HINT_REQUESTS', - 43: 'A7XX_PERF_UFC_L1_TP_STALLED_CYCLES', - 44: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS', - 45: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY', - 46: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY', -} -A7XX_PERF_UFC_NEVER_COUNT = 0 -A7XX_PERF_UFC_BUSY_CYCLES = 1 -A7XX_PERF_UFC_READ_DATA_VBIF = 2 -A7XX_PERF_UFC_WRITE_DATA_VBIF = 3 -A7XX_PERF_UFC_READ_REQUEST_VBIF = 4 -A7XX_PERF_UFC_WRITE_REQUEST_VBIF = 5 -A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH = 6 -A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH = 7 -A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH = 8 -A7XX_PERF_UFC_MAIN_HIT_UBWC_READ = 9 -A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE = 10 -A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH = 11 -A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH = 12 -A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH = 13 -A7XX_PERF_UFC_MAIN_MISS_UBWC_READ = 14 -A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE = 15 -A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY = 16 -A7XX_PERF_UFC_MAIN_UBWC_RD_RDY = 17 -A7XX_PERF_UFC_MAIN_TP_RD_NRDY = 18 -A7XX_PERF_UFC_MAIN_TP_RD_RDY = 19 -A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD = 20 -A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA = 21 -A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA = 22 -A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG = 23 -A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN = 24 -A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT = 25 -A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES = 26 -A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES = 27 -A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES = 28 -A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES = 29 -A7XX_PERF_UFC_EVICTION_STALLED_CYCLES = 30 -A7XX_PERF_UFC_LOCK_STALLED_CYCLES = 31 -A7XX_PERF_UFC_MISS_LATENCY_CYCLES = 32 -A7XX_PERF_UFC_MISS_LATENCY_SAMPLES = 33 -A7XX_PERF_UFC_L1_CRE_REQUESTS = 34 -A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES = 35 -A7XX_PERF_UFC_L1_CRE_FILTER_HIT = 36 -A7XX_PERF_UFC_L1_CRE_FILTER_MISS = 37 -A7XX_PERF_UFC_L1_SP_REQUESTS = 38 -A7XX_PERF_UFC_L1_SP_STALLED_CYCLES = 39 -A7XX_PERF_UFC_L1_SP_FILTER_HIT = 40 -A7XX_PERF_UFC_L1_SP_FILTER_MISS = 41 -A7XX_PERF_UFC_L1_TP_HINT_REQUESTS = 42 -A7XX_PERF_UFC_L1_TP_STALLED_CYCLES = 43 -A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS = 44 -A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY = 45 -A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY = 46 -a7xx_ufc_perfcounter_select = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_sequenced_thread_dist' -a6xx_sequenced_thread_dist__enumvalues = { - 0: 'DIST_SCREEN_COORD', - 1: 'DIST_ALL_TO_RB0', -} -DIST_SCREEN_COORD = 0 -DIST_ALL_TO_RB0 = 1 -a6xx_sequenced_thread_dist = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_single_prim_mode' -a6xx_single_prim_mode__enumvalues = { - 0: 'NO_FLUSH', - 1: 'FLUSH_PER_OVERLAP_AND_OVERWRITE', - 3: 'FLUSH_PER_OVERLAP', -} -NO_FLUSH = 0 -FLUSH_PER_OVERLAP_AND_OVERWRITE = 1 -FLUSH_PER_OVERLAP = 3 -a6xx_single_prim_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_raster_mode' -a6xx_raster_mode__enumvalues = { - 0: 'TYPE_TILED', - 1: 'TYPE_WRITER', -} -TYPE_TILED = 0 -TYPE_WRITER = 1 -a6xx_raster_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_raster_direction' -a6xx_raster_direction__enumvalues = { - 0: 'LR_TB', - 1: 'RL_TB', - 2: 'LR_BT', - 3: 'RB_BT', -} -LR_TB = 0 -RL_TB = 1 -LR_BT = 2 -RB_BT = 3 -a6xx_raster_direction = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_render_mode' -a6xx_render_mode__enumvalues = { - 0: 'RENDERING_PASS', - 1: 'BINNING_PASS', -} -RENDERING_PASS = 0 -BINNING_PASS = 1 -a6xx_render_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_buffers_location' -a6xx_buffers_location__enumvalues = { - 0: 'BUFFERS_IN_GMEM', - 3: 'BUFFERS_IN_SYSMEM', -} -BUFFERS_IN_GMEM = 0 -BUFFERS_IN_SYSMEM = 3 -a6xx_buffers_location = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_lrz_dir_status' -a6xx_lrz_dir_status__enumvalues = { - 1: 'LRZ_DIR_LE', - 2: 'LRZ_DIR_GE', - 3: 'LRZ_DIR_INVALID', -} -LRZ_DIR_LE = 1 -LRZ_DIR_GE = 2 -LRZ_DIR_INVALID = 3 -a6xx_lrz_dir_status = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_fragcoord_sample_mode' -a6xx_fragcoord_sample_mode__enumvalues = { - 0: 'FRAGCOORD_CENTER', - 3: 'FRAGCOORD_SAMPLE', -} -FRAGCOORD_CENTER = 0 -FRAGCOORD_SAMPLE = 3 -a6xx_fragcoord_sample_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_rotation' -a6xx_rotation__enumvalues = { - 0: 'ROTATE_0', - 1: 'ROTATE_90', - 2: 'ROTATE_180', - 3: 'ROTATE_270', - 4: 'ROTATE_HFLIP', - 5: 'ROTATE_VFLIP', -} -ROTATE_0 = 0 -ROTATE_90 = 1 -ROTATE_180 = 2 -ROTATE_270 = 3 -ROTATE_HFLIP = 4 -ROTATE_VFLIP = 5 -a6xx_rotation = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_ccu_cache_size' -a6xx_ccu_cache_size__enumvalues = { - 0: 'CCU_CACHE_SIZE_FULL', - 1: 'CCU_CACHE_SIZE_HALF', - 2: 'CCU_CACHE_SIZE_QUARTER', - 3: 'CCU_CACHE_SIZE_EIGHTH', -} -CCU_CACHE_SIZE_FULL = 0 -CCU_CACHE_SIZE_HALF = 1 -CCU_CACHE_SIZE_QUARTER = 2 -CCU_CACHE_SIZE_EIGHTH = 3 -a6xx_ccu_cache_size = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_varying_interp_mode' -a6xx_varying_interp_mode__enumvalues = { - 0: 'INTERP_SMOOTH', - 1: 'INTERP_FLAT', - 2: 'INTERP_ZERO', - 3: 'INTERP_ONE', -} -INTERP_SMOOTH = 0 -INTERP_FLAT = 1 -INTERP_ZERO = 2 -INTERP_ONE = 3 -a6xx_varying_interp_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_varying_ps_repl_mode' -a6xx_varying_ps_repl_mode__enumvalues = { - 0: 'PS_REPL_NONE', - 1: 'PS_REPL_S', - 2: 'PS_REPL_T', - 3: 'PS_REPL_ONE_MINUS_T', -} -PS_REPL_NONE = 0 -PS_REPL_S = 1 -PS_REPL_T = 2 -PS_REPL_ONE_MINUS_T = 3 -a6xx_varying_ps_repl_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_threadsize' -a6xx_threadsize__enumvalues = { - 0: 'THREAD64', - 1: 'THREAD128', -} -THREAD64 = 0 -THREAD128 = 1 -a6xx_threadsize = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_bindless_descriptor_size' -a6xx_bindless_descriptor_size__enumvalues = { - 1: 'BINDLESS_DESCRIPTOR_16B', - 3: 'BINDLESS_DESCRIPTOR_64B', -} -BINDLESS_DESCRIPTOR_16B = 1 -BINDLESS_DESCRIPTOR_64B = 3 -a6xx_bindless_descriptor_size = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_isam_mode' -a6xx_isam_mode__enumvalues = { - 1: 'ISAMMODE_CL', - 2: 'ISAMMODE_GL', -} -ISAMMODE_CL = 1 -ISAMMODE_GL = 2 -a6xx_isam_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a7xx_cs_yalign' -a7xx_cs_yalign__enumvalues = { - 8: 'CS_YALIGN_1', - 4: 'CS_YALIGN_2', - 2: 'CS_YALIGN_4', - 1: 'CS_YALIGN_8', -} -CS_YALIGN_1 = 8 -CS_YALIGN_2 = 4 -CS_YALIGN_4 = 2 -CS_YALIGN_8 = 1 -a7xx_cs_yalign = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_filter' -a6xx_tex_filter__enumvalues = { - 0: 'A6XX_TEX_NEAREST', - 1: 'A6XX_TEX_LINEAR', - 2: 'A6XX_TEX_ANISO', - 3: 'A6XX_TEX_CUBIC', -} -A6XX_TEX_NEAREST = 0 -A6XX_TEX_LINEAR = 1 -A6XX_TEX_ANISO = 2 -A6XX_TEX_CUBIC = 3 -a6xx_tex_filter = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_clamp' -a6xx_tex_clamp__enumvalues = { - 0: 'A6XX_TEX_REPEAT', - 1: 'A6XX_TEX_CLAMP_TO_EDGE', - 2: 'A6XX_TEX_MIRROR_REPEAT', - 3: 'A6XX_TEX_CLAMP_TO_BORDER', - 4: 'A6XX_TEX_MIRROR_CLAMP', -} -A6XX_TEX_REPEAT = 0 -A6XX_TEX_CLAMP_TO_EDGE = 1 -A6XX_TEX_MIRROR_REPEAT = 2 -A6XX_TEX_CLAMP_TO_BORDER = 3 -A6XX_TEX_MIRROR_CLAMP = 4 -a6xx_tex_clamp = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_aniso' -a6xx_tex_aniso__enumvalues = { - 0: 'A6XX_TEX_ANISO_1', - 1: 'A6XX_TEX_ANISO_2', - 2: 'A6XX_TEX_ANISO_4', - 3: 'A6XX_TEX_ANISO_8', - 4: 'A6XX_TEX_ANISO_16', -} -A6XX_TEX_ANISO_1 = 0 -A6XX_TEX_ANISO_2 = 1 -A6XX_TEX_ANISO_4 = 2 -A6XX_TEX_ANISO_8 = 3 -A6XX_TEX_ANISO_16 = 4 -a6xx_tex_aniso = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_reduction_mode' -a6xx_reduction_mode__enumvalues = { - 0: 'A6XX_REDUCTION_MODE_AVERAGE', - 1: 'A6XX_REDUCTION_MODE_MIN', - 2: 'A6XX_REDUCTION_MODE_MAX', -} -A6XX_REDUCTION_MODE_AVERAGE = 0 -A6XX_REDUCTION_MODE_MIN = 1 -A6XX_REDUCTION_MODE_MAX = 2 -a6xx_reduction_mode = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_swiz' -a6xx_tex_swiz__enumvalues = { - 0: 'A6XX_TEX_X', - 1: 'A6XX_TEX_Y', - 2: 'A6XX_TEX_Z', - 3: 'A6XX_TEX_W', - 4: 'A6XX_TEX_ZERO', - 5: 'A6XX_TEX_ONE', -} -A6XX_TEX_X = 0 -A6XX_TEX_Y = 1 -A6XX_TEX_Z = 2 -A6XX_TEX_W = 3 -A6XX_TEX_ZERO = 4 -A6XX_TEX_ONE = 5 -a6xx_tex_swiz = ctypes.c_uint32 # enum - -# values for enumeration 'a6xx_tex_type' -a6xx_tex_type__enumvalues = { - 0: 'A6XX_TEX_1D', - 1: 'A6XX_TEX_2D', - 2: 'A6XX_TEX_CUBE', - 3: 'A6XX_TEX_3D', - 4: 'A6XX_TEX_BUFFER', -} -A6XX_TEX_1D = 0 -A6XX_TEX_2D = 1 -A6XX_TEX_CUBE = 2 -A6XX_TEX_3D = 3 -A6XX_TEX_BUFFER = 4 -a6xx_tex_type = ctypes.c_uint32 # enum -__all__ = \ - ['A2XX', 'A3XX', 'A4XX', 'A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE', - 'A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE', - 'A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK', - 'A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT', - 'A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK', - 'A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT', - 'A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK', - 'A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK', - 'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT', 'A5XX', - 'A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK', - 'A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT', - 'A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK', - 'A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT', - 'A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK', - 'A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK', - 'A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT', - 'A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK', - 'A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT', - 'A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK', - 'A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK', - 'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT', 'A6XX', - 'A6XX_CP_2D_EVENT_END_STATE_ID__MASK', - 'A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT', - 'A6XX_CP_2D_EVENT_START_STATE_ID__MASK', - 'A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT', - 'A6XX_CP_APRIV_CNTL_CDREAD', 'A6XX_CP_APRIV_CNTL_CDWRITE', - 'A6XX_CP_APRIV_CNTL_ICACHE', 'A6XX_CP_APRIV_CNTL_RBFETCH', - 'A6XX_CP_APRIV_CNTL_RBPRIVLEVEL', 'A6XX_CP_APRIV_CNTL_RBRPWB', - 'A6XX_CP_CP2GMU_STATUS_IFPC', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK', - 'A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT', - 'A6XX_CP_EVENT_END_STATE_ID__MASK', - 'A6XX_CP_EVENT_END_STATE_ID__SHIFT', - 'A6XX_CP_EVENT_START_STATE_ID__MASK', - 'A6XX_CP_EVENT_START_STATE_ID__SHIFT', 'A6XX_CP_INT_CP_AHB_ERROR', - 'A6XX_CP_INT_CP_HW_FAULT_ERROR', - 'A6XX_CP_INT_CP_HW_FAULT_ERROR_BV', - 'A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC', - 'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR', - 'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV', - 'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC', - 'A6XX_CP_INT_CP_OPCODE_ERROR', 'A6XX_CP_INT_CP_OPCODE_ERROR_BV', - 'A6XX_CP_INT_CP_OPCODE_ERROR_LPAC', - 'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR', - 'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV', - 'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC', - 'A6XX_CP_INT_CP_UCODE_ERROR', 'A6XX_CP_INT_CP_UCODE_ERROR_BV', - 'A6XX_CP_INT_CP_UCODE_ERROR_LPAC', - 'A6XX_CP_INT_CP_VSD_PARITY_ERROR', - 'A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN', - 'A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN', - 'A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE', - 'A6XX_CP_PROTECT_REG_BASE_ADDR__MASK', - 'A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT', - 'A6XX_CP_PROTECT_REG_MASK_LEN__MASK', - 'A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT', 'A6XX_CP_PROTECT_REG_READ', - 'A6XX_CP_REG_TEST_0_BIT__MASK', 'A6XX_CP_REG_TEST_0_BIT__SHIFT', - 'A6XX_CP_REG_TEST_0_PRED_BIT__MASK', - 'A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT', - 'A6XX_CP_REG_TEST_0_PRED_UPDATE', 'A6XX_CP_REG_TEST_0_REG__MASK', - 'A6XX_CP_REG_TEST_0_REG__SHIFT', - 'A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK', - 'A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT', - 'A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME', - 'A6XX_CP_REG_TEST_0_SOURCE__MASK', - 'A6XX_CP_REG_TEST_0_SOURCE__SHIFT', - 'A6XX_CP_ROQ_AVAIL_IB1_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_IB2_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_MRB_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_RB_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_SDS_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT', - 'A6XX_CP_ROQ_AVAIL_VSD_REM__MASK', - 'A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT', - 'A6XX_CP_ROQ_IB1_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_IB1_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_IB2_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_IB2_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_MRB_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_MRB_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_RB_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_RB_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_SDS_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_SDS_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT', - 'A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK', - 'A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT', - 'A6XX_CP_ROQ_VSD_STAT_RPTR__MASK', - 'A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT', - 'A6XX_CP_ROQ_VSD_STAT_WPTR__MASK', - 'A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT', - 'A6XX_CP_SET_MARKER_0_MARKER__MASK', - 'A6XX_CP_SET_MARKER_0_MARKER__SHIFT', - 'A6XX_CP_SET_MARKER_0_MODE__MASK', - 'A6XX_CP_SET_MARKER_0_MODE__SHIFT', - 'A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK', - 'A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT', - 'A6XX_CP_SET_PSEUDO_REG__1_LO__MASK', - 'A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT', - 'A6XX_CP_SET_PSEUDO_REG__2_HI__MASK', - 'A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK', - 'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT', - 'A6XX_DBGBUS_A2D', 'A6XX_DBGBUS_CCUFCHE', 'A6XX_DBGBUS_CCU_0', - 'A6XX_DBGBUS_CCU_1', 'A6XX_DBGBUS_CCU_2', 'A6XX_DBGBUS_COM', - 'A6XX_DBGBUS_CP', 'A6XX_DBGBUS_CX', 'A6XX_DBGBUS_DBGC', - 'A6XX_DBGBUS_DCS', 'A6XX_DBGBUS_DPM', 'A6XX_DBGBUS_GBIF_GX', - 'A6XX_DBGBUS_GMU_CX', 'A6XX_DBGBUS_GMU_GX', 'A6XX_DBGBUS_GPC', - 'A6XX_DBGBUS_HLSQ', 'A6XX_DBGBUS_HLSQ_SPTP', 'A6XX_DBGBUS_LARC', - 'A6XX_DBGBUS_LRZ', 'A6XX_DBGBUS_PC', 'A6XX_DBGBUS_RAS', - 'A6XX_DBGBUS_RBBM', 'A6XX_DBGBUS_RBP', 'A6XX_DBGBUS_RB_0', - 'A6XX_DBGBUS_RB_1', 'A6XX_DBGBUS_RB_2', 'A6XX_DBGBUS_SPTP_0', - 'A6XX_DBGBUS_SPTP_1', 'A6XX_DBGBUS_SPTP_2', 'A6XX_DBGBUS_SPTP_3', - 'A6XX_DBGBUS_SPTP_4', 'A6XX_DBGBUS_SPTP_5', 'A6XX_DBGBUS_SP_0', - 'A6XX_DBGBUS_SP_1', 'A6XX_DBGBUS_SP_2', 'A6XX_DBGBUS_TESS', - 'A6XX_DBGBUS_TPFCHE', 'A6XX_DBGBUS_TPL1_0', 'A6XX_DBGBUS_TPL1_1', - 'A6XX_DBGBUS_TPL1_2', 'A6XX_DBGBUS_TPL1_3', 'A6XX_DBGBUS_TPL1_4', - 'A6XX_DBGBUS_TPL1_5', 'A6XX_DBGBUS_TSE', 'A6XX_DBGBUS_UCHE', - 'A6XX_DBGBUS_UCHE_WRAPPER', 'A6XX_DBGBUS_VBIF', - 'A6XX_DBGBUS_VFDP', 'A6XX_DBGBUS_VFD_0', 'A6XX_DBGBUS_VFD_1', - 'A6XX_DBGBUS_VFD_2', 'A6XX_DBGBUS_VFD_3', 'A6XX_DBGBUS_VFD_4', - 'A6XX_DBGBUS_VFD_5', 'A6XX_DBGBUS_VPC', 'A6XX_DBGBUS_VSC', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK', - 'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK', - 'A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK', - 'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT', - 'A6XX_EARLY_LRZ_LATE_Z', 'A6XX_EARLY_Z', - 'A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_D24S8', - 'A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN', - 'A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_SCISSOR', - 'A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK30', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK', - 'A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT', - 'A6XX_GRAS_2D_DST_BR_X__MASK', 'A6XX_GRAS_2D_DST_BR_X__SHIFT', - 'A6XX_GRAS_2D_DST_BR_Y__MASK', 'A6XX_GRAS_2D_DST_BR_Y__SHIFT', - 'A6XX_GRAS_2D_DST_TL_X__MASK', 'A6XX_GRAS_2D_DST_TL_X__SHIFT', - 'A6XX_GRAS_2D_DST_TL_Y__MASK', 'A6XX_GRAS_2D_DST_TL_Y__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK', - 'A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT', - 'A6XX_GRAS_2D_SRC_BR_X__MASK', 'A6XX_GRAS_2D_SRC_BR_X__SHIFT', - 'A6XX_GRAS_2D_SRC_BR_Y__MASK', 'A6XX_GRAS_2D_SRC_BR_Y__SHIFT', - 'A6XX_GRAS_2D_SRC_TL_X__MASK', 'A6XX_GRAS_2D_SRC_TL_X__SHIFT', - 'A6XX_GRAS_2D_SRC_TL_Y__MASK', 'A6XX_GRAS_2D_SRC_TL_Y__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_BINH__MASK', - 'A6XX_GRAS_BIN_CONTROL_BINH__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_BINW__MASK', - 'A6XX_GRAS_BIN_CONTROL_BINW__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK', - 'A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS', - 'A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK', - 'A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK', - 'A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT', - 'A6XX_GRAS_BIN_CONTROL_UNK27', 'A6XX_GRAS_CL_CNTL_CLIP_DISABLE', - 'A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE', - 'A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE', - 'A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE', - 'A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z', - 'A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE', - 'A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE', - 'A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK', - 'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT', - 'A6XX_GRAS_CL_VPORT_XOFFSET__MASK', - 'A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT', - 'A6XX_GRAS_CL_VPORT_XSCALE__MASK', - 'A6XX_GRAS_CL_VPORT_XSCALE__SHIFT', - 'A6XX_GRAS_CL_VPORT_YOFFSET__MASK', - 'A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT', - 'A6XX_GRAS_CL_VPORT_YSCALE__MASK', - 'A6XX_GRAS_CL_VPORT_YSCALE__SHIFT', - 'A6XX_GRAS_CL_VPORT_ZOFFSET__MASK', - 'A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT', - 'A6XX_GRAS_CL_VPORT_ZSCALE__MASK', - 'A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT', - 'A6XX_GRAS_CL_Z_CLAMP_MAX__MASK', - 'A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT', - 'A6XX_GRAS_CL_Z_CLAMP_MIN__MASK', - 'A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT', - 'A6XX_GRAS_CNTL_COORD_MASK__MASK', - 'A6XX_GRAS_CNTL_COORD_MASK__SHIFT', - 'A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID', - 'A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL', - 'A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE', - 'A6XX_GRAS_CNTL_IJ_PERSP_CENTROID', - 'A6XX_GRAS_CNTL_IJ_PERSP_PIXEL', 'A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE', - 'A6XX_GRAS_CNTL_UNK10', 'A6XX_GRAS_CNTL_UNK11', - 'A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS', - 'A6XX_GRAS_DBG_ECO_CNTL_UNK7', - 'A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE', - 'A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK', - 'A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT', - 'A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK', - 'A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT', - 'A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER', - 'A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW', - 'A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK', - 'A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT', - 'A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK', - 'A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT', - 'A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER', - 'A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK', - 'A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_GRAS_LRZ_CNTL_DIR_WRITE', 'A6XX_GRAS_LRZ_CNTL_DIR__MASK', - 'A6XX_GRAS_LRZ_CNTL_DIR__SHIFT', - 'A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR', - 'A6XX_GRAS_LRZ_CNTL_ENABLE', 'A6XX_GRAS_LRZ_CNTL_FC_ENABLE', - 'A6XX_GRAS_LRZ_CNTL_GREATER', 'A6XX_GRAS_LRZ_CNTL_LRZ_WRITE', - 'A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE', - 'A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK', - 'A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT', - 'A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK', - 'A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT', - 'A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK', - 'A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT', - 'A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK', - 'A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT', - 'A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID', - 'A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_GRAS_RAS_MSAA_CNTL_UNK2', 'A6XX_GRAS_RAS_MSAA_CNTL_UNK3', - 'A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE', - 'A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE', - 'A6XX_GRAS_SAMPLE_CONFIG_UNK0', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK', - 'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT', - 'A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK', - 'A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT', - 'A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN', - 'A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK', - 'A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT', - 'A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK', - 'A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT', - 'A6XX_GRAS_SC_CNTL_ROTATION__MASK', - 'A6XX_GRAS_SC_CNTL_ROTATION__SHIFT', - 'A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK', - 'A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT', - 'A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK', - 'A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT', - 'A6XX_GRAS_SC_CNTL_UNK9', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK', - 'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK', - 'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK', - 'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT', - 'A6XX_GRAS_SU_CNTL_CULL_BACK', 'A6XX_GRAS_SU_CNTL_CULL_FRONT', - 'A6XX_GRAS_SU_CNTL_FRONT_CW', - 'A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK', - 'A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT', - 'A6XX_GRAS_SU_CNTL_LINE_MODE__MASK', - 'A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT', - 'A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE', - 'A6XX_GRAS_SU_CNTL_POLY_OFFSET', - 'A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR', - 'A6XX_GRAS_SU_CNTL_UNK12', 'A6XX_GRAS_SU_CNTL_UNK15__MASK', - 'A6XX_GRAS_SU_CNTL_UNK15__SHIFT', 'A6XX_GRAS_SU_CNTL_UNK20__MASK', - 'A6XX_GRAS_SU_CNTL_UNK20__SHIFT', - 'A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK', - 'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT', - 'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3', - 'A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE', - 'A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK', - 'A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT', - 'A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN', - 'A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0', - 'A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK', - 'A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT', - 'A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK', - 'A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT', - 'A6XX_GRAS_SU_POINT_SIZE__MASK', 'A6XX_GRAS_SU_POINT_SIZE__SHIFT', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK', - 'A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT', - 'A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK', - 'A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT', - 'A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE', - 'A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK', - 'A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT', - 'A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK', - 'A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT', - 'A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER', - 'A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW', - 'A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK', - 'A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT', - 'A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT', - 'A6XX_HLSQ_BACKEND_META', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_HLSQ_CHUNK_CPS_RAM', 'A6XX_HLSQ_CHUNK_CPS_RAM_TAG', - 'A6XX_HLSQ_CHUNK_CVS_RAM', 'A6XX_HLSQ_CHUNK_CVS_RAM_TAG', - 'A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK', - 'A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK', - 'A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK', - 'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK', - 'A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK', - 'A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT', - 'A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK', - 'A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT', - 'A6XX_HLSQ_CPS_MISC_RAM', 'A6XX_HLSQ_CPS_MISC_RAM_TAG', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK', - 'A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE', - 'A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR', - 'A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK', - 'A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT', - 'A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_CS_CNTL_ENABLED', - 'A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK', - 'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK', - 'A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK', - 'A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK', - 'A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK', - 'A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK', - 'A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT', - 'A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK', - 'A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5', - 'A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6', 'A6XX_HLSQ_CVS_MISC_RAM', - 'A6XX_HLSQ_CVS_MISC_RAM_TAG', 'A6XX_HLSQ_DATAPATH_META', - 'A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT', - 'A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT', - 'A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_DS_CNTL_ENABLED', - 'A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_EVENT_CMD_EVENT__MASK', - 'A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT', - 'A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK', - 'A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT', 'A6XX_HLSQ_FRONTEND_META', - 'A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK', - 'A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT', - 'A6XX_HLSQ_FS_CNTL_0_UNK2__MASK', - 'A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT', 'A6XX_HLSQ_FS_CNTL_0_VARYINGS', - 'A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_FS_CNTL_ENABLED', - 'A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_GFX_CPS_CONST_RAM', 'A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 'A6XX_HLSQ_GFX_CVS_CONST_RAM', 'A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 'A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_GS_CNTL_ENABLED', - 'A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_HS_CNTL_ENABLED', - 'A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS', - 'A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', 'A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 'A6XX_HLSQ_INDIRECT_META', 'A6XX_HLSQ_INST_RAM', - 'A6XX_HLSQ_INST_RAM_1', 'A6XX_HLSQ_INST_RAM_TAG', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_IBO', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST', - 'A6XX_HLSQ_INVALIDATE_CMD_CS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_DS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_FS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO', - 'A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST', - 'A6XX_HLSQ_INVALIDATE_CMD_GS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_HS_STATE', - 'A6XX_HLSQ_INVALIDATE_CMD_VS_STATE', 'A6XX_HLSQ_PWR_REST_RAM', - 'A6XX_HLSQ_PWR_REST_TAG', 'A6XX_HLSQ_SHARED_CONSTS_ENABLE', - 'A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK', - 'A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_VS_CNTL_ENABLED', - 'A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS', 'A6XX_INVALID_ZTEST', - 'A6XX_LATE_Z', 'A6XX_PC_2D_EVENT_CMD_EVENT__MASK', - 'A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT', - 'A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK', - 'A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT', - 'A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN', - 'A6XX_PC_DISPATCH_CMD_STATE_ID__MASK', - 'A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT', - 'A6XX_PC_DRAW_CMD_STATE_ID__MASK', - 'A6XX_PC_DRAW_CMD_STATE_ID__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_GS_ENABLE', - 'A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK', - 'A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK', - 'A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK', - 'A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK', - 'A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT', - 'A6XX_PC_DRAW_INITIATOR_TESS_ENABLE', - 'A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK', - 'A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT', - 'A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_DS_OUT_CNTL_LAYER', 'A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_DS_OUT_CNTL_PSIZE', 'A6XX_PC_DS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_DS_OUT_CNTL_VIEW', 'A6XX_PC_EVENT_CMD_EVENT__MASK', - 'A6XX_PC_EVENT_CMD_EVENT__SHIFT', - 'A6XX_PC_EVENT_CMD_STATE_ID__MASK', - 'A6XX_PC_EVENT_CMD_STATE_ID__SHIFT', - 'A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_GS_OUT_CNTL_LAYER', 'A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_GS_OUT_CNTL_PSIZE', 'A6XX_PC_GS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_GS_OUT_CNTL_VIEW', 'A6XX_PC_HS_INPUT_SIZE_SIZE__MASK', - 'A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT', - 'A6XX_PC_HS_INPUT_SIZE_UNK13', - 'A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_HS_OUT_CNTL_LAYER', 'A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_HS_OUT_CNTL_PSIZE', 'A6XX_PC_HS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_HS_OUT_CNTL_VIEW', - 'A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS', - 'A6XX_PC_MULTIVIEW_CNTL_ENABLE', - 'A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK', - 'A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT', - 'A6XX_PC_POLYGON_MODE_MODE__MASK', - 'A6XX_PC_POLYGON_MODE_MODE__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING', - 'A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART', - 'A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST', - 'A6XX_PC_PRIMITIVE_CNTL_0_UNK3', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT', - 'A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN', - 'A6XX_PC_PRIMITIVE_CNTL_5_UNK18', - 'A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK', - 'A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_PS_CNTL_PRIMITIVEIDEN', 'A6XX_PC_RASTER_CNTL_DISCARD', - 'A6XX_PC_RASTER_CNTL_STREAM__MASK', - 'A6XX_PC_RASTER_CNTL_STREAM__SHIFT', - 'A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK', - 'A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT', - 'A6XX_PC_TESS_CNTL_OUTPUT__MASK', - 'A6XX_PC_TESS_CNTL_OUTPUT__SHIFT', - 'A6XX_PC_TESS_CNTL_SPACING__MASK', - 'A6XX_PC_TESS_CNTL_SPACING__SHIFT', - 'A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE', - 'A6XX_PC_VSTREAM_CONTROL_UNK0__MASK', - 'A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT', - 'A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK', - 'A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT', - 'A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK', - 'A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT', - 'A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK', - 'A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT', - 'A6XX_PC_VS_OUT_CNTL_LAYER', 'A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID', - 'A6XX_PC_VS_OUT_CNTL_PSIZE', 'A6XX_PC_VS_OUT_CNTL_SHADINGRATE', - 'A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK', - 'A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT', - 'A6XX_PC_VS_OUT_CNTL_VIEW', 'A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR', - 'A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS', - 'A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC', - 'A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS', - 'A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS', - 'A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS', - 'A6XX_RBBM_INT_0_MASK_CP_HW_ERROR', 'A6XX_RBBM_INT_0_MASK_CP_IB1', - 'A6XX_RBBM_INT_0_MASK_CP_IB2', - 'A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0', - 'A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1', - 'A6XX_RBBM_INT_0_MASK_CP_RB', - 'A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS', - 'A6XX_RBBM_INT_0_MASK_CP_SW', - 'A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS', - 'A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0', - 'A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1', - 'A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ', - 'A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG', - 'A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT', - 'A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC', - 'A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW', - 'A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW', - 'A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR', - 'A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE', - 'A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT', - 'A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION', - 'A6XX_RBBM_INT_0_MASK_TSBWRITEERROR', - 'A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS', - 'A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR', - 'A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT', - 'A6XX_RBBM_STATUS_A2D_BUSY', 'A6XX_RBBM_STATUS_CCU_BUSY', - 'A6XX_RBBM_STATUS_COM_DCOM_BUSY', - 'A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER', - 'A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER', - 'A6XX_RBBM_STATUS_CP_BUSY', 'A6XX_RBBM_STATUS_GFX_DBGC_BUSY', - 'A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB', - 'A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP', - 'A6XX_RBBM_STATUS_HLSQ_BUSY', 'A6XX_RBBM_STATUS_LRZ_BUSY', - 'A6XX_RBBM_STATUS_PC_DCALL_BUSY', 'A6XX_RBBM_STATUS_PC_VSD_BUSY', - 'A6XX_RBBM_STATUS_RAS_BUSY', 'A6XX_RBBM_STATUS_RB_BUSY', - 'A6XX_RBBM_STATUS_SP_BUSY', 'A6XX_RBBM_STATUS_TESS_BUSY', - 'A6XX_RBBM_STATUS_TPL1_BUSY', 'A6XX_RBBM_STATUS_TSE_BUSY', - 'A6XX_RBBM_STATUS_UCHE_BUSY', 'A6XX_RBBM_STATUS_VBIF_BUSY', - 'A6XX_RBBM_STATUS_VFD_BUSY', 'A6XX_RBBM_STATUS_VPC_BUSY', - 'A6XX_RBBM_STATUS_VSC_BUSY', - 'A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE', - 'A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK', - 'A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_D24S8', 'A6XX_RB_2D_BLIT_CNTL_IFMT__MASK', - 'A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_MASK__MASK', - 'A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN', - 'A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK', - 'A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK', - 'A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT', - 'A6XX_RB_2D_BLIT_CNTL_SCISSOR', - 'A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR', - 'A6XX_RB_2D_BLIT_CNTL_UNK17__MASK', - 'A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT', 'A6XX_RB_2D_BLIT_CNTL_UNK30', - 'A6XX_RB_2D_BLIT_CNTL_UNK4__MASK', - 'A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT', - 'A6XX_RB_2D_DST_FLAGS_PITCH__MASK', - 'A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT', - 'A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK', - 'A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT', - 'A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK', - 'A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK', - 'A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT', - 'A6XX_RB_2D_DST_INFO_FILTER', 'A6XX_RB_2D_DST_INFO_FLAGS', - 'A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE', - 'A6XX_RB_2D_DST_INFO_SAMPLES__MASK', - 'A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT', 'A6XX_RB_2D_DST_INFO_SRGB', - 'A6XX_RB_2D_DST_INFO_TILE_MODE__MASK', - 'A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT', - 'A6XX_RB_2D_DST_INFO_UNK17', 'A6XX_RB_2D_DST_INFO_UNK19', - 'A6XX_RB_2D_DST_INFO_UNK20', 'A6XX_RB_2D_DST_INFO_UNK21', - 'A6XX_RB_2D_DST_INFO_UNK22', 'A6XX_RB_2D_DST_INFO_UNK23__MASK', - 'A6XX_RB_2D_DST_INFO_UNK23__SHIFT', 'A6XX_RB_2D_DST_INFO_UNK28', - 'A6XX_RB_2D_DST_PITCH__MASK', 'A6XX_RB_2D_DST_PITCH__SHIFT', - 'A6XX_RB_2D_DST_PLANE_PITCH__MASK', - 'A6XX_RB_2D_DST_PLANE_PITCH__SHIFT', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK', - 'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT', - 'A6XX_RB_BIN_CONTROL2_BINH__MASK', - 'A6XX_RB_BIN_CONTROL2_BINH__SHIFT', - 'A6XX_RB_BIN_CONTROL2_BINW__MASK', - 'A6XX_RB_BIN_CONTROL2_BINW__SHIFT', - 'A6XX_RB_BIN_CONTROL_BINH__MASK', - 'A6XX_RB_BIN_CONTROL_BINH__SHIFT', - 'A6XX_RB_BIN_CONTROL_BINW__MASK', - 'A6XX_RB_BIN_CONTROL_BINW__SHIFT', - 'A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK', - 'A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT', - 'A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS', - 'A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK', - 'A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT', - 'A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK', - 'A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT', - 'A6XX_RB_BLEND_ALPHA_F32__MASK', 'A6XX_RB_BLEND_ALPHA_F32__SHIFT', - 'A6XX_RB_BLEND_BLUE_F32__MASK', 'A6XX_RB_BLEND_BLUE_F32__SHIFT', - 'A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE', - 'A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE', - 'A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE', - 'A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK', - 'A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT', - 'A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND', - 'A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK', - 'A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT', - 'A6XX_RB_BLEND_GREEN_F32__MASK', 'A6XX_RB_BLEND_GREEN_F32__SHIFT', - 'A6XX_RB_BLEND_RED_F32__MASK', 'A6XX_RB_BLEND_RED_F32__SHIFT', - 'A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK', - 'A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK', - 'A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK', - 'A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_FLAGS', - 'A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK', - 'A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK', - 'A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT', - 'A6XX_RB_BLIT_DST_INFO_UNK15', 'A6XX_RB_BLIT_DST_PITCH__MASK', - 'A6XX_RB_BLIT_DST_PITCH__SHIFT', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK', - 'A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT', - 'A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_RB_BLIT_INFO_BUFFER_ID__MASK', - 'A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT', - 'A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK', - 'A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT', 'A6XX_RB_BLIT_INFO_DEPTH', - 'A6XX_RB_BLIT_INFO_GMEM', 'A6XX_RB_BLIT_INFO_LAST__MASK', - 'A6XX_RB_BLIT_INFO_LAST__SHIFT', 'A6XX_RB_BLIT_INFO_SAMPLE_0', - 'A6XX_RB_BLIT_INFO_UNK0', 'A6XX_RB_BLIT_SCISSOR_BR_X__MASK', - 'A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT', - 'A6XX_RB_BLIT_SCISSOR_BR_Y__MASK', - 'A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT', - 'A6XX_RB_BLIT_SCISSOR_TL_X__MASK', - 'A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT', - 'A6XX_RB_BLIT_SCISSOR_TL_Y__MASK', - 'A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT', - 'A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK', - 'A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK', - 'A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT', - 'A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE', - 'A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK', - 'A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK', - 'A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT', - 'A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE', - 'A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK', - 'A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT', - 'A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK', - 'A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT', - 'A6XX_RB_DEPTH_BUFFER_PITCH__MASK', - 'A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT', - 'A6XX_RB_DEPTH_CNTL_ZFUNC__MASK', - 'A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT', - 'A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE', - 'A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK', - 'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT', - 'A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK', - 'A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT', - 'A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE', - 'A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK', - 'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT', - 'A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE', - 'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK', - 'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF', - 'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z', - 'A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK', - 'A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT', 'A6XX_RB_LRZ_CNTL_ENABLE', - 'A6XX_RB_MRT_ARRAY_PITCH__MASK', 'A6XX_RB_MRT_ARRAY_PITCH__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK', - 'A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK', - 'A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK', - 'A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK', - 'A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT', - 'A6XX_RB_MRT_BUF_INFO_UNK10', 'A6XX_RB_MRT_CONTROL_BLEND', - 'A6XX_RB_MRT_CONTROL_BLEND2', - 'A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK', - 'A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT', - 'A6XX_RB_MRT_CONTROL_ROP_CODE__MASK', - 'A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT', - 'A6XX_RB_MRT_CONTROL_ROP_ENABLE', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK', - 'A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_RB_MRT_PITCH__MASK', 'A6XX_RB_MRT_PITCH__SHIFT', - 'A6XX_RB_NC_MODE_CNTL_AMSBC', - 'A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK', - 'A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT', - 'A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH', - 'A6XX_RB_NC_MODE_CNTL_MODE', - 'A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR', - 'A6XX_RB_NC_MODE_CNTL_UNK12__MASK', - 'A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT', - 'A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK', - 'A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT', - 'A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_RB_RAS_MSAA_CNTL_UNK2', 'A6XX_RB_RAS_MSAA_CNTL_UNK3', - 'A6XX_RB_RENDER_CNTL_BINNING', - 'A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK', - 'A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT', - 'A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN', - 'A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN', - 'A6XX_RB_RENDER_CNTL_FLAG_DEPTH', - 'A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK', - 'A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT', - 'A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN', - 'A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK', - 'A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT', - 'A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK', - 'A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT', - 'A6XX_RB_RENDER_CNTL_UNK8__MASK', - 'A6XX_RB_RENDER_CNTL_UNK8__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT0__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT1__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT2__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT3__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT4__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT5__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT6__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT', - 'A6XX_RB_RENDER_COMPONENTS_RT7__MASK', - 'A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT', - 'A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK', - 'A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT', - 'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID', - 'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL', - 'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE', - 'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID', - 'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL', - 'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE', - 'A6XX_RB_RENDER_CONTROL0_UNK10', - 'A6XX_RB_RENDER_CONTROL1_CENTERRHW', - 'A6XX_RB_RENDER_CONTROL1_FACENESS', - 'A6XX_RB_RENDER_CONTROL1_FOVEATION', - 'A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK', - 'A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT', - 'A6XX_RB_RENDER_CONTROL1_LINELENGTHEN', - 'A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE', - 'A6XX_RB_RENDER_CONTROL1_SAMPLEID', - 'A6XX_RB_RENDER_CONTROL1_SAMPLEMASK', - 'A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE', - 'A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE', - 'A6XX_RB_SAMPLE_CONFIG_UNK0', 'A6XX_RB_SAMPLE_COUNT_CONTROL_COPY', - 'A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK', - 'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT0', 'A6XX_RB_SRGB_CNTL_SRGB_MRT1', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT2', 'A6XX_RB_SRGB_CNTL_SRGB_MRT3', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT4', 'A6XX_RB_SRGB_CNTL_SRGB_MRT5', - 'A6XX_RB_SRGB_CNTL_SRGB_MRT6', 'A6XX_RB_SRGB_CNTL_SRGB_MRT7', - 'A6XX_RB_STENCILMASK_BFMASK__MASK', - 'A6XX_RB_STENCILMASK_BFMASK__SHIFT', - 'A6XX_RB_STENCILMASK_MASK__MASK', - 'A6XX_RB_STENCILMASK_MASK__SHIFT', - 'A6XX_RB_STENCILREF_BFREF__MASK', - 'A6XX_RB_STENCILREF_BFREF__SHIFT', 'A6XX_RB_STENCILREF_REF__MASK', - 'A6XX_RB_STENCILREF_REF__SHIFT', - 'A6XX_RB_STENCILWRMASK_BFWRMASK__MASK', - 'A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT', - 'A6XX_RB_STENCILWRMASK_WRMASK__MASK', - 'A6XX_RB_STENCILWRMASK_WRMASK__SHIFT', - 'A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK', - 'A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT', - 'A6XX_RB_STENCIL_BUFFER_PITCH__MASK', - 'A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FAIL__MASK', - 'A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_FUNC__MASK', - 'A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE', - 'A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF', - 'A6XX_RB_STENCIL_CONTROL_STENCIL_READ', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT', - 'A6XX_RB_STENCIL_CONTROL_ZPASS__MASK', - 'A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT', - 'A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL', - 'A6XX_RB_STENCIL_INFO_UNK1', 'A6XX_RB_UNKNOWN_88D0_UNK0__MASK', - 'A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT', - 'A6XX_RB_UNKNOWN_88D0_UNK16__MASK', - 'A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK', - 'A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT', - 'A6XX_RB_WINDOW_OFFSET2_X__MASK', - 'A6XX_RB_WINDOW_OFFSET2_X__SHIFT', - 'A6XX_RB_WINDOW_OFFSET2_Y__MASK', - 'A6XX_RB_WINDOW_OFFSET2_Y__SHIFT', - 'A6XX_RB_WINDOW_OFFSET_X__MASK', 'A6XX_RB_WINDOW_OFFSET_X__SHIFT', - 'A6XX_RB_WINDOW_OFFSET_Y__MASK', 'A6XX_RB_WINDOW_OFFSET_Y__SHIFT', - 'A6XX_RB_Z_BOUNDS_MAX__MASK', 'A6XX_RB_Z_BOUNDS_MAX__SHIFT', - 'A6XX_RB_Z_BOUNDS_MIN__MASK', 'A6XX_RB_Z_BOUNDS_MIN__SHIFT', - 'A6XX_RB_Z_CLAMP_MAX__MASK', 'A6XX_RB_Z_CLAMP_MAX__SHIFT', - 'A6XX_RB_Z_CLAMP_MIN__MASK', 'A6XX_RB_Z_CLAMP_MIN__SHIFT', - 'A6XX_REDUCTION_MODE_AVERAGE', 'A6XX_REDUCTION_MODE_MAX', - 'A6XX_REDUCTION_MODE_MIN', - 'A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK', - 'A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT', - 'A6XX_SP_2D_DST_FORMAT_MASK__MASK', - 'A6XX_SP_2D_DST_FORMAT_MASK__SHIFT', 'A6XX_SP_2D_DST_FORMAT_NORM', - 'A6XX_SP_2D_DST_FORMAT_SINT', 'A6XX_SP_2D_DST_FORMAT_SRGB', - 'A6XX_SP_2D_DST_FORMAT_UINT', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE', - 'A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE', - 'A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK', - 'A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT', - 'A6XX_SP_BLEND_CNTL_UNK8', 'A6XX_SP_CB_BINDLESS_DATA', - 'A6XX_SP_CB_BINDLESS_TAG', 'A6XX_SP_CB_LEGACY_DATA', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK', - 'A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT', - 'A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK', - 'A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT', - 'A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK', - 'A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT', - 'A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK', - 'A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT', - 'A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE', - 'A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR', - 'A6XX_SP_CS_CNTL_1_THREADSIZE__MASK', - 'A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT', - 'A6XX_SP_CS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_CS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_CS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_CS_CONFIG_BINDLESS_UBO', 'A6XX_SP_CS_CONFIG_ENABLED', - 'A6XX_SP_CS_CONFIG_NIBO__MASK', 'A6XX_SP_CS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_CS_CONFIG_NSAMP__MASK', 'A6XX_SP_CS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_CS_CONFIG_NTEX__MASK', 'A6XX_SP_CS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_MERGEDREGS', - 'A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK', - 'A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT', - 'A6XX_SP_CS_CTRL_REG0_UNK13', 'A6XX_SP_CS_CTRL_REG0_UNK21', - 'A6XX_SP_CS_CTRL_REG0_UNK22', - 'A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK', - 'A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT', - 'A6XX_SP_CS_UNKNOWN_A9B1_UNK5', 'A6XX_SP_CS_UNKNOWN_A9B1_UNK6', - 'A6XX_SP_DS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_DS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_DS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_DS_CONFIG_BINDLESS_UBO', 'A6XX_SP_DS_CONFIG_ENABLED', - 'A6XX_SP_DS_CONFIG_NIBO__MASK', 'A6XX_SP_DS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_DS_CONFIG_NSAMP__MASK', 'A6XX_SP_DS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_DS_CONFIG_NTEX__MASK', 'A6XX_SP_DS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_DS_CTRL_REG0_UNK13', - 'A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK', - 'A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT', - 'A6XX_SP_DS_OUT_REG_A_REGID__MASK', - 'A6XX_SP_DS_OUT_REG_A_REGID__SHIFT', - 'A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK', - 'A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT', - 'A6XX_SP_DS_OUT_REG_B_REGID__MASK', - 'A6XX_SP_DS_OUT_REG_B_REGID__SHIFT', - 'A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK', - 'A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT', - 'A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK', - 'A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT', - 'A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK', - 'A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT', - 'A6XX_SP_FLOAT_CNTL_F16_NO_INF', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK', - 'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT', - 'A6XX_SP_FS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_FS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_FS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_FS_CONFIG_BINDLESS_UBO', 'A6XX_SP_FS_CONFIG_ENABLED', - 'A6XX_SP_FS_CONFIG_NIBO__MASK', 'A6XX_SP_FS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_FS_CONFIG_NSAMP__MASK', 'A6XX_SP_FS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_FS_CONFIG_NTEX__MASK', 'A6XX_SP_FS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_LODPIXMASK', - 'A6XX_SP_FS_CTRL_REG0_MERGEDREGS', - 'A6XX_SP_FS_CTRL_REG0_PIXLODENABLE', - 'A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK', - 'A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT', - 'A6XX_SP_FS_CTRL_REG0_UNK13', 'A6XX_SP_FS_CTRL_REG0_UNK21', - 'A6XX_SP_FS_CTRL_REG0_UNK24', 'A6XX_SP_FS_CTRL_REG0_UNK25', - 'A6XX_SP_FS_CTRL_REG0_UNK27', 'A6XX_SP_FS_CTRL_REG0_VARYING', - 'A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK', - 'A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT', - 'A6XX_SP_FS_MRT_REG_COLOR_SINT', 'A6XX_SP_FS_MRT_REG_COLOR_UINT', - 'A6XX_SP_FS_MRT_REG_UNK10', - 'A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT', - 'A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE', - 'A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT', - 'A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT', - 'A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK', - 'A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT', - 'A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION', - 'A6XX_SP_FS_OUTPUT_REG_REGID__MASK', - 'A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_BINDLESS', - 'A6XX_SP_FS_PREFETCH_CMD_CMD__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_DST__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_HALF', - 'A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_SRC__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CMD_UNK27', - 'A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK', - 'A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK', - 'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK', - 'A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT', - 'A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD', - 'A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE', - 'A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT', - 'A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK', - 'A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT', - 'A6XX_SP_GS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_GS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_GS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_GS_CONFIG_BINDLESS_UBO', 'A6XX_SP_GS_CONFIG_ENABLED', - 'A6XX_SP_GS_CONFIG_NIBO__MASK', 'A6XX_SP_GS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_GS_CONFIG_NSAMP__MASK', 'A6XX_SP_GS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_GS_CONFIG_NTEX__MASK', 'A6XX_SP_GS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_GS_CTRL_REG0_UNK13', - 'A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK', - 'A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT', - 'A6XX_SP_GS_OUT_REG_A_REGID__MASK', - 'A6XX_SP_GS_OUT_REG_A_REGID__SHIFT', - 'A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK', - 'A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT', - 'A6XX_SP_GS_OUT_REG_B_REGID__MASK', - 'A6XX_SP_GS_OUT_REG_B_REGID__SHIFT', - 'A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK', - 'A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT', - 'A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK', - 'A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT', - 'A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK', - 'A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT', - 'A6XX_SP_HS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_HS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_HS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_HS_CONFIG_BINDLESS_UBO', 'A6XX_SP_HS_CONFIG_ENABLED', - 'A6XX_SP_HS_CONFIG_NIBO__MASK', 'A6XX_SP_HS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_HS_CONFIG_NSAMP__MASK', 'A6XX_SP_HS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_HS_CONFIG_NTEX__MASK', 'A6XX_SP_HS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_HS_CTRL_REG0_UNK13', - 'A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_INST_DATA', 'A6XX_SP_INST_TAG', 'A6XX_SP_LB_0_DATA', - 'A6XX_SP_LB_1_DATA', 'A6XX_SP_LB_2_DATA', 'A6XX_SP_LB_3_DATA', - 'A6XX_SP_LB_4_DATA', 'A6XX_SP_LB_5_DATA', 'A6XX_SP_LB_6_DATA', - 'A6XX_SP_LB_7_DATA', - 'A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE', - 'A6XX_SP_MODE_CONTROL_ISAMMODE__MASK', - 'A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT', - 'A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE', - 'A6XX_SP_PERFCTR_ENABLE_CS', 'A6XX_SP_PERFCTR_ENABLE_DS', - 'A6XX_SP_PERFCTR_ENABLE_FS', 'A6XX_SP_PERFCTR_ENABLE_GS', - 'A6XX_SP_PERFCTR_ENABLE_HS', 'A6XX_SP_PERFCTR_ENABLE_VS', - 'A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK', - 'A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_FILTER', 'A6XX_SP_PS_2D_SRC_INFO_FLAGS', - 'A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE', - 'A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_SRGB', - 'A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_UNK17', 'A6XX_SP_PS_2D_SRC_INFO_UNK19', - 'A6XX_SP_PS_2D_SRC_INFO_UNK20', 'A6XX_SP_PS_2D_SRC_INFO_UNK21', - 'A6XX_SP_PS_2D_SRC_INFO_UNK22', - 'A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK', - 'A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT', - 'A6XX_SP_PS_2D_SRC_INFO_UNK28', - 'A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK', - 'A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT', - 'A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK', - 'A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT', - 'A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK', - 'A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT', - 'A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK', - 'A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT', - 'A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK', - 'A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT', 'A6XX_SP_SMO_TAG', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT0', 'A6XX_SP_SRGB_CNTL_SRGB_MRT1', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT2', 'A6XX_SP_SRGB_CNTL_SRGB_MRT3', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT4', 'A6XX_SP_SRGB_CNTL_SRGB_MRT5', - 'A6XX_SP_SRGB_CNTL_SRGB_MRT6', 'A6XX_SP_SRGB_CNTL_SRGB_MRT7', - 'A6XX_SP_STATE_DATA', 'A6XX_SP_TMO_UMO_TAG', - 'A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE', - 'A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK', - 'A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT', - 'A6XX_SP_TP_MODE_CNTL_UNK3__MASK', - 'A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT', - 'A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK', - 'A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT', - 'A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK', - 'A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT', - 'A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE', - 'A6XX_SP_TP_SAMPLE_CONFIG_UNK0', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK', - 'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT', - 'A6XX_SP_TP_WINDOW_OFFSET_X__MASK', - 'A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT', - 'A6XX_SP_TP_WINDOW_OFFSET_Y__MASK', - 'A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT', 'A6XX_SP_UAV_DATA', - 'A6XX_SP_VS_CONFIG_BINDLESS_IBO', - 'A6XX_SP_VS_CONFIG_BINDLESS_SAMP', - 'A6XX_SP_VS_CONFIG_BINDLESS_TEX', - 'A6XX_SP_VS_CONFIG_BINDLESS_UBO', 'A6XX_SP_VS_CONFIG_ENABLED', - 'A6XX_SP_VS_CONFIG_NIBO__MASK', 'A6XX_SP_VS_CONFIG_NIBO__SHIFT', - 'A6XX_SP_VS_CONFIG_NSAMP__MASK', 'A6XX_SP_VS_CONFIG_NSAMP__SHIFT', - 'A6XX_SP_VS_CONFIG_NTEX__MASK', 'A6XX_SP_VS_CONFIG_NTEX__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK', - 'A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE', - 'A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK', - 'A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK', - 'A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_MERGEDREGS', - 'A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK', - 'A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT', - 'A6XX_SP_VS_CTRL_REG0_UNK13', - 'A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK', - 'A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT', - 'A6XX_SP_VS_OUT_REG_A_REGID__MASK', - 'A6XX_SP_VS_OUT_REG_A_REGID__SHIFT', - 'A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK', - 'A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT', - 'A6XX_SP_VS_OUT_REG_B_REGID__MASK', - 'A6XX_SP_VS_OUT_REG_B_REGID__SHIFT', - 'A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK', - 'A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT', - 'A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK', - 'A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT', - 'A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK', - 'A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT', - 'A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK', - 'A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT', - 'A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK', - 'A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT', - 'A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT', - 'A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK', - 'A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK', - 'A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT', - 'A6XX_SP_WINDOW_OFFSET_X__MASK', 'A6XX_SP_WINDOW_OFFSET_X__SHIFT', - 'A6XX_SP_WINDOW_OFFSET_Y__MASK', 'A6XX_SP_WINDOW_OFFSET_Y__SHIFT', - 'A6XX_TEX_1D', 'A6XX_TEX_2D', 'A6XX_TEX_3D', 'A6XX_TEX_ANISO', - 'A6XX_TEX_ANISO_1', 'A6XX_TEX_ANISO_16', 'A6XX_TEX_ANISO_2', - 'A6XX_TEX_ANISO_4', 'A6XX_TEX_ANISO_8', 'A6XX_TEX_BUFFER', - 'A6XX_TEX_CLAMP_TO_BORDER', 'A6XX_TEX_CLAMP_TO_EDGE', - 'A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X', - 'A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y', - 'A6XX_TEX_CONST_0_FMT__MASK', 'A6XX_TEX_CONST_0_FMT__SHIFT', - 'A6XX_TEX_CONST_0_MIPLVLS__MASK', - 'A6XX_TEX_CONST_0_MIPLVLS__SHIFT', - 'A6XX_TEX_CONST_0_SAMPLES__MASK', - 'A6XX_TEX_CONST_0_SAMPLES__SHIFT', 'A6XX_TEX_CONST_0_SRGB', - 'A6XX_TEX_CONST_0_SWAP__MASK', 'A6XX_TEX_CONST_0_SWAP__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_W__MASK', 'A6XX_TEX_CONST_0_SWIZ_W__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_X__MASK', 'A6XX_TEX_CONST_0_SWIZ_X__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_Y__MASK', 'A6XX_TEX_CONST_0_SWIZ_Y__SHIFT', - 'A6XX_TEX_CONST_0_SWIZ_Z__MASK', 'A6XX_TEX_CONST_0_SWIZ_Z__SHIFT', - 'A6XX_TEX_CONST_0_TILE_MODE__MASK', - 'A6XX_TEX_CONST_0_TILE_MODE__SHIFT', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK', - 'A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT', - 'A6XX_TEX_CONST_1_HEIGHT__MASK', 'A6XX_TEX_CONST_1_HEIGHT__SHIFT', - 'A6XX_TEX_CONST_1_WIDTH__MASK', 'A6XX_TEX_CONST_1_WIDTH__SHIFT', - 'A6XX_TEX_CONST_2_PITCHALIGN__MASK', - 'A6XX_TEX_CONST_2_PITCHALIGN__SHIFT', - 'A6XX_TEX_CONST_2_PITCH__MASK', 'A6XX_TEX_CONST_2_PITCH__SHIFT', - 'A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK', - 'A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT', - 'A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK', - 'A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT', - 'A6XX_TEX_CONST_2_TYPE__MASK', 'A6XX_TEX_CONST_2_TYPE__SHIFT', - 'A6XX_TEX_CONST_3_ARRAY_PITCH__MASK', - 'A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT', 'A6XX_TEX_CONST_3_FLAG', - 'A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK', - 'A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT', - 'A6XX_TEX_CONST_3_TILE_ALL', 'A6XX_TEX_CONST_4_BASE_LO__MASK', - 'A6XX_TEX_CONST_4_BASE_LO__SHIFT', - 'A6XX_TEX_CONST_5_BASE_HI__MASK', - 'A6XX_TEX_CONST_5_BASE_HI__SHIFT', 'A6XX_TEX_CONST_5_DEPTH__MASK', - 'A6XX_TEX_CONST_5_DEPTH__SHIFT', - 'A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK', - 'A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT', - 'A6XX_TEX_CONST_6_PLANE_PITCH__MASK', - 'A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT', - 'A6XX_TEX_CONST_7_FLAG_LO__MASK', - 'A6XX_TEX_CONST_7_FLAG_LO__SHIFT', - 'A6XX_TEX_CONST_8_FLAG_HI__MASK', - 'A6XX_TEX_CONST_8_FLAG_HI__SHIFT', - 'A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK', - 'A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT', - 'A6XX_TEX_CUBE', 'A6XX_TEX_CUBIC', 'A6XX_TEX_LINEAR', - 'A6XX_TEX_MIRROR_CLAMP', 'A6XX_TEX_MIRROR_REPEAT', - 'A6XX_TEX_NEAREST', 'A6XX_TEX_ONE', 'A6XX_TEX_REPEAT', - 'A6XX_TEX_SAMP_0_ANISO__MASK', 'A6XX_TEX_SAMP_0_ANISO__SHIFT', - 'A6XX_TEX_SAMP_0_LOD_BIAS__MASK', - 'A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT', - 'A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR', - 'A6XX_TEX_SAMP_0_WRAP_R__MASK', 'A6XX_TEX_SAMP_0_WRAP_R__SHIFT', - 'A6XX_TEX_SAMP_0_WRAP_S__MASK', 'A6XX_TEX_SAMP_0_WRAP_S__SHIFT', - 'A6XX_TEX_SAMP_0_WRAP_T__MASK', 'A6XX_TEX_SAMP_0_WRAP_T__SHIFT', - 'A6XX_TEX_SAMP_0_XY_MAG__MASK', 'A6XX_TEX_SAMP_0_XY_MAG__SHIFT', - 'A6XX_TEX_SAMP_0_XY_MIN__MASK', 'A6XX_TEX_SAMP_0_XY_MIN__SHIFT', - 'A6XX_TEX_SAMP_1_CLAMPENABLE', - 'A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK', - 'A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT', - 'A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF', - 'A6XX_TEX_SAMP_1_MAX_LOD__MASK', 'A6XX_TEX_SAMP_1_MAX_LOD__SHIFT', - 'A6XX_TEX_SAMP_1_MIN_LOD__MASK', 'A6XX_TEX_SAMP_1_MIN_LOD__SHIFT', - 'A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR', - 'A6XX_TEX_SAMP_1_UNNORM_COORDS', 'A6XX_TEX_SAMP_2_BCOLOR__MASK', - 'A6XX_TEX_SAMP_2_BCOLOR__SHIFT', 'A6XX_TEX_SAMP_2_CHROMA_LINEAR', - 'A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK', - 'A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT', 'A6XX_TEX_W', - 'A6XX_TEX_X', 'A6XX_TEX_Y', 'A6XX_TEX_Z', 'A6XX_TEX_ZERO', - 'A6XX_TP0_MIPMAP_BASE_DATA', 'A6XX_TP0_SMO_DATA', - 'A6XX_TP0_TMO_DATA', 'A6XX_TP1_MIPMAP_BASE_DATA', - 'A6XX_TP1_SMO_DATA', 'A6XX_TP1_TMO_DATA', - 'A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND', - 'A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK', - 'A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT', - 'A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH', - 'A6XX_TPL1_NC_MODE_CNTL_MODE', - 'A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK', - 'A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT', - 'A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK', - 'A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT', - 'A6XX_UBO_0_BASE_LO__MASK', 'A6XX_UBO_0_BASE_LO__SHIFT', - 'A6XX_UBO_1_BASE_HI__MASK', 'A6XX_UBO_1_BASE_HI__SHIFT', - 'A6XX_UBO_1_SIZE__MASK', 'A6XX_UBO_1_SIZE__SHIFT', - 'A6XX_UCHE_CLIENT_PF_PERFSEL__MASK', - 'A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT', - 'A6XX_VBIF_CLKON_FORCE_ON_TESTBUS', - 'A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK', - 'A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT', - 'A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK', - 'A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT', - 'A6XX_VFD_ADD_OFFSET_INSTANCE', 'A6XX_VFD_ADD_OFFSET_VERTEX', - 'A6XX_VFD_CONTROL_0_DECODE_CNT__MASK', - 'A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT', - 'A6XX_VFD_CONTROL_0_FETCH_CNT__MASK', - 'A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4INST__MASK', - 'A6XX_VFD_CONTROL_1_REGID4INST__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK', - 'A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK', - 'A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT', - 'A6XX_VFD_CONTROL_1_REGID4VTX__MASK', - 'A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT', - 'A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK', - 'A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT', - 'A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK', - 'A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK', - 'A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK', - 'A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_TESSX__MASK', - 'A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT', - 'A6XX_VFD_CONTROL_3_REGID_TESSY__MASK', - 'A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT', - 'A6XX_VFD_CONTROL_4_UNK0__MASK', 'A6XX_VFD_CONTROL_4_UNK0__SHIFT', - 'A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK', - 'A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT', - 'A6XX_VFD_CONTROL_5_UNK8__MASK', 'A6XX_VFD_CONTROL_5_UNK8__SHIFT', - 'A6XX_VFD_CONTROL_6_PRIMID4PSEN', 'A6XX_VFD_DECODE_INSTR_FLOAT', - 'A6XX_VFD_DECODE_INSTR_FORMAT__MASK', - 'A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT', - 'A6XX_VFD_DECODE_INSTR_IDX__MASK', - 'A6XX_VFD_DECODE_INSTR_IDX__SHIFT', - 'A6XX_VFD_DECODE_INSTR_INSTANCED', - 'A6XX_VFD_DECODE_INSTR_OFFSET__MASK', - 'A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT', - 'A6XX_VFD_DECODE_INSTR_SWAP__MASK', - 'A6XX_VFD_DECODE_INSTR_SWAP__SHIFT', - 'A6XX_VFD_DECODE_INSTR_UNK30', - 'A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK', - 'A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT', - 'A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK', - 'A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT', - 'A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK', - 'A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT', - 'A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS', - 'A6XX_VFD_MULTIVIEW_CNTL_ENABLE', - 'A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK', - 'A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT', - 'A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK', - 'A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT', - 'A6XX_VPC_CNTL_0_PRIMIDLOC__MASK', - 'A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT', 'A6XX_VPC_CNTL_0_VARYING', - 'A6XX_VPC_CNTL_0_VIEWIDLOC__MASK', - 'A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK', - 'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT', - 'A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK', - 'A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT', - 'A6XX_VPC_DS_PACK_EXTRAPOS__MASK', - 'A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT', - 'A6XX_VPC_DS_PACK_POSITIONLOC__MASK', - 'A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT', - 'A6XX_VPC_DS_PACK_PSIZELOC__MASK', - 'A6XX_VPC_DS_PACK_PSIZELOC__SHIFT', - 'A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK', - 'A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK', - 'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT', - 'A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK', - 'A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT', - 'A6XX_VPC_GS_PACK_EXTRAPOS__MASK', - 'A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT', - 'A6XX_VPC_GS_PACK_POSITIONLOC__MASK', - 'A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT', - 'A6XX_VPC_GS_PACK_PSIZELOC__MASK', - 'A6XX_VPC_GS_PACK_PSIZELOC__SHIFT', - 'A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK', - 'A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT', - 'A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK', - 'A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT', - 'A6XX_VPC_POINT_COORD_INVERT_INVERT', - 'A6XX_VPC_POLYGON_MODE_MODE__MASK', - 'A6XX_VPC_POLYGON_MODE_MODE__SHIFT', - 'A6XX_VPC_SO_CNTL_ADDR__MASK', 'A6XX_VPC_SO_CNTL_ADDR__SHIFT', - 'A6XX_VPC_SO_CNTL_RESET', 'A6XX_VPC_SO_DISABLE_DISABLE', - 'A6XX_VPC_SO_PROG_A_BUF__MASK', 'A6XX_VPC_SO_PROG_A_BUF__SHIFT', - 'A6XX_VPC_SO_PROG_A_EN', 'A6XX_VPC_SO_PROG_A_OFF__MASK', - 'A6XX_VPC_SO_PROG_A_OFF__SHIFT', 'A6XX_VPC_SO_PROG_B_BUF__MASK', - 'A6XX_VPC_SO_PROG_B_BUF__SHIFT', 'A6XX_VPC_SO_PROG_B_EN', - 'A6XX_VPC_SO_PROG_B_OFF__MASK', 'A6XX_VPC_SO_PROG_B_OFF__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT', - 'A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK', - 'A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT', - 'A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD', - 'A6XX_VPC_UNKNOWN_9107_UNK2', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK', - 'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT', - 'A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK', - 'A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT', - 'A6XX_VPC_VS_PACK_EXTRAPOS__MASK', - 'A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT', - 'A6XX_VPC_VS_PACK_POSITIONLOC__MASK', - 'A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT', - 'A6XX_VPC_VS_PACK_PSIZELOC__MASK', - 'A6XX_VPC_VS_PACK_PSIZELOC__SHIFT', - 'A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK', - 'A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT', - 'A6XX_VSC_BIN_COUNT_NX__MASK', 'A6XX_VSC_BIN_COUNT_NX__SHIFT', - 'A6XX_VSC_BIN_COUNT_NY__MASK', 'A6XX_VSC_BIN_COUNT_NY__SHIFT', - 'A6XX_VSC_BIN_SIZE_HEIGHT__MASK', - 'A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT', - 'A6XX_VSC_BIN_SIZE_WIDTH__MASK', 'A6XX_VSC_BIN_SIZE_WIDTH__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_H__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_W__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_X__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT', - 'A6XX_VSC_PIPE_CONFIG_REG_Y__MASK', - 'A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT', 'A6XX_XML', 'A7XX', - 'A7XX_CLUSTER_FE', 'A7XX_CLUSTER_GRAS', 'A7XX_CLUSTER_NONE', - 'A7XX_CLUSTER_PC_VS', 'A7XX_CLUSTER_PS', 'A7XX_CLUSTER_SP_PS', - 'A7XX_CLUSTER_SP_VS', 'A7XX_CLUSTER_VPC_PS', - 'A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK', - 'A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT', - 'A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK', - 'A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT', - 'A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK', - 'A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT', - 'A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK', - 'A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT', - 'A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK', - 'A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT', - 'A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK', - 'A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT', - 'A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND', - 'A7XX_CX_MISC_SW_FUSE_VALUE_LPAC', - 'A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING', 'A7XX_DBGBUS_CCHE_0', - 'A7XX_DBGBUS_CCHE_1', 'A7XX_DBGBUS_CCHE_2', 'A7XX_DBGBUS_CCU_0', - 'A7XX_DBGBUS_CCU_1', 'A7XX_DBGBUS_CCU_2', 'A7XX_DBGBUS_CCU_3', - 'A7XX_DBGBUS_CCU_4', 'A7XX_DBGBUS_CCU_5', 'A7XX_DBGBUS_CGC_CORE', - 'A7XX_DBGBUS_CGC_SUBCORE', 'A7XX_DBGBUS_COM_0', - 'A7XX_DBGBUS_CP_0_0', 'A7XX_DBGBUS_CP_0_1', 'A7XX_DBGBUS_CX', - 'A7XX_DBGBUS_DBGC', 'A7XX_DBGBUS_GBIF_CX', 'A7XX_DBGBUS_GBIF_GX', - 'A7XX_DBGBUS_GMU_CX', 'A7XX_DBGBUS_GMU_GX', 'A7XX_DBGBUS_GPC_BR', - 'A7XX_DBGBUS_GPC_BV', 'A7XX_DBGBUS_HLSQ', - 'A7XX_DBGBUS_HLSQ_DP_STR_0', 'A7XX_DBGBUS_HLSQ_DP_STR_1', - 'A7XX_DBGBUS_HLSQ_DP_STR_2', 'A7XX_DBGBUS_HLSQ_DP_STR_3', - 'A7XX_DBGBUS_HLSQ_DP_STR_4', 'A7XX_DBGBUS_HLSQ_DP_STR_5', - 'A7XX_DBGBUS_HLSQ_SPTP', 'A7XX_DBGBUS_LARC', 'A7XX_DBGBUS_LRZ_BR', - 'A7XX_DBGBUS_LRZ_BV', 'A7XX_DBGBUS_PC_BR', 'A7XX_DBGBUS_PC_BV', - 'A7XX_DBGBUS_RAS_BR', 'A7XX_DBGBUS_RAS_BV', 'A7XX_DBGBUS_RBBM', - 'A7XX_DBGBUS_RB_0', 'A7XX_DBGBUS_RB_1', 'A7XX_DBGBUS_RB_2', - 'A7XX_DBGBUS_RB_3', 'A7XX_DBGBUS_RB_4', 'A7XX_DBGBUS_RB_5', - 'A7XX_DBGBUS_TESS_BR', 'A7XX_DBGBUS_TESS_BV', 'A7XX_DBGBUS_TP_0', - 'A7XX_DBGBUS_TP_1', 'A7XX_DBGBUS_TP_10', 'A7XX_DBGBUS_TP_11', - 'A7XX_DBGBUS_TP_2', 'A7XX_DBGBUS_TP_3', 'A7XX_DBGBUS_TP_4', - 'A7XX_DBGBUS_TP_5', 'A7XX_DBGBUS_TP_6', 'A7XX_DBGBUS_TP_7', - 'A7XX_DBGBUS_TP_8', 'A7XX_DBGBUS_TP_9', 'A7XX_DBGBUS_TSE_BR', - 'A7XX_DBGBUS_TSE_BV', 'A7XX_DBGBUS_UCHE_0', 'A7XX_DBGBUS_UCHE_1', - 'A7XX_DBGBUS_UCHE_WRAPPER', 'A7XX_DBGBUS_UFC_0', - 'A7XX_DBGBUS_UFC_1', 'A7XX_DBGBUS_UFC_DSTR_0', - 'A7XX_DBGBUS_UFC_DSTR_1', 'A7XX_DBGBUS_UFC_DSTR_2', - 'A7XX_DBGBUS_USPTP_0', 'A7XX_DBGBUS_USPTP_1', - 'A7XX_DBGBUS_USPTP_10', 'A7XX_DBGBUS_USPTP_11', - 'A7XX_DBGBUS_USPTP_2', 'A7XX_DBGBUS_USPTP_3', - 'A7XX_DBGBUS_USPTP_4', 'A7XX_DBGBUS_USPTP_5', - 'A7XX_DBGBUS_USPTP_6', 'A7XX_DBGBUS_USPTP_7', - 'A7XX_DBGBUS_USPTP_8', 'A7XX_DBGBUS_USPTP_9', 'A7XX_DBGBUS_USP_0', - 'A7XX_DBGBUS_USP_1', 'A7XX_DBGBUS_USP_2', 'A7XX_DBGBUS_USP_3', - 'A7XX_DBGBUS_USP_4', 'A7XX_DBGBUS_USP_5', 'A7XX_DBGBUS_VFDP_BR', - 'A7XX_DBGBUS_VFDP_BV', 'A7XX_DBGBUS_VFD_BR_0', - 'A7XX_DBGBUS_VFD_BR_1', 'A7XX_DBGBUS_VFD_BR_2', - 'A7XX_DBGBUS_VFD_BR_3', 'A7XX_DBGBUS_VFD_BR_4', - 'A7XX_DBGBUS_VFD_BR_5', 'A7XX_DBGBUS_VFD_BR_6', - 'A7XX_DBGBUS_VFD_BR_7', 'A7XX_DBGBUS_VFD_BV_0', - 'A7XX_DBGBUS_VFD_BV_1', 'A7XX_DBGBUS_VFD_BV_2', - 'A7XX_DBGBUS_VFD_BV_3', 'A7XX_DBGBUS_VPC_BR', - 'A7XX_DBGBUS_VPC_BV', 'A7XX_DBGBUS_VPC_DSTR_0', - 'A7XX_DBGBUS_VPC_DSTR_1', 'A7XX_DBGBUS_VPC_DSTR_2', - 'A7XX_DBGBUS_VSC', 'A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK', - 'A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT', - 'A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR', - 'A7XX_GRAS_LRZ_CNTL2_FC_ENABLE', - 'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3', - 'A7XX_GRAS_SU_RENDER_CNTL_BINNING', 'A7XX_HLSQ_BACKEND_META', - 'A7XX_HLSQ_BV_BE_META', 'A7XX_HLSQ_CHUNK_CPS_RAM', - 'A7XX_HLSQ_CHUNK_CPS_RAM_TAG', 'A7XX_HLSQ_CHUNK_CVS_RAM', - 'A7XX_HLSQ_CHUNK_CVS_RAM_TAG', - 'A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK', - 'A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK', - 'A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK', - 'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK', - 'A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK', - 'A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT', - 'A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK', - 'A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT', - 'A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', 'A7XX_HLSQ_CPS_MISC_RAM', - 'A7XX_HLSQ_CPS_MISC_RAM_1', 'A7XX_HLSQ_CPS_MISC_RAM_TAG', - 'A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK', - 'A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT', - 'A7XX_HLSQ_CS_CNTL_1_UNK11', 'A7XX_HLSQ_CS_CNTL_1_UNK22', - 'A7XX_HLSQ_CS_CNTL_1_UNK26', 'A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK', - 'A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT', - 'A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_CS_CNTL_ENABLED', - 'A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK', - 'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK', - 'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK', - 'A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK', - 'A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK', - 'A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK', - 'A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK', - 'A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT', - 'A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK', - 'A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT', - 'A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', 'A7XX_HLSQ_CVS_MISC_RAM', - 'A7XX_HLSQ_CVS_MISC_RAM_TAG', 'A7XX_HLSQ_DATAPATH_DSTR_META', - 'A7XX_HLSQ_DATAPATH_META', - 'A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK', - 'A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT', 'A7XX_HLSQ_DP', - 'A7XX_HLSQ_DP_STR', 'A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK', - 'A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT', - 'A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_DS_CNTL_ENABLED', - 'A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_EVENT_CMD_EVENT__MASK', - 'A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT', - 'A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK', - 'A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT', 'A7XX_HLSQ_FRONTEND_META', - 'A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK', - 'A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT', - 'A7XX_HLSQ_FS_CNTL_0_UNK2__MASK', - 'A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT', 'A7XX_HLSQ_FS_CNTL_0_VARYINGS', - 'A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_FS_CNTL_ENABLED', - 'A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE', - 'A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM', - 'A7XX_HLSQ_GFX_CPS_CONST_RAM', 'A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG', - 'A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM', - 'A7XX_HLSQ_GFX_CVS_CONST_RAM', 'A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG', - 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM', - 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG', - 'A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_GS_CNTL_ENABLED', - 'A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_HS_CNTL_ENABLED', - 'A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', 'A7XX_HLSQ_ICB_CVS_CB_BASE_TAG', - 'A7XX_HLSQ_INDIRECT_META', 'A7XX_HLSQ_INST_RAM', - 'A7XX_HLSQ_INST_RAM_1', 'A7XX_HLSQ_INST_RAM_2', - 'A7XX_HLSQ_INST_RAM_TAG', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_IBO', - 'A7XX_HLSQ_INVALIDATE_CMD_CS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_DS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_FS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK', - 'A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT', - 'A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO', - 'A7XX_HLSQ_INVALIDATE_CMD_GS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_HS_STATE', - 'A7XX_HLSQ_INVALIDATE_CMD_VS_STATE', 'A7XX_HLSQ_L2STC_INFO_CMD', - 'A7XX_HLSQ_L2STC_TAG_RAM', 'A7XX_HLSQ_STATE', - 'A7XX_HLSQ_STPROC_META', - 'A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK', - 'A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT', - 'A7XX_HLSQ_UNKNOWN_A9AE_UNK8', 'A7XX_HLSQ_UNKNOWN_A9AE_UNK9', - 'A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK', - 'A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_VS_CNTL_ENABLED', - 'A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS', - 'A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK', - 'A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT', - 'A7XX_PC_POLYGON_MODE_MODE__MASK', - 'A7XX_PC_POLYGON_MODE_MODE__SHIFT', 'A7XX_PC_RASTER_CNTL_DISCARD', - 'A7XX_PC_RASTER_CNTL_STREAM__MASK', - 'A7XX_PC_RASTER_CNTL_STREAM__SHIFT', - 'A7XX_PC_RASTER_CNTL_V2_DISCARD', - 'A7XX_PC_RASTER_CNTL_V2_STREAM__MASK', - 'A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT', 'A7XX_PERF_BYPC_FULL', - 'A7XX_PERF_BYPC_FULL_CCHE_STALL', 'A7XX_PERF_BYPC_VHUB_STALL', - 'A7XX_PERF_BYPD_FULL', 'A7XX_PERF_BYPD_FULL_GBIF_STALL', - 'A7XX_PERF_CCHE_BANK_REQ0', 'A7XX_PERF_CCHE_BANK_REQ1', - 'A7XX_PERF_CCHE_BANK_REQ10', 'A7XX_PERF_CCHE_BANK_REQ11', - 'A7XX_PERF_CCHE_BANK_REQ12', 'A7XX_PERF_CCHE_BANK_REQ13', - 'A7XX_PERF_CCHE_BANK_REQ14', 'A7XX_PERF_CCHE_BANK_REQ15', - 'A7XX_PERF_CCHE_BANK_REQ2', 'A7XX_PERF_CCHE_BANK_REQ3', - 'A7XX_PERF_CCHE_BANK_REQ4', 'A7XX_PERF_CCHE_BANK_REQ5', - 'A7XX_PERF_CCHE_BANK_REQ6', 'A7XX_PERF_CCHE_BANK_REQ7', - 'A7XX_PERF_CCHE_BANK_REQ8', 'A7XX_PERF_CCHE_BANK_REQ9', - 'A7XX_PERF_CCHE_BUSY_CYCLES', 'A7XX_PERF_CCHE_DBANK_CONFLICT', - 'A7XX_PERF_CCHE_DPH_QUEUE_FULL', 'A7XX_PERF_CCHE_GBANK_REQ0', - 'A7XX_PERF_CCHE_GBANK_REQ1', 'A7XX_PERF_CCHE_GBANK_REQ2', - 'A7XX_PERF_CCHE_GBANK_REQ3', - 'A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST', - 'A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_SP', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_TP', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD', - 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC', - 'A7XX_PERF_CCHE_OPH_QUEUE_FULL', 'A7XX_PERF_CCHE_RAM_READ_REQ', - 'A7XX_PERF_CCHE_RAM_WRITE_REQ', - 'A7XX_PERF_CCHE_READ_REQUESTS_GMEM', - 'A7XX_PERF_CCHE_READ_REQUESTS_LRZ', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL', - 'A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL', - 'A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC', - 'A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL', - 'A7XX_PERF_CCHE_READ_REQUESTS_VPC', - 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF', - 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM', - 'A7XX_PERF_CCHE_STALL_CYCLES_TP', - 'A7XX_PERF_CCHE_STALL_CYCLES_UCHE', - 'A7XX_PERF_CCHE_TPH_CONFLICT_CL', 'A7XX_PERF_CCHE_TPH_EXT_FULL', - 'A7XX_PERF_CCHE_TPH_QUEUE_FULL', 'A7XX_PERF_CCHE_TPH_REF_FULL', - 'A7XX_PERF_CCHE_TPH_VICTIM_FULL', - 'A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES', - 'A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_SP', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_TP', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD', - 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC', - 'A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA', - 'A7XX_PERF_CCHE_WACK_QUEUE_FULL', - 'A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM', - 'A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ', - 'A7XX_PERF_CCHE_WRITE_REQUESTS_SP', 'A7XX_PERF_CCU_2D_RD_REQ', - 'A7XX_PERF_CCU_2D_WR_REQ', 'A7XX_PERF_CCU_BUSY_CYCLES', - 'A7XX_PERF_CCU_COLOR_BLOCKS', 'A7XX_PERF_CCU_COLOR_BLOCK_HIT', - 'A7XX_PERF_CCU_COLOR_EVB_STALL', - 'A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT', - 'A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER', - 'A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED', - 'A7XX_PERF_CCU_DEPTH_BLOCKS', 'A7XX_PERF_CCU_DEPTH_BLOCK_HIT', - 'A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT', - 'A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER', - 'A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED', - 'A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES', - 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA', - 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL', - 'A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', 'A7XX_PERF_CCU_GMEM_READ', - 'A7XX_PERF_CCU_GMEM_WRITE', 'A7XX_PERF_CCU_NEVER_COUNT', - 'A7XX_PERF_CCU_PARTIAL_BLOCK_READ', - 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C', - 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z', - 'A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE', - 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C', - 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z', - 'A7XX_PERF_CCU_RESERVED_100', 'A7XX_PERF_CCU_RESERVED_101', - 'A7XX_PERF_CCU_RESERVED_102', 'A7XX_PERF_CCU_RESERVED_103', - 'A7XX_PERF_CCU_RESERVED_104', 'A7XX_PERF_CCU_RESERVED_105', - 'A7XX_PERF_CCU_RESERVED_106', 'A7XX_PERF_CCU_RESERVED_107', - 'A7XX_PERF_CCU_RESERVED_108', 'A7XX_PERF_CCU_RESERVED_109', - 'A7XX_PERF_CCU_RESERVED_110', 'A7XX_PERF_CCU_RESERVED_111', - 'A7XX_PERF_CCU_RESERVED_112', 'A7XX_PERF_CCU_RESERVED_113', - 'A7XX_PERF_CCU_RESERVED_114', 'A7XX_PERF_CCU_RESERVED_115', - 'A7XX_PERF_CCU_RESERVED_116', 'A7XX_PERF_CCU_RESERVED_117', - 'A7XX_PERF_CCU_RESERVED_118', 'A7XX_PERF_CCU_RESERVED_119', - 'A7XX_PERF_CCU_RESERVED_120', 'A7XX_PERF_CCU_RESERVED_121', - 'A7XX_PERF_CCU_RESERVED_122', 'A7XX_PERF_CCU_RESERVED_123', - 'A7XX_PERF_CCU_RESERVED_124', 'A7XX_PERF_CCU_RESERVED_125', - 'A7XX_PERF_CCU_RESERVED_126', 'A7XX_PERF_CCU_RESERVED_127', - 'A7XX_PERF_CCU_RESERVED_32', 'A7XX_PERF_CCU_RESERVED_33', - 'A7XX_PERF_CCU_RESERVED_34', 'A7XX_PERF_CCU_RESERVED_35', - 'A7XX_PERF_CCU_RESERVED_36', 'A7XX_PERF_CCU_RESERVED_37', - 'A7XX_PERF_CCU_RESERVED_38', 'A7XX_PERF_CCU_RESERVED_39', - 'A7XX_PERF_CCU_RESERVED_40', 'A7XX_PERF_CCU_RESERVED_41', - 'A7XX_PERF_CCU_RESERVED_42', 'A7XX_PERF_CCU_RESERVED_43', - 'A7XX_PERF_CCU_RESERVED_44', 'A7XX_PERF_CCU_RESERVED_45', - 'A7XX_PERF_CCU_RESERVED_46', 'A7XX_PERF_CCU_RESERVED_47', - 'A7XX_PERF_CCU_RESERVED_48', 'A7XX_PERF_CCU_RESERVED_49', - 'A7XX_PERF_CCU_RESERVED_50', 'A7XX_PERF_CCU_RESERVED_51', - 'A7XX_PERF_CCU_RESERVED_52', 'A7XX_PERF_CCU_RESERVED_53', - 'A7XX_PERF_CCU_RESERVED_54', 'A7XX_PERF_CCU_RESERVED_55', - 'A7XX_PERF_CCU_RESERVED_56', 'A7XX_PERF_CCU_RESERVED_57', - 'A7XX_PERF_CCU_RESERVED_58', 'A7XX_PERF_CCU_RESERVED_59', - 'A7XX_PERF_CCU_RESERVED_60', 'A7XX_PERF_CCU_RESERVED_61', - 'A7XX_PERF_CCU_RESERVED_62', 'A7XX_PERF_CCU_RESERVED_63', - 'A7XX_PERF_CCU_RESERVED_78', 'A7XX_PERF_CCU_RESERVED_79', - 'A7XX_PERF_CCU_RESERVED_80', 'A7XX_PERF_CCU_RESERVED_81', - 'A7XX_PERF_CCU_RESERVED_82', 'A7XX_PERF_CCU_RESERVED_83', - 'A7XX_PERF_CCU_RESERVED_84', 'A7XX_PERF_CCU_RESERVED_85', - 'A7XX_PERF_CCU_RESERVED_86', 'A7XX_PERF_CCU_RESERVED_87', - 'A7XX_PERF_CCU_RESERVED_88', 'A7XX_PERF_CCU_RESERVED_89', - 'A7XX_PERF_CCU_RESERVED_90', 'A7XX_PERF_CCU_RESERVED_91', - 'A7XX_PERF_CCU_RESERVED_92', 'A7XX_PERF_CCU_RESERVED_93', - 'A7XX_PERF_CCU_RESERVED_94', 'A7XX_PERF_CCU_RESERVED_95', - 'A7XX_PERF_CCU_RESERVED_96', 'A7XX_PERF_CCU_RESERVED_97', - 'A7XX_PERF_CCU_RESERVED_98', 'A7XX_PERF_CCU_RESERVED_99', - 'A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE', - 'A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 'A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 'A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT', - 'A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT', - 'A7XX_PERF_CMPDECMP_CDP_FILTER_HIT', - 'A7XX_PERF_CMPDECMP_CDP_FILTER_MISS', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 'A7XX_PERF_CMPDECMP_NEVER_COUNT', - 'A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB', - 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 'A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 'A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST', - 'A7XX_PERF_CP_AHB_STALL_SQE_GMU', - 'A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER', - 'A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER', - 'A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS', - 'A7XX_PERF_CP_ALWAYS_COUNT', 'A7XX_PERF_CP_AQE_NUM_AS_CHUNKS', - 'A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', 'A7XX_PERF_CP_AQE_SQE_STALL', - 'A7XX_PERF_CP_BUSY_CYCLES', 'A7XX_PERF_CP_BUSY_GFX_CORE_IDLE', - 'A7XX_PERF_CP_CACHE_FLUSH', 'A7XX_PERF_CP_CLUSTER_FE_S_EMPTY', - 'A7XX_PERF_CP_CLUSTER_FE_S_FULL', - 'A7XX_PERF_CP_CLUSTER_FE_US_FULL', - 'A7XX_PERF_CP_CLUSTER_FE_U_EMPTY', - 'A7XX_PERF_CP_CLUSTER_GRAS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_GRAS_FULL', 'A7XX_PERF_CP_CLUSTER_PS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_PS_FULL', - 'A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_SP_PS_FULL', - 'A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_SP_VS_FULL', - 'A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_VPC_PS_FULL', - 'A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY', - 'A7XX_PERF_CP_CLUSTER_VPC_US_FULL', - 'A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY', - 'A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', 'A7XX_PERF_CP_CONTEXT_DONE', - 'A7XX_PERF_CP_DCACHE_HITS', 'A7XX_PERF_CP_DCACHE_MISSES', - 'A7XX_PERF_CP_DCACHE_STALLS', - 'A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', - 'A7XX_PERF_CP_ICACHE_HITS', 'A7XX_PERF_CP_ICACHE_MISSES', - 'A7XX_PERF_CP_ICACHE_STALL', 'A7XX_PERF_CP_ISR_CYCLES', - 'A7XX_PERF_CP_LONG_PREEMPTIONS', - 'A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH', - 'A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH', - 'A7XX_PERF_CP_MEMORY_POOL_EMPTY', - 'A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', 'A7XX_PERF_CP_MODE_SWITCH', - 'A7XX_PERF_CP_NEVER_COUNT', 'A7XX_PERF_CP_NUM_PREEMPTIONS', - 'A7XX_PERF_CP_OUTPUT_BLOCKED', 'A7XX_PERF_CP_PM4_DATA', - 'A7XX_PERF_CP_PM4_HEADERS', - 'A7XX_PERF_CP_PREDICATED_DRAWS_KILLED', - 'A7XX_PERF_CP_PREEMPTION_REACTION_DELAY', - 'A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 'A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 'A7XX_PERF_CP_SQE_AQE_STARVE', - 'A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', - 'A7XX_PERF_CP_SQE_DRAW_EXEC', 'A7XX_PERF_CP_SQE_EXEC_PROFILED', - 'A7XX_PERF_CP_SQE_IDLE', 'A7XX_PERF_CP_SQE_INSTR_COUNTER', - 'A7XX_PERF_CP_SQE_I_CACHE_STARVE', - 'A7XX_PERF_CP_SQE_LOAD_STATE_EXEC', - 'A7XX_PERF_CP_SQE_MD8_STALL_CYCLES', - 'A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES', - 'A7XX_PERF_CP_SQE_MRB_STARVE', 'A7XX_PERF_CP_SQE_PIPE_OUT_STALL', - 'A7XX_PERF_CP_SQE_PM4_STARVE_FSDT', - 'A7XX_PERF_CP_SQE_PM4_STARVE_IB1', - 'A7XX_PERF_CP_SQE_PM4_STARVE_IB2', - 'A7XX_PERF_CP_SQE_PM4_STARVE_IB3', - 'A7XX_PERF_CP_SQE_PM4_STARVE_RB', - 'A7XX_PERF_CP_SQE_PM4_STARVE_SDS', - 'A7XX_PERF_CP_SQE_PM4_WFI_STALL', 'A7XX_PERF_CP_SQE_RRB_STARVE', - 'A7XX_PERF_CP_SQE_SAVE_SDS_STATE', 'A7XX_PERF_CP_SQE_SYNC_STALL', - 'A7XX_PERF_CP_SQE_SYS_WFI_STALL', 'A7XX_PERF_CP_SQE_T4_EXEC', - 'A7XX_PERF_CP_SQE_VSD_STARVE', - 'A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH', - 'A7XX_PERF_CP_S_SKEW_BUFFER_FULL', 'A7XX_PERF_CP_VBIF_READ_BEATS', - 'A7XX_PERF_CP_VBIF_WRITE_BEATS', 'A7XX_PERF_CP_VSD_DECODE_STARVE', - 'A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', 'A7XX_PERF_CP_ZPASS_DONE', - 'A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS', - 'A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS', - 'A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS', - 'A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT', - 'A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS', - 'A7XX_PERF_CRE_RESOLVE_EVENTS', - 'A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS', - 'A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS', - 'A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT', - 'A7XX_PERF_DHUB_PTABLE_FULL', - 'A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL', - 'A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF', - 'A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF', - 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL', - 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL', - 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL', - 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL', - 'A7XX_PERF_GBIF_NEVER_COUNT', - 'A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS', - 'A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS', - 'A7XX_PERF_GBIF_RESERVED_1', 'A7XX_PERF_GBIF_RESERVED_100', - 'A7XX_PERF_GBIF_RESERVED_101', 'A7XX_PERF_GBIF_RESERVED_102', - 'A7XX_PERF_GBIF_RESERVED_103', 'A7XX_PERF_GBIF_RESERVED_104', - 'A7XX_PERF_GBIF_RESERVED_105', 'A7XX_PERF_GBIF_RESERVED_106', - 'A7XX_PERF_GBIF_RESERVED_107', 'A7XX_PERF_GBIF_RESERVED_108', - 'A7XX_PERF_GBIF_RESERVED_109', 'A7XX_PERF_GBIF_RESERVED_110', - 'A7XX_PERF_GBIF_RESERVED_111', 'A7XX_PERF_GBIF_RESERVED_112', - 'A7XX_PERF_GBIF_RESERVED_113', 'A7XX_PERF_GBIF_RESERVED_114', - 'A7XX_PERF_GBIF_RESERVED_115', 'A7XX_PERF_GBIF_RESERVED_116', - 'A7XX_PERF_GBIF_RESERVED_117', 'A7XX_PERF_GBIF_RESERVED_118', - 'A7XX_PERF_GBIF_RESERVED_119', 'A7XX_PERF_GBIF_RESERVED_12', - 'A7XX_PERF_GBIF_RESERVED_120', 'A7XX_PERF_GBIF_RESERVED_121', - 'A7XX_PERF_GBIF_RESERVED_122', 'A7XX_PERF_GBIF_RESERVED_123', - 'A7XX_PERF_GBIF_RESERVED_124', 'A7XX_PERF_GBIF_RESERVED_125', - 'A7XX_PERF_GBIF_RESERVED_126', 'A7XX_PERF_GBIF_RESERVED_127', - 'A7XX_PERF_GBIF_RESERVED_128', 'A7XX_PERF_GBIF_RESERVED_129', - 'A7XX_PERF_GBIF_RESERVED_13', 'A7XX_PERF_GBIF_RESERVED_130', - 'A7XX_PERF_GBIF_RESERVED_131', 'A7XX_PERF_GBIF_RESERVED_132', - 'A7XX_PERF_GBIF_RESERVED_133', 'A7XX_PERF_GBIF_RESERVED_134', - 'A7XX_PERF_GBIF_RESERVED_135', 'A7XX_PERF_GBIF_RESERVED_136', - 'A7XX_PERF_GBIF_RESERVED_137', 'A7XX_PERF_GBIF_RESERVED_138', - 'A7XX_PERF_GBIF_RESERVED_139', 'A7XX_PERF_GBIF_RESERVED_14', - 'A7XX_PERF_GBIF_RESERVED_140', 'A7XX_PERF_GBIF_RESERVED_141', - 'A7XX_PERF_GBIF_RESERVED_142', 'A7XX_PERF_GBIF_RESERVED_143', - 'A7XX_PERF_GBIF_RESERVED_144', 'A7XX_PERF_GBIF_RESERVED_145', - 'A7XX_PERF_GBIF_RESERVED_146', 'A7XX_PERF_GBIF_RESERVED_147', - 'A7XX_PERF_GBIF_RESERVED_148', 'A7XX_PERF_GBIF_RESERVED_149', - 'A7XX_PERF_GBIF_RESERVED_15', 'A7XX_PERF_GBIF_RESERVED_150', - 'A7XX_PERF_GBIF_RESERVED_151', 'A7XX_PERF_GBIF_RESERVED_152', - 'A7XX_PERF_GBIF_RESERVED_153', 'A7XX_PERF_GBIF_RESERVED_154', - 'A7XX_PERF_GBIF_RESERVED_155', 'A7XX_PERF_GBIF_RESERVED_156', - 'A7XX_PERF_GBIF_RESERVED_16', 'A7XX_PERF_GBIF_RESERVED_17', - 'A7XX_PERF_GBIF_RESERVED_18', 'A7XX_PERF_GBIF_RESERVED_19', - 'A7XX_PERF_GBIF_RESERVED_2', 'A7XX_PERF_GBIF_RESERVED_20', - 'A7XX_PERF_GBIF_RESERVED_21', 'A7XX_PERF_GBIF_RESERVED_24', - 'A7XX_PERF_GBIF_RESERVED_25', 'A7XX_PERF_GBIF_RESERVED_26', - 'A7XX_PERF_GBIF_RESERVED_27', 'A7XX_PERF_GBIF_RESERVED_28', - 'A7XX_PERF_GBIF_RESERVED_29', 'A7XX_PERF_GBIF_RESERVED_3', - 'A7XX_PERF_GBIF_RESERVED_30', 'A7XX_PERF_GBIF_RESERVED_31', - 'A7XX_PERF_GBIF_RESERVED_32', 'A7XX_PERF_GBIF_RESERVED_33', - 'A7XX_PERF_GBIF_RESERVED_36', 'A7XX_PERF_GBIF_RESERVED_37', - 'A7XX_PERF_GBIF_RESERVED_38', 'A7XX_PERF_GBIF_RESERVED_39', - 'A7XX_PERF_GBIF_RESERVED_4', 'A7XX_PERF_GBIF_RESERVED_40', - 'A7XX_PERF_GBIF_RESERVED_41', 'A7XX_PERF_GBIF_RESERVED_42', - 'A7XX_PERF_GBIF_RESERVED_43', 'A7XX_PERF_GBIF_RESERVED_44', - 'A7XX_PERF_GBIF_RESERVED_45', 'A7XX_PERF_GBIF_RESERVED_48', - 'A7XX_PERF_GBIF_RESERVED_49', 'A7XX_PERF_GBIF_RESERVED_5', - 'A7XX_PERF_GBIF_RESERVED_50', 'A7XX_PERF_GBIF_RESERVED_51', - 'A7XX_PERF_GBIF_RESERVED_52', 'A7XX_PERF_GBIF_RESERVED_53', - 'A7XX_PERF_GBIF_RESERVED_54', 'A7XX_PERF_GBIF_RESERVED_55', - 'A7XX_PERF_GBIF_RESERVED_56', 'A7XX_PERF_GBIF_RESERVED_57', - 'A7XX_PERF_GBIF_RESERVED_58', 'A7XX_PERF_GBIF_RESERVED_59', - 'A7XX_PERF_GBIF_RESERVED_6', 'A7XX_PERF_GBIF_RESERVED_60', - 'A7XX_PERF_GBIF_RESERVED_61', 'A7XX_PERF_GBIF_RESERVED_62', - 'A7XX_PERF_GBIF_RESERVED_63', 'A7XX_PERF_GBIF_RESERVED_64', - 'A7XX_PERF_GBIF_RESERVED_65', 'A7XX_PERF_GBIF_RESERVED_66', - 'A7XX_PERF_GBIF_RESERVED_67', 'A7XX_PERF_GBIF_RESERVED_7', - 'A7XX_PERF_GBIF_RESERVED_78', 'A7XX_PERF_GBIF_RESERVED_79', - 'A7XX_PERF_GBIF_RESERVED_8', 'A7XX_PERF_GBIF_RESERVED_80', - 'A7XX_PERF_GBIF_RESERVED_81', 'A7XX_PERF_GBIF_RESERVED_82', - 'A7XX_PERF_GBIF_RESERVED_83', 'A7XX_PERF_GBIF_RESERVED_84', - 'A7XX_PERF_GBIF_RESERVED_85', 'A7XX_PERF_GBIF_RESERVED_86', - 'A7XX_PERF_GBIF_RESERVED_87', 'A7XX_PERF_GBIF_RESERVED_88', - 'A7XX_PERF_GBIF_RESERVED_89', 'A7XX_PERF_GBIF_RESERVED_9', - 'A7XX_PERF_GBIF_RESERVED_90', 'A7XX_PERF_GBIF_RESERVED_91', - 'A7XX_PERF_GBIF_RESERVED_92', 'A7XX_PERF_GBIF_RESERVED_93', - 'A7XX_PERF_GBIF_RESERVED_94', 'A7XX_PERF_GBIF_RESERVED_95', - 'A7XX_PERF_GBIF_RESERVED_96', 'A7XX_PERF_GBIF_RESERVED_97', - 'A7XX_PERF_GBIF_RESERVED_98', 'A7XX_PERF_GBIF_RESERVED_99', - 'A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL', - 'A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS', - 'A7XX_PERF_HLSQ_BUSY_CYCLES', 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT', - 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC', - 'A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING', - 'A7XX_PERF_HLSQ_BV_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_BV_S2W_CYCLES', 'A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_BV_STALL_CYCLES', 'A7XX_PERF_HLSQ_BV_WAIT_FS_S2W', - 'A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS', - 'A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE', - 'A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 'A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 'A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 'A7XX_PERF_HLSQ_FS_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_FS_S2W_CYCLES', 'A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_FS_STALL_CYCLES', 'A7XX_PERF_HLSQ_FS_STARVING_SP', - 'A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W', - 'A7XX_PERF_HLSQ_FS_WAIT_VS_S2W', - 'A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT', - 'A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT', - 'A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES', - 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ', - 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP', - 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_SP', 'A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT', - 'A7XX_PERF_HLSQ_L2STC_REQ_UCHE', - 'A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ', - 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT', - 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC', - 'A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES', - 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_LPAC_STALL_CYCLES', - 'A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W', - 'A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W', - 'A7XX_PERF_HLSQ_NEVER_COUNT', 'A7XX_PERF_HLSQ_PRIMITIVE_COUNT', - 'A7XX_PERF_HLSQ_RESERVED_19', 'A7XX_PERF_HLSQ_RESERVED_20', - 'A7XX_PERF_HLSQ_RESERVED_37', 'A7XX_PERF_HLSQ_RESERVED_7', - 'A7XX_PERF_HLSQ_RESERVED_8', 'A7XX_PERF_HLSQ_RESERVED_9', - 'A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC', - 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS', - 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE', - 'A7XX_PERF_HLSQ_STALL_CYCLES_UCHE', - 'A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT', - 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_HIT', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE', - 'A7XX_PERF_HLSQ_STPROC_L0_INS_MISS', - 'A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC', - 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS', - 'A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT', - 'A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP', - 'A7XX_PERF_HLSQ_VSBR_STALL_CYCLES', - 'A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ', - 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING', - 'A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC', - 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY', - 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL', - 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ', - 'A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 'A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING', - 'A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI', - 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD', - 'A7XX_PERF_LRZ_BUSY_CYCLES', 'A7XX_PERF_LRZ_FEEDBACK_ACCEPT', - 'A7XX_PERF_LRZ_FEEDBACK_DISCARD', 'A7XX_PERF_LRZ_FEEDBACK_STALL', - 'A7XX_PERF_LRZ_FULL_8X8_TILES', 'A7XX_PERF_LRZ_LRZ_READ', - 'A7XX_PERF_LRZ_LRZ_WRITE', 'A7XX_PERF_LRZ_MERGE_CACHE_UPDATING', - 'A7XX_PERF_LRZ_NEVER_COUNT', 'A7XX_PERF_LRZ_NUM_FLOCK', - 'A7XX_PERF_LRZ_PARTIAL_8X8_TILES', - 'A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ', - 'A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 'A7XX_PERF_LRZ_RAS_MASK_TRANS', 'A7XX_PERF_LRZ_READ_LATENCY', - 'A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR', - 'A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH', - 'A7XX_PERF_LRZ_STALL_CYCLES_MVC', 'A7XX_PERF_LRZ_STALL_CYCLES_RB', - 'A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 'A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE', - 'A7XX_PERF_LRZ_STALL_CYCLES_UCHE', - 'A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_LRZ_STALL_CYCLES_VSC', - 'A7XX_PERF_LRZ_STARVE_CYCLES_RAS', 'A7XX_PERF_LRZ_TILE_KILLED', - 'A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS', - 'A7XX_PERF_LRZ_TILE_KILLED_BY_Z', 'A7XX_PERF_LRZ_TOTAL_PIXEL', - 'A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 'A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', - 'A7XX_PERF_PC_NEVER_COUNT', 'A7XX_PERF_PC_RESERVED_51', - 'A7XX_PERF_PC_RESERVED_52', 'A7XX_PERF_PC_RESERVED_53', - 'A7XX_PERF_PC_RESERVED_54', 'A7XX_PERF_PC_RESERVED_55', - 'A7XX_PERF_PC_RESERVED_56', 'A7XX_PERF_PC_RESERVED_57', - 'A7XX_PERF_PC_RESERVED_58', 'A7XX_PERF_PC_RESERVED_59', - 'A7XX_PERF_PC_S_BUSY_CYCLES', 'A7XX_PERF_PC_S_DS_INVOCATIONS', - 'A7XX_PERF_PC_S_DS_PRIMITIVES', 'A7XX_PERF_PC_S_GS_INVOCATIONS', - 'A7XX_PERF_PC_S_HS_INVOCATIONS', 'A7XX_PERF_PC_S_IA_PRIMITIVES', - 'A7XX_PERF_PC_S_IA_VERTICES', 'A7XX_PERF_PC_S_MESH_VS_WAVES', - 'A7XX_PERF_PC_S_STALL_CYCLES_TESS', - 'A7XX_PERF_PC_S_STALL_CYCLES_VFD', - 'A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY', - 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE', - 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY', - 'A7XX_PERF_PC_S_TESS_BUSY_CYCLES', - 'A7XX_PERF_PC_S_TESS_FACTOR_TRANS', - 'A7XX_PERF_PC_S_TESS_PC_UV_PATCHES', - 'A7XX_PERF_PC_S_TESS_PC_UV_TRANS', - 'A7XX_PERF_PC_S_TESS_PID_ACTIVE', - 'A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE', - 'A7XX_PERF_PC_S_TESS_SETUP_ACTIVE', - 'A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC', - 'A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC', - 'A7XX_PERF_PC_S_TESS_WORKING_CYCLES', - 'A7XX_PERF_PC_S_VERTEX_HITS', 'A7XX_PERF_PC_S_VPC_PRIMITIVES', - 'A7XX_PERF_PC_S_VS_INVOCATIONS', 'A7XX_PERF_PC_S_WORKING_CYCLES', - 'A7XX_PERF_PC_US_2D_DRAWCALLS', 'A7XX_PERF_PC_US_3D_DRAWCALLS', - 'A7XX_PERF_PC_US_BR2BV_SWITCH', - 'A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD', - 'A7XX_PERF_PC_US_BUSY_CYCLES', 'A7XX_PERF_PC_US_BV2BR_SWITCH', - 'A7XX_PERF_PC_US_BV_STALLED_BY_ATTR', - 'A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK', - 'A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD', - 'A7XX_PERF_PC_US_BV_STARVED_BY_RARB', 'A7XX_PERF_PC_US_DEAD_PRIM', - 'A7XX_PERF_PC_US_DP0_INPUT_STALLS', - 'A7XX_PERF_PC_US_DP0_LIVE_PRIM', 'A7XX_PERF_PC_US_DP0_RARB_FULL', - 'A7XX_PERF_PC_US_DP1_INPUT_STALLS', - 'A7XX_PERF_PC_US_DP1_LIVE_PRIM', 'A7XX_PERF_PC_US_DP1_RARB_FULL', - 'A7XX_PERF_PC_US_INSTANCES', 'A7XX_PERF_PC_US_MESH_DEAD_DRAWS', - 'A7XX_PERF_PC_US_MESH_DEAD_PRIM', 'A7XX_PERF_PC_US_MESH_DRAWS', - 'A7XX_PERF_PC_US_MESH_LIVE_PRIM', - 'A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS', - 'A7XX_PERF_PC_US_MESH_PA_EN_PRIM', - 'A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS', - 'A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES', - 'A7XX_PERF_PC_US_PASSPAIR_STALL', - 'A7XX_PERF_PC_US_PREDRAW_STALLS', - 'A7XX_PERF_PC_US_SLICE_LIVE_PRIM', - 'A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX', - 'A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE', - 'A7XX_PERF_PC_US_STALL_CYCLES_PC_S', - 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE0', - 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE1', - 'A7XX_PERF_PC_US_STARVE_CYCLES_DI', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF', - 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM', - 'A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW', - 'A7XX_PERF_PC_US_UCHE_0_TRANS', 'A7XX_PERF_PC_US_UCHE_1_TRANS', - 'A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS', - 'A7XX_PERF_PC_US_VIS_STREAMS_LOADED', - 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR', - 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV', - 'A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL', - 'A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL', - 'A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL', - 'A7XX_PERF_PC_US_WORKING_CYCLES', 'A7XX_PERF_RAS_8X4_TILES', - 'A7XX_PERF_RAS_BLOCKS', 'A7XX_PERF_RAS_BUSY_CYCLES', - 'A7XX_PERF_RAS_FALSE_PARTIAL_STILE', - 'A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES', - 'A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES', - 'A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES', - 'A7XX_PERF_RAS_MASKGEN_ACTIVE', 'A7XX_PERF_RAS_NEVER_COUNT', - 'A7XX_PERF_RAS_PRIM_KILLED_INVISILBE', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2', - 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2', - 'A7XX_PERF_RAS_SLICE_BLOCK_EMPTY', - 'A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY', - 'A7XX_PERF_RAS_STALL_CYCLES_LRZ', - 'A7XX_PERF_RAS_STARVE_CYCLES_TSE', - 'A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 'A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', - 'A7XX_PERF_RAS_SUPER_TILES', 'A7XX_PERF_RBBM_NEVER_COUNT', - 'A7XX_PERF_RBBM_S_HLSQ_BUSY', 'A7XX_PERF_RBBM_S_PC_BUSY', - 'A7XX_PERF_RBBM_S_RAS_BUSY', 'A7XX_PERF_RBBM_S_TESS_BUSY', - 'A7XX_PERF_RBBM_S_TSEBE_BUSY', 'A7XX_PERF_RBBM_S_TSEFE_BUSY', - 'A7XX_PERF_RBBM_US_ALWAYS_COUNT', 'A7XX_PERF_RBBM_US_ALWAYS_ON', - 'A7XX_PERF_RBBM_US_COM_BUSY', 'A7XX_PERF_RBBM_US_DCOM_BUSY', - 'A7XX_PERF_RBBM_US_HLSQ_BUSY', 'A7XX_PERF_RBBM_US_PC_BUSY', - 'A7XX_PERF_RBBM_US_STATUS_MASKED', 'A7XX_PERF_RBBM_US_UCHE_BUSY', - 'A7XX_PERF_RBBM_US_VBIF_BUSY', 'A7XX_PERF_RBBM_US_VSC_BUSY', - 'A7XX_PERF_RB_2D_ALIVE_CYCLES', - 'A7XX_PERF_RB_2D_STARVE_CYCLES_SP', - 'A7XX_PERF_RB_2D_VALID_PIXELS', 'A7XX_PERF_RB_3D_PIXELS', - 'A7XX_PERF_RB_BLENDED_FP16_COMPONENTS', - 'A7XX_PERF_RB_BLENDED_FP32_COMPONENTS', - 'A7XX_PERF_RB_BLENDED_FXP_COMPONENTS', - 'A7XX_PERF_RB_BLENDER_WORKING_CYCLES', 'A7XX_PERF_RB_BUSY_CYCLES', - 'A7XX_PERF_RB_COLOR_PIX_TILES', - 'A7XX_PERF_RB_CPROC_WORKING_CYCLES', 'A7XX_PERF_RB_C_READ', - 'A7XX_PERF_RB_C_WRITE', 'A7XX_PERF_RB_EARLY_Z_ARB3_GRANT', - 'A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', 'A7XX_PERF_RB_HLSQ_ACTIVE', - 'A7XX_PERF_RB_LATE_Z_ARB3_GRANT', 'A7XX_PERF_RB_NEVER_COUNT', - 'A7XX_PERF_RB_PS_INVOCATIONS', - 'A7XX_PERF_RB_SAMPLER_WORKING_CYCLES', - 'A7XX_PERF_RB_STALL_CYCLES_CCU', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 'A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL', - 'A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL', - 'A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL', - 'A7XX_PERF_RB_STALL_CYCLES_HLSQ', - 'A7XX_PERF_RB_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE', - 'A7XX_PERF_RB_STARVE_CYCLES_CCU', - 'A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE', - 'A7XX_PERF_RB_STARVE_CYCLES_SP', - 'A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', 'A7XX_PERF_RB_S_FAIL', - 'A7XX_PERF_RB_TOTAL_PASS', 'A7XX_PERF_RB_VRS_1X1_QUADS', - 'A7XX_PERF_RB_VRS_1X2_QUADS', 'A7XX_PERF_RB_VRS_2X1_QUADS', - 'A7XX_PERF_RB_VRS_2X2_QUADS', 'A7XX_PERF_RB_VRS_2X4_QUADS', - 'A7XX_PERF_RB_VRS_4X2_QUADS', 'A7XX_PERF_RB_VRS_4X4_QUADS', - 'A7XX_PERF_RB_ZPROC_WORKING_CYCLES', 'A7XX_PERF_RB_Z_FAIL', - 'A7XX_PERF_RB_Z_PASS', 'A7XX_PERF_RB_Z_READ', - 'A7XX_PERF_RB_Z_WORKLOAD', 'A7XX_PERF_RB_Z_WRITE', - 'A7XX_PERF_SP_ADDR_LOCK_COUNT', - 'A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES', - 'A7XX_PERF_SP_ALU_GPR_READ_CYCLES', - 'A7XX_PERF_SP_ALU_WORKING_CYCLES', 'A7XX_PERF_SP_ANY_EU_WORKING', - 'A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE', - 'A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE', - 'A7XX_PERF_SP_ANY_EU_WORKING_LPAC', - 'A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE', - 'A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS', - 'A7XX_PERF_SP_BRANCH_INS_COUNT', - 'A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT', - 'A7XX_PERF_SP_BRANCH_NOT_TAKEN', 'A7XX_PERF_SP_BRANCH_TAKEN', - 'A7XX_PERF_SP_BUSY_CYCLES', 'A7XX_PERF_SP_BYPASS_BUSY_CYCLES', - 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD', - 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ', - 'A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD', - 'A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', 'A7XX_PERF_SP_CS_INSTRUCTIONS', - 'A7XX_PERF_SP_CS_INVOCATIONS', - 'A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES', - 'A7XX_PERF_SP_DS_INSTRUCTIONS', 'A7XX_PERF_SP_EFU_WORKING_CYCLES', - 'A7XX_PERF_SP_EWAVE_CONTEXTS', - 'A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES', - 'A7XX_PERF_SP_EXECUTABLE_WAVES', 'A7XX_PERF_SP_EXPORT_RB_TRANS', - 'A7XX_PERF_SP_EXPORT_VPC_TRANS', - 'A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 'A7XX_PERF_SP_FS_INSTRUCTIONS', 'A7XX_PERF_SP_FS_OOO_WAVE_ACC', - 'A7XX_PERF_SP_FS_STAGE_1X_WAVES', - 'A7XX_PERF_SP_FS_STAGE_2X_WAVES', - 'A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES', - 'A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION', - 'A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 'A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES', - 'A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES', - 'A7XX_PERF_SP_FS_WAVE_REQ_PENDING', - 'A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS', - 'A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS', - 'A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS', - 'A7XX_PERF_SP_GM_ATOMICS', 'A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS', - 'A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES', - 'A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 'A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', 'A7XX_PERF_SP_GPR_READ', - 'A7XX_PERF_SP_GPR_READ_BANK', 'A7XX_PERF_SP_GPR_READ_CONFLICT', - 'A7XX_PERF_SP_GPR_READ_PREFETCH', 'A7XX_PERF_SP_GPR_WRITE', - 'A7XX_PERF_SP_GPR_WRITE_BANK', 'A7XX_PERF_SP_GPR_WRITE_CONFLICT', - 'A7XX_PERF_SP_GS_INSTRUCTIONS', - 'A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS', - 'A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS', - 'A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS', - 'A7XX_PERF_SP_HS_INSTRUCTIONS', 'A7XX_PERF_SP_ICL1_MISSES', - 'A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES', - 'A7XX_PERF_SP_ICL1_REQUESTS', 'A7XX_PERF_SP_LB_ALU_READ_CONS', - 'A7XX_PERF_SP_LB_LDST_RW_LM', - 'A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED', - 'A7XX_PERF_SP_LB_LDST_WRITE_CONS', - 'A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED', - 'A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD', - 'A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ', - 'A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER', - 'A7XX_PERF_SP_LB_READ_XFER_ALU', - 'A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER', - 'A7XX_PERF_SP_LB_WRITE_XFER_VPC', 'A7XX_PERF_SP_LM_ATOMICS', - 'A7XX_PERF_SP_LM_BANK_CONFLICTS', 'A7XX_PERF_SP_LM_FULL_CYCLES', - 'A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS', - 'A7XX_PERF_SP_LM_STORE_INSTRUCTIONS', - 'A7XX_PERF_SP_LM_WORKING_CYCLES', - 'A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 'A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 'A7XX_PERF_SP_LPAC_BUSY_CYCLES', 'A7XX_PERF_SP_LPAC_DRAWCALLS', - 'A7XX_PERF_SP_LPAC_INSTRUCTIONS', - 'A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', 'A7XX_PERF_SP_NEVER_COUNT', - 'A7XX_PERF_SP_NON_EXECUTION_CYCLES', - 'A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES', - 'A7XX_PERF_SP_OUTPUT_3D_PIXELS', - 'A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', 'A7XX_PERF_SP_PIXELS', - 'A7XX_PERF_SP_PIXELS_KILLED', 'A7XX_PERF_SP_PI_WORKING_CYCLES', - 'A7XX_PERF_SP_PREDICT_INS_COUNT', - 'A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT', - 'A7XX_PERF_SP_PREDICT_NOT_TAKEN', 'A7XX_PERF_SP_PREDICT_TAKEN', - 'A7XX_PERF_SP_QUADS', 'A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS', - 'A7XX_PERF_SP_RBRT_KICKOFF_DQUADS', - 'A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', 'A7XX_PERF_SP_RESERVED_86', - 'A7XX_PERF_SP_RTU_BUSY_CYCLES', - 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES', - 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES', - 'A7XX_PERF_SP_RTU_L0_HITS', 'A7XX_PERF_SP_RTU_L0_HIT_ON_MISS', - 'A7XX_PERF_SP_RTU_L0_MISSES', - 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO', - 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0', - 'A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS', - 'A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE', - 'A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE', - 'A7XX_PERF_SP_SCH_STALL_CYCLES_RTU', - 'A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES', - 'A7XX_PERF_SP_STALL_CYCLES_RB', 'A7XX_PERF_SP_STALL_CYCLES_TP', - 'A7XX_PERF_SP_STALL_CYCLES_UCHE', - 'A7XX_PERF_SP_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_SP_STARVE_CYCLES_HLSQ', - 'A7XX_PERF_SP_STCHE_MISS_INC_BV', - 'A7XX_PERF_SP_STCHE_MISS_INC_FS', - 'A7XX_PERF_SP_STCHE_MISS_INC_LPAC', - 'A7XX_PERF_SP_STCHE_MISS_INC_VS', - 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES', - 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES', - 'A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES', - 'A7XX_PERF_SP_UCHE_READ_TRANS', 'A7XX_PERF_SP_UCHE_WRITE_TRANS', - 'A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS', - 'A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS', - 'A7XX_PERF_SP_VS_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES', - 'A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 'A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES', - 'A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES', - 'A7XX_PERF_SP_VS_WAVE_REQ_PENDING', - 'A7XX_PERF_SP_WAVE_ALU_CYCLES', 'A7XX_PERF_SP_WAVE_CONTEXTS', - 'A7XX_PERF_SP_WAVE_CONTEXT_CYCLES', - 'A7XX_PERF_SP_WAVE_CSP_CYCLES', 'A7XX_PERF_SP_WAVE_CTRL_CYCLES', - 'A7XX_PERF_SP_WAVE_EFU_CYCLES', 'A7XX_PERF_SP_WAVE_EMIT_CYCLES', - 'A7XX_PERF_SP_WAVE_END_CYCLES', 'A7XX_PERF_SP_WAVE_FETCH_CYCLES', - 'A7XX_PERF_SP_WAVE_HWAVE_SYNC', - 'A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES', - 'A7XX_PERF_SP_WAVE_IDLE_CYCLES', 'A7XX_PERF_SP_WAVE_INPUT_CYCLES', - 'A7XX_PERF_SP_WAVE_INT_CYCLES', 'A7XX_PERF_SP_WAVE_JOIN_CYCLES', - 'A7XX_PERF_SP_WAVE_LOAD_CYCLES', - 'A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES', - 'A7XX_PERF_SP_WAVE_NOP_CYCLES', 'A7XX_PERF_SP_WAVE_OUTPUT_CYCLES', - 'A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 'A7XX_PERF_SP_WAVE_SPLIT_CNT', 'A7XX_PERF_SP_WAVE_WAIT_CYCLES', - 'A7XX_PERF_SP_WORKING_EU', 'A7XX_PERF_SP_WORKING_EU_CS_STAGE', - 'A7XX_PERF_SP_WORKING_EU_FS_STAGE', - 'A7XX_PERF_SP_WORKING_EU_VS_STAGE', - 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT', - 'A7XX_PERF_TP_2D_OUTPUT_PIXELS', - 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT', - 'A7XX_PERF_TP_BACKEND_WORKING_CYCLES', 'A7XX_PERF_TP_BUSY_CYCLES', - 'A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED', - 'A7XX_PERF_TP_FILTER_POINT_FP16', - 'A7XX_PERF_TP_FILTER_POINT_FP32', - 'A7XX_PERF_TP_FILTER_WORKLOAD_16BIT', - 'A7XX_PERF_TP_FILTER_WORKLOAD_32BIT', - 'A7XX_PERF_TP_FLAG_CACHE_MISSES', - 'A7XX_PERF_TP_FLAG_CACHE_REQUESTS', - 'A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES', - 'A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES', - 'A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR', - 'A7XX_PERF_TP_FORMAT_DECOMP_POINT', - 'A7XX_PERF_TP_FRONTEND_WORKING_CYCLES', - 'A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 'A7XX_PERF_TP_L1_5_COMPRESS_REQS', - 'A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS', - 'A7XX_PERF_TP_L1_5_L2_REQUESTS', - 'A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 'A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS', - 'A7XX_PERF_TP_L1_BANK_CONFLICT', - 'A7XX_PERF_TP_L1_CACHELINE_MISSES', - 'A7XX_PERF_TP_L1_CACHELINE_REQUESTS', - 'A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 'A7XX_PERF_TP_L1_MISSES_ASTC_1TILE', - 'A7XX_PERF_TP_L1_MISSES_ASTC_2TILE', - 'A7XX_PERF_TP_L1_MISSES_ASTC_4TILE', - 'A7XX_PERF_TP_L1_TAG_WORKING_CYCLES', - 'A7XX_PERF_TP_LATENCY_CYCLES', 'A7XX_PERF_TP_LATENCY_FIFO_FULL', - 'A7XX_PERF_TP_LATENCY_TRANS', 'A7XX_PERF_TP_NEVER_COUNT', - 'A7XX_PERF_TP_OUTPUT_PIXELS', 'A7XX_PERF_TP_OUTPUT_PIXELS_ANISO', - 'A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR', - 'A7XX_PERF_TP_OUTPUT_PIXELS_MIP', - 'A7XX_PERF_TP_OUTPUT_PIXELS_POINT', - 'A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16', - 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32', - 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16', - 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32', - 'A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 'A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', 'A7XX_PERF_TP_QUADS_1D', - 'A7XX_PERF_TP_QUADS_2D', 'A7XX_PERF_TP_QUADS_3D', - 'A7XX_PERF_TP_QUADS_ARRAY', 'A7XX_PERF_TP_QUADS_BUFFER', - 'A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 'A7XX_PERF_TP_QUADS_CUBE', 'A7XX_PERF_TP_QUADS_GRADIENT', - 'A7XX_PERF_TP_QUADS_OFFSET', 'A7XX_PERF_TP_QUADS_RECEIVED', - 'A7XX_PERF_TP_QUADS_SHADOW', 'A7XX_PERF_TP_RESERVED_100', - 'A7XX_PERF_TP_RESERVED_101', 'A7XX_PERF_TP_RESERVED_102', - 'A7XX_PERF_TP_RESERVED_103', 'A7XX_PERF_TP_RESERVED_104', - 'A7XX_PERF_TP_RESERVED_105', 'A7XX_PERF_TP_RESERVED_106', - 'A7XX_PERF_TP_RESERVED_107', 'A7XX_PERF_TP_RESERVED_108', - 'A7XX_PERF_TP_RESERVED_109', 'A7XX_PERF_TP_RESERVED_110', - 'A7XX_PERF_TP_RESERVED_111', 'A7XX_PERF_TP_RESERVED_112', - 'A7XX_PERF_TP_RESERVED_113', 'A7XX_PERF_TP_RESERVED_114', - 'A7XX_PERF_TP_RESERVED_115', 'A7XX_PERF_TP_RESERVED_116', - 'A7XX_PERF_TP_RESERVED_117', 'A7XX_PERF_TP_RESERVED_118', - 'A7XX_PERF_TP_RESERVED_119', 'A7XX_PERF_TP_RESERVED_120', - 'A7XX_PERF_TP_RESERVED_121', 'A7XX_PERF_TP_RESERVED_122', - 'A7XX_PERF_TP_RESERVED_123', 'A7XX_PERF_TP_RESERVED_124', - 'A7XX_PERF_TP_RESERVED_125', 'A7XX_PERF_TP_RESERVED_126', - 'A7XX_PERF_TP_RESERVED_127', 'A7XX_PERF_TP_RESERVED_62', - 'A7XX_PERF_TP_RESERVED_63', 'A7XX_PERF_TP_RESERVED_64', - 'A7XX_PERF_TP_RESERVED_65', 'A7XX_PERF_TP_RESERVED_66', - 'A7XX_PERF_TP_RESERVED_67', 'A7XX_PERF_TP_RESERVED_68', - 'A7XX_PERF_TP_RESERVED_69', 'A7XX_PERF_TP_RESERVED_70', - 'A7XX_PERF_TP_RESERVED_71', 'A7XX_PERF_TP_RESERVED_72', - 'A7XX_PERF_TP_RESERVED_73', 'A7XX_PERF_TP_RESERVED_74', - 'A7XX_PERF_TP_RESERVED_75', 'A7XX_PERF_TP_RESERVED_76', - 'A7XX_PERF_TP_RESERVED_77', 'A7XX_PERF_TP_RESERVED_78', - 'A7XX_PERF_TP_RESERVED_79', 'A7XX_PERF_TP_RESERVED_80', - 'A7XX_PERF_TP_RESERVED_81', 'A7XX_PERF_TP_RESERVED_82', - 'A7XX_PERF_TP_RESERVED_83', 'A7XX_PERF_TP_RESERVED_84', - 'A7XX_PERF_TP_RESERVED_85', 'A7XX_PERF_TP_RESERVED_86', - 'A7XX_PERF_TP_RESERVED_87', 'A7XX_PERF_TP_RESERVED_88', - 'A7XX_PERF_TP_RESERVED_89', 'A7XX_PERF_TP_RESERVED_90', - 'A7XX_PERF_TP_RESERVED_91', 'A7XX_PERF_TP_RESERVED_92', - 'A7XX_PERF_TP_RESERVED_93', 'A7XX_PERF_TP_RESERVED_94', - 'A7XX_PERF_TP_RESERVED_95', 'A7XX_PERF_TP_RESERVED_96', - 'A7XX_PERF_TP_RESERVED_97', 'A7XX_PERF_TP_RESERVED_98', - 'A7XX_PERF_TP_RESERVED_99', 'A7XX_PERF_TP_SP_TP_TRANS', - 'A7XX_PERF_TP_STALL_CYCLES_UCHE', 'A7XX_PERF_TP_STALL_CYCLES_UFC', - 'A7XX_PERF_TP_STARVE_CYCLES_SP', - 'A7XX_PERF_TP_STARVE_CYCLES_UCHE', 'A7XX_PERF_TP_TPA2TPC_TRANS', - 'A7XX_PERF_TP_TP_SP_TRANS', 'A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES', - 'A7XX_PERF_TSE_BE_2D_INPUT_PRIM', - 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP', - 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY', - 'A7XX_PERF_TSE_BE_BUSY_CYCLES', - 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR', - 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP', - 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY', - 'A7XX_PERF_TSE_BE_CINVOCATION', 'A7XX_PERF_TSE_BE_CLIPPED_PRIM', - 'A7XX_PERF_TSE_BE_CLIPPING_CYCLES', - 'A7XX_PERF_TSE_BE_CLIP_PLANES', 'A7XX_PERF_TSE_BE_CPRIMITIVES', - 'A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM', - 'A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM', - 'A7XX_PERF_TSE_BE_EXCLUDED_PRIM', - 'A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM', - 'A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM', - 'A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', 'A7XX_PERF_TSE_BE_INPUT_PRIM', - 'A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM', - 'A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM', - 'A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE', - 'A7XX_PERF_TSE_BE_STALL_CYCLES_RAS', - 'A7XX_PERF_TSE_BE_STARVE_CYCLES_PC', - 'A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM', - 'A7XX_PERF_TSE_BE_VP_OUT_IS_NAN', - 'A7XX_PERF_TSE_BE_ZERO_AREA_PRIM', - 'A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM', - 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP', - 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY', - 'A7XX_PERF_TSE_FE_BUSY_CYCLES', - 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR', - 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP', - 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY', - 'A7XX_PERF_TSE_FE_CINVOCATION', 'A7XX_PERF_TSE_FE_CLIP_PLANES', - 'A7XX_PERF_TSE_FE_CPRIMITIVES', - 'A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM', - 'A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM', - 'A7XX_PERF_TSE_FE_EXCLUDED_PRIM', - 'A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM', - 'A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM', - 'A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', 'A7XX_PERF_TSE_FE_INPUT_PRIM', - 'A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM', - 'A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM', - 'A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS', - 'A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US', - 'A7XX_PERF_TSE_FE_STARVE_CYCLES_PC', - 'A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM', - 'A7XX_PERF_TSE_FE_VP_OUT_IS_NAN', - 'A7XX_PERF_TSE_FE_ZERO_AREA_PRIM', - 'A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', 'A7XX_PERF_TSE_NEVER_COUNT', - 'A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF', - 'A7XX_PERF_UCHE_BANK_REQ0', 'A7XX_PERF_UCHE_BANK_REQ1', - 'A7XX_PERF_UCHE_BANK_REQ2', 'A7XX_PERF_UCHE_BANK_REQ3', - 'A7XX_PERF_UCHE_BANK_REQ4', 'A7XX_PERF_UCHE_BANK_REQ5', - 'A7XX_PERF_UCHE_BANK_REQ6', 'A7XX_PERF_UCHE_BANK_REQ7', - 'A7XX_PERF_UCHE_BUSY_CYCLES', - 'A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL', - 'A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL', - 'A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL', - 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE', - 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS', - 'A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES', - 'A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', 'A7XX_PERF_UCHE_EVICTS', - 'A7XX_PERF_UCHE_EVICTS_LRZ', 'A7XX_PERF_UCHE_EVICTS_SP', - 'A7XX_PERF_UCHE_GMEM_READ_BEATS', - 'A7XX_PERF_UCHE_GMEM_WRITE_BEATS', - 'A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS', - 'A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS', - 'A7XX_PERF_UCHE_NEVER_COUNT', 'A7XX_PERF_UCHE_RAM_READ_REQ', - 'A7XX_PERF_UCHE_RAM_WRITE_REQ', - 'A7XX_PERF_UCHE_READ_REQUESTS_HLSQ', - 'A7XX_PERF_UCHE_READ_REQUESTS_LRZ', - 'A7XX_PERF_UCHE_READ_REQUESTS_PC', - 'A7XX_PERF_UCHE_READ_REQUESTS_SP', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM', - 'A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC', - 'A7XX_PERF_UCHE_READ_REQUESTS_VFD', - 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR', - 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV', - 'A7XX_PERF_UCHE_READ_REQUESTS_VPC', - 'A7XX_PERF_UCHE_READ_REQUESTS_VPCUS', - 'A7XX_PERF_UCHE_RESERVED_100', 'A7XX_PERF_UCHE_RESERVED_101', - 'A7XX_PERF_UCHE_RESERVED_102', 'A7XX_PERF_UCHE_RESERVED_103', - 'A7XX_PERF_UCHE_RESERVED_104', 'A7XX_PERF_UCHE_RESERVED_105', - 'A7XX_PERF_UCHE_RESERVED_106', 'A7XX_PERF_UCHE_RESERVED_107', - 'A7XX_PERF_UCHE_RESERVED_108', 'A7XX_PERF_UCHE_RESERVED_109', - 'A7XX_PERF_UCHE_RESERVED_110', 'A7XX_PERF_UCHE_RESERVED_111', - 'A7XX_PERF_UCHE_RESERVED_112', 'A7XX_PERF_UCHE_RESERVED_113', - 'A7XX_PERF_UCHE_RESERVED_114', 'A7XX_PERF_UCHE_RESERVED_115', - 'A7XX_PERF_UCHE_RESERVED_116', 'A7XX_PERF_UCHE_RESERVED_117', - 'A7XX_PERF_UCHE_RESERVED_118', 'A7XX_PERF_UCHE_RESERVED_119', - 'A7XX_PERF_UCHE_RESERVED_120', 'A7XX_PERF_UCHE_RESERVED_121', - 'A7XX_PERF_UCHE_RESERVED_122', 'A7XX_PERF_UCHE_RESERVED_123', - 'A7XX_PERF_UCHE_RESERVED_124', 'A7XX_PERF_UCHE_RESERVED_125', - 'A7XX_PERF_UCHE_RESERVED_126', 'A7XX_PERF_UCHE_RESERVED_127', - 'A7XX_PERF_UCHE_RESERVED_75', 'A7XX_PERF_UCHE_RESERVED_76', - 'A7XX_PERF_UCHE_RESERVED_77', 'A7XX_PERF_UCHE_RESERVED_78', - 'A7XX_PERF_UCHE_RESERVED_79', 'A7XX_PERF_UCHE_RESERVED_80', - 'A7XX_PERF_UCHE_RESERVED_81', 'A7XX_PERF_UCHE_RESERVED_82', - 'A7XX_PERF_UCHE_RESERVED_83', 'A7XX_PERF_UCHE_RESERVED_84', - 'A7XX_PERF_UCHE_RESERVED_85', 'A7XX_PERF_UCHE_RESERVED_86', - 'A7XX_PERF_UCHE_RESERVED_87', 'A7XX_PERF_UCHE_RESERVED_88', - 'A7XX_PERF_UCHE_RESERVED_89', 'A7XX_PERF_UCHE_RESERVED_90', - 'A7XX_PERF_UCHE_RESERVED_91', 'A7XX_PERF_UCHE_RESERVED_92', - 'A7XX_PERF_UCHE_RESERVED_93', 'A7XX_PERF_UCHE_RESERVED_94', - 'A7XX_PERF_UCHE_RESERVED_95', 'A7XX_PERF_UCHE_RESERVED_96', - 'A7XX_PERF_UCHE_RESERVED_97', 'A7XX_PERF_UCHE_RESERVED_98', - 'A7XX_PERF_UCHE_RESERVED_99', - 'A7XX_PERF_UCHE_STALL_CYCLES_ARBITER', - 'A7XX_PERF_UCHE_STALL_CYCLES_DECMP', - 'A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP', - 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE', - 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER', - 'A7XX_PERF_UCHE_TPH_EXT_FULL', 'A7XX_PERF_UCHE_TPH_REF_FULL', - 'A7XX_PERF_UCHE_TPH_VICTIM_FULL', - 'A7XX_PERF_UCHE_UBWC_READ_BEATS', - 'A7XX_PERF_UCHE_UBWC_WRITE_BEATS', - 'A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES', - 'A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_PC', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_SP', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_TP', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD', - 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC', - 'A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA', - 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0', - 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_SP', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_VPC', - 'A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', 'A7XX_PERF_UFC_BUSY_CYCLES', - 'A7XX_PERF_UFC_EVICTION_STALLED_CYCLES', - 'A7XX_PERF_UFC_L0_SP_FILTER_HIT', - 'A7XX_PERF_UFC_L0_SP_FILTER_MISS', 'A7XX_PERF_UFC_L0_SP_REQUESTS', - 'A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR', - 'A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP', - 'A7XX_PERF_UFC_L0_TP_HINT_REQUESTS', - 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY', - 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY', - 'A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS', - 'A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES', - 'A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES', - 'A7XX_PERF_UFC_L1_CRE_FILTER_HIT', - 'A7XX_PERF_UFC_L1_CRE_FILTER_MISS', - 'A7XX_PERF_UFC_L1_CRE_REQUESTS', - 'A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES', - 'A7XX_PERF_UFC_L1_SP_FILTER_HIT', - 'A7XX_PERF_UFC_L1_SP_FILTER_MISS', 'A7XX_PERF_UFC_L1_SP_REQUESTS', - 'A7XX_PERF_UFC_L1_SP_STALLED_CYCLES', - 'A7XX_PERF_UFC_L1_TP_HINT_REQUESTS', - 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY', - 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY', - 'A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS', - 'A7XX_PERF_UFC_L1_TP_STALLED_CYCLES', - 'A7XX_PERF_UFC_LOCK_STALLED_CYCLES', - 'A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH', - 'A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_HIT_UBWC_READ', - 'A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE', - 'A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH', - 'A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH', - 'A7XX_PERF_UFC_MAIN_MISS_UBWC_READ', - 'A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE', - 'A7XX_PERF_UFC_MAIN_TP_RD_NRDY', 'A7XX_PERF_UFC_MAIN_TP_RD_RDY', - 'A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY', - 'A7XX_PERF_UFC_MAIN_UBWC_RD_RDY', - 'A7XX_PERF_UFC_MISS_LATENCY_CYCLES', - 'A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', 'A7XX_PERF_UFC_NEVER_COUNT', - 'A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES', - 'A7XX_PERF_UFC_READ_DATA_VBIF', 'A7XX_PERF_UFC_READ_REQUEST_VBIF', - 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD', - 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA', - 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA', - 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT', - 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN', - 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG', - 'A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES', - 'A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES', - 'A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES', - 'A7XX_PERF_UFC_WRITE_DATA_VBIF', - 'A7XX_PERF_UFC_WRITE_REQUEST_VBIF', - 'A7XX_PERF_VFDP_STALL_CYCLES_VFD', - 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG', - 'A7XX_PERF_VFDP_STARVE_CYCLES_PC', - 'A7XX_PERF_VFDP_VS_STAGE_WAVES', - 'A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', 'A7XX_PERF_VFD_BUSY_CYCLES', - 'A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 'A7XX_PERF_VFD_LOWER_SHADER_FIBERS', - 'A7XX_PERF_VFD_MODE_0_FIBERS', 'A7XX_PERF_VFD_MODE_1_FIBERS', - 'A7XX_PERF_VFD_MODE_2_FIBERS', 'A7XX_PERF_VFD_MODE_3_FIBERS', - 'A7XX_PERF_VFD_MODE_4_FIBERS', 'A7XX_PERF_VFD_NEVER_COUNT', - 'A7XX_PERF_VFD_NUM_ATTRIBUTES', 'A7XX_PERF_VFD_RBUFFER_FULL', - 'A7XX_PERF_VFD_STALL_CYCLES_CBSYNC', - 'A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE', - 'A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR', - 'A7XX_PERF_VFD_STALL_CYCLES_SP_INFO', - 'A7XX_PERF_VFD_STALL_CYCLES_UCHE', - 'A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 'A7XX_PERF_VFD_STARVE_CYCLES_UCHE', - 'A7XX_PERF_VFD_TOTAL_VERTICES', - 'A7XX_PERF_VFD_UPPER_SHADER_FIBERS', 'A7XX_PERF_VHUB_PTABLE_FULL', - 'A7XX_PERF_VPC_BE_BOTTLENECK', 'A7XX_PERF_VPC_BE_BUSY_CYCLES', - 'A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ', - 'A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL', - 'A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END', - 'A7XX_PERF_VPC_BE_LM_TRANSACTION', - 'A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES', - 'A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM', - 'A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', 'A7XX_PERF_VPC_BE_NUM_PA_REQ', - 'A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR', - 'A7XX_PERF_VPC_BE_PS_BUSY_CYCLES', - 'A7XX_PERF_VPC_BE_PS_WORKING_CYCLES', - 'A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM', - 'A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE', - 'A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE', - 'A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ', - 'A7XX_PERF_VPC_BE_STARVE_CYCLES_RB', - 'A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES', - 'A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS', - 'A7XX_PERF_VPC_BE_WORKING_CYCLES', 'A7XX_PERF_VPC_FE_BOTTLENECK', - 'A7XX_PERF_VPC_FE_BUSY_CYCLES', - 'A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_GS_PRIMITIVES', - 'A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS', - 'A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE', - 'A7XX_PERF_VPC_FE_NUM_WM_HIT', 'A7XX_PERF_VPC_FE_PC_PRIMITIVES', - 'A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_SP_COMPONENTS', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_CCU', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS', - 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US', - 'A7XX_PERF_VPC_FE_STALL_DQ_WACK', - 'A7XX_PERF_VPC_FE_STARVE_CYCLES_SP', - 'A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES', - 'A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS', - 'A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_VS_BUSY_CYCLES', - 'A7XX_PERF_VPC_FE_VS_WORKING_CYCLES', - 'A7XX_PERF_VPC_FE_WIT_FULL_CYCLES', - 'A7XX_PERF_VPC_FE_WORKING_CYCLES', 'A7XX_PERF_VPC_NEVER_COUNT', - 'A7XX_PERF_VPC_RESERVED_42', 'A7XX_PERF_VPC_RESERVED_43', - 'A7XX_PERF_VPC_RESERVED_44', 'A7XX_PERF_VPC_US_BOTTLENECK', - 'A7XX_PERF_VPC_US_BUSY_CYCLES', - 'A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT', - 'A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', 'A7XX_PERF_VPC_US_PTUS_FULL', - 'A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS', - 'A7XX_PERF_VPC_US_STALL_CYCLES_UCHE', - 'A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE', - 'A7XX_PERF_VPC_US_STALL_CYCLES_VSC', - 'A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER', - 'A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE', - 'A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD', - 'A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION', - 'A7XX_PERF_VPC_US_WORKING_CYCLES', 'A7XX_PERF_VSC_BUSY_CYCLES', - 'A7XX_PERF_VSC_EOT_NUM', 'A7XX_PERF_VSC_INPUT_TILES', - 'A7XX_PERF_VSC_NEVER_COUNT', 'A7XX_PERF_VSC_STALL_CYCLES_UCHE', - 'A7XX_PERF_VSC_TILE_BYPASS_TRAN', 'A7XX_PERF_VSC_TILE_COMP_TRAN', - 'A7XX_PERF_VSC_WORKING_CYCLES', 'A7XX_PIPE_BR', 'A7XX_PIPE_BV', - 'A7XX_PIPE_LPAC', 'A7XX_PIPE_NONE', - 'A7XX_RBBM_CGC_P2S_STATUS_TXDONE', - 'A7XX_RB_BIN_CONTROL_BINH__MASK', - 'A7XX_RB_BIN_CONTROL_BINH__SHIFT', - 'A7XX_RB_BIN_CONTROL_BINW__MASK', - 'A7XX_RB_BIN_CONTROL_BINW__SHIFT', - 'A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS', - 'A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK', - 'A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT', - 'A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK', - 'A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT', - 'A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK', - 'A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK', - 'A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT', - 'A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK', - 'A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK', - 'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT', - 'A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE', - 'A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE', - 'A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK', - 'A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT', - 'A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN', - 'A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK', - 'A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT', - 'A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK', - 'A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK', - 'A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK', - 'A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK', - 'A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT', - 'A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN', - 'A7XX_RB_MRT_BUF_INFO_UNK10', 'A7XX_RB_RENDER_CNTL_BINNING', - 'A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN', - 'A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN', - 'A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN', - 'A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK', - 'A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT', - 'A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK', - 'A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT', - 'A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL', - 'A7XX_RB_STENCIL_INFO_TILEMODE__MASK', - 'A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT', - 'A7XX_RB_STENCIL_INFO_UNK1', 'A7XX_RB_UNKNOWN_88E4_UNK0', - 'A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK', - 'A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT', - 'A7XX_SP_2D_DST_FORMAT_MASK__MASK', - 'A7XX_SP_2D_DST_FORMAT_MASK__SHIFT', 'A7XX_SP_2D_DST_FORMAT_NORM', - 'A7XX_SP_2D_DST_FORMAT_SINT', 'A7XX_SP_2D_DST_FORMAT_SRGB', - 'A7XX_SP_2D_DST_FORMAT_UINT', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A7XX_SP_CB_RAM', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK', - 'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT', - 'A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK', - 'A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT', - 'A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR', - 'A7XX_SP_CS_CNTL_1_THREADSIZE__MASK', - 'A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT', 'A7XX_SP_CS_CNTL_1_UNK15', - 'A7XX_SP_CTX0_3D_CPS_REG', 'A7XX_SP_CTX0_3D_CVS_REG', - 'A7XX_SP_CTX1_3D_CPS_REG', 'A7XX_SP_CTX1_3D_CVS_REG', - 'A7XX_SP_CTX2_3D_CPS_REG', 'A7XX_SP_CTX3_3D_CPS_REG', - 'A7XX_SP_FS_PREFETCH_CMD_BINDLESS', - 'A7XX_SP_FS_PREFETCH_CMD_CMD__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_DST__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_HALF', - 'A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_SRC__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT', - 'A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK', - 'A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT', 'A7XX_SP_HWAVE_RAM', - 'A7XX_SP_INST_DATA', 'A7XX_SP_INST_DATA_1', 'A7XX_SP_INST_DATA_2', - 'A7XX_SP_INST_TAG', 'A7XX_SP_L0_INST_BUF', 'A7XX_SP_LB_0_DATA', - 'A7XX_SP_LB_10_DATA', 'A7XX_SP_LB_11_DATA', 'A7XX_SP_LB_12_DATA', - 'A7XX_SP_LB_13_DATA', 'A7XX_SP_LB_14_DATA', 'A7XX_SP_LB_1_DATA', - 'A7XX_SP_LB_2_DATA', 'A7XX_SP_LB_3_DATA', 'A7XX_SP_LB_4_DATA', - 'A7XX_SP_LB_5_DATA', 'A7XX_SP_LB_6_DATA', 'A7XX_SP_LB_7_DATA', - 'A7XX_SP_LB_8_DATA', 'A7XX_SP_LB_9_DATA', 'A7XX_SP_NCTX_REG', - 'A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK', - 'A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_FILTER', 'A7XX_SP_PS_2D_SRC_INFO_FLAGS', - 'A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE', - 'A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_SRGB', - 'A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_UNK17', 'A7XX_SP_PS_2D_SRC_INFO_UNK19', - 'A7XX_SP_PS_2D_SRC_INFO_UNK20', 'A7XX_SP_PS_2D_SRC_INFO_UNK21', - 'A7XX_SP_PS_2D_SRC_INFO_UNK22', - 'A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK', - 'A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT', - 'A7XX_SP_PS_2D_SRC_INFO_UNK28', - 'A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK', - 'A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT', - 'A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK', - 'A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT', - 'A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK', - 'A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT', - 'A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK', - 'A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT', - 'A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK', - 'A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK', - 'A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK', - 'A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT', - 'A7XX_SP_READ_SEL_LOCATION__MASK', - 'A7XX_SP_READ_SEL_LOCATION__SHIFT', 'A7XX_SP_READ_SEL_PIPE__MASK', - 'A7XX_SP_READ_SEL_PIPE__SHIFT', 'A7XX_SP_READ_SEL_SPTP__MASK', - 'A7XX_SP_READ_SEL_SPTP__SHIFT', - 'A7XX_SP_READ_SEL_STATETYPE__MASK', - 'A7XX_SP_READ_SEL_STATETYPE__SHIFT', - 'A7XX_SP_READ_SEL_USPTP__MASK', 'A7XX_SP_READ_SEL_USPTP__SHIFT', - 'A7XX_SP_SMO_TAG', 'A7XX_SP_STATE_DATA', 'A7XX_SP_TMO_TAG', - 'A7XX_SP_TOP', 'A7XX_SP_WINDOW_OFFSET_X__MASK', - 'A7XX_SP_WINDOW_OFFSET_X__SHIFT', 'A7XX_SP_WINDOW_OFFSET_Y__MASK', - 'A7XX_SP_WINDOW_OFFSET_Y__SHIFT', 'A7XX_TP0_CTX0_3D_CPS_REG', - 'A7XX_TP0_CTX0_3D_CVS_REG', 'A7XX_TP0_CTX1_3D_CPS_REG', - 'A7XX_TP0_CTX1_3D_CVS_REG', 'A7XX_TP0_CTX2_3D_CPS_REG', - 'A7XX_TP0_CTX3_3D_CPS_REG', 'A7XX_TP0_MIPMAP_BASE_DATA', - 'A7XX_TP0_NCTX_REG', 'A7XX_TP0_SMO_DATA', 'A7XX_TP0_TMO_DATA', - 'A7XX_USPTP', 'A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK', - 'A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT', - 'A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK', - 'A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT', - 'A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS', - 'A7XX_VPC_MULTIVIEW_CNTL_ENABLE', - 'A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK', - 'A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT', - 'A7XX_VPC_POLYGON_MODE2_MODE__MASK', - 'A7XX_VPC_POLYGON_MODE2_MODE__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING', - 'A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART', - 'A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST', - 'A7XX_VPC_PRIMITIVE_CNTL_0_UNK3', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK', - 'A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT', - 'A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN', - 'A7XX_VPC_PRIMITIVE_CNTL_5_UNK18', - 'A7XX_VSC_UNKNOWN_0CD8_BINNING', 'ADDR_32B', 'ADDR_64B', - 'AXXX_CP_CSQ_AVAIL_IB1__MASK', 'AXXX_CP_CSQ_AVAIL_IB1__SHIFT', - 'AXXX_CP_CSQ_AVAIL_IB2__MASK', 'AXXX_CP_CSQ_AVAIL_IB2__SHIFT', - 'AXXX_CP_CSQ_AVAIL_RING__MASK', 'AXXX_CP_CSQ_AVAIL_RING__SHIFT', - 'AXXX_CP_CSQ_IB1_STAT_RPTR__MASK', - 'AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT', - 'AXXX_CP_CSQ_IB1_STAT_WPTR__MASK', - 'AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT', - 'AXXX_CP_CSQ_IB2_STAT_RPTR__MASK', - 'AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT', - 'AXXX_CP_CSQ_IB2_STAT_WPTR__MASK', - 'AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT', - 'AXXX_CP_CSQ_RB_STAT_RPTR__MASK', - 'AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT', - 'AXXX_CP_CSQ_RB_STAT_WPTR__MASK', - 'AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT', - 'AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE', - 'AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE', - 'AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE', - 'AXXX_CP_DEBUG_PREDICATE_DISABLE', - 'AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE', - 'AXXX_CP_DEBUG_PREFETCH_PASS_NOPS', - 'AXXX_CP_DEBUG_PROG_END_PTR_ENABLE', - 'AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL', - 'AXXX_CP_INT_CNTL_IB1_INT_MASK', 'AXXX_CP_INT_CNTL_IB2_INT_MASK', - 'AXXX_CP_INT_CNTL_IB_ERROR_MASK', - 'AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK', - 'AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK', - 'AXXX_CP_INT_CNTL_RB_INT_MASK', - 'AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK', - 'AXXX_CP_INT_CNTL_SW_INT_MASK', - 'AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK', - 'AXXX_CP_MEQ_AVAIL_MEQ__MASK', 'AXXX_CP_MEQ_AVAIL_MEQ__SHIFT', - 'AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK', - 'AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT', - 'AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK', - 'AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT', 'AXXX_CP_ME_CNTL_BUSY', - 'AXXX_CP_ME_CNTL_HALT', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK', - 'AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT', - 'AXXX_CP_RB_CNTL_BLKSZ__MASK', 'AXXX_CP_RB_CNTL_BLKSZ__SHIFT', - 'AXXX_CP_RB_CNTL_BUFSZ__MASK', 'AXXX_CP_RB_CNTL_BUFSZ__SHIFT', - 'AXXX_CP_RB_CNTL_BUF_SWAP__MASK', - 'AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT', 'AXXX_CP_RB_CNTL_NO_UPDATE', - 'AXXX_CP_RB_CNTL_POLL_EN', 'AXXX_CP_RB_CNTL_RPTR_WR_EN', - 'AXXX_CP_RB_RPTR_ADDR_ADDR__MASK', - 'AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT', - 'AXXX_CP_RB_RPTR_ADDR_SWAP__MASK', - 'AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT', - 'AXXX_CP_STAT_CF_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_CP_3D_BUSY', - 'AXXX_CP_STAT_CP_BUSY', 'AXXX_CP_STAT_CP_NRT_BUSY', - 'AXXX_CP_STAT_CSF_BUSY', 'AXXX_CP_STAT_CSF_INDIRECT2_BUSY', - 'AXXX_CP_STAT_CSF_INDIRECTS_BUSY', 'AXXX_CP_STAT_CSF_RING_BUSY', - 'AXXX_CP_STAT_CSF_ST_BUSY', 'AXXX_CP_STAT_EVENT_BUSY', - 'AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY', - 'AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY', 'AXXX_CP_STAT_MEQ_RING_BUSY', - 'AXXX_CP_STAT_ME_BUSY', 'AXXX_CP_STAT_MIU_RD_REQ_BUSY', - 'AXXX_CP_STAT_MIU_RD_RETURN_BUSY', 'AXXX_CP_STAT_MIU_WR_BUSY', - 'AXXX_CP_STAT_MIU_WR_C_BUSY', 'AXXX_CP_STAT_PFP_BUSY', - 'AXXX_CP_STAT_PS_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_RBIU_BUSY', - 'AXXX_CP_STAT_RBIU_SCRATCH_BUSY', - 'AXXX_CP_STAT_RB_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_RCIU_BUSY', - 'AXXX_CP_STAT_RCIU_ME_BUSY', 'AXXX_CP_STAT_RCIU_PFP_BUSY', - 'AXXX_CP_STAT_RING_QUEUE_BUSY', 'AXXX_CP_STAT_ST_QUEUE_BUSY', - 'AXXX_CP_STAT_VS_EVENT_FIFO_BUSY', 'AXXX_CP_STQ_AVAIL_ST__MASK', - 'AXXX_CP_STQ_AVAIL_ST__SHIFT', 'AXXX_SCRATCH_UMSK_SWAP__MASK', - 'AXXX_SCRATCH_UMSK_SWAP__SHIFT', 'AXXX_SCRATCH_UMSK_UMSK__MASK', - 'AXXX_SCRATCH_UMSK_UMSK__SHIFT', 'BINDLESS_BASE_0_ADDR', - 'BINDLESS_BASE_1_ADDR', 'BINDLESS_BASE_2_ADDR', - 'BINDLESS_BASE_3_ADDR', 'BINDLESS_BASE_4_ADDR', - 'BINDLESS_BASE_5_ADDR', 'BINDLESS_BASE_6_ADDR', - 'BINDLESS_DESCRIPTOR_16B', 'BINDLESS_DESCRIPTOR_64B', 'BINNING', - 'BINNING_PASS', 'BLEND_DST_MINUS_SRC', 'BLEND_DST_PLUS_SRC', - 'BLEND_MAX_DST_SRC', 'BLEND_MIN_DST_SRC', 'BLEND_SRC_MINUS_DST', - 'BLIT', 'BLIT2D', 'BLIT2DSCALE', 'BLIT_OP_COPY', - 'BLIT_OP_COPY_2D', 'BLIT_OP_FILL', 'BLIT_OP_FILL_2D', - 'BLIT_OP_SCALE', 'BLIT_OP_SCALE_2D', 'BRESENHAM', 'BUFFER', - 'BUFFERS_IN_GMEM', 'BUFFERS_IN_SYSMEM', 'BYPASS', 'CACHE', - 'CACHE_CLEAN', 'CACHE_FLUSH', 'CACHE_FLUSH7', - 'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', - 'CACHE_FLUSH_TS', 'CACHE_INVALIDATE', 'CACHE_INVALIDATE7', - 'CACHE_RESET', 'CCU_CACHE_SIZE_EIGHTH', 'CCU_CACHE_SIZE_FULL', - 'CCU_CACHE_SIZE_HALF', 'CCU_CACHE_SIZE_QUARTER', - 'CCU_CLEAN_COLOR', 'CCU_CLEAN_DEPTH', 'CCU_END_RESOLVE_GROUP', - 'CCU_FLUSH_COLOR', 'CCU_FLUSH_DEPTH', 'CCU_INVALIDATE_COLOR', - 'CCU_INVALIDATE_DEPTH', 'CCU_RESOLVE', 'CCU_RESOLVE_CLEAN', - 'CONTEXT_DONE', 'CONTEXT_DONE_2D', 'COUNTER', 'CP_BLIT', - 'CP_BLIT_0_OP__MASK', 'CP_BLIT_0_OP__SHIFT', - 'CP_BLIT_1_SRC_X1__MASK', 'CP_BLIT_1_SRC_X1__SHIFT', - 'CP_BLIT_1_SRC_Y1__MASK', 'CP_BLIT_1_SRC_Y1__SHIFT', - 'CP_BLIT_2_SRC_X2__MASK', 'CP_BLIT_2_SRC_X2__SHIFT', - 'CP_BLIT_2_SRC_Y2__MASK', 'CP_BLIT_2_SRC_Y2__SHIFT', - 'CP_BLIT_3_DST_X1__MASK', 'CP_BLIT_3_DST_X1__SHIFT', - 'CP_BLIT_3_DST_Y1__MASK', 'CP_BLIT_3_DST_Y1__SHIFT', - 'CP_BLIT_4_DST_X2__MASK', 'CP_BLIT_4_DST_X2__SHIFT', - 'CP_BLIT_4_DST_Y2__MASK', 'CP_BLIT_4_DST_Y2__SHIFT', - 'CP_BOOTSTRAP_UCODE', 'CP_BV_BR_COUNT_OPS', - 'CP_BV_BR_COUNT_OPS_0_OP__MASK', 'CP_BV_BR_COUNT_OPS_0_OP__SHIFT', - 'CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK', - 'CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT', 'CP_CCHE_INVALIDATE', - 'CP_COMPUTE_CHECKPOINT', - 'CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK', - 'CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT', - 'CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK', - 'CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT', - 'CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK', - 'CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT', - 'CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK', - 'CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT', - 'CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK', - 'CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT', 'CP_COND_EXEC', - 'CP_COND_EXEC_0_ADDR0_LO__MASK', 'CP_COND_EXEC_0_ADDR0_LO__SHIFT', - 'CP_COND_EXEC_1_ADDR0_HI__MASK', 'CP_COND_EXEC_1_ADDR0_HI__SHIFT', - 'CP_COND_EXEC_2_ADDR1_LO__MASK', 'CP_COND_EXEC_2_ADDR1_LO__SHIFT', - 'CP_COND_EXEC_3_ADDR1_HI__MASK', 'CP_COND_EXEC_3_ADDR1_HI__SHIFT', - 'CP_COND_EXEC_4_REF__MASK', 'CP_COND_EXEC_4_REF__SHIFT', - 'CP_COND_EXEC_5_DWORDS__MASK', 'CP_COND_EXEC_5_DWORDS__SHIFT', - 'CP_COND_INDIRECT_BUFFER_PFD', 'CP_COND_INDIRECT_BUFFER_PFE', - 'CP_COND_REG_EXEC', 'CP_COND_REG_EXEC_0_BINNING', - 'CP_COND_REG_EXEC_0_BR', 'CP_COND_REG_EXEC_0_BV', - 'CP_COND_REG_EXEC_0_GMEM', 'CP_COND_REG_EXEC_0_LPAC', - 'CP_COND_REG_EXEC_0_MODE__MASK', 'CP_COND_REG_EXEC_0_MODE__SHIFT', - 'CP_COND_REG_EXEC_0_ONCHIP_MEM', - 'CP_COND_REG_EXEC_0_PRED_BIT__MASK', - 'CP_COND_REG_EXEC_0_PRED_BIT__SHIFT', - 'CP_COND_REG_EXEC_0_REG0__MASK', 'CP_COND_REG_EXEC_0_REG0__SHIFT', - 'CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME', - 'CP_COND_REG_EXEC_0_SYSMEM', 'CP_COND_REG_EXEC_2_DWORDS__MASK', - 'CP_COND_REG_EXEC_2_DWORDS__SHIFT', 'CP_COND_WRITE', - 'CP_COND_WRITE5', 'CP_COND_WRITE5_0_FUNCTION__MASK', - 'CP_COND_WRITE5_0_FUNCTION__SHIFT', 'CP_COND_WRITE5_0_POLL__MASK', - 'CP_COND_WRITE5_0_POLL__SHIFT', 'CP_COND_WRITE5_0_SIGNED_COMPARE', - 'CP_COND_WRITE5_0_WRITE_MEMORY', - 'CP_COND_WRITE5_1_POLL_ADDR_LO__MASK', - 'CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT', - 'CP_COND_WRITE5_2_POLL_ADDR_HI__MASK', - 'CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT', - 'CP_COND_WRITE5_3_REF__MASK', 'CP_COND_WRITE5_3_REF__SHIFT', - 'CP_COND_WRITE5_4_MASK__MASK', 'CP_COND_WRITE5_4_MASK__SHIFT', - 'CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK', - 'CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT', - 'CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK', - 'CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT', - 'CP_COND_WRITE5_7_WRITE_DATA__MASK', - 'CP_COND_WRITE5_7_WRITE_DATA__SHIFT', - 'CP_COND_WRITE_0_FUNCTION__MASK', - 'CP_COND_WRITE_0_FUNCTION__SHIFT', 'CP_COND_WRITE_0_POLL_MEMORY', - 'CP_COND_WRITE_0_WRITE_MEMORY', 'CP_COND_WRITE_1_POLL_ADDR__MASK', - 'CP_COND_WRITE_1_POLL_ADDR__SHIFT', 'CP_COND_WRITE_2_REF__MASK', - 'CP_COND_WRITE_2_REF__SHIFT', 'CP_COND_WRITE_3_MASK__MASK', - 'CP_COND_WRITE_3_MASK__SHIFT', 'CP_COND_WRITE_4_WRITE_ADDR__MASK', - 'CP_COND_WRITE_4_WRITE_ADDR__SHIFT', - 'CP_COND_WRITE_5_WRITE_DATA__MASK', - 'CP_COND_WRITE_5_WRITE_DATA__SHIFT', 'CP_CONTEXT_REG_BUNCH', - 'CP_CONTEXT_REG_BUNCH2', 'CP_CONTEXT_SWITCH', - 'CP_CONTEXT_SWITCH_YIELD', 'CP_CONTEXT_UPDATE', - 'CP_DISPATCH_COMPUTE_1_X__MASK', 'CP_DISPATCH_COMPUTE_1_X__SHIFT', - 'CP_DISPATCH_COMPUTE_2_Y__MASK', 'CP_DISPATCH_COMPUTE_2_Y__SHIFT', - 'CP_DISPATCH_COMPUTE_3_Z__MASK', 'CP_DISPATCH_COMPUTE_3_Z__SHIFT', - 'CP_DRAW_AUTO', 'CP_DRAW_AUTO_0_GS_ENABLE', - 'CP_DRAW_AUTO_0_INDEX_SIZE__MASK', - 'CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT', - 'CP_DRAW_AUTO_0_PATCH_TYPE__MASK', - 'CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT', - 'CP_DRAW_AUTO_0_PRIM_TYPE__MASK', - 'CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT', - 'CP_DRAW_AUTO_0_SOURCE_SELECT__MASK', - 'CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT', - 'CP_DRAW_AUTO_0_TESS_ENABLE', 'CP_DRAW_AUTO_0_VIS_CULL__MASK', - 'CP_DRAW_AUTO_0_VIS_CULL__SHIFT', - 'CP_DRAW_AUTO_1_NUM_INSTANCES__MASK', - 'CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK', - 'CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT', - 'CP_DRAW_AUTO_5_STRIDE__MASK', 'CP_DRAW_AUTO_5_STRIDE__SHIFT', - 'CP_DRAW_INDIRECT', 'CP_DRAW_INDIRECT_MULTI', 'CP_DRAW_INDX', - 'CP_DRAW_INDX_0_VIZ_QUERY__MASK', - 'CP_DRAW_INDX_0_VIZ_QUERY__SHIFT', - 'CP_DRAW_INDX_1_INDEX_SIZE__MASK', - 'CP_DRAW_INDX_1_INDEX_SIZE__SHIFT', 'CP_DRAW_INDX_1_NOT_EOP', - 'CP_DRAW_INDX_1_NUM_INSTANCES__MASK', - 'CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE', - 'CP_DRAW_INDX_1_PRIM_TYPE__MASK', - 'CP_DRAW_INDX_1_PRIM_TYPE__SHIFT', 'CP_DRAW_INDX_1_SMALL_INDEX', - 'CP_DRAW_INDX_1_SOURCE_SELECT__MASK', - 'CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT', - 'CP_DRAW_INDX_1_VIS_CULL__MASK', 'CP_DRAW_INDX_1_VIS_CULL__SHIFT', - 'CP_DRAW_INDX_2', 'CP_DRAW_INDX_2_0_VIZ_QUERY__MASK', - 'CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT', - 'CP_DRAW_INDX_2_1_INDEX_SIZE__MASK', - 'CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT', 'CP_DRAW_INDX_2_1_NOT_EOP', - 'CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK', - 'CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE', - 'CP_DRAW_INDX_2_1_PRIM_TYPE__MASK', - 'CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT', - 'CP_DRAW_INDX_2_1_SMALL_INDEX', - 'CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK', - 'CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT', - 'CP_DRAW_INDX_2_1_VIS_CULL__MASK', - 'CP_DRAW_INDX_2_1_VIS_CULL__SHIFT', - 'CP_DRAW_INDX_2_2_NUM_INDICES__MASK', - 'CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT', 'CP_DRAW_INDX_2_BIN', - 'CP_DRAW_INDX_2_NUM_INDICES__MASK', - 'CP_DRAW_INDX_2_NUM_INDICES__SHIFT', - 'CP_DRAW_INDX_3_INDX_BASE__MASK', - 'CP_DRAW_INDX_3_INDX_BASE__SHIFT', - 'CP_DRAW_INDX_4_INDX_SIZE__MASK', - 'CP_DRAW_INDX_4_INDX_SIZE__SHIFT', 'CP_DRAW_INDX_BIN', - 'CP_DRAW_INDX_INDIRECT', 'CP_DRAW_INDX_OFFSET', - 'CP_DRAW_INDX_OFFSET_0_GS_ENABLE', - 'CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK', - 'CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK', - 'CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK', - 'CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK', - 'CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT', - 'CP_DRAW_INDX_OFFSET_0_TESS_ENABLE', - 'CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK', - 'CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT', - 'CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK', - 'CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT', - 'CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK', - 'CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT', - 'CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK', - 'CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT', - 'CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK', - 'CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT', - 'CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK', - 'CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT', - 'CP_DRAW_PRED_ENABLE_GLOBAL', - 'CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE', - 'CP_DRAW_PRED_ENABLE_LOCAL', 'CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE', - 'CP_DRAW_PRED_SET', 'CP_DRAW_PRED_SET_0_SRC__MASK', - 'CP_DRAW_PRED_SET_0_SRC__SHIFT', 'CP_DRAW_PRED_SET_0_TEST__MASK', - 'CP_DRAW_PRED_SET_0_TEST__SHIFT', 'CP_END_BIN', 'CP_EVENT_WRITE', - 'CP_EVENT_WRITE7', 'CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE', - 'CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE', - 'CP_EVENT_WRITE7_0_EVENT__MASK', 'CP_EVENT_WRITE7_0_EVENT__SHIFT', - 'CP_EVENT_WRITE7_0_INC_BR_COUNT', - 'CP_EVENT_WRITE7_0_INC_BV_COUNT', - 'CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET', - 'CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF', - 'CP_EVENT_WRITE7_0_WRITE_DST__MASK', - 'CP_EVENT_WRITE7_0_WRITE_DST__SHIFT', - 'CP_EVENT_WRITE7_0_WRITE_ENABLED', - 'CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT', - 'CP_EVENT_WRITE7_0_WRITE_SRC__MASK', - 'CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT', - 'CP_EVENT_WRITE_0_EVENT__MASK', 'CP_EVENT_WRITE_0_EVENT__SHIFT', - 'CP_EVENT_WRITE_0_IRQ', 'CP_EVENT_WRITE_0_TIMESTAMP', - 'CP_EVENT_WRITE_1_ADDR_0_LO__MASK', - 'CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT', - 'CP_EVENT_WRITE_2_ADDR_0_HI__MASK', - 'CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT', 'CP_EVENT_WRITE_CFL', - 'CP_EVENT_WRITE_SHD', 'CP_EVENT_WRITE_ZPD', 'CP_EXEC_CS', - 'CP_EXEC_CS_1_NGROUPS_X__MASK', 'CP_EXEC_CS_1_NGROUPS_X__SHIFT', - 'CP_EXEC_CS_2_NGROUPS_Y__MASK', 'CP_EXEC_CS_2_NGROUPS_Y__SHIFT', - 'CP_EXEC_CS_3_NGROUPS_Z__MASK', 'CP_EXEC_CS_3_NGROUPS_Z__SHIFT', - 'CP_EXEC_CS_INDIRECT', 'CP_FIXED_STRIDE_DRAW_TABLE', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK', - 'CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT', - 'CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK', - 'CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT', - 'CP_GLOBAL_TIMESTAMP', 'CP_IM_LOAD', 'CP_IM_LOAD_IMMEDIATE', - 'CP_IM_STORE', 'CP_INDIRECT_BUFFER', 'CP_INDIRECT_BUFFER_CHAIN', - 'CP_INDIRECT_BUFFER_PFD', 'CP_INDIRECT_BUFFER_PFE', - 'CP_INTERRUPT', 'CP_INVALIDATE_STATE', 'CP_LOAD_CONSTANT_CONTEXT', - 'CP_LOAD_STATE', 'CP_LOAD_STATE4', - 'CP_LOAD_STATE4_0_DST_OFF__MASK', - 'CP_LOAD_STATE4_0_DST_OFF__SHIFT', - 'CP_LOAD_STATE4_0_NUM_UNIT__MASK', - 'CP_LOAD_STATE4_0_NUM_UNIT__SHIFT', - 'CP_LOAD_STATE4_0_STATE_BLOCK__MASK', - 'CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT', - 'CP_LOAD_STATE4_0_STATE_SRC__MASK', - 'CP_LOAD_STATE4_0_STATE_SRC__SHIFT', - 'CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK', - 'CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT', - 'CP_LOAD_STATE4_1_STATE_TYPE__MASK', - 'CP_LOAD_STATE4_1_STATE_TYPE__SHIFT', - 'CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK', - 'CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT', 'CP_LOAD_STATE6', - 'CP_LOAD_STATE6_0_DST_OFF__MASK', - 'CP_LOAD_STATE6_0_DST_OFF__SHIFT', - 'CP_LOAD_STATE6_0_NUM_UNIT__MASK', - 'CP_LOAD_STATE6_0_NUM_UNIT__SHIFT', - 'CP_LOAD_STATE6_0_STATE_BLOCK__MASK', - 'CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT', - 'CP_LOAD_STATE6_0_STATE_SRC__MASK', - 'CP_LOAD_STATE6_0_STATE_SRC__SHIFT', - 'CP_LOAD_STATE6_0_STATE_TYPE__MASK', - 'CP_LOAD_STATE6_0_STATE_TYPE__SHIFT', - 'CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK', - 'CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT', - 'CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK', - 'CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT', 'CP_LOAD_STATE6_FRAG', - 'CP_LOAD_STATE6_GEOM', 'CP_LOAD_STATE_0_DST_OFF__MASK', - 'CP_LOAD_STATE_0_DST_OFF__SHIFT', - 'CP_LOAD_STATE_0_NUM_UNIT__MASK', - 'CP_LOAD_STATE_0_NUM_UNIT__SHIFT', - 'CP_LOAD_STATE_0_STATE_BLOCK__MASK', - 'CP_LOAD_STATE_0_STATE_BLOCK__SHIFT', - 'CP_LOAD_STATE_0_STATE_SRC__MASK', - 'CP_LOAD_STATE_0_STATE_SRC__SHIFT', - 'CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK', - 'CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT', - 'CP_LOAD_STATE_1_STATE_TYPE__MASK', - 'CP_LOAD_STATE_1_STATE_TYPE__SHIFT', 'CP_LOCAL_TIMESTAMP', - 'CP_MEMCPY', 'CP_MEMCPY_0_DWORDS__MASK', - 'CP_MEMCPY_0_DWORDS__SHIFT', 'CP_MEMCPY_1_SRC_LO__MASK', - 'CP_MEMCPY_1_SRC_LO__SHIFT', 'CP_MEMCPY_2_SRC_HI__MASK', - 'CP_MEMCPY_2_SRC_HI__SHIFT', 'CP_MEMCPY_3_DST_LO__MASK', - 'CP_MEMCPY_3_DST_LO__SHIFT', 'CP_MEMCPY_4_DST_HI__MASK', - 'CP_MEMCPY_4_DST_HI__SHIFT', 'CP_MEM_TO_MEM', - 'CP_MEM_TO_MEM_0_DOUBLE', 'CP_MEM_TO_MEM_0_NEG_A', - 'CP_MEM_TO_MEM_0_NEG_B', 'CP_MEM_TO_MEM_0_NEG_C', - 'CP_MEM_TO_MEM_0_UNK31', 'CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES', - 'CP_MEM_TO_REG', 'CP_MEM_TO_REG_0_CNT__MASK', - 'CP_MEM_TO_REG_0_CNT__SHIFT', 'CP_MEM_TO_REG_0_REG__MASK', - 'CP_MEM_TO_REG_0_REG__SHIFT', 'CP_MEM_TO_REG_0_SHIFT_BY_2', - 'CP_MEM_TO_REG_0_UNK31', 'CP_MEM_TO_REG_1_SRC__MASK', - 'CP_MEM_TO_REG_1_SRC__SHIFT', 'CP_MEM_TO_REG_2_SRC_HI__MASK', - 'CP_MEM_TO_REG_2_SRC_HI__SHIFT', 'CP_MEM_TO_SCRATCH_MEM', - 'CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK', - 'CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT', - 'CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK', - 'CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT', - 'CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK', - 'CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT', - 'CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK', - 'CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT', 'CP_MEM_WRITE', - 'CP_MEM_WRITE_0_ADDR_LO__MASK', 'CP_MEM_WRITE_0_ADDR_LO__SHIFT', - 'CP_MEM_WRITE_1_ADDR_HI__MASK', 'CP_MEM_WRITE_1_ADDR_HI__SHIFT', - 'CP_MEM_WRITE_CNTR', 'CP_ME_INIT', 'CP_MODIFY_TIMESTAMP', - 'CP_MODIFY_TIMESTAMP_0_ADD__MASK', - 'CP_MODIFY_TIMESTAMP_0_ADD__SHIFT', - 'CP_MODIFY_TIMESTAMP_0_OP__MASK', - 'CP_MODIFY_TIMESTAMP_0_OP__SHIFT', 'CP_NOP', - 'CP_PERFCOUNTER_ACTION', - 'CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK', - 'CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT', - 'CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK', - 'CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT', 'CP_PREEMPT_DISABLE', - 'CP_PREEMPT_ENABLE', 'CP_PREEMPT_ENABLE_GLOBAL', - 'CP_PREEMPT_ENABLE_LOCAL', 'CP_PREEMPT_TOKEN', - 'CP_RECORD_PFP_TIMESTAMP', 'CP_REG_RMW', - 'CP_REG_RMW_0_DST_REG__MASK', 'CP_REG_RMW_0_DST_REG__SHIFT', - 'CP_REG_RMW_0_ROTATE__MASK', 'CP_REG_RMW_0_ROTATE__SHIFT', - 'CP_REG_RMW_0_SRC0_IS_REG', 'CP_REG_RMW_0_SRC1_ADD', - 'CP_REG_RMW_0_SRC1_IS_REG', 'CP_REG_RMW_1_SRC0__MASK', - 'CP_REG_RMW_1_SRC0__SHIFT', 'CP_REG_RMW_2_SRC1__MASK', - 'CP_REG_RMW_2_SRC1__SHIFT', 'CP_REG_TEST', 'CP_REG_TO_MEM', - 'CP_REG_TO_MEM_0_64B', 'CP_REG_TO_MEM_0_ACCUMULATE', - 'CP_REG_TO_MEM_0_CNT__MASK', 'CP_REG_TO_MEM_0_CNT__SHIFT', - 'CP_REG_TO_MEM_0_REG__MASK', 'CP_REG_TO_MEM_0_REG__SHIFT', - 'CP_REG_TO_MEM_1_DEST__MASK', 'CP_REG_TO_MEM_1_DEST__SHIFT', - 'CP_REG_TO_MEM_2_DEST_HI__MASK', 'CP_REG_TO_MEM_2_DEST_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM', 'CP_REG_TO_MEM_OFFSET_MEM_0_64B', - 'CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE', - 'CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT', - 'CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK', - 'CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG', 'CP_REG_TO_MEM_OFFSET_REG_0_64B', - 'CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE', - 'CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT', - 'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH', - 'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK', - 'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT', 'CP_REG_TO_SCRATCH', - 'CP_REG_TO_SCRATCH_0_CNT__MASK', 'CP_REG_TO_SCRATCH_0_CNT__SHIFT', - 'CP_REG_TO_SCRATCH_0_REG__MASK', 'CP_REG_TO_SCRATCH_0_REG__SHIFT', - 'CP_REG_TO_SCRATCH_0_SCRATCH__MASK', - 'CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT', 'CP_REG_WRITE', - 'CP_REG_WRITE_0_TRACKER__MASK', 'CP_REG_WRITE_0_TRACKER__SHIFT', - 'CP_REG_WR_NO_CTXT', 'CP_RESET_CONTEXT_STATE', - 'CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS', - 'CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS', - 'CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE', - 'CP_RESOURCE_LIST', 'CP_RUN_OPENCL', 'CP_SCRATCH_TO_REG', - 'CP_SCRATCH_TO_REG_0_CNT__MASK', 'CP_SCRATCH_TO_REG_0_CNT__SHIFT', - 'CP_SCRATCH_TO_REG_0_REG__MASK', 'CP_SCRATCH_TO_REG_0_REG__SHIFT', - 'CP_SCRATCH_TO_REG_0_SCRATCH__MASK', - 'CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT', 'CP_SCRATCH_TO_REG_0_UNK18', - 'CP_SCRATCH_WRITE', 'CP_SCRATCH_WRITE_0_SCRATCH__MASK', - 'CP_SCRATCH_WRITE_0_SCRATCH__SHIFT', 'CP_SET_BIN', - 'CP_SET_BIN_1_X1__MASK', 'CP_SET_BIN_1_X1__SHIFT', - 'CP_SET_BIN_1_Y1__MASK', 'CP_SET_BIN_1_Y1__SHIFT', - 'CP_SET_BIN_2_X2__MASK', 'CP_SET_BIN_2_X2__SHIFT', - 'CP_SET_BIN_2_Y2__MASK', 'CP_SET_BIN_2_Y2__SHIFT', - 'CP_SET_BIN_DATA', 'CP_SET_BIN_DATA5', - 'CP_SET_BIN_DATA5_0_VSC_N__MASK', - 'CP_SET_BIN_DATA5_0_VSC_N__SHIFT', - 'CP_SET_BIN_DATA5_0_VSC_SIZE__MASK', - 'CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT', - 'CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK', - 'CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT', - 'CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK', - 'CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT', - 'CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK', - 'CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT', - 'CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK', - 'CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT', - 'CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK', - 'CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT', - 'CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK', - 'CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK', - 'CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK', - 'CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK', - 'CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT', - 'CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK', - 'CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT', - 'CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK', - 'CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT', - 'CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK', - 'CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT', 'CP_SET_BIN_MASK', - 'CP_SET_BIN_SELECT', 'CP_SET_CONSTANT', 'CP_SET_CTXSWITCH_IB', - 'CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK', - 'CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT', - 'CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK', - 'CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT', - 'CP_SET_CTXSWITCH_IB_2_DWORDS__MASK', - 'CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT', - 'CP_SET_CTXSWITCH_IB_2_TYPE__MASK', - 'CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT', 'CP_SET_DRAW_INIT_FLAGS', - 'CP_SET_DRAW_STATE', 'CP_SET_DRAW_STATE__0_BINNING', - 'CP_SET_DRAW_STATE__0_COUNT__MASK', - 'CP_SET_DRAW_STATE__0_COUNT__SHIFT', 'CP_SET_DRAW_STATE__0_DIRTY', - 'CP_SET_DRAW_STATE__0_DISABLE', - 'CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS', - 'CP_SET_DRAW_STATE__0_GMEM', - 'CP_SET_DRAW_STATE__0_GROUP_ID__MASK', - 'CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT', - 'CP_SET_DRAW_STATE__0_LOAD_IMMED', 'CP_SET_DRAW_STATE__0_SYSMEM', - 'CP_SET_DRAW_STATE__1_ADDR_LO__MASK', - 'CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT', - 'CP_SET_DRAW_STATE__2_ADDR_HI__MASK', - 'CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT', 'CP_SET_MARKER', - 'CP_SET_MODE', 'CP_SET_PROTECTED_MODE', 'CP_SET_PSEUDO_REG', - 'CP_SET_RENDER_MODE', 'CP_SET_RENDER_MODE_0_MODE__MASK', - 'CP_SET_RENDER_MODE_0_MODE__SHIFT', - 'CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK', - 'CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT', - 'CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK', - 'CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT', - 'CP_SET_RENDER_MODE_3_GMEM_ENABLE', - 'CP_SET_RENDER_MODE_3_VSC_ENABLE', - 'CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK', - 'CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT', - 'CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK', - 'CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT', - 'CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK', - 'CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT', 'CP_SET_SECURE_MODE', - 'CP_SET_SHADER_BASES', 'CP_SET_STATE', 'CP_SET_SUBDRAW_SIZE', - 'CP_SET_THREAD_BOTH', 'CP_SET_THREAD_BR', 'CP_SET_THREAD_BV', - 'CP_SET_UNK_BIN_DATA', 'CP_SET_VISIBILITY_OVERRIDE', - 'CP_SKIP_IB2_ENABLE_GLOBAL', 'CP_SKIP_IB2_ENABLE_LOCAL', - 'CP_SMMU_TABLE_UPDATE', 'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK', - 'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT', - 'CP_SMMU_TABLE_UPDATE_1_ASID__MASK', - 'CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT', - 'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK', - 'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT', - 'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK', - 'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT', - 'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK', - 'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT', 'CP_START_BIN', - 'CP_TEST_TWO_MEMS', 'CP_THREAD_CONTROL', - 'CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE', - 'CP_THREAD_CONTROL_0_SYNC_THREADS', - 'CP_THREAD_CONTROL_0_THREAD__MASK', - 'CP_THREAD_CONTROL_0_THREAD__SHIFT', 'CP_TYPE0_PKT', - 'CP_TYPE1_PKT', 'CP_TYPE2_PKT', 'CP_TYPE3_PKT', 'CP_TYPE4_PKT', - 'CP_TYPE7_PKT', 'CP_VIZ_QUERY', 'CP_WAIT_FOR_IDLE', - 'CP_WAIT_FOR_ME', 'CP_WAIT_IB_PFD_COMPLETE', 'CP_WAIT_MEM_GTE', - 'CP_WAIT_MEM_GTE_0_RESERVED__MASK', - 'CP_WAIT_MEM_GTE_0_RESERVED__SHIFT', - 'CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK', - 'CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT', - 'CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK', - 'CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT', - 'CP_WAIT_MEM_GTE_3_REF__MASK', 'CP_WAIT_MEM_GTE_3_REF__SHIFT', - 'CP_WAIT_MEM_WRITES', 'CP_WAIT_REG_EQ', 'CP_WAIT_REG_GTE', - 'CP_WAIT_REG_MEM', 'CP_WAIT_REG_MEM_0_FUNCTION__MASK', - 'CP_WAIT_REG_MEM_0_FUNCTION__SHIFT', - 'CP_WAIT_REG_MEM_0_POLL__MASK', 'CP_WAIT_REG_MEM_0_POLL__SHIFT', - 'CP_WAIT_REG_MEM_0_SIGNED_COMPARE', - 'CP_WAIT_REG_MEM_0_WRITE_MEMORY', - 'CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK', - 'CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT', - 'CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK', - 'CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT', - 'CP_WAIT_REG_MEM_3_REF__MASK', 'CP_WAIT_REG_MEM_3_REF__SHIFT', - 'CP_WAIT_REG_MEM_4_MASK__MASK', 'CP_WAIT_REG_MEM_4_MASK__SHIFT', - 'CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK', - 'CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT', 'CP_WAIT_TIMESTAMP', - 'CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK', - 'CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT', - 'CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK', - 'CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT', 'CP_WAIT_TWO_REGS', - 'CP_WAIT_TWO_REGS_0_REG0__MASK', 'CP_WAIT_TWO_REGS_0_REG0__SHIFT', - 'CP_WAIT_TWO_REGS_1_REG1__MASK', 'CP_WAIT_TWO_REGS_1_REG1__SHIFT', - 'CP_WAIT_TWO_REGS_2_REF__MASK', 'CP_WAIT_TWO_REGS_2_REF__SHIFT', - 'CP_WAIT_UNTIL_READ', 'CP_WHERE_AM_I', 'CP_WIDE_REG_WRITE', - 'CP_YIELD_ENABLE', 'CS_YALIGN_1', 'CS_YALIGN_2', 'CS_YALIGN_4', - 'CS_YALIGN_8', 'DEPTH6_16', 'DEPTH6_24_8', 'DEPTH6_32', - 'DEPTH6_NONE', 'DEPTHX_16', 'DEPTHX_24_8', 'DEPTHX_32', - 'DIST_ALL_TO_RB0', 'DIST_SCREEN_COORD', 'DITHER_ALWAYS', - 'DITHER_DISABLE', 'DITHER_IF_ALPHA_OFF', 'DI_FACE_BACKFACE_CULL', - 'DI_FACE_CULL_FETCH', 'DI_FACE_CULL_NONE', - 'DI_FACE_FRONTFACE_CULL', 'DI_PT_LINELIST', 'DI_PT_LINELOOP', - 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', 'DI_PT_LINE_ADJ', - 'DI_PT_NONE', 'DI_PT_PATCHES0', 'DI_PT_PATCHES1', - 'DI_PT_PATCHES10', 'DI_PT_PATCHES11', 'DI_PT_PATCHES12', - 'DI_PT_PATCHES13', 'DI_PT_PATCHES14', 'DI_PT_PATCHES15', - 'DI_PT_PATCHES16', 'DI_PT_PATCHES17', 'DI_PT_PATCHES18', - 'DI_PT_PATCHES19', 'DI_PT_PATCHES2', 'DI_PT_PATCHES20', - 'DI_PT_PATCHES21', 'DI_PT_PATCHES22', 'DI_PT_PATCHES23', - 'DI_PT_PATCHES24', 'DI_PT_PATCHES25', 'DI_PT_PATCHES26', - 'DI_PT_PATCHES27', 'DI_PT_PATCHES28', 'DI_PT_PATCHES29', - 'DI_PT_PATCHES3', 'DI_PT_PATCHES30', 'DI_PT_PATCHES31', - 'DI_PT_PATCHES4', 'DI_PT_PATCHES5', 'DI_PT_PATCHES6', - 'DI_PT_PATCHES7', 'DI_PT_PATCHES8', 'DI_PT_PATCHES9', - 'DI_PT_POINTLIST', 'DI_PT_POINTLIST_PSIZE', 'DI_PT_RECTLIST', - 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRISTRIP', - 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_ADJ', 'DI_SRC_SEL_AUTO_INDEX', - 'DI_SRC_SEL_AUTO_XFB', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', - 'DRAW_STRM_ADDRESS', 'DRAW_STRM_SIZE_ADDRESS', 'DUMMY_EVENT', - 'END2D', 'ENDIAN_16IN32', 'ENDIAN_8IN128', 'ENDIAN_8IN16', - 'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE', 'EQUAL_SPACING', - 'EQ_0_PASS', 'EVEN_SPACING', 'EV_DST_ONCHIP', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK', - 'EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT', 'EV_DST_RAM', - 'EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT', - 'EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT', - 'EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT', - 'EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK', - 'EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT', - 'EV_WRITE_ALWAYSON', 'EV_WRITE_REGS_CONTENT', - 'EV_WRITE_TIMESTAMP_SUM', 'EV_WRITE_USER_32B', - 'EV_WRITE_USER_64B', 'FACENESS_FLUSH', 'FACTOR_CONSTANT_ALPHA', - 'FACTOR_CONSTANT_COLOR', 'FACTOR_DST_ALPHA', 'FACTOR_DST_COLOR', - 'FACTOR_ONE', 'FACTOR_ONE_MINUS_CONSTANT_ALPHA', - 'FACTOR_ONE_MINUS_CONSTANT_COLOR', 'FACTOR_ONE_MINUS_DST_ALPHA', - 'FACTOR_ONE_MINUS_DST_COLOR', 'FACTOR_ONE_MINUS_SRC1_ALPHA', - 'FACTOR_ONE_MINUS_SRC1_COLOR', 'FACTOR_ONE_MINUS_SRC_ALPHA', - 'FACTOR_ONE_MINUS_SRC_COLOR', 'FACTOR_SRC1_ALPHA', - 'FACTOR_SRC1_COLOR', 'FACTOR_SRC_ALPHA', - 'FACTOR_SRC_ALPHA_SATURATE', 'FACTOR_SRC_COLOR', 'FACTOR_ZERO', - 'FLUSH_PER_OVERLAP', 'FLUSH_PER_OVERLAP_AND_OVERWRITE', - 'FLUSH_SO_0', 'FLUSH_SO_1', 'FLUSH_SO_2', 'FLUSH_SO_3', - 'FMT6_10_10_10_2_SINT', 'FMT6_10_10_10_2_SNORM', - 'FMT6_10_10_10_2_UINT', 'FMT6_10_10_10_2_UNORM', - 'FMT6_10_10_10_2_UNORM_DEST', 'FMT6_11_11_10_FLOAT', - 'FMT6_16_16_16_16_FLOAT', 'FMT6_16_16_16_16_SINT', - 'FMT6_16_16_16_16_SNORM', 'FMT6_16_16_16_16_UINT', - 'FMT6_16_16_16_16_UNORM', 'FMT6_16_16_16_FLOAT', - 'FMT6_16_16_16_SINT', 'FMT6_16_16_16_SNORM', 'FMT6_16_16_16_UINT', - 'FMT6_16_16_16_UNORM', 'FMT6_16_16_FLOAT', 'FMT6_16_16_SINT', - 'FMT6_16_16_SNORM', 'FMT6_16_16_UINT', 'FMT6_16_16_UNORM', - 'FMT6_16_FLOAT', 'FMT6_16_SINT', 'FMT6_16_SNORM', 'FMT6_16_UINT', - 'FMT6_16_UNORM', 'FMT6_1_5_5_5_UNORM', 'FMT6_32_32_32_32_FIXED', - 'FMT6_32_32_32_32_FLOAT', 'FMT6_32_32_32_32_SINT', - 'FMT6_32_32_32_32_SNORM', 'FMT6_32_32_32_32_UINT', - 'FMT6_32_32_32_32_UNORM', 'FMT6_32_32_32_FIXED', - 'FMT6_32_32_32_FLOAT', 'FMT6_32_32_32_SINT', - 'FMT6_32_32_32_SNORM', 'FMT6_32_32_32_UINT', - 'FMT6_32_32_32_UNORM', 'FMT6_32_32_FIXED', 'FMT6_32_32_FLOAT', - 'FMT6_32_32_SINT', 'FMT6_32_32_SNORM', 'FMT6_32_32_UINT', - 'FMT6_32_32_UNORM', 'FMT6_32_FIXED', 'FMT6_32_FLOAT', - 'FMT6_32_SINT', 'FMT6_32_SNORM', 'FMT6_32_UINT', 'FMT6_32_UNORM', - 'FMT6_4_4_4_4_UNORM', 'FMT6_5_5_5_1_UNORM', 'FMT6_5_6_5_UNORM', - 'FMT6_8_8_8_8_SINT', 'FMT6_8_8_8_8_SNORM', 'FMT6_8_8_8_8_UINT', - 'FMT6_8_8_8_8_UNORM', 'FMT6_8_8_8_SINT', 'FMT6_8_8_8_SNORM', - 'FMT6_8_8_8_UINT', 'FMT6_8_8_8_UNORM', 'FMT6_8_8_8_X8_UNORM', - 'FMT6_8_8_SINT', 'FMT6_8_8_SNORM', 'FMT6_8_8_UINT', - 'FMT6_8_8_UNORM', 'FMT6_8_SINT', 'FMT6_8_SNORM', 'FMT6_8_UINT', - 'FMT6_8_UNORM', 'FMT6_9_9_9_E5_FLOAT', 'FMT6_A8_UNORM', - 'FMT6_ASTC_10x10', 'FMT6_ASTC_10x5', 'FMT6_ASTC_10x6', - 'FMT6_ASTC_10x8', 'FMT6_ASTC_12x10', 'FMT6_ASTC_12x12', - 'FMT6_ASTC_4x4', 'FMT6_ASTC_5x4', 'FMT6_ASTC_5x5', - 'FMT6_ASTC_6x5', 'FMT6_ASTC_6x6', 'FMT6_ASTC_8x5', - 'FMT6_ASTC_8x6', 'FMT6_ASTC_8x8', 'FMT6_BPTC', 'FMT6_BPTC_FLOAT', - 'FMT6_BPTC_UFLOAT', 'FMT6_DXT1', 'FMT6_DXT3', 'FMT6_DXT5', - 'FMT6_ETC1', 'FMT6_ETC2_R11_SNORM', 'FMT6_ETC2_R11_UNORM', - 'FMT6_ETC2_RG11_SNORM', 'FMT6_ETC2_RG11_UNORM', 'FMT6_ETC2_RGB8', - 'FMT6_ETC2_RGB8A1', 'FMT6_ETC2_RGBA8', 'FMT6_G8R8B8R8_422_UNORM', - 'FMT6_L8_A8_UNORM', 'FMT6_NONE', 'FMT6_NV12_4R', - 'FMT6_NV12_4R_UV', 'FMT6_NV12_4R_Y', 'FMT6_NV12_UV', - 'FMT6_NV12_VU', 'FMT6_NV12_Y', 'FMT6_NV21', 'FMT6_P010', - 'FMT6_P010_UV', 'FMT6_P010_Y', 'FMT6_R8G8R8B8_422_UNORM', - 'FMT6_R8_G8B8_2PLANE_420_UNORM', 'FMT6_R8_G8_B8_3PLANE_420_UNORM', - 'FMT6_RGTC1_SNORM', 'FMT6_RGTC1_UNORM', 'FMT6_RGTC2_SNORM', - 'FMT6_RGTC2_UNORM', 'FMT6_TP10', 'FMT6_TP10_UV', 'FMT6_TP10_Y', - 'FMT6_Z24_UINT_S8_UINT', 'FMT6_Z24_UNORM_S8_UINT', - 'FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 'FOUR_QUADS', - 'FRAGCOORD_CENTER', 'FRAGCOORD_SAMPLE', 'FUNC_ALWAYS', - 'FUNC_EQUAL', 'FUNC_GEQUAL', 'FUNC_GREATER', 'FUNC_LEQUAL', - 'FUNC_LESS', 'FUNC_NEVER', 'FUNC_NOTEQUAL', 'GMEM', 'HLSQ_FLUSH', - 'IGNORE_VISIBILITY', 'INDEX4_SIZE_16_BIT', 'INDEX4_SIZE_32_BIT', - 'INDEX4_SIZE_8_BIT', 'INDEX_SIZE_16_BIT', 'INDEX_SIZE_32_BIT', - 'INDEX_SIZE_8_BIT', 'INDEX_SIZE_IGN', 'INDEX_SIZE_INVALID', - 'INDIRECT_OP_INDEXED', 'INDIRECT_OP_INDIRECT_COUNT', - 'INDIRECT_OP_INDIRECT_COUNT_INDEXED', 'INDIRECT_OP_NORMAL', - 'INTERP_FLAT', 'INTERP_ONE', 'INTERP_SMOOTH', 'INTERP_ZERO', - 'IN_CONST_PREFETCH', 'IN_GMU_INTERRUPT', 'IN_IB_END', - 'IN_IB_PREFETCH_END', 'IN_INCR_UPDT_CONST', 'IN_INCR_UPDT_INSTR', - 'IN_INCR_UPDT_STATE', 'IN_INSTR_MATCH', 'IN_INSTR_PREFETCH', - 'IN_PREEMPT', 'IN_SUBBLK_PREFETCH', 'ISAMMODE_CL', 'ISAMMODE_GL', - 'LABEL', 'LRZ_CLEAR', 'LRZ_DIR_GE', 'LRZ_DIR_INVALID', - 'LRZ_DIR_LE', 'LRZ_FLIP_BUFFER', 'LRZ_FLUSH', 'LR_BT', 'LR_TB', - 'MODIFY_TIMESTAMP_ADD_GLOBAL', 'MODIFY_TIMESTAMP_ADD_LOCAL', - 'MODIFY_TIMESTAMP_CLEAR', 'MSAA_EIGHT', 'MSAA_FOUR', 'MSAA_ONE', - 'MSAA_TWO', 'MULTI', 'NE_0_PASS', 'NON_PRIV_SAVE_ADDR', - 'NON_SECURE_SAVE_ADDR', 'NO_FLUSH', 'ODD_SPACING', - 'PC_CCU_FLUSH_COLOR_TS', 'PC_CCU_FLUSH_DEPTH_TS', - 'PC_CCU_INVALIDATE_COLOR', 'PC_CCU_INVALIDATE_DEPTH', - 'PC_CCU_RESOLVE_TS', 'PC_DRAW_LINES', 'PC_DRAW_POINTS', - 'PC_DRAW_TRIANGLES', 'PERFCOUNTER_START', 'PERFCOUNTER_STOP', - 'PERF_CCU_2D_RD_REQ', 'PERF_CCU_2D_WR_REQ', - 'PERF_CCU_BUSY_CYCLES', 'PERF_CCU_COLOR_BLOCKS', - 'PERF_CCU_COLOR_BLOCK_HIT', 'PERF_CCU_COLOR_READ_FLAG0_COUNT', - 'PERF_CCU_COLOR_READ_FLAG1_COUNT', - 'PERF_CCU_COLOR_READ_FLAG2_COUNT', - 'PERF_CCU_COLOR_READ_FLAG3_COUNT', - 'PERF_CCU_COLOR_READ_FLAG4_COUNT', - 'PERF_CCU_COLOR_READ_FLAG5_COUNT', - 'PERF_CCU_COLOR_READ_FLAG6_COUNT', - 'PERF_CCU_COLOR_READ_FLAG8_COUNT', 'PERF_CCU_DEPTH_BLOCKS', - 'PERF_CCU_DEPTH_BLOCK_HIT', 'PERF_CCU_DEPTH_READ_FLAG0_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG1_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG2_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG3_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG4_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG5_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG6_COUNT', - 'PERF_CCU_DEPTH_READ_FLAG8_COUNT', 'PERF_CCU_GMEM_READ', - 'PERF_CCU_GMEM_WRITE', 'PERF_CCU_PARTIAL_BLOCK_READ', - 'PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', - 'PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', - 'PERF_CCU_STARVE_CYCLES_FLAG_RETURN', - 'PERF_CMPDECMP_2D_BUSY_CYCLES', 'PERF_CMPDECMP_2D_OUTPUT_TRANS', - 'PERF_CMPDECMP_2D_PIXELS', 'PERF_CMPDECMP_2D_RD_DATA', - 'PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES', - 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ', - 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN', - 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR', - 'PERF_CMPDECMP_2D_WR_DATA', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', - 'PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', - 'PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', - 'PERF_CMPDECMP_FLAG_FETCH_CYCLES', - 'PERF_CMPDECMP_FLAG_FETCH_SAMPLES', - 'PERF_CMPDECMP_STALL_CYCLES_ARB', - 'PERF_CMPDECMP_VBIF_LATENCY_CYCLES', - 'PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', - 'PERF_CMPDECMP_VBIF_READ_DATA', - 'PERF_CMPDECMP_VBIF_READ_DATA_CCU', - 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', - 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', - 'PERF_CMPDECMP_VBIF_READ_REQUEST', - 'PERF_CMPDECMP_VBIF_WRITE_DATA', - 'PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', - 'PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', - 'PERF_CMPDECMP_VBIF_WRITE_REQUEST', 'PERF_CP_AHB_STALL_SQE_GMU', - 'PERF_CP_AHB_STALL_SQE_RD_OTHER', - 'PERF_CP_AHB_STALL_SQE_WR_OTHER', - 'PERF_CP_AHB_WR_STALL_PRE_DRAWS', 'PERF_CP_ALWAYS_COUNT', - 'PERF_CP_BUSY_CYCLES', 'PERF_CP_BUSY_GFX_CORE_IDLE', - 'PERF_CP_CACHE_FLUSH', 'PERF_CP_CLUSTER0_EMPTY', - 'PERF_CP_CLUSTER1_EMPTY', 'PERF_CP_CLUSTER2_EMPTY', - 'PERF_CP_CLUSTER3_EMPTY', 'PERF_CP_CLUSTER4_EMPTY', - 'PERF_CP_CLUSTER5_EMPTY', 'PERF_CP_CONTEXT_DONE', - 'PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 'PERF_CP_LONG_PREEMPTIONS', - 'PERF_CP_MEMORY_POOL_ABOVE_THRESH', 'PERF_CP_MEMORY_POOL_EMPTY', - 'PERF_CP_MEMORY_POOL_SYNC_STALL', 'PERF_CP_MODE_SWITCH', - 'PERF_CP_NUM_PREEMPTIONS', 'PERF_CP_PM4_DATA', - 'PERF_CP_PM4_HEADERS', 'PERF_CP_PREDICATED_DRAWS_KILLED', - 'PERF_CP_PREEMPTION_REACTION_DELAY', - 'PERF_CP_PREEMPTION_SWITCH_IN_TIME', - 'PERF_CP_PREEMPTION_SWITCH_OUT_TIME', - 'PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 'PERF_CP_SQE_DRAW_EXEC', - 'PERF_CP_SQE_EXEC_PROFILED', 'PERF_CP_SQE_IDLE', - 'PERF_CP_SQE_INSTR_COUNTER', 'PERF_CP_SQE_I_CACHE_STARVE', - 'PERF_CP_SQE_LOAD_STATE_EXEC', 'PERF_CP_SQE_MRB_STARVE', - 'PERF_CP_SQE_PIPE_OUT_STALL', 'PERF_CP_SQE_PM4_STARVE_RB_IB', - 'PERF_CP_SQE_PM4_STARVE_SDS', 'PERF_CP_SQE_PM4_WFI_STALL', - 'PERF_CP_SQE_RRB_STARVE', 'PERF_CP_SQE_SAVE_SDS_STATE', - 'PERF_CP_SQE_SYNC_STALL', 'PERF_CP_SQE_SYS_WFI_STALL', - 'PERF_CP_SQE_T4_EXEC', 'PERF_CP_SQE_VSD_STARVE', - 'PERF_CP_VBIF_READ_BEATS', 'PERF_CP_VBIF_WRITE_BEATS', - 'PERF_CP_VSD_DECODE_STARVE', 'PERF_CP_ZPASS_DONE', - 'PERF_HLSQ_BUSY_CYCLES', 'PERF_HLSQ_COMPUTE_DRAWCALLS', - 'PERF_HLSQ_CS_INVOCATIONS', - 'PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC', - 'PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 'PERF_HLSQ_DUAL_VS_PROG_ACTIVE', - 'PERF_HLSQ_FS_BATCH_COUNT_ZERO', - 'PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', - 'PERF_HLSQ_FS_STAGE_1X_WAVES', 'PERF_HLSQ_FS_STAGE_2X_WAVES', - 'PERF_HLSQ_PIXELS', 'PERF_HLSQ_QUADS', - 'PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', - 'PERF_HLSQ_STALL_CYCLES_SP_STATE', 'PERF_HLSQ_STALL_CYCLES_UCHE', - 'PERF_HLSQ_STALL_CYCLES_VPC', 'PERF_HLSQ_UCHE_LATENCY_COUNT', - 'PERF_HLSQ_UCHE_LATENCY_CYCLES', 'PERF_HLSQ_VS_BATCH_COUNT_ZERO', - 'PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', - 'PERF_HLSQ_WAVE_PENDING_NO_QUAD', 'PERF_LRZ_BUSY_CYCLES', - 'PERF_LRZ_FEEDBACK_ACCEPT', 'PERF_LRZ_FEEDBACK_DISCARD', - 'PERF_LRZ_FEEDBACK_STALL', 'PERF_LRZ_FULLY_COVERED_TILES', - 'PERF_LRZ_FULL_8X8_TILES', 'PERF_LRZ_LRZ_READ', - 'PERF_LRZ_LRZ_WRITE', 'PERF_LRZ_MERGE_CACHE_UPDATING', - 'PERF_LRZ_PARTIAL_8X8_TILES', 'PERF_LRZ_PARTIAL_COVERED_TILES', - 'PERF_LRZ_PRIM_KILLED_BY_LRZ', 'PERF_LRZ_PRIM_KILLED_BY_MASKGEN', - 'PERF_LRZ_RAS_MASK_TRANS', 'PERF_LRZ_READ_LATENCY', - 'PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', 'PERF_LRZ_STALL_CYCLES_RB', - 'PERF_LRZ_STALL_CYCLES_RB_BPLANE', - 'PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 'PERF_LRZ_STALL_CYCLES_UCHE', - 'PERF_LRZ_STALL_CYCLES_VC', 'PERF_LRZ_STALL_CYCLES_VPC', - 'PERF_LRZ_STALL_CYCLES_VSC', 'PERF_LRZ_STARVE_CYCLES_RAS', - 'PERF_LRZ_TILE_KILLED', 'PERF_LRZ_TOTAL_PIXEL', - 'PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', - 'PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 'PERF_PC_2D_DRAWCALLS', - 'PERF_PC_3D_DRAWCALLS', 'PERF_PC_BUSY_CYCLES', - 'PERF_PC_DEAD_PRIM', 'PERF_PC_DS_INVOCATIONS', - 'PERF_PC_DS_PRIMITIVES', 'PERF_PC_GS_INVOCATIONS', - 'PERF_PC_GS_PRIMITIVES', 'PERF_PC_HS_INVOCATIONS', - 'PERF_PC_IA_PRIMITIVES', 'PERF_PC_IA_VERTICES', - 'PERF_PC_INSTANCES', 'PERF_PC_LIVE_PRIM', - 'PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS', - 'PERF_PC_PASS1_TF_STALL_CYCLES', 'PERF_PC_STALL_CYCLES_TESS', - 'PERF_PC_STALL_CYCLES_TSE', 'PERF_PC_STALL_CYCLES_TSE_ONLY', - 'PERF_PC_STALL_CYCLES_UCHE', 'PERF_PC_STALL_CYCLES_VFD', - 'PERF_PC_STALL_CYCLES_VPC', 'PERF_PC_STALL_CYCLES_VPC_ONLY', - 'PERF_PC_STARVE_CYCLES_DI', 'PERF_PC_STARVE_CYCLES_FOR_INDEX', - 'PERF_PC_STARVE_CYCLES_FOR_POSITION', - 'PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR', - 'PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM', - 'PERF_PC_TESS_FACTOR_TRANS', 'PERF_PC_TESS_PC_UV_PATCHES', - 'PERF_PC_TESS_PC_UV_TRANS', 'PERF_PC_TSE_TRANSACTION', - 'PERF_PC_TSE_VERTEX', 'PERF_PC_VERTEX_HITS', - 'PERF_PC_VIS_STREAMS_LOADED', 'PERF_PC_VPC_POS_DATA_TRANSACTION', - 'PERF_PC_VPC_PRIMITIVES', 'PERF_PC_VS_INVOCATIONS', - 'PERF_PC_WORKING_CYCLES', 'PERF_RAS_8X4_TILES', 'PERF_RAS_BLOCKS', - 'PERF_RAS_BUSY_CYCLES', 'PERF_RAS_FULLY_COVERED_8X4_TILES', - 'PERF_RAS_FULLY_COVERED_SUPER_TILES', - 'PERF_RAS_LRZ_INTF_WORKING_CYCLES', 'PERF_RAS_MASKGEN_ACTIVE', - 'PERF_RAS_PRIM_KILLED_INVISILBE', 'PERF_RAS_STALL_CYCLES_LRZ', - 'PERF_RAS_STARVE_CYCLES_TSE', 'PERF_RAS_SUPERTILE_ACTIVE_CYCLES', - 'PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 'PERF_RAS_SUPER_TILES', - 'PERF_RBBM_ALWAYS_COUNT', 'PERF_RBBM_ALWAYS_ON', - 'PERF_RBBM_COM_BUSY', 'PERF_RBBM_DCOM_BUSY', - 'PERF_RBBM_HLSQ_BUSY', 'PERF_RBBM_PC_DCALL_BUSY', - 'PERF_RBBM_PC_VSD_BUSY', 'PERF_RBBM_RAS_BUSY', - 'PERF_RBBM_STATUS_MASKED', 'PERF_RBBM_TESS_BUSY', - 'PERF_RBBM_TSE_BUSY', 'PERF_RBBM_UCHE_BUSY', - 'PERF_RBBM_VBIF_BUSY', 'PERF_RBBM_VSC_BUSY', - 'PERF_RB_2D_ALIVE_CYCLES', 'PERF_RB_2D_INPUT_TRANS', - 'PERF_RB_2D_OUTPUT_RB_DST_TRANS', - 'PERF_RB_2D_OUTPUT_RB_SRC_TRANS', 'PERF_RB_2D_STALL_CYCLES_A2D', - 'PERF_RB_2D_STARVE_CYCLES_DST', 'PERF_RB_2D_STARVE_CYCLES_SP', - 'PERF_RB_2D_STARVE_CYCLES_SRC', 'PERF_RB_2D_VALID_PIXELS', - 'PERF_RB_3D_PIXELS', 'PERF_RB_BLENDED_FP16_COMPONENTS', - 'PERF_RB_BLENDED_FP32_COMPONENTS', - 'PERF_RB_BLENDED_FXP_COMPONENTS', - 'PERF_RB_BLENDER_WORKING_CYCLES', 'PERF_RB_BUSY_CYCLES', - 'PERF_RB_COLOR_PIX_TILES', 'PERF_RB_CPROC_WORKING_CYCLES', - 'PERF_RB_C_READ', 'PERF_RB_C_WRITE', 'PERF_RB_EARLY_Z_ARB3_GRANT', - 'PERF_RB_EARLY_Z_SKIP_GRANT', 'PERF_RB_HLSQ_ACTIVE', - 'PERF_RB_LATE_Z_ARB3_GRANT', 'PERF_RB_PS_INVOCATIONS', - 'PERF_RB_SAMPLER_WORKING_CYCLES', 'PERF_RB_STALL_CYCLES_CCU', - 'PERF_RB_STALL_CYCLES_CCU_COLOR_READ', - 'PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', - 'PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', - 'PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', - 'PERF_RB_STALL_CYCLES_FIFO0_FULL', - 'PERF_RB_STALL_CYCLES_FIFO1_FULL', - 'PERF_RB_STALL_CYCLES_FIFO2_FULL', 'PERF_RB_STALL_CYCLES_HLSQ', - 'PERF_RB_STALL_CYCLES_VPC', 'PERF_RB_STARVE_CYCLES_BARY_PLANE', - 'PERF_RB_STARVE_CYCLES_CCU', 'PERF_RB_STARVE_CYCLES_LRZ_TILE', - 'PERF_RB_STARVE_CYCLES_SP', 'PERF_RB_STARVE_CYCLES_Z_PLANE', - 'PERF_RB_S_FAIL', 'PERF_RB_TOTAL_PASS', - 'PERF_RB_ZPROC_WORKING_CYCLES', 'PERF_RB_Z_FAIL', - 'PERF_RB_Z_PASS', 'PERF_RB_Z_READ', 'PERF_RB_Z_WORKLOAD', - 'PERF_RB_Z_WRITE', 'PERF_SP_ADDR_LOCK_COUNT', - 'PERF_SP_ALU_WORKING_CYCLES', 'PERF_SP_ANY_EU_WORKING', - 'PERF_SP_ANY_EU_WORKING_CS_STAGE', - 'PERF_SP_ANY_EU_WORKING_FS_STAGE', - 'PERF_SP_ANY_EU_WORKING_VS_STAGE', 'PERF_SP_BUSY_CYCLES', - 'PERF_SP_CS_INSTRUCTIONS', 'PERF_SP_DISPATCHER_WORKING_CYCLES', - 'PERF_SP_DS_INSTRUCTIONS', 'PERF_SP_EFU_WORKING_CYCLES', - 'PERF_SP_EXECUTABLE_WAVES', 'PERF_SP_EXPORT_RB_TRANS', - 'PERF_SP_EXPORT_VPC_TRANS', 'PERF_SP_FLOW_CONTROL_WORKING_CYCLES', - 'PERF_SP_FS_INSTRUCTIONS', 'PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_DURATION_CYCLES', - 'PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', - 'PERF_SP_FS_STAGE_WAVE_CYCLES', 'PERF_SP_FS_STAGE_WAVE_SAMPLES', - 'PERF_SP_GM_ATOMICS', 'PERF_SP_GM_LOAD_INSTRUCTIONS', - 'PERF_SP_GM_LOAD_LATENCY_CYCLES', - 'PERF_SP_GM_LOAD_LATENCY_SAMPLES', - 'PERF_SP_GM_STORE_INSTRUCTIONS', 'PERF_SP_GPR_READ', - 'PERF_SP_GPR_READ_CONFLICT', 'PERF_SP_GPR_READ_PREFETCH', - 'PERF_SP_GPR_WRITE', 'PERF_SP_GPR_WRITE_CONFLICT', - 'PERF_SP_GS_INSTRUCTIONS', 'PERF_SP_HS_INSTRUCTIONS', - 'PERF_SP_ICL1_MISSES', 'PERF_SP_ICL1_REQUESTS', - 'PERF_SP_LM_ATOMICS', 'PERF_SP_LM_BANK_CONFLICTS', - 'PERF_SP_LM_LOAD_INSTRUCTIONS', 'PERF_SP_LM_STORE_INSTRUCTIONS', - 'PERF_SP_LM_WORKING_CYCLES', - 'PERF_SP_LOAD_CONTROL_WORKING_CYCLES', - 'PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', - 'PERF_SP_NON_EXECUTION_CYCLES', 'PERF_SP_NON_EXECUTION_LS_CYCLES', - 'PERF_SP_PIXELS_KILLED', 'PERF_SP_SEQUENCER_WORKING_CYCLES', - 'PERF_SP_STALL_CYCLES_RB', 'PERF_SP_STALL_CYCLES_TP', - 'PERF_SP_STALL_CYCLES_UCHE', 'PERF_SP_STALL_CYCLES_VPC', - 'PERF_SP_STARVE_CYCLES_HLSQ', - 'PERF_SP_TEX_CONTROL_WORKING_CYCLES', 'PERF_SP_UCHE_READ_TRANS', - 'PERF_SP_UCHE_WRITE_TRANS', 'PERF_SP_VS_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_DURATION_CYCLES', - 'PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', - 'PERF_SP_VS_STAGE_WAVE_CYCLES', 'PERF_SP_VS_STAGE_WAVE_SAMPLES', - 'PERF_SP_WAVE_CONTEXTS', 'PERF_SP_WAVE_CONTEXT_CYCLES', - 'PERF_SP_WAVE_CTRL_CYCLES', 'PERF_SP_WAVE_EMIT_CYCLES', - 'PERF_SP_WAVE_END_CYCLES', 'PERF_SP_WAVE_FETCH_CYCLES', - 'PERF_SP_WAVE_IDLE_CYCLES', 'PERF_SP_WAVE_JOIN_CYCLES', - 'PERF_SP_WAVE_LOAD_CYCLES', 'PERF_SP_WAVE_LONG_SYNC_CYCLES', - 'PERF_SP_WAVE_NOP_CYCLES', 'PERF_SP_WAVE_SHORT_SYNC_CYCLES', - 'PERF_SP_WAVE_WAIT_CYCLES', 'PERF_SP_WORKING_EU', - 'PERF_SP_WORKING_EU_CS_STAGE', 'PERF_SP_WORKING_EU_FS_STAGE', - 'PERF_SP_WORKING_EU_VS_STAGE', 'PERF_TESS_BUSY_CYCLES', - 'PERF_TESS_STALL_CYCLES_PC', 'PERF_TESS_STARVE_CYCLES_PC', - 'PERF_TESS_WORKING_CYCLES', 'PERF_TP_2D_FILTER_WORKLOAD_16BIT', - 'PERF_TP_2D_FILTER_WORKLOAD_32BIT', 'PERF_TP_2D_OUTPUT_PIXELS', - 'PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', - 'PERF_TP_2D_OUTPUT_PIXELS_POINT', - 'PERF_TP_BACKEND_WORKING_CYCLES', 'PERF_TP_BUSY_CYCLES', - 'PERF_TP_DIVERGENT_QUADS_RECEIVED', - 'PERF_TP_FILTER_WORKLOAD_16BIT', 'PERF_TP_FILTER_WORKLOAD_32BIT', - 'PERF_TP_FLAG_CACHE_MISSES', 'PERF_TP_FLAG_CACHE_REQUESTS', - 'PERF_TP_FLAG_CACHE_REQUEST_LATENCY', - 'PERF_TP_FLAG_CACHE_REQUEST_SAMPLES', - 'PERF_TP_FLAG_CACHE_WORKING_CYCLES', - 'PERF_TP_FRONTEND_WORKING_CYCLES', - 'PERF_TP_L1_5_CACHE_WORKING_CYCLES', - 'PERF_TP_L1_5_L2_COMPRESS_MISS', 'PERF_TP_L1_5_L2_COMPRESS_REQS', - 'PERF_TP_L1_5_L2_REQUESTS', 'PERF_TP_L1_5_MISS_LATENCY_CYCLES', - 'PERF_TP_L1_5_MISS_LATENCY_TRANS', 'PERF_TP_L1_BANK_CONFLICT', - 'PERF_TP_L1_CACHELINE_MISSES', 'PERF_TP_L1_CACHELINE_REQUESTS', - 'PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', - 'PERF_TP_L1_MISSES_ASTC_1TILE', 'PERF_TP_L1_MISSES_ASTC_2TILE', - 'PERF_TP_L1_MISSES_ASTC_4TILE', 'PERF_TP_L1_TAG_WORKING_CYCLES', - 'PERF_TP_LATENCY_CYCLES', 'PERF_TP_LATENCY_TRANS', - 'PERF_TP_OUTPUT_PIXELS', 'PERF_TP_OUTPUT_PIXELS_ANISO', - 'PERF_TP_OUTPUT_PIXELS_BILINEAR', 'PERF_TP_OUTPUT_PIXELS_MIP', - 'PERF_TP_OUTPUT_PIXELS_POINT', 'PERF_TP_OUTPUT_PIXELS_ZERO_LOD', - 'PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', - 'PERF_TP_PRT_NON_RESIDENT_EVENTS', 'PERF_TP_QUADS_1D', - 'PERF_TP_QUADS_2D', 'PERF_TP_QUADS_3D', 'PERF_TP_QUADS_ARRAY', - 'PERF_TP_QUADS_BUFFER', 'PERF_TP_QUADS_CONSTANT_MULTIPLIED', - 'PERF_TP_QUADS_CUBE', 'PERF_TP_QUADS_GRADIENT', - 'PERF_TP_QUADS_OFFSET', 'PERF_TP_QUADS_RECEIVED', - 'PERF_TP_QUADS_SHADOW', 'PERF_TP_SP_TP_TRANS', - 'PERF_TP_STALL_CYCLES_UCHE', 'PERF_TP_STARVE_CYCLES_SP', - 'PERF_TP_STARVE_CYCLES_UCHE', 'PERF_TP_TPA2TPC_TRANS', - 'PERF_TP_TP_SP_TRANS', 'PERF_TSE_2D_ALIVE_CYCLES', - 'PERF_TSE_2D_INPUT_PRIM', 'PERF_TSE_BUSY_CYCLES', - 'PERF_TSE_CINVOCATION', 'PERF_TSE_CLIPPED_PRIM', - 'PERF_TSE_CLIPPING_CYCLES', 'PERF_TSE_CLIP_PLANES', - 'PERF_TSE_CPRIMITIVES', 'PERF_TSE_FACENESS_CULLED_PRIM', - 'PERF_TSE_INPUT_NULL_PRIM', 'PERF_TSE_INPUT_PRIM', - 'PERF_TSE_OUTPUT_NULL_PRIM', 'PERF_TSE_OUTPUT_VISIBLE_PRIM', - 'PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE', - 'PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', 'PERF_TSE_STALL_CYCLES_RAS', - 'PERF_TSE_STARVE_CYCLES_PC', 'PERF_TSE_TRIVAL_REJ_PRIM', - 'PERF_TSE_ZERO_AREA_PRIM', 'PERF_TSE_ZERO_PIXEL_PRIM', - 'PERF_UCHE_BANK_REQ0', 'PERF_UCHE_BANK_REQ1', - 'PERF_UCHE_BANK_REQ2', 'PERF_UCHE_BANK_REQ3', - 'PERF_UCHE_BANK_REQ4', 'PERF_UCHE_BANK_REQ5', - 'PERF_UCHE_BANK_REQ6', 'PERF_UCHE_BANK_REQ7', - 'PERF_UCHE_BUSY_CYCLES', 'PERF_UCHE_DCMP_LATENCY_CYCLES', - 'PERF_UCHE_DCMP_LATENCY_SAMPLES', 'PERF_UCHE_EVICTS', - 'PERF_UCHE_GMEM_READ_BEATS', 'PERF_UCHE_RAM_READ_REQ', - 'PERF_UCHE_RAM_WRITE_REQ', 'PERF_UCHE_READ_REQUESTS_HLSQ', - 'PERF_UCHE_READ_REQUESTS_LRZ', 'PERF_UCHE_READ_REQUESTS_PC', - 'PERF_UCHE_READ_REQUESTS_SP', 'PERF_UCHE_READ_REQUESTS_TP', - 'PERF_UCHE_READ_REQUESTS_VFD', 'PERF_UCHE_STALL_CYCLES_ARBITER', - 'PERF_UCHE_TPH_EXT_FULL', 'PERF_UCHE_TPH_REF_FULL', - 'PERF_UCHE_TPH_VICTIM_FULL', 'PERF_UCHE_VBIF_LATENCY_CYCLES', - 'PERF_UCHE_VBIF_LATENCY_SAMPLES', 'PERF_UCHE_VBIF_READ_BEATS_CH0', - 'PERF_UCHE_VBIF_READ_BEATS_CH1', 'PERF_UCHE_VBIF_READ_BEATS_HLSQ', - 'PERF_UCHE_VBIF_READ_BEATS_LRZ', 'PERF_UCHE_VBIF_READ_BEATS_PC', - 'PERF_UCHE_VBIF_READ_BEATS_SP', 'PERF_UCHE_VBIF_READ_BEATS_TP', - 'PERF_UCHE_VBIF_READ_BEATS_VFD', - 'PERF_UCHE_VBIF_STALL_WRITE_DATA', 'PERF_UCHE_WRITE_REQUESTS_LRZ', - 'PERF_UCHE_WRITE_REQUESTS_SP', 'PERF_UCHE_WRITE_REQUESTS_VPC', - 'PERF_UCHE_WRITE_REQUESTS_VSC', 'PERF_VFDP_STALL_CYCLES_VFD', - 'PERF_VFDP_STALL_CYCLES_VFD_INDEX', - 'PERF_VFDP_STALL_CYCLES_VFD_PROG', 'PERF_VFDP_STARVE_CYCLES_PC', - 'PERF_VFDP_VS_STAGE_WAVES', 'PERF_VFD_ATTR_INFO_FIFO_FULL', - 'PERF_VFD_BUSY_CYCLES', 'PERF_VFD_DECODED_ATTRIBUTE_BYTES', - 'PERF_VFD_LOWER_SHADER_FIBERS', 'PERF_VFD_MODE_0_FIBERS', - 'PERF_VFD_MODE_1_FIBERS', 'PERF_VFD_MODE_2_FIBERS', - 'PERF_VFD_MODE_3_FIBERS', 'PERF_VFD_MODE_4_FIBERS', - 'PERF_VFD_NUM_ATTRIBUTES', 'PERF_VFD_RBUFFER_FULL', - 'PERF_VFD_STALL_CYCLES_SP_ATTR', 'PERF_VFD_STALL_CYCLES_SP_INFO', - 'PERF_VFD_STALL_CYCLES_UCHE', 'PERF_VFD_STALL_CYCLES_VPC_ALLOC', - 'PERF_VFD_STARVE_CYCLES_UCHE', 'PERF_VFD_TOTAL_VERTICES', - 'PERF_VFD_UPPER_SHADER_FIBERS', 'PERF_VPC_BUSY_CYCLES', - 'PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', 'PERF_VPC_LM_TRANSACTION', - 'PERF_VPC_LRZ_ASSIGN_PRIMITIVES', 'PERF_VPC_NUM_ATTR_REQ_LM', - 'PERF_VPC_NUM_VPCRAM_READ_POS', 'PERF_VPC_NUM_VPCRAM_READ_SO', - 'PERF_VPC_NUM_VPCRAM_WRITE', 'PERF_VPC_PC_PRIMITIVES', - 'PERF_VPC_PS_BUSY_CYCLES', 'PERF_VPC_PS_WORKING_CYCLES', - 'PERF_VPC_RB_VISIBLE_PRIMITIVES', 'PERF_VPC_SP_COMPONENTS', - 'PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC', - 'PERF_VPC_STALL_CYCLES_PC', 'PERF_VPC_STALL_CYCLES_SP_LM', - 'PERF_VPC_STALL_CYCLES_UCHE', 'PERF_VPC_STALL_CYCLES_VFD_WACK', - 'PERF_VPC_STALL_CYCLES_VPCRAM_POS', 'PERF_VPC_STARVE_CYCLES_LRZ', - 'PERF_VPC_STARVE_CYCLES_RB', 'PERF_VPC_STARVE_CYCLES_SP', - 'PERF_VPC_STREAMOUT_TRANSACTION', 'PERF_VPC_VPCRAM_FULL_CYCLES', - 'PERF_VPC_VS_BUSY_CYCLES', 'PERF_VPC_VS_WORKING_CYCLES', - 'PERF_VPC_WIT_FULL_CYCLES', 'PERF_VPC_WORKING_CYCLES', - 'PERF_VSC_BUSY_CYCLES', 'PERF_VSC_EOT_NUM', - 'PERF_VSC_INPUT_TILES', 'PERF_VSC_STALL_CYCLES_UCHE', - 'PERF_VSC_WORKING_CYCLES', 'PIPE_BR_WAIT_FOR_BV', - 'PIPE_BV_WAIT_FOR_BR', 'PIPE_CLEAR_BV_BR', 'PIPE_SET_BR_OFFSET', - 'PKT4', 'POLL_MEMORY', 'POLL_ON_CHIP', 'POLL_REGISTER', - 'POLL_SCRATCH', 'POLYMODE6_LINES', 'POLYMODE6_POINTS', - 'POLYMODE6_TRIANGLES', 'PRED_SRC_MEM', 'PRED_TEST', - 'PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK', - 'PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'PRIM_STRM_ADDRESS', - 'PS_DEALLOC', 'PS_DONE_TS', 'PS_REPL_NONE', 'PS_REPL_ONE_MINUS_T', - 'PS_REPL_S', 'PS_REPL_T', 'R2D_FLOAT16', 'R2D_FLOAT32', - 'R2D_INT16', 'R2D_INT32', 'R2D_INT8', 'R2D_RAW', 'R2D_UNORM8', - 'R2D_UNORM8_SRGB', 'RB_BT', 'RB_COMPUTE_PASS', 'RB_COPY_CLEAR', - 'RB_COPY_DEPTH_STENCIL', 'RB_COPY_RESOLVE', 'RB_DONE_TS', - 'RB_RENDERING_PASS', 'RB_RESOLVE_PASS', 'RB_SAVE_IB', - 'RB_TILING_PASS', 'RECTANGULAR', 'REG_A4XX_CP_DRAW_INDIRECT_0', - 'REG_A4XX_CP_DRAW_INDIRECT_1', 'REG_A4XX_CP_DRAW_INDX_INDIRECT_0', - 'REG_A4XX_CP_DRAW_INDX_INDIRECT_1', - 'REG_A4XX_CP_DRAW_INDX_INDIRECT_2', - 'REG_A4XX_CP_DRAW_INDX_INDIRECT_3', - 'REG_A4XX_CP_EXEC_CS_INDIRECT_0', - 'REG_A4XX_CP_EXEC_CS_INDIRECT_1', - 'REG_A4XX_CP_EXEC_CS_INDIRECT_2', 'REG_A5XX_CP_DRAW_INDIRECT_1', - 'REG_A5XX_CP_DRAW_INDIRECT_2', - 'REG_A5XX_CP_DRAW_INDIRECT_INDIRECT', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_1', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_2', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_3', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_4', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_5', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT', - 'REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_4', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_5', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_6', - 'REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE', - 'REG_A5XX_CP_EXEC_CS_INDIRECT_1', - 'REG_A5XX_CP_EXEC_CS_INDIRECT_2', - 'REG_A5XX_CP_EXEC_CS_INDIRECT_3', 'REG_A6XX_CP_2D_EVENT_END', - 'REG_A6XX_CP_2D_EVENT_START', 'REG_A6XX_CP_ADDR_MODE_CNTL', - 'REG_A6XX_CP_AHB_CNTL', 'REG_A6XX_CP_ALWAYS_ON_COUNTER', - 'REG_A6XX_CP_APERTURE_CNTL_CD', 'REG_A6XX_CP_APERTURE_CNTL_HOST', - 'REG_A6XX_CP_APRIV_CNTL', 'REG_A6XX_CP_CHICKEN_DBG', - 'REG_A6XX_CP_CONTEXT_SWITCH_CNTL', - 'REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR', - 'REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR', - 'REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR', - 'REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO', - 'REG_A6XX_CP_CP2GMU_STATUS', 'REG_A6XX_CP_CRASH_DUMP_CNTL', - 'REG_A6XX_CP_CRASH_DUMP_STATUS', 'REG_A6XX_CP_CRASH_SCRIPT_BASE', - 'REG_A6XX_CP_DBG_ECO_CNTL', 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_0', - 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_1', - 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT', - 'REG_A6XX_CP_DRAW_STATE_ADDR', 'REG_A6XX_CP_DRAW_STATE_DATA', - 'REG_A6XX_CP_EVENT_END', 'REG_A6XX_CP_EVENT_START', - 'REG_A6XX_CP_HW_FAULT', 'REG_A6XX_CP_IB1_BASE', - 'REG_A6XX_CP_IB1_DWORDS', 'REG_A6XX_CP_IB1_REM_SIZE', - 'REG_A6XX_CP_IB2_BASE', 'REG_A6XX_CP_IB2_DWORDS', - 'REG_A6XX_CP_IB2_REM_SIZE', 'REG_A6XX_CP_INTERRUPT_STATUS', - 'REG_A6XX_CP_LPAC_PROG_FIFO_SIZE', 'REG_A6XX_CP_LPAC_SQE_CNTL', - 'REG_A6XX_CP_LPAC_SQE_INSTR_BASE', - 'REG_A6XX_CP_MEM_POOL_DBG_ADDR', 'REG_A6XX_CP_MEM_POOL_DBG_DATA', - 'REG_A6XX_CP_MEM_POOL_SIZE', 'REG_A6XX_CP_MISC_CNTL', - 'REG_A6XX_CP_MRB_BASE', 'REG_A6XX_CP_MRB_DWORDS', - 'REG_A6XX_CP_MRB_REM_SIZE', 'REG_A6XX_CP_PREEMPT_THRESHOLD', - 'REG_A6XX_CP_PROTECT_CNTL', 'REG_A6XX_CP_PROTECT_STATUS', - 'REG_A6XX_CP_RB_BASE', 'REG_A6XX_CP_RB_CNTL', - 'REG_A6XX_CP_RB_RPTR', 'REG_A6XX_CP_RB_RPTR_ADDR', - 'REG_A6XX_CP_RB_WPTR', 'REG_A6XX_CP_REG_TEST_0', - 'REG_A6XX_CP_REG_TEST_PRED_MASK', 'REG_A6XX_CP_REG_TEST_PRED_VAL', - 'REG_A6XX_CP_ROQ_AVAIL_IB1', 'REG_A6XX_CP_ROQ_AVAIL_IB2', - 'REG_A6XX_CP_ROQ_AVAIL_MRB', 'REG_A6XX_CP_ROQ_AVAIL_RB', - 'REG_A6XX_CP_ROQ_AVAIL_SDS', 'REG_A6XX_CP_ROQ_AVAIL_VSD', - 'REG_A6XX_CP_ROQ_DBG_ADDR', 'REG_A6XX_CP_ROQ_DBG_DATA', - 'REG_A6XX_CP_ROQ_IB1_STAT', 'REG_A6XX_CP_ROQ_IB2_STAT', - 'REG_A6XX_CP_ROQ_MRB_STAT', 'REG_A6XX_CP_ROQ_RB_STAT', - 'REG_A6XX_CP_ROQ_SDS_STAT', 'REG_A6XX_CP_ROQ_THRESHOLDS_1', - 'REG_A6XX_CP_ROQ_THRESHOLDS_2', 'REG_A6XX_CP_ROQ_VSD_STAT', - 'REG_A6XX_CP_SDS_BASE', 'REG_A6XX_CP_SDS_DWORDS', - 'REG_A6XX_CP_SDS_REM_SIZE', 'REG_A6XX_CP_SET_MARKER_0', - 'REG_A6XX_CP_SQE_CNTL', 'REG_A6XX_CP_SQE_INSTR_BASE', - 'REG_A6XX_CP_SQE_STAT_ADDR', 'REG_A6XX_CP_SQE_STAT_DATA', - 'REG_A6XX_CP_SQE_UCODE_DBG_ADDR', - 'REG_A6XX_CP_SQE_UCODE_DBG_DATA', 'REG_A6XX_CP_STATUS_1', - 'REG_A6XX_CP_VSD_BASE', 'REG_A6XX_CP_VSD_DWORDS', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1', - 'REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2', - 'REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0', - 'REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0', - 'REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_CNTLM', - 'REG_A6XX_DBGC_CFG_DBGBUS_CNTLT', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2', - 'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2', - 'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_A', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_B', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_C', - 'REG_A6XX_DBGC_CFG_DBGBUS_SEL_D', - 'REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1', - 'REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2', 'REG_A6XX_GBIF_HALT', - 'REG_A6XX_GBIF_HALT_ACK', 'REG_A6XX_GBIF_PERF_CNT_HIGH0', - 'REG_A6XX_GBIF_PERF_CNT_HIGH1', 'REG_A6XX_GBIF_PERF_CNT_HIGH2', - 'REG_A6XX_GBIF_PERF_CNT_HIGH3', 'REG_A6XX_GBIF_PERF_CNT_LOW0', - 'REG_A6XX_GBIF_PERF_CNT_LOW1', 'REG_A6XX_GBIF_PERF_CNT_LOW2', - 'REG_A6XX_GBIF_PERF_CNT_LOW3', 'REG_A6XX_GBIF_PERF_CNT_SEL', - 'REG_A6XX_GBIF_PERF_PWR_CNT_CLR', 'REG_A6XX_GBIF_PERF_PWR_CNT_EN', - 'REG_A6XX_GBIF_PERF_PWR_CNT_SEL', 'REG_A6XX_GBIF_PWR_CNT_HIGH0', - 'REG_A6XX_GBIF_PWR_CNT_HIGH1', 'REG_A6XX_GBIF_PWR_CNT_HIGH2', - 'REG_A6XX_GBIF_PWR_CNT_LOW0', 'REG_A6XX_GBIF_PWR_CNT_LOW1', - 'REG_A6XX_GBIF_PWR_CNT_LOW2', 'REG_A6XX_GBIF_QSB_SIDE0', - 'REG_A6XX_GBIF_QSB_SIDE1', 'REG_A6XX_GBIF_QSB_SIDE2', - 'REG_A6XX_GBIF_QSB_SIDE3', 'REG_A6XX_GBIF_SCACHE_CNTL0', - 'REG_A6XX_GBIF_SCACHE_CNTL1', 'REG_A6XX_GRAS_2D_BLIT_CNTL', - 'REG_A6XX_GRAS_2D_DST_BR', 'REG_A6XX_GRAS_2D_DST_TL', - 'REG_A6XX_GRAS_2D_RESOLVE_CNTL_1', - 'REG_A6XX_GRAS_2D_RESOLVE_CNTL_2', 'REG_A6XX_GRAS_2D_SRC_BR_X', - 'REG_A6XX_GRAS_2D_SRC_BR_Y', 'REG_A6XX_GRAS_2D_SRC_TL_X', - 'REG_A6XX_GRAS_2D_SRC_TL_Y', 'REG_A6XX_GRAS_2D_UNKNOWN_8407', - 'REG_A6XX_GRAS_2D_UNKNOWN_8408', 'REG_A6XX_GRAS_2D_UNKNOWN_8409', - 'REG_A6XX_GRAS_ADDR_MODE_CNTL', 'REG_A6XX_GRAS_BIN_CONTROL', - 'REG_A6XX_GRAS_CL_CNTL', 'REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ', - 'REG_A6XX_GRAS_CNTL', 'REG_A6XX_GRAS_DBG_ECO_CNTL', - 'REG_A6XX_GRAS_DEST_MSAA_CNTL', 'REG_A6XX_GRAS_DS_CL_CNTL', - 'REG_A6XX_GRAS_DS_LAYER_CNTL', 'REG_A6XX_GRAS_GS_CL_CNTL', - 'REG_A6XX_GRAS_GS_LAYER_CNTL', 'REG_A6XX_GRAS_LRZ_BUFFER_BASE', - 'REG_A6XX_GRAS_LRZ_BUFFER_PITCH', 'REG_A6XX_GRAS_LRZ_CNTL', - 'REG_A6XX_GRAS_LRZ_DEPTH_VIEW', - 'REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE', - 'REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0', - 'REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL', - 'REG_A6XX_GRAS_MAX_LAYER_INDEX', 'REG_A6XX_GRAS_RAS_MSAA_CNTL', - 'REG_A6XX_GRAS_SAMPLE_CNTL', 'REG_A6XX_GRAS_SAMPLE_CONFIG', - 'REG_A6XX_GRAS_SAMPLE_LOCATION_0', - 'REG_A6XX_GRAS_SAMPLE_LOCATION_1', 'REG_A6XX_GRAS_SC_CNTL', - 'REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR', - 'REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL', 'REG_A6XX_GRAS_SU_CNTL', - 'REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL', - 'REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO', - 'REG_A6XX_GRAS_SU_DEPTH_CNTL', - 'REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL', - 'REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL', - 'REG_A6XX_GRAS_SU_POINT_MINMAX', 'REG_A6XX_GRAS_SU_POINT_SIZE', - 'REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET', - 'REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP', - 'REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE', - 'REG_A6XX_GRAS_SU_STENCIL_CNTL', 'REG_A6XX_GRAS_UNKNOWN_80AF', - 'REG_A6XX_GRAS_UNKNOWN_8110', 'REG_A6XX_GRAS_VS_CL_CNTL', - 'REG_A6XX_GRAS_VS_LAYER_CNTL', 'REG_A6XX_HLSQ_2D_EVENT_CMD', - 'REG_A6XX_HLSQ_ADDR_MODE_CNTL', - 'REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE', - 'REG_A6XX_HLSQ_CONTROL_1_REG', 'REG_A6XX_HLSQ_CONTROL_2_REG', - 'REG_A6XX_HLSQ_CONTROL_3_REG', 'REG_A6XX_HLSQ_CONTROL_4_REG', - 'REG_A6XX_HLSQ_CONTROL_5_REG', 'REG_A6XX_HLSQ_CS_CNTL', - 'REG_A6XX_HLSQ_CS_CNTL_0', 'REG_A6XX_HLSQ_CS_CNTL_1', - 'REG_A6XX_HLSQ_CS_KERNEL_GROUP_X', - 'REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y', - 'REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z', 'REG_A6XX_HLSQ_CS_NDRANGE_0', - 'REG_A6XX_HLSQ_CS_NDRANGE_1', 'REG_A6XX_HLSQ_CS_NDRANGE_2', - 'REG_A6XX_HLSQ_CS_NDRANGE_3', 'REG_A6XX_HLSQ_CS_NDRANGE_4', - 'REG_A6XX_HLSQ_CS_NDRANGE_5', 'REG_A6XX_HLSQ_CS_NDRANGE_6', - 'REG_A6XX_HLSQ_CS_UNKNOWN_B9D0', - 'REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE', - 'REG_A6XX_HLSQ_DBG_ECO_CNTL', 'REG_A6XX_HLSQ_DBG_READ_SEL', - 'REG_A6XX_HLSQ_DISPATCH_CMD', 'REG_A6XX_HLSQ_DRAW_CMD', - 'REG_A6XX_HLSQ_DS_CNTL', 'REG_A6XX_HLSQ_EVENT_CMD', - 'REG_A6XX_HLSQ_FS_CNTL', 'REG_A6XX_HLSQ_FS_CNTL_0', - 'REG_A6XX_HLSQ_GS_CNTL', 'REG_A6XX_HLSQ_HS_CNTL', - 'REG_A6XX_HLSQ_INVALIDATE_CMD', - 'REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD', - 'REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA', - 'REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR', - 'REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD', - 'REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA', - 'REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR', - 'REG_A6XX_HLSQ_SHARED_CONSTS', 'REG_A6XX_HLSQ_UNKNOWN_B981', - 'REG_A6XX_HLSQ_UNKNOWN_BE00', 'REG_A6XX_HLSQ_UNKNOWN_BE01', - 'REG_A6XX_HLSQ_UNKNOWN_BE08', 'REG_A6XX_HLSQ_VS_CNTL', - 'REG_A6XX_PC_2D_EVENT_CMD', 'REG_A6XX_PC_ADDR_MODE_CNTL', - 'REG_A6XX_PC_BIN_DRAW_STRM', 'REG_A6XX_PC_BIN_PRIM_STRM', - 'REG_A6XX_PC_DBG_ECO_CNTL', - 'REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL', - 'REG_A6XX_PC_DISPATCH_CMD', 'REG_A6XX_PC_DRAW_CMD', - 'REG_A6XX_PC_DRAW_FIRST_INDX', 'REG_A6XX_PC_DRAW_INDX_BASE', - 'REG_A6XX_PC_DRAW_INITIATOR', 'REG_A6XX_PC_DRAW_MAX_INDICES', - 'REG_A6XX_PC_DRAW_NUM_INDICES', 'REG_A6XX_PC_DRAW_NUM_INSTANCES', - 'REG_A6XX_PC_DS_OUT_CNTL', 'REG_A6XX_PC_EVENT_CMD', - 'REG_A6XX_PC_GS_OUT_CNTL', 'REG_A6XX_PC_HS_INPUT_SIZE', - 'REG_A6XX_PC_HS_OUT_CNTL', 'REG_A6XX_PC_MARKER', - 'REG_A6XX_PC_MODE_CNTL', 'REG_A6XX_PC_MULTIVIEW_CNTL', - 'REG_A6XX_PC_MULTIVIEW_MASK', 'REG_A6XX_PC_POLYGON_MODE', - 'REG_A6XX_PC_POWER_CNTL', 'REG_A6XX_PC_PRIMITIVE_CNTL_0', - 'REG_A6XX_PC_PRIMITIVE_CNTL_5', 'REG_A6XX_PC_PRIMITIVE_CNTL_6', - 'REG_A6XX_PC_PS_CNTL', 'REG_A6XX_PC_RASTER_CNTL', - 'REG_A6XX_PC_RESTART_INDEX', 'REG_A6XX_PC_SO_STREAM_CNTL', - 'REG_A6XX_PC_TESSFACTOR_ADDR', 'REG_A6XX_PC_TESS_CNTL', - 'REG_A6XX_PC_TESS_NUM_VERTEX', 'REG_A6XX_PC_UNKNOWN_9E72', - 'REG_A6XX_PC_VISIBILITY_OVERRIDE', 'REG_A6XX_PC_VSTREAM_CONTROL', - 'REG_A6XX_PC_VS_OUT_CNTL', 'REG_A6XX_PDC_GPU_ENABLE_PDC', - 'REG_A6XX_PDC_GPU_SEQ_MEM_0', 'REG_A6XX_PDC_GPU_SEQ_START_ADDR', - 'REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS0_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS0_CONTROL', - 'REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS1_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS1_CONTROL', - 'REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS2_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS2_CONTROL', - 'REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR', - 'REG_A6XX_PDC_GPU_TCS3_CMD0_DATA', - 'REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID', - 'REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK', - 'REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK', - 'REG_A6XX_PDC_GPU_TCS3_CONTROL', - 'REG_A6XX_RBBM_BLOCK_SW_RESET_CMD', - 'REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2', 'REG_A6XX_RBBM_CLOCK_CNTL', - 'REG_A6XX_RBBM_CLOCK_CNTL2_RAC', 'REG_A6XX_RBBM_CLOCK_CNTL2_RB0', - 'REG_A6XX_RBBM_CLOCK_CNTL2_RB1', 'REG_A6XX_RBBM_CLOCK_CNTL2_RB2', - 'REG_A6XX_RBBM_CLOCK_CNTL2_RB3', 'REG_A6XX_RBBM_CLOCK_CNTL2_SP0', - 'REG_A6XX_RBBM_CLOCK_CNTL2_SP1', 'REG_A6XX_RBBM_CLOCK_CNTL2_SP2', - 'REG_A6XX_RBBM_CLOCK_CNTL2_SP3', 'REG_A6XX_RBBM_CLOCK_CNTL2_TP0', - 'REG_A6XX_RBBM_CLOCK_CNTL2_TP1', 'REG_A6XX_RBBM_CLOCK_CNTL2_TP2', - 'REG_A6XX_RBBM_CLOCK_CNTL2_TP3', 'REG_A6XX_RBBM_CLOCK_CNTL2_UCHE', - 'REG_A6XX_RBBM_CLOCK_CNTL3_TP0', 'REG_A6XX_RBBM_CLOCK_CNTL3_TP1', - 'REG_A6XX_RBBM_CLOCK_CNTL3_TP2', 'REG_A6XX_RBBM_CLOCK_CNTL3_TP3', - 'REG_A6XX_RBBM_CLOCK_CNTL3_UCHE', 'REG_A6XX_RBBM_CLOCK_CNTL4_TP0', - 'REG_A6XX_RBBM_CLOCK_CNTL4_TP1', 'REG_A6XX_RBBM_CLOCK_CNTL4_TP2', - 'REG_A6XX_RBBM_CLOCK_CNTL4_TP3', 'REG_A6XX_RBBM_CLOCK_CNTL4_UCHE', - 'REG_A6XX_RBBM_CLOCK_CNTL_CCU0', 'REG_A6XX_RBBM_CLOCK_CNTL_CCU1', - 'REG_A6XX_RBBM_CLOCK_CNTL_CCU2', 'REG_A6XX_RBBM_CLOCK_CNTL_CCU3', - 'REG_A6XX_RBBM_CLOCK_CNTL_FCHE', 'REG_A6XX_RBBM_CLOCK_CNTL_GLC', - 'REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX', - 'REG_A6XX_RBBM_CLOCK_CNTL_MHUB', 'REG_A6XX_RBBM_CLOCK_CNTL_RAC', - 'REG_A6XX_RBBM_CLOCK_CNTL_RB0', 'REG_A6XX_RBBM_CLOCK_CNTL_RB1', - 'REG_A6XX_RBBM_CLOCK_CNTL_RB2', 'REG_A6XX_RBBM_CLOCK_CNTL_RB3', - 'REG_A6XX_RBBM_CLOCK_CNTL_SP0', 'REG_A6XX_RBBM_CLOCK_CNTL_SP1', - 'REG_A6XX_RBBM_CLOCK_CNTL_SP2', 'REG_A6XX_RBBM_CLOCK_CNTL_SP3', - 'REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE', - 'REG_A6XX_RBBM_CLOCK_CNTL_TP0', 'REG_A6XX_RBBM_CLOCK_CNTL_TP1', - 'REG_A6XX_RBBM_CLOCK_CNTL_TP2', 'REG_A6XX_RBBM_CLOCK_CNTL_TP3', - 'REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM', - 'REG_A6XX_RBBM_CLOCK_CNTL_UCHE', 'REG_A6XX_RBBM_CLOCK_DELAY2_TP0', - 'REG_A6XX_RBBM_CLOCK_DELAY2_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY2_TP2', - 'REG_A6XX_RBBM_CLOCK_DELAY2_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP0', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP2', - 'REG_A6XX_RBBM_CLOCK_DELAY3_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP0', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP2', - 'REG_A6XX_RBBM_CLOCK_DELAY4_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY_FCHE', 'REG_A6XX_RBBM_CLOCK_DELAY_GLC', - 'REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX', - 'REG_A6XX_RBBM_CLOCK_DELAY_GPC', 'REG_A6XX_RBBM_CLOCK_DELAY_HLSQ', - 'REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2', - 'REG_A6XX_RBBM_CLOCK_DELAY_MHUB', 'REG_A6XX_RBBM_CLOCK_DELAY_RAC', - 'REG_A6XX_RBBM_CLOCK_DELAY_SP0', 'REG_A6XX_RBBM_CLOCK_DELAY_SP1', - 'REG_A6XX_RBBM_CLOCK_DELAY_SP2', 'REG_A6XX_RBBM_CLOCK_DELAY_SP3', - 'REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE', - 'REG_A6XX_RBBM_CLOCK_DELAY_TP0', 'REG_A6XX_RBBM_CLOCK_DELAY_TP1', - 'REG_A6XX_RBBM_CLOCK_DELAY_TP2', 'REG_A6XX_RBBM_CLOCK_DELAY_TP3', - 'REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM', - 'REG_A6XX_RBBM_CLOCK_DELAY_UCHE', 'REG_A6XX_RBBM_CLOCK_DELAY_VFD', - 'REG_A6XX_RBBM_CLOCK_HYST2_TP0', 'REG_A6XX_RBBM_CLOCK_HYST2_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST2_TP2', 'REG_A6XX_RBBM_CLOCK_HYST2_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST3_TP0', 'REG_A6XX_RBBM_CLOCK_HYST3_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST3_TP2', 'REG_A6XX_RBBM_CLOCK_HYST3_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST4_TP0', 'REG_A6XX_RBBM_CLOCK_HYST4_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST4_TP2', 'REG_A6XX_RBBM_CLOCK_HYST4_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST_FCHE', 'REG_A6XX_RBBM_CLOCK_HYST_GLC', - 'REG_A6XX_RBBM_CLOCK_HYST_GMU_GX', 'REG_A6XX_RBBM_CLOCK_HYST_GPC', - 'REG_A6XX_RBBM_CLOCK_HYST_HLSQ', 'REG_A6XX_RBBM_CLOCK_HYST_MHUB', - 'REG_A6XX_RBBM_CLOCK_HYST_RAC', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2', - 'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3', - 'REG_A6XX_RBBM_CLOCK_HYST_SP0', 'REG_A6XX_RBBM_CLOCK_HYST_SP1', - 'REG_A6XX_RBBM_CLOCK_HYST_SP2', 'REG_A6XX_RBBM_CLOCK_HYST_SP3', - 'REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE', - 'REG_A6XX_RBBM_CLOCK_HYST_TP0', 'REG_A6XX_RBBM_CLOCK_HYST_TP1', - 'REG_A6XX_RBBM_CLOCK_HYST_TP2', 'REG_A6XX_RBBM_CLOCK_HYST_TP3', - 'REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM', - 'REG_A6XX_RBBM_CLOCK_HYST_UCHE', 'REG_A6XX_RBBM_CLOCK_HYST_VFD', - 'REG_A6XX_RBBM_CLOCK_MODE_GPC', 'REG_A6XX_RBBM_CLOCK_MODE_HLSQ', - 'REG_A6XX_RBBM_CLOCK_MODE_VFD', - 'REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL', 'REG_A6XX_RBBM_GBIF_HALT', - 'REG_A6XX_RBBM_GBIF_HALT_ACK', 'REG_A6XX_RBBM_GPR0_CNTL', - 'REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL', - 'REG_A6XX_RBBM_INT_0_MASK', 'REG_A6XX_RBBM_INT_0_STATUS', - 'REG_A6XX_RBBM_INT_CLEAR_CMD', 'REG_A6XX_RBBM_ISDB_CNT', - 'REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL', - 'REG_A6XX_RBBM_PERFCTR_CNTL', - 'REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD0', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD1', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD2', - 'REG_A6XX_RBBM_PERFCTR_LOAD_CMD3', - 'REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI', - 'REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO', - 'REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD', - 'REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS', - 'REG_A6XX_RBBM_PRIMCTR_0_HI', 'REG_A6XX_RBBM_PRIMCTR_0_LO', - 'REG_A6XX_RBBM_PRIMCTR_10_HI', 'REG_A6XX_RBBM_PRIMCTR_10_LO', - 'REG_A6XX_RBBM_PRIMCTR_1_HI', 'REG_A6XX_RBBM_PRIMCTR_1_LO', - 'REG_A6XX_RBBM_PRIMCTR_2_HI', 'REG_A6XX_RBBM_PRIMCTR_2_LO', - 'REG_A6XX_RBBM_PRIMCTR_3_HI', 'REG_A6XX_RBBM_PRIMCTR_3_LO', - 'REG_A6XX_RBBM_PRIMCTR_4_HI', 'REG_A6XX_RBBM_PRIMCTR_4_LO', - 'REG_A6XX_RBBM_PRIMCTR_5_HI', 'REG_A6XX_RBBM_PRIMCTR_5_LO', - 'REG_A6XX_RBBM_PRIMCTR_6_HI', 'REG_A6XX_RBBM_PRIMCTR_6_LO', - 'REG_A6XX_RBBM_PRIMCTR_7_HI', 'REG_A6XX_RBBM_PRIMCTR_7_LO', - 'REG_A6XX_RBBM_PRIMCTR_8_HI', 'REG_A6XX_RBBM_PRIMCTR_8_LO', - 'REG_A6XX_RBBM_PRIMCTR_9_HI', 'REG_A6XX_RBBM_PRIMCTR_9_LO', - 'REG_A6XX_RBBM_RAC_THRESHOLD_CNT', - 'REG_A6XX_RBBM_SECVID_TRUST_CNTL', - 'REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL', - 'REG_A6XX_RBBM_SECVID_TSB_CNTL', - 'REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE', - 'REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE', - 'REG_A6XX_RBBM_SP_HYST_CNT', 'REG_A6XX_RBBM_STATUS', - 'REG_A6XX_RBBM_STATUS1', 'REG_A6XX_RBBM_STATUS2', - 'REG_A6XX_RBBM_STATUS3', 'REG_A6XX_RBBM_SW_RESET_CMD', - 'REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL', - 'REG_A6XX_RBBM_VBIF_GX_RESET_STATUS', - 'REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD', 'REG_A6XX_RB_2D_BLIT_CNTL', - 'REG_A6XX_RB_2D_DST', 'REG_A6XX_RB_2D_DST_FLAGS', - 'REG_A6XX_RB_2D_DST_FLAGS_PITCH', - 'REG_A6XX_RB_2D_DST_FLAGS_PLANE', - 'REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH', 'REG_A6XX_RB_2D_DST_INFO', - 'REG_A6XX_RB_2D_DST_PITCH', 'REG_A6XX_RB_2D_DST_PLANE1', - 'REG_A6XX_RB_2D_DST_PLANE2', 'REG_A6XX_RB_2D_DST_PLANE_PITCH', - 'REG_A6XX_RB_2D_SRC_SOLID_C0', 'REG_A6XX_RB_2D_SRC_SOLID_C1', - 'REG_A6XX_RB_2D_SRC_SOLID_C2', 'REG_A6XX_RB_2D_SRC_SOLID_C3', - 'REG_A6XX_RB_2D_UNKNOWN_8C01', 'REG_A6XX_RB_ADDR_MODE_CNTL', - 'REG_A6XX_RB_ALPHA_CONTROL', 'REG_A6XX_RB_BIN_CONTROL', - 'REG_A6XX_RB_BIN_CONTROL2', 'REG_A6XX_RB_BLEND_ALPHA_F32', - 'REG_A6XX_RB_BLEND_BLUE_F32', 'REG_A6XX_RB_BLEND_CNTL', - 'REG_A6XX_RB_BLEND_GREEN_F32', 'REG_A6XX_RB_BLEND_RED_F32', - 'REG_A6XX_RB_BLIT_BASE_GMEM', 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0', - 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1', - 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2', - 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3', 'REG_A6XX_RB_BLIT_DST', - 'REG_A6XX_RB_BLIT_DST_ARRAY_PITCH', 'REG_A6XX_RB_BLIT_DST_INFO', - 'REG_A6XX_RB_BLIT_DST_PITCH', 'REG_A6XX_RB_BLIT_FLAG_DST', - 'REG_A6XX_RB_BLIT_FLAG_DST_PITCH', - 'REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL', 'REG_A6XX_RB_BLIT_INFO', - 'REG_A6XX_RB_BLIT_SCISSOR_BR', 'REG_A6XX_RB_BLIT_SCISSOR_TL', - 'REG_A6XX_RB_CCU_CNTL', 'REG_A6XX_RB_CMP_DBG_ECO_CNTL', - 'REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE', - 'REG_A6XX_RB_DBG_ECO_CNTL', - 'REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH', - 'REG_A6XX_RB_DEPTH_BUFFER_BASE', - 'REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM', - 'REG_A6XX_RB_DEPTH_BUFFER_INFO', 'REG_A6XX_RB_DEPTH_BUFFER_PITCH', - 'REG_A6XX_RB_DEPTH_CNTL', 'REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE', - 'REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH', - 'REG_A6XX_RB_DEPTH_PLANE_CNTL', 'REG_A6XX_RB_DEST_MSAA_CNTL', - 'REG_A6XX_RB_DITHER_CNTL', 'REG_A6XX_RB_FS_OUTPUT_CNTL0', - 'REG_A6XX_RB_FS_OUTPUT_CNTL1', 'REG_A6XX_RB_LRZ_CNTL', - 'REG_A6XX_RB_NC_MODE_CNTL', 'REG_A6XX_RB_RAS_MSAA_CNTL', - 'REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD', - 'REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST', - 'REG_A6XX_RB_RENDER_CNTL', 'REG_A6XX_RB_RENDER_COMPONENTS', - 'REG_A6XX_RB_RENDER_CONTROL0', 'REG_A6XX_RB_RENDER_CONTROL1', - 'REG_A6XX_RB_SAMPLE_CNTL', 'REG_A6XX_RB_SAMPLE_CONFIG', - 'REG_A6XX_RB_SAMPLE_COUNT_ADDR', - 'REG_A6XX_RB_SAMPLE_COUNT_CONTROL', - 'REG_A6XX_RB_SAMPLE_LOCATION_0', 'REG_A6XX_RB_SAMPLE_LOCATION_1', - 'REG_A6XX_RB_SRGB_CNTL', 'REG_A6XX_RB_STENCILMASK', - 'REG_A6XX_RB_STENCILREF', 'REG_A6XX_RB_STENCILWRMASK', - 'REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH', - 'REG_A6XX_RB_STENCIL_BUFFER_BASE', - 'REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM', - 'REG_A6XX_RB_STENCIL_BUFFER_PITCH', 'REG_A6XX_RB_STENCIL_CONTROL', - 'REG_A6XX_RB_STENCIL_INFO', 'REG_A6XX_RB_UNKNOWN_8811', - 'REG_A6XX_RB_UNKNOWN_8818', 'REG_A6XX_RB_UNKNOWN_8819', - 'REG_A6XX_RB_UNKNOWN_881A', 'REG_A6XX_RB_UNKNOWN_881B', - 'REG_A6XX_RB_UNKNOWN_881C', 'REG_A6XX_RB_UNKNOWN_881D', - 'REG_A6XX_RB_UNKNOWN_881E', 'REG_A6XX_RB_UNKNOWN_88D0', - 'REG_A6XX_RB_UNKNOWN_88F0', 'REG_A6XX_RB_UNKNOWN_88F4', - 'REG_A6XX_RB_UNKNOWN_8A00', 'REG_A6XX_RB_UNKNOWN_8A10', - 'REG_A6XX_RB_UNKNOWN_8A20', 'REG_A6XX_RB_UNKNOWN_8A30', - 'REG_A6XX_RB_UNKNOWN_8E01', 'REG_A6XX_RB_UNKNOWN_8E51', - 'REG_A6XX_RB_UNK_FLAG_BUFFER_BASE', - 'REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH', 'REG_A6XX_RB_WINDOW_OFFSET', - 'REG_A6XX_RB_WINDOW_OFFSET2', 'REG_A6XX_RB_Z_BOUNDS_MAX', - 'REG_A6XX_RB_Z_BOUNDS_MIN', 'REG_A6XX_RB_Z_CLAMP_MAX', - 'REG_A6XX_RB_Z_CLAMP_MIN', 'REG_A6XX_SP_2D_DST_FORMAT', - 'REG_A6XX_SP_ADDR_MODE_CNTL', 'REG_A6XX_SP_BLEND_CNTL', - 'REG_A6XX_SP_CHICKEN_BITS', - 'REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE', - 'REG_A6XX_SP_CS_BRANCH_COND', 'REG_A6XX_SP_CS_CNTL_0', - 'REG_A6XX_SP_CS_CNTL_1', 'REG_A6XX_SP_CS_CONFIG', - 'REG_A6XX_SP_CS_CTRL_REG0', 'REG_A6XX_SP_CS_IBO', - 'REG_A6XX_SP_CS_IBO_COUNT', 'REG_A6XX_SP_CS_INSTRLEN', - 'REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_CS_OBJ_START', 'REG_A6XX_SP_CS_PVT_MEM_ADDR', - 'REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_CS_PVT_MEM_PARAM', 'REG_A6XX_SP_CS_PVT_MEM_SIZE', - 'REG_A6XX_SP_CS_TEX_CONST', 'REG_A6XX_SP_CS_TEX_COUNT', - 'REG_A6XX_SP_CS_TEX_SAMP', 'REG_A6XX_SP_CS_UNKNOWN_A9B1', - 'REG_A6XX_SP_DBG_ECO_CNTL', 'REG_A6XX_SP_DS_BRANCH_COND', - 'REG_A6XX_SP_DS_CONFIG', 'REG_A6XX_SP_DS_CTRL_REG0', - 'REG_A6XX_SP_DS_INSTRLEN', 'REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_DS_OBJ_START', 'REG_A6XX_SP_DS_PRIMITIVE_CNTL', - 'REG_A6XX_SP_DS_PVT_MEM_ADDR', - 'REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_DS_PVT_MEM_PARAM', 'REG_A6XX_SP_DS_PVT_MEM_SIZE', - 'REG_A6XX_SP_DS_TEX_CONST', 'REG_A6XX_SP_DS_TEX_COUNT', - 'REG_A6XX_SP_DS_TEX_SAMP', 'REG_A6XX_SP_FLOAT_CNTL', - 'REG_A6XX_SP_FS_BRANCH_COND', 'REG_A6XX_SP_FS_CONFIG', - 'REG_A6XX_SP_FS_CTRL_REG0', 'REG_A6XX_SP_FS_INSTRLEN', - 'REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_FS_OBJ_START', 'REG_A6XX_SP_FS_OUTPUT_CNTL0', - 'REG_A6XX_SP_FS_OUTPUT_CNTL1', 'REG_A6XX_SP_FS_PREFETCH_CNTL', - 'REG_A6XX_SP_FS_PVT_MEM_ADDR', - 'REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_FS_PVT_MEM_PARAM', 'REG_A6XX_SP_FS_PVT_MEM_SIZE', - 'REG_A6XX_SP_FS_RENDER_COMPONENTS', 'REG_A6XX_SP_FS_TEX_CONST', - 'REG_A6XX_SP_FS_TEX_COUNT', 'REG_A6XX_SP_FS_TEX_SAMP', - 'REG_A6XX_SP_GS_BRANCH_COND', 'REG_A6XX_SP_GS_CONFIG', - 'REG_A6XX_SP_GS_CTRL_REG0', 'REG_A6XX_SP_GS_INSTRLEN', - 'REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_GS_OBJ_START', 'REG_A6XX_SP_GS_PRIMITIVE_CNTL', - 'REG_A6XX_SP_GS_PRIM_SIZE', 'REG_A6XX_SP_GS_PVT_MEM_ADDR', - 'REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_GS_PVT_MEM_PARAM', 'REG_A6XX_SP_GS_PVT_MEM_SIZE', - 'REG_A6XX_SP_GS_TEX_CONST', 'REG_A6XX_SP_GS_TEX_COUNT', - 'REG_A6XX_SP_GS_TEX_SAMP', 'REG_A6XX_SP_HS_BRANCH_COND', - 'REG_A6XX_SP_HS_CONFIG', 'REG_A6XX_SP_HS_CTRL_REG0', - 'REG_A6XX_SP_HS_INSTRLEN', 'REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_HS_OBJ_START', 'REG_A6XX_SP_HS_PVT_MEM_ADDR', - 'REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_HS_PVT_MEM_PARAM', 'REG_A6XX_SP_HS_PVT_MEM_SIZE', - 'REG_A6XX_SP_HS_TEX_CONST', 'REG_A6XX_SP_HS_TEX_COUNT', - 'REG_A6XX_SP_HS_TEX_SAMP', 'REG_A6XX_SP_HS_WAVE_INPUT_SIZE', - 'REG_A6XX_SP_IBO', 'REG_A6XX_SP_IBO_COUNT', - 'REG_A6XX_SP_MODE_CONTROL', 'REG_A6XX_SP_NC_MODE_CNTL', - 'REG_A6XX_SP_PERFCTR_ENABLE', 'REG_A6XX_SP_PS_2D_SRC', - 'REG_A6XX_SP_PS_2D_SRC_FLAGS', - 'REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH', 'REG_A6XX_SP_PS_2D_SRC_INFO', - 'REG_A6XX_SP_PS_2D_SRC_PITCH', 'REG_A6XX_SP_PS_2D_SRC_PLANE1', - 'REG_A6XX_SP_PS_2D_SRC_PLANE2', - 'REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH', 'REG_A6XX_SP_PS_2D_SRC_SIZE', - 'REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR', - 'REG_A6XX_SP_PS_UNKNOWN_B4CD', 'REG_A6XX_SP_PS_UNKNOWN_B4CE', - 'REG_A6XX_SP_PS_UNKNOWN_B4CF', 'REG_A6XX_SP_PS_UNKNOWN_B4D0', - 'REG_A6XX_SP_SRGB_CNTL', 'REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR', - 'REG_A6XX_SP_TP_DEST_MSAA_CNTL', 'REG_A6XX_SP_TP_MODE_CNTL', - 'REG_A6XX_SP_TP_RAS_MSAA_CNTL', 'REG_A6XX_SP_TP_SAMPLE_CONFIG', - 'REG_A6XX_SP_TP_SAMPLE_LOCATION_0', - 'REG_A6XX_SP_TP_SAMPLE_LOCATION_1', - 'REG_A6XX_SP_TP_WINDOW_OFFSET', 'REG_A6XX_SP_UNKNOWN_A9A8', - 'REG_A6XX_SP_UNKNOWN_AAF2', 'REG_A6XX_SP_UNKNOWN_B182', - 'REG_A6XX_SP_UNKNOWN_B183', 'REG_A6XX_SP_UNKNOWN_B190', - 'REG_A6XX_SP_UNKNOWN_B191', 'REG_A6XX_SP_VS_BRANCH_COND', - 'REG_A6XX_SP_VS_CONFIG', 'REG_A6XX_SP_VS_CTRL_REG0', - 'REG_A6XX_SP_VS_INSTRLEN', 'REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET', - 'REG_A6XX_SP_VS_OBJ_START', 'REG_A6XX_SP_VS_PRIMITIVE_CNTL', - 'REG_A6XX_SP_VS_PVT_MEM_ADDR', - 'REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET', - 'REG_A6XX_SP_VS_PVT_MEM_PARAM', 'REG_A6XX_SP_VS_PVT_MEM_SIZE', - 'REG_A6XX_SP_VS_TEX_CONST', 'REG_A6XX_SP_VS_TEX_COUNT', - 'REG_A6XX_SP_VS_TEX_SAMP', 'REG_A6XX_SP_WINDOW_OFFSET', - 'REG_A6XX_TEX_CONST_0', 'REG_A6XX_TEX_CONST_1', - 'REG_A6XX_TEX_CONST_10', 'REG_A6XX_TEX_CONST_11', - 'REG_A6XX_TEX_CONST_12', 'REG_A6XX_TEX_CONST_13', - 'REG_A6XX_TEX_CONST_14', 'REG_A6XX_TEX_CONST_15', - 'REG_A6XX_TEX_CONST_2', 'REG_A6XX_TEX_CONST_3', - 'REG_A6XX_TEX_CONST_4', 'REG_A6XX_TEX_CONST_5', - 'REG_A6XX_TEX_CONST_6', 'REG_A6XX_TEX_CONST_7', - 'REG_A6XX_TEX_CONST_8', 'REG_A6XX_TEX_CONST_9', - 'REG_A6XX_TEX_SAMP_0', 'REG_A6XX_TEX_SAMP_1', - 'REG_A6XX_TEX_SAMP_2', 'REG_A6XX_TEX_SAMP_3', - 'REG_A6XX_TPL1_ADDR_MODE_CNTL', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3', - 'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4', - 'REG_A6XX_TPL1_DBG_ECO_CNTL', 'REG_A6XX_TPL1_DBG_ECO_CNTL1', - 'REG_A6XX_TPL1_NC_MODE_CNTL', 'REG_A6XX_TPL1_UNKNOWN_B605', - 'REG_A6XX_UBO_0', 'REG_A6XX_UBO_1', - 'REG_A6XX_UCHE_ADDR_MODE_CNTL', 'REG_A6XX_UCHE_CACHE_WAYS', - 'REG_A6XX_UCHE_CLIENT_PF', 'REG_A6XX_UCHE_CMDQ_CONFIG', - 'REG_A6XX_UCHE_FILTER_CNTL', 'REG_A6XX_UCHE_GBIF_GX_CONFIG', - 'REG_A6XX_UCHE_GMEM_RANGE_MAX', 'REG_A6XX_UCHE_GMEM_RANGE_MIN', - 'REG_A6XX_UCHE_MODE_CNTL', 'REG_A6XX_UCHE_TRAP_BASE', - 'REG_A6XX_UCHE_UNKNOWN_0E12', 'REG_A6XX_UCHE_WRITE_RANGE_MAX', - 'REG_A6XX_UCHE_WRITE_THRU_BASE', 'REG_A6XX_VBIF_CLKON', - 'REG_A6XX_VBIF_GATE_OFF_WRREQ_EN', 'REG_A6XX_VBIF_PERF_CNT_HIGH0', - 'REG_A6XX_VBIF_PERF_CNT_HIGH1', 'REG_A6XX_VBIF_PERF_CNT_HIGH2', - 'REG_A6XX_VBIF_PERF_CNT_HIGH3', 'REG_A6XX_VBIF_PERF_CNT_LOW0', - 'REG_A6XX_VBIF_PERF_CNT_LOW1', 'REG_A6XX_VBIF_PERF_CNT_LOW2', - 'REG_A6XX_VBIF_PERF_CNT_LOW3', 'REG_A6XX_VBIF_PERF_CNT_SEL0', - 'REG_A6XX_VBIF_PERF_CNT_SEL1', 'REG_A6XX_VBIF_PERF_CNT_SEL2', - 'REG_A6XX_VBIF_PERF_CNT_SEL3', 'REG_A6XX_VBIF_PERF_PWR_CNT_EN0', - 'REG_A6XX_VBIF_PERF_PWR_CNT_EN1', - 'REG_A6XX_VBIF_PERF_PWR_CNT_EN2', - 'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0', - 'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1', - 'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2', - 'REG_A6XX_VBIF_PERF_PWR_CNT_LOW0', - 'REG_A6XX_VBIF_PERF_PWR_CNT_LOW1', - 'REG_A6XX_VBIF_PERF_PWR_CNT_LOW2', - 'REG_A6XX_VBIF_TEST_BUS1_CTRL0', 'REG_A6XX_VBIF_TEST_BUS1_CTRL1', - 'REG_A6XX_VBIF_TEST_BUS2_CTRL0', 'REG_A6XX_VBIF_TEST_BUS2_CTRL1', - 'REG_A6XX_VBIF_TEST_BUS_OUT', 'REG_A6XX_VBIF_TEST_BUS_OUT_CTRL', - 'REG_A6XX_VBIF_VERSION', 'REG_A6XX_VBIF_XIN_HALT_CTRL0', - 'REG_A6XX_VBIF_XIN_HALT_CTRL1', 'REG_A6XX_VFD_ADDR_MODE_CNTL', - 'REG_A6XX_VFD_ADD_OFFSET', 'REG_A6XX_VFD_CONTROL_0', - 'REG_A6XX_VFD_CONTROL_1', 'REG_A6XX_VFD_CONTROL_2', - 'REG_A6XX_VFD_CONTROL_3', 'REG_A6XX_VFD_CONTROL_4', - 'REG_A6XX_VFD_CONTROL_5', 'REG_A6XX_VFD_CONTROL_6', - 'REG_A6XX_VFD_INDEX_OFFSET', 'REG_A6XX_VFD_INSTANCE_START_OFFSET', - 'REG_A6XX_VFD_MODE_CNTL', 'REG_A6XX_VFD_MULTIVIEW_CNTL', - 'REG_A6XX_VFD_POWER_CNTL', 'REG_A6XX_VPC_ADDR_MODE_CNTL', - 'REG_A6XX_VPC_CNTL_0', 'REG_A6XX_VPC_DBG_ECO_CNTL', - 'REG_A6XX_VPC_DS_CLIP_CNTL', 'REG_A6XX_VPC_DS_CLIP_CNTL_V2', - 'REG_A6XX_VPC_DS_LAYER_CNTL', 'REG_A6XX_VPC_DS_LAYER_CNTL_V2', - 'REG_A6XX_VPC_DS_PACK', 'REG_A6XX_VPC_GS_CLIP_CNTL', - 'REG_A6XX_VPC_GS_CLIP_CNTL_V2', 'REG_A6XX_VPC_GS_LAYER_CNTL', - 'REG_A6XX_VPC_GS_LAYER_CNTL_V2', 'REG_A6XX_VPC_GS_PACK', - 'REG_A6XX_VPC_GS_PARAM', 'REG_A6XX_VPC_POINT_COORD_INVERT', - 'REG_A6XX_VPC_POLYGON_MODE', 'REG_A6XX_VPC_SO_CNTL', - 'REG_A6XX_VPC_SO_DISABLE', 'REG_A6XX_VPC_SO_PROG', - 'REG_A6XX_VPC_SO_STREAM_CNTL', 'REG_A6XX_VPC_SO_STREAM_COUNTS', - 'REG_A6XX_VPC_UNKNOWN_9107', 'REG_A6XX_VPC_UNKNOWN_9210', - 'REG_A6XX_VPC_UNKNOWN_9211', 'REG_A6XX_VPC_UNKNOWN_9300', - 'REG_A6XX_VPC_UNKNOWN_9602', 'REG_A6XX_VPC_UNKNOWN_9603', - 'REG_A6XX_VPC_VS_CLIP_CNTL', 'REG_A6XX_VPC_VS_CLIP_CNTL_V2', - 'REG_A6XX_VPC_VS_LAYER_CNTL', 'REG_A6XX_VPC_VS_LAYER_CNTL_V2', - 'REG_A6XX_VPC_VS_PACK', 'REG_A6XX_VSC_ADDR_MODE_CNTL', - 'REG_A6XX_VSC_BIN_COUNT', 'REG_A6XX_VSC_BIN_SIZE', - 'REG_A6XX_VSC_DBG_ECO_CNTL', 'REG_A6XX_VSC_DRAW_STRM_ADDRESS', - 'REG_A6XX_VSC_DRAW_STRM_LIMIT', 'REG_A6XX_VSC_DRAW_STRM_PITCH', - 'REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS', - 'REG_A6XX_VSC_PRIM_STRM_ADDRESS', 'REG_A6XX_VSC_PRIM_STRM_LIMIT', - 'REG_A6XX_VSC_PRIM_STRM_PITCH', 'REG_A7XX_CP_APERTURE_CNTL_CD', - 'REG_A7XX_CP_APERTURE_CNTL_HOST', 'REG_A7XX_CP_AQE_APRIV_CNTL', - 'REG_A7XX_CP_AQE_INSTR_BASE_0', 'REG_A7XX_CP_AQE_INSTR_BASE_1', - 'REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0', - 'REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1', - 'REG_A7XX_CP_AQE_ROQ_DBG_DATA_0', - 'REG_A7XX_CP_AQE_ROQ_DBG_DATA_1', 'REG_A7XX_CP_AQE_STAT_ADDR_0', - 'REG_A7XX_CP_AQE_STAT_ADDR_1', 'REG_A7XX_CP_AQE_STAT_DATA_0', - 'REG_A7XX_CP_AQE_STAT_DATA_1', 'REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0', - 'REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1', - 'REG_A7XX_CP_AQE_UCODE_DBG_DATA_0', - 'REG_A7XX_CP_AQE_UCODE_DBG_DATA_1', 'REG_A7XX_CP_BV_APRIV_CNTL', - 'REG_A7XX_CP_BV_CHICKEN_DBG', 'REG_A7XX_CP_BV_DRAW_STATE_ADDR', - 'REG_A7XX_CP_BV_DRAW_STATE_DATA', 'REG_A7XX_CP_BV_HW_FAULT', - 'REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR', - 'REG_A7XX_CP_BV_MEM_POOL_DBG_DATA', - 'REG_A7XX_CP_BV_PROTECT_STATUS', 'REG_A7XX_CP_BV_RB_RPTR_ADDR', - 'REG_A7XX_CP_BV_ROQ_DBG_ADDR', 'REG_A7XX_CP_BV_ROQ_DBG_DATA', - 'REG_A7XX_CP_BV_SQE_STAT_ADDR', 'REG_A7XX_CP_BV_SQE_STAT_DATA', - 'REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR', - 'REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA', - 'REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS', - 'REG_A7XX_CP_LPAC_APRIV_CNTL', 'REG_A7XX_CP_LPAC_DRAW_STATE_ADDR', - 'REG_A7XX_CP_LPAC_DRAW_STATE_DATA', - 'REG_A7XX_CP_LPAC_FIFO_DBG_ADDR', - 'REG_A7XX_CP_LPAC_FIFO_DBG_DATA', 'REG_A7XX_CP_LPAC_ROQ_DBG_ADDR', - 'REG_A7XX_CP_LPAC_ROQ_DBG_DATA', - 'REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR', - 'REG_A7XX_CP_RESOURCE_TBL_DBG_DATA', - 'REG_A7XX_CP_SQE_AC_STAT_ADDR', 'REG_A7XX_CP_SQE_AC_STAT_DATA', - 'REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR', - 'REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA', - 'REG_A7XX_CX_MISC_SW_FUSE_VALUE', 'REG_A7XX_CX_MISC_TCM_RET_CNTL', - 'REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32', 'REG_A7XX_GRAS_LRZ_CNTL2', - 'REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO', - 'REG_A7XX_GRAS_NC_MODE_CNTL', 'REG_A7XX_GRAS_SU_RENDER_CNTL', - 'REG_A7XX_GRAS_UNKNOWN_8007', 'REG_A7XX_GRAS_UNKNOWN_8008', - 'REG_A7XX_GRAS_UNKNOWN_8009', 'REG_A7XX_GRAS_UNKNOWN_800A', - 'REG_A7XX_GRAS_UNKNOWN_800B', 'REG_A7XX_GRAS_UNKNOWN_800C', - 'REG_A7XX_GRAS_UNKNOWN_80A7', 'REG_A7XX_GRAS_UNKNOWN_80F4', - 'REG_A7XX_GRAS_UNKNOWN_80F5', 'REG_A7XX_GRAS_UNKNOWN_80F6', - 'REG_A7XX_GRAS_UNKNOWN_80F8', 'REG_A7XX_GRAS_UNKNOWN_80F9', - 'REG_A7XX_GRAS_UNKNOWN_80FA', 'REG_A7XX_GRAS_UNKNOWN_8120', - 'REG_A7XX_GRAS_UNKNOWN_8121', 'REG_A7XX_HLSQ_CONTROL_1_REG', - 'REG_A7XX_HLSQ_CONTROL_2_REG', 'REG_A7XX_HLSQ_CONTROL_3_REG', - 'REG_A7XX_HLSQ_CONTROL_4_REG', 'REG_A7XX_HLSQ_CONTROL_5_REG', - 'REG_A7XX_HLSQ_CS_CNTL', 'REG_A7XX_HLSQ_CS_CNTL_1', - 'REG_A7XX_HLSQ_CS_KERNEL_GROUP_X', - 'REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y', - 'REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z', 'REG_A7XX_HLSQ_CS_LOCAL_SIZE', - 'REG_A7XX_HLSQ_CS_NDRANGE_0', 'REG_A7XX_HLSQ_CS_NDRANGE_1', - 'REG_A7XX_HLSQ_CS_NDRANGE_2', 'REG_A7XX_HLSQ_CS_NDRANGE_3', - 'REG_A7XX_HLSQ_CS_NDRANGE_4', 'REG_A7XX_HLSQ_CS_NDRANGE_5', - 'REG_A7XX_HLSQ_CS_NDRANGE_6', 'REG_A7XX_HLSQ_DISPATCH_CMD', - 'REG_A7XX_HLSQ_DRAW_CMD', 'REG_A7XX_HLSQ_DS_CNTL', - 'REG_A7XX_HLSQ_EVENT_CMD', 'REG_A7XX_HLSQ_FS_CNTL', - 'REG_A7XX_HLSQ_FS_CNTL_0', 'REG_A7XX_HLSQ_FS_UNKNOWN_A9AA', - 'REG_A7XX_HLSQ_GS_CNTL', 'REG_A7XX_HLSQ_HS_CNTL', - 'REG_A7XX_HLSQ_INVALIDATE_CMD', 'REG_A7XX_HLSQ_UNKNOWN_A9AC', - 'REG_A7XX_HLSQ_UNKNOWN_A9AD', 'REG_A7XX_HLSQ_UNKNOWN_A9AE', - 'REG_A7XX_HLSQ_VS_CNTL', 'REG_A7XX_PC_ATTR_BUF_SIZE_GMEM', - 'REG_A7XX_PC_POLYGON_MODE', 'REG_A7XX_PC_RASTER_CNTL', - 'REG_A7XX_PC_RASTER_CNTL_V2', 'REG_A7XX_PC_TESSFACTOR_ADDR', - 'REG_A7XX_PC_TESS_FACTOR_SIZE', 'REG_A7XX_PC_TESS_PARAM_SIZE', - 'REG_A7XX_PC_UNKNOWN_9E24', 'REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD', - 'REG_A7XX_RBBM_CGC_P2S_STATUS', 'REG_A7XX_RBBM_CGC_P2S_TRIG_CMD', - 'REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL', - 'REG_A7XX_RBBM_CLOCK_HYST2_VFD', 'REG_A7XX_RBBM_CLOCK_MODE2_GRAS', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_GPC', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ', - 'REG_A7XX_RBBM_CLOCK_MODE_BV_VFD', 'REG_A7XX_RBBM_CLOCK_MODE_CP', - 'REG_A7XX_RBBM_GBIF_HALT', 'REG_A7XX_RBBM_GBIF_HALT_ACK', - 'REG_A7XX_RBBM_INT_2_MASK', 'REG_A7XX_RBBM_NC_MODE_CNTL', - 'REG_A7XX_RBBM_SECVID_TSB_STATUS', - 'REG_A7XX_RBBM_SNAPSHOT_STATUS', 'REG_A7XX_RBBM_SW_FUSE_INT_MASK', - 'REG_A7XX_RBBM_SW_FUSE_INT_STATUS', 'REG_A7XX_RB_BIN_CONTROL', - 'REG_A7XX_RB_CCU_CNTL', 'REG_A7XX_RB_CCU_CNTL2', - 'REG_A7XX_RB_DEPTH_BUFFER_INFO', 'REG_A7XX_RB_RENDER_CNTL', - 'REG_A7XX_RB_STENCIL_INFO', 'REG_A7XX_RB_UNKNOWN_8812', - 'REG_A7XX_RB_UNKNOWN_8899', 'REG_A7XX_RB_UNKNOWN_88E4', - 'REG_A7XX_RB_UNKNOWN_88F5', 'REG_A7XX_RB_UNKNOWN_8C34', - 'REG_A7XX_RB_UNKNOWN_8E06', 'REG_A7XX_RB_UNKNOWN_8E09', - 'REG_A7XX_RB_UNKNOWN_8E79', 'REG_A7XX_SP_2D_DST_FORMAT', - 'REG_A7XX_SP_AHB_READ_APERTURE', 'REG_A7XX_SP_CS_CNTL_1', - 'REG_A7XX_SP_CS_UNKNOWN_A9BE', 'REG_A7XX_SP_CS_VGPR_CONFIG', - 'REG_A7XX_SP_DBG_CNTL', 'REG_A7XX_SP_DS_VGPR_CONFIG', - 'REG_A7XX_SP_FS_VGPR_CONFIG', 'REG_A7XX_SP_GS_VGPR_CONFIG', - 'REG_A7XX_SP_HS_VGPR_CONFIG', 'REG_A7XX_SP_PS_2D_SRC', - 'REG_A7XX_SP_PS_2D_SRC_FLAGS', - 'REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH', 'REG_A7XX_SP_PS_2D_SRC_INFO', - 'REG_A7XX_SP_PS_2D_SRC_PITCH', 'REG_A7XX_SP_PS_2D_SRC_PLANE1', - 'REG_A7XX_SP_PS_2D_SRC_PLANE2', - 'REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH', 'REG_A7XX_SP_PS_2D_SRC_SIZE', - 'REG_A7XX_SP_PS_2D_WINDOW_OFFSET', - 'REG_A7XX_SP_PS_ALIASED_COMPONENTS', - 'REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL', - 'REG_A7XX_SP_PS_UNKNOWN_B2D2', 'REG_A7XX_SP_PS_UNKNOWN_B4CD', - 'REG_A7XX_SP_PS_UNKNOWN_B4CE', 'REG_A7XX_SP_PS_UNKNOWN_B4CF', - 'REG_A7XX_SP_PS_UNKNOWN_B4D0', 'REG_A7XX_SP_READ_SEL', - 'REG_A7XX_SP_UNKNOWN_0CE2', 'REG_A7XX_SP_UNKNOWN_0CE4', - 'REG_A7XX_SP_UNKNOWN_0CE6', 'REG_A7XX_SP_UNKNOWN_AB01', - 'REG_A7XX_SP_UNKNOWN_AB02', 'REG_A7XX_SP_UNKNOWN_AB22', - 'REG_A7XX_SP_UNKNOWN_AE06', 'REG_A7XX_SP_UNKNOWN_AE08', - 'REG_A7XX_SP_UNKNOWN_AE09', 'REG_A7XX_SP_UNKNOWN_AE0A', - 'REG_A7XX_SP_UNKNOWN_AE6A', 'REG_A7XX_SP_UNKNOWN_AE6B', - 'REG_A7XX_SP_UNKNOWN_AE6C', 'REG_A7XX_SP_UNKNOWN_AE73', - 'REG_A7XX_SP_UNKNOWN_B310', 'REG_A7XX_SP_VS_VGPR_CONFIG', - 'REG_A7XX_SP_WINDOW_OFFSET', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3', - 'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4', - 'REG_A7XX_UCHE_UNKNOWN_0E10', 'REG_A7XX_UCHE_UNKNOWN_0E11', - 'REG_A7XX_VFD_UNKNOWN_A600', 'REG_A7XX_VPC_ATTR_BUF_BASE_GMEM', - 'REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM', 'REG_A7XX_VPC_MULTIVIEW_CNTL', - 'REG_A7XX_VPC_MULTIVIEW_MASK', 'REG_A7XX_VPC_POLYGON_MODE2', - 'REG_A7XX_VPC_PRIMITIVE_CNTL_0', 'REG_A7XX_VPC_PRIMITIVE_CNTL_5', - 'REG_A7XX_VSC_UNKNOWN_0CD8', 'REG_A7XX_VSC_UNKNOWN_0D08', - 'REG_AXXX_CP_BIN_MASK_HI', 'REG_AXXX_CP_BIN_MASK_LO', - 'REG_AXXX_CP_BIN_SELECT_HI', 'REG_AXXX_CP_BIN_SELECT_LO', - 'REG_AXXX_CP_CSQ_AVAIL', 'REG_AXXX_CP_CSQ_IB1_STAT', - 'REG_AXXX_CP_CSQ_IB2_STAT', 'REG_AXXX_CP_CSQ_RB_STAT', - 'REG_AXXX_CP_DEBUG', 'REG_AXXX_CP_IB1_BASE', - 'REG_AXXX_CP_IB1_BUFSZ', 'REG_AXXX_CP_IB2_BASE', - 'REG_AXXX_CP_IB2_BUFSZ', 'REG_AXXX_CP_INT_ACK', - 'REG_AXXX_CP_INT_CNTL', 'REG_AXXX_CP_INT_STATUS', - 'REG_AXXX_CP_MEQ_AVAIL', 'REG_AXXX_CP_MEQ_STAT', - 'REG_AXXX_CP_MEQ_THRESHOLDS', 'REG_AXXX_CP_ME_CF_EVENT_ADDR', - 'REG_AXXX_CP_ME_CF_EVENT_DATA', 'REG_AXXX_CP_ME_CF_EVENT_SRC', - 'REG_AXXX_CP_ME_CNTL', 'REG_AXXX_CP_ME_NRT_ADDR', - 'REG_AXXX_CP_ME_NRT_DATA', 'REG_AXXX_CP_ME_PS_EVENT_ADDR', - 'REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM', - 'REG_AXXX_CP_ME_PS_EVENT_DATA', - 'REG_AXXX_CP_ME_PS_EVENT_DATA_SWM', 'REG_AXXX_CP_ME_PS_EVENT_SRC', - 'REG_AXXX_CP_ME_RAM_DATA', 'REG_AXXX_CP_ME_RAM_RADDR', - 'REG_AXXX_CP_ME_RAM_WADDR', 'REG_AXXX_CP_ME_RDADDR', - 'REG_AXXX_CP_ME_STATUS', 'REG_AXXX_CP_ME_VS_EVENT_ADDR', - 'REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM', - 'REG_AXXX_CP_ME_VS_EVENT_DATA', - 'REG_AXXX_CP_ME_VS_EVENT_DATA_SWM', 'REG_AXXX_CP_ME_VS_EVENT_SRC', - 'REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR', - 'REG_AXXX_CP_ME_VS_FETCH_DONE_DATA', - 'REG_AXXX_CP_ME_VS_FETCH_DONE_SRC', 'REG_AXXX_CP_MIU_TAG_STAT', - 'REG_AXXX_CP_NON_PREFETCH_CNTRS', 'REG_AXXX_CP_QUEUE_THRESHOLDS', - 'REG_AXXX_CP_RB_BASE', 'REG_AXXX_CP_RB_CNTL', - 'REG_AXXX_CP_RB_RPTR', 'REG_AXXX_CP_RB_RPTR_ADDR', - 'REG_AXXX_CP_RB_RPTR_WR', 'REG_AXXX_CP_RB_WPTR', - 'REG_AXXX_CP_RB_WPTR_BASE', 'REG_AXXX_CP_RB_WPTR_DELAY', - 'REG_AXXX_CP_SCRATCH_REG0', 'REG_AXXX_CP_SCRATCH_REG1', - 'REG_AXXX_CP_SCRATCH_REG2', 'REG_AXXX_CP_SCRATCH_REG3', - 'REG_AXXX_CP_SCRATCH_REG4', 'REG_AXXX_CP_SCRATCH_REG5', - 'REG_AXXX_CP_SCRATCH_REG6', 'REG_AXXX_CP_SCRATCH_REG7', - 'REG_AXXX_CP_STAT', 'REG_AXXX_CP_STATE_DEBUG_DATA', - 'REG_AXXX_CP_STATE_DEBUG_INDEX', 'REG_AXXX_CP_STQ_AVAIL', - 'REG_AXXX_CP_STQ_ST_STAT', 'REG_AXXX_CP_ST_BASE', - 'REG_AXXX_CP_ST_BUFSZ', 'REG_AXXX_SCRATCH_ADDR', - 'REG_AXXX_SCRATCH_UMSK', 'REG_COMPARE', - 'REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM', - 'REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK', - 'REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT', 'REG_COMPARE_IMM', - 'REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK', - 'REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT', 'REG_CP_BLIT_0', - 'REG_CP_BLIT_1', 'REG_CP_BLIT_2', 'REG_CP_BLIT_3', - 'REG_CP_BLIT_4', 'REG_CP_BV_BR_COUNT_OPS_0', - 'REG_CP_BV_BR_COUNT_OPS_1', 'REG_CP_COMPUTE_CHECKPOINT_0', - 'REG_CP_COMPUTE_CHECKPOINT_1', 'REG_CP_COMPUTE_CHECKPOINT_2', - 'REG_CP_COMPUTE_CHECKPOINT_3', 'REG_CP_COMPUTE_CHECKPOINT_4', - 'REG_CP_COMPUTE_CHECKPOINT_5', 'REG_CP_COMPUTE_CHECKPOINT_6', - 'REG_CP_COMPUTE_CHECKPOINT_7', 'REG_CP_COND_EXEC_0', - 'REG_CP_COND_EXEC_1', 'REG_CP_COND_EXEC_2', 'REG_CP_COND_EXEC_3', - 'REG_CP_COND_EXEC_4', 'REG_CP_COND_EXEC_5', - 'REG_CP_COND_REG_EXEC_0', 'REG_CP_COND_REG_EXEC_2', - 'REG_CP_COND_WRITE5_0', 'REG_CP_COND_WRITE5_1', - 'REG_CP_COND_WRITE5_2', 'REG_CP_COND_WRITE5_3', - 'REG_CP_COND_WRITE5_4', 'REG_CP_COND_WRITE5_5', - 'REG_CP_COND_WRITE5_6', 'REG_CP_COND_WRITE5_7', - 'REG_CP_COND_WRITE_0', 'REG_CP_COND_WRITE_1', - 'REG_CP_COND_WRITE_2', 'REG_CP_COND_WRITE_3', - 'REG_CP_COND_WRITE_4', 'REG_CP_COND_WRITE_5', - 'REG_CP_DISPATCH_COMPUTE_0', 'REG_CP_DISPATCH_COMPUTE_1', - 'REG_CP_DISPATCH_COMPUTE_2', 'REG_CP_DISPATCH_COMPUTE_3', - 'REG_CP_DRAW_AUTO_0', 'REG_CP_DRAW_AUTO_1', 'REG_CP_DRAW_AUTO_4', - 'REG_CP_DRAW_AUTO_5', 'REG_CP_DRAW_AUTO_NUM_VERTICES_BASE', - 'REG_CP_DRAW_INDX_0', 'REG_CP_DRAW_INDX_1', 'REG_CP_DRAW_INDX_2', - 'REG_CP_DRAW_INDX_2_0', 'REG_CP_DRAW_INDX_2_1', - 'REG_CP_DRAW_INDX_2_2', 'REG_CP_DRAW_INDX_3', - 'REG_CP_DRAW_INDX_4', 'REG_CP_DRAW_INDX_OFFSET_0', - 'REG_CP_DRAW_INDX_OFFSET_1', 'REG_CP_DRAW_INDX_OFFSET_2', - 'REG_CP_DRAW_INDX_OFFSET_3', 'REG_CP_DRAW_INDX_OFFSET_4', - 'REG_CP_DRAW_INDX_OFFSET_5', 'REG_CP_DRAW_PRED_ENABLE_GLOBAL_0', - 'REG_CP_DRAW_PRED_ENABLE_LOCAL_0', 'REG_CP_DRAW_PRED_SET_0', - 'REG_CP_DRAW_PRED_SET_MEM_ADDR', 'REG_CP_EVENT_WRITE7_0', - 'REG_CP_EVENT_WRITE_0', 'REG_CP_EVENT_WRITE_1', - 'REG_CP_EVENT_WRITE_2', 'REG_CP_EVENT_WRITE_3', - 'REG_CP_EXEC_CS_0', 'REG_CP_EXEC_CS_1', 'REG_CP_EXEC_CS_2', - 'REG_CP_EXEC_CS_3', 'REG_CP_FIXED_STRIDE_DRAW_TABLE_2', - 'REG_CP_FIXED_STRIDE_DRAW_TABLE_3', - 'REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE', 'REG_CP_LOAD_STATE4_0', - 'REG_CP_LOAD_STATE4_1', 'REG_CP_LOAD_STATE4_2', - 'REG_CP_LOAD_STATE6_0', 'REG_CP_LOAD_STATE6_1', - 'REG_CP_LOAD_STATE6_2', 'REG_CP_LOAD_STATE6_EXT_SRC_ADDR', - 'REG_CP_LOAD_STATE_0', 'REG_CP_LOAD_STATE_1', 'REG_CP_MEMCPY_0', - 'REG_CP_MEMCPY_1', 'REG_CP_MEMCPY_2', 'REG_CP_MEMCPY_3', - 'REG_CP_MEMCPY_4', 'REG_CP_MEM_TO_MEM_0', 'REG_CP_MEM_TO_REG_0', - 'REG_CP_MEM_TO_REG_1', 'REG_CP_MEM_TO_REG_2', - 'REG_CP_MEM_TO_SCRATCH_MEM_0', 'REG_CP_MEM_TO_SCRATCH_MEM_1', - 'REG_CP_MEM_TO_SCRATCH_MEM_2', 'REG_CP_MEM_TO_SCRATCH_MEM_3', - 'REG_CP_MEM_WRITE_0', 'REG_CP_MEM_WRITE_1', - 'REG_CP_MODIFY_TIMESTAMP_0', 'REG_CP_PERFCOUNTER_ACTION_0', - 'REG_CP_PERFCOUNTER_ACTION_1', 'REG_CP_PERFCOUNTER_ACTION_2', - 'REG_CP_REG_RMW_0', 'REG_CP_REG_RMW_1', 'REG_CP_REG_RMW_2', - 'REG_CP_REG_TO_MEM_0', 'REG_CP_REG_TO_MEM_1', - 'REG_CP_REG_TO_MEM_2', 'REG_CP_REG_TO_MEM_OFFSET_MEM_0', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_1', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_2', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_3', - 'REG_CP_REG_TO_MEM_OFFSET_MEM_4', - 'REG_CP_REG_TO_MEM_OFFSET_REG_0', - 'REG_CP_REG_TO_MEM_OFFSET_REG_1', - 'REG_CP_REG_TO_MEM_OFFSET_REG_2', - 'REG_CP_REG_TO_MEM_OFFSET_REG_3', 'REG_CP_REG_TO_SCRATCH_0', - 'REG_CP_REG_WRITE_0', 'REG_CP_REG_WRITE_1', 'REG_CP_REG_WRITE_2', - 'REG_CP_RESET_CONTEXT_STATE_0', 'REG_CP_SCRATCH_TO_REG_0', - 'REG_CP_SCRATCH_WRITE_0', 'REG_CP_SET_BIN_0', 'REG_CP_SET_BIN_1', - 'REG_CP_SET_BIN_2', 'REG_CP_SET_BIN_DATA5_0', - 'REG_CP_SET_BIN_DATA5_1', 'REG_CP_SET_BIN_DATA5_2', - 'REG_CP_SET_BIN_DATA5_3', 'REG_CP_SET_BIN_DATA5_4', - 'REG_CP_SET_BIN_DATA5_5', 'REG_CP_SET_BIN_DATA5_6', - 'REG_CP_SET_BIN_DATA5_7', 'REG_CP_SET_BIN_DATA5_9', - 'REG_CP_SET_BIN_DATA5_OFFSET_0', 'REG_CP_SET_BIN_DATA5_OFFSET_1', - 'REG_CP_SET_BIN_DATA5_OFFSET_2', 'REG_CP_SET_BIN_DATA5_OFFSET_3', - 'REG_CP_SET_BIN_DATA_0', 'REG_CP_SET_BIN_DATA_1', - 'REG_CP_SET_CTXSWITCH_IB_0', 'REG_CP_SET_CTXSWITCH_IB_1', - 'REG_CP_SET_CTXSWITCH_IB_2', 'REG_CP_SET_RENDER_MODE_0', - 'REG_CP_SET_RENDER_MODE_1', 'REG_CP_SET_RENDER_MODE_2', - 'REG_CP_SET_RENDER_MODE_3', 'REG_CP_SET_RENDER_MODE_4', - 'REG_CP_SET_RENDER_MODE_5', 'REG_CP_SET_RENDER_MODE_6', - 'REG_CP_SET_RENDER_MODE_7', 'REG_CP_SMMU_TABLE_UPDATE_0', - 'REG_CP_SMMU_TABLE_UPDATE_1', 'REG_CP_SMMU_TABLE_UPDATE_2', - 'REG_CP_SMMU_TABLE_UPDATE_3', 'REG_CP_START_BIN_BIN_COUNT', - 'REG_CP_START_BIN_BODY_DWORDS', 'REG_CP_START_BIN_PREFIX_ADDR', - 'REG_CP_START_BIN_PREFIX_DWORDS', 'REG_CP_THREAD_CONTROL_0', - 'REG_CP_WAIT_MEM_GTE_0', 'REG_CP_WAIT_MEM_GTE_1', - 'REG_CP_WAIT_MEM_GTE_2', 'REG_CP_WAIT_MEM_GTE_3', - 'REG_CP_WAIT_REG_MEM_0', 'REG_CP_WAIT_REG_MEM_1', - 'REG_CP_WAIT_REG_MEM_2', 'REG_CP_WAIT_REG_MEM_3', - 'REG_CP_WAIT_REG_MEM_4', 'REG_CP_WAIT_REG_MEM_5', - 'REG_CP_WAIT_TIMESTAMP_0', 'REG_CP_WAIT_TIMESTAMP_SRC_0', - 'REG_CP_WAIT_TIMESTAMP_SRC_1', 'REG_CP_WAIT_TWO_REGS_0', - 'REG_CP_WAIT_TWO_REGS_1', 'REG_CP_WAIT_TWO_REGS_2', - 'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1', - 'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3', - 'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_1', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_2', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_3', - 'REG_EV_DST_RAM_CP_EVENT_WRITE7_4', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES', - 'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES', - 'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT', - 'REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE', - 'REG_PRED_TEST_CP_COND_REG_EXEC_1', - 'REG_REG_COMPARE_CP_COND_REG_EXEC_1', - 'REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1', - 'REG_RENDER_MODE_CP_COND_REG_EXEC_1', - 'REG_THREAD_MODE_CP_COND_REG_EXEC_1', - 'REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0', - 'REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR', 'RENDERING_PASS', - 'RENDER_MODE', 'RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK', - 'RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'RESTORE_IB', - 'RL_TB', 'RM6_BINNING', 'RM6_BLIT2DSCALE', 'RM6_BYPASS', - 'RM6_COMPUTE', 'RM6_ENDVIS', 'RM6_GMEM', 'RM6_IB1LIST_END', - 'RM6_IB1LIST_START', 'RM6_IFPC_DISABLE', 'RM6_IFPC_ENABLE', - 'RM6_RESOLVE', 'RM6_YIELD', 'ROP_AND', 'ROP_AND_INVERTED', - 'ROP_AND_REVERSE', 'ROP_CLEAR', 'ROP_COPY', 'ROP_COPY_INVERTED', - 'ROP_EQUIV', 'ROP_INVERT', 'ROP_NAND', 'ROP_NOOP', 'ROP_NOR', - 'ROP_OR', 'ROP_OR_INVERTED', 'ROP_OR_REVERSE', 'ROP_SET', - 'ROP_XOR', 'ROTATE_0', 'ROTATE_180', 'ROTATE_270', 'ROTATE_90', - 'ROTATE_HFLIP', 'ROTATE_VFLIP', 'RST_PIX_CNT', 'RST_VTX_CNT', - 'SAVE_IB', 'SB4_CS_SHADER', 'SB4_CS_SSBO', 'SB4_CS_TEX', - 'SB4_DS_SHADER', 'SB4_DS_TEX', 'SB4_FS_SHADER', 'SB4_FS_TEX', - 'SB4_GS_SHADER', 'SB4_GS_TEX', 'SB4_HS_SHADER', 'SB4_HS_TEX', - 'SB4_SSBO', 'SB4_VS_SHADER', 'SB4_VS_TEX', 'SB6_CS_IBO', - 'SB6_CS_SHADER', 'SB6_CS_TEX', 'SB6_DS_SHADER', 'SB6_DS_TEX', - 'SB6_FS_SHADER', 'SB6_FS_TEX', 'SB6_GS_SHADER', 'SB6_GS_TEX', - 'SB6_HS_SHADER', 'SB6_HS_TEX', 'SB6_IBO', 'SB6_VS_SHADER', - 'SB6_VS_TEX', 'SB_COMPUTE_SHADER', 'SB_FRAG_MIPADDR', - 'SB_FRAG_SHADER', 'SB_FRAG_TEX', 'SB_GEOM_SHADER', - 'SB_VERT_MIPADDR', 'SB_VERT_SHADER', 'SB_VERT_TEX', 'SC_WAIT_WC', - 'SECURE_SAVE_ADDR', 'SINGLE', 'SMMU_INFO', 'SOURCE_REG', - 'SOURCE_SCRATCH_MEM', 'SS4_DIRECT', 'SS4_INDIRECT', - 'SS6_BINDLESS', 'SS6_DIRECT', 'SS6_INDIRECT', 'SS6_UBO', - 'SS_DIRECT', 'SS_INDIRECT', 'SS_INDIRECT_STM', 'SS_INDIRECT_TCM', - 'SS_INVALID_ALL_IC', 'SS_INVALID_PART_IC', 'ST4_CONSTANTS', - 'ST4_SHADER', 'ST4_UBO', 'ST6_CONSTANTS', 'ST6_IBO', 'ST6_SHADER', - 'ST6_UBO', 'START_COMPUTE_CTRS', 'START_FRAGMENT_CTRS', - 'START_PRIMITIVE_CTRS', 'STAT_EVENT', 'STENCIL_DECR_CLAMP', - 'STENCIL_DECR_WRAP', 'STENCIL_INCR_CLAMP', 'STENCIL_INCR_WRAP', - 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_REPLACE', - 'STENCIL_ZERO', 'STOP_COMPUTE_CTRS', 'STOP_FRAGMENT_CTRS', - 'STOP_PRIMITIVE_CTRS', 'ST_CONSTANTS', 'ST_SHADER', - 'TESS_CCW_TRIS', 'TESS_CW_TRIS', 'TESS_EQUAL', - 'TESS_FRACTIONAL_EVEN', 'TESS_FRACTIONAL_ODD', 'TESS_ISOLINES', - 'TESS_LINES', 'TESS_POINTS', 'TESS_QUADS', 'TESS_TRIANGLES', - 'TEX_PREFETCH_GATHER4A', 'TEX_PREFETCH_GATHER4B', - 'TEX_PREFETCH_GATHER4G', 'TEX_PREFETCH_GATHER4R', - 'TEX_PREFETCH_SAM', 'TEX_PREFETCH_UNK0', 'TEX_PREFETCH_UNK6', - 'TEX_PREFETCH_UNK7', 'THREAD128', 'THREAD64', 'THREAD_MODE', - 'THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK', - 'THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'TILE6_2', - 'TILE6_3', 'TILE6_LINEAR', 'TILE_FLUSH', 'TRACK_CNTL_REG', - 'TRACK_LRZ', 'TRACK_RENDER_CNTL', 'TS_WAIT_GE_32B', - 'TS_WAIT_GE_64B', 'TS_WAIT_GE_TIMESTAMP_SUM', 'TS_WAIT_ONCHIP', - 'TS_WAIT_RAM', 'TWO_QUADS', 'TYPE_TILED', 'TYPE_WRITER', 'UNK_2C', - 'UNK_2D', 'UNK_40', 'UNK_EVENT_WRITE', 'UNK_STRM_ADDRESS', - 'UNK_STRM_SIZE_ADDRESS', 'USE_VISIBILITY', 'VIZQUERY_END', - 'VIZQUERY_START', 'VS_DEALLOC', 'VS_DONE_TS', 'VS_FETCH_DONE', - 'WRITE_ALWAYS', 'WRITE_EQ', 'WRITE_GE', 'WRITE_GT', 'WRITE_LE', - 'WRITE_LT', 'WRITE_NE', 'WRITE_PRIMITIVE_COUNTS', 'WT_DONE_TS', - 'WXYZ', 'WZYX', 'XYZW', 'YIELD_RESTORE_IB', 'ZPASS_DONE', 'ZYXW', - 'a3xx_color_swap', 'a3xx_instrbuffermode', 'a3xx_msaa_samples', - 'a3xx_rb_blend_opcode', 'a3xx_render_mode', 'a3xx_rop_code', - 'a3xx_threadmode', 'a3xx_threadsize', 'a4xx_index_size', - 'a4xx_state_block', 'a4xx_state_src', 'a4xx_state_type', - 'a4xx_tess_spacing', 'a5xx_address_mode', 'a5xx_line_mode', - 'a6xx_2d_ifmt', 'a6xx_bindless_descriptor_size', - 'a6xx_buffers_location', 'a6xx_ccu_cache_size', - 'a6xx_ccu_perfcounter_select', 'a6xx_cmp_perfcounter_select', - 'a6xx_cp_perfcounter_select', 'a6xx_debugbus_id', - 'a6xx_depth_format', 'a6xx_draw_indirect_opcode', 'a6xx_format', - 'a6xx_fragcoord_sample_mode', 'a6xx_hlsq_perfcounter_select', - 'a6xx_isam_mode', 'a6xx_lrz_dir_status', - 'a6xx_lrz_perfcounter_select', 'a6xx_marker', 'a6xx_patch_type', - 'a6xx_pc_perfcounter_select', 'a6xx_polygon_mode', - 'a6xx_ras_perfcounter_select', 'a6xx_raster_direction', - 'a6xx_raster_mode', 'a6xx_rb_perfcounter_select', - 'a6xx_rbbm_perfcounter_select', 'a6xx_reduction_mode', - 'a6xx_render_mode', 'a6xx_rotation', 'a6xx_sequenced_thread_dist', - 'a6xx_shader_id', 'a6xx_single_prim_mode', - 'a6xx_sp_perfcounter_select', 'a6xx_state_block', - 'a6xx_state_src', 'a6xx_state_type', 'a6xx_tess_output', - 'a6xx_tess_spacing', 'a6xx_tex_aniso', 'a6xx_tex_clamp', - 'a6xx_tex_filter', 'a6xx_tex_prefetch_cmd', 'a6xx_tex_swiz', - 'a6xx_tex_type', 'a6xx_threadsize', 'a6xx_tile_mode', - 'a6xx_tp_perfcounter_select', 'a6xx_tse_perfcounter_select', - 'a6xx_uche_perfcounter_select', 'a6xx_varying_interp_mode', - 'a6xx_varying_ps_repl_mode', 'a6xx_vfd_perfcounter_select', - 'a6xx_vpc_perfcounter_select', 'a6xx_vsc_perfcounter_select', - 'a6xx_ztest_mode', 'a7xx_ccu_perfcounter_select', 'a7xx_cluster', - 'a7xx_cmp_perfcounter_select', 'a7xx_cp_perfcounter_select', - 'a7xx_cs_yalign', 'a7xx_debugbus_id', - 'a7xx_gbif_perfcounter_select', 'a7xx_hlsq_perfcounter_select', - 'a7xx_lrz_perfcounter_select', 'a7xx_pc_perfcounter_select', - 'a7xx_pipe', 'a7xx_ras_perfcounter_select', - 'a7xx_rb_perfcounter_select', 'a7xx_rbbm_perfcounter_select', - 'a7xx_sp_perfcounter_select', 'a7xx_state_location', - 'a7xx_statetype_id', 'a7xx_tp_perfcounter_select', - 'a7xx_tse_perfcounter_select', 'a7xx_uche_perfcounter_select', - 'a7xx_ufc_perfcounter_select', 'a7xx_vfd_perfcounter_select', - 'a7xx_vpc_perfcounter_select', 'a7xx_vsc_perfcounter_select', - 'adreno_compare_func', 'adreno_pa_su_sc_draw', - 'adreno_pm4_packet_type', 'adreno_pm4_type3_packets', - 'adreno_rb_blend_factor', 'adreno_rb_copy_control_mode', - 'adreno_rb_depth_format', 'adreno_rb_dither_mode', - 'adreno_rb_surface_endian', 'adreno_state_block', - 'adreno_state_src', 'adreno_state_type', 'adreno_stencil_op', - 'chip', 'compare_mode', 'cp_blit_cmd', 'cp_cond_function', - 'cp_draw_pred_src', 'cp_draw_pred_test', 'cp_thread', - 'ctxswitch_ib', 'event_write_dst', 'event_write_src', - 'pc_di_face_cull_sel', 'pc_di_index_size', 'pc_di_primtype', - 'pc_di_src_sel', 'pc_di_vis_cull_mode', 'pipe_count_op', - 'poll_memory_type', 'pseudo_reg', 'reg_tracker', - 'render_mode_cmd', 'source_type', 'timestamp_op', 'ts_wait_type', - 'ts_wait_value_src', 'vgt_event_type'] -def CP_LOAD_STATE_0_DST_OFF(val): return (val << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK -def CP_LOAD_STATE_0_STATE_SRC(val): return (val << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK -def CP_LOAD_STATE_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK -def CP_LOAD_STATE_0_NUM_UNIT(val): return (val << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK -def CP_LOAD_STATE_1_STATE_TYPE(val): return (val << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK -def CP_LOAD_STATE_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK -def CP_LOAD_STATE4_0_DST_OFF(val): return (val << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK -def CP_LOAD_STATE4_0_STATE_SRC(val): return (val << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK -def CP_LOAD_STATE4_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK -def CP_LOAD_STATE4_0_NUM_UNIT(val): return (val << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK -def CP_LOAD_STATE4_1_STATE_TYPE(val): return (val << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK -def CP_LOAD_STATE4_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK -def CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(val): return (val << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK -def CP_LOAD_STATE6_0_DST_OFF(val): return (val << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK -def CP_LOAD_STATE6_0_STATE_TYPE(val): return (val << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK -def CP_LOAD_STATE6_0_STATE_SRC(val): return (val << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK -def CP_LOAD_STATE6_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK -def CP_LOAD_STATE6_0_NUM_UNIT(val): return (val << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK -def CP_LOAD_STATE6_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK -def CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(val): return (val << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK -def CP_DRAW_INDX_0_VIZ_QUERY(val): return (val << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK -def CP_DRAW_INDX_1_PRIM_TYPE(val): return (val << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK -def CP_DRAW_INDX_1_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK -def CP_DRAW_INDX_1_VIS_CULL(val): return (val << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK -def CP_DRAW_INDX_1_INDEX_SIZE(val): return (val << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK -def CP_DRAW_INDX_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK -def CP_DRAW_INDX_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK -def CP_DRAW_INDX_3_INDX_BASE(val): return (val << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK -def CP_DRAW_INDX_4_INDX_SIZE(val): return (val << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK -def CP_DRAW_INDX_2_0_VIZ_QUERY(val): return (val << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK -def CP_DRAW_INDX_2_1_PRIM_TYPE(val): return (val << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK -def CP_DRAW_INDX_2_1_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK -def CP_DRAW_INDX_2_1_VIS_CULL(val): return (val << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK -def CP_DRAW_INDX_2_1_INDEX_SIZE(val): return (val << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK -def CP_DRAW_INDX_2_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK -def CP_DRAW_INDX_2_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK -def CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(val): return (val << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK -def CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK -def CP_DRAW_INDX_OFFSET_0_VIS_CULL(val): return (val << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK -def CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(val): return (val << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK -def CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(val): return (val << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK -def CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK -def CP_DRAW_INDX_OFFSET_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK -def CP_DRAW_INDX_OFFSET_3_FIRST_INDX(val): return (val << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK -def A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK -def A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK -def A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK -def CP_DRAW_INDX_OFFSET_4_INDX_BASE(val): return (val << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK -def CP_DRAW_INDX_OFFSET_5_INDX_SIZE(val): return (val << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK -def A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK -def A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(val): return (val << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK -def A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(val): return (val << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK -def A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK -def A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK -def A4XX_CP_DRAW_INDIRECT_1_INDIRECT(val): return (val << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK -def A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(val): return (val << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK -def A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(val): return (val << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK -def A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK -def A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK -def A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK -def CP_DRAW_AUTO_0_PRIM_TYPE(val): return (val << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK -def CP_DRAW_AUTO_0_SOURCE_SELECT(val): return (val << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK -def CP_DRAW_AUTO_0_VIS_CULL(val): return (val << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK -def CP_DRAW_AUTO_0_INDEX_SIZE(val): return (val << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK -def CP_DRAW_AUTO_0_PATCH_TYPE(val): return (val << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK -def CP_DRAW_AUTO_1_NUM_INSTANCES(val): return (val << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK -def CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(val): return (val << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK -def CP_DRAW_AUTO_5_STRIDE(val): return (val << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK -def CP_DRAW_PRED_SET_0_SRC(val): return (val << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK -def CP_DRAW_PRED_SET_0_TEST(val): return (val << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK -def CP_SET_DRAW_STATE__0_COUNT(val): return (val << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK -def CP_SET_DRAW_STATE__0_GROUP_ID(val): return (val << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK -def CP_SET_DRAW_STATE__1_ADDR_LO(val): return (val << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK -def CP_SET_DRAW_STATE__2_ADDR_HI(val): return (val << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK -def CP_SET_BIN_1_X1(val): return (val << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK -def CP_SET_BIN_1_Y1(val): return (val << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK -def CP_SET_BIN_2_X2(val): return (val << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK -def CP_SET_BIN_2_Y2(val): return (val << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK -def CP_SET_BIN_DATA_0_BIN_DATA_ADDR(val): return (val << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK -def CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(val): return (val << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK -def CP_SET_BIN_DATA5_0_VSC_SIZE(val): return (val << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK -def CP_SET_BIN_DATA5_0_VSC_N(val): return (val << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK -def CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(val): return (val << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK -def CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(val): return (val << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK -def CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(val): return (val << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK -def CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(val): return (val << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK -def CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(val): return (val << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK -def CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(val): return (val << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK -def CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(val): return (val << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK -def CP_SET_BIN_DATA5_OFFSET_0_VSC_N(val): return (val << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK -def CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK -def CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK -def CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK -def CP_REG_RMW_0_DST_REG(val): return (val << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK -def CP_REG_RMW_0_ROTATE(val): return (val << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK -def CP_REG_RMW_1_SRC0(val): return (val << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK -def CP_REG_RMW_2_SRC1(val): return (val << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK -def CP_REG_TO_MEM_0_REG(val): return (val << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK -def CP_REG_TO_MEM_0_CNT(val): return (val << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK -def CP_REG_TO_MEM_1_DEST(val): return (val << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK -def CP_REG_TO_MEM_2_DEST_HI(val): return (val << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK -def CP_REG_TO_MEM_OFFSET_REG_0_REG(val): return (val << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK -def CP_REG_TO_MEM_OFFSET_REG_0_CNT(val): return (val << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK -def CP_REG_TO_MEM_OFFSET_REG_1_DEST(val): return (val << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK -def CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(val): return (val << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK -def CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(val): return (val << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK -def CP_REG_TO_MEM_OFFSET_MEM_0_REG(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK -def CP_REG_TO_MEM_OFFSET_MEM_0_CNT(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK -def CP_REG_TO_MEM_OFFSET_MEM_1_DEST(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK -def CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK -def CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK -def CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK -def CP_MEM_TO_REG_0_REG(val): return (val << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK -def CP_MEM_TO_REG_0_CNT(val): return (val << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK -def CP_MEM_TO_REG_1_SRC(val): return (val << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK -def CP_MEM_TO_REG_2_SRC_HI(val): return (val << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK -def CP_MEMCPY_0_DWORDS(val): return (val << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK -def CP_MEMCPY_1_SRC_LO(val): return (val << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK -def CP_MEMCPY_2_SRC_HI(val): return (val << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK -def CP_MEMCPY_3_DST_LO(val): return (val << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK -def CP_MEMCPY_4_DST_HI(val): return (val << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK -def CP_REG_TO_SCRATCH_0_REG(val): return (val << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK -def CP_REG_TO_SCRATCH_0_SCRATCH(val): return (val << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK -def CP_REG_TO_SCRATCH_0_CNT(val): return (val << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK -def CP_SCRATCH_TO_REG_0_REG(val): return (val << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK -def CP_SCRATCH_TO_REG_0_SCRATCH(val): return (val << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK -def CP_SCRATCH_TO_REG_0_CNT(val): return (val << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK -def CP_SCRATCH_WRITE_0_SCRATCH(val): return (val << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK -def CP_MEM_WRITE_0_ADDR_LO(val): return (val << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK -def CP_MEM_WRITE_1_ADDR_HI(val): return (val << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK -def CP_COND_WRITE_0_FUNCTION(val): return (val << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK -def CP_COND_WRITE_1_POLL_ADDR(val): return (val << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK -def CP_COND_WRITE_2_REF(val): return (val << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK -def CP_COND_WRITE_3_MASK(val): return (val << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK -def CP_COND_WRITE_4_WRITE_ADDR(val): return (val << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK -def CP_COND_WRITE_5_WRITE_DATA(val): return (val << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK -def CP_COND_WRITE5_0_FUNCTION(val): return (val << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK -def CP_COND_WRITE5_0_POLL(val): return (val << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK -def CP_COND_WRITE5_1_POLL_ADDR_LO(val): return (val << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK -def CP_COND_WRITE5_2_POLL_ADDR_HI(val): return (val << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK -def CP_COND_WRITE5_3_REF(val): return (val << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK -def CP_COND_WRITE5_4_MASK(val): return (val << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK -def CP_COND_WRITE5_5_WRITE_ADDR_LO(val): return (val << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK -def CP_COND_WRITE5_6_WRITE_ADDR_HI(val): return (val << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK -def CP_COND_WRITE5_7_WRITE_DATA(val): return (val << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK -def CP_WAIT_MEM_GTE_0_RESERVED(val): return (val << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK -def CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(val): return (val << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK -def CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(val): return (val << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK -def CP_WAIT_MEM_GTE_3_REF(val): return (val << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK -def CP_WAIT_REG_MEM_0_FUNCTION(val): return (val << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK -def CP_WAIT_REG_MEM_0_POLL(val): return (val << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK -def CP_WAIT_REG_MEM_1_POLL_ADDR_LO(val): return (val << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK -def CP_WAIT_REG_MEM_2_POLL_ADDR_HI(val): return (val << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK -def CP_WAIT_REG_MEM_3_REF(val): return (val << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK -def CP_WAIT_REG_MEM_4_MASK(val): return (val << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK -def CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(val): return (val << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK -def CP_WAIT_TWO_REGS_0_REG0(val): return (val << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK -def CP_WAIT_TWO_REGS_1_REG1(val): return (val << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK -def CP_WAIT_TWO_REGS_2_REF(val): return (val << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK -def CP_DISPATCH_COMPUTE_1_X(val): return (val << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK -def CP_DISPATCH_COMPUTE_2_Y(val): return (val << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK -def CP_DISPATCH_COMPUTE_3_Z(val): return (val << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK -def CP_SET_RENDER_MODE_0_MODE(val): return (val << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK -def CP_SET_RENDER_MODE_1_ADDR_0_LO(val): return (val << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK -def CP_SET_RENDER_MODE_2_ADDR_0_HI(val): return (val << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK -def CP_SET_RENDER_MODE_5_ADDR_1_LEN(val): return (val << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK -def CP_SET_RENDER_MODE_6_ADDR_1_LO(val): return (val << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK -def CP_SET_RENDER_MODE_7_ADDR_1_HI(val): return (val << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK -def CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(val): return (val << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK -def CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(val): return (val << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK -def CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(val): return (val << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK -def CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(val): return (val << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK -def CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(val): return (val << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK -def CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(val): return (val << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK -def CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(val): return (val << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK -def CP_EVENT_WRITE_0_EVENT(val): return (val << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK -def CP_EVENT_WRITE_1_ADDR_0_LO(val): return (val << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK -def CP_EVENT_WRITE_2_ADDR_0_HI(val): return (val << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK -def CP_EVENT_WRITE7_0_EVENT(val): return (val << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK -def CP_EVENT_WRITE7_0_WRITE_SRC(val): return (val << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK -def CP_EVENT_WRITE7_0_WRITE_DST(val): return (val << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK -def EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK -def EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK -def EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK -def EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK -def CP_BLIT_0_OP(val): return (val << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK -def CP_BLIT_1_SRC_X1(val): return (val << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK -def CP_BLIT_1_SRC_Y1(val): return (val << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK -def CP_BLIT_2_SRC_X2(val): return (val << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK -def CP_BLIT_2_SRC_Y2(val): return (val << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK -def CP_BLIT_3_DST_X1(val): return (val << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK -def CP_BLIT_3_DST_Y1(val): return (val << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK -def CP_BLIT_4_DST_X2(val): return (val << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK -def CP_BLIT_4_DST_Y2(val): return (val << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK -def CP_EXEC_CS_1_NGROUPS_X(val): return (val << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK -def CP_EXEC_CS_2_NGROUPS_Y(val): return (val << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK -def CP_EXEC_CS_3_NGROUPS_Z(val): return (val << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK -def A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK -def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK -def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK -def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK -def A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK -def A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK -def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK -def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK -def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK -def A6XX_CP_SET_MARKER_0_MODE(val): return (val << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK -def A6XX_CP_SET_MARKER_0_MARKER(val): return (val << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK -def A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(val): return (val << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK -def A6XX_CP_SET_PSEUDO_REG__1_LO(val): return (val << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK -def A6XX_CP_SET_PSEUDO_REG__2_HI(val): return (val << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK -def A6XX_CP_REG_TEST_0_REG(val): return (val << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK -def A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(val): return (val << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK -def A6XX_CP_REG_TEST_0_SOURCE(val): return (val << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK -def A6XX_CP_REG_TEST_0_BIT(val): return (val << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK -def A6XX_CP_REG_TEST_0_PRED_BIT(val): return (val << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK -def CP_COND_REG_EXEC_0_REG0(val): return (val << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK -def CP_COND_REG_EXEC_0_PRED_BIT(val): return (val << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK -def CP_COND_REG_EXEC_0_MODE(val): return (val << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK -def PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(val): return (val << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK -def REG_COMPARE_CP_COND_REG_EXEC_1_REG1(val): return (val << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK -def RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(val): return (val << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK -def REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(val): return (val << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK -def THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(val): return (val << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK -def CP_COND_REG_EXEC_2_DWORDS(val): return (val << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK -def CP_COND_EXEC_0_ADDR0_LO(val): return (val << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK -def CP_COND_EXEC_1_ADDR0_HI(val): return (val << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK -def CP_COND_EXEC_2_ADDR1_LO(val): return (val << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK -def CP_COND_EXEC_3_ADDR1_HI(val): return (val << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK -def CP_COND_EXEC_4_REF(val): return (val << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK -def CP_COND_EXEC_5_DWORDS(val): return (val << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK -def CP_SET_CTXSWITCH_IB_0_ADDR_LO(val): return (val << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK -def CP_SET_CTXSWITCH_IB_1_ADDR_HI(val): return (val << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK -def CP_SET_CTXSWITCH_IB_2_DWORDS(val): return (val << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK -def CP_SET_CTXSWITCH_IB_2_TYPE(val): return (val << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK -def CP_REG_WRITE_0_TRACKER(val): return (val << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK -def CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(val): return (val << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK -def CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(val): return (val << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK -def CP_SMMU_TABLE_UPDATE_1_ASID(val): return (val << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK -def CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(val): return (val << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK -def CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(val): return (val << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK -def CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(val): return (val << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK -def CP_WAIT_TIMESTAMP_0_WAIT_DST(val): return (val << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK -def CP_BV_BR_COUNT_OPS_0_OP(val): return (val << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK -def CP_BV_BR_COUNT_OPS_1_BR_OFFSET(val): return (val << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK -def CP_MODIFY_TIMESTAMP_0_ADD(val): return (val << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK -def CP_MODIFY_TIMESTAMP_0_OP(val): return (val << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK -def CP_MEM_TO_SCRATCH_MEM_0_CNT(val): return (val << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK -def CP_MEM_TO_SCRATCH_MEM_1_OFFSET(val): return (val << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK -def CP_MEM_TO_SCRATCH_MEM_2_SRC(val): return (val << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK -def CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(val): return (val << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK -def CP_THREAD_CONTROL_0_THREAD(val): return (val << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK -def CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK -def CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK -def CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK -def AXXX_CP_RB_CNTL_BUFSZ(val): return (val << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK -def AXXX_CP_RB_CNTL_BLKSZ(val): return (val << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK -def AXXX_CP_RB_CNTL_BUF_SWAP(val): return (val << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK -def AXXX_CP_RB_RPTR_ADDR_SWAP(val): return (val << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK -def AXXX_CP_RB_RPTR_ADDR_ADDR(val): return (val << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK -def AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK -def AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK -def AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK -def AXXX_CP_MEQ_THRESHOLDS_MEQ_END(val): return (val << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK -def AXXX_CP_MEQ_THRESHOLDS_ROQ_END(val): return (val << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK -def AXXX_CP_CSQ_AVAIL_RING(val): return (val << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK -def AXXX_CP_CSQ_AVAIL_IB1(val): return (val << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK -def AXXX_CP_CSQ_AVAIL_IB2(val): return (val << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK -def AXXX_CP_STQ_AVAIL_ST(val): return (val << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK -def AXXX_CP_MEQ_AVAIL_MEQ(val): return (val << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK -def AXXX_SCRATCH_UMSK_UMSK(val): return (val << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK -def AXXX_SCRATCH_UMSK_SWAP(val): return (val << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK -def AXXX_CP_CSQ_RB_STAT_RPTR(val): return (val << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK -def AXXX_CP_CSQ_RB_STAT_WPTR(val): return (val << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK -def AXXX_CP_CSQ_IB1_STAT_RPTR(val): return (val << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK -def AXXX_CP_CSQ_IB1_STAT_WPTR(val): return (val << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK -def AXXX_CP_CSQ_IB2_STAT_RPTR(val): return (val << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK -def AXXX_CP_CSQ_IB2_STAT_WPTR(val): return (val << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK -def A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(val): return (val << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK -def A6XX_CP_PROTECT_REG_BASE_ADDR(val): return (val << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK -def A6XX_CP_PROTECT_REG_MASK_LEN(val): return (val << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK -def A6XX_CP_ROQ_RB_STAT_RPTR(val): return (val << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK -def A6XX_CP_ROQ_RB_STAT_WPTR(val): return (val << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK -def A6XX_CP_ROQ_IB1_STAT_RPTR(val): return (val << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK -def A6XX_CP_ROQ_IB1_STAT_WPTR(val): return (val << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK -def A6XX_CP_ROQ_IB2_STAT_RPTR(val): return (val << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK -def A6XX_CP_ROQ_IB2_STAT_WPTR(val): return (val << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK -def A6XX_CP_ROQ_SDS_STAT_RPTR(val): return (val << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK -def A6XX_CP_ROQ_SDS_STAT_WPTR(val): return (val << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK -def A6XX_CP_ROQ_MRB_STAT_RPTR(val): return (val << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK -def A6XX_CP_ROQ_MRB_STAT_WPTR(val): return (val << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK -def A6XX_CP_ROQ_VSD_STAT_RPTR(val): return (val << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK -def A6XX_CP_ROQ_VSD_STAT_WPTR(val): return (val << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK -def A6XX_CP_ROQ_AVAIL_RB_REM(val): return (val << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK -def A6XX_CP_ROQ_AVAIL_IB1_REM(val): return (val << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK -def A6XX_CP_ROQ_AVAIL_IB2_REM(val): return (val << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK -def A6XX_CP_ROQ_AVAIL_SDS_REM(val): return (val << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK -def A6XX_CP_ROQ_AVAIL_MRB_REM(val): return (val << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK -def A6XX_CP_ROQ_AVAIL_VSD_REM(val): return (val << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK -def A7XX_CP_APERTURE_CNTL_HOST_PIPE(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK -def A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK -def A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK -def A7XX_CP_APERTURE_CNTL_CD_PIPE(val): return (val << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK -def A7XX_CP_APERTURE_CNTL_CD_CLUSTER(val): return (val << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK -def A7XX_CP_APERTURE_CNTL_CD_CONTEXT(val): return (val << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK -def A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(val): return (val << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK -def A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(val): return (val << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK -def A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK -def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK -def A6XX_UCHE_CLIENT_PF_PERFSEL(val): return (val << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK -def A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(val): return (val << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK -def A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(val): return (val << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK -def A6XX_VSC_BIN_SIZE_WIDTH(val): return (val << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK -def A6XX_VSC_BIN_SIZE_HEIGHT(val): return (val << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK -def A6XX_VSC_BIN_COUNT_NX(val): return (val << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK -def A6XX_VSC_BIN_COUNT_NY(val): return (val << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK -def A6XX_VSC_PIPE_CONFIG_REG_X(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK -def A6XX_VSC_PIPE_CONFIG_REG_Y(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK -def A6XX_VSC_PIPE_CONFIG_REG_W(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK -def A6XX_VSC_PIPE_CONFIG_REG_H(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK -def A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK -def A6XX_GRAS_VS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK -def A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK -def A6XX_GRAS_DS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK -def A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK -def A6XX_GRAS_GS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK -def A6XX_GRAS_CNTL_COORD_MASK(val): return (val << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK -def A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(val): return (val << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK -def A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(val): return (val << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK -def A6XX_GRAS_CL_VPORT_XOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK -def A6XX_GRAS_CL_VPORT_XSCALE(val): return (val << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK -def A6XX_GRAS_CL_VPORT_YOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK -def A6XX_GRAS_CL_VPORT_YSCALE(val): return (val << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK -def A6XX_GRAS_CL_VPORT_ZOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK -def A6XX_GRAS_CL_VPORT_ZSCALE(val): return (val << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK -def A6XX_GRAS_CL_Z_CLAMP_MIN(val): return (val << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK -def A6XX_GRAS_CL_Z_CLAMP_MAX(val): return (val << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK -def A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(val): return (val << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK -def A6XX_GRAS_SU_CNTL_LINE_MODE(val): return (val << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK -def A6XX_GRAS_SU_CNTL_UNK15(val): return (val << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK -def A6XX_GRAS_SU_CNTL_UNK20(val): return (val << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK -def A6XX_GRAS_SU_POINT_MINMAX_MIN(val): return (val << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK -def A6XX_GRAS_SU_POINT_MINMAX_MAX(val): return (val << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK -def A6XX_GRAS_SU_POINT_SIZE(val): return (val << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK -def A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(val): return (val << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK -def A6XX_GRAS_SU_POLY_OFFSET_SCALE(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK -def A6XX_GRAS_SU_POLY_OFFSET_OFFSET(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK -def A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK -def A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(val): return (val << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK -def A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(val): return (val << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK -def A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(val): return (val << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK -def A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(val): return (val << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK -def A6XX_GRAS_SC_CNTL_RASTER_MODE(val): return (val << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK -def A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(val): return (val << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK -def A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(val): return (val << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK -def A6XX_GRAS_SC_CNTL_ROTATION(val): return (val << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK -def A6XX_GRAS_BIN_CONTROL_BINW(val): return (val << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK -def A6XX_GRAS_BIN_CONTROL_BINH(val): return (val << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK -def A6XX_GRAS_BIN_CONTROL_RENDER_MODE(val): return (val << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK -def A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(val): return (val << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK -def A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK -def A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK -def A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK -def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK -def A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK -def A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK -def A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK -def A6XX_GRAS_LRZ_CNTL_DIR(val): return (val << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK -def A6XX_GRAS_LRZ_CNTL_Z_FUNC(val): return (val << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK -def A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(val): return (val << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK -def A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(val): return (val << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK -def A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(val): return (val << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK -def A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK -def A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK -def A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK -def A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(val): return (val << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK -def A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A6XX_GRAS_2D_BLIT_CNTL_ROTATE(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK -def A6XX_GRAS_2D_BLIT_CNTL_UNK4(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK -def A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK -def A6XX_GRAS_2D_BLIT_CNTL_UNK17(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK -def A6XX_GRAS_2D_BLIT_CNTL_MASK(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK -def A6XX_GRAS_2D_BLIT_CNTL_IFMT(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK -def A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK -def A6XX_GRAS_2D_SRC_TL_X(val): return (val << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK -def A6XX_GRAS_2D_SRC_BR_X(val): return (val << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK -def A6XX_GRAS_2D_SRC_TL_Y(val): return (val << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK -def A6XX_GRAS_2D_SRC_BR_Y(val): return (val << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK -def A6XX_GRAS_2D_DST_TL_X(val): return (val << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK -def A6XX_GRAS_2D_DST_TL_Y(val): return (val << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK -def A6XX_GRAS_2D_DST_BR_X(val): return (val << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK -def A6XX_GRAS_2D_DST_BR_Y(val): return (val << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_1_X(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_2_X(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK -def A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK -def A6XX_RB_BIN_CONTROL_BINW(val): return (val << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK -def A6XX_RB_BIN_CONTROL_BINH(val): return (val << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK -def A6XX_RB_BIN_CONTROL_RENDER_MODE(val): return (val << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK -def A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(val): return (val << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK -def A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK -def A7XX_RB_BIN_CONTROL_BINW(val): return (val << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK -def A7XX_RB_BIN_CONTROL_BINH(val): return (val << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK -def A7XX_RB_BIN_CONTROL_RENDER_MODE(val): return (val << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK -def A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK -def A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(val): return (val << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK -def A6XX_RB_RENDER_CNTL_UNK8(val): return (val << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK -def A6XX_RB_RENDER_CNTL_RASTER_MODE(val): return (val << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK -def A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(val): return (val << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK -def A6XX_RB_RENDER_CNTL_FLAG_MRTS(val): return (val << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK -def A7XX_RB_RENDER_CNTL_RASTER_MODE(val): return (val << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK -def A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(val): return (val << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK -def A6XX_RB_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK -def A6XX_RB_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK -def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK -def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK -def A6XX_RB_RENDER_CONTROL0_COORD_MASK(val): return (val << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK -def A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(val): return (val << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK -def A6XX_RB_FS_OUTPUT_CNTL1_MRT(val): return (val << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK -def A6XX_RB_RENDER_COMPONENTS_RT0(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK -def A6XX_RB_RENDER_COMPONENTS_RT1(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK -def A6XX_RB_RENDER_COMPONENTS_RT2(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK -def A6XX_RB_RENDER_COMPONENTS_RT3(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK -def A6XX_RB_RENDER_COMPONENTS_RT4(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK -def A6XX_RB_RENDER_COMPONENTS_RT5(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK -def A6XX_RB_RENDER_COMPONENTS_RT6(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK -def A6XX_RB_RENDER_COMPONENTS_RT7(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK -def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK -def A6XX_RB_MRT_CONTROL_ROP_CODE(val): return (val << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK -def A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(val): return (val << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK -def A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK -def A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK -def A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK -def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK -def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK -def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK -def A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK -def A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK -def A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK -def A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK -def A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK -def A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK -def A6XX_RB_MRT_PITCH(val): return (val << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK -def A6XX_RB_MRT_ARRAY_PITCH(val): return (val << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK -def A6XX_RB_BLEND_RED_F32(val): return (val << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK -def A6XX_RB_BLEND_GREEN_F32(val): return (val << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK -def A6XX_RB_BLEND_BLUE_F32(val): return (val << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK -def A6XX_RB_BLEND_ALPHA_F32(val): return (val << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK -def A6XX_RB_ALPHA_CONTROL_ALPHA_REF(val): return (val << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK -def A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(val): return (val << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK -def A6XX_RB_BLEND_CNTL_ENABLE_BLEND(val): return (val << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK -def A6XX_RB_BLEND_CNTL_SAMPLE_MASK(val): return (val << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK -def A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(val): return (val << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK -def A6XX_RB_DEPTH_CNTL_ZFUNC(val): return (val << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK -def A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A6XX_RB_DEPTH_BUFFER_INFO_UNK3(val): return (val << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK -def A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK -def A7XX_RB_DEPTH_BUFFER_INFO_UNK3(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK -def A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK -def A6XX_RB_DEPTH_BUFFER_PITCH(val): return (val << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK -def A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(val): return (val << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK -def A6XX_RB_Z_BOUNDS_MIN(val): return (val << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK -def A6XX_RB_Z_BOUNDS_MAX(val): return (val << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK -def A6XX_RB_STENCIL_CONTROL_FUNC(val): return (val << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK -def A6XX_RB_STENCIL_CONTROL_FAIL(val): return (val << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK -def A6XX_RB_STENCIL_CONTROL_ZPASS(val): return (val << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK -def A6XX_RB_STENCIL_CONTROL_ZFAIL(val): return (val << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK -def A6XX_RB_STENCIL_CONTROL_FUNC_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK -def A6XX_RB_STENCIL_CONTROL_FAIL_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK -def A6XX_RB_STENCIL_CONTROL_ZPASS_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK -def A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK -def A7XX_RB_STENCIL_INFO_TILEMODE(val): return (val << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK -def A6XX_RB_STENCIL_BUFFER_PITCH(val): return (val << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK -def A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(val): return (val << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK -def A6XX_RB_STENCILREF_REF(val): return (val << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK -def A6XX_RB_STENCILREF_BFREF(val): return (val << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK -def A6XX_RB_STENCILMASK_MASK(val): return (val << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK -def A6XX_RB_STENCILMASK_BFMASK(val): return (val << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK -def A6XX_RB_STENCILWRMASK_WRMASK(val): return (val << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK -def A6XX_RB_STENCILWRMASK_BFWRMASK(val): return (val << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK -def A6XX_RB_WINDOW_OFFSET_X(val): return (val << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK -def A6XX_RB_WINDOW_OFFSET_Y(val): return (val << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK -def A6XX_RB_Z_CLAMP_MIN(val): return (val << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK -def A6XX_RB_Z_CLAMP_MAX(val): return (val << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK -def A6XX_RB_UNKNOWN_88D0_UNK0(val): return (val << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK -def A6XX_RB_UNKNOWN_88D0_UNK16(val): return (val << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK -def A6XX_RB_BLIT_SCISSOR_TL_X(val): return (val << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK -def A6XX_RB_BLIT_SCISSOR_TL_Y(val): return (val << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK -def A6XX_RB_BLIT_SCISSOR_BR_X(val): return (val << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK -def A6XX_RB_BLIT_SCISSOR_BR_Y(val): return (val << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK -def A6XX_RB_BIN_CONTROL2_BINW(val): return (val << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK -def A6XX_RB_BIN_CONTROL2_BINH(val): return (val << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK -def A6XX_RB_WINDOW_OFFSET2_X(val): return (val << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK -def A6XX_RB_WINDOW_OFFSET2_Y(val): return (val << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK -def A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK -def A6XX_RB_BLIT_DST_INFO_TILE_MODE(val): return (val << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK -def A6XX_RB_BLIT_DST_INFO_SAMPLES(val): return (val << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK -def A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(val): return (val << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK -def A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK -def A6XX_RB_BLIT_DST_PITCH(val): return (val << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK -def A6XX_RB_BLIT_DST_ARRAY_PITCH(val): return (val << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK -def A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(val): return (val << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK -def A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_BLIT_INFO_CLEAR_MASK(val): return (val << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK -def A6XX_RB_BLIT_INFO_LAST(val): return (val << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK -def A6XX_RB_BLIT_INFO_BUFFER_ID(val): return (val << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK -def A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK -def A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK -def A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK -def A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK -def A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK -def A7XX_RB_CCU_CNTL2_COLOR_OFFSET(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK -def A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK -def A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK -def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK -def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK -def A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK -def A6XX_RB_2D_BLIT_CNTL_ROTATE(val): return (val << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK -def A6XX_RB_2D_BLIT_CNTL_UNK4(val): return (val << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK -def A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(val): return (val << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK -def A6XX_RB_2D_BLIT_CNTL_UNK17(val): return (val << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK -def A6XX_RB_2D_BLIT_CNTL_MASK(val): return (val << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK -def A6XX_RB_2D_BLIT_CNTL_IFMT(val): return (val << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK -def A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(val): return (val << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK -def A6XX_RB_2D_DST_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK -def A6XX_RB_2D_DST_INFO_TILE_MODE(val): return (val << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK -def A6XX_RB_2D_DST_INFO_COLOR_SWAP(val): return (val << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK -def A6XX_RB_2D_DST_INFO_SAMPLES(val): return (val << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK -def A6XX_RB_2D_DST_INFO_UNK23(val): return (val << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK -def A6XX_RB_2D_DST_PITCH(val): return (val << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK -def A6XX_RB_2D_DST_PLANE_PITCH(val): return (val << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK -def A6XX_RB_2D_DST_FLAGS_PITCH(val): return (val << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK -def A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(val): return (val << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK -def A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK -def A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(val): return (val << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK -def A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK -def A6XX_RB_CCU_CNTL_DEPTH_OFFSET(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK -def A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(val): return (val << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK -def A6XX_RB_CCU_CNTL_COLOR_OFFSET(val): return (val << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK -def A6XX_RB_NC_MODE_CNTL_LOWER_BIT(val): return (val << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK -def A6XX_RB_NC_MODE_CNTL_UPPER_BIT(val): return (val << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK -def A6XX_RB_NC_MODE_CNTL_UNK12(val): return (val << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK -def A6XX_VPC_GS_PARAM_LINELENGTHLOC(val): return (val << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK -def A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK -def A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK -def A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK -def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK -def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK -def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK -def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK -def A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK -def A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK -def A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK -def A6XX_VPC_POLYGON_MODE_MODE(val): return (val << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK -def A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK -def A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK -def A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK -def A7XX_VPC_MULTIVIEW_CNTL_VIEWS(val): return (val << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK -def A6XX_VPC_SO_CNTL_ADDR(val): return (val << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK -def A6XX_VPC_SO_PROG_A_BUF(val): return (val << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK -def A6XX_VPC_SO_PROG_A_OFF(val): return (val << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK -def A6XX_VPC_SO_PROG_B_BUF(val): return (val << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK -def A6XX_VPC_SO_PROG_B_OFF(val): return (val << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK -def A6XX_VPC_VS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK -def A6XX_VPC_VS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK -def A6XX_VPC_VS_PACK_PSIZELOC(val): return (val << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK -def A6XX_VPC_VS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK -def A6XX_VPC_GS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK -def A6XX_VPC_GS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK -def A6XX_VPC_GS_PACK_PSIZELOC(val): return (val << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK -def A6XX_VPC_GS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK -def A6XX_VPC_DS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK -def A6XX_VPC_DS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK -def A6XX_VPC_DS_PACK_PSIZELOC(val): return (val << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK -def A6XX_VPC_DS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK -def A6XX_VPC_CNTL_0_NUMNONPOSVAR(val): return (val << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK -def A6XX_VPC_CNTL_0_PRIMIDLOC(val): return (val << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK -def A6XX_VPC_CNTL_0_VIEWIDLOC(val): return (val << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK -def A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(val): return (val << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK -def A7XX_VPC_POLYGON_MODE2_MODE(val): return (val << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK -def A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(val): return (val << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK -def A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(val): return (val << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK -def A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(val): return (val << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK -def A6XX_PC_HS_INPUT_SIZE_SIZE(val): return (val << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK -def A6XX_PC_TESS_CNTL_SPACING(val): return (val << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK -def A6XX_PC_TESS_CNTL_OUTPUT(val): return (val << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK -def A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(val): return (val << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK -def A6XX_PC_DRAW_CMD_STATE_ID(val): return (val << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK -def A6XX_PC_DISPATCH_CMD_STATE_ID(val): return (val << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK -def A6XX_PC_EVENT_CMD_STATE_ID(val): return (val << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK -def A6XX_PC_EVENT_CMD_EVENT(val): return (val << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK -def A6XX_PC_POLYGON_MODE_MODE(val): return (val << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK -def A7XX_PC_POLYGON_MODE_MODE(val): return (val << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK -def A6XX_PC_RASTER_CNTL_STREAM(val): return (val << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK -def A7XX_PC_RASTER_CNTL_STREAM(val): return (val << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK -def A7XX_PC_RASTER_CNTL_V2_STREAM(val): return (val << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK -def A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_VS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_GS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_HS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK -def A6XX_PC_DS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK -def A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK -def A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK -def A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK -def A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(val): return (val << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK -def A6XX_PC_MULTIVIEW_CNTL_VIEWS(val): return (val << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK -def A6XX_PC_2D_EVENT_CMD_EVENT(val): return (val << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK -def A6XX_PC_2D_EVENT_CMD_STATE_ID(val): return (val << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK -def A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(val): return (val << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK -def A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(val): return (val << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK -def A6XX_PC_DRAW_INITIATOR_VIS_CULL(val): return (val << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK -def A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(val): return (val << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK -def A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(val): return (val << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK -def A6XX_PC_VSTREAM_CONTROL_UNK0(val): return (val << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK -def A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(val): return (val << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK -def A6XX_PC_VSTREAM_CONTROL_VSC_N(val): return (val << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK -def A6XX_VFD_CONTROL_0_FETCH_CNT(val): return (val << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK -def A6XX_VFD_CONTROL_0_DECODE_CNT(val): return (val << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK -def A6XX_VFD_CONTROL_1_REGID4VTX(val): return (val << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK -def A6XX_VFD_CONTROL_1_REGID4INST(val): return (val << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK -def A6XX_VFD_CONTROL_1_REGID4PRIMID(val): return (val << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK -def A6XX_VFD_CONTROL_1_REGID4VIEWID(val): return (val << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK -def A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(val): return (val << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK -def A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(val): return (val << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK -def A6XX_VFD_CONTROL_3_REGID_DSPRIMID(val): return (val << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK -def A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(val): return (val << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK -def A6XX_VFD_CONTROL_3_REGID_TESSX(val): return (val << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK -def A6XX_VFD_CONTROL_3_REGID_TESSY(val): return (val << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK -def A6XX_VFD_CONTROL_4_UNK0(val): return (val << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK -def A6XX_VFD_CONTROL_5_REGID_GSHEADER(val): return (val << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK -def A6XX_VFD_CONTROL_5_UNK8(val): return (val << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK -def A6XX_VFD_MODE_CNTL_RENDER_MODE(val): return (val << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK -def A6XX_VFD_MULTIVIEW_CNTL_VIEWS(val): return (val << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK -def A6XX_VFD_DECODE_INSTR_IDX(val): return (val << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK -def A6XX_VFD_DECODE_INSTR_OFFSET(val): return (val << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK -def A6XX_VFD_DECODE_INSTR_FORMAT(val): return (val << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK -def A6XX_VFD_DECODE_INSTR_SWAP(val): return (val << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK -def A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(val): return (val << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK -def A6XX_VFD_DEST_CNTL_INSTR_REGID(val): return (val << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK -def A6XX_SP_VS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_VS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK -def A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK -def A6XX_SP_VS_OUT_REG_A_REGID(val): return (val << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK -def A6XX_SP_VS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK -def A6XX_SP_VS_OUT_REG_B_REGID(val): return (val << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK -def A6XX_SP_VS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK -def A6XX_SP_VS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK -def A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_VS_CONFIG_NTEX(val): return (val << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK -def A6XX_SP_VS_CONFIG_NSAMP(val): return (val << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK -def A6XX_SP_VS_CONFIG_NIBO(val): return (val << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK -def A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_HS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_HS_CONFIG_NTEX(val): return (val << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK -def A6XX_SP_HS_CONFIG_NSAMP(val): return (val << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK -def A6XX_SP_HS_CONFIG_NIBO(val): return (val << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK -def A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_DS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_DS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK -def A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK -def A6XX_SP_DS_OUT_REG_A_REGID(val): return (val << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK -def A6XX_SP_DS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK -def A6XX_SP_DS_OUT_REG_B_REGID(val): return (val << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK -def A6XX_SP_DS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK -def A6XX_SP_DS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK -def A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_DS_CONFIG_NTEX(val): return (val << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK -def A6XX_SP_DS_CONFIG_NSAMP(val): return (val << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK -def A6XX_SP_DS_CONFIG_NIBO(val): return (val << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK -def A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_GS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_GS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK -def A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK -def A6XX_SP_GS_OUT_REG_A_REGID(val): return (val << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK -def A6XX_SP_GS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK -def A6XX_SP_GS_OUT_REG_B_REGID(val): return (val << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK -def A6XX_SP_GS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK -def A6XX_SP_GS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK -def A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_GS_CONFIG_NTEX(val): return (val << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK -def A6XX_SP_GS_CONFIG_NSAMP(val): return (val << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK -def A6XX_SP_GS_CONFIG_NIBO(val): return (val << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK -def A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_FS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_FS_CTRL_REG0_THREADSIZE(val): return (val << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK -def A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_BLEND_CNTL_ENABLE_BLEND(val): return (val << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT0(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT1(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT2(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT3(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT4(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT5(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT6(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK -def A6XX_SP_FS_RENDER_COMPONENTS_RT7(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK -def A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK -def A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK -def A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK -def A6XX_SP_FS_OUTPUT_CNTL1_MRT(val): return (val << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK -def A6XX_SP_FS_OUTPUT_REG_REGID(val): return (val << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK -def A6XX_SP_FS_MRT_REG_COLOR_FORMAT(val): return (val << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK -def A6XX_SP_FS_PREFETCH_CNTL_COUNT(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK -def A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK -def A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK -def A6XX_SP_FS_PREFETCH_CMD_SRC(val): return (val << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK -def A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(val): return (val << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK -def A6XX_SP_FS_PREFETCH_CMD_TEX_ID(val): return (val << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK -def A6XX_SP_FS_PREFETCH_CMD_DST(val): return (val << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK -def A6XX_SP_FS_PREFETCH_CMD_WRMASK(val): return (val << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK -def A6XX_SP_FS_PREFETCH_CMD_CMD(val): return (val << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK -def A7XX_SP_FS_PREFETCH_CMD_SRC(val): return (val << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK -def A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(val): return (val << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK -def A7XX_SP_FS_PREFETCH_CMD_TEX_ID(val): return (val << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK -def A7XX_SP_FS_PREFETCH_CMD_DST(val): return (val << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK -def A7XX_SP_FS_PREFETCH_CMD_WRMASK(val): return (val << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK -def A7XX_SP_FS_PREFETCH_CMD_CMD(val): return (val << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK -def A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(val): return (val << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK -def A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(val): return (val << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK -def A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_CS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK -def A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK -def A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK -def A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK -def A6XX_SP_CS_CTRL_REG0_THREADSIZE(val): return (val << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK -def A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(val): return (val << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK -def A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK -def A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK -def A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK -def A6XX_SP_CS_CONFIG_NTEX(val): return (val << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK -def A6XX_SP_CS_CONFIG_NSAMP(val): return (val << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK -def A6XX_SP_CS_CONFIG_NIBO(val): return (val << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK -def A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK -def A6XX_SP_CS_CNTL_0_WGIDCONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK -def A6XX_SP_CS_CNTL_0_WGSIZECONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK -def A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK -def A6XX_SP_CS_CNTL_0_LOCALIDREGID(val): return (val << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK -def A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A6XX_SP_CS_CNTL_1_THREADSIZE(val): return (val << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK -def A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A7XX_SP_CS_CNTL_1_THREADSIZE(val): return (val << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK -def A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT0(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT1(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT2(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT3(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT4(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT5(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT6(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK -def A7XX_SP_PS_ALIASED_COMPONENTS_RT7(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK -def A6XX_SP_MODE_CONTROL_ISAMMODE(val): return (val << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK -def A6XX_SP_FS_CONFIG_NTEX(val): return (val << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK -def A6XX_SP_FS_CONFIG_NSAMP(val): return (val << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK -def A6XX_SP_FS_CONFIG_NIBO(val): return (val << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK -def A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(val): return (val << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK -def A6XX_SP_2D_DST_FORMAT_MASK(val): return (val << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK -def A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(val): return (val << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK -def A7XX_SP_2D_DST_FORMAT_MASK(val): return (val << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK -def A7XX_SP_READ_SEL_LOCATION(val): return (val << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK -def A7XX_SP_READ_SEL_PIPE(val): return (val << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK -def A7XX_SP_READ_SEL_STATETYPE(val): return (val << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK -def A7XX_SP_READ_SEL_USPTP(val): return (val << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK -def A7XX_SP_READ_SEL_SPTP(val): return (val << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK -def A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK -def A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(val): return (val << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK -def A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK -def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK -def A6XX_SP_TP_WINDOW_OFFSET_X(val): return (val << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK -def A6XX_SP_TP_WINDOW_OFFSET_Y(val): return (val << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK -def A6XX_SP_TP_MODE_CNTL_ISAMMODE(val): return (val << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK -def A6XX_SP_TP_MODE_CNTL_UNK3(val): return (val << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK -def A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(val): return (val << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK -def A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(val): return (val << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK -def A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(val): return (val << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK -def A6XX_SP_PS_2D_SRC_INFO_SAMPLES(val): return (val << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK -def A6XX_SP_PS_2D_SRC_INFO_UNK23(val): return (val << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK -def A6XX_SP_PS_2D_SRC_SIZE_WIDTH(val): return (val << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK -def A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(val): return (val << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK -def A6XX_SP_PS_2D_SRC_PITCH_UNK0(val): return (val << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK -def A6XX_SP_PS_2D_SRC_PITCH_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK -def A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(val): return (val << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK -def A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(val): return (val << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK -def A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(val): return (val << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK -def A7XX_SP_PS_2D_SRC_INFO_SAMPLES(val): return (val << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK -def A7XX_SP_PS_2D_SRC_INFO_UNK23(val): return (val << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK -def A7XX_SP_PS_2D_SRC_SIZE_WIDTH(val): return (val << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK -def A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(val): return (val << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK -def A7XX_SP_PS_2D_SRC_PITCH_UNK0(val): return (val << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK -def A7XX_SP_PS_2D_SRC_PITCH_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK -def A6XX_SP_PS_2D_SRC_PLANE_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK -def A7XX_SP_PS_2D_SRC_PLANE_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK -def A6XX_SP_PS_2D_SRC_FLAGS_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK -def A7XX_SP_PS_2D_SRC_FLAGS_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK -def A6XX_SP_WINDOW_OFFSET_X(val): return (val << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK -def A6XX_SP_WINDOW_OFFSET_Y(val): return (val << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK -def A7XX_SP_PS_2D_WINDOW_OFFSET_X(val): return (val << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK -def A7XX_SP_PS_2D_WINDOW_OFFSET_Y(val): return (val << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK -def A7XX_SP_WINDOW_OFFSET_X(val): return (val << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK -def A7XX_SP_WINDOW_OFFSET_Y(val): return (val << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK -def A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(val): return (val << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK -def A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(val): return (val << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK -def A6XX_TPL1_NC_MODE_CNTL_UNK6(val): return (val << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK -def A6XX_HLSQ_VS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_HS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_DS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_GS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_VS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_HS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_DS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_GS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(val): return (val << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK -def A6XX_HLSQ_FS_CNTL_0_THREADSIZE(val): return (val << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK -def A6XX_HLSQ_FS_CNTL_0_UNK2(val): return (val << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK -def A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(val): return (val << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK -def A6XX_HLSQ_CONTROL_2_REG_FACEREGID(val): return (val << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK -def A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(val): return (val << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK -def A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(val): return (val << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK -def A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(val): return (val << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK -def A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK -def A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(val): return (val << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK -def A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(val): return (val << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK -def A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(val): return (val << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK -def A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(val): return (val << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK -def A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(val): return (val << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK -def A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(val): return (val << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK -def A6XX_HLSQ_CS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_FS_CNTL_0_THREADSIZE(val): return (val << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK -def A7XX_HLSQ_FS_CNTL_0_UNK2(val): return (val << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK -def A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(val): return (val << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK -def A7XX_HLSQ_CONTROL_2_REG_FACEREGID(val): return (val << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK -def A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(val): return (val << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK -def A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(val): return (val << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK -def A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(val): return (val << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK -def A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK -def A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(val): return (val << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK -def A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(val): return (val << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK -def A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(val): return (val << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK -def A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(val): return (val << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK -def A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(val): return (val << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK -def A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(val): return (val << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK -def A7XX_HLSQ_CS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK -def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK -def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK -def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK -def A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(val): return (val << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK -def A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(val): return (val << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK -def A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(val): return (val << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK -def A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(val): return (val << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK -def A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(val): return (val << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK -def A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(val): return (val << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK -def A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK -def A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK -def A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK -def A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(val): return (val << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK -def A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A6XX_HLSQ_CS_CNTL_1_THREADSIZE(val): return (val << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK -def A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK -def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK -def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK -def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK -def A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(val): return (val << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK -def A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(val): return (val << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK -def A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(val): return (val << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK -def A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(val): return (val << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK -def A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(val): return (val << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK -def A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(val): return (val << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK -def A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK -def A7XX_HLSQ_CS_CNTL_1_THREADSIZE(val): return (val << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK -def A7XX_HLSQ_CS_CNTL_1_YALIGN(val): return (val << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK -def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK -def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK -def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK -def A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(val): return (val << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK -def A6XX_HLSQ_DRAW_CMD_STATE_ID(val): return (val << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK -def A6XX_HLSQ_DISPATCH_CMD_STATE_ID(val): return (val << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK -def A6XX_HLSQ_EVENT_CMD_STATE_ID(val): return (val << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK -def A6XX_HLSQ_EVENT_CMD_EVENT(val): return (val << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK -def A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(val): return (val << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK -def A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(val): return (val << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK -def A7XX_HLSQ_DRAW_CMD_STATE_ID(val): return (val << A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK -def A7XX_HLSQ_DISPATCH_CMD_STATE_ID(val): return (val << A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK -def A7XX_HLSQ_EVENT_CMD_STATE_ID(val): return (val << A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK -def A7XX_HLSQ_EVENT_CMD_EVENT(val): return (val << A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A7XX_HLSQ_EVENT_CMD_EVENT__MASK -def A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(val): return (val << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK -def A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(val): return (val << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK -def A6XX_HLSQ_FS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK -def A7XX_HLSQ_FS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK -def A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK -def A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK -def A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(val): return (val << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK -def A6XX_HLSQ_2D_EVENT_CMD_EVENT(val): return (val << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK -def A6XX_CP_EVENT_START_STATE_ID(val): return (val << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK -def A6XX_CP_EVENT_END_STATE_ID(val): return (val << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK -def A6XX_CP_2D_EVENT_START_STATE_ID(val): return (val << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK -def A6XX_CP_2D_EVENT_END_STATE_ID(val): return (val << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK -def A6XX_TEX_SAMP_0_XY_MAG(val): return (val << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK -def A6XX_TEX_SAMP_0_XY_MIN(val): return (val << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK -def A6XX_TEX_SAMP_0_WRAP_S(val): return (val << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK -def A6XX_TEX_SAMP_0_WRAP_T(val): return (val << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK -def A6XX_TEX_SAMP_0_WRAP_R(val): return (val << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK -def A6XX_TEX_SAMP_0_ANISO(val): return (val << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK -def A6XX_TEX_SAMP_0_LOD_BIAS(val): return (val << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK -def A6XX_TEX_SAMP_1_COMPARE_FUNC(val): return (val << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK -def A6XX_TEX_SAMP_1_MAX_LOD(val): return (val << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK -def A6XX_TEX_SAMP_1_MIN_LOD(val): return (val << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK -def A6XX_TEX_SAMP_2_REDUCTION_MODE(val): return (val << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK -def A6XX_TEX_SAMP_2_BCOLOR(val): return (val << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK -def A6XX_TEX_CONST_0_TILE_MODE(val): return (val << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK -def A6XX_TEX_CONST_0_SWIZ_X(val): return (val << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK -def A6XX_TEX_CONST_0_SWIZ_Y(val): return (val << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK -def A6XX_TEX_CONST_0_SWIZ_Z(val): return (val << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK -def A6XX_TEX_CONST_0_SWIZ_W(val): return (val << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK -def A6XX_TEX_CONST_0_MIPLVLS(val): return (val << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK -def A6XX_TEX_CONST_0_SAMPLES(val): return (val << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK -def A6XX_TEX_CONST_0_FMT(val): return (val << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK -def A6XX_TEX_CONST_0_SWAP(val): return (val << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK -def A6XX_TEX_CONST_1_WIDTH(val): return (val << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK -def A6XX_TEX_CONST_1_HEIGHT(val): return (val << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK -def A6XX_TEX_CONST_2_STRUCTSIZETEXELS(val): return (val << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK -def A6XX_TEX_CONST_2_STARTOFFSETTEXELS(val): return (val << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK -def A6XX_TEX_CONST_2_PITCHALIGN(val): return (val << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK -def A6XX_TEX_CONST_2_PITCH(val): return (val << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK -def A6XX_TEX_CONST_2_TYPE(val): return (val << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK -def A6XX_TEX_CONST_3_ARRAY_PITCH(val): return (val << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK -def A6XX_TEX_CONST_3_MIN_LAYERSZ(val): return (val << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK -def A6XX_TEX_CONST_4_BASE_LO(val): return (val << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK -def A6XX_TEX_CONST_5_BASE_HI(val): return (val << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK -def A6XX_TEX_CONST_5_DEPTH(val): return (val << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK -def A6XX_TEX_CONST_6_MIN_LOD_CLAMP(val): return (val << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK -def A6XX_TEX_CONST_6_PLANE_PITCH(val): return (val << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK -def A6XX_TEX_CONST_7_FLAG_LO(val): return (val << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK -def A6XX_TEX_CONST_8_FLAG_HI(val): return (val << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK -def A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(val): return (val << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK -def A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK -def A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK -def A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK -def A6XX_UBO_0_BASE_LO(val): return (val << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK -def A6XX_UBO_1_BASE_HI(val): return (val << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK -def A6XX_UBO_1_SIZE(val): return (val << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK -def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +enum_vgt_event_type = CEnum(ctypes.c_uint32) +VS_DEALLOC = enum_vgt_event_type.define('VS_DEALLOC', 0) +PS_DEALLOC = enum_vgt_event_type.define('PS_DEALLOC', 1) +VS_DONE_TS = enum_vgt_event_type.define('VS_DONE_TS', 2) +PS_DONE_TS = enum_vgt_event_type.define('PS_DONE_TS', 3) +CACHE_FLUSH_TS = enum_vgt_event_type.define('CACHE_FLUSH_TS', 4) +CONTEXT_DONE = enum_vgt_event_type.define('CONTEXT_DONE', 5) +CACHE_FLUSH = enum_vgt_event_type.define('CACHE_FLUSH', 6) +VIZQUERY_START = enum_vgt_event_type.define('VIZQUERY_START', 7) +HLSQ_FLUSH = enum_vgt_event_type.define('HLSQ_FLUSH', 7) +VIZQUERY_END = enum_vgt_event_type.define('VIZQUERY_END', 8) +SC_WAIT_WC = enum_vgt_event_type.define('SC_WAIT_WC', 9) +WRITE_PRIMITIVE_COUNTS = enum_vgt_event_type.define('WRITE_PRIMITIVE_COUNTS', 9) +START_PRIMITIVE_CTRS = enum_vgt_event_type.define('START_PRIMITIVE_CTRS', 11) +STOP_PRIMITIVE_CTRS = enum_vgt_event_type.define('STOP_PRIMITIVE_CTRS', 12) +RST_PIX_CNT = enum_vgt_event_type.define('RST_PIX_CNT', 13) +RST_VTX_CNT = enum_vgt_event_type.define('RST_VTX_CNT', 14) +TILE_FLUSH = enum_vgt_event_type.define('TILE_FLUSH', 15) +STAT_EVENT = enum_vgt_event_type.define('STAT_EVENT', 16) +CACHE_FLUSH_AND_INV_TS_EVENT = enum_vgt_event_type.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) +ZPASS_DONE = enum_vgt_event_type.define('ZPASS_DONE', 21) +CACHE_FLUSH_AND_INV_EVENT = enum_vgt_event_type.define('CACHE_FLUSH_AND_INV_EVENT', 22) +RB_DONE_TS = enum_vgt_event_type.define('RB_DONE_TS', 22) +PERFCOUNTER_START = enum_vgt_event_type.define('PERFCOUNTER_START', 23) +PERFCOUNTER_STOP = enum_vgt_event_type.define('PERFCOUNTER_STOP', 24) +VS_FETCH_DONE = enum_vgt_event_type.define('VS_FETCH_DONE', 27) +FACENESS_FLUSH = enum_vgt_event_type.define('FACENESS_FLUSH', 28) +WT_DONE_TS = enum_vgt_event_type.define('WT_DONE_TS', 8) +START_FRAGMENT_CTRS = enum_vgt_event_type.define('START_FRAGMENT_CTRS', 13) +STOP_FRAGMENT_CTRS = enum_vgt_event_type.define('STOP_FRAGMENT_CTRS', 14) +START_COMPUTE_CTRS = enum_vgt_event_type.define('START_COMPUTE_CTRS', 15) +STOP_COMPUTE_CTRS = enum_vgt_event_type.define('STOP_COMPUTE_CTRS', 16) +FLUSH_SO_0 = enum_vgt_event_type.define('FLUSH_SO_0', 17) +FLUSH_SO_1 = enum_vgt_event_type.define('FLUSH_SO_1', 18) +FLUSH_SO_2 = enum_vgt_event_type.define('FLUSH_SO_2', 19) +FLUSH_SO_3 = enum_vgt_event_type.define('FLUSH_SO_3', 20) +PC_CCU_INVALIDATE_DEPTH = enum_vgt_event_type.define('PC_CCU_INVALIDATE_DEPTH', 24) +PC_CCU_INVALIDATE_COLOR = enum_vgt_event_type.define('PC_CCU_INVALIDATE_COLOR', 25) +PC_CCU_RESOLVE_TS = enum_vgt_event_type.define('PC_CCU_RESOLVE_TS', 26) +PC_CCU_FLUSH_DEPTH_TS = enum_vgt_event_type.define('PC_CCU_FLUSH_DEPTH_TS', 28) +PC_CCU_FLUSH_COLOR_TS = enum_vgt_event_type.define('PC_CCU_FLUSH_COLOR_TS', 29) +BLIT = enum_vgt_event_type.define('BLIT', 30) +LRZ_FLIP_BUFFER = enum_vgt_event_type.define('LRZ_FLIP_BUFFER', 36) +LRZ_CLEAR = enum_vgt_event_type.define('LRZ_CLEAR', 37) +LRZ_FLUSH = enum_vgt_event_type.define('LRZ_FLUSH', 38) +BLIT_OP_FILL_2D = enum_vgt_event_type.define('BLIT_OP_FILL_2D', 39) +BLIT_OP_COPY_2D = enum_vgt_event_type.define('BLIT_OP_COPY_2D', 40) +UNK_40 = enum_vgt_event_type.define('UNK_40', 40) +BLIT_OP_SCALE_2D = enum_vgt_event_type.define('BLIT_OP_SCALE_2D', 42) +CONTEXT_DONE_2D = enum_vgt_event_type.define('CONTEXT_DONE_2D', 43) +UNK_2C = enum_vgt_event_type.define('UNK_2C', 44) +UNK_2D = enum_vgt_event_type.define('UNK_2D', 45) +CACHE_INVALIDATE = enum_vgt_event_type.define('CACHE_INVALIDATE', 49) +LABEL = enum_vgt_event_type.define('LABEL', 63) +DUMMY_EVENT = enum_vgt_event_type.define('DUMMY_EVENT', 1) +CCU_INVALIDATE_DEPTH = enum_vgt_event_type.define('CCU_INVALIDATE_DEPTH', 24) +CCU_INVALIDATE_COLOR = enum_vgt_event_type.define('CCU_INVALIDATE_COLOR', 25) +CCU_RESOLVE_CLEAN = enum_vgt_event_type.define('CCU_RESOLVE_CLEAN', 26) +CCU_FLUSH_DEPTH = enum_vgt_event_type.define('CCU_FLUSH_DEPTH', 28) +CCU_FLUSH_COLOR = enum_vgt_event_type.define('CCU_FLUSH_COLOR', 29) +CCU_RESOLVE = enum_vgt_event_type.define('CCU_RESOLVE', 30) +CCU_END_RESOLVE_GROUP = enum_vgt_event_type.define('CCU_END_RESOLVE_GROUP', 31) +CCU_CLEAN_DEPTH = enum_vgt_event_type.define('CCU_CLEAN_DEPTH', 32) +CCU_CLEAN_COLOR = enum_vgt_event_type.define('CCU_CLEAN_COLOR', 33) +CACHE_RESET = enum_vgt_event_type.define('CACHE_RESET', 48) +CACHE_CLEAN = enum_vgt_event_type.define('CACHE_CLEAN', 49) +CACHE_FLUSH7 = enum_vgt_event_type.define('CACHE_FLUSH7', 50) +CACHE_INVALIDATE7 = enum_vgt_event_type.define('CACHE_INVALIDATE7', 51) + +enum_pc_di_primtype = CEnum(ctypes.c_uint32) +DI_PT_NONE = enum_pc_di_primtype.define('DI_PT_NONE', 0) +DI_PT_POINTLIST_PSIZE = enum_pc_di_primtype.define('DI_PT_POINTLIST_PSIZE', 1) +DI_PT_LINELIST = enum_pc_di_primtype.define('DI_PT_LINELIST', 2) +DI_PT_LINESTRIP = enum_pc_di_primtype.define('DI_PT_LINESTRIP', 3) +DI_PT_TRILIST = enum_pc_di_primtype.define('DI_PT_TRILIST', 4) +DI_PT_TRIFAN = enum_pc_di_primtype.define('DI_PT_TRIFAN', 5) +DI_PT_TRISTRIP = enum_pc_di_primtype.define('DI_PT_TRISTRIP', 6) +DI_PT_LINELOOP = enum_pc_di_primtype.define('DI_PT_LINELOOP', 7) +DI_PT_RECTLIST = enum_pc_di_primtype.define('DI_PT_RECTLIST', 8) +DI_PT_POINTLIST = enum_pc_di_primtype.define('DI_PT_POINTLIST', 9) +DI_PT_LINE_ADJ = enum_pc_di_primtype.define('DI_PT_LINE_ADJ', 10) +DI_PT_LINESTRIP_ADJ = enum_pc_di_primtype.define('DI_PT_LINESTRIP_ADJ', 11) +DI_PT_TRI_ADJ = enum_pc_di_primtype.define('DI_PT_TRI_ADJ', 12) +DI_PT_TRISTRIP_ADJ = enum_pc_di_primtype.define('DI_PT_TRISTRIP_ADJ', 13) +DI_PT_PATCHES0 = enum_pc_di_primtype.define('DI_PT_PATCHES0', 31) +DI_PT_PATCHES1 = enum_pc_di_primtype.define('DI_PT_PATCHES1', 32) +DI_PT_PATCHES2 = enum_pc_di_primtype.define('DI_PT_PATCHES2', 33) +DI_PT_PATCHES3 = enum_pc_di_primtype.define('DI_PT_PATCHES3', 34) +DI_PT_PATCHES4 = enum_pc_di_primtype.define('DI_PT_PATCHES4', 35) +DI_PT_PATCHES5 = enum_pc_di_primtype.define('DI_PT_PATCHES5', 36) +DI_PT_PATCHES6 = enum_pc_di_primtype.define('DI_PT_PATCHES6', 37) +DI_PT_PATCHES7 = enum_pc_di_primtype.define('DI_PT_PATCHES7', 38) +DI_PT_PATCHES8 = enum_pc_di_primtype.define('DI_PT_PATCHES8', 39) +DI_PT_PATCHES9 = enum_pc_di_primtype.define('DI_PT_PATCHES9', 40) +DI_PT_PATCHES10 = enum_pc_di_primtype.define('DI_PT_PATCHES10', 41) +DI_PT_PATCHES11 = enum_pc_di_primtype.define('DI_PT_PATCHES11', 42) +DI_PT_PATCHES12 = enum_pc_di_primtype.define('DI_PT_PATCHES12', 43) +DI_PT_PATCHES13 = enum_pc_di_primtype.define('DI_PT_PATCHES13', 44) +DI_PT_PATCHES14 = enum_pc_di_primtype.define('DI_PT_PATCHES14', 45) +DI_PT_PATCHES15 = enum_pc_di_primtype.define('DI_PT_PATCHES15', 46) +DI_PT_PATCHES16 = enum_pc_di_primtype.define('DI_PT_PATCHES16', 47) +DI_PT_PATCHES17 = enum_pc_di_primtype.define('DI_PT_PATCHES17', 48) +DI_PT_PATCHES18 = enum_pc_di_primtype.define('DI_PT_PATCHES18', 49) +DI_PT_PATCHES19 = enum_pc_di_primtype.define('DI_PT_PATCHES19', 50) +DI_PT_PATCHES20 = enum_pc_di_primtype.define('DI_PT_PATCHES20', 51) +DI_PT_PATCHES21 = enum_pc_di_primtype.define('DI_PT_PATCHES21', 52) +DI_PT_PATCHES22 = enum_pc_di_primtype.define('DI_PT_PATCHES22', 53) +DI_PT_PATCHES23 = enum_pc_di_primtype.define('DI_PT_PATCHES23', 54) +DI_PT_PATCHES24 = enum_pc_di_primtype.define('DI_PT_PATCHES24', 55) +DI_PT_PATCHES25 = enum_pc_di_primtype.define('DI_PT_PATCHES25', 56) +DI_PT_PATCHES26 = enum_pc_di_primtype.define('DI_PT_PATCHES26', 57) +DI_PT_PATCHES27 = enum_pc_di_primtype.define('DI_PT_PATCHES27', 58) +DI_PT_PATCHES28 = enum_pc_di_primtype.define('DI_PT_PATCHES28', 59) +DI_PT_PATCHES29 = enum_pc_di_primtype.define('DI_PT_PATCHES29', 60) +DI_PT_PATCHES30 = enum_pc_di_primtype.define('DI_PT_PATCHES30', 61) +DI_PT_PATCHES31 = enum_pc_di_primtype.define('DI_PT_PATCHES31', 62) + +enum_pc_di_src_sel = CEnum(ctypes.c_uint32) +DI_SRC_SEL_DMA = enum_pc_di_src_sel.define('DI_SRC_SEL_DMA', 0) +DI_SRC_SEL_IMMEDIATE = enum_pc_di_src_sel.define('DI_SRC_SEL_IMMEDIATE', 1) +DI_SRC_SEL_AUTO_INDEX = enum_pc_di_src_sel.define('DI_SRC_SEL_AUTO_INDEX', 2) +DI_SRC_SEL_AUTO_XFB = enum_pc_di_src_sel.define('DI_SRC_SEL_AUTO_XFB', 3) + +enum_pc_di_face_cull_sel = CEnum(ctypes.c_uint32) +DI_FACE_CULL_NONE = enum_pc_di_face_cull_sel.define('DI_FACE_CULL_NONE', 0) +DI_FACE_CULL_FETCH = enum_pc_di_face_cull_sel.define('DI_FACE_CULL_FETCH', 1) +DI_FACE_BACKFACE_CULL = enum_pc_di_face_cull_sel.define('DI_FACE_BACKFACE_CULL', 2) +DI_FACE_FRONTFACE_CULL = enum_pc_di_face_cull_sel.define('DI_FACE_FRONTFACE_CULL', 3) + +enum_pc_di_index_size = CEnum(ctypes.c_uint32) +INDEX_SIZE_IGN = enum_pc_di_index_size.define('INDEX_SIZE_IGN', 0) +INDEX_SIZE_16_BIT = enum_pc_di_index_size.define('INDEX_SIZE_16_BIT', 0) +INDEX_SIZE_32_BIT = enum_pc_di_index_size.define('INDEX_SIZE_32_BIT', 1) +INDEX_SIZE_8_BIT = enum_pc_di_index_size.define('INDEX_SIZE_8_BIT', 2) +INDEX_SIZE_INVALID = enum_pc_di_index_size.define('INDEX_SIZE_INVALID', 0) + +enum_pc_di_vis_cull_mode = CEnum(ctypes.c_uint32) +IGNORE_VISIBILITY = enum_pc_di_vis_cull_mode.define('IGNORE_VISIBILITY', 0) +USE_VISIBILITY = enum_pc_di_vis_cull_mode.define('USE_VISIBILITY', 1) + +enum_adreno_pm4_packet_type = CEnum(ctypes.c_uint32) +CP_TYPE0_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE0_PKT', 0) +CP_TYPE1_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE1_PKT', 1073741824) +CP_TYPE2_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE2_PKT', 2147483648) +CP_TYPE3_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE3_PKT', 3221225472) +CP_TYPE4_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE4_PKT', 1073741824) +CP_TYPE7_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE7_PKT', 1879048192) + +enum_adreno_pm4_type3_packets = CEnum(ctypes.c_uint32) +CP_ME_INIT = enum_adreno_pm4_type3_packets.define('CP_ME_INIT', 72) +CP_NOP = enum_adreno_pm4_type3_packets.define('CP_NOP', 16) +CP_PREEMPT_ENABLE = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE', 28) +CP_PREEMPT_TOKEN = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_TOKEN', 30) +CP_INDIRECT_BUFFER = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER', 63) +CP_INDIRECT_BUFFER_CHAIN = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_CHAIN', 87) +CP_INDIRECT_BUFFER_PFD = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_PFD', 55) +CP_WAIT_FOR_IDLE = enum_adreno_pm4_type3_packets.define('CP_WAIT_FOR_IDLE', 38) +CP_WAIT_REG_MEM = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_MEM', 60) +CP_WAIT_REG_EQ = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_EQ', 82) +CP_WAIT_REG_GTE = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_GTE', 83) +CP_WAIT_UNTIL_READ = enum_adreno_pm4_type3_packets.define('CP_WAIT_UNTIL_READ', 92) +CP_WAIT_IB_PFD_COMPLETE = enum_adreno_pm4_type3_packets.define('CP_WAIT_IB_PFD_COMPLETE', 93) +CP_REG_RMW = enum_adreno_pm4_type3_packets.define('CP_REG_RMW', 33) +CP_SET_BIN_DATA = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA', 47) +CP_SET_BIN_DATA5 = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA5', 47) +CP_REG_TO_MEM = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM', 62) +CP_MEM_WRITE = enum_adreno_pm4_type3_packets.define('CP_MEM_WRITE', 61) +CP_MEM_WRITE_CNTR = enum_adreno_pm4_type3_packets.define('CP_MEM_WRITE_CNTR', 79) +CP_COND_EXEC = enum_adreno_pm4_type3_packets.define('CP_COND_EXEC', 68) +CP_COND_WRITE = enum_adreno_pm4_type3_packets.define('CP_COND_WRITE', 69) +CP_COND_WRITE5 = enum_adreno_pm4_type3_packets.define('CP_COND_WRITE5', 69) +CP_EVENT_WRITE = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE', 70) +CP_EVENT_WRITE7 = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE7', 70) +CP_EVENT_WRITE_SHD = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_SHD', 88) +CP_EVENT_WRITE_CFL = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_CFL', 89) +CP_EVENT_WRITE_ZPD = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_ZPD', 91) +CP_RUN_OPENCL = enum_adreno_pm4_type3_packets.define('CP_RUN_OPENCL', 49) +CP_DRAW_INDX = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX', 34) +CP_DRAW_INDX_2 = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_2', 54) +CP_DRAW_INDX_BIN = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_BIN', 52) +CP_DRAW_INDX_2_BIN = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_2_BIN', 53) +CP_VIZ_QUERY = enum_adreno_pm4_type3_packets.define('CP_VIZ_QUERY', 35) +CP_SET_STATE = enum_adreno_pm4_type3_packets.define('CP_SET_STATE', 37) +CP_SET_CONSTANT = enum_adreno_pm4_type3_packets.define('CP_SET_CONSTANT', 45) +CP_IM_LOAD = enum_adreno_pm4_type3_packets.define('CP_IM_LOAD', 39) +CP_IM_LOAD_IMMEDIATE = enum_adreno_pm4_type3_packets.define('CP_IM_LOAD_IMMEDIATE', 43) +CP_LOAD_CONSTANT_CONTEXT = enum_adreno_pm4_type3_packets.define('CP_LOAD_CONSTANT_CONTEXT', 46) +CP_INVALIDATE_STATE = enum_adreno_pm4_type3_packets.define('CP_INVALIDATE_STATE', 59) +CP_SET_SHADER_BASES = enum_adreno_pm4_type3_packets.define('CP_SET_SHADER_BASES', 74) +CP_SET_BIN_MASK = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_MASK', 80) +CP_SET_BIN_SELECT = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_SELECT', 81) +CP_CONTEXT_UPDATE = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_UPDATE', 94) +CP_INTERRUPT = enum_adreno_pm4_type3_packets.define('CP_INTERRUPT', 64) +CP_IM_STORE = enum_adreno_pm4_type3_packets.define('CP_IM_STORE', 44) +CP_SET_DRAW_INIT_FLAGS = enum_adreno_pm4_type3_packets.define('CP_SET_DRAW_INIT_FLAGS', 75) +CP_SET_PROTECTED_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_PROTECTED_MODE', 95) +CP_BOOTSTRAP_UCODE = enum_adreno_pm4_type3_packets.define('CP_BOOTSTRAP_UCODE', 111) +CP_LOAD_STATE = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE', 48) +CP_LOAD_STATE4 = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE4', 48) +CP_COND_INDIRECT_BUFFER_PFE = enum_adreno_pm4_type3_packets.define('CP_COND_INDIRECT_BUFFER_PFE', 58) +CP_COND_INDIRECT_BUFFER_PFD = enum_adreno_pm4_type3_packets.define('CP_COND_INDIRECT_BUFFER_PFD', 50) +CP_INDIRECT_BUFFER_PFE = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_PFE', 63) +CP_SET_BIN = enum_adreno_pm4_type3_packets.define('CP_SET_BIN', 76) +CP_TEST_TWO_MEMS = enum_adreno_pm4_type3_packets.define('CP_TEST_TWO_MEMS', 113) +CP_REG_WR_NO_CTXT = enum_adreno_pm4_type3_packets.define('CP_REG_WR_NO_CTXT', 120) +CP_RECORD_PFP_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_RECORD_PFP_TIMESTAMP', 17) +CP_SET_SECURE_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_SECURE_MODE', 102) +CP_WAIT_FOR_ME = enum_adreno_pm4_type3_packets.define('CP_WAIT_FOR_ME', 19) +CP_SET_DRAW_STATE = enum_adreno_pm4_type3_packets.define('CP_SET_DRAW_STATE', 67) +CP_DRAW_INDX_OFFSET = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_OFFSET', 56) +CP_DRAW_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDIRECT', 40) +CP_DRAW_INDX_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_INDIRECT', 41) +CP_DRAW_INDIRECT_MULTI = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDIRECT_MULTI', 42) +CP_DRAW_AUTO = enum_adreno_pm4_type3_packets.define('CP_DRAW_AUTO', 36) +CP_DRAW_PRED_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_ENABLE_GLOBAL', 25) +CP_DRAW_PRED_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_ENABLE_LOCAL', 26) +CP_DRAW_PRED_SET = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_SET', 78) +CP_WIDE_REG_WRITE = enum_adreno_pm4_type3_packets.define('CP_WIDE_REG_WRITE', 116) +CP_SCRATCH_TO_REG = enum_adreno_pm4_type3_packets.define('CP_SCRATCH_TO_REG', 77) +CP_REG_TO_SCRATCH = enum_adreno_pm4_type3_packets.define('CP_REG_TO_SCRATCH', 74) +CP_WAIT_MEM_WRITES = enum_adreno_pm4_type3_packets.define('CP_WAIT_MEM_WRITES', 18) +CP_COND_REG_EXEC = enum_adreno_pm4_type3_packets.define('CP_COND_REG_EXEC', 71) +CP_MEM_TO_REG = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_REG', 66) +CP_EXEC_CS_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_EXEC_CS_INDIRECT', 65) +CP_EXEC_CS = enum_adreno_pm4_type3_packets.define('CP_EXEC_CS', 51) +CP_PERFCOUNTER_ACTION = enum_adreno_pm4_type3_packets.define('CP_PERFCOUNTER_ACTION', 80) +CP_SMMU_TABLE_UPDATE = enum_adreno_pm4_type3_packets.define('CP_SMMU_TABLE_UPDATE', 83) +CP_SET_MARKER = enum_adreno_pm4_type3_packets.define('CP_SET_MARKER', 101) +CP_SET_PSEUDO_REG = enum_adreno_pm4_type3_packets.define('CP_SET_PSEUDO_REG', 86) +CP_CONTEXT_REG_BUNCH = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_REG_BUNCH', 92) +CP_YIELD_ENABLE = enum_adreno_pm4_type3_packets.define('CP_YIELD_ENABLE', 28) +CP_SKIP_IB2_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_SKIP_IB2_ENABLE_GLOBAL', 29) +CP_SKIP_IB2_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_SKIP_IB2_ENABLE_LOCAL', 35) +CP_SET_SUBDRAW_SIZE = enum_adreno_pm4_type3_packets.define('CP_SET_SUBDRAW_SIZE', 53) +CP_WHERE_AM_I = enum_adreno_pm4_type3_packets.define('CP_WHERE_AM_I', 98) +CP_SET_VISIBILITY_OVERRIDE = enum_adreno_pm4_type3_packets.define('CP_SET_VISIBILITY_OVERRIDE', 100) +CP_PREEMPT_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE_GLOBAL', 105) +CP_PREEMPT_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE_LOCAL', 106) +CP_CONTEXT_SWITCH_YIELD = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_SWITCH_YIELD', 107) +CP_SET_RENDER_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_RENDER_MODE', 108) +CP_COMPUTE_CHECKPOINT = enum_adreno_pm4_type3_packets.define('CP_COMPUTE_CHECKPOINT', 110) +CP_MEM_TO_MEM = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_MEM', 115) +CP_BLIT = enum_adreno_pm4_type3_packets.define('CP_BLIT', 44) +CP_REG_TEST = enum_adreno_pm4_type3_packets.define('CP_REG_TEST', 57) +CP_SET_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_MODE', 99) +CP_LOAD_STATE6_GEOM = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6_GEOM', 50) +CP_LOAD_STATE6_FRAG = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6_FRAG', 52) +CP_LOAD_STATE6 = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6', 54) +IN_IB_PREFETCH_END = enum_adreno_pm4_type3_packets.define('IN_IB_PREFETCH_END', 23) +IN_SUBBLK_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_SUBBLK_PREFETCH', 31) +IN_INSTR_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_INSTR_PREFETCH', 32) +IN_INSTR_MATCH = enum_adreno_pm4_type3_packets.define('IN_INSTR_MATCH', 71) +IN_CONST_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_CONST_PREFETCH', 73) +IN_INCR_UPDT_STATE = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_STATE', 85) +IN_INCR_UPDT_CONST = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_CONST', 86) +IN_INCR_UPDT_INSTR = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_INSTR', 87) +PKT4 = enum_adreno_pm4_type3_packets.define('PKT4', 4) +IN_IB_END = enum_adreno_pm4_type3_packets.define('IN_IB_END', 10) +IN_GMU_INTERRUPT = enum_adreno_pm4_type3_packets.define('IN_GMU_INTERRUPT', 11) +IN_PREEMPT = enum_adreno_pm4_type3_packets.define('IN_PREEMPT', 15) +CP_SCRATCH_WRITE = enum_adreno_pm4_type3_packets.define('CP_SCRATCH_WRITE', 76) +CP_REG_TO_MEM_OFFSET_MEM = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM_OFFSET_MEM', 116) +CP_REG_TO_MEM_OFFSET_REG = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM_OFFSET_REG', 114) +CP_WAIT_MEM_GTE = enum_adreno_pm4_type3_packets.define('CP_WAIT_MEM_GTE', 20) +CP_WAIT_TWO_REGS = enum_adreno_pm4_type3_packets.define('CP_WAIT_TWO_REGS', 112) +CP_MEMCPY = enum_adreno_pm4_type3_packets.define('CP_MEMCPY', 117) +CP_SET_BIN_DATA5_OFFSET = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA5_OFFSET', 46) +CP_SET_UNK_BIN_DATA = enum_adreno_pm4_type3_packets.define('CP_SET_UNK_BIN_DATA', 45) +CP_CONTEXT_SWITCH = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_SWITCH', 84) +CP_SET_CTXSWITCH_IB = enum_adreno_pm4_type3_packets.define('CP_SET_CTXSWITCH_IB', 85) +CP_REG_WRITE = enum_adreno_pm4_type3_packets.define('CP_REG_WRITE', 109) +CP_START_BIN = enum_adreno_pm4_type3_packets.define('CP_START_BIN', 80) +CP_END_BIN = enum_adreno_pm4_type3_packets.define('CP_END_BIN', 81) +CP_PREEMPT_DISABLE = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_DISABLE', 108) +CP_WAIT_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_WAIT_TIMESTAMP', 20) +CP_GLOBAL_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_GLOBAL_TIMESTAMP', 21) +CP_LOCAL_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_LOCAL_TIMESTAMP', 22) +CP_THREAD_CONTROL = enum_adreno_pm4_type3_packets.define('CP_THREAD_CONTROL', 23) +CP_RESOURCE_LIST = enum_adreno_pm4_type3_packets.define('CP_RESOURCE_LIST', 24) +CP_BV_BR_COUNT_OPS = enum_adreno_pm4_type3_packets.define('CP_BV_BR_COUNT_OPS', 27) +CP_MODIFY_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_MODIFY_TIMESTAMP', 28) +CP_CONTEXT_REG_BUNCH2 = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_REG_BUNCH2', 93) +CP_MEM_TO_SCRATCH_MEM = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_SCRATCH_MEM', 73) +CP_FIXED_STRIDE_DRAW_TABLE = enum_adreno_pm4_type3_packets.define('CP_FIXED_STRIDE_DRAW_TABLE', 127) +CP_RESET_CONTEXT_STATE = enum_adreno_pm4_type3_packets.define('CP_RESET_CONTEXT_STATE', 31) +CP_CCHE_INVALIDATE = enum_adreno_pm4_type3_packets.define('CP_CCHE_INVALIDATE', 58) + +enum_adreno_state_block = CEnum(ctypes.c_uint32) +SB_VERT_TEX = enum_adreno_state_block.define('SB_VERT_TEX', 0) +SB_VERT_MIPADDR = enum_adreno_state_block.define('SB_VERT_MIPADDR', 1) +SB_FRAG_TEX = enum_adreno_state_block.define('SB_FRAG_TEX', 2) +SB_FRAG_MIPADDR = enum_adreno_state_block.define('SB_FRAG_MIPADDR', 3) +SB_VERT_SHADER = enum_adreno_state_block.define('SB_VERT_SHADER', 4) +SB_GEOM_SHADER = enum_adreno_state_block.define('SB_GEOM_SHADER', 5) +SB_FRAG_SHADER = enum_adreno_state_block.define('SB_FRAG_SHADER', 6) +SB_COMPUTE_SHADER = enum_adreno_state_block.define('SB_COMPUTE_SHADER', 7) + +enum_adreno_state_type = CEnum(ctypes.c_uint32) +ST_SHADER = enum_adreno_state_type.define('ST_SHADER', 0) +ST_CONSTANTS = enum_adreno_state_type.define('ST_CONSTANTS', 1) + +enum_adreno_state_src = CEnum(ctypes.c_uint32) +SS_DIRECT = enum_adreno_state_src.define('SS_DIRECT', 0) +SS_INVALID_ALL_IC = enum_adreno_state_src.define('SS_INVALID_ALL_IC', 2) +SS_INVALID_PART_IC = enum_adreno_state_src.define('SS_INVALID_PART_IC', 3) +SS_INDIRECT = enum_adreno_state_src.define('SS_INDIRECT', 4) +SS_INDIRECT_TCM = enum_adreno_state_src.define('SS_INDIRECT_TCM', 5) +SS_INDIRECT_STM = enum_adreno_state_src.define('SS_INDIRECT_STM', 6) + +enum_a4xx_state_block = CEnum(ctypes.c_uint32) +SB4_VS_TEX = enum_a4xx_state_block.define('SB4_VS_TEX', 0) +SB4_HS_TEX = enum_a4xx_state_block.define('SB4_HS_TEX', 1) +SB4_DS_TEX = enum_a4xx_state_block.define('SB4_DS_TEX', 2) +SB4_GS_TEX = enum_a4xx_state_block.define('SB4_GS_TEX', 3) +SB4_FS_TEX = enum_a4xx_state_block.define('SB4_FS_TEX', 4) +SB4_CS_TEX = enum_a4xx_state_block.define('SB4_CS_TEX', 5) +SB4_VS_SHADER = enum_a4xx_state_block.define('SB4_VS_SHADER', 8) +SB4_HS_SHADER = enum_a4xx_state_block.define('SB4_HS_SHADER', 9) +SB4_DS_SHADER = enum_a4xx_state_block.define('SB4_DS_SHADER', 10) +SB4_GS_SHADER = enum_a4xx_state_block.define('SB4_GS_SHADER', 11) +SB4_FS_SHADER = enum_a4xx_state_block.define('SB4_FS_SHADER', 12) +SB4_CS_SHADER = enum_a4xx_state_block.define('SB4_CS_SHADER', 13) +SB4_SSBO = enum_a4xx_state_block.define('SB4_SSBO', 14) +SB4_CS_SSBO = enum_a4xx_state_block.define('SB4_CS_SSBO', 15) + +enum_a4xx_state_type = CEnum(ctypes.c_uint32) +ST4_SHADER = enum_a4xx_state_type.define('ST4_SHADER', 0) +ST4_CONSTANTS = enum_a4xx_state_type.define('ST4_CONSTANTS', 1) +ST4_UBO = enum_a4xx_state_type.define('ST4_UBO', 2) + +enum_a4xx_state_src = CEnum(ctypes.c_uint32) +SS4_DIRECT = enum_a4xx_state_src.define('SS4_DIRECT', 0) +SS4_INDIRECT = enum_a4xx_state_src.define('SS4_INDIRECT', 2) + +enum_a6xx_state_block = CEnum(ctypes.c_uint32) +SB6_VS_TEX = enum_a6xx_state_block.define('SB6_VS_TEX', 0) +SB6_HS_TEX = enum_a6xx_state_block.define('SB6_HS_TEX', 1) +SB6_DS_TEX = enum_a6xx_state_block.define('SB6_DS_TEX', 2) +SB6_GS_TEX = enum_a6xx_state_block.define('SB6_GS_TEX', 3) +SB6_FS_TEX = enum_a6xx_state_block.define('SB6_FS_TEX', 4) +SB6_CS_TEX = enum_a6xx_state_block.define('SB6_CS_TEX', 5) +SB6_VS_SHADER = enum_a6xx_state_block.define('SB6_VS_SHADER', 8) +SB6_HS_SHADER = enum_a6xx_state_block.define('SB6_HS_SHADER', 9) +SB6_DS_SHADER = enum_a6xx_state_block.define('SB6_DS_SHADER', 10) +SB6_GS_SHADER = enum_a6xx_state_block.define('SB6_GS_SHADER', 11) +SB6_FS_SHADER = enum_a6xx_state_block.define('SB6_FS_SHADER', 12) +SB6_CS_SHADER = enum_a6xx_state_block.define('SB6_CS_SHADER', 13) +SB6_IBO = enum_a6xx_state_block.define('SB6_IBO', 14) +SB6_CS_IBO = enum_a6xx_state_block.define('SB6_CS_IBO', 15) + +enum_a6xx_state_type = CEnum(ctypes.c_uint32) +ST6_SHADER = enum_a6xx_state_type.define('ST6_SHADER', 0) +ST6_CONSTANTS = enum_a6xx_state_type.define('ST6_CONSTANTS', 1) +ST6_UBO = enum_a6xx_state_type.define('ST6_UBO', 2) +ST6_IBO = enum_a6xx_state_type.define('ST6_IBO', 3) + +enum_a6xx_state_src = CEnum(ctypes.c_uint32) +SS6_DIRECT = enum_a6xx_state_src.define('SS6_DIRECT', 0) +SS6_BINDLESS = enum_a6xx_state_src.define('SS6_BINDLESS', 1) +SS6_INDIRECT = enum_a6xx_state_src.define('SS6_INDIRECT', 2) +SS6_UBO = enum_a6xx_state_src.define('SS6_UBO', 3) + +enum_a4xx_index_size = CEnum(ctypes.c_uint32) +INDEX4_SIZE_8_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_8_BIT', 0) +INDEX4_SIZE_16_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_16_BIT', 1) +INDEX4_SIZE_32_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_32_BIT', 2) + +enum_a6xx_patch_type = CEnum(ctypes.c_uint32) +TESS_QUADS = enum_a6xx_patch_type.define('TESS_QUADS', 0) +TESS_TRIANGLES = enum_a6xx_patch_type.define('TESS_TRIANGLES', 1) +TESS_ISOLINES = enum_a6xx_patch_type.define('TESS_ISOLINES', 2) + +enum_a6xx_draw_indirect_opcode = CEnum(ctypes.c_uint32) +INDIRECT_OP_NORMAL = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_NORMAL', 2) +INDIRECT_OP_INDEXED = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDEXED', 4) +INDIRECT_OP_INDIRECT_COUNT = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDIRECT_COUNT', 6) +INDIRECT_OP_INDIRECT_COUNT_INDEXED = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDIRECT_COUNT_INDEXED', 7) + +enum_cp_draw_pred_src = CEnum(ctypes.c_uint32) +PRED_SRC_MEM = enum_cp_draw_pred_src.define('PRED_SRC_MEM', 5) + +enum_cp_draw_pred_test = CEnum(ctypes.c_uint32) +NE_0_PASS = enum_cp_draw_pred_test.define('NE_0_PASS', 0) +EQ_0_PASS = enum_cp_draw_pred_test.define('EQ_0_PASS', 1) + +enum_cp_cond_function = CEnum(ctypes.c_uint32) +WRITE_ALWAYS = enum_cp_cond_function.define('WRITE_ALWAYS', 0) +WRITE_LT = enum_cp_cond_function.define('WRITE_LT', 1) +WRITE_LE = enum_cp_cond_function.define('WRITE_LE', 2) +WRITE_EQ = enum_cp_cond_function.define('WRITE_EQ', 3) +WRITE_NE = enum_cp_cond_function.define('WRITE_NE', 4) +WRITE_GE = enum_cp_cond_function.define('WRITE_GE', 5) +WRITE_GT = enum_cp_cond_function.define('WRITE_GT', 6) + +enum_poll_memory_type = CEnum(ctypes.c_uint32) +POLL_REGISTER = enum_poll_memory_type.define('POLL_REGISTER', 0) +POLL_MEMORY = enum_poll_memory_type.define('POLL_MEMORY', 1) +POLL_SCRATCH = enum_poll_memory_type.define('POLL_SCRATCH', 2) +POLL_ON_CHIP = enum_poll_memory_type.define('POLL_ON_CHIP', 3) + +enum_render_mode_cmd = CEnum(ctypes.c_uint32) +BYPASS = enum_render_mode_cmd.define('BYPASS', 1) +BINNING = enum_render_mode_cmd.define('BINNING', 2) +GMEM = enum_render_mode_cmd.define('GMEM', 3) +BLIT2D = enum_render_mode_cmd.define('BLIT2D', 5) +BLIT2DSCALE = enum_render_mode_cmd.define('BLIT2DSCALE', 7) +END2D = enum_render_mode_cmd.define('END2D', 8) + +enum_event_write_src = CEnum(ctypes.c_uint32) +EV_WRITE_USER_32B = enum_event_write_src.define('EV_WRITE_USER_32B', 0) +EV_WRITE_USER_64B = enum_event_write_src.define('EV_WRITE_USER_64B', 1) +EV_WRITE_TIMESTAMP_SUM = enum_event_write_src.define('EV_WRITE_TIMESTAMP_SUM', 2) +EV_WRITE_ALWAYSON = enum_event_write_src.define('EV_WRITE_ALWAYSON', 3) +EV_WRITE_REGS_CONTENT = enum_event_write_src.define('EV_WRITE_REGS_CONTENT', 4) + +enum_event_write_dst = CEnum(ctypes.c_uint32) +EV_DST_RAM = enum_event_write_dst.define('EV_DST_RAM', 0) +EV_DST_ONCHIP = enum_event_write_dst.define('EV_DST_ONCHIP', 1) + +enum_cp_blit_cmd = CEnum(ctypes.c_uint32) +BLIT_OP_FILL = enum_cp_blit_cmd.define('BLIT_OP_FILL', 0) +BLIT_OP_COPY = enum_cp_blit_cmd.define('BLIT_OP_COPY', 1) +BLIT_OP_SCALE = enum_cp_blit_cmd.define('BLIT_OP_SCALE', 3) + +enum_a6xx_marker = CEnum(ctypes.c_uint32) +RM6_BYPASS = enum_a6xx_marker.define('RM6_BYPASS', 1) +RM6_BINNING = enum_a6xx_marker.define('RM6_BINNING', 2) +RM6_GMEM = enum_a6xx_marker.define('RM6_GMEM', 4) +RM6_ENDVIS = enum_a6xx_marker.define('RM6_ENDVIS', 5) +RM6_RESOLVE = enum_a6xx_marker.define('RM6_RESOLVE', 6) +RM6_YIELD = enum_a6xx_marker.define('RM6_YIELD', 7) +RM6_COMPUTE = enum_a6xx_marker.define('RM6_COMPUTE', 8) +RM6_BLIT2DSCALE = enum_a6xx_marker.define('RM6_BLIT2DSCALE', 12) +RM6_IB1LIST_START = enum_a6xx_marker.define('RM6_IB1LIST_START', 13) +RM6_IB1LIST_END = enum_a6xx_marker.define('RM6_IB1LIST_END', 14) +RM6_IFPC_ENABLE = enum_a6xx_marker.define('RM6_IFPC_ENABLE', 256) +RM6_IFPC_DISABLE = enum_a6xx_marker.define('RM6_IFPC_DISABLE', 257) + +enum_pseudo_reg = CEnum(ctypes.c_uint32) +SMMU_INFO = enum_pseudo_reg.define('SMMU_INFO', 0) +NON_SECURE_SAVE_ADDR = enum_pseudo_reg.define('NON_SECURE_SAVE_ADDR', 1) +SECURE_SAVE_ADDR = enum_pseudo_reg.define('SECURE_SAVE_ADDR', 2) +NON_PRIV_SAVE_ADDR = enum_pseudo_reg.define('NON_PRIV_SAVE_ADDR', 3) +COUNTER = enum_pseudo_reg.define('COUNTER', 4) +DRAW_STRM_ADDRESS = enum_pseudo_reg.define('DRAW_STRM_ADDRESS', 8) +DRAW_STRM_SIZE_ADDRESS = enum_pseudo_reg.define('DRAW_STRM_SIZE_ADDRESS', 9) +PRIM_STRM_ADDRESS = enum_pseudo_reg.define('PRIM_STRM_ADDRESS', 10) +UNK_STRM_ADDRESS = enum_pseudo_reg.define('UNK_STRM_ADDRESS', 11) +UNK_STRM_SIZE_ADDRESS = enum_pseudo_reg.define('UNK_STRM_SIZE_ADDRESS', 12) +BINDLESS_BASE_0_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_0_ADDR', 16) +BINDLESS_BASE_1_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_1_ADDR', 17) +BINDLESS_BASE_2_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_2_ADDR', 18) +BINDLESS_BASE_3_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_3_ADDR', 19) +BINDLESS_BASE_4_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_4_ADDR', 20) +BINDLESS_BASE_5_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_5_ADDR', 21) +BINDLESS_BASE_6_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_6_ADDR', 22) + +enum_source_type = CEnum(ctypes.c_uint32) +SOURCE_REG = enum_source_type.define('SOURCE_REG', 0) +SOURCE_SCRATCH_MEM = enum_source_type.define('SOURCE_SCRATCH_MEM', 1) + +enum_compare_mode = CEnum(ctypes.c_uint32) +PRED_TEST = enum_compare_mode.define('PRED_TEST', 1) +REG_COMPARE = enum_compare_mode.define('REG_COMPARE', 2) +RENDER_MODE = enum_compare_mode.define('RENDER_MODE', 3) +REG_COMPARE_IMM = enum_compare_mode.define('REG_COMPARE_IMM', 4) +THREAD_MODE = enum_compare_mode.define('THREAD_MODE', 5) + +enum_ctxswitch_ib = CEnum(ctypes.c_uint32) +RESTORE_IB = enum_ctxswitch_ib.define('RESTORE_IB', 0) +YIELD_RESTORE_IB = enum_ctxswitch_ib.define('YIELD_RESTORE_IB', 1) +SAVE_IB = enum_ctxswitch_ib.define('SAVE_IB', 2) +RB_SAVE_IB = enum_ctxswitch_ib.define('RB_SAVE_IB', 3) + +enum_reg_tracker = CEnum(ctypes.c_uint32) +TRACK_CNTL_REG = enum_reg_tracker.define('TRACK_CNTL_REG', 1) +TRACK_RENDER_CNTL = enum_reg_tracker.define('TRACK_RENDER_CNTL', 2) +UNK_EVENT_WRITE = enum_reg_tracker.define('UNK_EVENT_WRITE', 4) +TRACK_LRZ = enum_reg_tracker.define('TRACK_LRZ', 8) + +enum_ts_wait_value_src = CEnum(ctypes.c_uint32) +TS_WAIT_GE_32B = enum_ts_wait_value_src.define('TS_WAIT_GE_32B', 0) +TS_WAIT_GE_64B = enum_ts_wait_value_src.define('TS_WAIT_GE_64B', 1) +TS_WAIT_GE_TIMESTAMP_SUM = enum_ts_wait_value_src.define('TS_WAIT_GE_TIMESTAMP_SUM', 2) + +enum_ts_wait_type = CEnum(ctypes.c_uint32) +TS_WAIT_RAM = enum_ts_wait_type.define('TS_WAIT_RAM', 0) +TS_WAIT_ONCHIP = enum_ts_wait_type.define('TS_WAIT_ONCHIP', 1) + +enum_pipe_count_op = CEnum(ctypes.c_uint32) +PIPE_CLEAR_BV_BR = enum_pipe_count_op.define('PIPE_CLEAR_BV_BR', 1) +PIPE_SET_BR_OFFSET = enum_pipe_count_op.define('PIPE_SET_BR_OFFSET', 2) +PIPE_BR_WAIT_FOR_BV = enum_pipe_count_op.define('PIPE_BR_WAIT_FOR_BV', 3) +PIPE_BV_WAIT_FOR_BR = enum_pipe_count_op.define('PIPE_BV_WAIT_FOR_BR', 4) + +enum_timestamp_op = CEnum(ctypes.c_uint32) +MODIFY_TIMESTAMP_CLEAR = enum_timestamp_op.define('MODIFY_TIMESTAMP_CLEAR', 0) +MODIFY_TIMESTAMP_ADD_GLOBAL = enum_timestamp_op.define('MODIFY_TIMESTAMP_ADD_GLOBAL', 1) +MODIFY_TIMESTAMP_ADD_LOCAL = enum_timestamp_op.define('MODIFY_TIMESTAMP_ADD_LOCAL', 2) + +enum_cp_thread = CEnum(ctypes.c_uint32) +CP_SET_THREAD_BR = enum_cp_thread.define('CP_SET_THREAD_BR', 1) +CP_SET_THREAD_BV = enum_cp_thread.define('CP_SET_THREAD_BV', 2) +CP_SET_THREAD_BOTH = enum_cp_thread.define('CP_SET_THREAD_BOTH', 3) + +enum_chip = CEnum(ctypes.c_uint32) +A2XX = enum_chip.define('A2XX', 2) +A3XX = enum_chip.define('A3XX', 3) +A4XX = enum_chip.define('A4XX', 4) +A5XX = enum_chip.define('A5XX', 5) +A6XX = enum_chip.define('A6XX', 6) +A7XX = enum_chip.define('A7XX', 7) + +enum_adreno_pa_su_sc_draw = CEnum(ctypes.c_uint32) +PC_DRAW_POINTS = enum_adreno_pa_su_sc_draw.define('PC_DRAW_POINTS', 0) +PC_DRAW_LINES = enum_adreno_pa_su_sc_draw.define('PC_DRAW_LINES', 1) +PC_DRAW_TRIANGLES = enum_adreno_pa_su_sc_draw.define('PC_DRAW_TRIANGLES', 2) + +enum_adreno_compare_func = CEnum(ctypes.c_uint32) +FUNC_NEVER = enum_adreno_compare_func.define('FUNC_NEVER', 0) +FUNC_LESS = enum_adreno_compare_func.define('FUNC_LESS', 1) +FUNC_EQUAL = enum_adreno_compare_func.define('FUNC_EQUAL', 2) +FUNC_LEQUAL = enum_adreno_compare_func.define('FUNC_LEQUAL', 3) +FUNC_GREATER = enum_adreno_compare_func.define('FUNC_GREATER', 4) +FUNC_NOTEQUAL = enum_adreno_compare_func.define('FUNC_NOTEQUAL', 5) +FUNC_GEQUAL = enum_adreno_compare_func.define('FUNC_GEQUAL', 6) +FUNC_ALWAYS = enum_adreno_compare_func.define('FUNC_ALWAYS', 7) + +enum_adreno_stencil_op = CEnum(ctypes.c_uint32) +STENCIL_KEEP = enum_adreno_stencil_op.define('STENCIL_KEEP', 0) +STENCIL_ZERO = enum_adreno_stencil_op.define('STENCIL_ZERO', 1) +STENCIL_REPLACE = enum_adreno_stencil_op.define('STENCIL_REPLACE', 2) +STENCIL_INCR_CLAMP = enum_adreno_stencil_op.define('STENCIL_INCR_CLAMP', 3) +STENCIL_DECR_CLAMP = enum_adreno_stencil_op.define('STENCIL_DECR_CLAMP', 4) +STENCIL_INVERT = enum_adreno_stencil_op.define('STENCIL_INVERT', 5) +STENCIL_INCR_WRAP = enum_adreno_stencil_op.define('STENCIL_INCR_WRAP', 6) +STENCIL_DECR_WRAP = enum_adreno_stencil_op.define('STENCIL_DECR_WRAP', 7) + +enum_adreno_rb_blend_factor = CEnum(ctypes.c_uint32) +FACTOR_ZERO = enum_adreno_rb_blend_factor.define('FACTOR_ZERO', 0) +FACTOR_ONE = enum_adreno_rb_blend_factor.define('FACTOR_ONE', 1) +FACTOR_SRC_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_SRC_COLOR', 4) +FACTOR_ONE_MINUS_SRC_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC_COLOR', 5) +FACTOR_SRC_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_SRC_ALPHA', 6) +FACTOR_ONE_MINUS_SRC_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC_ALPHA', 7) +FACTOR_DST_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_DST_COLOR', 8) +FACTOR_ONE_MINUS_DST_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_DST_COLOR', 9) +FACTOR_DST_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_DST_ALPHA', 10) +FACTOR_ONE_MINUS_DST_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_DST_ALPHA', 11) +FACTOR_CONSTANT_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_CONSTANT_COLOR', 12) +FACTOR_ONE_MINUS_CONSTANT_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_CONSTANT_COLOR', 13) +FACTOR_CONSTANT_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_CONSTANT_ALPHA', 14) +FACTOR_ONE_MINUS_CONSTANT_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_CONSTANT_ALPHA', 15) +FACTOR_SRC_ALPHA_SATURATE = enum_adreno_rb_blend_factor.define('FACTOR_SRC_ALPHA_SATURATE', 16) +FACTOR_SRC1_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_SRC1_COLOR', 20) +FACTOR_ONE_MINUS_SRC1_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC1_COLOR', 21) +FACTOR_SRC1_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_SRC1_ALPHA', 22) +FACTOR_ONE_MINUS_SRC1_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC1_ALPHA', 23) + +enum_adreno_rb_surface_endian = CEnum(ctypes.c_uint32) +ENDIAN_NONE = enum_adreno_rb_surface_endian.define('ENDIAN_NONE', 0) +ENDIAN_8IN16 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN16', 1) +ENDIAN_8IN32 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN32', 2) +ENDIAN_16IN32 = enum_adreno_rb_surface_endian.define('ENDIAN_16IN32', 3) +ENDIAN_8IN64 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN64', 4) +ENDIAN_8IN128 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN128', 5) + +enum_adreno_rb_dither_mode = CEnum(ctypes.c_uint32) +DITHER_DISABLE = enum_adreno_rb_dither_mode.define('DITHER_DISABLE', 0) +DITHER_ALWAYS = enum_adreno_rb_dither_mode.define('DITHER_ALWAYS', 1) +DITHER_IF_ALPHA_OFF = enum_adreno_rb_dither_mode.define('DITHER_IF_ALPHA_OFF', 2) + +enum_adreno_rb_depth_format = CEnum(ctypes.c_uint32) +DEPTHX_16 = enum_adreno_rb_depth_format.define('DEPTHX_16', 0) +DEPTHX_24_8 = enum_adreno_rb_depth_format.define('DEPTHX_24_8', 1) +DEPTHX_32 = enum_adreno_rb_depth_format.define('DEPTHX_32', 2) + +enum_adreno_rb_copy_control_mode = CEnum(ctypes.c_uint32) +RB_COPY_RESOLVE = enum_adreno_rb_copy_control_mode.define('RB_COPY_RESOLVE', 1) +RB_COPY_CLEAR = enum_adreno_rb_copy_control_mode.define('RB_COPY_CLEAR', 2) +RB_COPY_DEPTH_STENCIL = enum_adreno_rb_copy_control_mode.define('RB_COPY_DEPTH_STENCIL', 5) + +enum_a3xx_rop_code = CEnum(ctypes.c_uint32) +ROP_CLEAR = enum_a3xx_rop_code.define('ROP_CLEAR', 0) +ROP_NOR = enum_a3xx_rop_code.define('ROP_NOR', 1) +ROP_AND_INVERTED = enum_a3xx_rop_code.define('ROP_AND_INVERTED', 2) +ROP_COPY_INVERTED = enum_a3xx_rop_code.define('ROP_COPY_INVERTED', 3) +ROP_AND_REVERSE = enum_a3xx_rop_code.define('ROP_AND_REVERSE', 4) +ROP_INVERT = enum_a3xx_rop_code.define('ROP_INVERT', 5) +ROP_XOR = enum_a3xx_rop_code.define('ROP_XOR', 6) +ROP_NAND = enum_a3xx_rop_code.define('ROP_NAND', 7) +ROP_AND = enum_a3xx_rop_code.define('ROP_AND', 8) +ROP_EQUIV = enum_a3xx_rop_code.define('ROP_EQUIV', 9) +ROP_NOOP = enum_a3xx_rop_code.define('ROP_NOOP', 10) +ROP_OR_INVERTED = enum_a3xx_rop_code.define('ROP_OR_INVERTED', 11) +ROP_COPY = enum_a3xx_rop_code.define('ROP_COPY', 12) +ROP_OR_REVERSE = enum_a3xx_rop_code.define('ROP_OR_REVERSE', 13) +ROP_OR = enum_a3xx_rop_code.define('ROP_OR', 14) +ROP_SET = enum_a3xx_rop_code.define('ROP_SET', 15) + +enum_a3xx_render_mode = CEnum(ctypes.c_uint32) +RB_RENDERING_PASS = enum_a3xx_render_mode.define('RB_RENDERING_PASS', 0) +RB_TILING_PASS = enum_a3xx_render_mode.define('RB_TILING_PASS', 1) +RB_RESOLVE_PASS = enum_a3xx_render_mode.define('RB_RESOLVE_PASS', 2) +RB_COMPUTE_PASS = enum_a3xx_render_mode.define('RB_COMPUTE_PASS', 3) + +enum_a3xx_msaa_samples = CEnum(ctypes.c_uint32) +MSAA_ONE = enum_a3xx_msaa_samples.define('MSAA_ONE', 0) +MSAA_TWO = enum_a3xx_msaa_samples.define('MSAA_TWO', 1) +MSAA_FOUR = enum_a3xx_msaa_samples.define('MSAA_FOUR', 2) +MSAA_EIGHT = enum_a3xx_msaa_samples.define('MSAA_EIGHT', 3) + +enum_a3xx_threadmode = CEnum(ctypes.c_uint32) +MULTI = enum_a3xx_threadmode.define('MULTI', 0) +SINGLE = enum_a3xx_threadmode.define('SINGLE', 1) + +enum_a3xx_instrbuffermode = CEnum(ctypes.c_uint32) +CACHE = enum_a3xx_instrbuffermode.define('CACHE', 0) +BUFFER = enum_a3xx_instrbuffermode.define('BUFFER', 1) + +enum_a3xx_threadsize = CEnum(ctypes.c_uint32) +TWO_QUADS = enum_a3xx_threadsize.define('TWO_QUADS', 0) +FOUR_QUADS = enum_a3xx_threadsize.define('FOUR_QUADS', 1) + +enum_a3xx_color_swap = CEnum(ctypes.c_uint32) +WZYX = enum_a3xx_color_swap.define('WZYX', 0) +WXYZ = enum_a3xx_color_swap.define('WXYZ', 1) +ZYXW = enum_a3xx_color_swap.define('ZYXW', 2) +XYZW = enum_a3xx_color_swap.define('XYZW', 3) + +enum_a3xx_rb_blend_opcode = CEnum(ctypes.c_uint32) +BLEND_DST_PLUS_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_DST_PLUS_SRC', 0) +BLEND_SRC_MINUS_DST = enum_a3xx_rb_blend_opcode.define('BLEND_SRC_MINUS_DST', 1) +BLEND_DST_MINUS_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_DST_MINUS_SRC', 2) +BLEND_MIN_DST_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_MIN_DST_SRC', 3) +BLEND_MAX_DST_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_MAX_DST_SRC', 4) + +enum_a4xx_tess_spacing = CEnum(ctypes.c_uint32) +EQUAL_SPACING = enum_a4xx_tess_spacing.define('EQUAL_SPACING', 0) +ODD_SPACING = enum_a4xx_tess_spacing.define('ODD_SPACING', 2) +EVEN_SPACING = enum_a4xx_tess_spacing.define('EVEN_SPACING', 3) + +enum_a5xx_address_mode = CEnum(ctypes.c_uint32) +ADDR_32B = enum_a5xx_address_mode.define('ADDR_32B', 0) +ADDR_64B = enum_a5xx_address_mode.define('ADDR_64B', 1) + +enum_a5xx_line_mode = CEnum(ctypes.c_uint32) +BRESENHAM = enum_a5xx_line_mode.define('BRESENHAM', 0) +RECTANGULAR = enum_a5xx_line_mode.define('RECTANGULAR', 1) + +enum_a6xx_tex_prefetch_cmd = CEnum(ctypes.c_uint32) +TEX_PREFETCH_UNK0 = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_UNK0', 0) +TEX_PREFETCH_SAM = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_SAM', 1) +TEX_PREFETCH_GATHER4R = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4R', 2) +TEX_PREFETCH_GATHER4G = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4G', 3) +TEX_PREFETCH_GATHER4B = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4B', 4) +TEX_PREFETCH_GATHER4A = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4A', 5) +TEX_PREFETCH_UNK6 = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_UNK6', 6) +TEX_PREFETCH_UNK7 = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_UNK7', 7) + +enum_a6xx_tile_mode = CEnum(ctypes.c_uint32) +TILE6_LINEAR = enum_a6xx_tile_mode.define('TILE6_LINEAR', 0) +TILE6_2 = enum_a6xx_tile_mode.define('TILE6_2', 2) +TILE6_3 = enum_a6xx_tile_mode.define('TILE6_3', 3) + +enum_a6xx_format = CEnum(ctypes.c_uint32) +FMT6_A8_UNORM = enum_a6xx_format.define('FMT6_A8_UNORM', 2) +FMT6_8_UNORM = enum_a6xx_format.define('FMT6_8_UNORM', 3) +FMT6_8_SNORM = enum_a6xx_format.define('FMT6_8_SNORM', 4) +FMT6_8_UINT = enum_a6xx_format.define('FMT6_8_UINT', 5) +FMT6_8_SINT = enum_a6xx_format.define('FMT6_8_SINT', 6) +FMT6_4_4_4_4_UNORM = enum_a6xx_format.define('FMT6_4_4_4_4_UNORM', 8) +FMT6_5_5_5_1_UNORM = enum_a6xx_format.define('FMT6_5_5_5_1_UNORM', 10) +FMT6_1_5_5_5_UNORM = enum_a6xx_format.define('FMT6_1_5_5_5_UNORM', 12) +FMT6_5_6_5_UNORM = enum_a6xx_format.define('FMT6_5_6_5_UNORM', 14) +FMT6_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_UNORM', 15) +FMT6_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_SNORM', 16) +FMT6_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_UINT', 17) +FMT6_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_SINT', 18) +FMT6_L8_A8_UNORM = enum_a6xx_format.define('FMT6_L8_A8_UNORM', 19) +FMT6_16_UNORM = enum_a6xx_format.define('FMT6_16_UNORM', 21) +FMT6_16_SNORM = enum_a6xx_format.define('FMT6_16_SNORM', 22) +FMT6_16_FLOAT = enum_a6xx_format.define('FMT6_16_FLOAT', 23) +FMT6_16_UINT = enum_a6xx_format.define('FMT6_16_UINT', 24) +FMT6_16_SINT = enum_a6xx_format.define('FMT6_16_SINT', 25) +FMT6_8_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_UNORM', 33) +FMT6_8_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_8_SNORM', 34) +FMT6_8_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_8_UINT', 35) +FMT6_8_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_8_SINT', 36) +FMT6_8_8_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_8_UNORM', 48) +FMT6_8_8_8_X8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_X8_UNORM', 49) +FMT6_8_8_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_8_8_SNORM', 50) +FMT6_8_8_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_8_8_UINT', 51) +FMT6_8_8_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_8_8_SINT', 52) +FMT6_9_9_9_E5_FLOAT = enum_a6xx_format.define('FMT6_9_9_9_E5_FLOAT', 53) +FMT6_10_10_10_2_UNORM = enum_a6xx_format.define('FMT6_10_10_10_2_UNORM', 54) +FMT6_10_10_10_2_UNORM_DEST = enum_a6xx_format.define('FMT6_10_10_10_2_UNORM_DEST', 55) +FMT6_10_10_10_2_SNORM = enum_a6xx_format.define('FMT6_10_10_10_2_SNORM', 57) +FMT6_10_10_10_2_UINT = enum_a6xx_format.define('FMT6_10_10_10_2_UINT', 58) +FMT6_10_10_10_2_SINT = enum_a6xx_format.define('FMT6_10_10_10_2_SINT', 59) +FMT6_11_11_10_FLOAT = enum_a6xx_format.define('FMT6_11_11_10_FLOAT', 66) +FMT6_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_UNORM', 67) +FMT6_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_SNORM', 68) +FMT6_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_FLOAT', 69) +FMT6_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_UINT', 70) +FMT6_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_SINT', 71) +FMT6_32_UNORM = enum_a6xx_format.define('FMT6_32_UNORM', 72) +FMT6_32_SNORM = enum_a6xx_format.define('FMT6_32_SNORM', 73) +FMT6_32_FLOAT = enum_a6xx_format.define('FMT6_32_FLOAT', 74) +FMT6_32_UINT = enum_a6xx_format.define('FMT6_32_UINT', 75) +FMT6_32_SINT = enum_a6xx_format.define('FMT6_32_SINT', 76) +FMT6_32_FIXED = enum_a6xx_format.define('FMT6_32_FIXED', 77) +FMT6_16_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_16_UNORM', 88) +FMT6_16_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_16_SNORM', 89) +FMT6_16_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_16_FLOAT', 90) +FMT6_16_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_16_UINT', 91) +FMT6_16_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_16_SINT', 92) +FMT6_16_16_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_16_16_UNORM', 96) +FMT6_16_16_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_16_16_SNORM', 97) +FMT6_16_16_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_16_16_FLOAT', 98) +FMT6_16_16_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_16_16_UINT', 99) +FMT6_16_16_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_16_16_SINT', 100) +FMT6_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_UNORM', 101) +FMT6_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_SNORM', 102) +FMT6_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_FLOAT', 103) +FMT6_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_UINT', 104) +FMT6_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_SINT', 105) +FMT6_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_FIXED', 106) +FMT6_32_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_32_UNORM', 112) +FMT6_32_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_32_SNORM', 113) +FMT6_32_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_32_UINT', 114) +FMT6_32_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_32_SINT', 115) +FMT6_32_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_32_FLOAT', 116) +FMT6_32_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_32_FIXED', 117) +FMT6_32_32_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_32_32_UNORM', 128) +FMT6_32_32_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_32_32_SNORM', 129) +FMT6_32_32_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_32_32_FLOAT', 130) +FMT6_32_32_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_32_32_UINT', 131) +FMT6_32_32_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_32_32_SINT', 132) +FMT6_32_32_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_32_32_FIXED', 133) +FMT6_G8R8B8R8_422_UNORM = enum_a6xx_format.define('FMT6_G8R8B8R8_422_UNORM', 140) +FMT6_R8G8R8B8_422_UNORM = enum_a6xx_format.define('FMT6_R8G8R8B8_422_UNORM', 141) +FMT6_R8_G8B8_2PLANE_420_UNORM = enum_a6xx_format.define('FMT6_R8_G8B8_2PLANE_420_UNORM', 142) +FMT6_NV21 = enum_a6xx_format.define('FMT6_NV21', 143) +FMT6_R8_G8_B8_3PLANE_420_UNORM = enum_a6xx_format.define('FMT6_R8_G8_B8_3PLANE_420_UNORM', 144) +FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = enum_a6xx_format.define('FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 145) +FMT6_NV12_Y = enum_a6xx_format.define('FMT6_NV12_Y', 148) +FMT6_NV12_UV = enum_a6xx_format.define('FMT6_NV12_UV', 149) +FMT6_NV12_VU = enum_a6xx_format.define('FMT6_NV12_VU', 150) +FMT6_NV12_4R = enum_a6xx_format.define('FMT6_NV12_4R', 151) +FMT6_NV12_4R_Y = enum_a6xx_format.define('FMT6_NV12_4R_Y', 152) +FMT6_NV12_4R_UV = enum_a6xx_format.define('FMT6_NV12_4R_UV', 153) +FMT6_P010 = enum_a6xx_format.define('FMT6_P010', 154) +FMT6_P010_Y = enum_a6xx_format.define('FMT6_P010_Y', 155) +FMT6_P010_UV = enum_a6xx_format.define('FMT6_P010_UV', 156) +FMT6_TP10 = enum_a6xx_format.define('FMT6_TP10', 157) +FMT6_TP10_Y = enum_a6xx_format.define('FMT6_TP10_Y', 158) +FMT6_TP10_UV = enum_a6xx_format.define('FMT6_TP10_UV', 159) +FMT6_Z24_UNORM_S8_UINT = enum_a6xx_format.define('FMT6_Z24_UNORM_S8_UINT', 160) +FMT6_ETC2_RG11_UNORM = enum_a6xx_format.define('FMT6_ETC2_RG11_UNORM', 171) +FMT6_ETC2_RG11_SNORM = enum_a6xx_format.define('FMT6_ETC2_RG11_SNORM', 172) +FMT6_ETC2_R11_UNORM = enum_a6xx_format.define('FMT6_ETC2_R11_UNORM', 173) +FMT6_ETC2_R11_SNORM = enum_a6xx_format.define('FMT6_ETC2_R11_SNORM', 174) +FMT6_ETC1 = enum_a6xx_format.define('FMT6_ETC1', 175) +FMT6_ETC2_RGB8 = enum_a6xx_format.define('FMT6_ETC2_RGB8', 176) +FMT6_ETC2_RGBA8 = enum_a6xx_format.define('FMT6_ETC2_RGBA8', 177) +FMT6_ETC2_RGB8A1 = enum_a6xx_format.define('FMT6_ETC2_RGB8A1', 178) +FMT6_DXT1 = enum_a6xx_format.define('FMT6_DXT1', 179) +FMT6_DXT3 = enum_a6xx_format.define('FMT6_DXT3', 180) +FMT6_DXT5 = enum_a6xx_format.define('FMT6_DXT5', 181) +FMT6_RGTC1_UNORM = enum_a6xx_format.define('FMT6_RGTC1_UNORM', 183) +FMT6_RGTC1_SNORM = enum_a6xx_format.define('FMT6_RGTC1_SNORM', 184) +FMT6_RGTC2_UNORM = enum_a6xx_format.define('FMT6_RGTC2_UNORM', 187) +FMT6_RGTC2_SNORM = enum_a6xx_format.define('FMT6_RGTC2_SNORM', 188) +FMT6_BPTC_UFLOAT = enum_a6xx_format.define('FMT6_BPTC_UFLOAT', 190) +FMT6_BPTC_FLOAT = enum_a6xx_format.define('FMT6_BPTC_FLOAT', 191) +FMT6_BPTC = enum_a6xx_format.define('FMT6_BPTC', 192) +FMT6_ASTC_4x4 = enum_a6xx_format.define('FMT6_ASTC_4x4', 193) +FMT6_ASTC_5x4 = enum_a6xx_format.define('FMT6_ASTC_5x4', 194) +FMT6_ASTC_5x5 = enum_a6xx_format.define('FMT6_ASTC_5x5', 195) +FMT6_ASTC_6x5 = enum_a6xx_format.define('FMT6_ASTC_6x5', 196) +FMT6_ASTC_6x6 = enum_a6xx_format.define('FMT6_ASTC_6x6', 197) +FMT6_ASTC_8x5 = enum_a6xx_format.define('FMT6_ASTC_8x5', 198) +FMT6_ASTC_8x6 = enum_a6xx_format.define('FMT6_ASTC_8x6', 199) +FMT6_ASTC_8x8 = enum_a6xx_format.define('FMT6_ASTC_8x8', 200) +FMT6_ASTC_10x5 = enum_a6xx_format.define('FMT6_ASTC_10x5', 201) +FMT6_ASTC_10x6 = enum_a6xx_format.define('FMT6_ASTC_10x6', 202) +FMT6_ASTC_10x8 = enum_a6xx_format.define('FMT6_ASTC_10x8', 203) +FMT6_ASTC_10x10 = enum_a6xx_format.define('FMT6_ASTC_10x10', 204) +FMT6_ASTC_12x10 = enum_a6xx_format.define('FMT6_ASTC_12x10', 205) +FMT6_ASTC_12x12 = enum_a6xx_format.define('FMT6_ASTC_12x12', 206) +FMT6_Z24_UINT_S8_UINT = enum_a6xx_format.define('FMT6_Z24_UINT_S8_UINT', 234) +FMT6_NONE = enum_a6xx_format.define('FMT6_NONE', 255) + +enum_a6xx_polygon_mode = CEnum(ctypes.c_uint32) +POLYMODE6_POINTS = enum_a6xx_polygon_mode.define('POLYMODE6_POINTS', 1) +POLYMODE6_LINES = enum_a6xx_polygon_mode.define('POLYMODE6_LINES', 2) +POLYMODE6_TRIANGLES = enum_a6xx_polygon_mode.define('POLYMODE6_TRIANGLES', 3) + +enum_a6xx_depth_format = CEnum(ctypes.c_uint32) +DEPTH6_NONE = enum_a6xx_depth_format.define('DEPTH6_NONE', 0) +DEPTH6_16 = enum_a6xx_depth_format.define('DEPTH6_16', 1) +DEPTH6_24_8 = enum_a6xx_depth_format.define('DEPTH6_24_8', 2) +DEPTH6_32 = enum_a6xx_depth_format.define('DEPTH6_32', 4) + +enum_a6xx_shader_id = CEnum(ctypes.c_uint32) +A6XX_TP0_TMO_DATA = enum_a6xx_shader_id.define('A6XX_TP0_TMO_DATA', 9) +A6XX_TP0_SMO_DATA = enum_a6xx_shader_id.define('A6XX_TP0_SMO_DATA', 10) +A6XX_TP0_MIPMAP_BASE_DATA = enum_a6xx_shader_id.define('A6XX_TP0_MIPMAP_BASE_DATA', 11) +A6XX_TP1_TMO_DATA = enum_a6xx_shader_id.define('A6XX_TP1_TMO_DATA', 25) +A6XX_TP1_SMO_DATA = enum_a6xx_shader_id.define('A6XX_TP1_SMO_DATA', 26) +A6XX_TP1_MIPMAP_BASE_DATA = enum_a6xx_shader_id.define('A6XX_TP1_MIPMAP_BASE_DATA', 27) +A6XX_SP_INST_DATA = enum_a6xx_shader_id.define('A6XX_SP_INST_DATA', 41) +A6XX_SP_LB_0_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_0_DATA', 42) +A6XX_SP_LB_1_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_1_DATA', 43) +A6XX_SP_LB_2_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_2_DATA', 44) +A6XX_SP_LB_3_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_3_DATA', 45) +A6XX_SP_LB_4_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_4_DATA', 46) +A6XX_SP_LB_5_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_5_DATA', 47) +A6XX_SP_CB_BINDLESS_DATA = enum_a6xx_shader_id.define('A6XX_SP_CB_BINDLESS_DATA', 48) +A6XX_SP_CB_LEGACY_DATA = enum_a6xx_shader_id.define('A6XX_SP_CB_LEGACY_DATA', 49) +A6XX_SP_UAV_DATA = enum_a6xx_shader_id.define('A6XX_SP_UAV_DATA', 50) +A6XX_SP_INST_TAG = enum_a6xx_shader_id.define('A6XX_SP_INST_TAG', 51) +A6XX_SP_CB_BINDLESS_TAG = enum_a6xx_shader_id.define('A6XX_SP_CB_BINDLESS_TAG', 52) +A6XX_SP_TMO_UMO_TAG = enum_a6xx_shader_id.define('A6XX_SP_TMO_UMO_TAG', 53) +A6XX_SP_SMO_TAG = enum_a6xx_shader_id.define('A6XX_SP_SMO_TAG', 54) +A6XX_SP_STATE_DATA = enum_a6xx_shader_id.define('A6XX_SP_STATE_DATA', 55) +A6XX_HLSQ_CHUNK_CVS_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CVS_RAM', 73) +A6XX_HLSQ_CHUNK_CPS_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CPS_RAM', 74) +A6XX_HLSQ_CHUNK_CVS_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CVS_RAM_TAG', 75) +A6XX_HLSQ_CHUNK_CPS_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CPS_RAM_TAG', 76) +A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', 77) +A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', 78) +A6XX_HLSQ_CVS_MISC_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CVS_MISC_RAM', 80) +A6XX_HLSQ_CPS_MISC_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CPS_MISC_RAM', 81) +A6XX_HLSQ_INST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM', 82) +A6XX_HLSQ_GFX_CVS_CONST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CVS_CONST_RAM', 83) +A6XX_HLSQ_GFX_CPS_CONST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CPS_CONST_RAM', 84) +A6XX_HLSQ_CVS_MISC_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CVS_MISC_RAM_TAG', 85) +A6XX_HLSQ_CPS_MISC_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CPS_MISC_RAM_TAG', 86) +A6XX_HLSQ_INST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM_TAG', 87) +A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', 88) +A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', 89) +A6XX_HLSQ_PWR_REST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_PWR_REST_RAM', 90) +A6XX_HLSQ_PWR_REST_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_PWR_REST_TAG', 91) +A6XX_HLSQ_DATAPATH_META = enum_a6xx_shader_id.define('A6XX_HLSQ_DATAPATH_META', 96) +A6XX_HLSQ_FRONTEND_META = enum_a6xx_shader_id.define('A6XX_HLSQ_FRONTEND_META', 97) +A6XX_HLSQ_INDIRECT_META = enum_a6xx_shader_id.define('A6XX_HLSQ_INDIRECT_META', 98) +A6XX_HLSQ_BACKEND_META = enum_a6xx_shader_id.define('A6XX_HLSQ_BACKEND_META', 99) +A6XX_SP_LB_6_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_6_DATA', 112) +A6XX_SP_LB_7_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_7_DATA', 113) +A6XX_HLSQ_INST_RAM_1 = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM_1', 115) + +enum_a7xx_statetype_id = CEnum(ctypes.c_uint32) +A7XX_TP0_NCTX_REG = enum_a7xx_statetype_id.define('A7XX_TP0_NCTX_REG', 0) +A7XX_TP0_CTX0_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX0_3D_CVS_REG', 1) +A7XX_TP0_CTX0_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX0_3D_CPS_REG', 2) +A7XX_TP0_CTX1_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX1_3D_CVS_REG', 3) +A7XX_TP0_CTX1_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX1_3D_CPS_REG', 4) +A7XX_TP0_CTX2_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX2_3D_CPS_REG', 5) +A7XX_TP0_CTX3_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX3_3D_CPS_REG', 6) +A7XX_TP0_TMO_DATA = enum_a7xx_statetype_id.define('A7XX_TP0_TMO_DATA', 9) +A7XX_TP0_SMO_DATA = enum_a7xx_statetype_id.define('A7XX_TP0_SMO_DATA', 10) +A7XX_TP0_MIPMAP_BASE_DATA = enum_a7xx_statetype_id.define('A7XX_TP0_MIPMAP_BASE_DATA', 11) +A7XX_SP_NCTX_REG = enum_a7xx_statetype_id.define('A7XX_SP_NCTX_REG', 32) +A7XX_SP_CTX0_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX0_3D_CVS_REG', 33) +A7XX_SP_CTX0_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX0_3D_CPS_REG', 34) +A7XX_SP_CTX1_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX1_3D_CVS_REG', 35) +A7XX_SP_CTX1_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX1_3D_CPS_REG', 36) +A7XX_SP_CTX2_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX2_3D_CPS_REG', 37) +A7XX_SP_CTX3_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX3_3D_CPS_REG', 38) +A7XX_SP_INST_DATA = enum_a7xx_statetype_id.define('A7XX_SP_INST_DATA', 39) +A7XX_SP_INST_DATA_1 = enum_a7xx_statetype_id.define('A7XX_SP_INST_DATA_1', 40) +A7XX_SP_LB_0_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_0_DATA', 41) +A7XX_SP_LB_1_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_1_DATA', 42) +A7XX_SP_LB_2_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_2_DATA', 43) +A7XX_SP_LB_3_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_3_DATA', 44) +A7XX_SP_LB_4_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_4_DATA', 45) +A7XX_SP_LB_5_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_5_DATA', 46) +A7XX_SP_LB_6_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_6_DATA', 47) +A7XX_SP_LB_7_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_7_DATA', 48) +A7XX_SP_CB_RAM = enum_a7xx_statetype_id.define('A7XX_SP_CB_RAM', 49) +A7XX_SP_LB_13_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_13_DATA', 50) +A7XX_SP_LB_14_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_14_DATA', 51) +A7XX_SP_INST_TAG = enum_a7xx_statetype_id.define('A7XX_SP_INST_TAG', 52) +A7XX_SP_INST_DATA_2 = enum_a7xx_statetype_id.define('A7XX_SP_INST_DATA_2', 53) +A7XX_SP_TMO_TAG = enum_a7xx_statetype_id.define('A7XX_SP_TMO_TAG', 54) +A7XX_SP_SMO_TAG = enum_a7xx_statetype_id.define('A7XX_SP_SMO_TAG', 55) +A7XX_SP_STATE_DATA = enum_a7xx_statetype_id.define('A7XX_SP_STATE_DATA', 56) +A7XX_SP_HWAVE_RAM = enum_a7xx_statetype_id.define('A7XX_SP_HWAVE_RAM', 57) +A7XX_SP_L0_INST_BUF = enum_a7xx_statetype_id.define('A7XX_SP_L0_INST_BUF', 58) +A7XX_SP_LB_8_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_8_DATA', 59) +A7XX_SP_LB_9_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_9_DATA', 60) +A7XX_SP_LB_10_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_10_DATA', 61) +A7XX_SP_LB_11_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_11_DATA', 62) +A7XX_SP_LB_12_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_12_DATA', 63) +A7XX_HLSQ_DATAPATH_DSTR_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_DATAPATH_DSTR_META', 64) +A7XX_HLSQ_L2STC_TAG_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_L2STC_TAG_RAM', 67) +A7XX_HLSQ_L2STC_INFO_CMD = enum_a7xx_statetype_id.define('A7XX_HLSQ_L2STC_INFO_CMD', 68) +A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', 69) +A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', 70) +A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM', 71) +A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM', 72) +A7XX_HLSQ_CHUNK_CVS_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CVS_RAM', 73) +A7XX_HLSQ_CHUNK_CPS_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CPS_RAM', 74) +A7XX_HLSQ_CHUNK_CVS_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CVS_RAM_TAG', 75) +A7XX_HLSQ_CHUNK_CPS_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CPS_RAM_TAG', 76) +A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_ICB_CVS_CB_BASE_TAG', 77) +A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', 78) +A7XX_HLSQ_CVS_MISC_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CVS_MISC_RAM', 79) +A7XX_HLSQ_CPS_MISC_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_MISC_RAM', 80) +A7XX_HLSQ_CPS_MISC_RAM_1 = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_MISC_RAM_1', 81) +A7XX_HLSQ_INST_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM', 82) +A7XX_HLSQ_GFX_CVS_CONST_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CVS_CONST_RAM', 83) +A7XX_HLSQ_GFX_CPS_CONST_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CPS_CONST_RAM', 84) +A7XX_HLSQ_CVS_MISC_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CVS_MISC_RAM_TAG', 85) +A7XX_HLSQ_CPS_MISC_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_MISC_RAM_TAG', 86) +A7XX_HLSQ_INST_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM_TAG', 87) +A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG', 88) +A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG', 89) +A7XX_HLSQ_GFX_LOCAL_MISC_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_LOCAL_MISC_RAM', 90) +A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG', 91) +A7XX_HLSQ_INST_RAM_1 = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM_1', 92) +A7XX_HLSQ_STPROC_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_STPROC_META', 93) +A7XX_HLSQ_BV_BE_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_BV_BE_META', 94) +A7XX_HLSQ_INST_RAM_2 = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM_2', 95) +A7XX_HLSQ_DATAPATH_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_DATAPATH_META', 96) +A7XX_HLSQ_FRONTEND_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_FRONTEND_META', 97) +A7XX_HLSQ_INDIRECT_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_INDIRECT_META', 98) +A7XX_HLSQ_BACKEND_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_BACKEND_META', 99) + +enum_a6xx_debugbus_id = CEnum(ctypes.c_uint32) +A6XX_DBGBUS_CP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CP', 1) +A6XX_DBGBUS_RBBM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RBBM', 2) +A6XX_DBGBUS_VBIF = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VBIF', 3) +A6XX_DBGBUS_HLSQ = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_HLSQ', 4) +A6XX_DBGBUS_UCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_UCHE', 5) +A6XX_DBGBUS_DPM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DPM', 6) +A6XX_DBGBUS_TESS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TESS', 7) +A6XX_DBGBUS_PC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_PC', 8) +A6XX_DBGBUS_VFDP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFDP', 9) +A6XX_DBGBUS_VPC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VPC', 10) +A6XX_DBGBUS_TSE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TSE', 11) +A6XX_DBGBUS_RAS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RAS', 12) +A6XX_DBGBUS_VSC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VSC', 13) +A6XX_DBGBUS_COM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_COM', 14) +A6XX_DBGBUS_LRZ = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_LRZ', 16) +A6XX_DBGBUS_A2D = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_A2D', 17) +A6XX_DBGBUS_CCUFCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCUFCHE', 18) +A6XX_DBGBUS_GMU_CX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GMU_CX', 19) +A6XX_DBGBUS_RBP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RBP', 20) +A6XX_DBGBUS_DCS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DCS', 21) +A6XX_DBGBUS_DBGC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DBGC', 22) +A6XX_DBGBUS_CX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CX', 23) +A6XX_DBGBUS_GMU_GX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GMU_GX', 24) +A6XX_DBGBUS_TPFCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPFCHE', 25) +A6XX_DBGBUS_GBIF_GX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GBIF_GX', 26) +A6XX_DBGBUS_GPC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GPC', 29) +A6XX_DBGBUS_LARC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_LARC', 30) +A6XX_DBGBUS_HLSQ_SPTP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_HLSQ_SPTP', 31) +A6XX_DBGBUS_RB_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_0', 32) +A6XX_DBGBUS_RB_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_1', 33) +A6XX_DBGBUS_RB_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_2', 34) +A6XX_DBGBUS_UCHE_WRAPPER = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_UCHE_WRAPPER', 36) +A6XX_DBGBUS_CCU_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_0', 40) +A6XX_DBGBUS_CCU_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_1', 41) +A6XX_DBGBUS_CCU_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_2', 42) +A6XX_DBGBUS_VFD_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_0', 56) +A6XX_DBGBUS_VFD_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_1', 57) +A6XX_DBGBUS_VFD_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_2', 58) +A6XX_DBGBUS_VFD_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_3', 59) +A6XX_DBGBUS_VFD_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_4', 60) +A6XX_DBGBUS_VFD_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_5', 61) +A6XX_DBGBUS_SP_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_0', 64) +A6XX_DBGBUS_SP_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_1', 65) +A6XX_DBGBUS_SP_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_2', 66) +A6XX_DBGBUS_TPL1_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_0', 72) +A6XX_DBGBUS_TPL1_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_1', 73) +A6XX_DBGBUS_TPL1_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_2', 74) +A6XX_DBGBUS_TPL1_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_3', 75) +A6XX_DBGBUS_TPL1_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_4', 76) +A6XX_DBGBUS_TPL1_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_5', 77) +A6XX_DBGBUS_SPTP_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_0', 88) +A6XX_DBGBUS_SPTP_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_1', 89) +A6XX_DBGBUS_SPTP_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_2', 90) +A6XX_DBGBUS_SPTP_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_3', 91) +A6XX_DBGBUS_SPTP_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_4', 92) +A6XX_DBGBUS_SPTP_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_5', 93) + +enum_a7xx_state_location = CEnum(ctypes.c_uint32) +A7XX_HLSQ_STATE = enum_a7xx_state_location.define('A7XX_HLSQ_STATE', 0) +A7XX_HLSQ_DP = enum_a7xx_state_location.define('A7XX_HLSQ_DP', 1) +A7XX_SP_TOP = enum_a7xx_state_location.define('A7XX_SP_TOP', 2) +A7XX_USPTP = enum_a7xx_state_location.define('A7XX_USPTP', 3) +A7XX_HLSQ_DP_STR = enum_a7xx_state_location.define('A7XX_HLSQ_DP_STR', 4) + +enum_a7xx_pipe = CEnum(ctypes.c_uint32) +A7XX_PIPE_NONE = enum_a7xx_pipe.define('A7XX_PIPE_NONE', 0) +A7XX_PIPE_BR = enum_a7xx_pipe.define('A7XX_PIPE_BR', 1) +A7XX_PIPE_BV = enum_a7xx_pipe.define('A7XX_PIPE_BV', 2) +A7XX_PIPE_LPAC = enum_a7xx_pipe.define('A7XX_PIPE_LPAC', 3) + +enum_a7xx_cluster = CEnum(ctypes.c_uint32) +A7XX_CLUSTER_NONE = enum_a7xx_cluster.define('A7XX_CLUSTER_NONE', 0) +A7XX_CLUSTER_FE = enum_a7xx_cluster.define('A7XX_CLUSTER_FE', 1) +A7XX_CLUSTER_SP_VS = enum_a7xx_cluster.define('A7XX_CLUSTER_SP_VS', 2) +A7XX_CLUSTER_PC_VS = enum_a7xx_cluster.define('A7XX_CLUSTER_PC_VS', 3) +A7XX_CLUSTER_GRAS = enum_a7xx_cluster.define('A7XX_CLUSTER_GRAS', 4) +A7XX_CLUSTER_SP_PS = enum_a7xx_cluster.define('A7XX_CLUSTER_SP_PS', 5) +A7XX_CLUSTER_VPC_PS = enum_a7xx_cluster.define('A7XX_CLUSTER_VPC_PS', 6) +A7XX_CLUSTER_PS = enum_a7xx_cluster.define('A7XX_CLUSTER_PS', 7) + +enum_a7xx_debugbus_id = CEnum(ctypes.c_uint32) +A7XX_DBGBUS_CP_0_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CP_0_0', 1) +A7XX_DBGBUS_CP_0_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CP_0_1', 2) +A7XX_DBGBUS_RBBM = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RBBM', 3) +A7XX_DBGBUS_GBIF_GX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GBIF_GX', 5) +A7XX_DBGBUS_GBIF_CX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GBIF_CX', 6) +A7XX_DBGBUS_HLSQ = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ', 7) +A7XX_DBGBUS_UCHE_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UCHE_0', 9) +A7XX_DBGBUS_UCHE_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UCHE_1', 10) +A7XX_DBGBUS_TESS_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TESS_BR', 13) +A7XX_DBGBUS_TESS_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TESS_BV', 14) +A7XX_DBGBUS_PC_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_PC_BR', 17) +A7XX_DBGBUS_PC_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_PC_BV', 18) +A7XX_DBGBUS_VFDP_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFDP_BR', 21) +A7XX_DBGBUS_VFDP_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFDP_BV', 22) +A7XX_DBGBUS_VPC_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_BR', 25) +A7XX_DBGBUS_VPC_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_BV', 26) +A7XX_DBGBUS_TSE_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TSE_BR', 29) +A7XX_DBGBUS_TSE_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TSE_BV', 30) +A7XX_DBGBUS_RAS_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RAS_BR', 33) +A7XX_DBGBUS_RAS_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RAS_BV', 34) +A7XX_DBGBUS_VSC = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VSC', 37) +A7XX_DBGBUS_COM_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_COM_0', 39) +A7XX_DBGBUS_LRZ_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_LRZ_BR', 43) +A7XX_DBGBUS_LRZ_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_LRZ_BV', 44) +A7XX_DBGBUS_UFC_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_0', 47) +A7XX_DBGBUS_UFC_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_1', 48) +A7XX_DBGBUS_GMU_GX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GMU_GX', 55) +A7XX_DBGBUS_DBGC = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_DBGC', 59) +A7XX_DBGBUS_CX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CX', 60) +A7XX_DBGBUS_GMU_CX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GMU_CX', 61) +A7XX_DBGBUS_GPC_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GPC_BR', 62) +A7XX_DBGBUS_GPC_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GPC_BV', 63) +A7XX_DBGBUS_LARC = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_LARC', 66) +A7XX_DBGBUS_HLSQ_SPTP = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_SPTP', 68) +A7XX_DBGBUS_RB_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_0', 70) +A7XX_DBGBUS_RB_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_1', 71) +A7XX_DBGBUS_RB_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_2', 72) +A7XX_DBGBUS_RB_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_3', 73) +A7XX_DBGBUS_RB_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_4', 74) +A7XX_DBGBUS_RB_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_5', 75) +A7XX_DBGBUS_UCHE_WRAPPER = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UCHE_WRAPPER', 102) +A7XX_DBGBUS_CCU_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_0', 106) +A7XX_DBGBUS_CCU_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_1', 107) +A7XX_DBGBUS_CCU_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_2', 108) +A7XX_DBGBUS_CCU_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_3', 109) +A7XX_DBGBUS_CCU_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_4', 110) +A7XX_DBGBUS_CCU_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_5', 111) +A7XX_DBGBUS_VFD_BR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_0', 138) +A7XX_DBGBUS_VFD_BR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_1', 139) +A7XX_DBGBUS_VFD_BR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_2', 140) +A7XX_DBGBUS_VFD_BR_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_3', 141) +A7XX_DBGBUS_VFD_BR_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_4', 142) +A7XX_DBGBUS_VFD_BR_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_5', 143) +A7XX_DBGBUS_VFD_BR_6 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_6', 144) +A7XX_DBGBUS_VFD_BR_7 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_7', 145) +A7XX_DBGBUS_VFD_BV_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_0', 202) +A7XX_DBGBUS_VFD_BV_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_1', 203) +A7XX_DBGBUS_VFD_BV_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_2', 204) +A7XX_DBGBUS_VFD_BV_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_3', 205) +A7XX_DBGBUS_USP_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_0', 234) +A7XX_DBGBUS_USP_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_1', 235) +A7XX_DBGBUS_USP_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_2', 236) +A7XX_DBGBUS_USP_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_3', 237) +A7XX_DBGBUS_USP_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_4', 238) +A7XX_DBGBUS_USP_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_5', 239) +A7XX_DBGBUS_TP_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_0', 266) +A7XX_DBGBUS_TP_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_1', 267) +A7XX_DBGBUS_TP_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_2', 268) +A7XX_DBGBUS_TP_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_3', 269) +A7XX_DBGBUS_TP_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_4', 270) +A7XX_DBGBUS_TP_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_5', 271) +A7XX_DBGBUS_TP_6 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_6', 272) +A7XX_DBGBUS_TP_7 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_7', 273) +A7XX_DBGBUS_TP_8 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_8', 274) +A7XX_DBGBUS_TP_9 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_9', 275) +A7XX_DBGBUS_TP_10 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_10', 276) +A7XX_DBGBUS_TP_11 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_11', 277) +A7XX_DBGBUS_USPTP_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_0', 330) +A7XX_DBGBUS_USPTP_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_1', 331) +A7XX_DBGBUS_USPTP_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_2', 332) +A7XX_DBGBUS_USPTP_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_3', 333) +A7XX_DBGBUS_USPTP_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_4', 334) +A7XX_DBGBUS_USPTP_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_5', 335) +A7XX_DBGBUS_USPTP_6 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_6', 336) +A7XX_DBGBUS_USPTP_7 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_7', 337) +A7XX_DBGBUS_USPTP_8 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_8', 338) +A7XX_DBGBUS_USPTP_9 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_9', 339) +A7XX_DBGBUS_USPTP_10 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_10', 340) +A7XX_DBGBUS_USPTP_11 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_11', 341) +A7XX_DBGBUS_CCHE_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCHE_0', 396) +A7XX_DBGBUS_CCHE_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCHE_1', 397) +A7XX_DBGBUS_CCHE_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCHE_2', 398) +A7XX_DBGBUS_VPC_DSTR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_DSTR_0', 408) +A7XX_DBGBUS_VPC_DSTR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_DSTR_1', 409) +A7XX_DBGBUS_VPC_DSTR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_DSTR_2', 410) +A7XX_DBGBUS_HLSQ_DP_STR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_0', 411) +A7XX_DBGBUS_HLSQ_DP_STR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_1', 412) +A7XX_DBGBUS_HLSQ_DP_STR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_2', 413) +A7XX_DBGBUS_HLSQ_DP_STR_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_3', 414) +A7XX_DBGBUS_HLSQ_DP_STR_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_4', 415) +A7XX_DBGBUS_HLSQ_DP_STR_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_5', 416) +A7XX_DBGBUS_UFC_DSTR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_DSTR_0', 443) +A7XX_DBGBUS_UFC_DSTR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_DSTR_1', 444) +A7XX_DBGBUS_UFC_DSTR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_DSTR_2', 445) +A7XX_DBGBUS_CGC_SUBCORE = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CGC_SUBCORE', 446) +A7XX_DBGBUS_CGC_CORE = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CGC_CORE', 447) + +enum_a6xx_cp_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_CP_ALWAYS_COUNT = enum_a6xx_cp_perfcounter_select.define('PERF_CP_ALWAYS_COUNT', 0) +PERF_CP_BUSY_GFX_CORE_IDLE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_BUSY_GFX_CORE_IDLE', 1) +PERF_CP_BUSY_CYCLES = enum_a6xx_cp_perfcounter_select.define('PERF_CP_BUSY_CYCLES', 2) +PERF_CP_NUM_PREEMPTIONS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_NUM_PREEMPTIONS', 3) +PERF_CP_PREEMPTION_REACTION_DELAY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREEMPTION_REACTION_DELAY', 4) +PERF_CP_PREEMPTION_SWITCH_OUT_TIME = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREEMPTION_SWITCH_OUT_TIME', 5) +PERF_CP_PREEMPTION_SWITCH_IN_TIME = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREEMPTION_SWITCH_IN_TIME', 6) +PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 7) +PERF_CP_PREDICATED_DRAWS_KILLED = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREDICATED_DRAWS_KILLED', 8) +PERF_CP_MODE_SWITCH = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MODE_SWITCH', 9) +PERF_CP_ZPASS_DONE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_ZPASS_DONE', 10) +PERF_CP_CONTEXT_DONE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CONTEXT_DONE', 11) +PERF_CP_CACHE_FLUSH = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CACHE_FLUSH', 12) +PERF_CP_LONG_PREEMPTIONS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_LONG_PREEMPTIONS', 13) +PERF_CP_SQE_I_CACHE_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_I_CACHE_STARVE', 14) +PERF_CP_SQE_IDLE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_IDLE', 15) +PERF_CP_SQE_PM4_STARVE_RB_IB = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PM4_STARVE_RB_IB', 16) +PERF_CP_SQE_PM4_STARVE_SDS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PM4_STARVE_SDS', 17) +PERF_CP_SQE_MRB_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_MRB_STARVE', 18) +PERF_CP_SQE_RRB_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_RRB_STARVE', 19) +PERF_CP_SQE_VSD_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_VSD_STARVE', 20) +PERF_CP_VSD_DECODE_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_VSD_DECODE_STARVE', 21) +PERF_CP_SQE_PIPE_OUT_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PIPE_OUT_STALL', 22) +PERF_CP_SQE_SYNC_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_SYNC_STALL', 23) +PERF_CP_SQE_PM4_WFI_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PM4_WFI_STALL', 24) +PERF_CP_SQE_SYS_WFI_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_SYS_WFI_STALL', 25) +PERF_CP_SQE_T4_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_T4_EXEC', 26) +PERF_CP_SQE_LOAD_STATE_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_LOAD_STATE_EXEC', 27) +PERF_CP_SQE_SAVE_SDS_STATE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_SAVE_SDS_STATE', 28) +PERF_CP_SQE_DRAW_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_DRAW_EXEC', 29) +PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 30) +PERF_CP_SQE_EXEC_PROFILED = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_EXEC_PROFILED', 31) +PERF_CP_MEMORY_POOL_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MEMORY_POOL_EMPTY', 32) +PERF_CP_MEMORY_POOL_SYNC_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MEMORY_POOL_SYNC_STALL', 33) +PERF_CP_MEMORY_POOL_ABOVE_THRESH = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MEMORY_POOL_ABOVE_THRESH', 34) +PERF_CP_AHB_WR_STALL_PRE_DRAWS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_WR_STALL_PRE_DRAWS', 35) +PERF_CP_AHB_STALL_SQE_GMU = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_STALL_SQE_GMU', 36) +PERF_CP_AHB_STALL_SQE_WR_OTHER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_STALL_SQE_WR_OTHER', 37) +PERF_CP_AHB_STALL_SQE_RD_OTHER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_STALL_SQE_RD_OTHER', 38) +PERF_CP_CLUSTER0_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER0_EMPTY', 39) +PERF_CP_CLUSTER1_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER1_EMPTY', 40) +PERF_CP_CLUSTER2_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER2_EMPTY', 41) +PERF_CP_CLUSTER3_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER3_EMPTY', 42) +PERF_CP_CLUSTER4_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER4_EMPTY', 43) +PERF_CP_CLUSTER5_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER5_EMPTY', 44) +PERF_CP_PM4_DATA = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PM4_DATA', 45) +PERF_CP_PM4_HEADERS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PM4_HEADERS', 46) +PERF_CP_VBIF_READ_BEATS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_VBIF_READ_BEATS', 47) +PERF_CP_VBIF_WRITE_BEATS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_VBIF_WRITE_BEATS', 48) +PERF_CP_SQE_INSTR_COUNTER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_INSTR_COUNTER', 49) + +enum_a6xx_rbbm_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_RBBM_ALWAYS_COUNT = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_ALWAYS_COUNT', 0) +PERF_RBBM_ALWAYS_ON = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_ALWAYS_ON', 1) +PERF_RBBM_TSE_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_TSE_BUSY', 2) +PERF_RBBM_RAS_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_RAS_BUSY', 3) +PERF_RBBM_PC_DCALL_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_PC_DCALL_BUSY', 4) +PERF_RBBM_PC_VSD_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_PC_VSD_BUSY', 5) +PERF_RBBM_STATUS_MASKED = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_STATUS_MASKED', 6) +PERF_RBBM_COM_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_COM_BUSY', 7) +PERF_RBBM_DCOM_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_DCOM_BUSY', 8) +PERF_RBBM_VBIF_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_VBIF_BUSY', 9) +PERF_RBBM_VSC_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_VSC_BUSY', 10) +PERF_RBBM_TESS_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_TESS_BUSY', 11) +PERF_RBBM_UCHE_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_UCHE_BUSY', 12) +PERF_RBBM_HLSQ_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_HLSQ_BUSY', 13) + +enum_a6xx_pc_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_PC_BUSY_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_BUSY_CYCLES', 0) +PERF_PC_WORKING_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_WORKING_CYCLES', 1) +PERF_PC_STALL_CYCLES_VFD = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_VFD', 2) +PERF_PC_STALL_CYCLES_TSE = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_TSE', 3) +PERF_PC_STALL_CYCLES_VPC = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_VPC', 4) +PERF_PC_STALL_CYCLES_UCHE = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_UCHE', 5) +PERF_PC_STALL_CYCLES_TESS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_TESS', 6) +PERF_PC_STALL_CYCLES_TSE_ONLY = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_TSE_ONLY', 7) +PERF_PC_STALL_CYCLES_VPC_ONLY = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_VPC_ONLY', 8) +PERF_PC_PASS1_TF_STALL_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_PASS1_TF_STALL_CYCLES', 9) +PERF_PC_STARVE_CYCLES_FOR_INDEX = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_INDEX', 10) +PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR', 11) +PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM', 12) +PERF_PC_STARVE_CYCLES_FOR_POSITION = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_POSITION', 13) +PERF_PC_STARVE_CYCLES_DI = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_DI', 14) +PERF_PC_VIS_STREAMS_LOADED = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VIS_STREAMS_LOADED', 15) +PERF_PC_INSTANCES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_INSTANCES', 16) +PERF_PC_VPC_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VPC_PRIMITIVES', 17) +PERF_PC_DEAD_PRIM = enum_a6xx_pc_perfcounter_select.define('PERF_PC_DEAD_PRIM', 18) +PERF_PC_LIVE_PRIM = enum_a6xx_pc_perfcounter_select.define('PERF_PC_LIVE_PRIM', 19) +PERF_PC_VERTEX_HITS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VERTEX_HITS', 20) +PERF_PC_IA_VERTICES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_IA_VERTICES', 21) +PERF_PC_IA_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_IA_PRIMITIVES', 22) +PERF_PC_GS_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_GS_PRIMITIVES', 23) +PERF_PC_HS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_HS_INVOCATIONS', 24) +PERF_PC_DS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_DS_INVOCATIONS', 25) +PERF_PC_VS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VS_INVOCATIONS', 26) +PERF_PC_GS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_GS_INVOCATIONS', 27) +PERF_PC_DS_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_DS_PRIMITIVES', 28) +PERF_PC_VPC_POS_DATA_TRANSACTION = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VPC_POS_DATA_TRANSACTION', 29) +PERF_PC_3D_DRAWCALLS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_3D_DRAWCALLS', 30) +PERF_PC_2D_DRAWCALLS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_2D_DRAWCALLS', 31) +PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS', 32) +PERF_TESS_BUSY_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_BUSY_CYCLES', 33) +PERF_TESS_WORKING_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_WORKING_CYCLES', 34) +PERF_TESS_STALL_CYCLES_PC = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_STALL_CYCLES_PC', 35) +PERF_TESS_STARVE_CYCLES_PC = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_STARVE_CYCLES_PC', 36) +PERF_PC_TSE_TRANSACTION = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TSE_TRANSACTION', 37) +PERF_PC_TSE_VERTEX = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TSE_VERTEX', 38) +PERF_PC_TESS_PC_UV_TRANS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TESS_PC_UV_TRANS', 39) +PERF_PC_TESS_PC_UV_PATCHES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TESS_PC_UV_PATCHES', 40) +PERF_PC_TESS_FACTOR_TRANS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TESS_FACTOR_TRANS', 41) + +enum_a6xx_vfd_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_VFD_BUSY_CYCLES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_BUSY_CYCLES', 0) +PERF_VFD_STALL_CYCLES_UCHE = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_UCHE', 1) +PERF_VFD_STALL_CYCLES_VPC_ALLOC = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_VPC_ALLOC', 2) +PERF_VFD_STALL_CYCLES_SP_INFO = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_SP_INFO', 3) +PERF_VFD_STALL_CYCLES_SP_ATTR = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_SP_ATTR', 4) +PERF_VFD_STARVE_CYCLES_UCHE = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STARVE_CYCLES_UCHE', 5) +PERF_VFD_RBUFFER_FULL = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_RBUFFER_FULL', 6) +PERF_VFD_ATTR_INFO_FIFO_FULL = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_ATTR_INFO_FIFO_FULL', 7) +PERF_VFD_DECODED_ATTRIBUTE_BYTES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_DECODED_ATTRIBUTE_BYTES', 8) +PERF_VFD_NUM_ATTRIBUTES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_NUM_ATTRIBUTES', 9) +PERF_VFD_UPPER_SHADER_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_UPPER_SHADER_FIBERS', 10) +PERF_VFD_LOWER_SHADER_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_LOWER_SHADER_FIBERS', 11) +PERF_VFD_MODE_0_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_0_FIBERS', 12) +PERF_VFD_MODE_1_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_1_FIBERS', 13) +PERF_VFD_MODE_2_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_2_FIBERS', 14) +PERF_VFD_MODE_3_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_3_FIBERS', 15) +PERF_VFD_MODE_4_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_4_FIBERS', 16) +PERF_VFD_TOTAL_VERTICES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_TOTAL_VERTICES', 17) +PERF_VFDP_STALL_CYCLES_VFD = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STALL_CYCLES_VFD', 18) +PERF_VFDP_STALL_CYCLES_VFD_INDEX = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STALL_CYCLES_VFD_INDEX', 19) +PERF_VFDP_STALL_CYCLES_VFD_PROG = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STALL_CYCLES_VFD_PROG', 20) +PERF_VFDP_STARVE_CYCLES_PC = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STARVE_CYCLES_PC', 21) +PERF_VFDP_VS_STAGE_WAVES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_VS_STAGE_WAVES', 22) + +enum_a6xx_hlsq_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_HLSQ_BUSY_CYCLES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_BUSY_CYCLES', 0) +PERF_HLSQ_STALL_CYCLES_UCHE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_UCHE', 1) +PERF_HLSQ_STALL_CYCLES_SP_STATE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_SP_STATE', 2) +PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', 3) +PERF_HLSQ_UCHE_LATENCY_CYCLES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_UCHE_LATENCY_CYCLES', 4) +PERF_HLSQ_UCHE_LATENCY_COUNT = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_UCHE_LATENCY_COUNT', 5) +PERF_HLSQ_FS_STAGE_1X_WAVES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_STAGE_1X_WAVES', 6) +PERF_HLSQ_FS_STAGE_2X_WAVES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_STAGE_2X_WAVES', 7) +PERF_HLSQ_QUADS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_QUADS', 8) +PERF_HLSQ_CS_INVOCATIONS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_CS_INVOCATIONS', 9) +PERF_HLSQ_COMPUTE_DRAWCALLS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_COMPUTE_DRAWCALLS', 10) +PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', 11) +PERF_HLSQ_DUAL_FS_PROG_ACTIVE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 12) +PERF_HLSQ_DUAL_VS_PROG_ACTIVE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_DUAL_VS_PROG_ACTIVE', 13) +PERF_HLSQ_FS_BATCH_COUNT_ZERO = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_BATCH_COUNT_ZERO', 14) +PERF_HLSQ_VS_BATCH_COUNT_ZERO = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_VS_BATCH_COUNT_ZERO', 15) +PERF_HLSQ_WAVE_PENDING_NO_QUAD = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_WAVE_PENDING_NO_QUAD', 16) +PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', 17) +PERF_HLSQ_STALL_CYCLES_VPC = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_VPC', 18) +PERF_HLSQ_PIXELS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_PIXELS', 19) +PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC', 20) + +enum_a6xx_vpc_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_VPC_BUSY_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_BUSY_CYCLES', 0) +PERF_VPC_WORKING_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_WORKING_CYCLES', 1) +PERF_VPC_STALL_CYCLES_UCHE = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_UCHE', 2) +PERF_VPC_STALL_CYCLES_VFD_WACK = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_VFD_WACK', 3) +PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC', 4) +PERF_VPC_STALL_CYCLES_PC = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_PC', 5) +PERF_VPC_STALL_CYCLES_SP_LM = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_SP_LM', 6) +PERF_VPC_STARVE_CYCLES_SP = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STARVE_CYCLES_SP', 7) +PERF_VPC_STARVE_CYCLES_LRZ = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STARVE_CYCLES_LRZ', 8) +PERF_VPC_PC_PRIMITIVES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_PC_PRIMITIVES', 9) +PERF_VPC_SP_COMPONENTS = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_SP_COMPONENTS', 10) +PERF_VPC_STALL_CYCLES_VPCRAM_POS = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_VPCRAM_POS', 11) +PERF_VPC_LRZ_ASSIGN_PRIMITIVES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_LRZ_ASSIGN_PRIMITIVES', 12) +PERF_VPC_RB_VISIBLE_PRIMITIVES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_RB_VISIBLE_PRIMITIVES', 13) +PERF_VPC_LM_TRANSACTION = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_LM_TRANSACTION', 14) +PERF_VPC_STREAMOUT_TRANSACTION = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STREAMOUT_TRANSACTION', 15) +PERF_VPC_VS_BUSY_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_VS_BUSY_CYCLES', 16) +PERF_VPC_PS_BUSY_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_PS_BUSY_CYCLES', 17) +PERF_VPC_VS_WORKING_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_VS_WORKING_CYCLES', 18) +PERF_VPC_PS_WORKING_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_PS_WORKING_CYCLES', 19) +PERF_VPC_STARVE_CYCLES_RB = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STARVE_CYCLES_RB', 20) +PERF_VPC_NUM_VPCRAM_READ_POS = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_VPCRAM_READ_POS', 21) +PERF_VPC_WIT_FULL_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_WIT_FULL_CYCLES', 22) +PERF_VPC_VPCRAM_FULL_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_VPCRAM_FULL_CYCLES', 23) +PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', 24) +PERF_VPC_NUM_VPCRAM_WRITE = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_VPCRAM_WRITE', 25) +PERF_VPC_NUM_VPCRAM_READ_SO = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_VPCRAM_READ_SO', 26) +PERF_VPC_NUM_ATTR_REQ_LM = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_ATTR_REQ_LM', 27) + +enum_a6xx_tse_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_TSE_BUSY_CYCLES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_BUSY_CYCLES', 0) +PERF_TSE_CLIPPING_CYCLES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CLIPPING_CYCLES', 1) +PERF_TSE_STALL_CYCLES_RAS = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STALL_CYCLES_RAS', 2) +PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE', 3) +PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', 4) +PERF_TSE_STARVE_CYCLES_PC = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STARVE_CYCLES_PC', 5) +PERF_TSE_INPUT_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_INPUT_PRIM', 6) +PERF_TSE_INPUT_NULL_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_INPUT_NULL_PRIM', 7) +PERF_TSE_TRIVAL_REJ_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_TRIVAL_REJ_PRIM', 8) +PERF_TSE_CLIPPED_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CLIPPED_PRIM', 9) +PERF_TSE_ZERO_AREA_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_ZERO_AREA_PRIM', 10) +PERF_TSE_FACENESS_CULLED_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_FACENESS_CULLED_PRIM', 11) +PERF_TSE_ZERO_PIXEL_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_ZERO_PIXEL_PRIM', 12) +PERF_TSE_OUTPUT_NULL_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_OUTPUT_NULL_PRIM', 13) +PERF_TSE_OUTPUT_VISIBLE_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_OUTPUT_VISIBLE_PRIM', 14) +PERF_TSE_CINVOCATION = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CINVOCATION', 15) +PERF_TSE_CPRIMITIVES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CPRIMITIVES', 16) +PERF_TSE_2D_INPUT_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_2D_INPUT_PRIM', 17) +PERF_TSE_2D_ALIVE_CYCLES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_2D_ALIVE_CYCLES', 18) +PERF_TSE_CLIP_PLANES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CLIP_PLANES', 19) + +enum_a6xx_ras_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_RAS_BUSY_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_BUSY_CYCLES', 0) +PERF_RAS_SUPERTILE_ACTIVE_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_SUPERTILE_ACTIVE_CYCLES', 1) +PERF_RAS_STALL_CYCLES_LRZ = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_STALL_CYCLES_LRZ', 2) +PERF_RAS_STARVE_CYCLES_TSE = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_STARVE_CYCLES_TSE', 3) +PERF_RAS_SUPER_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_SUPER_TILES', 4) +PERF_RAS_8X4_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_8X4_TILES', 5) +PERF_RAS_MASKGEN_ACTIVE = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_MASKGEN_ACTIVE', 6) +PERF_RAS_FULLY_COVERED_SUPER_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_FULLY_COVERED_SUPER_TILES', 7) +PERF_RAS_FULLY_COVERED_8X4_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_FULLY_COVERED_8X4_TILES', 8) +PERF_RAS_PRIM_KILLED_INVISILBE = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_PRIM_KILLED_INVISILBE', 9) +PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 10) +PERF_RAS_LRZ_INTF_WORKING_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_LRZ_INTF_WORKING_CYCLES', 11) +PERF_RAS_BLOCKS = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_BLOCKS', 12) + +enum_a6xx_uche_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_UCHE_BUSY_CYCLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BUSY_CYCLES', 0) +PERF_UCHE_STALL_CYCLES_ARBITER = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_STALL_CYCLES_ARBITER', 1) +PERF_UCHE_VBIF_LATENCY_CYCLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_LATENCY_CYCLES', 2) +PERF_UCHE_VBIF_LATENCY_SAMPLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_LATENCY_SAMPLES', 3) +PERF_UCHE_VBIF_READ_BEATS_TP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_TP', 4) +PERF_UCHE_VBIF_READ_BEATS_VFD = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_VFD', 5) +PERF_UCHE_VBIF_READ_BEATS_HLSQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_HLSQ', 6) +PERF_UCHE_VBIF_READ_BEATS_LRZ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_LRZ', 7) +PERF_UCHE_VBIF_READ_BEATS_SP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_SP', 8) +PERF_UCHE_READ_REQUESTS_TP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_TP', 9) +PERF_UCHE_READ_REQUESTS_VFD = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_VFD', 10) +PERF_UCHE_READ_REQUESTS_HLSQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_HLSQ', 11) +PERF_UCHE_READ_REQUESTS_LRZ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_LRZ', 12) +PERF_UCHE_READ_REQUESTS_SP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_SP', 13) +PERF_UCHE_WRITE_REQUESTS_LRZ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_LRZ', 14) +PERF_UCHE_WRITE_REQUESTS_SP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_SP', 15) +PERF_UCHE_WRITE_REQUESTS_VPC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_VPC', 16) +PERF_UCHE_WRITE_REQUESTS_VSC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_VSC', 17) +PERF_UCHE_EVICTS = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_EVICTS', 18) +PERF_UCHE_BANK_REQ0 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ0', 19) +PERF_UCHE_BANK_REQ1 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ1', 20) +PERF_UCHE_BANK_REQ2 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ2', 21) +PERF_UCHE_BANK_REQ3 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ3', 22) +PERF_UCHE_BANK_REQ4 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ4', 23) +PERF_UCHE_BANK_REQ5 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ5', 24) +PERF_UCHE_BANK_REQ6 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ6', 25) +PERF_UCHE_BANK_REQ7 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ7', 26) +PERF_UCHE_VBIF_READ_BEATS_CH0 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_CH0', 27) +PERF_UCHE_VBIF_READ_BEATS_CH1 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_CH1', 28) +PERF_UCHE_GMEM_READ_BEATS = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_GMEM_READ_BEATS', 29) +PERF_UCHE_TPH_REF_FULL = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_TPH_REF_FULL', 30) +PERF_UCHE_TPH_VICTIM_FULL = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_TPH_VICTIM_FULL', 31) +PERF_UCHE_TPH_EXT_FULL = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_TPH_EXT_FULL', 32) +PERF_UCHE_VBIF_STALL_WRITE_DATA = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_STALL_WRITE_DATA', 33) +PERF_UCHE_DCMP_LATENCY_SAMPLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_DCMP_LATENCY_SAMPLES', 34) +PERF_UCHE_DCMP_LATENCY_CYCLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_DCMP_LATENCY_CYCLES', 35) +PERF_UCHE_VBIF_READ_BEATS_PC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_PC', 36) +PERF_UCHE_READ_REQUESTS_PC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_PC', 37) +PERF_UCHE_RAM_READ_REQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_RAM_READ_REQ', 38) +PERF_UCHE_RAM_WRITE_REQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_RAM_WRITE_REQ', 39) + +enum_a6xx_tp_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_TP_BUSY_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_BUSY_CYCLES', 0) +PERF_TP_STALL_CYCLES_UCHE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_STALL_CYCLES_UCHE', 1) +PERF_TP_LATENCY_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_LATENCY_CYCLES', 2) +PERF_TP_LATENCY_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_LATENCY_TRANS', 3) +PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_REQUEST_SAMPLES', 4) +PERF_TP_FLAG_CACHE_REQUEST_LATENCY = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_REQUEST_LATENCY', 5) +PERF_TP_L1_CACHELINE_REQUESTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_CACHELINE_REQUESTS', 6) +PERF_TP_L1_CACHELINE_MISSES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_CACHELINE_MISSES', 7) +PERF_TP_SP_TP_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_SP_TP_TRANS', 8) +PERF_TP_TP_SP_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_TP_SP_TRANS', 9) +PERF_TP_OUTPUT_PIXELS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS', 10) +PERF_TP_FILTER_WORKLOAD_16BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FILTER_WORKLOAD_16BIT', 11) +PERF_TP_FILTER_WORKLOAD_32BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FILTER_WORKLOAD_32BIT', 12) +PERF_TP_QUADS_RECEIVED = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_RECEIVED', 13) +PERF_TP_QUADS_OFFSET = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_OFFSET', 14) +PERF_TP_QUADS_SHADOW = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_SHADOW', 15) +PERF_TP_QUADS_ARRAY = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_ARRAY', 16) +PERF_TP_QUADS_GRADIENT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_GRADIENT', 17) +PERF_TP_QUADS_1D = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_1D', 18) +PERF_TP_QUADS_2D = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_2D', 19) +PERF_TP_QUADS_BUFFER = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_BUFFER', 20) +PERF_TP_QUADS_3D = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_3D', 21) +PERF_TP_QUADS_CUBE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_CUBE', 22) +PERF_TP_DIVERGENT_QUADS_RECEIVED = enum_a6xx_tp_perfcounter_select.define('PERF_TP_DIVERGENT_QUADS_RECEIVED', 23) +PERF_TP_PRT_NON_RESIDENT_EVENTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_PRT_NON_RESIDENT_EVENTS', 24) +PERF_TP_OUTPUT_PIXELS_POINT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_POINT', 25) +PERF_TP_OUTPUT_PIXELS_BILINEAR = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_BILINEAR', 26) +PERF_TP_OUTPUT_PIXELS_MIP = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_MIP', 27) +PERF_TP_OUTPUT_PIXELS_ANISO = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_ANISO', 28) +PERF_TP_OUTPUT_PIXELS_ZERO_LOD = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_ZERO_LOD', 29) +PERF_TP_FLAG_CACHE_REQUESTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_REQUESTS', 30) +PERF_TP_FLAG_CACHE_MISSES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_MISSES', 31) +PERF_TP_L1_5_L2_REQUESTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_L2_REQUESTS', 32) +PERF_TP_2D_OUTPUT_PIXELS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_OUTPUT_PIXELS', 33) +PERF_TP_2D_OUTPUT_PIXELS_POINT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_OUTPUT_PIXELS_POINT', 34) +PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', 35) +PERF_TP_2D_FILTER_WORKLOAD_16BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_FILTER_WORKLOAD_16BIT', 36) +PERF_TP_2D_FILTER_WORKLOAD_32BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_FILTER_WORKLOAD_32BIT', 37) +PERF_TP_TPA2TPC_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_TPA2TPC_TRANS', 38) +PERF_TP_L1_MISSES_ASTC_1TILE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_MISSES_ASTC_1TILE', 39) +PERF_TP_L1_MISSES_ASTC_2TILE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_MISSES_ASTC_2TILE', 40) +PERF_TP_L1_MISSES_ASTC_4TILE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_MISSES_ASTC_4TILE', 41) +PERF_TP_L1_5_L2_COMPRESS_REQS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_L2_COMPRESS_REQS', 42) +PERF_TP_L1_5_L2_COMPRESS_MISS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_L2_COMPRESS_MISS', 43) +PERF_TP_L1_BANK_CONFLICT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_BANK_CONFLICT', 44) +PERF_TP_L1_5_MISS_LATENCY_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_MISS_LATENCY_CYCLES', 45) +PERF_TP_L1_5_MISS_LATENCY_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_MISS_LATENCY_TRANS', 46) +PERF_TP_QUADS_CONSTANT_MULTIPLIED = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_CONSTANT_MULTIPLIED', 47) +PERF_TP_FRONTEND_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FRONTEND_WORKING_CYCLES', 48) +PERF_TP_L1_TAG_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_TAG_WORKING_CYCLES', 49) +PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', 50) +PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', 51) +PERF_TP_BACKEND_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_BACKEND_WORKING_CYCLES', 52) +PERF_TP_FLAG_CACHE_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_WORKING_CYCLES', 53) +PERF_TP_L1_5_CACHE_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_CACHE_WORKING_CYCLES', 54) +PERF_TP_STARVE_CYCLES_SP = enum_a6xx_tp_perfcounter_select.define('PERF_TP_STARVE_CYCLES_SP', 55) +PERF_TP_STARVE_CYCLES_UCHE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_STARVE_CYCLES_UCHE', 56) + +enum_a6xx_sp_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_SP_BUSY_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_BUSY_CYCLES', 0) +PERF_SP_ALU_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ALU_WORKING_CYCLES', 1) +PERF_SP_EFU_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EFU_WORKING_CYCLES', 2) +PERF_SP_STALL_CYCLES_VPC = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_VPC', 3) +PERF_SP_STALL_CYCLES_TP = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_TP', 4) +PERF_SP_STALL_CYCLES_UCHE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_UCHE', 5) +PERF_SP_STALL_CYCLES_RB = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_RB', 6) +PERF_SP_NON_EXECUTION_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_NON_EXECUTION_CYCLES', 7) +PERF_SP_WAVE_CONTEXTS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_CONTEXTS', 8) +PERF_SP_WAVE_CONTEXT_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_CONTEXT_CYCLES', 9) +PERF_SP_FS_STAGE_WAVE_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_WAVE_CYCLES', 10) +PERF_SP_FS_STAGE_WAVE_SAMPLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_WAVE_SAMPLES', 11) +PERF_SP_VS_STAGE_WAVE_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_WAVE_CYCLES', 12) +PERF_SP_VS_STAGE_WAVE_SAMPLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_WAVE_SAMPLES', 13) +PERF_SP_FS_STAGE_DURATION_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_DURATION_CYCLES', 14) +PERF_SP_VS_STAGE_DURATION_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_DURATION_CYCLES', 15) +PERF_SP_WAVE_CTRL_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_CTRL_CYCLES', 16) +PERF_SP_WAVE_LOAD_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_LOAD_CYCLES', 17) +PERF_SP_WAVE_EMIT_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_EMIT_CYCLES', 18) +PERF_SP_WAVE_NOP_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_NOP_CYCLES', 19) +PERF_SP_WAVE_WAIT_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_WAIT_CYCLES', 20) +PERF_SP_WAVE_FETCH_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_FETCH_CYCLES', 21) +PERF_SP_WAVE_IDLE_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_IDLE_CYCLES', 22) +PERF_SP_WAVE_END_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_END_CYCLES', 23) +PERF_SP_WAVE_LONG_SYNC_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_LONG_SYNC_CYCLES', 24) +PERF_SP_WAVE_SHORT_SYNC_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_SHORT_SYNC_CYCLES', 25) +PERF_SP_WAVE_JOIN_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_JOIN_CYCLES', 26) +PERF_SP_LM_LOAD_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_LOAD_INSTRUCTIONS', 27) +PERF_SP_LM_STORE_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_STORE_INSTRUCTIONS', 28) +PERF_SP_LM_ATOMICS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_ATOMICS', 29) +PERF_SP_GM_LOAD_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_LOAD_INSTRUCTIONS', 30) +PERF_SP_GM_STORE_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_STORE_INSTRUCTIONS', 31) +PERF_SP_GM_ATOMICS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_ATOMICS', 32) +PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', 33) +PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', 34) +PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', 35) +PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', 36) +PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', 37) +PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', 38) +PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', 39) +PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', 40) +PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', 41) +PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', 42) +PERF_SP_VS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_INSTRUCTIONS', 43) +PERF_SP_FS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_INSTRUCTIONS', 44) +PERF_SP_ADDR_LOCK_COUNT = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ADDR_LOCK_COUNT', 45) +PERF_SP_UCHE_READ_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_UCHE_READ_TRANS', 46) +PERF_SP_UCHE_WRITE_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_UCHE_WRITE_TRANS', 47) +PERF_SP_EXPORT_VPC_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EXPORT_VPC_TRANS', 48) +PERF_SP_EXPORT_RB_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EXPORT_RB_TRANS', 49) +PERF_SP_PIXELS_KILLED = enum_a6xx_sp_perfcounter_select.define('PERF_SP_PIXELS_KILLED', 50) +PERF_SP_ICL1_REQUESTS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ICL1_REQUESTS', 51) +PERF_SP_ICL1_MISSES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ICL1_MISSES', 52) +PERF_SP_HS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_HS_INSTRUCTIONS', 53) +PERF_SP_DS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_DS_INSTRUCTIONS', 54) +PERF_SP_GS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GS_INSTRUCTIONS', 55) +PERF_SP_CS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_CS_INSTRUCTIONS', 56) +PERF_SP_GPR_READ = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_READ', 57) +PERF_SP_GPR_WRITE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_WRITE', 58) +PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', 59) +PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', 60) +PERF_SP_LM_BANK_CONFLICTS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_BANK_CONFLICTS', 61) +PERF_SP_TEX_CONTROL_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_TEX_CONTROL_WORKING_CYCLES', 62) +PERF_SP_LOAD_CONTROL_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LOAD_CONTROL_WORKING_CYCLES', 63) +PERF_SP_FLOW_CONTROL_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FLOW_CONTROL_WORKING_CYCLES', 64) +PERF_SP_LM_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_WORKING_CYCLES', 65) +PERF_SP_DISPATCHER_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_DISPATCHER_WORKING_CYCLES', 66) +PERF_SP_SEQUENCER_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_SEQUENCER_WORKING_CYCLES', 67) +PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', 68) +PERF_SP_STARVE_CYCLES_HLSQ = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STARVE_CYCLES_HLSQ', 69) +PERF_SP_NON_EXECUTION_LS_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_NON_EXECUTION_LS_CYCLES', 70) +PERF_SP_WORKING_EU = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU', 71) +PERF_SP_ANY_EU_WORKING = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING', 72) +PERF_SP_WORKING_EU_FS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU_FS_STAGE', 73) +PERF_SP_ANY_EU_WORKING_FS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING_FS_STAGE', 74) +PERF_SP_WORKING_EU_VS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU_VS_STAGE', 75) +PERF_SP_ANY_EU_WORKING_VS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING_VS_STAGE', 76) +PERF_SP_WORKING_EU_CS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU_CS_STAGE', 77) +PERF_SP_ANY_EU_WORKING_CS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING_CS_STAGE', 78) +PERF_SP_GPR_READ_PREFETCH = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_READ_PREFETCH', 79) +PERF_SP_GPR_READ_CONFLICT = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_READ_CONFLICT', 80) +PERF_SP_GPR_WRITE_CONFLICT = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_WRITE_CONFLICT', 81) +PERF_SP_GM_LOAD_LATENCY_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_LOAD_LATENCY_CYCLES', 82) +PERF_SP_GM_LOAD_LATENCY_SAMPLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_LOAD_LATENCY_SAMPLES', 83) +PERF_SP_EXECUTABLE_WAVES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EXECUTABLE_WAVES', 84) + +enum_a6xx_rb_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_RB_BUSY_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BUSY_CYCLES', 0) +PERF_RB_STALL_CYCLES_HLSQ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_HLSQ', 1) +PERF_RB_STALL_CYCLES_FIFO0_FULL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_FIFO0_FULL', 2) +PERF_RB_STALL_CYCLES_FIFO1_FULL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_FIFO1_FULL', 3) +PERF_RB_STALL_CYCLES_FIFO2_FULL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_FIFO2_FULL', 4) +PERF_RB_STARVE_CYCLES_SP = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_SP', 5) +PERF_RB_STARVE_CYCLES_LRZ_TILE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_LRZ_TILE', 6) +PERF_RB_STARVE_CYCLES_CCU = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_CCU', 7) +PERF_RB_STARVE_CYCLES_Z_PLANE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_Z_PLANE', 8) +PERF_RB_STARVE_CYCLES_BARY_PLANE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_BARY_PLANE', 9) +PERF_RB_Z_WORKLOAD = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_WORKLOAD', 10) +PERF_RB_HLSQ_ACTIVE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_HLSQ_ACTIVE', 11) +PERF_RB_Z_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_READ', 12) +PERF_RB_Z_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_WRITE', 13) +PERF_RB_C_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_C_READ', 14) +PERF_RB_C_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_C_WRITE', 15) +PERF_RB_TOTAL_PASS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_TOTAL_PASS', 16) +PERF_RB_Z_PASS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_PASS', 17) +PERF_RB_Z_FAIL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_FAIL', 18) +PERF_RB_S_FAIL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_S_FAIL', 19) +PERF_RB_BLENDED_FXP_COMPONENTS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDED_FXP_COMPONENTS', 20) +PERF_RB_BLENDED_FP16_COMPONENTS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDED_FP16_COMPONENTS', 21) +PERF_RB_PS_INVOCATIONS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_PS_INVOCATIONS', 22) +PERF_RB_2D_ALIVE_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_ALIVE_CYCLES', 23) +PERF_RB_2D_STALL_CYCLES_A2D = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STALL_CYCLES_A2D', 24) +PERF_RB_2D_STARVE_CYCLES_SRC = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STARVE_CYCLES_SRC', 25) +PERF_RB_2D_STARVE_CYCLES_SP = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STARVE_CYCLES_SP', 26) +PERF_RB_2D_STARVE_CYCLES_DST = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STARVE_CYCLES_DST', 27) +PERF_RB_2D_VALID_PIXELS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_VALID_PIXELS', 28) +PERF_RB_3D_PIXELS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_3D_PIXELS', 29) +PERF_RB_BLENDER_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDER_WORKING_CYCLES', 30) +PERF_RB_ZPROC_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_ZPROC_WORKING_CYCLES', 31) +PERF_RB_CPROC_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_CPROC_WORKING_CYCLES', 32) +PERF_RB_SAMPLER_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_SAMPLER_WORKING_CYCLES', 33) +PERF_RB_STALL_CYCLES_CCU_COLOR_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_COLOR_READ', 34) +PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', 35) +PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', 36) +PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', 37) +PERF_RB_STALL_CYCLES_VPC = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_VPC', 38) +PERF_RB_2D_INPUT_TRANS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_INPUT_TRANS', 39) +PERF_RB_2D_OUTPUT_RB_DST_TRANS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_OUTPUT_RB_DST_TRANS', 40) +PERF_RB_2D_OUTPUT_RB_SRC_TRANS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_OUTPUT_RB_SRC_TRANS', 41) +PERF_RB_BLENDED_FP32_COMPONENTS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDED_FP32_COMPONENTS', 42) +PERF_RB_COLOR_PIX_TILES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_COLOR_PIX_TILES', 43) +PERF_RB_STALL_CYCLES_CCU = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU', 44) +PERF_RB_EARLY_Z_ARB3_GRANT = enum_a6xx_rb_perfcounter_select.define('PERF_RB_EARLY_Z_ARB3_GRANT', 45) +PERF_RB_LATE_Z_ARB3_GRANT = enum_a6xx_rb_perfcounter_select.define('PERF_RB_LATE_Z_ARB3_GRANT', 46) +PERF_RB_EARLY_Z_SKIP_GRANT = enum_a6xx_rb_perfcounter_select.define('PERF_RB_EARLY_Z_SKIP_GRANT', 47) + +enum_a6xx_vsc_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_VSC_BUSY_CYCLES = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_BUSY_CYCLES', 0) +PERF_VSC_WORKING_CYCLES = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_WORKING_CYCLES', 1) +PERF_VSC_STALL_CYCLES_UCHE = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_STALL_CYCLES_UCHE', 2) +PERF_VSC_EOT_NUM = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_EOT_NUM', 3) +PERF_VSC_INPUT_TILES = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_INPUT_TILES', 4) + +enum_a6xx_ccu_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_CCU_BUSY_CYCLES = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_BUSY_CYCLES', 0) +PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', 1) +PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', 2) +PERF_CCU_STARVE_CYCLES_FLAG_RETURN = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_STARVE_CYCLES_FLAG_RETURN', 3) +PERF_CCU_DEPTH_BLOCKS = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_BLOCKS', 4) +PERF_CCU_COLOR_BLOCKS = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_BLOCKS', 5) +PERF_CCU_DEPTH_BLOCK_HIT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_BLOCK_HIT', 6) +PERF_CCU_COLOR_BLOCK_HIT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_BLOCK_HIT', 7) +PERF_CCU_PARTIAL_BLOCK_READ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_PARTIAL_BLOCK_READ', 8) +PERF_CCU_GMEM_READ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_GMEM_READ', 9) +PERF_CCU_GMEM_WRITE = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_GMEM_WRITE', 10) +PERF_CCU_DEPTH_READ_FLAG0_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG0_COUNT', 11) +PERF_CCU_DEPTH_READ_FLAG1_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG1_COUNT', 12) +PERF_CCU_DEPTH_READ_FLAG2_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG2_COUNT', 13) +PERF_CCU_DEPTH_READ_FLAG3_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG3_COUNT', 14) +PERF_CCU_DEPTH_READ_FLAG4_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG4_COUNT', 15) +PERF_CCU_DEPTH_READ_FLAG5_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG5_COUNT', 16) +PERF_CCU_DEPTH_READ_FLAG6_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG6_COUNT', 17) +PERF_CCU_DEPTH_READ_FLAG8_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG8_COUNT', 18) +PERF_CCU_COLOR_READ_FLAG0_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG0_COUNT', 19) +PERF_CCU_COLOR_READ_FLAG1_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG1_COUNT', 20) +PERF_CCU_COLOR_READ_FLAG2_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG2_COUNT', 21) +PERF_CCU_COLOR_READ_FLAG3_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG3_COUNT', 22) +PERF_CCU_COLOR_READ_FLAG4_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG4_COUNT', 23) +PERF_CCU_COLOR_READ_FLAG5_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG5_COUNT', 24) +PERF_CCU_COLOR_READ_FLAG6_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG6_COUNT', 25) +PERF_CCU_COLOR_READ_FLAG8_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG8_COUNT', 26) +PERF_CCU_2D_RD_REQ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_2D_RD_REQ', 27) +PERF_CCU_2D_WR_REQ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_2D_WR_REQ', 28) + +enum_a6xx_lrz_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_LRZ_BUSY_CYCLES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_BUSY_CYCLES', 0) +PERF_LRZ_STARVE_CYCLES_RAS = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STARVE_CYCLES_RAS', 1) +PERF_LRZ_STALL_CYCLES_RB = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_RB', 2) +PERF_LRZ_STALL_CYCLES_VSC = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_VSC', 3) +PERF_LRZ_STALL_CYCLES_VPC = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_VPC', 4) +PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', 5) +PERF_LRZ_STALL_CYCLES_UCHE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_UCHE', 6) +PERF_LRZ_LRZ_READ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_LRZ_READ', 7) +PERF_LRZ_LRZ_WRITE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_LRZ_WRITE', 8) +PERF_LRZ_READ_LATENCY = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_READ_LATENCY', 9) +PERF_LRZ_MERGE_CACHE_UPDATING = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_MERGE_CACHE_UPDATING', 10) +PERF_LRZ_PRIM_KILLED_BY_MASKGEN = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PRIM_KILLED_BY_MASKGEN', 11) +PERF_LRZ_PRIM_KILLED_BY_LRZ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PRIM_KILLED_BY_LRZ', 12) +PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 13) +PERF_LRZ_FULL_8X8_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FULL_8X8_TILES', 14) +PERF_LRZ_PARTIAL_8X8_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PARTIAL_8X8_TILES', 15) +PERF_LRZ_TILE_KILLED = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_TILE_KILLED', 16) +PERF_LRZ_TOTAL_PIXEL = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_TOTAL_PIXEL', 17) +PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', 18) +PERF_LRZ_FULLY_COVERED_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FULLY_COVERED_TILES', 19) +PERF_LRZ_PARTIAL_COVERED_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PARTIAL_COVERED_TILES', 20) +PERF_LRZ_FEEDBACK_ACCEPT = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FEEDBACK_ACCEPT', 21) +PERF_LRZ_FEEDBACK_DISCARD = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FEEDBACK_DISCARD', 22) +PERF_LRZ_FEEDBACK_STALL = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FEEDBACK_STALL', 23) +PERF_LRZ_STALL_CYCLES_RB_ZPLANE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 24) +PERF_LRZ_STALL_CYCLES_RB_BPLANE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_RB_BPLANE', 25) +PERF_LRZ_STALL_CYCLES_VC = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_VC', 26) +PERF_LRZ_RAS_MASK_TRANS = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_RAS_MASK_TRANS', 27) + +enum_a6xx_cmp_perfcounter_select = CEnum(ctypes.c_uint32) +PERF_CMPDECMP_STALL_CYCLES_ARB = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_STALL_CYCLES_ARB', 0) +PERF_CMPDECMP_VBIF_LATENCY_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_LATENCY_CYCLES', 1) +PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', 2) +PERF_CMPDECMP_VBIF_READ_DATA_CCU = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA_CCU', 3) +PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', 4) +PERF_CMPDECMP_VBIF_READ_REQUEST = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_REQUEST', 5) +PERF_CMPDECMP_VBIF_WRITE_REQUEST = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_REQUEST', 6) +PERF_CMPDECMP_VBIF_READ_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA', 7) +PERF_CMPDECMP_VBIF_WRITE_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_DATA', 8) +PERF_CMPDECMP_FLAG_FETCH_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_FLAG_FETCH_CYCLES', 9) +PERF_CMPDECMP_FLAG_FETCH_SAMPLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_FLAG_FETCH_SAMPLES', 10) +PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', 11) +PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', 12) +PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', 13) +PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', 14) +PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', 15) +PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', 16) +PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', 17) +PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', 18) +PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', 19) +PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', 20) +PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', 21) +PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', 22) +PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', 23) +PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', 24) +PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ', 25) +PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR', 26) +PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN', 27) +PERF_CMPDECMP_2D_RD_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_RD_DATA', 28) +PERF_CMPDECMP_2D_WR_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_WR_DATA', 29) +PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', 30) +PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', 31) +PERF_CMPDECMP_2D_OUTPUT_TRANS = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_OUTPUT_TRANS', 32) +PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', 33) +PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', 34) +PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', 35) +PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', 36) +PERF_CMPDECMP_2D_BUSY_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_BUSY_CYCLES', 37) +PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES', 38) +PERF_CMPDECMP_2D_PIXELS = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_PIXELS', 39) + +enum_a6xx_2d_ifmt = CEnum(ctypes.c_uint32) +R2D_UNORM8 = enum_a6xx_2d_ifmt.define('R2D_UNORM8', 16) +R2D_INT32 = enum_a6xx_2d_ifmt.define('R2D_INT32', 7) +R2D_INT16 = enum_a6xx_2d_ifmt.define('R2D_INT16', 6) +R2D_INT8 = enum_a6xx_2d_ifmt.define('R2D_INT8', 5) +R2D_FLOAT32 = enum_a6xx_2d_ifmt.define('R2D_FLOAT32', 4) +R2D_FLOAT16 = enum_a6xx_2d_ifmt.define('R2D_FLOAT16', 3) +R2D_UNORM8_SRGB = enum_a6xx_2d_ifmt.define('R2D_UNORM8_SRGB', 1) +R2D_RAW = enum_a6xx_2d_ifmt.define('R2D_RAW', 0) + +enum_a6xx_ztest_mode = CEnum(ctypes.c_uint32) +A6XX_EARLY_Z = enum_a6xx_ztest_mode.define('A6XX_EARLY_Z', 0) +A6XX_LATE_Z = enum_a6xx_ztest_mode.define('A6XX_LATE_Z', 1) +A6XX_EARLY_LRZ_LATE_Z = enum_a6xx_ztest_mode.define('A6XX_EARLY_LRZ_LATE_Z', 2) +A6XX_INVALID_ZTEST = enum_a6xx_ztest_mode.define('A6XX_INVALID_ZTEST', 3) + +enum_a6xx_tess_spacing = CEnum(ctypes.c_uint32) +TESS_EQUAL = enum_a6xx_tess_spacing.define('TESS_EQUAL', 0) +TESS_FRACTIONAL_ODD = enum_a6xx_tess_spacing.define('TESS_FRACTIONAL_ODD', 2) +TESS_FRACTIONAL_EVEN = enum_a6xx_tess_spacing.define('TESS_FRACTIONAL_EVEN', 3) + +enum_a6xx_tess_output = CEnum(ctypes.c_uint32) +TESS_POINTS = enum_a6xx_tess_output.define('TESS_POINTS', 0) +TESS_LINES = enum_a6xx_tess_output.define('TESS_LINES', 1) +TESS_CW_TRIS = enum_a6xx_tess_output.define('TESS_CW_TRIS', 2) +TESS_CCW_TRIS = enum_a6xx_tess_output.define('TESS_CCW_TRIS', 3) + +enum_a7xx_cp_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_CP_NEVER_COUNT = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_NEVER_COUNT', 0) +A7XX_PERF_CP_ALWAYS_COUNT = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ALWAYS_COUNT', 1) +A7XX_PERF_CP_BUSY_GFX_CORE_IDLE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_BUSY_GFX_CORE_IDLE', 2) +A7XX_PERF_CP_BUSY_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_BUSY_CYCLES', 3) +A7XX_PERF_CP_NUM_PREEMPTIONS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_NUM_PREEMPTIONS', 4) +A7XX_PERF_CP_PREEMPTION_REACTION_DELAY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREEMPTION_REACTION_DELAY', 5) +A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME', 6) +A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME', 7) +A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 8) +A7XX_PERF_CP_PREDICATED_DRAWS_KILLED = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREDICATED_DRAWS_KILLED', 9) +A7XX_PERF_CP_MODE_SWITCH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MODE_SWITCH', 10) +A7XX_PERF_CP_ZPASS_DONE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ZPASS_DONE', 11) +A7XX_PERF_CP_CONTEXT_DONE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CONTEXT_DONE', 12) +A7XX_PERF_CP_CACHE_FLUSH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CACHE_FLUSH', 13) +A7XX_PERF_CP_LONG_PREEMPTIONS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_LONG_PREEMPTIONS', 14) +A7XX_PERF_CP_SQE_I_CACHE_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_I_CACHE_STARVE', 15) +A7XX_PERF_CP_SQE_IDLE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_IDLE', 16) +A7XX_PERF_CP_SQE_PM4_STARVE_RB = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_RB', 17) +A7XX_PERF_CP_SQE_PM4_STARVE_IB1 = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_IB1', 18) +A7XX_PERF_CP_SQE_PM4_STARVE_IB2 = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_IB2', 19) +A7XX_PERF_CP_SQE_PM4_STARVE_IB3 = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_IB3', 20) +A7XX_PERF_CP_SQE_PM4_STARVE_FSDT = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_FSDT', 21) +A7XX_PERF_CP_SQE_PM4_STARVE_SDS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_SDS', 22) +A7XX_PERF_CP_SQE_MRB_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_MRB_STARVE', 23) +A7XX_PERF_CP_SQE_RRB_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_RRB_STARVE', 24) +A7XX_PERF_CP_SQE_VSD_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_VSD_STARVE', 25) +A7XX_PERF_CP_VSD_DECODE_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_VSD_DECODE_STARVE', 26) +A7XX_PERF_CP_SQE_PIPE_OUT_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PIPE_OUT_STALL', 27) +A7XX_PERF_CP_SQE_SYNC_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_SYNC_STALL', 28) +A7XX_PERF_CP_SQE_PM4_WFI_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_WFI_STALL', 29) +A7XX_PERF_CP_SQE_SYS_WFI_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_SYS_WFI_STALL', 30) +A7XX_PERF_CP_WAIT_ON_OTHER_PIPE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', 31) +A7XX_PERF_CP_OUTPUT_BLOCKED = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_OUTPUT_BLOCKED', 32) +A7XX_PERF_CP_SQE_T4_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_T4_EXEC', 33) +A7XX_PERF_CP_SQE_LOAD_STATE_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_LOAD_STATE_EXEC', 34) +A7XX_PERF_CP_SQE_SAVE_SDS_STATE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_SAVE_SDS_STATE', 35) +A7XX_PERF_CP_SQE_DRAW_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_DRAW_EXEC', 36) +A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 37) +A7XX_PERF_CP_SQE_EXEC_PROFILED = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_EXEC_PROFILED', 38) +A7XX_PERF_CP_MEMORY_POOL_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_EMPTY', 39) +A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', 40) +A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH', 41) +A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH', 42) +A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS', 43) +A7XX_PERF_CP_AHB_STALL_SQE_GMU = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_STALL_SQE_GMU', 44) +A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER', 45) +A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER', 46) +A7XX_PERF_CP_CLUSTER_FE_U_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_U_EMPTY', 47) +A7XX_PERF_CP_CLUSTER_FE_S_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_S_EMPTY', 48) +A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY', 49) +A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY', 50) +A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY', 51) +A7XX_PERF_CP_CLUSTER_GRAS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_GRAS_EMPTY', 52) +A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY', 53) +A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY', 54) +A7XX_PERF_CP_CLUSTER_PS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_PS_EMPTY', 55) +A7XX_PERF_CP_PM4_DATA = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PM4_DATA', 56) +A7XX_PERF_CP_PM4_HEADERS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PM4_HEADERS', 57) +A7XX_PERF_CP_VBIF_READ_BEATS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_VBIF_READ_BEATS', 58) +A7XX_PERF_CP_VBIF_WRITE_BEATS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_VBIF_WRITE_BEATS', 59) +A7XX_PERF_CP_SQE_INSTR_COUNTER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_INSTR_COUNTER', 60) +A7XX_PERF_CP_CLUSTER_FE_US_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_US_FULL', 61) +A7XX_PERF_CP_CLUSTER_FE_S_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_S_FULL', 62) +A7XX_PERF_CP_CLUSTER_SP_VS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_VS_FULL', 63) +A7XX_PERF_CP_CLUSTER_VPC_US_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_US_FULL', 64) +A7XX_PERF_CP_CLUSTER_VPC_VS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', 65) +A7XX_PERF_CP_CLUSTER_GRAS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_GRAS_FULL', 66) +A7XX_PERF_CP_CLUSTER_SP_PS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_PS_FULL', 67) +A7XX_PERF_CP_CLUSTER_VPC_PS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_PS_FULL', 68) +A7XX_PERF_CP_CLUSTER_PS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_PS_FULL', 69) +A7XX_PERF_CP_ICACHE_MISSES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ICACHE_MISSES', 70) +A7XX_PERF_CP_ICACHE_HITS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ICACHE_HITS', 71) +A7XX_PERF_CP_ICACHE_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ICACHE_STALL', 72) +A7XX_PERF_CP_DCACHE_MISSES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DCACHE_MISSES', 73) +A7XX_PERF_CP_DCACHE_HITS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DCACHE_HITS', 74) +A7XX_PERF_CP_DCACHE_STALLS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DCACHE_STALLS', 75) +A7XX_PERF_CP_AQE_SQE_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AQE_SQE_STALL', 76) +A7XX_PERF_CP_SQE_AQE_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_AQE_STARVE', 77) +A7XX_PERF_CP_ISR_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ISR_CYCLES', 78) +A7XX_PERF_CP_SQE_MD8_STALL_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_MD8_STALL_CYCLES', 79) +A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES', 80) +A7XX_PERF_CP_AQE_NUM_AS_CHUNKS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AQE_NUM_AS_CHUNKS', 81) +A7XX_PERF_CP_AQE_NUM_MS_CHUNKS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', 82) +A7XX_PERF_CP_S_SKEW_BUFFER_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_S_SKEW_BUFFER_FULL', 83) +A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH', 84) + +enum_a7xx_rbbm_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_RBBM_NEVER_COUNT = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_NEVER_COUNT', 0) +A7XX_PERF_RBBM_US_ALWAYS_COUNT = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_ALWAYS_COUNT', 1) +A7XX_PERF_RBBM_US_ALWAYS_ON = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_ALWAYS_ON', 2) +A7XX_PERF_RBBM_US_STATUS_MASKED = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_STATUS_MASKED', 3) +A7XX_PERF_RBBM_US_PC_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_PC_BUSY', 4) +A7XX_PERF_RBBM_US_COM_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_COM_BUSY', 5) +A7XX_PERF_RBBM_US_DCOM_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_DCOM_BUSY', 6) +A7XX_PERF_RBBM_US_VBIF_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_VBIF_BUSY', 7) +A7XX_PERF_RBBM_US_VSC_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_VSC_BUSY', 8) +A7XX_PERF_RBBM_US_UCHE_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_UCHE_BUSY', 9) +A7XX_PERF_RBBM_US_HLSQ_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_HLSQ_BUSY', 10) +A7XX_PERF_RBBM_S_HLSQ_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_HLSQ_BUSY', 11) +A7XX_PERF_RBBM_S_PC_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_PC_BUSY', 12) +A7XX_PERF_RBBM_S_TESS_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_TESS_BUSY', 13) +A7XX_PERF_RBBM_S_TSEFE_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_TSEFE_BUSY', 14) +A7XX_PERF_RBBM_S_TSEBE_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_TSEBE_BUSY', 15) +A7XX_PERF_RBBM_S_RAS_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_RAS_BUSY', 16) + +enum_a7xx_pc_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_PC_NEVER_COUNT = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_NEVER_COUNT', 0) +A7XX_PERF_PC_US_BUSY_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BUSY_CYCLES', 1) +A7XX_PERF_PC_US_WORKING_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_WORKING_CYCLES', 2) +A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS', 3) +A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES', 4) +A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX', 5) +A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF', 6) +A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM', 7) +A7XX_PERF_PC_US_STARVE_CYCLES_DI = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_DI', 8) +A7XX_PERF_PC_US_VIS_STREAMS_LOADED = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VIS_STREAMS_LOADED', 9) +A7XX_PERF_PC_US_INSTANCES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_INSTANCES', 10) +A7XX_PERF_PC_US_DEAD_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DEAD_PRIM', 11) +A7XX_PERF_PC_US_SLICE_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_SLICE_LIVE_PRIM', 12) +A7XX_PERF_PC_US_3D_DRAWCALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_3D_DRAWCALLS', 13) +A7XX_PERF_PC_US_2D_DRAWCALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_2D_DRAWCALLS', 14) +A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS', 15) +A7XX_PERF_PC_US_MESH_DRAWS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_DRAWS', 16) +A7XX_PERF_PC_US_MESH_DEAD_DRAWS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_DEAD_DRAWS', 17) +A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS', 18) +A7XX_PERF_PC_US_MESH_DEAD_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_DEAD_PRIM', 19) +A7XX_PERF_PC_US_MESH_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_LIVE_PRIM', 20) +A7XX_PERF_PC_US_MESH_PA_EN_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_PA_EN_PRIM', 21) +A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM', 22) +A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW', 23) +A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX', 24) +A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE', 25) +A7XX_PERF_PC_US_PREDRAW_STALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_PREDRAW_STALLS', 26) +A7XX_PERF_PC_US_DP0_INPUT_STALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP0_INPUT_STALLS', 27) +A7XX_PERF_PC_US_DP1_INPUT_STALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP1_INPUT_STALLS', 28) +A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD', 29) +A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD', 30) +A7XX_PERF_PC_US_PASSPAIR_STALL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_PASSPAIR_STALL', 31) +A7XX_PERF_PC_US_STALL_CYCLES_UCHE0 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_UCHE0', 32) +A7XX_PERF_PC_US_STALL_CYCLES_UCHE1 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_UCHE1', 33) +A7XX_PERF_PC_US_UCHE_0_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_UCHE_0_TRANS', 34) +A7XX_PERF_PC_US_UCHE_1_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_UCHE_1_TRANS', 35) +A7XX_PERF_PC_US_BV_STALLED_BY_ATTR = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STALLED_BY_ATTR', 36) +A7XX_PERF_PC_US_BV_STARVED_BY_RARB = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STARVED_BY_RARB', 37) +A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR', 38) +A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV', 39) +A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK', 40) +A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL', 41) +A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL', 42) +A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL', 43) +A7XX_PERF_PC_US_DP0_RARB_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP0_RARB_FULL', 44) +A7XX_PERF_PC_US_DP1_RARB_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP1_RARB_FULL', 45) +A7XX_PERF_PC_US_DP0_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP0_LIVE_PRIM', 46) +A7XX_PERF_PC_US_DP1_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP1_LIVE_PRIM', 47) +A7XX_PERF_PC_US_BV2BR_SWITCH = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV2BR_SWITCH', 48) +A7XX_PERF_PC_US_BR2BV_SWITCH = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BR2BV_SWITCH', 49) +A7XX_PERF_PC_US_STALL_CYCLES_PC_S = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_PC_S', 50) +A7XX_PERF_PC_RESERVED_51 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_51', 51) +A7XX_PERF_PC_RESERVED_52 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_52', 52) +A7XX_PERF_PC_RESERVED_53 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_53', 53) +A7XX_PERF_PC_RESERVED_54 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_54', 54) +A7XX_PERF_PC_RESERVED_55 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_55', 55) +A7XX_PERF_PC_RESERVED_56 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_56', 56) +A7XX_PERF_PC_RESERVED_57 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_57', 57) +A7XX_PERF_PC_RESERVED_58 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_58', 58) +A7XX_PERF_PC_RESERVED_59 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_59', 59) +A7XX_PERF_PC_S_BUSY_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_BUSY_CYCLES', 60) +A7XX_PERF_PC_S_WORKING_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_WORKING_CYCLES', 61) +A7XX_PERF_PC_S_STALL_CYCLES_VFD = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VFD', 62) +A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE', 63) +A7XX_PERF_PC_S_STALL_CYCLES_TESS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_TESS', 64) +A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY', 65) +A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY', 66) +A7XX_PERF_PC_S_VPC_PRIMITIVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_VPC_PRIMITIVES', 67) +A7XX_PERF_PC_S_VERTEX_HITS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_VERTEX_HITS', 68) +A7XX_PERF_PC_S_IA_VERTICES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_IA_VERTICES', 69) +A7XX_PERF_PC_S_IA_PRIMITIVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_IA_PRIMITIVES', 70) +A7XX_PERF_PC_S_HS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_HS_INVOCATIONS', 71) +A7XX_PERF_PC_S_DS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_DS_INVOCATIONS', 72) +A7XX_PERF_PC_S_VS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_VS_INVOCATIONS', 73) +A7XX_PERF_PC_S_GS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_GS_INVOCATIONS', 74) +A7XX_PERF_PC_S_DS_PRIMITIVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_DS_PRIMITIVES', 75) +A7XX_PERF_PC_S_TESS_BUSY_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_BUSY_CYCLES', 76) +A7XX_PERF_PC_S_TESS_WORKING_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_WORKING_CYCLES', 77) +A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC', 78) +A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC', 79) +A7XX_PERF_PC_S_TESS_SETUP_ACTIVE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_SETUP_ACTIVE', 80) +A7XX_PERF_PC_S_TESS_PID_ACTIVE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PID_ACTIVE', 81) +A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE', 82) +A7XX_PERF_PC_S_TESS_FACTOR_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_FACTOR_TRANS', 83) +A7XX_PERF_PC_S_TESS_PC_UV_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PC_UV_TRANS', 84) +A7XX_PERF_PC_S_TESS_PC_UV_PATCHES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PC_UV_PATCHES', 85) +A7XX_PERF_PC_S_MESH_VS_WAVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_MESH_VS_WAVES', 86) + +enum_a7xx_vfd_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_VFD_NEVER_COUNT = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_NEVER_COUNT', 0) +A7XX_PERF_VFD_BUSY_CYCLES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_BUSY_CYCLES', 1) +A7XX_PERF_VFD_STALL_CYCLES_UCHE = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_UCHE', 2) +A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC', 3) +A7XX_PERF_VFD_STALL_CYCLES_SP_INFO = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_SP_INFO', 4) +A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR', 5) +A7XX_PERF_VFD_STARVE_CYCLES_UCHE = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STARVE_CYCLES_UCHE', 6) +A7XX_PERF_VFD_RBUFFER_FULL = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_RBUFFER_FULL', 7) +A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', 8) +A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES', 9) +A7XX_PERF_VFD_NUM_ATTRIBUTES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_NUM_ATTRIBUTES', 10) +A7XX_PERF_VFD_UPPER_SHADER_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_UPPER_SHADER_FIBERS', 11) +A7XX_PERF_VFD_LOWER_SHADER_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_LOWER_SHADER_FIBERS', 12) +A7XX_PERF_VFD_MODE_0_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_0_FIBERS', 13) +A7XX_PERF_VFD_MODE_1_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_1_FIBERS', 14) +A7XX_PERF_VFD_MODE_2_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_2_FIBERS', 15) +A7XX_PERF_VFD_MODE_3_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_3_FIBERS', 16) +A7XX_PERF_VFD_MODE_4_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_4_FIBERS', 17) +A7XX_PERF_VFD_TOTAL_VERTICES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_TOTAL_VERTICES', 18) +A7XX_PERF_VFDP_STALL_CYCLES_VFD = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STALL_CYCLES_VFD', 19) +A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX', 20) +A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG', 21) +A7XX_PERF_VFDP_STARVE_CYCLES_PC = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STARVE_CYCLES_PC', 22) +A7XX_PERF_VFDP_VS_STAGE_WAVES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_VS_STAGE_WAVES', 23) +A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE', 24) +A7XX_PERF_VFD_STALL_CYCLES_CBSYNC = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_CBSYNC', 25) + +enum_a7xx_hlsq_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_HLSQ_NEVER_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_NEVER_COUNT', 0) +A7XX_PERF_HLSQ_BUSY_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BUSY_CYCLES', 1) +A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE', 2) +A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', 3) +A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES', 4) +A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT', 5) +A7XX_PERF_HLSQ_STALL_CYCLES_UCHE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_UCHE', 6) +A7XX_PERF_HLSQ_RESERVED_7 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_7', 7) +A7XX_PERF_HLSQ_RESERVED_8 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_8', 8) +A7XX_PERF_HLSQ_RESERVED_9 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_9', 9) +A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS', 10) +A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', 11) +A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 12) +A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE', 13) +A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO', 14) +A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO', 15) +A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD', 16) +A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', 17) +A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE', 18) +A7XX_PERF_HLSQ_RESERVED_19 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_19', 19) +A7XX_PERF_HLSQ_RESERVED_20 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_20', 20) +A7XX_PERF_HLSQ_VSBR_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_STALL_CYCLES', 21) +A7XX_PERF_HLSQ_FS_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_STALL_CYCLES', 22) +A7XX_PERF_HLSQ_LPAC_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_STALL_CYCLES', 23) +A7XX_PERF_HLSQ_BV_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_STALL_CYCLES', 24) +A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES', 25) +A7XX_PERF_HLSQ_FS_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_DEREF_CYCLES', 26) +A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES', 27) +A7XX_PERF_HLSQ_BV_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_DEREF_CYCLES', 28) +A7XX_PERF_HLSQ_VSBR_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_S2W_CYCLES', 29) +A7XX_PERF_HLSQ_FS_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_S2W_CYCLES', 30) +A7XX_PERF_HLSQ_LPAC_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_S2W_CYCLES', 31) +A7XX_PERF_HLSQ_BV_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_S2W_CYCLES', 32) +A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W', 33) +A7XX_PERF_HLSQ_FS_WAIT_VS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_WAIT_VS_S2W', 34) +A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W', 35) +A7XX_PERF_HLSQ_BV_WAIT_FS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_WAIT_FS_S2W', 36) +A7XX_PERF_HLSQ_RESERVED_37 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_37', 37) +A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W', 38) +A7XX_PERF_HLSQ_FS_STARVING_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_STARVING_SP', 39) +A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING', 40) +A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING', 41) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS', 42) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS', 43) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS', 44) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS', 45) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV', 46) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV', 47) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC', 48) +A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC', 49) +A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS', 50) +A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS', 51) +A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV', 52) +A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC', 53) +A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS', 54) +A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS', 55) +A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV', 56) +A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC', 57) +A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP', 58) +A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP', 59) +A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP', 60) +A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP', 61) +A7XX_PERF_HLSQ_L2STC_REQ_HLSQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_HLSQ', 62) +A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT', 63) +A7XX_PERF_HLSQ_L2STC_REQ_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_SP', 64) +A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT', 65) +A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ', 66) +A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT', 67) +A7XX_PERF_HLSQ_L2STC_REQ_INS_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_SP', 68) +A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT', 69) +A7XX_PERF_HLSQ_L2STC_REQ_UCHE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_UCHE', 70) +A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES', 71) +A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT', 72) +A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ', 73) +A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT', 74) +A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT', 75) +A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT', 76) +A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT', 77) +A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN', 78) +A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W', 79) +A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD', 80) +A7XX_PERF_HLSQ_STPROC_L0_INS_MISS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_MISS', 81) +A7XX_PERF_HLSQ_STPROC_L0_INS_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_HIT', 82) +A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT', 83) +A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE', 84) +A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT', 85) +A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE', 86) +A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ', 87) +A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ', 88) +A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING', 89) +A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY', 90) +A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY', 91) +A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL', 92) +A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL', 93) +A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI', 94) +A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI', 95) +A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI', 96) +A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI', 97) +A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI', 98) +A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI', 99) +A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI', 100) +A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI', 101) +A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI', 102) +A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI', 103) +A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI', 104) +A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI', 105) +A7XX_PERF_HLSQ_PRIMITIVE_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_PRIMITIVE_COUNT', 106) +A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT', 107) +A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT', 108) +A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC', 109) +A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC', 110) +A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC', 111) + +enum_a7xx_vpc_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_VPC_NEVER_COUNT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_NEVER_COUNT', 0) +A7XX_PERF_VPC_FE_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_BUSY_CYCLES', 1) +A7XX_PERF_VPC_FE_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_WORKING_CYCLES', 2) +A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK', 3) +A7XX_PERF_VPC_FE_STARVE_CYCLES_SP = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STARVE_CYCLES_SP', 4) +A7XX_PERF_VPC_FE_PC_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_PC_PRIMITIVES', 5) +A7XX_PERF_VPC_FE_SP_COMPONENTS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_SP_COMPONENTS', 6) +A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS', 7) +A7XX_PERF_VPC_FE_VS_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_VS_BUSY_CYCLES', 8) +A7XX_PERF_VPC_FE_VS_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_VS_WORKING_CYCLES', 9) +A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS', 10) +A7XX_PERF_VPC_FE_WIT_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_WIT_FULL_CYCLES', 11) +A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES', 12) +A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE', 13) +A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE', 14) +A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US', 15) +A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES', 16) +A7XX_PERF_VPC_FE_GS_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_GS_PRIMITIVES', 17) +A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS', 18) +A7XX_PERF_VPC_FE_STALL_CYCLES_CCU = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_CCU', 19) +A7XX_PERF_VPC_FE_NUM_WM_HIT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_NUM_WM_HIT', 20) +A7XX_PERF_VPC_FE_STALL_DQ_WACK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_DQ_WACK', 21) +A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE', 22) +A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS', 23) +A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES', 24) +A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES', 25) +A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES', 26) +A7XX_PERF_VPC_FE_BOTTLENECK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_BOTTLENECK', 27) +A7XX_PERF_VPC_US_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_BUSY_CYCLES', 28) +A7XX_PERF_VPC_US_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_WORKING_CYCLES', 29) +A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE', 30) +A7XX_PERF_VPC_US_PTUS_FULL = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_PTUS_FULL', 31) +A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT', 32) +A7XX_PERF_VPC_US_STALL_CYCLES_VSC = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_VSC', 33) +A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE', 34) +A7XX_PERF_VPC_US_STALL_CYCLES_UCHE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_UCHE', 35) +A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION', 36) +A7XX_PERF_VPC_US_NUM_GMEM_READ_SO = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', 37) +A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD', 38) +A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS', 39) +A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER', 40) +A7XX_PERF_VPC_US_BOTTLENECK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_BOTTLENECK', 41) +A7XX_PERF_VPC_RESERVED_42 = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_RESERVED_42', 42) +A7XX_PERF_VPC_RESERVED_43 = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_RESERVED_43', 43) +A7XX_PERF_VPC_RESERVED_44 = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_RESERVED_44', 44) +A7XX_PERF_VPC_BE_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_BUSY_CYCLES', 45) +A7XX_PERF_VPC_BE_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_WORKING_CYCLES', 46) +A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE', 47) +A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES', 48) +A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS', 49) +A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ', 50) +A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES', 51) +A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES', 52) +A7XX_PERF_VPC_BE_STARVE_CYCLES_RB = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STARVE_CYCLES_RB', 53) +A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC', 54) +A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM', 55) +A7XX_PERF_VPC_BE_NUM_PA_REQ = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_NUM_PA_REQ', 56) +A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', 57) +A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM', 58) +A7XX_PERF_VPC_BE_LM_TRANSACTION = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_LM_TRANSACTION', 59) +A7XX_PERF_VPC_BE_PS_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_PS_BUSY_CYCLES', 60) +A7XX_PERF_VPC_BE_PS_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_PS_WORKING_CYCLES', 61) +A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE', 62) +A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE', 63) +A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END', 64) +A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL', 65) +A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ', 66) +A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK', 67) +A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS', 68) +A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR', 69) +A7XX_PERF_VPC_BE_BOTTLENECK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_BOTTLENECK', 70) + +enum_a7xx_tse_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_TSE_NEVER_COUNT = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_NEVER_COUNT', 0) +A7XX_PERF_TSE_BE_BUSY_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BUSY_CYCLES', 1) +A7XX_PERF_TSE_BE_CLIPPING_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CLIPPING_CYCLES', 2) +A7XX_PERF_TSE_BE_STALL_CYCLES_RAS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_RAS', 3) +A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE', 4) +A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE', 5) +A7XX_PERF_TSE_BE_STARVE_CYCLES_PC = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STARVE_CYCLES_PC', 6) +A7XX_PERF_TSE_BE_INPUT_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_INPUT_PRIM', 7) +A7XX_PERF_TSE_BE_INPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', 8) +A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM', 9) +A7XX_PERF_TSE_BE_CLIPPED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CLIPPED_PRIM', 10) +A7XX_PERF_TSE_BE_ZERO_AREA_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ZERO_AREA_PRIM', 11) +A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM', 12) +A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM', 13) +A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM', 14) +A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM', 15) +A7XX_PERF_TSE_BE_CINVOCATION = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CINVOCATION', 16) +A7XX_PERF_TSE_BE_CPRIMITIVES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CPRIMITIVES', 17) +A7XX_PERF_TSE_BE_2D_INPUT_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_2D_INPUT_PRIM', 18) +A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES', 19) +A7XX_PERF_TSE_BE_CLIP_PLANES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CLIP_PLANES', 20) +A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM', 21) +A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS', 22) +A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS', 23) +A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', 24) +A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM', 25) +A7XX_PERF_TSE_BE_VP_OUT_IS_NAN = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_VP_OUT_IS_NAN', 26) +A7XX_PERF_TSE_BE_EXCLUDED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_EXCLUDED_PRIM', 27) +A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM', 28) +A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP', 29) +A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY', 30) +A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP', 31) +A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY', 32) +A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR', 33) +A7XX_PERF_TSE_FE_BUSY_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BUSY_CYCLES', 34) +A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US', 35) +A7XX_PERF_TSE_FE_STARVE_CYCLES_PC = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_STARVE_CYCLES_PC', 36) +A7XX_PERF_TSE_FE_INPUT_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_INPUT_PRIM', 37) +A7XX_PERF_TSE_FE_INPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', 38) +A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM', 39) +A7XX_PERF_TSE_FE_ZERO_AREA_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ZERO_AREA_PRIM', 40) +A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM', 41) +A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', 42) +A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM', 43) +A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM', 44) +A7XX_PERF_TSE_FE_CINVOCATION = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_CINVOCATION', 45) +A7XX_PERF_TSE_FE_CPRIMITIVES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_CPRIMITIVES', 46) +A7XX_PERF_TSE_FE_CLIP_PLANES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_CLIP_PLANES', 47) +A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM', 48) +A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS', 49) +A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS', 50) +A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', 51) +A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM', 52) +A7XX_PERF_TSE_FE_VP_OUT_IS_NAN = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_VP_OUT_IS_NAN', 53) +A7XX_PERF_TSE_FE_EXCLUDED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_EXCLUDED_PRIM', 54) +A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM', 55) +A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP', 56) +A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY', 57) +A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP', 58) +A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY', 59) +A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR', 60) +A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM', 61) + +enum_a7xx_ras_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_RAS_NEVER_COUNT = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_NEVER_COUNT', 0) +A7XX_PERF_RAS_BUSY_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_BUSY_CYCLES', 1) +A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES', 2) +A7XX_PERF_RAS_STALL_CYCLES_LRZ = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_STALL_CYCLES_LRZ', 3) +A7XX_PERF_RAS_STARVE_CYCLES_TSE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_STARVE_CYCLES_TSE', 4) +A7XX_PERF_RAS_SUPER_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SUPER_TILES', 5) +A7XX_PERF_RAS_8X4_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_8X4_TILES', 6) +A7XX_PERF_RAS_MASKGEN_ACTIVE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_MASKGEN_ACTIVE', 7) +A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES', 8) +A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES', 9) +A7XX_PERF_RAS_PRIM_KILLED_INVISILBE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_PRIM_KILLED_INVISILBE', 10) +A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 11) +A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES', 12) +A7XX_PERF_RAS_BLOCKS = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_BLOCKS', 13) +A7XX_PERF_RAS_FALSE_PARTIAL_STILE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_FALSE_PARTIAL_STILE', 14) +A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY', 15) +A7XX_PERF_RAS_SLICE_BLOCK_EMPTY = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SLICE_BLOCK_EMPTY', 16) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2', 17) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2', 18) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2', 19) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2', 20) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2', 21) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2', 22) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2', 23) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2', 24) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2', 25) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2', 26) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2', 27) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2', 28) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2', 29) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2', 30) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2', 31) +A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2', 32) + +enum_a7xx_uche_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_UCHE_NEVER_COUNT = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_NEVER_COUNT', 0) +A7XX_PERF_UCHE_BUSY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BUSY_CYCLES', 1) +A7XX_PERF_UCHE_STALL_CYCLES_ARBITER = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_STALL_CYCLES_ARBITER', 2) +A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA', 3) +A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP', 4) +A7XX_PERF_UCHE_STALL_CYCLES_DECMP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_STALL_CYCLES_DECMP', 5) +A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF', 6) +A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES', 7) +A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES', 8) +A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', 9) +A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES', 10) +A7XX_PERF_UCHE_READ_REQUESTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_SP', 11) +A7XX_PERF_UCHE_READ_REQUESTS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP', 12) +A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC', 13) +A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF', 14) +A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM', 15) +A7XX_PERF_UCHE_READ_REQUESTS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VFD', 16) +A7XX_PERF_UCHE_READ_REQUESTS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VPC', 17) +A7XX_PERF_UCHE_READ_REQUESTS_HLSQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_HLSQ', 18) +A7XX_PERF_UCHE_READ_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_LRZ', 19) +A7XX_PERF_UCHE_READ_REQUESTS_PC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_PC', 20) +A7XX_PERF_UCHE_WRITE_REQUESTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_SP', 21) +A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ', 22) +A7XX_PERF_UCHE_WRITE_REQUESTS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_VPC', 23) +A7XX_PERF_UCHE_WRITE_REQUESTS_VSC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', 24) +A7XX_PERF_UCHE_VBIF_READ_BEATS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_SP', 25) +A7XX_PERF_UCHE_VBIF_READ_BEATS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_TP', 26) +A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD', 27) +A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC', 28) +A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ', 29) +A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ', 30) +A7XX_PERF_UCHE_VBIF_READ_BEATS_PC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_PC', 31) +A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0', 32) +A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1', 33) +A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0', 34) +A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1', 35) +A7XX_PERF_UCHE_GMEM_READ_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_GMEM_READ_BEATS', 36) +A7XX_PERF_UCHE_GMEM_WRITE_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_GMEM_WRITE_BEATS', 37) +A7XX_PERF_UCHE_UBWC_READ_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_UBWC_READ_BEATS', 38) +A7XX_PERF_UCHE_UBWC_WRITE_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_UBWC_WRITE_BEATS', 39) +A7XX_PERF_UCHE_EVICTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_EVICTS', 40) +A7XX_PERF_UCHE_BANK_REQ0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ0', 41) +A7XX_PERF_UCHE_BANK_REQ1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ1', 42) +A7XX_PERF_UCHE_BANK_REQ2 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ2', 43) +A7XX_PERF_UCHE_BANK_REQ3 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ3', 44) +A7XX_PERF_UCHE_BANK_REQ4 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ4', 45) +A7XX_PERF_UCHE_BANK_REQ5 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ5', 46) +A7XX_PERF_UCHE_BANK_REQ6 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ6', 47) +A7XX_PERF_UCHE_BANK_REQ7 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ7', 48) +A7XX_PERF_UCHE_TPH_REF_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_REF_FULL', 49) +A7XX_PERF_UCHE_TPH_VICTIM_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_VICTIM_FULL', 50) +A7XX_PERF_UCHE_TPH_EXT_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_EXT_FULL', 51) +A7XX_PERF_UCHE_RAM_READ_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RAM_READ_REQ', 52) +A7XX_PERF_UCHE_RAM_WRITE_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RAM_WRITE_REQ', 53) +A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS', 54) +A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS', 55) +A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE', 56) +A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER', 57) +A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE', 58) +A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS', 59) +A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL', 60) +A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL', 61) +A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL', 62) +A7XX_PERF_UCHE_EVICTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_EVICTS_SP', 63) +A7XX_PERF_UCHE_EVICTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_EVICTS_LRZ', 64) +A7XX_PERF_UCHE_READ_REQUESTS_VPCUS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VPCUS', 65) +A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV', 66) +A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR', 67) +A7XX_PERF_BYPC_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPC_FULL', 68) +A7XX_PERF_BYPC_FULL_CCHE_STALL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPC_FULL_CCHE_STALL', 69) +A7XX_PERF_BYPC_VHUB_STALL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPC_VHUB_STALL', 70) +A7XX_PERF_BYPD_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPD_FULL', 71) +A7XX_PERF_BYPD_FULL_GBIF_STALL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPD_FULL_GBIF_STALL', 72) +A7XX_PERF_VHUB_PTABLE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_VHUB_PTABLE_FULL', 73) +A7XX_PERF_DHUB_PTABLE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_DHUB_PTABLE_FULL', 74) +A7XX_PERF_UCHE_RESERVED_75 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_75', 75) +A7XX_PERF_UCHE_RESERVED_76 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_76', 76) +A7XX_PERF_UCHE_RESERVED_77 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_77', 77) +A7XX_PERF_UCHE_RESERVED_78 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_78', 78) +A7XX_PERF_UCHE_RESERVED_79 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_79', 79) +A7XX_PERF_UCHE_RESERVED_80 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_80', 80) +A7XX_PERF_UCHE_RESERVED_81 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_81', 81) +A7XX_PERF_UCHE_RESERVED_82 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_82', 82) +A7XX_PERF_UCHE_RESERVED_83 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_83', 83) +A7XX_PERF_UCHE_RESERVED_84 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_84', 84) +A7XX_PERF_UCHE_RESERVED_85 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_85', 85) +A7XX_PERF_UCHE_RESERVED_86 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_86', 86) +A7XX_PERF_UCHE_RESERVED_87 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_87', 87) +A7XX_PERF_UCHE_RESERVED_88 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_88', 88) +A7XX_PERF_UCHE_RESERVED_89 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_89', 89) +A7XX_PERF_UCHE_RESERVED_90 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_90', 90) +A7XX_PERF_UCHE_RESERVED_91 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_91', 91) +A7XX_PERF_UCHE_RESERVED_92 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_92', 92) +A7XX_PERF_UCHE_RESERVED_93 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_93', 93) +A7XX_PERF_UCHE_RESERVED_94 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_94', 94) +A7XX_PERF_UCHE_RESERVED_95 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_95', 95) +A7XX_PERF_UCHE_RESERVED_96 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_96', 96) +A7XX_PERF_UCHE_RESERVED_97 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_97', 97) +A7XX_PERF_UCHE_RESERVED_98 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_98', 98) +A7XX_PERF_UCHE_RESERVED_99 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_99', 99) +A7XX_PERF_UCHE_RESERVED_100 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_100', 100) +A7XX_PERF_UCHE_RESERVED_101 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_101', 101) +A7XX_PERF_UCHE_RESERVED_102 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_102', 102) +A7XX_PERF_UCHE_RESERVED_103 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_103', 103) +A7XX_PERF_UCHE_RESERVED_104 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_104', 104) +A7XX_PERF_UCHE_RESERVED_105 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_105', 105) +A7XX_PERF_UCHE_RESERVED_106 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_106', 106) +A7XX_PERF_UCHE_RESERVED_107 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_107', 107) +A7XX_PERF_UCHE_RESERVED_108 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_108', 108) +A7XX_PERF_UCHE_RESERVED_109 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_109', 109) +A7XX_PERF_UCHE_RESERVED_110 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_110', 110) +A7XX_PERF_UCHE_RESERVED_111 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_111', 111) +A7XX_PERF_UCHE_RESERVED_112 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_112', 112) +A7XX_PERF_UCHE_RESERVED_113 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_113', 113) +A7XX_PERF_UCHE_RESERVED_114 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_114', 114) +A7XX_PERF_UCHE_RESERVED_115 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_115', 115) +A7XX_PERF_UCHE_RESERVED_116 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_116', 116) +A7XX_PERF_UCHE_RESERVED_117 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_117', 117) +A7XX_PERF_UCHE_RESERVED_118 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_118', 118) +A7XX_PERF_UCHE_RESERVED_119 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_119', 119) +A7XX_PERF_UCHE_RESERVED_120 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_120', 120) +A7XX_PERF_UCHE_RESERVED_121 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_121', 121) +A7XX_PERF_UCHE_RESERVED_122 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_122', 122) +A7XX_PERF_UCHE_RESERVED_123 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_123', 123) +A7XX_PERF_UCHE_RESERVED_124 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_124', 124) +A7XX_PERF_UCHE_RESERVED_125 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_125', 125) +A7XX_PERF_UCHE_RESERVED_126 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_126', 126) +A7XX_PERF_UCHE_RESERVED_127 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_127', 127) +A7XX_PERF_CCHE_BUSY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BUSY_CYCLES', 128) +A7XX_PERF_CCHE_STALL_CYCLES_UCHE = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_STALL_CYCLES_UCHE', 129) +A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA', 130) +A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES', 131) +A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES', 132) +A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL', 133) +A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC', 134) +A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF', 135) +A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM', 136) +A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL', 137) +A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC', 138) +A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF', 139) +A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM', 140) +A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL', 141) +A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM', 142) +A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF', 143) +A7XX_PERF_CCHE_READ_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_LRZ', 144) +A7XX_PERF_CCHE_READ_REQUESTS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_VPC', 145) +A7XX_PERF_CCHE_WRITE_REQUESTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WRITE_REQUESTS_SP', 146) +A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ', 147) +A7XX_PERF_CCHE_READ_REQUESTS_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_GMEM', 148) +A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM', 149) +A7XX_PERF_CCHE_UCHE_READ_BEATS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_TP', 150) +A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD', 151) +A7XX_PERF_CCHE_UCHE_READ_BEATS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_SP', 152) +A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC', 153) +A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ', 154) +A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0', 155) +A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1', 156) +A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC', 157) +A7XX_PERF_CCHE_GMEM_READ_BEATS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_TP', 158) +A7XX_PERF_CCHE_GMEM_READ_BEATS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_SP', 159) +A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD', 160) +A7XX_PERF_CCHE_BANK_REQ0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ0', 161) +A7XX_PERF_CCHE_BANK_REQ1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ1', 162) +A7XX_PERF_CCHE_BANK_REQ2 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ2', 163) +A7XX_PERF_CCHE_BANK_REQ3 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ3', 164) +A7XX_PERF_CCHE_BANK_REQ4 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ4', 165) +A7XX_PERF_CCHE_BANK_REQ5 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ5', 166) +A7XX_PERF_CCHE_BANK_REQ6 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ6', 167) +A7XX_PERF_CCHE_BANK_REQ7 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ7', 168) +A7XX_PERF_CCHE_BANK_REQ8 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ8', 169) +A7XX_PERF_CCHE_BANK_REQ9 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ9', 170) +A7XX_PERF_CCHE_BANK_REQ10 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ10', 171) +A7XX_PERF_CCHE_BANK_REQ11 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ11', 172) +A7XX_PERF_CCHE_BANK_REQ12 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ12', 173) +A7XX_PERF_CCHE_BANK_REQ13 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ13', 174) +A7XX_PERF_CCHE_BANK_REQ14 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ14', 175) +A7XX_PERF_CCHE_BANK_REQ15 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ15', 176) +A7XX_PERF_CCHE_GBANK_REQ0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ0', 177) +A7XX_PERF_CCHE_GBANK_REQ1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ1', 178) +A7XX_PERF_CCHE_GBANK_REQ2 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ2', 179) +A7XX_PERF_CCHE_GBANK_REQ3 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ3', 180) +A7XX_PERF_CCHE_TPH_REF_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_REF_FULL', 181) +A7XX_PERF_CCHE_TPH_VICTIM_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_VICTIM_FULL', 182) +A7XX_PERF_CCHE_TPH_EXT_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_EXT_FULL', 183) +A7XX_PERF_CCHE_RAM_READ_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_RAM_READ_REQ', 184) +A7XX_PERF_CCHE_RAM_WRITE_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_RAM_WRITE_REQ', 185) +A7XX_PERF_CCHE_TPH_CONFLICT_CL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_CONFLICT_CL', 186) +A7XX_PERF_CCHE_DBANK_CONFLICT = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_DBANK_CONFLICT', 187) +A7XX_PERF_CCHE_TPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_QUEUE_FULL', 188) +A7XX_PERF_CCHE_DPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_DPH_QUEUE_FULL', 189) +A7XX_PERF_CCHE_OPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_OPH_QUEUE_FULL', 190) +A7XX_PERF_CCHE_WACK_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WACK_QUEUE_FULL', 191) +A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST', 192) +A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST', 193) +A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST', 194) +A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST', 195) +A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST', 196) +A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST', 197) +A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST', 198) +A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST', 199) +A7XX_PERF_CCHE_STALL_CYCLES_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_STALL_CYCLES_TP', 200) + +enum_a7xx_tp_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_TP_NEVER_COUNT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_NEVER_COUNT', 0) +A7XX_PERF_TP_BUSY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_BUSY_CYCLES', 1) +A7XX_PERF_TP_STALL_CYCLES_UCHE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STALL_CYCLES_UCHE', 2) +A7XX_PERF_TP_LATENCY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_LATENCY_CYCLES', 3) +A7XX_PERF_TP_LATENCY_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_LATENCY_TRANS', 4) +A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES', 5) +A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES', 6) +A7XX_PERF_TP_L1_CACHELINE_REQUESTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_CACHELINE_REQUESTS', 7) +A7XX_PERF_TP_L1_CACHELINE_MISSES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_CACHELINE_MISSES', 8) +A7XX_PERF_TP_SP_TP_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_SP_TP_TRANS', 9) +A7XX_PERF_TP_TP_SP_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_TP_SP_TRANS', 10) +A7XX_PERF_TP_OUTPUT_PIXELS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS', 11) +A7XX_PERF_TP_FILTER_WORKLOAD_16BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_WORKLOAD_16BIT', 12) +A7XX_PERF_TP_FILTER_WORKLOAD_32BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_WORKLOAD_32BIT', 13) +A7XX_PERF_TP_QUADS_RECEIVED = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_RECEIVED', 14) +A7XX_PERF_TP_QUADS_OFFSET = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_OFFSET', 15) +A7XX_PERF_TP_QUADS_SHADOW = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_SHADOW', 16) +A7XX_PERF_TP_QUADS_ARRAY = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_ARRAY', 17) +A7XX_PERF_TP_QUADS_GRADIENT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_GRADIENT', 18) +A7XX_PERF_TP_QUADS_1D = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_1D', 19) +A7XX_PERF_TP_QUADS_2D = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_2D', 20) +A7XX_PERF_TP_QUADS_BUFFER = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_BUFFER', 21) +A7XX_PERF_TP_QUADS_3D = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_3D', 22) +A7XX_PERF_TP_QUADS_CUBE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_CUBE', 23) +A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED', 24) +A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', 25) +A7XX_PERF_TP_OUTPUT_PIXELS_POINT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_POINT', 26) +A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR', 27) +A7XX_PERF_TP_OUTPUT_PIXELS_MIP = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_MIP', 28) +A7XX_PERF_TP_OUTPUT_PIXELS_ANISO = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_ANISO', 29) +A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD', 30) +A7XX_PERF_TP_FLAG_CACHE_REQUESTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_CACHE_REQUESTS', 31) +A7XX_PERF_TP_FLAG_CACHE_MISSES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_CACHE_MISSES', 32) +A7XX_PERF_TP_L1_5_L2_REQUESTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_L2_REQUESTS', 33) +A7XX_PERF_TP_2D_OUTPUT_PIXELS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_OUTPUT_PIXELS', 34) +A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT', 35) +A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', 36) +A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT', 37) +A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT', 38) +A7XX_PERF_TP_TPA2TPC_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_TPA2TPC_TRANS', 39) +A7XX_PERF_TP_L1_MISSES_ASTC_1TILE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_MISSES_ASTC_1TILE', 40) +A7XX_PERF_TP_L1_MISSES_ASTC_2TILE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_MISSES_ASTC_2TILE', 41) +A7XX_PERF_TP_L1_MISSES_ASTC_4TILE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_MISSES_ASTC_4TILE', 42) +A7XX_PERF_TP_L1_5_COMPRESS_REQS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_COMPRESS_REQS', 43) +A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS', 44) +A7XX_PERF_TP_L1_BANK_CONFLICT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_BANK_CONFLICT', 45) +A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES', 46) +A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS', 47) +A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED', 48) +A7XX_PERF_TP_FRONTEND_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FRONTEND_WORKING_CYCLES', 49) +A7XX_PERF_TP_L1_TAG_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_TAG_WORKING_CYCLES', 50) +A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', 51) +A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', 52) +A7XX_PERF_TP_BACKEND_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_BACKEND_WORKING_CYCLES', 53) +A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES', 54) +A7XX_PERF_TP_STARVE_CYCLES_SP = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STARVE_CYCLES_SP', 55) +A7XX_PERF_TP_STARVE_CYCLES_UCHE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STARVE_CYCLES_UCHE', 56) +A7XX_PERF_TP_STALL_CYCLES_UFC = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STALL_CYCLES_UFC', 57) +A7XX_PERF_TP_FORMAT_DECOMP_POINT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FORMAT_DECOMP_POINT', 58) +A7XX_PERF_TP_FILTER_POINT_FP16 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_POINT_FP16', 59) +A7XX_PERF_TP_FILTER_POINT_FP32 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_POINT_FP32', 60) +A7XX_PERF_TP_LATENCY_FIFO_FULL = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_LATENCY_FIFO_FULL', 61) +A7XX_PERF_TP_RESERVED_62 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_62', 62) +A7XX_PERF_TP_RESERVED_63 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_63', 63) +A7XX_PERF_TP_RESERVED_64 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_64', 64) +A7XX_PERF_TP_RESERVED_65 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_65', 65) +A7XX_PERF_TP_RESERVED_66 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_66', 66) +A7XX_PERF_TP_RESERVED_67 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_67', 67) +A7XX_PERF_TP_RESERVED_68 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_68', 68) +A7XX_PERF_TP_RESERVED_69 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_69', 69) +A7XX_PERF_TP_RESERVED_70 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_70', 70) +A7XX_PERF_TP_RESERVED_71 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_71', 71) +A7XX_PERF_TP_RESERVED_72 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_72', 72) +A7XX_PERF_TP_RESERVED_73 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_73', 73) +A7XX_PERF_TP_RESERVED_74 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_74', 74) +A7XX_PERF_TP_RESERVED_75 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_75', 75) +A7XX_PERF_TP_RESERVED_76 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_76', 76) +A7XX_PERF_TP_RESERVED_77 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_77', 77) +A7XX_PERF_TP_RESERVED_78 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_78', 78) +A7XX_PERF_TP_RESERVED_79 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_79', 79) +A7XX_PERF_TP_RESERVED_80 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_80', 80) +A7XX_PERF_TP_RESERVED_81 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_81', 81) +A7XX_PERF_TP_RESERVED_82 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_82', 82) +A7XX_PERF_TP_RESERVED_83 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_83', 83) +A7XX_PERF_TP_RESERVED_84 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_84', 84) +A7XX_PERF_TP_RESERVED_85 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_85', 85) +A7XX_PERF_TP_RESERVED_86 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_86', 86) +A7XX_PERF_TP_RESERVED_87 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_87', 87) +A7XX_PERF_TP_RESERVED_88 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_88', 88) +A7XX_PERF_TP_RESERVED_89 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_89', 89) +A7XX_PERF_TP_RESERVED_90 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_90', 90) +A7XX_PERF_TP_RESERVED_91 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_91', 91) +A7XX_PERF_TP_RESERVED_92 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_92', 92) +A7XX_PERF_TP_RESERVED_93 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_93', 93) +A7XX_PERF_TP_RESERVED_94 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_94', 94) +A7XX_PERF_TP_RESERVED_95 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_95', 95) +A7XX_PERF_TP_RESERVED_96 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_96', 96) +A7XX_PERF_TP_RESERVED_97 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_97', 97) +A7XX_PERF_TP_RESERVED_98 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_98', 98) +A7XX_PERF_TP_RESERVED_99 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_99', 99) +A7XX_PERF_TP_RESERVED_100 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_100', 100) +A7XX_PERF_TP_RESERVED_101 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_101', 101) +A7XX_PERF_TP_RESERVED_102 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_102', 102) +A7XX_PERF_TP_RESERVED_103 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_103', 103) +A7XX_PERF_TP_RESERVED_104 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_104', 104) +A7XX_PERF_TP_RESERVED_105 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_105', 105) +A7XX_PERF_TP_RESERVED_106 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_106', 106) +A7XX_PERF_TP_RESERVED_107 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_107', 107) +A7XX_PERF_TP_RESERVED_108 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_108', 108) +A7XX_PERF_TP_RESERVED_109 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_109', 109) +A7XX_PERF_TP_RESERVED_110 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_110', 110) +A7XX_PERF_TP_RESERVED_111 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_111', 111) +A7XX_PERF_TP_RESERVED_112 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_112', 112) +A7XX_PERF_TP_RESERVED_113 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_113', 113) +A7XX_PERF_TP_RESERVED_114 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_114', 114) +A7XX_PERF_TP_RESERVED_115 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_115', 115) +A7XX_PERF_TP_RESERVED_116 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_116', 116) +A7XX_PERF_TP_RESERVED_117 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_117', 117) +A7XX_PERF_TP_RESERVED_118 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_118', 118) +A7XX_PERF_TP_RESERVED_119 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_119', 119) +A7XX_PERF_TP_RESERVED_120 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_120', 120) +A7XX_PERF_TP_RESERVED_121 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_121', 121) +A7XX_PERF_TP_RESERVED_122 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_122', 122) +A7XX_PERF_TP_RESERVED_123 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_123', 123) +A7XX_PERF_TP_RESERVED_124 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_124', 124) +A7XX_PERF_TP_RESERVED_125 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_125', 125) +A7XX_PERF_TP_RESERVED_126 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_126', 126) +A7XX_PERF_TP_RESERVED_127 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_127', 127) +A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR', 128) +A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16', 129) +A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16', 130) +A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32', 131) +A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32', 132) + +enum_a7xx_sp_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_SP_NEVER_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_NEVER_COUNT', 0) +A7XX_PERF_SP_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BUSY_CYCLES', 1) +A7XX_PERF_SP_ALU_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ALU_WORKING_CYCLES', 2) +A7XX_PERF_SP_STALL_CYCLES_VPC_BE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_VPC_BE', 3) +A7XX_PERF_SP_STALL_CYCLES_TP = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_TP', 4) +A7XX_PERF_SP_STALL_CYCLES_UCHE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_UCHE', 5) +A7XX_PERF_SP_STALL_CYCLES_RB = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_RB', 6) +A7XX_PERF_SP_NON_EXECUTION_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_NON_EXECUTION_CYCLES', 7) +A7XX_PERF_SP_WAVE_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CONTEXTS', 8) +A7XX_PERF_SP_WAVE_CONTEXT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CONTEXT_CYCLES', 9) +A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES', 10) +A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES', 11) +A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES', 12) +A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES', 13) +A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES', 14) +A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES', 15) +A7XX_PERF_SP_WAVE_CTRL_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CTRL_CYCLES', 16) +A7XX_PERF_SP_WAVE_LOAD_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_LOAD_CYCLES', 17) +A7XX_PERF_SP_WAVE_EMIT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_EMIT_CYCLES', 18) +A7XX_PERF_SP_WAVE_NOP_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_NOP_CYCLES', 19) +A7XX_PERF_SP_WAVE_WAIT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_WAIT_CYCLES', 20) +A7XX_PERF_SP_WAVE_FETCH_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_FETCH_CYCLES', 21) +A7XX_PERF_SP_WAVE_IDLE_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_IDLE_CYCLES', 22) +A7XX_PERF_SP_WAVE_END_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_END_CYCLES', 23) +A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES', 24) +A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES', 25) +A7XX_PERF_SP_WAVE_JOIN_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_JOIN_CYCLES', 26) +A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS', 27) +A7XX_PERF_SP_LM_STORE_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_STORE_INSTRUCTIONS', 28) +A7XX_PERF_SP_LM_ATOMICS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_ATOMICS', 29) +A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS', 30) +A7XX_PERF_SP_GM_STORE_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', 31) +A7XX_PERF_SP_GM_ATOMICS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_ATOMICS', 32) +A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', 33) +A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', 34) +A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', 35) +A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', 36) +A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', 37) +A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', 38) +A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', 39) +A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', 40) +A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', 41) +A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', 42) +A7XX_PERF_SP_VS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_INSTRUCTIONS', 43) +A7XX_PERF_SP_FS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_INSTRUCTIONS', 44) +A7XX_PERF_SP_ADDR_LOCK_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ADDR_LOCK_COUNT', 45) +A7XX_PERF_SP_UCHE_READ_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_UCHE_READ_TRANS', 46) +A7XX_PERF_SP_UCHE_WRITE_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_UCHE_WRITE_TRANS', 47) +A7XX_PERF_SP_EXPORT_VPC_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EXPORT_VPC_TRANS', 48) +A7XX_PERF_SP_EXPORT_RB_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EXPORT_RB_TRANS', 49) +A7XX_PERF_SP_PIXELS_KILLED = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PIXELS_KILLED', 50) +A7XX_PERF_SP_ICL1_REQUESTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ICL1_REQUESTS', 51) +A7XX_PERF_SP_ICL1_MISSES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ICL1_MISSES', 52) +A7XX_PERF_SP_HS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HS_INSTRUCTIONS', 53) +A7XX_PERF_SP_DS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_DS_INSTRUCTIONS', 54) +A7XX_PERF_SP_GS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GS_INSTRUCTIONS', 55) +A7XX_PERF_SP_CS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CS_INSTRUCTIONS', 56) +A7XX_PERF_SP_GPR_READ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ', 57) +A7XX_PERF_SP_GPR_WRITE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_WRITE', 58) +A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', 59) +A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', 60) +A7XX_PERF_SP_LM_BANK_CONFLICTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_BANK_CONFLICTS', 61) +A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES', 62) +A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES', 63) +A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES', 64) +A7XX_PERF_SP_LM_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_WORKING_CYCLES', 65) +A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES', 66) +A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES', 67) +A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', 68) +A7XX_PERF_SP_STARVE_CYCLES_HLSQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STARVE_CYCLES_HLSQ', 69) +A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES', 70) +A7XX_PERF_SP_WORKING_EU = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU', 71) +A7XX_PERF_SP_ANY_EU_WORKING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING', 72) +A7XX_PERF_SP_WORKING_EU_FS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU_FS_STAGE', 73) +A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE', 74) +A7XX_PERF_SP_WORKING_EU_VS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU_VS_STAGE', 75) +A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE', 76) +A7XX_PERF_SP_WORKING_EU_CS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU_CS_STAGE', 77) +A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE', 78) +A7XX_PERF_SP_GPR_READ_PREFETCH = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ_PREFETCH', 79) +A7XX_PERF_SP_GPR_READ_CONFLICT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ_CONFLICT', 80) +A7XX_PERF_SP_GPR_WRITE_CONFLICT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_WRITE_CONFLICT', 81) +A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES', 82) +A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES', 83) +A7XX_PERF_SP_EXECUTABLE_WAVES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EXECUTABLE_WAVES', 84) +A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES', 85) +A7XX_PERF_SP_RESERVED_86 = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RESERVED_86', 86) +A7XX_PERF_SP_BYPASS_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BYPASS_BUSY_CYCLES', 87) +A7XX_PERF_SP_ANY_EU_WORKING_LPAC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_LPAC', 88) +A7XX_PERF_SP_WAVE_ALU_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_ALU_CYCLES', 89) +A7XX_PERF_SP_WAVE_EFU_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_EFU_CYCLES', 90) +A7XX_PERF_SP_WAVE_INT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_INT_CYCLES', 91) +A7XX_PERF_SP_WAVE_CSP_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CSP_CYCLES', 92) +A7XX_PERF_SP_EWAVE_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EWAVE_CONTEXTS', 93) +A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES', 94) +A7XX_PERF_SP_LPAC_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_BUSY_CYCLES', 95) +A7XX_PERF_SP_LPAC_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_INSTRUCTIONS', 96) +A7XX_PERF_SP_FS_STAGE_1X_WAVES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_1X_WAVES', 97) +A7XX_PERF_SP_FS_STAGE_2X_WAVES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_2X_WAVES', 98) +A7XX_PERF_SP_QUADS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_QUADS', 99) +A7XX_PERF_SP_CS_INVOCATIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CS_INVOCATIONS', 100) +A7XX_PERF_SP_PIXELS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PIXELS', 101) +A7XX_PERF_SP_LPAC_DRAWCALLS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_DRAWCALLS', 102) +A7XX_PERF_SP_PI_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PI_WORKING_CYCLES', 103) +A7XX_PERF_SP_WAVE_INPUT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_INPUT_CYCLES', 104) +A7XX_PERF_SP_WAVE_OUTPUT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_OUTPUT_CYCLES', 105) +A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES', 106) +A7XX_PERF_SP_WAVE_HWAVE_SYNC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_HWAVE_SYNC', 107) +A7XX_PERF_SP_OUTPUT_3D_PIXELS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_OUTPUT_3D_PIXELS', 108) +A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS', 109) +A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS', 110) +A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS', 111) +A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS', 112) +A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS', 113) +A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS', 114) +A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS', 115) +A7XX_PERF_SP_ALU_GPR_READ_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ALU_GPR_READ_CYCLES', 116) +A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES', 117) +A7XX_PERF_SP_LM_FULL_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_FULL_CYCLES', 118) +A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES', 119) +A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES', 120) +A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION', 121) +A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS', 122) +A7XX_PERF_SP_RBRT_KICKOFF_FIBERS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', 123) +A7XX_PERF_SP_RBRT_KICKOFF_DQUADS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RBRT_KICKOFF_DQUADS', 124) +A7XX_PERF_SP_RTU_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_BUSY_CYCLES', 125) +A7XX_PERF_SP_RTU_L0_HITS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_L0_HITS', 126) +A7XX_PERF_SP_RTU_L0_MISSES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_L0_MISSES', 127) +A7XX_PERF_SP_RTU_L0_HIT_ON_MISS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_L0_HIT_ON_MISS', 128) +A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE', 129) +A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE', 130) +A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE', 131) +A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE', 132) +A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA', 133) +A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT', 134) +A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT', 135) +A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE', 136) +A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0 = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0', 137) +A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO', 138) +A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES', 139) +A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES', 140) +A7XX_PERF_SP_STCHE_MISS_INC_VS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_VS', 141) +A7XX_PERF_SP_STCHE_MISS_INC_FS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_FS', 142) +A7XX_PERF_SP_STCHE_MISS_INC_BV = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_BV', 143) +A7XX_PERF_SP_STCHE_MISS_INC_LPAC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_LPAC', 144) +A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS', 145) +A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', 146) +A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS', 147) +A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS', 148) +A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS', 149) +A7XX_PERF_SP_SCH_STALL_CYCLES_RTU = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_SCH_STALL_CYCLES_RTU', 150) +A7XX_PERF_SP_EFU_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EFU_WORKING_CYCLES', 151) +A7XX_PERF_SP_BRANCH_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_TAKEN', 152) +A7XX_PERF_SP_BRANCH_NOT_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_NOT_TAKEN', 153) +A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT', 154) +A7XX_PERF_SP_BRANCH_INS_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_INS_COUNT', 155) +A7XX_PERF_SP_PREDICT_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_TAKEN', 156) +A7XX_PERF_SP_PREDICT_NOT_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_NOT_TAKEN', 157) +A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT', 158) +A7XX_PERF_SP_PREDICT_INS_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_INS_COUNT', 159) +A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', 160) +A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD', 161) +A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ', 162) +A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD', 163) +A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ', 164) +A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD', 165) +A7XX_PERF_SP_LB_READ_XFER_ALU = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_READ_XFER_ALU', 166) +A7XX_PERF_SP_LB_ALU_READ_CONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_ALU_READ_CONS', 167) +A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER', 168) +A7XX_PERF_SP_LB_WRITE_XFER_VPC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_WRITE_XFER_VPC', 169) +A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER', 170) +A7XX_PERF_SP_LB_LDST_RW_LM = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_RW_LM', 171) +A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED', 172) +A7XX_PERF_SP_LB_LDST_WRITE_CONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_WRITE_CONS', 173) +A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED', 174) +A7XX_PERF_SP_GPR_READ_BANK = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ_BANK', 175) +A7XX_PERF_SP_GPR_WRITE_BANK = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_WRITE_BANK', 176) +A7XX_PERF_SP_VS_WAVE_REQ_PENDING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_WAVE_REQ_PENDING', 177) +A7XX_PERF_SP_FS_WAVE_REQ_PENDING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_WAVE_REQ_PENDING', 178) +A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', 179) +A7XX_PERF_SP_WAVE_SPLIT_CNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_SPLIT_CNT', 180) +A7XX_PERF_SP_FS_OOO_WAVE_ACC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_OOO_WAVE_ACC', 181) + +enum_a7xx_rb_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_RB_NEVER_COUNT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_NEVER_COUNT', 0) +A7XX_PERF_RB_BUSY_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BUSY_CYCLES', 1) +A7XX_PERF_RB_STALL_CYCLES_HLSQ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_HLSQ', 2) +A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL', 3) +A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL', 4) +A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL', 5) +A7XX_PERF_RB_STARVE_CYCLES_SP = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_SP', 6) +A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE', 7) +A7XX_PERF_RB_STARVE_CYCLES_CCU = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_CCU', 8) +A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', 9) +A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE', 10) +A7XX_PERF_RB_Z_WORKLOAD = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_WORKLOAD', 11) +A7XX_PERF_RB_HLSQ_ACTIVE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_HLSQ_ACTIVE', 12) +A7XX_PERF_RB_Z_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_READ', 13) +A7XX_PERF_RB_Z_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_WRITE', 14) +A7XX_PERF_RB_C_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_C_READ', 15) +A7XX_PERF_RB_C_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_C_WRITE', 16) +A7XX_PERF_RB_TOTAL_PASS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_TOTAL_PASS', 17) +A7XX_PERF_RB_Z_PASS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_PASS', 18) +A7XX_PERF_RB_Z_FAIL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_FAIL', 19) +A7XX_PERF_RB_S_FAIL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_S_FAIL', 20) +A7XX_PERF_RB_BLENDED_FXP_COMPONENTS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDED_FXP_COMPONENTS', 21) +A7XX_PERF_RB_BLENDED_FP16_COMPONENTS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDED_FP16_COMPONENTS', 22) +A7XX_PERF_RB_PS_INVOCATIONS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_PS_INVOCATIONS', 23) +A7XX_PERF_RB_2D_ALIVE_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_2D_ALIVE_CYCLES', 24) +A7XX_PERF_RB_2D_STARVE_CYCLES_SP = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_2D_STARVE_CYCLES_SP', 25) +A7XX_PERF_RB_2D_VALID_PIXELS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_2D_VALID_PIXELS', 26) +A7XX_PERF_RB_3D_PIXELS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_3D_PIXELS', 27) +A7XX_PERF_RB_BLENDER_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDER_WORKING_CYCLES', 28) +A7XX_PERF_RB_ZPROC_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_ZPROC_WORKING_CYCLES', 29) +A7XX_PERF_RB_CPROC_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_CPROC_WORKING_CYCLES', 30) +A7XX_PERF_RB_SAMPLER_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_SAMPLER_WORKING_CYCLES', 31) +A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ', 32) +A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', 33) +A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', 34) +A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', 35) +A7XX_PERF_RB_STALL_CYCLES_VPC_BE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_VPC_BE', 36) +A7XX_PERF_RB_BLENDED_FP32_COMPONENTS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDED_FP32_COMPONENTS', 37) +A7XX_PERF_RB_COLOR_PIX_TILES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_COLOR_PIX_TILES', 38) +A7XX_PERF_RB_STALL_CYCLES_CCU = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU', 39) +A7XX_PERF_RB_EARLY_Z_ARB3_GRANT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_EARLY_Z_ARB3_GRANT', 40) +A7XX_PERF_RB_LATE_Z_ARB3_GRANT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_LATE_Z_ARB3_GRANT', 41) +A7XX_PERF_RB_EARLY_Z_SKIP_GRANT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', 42) +A7XX_PERF_RB_VRS_1X1_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_1X1_QUADS', 43) +A7XX_PERF_RB_VRS_2X1_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_2X1_QUADS', 44) +A7XX_PERF_RB_VRS_1X2_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_1X2_QUADS', 45) +A7XX_PERF_RB_VRS_2X2_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_2X2_QUADS', 46) +A7XX_PERF_RB_VRS_2X4_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_2X4_QUADS', 47) +A7XX_PERF_RB_VRS_4X2_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_4X2_QUADS', 48) +A7XX_PERF_RB_VRS_4X4_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_4X4_QUADS', 49) + +enum_a7xx_vsc_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_VSC_NEVER_COUNT = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_NEVER_COUNT', 0) +A7XX_PERF_VSC_BUSY_CYCLES = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_BUSY_CYCLES', 1) +A7XX_PERF_VSC_WORKING_CYCLES = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_WORKING_CYCLES', 2) +A7XX_PERF_VSC_STALL_CYCLES_UCHE = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_STALL_CYCLES_UCHE', 3) +A7XX_PERF_VSC_EOT_NUM = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_EOT_NUM', 4) +A7XX_PERF_VSC_INPUT_TILES = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_INPUT_TILES', 5) +A7XX_PERF_VSC_TILE_COMP_TRAN = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_TILE_COMP_TRAN', 6) +A7XX_PERF_VSC_TILE_BYPASS_TRAN = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_TILE_BYPASS_TRAN', 7) + +enum_a7xx_ccu_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_CCU_NEVER_COUNT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_NEVER_COUNT', 0) +A7XX_PERF_CCU_BUSY_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_BUSY_CYCLES', 1) +A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', 2) +A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', 3) +A7XX_PERF_CCU_DEPTH_BLOCKS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_BLOCKS', 4) +A7XX_PERF_CCU_COLOR_BLOCKS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_BLOCKS', 5) +A7XX_PERF_CCU_DEPTH_BLOCK_HIT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_BLOCK_HIT', 6) +A7XX_PERF_CCU_COLOR_BLOCK_HIT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_BLOCK_HIT', 7) +A7XX_PERF_CCU_PARTIAL_BLOCK_READ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_PARTIAL_BLOCK_READ', 8) +A7XX_PERF_CCU_GMEM_READ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_READ', 9) +A7XX_PERF_CCU_GMEM_WRITE = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_WRITE', 10) +A7XX_PERF_CCU_2D_RD_REQ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_2D_RD_REQ', 11) +A7XX_PERF_CCU_2D_WR_REQ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_2D_WR_REQ', 12) +A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT', 13) +A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT', 14) +A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED', 15) +A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED', 16) +A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT', 17) +A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT', 18) +A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER', 19) +A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER', 20) +A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', 21) +A7XX_PERF_CCU_GMEM_COLOR_READ_4AA = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_COLOR_READ_4AA', 22) +A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL', 23) +A7XX_PERF_CCU_COLOR_EVB_STALL = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_EVB_STALL', 24) +A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C', 25) +A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z', 26) +A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C', 27) +A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z', 28) +A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES', 29) +A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE', 30) +A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE', 31) +A7XX_PERF_CCU_RESERVED_32 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_32', 32) +A7XX_PERF_CCU_RESERVED_33 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_33', 33) +A7XX_PERF_CCU_RESERVED_34 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_34', 34) +A7XX_PERF_CCU_RESERVED_35 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_35', 35) +A7XX_PERF_CCU_RESERVED_36 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_36', 36) +A7XX_PERF_CCU_RESERVED_37 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_37', 37) +A7XX_PERF_CCU_RESERVED_38 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_38', 38) +A7XX_PERF_CCU_RESERVED_39 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_39', 39) +A7XX_PERF_CCU_RESERVED_40 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_40', 40) +A7XX_PERF_CCU_RESERVED_41 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_41', 41) +A7XX_PERF_CCU_RESERVED_42 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_42', 42) +A7XX_PERF_CCU_RESERVED_43 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_43', 43) +A7XX_PERF_CCU_RESERVED_44 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_44', 44) +A7XX_PERF_CCU_RESERVED_45 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_45', 45) +A7XX_PERF_CCU_RESERVED_46 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_46', 46) +A7XX_PERF_CCU_RESERVED_47 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_47', 47) +A7XX_PERF_CCU_RESERVED_48 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_48', 48) +A7XX_PERF_CCU_RESERVED_49 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_49', 49) +A7XX_PERF_CCU_RESERVED_50 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_50', 50) +A7XX_PERF_CCU_RESERVED_51 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_51', 51) +A7XX_PERF_CCU_RESERVED_52 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_52', 52) +A7XX_PERF_CCU_RESERVED_53 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_53', 53) +A7XX_PERF_CCU_RESERVED_54 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_54', 54) +A7XX_PERF_CCU_RESERVED_55 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_55', 55) +A7XX_PERF_CCU_RESERVED_56 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_56', 56) +A7XX_PERF_CCU_RESERVED_57 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_57', 57) +A7XX_PERF_CCU_RESERVED_58 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_58', 58) +A7XX_PERF_CCU_RESERVED_59 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_59', 59) +A7XX_PERF_CCU_RESERVED_60 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_60', 60) +A7XX_PERF_CCU_RESERVED_61 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_61', 61) +A7XX_PERF_CCU_RESERVED_62 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_62', 62) +A7XX_PERF_CCU_RESERVED_63 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_63', 63) +A7XX_PERF_UFC_L0_TP_HINT_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_REQUESTS', 64) +A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS', 65) +A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY', 66) +A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY', 67) +A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR', 68) +A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0', 69) +A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1', 70) +A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP', 71) +A7XX_PERF_UFC_L0_SP_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_REQUESTS', 72) +A7XX_PERF_UFC_L0_SP_FILTER_HIT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_FILTER_HIT', 73) +A7XX_PERF_UFC_L0_SP_FILTER_MISS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_FILTER_MISS', 74) +A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES', 75) +A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES', 76) +A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES', 77) +A7XX_PERF_CCU_RESERVED_78 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_78', 78) +A7XX_PERF_CCU_RESERVED_79 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_79', 79) +A7XX_PERF_CCU_RESERVED_80 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_80', 80) +A7XX_PERF_CCU_RESERVED_81 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_81', 81) +A7XX_PERF_CCU_RESERVED_82 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_82', 82) +A7XX_PERF_CCU_RESERVED_83 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_83', 83) +A7XX_PERF_CCU_RESERVED_84 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_84', 84) +A7XX_PERF_CCU_RESERVED_85 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_85', 85) +A7XX_PERF_CCU_RESERVED_86 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_86', 86) +A7XX_PERF_CCU_RESERVED_87 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_87', 87) +A7XX_PERF_CCU_RESERVED_88 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_88', 88) +A7XX_PERF_CCU_RESERVED_89 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_89', 89) +A7XX_PERF_CCU_RESERVED_90 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_90', 90) +A7XX_PERF_CCU_RESERVED_91 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_91', 91) +A7XX_PERF_CCU_RESERVED_92 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_92', 92) +A7XX_PERF_CCU_RESERVED_93 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_93', 93) +A7XX_PERF_CCU_RESERVED_94 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_94', 94) +A7XX_PERF_CCU_RESERVED_95 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_95', 95) +A7XX_PERF_CCU_RESERVED_96 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_96', 96) +A7XX_PERF_CCU_RESERVED_97 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_97', 97) +A7XX_PERF_CCU_RESERVED_98 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_98', 98) +A7XX_PERF_CCU_RESERVED_99 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_99', 99) +A7XX_PERF_CCU_RESERVED_100 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_100', 100) +A7XX_PERF_CCU_RESERVED_101 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_101', 101) +A7XX_PERF_CCU_RESERVED_102 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_102', 102) +A7XX_PERF_CCU_RESERVED_103 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_103', 103) +A7XX_PERF_CCU_RESERVED_104 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_104', 104) +A7XX_PERF_CCU_RESERVED_105 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_105', 105) +A7XX_PERF_CCU_RESERVED_106 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_106', 106) +A7XX_PERF_CCU_RESERVED_107 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_107', 107) +A7XX_PERF_CCU_RESERVED_108 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_108', 108) +A7XX_PERF_CCU_RESERVED_109 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_109', 109) +A7XX_PERF_CCU_RESERVED_110 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_110', 110) +A7XX_PERF_CCU_RESERVED_111 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_111', 111) +A7XX_PERF_CCU_RESERVED_112 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_112', 112) +A7XX_PERF_CCU_RESERVED_113 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_113', 113) +A7XX_PERF_CCU_RESERVED_114 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_114', 114) +A7XX_PERF_CCU_RESERVED_115 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_115', 115) +A7XX_PERF_CCU_RESERVED_116 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_116', 116) +A7XX_PERF_CCU_RESERVED_117 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_117', 117) +A7XX_PERF_CCU_RESERVED_118 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_118', 118) +A7XX_PERF_CCU_RESERVED_119 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_119', 119) +A7XX_PERF_CCU_RESERVED_120 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_120', 120) +A7XX_PERF_CCU_RESERVED_121 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_121', 121) +A7XX_PERF_CCU_RESERVED_122 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_122', 122) +A7XX_PERF_CCU_RESERVED_123 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_123', 123) +A7XX_PERF_CCU_RESERVED_124 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_124', 124) +A7XX_PERF_CCU_RESERVED_125 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_125', 125) +A7XX_PERF_CCU_RESERVED_126 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_126', 126) +A7XX_PERF_CCU_RESERVED_127 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_127', 127) +A7XX_PERF_CRE_RESOLVE_EVENTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_RESOLVE_EVENTS', 128) +A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS', 129) +A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS', 130) +A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT', 131) +A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT', 132) +A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS', 133) +A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS', 134) +A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS', 135) +A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS', 136) + +enum_a7xx_lrz_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_LRZ_NEVER_COUNT = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_NEVER_COUNT', 0) +A7XX_PERF_LRZ_BUSY_CYCLES = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_BUSY_CYCLES', 1) +A7XX_PERF_LRZ_STARVE_CYCLES_RAS = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STARVE_CYCLES_RAS', 2) +A7XX_PERF_LRZ_STALL_CYCLES_RB = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_RB', 3) +A7XX_PERF_LRZ_STALL_CYCLES_VSC = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_VSC', 4) +A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE', 5) +A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR', 6) +A7XX_PERF_LRZ_STALL_CYCLES_UCHE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_UCHE', 7) +A7XX_PERF_LRZ_LRZ_READ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_LRZ_READ', 8) +A7XX_PERF_LRZ_LRZ_WRITE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_LRZ_WRITE', 9) +A7XX_PERF_LRZ_READ_LATENCY = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_READ_LATENCY', 10) +A7XX_PERF_LRZ_MERGE_CACHE_UPDATING = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_MERGE_CACHE_UPDATING', 11) +A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN', 12) +A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ', 13) +A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 14) +A7XX_PERF_LRZ_FULL_8X8_TILES = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FULL_8X8_TILES', 15) +A7XX_PERF_LRZ_PARTIAL_8X8_TILES = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_PARTIAL_8X8_TILES', 16) +A7XX_PERF_LRZ_TILE_KILLED = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TILE_KILLED', 17) +A7XX_PERF_LRZ_TOTAL_PIXEL = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TOTAL_PIXEL', 18) +A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', 19) +A7XX_PERF_LRZ_FEEDBACK_ACCEPT = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FEEDBACK_ACCEPT', 20) +A7XX_PERF_LRZ_FEEDBACK_DISCARD = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FEEDBACK_DISCARD', 21) +A7XX_PERF_LRZ_FEEDBACK_STALL = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FEEDBACK_STALL', 22) +A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 23) +A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE', 24) +A7XX_PERF_LRZ_RAS_MASK_TRANS = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_RAS_MASK_TRANS', 25) +A7XX_PERF_LRZ_STALL_CYCLES_MVC = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_MVC', 26) +A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS', 27) +A7XX_PERF_LRZ_TILE_KILLED_BY_Z = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TILE_KILLED_BY_Z', 28) +A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH', 29) +A7XX_PERF_LRZ_NUM_FLOCK = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_NUM_FLOCK', 30) + +enum_a7xx_cmp_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_CMPDECMP_NEVER_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_NEVER_COUNT', 0) +A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB', 1) +A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES', 2) +A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', 3) +A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU', 4) +A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', 5) +A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST', 6) +A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST', 7) +A7XX_PERF_CMPDECMP_VBIF_READ_DATA = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA', 8) +A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA', 9) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', 10) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', 11) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', 12) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', 13) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', 14) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', 15) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', 16) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', 17) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', 18) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', 19) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', 20) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', 21) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', 22) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', 23) +A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', 24) +A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', 25) +A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', 26) +A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', 27) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', 28) +A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', 29) +A7XX_PERF_CMPDECMP_CDP_FILTER_HIT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_CDP_FILTER_HIT', 30) +A7XX_PERF_CMPDECMP_CDP_FILTER_MISS = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_CDP_FILTER_MISS', 31) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT', 32) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT', 33) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT', 34) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT', 35) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT', 36) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT', 37) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT', 38) +A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT', 39) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT', 40) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT', 41) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT', 42) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT', 43) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT', 44) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT', 45) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT', 46) +A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT', 47) + +enum_a7xx_gbif_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_GBIF_NEVER_COUNT = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_NEVER_COUNT', 0) +A7XX_PERF_GBIF_RESERVED_1 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_1', 1) +A7XX_PERF_GBIF_RESERVED_2 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_2', 2) +A7XX_PERF_GBIF_RESERVED_3 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_3', 3) +A7XX_PERF_GBIF_RESERVED_4 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_4', 4) +A7XX_PERF_GBIF_RESERVED_5 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_5', 5) +A7XX_PERF_GBIF_RESERVED_6 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_6', 6) +A7XX_PERF_GBIF_RESERVED_7 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_7', 7) +A7XX_PERF_GBIF_RESERVED_8 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_8', 8) +A7XX_PERF_GBIF_RESERVED_9 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_9', 9) +A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL', 10) +A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL', 11) +A7XX_PERF_GBIF_RESERVED_12 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_12', 12) +A7XX_PERF_GBIF_RESERVED_13 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_13', 13) +A7XX_PERF_GBIF_RESERVED_14 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_14', 14) +A7XX_PERF_GBIF_RESERVED_15 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_15', 15) +A7XX_PERF_GBIF_RESERVED_16 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_16', 16) +A7XX_PERF_GBIF_RESERVED_17 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_17', 17) +A7XX_PERF_GBIF_RESERVED_18 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_18', 18) +A7XX_PERF_GBIF_RESERVED_19 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_19', 19) +A7XX_PERF_GBIF_RESERVED_20 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_20', 20) +A7XX_PERF_GBIF_RESERVED_21 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_21', 21) +A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL', 22) +A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL', 23) +A7XX_PERF_GBIF_RESERVED_24 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_24', 24) +A7XX_PERF_GBIF_RESERVED_25 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_25', 25) +A7XX_PERF_GBIF_RESERVED_26 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_26', 26) +A7XX_PERF_GBIF_RESERVED_27 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_27', 27) +A7XX_PERF_GBIF_RESERVED_28 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_28', 28) +A7XX_PERF_GBIF_RESERVED_29 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_29', 29) +A7XX_PERF_GBIF_RESERVED_30 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_30', 30) +A7XX_PERF_GBIF_RESERVED_31 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_31', 31) +A7XX_PERF_GBIF_RESERVED_32 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_32', 32) +A7XX_PERF_GBIF_RESERVED_33 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_33', 33) +A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL', 34) +A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL', 35) +A7XX_PERF_GBIF_RESERVED_36 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_36', 36) +A7XX_PERF_GBIF_RESERVED_37 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_37', 37) +A7XX_PERF_GBIF_RESERVED_38 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_38', 38) +A7XX_PERF_GBIF_RESERVED_39 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_39', 39) +A7XX_PERF_GBIF_RESERVED_40 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_40', 40) +A7XX_PERF_GBIF_RESERVED_41 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_41', 41) +A7XX_PERF_GBIF_RESERVED_42 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_42', 42) +A7XX_PERF_GBIF_RESERVED_43 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_43', 43) +A7XX_PERF_GBIF_RESERVED_44 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_44', 44) +A7XX_PERF_GBIF_RESERVED_45 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_45', 45) +A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL', 46) +A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL', 47) +A7XX_PERF_GBIF_RESERVED_48 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_48', 48) +A7XX_PERF_GBIF_RESERVED_49 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_49', 49) +A7XX_PERF_GBIF_RESERVED_50 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_50', 50) +A7XX_PERF_GBIF_RESERVED_51 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_51', 51) +A7XX_PERF_GBIF_RESERVED_52 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_52', 52) +A7XX_PERF_GBIF_RESERVED_53 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_53', 53) +A7XX_PERF_GBIF_RESERVED_54 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_54', 54) +A7XX_PERF_GBIF_RESERVED_55 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_55', 55) +A7XX_PERF_GBIF_RESERVED_56 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_56', 56) +A7XX_PERF_GBIF_RESERVED_57 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_57', 57) +A7XX_PERF_GBIF_RESERVED_58 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_58', 58) +A7XX_PERF_GBIF_RESERVED_59 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_59', 59) +A7XX_PERF_GBIF_RESERVED_60 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_60', 60) +A7XX_PERF_GBIF_RESERVED_61 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_61', 61) +A7XX_PERF_GBIF_RESERVED_62 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_62', 62) +A7XX_PERF_GBIF_RESERVED_63 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_63', 63) +A7XX_PERF_GBIF_RESERVED_64 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_64', 64) +A7XX_PERF_GBIF_RESERVED_65 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_65', 65) +A7XX_PERF_GBIF_RESERVED_66 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_66', 66) +A7XX_PERF_GBIF_RESERVED_67 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_67', 67) +A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL', 68) +A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL', 69) +A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL', 70) +A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL', 71) +A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF', 72) +A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF', 73) +A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF', 74) +A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF', 75) +A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF', 76) +A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF', 77) +A7XX_PERF_GBIF_RESERVED_78 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_78', 78) +A7XX_PERF_GBIF_RESERVED_79 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_79', 79) +A7XX_PERF_GBIF_RESERVED_80 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_80', 80) +A7XX_PERF_GBIF_RESERVED_81 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_81', 81) +A7XX_PERF_GBIF_RESERVED_82 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_82', 82) +A7XX_PERF_GBIF_RESERVED_83 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_83', 83) +A7XX_PERF_GBIF_RESERVED_84 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_84', 84) +A7XX_PERF_GBIF_RESERVED_85 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_85', 85) +A7XX_PERF_GBIF_RESERVED_86 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_86', 86) +A7XX_PERF_GBIF_RESERVED_87 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_87', 87) +A7XX_PERF_GBIF_RESERVED_88 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_88', 88) +A7XX_PERF_GBIF_RESERVED_89 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_89', 89) +A7XX_PERF_GBIF_RESERVED_90 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_90', 90) +A7XX_PERF_GBIF_RESERVED_91 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_91', 91) +A7XX_PERF_GBIF_RESERVED_92 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_92', 92) +A7XX_PERF_GBIF_RESERVED_93 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_93', 93) +A7XX_PERF_GBIF_RESERVED_94 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_94', 94) +A7XX_PERF_GBIF_RESERVED_95 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_95', 95) +A7XX_PERF_GBIF_RESERVED_96 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_96', 96) +A7XX_PERF_GBIF_RESERVED_97 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_97', 97) +A7XX_PERF_GBIF_RESERVED_98 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_98', 98) +A7XX_PERF_GBIF_RESERVED_99 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_99', 99) +A7XX_PERF_GBIF_RESERVED_100 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_100', 100) +A7XX_PERF_GBIF_RESERVED_101 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_101', 101) +A7XX_PERF_GBIF_RESERVED_102 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_102', 102) +A7XX_PERF_GBIF_RESERVED_103 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_103', 103) +A7XX_PERF_GBIF_RESERVED_104 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_104', 104) +A7XX_PERF_GBIF_RESERVED_105 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_105', 105) +A7XX_PERF_GBIF_RESERVED_106 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_106', 106) +A7XX_PERF_GBIF_RESERVED_107 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_107', 107) +A7XX_PERF_GBIF_RESERVED_108 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_108', 108) +A7XX_PERF_GBIF_RESERVED_109 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_109', 109) +A7XX_PERF_GBIF_RESERVED_110 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_110', 110) +A7XX_PERF_GBIF_RESERVED_111 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_111', 111) +A7XX_PERF_GBIF_RESERVED_112 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_112', 112) +A7XX_PERF_GBIF_RESERVED_113 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_113', 113) +A7XX_PERF_GBIF_RESERVED_114 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_114', 114) +A7XX_PERF_GBIF_RESERVED_115 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_115', 115) +A7XX_PERF_GBIF_RESERVED_116 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_116', 116) +A7XX_PERF_GBIF_RESERVED_117 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_117', 117) +A7XX_PERF_GBIF_RESERVED_118 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_118', 118) +A7XX_PERF_GBIF_RESERVED_119 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_119', 119) +A7XX_PERF_GBIF_RESERVED_120 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_120', 120) +A7XX_PERF_GBIF_RESERVED_121 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_121', 121) +A7XX_PERF_GBIF_RESERVED_122 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_122', 122) +A7XX_PERF_GBIF_RESERVED_123 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_123', 123) +A7XX_PERF_GBIF_RESERVED_124 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_124', 124) +A7XX_PERF_GBIF_RESERVED_125 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_125', 125) +A7XX_PERF_GBIF_RESERVED_126 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_126', 126) +A7XX_PERF_GBIF_RESERVED_127 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_127', 127) +A7XX_PERF_GBIF_RESERVED_128 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_128', 128) +A7XX_PERF_GBIF_RESERVED_129 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_129', 129) +A7XX_PERF_GBIF_RESERVED_130 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_130', 130) +A7XX_PERF_GBIF_RESERVED_131 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_131', 131) +A7XX_PERF_GBIF_RESERVED_132 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_132', 132) +A7XX_PERF_GBIF_RESERVED_133 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_133', 133) +A7XX_PERF_GBIF_RESERVED_134 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_134', 134) +A7XX_PERF_GBIF_RESERVED_135 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_135', 135) +A7XX_PERF_GBIF_RESERVED_136 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_136', 136) +A7XX_PERF_GBIF_RESERVED_137 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_137', 137) +A7XX_PERF_GBIF_RESERVED_138 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_138', 138) +A7XX_PERF_GBIF_RESERVED_139 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_139', 139) +A7XX_PERF_GBIF_RESERVED_140 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_140', 140) +A7XX_PERF_GBIF_RESERVED_141 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_141', 141) +A7XX_PERF_GBIF_RESERVED_142 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_142', 142) +A7XX_PERF_GBIF_RESERVED_143 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_143', 143) +A7XX_PERF_GBIF_RESERVED_144 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_144', 144) +A7XX_PERF_GBIF_RESERVED_145 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_145', 145) +A7XX_PERF_GBIF_RESERVED_146 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_146', 146) +A7XX_PERF_GBIF_RESERVED_147 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_147', 147) +A7XX_PERF_GBIF_RESERVED_148 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_148', 148) +A7XX_PERF_GBIF_RESERVED_149 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_149', 149) +A7XX_PERF_GBIF_RESERVED_150 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_150', 150) +A7XX_PERF_GBIF_RESERVED_151 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_151', 151) +A7XX_PERF_GBIF_RESERVED_152 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_152', 152) +A7XX_PERF_GBIF_RESERVED_153 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_153', 153) +A7XX_PERF_GBIF_RESERVED_154 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_154', 154) +A7XX_PERF_GBIF_RESERVED_155 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_155', 155) +A7XX_PERF_GBIF_RESERVED_156 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_156', 156) +A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS', 157) +A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS', 158) +A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS', 159) +A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL', 160) +A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL', 161) + +enum_a7xx_ufc_perfcounter_select = CEnum(ctypes.c_uint32) +A7XX_PERF_UFC_NEVER_COUNT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_NEVER_COUNT', 0) +A7XX_PERF_UFC_BUSY_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_BUSY_CYCLES', 1) +A7XX_PERF_UFC_READ_DATA_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_READ_DATA_VBIF', 2) +A7XX_PERF_UFC_WRITE_DATA_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_WRITE_DATA_VBIF', 3) +A7XX_PERF_UFC_READ_REQUEST_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_READ_REQUEST_VBIF', 4) +A7XX_PERF_UFC_WRITE_REQUEST_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_WRITE_REQUEST_VBIF', 5) +A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH', 6) +A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH', 7) +A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH', 8) +A7XX_PERF_UFC_MAIN_HIT_UBWC_READ = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_UBWC_READ', 9) +A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE', 10) +A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH', 11) +A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH', 12) +A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH', 13) +A7XX_PERF_UFC_MAIN_MISS_UBWC_READ = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_UBWC_READ', 14) +A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE', 15) +A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY', 16) +A7XX_PERF_UFC_MAIN_UBWC_RD_RDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_UBWC_RD_RDY', 17) +A7XX_PERF_UFC_MAIN_TP_RD_NRDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_TP_RD_NRDY', 18) +A7XX_PERF_UFC_MAIN_TP_RD_RDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_TP_RD_RDY', 19) +A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD', 20) +A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA', 21) +A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA', 22) +A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG', 23) +A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN', 24) +A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT', 25) +A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES', 26) +A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES', 27) +A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES', 28) +A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES', 29) +A7XX_PERF_UFC_EVICTION_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_EVICTION_STALLED_CYCLES', 30) +A7XX_PERF_UFC_LOCK_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_LOCK_STALLED_CYCLES', 31) +A7XX_PERF_UFC_MISS_LATENCY_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MISS_LATENCY_CYCLES', 32) +A7XX_PERF_UFC_MISS_LATENCY_SAMPLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', 33) +A7XX_PERF_UFC_L1_CRE_REQUESTS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_REQUESTS', 34) +A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES', 35) +A7XX_PERF_UFC_L1_CRE_FILTER_HIT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_FILTER_HIT', 36) +A7XX_PERF_UFC_L1_CRE_FILTER_MISS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_FILTER_MISS', 37) +A7XX_PERF_UFC_L1_SP_REQUESTS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_REQUESTS', 38) +A7XX_PERF_UFC_L1_SP_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_STALLED_CYCLES', 39) +A7XX_PERF_UFC_L1_SP_FILTER_HIT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_FILTER_HIT', 40) +A7XX_PERF_UFC_L1_SP_FILTER_MISS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_FILTER_MISS', 41) +A7XX_PERF_UFC_L1_TP_HINT_REQUESTS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_REQUESTS', 42) +A7XX_PERF_UFC_L1_TP_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_STALLED_CYCLES', 43) +A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS', 44) +A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY', 45) +A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY', 46) + +enum_a6xx_sequenced_thread_dist = CEnum(ctypes.c_uint32) +DIST_SCREEN_COORD = enum_a6xx_sequenced_thread_dist.define('DIST_SCREEN_COORD', 0) +DIST_ALL_TO_RB0 = enum_a6xx_sequenced_thread_dist.define('DIST_ALL_TO_RB0', 1) + +enum_a6xx_single_prim_mode = CEnum(ctypes.c_uint32) +NO_FLUSH = enum_a6xx_single_prim_mode.define('NO_FLUSH', 0) +FLUSH_PER_OVERLAP_AND_OVERWRITE = enum_a6xx_single_prim_mode.define('FLUSH_PER_OVERLAP_AND_OVERWRITE', 1) +FLUSH_PER_OVERLAP = enum_a6xx_single_prim_mode.define('FLUSH_PER_OVERLAP', 3) + +enum_a6xx_raster_mode = CEnum(ctypes.c_uint32) +TYPE_TILED = enum_a6xx_raster_mode.define('TYPE_TILED', 0) +TYPE_WRITER = enum_a6xx_raster_mode.define('TYPE_WRITER', 1) + +enum_a6xx_raster_direction = CEnum(ctypes.c_uint32) +LR_TB = enum_a6xx_raster_direction.define('LR_TB', 0) +RL_TB = enum_a6xx_raster_direction.define('RL_TB', 1) +LR_BT = enum_a6xx_raster_direction.define('LR_BT', 2) +RB_BT = enum_a6xx_raster_direction.define('RB_BT', 3) + +enum_a6xx_render_mode = CEnum(ctypes.c_uint32) +RENDERING_PASS = enum_a6xx_render_mode.define('RENDERING_PASS', 0) +BINNING_PASS = enum_a6xx_render_mode.define('BINNING_PASS', 1) + +enum_a6xx_buffers_location = CEnum(ctypes.c_uint32) +BUFFERS_IN_GMEM = enum_a6xx_buffers_location.define('BUFFERS_IN_GMEM', 0) +BUFFERS_IN_SYSMEM = enum_a6xx_buffers_location.define('BUFFERS_IN_SYSMEM', 3) + +enum_a6xx_lrz_dir_status = CEnum(ctypes.c_uint32) +LRZ_DIR_LE = enum_a6xx_lrz_dir_status.define('LRZ_DIR_LE', 1) +LRZ_DIR_GE = enum_a6xx_lrz_dir_status.define('LRZ_DIR_GE', 2) +LRZ_DIR_INVALID = enum_a6xx_lrz_dir_status.define('LRZ_DIR_INVALID', 3) + +enum_a6xx_fragcoord_sample_mode = CEnum(ctypes.c_uint32) +FRAGCOORD_CENTER = enum_a6xx_fragcoord_sample_mode.define('FRAGCOORD_CENTER', 0) +FRAGCOORD_SAMPLE = enum_a6xx_fragcoord_sample_mode.define('FRAGCOORD_SAMPLE', 3) + +enum_a6xx_rotation = CEnum(ctypes.c_uint32) +ROTATE_0 = enum_a6xx_rotation.define('ROTATE_0', 0) +ROTATE_90 = enum_a6xx_rotation.define('ROTATE_90', 1) +ROTATE_180 = enum_a6xx_rotation.define('ROTATE_180', 2) +ROTATE_270 = enum_a6xx_rotation.define('ROTATE_270', 3) +ROTATE_HFLIP = enum_a6xx_rotation.define('ROTATE_HFLIP', 4) +ROTATE_VFLIP = enum_a6xx_rotation.define('ROTATE_VFLIP', 5) + +enum_a6xx_ccu_cache_size = CEnum(ctypes.c_uint32) +CCU_CACHE_SIZE_FULL = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_FULL', 0) +CCU_CACHE_SIZE_HALF = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_HALF', 1) +CCU_CACHE_SIZE_QUARTER = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_QUARTER', 2) +CCU_CACHE_SIZE_EIGHTH = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_EIGHTH', 3) + +enum_a6xx_varying_interp_mode = CEnum(ctypes.c_uint32) +INTERP_SMOOTH = enum_a6xx_varying_interp_mode.define('INTERP_SMOOTH', 0) +INTERP_FLAT = enum_a6xx_varying_interp_mode.define('INTERP_FLAT', 1) +INTERP_ZERO = enum_a6xx_varying_interp_mode.define('INTERP_ZERO', 2) +INTERP_ONE = enum_a6xx_varying_interp_mode.define('INTERP_ONE', 3) + +enum_a6xx_varying_ps_repl_mode = CEnum(ctypes.c_uint32) +PS_REPL_NONE = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_NONE', 0) +PS_REPL_S = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_S', 1) +PS_REPL_T = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_T', 2) +PS_REPL_ONE_MINUS_T = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_ONE_MINUS_T', 3) + +enum_a6xx_threadsize = CEnum(ctypes.c_uint32) +THREAD64 = enum_a6xx_threadsize.define('THREAD64', 0) +THREAD128 = enum_a6xx_threadsize.define('THREAD128', 1) + +enum_a6xx_bindless_descriptor_size = CEnum(ctypes.c_uint32) +BINDLESS_DESCRIPTOR_16B = enum_a6xx_bindless_descriptor_size.define('BINDLESS_DESCRIPTOR_16B', 1) +BINDLESS_DESCRIPTOR_64B = enum_a6xx_bindless_descriptor_size.define('BINDLESS_DESCRIPTOR_64B', 3) + +enum_a6xx_isam_mode = CEnum(ctypes.c_uint32) +ISAMMODE_CL = enum_a6xx_isam_mode.define('ISAMMODE_CL', 1) +ISAMMODE_GL = enum_a6xx_isam_mode.define('ISAMMODE_GL', 2) + +enum_a7xx_cs_yalign = CEnum(ctypes.c_uint32) +CS_YALIGN_1 = enum_a7xx_cs_yalign.define('CS_YALIGN_1', 8) +CS_YALIGN_2 = enum_a7xx_cs_yalign.define('CS_YALIGN_2', 4) +CS_YALIGN_4 = enum_a7xx_cs_yalign.define('CS_YALIGN_4', 2) +CS_YALIGN_8 = enum_a7xx_cs_yalign.define('CS_YALIGN_8', 1) + +enum_a6xx_tex_filter = CEnum(ctypes.c_uint32) +A6XX_TEX_NEAREST = enum_a6xx_tex_filter.define('A6XX_TEX_NEAREST', 0) +A6XX_TEX_LINEAR = enum_a6xx_tex_filter.define('A6XX_TEX_LINEAR', 1) +A6XX_TEX_ANISO = enum_a6xx_tex_filter.define('A6XX_TEX_ANISO', 2) +A6XX_TEX_CUBIC = enum_a6xx_tex_filter.define('A6XX_TEX_CUBIC', 3) + +enum_a6xx_tex_clamp = CEnum(ctypes.c_uint32) +A6XX_TEX_REPEAT = enum_a6xx_tex_clamp.define('A6XX_TEX_REPEAT', 0) +A6XX_TEX_CLAMP_TO_EDGE = enum_a6xx_tex_clamp.define('A6XX_TEX_CLAMP_TO_EDGE', 1) +A6XX_TEX_MIRROR_REPEAT = enum_a6xx_tex_clamp.define('A6XX_TEX_MIRROR_REPEAT', 2) +A6XX_TEX_CLAMP_TO_BORDER = enum_a6xx_tex_clamp.define('A6XX_TEX_CLAMP_TO_BORDER', 3) +A6XX_TEX_MIRROR_CLAMP = enum_a6xx_tex_clamp.define('A6XX_TEX_MIRROR_CLAMP', 4) + +enum_a6xx_tex_aniso = CEnum(ctypes.c_uint32) +A6XX_TEX_ANISO_1 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_1', 0) +A6XX_TEX_ANISO_2 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_2', 1) +A6XX_TEX_ANISO_4 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_4', 2) +A6XX_TEX_ANISO_8 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_8', 3) +A6XX_TEX_ANISO_16 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_16', 4) + +enum_a6xx_reduction_mode = CEnum(ctypes.c_uint32) +A6XX_REDUCTION_MODE_AVERAGE = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_AVERAGE', 0) +A6XX_REDUCTION_MODE_MIN = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_MIN', 1) +A6XX_REDUCTION_MODE_MAX = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_MAX', 2) + +enum_a6xx_tex_swiz = CEnum(ctypes.c_uint32) +A6XX_TEX_X = enum_a6xx_tex_swiz.define('A6XX_TEX_X', 0) +A6XX_TEX_Y = enum_a6xx_tex_swiz.define('A6XX_TEX_Y', 1) +A6XX_TEX_Z = enum_a6xx_tex_swiz.define('A6XX_TEX_Z', 2) +A6XX_TEX_W = enum_a6xx_tex_swiz.define('A6XX_TEX_W', 3) +A6XX_TEX_ZERO = enum_a6xx_tex_swiz.define('A6XX_TEX_ZERO', 4) +A6XX_TEX_ONE = enum_a6xx_tex_swiz.define('A6XX_TEX_ONE', 5) + +enum_a6xx_tex_type = CEnum(ctypes.c_uint32) +A6XX_TEX_1D = enum_a6xx_tex_type.define('A6XX_TEX_1D', 0) +A6XX_TEX_2D = enum_a6xx_tex_type.define('A6XX_TEX_2D', 1) +A6XX_TEX_CUBE = enum_a6xx_tex_type.define('A6XX_TEX_CUBE', 2) +A6XX_TEX_3D = enum_a6xx_tex_type.define('A6XX_TEX_3D', 3) +A6XX_TEX_BUFFER = enum_a6xx_tex_type.define('A6XX_TEX_BUFFER', 4) + +__struct__cast = lambda X: (struct_X) +REG_CP_LOAD_STATE_0 = 0x00000000 +CP_LOAD_STATE_0_DST_OFF__MASK = 0x0000ffff +CP_LOAD_STATE_0_DST_OFF__SHIFT = 0 +CP_LOAD_STATE_0_STATE_SRC__MASK = 0x00070000 +CP_LOAD_STATE_0_STATE_SRC__SHIFT = 16 +CP_LOAD_STATE_0_STATE_BLOCK__MASK = 0x00380000 +CP_LOAD_STATE_0_STATE_BLOCK__SHIFT = 19 +CP_LOAD_STATE_0_NUM_UNIT__MASK = 0xffc00000 +CP_LOAD_STATE_0_NUM_UNIT__SHIFT = 22 +REG_CP_LOAD_STATE_1 = 0x00000001 +CP_LOAD_STATE_1_STATE_TYPE__MASK = 0x00000003 +CP_LOAD_STATE_1_STATE_TYPE__SHIFT = 0 +CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK = 0xfffffffc +CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT = 2 +REG_CP_LOAD_STATE4_0 = 0x00000000 +CP_LOAD_STATE4_0_DST_OFF__MASK = 0x00003fff +CP_LOAD_STATE4_0_DST_OFF__SHIFT = 0 +CP_LOAD_STATE4_0_STATE_SRC__MASK = 0x00030000 +CP_LOAD_STATE4_0_STATE_SRC__SHIFT = 16 +CP_LOAD_STATE4_0_STATE_BLOCK__MASK = 0x003c0000 +CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT = 18 +CP_LOAD_STATE4_0_NUM_UNIT__MASK = 0xffc00000 +CP_LOAD_STATE4_0_NUM_UNIT__SHIFT = 22 +REG_CP_LOAD_STATE4_1 = 0x00000001 +CP_LOAD_STATE4_1_STATE_TYPE__MASK = 0x00000003 +CP_LOAD_STATE4_1_STATE_TYPE__SHIFT = 0 +CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK = 0xfffffffc +CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT = 2 +REG_CP_LOAD_STATE4_2 = 0x00000002 +CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff +CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT = 0 +REG_CP_LOAD_STATE6_0 = 0x00000000 +CP_LOAD_STATE6_0_DST_OFF__MASK = 0x00003fff +CP_LOAD_STATE6_0_DST_OFF__SHIFT = 0 +CP_LOAD_STATE6_0_STATE_TYPE__MASK = 0x0000c000 +CP_LOAD_STATE6_0_STATE_TYPE__SHIFT = 14 +CP_LOAD_STATE6_0_STATE_SRC__MASK = 0x00030000 +CP_LOAD_STATE6_0_STATE_SRC__SHIFT = 16 +CP_LOAD_STATE6_0_STATE_BLOCK__MASK = 0x003c0000 +CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT = 18 +CP_LOAD_STATE6_0_NUM_UNIT__MASK = 0xffc00000 +CP_LOAD_STATE6_0_NUM_UNIT__SHIFT = 22 +REG_CP_LOAD_STATE6_1 = 0x00000001 +CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK = 0xfffffffc +CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT = 2 +REG_CP_LOAD_STATE6_2 = 0x00000002 +CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff +CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT = 0 +REG_CP_LOAD_STATE6_EXT_SRC_ADDR = 0x00000001 +REG_CP_DRAW_INDX_0 = 0x00000000 +CP_DRAW_INDX_0_VIZ_QUERY__MASK = 0xffffffff +CP_DRAW_INDX_0_VIZ_QUERY__SHIFT = 0 +REG_CP_DRAW_INDX_1 = 0x00000001 +CP_DRAW_INDX_1_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_INDX_1_PRIM_TYPE__SHIFT = 0 +CP_DRAW_INDX_1_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_INDX_1_VIS_CULL__MASK = 0x00000600 +CP_DRAW_INDX_1_VIS_CULL__SHIFT = 9 +CP_DRAW_INDX_1_INDEX_SIZE__MASK = 0x00000800 +CP_DRAW_INDX_1_INDEX_SIZE__SHIFT = 11 +CP_DRAW_INDX_1_NOT_EOP = 0x00001000 +CP_DRAW_INDX_1_SMALL_INDEX = 0x00002000 +CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 +CP_DRAW_INDX_1_NUM_INSTANCES__MASK = 0xff000000 +CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT = 24 +REG_CP_DRAW_INDX_2 = 0x00000002 +CP_DRAW_INDX_2_NUM_INDICES__MASK = 0xffffffff +CP_DRAW_INDX_2_NUM_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_3 = 0x00000003 +CP_DRAW_INDX_3_INDX_BASE__MASK = 0xffffffff +CP_DRAW_INDX_3_INDX_BASE__SHIFT = 0 +REG_CP_DRAW_INDX_4 = 0x00000004 +CP_DRAW_INDX_4_INDX_SIZE__MASK = 0xffffffff +CP_DRAW_INDX_4_INDX_SIZE__SHIFT = 0 +REG_CP_DRAW_INDX_2_0 = 0x00000000 +CP_DRAW_INDX_2_0_VIZ_QUERY__MASK = 0xffffffff +CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT = 0 +REG_CP_DRAW_INDX_2_1 = 0x00000001 +CP_DRAW_INDX_2_1_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT = 0 +CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_INDX_2_1_VIS_CULL__MASK = 0x00000600 +CP_DRAW_INDX_2_1_VIS_CULL__SHIFT = 9 +CP_DRAW_INDX_2_1_INDEX_SIZE__MASK = 0x00000800 +CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT = 11 +CP_DRAW_INDX_2_1_NOT_EOP = 0x00001000 +CP_DRAW_INDX_2_1_SMALL_INDEX = 0x00002000 +CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 +CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK = 0xff000000 +CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT = 24 +REG_CP_DRAW_INDX_2_2 = 0x00000002 +CP_DRAW_INDX_2_2_NUM_INDICES__MASK = 0xffffffff +CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_0 = 0x00000000 +CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT = 0 +CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK = 0x00000300 +CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT = 8 +CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK = 0x00000c00 +CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT = 10 +CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK = 0x00003000 +CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT = 12 +CP_DRAW_INDX_OFFSET_0_GS_ENABLE = 0x00010000 +CP_DRAW_INDX_OFFSET_0_TESS_ENABLE = 0x00020000 +REG_CP_DRAW_INDX_OFFSET_1 = 0x00000001 +CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_2 = 0x00000002 +CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_3 = 0x00000003 +CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_OFFSET_4 = 0x00000004 +A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_OFFSET_5 = 0x00000005 +A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE = 0x00000004 +REG_A5XX_CP_DRAW_INDX_OFFSET_6 = 0x00000006 +A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_4 = 0x00000004 +CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_5 = 0x00000005 +CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT = 0 +REG_A4XX_CP_DRAW_INDIRECT_0 = 0x00000000 +A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f +A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT = 0 +A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 +A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 +A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK = 0x00000300 +A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT = 8 +A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 +A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT = 10 +A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 +A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT = 12 +A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE = 0x00010000 +A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE = 0x00020000 +REG_A4XX_CP_DRAW_INDIRECT_1 = 0x00000001 +A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK = 0xffffffff +A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT = 0 +REG_A5XX_CP_DRAW_INDIRECT_1 = 0x00000001 +A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDIRECT_2 = 0x00000002 +A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDIRECT_INDIRECT = 0x00000001 +REG_A4XX_CP_DRAW_INDX_INDIRECT_0 = 0x00000000 +A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f +A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT = 0 +A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 +A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 +A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK = 0x00000300 +A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT = 8 +A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 +A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT = 10 +A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 +A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT = 12 +A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE = 0x00010000 +A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE = 0x00020000 +REG_A4XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 +A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK = 0xffffffff +A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT = 0 +REG_A4XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 +A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK = 0xffffffff +A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT = 0 +REG_A4XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 +A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK = 0xffffffff +A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 +A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 +A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE = 0x00000001 +REG_A5XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 +A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_4 = 0x00000004 +A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_5 = 0x00000005 +A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT = 0x00000004 +REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 = 0x00000000 +A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK = 0x0000003f +A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT = 0 +A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK = 0x000000c0 +A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT = 6 +A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK = 0x00000300 +A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT = 8 +A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK = 0x00000c00 +A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT = 10 +A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK = 0x00003000 +A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT = 12 +A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE = 0x00010000 +A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE = 0x00020000 +REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 = 0x00000001 +A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK = 0x0000000f +A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT = 0 +A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK = 0x003fff00 +A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT = 8 +REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT = 0x00000002 +REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 +REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000005 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000008 +REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 +REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000005 +REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000007 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000008 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x0000000a +REG_CP_DRAW_AUTO_0 = 0x00000000 +CP_DRAW_AUTO_0_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT = 0 +CP_DRAW_AUTO_0_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_AUTO_0_VIS_CULL__MASK = 0x00000300 +CP_DRAW_AUTO_0_VIS_CULL__SHIFT = 8 +CP_DRAW_AUTO_0_INDEX_SIZE__MASK = 0x00000c00 +CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT = 10 +CP_DRAW_AUTO_0_PATCH_TYPE__MASK = 0x00003000 +CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT = 12 +CP_DRAW_AUTO_0_GS_ENABLE = 0x00010000 +CP_DRAW_AUTO_0_TESS_ENABLE = 0x00020000 +REG_CP_DRAW_AUTO_1 = 0x00000001 +CP_DRAW_AUTO_1_NUM_INSTANCES__MASK = 0xffffffff +CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT = 0 +REG_CP_DRAW_AUTO_NUM_VERTICES_BASE = 0x00000002 +REG_CP_DRAW_AUTO_4 = 0x00000004 +CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK = 0xffffffff +CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT = 0 +REG_CP_DRAW_AUTO_5 = 0x00000005 +CP_DRAW_AUTO_5_STRIDE__MASK = 0xffffffff +CP_DRAW_AUTO_5_STRIDE__SHIFT = 0 +REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 = 0x00000000 +CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE = 0x00000001 +REG_CP_DRAW_PRED_ENABLE_LOCAL_0 = 0x00000000 +CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE = 0x00000001 +REG_CP_DRAW_PRED_SET_0 = 0x00000000 +CP_DRAW_PRED_SET_0_SRC__MASK = 0x000000f0 +CP_DRAW_PRED_SET_0_SRC__SHIFT = 4 +CP_DRAW_PRED_SET_0_TEST__MASK = 0x00000100 +CP_DRAW_PRED_SET_0_TEST__SHIFT = 8 +REG_CP_DRAW_PRED_SET_MEM_ADDR = 0x00000001 +REG_CP_SET_DRAW_STATE_ = lambda i0: (0x00000000 + 0x3*i0 ) +CP_SET_DRAW_STATE__0_COUNT__MASK = 0x0000ffff +CP_SET_DRAW_STATE__0_COUNT__SHIFT = 0 +CP_SET_DRAW_STATE__0_DIRTY = 0x00010000 +CP_SET_DRAW_STATE__0_DISABLE = 0x00020000 +CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS = 0x00040000 +CP_SET_DRAW_STATE__0_LOAD_IMMED = 0x00080000 +CP_SET_DRAW_STATE__0_BINNING = 0x00100000 +CP_SET_DRAW_STATE__0_GMEM = 0x00200000 +CP_SET_DRAW_STATE__0_SYSMEM = 0x00400000 +CP_SET_DRAW_STATE__0_GROUP_ID__MASK = 0x1f000000 +CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT = 24 +CP_SET_DRAW_STATE__1_ADDR_LO__MASK = 0xffffffff +CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT = 0 +CP_SET_DRAW_STATE__2_ADDR_HI__MASK = 0xffffffff +CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT = 0 +REG_CP_SET_BIN_0 = 0x00000000 +REG_CP_SET_BIN_1 = 0x00000001 +CP_SET_BIN_1_X1__MASK = 0x0000ffff +CP_SET_BIN_1_X1__SHIFT = 0 +CP_SET_BIN_1_Y1__MASK = 0xffff0000 +CP_SET_BIN_1_Y1__SHIFT = 16 +REG_CP_SET_BIN_2 = 0x00000002 +CP_SET_BIN_2_X2__MASK = 0x0000ffff +CP_SET_BIN_2_X2__SHIFT = 0 +CP_SET_BIN_2_Y2__MASK = 0xffff0000 +CP_SET_BIN_2_Y2__SHIFT = 16 +REG_CP_SET_BIN_DATA_0 = 0x00000000 +CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK = 0xffffffff +CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT = 0 +REG_CP_SET_BIN_DATA_1 = 0x00000001 +CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK = 0xffffffff +CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT = 0 +REG_CP_SET_BIN_DATA5_0 = 0x00000000 +CP_SET_BIN_DATA5_0_VSC_SIZE__MASK = 0x003f0000 +CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT = 16 +CP_SET_BIN_DATA5_0_VSC_N__MASK = 0x07c00000 +CP_SET_BIN_DATA5_0_VSC_N__SHIFT = 22 +REG_CP_SET_BIN_DATA5_1 = 0x00000001 +CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK = 0xffffffff +CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT = 0 +REG_CP_SET_BIN_DATA5_2 = 0x00000002 +CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK = 0xffffffff +CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT = 0 +REG_CP_SET_BIN_DATA5_3 = 0x00000003 +CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff +CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT = 0 +REG_CP_SET_BIN_DATA5_4 = 0x00000004 +CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff +CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT = 0 +REG_CP_SET_BIN_DATA5_5 = 0x00000005 +CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK = 0xffffffff +CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT = 0 +REG_CP_SET_BIN_DATA5_6 = 0x00000006 +CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK = 0xffffffff +CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT = 0 +REG_CP_SET_BIN_DATA5_7 = 0x00000007 +REG_CP_SET_BIN_DATA5_9 = 0x00000009 +REG_CP_SET_BIN_DATA5_OFFSET_0 = 0x00000000 +CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK = 0x003f0000 +CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT = 16 +CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK = 0x07c00000 +CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT = 22 +REG_CP_SET_BIN_DATA5_OFFSET_1 = 0x00000001 +CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK = 0xffffffff +CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT = 0 +REG_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 +CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK = 0xffffffff +CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT = 0 +REG_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 +CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK = 0xffffffff +CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT = 0 +REG_CP_REG_RMW_0 = 0x00000000 +CP_REG_RMW_0_DST_REG__MASK = 0x0003ffff +CP_REG_RMW_0_DST_REG__SHIFT = 0 +CP_REG_RMW_0_ROTATE__MASK = 0x1f000000 +CP_REG_RMW_0_ROTATE__SHIFT = 24 +CP_REG_RMW_0_SRC1_ADD = 0x20000000 +CP_REG_RMW_0_SRC1_IS_REG = 0x40000000 +CP_REG_RMW_0_SRC0_IS_REG = 0x80000000 +REG_CP_REG_RMW_1 = 0x00000001 +CP_REG_RMW_1_SRC0__MASK = 0xffffffff +CP_REG_RMW_1_SRC0__SHIFT = 0 +REG_CP_REG_RMW_2 = 0x00000002 +CP_REG_RMW_2_SRC1__MASK = 0xffffffff +CP_REG_RMW_2_SRC1__SHIFT = 0 +REG_CP_REG_TO_MEM_0 = 0x00000000 +CP_REG_TO_MEM_0_REG__MASK = 0x0003ffff +CP_REG_TO_MEM_0_REG__SHIFT = 0 +CP_REG_TO_MEM_0_CNT__MASK = 0x3ffc0000 +CP_REG_TO_MEM_0_CNT__SHIFT = 18 +CP_REG_TO_MEM_0_64B = 0x40000000 +CP_REG_TO_MEM_0_ACCUMULATE = 0x80000000 +REG_CP_REG_TO_MEM_1 = 0x00000001 +CP_REG_TO_MEM_1_DEST__MASK = 0xffffffff +CP_REG_TO_MEM_1_DEST__SHIFT = 0 +REG_CP_REG_TO_MEM_2 = 0x00000002 +CP_REG_TO_MEM_2_DEST_HI__MASK = 0xffffffff +CP_REG_TO_MEM_2_DEST_HI__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_REG_0 = 0x00000000 +CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK = 0x0003ffff +CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT = 0 +CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK = 0x3ffc0000 +CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT = 18 +CP_REG_TO_MEM_OFFSET_REG_0_64B = 0x40000000 +CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE = 0x80000000 +REG_CP_REG_TO_MEM_OFFSET_REG_1 = 0x00000001 +CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_REG_2 = 0x00000002 +CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_REG_3 = 0x00000003 +CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK = 0x0003ffff +CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT = 0 +CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH = 0x00080000 +REG_CP_REG_TO_MEM_OFFSET_MEM_0 = 0x00000000 +CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK = 0x0003ffff +CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT = 0 +CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK = 0x3ffc0000 +CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT = 18 +CP_REG_TO_MEM_OFFSET_MEM_0_64B = 0x40000000 +CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE = 0x80000000 +REG_CP_REG_TO_MEM_OFFSET_MEM_1 = 0x00000001 +CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_MEM_2 = 0x00000002 +CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_MEM_3 = 0x00000003 +CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_MEM_4 = 0x00000004 +CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT = 0 +REG_CP_MEM_TO_REG_0 = 0x00000000 +CP_MEM_TO_REG_0_REG__MASK = 0x0003ffff +CP_MEM_TO_REG_0_REG__SHIFT = 0 +CP_MEM_TO_REG_0_CNT__MASK = 0x3ff80000 +CP_MEM_TO_REG_0_CNT__SHIFT = 19 +CP_MEM_TO_REG_0_SHIFT_BY_2 = 0x40000000 +CP_MEM_TO_REG_0_UNK31 = 0x80000000 +REG_CP_MEM_TO_REG_1 = 0x00000001 +CP_MEM_TO_REG_1_SRC__MASK = 0xffffffff +CP_MEM_TO_REG_1_SRC__SHIFT = 0 +REG_CP_MEM_TO_REG_2 = 0x00000002 +CP_MEM_TO_REG_2_SRC_HI__MASK = 0xffffffff +CP_MEM_TO_REG_2_SRC_HI__SHIFT = 0 +REG_CP_MEM_TO_MEM_0 = 0x00000000 +CP_MEM_TO_MEM_0_NEG_A = 0x00000001 +CP_MEM_TO_MEM_0_NEG_B = 0x00000002 +CP_MEM_TO_MEM_0_NEG_C = 0x00000004 +CP_MEM_TO_MEM_0_DOUBLE = 0x20000000 +CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES = 0x40000000 +CP_MEM_TO_MEM_0_UNK31 = 0x80000000 +REG_CP_MEMCPY_0 = 0x00000000 +CP_MEMCPY_0_DWORDS__MASK = 0xffffffff +CP_MEMCPY_0_DWORDS__SHIFT = 0 +REG_CP_MEMCPY_1 = 0x00000001 +CP_MEMCPY_1_SRC_LO__MASK = 0xffffffff +CP_MEMCPY_1_SRC_LO__SHIFT = 0 +REG_CP_MEMCPY_2 = 0x00000002 +CP_MEMCPY_2_SRC_HI__MASK = 0xffffffff +CP_MEMCPY_2_SRC_HI__SHIFT = 0 +REG_CP_MEMCPY_3 = 0x00000003 +CP_MEMCPY_3_DST_LO__MASK = 0xffffffff +CP_MEMCPY_3_DST_LO__SHIFT = 0 +REG_CP_MEMCPY_4 = 0x00000004 +CP_MEMCPY_4_DST_HI__MASK = 0xffffffff +CP_MEMCPY_4_DST_HI__SHIFT = 0 +REG_CP_REG_TO_SCRATCH_0 = 0x00000000 +CP_REG_TO_SCRATCH_0_REG__MASK = 0x0003ffff +CP_REG_TO_SCRATCH_0_REG__SHIFT = 0 +CP_REG_TO_SCRATCH_0_SCRATCH__MASK = 0x00700000 +CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT = 20 +CP_REG_TO_SCRATCH_0_CNT__MASK = 0x07000000 +CP_REG_TO_SCRATCH_0_CNT__SHIFT = 24 +REG_CP_SCRATCH_TO_REG_0 = 0x00000000 +CP_SCRATCH_TO_REG_0_REG__MASK = 0x0003ffff +CP_SCRATCH_TO_REG_0_REG__SHIFT = 0 +CP_SCRATCH_TO_REG_0_UNK18 = 0x00040000 +CP_SCRATCH_TO_REG_0_SCRATCH__MASK = 0x00700000 +CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT = 20 +CP_SCRATCH_TO_REG_0_CNT__MASK = 0x07000000 +CP_SCRATCH_TO_REG_0_CNT__SHIFT = 24 +REG_CP_SCRATCH_WRITE_0 = 0x00000000 +CP_SCRATCH_WRITE_0_SCRATCH__MASK = 0x00700000 +CP_SCRATCH_WRITE_0_SCRATCH__SHIFT = 20 +REG_CP_MEM_WRITE_0 = 0x00000000 +CP_MEM_WRITE_0_ADDR_LO__MASK = 0xffffffff +CP_MEM_WRITE_0_ADDR_LO__SHIFT = 0 +REG_CP_MEM_WRITE_1 = 0x00000001 +CP_MEM_WRITE_1_ADDR_HI__MASK = 0xffffffff +CP_MEM_WRITE_1_ADDR_HI__SHIFT = 0 +REG_CP_COND_WRITE_0 = 0x00000000 +CP_COND_WRITE_0_FUNCTION__MASK = 0x00000007 +CP_COND_WRITE_0_FUNCTION__SHIFT = 0 +CP_COND_WRITE_0_POLL_MEMORY = 0x00000010 +CP_COND_WRITE_0_WRITE_MEMORY = 0x00000100 +REG_CP_COND_WRITE_1 = 0x00000001 +CP_COND_WRITE_1_POLL_ADDR__MASK = 0xffffffff +CP_COND_WRITE_1_POLL_ADDR__SHIFT = 0 +REG_CP_COND_WRITE_2 = 0x00000002 +CP_COND_WRITE_2_REF__MASK = 0xffffffff +CP_COND_WRITE_2_REF__SHIFT = 0 +REG_CP_COND_WRITE_3 = 0x00000003 +CP_COND_WRITE_3_MASK__MASK = 0xffffffff +CP_COND_WRITE_3_MASK__SHIFT = 0 +REG_CP_COND_WRITE_4 = 0x00000004 +CP_COND_WRITE_4_WRITE_ADDR__MASK = 0xffffffff +CP_COND_WRITE_4_WRITE_ADDR__SHIFT = 0 +REG_CP_COND_WRITE_5 = 0x00000005 +CP_COND_WRITE_5_WRITE_DATA__MASK = 0xffffffff +CP_COND_WRITE_5_WRITE_DATA__SHIFT = 0 +REG_CP_COND_WRITE5_0 = 0x00000000 +CP_COND_WRITE5_0_FUNCTION__MASK = 0x00000007 +CP_COND_WRITE5_0_FUNCTION__SHIFT = 0 +CP_COND_WRITE5_0_SIGNED_COMPARE = 0x00000008 +CP_COND_WRITE5_0_POLL__MASK = 0x00000030 +CP_COND_WRITE5_0_POLL__SHIFT = 4 +CP_COND_WRITE5_0_WRITE_MEMORY = 0x00000100 +REG_CP_COND_WRITE5_1 = 0x00000001 +CP_COND_WRITE5_1_POLL_ADDR_LO__MASK = 0xffffffff +CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT = 0 +REG_CP_COND_WRITE5_2 = 0x00000002 +CP_COND_WRITE5_2_POLL_ADDR_HI__MASK = 0xffffffff +CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT = 0 +REG_CP_COND_WRITE5_3 = 0x00000003 +CP_COND_WRITE5_3_REF__MASK = 0xffffffff +CP_COND_WRITE5_3_REF__SHIFT = 0 +REG_CP_COND_WRITE5_4 = 0x00000004 +CP_COND_WRITE5_4_MASK__MASK = 0xffffffff +CP_COND_WRITE5_4_MASK__SHIFT = 0 +REG_CP_COND_WRITE5_5 = 0x00000005 +CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK = 0xffffffff +CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT = 0 +REG_CP_COND_WRITE5_6 = 0x00000006 +CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK = 0xffffffff +CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT = 0 +REG_CP_COND_WRITE5_7 = 0x00000007 +CP_COND_WRITE5_7_WRITE_DATA__MASK = 0xffffffff +CP_COND_WRITE5_7_WRITE_DATA__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_0 = 0x00000000 +CP_WAIT_MEM_GTE_0_RESERVED__MASK = 0xffffffff +CP_WAIT_MEM_GTE_0_RESERVED__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_1 = 0x00000001 +CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK = 0xffffffff +CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_2 = 0x00000002 +CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK = 0xffffffff +CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_3 = 0x00000003 +CP_WAIT_MEM_GTE_3_REF__MASK = 0xffffffff +CP_WAIT_MEM_GTE_3_REF__SHIFT = 0 +REG_CP_WAIT_REG_MEM_0 = 0x00000000 +CP_WAIT_REG_MEM_0_FUNCTION__MASK = 0x00000007 +CP_WAIT_REG_MEM_0_FUNCTION__SHIFT = 0 +CP_WAIT_REG_MEM_0_SIGNED_COMPARE = 0x00000008 +CP_WAIT_REG_MEM_0_POLL__MASK = 0x00000030 +CP_WAIT_REG_MEM_0_POLL__SHIFT = 4 +CP_WAIT_REG_MEM_0_WRITE_MEMORY = 0x00000100 +REG_CP_WAIT_REG_MEM_1 = 0x00000001 +CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK = 0xffffffff +CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT = 0 +REG_CP_WAIT_REG_MEM_2 = 0x00000002 +CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK = 0xffffffff +CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT = 0 +REG_CP_WAIT_REG_MEM_3 = 0x00000003 +CP_WAIT_REG_MEM_3_REF__MASK = 0xffffffff +CP_WAIT_REG_MEM_3_REF__SHIFT = 0 +REG_CP_WAIT_REG_MEM_4 = 0x00000004 +CP_WAIT_REG_MEM_4_MASK__MASK = 0xffffffff +CP_WAIT_REG_MEM_4_MASK__SHIFT = 0 +REG_CP_WAIT_REG_MEM_5 = 0x00000005 +CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK = 0xffffffff +CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT = 0 +REG_CP_WAIT_TWO_REGS_0 = 0x00000000 +CP_WAIT_TWO_REGS_0_REG0__MASK = 0x0003ffff +CP_WAIT_TWO_REGS_0_REG0__SHIFT = 0 +REG_CP_WAIT_TWO_REGS_1 = 0x00000001 +CP_WAIT_TWO_REGS_1_REG1__MASK = 0x0003ffff +CP_WAIT_TWO_REGS_1_REG1__SHIFT = 0 +REG_CP_WAIT_TWO_REGS_2 = 0x00000002 +CP_WAIT_TWO_REGS_2_REF__MASK = 0xffffffff +CP_WAIT_TWO_REGS_2_REF__SHIFT = 0 +REG_CP_DISPATCH_COMPUTE_0 = 0x00000000 +REG_CP_DISPATCH_COMPUTE_1 = 0x00000001 +CP_DISPATCH_COMPUTE_1_X__MASK = 0xffffffff +CP_DISPATCH_COMPUTE_1_X__SHIFT = 0 +REG_CP_DISPATCH_COMPUTE_2 = 0x00000002 +CP_DISPATCH_COMPUTE_2_Y__MASK = 0xffffffff +CP_DISPATCH_COMPUTE_2_Y__SHIFT = 0 +REG_CP_DISPATCH_COMPUTE_3 = 0x00000003 +CP_DISPATCH_COMPUTE_3_Z__MASK = 0xffffffff +CP_DISPATCH_COMPUTE_3_Z__SHIFT = 0 +REG_CP_SET_RENDER_MODE_0 = 0x00000000 +CP_SET_RENDER_MODE_0_MODE__MASK = 0x000001ff +CP_SET_RENDER_MODE_0_MODE__SHIFT = 0 +REG_CP_SET_RENDER_MODE_1 = 0x00000001 +CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK = 0xffffffff +CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT = 0 +REG_CP_SET_RENDER_MODE_2 = 0x00000002 +CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK = 0xffffffff +CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT = 0 +REG_CP_SET_RENDER_MODE_3 = 0x00000003 +CP_SET_RENDER_MODE_3_VSC_ENABLE = 0x00000008 +CP_SET_RENDER_MODE_3_GMEM_ENABLE = 0x00000010 +REG_CP_SET_RENDER_MODE_4 = 0x00000004 +REG_CP_SET_RENDER_MODE_5 = 0x00000005 +CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK = 0xffffffff +CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT = 0 +REG_CP_SET_RENDER_MODE_6 = 0x00000006 +CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK = 0xffffffff +CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT = 0 +REG_CP_SET_RENDER_MODE_7 = 0x00000007 +CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK = 0xffffffff +CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_0 = 0x00000000 +CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_1 = 0x00000001 +CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_2 = 0x00000002 +REG_CP_COMPUTE_CHECKPOINT_3 = 0x00000003 +REG_CP_COMPUTE_CHECKPOINT_4 = 0x00000004 +CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_5 = 0x00000005 +CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_6 = 0x00000006 +CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_7 = 0x00000007 +REG_CP_PERFCOUNTER_ACTION_0 = 0x00000000 +REG_CP_PERFCOUNTER_ACTION_1 = 0x00000001 +CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK = 0xffffffff +CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT = 0 +REG_CP_PERFCOUNTER_ACTION_2 = 0x00000002 +CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK = 0xffffffff +CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT = 0 +REG_CP_EVENT_WRITE_0 = 0x00000000 +CP_EVENT_WRITE_0_EVENT__MASK = 0x000000ff +CP_EVENT_WRITE_0_EVENT__SHIFT = 0 +CP_EVENT_WRITE_0_TIMESTAMP = 0x40000000 +CP_EVENT_WRITE_0_IRQ = 0x80000000 +REG_CP_EVENT_WRITE_1 = 0x00000001 +CP_EVENT_WRITE_1_ADDR_0_LO__MASK = 0xffffffff +CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT = 0 +REG_CP_EVENT_WRITE_2 = 0x00000002 +CP_EVENT_WRITE_2_ADDR_0_HI__MASK = 0xffffffff +CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT = 0 +REG_CP_EVENT_WRITE_3 = 0x00000003 +REG_CP_EVENT_WRITE7_0 = 0x00000000 +CP_EVENT_WRITE7_0_EVENT__MASK = 0x000000ff +CP_EVENT_WRITE7_0_EVENT__SHIFT = 0 +CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT = 0x00001000 +CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET = 0x00002000 +CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF = 0x00004000 +CP_EVENT_WRITE7_0_INC_BV_COUNT = 0x00010000 +CP_EVENT_WRITE7_0_INC_BR_COUNT = 0x00020000 +CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE = 0x00040000 +CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE = 0x00080000 +CP_EVENT_WRITE7_0_WRITE_SRC__MASK = 0x00700000 +CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT = 20 +CP_EVENT_WRITE7_0_WRITE_DST__MASK = 0x01000000 +CP_EVENT_WRITE7_0_WRITE_DST__SHIFT = 24 +CP_EVENT_WRITE7_0_WRITE_ENABLED = 0x08000000 +REG_EV_DST_RAM_CP_EVENT_WRITE7_1 = 0x00000001 +EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK = 0xffffffff +EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT = 0 +REG_EV_DST_RAM_CP_EVENT_WRITE7_2 = 0x00000002 +EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK = 0xffffffff +EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT = 0 +REG_EV_DST_RAM_CP_EVENT_WRITE7_3 = 0x00000003 +EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff +EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 +REG_EV_DST_RAM_CP_EVENT_WRITE7_4 = 0x00000004 +EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff +EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 +REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 = 0x00000001 +EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK = 0xffffffff +EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT = 0 +REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 = 0x00000003 +EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff +EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 +REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 = 0x00000004 +EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff +EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 +REG_CP_BLIT_0 = 0x00000000 +CP_BLIT_0_OP__MASK = 0x0000000f +CP_BLIT_0_OP__SHIFT = 0 +REG_CP_BLIT_1 = 0x00000001 +CP_BLIT_1_SRC_X1__MASK = 0x00003fff +CP_BLIT_1_SRC_X1__SHIFT = 0 +CP_BLIT_1_SRC_Y1__MASK = 0x3fff0000 +CP_BLIT_1_SRC_Y1__SHIFT = 16 +REG_CP_BLIT_2 = 0x00000002 +CP_BLIT_2_SRC_X2__MASK = 0x00003fff +CP_BLIT_2_SRC_X2__SHIFT = 0 +CP_BLIT_2_SRC_Y2__MASK = 0x3fff0000 +CP_BLIT_2_SRC_Y2__SHIFT = 16 +REG_CP_BLIT_3 = 0x00000003 +CP_BLIT_3_DST_X1__MASK = 0x00003fff +CP_BLIT_3_DST_X1__SHIFT = 0 +CP_BLIT_3_DST_Y1__MASK = 0x3fff0000 +CP_BLIT_3_DST_Y1__SHIFT = 16 +REG_CP_BLIT_4 = 0x00000004 +CP_BLIT_4_DST_X2__MASK = 0x00003fff +CP_BLIT_4_DST_X2__SHIFT = 0 +CP_BLIT_4_DST_Y2__MASK = 0x3fff0000 +CP_BLIT_4_DST_Y2__SHIFT = 16 +REG_CP_EXEC_CS_0 = 0x00000000 +REG_CP_EXEC_CS_1 = 0x00000001 +CP_EXEC_CS_1_NGROUPS_X__MASK = 0xffffffff +CP_EXEC_CS_1_NGROUPS_X__SHIFT = 0 +REG_CP_EXEC_CS_2 = 0x00000002 +CP_EXEC_CS_2_NGROUPS_Y__MASK = 0xffffffff +CP_EXEC_CS_2_NGROUPS_Y__SHIFT = 0 +REG_CP_EXEC_CS_3 = 0x00000003 +CP_EXEC_CS_3_NGROUPS_Z__MASK = 0xffffffff +CP_EXEC_CS_3_NGROUPS_Z__SHIFT = 0 +REG_A4XX_CP_EXEC_CS_INDIRECT_0 = 0x00000000 +REG_A4XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 +A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK = 0xffffffff +A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT = 0 +REG_A4XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK = 0x00000ffc +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT = 2 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK = 0x003ff000 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT = 12 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK = 0xffc00000 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT = 22 +REG_A5XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 +A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK = 0xffffffff +A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT = 0 +REG_A5XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 +A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK = 0xffffffff +A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT = 0 +REG_A5XX_CP_EXEC_CS_INDIRECT_3 = 0x00000003 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK = 0x00000ffc +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT = 2 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK = 0x003ff000 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT = 12 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK = 0xffc00000 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT = 22 +REG_A6XX_CP_SET_MARKER_0 = 0x00000000 +A6XX_CP_SET_MARKER_0_MODE__MASK = 0x000001ff +A6XX_CP_SET_MARKER_0_MODE__SHIFT = 0 +A6XX_CP_SET_MARKER_0_MARKER__MASK = 0x0000000f +A6XX_CP_SET_MARKER_0_MARKER__SHIFT = 0 +REG_A6XX_CP_SET_PSEUDO_REG_ = lambda i0: (0x00000000 + 0x3*i0 ) +A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK = 0x000007ff +A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT = 0 +A6XX_CP_SET_PSEUDO_REG__1_LO__MASK = 0xffffffff +A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT = 0 +A6XX_CP_SET_PSEUDO_REG__2_HI__MASK = 0xffffffff +A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT = 0 +REG_A6XX_CP_REG_TEST_0 = 0x00000000 +A6XX_CP_REG_TEST_0_REG__MASK = 0x0003ffff +A6XX_CP_REG_TEST_0_REG__SHIFT = 0 +A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK = 0x0003ffff +A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT = 0 +A6XX_CP_REG_TEST_0_SOURCE__MASK = 0x00040000 +A6XX_CP_REG_TEST_0_SOURCE__SHIFT = 18 +A6XX_CP_REG_TEST_0_BIT__MASK = 0x01f00000 +A6XX_CP_REG_TEST_0_BIT__SHIFT = 20 +A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME = 0x02000000 +A6XX_CP_REG_TEST_0_PRED_BIT__MASK = 0x7c000000 +A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT = 26 +A6XX_CP_REG_TEST_0_PRED_UPDATE = 0x80000000 +REG_A6XX_CP_REG_TEST_PRED_MASK = 0x00000001 +REG_A6XX_CP_REG_TEST_PRED_VAL = 0x00000002 +REG_CP_COND_REG_EXEC_0 = 0x00000000 +CP_COND_REG_EXEC_0_REG0__MASK = 0x0003ffff +CP_COND_REG_EXEC_0_REG0__SHIFT = 0 +CP_COND_REG_EXEC_0_PRED_BIT__MASK = 0x007c0000 +CP_COND_REG_EXEC_0_PRED_BIT__SHIFT = 18 +CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME = 0x00800000 +CP_COND_REG_EXEC_0_ONCHIP_MEM = 0x01000000 +CP_COND_REG_EXEC_0_BINNING = 0x02000000 +CP_COND_REG_EXEC_0_GMEM = 0x04000000 +CP_COND_REG_EXEC_0_SYSMEM = 0x08000000 +CP_COND_REG_EXEC_0_BV = 0x02000000 +CP_COND_REG_EXEC_0_BR = 0x04000000 +CP_COND_REG_EXEC_0_LPAC = 0x08000000 +CP_COND_REG_EXEC_0_MODE__MASK = 0xf0000000 +CP_COND_REG_EXEC_0_MODE__SHIFT = 28 +REG_PRED_TEST_CP_COND_REG_EXEC_1 = 0x00000001 +PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff +PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 +REG_REG_COMPARE_CP_COND_REG_EXEC_1 = 0x00000001 +REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK = 0x0003ffff +REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT = 0 +REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM = 0x01000000 +REG_RENDER_MODE_CP_COND_REG_EXEC_1 = 0x00000001 +RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff +RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 +REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 = 0x00000001 +REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK = 0xffffffff +REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT = 0 +REG_THREAD_MODE_CP_COND_REG_EXEC_1 = 0x00000001 +THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff +THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 +REG_CP_COND_REG_EXEC_2 = 0x00000002 +CP_COND_REG_EXEC_2_DWORDS__MASK = 0x00ffffff +CP_COND_REG_EXEC_2_DWORDS__SHIFT = 0 +REG_CP_COND_EXEC_0 = 0x00000000 +CP_COND_EXEC_0_ADDR0_LO__MASK = 0xffffffff +CP_COND_EXEC_0_ADDR0_LO__SHIFT = 0 +REG_CP_COND_EXEC_1 = 0x00000001 +CP_COND_EXEC_1_ADDR0_HI__MASK = 0xffffffff +CP_COND_EXEC_1_ADDR0_HI__SHIFT = 0 +REG_CP_COND_EXEC_2 = 0x00000002 +CP_COND_EXEC_2_ADDR1_LO__MASK = 0xffffffff +CP_COND_EXEC_2_ADDR1_LO__SHIFT = 0 +REG_CP_COND_EXEC_3 = 0x00000003 +CP_COND_EXEC_3_ADDR1_HI__MASK = 0xffffffff +CP_COND_EXEC_3_ADDR1_HI__SHIFT = 0 +REG_CP_COND_EXEC_4 = 0x00000004 +CP_COND_EXEC_4_REF__MASK = 0xffffffff +CP_COND_EXEC_4_REF__SHIFT = 0 +REG_CP_COND_EXEC_5 = 0x00000005 +CP_COND_EXEC_5_DWORDS__MASK = 0xffffffff +CP_COND_EXEC_5_DWORDS__SHIFT = 0 +REG_CP_SET_CTXSWITCH_IB_0 = 0x00000000 +CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK = 0xffffffff +CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT = 0 +REG_CP_SET_CTXSWITCH_IB_1 = 0x00000001 +CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK = 0xffffffff +CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT = 0 +REG_CP_SET_CTXSWITCH_IB_2 = 0x00000002 +CP_SET_CTXSWITCH_IB_2_DWORDS__MASK = 0x000fffff +CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT = 0 +CP_SET_CTXSWITCH_IB_2_TYPE__MASK = 0x00300000 +CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT = 20 +REG_CP_REG_WRITE_0 = 0x00000000 +CP_REG_WRITE_0_TRACKER__MASK = 0x0000000f +CP_REG_WRITE_0_TRACKER__SHIFT = 0 +REG_CP_REG_WRITE_1 = 0x00000001 +REG_CP_REG_WRITE_2 = 0x00000002 +REG_CP_SMMU_TABLE_UPDATE_0 = 0x00000000 +CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK = 0xffffffff +CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT = 0 +REG_CP_SMMU_TABLE_UPDATE_1 = 0x00000001 +CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK = 0x0000ffff +CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT = 0 +CP_SMMU_TABLE_UPDATE_1_ASID__MASK = 0xffff0000 +CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT = 16 +REG_CP_SMMU_TABLE_UPDATE_2 = 0x00000002 +CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK = 0xffffffff +CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT = 0 +REG_CP_SMMU_TABLE_UPDATE_3 = 0x00000003 +CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK = 0xffffffff +CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT = 0 +REG_CP_START_BIN_BIN_COUNT = 0x00000000 +REG_CP_START_BIN_PREFIX_ADDR = 0x00000001 +REG_CP_START_BIN_PREFIX_DWORDS = 0x00000003 +REG_CP_START_BIN_BODY_DWORDS = 0x00000004 +REG_CP_WAIT_TIMESTAMP_0 = 0x00000000 +CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK = 0x00000003 +CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT = 0 +CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK = 0x00000010 +CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT = 4 +REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR = 0x00000001 +REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 = 0x00000001 +REG_CP_WAIT_TIMESTAMP_SRC_0 = 0x00000003 +REG_CP_WAIT_TIMESTAMP_SRC_1 = 0x00000004 +REG_CP_BV_BR_COUNT_OPS_0 = 0x00000000 +CP_BV_BR_COUNT_OPS_0_OP__MASK = 0x0000000f +CP_BV_BR_COUNT_OPS_0_OP__SHIFT = 0 +REG_CP_BV_BR_COUNT_OPS_1 = 0x00000001 +CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK = 0x0000ffff +CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT = 0 +REG_CP_MODIFY_TIMESTAMP_0 = 0x00000000 +CP_MODIFY_TIMESTAMP_0_ADD__MASK = 0x000000ff +CP_MODIFY_TIMESTAMP_0_ADD__SHIFT = 0 +CP_MODIFY_TIMESTAMP_0_OP__MASK = 0xf0000000 +CP_MODIFY_TIMESTAMP_0_OP__SHIFT = 28 +REG_CP_MEM_TO_SCRATCH_MEM_0 = 0x00000000 +CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK = 0x0000003f +CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT = 0 +REG_CP_MEM_TO_SCRATCH_MEM_1 = 0x00000001 +CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK = 0x0000003f +CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT = 0 +REG_CP_MEM_TO_SCRATCH_MEM_2 = 0x00000002 +CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK = 0xffffffff +CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT = 0 +REG_CP_MEM_TO_SCRATCH_MEM_3 = 0x00000003 +CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK = 0xffffffff +CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT = 0 +REG_CP_THREAD_CONTROL_0 = 0x00000000 +CP_THREAD_CONTROL_0_THREAD__MASK = 0x00000003 +CP_THREAD_CONTROL_0_THREAD__SHIFT = 0 +CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE = 0x08000000 +CP_THREAD_CONTROL_0_SYNC_THREADS = 0x80000000 +REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE = 0x00000000 +REG_CP_FIXED_STRIDE_DRAW_TABLE_2 = 0x00000002 +CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK = 0x00000fff +CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT = 0 +CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK = 0xfff00000 +CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT = 20 +REG_CP_FIXED_STRIDE_DRAW_TABLE_3 = 0x00000003 +CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK = 0xffffffff +CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT = 0 +REG_CP_RESET_CONTEXT_STATE_0 = 0x00000000 +CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS = 0x00000001 +CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE = 0x00000002 +CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS = 0x00000004 +REG_AXXX_CP_RB_BASE = 0x000001c0 +REG_AXXX_CP_RB_CNTL = 0x000001c1 +AXXX_CP_RB_CNTL_BUFSZ__MASK = 0x0000003f +AXXX_CP_RB_CNTL_BUFSZ__SHIFT = 0 +AXXX_CP_RB_CNTL_BLKSZ__MASK = 0x00003f00 +AXXX_CP_RB_CNTL_BLKSZ__SHIFT = 8 +AXXX_CP_RB_CNTL_BUF_SWAP__MASK = 0x00030000 +AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT = 16 +AXXX_CP_RB_CNTL_POLL_EN = 0x00100000 +AXXX_CP_RB_CNTL_NO_UPDATE = 0x08000000 +AXXX_CP_RB_CNTL_RPTR_WR_EN = 0x80000000 +REG_AXXX_CP_RB_RPTR_ADDR = 0x000001c3 +AXXX_CP_RB_RPTR_ADDR_SWAP__MASK = 0x00000003 +AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT = 0 +AXXX_CP_RB_RPTR_ADDR_ADDR__MASK = 0xfffffffc +AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT = 2 +REG_AXXX_CP_RB_RPTR = 0x000001c4 +REG_AXXX_CP_RB_WPTR = 0x000001c5 +REG_AXXX_CP_RB_WPTR_DELAY = 0x000001c6 +REG_AXXX_CP_RB_RPTR_WR = 0x000001c7 +REG_AXXX_CP_RB_WPTR_BASE = 0x000001c8 +REG_AXXX_CP_QUEUE_THRESHOLDS = 0x000001d5 +AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK = 0x0000000f +AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT = 0 +AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK = 0x00000f00 +AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT = 8 +AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK = 0x000f0000 +AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT = 16 +REG_AXXX_CP_MEQ_THRESHOLDS = 0x000001d6 +AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK = 0x001f0000 +AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT = 16 +AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK = 0x1f000000 +AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT = 24 +REG_AXXX_CP_CSQ_AVAIL = 0x000001d7 +AXXX_CP_CSQ_AVAIL_RING__MASK = 0x0000007f +AXXX_CP_CSQ_AVAIL_RING__SHIFT = 0 +AXXX_CP_CSQ_AVAIL_IB1__MASK = 0x00007f00 +AXXX_CP_CSQ_AVAIL_IB1__SHIFT = 8 +AXXX_CP_CSQ_AVAIL_IB2__MASK = 0x007f0000 +AXXX_CP_CSQ_AVAIL_IB2__SHIFT = 16 +REG_AXXX_CP_STQ_AVAIL = 0x000001d8 +AXXX_CP_STQ_AVAIL_ST__MASK = 0x0000007f +AXXX_CP_STQ_AVAIL_ST__SHIFT = 0 +REG_AXXX_CP_MEQ_AVAIL = 0x000001d9 +AXXX_CP_MEQ_AVAIL_MEQ__MASK = 0x0000001f +AXXX_CP_MEQ_AVAIL_MEQ__SHIFT = 0 +REG_AXXX_SCRATCH_UMSK = 0x000001dc +AXXX_SCRATCH_UMSK_UMSK__MASK = 0x000000ff +AXXX_SCRATCH_UMSK_UMSK__SHIFT = 0 +AXXX_SCRATCH_UMSK_SWAP__MASK = 0x00030000 +AXXX_SCRATCH_UMSK_SWAP__SHIFT = 16 +REG_AXXX_SCRATCH_ADDR = 0x000001dd +REG_AXXX_CP_ME_RDADDR = 0x000001ea +REG_AXXX_CP_STATE_DEBUG_INDEX = 0x000001ec +REG_AXXX_CP_STATE_DEBUG_DATA = 0x000001ed +REG_AXXX_CP_INT_CNTL = 0x000001f2 +AXXX_CP_INT_CNTL_SW_INT_MASK = 0x00080000 +AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK = 0x00800000 +AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK = 0x01000000 +AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK = 0x02000000 +AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK = 0x04000000 +AXXX_CP_INT_CNTL_IB_ERROR_MASK = 0x08000000 +AXXX_CP_INT_CNTL_IB2_INT_MASK = 0x20000000 +AXXX_CP_INT_CNTL_IB1_INT_MASK = 0x40000000 +AXXX_CP_INT_CNTL_RB_INT_MASK = 0x80000000 +REG_AXXX_CP_INT_STATUS = 0x000001f3 +REG_AXXX_CP_INT_ACK = 0x000001f4 +REG_AXXX_CP_ME_CNTL = 0x000001f6 +AXXX_CP_ME_CNTL_BUSY = 0x20000000 +AXXX_CP_ME_CNTL_HALT = 0x10000000 +REG_AXXX_CP_ME_STATUS = 0x000001f7 +REG_AXXX_CP_ME_RAM_WADDR = 0x000001f8 +REG_AXXX_CP_ME_RAM_RADDR = 0x000001f9 +REG_AXXX_CP_ME_RAM_DATA = 0x000001fa +REG_AXXX_CP_DEBUG = 0x000001fc +AXXX_CP_DEBUG_PREDICATE_DISABLE = 0x00800000 +AXXX_CP_DEBUG_PROG_END_PTR_ENABLE = 0x01000000 +AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE = 0x02000000 +AXXX_CP_DEBUG_PREFETCH_PASS_NOPS = 0x04000000 +AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE = 0x08000000 +AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE = 0x10000000 +AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL = 0x40000000 +AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE = 0x80000000 +REG_AXXX_CP_CSQ_RB_STAT = 0x000001fd +AXXX_CP_CSQ_RB_STAT_RPTR__MASK = 0x0000007f +AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT = 0 +AXXX_CP_CSQ_RB_STAT_WPTR__MASK = 0x007f0000 +AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT = 16 +REG_AXXX_CP_CSQ_IB1_STAT = 0x000001fe +AXXX_CP_CSQ_IB1_STAT_RPTR__MASK = 0x0000007f +AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT = 0 +AXXX_CP_CSQ_IB1_STAT_WPTR__MASK = 0x007f0000 +AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT = 16 +REG_AXXX_CP_CSQ_IB2_STAT = 0x000001ff +AXXX_CP_CSQ_IB2_STAT_RPTR__MASK = 0x0000007f +AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT = 0 +AXXX_CP_CSQ_IB2_STAT_WPTR__MASK = 0x007f0000 +AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT = 16 +REG_AXXX_CP_NON_PREFETCH_CNTRS = 0x00000440 +REG_AXXX_CP_STQ_ST_STAT = 0x00000443 +REG_AXXX_CP_ST_BASE = 0x0000044d +REG_AXXX_CP_ST_BUFSZ = 0x0000044e +REG_AXXX_CP_MEQ_STAT = 0x0000044f +REG_AXXX_CP_MIU_TAG_STAT = 0x00000452 +REG_AXXX_CP_BIN_MASK_LO = 0x00000454 +REG_AXXX_CP_BIN_MASK_HI = 0x00000455 +REG_AXXX_CP_BIN_SELECT_LO = 0x00000456 +REG_AXXX_CP_BIN_SELECT_HI = 0x00000457 +REG_AXXX_CP_IB1_BASE = 0x00000458 +REG_AXXX_CP_IB1_BUFSZ = 0x00000459 +REG_AXXX_CP_IB2_BASE = 0x0000045a +REG_AXXX_CP_IB2_BUFSZ = 0x0000045b +REG_AXXX_CP_STAT = 0x0000047f +AXXX_CP_STAT_CP_BUSY = 0x80000000 +AXXX_CP_STAT_VS_EVENT_FIFO_BUSY = 0x40000000 +AXXX_CP_STAT_PS_EVENT_FIFO_BUSY = 0x20000000 +AXXX_CP_STAT_CF_EVENT_FIFO_BUSY = 0x10000000 +AXXX_CP_STAT_RB_EVENT_FIFO_BUSY = 0x08000000 +AXXX_CP_STAT_ME_BUSY = 0x04000000 +AXXX_CP_STAT_MIU_WR_C_BUSY = 0x02000000 +AXXX_CP_STAT_CP_3D_BUSY = 0x00800000 +AXXX_CP_STAT_CP_NRT_BUSY = 0x00400000 +AXXX_CP_STAT_RBIU_SCRATCH_BUSY = 0x00200000 +AXXX_CP_STAT_RCIU_ME_BUSY = 0x00100000 +AXXX_CP_STAT_RCIU_PFP_BUSY = 0x00080000 +AXXX_CP_STAT_MEQ_RING_BUSY = 0x00040000 +AXXX_CP_STAT_PFP_BUSY = 0x00020000 +AXXX_CP_STAT_ST_QUEUE_BUSY = 0x00010000 +AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY = 0x00002000 +AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY = 0x00001000 +AXXX_CP_STAT_RING_QUEUE_BUSY = 0x00000800 +AXXX_CP_STAT_CSF_BUSY = 0x00000400 +AXXX_CP_STAT_CSF_ST_BUSY = 0x00000200 +AXXX_CP_STAT_EVENT_BUSY = 0x00000100 +AXXX_CP_STAT_CSF_INDIRECT2_BUSY = 0x00000080 +AXXX_CP_STAT_CSF_INDIRECTS_BUSY = 0x00000040 +AXXX_CP_STAT_CSF_RING_BUSY = 0x00000020 +AXXX_CP_STAT_RCIU_BUSY = 0x00000010 +AXXX_CP_STAT_RBIU_BUSY = 0x00000008 +AXXX_CP_STAT_MIU_RD_RETURN_BUSY = 0x00000004 +AXXX_CP_STAT_MIU_RD_REQ_BUSY = 0x00000002 +AXXX_CP_STAT_MIU_WR_BUSY = 0x00000001 +REG_AXXX_CP_SCRATCH_REG0 = 0x00000578 +REG_AXXX_CP_SCRATCH_REG1 = 0x00000579 +REG_AXXX_CP_SCRATCH_REG2 = 0x0000057a +REG_AXXX_CP_SCRATCH_REG3 = 0x0000057b +REG_AXXX_CP_SCRATCH_REG4 = 0x0000057c +REG_AXXX_CP_SCRATCH_REG5 = 0x0000057d +REG_AXXX_CP_SCRATCH_REG6 = 0x0000057e +REG_AXXX_CP_SCRATCH_REG7 = 0x0000057f +REG_AXXX_CP_ME_VS_EVENT_SRC = 0x00000600 +REG_AXXX_CP_ME_VS_EVENT_ADDR = 0x00000601 +REG_AXXX_CP_ME_VS_EVENT_DATA = 0x00000602 +REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM = 0x00000603 +REG_AXXX_CP_ME_VS_EVENT_DATA_SWM = 0x00000604 +REG_AXXX_CP_ME_PS_EVENT_SRC = 0x00000605 +REG_AXXX_CP_ME_PS_EVENT_ADDR = 0x00000606 +REG_AXXX_CP_ME_PS_EVENT_DATA = 0x00000607 +REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM = 0x00000608 +REG_AXXX_CP_ME_PS_EVENT_DATA_SWM = 0x00000609 +REG_AXXX_CP_ME_CF_EVENT_SRC = 0x0000060a +REG_AXXX_CP_ME_CF_EVENT_ADDR = 0x0000060b +REG_AXXX_CP_ME_CF_EVENT_DATA = 0x0000060c +REG_AXXX_CP_ME_NRT_ADDR = 0x0000060d +REG_AXXX_CP_ME_NRT_DATA = 0x0000060e +REG_AXXX_CP_ME_VS_FETCH_DONE_SRC = 0x00000612 +REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR = 0x00000613 +REG_AXXX_CP_ME_VS_FETCH_DONE_DATA = 0x00000614 +A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE = 0x00000001 +A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR = 0x00000002 +A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 = 0x00000010 +A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 = 0x00000020 +A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW = 0x00000040 +A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR = 0x00000080 +A6XX_RBBM_INT_0_MASK_CP_SW = 0x00000100 +A6XX_RBBM_INT_0_MASK_CP_HW_ERROR = 0x00000200 +A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS = 0x00000400 +A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS = 0x00000800 +A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS = 0x00001000 +A6XX_RBBM_INT_0_MASK_CP_IB2 = 0x00002000 +A6XX_RBBM_INT_0_MASK_CP_IB1 = 0x00004000 +A6XX_RBBM_INT_0_MASK_CP_RB = 0x00008000 +A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT = 0x00008000 +A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC = 0x00010000 +A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS = 0x00020000 +A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS = 0x00040000 +A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS = 0x00100000 +A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC = 0x00200000 +A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW = 0x00400000 +A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT = 0x00800000 +A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS = 0x01000000 +A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR = 0x02000000 +A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 = 0x04000000 +A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 = 0x08000000 +A6XX_RBBM_INT_0_MASK_TSBWRITEERROR = 0x10000000 +A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION = 0x20000000 +A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ = 0x40000000 +A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG = 0x80000000 +A6XX_CP_INT_CP_OPCODE_ERROR = 0x00000001 +A6XX_CP_INT_CP_UCODE_ERROR = 0x00000002 +A6XX_CP_INT_CP_HW_FAULT_ERROR = 0x00000004 +A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR = 0x00000010 +A6XX_CP_INT_CP_AHB_ERROR = 0x00000020 +A6XX_CP_INT_CP_VSD_PARITY_ERROR = 0x00000040 +A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR = 0x00000080 +A6XX_CP_INT_CP_OPCODE_ERROR_LPAC = 0x00000100 +A6XX_CP_INT_CP_UCODE_ERROR_LPAC = 0x00000200 +A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC = 0x00000400 +A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC = 0x00000800 +A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC = 0x00001000 +A6XX_CP_INT_CP_OPCODE_ERROR_BV = 0x00002000 +A6XX_CP_INT_CP_UCODE_ERROR_BV = 0x00004000 +A6XX_CP_INT_CP_HW_FAULT_ERROR_BV = 0x00008000 +A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV = 0x00010000 +A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV = 0x00020000 +REG_A6XX_CP_RB_BASE = 0x00000800 +REG_A6XX_CP_RB_CNTL = 0x00000802 +REG_A6XX_CP_RB_RPTR_ADDR = 0x00000804 +REG_A6XX_CP_RB_RPTR = 0x00000806 +REG_A6XX_CP_RB_WPTR = 0x00000807 +REG_A6XX_CP_SQE_CNTL = 0x00000808 +REG_A6XX_CP_CP2GMU_STATUS = 0x00000812 +A6XX_CP_CP2GMU_STATUS_IFPC = 0x00000001 +REG_A6XX_CP_HW_FAULT = 0x00000821 +REG_A6XX_CP_INTERRUPT_STATUS = 0x00000823 +REG_A6XX_CP_PROTECT_STATUS = 0x00000824 +REG_A6XX_CP_STATUS_1 = 0x00000825 +REG_A6XX_CP_SQE_INSTR_BASE = 0x00000830 +REG_A6XX_CP_MISC_CNTL = 0x00000840 +REG_A6XX_CP_APRIV_CNTL = 0x00000844 +A6XX_CP_APRIV_CNTL_CDWRITE = 0x00000040 +A6XX_CP_APRIV_CNTL_CDREAD = 0x00000020 +A6XX_CP_APRIV_CNTL_RBRPWB = 0x00000008 +A6XX_CP_APRIV_CNTL_RBPRIVLEVEL = 0x00000004 +A6XX_CP_APRIV_CNTL_RBFETCH = 0x00000002 +A6XX_CP_APRIV_CNTL_ICACHE = 0x00000001 +REG_A6XX_CP_PREEMPT_THRESHOLD = 0x000008c0 +REG_A6XX_CP_ROQ_THRESHOLDS_1 = 0x000008c1 +A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK = 0x000000ff +A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT = 0 +A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK = 0x0000ff00 +A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT = 8 +A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK = 0x00ff0000 +A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT = 16 +A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK = 0xff000000 +A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT = 24 +REG_A6XX_CP_ROQ_THRESHOLDS_2 = 0x000008c2 +A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK = 0x000001ff +A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT = 0 +A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK = 0xffff0000 +A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT = 16 +REG_A6XX_CP_MEM_POOL_SIZE = 0x000008c3 +REG_A6XX_CP_CHICKEN_DBG = 0x00000841 +REG_A6XX_CP_ADDR_MODE_CNTL = 0x00000842 +REG_A6XX_CP_DBG_ECO_CNTL = 0x00000843 +REG_A6XX_CP_PROTECT_CNTL = 0x0000084f +A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE = 0x00000008 +A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN = 0x00000002 +A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN = 0x00000001 +REG_A6XX_CP_SCRATCH = lambda i0: (0x00000883 + 0x1*i0 ) +REG_A6XX_CP_PROTECT = lambda i0: (0x00000850 + 0x1*i0 ) +A6XX_CP_PROTECT_REG_BASE_ADDR__MASK = 0x0003ffff +A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT = 0 +A6XX_CP_PROTECT_REG_MASK_LEN__MASK = 0x7ffc0000 +A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT = 18 +A6XX_CP_PROTECT_REG_READ = 0x80000000 +REG_A6XX_CP_CONTEXT_SWITCH_CNTL = 0x000008a0 +REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO = 0x000008a1 +REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR = 0x000008a3 +REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR = 0x000008a5 +REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR = 0x000008a7 +REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS = 0x000008ab +REG_A6XX_CP_PERFCTR_CP_SEL = lambda i0: (0x000008d0 + 0x1*i0 ) +REG_A7XX_CP_BV_PERFCTR_CP_SEL = lambda i0: (0x000008e0 + 0x1*i0 ) +REG_A6XX_CP_CRASH_SCRIPT_BASE = 0x00000900 +REG_A6XX_CP_CRASH_DUMP_CNTL = 0x00000902 +REG_A6XX_CP_CRASH_DUMP_STATUS = 0x00000903 +REG_A6XX_CP_SQE_STAT_ADDR = 0x00000908 +REG_A6XX_CP_SQE_STAT_DATA = 0x00000909 +REG_A6XX_CP_DRAW_STATE_ADDR = 0x0000090a +REG_A6XX_CP_DRAW_STATE_DATA = 0x0000090b +REG_A6XX_CP_ROQ_DBG_ADDR = 0x0000090c +REG_A6XX_CP_ROQ_DBG_DATA = 0x0000090d +REG_A6XX_CP_MEM_POOL_DBG_ADDR = 0x0000090e +REG_A6XX_CP_MEM_POOL_DBG_DATA = 0x0000090f +REG_A6XX_CP_SQE_UCODE_DBG_ADDR = 0x00000910 +REG_A6XX_CP_SQE_UCODE_DBG_DATA = 0x00000911 +REG_A6XX_CP_IB1_BASE = 0x00000928 +REG_A6XX_CP_IB1_REM_SIZE = 0x0000092a +REG_A6XX_CP_IB2_BASE = 0x0000092b +REG_A6XX_CP_IB2_REM_SIZE = 0x0000092d +REG_A6XX_CP_SDS_BASE = 0x0000092e +REG_A6XX_CP_SDS_REM_SIZE = 0x00000930 +REG_A6XX_CP_MRB_BASE = 0x00000931 +REG_A6XX_CP_MRB_REM_SIZE = 0x00000933 +REG_A6XX_CP_VSD_BASE = 0x00000934 +REG_A6XX_CP_ROQ_RB_STAT = 0x00000939 +A6XX_CP_ROQ_RB_STAT_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT = 0 +A6XX_CP_ROQ_RB_STAT_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_IB1_STAT = 0x0000093a +A6XX_CP_ROQ_IB1_STAT_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT = 0 +A6XX_CP_ROQ_IB1_STAT_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_IB2_STAT = 0x0000093b +A6XX_CP_ROQ_IB2_STAT_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT = 0 +A6XX_CP_ROQ_IB2_STAT_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_SDS_STAT = 0x0000093c +A6XX_CP_ROQ_SDS_STAT_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT = 0 +A6XX_CP_ROQ_SDS_STAT_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_MRB_STAT = 0x0000093d +A6XX_CP_ROQ_MRB_STAT_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT = 0 +A6XX_CP_ROQ_MRB_STAT_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_VSD_STAT = 0x0000093e +A6XX_CP_ROQ_VSD_STAT_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT = 0 +A6XX_CP_ROQ_VSD_STAT_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT = 16 +REG_A6XX_CP_IB1_DWORDS = 0x00000943 +REG_A6XX_CP_IB2_DWORDS = 0x00000944 +REG_A6XX_CP_SDS_DWORDS = 0x00000945 +REG_A6XX_CP_MRB_DWORDS = 0x00000946 +REG_A6XX_CP_VSD_DWORDS = 0x00000947 +REG_A6XX_CP_ROQ_AVAIL_RB = 0x00000948 +A6XX_CP_ROQ_AVAIL_RB_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_IB1 = 0x00000949 +A6XX_CP_ROQ_AVAIL_IB1_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_IB2 = 0x0000094a +A6XX_CP_ROQ_AVAIL_IB2_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_SDS = 0x0000094b +A6XX_CP_ROQ_AVAIL_SDS_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_MRB = 0x0000094c +A6XX_CP_ROQ_AVAIL_MRB_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_VSD = 0x0000094d +A6XX_CP_ROQ_AVAIL_VSD_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT = 16 +REG_A6XX_CP_ALWAYS_ON_COUNTER = 0x00000980 +REG_A6XX_CP_AHB_CNTL = 0x0000098d +REG_A6XX_CP_APERTURE_CNTL_HOST = 0x00000a00 +REG_A7XX_CP_APERTURE_CNTL_HOST = 0x00000a00 +A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK = 0x00003000 +A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT = 12 +A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK = 0x00000700 +A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT = 8 +A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK = 0x00000030 +A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT = 4 +REG_A6XX_CP_APERTURE_CNTL_CD = 0x00000a03 +REG_A7XX_CP_APERTURE_CNTL_CD = 0x00000a03 +A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK = 0x00003000 +A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT = 12 +A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK = 0x00000700 +A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT = 8 +A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK = 0x00000030 +A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT = 4 +REG_A7XX_CP_BV_PROTECT_STATUS = 0x00000a61 +REG_A7XX_CP_BV_HW_FAULT = 0x00000a64 +REG_A7XX_CP_BV_DRAW_STATE_ADDR = 0x00000a81 +REG_A7XX_CP_BV_DRAW_STATE_DATA = 0x00000a82 +REG_A7XX_CP_BV_ROQ_DBG_ADDR = 0x00000a83 +REG_A7XX_CP_BV_ROQ_DBG_DATA = 0x00000a84 +REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR = 0x00000a85 +REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA = 0x00000a86 +REG_A7XX_CP_BV_SQE_STAT_ADDR = 0x00000a87 +REG_A7XX_CP_BV_SQE_STAT_DATA = 0x00000a88 +REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR = 0x00000a96 +REG_A7XX_CP_BV_MEM_POOL_DBG_DATA = 0x00000a97 +REG_A7XX_CP_BV_RB_RPTR_ADDR = 0x00000a98 +REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR = 0x00000a9a +REG_A7XX_CP_RESOURCE_TBL_DBG_DATA = 0x00000a9b +REG_A7XX_CP_BV_APRIV_CNTL = 0x00000ad0 +REG_A7XX_CP_BV_CHICKEN_DBG = 0x00000ada +REG_A7XX_CP_LPAC_DRAW_STATE_ADDR = 0x00000b0a +REG_A7XX_CP_LPAC_DRAW_STATE_DATA = 0x00000b0b +REG_A7XX_CP_LPAC_ROQ_DBG_ADDR = 0x00000b0c +REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR = 0x00000b27 +REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA = 0x00000b28 +REG_A7XX_CP_SQE_AC_STAT_ADDR = 0x00000b29 +REG_A7XX_CP_SQE_AC_STAT_DATA = 0x00000b2a +REG_A7XX_CP_LPAC_APRIV_CNTL = 0x00000b31 +REG_A6XX_CP_LPAC_PROG_FIFO_SIZE = 0x00000b34 +REG_A7XX_CP_LPAC_ROQ_DBG_DATA = 0x00000b35 +REG_A7XX_CP_LPAC_FIFO_DBG_DATA = 0x00000b36 +REG_A7XX_CP_LPAC_FIFO_DBG_ADDR = 0x00000b40 +REG_A6XX_CP_LPAC_SQE_CNTL = 0x00000b81 +REG_A6XX_CP_LPAC_SQE_INSTR_BASE = 0x00000b82 +REG_A7XX_CP_AQE_INSTR_BASE_0 = 0x00000b70 +REG_A7XX_CP_AQE_INSTR_BASE_1 = 0x00000b72 +REG_A7XX_CP_AQE_APRIV_CNTL = 0x00000b78 +REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 = 0x00000ba8 +REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 = 0x00000ba9 +REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 = 0x00000bac +REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 = 0x00000bad +REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 = 0x00000bb0 +REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 = 0x00000bb1 +REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 = 0x00000bb4 +REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 = 0x00000bb5 +REG_A7XX_CP_AQE_STAT_ADDR_0 = 0x00000bb8 +REG_A7XX_CP_AQE_STAT_ADDR_1 = 0x00000bb9 +REG_A7XX_CP_AQE_STAT_DATA_0 = 0x00000bbc +REG_A7XX_CP_AQE_STAT_DATA_1 = 0x00000bbd +REG_A6XX_VSC_ADDR_MODE_CNTL = 0x00000c01 +REG_A6XX_RBBM_GPR0_CNTL = 0x00000018 +REG_A6XX_RBBM_INT_0_STATUS = 0x00000201 +REG_A6XX_RBBM_STATUS = 0x00000210 +A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB = 0x00800000 +A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP = 0x00400000 +A6XX_RBBM_STATUS_HLSQ_BUSY = 0x00200000 +A6XX_RBBM_STATUS_VSC_BUSY = 0x00100000 +A6XX_RBBM_STATUS_TPL1_BUSY = 0x00080000 +A6XX_RBBM_STATUS_SP_BUSY = 0x00040000 +A6XX_RBBM_STATUS_UCHE_BUSY = 0x00020000 +A6XX_RBBM_STATUS_VPC_BUSY = 0x00010000 +A6XX_RBBM_STATUS_VFD_BUSY = 0x00008000 +A6XX_RBBM_STATUS_TESS_BUSY = 0x00004000 +A6XX_RBBM_STATUS_PC_VSD_BUSY = 0x00002000 +A6XX_RBBM_STATUS_PC_DCALL_BUSY = 0x00001000 +A6XX_RBBM_STATUS_COM_DCOM_BUSY = 0x00000800 +A6XX_RBBM_STATUS_LRZ_BUSY = 0x00000400 +A6XX_RBBM_STATUS_A2D_BUSY = 0x00000200 +A6XX_RBBM_STATUS_CCU_BUSY = 0x00000100 +A6XX_RBBM_STATUS_RB_BUSY = 0x00000080 +A6XX_RBBM_STATUS_RAS_BUSY = 0x00000040 +A6XX_RBBM_STATUS_TSE_BUSY = 0x00000020 +A6XX_RBBM_STATUS_VBIF_BUSY = 0x00000010 +A6XX_RBBM_STATUS_GFX_DBGC_BUSY = 0x00000008 +A6XX_RBBM_STATUS_CP_BUSY = 0x00000004 +A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER = 0x00000002 +A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER = 0x00000001 +REG_A6XX_RBBM_STATUS1 = 0x00000211 +REG_A6XX_RBBM_STATUS2 = 0x00000212 +REG_A6XX_RBBM_STATUS3 = 0x00000213 +A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT = 0x01000000 +REG_A6XX_RBBM_VBIF_GX_RESET_STATUS = 0x00000215 +REG_A7XX_RBBM_CLOCK_MODE_CP = 0x00000260 +REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ = 0x00000284 +REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS = 0x00000285 +REG_A7XX_RBBM_CLOCK_MODE2_GRAS = 0x00000286 +REG_A7XX_RBBM_CLOCK_MODE_BV_VFD = 0x00000287 +REG_A7XX_RBBM_CLOCK_MODE_BV_GPC = 0x00000288 +REG_A7XX_RBBM_SW_FUSE_INT_STATUS = 0x000002c0 +REG_A7XX_RBBM_SW_FUSE_INT_MASK = 0x000002c1 +REG_A6XX_RBBM_PERFCTR_CP = lambda i0: (0x00000400 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_RBBM = lambda i0: (0x0000041c + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_PC = lambda i0: (0x00000424 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_VFD = lambda i0: (0x00000434 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_HLSQ = lambda i0: (0x00000444 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_VPC = lambda i0: (0x00000450 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_CCU = lambda i0: (0x0000045c + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_TSE = lambda i0: (0x00000466 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_RAS = lambda i0: (0x0000046e + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_UCHE = lambda i0: (0x00000476 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_TP = lambda i0: (0x0000048e + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_SP = lambda i0: (0x000004a6 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_RB = lambda i0: (0x000004d6 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_VSC = lambda i0: (0x000004e6 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_LRZ = lambda i0: (0x000004ea + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_CMP = lambda i0: (0x000004f2 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_CP = lambda i0: (0x00000300 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_RBBM = lambda i0: (0x0000031c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_PC = lambda i0: (0x00000324 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_VFD = lambda i0: (0x00000334 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_HLSQ = lambda i0: (0x00000344 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_VPC = lambda i0: (0x00000350 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_CCU = lambda i0: (0x0000035c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_TSE = lambda i0: (0x00000366 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_RAS = lambda i0: (0x0000036e + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_UCHE = lambda i0: (0x00000376 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_TP = lambda i0: (0x0000038e + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_SP = lambda i0: (0x000003a6 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_RB = lambda i0: (0x000003d6 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_VSC = lambda i0: (0x000003e6 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_LRZ = lambda i0: (0x000003ea + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_CMP = lambda i0: (0x000003f2 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_UFC = lambda i0: (0x000003fa + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_HLSQ = lambda i0: (0x00000410 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_CP = lambda i0: (0x0000041c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_SP = lambda i0: (0x0000042a + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_TP = lambda i0: (0x00000442 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_UFC = lambda i0: (0x0000044e + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_PC = lambda i0: (0x00000460 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_VFD = lambda i0: (0x00000470 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_VPC = lambda i0: (0x00000480 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_TSE = lambda i0: (0x0000048c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_RAS = lambda i0: (0x00000494 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_LRZ = lambda i0: (0x0000049c + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_CNTL = 0x00000500 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 = 0x00000501 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 = 0x00000502 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 = 0x00000503 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 = 0x00000504 +REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO = 0x00000505 +REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI = 0x00000506 +REG_A6XX_RBBM_PERFCTR_RBBM_SEL = lambda i0: (0x00000507 + 0x1*i0 ) +REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED = 0x0000050b +REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD = 0x0000050e +REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS = 0x0000050f +REG_A6XX_RBBM_ISDB_CNT = 0x00000533 +REG_A7XX_RBBM_NC_MODE_CNTL = 0x00000534 +REG_A7XX_RBBM_SNAPSHOT_STATUS = 0x00000535 +REG_A6XX_RBBM_PRIMCTR_0_LO = 0x00000540 +REG_A6XX_RBBM_PRIMCTR_0_HI = 0x00000541 +REG_A6XX_RBBM_PRIMCTR_1_LO = 0x00000542 +REG_A6XX_RBBM_PRIMCTR_1_HI = 0x00000543 +REG_A6XX_RBBM_PRIMCTR_2_LO = 0x00000544 +REG_A6XX_RBBM_PRIMCTR_2_HI = 0x00000545 +REG_A6XX_RBBM_PRIMCTR_3_LO = 0x00000546 +REG_A6XX_RBBM_PRIMCTR_3_HI = 0x00000547 +REG_A6XX_RBBM_PRIMCTR_4_LO = 0x00000548 +REG_A6XX_RBBM_PRIMCTR_4_HI = 0x00000549 +REG_A6XX_RBBM_PRIMCTR_5_LO = 0x0000054a +REG_A6XX_RBBM_PRIMCTR_5_HI = 0x0000054b +REG_A6XX_RBBM_PRIMCTR_6_LO = 0x0000054c +REG_A6XX_RBBM_PRIMCTR_6_HI = 0x0000054d +REG_A6XX_RBBM_PRIMCTR_7_LO = 0x0000054e +REG_A6XX_RBBM_PRIMCTR_7_HI = 0x0000054f +REG_A6XX_RBBM_PRIMCTR_8_LO = 0x00000550 +REG_A6XX_RBBM_PRIMCTR_8_HI = 0x00000551 +REG_A6XX_RBBM_PRIMCTR_9_LO = 0x00000552 +REG_A6XX_RBBM_PRIMCTR_9_HI = 0x00000553 +REG_A6XX_RBBM_PRIMCTR_10_LO = 0x00000554 +REG_A6XX_RBBM_PRIMCTR_10_HI = 0x00000555 +REG_A6XX_RBBM_SECVID_TRUST_CNTL = 0x0000f400 +REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE = 0x0000f800 +REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE = 0x0000f802 +REG_A6XX_RBBM_SECVID_TSB_CNTL = 0x0000f803 +REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL = 0x0000f810 +REG_A7XX_RBBM_SECVID_TSB_STATUS = 0x0000fc00 +REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL = 0x00000010 +REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL = 0x00000011 +REG_A6XX_RBBM_GBIF_HALT = 0x00000016 +REG_A6XX_RBBM_GBIF_HALT_ACK = 0x00000017 +REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD = 0x0000001c +A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE = 0x00000001 +REG_A7XX_RBBM_GBIF_HALT = 0x00000016 +REG_A7XX_RBBM_GBIF_HALT_ACK = 0x00000017 +REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL = 0x0000001f +REG_A6XX_RBBM_INT_CLEAR_CMD = 0x00000037 +REG_A6XX_RBBM_INT_0_MASK = 0x00000038 +REG_A7XX_RBBM_INT_2_MASK = 0x0000003a +REG_A6XX_RBBM_SP_HYST_CNT = 0x00000042 +REG_A6XX_RBBM_SW_RESET_CMD = 0x00000043 +REG_A6XX_RBBM_RAC_THRESHOLD_CNT = 0x00000044 +REG_A6XX_RBBM_BLOCK_SW_RESET_CMD = 0x00000045 +REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 = 0x00000046 +REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL = 0x000000ad +REG_A6XX_RBBM_CLOCK_CNTL = 0x000000ae +REG_A6XX_RBBM_CLOCK_CNTL_SP0 = 0x000000b0 +REG_A6XX_RBBM_CLOCK_CNTL_SP1 = 0x000000b1 +REG_A6XX_RBBM_CLOCK_CNTL_SP2 = 0x000000b2 +REG_A6XX_RBBM_CLOCK_CNTL_SP3 = 0x000000b3 +REG_A6XX_RBBM_CLOCK_CNTL2_SP0 = 0x000000b4 +REG_A6XX_RBBM_CLOCK_CNTL2_SP1 = 0x000000b5 +REG_A6XX_RBBM_CLOCK_CNTL2_SP2 = 0x000000b6 +REG_A6XX_RBBM_CLOCK_CNTL2_SP3 = 0x000000b7 +REG_A6XX_RBBM_CLOCK_DELAY_SP0 = 0x000000b8 +REG_A6XX_RBBM_CLOCK_DELAY_SP1 = 0x000000b9 +REG_A6XX_RBBM_CLOCK_DELAY_SP2 = 0x000000ba +REG_A6XX_RBBM_CLOCK_DELAY_SP3 = 0x000000bb +REG_A6XX_RBBM_CLOCK_HYST_SP0 = 0x000000bc +REG_A6XX_RBBM_CLOCK_HYST_SP1 = 0x000000bd +REG_A6XX_RBBM_CLOCK_HYST_SP2 = 0x000000be +REG_A6XX_RBBM_CLOCK_HYST_SP3 = 0x000000bf +REG_A6XX_RBBM_CLOCK_CNTL_TP0 = 0x000000c0 +REG_A6XX_RBBM_CLOCK_CNTL_TP1 = 0x000000c1 +REG_A6XX_RBBM_CLOCK_CNTL_TP2 = 0x000000c2 +REG_A6XX_RBBM_CLOCK_CNTL_TP3 = 0x000000c3 +REG_A6XX_RBBM_CLOCK_CNTL2_TP0 = 0x000000c4 +REG_A6XX_RBBM_CLOCK_CNTL2_TP1 = 0x000000c5 +REG_A6XX_RBBM_CLOCK_CNTL2_TP2 = 0x000000c6 +REG_A6XX_RBBM_CLOCK_CNTL2_TP3 = 0x000000c7 +REG_A6XX_RBBM_CLOCK_CNTL3_TP0 = 0x000000c8 +REG_A6XX_RBBM_CLOCK_CNTL3_TP1 = 0x000000c9 +REG_A6XX_RBBM_CLOCK_CNTL3_TP2 = 0x000000ca +REG_A6XX_RBBM_CLOCK_CNTL3_TP3 = 0x000000cb +REG_A6XX_RBBM_CLOCK_CNTL4_TP0 = 0x000000cc +REG_A6XX_RBBM_CLOCK_CNTL4_TP1 = 0x000000cd +REG_A6XX_RBBM_CLOCK_CNTL4_TP2 = 0x000000ce +REG_A6XX_RBBM_CLOCK_CNTL4_TP3 = 0x000000cf +REG_A6XX_RBBM_CLOCK_DELAY_TP0 = 0x000000d0 +REG_A6XX_RBBM_CLOCK_DELAY_TP1 = 0x000000d1 +REG_A6XX_RBBM_CLOCK_DELAY_TP2 = 0x000000d2 +REG_A6XX_RBBM_CLOCK_DELAY_TP3 = 0x000000d3 +REG_A6XX_RBBM_CLOCK_DELAY2_TP0 = 0x000000d4 +REG_A6XX_RBBM_CLOCK_DELAY2_TP1 = 0x000000d5 +REG_A6XX_RBBM_CLOCK_DELAY2_TP2 = 0x000000d6 +REG_A6XX_RBBM_CLOCK_DELAY2_TP3 = 0x000000d7 +REG_A6XX_RBBM_CLOCK_DELAY3_TP0 = 0x000000d8 +REG_A6XX_RBBM_CLOCK_DELAY3_TP1 = 0x000000d9 +REG_A6XX_RBBM_CLOCK_DELAY3_TP2 = 0x000000da +REG_A6XX_RBBM_CLOCK_DELAY3_TP3 = 0x000000db +REG_A6XX_RBBM_CLOCK_DELAY4_TP0 = 0x000000dc +REG_A6XX_RBBM_CLOCK_DELAY4_TP1 = 0x000000dd +REG_A6XX_RBBM_CLOCK_DELAY4_TP2 = 0x000000de +REG_A6XX_RBBM_CLOCK_DELAY4_TP3 = 0x000000df +REG_A6XX_RBBM_CLOCK_HYST_TP0 = 0x000000e0 +REG_A6XX_RBBM_CLOCK_HYST_TP1 = 0x000000e1 +REG_A6XX_RBBM_CLOCK_HYST_TP2 = 0x000000e2 +REG_A6XX_RBBM_CLOCK_HYST_TP3 = 0x000000e3 +REG_A6XX_RBBM_CLOCK_HYST2_TP0 = 0x000000e4 +REG_A6XX_RBBM_CLOCK_HYST2_TP1 = 0x000000e5 +REG_A6XX_RBBM_CLOCK_HYST2_TP2 = 0x000000e6 +REG_A6XX_RBBM_CLOCK_HYST2_TP3 = 0x000000e7 +REG_A6XX_RBBM_CLOCK_HYST3_TP0 = 0x000000e8 +REG_A6XX_RBBM_CLOCK_HYST3_TP1 = 0x000000e9 +REG_A6XX_RBBM_CLOCK_HYST3_TP2 = 0x000000ea +REG_A6XX_RBBM_CLOCK_HYST3_TP3 = 0x000000eb +REG_A6XX_RBBM_CLOCK_HYST4_TP0 = 0x000000ec +REG_A6XX_RBBM_CLOCK_HYST4_TP1 = 0x000000ed +REG_A6XX_RBBM_CLOCK_HYST4_TP2 = 0x000000ee +REG_A6XX_RBBM_CLOCK_HYST4_TP3 = 0x000000ef +REG_A6XX_RBBM_CLOCK_CNTL_RB0 = 0x000000f0 +REG_A6XX_RBBM_CLOCK_CNTL_RB1 = 0x000000f1 +REG_A6XX_RBBM_CLOCK_CNTL_RB2 = 0x000000f2 +REG_A6XX_RBBM_CLOCK_CNTL_RB3 = 0x000000f3 +REG_A6XX_RBBM_CLOCK_CNTL2_RB0 = 0x000000f4 +REG_A6XX_RBBM_CLOCK_CNTL2_RB1 = 0x000000f5 +REG_A6XX_RBBM_CLOCK_CNTL2_RB2 = 0x000000f6 +REG_A6XX_RBBM_CLOCK_CNTL2_RB3 = 0x000000f7 +REG_A6XX_RBBM_CLOCK_CNTL_CCU0 = 0x000000f8 +REG_A6XX_RBBM_CLOCK_CNTL_CCU1 = 0x000000f9 +REG_A6XX_RBBM_CLOCK_CNTL_CCU2 = 0x000000fa +REG_A6XX_RBBM_CLOCK_CNTL_CCU3 = 0x000000fb +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 = 0x00000100 +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 = 0x00000101 +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 = 0x00000102 +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 = 0x00000103 +REG_A6XX_RBBM_CLOCK_CNTL_RAC = 0x00000104 +REG_A6XX_RBBM_CLOCK_CNTL2_RAC = 0x00000105 +REG_A6XX_RBBM_CLOCK_DELAY_RAC = 0x00000106 +REG_A6XX_RBBM_CLOCK_HYST_RAC = 0x00000107 +REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM = 0x00000108 +REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM = 0x00000109 +REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM = 0x0000010a +REG_A6XX_RBBM_CLOCK_CNTL_UCHE = 0x0000010b +REG_A6XX_RBBM_CLOCK_CNTL2_UCHE = 0x0000010c +REG_A6XX_RBBM_CLOCK_CNTL3_UCHE = 0x0000010d +REG_A6XX_RBBM_CLOCK_CNTL4_UCHE = 0x0000010e +REG_A6XX_RBBM_CLOCK_DELAY_UCHE = 0x0000010f +REG_A6XX_RBBM_CLOCK_HYST_UCHE = 0x00000110 +REG_A6XX_RBBM_CLOCK_MODE_VFD = 0x00000111 +REG_A6XX_RBBM_CLOCK_DELAY_VFD = 0x00000112 +REG_A6XX_RBBM_CLOCK_HYST_VFD = 0x00000113 +REG_A6XX_RBBM_CLOCK_MODE_GPC = 0x00000114 +REG_A6XX_RBBM_CLOCK_DELAY_GPC = 0x00000115 +REG_A6XX_RBBM_CLOCK_HYST_GPC = 0x00000116 +REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 = 0x00000117 +REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX = 0x00000118 +REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX = 0x00000119 +REG_A6XX_RBBM_CLOCK_HYST_GMU_GX = 0x0000011a +REG_A6XX_RBBM_CLOCK_MODE_HLSQ = 0x0000011b +REG_A6XX_RBBM_CLOCK_DELAY_HLSQ = 0x0000011c +REG_A6XX_RBBM_CLOCK_HYST_HLSQ = 0x0000011d +REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD = 0x0000011e +REG_A7XX_RBBM_CGC_P2S_TRIG_CMD = 0x0000011f +REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE = 0x00000120 +REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE = 0x00000121 +REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE = 0x00000122 +REG_A7XX_RBBM_CGC_P2S_STATUS = 0x00000122 +A7XX_RBBM_CGC_P2S_STATUS_TXDONE = 0x00000001 +REG_A6XX_RBBM_CLOCK_CNTL_FCHE = 0x00000123 +REG_A6XX_RBBM_CLOCK_DELAY_FCHE = 0x00000124 +REG_A6XX_RBBM_CLOCK_HYST_FCHE = 0x00000125 +REG_A6XX_RBBM_CLOCK_CNTL_MHUB = 0x00000126 +REG_A6XX_RBBM_CLOCK_DELAY_MHUB = 0x00000127 +REG_A6XX_RBBM_CLOCK_HYST_MHUB = 0x00000128 +REG_A6XX_RBBM_CLOCK_DELAY_GLC = 0x00000129 +REG_A6XX_RBBM_CLOCK_HYST_GLC = 0x0000012a +REG_A6XX_RBBM_CLOCK_CNTL_GLC = 0x0000012b +REG_A7XX_RBBM_CLOCK_HYST2_VFD = 0x0000012f +REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL = 0x000005ff +REG_A6XX_DBGC_CFG_DBGBUS_SEL_A = 0x00000600 +REG_A6XX_DBGC_CFG_DBGBUS_SEL_B = 0x00000601 +REG_A6XX_DBGC_CFG_DBGBUS_SEL_C = 0x00000602 +REG_A6XX_DBGC_CFG_DBGBUS_SEL_D = 0x00000603 +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK = 0x000000ff +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK = 0x0000ff00 +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT = 8 +REG_A6XX_DBGC_CFG_DBGBUS_CNTLT = 0x00000604 +A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f +A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 +A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 +A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 +A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 +REG_A6XX_DBGC_CFG_DBGBUS_CNTLM = 0x00000605 +A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 +A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000608 +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000609 +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000060a +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000060b +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000060c +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000060d +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000060e +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000060f +REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000610 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 +REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000611 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 +REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000062f +REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000630 +REG_A6XX_VSC_PERFCTR_VSC_SEL = lambda i0: (0x00000cd8 + 0x1*i0 ) +REG_A7XX_VSC_UNKNOWN_0CD8 = 0x00000cd8 +A7XX_VSC_UNKNOWN_0CD8_BINNING = 0x00000001 +REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE = 0x0000c800 +REG_A6XX_HLSQ_DBG_READ_SEL = 0x0000d000 +REG_A6XX_UCHE_ADDR_MODE_CNTL = 0x00000e00 +REG_A6XX_UCHE_MODE_CNTL = 0x00000e01 +REG_A6XX_UCHE_WRITE_RANGE_MAX = 0x00000e05 +REG_A6XX_UCHE_WRITE_THRU_BASE = 0x00000e07 +REG_A6XX_UCHE_TRAP_BASE = 0x00000e09 +REG_A6XX_UCHE_GMEM_RANGE_MIN = 0x00000e0b +REG_A6XX_UCHE_GMEM_RANGE_MAX = 0x00000e0d +REG_A6XX_UCHE_CACHE_WAYS = 0x00000e17 +REG_A6XX_UCHE_FILTER_CNTL = 0x00000e18 +REG_A6XX_UCHE_CLIENT_PF = 0x00000e19 +A6XX_UCHE_CLIENT_PF_PERFSEL__MASK = 0x000000ff +A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT = 0 +REG_A6XX_UCHE_PERFCTR_UCHE_SEL = lambda i0: (0x00000e1c + 0x1*i0 ) +REG_A6XX_UCHE_GBIF_GX_CONFIG = 0x00000e3a +REG_A6XX_UCHE_CMDQ_CONFIG = 0x00000e3c +REG_A6XX_VBIF_VERSION = 0x00003000 +REG_A6XX_VBIF_CLKON = 0x00003001 +A6XX_VBIF_CLKON_FORCE_ON_TESTBUS = 0x00000002 +REG_A6XX_VBIF_GATE_OFF_WRREQ_EN = 0x0000302a +REG_A6XX_VBIF_XIN_HALT_CTRL0 = 0x00003080 +REG_A6XX_VBIF_XIN_HALT_CTRL1 = 0x00003081 +REG_A6XX_VBIF_TEST_BUS_OUT_CTRL = 0x00003084 +REG_A6XX_VBIF_TEST_BUS1_CTRL0 = 0x00003085 +REG_A6XX_VBIF_TEST_BUS1_CTRL1 = 0x00003086 +A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK = 0x0000000f +A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT = 0 +REG_A6XX_VBIF_TEST_BUS2_CTRL0 = 0x00003087 +REG_A6XX_VBIF_TEST_BUS2_CTRL1 = 0x00003088 +A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK = 0x000001ff +A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT = 0 +REG_A6XX_VBIF_TEST_BUS_OUT = 0x0000308c +REG_A6XX_VBIF_PERF_CNT_SEL0 = 0x000030d0 +REG_A6XX_VBIF_PERF_CNT_SEL1 = 0x000030d1 +REG_A6XX_VBIF_PERF_CNT_SEL2 = 0x000030d2 +REG_A6XX_VBIF_PERF_CNT_SEL3 = 0x000030d3 +REG_A6XX_VBIF_PERF_CNT_LOW0 = 0x000030d8 +REG_A6XX_VBIF_PERF_CNT_LOW1 = 0x000030d9 +REG_A6XX_VBIF_PERF_CNT_LOW2 = 0x000030da +REG_A6XX_VBIF_PERF_CNT_LOW3 = 0x000030db +REG_A6XX_VBIF_PERF_CNT_HIGH0 = 0x000030e0 +REG_A6XX_VBIF_PERF_CNT_HIGH1 = 0x000030e1 +REG_A6XX_VBIF_PERF_CNT_HIGH2 = 0x000030e2 +REG_A6XX_VBIF_PERF_CNT_HIGH3 = 0x000030e3 +REG_A6XX_VBIF_PERF_PWR_CNT_EN0 = 0x00003100 +REG_A6XX_VBIF_PERF_PWR_CNT_EN1 = 0x00003101 +REG_A6XX_VBIF_PERF_PWR_CNT_EN2 = 0x00003102 +REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 = 0x00003110 +REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 = 0x00003111 +REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 = 0x00003112 +REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 = 0x00003118 +REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 = 0x00003119 +REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 = 0x0000311a +REG_A6XX_GBIF_SCACHE_CNTL0 = 0x00003c01 +REG_A6XX_GBIF_SCACHE_CNTL1 = 0x00003c02 +REG_A6XX_GBIF_QSB_SIDE0 = 0x00003c03 +REG_A6XX_GBIF_QSB_SIDE1 = 0x00003c04 +REG_A6XX_GBIF_QSB_SIDE2 = 0x00003c05 +REG_A6XX_GBIF_QSB_SIDE3 = 0x00003c06 +REG_A6XX_GBIF_HALT = 0x00003c45 +REG_A6XX_GBIF_HALT_ACK = 0x00003c46 +REG_A6XX_GBIF_PERF_PWR_CNT_EN = 0x00003cc0 +REG_A6XX_GBIF_PERF_PWR_CNT_CLR = 0x00003cc1 +REG_A6XX_GBIF_PERF_CNT_SEL = 0x00003cc2 +REG_A6XX_GBIF_PERF_PWR_CNT_SEL = 0x00003cc3 +REG_A6XX_GBIF_PERF_CNT_LOW0 = 0x00003cc4 +REG_A6XX_GBIF_PERF_CNT_LOW1 = 0x00003cc5 +REG_A6XX_GBIF_PERF_CNT_LOW2 = 0x00003cc6 +REG_A6XX_GBIF_PERF_CNT_LOW3 = 0x00003cc7 +REG_A6XX_GBIF_PERF_CNT_HIGH0 = 0x00003cc8 +REG_A6XX_GBIF_PERF_CNT_HIGH1 = 0x00003cc9 +REG_A6XX_GBIF_PERF_CNT_HIGH2 = 0x00003cca +REG_A6XX_GBIF_PERF_CNT_HIGH3 = 0x00003ccb +REG_A6XX_GBIF_PWR_CNT_LOW0 = 0x00003ccc +REG_A6XX_GBIF_PWR_CNT_LOW1 = 0x00003ccd +REG_A6XX_GBIF_PWR_CNT_LOW2 = 0x00003cce +REG_A6XX_GBIF_PWR_CNT_HIGH0 = 0x00003ccf +REG_A6XX_GBIF_PWR_CNT_HIGH1 = 0x00003cd0 +REG_A6XX_GBIF_PWR_CNT_HIGH2 = 0x00003cd1 +REG_A6XX_VSC_DBG_ECO_CNTL = 0x00000c00 +REG_A6XX_VSC_BIN_SIZE = 0x00000c02 +A6XX_VSC_BIN_SIZE_WIDTH__MASK = 0x000000ff +A6XX_VSC_BIN_SIZE_WIDTH__SHIFT = 0 +A6XX_VSC_BIN_SIZE_HEIGHT__MASK = 0x0001ff00 +A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT = 8 +REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS = 0x00000c03 +REG_A6XX_VSC_BIN_COUNT = 0x00000c06 +A6XX_VSC_BIN_COUNT_NX__MASK = 0x000007fe +A6XX_VSC_BIN_COUNT_NX__SHIFT = 1 +A6XX_VSC_BIN_COUNT_NY__MASK = 0x001ff800 +A6XX_VSC_BIN_COUNT_NY__SHIFT = 11 +REG_A6XX_VSC_PIPE_CONFIG = lambda i0: (0x00000c10 + 0x1*i0 ) +A6XX_VSC_PIPE_CONFIG_REG_X__MASK = 0x000003ff +A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT = 0 +A6XX_VSC_PIPE_CONFIG_REG_Y__MASK = 0x000ffc00 +A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT = 10 +A6XX_VSC_PIPE_CONFIG_REG_W__MASK = 0x03f00000 +A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT = 20 +A6XX_VSC_PIPE_CONFIG_REG_H__MASK = 0xfc000000 +A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT = 26 +REG_A6XX_VSC_PRIM_STRM_ADDRESS = 0x00000c30 +REG_A6XX_VSC_PRIM_STRM_PITCH = 0x00000c32 +REG_A6XX_VSC_PRIM_STRM_LIMIT = 0x00000c33 +REG_A6XX_VSC_DRAW_STRM_ADDRESS = 0x00000c34 +REG_A6XX_VSC_DRAW_STRM_PITCH = 0x00000c36 +REG_A6XX_VSC_DRAW_STRM_LIMIT = 0x00000c37 +REG_A6XX_VSC_STATE = lambda i0: (0x00000c38 + 0x1*i0 ) +REG_A6XX_VSC_PRIM_STRM_SIZE = lambda i0: (0x00000c58 + 0x1*i0 ) +REG_A6XX_VSC_DRAW_STRM_SIZE = lambda i0: (0x00000c78 + 0x1*i0 ) +REG_A7XX_VSC_UNKNOWN_0D08 = 0x00000d08 +REG_A7XX_UCHE_UNKNOWN_0E10 = 0x00000e10 +REG_A7XX_UCHE_UNKNOWN_0E11 = 0x00000e11 +REG_A6XX_UCHE_UNKNOWN_0E12 = 0x00000e12 +REG_A6XX_GRAS_CL_CNTL = 0x00008000 +A6XX_GRAS_CL_CNTL_CLIP_DISABLE = 0x00000001 +A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE = 0x00000002 +A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE = 0x00000004 +A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE = 0x00000020 +A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z = 0x00000040 +A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE = 0x00000080 +A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE = 0x00000100 +A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE = 0x00000200 +REG_A6XX_GRAS_VS_CL_CNTL = 0x00008001 +A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 +A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT = 8 +REG_A6XX_GRAS_DS_CL_CNTL = 0x00008002 +A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 +A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT = 8 +REG_A6XX_GRAS_GS_CL_CNTL = 0x00008003 +A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 +A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT = 8 +REG_A6XX_GRAS_MAX_LAYER_INDEX = 0x00008004 +REG_A6XX_GRAS_CNTL = 0x00008005 +A6XX_GRAS_CNTL_IJ_PERSP_PIXEL = 0x00000001 +A6XX_GRAS_CNTL_IJ_PERSP_CENTROID = 0x00000002 +A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE = 0x00000004 +A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL = 0x00000008 +A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID = 0x00000010 +A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 +A6XX_GRAS_CNTL_COORD_MASK__MASK = 0x000003c0 +A6XX_GRAS_CNTL_COORD_MASK__SHIFT = 6 +A6XX_GRAS_CNTL_UNK10 = 0x00000400 +A6XX_GRAS_CNTL_UNK11 = 0x00000800 +REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ = 0x00008006 +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK = 0x000001ff +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT = 0 +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK = 0x0007fc00 +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT = 10 +REG_A7XX_GRAS_UNKNOWN_8007 = 0x00008007 +REG_A7XX_GRAS_UNKNOWN_8008 = 0x00008008 +REG_A7XX_GRAS_UNKNOWN_8009 = 0x00008009 +REG_A7XX_GRAS_UNKNOWN_800A = 0x0000800a +REG_A7XX_GRAS_UNKNOWN_800B = 0x0000800b +REG_A7XX_GRAS_UNKNOWN_800C = 0x0000800c +REG_A6XX_GRAS_CL_VPORT = lambda i0: (0x00008010 + 0x6*i0 ) +A6XX_GRAS_CL_VPORT_XOFFSET__MASK = 0xffffffff +A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT = 0 +A6XX_GRAS_CL_VPORT_XSCALE__MASK = 0xffffffff +A6XX_GRAS_CL_VPORT_XSCALE__SHIFT = 0 +A6XX_GRAS_CL_VPORT_YOFFSET__MASK = 0xffffffff +A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT = 0 +A6XX_GRAS_CL_VPORT_YSCALE__MASK = 0xffffffff +A6XX_GRAS_CL_VPORT_YSCALE__SHIFT = 0 +A6XX_GRAS_CL_VPORT_ZOFFSET__MASK = 0xffffffff +A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT = 0 +A6XX_GRAS_CL_VPORT_ZSCALE__MASK = 0xffffffff +A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT = 0 +REG_A6XX_GRAS_CL_Z_CLAMP = lambda i0: (0x00008070 + 0x2*i0 ) +A6XX_GRAS_CL_Z_CLAMP_MIN__MASK = 0xffffffff +A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT = 0 +A6XX_GRAS_CL_Z_CLAMP_MAX__MASK = 0xffffffff +A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT = 0 +REG_A6XX_GRAS_SU_CNTL = 0x00008090 +A6XX_GRAS_SU_CNTL_CULL_FRONT = 0x00000001 +A6XX_GRAS_SU_CNTL_CULL_BACK = 0x00000002 +A6XX_GRAS_SU_CNTL_FRONT_CW = 0x00000004 +A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK = 0x000007f8 +A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT = 3 +A6XX_GRAS_SU_CNTL_POLY_OFFSET = 0x00000800 +A6XX_GRAS_SU_CNTL_UNK12 = 0x00001000 +A6XX_GRAS_SU_CNTL_LINE_MODE__MASK = 0x00002000 +A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT = 13 +A6XX_GRAS_SU_CNTL_UNK15__MASK = 0x00018000 +A6XX_GRAS_SU_CNTL_UNK15__SHIFT = 15 +A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE = 0x00020000 +A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR = 0x00040000 +A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR = 0x00080000 +A6XX_GRAS_SU_CNTL_UNK20__MASK = 0x00700000 +A6XX_GRAS_SU_CNTL_UNK20__SHIFT = 20 +REG_A6XX_GRAS_SU_POINT_MINMAX = 0x00008091 +A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK = 0x0000ffff +A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT = 0 +A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK = 0xffff0000 +A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT = 16 +REG_A6XX_GRAS_SU_POINT_SIZE = 0x00008092 +A6XX_GRAS_SU_POINT_SIZE__MASK = 0x0000ffff +A6XX_GRAS_SU_POINT_SIZE__SHIFT = 0 +REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL = 0x00008094 +A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 +A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 +REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE = 0x00008095 +A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK = 0xffffffff +A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT = 0 +REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET = 0x00008096 +A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK = 0xffffffff +A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT = 0 +REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP = 0x00008097 +A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK = 0xffffffff +A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT = 0 +REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO = 0x00008098 +A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 +REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL = 0x00008099 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK = 0x00000006 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT = 1 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN = 0x00000008 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK = 0x00000030 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT = 4 +REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL = 0x0000809a +A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 = 0x00000001 +A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN = 0x00000002 +REG_A6XX_GRAS_VS_LAYER_CNTL = 0x0000809b +A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER = 0x00000001 +A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW = 0x00000002 +REG_A6XX_GRAS_GS_LAYER_CNTL = 0x0000809c +A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER = 0x00000001 +A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW = 0x00000002 +REG_A6XX_GRAS_DS_LAYER_CNTL = 0x0000809d +A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER = 0x00000001 +A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW = 0x00000002 +REG_A6XX_GRAS_SC_CNTL = 0x000080a0 +A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000007 +A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 0 +A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK = 0x00000018 +A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT = 3 +A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK = 0x00000020 +A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT = 5 +A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK = 0x000000c0 +A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT = 6 +A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK = 0x00000100 +A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT = 8 +A6XX_GRAS_SC_CNTL_UNK9 = 0x00000200 +A6XX_GRAS_SC_CNTL_ROTATION__MASK = 0x00000c00 +A6XX_GRAS_SC_CNTL_ROTATION__SHIFT = 10 +A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN = 0x00001000 +REG_A6XX_GRAS_BIN_CONTROL = 0x000080a1 +A6XX_GRAS_BIN_CONTROL_BINW__MASK = 0x0000003f +A6XX_GRAS_BIN_CONTROL_BINW__SHIFT = 0 +A6XX_GRAS_BIN_CONTROL_BINH__MASK = 0x00007f00 +A6XX_GRAS_BIN_CONTROL_BINH__SHIFT = 8 +A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 +A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT = 18 +A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 +A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 +A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 +A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 +A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 +A6XX_GRAS_BIN_CONTROL_UNK27 = 0x08000000 +REG_A6XX_GRAS_RAS_MSAA_CNTL = 0x000080a2 +A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_GRAS_RAS_MSAA_CNTL_UNK2 = 0x00000004 +A6XX_GRAS_RAS_MSAA_CNTL_UNK3 = 0x00000008 +REG_A6XX_GRAS_DEST_MSAA_CNTL = 0x000080a3 +A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 +REG_A6XX_GRAS_SAMPLE_CONFIG = 0x000080a4 +A6XX_GRAS_SAMPLE_CONFIG_UNK0 = 0x00000001 +A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 +REG_A6XX_GRAS_SAMPLE_LOCATION_0 = 0x000080a5 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_GRAS_SAMPLE_LOCATION_1 = 0x000080a6 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 +REG_A7XX_GRAS_UNKNOWN_80A7 = 0x000080a7 +REG_A6XX_GRAS_UNKNOWN_80AF = 0x000080af +REG_A6XX_GRAS_SC_SCREEN_SCISSOR = lambda i0: (0x000080b0 + 0x2*i0 ) +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK = 0x0000ffff +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT = 16 +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK = 0x0000ffff +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR = lambda i0: (0x000080d0 + 0x2*i0 ) +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK = 0x0000ffff +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT = 16 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK = 0x0000ffff +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL = 0x000080f0 +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK = 0x00003fff +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK = 0x3fff0000 +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT = 16 +REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR = 0x000080f1 +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK = 0x00003fff +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK = 0x3fff0000 +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT = 16 +REG_A7XX_GRAS_UNKNOWN_80F4 = 0x000080f4 +REG_A7XX_GRAS_UNKNOWN_80F5 = 0x000080f5 +REG_A7XX_GRAS_UNKNOWN_80F6 = 0x000080f6 +REG_A7XX_GRAS_UNKNOWN_80F8 = 0x000080f8 +REG_A7XX_GRAS_UNKNOWN_80F9 = 0x000080f9 +REG_A7XX_GRAS_UNKNOWN_80FA = 0x000080fa +REG_A6XX_GRAS_LRZ_CNTL = 0x00008100 +A6XX_GRAS_LRZ_CNTL_ENABLE = 0x00000001 +A6XX_GRAS_LRZ_CNTL_LRZ_WRITE = 0x00000002 +A6XX_GRAS_LRZ_CNTL_GREATER = 0x00000004 +A6XX_GRAS_LRZ_CNTL_FC_ENABLE = 0x00000008 +A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE = 0x00000010 +A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE = 0x00000020 +A6XX_GRAS_LRZ_CNTL_DIR__MASK = 0x000000c0 +A6XX_GRAS_LRZ_CNTL_DIR__SHIFT = 6 +A6XX_GRAS_LRZ_CNTL_DIR_WRITE = 0x00000100 +A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR = 0x00000200 +A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK = 0x00003800 +A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT = 11 +REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL = 0x00008101 +A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID = 0x00000001 +A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000006 +A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 1 +REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 = 0x00008102 +A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK = 0x000000ff +A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT = 0 +REG_A6XX_GRAS_LRZ_BUFFER_BASE = 0x00008103 +REG_A6XX_GRAS_LRZ_BUFFER_PITCH = 0x00008105 +A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK = 0x000000ff +A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 +A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 +REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE = 0x00008106 +REG_A6XX_GRAS_SAMPLE_CNTL = 0x00008109 +A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 +REG_A6XX_GRAS_LRZ_DEPTH_VIEW = 0x0000810a +A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK = 0x000007ff +A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT = 0 +A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK = 0x07ff0000 +A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT = 16 +A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK = 0xf0000000 +A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT = 28 +REG_A7XX_GRAS_LRZ_CNTL2 = 0x0000810b +A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR = 0x00000001 +A7XX_GRAS_LRZ_CNTL2_FC_ENABLE = 0x00000002 +REG_A6XX_GRAS_UNKNOWN_8110 = 0x00008110 +REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 = 0x00008111 +A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK = 0xffffffff +A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT = 0 +REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO = 0x00008113 +A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 +REG_A7XX_GRAS_UNKNOWN_8120 = 0x00008120 +REG_A7XX_GRAS_UNKNOWN_8121 = 0x00008121 +REG_A6XX_GRAS_2D_BLIT_CNTL = 0x00008400 +A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 +A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT = 0 +A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 +A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 +A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT = 4 +A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 +A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 +A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 +A6XX_GRAS_2D_BLIT_CNTL_SCISSOR = 0x00010000 +A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 +A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT = 17 +A6XX_GRAS_2D_BLIT_CNTL_D24S8 = 0x00080000 +A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 +A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT = 20 +A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 +A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT = 24 +A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 +A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 +A6XX_GRAS_2D_BLIT_CNTL_UNK30 = 0x40000000 +REG_A6XX_GRAS_2D_SRC_TL_X = 0x00008401 +A6XX_GRAS_2D_SRC_TL_X__MASK = 0x01ffff00 +A6XX_GRAS_2D_SRC_TL_X__SHIFT = 8 +REG_A6XX_GRAS_2D_SRC_BR_X = 0x00008402 +A6XX_GRAS_2D_SRC_BR_X__MASK = 0x01ffff00 +A6XX_GRAS_2D_SRC_BR_X__SHIFT = 8 +REG_A6XX_GRAS_2D_SRC_TL_Y = 0x00008403 +A6XX_GRAS_2D_SRC_TL_Y__MASK = 0x01ffff00 +A6XX_GRAS_2D_SRC_TL_Y__SHIFT = 8 +REG_A6XX_GRAS_2D_SRC_BR_Y = 0x00008404 +A6XX_GRAS_2D_SRC_BR_Y__MASK = 0x01ffff00 +A6XX_GRAS_2D_SRC_BR_Y__SHIFT = 8 +REG_A6XX_GRAS_2D_DST_TL = 0x00008405 +A6XX_GRAS_2D_DST_TL_X__MASK = 0x00003fff +A6XX_GRAS_2D_DST_TL_X__SHIFT = 0 +A6XX_GRAS_2D_DST_TL_Y__MASK = 0x3fff0000 +A6XX_GRAS_2D_DST_TL_Y__SHIFT = 16 +REG_A6XX_GRAS_2D_DST_BR = 0x00008406 +A6XX_GRAS_2D_DST_BR_X__MASK = 0x00003fff +A6XX_GRAS_2D_DST_BR_X__SHIFT = 0 +A6XX_GRAS_2D_DST_BR_Y__MASK = 0x3fff0000 +A6XX_GRAS_2D_DST_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_2D_UNKNOWN_8407 = 0x00008407 +REG_A6XX_GRAS_2D_UNKNOWN_8408 = 0x00008408 +REG_A6XX_GRAS_2D_UNKNOWN_8409 = 0x00008409 +REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 = 0x0000840a +A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK = 0x00003fff +A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT = 0 +A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK = 0x3fff0000 +A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT = 16 +REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 = 0x0000840b +A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK = 0x00003fff +A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT = 0 +A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK = 0x3fff0000 +A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT = 16 +REG_A6XX_GRAS_DBG_ECO_CNTL = 0x00008600 +A6XX_GRAS_DBG_ECO_CNTL_UNK7 = 0x00000080 +A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS = 0x00000800 +REG_A6XX_GRAS_ADDR_MODE_CNTL = 0x00008601 +REG_A7XX_GRAS_NC_MODE_CNTL = 0x00008602 +REG_A6XX_GRAS_PERFCTR_TSE_SEL = lambda i0: (0x00008610 + 0x1*i0 ) +REG_A6XX_GRAS_PERFCTR_RAS_SEL = lambda i0: (0x00008614 + 0x1*i0 ) +REG_A6XX_GRAS_PERFCTR_LRZ_SEL = lambda i0: (0x00008618 + 0x1*i0 ) +REG_A6XX_RB_BIN_CONTROL = 0x00008800 +A6XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f +A6XX_RB_BIN_CONTROL_BINW__SHIFT = 0 +A6XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 +A6XX_RB_BIN_CONTROL_BINH__SHIFT = 8 +A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 +A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 +A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 +A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 +A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 +A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 +A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 +REG_A7XX_RB_BIN_CONTROL = 0x00008800 +A7XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f +A7XX_RB_BIN_CONTROL_BINW__SHIFT = 0 +A7XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 +A7XX_RB_BIN_CONTROL_BINH__SHIFT = 8 +A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 +A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 +A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 +A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 +A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 +REG_A6XX_RB_RENDER_CNTL = 0x00008801 +A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000038 +A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 3 +A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 +A6XX_RB_RENDER_CNTL_BINNING = 0x00000080 +A6XX_RB_RENDER_CNTL_UNK8__MASK = 0x00000700 +A6XX_RB_RENDER_CNTL_UNK8__SHIFT = 8 +A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 +A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 +A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 +A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 +A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 +A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 +A6XX_RB_RENDER_CNTL_FLAG_DEPTH = 0x00004000 +A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK = 0x00ff0000 +A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT = 16 +REG_A7XX_RB_RENDER_CNTL = 0x00008801 +A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 +A7XX_RB_RENDER_CNTL_BINNING = 0x00000080 +A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 +A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 +A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 +A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 +A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 +A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 +REG_A7XX_GRAS_SU_RENDER_CNTL = 0x00008116 +A7XX_GRAS_SU_RENDER_CNTL_BINNING = 0x00000080 +REG_A6XX_RB_RAS_MSAA_CNTL = 0x00008802 +A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_RB_RAS_MSAA_CNTL_UNK2 = 0x00000004 +A6XX_RB_RAS_MSAA_CNTL_UNK3 = 0x00000008 +REG_A6XX_RB_DEST_MSAA_CNTL = 0x00008803 +A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 +REG_A6XX_RB_SAMPLE_CONFIG = 0x00008804 +A6XX_RB_SAMPLE_CONFIG_UNK0 = 0x00000001 +A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 +REG_A6XX_RB_SAMPLE_LOCATION_0 = 0x00008805 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_RB_SAMPLE_LOCATION_1 = 0x00008806 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_RB_RENDER_CONTROL0 = 0x00008809 +A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL = 0x00000001 +A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID = 0x00000002 +A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE = 0x00000004 +A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL = 0x00000008 +A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID = 0x00000010 +A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE = 0x00000020 +A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK = 0x000003c0 +A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT = 6 +A6XX_RB_RENDER_CONTROL0_UNK10 = 0x00000400 +REG_A6XX_RB_RENDER_CONTROL1 = 0x0000880a +A6XX_RB_RENDER_CONTROL1_SAMPLEMASK = 0x00000001 +A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE = 0x00000002 +A6XX_RB_RENDER_CONTROL1_FACENESS = 0x00000004 +A6XX_RB_RENDER_CONTROL1_SAMPLEID = 0x00000008 +A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK = 0x00000030 +A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT = 4 +A6XX_RB_RENDER_CONTROL1_CENTERRHW = 0x00000040 +A6XX_RB_RENDER_CONTROL1_LINELENGTHEN = 0x00000080 +A6XX_RB_RENDER_CONTROL1_FOVEATION = 0x00000100 +REG_A6XX_RB_FS_OUTPUT_CNTL0 = 0x0000880b +A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 +A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z = 0x00000002 +A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK = 0x00000004 +A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF = 0x00000008 +REG_A6XX_RB_FS_OUTPUT_CNTL1 = 0x0000880c +A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f +A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 +REG_A6XX_RB_RENDER_COMPONENTS = 0x0000880d +A6XX_RB_RENDER_COMPONENTS_RT0__MASK = 0x0000000f +A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT = 0 +A6XX_RB_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 +A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT = 4 +A6XX_RB_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 +A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT = 8 +A6XX_RB_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 +A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT = 12 +A6XX_RB_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 +A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT = 16 +A6XX_RB_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 +A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT = 20 +A6XX_RB_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 +A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT = 24 +A6XX_RB_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 +A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT = 28 +REG_A6XX_RB_DITHER_CNTL = 0x0000880e +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 +REG_A6XX_RB_SRGB_CNTL = 0x0000880f +A6XX_RB_SRGB_CNTL_SRGB_MRT0 = 0x00000001 +A6XX_RB_SRGB_CNTL_SRGB_MRT1 = 0x00000002 +A6XX_RB_SRGB_CNTL_SRGB_MRT2 = 0x00000004 +A6XX_RB_SRGB_CNTL_SRGB_MRT3 = 0x00000008 +A6XX_RB_SRGB_CNTL_SRGB_MRT4 = 0x00000010 +A6XX_RB_SRGB_CNTL_SRGB_MRT5 = 0x00000020 +A6XX_RB_SRGB_CNTL_SRGB_MRT6 = 0x00000040 +A6XX_RB_SRGB_CNTL_SRGB_MRT7 = 0x00000080 +REG_A6XX_RB_SAMPLE_CNTL = 0x00008810 +A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 +REG_A6XX_RB_UNKNOWN_8811 = 0x00008811 +REG_A7XX_RB_UNKNOWN_8812 = 0x00008812 +REG_A6XX_RB_UNKNOWN_8818 = 0x00008818 +REG_A6XX_RB_UNKNOWN_8819 = 0x00008819 +REG_A6XX_RB_UNKNOWN_881A = 0x0000881a +REG_A6XX_RB_UNKNOWN_881B = 0x0000881b +REG_A6XX_RB_UNKNOWN_881C = 0x0000881c +REG_A6XX_RB_UNKNOWN_881D = 0x0000881d +REG_A6XX_RB_UNKNOWN_881E = 0x0000881e +REG_A6XX_RB_MRT = lambda i0: (0x00008820 + 0x8*i0 ) +A6XX_RB_MRT_CONTROL_BLEND = 0x00000001 +A6XX_RB_MRT_CONTROL_BLEND2 = 0x00000002 +A6XX_RB_MRT_CONTROL_ROP_ENABLE = 0x00000004 +A6XX_RB_MRT_CONTROL_ROP_CODE__MASK = 0x00000078 +A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT = 3 +A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK = 0x00000780 +A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT = 7 +A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK = 0x0000001f +A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT = 0 +A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK = 0x000000e0 +A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT = 5 +A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK = 0x00001f00 +A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT = 8 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK = 0x001f0000 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT = 16 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK = 0x00e00000 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT = 21 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK = 0x1f000000 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT = 24 +A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff +A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 +A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 +A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 +A6XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 +A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 +A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 +A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff +A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 +A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 +A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 +A7XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 +A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN = 0x00000800 +A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 +A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 +A6XX_RB_MRT_PITCH__MASK = 0xffffffff +A6XX_RB_MRT_PITCH__SHIFT = 0 +A6XX_RB_MRT_ARRAY_PITCH__MASK = 0xffffffff +A6XX_RB_MRT_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_BLEND_RED_F32 = 0x00008860 +A6XX_RB_BLEND_RED_F32__MASK = 0xffffffff +A6XX_RB_BLEND_RED_F32__SHIFT = 0 +REG_A6XX_RB_BLEND_GREEN_F32 = 0x00008861 +A6XX_RB_BLEND_GREEN_F32__MASK = 0xffffffff +A6XX_RB_BLEND_GREEN_F32__SHIFT = 0 +REG_A6XX_RB_BLEND_BLUE_F32 = 0x00008862 +A6XX_RB_BLEND_BLUE_F32__MASK = 0xffffffff +A6XX_RB_BLEND_BLUE_F32__SHIFT = 0 +REG_A6XX_RB_BLEND_ALPHA_F32 = 0x00008863 +A6XX_RB_BLEND_ALPHA_F32__MASK = 0xffffffff +A6XX_RB_BLEND_ALPHA_F32__SHIFT = 0 +REG_A6XX_RB_ALPHA_CONTROL = 0x00008864 +A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK = 0x000000ff +A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT = 0 +A6XX_RB_ALPHA_CONTROL_ALPHA_TEST = 0x00000100 +A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK = 0x00000e00 +A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT = 9 +REG_A6XX_RB_BLEND_CNTL = 0x00008865 +A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff +A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 +A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND = 0x00000100 +A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 +A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 +A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE = 0x00000800 +A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK = 0xffff0000 +A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT = 16 +REG_A6XX_RB_DEPTH_PLANE_CNTL = 0x00008870 +A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 +A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 +REG_A6XX_RB_DEPTH_CNTL = 0x00008871 +A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 +A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE = 0x00000002 +A6XX_RB_DEPTH_CNTL_ZFUNC__MASK = 0x0000001c +A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT = 2 +A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE = 0x00000020 +A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE = 0x00000040 +A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE = 0x00000080 +REG_A6XX_GRAS_SU_DEPTH_CNTL = 0x00008114 +A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 +REG_A6XX_RB_DEPTH_BUFFER_INFO = 0x00008872 +A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 +A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 +REG_A7XX_RB_DEPTH_BUFFER_INFO = 0x00008872 +A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 +A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 +A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK = 0x00000060 +A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT = 5 +A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN = 0x00000080 +REG_A6XX_RB_DEPTH_BUFFER_PITCH = 0x00008873 +A6XX_RB_DEPTH_BUFFER_PITCH__MASK = 0x00003fff +A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH = 0x00008874 +A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK = 0x0fffffff +A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_DEPTH_BUFFER_BASE = 0x00008875 +REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM = 0x00008877 +REG_A6XX_RB_Z_BOUNDS_MIN = 0x00008878 +A6XX_RB_Z_BOUNDS_MIN__MASK = 0xffffffff +A6XX_RB_Z_BOUNDS_MIN__SHIFT = 0 +REG_A6XX_RB_Z_BOUNDS_MAX = 0x00008879 +A6XX_RB_Z_BOUNDS_MAX__MASK = 0xffffffff +A6XX_RB_Z_BOUNDS_MAX__SHIFT = 0 +REG_A6XX_RB_STENCIL_CONTROL = 0x00008880 +A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE = 0x00000001 +A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF = 0x00000002 +A6XX_RB_STENCIL_CONTROL_STENCIL_READ = 0x00000004 +A6XX_RB_STENCIL_CONTROL_FUNC__MASK = 0x00000700 +A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT = 8 +A6XX_RB_STENCIL_CONTROL_FAIL__MASK = 0x00003800 +A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT = 11 +A6XX_RB_STENCIL_CONTROL_ZPASS__MASK = 0x0001c000 +A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT = 14 +A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK = 0x000e0000 +A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT = 17 +A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK = 0x00700000 +A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT = 20 +A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK = 0x03800000 +A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT = 23 +A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK = 0x1c000000 +A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT = 26 +A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK = 0xe0000000 +A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT = 29 +REG_A6XX_GRAS_SU_STENCIL_CNTL = 0x00008115 +A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 +REG_A6XX_RB_STENCIL_INFO = 0x00008881 +A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 +A6XX_RB_STENCIL_INFO_UNK1 = 0x00000002 +REG_A7XX_RB_STENCIL_INFO = 0x00008881 +A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 +A7XX_RB_STENCIL_INFO_UNK1 = 0x00000002 +A7XX_RB_STENCIL_INFO_TILEMODE__MASK = 0x0000000c +A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT = 2 +REG_A6XX_RB_STENCIL_BUFFER_PITCH = 0x00008882 +A6XX_RB_STENCIL_BUFFER_PITCH__MASK = 0x00000fff +A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH = 0x00008883 +A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK = 0x00ffffff +A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_STENCIL_BUFFER_BASE = 0x00008884 +REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM = 0x00008886 +REG_A6XX_RB_STENCILREF = 0x00008887 +A6XX_RB_STENCILREF_REF__MASK = 0x000000ff +A6XX_RB_STENCILREF_REF__SHIFT = 0 +A6XX_RB_STENCILREF_BFREF__MASK = 0x0000ff00 +A6XX_RB_STENCILREF_BFREF__SHIFT = 8 +REG_A6XX_RB_STENCILMASK = 0x00008888 +A6XX_RB_STENCILMASK_MASK__MASK = 0x000000ff +A6XX_RB_STENCILMASK_MASK__SHIFT = 0 +A6XX_RB_STENCILMASK_BFMASK__MASK = 0x0000ff00 +A6XX_RB_STENCILMASK_BFMASK__SHIFT = 8 +REG_A6XX_RB_STENCILWRMASK = 0x00008889 +A6XX_RB_STENCILWRMASK_WRMASK__MASK = 0x000000ff +A6XX_RB_STENCILWRMASK_WRMASK__SHIFT = 0 +A6XX_RB_STENCILWRMASK_BFWRMASK__MASK = 0x0000ff00 +A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT = 8 +REG_A6XX_RB_WINDOW_OFFSET = 0x00008890 +A6XX_RB_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_RB_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_RB_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_RB_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_RB_SAMPLE_COUNT_CONTROL = 0x00008891 +A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE = 0x00000001 +A6XX_RB_SAMPLE_COUNT_CONTROL_COPY = 0x00000002 +REG_A6XX_RB_LRZ_CNTL = 0x00008898 +A6XX_RB_LRZ_CNTL_ENABLE = 0x00000001 +REG_A7XX_RB_UNKNOWN_8899 = 0x00008899 +REG_A6XX_RB_Z_CLAMP_MIN = 0x000088c0 +A6XX_RB_Z_CLAMP_MIN__MASK = 0xffffffff +A6XX_RB_Z_CLAMP_MIN__SHIFT = 0 +REG_A6XX_RB_Z_CLAMP_MAX = 0x000088c1 +A6XX_RB_Z_CLAMP_MAX__MASK = 0xffffffff +A6XX_RB_Z_CLAMP_MAX__SHIFT = 0 +REG_A6XX_RB_UNKNOWN_88D0 = 0x000088d0 +A6XX_RB_UNKNOWN_88D0_UNK0__MASK = 0x00001fff +A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT = 0 +A6XX_RB_UNKNOWN_88D0_UNK16__MASK = 0x07ff0000 +A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT = 16 +REG_A6XX_RB_BLIT_SCISSOR_TL = 0x000088d1 +A6XX_RB_BLIT_SCISSOR_TL_X__MASK = 0x00003fff +A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT = 0 +A6XX_RB_BLIT_SCISSOR_TL_Y__MASK = 0x3fff0000 +A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT = 16 +REG_A6XX_RB_BLIT_SCISSOR_BR = 0x000088d2 +A6XX_RB_BLIT_SCISSOR_BR_X__MASK = 0x00003fff +A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT = 0 +A6XX_RB_BLIT_SCISSOR_BR_Y__MASK = 0x3fff0000 +A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT = 16 +REG_A6XX_RB_BIN_CONTROL2 = 0x000088d3 +A6XX_RB_BIN_CONTROL2_BINW__MASK = 0x0000003f +A6XX_RB_BIN_CONTROL2_BINW__SHIFT = 0 +A6XX_RB_BIN_CONTROL2_BINH__MASK = 0x00007f00 +A6XX_RB_BIN_CONTROL2_BINH__SHIFT = 8 +REG_A6XX_RB_WINDOW_OFFSET2 = 0x000088d4 +A6XX_RB_WINDOW_OFFSET2_X__MASK = 0x00003fff +A6XX_RB_WINDOW_OFFSET2_X__SHIFT = 0 +A6XX_RB_WINDOW_OFFSET2_Y__MASK = 0x3fff0000 +A6XX_RB_WINDOW_OFFSET2_Y__SHIFT = 16 +REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL = 0x000088d5 +A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK = 0x00000018 +A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT = 3 +REG_A6XX_RB_BLIT_BASE_GMEM = 0x000088d6 +REG_A6XX_RB_BLIT_DST_INFO = 0x000088d7 +A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK = 0x00000003 +A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT = 0 +A6XX_RB_BLIT_DST_INFO_FLAGS = 0x00000004 +A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK = 0x00000018 +A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT = 3 +A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK = 0x00000060 +A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT = 5 +A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK = 0x00007f80 +A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT = 7 +A6XX_RB_BLIT_DST_INFO_UNK15 = 0x00008000 +REG_A6XX_RB_BLIT_DST = 0x000088d8 +REG_A6XX_RB_BLIT_DST_PITCH = 0x000088da +A6XX_RB_BLIT_DST_PITCH__MASK = 0x0000ffff +A6XX_RB_BLIT_DST_PITCH__SHIFT = 0 +REG_A6XX_RB_BLIT_DST_ARRAY_PITCH = 0x000088db +A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK = 0x1fffffff +A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_BLIT_FLAG_DST = 0x000088dc +REG_A6XX_RB_BLIT_FLAG_DST_PITCH = 0x000088de +A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK = 0x000007ff +A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT = 0 +A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 +A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 = 0x000088df +REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 = 0x000088e0 +REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 = 0x000088e1 +REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 = 0x000088e2 +REG_A6XX_RB_BLIT_INFO = 0x000088e3 +A6XX_RB_BLIT_INFO_UNK0 = 0x00000001 +A6XX_RB_BLIT_INFO_GMEM = 0x00000002 +A6XX_RB_BLIT_INFO_SAMPLE_0 = 0x00000004 +A6XX_RB_BLIT_INFO_DEPTH = 0x00000008 +A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK = 0x000000f0 +A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT = 4 +A6XX_RB_BLIT_INFO_LAST__MASK = 0x00000300 +A6XX_RB_BLIT_INFO_LAST__SHIFT = 8 +A6XX_RB_BLIT_INFO_BUFFER_ID__MASK = 0x0000f000 +A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT = 12 +REG_A7XX_RB_UNKNOWN_88E4 = 0x000088e4 +A7XX_RB_UNKNOWN_88E4_UNK0 = 0x00000001 +REG_A7XX_RB_CCU_CNTL2 = 0x000088e5 +A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK = 0x00000001 +A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT = 0 +A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK = 0x00000004 +A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT = 2 +A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK = 0x00000c00 +A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT = 10 +A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK = 0x001ff000 +A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT = 12 +A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK = 0x00600000 +A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT = 21 +A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK = 0xff800000 +A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT = 23 +REG_A6XX_RB_UNKNOWN_88F0 = 0x000088f0 +REG_A6XX_RB_UNK_FLAG_BUFFER_BASE = 0x000088f1 +REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH = 0x000088f3 +A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff +A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x00fff800 +A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_UNKNOWN_88F4 = 0x000088f4 +REG_A7XX_RB_UNKNOWN_88F5 = 0x000088f5 +REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE = 0x00008900 +REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH = 0x00008902 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK = 0x0000007f +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK = 0x00000700 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT = 8 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_MRT_FLAG_BUFFER = lambda i0: (0x00008903 + 0x3*i0 ) +A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff +A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffff800 +A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_SAMPLE_COUNT_ADDR = 0x00008927 +REG_A6XX_RB_UNKNOWN_8A00 = 0x00008a00 +REG_A6XX_RB_UNKNOWN_8A10 = 0x00008a10 +REG_A6XX_RB_UNKNOWN_8A20 = 0x00008a20 +REG_A6XX_RB_UNKNOWN_8A30 = 0x00008a30 +REG_A6XX_RB_2D_BLIT_CNTL = 0x00008c00 +A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 +A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT = 0 +A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 +A6XX_RB_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 +A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT = 4 +A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 +A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 +A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 +A6XX_RB_2D_BLIT_CNTL_SCISSOR = 0x00010000 +A6XX_RB_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 +A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT = 17 +A6XX_RB_2D_BLIT_CNTL_D24S8 = 0x00080000 +A6XX_RB_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 +A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT = 20 +A6XX_RB_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 +A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT = 24 +A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 +A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 +A6XX_RB_2D_BLIT_CNTL_UNK30 = 0x40000000 +REG_A6XX_RB_2D_UNKNOWN_8C01 = 0x00008c01 +REG_A6XX_RB_2D_DST_INFO = 0x00008c17 +A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK = 0x000000ff +A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT = 0 +A6XX_RB_2D_DST_INFO_TILE_MODE__MASK = 0x00000300 +A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT = 8 +A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK = 0x00000c00 +A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT = 10 +A6XX_RB_2D_DST_INFO_FLAGS = 0x00001000 +A6XX_RB_2D_DST_INFO_SRGB = 0x00002000 +A6XX_RB_2D_DST_INFO_SAMPLES__MASK = 0x0000c000 +A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT = 14 +A6XX_RB_2D_DST_INFO_FILTER = 0x00010000 +A6XX_RB_2D_DST_INFO_UNK17 = 0x00020000 +A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE = 0x00040000 +A6XX_RB_2D_DST_INFO_UNK19 = 0x00080000 +A6XX_RB_2D_DST_INFO_UNK20 = 0x00100000 +A6XX_RB_2D_DST_INFO_UNK21 = 0x00200000 +A6XX_RB_2D_DST_INFO_UNK22 = 0x00400000 +A6XX_RB_2D_DST_INFO_UNK23__MASK = 0x07800000 +A6XX_RB_2D_DST_INFO_UNK23__SHIFT = 23 +A6XX_RB_2D_DST_INFO_UNK28 = 0x10000000 +REG_A6XX_RB_2D_DST = 0x00008c18 +REG_A6XX_RB_2D_DST_PITCH = 0x00008c1a +A6XX_RB_2D_DST_PITCH__MASK = 0x0000ffff +A6XX_RB_2D_DST_PITCH__SHIFT = 0 +REG_A6XX_RB_2D_DST_PLANE1 = 0x00008c1b +REG_A6XX_RB_2D_DST_PLANE_PITCH = 0x00008c1d +A6XX_RB_2D_DST_PLANE_PITCH__MASK = 0x0000ffff +A6XX_RB_2D_DST_PLANE_PITCH__SHIFT = 0 +REG_A6XX_RB_2D_DST_PLANE2 = 0x00008c1e +REG_A6XX_RB_2D_DST_FLAGS = 0x00008c20 +REG_A6XX_RB_2D_DST_FLAGS_PITCH = 0x00008c22 +A6XX_RB_2D_DST_FLAGS_PITCH__MASK = 0x000000ff +A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT = 0 +REG_A6XX_RB_2D_DST_FLAGS_PLANE = 0x00008c23 +REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH = 0x00008c25 +A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK = 0x000000ff +A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT = 0 +REG_A6XX_RB_2D_SRC_SOLID_C0 = 0x00008c2c +REG_A6XX_RB_2D_SRC_SOLID_C1 = 0x00008c2d +REG_A6XX_RB_2D_SRC_SOLID_C2 = 0x00008c2e +REG_A6XX_RB_2D_SRC_SOLID_C3 = 0x00008c2f +REG_A7XX_RB_UNKNOWN_8C34 = 0x00008c34 +REG_A6XX_RB_UNKNOWN_8E01 = 0x00008e01 +REG_A6XX_RB_DBG_ECO_CNTL = 0x00008e04 +REG_A6XX_RB_ADDR_MODE_CNTL = 0x00008e05 +REG_A7XX_RB_UNKNOWN_8E06 = 0x00008e06 +REG_A6XX_RB_CCU_CNTL = 0x00008e07 +A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 +A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000080 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT = 7 +A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK = 0x00000200 +A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT = 9 +A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 +A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT = 12 +A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 +A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 +A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK = 0xff800000 +A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT = 23 +REG_A7XX_RB_CCU_CNTL = 0x00008e07 +A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 +A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 +REG_A6XX_RB_NC_MODE_CNTL = 0x00008e08 +A6XX_RB_NC_MODE_CNTL_MODE = 0x00000001 +A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 +A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 +A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 +A6XX_RB_NC_MODE_CNTL_AMSBC = 0x00000010 +A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000400 +A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT = 10 +A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR = 0x00000800 +A6XX_RB_NC_MODE_CNTL_UNK12__MASK = 0x00003000 +A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT = 12 +REG_A7XX_RB_UNKNOWN_8E09 = 0x00008e09 +REG_A6XX_RB_PERFCTR_RB_SEL = lambda i0: (0x00008e10 + 0x1*i0 ) +REG_A6XX_RB_PERFCTR_CCU_SEL = lambda i0: (0x00008e18 + 0x1*i0 ) +REG_A6XX_RB_CMP_DBG_ECO_CNTL = 0x00008e28 +REG_A6XX_RB_PERFCTR_CMP_SEL = lambda i0: (0x00008e2c + 0x1*i0 ) +REG_A7XX_RB_PERFCTR_UFC_SEL = lambda i0: (0x00008e30 + 0x1*i0 ) +REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST = 0x00008e3b +REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD = 0x00008e3d +REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE = 0x00008e50 +REG_A6XX_RB_UNKNOWN_8E51 = 0x00008e51 +REG_A7XX_RB_UNKNOWN_8E79 = 0x00008e79 +REG_A6XX_VPC_GS_PARAM = 0x00009100 +A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK = 0x000000ff +A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT = 0 +REG_A6XX_VPC_VS_CLIP_CNTL = 0x00009101 +A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_GS_CLIP_CNTL = 0x00009102 +A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_DS_CLIP_CNTL = 0x00009103 +A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_VS_CLIP_CNTL_V2 = 0x00009311 +A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 +A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_GS_CLIP_CNTL_V2 = 0x00009312 +A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 +A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_DS_CLIP_CNTL_V2 = 0x00009313 +A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 +A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_VS_LAYER_CNTL = 0x00009104 +A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT = 0 +A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT = 8 +A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_GS_LAYER_CNTL = 0x00009105 +A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT = 0 +A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT = 8 +A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_DS_LAYER_CNTL = 0x00009106 +A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT = 0 +A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT = 8 +A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_VS_LAYER_CNTL_V2 = 0x00009314 +A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 +A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 +A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_GS_LAYER_CNTL_V2 = 0x00009315 +A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 +A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 +A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_DS_LAYER_CNTL_V2 = 0x00009316 +A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 +A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 +A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_UNKNOWN_9107 = 0x00009107 +A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD = 0x00000001 +A6XX_VPC_UNKNOWN_9107_UNK2 = 0x00000004 +REG_A6XX_VPC_POLYGON_MODE = 0x00009108 +A6XX_VPC_POLYGON_MODE_MODE__MASK = 0x00000003 +A6XX_VPC_POLYGON_MODE_MODE__SHIFT = 0 +REG_A7XX_VPC_PRIMITIVE_CNTL_0 = 0x00009109 +A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 +A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 +A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 +A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 +REG_A7XX_VPC_PRIMITIVE_CNTL_5 = 0x0000910a +A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff +A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 +A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 +A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 +A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 +A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 +A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 +A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 +REG_A7XX_VPC_MULTIVIEW_MASK = 0x0000910b +REG_A7XX_VPC_MULTIVIEW_CNTL = 0x0000910c +A7XX_VPC_MULTIVIEW_CNTL_ENABLE = 0x00000001 +A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 +A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c +A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 +REG_A6XX_VPC_VARYING_INTERP = lambda i0: (0x00009200 + 0x1*i0 ) +REG_A6XX_VPC_VARYING_PS_REPL = lambda i0: (0x00009208 + 0x1*i0 ) +REG_A6XX_VPC_UNKNOWN_9210 = 0x00009210 +REG_A6XX_VPC_UNKNOWN_9211 = 0x00009211 +REG_A6XX_VPC_VAR = lambda i0: (0x00009212 + 0x1*i0 ) +REG_A6XX_VPC_SO_CNTL = 0x00009216 +A6XX_VPC_SO_CNTL_ADDR__MASK = 0x000000ff +A6XX_VPC_SO_CNTL_ADDR__SHIFT = 0 +A6XX_VPC_SO_CNTL_RESET = 0x00010000 +REG_A6XX_VPC_SO_PROG = 0x00009217 +A6XX_VPC_SO_PROG_A_BUF__MASK = 0x00000003 +A6XX_VPC_SO_PROG_A_BUF__SHIFT = 0 +A6XX_VPC_SO_PROG_A_OFF__MASK = 0x000007fc +A6XX_VPC_SO_PROG_A_OFF__SHIFT = 2 +A6XX_VPC_SO_PROG_A_EN = 0x00000800 +A6XX_VPC_SO_PROG_B_BUF__MASK = 0x00003000 +A6XX_VPC_SO_PROG_B_BUF__SHIFT = 12 +A6XX_VPC_SO_PROG_B_OFF__MASK = 0x007fc000 +A6XX_VPC_SO_PROG_B_OFF__SHIFT = 14 +A6XX_VPC_SO_PROG_B_EN = 0x00800000 +REG_A6XX_VPC_SO_STREAM_COUNTS = 0x00009218 +REG_A6XX_VPC_SO = lambda i0: (0x0000921a + 0x7*i0 ) +REG_A6XX_VPC_POINT_COORD_INVERT = 0x00009236 +A6XX_VPC_POINT_COORD_INVERT_INVERT = 0x00000001 +REG_A6XX_VPC_UNKNOWN_9300 = 0x00009300 +REG_A6XX_VPC_VS_PACK = 0x00009301 +A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT = 0 +A6XX_VPC_VS_PACK_POSITIONLOC__MASK = 0x0000ff00 +A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT = 8 +A6XX_VPC_VS_PACK_PSIZELOC__MASK = 0x00ff0000 +A6XX_VPC_VS_PACK_PSIZELOC__SHIFT = 16 +A6XX_VPC_VS_PACK_EXTRAPOS__MASK = 0x0f000000 +A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT = 24 +REG_A6XX_VPC_GS_PACK = 0x00009302 +A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT = 0 +A6XX_VPC_GS_PACK_POSITIONLOC__MASK = 0x0000ff00 +A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT = 8 +A6XX_VPC_GS_PACK_PSIZELOC__MASK = 0x00ff0000 +A6XX_VPC_GS_PACK_PSIZELOC__SHIFT = 16 +A6XX_VPC_GS_PACK_EXTRAPOS__MASK = 0x0f000000 +A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT = 24 +REG_A6XX_VPC_DS_PACK = 0x00009303 +A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT = 0 +A6XX_VPC_DS_PACK_POSITIONLOC__MASK = 0x0000ff00 +A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT = 8 +A6XX_VPC_DS_PACK_PSIZELOC__MASK = 0x00ff0000 +A6XX_VPC_DS_PACK_PSIZELOC__SHIFT = 16 +A6XX_VPC_DS_PACK_EXTRAPOS__MASK = 0x0f000000 +A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT = 24 +REG_A6XX_VPC_CNTL_0 = 0x00009304 +A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK = 0x000000ff +A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT = 0 +A6XX_VPC_CNTL_0_PRIMIDLOC__MASK = 0x0000ff00 +A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT = 8 +A6XX_VPC_CNTL_0_VARYING = 0x00010000 +A6XX_VPC_CNTL_0_VIEWIDLOC__MASK = 0xff000000 +A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT = 24 +REG_A6XX_VPC_SO_STREAM_CNTL = 0x00009305 +A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK = 0x00000007 +A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT = 0 +A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK = 0x00000038 +A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT = 3 +A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK = 0x000001c0 +A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT = 6 +A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK = 0x00000e00 +A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT = 9 +A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 +A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 +REG_A6XX_VPC_SO_DISABLE = 0x00009306 +A6XX_VPC_SO_DISABLE_DISABLE = 0x00000001 +REG_A7XX_VPC_POLYGON_MODE2 = 0x00009307 +A7XX_VPC_POLYGON_MODE2_MODE__MASK = 0x00000003 +A7XX_VPC_POLYGON_MODE2_MODE__SHIFT = 0 +REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM = 0x00009308 +A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff +A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 +REG_A7XX_VPC_ATTR_BUF_BASE_GMEM = 0x00009309 +A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK = 0xffffffff +A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT = 0 +REG_A7XX_PC_ATTR_BUF_SIZE_GMEM = 0x00009b09 +A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff +A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 +REG_A6XX_VPC_DBG_ECO_CNTL = 0x00009600 +REG_A6XX_VPC_ADDR_MODE_CNTL = 0x00009601 +REG_A6XX_VPC_UNKNOWN_9602 = 0x00009602 +REG_A6XX_VPC_UNKNOWN_9603 = 0x00009603 +REG_A6XX_VPC_PERFCTR_VPC_SEL = lambda i0: (0x00009604 + 0x1*i0 ) +REG_A7XX_VPC_PERFCTR_VPC_SEL = lambda i0: (0x0000960b + 0x1*i0 ) +REG_A6XX_PC_TESS_NUM_VERTEX = 0x00009800 +REG_A6XX_PC_HS_INPUT_SIZE = 0x00009801 +A6XX_PC_HS_INPUT_SIZE_SIZE__MASK = 0x000007ff +A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT = 0 +A6XX_PC_HS_INPUT_SIZE_UNK13 = 0x00002000 +REG_A6XX_PC_TESS_CNTL = 0x00009802 +A6XX_PC_TESS_CNTL_SPACING__MASK = 0x00000003 +A6XX_PC_TESS_CNTL_SPACING__SHIFT = 0 +A6XX_PC_TESS_CNTL_OUTPUT__MASK = 0x0000000c +A6XX_PC_TESS_CNTL_OUTPUT__SHIFT = 2 +REG_A6XX_PC_RESTART_INDEX = 0x00009803 +REG_A6XX_PC_MODE_CNTL = 0x00009804 +REG_A6XX_PC_POWER_CNTL = 0x00009805 +REG_A6XX_PC_PS_CNTL = 0x00009806 +A6XX_PC_PS_CNTL_PRIMITIVEIDEN = 0x00000001 +REG_A6XX_PC_SO_STREAM_CNTL = 0x00009808 +A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 +A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 +REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL = 0x0000980a +A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 +REG_A6XX_PC_DRAW_CMD = 0x00009840 +A6XX_PC_DRAW_CMD_STATE_ID__MASK = 0x000000ff +A6XX_PC_DRAW_CMD_STATE_ID__SHIFT = 0 +REG_A6XX_PC_DISPATCH_CMD = 0x00009841 +A6XX_PC_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff +A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT = 0 +REG_A6XX_PC_EVENT_CMD = 0x00009842 +A6XX_PC_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 +A6XX_PC_EVENT_CMD_STATE_ID__SHIFT = 16 +A6XX_PC_EVENT_CMD_EVENT__MASK = 0x0000007f +A6XX_PC_EVENT_CMD_EVENT__SHIFT = 0 +REG_A6XX_PC_MARKER = 0x00009880 +REG_A6XX_PC_POLYGON_MODE = 0x00009981 +A6XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 +A6XX_PC_POLYGON_MODE_MODE__SHIFT = 0 +REG_A7XX_PC_POLYGON_MODE = 0x00009809 +A7XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 +A7XX_PC_POLYGON_MODE_MODE__SHIFT = 0 +REG_A6XX_PC_RASTER_CNTL = 0x00009980 +A6XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 +A6XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 +A6XX_PC_RASTER_CNTL_DISCARD = 0x00000004 +REG_A7XX_PC_RASTER_CNTL = 0x00009107 +A7XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 +A7XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 +A7XX_PC_RASTER_CNTL_DISCARD = 0x00000004 +REG_A7XX_PC_RASTER_CNTL_V2 = 0x00009317 +A7XX_PC_RASTER_CNTL_V2_STREAM__MASK = 0x00000003 +A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT = 0 +A7XX_PC_RASTER_CNTL_V2_DISCARD = 0x00000004 +REG_A7XX_PC_TESS_PARAM_SIZE = 0x00009885 +REG_A7XX_PC_TESS_FACTOR_SIZE = 0x00009886 +REG_A6XX_PC_PRIMITIVE_CNTL_0 = 0x00009b00 +A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 +A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 +A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 +A6XX_PC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 +REG_A6XX_PC_VS_OUT_CNTL = 0x00009b01 +A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_VS_OUT_CNTL_PSIZE = 0x00000100 +A6XX_PC_VS_OUT_CNTL_LAYER = 0x00000200 +A6XX_PC_VS_OUT_CNTL_VIEW = 0x00000400 +A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_VS_OUT_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_GS_OUT_CNTL = 0x00009b02 +A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_GS_OUT_CNTL_PSIZE = 0x00000100 +A6XX_PC_GS_OUT_CNTL_LAYER = 0x00000200 +A6XX_PC_GS_OUT_CNTL_VIEW = 0x00000400 +A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_GS_OUT_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_HS_OUT_CNTL = 0x00009b03 +A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_HS_OUT_CNTL_PSIZE = 0x00000100 +A6XX_PC_HS_OUT_CNTL_LAYER = 0x00000200 +A6XX_PC_HS_OUT_CNTL_VIEW = 0x00000400 +A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_HS_OUT_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_DS_OUT_CNTL = 0x00009b04 +A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_DS_OUT_CNTL_PSIZE = 0x00000100 +A6XX_PC_DS_OUT_CNTL_LAYER = 0x00000200 +A6XX_PC_DS_OUT_CNTL_VIEW = 0x00000400 +A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_DS_OUT_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_PRIMITIVE_CNTL_5 = 0x00009b05 +A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff +A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 +A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 +A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 +A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 +A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 +A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 +A6XX_PC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 +REG_A6XX_PC_PRIMITIVE_CNTL_6 = 0x00009b06 +A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK = 0x000007ff +A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT = 0 +REG_A6XX_PC_MULTIVIEW_CNTL = 0x00009b07 +A6XX_PC_MULTIVIEW_CNTL_ENABLE = 0x00000001 +A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 +A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c +A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 +REG_A6XX_PC_MULTIVIEW_MASK = 0x00009b08 +REG_A6XX_PC_2D_EVENT_CMD = 0x00009c00 +A6XX_PC_2D_EVENT_CMD_EVENT__MASK = 0x0000007f +A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT = 0 +A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 +A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT = 8 +REG_A6XX_PC_DBG_ECO_CNTL = 0x00009e00 +REG_A6XX_PC_ADDR_MODE_CNTL = 0x00009e01 +REG_A6XX_PC_DRAW_INDX_BASE = 0x00009e04 +REG_A6XX_PC_DRAW_FIRST_INDX = 0x00009e06 +REG_A6XX_PC_DRAW_MAX_INDICES = 0x00009e07 +REG_A6XX_PC_TESSFACTOR_ADDR = 0x00009e08 +REG_A7XX_PC_TESSFACTOR_ADDR = 0x00009810 +REG_A6XX_PC_DRAW_INITIATOR = 0x00009e0b +A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK = 0x0000003f +A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT = 0 +A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK = 0x000000c0 +A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT = 6 +A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK = 0x00000300 +A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT = 8 +A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK = 0x00000c00 +A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT = 10 +A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK = 0x00003000 +A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT = 12 +A6XX_PC_DRAW_INITIATOR_GS_ENABLE = 0x00010000 +A6XX_PC_DRAW_INITIATOR_TESS_ENABLE = 0x00020000 +REG_A6XX_PC_DRAW_NUM_INSTANCES = 0x00009e0c +REG_A6XX_PC_DRAW_NUM_INDICES = 0x00009e0d +REG_A6XX_PC_VSTREAM_CONTROL = 0x00009e11 +A6XX_PC_VSTREAM_CONTROL_UNK0__MASK = 0x0000ffff +A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT = 0 +A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK = 0x003f0000 +A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT = 16 +A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK = 0x07c00000 +A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT = 22 +REG_A6XX_PC_BIN_PRIM_STRM = 0x00009e12 +REG_A6XX_PC_BIN_DRAW_STRM = 0x00009e14 +REG_A6XX_PC_VISIBILITY_OVERRIDE = 0x00009e1c +A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE = 0x00000001 +REG_A7XX_PC_UNKNOWN_9E24 = 0x00009e24 +REG_A6XX_PC_PERFCTR_PC_SEL = lambda i0: (0x00009e34 + 0x1*i0 ) +REG_A7XX_PC_PERFCTR_PC_SEL = lambda i0: (0x00009e42 + 0x1*i0 ) +REG_A6XX_PC_UNKNOWN_9E72 = 0x00009e72 +REG_A6XX_VFD_CONTROL_0 = 0x0000a000 +A6XX_VFD_CONTROL_0_FETCH_CNT__MASK = 0x0000003f +A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT = 0 +A6XX_VFD_CONTROL_0_DECODE_CNT__MASK = 0x00003f00 +A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT = 8 +REG_A6XX_VFD_CONTROL_1 = 0x0000a001 +A6XX_VFD_CONTROL_1_REGID4VTX__MASK = 0x000000ff +A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT = 0 +A6XX_VFD_CONTROL_1_REGID4INST__MASK = 0x0000ff00 +A6XX_VFD_CONTROL_1_REGID4INST__SHIFT = 8 +A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK = 0x00ff0000 +A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT = 16 +A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK = 0xff000000 +A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT = 24 +REG_A6XX_VFD_CONTROL_2 = 0x0000a002 +A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK = 0x000000ff +A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT = 0 +A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK = 0x0000ff00 +A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT = 8 +REG_A6XX_VFD_CONTROL_3 = 0x0000a003 +A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK = 0x000000ff +A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT = 0 +A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK = 0x0000ff00 +A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT = 8 +A6XX_VFD_CONTROL_3_REGID_TESSX__MASK = 0x00ff0000 +A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT = 16 +A6XX_VFD_CONTROL_3_REGID_TESSY__MASK = 0xff000000 +A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT = 24 +REG_A6XX_VFD_CONTROL_4 = 0x0000a004 +A6XX_VFD_CONTROL_4_UNK0__MASK = 0x000000ff +A6XX_VFD_CONTROL_4_UNK0__SHIFT = 0 +REG_A6XX_VFD_CONTROL_5 = 0x0000a005 +A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK = 0x000000ff +A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT = 0 +A6XX_VFD_CONTROL_5_UNK8__MASK = 0x0000ff00 +A6XX_VFD_CONTROL_5_UNK8__SHIFT = 8 +REG_A6XX_VFD_CONTROL_6 = 0x0000a006 +A6XX_VFD_CONTROL_6_PRIMID4PSEN = 0x00000001 +REG_A6XX_VFD_MODE_CNTL = 0x0000a007 +A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK = 0x00000007 +A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT = 0 +REG_A6XX_VFD_MULTIVIEW_CNTL = 0x0000a008 +A6XX_VFD_MULTIVIEW_CNTL_ENABLE = 0x00000001 +A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 +A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c +A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 +REG_A6XX_VFD_ADD_OFFSET = 0x0000a009 +A6XX_VFD_ADD_OFFSET_VERTEX = 0x00000001 +A6XX_VFD_ADD_OFFSET_INSTANCE = 0x00000002 +REG_A6XX_VFD_INDEX_OFFSET = 0x0000a00e +REG_A6XX_VFD_INSTANCE_START_OFFSET = 0x0000a00f +REG_A6XX_VFD_FETCH = lambda i0: (0x0000a010 + 0x4*i0 ) +REG_A6XX_VFD_DECODE = lambda i0: (0x0000a090 + 0x2*i0 ) +A6XX_VFD_DECODE_INSTR_IDX__MASK = 0x0000001f +A6XX_VFD_DECODE_INSTR_IDX__SHIFT = 0 +A6XX_VFD_DECODE_INSTR_OFFSET__MASK = 0x0001ffe0 +A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT = 5 +A6XX_VFD_DECODE_INSTR_INSTANCED = 0x00020000 +A6XX_VFD_DECODE_INSTR_FORMAT__MASK = 0x0ff00000 +A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT = 20 +A6XX_VFD_DECODE_INSTR_SWAP__MASK = 0x30000000 +A6XX_VFD_DECODE_INSTR_SWAP__SHIFT = 28 +A6XX_VFD_DECODE_INSTR_UNK30 = 0x40000000 +A6XX_VFD_DECODE_INSTR_FLOAT = 0x80000000 +REG_A6XX_VFD_DEST_CNTL = lambda i0: (0x0000a0d0 + 0x1*i0 ) +A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK = 0x0000000f +A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT = 0 +A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK = 0x00000ff0 +A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT = 4 +REG_A6XX_VFD_POWER_CNTL = 0x0000a0f8 +REG_A7XX_VFD_UNKNOWN_A600 = 0x0000a600 +REG_A6XX_VFD_ADDR_MODE_CNTL = 0x0000a601 +REG_A6XX_VFD_PERFCTR_VFD_SEL = lambda i0: (0x0000a610 + 0x1*i0 ) +REG_A7XX_VFD_PERFCTR_VFD_SEL = lambda i0: (0x0000a610 + 0x1*i0 ) +REG_A6XX_SP_VS_CTRL_REG0 = 0x0000a800 +A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK = 0x00000001 +A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT = 0 +A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_VS_CTRL_REG0_UNK13 = 0x00002000 +A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_VS_CTRL_REG0_MERGEDREGS = 0x00100000 +A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE = 0x00200000 +REG_A6XX_SP_VS_BRANCH_COND = 0x0000a801 +REG_A6XX_SP_VS_PRIMITIVE_CNTL = 0x0000a802 +A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f +A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT = 0 +A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 +A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 +REG_A6XX_SP_VS_OUT = lambda i0: (0x0000a803 + 0x1*i0 ) +A6XX_SP_VS_OUT_REG_A_REGID__MASK = 0x000000ff +A6XX_SP_VS_OUT_REG_A_REGID__SHIFT = 0 +A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 +A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT = 8 +A6XX_SP_VS_OUT_REG_B_REGID__MASK = 0x00ff0000 +A6XX_SP_VS_OUT_REG_B_REGID__SHIFT = 16 +A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 +A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT = 24 +REG_A6XX_SP_VS_VPC_DST = lambda i0: (0x0000a813 + 0x1*i0 ) +A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff +A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT = 0 +A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 +A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT = 8 +A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 +A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT = 16 +A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 +A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT = 24 +REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET = 0x0000a81b +REG_A6XX_SP_VS_OBJ_START = 0x0000a81c +REG_A6XX_SP_VS_PVT_MEM_PARAM = 0x0000a81e +A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_VS_PVT_MEM_ADDR = 0x0000a81f +REG_A6XX_SP_VS_PVT_MEM_SIZE = 0x0000a821 +A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_VS_TEX_COUNT = 0x0000a822 +REG_A6XX_SP_VS_CONFIG = 0x0000a823 +A6XX_SP_VS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_VS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_VS_CONFIG_BINDLESS_IBO = 0x00000004 +A6XX_SP_VS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_VS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_VS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_VS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_VS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_VS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_VS_CONFIG_NIBO__MASK = 0x1fc00000 +A6XX_SP_VS_CONFIG_NIBO__SHIFT = 22 +REG_A6XX_SP_VS_INSTRLEN = 0x0000a824 +REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET = 0x0000a825 +A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_VS_VGPR_CONFIG = 0x0000a82d +REG_A6XX_SP_HS_CTRL_REG0 = 0x0000a830 +A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK = 0x00000001 +A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT = 0 +A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_HS_CTRL_REG0_UNK13 = 0x00002000 +A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 +REG_A6XX_SP_HS_WAVE_INPUT_SIZE = 0x0000a831 +REG_A6XX_SP_HS_BRANCH_COND = 0x0000a832 +REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET = 0x0000a833 +REG_A6XX_SP_HS_OBJ_START = 0x0000a834 +REG_A6XX_SP_HS_PVT_MEM_PARAM = 0x0000a836 +A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_HS_PVT_MEM_ADDR = 0x0000a837 +REG_A6XX_SP_HS_PVT_MEM_SIZE = 0x0000a839 +A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_HS_TEX_COUNT = 0x0000a83a +REG_A6XX_SP_HS_CONFIG = 0x0000a83b +A6XX_SP_HS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_HS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_HS_CONFIG_BINDLESS_IBO = 0x00000004 +A6XX_SP_HS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_HS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_HS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_HS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_HS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_HS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_HS_CONFIG_NIBO__MASK = 0x1fc00000 +A6XX_SP_HS_CONFIG_NIBO__SHIFT = 22 +REG_A6XX_SP_HS_INSTRLEN = 0x0000a83c +REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET = 0x0000a83d +A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_HS_VGPR_CONFIG = 0x0000a82f +REG_A6XX_SP_DS_CTRL_REG0 = 0x0000a840 +A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK = 0x00000001 +A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT = 0 +A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_DS_CTRL_REG0_UNK13 = 0x00002000 +A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 +REG_A6XX_SP_DS_BRANCH_COND = 0x0000a841 +REG_A6XX_SP_DS_PRIMITIVE_CNTL = 0x0000a842 +A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f +A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT = 0 +A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 +A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 +REG_A6XX_SP_DS_OUT = lambda i0: (0x0000a843 + 0x1*i0 ) +A6XX_SP_DS_OUT_REG_A_REGID__MASK = 0x000000ff +A6XX_SP_DS_OUT_REG_A_REGID__SHIFT = 0 +A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 +A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT = 8 +A6XX_SP_DS_OUT_REG_B_REGID__MASK = 0x00ff0000 +A6XX_SP_DS_OUT_REG_B_REGID__SHIFT = 16 +A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 +A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT = 24 +REG_A6XX_SP_DS_VPC_DST = lambda i0: (0x0000a853 + 0x1*i0 ) +A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff +A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT = 0 +A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 +A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT = 8 +A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 +A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT = 16 +A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 +A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT = 24 +REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET = 0x0000a85b +REG_A6XX_SP_DS_OBJ_START = 0x0000a85c +REG_A6XX_SP_DS_PVT_MEM_PARAM = 0x0000a85e +A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_DS_PVT_MEM_ADDR = 0x0000a85f +REG_A6XX_SP_DS_PVT_MEM_SIZE = 0x0000a861 +A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_DS_TEX_COUNT = 0x0000a862 +REG_A6XX_SP_DS_CONFIG = 0x0000a863 +A6XX_SP_DS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_DS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_DS_CONFIG_BINDLESS_IBO = 0x00000004 +A6XX_SP_DS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_DS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_DS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_DS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_DS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_DS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_DS_CONFIG_NIBO__MASK = 0x1fc00000 +A6XX_SP_DS_CONFIG_NIBO__SHIFT = 22 +REG_A6XX_SP_DS_INSTRLEN = 0x0000a864 +REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET = 0x0000a865 +A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_DS_VGPR_CONFIG = 0x0000a868 +REG_A6XX_SP_GS_CTRL_REG0 = 0x0000a870 +A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK = 0x00000001 +A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT = 0 +A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_GS_CTRL_REG0_UNK13 = 0x00002000 +A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 +REG_A6XX_SP_GS_PRIM_SIZE = 0x0000a871 +REG_A6XX_SP_GS_BRANCH_COND = 0x0000a872 +REG_A6XX_SP_GS_PRIMITIVE_CNTL = 0x0000a873 +A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f +A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT = 0 +A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 +A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 +REG_A6XX_SP_GS_OUT = lambda i0: (0x0000a874 + 0x1*i0 ) +A6XX_SP_GS_OUT_REG_A_REGID__MASK = 0x000000ff +A6XX_SP_GS_OUT_REG_A_REGID__SHIFT = 0 +A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 +A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT = 8 +A6XX_SP_GS_OUT_REG_B_REGID__MASK = 0x00ff0000 +A6XX_SP_GS_OUT_REG_B_REGID__SHIFT = 16 +A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 +A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT = 24 +REG_A6XX_SP_GS_VPC_DST = lambda i0: (0x0000a884 + 0x1*i0 ) +A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff +A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT = 0 +A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 +A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT = 8 +A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 +A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT = 16 +A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 +A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT = 24 +REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET = 0x0000a88c +REG_A6XX_SP_GS_OBJ_START = 0x0000a88d +REG_A6XX_SP_GS_PVT_MEM_PARAM = 0x0000a88f +A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_GS_PVT_MEM_ADDR = 0x0000a890 +REG_A6XX_SP_GS_PVT_MEM_SIZE = 0x0000a892 +A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_GS_TEX_COUNT = 0x0000a893 +REG_A6XX_SP_GS_CONFIG = 0x0000a894 +A6XX_SP_GS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_GS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_GS_CONFIG_BINDLESS_IBO = 0x00000004 +A6XX_SP_GS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_GS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_GS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_GS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_GS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_GS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_GS_CONFIG_NIBO__MASK = 0x1fc00000 +A6XX_SP_GS_CONFIG_NIBO__SHIFT = 22 +REG_A6XX_SP_GS_INSTRLEN = 0x0000a895 +REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET = 0x0000a896 +A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_GS_VGPR_CONFIG = 0x0000a899 +REG_A6XX_SP_VS_TEX_SAMP = 0x0000a8a0 +REG_A6XX_SP_HS_TEX_SAMP = 0x0000a8a2 +REG_A6XX_SP_DS_TEX_SAMP = 0x0000a8a4 +REG_A6XX_SP_GS_TEX_SAMP = 0x0000a8a6 +REG_A6XX_SP_VS_TEX_CONST = 0x0000a8a8 +REG_A6XX_SP_HS_TEX_CONST = 0x0000a8aa +REG_A6XX_SP_DS_TEX_CONST = 0x0000a8ac +REG_A6XX_SP_GS_TEX_CONST = 0x0000a8ae +REG_A6XX_SP_FS_CTRL_REG0 = 0x0000a980 +A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK = 0x00000001 +A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT = 0 +A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_FS_CTRL_REG0_UNK13 = 0x00002000 +A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 +A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT = 20 +A6XX_SP_FS_CTRL_REG0_UNK21 = 0x00200000 +A6XX_SP_FS_CTRL_REG0_VARYING = 0x00400000 +A6XX_SP_FS_CTRL_REG0_LODPIXMASK = 0x00800000 +A6XX_SP_FS_CTRL_REG0_UNK24 = 0x01000000 +A6XX_SP_FS_CTRL_REG0_UNK25 = 0x02000000 +A6XX_SP_FS_CTRL_REG0_PIXLODENABLE = 0x04000000 +A6XX_SP_FS_CTRL_REG0_UNK27 = 0x08000000 +A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE = 0x10000000 +A6XX_SP_FS_CTRL_REG0_MERGEDREGS = 0x80000000 +REG_A6XX_SP_FS_BRANCH_COND = 0x0000a981 +REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET = 0x0000a982 +REG_A6XX_SP_FS_OBJ_START = 0x0000a983 +REG_A6XX_SP_FS_PVT_MEM_PARAM = 0x0000a985 +A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_FS_PVT_MEM_ADDR = 0x0000a986 +REG_A6XX_SP_FS_PVT_MEM_SIZE = 0x0000a988 +A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_BLEND_CNTL = 0x0000a989 +A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff +A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 +A6XX_SP_BLEND_CNTL_UNK8 = 0x00000100 +A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 +A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 +REG_A6XX_SP_SRGB_CNTL = 0x0000a98a +A6XX_SP_SRGB_CNTL_SRGB_MRT0 = 0x00000001 +A6XX_SP_SRGB_CNTL_SRGB_MRT1 = 0x00000002 +A6XX_SP_SRGB_CNTL_SRGB_MRT2 = 0x00000004 +A6XX_SP_SRGB_CNTL_SRGB_MRT3 = 0x00000008 +A6XX_SP_SRGB_CNTL_SRGB_MRT4 = 0x00000010 +A6XX_SP_SRGB_CNTL_SRGB_MRT5 = 0x00000020 +A6XX_SP_SRGB_CNTL_SRGB_MRT6 = 0x00000040 +A6XX_SP_SRGB_CNTL_SRGB_MRT7 = 0x00000080 +REG_A6XX_SP_FS_RENDER_COMPONENTS = 0x0000a98b +A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK = 0x0000000f +A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT = 0 +A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 +A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT = 4 +A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 +A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT = 8 +A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 +A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT = 12 +A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 +A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT = 16 +A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 +A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT = 20 +A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 +A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT = 24 +A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 +A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT = 28 +REG_A6XX_SP_FS_OUTPUT_CNTL0 = 0x0000a98c +A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 +A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK = 0x0000ff00 +A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT = 8 +A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK = 0x00ff0000 +A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT = 16 +A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK = 0xff000000 +A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT = 24 +REG_A6XX_SP_FS_OUTPUT_CNTL1 = 0x0000a98d +A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f +A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 +REG_A6XX_SP_FS_OUTPUT = lambda i0: (0x0000a98e + 0x1*i0 ) +A6XX_SP_FS_OUTPUT_REG_REGID__MASK = 0x000000ff +A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT = 0 +A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION = 0x00000100 +REG_A6XX_SP_FS_MRT = lambda i0: (0x0000a996 + 0x1*i0 ) +A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK = 0x000000ff +A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT = 0 +A6XX_SP_FS_MRT_REG_COLOR_SINT = 0x00000100 +A6XX_SP_FS_MRT_REG_COLOR_UINT = 0x00000200 +A6XX_SP_FS_MRT_REG_UNK10 = 0x00000400 +REG_A6XX_SP_FS_PREFETCH_CNTL = 0x0000a99e +A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK = 0x00000007 +A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT = 0 +A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE = 0x00000008 +A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD = 0x00000010 +A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT = 0x00000020 +A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK = 0x00007fc0 +A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT = 6 +A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK = 0x01ff0000 +A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT = 16 +REG_A6XX_SP_FS_PREFETCH = lambda i0: (0x0000a99f + 0x1*i0 ) +A6XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f +A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 +A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000780 +A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 +A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x0000f800 +A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 11 +A6XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x003f0000 +A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 16 +A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x03c00000 +A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 22 +A6XX_SP_FS_PREFETCH_CMD_HALF = 0x04000000 +A6XX_SP_FS_PREFETCH_CMD_UNK27 = 0x08000000 +A6XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x10000000 +A6XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0xe0000000 +A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 29 +REG_A7XX_SP_FS_PREFETCH = lambda i0: (0x0000a99f + 0x1*i0 ) +A7XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f +A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 +A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000380 +A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 +A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x00001c00 +A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 10 +A7XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x0007e000 +A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 13 +A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x00780000 +A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 19 +A7XX_SP_FS_PREFETCH_CMD_HALF = 0x00800000 +A7XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x02000000 +A7XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0x3c000000 +A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 26 +REG_A6XX_SP_FS_BINDLESS_PREFETCH = lambda i0: (0x0000a9a3 + 0x1*i0 ) +A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK = 0x0000ffff +A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT = 0 +A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK = 0xffff0000 +A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT = 16 +REG_A6XX_SP_FS_TEX_COUNT = 0x0000a9a7 +REG_A6XX_SP_UNKNOWN_A9A8 = 0x0000a9a8 +REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9a9 +A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A6XX_SP_CS_CTRL_REG0 = 0x0000a9b0 +A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK = 0x00000001 +A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT = 0 +A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_CS_CTRL_REG0_UNK13 = 0x00002000 +A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 +A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT = 20 +A6XX_SP_CS_CTRL_REG0_UNK21 = 0x00200000 +A6XX_SP_CS_CTRL_REG0_UNK22 = 0x00400000 +A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE = 0x00800000 +A6XX_SP_CS_CTRL_REG0_MERGEDREGS = 0x80000000 +REG_A6XX_SP_CS_UNKNOWN_A9B1 = 0x0000a9b1 +A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK = 0x0000001f +A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT = 0 +A6XX_SP_CS_UNKNOWN_A9B1_UNK5 = 0x00000020 +A6XX_SP_CS_UNKNOWN_A9B1_UNK6 = 0x00000040 +REG_A6XX_SP_CS_BRANCH_COND = 0x0000a9b2 +REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET = 0x0000a9b3 +REG_A6XX_SP_CS_OBJ_START = 0x0000a9b4 +REG_A6XX_SP_CS_PVT_MEM_PARAM = 0x0000a9b6 +A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_CS_PVT_MEM_ADDR = 0x0000a9b7 +REG_A6XX_SP_CS_PVT_MEM_SIZE = 0x0000a9b9 +A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_CS_TEX_COUNT = 0x0000a9ba +REG_A6XX_SP_CS_CONFIG = 0x0000a9bb +A6XX_SP_CS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_CS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_CS_CONFIG_BINDLESS_IBO = 0x00000004 +A6XX_SP_CS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_CS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_CS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_CS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_CS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_CS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_CS_CONFIG_NIBO__MASK = 0x1fc00000 +A6XX_SP_CS_CONFIG_NIBO__SHIFT = 22 +REG_A6XX_SP_CS_INSTRLEN = 0x0000a9bc +REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9bd +A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_CS_UNKNOWN_A9BE = 0x0000a9be +REG_A7XX_SP_CS_VGPR_CONFIG = 0x0000a9c5 +REG_A6XX_SP_CS_CNTL_0 = 0x0000a9c2 +A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff +A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 +A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 +A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 +A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 +A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 +A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 +A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 +REG_A6XX_SP_CS_CNTL_1 = 0x0000a9c3 +A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff +A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 +A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 +A6XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 +A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 9 +A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 +REG_A7XX_SP_CS_CNTL_1 = 0x0000a9c3 +A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff +A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 +A7XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000100 +A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 8 +A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000200 +A7XX_SP_CS_CNTL_1_UNK15 = 0x00008000 +REG_A6XX_SP_FS_TEX_SAMP = 0x0000a9e0 +REG_A6XX_SP_CS_TEX_SAMP = 0x0000a9e2 +REG_A6XX_SP_FS_TEX_CONST = 0x0000a9e4 +REG_A6XX_SP_CS_TEX_CONST = 0x0000a9e6 +REG_A6XX_SP_CS_BINDLESS_BASE = lambda i0: (0x0000a9e8 + 0x2*i0 ) +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A7XX_SP_CS_BINDLESS_BASE = lambda i0: (0x0000a9e8 + 0x2*i0 ) +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_SP_CS_IBO = 0x0000a9f2 +REG_A6XX_SP_CS_IBO_COUNT = 0x0000aa00 +REG_A7XX_SP_FS_VGPR_CONFIG = 0x0000aa01 +REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL = 0x0000aa02 +A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED = 0x00000001 +REG_A7XX_SP_PS_ALIASED_COMPONENTS = 0x0000aa03 +A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK = 0x0000000f +A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT = 0 +A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK = 0x000000f0 +A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT = 4 +A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK = 0x00000f00 +A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT = 8 +A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK = 0x0000f000 +A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT = 12 +A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK = 0x000f0000 +A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT = 16 +A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK = 0x00f00000 +A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT = 20 +A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK = 0x0f000000 +A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT = 24 +A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK = 0xf0000000 +A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT = 28 +REG_A6XX_SP_UNKNOWN_AAF2 = 0x0000aaf2 +REG_A6XX_SP_MODE_CONTROL = 0x0000ab00 +A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE = 0x00000001 +A6XX_SP_MODE_CONTROL_ISAMMODE__MASK = 0x00000006 +A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT = 1 +A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE = 0x00000008 +REG_A7XX_SP_UNKNOWN_AB01 = 0x0000ab01 +REG_A7XX_SP_UNKNOWN_AB02 = 0x0000ab02 +REG_A6XX_SP_FS_CONFIG = 0x0000ab04 +A6XX_SP_FS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_FS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_FS_CONFIG_BINDLESS_IBO = 0x00000004 +A6XX_SP_FS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_FS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_FS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_FS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_FS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_FS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_FS_CONFIG_NIBO__MASK = 0x1fc00000 +A6XX_SP_FS_CONFIG_NIBO__SHIFT = 22 +REG_A6XX_SP_FS_INSTRLEN = 0x0000ab05 +REG_A6XX_SP_BINDLESS_BASE = lambda i0: (0x0000ab10 + 0x2*i0 ) +A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A7XX_SP_BINDLESS_BASE = lambda i0: (0x0000ab0a + 0x2*i0 ) +A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_SP_IBO = 0x0000ab1a +REG_A6XX_SP_IBO_COUNT = 0x0000ab20 +REG_A7XX_SP_UNKNOWN_AB22 = 0x0000ab22 +REG_A6XX_SP_2D_DST_FORMAT = 0x0000acc0 +A6XX_SP_2D_DST_FORMAT_NORM = 0x00000001 +A6XX_SP_2D_DST_FORMAT_SINT = 0x00000002 +A6XX_SP_2D_DST_FORMAT_UINT = 0x00000004 +A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 +A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 +A6XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 +A6XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 +A6XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 +REG_A7XX_SP_2D_DST_FORMAT = 0x0000a9bf +A7XX_SP_2D_DST_FORMAT_NORM = 0x00000001 +A7XX_SP_2D_DST_FORMAT_SINT = 0x00000002 +A7XX_SP_2D_DST_FORMAT_UINT = 0x00000004 +A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 +A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 +A7XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 +A7XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 +A7XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 +REG_A6XX_SP_DBG_ECO_CNTL = 0x0000ae00 +REG_A6XX_SP_ADDR_MODE_CNTL = 0x0000ae01 +REG_A6XX_SP_NC_MODE_CNTL = 0x0000ae02 +REG_A6XX_SP_CHICKEN_BITS = 0x0000ae03 +REG_A6XX_SP_FLOAT_CNTL = 0x0000ae04 +A6XX_SP_FLOAT_CNTL_F16_NO_INF = 0x00000008 +REG_A7XX_SP_UNKNOWN_AE06 = 0x0000ae06 +REG_A7XX_SP_UNKNOWN_AE08 = 0x0000ae08 +REG_A7XX_SP_UNKNOWN_AE09 = 0x0000ae09 +REG_A7XX_SP_UNKNOWN_AE0A = 0x0000ae0a +REG_A6XX_SP_PERFCTR_ENABLE = 0x0000ae0f +A6XX_SP_PERFCTR_ENABLE_VS = 0x00000001 +A6XX_SP_PERFCTR_ENABLE_HS = 0x00000002 +A6XX_SP_PERFCTR_ENABLE_DS = 0x00000004 +A6XX_SP_PERFCTR_ENABLE_GS = 0x00000008 +A6XX_SP_PERFCTR_ENABLE_FS = 0x00000010 +A6XX_SP_PERFCTR_ENABLE_CS = 0x00000020 +REG_A6XX_SP_PERFCTR_SP_SEL = lambda i0: (0x0000ae10 + 0x1*i0 ) +REG_A7XX_SP_PERFCTR_HLSQ_SEL = lambda i0: (0x0000ae60 + 0x1*i0 ) +REG_A7XX_SP_UNKNOWN_AE6A = 0x0000ae6a +REG_A7XX_SP_UNKNOWN_AE6B = 0x0000ae6b +REG_A7XX_SP_UNKNOWN_AE6C = 0x0000ae6c +REG_A7XX_SP_READ_SEL = 0x0000ae6d +A7XX_SP_READ_SEL_LOCATION__MASK = 0x000c0000 +A7XX_SP_READ_SEL_LOCATION__SHIFT = 18 +A7XX_SP_READ_SEL_PIPE__MASK = 0x00030000 +A7XX_SP_READ_SEL_PIPE__SHIFT = 16 +A7XX_SP_READ_SEL_STATETYPE__MASK = 0x0000ff00 +A7XX_SP_READ_SEL_STATETYPE__SHIFT = 8 +A7XX_SP_READ_SEL_USPTP__MASK = 0x000000f0 +A7XX_SP_READ_SEL_USPTP__SHIFT = 4 +A7XX_SP_READ_SEL_SPTP__MASK = 0x0000000f +A7XX_SP_READ_SEL_SPTP__SHIFT = 0 +REG_A7XX_SP_DBG_CNTL = 0x0000ae71 +REG_A7XX_SP_UNKNOWN_AE73 = 0x0000ae73 +REG_A7XX_SP_PERFCTR_SP_SEL = lambda i0: (0x0000ae80 + 0x1*i0 ) +REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 +REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR = 0x0000b180 +REG_A6XX_SP_UNKNOWN_B182 = 0x0000b182 +REG_A6XX_SP_UNKNOWN_B183 = 0x0000b183 +REG_A6XX_SP_UNKNOWN_B190 = 0x0000b190 +REG_A6XX_SP_UNKNOWN_B191 = 0x0000b191 +REG_A6XX_SP_TP_RAS_MSAA_CNTL = 0x0000b300 +A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK = 0x0000000c +A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT = 2 +REG_A6XX_SP_TP_DEST_MSAA_CNTL = 0x0000b301 +A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 +REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR = 0x0000b302 +REG_A6XX_SP_TP_SAMPLE_CONFIG = 0x0000b304 +A6XX_SP_TP_SAMPLE_CONFIG_UNK0 = 0x00000001 +A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 +REG_A6XX_SP_TP_SAMPLE_LOCATION_0 = 0x0000b305 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_SP_TP_SAMPLE_LOCATION_1 = 0x0000b306 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_SP_TP_WINDOW_OFFSET = 0x0000b307 +A6XX_SP_TP_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_SP_TP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_SP_TP_MODE_CNTL = 0x0000b309 +A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK = 0x00000003 +A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT = 0 +A6XX_SP_TP_MODE_CNTL_UNK3__MASK = 0x000000fc +A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT = 2 +REG_A7XX_SP_UNKNOWN_B310 = 0x0000b310 +REG_A6XX_SP_PS_2D_SRC_INFO = 0x0000b4c0 +A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff +A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 +A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 +A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 +A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 +A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 +A6XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 +A6XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 +A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 +A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 +A6XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 +A6XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 +A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 +A6XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 +A6XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 +A6XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 +A6XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 +A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 +A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 +A6XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 +REG_A6XX_SP_PS_2D_SRC_SIZE = 0x0000b4c1 +A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff +A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 +A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 +A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 +REG_A6XX_SP_PS_2D_SRC = 0x0000b4c2 +REG_A6XX_SP_PS_2D_SRC_PITCH = 0x0000b4c4 +A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff +A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 +A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 +A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 +REG_A7XX_SP_PS_2D_SRC_INFO = 0x0000b2c0 +A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff +A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 +A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 +A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 +A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 +A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 +A7XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 +A7XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 +A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 +A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 +A7XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 +A7XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 +A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 +A7XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 +A7XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 +A7XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 +A7XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 +A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 +A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 +A7XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 +REG_A7XX_SP_PS_2D_SRC_SIZE = 0x0000b2c1 +A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff +A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 +A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 +A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 +REG_A7XX_SP_PS_2D_SRC = 0x0000b2c2 +REG_A7XX_SP_PS_2D_SRC_PITCH = 0x0000b2c4 +A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff +A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 +A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 +A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 +REG_A6XX_SP_PS_2D_SRC_PLANE1 = 0x0000b4c5 +REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b4c7 +A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff +A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 +REG_A6XX_SP_PS_2D_SRC_PLANE2 = 0x0000b4c8 +REG_A7XX_SP_PS_2D_SRC_PLANE1 = 0x0000b2c5 +REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b2c7 +A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff +A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 +REG_A7XX_SP_PS_2D_SRC_PLANE2 = 0x0000b2c8 +REG_A6XX_SP_PS_2D_SRC_FLAGS = 0x0000b4ca +REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b4cc +A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff +A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 +REG_A7XX_SP_PS_2D_SRC_FLAGS = 0x0000b2ca +REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b2cc +A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff +A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 +REG_A6XX_SP_PS_UNKNOWN_B4CD = 0x0000b4cd +REG_A6XX_SP_PS_UNKNOWN_B4CE = 0x0000b4ce +REG_A6XX_SP_PS_UNKNOWN_B4CF = 0x0000b4cf +REG_A6XX_SP_PS_UNKNOWN_B4D0 = 0x0000b4d0 +REG_A6XX_SP_WINDOW_OFFSET = 0x0000b4d1 +A6XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_SP_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A7XX_SP_PS_UNKNOWN_B4CD = 0x0000b2cd +REG_A7XX_SP_PS_UNKNOWN_B4CE = 0x0000b2ce +REG_A7XX_SP_PS_UNKNOWN_B4CF = 0x0000b2cf +REG_A7XX_SP_PS_UNKNOWN_B4D0 = 0x0000b2d0 +REG_A7XX_SP_PS_2D_WINDOW_OFFSET = 0x0000b2d1 +A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK = 0x00003fff +A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT = 0 +A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A7XX_SP_PS_UNKNOWN_B2D2 = 0x0000b2d2 +REG_A7XX_SP_WINDOW_OFFSET = 0x0000ab21 +A7XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff +A7XX_SP_WINDOW_OFFSET_X__SHIFT = 0 +A7XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A7XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_TPL1_DBG_ECO_CNTL = 0x0000b600 +REG_A6XX_TPL1_ADDR_MODE_CNTL = 0x0000b601 +REG_A6XX_TPL1_DBG_ECO_CNTL1 = 0x0000b602 +A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND = 0x00040000 +REG_A6XX_TPL1_NC_MODE_CNTL = 0x0000b604 +A6XX_TPL1_NC_MODE_CNTL_MODE = 0x00000001 +A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 +A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 +A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 +A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000010 +A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT = 4 +A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK = 0x000000c0 +A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT = 6 +REG_A6XX_TPL1_UNKNOWN_B605 = 0x0000b605 +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c +REG_A6XX_TPL1_PERFCTR_TP_SEL = lambda i0: (0x0000b610 + 0x1*i0 ) +REG_A7XX_TPL1_PERFCTR_TP_SEL = lambda i0: (0x0000b610 + 0x1*i0 ) +REG_A6XX_HLSQ_VS_CNTL = 0x0000b800 +A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff +A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 +A6XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 +A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_HLSQ_HS_CNTL = 0x0000b801 +A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff +A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 +A6XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 +A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_HLSQ_DS_CNTL = 0x0000b802 +A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff +A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 +A6XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 +A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_HLSQ_GS_CNTL = 0x0000b803 +A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff +A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 +A6XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 +A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_VS_CNTL = 0x0000a827 +A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff +A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 +A7XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 +A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_HS_CNTL = 0x0000a83f +A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff +A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 +A7XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 +A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_DS_CNTL = 0x0000a867 +A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff +A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 +A7XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 +A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_GS_CNTL = 0x0000a898 +A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff +A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 +A7XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 +A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_FS_UNKNOWN_A9AA = 0x0000a9aa +A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE = 0x00000001 +REG_A7XX_HLSQ_UNKNOWN_A9AC = 0x0000a9ac +REG_A7XX_HLSQ_UNKNOWN_A9AD = 0x0000a9ad +REG_A7XX_HLSQ_UNKNOWN_A9AE = 0x0000a9ae +A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK = 0x000000ff +A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT = 0 +A7XX_HLSQ_UNKNOWN_A9AE_UNK8 = 0x00000100 +A7XX_HLSQ_UNKNOWN_A9AE_UNK9 = 0x00000200 +REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD = 0x0000b820 +REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR = 0x0000b821 +REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA = 0x0000b823 +REG_A6XX_HLSQ_FS_CNTL_0 = 0x0000b980 +A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 +A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 +A6XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 +A6XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc +A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 +REG_A6XX_HLSQ_UNKNOWN_B981 = 0x0000b981 +REG_A6XX_HLSQ_CONTROL_1_REG = 0x0000b982 +A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 +A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 +REG_A6XX_HLSQ_CONTROL_2_REG = 0x0000b983 +A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff +A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 +A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 +A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 +A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 +A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 +A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 +A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 +REG_A6XX_HLSQ_CONTROL_3_REG = 0x0000b984 +A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff +A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 +A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 +A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 +A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 +A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 +A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 +A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 +REG_A6XX_HLSQ_CONTROL_4_REG = 0x0000b985 +A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff +A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 +A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 +A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 +A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 +A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 +A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 +A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 +REG_A6XX_HLSQ_CONTROL_5_REG = 0x0000b986 +A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff +A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 +A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 +A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 +REG_A6XX_HLSQ_CS_CNTL = 0x0000b987 +A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff +A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 +A6XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 +A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_FS_CNTL_0 = 0x0000a9c6 +A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 +A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 +A7XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 +A7XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc +A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 +REG_A7XX_HLSQ_CONTROL_1_REG = 0x0000a9c7 +A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 +A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 +REG_A7XX_HLSQ_CONTROL_2_REG = 0x0000a9c8 +A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff +A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 +A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 +A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 +A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 +A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 +A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 +A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 +REG_A7XX_HLSQ_CONTROL_3_REG = 0x0000a9c9 +A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff +A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 +A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 +A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 +A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 +A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 +A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 +A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 +REG_A7XX_HLSQ_CONTROL_4_REG = 0x0000a9ca +A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff +A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 +A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 +A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 +A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 +A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 +A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 +A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 +REG_A7XX_HLSQ_CONTROL_5_REG = 0x0000a9cb +A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff +A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 +A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 +A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 +REG_A7XX_HLSQ_CS_CNTL = 0x0000a9cd +A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff +A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 +A7XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 +A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_HLSQ_CS_NDRANGE_0 = 0x0000b990 +A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 +A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 +A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc +A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 +A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 +A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 +A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 +A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 +REG_A6XX_HLSQ_CS_NDRANGE_1 = 0x0000b991 +A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff +A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 +REG_A6XX_HLSQ_CS_NDRANGE_2 = 0x0000b992 +A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff +A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 +REG_A6XX_HLSQ_CS_NDRANGE_3 = 0x0000b993 +A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff +A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 +REG_A6XX_HLSQ_CS_NDRANGE_4 = 0x0000b994 +A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff +A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 +REG_A6XX_HLSQ_CS_NDRANGE_5 = 0x0000b995 +A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff +A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 +REG_A6XX_HLSQ_CS_NDRANGE_6 = 0x0000b996 +A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff +A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 +REG_A6XX_HLSQ_CS_CNTL_0 = 0x0000b997 +A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff +A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 +A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 +A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 +A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 +A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 +A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 +A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 +REG_A6XX_HLSQ_CS_CNTL_1 = 0x0000b998 +A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff +A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 +A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 +A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 +A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 +A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 +REG_A6XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000b999 +REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000b99a +REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000b99b +REG_A7XX_HLSQ_CS_NDRANGE_0 = 0x0000a9d4 +A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 +A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 +A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc +A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 +A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 +A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 +A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 +A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 +REG_A7XX_HLSQ_CS_NDRANGE_1 = 0x0000a9d5 +A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff +A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 +REG_A7XX_HLSQ_CS_NDRANGE_2 = 0x0000a9d6 +A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff +A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 +REG_A7XX_HLSQ_CS_NDRANGE_3 = 0x0000a9d7 +A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff +A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 +REG_A7XX_HLSQ_CS_NDRANGE_4 = 0x0000a9d8 +A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff +A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 +REG_A7XX_HLSQ_CS_NDRANGE_5 = 0x0000a9d9 +A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff +A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 +REG_A7XX_HLSQ_CS_NDRANGE_6 = 0x0000a9da +A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff +A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 +REG_A7XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000a9dc +REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000a9dd +REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000a9de +REG_A7XX_HLSQ_CS_CNTL_1 = 0x0000a9db +A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff +A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 +A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 +A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 +A7XX_HLSQ_CS_CNTL_1_UNK11 = 0x00000800 +A7XX_HLSQ_CS_CNTL_1_UNK22 = 0x00400000 +A7XX_HLSQ_CS_CNTL_1_UNK26 = 0x04000000 +A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK = 0x78000000 +A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT = 27 +REG_A7XX_HLSQ_CS_LOCAL_SIZE = 0x0000a9df +A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK = 0x00000ffc +A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT = 2 +A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK = 0x003ff000 +A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT = 12 +A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK = 0xffc00000 +A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT = 22 +REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD = 0x0000b9a0 +REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR = 0x0000b9a1 +REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA = 0x0000b9a3 +REG_A6XX_HLSQ_CS_BINDLESS_BASE = lambda i0: (0x0000b9c0 + 0x2*i0 ) +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 = 0x0000b9d0 +A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK = 0x0000001f +A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT = 0 +A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 = 0x00000020 +A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 = 0x00000040 +REG_A6XX_HLSQ_DRAW_CMD = 0x0000bb00 +A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff +A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 +REG_A6XX_HLSQ_DISPATCH_CMD = 0x0000bb01 +A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff +A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 +REG_A6XX_HLSQ_EVENT_CMD = 0x0000bb02 +A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 +A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 +A6XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f +A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 +REG_A6XX_HLSQ_INVALIDATE_CMD = 0x0000bb08 +A6XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 +A6XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 +A6XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 +A6XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 +A6XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 +A6XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 +A6XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 +A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 +A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST = 0x00080000 +A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST = 0x00000100 +A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x00003e00 +A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 +A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x0007c000 +A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 14 +REG_A7XX_HLSQ_DRAW_CMD = 0x0000ab1c +A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff +A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 +REG_A7XX_HLSQ_DISPATCH_CMD = 0x0000ab1d +A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff +A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 +REG_A7XX_HLSQ_EVENT_CMD = 0x0000ab1e +A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 +A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 +A7XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f +A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 +REG_A7XX_HLSQ_INVALIDATE_CMD = 0x0000ab1f +A7XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 +A7XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 +A7XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 +A7XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 +A7XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 +A7XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 +A7XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 +A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 +A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x0001fe00 +A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 +A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x01fe0000 +A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 17 +REG_A6XX_HLSQ_FS_CNTL = 0x0000bb10 +A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff +A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 +A6XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 +A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_FS_CNTL = 0x0000ab03 +A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff +A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 +A7XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 +A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_HLSQ_SHARED_CONSTS_IMM = lambda i0: (0x0000ab40 + 0x1*i0 ) +REG_A6XX_HLSQ_SHARED_CONSTS = 0x0000bb11 +A6XX_HLSQ_SHARED_CONSTS_ENABLE = 0x00000001 +REG_A6XX_HLSQ_BINDLESS_BASE = lambda i0: (0x0000bb20 + 0x2*i0 ) +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_HLSQ_2D_EVENT_CMD = 0x0000bd80 +A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 +A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT = 8 +A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK = 0x0000007f +A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT = 0 +REG_A6XX_HLSQ_UNKNOWN_BE00 = 0x0000be00 +REG_A6XX_HLSQ_UNKNOWN_BE01 = 0x0000be01 +REG_A6XX_HLSQ_DBG_ECO_CNTL = 0x0000be04 +REG_A6XX_HLSQ_ADDR_MODE_CNTL = 0x0000be05 +REG_A6XX_HLSQ_UNKNOWN_BE08 = 0x0000be08 +REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL = lambda i0: (0x0000be10 + 0x1*i0 ) +REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 +REG_A7XX_SP_AHB_READ_APERTURE = 0x0000c000 +REG_A7XX_SP_UNKNOWN_0CE2 = 0x00000ce2 +REG_A7XX_SP_UNKNOWN_0CE4 = 0x00000ce4 +REG_A7XX_SP_UNKNOWN_0CE6 = 0x00000ce6 +REG_A6XX_CP_EVENT_START = 0x0000d600 +A6XX_CP_EVENT_START_STATE_ID__MASK = 0x000000ff +A6XX_CP_EVENT_START_STATE_ID__SHIFT = 0 +REG_A6XX_CP_EVENT_END = 0x0000d601 +A6XX_CP_EVENT_END_STATE_ID__MASK = 0x000000ff +A6XX_CP_EVENT_END_STATE_ID__SHIFT = 0 +REG_A6XX_CP_2D_EVENT_START = 0x0000d700 +A6XX_CP_2D_EVENT_START_STATE_ID__MASK = 0x000000ff +A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT = 0 +REG_A6XX_CP_2D_EVENT_END = 0x0000d701 +A6XX_CP_2D_EVENT_END_STATE_ID__MASK = 0x000000ff +A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT = 0 +REG_A6XX_TEX_SAMP_0 = 0x00000000 +A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR = 0x00000001 +A6XX_TEX_SAMP_0_XY_MAG__MASK = 0x00000006 +A6XX_TEX_SAMP_0_XY_MAG__SHIFT = 1 +A6XX_TEX_SAMP_0_XY_MIN__MASK = 0x00000018 +A6XX_TEX_SAMP_0_XY_MIN__SHIFT = 3 +A6XX_TEX_SAMP_0_WRAP_S__MASK = 0x000000e0 +A6XX_TEX_SAMP_0_WRAP_S__SHIFT = 5 +A6XX_TEX_SAMP_0_WRAP_T__MASK = 0x00000700 +A6XX_TEX_SAMP_0_WRAP_T__SHIFT = 8 +A6XX_TEX_SAMP_0_WRAP_R__MASK = 0x00003800 +A6XX_TEX_SAMP_0_WRAP_R__SHIFT = 11 +A6XX_TEX_SAMP_0_ANISO__MASK = 0x0001c000 +A6XX_TEX_SAMP_0_ANISO__SHIFT = 14 +A6XX_TEX_SAMP_0_LOD_BIAS__MASK = 0xfff80000 +A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT = 19 +REG_A6XX_TEX_SAMP_1 = 0x00000001 +A6XX_TEX_SAMP_1_CLAMPENABLE = 0x00000001 +A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK = 0x0000000e +A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT = 1 +A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF = 0x00000010 +A6XX_TEX_SAMP_1_UNNORM_COORDS = 0x00000020 +A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR = 0x00000040 +A6XX_TEX_SAMP_1_MAX_LOD__MASK = 0x000fff00 +A6XX_TEX_SAMP_1_MAX_LOD__SHIFT = 8 +A6XX_TEX_SAMP_1_MIN_LOD__MASK = 0xfff00000 +A6XX_TEX_SAMP_1_MIN_LOD__SHIFT = 20 +REG_A6XX_TEX_SAMP_2 = 0x00000002 +A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK = 0x00000003 +A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT = 0 +A6XX_TEX_SAMP_2_CHROMA_LINEAR = 0x00000020 +A6XX_TEX_SAMP_2_BCOLOR__MASK = 0xffffff80 +A6XX_TEX_SAMP_2_BCOLOR__SHIFT = 7 +REG_A6XX_TEX_SAMP_3 = 0x00000003 +REG_A6XX_TEX_CONST_0 = 0x00000000 +A6XX_TEX_CONST_0_TILE_MODE__MASK = 0x00000003 +A6XX_TEX_CONST_0_TILE_MODE__SHIFT = 0 +A6XX_TEX_CONST_0_SRGB = 0x00000004 +A6XX_TEX_CONST_0_SWIZ_X__MASK = 0x00000070 +A6XX_TEX_CONST_0_SWIZ_X__SHIFT = 4 +A6XX_TEX_CONST_0_SWIZ_Y__MASK = 0x00000380 +A6XX_TEX_CONST_0_SWIZ_Y__SHIFT = 7 +A6XX_TEX_CONST_0_SWIZ_Z__MASK = 0x00001c00 +A6XX_TEX_CONST_0_SWIZ_Z__SHIFT = 10 +A6XX_TEX_CONST_0_SWIZ_W__MASK = 0x0000e000 +A6XX_TEX_CONST_0_SWIZ_W__SHIFT = 13 +A6XX_TEX_CONST_0_MIPLVLS__MASK = 0x000f0000 +A6XX_TEX_CONST_0_MIPLVLS__SHIFT = 16 +A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X = 0x00010000 +A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y = 0x00040000 +A6XX_TEX_CONST_0_SAMPLES__MASK = 0x00300000 +A6XX_TEX_CONST_0_SAMPLES__SHIFT = 20 +A6XX_TEX_CONST_0_FMT__MASK = 0x3fc00000 +A6XX_TEX_CONST_0_FMT__SHIFT = 22 +A6XX_TEX_CONST_0_SWAP__MASK = 0xc0000000 +A6XX_TEX_CONST_0_SWAP__SHIFT = 30 +REG_A6XX_TEX_CONST_1 = 0x00000001 +A6XX_TEX_CONST_1_WIDTH__MASK = 0x00007fff +A6XX_TEX_CONST_1_WIDTH__SHIFT = 0 +A6XX_TEX_CONST_1_HEIGHT__MASK = 0x3fff8000 +A6XX_TEX_CONST_1_HEIGHT__SHIFT = 15 +REG_A6XX_TEX_CONST_2 = 0x00000002 +A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK = 0x0000fff0 +A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT = 4 +A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK = 0x003f0000 +A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT = 16 +A6XX_TEX_CONST_2_PITCHALIGN__MASK = 0x0000000f +A6XX_TEX_CONST_2_PITCHALIGN__SHIFT = 0 +A6XX_TEX_CONST_2_PITCH__MASK = 0x1fffff80 +A6XX_TEX_CONST_2_PITCH__SHIFT = 7 +A6XX_TEX_CONST_2_TYPE__MASK = 0xe0000000 +A6XX_TEX_CONST_2_TYPE__SHIFT = 29 +REG_A6XX_TEX_CONST_3 = 0x00000003 +A6XX_TEX_CONST_3_ARRAY_PITCH__MASK = 0x007fffff +A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT = 0 +A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK = 0x07800000 +A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT = 23 +A6XX_TEX_CONST_3_TILE_ALL = 0x08000000 +A6XX_TEX_CONST_3_FLAG = 0x10000000 +REG_A6XX_TEX_CONST_4 = 0x00000004 +A6XX_TEX_CONST_4_BASE_LO__MASK = 0xffffffe0 +A6XX_TEX_CONST_4_BASE_LO__SHIFT = 5 +REG_A6XX_TEX_CONST_5 = 0x00000005 +A6XX_TEX_CONST_5_BASE_HI__MASK = 0x0001ffff +A6XX_TEX_CONST_5_BASE_HI__SHIFT = 0 +A6XX_TEX_CONST_5_DEPTH__MASK = 0x3ffe0000 +A6XX_TEX_CONST_5_DEPTH__SHIFT = 17 +REG_A6XX_TEX_CONST_6 = 0x00000006 +A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK = 0x00000fff +A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT = 0 +A6XX_TEX_CONST_6_PLANE_PITCH__MASK = 0xffffff00 +A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT = 8 +REG_A6XX_TEX_CONST_7 = 0x00000007 +A6XX_TEX_CONST_7_FLAG_LO__MASK = 0xffffffe0 +A6XX_TEX_CONST_7_FLAG_LO__SHIFT = 5 +REG_A6XX_TEX_CONST_8 = 0x00000008 +A6XX_TEX_CONST_8_FLAG_HI__MASK = 0x0001ffff +A6XX_TEX_CONST_8_FLAG_HI__SHIFT = 0 +REG_A6XX_TEX_CONST_9 = 0x00000009 +A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK = 0x0001ffff +A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_TEX_CONST_10 = 0x0000000a +A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK = 0x0000007f +A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT = 0 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK = 0x00000f00 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT = 8 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK = 0x0000f000 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT = 12 +REG_A6XX_TEX_CONST_11 = 0x0000000b +REG_A6XX_TEX_CONST_12 = 0x0000000c +REG_A6XX_TEX_CONST_13 = 0x0000000d +REG_A6XX_TEX_CONST_14 = 0x0000000e +REG_A6XX_TEX_CONST_15 = 0x0000000f +REG_A6XX_UBO_0 = 0x00000000 +A6XX_UBO_0_BASE_LO__MASK = 0xffffffff +A6XX_UBO_0_BASE_LO__SHIFT = 0 +REG_A6XX_UBO_1 = 0x00000001 +A6XX_UBO_1_BASE_HI__MASK = 0x0001ffff +A6XX_UBO_1_BASE_HI__SHIFT = 0 +A6XX_UBO_1_SIZE__MASK = 0xfffe0000 +A6XX_UBO_1_SIZE__SHIFT = 17 +REG_A6XX_PDC_GPU_ENABLE_PDC = 0x00001140 +REG_A6XX_PDC_GPU_SEQ_START_ADDR = 0x00001148 +REG_A6XX_PDC_GPU_TCS0_CONTROL = 0x00001540 +REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK = 0x00001541 +REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK = 0x00001542 +REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID = 0x00001543 +REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR = 0x00001544 +REG_A6XX_PDC_GPU_TCS0_CMD0_DATA = 0x00001545 +REG_A6XX_PDC_GPU_TCS1_CONTROL = 0x00001572 +REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK = 0x00001573 +REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK = 0x00001574 +REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID = 0x00001575 +REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR = 0x00001576 +REG_A6XX_PDC_GPU_TCS1_CMD0_DATA = 0x00001577 +REG_A6XX_PDC_GPU_TCS2_CONTROL = 0x000015a4 +REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK = 0x000015a5 +REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK = 0x000015a6 +REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID = 0x000015a7 +REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR = 0x000015a8 +REG_A6XX_PDC_GPU_TCS2_CMD0_DATA = 0x000015a9 +REG_A6XX_PDC_GPU_TCS3_CONTROL = 0x000015d6 +REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK = 0x000015d7 +REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK = 0x000015d8 +REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID = 0x000015d9 +REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR = 0x000015da +REG_A6XX_PDC_GPU_TCS3_CMD0_DATA = 0x000015db +REG_A6XX_PDC_GPU_SEQ_MEM_0 = 0x00000000 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A = 0x00000000 +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK = 0x000000ff +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK = 0x0000ff00 +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT = 8 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B = 0x00000001 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C = 0x00000002 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D = 0x00000003 +REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT = 0x00000004 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 +REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM = 0x00000005 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000008 +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000009 +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000000a +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000000b +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000000c +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000000d +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000000e +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000000f +REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000010 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 +REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000011 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 +REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000002f +REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000030 +REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 = 0x00000001 +REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 = 0x00000002 +REG_A7XX_CX_MISC_TCM_RET_CNTL = 0x00000039 +REG_A7XX_CX_MISC_SW_FUSE_VALUE = 0x00000400 +A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND = 0x00000001 +A7XX_CX_MISC_SW_FUSE_VALUE_LPAC = 0x00000002 +A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING = 0x00000004 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/__init__.py b/tinygrad/runtime/autogen/am/__init__.py new file mode 100644 index 0000000000..f7c62eee0e --- /dev/null +++ b/tinygrad/runtime/autogen/am/__init__.py @@ -0,0 +1,23 @@ +from tinygrad.runtime.autogen import load, root + +am_src="https://github.com/ROCm/ROCK-Kernel-Driver/archive/ceb12c04e2b5b53ec0779362831f5ee40c4921e4.tar.gz" +AMD="{}/drivers/gpu/drm/amd" +inc = ["-include", "stdint.h"] + +def __getattr__(nm): + match nm: + case "am": return load("am/am", [], [root/f"extra/amdpci/headers/{s}.h" for s in ["v11_structs", "v12_structs", "amdgpu_vm", "discovery", + "amdgpu_ucode", "psp_gfx_if", "amdgpu_psp", "amdgpu_irq", "amdgpu_doorbell"]]+[f"{AMD}/include/soc15_ih_clientid.h"], args=inc, tarball=am_src) + case "pm4_soc15": return load("am/pm4_soc15", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/soc15d.h"], tarball=am_src) + case "pm4_nv": return load("am/pm4_nv", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/nvd.h"], tarball=am_src) + case "sdma_4_0_0": return load("am/sdma_4_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/vega10_sdma_pkt_open.h"], + args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src), + case "sdma_5_0_0": return load("am/sdma_5_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/navi10_sdma_pkt_open.h"], + args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src), + case "sdma_6_0_0": return load("am/sdma_6_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}//amdgpu/sdma_v6_0_0_pkt_open.h"], + args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src), + case "smu_v13_0_0": return load("am/smu_v13_0_0",[],[f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_0_ppsmc","smu13_driver_if_v13_0_0"]] + +[root/"extra/amdpci/headers/amdgpu_smu.h"], tarball=am_src), + case "smu_v14_0_2": return load("am/smu_v14_0_2", [], [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v14_0_0_pmfw", "smu_v14_0_2_ppsmc", + "smu14_driver_if_v14_0"]]+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, tarball=am_src) + case _: raise AttributeError(f"no such autogen: {nm}") diff --git a/tinygrad/runtime/autogen/am/am.py b/tinygrad/runtime/autogen/am/am.py index cad89c6925..37e881205c 100644 --- a/tinygrad/runtime/autogen/am/am.py +++ b/tinygrad/runtime/autogen/am/am.py @@ -1,5863 +1,4136 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-include', 'stdint.h'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -V11_STRUCTS_H_ = True # macro -uint32_t = True # macro -uint8_t = True # macro -uint16_t = True # macro -uint64_t = True # macro -class struct_v11_gfx_mqd(Structure): - pass - -struct_v11_gfx_mqd._pack_ = 1 # source:False +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class struct_v11_gfx_mqd(Struct): pass struct_v11_gfx_mqd._fields_ = [ - ('shadow_base_lo', ctypes.c_uint32), - ('shadow_base_hi', ctypes.c_uint32), - ('gds_bkup_base_lo', ctypes.c_uint32), - ('gds_bkup_base_hi', ctypes.c_uint32), - ('fw_work_area_base_lo', ctypes.c_uint32), - ('fw_work_area_base_hi', ctypes.c_uint32), - ('shadow_initialized', ctypes.c_uint32), - ('ib_vmid', ctypes.c_uint32), - ('reserved_8', ctypes.c_uint32), - ('reserved_9', ctypes.c_uint32), - ('reserved_10', ctypes.c_uint32), - ('reserved_11', ctypes.c_uint32), - ('reserved_12', ctypes.c_uint32), - ('reserved_13', ctypes.c_uint32), - ('reserved_14', ctypes.c_uint32), - ('reserved_15', ctypes.c_uint32), - ('reserved_16', ctypes.c_uint32), - ('reserved_17', ctypes.c_uint32), - ('reserved_18', ctypes.c_uint32), - ('reserved_19', ctypes.c_uint32), - ('reserved_20', ctypes.c_uint32), - ('reserved_21', ctypes.c_uint32), - ('reserved_22', ctypes.c_uint32), - ('reserved_23', ctypes.c_uint32), - ('reserved_24', ctypes.c_uint32), - ('reserved_25', ctypes.c_uint32), - ('reserved_26', ctypes.c_uint32), - ('reserved_27', ctypes.c_uint32), - ('reserved_28', ctypes.c_uint32), - ('reserved_29', ctypes.c_uint32), - ('reserved_30', ctypes.c_uint32), - ('reserved_31', ctypes.c_uint32), - ('reserved_32', ctypes.c_uint32), - ('reserved_33', ctypes.c_uint32), - ('reserved_34', ctypes.c_uint32), - ('reserved_35', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('reserved_37', ctypes.c_uint32), - ('reserved_38', ctypes.c_uint32), - ('reserved_39', ctypes.c_uint32), - ('reserved_40', ctypes.c_uint32), - ('reserved_41', ctypes.c_uint32), - ('reserved_42', ctypes.c_uint32), - ('reserved_43', ctypes.c_uint32), - ('reserved_44', ctypes.c_uint32), - ('reserved_45', ctypes.c_uint32), - ('reserved_46', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('checksum_lo', ctypes.c_uint32), - ('checksum_hi', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('cp_mqd_query_wave_count', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_offset', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('control_buf_addr_lo', ctypes.c_uint32), - ('control_buf_addr_hi', ctypes.c_uint32), - ('disable_queue', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_gfx_hqd_active', ctypes.c_uint32), - ('cp_gfx_hqd_vmid', ctypes.c_uint32), - ('reserved_131', ctypes.c_uint32), - ('reserved_132', ctypes.c_uint32), - ('cp_gfx_hqd_queue_priority', ctypes.c_uint32), - ('cp_gfx_hqd_quantum', ctypes.c_uint32), - ('cp_gfx_hqd_base', ctypes.c_uint32), - ('cp_gfx_hqd_base_hi', ctypes.c_uint32), - ('cp_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr_hi', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_rb_doorbell_control', ctypes.c_uint32), - ('cp_gfx_hqd_offset', ctypes.c_uint32), - ('cp_gfx_hqd_cntl', ctypes.c_uint32), - ('reserved_146', ctypes.c_uint32), - ('reserved_147', ctypes.c_uint32), - ('cp_gfx_hqd_csmd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr_hi', ctypes.c_uint32), - ('reserved_151', ctypes.c_uint32), - ('reserved_152', ctypes.c_uint32), - ('reserved_153', ctypes.c_uint32), - ('reserved_154', ctypes.c_uint32), - ('reserved_155', ctypes.c_uint32), - ('cp_gfx_hqd_mapped', ctypes.c_uint32), - ('cp_gfx_hqd_que_mgr_control', ctypes.c_uint32), - ('reserved_158', ctypes.c_uint32), - ('reserved_159', ctypes.c_uint32), - ('cp_gfx_hqd_hq_status0', ctypes.c_uint32), - ('cp_gfx_hqd_hq_control0', ctypes.c_uint32), - ('cp_gfx_mqd_control', ctypes.c_uint32), - ('reserved_163', ctypes.c_uint32), - ('reserved_164', ctypes.c_uint32), - ('reserved_165', ctypes.c_uint32), - ('reserved_166', ctypes.c_uint32), - ('reserved_167', ctypes.c_uint32), - ('reserved_168', ctypes.c_uint32), - ('reserved_169', ctypes.c_uint32), - ('cp_num_prim_needed_count0_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count0_hi', ctypes.c_uint32), - ('cp_num_prim_needed_count1_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count1_hi', ctypes.c_uint32), - ('cp_num_prim_needed_count2_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count2_hi', ctypes.c_uint32), - ('cp_num_prim_needed_count3_lo', ctypes.c_uint32), - ('cp_num_prim_needed_count3_hi', ctypes.c_uint32), - ('cp_num_prim_written_count0_lo', ctypes.c_uint32), - ('cp_num_prim_written_count0_hi', ctypes.c_uint32), - ('cp_num_prim_written_count1_lo', ctypes.c_uint32), - ('cp_num_prim_written_count1_hi', ctypes.c_uint32), - ('cp_num_prim_written_count2_lo', ctypes.c_uint32), - ('cp_num_prim_written_count2_hi', ctypes.c_uint32), - ('cp_num_prim_written_count3_lo', ctypes.c_uint32), - ('cp_num_prim_written_count3_hi', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('mp1_smn_fps_cnt', ctypes.c_uint32), - ('sq_thread_trace_buf0_base', ctypes.c_uint32), - ('sq_thread_trace_buf0_size', ctypes.c_uint32), - ('sq_thread_trace_buf1_base', ctypes.c_uint32), - ('sq_thread_trace_buf1_size', ctypes.c_uint32), - ('sq_thread_trace_wptr', ctypes.c_uint32), - ('sq_thread_trace_mask', ctypes.c_uint32), - ('sq_thread_trace_token_mask', ctypes.c_uint32), - ('sq_thread_trace_ctrl', ctypes.c_uint32), - ('sq_thread_trace_status', ctypes.c_uint32), - ('sq_thread_trace_dropped_cntr', ctypes.c_uint32), - ('sq_thread_trace_finish_done_debug', ctypes.c_uint32), - ('sq_thread_trace_gfx_draw_cntr', ctypes.c_uint32), - ('sq_thread_trace_gfx_marker_cntr', ctypes.c_uint32), - ('sq_thread_trace_hp3d_draw_cntr', ctypes.c_uint32), - ('sq_thread_trace_hp3d_marker_cntr', ctypes.c_uint32), - ('reserved_206', ctypes.c_uint32), - ('reserved_207', ctypes.c_uint32), - ('cp_sc_psinvoc_count0_lo', ctypes.c_uint32), - ('cp_sc_psinvoc_count0_hi', ctypes.c_uint32), - ('cp_pa_cprim_count_lo', ctypes.c_uint32), - ('cp_pa_cprim_count_hi', ctypes.c_uint32), - ('cp_pa_cinvoc_count_lo', ctypes.c_uint32), - ('cp_pa_cinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_vsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_vsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_gsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_gsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_gsprim_count_lo', ctypes.c_uint32), - ('cp_vgt_gsprim_count_hi', ctypes.c_uint32), - ('cp_vgt_iaprim_count_lo', ctypes.c_uint32), - ('cp_vgt_iaprim_count_hi', ctypes.c_uint32), - ('cp_vgt_iavert_count_lo', ctypes.c_uint32), - ('cp_vgt_iavert_count_hi', ctypes.c_uint32), - ('cp_vgt_hsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_hsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_dsinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_dsinvoc_count_hi', ctypes.c_uint32), - ('cp_vgt_csinvoc_count_lo', ctypes.c_uint32), - ('cp_vgt_csinvoc_count_hi', ctypes.c_uint32), - ('reserved_230', ctypes.c_uint32), - ('reserved_231', ctypes.c_uint32), - ('reserved_232', ctypes.c_uint32), - ('reserved_233', ctypes.c_uint32), - ('reserved_234', ctypes.c_uint32), - ('reserved_235', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('reserved_240', ctypes.c_uint32), - ('reserved_241', ctypes.c_uint32), - ('reserved_242', ctypes.c_uint32), - ('reserved_243', ctypes.c_uint32), - ('reserved_244', ctypes.c_uint32), - ('reserved_245', ctypes.c_uint32), - ('reserved_246', ctypes.c_uint32), - ('reserved_247', ctypes.c_uint32), - ('reserved_248', ctypes.c_uint32), - ('reserved_249', ctypes.c_uint32), - ('reserved_250', ctypes.c_uint32), - ('reserved_251', ctypes.c_uint32), - ('reserved_252', ctypes.c_uint32), - ('reserved_253', ctypes.c_uint32), - ('reserved_254', ctypes.c_uint32), - ('reserved_255', ctypes.c_uint32), - ('reserved_256', ctypes.c_uint32), - ('reserved_257', ctypes.c_uint32), - ('reserved_258', ctypes.c_uint32), - ('reserved_259', ctypes.c_uint32), - ('reserved_260', ctypes.c_uint32), - ('reserved_261', ctypes.c_uint32), - ('reserved_262', ctypes.c_uint32), - ('reserved_263', ctypes.c_uint32), - ('reserved_264', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_0', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_1', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_2', ctypes.c_uint32), - ('vgt_strmout_buffer_filled_size_3', ctypes.c_uint32), - ('reserved_272', ctypes.c_uint32), - ('reserved_273', ctypes.c_uint32), - ('reserved_274', ctypes.c_uint32), - ('reserved_275', ctypes.c_uint32), - ('vgt_dma_max_size', ctypes.c_uint32), - ('vgt_dma_num_instances', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('it_set_base_ib_addr_lo', ctypes.c_uint32), - ('it_set_base_ib_addr_hi', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - ('reserved_342', ctypes.c_uint32), - ('reserved_343', ctypes.c_uint32), - ('reserved_344', ctypes.c_uint32), - ('reserved_345', ctypes.c_uint32), - ('reserved_346', ctypes.c_uint32), - ('reserved_347', ctypes.c_uint32), - ('reserved_348', ctypes.c_uint32), - ('reserved_349', ctypes.c_uint32), - ('reserved_350', ctypes.c_uint32), - ('reserved_351', ctypes.c_uint32), - ('reserved_352', ctypes.c_uint32), - ('reserved_353', ctypes.c_uint32), - ('reserved_354', ctypes.c_uint32), - ('reserved_355', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_ps', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_vs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_gs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc3_hs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_ps', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_vs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_gs', ctypes.c_uint32), - ('spi_shader_pgm_rsrc4_hs', ctypes.c_uint32), - ('db_occlusion_count0_low_00', ctypes.c_uint32), - ('db_occlusion_count0_hi_00', ctypes.c_uint32), - ('db_occlusion_count1_low_00', ctypes.c_uint32), - ('db_occlusion_count1_hi_00', ctypes.c_uint32), - ('db_occlusion_count2_low_00', ctypes.c_uint32), - ('db_occlusion_count2_hi_00', ctypes.c_uint32), - ('db_occlusion_count3_low_00', ctypes.c_uint32), - ('db_occlusion_count3_hi_00', ctypes.c_uint32), - ('db_occlusion_count0_low_01', ctypes.c_uint32), - ('db_occlusion_count0_hi_01', ctypes.c_uint32), - ('db_occlusion_count1_low_01', ctypes.c_uint32), - ('db_occlusion_count1_hi_01', ctypes.c_uint32), - ('db_occlusion_count2_low_01', ctypes.c_uint32), - ('db_occlusion_count2_hi_01', ctypes.c_uint32), - ('db_occlusion_count3_low_01', ctypes.c_uint32), - ('db_occlusion_count3_hi_01', ctypes.c_uint32), - ('db_occlusion_count0_low_02', ctypes.c_uint32), - ('db_occlusion_count0_hi_02', ctypes.c_uint32), - ('db_occlusion_count1_low_02', ctypes.c_uint32), - ('db_occlusion_count1_hi_02', ctypes.c_uint32), - ('db_occlusion_count2_low_02', ctypes.c_uint32), - ('db_occlusion_count2_hi_02', ctypes.c_uint32), - ('db_occlusion_count3_low_02', ctypes.c_uint32), - ('db_occlusion_count3_hi_02', ctypes.c_uint32), - ('db_occlusion_count0_low_03', ctypes.c_uint32), - ('db_occlusion_count0_hi_03', ctypes.c_uint32), - ('db_occlusion_count1_low_03', ctypes.c_uint32), - ('db_occlusion_count1_hi_03', ctypes.c_uint32), - ('db_occlusion_count2_low_03', ctypes.c_uint32), - ('db_occlusion_count2_hi_03', ctypes.c_uint32), - ('db_occlusion_count3_low_03', ctypes.c_uint32), - ('db_occlusion_count3_hi_03', ctypes.c_uint32), - ('db_occlusion_count0_low_04', ctypes.c_uint32), - ('db_occlusion_count0_hi_04', ctypes.c_uint32), - ('db_occlusion_count1_low_04', ctypes.c_uint32), - ('db_occlusion_count1_hi_04', ctypes.c_uint32), - ('db_occlusion_count2_low_04', ctypes.c_uint32), - ('db_occlusion_count2_hi_04', ctypes.c_uint32), - ('db_occlusion_count3_low_04', ctypes.c_uint32), - ('db_occlusion_count3_hi_04', ctypes.c_uint32), - ('db_occlusion_count0_low_05', ctypes.c_uint32), - ('db_occlusion_count0_hi_05', ctypes.c_uint32), - ('db_occlusion_count1_low_05', ctypes.c_uint32), - ('db_occlusion_count1_hi_05', ctypes.c_uint32), - ('db_occlusion_count2_low_05', ctypes.c_uint32), - ('db_occlusion_count2_hi_05', ctypes.c_uint32), - ('db_occlusion_count3_low_05', ctypes.c_uint32), - ('db_occlusion_count3_hi_05', ctypes.c_uint32), - ('db_occlusion_count0_low_06', ctypes.c_uint32), - ('db_occlusion_count0_hi_06', ctypes.c_uint32), - ('db_occlusion_count1_low_06', ctypes.c_uint32), - ('db_occlusion_count1_hi_06', ctypes.c_uint32), - ('db_occlusion_count2_low_06', ctypes.c_uint32), - ('db_occlusion_count2_hi_06', ctypes.c_uint32), - ('db_occlusion_count3_low_06', ctypes.c_uint32), - ('db_occlusion_count3_hi_06', ctypes.c_uint32), - ('db_occlusion_count0_low_07', ctypes.c_uint32), - ('db_occlusion_count0_hi_07', ctypes.c_uint32), - ('db_occlusion_count1_low_07', ctypes.c_uint32), - ('db_occlusion_count1_hi_07', ctypes.c_uint32), - ('db_occlusion_count2_low_07', ctypes.c_uint32), - ('db_occlusion_count2_hi_07', ctypes.c_uint32), - ('db_occlusion_count3_low_07', ctypes.c_uint32), - ('db_occlusion_count3_hi_07', ctypes.c_uint32), - ('db_occlusion_count0_low_10', ctypes.c_uint32), - ('db_occlusion_count0_hi_10', ctypes.c_uint32), - ('db_occlusion_count1_low_10', ctypes.c_uint32), - ('db_occlusion_count1_hi_10', ctypes.c_uint32), - ('db_occlusion_count2_low_10', ctypes.c_uint32), - ('db_occlusion_count2_hi_10', ctypes.c_uint32), - ('db_occlusion_count3_low_10', ctypes.c_uint32), - ('db_occlusion_count3_hi_10', ctypes.c_uint32), - ('db_occlusion_count0_low_11', ctypes.c_uint32), - ('db_occlusion_count0_hi_11', ctypes.c_uint32), - ('db_occlusion_count1_low_11', ctypes.c_uint32), - ('db_occlusion_count1_hi_11', ctypes.c_uint32), - ('db_occlusion_count2_low_11', ctypes.c_uint32), - ('db_occlusion_count2_hi_11', ctypes.c_uint32), - ('db_occlusion_count3_low_11', ctypes.c_uint32), - ('db_occlusion_count3_hi_11', ctypes.c_uint32), - ('db_occlusion_count0_low_12', ctypes.c_uint32), - ('db_occlusion_count0_hi_12', ctypes.c_uint32), - ('db_occlusion_count1_low_12', ctypes.c_uint32), - ('db_occlusion_count1_hi_12', ctypes.c_uint32), - ('db_occlusion_count2_low_12', ctypes.c_uint32), - ('db_occlusion_count2_hi_12', ctypes.c_uint32), - ('db_occlusion_count3_low_12', ctypes.c_uint32), - ('db_occlusion_count3_hi_12', ctypes.c_uint32), - ('db_occlusion_count0_low_13', ctypes.c_uint32), - ('db_occlusion_count0_hi_13', ctypes.c_uint32), - ('db_occlusion_count1_low_13', ctypes.c_uint32), - ('db_occlusion_count1_hi_13', ctypes.c_uint32), - ('db_occlusion_count2_low_13', ctypes.c_uint32), - ('db_occlusion_count2_hi_13', ctypes.c_uint32), - ('db_occlusion_count3_low_13', ctypes.c_uint32), - ('db_occlusion_count3_hi_13', ctypes.c_uint32), - ('db_occlusion_count0_low_14', ctypes.c_uint32), - ('db_occlusion_count0_hi_14', ctypes.c_uint32), - ('db_occlusion_count1_low_14', ctypes.c_uint32), - ('db_occlusion_count1_hi_14', ctypes.c_uint32), - ('db_occlusion_count2_low_14', ctypes.c_uint32), - ('db_occlusion_count2_hi_14', ctypes.c_uint32), - ('db_occlusion_count3_low_14', ctypes.c_uint32), - ('db_occlusion_count3_hi_14', ctypes.c_uint32), - ('db_occlusion_count0_low_15', ctypes.c_uint32), - ('db_occlusion_count0_hi_15', ctypes.c_uint32), - ('db_occlusion_count1_low_15', ctypes.c_uint32), - ('db_occlusion_count1_hi_15', ctypes.c_uint32), - ('db_occlusion_count2_low_15', ctypes.c_uint32), - ('db_occlusion_count2_hi_15', ctypes.c_uint32), - ('db_occlusion_count3_low_15', ctypes.c_uint32), - ('db_occlusion_count3_hi_15', ctypes.c_uint32), - ('db_occlusion_count0_low_16', ctypes.c_uint32), - ('db_occlusion_count0_hi_16', ctypes.c_uint32), - ('db_occlusion_count1_low_16', ctypes.c_uint32), - ('db_occlusion_count1_hi_16', ctypes.c_uint32), - ('db_occlusion_count2_low_16', ctypes.c_uint32), - ('db_occlusion_count2_hi_16', ctypes.c_uint32), - ('db_occlusion_count3_low_16', ctypes.c_uint32), - ('db_occlusion_count3_hi_16', ctypes.c_uint32), - ('db_occlusion_count0_low_17', ctypes.c_uint32), - ('db_occlusion_count0_hi_17', ctypes.c_uint32), - ('db_occlusion_count1_low_17', ctypes.c_uint32), - ('db_occlusion_count1_hi_17', ctypes.c_uint32), - ('db_occlusion_count2_low_17', ctypes.c_uint32), - ('db_occlusion_count2_hi_17', ctypes.c_uint32), - ('db_occlusion_count3_low_17', ctypes.c_uint32), - ('db_occlusion_count3_hi_17', ctypes.c_uint32), - ('reserved_492', ctypes.c_uint32), - ('reserved_493', ctypes.c_uint32), - ('reserved_494', ctypes.c_uint32), - ('reserved_495', ctypes.c_uint32), - ('reserved_496', ctypes.c_uint32), - ('reserved_497', ctypes.c_uint32), - ('reserved_498', ctypes.c_uint32), - ('reserved_499', ctypes.c_uint32), - ('reserved_500', ctypes.c_uint32), - ('reserved_501', ctypes.c_uint32), - ('reserved_502', ctypes.c_uint32), - ('reserved_503', ctypes.c_uint32), - ('reserved_504', ctypes.c_uint32), - ('reserved_505', ctypes.c_uint32), - ('reserved_506', ctypes.c_uint32), - ('reserved_507', ctypes.c_uint32), - ('reserved_508', ctypes.c_uint32), - ('reserved_509', ctypes.c_uint32), - ('reserved_510', ctypes.c_uint32), - ('reserved_511', ctypes.c_uint32), + ('shadow_base_lo', ctypes.c_uint32), + ('shadow_base_hi', ctypes.c_uint32), + ('gds_bkup_base_lo', ctypes.c_uint32), + ('gds_bkup_base_hi', ctypes.c_uint32), + ('fw_work_area_base_lo', ctypes.c_uint32), + ('fw_work_area_base_hi', ctypes.c_uint32), + ('shadow_initialized', ctypes.c_uint32), + ('ib_vmid', ctypes.c_uint32), + ('reserved_8', ctypes.c_uint32), + ('reserved_9', ctypes.c_uint32), + ('reserved_10', ctypes.c_uint32), + ('reserved_11', ctypes.c_uint32), + ('reserved_12', ctypes.c_uint32), + ('reserved_13', ctypes.c_uint32), + ('reserved_14', ctypes.c_uint32), + ('reserved_15', ctypes.c_uint32), + ('reserved_16', ctypes.c_uint32), + ('reserved_17', ctypes.c_uint32), + ('reserved_18', ctypes.c_uint32), + ('reserved_19', ctypes.c_uint32), + ('reserved_20', ctypes.c_uint32), + ('reserved_21', ctypes.c_uint32), + ('reserved_22', ctypes.c_uint32), + ('reserved_23', ctypes.c_uint32), + ('reserved_24', ctypes.c_uint32), + ('reserved_25', ctypes.c_uint32), + ('reserved_26', ctypes.c_uint32), + ('reserved_27', ctypes.c_uint32), + ('reserved_28', ctypes.c_uint32), + ('reserved_29', ctypes.c_uint32), + ('reserved_30', ctypes.c_uint32), + ('reserved_31', ctypes.c_uint32), + ('reserved_32', ctypes.c_uint32), + ('reserved_33', ctypes.c_uint32), + ('reserved_34', ctypes.c_uint32), + ('reserved_35', ctypes.c_uint32), + ('reserved_36', ctypes.c_uint32), + ('reserved_37', ctypes.c_uint32), + ('reserved_38', ctypes.c_uint32), + ('reserved_39', ctypes.c_uint32), + ('reserved_40', ctypes.c_uint32), + ('reserved_41', ctypes.c_uint32), + ('reserved_42', ctypes.c_uint32), + ('reserved_43', ctypes.c_uint32), + ('reserved_44', ctypes.c_uint32), + ('reserved_45', ctypes.c_uint32), + ('reserved_46', ctypes.c_uint32), + ('reserved_47', ctypes.c_uint32), + ('reserved_48', ctypes.c_uint32), + ('reserved_49', ctypes.c_uint32), + ('reserved_50', ctypes.c_uint32), + ('reserved_51', ctypes.c_uint32), + ('reserved_52', ctypes.c_uint32), + ('reserved_53', ctypes.c_uint32), + ('reserved_54', ctypes.c_uint32), + ('reserved_55', ctypes.c_uint32), + ('reserved_56', ctypes.c_uint32), + ('reserved_57', ctypes.c_uint32), + ('reserved_58', ctypes.c_uint32), + ('reserved_59', ctypes.c_uint32), + ('reserved_60', ctypes.c_uint32), + ('reserved_61', ctypes.c_uint32), + ('reserved_62', ctypes.c_uint32), + ('reserved_63', ctypes.c_uint32), + ('reserved_64', ctypes.c_uint32), + ('reserved_65', ctypes.c_uint32), + ('reserved_66', ctypes.c_uint32), + ('reserved_67', ctypes.c_uint32), + ('reserved_68', ctypes.c_uint32), + ('reserved_69', ctypes.c_uint32), + ('reserved_70', ctypes.c_uint32), + ('reserved_71', ctypes.c_uint32), + ('reserved_72', ctypes.c_uint32), + ('reserved_73', ctypes.c_uint32), + ('reserved_74', ctypes.c_uint32), + ('reserved_75', ctypes.c_uint32), + ('reserved_76', ctypes.c_uint32), + ('reserved_77', ctypes.c_uint32), + ('reserved_78', ctypes.c_uint32), + ('reserved_79', ctypes.c_uint32), + ('reserved_80', ctypes.c_uint32), + ('reserved_81', ctypes.c_uint32), + ('reserved_82', ctypes.c_uint32), + ('reserved_83', ctypes.c_uint32), + ('checksum_lo', ctypes.c_uint32), + ('checksum_hi', ctypes.c_uint32), + ('cp_mqd_query_time_lo', ctypes.c_uint32), + ('cp_mqd_query_time_hi', ctypes.c_uint32), + ('reserved_88', ctypes.c_uint32), + ('reserved_89', ctypes.c_uint32), + ('reserved_90', ctypes.c_uint32), + ('reserved_91', ctypes.c_uint32), + ('cp_mqd_query_wave_count', ctypes.c_uint32), + ('cp_mqd_query_gfx_hqd_rptr', ctypes.c_uint32), + ('cp_mqd_query_gfx_hqd_wptr', ctypes.c_uint32), + ('cp_mqd_query_gfx_hqd_offset', ctypes.c_uint32), + ('reserved_96', ctypes.c_uint32), + ('reserved_97', ctypes.c_uint32), + ('reserved_98', ctypes.c_uint32), + ('reserved_99', ctypes.c_uint32), + ('reserved_100', ctypes.c_uint32), + ('reserved_101', ctypes.c_uint32), + ('reserved_102', ctypes.c_uint32), + ('reserved_103', ctypes.c_uint32), + ('control_buf_addr_lo', ctypes.c_uint32), + ('control_buf_addr_hi', ctypes.c_uint32), + ('disable_queue', ctypes.c_uint32), + ('reserved_107', ctypes.c_uint32), + ('reserved_108', ctypes.c_uint32), + ('reserved_109', ctypes.c_uint32), + ('reserved_110', ctypes.c_uint32), + ('reserved_111', ctypes.c_uint32), + ('reserved_112', ctypes.c_uint32), + ('reserved_113', ctypes.c_uint32), + ('reserved_114', ctypes.c_uint32), + ('reserved_115', ctypes.c_uint32), + ('reserved_116', ctypes.c_uint32), + ('reserved_117', ctypes.c_uint32), + ('reserved_118', ctypes.c_uint32), + ('reserved_119', ctypes.c_uint32), + ('reserved_120', ctypes.c_uint32), + ('reserved_121', ctypes.c_uint32), + ('reserved_122', ctypes.c_uint32), + ('reserved_123', ctypes.c_uint32), + ('reserved_124', ctypes.c_uint32), + ('reserved_125', ctypes.c_uint32), + ('reserved_126', ctypes.c_uint32), + ('reserved_127', ctypes.c_uint32), + ('cp_mqd_base_addr', ctypes.c_uint32), + ('cp_mqd_base_addr_hi', ctypes.c_uint32), + ('cp_gfx_hqd_active', ctypes.c_uint32), + ('cp_gfx_hqd_vmid', ctypes.c_uint32), + ('reserved_131', ctypes.c_uint32), + ('reserved_132', ctypes.c_uint32), + ('cp_gfx_hqd_queue_priority', ctypes.c_uint32), + ('cp_gfx_hqd_quantum', ctypes.c_uint32), + ('cp_gfx_hqd_base', ctypes.c_uint32), + ('cp_gfx_hqd_base_hi', ctypes.c_uint32), + ('cp_gfx_hqd_rptr', ctypes.c_uint32), + ('cp_gfx_hqd_rptr_addr', ctypes.c_uint32), + ('cp_gfx_hqd_rptr_addr_hi', ctypes.c_uint32), + ('cp_rb_wptr_poll_addr_lo', ctypes.c_uint32), + ('cp_rb_wptr_poll_addr_hi', ctypes.c_uint32), + ('cp_rb_doorbell_control', ctypes.c_uint32), + ('cp_gfx_hqd_offset', ctypes.c_uint32), + ('cp_gfx_hqd_cntl', ctypes.c_uint32), + ('reserved_146', ctypes.c_uint32), + ('reserved_147', ctypes.c_uint32), + ('cp_gfx_hqd_csmd_rptr', ctypes.c_uint32), + ('cp_gfx_hqd_wptr', ctypes.c_uint32), + ('cp_gfx_hqd_wptr_hi', ctypes.c_uint32), + ('reserved_151', ctypes.c_uint32), + ('reserved_152', ctypes.c_uint32), + ('reserved_153', ctypes.c_uint32), + ('reserved_154', ctypes.c_uint32), + ('reserved_155', ctypes.c_uint32), + ('cp_gfx_hqd_mapped', ctypes.c_uint32), + ('cp_gfx_hqd_que_mgr_control', ctypes.c_uint32), + ('reserved_158', ctypes.c_uint32), + ('reserved_159', ctypes.c_uint32), + ('cp_gfx_hqd_hq_status0', ctypes.c_uint32), + ('cp_gfx_hqd_hq_control0', ctypes.c_uint32), + ('cp_gfx_mqd_control', ctypes.c_uint32), + ('reserved_163', ctypes.c_uint32), + ('reserved_164', ctypes.c_uint32), + ('reserved_165', ctypes.c_uint32), + ('reserved_166', ctypes.c_uint32), + ('reserved_167', ctypes.c_uint32), + ('reserved_168', ctypes.c_uint32), + ('reserved_169', ctypes.c_uint32), + ('cp_num_prim_needed_count0_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count0_hi', ctypes.c_uint32), + ('cp_num_prim_needed_count1_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count1_hi', ctypes.c_uint32), + ('cp_num_prim_needed_count2_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count2_hi', ctypes.c_uint32), + ('cp_num_prim_needed_count3_lo', ctypes.c_uint32), + ('cp_num_prim_needed_count3_hi', ctypes.c_uint32), + ('cp_num_prim_written_count0_lo', ctypes.c_uint32), + ('cp_num_prim_written_count0_hi', ctypes.c_uint32), + ('cp_num_prim_written_count1_lo', ctypes.c_uint32), + ('cp_num_prim_written_count1_hi', ctypes.c_uint32), + ('cp_num_prim_written_count2_lo', ctypes.c_uint32), + ('cp_num_prim_written_count2_hi', ctypes.c_uint32), + ('cp_num_prim_written_count3_lo', ctypes.c_uint32), + ('cp_num_prim_written_count3_hi', ctypes.c_uint32), + ('reserved_186', ctypes.c_uint32), + ('reserved_187', ctypes.c_uint32), + ('reserved_188', ctypes.c_uint32), + ('reserved_189', ctypes.c_uint32), + ('mp1_smn_fps_cnt', ctypes.c_uint32), + ('sq_thread_trace_buf0_base', ctypes.c_uint32), + ('sq_thread_trace_buf0_size', ctypes.c_uint32), + ('sq_thread_trace_buf1_base', ctypes.c_uint32), + ('sq_thread_trace_buf1_size', ctypes.c_uint32), + ('sq_thread_trace_wptr', ctypes.c_uint32), + ('sq_thread_trace_mask', ctypes.c_uint32), + ('sq_thread_trace_token_mask', ctypes.c_uint32), + ('sq_thread_trace_ctrl', ctypes.c_uint32), + ('sq_thread_trace_status', ctypes.c_uint32), + ('sq_thread_trace_dropped_cntr', ctypes.c_uint32), + ('sq_thread_trace_finish_done_debug', ctypes.c_uint32), + ('sq_thread_trace_gfx_draw_cntr', ctypes.c_uint32), + ('sq_thread_trace_gfx_marker_cntr', ctypes.c_uint32), + ('sq_thread_trace_hp3d_draw_cntr', ctypes.c_uint32), + ('sq_thread_trace_hp3d_marker_cntr', ctypes.c_uint32), + ('reserved_206', ctypes.c_uint32), + ('reserved_207', ctypes.c_uint32), + ('cp_sc_psinvoc_count0_lo', ctypes.c_uint32), + ('cp_sc_psinvoc_count0_hi', ctypes.c_uint32), + ('cp_pa_cprim_count_lo', ctypes.c_uint32), + ('cp_pa_cprim_count_hi', ctypes.c_uint32), + ('cp_pa_cinvoc_count_lo', ctypes.c_uint32), + ('cp_pa_cinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_vsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_vsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_gsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_gsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_gsprim_count_lo', ctypes.c_uint32), + ('cp_vgt_gsprim_count_hi', ctypes.c_uint32), + ('cp_vgt_iaprim_count_lo', ctypes.c_uint32), + ('cp_vgt_iaprim_count_hi', ctypes.c_uint32), + ('cp_vgt_iavert_count_lo', ctypes.c_uint32), + ('cp_vgt_iavert_count_hi', ctypes.c_uint32), + ('cp_vgt_hsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_hsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_dsinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_dsinvoc_count_hi', ctypes.c_uint32), + ('cp_vgt_csinvoc_count_lo', ctypes.c_uint32), + ('cp_vgt_csinvoc_count_hi', ctypes.c_uint32), + ('reserved_230', ctypes.c_uint32), + ('reserved_231', ctypes.c_uint32), + ('reserved_232', ctypes.c_uint32), + ('reserved_233', ctypes.c_uint32), + ('reserved_234', ctypes.c_uint32), + ('reserved_235', ctypes.c_uint32), + ('reserved_236', ctypes.c_uint32), + ('reserved_237', ctypes.c_uint32), + ('reserved_238', ctypes.c_uint32), + ('reserved_239', ctypes.c_uint32), + ('reserved_240', ctypes.c_uint32), + ('reserved_241', ctypes.c_uint32), + ('reserved_242', ctypes.c_uint32), + ('reserved_243', ctypes.c_uint32), + ('reserved_244', ctypes.c_uint32), + ('reserved_245', ctypes.c_uint32), + ('reserved_246', ctypes.c_uint32), + ('reserved_247', ctypes.c_uint32), + ('reserved_248', ctypes.c_uint32), + ('reserved_249', ctypes.c_uint32), + ('reserved_250', ctypes.c_uint32), + ('reserved_251', ctypes.c_uint32), + ('reserved_252', ctypes.c_uint32), + ('reserved_253', ctypes.c_uint32), + ('reserved_254', ctypes.c_uint32), + ('reserved_255', ctypes.c_uint32), + ('reserved_256', ctypes.c_uint32), + ('reserved_257', ctypes.c_uint32), + ('reserved_258', ctypes.c_uint32), + ('reserved_259', ctypes.c_uint32), + ('reserved_260', ctypes.c_uint32), + ('reserved_261', ctypes.c_uint32), + ('reserved_262', ctypes.c_uint32), + ('reserved_263', ctypes.c_uint32), + ('reserved_264', ctypes.c_uint32), + ('reserved_265', ctypes.c_uint32), + ('reserved_266', ctypes.c_uint32), + ('reserved_267', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_0', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_1', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_2', ctypes.c_uint32), + ('vgt_strmout_buffer_filled_size_3', ctypes.c_uint32), + ('reserved_272', ctypes.c_uint32), + ('reserved_273', ctypes.c_uint32), + ('reserved_274', ctypes.c_uint32), + ('reserved_275', ctypes.c_uint32), + ('vgt_dma_max_size', ctypes.c_uint32), + ('vgt_dma_num_instances', ctypes.c_uint32), + ('reserved_278', ctypes.c_uint32), + ('reserved_279', ctypes.c_uint32), + ('reserved_280', ctypes.c_uint32), + ('reserved_281', ctypes.c_uint32), + ('reserved_282', ctypes.c_uint32), + ('reserved_283', ctypes.c_uint32), + ('reserved_284', ctypes.c_uint32), + ('reserved_285', ctypes.c_uint32), + ('reserved_286', ctypes.c_uint32), + ('reserved_287', ctypes.c_uint32), + ('it_set_base_ib_addr_lo', ctypes.c_uint32), + ('it_set_base_ib_addr_hi', ctypes.c_uint32), + ('reserved_290', ctypes.c_uint32), + ('reserved_291', ctypes.c_uint32), + ('reserved_292', ctypes.c_uint32), + ('reserved_293', ctypes.c_uint32), + ('reserved_294', ctypes.c_uint32), + ('reserved_295', ctypes.c_uint32), + ('reserved_296', ctypes.c_uint32), + ('reserved_297', ctypes.c_uint32), + ('reserved_298', ctypes.c_uint32), + ('reserved_299', ctypes.c_uint32), + ('reserved_300', ctypes.c_uint32), + ('reserved_301', ctypes.c_uint32), + ('reserved_302', ctypes.c_uint32), + ('reserved_303', ctypes.c_uint32), + ('reserved_304', ctypes.c_uint32), + ('reserved_305', ctypes.c_uint32), + ('reserved_306', ctypes.c_uint32), + ('reserved_307', ctypes.c_uint32), + ('reserved_308', ctypes.c_uint32), + ('reserved_309', ctypes.c_uint32), + ('reserved_310', ctypes.c_uint32), + ('reserved_311', ctypes.c_uint32), + ('reserved_312', ctypes.c_uint32), + ('reserved_313', ctypes.c_uint32), + ('reserved_314', ctypes.c_uint32), + ('reserved_315', ctypes.c_uint32), + ('reserved_316', ctypes.c_uint32), + ('reserved_317', ctypes.c_uint32), + ('reserved_318', ctypes.c_uint32), + ('reserved_319', ctypes.c_uint32), + ('reserved_320', ctypes.c_uint32), + ('reserved_321', ctypes.c_uint32), + ('reserved_322', ctypes.c_uint32), + ('reserved_323', ctypes.c_uint32), + ('reserved_324', ctypes.c_uint32), + ('reserved_325', ctypes.c_uint32), + ('reserved_326', ctypes.c_uint32), + ('reserved_327', ctypes.c_uint32), + ('reserved_328', ctypes.c_uint32), + ('reserved_329', ctypes.c_uint32), + ('reserved_330', ctypes.c_uint32), + ('reserved_331', ctypes.c_uint32), + ('reserved_332', ctypes.c_uint32), + ('reserved_333', ctypes.c_uint32), + ('reserved_334', ctypes.c_uint32), + ('reserved_335', ctypes.c_uint32), + ('reserved_336', ctypes.c_uint32), + ('reserved_337', ctypes.c_uint32), + ('reserved_338', ctypes.c_uint32), + ('reserved_339', ctypes.c_uint32), + ('reserved_340', ctypes.c_uint32), + ('reserved_341', ctypes.c_uint32), + ('reserved_342', ctypes.c_uint32), + ('reserved_343', ctypes.c_uint32), + ('reserved_344', ctypes.c_uint32), + ('reserved_345', ctypes.c_uint32), + ('reserved_346', ctypes.c_uint32), + ('reserved_347', ctypes.c_uint32), + ('reserved_348', ctypes.c_uint32), + ('reserved_349', ctypes.c_uint32), + ('reserved_350', ctypes.c_uint32), + ('reserved_351', ctypes.c_uint32), + ('reserved_352', ctypes.c_uint32), + ('reserved_353', ctypes.c_uint32), + ('reserved_354', ctypes.c_uint32), + ('reserved_355', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_ps', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_vs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_gs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc3_hs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_ps', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_vs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_gs', ctypes.c_uint32), + ('spi_shader_pgm_rsrc4_hs', ctypes.c_uint32), + ('db_occlusion_count0_low_00', ctypes.c_uint32), + ('db_occlusion_count0_hi_00', ctypes.c_uint32), + ('db_occlusion_count1_low_00', ctypes.c_uint32), + ('db_occlusion_count1_hi_00', ctypes.c_uint32), + ('db_occlusion_count2_low_00', ctypes.c_uint32), + ('db_occlusion_count2_hi_00', ctypes.c_uint32), + ('db_occlusion_count3_low_00', ctypes.c_uint32), + ('db_occlusion_count3_hi_00', ctypes.c_uint32), + ('db_occlusion_count0_low_01', ctypes.c_uint32), + ('db_occlusion_count0_hi_01', ctypes.c_uint32), + ('db_occlusion_count1_low_01', ctypes.c_uint32), + ('db_occlusion_count1_hi_01', ctypes.c_uint32), + ('db_occlusion_count2_low_01', ctypes.c_uint32), + ('db_occlusion_count2_hi_01', ctypes.c_uint32), + ('db_occlusion_count3_low_01', ctypes.c_uint32), + ('db_occlusion_count3_hi_01', ctypes.c_uint32), + ('db_occlusion_count0_low_02', ctypes.c_uint32), + ('db_occlusion_count0_hi_02', ctypes.c_uint32), + ('db_occlusion_count1_low_02', ctypes.c_uint32), + ('db_occlusion_count1_hi_02', ctypes.c_uint32), + ('db_occlusion_count2_low_02', ctypes.c_uint32), + ('db_occlusion_count2_hi_02', ctypes.c_uint32), + ('db_occlusion_count3_low_02', ctypes.c_uint32), + ('db_occlusion_count3_hi_02', ctypes.c_uint32), + ('db_occlusion_count0_low_03', ctypes.c_uint32), + ('db_occlusion_count0_hi_03', ctypes.c_uint32), + ('db_occlusion_count1_low_03', ctypes.c_uint32), + ('db_occlusion_count1_hi_03', ctypes.c_uint32), + ('db_occlusion_count2_low_03', ctypes.c_uint32), + ('db_occlusion_count2_hi_03', ctypes.c_uint32), + ('db_occlusion_count3_low_03', ctypes.c_uint32), + ('db_occlusion_count3_hi_03', ctypes.c_uint32), + ('db_occlusion_count0_low_04', ctypes.c_uint32), + ('db_occlusion_count0_hi_04', ctypes.c_uint32), + ('db_occlusion_count1_low_04', ctypes.c_uint32), + ('db_occlusion_count1_hi_04', ctypes.c_uint32), + ('db_occlusion_count2_low_04', ctypes.c_uint32), + ('db_occlusion_count2_hi_04', ctypes.c_uint32), + ('db_occlusion_count3_low_04', ctypes.c_uint32), + ('db_occlusion_count3_hi_04', ctypes.c_uint32), + ('db_occlusion_count0_low_05', ctypes.c_uint32), + ('db_occlusion_count0_hi_05', ctypes.c_uint32), + ('db_occlusion_count1_low_05', ctypes.c_uint32), + ('db_occlusion_count1_hi_05', ctypes.c_uint32), + ('db_occlusion_count2_low_05', ctypes.c_uint32), + ('db_occlusion_count2_hi_05', ctypes.c_uint32), + ('db_occlusion_count3_low_05', ctypes.c_uint32), + ('db_occlusion_count3_hi_05', ctypes.c_uint32), + ('db_occlusion_count0_low_06', ctypes.c_uint32), + ('db_occlusion_count0_hi_06', ctypes.c_uint32), + ('db_occlusion_count1_low_06', ctypes.c_uint32), + ('db_occlusion_count1_hi_06', ctypes.c_uint32), + ('db_occlusion_count2_low_06', ctypes.c_uint32), + ('db_occlusion_count2_hi_06', ctypes.c_uint32), + ('db_occlusion_count3_low_06', ctypes.c_uint32), + ('db_occlusion_count3_hi_06', ctypes.c_uint32), + ('db_occlusion_count0_low_07', ctypes.c_uint32), + ('db_occlusion_count0_hi_07', ctypes.c_uint32), + ('db_occlusion_count1_low_07', ctypes.c_uint32), + ('db_occlusion_count1_hi_07', ctypes.c_uint32), + ('db_occlusion_count2_low_07', ctypes.c_uint32), + ('db_occlusion_count2_hi_07', ctypes.c_uint32), + ('db_occlusion_count3_low_07', ctypes.c_uint32), + ('db_occlusion_count3_hi_07', ctypes.c_uint32), + ('db_occlusion_count0_low_10', ctypes.c_uint32), + ('db_occlusion_count0_hi_10', ctypes.c_uint32), + ('db_occlusion_count1_low_10', ctypes.c_uint32), + ('db_occlusion_count1_hi_10', ctypes.c_uint32), + ('db_occlusion_count2_low_10', ctypes.c_uint32), + ('db_occlusion_count2_hi_10', ctypes.c_uint32), + ('db_occlusion_count3_low_10', ctypes.c_uint32), + ('db_occlusion_count3_hi_10', ctypes.c_uint32), + ('db_occlusion_count0_low_11', ctypes.c_uint32), + ('db_occlusion_count0_hi_11', ctypes.c_uint32), + ('db_occlusion_count1_low_11', ctypes.c_uint32), + ('db_occlusion_count1_hi_11', ctypes.c_uint32), + ('db_occlusion_count2_low_11', ctypes.c_uint32), + ('db_occlusion_count2_hi_11', ctypes.c_uint32), + ('db_occlusion_count3_low_11', ctypes.c_uint32), + ('db_occlusion_count3_hi_11', ctypes.c_uint32), + ('db_occlusion_count0_low_12', ctypes.c_uint32), + ('db_occlusion_count0_hi_12', ctypes.c_uint32), + ('db_occlusion_count1_low_12', ctypes.c_uint32), + ('db_occlusion_count1_hi_12', ctypes.c_uint32), + ('db_occlusion_count2_low_12', ctypes.c_uint32), + ('db_occlusion_count2_hi_12', ctypes.c_uint32), + ('db_occlusion_count3_low_12', ctypes.c_uint32), + ('db_occlusion_count3_hi_12', ctypes.c_uint32), + ('db_occlusion_count0_low_13', ctypes.c_uint32), + ('db_occlusion_count0_hi_13', ctypes.c_uint32), + ('db_occlusion_count1_low_13', ctypes.c_uint32), + ('db_occlusion_count1_hi_13', ctypes.c_uint32), + ('db_occlusion_count2_low_13', ctypes.c_uint32), + ('db_occlusion_count2_hi_13', ctypes.c_uint32), + ('db_occlusion_count3_low_13', ctypes.c_uint32), + ('db_occlusion_count3_hi_13', ctypes.c_uint32), + ('db_occlusion_count0_low_14', ctypes.c_uint32), + ('db_occlusion_count0_hi_14', ctypes.c_uint32), + ('db_occlusion_count1_low_14', ctypes.c_uint32), + ('db_occlusion_count1_hi_14', ctypes.c_uint32), + ('db_occlusion_count2_low_14', ctypes.c_uint32), + ('db_occlusion_count2_hi_14', ctypes.c_uint32), + ('db_occlusion_count3_low_14', ctypes.c_uint32), + ('db_occlusion_count3_hi_14', ctypes.c_uint32), + ('db_occlusion_count0_low_15', ctypes.c_uint32), + ('db_occlusion_count0_hi_15', ctypes.c_uint32), + ('db_occlusion_count1_low_15', ctypes.c_uint32), + ('db_occlusion_count1_hi_15', ctypes.c_uint32), + ('db_occlusion_count2_low_15', ctypes.c_uint32), + ('db_occlusion_count2_hi_15', ctypes.c_uint32), + ('db_occlusion_count3_low_15', ctypes.c_uint32), + ('db_occlusion_count3_hi_15', ctypes.c_uint32), + ('db_occlusion_count0_low_16', ctypes.c_uint32), + ('db_occlusion_count0_hi_16', ctypes.c_uint32), + ('db_occlusion_count1_low_16', ctypes.c_uint32), + ('db_occlusion_count1_hi_16', ctypes.c_uint32), + ('db_occlusion_count2_low_16', ctypes.c_uint32), + ('db_occlusion_count2_hi_16', ctypes.c_uint32), + ('db_occlusion_count3_low_16', ctypes.c_uint32), + ('db_occlusion_count3_hi_16', ctypes.c_uint32), + ('db_occlusion_count0_low_17', ctypes.c_uint32), + ('db_occlusion_count0_hi_17', ctypes.c_uint32), + ('db_occlusion_count1_low_17', ctypes.c_uint32), + ('db_occlusion_count1_hi_17', ctypes.c_uint32), + ('db_occlusion_count2_low_17', ctypes.c_uint32), + ('db_occlusion_count2_hi_17', ctypes.c_uint32), + ('db_occlusion_count3_low_17', ctypes.c_uint32), + ('db_occlusion_count3_hi_17', ctypes.c_uint32), + ('reserved_492', ctypes.c_uint32), + ('reserved_493', ctypes.c_uint32), + ('reserved_494', ctypes.c_uint32), + ('reserved_495', ctypes.c_uint32), + ('reserved_496', ctypes.c_uint32), + ('reserved_497', ctypes.c_uint32), + ('reserved_498', ctypes.c_uint32), + ('reserved_499', ctypes.c_uint32), + ('reserved_500', ctypes.c_uint32), + ('reserved_501', ctypes.c_uint32), + ('reserved_502', ctypes.c_uint32), + ('reserved_503', ctypes.c_uint32), + ('reserved_504', ctypes.c_uint32), + ('reserved_505', ctypes.c_uint32), + ('reserved_506', ctypes.c_uint32), + ('reserved_507', ctypes.c_uint32), + ('reserved_508', ctypes.c_uint32), + ('reserved_509', ctypes.c_uint32), + ('reserved_510', ctypes.c_uint32), + ('reserved_511', ctypes.c_uint32), ] - -class struct_v11_sdma_mqd(Structure): - pass - -struct_v11_sdma_mqd._pack_ = 1 # source:False +class struct_v11_sdma_mqd(Struct): pass struct_v11_sdma_mqd._fields_ = [ - ('sdmax_rlcx_rb_cntl', ctypes.c_uint32), - ('sdmax_rlcx_rb_base', ctypes.c_uint32), - ('sdmax_rlcx_rb_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_ib_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_rptr', ctypes.c_uint32), - ('sdmax_rlcx_ib_offset', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_lo', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_ib_size', ctypes.c_uint32), - ('sdmax_rlcx_skip_cntl', ctypes.c_uint32), - ('sdmax_rlcx_context_status', ctypes.c_uint32), - ('sdmax_rlcx_doorbell', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_log', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_offset', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_sched_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_sub_remain', ctypes.c_uint32), - ('sdmax_rlcx_preempt', ctypes.c_uint32), - ('sdmax_rlcx_dummy_reg', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_rb_aql_cntl', ctypes.c_uint32), - ('sdmax_rlcx_minor_ptr_update', ctypes.c_uint32), - ('sdmax_rlcx_rb_preempt', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data0', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data1', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data2', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data3', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data4', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data5', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data6', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data7', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data8', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data9', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data10', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_cntl', ctypes.c_uint32), - ('sdmax_rlcx_f32_dbg0', ctypes.c_uint32), - ('sdmax_rlcx_f32_dbg1', ctypes.c_uint32), - ('reserved_45', ctypes.c_uint32), - ('reserved_46', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('reserved_86', ctypes.c_uint32), - ('reserved_87', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('reserved_92', ctypes.c_uint32), - ('reserved_93', ctypes.c_uint32), - ('reserved_94', ctypes.c_uint32), - ('reserved_95', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('reserved_104', ctypes.c_uint32), - ('reserved_105', ctypes.c_uint32), - ('reserved_106', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('sdma_engine_id', ctypes.c_uint32), - ('sdma_queue_id', ctypes.c_uint32), + ('sdmax_rlcx_rb_cntl', ctypes.c_uint32), + ('sdmax_rlcx_rb_base', ctypes.c_uint32), + ('sdmax_rlcx_rb_base_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr_addr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_rptr_addr_lo', ctypes.c_uint32), + ('sdmax_rlcx_ib_cntl', ctypes.c_uint32), + ('sdmax_rlcx_ib_rptr', ctypes.c_uint32), + ('sdmax_rlcx_ib_offset', ctypes.c_uint32), + ('sdmax_rlcx_ib_base_lo', ctypes.c_uint32), + ('sdmax_rlcx_ib_base_hi', ctypes.c_uint32), + ('sdmax_rlcx_ib_size', ctypes.c_uint32), + ('sdmax_rlcx_skip_cntl', ctypes.c_uint32), + ('sdmax_rlcx_context_status', ctypes.c_uint32), + ('sdmax_rlcx_doorbell', ctypes.c_uint32), + ('sdmax_rlcx_doorbell_log', ctypes.c_uint32), + ('sdmax_rlcx_doorbell_offset', ctypes.c_uint32), + ('sdmax_rlcx_csa_addr_lo', ctypes.c_uint32), + ('sdmax_rlcx_csa_addr_hi', ctypes.c_uint32), + ('sdmax_rlcx_sched_cntl', ctypes.c_uint32), + ('sdmax_rlcx_ib_sub_remain', ctypes.c_uint32), + ('sdmax_rlcx_preempt', ctypes.c_uint32), + ('sdmax_rlcx_dummy_reg', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr_poll_addr_hi', ctypes.c_uint32), + ('sdmax_rlcx_rb_wptr_poll_addr_lo', ctypes.c_uint32), + ('sdmax_rlcx_rb_aql_cntl', ctypes.c_uint32), + ('sdmax_rlcx_minor_ptr_update', ctypes.c_uint32), + ('sdmax_rlcx_rb_preempt', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data0', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data1', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data2', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data3', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data4', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data5', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data6', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data7', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data8', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data9', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_data10', ctypes.c_uint32), + ('sdmax_rlcx_midcmd_cntl', ctypes.c_uint32), + ('sdmax_rlcx_f32_dbg0', ctypes.c_uint32), + ('sdmax_rlcx_f32_dbg1', ctypes.c_uint32), + ('reserved_45', ctypes.c_uint32), + ('reserved_46', ctypes.c_uint32), + ('reserved_47', ctypes.c_uint32), + ('reserved_48', ctypes.c_uint32), + ('reserved_49', ctypes.c_uint32), + ('reserved_50', ctypes.c_uint32), + ('reserved_51', ctypes.c_uint32), + ('reserved_52', ctypes.c_uint32), + ('reserved_53', ctypes.c_uint32), + ('reserved_54', ctypes.c_uint32), + ('reserved_55', ctypes.c_uint32), + ('reserved_56', ctypes.c_uint32), + ('reserved_57', ctypes.c_uint32), + ('reserved_58', ctypes.c_uint32), + ('reserved_59', ctypes.c_uint32), + ('reserved_60', ctypes.c_uint32), + ('reserved_61', ctypes.c_uint32), + ('reserved_62', ctypes.c_uint32), + ('reserved_63', ctypes.c_uint32), + ('reserved_64', ctypes.c_uint32), + ('reserved_65', ctypes.c_uint32), + ('reserved_66', ctypes.c_uint32), + ('reserved_67', ctypes.c_uint32), + ('reserved_68', ctypes.c_uint32), + ('reserved_69', ctypes.c_uint32), + ('reserved_70', ctypes.c_uint32), + ('reserved_71', ctypes.c_uint32), + ('reserved_72', ctypes.c_uint32), + ('reserved_73', ctypes.c_uint32), + ('reserved_74', ctypes.c_uint32), + ('reserved_75', ctypes.c_uint32), + ('reserved_76', ctypes.c_uint32), + ('reserved_77', ctypes.c_uint32), + ('reserved_78', ctypes.c_uint32), + ('reserved_79', ctypes.c_uint32), + ('reserved_80', ctypes.c_uint32), + ('reserved_81', ctypes.c_uint32), + ('reserved_82', ctypes.c_uint32), + ('reserved_83', ctypes.c_uint32), + ('reserved_84', ctypes.c_uint32), + ('reserved_85', ctypes.c_uint32), + ('reserved_86', ctypes.c_uint32), + ('reserved_87', ctypes.c_uint32), + ('reserved_88', ctypes.c_uint32), + ('reserved_89', ctypes.c_uint32), + ('reserved_90', ctypes.c_uint32), + ('reserved_91', ctypes.c_uint32), + ('reserved_92', ctypes.c_uint32), + ('reserved_93', ctypes.c_uint32), + ('reserved_94', ctypes.c_uint32), + ('reserved_95', ctypes.c_uint32), + ('reserved_96', ctypes.c_uint32), + ('reserved_97', ctypes.c_uint32), + ('reserved_98', ctypes.c_uint32), + ('reserved_99', ctypes.c_uint32), + ('reserved_100', ctypes.c_uint32), + ('reserved_101', ctypes.c_uint32), + ('reserved_102', ctypes.c_uint32), + ('reserved_103', ctypes.c_uint32), + ('reserved_104', ctypes.c_uint32), + ('reserved_105', ctypes.c_uint32), + ('reserved_106', ctypes.c_uint32), + ('reserved_107', ctypes.c_uint32), + ('reserved_108', ctypes.c_uint32), + ('reserved_109', ctypes.c_uint32), + ('reserved_110', ctypes.c_uint32), + ('reserved_111', ctypes.c_uint32), + ('reserved_112', ctypes.c_uint32), + ('reserved_113', ctypes.c_uint32), + ('reserved_114', ctypes.c_uint32), + ('reserved_115', ctypes.c_uint32), + ('reserved_116', ctypes.c_uint32), + ('reserved_117', ctypes.c_uint32), + ('reserved_118', ctypes.c_uint32), + ('reserved_119', ctypes.c_uint32), + ('reserved_120', ctypes.c_uint32), + ('reserved_121', ctypes.c_uint32), + ('reserved_122', ctypes.c_uint32), + ('reserved_123', ctypes.c_uint32), + ('reserved_124', ctypes.c_uint32), + ('reserved_125', ctypes.c_uint32), + ('sdma_engine_id', ctypes.c_uint32), + ('sdma_queue_id', ctypes.c_uint32), ] - -class struct_v11_compute_mqd(Structure): - pass - -struct_v11_compute_mqd._pack_ = 1 # source:False +class struct_v11_compute_mqd(Struct): pass struct_v11_compute_mqd._fields_ = [ - ('header', ctypes.c_uint32), - ('compute_dispatch_initiator', ctypes.c_uint32), - ('compute_dim_x', ctypes.c_uint32), - ('compute_dim_y', ctypes.c_uint32), - ('compute_dim_z', ctypes.c_uint32), - ('compute_start_x', ctypes.c_uint32), - ('compute_start_y', ctypes.c_uint32), - ('compute_start_z', ctypes.c_uint32), - ('compute_num_thread_x', ctypes.c_uint32), - ('compute_num_thread_y', ctypes.c_uint32), - ('compute_num_thread_z', ctypes.c_uint32), - ('compute_pipelinestat_enable', ctypes.c_uint32), - ('compute_perfcount_enable', ctypes.c_uint32), - ('compute_pgm_lo', ctypes.c_uint32), - ('compute_pgm_hi', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_lo', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_hi', ctypes.c_uint32), - ('compute_dispatch_scratch_base_lo', ctypes.c_uint32), - ('compute_dispatch_scratch_base_hi', ctypes.c_uint32), - ('compute_pgm_rsrc1', ctypes.c_uint32), - ('compute_pgm_rsrc2', ctypes.c_uint32), - ('compute_vmid', ctypes.c_uint32), - ('compute_resource_limits', ctypes.c_uint32), - ('compute_static_thread_mgmt_se0', ctypes.c_uint32), - ('compute_static_thread_mgmt_se1', ctypes.c_uint32), - ('compute_tmpring_size', ctypes.c_uint32), - ('compute_static_thread_mgmt_se2', ctypes.c_uint32), - ('compute_static_thread_mgmt_se3', ctypes.c_uint32), - ('compute_restart_x', ctypes.c_uint32), - ('compute_restart_y', ctypes.c_uint32), - ('compute_restart_z', ctypes.c_uint32), - ('compute_thread_trace_enable', ctypes.c_uint32), - ('compute_misc_reserved', ctypes.c_uint32), - ('compute_dispatch_id', ctypes.c_uint32), - ('compute_threadgroup_id', ctypes.c_uint32), - ('compute_req_ctrl', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('compute_user_accum_0', ctypes.c_uint32), - ('compute_user_accum_1', ctypes.c_uint32), - ('compute_user_accum_2', ctypes.c_uint32), - ('compute_user_accum_3', ctypes.c_uint32), - ('compute_pgm_rsrc3', ctypes.c_uint32), - ('compute_ddid_index', ctypes.c_uint32), - ('compute_shader_chksum', ctypes.c_uint32), - ('compute_static_thread_mgmt_se4', ctypes.c_uint32), - ('compute_static_thread_mgmt_se5', ctypes.c_uint32), - ('compute_static_thread_mgmt_se6', ctypes.c_uint32), - ('compute_static_thread_mgmt_se7', ctypes.c_uint32), - ('compute_dispatch_interleave', ctypes.c_uint32), - ('compute_relaunch', ctypes.c_uint32), - ('compute_wave_restore_addr_lo', ctypes.c_uint32), - ('compute_wave_restore_addr_hi', ctypes.c_uint32), - ('compute_wave_restore_control', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('compute_user_data_0', ctypes.c_uint32), - ('compute_user_data_1', ctypes.c_uint32), - ('compute_user_data_2', ctypes.c_uint32), - ('compute_user_data_3', ctypes.c_uint32), - ('compute_user_data_4', ctypes.c_uint32), - ('compute_user_data_5', ctypes.c_uint32), - ('compute_user_data_6', ctypes.c_uint32), - ('compute_user_data_7', ctypes.c_uint32), - ('compute_user_data_8', ctypes.c_uint32), - ('compute_user_data_9', ctypes.c_uint32), - ('compute_user_data_10', ctypes.c_uint32), - ('compute_user_data_11', ctypes.c_uint32), - ('compute_user_data_12', ctypes.c_uint32), - ('compute_user_data_13', ctypes.c_uint32), - ('compute_user_data_14', ctypes.c_uint32), - ('compute_user_data_15', ctypes.c_uint32), - ('cp_compute_csinvoc_count_lo', ctypes.c_uint32), - ('cp_compute_csinvoc_count_hi', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_start_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_start_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_end_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_wf_count', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_rptr', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_wptr', ctypes.c_uint32), - ('cp_mqd_connect_end_ib_rptr', ctypes.c_uint32), - ('cp_mqd_readindex_lo', ctypes.c_uint32), - ('cp_mqd_readindex_hi', ctypes.c_uint32), - ('cp_mqd_save_start_time_lo', ctypes.c_uint32), - ('cp_mqd_save_start_time_hi', ctypes.c_uint32), - ('cp_mqd_save_end_time_lo', ctypes.c_uint32), - ('cp_mqd_save_end_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_start_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_start_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_end_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_end_time_hi', ctypes.c_uint32), - ('disable_queue', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt0', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt1', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt2', ctypes.c_uint32), - ('gds_cs_ctxsw_cnt3', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('cp_pq_exe_status_lo', ctypes.c_uint32), - ('cp_pq_exe_status_hi', ctypes.c_uint32), - ('cp_packet_id_lo', ctypes.c_uint32), - ('cp_packet_id_hi', ctypes.c_uint32), - ('cp_packet_exe_status_lo', ctypes.c_uint32), - ('cp_packet_exe_status_hi', ctypes.c_uint32), - ('gds_save_base_addr_lo', ctypes.c_uint32), - ('gds_save_base_addr_hi', ctypes.c_uint32), - ('gds_save_mask_lo', ctypes.c_uint32), - ('gds_save_mask_hi', ctypes.c_uint32), - ('ctx_save_base_addr_lo', ctypes.c_uint32), - ('ctx_save_base_addr_hi', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr_lo', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_active', ctypes.c_uint32), - ('cp_hqd_vmid', ctypes.c_uint32), - ('cp_hqd_persistent_state', ctypes.c_uint32), - ('cp_hqd_pipe_priority', ctypes.c_uint32), - ('cp_hqd_queue_priority', ctypes.c_uint32), - ('cp_hqd_quantum', ctypes.c_uint32), - ('cp_hqd_pq_base_lo', ctypes.c_uint32), - ('cp_hqd_pq_base_hi', ctypes.c_uint32), - ('cp_hqd_pq_rptr', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_doorbell_control', ctypes.c_uint32), - ('reserved_144', ctypes.c_uint32), - ('cp_hqd_pq_control', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ib_rptr', ctypes.c_uint32), - ('cp_hqd_ib_control', ctypes.c_uint32), - ('cp_hqd_iq_timer', ctypes.c_uint32), - ('cp_hqd_iq_rptr', ctypes.c_uint32), - ('cp_hqd_dequeue_request', ctypes.c_uint32), - ('cp_hqd_dma_offload', ctypes.c_uint32), - ('cp_hqd_sema_cmd', ctypes.c_uint32), - ('cp_hqd_msg_type', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_hi', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_hi', ctypes.c_uint32), - ('cp_hqd_hq_status0', ctypes.c_uint32), - ('cp_hqd_hq_control0', ctypes.c_uint32), - ('cp_mqd_control', ctypes.c_uint32), - ('cp_hqd_hq_status1', ctypes.c_uint32), - ('cp_hqd_hq_control1', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_eop_control', ctypes.c_uint32), - ('cp_hqd_eop_rptr', ctypes.c_uint32), - ('cp_hqd_eop_wptr', ctypes.c_uint32), - ('cp_hqd_eop_done_events', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ctx_save_control', ctypes.c_uint32), - ('cp_hqd_cntl_stack_offset', ctypes.c_uint32), - ('cp_hqd_cntl_stack_size', ctypes.c_uint32), - ('cp_hqd_wg_state_offset', ctypes.c_uint32), - ('cp_hqd_ctx_save_size', ctypes.c_uint32), - ('cp_hqd_gds_resource_state', ctypes.c_uint32), - ('cp_hqd_error', ctypes.c_uint32), - ('cp_hqd_eop_wptr_mem', ctypes.c_uint32), - ('cp_hqd_aql_control', ctypes.c_uint32), - ('cp_hqd_pq_wptr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_hi', ctypes.c_uint32), - ('reserved_184', ctypes.c_uint32), - ('reserved_185', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('reserved_190', ctypes.c_uint32), - ('reserved_191', ctypes.c_uint32), - ('iqtimer_pkt_header', ctypes.c_uint32), - ('iqtimer_pkt_dw0', ctypes.c_uint32), - ('iqtimer_pkt_dw1', ctypes.c_uint32), - ('iqtimer_pkt_dw2', ctypes.c_uint32), - ('iqtimer_pkt_dw3', ctypes.c_uint32), - ('iqtimer_pkt_dw4', ctypes.c_uint32), - ('iqtimer_pkt_dw5', ctypes.c_uint32), - ('iqtimer_pkt_dw6', ctypes.c_uint32), - ('iqtimer_pkt_dw7', ctypes.c_uint32), - ('iqtimer_pkt_dw8', ctypes.c_uint32), - ('iqtimer_pkt_dw9', ctypes.c_uint32), - ('iqtimer_pkt_dw10', ctypes.c_uint32), - ('iqtimer_pkt_dw11', ctypes.c_uint32), - ('iqtimer_pkt_dw12', ctypes.c_uint32), - ('iqtimer_pkt_dw13', ctypes.c_uint32), - ('iqtimer_pkt_dw14', ctypes.c_uint32), - ('iqtimer_pkt_dw15', ctypes.c_uint32), - ('iqtimer_pkt_dw16', ctypes.c_uint32), - ('iqtimer_pkt_dw17', ctypes.c_uint32), - ('iqtimer_pkt_dw18', ctypes.c_uint32), - ('iqtimer_pkt_dw19', ctypes.c_uint32), - ('iqtimer_pkt_dw20', ctypes.c_uint32), - ('iqtimer_pkt_dw21', ctypes.c_uint32), - ('iqtimer_pkt_dw22', ctypes.c_uint32), - ('iqtimer_pkt_dw23', ctypes.c_uint32), - ('iqtimer_pkt_dw24', ctypes.c_uint32), - ('iqtimer_pkt_dw25', ctypes.c_uint32), - ('iqtimer_pkt_dw26', ctypes.c_uint32), - ('iqtimer_pkt_dw27', ctypes.c_uint32), - ('iqtimer_pkt_dw28', ctypes.c_uint32), - ('iqtimer_pkt_dw29', ctypes.c_uint32), - ('iqtimer_pkt_dw30', ctypes.c_uint32), - ('iqtimer_pkt_dw31', ctypes.c_uint32), - ('reserved_225', ctypes.c_uint32), - ('reserved_226', ctypes.c_uint32), - ('reserved_227', ctypes.c_uint32), - ('set_resources_header', ctypes.c_uint32), - ('set_resources_dw1', ctypes.c_uint32), - ('set_resources_dw2', ctypes.c_uint32), - ('set_resources_dw3', ctypes.c_uint32), - ('set_resources_dw4', ctypes.c_uint32), - ('set_resources_dw5', ctypes.c_uint32), - ('set_resources_dw6', ctypes.c_uint32), - ('set_resources_dw7', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('queue_doorbell_id0', ctypes.c_uint32), - ('queue_doorbell_id1', ctypes.c_uint32), - ('queue_doorbell_id2', ctypes.c_uint32), - ('queue_doorbell_id3', ctypes.c_uint32), - ('queue_doorbell_id4', ctypes.c_uint32), - ('queue_doorbell_id5', ctypes.c_uint32), - ('queue_doorbell_id6', ctypes.c_uint32), - ('queue_doorbell_id7', ctypes.c_uint32), - ('queue_doorbell_id8', ctypes.c_uint32), - ('queue_doorbell_id9', ctypes.c_uint32), - ('queue_doorbell_id10', ctypes.c_uint32), - ('queue_doorbell_id11', ctypes.c_uint32), - ('queue_doorbell_id12', ctypes.c_uint32), - ('queue_doorbell_id13', ctypes.c_uint32), - ('queue_doorbell_id14', ctypes.c_uint32), - ('queue_doorbell_id15', ctypes.c_uint32), - ('control_buf_addr_lo', ctypes.c_uint32), - ('control_buf_addr_hi', ctypes.c_uint32), - ('control_buf_wptr_lo', ctypes.c_uint32), - ('control_buf_wptr_hi', ctypes.c_uint32), - ('control_buf_dptr_lo', ctypes.c_uint32), - ('control_buf_dptr_hi', ctypes.c_uint32), - ('control_buf_num_entries', ctypes.c_uint32), - ('draw_ring_addr_lo', ctypes.c_uint32), - ('draw_ring_addr_hi', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('reserved_268', ctypes.c_uint32), - ('reserved_269', ctypes.c_uint32), - ('reserved_270', ctypes.c_uint32), - ('reserved_271', ctypes.c_uint32), - ('reserved_272', ctypes.c_uint32), - ('reserved_273', ctypes.c_uint32), - ('reserved_274', ctypes.c_uint32), - ('reserved_275', ctypes.c_uint32), - ('reserved_276', ctypes.c_uint32), - ('reserved_277', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('reserved_288', ctypes.c_uint32), - ('reserved_289', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - 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('compute_dispatch_scratch_base_hi', ctypes.c_uint32), + ('compute_pgm_rsrc1', ctypes.c_uint32), + ('compute_pgm_rsrc2', ctypes.c_uint32), + ('compute_vmid', ctypes.c_uint32), + ('compute_resource_limits', ctypes.c_uint32), + ('compute_static_thread_mgmt_se0', ctypes.c_uint32), + ('compute_static_thread_mgmt_se1', ctypes.c_uint32), + ('compute_tmpring_size', ctypes.c_uint32), + ('compute_static_thread_mgmt_se2', ctypes.c_uint32), + ('compute_static_thread_mgmt_se3', ctypes.c_uint32), + ('compute_restart_x', ctypes.c_uint32), + ('compute_restart_y', ctypes.c_uint32), + ('compute_restart_z', ctypes.c_uint32), + ('compute_thread_trace_enable', ctypes.c_uint32), + ('compute_misc_reserved', ctypes.c_uint32), + ('compute_dispatch_id', ctypes.c_uint32), + ('compute_threadgroup_id', ctypes.c_uint32), + ('compute_req_ctrl', ctypes.c_uint32), + ('reserved_36', ctypes.c_uint32), + ('compute_user_accum_0', ctypes.c_uint32), + ('compute_user_accum_1', ctypes.c_uint32), + ('compute_user_accum_2', ctypes.c_uint32), + ('compute_user_accum_3', ctypes.c_uint32), + ('compute_pgm_rsrc3', ctypes.c_uint32), + ('compute_ddid_index', ctypes.c_uint32), + ('compute_shader_chksum', ctypes.c_uint32), + ('compute_static_thread_mgmt_se4', ctypes.c_uint32), + ('compute_static_thread_mgmt_se5', ctypes.c_uint32), + ('compute_static_thread_mgmt_se6', ctypes.c_uint32), + ('compute_static_thread_mgmt_se7', ctypes.c_uint32), + ('compute_dispatch_interleave', ctypes.c_uint32), + ('compute_relaunch', ctypes.c_uint32), + ('compute_wave_restore_addr_lo', ctypes.c_uint32), + ('compute_wave_restore_addr_hi', ctypes.c_uint32), + ('compute_wave_restore_control', ctypes.c_uint32), + ('reserved_53', ctypes.c_uint32), + ('reserved_54', ctypes.c_uint32), + ('reserved_55', ctypes.c_uint32), + ('reserved_56', ctypes.c_uint32), + ('reserved_57', ctypes.c_uint32), + ('reserved_58', ctypes.c_uint32), + ('reserved_59', ctypes.c_uint32), + ('reserved_60', ctypes.c_uint32), + ('reserved_61', ctypes.c_uint32), + ('reserved_62', ctypes.c_uint32), + ('reserved_63', ctypes.c_uint32), + ('reserved_64', ctypes.c_uint32), + ('compute_user_data_0', ctypes.c_uint32), + ('compute_user_data_1', ctypes.c_uint32), + ('compute_user_data_2', ctypes.c_uint32), + ('compute_user_data_3', ctypes.c_uint32), + ('compute_user_data_4', ctypes.c_uint32), + ('compute_user_data_5', ctypes.c_uint32), + ('compute_user_data_6', ctypes.c_uint32), + ('compute_user_data_7', ctypes.c_uint32), + ('compute_user_data_8', ctypes.c_uint32), + ('compute_user_data_9', ctypes.c_uint32), + ('compute_user_data_10', ctypes.c_uint32), + ('compute_user_data_11', ctypes.c_uint32), + ('compute_user_data_12', ctypes.c_uint32), + ('compute_user_data_13', ctypes.c_uint32), + ('compute_user_data_14', ctypes.c_uint32), + ('compute_user_data_15', ctypes.c_uint32), + ('cp_compute_csinvoc_count_lo', ctypes.c_uint32), + ('cp_compute_csinvoc_count_hi', ctypes.c_uint32), + ('reserved_83', ctypes.c_uint32), + ('reserved_84', ctypes.c_uint32), + ('reserved_85', ctypes.c_uint32), + ('cp_mqd_query_time_lo', ctypes.c_uint32), + ('cp_mqd_query_time_hi', ctypes.c_uint32), + ('cp_mqd_connect_start_time_lo', ctypes.c_uint32), + ('cp_mqd_connect_start_time_hi', ctypes.c_uint32), + ('cp_mqd_connect_end_time_lo', ctypes.c_uint32), + ('cp_mqd_connect_end_time_hi', ctypes.c_uint32), + ('cp_mqd_connect_end_wf_count', ctypes.c_uint32), + ('cp_mqd_connect_end_pq_rptr', ctypes.c_uint32), + ('cp_mqd_connect_end_pq_wptr', ctypes.c_uint32), + ('cp_mqd_connect_end_ib_rptr', ctypes.c_uint32), + ('cp_mqd_readindex_lo', ctypes.c_uint32), + ('cp_mqd_readindex_hi', ctypes.c_uint32), + ('cp_mqd_save_start_time_lo', ctypes.c_uint32), + ('cp_mqd_save_start_time_hi', ctypes.c_uint32), + ('cp_mqd_save_end_time_lo', ctypes.c_uint32), + ('cp_mqd_save_end_time_hi', ctypes.c_uint32), + ('cp_mqd_restore_start_time_lo', ctypes.c_uint32), + ('cp_mqd_restore_start_time_hi', ctypes.c_uint32), + ('cp_mqd_restore_end_time_lo', ctypes.c_uint32), + ('cp_mqd_restore_end_time_hi', ctypes.c_uint32), + ('disable_queue', ctypes.c_uint32), + ('reserved_107', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt0', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt1', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt2', ctypes.c_uint32), + ('gds_cs_ctxsw_cnt3', ctypes.c_uint32), + ('reserved_112', ctypes.c_uint32), + ('reserved_113', ctypes.c_uint32), + ('cp_pq_exe_status_lo', ctypes.c_uint32), + ('cp_pq_exe_status_hi', ctypes.c_uint32), + ('cp_packet_id_lo', ctypes.c_uint32), + ('cp_packet_id_hi', ctypes.c_uint32), + ('cp_packet_exe_status_lo', ctypes.c_uint32), + ('cp_packet_exe_status_hi', ctypes.c_uint32), + ('gds_save_base_addr_lo', ctypes.c_uint32), + ('gds_save_base_addr_hi', ctypes.c_uint32), + ('gds_save_mask_lo', ctypes.c_uint32), + ('gds_save_mask_hi', ctypes.c_uint32), + ('ctx_save_base_addr_lo', ctypes.c_uint32), + ('ctx_save_base_addr_hi', ctypes.c_uint32), + ('reserved_126', ctypes.c_uint32), + ('reserved_127', ctypes.c_uint32), + ('cp_mqd_base_addr_lo', ctypes.c_uint32), + ('cp_mqd_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_active', ctypes.c_uint32), + ('cp_hqd_vmid', ctypes.c_uint32), + ('cp_hqd_persistent_state', ctypes.c_uint32), + ('cp_hqd_pipe_priority', ctypes.c_uint32), + ('cp_hqd_queue_priority', ctypes.c_uint32), + ('cp_hqd_quantum', ctypes.c_uint32), + ('cp_hqd_pq_base_lo', ctypes.c_uint32), + ('cp_hqd_pq_base_hi', ctypes.c_uint32), + ('cp_hqd_pq_rptr', ctypes.c_uint32), + ('cp_hqd_pq_rptr_report_addr_lo', ctypes.c_uint32), + ('cp_hqd_pq_rptr_report_addr_hi', ctypes.c_uint32), + ('cp_hqd_pq_wptr_poll_addr_lo', ctypes.c_uint32), + ('cp_hqd_pq_wptr_poll_addr_hi', ctypes.c_uint32), + ('cp_hqd_pq_doorbell_control', ctypes.c_uint32), + ('reserved_144', ctypes.c_uint32), + ('cp_hqd_pq_control', ctypes.c_uint32), + ('cp_hqd_ib_base_addr_lo', ctypes.c_uint32), + ('cp_hqd_ib_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_ib_rptr', ctypes.c_uint32), + ('cp_hqd_ib_control', ctypes.c_uint32), + ('cp_hqd_iq_timer', ctypes.c_uint32), + ('cp_hqd_iq_rptr', ctypes.c_uint32), + ('cp_hqd_dequeue_request', ctypes.c_uint32), + ('cp_hqd_dma_offload', ctypes.c_uint32), + ('cp_hqd_sema_cmd', ctypes.c_uint32), + ('cp_hqd_msg_type', ctypes.c_uint32), + ('cp_hqd_atomic0_preop_lo', ctypes.c_uint32), + ('cp_hqd_atomic0_preop_hi', ctypes.c_uint32), + ('cp_hqd_atomic1_preop_lo', ctypes.c_uint32), + ('cp_hqd_atomic1_preop_hi', ctypes.c_uint32), + ('cp_hqd_hq_status0', ctypes.c_uint32), + ('cp_hqd_hq_control0', ctypes.c_uint32), + ('cp_mqd_control', ctypes.c_uint32), + ('cp_hqd_hq_status1', ctypes.c_uint32), + ('cp_hqd_hq_control1', ctypes.c_uint32), + ('cp_hqd_eop_base_addr_lo', ctypes.c_uint32), + ('cp_hqd_eop_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_eop_control', ctypes.c_uint32), + ('cp_hqd_eop_rptr', ctypes.c_uint32), + ('cp_hqd_eop_wptr', ctypes.c_uint32), + ('cp_hqd_eop_done_events', ctypes.c_uint32), + ('cp_hqd_ctx_save_base_addr_lo', ctypes.c_uint32), + ('cp_hqd_ctx_save_base_addr_hi', ctypes.c_uint32), + ('cp_hqd_ctx_save_control', ctypes.c_uint32), + ('cp_hqd_cntl_stack_offset', ctypes.c_uint32), + ('cp_hqd_cntl_stack_size', ctypes.c_uint32), + ('cp_hqd_wg_state_offset', ctypes.c_uint32), + ('cp_hqd_ctx_save_size', ctypes.c_uint32), + ('cp_hqd_gds_resource_state', ctypes.c_uint32), + ('cp_hqd_error', ctypes.c_uint32), + ('cp_hqd_eop_wptr_mem', ctypes.c_uint32), + ('cp_hqd_aql_control', ctypes.c_uint32), + ('cp_hqd_pq_wptr_lo', ctypes.c_uint32), + ('cp_hqd_pq_wptr_hi', ctypes.c_uint32), + ('reserved_184', ctypes.c_uint32), + ('reserved_185', ctypes.c_uint32), + ('reserved_186', ctypes.c_uint32), + ('reserved_187', ctypes.c_uint32), + ('reserved_188', ctypes.c_uint32), + ('reserved_189', ctypes.c_uint32), + ('reserved_190', ctypes.c_uint32), + ('reserved_191', ctypes.c_uint32), + ('iqtimer_pkt_header', ctypes.c_uint32), + ('iqtimer_pkt_dw0', ctypes.c_uint32), + ('iqtimer_pkt_dw1', ctypes.c_uint32), + ('iqtimer_pkt_dw2', ctypes.c_uint32), + ('iqtimer_pkt_dw3', ctypes.c_uint32), + ('iqtimer_pkt_dw4', ctypes.c_uint32), + ('iqtimer_pkt_dw5', ctypes.c_uint32), + ('iqtimer_pkt_dw6', ctypes.c_uint32), + ('iqtimer_pkt_dw7', ctypes.c_uint32), + ('iqtimer_pkt_dw8', ctypes.c_uint32), + ('iqtimer_pkt_dw9', ctypes.c_uint32), + ('iqtimer_pkt_dw10', ctypes.c_uint32), + ('iqtimer_pkt_dw11', ctypes.c_uint32), + ('iqtimer_pkt_dw12', ctypes.c_uint32), + ('iqtimer_pkt_dw13', ctypes.c_uint32), + ('iqtimer_pkt_dw14', ctypes.c_uint32), + ('iqtimer_pkt_dw15', ctypes.c_uint32), + ('iqtimer_pkt_dw16', ctypes.c_uint32), + ('iqtimer_pkt_dw17', ctypes.c_uint32), + ('iqtimer_pkt_dw18', ctypes.c_uint32), + ('iqtimer_pkt_dw19', ctypes.c_uint32), + ('iqtimer_pkt_dw20', ctypes.c_uint32), + ('iqtimer_pkt_dw21', ctypes.c_uint32), + ('iqtimer_pkt_dw22', ctypes.c_uint32), + ('iqtimer_pkt_dw23', ctypes.c_uint32), + ('iqtimer_pkt_dw24', ctypes.c_uint32), + ('iqtimer_pkt_dw25', ctypes.c_uint32), + ('iqtimer_pkt_dw26', ctypes.c_uint32), + ('iqtimer_pkt_dw27', ctypes.c_uint32), + ('iqtimer_pkt_dw28', ctypes.c_uint32), + ('iqtimer_pkt_dw29', ctypes.c_uint32), + ('iqtimer_pkt_dw30', ctypes.c_uint32), + ('iqtimer_pkt_dw31', ctypes.c_uint32), + ('reserved_225', ctypes.c_uint32), + ('reserved_226', ctypes.c_uint32), + ('reserved_227', ctypes.c_uint32), + ('set_resources_header', ctypes.c_uint32), + ('set_resources_dw1', ctypes.c_uint32), + ('set_resources_dw2', ctypes.c_uint32), + ('set_resources_dw3', ctypes.c_uint32), + ('set_resources_dw4', ctypes.c_uint32), + ('set_resources_dw5', ctypes.c_uint32), + ('set_resources_dw6', ctypes.c_uint32), + ('set_resources_dw7', ctypes.c_uint32), + ('reserved_236', ctypes.c_uint32), + ('reserved_237', ctypes.c_uint32), + ('reserved_238', ctypes.c_uint32), + ('reserved_239', ctypes.c_uint32), + ('queue_doorbell_id0', ctypes.c_uint32), + ('queue_doorbell_id1', ctypes.c_uint32), + ('queue_doorbell_id2', ctypes.c_uint32), + ('queue_doorbell_id3', ctypes.c_uint32), + ('queue_doorbell_id4', ctypes.c_uint32), + ('queue_doorbell_id5', ctypes.c_uint32), + ('queue_doorbell_id6', ctypes.c_uint32), + ('queue_doorbell_id7', ctypes.c_uint32), + ('queue_doorbell_id8', ctypes.c_uint32), + ('queue_doorbell_id9', ctypes.c_uint32), + ('queue_doorbell_id10', ctypes.c_uint32), + ('queue_doorbell_id11', ctypes.c_uint32), + ('queue_doorbell_id12', ctypes.c_uint32), + ('queue_doorbell_id13', ctypes.c_uint32), + ('queue_doorbell_id14', ctypes.c_uint32), + ('queue_doorbell_id15', ctypes.c_uint32), + ('control_buf_addr_lo', ctypes.c_uint32), + ('control_buf_addr_hi', ctypes.c_uint32), + ('control_buf_wptr_lo', ctypes.c_uint32), + ('control_buf_wptr_hi', ctypes.c_uint32), + ('control_buf_dptr_lo', ctypes.c_uint32), + ('control_buf_dptr_hi', ctypes.c_uint32), + ('control_buf_num_entries', ctypes.c_uint32), + ('draw_ring_addr_lo', ctypes.c_uint32), + ('draw_ring_addr_hi', ctypes.c_uint32), + ('reserved_265', ctypes.c_uint32), + ('reserved_266', ctypes.c_uint32), + ('reserved_267', ctypes.c_uint32), + ('reserved_268', ctypes.c_uint32), + ('reserved_269', ctypes.c_uint32), + ('reserved_270', ctypes.c_uint32), + ('reserved_271', ctypes.c_uint32), + ('reserved_272', ctypes.c_uint32), + ('reserved_273', ctypes.c_uint32), + ('reserved_274', ctypes.c_uint32), + ('reserved_275', ctypes.c_uint32), + ('reserved_276', ctypes.c_uint32), + ('reserved_277', ctypes.c_uint32), + ('reserved_278', ctypes.c_uint32), + ('reserved_279', ctypes.c_uint32), + ('reserved_280', ctypes.c_uint32), + ('reserved_281', ctypes.c_uint32), + ('reserved_282', ctypes.c_uint32), + ('reserved_283', ctypes.c_uint32), + ('reserved_284', ctypes.c_uint32), + ('reserved_285', ctypes.c_uint32), + ('reserved_286', ctypes.c_uint32), + ('reserved_287', ctypes.c_uint32), + ('reserved_288', ctypes.c_uint32), + ('reserved_289', ctypes.c_uint32), + ('reserved_290', ctypes.c_uint32), + ('reserved_291', ctypes.c_uint32), + ('reserved_292', ctypes.c_uint32), + ('reserved_293', ctypes.c_uint32), + ('reserved_294', ctypes.c_uint32), + ('reserved_295', ctypes.c_uint32), + ('reserved_296', ctypes.c_uint32), + ('reserved_297', ctypes.c_uint32), + ('reserved_298', ctypes.c_uint32), + ('reserved_299', ctypes.c_uint32), + ('reserved_300', ctypes.c_uint32), + ('reserved_301', ctypes.c_uint32), + ('reserved_302', ctypes.c_uint32), + ('reserved_303', ctypes.c_uint32), + ('reserved_304', ctypes.c_uint32), + ('reserved_305', ctypes.c_uint32), + ('reserved_306', ctypes.c_uint32), + ('reserved_307', ctypes.c_uint32), + ('reserved_308', ctypes.c_uint32), + ('reserved_309', ctypes.c_uint32), + ('reserved_310', ctypes.c_uint32), + ('reserved_311', ctypes.c_uint32), + ('reserved_312', ctypes.c_uint32), + ('reserved_313', ctypes.c_uint32), + ('reserved_314', ctypes.c_uint32), + ('reserved_315', ctypes.c_uint32), + ('reserved_316', ctypes.c_uint32), + ('reserved_317', ctypes.c_uint32), + ('reserved_318', ctypes.c_uint32), + ('reserved_319', ctypes.c_uint32), + ('reserved_320', ctypes.c_uint32), + ('reserved_321', ctypes.c_uint32), + ('reserved_322', ctypes.c_uint32), + ('reserved_323', ctypes.c_uint32), + ('reserved_324', ctypes.c_uint32), + ('reserved_325', ctypes.c_uint32), + ('reserved_326', ctypes.c_uint32), + ('reserved_327', ctypes.c_uint32), + ('reserved_328', ctypes.c_uint32), + ('reserved_329', ctypes.c_uint32), + ('reserved_330', ctypes.c_uint32), + ('reserved_331', ctypes.c_uint32), + ('reserved_332', ctypes.c_uint32), + ('reserved_333', ctypes.c_uint32), + ('reserved_334', ctypes.c_uint32), + ('reserved_335', ctypes.c_uint32), + ('reserved_336', ctypes.c_uint32), + ('reserved_337', ctypes.c_uint32), + ('reserved_338', ctypes.c_uint32), + ('reserved_339', ctypes.c_uint32), + ('reserved_340', ctypes.c_uint32), + ('reserved_341', ctypes.c_uint32), + ('reserved_342', ctypes.c_uint32), + ('reserved_343', ctypes.c_uint32), + ('reserved_344', ctypes.c_uint32), + ('reserved_345', ctypes.c_uint32), + ('reserved_346', ctypes.c_uint32), + ('reserved_347', ctypes.c_uint32), + ('reserved_348', ctypes.c_uint32), + ('reserved_349', ctypes.c_uint32), + ('reserved_350', ctypes.c_uint32), + ('reserved_351', ctypes.c_uint32), + ('reserved_352', ctypes.c_uint32), + ('reserved_353', ctypes.c_uint32), + ('reserved_354', ctypes.c_uint32), + ('reserved_355', ctypes.c_uint32), + ('reserved_356', ctypes.c_uint32), + ('reserved_357', ctypes.c_uint32), + ('reserved_358', ctypes.c_uint32), + ('reserved_359', ctypes.c_uint32), + ('reserved_360', ctypes.c_uint32), + ('reserved_361', ctypes.c_uint32), + ('reserved_362', ctypes.c_uint32), + ('reserved_363', ctypes.c_uint32), + ('reserved_364', ctypes.c_uint32), + ('reserved_365', ctypes.c_uint32), + ('reserved_366', ctypes.c_uint32), + ('reserved_367', ctypes.c_uint32), + ('reserved_368', ctypes.c_uint32), + ('reserved_369', ctypes.c_uint32), + ('reserved_370', ctypes.c_uint32), + ('reserved_371', ctypes.c_uint32), + ('reserved_372', ctypes.c_uint32), + ('reserved_373', ctypes.c_uint32), + ('reserved_374', ctypes.c_uint32), + ('reserved_375', ctypes.c_uint32), + ('reserved_376', ctypes.c_uint32), + ('reserved_377', ctypes.c_uint32), + ('reserved_378', ctypes.c_uint32), + ('reserved_379', ctypes.c_uint32), + ('reserved_380', ctypes.c_uint32), + ('reserved_381', ctypes.c_uint32), + ('reserved_382', ctypes.c_uint32), + ('reserved_383', ctypes.c_uint32), + ('reserved_384', ctypes.c_uint32), + ('reserved_385', ctypes.c_uint32), + ('reserved_386', ctypes.c_uint32), + ('reserved_387', ctypes.c_uint32), + ('reserved_388', ctypes.c_uint32), + ('reserved_389', ctypes.c_uint32), + ('reserved_390', ctypes.c_uint32), + ('reserved_391', ctypes.c_uint32), + ('reserved_392', ctypes.c_uint32), + ('reserved_393', ctypes.c_uint32), + ('reserved_394', ctypes.c_uint32), + ('reserved_395', ctypes.c_uint32), + ('reserved_396', ctypes.c_uint32), + ('reserved_397', ctypes.c_uint32), + ('reserved_398', ctypes.c_uint32), + ('reserved_399', ctypes.c_uint32), + ('reserved_400', ctypes.c_uint32), + ('reserved_401', ctypes.c_uint32), + ('reserved_402', ctypes.c_uint32), + ('reserved_403', ctypes.c_uint32), + ('reserved_404', ctypes.c_uint32), + ('reserved_405', ctypes.c_uint32), + ('reserved_406', ctypes.c_uint32), + ('reserved_407', ctypes.c_uint32), + ('reserved_408', ctypes.c_uint32), + ('reserved_409', ctypes.c_uint32), + ('reserved_410', ctypes.c_uint32), + ('reserved_411', ctypes.c_uint32), + ('reserved_412', ctypes.c_uint32), + ('reserved_413', ctypes.c_uint32), + ('reserved_414', ctypes.c_uint32), + ('reserved_415', ctypes.c_uint32), + ('reserved_416', ctypes.c_uint32), + ('reserved_417', ctypes.c_uint32), + ('reserved_418', ctypes.c_uint32), + ('reserved_419', ctypes.c_uint32), + ('reserved_420', ctypes.c_uint32), + ('reserved_421', ctypes.c_uint32), + ('reserved_422', ctypes.c_uint32), + ('reserved_423', ctypes.c_uint32), + ('reserved_424', ctypes.c_uint32), + ('reserved_425', ctypes.c_uint32), + ('reserved_426', ctypes.c_uint32), + ('reserved_427', ctypes.c_uint32), + ('reserved_428', ctypes.c_uint32), + ('reserved_429', ctypes.c_uint32), + ('reserved_430', ctypes.c_uint32), + ('reserved_431', ctypes.c_uint32), + ('reserved_432', ctypes.c_uint32), + ('reserved_433', ctypes.c_uint32), + ('reserved_434', ctypes.c_uint32), + ('reserved_435', ctypes.c_uint32), + ('reserved_436', ctypes.c_uint32), + ('reserved_437', ctypes.c_uint32), + ('reserved_438', ctypes.c_uint32), + ('reserved_439', ctypes.c_uint32), + ('reserved_440', ctypes.c_uint32), + ('reserved_441', ctypes.c_uint32), + ('reserved_442', ctypes.c_uint32), + ('reserved_443', ctypes.c_uint32), + ('reserved_444', ctypes.c_uint32), + ('reserved_445', ctypes.c_uint32), + ('reserved_446', ctypes.c_uint32), + ('reserved_447', ctypes.c_uint32), + ('gws_0_val', ctypes.c_uint32), + ('gws_1_val', ctypes.c_uint32), + ('gws_2_val', ctypes.c_uint32), + ('gws_3_val', ctypes.c_uint32), + ('gws_4_val', ctypes.c_uint32), + ('gws_5_val', ctypes.c_uint32), + ('gws_6_val', ctypes.c_uint32), + ('gws_7_val', ctypes.c_uint32), + ('gws_8_val', ctypes.c_uint32), + ('gws_9_val', ctypes.c_uint32), + ('gws_10_val', ctypes.c_uint32), + ('gws_11_val', ctypes.c_uint32), + ('gws_12_val', ctypes.c_uint32), + ('gws_13_val', ctypes.c_uint32), + ('gws_14_val', ctypes.c_uint32), + ('gws_15_val', ctypes.c_uint32), + ('gws_16_val', ctypes.c_uint32), + ('gws_17_val', ctypes.c_uint32), + ('gws_18_val', ctypes.c_uint32), + ('gws_19_val', ctypes.c_uint32), + ('gws_20_val', ctypes.c_uint32), + ('gws_21_val', ctypes.c_uint32), + ('gws_22_val', ctypes.c_uint32), + ('gws_23_val', ctypes.c_uint32), + ('gws_24_val', ctypes.c_uint32), + ('gws_25_val', ctypes.c_uint32), + ('gws_26_val', ctypes.c_uint32), + ('gws_27_val', ctypes.c_uint32), + ('gws_28_val', ctypes.c_uint32), + ('gws_29_val', ctypes.c_uint32), + ('gws_30_val', ctypes.c_uint32), + ('gws_31_val', ctypes.c_uint32), + ('gws_32_val', ctypes.c_uint32), + ('gws_33_val', ctypes.c_uint32), + ('gws_34_val', ctypes.c_uint32), + ('gws_35_val', ctypes.c_uint32), + ('gws_36_val', ctypes.c_uint32), + ('gws_37_val', ctypes.c_uint32), + ('gws_38_val', ctypes.c_uint32), + ('gws_39_val', ctypes.c_uint32), + ('gws_40_val', ctypes.c_uint32), + ('gws_41_val', ctypes.c_uint32), + ('gws_42_val', ctypes.c_uint32), + ('gws_43_val', ctypes.c_uint32), + ('gws_44_val', ctypes.c_uint32), + ('gws_45_val', ctypes.c_uint32), + ('gws_46_val', ctypes.c_uint32), + ('gws_47_val', ctypes.c_uint32), + ('gws_48_val', ctypes.c_uint32), + ('gws_49_val', ctypes.c_uint32), + ('gws_50_val', ctypes.c_uint32), + ('gws_51_val', ctypes.c_uint32), + ('gws_52_val', ctypes.c_uint32), + ('gws_53_val', ctypes.c_uint32), + ('gws_54_val', ctypes.c_uint32), + ('gws_55_val', ctypes.c_uint32), + ('gws_56_val', ctypes.c_uint32), + ('gws_57_val', ctypes.c_uint32), + ('gws_58_val', ctypes.c_uint32), + ('gws_59_val', ctypes.c_uint32), + ('gws_60_val', ctypes.c_uint32), + ('gws_61_val', ctypes.c_uint32), + ('gws_62_val', ctypes.c_uint32), + ('gws_63_val', ctypes.c_uint32), ] - -V12_STRUCTS_H_ = True # macro -class struct_v12_gfx_mqd(Structure): - pass - -struct_v12_gfx_mqd._pack_ = 1 # source:False +class struct_v12_gfx_mqd(Struct): pass +uint32_t = ctypes.c_uint32 struct_v12_gfx_mqd._fields_ = [ - ('shadow_base_lo', ctypes.c_uint32), - ('shadow_base_hi', ctypes.c_uint32), - ('reserved_2', ctypes.c_uint32), - ('reserved_3', ctypes.c_uint32), - ('fw_work_area_base_lo', ctypes.c_uint32), - ('fw_work_area_base_hi', ctypes.c_uint32), - ('shadow_initialized', ctypes.c_uint32), - ('ib_vmid', ctypes.c_uint32), - ('reserved_8', ctypes.c_uint32), - ('reserved_9', ctypes.c_uint32), - ('reserved_10', ctypes.c_uint32), - ('reserved_11', ctypes.c_uint32), - ('reserved_12', ctypes.c_uint32), - ('reserved_13', ctypes.c_uint32), - ('reserved_14', ctypes.c_uint32), - ('reserved_15', ctypes.c_uint32), - ('reserved_16', ctypes.c_uint32), - ('reserved_17', ctypes.c_uint32), - ('reserved_18', ctypes.c_uint32), - ('reserved_19', ctypes.c_uint32), - ('reserved_20', ctypes.c_uint32), - ('reserved_21', ctypes.c_uint32), - ('reserved_22', ctypes.c_uint32), - ('reserved_23', ctypes.c_uint32), - ('reserved_24', ctypes.c_uint32), - ('reserved_25', ctypes.c_uint32), - ('reserved_26', ctypes.c_uint32), - ('reserved_27', ctypes.c_uint32), - ('reserved_28', ctypes.c_uint32), - ('reserved_29', ctypes.c_uint32), - ('reserved_30', ctypes.c_uint32), - ('reserved_31', ctypes.c_uint32), - ('reserved_32', ctypes.c_uint32), - ('reserved_33', ctypes.c_uint32), - ('reserved_34', ctypes.c_uint32), - ('reserved_35', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('reserved_37', ctypes.c_uint32), - ('reserved_38', ctypes.c_uint32), - ('reserved_39', ctypes.c_uint32), - ('reserved_40', ctypes.c_uint32), - ('reserved_41', ctypes.c_uint32), - ('reserved_42', ctypes.c_uint32), - ('reserved_43', ctypes.c_uint32), - ('reserved_44', ctypes.c_uint32), - ('reserved_45', ctypes.c_uint32), - ('reserved_46', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('checksum_lo', ctypes.c_uint32), - ('checksum_hi', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('cp_mqd_query_wave_count', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_mqd_query_gfx_hqd_offset', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('task_shader_control_buf_addr_lo', ctypes.c_uint32), - ('task_shader_control_buf_addr_hi', ctypes.c_uint32), - ('task_shader_read_rptr_lo', ctypes.c_uint32), - ('task_shader_read_rptr_hi', ctypes.c_uint32), - ('task_shader_num_entries', ctypes.c_uint32), - ('task_shader_num_entries_bits', ctypes.c_uint32), - ('task_shader_ring_buffer_addr_lo', ctypes.c_uint32), - ('task_shader_ring_buffer_addr_hi', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_gfx_hqd_active', ctypes.c_uint32), - ('cp_gfx_hqd_vmid', ctypes.c_uint32), - ('reserved_132', ctypes.c_uint32), - ('reserved_133', ctypes.c_uint32), - ('cp_gfx_hqd_queue_priority', ctypes.c_uint32), - ('cp_gfx_hqd_quantum', ctypes.c_uint32), - ('cp_gfx_hqd_base', ctypes.c_uint32), - ('cp_gfx_hqd_base_hi', ctypes.c_uint32), - ('cp_gfx_hqd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr', ctypes.c_uint32), - ('cp_gfx_hqd_rptr_addr_hi', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_rb_doorbell_control', ctypes.c_uint32), - ('cp_gfx_hqd_offset', ctypes.c_uint32), - ('cp_gfx_hqd_cntl', ctypes.c_uint32), - ('reserved_146', ctypes.c_uint32), - ('reserved_147', ctypes.c_uint32), - ('cp_gfx_hqd_csmd_rptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr', ctypes.c_uint32), - ('cp_gfx_hqd_wptr_hi', ctypes.c_uint32), - ('reserved_151', ctypes.c_uint32), - ('reserved_152', ctypes.c_uint32), - ('reserved_153', ctypes.c_uint32), - ('reserved_154', ctypes.c_uint32), - ('reserved_155', ctypes.c_uint32), - ('cp_gfx_hqd_mapped', ctypes.c_uint32), - ('cp_gfx_hqd_que_mgr_control', ctypes.c_uint32), - ('reserved_158', ctypes.c_uint32), - ('reserved_159', ctypes.c_uint32), - ('cp_gfx_hqd_hq_status0', ctypes.c_uint32), - ('cp_gfx_hqd_hq_control0', ctypes.c_uint32), - ('cp_gfx_mqd_control', ctypes.c_uint32), - ('reserved_163', ctypes.c_uint32), - ('reserved_164', ctypes.c_uint32), - ('reserved_165', ctypes.c_uint32), - ('reserved_166', ctypes.c_uint32), - ('reserved_167', ctypes.c_uint32), - ('reserved_168', ctypes.c_uint32), - ('reserved_169', ctypes.c_uint32), - ('reserved_170', ctypes.c_uint32), - ('reserved_171', ctypes.c_uint32), - ('reserved_172', ctypes.c_uint32), - ('reserved_173', ctypes.c_uint32), - ('reserved_174', ctypes.c_uint32), - ('reserved_175', ctypes.c_uint32), - ('reserved_176', ctypes.c_uint32), - ('reserved_177', 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uint32_t), + ('reserved_88', uint32_t), + ('reserved_89', uint32_t), + ('reserved_90', uint32_t), + ('reserved_91', uint32_t), + ('cp_mqd_query_wave_count', uint32_t), + ('cp_mqd_query_gfx_hqd_rptr', uint32_t), + ('cp_mqd_query_gfx_hqd_wptr', uint32_t), + ('cp_mqd_query_gfx_hqd_offset', uint32_t), + ('reserved_96', uint32_t), + ('reserved_97', uint32_t), + ('reserved_98', uint32_t), + ('reserved_99', uint32_t), + ('reserved_100', uint32_t), + ('reserved_101', uint32_t), + ('reserved_102', uint32_t), + ('reserved_103', uint32_t), + ('task_shader_control_buf_addr_lo', uint32_t), + ('task_shader_control_buf_addr_hi', uint32_t), + ('task_shader_read_rptr_lo', uint32_t), + ('task_shader_read_rptr_hi', uint32_t), + ('task_shader_num_entries', uint32_t), + ('task_shader_num_entries_bits', uint32_t), + ('task_shader_ring_buffer_addr_lo', uint32_t), + ('task_shader_ring_buffer_addr_hi', uint32_t), + ('reserved_112', uint32_t), + ('reserved_113', uint32_t), + ('reserved_114', uint32_t), + ('reserved_115', uint32_t), + ('reserved_116', uint32_t), + ('reserved_117', uint32_t), + ('reserved_118', uint32_t), + ('reserved_119', uint32_t), + ('reserved_120', uint32_t), + ('reserved_121', uint32_t), + ('reserved_122', uint32_t), + ('reserved_123', uint32_t), + ('reserved_124', uint32_t), + ('reserved_125', uint32_t), + ('reserved_126', uint32_t), + ('reserved_127', uint32_t), + ('cp_mqd_base_addr', uint32_t), + ('cp_mqd_base_addr_hi', uint32_t), + ('cp_gfx_hqd_active', uint32_t), + ('cp_gfx_hqd_vmid', uint32_t), + ('reserved_132', uint32_t), + ('reserved_133', uint32_t), + ('cp_gfx_hqd_queue_priority', uint32_t), + ('cp_gfx_hqd_quantum', uint32_t), + ('cp_gfx_hqd_base', uint32_t), + ('cp_gfx_hqd_base_hi', uint32_t), + ('cp_gfx_hqd_rptr', uint32_t), + ('cp_gfx_hqd_rptr_addr', uint32_t), + ('cp_gfx_hqd_rptr_addr_hi', uint32_t), + ('cp_rb_wptr_poll_addr_lo', uint32_t), + ('cp_rb_wptr_poll_addr_hi', uint32_t), + ('cp_rb_doorbell_control', uint32_t), + ('cp_gfx_hqd_offset', uint32_t), + ('cp_gfx_hqd_cntl', uint32_t), + ('reserved_146', uint32_t), + ('reserved_147', uint32_t), + ('cp_gfx_hqd_csmd_rptr', uint32_t), + ('cp_gfx_hqd_wptr', uint32_t), + ('cp_gfx_hqd_wptr_hi', uint32_t), + ('reserved_151', uint32_t), + ('reserved_152', uint32_t), + ('reserved_153', uint32_t), + ('reserved_154', uint32_t), + ('reserved_155', uint32_t), + ('cp_gfx_hqd_mapped', uint32_t), + ('cp_gfx_hqd_que_mgr_control', uint32_t), + ('reserved_158', uint32_t), + ('reserved_159', uint32_t), + ('cp_gfx_hqd_hq_status0', uint32_t), + ('cp_gfx_hqd_hq_control0', uint32_t), + ('cp_gfx_mqd_control', uint32_t), + ('reserved_163', uint32_t), + ('reserved_164', uint32_t), + ('reserved_165', uint32_t), + ('reserved_166', uint32_t), + ('reserved_167', uint32_t), + ('reserved_168', uint32_t), + ('reserved_169', uint32_t), + ('reserved_170', uint32_t), + ('reserved_171', uint32_t), + ('reserved_172', uint32_t), + ('reserved_173', uint32_t), + ('reserved_174', uint32_t), + ('reserved_175', uint32_t), + ('reserved_176', uint32_t), + ('reserved_177', uint32_t), + ('reserved_178', uint32_t), + ('reserved_179', uint32_t), + ('reserved_180', uint32_t), + ('reserved_181', uint32_t), + ('reserved_182', uint32_t), + ('reserved_183', uint32_t), + ('reserved_184', uint32_t), + ('reserved_185', uint32_t), + ('reserved_186', uint32_t), + ('reserved_187', uint32_t), + ('reserved_188', uint32_t), + ('reserved_189', uint32_t), + ('reserved_190', uint32_t), + ('reserved_191', uint32_t), + ('reserved_192', uint32_t), + ('reserved_193', uint32_t), + ('reserved_194', uint32_t), + ('reserved_195', uint32_t), + ('reserved_196', uint32_t), + ('reserved_197', uint32_t), + ('reserved_198', uint32_t), + ('reserved_199', uint32_t), + ('reserved_200', uint32_t), + ('reserved_201', uint32_t), + ('reserved_202', uint32_t), + ('reserved_203', uint32_t), + ('reserved_204', uint32_t), + ('reserved_205', uint32_t), + ('reserved_206', uint32_t), + ('reserved_207', uint32_t), + ('reserved_208', uint32_t), + ('reserved_209', uint32_t), + ('reserved_210', uint32_t), + ('reserved_211', uint32_t), + ('reserved_212', uint32_t), + ('reserved_213', uint32_t), + ('reserved_214', uint32_t), + ('reserved_215', uint32_t), + ('reserved_216', uint32_t), + ('reserved_217', uint32_t), + ('reserved_218', uint32_t), + ('reserved_219', uint32_t), + ('reserved_220', uint32_t), + ('reserved_221', uint32_t), + ('reserved_222', uint32_t), + ('reserved_223', uint32_t), + ('reserved_224', uint32_t), + ('reserved_225', uint32_t), + ('reserved_226', uint32_t), + ('reserved_227', uint32_t), + ('reserved_228', uint32_t), + ('reserved_229', uint32_t), + ('reserved_230', uint32_t), + ('reserved_231', uint32_t), + ('reserved_232', uint32_t), + ('reserved_233', uint32_t), + ('reserved_234', uint32_t), + ('reserved_235', uint32_t), + ('reserved_236', uint32_t), + ('reserved_237', uint32_t), + ('reserved_238', uint32_t), + ('reserved_239', uint32_t), + ('reserved_240', uint32_t), + ('reserved_241', uint32_t), + ('reserved_242', uint32_t), + ('reserved_243', uint32_t), + ('reserved_244', uint32_t), + ('reserved_245', uint32_t), + ('reserved_246', uint32_t), + ('reserved_247', uint32_t), + ('reserved_248', uint32_t), + ('reserved_249', uint32_t), + ('reserved_250', uint32_t), + ('reserved_251', uint32_t), + ('reserved_252', uint32_t), + ('reserved_253', uint32_t), + ('reserved_254', uint32_t), + ('reserved_255', uint32_t), + ('reserved_256', uint32_t), + ('reserved_257', uint32_t), + ('reserved_258', uint32_t), + ('reserved_259', uint32_t), + ('reserved_260', uint32_t), + ('reserved_261', uint32_t), + ('reserved_262', uint32_t), + ('reserved_263', uint32_t), + ('reserved_264', uint32_t), + ('reserved_265', uint32_t), + ('reserved_266', uint32_t), + ('reserved_267', uint32_t), + ('reserved_268', uint32_t), + ('reserved_269', uint32_t), + ('reserved_270', uint32_t), + ('reserved_271', uint32_t), + ('dfwx_flags', uint32_t), + ('dfwx_slot', uint32_t), + ('dfwx_client_data_addr_lo', uint32_t), + ('dfwx_client_data_addr_hi', uint32_t), + ('reserved_276', uint32_t), + ('reserved_277', uint32_t), + ('reserved_278', uint32_t), + ('reserved_279', uint32_t), + ('reserved_280', uint32_t), + ('reserved_281', uint32_t), + ('reserved_282', uint32_t), + ('reserved_283', uint32_t), + ('reserved_284', uint32_t), + ('reserved_285', uint32_t), + ('reserved_286', uint32_t), + ('reserved_287', uint32_t), + ('reserved_288', uint32_t), + ('reserved_289', uint32_t), + ('reserved_290', uint32_t), + ('reserved_291', uint32_t), + ('reserved_292', uint32_t), + ('reserved_293', uint32_t), + ('reserved_294', uint32_t), + ('reserved_295', uint32_t), + ('reserved_296', uint32_t), + ('reserved_297', uint32_t), + ('reserved_298', uint32_t), + ('reserved_299', uint32_t), + ('reserved_300', uint32_t), + ('reserved_301', uint32_t), + ('reserved_302', uint32_t), + ('reserved_303', uint32_t), + ('reserved_304', uint32_t), + ('reserved_305', uint32_t), + ('reserved_306', uint32_t), + ('reserved_307', uint32_t), + ('reserved_308', uint32_t), + ('reserved_309', uint32_t), + ('reserved_310', uint32_t), + ('reserved_311', uint32_t), + ('reserved_312', uint32_t), + ('reserved_313', uint32_t), + ('reserved_314', uint32_t), + ('reserved_315', uint32_t), + ('reserved_316', uint32_t), + ('reserved_317', uint32_t), + ('reserved_318', uint32_t), + ('reserved_319', uint32_t), + ('reserved_320', uint32_t), + ('reserved_321', uint32_t), + ('reserved_322', uint32_t), + ('reserved_323', uint32_t), + ('reserved_324', uint32_t), + ('reserved_325', uint32_t), + ('reserved_326', uint32_t), + ('reserved_327', uint32_t), + ('reserved_328', uint32_t), + ('reserved_329', uint32_t), + ('reserved_330', uint32_t), + ('reserved_331', uint32_t), + ('reserved_332', uint32_t), + ('reserved_333', uint32_t), + ('reserved_334', uint32_t), + ('reserved_335', uint32_t), + ('reserved_336', uint32_t), + ('reserved_337', uint32_t), + ('reserved_338', uint32_t), + ('reserved_339', uint32_t), + ('reserved_340', uint32_t), + ('reserved_341', uint32_t), + ('reserved_342', uint32_t), + ('reserved_343', uint32_t), + ('reserved_344', uint32_t), + ('reserved_345', uint32_t), + ('reserved_346', uint32_t), + ('reserved_347', uint32_t), + ('reserved_348', uint32_t), + ('reserved_349', uint32_t), + ('reserved_350', uint32_t), + ('reserved_351', uint32_t), + ('reserved_352', uint32_t), + ('reserved_353', uint32_t), + ('reserved_354', uint32_t), + ('reserved_355', uint32_t), + ('reserved_356', uint32_t), + ('reserved_357', uint32_t), + ('reserved_358', uint32_t), + ('reserved_359', uint32_t), + ('reserved_360', uint32_t), + ('reserved_361', uint32_t), + ('reserved_362', uint32_t), + ('reserved_363', uint32_t), + ('reserved_364', uint32_t), + ('reserved_365', uint32_t), + ('reserved_366', uint32_t), + ('reserved_367', uint32_t), + ('reserved_368', uint32_t), + ('reserved_369', uint32_t), + ('reserved_370', uint32_t), + ('reserved_371', uint32_t), + ('reserved_372', uint32_t), + ('reserved_373', uint32_t), + ('reserved_374', uint32_t), + ('reserved_375', uint32_t), + ('reserved_376', uint32_t), + ('reserved_377', uint32_t), + ('reserved_378', uint32_t), + ('reserved_379', uint32_t), + ('reserved_380', uint32_t), + ('reserved_381', uint32_t), + ('reserved_382', uint32_t), + ('reserved_383', uint32_t), + ('reserved_384', uint32_t), + ('reserved_385', uint32_t), + ('reserved_386', uint32_t), + ('reserved_387', uint32_t), + ('reserved_388', uint32_t), + ('reserved_389', uint32_t), + ('reserved_390', uint32_t), + ('reserved_391', uint32_t), + ('reserved_392', uint32_t), + ('reserved_393', uint32_t), + ('reserved_394', uint32_t), + ('reserved_395', uint32_t), + ('reserved_396', uint32_t), + ('reserved_397', uint32_t), + ('reserved_398', uint32_t), + ('reserved_399', uint32_t), + ('reserved_400', uint32_t), + ('reserved_401', uint32_t), + ('reserved_402', uint32_t), + ('reserved_403', uint32_t), + ('reserved_404', uint32_t), + ('reserved_405', uint32_t), + ('reserved_406', uint32_t), + ('reserved_407', uint32_t), + ('reserved_408', uint32_t), + ('reserved_409', uint32_t), + ('reserved_410', uint32_t), + ('reserved_411', uint32_t), + ('reserved_412', uint32_t), + ('reserved_413', uint32_t), + ('reserved_414', uint32_t), + ('reserved_415', uint32_t), + ('reserved_416', uint32_t), + ('reserved_417', uint32_t), + ('reserved_418', uint32_t), + ('reserved_419', uint32_t), + ('reserved_420', uint32_t), + ('reserved_421', uint32_t), + ('reserved_422', uint32_t), + ('reserved_423', uint32_t), + ('reserved_424', uint32_t), + ('reserved_425', uint32_t), + ('reserved_426', uint32_t), + ('reserved_427', uint32_t), + ('reserved_428', uint32_t), + ('reserved_429', uint32_t), + ('reserved_430', uint32_t), + ('reserved_431', uint32_t), + ('reserved_432', uint32_t), + ('reserved_433', uint32_t), + ('reserved_434', uint32_t), + ('reserved_435', uint32_t), + ('reserved_436', uint32_t), + ('reserved_437', uint32_t), + ('reserved_438', uint32_t), + ('reserved_439', uint32_t), + ('reserved_440', uint32_t), + ('reserved_441', uint32_t), + ('reserved_442', uint32_t), + ('reserved_443', uint32_t), + ('reserved_444', uint32_t), + ('reserved_445', uint32_t), + ('reserved_446', uint32_t), + ('reserved_447', uint32_t), + ('reserved_448', uint32_t), + ('reserved_449', uint32_t), + ('reserved_450', uint32_t), + ('reserved_451', uint32_t), + ('reserved_452', uint32_t), + ('reserved_453', uint32_t), + ('reserved_454', uint32_t), + ('reserved_455', uint32_t), + ('reserved_456', uint32_t), + ('reserved_457', uint32_t), + ('reserved_458', uint32_t), + ('reserved_459', uint32_t), + ('reserved_460', uint32_t), + ('reserved_461', uint32_t), + ('reserved_462', uint32_t), + ('reserved_463', uint32_t), + ('reserved_464', uint32_t), + ('reserved_465', uint32_t), + ('reserved_466', uint32_t), + ('reserved_467', uint32_t), + ('reserved_468', uint32_t), + ('reserved_469', uint32_t), + ('reserved_470', uint32_t), + ('reserved_471', uint32_t), + ('reserved_472', uint32_t), + ('reserved_473', uint32_t), + ('reserved_474', uint32_t), + ('reserved_475', uint32_t), + ('reserved_476', uint32_t), + ('reserved_477', uint32_t), + ('reserved_478', uint32_t), + ('reserved_479', uint32_t), + ('reserved_480', uint32_t), + ('reserved_481', uint32_t), + ('reserved_482', uint32_t), + ('reserved_483', uint32_t), + ('reserved_484', uint32_t), + ('reserved_485', uint32_t), + ('reserved_486', uint32_t), + ('reserved_487', uint32_t), + ('reserved_488', uint32_t), + ('reserved_489', uint32_t), + ('reserved_490', uint32_t), + ('reserved_491', uint32_t), + ('reserved_492', uint32_t), + ('reserved_493', uint32_t), + ('reserved_494', uint32_t), + ('reserved_495', uint32_t), + ('reserved_496', uint32_t), + ('reserved_497', uint32_t), + ('reserved_498', uint32_t), + ('reserved_499', uint32_t), + ('reserved_500', uint32_t), + ('reserved_501', uint32_t), + ('reserved_502', uint32_t), + ('reserved_503', uint32_t), + ('reserved_504', uint32_t), + ('reserved_505', uint32_t), + ('reserved_506', uint32_t), + ('reserved_507', uint32_t), + ('reserved_508', uint32_t), + ('reserved_509', uint32_t), + ('reserved_510', uint32_t), + ('reserved_511', uint32_t), ] - -class struct_v12_sdma_mqd(Structure): - pass - -struct_v12_sdma_mqd._pack_ = 1 # source:False +class struct_v12_sdma_mqd(Struct): pass struct_v12_sdma_mqd._fields_ = [ - ('sdmax_rlcx_rb_cntl', ctypes.c_uint32), - ('sdmax_rlcx_rb_base', ctypes.c_uint32), - ('sdmax_rlcx_rb_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_rb_rptr_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_ib_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_rptr', ctypes.c_uint32), - ('sdmax_rlcx_ib_offset', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_lo', ctypes.c_uint32), - ('sdmax_rlcx_ib_base_hi', ctypes.c_uint32), - ('sdmax_rlcx_ib_size', ctypes.c_uint32), - ('sdmax_rlcx_doorbell', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_log', ctypes.c_uint32), - ('sdmax_rlcx_doorbell_offset', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_csa_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_sched_cntl', ctypes.c_uint32), - ('sdmax_rlcx_ib_sub_remain', ctypes.c_uint32), - ('sdmax_rlcx_preempt', ctypes.c_uint32), - ('sdmax_rlcx_dummy_reg', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_rb_wptr_poll_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_rb_aql_cntl', ctypes.c_uint32), - ('sdmax_rlcx_minor_ptr_update', ctypes.c_uint32), - ('sdmax_rlcx_mcu_dbg0', ctypes.c_uint32), - ('sdmax_rlcx_mcu_dbg1', ctypes.c_uint32), - ('sdmax_rlcx_context_switch_status', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_cntl', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data0', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data1', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data2', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data3', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data4', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data5', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data6', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data7', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data8', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data9', ctypes.c_uint32), - ('sdmax_rlcx_midcmd_data10', ctypes.c_uint32), - ('sdmax_rlcx_wait_unsatisfied_thd', ctypes.c_uint32), - ('sdmax_rlcx_mqd_base_addr_lo', ctypes.c_uint32), - ('sdmax_rlcx_mqd_base_addr_hi', ctypes.c_uint32), - ('sdmax_rlcx_mqd_control', ctypes.c_uint32), - ('reserved_47', ctypes.c_uint32), - ('reserved_48', ctypes.c_uint32), - ('reserved_49', ctypes.c_uint32), - ('reserved_50', ctypes.c_uint32), - ('reserved_51', ctypes.c_uint32), - ('reserved_52', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('reserved_59', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('reserved_65', ctypes.c_uint32), - ('reserved_66', ctypes.c_uint32), - ('reserved_67', ctypes.c_uint32), - ('reserved_68', ctypes.c_uint32), - ('reserved_69', ctypes.c_uint32), - ('reserved_70', ctypes.c_uint32), - ('reserved_71', ctypes.c_uint32), - ('reserved_72', ctypes.c_uint32), - ('reserved_73', ctypes.c_uint32), - ('reserved_74', ctypes.c_uint32), - ('reserved_75', ctypes.c_uint32), - ('reserved_76', ctypes.c_uint32), - ('reserved_77', ctypes.c_uint32), - ('reserved_78', ctypes.c_uint32), - ('reserved_79', ctypes.c_uint32), - ('reserved_80', ctypes.c_uint32), - ('reserved_81', ctypes.c_uint32), - ('reserved_82', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('reserved_86', ctypes.c_uint32), - ('reserved_87', ctypes.c_uint32), - ('reserved_88', ctypes.c_uint32), - ('reserved_89', ctypes.c_uint32), - ('reserved_90', ctypes.c_uint32), - ('reserved_91', ctypes.c_uint32), - ('reserved_92', ctypes.c_uint32), - ('reserved_93', ctypes.c_uint32), - ('reserved_94', ctypes.c_uint32), - ('reserved_95', ctypes.c_uint32), - ('reserved_96', ctypes.c_uint32), - ('reserved_97', ctypes.c_uint32), - ('reserved_98', ctypes.c_uint32), - ('reserved_99', ctypes.c_uint32), - ('reserved_100', ctypes.c_uint32), - ('reserved_101', ctypes.c_uint32), - ('reserved_102', ctypes.c_uint32), - ('reserved_103', ctypes.c_uint32), - ('reserved_104', ctypes.c_uint32), - ('reserved_105', ctypes.c_uint32), - ('reserved_106', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('reserved_114', ctypes.c_uint32), - ('reserved_115', ctypes.c_uint32), - ('reserved_116', ctypes.c_uint32), - ('reserved_117', ctypes.c_uint32), - ('reserved_118', ctypes.c_uint32), - ('reserved_119', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('reserved_124', ctypes.c_uint32), - ('reserved_125', ctypes.c_uint32), - ('sdma_engine_id', ctypes.c_uint32), - ('sdma_queue_id', ctypes.c_uint32), + ('sdmax_rlcx_rb_cntl', uint32_t), + ('sdmax_rlcx_rb_base', uint32_t), + ('sdmax_rlcx_rb_base_hi', uint32_t), + ('sdmax_rlcx_rb_rptr', uint32_t), + ('sdmax_rlcx_rb_rptr_hi', uint32_t), + ('sdmax_rlcx_rb_wptr', uint32_t), + ('sdmax_rlcx_rb_wptr_hi', uint32_t), + ('sdmax_rlcx_rb_rptr_addr_lo', uint32_t), + ('sdmax_rlcx_rb_rptr_addr_hi', uint32_t), + ('sdmax_rlcx_ib_cntl', uint32_t), + ('sdmax_rlcx_ib_rptr', uint32_t), + ('sdmax_rlcx_ib_offset', uint32_t), + ('sdmax_rlcx_ib_base_lo', uint32_t), + ('sdmax_rlcx_ib_base_hi', uint32_t), + ('sdmax_rlcx_ib_size', uint32_t), + ('sdmax_rlcx_doorbell', uint32_t), + ('sdmax_rlcx_doorbell_log', uint32_t), + ('sdmax_rlcx_doorbell_offset', uint32_t), + ('sdmax_rlcx_csa_addr_lo', uint32_t), + ('sdmax_rlcx_csa_addr_hi', uint32_t), + ('sdmax_rlcx_sched_cntl', uint32_t), + ('sdmax_rlcx_ib_sub_remain', uint32_t), + ('sdmax_rlcx_preempt', uint32_t), + ('sdmax_rlcx_dummy_reg', uint32_t), + ('sdmax_rlcx_rb_wptr_poll_addr_lo', uint32_t), + ('sdmax_rlcx_rb_wptr_poll_addr_hi', uint32_t), + ('sdmax_rlcx_rb_aql_cntl', uint32_t), + ('sdmax_rlcx_minor_ptr_update', uint32_t), + ('sdmax_rlcx_mcu_dbg0', uint32_t), + ('sdmax_rlcx_mcu_dbg1', uint32_t), + ('sdmax_rlcx_context_switch_status', uint32_t), + ('sdmax_rlcx_midcmd_cntl', uint32_t), + ('sdmax_rlcx_midcmd_data0', uint32_t), + ('sdmax_rlcx_midcmd_data1', uint32_t), + ('sdmax_rlcx_midcmd_data2', uint32_t), + ('sdmax_rlcx_midcmd_data3', uint32_t), + ('sdmax_rlcx_midcmd_data4', uint32_t), + ('sdmax_rlcx_midcmd_data5', uint32_t), + ('sdmax_rlcx_midcmd_data6', uint32_t), + ('sdmax_rlcx_midcmd_data7', uint32_t), + ('sdmax_rlcx_midcmd_data8', uint32_t), + ('sdmax_rlcx_midcmd_data9', uint32_t), + ('sdmax_rlcx_midcmd_data10', uint32_t), + ('sdmax_rlcx_wait_unsatisfied_thd', uint32_t), + ('sdmax_rlcx_mqd_base_addr_lo', uint32_t), + ('sdmax_rlcx_mqd_base_addr_hi', uint32_t), + ('sdmax_rlcx_mqd_control', uint32_t), + ('reserved_47', uint32_t), + ('reserved_48', uint32_t), + ('reserved_49', uint32_t), + ('reserved_50', uint32_t), + ('reserved_51', uint32_t), + ('reserved_52', uint32_t), + ('reserved_53', uint32_t), + ('reserved_54', uint32_t), + ('reserved_55', uint32_t), + ('reserved_56', uint32_t), + ('reserved_57', uint32_t), + ('reserved_58', uint32_t), + ('reserved_59', uint32_t), + ('reserved_60', uint32_t), + ('reserved_61', uint32_t), + ('reserved_62', uint32_t), + ('reserved_63', uint32_t), + ('reserved_64', uint32_t), + ('reserved_65', uint32_t), + ('reserved_66', uint32_t), + ('reserved_67', uint32_t), + ('reserved_68', uint32_t), + ('reserved_69', uint32_t), + ('reserved_70', uint32_t), + ('reserved_71', uint32_t), + ('reserved_72', uint32_t), + ('reserved_73', uint32_t), + ('reserved_74', uint32_t), + ('reserved_75', uint32_t), + ('reserved_76', uint32_t), + ('reserved_77', uint32_t), + ('reserved_78', uint32_t), + ('reserved_79', uint32_t), + ('reserved_80', uint32_t), + ('reserved_81', uint32_t), + ('reserved_82', uint32_t), + ('reserved_83', uint32_t), + ('reserved_84', uint32_t), + ('reserved_85', uint32_t), + ('reserved_86', uint32_t), + ('reserved_87', uint32_t), + ('reserved_88', uint32_t), + ('reserved_89', uint32_t), + ('reserved_90', uint32_t), + ('reserved_91', uint32_t), + ('reserved_92', uint32_t), + ('reserved_93', uint32_t), + ('reserved_94', uint32_t), + ('reserved_95', uint32_t), + ('reserved_96', uint32_t), + ('reserved_97', uint32_t), + ('reserved_98', uint32_t), + ('reserved_99', uint32_t), + ('reserved_100', uint32_t), + ('reserved_101', uint32_t), + ('reserved_102', uint32_t), + ('reserved_103', uint32_t), + ('reserved_104', uint32_t), + ('reserved_105', uint32_t), + ('reserved_106', uint32_t), + ('reserved_107', uint32_t), + ('reserved_108', uint32_t), + ('reserved_109', uint32_t), + ('reserved_110', uint32_t), + ('reserved_111', uint32_t), + ('reserved_112', uint32_t), + ('reserved_113', uint32_t), + ('reserved_114', uint32_t), + ('reserved_115', uint32_t), + ('reserved_116', uint32_t), + ('reserved_117', uint32_t), + ('reserved_118', uint32_t), + ('reserved_119', uint32_t), + ('reserved_120', uint32_t), + ('reserved_121', uint32_t), + ('reserved_122', uint32_t), + ('reserved_123', uint32_t), + ('reserved_124', uint32_t), + ('reserved_125', uint32_t), + ('sdma_engine_id', uint32_t), + ('sdma_queue_id', uint32_t), ] - -class struct_v12_compute_mqd(Structure): - pass - -struct_v12_compute_mqd._pack_ = 1 # source:False +class struct_v12_compute_mqd(Struct): pass struct_v12_compute_mqd._fields_ = [ - ('header', ctypes.c_uint32), - ('compute_dispatch_initiator', ctypes.c_uint32), - ('compute_dim_x', ctypes.c_uint32), - ('compute_dim_y', ctypes.c_uint32), - ('compute_dim_z', ctypes.c_uint32), - ('compute_start_x', ctypes.c_uint32), - ('compute_start_y', ctypes.c_uint32), - ('compute_start_z', ctypes.c_uint32), - ('compute_num_thread_x', ctypes.c_uint32), - ('compute_num_thread_y', ctypes.c_uint32), - ('compute_num_thread_z', ctypes.c_uint32), - ('compute_pipelinestat_enable', ctypes.c_uint32), - ('compute_perfcount_enable', ctypes.c_uint32), - ('compute_pgm_lo', ctypes.c_uint32), - ('compute_pgm_hi', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_lo', ctypes.c_uint32), - ('compute_dispatch_pkt_addr_hi', ctypes.c_uint32), - ('compute_dispatch_scratch_base_lo', ctypes.c_uint32), - ('compute_dispatch_scratch_base_hi', ctypes.c_uint32), - ('compute_pgm_rsrc1', ctypes.c_uint32), - ('compute_pgm_rsrc2', ctypes.c_uint32), - ('compute_vmid', ctypes.c_uint32), - ('compute_resource_limits', ctypes.c_uint32), - ('compute_static_thread_mgmt_se0', ctypes.c_uint32), - ('compute_static_thread_mgmt_se1', ctypes.c_uint32), - ('compute_tmpring_size', ctypes.c_uint32), - ('compute_static_thread_mgmt_se2', ctypes.c_uint32), - ('compute_static_thread_mgmt_se3', ctypes.c_uint32), - ('compute_restart_x', ctypes.c_uint32), - ('compute_restart_y', ctypes.c_uint32), - ('compute_restart_z', ctypes.c_uint32), - ('compute_thread_trace_enable', ctypes.c_uint32), - ('compute_misc_reserved', ctypes.c_uint32), - ('compute_dispatch_id', ctypes.c_uint32), - ('compute_threadgroup_id', ctypes.c_uint32), - ('compute_req_ctrl', ctypes.c_uint32), - ('reserved_36', ctypes.c_uint32), - ('compute_user_accum_0', ctypes.c_uint32), - ('compute_user_accum_1', ctypes.c_uint32), - ('compute_user_accum_2', ctypes.c_uint32), - ('compute_user_accum_3', ctypes.c_uint32), - ('compute_pgm_rsrc3', ctypes.c_uint32), - ('compute_ddid_index', ctypes.c_uint32), - ('compute_shader_chksum', ctypes.c_uint32), - ('compute_static_thread_mgmt_se4', ctypes.c_uint32), - ('compute_static_thread_mgmt_se5', ctypes.c_uint32), - ('compute_static_thread_mgmt_se6', ctypes.c_uint32), - ('compute_static_thread_mgmt_se7', ctypes.c_uint32), - ('compute_dispatch_interleave', ctypes.c_uint32), - ('compute_relaunch', ctypes.c_uint32), - ('compute_wave_restore_addr_lo', ctypes.c_uint32), - ('compute_wave_restore_addr_hi', ctypes.c_uint32), - ('compute_wave_restore_control', ctypes.c_uint32), - ('reserved_53', ctypes.c_uint32), - ('reserved_54', ctypes.c_uint32), - ('reserved_55', ctypes.c_uint32), - ('reserved_56', ctypes.c_uint32), - ('reserved_57', ctypes.c_uint32), - ('reserved_58', ctypes.c_uint32), - ('compute_static_thread_mgmt_se8', ctypes.c_uint32), - ('reserved_60', ctypes.c_uint32), - ('reserved_61', ctypes.c_uint32), - ('reserved_62', ctypes.c_uint32), - ('reserved_63', ctypes.c_uint32), - ('reserved_64', ctypes.c_uint32), - ('compute_user_data_0', ctypes.c_uint32), - ('compute_user_data_1', ctypes.c_uint32), - ('compute_user_data_2', ctypes.c_uint32), - ('compute_user_data_3', ctypes.c_uint32), - ('compute_user_data_4', ctypes.c_uint32), - ('compute_user_data_5', ctypes.c_uint32), - ('compute_user_data_6', ctypes.c_uint32), - ('compute_user_data_7', ctypes.c_uint32), - ('compute_user_data_8', ctypes.c_uint32), - ('compute_user_data_9', ctypes.c_uint32), - ('compute_user_data_10', ctypes.c_uint32), - ('compute_user_data_11', ctypes.c_uint32), - ('compute_user_data_12', ctypes.c_uint32), - ('compute_user_data_13', ctypes.c_uint32), - ('compute_user_data_14', ctypes.c_uint32), - ('compute_user_data_15', ctypes.c_uint32), - ('cp_compute_csinvoc_count_lo', ctypes.c_uint32), - ('cp_compute_csinvoc_count_hi', ctypes.c_uint32), - ('reserved_83', ctypes.c_uint32), - ('reserved_84', ctypes.c_uint32), - ('reserved_85', ctypes.c_uint32), - ('cp_mqd_query_time_lo', ctypes.c_uint32), - ('cp_mqd_query_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_start_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_start_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_time_lo', ctypes.c_uint32), - ('cp_mqd_connect_end_time_hi', ctypes.c_uint32), - ('cp_mqd_connect_end_wf_count', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_rptr', ctypes.c_uint32), - ('cp_mqd_connect_end_pq_wptr', ctypes.c_uint32), - ('cp_mqd_connect_end_ib_rptr', ctypes.c_uint32), - ('cp_mqd_readindex_lo', ctypes.c_uint32), - ('cp_mqd_readindex_hi', ctypes.c_uint32), - ('cp_mqd_save_start_time_lo', ctypes.c_uint32), - ('cp_mqd_save_start_time_hi', ctypes.c_uint32), - ('cp_mqd_save_end_time_lo', ctypes.c_uint32), - ('cp_mqd_save_end_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_start_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_start_time_hi', ctypes.c_uint32), - ('cp_mqd_restore_end_time_lo', ctypes.c_uint32), - ('cp_mqd_restore_end_time_hi', ctypes.c_uint32), - ('disable_queue', ctypes.c_uint32), - ('reserved_107', ctypes.c_uint32), - ('reserved_108', ctypes.c_uint32), - ('reserved_109', ctypes.c_uint32), - ('reserved_110', ctypes.c_uint32), - ('reserved_111', ctypes.c_uint32), - ('reserved_112', ctypes.c_uint32), - ('reserved_113', ctypes.c_uint32), - ('cp_pq_exe_status_lo', ctypes.c_uint32), - ('cp_pq_exe_status_hi', ctypes.c_uint32), - ('cp_packet_id_lo', ctypes.c_uint32), - ('cp_packet_id_hi', ctypes.c_uint32), - ('cp_packet_exe_status_lo', ctypes.c_uint32), - ('cp_packet_exe_status_hi', ctypes.c_uint32), - ('reserved_120', ctypes.c_uint32), - ('reserved_121', ctypes.c_uint32), - ('reserved_122', ctypes.c_uint32), - ('reserved_123', ctypes.c_uint32), - ('ctx_save_base_addr_lo', ctypes.c_uint32), - ('ctx_save_base_addr_hi', ctypes.c_uint32), - ('reserved_126', ctypes.c_uint32), - ('reserved_127', ctypes.c_uint32), - ('cp_mqd_base_addr_lo', ctypes.c_uint32), - ('cp_mqd_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_active', ctypes.c_uint32), - ('cp_hqd_vmid', ctypes.c_uint32), - ('cp_hqd_persistent_state', ctypes.c_uint32), - ('cp_hqd_pipe_priority', ctypes.c_uint32), - ('cp_hqd_queue_priority', ctypes.c_uint32), - ('cp_hqd_quantum', ctypes.c_uint32), - ('cp_hqd_pq_base_lo', ctypes.c_uint32), - ('cp_hqd_pq_base_hi', ctypes.c_uint32), - ('cp_hqd_pq_rptr', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_rptr_report_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_poll_addr_hi', ctypes.c_uint32), - ('cp_hqd_pq_doorbell_control', ctypes.c_uint32), - ('reserved_144', ctypes.c_uint32), - ('cp_hqd_pq_control', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ib_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ib_rptr', ctypes.c_uint32), - ('cp_hqd_ib_control', ctypes.c_uint32), - ('cp_hqd_iq_timer', ctypes.c_uint32), - ('cp_hqd_iq_rptr', ctypes.c_uint32), - ('cp_hqd_dequeue_request', ctypes.c_uint32), - ('cp_hqd_dma_offload', ctypes.c_uint32), - ('cp_hqd_sema_cmd', ctypes.c_uint32), - ('cp_hqd_msg_type', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic0_preop_hi', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_lo', ctypes.c_uint32), - ('cp_hqd_atomic1_preop_hi', ctypes.c_uint32), - ('cp_hqd_hq_status0', ctypes.c_uint32), - ('cp_hqd_hq_control0', ctypes.c_uint32), - ('cp_mqd_control', ctypes.c_uint32), - ('cp_hqd_hq_status1', ctypes.c_uint32), - ('cp_hqd_hq_control1', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_eop_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_eop_control', ctypes.c_uint32), - ('cp_hqd_eop_rptr', ctypes.c_uint32), - ('cp_hqd_eop_wptr', ctypes.c_uint32), - ('cp_hqd_eop_done_events', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_lo', ctypes.c_uint32), - ('cp_hqd_ctx_save_base_addr_hi', ctypes.c_uint32), - ('cp_hqd_ctx_save_control', ctypes.c_uint32), - ('cp_hqd_cntl_stack_offset', ctypes.c_uint32), - ('cp_hqd_cntl_stack_size', ctypes.c_uint32), - ('cp_hqd_wg_state_offset', ctypes.c_uint32), - ('cp_hqd_ctx_save_size', ctypes.c_uint32), - ('reserved_178', ctypes.c_uint32), - ('cp_hqd_error', ctypes.c_uint32), - ('cp_hqd_eop_wptr_mem', ctypes.c_uint32), - ('cp_hqd_aql_control', ctypes.c_uint32), - ('cp_hqd_pq_wptr_lo', ctypes.c_uint32), - ('cp_hqd_pq_wptr_hi', ctypes.c_uint32), - ('reserved_184', ctypes.c_uint32), - ('reserved_185', ctypes.c_uint32), - ('reserved_186', ctypes.c_uint32), - ('reserved_187', ctypes.c_uint32), - ('reserved_188', ctypes.c_uint32), - ('reserved_189', ctypes.c_uint32), - ('reserved_190', ctypes.c_uint32), - ('reserved_191', ctypes.c_uint32), - ('iqtimer_pkt_header', ctypes.c_uint32), - ('iqtimer_pkt_dw0', ctypes.c_uint32), - ('iqtimer_pkt_dw1', ctypes.c_uint32), - ('iqtimer_pkt_dw2', ctypes.c_uint32), - ('iqtimer_pkt_dw3', ctypes.c_uint32), - ('iqtimer_pkt_dw4', ctypes.c_uint32), - ('iqtimer_pkt_dw5', ctypes.c_uint32), - ('iqtimer_pkt_dw6', ctypes.c_uint32), - ('iqtimer_pkt_dw7', ctypes.c_uint32), - ('iqtimer_pkt_dw8', ctypes.c_uint32), - ('iqtimer_pkt_dw9', ctypes.c_uint32), - ('iqtimer_pkt_dw10', ctypes.c_uint32), - ('iqtimer_pkt_dw11', ctypes.c_uint32), - ('iqtimer_pkt_dw12', ctypes.c_uint32), - ('iqtimer_pkt_dw13', ctypes.c_uint32), - ('iqtimer_pkt_dw14', ctypes.c_uint32), - ('iqtimer_pkt_dw15', ctypes.c_uint32), - ('iqtimer_pkt_dw16', ctypes.c_uint32), - ('iqtimer_pkt_dw17', ctypes.c_uint32), - ('iqtimer_pkt_dw18', ctypes.c_uint32), - ('iqtimer_pkt_dw19', ctypes.c_uint32), - ('iqtimer_pkt_dw20', ctypes.c_uint32), - ('iqtimer_pkt_dw21', ctypes.c_uint32), - ('iqtimer_pkt_dw22', ctypes.c_uint32), - ('iqtimer_pkt_dw23', ctypes.c_uint32), - ('iqtimer_pkt_dw24', ctypes.c_uint32), - ('iqtimer_pkt_dw25', ctypes.c_uint32), - ('iqtimer_pkt_dw26', ctypes.c_uint32), - ('iqtimer_pkt_dw27', ctypes.c_uint32), - ('iqtimer_pkt_dw28', ctypes.c_uint32), - ('iqtimer_pkt_dw29', ctypes.c_uint32), - ('iqtimer_pkt_dw30', ctypes.c_uint32), - ('iqtimer_pkt_dw31', ctypes.c_uint32), - ('reserved_225', ctypes.c_uint32), - ('reserved_226', ctypes.c_uint32), - ('reserved_227', ctypes.c_uint32), - ('set_resources_header', ctypes.c_uint32), - ('set_resources_dw1', ctypes.c_uint32), - ('set_resources_dw2', ctypes.c_uint32), - ('set_resources_dw3', ctypes.c_uint32), - ('set_resources_dw4', ctypes.c_uint32), - ('set_resources_dw5', ctypes.c_uint32), - ('set_resources_dw6', ctypes.c_uint32), - ('set_resources_dw7', ctypes.c_uint32), - ('reserved_236', ctypes.c_uint32), - ('reserved_237', ctypes.c_uint32), - ('reserved_238', ctypes.c_uint32), - ('reserved_239', ctypes.c_uint32), - ('queue_doorbell_id0', ctypes.c_uint32), - ('queue_doorbell_id1', ctypes.c_uint32), - ('queue_doorbell_id2', ctypes.c_uint32), - ('queue_doorbell_id3', ctypes.c_uint32), - ('queue_doorbell_id4', ctypes.c_uint32), - ('queue_doorbell_id5', ctypes.c_uint32), - ('queue_doorbell_id6', ctypes.c_uint32), - ('queue_doorbell_id7', ctypes.c_uint32), - ('queue_doorbell_id8', ctypes.c_uint32), - ('queue_doorbell_id9', ctypes.c_uint32), - ('queue_doorbell_id10', ctypes.c_uint32), - ('queue_doorbell_id11', ctypes.c_uint32), - ('queue_doorbell_id12', ctypes.c_uint32), - ('queue_doorbell_id13', ctypes.c_uint32), - ('queue_doorbell_id14', ctypes.c_uint32), - ('queue_doorbell_id15', ctypes.c_uint32), - ('control_buf_addr_lo', ctypes.c_uint32), - ('control_buf_addr_hi', ctypes.c_uint32), - ('control_buf_wptr_lo', ctypes.c_uint32), - ('control_buf_wptr_hi', ctypes.c_uint32), - ('control_buf_dptr_lo', ctypes.c_uint32), - ('control_buf_dptr_hi', ctypes.c_uint32), - ('control_buf_num_entries', ctypes.c_uint32), - ('draw_ring_addr_lo', ctypes.c_uint32), - ('draw_ring_addr_hi', ctypes.c_uint32), - ('reserved_265', ctypes.c_uint32), - ('reserved_266', ctypes.c_uint32), - ('reserved_267', ctypes.c_uint32), - ('reserved_268', ctypes.c_uint32), - ('reserved_269', ctypes.c_uint32), - ('reserved_270', ctypes.c_uint32), - ('reserved_271', ctypes.c_uint32), - ('dfwx_flags', ctypes.c_uint32), - ('dfwx_slot', ctypes.c_uint32), - ('dfwx_client_data_addr_lo', ctypes.c_uint32), - ('dfwx_client_data_addr_hi', ctypes.c_uint32), - ('reserved_276', ctypes.c_uint32), - ('reserved_277', ctypes.c_uint32), - ('reserved_278', ctypes.c_uint32), - ('reserved_279', ctypes.c_uint32), - ('reserved_280', ctypes.c_uint32), - ('reserved_281', ctypes.c_uint32), - ('reserved_282', ctypes.c_uint32), - ('reserved_283', ctypes.c_uint32), - ('reserved_284', ctypes.c_uint32), - ('reserved_285', ctypes.c_uint32), - ('reserved_286', ctypes.c_uint32), - ('reserved_287', ctypes.c_uint32), - ('reserved_288', ctypes.c_uint32), - ('reserved_289', ctypes.c_uint32), - ('reserved_290', ctypes.c_uint32), - ('reserved_291', ctypes.c_uint32), - ('reserved_292', ctypes.c_uint32), - ('reserved_293', ctypes.c_uint32), - ('reserved_294', ctypes.c_uint32), - ('reserved_295', ctypes.c_uint32), - ('reserved_296', ctypes.c_uint32), - ('reserved_297', ctypes.c_uint32), - ('reserved_298', ctypes.c_uint32), - ('reserved_299', ctypes.c_uint32), - ('reserved_300', ctypes.c_uint32), - ('reserved_301', ctypes.c_uint32), - ('reserved_302', ctypes.c_uint32), - ('reserved_303', ctypes.c_uint32), - ('reserved_304', ctypes.c_uint32), - ('reserved_305', ctypes.c_uint32), - ('reserved_306', ctypes.c_uint32), - ('reserved_307', ctypes.c_uint32), - ('reserved_308', ctypes.c_uint32), - ('reserved_309', ctypes.c_uint32), - ('reserved_310', ctypes.c_uint32), - ('reserved_311', ctypes.c_uint32), - ('reserved_312', ctypes.c_uint32), - ('reserved_313', ctypes.c_uint32), - ('reserved_314', ctypes.c_uint32), - ('reserved_315', ctypes.c_uint32), - ('reserved_316', ctypes.c_uint32), - ('reserved_317', ctypes.c_uint32), - ('reserved_318', ctypes.c_uint32), - ('reserved_319', ctypes.c_uint32), - ('reserved_320', ctypes.c_uint32), - ('reserved_321', ctypes.c_uint32), - ('reserved_322', ctypes.c_uint32), - ('reserved_323', ctypes.c_uint32), - ('reserved_324', ctypes.c_uint32), - ('reserved_325', ctypes.c_uint32), - ('reserved_326', ctypes.c_uint32), - ('reserved_327', ctypes.c_uint32), - ('reserved_328', ctypes.c_uint32), - ('reserved_329', ctypes.c_uint32), - ('reserved_330', ctypes.c_uint32), - ('reserved_331', ctypes.c_uint32), - ('reserved_332', ctypes.c_uint32), - ('reserved_333', ctypes.c_uint32), - ('reserved_334', ctypes.c_uint32), - ('reserved_335', ctypes.c_uint32), - ('reserved_336', ctypes.c_uint32), - ('reserved_337', ctypes.c_uint32), - ('reserved_338', ctypes.c_uint32), - ('reserved_339', ctypes.c_uint32), - ('reserved_340', ctypes.c_uint32), - ('reserved_341', ctypes.c_uint32), - ('reserved_342', ctypes.c_uint32), - ('reserved_343', ctypes.c_uint32), - ('reserved_344', ctypes.c_uint32), - ('reserved_345', ctypes.c_uint32), - ('reserved_346', ctypes.c_uint32), - ('reserved_347', ctypes.c_uint32), - ('reserved_348', ctypes.c_uint32), - ('reserved_349', ctypes.c_uint32), - ('reserved_350', ctypes.c_uint32), - ('reserved_351', ctypes.c_uint32), - ('reserved_352', ctypes.c_uint32), - ('reserved_353', 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('reserved_58', uint32_t), + ('compute_static_thread_mgmt_se8', uint32_t), + ('reserved_60', uint32_t), + ('reserved_61', uint32_t), + ('reserved_62', uint32_t), + ('reserved_63', uint32_t), + ('reserved_64', uint32_t), + ('compute_user_data_0', uint32_t), + ('compute_user_data_1', uint32_t), + ('compute_user_data_2', uint32_t), + ('compute_user_data_3', uint32_t), + ('compute_user_data_4', uint32_t), + ('compute_user_data_5', uint32_t), + ('compute_user_data_6', uint32_t), + ('compute_user_data_7', uint32_t), + ('compute_user_data_8', uint32_t), + ('compute_user_data_9', uint32_t), + ('compute_user_data_10', uint32_t), + ('compute_user_data_11', uint32_t), + ('compute_user_data_12', uint32_t), + ('compute_user_data_13', uint32_t), + ('compute_user_data_14', uint32_t), + ('compute_user_data_15', uint32_t), + ('cp_compute_csinvoc_count_lo', uint32_t), + ('cp_compute_csinvoc_count_hi', uint32_t), + ('reserved_83', uint32_t), + ('reserved_84', uint32_t), + ('reserved_85', uint32_t), + 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uint32_t), + ('reserved_111', uint32_t), + ('reserved_112', uint32_t), + ('reserved_113', uint32_t), + ('cp_pq_exe_status_lo', uint32_t), + ('cp_pq_exe_status_hi', uint32_t), + ('cp_packet_id_lo', uint32_t), + ('cp_packet_id_hi', uint32_t), + ('cp_packet_exe_status_lo', uint32_t), + ('cp_packet_exe_status_hi', uint32_t), + ('reserved_120', uint32_t), + ('reserved_121', uint32_t), + ('reserved_122', uint32_t), + ('reserved_123', uint32_t), + ('ctx_save_base_addr_lo', uint32_t), + ('ctx_save_base_addr_hi', uint32_t), + ('reserved_126', uint32_t), + ('reserved_127', uint32_t), + ('cp_mqd_base_addr_lo', uint32_t), + ('cp_mqd_base_addr_hi', uint32_t), + ('cp_hqd_active', uint32_t), + ('cp_hqd_vmid', uint32_t), + ('cp_hqd_persistent_state', uint32_t), + ('cp_hqd_pipe_priority', uint32_t), + ('cp_hqd_queue_priority', uint32_t), + ('cp_hqd_quantum', uint32_t), + ('cp_hqd_pq_base_lo', uint32_t), + ('cp_hqd_pq_base_hi', uint32_t), + ('cp_hqd_pq_rptr', uint32_t), + ('cp_hqd_pq_rptr_report_addr_lo', uint32_t), + ('cp_hqd_pq_rptr_report_addr_hi', uint32_t), + ('cp_hqd_pq_wptr_poll_addr_lo', uint32_t), + ('cp_hqd_pq_wptr_poll_addr_hi', uint32_t), + ('cp_hqd_pq_doorbell_control', uint32_t), + ('reserved_144', uint32_t), + ('cp_hqd_pq_control', uint32_t), + ('cp_hqd_ib_base_addr_lo', uint32_t), + ('cp_hqd_ib_base_addr_hi', uint32_t), + ('cp_hqd_ib_rptr', uint32_t), + ('cp_hqd_ib_control', uint32_t), + ('cp_hqd_iq_timer', uint32_t), + ('cp_hqd_iq_rptr', uint32_t), + ('cp_hqd_dequeue_request', uint32_t), + ('cp_hqd_dma_offload', uint32_t), + ('cp_hqd_sema_cmd', uint32_t), + ('cp_hqd_msg_type', uint32_t), + ('cp_hqd_atomic0_preop_lo', uint32_t), + ('cp_hqd_atomic0_preop_hi', uint32_t), + ('cp_hqd_atomic1_preop_lo', uint32_t), + ('cp_hqd_atomic1_preop_hi', uint32_t), + ('cp_hqd_hq_status0', uint32_t), + ('cp_hqd_hq_control0', uint32_t), + ('cp_mqd_control', uint32_t), + ('cp_hqd_hq_status1', uint32_t), + ('cp_hqd_hq_control1', uint32_t), + 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('iqtimer_pkt_dw0', uint32_t), + ('iqtimer_pkt_dw1', uint32_t), + ('iqtimer_pkt_dw2', uint32_t), + ('iqtimer_pkt_dw3', uint32_t), + ('iqtimer_pkt_dw4', uint32_t), + ('iqtimer_pkt_dw5', uint32_t), + ('iqtimer_pkt_dw6', uint32_t), + ('iqtimer_pkt_dw7', uint32_t), + ('iqtimer_pkt_dw8', uint32_t), + ('iqtimer_pkt_dw9', uint32_t), + ('iqtimer_pkt_dw10', uint32_t), + ('iqtimer_pkt_dw11', uint32_t), + ('iqtimer_pkt_dw12', uint32_t), + ('iqtimer_pkt_dw13', uint32_t), + ('iqtimer_pkt_dw14', uint32_t), + ('iqtimer_pkt_dw15', uint32_t), + ('iqtimer_pkt_dw16', uint32_t), + ('iqtimer_pkt_dw17', uint32_t), + ('iqtimer_pkt_dw18', uint32_t), + ('iqtimer_pkt_dw19', uint32_t), + ('iqtimer_pkt_dw20', uint32_t), + ('iqtimer_pkt_dw21', uint32_t), + ('iqtimer_pkt_dw22', uint32_t), + ('iqtimer_pkt_dw23', uint32_t), + ('iqtimer_pkt_dw24', uint32_t), + ('iqtimer_pkt_dw25', uint32_t), + ('iqtimer_pkt_dw26', uint32_t), + ('iqtimer_pkt_dw27', uint32_t), + ('iqtimer_pkt_dw28', uint32_t), + ('iqtimer_pkt_dw29', uint32_t), + ('iqtimer_pkt_dw30', uint32_t), + ('iqtimer_pkt_dw31', uint32_t), + ('reserved_225', uint32_t), + ('reserved_226', uint32_t), + ('reserved_227', uint32_t), + ('set_resources_header', uint32_t), + ('set_resources_dw1', uint32_t), + ('set_resources_dw2', uint32_t), + ('set_resources_dw3', uint32_t), + ('set_resources_dw4', uint32_t), + ('set_resources_dw5', uint32_t), + ('set_resources_dw6', uint32_t), + ('set_resources_dw7', uint32_t), + ('reserved_236', uint32_t), + ('reserved_237', uint32_t), + ('reserved_238', uint32_t), + ('reserved_239', uint32_t), + ('queue_doorbell_id0', uint32_t), + ('queue_doorbell_id1', uint32_t), + ('queue_doorbell_id2', uint32_t), + ('queue_doorbell_id3', uint32_t), + ('queue_doorbell_id4', uint32_t), + ('queue_doorbell_id5', uint32_t), + ('queue_doorbell_id6', uint32_t), + ('queue_doorbell_id7', uint32_t), + ('queue_doorbell_id8', uint32_t), + ('queue_doorbell_id9', uint32_t), + ('queue_doorbell_id10', uint32_t), + ('queue_doorbell_id11', uint32_t), + ('queue_doorbell_id12', uint32_t), + ('queue_doorbell_id13', uint32_t), + ('queue_doorbell_id14', uint32_t), + ('queue_doorbell_id15', uint32_t), + ('control_buf_addr_lo', uint32_t), + ('control_buf_addr_hi', uint32_t), + ('control_buf_wptr_lo', uint32_t), + ('control_buf_wptr_hi', uint32_t), + ('control_buf_dptr_lo', uint32_t), + ('control_buf_dptr_hi', uint32_t), + ('control_buf_num_entries', uint32_t), + ('draw_ring_addr_lo', uint32_t), + ('draw_ring_addr_hi', uint32_t), + ('reserved_265', uint32_t), + ('reserved_266', uint32_t), + ('reserved_267', uint32_t), + ('reserved_268', uint32_t), + ('reserved_269', uint32_t), + ('reserved_270', uint32_t), + ('reserved_271', uint32_t), + ('dfwx_flags', uint32_t), + ('dfwx_slot', uint32_t), + ('dfwx_client_data_addr_lo', uint32_t), + ('dfwx_client_data_addr_hi', uint32_t), + ('reserved_276', uint32_t), + ('reserved_277', uint32_t), + ('reserved_278', uint32_t), + ('reserved_279', uint32_t), + ('reserved_280', uint32_t), + ('reserved_281', uint32_t), + ('reserved_282', uint32_t), + ('reserved_283', uint32_t), + ('reserved_284', uint32_t), + ('reserved_285', uint32_t), + ('reserved_286', uint32_t), + ('reserved_287', uint32_t), + ('reserved_288', uint32_t), + ('reserved_289', uint32_t), + ('reserved_290', uint32_t), + ('reserved_291', uint32_t), + ('reserved_292', uint32_t), + ('reserved_293', uint32_t), + ('reserved_294', uint32_t), + ('reserved_295', uint32_t), + ('reserved_296', uint32_t), + ('reserved_297', uint32_t), + ('reserved_298', uint32_t), + ('reserved_299', uint32_t), + ('reserved_300', uint32_t), + ('reserved_301', uint32_t), + ('reserved_302', uint32_t), + ('reserved_303', uint32_t), + ('reserved_304', uint32_t), + ('reserved_305', uint32_t), + ('reserved_306', uint32_t), + ('reserved_307', uint32_t), + ('reserved_308', uint32_t), + ('reserved_309', uint32_t), + ('reserved_310', uint32_t), + ('reserved_311', uint32_t), + ('reserved_312', uint32_t), + ('reserved_313', uint32_t), + ('reserved_314', uint32_t), + ('reserved_315', uint32_t), + ('reserved_316', uint32_t), + ('reserved_317', uint32_t), + ('reserved_318', uint32_t), + ('reserved_319', uint32_t), + ('reserved_320', uint32_t), + ('reserved_321', uint32_t), + ('reserved_322', uint32_t), + ('reserved_323', uint32_t), + ('reserved_324', uint32_t), + ('reserved_325', uint32_t), + ('reserved_326', uint32_t), + ('reserved_327', uint32_t), + ('reserved_328', uint32_t), + ('reserved_329', uint32_t), + ('reserved_330', uint32_t), + ('reserved_331', uint32_t), + ('reserved_332', uint32_t), + ('reserved_333', uint32_t), + ('reserved_334', uint32_t), + ('reserved_335', uint32_t), + ('reserved_336', uint32_t), + ('reserved_337', uint32_t), + ('reserved_338', uint32_t), + ('reserved_339', uint32_t), + ('reserved_340', uint32_t), + ('reserved_341', uint32_t), + ('reserved_342', uint32_t), + ('reserved_343', uint32_t), + ('reserved_344', uint32_t), + ('reserved_345', uint32_t), + ('reserved_346', uint32_t), + ('reserved_347', uint32_t), + ('reserved_348', uint32_t), + ('reserved_349', uint32_t), + ('reserved_350', uint32_t), + ('reserved_351', uint32_t), + ('reserved_352', uint32_t), + ('reserved_353', uint32_t), + ('reserved_354', uint32_t), + ('reserved_355', uint32_t), + ('reserved_356', uint32_t), + ('reserved_357', uint32_t), + ('reserved_358', uint32_t), + ('reserved_359', uint32_t), + ('reserved_360', uint32_t), + ('reserved_361', uint32_t), + ('reserved_362', uint32_t), + ('reserved_363', uint32_t), + ('reserved_364', uint32_t), + ('reserved_365', uint32_t), + ('reserved_366', uint32_t), + ('reserved_367', uint32_t), + ('reserved_368', uint32_t), + ('reserved_369', uint32_t), + ('reserved_370', uint32_t), + ('reserved_371', uint32_t), + ('reserved_372', uint32_t), + ('reserved_373', uint32_t), + ('reserved_374', uint32_t), + ('reserved_375', uint32_t), + ('reserved_376', uint32_t), + ('reserved_377', uint32_t), + ('reserved_378', uint32_t), + ('reserved_379', uint32_t), + ('reserved_380', uint32_t), + ('reserved_381', uint32_t), + ('reserved_382', uint32_t), + ('reserved_383', uint32_t), + ('reserved_384', uint32_t), + ('reserved_385', uint32_t), + ('reserved_386', uint32_t), + ('reserved_387', uint32_t), + ('reserved_388', uint32_t), + ('reserved_389', uint32_t), + ('reserved_390', uint32_t), + ('reserved_391', uint32_t), + ('reserved_392', uint32_t), + ('reserved_393', uint32_t), + ('reserved_394', uint32_t), + ('reserved_395', uint32_t), + ('reserved_396', uint32_t), + ('reserved_397', uint32_t), + ('reserved_398', uint32_t), + ('reserved_399', uint32_t), + ('reserved_400', uint32_t), + ('reserved_401', uint32_t), + ('reserved_402', uint32_t), + ('reserved_403', uint32_t), + ('reserved_404', uint32_t), + ('reserved_405', uint32_t), + ('reserved_406', uint32_t), + ('reserved_407', uint32_t), + ('reserved_408', uint32_t), + ('reserved_409', uint32_t), + ('reserved_410', uint32_t), + ('reserved_411', uint32_t), + ('reserved_412', uint32_t), + ('reserved_413', uint32_t), + ('reserved_414', uint32_t), + ('reserved_415', uint32_t), + ('reserved_416', uint32_t), + ('reserved_417', uint32_t), + ('reserved_418', uint32_t), + ('reserved_419', uint32_t), + ('reserved_420', uint32_t), + ('reserved_421', uint32_t), + ('reserved_422', uint32_t), + ('reserved_423', uint32_t), + ('reserved_424', uint32_t), + ('reserved_425', uint32_t), + ('reserved_426', uint32_t), + ('reserved_427', uint32_t), + ('reserved_428', uint32_t), + ('reserved_429', uint32_t), + ('reserved_430', uint32_t), + ('reserved_431', uint32_t), + ('reserved_432', uint32_t), + ('reserved_433', uint32_t), + ('reserved_434', uint32_t), + ('reserved_435', uint32_t), + ('reserved_436', uint32_t), + ('reserved_437', uint32_t), + ('reserved_438', uint32_t), + ('reserved_439', uint32_t), + ('reserved_440', uint32_t), + ('reserved_441', uint32_t), + ('reserved_442', uint32_t), + ('reserved_443', uint32_t), + ('reserved_444', uint32_t), + ('reserved_445', uint32_t), + ('reserved_446', uint32_t), + ('reserved_447', uint32_t), + ('gws_0_val', uint32_t), + ('gws_1_val', uint32_t), + ('gws_2_val', uint32_t), + ('gws_3_val', uint32_t), + ('gws_4_val', uint32_t), + ('gws_5_val', uint32_t), + ('gws_6_val', uint32_t), + ('gws_7_val', uint32_t), + ('gws_8_val', uint32_t), + ('gws_9_val', uint32_t), + ('gws_10_val', uint32_t), + ('gws_11_val', uint32_t), + ('gws_12_val', uint32_t), + ('gws_13_val', uint32_t), + ('gws_14_val', uint32_t), + ('gws_15_val', uint32_t), + ('gws_16_val', uint32_t), + ('gws_17_val', uint32_t), + ('gws_18_val', uint32_t), + ('gws_19_val', uint32_t), + ('gws_20_val', uint32_t), + ('gws_21_val', uint32_t), + ('gws_22_val', uint32_t), + ('gws_23_val', uint32_t), + ('gws_24_val', uint32_t), + ('gws_25_val', uint32_t), + ('gws_26_val', uint32_t), + ('gws_27_val', uint32_t), + ('gws_28_val', uint32_t), + ('gws_29_val', uint32_t), + ('gws_30_val', uint32_t), + ('gws_31_val', uint32_t), + ('gws_32_val', uint32_t), + ('gws_33_val', uint32_t), + ('gws_34_val', uint32_t), + ('gws_35_val', uint32_t), + ('gws_36_val', uint32_t), + ('gws_37_val', uint32_t), + ('gws_38_val', uint32_t), + ('gws_39_val', uint32_t), + ('gws_40_val', uint32_t), + ('gws_41_val', uint32_t), + ('gws_42_val', uint32_t), + ('gws_43_val', uint32_t), + ('gws_44_val', uint32_t), + ('gws_45_val', uint32_t), + ('gws_46_val', uint32_t), + ('gws_47_val', uint32_t), + ('gws_48_val', uint32_t), + ('gws_49_val', uint32_t), + ('gws_50_val', uint32_t), + ('gws_51_val', uint32_t), + ('gws_52_val', uint32_t), + ('gws_53_val', uint32_t), + ('gws_54_val', uint32_t), + ('gws_55_val', uint32_t), + ('gws_56_val', uint32_t), + ('gws_57_val', uint32_t), + ('gws_58_val', uint32_t), + ('gws_59_val', uint32_t), + ('gws_60_val', uint32_t), + ('gws_61_val', uint32_t), + ('gws_62_val', uint32_t), + ('gws_63_val', uint32_t), ] +enum_amdgpu_vm_level = CEnum(ctypes.c_uint32) +AMDGPU_VM_PDB2 = enum_amdgpu_vm_level.define('AMDGPU_VM_PDB2', 0) +AMDGPU_VM_PDB1 = enum_amdgpu_vm_level.define('AMDGPU_VM_PDB1', 1) +AMDGPU_VM_PDB0 = enum_amdgpu_vm_level.define('AMDGPU_VM_PDB0', 2) +AMDGPU_VM_PTB = enum_amdgpu_vm_level.define('AMDGPU_VM_PTB', 3) -__AMDGPU_VM_H__ = True # macro -AMDGPU_VM_MAX_UPDATE_SIZE = 0x3FFFF # macro -# def AMDGPU_VM_PTE_COUNT(adev): # macro -# return (1<<(adev)->vm_manager.block_size) -AMDGPU_PTE_VALID = (1<<0) # macro -AMDGPU_PTE_SYSTEM = (1<<1) # macro -AMDGPU_PTE_SNOOPED = (1<<2) # macro -AMDGPU_PTE_TMZ = (1<<3) # macro -AMDGPU_PTE_EXECUTABLE = (1<<4) # macro -AMDGPU_PTE_READABLE = (1<<5) # macro -AMDGPU_PTE_WRITEABLE = (1<<6) # macro -def AMDGPU_PTE_FRAG(x): # macro - return ((x&0x1f)<<7) -AMDGPU_PTE_PRT = (1<<51) # macro -AMDGPU_PDE_PTE = (1<<54) # macro -AMDGPU_PTE_LOG = (1<<55) # macro -AMDGPU_PTE_TF = (1<<56) # macro -AMDGPU_PTE_NOALLOC = (1<<58) # macro -def AMDGPU_PDE_BFS(a): # macro - return ( a<<59) -AMDGPU_VM_NORETRY_FLAGS = ((1<<4)|(1<<54)|(1<<56)) # macro -AMDGPU_VM_NORETRY_FLAGS_TF = ((1<<0)|(1<<1)|(1<<51)) # macro -def AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype): # macro - return ( (mtype)<<57) -AMDGPU_PTE_MTYPE_VG10_MASK = AMDGPU_PTE_MTYPE_VG10_SHIFT ( 3 ) # macro -def AMDGPU_PTE_MTYPE_VG10(flags, mtype): # macro - return (( (flags)&(~AMDGPU_PTE_MTYPE_VG10_SHIFT(3)))|AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) -AMDGPU_MTYPE_NC = 0 # macro -AMDGPU_MTYPE_CC = 2 # macro -AMDGPU_PTE_DEFAULT_ATC = ((1<<1)|(1<<2)|(1<<4)|(1<<5)|(1<<6)|AMDGPU_PTE_MTYPE_VG10(0, 2)) # macro -def AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype): # macro - return ( (mtype)<<48) -AMDGPU_PTE_MTYPE_NV10_MASK = AMDGPU_PTE_MTYPE_NV10_SHIFT ( 7 ) # macro -def AMDGPU_PTE_MTYPE_NV10(flags, mtype): # macro - return (( (flags)&(~AMDGPU_PTE_MTYPE_NV10_SHIFT(7)))|AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) -AMDGPU_PTE_PRT_GFX12 = (1<<56) # macro -def AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype): # macro - return ( (mtype)<<54) -AMDGPU_PTE_MTYPE_GFX12_MASK = AMDGPU_PTE_MTYPE_GFX12_SHIFT ( 3 ) # macro -def AMDGPU_PTE_MTYPE_GFX12(flags, mtype): # macro - return (( (flags)&(~AMDGPU_PTE_MTYPE_GFX12_SHIFT(3)))|AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) -AMDGPU_PTE_IS_PTE = (1<<63) # macro -def AMDGPU_PDE_BFS_GFX12(a): # macro - return ( ((a)&0x1f)<<58) -AMDGPU_PDE_PTE_GFX12 = (1<<63) # macro -AMDGPU_VM_FAULT_STOP_NEVER = 0 # macro -AMDGPU_VM_FAULT_STOP_FIRST = 1 # macro -AMDGPU_VM_FAULT_STOP_ALWAYS = 2 # macro -AMDGPU_VM_RESERVED_VRAM = (8<<20) # macro -AMDGPU_MAX_VMHUBS = 13 # macro -AMDGPU_GFXHUB_START = 0 # macro -AMDGPU_MMHUB0_START = 8 # macro -AMDGPU_MMHUB1_START = 12 # macro -def AMDGPU_GFXHUB(x): # macro - return (0+(x)) -def AMDGPU_MMHUB0(x): # macro - return (8+(x)) -def AMDGPU_MMHUB1(x): # macro - return (12+(x)) -def AMDGPU_IS_GFXHUB(x): # macro - return ((x)>=0 and (x)<8) -def AMDGPU_IS_MMHUB0(x): # macro - return ((x)>=8 and (x)<12) -def AMDGPU_IS_MMHUB1(x): # macro - return ((x)>=12 and (x)<13) -AMDGPU_VA_RESERVED_CSA_SIZE = (2<<20) # macro -# def AMDGPU_VA_RESERVED_CSA_START(adev): # macro -# return (((adev)->vm_manager.max_pfn<=IP_VERSION(12,0,0))?(1<<56):(1<<51)) -# def AMDGPU_PDE_BFS_FLAG(adev, a): # macro -# return ((amdgpu_ip_version((adev),GC_HWIP,0)>=IP_VERSION(12,0,0))?AMDGPU_PDE_BFS_GFX12(a):AMDGPU_PDE_BFS(a)) -# def AMDGPU_PDE_PTE_FLAG(adev): # macro -# return ((amdgpu_ip_version((adev),GC_HWIP,0)>=IP_VERSION(12,0,0))?(1<<63):(1<<54)) -hw_id_map = [['GC_HWIP', '11'],['HDP_HWIP', '41'],['SDMA0_HWIP', '42'],['SDMA1_HWIP', '43'],['SDMA2_HWIP', '68'],['SDMA3_HWIP', '69'],['LSDMA_HWIP', '91'],['MMHUB_HWIP', '34'],['ATHUB_HWIP', '35'],['NBIO_HWIP', '108'],['MP0_HWIP', '255'],['MP1_HWIP', '1'],['UVD_HWIP', '12'],['VCE_HWIP', '32'],['DF_HWIP', '46'],['DCE_HWIP', '271'],['OSSSYS_HWIP', '40'],['SMUIO_HWIP', '4'],['PWR_HWIP', '10'],['NBIF_HWIP', '108'],['THM_HWIP', '3'],['CLK_HWIP', '6'],['UMC_HWIP', '150'],['XGMI_HWIP', '200'],['DCI_HWIP', '15'],['PCIE_HWIP', '70'],['VPE_HWIP', '21'],['ISP_HWIP', '44']] # Variable ctypes.c_int32 * 35 -__AMDGPU_UCODE_H__ = True # macro -int32_t = True # macro -int8_t = True # macro -int16_t = True # macro -bool = True # macro -u32 = True # macro -AMDGPU_SDMA0_UCODE_LOADED = 0x00000001 # macro -AMDGPU_SDMA1_UCODE_LOADED = 0x00000002 # macro -AMDGPU_CPCE_UCODE_LOADED = 0x00000004 # macro -AMDGPU_CPPFP_UCODE_LOADED = 0x00000008 # macro -AMDGPU_CPME_UCODE_LOADED = 0x00000010 # macro -AMDGPU_CPMEC1_UCODE_LOADED = 0x00000020 # macro -AMDGPU_CPMEC2_UCODE_LOADED = 0x00000040 # macro -AMDGPU_CPRLC_UCODE_LOADED = 0x00000100 # macro -class struct_common_firmware_header(Structure): - pass - -struct_common_firmware_header._pack_ = 1 # source:False +class struct_common_firmware_header(Struct): pass struct_common_firmware_header._fields_ = [ - ('size_bytes', ctypes.c_uint32), - ('header_size_bytes', ctypes.c_uint32), - ('header_version_major', ctypes.c_uint16), - ('header_version_minor', ctypes.c_uint16), - ('ip_version_major', ctypes.c_uint16), - ('ip_version_minor', ctypes.c_uint16), - ('ucode_version', ctypes.c_uint32), - ('ucode_size_bytes', ctypes.c_uint32), - ('ucode_array_offset_bytes', ctypes.c_uint32), - ('crc32', ctypes.c_uint32), + ('size_bytes', ctypes.c_uint32), + ('header_size_bytes', ctypes.c_uint32), + ('header_version_major', ctypes.c_uint16), + ('header_version_minor', ctypes.c_uint16), + ('ip_version_major', ctypes.c_uint16), + ('ip_version_minor', ctypes.c_uint16), + ('ucode_version', ctypes.c_uint32), + ('ucode_size_bytes', ctypes.c_uint32), + ('ucode_array_offset_bytes', ctypes.c_uint32), + ('crc32', ctypes.c_uint32), ] - -class struct_mc_firmware_header_v1_0(Structure): - pass - -struct_mc_firmware_header_v1_0._pack_ = 1 # source:False +class struct_mc_firmware_header_v1_0(Struct): pass struct_mc_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('io_debug_size_bytes', ctypes.c_uint32), - ('io_debug_array_offset_bytes', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('io_debug_size_bytes', ctypes.c_uint32), + ('io_debug_array_offset_bytes', ctypes.c_uint32), ] - -class struct_smc_firmware_header_v1_0(Structure): - pass - -struct_smc_firmware_header_v1_0._pack_ = 1 # source:False +class struct_smc_firmware_header_v1_0(Struct): pass struct_smc_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_start_addr', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_start_addr', ctypes.c_uint32), ] - -class struct_smc_firmware_header_v2_0(Structure): - pass - -struct_smc_firmware_header_v2_0._pack_ = 1 # source:False +class struct_smc_firmware_header_v2_0(Struct): pass struct_smc_firmware_header_v2_0._fields_ = [ - ('v1_0', struct_smc_firmware_header_v1_0), - ('ppt_offset_bytes', ctypes.c_uint32), - ('ppt_size_bytes', ctypes.c_uint32), + ('v1_0', struct_smc_firmware_header_v1_0), + ('ppt_offset_bytes', ctypes.c_uint32), + ('ppt_size_bytes', ctypes.c_uint32), ] - -class struct_smc_soft_pptable_entry(Structure): - pass - -struct_smc_soft_pptable_entry._pack_ = 1 # source:False +class struct_smc_soft_pptable_entry(Struct): pass struct_smc_soft_pptable_entry._fields_ = [ - ('id', ctypes.c_uint32), - ('ppt_offset_bytes', ctypes.c_uint32), - ('ppt_size_bytes', ctypes.c_uint32), + ('id', ctypes.c_uint32), + ('ppt_offset_bytes', ctypes.c_uint32), + ('ppt_size_bytes', ctypes.c_uint32), ] - -class struct_smc_firmware_header_v2_1(Structure): - pass - -struct_smc_firmware_header_v2_1._pack_ = 1 # source:False +class struct_smc_firmware_header_v2_1(Struct): pass struct_smc_firmware_header_v2_1._fields_ = [ - ('v1_0', struct_smc_firmware_header_v1_0), - ('pptable_count', ctypes.c_uint32), - ('pptable_entry_offset', ctypes.c_uint32), + ('v1_0', struct_smc_firmware_header_v1_0), + ('pptable_count', ctypes.c_uint32), + ('pptable_entry_offset', ctypes.c_uint32), ] - -class struct_psp_fw_legacy_bin_desc(Structure): - pass - -struct_psp_fw_legacy_bin_desc._pack_ = 1 # source:False +class struct_psp_fw_legacy_bin_desc(Struct): pass struct_psp_fw_legacy_bin_desc._fields_ = [ - ('fw_version', ctypes.c_uint32), - ('offset_bytes', ctypes.c_uint32), - ('size_bytes', ctypes.c_uint32), + ('fw_version', ctypes.c_uint32), + ('offset_bytes', ctypes.c_uint32), + ('size_bytes', ctypes.c_uint32), ] - -class struct_psp_firmware_header_v1_0(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('header', struct_common_firmware_header), - ('sos', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_firmware_header_v1_1(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('v1_0', struct_psp_firmware_header_v1_0), - ('toc', struct_psp_fw_legacy_bin_desc), - ('kdb', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_firmware_header_v1_2(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('v1_0', struct_psp_firmware_header_v1_0), - ('res', struct_psp_fw_legacy_bin_desc), - ('kdb', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_firmware_header_v1_3(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('v1_1', struct_psp_firmware_header_v1_1), - ('spl', struct_psp_fw_legacy_bin_desc), - ('rl', struct_psp_fw_legacy_bin_desc), - ('sys_drv_aux', struct_psp_fw_legacy_bin_desc), - ('sos_aux', struct_psp_fw_legacy_bin_desc), - ] - -class struct_psp_fw_bin_desc(Structure): - pass - -struct_psp_fw_bin_desc._pack_ = 1 # source:False +class struct_psp_firmware_header_v1_0(Struct): pass +struct_psp_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('sos', struct_psp_fw_legacy_bin_desc), +] +class struct_psp_firmware_header_v1_1(Struct): pass +struct_psp_firmware_header_v1_1._fields_ = [ + ('v1_0', struct_psp_firmware_header_v1_0), + ('toc', struct_psp_fw_legacy_bin_desc), + ('kdb', struct_psp_fw_legacy_bin_desc), +] +class struct_psp_firmware_header_v1_2(Struct): pass +struct_psp_firmware_header_v1_2._fields_ = [ + ('v1_0', struct_psp_firmware_header_v1_0), + ('res', struct_psp_fw_legacy_bin_desc), + ('kdb', struct_psp_fw_legacy_bin_desc), +] +class struct_psp_firmware_header_v1_3(Struct): pass +struct_psp_firmware_header_v1_3._fields_ = [ + ('v1_1', struct_psp_firmware_header_v1_1), + ('spl', struct_psp_fw_legacy_bin_desc), + ('rl', struct_psp_fw_legacy_bin_desc), + ('sys_drv_aux', struct_psp_fw_legacy_bin_desc), + ('sos_aux', struct_psp_fw_legacy_bin_desc), +] +class struct_psp_fw_bin_desc(Struct): pass struct_psp_fw_bin_desc._fields_ = [ - ('fw_type', ctypes.c_uint32), - ('fw_version', ctypes.c_uint32), - ('offset_bytes', ctypes.c_uint32), - ('size_bytes', ctypes.c_uint32), + ('fw_type', ctypes.c_uint32), + ('fw_version', ctypes.c_uint32), + ('offset_bytes', ctypes.c_uint32), + ('size_bytes', ctypes.c_uint32), ] +enum_psp_fw_type = CEnum(ctypes.c_uint32) +PSP_FW_TYPE_UNKOWN = enum_psp_fw_type.define('PSP_FW_TYPE_UNKOWN', 0) +PSP_FW_TYPE_PSP_SOS = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_SOS', 1) +PSP_FW_TYPE_PSP_SYS_DRV = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_SYS_DRV', 2) +PSP_FW_TYPE_PSP_KDB = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_KDB', 3) +PSP_FW_TYPE_PSP_TOC = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_TOC', 4) +PSP_FW_TYPE_PSP_SPL = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_SPL', 5) +PSP_FW_TYPE_PSP_RL = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_RL', 6) +PSP_FW_TYPE_PSP_SOC_DRV = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_SOC_DRV', 7) +PSP_FW_TYPE_PSP_INTF_DRV = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_INTF_DRV', 8) +PSP_FW_TYPE_PSP_DBG_DRV = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_DBG_DRV', 9) +PSP_FW_TYPE_PSP_RAS_DRV = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_RAS_DRV', 10) +PSP_FW_TYPE_PSP_IPKEYMGR_DRV = enum_psp_fw_type.define('PSP_FW_TYPE_PSP_IPKEYMGR_DRV', 11) +PSP_FW_TYPE_MAX_INDEX = enum_psp_fw_type.define('PSP_FW_TYPE_MAX_INDEX', 12) -# UCODE_MAX_PSP_PACKAGING = (((ctypes.sizeof(amdgpu_firmware_header)-ctypes.sizeof(struct_common_firmware_header)-4)/ctypes.sizeof(struct_psp_fw_bin_desc))*2) # macro - -# values for enumeration 'psp_fw_type' -psp_fw_type__enumvalues = { - 0: 'PSP_FW_TYPE_UNKOWN', - 1: 'PSP_FW_TYPE_PSP_SOS', - 2: 'PSP_FW_TYPE_PSP_SYS_DRV', - 3: 'PSP_FW_TYPE_PSP_KDB', - 4: 'PSP_FW_TYPE_PSP_TOC', - 5: 'PSP_FW_TYPE_PSP_SPL', - 6: 'PSP_FW_TYPE_PSP_RL', - 7: 'PSP_FW_TYPE_PSP_SOC_DRV', - 8: 'PSP_FW_TYPE_PSP_INTF_DRV', - 9: 'PSP_FW_TYPE_PSP_DBG_DRV', - 10: 'PSP_FW_TYPE_PSP_RAS_DRV', - 11: 'PSP_FW_TYPE_PSP_IPKEYMGR_DRV', - 12: 'PSP_FW_TYPE_MAX_INDEX', -} -PSP_FW_TYPE_UNKOWN = 0 -PSP_FW_TYPE_PSP_SOS = 1 -PSP_FW_TYPE_PSP_SYS_DRV = 2 -PSP_FW_TYPE_PSP_KDB = 3 -PSP_FW_TYPE_PSP_TOC = 4 -PSP_FW_TYPE_PSP_SPL = 5 -PSP_FW_TYPE_PSP_RL = 6 -PSP_FW_TYPE_PSP_SOC_DRV = 7 -PSP_FW_TYPE_PSP_INTF_DRV = 8 -PSP_FW_TYPE_PSP_DBG_DRV = 9 -PSP_FW_TYPE_PSP_RAS_DRV = 10 -PSP_FW_TYPE_PSP_IPKEYMGR_DRV = 11 -PSP_FW_TYPE_MAX_INDEX = 12 -psp_fw_type = ctypes.c_uint32 # enum -class struct_psp_firmware_header_v2_0(Structure): - pass - -struct_psp_firmware_header_v2_0._pack_ = 1 # source:False +class struct_psp_firmware_header_v2_0(Struct): pass struct_psp_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('psp_fw_bin_count', ctypes.c_uint32), - ('psp_fw_bin', struct_psp_fw_bin_desc * 1), + ('header', struct_common_firmware_header), + ('psp_fw_bin_count', ctypes.c_uint32), + ('psp_fw_bin', (struct_psp_fw_bin_desc * 1)), ] - -class struct_psp_firmware_header_v2_1(Structure): - pass - -struct_psp_firmware_header_v2_1._pack_ = 1 # source:False +class struct_psp_firmware_header_v2_1(Struct): pass struct_psp_firmware_header_v2_1._fields_ = [ - ('header', struct_common_firmware_header), - ('psp_fw_bin_count', ctypes.c_uint32), - ('psp_aux_fw_bin_index', ctypes.c_uint32), - ('psp_fw_bin', struct_psp_fw_bin_desc * 1), + ('header', struct_common_firmware_header), + ('psp_fw_bin_count', ctypes.c_uint32), + ('psp_aux_fw_bin_index', ctypes.c_uint32), + ('psp_fw_bin', (struct_psp_fw_bin_desc * 1)), ] +class struct_ta_firmware_header_v1_0(Struct): pass +struct_ta_firmware_header_v1_0._fields_ = [ + ('header', struct_common_firmware_header), + ('xgmi', struct_psp_fw_legacy_bin_desc), + ('ras', struct_psp_fw_legacy_bin_desc), + ('hdcp', struct_psp_fw_legacy_bin_desc), + ('dtm', struct_psp_fw_legacy_bin_desc), + ('securedisplay', struct_psp_fw_legacy_bin_desc), +] +enum_ta_fw_type = CEnum(ctypes.c_uint32) +TA_FW_TYPE_UNKOWN = enum_ta_fw_type.define('TA_FW_TYPE_UNKOWN', 0) +TA_FW_TYPE_PSP_ASD = enum_ta_fw_type.define('TA_FW_TYPE_PSP_ASD', 1) +TA_FW_TYPE_PSP_XGMI = enum_ta_fw_type.define('TA_FW_TYPE_PSP_XGMI', 2) +TA_FW_TYPE_PSP_RAS = enum_ta_fw_type.define('TA_FW_TYPE_PSP_RAS', 3) +TA_FW_TYPE_PSP_HDCP = enum_ta_fw_type.define('TA_FW_TYPE_PSP_HDCP', 4) +TA_FW_TYPE_PSP_DTM = enum_ta_fw_type.define('TA_FW_TYPE_PSP_DTM', 5) +TA_FW_TYPE_PSP_RAP = enum_ta_fw_type.define('TA_FW_TYPE_PSP_RAP', 6) +TA_FW_TYPE_PSP_SECUREDISPLAY = enum_ta_fw_type.define('TA_FW_TYPE_PSP_SECUREDISPLAY', 7) +TA_FW_TYPE_MAX_INDEX = enum_ta_fw_type.define('TA_FW_TYPE_MAX_INDEX', 8) -class struct_ta_firmware_header_v1_0(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('header', struct_common_firmware_header), - ('xgmi', struct_psp_fw_legacy_bin_desc), - ('ras', struct_psp_fw_legacy_bin_desc), - ('hdcp', struct_psp_fw_legacy_bin_desc), - ('dtm', struct_psp_fw_legacy_bin_desc), - ('securedisplay', struct_psp_fw_legacy_bin_desc), - ] - - -# values for enumeration 'ta_fw_type' -ta_fw_type__enumvalues = { - 0: 'TA_FW_TYPE_UNKOWN', - 1: 'TA_FW_TYPE_PSP_ASD', - 2: 'TA_FW_TYPE_PSP_XGMI', - 3: 'TA_FW_TYPE_PSP_RAS', - 4: 'TA_FW_TYPE_PSP_HDCP', - 5: 'TA_FW_TYPE_PSP_DTM', - 6: 'TA_FW_TYPE_PSP_RAP', - 7: 'TA_FW_TYPE_PSP_SECUREDISPLAY', - 8: 'TA_FW_TYPE_MAX_INDEX', -} -TA_FW_TYPE_UNKOWN = 0 -TA_FW_TYPE_PSP_ASD = 1 -TA_FW_TYPE_PSP_XGMI = 2 -TA_FW_TYPE_PSP_RAS = 3 -TA_FW_TYPE_PSP_HDCP = 4 -TA_FW_TYPE_PSP_DTM = 5 -TA_FW_TYPE_PSP_RAP = 6 -TA_FW_TYPE_PSP_SECUREDISPLAY = 7 -TA_FW_TYPE_MAX_INDEX = 8 -ta_fw_type = ctypes.c_uint32 # enum -class struct_ta_firmware_header_v2_0(Structure): - pass - -struct_ta_firmware_header_v2_0._pack_ = 1 # source:False +class struct_ta_firmware_header_v2_0(Struct): pass struct_ta_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ta_fw_bin_count', ctypes.c_uint32), - ('ta_fw_bin', struct_psp_fw_bin_desc * 1), + ('header', struct_common_firmware_header), + ('ta_fw_bin_count', ctypes.c_uint32), + ('ta_fw_bin', (struct_psp_fw_bin_desc * 1)), ] - -class struct_gfx_firmware_header_v1_0(Structure): - pass - -struct_gfx_firmware_header_v1_0._pack_ = 1 # source:False +class struct_gfx_firmware_header_v1_0(Struct): pass struct_gfx_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('jt_offset', ctypes.c_uint32), - ('jt_size', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('jt_offset', ctypes.c_uint32), + ('jt_size', ctypes.c_uint32), ] - -class struct_gfx_firmware_header_v2_0(Structure): - pass - -struct_gfx_firmware_header_v2_0._pack_ = 1 # source:False +class struct_gfx_firmware_header_v2_0(Struct): pass struct_gfx_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ucode_size_bytes', ctypes.c_uint32), - ('ucode_offset_bytes', ctypes.c_uint32), - ('data_size_bytes', ctypes.c_uint32), - ('data_offset_bytes', ctypes.c_uint32), - ('ucode_start_addr_lo', ctypes.c_uint32), - ('ucode_start_addr_hi', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ucode_size_bytes', ctypes.c_uint32), + ('ucode_offset_bytes', ctypes.c_uint32), + ('data_size_bytes', ctypes.c_uint32), + ('data_offset_bytes', ctypes.c_uint32), + ('ucode_start_addr_lo', ctypes.c_uint32), + ('ucode_start_addr_hi', ctypes.c_uint32), ] - -class struct_mes_firmware_header_v1_0(Structure): - pass - -struct_mes_firmware_header_v1_0._pack_ = 1 # source:False +class struct_mes_firmware_header_v1_0(Struct): pass struct_mes_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('mes_ucode_version', ctypes.c_uint32), - ('mes_ucode_size_bytes', ctypes.c_uint32), - ('mes_ucode_offset_bytes', ctypes.c_uint32), - ('mes_ucode_data_version', ctypes.c_uint32), - ('mes_ucode_data_size_bytes', ctypes.c_uint32), - ('mes_ucode_data_offset_bytes', ctypes.c_uint32), - ('mes_uc_start_addr_lo', ctypes.c_uint32), - ('mes_uc_start_addr_hi', ctypes.c_uint32), - ('mes_data_start_addr_lo', ctypes.c_uint32), - ('mes_data_start_addr_hi', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('mes_ucode_version', ctypes.c_uint32), + ('mes_ucode_size_bytes', ctypes.c_uint32), + ('mes_ucode_offset_bytes', ctypes.c_uint32), + ('mes_ucode_data_version', ctypes.c_uint32), + ('mes_ucode_data_size_bytes', ctypes.c_uint32), + ('mes_ucode_data_offset_bytes', ctypes.c_uint32), + ('mes_uc_start_addr_lo', ctypes.c_uint32), + ('mes_uc_start_addr_hi', ctypes.c_uint32), + ('mes_data_start_addr_lo', ctypes.c_uint32), + ('mes_data_start_addr_hi', ctypes.c_uint32), ] - -class struct_rlc_firmware_header_v1_0(Structure): - pass - -struct_rlc_firmware_header_v1_0._pack_ = 1 # source:False +class struct_rlc_firmware_header_v1_0(Struct): pass struct_rlc_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('save_and_restore_offset', ctypes.c_uint32), - ('clear_state_descriptor_offset', ctypes.c_uint32), - ('avail_scratch_ram_locations', ctypes.c_uint32), - ('master_pkt_description_offset', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('save_and_restore_offset', ctypes.c_uint32), + ('clear_state_descriptor_offset', ctypes.c_uint32), + ('avail_scratch_ram_locations', ctypes.c_uint32), + ('master_pkt_description_offset', ctypes.c_uint32), ] - -class struct_rlc_firmware_header_v2_0(Structure): - pass - -struct_rlc_firmware_header_v2_0._pack_ = 1 # source:False +class struct_rlc_firmware_header_v2_0(Struct): pass struct_rlc_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('jt_offset', ctypes.c_uint32), - ('jt_size', ctypes.c_uint32), - ('save_and_restore_offset', ctypes.c_uint32), - ('clear_state_descriptor_offset', ctypes.c_uint32), - ('avail_scratch_ram_locations', ctypes.c_uint32), - ('reg_restore_list_size', ctypes.c_uint32), - ('reg_list_format_start', ctypes.c_uint32), - ('reg_list_format_separate_start', ctypes.c_uint32), - ('starting_offsets_start', ctypes.c_uint32), - ('reg_list_format_size_bytes', ctypes.c_uint32), - ('reg_list_format_array_offset_bytes', ctypes.c_uint32), - ('reg_list_size_bytes', ctypes.c_uint32), - ('reg_list_array_offset_bytes', ctypes.c_uint32), - ('reg_list_format_separate_size_bytes', ctypes.c_uint32), - ('reg_list_format_separate_array_offset_bytes', ctypes.c_uint32), - ('reg_list_separate_size_bytes', ctypes.c_uint32), - ('reg_list_separate_array_offset_bytes', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('jt_offset', ctypes.c_uint32), + ('jt_size', ctypes.c_uint32), + ('save_and_restore_offset', ctypes.c_uint32), + ('clear_state_descriptor_offset', ctypes.c_uint32), + ('avail_scratch_ram_locations', ctypes.c_uint32), + ('reg_restore_list_size', ctypes.c_uint32), + ('reg_list_format_start', ctypes.c_uint32), + ('reg_list_format_separate_start', ctypes.c_uint32), + ('starting_offsets_start', ctypes.c_uint32), + ('reg_list_format_size_bytes', ctypes.c_uint32), + ('reg_list_format_array_offset_bytes', ctypes.c_uint32), + ('reg_list_size_bytes', ctypes.c_uint32), + ('reg_list_array_offset_bytes', ctypes.c_uint32), + ('reg_list_format_separate_size_bytes', ctypes.c_uint32), + ('reg_list_format_separate_array_offset_bytes', ctypes.c_uint32), + ('reg_list_separate_size_bytes', ctypes.c_uint32), + ('reg_list_separate_array_offset_bytes', ctypes.c_uint32), ] - -class struct_rlc_firmware_header_v2_1(Structure): - pass - -struct_rlc_firmware_header_v2_1._pack_ = 1 # source:False +class struct_rlc_firmware_header_v2_1(Struct): pass struct_rlc_firmware_header_v2_1._fields_ = [ - ('v2_0', struct_rlc_firmware_header_v2_0), - ('reg_list_format_direct_reg_list_length', ctypes.c_uint32), - ('save_restore_list_cntl_ucode_ver', ctypes.c_uint32), - ('save_restore_list_cntl_feature_ver', ctypes.c_uint32), - ('save_restore_list_cntl_size_bytes', ctypes.c_uint32), - ('save_restore_list_cntl_offset_bytes', ctypes.c_uint32), - ('save_restore_list_gpm_ucode_ver', ctypes.c_uint32), - ('save_restore_list_gpm_feature_ver', ctypes.c_uint32), - ('save_restore_list_gpm_size_bytes', ctypes.c_uint32), - ('save_restore_list_gpm_offset_bytes', ctypes.c_uint32), - ('save_restore_list_srm_ucode_ver', ctypes.c_uint32), - ('save_restore_list_srm_feature_ver', ctypes.c_uint32), - ('save_restore_list_srm_size_bytes', ctypes.c_uint32), - ('save_restore_list_srm_offset_bytes', ctypes.c_uint32), + ('v2_0', struct_rlc_firmware_header_v2_0), + ('reg_list_format_direct_reg_list_length', ctypes.c_uint32), + ('save_restore_list_cntl_ucode_ver', ctypes.c_uint32), + ('save_restore_list_cntl_feature_ver', ctypes.c_uint32), + ('save_restore_list_cntl_size_bytes', ctypes.c_uint32), + ('save_restore_list_cntl_offset_bytes', ctypes.c_uint32), + ('save_restore_list_gpm_ucode_ver', ctypes.c_uint32), + ('save_restore_list_gpm_feature_ver', ctypes.c_uint32), + ('save_restore_list_gpm_size_bytes', ctypes.c_uint32), + ('save_restore_list_gpm_offset_bytes', ctypes.c_uint32), + ('save_restore_list_srm_ucode_ver', ctypes.c_uint32), + ('save_restore_list_srm_feature_ver', ctypes.c_uint32), + ('save_restore_list_srm_size_bytes', ctypes.c_uint32), + ('save_restore_list_srm_offset_bytes', ctypes.c_uint32), ] - -class struct_rlc_firmware_header_v2_2(Structure): - pass - -struct_rlc_firmware_header_v2_2._pack_ = 1 # source:False +class struct_rlc_firmware_header_v2_2(Struct): pass struct_rlc_firmware_header_v2_2._fields_ = [ - ('v2_1', struct_rlc_firmware_header_v2_1), - ('rlc_iram_ucode_size_bytes', ctypes.c_uint32), - ('rlc_iram_ucode_offset_bytes', ctypes.c_uint32), - ('rlc_dram_ucode_size_bytes', ctypes.c_uint32), - ('rlc_dram_ucode_offset_bytes', ctypes.c_uint32), + ('v2_1', struct_rlc_firmware_header_v2_1), + ('rlc_iram_ucode_size_bytes', ctypes.c_uint32), + ('rlc_iram_ucode_offset_bytes', ctypes.c_uint32), + ('rlc_dram_ucode_size_bytes', ctypes.c_uint32), + ('rlc_dram_ucode_offset_bytes', ctypes.c_uint32), ] - -class struct_rlc_firmware_header_v2_3(Structure): - pass - -struct_rlc_firmware_header_v2_3._pack_ = 1 # source:False +class struct_rlc_firmware_header_v2_3(Struct): pass struct_rlc_firmware_header_v2_3._fields_ = [ - ('v2_2', struct_rlc_firmware_header_v2_2), - ('rlcp_ucode_version', ctypes.c_uint32), - ('rlcp_ucode_feature_version', ctypes.c_uint32), - ('rlcp_ucode_size_bytes', ctypes.c_uint32), - ('rlcp_ucode_offset_bytes', ctypes.c_uint32), - ('rlcv_ucode_version', ctypes.c_uint32), - ('rlcv_ucode_feature_version', ctypes.c_uint32), - ('rlcv_ucode_size_bytes', ctypes.c_uint32), - ('rlcv_ucode_offset_bytes', ctypes.c_uint32), + ('v2_2', struct_rlc_firmware_header_v2_2), + ('rlcp_ucode_version', ctypes.c_uint32), + ('rlcp_ucode_feature_version', ctypes.c_uint32), + ('rlcp_ucode_size_bytes', ctypes.c_uint32), + ('rlcp_ucode_offset_bytes', ctypes.c_uint32), + ('rlcv_ucode_version', ctypes.c_uint32), + ('rlcv_ucode_feature_version', ctypes.c_uint32), + ('rlcv_ucode_size_bytes', ctypes.c_uint32), + ('rlcv_ucode_offset_bytes', ctypes.c_uint32), ] - -class struct_rlc_firmware_header_v2_4(Structure): - pass - -struct_rlc_firmware_header_v2_4._pack_ = 1 # source:False +class struct_rlc_firmware_header_v2_4(Struct): pass struct_rlc_firmware_header_v2_4._fields_ = [ - ('v2_3', struct_rlc_firmware_header_v2_3), - ('global_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('global_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se0_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se0_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se1_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se1_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se2_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se2_tap_delays_ucode_offset_bytes', ctypes.c_uint32), - ('se3_tap_delays_ucode_size_bytes', ctypes.c_uint32), - ('se3_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('v2_3', struct_rlc_firmware_header_v2_3), + ('global_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('global_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se0_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se0_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se1_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se1_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se2_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se2_tap_delays_ucode_offset_bytes', ctypes.c_uint32), + ('se3_tap_delays_ucode_size_bytes', ctypes.c_uint32), + ('se3_tap_delays_ucode_offset_bytes', ctypes.c_uint32), ] - -class struct_sdma_firmware_header_v1_0(Structure): - pass - -struct_sdma_firmware_header_v1_0._pack_ = 1 # source:False +class struct_sdma_firmware_header_v1_0(Struct): pass struct_sdma_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ucode_change_version', ctypes.c_uint32), - ('jt_offset', ctypes.c_uint32), - ('jt_size', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ucode_change_version', ctypes.c_uint32), + ('jt_offset', ctypes.c_uint32), + ('jt_size', ctypes.c_uint32), ] - -class struct_sdma_firmware_header_v1_1(Structure): - pass - -struct_sdma_firmware_header_v1_1._pack_ = 1 # source:False +class struct_sdma_firmware_header_v1_1(Struct): pass struct_sdma_firmware_header_v1_1._fields_ = [ - ('v1_0', struct_sdma_firmware_header_v1_0), - ('digest_size', ctypes.c_uint32), + ('v1_0', struct_sdma_firmware_header_v1_0), + ('digest_size', ctypes.c_uint32), ] - -class struct_sdma_firmware_header_v2_0(Structure): - pass - -struct_sdma_firmware_header_v2_0._pack_ = 1 # source:False +class struct_sdma_firmware_header_v2_0(Struct): pass struct_sdma_firmware_header_v2_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ctx_ucode_size_bytes', ctypes.c_uint32), - ('ctx_jt_offset', ctypes.c_uint32), - ('ctx_jt_size', ctypes.c_uint32), - ('ctl_ucode_offset', ctypes.c_uint32), - ('ctl_ucode_size_bytes', ctypes.c_uint32), - ('ctl_jt_offset', ctypes.c_uint32), - ('ctl_jt_size', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ctx_ucode_size_bytes', ctypes.c_uint32), + ('ctx_jt_offset', ctypes.c_uint32), + ('ctx_jt_size', ctypes.c_uint32), + ('ctl_ucode_offset', ctypes.c_uint32), + ('ctl_ucode_size_bytes', ctypes.c_uint32), + ('ctl_jt_offset', ctypes.c_uint32), + ('ctl_jt_size', ctypes.c_uint32), ] - -class struct_vpe_firmware_header_v1_0(Structure): - pass - -struct_vpe_firmware_header_v1_0._pack_ = 1 # source:False +class struct_vpe_firmware_header_v1_0(Struct): pass struct_vpe_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ctx_ucode_size_bytes', ctypes.c_uint32), - ('ctx_jt_offset', ctypes.c_uint32), - ('ctx_jt_size', ctypes.c_uint32), - ('ctl_ucode_offset', ctypes.c_uint32), - ('ctl_ucode_size_bytes', ctypes.c_uint32), - ('ctl_jt_offset', ctypes.c_uint32), - ('ctl_jt_size', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ctx_ucode_size_bytes', ctypes.c_uint32), + ('ctx_jt_offset', ctypes.c_uint32), + ('ctx_jt_size', ctypes.c_uint32), + ('ctl_ucode_offset', ctypes.c_uint32), + ('ctl_ucode_size_bytes', ctypes.c_uint32), + ('ctl_jt_offset', ctypes.c_uint32), + ('ctl_jt_size', ctypes.c_uint32), ] - -class struct_umsch_mm_firmware_header_v1_0(Structure): - pass - -struct_umsch_mm_firmware_header_v1_0._pack_ = 1 # source:False +class struct_umsch_mm_firmware_header_v1_0(Struct): pass struct_umsch_mm_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('umsch_mm_ucode_version', ctypes.c_uint32), - ('umsch_mm_ucode_size_bytes', ctypes.c_uint32), - ('umsch_mm_ucode_offset_bytes', ctypes.c_uint32), - ('umsch_mm_ucode_data_version', ctypes.c_uint32), - ('umsch_mm_ucode_data_size_bytes', ctypes.c_uint32), - ('umsch_mm_ucode_data_offset_bytes', ctypes.c_uint32), - ('umsch_mm_irq_start_addr_lo', ctypes.c_uint32), - ('umsch_mm_irq_start_addr_hi', ctypes.c_uint32), - ('umsch_mm_uc_start_addr_lo', ctypes.c_uint32), - ('umsch_mm_uc_start_addr_hi', ctypes.c_uint32), - ('umsch_mm_data_start_addr_lo', ctypes.c_uint32), - ('umsch_mm_data_start_addr_hi', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('umsch_mm_ucode_version', ctypes.c_uint32), + ('umsch_mm_ucode_size_bytes', ctypes.c_uint32), + ('umsch_mm_ucode_offset_bytes', ctypes.c_uint32), + ('umsch_mm_ucode_data_version', ctypes.c_uint32), + ('umsch_mm_ucode_data_size_bytes', ctypes.c_uint32), + ('umsch_mm_ucode_data_offset_bytes', ctypes.c_uint32), + ('umsch_mm_irq_start_addr_lo', ctypes.c_uint32), + ('umsch_mm_irq_start_addr_hi', ctypes.c_uint32), + ('umsch_mm_uc_start_addr_lo', ctypes.c_uint32), + ('umsch_mm_uc_start_addr_hi', ctypes.c_uint32), + ('umsch_mm_data_start_addr_lo', ctypes.c_uint32), + ('umsch_mm_data_start_addr_hi', ctypes.c_uint32), ] - -class struct_sdma_firmware_header_v3_0(Structure): - pass - -struct_sdma_firmware_header_v3_0._pack_ = 1 # source:False +class struct_sdma_firmware_header_v3_0(Struct): pass struct_sdma_firmware_header_v3_0._fields_ = [ - ('header', struct_common_firmware_header), - ('ucode_feature_version', ctypes.c_uint32), - ('ucode_offset_bytes', ctypes.c_uint32), - ('ucode_size_bytes', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('ucode_feature_version', ctypes.c_uint32), + ('ucode_offset_bytes', ctypes.c_uint32), + ('ucode_size_bytes', ctypes.c_uint32), ] - -class struct_gpu_info_firmware_v1_0(Structure): - pass - -struct_gpu_info_firmware_v1_0._pack_ = 1 # source:False +class struct_gpu_info_firmware_v1_0(Struct): pass struct_gpu_info_firmware_v1_0._fields_ = [ - ('gc_num_se', ctypes.c_uint32), - ('gc_num_cu_per_sh', ctypes.c_uint32), - ('gc_num_sh_per_se', ctypes.c_uint32), - ('gc_num_rb_per_se', ctypes.c_uint32), - ('gc_num_tccs', ctypes.c_uint32), - ('gc_num_gprs', ctypes.c_uint32), - ('gc_num_max_gs_thds', ctypes.c_uint32), - ('gc_gs_table_depth', ctypes.c_uint32), - ('gc_gsprim_buff_depth', ctypes.c_uint32), - ('gc_parameter_cache_depth', ctypes.c_uint32), - ('gc_double_offchip_lds_buffer', ctypes.c_uint32), - ('gc_wave_size', ctypes.c_uint32), - ('gc_max_waves_per_simd', ctypes.c_uint32), - ('gc_max_scratch_slots_per_cu', ctypes.c_uint32), - ('gc_lds_size', ctypes.c_uint32), + ('gc_num_se', ctypes.c_uint32), + ('gc_num_cu_per_sh', ctypes.c_uint32), + ('gc_num_sh_per_se', ctypes.c_uint32), + ('gc_num_rb_per_se', ctypes.c_uint32), + ('gc_num_tccs', ctypes.c_uint32), + ('gc_num_gprs', ctypes.c_uint32), + ('gc_num_max_gs_thds', ctypes.c_uint32), + ('gc_gs_table_depth', ctypes.c_uint32), + ('gc_gsprim_buff_depth', ctypes.c_uint32), + ('gc_parameter_cache_depth', ctypes.c_uint32), + ('gc_double_offchip_lds_buffer', ctypes.c_uint32), + ('gc_wave_size', ctypes.c_uint32), + ('gc_max_waves_per_simd', ctypes.c_uint32), + ('gc_max_scratch_slots_per_cu', ctypes.c_uint32), + ('gc_lds_size', ctypes.c_uint32), ] - -class struct_gpu_info_firmware_v1_1(Structure): - pass - -struct_gpu_info_firmware_v1_1._pack_ = 1 # source:False +class struct_gpu_info_firmware_v1_1(Struct): pass struct_gpu_info_firmware_v1_1._fields_ = [ - ('v1_0', struct_gpu_info_firmware_v1_0), - ('num_sc_per_sh', ctypes.c_uint32), - ('num_packer_per_sc', ctypes.c_uint32), + ('v1_0', struct_gpu_info_firmware_v1_0), + ('num_sc_per_sh', ctypes.c_uint32), + ('num_packer_per_sc', ctypes.c_uint32), ] - -class struct_gpu_info_firmware_header_v1_0(Structure): - pass - -struct_gpu_info_firmware_header_v1_0._pack_ = 1 # source:False +class struct_gpu_info_firmware_header_v1_0(Struct): pass struct_gpu_info_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('version_major', ctypes.c_uint16), - ('version_minor', ctypes.c_uint16), + ('header', struct_common_firmware_header), + ('version_major', ctypes.c_uint16), + ('version_minor', ctypes.c_uint16), ] - -class struct_dmcu_firmware_header_v1_0(Structure): - pass - -struct_dmcu_firmware_header_v1_0._pack_ = 1 # source:False +class struct_dmcu_firmware_header_v1_0(Struct): pass struct_dmcu_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('intv_offset_bytes', ctypes.c_uint32), - ('intv_size_bytes', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('intv_offset_bytes', ctypes.c_uint32), + ('intv_size_bytes', ctypes.c_uint32), ] - -class struct_dmcub_firmware_header_v1_0(Structure): - pass - -struct_dmcub_firmware_header_v1_0._pack_ = 1 # source:False +class struct_dmcub_firmware_header_v1_0(Struct): pass struct_dmcub_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('inst_const_bytes', ctypes.c_uint32), - ('bss_data_bytes', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('inst_const_bytes', ctypes.c_uint32), + ('bss_data_bytes', ctypes.c_uint32), ] - -class struct_imu_firmware_header_v1_0(Structure): - pass - -struct_imu_firmware_header_v1_0._pack_ = 1 # source:False +class struct_imu_firmware_header_v1_0(Struct): pass struct_imu_firmware_header_v1_0._fields_ = [ - ('header', struct_common_firmware_header), - ('imu_iram_ucode_size_bytes', ctypes.c_uint32), - ('imu_iram_ucode_offset_bytes', ctypes.c_uint32), - ('imu_dram_ucode_size_bytes', ctypes.c_uint32), - ('imu_dram_ucode_offset_bytes', ctypes.c_uint32), + ('header', struct_common_firmware_header), + ('imu_iram_ucode_size_bytes', ctypes.c_uint32), + ('imu_iram_ucode_offset_bytes', ctypes.c_uint32), + ('imu_dram_ucode_size_bytes', ctypes.c_uint32), + ('imu_dram_ucode_offset_bytes', ctypes.c_uint32), ] - -class union_amdgpu_firmware_header(Union): - pass - -union_amdgpu_firmware_header._pack_ = 1 # source:False +class union_amdgpu_firmware_header(ctypes.Union): pass union_amdgpu_firmware_header._fields_ = [ - ('common', struct_common_firmware_header), - ('mc', struct_mc_firmware_header_v1_0), - ('smc', struct_smc_firmware_header_v1_0), - ('smc_v2_0', struct_smc_firmware_header_v2_0), - ('psp', struct_psp_firmware_header_v1_0), - ('psp_v1_1', struct_psp_firmware_header_v1_1), - ('psp_v1_3', struct_psp_firmware_header_v1_3), - ('psp_v2_0', struct_psp_firmware_header_v2_0), - ('psp_v2_1', struct_psp_firmware_header_v2_0), - ('ta', struct_ta_firmware_header_v1_0), - ('ta_v2_0', struct_ta_firmware_header_v2_0), - ('gfx', struct_gfx_firmware_header_v1_0), - ('gfx_v2_0', struct_gfx_firmware_header_v2_0), - ('rlc', struct_rlc_firmware_header_v1_0), - ('rlc_v2_0', struct_rlc_firmware_header_v2_0), - ('rlc_v2_1', struct_rlc_firmware_header_v2_1), - ('rlc_v2_2', struct_rlc_firmware_header_v2_2), - ('rlc_v2_3', struct_rlc_firmware_header_v2_3), - ('rlc_v2_4', struct_rlc_firmware_header_v2_4), - ('sdma', struct_sdma_firmware_header_v1_0), - ('sdma_v1_1', struct_sdma_firmware_header_v1_1), - ('sdma_v2_0', struct_sdma_firmware_header_v2_0), - ('sdma_v3_0', struct_sdma_firmware_header_v3_0), - ('gpu_info', struct_gpu_info_firmware_header_v1_0), - ('dmcu', struct_dmcu_firmware_header_v1_0), - ('dmcub', struct_dmcub_firmware_header_v1_0), - ('imu', struct_imu_firmware_header_v1_0), - ('raw', ctypes.c_ubyte * 256), + ('common', struct_common_firmware_header), + ('mc', struct_mc_firmware_header_v1_0), + ('smc', struct_smc_firmware_header_v1_0), + ('smc_v2_0', struct_smc_firmware_header_v2_0), + ('psp', struct_psp_firmware_header_v1_0), + ('psp_v1_1', struct_psp_firmware_header_v1_1), + ('psp_v1_3', struct_psp_firmware_header_v1_3), + ('psp_v2_0', struct_psp_firmware_header_v2_0), + ('psp_v2_1', struct_psp_firmware_header_v2_0), + ('ta', struct_ta_firmware_header_v1_0), + ('ta_v2_0', struct_ta_firmware_header_v2_0), + ('gfx', struct_gfx_firmware_header_v1_0), + ('gfx_v2_0', struct_gfx_firmware_header_v2_0), + ('rlc', struct_rlc_firmware_header_v1_0), + ('rlc_v2_0', struct_rlc_firmware_header_v2_0), + ('rlc_v2_1', struct_rlc_firmware_header_v2_1), + ('rlc_v2_2', struct_rlc_firmware_header_v2_2), + ('rlc_v2_3', struct_rlc_firmware_header_v2_3), + ('rlc_v2_4', struct_rlc_firmware_header_v2_4), + ('sdma', struct_sdma_firmware_header_v1_0), + ('sdma_v1_1', struct_sdma_firmware_header_v1_1), + ('sdma_v2_0', struct_sdma_firmware_header_v2_0), + ('sdma_v3_0', struct_sdma_firmware_header_v3_0), + ('gpu_info', struct_gpu_info_firmware_header_v1_0), + ('dmcu', struct_dmcu_firmware_header_v1_0), + ('dmcub', struct_dmcub_firmware_header_v1_0), + ('imu', struct_imu_firmware_header_v1_0), + ('raw', (ctypes.c_ubyte * 256)), ] +enum_AMDGPU_UCODE_ID = CEnum(ctypes.c_uint32) +AMDGPU_UCODE_ID_CAP = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CAP', 0) +AMDGPU_UCODE_ID_SDMA0 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA0', 1) +AMDGPU_UCODE_ID_SDMA1 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA1', 2) +AMDGPU_UCODE_ID_SDMA2 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA2', 3) +AMDGPU_UCODE_ID_SDMA3 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA3', 4) +AMDGPU_UCODE_ID_SDMA4 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA4', 5) +AMDGPU_UCODE_ID_SDMA5 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA5', 6) +AMDGPU_UCODE_ID_SDMA6 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA6', 7) +AMDGPU_UCODE_ID_SDMA7 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA7', 8) +AMDGPU_UCODE_ID_SDMA_UCODE_TH0 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA_UCODE_TH0', 9) +AMDGPU_UCODE_ID_SDMA_UCODE_TH1 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA_UCODE_TH1', 10) +AMDGPU_UCODE_ID_SDMA_RS64 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SDMA_RS64', 11) +AMDGPU_UCODE_ID_CP_CE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_CE', 12) +AMDGPU_UCODE_ID_CP_PFP = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_PFP', 13) +AMDGPU_UCODE_ID_CP_ME = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_ME', 14) +AMDGPU_UCODE_ID_CP_RS64_PFP = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_PFP', 15) +AMDGPU_UCODE_ID_CP_RS64_ME = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_ME', 16) +AMDGPU_UCODE_ID_CP_RS64_MEC = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_MEC', 17) +AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', 18) +AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', 19) +AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', 20) +AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', 21) +AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', 22) +AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', 23) +AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', 24) +AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', 25) +AMDGPU_UCODE_ID_CP_MEC1 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MEC1', 26) +AMDGPU_UCODE_ID_CP_MEC1_JT = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MEC1_JT', 27) +AMDGPU_UCODE_ID_CP_MEC2 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MEC2', 28) +AMDGPU_UCODE_ID_CP_MEC2_JT = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MEC2_JT', 29) +AMDGPU_UCODE_ID_CP_MES = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MES', 30) +AMDGPU_UCODE_ID_CP_MES_DATA = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MES_DATA', 31) +AMDGPU_UCODE_ID_CP_MES1 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MES1', 32) +AMDGPU_UCODE_ID_CP_MES1_DATA = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_CP_MES1_DATA', 33) +AMDGPU_UCODE_ID_IMU_I = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_IMU_I', 34) +AMDGPU_UCODE_ID_IMU_D = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_IMU_D', 35) +AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', 36) +AMDGPU_UCODE_ID_SE0_TAP_DELAYS = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SE0_TAP_DELAYS', 37) +AMDGPU_UCODE_ID_SE1_TAP_DELAYS = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SE1_TAP_DELAYS', 38) +AMDGPU_UCODE_ID_SE2_TAP_DELAYS = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SE2_TAP_DELAYS', 39) +AMDGPU_UCODE_ID_SE3_TAP_DELAYS = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SE3_TAP_DELAYS', 40) +AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', 41) +AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', 42) +AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', 43) +AMDGPU_UCODE_ID_RLC_IRAM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_IRAM', 44) +AMDGPU_UCODE_ID_RLC_DRAM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_DRAM', 45) +AMDGPU_UCODE_ID_RLC_P = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_P', 46) +AMDGPU_UCODE_ID_RLC_V = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_V', 47) +AMDGPU_UCODE_ID_RLC_G = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_RLC_G', 48) +AMDGPU_UCODE_ID_STORAGE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_STORAGE', 49) +AMDGPU_UCODE_ID_SMC = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_SMC', 50) +AMDGPU_UCODE_ID_PPTABLE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_PPTABLE', 51) +AMDGPU_UCODE_ID_UVD = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_UVD', 52) +AMDGPU_UCODE_ID_UVD1 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_UVD1', 53) +AMDGPU_UCODE_ID_VCE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VCE', 54) +AMDGPU_UCODE_ID_VCN = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VCN', 55) +AMDGPU_UCODE_ID_VCN1 = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VCN1', 56) +AMDGPU_UCODE_ID_DMCU_ERAM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_DMCU_ERAM', 57) +AMDGPU_UCODE_ID_DMCU_INTV = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_DMCU_INTV', 58) +AMDGPU_UCODE_ID_VCN0_RAM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VCN0_RAM', 59) +AMDGPU_UCODE_ID_VCN1_RAM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VCN1_RAM', 60) +AMDGPU_UCODE_ID_DMCUB = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_DMCUB', 61) +AMDGPU_UCODE_ID_VPE_CTX = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VPE_CTX', 62) +AMDGPU_UCODE_ID_VPE_CTL = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VPE_CTL', 63) +AMDGPU_UCODE_ID_VPE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_VPE', 64) +AMDGPU_UCODE_ID_UMSCH_MM_UCODE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_UMSCH_MM_UCODE', 65) +AMDGPU_UCODE_ID_UMSCH_MM_DATA = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_UMSCH_MM_DATA', 66) +AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', 67) +AMDGPU_UCODE_ID_P2S_TABLE = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_P2S_TABLE', 68) +AMDGPU_UCODE_ID_JPEG_RAM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_JPEG_RAM', 69) +AMDGPU_UCODE_ID_ISP = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_ISP', 70) +AMDGPU_UCODE_ID_MAXIMUM = enum_AMDGPU_UCODE_ID.define('AMDGPU_UCODE_ID_MAXIMUM', 71) +enum_AMDGPU_UCODE_STATUS = CEnum(ctypes.c_uint32) +AMDGPU_UCODE_STATUS_INVALID = enum_AMDGPU_UCODE_STATUS.define('AMDGPU_UCODE_STATUS_INVALID', 0) +AMDGPU_UCODE_STATUS_NOT_LOADED = enum_AMDGPU_UCODE_STATUS.define('AMDGPU_UCODE_STATUS_NOT_LOADED', 1) +AMDGPU_UCODE_STATUS_LOADED = enum_AMDGPU_UCODE_STATUS.define('AMDGPU_UCODE_STATUS_LOADED', 2) -# values for enumeration 'AMDGPU_UCODE_ID' -AMDGPU_UCODE_ID__enumvalues = { - 0: 'AMDGPU_UCODE_ID_CAP', - 1: 'AMDGPU_UCODE_ID_SDMA0', - 2: 'AMDGPU_UCODE_ID_SDMA1', - 3: 'AMDGPU_UCODE_ID_SDMA2', - 4: 'AMDGPU_UCODE_ID_SDMA3', - 5: 'AMDGPU_UCODE_ID_SDMA4', - 6: 'AMDGPU_UCODE_ID_SDMA5', - 7: 'AMDGPU_UCODE_ID_SDMA6', - 8: 'AMDGPU_UCODE_ID_SDMA7', - 9: 'AMDGPU_UCODE_ID_SDMA_UCODE_TH0', - 10: 'AMDGPU_UCODE_ID_SDMA_UCODE_TH1', - 11: 'AMDGPU_UCODE_ID_SDMA_RS64', - 12: 'AMDGPU_UCODE_ID_CP_CE', - 13: 'AMDGPU_UCODE_ID_CP_PFP', - 14: 'AMDGPU_UCODE_ID_CP_ME', - 15: 'AMDGPU_UCODE_ID_CP_RS64_PFP', - 16: 'AMDGPU_UCODE_ID_CP_RS64_ME', - 17: 'AMDGPU_UCODE_ID_CP_RS64_MEC', - 18: 'AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', - 19: 'AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', - 20: 'AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', - 21: 'AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', - 22: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', - 23: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', - 24: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', - 25: 'AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', - 26: 'AMDGPU_UCODE_ID_CP_MEC1', - 27: 'AMDGPU_UCODE_ID_CP_MEC1_JT', - 28: 'AMDGPU_UCODE_ID_CP_MEC2', - 29: 'AMDGPU_UCODE_ID_CP_MEC2_JT', - 30: 'AMDGPU_UCODE_ID_CP_MES', - 31: 'AMDGPU_UCODE_ID_CP_MES_DATA', - 32: 'AMDGPU_UCODE_ID_CP_MES1', - 33: 'AMDGPU_UCODE_ID_CP_MES1_DATA', - 34: 'AMDGPU_UCODE_ID_IMU_I', - 35: 'AMDGPU_UCODE_ID_IMU_D', - 36: 'AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', - 37: 'AMDGPU_UCODE_ID_SE0_TAP_DELAYS', - 38: 'AMDGPU_UCODE_ID_SE1_TAP_DELAYS', - 39: 'AMDGPU_UCODE_ID_SE2_TAP_DELAYS', - 40: 'AMDGPU_UCODE_ID_SE3_TAP_DELAYS', - 41: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', - 42: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', - 43: 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', - 44: 'AMDGPU_UCODE_ID_RLC_IRAM', - 45: 'AMDGPU_UCODE_ID_RLC_DRAM', - 46: 'AMDGPU_UCODE_ID_RLC_P', - 47: 'AMDGPU_UCODE_ID_RLC_V', - 48: 'AMDGPU_UCODE_ID_RLC_G', - 49: 'AMDGPU_UCODE_ID_STORAGE', - 50: 'AMDGPU_UCODE_ID_SMC', - 51: 'AMDGPU_UCODE_ID_PPTABLE', - 52: 'AMDGPU_UCODE_ID_UVD', - 53: 'AMDGPU_UCODE_ID_UVD1', - 54: 'AMDGPU_UCODE_ID_VCE', - 55: 'AMDGPU_UCODE_ID_VCN', - 56: 'AMDGPU_UCODE_ID_VCN1', - 57: 'AMDGPU_UCODE_ID_DMCU_ERAM', - 58: 'AMDGPU_UCODE_ID_DMCU_INTV', - 59: 'AMDGPU_UCODE_ID_VCN0_RAM', - 60: 'AMDGPU_UCODE_ID_VCN1_RAM', - 61: 'AMDGPU_UCODE_ID_DMCUB', - 62: 'AMDGPU_UCODE_ID_VPE_CTX', - 63: 'AMDGPU_UCODE_ID_VPE_CTL', - 64: 'AMDGPU_UCODE_ID_VPE', - 65: 'AMDGPU_UCODE_ID_UMSCH_MM_UCODE', - 66: 'AMDGPU_UCODE_ID_UMSCH_MM_DATA', - 67: 'AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', - 68: 'AMDGPU_UCODE_ID_P2S_TABLE', - 69: 'AMDGPU_UCODE_ID_JPEG_RAM', - 70: 'AMDGPU_UCODE_ID_ISP', - 71: 'AMDGPU_UCODE_ID_MAXIMUM', -} -AMDGPU_UCODE_ID_CAP = 0 -AMDGPU_UCODE_ID_SDMA0 = 1 -AMDGPU_UCODE_ID_SDMA1 = 2 -AMDGPU_UCODE_ID_SDMA2 = 3 -AMDGPU_UCODE_ID_SDMA3 = 4 -AMDGPU_UCODE_ID_SDMA4 = 5 -AMDGPU_UCODE_ID_SDMA5 = 6 -AMDGPU_UCODE_ID_SDMA6 = 7 -AMDGPU_UCODE_ID_SDMA7 = 8 -AMDGPU_UCODE_ID_SDMA_UCODE_TH0 = 9 -AMDGPU_UCODE_ID_SDMA_UCODE_TH1 = 10 -AMDGPU_UCODE_ID_SDMA_RS64 = 11 -AMDGPU_UCODE_ID_CP_CE = 12 -AMDGPU_UCODE_ID_CP_PFP = 13 -AMDGPU_UCODE_ID_CP_ME = 14 -AMDGPU_UCODE_ID_CP_RS64_PFP = 15 -AMDGPU_UCODE_ID_CP_RS64_ME = 16 -AMDGPU_UCODE_ID_CP_RS64_MEC = 17 -AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK = 18 -AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK = 19 -AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK = 20 -AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK = 21 -AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK = 22 -AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK = 23 -AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK = 24 -AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK = 25 -AMDGPU_UCODE_ID_CP_MEC1 = 26 -AMDGPU_UCODE_ID_CP_MEC1_JT = 27 -AMDGPU_UCODE_ID_CP_MEC2 = 28 -AMDGPU_UCODE_ID_CP_MEC2_JT = 29 -AMDGPU_UCODE_ID_CP_MES = 30 -AMDGPU_UCODE_ID_CP_MES_DATA = 31 -AMDGPU_UCODE_ID_CP_MES1 = 32 -AMDGPU_UCODE_ID_CP_MES1_DATA = 33 -AMDGPU_UCODE_ID_IMU_I = 34 -AMDGPU_UCODE_ID_IMU_D = 35 -AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS = 36 -AMDGPU_UCODE_ID_SE0_TAP_DELAYS = 37 -AMDGPU_UCODE_ID_SE1_TAP_DELAYS = 38 -AMDGPU_UCODE_ID_SE2_TAP_DELAYS = 39 -AMDGPU_UCODE_ID_SE3_TAP_DELAYS = 40 -AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL = 41 -AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM = 42 -AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM = 43 -AMDGPU_UCODE_ID_RLC_IRAM = 44 -AMDGPU_UCODE_ID_RLC_DRAM = 45 -AMDGPU_UCODE_ID_RLC_P = 46 -AMDGPU_UCODE_ID_RLC_V = 47 -AMDGPU_UCODE_ID_RLC_G = 48 -AMDGPU_UCODE_ID_STORAGE = 49 -AMDGPU_UCODE_ID_SMC = 50 -AMDGPU_UCODE_ID_PPTABLE = 51 -AMDGPU_UCODE_ID_UVD = 52 -AMDGPU_UCODE_ID_UVD1 = 53 -AMDGPU_UCODE_ID_VCE = 54 -AMDGPU_UCODE_ID_VCN = 55 -AMDGPU_UCODE_ID_VCN1 = 56 -AMDGPU_UCODE_ID_DMCU_ERAM = 57 -AMDGPU_UCODE_ID_DMCU_INTV = 58 -AMDGPU_UCODE_ID_VCN0_RAM = 59 -AMDGPU_UCODE_ID_VCN1_RAM = 60 -AMDGPU_UCODE_ID_DMCUB = 61 -AMDGPU_UCODE_ID_VPE_CTX = 62 -AMDGPU_UCODE_ID_VPE_CTL = 63 -AMDGPU_UCODE_ID_VPE = 64 -AMDGPU_UCODE_ID_UMSCH_MM_UCODE = 65 -AMDGPU_UCODE_ID_UMSCH_MM_DATA = 66 -AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER = 67 -AMDGPU_UCODE_ID_P2S_TABLE = 68 -AMDGPU_UCODE_ID_JPEG_RAM = 69 -AMDGPU_UCODE_ID_ISP = 70 -AMDGPU_UCODE_ID_MAXIMUM = 71 -AMDGPU_UCODE_ID = ctypes.c_uint32 # enum +enum_amdgpu_firmware_load_type = CEnum(ctypes.c_uint32) +AMDGPU_FW_LOAD_DIRECT = enum_amdgpu_firmware_load_type.define('AMDGPU_FW_LOAD_DIRECT', 0) +AMDGPU_FW_LOAD_PSP = enum_amdgpu_firmware_load_type.define('AMDGPU_FW_LOAD_PSP', 1) +AMDGPU_FW_LOAD_SMU = enum_amdgpu_firmware_load_type.define('AMDGPU_FW_LOAD_SMU', 2) +AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO = enum_amdgpu_firmware_load_type.define('AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', 3) -# values for enumeration 'AMDGPU_UCODE_STATUS' -AMDGPU_UCODE_STATUS__enumvalues = { - 0: 'AMDGPU_UCODE_STATUS_INVALID', - 1: 'AMDGPU_UCODE_STATUS_NOT_LOADED', - 2: 'AMDGPU_UCODE_STATUS_LOADED', -} -AMDGPU_UCODE_STATUS_INVALID = 0 -AMDGPU_UCODE_STATUS_NOT_LOADED = 1 -AMDGPU_UCODE_STATUS_LOADED = 2 -AMDGPU_UCODE_STATUS = ctypes.c_uint32 # enum - -# values for enumeration 'amdgpu_firmware_load_type' -amdgpu_firmware_load_type__enumvalues = { - 0: 'AMDGPU_FW_LOAD_DIRECT', - 1: 'AMDGPU_FW_LOAD_PSP', - 2: 'AMDGPU_FW_LOAD_SMU', - 3: 'AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', -} -AMDGPU_FW_LOAD_DIRECT = 0 -AMDGPU_FW_LOAD_PSP = 1 -AMDGPU_FW_LOAD_SMU = 2 -AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO = 3 -amdgpu_firmware_load_type = ctypes.c_uint32 # enum -class struct_amdgpu_firmware_info(Structure): - pass - -class struct_firmware(Structure): - pass - -struct_amdgpu_firmware_info._pack_ = 1 # source:False +class struct_amdgpu_firmware_info(Struct): pass +class struct_firmware(Struct): pass struct_amdgpu_firmware_info._fields_ = [ - ('ucode_id', AMDGPU_UCODE_ID), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fw', ctypes.POINTER(struct_firmware)), - ('mc_addr', ctypes.c_uint64), - ('kaddr', ctypes.POINTER(None)), - ('ucode_size', ctypes.c_uint32), - ('tmr_mc_addr_lo', ctypes.c_uint32), - ('tmr_mc_addr_hi', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('ucode_id', enum_AMDGPU_UCODE_ID), + ('fw', ctypes.POINTER(struct_firmware)), + ('mc_addr', ctypes.c_uint64), + ('kaddr', ctypes.c_void_p), + ('ucode_size', ctypes.c_uint32), + ('tmr_mc_addr_lo', ctypes.c_uint32), + ('tmr_mc_addr_hi', ctypes.c_uint32), ] +enum_psp_gfx_crtl_cmd_id = CEnum(ctypes.c_uint32) +GFX_CTRL_CMD_ID_INIT_RBI_RING = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_INIT_RBI_RING', 65536) +GFX_CTRL_CMD_ID_INIT_GPCOM_RING = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_INIT_GPCOM_RING', 131072) +GFX_CTRL_CMD_ID_DESTROY_RINGS = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_DESTROY_RINGS', 196608) +GFX_CTRL_CMD_ID_CAN_INIT_RINGS = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_CAN_INIT_RINGS', 262144) +GFX_CTRL_CMD_ID_ENABLE_INT = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_ENABLE_INT', 327680) +GFX_CTRL_CMD_ID_DISABLE_INT = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_DISABLE_INT', 393216) +GFX_CTRL_CMD_ID_MODE1_RST = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_MODE1_RST', 458752) +GFX_CTRL_CMD_ID_GBR_IH_SET = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_GBR_IH_SET', 524288) +GFX_CTRL_CMD_ID_CONSUME_CMD = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_CONSUME_CMD', 589824) +GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', 786432) +GFX_CTRL_CMD_ID_MAX = enum_psp_gfx_crtl_cmd_id.define('GFX_CTRL_CMD_ID_MAX', 983040) -_PSP_TEE_GFX_IF_H_ = True # macro -PSP_GFX_CMD_BUF_VERSION = 0x00000001 # macro -GFX_CMD_STATUS_MASK = 0x0000FFFF # macro -GFX_CMD_ID_MASK = 0x000F0000 # macro -GFX_CMD_RESERVED_MASK = 0x7FF00000 # macro -GFX_CMD_RESPONSE_MASK = 0x80000000 # macro -C2PMSG_CMD_GFX_USB_PD_FW_VER = 0x2000000 # macro -GFX_FLAG_RESPONSE = 0x80000000 # macro -GFX_BUF_MAX_DESC = 64 # macro -FRAME_TYPE_DESTROY = 1 # macro -PSP_ERR_UNKNOWN_COMMAND = 0x00000100 # macro - -# values for enumeration 'psp_gfx_crtl_cmd_id' -psp_gfx_crtl_cmd_id__enumvalues = { - 65536: 'GFX_CTRL_CMD_ID_INIT_RBI_RING', - 131072: 'GFX_CTRL_CMD_ID_INIT_GPCOM_RING', - 196608: 'GFX_CTRL_CMD_ID_DESTROY_RINGS', - 262144: 'GFX_CTRL_CMD_ID_CAN_INIT_RINGS', - 327680: 'GFX_CTRL_CMD_ID_ENABLE_INT', - 393216: 'GFX_CTRL_CMD_ID_DISABLE_INT', - 458752: 'GFX_CTRL_CMD_ID_MODE1_RST', - 524288: 'GFX_CTRL_CMD_ID_GBR_IH_SET', - 589824: 'GFX_CTRL_CMD_ID_CONSUME_CMD', - 786432: 'GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', - 983040: 'GFX_CTRL_CMD_ID_MAX', -} -GFX_CTRL_CMD_ID_INIT_RBI_RING = 65536 -GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 131072 -GFX_CTRL_CMD_ID_DESTROY_RINGS = 196608 -GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 262144 -GFX_CTRL_CMD_ID_ENABLE_INT = 327680 -GFX_CTRL_CMD_ID_DISABLE_INT = 393216 -GFX_CTRL_CMD_ID_MODE1_RST = 458752 -GFX_CTRL_CMD_ID_GBR_IH_SET = 524288 -GFX_CTRL_CMD_ID_CONSUME_CMD = 589824 -GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 786432 -GFX_CTRL_CMD_ID_MAX = 983040 -psp_gfx_crtl_cmd_id = ctypes.c_uint32 # enum -class struct_psp_gfx_ctrl(Structure): - pass - -struct_psp_gfx_ctrl._pack_ = 1 # source:False +class struct_psp_gfx_ctrl(Struct): pass struct_psp_gfx_ctrl._fields_ = [ - ('cmd_resp', ctypes.c_uint32), - ('rbi_wptr', ctypes.c_uint32), - ('rbi_rptr', ctypes.c_uint32), - ('gpcom_wptr', ctypes.c_uint32), - ('gpcom_rptr', ctypes.c_uint32), - ('ring_addr_lo', ctypes.c_uint32), - ('ring_addr_hi', ctypes.c_uint32), - ('ring_buf_size', ctypes.c_uint32), + ('cmd_resp', ctypes.c_uint32), + ('rbi_wptr', ctypes.c_uint32), + ('rbi_rptr', ctypes.c_uint32), + ('gpcom_wptr', ctypes.c_uint32), + ('gpcom_rptr', ctypes.c_uint32), + ('ring_addr_lo', ctypes.c_uint32), + ('ring_addr_hi', ctypes.c_uint32), + ('ring_buf_size', ctypes.c_uint32), ] +enum_psp_gfx_cmd_id = CEnum(ctypes.c_uint32) +GFX_CMD_ID_LOAD_TA = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_LOAD_TA', 1) +GFX_CMD_ID_UNLOAD_TA = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_UNLOAD_TA', 2) +GFX_CMD_ID_INVOKE_CMD = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_INVOKE_CMD', 3) +GFX_CMD_ID_LOAD_ASD = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_LOAD_ASD', 4) +GFX_CMD_ID_SETUP_TMR = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_SETUP_TMR', 5) +GFX_CMD_ID_LOAD_IP_FW = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_LOAD_IP_FW', 6) +GFX_CMD_ID_DESTROY_TMR = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_DESTROY_TMR', 7) +GFX_CMD_ID_SAVE_RESTORE = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_SAVE_RESTORE', 8) +GFX_CMD_ID_SETUP_VMR = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_SETUP_VMR', 9) +GFX_CMD_ID_DESTROY_VMR = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_DESTROY_VMR', 10) +GFX_CMD_ID_PROG_REG = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_PROG_REG', 11) +GFX_CMD_ID_GET_FW_ATTESTATION = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_GET_FW_ATTESTATION', 15) +GFX_CMD_ID_LOAD_TOC = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_LOAD_TOC', 32) +GFX_CMD_ID_AUTOLOAD_RLC = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_AUTOLOAD_RLC', 33) +GFX_CMD_ID_BOOT_CFG = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_BOOT_CFG', 34) +GFX_CMD_ID_SRIOV_SPATIAL_PART = enum_psp_gfx_cmd_id.define('GFX_CMD_ID_SRIOV_SPATIAL_PART', 39) +enum_psp_gfx_boot_config_cmd = CEnum(ctypes.c_uint32) +BOOTCFG_CMD_SET = enum_psp_gfx_boot_config_cmd.define('BOOTCFG_CMD_SET', 1) +BOOTCFG_CMD_GET = enum_psp_gfx_boot_config_cmd.define('BOOTCFG_CMD_GET', 2) +BOOTCFG_CMD_INVALIDATE = enum_psp_gfx_boot_config_cmd.define('BOOTCFG_CMD_INVALIDATE', 3) -# values for enumeration 'psp_gfx_cmd_id' -psp_gfx_cmd_id__enumvalues = { - 1: 'GFX_CMD_ID_LOAD_TA', - 2: 'GFX_CMD_ID_UNLOAD_TA', - 3: 'GFX_CMD_ID_INVOKE_CMD', - 4: 'GFX_CMD_ID_LOAD_ASD', - 5: 'GFX_CMD_ID_SETUP_TMR', - 6: 'GFX_CMD_ID_LOAD_IP_FW', - 7: 'GFX_CMD_ID_DESTROY_TMR', - 8: 'GFX_CMD_ID_SAVE_RESTORE', - 9: 'GFX_CMD_ID_SETUP_VMR', - 10: 'GFX_CMD_ID_DESTROY_VMR', - 11: 'GFX_CMD_ID_PROG_REG', - 15: 'GFX_CMD_ID_GET_FW_ATTESTATION', - 32: 'GFX_CMD_ID_LOAD_TOC', - 33: 'GFX_CMD_ID_AUTOLOAD_RLC', - 34: 'GFX_CMD_ID_BOOT_CFG', - 39: 'GFX_CMD_ID_SRIOV_SPATIAL_PART', -} -GFX_CMD_ID_LOAD_TA = 1 -GFX_CMD_ID_UNLOAD_TA = 2 -GFX_CMD_ID_INVOKE_CMD = 3 -GFX_CMD_ID_LOAD_ASD = 4 -GFX_CMD_ID_SETUP_TMR = 5 -GFX_CMD_ID_LOAD_IP_FW = 6 -GFX_CMD_ID_DESTROY_TMR = 7 -GFX_CMD_ID_SAVE_RESTORE = 8 -GFX_CMD_ID_SETUP_VMR = 9 -GFX_CMD_ID_DESTROY_VMR = 10 -GFX_CMD_ID_PROG_REG = 11 -GFX_CMD_ID_GET_FW_ATTESTATION = 15 -GFX_CMD_ID_LOAD_TOC = 32 -GFX_CMD_ID_AUTOLOAD_RLC = 33 -GFX_CMD_ID_BOOT_CFG = 34 -GFX_CMD_ID_SRIOV_SPATIAL_PART = 39 -psp_gfx_cmd_id = ctypes.c_uint32 # enum +enum_psp_gfx_boot_config = CEnum(ctypes.c_uint32) +BOOT_CONFIG_GECC = enum_psp_gfx_boot_config.define('BOOT_CONFIG_GECC', 1) -# values for enumeration 'psp_gfx_boot_config_cmd' -psp_gfx_boot_config_cmd__enumvalues = { - 1: 'BOOTCFG_CMD_SET', - 2: 'BOOTCFG_CMD_GET', - 3: 'BOOTCFG_CMD_INVALIDATE', -} -BOOTCFG_CMD_SET = 1 -BOOTCFG_CMD_GET = 2 -BOOTCFG_CMD_INVALIDATE = 3 -psp_gfx_boot_config_cmd = ctypes.c_uint32 # enum - -# values for enumeration 'psp_gfx_boot_config' -psp_gfx_boot_config__enumvalues = { - 1: 'BOOT_CONFIG_GECC', -} -BOOT_CONFIG_GECC = 1 -psp_gfx_boot_config = ctypes.c_uint32 # enum -class struct_psp_gfx_cmd_load_ta(Structure): - pass - -struct_psp_gfx_cmd_load_ta._pack_ = 1 # source:False +class struct_psp_gfx_cmd_load_ta(Struct): pass struct_psp_gfx_cmd_load_ta._fields_ = [ - ('app_phy_addr_lo', ctypes.c_uint32), - ('app_phy_addr_hi', ctypes.c_uint32), - ('app_len', ctypes.c_uint32), - ('cmd_buf_phy_addr_lo', ctypes.c_uint32), - ('cmd_buf_phy_addr_hi', ctypes.c_uint32), - ('cmd_buf_len', ctypes.c_uint32), + ('app_phy_addr_lo', ctypes.c_uint32), + ('app_phy_addr_hi', ctypes.c_uint32), + ('app_len', ctypes.c_uint32), + ('cmd_buf_phy_addr_lo', ctypes.c_uint32), + ('cmd_buf_phy_addr_hi', ctypes.c_uint32), + ('cmd_buf_len', ctypes.c_uint32), ] - -class struct_psp_gfx_cmd_unload_ta(Structure): - pass - -struct_psp_gfx_cmd_unload_ta._pack_ = 1 # source:False +class struct_psp_gfx_cmd_unload_ta(Struct): pass struct_psp_gfx_cmd_unload_ta._fields_ = [ - ('session_id', ctypes.c_uint32), + ('session_id', ctypes.c_uint32), ] - -class struct_psp_gfx_buf_desc(Structure): - pass - -struct_psp_gfx_buf_desc._pack_ = 1 # source:False +class struct_psp_gfx_buf_desc(Struct): pass struct_psp_gfx_buf_desc._fields_ = [ - ('buf_phy_addr_lo', ctypes.c_uint32), - ('buf_phy_addr_hi', ctypes.c_uint32), - ('buf_size', ctypes.c_uint32), + ('buf_phy_addr_lo', ctypes.c_uint32), + ('buf_phy_addr_hi', ctypes.c_uint32), + ('buf_size', ctypes.c_uint32), ] - -class struct_psp_gfx_buf_list(Structure): - pass - -struct_psp_gfx_buf_list._pack_ = 1 # source:False +class struct_psp_gfx_buf_list(Struct): pass struct_psp_gfx_buf_list._fields_ = [ - ('num_desc', ctypes.c_uint32), - ('total_size', ctypes.c_uint32), - ('buf_desc', struct_psp_gfx_buf_desc * 64), + ('num_desc', ctypes.c_uint32), + ('total_size', ctypes.c_uint32), + ('buf_desc', (struct_psp_gfx_buf_desc * 64)), ] - -class struct_psp_gfx_cmd_invoke_cmd(Structure): - pass - -struct_psp_gfx_cmd_invoke_cmd._pack_ = 1 # source:False +class struct_psp_gfx_cmd_invoke_cmd(Struct): pass struct_psp_gfx_cmd_invoke_cmd._fields_ = [ - ('session_id', ctypes.c_uint32), - ('ta_cmd_id', ctypes.c_uint32), - ('buf', struct_psp_gfx_buf_list), + ('session_id', ctypes.c_uint32), + ('ta_cmd_id', ctypes.c_uint32), + ('buf', struct_psp_gfx_buf_list), ] - -class struct_psp_gfx_cmd_setup_tmr(Structure): - pass - -class union_psp_gfx_cmd_setup_tmr_0(Union): - pass - -class struct_psp_gfx_cmd_setup_tmr_0_bitfield(Structure): - pass - -struct_psp_gfx_cmd_setup_tmr_0_bitfield._pack_ = 1 # source:False +class struct_psp_gfx_cmd_setup_tmr(Struct): pass +class struct_psp_gfx_cmd_setup_tmr_0(ctypes.Union): pass +class struct_psp_gfx_cmd_setup_tmr_0_bitfield(Struct): pass struct_psp_gfx_cmd_setup_tmr_0_bitfield._fields_ = [ - ('sriov_enabled', ctypes.c_uint32, 1), - ('virt_phy_addr', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 30), + ('sriov_enabled', ctypes.c_uint32,1), + ('virt_phy_addr', ctypes.c_uint32,1), + ('reserved', ctypes.c_uint32,30), ] - -union_psp_gfx_cmd_setup_tmr_0._pack_ = 1 # source:False -union_psp_gfx_cmd_setup_tmr_0._fields_ = [ - ('bitfield', struct_psp_gfx_cmd_setup_tmr_0_bitfield), - ('tmr_flags', ctypes.c_uint32), +struct_psp_gfx_cmd_setup_tmr_0._fields_ = [ + ('bitfield', struct_psp_gfx_cmd_setup_tmr_0_bitfield), + ('tmr_flags', ctypes.c_uint32), ] - -struct_psp_gfx_cmd_setup_tmr._pack_ = 1 # source:False -struct_psp_gfx_cmd_setup_tmr._anonymous_ = ('_0',) +struct_psp_gfx_cmd_setup_tmr._anonymous_ = ['_0'] struct_psp_gfx_cmd_setup_tmr._fields_ = [ - ('buf_phy_addr_lo', ctypes.c_uint32), - ('buf_phy_addr_hi', ctypes.c_uint32), - ('buf_size', ctypes.c_uint32), - ('_0', union_psp_gfx_cmd_setup_tmr_0), - ('system_phy_addr_lo', ctypes.c_uint32), - ('system_phy_addr_hi', ctypes.c_uint32), + ('buf_phy_addr_lo', ctypes.c_uint32), + ('buf_phy_addr_hi', ctypes.c_uint32), + ('buf_size', ctypes.c_uint32), + ('_0', struct_psp_gfx_cmd_setup_tmr_0), + ('system_phy_addr_lo', ctypes.c_uint32), + ('system_phy_addr_hi', ctypes.c_uint32), ] +enum_psp_gfx_fw_type = CEnum(ctypes.c_uint32) +GFX_FW_TYPE_NONE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_NONE', 0) +GFX_FW_TYPE_CP_ME = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_ME', 1) +GFX_FW_TYPE_CP_PFP = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_PFP', 2) +GFX_FW_TYPE_CP_CE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_CE', 3) +GFX_FW_TYPE_CP_MEC = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_MEC', 4) +GFX_FW_TYPE_CP_MEC_ME1 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_MEC_ME1', 5) +GFX_FW_TYPE_CP_MEC_ME2 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_MEC_ME2', 6) +GFX_FW_TYPE_RLC_V = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_V', 7) +GFX_FW_TYPE_RLC_G = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_G', 8) +GFX_FW_TYPE_SDMA0 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA0', 9) +GFX_FW_TYPE_SDMA1 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA1', 10) +GFX_FW_TYPE_DMCU_ERAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_DMCU_ERAM', 11) +GFX_FW_TYPE_DMCU_ISR = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_DMCU_ISR', 12) +GFX_FW_TYPE_VCN = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VCN', 13) +GFX_FW_TYPE_UVD = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_UVD', 14) +GFX_FW_TYPE_VCE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VCE', 15) +GFX_FW_TYPE_ISP = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_ISP', 16) +GFX_FW_TYPE_ACP = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_ACP', 17) +GFX_FW_TYPE_SMU = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SMU', 18) +GFX_FW_TYPE_MMSCH = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_MMSCH', 19) +GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', 20) +GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', 21) +GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', 22) +GFX_FW_TYPE_UVD1 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_UVD1', 23) +GFX_FW_TYPE_TOC = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_TOC', 24) +GFX_FW_TYPE_RLC_P = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_P', 25) +GFX_FW_TYPE_RLC_IRAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_IRAM', 26) +GFX_FW_TYPE_GLOBAL_TAP_DELAYS = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_GLOBAL_TAP_DELAYS', 27) +GFX_FW_TYPE_SE0_TAP_DELAYS = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SE0_TAP_DELAYS', 28) +GFX_FW_TYPE_SE1_TAP_DELAYS = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SE1_TAP_DELAYS', 29) +GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', 30) +GFX_FW_TYPE_SDMA0_JT = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA0_JT', 31) +GFX_FW_TYPE_SDMA1_JT = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA1_JT', 32) +GFX_FW_TYPE_CP_MES = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_MES', 33) +GFX_FW_TYPE_MES_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_MES_STACK', 34) +GFX_FW_TYPE_RLC_SRM_DRAM_SR = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_SRM_DRAM_SR', 35) +GFX_FW_TYPE_RLCG_SCRATCH_SR = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLCG_SCRATCH_SR', 36) +GFX_FW_TYPE_RLCP_SCRATCH_SR = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLCP_SCRATCH_SR', 37) +GFX_FW_TYPE_RLCV_SCRATCH_SR = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLCV_SCRATCH_SR', 38) +GFX_FW_TYPE_RLX6_DRAM_SR = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLX6_DRAM_SR', 39) +GFX_FW_TYPE_SDMA0_PG_CONTEXT = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA0_PG_CONTEXT', 40) +GFX_FW_TYPE_SDMA1_PG_CONTEXT = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA1_PG_CONTEXT', 41) +GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', 42) +GFX_FW_TYPE_SE0_MUX_SELECT_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SE0_MUX_SELECT_RAM', 43) +GFX_FW_TYPE_SE1_MUX_SELECT_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SE1_MUX_SELECT_RAM', 44) +GFX_FW_TYPE_ACCUM_CTRL_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_ACCUM_CTRL_RAM', 45) +GFX_FW_TYPE_RLCP_CAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLCP_CAM', 46) +GFX_FW_TYPE_RLC_SPP_CAM_EXT = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_SPP_CAM_EXT', 47) +GFX_FW_TYPE_RLC_DRAM_BOOT = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RLC_DRAM_BOOT', 48) +GFX_FW_TYPE_VCN0_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VCN0_RAM', 49) +GFX_FW_TYPE_VCN1_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VCN1_RAM', 50) +GFX_FW_TYPE_DMUB = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_DMUB', 51) +GFX_FW_TYPE_SDMA2 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA2', 52) +GFX_FW_TYPE_SDMA3 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA3', 53) +GFX_FW_TYPE_SDMA4 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA4', 54) +GFX_FW_TYPE_SDMA5 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA5', 55) +GFX_FW_TYPE_SDMA6 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA6', 56) +GFX_FW_TYPE_SDMA7 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA7', 57) +GFX_FW_TYPE_VCN1 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VCN1', 58) +GFX_FW_TYPE_CAP = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CAP', 62) +GFX_FW_TYPE_SE2_TAP_DELAYS = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SE2_TAP_DELAYS', 65) +GFX_FW_TYPE_SE3_TAP_DELAYS = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SE3_TAP_DELAYS', 66) +GFX_FW_TYPE_REG_LIST = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_REG_LIST', 67) +GFX_FW_TYPE_IMU_I = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_IMU_I', 68) +GFX_FW_TYPE_IMU_D = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_IMU_D', 69) +GFX_FW_TYPE_LSDMA = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_LSDMA', 70) +GFX_FW_TYPE_SDMA_UCODE_TH0 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA_UCODE_TH0', 71) +GFX_FW_TYPE_SDMA_UCODE_TH1 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_SDMA_UCODE_TH1', 72) +GFX_FW_TYPE_PPTABLE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_PPTABLE', 73) +GFX_FW_TYPE_DISCRETE_USB4 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_DISCRETE_USB4', 74) +GFX_FW_TYPE_TA = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_TA', 75) +GFX_FW_TYPE_RS64_MES = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MES', 76) +GFX_FW_TYPE_RS64_MES_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MES_STACK', 77) +GFX_FW_TYPE_RS64_KIQ = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_KIQ', 78) +GFX_FW_TYPE_RS64_KIQ_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_KIQ_STACK', 79) +GFX_FW_TYPE_ISP_DATA = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_ISP_DATA', 80) +GFX_FW_TYPE_CP_MES_KIQ = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_CP_MES_KIQ', 81) +GFX_FW_TYPE_MES_KIQ_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_MES_KIQ_STACK', 82) +GFX_FW_TYPE_UMSCH_DATA = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_UMSCH_DATA', 83) +GFX_FW_TYPE_UMSCH_UCODE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_UMSCH_UCODE', 84) +GFX_FW_TYPE_UMSCH_CMD_BUFFER = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_UMSCH_CMD_BUFFER', 85) +GFX_FW_TYPE_USB_DP_COMBO_PHY = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_USB_DP_COMBO_PHY', 86) +GFX_FW_TYPE_RS64_PFP = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_PFP', 87) +GFX_FW_TYPE_RS64_ME = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_ME', 88) +GFX_FW_TYPE_RS64_MEC = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MEC', 89) +GFX_FW_TYPE_RS64_PFP_P0_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_PFP_P0_STACK', 90) +GFX_FW_TYPE_RS64_PFP_P1_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_PFP_P1_STACK', 91) +GFX_FW_TYPE_RS64_ME_P0_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_ME_P0_STACK', 92) +GFX_FW_TYPE_RS64_ME_P1_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_ME_P1_STACK', 93) +GFX_FW_TYPE_RS64_MEC_P0_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MEC_P0_STACK', 94) +GFX_FW_TYPE_RS64_MEC_P1_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MEC_P1_STACK', 95) +GFX_FW_TYPE_RS64_MEC_P2_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MEC_P2_STACK', 96) +GFX_FW_TYPE_RS64_MEC_P3_STACK = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_RS64_MEC_P3_STACK', 97) +GFX_FW_TYPE_VPEC_FW1 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VPEC_FW1', 100) +GFX_FW_TYPE_VPEC_FW2 = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VPEC_FW2', 101) +GFX_FW_TYPE_VPE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_VPE', 102) +GFX_FW_TYPE_JPEG_RAM = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_JPEG_RAM', 128) +GFX_FW_TYPE_P2S_TABLE = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_P2S_TABLE', 129) +GFX_FW_TYPE_MAX = enum_psp_gfx_fw_type.define('GFX_FW_TYPE_MAX', 130) - -# values for enumeration 'psp_gfx_fw_type' -psp_gfx_fw_type__enumvalues = { - 0: 'GFX_FW_TYPE_NONE', - 1: 'GFX_FW_TYPE_CP_ME', - 2: 'GFX_FW_TYPE_CP_PFP', - 3: 'GFX_FW_TYPE_CP_CE', - 4: 'GFX_FW_TYPE_CP_MEC', - 5: 'GFX_FW_TYPE_CP_MEC_ME1', - 6: 'GFX_FW_TYPE_CP_MEC_ME2', - 7: 'GFX_FW_TYPE_RLC_V', - 8: 'GFX_FW_TYPE_RLC_G', - 9: 'GFX_FW_TYPE_SDMA0', - 10: 'GFX_FW_TYPE_SDMA1', - 11: 'GFX_FW_TYPE_DMCU_ERAM', - 12: 'GFX_FW_TYPE_DMCU_ISR', - 13: 'GFX_FW_TYPE_VCN', - 14: 'GFX_FW_TYPE_UVD', - 15: 'GFX_FW_TYPE_VCE', - 16: 'GFX_FW_TYPE_ISP', - 17: 'GFX_FW_TYPE_ACP', - 18: 'GFX_FW_TYPE_SMU', - 19: 'GFX_FW_TYPE_MMSCH', - 20: 'GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', - 21: 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', - 22: 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', - 23: 'GFX_FW_TYPE_UVD1', - 24: 'GFX_FW_TYPE_TOC', - 25: 'GFX_FW_TYPE_RLC_P', - 26: 'GFX_FW_TYPE_RLC_IRAM', - 27: 'GFX_FW_TYPE_GLOBAL_TAP_DELAYS', - 28: 'GFX_FW_TYPE_SE0_TAP_DELAYS', - 29: 'GFX_FW_TYPE_SE1_TAP_DELAYS', - 30: 'GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', - 31: 'GFX_FW_TYPE_SDMA0_JT', - 32: 'GFX_FW_TYPE_SDMA1_JT', - 33: 'GFX_FW_TYPE_CP_MES', - 34: 'GFX_FW_TYPE_MES_STACK', - 35: 'GFX_FW_TYPE_RLC_SRM_DRAM_SR', - 36: 'GFX_FW_TYPE_RLCG_SCRATCH_SR', - 37: 'GFX_FW_TYPE_RLCP_SCRATCH_SR', - 38: 'GFX_FW_TYPE_RLCV_SCRATCH_SR', - 39: 'GFX_FW_TYPE_RLX6_DRAM_SR', - 40: 'GFX_FW_TYPE_SDMA0_PG_CONTEXT', - 41: 'GFX_FW_TYPE_SDMA1_PG_CONTEXT', - 42: 'GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', - 43: 'GFX_FW_TYPE_SE0_MUX_SELECT_RAM', - 44: 'GFX_FW_TYPE_SE1_MUX_SELECT_RAM', - 45: 'GFX_FW_TYPE_ACCUM_CTRL_RAM', - 46: 'GFX_FW_TYPE_RLCP_CAM', - 47: 'GFX_FW_TYPE_RLC_SPP_CAM_EXT', - 48: 'GFX_FW_TYPE_RLC_DRAM_BOOT', - 49: 'GFX_FW_TYPE_VCN0_RAM', - 50: 'GFX_FW_TYPE_VCN1_RAM', - 51: 'GFX_FW_TYPE_DMUB', - 52: 'GFX_FW_TYPE_SDMA2', - 53: 'GFX_FW_TYPE_SDMA3', - 54: 'GFX_FW_TYPE_SDMA4', - 55: 'GFX_FW_TYPE_SDMA5', - 56: 'GFX_FW_TYPE_SDMA6', - 57: 'GFX_FW_TYPE_SDMA7', - 58: 'GFX_FW_TYPE_VCN1', - 62: 'GFX_FW_TYPE_CAP', - 65: 'GFX_FW_TYPE_SE2_TAP_DELAYS', - 66: 'GFX_FW_TYPE_SE3_TAP_DELAYS', - 67: 'GFX_FW_TYPE_REG_LIST', - 68: 'GFX_FW_TYPE_IMU_I', - 69: 'GFX_FW_TYPE_IMU_D', - 70: 'GFX_FW_TYPE_LSDMA', - 71: 'GFX_FW_TYPE_SDMA_UCODE_TH0', - 72: 'GFX_FW_TYPE_SDMA_UCODE_TH1', - 73: 'GFX_FW_TYPE_PPTABLE', - 74: 'GFX_FW_TYPE_DISCRETE_USB4', - 75: 'GFX_FW_TYPE_TA', - 76: 'GFX_FW_TYPE_RS64_MES', - 77: 'GFX_FW_TYPE_RS64_MES_STACK', - 78: 'GFX_FW_TYPE_RS64_KIQ', - 79: 'GFX_FW_TYPE_RS64_KIQ_STACK', - 80: 'GFX_FW_TYPE_ISP_DATA', - 81: 'GFX_FW_TYPE_CP_MES_KIQ', - 82: 'GFX_FW_TYPE_MES_KIQ_STACK', - 83: 'GFX_FW_TYPE_UMSCH_DATA', - 84: 'GFX_FW_TYPE_UMSCH_UCODE', - 85: 'GFX_FW_TYPE_UMSCH_CMD_BUFFER', - 86: 'GFX_FW_TYPE_USB_DP_COMBO_PHY', - 87: 'GFX_FW_TYPE_RS64_PFP', - 88: 'GFX_FW_TYPE_RS64_ME', - 89: 'GFX_FW_TYPE_RS64_MEC', - 90: 'GFX_FW_TYPE_RS64_PFP_P0_STACK', - 91: 'GFX_FW_TYPE_RS64_PFP_P1_STACK', - 92: 'GFX_FW_TYPE_RS64_ME_P0_STACK', - 93: 'GFX_FW_TYPE_RS64_ME_P1_STACK', - 94: 'GFX_FW_TYPE_RS64_MEC_P0_STACK', - 95: 'GFX_FW_TYPE_RS64_MEC_P1_STACK', - 96: 'GFX_FW_TYPE_RS64_MEC_P2_STACK', - 97: 'GFX_FW_TYPE_RS64_MEC_P3_STACK', - 100: 'GFX_FW_TYPE_VPEC_FW1', - 101: 'GFX_FW_TYPE_VPEC_FW2', - 102: 'GFX_FW_TYPE_VPE', - 128: 'GFX_FW_TYPE_JPEG_RAM', - 129: 'GFX_FW_TYPE_P2S_TABLE', - 130: 'GFX_FW_TYPE_MAX', -} -GFX_FW_TYPE_NONE = 0 -GFX_FW_TYPE_CP_ME = 1 -GFX_FW_TYPE_CP_PFP = 2 -GFX_FW_TYPE_CP_CE = 3 -GFX_FW_TYPE_CP_MEC = 4 -GFX_FW_TYPE_CP_MEC_ME1 = 5 -GFX_FW_TYPE_CP_MEC_ME2 = 6 -GFX_FW_TYPE_RLC_V = 7 -GFX_FW_TYPE_RLC_G = 8 -GFX_FW_TYPE_SDMA0 = 9 -GFX_FW_TYPE_SDMA1 = 10 -GFX_FW_TYPE_DMCU_ERAM = 11 -GFX_FW_TYPE_DMCU_ISR = 12 -GFX_FW_TYPE_VCN = 13 -GFX_FW_TYPE_UVD = 14 -GFX_FW_TYPE_VCE = 15 -GFX_FW_TYPE_ISP = 16 -GFX_FW_TYPE_ACP = 17 -GFX_FW_TYPE_SMU = 18 -GFX_FW_TYPE_MMSCH = 19 -GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20 -GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21 -GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22 -GFX_FW_TYPE_UVD1 = 23 -GFX_FW_TYPE_TOC = 24 -GFX_FW_TYPE_RLC_P = 25 -GFX_FW_TYPE_RLC_IRAM = 26 -GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27 -GFX_FW_TYPE_SE0_TAP_DELAYS = 28 -GFX_FW_TYPE_SE1_TAP_DELAYS = 29 -GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30 -GFX_FW_TYPE_SDMA0_JT = 31 -GFX_FW_TYPE_SDMA1_JT = 32 -GFX_FW_TYPE_CP_MES = 33 -GFX_FW_TYPE_MES_STACK = 34 -GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35 -GFX_FW_TYPE_RLCG_SCRATCH_SR = 36 -GFX_FW_TYPE_RLCP_SCRATCH_SR = 37 -GFX_FW_TYPE_RLCV_SCRATCH_SR = 38 -GFX_FW_TYPE_RLX6_DRAM_SR = 39 -GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40 -GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41 -GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42 -GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43 -GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44 -GFX_FW_TYPE_ACCUM_CTRL_RAM = 45 -GFX_FW_TYPE_RLCP_CAM = 46 -GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47 -GFX_FW_TYPE_RLC_DRAM_BOOT = 48 -GFX_FW_TYPE_VCN0_RAM = 49 -GFX_FW_TYPE_VCN1_RAM = 50 -GFX_FW_TYPE_DMUB = 51 -GFX_FW_TYPE_SDMA2 = 52 -GFX_FW_TYPE_SDMA3 = 53 -GFX_FW_TYPE_SDMA4 = 54 -GFX_FW_TYPE_SDMA5 = 55 -GFX_FW_TYPE_SDMA6 = 56 -GFX_FW_TYPE_SDMA7 = 57 -GFX_FW_TYPE_VCN1 = 58 -GFX_FW_TYPE_CAP = 62 -GFX_FW_TYPE_SE2_TAP_DELAYS = 65 -GFX_FW_TYPE_SE3_TAP_DELAYS = 66 -GFX_FW_TYPE_REG_LIST = 67 -GFX_FW_TYPE_IMU_I = 68 -GFX_FW_TYPE_IMU_D = 69 -GFX_FW_TYPE_LSDMA = 70 -GFX_FW_TYPE_SDMA_UCODE_TH0 = 71 -GFX_FW_TYPE_SDMA_UCODE_TH1 = 72 -GFX_FW_TYPE_PPTABLE = 73 -GFX_FW_TYPE_DISCRETE_USB4 = 74 -GFX_FW_TYPE_TA = 75 -GFX_FW_TYPE_RS64_MES = 76 -GFX_FW_TYPE_RS64_MES_STACK = 77 -GFX_FW_TYPE_RS64_KIQ = 78 -GFX_FW_TYPE_RS64_KIQ_STACK = 79 -GFX_FW_TYPE_ISP_DATA = 80 -GFX_FW_TYPE_CP_MES_KIQ = 81 -GFX_FW_TYPE_MES_KIQ_STACK = 82 -GFX_FW_TYPE_UMSCH_DATA = 83 -GFX_FW_TYPE_UMSCH_UCODE = 84 -GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85 -GFX_FW_TYPE_USB_DP_COMBO_PHY = 86 -GFX_FW_TYPE_RS64_PFP = 87 -GFX_FW_TYPE_RS64_ME = 88 -GFX_FW_TYPE_RS64_MEC = 89 -GFX_FW_TYPE_RS64_PFP_P0_STACK = 90 -GFX_FW_TYPE_RS64_PFP_P1_STACK = 91 -GFX_FW_TYPE_RS64_ME_P0_STACK = 92 -GFX_FW_TYPE_RS64_ME_P1_STACK = 93 -GFX_FW_TYPE_RS64_MEC_P0_STACK = 94 -GFX_FW_TYPE_RS64_MEC_P1_STACK = 95 -GFX_FW_TYPE_RS64_MEC_P2_STACK = 96 -GFX_FW_TYPE_RS64_MEC_P3_STACK = 97 -GFX_FW_TYPE_VPEC_FW1 = 100 -GFX_FW_TYPE_VPEC_FW2 = 101 -GFX_FW_TYPE_VPE = 102 -GFX_FW_TYPE_JPEG_RAM = 128 -GFX_FW_TYPE_P2S_TABLE = 129 -GFX_FW_TYPE_MAX = 130 -psp_gfx_fw_type = ctypes.c_uint32 # enum -class struct_psp_gfx_cmd_load_ip_fw(Structure): - pass - -struct_psp_gfx_cmd_load_ip_fw._pack_ = 1 # source:False +class struct_psp_gfx_cmd_load_ip_fw(Struct): pass struct_psp_gfx_cmd_load_ip_fw._fields_ = [ - ('fw_phy_addr_lo', ctypes.c_uint32), - ('fw_phy_addr_hi', ctypes.c_uint32), - ('fw_size', ctypes.c_uint32), - ('fw_type', psp_gfx_fw_type), + ('fw_phy_addr_lo', ctypes.c_uint32), + ('fw_phy_addr_hi', ctypes.c_uint32), + ('fw_size', ctypes.c_uint32), + ('fw_type', enum_psp_gfx_fw_type), ] - -class struct_psp_gfx_cmd_save_restore_ip_fw(Structure): - pass - -struct_psp_gfx_cmd_save_restore_ip_fw._pack_ = 1 # source:False +class struct_psp_gfx_cmd_save_restore_ip_fw(Struct): pass struct_psp_gfx_cmd_save_restore_ip_fw._fields_ = [ - ('save_fw', ctypes.c_uint32), - ('save_restore_addr_lo', ctypes.c_uint32), - ('save_restore_addr_hi', ctypes.c_uint32), - ('buf_size', ctypes.c_uint32), - ('fw_type', psp_gfx_fw_type), + ('save_fw', ctypes.c_uint32), + ('save_restore_addr_lo', ctypes.c_uint32), + ('save_restore_addr_hi', ctypes.c_uint32), + ('buf_size', ctypes.c_uint32), + ('fw_type', enum_psp_gfx_fw_type), ] - -class struct_psp_gfx_cmd_reg_prog(Structure): - pass - -struct_psp_gfx_cmd_reg_prog._pack_ = 1 # source:False +class struct_psp_gfx_cmd_reg_prog(Struct): pass struct_psp_gfx_cmd_reg_prog._fields_ = [ - ('reg_value', ctypes.c_uint32), - ('reg_id', ctypes.c_uint32), + ('reg_value', ctypes.c_uint32), + ('reg_id', ctypes.c_uint32), ] - -class struct_psp_gfx_cmd_load_toc(Structure): - pass - -struct_psp_gfx_cmd_load_toc._pack_ = 1 # source:False +class struct_psp_gfx_cmd_load_toc(Struct): pass struct_psp_gfx_cmd_load_toc._fields_ = [ - ('toc_phy_addr_lo', ctypes.c_uint32), - ('toc_phy_addr_hi', ctypes.c_uint32), - ('toc_size', ctypes.c_uint32), + ('toc_phy_addr_lo', ctypes.c_uint32), + ('toc_phy_addr_hi', ctypes.c_uint32), + ('toc_size', ctypes.c_uint32), ] - -class struct_psp_gfx_cmd_boot_cfg(Structure): - pass - -struct_psp_gfx_cmd_boot_cfg._pack_ = 1 # source:False +class struct_psp_gfx_cmd_boot_cfg(Struct): pass struct_psp_gfx_cmd_boot_cfg._fields_ = [ - ('timestamp', ctypes.c_uint32), - ('sub_cmd', psp_gfx_boot_config_cmd), - ('boot_config', ctypes.c_uint32), - ('boot_config_valid', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), + ('sub_cmd', enum_psp_gfx_boot_config_cmd), + ('boot_config', ctypes.c_uint32), + ('boot_config_valid', ctypes.c_uint32), ] - -class struct_psp_gfx_cmd_sriov_spatial_part(Structure): - pass - -struct_psp_gfx_cmd_sriov_spatial_part._pack_ = 1 # source:False +class struct_psp_gfx_cmd_sriov_spatial_part(Struct): pass struct_psp_gfx_cmd_sriov_spatial_part._fields_ = [ - ('mode', ctypes.c_uint32), - ('override_ips', ctypes.c_uint32), - ('override_xcds_avail', ctypes.c_uint32), - ('override_this_aid', ctypes.c_uint32), + ('mode', ctypes.c_uint32), + ('override_ips', ctypes.c_uint32), + ('override_xcds_avail', ctypes.c_uint32), + ('override_this_aid', ctypes.c_uint32), ] - -class union_psp_gfx_commands(Union): - pass - -union_psp_gfx_commands._pack_ = 1 # source:False +class union_psp_gfx_commands(ctypes.Union): pass union_psp_gfx_commands._fields_ = [ - ('cmd_load_ta', struct_psp_gfx_cmd_load_ta), - ('cmd_unload_ta', struct_psp_gfx_cmd_unload_ta), - ('cmd_invoke_cmd', struct_psp_gfx_cmd_invoke_cmd), - ('cmd_setup_tmr', struct_psp_gfx_cmd_setup_tmr), - ('cmd_load_ip_fw', struct_psp_gfx_cmd_load_ip_fw), - ('cmd_save_restore_ip_fw', struct_psp_gfx_cmd_save_restore_ip_fw), - ('cmd_setup_reg_prog', struct_psp_gfx_cmd_reg_prog), - ('cmd_setup_vmr', struct_psp_gfx_cmd_setup_tmr), - ('cmd_load_toc', struct_psp_gfx_cmd_load_toc), - ('boot_cfg', struct_psp_gfx_cmd_boot_cfg), - ('cmd_spatial_part', struct_psp_gfx_cmd_sriov_spatial_part), - ('PADDING_0', ctypes.c_ubyte * 768), + ('cmd_load_ta', struct_psp_gfx_cmd_load_ta), + ('cmd_unload_ta', struct_psp_gfx_cmd_unload_ta), + ('cmd_invoke_cmd', struct_psp_gfx_cmd_invoke_cmd), + ('cmd_setup_tmr', struct_psp_gfx_cmd_setup_tmr), + ('cmd_load_ip_fw', struct_psp_gfx_cmd_load_ip_fw), + ('cmd_save_restore_ip_fw', struct_psp_gfx_cmd_save_restore_ip_fw), + ('cmd_setup_reg_prog', struct_psp_gfx_cmd_reg_prog), + ('cmd_setup_vmr', struct_psp_gfx_cmd_setup_tmr), + ('cmd_load_toc', struct_psp_gfx_cmd_load_toc), + ('boot_cfg', struct_psp_gfx_cmd_boot_cfg), + ('cmd_spatial_part', struct_psp_gfx_cmd_sriov_spatial_part), ] - -class struct_psp_gfx_uresp_reserved(Structure): - pass - -struct_psp_gfx_uresp_reserved._pack_ = 1 # source:False +class struct_psp_gfx_uresp_reserved(Struct): pass struct_psp_gfx_uresp_reserved._fields_ = [ - ('reserved', ctypes.c_uint32 * 8), + ('reserved', (ctypes.c_uint32 * 8)), ] - -class struct_psp_gfx_uresp_fwar_db_info(Structure): - pass - -struct_psp_gfx_uresp_fwar_db_info._pack_ = 1 # source:False +class struct_psp_gfx_uresp_fwar_db_info(Struct): pass struct_psp_gfx_uresp_fwar_db_info._fields_ = [ - ('fwar_db_addr_lo', ctypes.c_uint32), - ('fwar_db_addr_hi', ctypes.c_uint32), + ('fwar_db_addr_lo', ctypes.c_uint32), + ('fwar_db_addr_hi', ctypes.c_uint32), ] - -class struct_psp_gfx_uresp_bootcfg(Structure): - pass - -struct_psp_gfx_uresp_bootcfg._pack_ = 1 # source:False +class struct_psp_gfx_uresp_bootcfg(Struct): pass struct_psp_gfx_uresp_bootcfg._fields_ = [ - ('boot_cfg', ctypes.c_uint32), + ('boot_cfg', ctypes.c_uint32), ] - -class union_psp_gfx_uresp(Union): - pass - -union_psp_gfx_uresp._pack_ = 1 # source:False +class union_psp_gfx_uresp(ctypes.Union): pass union_psp_gfx_uresp._fields_ = [ - ('reserved', struct_psp_gfx_uresp_reserved), - ('boot_cfg', struct_psp_gfx_uresp_bootcfg), - ('fwar_db_info', struct_psp_gfx_uresp_fwar_db_info), - ('PADDING_0', ctypes.c_ubyte * 24), + ('reserved', struct_psp_gfx_uresp_reserved), + ('boot_cfg', struct_psp_gfx_uresp_bootcfg), + ('fwar_db_info', struct_psp_gfx_uresp_fwar_db_info), ] - -class struct_psp_gfx_resp(Structure): - pass - -struct_psp_gfx_resp._pack_ = 1 # source:False +class struct_psp_gfx_resp(Struct): pass struct_psp_gfx_resp._fields_ = [ - ('status', ctypes.c_uint32), - ('session_id', ctypes.c_uint32), - ('fw_addr_lo', ctypes.c_uint32), - ('fw_addr_hi', ctypes.c_uint32), - ('tmr_size', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 11), - ('uresp', union_psp_gfx_uresp), + ('status', ctypes.c_uint32), + ('session_id', ctypes.c_uint32), + ('fw_addr_lo', ctypes.c_uint32), + ('fw_addr_hi', ctypes.c_uint32), + ('tmr_size', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 11)), + ('uresp', union_psp_gfx_uresp), ] - -class struct_psp_gfx_cmd_resp(Structure): - pass - -struct_psp_gfx_cmd_resp._pack_ = 1 # source:False +class struct_psp_gfx_cmd_resp(Struct): pass struct_psp_gfx_cmd_resp._fields_ = [ - ('buf_size', ctypes.c_uint32), - ('buf_version', ctypes.c_uint32), - ('cmd_id', ctypes.c_uint32), - ('resp_buf_addr_lo', ctypes.c_uint32), - ('resp_buf_addr_hi', ctypes.c_uint32), - ('resp_offset', ctypes.c_uint32), - ('resp_buf_size', ctypes.c_uint32), - ('cmd', union_psp_gfx_commands), - ('reserved_1', ctypes.c_ubyte * 52), - ('resp', struct_psp_gfx_resp), - ('reserved_2', ctypes.c_ubyte * 64), + ('buf_size', ctypes.c_uint32), + ('buf_version', ctypes.c_uint32), + ('cmd_id', ctypes.c_uint32), + ('resp_buf_addr_lo', ctypes.c_uint32), + ('resp_buf_addr_hi', ctypes.c_uint32), + ('resp_offset', ctypes.c_uint32), + ('resp_buf_size', ctypes.c_uint32), + ('cmd', union_psp_gfx_commands), + ('reserved_1', (ctypes.c_ubyte * 52)), + ('resp', struct_psp_gfx_resp), + ('reserved_2', (ctypes.c_ubyte * 64)), ] - -class struct_psp_gfx_rb_frame(Structure): - pass - -struct_psp_gfx_rb_frame._pack_ = 1 # source:False +class struct_psp_gfx_rb_frame(Struct): pass struct_psp_gfx_rb_frame._fields_ = [ - ('cmd_buf_addr_lo', ctypes.c_uint32), - ('cmd_buf_addr_hi', ctypes.c_uint32), - ('cmd_buf_size', ctypes.c_uint32), - ('fence_addr_lo', ctypes.c_uint32), - ('fence_addr_hi', ctypes.c_uint32), - ('fence_value', ctypes.c_uint32), - ('sid_lo', ctypes.c_uint32), - ('sid_hi', ctypes.c_uint32), - ('vmid', ctypes.c_ubyte), - ('frame_type', ctypes.c_ubyte), - ('reserved1', ctypes.c_ubyte * 2), - ('reserved2', ctypes.c_uint32 * 7), + ('cmd_buf_addr_lo', ctypes.c_uint32), + ('cmd_buf_addr_hi', ctypes.c_uint32), + ('cmd_buf_size', ctypes.c_uint32), + ('fence_addr_lo', ctypes.c_uint32), + ('fence_addr_hi', ctypes.c_uint32), + ('fence_value', ctypes.c_uint32), + ('sid_lo', ctypes.c_uint32), + ('sid_hi', ctypes.c_uint32), + ('vmid', ctypes.c_ubyte), + ('frame_type', ctypes.c_ubyte), + ('reserved1', (ctypes.c_ubyte * 2)), + ('reserved2', (ctypes.c_uint32 * 7)), ] +enum_tee_error_code = CEnum(ctypes.c_uint32) +TEE_SUCCESS = enum_tee_error_code.define('TEE_SUCCESS', 0) +TEE_ERROR_NOT_SUPPORTED = enum_tee_error_code.define('TEE_ERROR_NOT_SUPPORTED', 4294901770) +enum_psp_shared_mem_size = CEnum(ctypes.c_uint32) +PSP_ASD_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_ASD_SHARED_MEM_SIZE', 0) +PSP_XGMI_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_XGMI_SHARED_MEM_SIZE', 16384) +PSP_RAS_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_RAS_SHARED_MEM_SIZE', 16384) +PSP_HDCP_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_HDCP_SHARED_MEM_SIZE', 16384) +PSP_DTM_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_DTM_SHARED_MEM_SIZE', 16384) +PSP_RAP_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_RAP_SHARED_MEM_SIZE', 16384) +PSP_SECUREDISPLAY_SHARED_MEM_SIZE = enum_psp_shared_mem_size.define('PSP_SECUREDISPLAY_SHARED_MEM_SIZE', 16384) -# values for enumeration 'tee_error_code' -tee_error_code__enumvalues = { - 0: 'TEE_SUCCESS', - 4294901770: 'TEE_ERROR_NOT_SUPPORTED', -} -TEE_SUCCESS = 0 -TEE_ERROR_NOT_SUPPORTED = 4294901770 -tee_error_code = ctypes.c_uint32 # enum -__AMDGPU_PSP_H__ = True # macro -PSP_FENCE_BUFFER_SIZE = 0x1000 # macro -PSP_CMD_BUFFER_SIZE = 0x1000 # macro -PSP_1_MEG = 0x100000 # macro -# def PSP_TMR_SIZE(adev): # macro -# return ((adev)->asic_type==CHIP_ALDEBARAN?0x800000:0x400000) -PSP_TMR_ALIGNMENT = 0x100000 # macro -PSP_FW_NAME_LEN = 0x24 # macro -AMDGPU_XGMI_MAX_CONNECTED_NODES = 64 # macro -MEM_TRAIN_SYSTEM_SIGNATURE = 0x54534942 # macro -GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES = 0x1000 # macro -GDDR6_MEM_TRAINING_OFFSET = 0x8000 # macro -BIST_MEM_TRAINING_ENCROACHED_SIZE = 0x2000000 # macro -PSP_RUNTIME_DB_SIZE_IN_BYTES = 0x10000 # macro -PSP_RUNTIME_DB_OFFSET = 0x100000 # macro -PSP_RUNTIME_DB_COOKIE_ID = 0x0ed5 # macro -PSP_RUNTIME_DB_VER_1 = 0x0100 # macro -PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT = 0x40 # macro +enum_ta_type_id = CEnum(ctypes.c_uint32) +TA_TYPE_XGMI = enum_ta_type_id.define('TA_TYPE_XGMI', 1) +TA_TYPE_RAS = enum_ta_type_id.define('TA_TYPE_RAS', 2) +TA_TYPE_HDCP = enum_ta_type_id.define('TA_TYPE_HDCP', 3) +TA_TYPE_DTM = enum_ta_type_id.define('TA_TYPE_DTM', 4) +TA_TYPE_RAP = enum_ta_type_id.define('TA_TYPE_RAP', 5) +TA_TYPE_SECUREDISPLAY = enum_ta_type_id.define('TA_TYPE_SECUREDISPLAY', 6) +TA_TYPE_MAX_INDEX = enum_ta_type_id.define('TA_TYPE_MAX_INDEX', 7) -# values for enumeration 'psp_shared_mem_size' -psp_shared_mem_size__enumvalues = { - 0: 'PSP_ASD_SHARED_MEM_SIZE', - 16384: 'PSP_XGMI_SHARED_MEM_SIZE', - 16384: 'PSP_RAS_SHARED_MEM_SIZE', - 16384: 'PSP_HDCP_SHARED_MEM_SIZE', - 16384: 'PSP_DTM_SHARED_MEM_SIZE', - 16384: 'PSP_RAP_SHARED_MEM_SIZE', - 16384: 'PSP_SECUREDISPLAY_SHARED_MEM_SIZE', -} -PSP_ASD_SHARED_MEM_SIZE = 0 -PSP_XGMI_SHARED_MEM_SIZE = 16384 -PSP_RAS_SHARED_MEM_SIZE = 16384 -PSP_HDCP_SHARED_MEM_SIZE = 16384 -PSP_DTM_SHARED_MEM_SIZE = 16384 -PSP_RAP_SHARED_MEM_SIZE = 16384 -PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 16384 -psp_shared_mem_size = ctypes.c_uint32 # enum +class struct_psp_context(Struct): pass +class struct_psp_xgmi_node_info(Struct): pass +class struct_psp_xgmi_topology_info(Struct): pass +class struct_psp_bin_desc(Struct): pass +enum_psp_bootloader_cmd = CEnum(ctypes.c_uint32) +PSP_BL__LOAD_SYSDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_SYSDRV', 65536) +PSP_BL__LOAD_SOSDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_SOSDRV', 131072) +PSP_BL__LOAD_KEY_DATABASE = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_KEY_DATABASE', 524288) +PSP_BL__LOAD_SOCDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_SOCDRV', 720896) +PSP_BL__LOAD_DBGDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_DBGDRV', 786432) +PSP_BL__LOAD_HADDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_HADDRV', 786432) +PSP_BL__LOAD_INTFDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_INTFDRV', 851968) +PSP_BL__LOAD_RASDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_RASDRV', 917504) +PSP_BL__LOAD_IPKEYMGRDRV = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_IPKEYMGRDRV', 983040) +PSP_BL__DRAM_LONG_TRAIN = enum_psp_bootloader_cmd.define('PSP_BL__DRAM_LONG_TRAIN', 1048576) +PSP_BL__DRAM_SHORT_TRAIN = enum_psp_bootloader_cmd.define('PSP_BL__DRAM_SHORT_TRAIN', 2097152) +PSP_BL__LOAD_TOS_SPL_TABLE = enum_psp_bootloader_cmd.define('PSP_BL__LOAD_TOS_SPL_TABLE', 268435456) -# values for enumeration 'ta_type_id' -ta_type_id__enumvalues = { - 1: 'TA_TYPE_XGMI', - 2: 'TA_TYPE_RAS', - 3: 'TA_TYPE_HDCP', - 4: 'TA_TYPE_DTM', - 5: 'TA_TYPE_RAP', - 6: 'TA_TYPE_SECUREDISPLAY', - 7: 'TA_TYPE_MAX_INDEX', -} -TA_TYPE_XGMI = 1 -TA_TYPE_RAS = 2 -TA_TYPE_HDCP = 3 -TA_TYPE_DTM = 4 -TA_TYPE_RAP = 5 -TA_TYPE_SECUREDISPLAY = 6 -TA_TYPE_MAX_INDEX = 7 -ta_type_id = ctypes.c_uint32 # enum -class struct_psp_context(Structure): - pass +enum_psp_ring_type = CEnum(ctypes.c_uint32) +PSP_RING_TYPE__INVALID = enum_psp_ring_type.define('PSP_RING_TYPE__INVALID', 0) +PSP_RING_TYPE__UM = enum_psp_ring_type.define('PSP_RING_TYPE__UM', 1) +PSP_RING_TYPE__KM = enum_psp_ring_type.define('PSP_RING_TYPE__KM', 2) -class struct_psp_xgmi_node_info(Structure): - pass +enum_psp_reg_prog_id = CEnum(ctypes.c_uint32) +PSP_REG_IH_RB_CNTL = enum_psp_reg_prog_id.define('PSP_REG_IH_RB_CNTL', 0) +PSP_REG_IH_RB_CNTL_RING1 = enum_psp_reg_prog_id.define('PSP_REG_IH_RB_CNTL_RING1', 1) +PSP_REG_IH_RB_CNTL_RING2 = enum_psp_reg_prog_id.define('PSP_REG_IH_RB_CNTL_RING2', 2) +PSP_REG_LAST = enum_psp_reg_prog_id.define('PSP_REG_LAST', 3) -class struct_psp_xgmi_topology_info(Structure): - pass +enum_psp_memory_training_init_flag = CEnum(ctypes.c_uint32) +PSP_MEM_TRAIN_NOT_SUPPORT = enum_psp_memory_training_init_flag.define('PSP_MEM_TRAIN_NOT_SUPPORT', 0) +PSP_MEM_TRAIN_SUPPORT = enum_psp_memory_training_init_flag.define('PSP_MEM_TRAIN_SUPPORT', 1) +PSP_MEM_TRAIN_INIT_FAILED = enum_psp_memory_training_init_flag.define('PSP_MEM_TRAIN_INIT_FAILED', 2) +PSP_MEM_TRAIN_RESERVE_SUCCESS = enum_psp_memory_training_init_flag.define('PSP_MEM_TRAIN_RESERVE_SUCCESS', 4) +PSP_MEM_TRAIN_INIT_SUCCESS = enum_psp_memory_training_init_flag.define('PSP_MEM_TRAIN_INIT_SUCCESS', 8) -class struct_psp_bin_desc(Structure): - pass +enum_psp_memory_training_ops = CEnum(ctypes.c_uint32) +PSP_MEM_TRAIN_SEND_LONG_MSG = enum_psp_memory_training_ops.define('PSP_MEM_TRAIN_SEND_LONG_MSG', 1) +PSP_MEM_TRAIN_SAVE = enum_psp_memory_training_ops.define('PSP_MEM_TRAIN_SAVE', 2) +PSP_MEM_TRAIN_RESTORE = enum_psp_memory_training_ops.define('PSP_MEM_TRAIN_RESTORE', 4) +PSP_MEM_TRAIN_SEND_SHORT_MSG = enum_psp_memory_training_ops.define('PSP_MEM_TRAIN_SEND_SHORT_MSG', 8) +PSP_MEM_TRAIN_COLD_BOOT = enum_psp_memory_training_ops.define('PSP_MEM_TRAIN_COLD_BOOT', 1) +PSP_MEM_TRAIN_RESUME = enum_psp_memory_training_ops.define('PSP_MEM_TRAIN_RESUME', 8) +enum_psp_runtime_entry_type = CEnum(ctypes.c_uint32) +PSP_RUNTIME_ENTRY_TYPE_INVALID = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_INVALID', 0) +PSP_RUNTIME_ENTRY_TYPE_TEST = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_TEST', 1) +PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', 2) +PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', 3) +PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', 4) +PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', 5) +PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = enum_psp_runtime_entry_type.define('PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', 6) -# values for enumeration 'psp_bootloader_cmd' -psp_bootloader_cmd__enumvalues = { - 65536: 'PSP_BL__LOAD_SYSDRV', - 131072: 'PSP_BL__LOAD_SOSDRV', - 524288: 'PSP_BL__LOAD_KEY_DATABASE', - 720896: 'PSP_BL__LOAD_SOCDRV', - 786432: 'PSP_BL__LOAD_DBGDRV', - 786432: 'PSP_BL__LOAD_HADDRV', - 851968: 'PSP_BL__LOAD_INTFDRV', - 917504: 'PSP_BL__LOAD_RASDRV', - 983040: 'PSP_BL__LOAD_IPKEYMGRDRV', - 1048576: 'PSP_BL__DRAM_LONG_TRAIN', - 2097152: 'PSP_BL__DRAM_SHORT_TRAIN', - 268435456: 'PSP_BL__LOAD_TOS_SPL_TABLE', -} -PSP_BL__LOAD_SYSDRV = 65536 -PSP_BL__LOAD_SOSDRV = 131072 -PSP_BL__LOAD_KEY_DATABASE = 524288 -PSP_BL__LOAD_SOCDRV = 720896 -PSP_BL__LOAD_DBGDRV = 786432 -PSP_BL__LOAD_HADDRV = 786432 -PSP_BL__LOAD_INTFDRV = 851968 -PSP_BL__LOAD_RASDRV = 917504 -PSP_BL__LOAD_IPKEYMGRDRV = 983040 -PSP_BL__DRAM_LONG_TRAIN = 1048576 -PSP_BL__DRAM_SHORT_TRAIN = 2097152 -PSP_BL__LOAD_TOS_SPL_TABLE = 268435456 -psp_bootloader_cmd = ctypes.c_uint32 # enum +enum_psp_runtime_boot_cfg_feature = CEnum(ctypes.c_uint32) +BOOT_CFG_FEATURE_GECC = enum_psp_runtime_boot_cfg_feature.define('BOOT_CFG_FEATURE_GECC', 1) +BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = enum_psp_runtime_boot_cfg_feature.define('BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', 2) -# values for enumeration 'psp_ring_type' -psp_ring_type__enumvalues = { - 0: 'PSP_RING_TYPE__INVALID', - 1: 'PSP_RING_TYPE__UM', - 2: 'PSP_RING_TYPE__KM', -} -PSP_RING_TYPE__INVALID = 0 -PSP_RING_TYPE__UM = 1 -PSP_RING_TYPE__KM = 2 -psp_ring_type = ctypes.c_uint32 # enum +enum_psp_runtime_scpm_authentication = CEnum(ctypes.c_uint32) +SCPM_DISABLE = enum_psp_runtime_scpm_authentication.define('SCPM_DISABLE', 0) +SCPM_ENABLE = enum_psp_runtime_scpm_authentication.define('SCPM_ENABLE', 1) +SCPM_ENABLE_WITH_SCPM_ERR = enum_psp_runtime_scpm_authentication.define('SCPM_ENABLE_WITH_SCPM_ERR', 2) -# values for enumeration 'psp_reg_prog_id' -psp_reg_prog_id__enumvalues = { - 0: 'PSP_REG_IH_RB_CNTL', - 1: 'PSP_REG_IH_RB_CNTL_RING1', - 2: 'PSP_REG_IH_RB_CNTL_RING2', - 3: 'PSP_REG_LAST', -} -PSP_REG_IH_RB_CNTL = 0 -PSP_REG_IH_RB_CNTL_RING1 = 1 -PSP_REG_IH_RB_CNTL_RING2 = 2 -PSP_REG_LAST = 3 -psp_reg_prog_id = ctypes.c_uint32 # enum +class struct_amdgpu_device(Struct): pass +enum_amdgpu_interrupt_state = CEnum(ctypes.c_uint32) +AMDGPU_IRQ_STATE_DISABLE = enum_amdgpu_interrupt_state.define('AMDGPU_IRQ_STATE_DISABLE', 0) +AMDGPU_IRQ_STATE_ENABLE = enum_amdgpu_interrupt_state.define('AMDGPU_IRQ_STATE_ENABLE', 1) -# values for enumeration 'psp_memory_training_init_flag' -psp_memory_training_init_flag__enumvalues = { - 0: 'PSP_MEM_TRAIN_NOT_SUPPORT', - 1: 'PSP_MEM_TRAIN_SUPPORT', - 2: 'PSP_MEM_TRAIN_INIT_FAILED', - 4: 'PSP_MEM_TRAIN_RESERVE_SUCCESS', - 8: 'PSP_MEM_TRAIN_INIT_SUCCESS', -} -PSP_MEM_TRAIN_NOT_SUPPORT = 0 -PSP_MEM_TRAIN_SUPPORT = 1 -PSP_MEM_TRAIN_INIT_FAILED = 2 -PSP_MEM_TRAIN_RESERVE_SUCCESS = 4 -PSP_MEM_TRAIN_INIT_SUCCESS = 8 -psp_memory_training_init_flag = ctypes.c_uint32 # enum - -# values for enumeration 'psp_memory_training_ops' -psp_memory_training_ops__enumvalues = { - 1: 'PSP_MEM_TRAIN_SEND_LONG_MSG', - 2: 'PSP_MEM_TRAIN_SAVE', - 4: 'PSP_MEM_TRAIN_RESTORE', - 8: 'PSP_MEM_TRAIN_SEND_SHORT_MSG', - 1: 'PSP_MEM_TRAIN_COLD_BOOT', - 8: 'PSP_MEM_TRAIN_RESUME', -} -PSP_MEM_TRAIN_SEND_LONG_MSG = 1 -PSP_MEM_TRAIN_SAVE = 2 -PSP_MEM_TRAIN_RESTORE = 4 -PSP_MEM_TRAIN_SEND_SHORT_MSG = 8 -PSP_MEM_TRAIN_COLD_BOOT = 1 -PSP_MEM_TRAIN_RESUME = 8 -psp_memory_training_ops = ctypes.c_uint32 # enum - -# values for enumeration 'psp_runtime_entry_type' -psp_runtime_entry_type__enumvalues = { - 0: 'PSP_RUNTIME_ENTRY_TYPE_INVALID', - 1: 'PSP_RUNTIME_ENTRY_TYPE_TEST', - 2: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', - 3: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', - 4: 'PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', - 5: 'PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', - 6: 'PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', -} -PSP_RUNTIME_ENTRY_TYPE_INVALID = 0 -PSP_RUNTIME_ENTRY_TYPE_TEST = 1 -PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 2 -PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 3 -PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 4 -PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 5 -PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 6 -psp_runtime_entry_type = ctypes.c_uint32 # enum - -# values for enumeration 'psp_runtime_boot_cfg_feature' -psp_runtime_boot_cfg_feature__enumvalues = { - 1: 'BOOT_CFG_FEATURE_GECC', - 2: 'BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', -} -BOOT_CFG_FEATURE_GECC = 1 -BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 2 -psp_runtime_boot_cfg_feature = ctypes.c_uint32 # enum - -# values for enumeration 'psp_runtime_scpm_authentication' -psp_runtime_scpm_authentication__enumvalues = { - 0: 'SCPM_DISABLE', - 1: 'SCPM_ENABLE', - 2: 'SCPM_ENABLE_WITH_SCPM_ERR', -} -SCPM_DISABLE = 0 -SCPM_ENABLE = 1 -SCPM_ENABLE_WITH_SCPM_ERR = 2 -psp_runtime_scpm_authentication = ctypes.c_uint32 # enum -__AMDGPU_IRQ_H__ = True # macro -AMDGPU_MAX_IRQ_SRC_ID = 0x100 # macro -AMDGPU_MAX_IRQ_CLIENT_ID = 0x100 # macro -AMDGPU_IRQ_CLIENTID_LEGACY = 0 # macro -AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW = 4 # macro -class struct_amdgpu_device(Structure): - pass - - -# values for enumeration 'amdgpu_interrupt_state' -amdgpu_interrupt_state__enumvalues = { - 0: 'AMDGPU_IRQ_STATE_DISABLE', - 1: 'AMDGPU_IRQ_STATE_ENABLE', -} -AMDGPU_IRQ_STATE_DISABLE = 0 -AMDGPU_IRQ_STATE_ENABLE = 1 -amdgpu_interrupt_state = ctypes.c_uint32 # enum -class struct_amdgpu_iv_entry(Structure): - pass - -struct_amdgpu_iv_entry._pack_ = 1 # source:False +class struct_amdgpu_iv_entry(Struct): pass struct_amdgpu_iv_entry._fields_ = [ - ('client_id', ctypes.c_uint32), - ('src_id', ctypes.c_uint32), - ('ring_id', ctypes.c_uint32), - ('vmid', ctypes.c_uint32), - ('vmid_src', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timestamp', ctypes.c_uint64), - ('timestamp_src', ctypes.c_uint32), - ('pasid', ctypes.c_uint32), - ('node_id', ctypes.c_uint32), - ('src_data', ctypes.c_uint32 * 4), - ('PADDING_1', ctypes.c_ubyte * 4), - ('iv_entry', ctypes.POINTER(ctypes.c_uint32)), + ('client_id', ctypes.c_uint32), + ('src_id', ctypes.c_uint32), + ('ring_id', ctypes.c_uint32), + ('vmid', ctypes.c_uint32), + ('vmid_src', ctypes.c_uint32), + ('timestamp', ctypes.c_uint64), + ('timestamp_src', ctypes.c_uint32), + ('pasid', ctypes.c_uint32), + ('node_id', ctypes.c_uint32), + ('src_data', (ctypes.c_uint32 * 4)), + ('iv_entry', ctypes.POINTER(ctypes.c_uint32)), ] +enum_interrupt_node_id_per_aid = CEnum(ctypes.c_uint32) +AID0_NODEID = enum_interrupt_node_id_per_aid.define('AID0_NODEID', 0) +XCD0_NODEID = enum_interrupt_node_id_per_aid.define('XCD0_NODEID', 1) +XCD1_NODEID = enum_interrupt_node_id_per_aid.define('XCD1_NODEID', 2) +AID1_NODEID = enum_interrupt_node_id_per_aid.define('AID1_NODEID', 4) +XCD2_NODEID = enum_interrupt_node_id_per_aid.define('XCD2_NODEID', 5) +XCD3_NODEID = enum_interrupt_node_id_per_aid.define('XCD3_NODEID', 6) +AID2_NODEID = enum_interrupt_node_id_per_aid.define('AID2_NODEID', 8) +XCD4_NODEID = enum_interrupt_node_id_per_aid.define('XCD4_NODEID', 9) +XCD5_NODEID = enum_interrupt_node_id_per_aid.define('XCD5_NODEID', 10) +AID3_NODEID = enum_interrupt_node_id_per_aid.define('AID3_NODEID', 12) +XCD6_NODEID = enum_interrupt_node_id_per_aid.define('XCD6_NODEID', 13) +XCD7_NODEID = enum_interrupt_node_id_per_aid.define('XCD7_NODEID', 14) +NODEID_MAX = enum_interrupt_node_id_per_aid.define('NODEID_MAX', 15) +enum_AMDGPU_DOORBELL_ASSIGNMENT = CEnum(ctypes.c_uint32) +AMDGPU_DOORBELL_KIQ = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_KIQ', 0) +AMDGPU_DOORBELL_HIQ = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_HIQ', 1) +AMDGPU_DOORBELL_DIQ = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_DIQ', 2) +AMDGPU_DOORBELL_MEC_RING0 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING0', 16) +AMDGPU_DOORBELL_MEC_RING1 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING1', 17) +AMDGPU_DOORBELL_MEC_RING2 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING2', 18) +AMDGPU_DOORBELL_MEC_RING3 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING3', 19) +AMDGPU_DOORBELL_MEC_RING4 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING4', 20) +AMDGPU_DOORBELL_MEC_RING5 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING5', 21) +AMDGPU_DOORBELL_MEC_RING6 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING6', 22) +AMDGPU_DOORBELL_MEC_RING7 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MEC_RING7', 23) +AMDGPU_DOORBELL_GFX_RING0 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_GFX_RING0', 32) +AMDGPU_DOORBELL_sDMA_ENGINE0 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_sDMA_ENGINE0', 480) +AMDGPU_DOORBELL_sDMA_ENGINE1 = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_sDMA_ENGINE1', 481) +AMDGPU_DOORBELL_IH = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_IH', 488) +AMDGPU_DOORBELL_MAX_ASSIGNMENT = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_MAX_ASSIGNMENT', 1023) +AMDGPU_DOORBELL_INVALID = enum_AMDGPU_DOORBELL_ASSIGNMENT.define('AMDGPU_DOORBELL_INVALID', 65535) -# values for enumeration 'interrupt_node_id_per_aid' -interrupt_node_id_per_aid__enumvalues = { - 0: 'AID0_NODEID', - 1: 'XCD0_NODEID', - 2: 'XCD1_NODEID', - 4: 'AID1_NODEID', - 5: 'XCD2_NODEID', - 6: 'XCD3_NODEID', - 8: 'AID2_NODEID', - 9: 'XCD4_NODEID', - 10: 'XCD5_NODEID', - 12: 'AID3_NODEID', - 13: 'XCD6_NODEID', - 14: 'XCD7_NODEID', - 15: 'NODEID_MAX', -} -AID0_NODEID = 0 -XCD0_NODEID = 1 -XCD1_NODEID = 2 -AID1_NODEID = 4 -XCD2_NODEID = 5 -XCD3_NODEID = 6 -AID2_NODEID = 8 -XCD4_NODEID = 9 -XCD5_NODEID = 10 -AID3_NODEID = 12 -XCD6_NODEID = 13 -XCD7_NODEID = 14 -NODEID_MAX = 15 -interrupt_node_id_per_aid = ctypes.c_uint32 # enum -AMDGPU_DOORBELL_H = True # macro +enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT = CEnum(ctypes.c_uint32) +AMDGPU_VEGA20_DOORBELL_KIQ = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_KIQ', 0) +AMDGPU_VEGA20_DOORBELL_HIQ = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_HIQ', 1) +AMDGPU_VEGA20_DOORBELL_DIQ = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_DIQ', 2) +AMDGPU_VEGA20_DOORBELL_MEC_RING0 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING0', 3) +AMDGPU_VEGA20_DOORBELL_MEC_RING1 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING1', 4) +AMDGPU_VEGA20_DOORBELL_MEC_RING2 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING2', 5) +AMDGPU_VEGA20_DOORBELL_MEC_RING3 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING3', 6) +AMDGPU_VEGA20_DOORBELL_MEC_RING4 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING4', 7) +AMDGPU_VEGA20_DOORBELL_MEC_RING5 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING5', 8) +AMDGPU_VEGA20_DOORBELL_MEC_RING6 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING6', 9) +AMDGPU_VEGA20_DOORBELL_MEC_RING7 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MEC_RING7', 10) +AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', 11) +AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', 138) +AMDGPU_VEGA20_DOORBELL_GFX_RING0 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_GFX_RING0', 139) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', 256) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', 266) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', 276) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', 286) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', 296) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', 306) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', 316) +AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', 326) +AMDGPU_VEGA20_DOORBELL_IH = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_IH', 376) +AMDGPU_VEGA20_DOORBELL64_VCN0_1 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCN0_1', 392) +AMDGPU_VEGA20_DOORBELL64_VCN2_3 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCN2_3', 393) +AMDGPU_VEGA20_DOORBELL64_VCN4_5 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCN4_5', 394) +AMDGPU_VEGA20_DOORBELL64_VCN6_7 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCN6_7', 395) +AMDGPU_VEGA20_DOORBELL64_VCN8_9 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCN8_9', 396) +AMDGPU_VEGA20_DOORBELL64_VCNa_b = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCNa_b', 397) +AMDGPU_VEGA20_DOORBELL64_VCNc_d = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCNc_d', 398) +AMDGPU_VEGA20_DOORBELL64_VCNe_f = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCNe_f', 399) +AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', 392) +AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', 393) +AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', 394) +AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', 395) +AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', 396) +AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', 397) +AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', 398) +AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', 399) +AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', 256) +AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', 399) +AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', 400) +AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', 407) +AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', 464) +AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', 503) +AMDGPU_VEGA20_DOORBELL_INVALID = enum_AMDGPU_VEGA20_DOORBELL_ASSIGNMENT.define('AMDGPU_VEGA20_DOORBELL_INVALID', 65535) -# values for enumeration 'AMDGPU_DOORBELL_ASSIGNMENT' -AMDGPU_DOORBELL_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_DOORBELL_KIQ', - 1: 'AMDGPU_DOORBELL_HIQ', - 2: 'AMDGPU_DOORBELL_DIQ', - 16: 'AMDGPU_DOORBELL_MEC_RING0', - 17: 'AMDGPU_DOORBELL_MEC_RING1', - 18: 'AMDGPU_DOORBELL_MEC_RING2', - 19: 'AMDGPU_DOORBELL_MEC_RING3', - 20: 'AMDGPU_DOORBELL_MEC_RING4', - 21: 'AMDGPU_DOORBELL_MEC_RING5', - 22: 'AMDGPU_DOORBELL_MEC_RING6', - 23: 'AMDGPU_DOORBELL_MEC_RING7', - 32: 'AMDGPU_DOORBELL_GFX_RING0', - 480: 'AMDGPU_DOORBELL_sDMA_ENGINE0', - 481: 'AMDGPU_DOORBELL_sDMA_ENGINE1', - 488: 'AMDGPU_DOORBELL_IH', - 1023: 'AMDGPU_DOORBELL_MAX_ASSIGNMENT', - 65535: 'AMDGPU_DOORBELL_INVALID', -} -AMDGPU_DOORBELL_KIQ = 0 -AMDGPU_DOORBELL_HIQ = 1 -AMDGPU_DOORBELL_DIQ = 2 -AMDGPU_DOORBELL_MEC_RING0 = 16 -AMDGPU_DOORBELL_MEC_RING1 = 17 -AMDGPU_DOORBELL_MEC_RING2 = 18 -AMDGPU_DOORBELL_MEC_RING3 = 19 -AMDGPU_DOORBELL_MEC_RING4 = 20 -AMDGPU_DOORBELL_MEC_RING5 = 21 -AMDGPU_DOORBELL_MEC_RING6 = 22 -AMDGPU_DOORBELL_MEC_RING7 = 23 -AMDGPU_DOORBELL_GFX_RING0 = 32 -AMDGPU_DOORBELL_sDMA_ENGINE0 = 480 -AMDGPU_DOORBELL_sDMA_ENGINE1 = 481 -AMDGPU_DOORBELL_IH = 488 -AMDGPU_DOORBELL_MAX_ASSIGNMENT = 1023 -AMDGPU_DOORBELL_INVALID = 65535 -AMDGPU_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum +enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT = CEnum(ctypes.c_uint32) +AMDGPU_NAVI10_DOORBELL_KIQ = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_KIQ', 0) +AMDGPU_NAVI10_DOORBELL_HIQ = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_HIQ', 1) +AMDGPU_NAVI10_DOORBELL_DIQ = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_DIQ', 2) +AMDGPU_NAVI10_DOORBELL_MEC_RING0 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING0', 3) +AMDGPU_NAVI10_DOORBELL_MEC_RING1 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING1', 4) +AMDGPU_NAVI10_DOORBELL_MEC_RING2 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING2', 5) +AMDGPU_NAVI10_DOORBELL_MEC_RING3 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING3', 6) +AMDGPU_NAVI10_DOORBELL_MEC_RING4 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING4', 7) +AMDGPU_NAVI10_DOORBELL_MEC_RING5 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING5', 8) +AMDGPU_NAVI10_DOORBELL_MEC_RING6 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING6', 9) +AMDGPU_NAVI10_DOORBELL_MEC_RING7 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MEC_RING7', 10) +AMDGPU_NAVI10_DOORBELL_MES_RING0 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MES_RING0', 11) +AMDGPU_NAVI10_DOORBELL_MES_RING1 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MES_RING1', 12) +AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', 13) +AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', 138) +AMDGPU_NAVI10_DOORBELL_GFX_RING0 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_GFX_RING0', 139) +AMDGPU_NAVI10_DOORBELL_GFX_RING1 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_GFX_RING1', 140) +AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', 141) +AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', 255) +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', 256) +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', 266) +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', 276) +AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', 286) +AMDGPU_NAVI10_DOORBELL_IH = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_IH', 376) +AMDGPU_NAVI10_DOORBELL64_VCN0_1 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCN0_1', 392) +AMDGPU_NAVI10_DOORBELL64_VCN2_3 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCN2_3', 393) +AMDGPU_NAVI10_DOORBELL64_VCN4_5 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCN4_5', 394) +AMDGPU_NAVI10_DOORBELL64_VCN6_7 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCN6_7', 395) +AMDGPU_NAVI10_DOORBELL64_VCN8_9 = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCN8_9', 396) +AMDGPU_NAVI10_DOORBELL64_VCNa_b = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCNa_b', 397) +AMDGPU_NAVI10_DOORBELL64_VCNc_d = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCNc_d', 398) +AMDGPU_NAVI10_DOORBELL64_VCNe_f = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VCNe_f', 399) +AMDGPU_NAVI10_DOORBELL64_VPE = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_VPE', 400) +AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', 256) +AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', 400) +AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', 400) +AMDGPU_NAVI10_DOORBELL_INVALID = enum_AMDGPU_NAVI10_DOORBELL_ASSIGNMENT.define('AMDGPU_NAVI10_DOORBELL_INVALID', 65535) -# values for enumeration 'AMDGPU_VEGA20_DOORBELL_ASSIGNMENT' -AMDGPU_VEGA20_DOORBELL_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_VEGA20_DOORBELL_KIQ', - 1: 'AMDGPU_VEGA20_DOORBELL_HIQ', - 2: 'AMDGPU_VEGA20_DOORBELL_DIQ', - 3: 'AMDGPU_VEGA20_DOORBELL_MEC_RING0', - 4: 'AMDGPU_VEGA20_DOORBELL_MEC_RING1', - 5: 'AMDGPU_VEGA20_DOORBELL_MEC_RING2', - 6: 'AMDGPU_VEGA20_DOORBELL_MEC_RING3', - 7: 'AMDGPU_VEGA20_DOORBELL_MEC_RING4', - 8: 'AMDGPU_VEGA20_DOORBELL_MEC_RING5', - 9: 'AMDGPU_VEGA20_DOORBELL_MEC_RING6', - 10: 'AMDGPU_VEGA20_DOORBELL_MEC_RING7', - 11: 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', - 138: 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', - 139: 'AMDGPU_VEGA20_DOORBELL_GFX_RING0', - 256: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', - 266: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', - 276: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', - 286: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', - 296: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', - 306: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', - 316: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', - 326: 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', - 376: 'AMDGPU_VEGA20_DOORBELL_IH', - 392: 'AMDGPU_VEGA20_DOORBELL64_VCN0_1', - 393: 'AMDGPU_VEGA20_DOORBELL64_VCN2_3', - 394: 'AMDGPU_VEGA20_DOORBELL64_VCN4_5', - 395: 'AMDGPU_VEGA20_DOORBELL64_VCN6_7', - 396: 'AMDGPU_VEGA20_DOORBELL64_VCN8_9', - 397: 'AMDGPU_VEGA20_DOORBELL64_VCNa_b', - 398: 'AMDGPU_VEGA20_DOORBELL64_VCNc_d', - 399: 'AMDGPU_VEGA20_DOORBELL64_VCNe_f', - 392: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', - 393: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', - 394: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', - 395: 'AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', - 396: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', - 397: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', - 398: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', - 399: 'AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', - 256: 'AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', - 399: 'AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', - 400: 'AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', - 407: 'AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', - 464: 'AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', - 503: 'AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', - 65535: 'AMDGPU_VEGA20_DOORBELL_INVALID', -} -AMDGPU_VEGA20_DOORBELL_KIQ = 0 -AMDGPU_VEGA20_DOORBELL_HIQ = 1 -AMDGPU_VEGA20_DOORBELL_DIQ = 2 -AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 3 -AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 4 -AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 5 -AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 6 -AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 7 -AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 8 -AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 9 -AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 10 -AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 11 -AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 138 -AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 139 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 256 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 266 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 276 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 286 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 296 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 306 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 316 -AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 326 -AMDGPU_VEGA20_DOORBELL_IH = 376 -AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 392 -AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 393 -AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 394 -AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 395 -AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 396 -AMDGPU_VEGA20_DOORBELL64_VCNa_b = 397 -AMDGPU_VEGA20_DOORBELL64_VCNc_d = 398 -AMDGPU_VEGA20_DOORBELL64_VCNe_f = 399 -AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 392 -AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 393 -AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 394 -AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 395 -AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 396 -AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 397 -AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 398 -AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 399 -AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = 256 -AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = 399 -AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 400 -AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 407 -AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 464 -AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 503 -AMDGPU_VEGA20_DOORBELL_INVALID = 65535 -AMDGPU_VEGA20_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum +enum_AMDGPU_DOORBELL64_ASSIGNMENT = CEnum(ctypes.c_uint32) +AMDGPU_DOORBELL64_KIQ = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_KIQ', 0) +AMDGPU_DOORBELL64_HIQ = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_HIQ', 1) +AMDGPU_DOORBELL64_DIQ = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_DIQ', 2) +AMDGPU_DOORBELL64_MEC_RING0 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING0', 3) +AMDGPU_DOORBELL64_MEC_RING1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING1', 4) +AMDGPU_DOORBELL64_MEC_RING2 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING2', 5) +AMDGPU_DOORBELL64_MEC_RING3 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING3', 6) +AMDGPU_DOORBELL64_MEC_RING4 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING4', 7) +AMDGPU_DOORBELL64_MEC_RING5 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING5', 8) +AMDGPU_DOORBELL64_MEC_RING6 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING6', 9) +AMDGPU_DOORBELL64_MEC_RING7 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MEC_RING7', 10) +AMDGPU_DOORBELL64_USERQUEUE_START = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_USERQUEUE_START', 11) +AMDGPU_DOORBELL64_USERQUEUE_END = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_USERQUEUE_END', 138) +AMDGPU_DOORBELL64_GFX_RING0 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_GFX_RING0', 139) +AMDGPU_DOORBELL64_sDMA_ENGINE0 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_sDMA_ENGINE0', 240) +AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', 241) +AMDGPU_DOORBELL64_sDMA_ENGINE1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_sDMA_ENGINE1', 242) +AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', 243) +AMDGPU_DOORBELL64_IH = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_IH', 244) +AMDGPU_DOORBELL64_IH_RING1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_IH_RING1', 245) +AMDGPU_DOORBELL64_IH_RING2 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_IH_RING2', 246) +AMDGPU_DOORBELL64_VCN0_1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCN0_1', 248) +AMDGPU_DOORBELL64_VCN2_3 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCN2_3', 249) +AMDGPU_DOORBELL64_VCN4_5 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCN4_5', 250) +AMDGPU_DOORBELL64_VCN6_7 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCN6_7', 251) +AMDGPU_DOORBELL64_UVD_RING0_1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_UVD_RING0_1', 248) +AMDGPU_DOORBELL64_UVD_RING2_3 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_UVD_RING2_3', 249) +AMDGPU_DOORBELL64_UVD_RING4_5 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_UVD_RING4_5', 250) +AMDGPU_DOORBELL64_UVD_RING6_7 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_UVD_RING6_7', 251) +AMDGPU_DOORBELL64_VCE_RING0_1 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCE_RING0_1', 252) +AMDGPU_DOORBELL64_VCE_RING2_3 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCE_RING2_3', 253) +AMDGPU_DOORBELL64_VCE_RING4_5 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCE_RING4_5', 254) +AMDGPU_DOORBELL64_VCE_RING6_7 = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_VCE_RING6_7', 255) +AMDGPU_DOORBELL64_FIRST_NON_CP = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_FIRST_NON_CP', 240) +AMDGPU_DOORBELL64_LAST_NON_CP = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_LAST_NON_CP', 255) +AMDGPU_DOORBELL64_MAX_ASSIGNMENT = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_MAX_ASSIGNMENT', 255) +AMDGPU_DOORBELL64_INVALID = enum_AMDGPU_DOORBELL64_ASSIGNMENT.define('AMDGPU_DOORBELL64_INVALID', 65535) -# values for enumeration 'AMDGPU_NAVI10_DOORBELL_ASSIGNMENT' -AMDGPU_NAVI10_DOORBELL_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_NAVI10_DOORBELL_KIQ', - 1: 'AMDGPU_NAVI10_DOORBELL_HIQ', - 2: 'AMDGPU_NAVI10_DOORBELL_DIQ', - 3: 'AMDGPU_NAVI10_DOORBELL_MEC_RING0', - 4: 'AMDGPU_NAVI10_DOORBELL_MEC_RING1', - 5: 'AMDGPU_NAVI10_DOORBELL_MEC_RING2', - 6: 'AMDGPU_NAVI10_DOORBELL_MEC_RING3', - 7: 'AMDGPU_NAVI10_DOORBELL_MEC_RING4', - 8: 'AMDGPU_NAVI10_DOORBELL_MEC_RING5', - 9: 'AMDGPU_NAVI10_DOORBELL_MEC_RING6', - 10: 'AMDGPU_NAVI10_DOORBELL_MEC_RING7', - 11: 'AMDGPU_NAVI10_DOORBELL_MES_RING0', - 12: 'AMDGPU_NAVI10_DOORBELL_MES_RING1', - 13: 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', - 138: 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', - 139: 'AMDGPU_NAVI10_DOORBELL_GFX_RING0', - 140: 'AMDGPU_NAVI10_DOORBELL_GFX_RING1', - 141: 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', - 255: 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', - 256: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', - 266: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', - 276: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', - 286: 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', - 376: 'AMDGPU_NAVI10_DOORBELL_IH', - 392: 'AMDGPU_NAVI10_DOORBELL64_VCN0_1', - 393: 'AMDGPU_NAVI10_DOORBELL64_VCN2_3', - 394: 'AMDGPU_NAVI10_DOORBELL64_VCN4_5', - 395: 'AMDGPU_NAVI10_DOORBELL64_VCN6_7', - 396: 'AMDGPU_NAVI10_DOORBELL64_VCN8_9', - 397: 'AMDGPU_NAVI10_DOORBELL64_VCNa_b', - 398: 'AMDGPU_NAVI10_DOORBELL64_VCNc_d', - 399: 'AMDGPU_NAVI10_DOORBELL64_VCNe_f', - 400: 'AMDGPU_NAVI10_DOORBELL64_VPE', - 256: 'AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', - 400: 'AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', - 400: 'AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', - 65535: 'AMDGPU_NAVI10_DOORBELL_INVALID', -} -AMDGPU_NAVI10_DOORBELL_KIQ = 0 -AMDGPU_NAVI10_DOORBELL_HIQ = 1 -AMDGPU_NAVI10_DOORBELL_DIQ = 2 -AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 3 -AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 4 -AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 5 -AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 6 -AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 7 -AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 8 -AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 9 -AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 10 -AMDGPU_NAVI10_DOORBELL_MES_RING0 = 11 -AMDGPU_NAVI10_DOORBELL_MES_RING1 = 12 -AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 13 -AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 138 -AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 139 -AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 140 -AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 141 -AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 255 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 256 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 266 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 276 -AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 286 -AMDGPU_NAVI10_DOORBELL_IH = 376 -AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 392 -AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 393 -AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 394 -AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 395 -AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 396 -AMDGPU_NAVI10_DOORBELL64_VCNa_b = 397 -AMDGPU_NAVI10_DOORBELL64_VCNc_d = 398 -AMDGPU_NAVI10_DOORBELL64_VCNe_f = 399 -AMDGPU_NAVI10_DOORBELL64_VPE = 400 -AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = 256 -AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = 400 -AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 400 -AMDGPU_NAVI10_DOORBELL_INVALID = 65535 -AMDGPU_NAVI10_DOORBELL_ASSIGNMENT = ctypes.c_uint32 # enum +enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 = CEnum(ctypes.c_uint32) +AMDGPU_DOORBELL_LAYOUT1_KIQ_START = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_KIQ_START', 0) +AMDGPU_DOORBELL_LAYOUT1_HIQ = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_HIQ', 1) +AMDGPU_DOORBELL_LAYOUT1_DIQ = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_DIQ', 2) +AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', 8) +AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', 15) +AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', 16) +AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', 31) +AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', 32) +AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', 256) +AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', 415) +AMDGPU_DOORBELL_LAYOUT1_IH = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_IH', 416) +AMDGPU_DOORBELL_LAYOUT1_VCN_START = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_VCN_START', 432) +AMDGPU_DOORBELL_LAYOUT1_VCN_END = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_VCN_END', 488) +AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', 256) +AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', 488) +AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', 488) +AMDGPU_DOORBELL_LAYOUT1_INVALID = enum_AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1.define('AMDGPU_DOORBELL_LAYOUT1_INVALID', 65535) -# values for enumeration 'AMDGPU_DOORBELL64_ASSIGNMENT' -AMDGPU_DOORBELL64_ASSIGNMENT__enumvalues = { - 0: 'AMDGPU_DOORBELL64_KIQ', - 1: 'AMDGPU_DOORBELL64_HIQ', - 2: 'AMDGPU_DOORBELL64_DIQ', - 3: 'AMDGPU_DOORBELL64_MEC_RING0', - 4: 'AMDGPU_DOORBELL64_MEC_RING1', - 5: 'AMDGPU_DOORBELL64_MEC_RING2', - 6: 'AMDGPU_DOORBELL64_MEC_RING3', - 7: 'AMDGPU_DOORBELL64_MEC_RING4', - 8: 'AMDGPU_DOORBELL64_MEC_RING5', - 9: 'AMDGPU_DOORBELL64_MEC_RING6', - 10: 'AMDGPU_DOORBELL64_MEC_RING7', - 11: 'AMDGPU_DOORBELL64_USERQUEUE_START', - 138: 'AMDGPU_DOORBELL64_USERQUEUE_END', - 139: 'AMDGPU_DOORBELL64_GFX_RING0', - 240: 'AMDGPU_DOORBELL64_sDMA_ENGINE0', - 241: 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', - 242: 'AMDGPU_DOORBELL64_sDMA_ENGINE1', - 243: 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', - 244: 'AMDGPU_DOORBELL64_IH', - 245: 'AMDGPU_DOORBELL64_IH_RING1', - 246: 'AMDGPU_DOORBELL64_IH_RING2', - 248: 'AMDGPU_DOORBELL64_VCN0_1', - 249: 'AMDGPU_DOORBELL64_VCN2_3', - 250: 'AMDGPU_DOORBELL64_VCN4_5', - 251: 'AMDGPU_DOORBELL64_VCN6_7', - 248: 'AMDGPU_DOORBELL64_UVD_RING0_1', - 249: 'AMDGPU_DOORBELL64_UVD_RING2_3', - 250: 'AMDGPU_DOORBELL64_UVD_RING4_5', - 251: 'AMDGPU_DOORBELL64_UVD_RING6_7', - 252: 'AMDGPU_DOORBELL64_VCE_RING0_1', - 253: 'AMDGPU_DOORBELL64_VCE_RING2_3', - 254: 'AMDGPU_DOORBELL64_VCE_RING4_5', - 255: 'AMDGPU_DOORBELL64_VCE_RING6_7', - 240: 'AMDGPU_DOORBELL64_FIRST_NON_CP', - 255: 'AMDGPU_DOORBELL64_LAST_NON_CP', - 255: 'AMDGPU_DOORBELL64_MAX_ASSIGNMENT', - 65535: 'AMDGPU_DOORBELL64_INVALID', -} -AMDGPU_DOORBELL64_KIQ = 0 -AMDGPU_DOORBELL64_HIQ = 1 -AMDGPU_DOORBELL64_DIQ = 2 -AMDGPU_DOORBELL64_MEC_RING0 = 3 -AMDGPU_DOORBELL64_MEC_RING1 = 4 -AMDGPU_DOORBELL64_MEC_RING2 = 5 -AMDGPU_DOORBELL64_MEC_RING3 = 6 -AMDGPU_DOORBELL64_MEC_RING4 = 7 -AMDGPU_DOORBELL64_MEC_RING5 = 8 -AMDGPU_DOORBELL64_MEC_RING6 = 9 -AMDGPU_DOORBELL64_MEC_RING7 = 10 -AMDGPU_DOORBELL64_USERQUEUE_START = 11 -AMDGPU_DOORBELL64_USERQUEUE_END = 138 -AMDGPU_DOORBELL64_GFX_RING0 = 139 -AMDGPU_DOORBELL64_sDMA_ENGINE0 = 240 -AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 241 -AMDGPU_DOORBELL64_sDMA_ENGINE1 = 242 -AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 243 -AMDGPU_DOORBELL64_IH = 244 -AMDGPU_DOORBELL64_IH_RING1 = 245 -AMDGPU_DOORBELL64_IH_RING2 = 246 -AMDGPU_DOORBELL64_VCN0_1 = 248 -AMDGPU_DOORBELL64_VCN2_3 = 249 -AMDGPU_DOORBELL64_VCN4_5 = 250 -AMDGPU_DOORBELL64_VCN6_7 = 251 -AMDGPU_DOORBELL64_UVD_RING0_1 = 248 -AMDGPU_DOORBELL64_UVD_RING2_3 = 249 -AMDGPU_DOORBELL64_UVD_RING4_5 = 250 -AMDGPU_DOORBELL64_UVD_RING6_7 = 251 -AMDGPU_DOORBELL64_VCE_RING0_1 = 252 -AMDGPU_DOORBELL64_VCE_RING2_3 = 253 -AMDGPU_DOORBELL64_VCE_RING4_5 = 254 -AMDGPU_DOORBELL64_VCE_RING6_7 = 255 -AMDGPU_DOORBELL64_FIRST_NON_CP = 240 -AMDGPU_DOORBELL64_LAST_NON_CP = 255 -AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 255 -AMDGPU_DOORBELL64_INVALID = 65535 -AMDGPU_DOORBELL64_ASSIGNMENT = ctypes.c_uint32 # enum +enum_soc15_ih_clientid = CEnum(ctypes.c_uint32) +SOC15_IH_CLIENTID_IH = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_IH', 0) +SOC15_IH_CLIENTID_ACP = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_ACP', 1) +SOC15_IH_CLIENTID_ATHUB = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_ATHUB', 2) +SOC15_IH_CLIENTID_BIF = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_BIF', 3) +SOC15_IH_CLIENTID_DCE = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_DCE', 4) +SOC15_IH_CLIENTID_ISP = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_ISP', 5) +SOC15_IH_CLIENTID_PCIE0 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_PCIE0', 6) +SOC15_IH_CLIENTID_RLC = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_RLC', 7) +SOC15_IH_CLIENTID_SDMA0 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA0', 8) +SOC15_IH_CLIENTID_SDMA1 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA1', 9) +SOC15_IH_CLIENTID_SE0SH = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SE0SH', 10) +SOC15_IH_CLIENTID_SE1SH = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SE1SH', 11) +SOC15_IH_CLIENTID_SE2SH = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SE2SH', 12) +SOC15_IH_CLIENTID_SE3SH = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SE3SH', 13) +SOC15_IH_CLIENTID_UVD1 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_UVD1', 14) +SOC15_IH_CLIENTID_THM = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_THM', 15) +SOC15_IH_CLIENTID_UVD = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_UVD', 16) +SOC15_IH_CLIENTID_VCE0 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_VCE0', 17) +SOC15_IH_CLIENTID_VMC = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_VMC', 18) +SOC15_IH_CLIENTID_XDMA = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_XDMA', 19) +SOC15_IH_CLIENTID_GRBM_CP = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_GRBM_CP', 20) +SOC15_IH_CLIENTID_ATS = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_ATS', 21) +SOC15_IH_CLIENTID_ROM_SMUIO = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_ROM_SMUIO', 22) +SOC15_IH_CLIENTID_DF = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_DF', 23) +SOC15_IH_CLIENTID_VCE1 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_VCE1', 24) +SOC15_IH_CLIENTID_PWR = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_PWR', 25) +SOC15_IH_CLIENTID_RESERVED = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_RESERVED', 26) +SOC15_IH_CLIENTID_UTCL2 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_UTCL2', 27) +SOC15_IH_CLIENTID_EA = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_EA', 28) +SOC15_IH_CLIENTID_UTCL2LOG = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_UTCL2LOG', 29) +SOC15_IH_CLIENTID_MP0 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_MP0', 30) +SOC15_IH_CLIENTID_MP1 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_MP1', 31) +SOC15_IH_CLIENTID_MAX = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_MAX', 32) +SOC15_IH_CLIENTID_VCN = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_VCN', 16) +SOC15_IH_CLIENTID_VCN1 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_VCN1', 14) +SOC15_IH_CLIENTID_SDMA2 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA2', 1) +SOC15_IH_CLIENTID_SDMA3 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA3', 4) +SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', 5) +SOC15_IH_CLIENTID_SDMA4 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA4', 5) +SOC15_IH_CLIENTID_SDMA5 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA5', 17) +SOC15_IH_CLIENTID_SDMA6 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA6', 19) +SOC15_IH_CLIENTID_SDMA7 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_SDMA7', 24) +SOC15_IH_CLIENTID_VMC1 = enum_soc15_ih_clientid.define('SOC15_IH_CLIENTID_VMC1', 6) -# values for enumeration 'AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1' -AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1__enumvalues = { - 0: 'AMDGPU_DOORBELL_LAYOUT1_KIQ_START', - 1: 'AMDGPU_DOORBELL_LAYOUT1_HIQ', - 2: 'AMDGPU_DOORBELL_LAYOUT1_DIQ', - 8: 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', - 15: 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', - 16: 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', - 31: 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', - 32: 'AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', - 256: 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', - 415: 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', - 416: 'AMDGPU_DOORBELL_LAYOUT1_IH', - 432: 'AMDGPU_DOORBELL_LAYOUT1_VCN_START', - 488: 'AMDGPU_DOORBELL_LAYOUT1_VCN_END', - 256: 'AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', - 488: 'AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', - 488: 'AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', - 65535: 'AMDGPU_DOORBELL_LAYOUT1_INVALID', -} -AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0 -AMDGPU_DOORBELL_LAYOUT1_HIQ = 1 -AMDGPU_DOORBELL_LAYOUT1_DIQ = 2 -AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 8 -AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 15 -AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 16 -AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 31 -AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 32 -AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 256 -AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 415 -AMDGPU_DOORBELL_LAYOUT1_IH = 416 -AMDGPU_DOORBELL_LAYOUT1_VCN_START = 432 -AMDGPU_DOORBELL_LAYOUT1_VCN_END = 488 -AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = 256 -AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = 488 -AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 488 -AMDGPU_DOORBELL_LAYOUT1_INVALID = 65535 -AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 = ctypes.c_uint32 # enum -__SOC15_IH_CLIENTID_H__ = True # macro +enum_soc21_ih_clientid = CEnum(ctypes.c_uint32) +SOC21_IH_CLIENTID_IH = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_IH', 0) +SOC21_IH_CLIENTID_ATHUB = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_ATHUB', 2) +SOC21_IH_CLIENTID_BIF = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_BIF', 3) +SOC21_IH_CLIENTID_DCN = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_DCN', 4) +SOC21_IH_CLIENTID_ISP = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_ISP', 5) +SOC21_IH_CLIENTID_MP3 = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_MP3', 6) +SOC21_IH_CLIENTID_RLC = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_RLC', 7) +SOC21_IH_CLIENTID_GFX = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_GFX', 10) +SOC21_IH_CLIENTID_IMU = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_IMU', 11) +SOC21_IH_CLIENTID_VCN1 = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_VCN1', 14) +SOC21_IH_CLIENTID_THM = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_THM', 15) +SOC21_IH_CLIENTID_VCN = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_VCN', 16) +SOC21_IH_CLIENTID_VPE1 = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_VPE1', 17) +SOC21_IH_CLIENTID_VMC = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_VMC', 18) +SOC21_IH_CLIENTID_GRBM_CP = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_GRBM_CP', 20) +SOC21_IH_CLIENTID_ROM_SMUIO = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_ROM_SMUIO', 22) +SOC21_IH_CLIENTID_DF = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_DF', 23) +SOC21_IH_CLIENTID_VPE = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_VPE', 24) +SOC21_IH_CLIENTID_PWR = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_PWR', 25) +SOC21_IH_CLIENTID_LSDMA = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_LSDMA', 26) +SOC21_IH_CLIENTID_MP0 = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_MP0', 30) +SOC21_IH_CLIENTID_MP1 = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_MP1', 31) +SOC21_IH_CLIENTID_MAX = enum_soc21_ih_clientid.define('SOC21_IH_CLIENTID_MAX', 32) -# values for enumeration 'soc15_ih_clientid' -soc15_ih_clientid__enumvalues = { - 0: 'SOC15_IH_CLIENTID_IH', - 1: 'SOC15_IH_CLIENTID_ACP', - 2: 'SOC15_IH_CLIENTID_ATHUB', - 3: 'SOC15_IH_CLIENTID_BIF', - 4: 'SOC15_IH_CLIENTID_DCE', - 5: 'SOC15_IH_CLIENTID_ISP', - 6: 'SOC15_IH_CLIENTID_PCIE0', - 7: 'SOC15_IH_CLIENTID_RLC', - 8: 'SOC15_IH_CLIENTID_SDMA0', - 9: 'SOC15_IH_CLIENTID_SDMA1', - 10: 'SOC15_IH_CLIENTID_SE0SH', - 11: 'SOC15_IH_CLIENTID_SE1SH', - 12: 'SOC15_IH_CLIENTID_SE2SH', - 13: 'SOC15_IH_CLIENTID_SE3SH', - 14: 'SOC15_IH_CLIENTID_UVD1', - 15: 'SOC15_IH_CLIENTID_THM', - 16: 'SOC15_IH_CLIENTID_UVD', - 17: 'SOC15_IH_CLIENTID_VCE0', - 18: 'SOC15_IH_CLIENTID_VMC', - 19: 'SOC15_IH_CLIENTID_XDMA', - 20: 'SOC15_IH_CLIENTID_GRBM_CP', - 21: 'SOC15_IH_CLIENTID_ATS', - 22: 'SOC15_IH_CLIENTID_ROM_SMUIO', - 23: 'SOC15_IH_CLIENTID_DF', - 24: 'SOC15_IH_CLIENTID_VCE1', - 25: 'SOC15_IH_CLIENTID_PWR', - 26: 'SOC15_IH_CLIENTID_RESERVED', - 27: 'SOC15_IH_CLIENTID_UTCL2', - 28: 'SOC15_IH_CLIENTID_EA', - 29: 'SOC15_IH_CLIENTID_UTCL2LOG', - 30: 'SOC15_IH_CLIENTID_MP0', - 31: 'SOC15_IH_CLIENTID_MP1', - 32: 'SOC15_IH_CLIENTID_MAX', - 16: 'SOC15_IH_CLIENTID_VCN', - 14: 'SOC15_IH_CLIENTID_VCN1', - 1: 'SOC15_IH_CLIENTID_SDMA2', - 4: 'SOC15_IH_CLIENTID_SDMA3', - 5: 'SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', - 5: 'SOC15_IH_CLIENTID_SDMA4', - 17: 'SOC15_IH_CLIENTID_SDMA5', - 19: 'SOC15_IH_CLIENTID_SDMA6', - 24: 'SOC15_IH_CLIENTID_SDMA7', - 6: 'SOC15_IH_CLIENTID_VMC1', -} -SOC15_IH_CLIENTID_IH = 0 -SOC15_IH_CLIENTID_ACP = 1 -SOC15_IH_CLIENTID_ATHUB = 2 -SOC15_IH_CLIENTID_BIF = 3 -SOC15_IH_CLIENTID_DCE = 4 -SOC15_IH_CLIENTID_ISP = 5 -SOC15_IH_CLIENTID_PCIE0 = 6 -SOC15_IH_CLIENTID_RLC = 7 -SOC15_IH_CLIENTID_SDMA0 = 8 -SOC15_IH_CLIENTID_SDMA1 = 9 -SOC15_IH_CLIENTID_SE0SH = 10 -SOC15_IH_CLIENTID_SE1SH = 11 -SOC15_IH_CLIENTID_SE2SH = 12 -SOC15_IH_CLIENTID_SE3SH = 13 -SOC15_IH_CLIENTID_UVD1 = 14 -SOC15_IH_CLIENTID_THM = 15 -SOC15_IH_CLIENTID_UVD = 16 -SOC15_IH_CLIENTID_VCE0 = 17 -SOC15_IH_CLIENTID_VMC = 18 -SOC15_IH_CLIENTID_XDMA = 19 -SOC15_IH_CLIENTID_GRBM_CP = 20 -SOC15_IH_CLIENTID_ATS = 21 -SOC15_IH_CLIENTID_ROM_SMUIO = 22 -SOC15_IH_CLIENTID_DF = 23 -SOC15_IH_CLIENTID_VCE1 = 24 -SOC15_IH_CLIENTID_PWR = 25 -SOC15_IH_CLIENTID_RESERVED = 26 -SOC15_IH_CLIENTID_UTCL2 = 27 -SOC15_IH_CLIENTID_EA = 28 -SOC15_IH_CLIENTID_UTCL2LOG = 29 -SOC15_IH_CLIENTID_MP0 = 30 -SOC15_IH_CLIENTID_MP1 = 31 -SOC15_IH_CLIENTID_MAX = 32 -SOC15_IH_CLIENTID_VCN = 16 -SOC15_IH_CLIENTID_VCN1 = 14 -SOC15_IH_CLIENTID_SDMA2 = 1 -SOC15_IH_CLIENTID_SDMA3 = 4 -SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = 5 -SOC15_IH_CLIENTID_SDMA4 = 5 -SOC15_IH_CLIENTID_SDMA5 = 17 -SOC15_IH_CLIENTID_SDMA6 = 19 -SOC15_IH_CLIENTID_SDMA7 = 24 -SOC15_IH_CLIENTID_VMC1 = 6 -soc15_ih_clientid = ctypes.c_uint32 # enum -AMDGPU_IRQ_CLIENTID_MAX = SOC15_IH_CLIENTID_MAX # macro -soc15_ih_clientid_name = [] # Variable ctypes.POINTER(ctypes.c_char) * 0 - -# values for enumeration 'soc21_ih_clientid' -soc21_ih_clientid__enumvalues = { - 0: 'SOC21_IH_CLIENTID_IH', - 2: 'SOC21_IH_CLIENTID_ATHUB', - 3: 'SOC21_IH_CLIENTID_BIF', - 4: 'SOC21_IH_CLIENTID_DCN', - 5: 'SOC21_IH_CLIENTID_ISP', - 6: 'SOC21_IH_CLIENTID_MP3', - 7: 'SOC21_IH_CLIENTID_RLC', - 10: 'SOC21_IH_CLIENTID_GFX', - 11: 'SOC21_IH_CLIENTID_IMU', - 14: 'SOC21_IH_CLIENTID_VCN1', - 15: 'SOC21_IH_CLIENTID_THM', - 16: 'SOC21_IH_CLIENTID_VCN', - 17: 'SOC21_IH_CLIENTID_VPE1', - 18: 'SOC21_IH_CLIENTID_VMC', - 20: 'SOC21_IH_CLIENTID_GRBM_CP', - 22: 'SOC21_IH_CLIENTID_ROM_SMUIO', - 23: 'SOC21_IH_CLIENTID_DF', - 24: 'SOC21_IH_CLIENTID_VPE', - 25: 'SOC21_IH_CLIENTID_PWR', - 26: 'SOC21_IH_CLIENTID_LSDMA', - 30: 'SOC21_IH_CLIENTID_MP0', - 31: 'SOC21_IH_CLIENTID_MP1', - 32: 'SOC21_IH_CLIENTID_MAX', -} -SOC21_IH_CLIENTID_IH = 0 -SOC21_IH_CLIENTID_ATHUB = 2 -SOC21_IH_CLIENTID_BIF = 3 -SOC21_IH_CLIENTID_DCN = 4 -SOC21_IH_CLIENTID_ISP = 5 -SOC21_IH_CLIENTID_MP3 = 6 -SOC21_IH_CLIENTID_RLC = 7 -SOC21_IH_CLIENTID_GFX = 10 -SOC21_IH_CLIENTID_IMU = 11 -SOC21_IH_CLIENTID_VCN1 = 14 -SOC21_IH_CLIENTID_THM = 15 -SOC21_IH_CLIENTID_VCN = 16 -SOC21_IH_CLIENTID_VPE1 = 17 -SOC21_IH_CLIENTID_VMC = 18 -SOC21_IH_CLIENTID_GRBM_CP = 20 -SOC21_IH_CLIENTID_ROM_SMUIO = 22 -SOC21_IH_CLIENTID_DF = 23 -SOC21_IH_CLIENTID_VPE = 24 -SOC21_IH_CLIENTID_PWR = 25 -SOC21_IH_CLIENTID_LSDMA = 26 -SOC21_IH_CLIENTID_MP0 = 30 -SOC21_IH_CLIENTID_MP1 = 31 -SOC21_IH_CLIENTID_MAX = 32 -soc21_ih_clientid = ctypes.c_uint32 # enum -__all__ = \ - ['ACP_HWID', 'AID0_NODEID', 'AID1_NODEID', 'AID2_NODEID', - 'AID3_NODEID', 'AMDGPU_CPCE_UCODE_LOADED', - 'AMDGPU_CPMEC1_UCODE_LOADED', 'AMDGPU_CPMEC2_UCODE_LOADED', - 'AMDGPU_CPME_UCODE_LOADED', 'AMDGPU_CPPFP_UCODE_LOADED', - 'AMDGPU_CPRLC_UCODE_LOADED', 'AMDGPU_DOORBELL64_ASSIGNMENT', - 'AMDGPU_DOORBELL64_DIQ', 'AMDGPU_DOORBELL64_FIRST_NON_CP', - 'AMDGPU_DOORBELL64_GFX_RING0', 'AMDGPU_DOORBELL64_HIQ', - 'AMDGPU_DOORBELL64_IH', 'AMDGPU_DOORBELL64_IH_RING1', - 'AMDGPU_DOORBELL64_IH_RING2', 'AMDGPU_DOORBELL64_INVALID', - 'AMDGPU_DOORBELL64_KIQ', 'AMDGPU_DOORBELL64_LAST_NON_CP', - 'AMDGPU_DOORBELL64_MAX_ASSIGNMENT', 'AMDGPU_DOORBELL64_MEC_RING0', - 'AMDGPU_DOORBELL64_MEC_RING1', 'AMDGPU_DOORBELL64_MEC_RING2', - 'AMDGPU_DOORBELL64_MEC_RING3', 'AMDGPU_DOORBELL64_MEC_RING4', - 'AMDGPU_DOORBELL64_MEC_RING5', 'AMDGPU_DOORBELL64_MEC_RING6', - 'AMDGPU_DOORBELL64_MEC_RING7', 'AMDGPU_DOORBELL64_USERQUEUE_END', - 'AMDGPU_DOORBELL64_USERQUEUE_START', - 'AMDGPU_DOORBELL64_UVD_RING0_1', 'AMDGPU_DOORBELL64_UVD_RING2_3', - 'AMDGPU_DOORBELL64_UVD_RING4_5', 'AMDGPU_DOORBELL64_UVD_RING6_7', - 'AMDGPU_DOORBELL64_VCE_RING0_1', 'AMDGPU_DOORBELL64_VCE_RING2_3', - 'AMDGPU_DOORBELL64_VCE_RING4_5', 'AMDGPU_DOORBELL64_VCE_RING6_7', - 'AMDGPU_DOORBELL64_VCN0_1', 'AMDGPU_DOORBELL64_VCN2_3', - 'AMDGPU_DOORBELL64_VCN4_5', 'AMDGPU_DOORBELL64_VCN6_7', - 'AMDGPU_DOORBELL64_sDMA_ENGINE0', - 'AMDGPU_DOORBELL64_sDMA_ENGINE1', - 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0', - 'AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1', - 'AMDGPU_DOORBELL_ASSIGNMENT', - 'AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1', 'AMDGPU_DOORBELL_DIQ', - 'AMDGPU_DOORBELL_GFX_RING0', 'AMDGPU_DOORBELL_H', - 'AMDGPU_DOORBELL_HIQ', 'AMDGPU_DOORBELL_IH', - 'AMDGPU_DOORBELL_INVALID', 'AMDGPU_DOORBELL_KIQ', - 'AMDGPU_DOORBELL_LAYOUT1_DIQ', - 'AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP', - 'AMDGPU_DOORBELL_LAYOUT1_HIQ', 'AMDGPU_DOORBELL_LAYOUT1_IH', - 'AMDGPU_DOORBELL_LAYOUT1_INVALID', - 'AMDGPU_DOORBELL_LAYOUT1_KIQ_START', - 'AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP', - 'AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT', - 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END', - 'AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START', - 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END', - 'AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START', - 'AMDGPU_DOORBELL_LAYOUT1_VCN_END', - 'AMDGPU_DOORBELL_LAYOUT1_VCN_START', - 'AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE', - 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END', - 'AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START', - 'AMDGPU_DOORBELL_MAX_ASSIGNMENT', 'AMDGPU_DOORBELL_MEC_RING0', - 'AMDGPU_DOORBELL_MEC_RING1', 'AMDGPU_DOORBELL_MEC_RING2', - 'AMDGPU_DOORBELL_MEC_RING3', 'AMDGPU_DOORBELL_MEC_RING4', - 'AMDGPU_DOORBELL_MEC_RING5', 'AMDGPU_DOORBELL_MEC_RING6', - 'AMDGPU_DOORBELL_MEC_RING7', 'AMDGPU_DOORBELL_sDMA_ENGINE0', - 'AMDGPU_DOORBELL_sDMA_ENGINE1', 'AMDGPU_FW_LOAD_DIRECT', - 'AMDGPU_FW_LOAD_PSP', 'AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO', - 'AMDGPU_FW_LOAD_SMU', 'AMDGPU_GFXHUB_START', - 'AMDGPU_IRQ_CLIENTID_LEGACY', 'AMDGPU_IRQ_CLIENTID_MAX', - 'AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW', 'AMDGPU_IRQ_STATE_DISABLE', - 'AMDGPU_IRQ_STATE_ENABLE', 'AMDGPU_MAX_IRQ_CLIENT_ID', - 'AMDGPU_MAX_IRQ_SRC_ID', 'AMDGPU_MAX_VMHUBS', - 'AMDGPU_MMHUB0_START', 'AMDGPU_MMHUB1_START', 'AMDGPU_MTYPE_CC', - 'AMDGPU_MTYPE_NC', 'AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP', - 'AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP', - 'AMDGPU_NAVI10_DOORBELL64_VCN0_1', - 'AMDGPU_NAVI10_DOORBELL64_VCN2_3', - 'AMDGPU_NAVI10_DOORBELL64_VCN4_5', - 'AMDGPU_NAVI10_DOORBELL64_VCN6_7', - 'AMDGPU_NAVI10_DOORBELL64_VCN8_9', - 'AMDGPU_NAVI10_DOORBELL64_VCNa_b', - 'AMDGPU_NAVI10_DOORBELL64_VCNc_d', - 'AMDGPU_NAVI10_DOORBELL64_VCNe_f', 'AMDGPU_NAVI10_DOORBELL64_VPE', - 'AMDGPU_NAVI10_DOORBELL_ASSIGNMENT', 'AMDGPU_NAVI10_DOORBELL_DIQ', - 'AMDGPU_NAVI10_DOORBELL_GFX_RING0', - 'AMDGPU_NAVI10_DOORBELL_GFX_RING1', - 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END', - 'AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START', - 'AMDGPU_NAVI10_DOORBELL_HIQ', 'AMDGPU_NAVI10_DOORBELL_IH', - 'AMDGPU_NAVI10_DOORBELL_INVALID', 'AMDGPU_NAVI10_DOORBELL_KIQ', - 'AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING0', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING1', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING2', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING3', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING4', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING5', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING6', - 'AMDGPU_NAVI10_DOORBELL_MEC_RING7', - 'AMDGPU_NAVI10_DOORBELL_MES_RING0', - 'AMDGPU_NAVI10_DOORBELL_MES_RING1', - 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_END', - 'AMDGPU_NAVI10_DOORBELL_USERQUEUE_START', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2', - 'AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3', 'AMDGPU_PDE_PTE', - 'AMDGPU_PDE_PTE_GFX12', 'AMDGPU_PTE_DEFAULT_ATC', - 'AMDGPU_PTE_EXECUTABLE', 'AMDGPU_PTE_IS_PTE', 'AMDGPU_PTE_LOG', - 'AMDGPU_PTE_MTYPE_GFX12_MASK', 'AMDGPU_PTE_MTYPE_NV10_MASK', - 'AMDGPU_PTE_MTYPE_VG10_MASK', 'AMDGPU_PTE_NOALLOC', - 'AMDGPU_PTE_PRT', 'AMDGPU_PTE_PRT_GFX12', 'AMDGPU_PTE_READABLE', - 'AMDGPU_PTE_SNOOPED', 'AMDGPU_PTE_SYSTEM', 'AMDGPU_PTE_TF', - 'AMDGPU_PTE_TMZ', 'AMDGPU_PTE_VALID', 'AMDGPU_PTE_WRITEABLE', - 'AMDGPU_SDMA0_UCODE_LOADED', 'AMDGPU_SDMA1_UCODE_LOADED', - 'AMDGPU_UCODE_ID', 'AMDGPU_UCODE_ID_CAP', 'AMDGPU_UCODE_ID_CP_CE', - 'AMDGPU_UCODE_ID_CP_ME', 'AMDGPU_UCODE_ID_CP_MEC1', - 'AMDGPU_UCODE_ID_CP_MEC1_JT', 'AMDGPU_UCODE_ID_CP_MEC2', - 'AMDGPU_UCODE_ID_CP_MEC2_JT', 'AMDGPU_UCODE_ID_CP_MES', - 'AMDGPU_UCODE_ID_CP_MES1', 'AMDGPU_UCODE_ID_CP_MES1_DATA', - 'AMDGPU_UCODE_ID_CP_MES_DATA', 'AMDGPU_UCODE_ID_CP_PFP', - 'AMDGPU_UCODE_ID_CP_RS64_ME', 'AMDGPU_UCODE_ID_CP_RS64_MEC', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_PFP', - 'AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK', - 'AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK', 'AMDGPU_UCODE_ID_DMCUB', - 'AMDGPU_UCODE_ID_DMCU_ERAM', 'AMDGPU_UCODE_ID_DMCU_INTV', - 'AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS', 'AMDGPU_UCODE_ID_IMU_D', - 'AMDGPU_UCODE_ID_IMU_I', 'AMDGPU_UCODE_ID_ISP', - 'AMDGPU_UCODE_ID_JPEG_RAM', 'AMDGPU_UCODE_ID_MAXIMUM', - 'AMDGPU_UCODE_ID_P2S_TABLE', 'AMDGPU_UCODE_ID_PPTABLE', - 'AMDGPU_UCODE_ID_RLC_DRAM', 'AMDGPU_UCODE_ID_RLC_G', - 'AMDGPU_UCODE_ID_RLC_IRAM', 'AMDGPU_UCODE_ID_RLC_P', - 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL', - 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM', - 'AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM', - 'AMDGPU_UCODE_ID_RLC_V', 'AMDGPU_UCODE_ID_SDMA0', - 'AMDGPU_UCODE_ID_SDMA1', 'AMDGPU_UCODE_ID_SDMA2', - 'AMDGPU_UCODE_ID_SDMA3', 'AMDGPU_UCODE_ID_SDMA4', - 'AMDGPU_UCODE_ID_SDMA5', 'AMDGPU_UCODE_ID_SDMA6', - 'AMDGPU_UCODE_ID_SDMA7', 'AMDGPU_UCODE_ID_SDMA_RS64', - 'AMDGPU_UCODE_ID_SDMA_UCODE_TH0', - 'AMDGPU_UCODE_ID_SDMA_UCODE_TH1', - 'AMDGPU_UCODE_ID_SE0_TAP_DELAYS', - 'AMDGPU_UCODE_ID_SE1_TAP_DELAYS', - 'AMDGPU_UCODE_ID_SE2_TAP_DELAYS', - 'AMDGPU_UCODE_ID_SE3_TAP_DELAYS', 'AMDGPU_UCODE_ID_SMC', - 'AMDGPU_UCODE_ID_STORAGE', 'AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER', - 'AMDGPU_UCODE_ID_UMSCH_MM_DATA', 'AMDGPU_UCODE_ID_UMSCH_MM_UCODE', - 'AMDGPU_UCODE_ID_UVD', 'AMDGPU_UCODE_ID_UVD1', - 'AMDGPU_UCODE_ID_VCE', 'AMDGPU_UCODE_ID_VCN', - 'AMDGPU_UCODE_ID_VCN0_RAM', 'AMDGPU_UCODE_ID_VCN1', - 'AMDGPU_UCODE_ID_VCN1_RAM', 'AMDGPU_UCODE_ID_VPE', - 'AMDGPU_UCODE_ID_VPE_CTL', 'AMDGPU_UCODE_ID_VPE_CTX', - 'AMDGPU_UCODE_STATUS', 'AMDGPU_UCODE_STATUS_INVALID', - 'AMDGPU_UCODE_STATUS_LOADED', 'AMDGPU_UCODE_STATUS_NOT_LOADED', - 'AMDGPU_VA_RESERVED_BOTTOM', 'AMDGPU_VA_RESERVED_CSA_SIZE', - 'AMDGPU_VA_RESERVED_SEQ64_SIZE', 'AMDGPU_VA_RESERVED_TOP', - 'AMDGPU_VA_RESERVED_TRAP_SIZE', - 'AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP', - 'AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5', - 'AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5', - 'AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7', - 'AMDGPU_VEGA20_DOORBELL64_VCN0_1', - 'AMDGPU_VEGA20_DOORBELL64_VCN2_3', - 'AMDGPU_VEGA20_DOORBELL64_VCN4_5', - 'AMDGPU_VEGA20_DOORBELL64_VCN6_7', - 'AMDGPU_VEGA20_DOORBELL64_VCN8_9', - 'AMDGPU_VEGA20_DOORBELL64_VCNa_b', - 'AMDGPU_VEGA20_DOORBELL64_VCNc_d', - 'AMDGPU_VEGA20_DOORBELL64_VCNe_f', - 'AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START', - 'AMDGPU_VEGA20_DOORBELL_ASSIGNMENT', 'AMDGPU_VEGA20_DOORBELL_DIQ', - 'AMDGPU_VEGA20_DOORBELL_GFX_RING0', 'AMDGPU_VEGA20_DOORBELL_HIQ', - 'AMDGPU_VEGA20_DOORBELL_IH', 'AMDGPU_VEGA20_DOORBELL_INVALID', - 'AMDGPU_VEGA20_DOORBELL_KIQ', - 'AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING0', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING1', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING2', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING3', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING4', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING5', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING6', - 'AMDGPU_VEGA20_DOORBELL_MEC_RING7', - 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_END', - 'AMDGPU_VEGA20_DOORBELL_USERQUEUE_START', - 'AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START', - 'AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6', - 'AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7', - 'AMDGPU_VM_FAULT_STOP_ALWAYS', 'AMDGPU_VM_FAULT_STOP_FIRST', - 'AMDGPU_VM_FAULT_STOP_NEVER', 'AMDGPU_VM_MAX_UPDATE_SIZE', - 'AMDGPU_VM_NORETRY_FLAGS', 'AMDGPU_VM_NORETRY_FLAGS_TF', - 'AMDGPU_VM_PDB0', 'AMDGPU_VM_PDB1', 'AMDGPU_VM_PDB2', - 'AMDGPU_VM_PTB', 'AMDGPU_VM_RESERVED_VRAM', - 'AMDGPU_VM_USE_CPU_FOR_COMPUTE', 'AMDGPU_VM_USE_CPU_FOR_GFX', - 'AMDGPU_XGMI_MAX_CONNECTED_NODES', 'ATHUB_HWID', 'ATHUB_HWIP', - 'AUDIO_AZ_HWID', 'BINARY_SIGNATURE', - 'BIST_MEM_TRAINING_ENCROACHED_SIZE', 'BOOTCFG_CMD_GET', - 'BOOTCFG_CMD_INVALIDATE', 'BOOTCFG_CMD_SET', - 'BOOT_CFG_FEATURE_GECC', - 'BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING', 'BOOT_CONFIG_GECC', - 'C2PMSG_CMD_GFX_USB_PD_FW_VER', 'CCXSEC_HWID', 'CLKA_HWID', - 'CLKB_HWID', 'CLK_HWIP', 'DAZ_HWID', 'DBGU0_HWID', 'DBGU1_HWID', - 'DBGU_IO_HWID', 'DBGU_NBIO_HWID', 'DCEAZ_HWID', 'DCE_HWIP', - 'DCI_HWID', 'DCI_HWIP', 'DCO_HWID', 'DDCL_HWID', 'DFX_DAP_HWID', - 'DFX_HWID', 'DF_HWID', 'DF_HWIP', 'DIO_HWID', - 'DISCOVERY_TABLE_SIGNATURE', 'DMU_HWID', 'FCH_HWID', - 'FCH_USB_PD_HWID', 'FRAME_TYPE_DESTROY', 'FUSE_HWID', 'GC', - 'GC_HWID', 'GC_HWIP', 'GC_TABLE_ID', - 'GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES', - 'GDDR6_MEM_TRAINING_OFFSET', 'GFX_BUF_MAX_DESC', - 'GFX_CMD_ID_AUTOLOAD_RLC', 'GFX_CMD_ID_BOOT_CFG', - 'GFX_CMD_ID_DESTROY_TMR', 'GFX_CMD_ID_DESTROY_VMR', - 'GFX_CMD_ID_GET_FW_ATTESTATION', 'GFX_CMD_ID_INVOKE_CMD', - 'GFX_CMD_ID_LOAD_ASD', 'GFX_CMD_ID_LOAD_IP_FW', - 'GFX_CMD_ID_LOAD_TA', 'GFX_CMD_ID_LOAD_TOC', 'GFX_CMD_ID_MASK', - 'GFX_CMD_ID_PROG_REG', 'GFX_CMD_ID_SAVE_RESTORE', - 'GFX_CMD_ID_SETUP_TMR', 'GFX_CMD_ID_SETUP_VMR', - 'GFX_CMD_ID_SRIOV_SPATIAL_PART', 'GFX_CMD_ID_UNLOAD_TA', - 'GFX_CMD_RESERVED_MASK', 'GFX_CMD_RESPONSE_MASK', - 'GFX_CMD_STATUS_MASK', 'GFX_CTRL_CMD_ID_CAN_INIT_RINGS', - 'GFX_CTRL_CMD_ID_CONSUME_CMD', - 'GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING', - 'GFX_CTRL_CMD_ID_DESTROY_RINGS', 'GFX_CTRL_CMD_ID_DISABLE_INT', - 'GFX_CTRL_CMD_ID_ENABLE_INT', 'GFX_CTRL_CMD_ID_GBR_IH_SET', - 'GFX_CTRL_CMD_ID_INIT_GPCOM_RING', - 'GFX_CTRL_CMD_ID_INIT_RBI_RING', 'GFX_CTRL_CMD_ID_MAX', - 'GFX_CTRL_CMD_ID_MODE1_RST', 'GFX_FLAG_RESPONSE', - 'GFX_FW_TYPE_ACCUM_CTRL_RAM', 'GFX_FW_TYPE_ACP', - 'GFX_FW_TYPE_CAP', 'GFX_FW_TYPE_CP_CE', 'GFX_FW_TYPE_CP_ME', - 'GFX_FW_TYPE_CP_MEC', 'GFX_FW_TYPE_CP_MEC_ME1', - 'GFX_FW_TYPE_CP_MEC_ME2', 'GFX_FW_TYPE_CP_MES', - 'GFX_FW_TYPE_CP_MES_KIQ', 'GFX_FW_TYPE_CP_PFP', - 'GFX_FW_TYPE_DISCRETE_USB4', 'GFX_FW_TYPE_DMCU_ERAM', - 'GFX_FW_TYPE_DMCU_ISR', 'GFX_FW_TYPE_DMUB', - 'GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM', - 'GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS', - 'GFX_FW_TYPE_GLOBAL_TAP_DELAYS', 'GFX_FW_TYPE_IMU_D', - 'GFX_FW_TYPE_IMU_I', 'GFX_FW_TYPE_ISP', 'GFX_FW_TYPE_ISP_DATA', - 'GFX_FW_TYPE_JPEG_RAM', 'GFX_FW_TYPE_LSDMA', 'GFX_FW_TYPE_MAX', - 'GFX_FW_TYPE_MES_KIQ_STACK', 'GFX_FW_TYPE_MES_STACK', - 'GFX_FW_TYPE_MMSCH', 'GFX_FW_TYPE_NONE', 'GFX_FW_TYPE_P2S_TABLE', - 'GFX_FW_TYPE_PPTABLE', 'GFX_FW_TYPE_REG_LIST', - 'GFX_FW_TYPE_RLCG_SCRATCH_SR', 'GFX_FW_TYPE_RLCP_CAM', - 'GFX_FW_TYPE_RLCP_SCRATCH_SR', 'GFX_FW_TYPE_RLCV_SCRATCH_SR', - 'GFX_FW_TYPE_RLC_DRAM_BOOT', 'GFX_FW_TYPE_RLC_G', - 'GFX_FW_TYPE_RLC_IRAM', 'GFX_FW_TYPE_RLC_P', - 'GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM', - 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL', - 'GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM', - 'GFX_FW_TYPE_RLC_SPP_CAM_EXT', 'GFX_FW_TYPE_RLC_SRM_DRAM_SR', - 'GFX_FW_TYPE_RLC_V', 'GFX_FW_TYPE_RLX6_DRAM_SR', - 'GFX_FW_TYPE_RS64_KIQ', 'GFX_FW_TYPE_RS64_KIQ_STACK', - 'GFX_FW_TYPE_RS64_ME', 'GFX_FW_TYPE_RS64_MEC', - 'GFX_FW_TYPE_RS64_MEC_P0_STACK', 'GFX_FW_TYPE_RS64_MEC_P1_STACK', - 'GFX_FW_TYPE_RS64_MEC_P2_STACK', 'GFX_FW_TYPE_RS64_MEC_P3_STACK', - 'GFX_FW_TYPE_RS64_MES', 'GFX_FW_TYPE_RS64_MES_STACK', - 'GFX_FW_TYPE_RS64_ME_P0_STACK', 'GFX_FW_TYPE_RS64_ME_P1_STACK', - 'GFX_FW_TYPE_RS64_PFP', 'GFX_FW_TYPE_RS64_PFP_P0_STACK', - 'GFX_FW_TYPE_RS64_PFP_P1_STACK', 'GFX_FW_TYPE_SDMA0', - 'GFX_FW_TYPE_SDMA0_JT', 'GFX_FW_TYPE_SDMA0_PG_CONTEXT', - 'GFX_FW_TYPE_SDMA1', 'GFX_FW_TYPE_SDMA1_JT', - 'GFX_FW_TYPE_SDMA1_PG_CONTEXT', 'GFX_FW_TYPE_SDMA2', - 'GFX_FW_TYPE_SDMA3', 'GFX_FW_TYPE_SDMA4', 'GFX_FW_TYPE_SDMA5', - 'GFX_FW_TYPE_SDMA6', 'GFX_FW_TYPE_SDMA7', - 'GFX_FW_TYPE_SDMA_UCODE_TH0', 'GFX_FW_TYPE_SDMA_UCODE_TH1', - 'GFX_FW_TYPE_SE0_MUX_SELECT_RAM', 'GFX_FW_TYPE_SE0_TAP_DELAYS', - 'GFX_FW_TYPE_SE1_MUX_SELECT_RAM', 'GFX_FW_TYPE_SE1_TAP_DELAYS', - 'GFX_FW_TYPE_SE2_TAP_DELAYS', 'GFX_FW_TYPE_SE3_TAP_DELAYS', - 'GFX_FW_TYPE_SMU', 'GFX_FW_TYPE_TA', 'GFX_FW_TYPE_TOC', - 'GFX_FW_TYPE_UMSCH_CMD_BUFFER', 'GFX_FW_TYPE_UMSCH_DATA', - 'GFX_FW_TYPE_UMSCH_UCODE', 'GFX_FW_TYPE_USB_DP_COMBO_PHY', - 'GFX_FW_TYPE_UVD', 'GFX_FW_TYPE_UVD1', 'GFX_FW_TYPE_VCE', - 'GFX_FW_TYPE_VCN', 'GFX_FW_TYPE_VCN0_RAM', 'GFX_FW_TYPE_VCN1', - 'GFX_FW_TYPE_VCN1_RAM', 'GFX_FW_TYPE_VPE', 'GFX_FW_TYPE_VPEC_FW1', - 'GFX_FW_TYPE_VPEC_FW2', 'HARVEST_INFO', 'HARVEST_TABLE_SIGNATURE', - 'HDP_HWID', 'HDP_HWIP', 'HWIP_MAX_INSTANCE', 'HW_ID_MAX', - 'IOAGR_HWID', 'IOAPIC_HWID', 'IOHC_HWID', 'IP_DISCOVERY', - 'ISP_HWID', 'ISP_HWIP', 'JPEG_HWIP', 'L1IMU10_HWID', - 'L1IMU11_HWID', 'L1IMU12_HWID', 'L1IMU13_HWID', 'L1IMU14_HWID', - 'L1IMU15_HWID', 'L1IMU3_HWID', 'L1IMU4_HWID', 'L1IMU5_HWID', - 'L1IMU6_HWID', 'L1IMU7_HWID', 'L1IMU8_HWID', 'L1IMU9_HWID', - 'L1IMU_IOAGR_HWID', 'L1IMU_NBIF_HWID', 'L1IMU_PCIE_HWID', - 'L2IMU_HWID', 'LSDMA_HWID', 'LSDMA_HWIP', 'MALL_INFO', - 'MALL_INFO_TABLE_ID', 'MAX_HWIP', 'MEM_TRAIN_SYSTEM_SIGNATURE', - 'MMHUB_HWID', 'MMHUB_HWIP', 'MP0_HWID', 'MP0_HWIP', 'MP1_HWID', - 'MP1_HWIP', 'MP2_HWID', 'NBIF_HWID', 'NBIF_HWIP', 'NBIO_HWIP', - 'NODEID_MAX', 'NPS_INFO', 'NPS_INFO_TABLE_ID', - 'NPS_INFO_TABLE_MAX_NUM_INSTANCES', 'NTBCCP_HWID', 'NTB_HWID', - 'OSSSYS_HWID', 'OSSSYS_HWIP', 'PCIE_HWID', 'PCIE_HWIP', - 'PCS_HWID', 'PSP_1_MEG', 'PSP_ASD_SHARED_MEM_SIZE', - 'PSP_BL__DRAM_LONG_TRAIN', 'PSP_BL__DRAM_SHORT_TRAIN', - 'PSP_BL__LOAD_DBGDRV', 'PSP_BL__LOAD_HADDRV', - 'PSP_BL__LOAD_INTFDRV', 'PSP_BL__LOAD_IPKEYMGRDRV', - 'PSP_BL__LOAD_KEY_DATABASE', 'PSP_BL__LOAD_RASDRV', - 'PSP_BL__LOAD_SOCDRV', 'PSP_BL__LOAD_SOSDRV', - 'PSP_BL__LOAD_SYSDRV', 'PSP_BL__LOAD_TOS_SPL_TABLE', - 'PSP_CMD_BUFFER_SIZE', 'PSP_DTM_SHARED_MEM_SIZE', - 'PSP_ERR_UNKNOWN_COMMAND', 'PSP_FENCE_BUFFER_SIZE', - 'PSP_FW_NAME_LEN', 'PSP_FW_TYPE_MAX_INDEX', - 'PSP_FW_TYPE_PSP_DBG_DRV', 'PSP_FW_TYPE_PSP_INTF_DRV', - 'PSP_FW_TYPE_PSP_IPKEYMGR_DRV', 'PSP_FW_TYPE_PSP_KDB', - 'PSP_FW_TYPE_PSP_RAS_DRV', 'PSP_FW_TYPE_PSP_RL', - 'PSP_FW_TYPE_PSP_SOC_DRV', 'PSP_FW_TYPE_PSP_SOS', - 'PSP_FW_TYPE_PSP_SPL', 'PSP_FW_TYPE_PSP_SYS_DRV', - 'PSP_FW_TYPE_PSP_TOC', 'PSP_FW_TYPE_UNKOWN', - 'PSP_GFX_CMD_BUF_VERSION', 'PSP_HDCP_SHARED_MEM_SIZE', - 'PSP_HEADER_SIZE', 'PSP_MEM_TRAIN_COLD_BOOT', - 'PSP_MEM_TRAIN_INIT_FAILED', 'PSP_MEM_TRAIN_INIT_SUCCESS', - 'PSP_MEM_TRAIN_NOT_SUPPORT', 'PSP_MEM_TRAIN_RESERVE_SUCCESS', - 'PSP_MEM_TRAIN_RESTORE', 'PSP_MEM_TRAIN_RESUME', - 'PSP_MEM_TRAIN_SAVE', 'PSP_MEM_TRAIN_SEND_LONG_MSG', - 'PSP_MEM_TRAIN_SEND_SHORT_MSG', 'PSP_MEM_TRAIN_SUPPORT', - 'PSP_RAP_SHARED_MEM_SIZE', 'PSP_RAS_SHARED_MEM_SIZE', - 'PSP_REG_IH_RB_CNTL', 'PSP_REG_IH_RB_CNTL_RING1', - 'PSP_REG_IH_RB_CNTL_RING2', 'PSP_REG_LAST', - 'PSP_RING_TYPE__INVALID', 'PSP_RING_TYPE__KM', - 'PSP_RING_TYPE__UM', 'PSP_RUNTIME_DB_COOKIE_ID', - 'PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT', 'PSP_RUNTIME_DB_OFFSET', - 'PSP_RUNTIME_DB_SIZE_IN_BYTES', 'PSP_RUNTIME_DB_VER_1', - 'PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG', - 'PSP_RUNTIME_ENTRY_TYPE_INVALID', - 'PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON', - 'PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL', - 'PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI', - 'PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS', - 'PSP_RUNTIME_ENTRY_TYPE_TEST', - 'PSP_SECUREDISPLAY_SHARED_MEM_SIZE', 'PSP_TMR_ALIGNMENT', - 'PSP_XGMI_SHARED_MEM_SIZE', 'PWR_HWID', 'PWR_HWIP', 'RSMU_HWIP', - 'SATA_HWID', 'SCPM_DISABLE', 'SCPM_ENABLE', - 'SCPM_ENABLE_WITH_SCPM_ERR', 'SDMA0_HWID', 'SDMA0_HWIP', - 'SDMA1_HWID', 'SDMA1_HWIP', 'SDMA2_HWID', 'SDMA2_HWIP', - 'SDMA3_HWID', 'SDMA3_HWIP', 'SDMA4_HWIP', 'SDMA5_HWIP', - 'SDMA6_HWIP', 'SDMA7_HWIP', 'SDPMUX_HWID', 'SMUIO_HWID', - 'SMUIO_HWIP', 'SOC15_IH_CLIENTID_ACP', 'SOC15_IH_CLIENTID_ATHUB', - 'SOC15_IH_CLIENTID_ATS', 'SOC15_IH_CLIENTID_BIF', - 'SOC15_IH_CLIENTID_DCE', 'SOC15_IH_CLIENTID_DF', - 'SOC15_IH_CLIENTID_EA', 'SOC15_IH_CLIENTID_GRBM_CP', - 'SOC15_IH_CLIENTID_IH', 'SOC15_IH_CLIENTID_ISP', - 'SOC15_IH_CLIENTID_MAX', 'SOC15_IH_CLIENTID_MP0', - 'SOC15_IH_CLIENTID_MP1', 'SOC15_IH_CLIENTID_PCIE0', - 'SOC15_IH_CLIENTID_PWR', 'SOC15_IH_CLIENTID_RESERVED', - 'SOC15_IH_CLIENTID_RLC', 'SOC15_IH_CLIENTID_ROM_SMUIO', - 'SOC15_IH_CLIENTID_SDMA0', 'SOC15_IH_CLIENTID_SDMA1', - 'SOC15_IH_CLIENTID_SDMA2', 'SOC15_IH_CLIENTID_SDMA3', - 'SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid', - 'SOC15_IH_CLIENTID_SDMA4', 'SOC15_IH_CLIENTID_SDMA5', - 'SOC15_IH_CLIENTID_SDMA6', 'SOC15_IH_CLIENTID_SDMA7', - 'SOC15_IH_CLIENTID_SE0SH', 'SOC15_IH_CLIENTID_SE1SH', - 'SOC15_IH_CLIENTID_SE2SH', 'SOC15_IH_CLIENTID_SE3SH', - 'SOC15_IH_CLIENTID_THM', 'SOC15_IH_CLIENTID_UTCL2', - 'SOC15_IH_CLIENTID_UTCL2LOG', 'SOC15_IH_CLIENTID_UVD', - 'SOC15_IH_CLIENTID_UVD1', 'SOC15_IH_CLIENTID_VCE0', - 'SOC15_IH_CLIENTID_VCE1', 'SOC15_IH_CLIENTID_VCN', - 'SOC15_IH_CLIENTID_VCN1', 'SOC15_IH_CLIENTID_VMC', - 'SOC15_IH_CLIENTID_VMC1', 'SOC15_IH_CLIENTID_XDMA', - 'SOC21_IH_CLIENTID_ATHUB', 'SOC21_IH_CLIENTID_BIF', - 'SOC21_IH_CLIENTID_DCN', 'SOC21_IH_CLIENTID_DF', - 'SOC21_IH_CLIENTID_GFX', 'SOC21_IH_CLIENTID_GRBM_CP', - 'SOC21_IH_CLIENTID_IH', 'SOC21_IH_CLIENTID_IMU', - 'SOC21_IH_CLIENTID_ISP', 'SOC21_IH_CLIENTID_LSDMA', - 'SOC21_IH_CLIENTID_MAX', 'SOC21_IH_CLIENTID_MP0', - 'SOC21_IH_CLIENTID_MP1', 'SOC21_IH_CLIENTID_MP3', - 'SOC21_IH_CLIENTID_PWR', 'SOC21_IH_CLIENTID_RLC', - 'SOC21_IH_CLIENTID_ROM_SMUIO', 'SOC21_IH_CLIENTID_THM', - 'SOC21_IH_CLIENTID_VCN', 'SOC21_IH_CLIENTID_VCN1', - 'SOC21_IH_CLIENTID_VMC', 'SOC21_IH_CLIENTID_VPE', - 'SOC21_IH_CLIENTID_VPE1', 'SST_HWID', 'SYSTEMHUB_HWID', - 'TA_FW_TYPE_MAX_INDEX', 'TA_FW_TYPE_PSP_ASD', - 'TA_FW_TYPE_PSP_DTM', 'TA_FW_TYPE_PSP_HDCP', 'TA_FW_TYPE_PSP_RAP', - 'TA_FW_TYPE_PSP_RAS', 'TA_FW_TYPE_PSP_SECUREDISPLAY', - 'TA_FW_TYPE_PSP_XGMI', 'TA_FW_TYPE_UNKOWN', 'TA_TYPE_DTM', - 'TA_TYPE_HDCP', 'TA_TYPE_MAX_INDEX', 'TA_TYPE_RAP', 'TA_TYPE_RAS', - 'TA_TYPE_SECUREDISPLAY', 'TA_TYPE_XGMI', - 'TEE_ERROR_NOT_SUPPORTED', 'TEE_SUCCESS', 'THM_HWID', 'THM_HWIP', - 'TOTAL_TABLES', 'UMC_HWID', 'UMC_HWIP', 'USB_HWID', 'UVD_HWID', - 'UVD_HWIP', 'V11_STRUCTS_H_', 'V12_STRUCTS_H_', 'VCE_HWID', - 'VCE_HWIP', 'VCN1_HWIP', 'VCN_HWID', 'VCN_HWIP', 'VCN_INFO', - 'VCN_INFO_TABLE_ID', 'VCN_INFO_TABLE_MAX_NUM_INSTANCES', - 'VPE_HWID', 'VPE_HWIP', 'WAFLC_HWID', 'XCD0_NODEID', - 'XCD1_NODEID', 'XCD2_NODEID', 'XCD3_NODEID', 'XCD4_NODEID', - 'XCD5_NODEID', 'XCD6_NODEID', 'XCD7_NODEID', 'XDMA_HWID', - 'XGBE_HWID', 'XGMI_HWID', 'XGMI_HWIP', '_DISCOVERY_H_', - '_PSP_TEE_GFX_IF_H_', '__AMDGPU_IRQ_H__', '__AMDGPU_PSP_H__', - '__AMDGPU_UCODE_H__', '__AMDGPU_VM_H__', - '__SOC15_IH_CLIENTID_H__', 'amd_hw_ip_block_type', - 'amdgpu_firmware_load_type', 'amdgpu_interrupt_state', - 'amdgpu_vm_level', 'binary_header', 'bool', 'c__EA_table', - 'die_header', 'die_info', 'harvest_info', 'harvest_info_header', - 'harvest_table', 'hw_id_map', 'int16_t', 'int32_t', 'int8_t', - 'interrupt_node_id_per_aid', 'ip', 'ip_discovery_header', - 'ip_structure', 'ip_v3', 'ip_v4', 'psp_bootloader_cmd', - 'psp_fw_type', 'psp_gfx_boot_config', 'psp_gfx_boot_config_cmd', - 'psp_gfx_cmd_id', 'psp_gfx_crtl_cmd_id', 'psp_gfx_fw_type', - 'psp_memory_training_init_flag', 'psp_memory_training_ops', - 'psp_reg_prog_id', 'psp_ring_type', - 'psp_runtime_boot_cfg_feature', 'psp_runtime_entry_type', - 'psp_runtime_scpm_authentication', 'psp_shared_mem_size', - 'soc15_ih_clientid', 'soc15_ih_clientid_name', - 'soc21_ih_clientid', 'struct__fuse_data_bits', - 'struct_amdgpu_device', 'struct_amdgpu_firmware_info', - 'struct_amdgpu_iv_entry', 'struct_binary_header', - 'struct_common_firmware_header', 'struct_die', - 'struct_die_header', 'struct_die_info', - 'struct_dmcu_firmware_header_v1_0', - 'struct_dmcub_firmware_header_v1_0', 'struct_firmware', - 'struct_gc_info_v1_0', 'struct_gc_info_v1_1', - 'struct_gc_info_v1_2', 'struct_gc_info_v1_3', - 'struct_gc_info_v2_0', 'struct_gc_info_v2_1', - 'struct_gfx_firmware_header_v1_0', - 'struct_gfx_firmware_header_v2_0', - 'struct_gpu_info_firmware_header_v1_0', - 'struct_gpu_info_firmware_v1_0', 'struct_gpu_info_firmware_v1_1', - 'struct_gpu_info_header', 'struct_harvest_info', - 'struct_harvest_info_header', 'struct_harvest_table', - 'struct_imu_firmware_header_v1_0', 'struct_ip', - 'struct_ip_discovery_header', 'struct_ip_discovery_header_0_0', - 'struct_ip_structure', 'struct_ip_v3', 'struct_ip_v4', - 'struct_mall_info_header', 'struct_mall_info_v1_0', - 'struct_mall_info_v2_0', 'struct_mc_firmware_header_v1_0', - 'struct_mes_firmware_header_v1_0', 'struct_nps_info_header', - 'struct_nps_info_v1_0', 'struct_nps_instance_info_v1_0', - 'struct_psp_bin_desc', 'struct_psp_context', - 'struct_psp_firmware_header_v1_0', - 'struct_psp_firmware_header_v1_1', - 'struct_psp_firmware_header_v1_2', - 'struct_psp_firmware_header_v1_3', - 'struct_psp_firmware_header_v2_0', - 'struct_psp_firmware_header_v2_1', 'struct_psp_fw_bin_desc', - 'struct_psp_fw_legacy_bin_desc', 'struct_psp_gfx_buf_desc', - 'struct_psp_gfx_buf_list', 'struct_psp_gfx_cmd_boot_cfg', - 'struct_psp_gfx_cmd_invoke_cmd', 'struct_psp_gfx_cmd_load_ip_fw', - 'struct_psp_gfx_cmd_load_ta', 'struct_psp_gfx_cmd_load_toc', - 'struct_psp_gfx_cmd_reg_prog', 'struct_psp_gfx_cmd_resp', - 'struct_psp_gfx_cmd_save_restore_ip_fw', - 'struct_psp_gfx_cmd_setup_tmr', - 'struct_psp_gfx_cmd_setup_tmr_0_bitfield', - 'struct_psp_gfx_cmd_sriov_spatial_part', - 'struct_psp_gfx_cmd_unload_ta', 'struct_psp_gfx_ctrl', - 'struct_psp_gfx_rb_frame', 'struct_psp_gfx_resp', - 'struct_psp_gfx_uresp_bootcfg', - 'struct_psp_gfx_uresp_fwar_db_info', - 'struct_psp_gfx_uresp_reserved', 'struct_psp_xgmi_node_info', - 'struct_psp_xgmi_topology_info', - 'struct_rlc_firmware_header_v1_0', - 'struct_rlc_firmware_header_v2_0', - 'struct_rlc_firmware_header_v2_1', - 'struct_rlc_firmware_header_v2_2', - 'struct_rlc_firmware_header_v2_3', - 'struct_rlc_firmware_header_v2_4', - 'struct_sdma_firmware_header_v1_0', - 'struct_sdma_firmware_header_v1_1', - 'struct_sdma_firmware_header_v2_0', - 'struct_sdma_firmware_header_v3_0', - 'struct_smc_firmware_header_v1_0', - 'struct_smc_firmware_header_v2_0', - 'struct_smc_firmware_header_v2_1', - 'struct_smc_soft_pptable_entry', 'struct_ta_firmware_header_v1_0', - 'struct_ta_firmware_header_v2_0', 'struct_table_info', - 'struct_umsch_mm_firmware_header_v1_0', 'struct_v11_compute_mqd', - 'struct_v11_gfx_mqd', 'struct_v11_sdma_mqd', - 'struct_v12_compute_mqd', 'struct_v12_gfx_mqd', - 'struct_v12_sdma_mqd', 'struct_vcn_info_header', - 'struct_vcn_info_v1_0', 'struct_vcn_instance_info_v1_0', - 'struct_vpe_firmware_header_v1_0', 'ta_fw_type', 'ta_type_id', - 'table', 'table__enumvalues', 'table_info', 'tee_error_code', - 'u32', 'uint16_t', 'uint32_t', 'uint64_t', 'uint8_t', - 'union__fuse_data', 'union_amdgpu_firmware_header', 'union_die_0', - 'union_ip_discovery_header_0', 'union_psp_gfx_cmd_setup_tmr_0', - 'union_psp_gfx_commands', 'union_psp_gfx_uresp'] +AMDGPU_VM_MAX_UPDATE_SIZE = 0x3FFFF +AMDGPU_PTE_VALID = (1 << 0) +AMDGPU_PTE_SYSTEM = (1 << 1) +AMDGPU_PTE_SNOOPED = (1 << 2) +AMDGPU_PTE_TMZ = (1 << 3) +AMDGPU_PTE_EXECUTABLE = (1 << 4) +AMDGPU_PTE_READABLE = (1 << 5) +AMDGPU_PTE_WRITEABLE = (1 << 6) +AMDGPU_PTE_FRAG = lambda x: ((x & 0x1f) << 7) +AMDGPU_PTE_PRT = (1 << 51) +AMDGPU_PDE_PTE = (1 << 54) +AMDGPU_PTE_LOG = (1 << 55) +AMDGPU_PTE_TF = (1 << 56) +AMDGPU_PTE_NOALLOC = (1 << 58) +AMDGPU_PDE_BFS = lambda a: (a << 59) +AMDGPU_VM_NORETRY_FLAGS = (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | AMDGPU_PTE_TF) +AMDGPU_VM_NORETRY_FLAGS_TF = (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | AMDGPU_PTE_PRT) +AMDGPU_PTE_MTYPE_VG10_SHIFT = lambda mtype: ((mtype) << 57) +AMDGPU_PTE_MTYPE_VG10_MASK = AMDGPU_PTE_MTYPE_VG10_SHIFT(3) +AMDGPU_PTE_MTYPE_VG10 = lambda flags,mtype: (((flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)) +AMDGPU_MTYPE_NC = 0 +AMDGPU_MTYPE_CC = 2 +AMDGPU_PTE_MTYPE_NV10_SHIFT = lambda mtype: ((mtype) << 48) +AMDGPU_PTE_MTYPE_NV10_MASK = AMDGPU_PTE_MTYPE_NV10_SHIFT(7) +AMDGPU_PTE_MTYPE_NV10 = lambda flags,mtype: (((flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)) +AMDGPU_PTE_PRT_GFX12 = (1 << 56) +AMDGPU_PTE_MTYPE_GFX12_SHIFT = lambda mtype: ((mtype) << 54) +AMDGPU_PTE_MTYPE_GFX12_MASK = AMDGPU_PTE_MTYPE_GFX12_SHIFT(3) +AMDGPU_PTE_MTYPE_GFX12 = lambda flags,mtype: (((flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) +AMDGPU_PTE_IS_PTE = (1 << 63) +AMDGPU_PDE_BFS_GFX12 = lambda a: (((a) & 0x1f) << 58) +AMDGPU_PDE_PTE_GFX12 = (1 << 63) +AMDGPU_VM_FAULT_STOP_NEVER = 0 +AMDGPU_VM_FAULT_STOP_FIRST = 1 +AMDGPU_VM_FAULT_STOP_ALWAYS = 2 +AMDGPU_VM_RESERVED_VRAM = (8 << 20) +AMDGPU_MAX_VMHUBS = 13 +AMDGPU_GFXHUB_START = 0 +AMDGPU_MMHUB0_START = 8 +AMDGPU_MMHUB1_START = 12 +AMDGPU_GFXHUB = lambda x: (AMDGPU_GFXHUB_START + (x)) +AMDGPU_MMHUB0 = lambda x: (AMDGPU_MMHUB0_START + (x)) +AMDGPU_MMHUB1 = lambda x: (AMDGPU_MMHUB1_START + (x)) +AMDGPU_IS_GFXHUB = lambda x: ((x) >= AMDGPU_GFXHUB_START and (x) < AMDGPU_MMHUB0_START) +AMDGPU_IS_MMHUB0 = lambda x: ((x) >= AMDGPU_MMHUB0_START and (x) < AMDGPU_MMHUB1_START) +AMDGPU_IS_MMHUB1 = lambda x: ((x) >= AMDGPU_MMHUB1_START and (x) < AMDGPU_MAX_VMHUBS) +AMDGPU_VA_RESERVED_CSA_SIZE = (2 << 20) +AMDGPU_VA_RESERVED_SEQ64_SIZE = (2 << 20) +AMDGPU_VA_RESERVED_SEQ64_START = lambda adev: (AMDGPU_VA_RESERVED_CSA_START(adev) - AMDGPU_VA_RESERVED_SEQ64_SIZE) +AMDGPU_VA_RESERVED_TRAP_SIZE = (2 << 12) +AMDGPU_VA_RESERVED_TRAP_START = lambda adev: (AMDGPU_VA_RESERVED_SEQ64_START(adev) - AMDGPU_VA_RESERVED_TRAP_SIZE) +AMDGPU_VA_RESERVED_BOTTOM = (1 << 16) +AMDGPU_VA_RESERVED_TOP = (AMDGPU_VA_RESERVED_TRAP_SIZE + AMDGPU_VA_RESERVED_SEQ64_SIZE + AMDGPU_VA_RESERVED_CSA_SIZE) +AMDGPU_VM_USE_CPU_FOR_GFX = (1 << 0) +AMDGPU_VM_USE_CPU_FOR_COMPUTE = (1 << 1) +PSP_HEADER_SIZE = 256 +BINARY_SIGNATURE = 0x28211407 +DISCOVERY_TABLE_SIGNATURE = 0x53445049 +GC_TABLE_ID = 0x4347 +HARVEST_TABLE_SIGNATURE = 0x56524148 +VCN_INFO_TABLE_ID = 0x004E4356 +MALL_INFO_TABLE_ID = 0x4C4C414D +NPS_INFO_TABLE_ID = 0x0053504E +VCN_INFO_TABLE_MAX_NUM_INSTANCES = 4 +NPS_INFO_TABLE_MAX_NUM_INSTANCES = 12 +HWIP_MAX_INSTANCE = 44 +HW_ID_MAX = 300 +MP1_HWID = 1 +MP2_HWID = 2 +THM_HWID = 3 +SMUIO_HWID = 4 +FUSE_HWID = 5 +CLKA_HWID = 6 +PWR_HWID = 10 +GC_HWID = 11 +UVD_HWID = 12 +VCN_HWID = UVD_HWID +AUDIO_AZ_HWID = 13 +ACP_HWID = 14 +DCI_HWID = 15 +DMU_HWID = 271 +DCO_HWID = 16 +DIO_HWID = 272 +XDMA_HWID = 17 +DCEAZ_HWID = 18 +DAZ_HWID = 274 +SDPMUX_HWID = 19 +NTB_HWID = 20 +VPE_HWID = 21 +IOHC_HWID = 24 +L2IMU_HWID = 28 +VCE_HWID = 32 +MMHUB_HWID = 34 +ATHUB_HWID = 35 +DBGU_NBIO_HWID = 36 +DFX_HWID = 37 +DBGU0_HWID = 38 +DBGU1_HWID = 39 +OSSSYS_HWID = 40 +HDP_HWID = 41 +SDMA0_HWID = 42 +SDMA1_HWID = 43 +ISP_HWID = 44 +DBGU_IO_HWID = 45 +DF_HWID = 46 +CLKB_HWID = 47 +FCH_HWID = 48 +DFX_DAP_HWID = 49 +L1IMU_PCIE_HWID = 50 +L1IMU_NBIF_HWID = 51 +L1IMU_IOAGR_HWID = 52 +L1IMU3_HWID = 53 +L1IMU4_HWID = 54 +L1IMU5_HWID = 55 +L1IMU6_HWID = 56 +L1IMU7_HWID = 57 +L1IMU8_HWID = 58 +L1IMU9_HWID = 59 +L1IMU10_HWID = 60 +L1IMU11_HWID = 61 +L1IMU12_HWID = 62 +L1IMU13_HWID = 63 +L1IMU14_HWID = 64 +L1IMU15_HWID = 65 +WAFLC_HWID = 66 +FCH_USB_PD_HWID = 67 +SDMA2_HWID = 68 +SDMA3_HWID = 69 +PCIE_HWID = 70 +PCS_HWID = 80 +DDCL_HWID = 89 +SST_HWID = 90 +LSDMA_HWID = 91 +IOAGR_HWID = 100 +NBIF_HWID = 108 +IOAPIC_HWID = 124 +SYSTEMHUB_HWID = 128 +NTBCCP_HWID = 144 +UMC_HWID = 150 +SATA_HWID = 168 +USB_HWID = 170 +CCXSEC_HWID = 176 +XGMI_HWID = 200 +XGBE_HWID = 216 +MP0_HWID = 255 +hw_id_map = {GC_HWIP:GC_HWID,HDP_HWIP:HDP_HWID,SDMA0_HWIP:SDMA0_HWID,SDMA1_HWIP:SDMA1_HWID,SDMA2_HWIP:SDMA2_HWID,SDMA3_HWIP:SDMA3_HWID,LSDMA_HWIP:LSDMA_HWID,MMHUB_HWIP:MMHUB_HWID,ATHUB_HWIP:ATHUB_HWID,NBIO_HWIP:NBIF_HWID,MP0_HWIP:MP0_HWID,MP1_HWIP:MP1_HWID,UVD_HWIP:UVD_HWID,VCE_HWIP:VCE_HWID,DF_HWIP:DF_HWID,DCE_HWIP:DMU_HWID,OSSSYS_HWIP:OSSSYS_HWID,SMUIO_HWIP:SMUIO_HWID,PWR_HWIP:PWR_HWID,NBIF_HWIP:NBIF_HWID,THM_HWIP:THM_HWID,CLK_HWIP:CLKA_HWID,UMC_HWIP:UMC_HWID,XGMI_HWIP:XGMI_HWID,DCI_HWIP:DCI_HWID,PCIE_HWIP:PCIE_HWID,VPE_HWIP:VPE_HWID,ISP_HWIP:ISP_HWID} +int32_t = int +AMDGPU_SDMA0_UCODE_LOADED = 0x00000001 +AMDGPU_SDMA1_UCODE_LOADED = 0x00000002 +AMDGPU_CPCE_UCODE_LOADED = 0x00000004 +AMDGPU_CPPFP_UCODE_LOADED = 0x00000008 +AMDGPU_CPME_UCODE_LOADED = 0x00000010 +AMDGPU_CPMEC1_UCODE_LOADED = 0x00000020 +AMDGPU_CPMEC2_UCODE_LOADED = 0x00000040 +AMDGPU_CPRLC_UCODE_LOADED = 0x00000100 +PSP_GFX_CMD_BUF_VERSION = 0x00000001 +GFX_CMD_STATUS_MASK = 0x0000FFFF +GFX_CMD_ID_MASK = 0x000F0000 +GFX_CMD_RESERVED_MASK = 0x7FF00000 +GFX_CMD_RESPONSE_MASK = 0x80000000 +C2PMSG_CMD_GFX_USB_PD_FW_VER = 0x2000000 +GFX_FLAG_RESPONSE = 0x80000000 +GFX_BUF_MAX_DESC = 64 +FRAME_TYPE_DESTROY = 1 +PSP_ERR_UNKNOWN_COMMAND = 0x00000100 +PSP_FENCE_BUFFER_SIZE = 0x1000 +PSP_CMD_BUFFER_SIZE = 0x1000 +PSP_1_MEG = 0x100000 +PSP_TMR_ALIGNMENT = 0x100000 +PSP_FW_NAME_LEN = 0x24 +AMDGPU_XGMI_MAX_CONNECTED_NODES = 64 +MEM_TRAIN_SYSTEM_SIGNATURE = 0x54534942 +GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES = 0x1000 +GDDR6_MEM_TRAINING_OFFSET = 0x8000 +BIST_MEM_TRAINING_ENCROACHED_SIZE = 0x2000000 +PSP_RUNTIME_DB_SIZE_IN_BYTES = 0x10000 +PSP_RUNTIME_DB_OFFSET = 0x100000 +PSP_RUNTIME_DB_COOKIE_ID = 0x0ed5 +PSP_RUNTIME_DB_VER_1 = 0x0100 +PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT = 0x40 +int32_t = int +AMDGPU_MAX_IRQ_SRC_ID = 0x100 +AMDGPU_MAX_IRQ_CLIENT_ID = 0x100 +AMDGPU_IRQ_CLIENTID_LEGACY = 0 +AMDGPU_IRQ_CLIENTID_MAX = SOC15_IH_CLIENTID_MAX +AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW = 4 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/pm4_nv.py b/tinygrad/runtime/autogen/am/pm4_nv.py index a12b11eb93..3112463e2e 100644 --- a/tinygrad/runtime/autogen/am/pm4_nv.py +++ b/tinygrad/runtime/autogen/am/pm4_nv.py @@ -1,964 +1,461 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class union_PM4_MES_TYPE_3_HEADER(ctypes.Union): pass +class _anonstruct0(Struct): pass +enum_mes_set_resources_queue_type_enum = CEnum(ctypes.c_uint32) +queue_type__mes_set_resources__kernel_interface_queue_kiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__kernel_interface_queue_kiq', 0) +queue_type__mes_set_resources__hsa_interface_queue_hiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_interface_queue_hiq', 1) +queue_type__mes_set_resources__hsa_debug_interface_queue = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_debug_interface_queue', 4) +class struct_pm4_mes_set_resources(Struct): pass +class _anonunion1(ctypes.Union): pass +class _anonunion2(ctypes.Union): pass +class _anonstruct3(Struct): pass +class _anonunion4(ctypes.Union): pass +class _anonstruct5(Struct): pass +class _anonunion6(ctypes.Union): pass +class _anonstruct7(Struct): pass +class struct_pm4_mes_runlist(Struct): pass +class _anonunion8(ctypes.Union): pass +class _anonunion9(ctypes.Union): pass +class _anonstruct10(Struct): pass +class _anonunion11(ctypes.Union): pass +class _anonstruct12(Struct): pass +class struct_pm4_mes_map_process(Struct): pass +class _anonunion13(ctypes.Union): pass +class _anonunion14(ctypes.Union): pass +class _anonstruct15(Struct): pass +class _anonunion16(ctypes.Union): pass +class _anonstruct17(Struct): pass +class struct_PM4_MES_MAP_PROCESS_VM(Struct): pass +class _anonunion18(ctypes.Union): pass +enum_mes_map_queues_queue_sel_enum = CEnum(ctypes.c_uint32) +queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_specified_queue_slots_vi', 0) +queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi', 1) -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result +enum_mes_map_queues_queue_type_enum = CEnum(ctypes.c_uint32) +queue_type__mes_map_queues__normal_compute_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__normal_compute_vi', 0) +queue_type__mes_map_queues__debug_interface_queue_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__debug_interface_queue_vi', 1) +queue_type__mes_map_queues__normal_latency_static_queue_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__normal_latency_static_queue_vi', 2) +queue_type__mes_map_queues__low_latency_static_queue_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__low_latency_static_queue_vi', 3) +enum_mes_map_queues_engine_sel_enum = CEnum(ctypes.c_uint32) +engine_sel__mes_map_queues__compute_vi = enum_mes_map_queues_engine_sel_enum.define('engine_sel__mes_map_queues__compute_vi', 0) +engine_sel__mes_map_queues__sdma0_vi = enum_mes_map_queues_engine_sel_enum.define('engine_sel__mes_map_queues__sdma0_vi', 2) +engine_sel__mes_map_queues__sdma1_vi = enum_mes_map_queues_engine_sel_enum.define('engine_sel__mes_map_queues__sdma1_vi', 3) -class Structure(ctypes.Structure, AsDictMixin): +enum_mes_map_queues_extended_engine_sel_enum = CEnum(ctypes.c_uint32) +extended_engine_sel__mes_map_queues__legacy_engine_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__legacy_engine_sel', 0) +extended_engine_sel__mes_map_queues__sdma0_to_7_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__sdma0_to_7_sel', 1) +extended_engine_sel__mes_map_queues__sdma8_to_15_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__sdma8_to_15_sel', 2) - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields +class struct_pm4_mes_map_queues(Struct): pass +class _anonunion19(ctypes.Union): pass +class _anonunion20(ctypes.Union): pass +class _anonstruct21(Struct): pass +class _anonunion22(ctypes.Union): pass +class _anonstruct23(Struct): pass +enum_mes_query_status_interrupt_sel_enum = CEnum(ctypes.c_uint32) +interrupt_sel__mes_query_status__completion_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__completion_status', 0) +interrupt_sel__mes_query_status__process_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__process_status', 1) +interrupt_sel__mes_query_status__queue_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__queue_status', 2) - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) +enum_mes_query_status_command_enum = CEnum(ctypes.c_uint32) +command__mes_query_status__interrupt_only = enum_mes_query_status_command_enum.define('command__mes_query_status__interrupt_only', 0) +command__mes_query_status__fence_only_immediate = enum_mes_query_status_command_enum.define('command__mes_query_status__fence_only_immediate', 1) +command__mes_query_status__fence_only_after_write_ack = enum_mes_query_status_command_enum.define('command__mes_query_status__fence_only_after_write_ack', 2) +command__mes_query_status__fence_wait_for_write_ack_send_interrupt = enum_mes_query_status_command_enum.define('command__mes_query_status__fence_wait_for_write_ack_send_interrupt', 3) - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () +enum_mes_query_status_engine_sel_enum = CEnum(ctypes.c_uint32) +engine_sel__mes_query_status__compute = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__compute', 0) +engine_sel__mes_query_status__sdma0_queue = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__sdma0_queue', 2) +engine_sel__mes_query_status__sdma1_queue = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__sdma1_queue', 3) - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None +class struct_pm4_mes_query_status(Struct): pass +class _anonunion24(ctypes.Union): pass +class _anonunion25(ctypes.Union): pass +class _anonstruct26(Struct): pass +class _anonunion27(ctypes.Union): pass +class _anonstruct28(Struct): pass +class _anonstruct29(Struct): pass +enum_mes_unmap_queues_action_enum = CEnum(ctypes.c_uint32) +action__mes_unmap_queues__preempt_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__preempt_queues', 0) +action__mes_unmap_queues__reset_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__reset_queues', 1) +action__mes_unmap_queues__disable_process_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__disable_process_queues', 2) +action__mes_unmap_queues__reserved = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__reserved', 3) - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) +enum_mes_unmap_queues_queue_sel_enum = CEnum(ctypes.c_uint32) +queue_sel__mes_unmap_queues__perform_request_on_specified_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__perform_request_on_specified_queues', 0) +queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__perform_request_on_pasid_queues', 1) +queue_sel__mes_unmap_queues__unmap_all_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__unmap_all_queues', 2) +queue_sel__mes_unmap_queues__unmap_all_non_static_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__unmap_all_non_static_queues', 3) +enum_mes_unmap_queues_engine_sel_enum = CEnum(ctypes.c_uint32) +engine_sel__mes_unmap_queues__compute = enum_mes_unmap_queues_engine_sel_enum.define('engine_sel__mes_unmap_queues__compute', 0) +engine_sel__mes_unmap_queues__sdma0 = enum_mes_unmap_queues_engine_sel_enum.define('engine_sel__mes_unmap_queues__sdma0', 2) +engine_sel__mes_unmap_queues__sdmal = enum_mes_unmap_queues_engine_sel_enum.define('engine_sel__mes_unmap_queues__sdmal', 3) -class Union(ctypes.Union, AsDictMixin): - pass +enum_mes_unmap_queues_extended_engine_sel_enum = CEnum(ctypes.c_uint32) +extended_engine_sel__mes_unmap_queues__legacy_engine_sel = enum_mes_unmap_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_unmap_queues__legacy_engine_sel', 0) +extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = enum_mes_unmap_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel', 1) +class struct_pm4_mes_unmap_queues(Struct): pass +class _anonunion30(ctypes.Union): pass +class _anonunion31(ctypes.Union): pass +class _anonstruct32(Struct): pass +class _anonunion33(ctypes.Union): pass +class _anonstruct34(Struct): pass +class _anonstruct35(Struct): pass +class _anonunion36(ctypes.Union): pass +class _anonstruct37(Struct): pass +class _anonunion38(ctypes.Union): pass +class _anonstruct39(Struct): pass +class _anonunion40(ctypes.Union): pass +class _anonstruct41(Struct): pass +enum_mec_release_mem_event_index_enum = CEnum(ctypes.c_uint32) +event_index__mec_release_mem__end_of_pipe = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__end_of_pipe', 5) +event_index__mec_release_mem__shader_done = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__shader_done', 6) +enum_mec_release_mem_cache_policy_enum = CEnum(ctypes.c_uint32) +cache_policy__mec_release_mem__lru = enum_mec_release_mem_cache_policy_enum.define('cache_policy__mec_release_mem__lru', 0) +cache_policy__mec_release_mem__stream = enum_mec_release_mem_cache_policy_enum.define('cache_policy__mec_release_mem__stream', 1) +enum_mec_release_mem_pq_exe_status_enum = CEnum(ctypes.c_uint32) +pq_exe_status__mec_release_mem__default = enum_mec_release_mem_pq_exe_status_enum.define('pq_exe_status__mec_release_mem__default', 0) +pq_exe_status__mec_release_mem__phase_update = enum_mec_release_mem_pq_exe_status_enum.define('pq_exe_status__mec_release_mem__phase_update', 1) +enum_mec_release_mem_dst_sel_enum = CEnum(ctypes.c_uint32) +dst_sel__mec_release_mem__memory_controller = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__memory_controller', 0) +dst_sel__mec_release_mem__tc_l2 = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__tc_l2', 1) +dst_sel__mec_release_mem__queue_write_pointer_register = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__queue_write_pointer_register', 2) +dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', 3) -F32_MES_PM4_PACKETS_H = True # macro -uint32_t = True # macro -int32_t = True # macro -PM4_MES_HEADER_DEFINED = True # macro -PM4_MEC_RELEASE_MEM_DEFINED = True # macro -PM4_MEC_WRITE_DATA_DEFINED = True # macro -class union_PM4_MES_TYPE_3_HEADER(Union): - pass +enum_mec_release_mem_int_sel_enum = CEnum(ctypes.c_uint32) +int_sel__mec_release_mem__none = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__none', 0) +int_sel__mec_release_mem__send_interrupt_only = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__send_interrupt_only', 1) +int_sel__mec_release_mem__send_interrupt_after_write_confirm = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__send_interrupt_after_write_confirm', 2) +int_sel__mec_release_mem__send_data_after_write_confirm = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__send_data_after_write_confirm', 3) +int_sel__mec_release_mem__unconditionally_send_int_ctxid = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__unconditionally_send_int_ctxid', 4) +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', 5) +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', 6) -class struct_PM4_MES_TYPE_3_HEADER_0(Structure): - pass +enum_mec_release_mem_data_sel_enum = CEnum(ctypes.c_uint32) +data_sel__mec_release_mem__none = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__none', 0) +data_sel__mec_release_mem__send_32_bit_low = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_32_bit_low', 1) +data_sel__mec_release_mem__send_64_bit_data = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_64_bit_data', 2) +data_sel__mec_release_mem__send_gpu_clock_counter = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_gpu_clock_counter', 3) +data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', 4) +data_sel__mec_release_mem__store_gds_data_to_memory = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__store_gds_data_to_memory', 5) -struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False -struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('opcode', ctypes.c_uint32, 8), - ('count', ctypes.c_uint32, 14), - ('type', ctypes.c_uint32, 2), +class struct_pm4_mec_release_mem(Struct): pass +class _anonunion42(ctypes.Union): pass +class _anonunion43(ctypes.Union): pass +class _anonstruct44(Struct): pass +class _anonunion45(ctypes.Union): pass +class _anonstruct46(Struct): pass +class _anonunion47(ctypes.Union): pass +class _anonstruct48(Struct): pass +class _anonstruct49(Struct): pass +class _anonunion50(ctypes.Union): pass +class _anonunion51(ctypes.Union): pass +class _anonstruct52(Struct): pass +class _anonunion53(ctypes.Union): pass +enum_WRITE_DATA_dst_sel_enum = CEnum(ctypes.c_uint32) +dst_sel___write_data__mem_mapped_register = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__mem_mapped_register', 0) +dst_sel___write_data__tc_l2 = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__tc_l2', 2) +dst_sel___write_data__gds = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__gds', 3) +dst_sel___write_data__memory = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__memory', 5) +dst_sel___write_data__memory_mapped_adc_persistent_state = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__memory_mapped_adc_persistent_state', 6) + +enum_WRITE_DATA_addr_incr_enum = CEnum(ctypes.c_uint32) +addr_incr___write_data__increment_address = enum_WRITE_DATA_addr_incr_enum.define('addr_incr___write_data__increment_address', 0) +addr_incr___write_data__do_not_increment_address = enum_WRITE_DATA_addr_incr_enum.define('addr_incr___write_data__do_not_increment_address', 1) + +enum_WRITE_DATA_wr_confirm_enum = CEnum(ctypes.c_uint32) +wr_confirm___write_data__do_not_wait_for_write_confirmation = enum_WRITE_DATA_wr_confirm_enum.define('wr_confirm___write_data__do_not_wait_for_write_confirmation', 0) +wr_confirm___write_data__wait_for_write_confirmation = enum_WRITE_DATA_wr_confirm_enum.define('wr_confirm___write_data__wait_for_write_confirmation', 1) + +enum_WRITE_DATA_cache_policy_enum = CEnum(ctypes.c_uint32) +cache_policy___write_data__lru = enum_WRITE_DATA_cache_policy_enum.define('cache_policy___write_data__lru', 0) +cache_policy___write_data__stream = enum_WRITE_DATA_cache_policy_enum.define('cache_policy___write_data__stream', 1) + +class struct_pm4_mec_write_data_mmio(Struct): pass +class _anonunion54(ctypes.Union): pass +class _anonunion55(ctypes.Union): pass +class _anonunion55_bitfields2(Struct): pass +_anonunion55_bitfields2._fields_ = [ + ('reserved1', ctypes.c_uint32,8), + ('dst_sel', ctypes.c_uint32,4), + ('reserved2', ctypes.c_uint32,4), + ('addr_incr', ctypes.c_uint32,1), + ('reserved3', ctypes.c_uint32,2), + ('resume_vf', ctypes.c_uint32,1), + ('wr_confirm', ctypes.c_uint32,1), + ('reserved4', ctypes.c_uint32,4), + ('cache_policy', ctypes.c_uint32,2), + ('reserved5', ctypes.c_uint32,5), ] - -union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False -union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) -union_PM4_MES_TYPE_3_HEADER._fields_ = [ - ('_0', struct_PM4_MES_TYPE_3_HEADER_0), - ('u32All', ctypes.c_uint32), +_anonunion55._fields_ = [ + ('bitfields2', _anonunion55_bitfields2), + ('ordinal2', ctypes.c_uint32), ] - - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 5: 'event_index__mec_release_mem__end_of_pipe', - 6: 'event_index__mec_release_mem__shader_done', -} -event_index__mec_release_mem__end_of_pipe = 5 -event_index__mec_release_mem__shader_done = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'cache_policy__mec_release_mem__lru', - 1: 'cache_policy__mec_release_mem__stream', -} -cache_policy__mec_release_mem__lru = 0 -cache_policy__mec_release_mem__stream = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'pq_exe_status__mec_release_mem__default', - 1: 'pq_exe_status__mec_release_mem__phase_update', -} -pq_exe_status__mec_release_mem__default = 0 -pq_exe_status__mec_release_mem__phase_update = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'dst_sel__mec_release_mem__memory_controller', - 1: 'dst_sel__mec_release_mem__tc_l2', - 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', - 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', -} -dst_sel__mec_release_mem__memory_controller = 0 -dst_sel__mec_release_mem__tc_l2 = 1 -dst_sel__mec_release_mem__queue_write_pointer_register = 2 -dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'int_sel__mec_release_mem__none', - 1: 'int_sel__mec_release_mem__send_interrupt_only', - 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', - 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', -} -int_sel__mec_release_mem__none = 0 -int_sel__mec_release_mem__send_interrupt_only = 1 -int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 -int_sel__mec_release_mem__send_data_after_write_confirm = 3 -int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'data_sel__mec_release_mem__none', - 1: 'data_sel__mec_release_mem__send_32_bit_low', - 2: 'data_sel__mec_release_mem__send_64_bit_data', - 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', - 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', -} -data_sel__mec_release_mem__none = 0 -data_sel__mec_release_mem__send_32_bit_low = 1 -data_sel__mec_release_mem__send_64_bit_data = 2 -data_sel__mec_release_mem__send_gpu_clock_counter = 3 -data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 -data_sel__mec_release_mem__store_gds_data_to_memory = 5 -c_uint32 = ctypes.c_uint32 # enum -class struct_pm4_mec_release_mem(Structure): - pass - -class union_pm4_mec_release_mem_0(Union): - pass - -union_pm4_mec_release_mem_0._pack_ = 1 # source:False -union_pm4_mec_release_mem_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), +class _anonunion56(ctypes.Union): pass +class _anonunion56_bitfields3(Struct): pass +_anonunion56_bitfields3._fields_ = [ + ('dst_mmreg_addr', ctypes.c_uint32,18), + ('reserved6', ctypes.c_uint32,14), ] - -class union_pm4_mec_release_mem_1(Union): - pass - -class struct_pm4_mec_release_mem_1_bitfields2(Structure): - pass - -struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ - ('event_type', ctypes.c_uint32, 6), - ('reserved1', ctypes.c_uint32, 2), - ('event_index', c_uint32, 4), - ('tcl1_vol_action_ena', ctypes.c_uint32, 1), - ('tc_vol_action_ena', ctypes.c_uint32, 1), - ('reserved2', ctypes.c_uint32, 1), - ('tc_wb_action_ena', ctypes.c_uint32, 1), - ('tcl1_action_ena', ctypes.c_uint32, 1), - ('tc_action_ena', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 1), - ('tc_nc_action_ena', ctypes.c_uint32, 1), - ('tc_wc_action_ena', ctypes.c_uint32, 1), - ('tc_md_action_ena', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 3), - ('cache_policy', c_uint32, 2), - ('reserved5', ctypes.c_uint32, 2), - ('pq_exe_status', c_uint32, 1), - ('reserved6', ctypes.c_uint32, 2), +_anonunion56._fields_ = [ + ('bitfields3', _anonunion56_bitfields3), + ('ordinal3', ctypes.c_uint32), ] +_anonenum57 = CEnum(ctypes.c_uint32) +CACHE_FLUSH_AND_INV_TS_EVENT = _anonenum57.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) -union_pm4_mec_release_mem_1._pack_ = 1 # source:False -union_pm4_mec_release_mem_1._fields_ = [ - ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_2(Union): - pass - -class struct_pm4_mec_release_mem_2_bitfields3(Structure): - pass - -struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ - ('reserved7', ctypes.c_uint32, 16), - ('dst_sel', c_uint32, 2), - ('reserved8', ctypes.c_uint32, 6), - ('int_sel', c_uint32, 3), - ('reserved9', ctypes.c_uint32, 2), - ('data_sel', c_uint32, 3), -] - -union_pm4_mec_release_mem_2._pack_ = 1 # source:False -union_pm4_mec_release_mem_2._fields_ = [ - ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_3(Union): - pass - -class struct_pm4_mec_release_mem_3_bitfields4(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ - ('reserved10', ctypes.c_uint32, 2), - ('address_lo_32b', ctypes.c_uint32, 30), -] - -class struct_pm4_mec_release_mem_3_bitfields4b(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ - ('reserved11', ctypes.c_uint32, 3), - ('address_lo_64b', ctypes.c_uint32, 29), -] - -union_pm4_mec_release_mem_3._pack_ = 1 # source:False -union_pm4_mec_release_mem_3._fields_ = [ - ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), - ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), - ('reserved12', ctypes.c_uint32), - ('ordinal4', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_4(Union): - pass - -union_pm4_mec_release_mem_4._pack_ = 1 # source:False -union_pm4_mec_release_mem_4._fields_ = [ - ('address_hi', ctypes.c_uint32), - ('reserved13', ctypes.c_uint32), - ('ordinal5', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_5(Union): - pass - -class struct_pm4_mec_release_mem_5_bitfields6c(Structure): - pass - -struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False -struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ - ('dw_offset', ctypes.c_uint32, 16), - ('num_dwords', ctypes.c_uint32, 16), -] - -union_pm4_mec_release_mem_5._pack_ = 1 # source:False -union_pm4_mec_release_mem_5._fields_ = [ - ('data_lo', ctypes.c_uint32), - ('cmp_data_lo', ctypes.c_uint32), - ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), - ('reserved14', ctypes.c_uint32), - ('ordinal6', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_6(Union): - pass - -union_pm4_mec_release_mem_6._pack_ = 1 # source:False -union_pm4_mec_release_mem_6._fields_ = [ - ('data_hi', ctypes.c_uint32), - ('cmp_data_hi', ctypes.c_uint32), - ('reserved15', ctypes.c_uint32), - ('reserved16', ctypes.c_uint32), - ('ordinal7', ctypes.c_uint32), -] - -struct_pm4_mec_release_mem._pack_ = 1 # source:False -struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) -struct_pm4_mec_release_mem._fields_ = [ - ('_0', union_pm4_mec_release_mem_0), - ('_1', union_pm4_mec_release_mem_1), - ('_2', union_pm4_mec_release_mem_2), - ('_3', union_pm4_mec_release_mem_3), - ('_4', union_pm4_mec_release_mem_4), - ('_5', union_pm4_mec_release_mem_5), - ('_6', union_pm4_mec_release_mem_6), - ('int_ctxid', ctypes.c_uint32), -] - - -# values for enumeration 'WRITE_DATA_dst_sel_enum' -WRITE_DATA_dst_sel_enum__enumvalues = { - 0: 'dst_sel___write_data__mem_mapped_register', - 2: 'dst_sel___write_data__tc_l2', - 3: 'dst_sel___write_data__gds', - 5: 'dst_sel___write_data__memory', - 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', -} -dst_sel___write_data__mem_mapped_register = 0 -dst_sel___write_data__tc_l2 = 2 -dst_sel___write_data__gds = 3 -dst_sel___write_data__memory = 5 -dst_sel___write_data__memory_mapped_adc_persistent_state = 6 -WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_addr_incr_enum' -WRITE_DATA_addr_incr_enum__enumvalues = { - 0: 'addr_incr___write_data__increment_address', - 1: 'addr_incr___write_data__do_not_increment_address', -} -addr_incr___write_data__increment_address = 0 -addr_incr___write_data__do_not_increment_address = 1 -WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_wr_confirm_enum' -WRITE_DATA_wr_confirm_enum__enumvalues = { - 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 1: 'wr_confirm___write_data__wait_for_write_confirmation', -} -wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 -wr_confirm___write_data__wait_for_write_confirmation = 1 -WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_cache_policy_enum' -WRITE_DATA_cache_policy_enum__enumvalues = { - 0: 'cache_policy___write_data__lru', - 1: 'cache_policy___write_data__stream', -} -cache_policy___write_data__lru = 0 -cache_policy___write_data__stream = 1 -WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum -class struct_pm4_mec_write_data_mmio(Structure): - pass - -class union_pm4_mec_write_data_mmio_0(Union): - pass - -union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_1(Union): - pass - -class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): - pass - -struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('dst_sel', ctypes.c_uint32, 4), - ('reserved2', ctypes.c_uint32, 4), - ('addr_incr', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 2), - ('resume_vf', ctypes.c_uint32, 1), - ('wr_confirm', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 4), - ('cache_policy', ctypes.c_uint32, 2), - ('reserved5', ctypes.c_uint32, 5), -] - -union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_1._fields_ = [ - ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_2(Union): - pass - -class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): - pass - -struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ - ('dst_mmreg_addr', ctypes.c_uint32, 18), - ('reserved6', ctypes.c_uint32, 14), -] - -union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_2._fields_ = [ - ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) -struct_pm4_mec_write_data_mmio._fields_ = [ - ('_0', union_pm4_mec_write_data_mmio_0), - ('_1', union_pm4_mec_write_data_mmio_1), - ('_2', union_pm4_mec_write_data_mmio_2), - ('reserved7', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', -} -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum -NVD_H = True # macro -PACKET_TYPE0 = 0 # macro -PACKET_TYPE1 = 1 # macro -PACKET_TYPE2 = 2 # macro -PACKET_TYPE3 = 3 # macro -def CP_PACKET_GET_TYPE(h): # macro - return (((h)>>30)&3) -def CP_PACKET_GET_COUNT(h): # macro - return (((h)>>16)&0x3FFF) -def CP_PACKET0_GET_REG(h): # macro - return ((h)&0xFFFF) -def CP_PACKET3_GET_OPCODE(h): # macro - return (((h)>>8)&0xFF) -def PACKET0(reg, n): # macro - return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) -CP_PACKET2 = 0x80000000 # macro -PACKET2_PAD_SHIFT = 0 # macro -PACKET2_PAD_MASK = (0x3fffffff<<0) # macro -# def PACKET2(v): # macro -# return (0x80000000|REG_SET(PACKET2_PAD,(v))) -def PACKET3(op, n): # macro - return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) -def PACKET3_COMPUTE(op, n): # macro - return (PACKET3(op,n)|1<<1) -PACKET3_NOP = 0x10 # macro -PACKET3_SET_BASE = 0x11 # macro -def PACKET3_BASE_INDEX(x): # macro - return ((x)<<0) -CE_PARTITION_BASE = 3 # macro -PACKET3_CLEAR_STATE = 0x12 # macro -PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro -PACKET3_DISPATCH_DIRECT = 0x15 # macro -PACKET3_DISPATCH_INDIRECT = 0x16 # macro -PACKET3_INDIRECT_BUFFER_END = 0x17 # macro -PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 # macro -PACKET3_ATOMIC_GDS = 0x1D # macro -PACKET3_ATOMIC_MEM = 0x1E # macro -PACKET3_OCCLUSION_QUERY = 0x1F # macro -PACKET3_SET_PREDICATION = 0x20 # macro -PACKET3_REG_RMW = 0x21 # macro -PACKET3_COND_EXEC = 0x22 # macro -PACKET3_PRED_EXEC = 0x23 # macro -PACKET3_DRAW_INDIRECT = 0x24 # macro -PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro -PACKET3_INDEX_BASE = 0x26 # macro -PACKET3_DRAW_INDEX_2 = 0x27 # macro -PACKET3_CONTEXT_CONTROL = 0x28 # macro -PACKET3_INDEX_TYPE = 0x2A # macro -PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro -PACKET3_DRAW_INDEX_AUTO = 0x2D # macro -PACKET3_NUM_INSTANCES = 0x2F # macro -PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro -PACKET3_INDIRECT_BUFFER_PRIV = 0x32 # macro -PACKET3_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro -PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro -PACKET3_DRAW_PREAMBLE = 0x36 # macro -PACKET3_WRITE_DATA = 0x37 # macro -def WRITE_DATA_DST_SEL(x): # macro - return ((x)<<8) -WR_ONE_ADDR = (1<<16) # macro -WR_CONFIRM = (1<<20) # macro -def WRITE_DATA_CACHE_POLICY(x): # macro - return ((x)<<25) -def WRITE_DATA_ENGINE_SEL(x): # macro - return ((x)<<30) -PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro -PACKET3_MEM_SEMAPHORE = 0x39 # macro -PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro -PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro -PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro -PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro -PACKET3_DRAW_INDEX_MULTI_INST = 0x3A # macro -PACKET3_COPY_DW = 0x3B # macro -PACKET3_WAIT_REG_MEM = 0x3C # macro -def WAIT_REG_MEM_FUNCTION(x): # macro - return ((x)<<0) -def WAIT_REG_MEM_MEM_SPACE(x): # macro - return ((x)<<4) -def WAIT_REG_MEM_OPERATION(x): # macro - return ((x)<<6) -def WAIT_REG_MEM_ENGINE(x): # macro - return ((x)<<8) -PACKET3_INDIRECT_BUFFER = 0x3F # macro -INDIRECT_BUFFER_VALID = (1<<23) # macro -def INDIRECT_BUFFER_CACHE_POLICY(x): # macro - return ((x)<<28) -def INDIRECT_BUFFER_PRE_ENB(x): # macro - return ((x)<<21) -def INDIRECT_BUFFER_PRE_RESUME(x): # macro - return ((x)<<30) -PACKET3_COND_INDIRECT_BUFFER = 0x3F # macro -PACKET3_COPY_DATA = 0x40 # macro -PACKET3_CP_DMA = 0x41 # macro -PACKET3_PFP_SYNC_ME = 0x42 # macro -PACKET3_SURFACE_SYNC = 0x43 # macro -PACKET3_ME_INITIALIZE = 0x44 # macro -PACKET3_COND_WRITE = 0x45 # macro -PACKET3_EVENT_WRITE = 0x46 # macro -def EVENT_TYPE(x): # macro - return ((x)<<0) -def EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_EVENT_WRITE_EOP = 0x47 # macro -PACKET3_EVENT_WRITE_EOS = 0x48 # macro -PACKET3_RELEASE_MEM = 0x49 # macro -def PACKET3_RELEASE_MEM_EVENT_TYPE(x): # macro - return ((x)<<0) -def PACKET3_RELEASE_MEM_EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_RELEASE_MEM_GCR_GLM_WB = (1<<12) # macro -PACKET3_RELEASE_MEM_GCR_GLM_INV = (1<<13) # macro -PACKET3_RELEASE_MEM_GCR_GLV_INV = (1<<14) # macro -PACKET3_RELEASE_MEM_GCR_GL1_INV = (1<<15) # macro -PACKET3_RELEASE_MEM_GCR_GL2_US = (1<<16) # macro -PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1<<17) # macro -PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1<<19) # macro -PACKET3_RELEASE_MEM_GCR_GL2_INV = (1<<20) # macro -PACKET3_RELEASE_MEM_GCR_GL2_WB = (1<<21) # macro -PACKET3_RELEASE_MEM_GCR_SEQ = (1<<22) # macro -def PACKET3_RELEASE_MEM_CACHE_POLICY(x): # macro - return ((x)<<25) -PACKET3_RELEASE_MEM_EXECUTE = (1<<28) # macro -def PACKET3_RELEASE_MEM_DATA_SEL(x): # macro - return ((x)<<29) -def PACKET3_RELEASE_MEM_INT_SEL(x): # macro - return ((x)<<24) -def PACKET3_RELEASE_MEM_DST_SEL(x): # macro - return ((x)<<16) -PACKET3_PREAMBLE_CNTL = 0x4A # macro -PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro -PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro -PACKET3_DMA_DATA = 0x50 # macro -def PACKET3_DMA_DATA_ENGINE(x): # macro - return ((x)<<0) -def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro - return ((x)<<13) -def PACKET3_DMA_DATA_DST_SEL(x): # macro - return ((x)<<20) -def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro - return ((x)<<25) -def PACKET3_DMA_DATA_SRC_SEL(x): # macro - return ((x)<<29) -PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro -PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro -PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro -PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro -PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro -PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro -PACKET3_CONTEXT_REG_RMW = 0x51 # macro -PACKET3_GFX_CNTX_UPDATE = 0x52 # macro -PACKET3_BLK_CNTX_UPDATE = 0x53 # macro -PACKET3_INCR_UPDT_STATE = 0x55 # macro -PACKET3_ACQUIRE_MEM = 0x58 # macro -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x): # macro - return ((x)<<0) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x): # macro - return ((x)<<2) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x): # macro - return ((x)<<4) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x): # macro - return ((x)<<5) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x): # macro - return ((x)<<6) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x): # macro - return ((x)<<7) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x): # macro - return ((x)<<8) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x): # macro - return ((x)<<9) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x): # macro - return ((x)<<10) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x): # macro - return ((x)<<11) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x): # macro - return ((x)<<13) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x): # macro - return ((x)<<14) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x): # macro - return ((x)<<15) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x): # macro - return ((x)<<16) -PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1<<18) # macro -PACKET3_REWIND = 0x59 # macro -PACKET3_INTERRUPT = 0x5A # macro -PACKET3_GEN_PDEPTE = 0x5B # macro -PACKET3_INDIRECT_BUFFER_PASID = 0x5C # macro -PACKET3_PRIME_UTCL2 = 0x5D # macro -PACKET3_LOAD_UCONFIG_REG = 0x5E # macro -PACKET3_LOAD_SH_REG = 0x5F # macro -PACKET3_LOAD_CONFIG_REG = 0x60 # macro -PACKET3_LOAD_CONTEXT_REG = 0x61 # macro -PACKET3_LOAD_COMPUTE_STATE = 0x62 # macro -PACKET3_LOAD_SH_REG_INDEX = 0x63 # macro -PACKET3_SET_CONFIG_REG = 0x68 # macro -PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro -PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro -PACKET3_SET_CONTEXT_REG = 0x69 # macro -PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro -PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro -PACKET3_SET_CONTEXT_REG_INDEX = 0x6A # macro -PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 # macro -PACKET3_SET_SH_REG_DI = 0x72 # macro -PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro -PACKET3_SET_SH_REG_DI_MULTI = 0x74 # macro -PACKET3_GFX_PIPE_LOCK = 0x75 # macro -PACKET3_SET_SH_REG = 0x76 # macro -PACKET3_SET_SH_REG_START = 0x00002c00 # macro -PACKET3_SET_SH_REG_END = 0x00003000 # macro -PACKET3_SET_SH_REG_OFFSET = 0x77 # macro -PACKET3_SET_QUEUE_REG = 0x78 # macro -PACKET3_SET_UCONFIG_REG = 0x79 # macro -PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro -PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro -PACKET3_SET_UCONFIG_REG_INDEX = 0x7A # macro -PACKET3_FORWARD_HEADER = 0x7C # macro -PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro -PACKET3_SCRATCH_RAM_READ = 0x7E # macro -PACKET3_LOAD_CONST_RAM = 0x80 # macro -PACKET3_WRITE_CONST_RAM = 0x81 # macro -PACKET3_DUMP_CONST_RAM = 0x83 # macro -PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro -PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro -PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro -PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro -PACKET3_SWITCH_BUFFER = 0x8B # macro -PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C # macro -PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C # macro -PACKET3_DISPATCH_DRAW = 0x8D # macro -PACKET3_DISPATCH_DRAW_ACE = 0x8D # macro -PACKET3_GET_LOD_STATS = 0x8E # macro -PACKET3_DRAW_MULTI_PREAMBLE = 0x8F # macro -PACKET3_FRAME_CONTROL = 0x90 # macro -FRAME_TMZ = (1<<0) # macro -def FRAME_CMD(x): # macro - return ((x)<<28) -PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 # macro -PACKET3_WAIT_REG_MEM64 = 0x93 # macro -PACKET3_COND_PREEMPT = 0x94 # macro -PACKET3_HDP_FLUSH = 0x95 # macro -PACKET3_COPY_DATA_RB = 0x96 # macro -PACKET3_INVALIDATE_TLBS = 0x98 # macro -def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro - return ((x)<<0) -def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro - return ((x)<<4) -def PACKET3_INVALIDATE_TLBS_PASID(x): # macro - return ((x)<<5) -PACKET3_AQL_PACKET = 0x99 # macro -PACKET3_DMA_DATA_FILL_MULTI = 0x9A # macro -PACKET3_SET_SH_REG_INDEX = 0x9B # macro -PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C # macro -PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D # macro -PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E # macro -PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F # macro -PACKET3_SET_RESOURCES = 0xA0 # macro -def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro - return ((x)<<0) -def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro - return ((x)<<16) -def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro - return ((x)<<29) -PACKET3_MAP_PROCESS = 0xA1 # macro -PACKET3_MAP_QUEUES = 0xA2 # macro -def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_MAP_QUEUES_VMID(x): # macro - return ((x)<<8) -def PACKET3_MAP_QUEUES_QUEUE(x): # macro - return ((x)<<13) -def PACKET3_MAP_QUEUES_PIPE(x): # macro - return ((x)<<16) -def PACKET3_MAP_QUEUES_ME(x): # macro - return ((x)<<18) -def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro - return ((x)<<21) -def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro - return ((x)<<24) -def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro - return ((x)<<1) -def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -PACKET3_UNMAP_QUEUES = 0xA3 # macro -def PACKET3_UNMAP_QUEUES_ACTION(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_UNMAP_QUEUES_PASID(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro - return ((x)<<2) -PACKET3_QUERY_STATUS = 0xA4 # macro -def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro - return ((x)<<28) -def PACKET3_QUERY_STATUS_COMMAND(x): # macro - return ((x)<<30) -def PACKET3_QUERY_STATUS_PASID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro - return ((x)<<25) -PACKET3_RUN_LIST = 0xA5 # macro -PACKET3_MAP_PROCESS_VM = 0xA6 # macro -PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro -def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro - return ((x)<<0) -PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro -__all__ = \ - ['CACHE_FLUSH_AND_INV_TS_EVENT', 'CE_PARTITION_BASE', - 'CP_PACKET2', 'F32_MES_PM4_PACKETS_H', 'FRAME_TMZ', - 'INDIRECT_BUFFER_VALID', 'NVD_H', 'PACKET2_PAD_MASK', - 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', - 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', 'PACKET3_AQL_PACKET', - 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM', - 'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE', - 'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER', - 'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT', - 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', - 'PACKET3_CONTEXT_REG_RMW', 'PACKET3_COPY_DATA', - 'PACKET3_COPY_DATA_RB', 'PACKET3_COPY_DW', 'PACKET3_CP_DMA', - 'PACKET3_DISPATCH_DIRECT', 'PACKET3_DISPATCH_DRAW', - 'PACKET3_DISPATCH_DRAW_ACE', 'PACKET3_DISPATCH_DRAW_PREAMBLE', - 'PACKET3_DISPATCH_DRAW_PREAMBLE_ACE', 'PACKET3_DISPATCH_INDIRECT', - 'PACKET3_DMA_DATA', 'PACKET3_DMA_DATA_CMD_DAIC', - 'PACKET3_DMA_DATA_CMD_DAS', 'PACKET3_DMA_DATA_CMD_RAW_WAIT', - 'PACKET3_DMA_DATA_CMD_SAIC', 'PACKET3_DMA_DATA_CMD_SAS', - 'PACKET3_DMA_DATA_CP_SYNC', 'PACKET3_DMA_DATA_FILL_MULTI', - 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', - 'PACKET3_DRAW_INDEX_INDIRECT', - 'PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', - 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_MULTI_INST', - 'PACKET3_DRAW_INDEX_OFFSET_2', 'PACKET3_DRAW_INDIRECT', - 'PACKET3_DRAW_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDIRECT_MULTI', 'PACKET3_DRAW_MULTI_PREAMBLE', - 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', - 'PACKET3_DUMP_CONST_RAM_OFFSET', 'PACKET3_EVENT_WRITE', - 'PACKET3_EVENT_WRITE_EOP', 'PACKET3_EVENT_WRITE_EOS', - 'PACKET3_FORWARD_HEADER', 'PACKET3_FRAME_CONTROL', - 'PACKET3_GEN_PDEPTE', 'PACKET3_GET_LOD_STATS', - 'PACKET3_GFX_CNTX_UPDATE', 'PACKET3_GFX_PIPE_LOCK', - 'PACKET3_HDP_FLUSH', 'PACKET3_INCREMENT_CE_COUNTER', - 'PACKET3_INCREMENT_DE_COUNTER', 'PACKET3_INCR_UPDT_STATE', - 'PACKET3_INDEX_ATTRIBUTES_INDIRECT', 'PACKET3_INDEX_BASE', - 'PACKET3_INDEX_BUFFER_SIZE', 'PACKET3_INDEX_TYPE', - 'PACKET3_INDIRECT_BUFFER', 'PACKET3_INDIRECT_BUFFER_CNST', - 'PACKET3_INDIRECT_BUFFER_CNST_END', 'PACKET3_INDIRECT_BUFFER_END', - 'PACKET3_INDIRECT_BUFFER_PASID', 'PACKET3_INDIRECT_BUFFER_PRIV', - 'PACKET3_INTERRUPT', 'PACKET3_INVALIDATE_TLBS', - 'PACKET3_LOAD_COMPUTE_STATE', 'PACKET3_LOAD_CONFIG_REG', - 'PACKET3_LOAD_CONST_RAM', 'PACKET3_LOAD_CONTEXT_REG', - 'PACKET3_LOAD_CONTEXT_REG_INDEX', 'PACKET3_LOAD_SH_REG', - 'PACKET3_LOAD_SH_REG_INDEX', 'PACKET3_LOAD_UCONFIG_REG', - 'PACKET3_MAP_PROCESS', 'PACKET3_MAP_PROCESS_VM', - 'PACKET3_MAP_QUEUES', 'PACKET3_MEM_SEMAPHORE', - 'PACKET3_ME_INITIALIZE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', - 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', - 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', - 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', - 'PACKET3_PRIME_UTCL2', 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', - 'PACKET3_RELEASE_MEM', 'PACKET3_RELEASE_MEM_EXECUTE', - 'PACKET3_RELEASE_MEM_GCR_GL1_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_DISCARD', - 'PACKET3_RELEASE_MEM_GCR_GL2_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_RANGE', - 'PACKET3_RELEASE_MEM_GCR_GL2_US', - 'PACKET3_RELEASE_MEM_GCR_GL2_WB', - 'PACKET3_RELEASE_MEM_GCR_GLM_INV', - 'PACKET3_RELEASE_MEM_GCR_GLM_WB', - 'PACKET3_RELEASE_MEM_GCR_GLV_INV', 'PACKET3_RELEASE_MEM_GCR_SEQ', - 'PACKET3_REWIND', 'PACKET3_RUN_LIST', 'PACKET3_SCRATCH_RAM_READ', - 'PACKET3_SCRATCH_RAM_WRITE', 'PACKET3_SEM_SEL_SIGNAL', - 'PACKET3_SEM_SEL_SIGNAL_TYPE', 'PACKET3_SEM_SEL_WAIT', - 'PACKET3_SEM_USE_MAILBOX', 'PACKET3_SET_BASE', - 'PACKET3_SET_CONFIG_REG', 'PACKET3_SET_CONFIG_REG_END', - 'PACKET3_SET_CONFIG_REG_START', 'PACKET3_SET_CONTEXT_REG', - 'PACKET3_SET_CONTEXT_REG_END', 'PACKET3_SET_CONTEXT_REG_INDEX', - 'PACKET3_SET_CONTEXT_REG_INDIRECT', - 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', - 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_Q_PREEMPTION_MODE', - 'PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM', - 'PACKET3_SET_RESOURCES', 'PACKET3_SET_SH_REG', - 'PACKET3_SET_SH_REG_DI', 'PACKET3_SET_SH_REG_DI_MULTI', - 'PACKET3_SET_SH_REG_END', 'PACKET3_SET_SH_REG_INDEX', - 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', - 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', - 'PACKET3_SET_UCONFIG_REG_INDEX', 'PACKET3_SET_UCONFIG_REG_START', - 'PACKET3_SET_VGPR_REG_DI_MULTI', 'PACKET3_STRMOUT_BUFFER_UPDATE', - 'PACKET3_SURFACE_SYNC', 'PACKET3_SWITCH_BUFFER', - 'PACKET3_UNMAP_QUEUES', 'PACKET3_WAIT_ON_CE_COUNTER', - 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM', - 'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM', - 'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1', - 'PACKET_TYPE2', 'PACKET_TYPE3', 'PM4_MEC_RELEASE_MEM_DEFINED', - 'PM4_MEC_WRITE_DATA_DEFINED', 'PM4_MES_HEADER_DEFINED', - 'WRITE_DATA_addr_incr_enum', 'WRITE_DATA_cache_policy_enum', - 'WRITE_DATA_dst_sel_enum', 'WRITE_DATA_wr_confirm_enum', - 'WR_CONFIRM', 'WR_ONE_ADDR', - 'addr_incr___write_data__do_not_increment_address', - 'addr_incr___write_data__increment_address', - 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', - 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', - 'cache_policy___write_data__lru', - 'cache_policy___write_data__stream', - 'cache_policy__mec_release_mem__lru', - 'cache_policy__mec_release_mem__stream', - 'data_sel__mec_release_mem__none', - 'data_sel__mec_release_mem__send_32_bit_low', - 'data_sel__mec_release_mem__send_64_bit_data', - 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 'data_sel__mec_release_mem__send_gpu_clock_counter', - 'data_sel__mec_release_mem__store_gds_data_to_memory', - 'dst_sel___write_data__gds', - 'dst_sel___write_data__mem_mapped_register', - 'dst_sel___write_data__memory', - 'dst_sel___write_data__memory_mapped_adc_persistent_state', - 'dst_sel___write_data__tc_l2', - 'dst_sel__mec_release_mem__memory_controller', - 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', - 'dst_sel__mec_release_mem__queue_write_pointer_register', - 'dst_sel__mec_release_mem__tc_l2', - 'event_index__mec_release_mem__end_of_pipe', - 'event_index__mec_release_mem__shader_done', 'int32_t', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', - 'int_sel__mec_release_mem__none', - 'int_sel__mec_release_mem__send_data_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_only', - 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 'pq_exe_status__mec_release_mem__default', - 'pq_exe_status__mec_release_mem__phase_update', - 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_pm4_mec_release_mem', - 'struct_pm4_mec_release_mem_1_bitfields2', - 'struct_pm4_mec_release_mem_2_bitfields3', - 'struct_pm4_mec_release_mem_3_bitfields4', - 'struct_pm4_mec_release_mem_3_bitfields4b', - 'struct_pm4_mec_release_mem_5_bitfields6c', - 'struct_pm4_mec_write_data_mmio', - 'struct_pm4_mec_write_data_mmio_1_bitfields2', - 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', - 'union_PM4_MES_TYPE_3_HEADER', 'union_pm4_mec_release_mem_0', - 'union_pm4_mec_release_mem_1', 'union_pm4_mec_release_mem_2', - 'union_pm4_mec_release_mem_3', 'union_pm4_mec_release_mem_4', - 'union_pm4_mec_release_mem_5', 'union_pm4_mec_release_mem_6', - 'union_pm4_mec_write_data_mmio_0', - 'union_pm4_mec_write_data_mmio_1', - 'union_pm4_mec_write_data_mmio_2', - 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 'wr_confirm___write_data__wait_for_write_confirmation'] +PACKET_TYPE0 = 0 +PACKET_TYPE1 = 1 +PACKET_TYPE2 = 2 +PACKET_TYPE3 = 3 +CP_PACKET_GET_TYPE = lambda h: (((h) >> 30) & 3) +CP_PACKET_GET_COUNT = lambda h: (((h) >> 16) & 0x3FFF) +CP_PACKET0_GET_REG = lambda h: ((h) & 0xFFFF) +CP_PACKET3_GET_OPCODE = lambda h: (((h) >> 8) & 0xFF) +PACKET0 = lambda reg,n: ((PACKET_TYPE0 << 30) | ((reg) & 0xFFFF) | ((n) & 0x3FFF) << 16) +CP_PACKET2 = 0x80000000 +PACKET2_PAD_SHIFT = 0 +PACKET2_PAD_MASK = (0x3fffffff << 0) +PACKET2 = lambda v: (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +PACKET3 = lambda op,n: ((PACKET_TYPE3 << 30) | (((op) & 0xFF) << 8) | ((n) & 0x3FFF) << 16) +PACKET3_COMPUTE = lambda op,n: (PACKET3(op, n) | 1 << 1) +PACKET3_NOP = 0x10 +PACKET3_SET_BASE = 0x11 +PACKET3_BASE_INDEX = lambda x: ((x) << 0) +CE_PARTITION_BASE = 3 +PACKET3_CLEAR_STATE = 0x12 +PACKET3_INDEX_BUFFER_SIZE = 0x13 +PACKET3_DISPATCH_DIRECT = 0x15 +PACKET3_DISPATCH_INDIRECT = 0x16 +PACKET3_INDIRECT_BUFFER_END = 0x17 +PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 +PACKET3_ATOMIC_GDS = 0x1D +PACKET3_ATOMIC_MEM = 0x1E +PACKET3_OCCLUSION_QUERY = 0x1F +PACKET3_SET_PREDICATION = 0x20 +PACKET3_REG_RMW = 0x21 +PACKET3_COND_EXEC = 0x22 +PACKET3_PRED_EXEC = 0x23 +PACKET3_DRAW_INDIRECT = 0x24 +PACKET3_DRAW_INDEX_INDIRECT = 0x25 +PACKET3_INDEX_BASE = 0x26 +PACKET3_DRAW_INDEX_2 = 0x27 +PACKET3_CONTEXT_CONTROL = 0x28 +PACKET3_INDEX_TYPE = 0x2A +PACKET3_DRAW_INDIRECT_MULTI = 0x2C +PACKET3_DRAW_INDEX_AUTO = 0x2D +PACKET3_NUM_INSTANCES = 0x2F +PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 +PACKET3_INDIRECT_BUFFER_PRIV = 0x32 +PACKET3_INDIRECT_BUFFER_CNST = 0x33 +PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 +PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 +PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 +PACKET3_DRAW_PREAMBLE = 0x36 +PACKET3_WRITE_DATA = 0x37 +WRITE_DATA_DST_SEL = lambda x: ((x) << 8) +WR_ONE_ADDR = (1 << 16) +WR_CONFIRM = (1 << 20) +WRITE_DATA_CACHE_POLICY = lambda x: ((x) << 25) +WRITE_DATA_ENGINE_SEL = lambda x: ((x) << 30) +PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 +PACKET3_MEM_SEMAPHORE = 0x39 +PACKET3_SEM_USE_MAILBOX = (0x1 << 16) +PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1 << 20) +PACKET3_SEM_SEL_SIGNAL = (0x6 << 29) +PACKET3_SEM_SEL_WAIT = (0x7 << 29) +PACKET3_DRAW_INDEX_MULTI_INST = 0x3A +PACKET3_COPY_DW = 0x3B +PACKET3_WAIT_REG_MEM = 0x3C +WAIT_REG_MEM_FUNCTION = lambda x: ((x) << 0) +WAIT_REG_MEM_MEM_SPACE = lambda x: ((x) << 4) +WAIT_REG_MEM_OPERATION = lambda x: ((x) << 6) +WAIT_REG_MEM_ENGINE = lambda x: ((x) << 8) +PACKET3_INDIRECT_BUFFER = 0x3F +INDIRECT_BUFFER_VALID = (1 << 23) +INDIRECT_BUFFER_CACHE_POLICY = lambda x: ((x) << 28) +INDIRECT_BUFFER_PRE_ENB = lambda x: ((x) << 21) +INDIRECT_BUFFER_PRE_RESUME = lambda x: ((x) << 30) +PACKET3_COND_INDIRECT_BUFFER = 0x3F +PACKET3_COPY_DATA = 0x40 +PACKET3_CP_DMA = 0x41 +PACKET3_PFP_SYNC_ME = 0x42 +PACKET3_SURFACE_SYNC = 0x43 +PACKET3_ME_INITIALIZE = 0x44 +PACKET3_COND_WRITE = 0x45 +PACKET3_EVENT_WRITE = 0x46 +EVENT_TYPE = lambda x: ((x) << 0) +EVENT_INDEX = lambda x: ((x) << 8) +PACKET3_EVENT_WRITE_EOP = 0x47 +PACKET3_EVENT_WRITE_EOS = 0x48 +PACKET3_RELEASE_MEM = 0x49 +PACKET3_RELEASE_MEM_EVENT_TYPE = lambda x: ((x) << 0) +PACKET3_RELEASE_MEM_EVENT_INDEX = lambda x: ((x) << 8) +PACKET3_RELEASE_MEM_GCR_GLM_WB = (1 << 12) +PACKET3_RELEASE_MEM_GCR_GLM_INV = (1 << 13) +PACKET3_RELEASE_MEM_GCR_GLV_INV = (1 << 14) +PACKET3_RELEASE_MEM_GCR_GL1_INV = (1 << 15) +PACKET3_RELEASE_MEM_GCR_GL2_US = (1 << 16) +PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1 << 17) +PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1 << 19) +PACKET3_RELEASE_MEM_GCR_GL2_INV = (1 << 20) +PACKET3_RELEASE_MEM_GCR_GL2_WB = (1 << 21) +PACKET3_RELEASE_MEM_GCR_SEQ = (1 << 22) +PACKET3_RELEASE_MEM_CACHE_POLICY = lambda x: ((x) << 25) +PACKET3_RELEASE_MEM_EXECUTE = (1 << 28) +PACKET3_RELEASE_MEM_DATA_SEL = lambda x: ((x) << 29) +PACKET3_RELEASE_MEM_INT_SEL = lambda x: ((x) << 24) +PACKET3_RELEASE_MEM_DST_SEL = lambda x: ((x) << 16) +PACKET3_PREAMBLE_CNTL = 0x4A +PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2 << 28) +PACKET3_PREAMBLE_END_CLEAR_STATE = (3 << 28) +PACKET3_DMA_DATA = 0x50 +PACKET3_DMA_DATA_ENGINE = lambda x: ((x) << 0) +PACKET3_DMA_DATA_SRC_CACHE_POLICY = lambda x: ((x) << 13) +PACKET3_DMA_DATA_DST_SEL = lambda x: ((x) << 20) +PACKET3_DMA_DATA_DST_CACHE_POLICY = lambda x: ((x) << 25) +PACKET3_DMA_DATA_SRC_SEL = lambda x: ((x) << 29) +PACKET3_DMA_DATA_CP_SYNC = (1 << 31) +PACKET3_DMA_DATA_CMD_SAS = (1 << 26) +PACKET3_DMA_DATA_CMD_DAS = (1 << 27) +PACKET3_DMA_DATA_CMD_SAIC = (1 << 28) +PACKET3_DMA_DATA_CMD_DAIC = (1 << 29) +PACKET3_DMA_DATA_CMD_RAW_WAIT = (1 << 30) +PACKET3_CONTEXT_REG_RMW = 0x51 +PACKET3_GFX_CNTX_UPDATE = 0x52 +PACKET3_BLK_CNTX_UPDATE = 0x53 +PACKET3_INCR_UPDT_STATE = 0x55 +PACKET3_ACQUIRE_MEM = 0x58 +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV = lambda x: ((x) << 0) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE = lambda x: ((x) << 2) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB = lambda x: ((x) << 4) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV = lambda x: ((x) << 5) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB = lambda x: ((x) << 6) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV = lambda x: ((x) << 7) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV = lambda x: ((x) << 8) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV = lambda x: ((x) << 9) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US = lambda x: ((x) << 10) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE = lambda x: ((x) << 11) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD = lambda x: ((x) << 13) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV = lambda x: ((x) << 14) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB = lambda x: ((x) << 15) +PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ = lambda x: ((x) << 16) +PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1 << 18) +PACKET3_REWIND = 0x59 +PACKET3_INTERRUPT = 0x5A +PACKET3_GEN_PDEPTE = 0x5B +PACKET3_INDIRECT_BUFFER_PASID = 0x5C +PACKET3_PRIME_UTCL2 = 0x5D +PACKET3_LOAD_UCONFIG_REG = 0x5E +PACKET3_LOAD_SH_REG = 0x5F +PACKET3_LOAD_CONFIG_REG = 0x60 +PACKET3_LOAD_CONTEXT_REG = 0x61 +PACKET3_LOAD_COMPUTE_STATE = 0x62 +PACKET3_LOAD_SH_REG_INDEX = 0x63 +PACKET3_SET_CONFIG_REG = 0x68 +PACKET3_SET_CONFIG_REG_START = 0x00002000 +PACKET3_SET_CONFIG_REG_END = 0x00002c00 +PACKET3_SET_CONTEXT_REG = 0x69 +PACKET3_SET_CONTEXT_REG_START = 0x0000a000 +PACKET3_SET_CONTEXT_REG_END = 0x0000a400 +PACKET3_SET_CONTEXT_REG_INDEX = 0x6A +PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 +PACKET3_SET_SH_REG_DI = 0x72 +PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 +PACKET3_SET_SH_REG_DI_MULTI = 0x74 +PACKET3_GFX_PIPE_LOCK = 0x75 +PACKET3_SET_SH_REG = 0x76 +PACKET3_SET_SH_REG_START = 0x00002c00 +PACKET3_SET_SH_REG_END = 0x00003000 +PACKET3_SET_SH_REG_OFFSET = 0x77 +PACKET3_SET_QUEUE_REG = 0x78 +PACKET3_SET_UCONFIG_REG = 0x79 +PACKET3_SET_UCONFIG_REG_START = 0x0000c000 +PACKET3_SET_UCONFIG_REG_END = 0x0000c400 +PACKET3_SET_UCONFIG_REG_INDEX = 0x7A +PACKET3_FORWARD_HEADER = 0x7C +PACKET3_SCRATCH_RAM_WRITE = 0x7D +PACKET3_SCRATCH_RAM_READ = 0x7E +PACKET3_LOAD_CONST_RAM = 0x80 +PACKET3_WRITE_CONST_RAM = 0x81 +PACKET3_DUMP_CONST_RAM = 0x83 +PACKET3_INCREMENT_CE_COUNTER = 0x84 +PACKET3_INCREMENT_DE_COUNTER = 0x85 +PACKET3_WAIT_ON_CE_COUNTER = 0x86 +PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 +PACKET3_SWITCH_BUFFER = 0x8B +PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C +PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C +PACKET3_DISPATCH_DRAW = 0x8D +PACKET3_DISPATCH_DRAW_ACE = 0x8D +PACKET3_GET_LOD_STATS = 0x8E +PACKET3_DRAW_MULTI_PREAMBLE = 0x8F +PACKET3_FRAME_CONTROL = 0x90 +FRAME_TMZ = (1 << 0) +FRAME_CMD = lambda x: ((x) << 28) +PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 +PACKET3_WAIT_REG_MEM64 = 0x93 +PACKET3_COND_PREEMPT = 0x94 +PACKET3_HDP_FLUSH = 0x95 +PACKET3_COPY_DATA_RB = 0x96 +PACKET3_INVALIDATE_TLBS = 0x98 +PACKET3_INVALIDATE_TLBS_DST_SEL = lambda x: ((x) << 0) +PACKET3_INVALIDATE_TLBS_ALL_HUB = lambda x: ((x) << 4) +PACKET3_INVALIDATE_TLBS_PASID = lambda x: ((x) << 5) +PACKET3_AQL_PACKET = 0x99 +PACKET3_DMA_DATA_FILL_MULTI = 0x9A +PACKET3_SET_SH_REG_INDEX = 0x9B +PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C +PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D +PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E +PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F +PACKET3_SET_RESOURCES = 0xA0 +PACKET3_SET_RESOURCES_VMID_MASK = lambda x: ((x) << 0) +PACKET3_SET_RESOURCES_UNMAP_LATENTY = lambda x: ((x) << 16) +PACKET3_SET_RESOURCES_QUEUE_TYPE = lambda x: ((x) << 29) +PACKET3_MAP_PROCESS = 0xA1 +PACKET3_MAP_QUEUES = 0xA2 +PACKET3_MAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) +PACKET3_MAP_QUEUES_VMID = lambda x: ((x) << 8) +PACKET3_MAP_QUEUES_QUEUE = lambda x: ((x) << 13) +PACKET3_MAP_QUEUES_PIPE = lambda x: ((x) << 16) +PACKET3_MAP_QUEUES_ME = lambda x: ((x) << 18) +PACKET3_MAP_QUEUES_QUEUE_TYPE = lambda x: ((x) << 21) +PACKET3_MAP_QUEUES_ALLOC_FORMAT = lambda x: ((x) << 24) +PACKET3_MAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) +PACKET3_MAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) +PACKET3_MAP_QUEUES_CHECK_DISABLE = lambda x: ((x) << 1) +PACKET3_MAP_QUEUES_DOORBELL_OFFSET = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES = 0xA3 +PACKET3_UNMAP_QUEUES_ACTION = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) +PACKET3_UNMAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) +PACKET3_UNMAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) +PACKET3_UNMAP_QUEUES_PASID = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_RB_WPTR = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3 = lambda x: ((x) << 2) +PACKET3_QUERY_STATUS = 0xA4 +PACKET3_QUERY_STATUS_CONTEXT_ID = lambda x: ((x) << 0) +PACKET3_QUERY_STATUS_INTERRUPT_SEL = lambda x: ((x) << 28) +PACKET3_QUERY_STATUS_COMMAND = lambda x: ((x) << 30) +PACKET3_QUERY_STATUS_PASID = lambda x: ((x) << 0) +PACKET3_QUERY_STATUS_DOORBELL_OFFSET = lambda x: ((x) << 2) +PACKET3_QUERY_STATUS_ENG_SEL = lambda x: ((x) << 25) +PACKET3_RUN_LIST = 0xA5 +PACKET3_MAP_PROCESS_VM = 0xA6 +PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 +PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID = lambda x: ((x) << 0) +PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1 << 0) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/pm4_soc15.py b/tinygrad/runtime/autogen/am/pm4_soc15.py index 3301a0d11b..e2e82937d1 100644 --- a/tinygrad/runtime/autogen/am/pm4_soc15.py +++ b/tinygrad/runtime/autogen/am/pm4_soc15.py @@ -1,933 +1,449 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class union_PM4_MES_TYPE_3_HEADER(ctypes.Union): pass +class _anonstruct0(Struct): pass +enum_mes_set_resources_queue_type_enum = CEnum(ctypes.c_uint32) +queue_type__mes_set_resources__kernel_interface_queue_kiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__kernel_interface_queue_kiq', 0) +queue_type__mes_set_resources__hsa_interface_queue_hiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_interface_queue_hiq', 1) +queue_type__mes_set_resources__hsa_debug_interface_queue = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_debug_interface_queue', 4) +class struct_pm4_mes_set_resources(Struct): pass +class _anonunion1(ctypes.Union): pass +class _anonunion2(ctypes.Union): pass +class _anonstruct3(Struct): pass +class _anonunion4(ctypes.Union): pass +class _anonstruct5(Struct): pass +class _anonunion6(ctypes.Union): pass +class _anonstruct7(Struct): pass +class struct_pm4_mes_runlist(Struct): pass +class _anonunion8(ctypes.Union): pass +class _anonunion9(ctypes.Union): pass +class _anonstruct10(Struct): pass +class _anonunion11(ctypes.Union): pass +class _anonstruct12(Struct): pass +class struct_pm4_mes_map_process(Struct): pass +class _anonunion13(ctypes.Union): pass +class _anonunion14(ctypes.Union): pass +class _anonstruct15(Struct): pass +class _anonunion16(ctypes.Union): pass +class _anonstruct17(Struct): pass +class struct_PM4_MES_MAP_PROCESS_VM(Struct): pass +class _anonunion18(ctypes.Union): pass +enum_mes_map_queues_queue_sel_enum = CEnum(ctypes.c_uint32) +queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_specified_queue_slots_vi', 0) +queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi', 1) -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result +enum_mes_map_queues_queue_type_enum = CEnum(ctypes.c_uint32) +queue_type__mes_map_queues__normal_compute_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__normal_compute_vi', 0) +queue_type__mes_map_queues__debug_interface_queue_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__debug_interface_queue_vi', 1) +queue_type__mes_map_queues__normal_latency_static_queue_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__normal_latency_static_queue_vi', 2) +queue_type__mes_map_queues__low_latency_static_queue_vi = enum_mes_map_queues_queue_type_enum.define('queue_type__mes_map_queues__low_latency_static_queue_vi', 3) +enum_mes_map_queues_engine_sel_enum = CEnum(ctypes.c_uint32) +engine_sel__mes_map_queues__compute_vi = enum_mes_map_queues_engine_sel_enum.define('engine_sel__mes_map_queues__compute_vi', 0) +engine_sel__mes_map_queues__sdma0_vi = enum_mes_map_queues_engine_sel_enum.define('engine_sel__mes_map_queues__sdma0_vi', 2) +engine_sel__mes_map_queues__sdma1_vi = enum_mes_map_queues_engine_sel_enum.define('engine_sel__mes_map_queues__sdma1_vi', 3) -class Structure(ctypes.Structure, AsDictMixin): +enum_mes_map_queues_extended_engine_sel_enum = CEnum(ctypes.c_uint32) +extended_engine_sel__mes_map_queues__legacy_engine_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__legacy_engine_sel', 0) +extended_engine_sel__mes_map_queues__sdma0_to_7_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__sdma0_to_7_sel', 1) +extended_engine_sel__mes_map_queues__sdma8_to_15_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__sdma8_to_15_sel', 2) - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields +class struct_pm4_mes_map_queues(Struct): pass +class _anonunion19(ctypes.Union): pass +class _anonunion20(ctypes.Union): pass +class _anonstruct21(Struct): pass +class _anonunion22(ctypes.Union): pass +class _anonstruct23(Struct): pass +enum_mes_query_status_interrupt_sel_enum = CEnum(ctypes.c_uint32) +interrupt_sel__mes_query_status__completion_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__completion_status', 0) +interrupt_sel__mes_query_status__process_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__process_status', 1) +interrupt_sel__mes_query_status__queue_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__queue_status', 2) - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) +enum_mes_query_status_command_enum = CEnum(ctypes.c_uint32) +command__mes_query_status__interrupt_only = enum_mes_query_status_command_enum.define('command__mes_query_status__interrupt_only', 0) +command__mes_query_status__fence_only_immediate = enum_mes_query_status_command_enum.define('command__mes_query_status__fence_only_immediate', 1) +command__mes_query_status__fence_only_after_write_ack = enum_mes_query_status_command_enum.define('command__mes_query_status__fence_only_after_write_ack', 2) +command__mes_query_status__fence_wait_for_write_ack_send_interrupt = enum_mes_query_status_command_enum.define('command__mes_query_status__fence_wait_for_write_ack_send_interrupt', 3) - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () +enum_mes_query_status_engine_sel_enum = CEnum(ctypes.c_uint32) +engine_sel__mes_query_status__compute = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__compute', 0) +engine_sel__mes_query_status__sdma0_queue = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__sdma0_queue', 2) +engine_sel__mes_query_status__sdma1_queue = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__sdma1_queue', 3) - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None +class struct_pm4_mes_query_status(Struct): pass +class _anonunion24(ctypes.Union): pass +class _anonunion25(ctypes.Union): pass +class _anonstruct26(Struct): pass +class _anonunion27(ctypes.Union): pass +class _anonstruct28(Struct): pass +class _anonstruct29(Struct): pass +enum_mes_unmap_queues_action_enum = CEnum(ctypes.c_uint32) +action__mes_unmap_queues__preempt_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__preempt_queues', 0) +action__mes_unmap_queues__reset_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__reset_queues', 1) +action__mes_unmap_queues__disable_process_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__disable_process_queues', 2) +action__mes_unmap_queues__reserved = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__reserved', 3) - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) +enum_mes_unmap_queues_queue_sel_enum = CEnum(ctypes.c_uint32) +queue_sel__mes_unmap_queues__perform_request_on_specified_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__perform_request_on_specified_queues', 0) +queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__perform_request_on_pasid_queues', 1) +queue_sel__mes_unmap_queues__unmap_all_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__unmap_all_queues', 2) +queue_sel__mes_unmap_queues__unmap_all_non_static_queues = enum_mes_unmap_queues_queue_sel_enum.define('queue_sel__mes_unmap_queues__unmap_all_non_static_queues', 3) +enum_mes_unmap_queues_engine_sel_enum = CEnum(ctypes.c_uint32) +engine_sel__mes_unmap_queues__compute = enum_mes_unmap_queues_engine_sel_enum.define('engine_sel__mes_unmap_queues__compute', 0) +engine_sel__mes_unmap_queues__sdma0 = enum_mes_unmap_queues_engine_sel_enum.define('engine_sel__mes_unmap_queues__sdma0', 2) +engine_sel__mes_unmap_queues__sdmal = enum_mes_unmap_queues_engine_sel_enum.define('engine_sel__mes_unmap_queues__sdmal', 3) -class Union(ctypes.Union, AsDictMixin): - pass +enum_mes_unmap_queues_extended_engine_sel_enum = CEnum(ctypes.c_uint32) +extended_engine_sel__mes_unmap_queues__legacy_engine_sel = enum_mes_unmap_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_unmap_queues__legacy_engine_sel', 0) +extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = enum_mes_unmap_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel', 1) +class struct_pm4_mes_unmap_queues(Struct): pass +class _anonunion30(ctypes.Union): pass +class _anonunion31(ctypes.Union): pass +class _anonstruct32(Struct): pass +class _anonunion33(ctypes.Union): pass +class _anonstruct34(Struct): pass +class _anonstruct35(Struct): pass +class _anonunion36(ctypes.Union): pass +class _anonstruct37(Struct): pass +class _anonunion38(ctypes.Union): pass +class _anonstruct39(Struct): pass +class _anonunion40(ctypes.Union): pass +class _anonstruct41(Struct): pass +enum_mec_release_mem_event_index_enum = CEnum(ctypes.c_uint32) +event_index__mec_release_mem__end_of_pipe = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__end_of_pipe', 5) +event_index__mec_release_mem__shader_done = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__shader_done', 6) +enum_mec_release_mem_cache_policy_enum = CEnum(ctypes.c_uint32) +cache_policy__mec_release_mem__lru = enum_mec_release_mem_cache_policy_enum.define('cache_policy__mec_release_mem__lru', 0) +cache_policy__mec_release_mem__stream = enum_mec_release_mem_cache_policy_enum.define('cache_policy__mec_release_mem__stream', 1) +enum_mec_release_mem_pq_exe_status_enum = CEnum(ctypes.c_uint32) +pq_exe_status__mec_release_mem__default = enum_mec_release_mem_pq_exe_status_enum.define('pq_exe_status__mec_release_mem__default', 0) +pq_exe_status__mec_release_mem__phase_update = enum_mec_release_mem_pq_exe_status_enum.define('pq_exe_status__mec_release_mem__phase_update', 1) +enum_mec_release_mem_dst_sel_enum = CEnum(ctypes.c_uint32) +dst_sel__mec_release_mem__memory_controller = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__memory_controller', 0) +dst_sel__mec_release_mem__tc_l2 = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__tc_l2', 1) +dst_sel__mec_release_mem__queue_write_pointer_register = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__queue_write_pointer_register', 2) +dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = enum_mec_release_mem_dst_sel_enum.define('dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', 3) -F32_MES_PM4_PACKETS_H = True # macro -uint32_t = True # macro -int32_t = True # macro -PM4_MES_HEADER_DEFINED = True # macro -PM4_MEC_RELEASE_MEM_DEFINED = True # macro -PM4_MEC_WRITE_DATA_DEFINED = True # macro -class union_PM4_MES_TYPE_3_HEADER(Union): - pass +enum_mec_release_mem_int_sel_enum = CEnum(ctypes.c_uint32) +int_sel__mec_release_mem__none = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__none', 0) +int_sel__mec_release_mem__send_interrupt_only = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__send_interrupt_only', 1) +int_sel__mec_release_mem__send_interrupt_after_write_confirm = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__send_interrupt_after_write_confirm', 2) +int_sel__mec_release_mem__send_data_after_write_confirm = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__send_data_after_write_confirm', 3) +int_sel__mec_release_mem__unconditionally_send_int_ctxid = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__unconditionally_send_int_ctxid', 4) +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', 5) +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = enum_mec_release_mem_int_sel_enum.define('int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', 6) -class struct_PM4_MES_TYPE_3_HEADER_0(Structure): - pass +enum_mec_release_mem_data_sel_enum = CEnum(ctypes.c_uint32) +data_sel__mec_release_mem__none = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__none', 0) +data_sel__mec_release_mem__send_32_bit_low = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_32_bit_low', 1) +data_sel__mec_release_mem__send_64_bit_data = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_64_bit_data', 2) +data_sel__mec_release_mem__send_gpu_clock_counter = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_gpu_clock_counter', 3) +data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', 4) +data_sel__mec_release_mem__store_gds_data_to_memory = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__store_gds_data_to_memory', 5) -struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False -struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('opcode', ctypes.c_uint32, 8), - ('count', ctypes.c_uint32, 14), - ('type', ctypes.c_uint32, 2), +class struct_pm4_mec_release_mem(Struct): pass +class _anonunion42(ctypes.Union): pass +class _anonunion43(ctypes.Union): pass +class _anonstruct44(Struct): pass +class _anonunion45(ctypes.Union): pass +class _anonstruct46(Struct): pass +class _anonunion47(ctypes.Union): pass +class _anonstruct48(Struct): pass +class _anonstruct49(Struct): pass +class _anonunion50(ctypes.Union): pass +class _anonunion51(ctypes.Union): pass +class _anonstruct52(Struct): pass +class _anonunion53(ctypes.Union): pass +enum_WRITE_DATA_dst_sel_enum = CEnum(ctypes.c_uint32) +dst_sel___write_data__mem_mapped_register = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__mem_mapped_register', 0) +dst_sel___write_data__tc_l2 = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__tc_l2', 2) +dst_sel___write_data__gds = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__gds', 3) +dst_sel___write_data__memory = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__memory', 5) +dst_sel___write_data__memory_mapped_adc_persistent_state = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__memory_mapped_adc_persistent_state', 6) + +enum_WRITE_DATA_addr_incr_enum = CEnum(ctypes.c_uint32) +addr_incr___write_data__increment_address = enum_WRITE_DATA_addr_incr_enum.define('addr_incr___write_data__increment_address', 0) +addr_incr___write_data__do_not_increment_address = enum_WRITE_DATA_addr_incr_enum.define('addr_incr___write_data__do_not_increment_address', 1) + +enum_WRITE_DATA_wr_confirm_enum = CEnum(ctypes.c_uint32) +wr_confirm___write_data__do_not_wait_for_write_confirmation = enum_WRITE_DATA_wr_confirm_enum.define('wr_confirm___write_data__do_not_wait_for_write_confirmation', 0) +wr_confirm___write_data__wait_for_write_confirmation = enum_WRITE_DATA_wr_confirm_enum.define('wr_confirm___write_data__wait_for_write_confirmation', 1) + +enum_WRITE_DATA_cache_policy_enum = CEnum(ctypes.c_uint32) +cache_policy___write_data__lru = enum_WRITE_DATA_cache_policy_enum.define('cache_policy___write_data__lru', 0) +cache_policy___write_data__stream = enum_WRITE_DATA_cache_policy_enum.define('cache_policy___write_data__stream', 1) + +class struct_pm4_mec_write_data_mmio(Struct): pass +class _anonunion54(ctypes.Union): pass +class _anonunion55(ctypes.Union): pass +class _anonunion55_bitfields2(Struct): pass +_anonunion55_bitfields2._fields_ = [ + ('reserved1', ctypes.c_uint32,8), + ('dst_sel', ctypes.c_uint32,4), + ('reserved2', ctypes.c_uint32,4), + ('addr_incr', ctypes.c_uint32,1), + ('reserved3', ctypes.c_uint32,2), + ('resume_vf', ctypes.c_uint32,1), + ('wr_confirm', ctypes.c_uint32,1), + ('reserved4', ctypes.c_uint32,4), + ('cache_policy', ctypes.c_uint32,2), + ('reserved5', ctypes.c_uint32,5), ] - -union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False -union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) -union_PM4_MES_TYPE_3_HEADER._fields_ = [ - ('_0', struct_PM4_MES_TYPE_3_HEADER_0), - ('u32All', ctypes.c_uint32), +_anonunion55._fields_ = [ + ('bitfields2', _anonunion55_bitfields2), + ('ordinal2', ctypes.c_uint32), ] - - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 5: 'event_index__mec_release_mem__end_of_pipe', - 6: 'event_index__mec_release_mem__shader_done', -} -event_index__mec_release_mem__end_of_pipe = 5 -event_index__mec_release_mem__shader_done = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'cache_policy__mec_release_mem__lru', - 1: 'cache_policy__mec_release_mem__stream', -} -cache_policy__mec_release_mem__lru = 0 -cache_policy__mec_release_mem__stream = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'pq_exe_status__mec_release_mem__default', - 1: 'pq_exe_status__mec_release_mem__phase_update', -} -pq_exe_status__mec_release_mem__default = 0 -pq_exe_status__mec_release_mem__phase_update = 1 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'dst_sel__mec_release_mem__memory_controller', - 1: 'dst_sel__mec_release_mem__tc_l2', - 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', - 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', -} -dst_sel__mec_release_mem__memory_controller = 0 -dst_sel__mec_release_mem__tc_l2 = 1 -dst_sel__mec_release_mem__queue_write_pointer_register = 2 -dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'int_sel__mec_release_mem__none', - 1: 'int_sel__mec_release_mem__send_interrupt_only', - 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', - 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', -} -int_sel__mec_release_mem__none = 0 -int_sel__mec_release_mem__send_interrupt_only = 1 -int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 -int_sel__mec_release_mem__send_data_after_write_confirm = 3 -int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 -int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 -c_uint32 = ctypes.c_uint32 # enum - -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'data_sel__mec_release_mem__none', - 1: 'data_sel__mec_release_mem__send_32_bit_low', - 2: 'data_sel__mec_release_mem__send_64_bit_data', - 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', - 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', -} -data_sel__mec_release_mem__none = 0 -data_sel__mec_release_mem__send_32_bit_low = 1 -data_sel__mec_release_mem__send_64_bit_data = 2 -data_sel__mec_release_mem__send_gpu_clock_counter = 3 -data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 -data_sel__mec_release_mem__store_gds_data_to_memory = 5 -c_uint32 = ctypes.c_uint32 # enum -class struct_pm4_mec_release_mem(Structure): - pass - -class union_pm4_mec_release_mem_0(Union): - pass - -union_pm4_mec_release_mem_0._pack_ = 1 # source:False -union_pm4_mec_release_mem_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), +class _anonunion56(ctypes.Union): pass +class _anonunion56_bitfields3(Struct): pass +_anonunion56_bitfields3._fields_ = [ + ('dst_mmreg_addr', ctypes.c_uint32,18), + ('reserved6', ctypes.c_uint32,14), ] - -class union_pm4_mec_release_mem_1(Union): - pass - -class struct_pm4_mec_release_mem_1_bitfields2(Structure): - pass - -struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ - ('event_type', ctypes.c_uint32, 6), - ('reserved1', ctypes.c_uint32, 2), - ('event_index', c_uint32, 4), - ('tcl1_vol_action_ena', ctypes.c_uint32, 1), - ('tc_vol_action_ena', ctypes.c_uint32, 1), - ('reserved2', ctypes.c_uint32, 1), - ('tc_wb_action_ena', ctypes.c_uint32, 1), - ('tcl1_action_ena', ctypes.c_uint32, 1), - ('tc_action_ena', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 1), - ('tc_nc_action_ena', ctypes.c_uint32, 1), - ('tc_wc_action_ena', ctypes.c_uint32, 1), - ('tc_md_action_ena', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 3), - ('cache_policy', c_uint32, 2), - ('reserved5', ctypes.c_uint32, 2), - ('pq_exe_status', c_uint32, 1), - ('reserved6', ctypes.c_uint32, 2), +_anonunion56._fields_ = [ + ('bitfields3', _anonunion56_bitfields3), + ('ordinal3', ctypes.c_uint32), ] +_anonenum57 = CEnum(ctypes.c_uint32) +CACHE_FLUSH_AND_INV_TS_EVENT = _anonenum57.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) -union_pm4_mec_release_mem_1._pack_ = 1 # source:False -union_pm4_mec_release_mem_1._fields_ = [ - ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_2(Union): - pass - -class struct_pm4_mec_release_mem_2_bitfields3(Structure): - pass - -struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ - ('reserved7', ctypes.c_uint32, 16), - ('dst_sel', c_uint32, 2), - ('reserved8', ctypes.c_uint32, 6), - ('int_sel', c_uint32, 3), - ('reserved9', ctypes.c_uint32, 2), - ('data_sel', c_uint32, 3), -] - -union_pm4_mec_release_mem_2._pack_ = 1 # source:False -union_pm4_mec_release_mem_2._fields_ = [ - ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_3(Union): - pass - -class struct_pm4_mec_release_mem_3_bitfields4(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ - ('reserved10', ctypes.c_uint32, 2), - ('address_lo_32b', ctypes.c_uint32, 30), -] - -class struct_pm4_mec_release_mem_3_bitfields4b(Structure): - pass - -struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False -struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ - ('reserved11', ctypes.c_uint32, 3), - ('address_lo_64b', ctypes.c_uint32, 29), -] - -union_pm4_mec_release_mem_3._pack_ = 1 # source:False -union_pm4_mec_release_mem_3._fields_ = [ - ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), - ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), - ('reserved12', ctypes.c_uint32), - ('ordinal4', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_4(Union): - pass - -union_pm4_mec_release_mem_4._pack_ = 1 # source:False -union_pm4_mec_release_mem_4._fields_ = [ - ('address_hi', ctypes.c_uint32), - ('reserved13', ctypes.c_uint32), - ('ordinal5', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_5(Union): - pass - -class struct_pm4_mec_release_mem_5_bitfields6c(Structure): - pass - -struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False -struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ - ('dw_offset', ctypes.c_uint32, 16), - ('num_dwords', ctypes.c_uint32, 16), -] - -union_pm4_mec_release_mem_5._pack_ = 1 # source:False -union_pm4_mec_release_mem_5._fields_ = [ - ('data_lo', ctypes.c_uint32), - ('cmp_data_lo', ctypes.c_uint32), - ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), - ('reserved14', ctypes.c_uint32), - ('ordinal6', ctypes.c_uint32), -] - -class union_pm4_mec_release_mem_6(Union): - pass - -union_pm4_mec_release_mem_6._pack_ = 1 # source:False -union_pm4_mec_release_mem_6._fields_ = [ - ('data_hi', ctypes.c_uint32), - ('cmp_data_hi', ctypes.c_uint32), - ('reserved15', ctypes.c_uint32), - ('reserved16', ctypes.c_uint32), - ('ordinal7', ctypes.c_uint32), -] - -struct_pm4_mec_release_mem._pack_ = 1 # source:False -struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) -struct_pm4_mec_release_mem._fields_ = [ - ('_0', union_pm4_mec_release_mem_0), - ('_1', union_pm4_mec_release_mem_1), - ('_2', union_pm4_mec_release_mem_2), - ('_3', union_pm4_mec_release_mem_3), - ('_4', union_pm4_mec_release_mem_4), - ('_5', union_pm4_mec_release_mem_5), - ('_6', union_pm4_mec_release_mem_6), - ('int_ctxid', ctypes.c_uint32), -] - - -# values for enumeration 'WRITE_DATA_dst_sel_enum' -WRITE_DATA_dst_sel_enum__enumvalues = { - 0: 'dst_sel___write_data__mem_mapped_register', - 2: 'dst_sel___write_data__tc_l2', - 3: 'dst_sel___write_data__gds', - 5: 'dst_sel___write_data__memory', - 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', -} -dst_sel___write_data__mem_mapped_register = 0 -dst_sel___write_data__tc_l2 = 2 -dst_sel___write_data__gds = 3 -dst_sel___write_data__memory = 5 -dst_sel___write_data__memory_mapped_adc_persistent_state = 6 -WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_addr_incr_enum' -WRITE_DATA_addr_incr_enum__enumvalues = { - 0: 'addr_incr___write_data__increment_address', - 1: 'addr_incr___write_data__do_not_increment_address', -} -addr_incr___write_data__increment_address = 0 -addr_incr___write_data__do_not_increment_address = 1 -WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_wr_confirm_enum' -WRITE_DATA_wr_confirm_enum__enumvalues = { - 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 1: 'wr_confirm___write_data__wait_for_write_confirmation', -} -wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 -wr_confirm___write_data__wait_for_write_confirmation = 1 -WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum - -# values for enumeration 'WRITE_DATA_cache_policy_enum' -WRITE_DATA_cache_policy_enum__enumvalues = { - 0: 'cache_policy___write_data__lru', - 1: 'cache_policy___write_data__stream', -} -cache_policy___write_data__lru = 0 -cache_policy___write_data__stream = 1 -WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum -class struct_pm4_mec_write_data_mmio(Structure): - pass - -class union_pm4_mec_write_data_mmio_0(Union): - pass - -union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_0._fields_ = [ - ('header', union_PM4_MES_TYPE_3_HEADER), - ('ordinal1', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_1(Union): - pass - -class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): - pass - -struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ - ('reserved1', ctypes.c_uint32, 8), - ('dst_sel', ctypes.c_uint32, 4), - ('reserved2', ctypes.c_uint32, 4), - ('addr_incr', ctypes.c_uint32, 1), - ('reserved3', ctypes.c_uint32, 2), - ('resume_vf', ctypes.c_uint32, 1), - ('wr_confirm', ctypes.c_uint32, 1), - ('reserved4', ctypes.c_uint32, 4), - ('cache_policy', ctypes.c_uint32, 2), - ('reserved5', ctypes.c_uint32, 5), -] - -union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_1._fields_ = [ - ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), - ('ordinal2', ctypes.c_uint32), -] - -class union_pm4_mec_write_data_mmio_2(Union): - pass - -class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): - pass - -struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ - ('dst_mmreg_addr', ctypes.c_uint32, 18), - ('reserved6', ctypes.c_uint32, 14), -] - -union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False -union_pm4_mec_write_data_mmio_2._fields_ = [ - ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), - ('ordinal3', ctypes.c_uint32), -] - -struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False -struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) -struct_pm4_mec_write_data_mmio._fields_ = [ - ('_0', union_pm4_mec_write_data_mmio_0), - ('_1', union_pm4_mec_write_data_mmio_1), - ('_2', union_pm4_mec_write_data_mmio_2), - ('reserved7', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { - 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', -} -CACHE_FLUSH_AND_INV_TS_EVENT = 20 -c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum -SOC15_H = True # macro -GFX9_NUM_GFX_RINGS = 1 # macro -GFX9_NUM_COMPUTE_RINGS = 8 # macro -PACKET_TYPE0 = 0 # macro -PACKET_TYPE1 = 1 # macro -PACKET_TYPE2 = 2 # macro -PACKET_TYPE3 = 3 # macro -def CP_PACKET_GET_TYPE(h): # macro - return (((h)>>30)&3) -def CP_PACKET_GET_COUNT(h): # macro - return (((h)>>16)&0x3FFF) -def CP_PACKET0_GET_REG(h): # macro - return ((h)&0xFFFF) -def CP_PACKET3_GET_OPCODE(h): # macro - return (((h)>>8)&0xFF) -def PACKET0(reg, n): # macro - return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) -CP_PACKET2 = 0x80000000 # macro -PACKET2_PAD_SHIFT = 0 # macro -PACKET2_PAD_MASK = (0x3fffffff<<0) # macro -# def PACKET2(v): # macro -# return (0x80000000|REG_SET(PACKET2_PAD,(v))) -def PACKET3(op, n): # macro - return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) -def PACKET3_COMPUTE(op, n): # macro - return (PACKET3(op,n)|1<<1) -PACKETJ_CONDITION_CHECK0 = 0 # macro -PACKETJ_CONDITION_CHECK1 = 1 # macro -PACKETJ_CONDITION_CHECK2 = 2 # macro -PACKETJ_CONDITION_CHECK3 = 3 # macro -PACKETJ_CONDITION_CHECK4 = 4 # macro -PACKETJ_CONDITION_CHECK5 = 5 # macro -PACKETJ_CONDITION_CHECK6 = 6 # macro -PACKETJ_CONDITION_CHECK7 = 7 # macro -PACKETJ_TYPE0 = 0 # macro -PACKETJ_TYPE1 = 1 # macro -PACKETJ_TYPE2 = 2 # macro -PACKETJ_TYPE3 = 3 # macro -PACKETJ_TYPE4 = 4 # macro -PACKETJ_TYPE5 = 5 # macro -PACKETJ_TYPE6 = 6 # macro -PACKETJ_TYPE7 = 7 # macro -def PACKETJ(reg, r, cond, type): # macro - return ((reg&0x3FFFF)|((r&0x3F)<<18)|((cond&0xF)<<24)|((type&0xF)<<28)) -CP_PACKETJ_NOP = 0x60000000 # macro -def CP_PACKETJ_GET_REG(x): # macro - return ((x)&0x3FFFF) -def CP_PACKETJ_GET_RES(x): # macro - return (((x)>>18)&0x3F) -def CP_PACKETJ_GET_COND(x): # macro - return (((x)>>24)&0xF) -def CP_PACKETJ_GET_TYPE(x): # macro - return (((x)>>28)&0xF) -PACKET3_NOP = 0x10 # macro -PACKET3_SET_BASE = 0x11 # macro -def PACKET3_BASE_INDEX(x): # macro - return ((x)<<0) -CE_PARTITION_BASE = 3 # macro -PACKET3_CLEAR_STATE = 0x12 # macro -PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro -PACKET3_DISPATCH_DIRECT = 0x15 # macro -PACKET3_DISPATCH_INDIRECT = 0x16 # macro -PACKET3_ATOMIC_GDS = 0x1D # macro -PACKET3_ATOMIC_MEM = 0x1E # macro -PACKET3_OCCLUSION_QUERY = 0x1F # macro -PACKET3_SET_PREDICATION = 0x20 # macro -PACKET3_REG_RMW = 0x21 # macro -PACKET3_COND_EXEC = 0x22 # macro -PACKET3_PRED_EXEC = 0x23 # macro -PACKET3_DRAW_INDIRECT = 0x24 # macro -PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro -PACKET3_INDEX_BASE = 0x26 # macro -PACKET3_DRAW_INDEX_2 = 0x27 # macro -PACKET3_CONTEXT_CONTROL = 0x28 # macro -PACKET3_INDEX_TYPE = 0x2A # macro -PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro -PACKET3_DRAW_INDEX_AUTO = 0x2D # macro -PACKET3_NUM_INSTANCES = 0x2F # macro -PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro -PACKET3_INDIRECT_BUFFER_CONST = 0x33 # macro -PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro -PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro -PACKET3_DRAW_PREAMBLE = 0x36 # macro -PACKET3_WRITE_DATA = 0x37 # macro -def WRITE_DATA_DST_SEL(x): # macro - return ((x)<<8) -WR_ONE_ADDR = (1<<16) # macro -WR_CONFIRM = (1<<20) # macro -def WRITE_DATA_CACHE_POLICY(x): # macro - return ((x)<<25) -def WRITE_DATA_ENGINE_SEL(x): # macro - return ((x)<<30) -PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro -PACKET3_MEM_SEMAPHORE = 0x39 # macro -PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro -PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro -PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro -PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro -PACKET3_WAIT_REG_MEM = 0x3C # macro -def WAIT_REG_MEM_FUNCTION(x): # macro - return ((x)<<0) -def WAIT_REG_MEM_MEM_SPACE(x): # macro - return ((x)<<4) -def WAIT_REG_MEM_OPERATION(x): # macro - return ((x)<<6) -def WAIT_REG_MEM_ENGINE(x): # macro - return ((x)<<8) -PACKET3_INDIRECT_BUFFER = 0x3F # macro -INDIRECT_BUFFER_VALID = (1<<23) # macro -def INDIRECT_BUFFER_CACHE_POLICY(x): # macro - return ((x)<<28) -def INDIRECT_BUFFER_PRE_ENB(x): # macro - return ((x)<<21) -def INDIRECT_BUFFER_PRE_RESUME(x): # macro - return ((x)<<30) -PACKET3_COPY_DATA = 0x40 # macro -PACKET3_PFP_SYNC_ME = 0x42 # macro -PACKET3_COND_WRITE = 0x45 # macro -PACKET3_EVENT_WRITE = 0x46 # macro -def EVENT_TYPE(x): # macro - return ((x)<<0) -def EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_RELEASE_MEM = 0x49 # macro -EOP_TCL1_VOL_ACTION_EN = (1<<12) # macro -EOP_TC_VOL_ACTION_EN = (1<<13) # macro -EOP_TC_WB_ACTION_EN = (1<<15) # macro -EOP_TCL1_ACTION_EN = (1<<16) # macro -EOP_TC_ACTION_EN = (1<<17) # macro -EOP_TC_NC_ACTION_EN = (1<<19) # macro -EOP_TC_MD_ACTION_EN = (1<<21) # macro -EOP_EXEC = (1<<28) # macro -def DATA_SEL(x): # macro - return ((x)<<29) -def INT_SEL(x): # macro - return ((x)<<24) -def DST_SEL(x): # macro - return ((x)<<16) -PACKET3_PREAMBLE_CNTL = 0x4A # macro -PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro -PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro -PACKET3_DMA_DATA = 0x50 # macro -def PACKET3_DMA_DATA_ENGINE(x): # macro - return ((x)<<0) -def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro - return ((x)<<13) -def PACKET3_DMA_DATA_DST_SEL(x): # macro - return ((x)<<20) -def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro - return ((x)<<25) -def PACKET3_DMA_DATA_SRC_SEL(x): # macro - return ((x)<<29) -PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro -PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro -PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro -PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro -PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro -PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro -PACKET3_ACQUIRE_MEM = 0x58 # macro -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x): # macro - return ((x)<<3) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x): # macro - return ((x)<<4) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x): # macro - return ((x)<<5) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x): # macro - return ((x)<<15) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x): # macro - return ((x)<<18) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x): # macro - return ((x)<<22) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x): # macro - return ((x)<<23) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x): # macro - return ((x)<<25) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x): # macro - return ((x)<<26) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x): # macro - return ((x)<<27) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x): # macro - return ((x)<<28) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x): # macro - return ((x)<<29) -def PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x): # macro - return ((x)<<30) -PACKET3_REWIND = 0x59 # macro -PACKET3_LOAD_UCONFIG_REG = 0x5E # macro -PACKET3_LOAD_SH_REG = 0x5F # macro -PACKET3_LOAD_CONFIG_REG = 0x60 # macro -PACKET3_LOAD_CONTEXT_REG = 0x61 # macro -PACKET3_SET_CONFIG_REG = 0x68 # macro -PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro -PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro -PACKET3_SET_CONTEXT_REG = 0x69 # macro -PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro -PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro -PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro -PACKET3_SET_SH_REG = 0x76 # macro -PACKET3_SET_SH_REG_START = 0x00002c00 # macro -PACKET3_SET_SH_REG_END = 0x00003000 # macro -PACKET3_SET_SH_REG_OFFSET = 0x77 # macro -PACKET3_SET_QUEUE_REG = 0x78 # macro -PACKET3_SET_UCONFIG_REG = 0x79 # macro -PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro -PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro -PACKET3_SET_UCONFIG_REG_INDEX_TYPE = (2<<28) # macro -PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro -PACKET3_SCRATCH_RAM_READ = 0x7E # macro -PACKET3_LOAD_CONST_RAM = 0x80 # macro -PACKET3_WRITE_CONST_RAM = 0x81 # macro -PACKET3_DUMP_CONST_RAM = 0x83 # macro -PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro -PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro -PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro -PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro -PACKET3_SWITCH_BUFFER = 0x8B # macro -PACKET3_FRAME_CONTROL = 0x90 # macro -FRAME_TMZ = (1<<0) # macro -def FRAME_CMD(x): # macro - return ((x)<<28) -PACKET3_INVALIDATE_TLBS = 0x98 # macro -def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro - return ((x)<<0) -def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro - return ((x)<<4) -def PACKET3_INVALIDATE_TLBS_PASID(x): # macro - return ((x)<<5) -def PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x): # macro - return ((x)<<29) -PACKET3_SET_RESOURCES = 0xA0 # macro -def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro - return ((x)<<0) -def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro - return ((x)<<16) -def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro - return ((x)<<29) -PACKET3_MAP_QUEUES = 0xA2 # macro -def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_MAP_QUEUES_VMID(x): # macro - return ((x)<<8) -def PACKET3_MAP_QUEUES_QUEUE(x): # macro - return ((x)<<13) -def PACKET3_MAP_QUEUES_PIPE(x): # macro - return ((x)<<16) -def PACKET3_MAP_QUEUES_ME(x): # macro - return ((x)<<18) -def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro - return ((x)<<21) -def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro - return ((x)<<24) -def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro - return ((x)<<1) -def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -PACKET3_UNMAP_QUEUES = 0xA3 # macro -def PACKET3_UNMAP_QUEUES_ACTION(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_UNMAP_QUEUES_PASID(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro - return ((x)<<2) -PACKET3_QUERY_STATUS = 0xA4 # macro -def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro - return ((x)<<28) -def PACKET3_QUERY_STATUS_COMMAND(x): # macro - return ((x)<<30) -def PACKET3_QUERY_STATUS_PASID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro - return ((x)<<25) -PACKET3_RUN_CLEANER_SHADER = 0xD2 # macro -VCE_CMD_NO_OP = 0x00000000 # macro -VCE_CMD_END = 0x00000001 # macro -VCE_CMD_IB = 0x00000002 # macro -VCE_CMD_FENCE = 0x00000003 # macro -VCE_CMD_TRAP = 0x00000004 # macro -VCE_CMD_IB_AUTO = 0x00000005 # macro -VCE_CMD_SEMAPHORE = 0x00000006 # macro -VCE_CMD_IB_VM = 0x00000102 # macro -VCE_CMD_WAIT_GE = 0x00000106 # macro -VCE_CMD_UPDATE_PTB = 0x00000107 # macro -VCE_CMD_FLUSH_TLB = 0x00000108 # macro -VCE_CMD_REG_WRITE = 0x00000109 # macro -VCE_CMD_REG_WAIT = 0x0000010a # macro -HEVC_ENC_CMD_NO_OP = 0x00000000 # macro -HEVC_ENC_CMD_END = 0x00000001 # macro -HEVC_ENC_CMD_FENCE = 0x00000003 # macro -HEVC_ENC_CMD_TRAP = 0x00000004 # macro -HEVC_ENC_CMD_IB_VM = 0x00000102 # macro -HEVC_ENC_CMD_REG_WRITE = 0x00000109 # macro -HEVC_ENC_CMD_REG_WAIT = 0x0000010a # macro -__all__ = \ - ['CACHE_FLUSH_AND_INV_TS_EVENT', 'CE_PARTITION_BASE', - 'CP_PACKET2', 'CP_PACKETJ_NOP', 'EOP_EXEC', 'EOP_TCL1_ACTION_EN', - 'EOP_TCL1_VOL_ACTION_EN', 'EOP_TC_ACTION_EN', - 'EOP_TC_MD_ACTION_EN', 'EOP_TC_NC_ACTION_EN', - 'EOP_TC_VOL_ACTION_EN', 'EOP_TC_WB_ACTION_EN', - 'F32_MES_PM4_PACKETS_H', 'FRAME_TMZ', 'GFX9_NUM_COMPUTE_RINGS', - 'GFX9_NUM_GFX_RINGS', 'HEVC_ENC_CMD_END', 'HEVC_ENC_CMD_FENCE', - 'HEVC_ENC_CMD_IB_VM', 'HEVC_ENC_CMD_NO_OP', - 'HEVC_ENC_CMD_REG_WAIT', 'HEVC_ENC_CMD_REG_WRITE', - 'HEVC_ENC_CMD_TRAP', 'INDIRECT_BUFFER_VALID', 'PACKET2_PAD_MASK', - 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', 'PACKET3_ATOMIC_GDS', - 'PACKET3_ATOMIC_MEM', 'PACKET3_CLEAR_STATE', 'PACKET3_COND_EXEC', - 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', - 'PACKET3_COPY_DATA', 'PACKET3_DISPATCH_DIRECT', - 'PACKET3_DISPATCH_INDIRECT', 'PACKET3_DMA_DATA', - 'PACKET3_DMA_DATA_CMD_DAIC', 'PACKET3_DMA_DATA_CMD_DAS', - 'PACKET3_DMA_DATA_CMD_RAW_WAIT', 'PACKET3_DMA_DATA_CMD_SAIC', - 'PACKET3_DMA_DATA_CMD_SAS', 'PACKET3_DMA_DATA_CP_SYNC', - 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', - 'PACKET3_DRAW_INDEX_INDIRECT', - 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', - 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_OFFSET_2', - 'PACKET3_DRAW_INDIRECT', 'PACKET3_DRAW_INDIRECT_MULTI', - 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', - 'PACKET3_EVENT_WRITE', 'PACKET3_FRAME_CONTROL', - 'PACKET3_INCREMENT_CE_COUNTER', 'PACKET3_INCREMENT_DE_COUNTER', - 'PACKET3_INDEX_BASE', 'PACKET3_INDEX_BUFFER_SIZE', - 'PACKET3_INDEX_TYPE', 'PACKET3_INDIRECT_BUFFER', - 'PACKET3_INDIRECT_BUFFER_CONST', 'PACKET3_INVALIDATE_TLBS', - 'PACKET3_LOAD_CONFIG_REG', 'PACKET3_LOAD_CONST_RAM', - 'PACKET3_LOAD_CONTEXT_REG', 'PACKET3_LOAD_SH_REG', - 'PACKET3_LOAD_UCONFIG_REG', 'PACKET3_MAP_QUEUES', - 'PACKET3_MEM_SEMAPHORE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', - 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', - 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', - 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', - 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', 'PACKET3_RELEASE_MEM', - 'PACKET3_REWIND', 'PACKET3_RUN_CLEANER_SHADER', - 'PACKET3_SCRATCH_RAM_READ', 'PACKET3_SCRATCH_RAM_WRITE', - 'PACKET3_SEM_SEL_SIGNAL', 'PACKET3_SEM_SEL_SIGNAL_TYPE', - 'PACKET3_SEM_SEL_WAIT', 'PACKET3_SEM_USE_MAILBOX', - 'PACKET3_SET_BASE', 'PACKET3_SET_CONFIG_REG', - 'PACKET3_SET_CONFIG_REG_END', 'PACKET3_SET_CONFIG_REG_START', - 'PACKET3_SET_CONTEXT_REG', 'PACKET3_SET_CONTEXT_REG_END', - 'PACKET3_SET_CONTEXT_REG_INDIRECT', - 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', - 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_RESOURCES', - 'PACKET3_SET_SH_REG', 'PACKET3_SET_SH_REG_END', - 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', - 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', - 'PACKET3_SET_UCONFIG_REG_INDEX_TYPE', - 'PACKET3_SET_UCONFIG_REG_START', 'PACKET3_STRMOUT_BUFFER_UPDATE', - 'PACKET3_SWITCH_BUFFER', 'PACKET3_UNMAP_QUEUES', - 'PACKET3_WAIT_ON_CE_COUNTER', 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', - 'PACKET3_WAIT_REG_MEM', 'PACKET3_WRITE_CONST_RAM', - 'PACKET3_WRITE_DATA', 'PACKETJ_CONDITION_CHECK0', - 'PACKETJ_CONDITION_CHECK1', 'PACKETJ_CONDITION_CHECK2', - 'PACKETJ_CONDITION_CHECK3', 'PACKETJ_CONDITION_CHECK4', - 'PACKETJ_CONDITION_CHECK5', 'PACKETJ_CONDITION_CHECK6', - 'PACKETJ_CONDITION_CHECK7', 'PACKETJ_TYPE0', 'PACKETJ_TYPE1', - 'PACKETJ_TYPE2', 'PACKETJ_TYPE3', 'PACKETJ_TYPE4', - 'PACKETJ_TYPE5', 'PACKETJ_TYPE6', 'PACKETJ_TYPE7', 'PACKET_TYPE0', - 'PACKET_TYPE1', 'PACKET_TYPE2', 'PACKET_TYPE3', - 'PM4_MEC_RELEASE_MEM_DEFINED', 'PM4_MEC_WRITE_DATA_DEFINED', - 'PM4_MES_HEADER_DEFINED', 'SOC15_H', 'VCE_CMD_END', - 'VCE_CMD_FENCE', 'VCE_CMD_FLUSH_TLB', 'VCE_CMD_IB', - 'VCE_CMD_IB_AUTO', 'VCE_CMD_IB_VM', 'VCE_CMD_NO_OP', - 'VCE_CMD_REG_WAIT', 'VCE_CMD_REG_WRITE', 'VCE_CMD_SEMAPHORE', - 'VCE_CMD_TRAP', 'VCE_CMD_UPDATE_PTB', 'VCE_CMD_WAIT_GE', - 'WRITE_DATA_addr_incr_enum', 'WRITE_DATA_cache_policy_enum', - 'WRITE_DATA_dst_sel_enum', 'WRITE_DATA_wr_confirm_enum', - 'WR_CONFIRM', 'WR_ONE_ADDR', - 'addr_incr___write_data__do_not_increment_address', - 'addr_incr___write_data__increment_address', - 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', - 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', - 'cache_policy___write_data__lru', - 'cache_policy___write_data__stream', - 'cache_policy__mec_release_mem__lru', - 'cache_policy__mec_release_mem__stream', - 'data_sel__mec_release_mem__none', - 'data_sel__mec_release_mem__send_32_bit_low', - 'data_sel__mec_release_mem__send_64_bit_data', - 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', - 'data_sel__mec_release_mem__send_gpu_clock_counter', - 'data_sel__mec_release_mem__store_gds_data_to_memory', - 'dst_sel___write_data__gds', - 'dst_sel___write_data__mem_mapped_register', - 'dst_sel___write_data__memory', - 'dst_sel___write_data__memory_mapped_adc_persistent_state', - 'dst_sel___write_data__tc_l2', - 'dst_sel__mec_release_mem__memory_controller', - 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', - 'dst_sel__mec_release_mem__queue_write_pointer_register', - 'dst_sel__mec_release_mem__tc_l2', - 'event_index__mec_release_mem__end_of_pipe', - 'event_index__mec_release_mem__shader_done', 'int32_t', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', - 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', - 'int_sel__mec_release_mem__none', - 'int_sel__mec_release_mem__send_data_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', - 'int_sel__mec_release_mem__send_interrupt_only', - 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', - 'pq_exe_status__mec_release_mem__default', - 'pq_exe_status__mec_release_mem__phase_update', - 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_pm4_mec_release_mem', - 'struct_pm4_mec_release_mem_1_bitfields2', - 'struct_pm4_mec_release_mem_2_bitfields3', - 'struct_pm4_mec_release_mem_3_bitfields4', - 'struct_pm4_mec_release_mem_3_bitfields4b', - 'struct_pm4_mec_release_mem_5_bitfields6c', - 'struct_pm4_mec_write_data_mmio', - 'struct_pm4_mec_write_data_mmio_1_bitfields2', - 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', - 'union_PM4_MES_TYPE_3_HEADER', 'union_pm4_mec_release_mem_0', - 'union_pm4_mec_release_mem_1', 'union_pm4_mec_release_mem_2', - 'union_pm4_mec_release_mem_3', 'union_pm4_mec_release_mem_4', - 'union_pm4_mec_release_mem_5', 'union_pm4_mec_release_mem_6', - 'union_pm4_mec_write_data_mmio_0', - 'union_pm4_mec_write_data_mmio_1', - 'union_pm4_mec_write_data_mmio_2', - 'wr_confirm___write_data__do_not_wait_for_write_confirmation', - 'wr_confirm___write_data__wait_for_write_confirmation'] +GFX9_NUM_GFX_RINGS = 1 +GFX9_NUM_COMPUTE_RINGS = 8 +PACKET_TYPE0 = 0 +PACKET_TYPE1 = 1 +PACKET_TYPE2 = 2 +PACKET_TYPE3 = 3 +CP_PACKET_GET_TYPE = lambda h: (((h) >> 30) & 3) +CP_PACKET_GET_COUNT = lambda h: (((h) >> 16) & 0x3FFF) +CP_PACKET0_GET_REG = lambda h: ((h) & 0xFFFF) +CP_PACKET3_GET_OPCODE = lambda h: (((h) >> 8) & 0xFF) +PACKET0 = lambda reg,n: ((PACKET_TYPE0 << 30) | ((reg) & 0xFFFF) | ((n) & 0x3FFF) << 16) +CP_PACKET2 = 0x80000000 +PACKET2_PAD_SHIFT = 0 +PACKET2_PAD_MASK = (0x3fffffff << 0) +PACKET2 = lambda v: (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +PACKET3 = lambda op,n: ((PACKET_TYPE3 << 30) | (((op) & 0xFF) << 8) | ((n) & 0x3FFF) << 16) +PACKET3_COMPUTE = lambda op,n: (PACKET3(op, n) | 1 << 1) +PACKETJ_CONDITION_CHECK0 = 0 +PACKETJ_CONDITION_CHECK1 = 1 +PACKETJ_CONDITION_CHECK2 = 2 +PACKETJ_CONDITION_CHECK3 = 3 +PACKETJ_CONDITION_CHECK4 = 4 +PACKETJ_CONDITION_CHECK5 = 5 +PACKETJ_CONDITION_CHECK6 = 6 +PACKETJ_CONDITION_CHECK7 = 7 +PACKETJ_TYPE0 = 0 +PACKETJ_TYPE1 = 1 +PACKETJ_TYPE2 = 2 +PACKETJ_TYPE3 = 3 +PACKETJ_TYPE4 = 4 +PACKETJ_TYPE5 = 5 +PACKETJ_TYPE6 = 6 +PACKETJ_TYPE7 = 7 +PACKETJ = lambda reg,r,cond,type: ((reg & 0x3FFFF) | ((r & 0x3F) << 18) | ((cond & 0xF) << 24) | ((type & 0xF) << 28)) +CP_PACKETJ_NOP = 0x60000000 +CP_PACKETJ_GET_REG = lambda x: ((x) & 0x3FFFF) +CP_PACKETJ_GET_RES = lambda x: (((x) >> 18) & 0x3F) +CP_PACKETJ_GET_COND = lambda x: (((x) >> 24) & 0xF) +CP_PACKETJ_GET_TYPE = lambda x: (((x) >> 28) & 0xF) +PACKET3_NOP = 0x10 +PACKET3_SET_BASE = 0x11 +PACKET3_BASE_INDEX = lambda x: ((x) << 0) +CE_PARTITION_BASE = 3 +PACKET3_CLEAR_STATE = 0x12 +PACKET3_INDEX_BUFFER_SIZE = 0x13 +PACKET3_DISPATCH_DIRECT = 0x15 +PACKET3_DISPATCH_INDIRECT = 0x16 +PACKET3_ATOMIC_GDS = 0x1D +PACKET3_ATOMIC_MEM = 0x1E +PACKET3_OCCLUSION_QUERY = 0x1F +PACKET3_SET_PREDICATION = 0x20 +PACKET3_REG_RMW = 0x21 +PACKET3_COND_EXEC = 0x22 +PACKET3_PRED_EXEC = 0x23 +PACKET3_DRAW_INDIRECT = 0x24 +PACKET3_DRAW_INDEX_INDIRECT = 0x25 +PACKET3_INDEX_BASE = 0x26 +PACKET3_DRAW_INDEX_2 = 0x27 +PACKET3_CONTEXT_CONTROL = 0x28 +PACKET3_INDEX_TYPE = 0x2A +PACKET3_DRAW_INDIRECT_MULTI = 0x2C +PACKET3_DRAW_INDEX_AUTO = 0x2D +PACKET3_NUM_INSTANCES = 0x2F +PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 +PACKET3_INDIRECT_BUFFER_CONST = 0x33 +PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 +PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 +PACKET3_DRAW_PREAMBLE = 0x36 +PACKET3_WRITE_DATA = 0x37 +WRITE_DATA_DST_SEL = lambda x: ((x) << 8) +WR_ONE_ADDR = (1 << 16) +WR_CONFIRM = (1 << 20) +WRITE_DATA_CACHE_POLICY = lambda x: ((x) << 25) +WRITE_DATA_ENGINE_SEL = lambda x: ((x) << 30) +PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 +PACKET3_MEM_SEMAPHORE = 0x39 +PACKET3_SEM_USE_MAILBOX = (0x1 << 16) +PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1 << 20) +PACKET3_SEM_SEL_SIGNAL = (0x6 << 29) +PACKET3_SEM_SEL_WAIT = (0x7 << 29) +PACKET3_WAIT_REG_MEM = 0x3C +WAIT_REG_MEM_FUNCTION = lambda x: ((x) << 0) +WAIT_REG_MEM_MEM_SPACE = lambda x: ((x) << 4) +WAIT_REG_MEM_OPERATION = lambda x: ((x) << 6) +WAIT_REG_MEM_ENGINE = lambda x: ((x) << 8) +PACKET3_INDIRECT_BUFFER = 0x3F +INDIRECT_BUFFER_VALID = (1 << 23) +INDIRECT_BUFFER_CACHE_POLICY = lambda x: ((x) << 28) +INDIRECT_BUFFER_PRE_ENB = lambda x: ((x) << 21) +INDIRECT_BUFFER_PRE_RESUME = lambda x: ((x) << 30) +PACKET3_COPY_DATA = 0x40 +PACKET3_PFP_SYNC_ME = 0x42 +PACKET3_COND_WRITE = 0x45 +PACKET3_EVENT_WRITE = 0x46 +EVENT_TYPE = lambda x: ((x) << 0) +EVENT_INDEX = lambda x: ((x) << 8) +PACKET3_RELEASE_MEM = 0x49 +EVENT_TYPE = lambda x: ((x) << 0) +EVENT_INDEX = lambda x: ((x) << 8) +EOP_TCL1_VOL_ACTION_EN = (1 << 12) +EOP_TC_VOL_ACTION_EN = (1 << 13) +EOP_TC_WB_ACTION_EN = (1 << 15) +EOP_TCL1_ACTION_EN = (1 << 16) +EOP_TC_ACTION_EN = (1 << 17) +EOP_TC_NC_ACTION_EN = (1 << 19) +EOP_TC_MD_ACTION_EN = (1 << 21) +EOP_EXEC = (1 << 28) +DATA_SEL = lambda x: ((x) << 29) +INT_SEL = lambda x: ((x) << 24) +DST_SEL = lambda x: ((x) << 16) +PACKET3_PREAMBLE_CNTL = 0x4A +PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2 << 28) +PACKET3_PREAMBLE_END_CLEAR_STATE = (3 << 28) +PACKET3_DMA_DATA = 0x50 +PACKET3_DMA_DATA_ENGINE = lambda x: ((x) << 0) +PACKET3_DMA_DATA_SRC_CACHE_POLICY = lambda x: ((x) << 13) +PACKET3_DMA_DATA_DST_SEL = lambda x: ((x) << 20) +PACKET3_DMA_DATA_DST_CACHE_POLICY = lambda x: ((x) << 25) +PACKET3_DMA_DATA_SRC_SEL = lambda x: ((x) << 29) +PACKET3_DMA_DATA_CP_SYNC = (1 << 31) +PACKET3_DMA_DATA_CMD_SAS = (1 << 26) +PACKET3_DMA_DATA_CMD_DAS = (1 << 27) +PACKET3_DMA_DATA_CMD_SAIC = (1 << 28) +PACKET3_DMA_DATA_CMD_DAIC = (1 << 29) +PACKET3_DMA_DATA_CMD_RAW_WAIT = (1 << 30) +PACKET3_ACQUIRE_MEM = 0x58 +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA = lambda x: ((x) << 3) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA = lambda x: ((x) << 4) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA = lambda x: ((x) << 5) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA = lambda x: ((x) << 15) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA = lambda x: ((x) << 18) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA = lambda x: ((x) << 22) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA = lambda x: ((x) << 23) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA = lambda x: ((x) << 25) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA = lambda x: ((x) << 26) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA = lambda x: ((x) << 27) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA = lambda x: ((x) << 28) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA = lambda x: ((x) << 29) +PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA = lambda x: ((x) << 30) +PACKET3_REWIND = 0x59 +PACKET3_LOAD_UCONFIG_REG = 0x5E +PACKET3_LOAD_SH_REG = 0x5F +PACKET3_LOAD_CONFIG_REG = 0x60 +PACKET3_LOAD_CONTEXT_REG = 0x61 +PACKET3_SET_CONFIG_REG = 0x68 +PACKET3_SET_CONFIG_REG_START = 0x00002000 +PACKET3_SET_CONFIG_REG_END = 0x00002c00 +PACKET3_SET_CONTEXT_REG = 0x69 +PACKET3_SET_CONTEXT_REG_START = 0x0000a000 +PACKET3_SET_CONTEXT_REG_END = 0x0000a400 +PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 +PACKET3_SET_SH_REG = 0x76 +PACKET3_SET_SH_REG_START = 0x00002c00 +PACKET3_SET_SH_REG_END = 0x00003000 +PACKET3_SET_SH_REG_OFFSET = 0x77 +PACKET3_SET_QUEUE_REG = 0x78 +PACKET3_SET_UCONFIG_REG = 0x79 +PACKET3_SET_UCONFIG_REG_START = 0x0000c000 +PACKET3_SET_UCONFIG_REG_END = 0x0000c400 +PACKET3_SET_UCONFIG_REG_INDEX_TYPE = (2 << 28) +PACKET3_SCRATCH_RAM_WRITE = 0x7D +PACKET3_SCRATCH_RAM_READ = 0x7E +PACKET3_LOAD_CONST_RAM = 0x80 +PACKET3_WRITE_CONST_RAM = 0x81 +PACKET3_DUMP_CONST_RAM = 0x83 +PACKET3_INCREMENT_CE_COUNTER = 0x84 +PACKET3_INCREMENT_DE_COUNTER = 0x85 +PACKET3_WAIT_ON_CE_COUNTER = 0x86 +PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 +PACKET3_SWITCH_BUFFER = 0x8B +PACKET3_FRAME_CONTROL = 0x90 +FRAME_TMZ = (1 << 0) +FRAME_CMD = lambda x: ((x) << 28) +PACKET3_INVALIDATE_TLBS = 0x98 +PACKET3_INVALIDATE_TLBS_DST_SEL = lambda x: ((x) << 0) +PACKET3_INVALIDATE_TLBS_ALL_HUB = lambda x: ((x) << 4) +PACKET3_INVALIDATE_TLBS_PASID = lambda x: ((x) << 5) +PACKET3_INVALIDATE_TLBS_FLUSH_TYPE = lambda x: ((x) << 29) +PACKET3_SET_RESOURCES = 0xA0 +PACKET3_SET_RESOURCES_VMID_MASK = lambda x: ((x) << 0) +PACKET3_SET_RESOURCES_UNMAP_LATENTY = lambda x: ((x) << 16) +PACKET3_SET_RESOURCES_QUEUE_TYPE = lambda x: ((x) << 29) +PACKET3_MAP_QUEUES = 0xA2 +PACKET3_MAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) +PACKET3_MAP_QUEUES_VMID = lambda x: ((x) << 8) +PACKET3_MAP_QUEUES_QUEUE = lambda x: ((x) << 13) +PACKET3_MAP_QUEUES_PIPE = lambda x: ((x) << 16) +PACKET3_MAP_QUEUES_ME = lambda x: ((x) << 18) +PACKET3_MAP_QUEUES_QUEUE_TYPE = lambda x: ((x) << 21) +PACKET3_MAP_QUEUES_ALLOC_FORMAT = lambda x: ((x) << 24) +PACKET3_MAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) +PACKET3_MAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) +PACKET3_MAP_QUEUES_CHECK_DISABLE = lambda x: ((x) << 1) +PACKET3_MAP_QUEUES_DOORBELL_OFFSET = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES = 0xA3 +PACKET3_UNMAP_QUEUES_ACTION = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) +PACKET3_UNMAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) +PACKET3_UNMAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) +PACKET3_UNMAP_QUEUES_PASID = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_RB_WPTR = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3 = lambda x: ((x) << 2) +PACKET3_QUERY_STATUS = 0xA4 +PACKET3_QUERY_STATUS_CONTEXT_ID = lambda x: ((x) << 0) +PACKET3_QUERY_STATUS_INTERRUPT_SEL = lambda x: ((x) << 28) +PACKET3_QUERY_STATUS_COMMAND = lambda x: ((x) << 30) +PACKET3_QUERY_STATUS_PASID = lambda x: ((x) << 0) +PACKET3_QUERY_STATUS_DOORBELL_OFFSET = lambda x: ((x) << 2) +PACKET3_QUERY_STATUS_ENG_SEL = lambda x: ((x) << 25) +PACKET3_RUN_CLEANER_SHADER = 0xD2 +VCE_CMD_NO_OP = 0x00000000 +VCE_CMD_END = 0x00000001 +VCE_CMD_IB = 0x00000002 +VCE_CMD_FENCE = 0x00000003 +VCE_CMD_TRAP = 0x00000004 +VCE_CMD_IB_AUTO = 0x00000005 +VCE_CMD_SEMAPHORE = 0x00000006 +VCE_CMD_IB_VM = 0x00000102 +VCE_CMD_WAIT_GE = 0x00000106 +VCE_CMD_UPDATE_PTB = 0x00000107 +VCE_CMD_FLUSH_TLB = 0x00000108 +VCE_CMD_REG_WRITE = 0x00000109 +VCE_CMD_REG_WAIT = 0x0000010a +HEVC_ENC_CMD_NO_OP = 0x00000000 +HEVC_ENC_CMD_END = 0x00000001 +HEVC_ENC_CMD_FENCE = 0x00000003 +HEVC_ENC_CMD_TRAP = 0x00000004 +HEVC_ENC_CMD_IB_VM = 0x00000102 +HEVC_ENC_CMD_REG_WRITE = 0x00000109 +HEVC_ENC_CMD_REG_WAIT = 0x0000010a \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/sdma_4_0_0.py b/tinygrad/runtime/autogen/am/sdma_4_0_0.py index 14f7ee660e..c0eaf06e40 100644 --- a/tinygrad/runtime/autogen/am/sdma_4_0_0.py +++ b/tinygrad/runtime/autogen/am/sdma_4_0_0.py @@ -1,5211 +1,2639 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__VEGA10_SDMA_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_DUMMY_TRAP = 16 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_PKT_HEADER_op_offset = 0 # macro -SDMA_PKT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_op_shift = 0 # macro -def SDMA_PKT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_INDIRECT', 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', - 'SDMA_OP_PRE_EXE', 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', - 'SDMA_OP_SRBM_WRITE', 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', - 'SDMA_OP_WRITE', 'SDMA_PKT_ATOMIC', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_mask', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_offset', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', - 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', - 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', - 'SDMA_PKT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_PHY', 'SDMA_SUBOP_COPY_LINEAR_RECT', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_TILED', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', - 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', - 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', - 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', - 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', '__VEGA10_SDMA_PKT_OPEN_H_', - 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('extra_info', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0._fields_ = [ + ('reserved_0', ctypes.c_uint32,16), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_1', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), + ('PARAMETER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR = rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved', ctypes.c_uint32,13), + ('element', ctypes.c_uint32,3), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0._fields_ = [ + ('src_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('src_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0._fields_ = [ + ('src_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('src_pitch', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0._fields_ = [ + ('src_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0._fields_ = [ + ('dst_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('dst_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0), + ('DW_8_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0._fields_ = [ + ('dst_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('dst_pitch', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0), + ('DW_9_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0._fields_ = [ + ('dst_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0), + ('DW_10_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0._fields_ = [ + ('rect_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('rect_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0), + ('DW_11_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0._fields_ = [ + ('rect_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,5), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_3', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0), + ('DW_12_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), + ('SRC_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), + ('SRC_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), + ('SRC_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), + ('DST_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), + ('DST_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), + ('DST_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), + ('RECT_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), + ('RECT_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT = rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('sw', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,12), + ('fillsize', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL = rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG +class rocr_AMD_SDMA_PKT_FENCE_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('mtype', ctypes.c_uint32,3), + ('gcc', ctypes.c_uint32,1), + ('sys', ctypes.c_uint32,1), + ('pad1', ctypes.c_uint32,1), + ('snp', ctypes.c_uint32,1), + ('gpa', ctypes.c_uint32,1), + ('l2_policy', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0._fields_ = [ + ('data', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION), +] +rocr_AMD_SDMA_PKT_FENCE = rocr_AMD_SDMA_PKT_FENCE_TAG +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,10), + ('hdp_flush', ctypes.c_uint32,1), + ('reserved_1', ctypes.c_uint32,1), + ('func', ctypes.c_uint32,3), + ('mem_poll', ctypes.c_uint32,1), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0._fields_ = [ + ('value', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0._fields_ = [ + ('mask', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0._fields_ = [ + ('interval', ctypes.c_uint32,16), + ('retry_count', ctypes.c_uint32,12), + ('reserved_0', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), + ('VALUE_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), + ('MASK_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), + ('DW5_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM = rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG +class rocr_AMD_SDMA_PKT_ATOMIC_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('l', ctypes.c_uint32,1), + ('reserved_0', ctypes.c_uint32,8), + ('operation', ctypes.c_uint32,7), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0._fields_ = [ + ('src_data_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0._fields_ = [ + ('cmp_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0._fields_ = [ + ('cmp_data_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0._fields_ = [ + ('loop_interval', ctypes.c_uint32,13), + ('reserved_0', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), + ('SRC_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), + ('SRC_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), + ('CMP_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), + ('CMP_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), + ('LOOP_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), +] +rocr_AMD_SDMA_PKT_ATOMIC = rocr_AMD_SDMA_PKT_ATOMIC_TAG +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), +] +rocr_AMD_SDMA_PKT_TIMESTAMP = rocr_AMD_SDMA_PKT_TIMESTAMP_TAG +class rocr_AMD_SDMA_PKT_TRAP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0._fields_ = [ + ('int_ctx', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_TRAP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION), + ('INT_CONTEXT_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), +] +rocr_AMD_SDMA_PKT_TRAP = rocr_AMD_SDMA_PKT_TRAP_TAG +class rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG(Struct): pass +rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ + ('DW_0_DATA', ctypes.c_uint32), + ('DW_1_DATA', ctypes.c_uint32), + ('DW_2_DATA', ctypes.c_uint32), + ('DW_3_DATA', ctypes.c_uint32), + ('DW_4_DATA', ctypes.c_uint32), + ('DW_5_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_HDP_FLUSH = rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG +class rocr_AMD_SDMA_PKT_GCR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0._fields_ = [ + ('', ctypes.c_uint32,7), + ('BaseVA_LO', ctypes.c_uint32,25), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0._fields_ = [ + ('BaseVA_HI', ctypes.c_uint32,16), + ('GCR_CONTROL_GLI_INV', ctypes.c_uint32,2), + ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GLM_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLM_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLV_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL1_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_US', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_WB', ctypes.c_uint32,1), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0._fields_ = [ + ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32,1), + ('GCR_CONTROL_SEQ', ctypes.c_uint32,2), + ('', ctypes.c_uint32,4), + ('LimitVA_LO', ctypes.c_uint32,25), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0._fields_ = [ + ('LimitVA_HI', ctypes.c_uint32,16), + ('', ctypes.c_uint32,8), + ('VMID', ctypes.c_uint32,4), + ('', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_GCR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION), + ('WORD1_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION), + ('WORD2_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION), + ('WORD3_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION), + ('WORD4_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION), +] +rocr_AMD_SDMA_PKT_GCR = rocr_AMD_SDMA_PKT_GCR_TAG +SDMA_OP_COPY = 1 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_GCR = 17 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_RECT = 4 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_USER_GCR = 1 +SDMA_ATOMIC_ADD64 = 47 +SDMA_OP_NOP = 0 +SDMA_OP_COPY = 1 +SDMA_OP_WRITE = 2 +SDMA_OP_INDIRECT = 4 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_SEM = 7 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_COND_EXE = 9 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_PTEPDE = 12 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_SRBM_WRITE = 14 +SDMA_OP_PRE_EXE = 15 +SDMA_OP_DUMMY_TRAP = 16 +SDMA_SUBOP_TIMESTAMP_SET = 0 +SDMA_SUBOP_TIMESTAMP_GET = 1 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 +SDMA_SUBOP_COPY_TILED = 1 +SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 +SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 +SDMA_SUBOP_COPY_SOA = 3 +SDMA_SUBOP_COPY_DIRTY_PAGE = 7 +SDMA_SUBOP_COPY_LINEAR_PHY = 8 +SDMA_SUBOP_WRITE_LINEAR = 0 +SDMA_SUBOP_WRITE_TILED = 1 +SDMA_SUBOP_PTEPDE_GEN = 0 +SDMA_SUBOP_PTEPDE_COPY = 1 +SDMA_SUBOP_PTEPDE_RMW = 2 +SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 +SDMA_SUBOP_DATA_FILL_MULTI = 1 +SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 +SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 +SDMA_SUBOP_POLL_MEM_VERIFY = 3 +HEADER_AGENT_DISPATCH = 4 +HEADER_BARRIER = 5 +SDMA_OP_AQL_COPY = 0 +SDMA_OP_AQL_BARRIER_OR = 0 +SDMA_PKT_HEADER_op_offset = 0 +SDMA_PKT_HEADER_op_mask = 0x000000FF +SDMA_PKT_HEADER_op_shift = 0 +SDMA_PKT_HEADER_OP = lambda x: (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) +SDMA_PKT_HEADER_sub_op_offset = 0 +SDMA_PKT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_HEADER_sub_op_shift = 8 +SDMA_PKT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) +SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) +SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) +SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) +SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_TILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) +SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_TILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) +SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 +SDMA_PKT_COPY_TILED_HEADER_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_HEADER_mip_max_shift) +SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 +SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 +SDMA_PKT_COPY_TILED_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) +SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 +SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 +SDMA_PKT_COPY_TILED_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) +SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 +SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF +SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 +SDMA_PKT_COPY_TILED_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) +SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 +SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 +SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) +SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 +SDMA_PKT_COPY_TILED_DW_5_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) +SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF +SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 +SDMA_PKT_COPY_TILED_DW_5_EPITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_epitch_mask) << SDMA_PKT_COPY_TILED_DW_5_epitch_shift) +SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 +SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 +SDMA_PKT_COPY_TILED_DW_6_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) +SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 +SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 +SDMA_PKT_COPY_TILED_DW_6_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) +SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 +SDMA_PKT_COPY_TILED_DW_7_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) +SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) +SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_DW_7_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 +SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 +SDMA_PKT_COPY_TILED_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) +SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 +SDMA_PKT_COPY_T2T_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) +SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_T2T_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) +SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_T2T_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) +SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 +SDMA_PKT_COPY_T2T_HEADER_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_mip_max_mask) << SDMA_PKT_COPY_T2T_HEADER_mip_max_shift) +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) +SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) +SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) +SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 +SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 +SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) +SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 +SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 +SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) +SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 +SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF +SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 +SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) +SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 +SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 +SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) +SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 +SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) +SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF +SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 +SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask) << SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift) +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 +SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_9_DST_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) +SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 +SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_9_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) +SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 +SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_10_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) +SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 +SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 +SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) +SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 +SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 +SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) +SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 +SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF +SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 +SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 +SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 +SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 +SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF +SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 +SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift) +SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 +SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_13_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) +SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 +SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_13_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) +SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_14_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) +SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 +SDMA_PKT_COPY_T2T_DW_14_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) +SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 +SDMA_PKT_COPY_T2T_DW_14_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) +SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 +SDMA_PKT_COPY_STRUCT_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) +SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_STRUCT_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) +SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 +SDMA_PKT_COPY_STRUCT_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 +SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) +SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 +SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 +SDMA_PKT_COPY_STRUCT_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) +SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF +SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 +SDMA_PKT_COPY_STRUCT_DW_5_STRIDE = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 +SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_mask = 0x00000003 +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_shift = 24 +SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_shift) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 +SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 +SDMA_PKT_WRITE_UNTILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 +SDMA_PKT_WRITE_UNTILED_DW_3_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 +SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 +SDMA_PKT_WRITE_UNTILED_DW_3_SW = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) +SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 +SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_UNTILED_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) +SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 +SDMA_PKT_WRITE_TILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) +SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_TILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) +SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 +SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) +SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 +SDMA_PKT_WRITE_TILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) +SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F +SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 +SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask) << SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift) +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 +SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 +SDMA_PKT_WRITE_TILED_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) +SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 +SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 +SDMA_PKT_WRITE_TILED_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) +SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 +SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF +SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 +SDMA_PKT_WRITE_TILED_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) +SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 +SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 +SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) +SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 +SDMA_PKT_WRITE_TILED_DW_5_DIMENSION = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) +SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF +SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 +SDMA_PKT_WRITE_TILED_DW_5_EPITCH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_epitch_mask) << SDMA_PKT_WRITE_TILED_DW_5_epitch_shift) +SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 +SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 +SDMA_PKT_WRITE_TILED_DW_6_X = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) +SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 +SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 +SDMA_PKT_WRITE_TILED_DW_6_Y = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) +SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF +SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 +SDMA_PKT_WRITE_TILED_DW_7_Z = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) +SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 +SDMA_PKT_WRITE_TILED_DW_7_SW = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) +SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 +SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 +SDMA_PKT_WRITE_TILED_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) +SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 +SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_TILED_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 +SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 +SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 +SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) +SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 +SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF +SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 +SDMA_PKT_PTEPDE_COPY_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 +SDMA_PKT_PTEPDE_RMW_HEADER_GCC = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 +SDMA_PKT_PTEPDE_RMW_HEADER_SYS = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 +SDMA_PKT_PTEPDE_RMW_HEADER_SNP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 +SDMA_PKT_PTEPDE_RMW_HEADER_GPA = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) +SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 +SDMA_PKT_WRITE_INCR_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) +SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_INCR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) +SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 +SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF +SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 +SDMA_PKT_WRITE_INCR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) +SDMA_PKT_INDIRECT_HEADER_op_offset = 0 +SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF +SDMA_PKT_INDIRECT_HEADER_op_shift = 0 +SDMA_PKT_INDIRECT_HEADER_OP = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) +SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 +SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 +SDMA_PKT_INDIRECT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) +SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 +SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F +SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 +SDMA_PKT_INDIRECT_HEADER_VMID = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 +SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0 = lambda x: (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 +SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32 = lambda x: (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 +SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE = lambda x: (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 +SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 +SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) +SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF +SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 +SDMA_PKT_SEMAPHORE_HEADER_OP = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) +SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 +SDMA_PKT_SEMAPHORE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) +SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 +SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) +SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 +SDMA_PKT_SEMAPHORE_HEADER_SIGNAL = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) +SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 +SDMA_PKT_SEMAPHORE_HEADER_MAILBOX = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_FENCE_HEADER_op_offset = 0 +SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF +SDMA_PKT_FENCE_HEADER_op_shift = 0 +SDMA_PKT_FENCE_HEADER_OP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) +SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 +SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 +SDMA_PKT_FENCE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_FENCE_DATA_data_offset = 3 +SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_DATA_data_shift = 0 +SDMA_PKT_FENCE_DATA_DATA = lambda x: (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) +SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF +SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 +SDMA_PKT_SRBM_WRITE_HEADER_OP = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 +SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 +SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) +SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 +SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF +SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 +SDMA_PKT_SRBM_WRITE_ADDR_ADDR = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) +SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 +SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF +SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 +SDMA_PKT_SRBM_WRITE_DATA_DATA = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) +SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 +SDMA_PKT_PRE_EXE_HEADER_OP = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) +SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 +SDMA_PKT_PRE_EXE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) +SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 +SDMA_PKT_PRE_EXE_HEADER_DEV_SEL = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 +SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT = lambda x: (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) +SDMA_PKT_COND_EXE_HEADER_op_offset = 0 +SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COND_EXE_HEADER_op_shift = 0 +SDMA_PKT_COND_EXE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) +SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 +SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 +SDMA_PKT_COND_EXE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 +SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 +SDMA_PKT_COND_EXE_REFERENCE_REFERENCE = lambda x: (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 +SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT = lambda x: (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF +SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_OP = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 +SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 +SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 +SDMA_PKT_CONSTANT_FILL_HEADER_SW = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 +SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 +SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) +SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 +SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 +SDMA_PKT_CONSTANT_FILL_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_OP = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 +SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 +SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) +SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_REGMEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 +SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) +SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 +SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 +SDMA_PKT_POLL_REGMEM_HEADER_FUNC = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 +SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 +SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 +SDMA_PKT_POLL_REGMEM_VALUE_VALUE = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) +SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 +SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 +SDMA_PKT_POLL_REGMEM_MASK_MASK = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) +SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 +SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF +SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 +SDMA_PKT_POLL_REGMEM_DW5_INTERVAL = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) +SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 +SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF +SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 +SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) +SDMA_PKT_ATOMIC_HEADER_op_offset = 0 +SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF +SDMA_PKT_ATOMIC_HEADER_op_shift = 0 +SDMA_PKT_ATOMIC_HEADER_OP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) +SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 +SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 +SDMA_PKT_ATOMIC_HEADER_LOOP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) +SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 +SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 +SDMA_PKT_ATOMIC_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) +SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 +SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F +SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 +SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 +SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 +SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 +SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 +SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 +SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL = lambda x: (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) +SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) +SDMA_PKT_TRAP_HEADER_op_offset = 0 +SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF +SDMA_PKT_TRAP_HEADER_op_shift = 0 +SDMA_PKT_TRAP_HEADER_OP = lambda x: (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) +SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 +SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 +SDMA_PKT_TRAP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) +SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 +SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF +SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 +SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT = lambda x: (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) +SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF +SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_OP = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 +SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) +SDMA_PKT_NOP_HEADER_op_offset = 0 +SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF +SDMA_PKT_NOP_HEADER_op_shift = 0 +SDMA_PKT_NOP_HEADER_OP = lambda x: (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) +SDMA_PKT_NOP_HEADER_sub_op_offset = 0 +SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_NOP_HEADER_sub_op_shift = 8 +SDMA_PKT_NOP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) +SDMA_PKT_NOP_HEADER_count_offset = 0 +SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF +SDMA_PKT_NOP_HEADER_count_shift = 16 +SDMA_PKT_NOP_HEADER_COUNT = lambda x: (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) +SDMA_PKT_NOP_DATA0_data0_offset = 1 +SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_NOP_DATA0_data0_shift = 0 +SDMA_PKT_NOP_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) +SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 +SDMA_AQL_PKT_HEADER_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) +SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_HEADER_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_HEADER_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) +SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 +SDMA_AQL_PKT_HEADER_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) +SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 +SDMA_AQL_PKT_HEADER_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 +SDMA_AQL_PKT_BARRIER_OR_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 +SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/sdma_4_4_2.py b/tinygrad/runtime/autogen/am/sdma_4_4_2.py deleted file mode 100644 index 14f7ee660e..0000000000 --- a/tinygrad/runtime/autogen/am/sdma_4_4_2.py +++ /dev/null @@ -1,5211 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__VEGA10_SDMA_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_DUMMY_TRAP = 16 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_PKT_HEADER_op_offset = 0 # macro -SDMA_PKT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_op_shift = 0 # macro -def SDMA_PKT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_T2T_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_MIP_ID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift = 20 # macro -def SDMA_PKT_WRITE_TILED_HEADER_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_epitch_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_mask = 0x0000FFFF # macro -SDMA_PKT_WRITE_TILED_DW_5_epitch_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_EPITCH(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_INDIRECT', 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', - 'SDMA_OP_PRE_EXE', 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', - 'SDMA_OP_SRBM_WRITE', 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', - 'SDMA_OP_WRITE', 'SDMA_PKT_ATOMIC', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_epitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_epitch_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_T2T_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_mask', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_offset', - 'SDMA_PKT_COPY_TILED_DW_5_epitch_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_epitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', - 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', - 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', - 'SDMA_PKT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_epitch_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_PHY', 'SDMA_SUBOP_COPY_LINEAR_RECT', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_TILED', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', - 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', - 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', - 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', - 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', '__VEGA10_SDMA_PKT_OPEN_H_', - 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] diff --git a/tinygrad/runtime/autogen/am/sdma_5_0_0.py b/tinygrad/runtime/autogen/am/sdma_5_0_0.py index 57f541bee5..d2790985b5 100644 --- a/tinygrad/runtime/autogen/am/sdma_5_0_0.py +++ b/tinygrad/runtime/autogen/am/sdma_5_0_0.py @@ -1,7105 +1,3591 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__NAVI10_SDMA_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_GPUVM_INV = 16 # macro -SDMA_OP_GCR_REQ = 17 # macro -SDMA_OP_DUMMY_TRAP = 32 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro -SDMA_SUBOP_COPY_TILED_BC = 17 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_WRITE_TILED_BC = 17 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -SDMA_SUBOP_VM_INVALIDATION = 4 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_GCR_RANGE_IS_PA = (1<<18) # macro -def SDMA_GCR_SEQ(x): # macro - return (((x)&0x3)<<16) -SDMA_GCR_GL2_WB = (1<<15) # macro -SDMA_GCR_GL2_INV = (1<<14) # macro -SDMA_GCR_GL2_DISCARD = (1<<13) # macro -def SDMA_GCR_GL2_RANGE(x): # macro - return (((x)&0x3)<<11) -SDMA_GCR_GL2_US = (1<<10) # macro -SDMA_GCR_GL1_INV = (1<<9) # macro -SDMA_GCR_GLV_INV = (1<<8) # macro -SDMA_GCR_GLK_INV = (1<<7) # macro -SDMA_GCR_GLK_WB = (1<<6) # macro -SDMA_GCR_GLM_INV = (1<<5) # macro -SDMA_GCR_GLM_WB = (1<<4) # macro -def SDMA_GCR_GL1_RANGE(x): # macro - return (((x)&0x3)<<2) -def SDMA_GCR_GLI_INV(x): # macro - return (((x)&0x3)<<0) -SDMA_PKT_HEADER_op_offset = 0 # macro -SDMA_PKT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_op_shift = 0 # macro -def SDMA_PKT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 22 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 30 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 22 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 30 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift = 20 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 11 # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro - return ((x&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro -SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro -def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_FENCE_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro -def SDMA_PKT_FENCE_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro -def SDMA_PKT_FENCE_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_FENCE_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro - return (((x)&0x0000001F)<<24) -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro - return (((x)&0x000001FF)<<23) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro - return (((x)&0x00000001)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro - return (((x)&0x7FFFFFFF)<<1) -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro - return (((x)&0x0000003F)<<0) -SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro -def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV', - 'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV', - 'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB', - 'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT', - 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE', - 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE', - 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE', - 'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', - 'SDMA_PKT_FENCE_HEADER_gcc_mask', - 'SDMA_PKT_FENCE_HEADER_gcc_offset', - 'SDMA_PKT_FENCE_HEADER_gcc_shift', - 'SDMA_PKT_FENCE_HEADER_gpa_mask', - 'SDMA_PKT_FENCE_HEADER_gpa_offset', - 'SDMA_PKT_FENCE_HEADER_gpa_shift', - 'SDMA_PKT_FENCE_HEADER_l2_policy_mask', - 'SDMA_PKT_FENCE_HEADER_l2_policy_offset', - 'SDMA_PKT_FENCE_HEADER_l2_policy_shift', - 'SDMA_PKT_FENCE_HEADER_mtype_mask', - 'SDMA_PKT_FENCE_HEADER_mtype_offset', - 'SDMA_PKT_FENCE_HEADER_mtype_shift', - 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_snp_mask', - 'SDMA_PKT_FENCE_HEADER_snp_offset', - 'SDMA_PKT_FENCE_HEADER_snp_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', - 'SDMA_PKT_FENCE_HEADER_sys_mask', - 'SDMA_PKT_FENCE_HEADER_sys_offset', - 'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_GCR_REQ_HEADER_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_op_shift', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_op_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift', - 'SDMA_PKT_HDP_FLUSH', 'SDMA_PKT_HEADER_op_mask', - 'SDMA_PKT_HEADER_op_offset', 'SDMA_PKT_HEADER_op_shift', - 'SDMA_PKT_HEADER_sub_op_mask', 'SDMA_PKT_HEADER_sub_op_offset', - 'SDMA_PKT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_priv_mask', - 'SDMA_PKT_INDIRECT_HEADER_priv_offset', - 'SDMA_PKT_INDIRECT_HEADER_priv_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY', - 'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', 'SDMA_SUBOP_POLL_MEM_VERIFY', - 'SDMA_SUBOP_POLL_REG_WRITE_MEM', 'SDMA_SUBOP_PTEPDE_COPY', - 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', 'SDMA_SUBOP_PTEPDE_GEN', - 'SDMA_SUBOP_PTEPDE_RMW', 'SDMA_SUBOP_TIMESTAMP_GET', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_TIMESTAMP_SET', - 'SDMA_SUBOP_USER_GCR', 'SDMA_SUBOP_VM_INVALIDATION', - 'SDMA_SUBOP_WRITE_LINEAR', 'SDMA_SUBOP_WRITE_TILED', - 'SDMA_SUBOP_WRITE_TILED_BC', '__NAVI10_SDMA_PKT_OPEN_H_', - 'hdp_flush_cmd', 'struct_SDMA_PKT_ATOMIC_TAG', - 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('extra_info', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0._fields_ = [ + ('reserved_0', ctypes.c_uint32,16), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_1', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), + ('PARAMETER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR = rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved', ctypes.c_uint32,13), + ('element', ctypes.c_uint32,3), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0._fields_ = [ + ('src_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('src_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0._fields_ = [ + ('src_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('src_pitch', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0._fields_ = [ + ('src_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0._fields_ = [ + ('dst_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('dst_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0), + ('DW_8_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0._fields_ = [ + ('dst_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('dst_pitch', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0), + ('DW_9_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0._fields_ = [ + ('dst_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0), + ('DW_10_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0._fields_ = [ + ('rect_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('rect_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0), + ('DW_11_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0._fields_ = [ + ('rect_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,5), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_3', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0), + ('DW_12_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), + ('SRC_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), + ('SRC_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), + ('SRC_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), + ('DST_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), + ('DST_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), + ('DST_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), + ('RECT_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), + ('RECT_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT = rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('sw', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,12), + ('fillsize', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL = rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG +class rocr_AMD_SDMA_PKT_FENCE_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('mtype', ctypes.c_uint32,3), + ('gcc', ctypes.c_uint32,1), + ('sys', ctypes.c_uint32,1), + ('pad1', ctypes.c_uint32,1), + ('snp', ctypes.c_uint32,1), + ('gpa', ctypes.c_uint32,1), + ('l2_policy', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0._fields_ = [ + ('data', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION), +] +rocr_AMD_SDMA_PKT_FENCE = rocr_AMD_SDMA_PKT_FENCE_TAG +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,10), + ('hdp_flush', ctypes.c_uint32,1), + ('reserved_1', ctypes.c_uint32,1), + ('func', ctypes.c_uint32,3), + ('mem_poll', ctypes.c_uint32,1), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0._fields_ = [ + ('value', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0._fields_ = [ + ('mask', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0._fields_ = [ + ('interval', ctypes.c_uint32,16), + ('retry_count', ctypes.c_uint32,12), + ('reserved_0', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), + ('VALUE_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), + ('MASK_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), + ('DW5_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM = rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG +class rocr_AMD_SDMA_PKT_ATOMIC_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('l', ctypes.c_uint32,1), + ('reserved_0', ctypes.c_uint32,8), + ('operation', ctypes.c_uint32,7), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0._fields_ = [ + ('src_data_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0._fields_ = [ + ('cmp_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0._fields_ = [ + ('cmp_data_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0._fields_ = [ + ('loop_interval', ctypes.c_uint32,13), + ('reserved_0', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), + ('SRC_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), + ('SRC_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), + ('CMP_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), + ('CMP_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), + ('LOOP_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), +] +rocr_AMD_SDMA_PKT_ATOMIC = rocr_AMD_SDMA_PKT_ATOMIC_TAG +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), +] +rocr_AMD_SDMA_PKT_TIMESTAMP = rocr_AMD_SDMA_PKT_TIMESTAMP_TAG +class rocr_AMD_SDMA_PKT_TRAP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0._fields_ = [ + ('int_ctx', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_TRAP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION), + ('INT_CONTEXT_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), +] +rocr_AMD_SDMA_PKT_TRAP = rocr_AMD_SDMA_PKT_TRAP_TAG +class rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG(Struct): pass +rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ + ('DW_0_DATA', ctypes.c_uint32), + ('DW_1_DATA', ctypes.c_uint32), + ('DW_2_DATA', ctypes.c_uint32), + ('DW_3_DATA', ctypes.c_uint32), + ('DW_4_DATA', ctypes.c_uint32), + ('DW_5_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_HDP_FLUSH = rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG +class rocr_AMD_SDMA_PKT_GCR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0._fields_ = [ + ('', ctypes.c_uint32,7), + ('BaseVA_LO', ctypes.c_uint32,25), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0._fields_ = [ + ('BaseVA_HI', ctypes.c_uint32,16), + ('GCR_CONTROL_GLI_INV', ctypes.c_uint32,2), + ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GLM_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLM_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLV_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL1_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_US', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_WB', ctypes.c_uint32,1), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0._fields_ = [ + ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32,1), + ('GCR_CONTROL_SEQ', ctypes.c_uint32,2), + ('', ctypes.c_uint32,4), + ('LimitVA_LO', ctypes.c_uint32,25), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0._fields_ = [ + ('LimitVA_HI', ctypes.c_uint32,16), + ('', ctypes.c_uint32,8), + ('VMID', ctypes.c_uint32,4), + ('', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_GCR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION), + ('WORD1_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION), + ('WORD2_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION), + ('WORD3_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION), + ('WORD4_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION), +] +rocr_AMD_SDMA_PKT_GCR = rocr_AMD_SDMA_PKT_GCR_TAG +SDMA_OP_COPY = 1 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_GCR = 17 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_RECT = 4 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_USER_GCR = 1 +SDMA_ATOMIC_ADD64 = 47 +SDMA_OP_NOP = 0 +SDMA_OP_COPY = 1 +SDMA_OP_WRITE = 2 +SDMA_OP_INDIRECT = 4 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_SEM = 7 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_COND_EXE = 9 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_PTEPDE = 12 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_SRBM_WRITE = 14 +SDMA_OP_PRE_EXE = 15 +SDMA_OP_GPUVM_INV = 16 +SDMA_OP_GCR_REQ = 17 +SDMA_OP_DUMMY_TRAP = 32 +SDMA_SUBOP_TIMESTAMP_SET = 0 +SDMA_SUBOP_TIMESTAMP_GET = 1 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 +SDMA_SUBOP_COPY_TILED = 1 +SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 +SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 +SDMA_SUBOP_COPY_SOA = 3 +SDMA_SUBOP_COPY_DIRTY_PAGE = 7 +SDMA_SUBOP_COPY_LINEAR_PHY = 8 +SDMA_SUBOP_COPY_LINEAR_BC = 16 +SDMA_SUBOP_COPY_TILED_BC = 17 +SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 +SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 +SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 +SDMA_SUBOP_WRITE_LINEAR = 0 +SDMA_SUBOP_WRITE_TILED = 1 +SDMA_SUBOP_WRITE_TILED_BC = 17 +SDMA_SUBOP_PTEPDE_GEN = 0 +SDMA_SUBOP_PTEPDE_COPY = 1 +SDMA_SUBOP_PTEPDE_RMW = 2 +SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 +SDMA_SUBOP_DATA_FILL_MULTI = 1 +SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 +SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 +SDMA_SUBOP_POLL_MEM_VERIFY = 3 +SDMA_SUBOP_VM_INVALIDATION = 4 +HEADER_AGENT_DISPATCH = 4 +HEADER_BARRIER = 5 +SDMA_OP_AQL_COPY = 0 +SDMA_OP_AQL_BARRIER_OR = 0 +SDMA_GCR_RANGE_IS_PA = (1 << 18) +SDMA_GCR_SEQ = lambda x: (((x) & 0x3) << 16) +SDMA_GCR_GL2_WB = (1 << 15) +SDMA_GCR_GL2_INV = (1 << 14) +SDMA_GCR_GL2_DISCARD = (1 << 13) +SDMA_GCR_GL2_RANGE = lambda x: (((x) & 0x3) << 11) +SDMA_GCR_GL2_US = (1 << 10) +SDMA_GCR_GL1_INV = (1 << 9) +SDMA_GCR_GLV_INV = (1 << 8) +SDMA_GCR_GLK_INV = (1 << 7) +SDMA_GCR_GLK_WB = (1 << 6) +SDMA_GCR_GLM_INV = (1 << 5) +SDMA_GCR_GLM_WB = (1 << 4) +SDMA_GCR_GL1_RANGE = lambda x: (((x) & 0x3) << 2) +SDMA_GCR_GLI_INV = lambda x: (((x) & 0x3) << 0) +SDMA_PKT_HEADER_op_offset = 0 +SDMA_PKT_HEADER_op_mask = 0x000000FF +SDMA_PKT_HEADER_op_shift = 0 +SDMA_PKT_HEADER_OP = lambda x: (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) +SDMA_PKT_HEADER_sub_op_offset = 0 +SDMA_PKT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_HEADER_sub_op_shift = 8 +SDMA_PKT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) +SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 +SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) +SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 22 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 30 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 22 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 30 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) +SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) +SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_TILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) +SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_TILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) +SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 +SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 +SDMA_PKT_COPY_TILED_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) +SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 +SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 +SDMA_PKT_COPY_TILED_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) +SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 +SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 +SDMA_PKT_COPY_TILED_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) +SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 +SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 +SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) +SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 +SDMA_PKT_COPY_TILED_DW_5_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) +SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 +SDMA_PKT_COPY_TILED_DW_5_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) +SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 +SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 +SDMA_PKT_COPY_TILED_DW_6_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) +SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 +SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 +SDMA_PKT_COPY_TILED_DW_6_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) +SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 +SDMA_PKT_COPY_TILED_DW_7_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) +SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) +SDMA_PKT_COPY_TILED_DW_7_linear_cc_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask = 0x00000001 +SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift = 20 +SDMA_PKT_COPY_TILED_DW_7_LINEAR_CC = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cc_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cc_shift) +SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_DW_7_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 +SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 +SDMA_PKT_COPY_TILED_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) +SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_BC_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 +SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) +SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 +SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) +SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 +SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF +SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 +SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 +SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 +SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 +SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 +SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 +SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 +SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 +SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 +SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) +SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 +SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_6_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) +SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 +SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 +SDMA_PKT_COPY_TILED_BC_DW_6_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) +SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 +SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_7_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 11 +SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 +SDMA_PKT_COPY_TILED_BC_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) +SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 +SDMA_PKT_COPY_T2T_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) +SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_T2T_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) +SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_T2T_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) +SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 +SDMA_PKT_COPY_T2T_HEADER_DCC = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 +SDMA_PKT_COPY_T2T_HEADER_DCC_DIR = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) +SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) +SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) +SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 +SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 +SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) +SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 +SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 +SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) +SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 +SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 +SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) +SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 +SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 +SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) +SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 +SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 +SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 +SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 +SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_9_DST_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) +SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 +SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_9_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) +SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 +SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_10_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) +SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 +SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 +SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) +SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 +SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 +SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) +SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 +SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 +SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 +SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 +SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 +SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 +SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 +SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) +SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 +SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_13_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) +SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 +SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_13_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) +SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_14_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) +SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 +SDMA_PKT_COPY_T2T_DW_14_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) +SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 +SDMA_PKT_COPY_T2T_DW_14_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 +SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 +SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 +SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 +SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 +SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 +SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 +SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 +SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 +SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) +SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_T2T_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_9_DST_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 +SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT = lambda x: ((x & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) +SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 +SDMA_PKT_COPY_STRUCT_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) +SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_STRUCT_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) +SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 +SDMA_PKT_COPY_STRUCT_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 +SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) +SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 +SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 +SDMA_PKT_COPY_STRUCT_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) +SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF +SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 +SDMA_PKT_COPY_STRUCT_DW_5_STRIDE = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 +SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_mask = 0x00000003 +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_shift = 24 +SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_shift) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 +SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 +SDMA_PKT_WRITE_UNTILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 +SDMA_PKT_WRITE_UNTILED_DW_3_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 +SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 +SDMA_PKT_WRITE_UNTILED_DW_3_SW = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) +SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 +SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_UNTILED_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) +SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 +SDMA_PKT_WRITE_TILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) +SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_TILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) +SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 +SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) +SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 +SDMA_PKT_WRITE_TILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 +SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 +SDMA_PKT_WRITE_TILED_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) +SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 +SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 +SDMA_PKT_WRITE_TILED_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) +SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 +SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF +SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 +SDMA_PKT_WRITE_TILED_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) +SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 +SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 +SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) +SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 +SDMA_PKT_WRITE_TILED_DW_5_DIMENSION = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) +SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F +SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 +SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) +SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 +SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 +SDMA_PKT_WRITE_TILED_DW_6_X = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) +SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 +SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 +SDMA_PKT_WRITE_TILED_DW_6_Y = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) +SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF +SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 +SDMA_PKT_WRITE_TILED_DW_7_Z = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) +SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 +SDMA_PKT_WRITE_TILED_DW_7_SW = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) +SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 +SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 +SDMA_PKT_WRITE_TILED_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) +SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 +SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_TILED_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) +SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 +SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 +SDMA_PKT_WRITE_TILED_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 +SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) +SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 +SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 +SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 +SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 +SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 +SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 +SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 +SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 +SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 +SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 +SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) +SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 +SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_6_X = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) +SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 +SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 +SDMA_PKT_WRITE_TILED_BC_DW_6_Y = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) +SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 +SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF +SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_7_Z = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 +SDMA_PKT_WRITE_TILED_BC_DW_7_SW = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) +SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 +SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 +SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 +SDMA_PKT_PTEPDE_COPY_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 +SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 +SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 +SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) +SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 +SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF +SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 +SDMA_PKT_PTEPDE_COPY_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 +SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 +SDMA_PKT_PTEPDE_RMW_HEADER_GCC = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 +SDMA_PKT_PTEPDE_RMW_HEADER_SYS = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 +SDMA_PKT_PTEPDE_RMW_HEADER_SNP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 +SDMA_PKT_PTEPDE_RMW_HEADER_GPA = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 +SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) +SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 +SDMA_PKT_WRITE_INCR_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) +SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_INCR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) +SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 +SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF +SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 +SDMA_PKT_WRITE_INCR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) +SDMA_PKT_INDIRECT_HEADER_op_offset = 0 +SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF +SDMA_PKT_INDIRECT_HEADER_op_shift = 0 +SDMA_PKT_INDIRECT_HEADER_OP = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) +SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 +SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 +SDMA_PKT_INDIRECT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) +SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 +SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F +SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 +SDMA_PKT_INDIRECT_HEADER_VMID = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) +SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 +SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 +SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 +SDMA_PKT_INDIRECT_HEADER_PRIV = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 +SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0 = lambda x: (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 +SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32 = lambda x: (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 +SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE = lambda x: (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 +SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 +SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) +SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF +SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 +SDMA_PKT_SEMAPHORE_HEADER_OP = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) +SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 +SDMA_PKT_SEMAPHORE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) +SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 +SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) +SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 +SDMA_PKT_SEMAPHORE_HEADER_SIGNAL = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) +SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 +SDMA_PKT_SEMAPHORE_HEADER_MAILBOX = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_FENCE_HEADER_op_offset = 0 +SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF +SDMA_PKT_FENCE_HEADER_op_shift = 0 +SDMA_PKT_FENCE_HEADER_OP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) +SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 +SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 +SDMA_PKT_FENCE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) +SDMA_PKT_FENCE_HEADER_mtype_offset = 0 +SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 +SDMA_PKT_FENCE_HEADER_mtype_shift = 16 +SDMA_PKT_FENCE_HEADER_MTYPE = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) +SDMA_PKT_FENCE_HEADER_gcc_offset = 0 +SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_gcc_shift = 19 +SDMA_PKT_FENCE_HEADER_GCC = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) +SDMA_PKT_FENCE_HEADER_sys_offset = 0 +SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_sys_shift = 20 +SDMA_PKT_FENCE_HEADER_SYS = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) +SDMA_PKT_FENCE_HEADER_snp_offset = 0 +SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_snp_shift = 22 +SDMA_PKT_FENCE_HEADER_SNP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) +SDMA_PKT_FENCE_HEADER_gpa_offset = 0 +SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_gpa_shift = 23 +SDMA_PKT_FENCE_HEADER_GPA = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) +SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 +SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 +SDMA_PKT_FENCE_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_FENCE_DATA_data_offset = 3 +SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_DATA_data_shift = 0 +SDMA_PKT_FENCE_DATA_DATA = lambda x: (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) +SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF +SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 +SDMA_PKT_SRBM_WRITE_HEADER_OP = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 +SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 +SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) +SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 +SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF +SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 +SDMA_PKT_SRBM_WRITE_ADDR_ADDR = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 +SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) +SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 +SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF +SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 +SDMA_PKT_SRBM_WRITE_DATA_DATA = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) +SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 +SDMA_PKT_PRE_EXE_HEADER_OP = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) +SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 +SDMA_PKT_PRE_EXE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) +SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 +SDMA_PKT_PRE_EXE_HEADER_DEV_SEL = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 +SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT = lambda x: (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) +SDMA_PKT_COND_EXE_HEADER_op_offset = 0 +SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COND_EXE_HEADER_op_shift = 0 +SDMA_PKT_COND_EXE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) +SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 +SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 +SDMA_PKT_COND_EXE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 +SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 +SDMA_PKT_COND_EXE_REFERENCE_REFERENCE = lambda x: (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 +SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT = lambda x: (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF +SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_OP = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 +SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 +SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 +SDMA_PKT_CONSTANT_FILL_HEADER_SW = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 +SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 +SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) +SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 +SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 +SDMA_PKT_CONSTANT_FILL_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_OP = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 +SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 +SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) +SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_REGMEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 +SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) +SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 +SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 +SDMA_PKT_POLL_REGMEM_HEADER_FUNC = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 +SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 +SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 +SDMA_PKT_POLL_REGMEM_VALUE_VALUE = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) +SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 +SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 +SDMA_PKT_POLL_REGMEM_MASK_MASK = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) +SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 +SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF +SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 +SDMA_PKT_POLL_REGMEM_DW5_INTERVAL = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) +SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 +SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF +SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 +SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_offset = 4 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP1_END_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp1_end_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_offset = 5 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP1_END_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp1_end_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF +SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_OP = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 +SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 +SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 +SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) +SDMA_PKT_ATOMIC_HEADER_op_offset = 0 +SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF +SDMA_PKT_ATOMIC_HEADER_op_shift = 0 +SDMA_PKT_ATOMIC_HEADER_OP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) +SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 +SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 +SDMA_PKT_ATOMIC_HEADER_LOOP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) +SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 +SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 +SDMA_PKT_ATOMIC_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) +SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 +SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F +SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 +SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 +SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 +SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 +SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 +SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 +SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL = lambda x: (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) +SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) +SDMA_PKT_TRAP_HEADER_op_offset = 0 +SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF +SDMA_PKT_TRAP_HEADER_op_shift = 0 +SDMA_PKT_TRAP_HEADER_OP = lambda x: (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) +SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 +SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 +SDMA_PKT_TRAP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) +SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 +SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF +SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 +SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT = lambda x: (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) +SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF +SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_OP = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 +SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) +SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 +SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF +SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 +SDMA_PKT_GPUVM_INV_HEADER_OP = lambda x: (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) +SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 +SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 +SDMA_PKT_GPUVM_INV_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 +SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 +SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 +SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 +SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 +SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 +SDMA_PKT_GPUVM_INV_PAYLOAD2_S = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 +SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) +SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 +SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF +SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 +SDMA_PKT_GCR_REQ_HEADER_OP = lambda x: (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) +SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 +SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 +SDMA_PKT_GCR_REQ_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 +SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 +SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 +SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 +SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 +SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 +SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 +SDMA_PKT_GCR_REQ_PAYLOAD4_VMID = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) +SDMA_PKT_NOP_HEADER_op_offset = 0 +SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF +SDMA_PKT_NOP_HEADER_op_shift = 0 +SDMA_PKT_NOP_HEADER_OP = lambda x: (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) +SDMA_PKT_NOP_HEADER_sub_op_offset = 0 +SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_NOP_HEADER_sub_op_shift = 8 +SDMA_PKT_NOP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) +SDMA_PKT_NOP_HEADER_count_offset = 0 +SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF +SDMA_PKT_NOP_HEADER_count_shift = 16 +SDMA_PKT_NOP_HEADER_COUNT = lambda x: (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) +SDMA_PKT_NOP_DATA0_data0_offset = 1 +SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_NOP_DATA0_data0_shift = 0 +SDMA_PKT_NOP_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) +SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 +SDMA_AQL_PKT_HEADER_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) +SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_HEADER_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_HEADER_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) +SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 +SDMA_AQL_PKT_HEADER_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) +SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 +SDMA_AQL_PKT_HEADER_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 +SDMA_AQL_PKT_BARRIER_OR_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 +SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_RESERVED_DW12 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW12_reserved_dw12_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/sdma_6_0_0.py b/tinygrad/runtime/autogen/am/sdma_6_0_0.py index 37d2329ca6..0ec83f82a7 100644 --- a/tinygrad/runtime/autogen/am/sdma_6_0_0.py +++ b/tinygrad/runtime/autogen/am/sdma_6_0_0.py @@ -1,8087 +1,4087 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # macro -SDMA_OP_FENCE = 5 # macro -SDMA_OP_TRAP = 6 # macro -SDMA_OP_POLL_REGMEM = 8 # macro -SDMA_OP_ATOMIC = 10 # macro -SDMA_OP_CONST_FILL = 11 # macro -SDMA_OP_TIMESTAMP = 13 # macro -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # macro -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), -] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), -] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), -] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), -] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), -] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), -] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), -] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), -] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), -] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), -] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), -] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), -] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), -] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), -] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), -] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), -] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), -] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), -] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), -] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), -] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), -] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -__SDMA_V6_0_0_PKT_OPEN_H_ = True # macro -SDMA_OP_NOP = 0 # macro -SDMA_OP_WRITE = 2 # macro -SDMA_OP_INDIRECT = 4 # macro -SDMA_OP_SEM = 7 # macro -SDMA_OP_COND_EXE = 9 # macro -SDMA_OP_PTEPDE = 12 # macro -SDMA_OP_SRBM_WRITE = 14 # macro -SDMA_OP_PRE_EXE = 15 # macro -SDMA_OP_GPUVM_INV = 16 # macro -SDMA_OP_GCR_REQ = 17 # macro -SDMA_OP_DUMMY_TRAP = 32 # macro -SDMA_SUBOP_TIMESTAMP_SET = 0 # macro -SDMA_SUBOP_TIMESTAMP_GET = 1 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro -SDMA_SUBOP_COPY_TILED = 1 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro -SDMA_SUBOP_COPY_SOA = 3 # macro -SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro -SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE = 36 # macro -SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro -SDMA_SUBOP_COPY_TILED_BC = 17 # macro -SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro -SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro -SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro -SDMA_SUBOP_WRITE_LINEAR = 0 # macro -SDMA_SUBOP_WRITE_TILED = 1 # macro -SDMA_SUBOP_WRITE_TILED_BC = 17 # macro -SDMA_SUBOP_PTEPDE_GEN = 0 # macro -SDMA_SUBOP_PTEPDE_COPY = 1 # macro -SDMA_SUBOP_PTEPDE_RMW = 2 # macro -SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro -SDMA_SUBOP_MEM_INCR = 1 # macro -SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro -SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro -SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro -SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro -SDMA_SUBOP_VM_INVALIDATION = 4 # macro -HEADER_AGENT_DISPATCH = 4 # macro -HEADER_BARRIER = 5 # macro -SDMA_OP_AQL_COPY = 0 # macro -SDMA_OP_AQL_BARRIER_OR = 0 # macro -SDMA_GCR_RANGE_IS_PA = (1<<18) # macro -def SDMA_GCR_SEQ(x): # macro - return (((x)&0x3)<<16) -SDMA_GCR_GL2_WB = (1<<15) # macro -SDMA_GCR_GL2_INV = (1<<14) # macro -SDMA_GCR_GL2_DISCARD = (1<<13) # macro -def SDMA_GCR_GL2_RANGE(x): # macro - return (((x)&0x3)<<11) -SDMA_GCR_GL2_US = (1<<10) # macro -SDMA_GCR_GL1_INV = (1<<9) # macro -SDMA_GCR_GLV_INV = (1<<8) # macro -SDMA_GCR_GLK_INV = (1<<7) # macro -SDMA_GCR_GLK_WB = (1<<6) # macro -SDMA_GCR_GLM_INV = (1<<5) # macro -SDMA_GCR_GLM_WB = (1<<4) # macro -def SDMA_GCR_GL1_RANGE(x): # macro - return (((x)&0x3)<<2) -def SDMA_GCR_GLI_INV(x): # macro - return (((x)&0x3)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift = 8 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift = 16 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 17 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<17) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset = 1 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask = 0x000000FF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x): # macro - return (((x)&0x000000FF)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro - return (((x)&0x00000007)<<3) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro - return (((x)&0x00000003)<<6) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift = 8 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro - return (((x)&0x00000003)<<14) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift = 16 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 17 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<17) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift = 10 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<10) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro - return (((x)&0x0007FFFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset = 13 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset = 14 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset = 15 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift = 18 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset = 16 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift = 26 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset = 17 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset = 18 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset = 19 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro - return (((x)&0x00003FFF)<<13) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 19 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro -SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 27 # macro -def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_TILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset = 7 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 12 # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift = 19 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro -SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro - return (((x)&0x00000001)<<27) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro - return (((x)&0x00000003)<<8) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift = 10 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<10) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset = 10 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_T2T_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_T2T_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro -def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset = 14 # macro -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift = 14 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x): # macro - return (((x)&0x00000001)<<14) -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset = 17 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro -SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift = 31 # macro -def SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro -def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro - return (((x)&0x0000000F)<<20) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro - return (((x)&0x0000007F)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro - return (((x)&0x00000001)<<7) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro - return (((x)&0x00000001)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro - return (((x)&0x00000007)<<9) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro - return (((x)&0x00000003)<<12) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift = 14 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x): # macro - return (((x)&0x00000001)<<14) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro - return (((x)&0x00000003)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset = 16 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro -def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro -SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro -def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro -SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift = 18 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset = 5 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift = 26 # macro -def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro -def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset = 3 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift = 26 # macro -def SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_WRITE_TILED_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_TILED_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_TILED_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_TILED_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro - return (((x)&0x00001FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro - return (((x)&0x0000001F)<<3) -SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro -def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro - return (((x)&0x00000003)<<9) -SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro -SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset = 7 # macro -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro - return (((x)&0x000007FF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro - return (((x)&0x0000000F)<<3) -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro - return (((x)&0x00000007)<<8) -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro - return (((x)&0x00000007)<<11) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro - return (((x)&0x00000003)<<15) -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro - return (((x)&0x00000003)<<18) -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro - return (((x)&0x00000003)<<21) -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro -SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro - return (((x)&0x0000001F)<<26) -SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro -SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro - return (((x)&0x000007FF)<<0) -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro -SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro -def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro -SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro -def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro - return (((x)&0x000FFFFF)<<2) -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro -def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift = 22 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<22) -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset = 7 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift = 29 # macro -def SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<29) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro - return (((x)&0x00000003)<<28) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro -SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro -def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro - return (((x)&0x0001FFFF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset = 0 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset = 7 # macro -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask = 0xFFFFFFFF # macro -SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift = 0 # macro -def SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_HEADER_op_offset = 0 # macro -SDMA_PKT_REGISTER_RMW_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_REGISTER_RMW_HEADER_op_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_REGISTER_RMW_ADDR_addr_offset = 1 # macro -SDMA_PKT_REGISTER_RMW_ADDR_addr_mask = 0x000FFFFF # macro -SDMA_PKT_REGISTER_RMW_ADDR_addr_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset = 1 # macro -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask = 0x00000FFF # macro -SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift = 20 # macro -def SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_REGISTER_RMW_MASK_mask_offset = 2 # macro -SDMA_PKT_REGISTER_RMW_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_REGISTER_RMW_MASK_mask_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_VALUE_value_offset = 3 # macro -SDMA_PKT_REGISTER_RMW_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_REGISTER_RMW_VALUE_value_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_REGISTER_RMW_MISC_stride_offset = 4 # macro -SDMA_PKT_REGISTER_RMW_MISC_stride_mask = 0x000FFFFF # macro -SDMA_PKT_REGISTER_RMW_MISC_stride_shift = 0 # macro -def SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset = 4 # macro -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask = 0x00000FFF # macro -SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift = 20 # macro -def SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_WRITE_INCR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_WRITE_INCR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_WRITE_INCR_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_WRITE_INCR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro -SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro -SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro -SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro -def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro - return (((x)&0x0007FFFF)<<0) -SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro -def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro -SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro -def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro -SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro -SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro -def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro -SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro -def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro - return (((x)&0x000FFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro -def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro -def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro - return (((x)&0x00000001)<<29) -SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro -def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro - return (((x)&0x00000001)<<30) -SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro -SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro -def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_MEM_INCR_HEADER_op_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_MEM_INCR_HEADER_op_shift = 0 # macro -def SDMA_PKT_MEM_INCR_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_MEM_INCR_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_MEM_INCR_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_MEM_INCR_HEADER_cpv_offset = 0 # macro -SDMA_PKT_MEM_INCR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_MEM_INCR_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_MEM_INCR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro -def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro - return (((x)&0x0000001F)<<24) -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro - return (((x)&0x0000001F)<<16) -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro -SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro -def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro - return (((x)&0x000001FF)<<23) -SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro -def SDMA_PKT_FENCE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro -SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro -def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro -def SDMA_PKT_FENCE_HEADER_GCC(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro -def SDMA_PKT_FENCE_HEADER_SYS(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro -def SDMA_PKT_FENCE_HEADER_SNP(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro -def SDMA_PKT_FENCE_HEADER_GPA(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_FENCE_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_FENCE_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_FENCE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_FENCE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_FENCE_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_FENCE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_FENCE_DATA_data_offset = 3 # macro -SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_FENCE_DATA_data_shift = 0 # macro -def SDMA_PKT_FENCE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro -SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro -def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro - return (((x)&0x0000000F)<<28) -SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro - return (((x)&0x0003FFFF)<<0) -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro -SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro -def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro - return (((x)&0x00000FFF)<<20) -SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro -SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro -SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro -def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro -SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro -def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro - return (((x)&0x000000FF)<<16) -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro -def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_COND_EXE_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_COND_EXE_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_COND_EXE_HEADER_cpv_offset = 0 # macro -SDMA_PKT_COND_EXE_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_COND_EXE_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_COND_EXE_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro -SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro -def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro -SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro -def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro - return (((x)&0x00003FFF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro -SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro -def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro - return (((x)&0x00000003)<<30) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x3FFFFFFF # macro -SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro -def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro - return (((x)&0x3FFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro -SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro -def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro -SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro -def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro - return (((x)&0x03FFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift = 20 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<20) -SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift = 24 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro -SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro - return (((x)&0x00000007)<<28) -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro -SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro -def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro -SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro -def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro -SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro -def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro - return (((x)&0x00000FFF)<<16) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro - return (((x)&0x3FFFFFFF)<<2) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro - return (((x)&0x00000003)<<16) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro - return (((x)&0x0FFFFFFF)<<4) -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro -def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift = 24 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<24) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro -SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro -def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro - return (((x)&0x00000001)<<31) -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset = 4 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset = 5 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro -SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro -def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro -def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro -def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro - return (((x)&0x00000001)<<16) -SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro -def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro - return (((x)&0x00000001)<<18) -SDMA_PKT_ATOMIC_HEADER_cache_policy_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_cache_policy_mask = 0x00000007 # macro -SDMA_PKT_ATOMIC_HEADER_cache_policy_shift = 20 # macro -def SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<20) -SDMA_PKT_ATOMIC_HEADER_cpv_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_ATOMIC_HEADER_cpv_shift = 24 # macro -def SDMA_PKT_ATOMIC_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro -SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro -def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro - return (((x)&0x0000007F)<<25) -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro -def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro -SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro -def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro - return (((x)&0x00001FFF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask = 0x00000003 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift = 24 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x): # macro - return (((x)&0x00000003)<<24) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift = 26 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset = 0 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask = 0x00000001 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift = 28 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro - return (((x)&0x1FFFFFFF)<<3) -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro -def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro -SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro -def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro - return (((x)&0x0FFFFFFF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro - return (((x)&0x00000007)<<16) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro - return (((x)&0x00000001)<<19) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro - return (((x)&0x00000001)<<20) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro - return (((x)&0x00000001)<<21) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro - return (((x)&0x00000001)<<22) -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro - return (((x)&0x00000001)<<23) -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro - return (((x)&0x00000001)<<24) -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro - return (((x)&0x00000001)<<25) -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro - return (((x)&0x00000001)<<26) -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro - return (((x)&0x00000001)<<0) -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro -SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro - return (((x)&0x7FFFFFFF)<<1) -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro -SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro -def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro - return (((x)&0x0000003F)<<0) -SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro -def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro - return (((x)&0x0000FFFF)<<16) -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro - return (((x)&0x00000007)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro - return (((x)&0x01FFFFFF)<<7) -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro - return (((x)&0x0000FFFF)<<0) -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro -SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro -def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro - return (((x)&0x0000000F)<<24) -SDMA_PKT_NOP_HEADER_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_op_shift = 0 # macro -def SDMA_PKT_NOP_HEADER_OP(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro -SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro -SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro -def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro - return (((x)&0x000000FF)<<8) -SDMA_PKT_NOP_HEADER_count_offset = 0 # macro -SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro -SDMA_PKT_NOP_HEADER_count_shift = 16 # macro -def SDMA_PKT_NOP_HEADER_COUNT(x): # macro - return (((x)&0x00003FFF)<<16) -SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro -SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro -SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro -def SDMA_PKT_NOP_DATA0_DATA0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_HEADER_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_HEADER_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_HEADER_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_HEADER_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro - return (((x)&0x003FFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro - return (((x)&0x00000003)<<16) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<18) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro - return (((x)&0x00000003)<<24) -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 5 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro -SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro -def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro - return (((x)&0x00000007)<<26) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro - return (((x)&0x000000FF)<<0) -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro - return (((x)&0x00000001)<<8) -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<9) -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro - return (((x)&0x00000003)<<11) -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro - return (((x)&0x00000007)<<13) -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro - return (((x)&0x0000000F)<<16) -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset = 0 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask = 0x00000001 # macro -SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift = 28 # macro -def SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x): # macro - return (((x)&0x00000001)<<28) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x): # macro - return (((x)&0x00000007)<<0) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift = 5 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x): # macro - return (((x)&0x00000007)<<5) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift = 10 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x): # macro - return (((x)&0x00000007)<<10) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift = 15 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x): # macro - return (((x)&0x00000007)<<15) -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset = 12 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask = 0x00000007 # macro -SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift = 20 # macro -def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x): # macro - return (((x)&0x00000007)<<20) -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro - return (((x)&0xFFFFFFFF)<<0) -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro -SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro -def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro - return (((x)&0xFFFFFFFF)<<0) -__all__ = \ - ['HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset', - 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', - 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', - 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_cpv_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', - 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', - 'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV', - 'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV', - 'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB', - 'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA', - 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', - 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', - 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', - 'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT', - 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE', - 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE', - 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE', - 'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', - 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_mask', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_offset', - 'SDMA_PKT_ATOMIC_HEADER_cache_policy_shift', - 'SDMA_PKT_ATOMIC_HEADER_cpv_mask', - 'SDMA_PKT_ATOMIC_HEADER_cpv_offset', - 'SDMA_PKT_ATOMIC_HEADER_cpv_shift', - 'SDMA_PKT_ATOMIC_HEADER_loop_mask', - 'SDMA_PKT_ATOMIC_HEADER_loop_offset', - 'SDMA_PKT_ATOMIC_HEADER_loop_shift', - 'SDMA_PKT_ATOMIC_HEADER_op_mask', - 'SDMA_PKT_ATOMIC_HEADER_op_offset', - 'SDMA_PKT_ATOMIC_HEADER_op_shift', - 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', - 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', - 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', - 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', - 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_mask', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_offset', - 'SDMA_PKT_COND_EXE_HEADER_cache_policy_shift', - 'SDMA_PKT_COND_EXE_HEADER_cpv_mask', - 'SDMA_PKT_COND_EXE_HEADER_cpv_offset', - 'SDMA_PKT_COND_EXE_HEADER_cpv_shift', - 'SDMA_PKT_COND_EXE_HEADER_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_op_shift', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', - 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', - 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', - 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', - 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', - 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', - 'SDMA_PKT_COPY_LINEAR', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', - 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', - 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', - 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', - 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', - 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', - 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', - 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', - 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', - 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', - 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', - 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', - 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', - 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', - 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', - 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_mask', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_offset', - 'SDMA_PKT_COPY_T2T_HEADER_cpv_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_mask', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_offset', - 'SDMA_PKT_COPY_T2T_HEADER_dcc_shift', - 'SDMA_PKT_COPY_T2T_HEADER_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', - 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_COUNT_count_mask', - 'SDMA_PKT_COPY_TILED_COUNT_count_offset', - 'SDMA_PKT_COPY_TILED_COUNT_count_shift', - 'SDMA_PKT_COPY_TILED_DW_3_width_mask', - 'SDMA_PKT_COPY_TILED_DW_3_width_offset', - 'SDMA_PKT_COPY_TILED_DW_3_width_shift', - 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', - 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', - 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', - 'SDMA_PKT_COPY_TILED_DW_4_height_mask', - 'SDMA_PKT_COPY_TILED_DW_4_height_offset', - 'SDMA_PKT_COPY_TILED_DW_4_height_shift', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', - 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', - 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_DW_6_x_mask', - 'SDMA_PKT_COPY_TILED_DW_6_x_offset', - 'SDMA_PKT_COPY_TILED_DW_6_x_shift', - 'SDMA_PKT_COPY_TILED_DW_6_y_mask', - 'SDMA_PKT_COPY_TILED_DW_6_y_offset', - 'SDMA_PKT_COPY_TILED_DW_6_y_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_DW_7_z_mask', - 'SDMA_PKT_COPY_TILED_DW_7_z_offset', - 'SDMA_PKT_COPY_TILED_DW_7_z_shift', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_mask', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_offset', - 'SDMA_PKT_COPY_TILED_HEADER_cpv_shift', - 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_COPY_TILED_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', - 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', - 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', - 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_FENCE_DATA_data_mask', - 'SDMA_PKT_FENCE_DATA_data_offset', - 'SDMA_PKT_FENCE_DATA_data_shift', - 'SDMA_PKT_FENCE_HEADER_cpv_mask', - 'SDMA_PKT_FENCE_HEADER_cpv_offset', - 'SDMA_PKT_FENCE_HEADER_cpv_shift', - 'SDMA_PKT_FENCE_HEADER_gcc_mask', - 'SDMA_PKT_FENCE_HEADER_gcc_offset', - 'SDMA_PKT_FENCE_HEADER_gcc_shift', - 'SDMA_PKT_FENCE_HEADER_gpa_mask', - 'SDMA_PKT_FENCE_HEADER_gpa_offset', - 'SDMA_PKT_FENCE_HEADER_gpa_shift', - 'SDMA_PKT_FENCE_HEADER_l2_policy_mask', - 'SDMA_PKT_FENCE_HEADER_l2_policy_offset', - 'SDMA_PKT_FENCE_HEADER_l2_policy_shift', - 'SDMA_PKT_FENCE_HEADER_llc_policy_mask', - 'SDMA_PKT_FENCE_HEADER_llc_policy_offset', - 'SDMA_PKT_FENCE_HEADER_llc_policy_shift', - 'SDMA_PKT_FENCE_HEADER_mtype_mask', - 'SDMA_PKT_FENCE_HEADER_mtype_offset', - 'SDMA_PKT_FENCE_HEADER_mtype_shift', - 'SDMA_PKT_FENCE_HEADER_op_mask', - 'SDMA_PKT_FENCE_HEADER_op_offset', - 'SDMA_PKT_FENCE_HEADER_op_shift', - 'SDMA_PKT_FENCE_HEADER_snp_mask', - 'SDMA_PKT_FENCE_HEADER_snp_offset', - 'SDMA_PKT_FENCE_HEADER_snp_shift', - 'SDMA_PKT_FENCE_HEADER_sub_op_mask', - 'SDMA_PKT_FENCE_HEADER_sub_op_offset', - 'SDMA_PKT_FENCE_HEADER_sub_op_shift', - 'SDMA_PKT_FENCE_HEADER_sys_mask', - 'SDMA_PKT_FENCE_HEADER_sys_offset', - 'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR', - 'SDMA_PKT_GCR_REQ_HEADER_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_op_shift', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset', - 'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset', - 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_op_shift', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset', - 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset', - 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift', - 'SDMA_PKT_HDP_FLUSH', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', - 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', - 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', - 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', - 'SDMA_PKT_INDIRECT_HEADER_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_priv_mask', - 'SDMA_PKT_INDIRECT_HEADER_priv_offset', - 'SDMA_PKT_INDIRECT_HEADER_priv_shift', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', - 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', - 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', - 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', - 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', - 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_mask', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_offset', - 'SDMA_PKT_MEM_INCR_HEADER_cpv_shift', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset', - 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset', - 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift', - 'SDMA_PKT_MEM_INCR_HEADER_op_mask', - 'SDMA_PKT_MEM_INCR_HEADER_op_offset', - 'SDMA_PKT_MEM_INCR_HEADER_op_shift', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_MEM_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_NOP_DATA0_data0_mask', - 'SDMA_PKT_NOP_DATA0_data0_offset', - 'SDMA_PKT_NOP_DATA0_data0_shift', - 'SDMA_PKT_NOP_HEADER_count_mask', - 'SDMA_PKT_NOP_HEADER_count_offset', - 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', - 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', - 'SDMA_PKT_NOP_HEADER_sub_op_mask', - 'SDMA_PKT_NOP_HEADER_sub_op_offset', - 'SDMA_PKT_NOP_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', - 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', - 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', - 'SDMA_PKT_POLL_REGMEM', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', - 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', - 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', - 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', - 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', - 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', - 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', - 'SDMA_PKT_PRE_EXE_HEADER_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_op_shift', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', - 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset', - 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset', - 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset', - 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', - 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', - 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_mask', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_offset', - 'SDMA_PKT_REGISTER_RMW_ADDR_addr_shift', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset', - 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_mask', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_offset', - 'SDMA_PKT_REGISTER_RMW_HEADER_op_shift', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset', - 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_mask', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_offset', - 'SDMA_PKT_REGISTER_RMW_MASK_mask_shift', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset', - 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_mask', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_offset', - 'SDMA_PKT_REGISTER_RMW_MISC_stride_shift', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_mask', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_offset', - 'SDMA_PKT_REGISTER_RMW_VALUE_value_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', - 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', - 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset', - 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift', - 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', - 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', - 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', - 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', - 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', - 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', - 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', - 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', - 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', - 'SDMA_PKT_TRAP_HEADER_sub_op_mask', - 'SDMA_PKT_TRAP_HEADER_sub_op_offset', - 'SDMA_PKT_TRAP_HEADER_sub_op_shift', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', - 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset', - 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset', - 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset', - 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift', - 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', - 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', - 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', - 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', - 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', - 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', - 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', - 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', - 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', - 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', - 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', - 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', - 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', - 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', - 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', - 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', - 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', - 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', - 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', - 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', - 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', - 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', - 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', - 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', - 'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY', - 'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE', 'SDMA_SUBOP_COPY_SOA', - 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC', - 'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND', - 'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI', - 'SDMA_SUBOP_MEM_INCR', 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', - 'SDMA_SUBOP_POLL_MEM_VERIFY', 'SDMA_SUBOP_POLL_REG_WRITE_MEM', - 'SDMA_SUBOP_PTEPDE_COPY', 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', - 'SDMA_SUBOP_PTEPDE_GEN', 'SDMA_SUBOP_PTEPDE_RMW', - 'SDMA_SUBOP_TIMESTAMP_GET', 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', - 'SDMA_SUBOP_TIMESTAMP_SET', 'SDMA_SUBOP_USER_GCR', - 'SDMA_SUBOP_VM_INVALIDATION', 'SDMA_SUBOP_WRITE_LINEAR', - 'SDMA_SUBOP_WRITE_TILED', 'SDMA_SUBOP_WRITE_TILED_BC', - '__SDMA_V6_0_0_PKT_OPEN_H_', 'hdp_flush_cmd', - 'struct_SDMA_PKT_ATOMIC_TAG', 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('extra_info', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0._fields_ = [ + ('reserved_0', ctypes.c_uint32,16), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_1', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), + ('PARAMETER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR = rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved', ctypes.c_uint32,13), + ('element', ctypes.c_uint32,3), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0._fields_ = [ + ('src_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('src_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0._fields_ = [ + ('src_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('src_pitch', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0._fields_ = [ + ('src_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0._fields_ = [ + ('dst_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('dst_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0), + ('DW_8_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0._fields_ = [ + ('dst_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('dst_pitch', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0), + ('DW_9_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0._fields_ = [ + ('dst_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0), + ('DW_10_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0._fields_ = [ + ('rect_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('rect_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0), + ('DW_11_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0._fields_ = [ + ('rect_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,5), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_3', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0), + ('DW_12_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), + ('SRC_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), + ('SRC_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), + ('SRC_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), + ('DST_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), + ('DST_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), + ('DST_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), + ('RECT_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), + ('RECT_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), +] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT = rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('sw', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,12), + ('fillsize', ctypes.c_uint32,2), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), +] +rocr_AMD_SDMA_PKT_CONSTANT_FILL = rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG +class rocr_AMD_SDMA_PKT_FENCE_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('mtype', ctypes.c_uint32,3), + ('gcc', ctypes.c_uint32,1), + ('sys', ctypes.c_uint32,1), + ('pad1', ctypes.c_uint32,1), + ('snp', ctypes.c_uint32,1), + ('gpa', ctypes.c_uint32,1), + ('l2_policy', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,6), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0._fields_ = [ + ('data', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_FENCE_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION), +] +rocr_AMD_SDMA_PKT_FENCE = rocr_AMD_SDMA_PKT_FENCE_TAG +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,10), + ('hdp_flush', ctypes.c_uint32,1), + ('reserved_1', ctypes.c_uint32,1), + ('func', ctypes.c_uint32,3), + ('mem_poll', ctypes.c_uint32,1), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0._fields_ = [ + ('value', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0._fields_ = [ + ('mask', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0._fields_ = [ + ('interval', ctypes.c_uint32,16), + ('retry_count', ctypes.c_uint32,12), + ('reserved_0', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), + ('VALUE_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), + ('MASK_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), + ('DW5_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), +] +rocr_AMD_SDMA_PKT_POLL_REGMEM = rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG +class rocr_AMD_SDMA_PKT_ATOMIC_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('l', ctypes.c_uint32,1), + ('reserved_0', ctypes.c_uint32,8), + ('operation', ctypes.c_uint32,7), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0._fields_ = [ + ('src_data_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0._fields_ = [ + ('cmp_data_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0._fields_ = [ + ('cmp_data_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0._fields_ = [ + ('loop_interval', ctypes.c_uint32,13), + ('reserved_0', ctypes.c_uint32,19), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_ATOMIC_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), + ('SRC_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), + ('SRC_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), + ('CMP_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), + ('CMP_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), + ('LOOP_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), +] +rocr_AMD_SDMA_PKT_ATOMIC = rocr_AMD_SDMA_PKT_ATOMIC_TAG +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), +] +rocr_AMD_SDMA_PKT_TIMESTAMP = rocr_AMD_SDMA_PKT_TIMESTAMP_TAG +class rocr_AMD_SDMA_PKT_TRAP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0._fields_ = [ + ('int_ctx', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_TRAP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION), + ('INT_CONTEXT_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), +] +rocr_AMD_SDMA_PKT_TRAP = rocr_AMD_SDMA_PKT_TRAP_TAG +class rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG(Struct): pass +rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ + ('DW_0_DATA', ctypes.c_uint32), + ('DW_1_DATA', ctypes.c_uint32), + ('DW_2_DATA', ctypes.c_uint32), + ('DW_3_DATA', ctypes.c_uint32), + ('DW_4_DATA', ctypes.c_uint32), + ('DW_5_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_HDP_FLUSH = rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG +class rocr_AMD_SDMA_PKT_GCR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('', ctypes.c_uint32,16), +] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0._fields_ = [ + ('', ctypes.c_uint32,7), + ('BaseVA_LO', ctypes.c_uint32,25), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0._fields_ = [ + ('BaseVA_HI', ctypes.c_uint32,16), + ('GCR_CONTROL_GLI_INV', ctypes.c_uint32,2), + ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GLM_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLM_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLV_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL1_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_US', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_WB', ctypes.c_uint32,1), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0._fields_ = [ + ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32,1), + ('GCR_CONTROL_SEQ', ctypes.c_uint32,2), + ('', ctypes.c_uint32,4), + ('LimitVA_LO', ctypes.c_uint32,25), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), +] +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0._fields_ = [ + ('LimitVA_HI', ctypes.c_uint32,16), + ('', ctypes.c_uint32,8), + ('VMID', ctypes.c_uint32,4), + ('', ctypes.c_uint32,4), +] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), +] +rocr_AMD_SDMA_PKT_GCR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION), + ('WORD1_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION), + ('WORD2_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION), + ('WORD3_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION), + ('WORD4_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION), +] +rocr_AMD_SDMA_PKT_GCR = rocr_AMD_SDMA_PKT_GCR_TAG +SDMA_OP_COPY = 1 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_GCR = 17 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_RECT = 4 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_USER_GCR = 1 +SDMA_ATOMIC_ADD64 = 47 +SDMA_OP_NOP = 0 +SDMA_OP_COPY = 1 +SDMA_OP_WRITE = 2 +SDMA_OP_INDIRECT = 4 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_SEM = 7 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_COND_EXE = 9 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_PTEPDE = 12 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_SRBM_WRITE = 14 +SDMA_OP_PRE_EXE = 15 +SDMA_OP_GPUVM_INV = 16 +SDMA_OP_GCR_REQ = 17 +SDMA_OP_DUMMY_TRAP = 32 +SDMA_SUBOP_TIMESTAMP_SET = 0 +SDMA_SUBOP_TIMESTAMP_GET = 1 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 +SDMA_SUBOP_COPY_TILED = 1 +SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 +SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 +SDMA_SUBOP_COPY_SOA = 3 +SDMA_SUBOP_COPY_DIRTY_PAGE = 7 +SDMA_SUBOP_COPY_LINEAR_PHY = 8 +SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE = 36 +SDMA_SUBOP_COPY_LINEAR_BC = 16 +SDMA_SUBOP_COPY_TILED_BC = 17 +SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 +SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 +SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 +SDMA_SUBOP_WRITE_LINEAR = 0 +SDMA_SUBOP_WRITE_TILED = 1 +SDMA_SUBOP_WRITE_TILED_BC = 17 +SDMA_SUBOP_PTEPDE_GEN = 0 +SDMA_SUBOP_PTEPDE_COPY = 1 +SDMA_SUBOP_PTEPDE_RMW = 2 +SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 +SDMA_SUBOP_MEM_INCR = 1 +SDMA_SUBOP_DATA_FILL_MULTI = 1 +SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 +SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 +SDMA_SUBOP_POLL_MEM_VERIFY = 3 +SDMA_SUBOP_VM_INVALIDATION = 4 +HEADER_AGENT_DISPATCH = 4 +HEADER_BARRIER = 5 +SDMA_OP_AQL_COPY = 0 +SDMA_OP_AQL_BARRIER_OR = 0 +SDMA_GCR_RANGE_IS_PA = (1 << 18) +SDMA_GCR_SEQ = lambda x: (((x) & 0x3) << 16) +SDMA_GCR_GL2_WB = (1 << 15) +SDMA_GCR_GL2_INV = (1 << 14) +SDMA_GCR_GL2_DISCARD = (1 << 13) +SDMA_GCR_GL2_RANGE = lambda x: (((x) & 0x3) << 11) +SDMA_GCR_GL2_US = (1 << 10) +SDMA_GCR_GL1_INV = (1 << 9) +SDMA_GCR_GLV_INV = (1 << 8) +SDMA_GCR_GLK_INV = (1 << 7) +SDMA_GCR_GLK_WB = (1 << 6) +SDMA_GCR_GLM_INV = (1 << 5) +SDMA_GCR_GLM_WB = (1 << 4) +SDMA_GCR_GL1_RANGE = lambda x: (((x) & 0x3) << 2) +SDMA_GCR_GLI_INV = lambda x: (((x) & 0x3) << 0) +SDMA_DCC_DATA_FORMAT = lambda x: ((x) & 0x3f) +SDMA_DCC_NUM_TYPE = lambda x: (((x) & 0x7) << 9) +SDMA_DCC_READ_CM = lambda x: (((x) & 0x3) << 16) +SDMA_DCC_WRITE_CM = lambda x: (((x) & 0x3) << 18) +SDMA_DCC_MAX_COM = lambda x: (((x) & 0x3) << 24) +SDMA_DCC_MAX_UCOM = lambda x: (((x) & 0x1) << 26) +SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) +SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_LINEAR_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift) +SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 +SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) +SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x3FFFFFFF +SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 +SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 2 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 +SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 19 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 27 +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift = 8 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift = 16 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 17 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset = 1 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask = 0x000000FF +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift = 24 +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift = 8 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift = 16 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 17 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x3FFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift = 10 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift = 18 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset = 2 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift = 26 +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift = 26 +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset = 5 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset = 6 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset = 7 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask = 0x0000FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset = 10 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset = 14 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset = 15 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask = 0x0000FFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift = 26 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset = 17 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset = 18 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset = 19 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 19 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 27 +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA = lambda x: (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) +SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) +SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_TILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) +SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_TILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) +SDMA_PKT_COPY_TILED_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_TILED_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_HEADER_cpv_shift) +SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 +SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 +SDMA_PKT_COPY_TILED_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) +SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 +SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 +SDMA_PKT_COPY_TILED_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) +SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 +SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 +SDMA_PKT_COPY_TILED_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) +SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 +SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 +SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) +SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 +SDMA_PKT_COPY_TILED_DW_5_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) +SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 +SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 +SDMA_PKT_COPY_TILED_DW_5_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) +SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 +SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 +SDMA_PKT_COPY_TILED_DW_6_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) +SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 +SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 +SDMA_PKT_COPY_TILED_DW_6_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) +SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 +SDMA_PKT_COPY_TILED_DW_7_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) +SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) +SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift = 18 +SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift) +SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_DW_7_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) +SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset = 7 +SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift = 26 +SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 +SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x3FFFFFFF +SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 +SDMA_PKT_COPY_TILED_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) +SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_BC_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 +SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) +SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 +SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) +SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 +SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF +SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 +SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 +SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 +SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 +SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 +SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 +SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 +SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 +SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 +SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) +SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 +SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_6_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) +SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 +SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 +SDMA_PKT_COPY_TILED_BC_DW_6_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) +SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 +SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 +SDMA_PKT_COPY_TILED_BC_DW_7_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 12 +SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 +SDMA_PKT_COPY_TILED_BC_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift = 19 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift = 18 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset = 10 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift = 26 +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x3FFFFFFF +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) +SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 +SDMA_PKT_COPY_T2T_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) +SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_T2T_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) +SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_T2T_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) +SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 +SDMA_PKT_COPY_T2T_HEADER_DCC = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) +SDMA_PKT_COPY_T2T_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_cpv_shift = 28 +SDMA_PKT_COPY_T2T_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_cpv_mask) << SDMA_PKT_COPY_T2T_HEADER_cpv_shift) +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 +SDMA_PKT_COPY_T2T_HEADER_DCC_DIR = lambda x: (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) +SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) +SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) +SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 +SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 +SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) +SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 +SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 +SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) +SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 +SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 +SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) +SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 +SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 +SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) +SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 +SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 +SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 +SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 +SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_9_DST_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) +SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 +SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_9_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) +SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 +SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_10_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) +SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 +SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 +SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) +SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 +SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 +SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) +SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 +SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 +SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 +SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 +SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 +SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 +SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 +SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) +SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 +SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 +SDMA_PKT_COPY_T2T_DW_13_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) +SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 +SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 +SDMA_PKT_COPY_T2T_DW_13_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) +SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF +SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 +SDMA_PKT_COPY_T2T_DW_14_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) +SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 +SDMA_PKT_COPY_T2T_DW_14_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) +SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift = 18 +SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift) +SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 +SDMA_PKT_COPY_T2T_DW_14_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) +SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset = 14 +SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift = 26 +SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift) +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 +SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 +SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 +SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 +SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 +SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift = 14 +SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 +SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 +SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 +SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 +SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) +SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset = 17 +SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask = 0x00000001 +SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift = 31 +SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED = lambda x: (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift) +SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_T2T_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 +SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_9_DST_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 +SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 +SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 +SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 +SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW = lambda x: (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift = 28 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift = 18 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift = 26 +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift = 14 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset = 16 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift = 31 +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW = lambda x: (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) +SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF +SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 +SDMA_PKT_COPY_STRUCT_HEADER_OP = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 +SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) +SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 +SDMA_PKT_COPY_STRUCT_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) +SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift = 28 +SDMA_PKT_COPY_STRUCT_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask) << SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift) +SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 +SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 +SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 +SDMA_PKT_COPY_STRUCT_HEADER_DETILE = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 +SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) +SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 +SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 +SDMA_PKT_COPY_STRUCT_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) +SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF +SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 +SDMA_PKT_COPY_STRUCT_DW_5_STRIDE = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 +SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) +SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift = 18 +SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift) +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_mask = 0x00000003 +SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_shift = 24 +SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct__sw_shift) +SDMA_PKT_COPY_STRUCT_DW_5_struct__cache_policy_offset = 5 +SDMA_PKT_COPY_STRUCT_DW_5_struct__cache_policy_mask = 0x00000007 +SDMA_PKT_COPY_STRUCT_DW_5_struct__cache_policy_shift = 26 +SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct__cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct__cache_policy_shift) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 +SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 +SDMA_PKT_WRITE_UNTILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) +SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset = 0 +SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift = 28 +SDMA_PKT_WRITE_UNTILED_HEADER_CPV = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 +SDMA_PKT_WRITE_UNTILED_DW_3_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 +SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 +SDMA_PKT_WRITE_UNTILED_DW_3_SW = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) +SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset = 3 +SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask = 0x00000007 +SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift = 26 +SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift) +SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 +SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_UNTILED_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) +SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 +SDMA_PKT_WRITE_TILED_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) +SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_TILED_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) +SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 +SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) +SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 +SDMA_PKT_WRITE_TILED_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) +SDMA_PKT_WRITE_TILED_HEADER_cpv_offset = 0 +SDMA_PKT_WRITE_TILED_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_WRITE_TILED_HEADER_cpv_shift = 28 +SDMA_PKT_WRITE_TILED_HEADER_CPV = lambda x: (((x) & SDMA_PKT_WRITE_TILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_TILED_HEADER_cpv_shift) +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 +SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 +SDMA_PKT_WRITE_TILED_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) +SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 +SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 +SDMA_PKT_WRITE_TILED_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) +SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 +SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF +SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 +SDMA_PKT_WRITE_TILED_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) +SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 +SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 +SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) +SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 +SDMA_PKT_WRITE_TILED_DW_5_DIMENSION = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) +SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 +SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F +SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 +SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) +SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 +SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 +SDMA_PKT_WRITE_TILED_DW_6_X = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) +SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 +SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 +SDMA_PKT_WRITE_TILED_DW_6_Y = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) +SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF +SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 +SDMA_PKT_WRITE_TILED_DW_7_Z = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) +SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 +SDMA_PKT_WRITE_TILED_DW_7_SW = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) +SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset = 7 +SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift = 26 +SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask) << SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift) +SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 +SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 +SDMA_PKT_WRITE_TILED_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) +SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 +SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_TILED_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) +SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 +SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 +SDMA_PKT_WRITE_TILED_BC_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 +SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) +SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 +SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 +SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 +SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 +SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 +SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 +SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 +SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 +SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 +SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 +SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) +SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 +SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_6_X = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) +SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 +SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF +SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 +SDMA_PKT_WRITE_TILED_BC_DW_6_Y = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) +SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 +SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF +SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DW_7_Z = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 +SDMA_PKT_WRITE_TILED_BC_DW_7_SW = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) +SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 +SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF +SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 +SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 +SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 +SDMA_PKT_PTEPDE_COPY_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift = 28 +SDMA_PKT_PTEPDE_COPY_HEADER_CPV = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift) +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 +SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 +SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 +SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) +SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 +SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF +SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 +SDMA_PKT_PTEPDE_COPY_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) +SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset = 7 +SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask = 0x00000007 +SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift = 22 +SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift) +SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset = 7 +SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask = 0x00000007 +SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift = 29 +SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT = lambda x: (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 +SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 +SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 +SDMA_PKT_PTEPDE_RMW_HEADER_GCC = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 +SDMA_PKT_PTEPDE_RMW_HEADER_SYS = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 +SDMA_PKT_PTEPDE_RMW_HEADER_SNP = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 +SDMA_PKT_PTEPDE_RMW_HEADER_GPA = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 +SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift = 26 +SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift) +SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset = 0 +SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift = 28 +SDMA_PKT_PTEPDE_RMW_HEADER_CPV = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift) +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 +SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 +SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32 = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) +SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset = 7 +SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask = 0xFFFFFFFF +SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift = 0 +SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE = lambda x: (((x) & SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask) << SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift) +SDMA_PKT_REGISTER_RMW_HEADER_op_offset = 0 +SDMA_PKT_REGISTER_RMW_HEADER_op_mask = 0x000000FF +SDMA_PKT_REGISTER_RMW_HEADER_op_shift = 0 +SDMA_PKT_REGISTER_RMW_HEADER_OP = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_HEADER_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_op_shift) +SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset = 0 +SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift = 8 +SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift) +SDMA_PKT_REGISTER_RMW_ADDR_addr_offset = 1 +SDMA_PKT_REGISTER_RMW_ADDR_addr_mask = 0x000FFFFF +SDMA_PKT_REGISTER_RMW_ADDR_addr_shift = 0 +SDMA_PKT_REGISTER_RMW_ADDR_ADDR = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_ADDR_addr_mask) << SDMA_PKT_REGISTER_RMW_ADDR_addr_shift) +SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset = 1 +SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask = 0x00000FFF +SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift = 20 +SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask) << SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift) +SDMA_PKT_REGISTER_RMW_MASK_mask_offset = 2 +SDMA_PKT_REGISTER_RMW_MASK_mask_mask = 0xFFFFFFFF +SDMA_PKT_REGISTER_RMW_MASK_mask_shift = 0 +SDMA_PKT_REGISTER_RMW_MASK_MASK = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_MASK_mask_mask) << SDMA_PKT_REGISTER_RMW_MASK_mask_shift) +SDMA_PKT_REGISTER_RMW_VALUE_value_offset = 3 +SDMA_PKT_REGISTER_RMW_VALUE_value_mask = 0xFFFFFFFF +SDMA_PKT_REGISTER_RMW_VALUE_value_shift = 0 +SDMA_PKT_REGISTER_RMW_VALUE_VALUE = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_VALUE_value_mask) << SDMA_PKT_REGISTER_RMW_VALUE_value_shift) +SDMA_PKT_REGISTER_RMW_MISC_stride_offset = 4 +SDMA_PKT_REGISTER_RMW_MISC_stride_mask = 0x000FFFFF +SDMA_PKT_REGISTER_RMW_MISC_stride_shift = 0 +SDMA_PKT_REGISTER_RMW_MISC_STRIDE = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_MISC_stride_mask) << SDMA_PKT_REGISTER_RMW_MISC_stride_shift) +SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset = 4 +SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask = 0x00000FFF +SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift = 20 +SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG = lambda x: (((x) & SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask) << SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift) +SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF +SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 +SDMA_PKT_WRITE_INCR_HEADER_OP = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) +SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 +SDMA_PKT_WRITE_INCR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) +SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift = 24 +SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask) << SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift) +SDMA_PKT_WRITE_INCR_HEADER_cpv_offset = 0 +SDMA_PKT_WRITE_INCR_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_WRITE_INCR_HEADER_cpv_shift = 28 +SDMA_PKT_WRITE_INCR_HEADER_CPV = lambda x: (((x) & SDMA_PKT_WRITE_INCR_HEADER_cpv_mask) << SDMA_PKT_WRITE_INCR_HEADER_cpv_shift) +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 +SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 +SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1 = lambda x: (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) +SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 +SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF +SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 +SDMA_PKT_WRITE_INCR_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) +SDMA_PKT_INDIRECT_HEADER_op_offset = 0 +SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF +SDMA_PKT_INDIRECT_HEADER_op_shift = 0 +SDMA_PKT_INDIRECT_HEADER_OP = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) +SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 +SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 +SDMA_PKT_INDIRECT_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) +SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 +SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F +SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 +SDMA_PKT_INDIRECT_HEADER_VMID = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) +SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 +SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 +SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 +SDMA_PKT_INDIRECT_HEADER_PRIV = lambda x: (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 +SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0 = lambda x: (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 +SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32 = lambda x: (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 +SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE = lambda x: (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 +SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 +SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) +SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF +SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 +SDMA_PKT_SEMAPHORE_HEADER_OP = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) +SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 +SDMA_PKT_SEMAPHORE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) +SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 +SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) +SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 +SDMA_PKT_SEMAPHORE_HEADER_SIGNAL = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) +SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 +SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 +SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 +SDMA_PKT_SEMAPHORE_HEADER_MAILBOX = lambda x: (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_MEM_INCR_HEADER_op_offset = 0 +SDMA_PKT_MEM_INCR_HEADER_op_mask = 0x000000FF +SDMA_PKT_MEM_INCR_HEADER_op_shift = 0 +SDMA_PKT_MEM_INCR_HEADER_OP = lambda x: (((x) & SDMA_PKT_MEM_INCR_HEADER_op_mask) << SDMA_PKT_MEM_INCR_HEADER_op_shift) +SDMA_PKT_MEM_INCR_HEADER_sub_op_offset = 0 +SDMA_PKT_MEM_INCR_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_MEM_INCR_HEADER_sub_op_shift = 8 +SDMA_PKT_MEM_INCR_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_MEM_INCR_HEADER_sub_op_mask) << SDMA_PKT_MEM_INCR_HEADER_sub_op_shift) +SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset = 0 +SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift = 24 +SDMA_PKT_MEM_INCR_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift) +SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset = 0 +SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask = 0x00000001 +SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift = 26 +SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY = lambda x: (((x) & SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift) +SDMA_PKT_MEM_INCR_HEADER_cpv_offset = 0 +SDMA_PKT_MEM_INCR_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_MEM_INCR_HEADER_cpv_shift = 28 +SDMA_PKT_MEM_INCR_HEADER_CPV = lambda x: (((x) & SDMA_PKT_MEM_INCR_HEADER_cpv_mask) << SDMA_PKT_MEM_INCR_HEADER_cpv_shift) +SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask) << SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift) +SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask) << SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF +SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_OP = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 +SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 +SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 +SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED = lambda x: (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) +SDMA_PKT_FENCE_HEADER_op_offset = 0 +SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF +SDMA_PKT_FENCE_HEADER_op_shift = 0 +SDMA_PKT_FENCE_HEADER_OP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) +SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 +SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 +SDMA_PKT_FENCE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) +SDMA_PKT_FENCE_HEADER_mtype_offset = 0 +SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 +SDMA_PKT_FENCE_HEADER_mtype_shift = 16 +SDMA_PKT_FENCE_HEADER_MTYPE = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) +SDMA_PKT_FENCE_HEADER_gcc_offset = 0 +SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_gcc_shift = 19 +SDMA_PKT_FENCE_HEADER_GCC = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) +SDMA_PKT_FENCE_HEADER_sys_offset = 0 +SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_sys_shift = 20 +SDMA_PKT_FENCE_HEADER_SYS = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) +SDMA_PKT_FENCE_HEADER_snp_offset = 0 +SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_snp_shift = 22 +SDMA_PKT_FENCE_HEADER_SNP = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) +SDMA_PKT_FENCE_HEADER_gpa_offset = 0 +SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_gpa_shift = 23 +SDMA_PKT_FENCE_HEADER_GPA = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) +SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 +SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 +SDMA_PKT_FENCE_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) +SDMA_PKT_FENCE_HEADER_llc_policy_offset = 0 +SDMA_PKT_FENCE_HEADER_llc_policy_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_llc_policy_shift = 26 +SDMA_PKT_FENCE_HEADER_LLC_POLICY = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_llc_policy_mask) << SDMA_PKT_FENCE_HEADER_llc_policy_shift) +SDMA_PKT_FENCE_HEADER_cpv_offset = 0 +SDMA_PKT_FENCE_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_FENCE_HEADER_cpv_shift = 28 +SDMA_PKT_FENCE_HEADER_CPV = lambda x: (((x) & SDMA_PKT_FENCE_HEADER_cpv_mask) << SDMA_PKT_FENCE_HEADER_cpv_shift) +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_FENCE_DATA_data_offset = 3 +SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF +SDMA_PKT_FENCE_DATA_data_shift = 0 +SDMA_PKT_FENCE_DATA_DATA = lambda x: (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) +SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF +SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 +SDMA_PKT_SRBM_WRITE_HEADER_OP = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 +SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 +SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) +SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 +SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF +SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 +SDMA_PKT_SRBM_WRITE_ADDR_ADDR = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 +SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) +SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 +SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF +SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 +SDMA_PKT_SRBM_WRITE_DATA_DATA = lambda x: (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) +SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 +SDMA_PKT_PRE_EXE_HEADER_OP = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) +SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 +SDMA_PKT_PRE_EXE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) +SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 +SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF +SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 +SDMA_PKT_PRE_EXE_HEADER_DEV_SEL = lambda x: (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 +SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT = lambda x: (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) +SDMA_PKT_COND_EXE_HEADER_op_offset = 0 +SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF +SDMA_PKT_COND_EXE_HEADER_op_shift = 0 +SDMA_PKT_COND_EXE_HEADER_OP = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) +SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 +SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 +SDMA_PKT_COND_EXE_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) +SDMA_PKT_COND_EXE_HEADER_cache_policy_offset = 0 +SDMA_PKT_COND_EXE_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_COND_EXE_HEADER_cache_policy_shift = 24 +SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_cache_policy_mask) << SDMA_PKT_COND_EXE_HEADER_cache_policy_shift) +SDMA_PKT_COND_EXE_HEADER_cpv_offset = 0 +SDMA_PKT_COND_EXE_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_COND_EXE_HEADER_cpv_shift = 28 +SDMA_PKT_COND_EXE_HEADER_CPV = lambda x: (((x) & SDMA_PKT_COND_EXE_HEADER_cpv_mask) << SDMA_PKT_COND_EXE_HEADER_cpv_shift) +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) +SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 +SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF +SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 +SDMA_PKT_COND_EXE_REFERENCE_REFERENCE = lambda x: (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 +SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT = lambda x: (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF +SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_OP = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 +SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 +SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 +SDMA_PKT_CONSTANT_FILL_HEADER_SW = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift = 24 +SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift = 28 +SDMA_PKT_CONSTANT_FILL_HEADER_CPV = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift) +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 +SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 +SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0 = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) +SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 +SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x3FFFFFFF +SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 +SDMA_PKT_CONSTANT_FILL_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_OP = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 +SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift = 24 +SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift = 28 +SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift) +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 +SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT = lambda x: (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) +SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_REGMEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift = 20 +SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift) +SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift = 24 +SDMA_PKT_POLL_REGMEM_HEADER_CPV = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift) +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 +SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) +SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 +SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 +SDMA_PKT_POLL_REGMEM_HEADER_FUNC = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 +SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 +SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 +SDMA_PKT_POLL_REGMEM_VALUE_VALUE = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) +SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 +SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 +SDMA_PKT_POLL_REGMEM_MASK_MASK = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) +SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 +SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF +SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 +SDMA_PKT_POLL_REGMEM_DW5_INTERVAL = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) +SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 +SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF +SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 +SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT = lambda x: (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift = 24 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift = 28 +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift = 24 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift = 28 +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0 = lambda x: (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift = 24 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift = 28 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 +SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset = 4 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset = 5 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32 = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED = lambda x: (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) +SDMA_PKT_ATOMIC_HEADER_op_offset = 0 +SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF +SDMA_PKT_ATOMIC_HEADER_op_shift = 0 +SDMA_PKT_ATOMIC_HEADER_OP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) +SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 +SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 +SDMA_PKT_ATOMIC_HEADER_LOOP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) +SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 +SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 +SDMA_PKT_ATOMIC_HEADER_TMZ = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) +SDMA_PKT_ATOMIC_HEADER_cache_policy_offset = 0 +SDMA_PKT_ATOMIC_HEADER_cache_policy_mask = 0x00000007 +SDMA_PKT_ATOMIC_HEADER_cache_policy_shift = 20 +SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_cache_policy_mask) << SDMA_PKT_ATOMIC_HEADER_cache_policy_shift) +SDMA_PKT_ATOMIC_HEADER_cpv_offset = 0 +SDMA_PKT_ATOMIC_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_ATOMIC_HEADER_cpv_shift = 24 +SDMA_PKT_ATOMIC_HEADER_CPV = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_cpv_mask) << SDMA_PKT_ATOMIC_HEADER_cpv_shift) +SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 +SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F +SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 +SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP = lambda x: (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 +SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 +SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 +SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 +SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 +SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0 = lambda x: (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 +SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32 = lambda x: (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 +SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL = lambda x: (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) +SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift = 24 +SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask = 0x00000001 +SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift = 26 +SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift) +SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset = 0 +SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift = 28 +SDMA_PKT_TIMESTAMP_GET_HEADER_CPV = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask = 0x00000003 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift = 24 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask = 0x00000001 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift = 26 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask = 0x00000001 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift = 28 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32 = lambda x: (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) +SDMA_PKT_TRAP_HEADER_op_offset = 0 +SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF +SDMA_PKT_TRAP_HEADER_op_shift = 0 +SDMA_PKT_TRAP_HEADER_OP = lambda x: (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) +SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 +SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 +SDMA_PKT_TRAP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) +SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 +SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF +SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 +SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT = lambda x: (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) +SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF +SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_OP = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 +SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT = lambda x: (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) +SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 +SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF +SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 +SDMA_PKT_GPUVM_INV_HEADER_OP = lambda x: (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) +SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 +SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 +SDMA_PKT_GPUVM_INV_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 +SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 +SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 +SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 +SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 +SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 +SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 +SDMA_PKT_GPUVM_INV_PAYLOAD2_S = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 +SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 +SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43 = lambda x: (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) +SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 +SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF +SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 +SDMA_PKT_GCR_REQ_HEADER_OP = lambda x: (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) +SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 +SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 +SDMA_PKT_GCR_REQ_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 +SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 +SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 +SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 +SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 +SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 +SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32 = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 +SDMA_PKT_GCR_REQ_PAYLOAD4_VMID = lambda x: (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) +SDMA_PKT_NOP_HEADER_op_offset = 0 +SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF +SDMA_PKT_NOP_HEADER_op_shift = 0 +SDMA_PKT_NOP_HEADER_OP = lambda x: (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) +SDMA_PKT_NOP_HEADER_sub_op_offset = 0 +SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF +SDMA_PKT_NOP_HEADER_sub_op_shift = 8 +SDMA_PKT_NOP_HEADER_SUB_OP = lambda x: (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) +SDMA_PKT_NOP_HEADER_count_offset = 0 +SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF +SDMA_PKT_NOP_HEADER_count_shift = 16 +SDMA_PKT_NOP_HEADER_COUNT = lambda x: (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) +SDMA_PKT_NOP_DATA0_data0_offset = 1 +SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF +SDMA_PKT_NOP_DATA0_data0_shift = 0 +SDMA_PKT_NOP_DATA0_DATA0 = lambda x: (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) +SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 +SDMA_AQL_PKT_HEADER_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) +SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_HEADER_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_HEADER_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) +SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 +SDMA_AQL_PKT_HEADER_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) +SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 +SDMA_AQL_PKT_HEADER_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) +SDMA_AQL_PKT_HEADER_HEADER_cpv_offset = 0 +SDMA_AQL_PKT_HEADER_HEADER_cpv_mask = 0x00000001 +SDMA_AQL_PKT_HEADER_HEADER_cpv_shift = 28 +SDMA_AQL_PKT_HEADER_HEADER_CPV = lambda x: (((x) & SDMA_AQL_PKT_HEADER_HEADER_cpv_mask) << SDMA_AQL_PKT_HEADER_HEADER_cpv_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift = 28 +SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 5 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32 = lambda x: (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 +SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 +SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 +SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 +SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 +SDMA_AQL_PKT_BARRIER_OR_HEADER_OP = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 +SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) +SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset = 0 +SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask = 0x00000001 +SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift = 28 +SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift = 5 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift = 10 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift = 15 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset = 12 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask = 0x00000007 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift = 20 +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32 = lambda x: (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/smu_v13_0_0.py b/tinygrad/runtime/autogen/am/smu_v13_0_0.py index b4257a2454..af87e13984 100644 --- a/tinygrad/runtime/autogen/am/smu_v13_0_0.py +++ b/tinygrad/runtime/autogen/am/smu_v13_0_0.py @@ -1,3070 +1,1030 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -SMU_V13_0_0_PPSMC_H = True # macro -PPSMC_VERSION = 0x1 # macro -DEBUGSMC_VERSION = 0x1 # macro -PPSMC_Result_OK = 0x1 # macro -PPSMC_Result_Failed = 0xFF # macro -PPSMC_Result_UnknownCmd = 0xFE # macro -PPSMC_Result_CmdRejectedPrereq = 0xFD # macro -PPSMC_Result_CmdRejectedBusy = 0xFC # macro -PPSMC_MSG_TestMessage = 0x1 # macro -PPSMC_MSG_GetSmuVersion = 0x2 # macro -PPSMC_MSG_GetDriverIfVersion = 0x3 # macro -PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 # macro -PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 # macro -PPSMC_MSG_EnableAllSmuFeatures = 0x6 # macro -PPSMC_MSG_DisableAllSmuFeatures = 0x7 # macro -PPSMC_MSG_EnableSmuFeaturesLow = 0x8 # macro -PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 # macro -PPSMC_MSG_DisableSmuFeaturesLow = 0xA # macro -PPSMC_MSG_DisableSmuFeaturesHigh = 0xB # macro -PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC # macro -PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD # macro -PPSMC_MSG_SetDriverDramAddrHigh = 0xE # macro -PPSMC_MSG_SetDriverDramAddrLow = 0xF # macro -PPSMC_MSG_SetToolsDramAddrHigh = 0x10 # macro -PPSMC_MSG_SetToolsDramAddrLow = 0x11 # macro -PPSMC_MSG_TransferTableSmu2Dram = 0x12 # macro -PPSMC_MSG_TransferTableDram2Smu = 0x13 # macro -PPSMC_MSG_UseDefaultPPTable = 0x14 # macro -PPSMC_MSG_EnterBaco = 0x15 # macro -PPSMC_MSG_ExitBaco = 0x16 # macro -PPSMC_MSG_ArmD3 = 0x17 # macro -PPSMC_MSG_BacoAudioD3PME = 0x18 # macro -PPSMC_MSG_SetSoftMinByFreq = 0x19 # macro -PPSMC_MSG_SetSoftMaxByFreq = 0x1A # macro -PPSMC_MSG_SetHardMinByFreq = 0x1B # macro -PPSMC_MSG_SetHardMaxByFreq = 0x1C # macro -PPSMC_MSG_GetMinDpmFreq = 0x1D # macro -PPSMC_MSG_GetMaxDpmFreq = 0x1E # macro -PPSMC_MSG_GetDpmFreqByIndex = 0x1F # macro -PPSMC_MSG_OverridePcieParameters = 0x20 # macro -PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 # macro -PPSMC_MSG_DramLogSetDramAddrLow = 0x22 # macro -PPSMC_MSG_DramLogSetDramSize = 0x23 # macro -PPSMC_MSG_SetWorkloadMask = 0x24 # macro -PPSMC_MSG_GetVoltageByDpm = 0x25 # macro -PPSMC_MSG_SetVideoFps = 0x26 # macro -PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 # macro -PPSMC_MSG_AllowGfxOff = 0x28 # macro -PPSMC_MSG_DisallowGfxOff = 0x29 # macro -PPSMC_MSG_PowerUpVcn = 0x2A # macro -PPSMC_MSG_PowerDownVcn = 0x2B # macro -PPSMC_MSG_PowerUpJpeg = 0x2C # macro -PPSMC_MSG_PowerDownJpeg = 0x2D # macro -PPSMC_MSG_PrepareMp1ForUnload = 0x2E # macro -PPSMC_MSG_Mode1Reset = 0x2F # macro -PPSMC_MSG_Mode2Reset = 0x4F # macro -PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 # macro -PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 # macro -PPSMC_MSG_SetPptLimit = 0x32 # macro -PPSMC_MSG_GetPptLimit = 0x33 # macro -PPSMC_MSG_ReenableAcDcInterrupt = 0x34 # macro -PPSMC_MSG_NotifyPowerSource = 0x35 # macro -PPSMC_MSG_RunDcBtc = 0x36 # macro -PPSMC_MSG_GetDebugData = 0x37 # macro -PPSMC_MSG_SetTemperatureInputSelect = 0x38 # macro -PPSMC_MSG_SetFwDstatesMask = 0x39 # macro -PPSMC_MSG_SetThrottlerMask = 0x3A # macro -PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B # macro -PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C # macro -PPSMC_MSG_DumpSTBtoDram = 0x3D # macro -PPSMC_MSG_STBtoDramLogSetDramAddrHigh = 0x3E # macro -PPSMC_MSG_STBtoDramLogSetDramAddrLow = 0x3F # macro -PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 # macro -PPSMC_MSG_SetGpoAllow = 0x41 # macro -PPSMC_MSG_AllowGfxDcs = 0x42 # macro -PPSMC_MSG_DisallowGfxDcs = 0x43 # macro -PPSMC_MSG_EnableAudioStutterWA = 0x44 # macro -PPSMC_MSG_PowerUpUmsch = 0x45 # macro -PPSMC_MSG_PowerDownUmsch = 0x46 # macro -PPSMC_MSG_SetDcsArch = 0x47 # macro -PPSMC_MSG_TriggerVFFLR = 0x48 # macro -PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x49 # macro -PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4A # macro -PPSMC_MSG_SetPriorityDeltaGain = 0x4B # macro -PPSMC_MSG_AllowIHHostInterrupt = 0x4C # macro -PPSMC_MSG_DALNotPresent = 0x4E # macro -PPSMC_MSG_EnableUCLKShadow = 0x51 # macro -PPSMC_Message_Count = 0x52 # macro -DEBUGSMC_MSG_TestMessage = 0x1 # macro -DEBUGSMC_MSG_GetDebugData = 0x2 # macro -DEBUGSMC_MSG_DebugDumpExit = 0x3 # macro -DEBUGSMC_Message_Count = 0x4 # macro -SMU13_DRIVER_IF_V13_0_0_H = True # macro -int32_t = True # macro -uint32_t = True # macro -int8_t = True # macro -uint8_t = True # macro -uint16_t = True # macro -int16_t = True # macro -uint64_t = True # macro -bool = True # macro -SMU13_0_0_DRIVER_IF_VERSION = 0x3D # macro -PPTABLE_VERSION = 0x2B # macro -NUM_GFXCLK_DPM_LEVELS = 16 # macro -NUM_SOCCLK_DPM_LEVELS = 8 # macro -NUM_MP0CLK_DPM_LEVELS = 2 # macro -NUM_DCLK_DPM_LEVELS = 8 # macro -NUM_VCLK_DPM_LEVELS = 8 # macro -NUM_DISPCLK_DPM_LEVELS = 8 # macro -NUM_DPPCLK_DPM_LEVELS = 8 # macro -NUM_DPREFCLK_DPM_LEVELS = 8 # macro -NUM_DCFCLK_DPM_LEVELS = 8 # macro -NUM_DTBCLK_DPM_LEVELS = 8 # macro -NUM_UCLK_DPM_LEVELS = 4 # macro -NUM_LINK_LEVELS = 3 # macro -NUM_FCLK_DPM_LEVELS = 8 # macro -NUM_OD_FAN_MAX_POINTS = 6 # macro -FEATURE_FW_DATA_READ_BIT = 0 # macro -FEATURE_DPM_GFXCLK_BIT = 1 # macro -FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 # macro -FEATURE_DPM_UCLK_BIT = 3 # macro -FEATURE_DPM_FCLK_BIT = 4 # macro -FEATURE_DPM_SOCCLK_BIT = 5 # macro -FEATURE_DPM_MP0CLK_BIT = 6 # macro -FEATURE_DPM_LINK_BIT = 7 # macro -FEATURE_DPM_DCN_BIT = 8 # macro -FEATURE_VMEMP_SCALING_BIT = 9 # macro -FEATURE_VDDIO_MEM_SCALING_BIT = 10 # macro -FEATURE_DS_GFXCLK_BIT = 11 # macro -FEATURE_DS_SOCCLK_BIT = 12 # macro -FEATURE_DS_FCLK_BIT = 13 # macro -FEATURE_DS_LCLK_BIT = 14 # macro -FEATURE_DS_DCFCLK_BIT = 15 # macro -FEATURE_DS_UCLK_BIT = 16 # macro -FEATURE_GFX_ULV_BIT = 17 # macro -FEATURE_FW_DSTATE_BIT = 18 # macro -FEATURE_GFXOFF_BIT = 19 # macro -FEATURE_BACO_BIT = 20 # macro -FEATURE_MM_DPM_BIT = 21 # macro -FEATURE_SOC_MPCLK_DS_BIT = 22 # macro -FEATURE_BACO_MPCLK_DS_BIT = 23 # macro -FEATURE_THROTTLERS_BIT = 24 # macro -FEATURE_SMARTSHIFT_BIT = 25 # macro -FEATURE_GTHR_BIT = 26 # macro -FEATURE_ACDC_BIT = 27 # macro -FEATURE_VR0HOT_BIT = 28 # macro -FEATURE_FW_CTF_BIT = 29 # macro -FEATURE_FAN_CONTROL_BIT = 30 # macro -FEATURE_GFX_DCS_BIT = 31 # macro -FEATURE_GFX_READ_MARGIN_BIT = 32 # macro -FEATURE_LED_DISPLAY_BIT = 33 # macro -FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 34 # macro -FEATURE_OUT_OF_BAND_MONITOR_BIT = 35 # macro -FEATURE_OPTIMIZED_VMIN_BIT = 36 # macro -FEATURE_GFX_IMU_BIT = 37 # macro -FEATURE_BOOT_TIME_CAL_BIT = 38 # macro -FEATURE_GFX_PCC_DFLL_BIT = 39 # macro -FEATURE_SOC_CG_BIT = 40 # macro -FEATURE_DF_CSTATE_BIT = 41 # macro -FEATURE_GFX_EDC_BIT = 42 # macro -FEATURE_BOOT_POWER_OPT_BIT = 43 # macro -FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 44 # macro -FEATURE_DS_VCN_BIT = 45 # macro -FEATURE_BACO_CG_BIT = 46 # macro -FEATURE_MEM_TEMP_READ_BIT = 47 # macro -FEATURE_ATHUB_MMHUB_PG_BIT = 48 # macro -FEATURE_SOC_PCC_BIT = 49 # macro -FEATURE_EDC_PWRBRK_BIT = 50 # macro -FEATURE_BOMXCO_SVI3_PROG_BIT = 51 # macro -FEATURE_SPARE_52_BIT = 52 # macro -FEATURE_SPARE_53_BIT = 53 # macro -FEATURE_SPARE_54_BIT = 54 # macro -FEATURE_SPARE_55_BIT = 55 # macro -FEATURE_SPARE_56_BIT = 56 # macro -FEATURE_SPARE_57_BIT = 57 # macro -FEATURE_SPARE_58_BIT = 58 # macro -FEATURE_SPARE_59_BIT = 59 # macro -FEATURE_SPARE_60_BIT = 60 # macro -FEATURE_SPARE_61_BIT = 61 # macro -FEATURE_SPARE_62_BIT = 62 # macro -FEATURE_SPARE_63_BIT = 63 # macro -NUM_FEATURES = 64 # macro -ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF # macro -ALLOWED_FEATURE_CTRL_SCPM = ((1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<11)|(1<<12)|(1<<13)|(1<<14)|(1<<15)|(1<<16)|(1<<45)) # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK = 0x00000001 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 # macro -DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 # macro -DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 # macro -DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 # macro -DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 # macro -DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 # macro -DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 # macro -DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 # macro -DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 # macro -DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 # macro -VR_MAPPING_VR_SELECT_MASK = 0x01 # macro -VR_MAPPING_VR_SELECT_SHIFT = 0x00 # macro -VR_MAPPING_PLANE_SELECT_MASK = 0x02 # macro -VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI0 = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI1 = 0x02 # macro -PSI_SEL_VR0_PLANE1_PSI0 = 0x04 # macro -PSI_SEL_VR0_PLANE1_PSI1 = 0x08 # macro -PSI_SEL_VR1_PLANE0_PSI0 = 0x10 # macro -PSI_SEL_VR1_PLANE0_PSI1 = 0x20 # macro -PSI_SEL_VR1_PLANE1_PSI0 = 0x40 # macro -PSI_SEL_VR1_PLANE1_PSI1 = 0x80 # macro -THROTTLER_TEMP_EDGE_BIT = 0 # macro -THROTTLER_TEMP_HOTSPOT_BIT = 1 # macro -THROTTLER_TEMP_HOTSPOT_G_BIT = 2 # macro -THROTTLER_TEMP_HOTSPOT_M_BIT = 3 # macro -THROTTLER_TEMP_MEM_BIT = 4 # macro -THROTTLER_TEMP_VR_GFX_BIT = 5 # macro -THROTTLER_TEMP_VR_MEM0_BIT = 6 # macro -THROTTLER_TEMP_VR_MEM1_BIT = 7 # macro -THROTTLER_TEMP_VR_SOC_BIT = 8 # macro -THROTTLER_TEMP_VR_U_BIT = 9 # macro -THROTTLER_TEMP_LIQUID0_BIT = 10 # macro -THROTTLER_TEMP_LIQUID1_BIT = 11 # macro -THROTTLER_TEMP_PLX_BIT = 12 # macro -THROTTLER_TDC_GFX_BIT = 13 # macro -THROTTLER_TDC_SOC_BIT = 14 # macro -THROTTLER_TDC_U_BIT = 15 # macro -THROTTLER_PPT0_BIT = 16 # macro -THROTTLER_PPT1_BIT = 17 # macro -THROTTLER_PPT2_BIT = 18 # macro -THROTTLER_PPT3_BIT = 19 # macro -THROTTLER_FIT_BIT = 20 # macro -THROTTLER_GFX_APCC_PLUS_BIT = 21 # macro -THROTTLER_COUNT = 22 # macro -FW_DSTATE_SOC_ULV_BIT = 0 # macro -FW_DSTATE_G6_HSR_BIT = 1 # macro -FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 # macro -FW_DSTATE_SMN_DS_BIT = 3 # macro -FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 # macro -FW_DSTATE_SOC_LIV_MIN_BIT = 5 # macro -FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 # macro -FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 # macro -FW_DSTATE_MALL_ALLOC_BIT = 8 # macro -FW_DSTATE_MEM_PSI_BIT = 9 # macro -FW_DSTATE_HSR_NON_STROBE_BIT = 10 # macro -FW_DSTATE_MP0_ENTER_WFI_BIT = 11 # macro -FW_DSTATE_U_ULV_BIT = 12 # macro -FW_DSTATE_MALL_FLUSH_BIT = 13 # macro -FW_DSTATE_SOC_PSI_BIT = 14 # macro -FW_DSTATE_U_PSI_BIT = 15 # macro -FW_DSTATE_UCP_DS_BIT = 16 # macro -FW_DSTATE_CSRCLK_DS_BIT = 17 # macro -FW_DSTATE_MMHUB_INTERLOCK_BIT = 18 # macro -FW_DSTATE_D0i3_2_QUIET_FW_BIT = 19 # macro -FW_DSTATE_CLDO_PRG_BIT = 20 # macro -FW_DSTATE_DF_PLL_PWRDN_BIT = 21 # macro -FW_DSTATE_U_LOW_PWR_MODE_EN_BIT = 22 # macro -FW_DSTATE_GFX_PSI6_BIT = 23 # macro -FW_DSTATE_GFX_VR_PWR_STAGE_BIT = 24 # macro -LED_DISPLAY_GFX_DPM_BIT = 0 # macro -LED_DISPLAY_PCIE_BIT = 1 # macro -LED_DISPLAY_ERROR_BIT = 2 # macro -MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 # macro -MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 # macro -MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 # macro -NUM_I2C_CONTROLLERS = 8 # macro -I2C_CONTROLLER_ENABLED = 1 # macro -I2C_CONTROLLER_DISABLED = 0 # macro -MAX_SW_I2C_COMMANDS = 24 # macro -CMDCONFIG_STOP_BIT = 0 # macro -CMDCONFIG_RESTART_BIT = 1 # macro -CMDCONFIG_READWRITE_BIT = 2 # macro -CMDCONFIG_STOP_MASK = (1<<0) # macro -CMDCONFIG_RESTART_MASK = (1<<1) # macro -CMDCONFIG_READWRITE_MASK = (1<<2) # macro -PP_NUM_RTAVFS_PWL_ZONES = 5 # macro -PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 # macro -PP_OD_FEATURE_PPT_BIT = 2 # macro -PP_OD_FEATURE_FAN_CURVE_BIT = 3 # macro -PP_OD_FEATURE_GFXCLK_BIT = 7 # macro -PP_OD_FEATURE_UCLK_BIT = 8 # macro -PP_OD_FEATURE_ZERO_FAN_BIT = 9 # macro -PP_OD_FEATURE_TEMPERATURE_BIT = 10 # macro -PP_OD_FEATURE_COUNT = 13 # macro -PP_NUM_OD_VF_CURVE_POINTS = 5 + 1 # macro -INVALID_BOARD_GPIO = 0xFF # macro -MARKETING_BASE_CLOCKS = 0 # macro -MARKETING_GAME_CLOCKS = 1 # macro -MARKETING_BOOST_CLOCKS = 2 # macro -NUM_WM_RANGES = 4 # macro -WORKLOAD_PPLIB_DEFAULT_BIT = 0 # macro -WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 # macro -WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 # macro -WORKLOAD_PPLIB_VIDEO_BIT = 3 # macro -WORKLOAD_PPLIB_VR_BIT = 4 # macro -WORKLOAD_PPLIB_COMPUTE_BIT = 5 # macro -WORKLOAD_PPLIB_CUSTOM_BIT = 6 # macro -WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 # macro -WORKLOAD_PPLIB_COUNT = 8 # macro -TABLE_TRANSFER_OK = 0x0 # macro -TABLE_TRANSFER_FAILED = 0xFF # macro -TABLE_TRANSFER_PENDING = 0xAB # macro -TABLE_PPTABLE = 0 # macro -TABLE_COMBO_PPTABLE = 1 # macro -TABLE_WATERMARKS = 2 # macro -TABLE_AVFS_PSM_DEBUG = 3 # macro -TABLE_PMSTATUSLOG = 4 # macro -TABLE_SMU_METRICS = 5 # macro -TABLE_DRIVER_SMU_CONFIG = 6 # macro -TABLE_ACTIVITY_MONITOR_COEFF = 7 # macro -TABLE_OVERDRIVE = 8 # macro -TABLE_I2C_COMMANDS = 9 # macro -TABLE_DRIVER_INFO = 10 # macro -TABLE_ECCINFO = 11 # macro -TABLE_WIFIBAND = 12 # macro -TABLE_COUNT = 13 # macro -IH_INTERRUPT_ID_TO_DRIVER = 0xFE # macro -IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 # macro -IH_INTERRUPT_CONTEXT_ID_AC = 0x3 # macro -IH_INTERRUPT_CONTEXT_ID_DC = 0x4 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 # macro -IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 # macro - -# values for enumeration 'c__EA_FEATURE_PWR_DOMAIN_e' -c__EA_FEATURE_PWR_DOMAIN_e__enumvalues = { - 0: 'FEATURE_PWR_ALL', - 1: 'FEATURE_PWR_S5', - 2: 'FEATURE_PWR_BACO', - 3: 'FEATURE_PWR_SOC', - 4: 'FEATURE_PWR_GFX', - 5: 'FEATURE_PWR_DOMAIN_COUNT', -} -FEATURE_PWR_ALL = 0 -FEATURE_PWR_S5 = 1 -FEATURE_PWR_BACO = 2 -FEATURE_PWR_SOC = 3 -FEATURE_PWR_GFX = 4 -FEATURE_PWR_DOMAIN_COUNT = 5 -c__EA_FEATURE_PWR_DOMAIN_e = ctypes.c_uint32 # enum -FEATURE_PWR_DOMAIN_e = c__EA_FEATURE_PWR_DOMAIN_e -FEATURE_PWR_DOMAIN_e__enumvalues = c__EA_FEATURE_PWR_DOMAIN_e__enumvalues - -# values for enumeration 'c__EA_SVI_PSI_e' -c__EA_SVI_PSI_e__enumvalues = { - 0: 'SVI_PSI_0', - 1: 'SVI_PSI_1', - 2: 'SVI_PSI_2', - 3: 'SVI_PSI_3', - 4: 'SVI_PSI_4', - 5: 'SVI_PSI_5', - 6: 'SVI_PSI_6', - 7: 'SVI_PSI_7', -} -SVI_PSI_0 = 0 -SVI_PSI_1 = 1 -SVI_PSI_2 = 2 -SVI_PSI_3 = 3 -SVI_PSI_4 = 4 -SVI_PSI_5 = 5 -SVI_PSI_6 = 6 -SVI_PSI_7 = 7 -c__EA_SVI_PSI_e = ctypes.c_uint32 # enum -SVI_PSI_e = c__EA_SVI_PSI_e -SVI_PSI_e__enumvalues = c__EA_SVI_PSI_e__enumvalues - -# values for enumeration 'c__EA_SMARTSHIFT_VERSION_e' -c__EA_SMARTSHIFT_VERSION_e__enumvalues = { - 0: 'SMARTSHIFT_VERSION_1', - 1: 'SMARTSHIFT_VERSION_2', - 2: 'SMARTSHIFT_VERSION_3', -} -SMARTSHIFT_VERSION_1 = 0 -SMARTSHIFT_VERSION_2 = 1 -SMARTSHIFT_VERSION_3 = 2 -c__EA_SMARTSHIFT_VERSION_e = ctypes.c_uint32 # enum -SMARTSHIFT_VERSION_e = c__EA_SMARTSHIFT_VERSION_e -SMARTSHIFT_VERSION_e__enumvalues = c__EA_SMARTSHIFT_VERSION_e__enumvalues - -# values for enumeration 'c__EA_FOPT_CALC_e' -c__EA_FOPT_CALC_e__enumvalues = { - 0: 'FOPT_CALC_AC_CALC_DC', - 1: 'FOPT_PPTABLE_AC_CALC_DC', - 2: 'FOPT_CALC_AC_PPTABLE_DC', - 3: 'FOPT_PPTABLE_AC_PPTABLE_DC', -} -FOPT_CALC_AC_CALC_DC = 0 -FOPT_PPTABLE_AC_CALC_DC = 1 -FOPT_CALC_AC_PPTABLE_DC = 2 -FOPT_PPTABLE_AC_PPTABLE_DC = 3 -c__EA_FOPT_CALC_e = ctypes.c_uint32 # enum -FOPT_CALC_e = c__EA_FOPT_CALC_e -FOPT_CALC_e__enumvalues = c__EA_FOPT_CALC_e__enumvalues - -# values for enumeration 'c__EA_DRAM_BIT_WIDTH_TYPE_e' -c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues = { - 0: 'DRAM_BIT_WIDTH_DISABLED', - 8: 'DRAM_BIT_WIDTH_X_8', - 16: 'DRAM_BIT_WIDTH_X_16', - 32: 'DRAM_BIT_WIDTH_X_32', - 64: 'DRAM_BIT_WIDTH_X_64', - 128: 'DRAM_BIT_WIDTH_X_128', - 129: 'DRAM_BIT_WIDTH_COUNT', -} -DRAM_BIT_WIDTH_DISABLED = 0 -DRAM_BIT_WIDTH_X_8 = 8 -DRAM_BIT_WIDTH_X_16 = 16 -DRAM_BIT_WIDTH_X_32 = 32 -DRAM_BIT_WIDTH_X_64 = 64 -DRAM_BIT_WIDTH_X_128 = 128 -DRAM_BIT_WIDTH_COUNT = 129 -c__EA_DRAM_BIT_WIDTH_TYPE_e = ctypes.c_uint32 # enum -DRAM_BIT_WIDTH_TYPE_e = c__EA_DRAM_BIT_WIDTH_TYPE_e -DRAM_BIT_WIDTH_TYPE_e__enumvalues = c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerPort_e' -c__EA_I2cControllerPort_e__enumvalues = { - 0: 'I2C_CONTROLLER_PORT_0', - 1: 'I2C_CONTROLLER_PORT_1', - 2: 'I2C_CONTROLLER_PORT_COUNT', -} -I2C_CONTROLLER_PORT_0 = 0 -I2C_CONTROLLER_PORT_1 = 1 -I2C_CONTROLLER_PORT_COUNT = 2 -c__EA_I2cControllerPort_e = ctypes.c_uint32 # enum -I2cControllerPort_e = c__EA_I2cControllerPort_e -I2cControllerPort_e__enumvalues = c__EA_I2cControllerPort_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerName_e' -c__EA_I2cControllerName_e__enumvalues = { - 0: 'I2C_CONTROLLER_NAME_VR_GFX', - 1: 'I2C_CONTROLLER_NAME_VR_SOC', - 2: 'I2C_CONTROLLER_NAME_VR_VMEMP', - 3: 'I2C_CONTROLLER_NAME_VR_VDDIO', - 4: 'I2C_CONTROLLER_NAME_LIQUID0', - 5: 'I2C_CONTROLLER_NAME_LIQUID1', - 6: 'I2C_CONTROLLER_NAME_PLX', - 7: 'I2C_CONTROLLER_NAME_FAN_INTAKE', - 8: 'I2C_CONTROLLER_NAME_COUNT', -} -I2C_CONTROLLER_NAME_VR_GFX = 0 -I2C_CONTROLLER_NAME_VR_SOC = 1 -I2C_CONTROLLER_NAME_VR_VMEMP = 2 -I2C_CONTROLLER_NAME_VR_VDDIO = 3 -I2C_CONTROLLER_NAME_LIQUID0 = 4 -I2C_CONTROLLER_NAME_LIQUID1 = 5 -I2C_CONTROLLER_NAME_PLX = 6 -I2C_CONTROLLER_NAME_FAN_INTAKE = 7 -I2C_CONTROLLER_NAME_COUNT = 8 -c__EA_I2cControllerName_e = ctypes.c_uint32 # enum -I2cControllerName_e = c__EA_I2cControllerName_e -I2cControllerName_e__enumvalues = c__EA_I2cControllerName_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerThrottler_e' -c__EA_I2cControllerThrottler_e__enumvalues = { - 0: 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 1: 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 2: 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 3: 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', - 4: 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 5: 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 6: 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 7: 'I2C_CONTROLLER_THROTTLER_PLX', - 8: 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 9: 'I2C_CONTROLLER_THROTTLER_INA3221', - 10: 'I2C_CONTROLLER_THROTTLER_COUNT', -} -I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0 -I2C_CONTROLLER_THROTTLER_VR_GFX = 1 -I2C_CONTROLLER_THROTTLER_VR_SOC = 2 -I2C_CONTROLLER_THROTTLER_VR_VMEMP = 3 -I2C_CONTROLLER_THROTTLER_VR_VDDIO = 4 -I2C_CONTROLLER_THROTTLER_LIQUID0 = 5 -I2C_CONTROLLER_THROTTLER_LIQUID1 = 6 -I2C_CONTROLLER_THROTTLER_PLX = 7 -I2C_CONTROLLER_THROTTLER_FAN_INTAKE = 8 -I2C_CONTROLLER_THROTTLER_INA3221 = 9 -I2C_CONTROLLER_THROTTLER_COUNT = 10 -c__EA_I2cControllerThrottler_e = ctypes.c_uint32 # enum -I2cControllerThrottler_e = c__EA_I2cControllerThrottler_e -I2cControllerThrottler_e__enumvalues = c__EA_I2cControllerThrottler_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerProtocol_e' -c__EA_I2cControllerProtocol_e__enumvalues = { - 0: 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 1: 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 2: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 3: 'I2C_CONTROLLER_PROTOCOL_INA3221', - 4: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 5: 'I2C_CONTROLLER_PROTOCOL_COUNT', -} -I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = 0 -I2C_CONTROLLER_PROTOCOL_VR_IR35217 = 1 -I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = 2 -I2C_CONTROLLER_PROTOCOL_INA3221 = 3 -I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = 4 -I2C_CONTROLLER_PROTOCOL_COUNT = 5 -c__EA_I2cControllerProtocol_e = ctypes.c_uint32 # enum -I2cControllerProtocol_e = c__EA_I2cControllerProtocol_e -I2cControllerProtocol_e__enumvalues = c__EA_I2cControllerProtocol_e__enumvalues -class struct_c__SA_I2cControllerConfig_t(Structure): - pass - -struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False -struct_c__SA_I2cControllerConfig_t._fields_ = [ - ('Enabled', ctypes.c_ubyte), - ('Speed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('ControllerPort', ctypes.c_ubyte), - ('ControllerName', ctypes.c_ubyte), - ('ThermalThrotter', ctypes.c_ubyte), - ('I2cProtocol', ctypes.c_ubyte), - ('PaddingConfig', ctypes.c_ubyte), -] - -I2cControllerConfig_t = struct_c__SA_I2cControllerConfig_t - -# values for enumeration 'c__EA_I2cPort_e' -c__EA_I2cPort_e__enumvalues = { - 0: 'I2C_PORT_SVD_SCL', - 1: 'I2C_PORT_GPIO', -} -I2C_PORT_SVD_SCL = 0 -I2C_PORT_GPIO = 1 -c__EA_I2cPort_e = ctypes.c_uint32 # enum -I2cPort_e = c__EA_I2cPort_e -I2cPort_e__enumvalues = c__EA_I2cPort_e__enumvalues - -# values for enumeration 'c__EA_I2cSpeed_e' -c__EA_I2cSpeed_e__enumvalues = { - 0: 'I2C_SPEED_FAST_50K', - 1: 'I2C_SPEED_FAST_100K', - 2: 'I2C_SPEED_FAST_400K', - 3: 'I2C_SPEED_FAST_PLUS_1M', - 4: 'I2C_SPEED_HIGH_1M', - 5: 'I2C_SPEED_HIGH_2M', - 6: 'I2C_SPEED_COUNT', -} -I2C_SPEED_FAST_50K = 0 -I2C_SPEED_FAST_100K = 1 -I2C_SPEED_FAST_400K = 2 -I2C_SPEED_FAST_PLUS_1M = 3 -I2C_SPEED_HIGH_1M = 4 -I2C_SPEED_HIGH_2M = 5 -I2C_SPEED_COUNT = 6 -c__EA_I2cSpeed_e = ctypes.c_uint32 # enum -I2cSpeed_e = c__EA_I2cSpeed_e -I2cSpeed_e__enumvalues = c__EA_I2cSpeed_e__enumvalues - -# values for enumeration 'c__EA_I2cCmdType_e' -c__EA_I2cCmdType_e__enumvalues = { - 0: 'I2C_CMD_READ', - 1: 'I2C_CMD_WRITE', - 2: 'I2C_CMD_COUNT', -} -I2C_CMD_READ = 0 -I2C_CMD_WRITE = 1 -I2C_CMD_COUNT = 2 -c__EA_I2cCmdType_e = ctypes.c_uint32 # enum -I2cCmdType_e = c__EA_I2cCmdType_e -I2cCmdType_e__enumvalues = c__EA_I2cCmdType_e__enumvalues -class struct_c__SA_SwI2cCmd_t(Structure): - pass - -struct_c__SA_SwI2cCmd_t._pack_ = 1 # source:False -struct_c__SA_SwI2cCmd_t._fields_ = [ - ('ReadWriteData', ctypes.c_ubyte), - ('CmdConfig', ctypes.c_ubyte), -] - -SwI2cCmd_t = struct_c__SA_SwI2cCmd_t -class struct_c__SA_SwI2cRequest_t(Structure): - pass - -struct_c__SA_SwI2cRequest_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequest_t._fields_ = [ - ('I2CcontrollerPort', ctypes.c_ubyte), - ('I2CSpeed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('NumCmds', ctypes.c_ubyte), - ('SwI2cCmds', struct_c__SA_SwI2cCmd_t * 24), -] - -SwI2cRequest_t = struct_c__SA_SwI2cRequest_t -class struct_c__SA_SwI2cRequestExternal_t(Structure): - pass - -struct_c__SA_SwI2cRequestExternal_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequestExternal_t._fields_ = [ - ('SwI2cRequest', SwI2cRequest_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SwI2cRequestExternal_t = struct_c__SA_SwI2cRequestExternal_t -class struct_c__SA_EccInfo_t(Structure): - pass - -struct_c__SA_EccInfo_t._pack_ = 1 # source:False -struct_c__SA_EccInfo_t._fields_ = [ - ('mca_umc_status', ctypes.c_uint64), - ('mca_umc_addr', ctypes.c_uint64), - ('ce_count_lo_chip', ctypes.c_uint16), - ('ce_count_hi_chip', ctypes.c_uint16), - ('eccPadding', ctypes.c_uint32), -] - -EccInfo_t = struct_c__SA_EccInfo_t -class struct_c__SA_EccInfoTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('EccInfo', struct_c__SA_EccInfo_t * 24), - ] - -EccInfoTable_t = struct_c__SA_EccInfoTable_t - -# values for enumeration 'c__EA_D3HOTSequence_e' -c__EA_D3HOTSequence_e__enumvalues = { - 0: 'BACO_SEQUENCE', - 1: 'MSR_SEQUENCE', - 2: 'BAMACO_SEQUENCE', - 3: 'ULPS_SEQUENCE', - 4: 'D3HOT_SEQUENCE_COUNT', -} -BACO_SEQUENCE = 0 -MSR_SEQUENCE = 1 -BAMACO_SEQUENCE = 2 -ULPS_SEQUENCE = 3 -D3HOT_SEQUENCE_COUNT = 4 -c__EA_D3HOTSequence_e = ctypes.c_uint32 # enum -D3HOTSequence_e = c__EA_D3HOTSequence_e -D3HOTSequence_e__enumvalues = c__EA_D3HOTSequence_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingMode_e' -c__EA_PowerGatingMode_e__enumvalues = { - 0: 'PG_DYNAMIC_MODE', - 1: 'PG_STATIC_MODE', -} -PG_DYNAMIC_MODE = 0 -PG_STATIC_MODE = 1 -c__EA_PowerGatingMode_e = ctypes.c_uint32 # enum -PowerGatingMode_e = c__EA_PowerGatingMode_e -PowerGatingMode_e__enumvalues = c__EA_PowerGatingMode_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingSettings_e' -c__EA_PowerGatingSettings_e__enumvalues = { - 0: 'PG_POWER_DOWN', - 1: 'PG_POWER_UP', -} -PG_POWER_DOWN = 0 -PG_POWER_UP = 1 -c__EA_PowerGatingSettings_e = ctypes.c_uint32 # enum -PowerGatingSettings_e = c__EA_PowerGatingSettings_e -PowerGatingSettings_e__enumvalues = c__EA_PowerGatingSettings_e__enumvalues -class struct_c__SA_QuadraticInt_t(Structure): - pass - -struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False -struct_c__SA_QuadraticInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -QuadraticInt_t = struct_c__SA_QuadraticInt_t -class struct_c__SA_LinearInt_t(Structure): - pass - -struct_c__SA_LinearInt_t._pack_ = 1 # source:False -struct_c__SA_LinearInt_t._fields_ = [ - ('m', ctypes.c_uint32), - ('b', ctypes.c_uint32), -] - -LinearInt_t = struct_c__SA_LinearInt_t -class struct_c__SA_DroopInt_t(Structure): - pass - -struct_c__SA_DroopInt_t._pack_ = 1 # source:False -struct_c__SA_DroopInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), -] - -DroopInt_t = struct_c__SA_DroopInt_t - -# values for enumeration 'c__EA_DCS_ARCH_e' -c__EA_DCS_ARCH_e__enumvalues = { - 0: 'DCS_ARCH_DISABLED', - 1: 'DCS_ARCH_FADCS', - 2: 'DCS_ARCH_ASYNC', -} -DCS_ARCH_DISABLED = 0 -DCS_ARCH_FADCS = 1 -DCS_ARCH_ASYNC = 2 -c__EA_DCS_ARCH_e = ctypes.c_uint32 # enum -DCS_ARCH_e = c__EA_DCS_ARCH_e -DCS_ARCH_e__enumvalues = c__EA_DCS_ARCH_e__enumvalues - -# values for enumeration 'c__EA_PPCLK_e' -c__EA_PPCLK_e__enumvalues = { - 0: 'PPCLK_GFXCLK', - 1: 'PPCLK_SOCCLK', - 2: 'PPCLK_UCLK', - 3: 'PPCLK_FCLK', - 4: 'PPCLK_DCLK_0', - 5: 'PPCLK_VCLK_0', - 6: 'PPCLK_DCLK_1', - 7: 'PPCLK_VCLK_1', - 8: 'PPCLK_DISPCLK', - 9: 'PPCLK_DPPCLK', - 10: 'PPCLK_DPREFCLK', - 11: 'PPCLK_DCFCLK', - 12: 'PPCLK_DTBCLK', - 13: 'PPCLK_COUNT', -} -PPCLK_GFXCLK = 0 -PPCLK_SOCCLK = 1 -PPCLK_UCLK = 2 -PPCLK_FCLK = 3 -PPCLK_DCLK_0 = 4 -PPCLK_VCLK_0 = 5 -PPCLK_DCLK_1 = 6 -PPCLK_VCLK_1 = 7 -PPCLK_DISPCLK = 8 -PPCLK_DPPCLK = 9 -PPCLK_DPREFCLK = 10 -PPCLK_DCFCLK = 11 -PPCLK_DTBCLK = 12 -PPCLK_COUNT = 13 -c__EA_PPCLK_e = ctypes.c_uint32 # enum -PPCLK_e = c__EA_PPCLK_e -PPCLK_e__enumvalues = c__EA_PPCLK_e__enumvalues - -# values for enumeration 'c__EA_VOLTAGE_MODE_e' -c__EA_VOLTAGE_MODE_e__enumvalues = { - 0: 'VOLTAGE_MODE_PPTABLE', - 1: 'VOLTAGE_MODE_FUSES', - 2: 'VOLTAGE_MODE_COUNT', -} -VOLTAGE_MODE_PPTABLE = 0 -VOLTAGE_MODE_FUSES = 1 -VOLTAGE_MODE_COUNT = 2 -c__EA_VOLTAGE_MODE_e = ctypes.c_uint32 # enum -VOLTAGE_MODE_e = c__EA_VOLTAGE_MODE_e -VOLTAGE_MODE_e__enumvalues = c__EA_VOLTAGE_MODE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_VOLTAGE_TYPE_e' -c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues = { - 0: 'AVFS_VOLTAGE_GFX', - 1: 'AVFS_VOLTAGE_SOC', - 2: 'AVFS_VOLTAGE_COUNT', -} -AVFS_VOLTAGE_GFX = 0 -AVFS_VOLTAGE_SOC = 1 -AVFS_VOLTAGE_COUNT = 2 -c__EA_AVFS_VOLTAGE_TYPE_e = ctypes.c_uint32 # enum -AVFS_VOLTAGE_TYPE_e = c__EA_AVFS_VOLTAGE_TYPE_e -AVFS_VOLTAGE_TYPE_e__enumvalues = c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_TEMP_e' -c__EA_AVFS_TEMP_e__enumvalues = { - 0: 'AVFS_TEMP_COLD', - 1: 'AVFS_TEMP_HOT', - 2: 'AVFS_TEMP_COUNT', -} -AVFS_TEMP_COLD = 0 -AVFS_TEMP_HOT = 1 -AVFS_TEMP_COUNT = 2 -c__EA_AVFS_TEMP_e = ctypes.c_uint32 # enum -AVFS_TEMP_e = c__EA_AVFS_TEMP_e -AVFS_TEMP_e__enumvalues = c__EA_AVFS_TEMP_e__enumvalues - -# values for enumeration 'c__EA_AVFS_D_e' -c__EA_AVFS_D_e__enumvalues = { - 0: 'AVFS_D_G', - 1: 'AVFS_D_M_B', - 2: 'AVFS_D_M_S', - 3: 'AVFS_D_COUNT', -} -AVFS_D_G = 0 -AVFS_D_M_B = 1 -AVFS_D_M_S = 2 -AVFS_D_COUNT = 3 -c__EA_AVFS_D_e = ctypes.c_uint32 # enum -AVFS_D_e = c__EA_AVFS_D_e -AVFS_D_e__enumvalues = c__EA_AVFS_D_e__enumvalues - -# values for enumeration 'c__EA_UCLK_DIV_e' -c__EA_UCLK_DIV_e__enumvalues = { - 0: 'UCLK_DIV_BY_1', - 1: 'UCLK_DIV_BY_2', - 2: 'UCLK_DIV_BY_4', - 3: 'UCLK_DIV_BY_8', -} -UCLK_DIV_BY_1 = 0 -UCLK_DIV_BY_2 = 1 -UCLK_DIV_BY_4 = 2 -UCLK_DIV_BY_8 = 3 -c__EA_UCLK_DIV_e = ctypes.c_uint32 # enum -UCLK_DIV_e = c__EA_UCLK_DIV_e -UCLK_DIV_e__enumvalues = c__EA_UCLK_DIV_e__enumvalues - -# values for enumeration 'c__EA_GpioIntPolarity_e' -c__EA_GpioIntPolarity_e__enumvalues = { - 0: 'GPIO_INT_POLARITY_ACTIVE_LOW', - 1: 'GPIO_INT_POLARITY_ACTIVE_HIGH', -} -GPIO_INT_POLARITY_ACTIVE_LOW = 0 -GPIO_INT_POLARITY_ACTIVE_HIGH = 1 -c__EA_GpioIntPolarity_e = ctypes.c_uint32 # enum -GpioIntPolarity_e = c__EA_GpioIntPolarity_e -GpioIntPolarity_e__enumvalues = c__EA_GpioIntPolarity_e__enumvalues - -# values for enumeration 'c__EA_PwrConfig_e' -c__EA_PwrConfig_e__enumvalues = { - 0: 'PWR_CONFIG_TDP', - 1: 'PWR_CONFIG_TGP', - 2: 'PWR_CONFIG_TCP_ESTIMATED', - 3: 'PWR_CONFIG_TCP_MEASURED', -} -PWR_CONFIG_TDP = 0 -PWR_CONFIG_TGP = 1 -PWR_CONFIG_TCP_ESTIMATED = 2 -PWR_CONFIG_TCP_MEASURED = 3 -c__EA_PwrConfig_e = ctypes.c_uint32 # enum -PwrConfig_e = c__EA_PwrConfig_e -PwrConfig_e__enumvalues = c__EA_PwrConfig_e__enumvalues -class struct_c__SA_DpmDescriptor_t(Structure): - pass - -struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False -struct_c__SA_DpmDescriptor_t._fields_ = [ - ('Padding', ctypes.c_ubyte), - ('SnapToDiscrete', ctypes.c_ubyte), - ('NumDiscreteLevels', ctypes.c_ubyte), - ('CalculateFopt', ctypes.c_ubyte), - ('ConversionToAvfsClk', LinearInt_t), - ('Padding3', ctypes.c_uint32 * 3), - ('Padding4', ctypes.c_uint16), - ('FoptimalDc', ctypes.c_uint16), - ('FoptimalAc', ctypes.c_uint16), - ('Padding2', ctypes.c_uint16), -] - -DpmDescriptor_t = struct_c__SA_DpmDescriptor_t - -# values for enumeration 'c__EA_PPT_THROTTLER_e' -c__EA_PPT_THROTTLER_e__enumvalues = { - 0: 'PPT_THROTTLER_PPT0', - 1: 'PPT_THROTTLER_PPT1', - 2: 'PPT_THROTTLER_PPT2', - 3: 'PPT_THROTTLER_PPT3', - 4: 'PPT_THROTTLER_COUNT', -} -PPT_THROTTLER_PPT0 = 0 -PPT_THROTTLER_PPT1 = 1 -PPT_THROTTLER_PPT2 = 2 -PPT_THROTTLER_PPT3 = 3 -PPT_THROTTLER_COUNT = 4 -c__EA_PPT_THROTTLER_e = ctypes.c_uint32 # enum -PPT_THROTTLER_e = c__EA_PPT_THROTTLER_e -PPT_THROTTLER_e__enumvalues = c__EA_PPT_THROTTLER_e__enumvalues - -# values for enumeration 'c__EA_TEMP_e' -c__EA_TEMP_e__enumvalues = { - 0: 'TEMP_EDGE', - 1: 'TEMP_HOTSPOT', - 2: 'TEMP_HOTSPOT_G', - 3: 'TEMP_HOTSPOT_M', - 4: 'TEMP_MEM', - 5: 'TEMP_VR_GFX', - 6: 'TEMP_VR_MEM0', - 7: 'TEMP_VR_MEM1', - 8: 'TEMP_VR_SOC', - 9: 'TEMP_VR_U', - 10: 'TEMP_LIQUID0', - 11: 'TEMP_LIQUID1', - 12: 'TEMP_PLX', - 13: 'TEMP_COUNT', -} -TEMP_EDGE = 0 -TEMP_HOTSPOT = 1 -TEMP_HOTSPOT_G = 2 -TEMP_HOTSPOT_M = 3 -TEMP_MEM = 4 -TEMP_VR_GFX = 5 -TEMP_VR_MEM0 = 6 -TEMP_VR_MEM1 = 7 -TEMP_VR_SOC = 8 -TEMP_VR_U = 9 -TEMP_LIQUID0 = 10 -TEMP_LIQUID1 = 11 -TEMP_PLX = 12 -TEMP_COUNT = 13 -c__EA_TEMP_e = ctypes.c_uint32 # enum -TEMP_e = c__EA_TEMP_e -TEMP_e__enumvalues = c__EA_TEMP_e__enumvalues - -# values for enumeration 'c__EA_TDC_THROTTLER_e' -c__EA_TDC_THROTTLER_e__enumvalues = { - 0: 'TDC_THROTTLER_GFX', - 1: 'TDC_THROTTLER_SOC', - 2: 'TDC_THROTTLER_U', - 3: 'TDC_THROTTLER_COUNT', -} -TDC_THROTTLER_GFX = 0 -TDC_THROTTLER_SOC = 1 -TDC_THROTTLER_U = 2 -TDC_THROTTLER_COUNT = 3 -c__EA_TDC_THROTTLER_e = ctypes.c_uint32 # enum -TDC_THROTTLER_e = c__EA_TDC_THROTTLER_e -TDC_THROTTLER_e__enumvalues = c__EA_TDC_THROTTLER_e__enumvalues - -# values for enumeration 'c__EA_SVI_PLANE_e' -c__EA_SVI_PLANE_e__enumvalues = { - 0: 'SVI_PLANE_GFX', - 1: 'SVI_PLANE_SOC', - 2: 'SVI_PLANE_VMEMP', - 3: 'SVI_PLANE_VDDIO_MEM', - 4: 'SVI_PLANE_U', - 5: 'SVI_PLANE_COUNT', -} -SVI_PLANE_GFX = 0 -SVI_PLANE_SOC = 1 -SVI_PLANE_VMEMP = 2 -SVI_PLANE_VDDIO_MEM = 3 -SVI_PLANE_U = 4 -SVI_PLANE_COUNT = 5 -c__EA_SVI_PLANE_e = ctypes.c_uint32 # enum -SVI_PLANE_e = c__EA_SVI_PLANE_e -SVI_PLANE_e__enumvalues = c__EA_SVI_PLANE_e__enumvalues - -# values for enumeration 'c__EA_PMFW_VOLT_PLANE_e' -c__EA_PMFW_VOLT_PLANE_e__enumvalues = { - 0: 'PMFW_VOLT_PLANE_GFX', - 1: 'PMFW_VOLT_PLANE_SOC', - 2: 'PMFW_VOLT_PLANE_COUNT', -} -PMFW_VOLT_PLANE_GFX = 0 -PMFW_VOLT_PLANE_SOC = 1 -PMFW_VOLT_PLANE_COUNT = 2 -c__EA_PMFW_VOLT_PLANE_e = ctypes.c_uint32 # enum -PMFW_VOLT_PLANE_e = c__EA_PMFW_VOLT_PLANE_e -PMFW_VOLT_PLANE_e__enumvalues = c__EA_PMFW_VOLT_PLANE_e__enumvalues - -# values for enumeration 'c__EA_CUSTOMER_VARIANT_e' -c__EA_CUSTOMER_VARIANT_e__enumvalues = { - 0: 'CUSTOMER_VARIANT_ROW', - 1: 'CUSTOMER_VARIANT_FALCON', - 2: 'CUSTOMER_VARIANT_COUNT', -} -CUSTOMER_VARIANT_ROW = 0 -CUSTOMER_VARIANT_FALCON = 1 -CUSTOMER_VARIANT_COUNT = 2 -c__EA_CUSTOMER_VARIANT_e = ctypes.c_uint32 # enum -CUSTOMER_VARIANT_e = c__EA_CUSTOMER_VARIANT_e -CUSTOMER_VARIANT_e__enumvalues = c__EA_CUSTOMER_VARIANT_e__enumvalues - -# values for enumeration 'c__EA_POWER_SOURCE_e' -c__EA_POWER_SOURCE_e__enumvalues = { - 0: 'POWER_SOURCE_AC', - 1: 'POWER_SOURCE_DC', - 2: 'POWER_SOURCE_COUNT', -} -POWER_SOURCE_AC = 0 -POWER_SOURCE_DC = 1 -POWER_SOURCE_COUNT = 2 -c__EA_POWER_SOURCE_e = ctypes.c_uint32 # enum -POWER_SOURCE_e = c__EA_POWER_SOURCE_e -POWER_SOURCE_e__enumvalues = c__EA_POWER_SOURCE_e__enumvalues - -# values for enumeration 'c__EA_MEM_VENDOR_e' -c__EA_MEM_VENDOR_e__enumvalues = { - 0: 'MEM_VENDOR_PLACEHOLDER0', - 1: 'MEM_VENDOR_SAMSUNG', - 2: 'MEM_VENDOR_INFINEON', - 3: 'MEM_VENDOR_ELPIDA', - 4: 'MEM_VENDOR_ETRON', - 5: 'MEM_VENDOR_NANYA', - 6: 'MEM_VENDOR_HYNIX', - 7: 'MEM_VENDOR_MOSEL', - 8: 'MEM_VENDOR_WINBOND', - 9: 'MEM_VENDOR_ESMT', - 10: 'MEM_VENDOR_PLACEHOLDER1', - 11: 'MEM_VENDOR_PLACEHOLDER2', - 12: 'MEM_VENDOR_PLACEHOLDER3', - 13: 'MEM_VENDOR_PLACEHOLDER4', - 14: 'MEM_VENDOR_PLACEHOLDER5', - 15: 'MEM_VENDOR_MICRON', - 16: 'MEM_VENDOR_COUNT', -} -MEM_VENDOR_PLACEHOLDER0 = 0 -MEM_VENDOR_SAMSUNG = 1 -MEM_VENDOR_INFINEON = 2 -MEM_VENDOR_ELPIDA = 3 -MEM_VENDOR_ETRON = 4 -MEM_VENDOR_NANYA = 5 -MEM_VENDOR_HYNIX = 6 -MEM_VENDOR_MOSEL = 7 -MEM_VENDOR_WINBOND = 8 -MEM_VENDOR_ESMT = 9 -MEM_VENDOR_PLACEHOLDER1 = 10 -MEM_VENDOR_PLACEHOLDER2 = 11 -MEM_VENDOR_PLACEHOLDER3 = 12 -MEM_VENDOR_PLACEHOLDER4 = 13 -MEM_VENDOR_PLACEHOLDER5 = 14 -MEM_VENDOR_MICRON = 15 -MEM_VENDOR_COUNT = 16 -c__EA_MEM_VENDOR_e = ctypes.c_uint32 # enum -MEM_VENDOR_e = c__EA_MEM_VENDOR_e -MEM_VENDOR_e__enumvalues = c__EA_MEM_VENDOR_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_HW_FUSE_e' -c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', - 1: 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 2: 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', - 3: 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 4: 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', - 5: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 6: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 7: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 8: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 9: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 10: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 11: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 12: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 13: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 14: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', - 15: 'PP_GRTAVFS_HW_ZONE0_VF', - 16: 'PP_GRTAVFS_HW_ZONE1_VF1', - 17: 'PP_GRTAVFS_HW_ZONE2_VF2', - 18: 'PP_GRTAVFS_HW_ZONE3_VF3', - 19: 'PP_GRTAVFS_HW_VOLTAGE_GB', - 20: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 21: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 22: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 23: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 24: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 25: 'PP_GRTAVFS_HW_RESERVED_0', - 26: 'PP_GRTAVFS_HW_RESERVED_1', - 27: 'PP_GRTAVFS_HW_RESERVED_2', - 28: 'PP_GRTAVFS_HW_RESERVED_3', - 29: 'PP_GRTAVFS_HW_RESERVED_4', - 30: 'PP_GRTAVFS_HW_RESERVED_5', - 31: 'PP_GRTAVFS_HW_RESERVED_6', - 32: 'PP_GRTAVFS_HW_FUSE_COUNT', -} -PP_GRTAVFS_HW_CPO_CTL_ZONE0 = 0 -PP_GRTAVFS_HW_CPO_CTL_ZONE1 = 1 -PP_GRTAVFS_HW_CPO_CTL_ZONE2 = 2 -PP_GRTAVFS_HW_CPO_CTL_ZONE3 = 3 -PP_GRTAVFS_HW_CPO_CTL_ZONE4 = 4 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = 5 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = 6 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = 7 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = 8 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = 9 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = 10 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = 11 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = 12 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = 13 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = 14 -PP_GRTAVFS_HW_ZONE0_VF = 15 -PP_GRTAVFS_HW_ZONE1_VF1 = 16 -PP_GRTAVFS_HW_ZONE2_VF2 = 17 -PP_GRTAVFS_HW_ZONE3_VF3 = 18 -PP_GRTAVFS_HW_VOLTAGE_GB = 19 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = 20 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = 21 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = 22 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = 23 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = 24 -PP_GRTAVFS_HW_RESERVED_0 = 25 -PP_GRTAVFS_HW_RESERVED_1 = 26 -PP_GRTAVFS_HW_RESERVED_2 = 27 -PP_GRTAVFS_HW_RESERVED_3 = 28 -PP_GRTAVFS_HW_RESERVED_4 = 29 -PP_GRTAVFS_HW_RESERVED_5 = 30 -PP_GRTAVFS_HW_RESERVED_6 = 31 -PP_GRTAVFS_HW_FUSE_COUNT = 32 -c__EA_PP_GRTAVFS_HW_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_HW_FUSE_e = c__EA_PP_GRTAVFS_HW_FUSE_e -PP_GRTAVFS_HW_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e' -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 1: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 2: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 3: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 4: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 5: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 6: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 7: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 8: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 9: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 10: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 11: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 12: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', - 13: 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', -} -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = 0 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = 1 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = 2 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = 3 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = 4 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = 5 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = 6 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = 7 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = 8 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = 9 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = 10 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = 11 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = 12 -PP_GRTAVFS_FW_COMMON_FUSE_COUNT = 13 -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_COMMON_FUSE_e = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e -PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e' -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 1: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 2: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 3: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 4: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 5: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 6: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 7: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 8: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 9: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 10: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 11: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 12: 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 13: 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 14: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 15: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 16: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 17: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 18: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 19: 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', -} -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = 0 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = 1 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = 2 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = 3 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = 4 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = 5 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = 6 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = 7 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = 8 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = 9 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = 10 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = 11 -PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = 12 -PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = 13 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = 14 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = 15 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = 16 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = 17 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = 18 -PP_GRTAVFS_FW_SEP_FUSE_COUNT = 19 -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_SEP_FUSE_e = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e -PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues -class struct_c__SA_SviTelemetryScale_t(Structure): - pass - -struct_c__SA_SviTelemetryScale_t._pack_ = 1 # source:False -struct_c__SA_SviTelemetryScale_t._fields_ = [ - ('Offset', ctypes.c_byte), - ('Padding', ctypes.c_ubyte), - ('MaxCurrent', ctypes.c_uint16), -] - -SviTelemetryScale_t = struct_c__SA_SviTelemetryScale_t - -# values for enumeration 'c__EA_FanMode_e' -c__EA_FanMode_e__enumvalues = { - 0: 'FAN_MODE_AUTO', - 1: 'FAN_MODE_MANUAL_LINEAR', -} -FAN_MODE_AUTO = 0 -FAN_MODE_MANUAL_LINEAR = 1 -c__EA_FanMode_e = ctypes.c_uint32 # enum -FanMode_e = c__EA_FanMode_e -FanMode_e__enumvalues = c__EA_FanMode_e__enumvalues -class struct_c__SA_OverDriveTable_t(Structure): - pass - -struct_c__SA_OverDriveTable_t._pack_ = 1 # source:False -struct_c__SA_OverDriveTable_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), - ('Reserved', ctypes.c_uint32), - ('GfxclkFmin', ctypes.c_int16), - ('GfxclkFmax', ctypes.c_int16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte * 6), - ('FanLinearTempPoints', ctypes.c_ubyte * 6), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanZeroRpmStopTemp', ctypes.c_ubyte), - ('FanMode', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('Spare', ctypes.c_uint32 * 13), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -OverDriveTable_t = struct_c__SA_OverDriveTable_t -class struct_c__SA_OverDriveTableExternal_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('OverDriveTable', OverDriveTable_t), - ] - -OverDriveTableExternal_t = struct_c__SA_OverDriveTableExternal_t -class struct_c__SA_OverDriveLimits_t(Structure): - pass - -struct_c__SA_OverDriveLimits_t._pack_ = 1 # source:False -struct_c__SA_OverDriveLimits_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16), - ('Reserved1', ctypes.c_uint16), - ('Reserved2', ctypes.c_uint16), - ('GfxclkFmin', ctypes.c_int16), - ('GfxclkFmax', ctypes.c_int16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte), - ('FanLinearTempPoints', ctypes.c_ubyte), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanZeroRpmStopTemp', ctypes.c_ubyte), - ('FanMode', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('Spare', ctypes.c_uint32 * 13), -] - -OverDriveLimits_t = struct_c__SA_OverDriveLimits_t - -# values for enumeration 'c__EA_BOARD_GPIO_TYPE_e' -c__EA_BOARD_GPIO_TYPE_e__enumvalues = { - 0: 'BOARD_GPIO_SMUIO_0', - 1: 'BOARD_GPIO_SMUIO_1', - 2: 'BOARD_GPIO_SMUIO_2', - 3: 'BOARD_GPIO_SMUIO_3', - 4: 'BOARD_GPIO_SMUIO_4', - 5: 'BOARD_GPIO_SMUIO_5', - 6: 'BOARD_GPIO_SMUIO_6', - 7: 'BOARD_GPIO_SMUIO_7', - 8: 'BOARD_GPIO_SMUIO_8', - 9: 'BOARD_GPIO_SMUIO_9', - 10: 'BOARD_GPIO_SMUIO_10', - 11: 'BOARD_GPIO_SMUIO_11', - 12: 'BOARD_GPIO_SMUIO_12', - 13: 'BOARD_GPIO_SMUIO_13', - 14: 'BOARD_GPIO_SMUIO_14', - 15: 'BOARD_GPIO_SMUIO_15', - 16: 'BOARD_GPIO_SMUIO_16', - 17: 'BOARD_GPIO_SMUIO_17', - 18: 'BOARD_GPIO_SMUIO_18', - 19: 'BOARD_GPIO_SMUIO_19', - 20: 'BOARD_GPIO_SMUIO_20', - 21: 'BOARD_GPIO_SMUIO_21', - 22: 'BOARD_GPIO_SMUIO_22', - 23: 'BOARD_GPIO_SMUIO_23', - 24: 'BOARD_GPIO_SMUIO_24', - 25: 'BOARD_GPIO_SMUIO_25', - 26: 'BOARD_GPIO_SMUIO_26', - 27: 'BOARD_GPIO_SMUIO_27', - 28: 'BOARD_GPIO_SMUIO_28', - 29: 'BOARD_GPIO_SMUIO_29', - 30: 'BOARD_GPIO_SMUIO_30', - 31: 'BOARD_GPIO_SMUIO_31', - 32: 'MAX_BOARD_GPIO_SMUIO_NUM', - 33: 'BOARD_GPIO_DC_GEN_A', - 34: 'BOARD_GPIO_DC_GEN_B', - 35: 'BOARD_GPIO_DC_GEN_C', - 36: 'BOARD_GPIO_DC_GEN_D', - 37: 'BOARD_GPIO_DC_GEN_E', - 38: 'BOARD_GPIO_DC_GEN_F', - 39: 'BOARD_GPIO_DC_GEN_G', - 40: 'BOARD_GPIO_DC_GENLK_CLK', - 41: 'BOARD_GPIO_DC_GENLK_VSYNC', - 42: 'BOARD_GPIO_DC_SWAPLOCK_A', - 43: 'BOARD_GPIO_DC_SWAPLOCK_B', -} -BOARD_GPIO_SMUIO_0 = 0 -BOARD_GPIO_SMUIO_1 = 1 -BOARD_GPIO_SMUIO_2 = 2 -BOARD_GPIO_SMUIO_3 = 3 -BOARD_GPIO_SMUIO_4 = 4 -BOARD_GPIO_SMUIO_5 = 5 -BOARD_GPIO_SMUIO_6 = 6 -BOARD_GPIO_SMUIO_7 = 7 -BOARD_GPIO_SMUIO_8 = 8 -BOARD_GPIO_SMUIO_9 = 9 -BOARD_GPIO_SMUIO_10 = 10 -BOARD_GPIO_SMUIO_11 = 11 -BOARD_GPIO_SMUIO_12 = 12 -BOARD_GPIO_SMUIO_13 = 13 -BOARD_GPIO_SMUIO_14 = 14 -BOARD_GPIO_SMUIO_15 = 15 -BOARD_GPIO_SMUIO_16 = 16 -BOARD_GPIO_SMUIO_17 = 17 -BOARD_GPIO_SMUIO_18 = 18 -BOARD_GPIO_SMUIO_19 = 19 -BOARD_GPIO_SMUIO_20 = 20 -BOARD_GPIO_SMUIO_21 = 21 -BOARD_GPIO_SMUIO_22 = 22 -BOARD_GPIO_SMUIO_23 = 23 -BOARD_GPIO_SMUIO_24 = 24 -BOARD_GPIO_SMUIO_25 = 25 -BOARD_GPIO_SMUIO_26 = 26 -BOARD_GPIO_SMUIO_27 = 27 -BOARD_GPIO_SMUIO_28 = 28 -BOARD_GPIO_SMUIO_29 = 29 -BOARD_GPIO_SMUIO_30 = 30 -BOARD_GPIO_SMUIO_31 = 31 -MAX_BOARD_GPIO_SMUIO_NUM = 32 -BOARD_GPIO_DC_GEN_A = 33 -BOARD_GPIO_DC_GEN_B = 34 -BOARD_GPIO_DC_GEN_C = 35 -BOARD_GPIO_DC_GEN_D = 36 -BOARD_GPIO_DC_GEN_E = 37 -BOARD_GPIO_DC_GEN_F = 38 -BOARD_GPIO_DC_GEN_G = 39 -BOARD_GPIO_DC_GENLK_CLK = 40 -BOARD_GPIO_DC_GENLK_VSYNC = 41 -BOARD_GPIO_DC_SWAPLOCK_A = 42 -BOARD_GPIO_DC_SWAPLOCK_B = 43 -c__EA_BOARD_GPIO_TYPE_e = ctypes.c_uint32 # enum -BOARD_GPIO_TYPE_e = c__EA_BOARD_GPIO_TYPE_e -BOARD_GPIO_TYPE_e__enumvalues = c__EA_BOARD_GPIO_TYPE_e__enumvalues -class struct_c__SA_BootValues_t(Structure): - pass - -struct_c__SA_BootValues_t._pack_ = 1 # source:False -struct_c__SA_BootValues_t._fields_ = [ - ('InitGfxclk_bypass', ctypes.c_uint16), - ('InitSocclk', ctypes.c_uint16), - ('InitMp0clk', ctypes.c_uint16), - ('InitMpioclk', ctypes.c_uint16), - ('InitSmnclk', ctypes.c_uint16), - ('InitUcpclk', ctypes.c_uint16), - ('InitCsrclk', ctypes.c_uint16), - ('InitDprefclk', ctypes.c_uint16), - ('InitDcfclk', ctypes.c_uint16), - ('InitDtbclk', ctypes.c_uint16), - ('InitDclk', ctypes.c_uint16), - ('InitVclk', ctypes.c_uint16), - ('InitUsbdfsclk', ctypes.c_uint16), - ('InitMp1clk', ctypes.c_uint16), - ('InitLclk', ctypes.c_uint16), - ('InitBaco400clk_bypass', ctypes.c_uint16), - ('InitBaco1200clk_bypass', ctypes.c_uint16), - ('InitBaco700clk_bypass', ctypes.c_uint16), - ('InitFclk', ctypes.c_uint16), - ('InitGfxclk_clkb', ctypes.c_uint16), - ('InitUclkDPMState', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('InitVcoFreqPll0', ctypes.c_uint32), - ('InitVcoFreqPll1', ctypes.c_uint32), - ('InitVcoFreqPll2', ctypes.c_uint32), - ('InitVcoFreqPll3', ctypes.c_uint32), - ('InitVcoFreqPll4', ctypes.c_uint32), - ('InitVcoFreqPll5', ctypes.c_uint32), - ('InitVcoFreqPll6', ctypes.c_uint32), - ('InitGfx', ctypes.c_uint16), - ('InitSoc', ctypes.c_uint16), - ('InitU', ctypes.c_uint16), - ('Padding2', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 8), -] - -BootValues_t = struct_c__SA_BootValues_t -class struct_c__SA_MsgLimits_t(Structure): - pass - -struct_c__SA_MsgLimits_t._pack_ = 1 # source:False -struct_c__SA_MsgLimits_t._fields_ = [ - ('Power', ctypes.c_uint16 * 2 * 4), - ('Tdc', ctypes.c_uint16 * 3), - ('Temperature', ctypes.c_uint16 * 13), - ('PwmLimitMin', ctypes.c_ubyte), - ('PwmLimitMax', ctypes.c_ubyte), - ('FanTargetTemperature', ctypes.c_ubyte), - ('Spare1', ctypes.c_ubyte * 1), - ('AcousticTargetRpmThresholdMin', ctypes.c_uint16), - ('AcousticTargetRpmThresholdMax', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMin', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMax', ctypes.c_uint16), - ('PccLimitMin', ctypes.c_uint16), - ('PccLimitMax', ctypes.c_uint16), - ('FanStopTempMin', ctypes.c_uint16), - ('FanStopTempMax', ctypes.c_uint16), - ('FanStartTempMin', ctypes.c_uint16), - ('FanStartTempMax', ctypes.c_uint16), - ('PowerMinPpt0', ctypes.c_uint16 * 2), - ('Spare', ctypes.c_uint32 * 11), -] - -MsgLimits_t = struct_c__SA_MsgLimits_t -class struct_c__SA_DriverReportedClocks_t(Structure): - pass - -struct_c__SA_DriverReportedClocks_t._pack_ = 1 # source:False -struct_c__SA_DriverReportedClocks_t._fields_ = [ - ('BaseClockAc', ctypes.c_uint16), - ('GameClockAc', ctypes.c_uint16), - ('BoostClockAc', ctypes.c_uint16), - ('BaseClockDc', ctypes.c_uint16), - ('GameClockDc', ctypes.c_uint16), - ('BoostClockDc', ctypes.c_uint16), - ('Reserved', ctypes.c_uint32 * 4), -] - -DriverReportedClocks_t = struct_c__SA_DriverReportedClocks_t -class struct_c__SA_AvfsDcBtcParams_t(Structure): - pass - -struct_c__SA_AvfsDcBtcParams_t._pack_ = 1 # source:False -struct_c__SA_AvfsDcBtcParams_t._fields_ = [ - ('DcBtcEnabled', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('DcTol', ctypes.c_uint16), - ('DcBtcGb', ctypes.c_uint16), - ('DcBtcMin', ctypes.c_uint16), - ('DcBtcMax', ctypes.c_uint16), - ('DcBtcGbScalar', LinearInt_t), -] - -AvfsDcBtcParams_t = struct_c__SA_AvfsDcBtcParams_t -class struct_c__SA_AvfsFuseOverride_t(Structure): - pass - -struct_c__SA_AvfsFuseOverride_t._pack_ = 1 # source:False -struct_c__SA_AvfsFuseOverride_t._fields_ = [ - ('AvfsTemp', ctypes.c_uint16 * 2), - ('VftFMin', ctypes.c_uint16), - ('VInversion', ctypes.c_uint16), - ('qVft', struct_c__SA_QuadraticInt_t * 2), - ('qAvfsGb', QuadraticInt_t), - ('qAvfsGb2', QuadraticInt_t), -] - -AvfsFuseOverride_t = struct_c__SA_AvfsFuseOverride_t -class struct_c__SA_SkuTable_t(Structure): - pass - -struct_c__SA_SkuTable_t._pack_ = 1 # source:False -struct_c__SA_SkuTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('FeaturesToRun', ctypes.c_uint32 * 2), - ('TotalPowerConfig', ctypes.c_ubyte), - ('CustomerVariant', ctypes.c_ubyte), - ('MemoryTemperatureTypeMask', ctypes.c_ubyte), - ('SmartShiftVersion', ctypes.c_ubyte), - ('SocketPowerLimitAc', ctypes.c_uint16 * 4), - ('SocketPowerLimitDc', ctypes.c_uint16 * 4), - ('SocketPowerLimitSmartShift2', ctypes.c_uint16), - ('EnableLegacyPptLimit', ctypes.c_ubyte), - ('UseInputTelemetry', ctypes.c_ubyte), - ('SmartShiftMinReportedPptinDcs', ctypes.c_ubyte), - ('PaddingPpt', ctypes.c_ubyte * 1), - ('VrTdcLimit', ctypes.c_uint16 * 3), - ('PlatformTdcLimit', ctypes.c_uint16 * 3), - ('TemperatureLimit', ctypes.c_uint16 * 13), - ('HwCtfTempLimit', ctypes.c_uint16), - ('PaddingInfra', ctypes.c_uint16), - ('FitControllerFailureRateLimit', ctypes.c_uint32), - ('FitControllerGfxDutyCycle', ctypes.c_uint32), - ('FitControllerSocDutyCycle', ctypes.c_uint32), - ('FitControllerSocOffset', ctypes.c_uint32), - ('GfxApccPlusResidencyLimit', ctypes.c_uint32), - ('ThrottlerControlMask', ctypes.c_uint32), - ('FwDStateMask', ctypes.c_uint32), - ('UlvVoltageOffset', ctypes.c_uint16 * 2), - ('UlvVoltageOffsetU', ctypes.c_uint16), - ('DeepUlvVoltageOffsetSoc', ctypes.c_uint16), - ('DefaultMaxVoltage', ctypes.c_uint16 * 2), - ('BoostMaxVoltage', ctypes.c_uint16 * 2), - ('VminTempHystersis', ctypes.c_int16 * 2), - ('VminTempThreshold', ctypes.c_int16 * 2), - ('Vmin_Hot_T0', ctypes.c_uint16 * 2), - ('Vmin_Cold_T0', ctypes.c_uint16 * 2), - ('Vmin_Hot_Eol', ctypes.c_uint16 * 2), - ('Vmin_Cold_Eol', ctypes.c_uint16 * 2), - ('Vmin_Aging_Offset', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Hot', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Cold', ctypes.c_uint16 * 2), - ('VcBtcFixedVminAgingOffset', ctypes.c_uint16 * 2), - ('VcBtcVmin2PsmDegrationGb', ctypes.c_uint16 * 2), - ('VcBtcPsmA', ctypes.c_uint32 * 2), - ('VcBtcPsmB', ctypes.c_uint32 * 2), - ('VcBtcVminA', ctypes.c_uint32 * 2), - ('VcBtcVminB', ctypes.c_uint32 * 2), - ('PerPartVminEnabled', ctypes.c_ubyte * 2), - ('VcBtcEnabled', ctypes.c_ubyte * 2), - ('SocketPowerLimitAcTau', ctypes.c_uint16 * 4), - ('SocketPowerLimitDcTau', ctypes.c_uint16 * 4), - ('Vmin_droop', QuadraticInt_t), - ('SpareVmin', ctypes.c_uint32 * 9), - ('DpmDescriptor', struct_c__SA_DpmDescriptor_t * 13), - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 4), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint32 * 13), - ('Mp0clkFreq', ctypes.c_uint16 * 2), - ('Mp0DpmVoltage', ctypes.c_uint16 * 2), - ('GfxclkSpare', ctypes.c_ubyte * 2), - ('GfxclkFreqCap', ctypes.c_uint16), - ('GfxclkFgfxoffEntry', ctypes.c_uint16), - ('GfxclkFgfxoffExitImu', ctypes.c_uint16), - ('GfxclkFgfxoffExitRlc', ctypes.c_uint16), - ('GfxclkThrottleClock', ctypes.c_uint16), - ('EnableGfxPowerStagesGpio', ctypes.c_ubyte), - ('GfxIdlePadding', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivEn', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivVal', ctypes.c_ubyte), - ('GfxOffEntryEarlyMGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayVal', ctypes.c_ubyte), - ('GfxclkFreqGfxUlv', ctypes.c_uint16), - ('GfxIdlePadding2', ctypes.c_ubyte * 2), - ('GfxOffEntryHysteresis', ctypes.c_uint32), - ('GfxoffSpare', ctypes.c_uint32 * 15), - ('DfllBtcMasterScalerM', ctypes.c_uint32), - ('DfllBtcMasterScalerB', ctypes.c_int32), - ('DfllBtcSlaveScalerM', ctypes.c_uint32), - ('DfllBtcSlaveScalerB', ctypes.c_int32), - ('DfllPccAsWaitCtrl', ctypes.c_uint32), - ('DfllPccAsStepCtrl', ctypes.c_uint32), - ('DfllL2FrequencyBoostM', ctypes.c_uint32), - ('DfllL2FrequencyBoostB', ctypes.c_uint32), - ('GfxGpoSpare', ctypes.c_uint32 * 8), - ('DcsGfxOffVoltage', ctypes.c_uint16), - ('PaddingDcs', ctypes.c_uint16), - ('DcsMinGfxOffTime', ctypes.c_uint16), - ('DcsMaxGfxOffTime', ctypes.c_uint16), - ('DcsMinCreditAccum', ctypes.c_uint32), - ('DcsExitHysteresis', ctypes.c_uint16), - ('DcsTimeout', ctypes.c_uint16), - ('FoptEnabled', ctypes.c_ubyte), - ('DcsSpare2', ctypes.c_ubyte * 3), - ('DcsFoptM', ctypes.c_uint32), - ('DcsFoptB', ctypes.c_uint32), - ('DcsSpare', ctypes.c_uint32 * 11), - ('ShadowFreqTableUclk', ctypes.c_uint16 * 4), - ('UseStrobeModeOptimizations', ctypes.c_ubyte), - ('PaddingMem', ctypes.c_ubyte * 3), - ('UclkDpmPstates', ctypes.c_ubyte * 4), - ('FreqTableUclkDiv', ctypes.c_ubyte * 4), - ('MemVmempVoltage', ctypes.c_uint16 * 4), - ('MemVddioVoltage', ctypes.c_uint16 * 4), - ('FclkDpmUPstates', ctypes.c_ubyte * 8), - ('FclkDpmVddU', ctypes.c_uint16 * 8), - ('FclkDpmUSpeed', ctypes.c_uint16 * 8), - ('FclkDpmDisallowPstateFreq', ctypes.c_uint16), - ('PaddingFclk', ctypes.c_uint16), - ('PcieGenSpeed', ctypes.c_ubyte * 3), - ('PcieLaneCount', ctypes.c_ubyte * 3), - ('LclkFreq', ctypes.c_uint16 * 3), - ('FanStopTemp', ctypes.c_uint16 * 13), - ('FanStartTemp', ctypes.c_uint16 * 13), - ('FanGain', ctypes.c_uint16 * 13), - ('FanGainPadding', ctypes.c_uint16), - ('FanPwmMin', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanMaximumRpm', ctypes.c_uint16), - ('MGpuAcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetGfxclk', ctypes.c_uint16), - ('TempInputSelectMask', ctypes.c_uint32), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanTachEdgePerRev', ctypes.c_ubyte), - ('FanTargetTemperature', ctypes.c_uint16 * 13), - ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), - ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), - ('FuzzyFan_PwmSetDelta', ctypes.c_int16), - ('FuzzyFan_Reserved', ctypes.c_uint16), - ('FwCtfLimit', ctypes.c_uint16 * 13), - ('IntakeTempEnableRPM', ctypes.c_uint16), - ('IntakeTempOffsetTemp', ctypes.c_int16), - ('IntakeTempReleaseTemp', ctypes.c_uint16), - ('IntakeTempHighIntakeAcousticLimit', ctypes.c_uint16), - ('IntakeTempAcouticLimitReleaseRate', ctypes.c_uint16), - ('FanAbnormalTempLimitOffset', ctypes.c_int16), - ('FanStalledTriggerRpm', ctypes.c_uint16), - ('FanAbnormalTriggerRpmCoeff', ctypes.c_uint16), - ('FanAbnormalDetectionEnable', ctypes.c_uint16), - ('FanIntakeSensorSupport', ctypes.c_ubyte), - ('FanIntakePadding', ctypes.c_ubyte * 3), - ('FanSpare', ctypes.c_uint32 * 13), - ('OverrideGfxAvfsFuses', ctypes.c_ubyte), - ('GfxAvfsPadding', ctypes.c_ubyte * 3), - ('L2HwRtAvfsFuses', ctypes.c_uint32 * 32), - ('SeHwRtAvfsFuses', ctypes.c_uint32 * 32), - ('CommonRtAvfs', ctypes.c_uint32 * 13), - ('L2FwRtAvfsFuses', ctypes.c_uint32 * 19), - ('SeFwRtAvfsFuses', ctypes.c_uint32 * 19), - ('Droop_PWL_F', ctypes.c_uint32 * 5), - ('Droop_PWL_a', ctypes.c_uint32 * 5), - ('Droop_PWL_b', ctypes.c_uint32 * 5), - ('Droop_PWL_c', ctypes.c_uint32 * 5), - ('Static_PWL_Offset', ctypes.c_uint32 * 5), - ('dGbV_dT_vmin', ctypes.c_uint32), - ('dGbV_dT_vmax', ctypes.c_uint32), - ('V2F_vmin_range_low', ctypes.c_uint32), - ('V2F_vmin_range_high', ctypes.c_uint32), - ('V2F_vmax_range_low', ctypes.c_uint32), - ('V2F_vmax_range_high', ctypes.c_uint32), - ('DcBtcGfxParams', AvfsDcBtcParams_t), - ('GfxAvfsSpare', ctypes.c_uint32 * 32), - ('OverrideSocAvfsFuses', ctypes.c_ubyte), - ('MinSocAvfsRevision', ctypes.c_ubyte), - ('SocAvfsPadding', ctypes.c_ubyte * 2), - ('SocAvfsFuseOverride', struct_c__SA_AvfsFuseOverride_t * 3), - ('dBtcGbSoc', struct_c__SA_DroopInt_t * 3), - ('qAgingGb', struct_c__SA_LinearInt_t * 3), - ('qStaticVoltageOffset', struct_c__SA_QuadraticInt_t * 3), - ('DcBtcSocParams', struct_c__SA_AvfsDcBtcParams_t * 3), - ('SocAvfsSpare', ctypes.c_uint32 * 32), - ('BootValues', BootValues_t), - ('DriverReportedClocks', DriverReportedClocks_t), - ('MsgLimits', MsgLimits_t), - ('OverDriveLimitsMin', OverDriveLimits_t), - ('OverDriveLimitsBasicMax', OverDriveLimits_t), - ('reserved', ctypes.c_uint32 * 22), - ('DebugOverrides', ctypes.c_uint32), - ('TotalBoardPowerSupport', ctypes.c_ubyte), - ('TotalBoardPowerPadding', ctypes.c_ubyte * 3), - ('TotalIdleBoardPowerM', ctypes.c_int16), - ('TotalIdleBoardPowerB', ctypes.c_int16), - ('TotalBoardPowerM', ctypes.c_int16), - ('TotalBoardPowerB', ctypes.c_int16), - ('qFeffCoeffGameClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBaseClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBoostClock', struct_c__SA_QuadraticInt_t * 2), - ('TemperatureLimit_Hynix', ctypes.c_uint16), - ('TemperatureLimit_Micron', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Hynix', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Micron', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 41), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SkuTable_t = struct_c__SA_SkuTable_t -class struct_c__SA_BoardTable_t(Structure): - pass - -struct_c__SA_BoardTable_t._pack_ = 1 # source:False -struct_c__SA_BoardTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('I2cControllers', struct_c__SA_I2cControllerConfig_t * 8), - ('VddGfxVrMapping', ctypes.c_ubyte), - ('VddSocVrMapping', ctypes.c_ubyte), - ('VddMem0VrMapping', ctypes.c_ubyte), - ('VddMem1VrMapping', ctypes.c_ubyte), - ('GfxUlvPhaseSheddingMask', ctypes.c_ubyte), - ('SocUlvPhaseSheddingMask', ctypes.c_ubyte), - ('VmempUlvPhaseSheddingMask', ctypes.c_ubyte), - ('VddioUlvPhaseSheddingMask', ctypes.c_ubyte), - ('SlaveAddrMapping', ctypes.c_ubyte * 5), - ('VrPsiSupport', ctypes.c_ubyte * 5), - ('PaddingPsi', ctypes.c_ubyte * 5), - ('EnablePsi6', ctypes.c_ubyte * 5), - ('SviTelemetryScale', struct_c__SA_SviTelemetryScale_t * 5), - ('VoltageTelemetryRatio', ctypes.c_uint32 * 5), - ('DownSlewRateVr', ctypes.c_ubyte * 5), - ('LedOffGpio', ctypes.c_ubyte), - ('FanOffGpio', ctypes.c_ubyte), - ('GfxVrPowerStageOffGpio', ctypes.c_ubyte), - ('AcDcGpio', ctypes.c_ubyte), - ('AcDcPolarity', ctypes.c_ubyte), - ('VR0HotGpio', ctypes.c_ubyte), - ('VR0HotPolarity', ctypes.c_ubyte), - ('GthrGpio', ctypes.c_ubyte), - ('GthrPolarity', ctypes.c_ubyte), - ('LedPin0', ctypes.c_ubyte), - ('LedPin1', ctypes.c_ubyte), - ('LedPin2', ctypes.c_ubyte), - ('LedEnableMask', ctypes.c_ubyte), - ('LedPcie', ctypes.c_ubyte), - ('LedError', ctypes.c_ubyte), - ('UclkTrainingModeSpreadPercent', ctypes.c_ubyte), - ('UclkSpreadPadding', ctypes.c_ubyte), - ('UclkSpreadFreq', ctypes.c_uint16), - ('UclkSpreadPercent', ctypes.c_ubyte * 16), - ('GfxclkSpreadEnable', ctypes.c_ubyte), - ('FclkSpreadPercent', ctypes.c_ubyte), - ('FclkSpreadFreq', ctypes.c_uint16), - ('DramWidth', ctypes.c_ubyte), - ('PaddingMem1', ctypes.c_ubyte * 7), - ('HsrEnabled', ctypes.c_ubyte), - ('VddqOffEnabled', ctypes.c_ubyte), - ('PaddingUmcFlags', ctypes.c_ubyte * 2), - ('PostVoltageSetBacoDelay', ctypes.c_uint32), - ('BacoEntryDelay', ctypes.c_uint32), - ('FuseWritePowerMuxPresent', ctypes.c_ubyte), - ('FuseWritePadding', ctypes.c_ubyte * 3), - ('BoardSpare', ctypes.c_uint32 * 63), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -BoardTable_t = struct_c__SA_BoardTable_t -class struct_c__SA_PPTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('SkuTable', SkuTable_t), - ('BoardTable', BoardTable_t), - ] - -PPTable_t = struct_c__SA_PPTable_t -class struct_c__SA_DriverSmuConfig_t(Structure): - pass - -struct_c__SA_DriverSmuConfig_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfig_t._fields_ = [ - ('GfxclkAverageLpfTau', ctypes.c_uint16), - ('FclkAverageLpfTau', ctypes.c_uint16), - ('UclkAverageLpfTau', ctypes.c_uint16), - ('GfxActivityLpfTau', ctypes.c_uint16), - ('UclkActivityLpfTau', ctypes.c_uint16), - ('SocketPowerLpfTau', ctypes.c_uint16), - ('VcnClkAverageLpfTau', ctypes.c_uint16), - ('VcnUsageAverageLpfTau', ctypes.c_uint16), -] - -DriverSmuConfig_t = struct_c__SA_DriverSmuConfig_t -class struct_c__SA_DriverSmuConfigExternal_t(Structure): - pass - -struct_c__SA_DriverSmuConfigExternal_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfigExternal_t._fields_ = [ - ('DriverSmuConfig', DriverSmuConfig_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DriverSmuConfigExternal_t = struct_c__SA_DriverSmuConfigExternal_t -class struct_c__SA_DriverInfoTable_t(Structure): - pass - -struct_c__SA_DriverInfoTable_t._pack_ = 1 # source:False -struct_c__SA_DriverInfoTable_t._fields_ = [ - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 4), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint16 * 13), - ('Padding', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 32), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DriverInfoTable_t = struct_c__SA_DriverInfoTable_t -class struct_c__SA_SmuMetrics_t(Structure): - pass - -struct_c__SA_SmuMetrics_t._pack_ = 1 # source:False -struct_c__SA_SmuMetrics_t._fields_ = [ - ('CurrClock', ctypes.c_uint32 * 13), - ('AverageGfxclkFrequencyTarget', ctypes.c_uint16), - ('AverageGfxclkFrequencyPreDs', ctypes.c_uint16), - ('AverageGfxclkFrequencyPostDs', ctypes.c_uint16), - ('AverageFclkFrequencyPreDs', ctypes.c_uint16), - ('AverageFclkFrequencyPostDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPreDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPostDs', ctypes.c_uint16), - ('AverageVclk0Frequency', ctypes.c_uint16), - ('AverageDclk0Frequency', ctypes.c_uint16), - ('AverageVclk1Frequency', ctypes.c_uint16), - ('AverageDclk1Frequency', ctypes.c_uint16), - ('PCIeBusy', ctypes.c_uint16), - ('dGPU_W_MAX', ctypes.c_uint16), - ('padding', ctypes.c_uint16), - ('MetricsCounter', ctypes.c_uint32), - ('AvgVoltage', ctypes.c_uint16 * 5), - ('AvgCurrent', ctypes.c_uint16 * 5), - ('AverageGfxActivity', ctypes.c_uint16), - ('AverageUclkActivity', ctypes.c_uint16), - ('Vcn0ActivityPercentage', ctypes.c_uint16), - ('Vcn1ActivityPercentage', ctypes.c_uint16), - ('EnergyAccumulator', ctypes.c_uint32), - ('AverageSocketPower', ctypes.c_uint16), - ('AverageTotalBoardPower', ctypes.c_uint16), - ('AvgTemperature', ctypes.c_uint16 * 13), - ('AvgTemperatureFanIntake', ctypes.c_uint16), - ('PcieRate', ctypes.c_ubyte), - ('PcieWidth', ctypes.c_ubyte), - ('AvgFanPwm', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 1), - ('AvgFanRpm', ctypes.c_uint16), - ('ThrottlingPercentage', ctypes.c_ubyte * 22), - ('VmaxThrottlingPercentage', ctypes.c_ubyte), - ('Padding1', ctypes.c_ubyte * 3), - ('D3HotEntryCountPerMode', ctypes.c_uint32 * 4), - ('D3HotExitCountPerMode', ctypes.c_uint32 * 4), - ('ArmMsgReceivedCountPerMode', ctypes.c_uint32 * 4), - ('ApuSTAPMSmartShiftLimit', ctypes.c_uint16), - ('ApuSTAPMLimit', ctypes.c_uint16), - ('AvgApuSocketPower', ctypes.c_uint16), - ('AverageUclkActivity_MAX', ctypes.c_uint16), - ('PublicSerialNumberLower', ctypes.c_uint32), - ('PublicSerialNumberUpper', ctypes.c_uint32), -] - -SmuMetrics_t = struct_c__SA_SmuMetrics_t -class struct_c__SA_SmuMetricsExternal_t(Structure): - pass - -struct_c__SA_SmuMetricsExternal_t._pack_ = 1 # source:False -struct_c__SA_SmuMetricsExternal_t._fields_ = [ - ('SmuMetrics', SmuMetrics_t), - ('Spare', ctypes.c_uint32 * 29), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -SmuMetricsExternal_t = struct_c__SA_SmuMetricsExternal_t -class struct_c__SA_WatermarkRowGeneric_t(Structure): - pass - -struct_c__SA_WatermarkRowGeneric_t._pack_ = 1 # source:False -struct_c__SA_WatermarkRowGeneric_t._fields_ = [ - ('WmSetting', ctypes.c_ubyte), - ('Flags', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 2), -] - -WatermarkRowGeneric_t = struct_c__SA_WatermarkRowGeneric_t - -# values for enumeration 'c__EA_WATERMARKS_FLAGS_e' -c__EA_WATERMARKS_FLAGS_e__enumvalues = { - 0: 'WATERMARKS_CLOCK_RANGE', - 1: 'WATERMARKS_DUMMY_PSTATE', - 2: 'WATERMARKS_MALL', - 3: 'WATERMARKS_COUNT', -} -WATERMARKS_CLOCK_RANGE = 0 -WATERMARKS_DUMMY_PSTATE = 1 -WATERMARKS_MALL = 2 -WATERMARKS_COUNT = 3 -c__EA_WATERMARKS_FLAGS_e = ctypes.c_uint32 # enum -WATERMARKS_FLAGS_e = c__EA_WATERMARKS_FLAGS_e -WATERMARKS_FLAGS_e__enumvalues = c__EA_WATERMARKS_FLAGS_e__enumvalues -class struct_c__SA_Watermarks_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('WatermarkRow', struct_c__SA_WatermarkRowGeneric_t * 4), - ] - -Watermarks_t = struct_c__SA_Watermarks_t -class struct_c__SA_WatermarksExternal_t(Structure): - pass - -struct_c__SA_WatermarksExternal_t._pack_ = 1 # source:False -struct_c__SA_WatermarksExternal_t._fields_ = [ - ('Watermarks', Watermarks_t), - ('Spare', ctypes.c_uint32 * 16), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -WatermarksExternal_t = struct_c__SA_WatermarksExternal_t -class struct_c__SA_AvfsDebugTable_t(Structure): - pass - -struct_c__SA_AvfsDebugTable_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTable_t._fields_ = [ - ('avgPsmCount', ctypes.c_uint16 * 214), - ('minPsmCount', ctypes.c_uint16 * 214), - ('avgPsmVoltage', ctypes.c_float * 214), - ('minPsmVoltage', ctypes.c_float * 214), -] - -AvfsDebugTable_t = struct_c__SA_AvfsDebugTable_t -class struct_c__SA_AvfsDebugTableExternal_t(Structure): - pass - -struct_c__SA_AvfsDebugTableExternal_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTableExternal_t._fields_ = [ - ('AvfsDebugTable', AvfsDebugTable_t), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -AvfsDebugTableExternal_t = struct_c__SA_AvfsDebugTableExternal_t -class struct_c__SA_DpmActivityMonitorCoeffInt_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffInt_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffInt_t._fields_ = [ - ('Gfx_ActiveHystLimit', ctypes.c_ubyte), - ('Gfx_IdleHystLimit', ctypes.c_ubyte), - ('Gfx_FPS', ctypes.c_ubyte), - ('Gfx_MinActiveFreqType', ctypes.c_ubyte), - ('Gfx_BoosterFreqType', ctypes.c_ubyte), - ('PaddingGfx', ctypes.c_ubyte), - ('Gfx_MinActiveFreq', ctypes.c_uint16), - ('Gfx_BoosterFreq', ctypes.c_uint16), - ('Gfx_PD_Data_time_constant', ctypes.c_uint16), - ('Gfx_PD_Data_limit_a', ctypes.c_uint32), - ('Gfx_PD_Data_limit_b', ctypes.c_uint32), - ('Gfx_PD_Data_limit_c', ctypes.c_uint32), - ('Gfx_PD_Data_error_coeff', ctypes.c_uint32), - ('Gfx_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Fclk_ActiveHystLimit', ctypes.c_ubyte), - ('Fclk_IdleHystLimit', ctypes.c_ubyte), - ('Fclk_FPS', ctypes.c_ubyte), - ('Fclk_MinActiveFreqType', ctypes.c_ubyte), - ('Fclk_BoosterFreqType', ctypes.c_ubyte), - ('PaddingFclk', ctypes.c_ubyte), - ('Fclk_MinActiveFreq', ctypes.c_uint16), - ('Fclk_BoosterFreq', ctypes.c_uint16), - ('Fclk_PD_Data_time_constant', ctypes.c_uint16), - ('Fclk_PD_Data_limit_a', ctypes.c_uint32), - ('Fclk_PD_Data_limit_b', ctypes.c_uint32), - ('Fclk_PD_Data_limit_c', ctypes.c_uint32), - ('Fclk_PD_Data_error_coeff', ctypes.c_uint32), - ('Fclk_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Mem_UpThreshold_Limit', ctypes.c_uint32 * 4), - ('Mem_UpHystLimit', ctypes.c_ubyte * 4), - ('Mem_DownHystLimit', ctypes.c_ubyte * 4), - ('Mem_Fps', ctypes.c_uint16), - ('padding', ctypes.c_ubyte * 2), -] - -DpmActivityMonitorCoeffInt_t = struct_c__SA_DpmActivityMonitorCoeffInt_t -class struct_c__SA_DpmActivityMonitorCoeffIntExternal_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._fields_ = [ - ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), - ('MmHubPadding', ctypes.c_uint32 * 8), -] - -DpmActivityMonitorCoeffIntExternal_t = struct_c__SA_DpmActivityMonitorCoeffIntExternal_t -__AMDGPU_SMU_H__ = True # macro -u32 = True # macro -SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 # macro -SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 # macro -SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 # macro -SMU_FW_NAME_LEN = 0x24 # macro -SMU_DPM_USER_PROFILE_RESTORE = (1<<0) # macro -SMU_CUSTOM_FAN_SPEED_RPM = (1<<1) # macro -SMU_CUSTOM_FAN_SPEED_PWM = (1<<2) # macro -SMU_THROTTLER_PPT0_BIT = 0 # macro -SMU_THROTTLER_PPT1_BIT = 1 # macro -SMU_THROTTLER_PPT2_BIT = 2 # macro -SMU_THROTTLER_PPT3_BIT = 3 # macro -SMU_THROTTLER_SPL_BIT = 4 # macro -SMU_THROTTLER_FPPT_BIT = 5 # macro -SMU_THROTTLER_SPPT_BIT = 6 # macro -SMU_THROTTLER_SPPT_APU_BIT = 7 # macro -SMU_THROTTLER_TDC_GFX_BIT = 16 # macro -SMU_THROTTLER_TDC_SOC_BIT = 17 # macro -SMU_THROTTLER_TDC_MEM_BIT = 18 # macro -SMU_THROTTLER_TDC_VDD_BIT = 19 # macro -SMU_THROTTLER_TDC_CVIP_BIT = 20 # macro -SMU_THROTTLER_EDC_CPU_BIT = 21 # macro -SMU_THROTTLER_EDC_GFX_BIT = 22 # macro -SMU_THROTTLER_APCC_BIT = 23 # macro -SMU_THROTTLER_TEMP_GPU_BIT = 32 # macro -SMU_THROTTLER_TEMP_CORE_BIT = 33 # macro -SMU_THROTTLER_TEMP_MEM_BIT = 34 # macro -SMU_THROTTLER_TEMP_EDGE_BIT = 35 # macro -SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 # macro -SMU_THROTTLER_TEMP_SOC_BIT = 37 # macro -SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 # macro -SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 # macro -SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 # macro -SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 # macro -SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 # macro -SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 # macro -SMU_THROTTLER_VRHOT0_BIT = 44 # macro -SMU_THROTTLER_VRHOT1_BIT = 45 # macro -SMU_THROTTLER_PROCHOT_CPU_BIT = 46 # macro -SMU_THROTTLER_PROCHOT_GFX_BIT = 47 # macro -SMU_THROTTLER_PPM_BIT = 56 # macro -SMU_THROTTLER_FIT_BIT = 57 # macro -# def SMU_TABLE_INIT(tables, table_id, s, a, d): # macro -# return {tables[table_id].size=s;tables[table_id].align=a;tables[table_id].domain=d;}(0) -class struct_smu_hw_power_state(Structure): - pass - -struct_smu_hw_power_state._pack_ = 1 # source:False +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +FEATURE_PWR_DOMAIN_e = CEnum(ctypes.c_uint32) +FEATURE_PWR_ALL = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_ALL', 0) +FEATURE_PWR_S5 = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_S5', 1) +FEATURE_PWR_BACO = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_BACO', 2) +FEATURE_PWR_SOC = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_SOC', 3) +FEATURE_PWR_GFX = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_GFX', 4) +FEATURE_PWR_DOMAIN_COUNT = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_DOMAIN_COUNT', 5) + +SVI_PSI_e = CEnum(ctypes.c_uint32) +SVI_PSI_0 = SVI_PSI_e.define('SVI_PSI_0', 0) +SVI_PSI_1 = SVI_PSI_e.define('SVI_PSI_1', 1) +SVI_PSI_2 = SVI_PSI_e.define('SVI_PSI_2', 2) +SVI_PSI_3 = SVI_PSI_e.define('SVI_PSI_3', 3) +SVI_PSI_4 = SVI_PSI_e.define('SVI_PSI_4', 4) +SVI_PSI_5 = SVI_PSI_e.define('SVI_PSI_5', 5) +SVI_PSI_6 = SVI_PSI_e.define('SVI_PSI_6', 6) +SVI_PSI_7 = SVI_PSI_e.define('SVI_PSI_7', 7) + +SMARTSHIFT_VERSION_e = CEnum(ctypes.c_uint32) +SMARTSHIFT_VERSION_1 = SMARTSHIFT_VERSION_e.define('SMARTSHIFT_VERSION_1', 0) +SMARTSHIFT_VERSION_2 = SMARTSHIFT_VERSION_e.define('SMARTSHIFT_VERSION_2', 1) +SMARTSHIFT_VERSION_3 = SMARTSHIFT_VERSION_e.define('SMARTSHIFT_VERSION_3', 2) + +FOPT_CALC_e = CEnum(ctypes.c_uint32) +FOPT_CALC_AC_CALC_DC = FOPT_CALC_e.define('FOPT_CALC_AC_CALC_DC', 0) +FOPT_PPTABLE_AC_CALC_DC = FOPT_CALC_e.define('FOPT_PPTABLE_AC_CALC_DC', 1) +FOPT_CALC_AC_PPTABLE_DC = FOPT_CALC_e.define('FOPT_CALC_AC_PPTABLE_DC', 2) +FOPT_PPTABLE_AC_PPTABLE_DC = FOPT_CALC_e.define('FOPT_PPTABLE_AC_PPTABLE_DC', 3) + +DRAM_BIT_WIDTH_TYPE_e = CEnum(ctypes.c_uint32) +DRAM_BIT_WIDTH_DISABLED = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_DISABLED', 0) +DRAM_BIT_WIDTH_X_8 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_8', 8) +DRAM_BIT_WIDTH_X_16 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_16', 16) +DRAM_BIT_WIDTH_X_32 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_32', 32) +DRAM_BIT_WIDTH_X_64 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_64', 64) +DRAM_BIT_WIDTH_X_128 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_128', 128) +DRAM_BIT_WIDTH_COUNT = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_COUNT', 129) + +I2cControllerPort_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_PORT_0 = I2cControllerPort_e.define('I2C_CONTROLLER_PORT_0', 0) +I2C_CONTROLLER_PORT_1 = I2cControllerPort_e.define('I2C_CONTROLLER_PORT_1', 1) +I2C_CONTROLLER_PORT_COUNT = I2cControllerPort_e.define('I2C_CONTROLLER_PORT_COUNT', 2) + +I2cControllerName_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_NAME_VR_GFX = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_GFX', 0) +I2C_CONTROLLER_NAME_VR_SOC = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_SOC', 1) +I2C_CONTROLLER_NAME_VR_VMEMP = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_VMEMP', 2) +I2C_CONTROLLER_NAME_VR_VDDIO = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_VDDIO', 3) +I2C_CONTROLLER_NAME_LIQUID0 = I2cControllerName_e.define('I2C_CONTROLLER_NAME_LIQUID0', 4) +I2C_CONTROLLER_NAME_LIQUID1 = I2cControllerName_e.define('I2C_CONTROLLER_NAME_LIQUID1', 5) +I2C_CONTROLLER_NAME_PLX = I2cControllerName_e.define('I2C_CONTROLLER_NAME_PLX', 6) +I2C_CONTROLLER_NAME_FAN_INTAKE = I2cControllerName_e.define('I2C_CONTROLLER_NAME_FAN_INTAKE', 7) +I2C_CONTROLLER_NAME_COUNT = I2cControllerName_e.define('I2C_CONTROLLER_NAME_COUNT', 8) + +I2cControllerThrottler_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_THROTTLER_TYPE_NONE = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_TYPE_NONE', 0) +I2C_CONTROLLER_THROTTLER_VR_GFX = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_GFX', 1) +I2C_CONTROLLER_THROTTLER_VR_SOC = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_SOC', 2) +I2C_CONTROLLER_THROTTLER_VR_VMEMP = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_VMEMP', 3) +I2C_CONTROLLER_THROTTLER_VR_VDDIO = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_VDDIO', 4) +I2C_CONTROLLER_THROTTLER_LIQUID0 = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_LIQUID0', 5) +I2C_CONTROLLER_THROTTLER_LIQUID1 = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_LIQUID1', 6) +I2C_CONTROLLER_THROTTLER_PLX = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_PLX', 7) +I2C_CONTROLLER_THROTTLER_FAN_INTAKE = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_FAN_INTAKE', 8) +I2C_CONTROLLER_THROTTLER_INA3221 = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_INA3221', 9) +I2C_CONTROLLER_THROTTLER_COUNT = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_COUNT', 10) + +I2cControllerProtocol_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', 0) +I2C_CONTROLLER_PROTOCOL_VR_IR35217 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_VR_IR35217', 1) +I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', 2) +I2C_CONTROLLER_PROTOCOL_INA3221 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_INA3221', 3) +I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', 4) +I2C_CONTROLLER_PROTOCOL_COUNT = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_COUNT', 5) + +class _anonstruct0(Struct): pass +I2cControllerConfig_t = _anonstruct0 +I2cPort_e = CEnum(ctypes.c_uint32) +I2C_PORT_SVD_SCL = I2cPort_e.define('I2C_PORT_SVD_SCL', 0) +I2C_PORT_GPIO = I2cPort_e.define('I2C_PORT_GPIO', 1) + +I2cSpeed_e = CEnum(ctypes.c_uint32) +I2C_SPEED_FAST_50K = I2cSpeed_e.define('I2C_SPEED_FAST_50K', 0) +I2C_SPEED_FAST_100K = I2cSpeed_e.define('I2C_SPEED_FAST_100K', 1) +I2C_SPEED_FAST_400K = I2cSpeed_e.define('I2C_SPEED_FAST_400K', 2) +I2C_SPEED_FAST_PLUS_1M = I2cSpeed_e.define('I2C_SPEED_FAST_PLUS_1M', 3) +I2C_SPEED_HIGH_1M = I2cSpeed_e.define('I2C_SPEED_HIGH_1M', 4) +I2C_SPEED_HIGH_2M = I2cSpeed_e.define('I2C_SPEED_HIGH_2M', 5) +I2C_SPEED_COUNT = I2cSpeed_e.define('I2C_SPEED_COUNT', 6) + +I2cCmdType_e = CEnum(ctypes.c_uint32) +I2C_CMD_READ = I2cCmdType_e.define('I2C_CMD_READ', 0) +I2C_CMD_WRITE = I2cCmdType_e.define('I2C_CMD_WRITE', 1) +I2C_CMD_COUNT = I2cCmdType_e.define('I2C_CMD_COUNT', 2) + +class _anonstruct1(Struct): pass +SwI2cCmd_t = _anonstruct1 +class _anonstruct2(Struct): pass +SwI2cRequest_t = _anonstruct2 +class _anonstruct3(Struct): pass +SwI2cRequestExternal_t = _anonstruct3 +class _anonstruct4(Struct): pass +EccInfo_t = _anonstruct4 +class _anonstruct5(Struct): pass +EccInfoTable_t = _anonstruct5 +D3HOTSequence_e = CEnum(ctypes.c_uint32) +BACO_SEQUENCE = D3HOTSequence_e.define('BACO_SEQUENCE', 0) +MSR_SEQUENCE = D3HOTSequence_e.define('MSR_SEQUENCE', 1) +BAMACO_SEQUENCE = D3HOTSequence_e.define('BAMACO_SEQUENCE', 2) +ULPS_SEQUENCE = D3HOTSequence_e.define('ULPS_SEQUENCE', 3) +D3HOT_SEQUENCE_COUNT = D3HOTSequence_e.define('D3HOT_SEQUENCE_COUNT', 4) + +PowerGatingMode_e = CEnum(ctypes.c_uint32) +PG_DYNAMIC_MODE = PowerGatingMode_e.define('PG_DYNAMIC_MODE', 0) +PG_STATIC_MODE = PowerGatingMode_e.define('PG_STATIC_MODE', 1) + +PowerGatingSettings_e = CEnum(ctypes.c_uint32) +PG_POWER_DOWN = PowerGatingSettings_e.define('PG_POWER_DOWN', 0) +PG_POWER_UP = PowerGatingSettings_e.define('PG_POWER_UP', 1) + +class _anonstruct6(Struct): pass +QuadraticInt_t = _anonstruct6 +class _anonstruct7(Struct): pass +LinearInt_t = _anonstruct7 +class _anonstruct8(Struct): pass +DroopInt_t = _anonstruct8 +DCS_ARCH_e = CEnum(ctypes.c_uint32) +DCS_ARCH_DISABLED = DCS_ARCH_e.define('DCS_ARCH_DISABLED', 0) +DCS_ARCH_FADCS = DCS_ARCH_e.define('DCS_ARCH_FADCS', 1) +DCS_ARCH_ASYNC = DCS_ARCH_e.define('DCS_ARCH_ASYNC', 2) + +PPCLK_e = CEnum(ctypes.c_uint32) +PPCLK_GFXCLK = PPCLK_e.define('PPCLK_GFXCLK', 0) +PPCLK_SOCCLK = PPCLK_e.define('PPCLK_SOCCLK', 1) +PPCLK_UCLK = PPCLK_e.define('PPCLK_UCLK', 2) +PPCLK_FCLK = PPCLK_e.define('PPCLK_FCLK', 3) +PPCLK_DCLK_0 = PPCLK_e.define('PPCLK_DCLK_0', 4) +PPCLK_VCLK_0 = PPCLK_e.define('PPCLK_VCLK_0', 5) +PPCLK_DCLK_1 = PPCLK_e.define('PPCLK_DCLK_1', 6) +PPCLK_VCLK_1 = PPCLK_e.define('PPCLK_VCLK_1', 7) +PPCLK_DISPCLK = PPCLK_e.define('PPCLK_DISPCLK', 8) +PPCLK_DPPCLK = PPCLK_e.define('PPCLK_DPPCLK', 9) +PPCLK_DPREFCLK = PPCLK_e.define('PPCLK_DPREFCLK', 10) +PPCLK_DCFCLK = PPCLK_e.define('PPCLK_DCFCLK', 11) +PPCLK_DTBCLK = PPCLK_e.define('PPCLK_DTBCLK', 12) +PPCLK_COUNT = PPCLK_e.define('PPCLK_COUNT', 13) + +VOLTAGE_MODE_e = CEnum(ctypes.c_uint32) +VOLTAGE_MODE_PPTABLE = VOLTAGE_MODE_e.define('VOLTAGE_MODE_PPTABLE', 0) +VOLTAGE_MODE_FUSES = VOLTAGE_MODE_e.define('VOLTAGE_MODE_FUSES', 1) +VOLTAGE_MODE_COUNT = VOLTAGE_MODE_e.define('VOLTAGE_MODE_COUNT', 2) + +AVFS_VOLTAGE_TYPE_e = CEnum(ctypes.c_uint32) +AVFS_VOLTAGE_GFX = AVFS_VOLTAGE_TYPE_e.define('AVFS_VOLTAGE_GFX', 0) +AVFS_VOLTAGE_SOC = AVFS_VOLTAGE_TYPE_e.define('AVFS_VOLTAGE_SOC', 1) +AVFS_VOLTAGE_COUNT = AVFS_VOLTAGE_TYPE_e.define('AVFS_VOLTAGE_COUNT', 2) + +AVFS_TEMP_e = CEnum(ctypes.c_uint32) +AVFS_TEMP_COLD = AVFS_TEMP_e.define('AVFS_TEMP_COLD', 0) +AVFS_TEMP_HOT = AVFS_TEMP_e.define('AVFS_TEMP_HOT', 1) +AVFS_TEMP_COUNT = AVFS_TEMP_e.define('AVFS_TEMP_COUNT', 2) + +AVFS_D_e = CEnum(ctypes.c_uint32) +AVFS_D_G = AVFS_D_e.define('AVFS_D_G', 0) +AVFS_D_M_B = AVFS_D_e.define('AVFS_D_M_B', 1) +AVFS_D_M_S = AVFS_D_e.define('AVFS_D_M_S', 2) +AVFS_D_COUNT = AVFS_D_e.define('AVFS_D_COUNT', 3) + +UCLK_DIV_e = CEnum(ctypes.c_uint32) +UCLK_DIV_BY_1 = UCLK_DIV_e.define('UCLK_DIV_BY_1', 0) +UCLK_DIV_BY_2 = UCLK_DIV_e.define('UCLK_DIV_BY_2', 1) +UCLK_DIV_BY_4 = UCLK_DIV_e.define('UCLK_DIV_BY_4', 2) +UCLK_DIV_BY_8 = UCLK_DIV_e.define('UCLK_DIV_BY_8', 3) + +GpioIntPolarity_e = CEnum(ctypes.c_uint32) +GPIO_INT_POLARITY_ACTIVE_LOW = GpioIntPolarity_e.define('GPIO_INT_POLARITY_ACTIVE_LOW', 0) +GPIO_INT_POLARITY_ACTIVE_HIGH = GpioIntPolarity_e.define('GPIO_INT_POLARITY_ACTIVE_HIGH', 1) + +PwrConfig_e = CEnum(ctypes.c_uint32) +PWR_CONFIG_TDP = PwrConfig_e.define('PWR_CONFIG_TDP', 0) +PWR_CONFIG_TGP = PwrConfig_e.define('PWR_CONFIG_TGP', 1) +PWR_CONFIG_TCP_ESTIMATED = PwrConfig_e.define('PWR_CONFIG_TCP_ESTIMATED', 2) +PWR_CONFIG_TCP_MEASURED = PwrConfig_e.define('PWR_CONFIG_TCP_MEASURED', 3) + +class _anonstruct9(Struct): pass +DpmDescriptor_t = _anonstruct9 +PPT_THROTTLER_e = CEnum(ctypes.c_uint32) +PPT_THROTTLER_PPT0 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT0', 0) +PPT_THROTTLER_PPT1 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT1', 1) +PPT_THROTTLER_PPT2 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT2', 2) +PPT_THROTTLER_PPT3 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT3', 3) +PPT_THROTTLER_COUNT = PPT_THROTTLER_e.define('PPT_THROTTLER_COUNT', 4) + +TEMP_e = CEnum(ctypes.c_uint32) +TEMP_EDGE = TEMP_e.define('TEMP_EDGE', 0) +TEMP_HOTSPOT = TEMP_e.define('TEMP_HOTSPOT', 1) +TEMP_HOTSPOT_G = TEMP_e.define('TEMP_HOTSPOT_G', 2) +TEMP_HOTSPOT_M = TEMP_e.define('TEMP_HOTSPOT_M', 3) +TEMP_MEM = TEMP_e.define('TEMP_MEM', 4) +TEMP_VR_GFX = TEMP_e.define('TEMP_VR_GFX', 5) +TEMP_VR_MEM0 = TEMP_e.define('TEMP_VR_MEM0', 6) +TEMP_VR_MEM1 = TEMP_e.define('TEMP_VR_MEM1', 7) +TEMP_VR_SOC = TEMP_e.define('TEMP_VR_SOC', 8) +TEMP_VR_U = TEMP_e.define('TEMP_VR_U', 9) +TEMP_LIQUID0 = TEMP_e.define('TEMP_LIQUID0', 10) +TEMP_LIQUID1 = TEMP_e.define('TEMP_LIQUID1', 11) +TEMP_PLX = TEMP_e.define('TEMP_PLX', 12) +TEMP_COUNT = TEMP_e.define('TEMP_COUNT', 13) + +TDC_THROTTLER_e = CEnum(ctypes.c_uint32) +TDC_THROTTLER_GFX = TDC_THROTTLER_e.define('TDC_THROTTLER_GFX', 0) +TDC_THROTTLER_SOC = TDC_THROTTLER_e.define('TDC_THROTTLER_SOC', 1) +TDC_THROTTLER_U = TDC_THROTTLER_e.define('TDC_THROTTLER_U', 2) +TDC_THROTTLER_COUNT = TDC_THROTTLER_e.define('TDC_THROTTLER_COUNT', 3) + +SVI_PLANE_e = CEnum(ctypes.c_uint32) +SVI_PLANE_GFX = SVI_PLANE_e.define('SVI_PLANE_GFX', 0) +SVI_PLANE_SOC = SVI_PLANE_e.define('SVI_PLANE_SOC', 1) +SVI_PLANE_VMEMP = SVI_PLANE_e.define('SVI_PLANE_VMEMP', 2) +SVI_PLANE_VDDIO_MEM = SVI_PLANE_e.define('SVI_PLANE_VDDIO_MEM', 3) +SVI_PLANE_U = SVI_PLANE_e.define('SVI_PLANE_U', 4) +SVI_PLANE_COUNT = SVI_PLANE_e.define('SVI_PLANE_COUNT', 5) + +PMFW_VOLT_PLANE_e = CEnum(ctypes.c_uint32) +PMFW_VOLT_PLANE_GFX = PMFW_VOLT_PLANE_e.define('PMFW_VOLT_PLANE_GFX', 0) +PMFW_VOLT_PLANE_SOC = PMFW_VOLT_PLANE_e.define('PMFW_VOLT_PLANE_SOC', 1) +PMFW_VOLT_PLANE_COUNT = PMFW_VOLT_PLANE_e.define('PMFW_VOLT_PLANE_COUNT', 2) + +CUSTOMER_VARIANT_e = CEnum(ctypes.c_uint32) +CUSTOMER_VARIANT_ROW = CUSTOMER_VARIANT_e.define('CUSTOMER_VARIANT_ROW', 0) +CUSTOMER_VARIANT_FALCON = CUSTOMER_VARIANT_e.define('CUSTOMER_VARIANT_FALCON', 1) +CUSTOMER_VARIANT_COUNT = CUSTOMER_VARIANT_e.define('CUSTOMER_VARIANT_COUNT', 2) + +POWER_SOURCE_e = CEnum(ctypes.c_uint32) +POWER_SOURCE_AC = POWER_SOURCE_e.define('POWER_SOURCE_AC', 0) +POWER_SOURCE_DC = POWER_SOURCE_e.define('POWER_SOURCE_DC', 1) +POWER_SOURCE_COUNT = POWER_SOURCE_e.define('POWER_SOURCE_COUNT', 2) + +MEM_VENDOR_e = CEnum(ctypes.c_uint32) +MEM_VENDOR_PLACEHOLDER0 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER0', 0) +MEM_VENDOR_SAMSUNG = MEM_VENDOR_e.define('MEM_VENDOR_SAMSUNG', 1) +MEM_VENDOR_INFINEON = MEM_VENDOR_e.define('MEM_VENDOR_INFINEON', 2) +MEM_VENDOR_ELPIDA = MEM_VENDOR_e.define('MEM_VENDOR_ELPIDA', 3) +MEM_VENDOR_ETRON = MEM_VENDOR_e.define('MEM_VENDOR_ETRON', 4) +MEM_VENDOR_NANYA = MEM_VENDOR_e.define('MEM_VENDOR_NANYA', 5) +MEM_VENDOR_HYNIX = MEM_VENDOR_e.define('MEM_VENDOR_HYNIX', 6) +MEM_VENDOR_MOSEL = MEM_VENDOR_e.define('MEM_VENDOR_MOSEL', 7) +MEM_VENDOR_WINBOND = MEM_VENDOR_e.define('MEM_VENDOR_WINBOND', 8) +MEM_VENDOR_ESMT = MEM_VENDOR_e.define('MEM_VENDOR_ESMT', 9) +MEM_VENDOR_PLACEHOLDER1 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER1', 10) +MEM_VENDOR_PLACEHOLDER2 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER2', 11) +MEM_VENDOR_PLACEHOLDER3 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER3', 12) +MEM_VENDOR_PLACEHOLDER4 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER4', 13) +MEM_VENDOR_PLACEHOLDER5 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER5', 14) +MEM_VENDOR_MICRON = MEM_VENDOR_e.define('MEM_VENDOR_MICRON', 15) +MEM_VENDOR_COUNT = MEM_VENDOR_e.define('MEM_VENDOR_COUNT', 16) + +PP_GRTAVFS_HW_FUSE_e = CEnum(ctypes.c_uint32) +PP_GRTAVFS_HW_CPO_CTL_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE0', 0) +PP_GRTAVFS_HW_CPO_CTL_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE1', 1) +PP_GRTAVFS_HW_CPO_CTL_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE2', 2) +PP_GRTAVFS_HW_CPO_CTL_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE3', 3) +PP_GRTAVFS_HW_CPO_CTL_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE4', 4) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', 5) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', 6) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', 7) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', 8) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', 9) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', 10) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', 11) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', 12) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', 13) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 14) +PP_GRTAVFS_HW_ZONE0_VF = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE0_VF', 15) +PP_GRTAVFS_HW_ZONE1_VF1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE1_VF1', 16) +PP_GRTAVFS_HW_ZONE2_VF2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE2_VF2', 17) +PP_GRTAVFS_HW_ZONE3_VF3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE3_VF3', 18) +PP_GRTAVFS_HW_VOLTAGE_GB = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_VOLTAGE_GB', 19) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', 20) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', 21) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', 22) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', 23) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', 24) +PP_GRTAVFS_HW_RESERVED_0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_0', 25) +PP_GRTAVFS_HW_RESERVED_1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_1', 26) +PP_GRTAVFS_HW_RESERVED_2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_2', 27) +PP_GRTAVFS_HW_RESERVED_3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_3', 28) +PP_GRTAVFS_HW_RESERVED_4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_4', 29) +PP_GRTAVFS_HW_RESERVED_5 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_5', 30) +PP_GRTAVFS_HW_RESERVED_6 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_6', 31) +PP_GRTAVFS_HW_FUSE_COUNT = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_FUSE_COUNT', 32) + +PP_GRTAVFS_FW_COMMON_FUSE_e = CEnum(ctypes.c_uint32) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', 0) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', 1) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', 2) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', 3) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', 4) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', 5) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', 6) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', 7) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', 8) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', 9) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', 10) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', 11) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 12) +PP_GRTAVFS_FW_COMMON_FUSE_COUNT = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 13) + +PP_GRTAVFS_FW_SEP_FUSE_e = CEnum(ctypes.c_uint32) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', 0) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', 1) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', 2) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', 3) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', 4) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', 5) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', 6) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', 7) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', 8) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', 9) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', 10) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', 11) +PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', 12) +PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', 13) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', 14) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', 15) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', 16) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', 17) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', 18) +PP_GRTAVFS_FW_SEP_FUSE_COUNT = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_COUNT', 19) + +class _anonstruct10(Struct): pass +SviTelemetryScale_t = _anonstruct10 +FanMode_e = CEnum(ctypes.c_uint32) +FAN_MODE_AUTO = FanMode_e.define('FAN_MODE_AUTO', 0) +FAN_MODE_MANUAL_LINEAR = FanMode_e.define('FAN_MODE_MANUAL_LINEAR', 1) + +class _anonstruct11(Struct): pass +OverDriveTable_t = _anonstruct11 +class _anonstruct12(Struct): pass +OverDriveTableExternal_t = _anonstruct12 +class _anonstruct13(Struct): pass +OverDriveLimits_t = _anonstruct13 +BOARD_GPIO_TYPE_e = CEnum(ctypes.c_uint32) +BOARD_GPIO_SMUIO_0 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_0', 0) +BOARD_GPIO_SMUIO_1 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_1', 1) +BOARD_GPIO_SMUIO_2 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_2', 2) +BOARD_GPIO_SMUIO_3 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_3', 3) +BOARD_GPIO_SMUIO_4 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_4', 4) +BOARD_GPIO_SMUIO_5 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_5', 5) +BOARD_GPIO_SMUIO_6 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_6', 6) +BOARD_GPIO_SMUIO_7 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_7', 7) +BOARD_GPIO_SMUIO_8 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_8', 8) +BOARD_GPIO_SMUIO_9 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_9', 9) +BOARD_GPIO_SMUIO_10 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_10', 10) +BOARD_GPIO_SMUIO_11 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_11', 11) +BOARD_GPIO_SMUIO_12 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_12', 12) +BOARD_GPIO_SMUIO_13 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_13', 13) +BOARD_GPIO_SMUIO_14 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_14', 14) +BOARD_GPIO_SMUIO_15 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_15', 15) +BOARD_GPIO_SMUIO_16 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_16', 16) +BOARD_GPIO_SMUIO_17 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_17', 17) +BOARD_GPIO_SMUIO_18 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_18', 18) +BOARD_GPIO_SMUIO_19 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_19', 19) +BOARD_GPIO_SMUIO_20 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_20', 20) +BOARD_GPIO_SMUIO_21 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_21', 21) +BOARD_GPIO_SMUIO_22 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_22', 22) +BOARD_GPIO_SMUIO_23 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_23', 23) +BOARD_GPIO_SMUIO_24 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_24', 24) +BOARD_GPIO_SMUIO_25 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_25', 25) +BOARD_GPIO_SMUIO_26 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_26', 26) +BOARD_GPIO_SMUIO_27 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_27', 27) +BOARD_GPIO_SMUIO_28 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_28', 28) +BOARD_GPIO_SMUIO_29 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_29', 29) +BOARD_GPIO_SMUIO_30 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_30', 30) +BOARD_GPIO_SMUIO_31 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_31', 31) +MAX_BOARD_GPIO_SMUIO_NUM = BOARD_GPIO_TYPE_e.define('MAX_BOARD_GPIO_SMUIO_NUM', 32) +BOARD_GPIO_DC_GEN_A = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_A', 33) +BOARD_GPIO_DC_GEN_B = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_B', 34) +BOARD_GPIO_DC_GEN_C = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_C', 35) +BOARD_GPIO_DC_GEN_D = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_D', 36) +BOARD_GPIO_DC_GEN_E = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_E', 37) +BOARD_GPIO_DC_GEN_F = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_F', 38) +BOARD_GPIO_DC_GEN_G = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_G', 39) +BOARD_GPIO_DC_GENLK_CLK = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GENLK_CLK', 40) +BOARD_GPIO_DC_GENLK_VSYNC = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GENLK_VSYNC', 41) +BOARD_GPIO_DC_SWAPLOCK_A = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_A', 42) +BOARD_GPIO_DC_SWAPLOCK_B = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_B', 43) + +class _anonstruct14(Struct): pass +BootValues_t = _anonstruct14 +class _anonstruct15(Struct): pass +MsgLimits_t = _anonstruct15 +class _anonstruct16(Struct): pass +DriverReportedClocks_t = _anonstruct16 +class _anonstruct17(Struct): pass +AvfsDcBtcParams_t = _anonstruct17 +class _anonstruct18(Struct): pass +AvfsFuseOverride_t = _anonstruct18 +class _anonstruct19(Struct): pass +SkuTable_t = _anonstruct19 +class _anonstruct20(Struct): pass +BoardTable_t = _anonstruct20 +class _anonstruct21(Struct): pass +PPTable_t = _anonstruct21 +class _anonstruct22(Struct): pass +DriverSmuConfig_t = _anonstruct22 +class _anonstruct23(Struct): pass +DriverSmuConfigExternal_t = _anonstruct23 +class _anonstruct24(Struct): pass +DriverInfoTable_t = _anonstruct24 +class _anonstruct25(Struct): pass +SmuMetrics_t = _anonstruct25 +class _anonstruct26(Struct): pass +SmuMetricsExternal_t = _anonstruct26 +class _anonstruct27(Struct): pass +WatermarkRowGeneric_t = _anonstruct27 +WATERMARKS_FLAGS_e = CEnum(ctypes.c_uint32) +WATERMARKS_CLOCK_RANGE = WATERMARKS_FLAGS_e.define('WATERMARKS_CLOCK_RANGE', 0) +WATERMARKS_DUMMY_PSTATE = WATERMARKS_FLAGS_e.define('WATERMARKS_DUMMY_PSTATE', 1) +WATERMARKS_MALL = WATERMARKS_FLAGS_e.define('WATERMARKS_MALL', 2) +WATERMARKS_COUNT = WATERMARKS_FLAGS_e.define('WATERMARKS_COUNT', 3) + +class _anonstruct28(Struct): pass +Watermarks_t = _anonstruct28 +class _anonstruct29(Struct): pass +WatermarksExternal_t = _anonstruct29 +class _anonstruct30(Struct): pass +AvfsDebugTable_t = _anonstruct30 +class _anonstruct31(Struct): pass +AvfsDebugTableExternal_t = _anonstruct31 +class _anonstruct32(Struct): pass +DpmActivityMonitorCoeffInt_t = _anonstruct32 +class _anonstruct33(Struct): pass +DpmActivityMonitorCoeffIntExternal_t = _anonstruct33 +class struct_smu_hw_power_state(Struct): pass struct_smu_hw_power_state._fields_ = [ - ('magic', ctypes.c_uint32), + ('magic', ctypes.c_uint32), ] +class struct_smu_power_state(Struct): pass +enum_smu_state_ui_label = CEnum(ctypes.c_uint32) +SMU_STATE_UI_LABEL_NONE = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_NONE', 0) +SMU_STATE_UI_LABEL_BATTERY = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_BATTERY', 1) +SMU_STATE_UI_TABEL_MIDDLE_LOW = enum_smu_state_ui_label.define('SMU_STATE_UI_TABEL_MIDDLE_LOW', 2) +SMU_STATE_UI_LABEL_BALLANCED = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_BALLANCED', 3) +SMU_STATE_UI_LABEL_MIDDLE_HIGHT = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 4) +SMU_STATE_UI_LABEL_PERFORMANCE = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_PERFORMANCE', 5) +SMU_STATE_UI_LABEL_BACO = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_BACO', 6) -class struct_smu_power_state(Structure): - pass +enum_smu_state_classification_flag = CEnum(ctypes.c_uint32) +SMU_STATE_CLASSIFICATION_FLAG_BOOT = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_BOOT', 1) +SMU_STATE_CLASSIFICATION_FLAG_THERMAL = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_THERMAL', 2) +SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', 4) +SMU_STATE_CLASSIFICATION_FLAG_RESET = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_RESET', 8) +SMU_STATE_CLASSIFICATION_FLAG_FORCED = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_FORCED', 16) +SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', 32) +SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', 64) +SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', 128) +SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', 256) +SMU_STATE_CLASSIFICATION_FLAG_UVD = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD', 512) +SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', 1024) +SMU_STATE_CLASSIFICATION_FLAG_ACPI = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_ACPI', 2048) +SMU_STATE_CLASSIFICATION_FLAG_HD2 = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_HD2', 4096) +SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', 8192) +SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 16384) +SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', 32768) +SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', 65536) +SMU_STATE_CLASSIFICATION_FLAG_BACO = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_BACO', 131072) +SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', 262144) +SMU_STATE_CLASSIFICATION_FLAG_ULV = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_ULV', 524288) +SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', 1048576) - -# values for enumeration 'smu_state_ui_label' -smu_state_ui_label__enumvalues = { - 0: 'SMU_STATE_UI_LABEL_NONE', - 1: 'SMU_STATE_UI_LABEL_BATTERY', - 2: 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 3: 'SMU_STATE_UI_LABEL_BALLANCED', - 4: 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', - 5: 'SMU_STATE_UI_LABEL_PERFORMANCE', - 6: 'SMU_STATE_UI_LABEL_BACO', -} -SMU_STATE_UI_LABEL_NONE = 0 -SMU_STATE_UI_LABEL_BATTERY = 1 -SMU_STATE_UI_TABEL_MIDDLE_LOW = 2 -SMU_STATE_UI_LABEL_BALLANCED = 3 -SMU_STATE_UI_LABEL_MIDDLE_HIGHT = 4 -SMU_STATE_UI_LABEL_PERFORMANCE = 5 -SMU_STATE_UI_LABEL_BACO = 6 -smu_state_ui_label = ctypes.c_uint32 # enum - -# values for enumeration 'smu_state_classification_flag' -smu_state_classification_flag__enumvalues = { - 1: 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 2: 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 4: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 8: 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 16: 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 32: 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 64: 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 128: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 256: 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 512: 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 1024: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 2048: 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 4096: 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 8192: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 16384: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', - 32768: 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 65536: 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 131072: 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 262144: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 524288: 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 1048576: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', -} -SMU_STATE_CLASSIFICATION_FLAG_BOOT = 1 -SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 2 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 4 -SMU_STATE_CLASSIFICATION_FLAG_RESET = 8 -SMU_STATE_CLASSIFICATION_FLAG_FORCED = 16 -SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 32 -SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 64 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 128 -SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 256 -SMU_STATE_CLASSIFICATION_FLAG_UVD = 512 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 1024 -SMU_STATE_CLASSIFICATION_FLAG_ACPI = 2048 -SMU_STATE_CLASSIFICATION_FLAG_HD2 = 4096 -SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 8192 -SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 16384 -SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 32768 -SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 65536 -SMU_STATE_CLASSIFICATION_FLAG_BACO = 131072 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 262144 -SMU_STATE_CLASSIFICATION_FLAG_ULV = 524288 -SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 1048576 -smu_state_classification_flag = ctypes.c_uint32 # enum -class struct_smu_state_classification_block(Structure): - pass - -struct_smu_state_classification_block._pack_ = 1 # source:False +class struct_smu_state_classification_block(Struct): pass struct_smu_state_classification_block._fields_ = [ - ('ui_label', smu_state_ui_label), - ('flags', smu_state_classification_flag), - ('bios_index', ctypes.c_int32), - ('temporary_state', ctypes.c_bool), - ('to_be_deleted', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), + ('ui_label', enum_smu_state_ui_label), + ('flags', enum_smu_state_classification_flag), + ('bios_index', ctypes.c_int32), + ('temporary_state', ctypes.c_bool), + ('to_be_deleted', ctypes.c_bool), ] - -class struct_smu_state_pcie_block(Structure): - pass - -struct_smu_state_pcie_block._pack_ = 1 # source:False +class struct_smu_state_pcie_block(Struct): pass struct_smu_state_pcie_block._fields_ = [ - ('lanes', ctypes.c_uint32), + ('lanes', ctypes.c_uint32), ] +enum_smu_refreshrate_source = CEnum(ctypes.c_uint32) +SMU_REFRESHRATE_SOURCE_EDID = enum_smu_refreshrate_source.define('SMU_REFRESHRATE_SOURCE_EDID', 0) +SMU_REFRESHRATE_SOURCE_EXPLICIT = enum_smu_refreshrate_source.define('SMU_REFRESHRATE_SOURCE_EXPLICIT', 1) - -# values for enumeration 'smu_refreshrate_source' -smu_refreshrate_source__enumvalues = { - 0: 'SMU_REFRESHRATE_SOURCE_EDID', - 1: 'SMU_REFRESHRATE_SOURCE_EXPLICIT', -} -SMU_REFRESHRATE_SOURCE_EDID = 0 -SMU_REFRESHRATE_SOURCE_EXPLICIT = 1 -smu_refreshrate_source = ctypes.c_uint32 # enum -class struct_smu_state_display_block(Structure): - pass - -struct_smu_state_display_block._pack_ = 1 # source:False +class struct_smu_state_display_block(Struct): pass struct_smu_state_display_block._fields_ = [ - ('disable_frame_modulation', ctypes.c_bool), - ('limit_refreshrate', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), - ('refreshrate_source', smu_refreshrate_source), - ('explicit_refreshrate', ctypes.c_int32), - ('edid_refreshrate_index', ctypes.c_int32), - ('enable_vari_bright', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), + ('disable_frame_modulation', ctypes.c_bool), + ('limit_refreshrate', ctypes.c_bool), + ('refreshrate_source', enum_smu_refreshrate_source), + ('explicit_refreshrate', ctypes.c_int32), + ('edid_refreshrate_index', ctypes.c_int32), + ('enable_vari_bright', ctypes.c_bool), ] - -class struct_smu_state_memory_block(Structure): - pass - -struct_smu_state_memory_block._pack_ = 1 # source:False +class struct_smu_state_memory_block(Struct): pass struct_smu_state_memory_block._fields_ = [ - ('dll_off', ctypes.c_bool), - ('m3arb', ctypes.c_ubyte), - ('unused', ctypes.c_ubyte * 3), + ('dll_off', ctypes.c_bool), + ('m3arb', ctypes.c_ubyte), + ('unused', (ctypes.c_ubyte * 3)), ] - -class struct_smu_state_software_algorithm_block(Structure): - pass - -struct_smu_state_software_algorithm_block._pack_ = 1 # source:False +class struct_smu_state_software_algorithm_block(Struct): pass struct_smu_state_software_algorithm_block._fields_ = [ - ('disable_load_balancing', ctypes.c_bool), - ('enable_sleep_for_timestamps', ctypes.c_bool), + ('disable_load_balancing', ctypes.c_bool), + ('enable_sleep_for_timestamps', ctypes.c_bool), ] - -class struct_smu_temperature_range(Structure): - pass - -struct_smu_temperature_range._pack_ = 1 # source:False +class struct_smu_temperature_range(Struct): pass struct_smu_temperature_range._fields_ = [ - ('min', ctypes.c_int32), - ('max', ctypes.c_int32), - ('edge_emergency_max', ctypes.c_int32), - ('hotspot_min', ctypes.c_int32), - ('hotspot_crit_max', ctypes.c_int32), - ('hotspot_emergency_max', ctypes.c_int32), - ('mem_min', ctypes.c_int32), - ('mem_crit_max', ctypes.c_int32), - ('mem_emergency_max', ctypes.c_int32), - ('software_shutdown_temp', ctypes.c_int32), - ('software_shutdown_temp_offset', ctypes.c_int32), + ('min', ctypes.c_int32), + ('max', ctypes.c_int32), + ('edge_emergency_max', ctypes.c_int32), + ('hotspot_min', ctypes.c_int32), + ('hotspot_crit_max', ctypes.c_int32), + ('hotspot_emergency_max', ctypes.c_int32), + ('mem_min', ctypes.c_int32), + ('mem_crit_max', ctypes.c_int32), + ('mem_emergency_max', ctypes.c_int32), + ('software_shutdown_temp', ctypes.c_int32), + ('software_shutdown_temp_offset', ctypes.c_int32), ] - -class struct_smu_state_validation_block(Structure): - pass - -struct_smu_state_validation_block._pack_ = 1 # source:False +class struct_smu_state_validation_block(Struct): pass struct_smu_state_validation_block._fields_ = [ - ('single_display_only', ctypes.c_bool), - ('disallow_on_dc', ctypes.c_bool), - ('supported_power_levels', ctypes.c_ubyte), + ('single_display_only', ctypes.c_bool), + ('disallow_on_dc', ctypes.c_bool), + ('supported_power_levels', ctypes.c_ubyte), ] - -class struct_smu_uvd_clocks(Structure): - pass - -struct_smu_uvd_clocks._pack_ = 1 # source:False +class struct_smu_uvd_clocks(Struct): pass struct_smu_uvd_clocks._fields_ = [ - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), + ('vclk', ctypes.c_uint32), + ('dclk', ctypes.c_uint32), ] +enum_smu_power_src_type = CEnum(ctypes.c_uint32) +SMU_POWER_SOURCE_AC = enum_smu_power_src_type.define('SMU_POWER_SOURCE_AC', 0) +SMU_POWER_SOURCE_DC = enum_smu_power_src_type.define('SMU_POWER_SOURCE_DC', 1) +SMU_POWER_SOURCE_COUNT = enum_smu_power_src_type.define('SMU_POWER_SOURCE_COUNT', 2) +enum_smu_ppt_limit_type = CEnum(ctypes.c_uint32) +SMU_DEFAULT_PPT_LIMIT = enum_smu_ppt_limit_type.define('SMU_DEFAULT_PPT_LIMIT', 0) +SMU_FAST_PPT_LIMIT = enum_smu_ppt_limit_type.define('SMU_FAST_PPT_LIMIT', 1) -# values for enumeration 'smu_power_src_type' -smu_power_src_type__enumvalues = { - 0: 'SMU_POWER_SOURCE_AC', - 1: 'SMU_POWER_SOURCE_DC', - 2: 'SMU_POWER_SOURCE_COUNT', -} -SMU_POWER_SOURCE_AC = 0 -SMU_POWER_SOURCE_DC = 1 -SMU_POWER_SOURCE_COUNT = 2 -smu_power_src_type = ctypes.c_uint32 # enum +enum_smu_ppt_limit_level = CEnum(ctypes.c_int32) +SMU_PPT_LIMIT_MIN = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_MIN', -1) +SMU_PPT_LIMIT_CURRENT = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_CURRENT', 0) +SMU_PPT_LIMIT_DEFAULT = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_DEFAULT', 1) +SMU_PPT_LIMIT_MAX = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_MAX', 2) -# values for enumeration 'smu_ppt_limit_type' -smu_ppt_limit_type__enumvalues = { - 0: 'SMU_DEFAULT_PPT_LIMIT', - 1: 'SMU_FAST_PPT_LIMIT', -} -SMU_DEFAULT_PPT_LIMIT = 0 -SMU_FAST_PPT_LIMIT = 1 -smu_ppt_limit_type = ctypes.c_uint32 # enum +enum_smu_memory_pool_size = CEnum(ctypes.c_uint32) +SMU_MEMORY_POOL_SIZE_ZERO = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_ZERO', 0) +SMU_MEMORY_POOL_SIZE_256_MB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_256_MB', 268435456) +SMU_MEMORY_POOL_SIZE_512_MB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_512_MB', 536870912) +SMU_MEMORY_POOL_SIZE_1_GB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_1_GB', 1073741824) +SMU_MEMORY_POOL_SIZE_2_GB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_2_GB', 2147483648) -# values for enumeration 'smu_ppt_limit_level' -smu_ppt_limit_level__enumvalues = { - -1: 'SMU_PPT_LIMIT_MIN', - 0: 'SMU_PPT_LIMIT_CURRENT', - 1: 'SMU_PPT_LIMIT_DEFAULT', - 2: 'SMU_PPT_LIMIT_MAX', -} -SMU_PPT_LIMIT_MIN = -1 -SMU_PPT_LIMIT_CURRENT = 0 -SMU_PPT_LIMIT_DEFAULT = 1 -SMU_PPT_LIMIT_MAX = 2 -smu_ppt_limit_level = ctypes.c_int32 # enum +enum_smu_clk_type = CEnum(ctypes.c_uint32) +SMU_GFXCLK = enum_smu_clk_type.define('SMU_GFXCLK', 0) +SMU_VCLK = enum_smu_clk_type.define('SMU_VCLK', 1) +SMU_DCLK = enum_smu_clk_type.define('SMU_DCLK', 2) +SMU_VCLK1 = enum_smu_clk_type.define('SMU_VCLK1', 3) +SMU_DCLK1 = enum_smu_clk_type.define('SMU_DCLK1', 4) +SMU_ECLK = enum_smu_clk_type.define('SMU_ECLK', 5) +SMU_SOCCLK = enum_smu_clk_type.define('SMU_SOCCLK', 6) +SMU_UCLK = enum_smu_clk_type.define('SMU_UCLK', 7) +SMU_DCEFCLK = enum_smu_clk_type.define('SMU_DCEFCLK', 8) +SMU_DISPCLK = enum_smu_clk_type.define('SMU_DISPCLK', 9) +SMU_PIXCLK = enum_smu_clk_type.define('SMU_PIXCLK', 10) +SMU_PHYCLK = enum_smu_clk_type.define('SMU_PHYCLK', 11) +SMU_FCLK = enum_smu_clk_type.define('SMU_FCLK', 12) +SMU_SCLK = enum_smu_clk_type.define('SMU_SCLK', 13) +SMU_MCLK = enum_smu_clk_type.define('SMU_MCLK', 14) +SMU_PCIE = enum_smu_clk_type.define('SMU_PCIE', 15) +SMU_LCLK = enum_smu_clk_type.define('SMU_LCLK', 16) +SMU_OD_CCLK = enum_smu_clk_type.define('SMU_OD_CCLK', 17) +SMU_OD_SCLK = enum_smu_clk_type.define('SMU_OD_SCLK', 18) +SMU_OD_MCLK = enum_smu_clk_type.define('SMU_OD_MCLK', 19) +SMU_OD_VDDC_CURVE = enum_smu_clk_type.define('SMU_OD_VDDC_CURVE', 20) +SMU_OD_RANGE = enum_smu_clk_type.define('SMU_OD_RANGE', 21) +SMU_OD_VDDGFX_OFFSET = enum_smu_clk_type.define('SMU_OD_VDDGFX_OFFSET', 22) +SMU_OD_FAN_CURVE = enum_smu_clk_type.define('SMU_OD_FAN_CURVE', 23) +SMU_OD_ACOUSTIC_LIMIT = enum_smu_clk_type.define('SMU_OD_ACOUSTIC_LIMIT', 24) +SMU_OD_ACOUSTIC_TARGET = enum_smu_clk_type.define('SMU_OD_ACOUSTIC_TARGET', 25) +SMU_OD_FAN_TARGET_TEMPERATURE = enum_smu_clk_type.define('SMU_OD_FAN_TARGET_TEMPERATURE', 26) +SMU_OD_FAN_MINIMUM_PWM = enum_smu_clk_type.define('SMU_OD_FAN_MINIMUM_PWM', 27) +SMU_CLK_COUNT = enum_smu_clk_type.define('SMU_CLK_COUNT', 28) -# values for enumeration 'smu_memory_pool_size' -smu_memory_pool_size__enumvalues = { - 0: 'SMU_MEMORY_POOL_SIZE_ZERO', - 268435456: 'SMU_MEMORY_POOL_SIZE_256_MB', - 536870912: 'SMU_MEMORY_POOL_SIZE_512_MB', - 1073741824: 'SMU_MEMORY_POOL_SIZE_1_GB', - 2147483648: 'SMU_MEMORY_POOL_SIZE_2_GB', -} -SMU_MEMORY_POOL_SIZE_ZERO = 0 -SMU_MEMORY_POOL_SIZE_256_MB = 268435456 -SMU_MEMORY_POOL_SIZE_512_MB = 536870912 -SMU_MEMORY_POOL_SIZE_1_GB = 1073741824 -SMU_MEMORY_POOL_SIZE_2_GB = 2147483648 -smu_memory_pool_size = ctypes.c_uint32 # enum - -# values for enumeration 'smu_clk_type' -smu_clk_type__enumvalues = { - 0: 'SMU_GFXCLK', - 1: 'SMU_VCLK', - 2: 'SMU_DCLK', - 3: 'SMU_VCLK1', - 4: 'SMU_DCLK1', - 5: 'SMU_ECLK', - 6: 'SMU_SOCCLK', - 7: 'SMU_UCLK', - 8: 'SMU_DCEFCLK', - 9: 'SMU_DISPCLK', - 10: 'SMU_PIXCLK', - 11: 'SMU_PHYCLK', - 12: 'SMU_FCLK', - 13: 'SMU_SCLK', - 14: 'SMU_MCLK', - 15: 'SMU_PCIE', - 16: 'SMU_LCLK', - 17: 'SMU_OD_CCLK', - 18: 'SMU_OD_SCLK', - 19: 'SMU_OD_MCLK', - 20: 'SMU_OD_VDDC_CURVE', - 21: 'SMU_OD_RANGE', - 22: 'SMU_OD_VDDGFX_OFFSET', - 23: 'SMU_OD_FAN_CURVE', - 24: 'SMU_OD_ACOUSTIC_LIMIT', - 25: 'SMU_OD_ACOUSTIC_TARGET', - 26: 'SMU_OD_FAN_TARGET_TEMPERATURE', - 27: 'SMU_OD_FAN_MINIMUM_PWM', - 28: 'SMU_CLK_COUNT', -} -SMU_GFXCLK = 0 -SMU_VCLK = 1 -SMU_DCLK = 2 -SMU_VCLK1 = 3 -SMU_DCLK1 = 4 -SMU_ECLK = 5 -SMU_SOCCLK = 6 -SMU_UCLK = 7 -SMU_DCEFCLK = 8 -SMU_DISPCLK = 9 -SMU_PIXCLK = 10 -SMU_PHYCLK = 11 -SMU_FCLK = 12 -SMU_SCLK = 13 -SMU_MCLK = 14 -SMU_PCIE = 15 -SMU_LCLK = 16 -SMU_OD_CCLK = 17 -SMU_OD_SCLK = 18 -SMU_OD_MCLK = 19 -SMU_OD_VDDC_CURVE = 20 -SMU_OD_RANGE = 21 -SMU_OD_VDDGFX_OFFSET = 22 -SMU_OD_FAN_CURVE = 23 -SMU_OD_ACOUSTIC_LIMIT = 24 -SMU_OD_ACOUSTIC_TARGET = 25 -SMU_OD_FAN_TARGET_TEMPERATURE = 26 -SMU_OD_FAN_MINIMUM_PWM = 27 -SMU_CLK_COUNT = 28 -smu_clk_type = ctypes.c_uint32 # enum -class struct_smu_user_dpm_profile(Structure): - pass - -struct_smu_user_dpm_profile._pack_ = 1 # source:False +class struct_smu_user_dpm_profile(Struct): pass struct_smu_user_dpm_profile._fields_ = [ - ('fan_mode', ctypes.c_uint32), - ('power_limit', ctypes.c_uint32), - ('fan_speed_pwm', ctypes.c_uint32), - ('fan_speed_rpm', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('user_od', ctypes.c_uint32), - ('clk_mask', ctypes.c_uint32 * 28), - ('clk_dependency', ctypes.c_uint32), + ('fan_mode', ctypes.c_uint32), + ('power_limit', ctypes.c_uint32), + ('fan_speed_pwm', ctypes.c_uint32), + ('fan_speed_rpm', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('user_od', ctypes.c_uint32), + ('clk_mask', (ctypes.c_uint32 * 28)), + ('clk_dependency', ctypes.c_uint32), ] - -class struct_smu_table(Structure): - pass - -class struct_amdgpu_bo(Structure): - pass - -struct_smu_table._pack_ = 1 # source:False +class struct_smu_table(Struct): pass +class struct_amdgpu_bo(Struct): pass struct_smu_table._fields_ = [ - ('size', ctypes.c_uint64), - ('align', ctypes.c_uint32), - ('domain', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('mc_address', ctypes.c_uint64), - ('cpu_addr', ctypes.POINTER(None)), - ('bo', ctypes.POINTER(struct_amdgpu_bo)), - ('version', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('size', ctypes.c_uint64), + ('align', ctypes.c_uint32), + ('domain', ctypes.c_ubyte), + ('mc_address', ctypes.c_uint64), + ('cpu_addr', ctypes.c_void_p), + ('bo', ctypes.POINTER(struct_amdgpu_bo)), + ('version', ctypes.c_uint32), ] +enum_smu_perf_level_designation = CEnum(ctypes.c_uint32) +PERF_LEVEL_ACTIVITY = enum_smu_perf_level_designation.define('PERF_LEVEL_ACTIVITY', 0) +PERF_LEVEL_POWER_CONTAINMENT = enum_smu_perf_level_designation.define('PERF_LEVEL_POWER_CONTAINMENT', 1) - -# values for enumeration 'smu_perf_level_designation' -smu_perf_level_designation__enumvalues = { - 0: 'PERF_LEVEL_ACTIVITY', - 1: 'PERF_LEVEL_POWER_CONTAINMENT', -} -PERF_LEVEL_ACTIVITY = 0 -PERF_LEVEL_POWER_CONTAINMENT = 1 -smu_perf_level_designation = ctypes.c_uint32 # enum -class struct_smu_performance_level(Structure): - pass - -struct_smu_performance_level._pack_ = 1 # source:False +class struct_smu_performance_level(Struct): pass struct_smu_performance_level._fields_ = [ - ('core_clock', ctypes.c_uint32), - ('memory_clock', ctypes.c_uint32), - ('vddc', ctypes.c_uint32), - ('vddci', ctypes.c_uint32), - ('non_local_mem_freq', ctypes.c_uint32), - ('non_local_mem_width', ctypes.c_uint32), + ('core_clock', ctypes.c_uint32), + ('memory_clock', ctypes.c_uint32), + ('vddc', ctypes.c_uint32), + ('vddci', ctypes.c_uint32), + ('non_local_mem_freq', ctypes.c_uint32), + ('non_local_mem_width', ctypes.c_uint32), ] - -class struct_smu_clock_info(Structure): - pass - -struct_smu_clock_info._pack_ = 1 # source:False +class struct_smu_clock_info(Struct): pass struct_smu_clock_info._fields_ = [ - ('min_mem_clk', ctypes.c_uint32), - ('max_mem_clk', ctypes.c_uint32), - ('min_eng_clk', ctypes.c_uint32), - ('max_eng_clk', ctypes.c_uint32), - ('min_bus_bandwidth', ctypes.c_uint32), - ('max_bus_bandwidth', ctypes.c_uint32), + ('min_mem_clk', ctypes.c_uint32), + ('max_mem_clk', ctypes.c_uint32), + ('min_eng_clk', ctypes.c_uint32), + ('max_eng_clk', ctypes.c_uint32), + ('min_bus_bandwidth', ctypes.c_uint32), + ('max_bus_bandwidth', ctypes.c_uint32), ] - -class struct_smu_bios_boot_up_values(Structure): - pass - -struct_smu_bios_boot_up_values._pack_ = 1 # source:False +class struct_smu_bios_boot_up_values(Struct): pass struct_smu_bios_boot_up_values._fields_ = [ - ('revision', ctypes.c_uint32), - ('gfxclk', ctypes.c_uint32), - ('uclk', ctypes.c_uint32), - ('socclk', ctypes.c_uint32), - ('dcefclk', ctypes.c_uint32), - ('eclk', ctypes.c_uint32), - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), - ('vddc', ctypes.c_uint16), - ('vddci', ctypes.c_uint16), - ('mvddc', ctypes.c_uint16), - ('vdd_gfx', ctypes.c_uint16), - ('cooling_id', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pp_table_id', ctypes.c_uint32), - ('format_revision', ctypes.c_uint32), - ('content_revision', ctypes.c_uint32), - ('fclk', ctypes.c_uint32), - ('lclk', ctypes.c_uint32), - ('firmware_caps', ctypes.c_uint32), + ('revision', ctypes.c_uint32), + ('gfxclk', ctypes.c_uint32), + ('uclk', ctypes.c_uint32), + ('socclk', ctypes.c_uint32), + ('dcefclk', ctypes.c_uint32), + ('eclk', ctypes.c_uint32), + ('vclk', ctypes.c_uint32), + ('dclk', ctypes.c_uint32), + ('vddc', ctypes.c_uint16), + ('vddci', ctypes.c_uint16), + ('mvddc', ctypes.c_uint16), + ('vdd_gfx', ctypes.c_uint16), + ('cooling_id', ctypes.c_ubyte), + ('pp_table_id', ctypes.c_uint32), + ('format_revision', ctypes.c_uint32), + ('content_revision', ctypes.c_uint32), + ('fclk', ctypes.c_uint32), + ('lclk', ctypes.c_uint32), + ('firmware_caps', ctypes.c_uint32), ] +enum_smu_table_id = CEnum(ctypes.c_uint32) +SMU_TABLE_PPTABLE = enum_smu_table_id.define('SMU_TABLE_PPTABLE', 0) +SMU_TABLE_WATERMARKS = enum_smu_table_id.define('SMU_TABLE_WATERMARKS', 1) +SMU_TABLE_CUSTOM_DPM = enum_smu_table_id.define('SMU_TABLE_CUSTOM_DPM', 2) +SMU_TABLE_DPMCLOCKS = enum_smu_table_id.define('SMU_TABLE_DPMCLOCKS', 3) +SMU_TABLE_AVFS = enum_smu_table_id.define('SMU_TABLE_AVFS', 4) +SMU_TABLE_AVFS_PSM_DEBUG = enum_smu_table_id.define('SMU_TABLE_AVFS_PSM_DEBUG', 5) +SMU_TABLE_AVFS_FUSE_OVERRIDE = enum_smu_table_id.define('SMU_TABLE_AVFS_FUSE_OVERRIDE', 6) +SMU_TABLE_PMSTATUSLOG = enum_smu_table_id.define('SMU_TABLE_PMSTATUSLOG', 7) +SMU_TABLE_SMU_METRICS = enum_smu_table_id.define('SMU_TABLE_SMU_METRICS', 8) +SMU_TABLE_DRIVER_SMU_CONFIG = enum_smu_table_id.define('SMU_TABLE_DRIVER_SMU_CONFIG', 9) +SMU_TABLE_ACTIVITY_MONITOR_COEFF = enum_smu_table_id.define('SMU_TABLE_ACTIVITY_MONITOR_COEFF', 10) +SMU_TABLE_OVERDRIVE = enum_smu_table_id.define('SMU_TABLE_OVERDRIVE', 11) +SMU_TABLE_I2C_COMMANDS = enum_smu_table_id.define('SMU_TABLE_I2C_COMMANDS', 12) +SMU_TABLE_PACE = enum_smu_table_id.define('SMU_TABLE_PACE', 13) +SMU_TABLE_ECCINFO = enum_smu_table_id.define('SMU_TABLE_ECCINFO', 14) +SMU_TABLE_COMBO_PPTABLE = enum_smu_table_id.define('SMU_TABLE_COMBO_PPTABLE', 15) +SMU_TABLE_WIFIBAND = enum_smu_table_id.define('SMU_TABLE_WIFIBAND', 16) +SMU_TABLE_COUNT = enum_smu_table_id.define('SMU_TABLE_COUNT', 17) - -# values for enumeration 'smu_table_id' -smu_table_id__enumvalues = { - 0: 'SMU_TABLE_PPTABLE', - 1: 'SMU_TABLE_WATERMARKS', - 2: 'SMU_TABLE_CUSTOM_DPM', - 3: 'SMU_TABLE_DPMCLOCKS', - 4: 'SMU_TABLE_AVFS', - 5: 'SMU_TABLE_AVFS_PSM_DEBUG', - 6: 'SMU_TABLE_AVFS_FUSE_OVERRIDE', - 7: 'SMU_TABLE_PMSTATUSLOG', - 8: 'SMU_TABLE_SMU_METRICS', - 9: 'SMU_TABLE_DRIVER_SMU_CONFIG', - 10: 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', - 11: 'SMU_TABLE_OVERDRIVE', - 12: 'SMU_TABLE_I2C_COMMANDS', - 13: 'SMU_TABLE_PACE', - 14: 'SMU_TABLE_ECCINFO', - 15: 'SMU_TABLE_COMBO_PPTABLE', - 16: 'SMU_TABLE_WIFIBAND', - 17: 'SMU_TABLE_COUNT', -} -SMU_TABLE_PPTABLE = 0 -SMU_TABLE_WATERMARKS = 1 -SMU_TABLE_CUSTOM_DPM = 2 -SMU_TABLE_DPMCLOCKS = 3 -SMU_TABLE_AVFS = 4 -SMU_TABLE_AVFS_PSM_DEBUG = 5 -SMU_TABLE_AVFS_FUSE_OVERRIDE = 6 -SMU_TABLE_PMSTATUSLOG = 7 -SMU_TABLE_SMU_METRICS = 8 -SMU_TABLE_DRIVER_SMU_CONFIG = 9 -SMU_TABLE_ACTIVITY_MONITOR_COEFF = 10 -SMU_TABLE_OVERDRIVE = 11 -SMU_TABLE_I2C_COMMANDS = 12 -SMU_TABLE_PACE = 13 -SMU_TABLE_ECCINFO = 14 -SMU_TABLE_COMBO_PPTABLE = 15 -SMU_TABLE_WIFIBAND = 16 -SMU_TABLE_COUNT = 17 -smu_table_id = ctypes.c_uint32 # enum -__all__ = \ - ['ALLOWED_FEATURE_CTRL_DEFAULT', 'ALLOWED_FEATURE_CTRL_SCPM', - 'AVFS_D_COUNT', 'AVFS_D_G', 'AVFS_D_M_B', 'AVFS_D_M_S', - 'AVFS_D_e', 'AVFS_D_e__enumvalues', 'AVFS_TEMP_COLD', - 'AVFS_TEMP_COUNT', 'AVFS_TEMP_HOT', 'AVFS_TEMP_e', - 'AVFS_TEMP_e__enumvalues', 'AVFS_VOLTAGE_COUNT', - 'AVFS_VOLTAGE_GFX', 'AVFS_VOLTAGE_SOC', 'AVFS_VOLTAGE_TYPE_e', - 'AVFS_VOLTAGE_TYPE_e__enumvalues', 'AvfsDcBtcParams_t', - 'AvfsDebugTableExternal_t', 'AvfsDebugTable_t', - 'AvfsFuseOverride_t', 'BACO_SEQUENCE', 'BAMACO_SEQUENCE', - 'BOARD_GPIO_DC_GENLK_CLK', 'BOARD_GPIO_DC_GENLK_VSYNC', - 'BOARD_GPIO_DC_GEN_A', 'BOARD_GPIO_DC_GEN_B', - 'BOARD_GPIO_DC_GEN_C', 'BOARD_GPIO_DC_GEN_D', - 'BOARD_GPIO_DC_GEN_E', 'BOARD_GPIO_DC_GEN_F', - 'BOARD_GPIO_DC_GEN_G', 'BOARD_GPIO_DC_SWAPLOCK_A', - 'BOARD_GPIO_DC_SWAPLOCK_B', 'BOARD_GPIO_SMUIO_0', - 'BOARD_GPIO_SMUIO_1', 'BOARD_GPIO_SMUIO_10', - 'BOARD_GPIO_SMUIO_11', 'BOARD_GPIO_SMUIO_12', - 'BOARD_GPIO_SMUIO_13', 'BOARD_GPIO_SMUIO_14', - 'BOARD_GPIO_SMUIO_15', 'BOARD_GPIO_SMUIO_16', - 'BOARD_GPIO_SMUIO_17', 'BOARD_GPIO_SMUIO_18', - 'BOARD_GPIO_SMUIO_19', 'BOARD_GPIO_SMUIO_2', - 'BOARD_GPIO_SMUIO_20', 'BOARD_GPIO_SMUIO_21', - 'BOARD_GPIO_SMUIO_22', 'BOARD_GPIO_SMUIO_23', - 'BOARD_GPIO_SMUIO_24', 'BOARD_GPIO_SMUIO_25', - 'BOARD_GPIO_SMUIO_26', 'BOARD_GPIO_SMUIO_27', - 'BOARD_GPIO_SMUIO_28', 'BOARD_GPIO_SMUIO_29', - 'BOARD_GPIO_SMUIO_3', 'BOARD_GPIO_SMUIO_30', - 'BOARD_GPIO_SMUIO_31', 'BOARD_GPIO_SMUIO_4', 'BOARD_GPIO_SMUIO_5', - 'BOARD_GPIO_SMUIO_6', 'BOARD_GPIO_SMUIO_7', 'BOARD_GPIO_SMUIO_8', - 'BOARD_GPIO_SMUIO_9', 'BOARD_GPIO_TYPE_e', - 'BOARD_GPIO_TYPE_e__enumvalues', 'BoardTable_t', 'BootValues_t', - 'CMDCONFIG_READWRITE_BIT', 'CMDCONFIG_READWRITE_MASK', - 'CMDCONFIG_RESTART_BIT', 'CMDCONFIG_RESTART_MASK', - 'CMDCONFIG_STOP_BIT', 'CMDCONFIG_STOP_MASK', - 'CUSTOMER_VARIANT_COUNT', 'CUSTOMER_VARIANT_FALCON', - 'CUSTOMER_VARIANT_ROW', 'CUSTOMER_VARIANT_e', - 'CUSTOMER_VARIANT_e__enumvalues', 'D3HOTSequence_e', - 'D3HOTSequence_e__enumvalues', 'D3HOT_SEQUENCE_COUNT', - 'DCS_ARCH_ASYNC', 'DCS_ARCH_DISABLED', 'DCS_ARCH_FADCS', - 'DCS_ARCH_e', 'DCS_ARCH_e__enumvalues', - 'DEBUGSMC_MSG_DebugDumpExit', 'DEBUGSMC_MSG_GetDebugData', - 'DEBUGSMC_MSG_TestMessage', 'DEBUGSMC_Message_Count', - 'DEBUGSMC_VERSION', 'DEBUG_OVERRIDE_DFLL_MASTER_MODE', - 'DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK', - 'DEBUG_OVERRIDE_DISABLE_DFLL', - 'DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER', - 'DEBUG_OVERRIDE_DISABLE_FMAX_VMAX', - 'DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS', - 'DEBUG_OVERRIDE_DISABLE_VCN_PG', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK', - 'DEBUG_OVERRIDE_ENABLE_PROFILING_MODE', - 'DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE', - 'DRAM_BIT_WIDTH_COUNT', 'DRAM_BIT_WIDTH_DISABLED', - 'DRAM_BIT_WIDTH_TYPE_e', 'DRAM_BIT_WIDTH_TYPE_e__enumvalues', - 'DRAM_BIT_WIDTH_X_128', 'DRAM_BIT_WIDTH_X_16', - 'DRAM_BIT_WIDTH_X_32', 'DRAM_BIT_WIDTH_X_64', - 'DRAM_BIT_WIDTH_X_8', 'DpmActivityMonitorCoeffIntExternal_t', - 'DpmActivityMonitorCoeffInt_t', 'DpmDescriptor_t', - 'DriverInfoTable_t', 'DriverReportedClocks_t', - 'DriverSmuConfigExternal_t', 'DriverSmuConfig_t', 'DroopInt_t', - 'EccInfoTable_t', 'EccInfo_t', 'FAN_MODE_AUTO', - 'FAN_MODE_MANUAL_LINEAR', 'FEATURE_ACDC_BIT', - 'FEATURE_ATHUB_MMHUB_PG_BIT', 'FEATURE_BACO_BIT', - 'FEATURE_BACO_CG_BIT', 'FEATURE_BACO_MPCLK_DS_BIT', - 'FEATURE_BOMXCO_SVI3_PROG_BIT', 'FEATURE_BOOT_POWER_OPT_BIT', - 'FEATURE_BOOT_TIME_CAL_BIT', - 'FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT', 'FEATURE_DF_CSTATE_BIT', - 'FEATURE_DPM_DCN_BIT', 'FEATURE_DPM_FCLK_BIT', - 'FEATURE_DPM_GFXCLK_BIT', 'FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT', - 'FEATURE_DPM_LINK_BIT', 'FEATURE_DPM_MP0CLK_BIT', - 'FEATURE_DPM_SOCCLK_BIT', 'FEATURE_DPM_UCLK_BIT', - 'FEATURE_DS_DCFCLK_BIT', 'FEATURE_DS_FCLK_BIT', - 'FEATURE_DS_GFXCLK_BIT', 'FEATURE_DS_LCLK_BIT', - 'FEATURE_DS_SOCCLK_BIT', 'FEATURE_DS_UCLK_BIT', - 'FEATURE_DS_VCN_BIT', 'FEATURE_EDC_PWRBRK_BIT', - 'FEATURE_FAN_CONTROL_BIT', 'FEATURE_FW_CTF_BIT', - 'FEATURE_FW_DATA_READ_BIT', 'FEATURE_FW_DSTATE_BIT', - 'FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT', 'FEATURE_GFXOFF_BIT', - 'FEATURE_GFX_DCS_BIT', 'FEATURE_GFX_EDC_BIT', - 'FEATURE_GFX_IMU_BIT', 'FEATURE_GFX_PCC_DFLL_BIT', - 'FEATURE_GFX_READ_MARGIN_BIT', 'FEATURE_GFX_ULV_BIT', - 'FEATURE_GTHR_BIT', 'FEATURE_LED_DISPLAY_BIT', - 'FEATURE_MEM_TEMP_READ_BIT', 'FEATURE_MM_DPM_BIT', - 'FEATURE_OPTIMIZED_VMIN_BIT', 'FEATURE_OUT_OF_BAND_MONITOR_BIT', - 'FEATURE_PWR_ALL', 'FEATURE_PWR_BACO', 'FEATURE_PWR_DOMAIN_COUNT', - 'FEATURE_PWR_DOMAIN_e', 'FEATURE_PWR_DOMAIN_e__enumvalues', - 'FEATURE_PWR_GFX', 'FEATURE_PWR_S5', 'FEATURE_PWR_SOC', - 'FEATURE_SMARTSHIFT_BIT', 'FEATURE_SOC_CG_BIT', - 'FEATURE_SOC_MPCLK_DS_BIT', 'FEATURE_SOC_PCC_BIT', - 'FEATURE_SPARE_52_BIT', 'FEATURE_SPARE_53_BIT', - 'FEATURE_SPARE_54_BIT', 'FEATURE_SPARE_55_BIT', - 'FEATURE_SPARE_56_BIT', 'FEATURE_SPARE_57_BIT', - 'FEATURE_SPARE_58_BIT', 'FEATURE_SPARE_59_BIT', - 'FEATURE_SPARE_60_BIT', 'FEATURE_SPARE_61_BIT', - 'FEATURE_SPARE_62_BIT', 'FEATURE_SPARE_63_BIT', - 'FEATURE_THROTTLERS_BIT', 'FEATURE_VDDIO_MEM_SCALING_BIT', - 'FEATURE_VMEMP_SCALING_BIT', 'FEATURE_VR0HOT_BIT', - 'FOPT_CALC_AC_CALC_DC', 'FOPT_CALC_AC_PPTABLE_DC', 'FOPT_CALC_e', - 'FOPT_CALC_e__enumvalues', 'FOPT_PPTABLE_AC_CALC_DC', - 'FOPT_PPTABLE_AC_PPTABLE_DC', 'FW_DSTATE_CLDO_PRG_BIT', - 'FW_DSTATE_CSRCLK_DS_BIT', 'FW_DSTATE_D0i3_2_QUIET_FW_BIT', - 'FW_DSTATE_DF_PLL_PWRDN_BIT', 'FW_DSTATE_G6_HSR_BIT', - 'FW_DSTATE_G6_PHY_VMEMP_OFF_BIT', 'FW_DSTATE_GFX_PSI6_BIT', - 'FW_DSTATE_GFX_VR_PWR_STAGE_BIT', 'FW_DSTATE_HSR_NON_STROBE_BIT', - 'FW_DSTATE_MALL_ALLOC_BIT', 'FW_DSTATE_MALL_FLUSH_BIT', - 'FW_DSTATE_MEM_PLL_PWRDN_BIT', 'FW_DSTATE_MEM_PSI_BIT', - 'FW_DSTATE_MMHUB_INTERLOCK_BIT', 'FW_DSTATE_MP0_ENTER_WFI_BIT', - 'FW_DSTATE_MP1_WHISPER_MODE_BIT', 'FW_DSTATE_SMN_DS_BIT', - 'FW_DSTATE_SOC_LIV_MIN_BIT', 'FW_DSTATE_SOC_PLL_PWRDN_BIT', - 'FW_DSTATE_SOC_PSI_BIT', 'FW_DSTATE_SOC_ULV_BIT', - 'FW_DSTATE_UCP_DS_BIT', 'FW_DSTATE_U_LOW_PWR_MODE_EN_BIT', - 'FW_DSTATE_U_PSI_BIT', 'FW_DSTATE_U_ULV_BIT', 'FanMode_e', - 'FanMode_e__enumvalues', 'GPIO_INT_POLARITY_ACTIVE_HIGH', - 'GPIO_INT_POLARITY_ACTIVE_LOW', 'GpioIntPolarity_e', - 'GpioIntPolarity_e__enumvalues', 'I2C_CMD_COUNT', 'I2C_CMD_READ', - 'I2C_CMD_WRITE', 'I2C_CONTROLLER_DISABLED', - 'I2C_CONTROLLER_ENABLED', 'I2C_CONTROLLER_NAME_COUNT', - 'I2C_CONTROLLER_NAME_FAN_INTAKE', 'I2C_CONTROLLER_NAME_LIQUID0', - 'I2C_CONTROLLER_NAME_LIQUID1', 'I2C_CONTROLLER_NAME_PLX', - 'I2C_CONTROLLER_NAME_VR_GFX', 'I2C_CONTROLLER_NAME_VR_SOC', - 'I2C_CONTROLLER_NAME_VR_VDDIO', 'I2C_CONTROLLER_NAME_VR_VMEMP', - 'I2C_CONTROLLER_PORT_0', 'I2C_CONTROLLER_PORT_1', - 'I2C_CONTROLLER_PORT_COUNT', 'I2C_CONTROLLER_PROTOCOL_COUNT', - 'I2C_CONTROLLER_PROTOCOL_INA3221', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 'I2C_CONTROLLER_THROTTLER_COUNT', - 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 'I2C_CONTROLLER_THROTTLER_INA3221', - 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 'I2C_CONTROLLER_THROTTLER_PLX', - 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', 'I2C_PORT_GPIO', - 'I2C_PORT_SVD_SCL', 'I2C_SPEED_COUNT', 'I2C_SPEED_FAST_100K', - 'I2C_SPEED_FAST_400K', 'I2C_SPEED_FAST_50K', - 'I2C_SPEED_FAST_PLUS_1M', 'I2C_SPEED_HIGH_1M', - 'I2C_SPEED_HIGH_2M', 'I2cCmdType_e', 'I2cCmdType_e__enumvalues', - 'I2cControllerConfig_t', 'I2cControllerName_e', - 'I2cControllerName_e__enumvalues', 'I2cControllerPort_e', - 'I2cControllerPort_e__enumvalues', 'I2cControllerProtocol_e', - 'I2cControllerProtocol_e__enumvalues', 'I2cControllerThrottler_e', - 'I2cControllerThrottler_e__enumvalues', 'I2cPort_e', - 'I2cPort_e__enumvalues', 'I2cSpeed_e', 'I2cSpeed_e__enumvalues', - 'IH_INTERRUPT_CONTEXT_ID_AC', 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D0', - 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D3', - 'IH_INTERRUPT_CONTEXT_ID_BACO', 'IH_INTERRUPT_CONTEXT_ID_DC', - 'IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL', - 'IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY', - 'IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING', - 'IH_INTERRUPT_ID_TO_DRIVER', 'INVALID_BOARD_GPIO', - 'LED_DISPLAY_ERROR_BIT', 'LED_DISPLAY_GFX_DPM_BIT', - 'LED_DISPLAY_PCIE_BIT', 'LinearInt_t', 'MARKETING_BASE_CLOCKS', - 'MARKETING_BOOST_CLOCKS', 'MARKETING_GAME_CLOCKS', - 'MAX_BOARD_GPIO_SMUIO_NUM', 'MAX_SW_I2C_COMMANDS', - 'MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT', - 'MEM_TEMP_READ_IN_BAND_REFRESH_BIT', - 'MEM_TEMP_READ_OUT_OF_BAND_BIT', 'MEM_VENDOR_COUNT', - 'MEM_VENDOR_ELPIDA', 'MEM_VENDOR_ESMT', 'MEM_VENDOR_ETRON', - 'MEM_VENDOR_HYNIX', 'MEM_VENDOR_INFINEON', 'MEM_VENDOR_MICRON', - 'MEM_VENDOR_MOSEL', 'MEM_VENDOR_NANYA', 'MEM_VENDOR_PLACEHOLDER0', - 'MEM_VENDOR_PLACEHOLDER1', 'MEM_VENDOR_PLACEHOLDER2', - 'MEM_VENDOR_PLACEHOLDER3', 'MEM_VENDOR_PLACEHOLDER4', - 'MEM_VENDOR_PLACEHOLDER5', 'MEM_VENDOR_SAMSUNG', - 'MEM_VENDOR_WINBOND', 'MEM_VENDOR_e', 'MEM_VENDOR_e__enumvalues', - 'MSR_SEQUENCE', 'MsgLimits_t', 'NUM_DCFCLK_DPM_LEVELS', - 'NUM_DCLK_DPM_LEVELS', 'NUM_DISPCLK_DPM_LEVELS', - 'NUM_DPPCLK_DPM_LEVELS', 'NUM_DPREFCLK_DPM_LEVELS', - 'NUM_DTBCLK_DPM_LEVELS', 'NUM_FCLK_DPM_LEVELS', 'NUM_FEATURES', - 'NUM_GFXCLK_DPM_LEVELS', 'NUM_I2C_CONTROLLERS', 'NUM_LINK_LEVELS', - 'NUM_MP0CLK_DPM_LEVELS', 'NUM_OD_FAN_MAX_POINTS', - 'NUM_SOCCLK_DPM_LEVELS', 'NUM_UCLK_DPM_LEVELS', - 'NUM_VCLK_DPM_LEVELS', 'NUM_WM_RANGES', 'OverDriveLimits_t', - 'OverDriveTableExternal_t', 'OverDriveTable_t', - 'PERF_LEVEL_ACTIVITY', 'PERF_LEVEL_POWER_CONTAINMENT', - 'PG_DYNAMIC_MODE', 'PG_POWER_DOWN', 'PG_POWER_UP', - 'PG_STATIC_MODE', 'PMFW_VOLT_PLANE_COUNT', 'PMFW_VOLT_PLANE_GFX', - 'PMFW_VOLT_PLANE_SOC', 'PMFW_VOLT_PLANE_e', - 'PMFW_VOLT_PLANE_e__enumvalues', 'POWER_SOURCE_AC', - 'POWER_SOURCE_COUNT', 'POWER_SOURCE_DC', 'POWER_SOURCE_e', - 'POWER_SOURCE_e__enumvalues', 'PPCLK_COUNT', 'PPCLK_DCFCLK', - 'PPCLK_DCLK_0', 'PPCLK_DCLK_1', 'PPCLK_DISPCLK', 'PPCLK_DPPCLK', - 'PPCLK_DPREFCLK', 'PPCLK_DTBCLK', 'PPCLK_FCLK', 'PPCLK_GFXCLK', - 'PPCLK_SOCCLK', 'PPCLK_UCLK', 'PPCLK_VCLK_0', 'PPCLK_VCLK_1', - 'PPCLK_e', 'PPCLK_e__enumvalues', 'PPSMC_MSG_AllowGfxDcs', - 'PPSMC_MSG_AllowGfxOff', 'PPSMC_MSG_AllowIHHostInterrupt', - 'PPSMC_MSG_ArmD3', 'PPSMC_MSG_BacoAudioD3PME', - 'PPSMC_MSG_DALNotPresent', 'PPSMC_MSG_DisableAllSmuFeatures', - 'PPSMC_MSG_DisableSmuFeaturesHigh', - 'PPSMC_MSG_DisableSmuFeaturesLow', 'PPSMC_MSG_DisallowGfxDcs', - 'PPSMC_MSG_DisallowGfxOff', 'PPSMC_MSG_DramLogSetDramAddrHigh', - 'PPSMC_MSG_DramLogSetDramAddrLow', 'PPSMC_MSG_DramLogSetDramSize', - 'PPSMC_MSG_DumpSTBtoDram', 'PPSMC_MSG_EnableAllSmuFeatures', - 'PPSMC_MSG_EnableAudioStutterWA', - 'PPSMC_MSG_EnableSmuFeaturesHigh', - 'PPSMC_MSG_EnableSmuFeaturesLow', 'PPSMC_MSG_EnableUCLKShadow', - 'PPSMC_MSG_EnterBaco', 'PPSMC_MSG_ExitBaco', - 'PPSMC_MSG_GetDcModeMaxDpmFreq', 'PPSMC_MSG_GetDebugData', - 'PPSMC_MSG_GetDpmFreqByIndex', 'PPSMC_MSG_GetDriverIfVersion', - 'PPSMC_MSG_GetMaxDpmFreq', 'PPSMC_MSG_GetMinDpmFreq', - 'PPSMC_MSG_GetPptLimit', 'PPSMC_MSG_GetRunningSmuFeaturesHigh', - 'PPSMC_MSG_GetRunningSmuFeaturesLow', 'PPSMC_MSG_GetSmuVersion', - 'PPSMC_MSG_GetVoltageByDpm', 'PPSMC_MSG_Mode1Reset', - 'PPSMC_MSG_Mode2Reset', 'PPSMC_MSG_NotifyPowerSource', - 'PPSMC_MSG_OverridePcieParameters', 'PPSMC_MSG_PowerDownJpeg', - 'PPSMC_MSG_PowerDownUmsch', 'PPSMC_MSG_PowerDownVcn', - 'PPSMC_MSG_PowerUpJpeg', 'PPSMC_MSG_PowerUpUmsch', - 'PPSMC_MSG_PowerUpVcn', 'PPSMC_MSG_PrepareMp1ForUnload', - 'PPSMC_MSG_ReenableAcDcInterrupt', 'PPSMC_MSG_RunDcBtc', - 'PPSMC_MSG_STBtoDramLogSetDramAddrHigh', - 'PPSMC_MSG_STBtoDramLogSetDramAddrLow', - 'PPSMC_MSG_STBtoDramLogSetDramSize', - 'PPSMC_MSG_SetAllowedFeaturesMaskHigh', - 'PPSMC_MSG_SetAllowedFeaturesMaskLow', - 'PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel', - 'PPSMC_MSG_SetDcsArch', 'PPSMC_MSG_SetDriverDramAddrHigh', - 'PPSMC_MSG_SetDriverDramAddrLow', - 'PPSMC_MSG_SetExternalClientDfCstateAllow', - 'PPSMC_MSG_SetFwDstatesMask', 'PPSMC_MSG_SetGpoAllow', - 'PPSMC_MSG_SetHardMaxByFreq', 'PPSMC_MSG_SetHardMinByFreq', - 'PPSMC_MSG_SetMGpuFanBoostLimitRpm', - 'PPSMC_MSG_SetNumBadMemoryPagesRetired', 'PPSMC_MSG_SetPptLimit', - 'PPSMC_MSG_SetPriorityDeltaGain', 'PPSMC_MSG_SetSoftMaxByFreq', - 'PPSMC_MSG_SetSoftMinByFreq', - 'PPSMC_MSG_SetSystemVirtualDramAddrHigh', - 'PPSMC_MSG_SetSystemVirtualDramAddrLow', - 'PPSMC_MSG_SetTemperatureInputSelect', - 'PPSMC_MSG_SetThrottlerMask', 'PPSMC_MSG_SetToolsDramAddrHigh', - 'PPSMC_MSG_SetToolsDramAddrLow', 'PPSMC_MSG_SetVideoFps', - 'PPSMC_MSG_SetWorkloadMask', 'PPSMC_MSG_TestMessage', - 'PPSMC_MSG_TransferTableDram2Smu', - 'PPSMC_MSG_TransferTableSmu2Dram', 'PPSMC_MSG_TriggerVFFLR', - 'PPSMC_MSG_UseDefaultPPTable', 'PPSMC_Message_Count', - 'PPSMC_Result_CmdRejectedBusy', 'PPSMC_Result_CmdRejectedPrereq', - 'PPSMC_Result_Failed', 'PPSMC_Result_OK', - 'PPSMC_Result_UnknownCmd', 'PPSMC_VERSION', 'PPTABLE_VERSION', - 'PPT_THROTTLER_COUNT', 'PPT_THROTTLER_PPT0', 'PPT_THROTTLER_PPT1', - 'PPT_THROTTLER_PPT2', 'PPT_THROTTLER_PPT3', 'PPT_THROTTLER_e', - 'PPT_THROTTLER_e__enumvalues', 'PPTable_t', - 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 'PP_GRTAVFS_FW_COMMON_FUSE_e', - 'PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_e', - 'PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 'PP_GRTAVFS_HW_FUSE_COUNT', - 'PP_GRTAVFS_HW_FUSE_e', 'PP_GRTAVFS_HW_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_RESERVED_0', 'PP_GRTAVFS_HW_RESERVED_1', - 'PP_GRTAVFS_HW_RESERVED_2', 'PP_GRTAVFS_HW_RESERVED_3', - 'PP_GRTAVFS_HW_RESERVED_4', 'PP_GRTAVFS_HW_RESERVED_5', - 'PP_GRTAVFS_HW_RESERVED_6', 'PP_GRTAVFS_HW_VOLTAGE_GB', - 'PP_GRTAVFS_HW_ZONE0_VF', 'PP_GRTAVFS_HW_ZONE1_VF1', - 'PP_GRTAVFS_HW_ZONE2_VF2', 'PP_GRTAVFS_HW_ZONE3_VF3', - 'PP_NUM_OD_VF_CURVE_POINTS', 'PP_NUM_RTAVFS_PWL_ZONES', - 'PP_OD_FEATURE_COUNT', 'PP_OD_FEATURE_FAN_CURVE_BIT', - 'PP_OD_FEATURE_GFXCLK_BIT', 'PP_OD_FEATURE_GFX_VF_CURVE_BIT', - 'PP_OD_FEATURE_PPT_BIT', 'PP_OD_FEATURE_TEMPERATURE_BIT', - 'PP_OD_FEATURE_UCLK_BIT', 'PP_OD_FEATURE_ZERO_FAN_BIT', - 'PSI_SEL_VR0_PLANE0_PSI0', 'PSI_SEL_VR0_PLANE0_PSI1', - 'PSI_SEL_VR0_PLANE1_PSI0', 'PSI_SEL_VR0_PLANE1_PSI1', - 'PSI_SEL_VR1_PLANE0_PSI0', 'PSI_SEL_VR1_PLANE0_PSI1', - 'PSI_SEL_VR1_PLANE1_PSI0', 'PSI_SEL_VR1_PLANE1_PSI1', - 'PWR_CONFIG_TCP_ESTIMATED', 'PWR_CONFIG_TCP_MEASURED', - 'PWR_CONFIG_TDP', 'PWR_CONFIG_TGP', 'PowerGatingMode_e', - 'PowerGatingMode_e__enumvalues', 'PowerGatingSettings_e', - 'PowerGatingSettings_e__enumvalues', 'PwrConfig_e', - 'PwrConfig_e__enumvalues', 'QuadraticInt_t', - 'SMARTSHIFT_VERSION_1', 'SMARTSHIFT_VERSION_2', - 'SMARTSHIFT_VERSION_3', 'SMARTSHIFT_VERSION_e', - 'SMARTSHIFT_VERSION_e__enumvalues', 'SMU13_0_0_DRIVER_IF_VERSION', - 'SMU13_DRIVER_IF_V13_0_0_H', 'SMU_CLK_COUNT', - 'SMU_CUSTOM_FAN_SPEED_PWM', 'SMU_CUSTOM_FAN_SPEED_RPM', - 'SMU_DCEFCLK', 'SMU_DCLK', 'SMU_DCLK1', 'SMU_DEFAULT_PPT_LIMIT', - 'SMU_DISPCLK', 'SMU_DPM_USER_PROFILE_RESTORE', 'SMU_ECLK', - 'SMU_FAST_PPT_LIMIT', 'SMU_FCLK', 'SMU_FW_NAME_LEN', 'SMU_GFXCLK', - 'SMU_LCLK', 'SMU_MCLK', 'SMU_MEMORY_POOL_SIZE_1_GB', - 'SMU_MEMORY_POOL_SIZE_256_MB', 'SMU_MEMORY_POOL_SIZE_2_GB', - 'SMU_MEMORY_POOL_SIZE_512_MB', 'SMU_MEMORY_POOL_SIZE_ZERO', - 'SMU_OD_ACOUSTIC_LIMIT', 'SMU_OD_ACOUSTIC_TARGET', 'SMU_OD_CCLK', - 'SMU_OD_FAN_CURVE', 'SMU_OD_FAN_MINIMUM_PWM', - 'SMU_OD_FAN_TARGET_TEMPERATURE', 'SMU_OD_MCLK', 'SMU_OD_RANGE', - 'SMU_OD_SCLK', 'SMU_OD_VDDC_CURVE', 'SMU_OD_VDDGFX_OFFSET', - 'SMU_PCIE', 'SMU_PHYCLK', 'SMU_PIXCLK', 'SMU_POWER_SOURCE_AC', - 'SMU_POWER_SOURCE_COUNT', 'SMU_POWER_SOURCE_DC', - 'SMU_PPT_LIMIT_CURRENT', 'SMU_PPT_LIMIT_DEFAULT', - 'SMU_PPT_LIMIT_MAX', 'SMU_PPT_LIMIT_MIN', - 'SMU_REFRESHRATE_SOURCE_EDID', 'SMU_REFRESHRATE_SOURCE_EXPLICIT', - 'SMU_SCLK', 'SMU_SOCCLK', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 'SMU_STATE_UI_LABEL_BACO', - 'SMU_STATE_UI_LABEL_BALLANCED', 'SMU_STATE_UI_LABEL_BATTERY', - 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 'SMU_STATE_UI_LABEL_NONE', - 'SMU_STATE_UI_LABEL_PERFORMANCE', 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', 'SMU_TABLE_AVFS', - 'SMU_TABLE_AVFS_FUSE_OVERRIDE', 'SMU_TABLE_AVFS_PSM_DEBUG', - 'SMU_TABLE_COMBO_PPTABLE', 'SMU_TABLE_COUNT', - 'SMU_TABLE_CUSTOM_DPM', 'SMU_TABLE_DPMCLOCKS', - 'SMU_TABLE_DRIVER_SMU_CONFIG', 'SMU_TABLE_ECCINFO', - 'SMU_TABLE_I2C_COMMANDS', 'SMU_TABLE_OVERDRIVE', 'SMU_TABLE_PACE', - 'SMU_TABLE_PMSTATUSLOG', 'SMU_TABLE_PPTABLE', - 'SMU_TABLE_SMU_METRICS', 'SMU_TABLE_WATERMARKS', - 'SMU_TABLE_WIFIBAND', 'SMU_TEMPERATURE_UNITS_PER_CENTIGRADES', - 'SMU_THERMAL_MAXIMUM_ALERT_TEMP', - 'SMU_THERMAL_MINIMUM_ALERT_TEMP', 'SMU_THROTTLER_APCC_BIT', - 'SMU_THROTTLER_EDC_CPU_BIT', 'SMU_THROTTLER_EDC_GFX_BIT', - 'SMU_THROTTLER_FIT_BIT', 'SMU_THROTTLER_FPPT_BIT', - 'SMU_THROTTLER_PPM_BIT', 'SMU_THROTTLER_PPT0_BIT', - 'SMU_THROTTLER_PPT1_BIT', 'SMU_THROTTLER_PPT2_BIT', - 'SMU_THROTTLER_PPT3_BIT', 'SMU_THROTTLER_PROCHOT_CPU_BIT', - 'SMU_THROTTLER_PROCHOT_GFX_BIT', 'SMU_THROTTLER_SPL_BIT', - 'SMU_THROTTLER_SPPT_APU_BIT', 'SMU_THROTTLER_SPPT_BIT', - 'SMU_THROTTLER_TDC_CVIP_BIT', 'SMU_THROTTLER_TDC_GFX_BIT', - 'SMU_THROTTLER_TDC_MEM_BIT', 'SMU_THROTTLER_TDC_SOC_BIT', - 'SMU_THROTTLER_TDC_VDD_BIT', 'SMU_THROTTLER_TEMP_CORE_BIT', - 'SMU_THROTTLER_TEMP_EDGE_BIT', 'SMU_THROTTLER_TEMP_GPU_BIT', - 'SMU_THROTTLER_TEMP_HOTSPOT_BIT', - 'SMU_THROTTLER_TEMP_LIQUID0_BIT', - 'SMU_THROTTLER_TEMP_LIQUID1_BIT', 'SMU_THROTTLER_TEMP_MEM_BIT', - 'SMU_THROTTLER_TEMP_SOC_BIT', 'SMU_THROTTLER_TEMP_VR_GFX_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM0_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM1_BIT', 'SMU_THROTTLER_TEMP_VR_SOC_BIT', - 'SMU_THROTTLER_VRHOT0_BIT', 'SMU_THROTTLER_VRHOT1_BIT', - 'SMU_UCLK', 'SMU_V13_0_0_PPSMC_H', 'SMU_VCLK', 'SMU_VCLK1', - 'SVI_PLANE_COUNT', 'SVI_PLANE_GFX', 'SVI_PLANE_SOC', - 'SVI_PLANE_U', 'SVI_PLANE_VDDIO_MEM', 'SVI_PLANE_VMEMP', - 'SVI_PLANE_e', 'SVI_PLANE_e__enumvalues', 'SVI_PSI_0', - 'SVI_PSI_1', 'SVI_PSI_2', 'SVI_PSI_3', 'SVI_PSI_4', 'SVI_PSI_5', - 'SVI_PSI_6', 'SVI_PSI_7', 'SVI_PSI_e', 'SVI_PSI_e__enumvalues', - 'SkuTable_t', 'SmuMetricsExternal_t', 'SmuMetrics_t', - 'SviTelemetryScale_t', 'SwI2cCmd_t', 'SwI2cRequestExternal_t', - 'SwI2cRequest_t', 'TABLE_ACTIVITY_MONITOR_COEFF', - 'TABLE_AVFS_PSM_DEBUG', 'TABLE_COMBO_PPTABLE', 'TABLE_COUNT', - 'TABLE_DRIVER_INFO', 'TABLE_DRIVER_SMU_CONFIG', 'TABLE_ECCINFO', - 'TABLE_I2C_COMMANDS', 'TABLE_OVERDRIVE', 'TABLE_PMSTATUSLOG', - 'TABLE_PPTABLE', 'TABLE_SMU_METRICS', 'TABLE_TRANSFER_FAILED', - 'TABLE_TRANSFER_OK', 'TABLE_TRANSFER_PENDING', 'TABLE_WATERMARKS', - 'TABLE_WIFIBAND', 'TDC_THROTTLER_COUNT', 'TDC_THROTTLER_GFX', - 'TDC_THROTTLER_SOC', 'TDC_THROTTLER_U', 'TDC_THROTTLER_e', - 'TDC_THROTTLER_e__enumvalues', 'TEMP_COUNT', 'TEMP_EDGE', - 'TEMP_HOTSPOT', 'TEMP_HOTSPOT_G', 'TEMP_HOTSPOT_M', - 'TEMP_LIQUID0', 'TEMP_LIQUID1', 'TEMP_MEM', 'TEMP_PLX', - 'TEMP_VR_GFX', 'TEMP_VR_MEM0', 'TEMP_VR_MEM1', 'TEMP_VR_SOC', - 'TEMP_VR_U', 'TEMP_e', 'TEMP_e__enumvalues', 'THROTTLER_COUNT', - 'THROTTLER_FIT_BIT', 'THROTTLER_GFX_APCC_PLUS_BIT', - 'THROTTLER_PPT0_BIT', 'THROTTLER_PPT1_BIT', 'THROTTLER_PPT2_BIT', - 'THROTTLER_PPT3_BIT', 'THROTTLER_TDC_GFX_BIT', - 'THROTTLER_TDC_SOC_BIT', 'THROTTLER_TDC_U_BIT', - 'THROTTLER_TEMP_EDGE_BIT', 'THROTTLER_TEMP_HOTSPOT_BIT', - 'THROTTLER_TEMP_HOTSPOT_G_BIT', 'THROTTLER_TEMP_HOTSPOT_M_BIT', - 'THROTTLER_TEMP_LIQUID0_BIT', 'THROTTLER_TEMP_LIQUID1_BIT', - 'THROTTLER_TEMP_MEM_BIT', 'THROTTLER_TEMP_PLX_BIT', - 'THROTTLER_TEMP_VR_GFX_BIT', 'THROTTLER_TEMP_VR_MEM0_BIT', - 'THROTTLER_TEMP_VR_MEM1_BIT', 'THROTTLER_TEMP_VR_SOC_BIT', - 'THROTTLER_TEMP_VR_U_BIT', 'UCLK_DIV_BY_1', 'UCLK_DIV_BY_2', - 'UCLK_DIV_BY_4', 'UCLK_DIV_BY_8', 'UCLK_DIV_e', - 'UCLK_DIV_e__enumvalues', 'ULPS_SEQUENCE', 'VOLTAGE_MODE_COUNT', - 'VOLTAGE_MODE_FUSES', 'VOLTAGE_MODE_PPTABLE', 'VOLTAGE_MODE_e', - 'VOLTAGE_MODE_e__enumvalues', 'VR_MAPPING_PLANE_SELECT_MASK', - 'VR_MAPPING_PLANE_SELECT_SHIFT', 'VR_MAPPING_VR_SELECT_MASK', - 'VR_MAPPING_VR_SELECT_SHIFT', 'WATERMARKS_CLOCK_RANGE', - 'WATERMARKS_COUNT', 'WATERMARKS_DUMMY_PSTATE', - 'WATERMARKS_FLAGS_e', 'WATERMARKS_FLAGS_e__enumvalues', - 'WATERMARKS_MALL', 'WORKLOAD_PPLIB_COMPUTE_BIT', - 'WORKLOAD_PPLIB_COUNT', 'WORKLOAD_PPLIB_CUSTOM_BIT', - 'WORKLOAD_PPLIB_DEFAULT_BIT', 'WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT', - 'WORKLOAD_PPLIB_POWER_SAVING_BIT', 'WORKLOAD_PPLIB_VIDEO_BIT', - 'WORKLOAD_PPLIB_VR_BIT', 'WORKLOAD_PPLIB_WINDOW_3D_BIT', - 'WatermarkRowGeneric_t', 'WatermarksExternal_t', 'Watermarks_t', - '__AMDGPU_SMU_H__', 'bool', 'c__EA_AVFS_D_e', 'c__EA_AVFS_TEMP_e', - 'c__EA_AVFS_VOLTAGE_TYPE_e', 'c__EA_BOARD_GPIO_TYPE_e', - 'c__EA_CUSTOMER_VARIANT_e', 'c__EA_D3HOTSequence_e', - 'c__EA_DCS_ARCH_e', 'c__EA_DRAM_BIT_WIDTH_TYPE_e', - 'c__EA_FEATURE_PWR_DOMAIN_e', 'c__EA_FOPT_CALC_e', - 'c__EA_FanMode_e', 'c__EA_GpioIntPolarity_e', - 'c__EA_I2cCmdType_e', 'c__EA_I2cControllerName_e', - 'c__EA_I2cControllerPort_e', 'c__EA_I2cControllerProtocol_e', - 'c__EA_I2cControllerThrottler_e', 'c__EA_I2cPort_e', - 'c__EA_I2cSpeed_e', 'c__EA_MEM_VENDOR_e', - 'c__EA_PMFW_VOLT_PLANE_e', 'c__EA_POWER_SOURCE_e', - 'c__EA_PPCLK_e', 'c__EA_PPT_THROTTLER_e', - 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e', - 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e', 'c__EA_PP_GRTAVFS_HW_FUSE_e', - 'c__EA_PowerGatingMode_e', 'c__EA_PowerGatingSettings_e', - 'c__EA_PwrConfig_e', 'c__EA_SMARTSHIFT_VERSION_e', - 'c__EA_SVI_PLANE_e', 'c__EA_SVI_PSI_e', 'c__EA_TDC_THROTTLER_e', - 'c__EA_TEMP_e', 'c__EA_UCLK_DIV_e', 'c__EA_VOLTAGE_MODE_e', - 'c__EA_WATERMARKS_FLAGS_e', 'int16_t', 'int32_t', 'int8_t', - 'smu_clk_type', 'smu_memory_pool_size', - 'smu_perf_level_designation', 'smu_power_src_type', - 'smu_ppt_limit_level', 'smu_ppt_limit_type', - 'smu_refreshrate_source', 'smu_state_classification_flag', - 'smu_state_ui_label', 'smu_table_id', 'struct_amdgpu_bo', - 'struct_c__SA_AvfsDcBtcParams_t', - 'struct_c__SA_AvfsDebugTableExternal_t', - 'struct_c__SA_AvfsDebugTable_t', - 'struct_c__SA_AvfsFuseOverride_t', 'struct_c__SA_BoardTable_t', - 'struct_c__SA_BootValues_t', - 'struct_c__SA_DpmActivityMonitorCoeffIntExternal_t', - 'struct_c__SA_DpmActivityMonitorCoeffInt_t', - 'struct_c__SA_DpmDescriptor_t', 'struct_c__SA_DriverInfoTable_t', - 'struct_c__SA_DriverReportedClocks_t', - 'struct_c__SA_DriverSmuConfigExternal_t', - 'struct_c__SA_DriverSmuConfig_t', 'struct_c__SA_DroopInt_t', - 'struct_c__SA_EccInfoTable_t', 'struct_c__SA_EccInfo_t', - 'struct_c__SA_I2cControllerConfig_t', 'struct_c__SA_LinearInt_t', - 'struct_c__SA_MsgLimits_t', 'struct_c__SA_OverDriveLimits_t', - 'struct_c__SA_OverDriveTableExternal_t', - 'struct_c__SA_OverDriveTable_t', 'struct_c__SA_PPTable_t', - 'struct_c__SA_QuadraticInt_t', 'struct_c__SA_SkuTable_t', - 'struct_c__SA_SmuMetricsExternal_t', 'struct_c__SA_SmuMetrics_t', - 'struct_c__SA_SviTelemetryScale_t', 'struct_c__SA_SwI2cCmd_t', - 'struct_c__SA_SwI2cRequestExternal_t', - 'struct_c__SA_SwI2cRequest_t', - 'struct_c__SA_WatermarkRowGeneric_t', - 'struct_c__SA_WatermarksExternal_t', 'struct_c__SA_Watermarks_t', - 'struct_smu_bios_boot_up_values', 'struct_smu_clock_info', - 'struct_smu_hw_power_state', 'struct_smu_performance_level', - 'struct_smu_power_state', 'struct_smu_state_classification_block', - 'struct_smu_state_display_block', 'struct_smu_state_memory_block', - 'struct_smu_state_pcie_block', - 'struct_smu_state_software_algorithm_block', - 'struct_smu_state_validation_block', 'struct_smu_table', - 'struct_smu_temperature_range', 'struct_smu_user_dpm_profile', - 'struct_smu_uvd_clocks', 'u32', 'uint16_t', 'uint32_t', - 'uint64_t', 'uint8_t'] +PPSMC_VERSION = 0x1 +DEBUGSMC_VERSION = 0x1 +PPSMC_Result_OK = 0x1 +PPSMC_Result_Failed = 0xFF +PPSMC_Result_UnknownCmd = 0xFE +PPSMC_Result_CmdRejectedPrereq = 0xFD +PPSMC_Result_CmdRejectedBusy = 0xFC +PPSMC_MSG_TestMessage = 0x1 +PPSMC_MSG_GetSmuVersion = 0x2 +PPSMC_MSG_GetDriverIfVersion = 0x3 +PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 +PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 +PPSMC_MSG_EnableAllSmuFeatures = 0x6 +PPSMC_MSG_DisableAllSmuFeatures = 0x7 +PPSMC_MSG_EnableSmuFeaturesLow = 0x8 +PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 +PPSMC_MSG_DisableSmuFeaturesLow = 0xA +PPSMC_MSG_DisableSmuFeaturesHigh = 0xB +PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC +PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD +PPSMC_MSG_SetDriverDramAddrHigh = 0xE +PPSMC_MSG_SetDriverDramAddrLow = 0xF +PPSMC_MSG_SetToolsDramAddrHigh = 0x10 +PPSMC_MSG_SetToolsDramAddrLow = 0x11 +PPSMC_MSG_TransferTableSmu2Dram = 0x12 +PPSMC_MSG_TransferTableDram2Smu = 0x13 +PPSMC_MSG_UseDefaultPPTable = 0x14 +PPSMC_MSG_EnterBaco = 0x15 +PPSMC_MSG_ExitBaco = 0x16 +PPSMC_MSG_ArmD3 = 0x17 +PPSMC_MSG_BacoAudioD3PME = 0x18 +PPSMC_MSG_SetSoftMinByFreq = 0x19 +PPSMC_MSG_SetSoftMaxByFreq = 0x1A +PPSMC_MSG_SetHardMinByFreq = 0x1B +PPSMC_MSG_SetHardMaxByFreq = 0x1C +PPSMC_MSG_GetMinDpmFreq = 0x1D +PPSMC_MSG_GetMaxDpmFreq = 0x1E +PPSMC_MSG_GetDpmFreqByIndex = 0x1F +PPSMC_MSG_OverridePcieParameters = 0x20 +PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 +PPSMC_MSG_DramLogSetDramAddrLow = 0x22 +PPSMC_MSG_DramLogSetDramSize = 0x23 +PPSMC_MSG_SetWorkloadMask = 0x24 +PPSMC_MSG_GetVoltageByDpm = 0x25 +PPSMC_MSG_SetVideoFps = 0x26 +PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 +PPSMC_MSG_AllowGfxOff = 0x28 +PPSMC_MSG_DisallowGfxOff = 0x29 +PPSMC_MSG_PowerUpVcn = 0x2A +PPSMC_MSG_PowerDownVcn = 0x2B +PPSMC_MSG_PowerUpJpeg = 0x2C +PPSMC_MSG_PowerDownJpeg = 0x2D +PPSMC_MSG_PrepareMp1ForUnload = 0x2E +PPSMC_MSG_Mode1Reset = 0x2F +PPSMC_MSG_Mode2Reset = 0x4F +PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 +PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 +PPSMC_MSG_SetPptLimit = 0x32 +PPSMC_MSG_GetPptLimit = 0x33 +PPSMC_MSG_ReenableAcDcInterrupt = 0x34 +PPSMC_MSG_NotifyPowerSource = 0x35 +PPSMC_MSG_RunDcBtc = 0x36 +PPSMC_MSG_GetDebugData = 0x37 +PPSMC_MSG_SetTemperatureInputSelect = 0x38 +PPSMC_MSG_SetFwDstatesMask = 0x39 +PPSMC_MSG_SetThrottlerMask = 0x3A +PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B +PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C +PPSMC_MSG_DumpSTBtoDram = 0x3D +PPSMC_MSG_STBtoDramLogSetDramAddrHigh = 0x3E +PPSMC_MSG_STBtoDramLogSetDramAddrLow = 0x3F +PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 +PPSMC_MSG_SetGpoAllow = 0x41 +PPSMC_MSG_AllowGfxDcs = 0x42 +PPSMC_MSG_DisallowGfxDcs = 0x43 +PPSMC_MSG_EnableAudioStutterWA = 0x44 +PPSMC_MSG_PowerUpUmsch = 0x45 +PPSMC_MSG_PowerDownUmsch = 0x46 +PPSMC_MSG_SetDcsArch = 0x47 +PPSMC_MSG_TriggerVFFLR = 0x48 +PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x49 +PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4A +PPSMC_MSG_SetPriorityDeltaGain = 0x4B +PPSMC_MSG_AllowIHHostInterrupt = 0x4C +PPSMC_MSG_DALNotPresent = 0x4E +PPSMC_MSG_EnableUCLKShadow = 0x51 +PPSMC_Message_Count = 0x52 +DEBUGSMC_MSG_TestMessage = 0x1 +DEBUGSMC_MSG_GetDebugData = 0x2 +DEBUGSMC_MSG_DebugDumpExit = 0x3 +DEBUGSMC_Message_Count = 0x4 +SMU13_0_0_DRIVER_IF_VERSION = 0x3D +PPTABLE_VERSION = 0x2B +NUM_GFXCLK_DPM_LEVELS = 16 +NUM_SOCCLK_DPM_LEVELS = 8 +NUM_MP0CLK_DPM_LEVELS = 2 +NUM_DCLK_DPM_LEVELS = 8 +NUM_VCLK_DPM_LEVELS = 8 +NUM_DISPCLK_DPM_LEVELS = 8 +NUM_DPPCLK_DPM_LEVELS = 8 +NUM_DPREFCLK_DPM_LEVELS = 8 +NUM_DCFCLK_DPM_LEVELS = 8 +NUM_DTBCLK_DPM_LEVELS = 8 +NUM_UCLK_DPM_LEVELS = 4 +NUM_LINK_LEVELS = 3 +NUM_FCLK_DPM_LEVELS = 8 +NUM_OD_FAN_MAX_POINTS = 6 +FEATURE_FW_DATA_READ_BIT = 0 +FEATURE_DPM_GFXCLK_BIT = 1 +FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 +FEATURE_DPM_UCLK_BIT = 3 +FEATURE_DPM_FCLK_BIT = 4 +FEATURE_DPM_SOCCLK_BIT = 5 +FEATURE_DPM_MP0CLK_BIT = 6 +FEATURE_DPM_LINK_BIT = 7 +FEATURE_DPM_DCN_BIT = 8 +FEATURE_VMEMP_SCALING_BIT = 9 +FEATURE_VDDIO_MEM_SCALING_BIT = 10 +FEATURE_DS_GFXCLK_BIT = 11 +FEATURE_DS_SOCCLK_BIT = 12 +FEATURE_DS_FCLK_BIT = 13 +FEATURE_DS_LCLK_BIT = 14 +FEATURE_DS_DCFCLK_BIT = 15 +FEATURE_DS_UCLK_BIT = 16 +FEATURE_GFX_ULV_BIT = 17 +FEATURE_FW_DSTATE_BIT = 18 +FEATURE_GFXOFF_BIT = 19 +FEATURE_BACO_BIT = 20 +FEATURE_MM_DPM_BIT = 21 +FEATURE_SOC_MPCLK_DS_BIT = 22 +FEATURE_BACO_MPCLK_DS_BIT = 23 +FEATURE_THROTTLERS_BIT = 24 +FEATURE_SMARTSHIFT_BIT = 25 +FEATURE_GTHR_BIT = 26 +FEATURE_ACDC_BIT = 27 +FEATURE_VR0HOT_BIT = 28 +FEATURE_FW_CTF_BIT = 29 +FEATURE_FAN_CONTROL_BIT = 30 +FEATURE_GFX_DCS_BIT = 31 +FEATURE_GFX_READ_MARGIN_BIT = 32 +FEATURE_LED_DISPLAY_BIT = 33 +FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 34 +FEATURE_OUT_OF_BAND_MONITOR_BIT = 35 +FEATURE_OPTIMIZED_VMIN_BIT = 36 +FEATURE_GFX_IMU_BIT = 37 +FEATURE_BOOT_TIME_CAL_BIT = 38 +FEATURE_GFX_PCC_DFLL_BIT = 39 +FEATURE_SOC_CG_BIT = 40 +FEATURE_DF_CSTATE_BIT = 41 +FEATURE_GFX_EDC_BIT = 42 +FEATURE_BOOT_POWER_OPT_BIT = 43 +FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 44 +FEATURE_DS_VCN_BIT = 45 +FEATURE_BACO_CG_BIT = 46 +FEATURE_MEM_TEMP_READ_BIT = 47 +FEATURE_ATHUB_MMHUB_PG_BIT = 48 +FEATURE_SOC_PCC_BIT = 49 +FEATURE_EDC_PWRBRK_BIT = 50 +FEATURE_BOMXCO_SVI3_PROG_BIT = 51 +FEATURE_SPARE_52_BIT = 52 +FEATURE_SPARE_53_BIT = 53 +FEATURE_SPARE_54_BIT = 54 +FEATURE_SPARE_55_BIT = 55 +FEATURE_SPARE_56_BIT = 56 +FEATURE_SPARE_57_BIT = 57 +FEATURE_SPARE_58_BIT = 58 +FEATURE_SPARE_59_BIT = 59 +FEATURE_SPARE_60_BIT = 60 +FEATURE_SPARE_61_BIT = 61 +FEATURE_SPARE_62_BIT = 62 +FEATURE_SPARE_63_BIT = 63 +NUM_FEATURES = 64 +ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF +ALLOWED_FEATURE_CTRL_SCPM = ((1 << FEATURE_DPM_GFXCLK_BIT) | (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | (1 << FEATURE_DPM_UCLK_BIT) | (1 << FEATURE_DPM_FCLK_BIT) | (1 << FEATURE_DPM_SOCCLK_BIT) | (1 << FEATURE_DPM_MP0CLK_BIT) | (1 << FEATURE_DPM_LINK_BIT) | (1 << FEATURE_DPM_DCN_BIT) | (1 << FEATURE_DS_GFXCLK_BIT) | (1 << FEATURE_DS_SOCCLK_BIT) | (1 << FEATURE_DS_FCLK_BIT) | (1 << FEATURE_DS_LCLK_BIT) | (1 << FEATURE_DS_DCFCLK_BIT) | (1 << FEATURE_DS_UCLK_BIT) | (1 << FEATURE_DS_VCN_BIT)) +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK = 0x00000001 +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 +DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 +DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 +DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 +DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 +DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 +DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 +DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 +DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 +DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 +VR_MAPPING_VR_SELECT_MASK = 0x01 +VR_MAPPING_VR_SELECT_SHIFT = 0x00 +VR_MAPPING_PLANE_SELECT_MASK = 0x02 +VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 +PSI_SEL_VR0_PLANE0_PSI0 = 0x01 +PSI_SEL_VR0_PLANE0_PSI1 = 0x02 +PSI_SEL_VR0_PLANE1_PSI0 = 0x04 +PSI_SEL_VR0_PLANE1_PSI1 = 0x08 +PSI_SEL_VR1_PLANE0_PSI0 = 0x10 +PSI_SEL_VR1_PLANE0_PSI1 = 0x20 +PSI_SEL_VR1_PLANE1_PSI0 = 0x40 +PSI_SEL_VR1_PLANE1_PSI1 = 0x80 +THROTTLER_TEMP_EDGE_BIT = 0 +THROTTLER_TEMP_HOTSPOT_BIT = 1 +THROTTLER_TEMP_HOTSPOT_G_BIT = 2 +THROTTLER_TEMP_HOTSPOT_M_BIT = 3 +THROTTLER_TEMP_MEM_BIT = 4 +THROTTLER_TEMP_VR_GFX_BIT = 5 +THROTTLER_TEMP_VR_MEM0_BIT = 6 +THROTTLER_TEMP_VR_MEM1_BIT = 7 +THROTTLER_TEMP_VR_SOC_BIT = 8 +THROTTLER_TEMP_VR_U_BIT = 9 +THROTTLER_TEMP_LIQUID0_BIT = 10 +THROTTLER_TEMP_LIQUID1_BIT = 11 +THROTTLER_TEMP_PLX_BIT = 12 +THROTTLER_TDC_GFX_BIT = 13 +THROTTLER_TDC_SOC_BIT = 14 +THROTTLER_TDC_U_BIT = 15 +THROTTLER_PPT0_BIT = 16 +THROTTLER_PPT1_BIT = 17 +THROTTLER_PPT2_BIT = 18 +THROTTLER_PPT3_BIT = 19 +THROTTLER_FIT_BIT = 20 +THROTTLER_GFX_APCC_PLUS_BIT = 21 +THROTTLER_COUNT = 22 +FW_DSTATE_SOC_ULV_BIT = 0 +FW_DSTATE_G6_HSR_BIT = 1 +FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 +FW_DSTATE_SMN_DS_BIT = 3 +FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 +FW_DSTATE_SOC_LIV_MIN_BIT = 5 +FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 +FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 +FW_DSTATE_MALL_ALLOC_BIT = 8 +FW_DSTATE_MEM_PSI_BIT = 9 +FW_DSTATE_HSR_NON_STROBE_BIT = 10 +FW_DSTATE_MP0_ENTER_WFI_BIT = 11 +FW_DSTATE_U_ULV_BIT = 12 +FW_DSTATE_MALL_FLUSH_BIT = 13 +FW_DSTATE_SOC_PSI_BIT = 14 +FW_DSTATE_U_PSI_BIT = 15 +FW_DSTATE_UCP_DS_BIT = 16 +FW_DSTATE_CSRCLK_DS_BIT = 17 +FW_DSTATE_MMHUB_INTERLOCK_BIT = 18 +FW_DSTATE_D0i3_2_QUIET_FW_BIT = 19 +FW_DSTATE_CLDO_PRG_BIT = 20 +FW_DSTATE_DF_PLL_PWRDN_BIT = 21 +FW_DSTATE_U_LOW_PWR_MODE_EN_BIT = 22 +FW_DSTATE_GFX_PSI6_BIT = 23 +FW_DSTATE_GFX_VR_PWR_STAGE_BIT = 24 +LED_DISPLAY_GFX_DPM_BIT = 0 +LED_DISPLAY_PCIE_BIT = 1 +LED_DISPLAY_ERROR_BIT = 2 +MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 +MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 +MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 +NUM_I2C_CONTROLLERS = 8 +I2C_CONTROLLER_ENABLED = 1 +I2C_CONTROLLER_DISABLED = 0 +MAX_SW_I2C_COMMANDS = 24 +CMDCONFIG_STOP_BIT = 0 +CMDCONFIG_RESTART_BIT = 1 +CMDCONFIG_READWRITE_BIT = 2 +CMDCONFIG_STOP_MASK = (1 << CMDCONFIG_STOP_BIT) +CMDCONFIG_RESTART_MASK = (1 << CMDCONFIG_RESTART_BIT) +CMDCONFIG_READWRITE_MASK = (1 << CMDCONFIG_READWRITE_BIT) +PP_NUM_RTAVFS_PWL_ZONES = 5 +PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 +PP_OD_FEATURE_PPT_BIT = 2 +PP_OD_FEATURE_FAN_CURVE_BIT = 3 +PP_OD_FEATURE_GFXCLK_BIT = 7 +PP_OD_FEATURE_UCLK_BIT = 8 +PP_OD_FEATURE_ZERO_FAN_BIT = 9 +PP_OD_FEATURE_TEMPERATURE_BIT = 10 +PP_OD_FEATURE_COUNT = 13 +PP_NUM_OD_VF_CURVE_POINTS = PP_NUM_RTAVFS_PWL_ZONES + 1 +INVALID_BOARD_GPIO = 0xFF +MARKETING_BASE_CLOCKS = 0 +MARKETING_GAME_CLOCKS = 1 +MARKETING_BOOST_CLOCKS = 2 +NUM_WM_RANGES = 4 +WORKLOAD_PPLIB_DEFAULT_BIT = 0 +WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 +WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 +WORKLOAD_PPLIB_VIDEO_BIT = 3 +WORKLOAD_PPLIB_VR_BIT = 4 +WORKLOAD_PPLIB_COMPUTE_BIT = 5 +WORKLOAD_PPLIB_CUSTOM_BIT = 6 +WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 +WORKLOAD_PPLIB_COUNT = 8 +TABLE_TRANSFER_OK = 0x0 +TABLE_TRANSFER_FAILED = 0xFF +TABLE_TRANSFER_PENDING = 0xAB +TABLE_PPTABLE = 0 +TABLE_COMBO_PPTABLE = 1 +TABLE_WATERMARKS = 2 +TABLE_AVFS_PSM_DEBUG = 3 +TABLE_PMSTATUSLOG = 4 +TABLE_SMU_METRICS = 5 +TABLE_DRIVER_SMU_CONFIG = 6 +TABLE_ACTIVITY_MONITOR_COEFF = 7 +TABLE_OVERDRIVE = 8 +TABLE_I2C_COMMANDS = 9 +TABLE_DRIVER_INFO = 10 +TABLE_ECCINFO = 11 +TABLE_WIFIBAND = 12 +TABLE_COUNT = 13 +IH_INTERRUPT_ID_TO_DRIVER = 0xFE +IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 +IH_INTERRUPT_CONTEXT_ID_AC = 0x3 +IH_INTERRUPT_CONTEXT_ID_DC = 0x4 +IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 +IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 +IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 +IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 +IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 +int32_t = int +SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 +SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 +SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 +SMU_FW_NAME_LEN = 0x24 +SMU_DPM_USER_PROFILE_RESTORE = (1 << 0) +SMU_CUSTOM_FAN_SPEED_RPM = (1 << 1) +SMU_CUSTOM_FAN_SPEED_PWM = (1 << 2) +SMU_THROTTLER_PPT0_BIT = 0 +SMU_THROTTLER_PPT1_BIT = 1 +SMU_THROTTLER_PPT2_BIT = 2 +SMU_THROTTLER_PPT3_BIT = 3 +SMU_THROTTLER_SPL_BIT = 4 +SMU_THROTTLER_FPPT_BIT = 5 +SMU_THROTTLER_SPPT_BIT = 6 +SMU_THROTTLER_SPPT_APU_BIT = 7 +SMU_THROTTLER_TDC_GFX_BIT = 16 +SMU_THROTTLER_TDC_SOC_BIT = 17 +SMU_THROTTLER_TDC_MEM_BIT = 18 +SMU_THROTTLER_TDC_VDD_BIT = 19 +SMU_THROTTLER_TDC_CVIP_BIT = 20 +SMU_THROTTLER_EDC_CPU_BIT = 21 +SMU_THROTTLER_EDC_GFX_BIT = 22 +SMU_THROTTLER_APCC_BIT = 23 +SMU_THROTTLER_TEMP_GPU_BIT = 32 +SMU_THROTTLER_TEMP_CORE_BIT = 33 +SMU_THROTTLER_TEMP_MEM_BIT = 34 +SMU_THROTTLER_TEMP_EDGE_BIT = 35 +SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 +SMU_THROTTLER_TEMP_SOC_BIT = 37 +SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 +SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 +SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 +SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 +SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 +SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 +SMU_THROTTLER_VRHOT0_BIT = 44 +SMU_THROTTLER_VRHOT1_BIT = 45 +SMU_THROTTLER_PROCHOT_CPU_BIT = 46 +SMU_THROTTLER_PROCHOT_GFX_BIT = 47 +SMU_THROTTLER_PPM_BIT = 56 +SMU_THROTTLER_FIT_BIT = 57 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/smu_v14_0_2.py b/tinygrad/runtime/autogen/am/smu_v14_0_2.py index 4d3cc93966..751c7e6834 100644 --- a/tinygrad/runtime/autogen/am/smu_v14_0_2.py +++ b/tinygrad/runtime/autogen/am/smu_v14_0_2.py @@ -1,3607 +1,1984 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-include', 'stdint.h'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -__SMU_V14_0_0_PMFW_H__ = True # macro -ENABLE_DEBUG_FEATURES = True # macro -FEATURE_CCLK_DPM_BIT = 0 # macro -FEATURE_FAN_CONTROLLER_BIT = 1 # macro -FEATURE_DATA_CALCULATION_BIT = 2 # macro -FEATURE_PPT_BIT = 3 # macro -FEATURE_TDC_BIT = 4 # macro -FEATURE_THERMAL_BIT = 5 # macro -FEATURE_FIT_BIT = 6 # macro -FEATURE_EDC_BIT = 7 # macro -FEATURE_PLL_POWER_DOWN_BIT = 8 # macro -FEATURE_VDDOFF_BIT = 9 # macro -FEATURE_VCN_DPM_BIT = 10 # macro -FEATURE_DS_MPM_BIT = 11 # macro -FEATURE_FCLK_DPM_BIT = 12 # macro -FEATURE_SOCCLK_DPM_BIT = 13 # macro -FEATURE_DS_MPIO_BIT = 14 # macro -FEATURE_LCLK_DPM_BIT = 15 # macro -FEATURE_SHUBCLK_DPM_BIT = 16 # macro -FEATURE_DCFCLK_DPM_BIT = 17 # macro -FEATURE_ISP_DPM_BIT = 18 # macro -FEATURE_IPU_DPM_BIT = 19 # macro -FEATURE_GFX_DPM_BIT = 20 # macro -FEATURE_DS_GFXCLK_BIT = 10 # macro -FEATURE_DS_SOCCLK_BIT = 11 # macro -FEATURE_DS_LCLK_BIT = 13 # macro -FEATURE_LOW_POWER_DCNCLKS_BIT = 24 # macro -FEATURE_DS_SHUBCLK_BIT = 25 # macro -FEATURE_RESERVED0_BIT = 26 # macro -FEATURE_ZSTATES_BIT = 27 # macro -FEATURE_IOMMUL2_PG_BIT = 28 # macro -FEATURE_DS_FCLK_BIT = 12 # macro -FEATURE_DS_SMNCLK_BIT = 30 # macro -FEATURE_DS_MP1CLK_BIT = 31 # macro -FEATURE_WHISPER_MODE_BIT = 32 # macro -FEATURE_SMU_LOW_POWER_BIT = 33 # macro -FEATURE_RESERVED1_BIT = 34 # macro -FEATURE_GFX_DEM_BIT = 35 # macro -FEATURE_PSI_BIT = 36 # macro -FEATURE_PROCHOT_BIT = 37 # macro -FEATURE_CPUOFF_BIT = 38 # macro -FEATURE_STAPM_BIT = 39 # macro -FEATURE_S0I3_BIT = 40 # macro -FEATURE_DF_LIGHT_CSTATE = 41 # macro -FEATURE_PERF_LIMIT_BIT = 42 # macro -FEATURE_CORE_DLDO_BIT = 43 # macro -FEATURE_DVO_BIT = 44 # macro -FEATURE_DS_VCN_BIT = 44 # macro -FEATURE_CPPC_BIT = 46 # macro -FEATURE_CPPC_PREFERRED_CORES = 47 # macro -FEATURE_DF_CSTATES_BIT = 48 # macro -FEATURE_FAST_PSTATE_CLDO_BIT = 49 # macro -FEATURE_ATHUB_PG_BIT = 50 # macro -FEATURE_VDDOFF_ECO_BIT = 51 # macro -FEATURE_ZSTATES_ECO_BIT = 52 # macro -FEATURE_CC6_BIT = 53 # macro -FEATURE_DS_UMCCLK_BIT = 54 # macro -FEATURE_DS_ISPCLK_BIT = 55 # macro -FEATURE_DS_HSPCLK_BIT = 56 # macro -FEATURE_P3T_BIT = 57 # macro -FEATURE_DS_IPUCLK_BIT = 58 # macro -FEATURE_DS_VPECLK_BIT = 59 # macro -FEATURE_VPE_DPM_BIT = 60 # macro -FEATURE_SMART_L3_RINSER_BIT = 61 # macro -FEATURE_PCC_BIT = 62 # macro -NUM_FEATURES = 64 # macro -class struct_SMU14_Firmware_Footer(Structure): - pass - -struct_SMU14_Firmware_Footer._pack_ = 1 # source:False +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class struct_SMU14_Firmware_Footer(Struct): pass +uint32_t = ctypes.c_uint32 +struct_SMU14_Firmware_Footer._packed_ = True struct_SMU14_Firmware_Footer._fields_ = [ - ('Signature', ctypes.c_uint32), + ('Signature', uint32_t), ] - SMU14_Firmware_Footer = struct_SMU14_Firmware_Footer -class struct_c__SA_SMU_Firmware_Header(Structure): - pass - -struct_c__SA_SMU_Firmware_Header._pack_ = 1 # source:False -struct_c__SA_SMU_Firmware_Header._fields_ = [ - ('ImageVersion', ctypes.c_uint32), - ('ImageVersion2', ctypes.c_uint32), - ('Padding0', ctypes.c_uint32 * 3), - ('SizeFWSigned', ctypes.c_uint32), - ('Padding1', ctypes.c_uint32 * 25), - ('FirmwareType', ctypes.c_uint32), - ('Filler', ctypes.c_uint32 * 32), +class SMU_Firmware_Header(Struct): pass +SMU_Firmware_Header._packed_ = True +SMU_Firmware_Header._fields_ = [ + ('ImageVersion', uint32_t), + ('ImageVersion2', uint32_t), + ('Padding0', (uint32_t * 3)), + ('SizeFWSigned', uint32_t), + ('Padding1', (uint32_t * 25)), + ('FirmwareType', uint32_t), + ('Filler', (uint32_t * 32)), ] - -SMU_Firmware_Header = struct_c__SA_SMU_Firmware_Header -class struct_c__SA_FwStatus_t(Structure): - pass - -struct_c__SA_FwStatus_t._pack_ = 1 # source:False -struct_c__SA_FwStatus_t._fields_ = [ - ('DpmHandlerID', ctypes.c_uint64, 8), - ('ActivityMonitorID', ctypes.c_uint64, 8), - ('DpmTimerID', ctypes.c_uint64, 8), - ('DpmHubID', ctypes.c_uint64, 4), - ('DpmHubTask', ctypes.c_uint64, 4), - ('CclkSyncStatus', ctypes.c_uint64, 8), - ('Ccx0CpuOff', ctypes.c_uint64, 2), - ('Ccx1CpuOff', ctypes.c_uint64, 2), - ('GfxOffStatus', ctypes.c_uint64, 2), - ('VddOff', ctypes.c_uint64, 1), - ('InWhisperMode', ctypes.c_uint64, 1), - ('ZstateStatus', ctypes.c_uint64, 4), - ('spare0', ctypes.c_uint64, 4), - ('DstateFun', ctypes.c_uint64, 4), - ('DstateDev', ctypes.c_uint64, 4), - ('P2JobHandler', ctypes.c_uint64, 24), - ('RsmuPmiP2PendingCnt', ctypes.c_uint64, 8), - ('PostCode', ctypes.c_uint64, 32), - ('MsgPortBusy', ctypes.c_uint64, 24), - ('RsmuPmiP1Pending', ctypes.c_uint64, 1), - ('DfCstateExitPending', ctypes.c_uint64, 1), - ('Ccx0Pc6ExitPending', ctypes.c_uint64, 1), - ('Ccx1Pc6ExitPending', ctypes.c_uint64, 1), - ('WarmResetPending', ctypes.c_uint64, 1), - ('spare1', ctypes.c_uint64, 3), - ('IdleMask', ctypes.c_uint64, 32), +class FwStatus_t(Struct): pass +FwStatus_t._packed_ = True +FwStatus_t._fields_ = [ + ('DpmHandlerID', uint32_t,8), + ('ActivityMonitorID', uint32_t,8), + ('DpmTimerID', uint32_t,8), + ('DpmHubID', uint32_t,4), + ('DpmHubTask', uint32_t,4), + ('CclkSyncStatus', uint32_t,8), + ('Ccx0CpuOff', uint32_t,2), + ('Ccx1CpuOff', uint32_t,2), + ('GfxOffStatus', uint32_t,2), + ('VddOff', uint32_t,1), + ('InWhisperMode', uint32_t,1), + ('ZstateStatus', uint32_t,4), + ('spare0', uint32_t,4), + ('DstateFun', uint32_t,4), + ('DstateDev', uint32_t,4), + ('P2JobHandler', uint32_t,24), + ('RsmuPmiP2PendingCnt', uint32_t,8), + ('PostCode', uint32_t,32), + ('MsgPortBusy', uint32_t,24), + ('RsmuPmiP1Pending', uint32_t,1), + ('DfCstateExitPending', uint32_t,1), + ('Ccx0Pc6ExitPending', uint32_t,1), + ('Ccx1Pc6ExitPending', uint32_t,1), + ('WarmResetPending', uint32_t,1), + ('spare1', uint32_t,3), + ('IdleMask', uint32_t,32), ] - -FwStatus_t = struct_c__SA_FwStatus_t -class struct_c__SA_FwStatus_t_v14_0_1(Structure): - pass - -struct_c__SA_FwStatus_t_v14_0_1._pack_ = 1 # source:False -struct_c__SA_FwStatus_t_v14_0_1._fields_ = [ - ('DpmHandlerID', ctypes.c_uint64, 8), - ('ActivityMonitorID', ctypes.c_uint64, 8), - ('DpmTimerID', ctypes.c_uint64, 8), - ('DpmHubID', ctypes.c_uint64, 4), - ('DpmHubTask', ctypes.c_uint64, 4), - ('CclkSyncStatus', ctypes.c_uint64, 8), - ('ZstateStatus', ctypes.c_uint64, 4), - ('Cpu1VddOff', ctypes.c_uint64, 4), - ('DstateFun', ctypes.c_uint64, 4), - ('DstateDev', ctypes.c_uint64, 4), - ('GfxOffStatus', ctypes.c_uint64, 2), - ('Cpu0Off', ctypes.c_uint64, 2), - ('Cpu1Off', ctypes.c_uint64, 2), - ('Cpu0VddOff', ctypes.c_uint64, 2), - ('P2JobHandler', ctypes.c_uint64, 32), - ('PostCode', ctypes.c_uint64, 32), - ('MsgPortBusy', ctypes.c_uint64, 15), - ('RsmuPmiP1Pending', ctypes.c_uint64, 1), - ('RsmuPmiP2PendingCnt', ctypes.c_uint64, 8), - ('DfCstateExitPending', ctypes.c_uint64, 1), - ('Pc6EntryPending', ctypes.c_uint64, 1), - ('Pc6ExitPending', ctypes.c_uint64, 1), - ('WarmResetPending', ctypes.c_uint64, 1), - ('Mp0ClkPending', ctypes.c_uint64, 1), - ('InWhisperMode', ctypes.c_uint64, 1), - ('spare2', ctypes.c_uint64, 2), - ('IdleMask', ctypes.c_uint64, 32), +class FwStatus_t_v14_0_1(Struct): pass +FwStatus_t_v14_0_1._packed_ = True +FwStatus_t_v14_0_1._fields_ = [ + ('DpmHandlerID', uint32_t,8), + ('ActivityMonitorID', uint32_t,8), + ('DpmTimerID', uint32_t,8), + ('DpmHubID', uint32_t,4), + ('DpmHubTask', uint32_t,4), + ('CclkSyncStatus', uint32_t,8), + ('ZstateStatus', uint32_t,4), + ('Cpu1VddOff', uint32_t,4), + ('DstateFun', uint32_t,4), + ('DstateDev', uint32_t,4), + ('GfxOffStatus', uint32_t,2), + ('Cpu0Off', uint32_t,2), + ('Cpu1Off', uint32_t,2), + ('Cpu0VddOff', uint32_t,2), + ('P2JobHandler', uint32_t,32), + ('PostCode', uint32_t,32), + ('MsgPortBusy', uint32_t,15), + ('RsmuPmiP1Pending', uint32_t,1), + ('RsmuPmiP2PendingCnt', uint32_t,8), + ('DfCstateExitPending', uint32_t,1), + ('Pc6EntryPending', uint32_t,1), + ('Pc6ExitPending', uint32_t,1), + ('WarmResetPending', uint32_t,1), + ('Mp0ClkPending', uint32_t,1), + ('InWhisperMode', uint32_t,1), + ('spare2', uint32_t,2), + ('IdleMask', uint32_t,32), ] +FEATURE_PWR_DOMAIN_e = CEnum(ctypes.c_uint32) +FEATURE_PWR_ALL = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_ALL', 0) +FEATURE_PWR_S5 = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_S5', 1) +FEATURE_PWR_BACO = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_BACO', 2) +FEATURE_PWR_SOC = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_SOC', 3) +FEATURE_PWR_GFX = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_GFX', 4) +FEATURE_PWR_DOMAIN_COUNT = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_DOMAIN_COUNT', 5) -FwStatus_t_v14_0_1 = struct_c__SA_FwStatus_t_v14_0_1 -SMU_V14_0_2_PPSMC_H = True # macro -PPSMC_VERSION = 0x1 # macro -PPSMC_Result_OK = 0x1 # macro -PPSMC_Result_Failed = 0xFF # macro -PPSMC_Result_UnknownCmd = 0xFE # macro -PPSMC_Result_CmdRejectedPrereq = 0xFD # macro -PPSMC_Result_CmdRejectedBusy = 0xFC # macro -PPSMC_MSG_TestMessage = 0x1 # macro -PPSMC_MSG_GetSmuVersion = 0x2 # macro -PPSMC_MSG_GetDriverIfVersion = 0x3 # macro -PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 # macro -PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 # macro -PPSMC_MSG_EnableAllSmuFeatures = 0x6 # macro -PPSMC_MSG_DisableAllSmuFeatures = 0x7 # macro -PPSMC_MSG_EnableSmuFeaturesLow = 0x8 # macro -PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 # macro -PPSMC_MSG_DisableSmuFeaturesLow = 0xA # macro -PPSMC_MSG_DisableSmuFeaturesHigh = 0xB # macro -PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC # macro -PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD # macro -PPSMC_MSG_SetDriverDramAddrHigh = 0xE # macro -PPSMC_MSG_SetDriverDramAddrLow = 0xF # macro -PPSMC_MSG_SetToolsDramAddrHigh = 0x10 # macro -PPSMC_MSG_SetToolsDramAddrLow = 0x11 # macro -PPSMC_MSG_TransferTableSmu2Dram = 0x12 # macro -PPSMC_MSG_TransferTableDram2Smu = 0x13 # macro -PPSMC_MSG_UseDefaultPPTable = 0x14 # macro -PPSMC_MSG_EnterBaco = 0x15 # macro -PPSMC_MSG_ExitBaco = 0x16 # macro -PPSMC_MSG_ArmD3 = 0x17 # macro -PPSMC_MSG_BacoAudioD3PME = 0x18 # macro -PPSMC_MSG_SetSoftMinByFreq = 0x19 # macro -PPSMC_MSG_SetSoftMaxByFreq = 0x1A # macro -PPSMC_MSG_SetHardMinByFreq = 0x1B # macro -PPSMC_MSG_SetHardMaxByFreq = 0x1C # macro -PPSMC_MSG_GetMinDpmFreq = 0x1D # macro -PPSMC_MSG_GetMaxDpmFreq = 0x1E # macro -PPSMC_MSG_GetDpmFreqByIndex = 0x1F # macro -PPSMC_MSG_OverridePcieParameters = 0x20 # macro -PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 # macro -PPSMC_MSG_DramLogSetDramAddrLow = 0x22 # macro -PPSMC_MSG_DramLogSetDramSize = 0x23 # macro -PPSMC_MSG_SetWorkloadMask = 0x24 # macro -PPSMC_MSG_GetVoltageByDpm = 0x25 # macro -PPSMC_MSG_SetVideoFps = 0x26 # macro -PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 # macro -PPSMC_MSG_AllowGfxOff = 0x28 # macro -PPSMC_MSG_DisallowGfxOff = 0x29 # macro -PPSMC_MSG_PowerUpVcn = 0x2A # macro -PPSMC_MSG_PowerDownVcn = 0x2B # macro -PPSMC_MSG_PowerUpJpeg = 0x2C # macro -PPSMC_MSG_PowerDownJpeg = 0x2D # macro -PPSMC_MSG_PrepareMp1ForUnload = 0x2E # macro -PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 # macro -PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 # macro -PPSMC_MSG_SetPptLimit = 0x32 # macro -PPSMC_MSG_GetPptLimit = 0x33 # macro -PPSMC_MSG_ReenableAcDcInterrupt = 0x34 # macro -PPSMC_MSG_NotifyPowerSource = 0x35 # macro -PPSMC_MSG_RunDcBtc = 0x36 # macro -PPSMC_MSG_SetTemperatureInputSelect = 0x38 # macro -PPSMC_MSG_SetFwDstatesMask = 0x39 # macro -PPSMC_MSG_SetThrottlerMask = 0x3A # macro -PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B # macro -PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C # macro -PPSMC_MSG_DumpSTBtoDram = 0x3D # macro -PPSMC_MSG_STBtoDramLogSetDramAddress = 0x3E # macro -PPSMC_MSG_DummyUndefined = 0x3F # macro -PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 # macro -PPSMC_MSG_SetOBMTraceBufferLogging = 0x41 # macro -PPSMC_MSG_UseProfilingMode = 0x42 # macro -PPSMC_MSG_AllowGfxDcs = 0x43 # macro -PPSMC_MSG_DisallowGfxDcs = 0x44 # macro -PPSMC_MSG_EnableAudioStutterWA = 0x45 # macro -PPSMC_MSG_PowerUpUmsch = 0x46 # macro -PPSMC_MSG_PowerDownUmsch = 0x47 # macro -PPSMC_MSG_SetDcsArch = 0x48 # macro -PPSMC_MSG_TriggerVFFLR = 0x49 # macro -PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x4A # macro -PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4B # macro -PPSMC_MSG_SetPriorityDeltaGain = 0x4C # macro -PPSMC_MSG_AllowIHHostInterrupt = 0x4D # macro -PPSMC_MSG_EnableShadowDpm = 0x4E # macro -PPSMC_MSG_Mode3Reset = 0x4F # macro -PPSMC_MSG_SetDriverDramAddr = 0x50 # macro -PPSMC_MSG_SetToolsDramAddr = 0x51 # macro -PPSMC_MSG_TransferTableSmu2DramWithAddr = 0x52 # macro -PPSMC_MSG_TransferTableDram2SmuWithAddr = 0x53 # macro -PPSMC_MSG_GetAllRunningSmuFeatures = 0x54 # macro -PPSMC_MSG_GetSvi3Voltage = 0x55 # macro -PPSMC_MSG_UpdatePolicy = 0x56 # macro -PPSMC_MSG_ExtPwrConnSupport = 0x57 # macro -PPSMC_MSG_PreloadSwPstateForUclkOverDrive = 0x58 # macro -PPSMC_Message_Count = 0x59 # macro -SMU14_DRIVER_IF_V14_0_H = True # macro -PPTABLE_VERSION = 0x1B # macro -NUM_GFXCLK_DPM_LEVELS = 16 # macro -NUM_SOCCLK_DPM_LEVELS = 8 # macro -NUM_MP0CLK_DPM_LEVELS = 2 # macro -NUM_DCLK_DPM_LEVELS = 8 # macro -NUM_VCLK_DPM_LEVELS = 8 # macro -NUM_DISPCLK_DPM_LEVELS = 8 # macro -NUM_DPPCLK_DPM_LEVELS = 8 # macro -NUM_DPREFCLK_DPM_LEVELS = 8 # macro -NUM_DCFCLK_DPM_LEVELS = 8 # macro -NUM_DTBCLK_DPM_LEVELS = 8 # macro -NUM_UCLK_DPM_LEVELS = 6 # macro -NUM_LINK_LEVELS = 3 # macro -NUM_FCLK_DPM_LEVELS = 8 # macro -NUM_OD_FAN_MAX_POINTS = 6 # macro -FEATURE_FW_DATA_READ_BIT = 0 # macro -FEATURE_DPM_GFXCLK_BIT = 1 # macro -FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 # macro -FEATURE_DPM_UCLK_BIT = 3 # macro -FEATURE_DPM_FCLK_BIT = 4 # macro -FEATURE_DPM_SOCCLK_BIT = 5 # macro -FEATURE_DPM_LINK_BIT = 6 # macro -FEATURE_DPM_DCN_BIT = 7 # macro -FEATURE_VMEMP_SCALING_BIT = 8 # macro -FEATURE_VDDIO_MEM_SCALING_BIT = 9 # macro -FEATURE_DS_DCFCLK_BIT = 14 # macro -FEATURE_DS_UCLK_BIT = 15 # macro -FEATURE_GFX_ULV_BIT = 16 # macro -FEATURE_FW_DSTATE_BIT = 17 # macro -FEATURE_GFXOFF_BIT = 18 # macro -FEATURE_BACO_BIT = 19 # macro -FEATURE_MM_DPM_BIT = 20 # macro -FEATURE_SOC_MPCLK_DS_BIT = 21 # macro -FEATURE_BACO_MPCLK_DS_BIT = 22 # macro -FEATURE_THROTTLERS_BIT = 23 # macro -FEATURE_SMARTSHIFT_BIT = 24 # macro -FEATURE_GTHR_BIT = 25 # macro -FEATURE_ACDC_BIT = 26 # macro -FEATURE_VR0HOT_BIT = 27 # macro -FEATURE_FW_CTF_BIT = 28 # macro -FEATURE_FAN_CONTROL_BIT = 29 # macro -FEATURE_GFX_DCS_BIT = 30 # macro -FEATURE_GFX_READ_MARGIN_BIT = 31 # macro -FEATURE_LED_DISPLAY_BIT = 32 # macro -FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 33 # macro -FEATURE_OUT_OF_BAND_MONITOR_BIT = 34 # macro -FEATURE_OPTIMIZED_VMIN_BIT = 35 # macro -FEATURE_GFX_IMU_BIT = 36 # macro -FEATURE_BOOT_TIME_CAL_BIT = 37 # macro -FEATURE_GFX_PCC_DFLL_BIT = 38 # macro -FEATURE_SOC_CG_BIT = 39 # macro -FEATURE_DF_CSTATE_BIT = 40 # macro -FEATURE_GFX_EDC_BIT = 41 # macro -FEATURE_BOOT_POWER_OPT_BIT = 42 # macro -FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 43 # macro -FEATURE_BACO_CG_BIT = 45 # macro -FEATURE_MEM_TEMP_READ_BIT = 46 # macro -FEATURE_ATHUB_MMHUB_PG_BIT = 47 # macro -FEATURE_SOC_PCC_BIT = 48 # macro -FEATURE_EDC_PWRBRK_BIT = 49 # macro -FEATURE_SOC_EDC_XVMIN_BIT = 50 # macro -FEATURE_GFX_PSM_DIDT_BIT = 51 # macro -FEATURE_APT_ALL_ENABLE_BIT = 52 # macro -FEATURE_APT_SQ_THROTTLE_BIT = 53 # macro -FEATURE_APT_PF_DCS_BIT = 54 # macro -FEATURE_GFX_EDC_XVMIN_BIT = 55 # macro -FEATURE_GFX_DIDT_XVMIN_BIT = 56 # macro -FEATURE_FAN_ABNORMAL_BIT = 57 # macro -FEATURE_CLOCK_STRETCH_COMPENSATOR = 58 # macro -FEATURE_SPARE_59_BIT = 59 # macro -FEATURE_SPARE_60_BIT = 60 # macro -FEATURE_SPARE_61_BIT = 61 # macro -FEATURE_SPARE_62_BIT = 62 # macro -FEATURE_SPARE_63_BIT = 63 # macro -ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF # macro -ALLOWED_FEATURE_CTRL_SCPM = (1<<1) # macro -DEBUG_OVERRIDE_NOT_USE = 0x00000001 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 # macro -DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 # macro -DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 # macro -DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 # macro -DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 # macro -DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 # macro -DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 # macro -DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 # macro -DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 # macro -DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 # macro -DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 # macro -DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE = 0x00002000 # macro -DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY = 0x00004000 # macro -DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING = 0x00008000 # macro -DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG = 0x00010000 # macro -VR_MAPPING_VR_SELECT_MASK = 0x01 # macro -VR_MAPPING_VR_SELECT_SHIFT = 0x00 # macro -VR_MAPPING_PLANE_SELECT_MASK = 0x02 # macro -VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI0 = 0x01 # macro -PSI_SEL_VR0_PLANE0_PSI1 = 0x02 # macro -PSI_SEL_VR0_PLANE1_PSI0 = 0x04 # macro -PSI_SEL_VR0_PLANE1_PSI1 = 0x08 # macro -PSI_SEL_VR1_PLANE0_PSI0 = 0x10 # macro -PSI_SEL_VR1_PLANE0_PSI1 = 0x20 # macro -PSI_SEL_VR1_PLANE1_PSI0 = 0x40 # macro -PSI_SEL_VR1_PLANE1_PSI1 = 0x80 # macro -THROTTLER_TEMP_EDGE_BIT = 0 # macro -THROTTLER_TEMP_HOTSPOT_BIT = 1 # macro -THROTTLER_TEMP_HOTSPOT_GFX_BIT = 2 # macro -THROTTLER_TEMP_HOTSPOT_SOC_BIT = 3 # macro -THROTTLER_TEMP_MEM_BIT = 4 # macro -THROTTLER_TEMP_VR_GFX_BIT = 5 # macro -THROTTLER_TEMP_VR_SOC_BIT = 6 # macro -THROTTLER_TEMP_VR_MEM0_BIT = 7 # macro -THROTTLER_TEMP_VR_MEM1_BIT = 8 # macro -THROTTLER_TEMP_LIQUID0_BIT = 9 # macro -THROTTLER_TEMP_LIQUID1_BIT = 10 # macro -THROTTLER_TEMP_PLX_BIT = 11 # macro -THROTTLER_TDC_GFX_BIT = 12 # macro -THROTTLER_TDC_SOC_BIT = 13 # macro -THROTTLER_PPT0_BIT = 14 # macro -THROTTLER_PPT1_BIT = 15 # macro -THROTTLER_PPT2_BIT = 16 # macro -THROTTLER_PPT3_BIT = 17 # macro -THROTTLER_FIT_BIT = 18 # macro -THROTTLER_GFX_APCC_PLUS_BIT = 19 # macro -THROTTLER_GFX_DVO_BIT = 20 # macro -THROTTLER_COUNT = 21 # macro -FW_DSTATE_SOC_ULV_BIT = 0 # macro -FW_DSTATE_G6_HSR_BIT = 1 # macro -FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 # macro -FW_DSTATE_SMN_DS_BIT = 3 # macro -FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 # macro -FW_DSTATE_SOC_LIV_MIN_BIT = 5 # macro -FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 # macro -FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 # macro -FW_DSTATE_MALL_ALLOC_BIT = 8 # macro -FW_DSTATE_MEM_PSI_BIT = 9 # macro -FW_DSTATE_HSR_NON_STROBE_BIT = 10 # macro -FW_DSTATE_MP0_ENTER_WFI_BIT = 11 # macro -FW_DSTATE_MALL_FLUSH_BIT = 12 # macro -FW_DSTATE_SOC_PSI_BIT = 13 # macro -FW_DSTATE_MMHUB_INTERLOCK_BIT = 14 # macro -FW_DSTATE_D0i3_2_QUIET_FW_BIT = 15 # macro -FW_DSTATE_CLDO_PRG_BIT = 16 # macro -FW_DSTATE_DF_PLL_PWRDN_BIT = 17 # macro -LED_DISPLAY_GFX_DPM_BIT = 0 # macro -LED_DISPLAY_PCIE_BIT = 1 # macro -LED_DISPLAY_ERROR_BIT = 2 # macro -MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 # macro -MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 # macro -MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 # macro -NUM_I2C_CONTROLLERS = 8 # macro -I2C_CONTROLLER_ENABLED = 1 # macro -I2C_CONTROLLER_DISABLED = 0 # macro -MAX_SW_I2C_COMMANDS = 24 # macro -CMDCONFIG_STOP_BIT = 0 # macro -CMDCONFIG_RESTART_BIT = 1 # macro -CMDCONFIG_READWRITE_BIT = 2 # macro -CMDCONFIG_STOP_MASK = (1<<0) # macro -CMDCONFIG_RESTART_MASK = (1<<1) # macro -CMDCONFIG_READWRITE_MASK = (1<<2) # macro -EPCS_HIGH_POWER = 600 # macro -EPCS_NORMAL_POWER = 450 # macro -EPCS_LOW_POWER = 300 # macro -EPCS_SHORTED_POWER = 150 # macro -EPCS_NO_BOOTUP = 0 # macro -PP_NUM_RTAVFS_PWL_ZONES = 5 # macro -PP_NUM_PSM_DIDT_PWL_ZONES = 3 # macro -PP_NUM_OD_VF_CURVE_POINTS = 5 + 1 # macro -PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 # macro -PP_OD_FEATURE_GFX_VMAX_BIT = 1 # macro -PP_OD_FEATURE_SOC_VMAX_BIT = 2 # macro -PP_OD_FEATURE_PPT_BIT = 3 # macro -PP_OD_FEATURE_FAN_CURVE_BIT = 4 # macro -PP_OD_FEATURE_FAN_LEGACY_BIT = 5 # macro -PP_OD_FEATURE_FULL_CTRL_BIT = 6 # macro -PP_OD_FEATURE_TDC_BIT = 7 # macro -PP_OD_FEATURE_GFXCLK_BIT = 8 # macro -PP_OD_FEATURE_UCLK_BIT = 9 # macro -PP_OD_FEATURE_FCLK_BIT = 10 # macro -PP_OD_FEATURE_ZERO_FAN_BIT = 11 # macro -PP_OD_FEATURE_TEMPERATURE_BIT = 12 # macro -PP_OD_FEATURE_EDC_BIT = 13 # macro -PP_OD_FEATURE_COUNT = 14 # macro -INVALID_BOARD_GPIO = 0xFF # macro -NUM_WM_RANGES = 4 # macro -WORKLOAD_PPLIB_DEFAULT_BIT = 0 # macro -WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 # macro -WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 # macro -WORKLOAD_PPLIB_VIDEO_BIT = 3 # macro -WORKLOAD_PPLIB_VR_BIT = 4 # macro -WORKLOAD_PPLIB_COMPUTE_BIT = 5 # macro -WORKLOAD_PPLIB_CUSTOM_BIT = 6 # macro -WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 # macro -WORKLOAD_PPLIB_DIRECT_ML_BIT = 8 # macro -WORKLOAD_PPLIB_CGVDI_BIT = 9 # macro -WORKLOAD_PPLIB_COUNT = 10 # macro -TABLE_TRANSFER_OK = 0x0 # macro -TABLE_TRANSFER_FAILED = 0xFF # macro -TABLE_TRANSFER_PENDING = 0xAB # macro -TABLE_PPT_FAILED = 0x100 # macro -TABLE_TDC_FAILED = 0x200 # macro -TABLE_TEMP_FAILED = 0x400 # macro -TABLE_FAN_TARGET_TEMP_FAILED = 0x800 # macro -TABLE_FAN_STOP_TEMP_FAILED = 0x1000 # macro -TABLE_FAN_START_TEMP_FAILED = 0x2000 # macro -TABLE_FAN_PWM_MIN_FAILED = 0x4000 # macro -TABLE_ACOUSTIC_TARGET_RPM_FAILED = 0x8000 # macro -TABLE_ACOUSTIC_LIMIT_RPM_FAILED = 0x10000 # macro -TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED = 0x20000 # macro -TABLE_PPTABLE = 0 # macro -TABLE_COMBO_PPTABLE = 1 # macro -TABLE_WATERMARKS = 2 # macro -TABLE_AVFS_PSM_DEBUG = 3 # macro -TABLE_PMSTATUSLOG = 4 # macro -TABLE_SMU_METRICS = 5 # macro -TABLE_DRIVER_SMU_CONFIG = 6 # macro -TABLE_ACTIVITY_MONITOR_COEFF = 7 # macro -TABLE_OVERDRIVE = 8 # macro -TABLE_I2C_COMMANDS = 9 # macro -TABLE_DRIVER_INFO = 10 # macro -TABLE_ECCINFO = 11 # macro -TABLE_CUSTOM_SKUTABLE = 12 # macro -TABLE_COUNT = 13 # macro -IH_INTERRUPT_ID_TO_DRIVER = 0xFE # macro -IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 # macro -IH_INTERRUPT_CONTEXT_ID_AC = 0x3 # macro -IH_INTERRUPT_CONTEXT_ID_DC = 0x4 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 # macro -IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 # macro -IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 # macro -IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 # macro -IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE = 0xA # macro +FEATURE_BTC_e = CEnum(ctypes.c_uint32) +FEATURE_BTC_NOP = FEATURE_BTC_e.define('FEATURE_BTC_NOP', 0) +FEATURE_BTC_SAVE = FEATURE_BTC_e.define('FEATURE_BTC_SAVE', 1) +FEATURE_BTC_RESTORE = FEATURE_BTC_e.define('FEATURE_BTC_RESTORE', 2) +FEATURE_BTC_COUNT = FEATURE_BTC_e.define('FEATURE_BTC_COUNT', 3) -# values for enumeration 'c__EA_FEATURE_PWR_DOMAIN_e' -c__EA_FEATURE_PWR_DOMAIN_e__enumvalues = { - 0: 'FEATURE_PWR_ALL', - 1: 'FEATURE_PWR_S5', - 2: 'FEATURE_PWR_BACO', - 3: 'FEATURE_PWR_SOC', - 4: 'FEATURE_PWR_GFX', - 5: 'FEATURE_PWR_DOMAIN_COUNT', -} -FEATURE_PWR_ALL = 0 -FEATURE_PWR_S5 = 1 -FEATURE_PWR_BACO = 2 -FEATURE_PWR_SOC = 3 -FEATURE_PWR_GFX = 4 -FEATURE_PWR_DOMAIN_COUNT = 5 -c__EA_FEATURE_PWR_DOMAIN_e = ctypes.c_uint32 # enum -FEATURE_PWR_DOMAIN_e = c__EA_FEATURE_PWR_DOMAIN_e -FEATURE_PWR_DOMAIN_e__enumvalues = c__EA_FEATURE_PWR_DOMAIN_e__enumvalues +SVI_PSI_e = CEnum(ctypes.c_uint32) +SVI_PSI_0 = SVI_PSI_e.define('SVI_PSI_0', 0) +SVI_PSI_1 = SVI_PSI_e.define('SVI_PSI_1', 1) +SVI_PSI_2 = SVI_PSI_e.define('SVI_PSI_2', 2) +SVI_PSI_3 = SVI_PSI_e.define('SVI_PSI_3', 3) +SVI_PSI_4 = SVI_PSI_e.define('SVI_PSI_4', 4) +SVI_PSI_5 = SVI_PSI_e.define('SVI_PSI_5', 5) +SVI_PSI_6 = SVI_PSI_e.define('SVI_PSI_6', 6) +SVI_PSI_7 = SVI_PSI_e.define('SVI_PSI_7', 7) -# values for enumeration 'c__EA_FEATURE_BTC_e' -c__EA_FEATURE_BTC_e__enumvalues = { - 0: 'FEATURE_BTC_NOP', - 1: 'FEATURE_BTC_SAVE', - 2: 'FEATURE_BTC_RESTORE', - 3: 'FEATURE_BTC_COUNT', -} -FEATURE_BTC_NOP = 0 -FEATURE_BTC_SAVE = 1 -FEATURE_BTC_RESTORE = 2 -FEATURE_BTC_COUNT = 3 -c__EA_FEATURE_BTC_e = ctypes.c_uint32 # enum -FEATURE_BTC_e = c__EA_FEATURE_BTC_e -FEATURE_BTC_e__enumvalues = c__EA_FEATURE_BTC_e__enumvalues +SMARTSHIFT_VERSION_e = CEnum(ctypes.c_uint32) +SMARTSHIFT_VERSION_1 = SMARTSHIFT_VERSION_e.define('SMARTSHIFT_VERSION_1', 0) +SMARTSHIFT_VERSION_2 = SMARTSHIFT_VERSION_e.define('SMARTSHIFT_VERSION_2', 1) +SMARTSHIFT_VERSION_3 = SMARTSHIFT_VERSION_e.define('SMARTSHIFT_VERSION_3', 2) -# values for enumeration 'c__EA_SVI_PSI_e' -c__EA_SVI_PSI_e__enumvalues = { - 0: 'SVI_PSI_0', - 1: 'SVI_PSI_1', - 2: 'SVI_PSI_2', - 3: 'SVI_PSI_3', - 4: 'SVI_PSI_4', - 5: 'SVI_PSI_5', - 6: 'SVI_PSI_6', - 7: 'SVI_PSI_7', -} -SVI_PSI_0 = 0 -SVI_PSI_1 = 1 -SVI_PSI_2 = 2 -SVI_PSI_3 = 3 -SVI_PSI_4 = 4 -SVI_PSI_5 = 5 -SVI_PSI_6 = 6 -SVI_PSI_7 = 7 -c__EA_SVI_PSI_e = ctypes.c_uint32 # enum -SVI_PSI_e = c__EA_SVI_PSI_e -SVI_PSI_e__enumvalues = c__EA_SVI_PSI_e__enumvalues +FOPT_CALC_e = CEnum(ctypes.c_uint32) +FOPT_CALC_AC_CALC_DC = FOPT_CALC_e.define('FOPT_CALC_AC_CALC_DC', 0) +FOPT_PPTABLE_AC_CALC_DC = FOPT_CALC_e.define('FOPT_PPTABLE_AC_CALC_DC', 1) +FOPT_CALC_AC_PPTABLE_DC = FOPT_CALC_e.define('FOPT_CALC_AC_PPTABLE_DC', 2) +FOPT_PPTABLE_AC_PPTABLE_DC = FOPT_CALC_e.define('FOPT_PPTABLE_AC_PPTABLE_DC', 3) -# values for enumeration 'c__EA_SMARTSHIFT_VERSION_e' -c__EA_SMARTSHIFT_VERSION_e__enumvalues = { - 0: 'SMARTSHIFT_VERSION_1', - 1: 'SMARTSHIFT_VERSION_2', - 2: 'SMARTSHIFT_VERSION_3', -} -SMARTSHIFT_VERSION_1 = 0 -SMARTSHIFT_VERSION_2 = 1 -SMARTSHIFT_VERSION_3 = 2 -c__EA_SMARTSHIFT_VERSION_e = ctypes.c_uint32 # enum -SMARTSHIFT_VERSION_e = c__EA_SMARTSHIFT_VERSION_e -SMARTSHIFT_VERSION_e__enumvalues = c__EA_SMARTSHIFT_VERSION_e__enumvalues +DRAM_BIT_WIDTH_TYPE_e = CEnum(ctypes.c_uint32) +DRAM_BIT_WIDTH_DISABLED = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_DISABLED', 0) +DRAM_BIT_WIDTH_X_8 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_8', 8) +DRAM_BIT_WIDTH_X_16 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_16', 16) +DRAM_BIT_WIDTH_X_32 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_32', 32) +DRAM_BIT_WIDTH_X_64 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_64', 64) +DRAM_BIT_WIDTH_X_128 = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_X_128', 128) +DRAM_BIT_WIDTH_COUNT = DRAM_BIT_WIDTH_TYPE_e.define('DRAM_BIT_WIDTH_COUNT', 129) -# values for enumeration 'c__EA_FOPT_CALC_e' -c__EA_FOPT_CALC_e__enumvalues = { - 0: 'FOPT_CALC_AC_CALC_DC', - 1: 'FOPT_PPTABLE_AC_CALC_DC', - 2: 'FOPT_CALC_AC_PPTABLE_DC', - 3: 'FOPT_PPTABLE_AC_PPTABLE_DC', -} -FOPT_CALC_AC_CALC_DC = 0 -FOPT_PPTABLE_AC_CALC_DC = 1 -FOPT_CALC_AC_PPTABLE_DC = 2 -FOPT_PPTABLE_AC_PPTABLE_DC = 3 -c__EA_FOPT_CALC_e = ctypes.c_uint32 # enum -FOPT_CALC_e = c__EA_FOPT_CALC_e -FOPT_CALC_e__enumvalues = c__EA_FOPT_CALC_e__enumvalues +I2cControllerPort_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_PORT_0 = I2cControllerPort_e.define('I2C_CONTROLLER_PORT_0', 0) +I2C_CONTROLLER_PORT_1 = I2cControllerPort_e.define('I2C_CONTROLLER_PORT_1', 1) +I2C_CONTROLLER_PORT_COUNT = I2cControllerPort_e.define('I2C_CONTROLLER_PORT_COUNT', 2) -# values for enumeration 'c__EA_DRAM_BIT_WIDTH_TYPE_e' -c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues = { - 0: 'DRAM_BIT_WIDTH_DISABLED', - 8: 'DRAM_BIT_WIDTH_X_8', - 16: 'DRAM_BIT_WIDTH_X_16', - 32: 'DRAM_BIT_WIDTH_X_32', - 64: 'DRAM_BIT_WIDTH_X_64', - 128: 'DRAM_BIT_WIDTH_X_128', - 129: 'DRAM_BIT_WIDTH_COUNT', -} -DRAM_BIT_WIDTH_DISABLED = 0 -DRAM_BIT_WIDTH_X_8 = 8 -DRAM_BIT_WIDTH_X_16 = 16 -DRAM_BIT_WIDTH_X_32 = 32 -DRAM_BIT_WIDTH_X_64 = 64 -DRAM_BIT_WIDTH_X_128 = 128 -DRAM_BIT_WIDTH_COUNT = 129 -c__EA_DRAM_BIT_WIDTH_TYPE_e = ctypes.c_uint32 # enum -DRAM_BIT_WIDTH_TYPE_e = c__EA_DRAM_BIT_WIDTH_TYPE_e -DRAM_BIT_WIDTH_TYPE_e__enumvalues = c__EA_DRAM_BIT_WIDTH_TYPE_e__enumvalues +I2cControllerName_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_NAME_VR_GFX = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_GFX', 0) +I2C_CONTROLLER_NAME_VR_SOC = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_SOC', 1) +I2C_CONTROLLER_NAME_VR_VMEMP = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_VMEMP', 2) +I2C_CONTROLLER_NAME_VR_VDDIO = I2cControllerName_e.define('I2C_CONTROLLER_NAME_VR_VDDIO', 3) +I2C_CONTROLLER_NAME_LIQUID0 = I2cControllerName_e.define('I2C_CONTROLLER_NAME_LIQUID0', 4) +I2C_CONTROLLER_NAME_LIQUID1 = I2cControllerName_e.define('I2C_CONTROLLER_NAME_LIQUID1', 5) +I2C_CONTROLLER_NAME_PLX = I2cControllerName_e.define('I2C_CONTROLLER_NAME_PLX', 6) +I2C_CONTROLLER_NAME_FAN_INTAKE = I2cControllerName_e.define('I2C_CONTROLLER_NAME_FAN_INTAKE', 7) +I2C_CONTROLLER_NAME_COUNT = I2cControllerName_e.define('I2C_CONTROLLER_NAME_COUNT', 8) -# values for enumeration 'c__EA_I2cControllerPort_e' -c__EA_I2cControllerPort_e__enumvalues = { - 0: 'I2C_CONTROLLER_PORT_0', - 1: 'I2C_CONTROLLER_PORT_1', - 2: 'I2C_CONTROLLER_PORT_COUNT', -} -I2C_CONTROLLER_PORT_0 = 0 -I2C_CONTROLLER_PORT_1 = 1 -I2C_CONTROLLER_PORT_COUNT = 2 -c__EA_I2cControllerPort_e = ctypes.c_uint32 # enum -I2cControllerPort_e = c__EA_I2cControllerPort_e -I2cControllerPort_e__enumvalues = c__EA_I2cControllerPort_e__enumvalues +I2cControllerThrottler_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_THROTTLER_TYPE_NONE = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_TYPE_NONE', 0) +I2C_CONTROLLER_THROTTLER_VR_GFX = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_GFX', 1) +I2C_CONTROLLER_THROTTLER_VR_SOC = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_SOC', 2) +I2C_CONTROLLER_THROTTLER_VR_VMEMP = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_VMEMP', 3) +I2C_CONTROLLER_THROTTLER_VR_VDDIO = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_VR_VDDIO', 4) +I2C_CONTROLLER_THROTTLER_LIQUID0 = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_LIQUID0', 5) +I2C_CONTROLLER_THROTTLER_LIQUID1 = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_LIQUID1', 6) +I2C_CONTROLLER_THROTTLER_PLX = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_PLX', 7) +I2C_CONTROLLER_THROTTLER_FAN_INTAKE = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_FAN_INTAKE', 8) +I2C_CONTROLLER_THROTTLER_INA3221 = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_INA3221', 9) +I2C_CONTROLLER_THROTTLER_COUNT = I2cControllerThrottler_e.define('I2C_CONTROLLER_THROTTLER_COUNT', 10) -# values for enumeration 'c__EA_I2cControllerName_e' -c__EA_I2cControllerName_e__enumvalues = { - 0: 'I2C_CONTROLLER_NAME_VR_GFX', - 1: 'I2C_CONTROLLER_NAME_VR_SOC', - 2: 'I2C_CONTROLLER_NAME_VR_VMEMP', - 3: 'I2C_CONTROLLER_NAME_VR_VDDIO', - 4: 'I2C_CONTROLLER_NAME_LIQUID0', - 5: 'I2C_CONTROLLER_NAME_LIQUID1', - 6: 'I2C_CONTROLLER_NAME_PLX', - 7: 'I2C_CONTROLLER_NAME_FAN_INTAKE', - 8: 'I2C_CONTROLLER_NAME_COUNT', -} -I2C_CONTROLLER_NAME_VR_GFX = 0 -I2C_CONTROLLER_NAME_VR_SOC = 1 -I2C_CONTROLLER_NAME_VR_VMEMP = 2 -I2C_CONTROLLER_NAME_VR_VDDIO = 3 -I2C_CONTROLLER_NAME_LIQUID0 = 4 -I2C_CONTROLLER_NAME_LIQUID1 = 5 -I2C_CONTROLLER_NAME_PLX = 6 -I2C_CONTROLLER_NAME_FAN_INTAKE = 7 -I2C_CONTROLLER_NAME_COUNT = 8 -c__EA_I2cControllerName_e = ctypes.c_uint32 # enum -I2cControllerName_e = c__EA_I2cControllerName_e -I2cControllerName_e__enumvalues = c__EA_I2cControllerName_e__enumvalues +I2cControllerProtocol_e = CEnum(ctypes.c_uint32) +I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', 0) +I2C_CONTROLLER_PROTOCOL_VR_IR35217 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_VR_IR35217', 1) +I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', 2) +I2C_CONTROLLER_PROTOCOL_INA3221 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_INA3221', 3) +I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', 4) +I2C_CONTROLLER_PROTOCOL_COUNT = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_COUNT', 5) -# values for enumeration 'c__EA_I2cControllerThrottler_e' -c__EA_I2cControllerThrottler_e__enumvalues = { - 0: 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 1: 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 2: 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 3: 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', - 4: 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 5: 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 6: 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 7: 'I2C_CONTROLLER_THROTTLER_PLX', - 8: 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 9: 'I2C_CONTROLLER_THROTTLER_INA3221', - 10: 'I2C_CONTROLLER_THROTTLER_COUNT', -} -I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0 -I2C_CONTROLLER_THROTTLER_VR_GFX = 1 -I2C_CONTROLLER_THROTTLER_VR_SOC = 2 -I2C_CONTROLLER_THROTTLER_VR_VMEMP = 3 -I2C_CONTROLLER_THROTTLER_VR_VDDIO = 4 -I2C_CONTROLLER_THROTTLER_LIQUID0 = 5 -I2C_CONTROLLER_THROTTLER_LIQUID1 = 6 -I2C_CONTROLLER_THROTTLER_PLX = 7 -I2C_CONTROLLER_THROTTLER_FAN_INTAKE = 8 -I2C_CONTROLLER_THROTTLER_INA3221 = 9 -I2C_CONTROLLER_THROTTLER_COUNT = 10 -c__EA_I2cControllerThrottler_e = ctypes.c_uint32 # enum -I2cControllerThrottler_e = c__EA_I2cControllerThrottler_e -I2cControllerThrottler_e__enumvalues = c__EA_I2cControllerThrottler_e__enumvalues - -# values for enumeration 'c__EA_I2cControllerProtocol_e' -c__EA_I2cControllerProtocol_e__enumvalues = { - 0: 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 1: 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 2: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 3: 'I2C_CONTROLLER_PROTOCOL_INA3221', - 4: 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 5: 'I2C_CONTROLLER_PROTOCOL_COUNT', -} -I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5 = 0 -I2C_CONTROLLER_PROTOCOL_VR_IR35217 = 1 -I2C_CONTROLLER_PROTOCOL_TMP_MAX31875 = 2 -I2C_CONTROLLER_PROTOCOL_INA3221 = 3 -I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = 4 -I2C_CONTROLLER_PROTOCOL_COUNT = 5 -c__EA_I2cControllerProtocol_e = ctypes.c_uint32 # enum -I2cControllerProtocol_e = c__EA_I2cControllerProtocol_e -I2cControllerProtocol_e__enumvalues = c__EA_I2cControllerProtocol_e__enumvalues -class struct_c__SA_I2cControllerConfig_t(Structure): - pass - -struct_c__SA_I2cControllerConfig_t._pack_ = 1 # source:False -struct_c__SA_I2cControllerConfig_t._fields_ = [ - ('Enabled', ctypes.c_ubyte), - ('Speed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('ControllerPort', ctypes.c_ubyte), - ('ControllerName', ctypes.c_ubyte), - ('ThermalThrotter', ctypes.c_ubyte), - ('I2cProtocol', ctypes.c_ubyte), - ('PaddingConfig', ctypes.c_ubyte), +class I2cControllerConfig_t(Struct): pass +uint8_t = ctypes.c_ubyte +I2cControllerConfig_t._fields_ = [ + ('Enabled', uint8_t), + ('Speed', uint8_t), + ('SlaveAddress', uint8_t), + ('ControllerPort', uint8_t), + ('ControllerName', uint8_t), + ('ThermalThrotter', uint8_t), + ('I2cProtocol', uint8_t), + ('PaddingConfig', uint8_t), ] +I2cPort_e = CEnum(ctypes.c_uint32) +I2C_PORT_SVD_SCL = I2cPort_e.define('I2C_PORT_SVD_SCL', 0) +I2C_PORT_GPIO = I2cPort_e.define('I2C_PORT_GPIO', 1) -I2cControllerConfig_t = struct_c__SA_I2cControllerConfig_t +I2cSpeed_e = CEnum(ctypes.c_uint32) +I2C_SPEED_FAST_50K = I2cSpeed_e.define('I2C_SPEED_FAST_50K', 0) +I2C_SPEED_FAST_100K = I2cSpeed_e.define('I2C_SPEED_FAST_100K', 1) +I2C_SPEED_FAST_400K = I2cSpeed_e.define('I2C_SPEED_FAST_400K', 2) +I2C_SPEED_FAST_PLUS_1M = I2cSpeed_e.define('I2C_SPEED_FAST_PLUS_1M', 3) +I2C_SPEED_HIGH_1M = I2cSpeed_e.define('I2C_SPEED_HIGH_1M', 4) +I2C_SPEED_HIGH_2M = I2cSpeed_e.define('I2C_SPEED_HIGH_2M', 5) +I2C_SPEED_COUNT = I2cSpeed_e.define('I2C_SPEED_COUNT', 6) -# values for enumeration 'c__EA_I2cPort_e' -c__EA_I2cPort_e__enumvalues = { - 0: 'I2C_PORT_SVD_SCL', - 1: 'I2C_PORT_GPIO', -} -I2C_PORT_SVD_SCL = 0 -I2C_PORT_GPIO = 1 -c__EA_I2cPort_e = ctypes.c_uint32 # enum -I2cPort_e = c__EA_I2cPort_e -I2cPort_e__enumvalues = c__EA_I2cPort_e__enumvalues +I2cCmdType_e = CEnum(ctypes.c_uint32) +I2C_CMD_READ = I2cCmdType_e.define('I2C_CMD_READ', 0) +I2C_CMD_WRITE = I2cCmdType_e.define('I2C_CMD_WRITE', 1) +I2C_CMD_COUNT = I2cCmdType_e.define('I2C_CMD_COUNT', 2) -# values for enumeration 'c__EA_I2cSpeed_e' -c__EA_I2cSpeed_e__enumvalues = { - 0: 'I2C_SPEED_FAST_50K', - 1: 'I2C_SPEED_FAST_100K', - 2: 'I2C_SPEED_FAST_400K', - 3: 'I2C_SPEED_FAST_PLUS_1M', - 4: 'I2C_SPEED_HIGH_1M', - 5: 'I2C_SPEED_HIGH_2M', - 6: 'I2C_SPEED_COUNT', -} -I2C_SPEED_FAST_50K = 0 -I2C_SPEED_FAST_100K = 1 -I2C_SPEED_FAST_400K = 2 -I2C_SPEED_FAST_PLUS_1M = 3 -I2C_SPEED_HIGH_1M = 4 -I2C_SPEED_HIGH_2M = 5 -I2C_SPEED_COUNT = 6 -c__EA_I2cSpeed_e = ctypes.c_uint32 # enum -I2cSpeed_e = c__EA_I2cSpeed_e -I2cSpeed_e__enumvalues = c__EA_I2cSpeed_e__enumvalues - -# values for enumeration 'c__EA_I2cCmdType_e' -c__EA_I2cCmdType_e__enumvalues = { - 0: 'I2C_CMD_READ', - 1: 'I2C_CMD_WRITE', - 2: 'I2C_CMD_COUNT', -} -I2C_CMD_READ = 0 -I2C_CMD_WRITE = 1 -I2C_CMD_COUNT = 2 -c__EA_I2cCmdType_e = ctypes.c_uint32 # enum -I2cCmdType_e = c__EA_I2cCmdType_e -I2cCmdType_e__enumvalues = c__EA_I2cCmdType_e__enumvalues -class struct_c__SA_SwI2cCmd_t(Structure): - pass - -struct_c__SA_SwI2cCmd_t._pack_ = 1 # source:False -struct_c__SA_SwI2cCmd_t._fields_ = [ - ('ReadWriteData', ctypes.c_ubyte), - ('CmdConfig', ctypes.c_ubyte), +class SwI2cCmd_t(Struct): pass +SwI2cCmd_t._fields_ = [ + ('ReadWriteData', uint8_t), + ('CmdConfig', uint8_t), ] - -SwI2cCmd_t = struct_c__SA_SwI2cCmd_t -class struct_c__SA_SwI2cRequest_t(Structure): - pass - -struct_c__SA_SwI2cRequest_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequest_t._fields_ = [ - ('I2CcontrollerPort', ctypes.c_ubyte), - ('I2CSpeed', ctypes.c_ubyte), - ('SlaveAddress', ctypes.c_ubyte), - ('NumCmds', ctypes.c_ubyte), - ('SwI2cCmds', struct_c__SA_SwI2cCmd_t * 24), +class SwI2cRequest_t(Struct): pass +SwI2cRequest_t._fields_ = [ + ('I2CcontrollerPort', uint8_t), + ('I2CSpeed', uint8_t), + ('SlaveAddress', uint8_t), + ('NumCmds', uint8_t), + ('SwI2cCmds', (SwI2cCmd_t * 24)), ] - -SwI2cRequest_t = struct_c__SA_SwI2cRequest_t -class struct_c__SA_SwI2cRequestExternal_t(Structure): - pass - -struct_c__SA_SwI2cRequestExternal_t._pack_ = 1 # source:False -struct_c__SA_SwI2cRequestExternal_t._fields_ = [ - ('SwI2cRequest', SwI2cRequest_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), +class SwI2cRequestExternal_t(Struct): pass +SwI2cRequestExternal_t._fields_ = [ + ('SwI2cRequest', SwI2cRequest_t), + ('Spare', (uint32_t * 8)), + ('MmHubPadding', (uint32_t * 8)), ] - -SwI2cRequestExternal_t = struct_c__SA_SwI2cRequestExternal_t -class struct_c__SA_EccInfo_t(Structure): - pass - -struct_c__SA_EccInfo_t._pack_ = 1 # source:False -struct_c__SA_EccInfo_t._fields_ = [ - ('mca_umc_status', ctypes.c_uint64), - ('mca_umc_addr', ctypes.c_uint64), - ('ce_count_lo_chip', ctypes.c_uint16), - ('ce_count_hi_chip', ctypes.c_uint16), - ('eccPadding', ctypes.c_uint32), +class EccInfo_t(Struct): pass +uint64_t = ctypes.c_uint64 +uint16_t = ctypes.c_uint16 +EccInfo_t._fields_ = [ + ('mca_umc_status', uint64_t), + ('mca_umc_addr', uint64_t), + ('ce_count_lo_chip', uint16_t), + ('ce_count_hi_chip', uint16_t), + ('eccPadding', uint32_t), ] - -EccInfo_t = struct_c__SA_EccInfo_t -class struct_c__SA_EccInfoTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('EccInfo', struct_c__SA_EccInfo_t * 24), - ] - -EccInfoTable_t = struct_c__SA_EccInfoTable_t - -# values for enumeration 'c__EA_EPCS_STATUS_e' -c__EA_EPCS_STATUS_e__enumvalues = { - 0: 'EPCS_SHORTED_LIMIT', - 1: 'EPCS_LOW_POWER_LIMIT', - 2: 'EPCS_NORMAL_POWER_LIMIT', - 3: 'EPCS_HIGH_POWER_LIMIT', - 4: 'EPCS_NOT_CONFIGURED', - 5: 'EPCS_STATUS_COUNT', -} -EPCS_SHORTED_LIMIT = 0 -EPCS_LOW_POWER_LIMIT = 1 -EPCS_NORMAL_POWER_LIMIT = 2 -EPCS_HIGH_POWER_LIMIT = 3 -EPCS_NOT_CONFIGURED = 4 -EPCS_STATUS_COUNT = 5 -c__EA_EPCS_STATUS_e = ctypes.c_uint32 # enum -EPCS_STATUS_e = c__EA_EPCS_STATUS_e -EPCS_STATUS_e__enumvalues = c__EA_EPCS_STATUS_e__enumvalues - -# values for enumeration 'c__EA_D3HOTSequence_e' -c__EA_D3HOTSequence_e__enumvalues = { - 0: 'BACO_SEQUENCE', - 1: 'MSR_SEQUENCE', - 2: 'BAMACO_SEQUENCE', - 3: 'ULPS_SEQUENCE', - 4: 'D3HOT_SEQUENCE_COUNT', -} -BACO_SEQUENCE = 0 -MSR_SEQUENCE = 1 -BAMACO_SEQUENCE = 2 -ULPS_SEQUENCE = 3 -D3HOT_SEQUENCE_COUNT = 4 -c__EA_D3HOTSequence_e = ctypes.c_uint32 # enum -D3HOTSequence_e = c__EA_D3HOTSequence_e -D3HOTSequence_e__enumvalues = c__EA_D3HOTSequence_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingMode_e' -c__EA_PowerGatingMode_e__enumvalues = { - 0: 'PG_DYNAMIC_MODE', - 1: 'PG_STATIC_MODE', -} -PG_DYNAMIC_MODE = 0 -PG_STATIC_MODE = 1 -c__EA_PowerGatingMode_e = ctypes.c_uint32 # enum -PowerGatingMode_e = c__EA_PowerGatingMode_e -PowerGatingMode_e__enumvalues = c__EA_PowerGatingMode_e__enumvalues - -# values for enumeration 'c__EA_PowerGatingSettings_e' -c__EA_PowerGatingSettings_e__enumvalues = { - 0: 'PG_POWER_DOWN', - 1: 'PG_POWER_UP', -} -PG_POWER_DOWN = 0 -PG_POWER_UP = 1 -c__EA_PowerGatingSettings_e = ctypes.c_uint32 # enum -PowerGatingSettings_e = c__EA_PowerGatingSettings_e -PowerGatingSettings_e__enumvalues = c__EA_PowerGatingSettings_e__enumvalues -class struct_c__SA_QuadraticInt_t(Structure): - pass - -struct_c__SA_QuadraticInt_t._pack_ = 1 # source:False -struct_c__SA_QuadraticInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), +class EccInfoTable_t(Struct): pass +EccInfoTable_t._fields_ = [ + ('EccInfo', (EccInfo_t * 24)), ] +EPCS_STATUS_e = CEnum(ctypes.c_uint32) +EPCS_SHORTED_LIMIT = EPCS_STATUS_e.define('EPCS_SHORTED_LIMIT', 0) +EPCS_LOW_POWER_LIMIT = EPCS_STATUS_e.define('EPCS_LOW_POWER_LIMIT', 1) +EPCS_NORMAL_POWER_LIMIT = EPCS_STATUS_e.define('EPCS_NORMAL_POWER_LIMIT', 2) +EPCS_HIGH_POWER_LIMIT = EPCS_STATUS_e.define('EPCS_HIGH_POWER_LIMIT', 3) +EPCS_NOT_CONFIGURED = EPCS_STATUS_e.define('EPCS_NOT_CONFIGURED', 4) +EPCS_STATUS_COUNT = EPCS_STATUS_e.define('EPCS_STATUS_COUNT', 5) -QuadraticInt_t = struct_c__SA_QuadraticInt_t -class struct_c__SA_LinearInt_t(Structure): - pass +D3HOTSequence_e = CEnum(ctypes.c_uint32) +BACO_SEQUENCE = D3HOTSequence_e.define('BACO_SEQUENCE', 0) +MSR_SEQUENCE = D3HOTSequence_e.define('MSR_SEQUENCE', 1) +BAMACO_SEQUENCE = D3HOTSequence_e.define('BAMACO_SEQUENCE', 2) +ULPS_SEQUENCE = D3HOTSequence_e.define('ULPS_SEQUENCE', 3) +D3HOT_SEQUENCE_COUNT = D3HOTSequence_e.define('D3HOT_SEQUENCE_COUNT', 4) -struct_c__SA_LinearInt_t._pack_ = 1 # source:False -struct_c__SA_LinearInt_t._fields_ = [ - ('m', ctypes.c_uint32), - ('b', ctypes.c_uint32), +PowerGatingMode_e = CEnum(ctypes.c_uint32) +PG_DYNAMIC_MODE = PowerGatingMode_e.define('PG_DYNAMIC_MODE', 0) +PG_STATIC_MODE = PowerGatingMode_e.define('PG_STATIC_MODE', 1) + +PowerGatingSettings_e = CEnum(ctypes.c_uint32) +PG_POWER_DOWN = PowerGatingSettings_e.define('PG_POWER_DOWN', 0) +PG_POWER_UP = PowerGatingSettings_e.define('PG_POWER_UP', 1) + +class QuadraticInt_t(Struct): pass +QuadraticInt_t._fields_ = [ + ('a', uint32_t), + ('b', uint32_t), + ('c', uint32_t), ] - -LinearInt_t = struct_c__SA_LinearInt_t -class struct_c__SA_DroopInt_t(Structure): - pass - -struct_c__SA_DroopInt_t._pack_ = 1 # source:False -struct_c__SA_DroopInt_t._fields_ = [ - ('a', ctypes.c_uint32), - ('b', ctypes.c_uint32), - ('c', ctypes.c_uint32), +class LinearInt_t(Struct): pass +LinearInt_t._fields_ = [ + ('m', uint32_t), + ('b', uint32_t), ] - -DroopInt_t = struct_c__SA_DroopInt_t - -# values for enumeration 'c__EA_DCS_ARCH_e' -c__EA_DCS_ARCH_e__enumvalues = { - 0: 'DCS_ARCH_DISABLED', - 1: 'DCS_ARCH_FADCS', - 2: 'DCS_ARCH_ASYNC', -} -DCS_ARCH_DISABLED = 0 -DCS_ARCH_FADCS = 1 -DCS_ARCH_ASYNC = 2 -c__EA_DCS_ARCH_e = ctypes.c_uint32 # enum -DCS_ARCH_e = c__EA_DCS_ARCH_e -DCS_ARCH_e__enumvalues = c__EA_DCS_ARCH_e__enumvalues - -# values for enumeration 'c__EA_PPCLK_e' -c__EA_PPCLK_e__enumvalues = { - 0: 'PPCLK_GFXCLK', - 1: 'PPCLK_SOCCLK', - 2: 'PPCLK_UCLK', - 3: 'PPCLK_FCLK', - 4: 'PPCLK_DCLK_0', - 5: 'PPCLK_VCLK_0', - 6: 'PPCLK_DISPCLK', - 7: 'PPCLK_DPPCLK', - 8: 'PPCLK_DPREFCLK', - 9: 'PPCLK_DCFCLK', - 10: 'PPCLK_DTBCLK', - 11: 'PPCLK_COUNT', -} -PPCLK_GFXCLK = 0 -PPCLK_SOCCLK = 1 -PPCLK_UCLK = 2 -PPCLK_FCLK = 3 -PPCLK_DCLK_0 = 4 -PPCLK_VCLK_0 = 5 -PPCLK_DISPCLK = 6 -PPCLK_DPPCLK = 7 -PPCLK_DPREFCLK = 8 -PPCLK_DCFCLK = 9 -PPCLK_DTBCLK = 10 -PPCLK_COUNT = 11 -c__EA_PPCLK_e = ctypes.c_uint32 # enum -PPCLK_e = c__EA_PPCLK_e -PPCLK_e__enumvalues = c__EA_PPCLK_e__enumvalues - -# values for enumeration 'c__EA_VOLTAGE_MODE_e' -c__EA_VOLTAGE_MODE_e__enumvalues = { - 0: 'VOLTAGE_MODE_PPTABLE', - 1: 'VOLTAGE_MODE_FUSES', - 2: 'VOLTAGE_MODE_COUNT', -} -VOLTAGE_MODE_PPTABLE = 0 -VOLTAGE_MODE_FUSES = 1 -VOLTAGE_MODE_COUNT = 2 -c__EA_VOLTAGE_MODE_e = ctypes.c_uint32 # enum -VOLTAGE_MODE_e = c__EA_VOLTAGE_MODE_e -VOLTAGE_MODE_e__enumvalues = c__EA_VOLTAGE_MODE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_VOLTAGE_TYPE_e' -c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues = { - 0: 'AVFS_VOLTAGE_GFX', - 1: 'AVFS_VOLTAGE_SOC', - 2: 'AVFS_VOLTAGE_COUNT', -} -AVFS_VOLTAGE_GFX = 0 -AVFS_VOLTAGE_SOC = 1 -AVFS_VOLTAGE_COUNT = 2 -c__EA_AVFS_VOLTAGE_TYPE_e = ctypes.c_uint32 # enum -AVFS_VOLTAGE_TYPE_e = c__EA_AVFS_VOLTAGE_TYPE_e -AVFS_VOLTAGE_TYPE_e__enumvalues = c__EA_AVFS_VOLTAGE_TYPE_e__enumvalues - -# values for enumeration 'c__EA_AVFS_TEMP_e' -c__EA_AVFS_TEMP_e__enumvalues = { - 0: 'AVFS_TEMP_COLD', - 1: 'AVFS_TEMP_HOT', - 2: 'AVFS_TEMP_COUNT', -} -AVFS_TEMP_COLD = 0 -AVFS_TEMP_HOT = 1 -AVFS_TEMP_COUNT = 2 -c__EA_AVFS_TEMP_e = ctypes.c_uint32 # enum -AVFS_TEMP_e = c__EA_AVFS_TEMP_e -AVFS_TEMP_e__enumvalues = c__EA_AVFS_TEMP_e__enumvalues - -# values for enumeration 'c__EA_AVFS_D_e' -c__EA_AVFS_D_e__enumvalues = { - 0: 'AVFS_D_G', - 1: 'AVFS_D_COUNT', -} -AVFS_D_G = 0 -AVFS_D_COUNT = 1 -c__EA_AVFS_D_e = ctypes.c_uint32 # enum -AVFS_D_e = c__EA_AVFS_D_e -AVFS_D_e__enumvalues = c__EA_AVFS_D_e__enumvalues - -# values for enumeration 'c__EA_UCLK_DIV_e' -c__EA_UCLK_DIV_e__enumvalues = { - 0: 'UCLK_DIV_BY_1', - 1: 'UCLK_DIV_BY_2', - 2: 'UCLK_DIV_BY_4', - 3: 'UCLK_DIV_BY_8', -} -UCLK_DIV_BY_1 = 0 -UCLK_DIV_BY_2 = 1 -UCLK_DIV_BY_4 = 2 -UCLK_DIV_BY_8 = 3 -c__EA_UCLK_DIV_e = ctypes.c_uint32 # enum -UCLK_DIV_e = c__EA_UCLK_DIV_e -UCLK_DIV_e__enumvalues = c__EA_UCLK_DIV_e__enumvalues - -# values for enumeration 'c__EA_GpioIntPolarity_e' -c__EA_GpioIntPolarity_e__enumvalues = { - 0: 'GPIO_INT_POLARITY_ACTIVE_LOW', - 1: 'GPIO_INT_POLARITY_ACTIVE_HIGH', -} -GPIO_INT_POLARITY_ACTIVE_LOW = 0 -GPIO_INT_POLARITY_ACTIVE_HIGH = 1 -c__EA_GpioIntPolarity_e = ctypes.c_uint32 # enum -GpioIntPolarity_e = c__EA_GpioIntPolarity_e -GpioIntPolarity_e__enumvalues = c__EA_GpioIntPolarity_e__enumvalues - -# values for enumeration 'c__EA_PwrConfig_e' -c__EA_PwrConfig_e__enumvalues = { - 0: 'PWR_CONFIG_TDP', - 1: 'PWR_CONFIG_TGP', - 2: 'PWR_CONFIG_TCP_ESTIMATED', - 3: 'PWR_CONFIG_TCP_MEASURED', - 4: 'PWR_CONFIG_TBP_DESKTOP', - 5: 'PWR_CONFIG_TBP_MOBILE', -} -PWR_CONFIG_TDP = 0 -PWR_CONFIG_TGP = 1 -PWR_CONFIG_TCP_ESTIMATED = 2 -PWR_CONFIG_TCP_MEASURED = 3 -PWR_CONFIG_TBP_DESKTOP = 4 -PWR_CONFIG_TBP_MOBILE = 5 -c__EA_PwrConfig_e = ctypes.c_uint32 # enum -PwrConfig_e = c__EA_PwrConfig_e -PwrConfig_e__enumvalues = c__EA_PwrConfig_e__enumvalues -class struct_c__SA_DpmDescriptor_t(Structure): - pass - -struct_c__SA_DpmDescriptor_t._pack_ = 1 # source:False -struct_c__SA_DpmDescriptor_t._fields_ = [ - ('Padding', ctypes.c_ubyte), - ('SnapToDiscrete', ctypes.c_ubyte), - ('NumDiscreteLevels', ctypes.c_ubyte), - ('CalculateFopt', ctypes.c_ubyte), - ('ConversionToAvfsClk', LinearInt_t), - ('Padding3', ctypes.c_uint32 * 3), - ('Padding4', ctypes.c_uint16), - ('FoptimalDc', ctypes.c_uint16), - ('FoptimalAc', ctypes.c_uint16), - ('Padding2', ctypes.c_uint16), +class DroopInt_t(Struct): pass +DroopInt_t._fields_ = [ + ('a', uint32_t), + ('b', uint32_t), + ('c', uint32_t), ] +DCS_ARCH_e = CEnum(ctypes.c_uint32) +DCS_ARCH_DISABLED = DCS_ARCH_e.define('DCS_ARCH_DISABLED', 0) +DCS_ARCH_FADCS = DCS_ARCH_e.define('DCS_ARCH_FADCS', 1) +DCS_ARCH_ASYNC = DCS_ARCH_e.define('DCS_ARCH_ASYNC', 2) -DpmDescriptor_t = struct_c__SA_DpmDescriptor_t +PPCLK_e = CEnum(ctypes.c_uint32) +PPCLK_GFXCLK = PPCLK_e.define('PPCLK_GFXCLK', 0) +PPCLK_SOCCLK = PPCLK_e.define('PPCLK_SOCCLK', 1) +PPCLK_UCLK = PPCLK_e.define('PPCLK_UCLK', 2) +PPCLK_FCLK = PPCLK_e.define('PPCLK_FCLK', 3) +PPCLK_DCLK_0 = PPCLK_e.define('PPCLK_DCLK_0', 4) +PPCLK_VCLK_0 = PPCLK_e.define('PPCLK_VCLK_0', 5) +PPCLK_DISPCLK = PPCLK_e.define('PPCLK_DISPCLK', 6) +PPCLK_DPPCLK = PPCLK_e.define('PPCLK_DPPCLK', 7) +PPCLK_DPREFCLK = PPCLK_e.define('PPCLK_DPREFCLK', 8) +PPCLK_DCFCLK = PPCLK_e.define('PPCLK_DCFCLK', 9) +PPCLK_DTBCLK = PPCLK_e.define('PPCLK_DTBCLK', 10) +PPCLK_COUNT = PPCLK_e.define('PPCLK_COUNT', 11) -# values for enumeration 'c__EA_PPT_THROTTLER_e' -c__EA_PPT_THROTTLER_e__enumvalues = { - 0: 'PPT_THROTTLER_PPT0', - 1: 'PPT_THROTTLER_PPT1', - 2: 'PPT_THROTTLER_PPT2', - 3: 'PPT_THROTTLER_PPT3', - 4: 'PPT_THROTTLER_COUNT', -} -PPT_THROTTLER_PPT0 = 0 -PPT_THROTTLER_PPT1 = 1 -PPT_THROTTLER_PPT2 = 2 -PPT_THROTTLER_PPT3 = 3 -PPT_THROTTLER_COUNT = 4 -c__EA_PPT_THROTTLER_e = ctypes.c_uint32 # enum -PPT_THROTTLER_e = c__EA_PPT_THROTTLER_e -PPT_THROTTLER_e__enumvalues = c__EA_PPT_THROTTLER_e__enumvalues +VOLTAGE_MODE_e = CEnum(ctypes.c_uint32) +VOLTAGE_MODE_PPTABLE = VOLTAGE_MODE_e.define('VOLTAGE_MODE_PPTABLE', 0) +VOLTAGE_MODE_FUSES = VOLTAGE_MODE_e.define('VOLTAGE_MODE_FUSES', 1) +VOLTAGE_MODE_COUNT = VOLTAGE_MODE_e.define('VOLTAGE_MODE_COUNT', 2) -# values for enumeration 'c__EA_TEMP_e' -c__EA_TEMP_e__enumvalues = { - 0: 'TEMP_EDGE', - 1: 'TEMP_HOTSPOT', - 2: 'TEMP_HOTSPOT_GFX', - 3: 'TEMP_HOTSPOT_SOC', - 4: 'TEMP_MEM', - 5: 'TEMP_VR_GFX', - 6: 'TEMP_VR_SOC', - 7: 'TEMP_VR_MEM0', - 8: 'TEMP_VR_MEM1', - 9: 'TEMP_LIQUID0', - 10: 'TEMP_LIQUID1', - 11: 'TEMP_PLX', - 12: 'TEMP_COUNT', -} -TEMP_EDGE = 0 -TEMP_HOTSPOT = 1 -TEMP_HOTSPOT_GFX = 2 -TEMP_HOTSPOT_SOC = 3 -TEMP_MEM = 4 -TEMP_VR_GFX = 5 -TEMP_VR_SOC = 6 -TEMP_VR_MEM0 = 7 -TEMP_VR_MEM1 = 8 -TEMP_LIQUID0 = 9 -TEMP_LIQUID1 = 10 -TEMP_PLX = 11 -TEMP_COUNT = 12 -c__EA_TEMP_e = ctypes.c_uint32 # enum -TEMP_e = c__EA_TEMP_e -TEMP_e__enumvalues = c__EA_TEMP_e__enumvalues +AVFS_VOLTAGE_TYPE_e = CEnum(ctypes.c_uint32) +AVFS_VOLTAGE_GFX = AVFS_VOLTAGE_TYPE_e.define('AVFS_VOLTAGE_GFX', 0) +AVFS_VOLTAGE_SOC = AVFS_VOLTAGE_TYPE_e.define('AVFS_VOLTAGE_SOC', 1) +AVFS_VOLTAGE_COUNT = AVFS_VOLTAGE_TYPE_e.define('AVFS_VOLTAGE_COUNT', 2) -# values for enumeration 'c__EA_TDC_THROTTLER_e' -c__EA_TDC_THROTTLER_e__enumvalues = { - 0: 'TDC_THROTTLER_GFX', - 1: 'TDC_THROTTLER_SOC', - 2: 'TDC_THROTTLER_COUNT', -} -TDC_THROTTLER_GFX = 0 -TDC_THROTTLER_SOC = 1 -TDC_THROTTLER_COUNT = 2 -c__EA_TDC_THROTTLER_e = ctypes.c_uint32 # enum -TDC_THROTTLER_e = c__EA_TDC_THROTTLER_e -TDC_THROTTLER_e__enumvalues = c__EA_TDC_THROTTLER_e__enumvalues +AVFS_TEMP_e = CEnum(ctypes.c_uint32) +AVFS_TEMP_COLD = AVFS_TEMP_e.define('AVFS_TEMP_COLD', 0) +AVFS_TEMP_HOT = AVFS_TEMP_e.define('AVFS_TEMP_HOT', 1) +AVFS_TEMP_COUNT = AVFS_TEMP_e.define('AVFS_TEMP_COUNT', 2) -# values for enumeration 'c__EA_SVI_PLANE_e' -c__EA_SVI_PLANE_e__enumvalues = { - 0: 'SVI_PLANE_VDD_GFX', - 1: 'SVI_PLANE_VDD_SOC', - 2: 'SVI_PLANE_VDDCI_MEM', - 3: 'SVI_PLANE_VDDIO_MEM', - 4: 'SVI_PLANE_COUNT', -} -SVI_PLANE_VDD_GFX = 0 -SVI_PLANE_VDD_SOC = 1 -SVI_PLANE_VDDCI_MEM = 2 -SVI_PLANE_VDDIO_MEM = 3 -SVI_PLANE_COUNT = 4 -c__EA_SVI_PLANE_e = ctypes.c_uint32 # enum -SVI_PLANE_e = c__EA_SVI_PLANE_e -SVI_PLANE_e__enumvalues = c__EA_SVI_PLANE_e__enumvalues +AVFS_D_e = CEnum(ctypes.c_uint32) +AVFS_D_G = AVFS_D_e.define('AVFS_D_G', 0) +AVFS_D_COUNT = AVFS_D_e.define('AVFS_D_COUNT', 1) -# values for enumeration 'c__EA_PMFW_VOLT_PLANE_e' -c__EA_PMFW_VOLT_PLANE_e__enumvalues = { - 0: 'PMFW_VOLT_PLANE_GFX', - 1: 'PMFW_VOLT_PLANE_SOC', - 2: 'PMFW_VOLT_PLANE_COUNT', -} -PMFW_VOLT_PLANE_GFX = 0 -PMFW_VOLT_PLANE_SOC = 1 -PMFW_VOLT_PLANE_COUNT = 2 -c__EA_PMFW_VOLT_PLANE_e = ctypes.c_uint32 # enum -PMFW_VOLT_PLANE_e = c__EA_PMFW_VOLT_PLANE_e -PMFW_VOLT_PLANE_e__enumvalues = c__EA_PMFW_VOLT_PLANE_e__enumvalues +UCLK_DIV_e = CEnum(ctypes.c_uint32) +UCLK_DIV_BY_1 = UCLK_DIV_e.define('UCLK_DIV_BY_1', 0) +UCLK_DIV_BY_2 = UCLK_DIV_e.define('UCLK_DIV_BY_2', 1) +UCLK_DIV_BY_4 = UCLK_DIV_e.define('UCLK_DIV_BY_4', 2) +UCLK_DIV_BY_8 = UCLK_DIV_e.define('UCLK_DIV_BY_8', 3) -# values for enumeration 'c__EA_CUSTOMER_VARIANT_e' -c__EA_CUSTOMER_VARIANT_e__enumvalues = { - 0: 'CUSTOMER_VARIANT_ROW', - 1: 'CUSTOMER_VARIANT_FALCON', - 2: 'CUSTOMER_VARIANT_COUNT', -} -CUSTOMER_VARIANT_ROW = 0 -CUSTOMER_VARIANT_FALCON = 1 -CUSTOMER_VARIANT_COUNT = 2 -c__EA_CUSTOMER_VARIANT_e = ctypes.c_uint32 # enum -CUSTOMER_VARIANT_e = c__EA_CUSTOMER_VARIANT_e -CUSTOMER_VARIANT_e__enumvalues = c__EA_CUSTOMER_VARIANT_e__enumvalues +GpioIntPolarity_e = CEnum(ctypes.c_uint32) +GPIO_INT_POLARITY_ACTIVE_LOW = GpioIntPolarity_e.define('GPIO_INT_POLARITY_ACTIVE_LOW', 0) +GPIO_INT_POLARITY_ACTIVE_HIGH = GpioIntPolarity_e.define('GPIO_INT_POLARITY_ACTIVE_HIGH', 1) -# values for enumeration 'c__EA_POWER_SOURCE_e' -c__EA_POWER_SOURCE_e__enumvalues = { - 0: 'POWER_SOURCE_AC', - 1: 'POWER_SOURCE_DC', - 2: 'POWER_SOURCE_COUNT', -} -POWER_SOURCE_AC = 0 -POWER_SOURCE_DC = 1 -POWER_SOURCE_COUNT = 2 -c__EA_POWER_SOURCE_e = ctypes.c_uint32 # enum -POWER_SOURCE_e = c__EA_POWER_SOURCE_e -POWER_SOURCE_e__enumvalues = c__EA_POWER_SOURCE_e__enumvalues +PwrConfig_e = CEnum(ctypes.c_uint32) +PWR_CONFIG_TDP = PwrConfig_e.define('PWR_CONFIG_TDP', 0) +PWR_CONFIG_TGP = PwrConfig_e.define('PWR_CONFIG_TGP', 1) +PWR_CONFIG_TCP_ESTIMATED = PwrConfig_e.define('PWR_CONFIG_TCP_ESTIMATED', 2) +PWR_CONFIG_TCP_MEASURED = PwrConfig_e.define('PWR_CONFIG_TCP_MEASURED', 3) +PWR_CONFIG_TBP_DESKTOP = PwrConfig_e.define('PWR_CONFIG_TBP_DESKTOP', 4) +PWR_CONFIG_TBP_MOBILE = PwrConfig_e.define('PWR_CONFIG_TBP_MOBILE', 5) -# values for enumeration 'c__EA_MEM_VENDOR_e' -c__EA_MEM_VENDOR_e__enumvalues = { - 0: 'MEM_VENDOR_PLACEHOLDER0', - 1: 'MEM_VENDOR_SAMSUNG', - 2: 'MEM_VENDOR_INFINEON', - 3: 'MEM_VENDOR_ELPIDA', - 4: 'MEM_VENDOR_ETRON', - 5: 'MEM_VENDOR_NANYA', - 6: 'MEM_VENDOR_HYNIX', - 7: 'MEM_VENDOR_MOSEL', - 8: 'MEM_VENDOR_WINBOND', - 9: 'MEM_VENDOR_ESMT', - 10: 'MEM_VENDOR_PLACEHOLDER1', - 11: 'MEM_VENDOR_PLACEHOLDER2', - 12: 'MEM_VENDOR_PLACEHOLDER3', - 13: 'MEM_VENDOR_PLACEHOLDER4', - 14: 'MEM_VENDOR_PLACEHOLDER5', - 15: 'MEM_VENDOR_MICRON', - 16: 'MEM_VENDOR_COUNT', -} -MEM_VENDOR_PLACEHOLDER0 = 0 -MEM_VENDOR_SAMSUNG = 1 -MEM_VENDOR_INFINEON = 2 -MEM_VENDOR_ELPIDA = 3 -MEM_VENDOR_ETRON = 4 -MEM_VENDOR_NANYA = 5 -MEM_VENDOR_HYNIX = 6 -MEM_VENDOR_MOSEL = 7 -MEM_VENDOR_WINBOND = 8 -MEM_VENDOR_ESMT = 9 -MEM_VENDOR_PLACEHOLDER1 = 10 -MEM_VENDOR_PLACEHOLDER2 = 11 -MEM_VENDOR_PLACEHOLDER3 = 12 -MEM_VENDOR_PLACEHOLDER4 = 13 -MEM_VENDOR_PLACEHOLDER5 = 14 -MEM_VENDOR_MICRON = 15 -MEM_VENDOR_COUNT = 16 -c__EA_MEM_VENDOR_e = ctypes.c_uint32 # enum -MEM_VENDOR_e = c__EA_MEM_VENDOR_e -MEM_VENDOR_e__enumvalues = c__EA_MEM_VENDOR_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_HW_FUSE_e' -c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', - 1: 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 2: 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', - 3: 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 4: 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', - 5: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 6: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 7: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 8: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 9: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 10: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 11: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 12: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 13: 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 14: 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', - 15: 'PP_GRTAVFS_HW_ZONE0_VF', - 16: 'PP_GRTAVFS_HW_ZONE1_VF1', - 17: 'PP_GRTAVFS_HW_ZONE2_VF2', - 18: 'PP_GRTAVFS_HW_ZONE3_VF3', - 19: 'PP_GRTAVFS_HW_VOLTAGE_GB', - 20: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 21: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 22: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 23: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 24: 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 25: 'PP_GRTAVFS_HW_RESERVED_0', - 26: 'PP_GRTAVFS_HW_RESERVED_1', - 27: 'PP_GRTAVFS_HW_RESERVED_2', - 28: 'PP_GRTAVFS_HW_RESERVED_3', - 29: 'PP_GRTAVFS_HW_RESERVED_4', - 30: 'PP_GRTAVFS_HW_RESERVED_5', - 31: 'PP_GRTAVFS_HW_RESERVED_6', - 32: 'PP_GRTAVFS_HW_FUSE_COUNT', -} -PP_GRTAVFS_HW_CPO_CTL_ZONE0 = 0 -PP_GRTAVFS_HW_CPO_CTL_ZONE1 = 1 -PP_GRTAVFS_HW_CPO_CTL_ZONE2 = 2 -PP_GRTAVFS_HW_CPO_CTL_ZONE3 = 3 -PP_GRTAVFS_HW_CPO_CTL_ZONE4 = 4 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = 5 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = 6 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = 7 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = 8 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = 9 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = 10 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = 11 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = 12 -PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = 13 -PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = 14 -PP_GRTAVFS_HW_ZONE0_VF = 15 -PP_GRTAVFS_HW_ZONE1_VF1 = 16 -PP_GRTAVFS_HW_ZONE2_VF2 = 17 -PP_GRTAVFS_HW_ZONE3_VF3 = 18 -PP_GRTAVFS_HW_VOLTAGE_GB = 19 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = 20 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = 21 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = 22 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = 23 -PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = 24 -PP_GRTAVFS_HW_RESERVED_0 = 25 -PP_GRTAVFS_HW_RESERVED_1 = 26 -PP_GRTAVFS_HW_RESERVED_2 = 27 -PP_GRTAVFS_HW_RESERVED_3 = 28 -PP_GRTAVFS_HW_RESERVED_4 = 29 -PP_GRTAVFS_HW_RESERVED_5 = 30 -PP_GRTAVFS_HW_RESERVED_6 = 31 -PP_GRTAVFS_HW_FUSE_COUNT = 32 -c__EA_PP_GRTAVFS_HW_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_HW_FUSE_e = c__EA_PP_GRTAVFS_HW_FUSE_e -PP_GRTAVFS_HW_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_HW_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e' -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 1: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 2: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 3: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 4: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 5: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 6: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 7: 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 8: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 9: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 10: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 11: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 12: 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', - 13: 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', -} -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = 0 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = 1 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = 2 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = 3 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = 4 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = 5 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = 6 -PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = 7 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = 8 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = 9 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = 10 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = 11 -PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = 12 -PP_GRTAVFS_FW_COMMON_FUSE_COUNT = 13 -c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_COMMON_FUSE_e = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e -PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues - -# values for enumeration 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e' -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = { - 0: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 1: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 2: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 3: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 4: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 5: 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 6: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 7: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 8: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 9: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 10: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 11: 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 12: 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 13: 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 14: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 15: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 16: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 17: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 18: 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 19: 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', -} -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = 0 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = 1 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = 2 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = 3 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = 4 -PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = 5 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = 6 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = 7 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = 8 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = 9 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = 10 -PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = 11 -PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = 12 -PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = 13 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = 14 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = 15 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = 16 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = 17 -PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = 18 -PP_GRTAVFS_FW_SEP_FUSE_COUNT = 19 -c__EA_PP_GRTAVFS_FW_SEP_FUSE_e = ctypes.c_uint32 # enum -PP_GRTAVFS_FW_SEP_FUSE_e = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e -PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues = c__EA_PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues -class struct_c__SA_SviTelemetryScale_t(Structure): - pass - -struct_c__SA_SviTelemetryScale_t._pack_ = 1 # source:False -struct_c__SA_SviTelemetryScale_t._fields_ = [ - ('Offset', ctypes.c_byte), - ('Padding', ctypes.c_ubyte), - ('MaxCurrent', ctypes.c_uint16), +class DpmDescriptor_t(Struct): pass +DpmDescriptor_t._fields_ = [ + ('Padding', uint8_t), + ('SnapToDiscrete', uint8_t), + ('NumDiscreteLevels', uint8_t), + ('CalculateFopt', uint8_t), + ('ConversionToAvfsClk', LinearInt_t), + ('Padding3', (uint32_t * 3)), + ('Padding4', uint16_t), + ('FoptimalDc', uint16_t), + ('FoptimalAc', uint16_t), + ('Padding2', uint16_t), ] +PPT_THROTTLER_e = CEnum(ctypes.c_uint32) +PPT_THROTTLER_PPT0 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT0', 0) +PPT_THROTTLER_PPT1 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT1', 1) +PPT_THROTTLER_PPT2 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT2', 2) +PPT_THROTTLER_PPT3 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT3', 3) +PPT_THROTTLER_COUNT = PPT_THROTTLER_e.define('PPT_THROTTLER_COUNT', 4) -SviTelemetryScale_t = struct_c__SA_SviTelemetryScale_t +TEMP_e = CEnum(ctypes.c_uint32) +TEMP_EDGE = TEMP_e.define('TEMP_EDGE', 0) +TEMP_HOTSPOT = TEMP_e.define('TEMP_HOTSPOT', 1) +TEMP_HOTSPOT_GFX = TEMP_e.define('TEMP_HOTSPOT_GFX', 2) +TEMP_HOTSPOT_SOC = TEMP_e.define('TEMP_HOTSPOT_SOC', 3) +TEMP_MEM = TEMP_e.define('TEMP_MEM', 4) +TEMP_VR_GFX = TEMP_e.define('TEMP_VR_GFX', 5) +TEMP_VR_SOC = TEMP_e.define('TEMP_VR_SOC', 6) +TEMP_VR_MEM0 = TEMP_e.define('TEMP_VR_MEM0', 7) +TEMP_VR_MEM1 = TEMP_e.define('TEMP_VR_MEM1', 8) +TEMP_LIQUID0 = TEMP_e.define('TEMP_LIQUID0', 9) +TEMP_LIQUID1 = TEMP_e.define('TEMP_LIQUID1', 10) +TEMP_PLX = TEMP_e.define('TEMP_PLX', 11) +TEMP_COUNT = TEMP_e.define('TEMP_COUNT', 12) -# values for enumeration 'c__EA_PP_OD_POWER_FEATURE_e' -c__EA_PP_OD_POWER_FEATURE_e__enumvalues = { - 0: 'PP_OD_POWER_FEATURE_ALWAYS_ENABLED', - 1: 'PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING', - 2: 'PP_OD_POWER_FEATURE_ALWAYS_DISABLED', -} -PP_OD_POWER_FEATURE_ALWAYS_ENABLED = 0 -PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING = 1 -PP_OD_POWER_FEATURE_ALWAYS_DISABLED = 2 -c__EA_PP_OD_POWER_FEATURE_e = ctypes.c_uint32 # enum -PP_OD_POWER_FEATURE_e = c__EA_PP_OD_POWER_FEATURE_e -PP_OD_POWER_FEATURE_e__enumvalues = c__EA_PP_OD_POWER_FEATURE_e__enumvalues +TDC_THROTTLER_e = CEnum(ctypes.c_uint32) +TDC_THROTTLER_GFX = TDC_THROTTLER_e.define('TDC_THROTTLER_GFX', 0) +TDC_THROTTLER_SOC = TDC_THROTTLER_e.define('TDC_THROTTLER_SOC', 1) +TDC_THROTTLER_COUNT = TDC_THROTTLER_e.define('TDC_THROTTLER_COUNT', 2) -# values for enumeration 'c__EA_FanMode_e' -c__EA_FanMode_e__enumvalues = { - 0: 'FAN_MODE_AUTO', - 1: 'FAN_MODE_MANUAL_LINEAR', -} -FAN_MODE_AUTO = 0 -FAN_MODE_MANUAL_LINEAR = 1 -c__EA_FanMode_e = ctypes.c_uint32 # enum -FanMode_e = c__EA_FanMode_e -FanMode_e__enumvalues = c__EA_FanMode_e__enumvalues +SVI_PLANE_e = CEnum(ctypes.c_uint32) +SVI_PLANE_VDD_GFX = SVI_PLANE_e.define('SVI_PLANE_VDD_GFX', 0) +SVI_PLANE_VDD_SOC = SVI_PLANE_e.define('SVI_PLANE_VDD_SOC', 1) +SVI_PLANE_VDDCI_MEM = SVI_PLANE_e.define('SVI_PLANE_VDDCI_MEM', 2) +SVI_PLANE_VDDIO_MEM = SVI_PLANE_e.define('SVI_PLANE_VDDIO_MEM', 3) +SVI_PLANE_COUNT = SVI_PLANE_e.define('SVI_PLANE_COUNT', 4) -# values for enumeration 'c__EA_OD_FAIL_e' -c__EA_OD_FAIL_e__enumvalues = { - 0: 'OD_NO_ERROR', - 1: 'OD_REQUEST_ADVANCED_NOT_SUPPORTED', - 2: 'OD_UNSUPPORTED_FEATURE', - 3: 'OD_INVALID_FEATURE_COMBO_ERROR', - 4: 'OD_GFXCLK_VF_CURVE_OFFSET_ERROR', - 5: 'OD_VDD_GFX_VMAX_ERROR', - 6: 'OD_VDD_SOC_VMAX_ERROR', - 7: 'OD_PPT_ERROR', - 8: 'OD_FAN_MIN_PWM_ERROR', - 9: 'OD_FAN_ACOUSTIC_TARGET_ERROR', - 10: 'OD_FAN_ACOUSTIC_LIMIT_ERROR', - 11: 'OD_FAN_TARGET_TEMP_ERROR', - 12: 'OD_FAN_ZERO_RPM_STOP_TEMP_ERROR', - 13: 'OD_FAN_CURVE_PWM_ERROR', - 14: 'OD_FAN_CURVE_TEMP_ERROR', - 15: 'OD_FULL_CTRL_GFXCLK_ERROR', - 16: 'OD_FULL_CTRL_UCLK_ERROR', - 17: 'OD_FULL_CTRL_FCLK_ERROR', - 18: 'OD_FULL_CTRL_VDD_GFX_ERROR', - 19: 'OD_FULL_CTRL_VDD_SOC_ERROR', - 20: 'OD_TDC_ERROR', - 21: 'OD_GFXCLK_ERROR', - 22: 'OD_UCLK_ERROR', - 23: 'OD_FCLK_ERROR', - 24: 'OD_OP_TEMP_ERROR', - 25: 'OD_OP_GFX_EDC_ERROR', - 26: 'OD_OP_GFX_PCC_ERROR', - 27: 'OD_POWER_FEATURE_CTRL_ERROR', -} -OD_NO_ERROR = 0 -OD_REQUEST_ADVANCED_NOT_SUPPORTED = 1 -OD_UNSUPPORTED_FEATURE = 2 -OD_INVALID_FEATURE_COMBO_ERROR = 3 -OD_GFXCLK_VF_CURVE_OFFSET_ERROR = 4 -OD_VDD_GFX_VMAX_ERROR = 5 -OD_VDD_SOC_VMAX_ERROR = 6 -OD_PPT_ERROR = 7 -OD_FAN_MIN_PWM_ERROR = 8 -OD_FAN_ACOUSTIC_TARGET_ERROR = 9 -OD_FAN_ACOUSTIC_LIMIT_ERROR = 10 -OD_FAN_TARGET_TEMP_ERROR = 11 -OD_FAN_ZERO_RPM_STOP_TEMP_ERROR = 12 -OD_FAN_CURVE_PWM_ERROR = 13 -OD_FAN_CURVE_TEMP_ERROR = 14 -OD_FULL_CTRL_GFXCLK_ERROR = 15 -OD_FULL_CTRL_UCLK_ERROR = 16 -OD_FULL_CTRL_FCLK_ERROR = 17 -OD_FULL_CTRL_VDD_GFX_ERROR = 18 -OD_FULL_CTRL_VDD_SOC_ERROR = 19 -OD_TDC_ERROR = 20 -OD_GFXCLK_ERROR = 21 -OD_UCLK_ERROR = 22 -OD_FCLK_ERROR = 23 -OD_OP_TEMP_ERROR = 24 -OD_OP_GFX_EDC_ERROR = 25 -OD_OP_GFX_PCC_ERROR = 26 -OD_POWER_FEATURE_CTRL_ERROR = 27 -c__EA_OD_FAIL_e = ctypes.c_uint32 # enum -OD_FAIL_e = c__EA_OD_FAIL_e -OD_FAIL_e__enumvalues = c__EA_OD_FAIL_e__enumvalues -class struct_c__SA_OverDriveTable_t(Structure): - pass +PMFW_VOLT_PLANE_e = CEnum(ctypes.c_uint32) +PMFW_VOLT_PLANE_GFX = PMFW_VOLT_PLANE_e.define('PMFW_VOLT_PLANE_GFX', 0) +PMFW_VOLT_PLANE_SOC = PMFW_VOLT_PLANE_e.define('PMFW_VOLT_PLANE_SOC', 1) +PMFW_VOLT_PLANE_COUNT = PMFW_VOLT_PLANE_e.define('PMFW_VOLT_PLANE_COUNT', 2) -struct_c__SA_OverDriveTable_t._pack_ = 1 # source:False -struct_c__SA_OverDriveTable_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), - ('VddGfxVmax', ctypes.c_uint16), - ('VddSocVmax', ctypes.c_uint16), - ('IdlePwrSavingFeaturesCtrl', ctypes.c_ubyte), - ('RuntimePwrSavingFeaturesCtrl', ctypes.c_ubyte), - ('Padding', ctypes.c_uint16), - ('GfxclkFoffset', ctypes.c_int16), - ('Padding1', ctypes.c_uint16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('FclkFmin', ctypes.c_uint16), - ('FclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte * 6), - ('FanLinearTempPoints', ctypes.c_ubyte * 6), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanZeroRpmStopTemp', ctypes.c_ubyte), - ('FanMode', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('AdvancedOdModeEnabled', ctypes.c_ubyte), - ('Padding2', ctypes.c_ubyte * 3), - ('GfxVoltageFullCtrlMode', ctypes.c_uint16), - ('SocVoltageFullCtrlMode', ctypes.c_uint16), - ('GfxclkFullCtrlMode', ctypes.c_uint16), - ('UclkFullCtrlMode', ctypes.c_uint16), - ('FclkFullCtrlMode', ctypes.c_uint16), - ('Padding3', ctypes.c_uint16), - ('GfxEdc', ctypes.c_int16), - ('GfxPccLimitControl', ctypes.c_int16), - ('GfxclkFmaxVmax', ctypes.c_uint16), - ('GfxclkFmaxVmaxTemperature', ctypes.c_ubyte), - ('Padding4', ctypes.c_ubyte * 1), - ('Spare', ctypes.c_uint32 * 9), - ('MmHubPadding', ctypes.c_uint32 * 8), +CUSTOMER_VARIANT_e = CEnum(ctypes.c_uint32) +CUSTOMER_VARIANT_ROW = CUSTOMER_VARIANT_e.define('CUSTOMER_VARIANT_ROW', 0) +CUSTOMER_VARIANT_FALCON = CUSTOMER_VARIANT_e.define('CUSTOMER_VARIANT_FALCON', 1) +CUSTOMER_VARIANT_COUNT = CUSTOMER_VARIANT_e.define('CUSTOMER_VARIANT_COUNT', 2) + +POWER_SOURCE_e = CEnum(ctypes.c_uint32) +POWER_SOURCE_AC = POWER_SOURCE_e.define('POWER_SOURCE_AC', 0) +POWER_SOURCE_DC = POWER_SOURCE_e.define('POWER_SOURCE_DC', 1) +POWER_SOURCE_COUNT = POWER_SOURCE_e.define('POWER_SOURCE_COUNT', 2) + +MEM_VENDOR_e = CEnum(ctypes.c_uint32) +MEM_VENDOR_PLACEHOLDER0 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER0', 0) +MEM_VENDOR_SAMSUNG = MEM_VENDOR_e.define('MEM_VENDOR_SAMSUNG', 1) +MEM_VENDOR_INFINEON = MEM_VENDOR_e.define('MEM_VENDOR_INFINEON', 2) +MEM_VENDOR_ELPIDA = MEM_VENDOR_e.define('MEM_VENDOR_ELPIDA', 3) +MEM_VENDOR_ETRON = MEM_VENDOR_e.define('MEM_VENDOR_ETRON', 4) +MEM_VENDOR_NANYA = MEM_VENDOR_e.define('MEM_VENDOR_NANYA', 5) +MEM_VENDOR_HYNIX = MEM_VENDOR_e.define('MEM_VENDOR_HYNIX', 6) +MEM_VENDOR_MOSEL = MEM_VENDOR_e.define('MEM_VENDOR_MOSEL', 7) +MEM_VENDOR_WINBOND = MEM_VENDOR_e.define('MEM_VENDOR_WINBOND', 8) +MEM_VENDOR_ESMT = MEM_VENDOR_e.define('MEM_VENDOR_ESMT', 9) +MEM_VENDOR_PLACEHOLDER1 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER1', 10) +MEM_VENDOR_PLACEHOLDER2 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER2', 11) +MEM_VENDOR_PLACEHOLDER3 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER3', 12) +MEM_VENDOR_PLACEHOLDER4 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER4', 13) +MEM_VENDOR_PLACEHOLDER5 = MEM_VENDOR_e.define('MEM_VENDOR_PLACEHOLDER5', 14) +MEM_VENDOR_MICRON = MEM_VENDOR_e.define('MEM_VENDOR_MICRON', 15) +MEM_VENDOR_COUNT = MEM_VENDOR_e.define('MEM_VENDOR_COUNT', 16) + +PP_GRTAVFS_HW_FUSE_e = CEnum(ctypes.c_uint32) +PP_GRTAVFS_HW_CPO_CTL_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE0', 0) +PP_GRTAVFS_HW_CPO_CTL_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE1', 1) +PP_GRTAVFS_HW_CPO_CTL_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE2', 2) +PP_GRTAVFS_HW_CPO_CTL_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE3', 3) +PP_GRTAVFS_HW_CPO_CTL_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_CTL_ZONE4', 4) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', 5) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', 6) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', 7) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', 8) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', 9) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', 10) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', 11) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', 12) +PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', 13) +PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 14) +PP_GRTAVFS_HW_ZONE0_VF = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE0_VF', 15) +PP_GRTAVFS_HW_ZONE1_VF1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE1_VF1', 16) +PP_GRTAVFS_HW_ZONE2_VF2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE2_VF2', 17) +PP_GRTAVFS_HW_ZONE3_VF3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_ZONE3_VF3', 18) +PP_GRTAVFS_HW_VOLTAGE_GB = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_VOLTAGE_GB', 19) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', 20) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', 21) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', 22) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', 23) +PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', 24) +PP_GRTAVFS_HW_RESERVED_0 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_0', 25) +PP_GRTAVFS_HW_RESERVED_1 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_1', 26) +PP_GRTAVFS_HW_RESERVED_2 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_2', 27) +PP_GRTAVFS_HW_RESERVED_3 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_3', 28) +PP_GRTAVFS_HW_RESERVED_4 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_4', 29) +PP_GRTAVFS_HW_RESERVED_5 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_5', 30) +PP_GRTAVFS_HW_RESERVED_6 = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_RESERVED_6', 31) +PP_GRTAVFS_HW_FUSE_COUNT = PP_GRTAVFS_HW_FUSE_e.define('PP_GRTAVFS_HW_FUSE_COUNT', 32) + +PP_GRTAVFS_FW_COMMON_FUSE_e = CEnum(ctypes.c_uint32) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', 0) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', 1) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', 2) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', 3) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', 4) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', 5) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', 6) +PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', 7) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', 8) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', 9) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', 10) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', 11) +PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4 = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 12) +PP_GRTAVFS_FW_COMMON_FUSE_COUNT = PP_GRTAVFS_FW_COMMON_FUSE_e.define('PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 13) + +PP_GRTAVFS_FW_SEP_FUSE_e = CEnum(ctypes.c_uint32) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', 0) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', 1) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', 2) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', 3) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', 4) +PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', 5) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', 6) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', 7) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', 8) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', 9) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', 10) +PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', 11) +PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', 12) +PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', 13) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', 14) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', 15) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', 16) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', 17) +PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', 18) +PP_GRTAVFS_FW_SEP_FUSE_COUNT = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_COUNT', 19) + +class SviTelemetryScale_t(Struct): pass +int8_t = ctypes.c_char +SviTelemetryScale_t._fields_ = [ + ('Offset', int8_t), + ('Padding', uint8_t), + ('MaxCurrent', uint16_t), ] +PP_OD_POWER_FEATURE_e = CEnum(ctypes.c_uint32) +PP_OD_POWER_FEATURE_ALWAYS_ENABLED = PP_OD_POWER_FEATURE_e.define('PP_OD_POWER_FEATURE_ALWAYS_ENABLED', 0) +PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING = PP_OD_POWER_FEATURE_e.define('PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING', 1) +PP_OD_POWER_FEATURE_ALWAYS_DISABLED = PP_OD_POWER_FEATURE_e.define('PP_OD_POWER_FEATURE_ALWAYS_DISABLED', 2) -OverDriveTable_t = struct_c__SA_OverDriveTable_t -class struct_c__SA_OverDriveTableExternal_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('OverDriveTable', OverDriveTable_t), - ] +FanMode_e = CEnum(ctypes.c_uint32) +FAN_MODE_AUTO = FanMode_e.define('FAN_MODE_AUTO', 0) +FAN_MODE_MANUAL_LINEAR = FanMode_e.define('FAN_MODE_MANUAL_LINEAR', 1) -OverDriveTableExternal_t = struct_c__SA_OverDriveTableExternal_t -class struct_c__SA_OverDriveLimits_t(Structure): - pass +OD_FAIL_e = CEnum(ctypes.c_uint32) +OD_NO_ERROR = OD_FAIL_e.define('OD_NO_ERROR', 0) +OD_REQUEST_ADVANCED_NOT_SUPPORTED = OD_FAIL_e.define('OD_REQUEST_ADVANCED_NOT_SUPPORTED', 1) +OD_UNSUPPORTED_FEATURE = OD_FAIL_e.define('OD_UNSUPPORTED_FEATURE', 2) +OD_INVALID_FEATURE_COMBO_ERROR = OD_FAIL_e.define('OD_INVALID_FEATURE_COMBO_ERROR', 3) +OD_GFXCLK_VF_CURVE_OFFSET_ERROR = OD_FAIL_e.define('OD_GFXCLK_VF_CURVE_OFFSET_ERROR', 4) +OD_VDD_GFX_VMAX_ERROR = OD_FAIL_e.define('OD_VDD_GFX_VMAX_ERROR', 5) +OD_VDD_SOC_VMAX_ERROR = OD_FAIL_e.define('OD_VDD_SOC_VMAX_ERROR', 6) +OD_PPT_ERROR = OD_FAIL_e.define('OD_PPT_ERROR', 7) +OD_FAN_MIN_PWM_ERROR = OD_FAIL_e.define('OD_FAN_MIN_PWM_ERROR', 8) +OD_FAN_ACOUSTIC_TARGET_ERROR = OD_FAIL_e.define('OD_FAN_ACOUSTIC_TARGET_ERROR', 9) +OD_FAN_ACOUSTIC_LIMIT_ERROR = OD_FAIL_e.define('OD_FAN_ACOUSTIC_LIMIT_ERROR', 10) +OD_FAN_TARGET_TEMP_ERROR = OD_FAIL_e.define('OD_FAN_TARGET_TEMP_ERROR', 11) +OD_FAN_ZERO_RPM_STOP_TEMP_ERROR = OD_FAIL_e.define('OD_FAN_ZERO_RPM_STOP_TEMP_ERROR', 12) +OD_FAN_CURVE_PWM_ERROR = OD_FAIL_e.define('OD_FAN_CURVE_PWM_ERROR', 13) +OD_FAN_CURVE_TEMP_ERROR = OD_FAIL_e.define('OD_FAN_CURVE_TEMP_ERROR', 14) +OD_FULL_CTRL_GFXCLK_ERROR = OD_FAIL_e.define('OD_FULL_CTRL_GFXCLK_ERROR', 15) +OD_FULL_CTRL_UCLK_ERROR = OD_FAIL_e.define('OD_FULL_CTRL_UCLK_ERROR', 16) +OD_FULL_CTRL_FCLK_ERROR = OD_FAIL_e.define('OD_FULL_CTRL_FCLK_ERROR', 17) +OD_FULL_CTRL_VDD_GFX_ERROR = OD_FAIL_e.define('OD_FULL_CTRL_VDD_GFX_ERROR', 18) +OD_FULL_CTRL_VDD_SOC_ERROR = OD_FAIL_e.define('OD_FULL_CTRL_VDD_SOC_ERROR', 19) +OD_TDC_ERROR = OD_FAIL_e.define('OD_TDC_ERROR', 20) +OD_GFXCLK_ERROR = OD_FAIL_e.define('OD_GFXCLK_ERROR', 21) +OD_UCLK_ERROR = OD_FAIL_e.define('OD_UCLK_ERROR', 22) +OD_FCLK_ERROR = OD_FAIL_e.define('OD_FCLK_ERROR', 23) +OD_OP_TEMP_ERROR = OD_FAIL_e.define('OD_OP_TEMP_ERROR', 24) +OD_OP_GFX_EDC_ERROR = OD_FAIL_e.define('OD_OP_GFX_EDC_ERROR', 25) +OD_OP_GFX_PCC_ERROR = OD_FAIL_e.define('OD_OP_GFX_PCC_ERROR', 26) +OD_POWER_FEATURE_CTRL_ERROR = OD_FAIL_e.define('OD_POWER_FEATURE_CTRL_ERROR', 27) -struct_c__SA_OverDriveLimits_t._pack_ = 1 # source:False -struct_c__SA_OverDriveLimits_t._fields_ = [ - ('FeatureCtrlMask', ctypes.c_uint32), - ('VoltageOffsetPerZoneBoundary', ctypes.c_int16 * 6), - ('VddGfxVmax', ctypes.c_uint16), - ('VddSocVmax', ctypes.c_uint16), - ('GfxclkFoffset', ctypes.c_int16), - ('Padding', ctypes.c_uint16), - ('UclkFmin', ctypes.c_uint16), - ('UclkFmax', ctypes.c_uint16), - ('FclkFmin', ctypes.c_uint16), - ('FclkFmax', ctypes.c_uint16), - ('Ppt', ctypes.c_int16), - ('Tdc', ctypes.c_int16), - ('FanLinearPwmPoints', ctypes.c_ubyte * 6), - ('FanLinearTempPoints', ctypes.c_ubyte * 6), - ('FanMinimumPwm', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('MaxOpTemp', ctypes.c_ubyte), - ('Padding1', ctypes.c_ubyte * 2), - ('GfxVoltageFullCtrlMode', ctypes.c_uint16), - ('SocVoltageFullCtrlMode', ctypes.c_uint16), - ('GfxclkFullCtrlMode', ctypes.c_uint16), - ('UclkFullCtrlMode', ctypes.c_uint16), - ('FclkFullCtrlMode', ctypes.c_uint16), - ('GfxEdc', ctypes.c_int16), - ('GfxPccLimitControl', ctypes.c_int16), - ('Padding2', ctypes.c_int16), - ('Spare', ctypes.c_uint32 * 5), +class OverDriveTable_t(Struct): pass +int16_t = ctypes.c_int16 +OverDriveTable_t._fields_ = [ + ('FeatureCtrlMask', uint32_t), + ('VoltageOffsetPerZoneBoundary', (int16_t * 6)), + ('VddGfxVmax', uint16_t), + ('VddSocVmax', uint16_t), + ('IdlePwrSavingFeaturesCtrl', uint8_t), + ('RuntimePwrSavingFeaturesCtrl', uint8_t), + ('Padding', uint16_t), + ('GfxclkFoffset', int16_t), + ('Padding1', uint16_t), + ('UclkFmin', uint16_t), + ('UclkFmax', uint16_t), + ('FclkFmin', uint16_t), + ('FclkFmax', uint16_t), + ('Ppt', int16_t), + ('Tdc', int16_t), + ('FanLinearPwmPoints', (uint8_t * 6)), + ('FanLinearTempPoints', (uint8_t * 6)), + ('FanMinimumPwm', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanTargetTemperature', uint16_t), + ('FanZeroRpmEnable', uint8_t), + ('FanZeroRpmStopTemp', uint8_t), + ('FanMode', uint8_t), + ('MaxOpTemp', uint8_t), + ('AdvancedOdModeEnabled', uint8_t), + ('Padding2', (uint8_t * 3)), + ('GfxVoltageFullCtrlMode', uint16_t), + ('SocVoltageFullCtrlMode', uint16_t), + ('GfxclkFullCtrlMode', uint16_t), + ('UclkFullCtrlMode', uint16_t), + ('FclkFullCtrlMode', uint16_t), + ('Padding3', uint16_t), + ('GfxEdc', int16_t), + ('GfxPccLimitControl', int16_t), + ('GfxclkFmaxVmax', uint16_t), + ('GfxclkFmaxVmaxTemperature', uint8_t), + ('Padding4', (uint8_t * 1)), + ('Spare', (uint32_t * 9)), + ('MmHubPadding', (uint32_t * 8)), ] - -OverDriveLimits_t = struct_c__SA_OverDriveLimits_t - -# values for enumeration 'c__EA_BOARD_GPIO_TYPE_e' -c__EA_BOARD_GPIO_TYPE_e__enumvalues = { - 0: 'BOARD_GPIO_SMUIO_0', - 1: 'BOARD_GPIO_SMUIO_1', - 2: 'BOARD_GPIO_SMUIO_2', - 3: 'BOARD_GPIO_SMUIO_3', - 4: 'BOARD_GPIO_SMUIO_4', - 5: 'BOARD_GPIO_SMUIO_5', - 6: 'BOARD_GPIO_SMUIO_6', - 7: 'BOARD_GPIO_SMUIO_7', - 8: 'BOARD_GPIO_SMUIO_8', - 9: 'BOARD_GPIO_SMUIO_9', - 10: 'BOARD_GPIO_SMUIO_10', - 11: 'BOARD_GPIO_SMUIO_11', - 12: 'BOARD_GPIO_SMUIO_12', - 13: 'BOARD_GPIO_SMUIO_13', - 14: 'BOARD_GPIO_SMUIO_14', - 15: 'BOARD_GPIO_SMUIO_15', - 16: 'BOARD_GPIO_SMUIO_16', - 17: 'BOARD_GPIO_SMUIO_17', - 18: 'BOARD_GPIO_SMUIO_18', - 19: 'BOARD_GPIO_SMUIO_19', - 20: 'BOARD_GPIO_SMUIO_20', - 21: 'BOARD_GPIO_SMUIO_21', - 22: 'BOARD_GPIO_SMUIO_22', - 23: 'BOARD_GPIO_SMUIO_23', - 24: 'BOARD_GPIO_SMUIO_24', - 25: 'BOARD_GPIO_SMUIO_25', - 26: 'BOARD_GPIO_SMUIO_26', - 27: 'BOARD_GPIO_SMUIO_27', - 28: 'BOARD_GPIO_SMUIO_28', - 29: 'BOARD_GPIO_SMUIO_29', - 30: 'BOARD_GPIO_SMUIO_30', - 31: 'BOARD_GPIO_SMUIO_31', - 32: 'MAX_BOARD_GPIO_SMUIO_NUM', - 33: 'BOARD_GPIO_DC_GEN_A', - 34: 'BOARD_GPIO_DC_GEN_B', - 35: 'BOARD_GPIO_DC_GEN_C', - 36: 'BOARD_GPIO_DC_GEN_D', - 37: 'BOARD_GPIO_DC_GEN_E', - 38: 'BOARD_GPIO_DC_GEN_F', - 39: 'BOARD_GPIO_DC_GEN_G', - 40: 'BOARD_GPIO_DC_GENLK_CLK', - 41: 'BOARD_GPIO_DC_GENLK_VSYNC', - 42: 'BOARD_GPIO_DC_SWAPLOCK_A', - 43: 'BOARD_GPIO_DC_SWAPLOCK_B', - 44: 'MAX_BOARD_DC_GPIO_NUM', - 45: 'BOARD_GPIO_LV_EN', -} -BOARD_GPIO_SMUIO_0 = 0 -BOARD_GPIO_SMUIO_1 = 1 -BOARD_GPIO_SMUIO_2 = 2 -BOARD_GPIO_SMUIO_3 = 3 -BOARD_GPIO_SMUIO_4 = 4 -BOARD_GPIO_SMUIO_5 = 5 -BOARD_GPIO_SMUIO_6 = 6 -BOARD_GPIO_SMUIO_7 = 7 -BOARD_GPIO_SMUIO_8 = 8 -BOARD_GPIO_SMUIO_9 = 9 -BOARD_GPIO_SMUIO_10 = 10 -BOARD_GPIO_SMUIO_11 = 11 -BOARD_GPIO_SMUIO_12 = 12 -BOARD_GPIO_SMUIO_13 = 13 -BOARD_GPIO_SMUIO_14 = 14 -BOARD_GPIO_SMUIO_15 = 15 -BOARD_GPIO_SMUIO_16 = 16 -BOARD_GPIO_SMUIO_17 = 17 -BOARD_GPIO_SMUIO_18 = 18 -BOARD_GPIO_SMUIO_19 = 19 -BOARD_GPIO_SMUIO_20 = 20 -BOARD_GPIO_SMUIO_21 = 21 -BOARD_GPIO_SMUIO_22 = 22 -BOARD_GPIO_SMUIO_23 = 23 -BOARD_GPIO_SMUIO_24 = 24 -BOARD_GPIO_SMUIO_25 = 25 -BOARD_GPIO_SMUIO_26 = 26 -BOARD_GPIO_SMUIO_27 = 27 -BOARD_GPIO_SMUIO_28 = 28 -BOARD_GPIO_SMUIO_29 = 29 -BOARD_GPIO_SMUIO_30 = 30 -BOARD_GPIO_SMUIO_31 = 31 -MAX_BOARD_GPIO_SMUIO_NUM = 32 -BOARD_GPIO_DC_GEN_A = 33 -BOARD_GPIO_DC_GEN_B = 34 -BOARD_GPIO_DC_GEN_C = 35 -BOARD_GPIO_DC_GEN_D = 36 -BOARD_GPIO_DC_GEN_E = 37 -BOARD_GPIO_DC_GEN_F = 38 -BOARD_GPIO_DC_GEN_G = 39 -BOARD_GPIO_DC_GENLK_CLK = 40 -BOARD_GPIO_DC_GENLK_VSYNC = 41 -BOARD_GPIO_DC_SWAPLOCK_A = 42 -BOARD_GPIO_DC_SWAPLOCK_B = 43 -MAX_BOARD_DC_GPIO_NUM = 44 -BOARD_GPIO_LV_EN = 45 -c__EA_BOARD_GPIO_TYPE_e = ctypes.c_uint32 # enum -BOARD_GPIO_TYPE_e = c__EA_BOARD_GPIO_TYPE_e -BOARD_GPIO_TYPE_e__enumvalues = c__EA_BOARD_GPIO_TYPE_e__enumvalues -class struct_c__SA_BootValues_t(Structure): - pass - -struct_c__SA_BootValues_t._pack_ = 1 # source:False -struct_c__SA_BootValues_t._fields_ = [ - ('InitImuClk', ctypes.c_uint16), - ('InitSocclk', ctypes.c_uint16), - ('InitMpioclk', ctypes.c_uint16), - ('InitSmnclk', ctypes.c_uint16), - ('InitDispClk', ctypes.c_uint16), - ('InitDppClk', ctypes.c_uint16), - ('InitDprefclk', ctypes.c_uint16), - ('InitDcfclk', ctypes.c_uint16), - ('InitDtbclk', ctypes.c_uint16), - ('InitDbguSocClk', ctypes.c_uint16), - ('InitGfxclk_bypass', ctypes.c_uint16), - ('InitMp1clk', ctypes.c_uint16), - ('InitLclk', ctypes.c_uint16), - ('InitDbguBacoClk', ctypes.c_uint16), - ('InitBaco400clk', ctypes.c_uint16), - ('InitBaco1200clk_bypass', ctypes.c_uint16), - ('InitBaco700clk_bypass', ctypes.c_uint16), - ('InitBaco500clk', ctypes.c_uint16), - ('InitDclk0', ctypes.c_uint16), - ('InitVclk0', ctypes.c_uint16), - ('InitFclk', ctypes.c_uint16), - ('Padding1', ctypes.c_uint16), - ('InitUclkLevel', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('InitVcoFreqPll0', ctypes.c_uint32), - ('InitVcoFreqPll1', ctypes.c_uint32), - ('InitVcoFreqPll2', ctypes.c_uint32), - ('InitVcoFreqPll3', ctypes.c_uint32), - ('InitVcoFreqPll4', ctypes.c_uint32), - ('InitVcoFreqPll5', ctypes.c_uint32), - ('InitVcoFreqPll6', ctypes.c_uint32), - ('InitVcoFreqPll7', ctypes.c_uint32), - ('InitVcoFreqPll8', ctypes.c_uint32), - ('InitGfx', ctypes.c_uint16), - ('InitSoc', ctypes.c_uint16), - ('InitVddIoMem', ctypes.c_uint16), - ('InitVddCiMem', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 8), +class OverDriveTableExternal_t(Struct): pass +OverDriveTableExternal_t._fields_ = [ + ('OverDriveTable', OverDriveTable_t), ] - -BootValues_t = struct_c__SA_BootValues_t -class struct_c__SA_MsgLimits_t(Structure): - pass - -struct_c__SA_MsgLimits_t._pack_ = 1 # source:False -struct_c__SA_MsgLimits_t._fields_ = [ - ('Power', ctypes.c_uint16 * 2 * 4), - ('Tdc', ctypes.c_uint16 * 2), - ('Temperature', ctypes.c_uint16 * 12), - ('PwmLimitMin', ctypes.c_ubyte), - ('PwmLimitMax', ctypes.c_ubyte), - ('FanTargetTemperature', ctypes.c_ubyte), - ('Spare1', ctypes.c_ubyte * 1), - ('AcousticTargetRpmThresholdMin', ctypes.c_uint16), - ('AcousticTargetRpmThresholdMax', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMin', ctypes.c_uint16), - ('AcousticLimitRpmThresholdMax', ctypes.c_uint16), - ('PccLimitMin', ctypes.c_uint16), - ('PccLimitMax', ctypes.c_uint16), - ('FanStopTempMin', ctypes.c_uint16), - ('FanStopTempMax', ctypes.c_uint16), - ('FanStartTempMin', ctypes.c_uint16), - ('FanStartTempMax', ctypes.c_uint16), - ('PowerMinPpt0', ctypes.c_uint16 * 2), - ('Spare', ctypes.c_uint32 * 11), +class OverDriveLimits_t(Struct): pass +OverDriveLimits_t._fields_ = [ + ('FeatureCtrlMask', uint32_t), + ('VoltageOffsetPerZoneBoundary', (int16_t * 6)), + ('VddGfxVmax', uint16_t), + ('VddSocVmax', uint16_t), + ('GfxclkFoffset', int16_t), + ('Padding', uint16_t), + ('UclkFmin', uint16_t), + ('UclkFmax', uint16_t), + ('FclkFmin', uint16_t), + ('FclkFmax', uint16_t), + ('Ppt', int16_t), + ('Tdc', int16_t), + ('FanLinearPwmPoints', (uint8_t * 6)), + ('FanLinearTempPoints', (uint8_t * 6)), + ('FanMinimumPwm', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanTargetTemperature', uint16_t), + ('FanZeroRpmEnable', uint8_t), + ('MaxOpTemp', uint8_t), + ('Padding1', (uint8_t * 2)), + ('GfxVoltageFullCtrlMode', uint16_t), + ('SocVoltageFullCtrlMode', uint16_t), + ('GfxclkFullCtrlMode', uint16_t), + ('UclkFullCtrlMode', uint16_t), + ('FclkFullCtrlMode', uint16_t), + ('GfxEdc', int16_t), + ('GfxPccLimitControl', int16_t), + ('Padding2', int16_t), + ('Spare', (uint32_t * 5)), ] +BOARD_GPIO_TYPE_e = CEnum(ctypes.c_uint32) +BOARD_GPIO_SMUIO_0 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_0', 0) +BOARD_GPIO_SMUIO_1 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_1', 1) +BOARD_GPIO_SMUIO_2 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_2', 2) +BOARD_GPIO_SMUIO_3 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_3', 3) +BOARD_GPIO_SMUIO_4 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_4', 4) +BOARD_GPIO_SMUIO_5 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_5', 5) +BOARD_GPIO_SMUIO_6 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_6', 6) +BOARD_GPIO_SMUIO_7 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_7', 7) +BOARD_GPIO_SMUIO_8 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_8', 8) +BOARD_GPIO_SMUIO_9 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_9', 9) +BOARD_GPIO_SMUIO_10 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_10', 10) +BOARD_GPIO_SMUIO_11 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_11', 11) +BOARD_GPIO_SMUIO_12 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_12', 12) +BOARD_GPIO_SMUIO_13 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_13', 13) +BOARD_GPIO_SMUIO_14 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_14', 14) +BOARD_GPIO_SMUIO_15 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_15', 15) +BOARD_GPIO_SMUIO_16 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_16', 16) +BOARD_GPIO_SMUIO_17 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_17', 17) +BOARD_GPIO_SMUIO_18 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_18', 18) +BOARD_GPIO_SMUIO_19 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_19', 19) +BOARD_GPIO_SMUIO_20 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_20', 20) +BOARD_GPIO_SMUIO_21 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_21', 21) +BOARD_GPIO_SMUIO_22 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_22', 22) +BOARD_GPIO_SMUIO_23 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_23', 23) +BOARD_GPIO_SMUIO_24 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_24', 24) +BOARD_GPIO_SMUIO_25 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_25', 25) +BOARD_GPIO_SMUIO_26 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_26', 26) +BOARD_GPIO_SMUIO_27 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_27', 27) +BOARD_GPIO_SMUIO_28 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_28', 28) +BOARD_GPIO_SMUIO_29 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_29', 29) +BOARD_GPIO_SMUIO_30 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_30', 30) +BOARD_GPIO_SMUIO_31 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_31', 31) +MAX_BOARD_GPIO_SMUIO_NUM = BOARD_GPIO_TYPE_e.define('MAX_BOARD_GPIO_SMUIO_NUM', 32) +BOARD_GPIO_DC_GEN_A = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_A', 33) +BOARD_GPIO_DC_GEN_B = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_B', 34) +BOARD_GPIO_DC_GEN_C = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_C', 35) +BOARD_GPIO_DC_GEN_D = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_D', 36) +BOARD_GPIO_DC_GEN_E = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_E', 37) +BOARD_GPIO_DC_GEN_F = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_F', 38) +BOARD_GPIO_DC_GEN_G = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GEN_G', 39) +BOARD_GPIO_DC_GENLK_CLK = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GENLK_CLK', 40) +BOARD_GPIO_DC_GENLK_VSYNC = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GENLK_VSYNC', 41) +BOARD_GPIO_DC_SWAPLOCK_A = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_A', 42) +BOARD_GPIO_DC_SWAPLOCK_B = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_B', 43) +MAX_BOARD_DC_GPIO_NUM = BOARD_GPIO_TYPE_e.define('MAX_BOARD_DC_GPIO_NUM', 44) +BOARD_GPIO_LV_EN = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_LV_EN', 45) -MsgLimits_t = struct_c__SA_MsgLimits_t -class struct_c__SA_DriverReportedClocks_t(Structure): - pass - -struct_c__SA_DriverReportedClocks_t._pack_ = 1 # source:False -struct_c__SA_DriverReportedClocks_t._fields_ = [ - ('BaseClockAc', ctypes.c_uint16), - ('GameClockAc', ctypes.c_uint16), - ('BoostClockAc', ctypes.c_uint16), - ('BaseClockDc', ctypes.c_uint16), - ('GameClockDc', ctypes.c_uint16), - ('BoostClockDc', ctypes.c_uint16), - ('MaxReportedClock', ctypes.c_uint16), - ('Padding', ctypes.c_uint16), - ('Reserved', ctypes.c_uint32 * 3), +class BootValues_t(Struct): pass +BootValues_t._fields_ = [ + ('InitImuClk', uint16_t), + ('InitSocclk', uint16_t), + ('InitMpioclk', uint16_t), + ('InitSmnclk', uint16_t), + ('InitDispClk', uint16_t), + ('InitDppClk', uint16_t), + ('InitDprefclk', uint16_t), + ('InitDcfclk', uint16_t), + ('InitDtbclk', uint16_t), + ('InitDbguSocClk', uint16_t), + ('InitGfxclk_bypass', uint16_t), + ('InitMp1clk', uint16_t), + ('InitLclk', uint16_t), + ('InitDbguBacoClk', uint16_t), + ('InitBaco400clk', uint16_t), + ('InitBaco1200clk_bypass', uint16_t), + ('InitBaco700clk_bypass', uint16_t), + ('InitBaco500clk', uint16_t), + ('InitDclk0', uint16_t), + ('InitVclk0', uint16_t), + ('InitFclk', uint16_t), + ('Padding1', uint16_t), + ('InitUclkLevel', uint8_t), + ('Padding', (uint8_t * 3)), + ('InitVcoFreqPll0', uint32_t), + ('InitVcoFreqPll1', uint32_t), + ('InitVcoFreqPll2', uint32_t), + ('InitVcoFreqPll3', uint32_t), + ('InitVcoFreqPll4', uint32_t), + ('InitVcoFreqPll5', uint32_t), + ('InitVcoFreqPll6', uint32_t), + ('InitVcoFreqPll7', uint32_t), + ('InitVcoFreqPll8', uint32_t), + ('InitGfx', uint16_t), + ('InitSoc', uint16_t), + ('InitVddIoMem', uint16_t), + ('InitVddCiMem', uint16_t), + ('Spare', (uint32_t * 8)), ] - -DriverReportedClocks_t = struct_c__SA_DriverReportedClocks_t -class struct_c__SA_AvfsDcBtcParams_t(Structure): - pass - -struct_c__SA_AvfsDcBtcParams_t._pack_ = 1 # source:False -struct_c__SA_AvfsDcBtcParams_t._fields_ = [ - ('DcBtcEnabled', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 3), - ('DcTol', ctypes.c_uint16), - ('DcBtcGb', ctypes.c_uint16), - ('DcBtcMin', ctypes.c_uint16), - ('DcBtcMax', ctypes.c_uint16), - ('DcBtcGbScalar', LinearInt_t), +class MsgLimits_t(Struct): pass +MsgLimits_t._fields_ = [ + ('Power', ((uint16_t * 2) * 4)), + ('Tdc', (uint16_t * 2)), + ('Temperature', (uint16_t * 12)), + ('PwmLimitMin', uint8_t), + ('PwmLimitMax', uint8_t), + ('FanTargetTemperature', uint8_t), + ('Spare1', (uint8_t * 1)), + ('AcousticTargetRpmThresholdMin', uint16_t), + ('AcousticTargetRpmThresholdMax', uint16_t), + ('AcousticLimitRpmThresholdMin', uint16_t), + ('AcousticLimitRpmThresholdMax', uint16_t), + ('PccLimitMin', uint16_t), + ('PccLimitMax', uint16_t), + ('FanStopTempMin', uint16_t), + ('FanStopTempMax', uint16_t), + ('FanStartTempMin', uint16_t), + ('FanStartTempMax', uint16_t), + ('PowerMinPpt0', (uint16_t * 2)), + ('Spare', (uint32_t * 11)), ] - -AvfsDcBtcParams_t = struct_c__SA_AvfsDcBtcParams_t -class struct_c__SA_AvfsFuseOverride_t(Structure): - pass - -struct_c__SA_AvfsFuseOverride_t._pack_ = 1 # source:False -struct_c__SA_AvfsFuseOverride_t._fields_ = [ - ('AvfsTemp', ctypes.c_uint16 * 2), - ('VftFMin', ctypes.c_uint16), - ('VInversion', ctypes.c_uint16), - ('qVft', struct_c__SA_QuadraticInt_t * 2), - ('qAvfsGb', QuadraticInt_t), - ('qAvfsGb2', QuadraticInt_t), +class DriverReportedClocks_t(Struct): pass +DriverReportedClocks_t._fields_ = [ + ('BaseClockAc', uint16_t), + ('GameClockAc', uint16_t), + ('BoostClockAc', uint16_t), + ('BaseClockDc', uint16_t), + ('GameClockDc', uint16_t), + ('BoostClockDc', uint16_t), + ('MaxReportedClock', uint16_t), + ('Padding', uint16_t), + ('Reserved', (uint32_t * 3)), ] - -AvfsFuseOverride_t = struct_c__SA_AvfsFuseOverride_t -class struct_c__SA_PFE_Settings_t(Structure): - pass - -struct_c__SA_PFE_Settings_t._pack_ = 1 # source:False -struct_c__SA_PFE_Settings_t._fields_ = [ - ('Version', ctypes.c_ubyte), - ('Spare8', ctypes.c_ubyte * 3), - ('FeaturesToRun', ctypes.c_uint32 * 2), - ('FwDStateMask', ctypes.c_uint32), - ('DebugOverrides', ctypes.c_uint32), - ('Spare', ctypes.c_uint32 * 2), +class AvfsDcBtcParams_t(Struct): pass +AvfsDcBtcParams_t._fields_ = [ + ('DcBtcEnabled', uint8_t), + ('Padding', (uint8_t * 3)), + ('DcTol', uint16_t), + ('DcBtcGb', uint16_t), + ('DcBtcMin', uint16_t), + ('DcBtcMax', uint16_t), + ('DcBtcGbScalar', LinearInt_t), ] - -PFE_Settings_t = struct_c__SA_PFE_Settings_t -class struct_c__SA_SkuTable_t(Structure): - pass - -struct_c__SA_SkuTable_t._pack_ = 1 # source:False -struct_c__SA_SkuTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('TotalPowerConfig', ctypes.c_ubyte), - ('CustomerVariant', ctypes.c_ubyte), - ('MemoryTemperatureTypeMask', ctypes.c_ubyte), - ('SmartShiftVersion', ctypes.c_ubyte), - ('SocketPowerLimitSpare', ctypes.c_ubyte * 10), - ('EnableLegacyPptLimit', ctypes.c_ubyte), - ('UseInputTelemetry', ctypes.c_ubyte), - ('SmartShiftMinReportedPptinDcs', ctypes.c_ubyte), - ('PaddingPpt', ctypes.c_ubyte * 7), - ('HwCtfTempLimit', ctypes.c_uint16), - ('PaddingInfra', ctypes.c_uint16), - ('FitControllerFailureRateLimit', ctypes.c_uint32), - ('FitControllerGfxDutyCycle', ctypes.c_uint32), - ('FitControllerSocDutyCycle', ctypes.c_uint32), - ('FitControllerSocOffset', ctypes.c_uint32), - ('GfxApccPlusResidencyLimit', ctypes.c_uint32), - ('ThrottlerControlMask', ctypes.c_uint32), - ('UlvVoltageOffset', ctypes.c_uint16 * 2), - ('Padding', ctypes.c_ubyte * 2), - ('DeepUlvVoltageOffsetSoc', ctypes.c_uint16), - ('DefaultMaxVoltage', ctypes.c_uint16 * 2), - ('BoostMaxVoltage', ctypes.c_uint16 * 2), - ('VminTempHystersis', ctypes.c_int16 * 2), - ('VminTempThreshold', ctypes.c_int16 * 2), - ('Vmin_Hot_T0', ctypes.c_uint16 * 2), - ('Vmin_Cold_T0', ctypes.c_uint16 * 2), - ('Vmin_Hot_Eol', ctypes.c_uint16 * 2), - ('Vmin_Cold_Eol', ctypes.c_uint16 * 2), - ('Vmin_Aging_Offset', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Hot', ctypes.c_uint16 * 2), - ('Spare_Vmin_Plat_Offset_Cold', ctypes.c_uint16 * 2), - ('VcBtcFixedVminAgingOffset', ctypes.c_uint16 * 2), - ('VcBtcVmin2PsmDegrationGb', ctypes.c_uint16 * 2), - ('VcBtcPsmA', ctypes.c_uint32 * 2), - ('VcBtcPsmB', ctypes.c_uint32 * 2), - ('VcBtcVminA', ctypes.c_uint32 * 2), - ('VcBtcVminB', ctypes.c_uint32 * 2), - ('PerPartVminEnabled', ctypes.c_ubyte * 2), - ('VcBtcEnabled', ctypes.c_ubyte * 2), - ('SocketPowerLimitAcTau', ctypes.c_uint16 * 4), - ('SocketPowerLimitDcTau', ctypes.c_uint16 * 4), - ('Gfx_Vmin_droop', QuadraticInt_t), - ('Soc_Vmin_droop', QuadraticInt_t), - ('SpareVmin', ctypes.c_uint32 * 6), - ('DpmDescriptor', struct_c__SA_DpmDescriptor_t * 11), - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 6), - ('FreqTableShadowUclk', ctypes.c_uint16 * 6), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint32 * 11), - ('GfxclkAibFmax', ctypes.c_uint16), - ('GfxDpmPadding', ctypes.c_uint16), - ('GfxclkFgfxoffEntry', ctypes.c_uint16), - ('GfxclkFgfxoffExitImu', ctypes.c_uint16), - ('GfxclkFgfxoffExitRlc', ctypes.c_uint16), - ('GfxclkThrottleClock', ctypes.c_uint16), - ('EnableGfxPowerStagesGpio', ctypes.c_ubyte), - ('GfxIdlePadding', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivEn', ctypes.c_ubyte), - ('SmsRepairWRCKClkDivVal', ctypes.c_ubyte), - ('GfxOffEntryEarlyMGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayEn', ctypes.c_ubyte), - ('GfxOffEntryForceCGCGDelayVal', ctypes.c_ubyte), - ('GfxclkFreqGfxUlv', ctypes.c_uint16), - ('GfxIdlePadding2', ctypes.c_ubyte * 2), - ('GfxOffEntryHysteresis', ctypes.c_uint32), - ('GfxoffSpare', ctypes.c_uint32 * 15), - ('DfllMstrOscConfigA', ctypes.c_uint16), - ('DfllSlvOscConfigA', ctypes.c_uint16), - ('DfllBtcMasterScalerM', ctypes.c_uint32), - ('DfllBtcMasterScalerB', ctypes.c_int32), - ('DfllBtcSlaveScalerM', ctypes.c_uint32), - ('DfllBtcSlaveScalerB', ctypes.c_int32), - ('DfllPccAsWaitCtrl', ctypes.c_uint32), - ('DfllPccAsStepCtrl', ctypes.c_uint32), - ('GfxDfllSpare', ctypes.c_uint32 * 9), - ('DvoPsmDownThresholdVoltage', ctypes.c_uint32), - ('DvoPsmUpThresholdVoltage', ctypes.c_uint32), - ('DvoFmaxLowScaler', ctypes.c_uint32), - ('PaddingDcs', ctypes.c_uint32), - ('DcsMinGfxOffTime', ctypes.c_uint16), - ('DcsMaxGfxOffTime', ctypes.c_uint16), - ('DcsMinCreditAccum', ctypes.c_uint32), - ('DcsExitHysteresis', ctypes.c_uint16), - ('DcsTimeout', ctypes.c_uint16), - ('DcsPfGfxFopt', ctypes.c_uint32), - ('DcsPfUclkFopt', ctypes.c_uint32), - ('FoptEnabled', ctypes.c_ubyte), - ('DcsSpare2', ctypes.c_ubyte * 3), - ('DcsFoptM', ctypes.c_uint32), - ('DcsFoptB', ctypes.c_uint32), - ('DcsSpare', ctypes.c_uint32 * 9), - ('UseStrobeModeOptimizations', ctypes.c_ubyte), - ('PaddingMem', ctypes.c_ubyte * 3), - ('UclkDpmPstates', ctypes.c_ubyte * 6), - ('UclkDpmShadowPstates', ctypes.c_ubyte * 6), - ('FreqTableUclkDiv', ctypes.c_ubyte * 6), - ('FreqTableShadowUclkDiv', ctypes.c_ubyte * 6), - ('MemVmempVoltage', ctypes.c_uint16 * 6), - ('MemVddioVoltage', ctypes.c_uint16 * 6), - ('DalDcModeMaxUclkFreq', ctypes.c_uint16), - ('PaddingsMem', ctypes.c_ubyte * 2), - ('PaddingFclk', ctypes.c_uint32), - ('PcieGenSpeed', ctypes.c_ubyte * 3), - ('PcieLaneCount', ctypes.c_ubyte * 3), - ('LclkFreq', ctypes.c_uint16 * 3), - ('OverrideGfxAvfsFuses', ctypes.c_ubyte), - ('GfxAvfsPadding', ctypes.c_ubyte * 1), - ('DroopGBStDev', ctypes.c_uint16), - ('SocHwRtAvfsFuses', ctypes.c_uint32 * 32), - ('GfxL2HwRtAvfsFuses', ctypes.c_uint32 * 32), - ('PsmDidt_Vcross', ctypes.c_uint16 * 2), - ('PsmDidt_StaticDroop_A', ctypes.c_uint32 * 3), - ('PsmDidt_StaticDroop_B', ctypes.c_uint32 * 3), - ('PsmDidt_DynDroop_A', ctypes.c_uint32 * 3), - ('PsmDidt_DynDroop_B', ctypes.c_uint32 * 3), - ('spare_HwRtAvfsFuses', ctypes.c_uint32 * 19), - ('SocCommonRtAvfs', ctypes.c_uint32 * 13), - ('GfxCommonRtAvfs', ctypes.c_uint32 * 13), - ('SocFwRtAvfsFuses', ctypes.c_uint32 * 19), - ('GfxL2FwRtAvfsFuses', ctypes.c_uint32 * 19), - ('spare_FwRtAvfsFuses', ctypes.c_uint32 * 19), - ('Soc_Droop_PWL_F', ctypes.c_uint32 * 5), - ('Soc_Droop_PWL_a', ctypes.c_uint32 * 5), - ('Soc_Droop_PWL_b', ctypes.c_uint32 * 5), - ('Soc_Droop_PWL_c', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_F', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_a', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_b', ctypes.c_uint32 * 5), - ('Gfx_Droop_PWL_c', ctypes.c_uint32 * 5), - ('Gfx_Static_PWL_Offset', ctypes.c_uint32 * 5), - ('Soc_Static_PWL_Offset', ctypes.c_uint32 * 5), - ('dGbV_dT_vmin', ctypes.c_uint32), - ('dGbV_dT_vmax', ctypes.c_uint32), - ('PaddingV2F', ctypes.c_uint32 * 4), - ('DcBtcGfxParams', AvfsDcBtcParams_t), - ('SSCurve_GFX', QuadraticInt_t), - ('GfxAvfsSpare', ctypes.c_uint32 * 29), - ('OverrideSocAvfsFuses', ctypes.c_ubyte), - ('MinSocAvfsRevision', ctypes.c_ubyte), - ('SocAvfsPadding', ctypes.c_ubyte * 2), - ('SocAvfsFuseOverride', struct_c__SA_AvfsFuseOverride_t * 1), - ('dBtcGbSoc', struct_c__SA_DroopInt_t * 1), - ('qAgingGb', struct_c__SA_LinearInt_t * 1), - ('qStaticVoltageOffset', struct_c__SA_QuadraticInt_t * 1), - ('DcBtcSocParams', struct_c__SA_AvfsDcBtcParams_t * 1), - ('SSCurve_SOC', QuadraticInt_t), - ('SocAvfsSpare', ctypes.c_uint32 * 29), - ('BootValues', BootValues_t), - ('DriverReportedClocks', DriverReportedClocks_t), - ('MsgLimits', MsgLimits_t), - ('OverDriveLimitsBasicMin', OverDriveLimits_t), - ('OverDriveLimitsBasicMax', OverDriveLimits_t), - ('OverDriveLimitsAdvancedMin', OverDriveLimits_t), - ('OverDriveLimitsAdvancedMax', OverDriveLimits_t), - ('TotalBoardPowerSupport', ctypes.c_ubyte), - ('TotalBoardPowerPadding', ctypes.c_ubyte * 1), - ('TotalBoardPowerRoc', ctypes.c_uint16), - ('qFeffCoeffGameClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBaseClock', struct_c__SA_QuadraticInt_t * 2), - ('qFeffCoeffBoostClock', struct_c__SA_QuadraticInt_t * 2), - ('AptUclkGfxclkLookup', ctypes.c_int32 * 6 * 2), - ('AptUclkGfxclkLookupHyst', ctypes.c_uint32 * 6 * 2), - ('AptPadding', ctypes.c_uint32), - ('GfxXvminDidtDroopThresh', QuadraticInt_t), - ('GfxXvminDidtResetDDWait', ctypes.c_uint32), - ('GfxXvminDidtClkStopWait', ctypes.c_uint32), - ('GfxXvminDidtFcsStepCtrl', ctypes.c_uint32), - ('GfxXvminDidtFcsWaitCtrl', ctypes.c_uint32), - ('PsmModeEnabled', ctypes.c_uint32), - ('P2v_a', ctypes.c_uint32), - ('P2v_b', ctypes.c_uint32), - ('P2v_c', ctypes.c_uint32), - ('T2p_a', ctypes.c_uint32), - ('T2p_b', ctypes.c_uint32), - ('T2p_c', ctypes.c_uint32), - ('P2vTemp', ctypes.c_uint32), - ('PsmDidtStaticSettings', QuadraticInt_t), - ('PsmDidtDynamicSettings', QuadraticInt_t), - ('PsmDidtAvgDiv', ctypes.c_ubyte), - ('PsmDidtForceStall', ctypes.c_ubyte), - ('PsmDidtReleaseTimer', ctypes.c_uint16), - ('PsmDidtStallPattern', ctypes.c_uint32), - ('CacEdcCacLeakageC0', ctypes.c_uint32), - ('CacEdcCacLeakageC1', ctypes.c_uint32), - ('CacEdcCacLeakageC2', ctypes.c_uint32), - ('CacEdcCacLeakageC3', ctypes.c_uint32), - ('CacEdcCacLeakageC4', ctypes.c_uint32), - ('CacEdcCacLeakageC5', ctypes.c_uint32), - ('CacEdcGfxClkScalar', ctypes.c_uint32), - ('CacEdcGfxClkIntercept', ctypes.c_uint32), - ('CacEdcCac_m', ctypes.c_uint32), - ('CacEdcCac_b', ctypes.c_uint32), - ('CacEdcCurrLimitGuardband', ctypes.c_uint32), - ('CacEdcDynToTotalCacRatio', ctypes.c_uint32), - ('XVmin_Gfx_EdcThreshScalar', ctypes.c_uint32), - ('XVmin_Gfx_EdcEnableFreq', ctypes.c_uint32), - ('XVmin_Gfx_EdcPccAsStepCtrl', ctypes.c_uint32), - ('XVmin_Gfx_EdcPccAsWaitCtrl', ctypes.c_uint32), - ('XVmin_Gfx_EdcThreshold', ctypes.c_uint16), - ('XVmin_Gfx_EdcFiltHysWaitCtrl', ctypes.c_uint16), - ('XVmin_Soc_EdcThreshScalar', ctypes.c_uint32), - ('XVmin_Soc_EdcEnableFreq', ctypes.c_uint32), - ('XVmin_Soc_EdcThreshold', ctypes.c_uint32), - ('XVmin_Soc_EdcStepUpTime', ctypes.c_uint16), - ('XVmin_Soc_EdcStepDownTime', ctypes.c_uint16), - ('XVmin_Soc_EdcInitPccStep', ctypes.c_ubyte), - ('PaddingSocEdc', ctypes.c_ubyte * 3), - ('GfxXvminFuseOverride', ctypes.c_ubyte), - ('SocXvminFuseOverride', ctypes.c_ubyte), - ('PaddingXvminFuseOverride', ctypes.c_ubyte * 2), - ('GfxXvminFddTempLow', ctypes.c_ubyte), - ('GfxXvminFddTempHigh', ctypes.c_ubyte), - ('SocXvminFddTempLow', ctypes.c_ubyte), - ('SocXvminFddTempHigh', ctypes.c_ubyte), - ('GfxXvminFddVolt0', ctypes.c_uint16), - ('GfxXvminFddVolt1', ctypes.c_uint16), - ('GfxXvminFddVolt2', ctypes.c_uint16), - ('SocXvminFddVolt0', ctypes.c_uint16), - ('SocXvminFddVolt1', ctypes.c_uint16), - ('SocXvminFddVolt2', ctypes.c_uint16), - ('GfxXvminDsFddDsm', ctypes.c_uint16 * 6), - ('GfxXvminEdcFddDsm', ctypes.c_uint16 * 6), - ('SocXvminEdcFddDsm', ctypes.c_uint16 * 6), - ('Spare', ctypes.c_uint32), - ('MmHubPadding', ctypes.c_uint32 * 8), +class AvfsFuseOverride_t(Struct): pass +AvfsFuseOverride_t._fields_ = [ + ('AvfsTemp', (uint16_t * 2)), + ('VftFMin', uint16_t), + ('VInversion', uint16_t), + ('qVft', (QuadraticInt_t * 2)), + ('qAvfsGb', QuadraticInt_t), + ('qAvfsGb2', QuadraticInt_t), ] - -SkuTable_t = struct_c__SA_SkuTable_t -class struct_c__SA_Svi3RegulatorSettings_t(Structure): - pass - -struct_c__SA_Svi3RegulatorSettings_t._pack_ = 1 # source:False -struct_c__SA_Svi3RegulatorSettings_t._fields_ = [ - ('SlewRateConditions', ctypes.c_ubyte), - ('LoadLineAdjust', ctypes.c_ubyte), - ('VoutOffset', ctypes.c_ubyte), - ('VidMax', ctypes.c_ubyte), - ('VidMin', ctypes.c_ubyte), - ('TenBitTelEn', ctypes.c_ubyte), - ('SixteenBitTelEn', ctypes.c_ubyte), - ('OcpThresh', ctypes.c_ubyte), - ('OcpWarnThresh', ctypes.c_ubyte), - ('OcpSettings', ctypes.c_ubyte), - ('VrhotThresh', ctypes.c_ubyte), - ('OtpThresh', ctypes.c_ubyte), - ('UvpOvpDeltaRef', ctypes.c_ubyte), - ('PhaseShed', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 10), - ('SettingOverrideMask', ctypes.c_uint32), +class PFE_Settings_t(Struct): pass +PFE_Settings_t._fields_ = [ + ('Version', uint8_t), + ('Spare8', (uint8_t * 3)), + ('FeaturesToRun', (uint32_t * 2)), + ('FwDStateMask', uint32_t), + ('DebugOverrides', uint32_t), + ('Spare', (uint32_t * 2)), ] - -Svi3RegulatorSettings_t = struct_c__SA_Svi3RegulatorSettings_t -class struct_c__SA_BoardTable_t(Structure): - pass - -struct_c__SA_BoardTable_t._pack_ = 1 # source:False -struct_c__SA_BoardTable_t._fields_ = [ - ('Version', ctypes.c_uint32), - ('I2cControllers', struct_c__SA_I2cControllerConfig_t * 8), - ('SlaveAddrMapping', ctypes.c_ubyte * 4), - ('VrPsiSupport', ctypes.c_ubyte * 4), - ('Svi3SvcSpeed', ctypes.c_uint32), - ('EnablePsi6', ctypes.c_ubyte * 4), - ('Svi3RegSettings', struct_c__SA_Svi3RegulatorSettings_t * 4), - ('LedOffGpio', ctypes.c_ubyte), - ('FanOffGpio', ctypes.c_ubyte), - ('GfxVrPowerStageOffGpio', ctypes.c_ubyte), - ('AcDcGpio', ctypes.c_ubyte), - ('AcDcPolarity', ctypes.c_ubyte), - ('VR0HotGpio', ctypes.c_ubyte), - ('VR0HotPolarity', ctypes.c_ubyte), - ('GthrGpio', ctypes.c_ubyte), - ('GthrPolarity', ctypes.c_ubyte), - ('LedPin0', ctypes.c_ubyte), - ('LedPin1', ctypes.c_ubyte), - ('LedPin2', ctypes.c_ubyte), - ('LedEnableMask', ctypes.c_ubyte), - ('LedPcie', ctypes.c_ubyte), - ('LedError', ctypes.c_ubyte), - ('PaddingLed', ctypes.c_ubyte), - ('UclkTrainingModeSpreadPercent', ctypes.c_ubyte), - ('UclkSpreadPadding', ctypes.c_ubyte), - ('UclkSpreadFreq', ctypes.c_uint16), - ('UclkSpreadPercent', ctypes.c_ubyte * 16), - ('GfxclkSpreadEnable', ctypes.c_ubyte), - ('FclkSpreadPercent', ctypes.c_ubyte), - ('FclkSpreadFreq', ctypes.c_uint16), - ('DramWidth', ctypes.c_ubyte), - ('PaddingMem1', ctypes.c_ubyte * 7), - ('HsrEnabled', ctypes.c_ubyte), - ('VddqOffEnabled', ctypes.c_ubyte), - ('PaddingUmcFlags', ctypes.c_ubyte * 2), - ('Paddign1', ctypes.c_uint32), - ('BacoEntryDelay', ctypes.c_uint32), - ('FuseWritePowerMuxPresent', ctypes.c_ubyte), - ('FuseWritePadding', ctypes.c_ubyte * 3), - ('LoadlineGfx', ctypes.c_uint32), - ('LoadlineSoc', ctypes.c_uint32), - ('GfxEdcLimit', ctypes.c_uint32), - ('SocEdcLimit', ctypes.c_uint32), - ('RestBoardPower', ctypes.c_uint32), - ('ConnectorsImpedance', ctypes.c_uint32), - ('EpcsSens0', ctypes.c_ubyte), - ('EpcsSens1', ctypes.c_ubyte), - ('PaddingEpcs', ctypes.c_ubyte * 2), - ('BoardSpare', ctypes.c_uint32 * 52), - ('MmHubPadding', ctypes.c_uint32 * 8), +class SkuTable_t(Struct): pass +int32_t = ctypes.c_int32 +SkuTable_t._fields_ = [ + ('Version', uint32_t), + ('TotalPowerConfig', uint8_t), + ('CustomerVariant', uint8_t), + ('MemoryTemperatureTypeMask', uint8_t), + ('SmartShiftVersion', uint8_t), + ('SocketPowerLimitSpare', (uint8_t * 10)), + ('EnableLegacyPptLimit', uint8_t), + ('UseInputTelemetry', uint8_t), + ('SmartShiftMinReportedPptinDcs', uint8_t), + ('PaddingPpt', (uint8_t * 7)), + ('HwCtfTempLimit', uint16_t), + ('PaddingInfra', uint16_t), + ('FitControllerFailureRateLimit', uint32_t), + ('FitControllerGfxDutyCycle', uint32_t), + ('FitControllerSocDutyCycle', uint32_t), + ('FitControllerSocOffset', uint32_t), + ('GfxApccPlusResidencyLimit', uint32_t), + ('ThrottlerControlMask', uint32_t), + ('UlvVoltageOffset', (uint16_t * 2)), + ('Padding', (uint8_t * 2)), + ('DeepUlvVoltageOffsetSoc', uint16_t), + ('DefaultMaxVoltage', (uint16_t * 2)), + ('BoostMaxVoltage', (uint16_t * 2)), + ('VminTempHystersis', (int16_t * 2)), + ('VminTempThreshold', (int16_t * 2)), + ('Vmin_Hot_T0', (uint16_t * 2)), + ('Vmin_Cold_T0', (uint16_t * 2)), + ('Vmin_Hot_Eol', (uint16_t * 2)), + ('Vmin_Cold_Eol', (uint16_t * 2)), + ('Vmin_Aging_Offset', (uint16_t * 2)), + ('Spare_Vmin_Plat_Offset_Hot', (uint16_t * 2)), + ('Spare_Vmin_Plat_Offset_Cold', (uint16_t * 2)), + ('VcBtcFixedVminAgingOffset', (uint16_t * 2)), + ('VcBtcVmin2PsmDegrationGb', (uint16_t * 2)), + ('VcBtcPsmA', (uint32_t * 2)), + ('VcBtcPsmB', (uint32_t * 2)), + ('VcBtcVminA', (uint32_t * 2)), + ('VcBtcVminB', (uint32_t * 2)), + ('PerPartVminEnabled', (uint8_t * 2)), + ('VcBtcEnabled', (uint8_t * 2)), + ('SocketPowerLimitAcTau', (uint16_t * 4)), + ('SocketPowerLimitDcTau', (uint16_t * 4)), + ('Gfx_Vmin_droop', QuadraticInt_t), + ('Soc_Vmin_droop', QuadraticInt_t), + ('SpareVmin', (uint32_t * 6)), + ('DpmDescriptor', (DpmDescriptor_t * 11)), + ('FreqTableGfx', (uint16_t * 16)), + ('FreqTableVclk', (uint16_t * 8)), + ('FreqTableDclk', (uint16_t * 8)), + ('FreqTableSocclk', (uint16_t * 8)), + ('FreqTableUclk', (uint16_t * 6)), + ('FreqTableShadowUclk', (uint16_t * 6)), + ('FreqTableDispclk', (uint16_t * 8)), + ('FreqTableDppClk', (uint16_t * 8)), + ('FreqTableDprefclk', (uint16_t * 8)), + ('FreqTableDcfclk', (uint16_t * 8)), + ('FreqTableDtbclk', (uint16_t * 8)), + ('FreqTableFclk', (uint16_t * 8)), + ('DcModeMaxFreq', (uint32_t * 11)), + ('GfxclkAibFmax', uint16_t), + ('GfxDpmPadding', uint16_t), + ('GfxclkFgfxoffEntry', uint16_t), + ('GfxclkFgfxoffExitImu', uint16_t), + ('GfxclkFgfxoffExitRlc', uint16_t), + ('GfxclkThrottleClock', uint16_t), + ('EnableGfxPowerStagesGpio', uint8_t), + ('GfxIdlePadding', uint8_t), + ('SmsRepairWRCKClkDivEn', uint8_t), + ('SmsRepairWRCKClkDivVal', uint8_t), + ('GfxOffEntryEarlyMGCGEn', uint8_t), + ('GfxOffEntryForceCGCGEn', uint8_t), + ('GfxOffEntryForceCGCGDelayEn', uint8_t), + ('GfxOffEntryForceCGCGDelayVal', uint8_t), + ('GfxclkFreqGfxUlv', uint16_t), + ('GfxIdlePadding2', (uint8_t * 2)), + ('GfxOffEntryHysteresis', uint32_t), + ('GfxoffSpare', (uint32_t * 15)), + ('DfllMstrOscConfigA', uint16_t), + ('DfllSlvOscConfigA', uint16_t), + ('DfllBtcMasterScalerM', uint32_t), + ('DfllBtcMasterScalerB', int32_t), + ('DfllBtcSlaveScalerM', uint32_t), + ('DfllBtcSlaveScalerB', int32_t), + ('DfllPccAsWaitCtrl', uint32_t), + ('DfllPccAsStepCtrl', uint32_t), + ('GfxDfllSpare', (uint32_t * 9)), + ('DvoPsmDownThresholdVoltage', uint32_t), + ('DvoPsmUpThresholdVoltage', uint32_t), + ('DvoFmaxLowScaler', uint32_t), + ('PaddingDcs', uint32_t), + ('DcsMinGfxOffTime', uint16_t), + ('DcsMaxGfxOffTime', uint16_t), + ('DcsMinCreditAccum', uint32_t), + ('DcsExitHysteresis', uint16_t), + ('DcsTimeout', uint16_t), + ('DcsPfGfxFopt', uint32_t), + ('DcsPfUclkFopt', uint32_t), + ('FoptEnabled', uint8_t), + ('DcsSpare2', (uint8_t * 3)), + ('DcsFoptM', uint32_t), + ('DcsFoptB', uint32_t), + ('DcsSpare', (uint32_t * 9)), + ('UseStrobeModeOptimizations', uint8_t), + ('PaddingMem', (uint8_t * 3)), + ('UclkDpmPstates', (uint8_t * 6)), + ('UclkDpmShadowPstates', (uint8_t * 6)), + ('FreqTableUclkDiv', (uint8_t * 6)), + ('FreqTableShadowUclkDiv', (uint8_t * 6)), + ('MemVmempVoltage', (uint16_t * 6)), + ('MemVddioVoltage', (uint16_t * 6)), + ('DalDcModeMaxUclkFreq', uint16_t), + ('PaddingsMem', (uint8_t * 2)), + ('PaddingFclk', uint32_t), + ('PcieGenSpeed', (uint8_t * 3)), + ('PcieLaneCount', (uint8_t * 3)), + ('LclkFreq', (uint16_t * 3)), + ('OverrideGfxAvfsFuses', uint8_t), + ('GfxAvfsPadding', (uint8_t * 1)), + ('DroopGBStDev', uint16_t), + ('SocHwRtAvfsFuses', (uint32_t * 32)), + ('GfxL2HwRtAvfsFuses', (uint32_t * 32)), + ('PsmDidt_Vcross', (uint16_t * 2)), + ('PsmDidt_StaticDroop_A', (uint32_t * 3)), + ('PsmDidt_StaticDroop_B', (uint32_t * 3)), + ('PsmDidt_DynDroop_A', (uint32_t * 3)), + ('PsmDidt_DynDroop_B', (uint32_t * 3)), + ('spare_HwRtAvfsFuses', (uint32_t * 19)), + ('SocCommonRtAvfs', (uint32_t * 13)), + ('GfxCommonRtAvfs', (uint32_t * 13)), + ('SocFwRtAvfsFuses', (uint32_t * 19)), + ('GfxL2FwRtAvfsFuses', (uint32_t * 19)), + ('spare_FwRtAvfsFuses', (uint32_t * 19)), + ('Soc_Droop_PWL_F', (uint32_t * 5)), + ('Soc_Droop_PWL_a', (uint32_t * 5)), + ('Soc_Droop_PWL_b', (uint32_t * 5)), + ('Soc_Droop_PWL_c', (uint32_t * 5)), + ('Gfx_Droop_PWL_F', (uint32_t * 5)), + ('Gfx_Droop_PWL_a', (uint32_t * 5)), + ('Gfx_Droop_PWL_b', (uint32_t * 5)), + ('Gfx_Droop_PWL_c', (uint32_t * 5)), + ('Gfx_Static_PWL_Offset', (uint32_t * 5)), + ('Soc_Static_PWL_Offset', (uint32_t * 5)), + ('dGbV_dT_vmin', uint32_t), + ('dGbV_dT_vmax', uint32_t), + ('PaddingV2F', (uint32_t * 4)), + ('DcBtcGfxParams', AvfsDcBtcParams_t), + ('SSCurve_GFX', QuadraticInt_t), + ('GfxAvfsSpare', (uint32_t * 29)), + ('OverrideSocAvfsFuses', uint8_t), + ('MinSocAvfsRevision', uint8_t), + ('SocAvfsPadding', (uint8_t * 2)), + ('SocAvfsFuseOverride', (AvfsFuseOverride_t * 1)), + ('dBtcGbSoc', (DroopInt_t * 1)), + ('qAgingGb', (LinearInt_t * 1)), + ('qStaticVoltageOffset', (QuadraticInt_t * 1)), + ('DcBtcSocParams', (AvfsDcBtcParams_t * 1)), + ('SSCurve_SOC', QuadraticInt_t), + ('SocAvfsSpare', (uint32_t * 29)), + ('BootValues', BootValues_t), + ('DriverReportedClocks', DriverReportedClocks_t), + ('MsgLimits', MsgLimits_t), + ('OverDriveLimitsBasicMin', OverDriveLimits_t), + ('OverDriveLimitsBasicMax', OverDriveLimits_t), + ('OverDriveLimitsAdvancedMin', OverDriveLimits_t), + ('OverDriveLimitsAdvancedMax', OverDriveLimits_t), + ('TotalBoardPowerSupport', uint8_t), + ('TotalBoardPowerPadding', (uint8_t * 1)), + ('TotalBoardPowerRoc', uint16_t), + ('qFeffCoeffGameClock', (QuadraticInt_t * 2)), + ('qFeffCoeffBaseClock', (QuadraticInt_t * 2)), + ('qFeffCoeffBoostClock', (QuadraticInt_t * 2)), + ('AptUclkGfxclkLookup', ((int32_t * 6) * 2)), + ('AptUclkGfxclkLookupHyst', ((uint32_t * 6) * 2)), + ('AptPadding', uint32_t), + ('GfxXvminDidtDroopThresh', QuadraticInt_t), + ('GfxXvminDidtResetDDWait', uint32_t), + ('GfxXvminDidtClkStopWait', uint32_t), + ('GfxXvminDidtFcsStepCtrl', uint32_t), + ('GfxXvminDidtFcsWaitCtrl', uint32_t), + ('PsmModeEnabled', uint32_t), + ('P2v_a', uint32_t), + ('P2v_b', uint32_t), + ('P2v_c', uint32_t), + ('T2p_a', uint32_t), + ('T2p_b', uint32_t), + ('T2p_c', uint32_t), + ('P2vTemp', uint32_t), + ('PsmDidtStaticSettings', QuadraticInt_t), + ('PsmDidtDynamicSettings', QuadraticInt_t), + ('PsmDidtAvgDiv', uint8_t), + ('PsmDidtForceStall', uint8_t), + ('PsmDidtReleaseTimer', uint16_t), + ('PsmDidtStallPattern', uint32_t), + ('CacEdcCacLeakageC0', uint32_t), + ('CacEdcCacLeakageC1', uint32_t), + ('CacEdcCacLeakageC2', uint32_t), + ('CacEdcCacLeakageC3', uint32_t), + ('CacEdcCacLeakageC4', uint32_t), + ('CacEdcCacLeakageC5', uint32_t), + ('CacEdcGfxClkScalar', uint32_t), + ('CacEdcGfxClkIntercept', uint32_t), + ('CacEdcCac_m', uint32_t), + ('CacEdcCac_b', uint32_t), + ('CacEdcCurrLimitGuardband', uint32_t), + ('CacEdcDynToTotalCacRatio', uint32_t), + ('XVmin_Gfx_EdcThreshScalar', uint32_t), + ('XVmin_Gfx_EdcEnableFreq', uint32_t), + ('XVmin_Gfx_EdcPccAsStepCtrl', uint32_t), + ('XVmin_Gfx_EdcPccAsWaitCtrl', uint32_t), + ('XVmin_Gfx_EdcThreshold', uint16_t), + ('XVmin_Gfx_EdcFiltHysWaitCtrl', uint16_t), + ('XVmin_Soc_EdcThreshScalar', uint32_t), + ('XVmin_Soc_EdcEnableFreq', uint32_t), + ('XVmin_Soc_EdcThreshold', uint32_t), + ('XVmin_Soc_EdcStepUpTime', uint16_t), + ('XVmin_Soc_EdcStepDownTime', uint16_t), + ('XVmin_Soc_EdcInitPccStep', uint8_t), + ('PaddingSocEdc', (uint8_t * 3)), + ('GfxXvminFuseOverride', uint8_t), + ('SocXvminFuseOverride', uint8_t), + ('PaddingXvminFuseOverride', (uint8_t * 2)), + ('GfxXvminFddTempLow', uint8_t), + ('GfxXvminFddTempHigh', uint8_t), + ('SocXvminFddTempLow', uint8_t), + ('SocXvminFddTempHigh', uint8_t), + ('GfxXvminFddVolt0', uint16_t), + ('GfxXvminFddVolt1', uint16_t), + ('GfxXvminFddVolt2', uint16_t), + ('SocXvminFddVolt0', uint16_t), + ('SocXvminFddVolt1', uint16_t), + ('SocXvminFddVolt2', uint16_t), + ('GfxXvminDsFddDsm', (uint16_t * 6)), + ('GfxXvminEdcFddDsm', (uint16_t * 6)), + ('SocXvminEdcFddDsm', (uint16_t * 6)), + ('Spare', uint32_t), + ('MmHubPadding', (uint32_t * 8)), ] - -BoardTable_t = struct_c__SA_BoardTable_t -class struct_c__SA_CustomSkuTable_t(Structure): - pass - -struct_c__SA_CustomSkuTable_t._pack_ = 1 # source:False -struct_c__SA_CustomSkuTable_t._fields_ = [ - ('SocketPowerLimitAc', ctypes.c_uint16 * 4), - ('VrTdcLimit', ctypes.c_uint16 * 2), - ('TotalIdleBoardPowerM', ctypes.c_int16), - ('TotalIdleBoardPowerB', ctypes.c_int16), - ('TotalBoardPowerM', ctypes.c_int16), - ('TotalBoardPowerB', ctypes.c_int16), - ('TemperatureLimit', ctypes.c_uint16 * 12), - ('FanStopTemp', ctypes.c_uint16 * 12), - ('FanStartTemp', ctypes.c_uint16 * 12), - ('FanGain', ctypes.c_uint16 * 12), - ('FanPwmMin', ctypes.c_uint16), - ('AcousticTargetRpmThreshold', ctypes.c_uint16), - ('AcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanMaximumRpm', ctypes.c_uint16), - ('MGpuAcousticLimitRpmThreshold', ctypes.c_uint16), - ('FanTargetGfxclk', ctypes.c_uint16), - ('TempInputSelectMask', ctypes.c_uint32), - ('FanZeroRpmEnable', ctypes.c_ubyte), - ('FanTachEdgePerRev', ctypes.c_ubyte), - ('FanPadding', ctypes.c_uint16), - ('FanTargetTemperature', ctypes.c_uint16 * 12), - ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), - ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), - ('FuzzyFan_PwmSetDelta', ctypes.c_int16), - ('FanPadding2', ctypes.c_uint16), - ('FwCtfLimit', ctypes.c_uint16 * 12), - ('IntakeTempEnableRPM', ctypes.c_uint16), - ('IntakeTempOffsetTemp', ctypes.c_int16), - ('IntakeTempReleaseTemp', ctypes.c_uint16), - ('IntakeTempHighIntakeAcousticLimit', ctypes.c_uint16), - ('IntakeTempAcouticLimitReleaseRate', ctypes.c_uint16), - ('FanAbnormalTempLimitOffset', ctypes.c_int16), - ('FanStalledTriggerRpm', ctypes.c_uint16), - ('FanAbnormalTriggerRpmCoeff', ctypes.c_uint16), - ('FanSpare', ctypes.c_uint16 * 1), - ('FanIntakeSensorSupport', ctypes.c_ubyte), - ('FanIntakePadding', ctypes.c_ubyte), - ('FanSpare2', ctypes.c_uint32 * 12), - ('ODFeatureCtrlMask', ctypes.c_uint32), - ('TemperatureLimit_Hynix', ctypes.c_uint16), - ('TemperatureLimit_Micron', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Hynix', ctypes.c_uint16), - ('TemperatureFwCtfLimit_Micron', ctypes.c_uint16), - ('PlatformTdcLimit', ctypes.c_uint16 * 2), - ('SocketPowerLimitDc', ctypes.c_uint16 * 4), - ('SocketPowerLimitSmartShift2', ctypes.c_uint16), - ('CustomSkuSpare16b', ctypes.c_uint16), - ('CustomSkuSpare32b', ctypes.c_uint32 * 10), - ('MmHubPadding', ctypes.c_uint32 * 8), +class Svi3RegulatorSettings_t(Struct): pass +Svi3RegulatorSettings_t._fields_ = [ + ('SlewRateConditions', uint8_t), + ('LoadLineAdjust', uint8_t), + ('VoutOffset', uint8_t), + ('VidMax', uint8_t), + ('VidMin', uint8_t), + ('TenBitTelEn', uint8_t), + ('SixteenBitTelEn', uint8_t), + ('OcpThresh', uint8_t), + ('OcpWarnThresh', uint8_t), + ('OcpSettings', uint8_t), + ('VrhotThresh', uint8_t), + ('OtpThresh', uint8_t), + ('UvpOvpDeltaRef', uint8_t), + ('PhaseShed', uint8_t), + ('Padding', (uint8_t * 10)), + ('SettingOverrideMask', uint32_t), ] - -CustomSkuTable_t = struct_c__SA_CustomSkuTable_t -class struct_c__SA_PPTable_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('PFE_Settings', PFE_Settings_t), - ('SkuTable', SkuTable_t), - ('CustomSkuTable', CustomSkuTable_t), - ('BoardTable', BoardTable_t), - ] - -PPTable_t = struct_c__SA_PPTable_t -class struct_c__SA_DriverSmuConfig_t(Structure): - pass - -struct_c__SA_DriverSmuConfig_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfig_t._fields_ = [ - ('GfxclkAverageLpfTau', ctypes.c_uint16), - ('FclkAverageLpfTau', ctypes.c_uint16), - ('UclkAverageLpfTau', ctypes.c_uint16), - ('GfxActivityLpfTau', ctypes.c_uint16), - ('UclkActivityLpfTau', ctypes.c_uint16), - ('UclkMaxActivityLpfTau', ctypes.c_uint16), - ('SocketPowerLpfTau', ctypes.c_uint16), - ('VcnClkAverageLpfTau', ctypes.c_uint16), - ('VcnUsageAverageLpfTau', ctypes.c_uint16), - ('PcieActivityLpTau', ctypes.c_uint16), +class BoardTable_t(Struct): pass +BoardTable_t._fields_ = [ + ('Version', uint32_t), + ('I2cControllers', (I2cControllerConfig_t * 8)), + ('SlaveAddrMapping', (uint8_t * 4)), + ('VrPsiSupport', (uint8_t * 4)), + ('Svi3SvcSpeed', uint32_t), + ('EnablePsi6', (uint8_t * 4)), + ('Svi3RegSettings', (Svi3RegulatorSettings_t * 4)), + ('LedOffGpio', uint8_t), + ('FanOffGpio', uint8_t), + ('GfxVrPowerStageOffGpio', uint8_t), + ('AcDcGpio', uint8_t), + ('AcDcPolarity', uint8_t), + ('VR0HotGpio', uint8_t), + ('VR0HotPolarity', uint8_t), + ('GthrGpio', uint8_t), + ('GthrPolarity', uint8_t), + ('LedPin0', uint8_t), + ('LedPin1', uint8_t), + ('LedPin2', uint8_t), + ('LedEnableMask', uint8_t), + ('LedPcie', uint8_t), + ('LedError', uint8_t), + ('PaddingLed', uint8_t), + ('UclkTrainingModeSpreadPercent', uint8_t), + ('UclkSpreadPadding', uint8_t), + ('UclkSpreadFreq', uint16_t), + ('UclkSpreadPercent', (uint8_t * 16)), + ('GfxclkSpreadEnable', uint8_t), + ('FclkSpreadPercent', uint8_t), + ('FclkSpreadFreq', uint16_t), + ('DramWidth', uint8_t), + ('PaddingMem1', (uint8_t * 7)), + ('HsrEnabled', uint8_t), + ('VddqOffEnabled', uint8_t), + ('PaddingUmcFlags', (uint8_t * 2)), + ('Paddign1', uint32_t), + ('BacoEntryDelay', uint32_t), + ('FuseWritePowerMuxPresent', uint8_t), + ('FuseWritePadding', (uint8_t * 3)), + ('LoadlineGfx', uint32_t), + ('LoadlineSoc', uint32_t), + ('GfxEdcLimit', uint32_t), + ('SocEdcLimit', uint32_t), + ('RestBoardPower', uint32_t), + ('ConnectorsImpedance', uint32_t), + ('EpcsSens0', uint8_t), + ('EpcsSens1', uint8_t), + ('PaddingEpcs', (uint8_t * 2)), + ('BoardSpare', (uint32_t * 52)), + ('MmHubPadding', (uint32_t * 8)), ] - -DriverSmuConfig_t = struct_c__SA_DriverSmuConfig_t -class struct_c__SA_DriverSmuConfigExternal_t(Structure): - pass - -struct_c__SA_DriverSmuConfigExternal_t._pack_ = 1 # source:False -struct_c__SA_DriverSmuConfigExternal_t._fields_ = [ - ('DriverSmuConfig', DriverSmuConfig_t), - ('Spare', ctypes.c_uint32 * 8), - ('MmHubPadding', ctypes.c_uint32 * 8), +class CustomSkuTable_t(Struct): pass +CustomSkuTable_t._fields_ = [ + ('SocketPowerLimitAc', (uint16_t * 4)), + ('VrTdcLimit', (uint16_t * 2)), + ('TotalIdleBoardPowerM', int16_t), + ('TotalIdleBoardPowerB', int16_t), + ('TotalBoardPowerM', int16_t), + ('TotalBoardPowerB', int16_t), + ('TemperatureLimit', (uint16_t * 12)), + ('FanStopTemp', (uint16_t * 12)), + ('FanStartTemp', (uint16_t * 12)), + ('FanGain', (uint16_t * 12)), + ('FanPwmMin', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanMaximumRpm', uint16_t), + ('MGpuAcousticLimitRpmThreshold', uint16_t), + ('FanTargetGfxclk', uint16_t), + ('TempInputSelectMask', uint32_t), + ('FanZeroRpmEnable', uint8_t), + ('FanTachEdgePerRev', uint8_t), + ('FanPadding', uint16_t), + ('FanTargetTemperature', (uint16_t * 12)), + ('FuzzyFan_ErrorSetDelta', int16_t), + ('FuzzyFan_ErrorRateSetDelta', int16_t), + ('FuzzyFan_PwmSetDelta', int16_t), + ('FanPadding2', uint16_t), + ('FwCtfLimit', (uint16_t * 12)), + ('IntakeTempEnableRPM', uint16_t), + ('IntakeTempOffsetTemp', int16_t), + ('IntakeTempReleaseTemp', uint16_t), + ('IntakeTempHighIntakeAcousticLimit', uint16_t), + ('IntakeTempAcouticLimitReleaseRate', uint16_t), + ('FanAbnormalTempLimitOffset', int16_t), + ('FanStalledTriggerRpm', uint16_t), + ('FanAbnormalTriggerRpmCoeff', uint16_t), + ('FanSpare', (uint16_t * 1)), + ('FanIntakeSensorSupport', uint8_t), + ('FanIntakePadding', uint8_t), + ('FanSpare2', (uint32_t * 12)), + ('ODFeatureCtrlMask', uint32_t), + ('TemperatureLimit_Hynix', uint16_t), + ('TemperatureLimit_Micron', uint16_t), + ('TemperatureFwCtfLimit_Hynix', uint16_t), + ('TemperatureFwCtfLimit_Micron', uint16_t), + ('PlatformTdcLimit', (uint16_t * 2)), + ('SocketPowerLimitDc', (uint16_t * 4)), + ('SocketPowerLimitSmartShift2', uint16_t), + ('CustomSkuSpare16b', uint16_t), + ('CustomSkuSpare32b', (uint32_t * 10)), + ('MmHubPadding', (uint32_t * 8)), ] - -DriverSmuConfigExternal_t = struct_c__SA_DriverSmuConfigExternal_t -class struct_c__SA_DriverInfoTable_t(Structure): - pass - -struct_c__SA_DriverInfoTable_t._pack_ = 1 # source:False -struct_c__SA_DriverInfoTable_t._fields_ = [ - ('FreqTableGfx', ctypes.c_uint16 * 16), - ('FreqTableVclk', ctypes.c_uint16 * 8), - ('FreqTableDclk', ctypes.c_uint16 * 8), - ('FreqTableSocclk', ctypes.c_uint16 * 8), - ('FreqTableUclk', ctypes.c_uint16 * 6), - ('FreqTableDispclk', ctypes.c_uint16 * 8), - ('FreqTableDppClk', ctypes.c_uint16 * 8), - ('FreqTableDprefclk', ctypes.c_uint16 * 8), - ('FreqTableDcfclk', ctypes.c_uint16 * 8), - ('FreqTableDtbclk', ctypes.c_uint16 * 8), - ('FreqTableFclk', ctypes.c_uint16 * 8), - ('DcModeMaxFreq', ctypes.c_uint16 * 11), - ('Padding', ctypes.c_uint16), - ('Spare', ctypes.c_uint32 * 32), - ('MmHubPadding', ctypes.c_uint32 * 8), +class PPTable_t(Struct): pass +PPTable_t._fields_ = [ + ('PFE_Settings', PFE_Settings_t), + ('SkuTable', SkuTable_t), + ('CustomSkuTable', CustomSkuTable_t), + ('BoardTable', BoardTable_t), ] - -DriverInfoTable_t = struct_c__SA_DriverInfoTable_t -class struct_c__SA_SmuMetrics_t(Structure): - pass - -struct_c__SA_SmuMetrics_t._pack_ = 1 # source:False -struct_c__SA_SmuMetrics_t._fields_ = [ - ('CurrClock', ctypes.c_uint32 * 11), - ('AverageGfxclkFrequencyTarget', ctypes.c_uint16), - ('AverageGfxclkFrequencyPreDs', ctypes.c_uint16), - ('AverageGfxclkFrequencyPostDs', ctypes.c_uint16), - ('AverageFclkFrequencyPreDs', ctypes.c_uint16), - ('AverageFclkFrequencyPostDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPreDs', ctypes.c_uint16), - ('AverageMemclkFrequencyPostDs', ctypes.c_uint16), - ('AverageVclk0Frequency', ctypes.c_uint16), - ('AverageDclk0Frequency', ctypes.c_uint16), - ('AverageVclk1Frequency', ctypes.c_uint16), - ('AverageDclk1Frequency', ctypes.c_uint16), - ('AveragePCIeBusy', ctypes.c_uint16), - ('dGPU_W_MAX', ctypes.c_uint16), - ('padding', ctypes.c_uint16), - ('MovingAverageGfxclkFrequencyTarget', ctypes.c_uint16), - ('MovingAverageGfxclkFrequencyPreDs', ctypes.c_uint16), - ('MovingAverageGfxclkFrequencyPostDs', ctypes.c_uint16), - ('MovingAverageFclkFrequencyPreDs', ctypes.c_uint16), - ('MovingAverageFclkFrequencyPostDs', ctypes.c_uint16), - ('MovingAverageMemclkFrequencyPreDs', ctypes.c_uint16), - ('MovingAverageMemclkFrequencyPostDs', ctypes.c_uint16), - ('MovingAverageVclk0Frequency', ctypes.c_uint16), - ('MovingAverageDclk0Frequency', ctypes.c_uint16), - ('MovingAverageGfxActivity', ctypes.c_uint16), - ('MovingAverageUclkActivity', ctypes.c_uint16), - ('MovingAverageVcn0ActivityPercentage', ctypes.c_uint16), - ('MovingAveragePCIeBusy', ctypes.c_uint16), - ('MovingAverageUclkActivity_MAX', ctypes.c_uint16), - ('MovingAverageSocketPower', ctypes.c_uint16), - ('MovingAveragePadding', ctypes.c_uint16), - ('MetricsCounter', ctypes.c_uint32), - ('AvgVoltage', ctypes.c_uint16 * 4), - ('AvgCurrent', ctypes.c_uint16 * 4), - ('AverageGfxActivity', ctypes.c_uint16), - ('AverageUclkActivity', ctypes.c_uint16), - ('AverageVcn0ActivityPercentage', ctypes.c_uint16), - ('Vcn1ActivityPercentage', ctypes.c_uint16), - ('EnergyAccumulator', ctypes.c_uint32), - ('AverageSocketPower', ctypes.c_uint16), - ('AverageTotalBoardPower', ctypes.c_uint16), - ('AvgTemperature', ctypes.c_uint16 * 12), - ('AvgTemperatureFanIntake', ctypes.c_uint16), - ('PcieRate', ctypes.c_ubyte), - ('PcieWidth', ctypes.c_ubyte), - ('AvgFanPwm', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 1), - ('AvgFanRpm', ctypes.c_uint16), - ('ThrottlingPercentage', ctypes.c_ubyte * 21), - ('VmaxThrottlingPercentage', ctypes.c_ubyte), - ('padding1', ctypes.c_ubyte * 2), - ('D3HotEntryCountPerMode', ctypes.c_uint32 * 4), - ('D3HotExitCountPerMode', ctypes.c_uint32 * 4), - ('ArmMsgReceivedCountPerMode', ctypes.c_uint32 * 4), - ('ApuSTAPMSmartShiftLimit', ctypes.c_uint16), - ('ApuSTAPMLimit', ctypes.c_uint16), - ('AvgApuSocketPower', ctypes.c_uint16), - ('AverageUclkActivity_MAX', ctypes.c_uint16), - ('PublicSerialNumberLower', ctypes.c_uint32), - ('PublicSerialNumberUpper', ctypes.c_uint32), +class DriverSmuConfig_t(Struct): pass +DriverSmuConfig_t._fields_ = [ + ('GfxclkAverageLpfTau', uint16_t), + ('FclkAverageLpfTau', uint16_t), + ('UclkAverageLpfTau', uint16_t), + ('GfxActivityLpfTau', uint16_t), + ('UclkActivityLpfTau', uint16_t), + ('UclkMaxActivityLpfTau', uint16_t), + ('SocketPowerLpfTau', uint16_t), + ('VcnClkAverageLpfTau', uint16_t), + ('VcnUsageAverageLpfTau', uint16_t), + ('PcieActivityLpTau', uint16_t), ] - -SmuMetrics_t = struct_c__SA_SmuMetrics_t -class struct_c__SA_SmuMetricsExternal_t(Structure): - pass - -struct_c__SA_SmuMetricsExternal_t._pack_ = 1 # source:False -struct_c__SA_SmuMetricsExternal_t._fields_ = [ - ('SmuMetrics', SmuMetrics_t), - ('Spare', ctypes.c_uint32 * 30), - ('MmHubPadding', ctypes.c_uint32 * 8), +class DriverSmuConfigExternal_t(Struct): pass +DriverSmuConfigExternal_t._fields_ = [ + ('DriverSmuConfig', DriverSmuConfig_t), + ('Spare', (uint32_t * 8)), + ('MmHubPadding', (uint32_t * 8)), ] - -SmuMetricsExternal_t = struct_c__SA_SmuMetricsExternal_t -class struct_c__SA_WatermarkRowGeneric_t(Structure): - pass - -struct_c__SA_WatermarkRowGeneric_t._pack_ = 1 # source:False -struct_c__SA_WatermarkRowGeneric_t._fields_ = [ - ('WmSetting', ctypes.c_ubyte), - ('Flags', ctypes.c_ubyte), - ('Padding', ctypes.c_ubyte * 2), +class DriverInfoTable_t(Struct): pass +DriverInfoTable_t._fields_ = [ + ('FreqTableGfx', (uint16_t * 16)), + ('FreqTableVclk', (uint16_t * 8)), + ('FreqTableDclk', (uint16_t * 8)), + ('FreqTableSocclk', (uint16_t * 8)), + ('FreqTableUclk', (uint16_t * 6)), + ('FreqTableDispclk', (uint16_t * 8)), + ('FreqTableDppClk', (uint16_t * 8)), + ('FreqTableDprefclk', (uint16_t * 8)), + ('FreqTableDcfclk', (uint16_t * 8)), + ('FreqTableDtbclk', (uint16_t * 8)), + ('FreqTableFclk', (uint16_t * 8)), + ('DcModeMaxFreq', (uint16_t * 11)), + ('Padding', uint16_t), + ('Spare', (uint32_t * 32)), + ('MmHubPadding', (uint32_t * 8)), ] - -WatermarkRowGeneric_t = struct_c__SA_WatermarkRowGeneric_t - -# values for enumeration 'c__EA_WATERMARKS_FLAGS_e' -c__EA_WATERMARKS_FLAGS_e__enumvalues = { - 0: 'WATERMARKS_CLOCK_RANGE', - 1: 'WATERMARKS_DUMMY_PSTATE', - 2: 'WATERMARKS_MALL', - 3: 'WATERMARKS_COUNT', -} -WATERMARKS_CLOCK_RANGE = 0 -WATERMARKS_DUMMY_PSTATE = 1 -WATERMARKS_MALL = 2 -WATERMARKS_COUNT = 3 -c__EA_WATERMARKS_FLAGS_e = ctypes.c_uint32 # enum -WATERMARKS_FLAGS_e = c__EA_WATERMARKS_FLAGS_e -WATERMARKS_FLAGS_e__enumvalues = c__EA_WATERMARKS_FLAGS_e__enumvalues -class struct_c__SA_Watermarks_t(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('WatermarkRow', struct_c__SA_WatermarkRowGeneric_t * 4), - ] - -Watermarks_t = struct_c__SA_Watermarks_t -class struct_c__SA_WatermarksExternal_t(Structure): - pass - -struct_c__SA_WatermarksExternal_t._pack_ = 1 # source:False -struct_c__SA_WatermarksExternal_t._fields_ = [ - ('Watermarks', Watermarks_t), - ('Spare', ctypes.c_uint32 * 16), - ('MmHubPadding', ctypes.c_uint32 * 8), +class SmuMetrics_t(Struct): pass +SmuMetrics_t._fields_ = [ + ('CurrClock', (uint32_t * 11)), + ('AverageGfxclkFrequencyTarget', uint16_t), + ('AverageGfxclkFrequencyPreDs', uint16_t), + ('AverageGfxclkFrequencyPostDs', uint16_t), + ('AverageFclkFrequencyPreDs', uint16_t), + ('AverageFclkFrequencyPostDs', uint16_t), + ('AverageMemclkFrequencyPreDs', uint16_t), + ('AverageMemclkFrequencyPostDs', uint16_t), + ('AverageVclk0Frequency', uint16_t), + ('AverageDclk0Frequency', uint16_t), + ('AverageVclk1Frequency', uint16_t), + ('AverageDclk1Frequency', uint16_t), + ('AveragePCIeBusy', uint16_t), + ('dGPU_W_MAX', uint16_t), + ('padding', uint16_t), + ('MovingAverageGfxclkFrequencyTarget', uint16_t), + ('MovingAverageGfxclkFrequencyPreDs', uint16_t), + ('MovingAverageGfxclkFrequencyPostDs', uint16_t), + ('MovingAverageFclkFrequencyPreDs', uint16_t), + ('MovingAverageFclkFrequencyPostDs', uint16_t), + ('MovingAverageMemclkFrequencyPreDs', uint16_t), + ('MovingAverageMemclkFrequencyPostDs', uint16_t), + ('MovingAverageVclk0Frequency', uint16_t), + ('MovingAverageDclk0Frequency', uint16_t), + ('MovingAverageGfxActivity', uint16_t), + ('MovingAverageUclkActivity', uint16_t), + ('MovingAverageVcn0ActivityPercentage', uint16_t), + ('MovingAveragePCIeBusy', uint16_t), + ('MovingAverageUclkActivity_MAX', uint16_t), + ('MovingAverageSocketPower', uint16_t), + ('MovingAveragePadding', uint16_t), + ('MetricsCounter', uint32_t), + ('AvgVoltage', (uint16_t * 4)), + ('AvgCurrent', (uint16_t * 4)), + ('AverageGfxActivity', uint16_t), + ('AverageUclkActivity', uint16_t), + ('AverageVcn0ActivityPercentage', uint16_t), + ('Vcn1ActivityPercentage', uint16_t), + ('EnergyAccumulator', uint32_t), + ('AverageSocketPower', uint16_t), + ('AverageTotalBoardPower', uint16_t), + ('AvgTemperature', (uint16_t * 12)), + ('AvgTemperatureFanIntake', uint16_t), + ('PcieRate', uint8_t), + ('PcieWidth', uint8_t), + ('AvgFanPwm', uint8_t), + ('Padding', (uint8_t * 1)), + ('AvgFanRpm', uint16_t), + ('ThrottlingPercentage', (uint8_t * 21)), + ('VmaxThrottlingPercentage', uint8_t), + ('padding1', (uint8_t * 2)), + ('D3HotEntryCountPerMode', (uint32_t * 4)), + ('D3HotExitCountPerMode', (uint32_t * 4)), + ('ArmMsgReceivedCountPerMode', (uint32_t * 4)), + ('ApuSTAPMSmartShiftLimit', uint16_t), + ('ApuSTAPMLimit', uint16_t), + ('AvgApuSocketPower', uint16_t), + ('AverageUclkActivity_MAX', uint16_t), + ('PublicSerialNumberLower', uint32_t), + ('PublicSerialNumberUpper', uint32_t), ] - -WatermarksExternal_t = struct_c__SA_WatermarksExternal_t -class struct_c__SA_AvfsDebugTable_t(Structure): - pass - -struct_c__SA_AvfsDebugTable_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTable_t._fields_ = [ - ('avgPsmCount', ctypes.c_uint16 * 76), - ('minPsmCount', ctypes.c_uint16 * 76), - ('maxPsmCount', ctypes.c_uint16 * 76), - ('avgPsmVoltage', ctypes.c_float * 76), - ('minPsmVoltage', ctypes.c_float * 76), - ('maxPsmVoltage', ctypes.c_float * 76), +class SmuMetricsExternal_t(Struct): pass +SmuMetricsExternal_t._fields_ = [ + ('SmuMetrics', SmuMetrics_t), + ('Spare', (uint32_t * 30)), + ('MmHubPadding', (uint32_t * 8)), ] - -AvfsDebugTable_t = struct_c__SA_AvfsDebugTable_t -class struct_c__SA_AvfsDebugTableExternal_t(Structure): - pass - -struct_c__SA_AvfsDebugTableExternal_t._pack_ = 1 # source:False -struct_c__SA_AvfsDebugTableExternal_t._fields_ = [ - ('AvfsDebugTable', AvfsDebugTable_t), - ('MmHubPadding', ctypes.c_uint32 * 8), +class WatermarkRowGeneric_t(Struct): pass +WatermarkRowGeneric_t._fields_ = [ + ('WmSetting', uint8_t), + ('Flags', uint8_t), + ('Padding', (uint8_t * 2)), ] +WATERMARKS_FLAGS_e = CEnum(ctypes.c_uint32) +WATERMARKS_CLOCK_RANGE = WATERMARKS_FLAGS_e.define('WATERMARKS_CLOCK_RANGE', 0) +WATERMARKS_DUMMY_PSTATE = WATERMARKS_FLAGS_e.define('WATERMARKS_DUMMY_PSTATE', 1) +WATERMARKS_MALL = WATERMARKS_FLAGS_e.define('WATERMARKS_MALL', 2) +WATERMARKS_COUNT = WATERMARKS_FLAGS_e.define('WATERMARKS_COUNT', 3) -AvfsDebugTableExternal_t = struct_c__SA_AvfsDebugTableExternal_t -class struct_c__SA_DpmActivityMonitorCoeffInt_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffInt_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffInt_t._fields_ = [ - ('Gfx_ActiveHystLimit', ctypes.c_ubyte), - ('Gfx_IdleHystLimit', ctypes.c_ubyte), - ('Gfx_FPS', ctypes.c_ubyte), - ('Gfx_MinActiveFreqType', ctypes.c_ubyte), - ('Gfx_BoosterFreqType', ctypes.c_ubyte), - ('PaddingGfx', ctypes.c_ubyte), - ('Gfx_MinActiveFreq', ctypes.c_uint16), - ('Gfx_BoosterFreq', ctypes.c_uint16), - ('Gfx_PD_Data_time_constant', ctypes.c_uint16), - ('Gfx_PD_Data_limit_a', ctypes.c_uint32), - ('Gfx_PD_Data_limit_b', ctypes.c_uint32), - ('Gfx_PD_Data_limit_c', ctypes.c_uint32), - ('Gfx_PD_Data_error_coeff', ctypes.c_uint32), - ('Gfx_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Fclk_ActiveHystLimit', ctypes.c_ubyte), - ('Fclk_IdleHystLimit', ctypes.c_ubyte), - ('Fclk_FPS', ctypes.c_ubyte), - ('Fclk_MinActiveFreqType', ctypes.c_ubyte), - ('Fclk_BoosterFreqType', ctypes.c_ubyte), - ('PaddingFclk', ctypes.c_ubyte), - ('Fclk_MinActiveFreq', ctypes.c_uint16), - ('Fclk_BoosterFreq', ctypes.c_uint16), - ('Fclk_PD_Data_time_constant', ctypes.c_uint16), - ('Fclk_PD_Data_limit_a', ctypes.c_uint32), - ('Fclk_PD_Data_limit_b', ctypes.c_uint32), - ('Fclk_PD_Data_limit_c', ctypes.c_uint32), - ('Fclk_PD_Data_error_coeff', ctypes.c_uint32), - ('Fclk_PD_Data_error_rate_coeff', ctypes.c_uint32), - ('Mem_UpThreshold_Limit', ctypes.c_uint32 * 6), - ('Mem_UpHystLimit', ctypes.c_ubyte * 6), - ('Mem_DownHystLimit', ctypes.c_uint16 * 6), - ('Mem_Fps', ctypes.c_uint16), +class Watermarks_t(Struct): pass +Watermarks_t._fields_ = [ + ('WatermarkRow', (WatermarkRowGeneric_t * 4)), ] - -DpmActivityMonitorCoeffInt_t = struct_c__SA_DpmActivityMonitorCoeffInt_t -class struct_c__SA_DpmActivityMonitorCoeffIntExternal_t(Structure): - pass - -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._pack_ = 1 # source:False -struct_c__SA_DpmActivityMonitorCoeffIntExternal_t._fields_ = [ - ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), - ('MmHubPadding', ctypes.c_uint32 * 8), +class WatermarksExternal_t(Struct): pass +WatermarksExternal_t._fields_ = [ + ('Watermarks', Watermarks_t), + ('Spare', (uint32_t * 16)), + ('MmHubPadding', (uint32_t * 8)), ] - -DpmActivityMonitorCoeffIntExternal_t = struct_c__SA_DpmActivityMonitorCoeffIntExternal_t -__AMDGPU_SMU_H__ = True # macro -int32_t = True # macro -uint32_t = True # macro -int8_t = True # macro -uint8_t = True # macro -uint16_t = True # macro -int16_t = True # macro -uint64_t = True # macro -bool = True # macro -u32 = True # macro -SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 # macro -SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 # macro -SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 # macro -SMU_FW_NAME_LEN = 0x24 # macro -SMU_DPM_USER_PROFILE_RESTORE = (1<<0) # macro -SMU_CUSTOM_FAN_SPEED_RPM = (1<<1) # macro -SMU_CUSTOM_FAN_SPEED_PWM = (1<<2) # macro -SMU_THROTTLER_PPT0_BIT = 0 # macro -SMU_THROTTLER_PPT1_BIT = 1 # macro -SMU_THROTTLER_PPT2_BIT = 2 # macro -SMU_THROTTLER_PPT3_BIT = 3 # macro -SMU_THROTTLER_SPL_BIT = 4 # macro -SMU_THROTTLER_FPPT_BIT = 5 # macro -SMU_THROTTLER_SPPT_BIT = 6 # macro -SMU_THROTTLER_SPPT_APU_BIT = 7 # macro -SMU_THROTTLER_TDC_GFX_BIT = 16 # macro -SMU_THROTTLER_TDC_SOC_BIT = 17 # macro -SMU_THROTTLER_TDC_MEM_BIT = 18 # macro -SMU_THROTTLER_TDC_VDD_BIT = 19 # macro -SMU_THROTTLER_TDC_CVIP_BIT = 20 # macro -SMU_THROTTLER_EDC_CPU_BIT = 21 # macro -SMU_THROTTLER_EDC_GFX_BIT = 22 # macro -SMU_THROTTLER_APCC_BIT = 23 # macro -SMU_THROTTLER_TEMP_GPU_BIT = 32 # macro -SMU_THROTTLER_TEMP_CORE_BIT = 33 # macro -SMU_THROTTLER_TEMP_MEM_BIT = 34 # macro -SMU_THROTTLER_TEMP_EDGE_BIT = 35 # macro -SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 # macro -SMU_THROTTLER_TEMP_SOC_BIT = 37 # macro -SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 # macro -SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 # macro -SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 # macro -SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 # macro -SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 # macro -SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 # macro -SMU_THROTTLER_VRHOT0_BIT = 44 # macro -SMU_THROTTLER_VRHOT1_BIT = 45 # macro -SMU_THROTTLER_PROCHOT_CPU_BIT = 46 # macro -SMU_THROTTLER_PROCHOT_GFX_BIT = 47 # macro -SMU_THROTTLER_PPM_BIT = 56 # macro -SMU_THROTTLER_FIT_BIT = 57 # macro -# def SMU_TABLE_INIT(tables, table_id, s, a, d): # macro -# return {tables[table_id].size=s;tables[table_id].align=a;tables[table_id].domain=d;}(0) -class struct_smu_hw_power_state(Structure): - pass - -struct_smu_hw_power_state._pack_ = 1 # source:False +class AvfsDebugTable_t(Struct): pass +AvfsDebugTable_t._fields_ = [ + ('avgPsmCount', (uint16_t * 76)), + ('minPsmCount', (uint16_t * 76)), + ('maxPsmCount', (uint16_t * 76)), + ('avgPsmVoltage', (ctypes.c_float * 76)), + ('minPsmVoltage', (ctypes.c_float * 76)), + ('maxPsmVoltage', (ctypes.c_float * 76)), +] +class AvfsDebugTableExternal_t(Struct): pass +AvfsDebugTableExternal_t._fields_ = [ + ('AvfsDebugTable', AvfsDebugTable_t), + ('MmHubPadding', (uint32_t * 8)), +] +class DpmActivityMonitorCoeffInt_t(Struct): pass +DpmActivityMonitorCoeffInt_t._fields_ = [ + ('Gfx_ActiveHystLimit', uint8_t), + ('Gfx_IdleHystLimit', uint8_t), + ('Gfx_FPS', uint8_t), + ('Gfx_MinActiveFreqType', uint8_t), + ('Gfx_BoosterFreqType', uint8_t), + ('PaddingGfx', uint8_t), + ('Gfx_MinActiveFreq', uint16_t), + ('Gfx_BoosterFreq', uint16_t), + ('Gfx_PD_Data_time_constant', uint16_t), + ('Gfx_PD_Data_limit_a', uint32_t), + ('Gfx_PD_Data_limit_b', uint32_t), + ('Gfx_PD_Data_limit_c', uint32_t), + ('Gfx_PD_Data_error_coeff', uint32_t), + ('Gfx_PD_Data_error_rate_coeff', uint32_t), + ('Fclk_ActiveHystLimit', uint8_t), + ('Fclk_IdleHystLimit', uint8_t), + ('Fclk_FPS', uint8_t), + ('Fclk_MinActiveFreqType', uint8_t), + ('Fclk_BoosterFreqType', uint8_t), + ('PaddingFclk', uint8_t), + ('Fclk_MinActiveFreq', uint16_t), + ('Fclk_BoosterFreq', uint16_t), + ('Fclk_PD_Data_time_constant', uint16_t), + ('Fclk_PD_Data_limit_a', uint32_t), + ('Fclk_PD_Data_limit_b', uint32_t), + ('Fclk_PD_Data_limit_c', uint32_t), + ('Fclk_PD_Data_error_coeff', uint32_t), + ('Fclk_PD_Data_error_rate_coeff', uint32_t), + ('Mem_UpThreshold_Limit', (uint32_t * 6)), + ('Mem_UpHystLimit', (uint8_t * 6)), + ('Mem_DownHystLimit', (uint16_t * 6)), + ('Mem_Fps', uint16_t), +] +class DpmActivityMonitorCoeffIntExternal_t(Struct): pass +DpmActivityMonitorCoeffIntExternal_t._fields_ = [ + ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), + ('MmHubPadding', (uint32_t * 8)), +] +class struct_smu_hw_power_state(Struct): pass struct_smu_hw_power_state._fields_ = [ - ('magic', ctypes.c_uint32), + ('magic', ctypes.c_uint32), ] +class struct_smu_power_state(Struct): pass +enum_smu_state_ui_label = CEnum(ctypes.c_uint32) +SMU_STATE_UI_LABEL_NONE = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_NONE', 0) +SMU_STATE_UI_LABEL_BATTERY = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_BATTERY', 1) +SMU_STATE_UI_TABEL_MIDDLE_LOW = enum_smu_state_ui_label.define('SMU_STATE_UI_TABEL_MIDDLE_LOW', 2) +SMU_STATE_UI_LABEL_BALLANCED = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_BALLANCED', 3) +SMU_STATE_UI_LABEL_MIDDLE_HIGHT = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 4) +SMU_STATE_UI_LABEL_PERFORMANCE = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_PERFORMANCE', 5) +SMU_STATE_UI_LABEL_BACO = enum_smu_state_ui_label.define('SMU_STATE_UI_LABEL_BACO', 6) -class struct_smu_power_state(Structure): - pass +enum_smu_state_classification_flag = CEnum(ctypes.c_uint32) +SMU_STATE_CLASSIFICATION_FLAG_BOOT = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_BOOT', 1) +SMU_STATE_CLASSIFICATION_FLAG_THERMAL = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_THERMAL', 2) +SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', 4) +SMU_STATE_CLASSIFICATION_FLAG_RESET = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_RESET', 8) +SMU_STATE_CLASSIFICATION_FLAG_FORCED = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_FORCED', 16) +SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', 32) +SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', 64) +SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', 128) +SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', 256) +SMU_STATE_CLASSIFICATION_FLAG_UVD = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD', 512) +SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', 1024) +SMU_STATE_CLASSIFICATION_FLAG_ACPI = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_ACPI', 2048) +SMU_STATE_CLASSIFICATION_FLAG_HD2 = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_HD2', 4096) +SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', 8192) +SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 16384) +SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', 32768) +SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', 65536) +SMU_STATE_CLASSIFICATION_FLAG_BACO = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_BACO', 131072) +SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', 262144) +SMU_STATE_CLASSIFICATION_FLAG_ULV = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_ULV', 524288) +SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = enum_smu_state_classification_flag.define('SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', 1048576) - -# values for enumeration 'smu_state_ui_label' -smu_state_ui_label__enumvalues = { - 0: 'SMU_STATE_UI_LABEL_NONE', - 1: 'SMU_STATE_UI_LABEL_BATTERY', - 2: 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 3: 'SMU_STATE_UI_LABEL_BALLANCED', - 4: 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', - 5: 'SMU_STATE_UI_LABEL_PERFORMANCE', - 6: 'SMU_STATE_UI_LABEL_BACO', -} -SMU_STATE_UI_LABEL_NONE = 0 -SMU_STATE_UI_LABEL_BATTERY = 1 -SMU_STATE_UI_TABEL_MIDDLE_LOW = 2 -SMU_STATE_UI_LABEL_BALLANCED = 3 -SMU_STATE_UI_LABEL_MIDDLE_HIGHT = 4 -SMU_STATE_UI_LABEL_PERFORMANCE = 5 -SMU_STATE_UI_LABEL_BACO = 6 -smu_state_ui_label = ctypes.c_uint32 # enum - -# values for enumeration 'smu_state_classification_flag' -smu_state_classification_flag__enumvalues = { - 1: 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 2: 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 4: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 8: 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 16: 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 32: 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 64: 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 128: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 256: 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 512: 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 1024: 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 2048: 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 4096: 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 8192: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 16384: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', - 32768: 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 65536: 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 131072: 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 262144: 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 524288: 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 1048576: 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', -} -SMU_STATE_CLASSIFICATION_FLAG_BOOT = 1 -SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 2 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 4 -SMU_STATE_CLASSIFICATION_FLAG_RESET = 8 -SMU_STATE_CLASSIFICATION_FLAG_FORCED = 16 -SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 32 -SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 64 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 128 -SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 256 -SMU_STATE_CLASSIFICATION_FLAG_UVD = 512 -SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 1024 -SMU_STATE_CLASSIFICATION_FLAG_ACPI = 2048 -SMU_STATE_CLASSIFICATION_FLAG_HD2 = 4096 -SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 8192 -SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 16384 -SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 32768 -SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 65536 -SMU_STATE_CLASSIFICATION_FLAG_BACO = 131072 -SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 262144 -SMU_STATE_CLASSIFICATION_FLAG_ULV = 524288 -SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 1048576 -smu_state_classification_flag = ctypes.c_uint32 # enum -class struct_smu_state_classification_block(Structure): - pass - -struct_smu_state_classification_block._pack_ = 1 # source:False +class struct_smu_state_classification_block(Struct): pass struct_smu_state_classification_block._fields_ = [ - ('ui_label', smu_state_ui_label), - ('flags', smu_state_classification_flag), - ('bios_index', ctypes.c_int32), - ('temporary_state', ctypes.c_bool), - ('to_be_deleted', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), + ('ui_label', enum_smu_state_ui_label), + ('flags', enum_smu_state_classification_flag), + ('bios_index', ctypes.c_int32), + ('temporary_state', ctypes.c_bool), + ('to_be_deleted', ctypes.c_bool), ] - -class struct_smu_state_pcie_block(Structure): - pass - -struct_smu_state_pcie_block._pack_ = 1 # source:False +class struct_smu_state_pcie_block(Struct): pass struct_smu_state_pcie_block._fields_ = [ - ('lanes', ctypes.c_uint32), + ('lanes', ctypes.c_uint32), ] +enum_smu_refreshrate_source = CEnum(ctypes.c_uint32) +SMU_REFRESHRATE_SOURCE_EDID = enum_smu_refreshrate_source.define('SMU_REFRESHRATE_SOURCE_EDID', 0) +SMU_REFRESHRATE_SOURCE_EXPLICIT = enum_smu_refreshrate_source.define('SMU_REFRESHRATE_SOURCE_EXPLICIT', 1) - -# values for enumeration 'smu_refreshrate_source' -smu_refreshrate_source__enumvalues = { - 0: 'SMU_REFRESHRATE_SOURCE_EDID', - 1: 'SMU_REFRESHRATE_SOURCE_EXPLICIT', -} -SMU_REFRESHRATE_SOURCE_EDID = 0 -SMU_REFRESHRATE_SOURCE_EXPLICIT = 1 -smu_refreshrate_source = ctypes.c_uint32 # enum -class struct_smu_state_display_block(Structure): - pass - -struct_smu_state_display_block._pack_ = 1 # source:False +class struct_smu_state_display_block(Struct): pass struct_smu_state_display_block._fields_ = [ - ('disable_frame_modulation', ctypes.c_bool), - ('limit_refreshrate', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 2), - ('refreshrate_source', smu_refreshrate_source), - ('explicit_refreshrate', ctypes.c_int32), - ('edid_refreshrate_index', ctypes.c_int32), - ('enable_vari_bright', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), + ('disable_frame_modulation', ctypes.c_bool), + ('limit_refreshrate', ctypes.c_bool), + ('refreshrate_source', enum_smu_refreshrate_source), + ('explicit_refreshrate', ctypes.c_int32), + ('edid_refreshrate_index', ctypes.c_int32), + ('enable_vari_bright', ctypes.c_bool), ] - -class struct_smu_state_memory_block(Structure): - pass - -struct_smu_state_memory_block._pack_ = 1 # source:False +class struct_smu_state_memory_block(Struct): pass struct_smu_state_memory_block._fields_ = [ - ('dll_off', ctypes.c_bool), - ('m3arb', ctypes.c_ubyte), - ('unused', ctypes.c_ubyte * 3), + ('dll_off', ctypes.c_bool), + ('m3arb', ctypes.c_ubyte), + ('unused', (ctypes.c_ubyte * 3)), ] - -class struct_smu_state_software_algorithm_block(Structure): - pass - -struct_smu_state_software_algorithm_block._pack_ = 1 # source:False +class struct_smu_state_software_algorithm_block(Struct): pass struct_smu_state_software_algorithm_block._fields_ = [ - ('disable_load_balancing', ctypes.c_bool), - ('enable_sleep_for_timestamps', ctypes.c_bool), + ('disable_load_balancing', ctypes.c_bool), + ('enable_sleep_for_timestamps', ctypes.c_bool), ] - -class struct_smu_temperature_range(Structure): - pass - -struct_smu_temperature_range._pack_ = 1 # source:False +class struct_smu_temperature_range(Struct): pass struct_smu_temperature_range._fields_ = [ - ('min', ctypes.c_int32), - ('max', ctypes.c_int32), - ('edge_emergency_max', ctypes.c_int32), - ('hotspot_min', ctypes.c_int32), - ('hotspot_crit_max', ctypes.c_int32), - ('hotspot_emergency_max', ctypes.c_int32), - ('mem_min', ctypes.c_int32), - ('mem_crit_max', ctypes.c_int32), - ('mem_emergency_max', ctypes.c_int32), - ('software_shutdown_temp', ctypes.c_int32), - ('software_shutdown_temp_offset', ctypes.c_int32), + ('min', ctypes.c_int32), + ('max', ctypes.c_int32), + ('edge_emergency_max', ctypes.c_int32), + ('hotspot_min', ctypes.c_int32), + ('hotspot_crit_max', ctypes.c_int32), + ('hotspot_emergency_max', ctypes.c_int32), + ('mem_min', ctypes.c_int32), + ('mem_crit_max', ctypes.c_int32), + ('mem_emergency_max', ctypes.c_int32), + ('software_shutdown_temp', ctypes.c_int32), + ('software_shutdown_temp_offset', ctypes.c_int32), ] - -class struct_smu_state_validation_block(Structure): - pass - -struct_smu_state_validation_block._pack_ = 1 # source:False +class struct_smu_state_validation_block(Struct): pass struct_smu_state_validation_block._fields_ = [ - ('single_display_only', ctypes.c_bool), - ('disallow_on_dc', ctypes.c_bool), - ('supported_power_levels', ctypes.c_ubyte), + ('single_display_only', ctypes.c_bool), + ('disallow_on_dc', ctypes.c_bool), + ('supported_power_levels', ctypes.c_ubyte), ] - -class struct_smu_uvd_clocks(Structure): - pass - -struct_smu_uvd_clocks._pack_ = 1 # source:False +class struct_smu_uvd_clocks(Struct): pass struct_smu_uvd_clocks._fields_ = [ - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), + ('vclk', ctypes.c_uint32), + ('dclk', ctypes.c_uint32), ] +enum_smu_power_src_type = CEnum(ctypes.c_uint32) +SMU_POWER_SOURCE_AC = enum_smu_power_src_type.define('SMU_POWER_SOURCE_AC', 0) +SMU_POWER_SOURCE_DC = enum_smu_power_src_type.define('SMU_POWER_SOURCE_DC', 1) +SMU_POWER_SOURCE_COUNT = enum_smu_power_src_type.define('SMU_POWER_SOURCE_COUNT', 2) +enum_smu_ppt_limit_type = CEnum(ctypes.c_uint32) +SMU_DEFAULT_PPT_LIMIT = enum_smu_ppt_limit_type.define('SMU_DEFAULT_PPT_LIMIT', 0) +SMU_FAST_PPT_LIMIT = enum_smu_ppt_limit_type.define('SMU_FAST_PPT_LIMIT', 1) -# values for enumeration 'smu_power_src_type' -smu_power_src_type__enumvalues = { - 0: 'SMU_POWER_SOURCE_AC', - 1: 'SMU_POWER_SOURCE_DC', - 2: 'SMU_POWER_SOURCE_COUNT', -} -SMU_POWER_SOURCE_AC = 0 -SMU_POWER_SOURCE_DC = 1 -SMU_POWER_SOURCE_COUNT = 2 -smu_power_src_type = ctypes.c_uint32 # enum +enum_smu_ppt_limit_level = CEnum(ctypes.c_int32) +SMU_PPT_LIMIT_MIN = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_MIN', -1) +SMU_PPT_LIMIT_CURRENT = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_CURRENT', 0) +SMU_PPT_LIMIT_DEFAULT = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_DEFAULT', 1) +SMU_PPT_LIMIT_MAX = enum_smu_ppt_limit_level.define('SMU_PPT_LIMIT_MAX', 2) -# values for enumeration 'smu_ppt_limit_type' -smu_ppt_limit_type__enumvalues = { - 0: 'SMU_DEFAULT_PPT_LIMIT', - 1: 'SMU_FAST_PPT_LIMIT', -} -SMU_DEFAULT_PPT_LIMIT = 0 -SMU_FAST_PPT_LIMIT = 1 -smu_ppt_limit_type = ctypes.c_uint32 # enum +enum_smu_memory_pool_size = CEnum(ctypes.c_uint32) +SMU_MEMORY_POOL_SIZE_ZERO = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_ZERO', 0) +SMU_MEMORY_POOL_SIZE_256_MB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_256_MB', 268435456) +SMU_MEMORY_POOL_SIZE_512_MB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_512_MB', 536870912) +SMU_MEMORY_POOL_SIZE_1_GB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_1_GB', 1073741824) +SMU_MEMORY_POOL_SIZE_2_GB = enum_smu_memory_pool_size.define('SMU_MEMORY_POOL_SIZE_2_GB', 2147483648) -# values for enumeration 'smu_ppt_limit_level' -smu_ppt_limit_level__enumvalues = { - -1: 'SMU_PPT_LIMIT_MIN', - 0: 'SMU_PPT_LIMIT_CURRENT', - 1: 'SMU_PPT_LIMIT_DEFAULT', - 2: 'SMU_PPT_LIMIT_MAX', -} -SMU_PPT_LIMIT_MIN = -1 -SMU_PPT_LIMIT_CURRENT = 0 -SMU_PPT_LIMIT_DEFAULT = 1 -SMU_PPT_LIMIT_MAX = 2 -smu_ppt_limit_level = ctypes.c_int32 # enum +enum_smu_clk_type = CEnum(ctypes.c_uint32) +SMU_GFXCLK = enum_smu_clk_type.define('SMU_GFXCLK', 0) +SMU_VCLK = enum_smu_clk_type.define('SMU_VCLK', 1) +SMU_DCLK = enum_smu_clk_type.define('SMU_DCLK', 2) +SMU_VCLK1 = enum_smu_clk_type.define('SMU_VCLK1', 3) +SMU_DCLK1 = enum_smu_clk_type.define('SMU_DCLK1', 4) +SMU_ECLK = enum_smu_clk_type.define('SMU_ECLK', 5) +SMU_SOCCLK = enum_smu_clk_type.define('SMU_SOCCLK', 6) +SMU_UCLK = enum_smu_clk_type.define('SMU_UCLK', 7) +SMU_DCEFCLK = enum_smu_clk_type.define('SMU_DCEFCLK', 8) +SMU_DISPCLK = enum_smu_clk_type.define('SMU_DISPCLK', 9) +SMU_PIXCLK = enum_smu_clk_type.define('SMU_PIXCLK', 10) +SMU_PHYCLK = enum_smu_clk_type.define('SMU_PHYCLK', 11) +SMU_FCLK = enum_smu_clk_type.define('SMU_FCLK', 12) +SMU_SCLK = enum_smu_clk_type.define('SMU_SCLK', 13) +SMU_MCLK = enum_smu_clk_type.define('SMU_MCLK', 14) +SMU_PCIE = enum_smu_clk_type.define('SMU_PCIE', 15) +SMU_LCLK = enum_smu_clk_type.define('SMU_LCLK', 16) +SMU_OD_CCLK = enum_smu_clk_type.define('SMU_OD_CCLK', 17) +SMU_OD_SCLK = enum_smu_clk_type.define('SMU_OD_SCLK', 18) +SMU_OD_MCLK = enum_smu_clk_type.define('SMU_OD_MCLK', 19) +SMU_OD_VDDC_CURVE = enum_smu_clk_type.define('SMU_OD_VDDC_CURVE', 20) +SMU_OD_RANGE = enum_smu_clk_type.define('SMU_OD_RANGE', 21) +SMU_OD_VDDGFX_OFFSET = enum_smu_clk_type.define('SMU_OD_VDDGFX_OFFSET', 22) +SMU_OD_FAN_CURVE = enum_smu_clk_type.define('SMU_OD_FAN_CURVE', 23) +SMU_OD_ACOUSTIC_LIMIT = enum_smu_clk_type.define('SMU_OD_ACOUSTIC_LIMIT', 24) +SMU_OD_ACOUSTIC_TARGET = enum_smu_clk_type.define('SMU_OD_ACOUSTIC_TARGET', 25) +SMU_OD_FAN_TARGET_TEMPERATURE = enum_smu_clk_type.define('SMU_OD_FAN_TARGET_TEMPERATURE', 26) +SMU_OD_FAN_MINIMUM_PWM = enum_smu_clk_type.define('SMU_OD_FAN_MINIMUM_PWM', 27) +SMU_CLK_COUNT = enum_smu_clk_type.define('SMU_CLK_COUNT', 28) -# values for enumeration 'smu_memory_pool_size' -smu_memory_pool_size__enumvalues = { - 0: 'SMU_MEMORY_POOL_SIZE_ZERO', - 268435456: 'SMU_MEMORY_POOL_SIZE_256_MB', - 536870912: 'SMU_MEMORY_POOL_SIZE_512_MB', - 1073741824: 'SMU_MEMORY_POOL_SIZE_1_GB', - 2147483648: 'SMU_MEMORY_POOL_SIZE_2_GB', -} -SMU_MEMORY_POOL_SIZE_ZERO = 0 -SMU_MEMORY_POOL_SIZE_256_MB = 268435456 -SMU_MEMORY_POOL_SIZE_512_MB = 536870912 -SMU_MEMORY_POOL_SIZE_1_GB = 1073741824 -SMU_MEMORY_POOL_SIZE_2_GB = 2147483648 -smu_memory_pool_size = ctypes.c_uint32 # enum - -# values for enumeration 'smu_clk_type' -smu_clk_type__enumvalues = { - 0: 'SMU_GFXCLK', - 1: 'SMU_VCLK', - 2: 'SMU_DCLK', - 3: 'SMU_VCLK1', - 4: 'SMU_DCLK1', - 5: 'SMU_ECLK', - 6: 'SMU_SOCCLK', - 7: 'SMU_UCLK', - 8: 'SMU_DCEFCLK', - 9: 'SMU_DISPCLK', - 10: 'SMU_PIXCLK', - 11: 'SMU_PHYCLK', - 12: 'SMU_FCLK', - 13: 'SMU_SCLK', - 14: 'SMU_MCLK', - 15: 'SMU_PCIE', - 16: 'SMU_LCLK', - 17: 'SMU_OD_CCLK', - 18: 'SMU_OD_SCLK', - 19: 'SMU_OD_MCLK', - 20: 'SMU_OD_VDDC_CURVE', - 21: 'SMU_OD_RANGE', - 22: 'SMU_OD_VDDGFX_OFFSET', - 23: 'SMU_OD_FAN_CURVE', - 24: 'SMU_OD_ACOUSTIC_LIMIT', - 25: 'SMU_OD_ACOUSTIC_TARGET', - 26: 'SMU_OD_FAN_TARGET_TEMPERATURE', - 27: 'SMU_OD_FAN_MINIMUM_PWM', - 28: 'SMU_CLK_COUNT', -} -SMU_GFXCLK = 0 -SMU_VCLK = 1 -SMU_DCLK = 2 -SMU_VCLK1 = 3 -SMU_DCLK1 = 4 -SMU_ECLK = 5 -SMU_SOCCLK = 6 -SMU_UCLK = 7 -SMU_DCEFCLK = 8 -SMU_DISPCLK = 9 -SMU_PIXCLK = 10 -SMU_PHYCLK = 11 -SMU_FCLK = 12 -SMU_SCLK = 13 -SMU_MCLK = 14 -SMU_PCIE = 15 -SMU_LCLK = 16 -SMU_OD_CCLK = 17 -SMU_OD_SCLK = 18 -SMU_OD_MCLK = 19 -SMU_OD_VDDC_CURVE = 20 -SMU_OD_RANGE = 21 -SMU_OD_VDDGFX_OFFSET = 22 -SMU_OD_FAN_CURVE = 23 -SMU_OD_ACOUSTIC_LIMIT = 24 -SMU_OD_ACOUSTIC_TARGET = 25 -SMU_OD_FAN_TARGET_TEMPERATURE = 26 -SMU_OD_FAN_MINIMUM_PWM = 27 -SMU_CLK_COUNT = 28 -smu_clk_type = ctypes.c_uint32 # enum -class struct_smu_user_dpm_profile(Structure): - pass - -struct_smu_user_dpm_profile._pack_ = 1 # source:False +class struct_smu_user_dpm_profile(Struct): pass struct_smu_user_dpm_profile._fields_ = [ - ('fan_mode', ctypes.c_uint32), - ('power_limit', ctypes.c_uint32), - ('fan_speed_pwm', ctypes.c_uint32), - ('fan_speed_rpm', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('user_od', ctypes.c_uint32), - ('clk_mask', ctypes.c_uint32 * 28), - ('clk_dependency', ctypes.c_uint32), + ('fan_mode', ctypes.c_uint32), + ('power_limit', ctypes.c_uint32), + ('fan_speed_pwm', ctypes.c_uint32), + ('fan_speed_rpm', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('user_od', ctypes.c_uint32), + ('clk_mask', (ctypes.c_uint32 * 28)), + ('clk_dependency', ctypes.c_uint32), ] - -class struct_smu_table(Structure): - pass - -class struct_amdgpu_bo(Structure): - pass - -struct_smu_table._pack_ = 1 # source:False +class struct_smu_table(Struct): pass +class struct_amdgpu_bo(Struct): pass struct_smu_table._fields_ = [ - ('size', ctypes.c_uint64), - ('align', ctypes.c_uint32), - ('domain', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('mc_address', ctypes.c_uint64), - ('cpu_addr', ctypes.POINTER(None)), - ('bo', ctypes.POINTER(struct_amdgpu_bo)), - ('version', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('size', ctypes.c_uint64), + ('align', ctypes.c_uint32), + ('domain', ctypes.c_ubyte), + ('mc_address', ctypes.c_uint64), + ('cpu_addr', ctypes.c_void_p), + ('bo', ctypes.POINTER(struct_amdgpu_bo)), + ('version', ctypes.c_uint32), ] +enum_smu_perf_level_designation = CEnum(ctypes.c_uint32) +PERF_LEVEL_ACTIVITY = enum_smu_perf_level_designation.define('PERF_LEVEL_ACTIVITY', 0) +PERF_LEVEL_POWER_CONTAINMENT = enum_smu_perf_level_designation.define('PERF_LEVEL_POWER_CONTAINMENT', 1) - -# values for enumeration 'smu_perf_level_designation' -smu_perf_level_designation__enumvalues = { - 0: 'PERF_LEVEL_ACTIVITY', - 1: 'PERF_LEVEL_POWER_CONTAINMENT', -} -PERF_LEVEL_ACTIVITY = 0 -PERF_LEVEL_POWER_CONTAINMENT = 1 -smu_perf_level_designation = ctypes.c_uint32 # enum -class struct_smu_performance_level(Structure): - pass - -struct_smu_performance_level._pack_ = 1 # source:False +class struct_smu_performance_level(Struct): pass struct_smu_performance_level._fields_ = [ - ('core_clock', ctypes.c_uint32), - ('memory_clock', ctypes.c_uint32), - ('vddc', ctypes.c_uint32), - ('vddci', ctypes.c_uint32), - ('non_local_mem_freq', ctypes.c_uint32), - ('non_local_mem_width', ctypes.c_uint32), + ('core_clock', ctypes.c_uint32), + ('memory_clock', ctypes.c_uint32), + ('vddc', ctypes.c_uint32), + ('vddci', ctypes.c_uint32), + ('non_local_mem_freq', ctypes.c_uint32), + ('non_local_mem_width', ctypes.c_uint32), ] - -class struct_smu_clock_info(Structure): - pass - -struct_smu_clock_info._pack_ = 1 # source:False +class struct_smu_clock_info(Struct): pass struct_smu_clock_info._fields_ = [ - ('min_mem_clk', ctypes.c_uint32), - ('max_mem_clk', ctypes.c_uint32), - ('min_eng_clk', ctypes.c_uint32), - ('max_eng_clk', ctypes.c_uint32), - ('min_bus_bandwidth', ctypes.c_uint32), - ('max_bus_bandwidth', ctypes.c_uint32), + ('min_mem_clk', ctypes.c_uint32), + ('max_mem_clk', ctypes.c_uint32), + ('min_eng_clk', ctypes.c_uint32), + ('max_eng_clk', ctypes.c_uint32), + ('min_bus_bandwidth', ctypes.c_uint32), + ('max_bus_bandwidth', ctypes.c_uint32), ] - -class struct_smu_bios_boot_up_values(Structure): - pass - -struct_smu_bios_boot_up_values._pack_ = 1 # source:False +class struct_smu_bios_boot_up_values(Struct): pass struct_smu_bios_boot_up_values._fields_ = [ - ('revision', ctypes.c_uint32), - ('gfxclk', ctypes.c_uint32), - ('uclk', ctypes.c_uint32), - ('socclk', ctypes.c_uint32), - ('dcefclk', ctypes.c_uint32), - ('eclk', ctypes.c_uint32), - ('vclk', ctypes.c_uint32), - ('dclk', ctypes.c_uint32), - ('vddc', ctypes.c_uint16), - ('vddci', ctypes.c_uint16), - ('mvddc', ctypes.c_uint16), - ('vdd_gfx', ctypes.c_uint16), - ('cooling_id', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pp_table_id', ctypes.c_uint32), - ('format_revision', ctypes.c_uint32), - ('content_revision', ctypes.c_uint32), - ('fclk', ctypes.c_uint32), - ('lclk', ctypes.c_uint32), - ('firmware_caps', ctypes.c_uint32), + ('revision', ctypes.c_uint32), + ('gfxclk', ctypes.c_uint32), + ('uclk', ctypes.c_uint32), + ('socclk', ctypes.c_uint32), + ('dcefclk', ctypes.c_uint32), + ('eclk', ctypes.c_uint32), + ('vclk', ctypes.c_uint32), + ('dclk', ctypes.c_uint32), + ('vddc', ctypes.c_uint16), + ('vddci', ctypes.c_uint16), + ('mvddc', ctypes.c_uint16), + ('vdd_gfx', ctypes.c_uint16), + ('cooling_id', ctypes.c_ubyte), + ('pp_table_id', ctypes.c_uint32), + ('format_revision', ctypes.c_uint32), + ('content_revision', ctypes.c_uint32), + ('fclk', ctypes.c_uint32), + ('lclk', ctypes.c_uint32), + ('firmware_caps', ctypes.c_uint32), ] +enum_smu_table_id = CEnum(ctypes.c_uint32) +SMU_TABLE_PPTABLE = enum_smu_table_id.define('SMU_TABLE_PPTABLE', 0) +SMU_TABLE_WATERMARKS = enum_smu_table_id.define('SMU_TABLE_WATERMARKS', 1) +SMU_TABLE_CUSTOM_DPM = enum_smu_table_id.define('SMU_TABLE_CUSTOM_DPM', 2) +SMU_TABLE_DPMCLOCKS = enum_smu_table_id.define('SMU_TABLE_DPMCLOCKS', 3) +SMU_TABLE_AVFS = enum_smu_table_id.define('SMU_TABLE_AVFS', 4) +SMU_TABLE_AVFS_PSM_DEBUG = enum_smu_table_id.define('SMU_TABLE_AVFS_PSM_DEBUG', 5) +SMU_TABLE_AVFS_FUSE_OVERRIDE = enum_smu_table_id.define('SMU_TABLE_AVFS_FUSE_OVERRIDE', 6) +SMU_TABLE_PMSTATUSLOG = enum_smu_table_id.define('SMU_TABLE_PMSTATUSLOG', 7) +SMU_TABLE_SMU_METRICS = enum_smu_table_id.define('SMU_TABLE_SMU_METRICS', 8) +SMU_TABLE_DRIVER_SMU_CONFIG = enum_smu_table_id.define('SMU_TABLE_DRIVER_SMU_CONFIG', 9) +SMU_TABLE_ACTIVITY_MONITOR_COEFF = enum_smu_table_id.define('SMU_TABLE_ACTIVITY_MONITOR_COEFF', 10) +SMU_TABLE_OVERDRIVE = enum_smu_table_id.define('SMU_TABLE_OVERDRIVE', 11) +SMU_TABLE_I2C_COMMANDS = enum_smu_table_id.define('SMU_TABLE_I2C_COMMANDS', 12) +SMU_TABLE_PACE = enum_smu_table_id.define('SMU_TABLE_PACE', 13) +SMU_TABLE_ECCINFO = enum_smu_table_id.define('SMU_TABLE_ECCINFO', 14) +SMU_TABLE_COMBO_PPTABLE = enum_smu_table_id.define('SMU_TABLE_COMBO_PPTABLE', 15) +SMU_TABLE_WIFIBAND = enum_smu_table_id.define('SMU_TABLE_WIFIBAND', 16) +SMU_TABLE_COUNT = enum_smu_table_id.define('SMU_TABLE_COUNT', 17) - -# values for enumeration 'smu_table_id' -smu_table_id__enumvalues = { - 0: 'SMU_TABLE_PPTABLE', - 1: 'SMU_TABLE_WATERMARKS', - 2: 'SMU_TABLE_CUSTOM_DPM', - 3: 'SMU_TABLE_DPMCLOCKS', - 4: 'SMU_TABLE_AVFS', - 5: 'SMU_TABLE_AVFS_PSM_DEBUG', - 6: 'SMU_TABLE_AVFS_FUSE_OVERRIDE', - 7: 'SMU_TABLE_PMSTATUSLOG', - 8: 'SMU_TABLE_SMU_METRICS', - 9: 'SMU_TABLE_DRIVER_SMU_CONFIG', - 10: 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', - 11: 'SMU_TABLE_OVERDRIVE', - 12: 'SMU_TABLE_I2C_COMMANDS', - 13: 'SMU_TABLE_PACE', - 14: 'SMU_TABLE_ECCINFO', - 15: 'SMU_TABLE_COMBO_PPTABLE', - 16: 'SMU_TABLE_WIFIBAND', - 17: 'SMU_TABLE_COUNT', -} -SMU_TABLE_PPTABLE = 0 -SMU_TABLE_WATERMARKS = 1 -SMU_TABLE_CUSTOM_DPM = 2 -SMU_TABLE_DPMCLOCKS = 3 -SMU_TABLE_AVFS = 4 -SMU_TABLE_AVFS_PSM_DEBUG = 5 -SMU_TABLE_AVFS_FUSE_OVERRIDE = 6 -SMU_TABLE_PMSTATUSLOG = 7 -SMU_TABLE_SMU_METRICS = 8 -SMU_TABLE_DRIVER_SMU_CONFIG = 9 -SMU_TABLE_ACTIVITY_MONITOR_COEFF = 10 -SMU_TABLE_OVERDRIVE = 11 -SMU_TABLE_I2C_COMMANDS = 12 -SMU_TABLE_PACE = 13 -SMU_TABLE_ECCINFO = 14 -SMU_TABLE_COMBO_PPTABLE = 15 -SMU_TABLE_WIFIBAND = 16 -SMU_TABLE_COUNT = 17 -smu_table_id = ctypes.c_uint32 # enum -__all__ = \ - ['ALLOWED_FEATURE_CTRL_DEFAULT', 'ALLOWED_FEATURE_CTRL_SCPM', - 'AVFS_D_COUNT', 'AVFS_D_G', 'AVFS_D_e', 'AVFS_D_e__enumvalues', - 'AVFS_TEMP_COLD', 'AVFS_TEMP_COUNT', 'AVFS_TEMP_HOT', - 'AVFS_TEMP_e', 'AVFS_TEMP_e__enumvalues', 'AVFS_VOLTAGE_COUNT', - 'AVFS_VOLTAGE_GFX', 'AVFS_VOLTAGE_SOC', 'AVFS_VOLTAGE_TYPE_e', - 'AVFS_VOLTAGE_TYPE_e__enumvalues', 'AvfsDcBtcParams_t', - 'AvfsDebugTableExternal_t', 'AvfsDebugTable_t', - 'AvfsFuseOverride_t', 'BACO_SEQUENCE', 'BAMACO_SEQUENCE', - 'BOARD_GPIO_DC_GENLK_CLK', 'BOARD_GPIO_DC_GENLK_VSYNC', - 'BOARD_GPIO_DC_GEN_A', 'BOARD_GPIO_DC_GEN_B', - 'BOARD_GPIO_DC_GEN_C', 'BOARD_GPIO_DC_GEN_D', - 'BOARD_GPIO_DC_GEN_E', 'BOARD_GPIO_DC_GEN_F', - 'BOARD_GPIO_DC_GEN_G', 'BOARD_GPIO_DC_SWAPLOCK_A', - 'BOARD_GPIO_DC_SWAPLOCK_B', 'BOARD_GPIO_LV_EN', - 'BOARD_GPIO_SMUIO_0', 'BOARD_GPIO_SMUIO_1', 'BOARD_GPIO_SMUIO_10', - 'BOARD_GPIO_SMUIO_11', 'BOARD_GPIO_SMUIO_12', - 'BOARD_GPIO_SMUIO_13', 'BOARD_GPIO_SMUIO_14', - 'BOARD_GPIO_SMUIO_15', 'BOARD_GPIO_SMUIO_16', - 'BOARD_GPIO_SMUIO_17', 'BOARD_GPIO_SMUIO_18', - 'BOARD_GPIO_SMUIO_19', 'BOARD_GPIO_SMUIO_2', - 'BOARD_GPIO_SMUIO_20', 'BOARD_GPIO_SMUIO_21', - 'BOARD_GPIO_SMUIO_22', 'BOARD_GPIO_SMUIO_23', - 'BOARD_GPIO_SMUIO_24', 'BOARD_GPIO_SMUIO_25', - 'BOARD_GPIO_SMUIO_26', 'BOARD_GPIO_SMUIO_27', - 'BOARD_GPIO_SMUIO_28', 'BOARD_GPIO_SMUIO_29', - 'BOARD_GPIO_SMUIO_3', 'BOARD_GPIO_SMUIO_30', - 'BOARD_GPIO_SMUIO_31', 'BOARD_GPIO_SMUIO_4', 'BOARD_GPIO_SMUIO_5', - 'BOARD_GPIO_SMUIO_6', 'BOARD_GPIO_SMUIO_7', 'BOARD_GPIO_SMUIO_8', - 'BOARD_GPIO_SMUIO_9', 'BOARD_GPIO_TYPE_e', - 'BOARD_GPIO_TYPE_e__enumvalues', 'BoardTable_t', 'BootValues_t', - 'CMDCONFIG_READWRITE_BIT', 'CMDCONFIG_READWRITE_MASK', - 'CMDCONFIG_RESTART_BIT', 'CMDCONFIG_RESTART_MASK', - 'CMDCONFIG_STOP_BIT', 'CMDCONFIG_STOP_MASK', - 'CUSTOMER_VARIANT_COUNT', 'CUSTOMER_VARIANT_FALCON', - 'CUSTOMER_VARIANT_ROW', 'CUSTOMER_VARIANT_e', - 'CUSTOMER_VARIANT_e__enumvalues', 'CustomSkuTable_t', - 'D3HOTSequence_e', 'D3HOTSequence_e__enumvalues', - 'D3HOT_SEQUENCE_COUNT', 'DCS_ARCH_ASYNC', 'DCS_ARCH_DISABLED', - 'DCS_ARCH_FADCS', 'DCS_ARCH_e', 'DCS_ARCH_e__enumvalues', - 'DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG', - 'DEBUG_OVERRIDE_DFLL_MASTER_MODE', - 'DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK', - 'DEBUG_OVERRIDE_DISABLE_DFLL', - 'DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER', - 'DEBUG_OVERRIDE_DISABLE_FMAX_VMAX', - 'DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS', - 'DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING', - 'DEBUG_OVERRIDE_DISABLE_VCN_PG', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK', - 'DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK', - 'DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY', - 'DEBUG_OVERRIDE_ENABLE_PROFILING_MODE', - 'DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE', - 'DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE', - 'DEBUG_OVERRIDE_NOT_USE', 'DRAM_BIT_WIDTH_COUNT', - 'DRAM_BIT_WIDTH_DISABLED', 'DRAM_BIT_WIDTH_TYPE_e', - 'DRAM_BIT_WIDTH_TYPE_e__enumvalues', 'DRAM_BIT_WIDTH_X_128', - 'DRAM_BIT_WIDTH_X_16', 'DRAM_BIT_WIDTH_X_32', - 'DRAM_BIT_WIDTH_X_64', 'DRAM_BIT_WIDTH_X_8', - 'DpmActivityMonitorCoeffIntExternal_t', - 'DpmActivityMonitorCoeffInt_t', 'DpmDescriptor_t', - 'DriverInfoTable_t', 'DriverReportedClocks_t', - 'DriverSmuConfigExternal_t', 'DriverSmuConfig_t', 'DroopInt_t', - 'ENABLE_DEBUG_FEATURES', 'EPCS_HIGH_POWER', - 'EPCS_HIGH_POWER_LIMIT', 'EPCS_LOW_POWER', 'EPCS_LOW_POWER_LIMIT', - 'EPCS_NORMAL_POWER', 'EPCS_NORMAL_POWER_LIMIT', - 'EPCS_NOT_CONFIGURED', 'EPCS_NO_BOOTUP', 'EPCS_SHORTED_LIMIT', - 'EPCS_SHORTED_POWER', 'EPCS_STATUS_COUNT', 'EPCS_STATUS_e', - 'EPCS_STATUS_e__enumvalues', 'EccInfoTable_t', 'EccInfo_t', - 'FAN_MODE_AUTO', 'FAN_MODE_MANUAL_LINEAR', 'FEATURE_ACDC_BIT', - 'FEATURE_APT_ALL_ENABLE_BIT', 'FEATURE_APT_PF_DCS_BIT', - 'FEATURE_APT_SQ_THROTTLE_BIT', 'FEATURE_ATHUB_MMHUB_PG_BIT', - 'FEATURE_ATHUB_PG_BIT', 'FEATURE_BACO_BIT', 'FEATURE_BACO_CG_BIT', - 'FEATURE_BACO_MPCLK_DS_BIT', 'FEATURE_BOOT_POWER_OPT_BIT', - 'FEATURE_BOOT_TIME_CAL_BIT', 'FEATURE_BTC_COUNT', - 'FEATURE_BTC_NOP', 'FEATURE_BTC_RESTORE', 'FEATURE_BTC_SAVE', - 'FEATURE_BTC_e', 'FEATURE_BTC_e__enumvalues', 'FEATURE_CC6_BIT', - 'FEATURE_CCLK_DPM_BIT', 'FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT', - 'FEATURE_CLOCK_STRETCH_COMPENSATOR', 'FEATURE_CORE_DLDO_BIT', - 'FEATURE_CPPC_BIT', 'FEATURE_CPPC_PREFERRED_CORES', - 'FEATURE_CPUOFF_BIT', 'FEATURE_DATA_CALCULATION_BIT', - 'FEATURE_DCFCLK_DPM_BIT', 'FEATURE_DF_CSTATES_BIT', - 'FEATURE_DF_CSTATE_BIT', 'FEATURE_DF_LIGHT_CSTATE', - 'FEATURE_DPM_DCN_BIT', 'FEATURE_DPM_FCLK_BIT', - 'FEATURE_DPM_GFXCLK_BIT', 'FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT', - 'FEATURE_DPM_LINK_BIT', 'FEATURE_DPM_SOCCLK_BIT', - 'FEATURE_DPM_UCLK_BIT', 'FEATURE_DS_DCFCLK_BIT', - 'FEATURE_DS_FCLK_BIT', 'FEATURE_DS_GFXCLK_BIT', - 'FEATURE_DS_HSPCLK_BIT', 'FEATURE_DS_IPUCLK_BIT', - 'FEATURE_DS_ISPCLK_BIT', 'FEATURE_DS_LCLK_BIT', - 'FEATURE_DS_MP1CLK_BIT', 'FEATURE_DS_MPIO_BIT', - 'FEATURE_DS_MPM_BIT', 'FEATURE_DS_SHUBCLK_BIT', - 'FEATURE_DS_SMNCLK_BIT', 'FEATURE_DS_SOCCLK_BIT', - 'FEATURE_DS_UCLK_BIT', 'FEATURE_DS_UMCCLK_BIT', - 'FEATURE_DS_VCN_BIT', 'FEATURE_DS_VPECLK_BIT', 'FEATURE_DVO_BIT', - 'FEATURE_EDC_BIT', 'FEATURE_EDC_PWRBRK_BIT', - 'FEATURE_FAN_ABNORMAL_BIT', 'FEATURE_FAN_CONTROLLER_BIT', - 'FEATURE_FAN_CONTROL_BIT', 'FEATURE_FAST_PSTATE_CLDO_BIT', - 'FEATURE_FCLK_DPM_BIT', 'FEATURE_FIT_BIT', 'FEATURE_FW_CTF_BIT', - 'FEATURE_FW_DATA_READ_BIT', 'FEATURE_FW_DSTATE_BIT', - 'FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT', 'FEATURE_GFXOFF_BIT', - 'FEATURE_GFX_DCS_BIT', 'FEATURE_GFX_DEM_BIT', - 'FEATURE_GFX_DIDT_XVMIN_BIT', 'FEATURE_GFX_DPM_BIT', - 'FEATURE_GFX_EDC_BIT', 'FEATURE_GFX_EDC_XVMIN_BIT', - 'FEATURE_GFX_IMU_BIT', 'FEATURE_GFX_PCC_DFLL_BIT', - 'FEATURE_GFX_PSM_DIDT_BIT', 'FEATURE_GFX_READ_MARGIN_BIT', - 'FEATURE_GFX_ULV_BIT', 'FEATURE_GTHR_BIT', - 'FEATURE_IOMMUL2_PG_BIT', 'FEATURE_IPU_DPM_BIT', - 'FEATURE_ISP_DPM_BIT', 'FEATURE_LCLK_DPM_BIT', - 'FEATURE_LED_DISPLAY_BIT', 'FEATURE_LOW_POWER_DCNCLKS_BIT', - 'FEATURE_MEM_TEMP_READ_BIT', 'FEATURE_MM_DPM_BIT', - 'FEATURE_OPTIMIZED_VMIN_BIT', 'FEATURE_OUT_OF_BAND_MONITOR_BIT', - 'FEATURE_P3T_BIT', 'FEATURE_PCC_BIT', 'FEATURE_PERF_LIMIT_BIT', - 'FEATURE_PLL_POWER_DOWN_BIT', 'FEATURE_PPT_BIT', - 'FEATURE_PROCHOT_BIT', 'FEATURE_PSI_BIT', 'FEATURE_PWR_ALL', - 'FEATURE_PWR_BACO', 'FEATURE_PWR_DOMAIN_COUNT', - 'FEATURE_PWR_DOMAIN_e', 'FEATURE_PWR_DOMAIN_e__enumvalues', - 'FEATURE_PWR_GFX', 'FEATURE_PWR_S5', 'FEATURE_PWR_SOC', - 'FEATURE_RESERVED0_BIT', 'FEATURE_RESERVED1_BIT', - 'FEATURE_S0I3_BIT', 'FEATURE_SHUBCLK_DPM_BIT', - 'FEATURE_SMARTSHIFT_BIT', 'FEATURE_SMART_L3_RINSER_BIT', - 'FEATURE_SMU_LOW_POWER_BIT', 'FEATURE_SOCCLK_DPM_BIT', - 'FEATURE_SOC_CG_BIT', 'FEATURE_SOC_EDC_XVMIN_BIT', - 'FEATURE_SOC_MPCLK_DS_BIT', 'FEATURE_SOC_PCC_BIT', - 'FEATURE_SPARE_59_BIT', 'FEATURE_SPARE_60_BIT', - 'FEATURE_SPARE_61_BIT', 'FEATURE_SPARE_62_BIT', - 'FEATURE_SPARE_63_BIT', 'FEATURE_STAPM_BIT', 'FEATURE_TDC_BIT', - 'FEATURE_THERMAL_BIT', 'FEATURE_THROTTLERS_BIT', - 'FEATURE_VCN_DPM_BIT', 'FEATURE_VDDIO_MEM_SCALING_BIT', - 'FEATURE_VDDOFF_BIT', 'FEATURE_VDDOFF_ECO_BIT', - 'FEATURE_VMEMP_SCALING_BIT', 'FEATURE_VPE_DPM_BIT', - 'FEATURE_VR0HOT_BIT', 'FEATURE_WHISPER_MODE_BIT', - 'FEATURE_ZSTATES_BIT', 'FEATURE_ZSTATES_ECO_BIT', - 'FOPT_CALC_AC_CALC_DC', 'FOPT_CALC_AC_PPTABLE_DC', 'FOPT_CALC_e', - 'FOPT_CALC_e__enumvalues', 'FOPT_PPTABLE_AC_CALC_DC', - 'FOPT_PPTABLE_AC_PPTABLE_DC', 'FW_DSTATE_CLDO_PRG_BIT', - 'FW_DSTATE_D0i3_2_QUIET_FW_BIT', 'FW_DSTATE_DF_PLL_PWRDN_BIT', - 'FW_DSTATE_G6_HSR_BIT', 'FW_DSTATE_G6_PHY_VMEMP_OFF_BIT', - 'FW_DSTATE_HSR_NON_STROBE_BIT', 'FW_DSTATE_MALL_ALLOC_BIT', - 'FW_DSTATE_MALL_FLUSH_BIT', 'FW_DSTATE_MEM_PLL_PWRDN_BIT', - 'FW_DSTATE_MEM_PSI_BIT', 'FW_DSTATE_MMHUB_INTERLOCK_BIT', - 'FW_DSTATE_MP0_ENTER_WFI_BIT', 'FW_DSTATE_MP1_WHISPER_MODE_BIT', - 'FW_DSTATE_SMN_DS_BIT', 'FW_DSTATE_SOC_LIV_MIN_BIT', - 'FW_DSTATE_SOC_PLL_PWRDN_BIT', 'FW_DSTATE_SOC_PSI_BIT', - 'FW_DSTATE_SOC_ULV_BIT', 'FanMode_e', 'FanMode_e__enumvalues', - 'FwStatus_t', 'FwStatus_t_v14_0_1', - 'GPIO_INT_POLARITY_ACTIVE_HIGH', 'GPIO_INT_POLARITY_ACTIVE_LOW', - 'GpioIntPolarity_e', 'GpioIntPolarity_e__enumvalues', - 'I2C_CMD_COUNT', 'I2C_CMD_READ', 'I2C_CMD_WRITE', - 'I2C_CONTROLLER_DISABLED', 'I2C_CONTROLLER_ENABLED', - 'I2C_CONTROLLER_NAME_COUNT', 'I2C_CONTROLLER_NAME_FAN_INTAKE', - 'I2C_CONTROLLER_NAME_LIQUID0', 'I2C_CONTROLLER_NAME_LIQUID1', - 'I2C_CONTROLLER_NAME_PLX', 'I2C_CONTROLLER_NAME_VR_GFX', - 'I2C_CONTROLLER_NAME_VR_SOC', 'I2C_CONTROLLER_NAME_VR_VDDIO', - 'I2C_CONTROLLER_NAME_VR_VMEMP', 'I2C_CONTROLLER_PORT_0', - 'I2C_CONTROLLER_PORT_1', 'I2C_CONTROLLER_PORT_COUNT', - 'I2C_CONTROLLER_PROTOCOL_COUNT', - 'I2C_CONTROLLER_PROTOCOL_INA3221', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX31875', - 'I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', - 'I2C_CONTROLLER_PROTOCOL_VR_IR35217', - 'I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5', - 'I2C_CONTROLLER_THROTTLER_COUNT', - 'I2C_CONTROLLER_THROTTLER_FAN_INTAKE', - 'I2C_CONTROLLER_THROTTLER_INA3221', - 'I2C_CONTROLLER_THROTTLER_LIQUID0', - 'I2C_CONTROLLER_THROTTLER_LIQUID1', - 'I2C_CONTROLLER_THROTTLER_PLX', - 'I2C_CONTROLLER_THROTTLER_TYPE_NONE', - 'I2C_CONTROLLER_THROTTLER_VR_GFX', - 'I2C_CONTROLLER_THROTTLER_VR_SOC', - 'I2C_CONTROLLER_THROTTLER_VR_VDDIO', - 'I2C_CONTROLLER_THROTTLER_VR_VMEMP', 'I2C_PORT_GPIO', - 'I2C_PORT_SVD_SCL', 'I2C_SPEED_COUNT', 'I2C_SPEED_FAST_100K', - 'I2C_SPEED_FAST_400K', 'I2C_SPEED_FAST_50K', - 'I2C_SPEED_FAST_PLUS_1M', 'I2C_SPEED_HIGH_1M', - 'I2C_SPEED_HIGH_2M', 'I2cCmdType_e', 'I2cCmdType_e__enumvalues', - 'I2cControllerConfig_t', 'I2cControllerName_e', - 'I2cControllerName_e__enumvalues', 'I2cControllerPort_e', - 'I2cControllerPort_e__enumvalues', 'I2cControllerProtocol_e', - 'I2cControllerProtocol_e__enumvalues', 'I2cControllerThrottler_e', - 'I2cControllerThrottler_e__enumvalues', 'I2cPort_e', - 'I2cPort_e__enumvalues', 'I2cSpeed_e', 'I2cSpeed_e__enumvalues', - 'IH_INTERRUPT_CONTEXT_ID_AC', 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D0', - 'IH_INTERRUPT_CONTEXT_ID_AUDIO_D3', - 'IH_INTERRUPT_CONTEXT_ID_BACO', 'IH_INTERRUPT_CONTEXT_ID_DC', - 'IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE', - 'IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL', - 'IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY', - 'IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING', - 'IH_INTERRUPT_ID_TO_DRIVER', 'INVALID_BOARD_GPIO', - 'LED_DISPLAY_ERROR_BIT', 'LED_DISPLAY_GFX_DPM_BIT', - 'LED_DISPLAY_PCIE_BIT', 'LinearInt_t', 'MAX_BOARD_DC_GPIO_NUM', - 'MAX_BOARD_GPIO_SMUIO_NUM', 'MAX_SW_I2C_COMMANDS', - 'MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT', - 'MEM_TEMP_READ_IN_BAND_REFRESH_BIT', - 'MEM_TEMP_READ_OUT_OF_BAND_BIT', 'MEM_VENDOR_COUNT', - 'MEM_VENDOR_ELPIDA', 'MEM_VENDOR_ESMT', 'MEM_VENDOR_ETRON', - 'MEM_VENDOR_HYNIX', 'MEM_VENDOR_INFINEON', 'MEM_VENDOR_MICRON', - 'MEM_VENDOR_MOSEL', 'MEM_VENDOR_NANYA', 'MEM_VENDOR_PLACEHOLDER0', - 'MEM_VENDOR_PLACEHOLDER1', 'MEM_VENDOR_PLACEHOLDER2', - 'MEM_VENDOR_PLACEHOLDER3', 'MEM_VENDOR_PLACEHOLDER4', - 'MEM_VENDOR_PLACEHOLDER5', 'MEM_VENDOR_SAMSUNG', - 'MEM_VENDOR_WINBOND', 'MEM_VENDOR_e', 'MEM_VENDOR_e__enumvalues', - 'MSR_SEQUENCE', 'MsgLimits_t', 'NUM_DCFCLK_DPM_LEVELS', - 'NUM_DCLK_DPM_LEVELS', 'NUM_DISPCLK_DPM_LEVELS', - 'NUM_DPPCLK_DPM_LEVELS', 'NUM_DPREFCLK_DPM_LEVELS', - 'NUM_DTBCLK_DPM_LEVELS', 'NUM_FCLK_DPM_LEVELS', 'NUM_FEATURES', - 'NUM_GFXCLK_DPM_LEVELS', 'NUM_I2C_CONTROLLERS', 'NUM_LINK_LEVELS', - 'NUM_MP0CLK_DPM_LEVELS', 'NUM_OD_FAN_MAX_POINTS', - 'NUM_SOCCLK_DPM_LEVELS', 'NUM_UCLK_DPM_LEVELS', - 'NUM_VCLK_DPM_LEVELS', 'NUM_WM_RANGES', 'OD_FAIL_e', - 'OD_FAIL_e__enumvalues', 'OD_FAN_ACOUSTIC_LIMIT_ERROR', - 'OD_FAN_ACOUSTIC_TARGET_ERROR', 'OD_FAN_CURVE_PWM_ERROR', - 'OD_FAN_CURVE_TEMP_ERROR', 'OD_FAN_MIN_PWM_ERROR', - 'OD_FAN_TARGET_TEMP_ERROR', 'OD_FAN_ZERO_RPM_STOP_TEMP_ERROR', - 'OD_FCLK_ERROR', 'OD_FULL_CTRL_FCLK_ERROR', - 'OD_FULL_CTRL_GFXCLK_ERROR', 'OD_FULL_CTRL_UCLK_ERROR', - 'OD_FULL_CTRL_VDD_GFX_ERROR', 'OD_FULL_CTRL_VDD_SOC_ERROR', - 'OD_GFXCLK_ERROR', 'OD_GFXCLK_VF_CURVE_OFFSET_ERROR', - 'OD_INVALID_FEATURE_COMBO_ERROR', 'OD_NO_ERROR', - 'OD_OP_GFX_EDC_ERROR', 'OD_OP_GFX_PCC_ERROR', 'OD_OP_TEMP_ERROR', - 'OD_POWER_FEATURE_CTRL_ERROR', 'OD_PPT_ERROR', - 'OD_REQUEST_ADVANCED_NOT_SUPPORTED', 'OD_TDC_ERROR', - 'OD_UCLK_ERROR', 'OD_UNSUPPORTED_FEATURE', - 'OD_VDD_GFX_VMAX_ERROR', 'OD_VDD_SOC_VMAX_ERROR', - 'OverDriveLimits_t', 'OverDriveTableExternal_t', - 'OverDriveTable_t', 'PERF_LEVEL_ACTIVITY', - 'PERF_LEVEL_POWER_CONTAINMENT', 'PFE_Settings_t', - 'PG_DYNAMIC_MODE', 'PG_POWER_DOWN', 'PG_POWER_UP', - 'PG_STATIC_MODE', 'PMFW_VOLT_PLANE_COUNT', 'PMFW_VOLT_PLANE_GFX', - 'PMFW_VOLT_PLANE_SOC', 'PMFW_VOLT_PLANE_e', - 'PMFW_VOLT_PLANE_e__enumvalues', 'POWER_SOURCE_AC', - 'POWER_SOURCE_COUNT', 'POWER_SOURCE_DC', 'POWER_SOURCE_e', - 'POWER_SOURCE_e__enumvalues', 'PPCLK_COUNT', 'PPCLK_DCFCLK', - 'PPCLK_DCLK_0', 'PPCLK_DISPCLK', 'PPCLK_DPPCLK', 'PPCLK_DPREFCLK', - 'PPCLK_DTBCLK', 'PPCLK_FCLK', 'PPCLK_GFXCLK', 'PPCLK_SOCCLK', - 'PPCLK_UCLK', 'PPCLK_VCLK_0', 'PPCLK_e', 'PPCLK_e__enumvalues', - 'PPSMC_MSG_AllowGfxDcs', 'PPSMC_MSG_AllowGfxOff', - 'PPSMC_MSG_AllowIHHostInterrupt', 'PPSMC_MSG_ArmD3', - 'PPSMC_MSG_BacoAudioD3PME', 'PPSMC_MSG_DisableAllSmuFeatures', - 'PPSMC_MSG_DisableSmuFeaturesHigh', - 'PPSMC_MSG_DisableSmuFeaturesLow', 'PPSMC_MSG_DisallowGfxDcs', - 'PPSMC_MSG_DisallowGfxOff', 'PPSMC_MSG_DramLogSetDramAddrHigh', - 'PPSMC_MSG_DramLogSetDramAddrLow', 'PPSMC_MSG_DramLogSetDramSize', - 'PPSMC_MSG_DummyUndefined', 'PPSMC_MSG_DumpSTBtoDram', - 'PPSMC_MSG_EnableAllSmuFeatures', - 'PPSMC_MSG_EnableAudioStutterWA', 'PPSMC_MSG_EnableShadowDpm', - 'PPSMC_MSG_EnableSmuFeaturesHigh', - 'PPSMC_MSG_EnableSmuFeaturesLow', 'PPSMC_MSG_EnterBaco', - 'PPSMC_MSG_ExitBaco', 'PPSMC_MSG_ExtPwrConnSupport', - 'PPSMC_MSG_GetAllRunningSmuFeatures', - 'PPSMC_MSG_GetDcModeMaxDpmFreq', 'PPSMC_MSG_GetDpmFreqByIndex', - 'PPSMC_MSG_GetDriverIfVersion', 'PPSMC_MSG_GetMaxDpmFreq', - 'PPSMC_MSG_GetMinDpmFreq', 'PPSMC_MSG_GetPptLimit', - 'PPSMC_MSG_GetRunningSmuFeaturesHigh', - 'PPSMC_MSG_GetRunningSmuFeaturesLow', 'PPSMC_MSG_GetSmuVersion', - 'PPSMC_MSG_GetSvi3Voltage', 'PPSMC_MSG_GetVoltageByDpm', - 'PPSMC_MSG_Mode3Reset', 'PPSMC_MSG_NotifyPowerSource', - 'PPSMC_MSG_OverridePcieParameters', 'PPSMC_MSG_PowerDownJpeg', - 'PPSMC_MSG_PowerDownUmsch', 'PPSMC_MSG_PowerDownVcn', - 'PPSMC_MSG_PowerUpJpeg', 'PPSMC_MSG_PowerUpUmsch', - 'PPSMC_MSG_PowerUpVcn', - 'PPSMC_MSG_PreloadSwPstateForUclkOverDrive', - 'PPSMC_MSG_PrepareMp1ForUnload', - 'PPSMC_MSG_ReenableAcDcInterrupt', 'PPSMC_MSG_RunDcBtc', - 'PPSMC_MSG_STBtoDramLogSetDramAddress', - 'PPSMC_MSG_STBtoDramLogSetDramSize', - 'PPSMC_MSG_SetAllowedFeaturesMaskHigh', - 'PPSMC_MSG_SetAllowedFeaturesMaskLow', - 'PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel', - 'PPSMC_MSG_SetDcsArch', 'PPSMC_MSG_SetDriverDramAddr', - 'PPSMC_MSG_SetDriverDramAddrHigh', - 'PPSMC_MSG_SetDriverDramAddrLow', - 'PPSMC_MSG_SetExternalClientDfCstateAllow', - 'PPSMC_MSG_SetFwDstatesMask', 'PPSMC_MSG_SetHardMaxByFreq', - 'PPSMC_MSG_SetHardMinByFreq', 'PPSMC_MSG_SetMGpuFanBoostLimitRpm', - 'PPSMC_MSG_SetNumBadMemoryPagesRetired', - 'PPSMC_MSG_SetOBMTraceBufferLogging', 'PPSMC_MSG_SetPptLimit', - 'PPSMC_MSG_SetPriorityDeltaGain', 'PPSMC_MSG_SetSoftMaxByFreq', - 'PPSMC_MSG_SetSoftMinByFreq', - 'PPSMC_MSG_SetSystemVirtualDramAddrHigh', - 'PPSMC_MSG_SetSystemVirtualDramAddrLow', - 'PPSMC_MSG_SetTemperatureInputSelect', - 'PPSMC_MSG_SetThrottlerMask', 'PPSMC_MSG_SetToolsDramAddr', - 'PPSMC_MSG_SetToolsDramAddrHigh', 'PPSMC_MSG_SetToolsDramAddrLow', - 'PPSMC_MSG_SetVideoFps', 'PPSMC_MSG_SetWorkloadMask', - 'PPSMC_MSG_TestMessage', 'PPSMC_MSG_TransferTableDram2Smu', - 'PPSMC_MSG_TransferTableDram2SmuWithAddr', - 'PPSMC_MSG_TransferTableSmu2Dram', - 'PPSMC_MSG_TransferTableSmu2DramWithAddr', - 'PPSMC_MSG_TriggerVFFLR', 'PPSMC_MSG_UpdatePolicy', - 'PPSMC_MSG_UseDefaultPPTable', 'PPSMC_MSG_UseProfilingMode', - 'PPSMC_Message_Count', 'PPSMC_Result_CmdRejectedBusy', - 'PPSMC_Result_CmdRejectedPrereq', 'PPSMC_Result_Failed', - 'PPSMC_Result_OK', 'PPSMC_Result_UnknownCmd', 'PPSMC_VERSION', - 'PPTABLE_VERSION', 'PPT_THROTTLER_COUNT', 'PPT_THROTTLER_PPT0', - 'PPT_THROTTLER_PPT1', 'PPT_THROTTLER_PPT2', 'PPT_THROTTLER_PPT3', - 'PPT_THROTTLER_e', 'PPT_THROTTLER_e__enumvalues', 'PPTable_t', - 'PP_GRTAVFS_FW_COMMON_FUSE_COUNT', 'PP_GRTAVFS_FW_COMMON_FUSE_e', - 'PP_GRTAVFS_FW_COMMON_FUSE_e__enumvalues', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0', - 'PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3', - 'PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4', 'PP_GRTAVFS_FW_SEP_FUSE_COUNT', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3', - 'PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4', - 'PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1', - 'PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY', - 'PP_GRTAVFS_FW_SEP_FUSE_e', - 'PP_GRTAVFS_FW_SEP_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3', - 'PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE0', 'PP_GRTAVFS_HW_CPO_CTL_ZONE1', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE2', 'PP_GRTAVFS_HW_CPO_CTL_ZONE3', - 'PP_GRTAVFS_HW_CPO_CTL_ZONE4', 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3', - 'PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4', 'PP_GRTAVFS_HW_FUSE_COUNT', - 'PP_GRTAVFS_HW_FUSE_e', 'PP_GRTAVFS_HW_FUSE_e__enumvalues', - 'PP_GRTAVFS_HW_RESERVED_0', 'PP_GRTAVFS_HW_RESERVED_1', - 'PP_GRTAVFS_HW_RESERVED_2', 'PP_GRTAVFS_HW_RESERVED_3', - 'PP_GRTAVFS_HW_RESERVED_4', 'PP_GRTAVFS_HW_RESERVED_5', - 'PP_GRTAVFS_HW_RESERVED_6', 'PP_GRTAVFS_HW_VOLTAGE_GB', - 'PP_GRTAVFS_HW_ZONE0_VF', 'PP_GRTAVFS_HW_ZONE1_VF1', - 'PP_GRTAVFS_HW_ZONE2_VF2', 'PP_GRTAVFS_HW_ZONE3_VF3', - 'PP_NUM_OD_VF_CURVE_POINTS', 'PP_NUM_PSM_DIDT_PWL_ZONES', - 'PP_NUM_RTAVFS_PWL_ZONES', 'PP_OD_FEATURE_COUNT', - 'PP_OD_FEATURE_EDC_BIT', 'PP_OD_FEATURE_FAN_CURVE_BIT', - 'PP_OD_FEATURE_FAN_LEGACY_BIT', 'PP_OD_FEATURE_FCLK_BIT', - 'PP_OD_FEATURE_FULL_CTRL_BIT', 'PP_OD_FEATURE_GFXCLK_BIT', - 'PP_OD_FEATURE_GFX_VF_CURVE_BIT', 'PP_OD_FEATURE_GFX_VMAX_BIT', - 'PP_OD_FEATURE_PPT_BIT', 'PP_OD_FEATURE_SOC_VMAX_BIT', - 'PP_OD_FEATURE_TDC_BIT', 'PP_OD_FEATURE_TEMPERATURE_BIT', - 'PP_OD_FEATURE_UCLK_BIT', 'PP_OD_FEATURE_ZERO_FAN_BIT', - 'PP_OD_POWER_FEATURE_ALWAYS_DISABLED', - 'PP_OD_POWER_FEATURE_ALWAYS_ENABLED', - 'PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING', - 'PP_OD_POWER_FEATURE_e', 'PP_OD_POWER_FEATURE_e__enumvalues', - 'PSI_SEL_VR0_PLANE0_PSI0', 'PSI_SEL_VR0_PLANE0_PSI1', - 'PSI_SEL_VR0_PLANE1_PSI0', 'PSI_SEL_VR0_PLANE1_PSI1', - 'PSI_SEL_VR1_PLANE0_PSI0', 'PSI_SEL_VR1_PLANE0_PSI1', - 'PSI_SEL_VR1_PLANE1_PSI0', 'PSI_SEL_VR1_PLANE1_PSI1', - 'PWR_CONFIG_TBP_DESKTOP', 'PWR_CONFIG_TBP_MOBILE', - 'PWR_CONFIG_TCP_ESTIMATED', 'PWR_CONFIG_TCP_MEASURED', - 'PWR_CONFIG_TDP', 'PWR_CONFIG_TGP', 'PowerGatingMode_e', - 'PowerGatingMode_e__enumvalues', 'PowerGatingSettings_e', - 'PowerGatingSettings_e__enumvalues', 'PwrConfig_e', - 'PwrConfig_e__enumvalues', 'QuadraticInt_t', - 'SMARTSHIFT_VERSION_1', 'SMARTSHIFT_VERSION_2', - 'SMARTSHIFT_VERSION_3', 'SMARTSHIFT_VERSION_e', - 'SMARTSHIFT_VERSION_e__enumvalues', 'SMU14_DRIVER_IF_V14_0_H', - 'SMU14_Firmware_Footer', 'SMU_CLK_COUNT', - 'SMU_CUSTOM_FAN_SPEED_PWM', 'SMU_CUSTOM_FAN_SPEED_RPM', - 'SMU_DCEFCLK', 'SMU_DCLK', 'SMU_DCLK1', 'SMU_DEFAULT_PPT_LIMIT', - 'SMU_DISPCLK', 'SMU_DPM_USER_PROFILE_RESTORE', 'SMU_ECLK', - 'SMU_FAST_PPT_LIMIT', 'SMU_FCLK', 'SMU_FW_NAME_LEN', - 'SMU_Firmware_Header', 'SMU_GFXCLK', 'SMU_LCLK', 'SMU_MCLK', - 'SMU_MEMORY_POOL_SIZE_1_GB', 'SMU_MEMORY_POOL_SIZE_256_MB', - 'SMU_MEMORY_POOL_SIZE_2_GB', 'SMU_MEMORY_POOL_SIZE_512_MB', - 'SMU_MEMORY_POOL_SIZE_ZERO', 'SMU_OD_ACOUSTIC_LIMIT', - 'SMU_OD_ACOUSTIC_TARGET', 'SMU_OD_CCLK', 'SMU_OD_FAN_CURVE', - 'SMU_OD_FAN_MINIMUM_PWM', 'SMU_OD_FAN_TARGET_TEMPERATURE', - 'SMU_OD_MCLK', 'SMU_OD_RANGE', 'SMU_OD_SCLK', 'SMU_OD_VDDC_CURVE', - 'SMU_OD_VDDGFX_OFFSET', 'SMU_PCIE', 'SMU_PHYCLK', 'SMU_PIXCLK', - 'SMU_POWER_SOURCE_AC', 'SMU_POWER_SOURCE_COUNT', - 'SMU_POWER_SOURCE_DC', 'SMU_PPT_LIMIT_CURRENT', - 'SMU_PPT_LIMIT_DEFAULT', 'SMU_PPT_LIMIT_MAX', 'SMU_PPT_LIMIT_MIN', - 'SMU_REFRESHRATE_SOURCE_EDID', 'SMU_REFRESHRATE_SOURCE_EXPLICIT', - 'SMU_SCLK', 'SMU_SOCCLK', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE', - 'SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW', - 'SMU_STATE_CLASSIFICATION_FLAG_ACPI', - 'SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_BACO', - 'SMU_STATE_CLASSIFICATION_FLAG_BOOT', - 'SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE', - 'SMU_STATE_CLASSIFICATION_FLAG_FORCED', - 'SMU_STATE_CLASSIFICATION_FLAG_HD2', - 'SMU_STATE_CLASSIFICATION_FLAG_RESET', - 'SMU_STATE_CLASSIFICATION_FLAG_THERMAL', - 'SMU_STATE_CLASSIFICATION_FLAG_ULV', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_HD', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC', - 'SMU_STATE_CLASSIFICATION_FLAG_UVD_SD', 'SMU_STATE_UI_LABEL_BACO', - 'SMU_STATE_UI_LABEL_BALLANCED', 'SMU_STATE_UI_LABEL_BATTERY', - 'SMU_STATE_UI_LABEL_MIDDLE_HIGHT', 'SMU_STATE_UI_LABEL_NONE', - 'SMU_STATE_UI_LABEL_PERFORMANCE', 'SMU_STATE_UI_TABEL_MIDDLE_LOW', - 'SMU_TABLE_ACTIVITY_MONITOR_COEFF', 'SMU_TABLE_AVFS', - 'SMU_TABLE_AVFS_FUSE_OVERRIDE', 'SMU_TABLE_AVFS_PSM_DEBUG', - 'SMU_TABLE_COMBO_PPTABLE', 'SMU_TABLE_COUNT', - 'SMU_TABLE_CUSTOM_DPM', 'SMU_TABLE_DPMCLOCKS', - 'SMU_TABLE_DRIVER_SMU_CONFIG', 'SMU_TABLE_ECCINFO', - 'SMU_TABLE_I2C_COMMANDS', 'SMU_TABLE_OVERDRIVE', 'SMU_TABLE_PACE', - 'SMU_TABLE_PMSTATUSLOG', 'SMU_TABLE_PPTABLE', - 'SMU_TABLE_SMU_METRICS', 'SMU_TABLE_WATERMARKS', - 'SMU_TABLE_WIFIBAND', 'SMU_TEMPERATURE_UNITS_PER_CENTIGRADES', - 'SMU_THERMAL_MAXIMUM_ALERT_TEMP', - 'SMU_THERMAL_MINIMUM_ALERT_TEMP', 'SMU_THROTTLER_APCC_BIT', - 'SMU_THROTTLER_EDC_CPU_BIT', 'SMU_THROTTLER_EDC_GFX_BIT', - 'SMU_THROTTLER_FIT_BIT', 'SMU_THROTTLER_FPPT_BIT', - 'SMU_THROTTLER_PPM_BIT', 'SMU_THROTTLER_PPT0_BIT', - 'SMU_THROTTLER_PPT1_BIT', 'SMU_THROTTLER_PPT2_BIT', - 'SMU_THROTTLER_PPT3_BIT', 'SMU_THROTTLER_PROCHOT_CPU_BIT', - 'SMU_THROTTLER_PROCHOT_GFX_BIT', 'SMU_THROTTLER_SPL_BIT', - 'SMU_THROTTLER_SPPT_APU_BIT', 'SMU_THROTTLER_SPPT_BIT', - 'SMU_THROTTLER_TDC_CVIP_BIT', 'SMU_THROTTLER_TDC_GFX_BIT', - 'SMU_THROTTLER_TDC_MEM_BIT', 'SMU_THROTTLER_TDC_SOC_BIT', - 'SMU_THROTTLER_TDC_VDD_BIT', 'SMU_THROTTLER_TEMP_CORE_BIT', - 'SMU_THROTTLER_TEMP_EDGE_BIT', 'SMU_THROTTLER_TEMP_GPU_BIT', - 'SMU_THROTTLER_TEMP_HOTSPOT_BIT', - 'SMU_THROTTLER_TEMP_LIQUID0_BIT', - 'SMU_THROTTLER_TEMP_LIQUID1_BIT', 'SMU_THROTTLER_TEMP_MEM_BIT', - 'SMU_THROTTLER_TEMP_SOC_BIT', 'SMU_THROTTLER_TEMP_VR_GFX_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM0_BIT', - 'SMU_THROTTLER_TEMP_VR_MEM1_BIT', 'SMU_THROTTLER_TEMP_VR_SOC_BIT', - 'SMU_THROTTLER_VRHOT0_BIT', 'SMU_THROTTLER_VRHOT1_BIT', - 'SMU_UCLK', 'SMU_V14_0_2_PPSMC_H', 'SMU_VCLK', 'SMU_VCLK1', - 'SVI_PLANE_COUNT', 'SVI_PLANE_VDDCI_MEM', 'SVI_PLANE_VDDIO_MEM', - 'SVI_PLANE_VDD_GFX', 'SVI_PLANE_VDD_SOC', 'SVI_PLANE_e', - 'SVI_PLANE_e__enumvalues', 'SVI_PSI_0', 'SVI_PSI_1', 'SVI_PSI_2', - 'SVI_PSI_3', 'SVI_PSI_4', 'SVI_PSI_5', 'SVI_PSI_6', 'SVI_PSI_7', - 'SVI_PSI_e', 'SVI_PSI_e__enumvalues', 'SkuTable_t', - 'SmuMetricsExternal_t', 'SmuMetrics_t', 'Svi3RegulatorSettings_t', - 'SviTelemetryScale_t', 'SwI2cCmd_t', 'SwI2cRequestExternal_t', - 'SwI2cRequest_t', 'TABLE_ACOUSTIC_LIMIT_RPM_FAILED', - 'TABLE_ACOUSTIC_TARGET_RPM_FAILED', - 'TABLE_ACTIVITY_MONITOR_COEFF', 'TABLE_AVFS_PSM_DEBUG', - 'TABLE_COMBO_PPTABLE', 'TABLE_COUNT', 'TABLE_CUSTOM_SKUTABLE', - 'TABLE_DRIVER_INFO', 'TABLE_DRIVER_SMU_CONFIG', 'TABLE_ECCINFO', - 'TABLE_FAN_PWM_MIN_FAILED', 'TABLE_FAN_START_TEMP_FAILED', - 'TABLE_FAN_STOP_TEMP_FAILED', 'TABLE_FAN_TARGET_TEMP_FAILED', - 'TABLE_I2C_COMMANDS', 'TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED', - 'TABLE_OVERDRIVE', 'TABLE_PMSTATUSLOG', 'TABLE_PPTABLE', - 'TABLE_PPT_FAILED', 'TABLE_SMU_METRICS', 'TABLE_TDC_FAILED', - 'TABLE_TEMP_FAILED', 'TABLE_TRANSFER_FAILED', 'TABLE_TRANSFER_OK', - 'TABLE_TRANSFER_PENDING', 'TABLE_WATERMARKS', - 'TDC_THROTTLER_COUNT', 'TDC_THROTTLER_GFX', 'TDC_THROTTLER_SOC', - 'TDC_THROTTLER_e', 'TDC_THROTTLER_e__enumvalues', 'TEMP_COUNT', - 'TEMP_EDGE', 'TEMP_HOTSPOT', 'TEMP_HOTSPOT_GFX', - 'TEMP_HOTSPOT_SOC', 'TEMP_LIQUID0', 'TEMP_LIQUID1', 'TEMP_MEM', - 'TEMP_PLX', 'TEMP_VR_GFX', 'TEMP_VR_MEM0', 'TEMP_VR_MEM1', - 'TEMP_VR_SOC', 'TEMP_e', 'TEMP_e__enumvalues', 'THROTTLER_COUNT', - 'THROTTLER_FIT_BIT', 'THROTTLER_GFX_APCC_PLUS_BIT', - 'THROTTLER_GFX_DVO_BIT', 'THROTTLER_PPT0_BIT', - 'THROTTLER_PPT1_BIT', 'THROTTLER_PPT2_BIT', 'THROTTLER_PPT3_BIT', - 'THROTTLER_TDC_GFX_BIT', 'THROTTLER_TDC_SOC_BIT', - 'THROTTLER_TEMP_EDGE_BIT', 'THROTTLER_TEMP_HOTSPOT_BIT', - 'THROTTLER_TEMP_HOTSPOT_GFX_BIT', - 'THROTTLER_TEMP_HOTSPOT_SOC_BIT', 'THROTTLER_TEMP_LIQUID0_BIT', - 'THROTTLER_TEMP_LIQUID1_BIT', 'THROTTLER_TEMP_MEM_BIT', - 'THROTTLER_TEMP_PLX_BIT', 'THROTTLER_TEMP_VR_GFX_BIT', - 'THROTTLER_TEMP_VR_MEM0_BIT', 'THROTTLER_TEMP_VR_MEM1_BIT', - 'THROTTLER_TEMP_VR_SOC_BIT', 'UCLK_DIV_BY_1', 'UCLK_DIV_BY_2', - 'UCLK_DIV_BY_4', 'UCLK_DIV_BY_8', 'UCLK_DIV_e', - 'UCLK_DIV_e__enumvalues', 'ULPS_SEQUENCE', 'VOLTAGE_MODE_COUNT', - 'VOLTAGE_MODE_FUSES', 'VOLTAGE_MODE_PPTABLE', 'VOLTAGE_MODE_e', - 'VOLTAGE_MODE_e__enumvalues', 'VR_MAPPING_PLANE_SELECT_MASK', - 'VR_MAPPING_PLANE_SELECT_SHIFT', 'VR_MAPPING_VR_SELECT_MASK', - 'VR_MAPPING_VR_SELECT_SHIFT', 'WATERMARKS_CLOCK_RANGE', - 'WATERMARKS_COUNT', 'WATERMARKS_DUMMY_PSTATE', - 'WATERMARKS_FLAGS_e', 'WATERMARKS_FLAGS_e__enumvalues', - 'WATERMARKS_MALL', 'WORKLOAD_PPLIB_CGVDI_BIT', - 'WORKLOAD_PPLIB_COMPUTE_BIT', 'WORKLOAD_PPLIB_COUNT', - 'WORKLOAD_PPLIB_CUSTOM_BIT', 'WORKLOAD_PPLIB_DEFAULT_BIT', - 'WORKLOAD_PPLIB_DIRECT_ML_BIT', - 'WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT', - 'WORKLOAD_PPLIB_POWER_SAVING_BIT', 'WORKLOAD_PPLIB_VIDEO_BIT', - 'WORKLOAD_PPLIB_VR_BIT', 'WORKLOAD_PPLIB_WINDOW_3D_BIT', - 'WatermarkRowGeneric_t', 'WatermarksExternal_t', 'Watermarks_t', - '__AMDGPU_SMU_H__', '__SMU_V14_0_0_PMFW_H__', 'bool', - 'c__EA_AVFS_D_e', 'c__EA_AVFS_TEMP_e', - 'c__EA_AVFS_VOLTAGE_TYPE_e', 'c__EA_BOARD_GPIO_TYPE_e', - 'c__EA_CUSTOMER_VARIANT_e', 'c__EA_D3HOTSequence_e', - 'c__EA_DCS_ARCH_e', 'c__EA_DRAM_BIT_WIDTH_TYPE_e', - 'c__EA_EPCS_STATUS_e', 'c__EA_FEATURE_BTC_e', - 'c__EA_FEATURE_PWR_DOMAIN_e', 'c__EA_FOPT_CALC_e', - 'c__EA_FanMode_e', 'c__EA_GpioIntPolarity_e', - 'c__EA_I2cCmdType_e', 'c__EA_I2cControllerName_e', - 'c__EA_I2cControllerPort_e', 'c__EA_I2cControllerProtocol_e', - 'c__EA_I2cControllerThrottler_e', 'c__EA_I2cPort_e', - 'c__EA_I2cSpeed_e', 'c__EA_MEM_VENDOR_e', 'c__EA_OD_FAIL_e', - 'c__EA_PMFW_VOLT_PLANE_e', 'c__EA_POWER_SOURCE_e', - 'c__EA_PPCLK_e', 'c__EA_PPT_THROTTLER_e', - 'c__EA_PP_GRTAVFS_FW_COMMON_FUSE_e', - 'c__EA_PP_GRTAVFS_FW_SEP_FUSE_e', 'c__EA_PP_GRTAVFS_HW_FUSE_e', - 'c__EA_PP_OD_POWER_FEATURE_e', 'c__EA_PowerGatingMode_e', - 'c__EA_PowerGatingSettings_e', 'c__EA_PwrConfig_e', - 'c__EA_SMARTSHIFT_VERSION_e', 'c__EA_SVI_PLANE_e', - 'c__EA_SVI_PSI_e', 'c__EA_TDC_THROTTLER_e', 'c__EA_TEMP_e', - 'c__EA_UCLK_DIV_e', 'c__EA_VOLTAGE_MODE_e', - 'c__EA_WATERMARKS_FLAGS_e', 'int16_t', 'int32_t', 'int8_t', - 'smu_clk_type', 'smu_memory_pool_size', - 'smu_perf_level_designation', 'smu_power_src_type', - 'smu_ppt_limit_level', 'smu_ppt_limit_type', - 'smu_refreshrate_source', 'smu_state_classification_flag', - 'smu_state_ui_label', 'smu_table_id', - 'struct_SMU14_Firmware_Footer', 'struct_amdgpu_bo', - 'struct_c__SA_AvfsDcBtcParams_t', - 'struct_c__SA_AvfsDebugTableExternal_t', - 'struct_c__SA_AvfsDebugTable_t', - 'struct_c__SA_AvfsFuseOverride_t', 'struct_c__SA_BoardTable_t', - 'struct_c__SA_BootValues_t', 'struct_c__SA_CustomSkuTable_t', - 'struct_c__SA_DpmActivityMonitorCoeffIntExternal_t', - 'struct_c__SA_DpmActivityMonitorCoeffInt_t', - 'struct_c__SA_DpmDescriptor_t', 'struct_c__SA_DriverInfoTable_t', - 'struct_c__SA_DriverReportedClocks_t', - 'struct_c__SA_DriverSmuConfigExternal_t', - 'struct_c__SA_DriverSmuConfig_t', 'struct_c__SA_DroopInt_t', - 'struct_c__SA_EccInfoTable_t', 'struct_c__SA_EccInfo_t', - 'struct_c__SA_FwStatus_t', 'struct_c__SA_FwStatus_t_v14_0_1', - 'struct_c__SA_I2cControllerConfig_t', 'struct_c__SA_LinearInt_t', - 'struct_c__SA_MsgLimits_t', 'struct_c__SA_OverDriveLimits_t', - 'struct_c__SA_OverDriveTableExternal_t', - 'struct_c__SA_OverDriveTable_t', 'struct_c__SA_PFE_Settings_t', - 'struct_c__SA_PPTable_t', 'struct_c__SA_QuadraticInt_t', - 'struct_c__SA_SMU_Firmware_Header', 'struct_c__SA_SkuTable_t', - 'struct_c__SA_SmuMetricsExternal_t', 'struct_c__SA_SmuMetrics_t', - 'struct_c__SA_Svi3RegulatorSettings_t', - 'struct_c__SA_SviTelemetryScale_t', 'struct_c__SA_SwI2cCmd_t', - 'struct_c__SA_SwI2cRequestExternal_t', - 'struct_c__SA_SwI2cRequest_t', - 'struct_c__SA_WatermarkRowGeneric_t', - 'struct_c__SA_WatermarksExternal_t', 'struct_c__SA_Watermarks_t', - 'struct_smu_bios_boot_up_values', 'struct_smu_clock_info', - 'struct_smu_hw_power_state', 'struct_smu_performance_level', - 'struct_smu_power_state', 'struct_smu_state_classification_block', - 'struct_smu_state_display_block', 'struct_smu_state_memory_block', - 'struct_smu_state_pcie_block', - 'struct_smu_state_software_algorithm_block', - 'struct_smu_state_validation_block', 'struct_smu_table', - 'struct_smu_temperature_range', 'struct_smu_user_dpm_profile', - 'struct_smu_uvd_clocks', 'u32', 'uint16_t', 'uint32_t', - 'uint64_t', 'uint8_t'] +FEATURE_CCLK_DPM_BIT = 0 +FEATURE_FAN_CONTROLLER_BIT = 1 +FEATURE_DATA_CALCULATION_BIT = 2 +FEATURE_PPT_BIT = 3 +FEATURE_TDC_BIT = 4 +FEATURE_THERMAL_BIT = 5 +FEATURE_FIT_BIT = 6 +FEATURE_EDC_BIT = 7 +FEATURE_PLL_POWER_DOWN_BIT = 8 +FEATURE_VDDOFF_BIT = 9 +FEATURE_VCN_DPM_BIT = 10 +FEATURE_DS_MPM_BIT = 11 +FEATURE_FCLK_DPM_BIT = 12 +FEATURE_SOCCLK_DPM_BIT = 13 +FEATURE_DS_MPIO_BIT = 14 +FEATURE_LCLK_DPM_BIT = 15 +FEATURE_SHUBCLK_DPM_BIT = 16 +FEATURE_DCFCLK_DPM_BIT = 17 +FEATURE_ISP_DPM_BIT = 18 +FEATURE_IPU_DPM_BIT = 19 +FEATURE_GFX_DPM_BIT = 20 +FEATURE_DS_GFXCLK_BIT = 21 +FEATURE_DS_SOCCLK_BIT = 22 +FEATURE_DS_LCLK_BIT = 23 +FEATURE_LOW_POWER_DCNCLKS_BIT = 24 +FEATURE_DS_SHUBCLK_BIT = 25 +FEATURE_RESERVED0_BIT = 26 +FEATURE_ZSTATES_BIT = 27 +FEATURE_IOMMUL2_PG_BIT = 28 +FEATURE_DS_FCLK_BIT = 29 +FEATURE_DS_SMNCLK_BIT = 30 +FEATURE_DS_MP1CLK_BIT = 31 +FEATURE_WHISPER_MODE_BIT = 32 +FEATURE_SMU_LOW_POWER_BIT = 33 +FEATURE_RESERVED1_BIT = 34 +FEATURE_GFX_DEM_BIT = 35 +FEATURE_PSI_BIT = 36 +FEATURE_PROCHOT_BIT = 37 +FEATURE_CPUOFF_BIT = 38 +FEATURE_STAPM_BIT = 39 +FEATURE_S0I3_BIT = 40 +FEATURE_DF_LIGHT_CSTATE = 41 +FEATURE_PERF_LIMIT_BIT = 42 +FEATURE_CORE_DLDO_BIT = 43 +FEATURE_DVO_BIT = 44 +FEATURE_DS_VCN_BIT = 45 +FEATURE_CPPC_BIT = 46 +FEATURE_CPPC_PREFERRED_CORES = 47 +FEATURE_DF_CSTATES_BIT = 48 +FEATURE_FAST_PSTATE_CLDO_BIT = 49 +FEATURE_ATHUB_PG_BIT = 50 +FEATURE_VDDOFF_ECO_BIT = 51 +FEATURE_ZSTATES_ECO_BIT = 52 +FEATURE_CC6_BIT = 53 +FEATURE_DS_UMCCLK_BIT = 54 +FEATURE_DS_ISPCLK_BIT = 55 +FEATURE_DS_HSPCLK_BIT = 56 +FEATURE_P3T_BIT = 57 +FEATURE_DS_IPUCLK_BIT = 58 +FEATURE_DS_VPECLK_BIT = 59 +FEATURE_VPE_DPM_BIT = 60 +FEATURE_SMART_L3_RINSER_BIT = 61 +FEATURE_PCC_BIT = 62 +NUM_FEATURES = 63 +PPSMC_VERSION = 0x1 +PPSMC_Result_OK = 0x1 +PPSMC_Result_Failed = 0xFF +PPSMC_Result_UnknownCmd = 0xFE +PPSMC_Result_CmdRejectedPrereq = 0xFD +PPSMC_Result_CmdRejectedBusy = 0xFC +PPSMC_MSG_TestMessage = 0x1 +PPSMC_MSG_GetSmuVersion = 0x2 +PPSMC_MSG_GetDriverIfVersion = 0x3 +PPSMC_MSG_SetAllowedFeaturesMaskLow = 0x4 +PPSMC_MSG_SetAllowedFeaturesMaskHigh = 0x5 +PPSMC_MSG_EnableAllSmuFeatures = 0x6 +PPSMC_MSG_DisableAllSmuFeatures = 0x7 +PPSMC_MSG_EnableSmuFeaturesLow = 0x8 +PPSMC_MSG_EnableSmuFeaturesHigh = 0x9 +PPSMC_MSG_DisableSmuFeaturesLow = 0xA +PPSMC_MSG_DisableSmuFeaturesHigh = 0xB +PPSMC_MSG_GetRunningSmuFeaturesLow = 0xC +PPSMC_MSG_GetRunningSmuFeaturesHigh = 0xD +PPSMC_MSG_SetDriverDramAddrHigh = 0xE +PPSMC_MSG_SetDriverDramAddrLow = 0xF +PPSMC_MSG_SetToolsDramAddrHigh = 0x10 +PPSMC_MSG_SetToolsDramAddrLow = 0x11 +PPSMC_MSG_TransferTableSmu2Dram = 0x12 +PPSMC_MSG_TransferTableDram2Smu = 0x13 +PPSMC_MSG_UseDefaultPPTable = 0x14 +PPSMC_MSG_EnterBaco = 0x15 +PPSMC_MSG_ExitBaco = 0x16 +PPSMC_MSG_ArmD3 = 0x17 +PPSMC_MSG_BacoAudioD3PME = 0x18 +PPSMC_MSG_SetSoftMinByFreq = 0x19 +PPSMC_MSG_SetSoftMaxByFreq = 0x1A +PPSMC_MSG_SetHardMinByFreq = 0x1B +PPSMC_MSG_SetHardMaxByFreq = 0x1C +PPSMC_MSG_GetMinDpmFreq = 0x1D +PPSMC_MSG_GetMaxDpmFreq = 0x1E +PPSMC_MSG_GetDpmFreqByIndex = 0x1F +PPSMC_MSG_OverridePcieParameters = 0x20 +PPSMC_MSG_DramLogSetDramAddrHigh = 0x21 +PPSMC_MSG_DramLogSetDramAddrLow = 0x22 +PPSMC_MSG_DramLogSetDramSize = 0x23 +PPSMC_MSG_SetWorkloadMask = 0x24 +PPSMC_MSG_GetVoltageByDpm = 0x25 +PPSMC_MSG_SetVideoFps = 0x26 +PPSMC_MSG_GetDcModeMaxDpmFreq = 0x27 +PPSMC_MSG_AllowGfxOff = 0x28 +PPSMC_MSG_DisallowGfxOff = 0x29 +PPSMC_MSG_PowerUpVcn = 0x2A +PPSMC_MSG_PowerDownVcn = 0x2B +PPSMC_MSG_PowerUpJpeg = 0x2C +PPSMC_MSG_PowerDownJpeg = 0x2D +PPSMC_MSG_PrepareMp1ForUnload = 0x2E +PPSMC_MSG_SetSystemVirtualDramAddrHigh = 0x30 +PPSMC_MSG_SetSystemVirtualDramAddrLow = 0x31 +PPSMC_MSG_SetPptLimit = 0x32 +PPSMC_MSG_GetPptLimit = 0x33 +PPSMC_MSG_ReenableAcDcInterrupt = 0x34 +PPSMC_MSG_NotifyPowerSource = 0x35 +PPSMC_MSG_RunDcBtc = 0x36 +PPSMC_MSG_SetTemperatureInputSelect = 0x38 +PPSMC_MSG_SetFwDstatesMask = 0x39 +PPSMC_MSG_SetThrottlerMask = 0x3A +PPSMC_MSG_SetExternalClientDfCstateAllow = 0x3B +PPSMC_MSG_SetMGpuFanBoostLimitRpm = 0x3C +PPSMC_MSG_DumpSTBtoDram = 0x3D +PPSMC_MSG_STBtoDramLogSetDramAddress = 0x3E +PPSMC_MSG_DummyUndefined = 0x3F +PPSMC_MSG_STBtoDramLogSetDramSize = 0x40 +PPSMC_MSG_SetOBMTraceBufferLogging = 0x41 +PPSMC_MSG_UseProfilingMode = 0x42 +PPSMC_MSG_AllowGfxDcs = 0x43 +PPSMC_MSG_DisallowGfxDcs = 0x44 +PPSMC_MSG_EnableAudioStutterWA = 0x45 +PPSMC_MSG_PowerUpUmsch = 0x46 +PPSMC_MSG_PowerDownUmsch = 0x47 +PPSMC_MSG_SetDcsArch = 0x48 +PPSMC_MSG_TriggerVFFLR = 0x49 +PPSMC_MSG_SetNumBadMemoryPagesRetired = 0x4A +PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel = 0x4B +PPSMC_MSG_SetPriorityDeltaGain = 0x4C +PPSMC_MSG_AllowIHHostInterrupt = 0x4D +PPSMC_MSG_EnableShadowDpm = 0x4E +PPSMC_MSG_Mode3Reset = 0x4F +PPSMC_MSG_SetDriverDramAddr = 0x50 +PPSMC_MSG_SetToolsDramAddr = 0x51 +PPSMC_MSG_TransferTableSmu2DramWithAddr = 0x52 +PPSMC_MSG_TransferTableDram2SmuWithAddr = 0x53 +PPSMC_MSG_GetAllRunningSmuFeatures = 0x54 +PPSMC_MSG_GetSvi3Voltage = 0x55 +PPSMC_MSG_UpdatePolicy = 0x56 +PPSMC_MSG_ExtPwrConnSupport = 0x57 +PPSMC_MSG_PreloadSwPstateForUclkOverDrive = 0x58 +PPSMC_Message_Count = 0x59 +PPTABLE_VERSION = 0x1B +NUM_GFXCLK_DPM_LEVELS = 16 +NUM_SOCCLK_DPM_LEVELS = 8 +NUM_MP0CLK_DPM_LEVELS = 2 +NUM_DCLK_DPM_LEVELS = 8 +NUM_VCLK_DPM_LEVELS = 8 +NUM_DISPCLK_DPM_LEVELS = 8 +NUM_DPPCLK_DPM_LEVELS = 8 +NUM_DPREFCLK_DPM_LEVELS = 8 +NUM_DCFCLK_DPM_LEVELS = 8 +NUM_DTBCLK_DPM_LEVELS = 8 +NUM_UCLK_DPM_LEVELS = 6 +NUM_LINK_LEVELS = 3 +NUM_FCLK_DPM_LEVELS = 8 +NUM_OD_FAN_MAX_POINTS = 6 +FEATURE_FW_DATA_READ_BIT = 0 +FEATURE_DPM_GFXCLK_BIT = 1 +FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT = 2 +FEATURE_DPM_UCLK_BIT = 3 +FEATURE_DPM_FCLK_BIT = 4 +FEATURE_DPM_SOCCLK_BIT = 5 +FEATURE_DPM_LINK_BIT = 6 +FEATURE_DPM_DCN_BIT = 7 +FEATURE_VMEMP_SCALING_BIT = 8 +FEATURE_VDDIO_MEM_SCALING_BIT = 9 +FEATURE_DS_GFXCLK_BIT = 10 +FEATURE_DS_SOCCLK_BIT = 11 +FEATURE_DS_FCLK_BIT = 12 +FEATURE_DS_LCLK_BIT = 13 +FEATURE_DS_DCFCLK_BIT = 14 +FEATURE_DS_UCLK_BIT = 15 +FEATURE_GFX_ULV_BIT = 16 +FEATURE_FW_DSTATE_BIT = 17 +FEATURE_GFXOFF_BIT = 18 +FEATURE_BACO_BIT = 19 +FEATURE_MM_DPM_BIT = 20 +FEATURE_SOC_MPCLK_DS_BIT = 21 +FEATURE_BACO_MPCLK_DS_BIT = 22 +FEATURE_THROTTLERS_BIT = 23 +FEATURE_SMARTSHIFT_BIT = 24 +FEATURE_GTHR_BIT = 25 +FEATURE_ACDC_BIT = 26 +FEATURE_VR0HOT_BIT = 27 +FEATURE_FW_CTF_BIT = 28 +FEATURE_FAN_CONTROL_BIT = 29 +FEATURE_GFX_DCS_BIT = 30 +FEATURE_GFX_READ_MARGIN_BIT = 31 +FEATURE_LED_DISPLAY_BIT = 32 +FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT = 33 +FEATURE_OUT_OF_BAND_MONITOR_BIT = 34 +FEATURE_OPTIMIZED_VMIN_BIT = 35 +FEATURE_GFX_IMU_BIT = 36 +FEATURE_BOOT_TIME_CAL_BIT = 37 +FEATURE_GFX_PCC_DFLL_BIT = 38 +FEATURE_SOC_CG_BIT = 39 +FEATURE_DF_CSTATE_BIT = 40 +FEATURE_GFX_EDC_BIT = 41 +FEATURE_BOOT_POWER_OPT_BIT = 42 +FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT = 43 +FEATURE_DS_VCN_BIT = 44 +FEATURE_BACO_CG_BIT = 45 +FEATURE_MEM_TEMP_READ_BIT = 46 +FEATURE_ATHUB_MMHUB_PG_BIT = 47 +FEATURE_SOC_PCC_BIT = 48 +FEATURE_EDC_PWRBRK_BIT = 49 +FEATURE_SOC_EDC_XVMIN_BIT = 50 +FEATURE_GFX_PSM_DIDT_BIT = 51 +FEATURE_APT_ALL_ENABLE_BIT = 52 +FEATURE_APT_SQ_THROTTLE_BIT = 53 +FEATURE_APT_PF_DCS_BIT = 54 +FEATURE_GFX_EDC_XVMIN_BIT = 55 +FEATURE_GFX_DIDT_XVMIN_BIT = 56 +FEATURE_FAN_ABNORMAL_BIT = 57 +FEATURE_CLOCK_STRETCH_COMPENSATOR = 58 +FEATURE_SPARE_59_BIT = 59 +FEATURE_SPARE_60_BIT = 60 +FEATURE_SPARE_61_BIT = 61 +FEATURE_SPARE_62_BIT = 62 +FEATURE_SPARE_63_BIT = 63 +NUM_FEATURES = 64 +ALLOWED_FEATURE_CTRL_DEFAULT = 0xFFFFFFFFFFFFFFFF +ALLOWED_FEATURE_CTRL_SCPM = (1 << FEATURE_DPM_GFXCLK_BIT) | (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | (1 << FEATURE_DPM_UCLK_BIT) | (1 << FEATURE_DPM_FCLK_BIT) | (1 << FEATURE_DPM_SOCCLK_BIT) | (1 << FEATURE_DPM_LINK_BIT) | (1 << FEATURE_DPM_DCN_BIT) | (1 << FEATURE_DS_GFXCLK_BIT) | (1 << FEATURE_DS_SOCCLK_BIT) | (1 << FEATURE_DS_FCLK_BIT) | (1 << FEATURE_DS_LCLK_BIT) | (1 << FEATURE_DS_DCFCLK_BIT) | (1 << FEATURE_DS_UCLK_BIT) | (1 << FEATURE_DS_VCN_BIT) +DEBUG_OVERRIDE_NOT_USE = 0x00000001 +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK = 0x00000002 +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK = 0x00000004 +DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK = 0x00000008 +DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER = 0x00000010 +DEBUG_OVERRIDE_DISABLE_VCN_PG = 0x00000020 +DEBUG_OVERRIDE_DISABLE_FMAX_VMAX = 0x00000040 +DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS = 0x00000080 +DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK = 0x00000100 +DEBUG_OVERRIDE_DISABLE_DFLL = 0x00000200 +DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE = 0x00000400 +DEBUG_OVERRIDE_DFLL_MASTER_MODE = 0x00000800 +DEBUG_OVERRIDE_ENABLE_PROFILING_MODE = 0x00001000 +DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE = 0x00002000 +DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY = 0x00004000 +DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING = 0x00008000 +DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG = 0x00010000 +VR_MAPPING_VR_SELECT_MASK = 0x01 +VR_MAPPING_VR_SELECT_SHIFT = 0x00 +VR_MAPPING_PLANE_SELECT_MASK = 0x02 +VR_MAPPING_PLANE_SELECT_SHIFT = 0x01 +PSI_SEL_VR0_PLANE0_PSI0 = 0x01 +PSI_SEL_VR0_PLANE0_PSI1 = 0x02 +PSI_SEL_VR0_PLANE1_PSI0 = 0x04 +PSI_SEL_VR0_PLANE1_PSI1 = 0x08 +PSI_SEL_VR1_PLANE0_PSI0 = 0x10 +PSI_SEL_VR1_PLANE0_PSI1 = 0x20 +PSI_SEL_VR1_PLANE1_PSI0 = 0x40 +PSI_SEL_VR1_PLANE1_PSI1 = 0x80 +THROTTLER_TEMP_EDGE_BIT = 0 +THROTTLER_TEMP_HOTSPOT_BIT = 1 +THROTTLER_TEMP_HOTSPOT_GFX_BIT = 2 +THROTTLER_TEMP_HOTSPOT_SOC_BIT = 3 +THROTTLER_TEMP_MEM_BIT = 4 +THROTTLER_TEMP_VR_GFX_BIT = 5 +THROTTLER_TEMP_VR_SOC_BIT = 6 +THROTTLER_TEMP_VR_MEM0_BIT = 7 +THROTTLER_TEMP_VR_MEM1_BIT = 8 +THROTTLER_TEMP_LIQUID0_BIT = 9 +THROTTLER_TEMP_LIQUID1_BIT = 10 +THROTTLER_TEMP_PLX_BIT = 11 +THROTTLER_TDC_GFX_BIT = 12 +THROTTLER_TDC_SOC_BIT = 13 +THROTTLER_PPT0_BIT = 14 +THROTTLER_PPT1_BIT = 15 +THROTTLER_PPT2_BIT = 16 +THROTTLER_PPT3_BIT = 17 +THROTTLER_FIT_BIT = 18 +THROTTLER_GFX_APCC_PLUS_BIT = 19 +THROTTLER_GFX_DVO_BIT = 20 +THROTTLER_COUNT = 21 +FW_DSTATE_SOC_ULV_BIT = 0 +FW_DSTATE_G6_HSR_BIT = 1 +FW_DSTATE_G6_PHY_VMEMP_OFF_BIT = 2 +FW_DSTATE_SMN_DS_BIT = 3 +FW_DSTATE_MP1_WHISPER_MODE_BIT = 4 +FW_DSTATE_SOC_LIV_MIN_BIT = 5 +FW_DSTATE_SOC_PLL_PWRDN_BIT = 6 +FW_DSTATE_MEM_PLL_PWRDN_BIT = 7 +FW_DSTATE_MALL_ALLOC_BIT = 8 +FW_DSTATE_MEM_PSI_BIT = 9 +FW_DSTATE_HSR_NON_STROBE_BIT = 10 +FW_DSTATE_MP0_ENTER_WFI_BIT = 11 +FW_DSTATE_MALL_FLUSH_BIT = 12 +FW_DSTATE_SOC_PSI_BIT = 13 +FW_DSTATE_MMHUB_INTERLOCK_BIT = 14 +FW_DSTATE_D0i3_2_QUIET_FW_BIT = 15 +FW_DSTATE_CLDO_PRG_BIT = 16 +FW_DSTATE_DF_PLL_PWRDN_BIT = 17 +LED_DISPLAY_GFX_DPM_BIT = 0 +LED_DISPLAY_PCIE_BIT = 1 +LED_DISPLAY_ERROR_BIT = 2 +MEM_TEMP_READ_OUT_OF_BAND_BIT = 0 +MEM_TEMP_READ_IN_BAND_REFRESH_BIT = 1 +MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT = 2 +NUM_I2C_CONTROLLERS = 8 +I2C_CONTROLLER_ENABLED = 1 +I2C_CONTROLLER_DISABLED = 0 +MAX_SW_I2C_COMMANDS = 24 +CMDCONFIG_STOP_BIT = 0 +CMDCONFIG_RESTART_BIT = 1 +CMDCONFIG_READWRITE_BIT = 2 +CMDCONFIG_STOP_MASK = (1 << CMDCONFIG_STOP_BIT) +CMDCONFIG_RESTART_MASK = (1 << CMDCONFIG_RESTART_BIT) +CMDCONFIG_READWRITE_MASK = (1 << CMDCONFIG_READWRITE_BIT) +EPCS_HIGH_POWER = 600 +EPCS_NORMAL_POWER = 450 +EPCS_LOW_POWER = 300 +EPCS_SHORTED_POWER = 150 +EPCS_NO_BOOTUP = 0 +PP_NUM_RTAVFS_PWL_ZONES = 5 +PP_NUM_PSM_DIDT_PWL_ZONES = 3 +PP_NUM_OD_VF_CURVE_POINTS = PP_NUM_RTAVFS_PWL_ZONES + 1 +PP_OD_FEATURE_GFX_VF_CURVE_BIT = 0 +PP_OD_FEATURE_GFX_VMAX_BIT = 1 +PP_OD_FEATURE_SOC_VMAX_BIT = 2 +PP_OD_FEATURE_PPT_BIT = 3 +PP_OD_FEATURE_FAN_CURVE_BIT = 4 +PP_OD_FEATURE_FAN_LEGACY_BIT = 5 +PP_OD_FEATURE_FULL_CTRL_BIT = 6 +PP_OD_FEATURE_TDC_BIT = 7 +PP_OD_FEATURE_GFXCLK_BIT = 8 +PP_OD_FEATURE_UCLK_BIT = 9 +PP_OD_FEATURE_FCLK_BIT = 10 +PP_OD_FEATURE_ZERO_FAN_BIT = 11 +PP_OD_FEATURE_TEMPERATURE_BIT = 12 +PP_OD_FEATURE_EDC_BIT = 13 +PP_OD_FEATURE_COUNT = 14 +INVALID_BOARD_GPIO = 0xFF +NUM_WM_RANGES = 4 +WORKLOAD_PPLIB_DEFAULT_BIT = 0 +WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT = 1 +WORKLOAD_PPLIB_POWER_SAVING_BIT = 2 +WORKLOAD_PPLIB_VIDEO_BIT = 3 +WORKLOAD_PPLIB_VR_BIT = 4 +WORKLOAD_PPLIB_COMPUTE_BIT = 5 +WORKLOAD_PPLIB_CUSTOM_BIT = 6 +WORKLOAD_PPLIB_WINDOW_3D_BIT = 7 +WORKLOAD_PPLIB_DIRECT_ML_BIT = 8 +WORKLOAD_PPLIB_CGVDI_BIT = 9 +WORKLOAD_PPLIB_COUNT = 10 +TABLE_TRANSFER_OK = 0x0 +TABLE_TRANSFER_FAILED = 0xFF +TABLE_TRANSFER_PENDING = 0xAB +TABLE_PPT_FAILED = 0x100 +TABLE_TDC_FAILED = 0x200 +TABLE_TEMP_FAILED = 0x400 +TABLE_FAN_TARGET_TEMP_FAILED = 0x800 +TABLE_FAN_STOP_TEMP_FAILED = 0x1000 +TABLE_FAN_START_TEMP_FAILED = 0x2000 +TABLE_FAN_PWM_MIN_FAILED = 0x4000 +TABLE_ACOUSTIC_TARGET_RPM_FAILED = 0x8000 +TABLE_ACOUSTIC_LIMIT_RPM_FAILED = 0x10000 +TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED = 0x20000 +TABLE_PPTABLE = 0 +TABLE_COMBO_PPTABLE = 1 +TABLE_WATERMARKS = 2 +TABLE_AVFS_PSM_DEBUG = 3 +TABLE_PMSTATUSLOG = 4 +TABLE_SMU_METRICS = 5 +TABLE_DRIVER_SMU_CONFIG = 6 +TABLE_ACTIVITY_MONITOR_COEFF = 7 +TABLE_OVERDRIVE = 8 +TABLE_I2C_COMMANDS = 9 +TABLE_DRIVER_INFO = 10 +TABLE_ECCINFO = 11 +TABLE_CUSTOM_SKUTABLE = 12 +TABLE_COUNT = 13 +IH_INTERRUPT_ID_TO_DRIVER = 0xFE +IH_INTERRUPT_CONTEXT_ID_BACO = 0x2 +IH_INTERRUPT_CONTEXT_ID_AC = 0x3 +IH_INTERRUPT_CONTEXT_ID_DC = 0x4 +IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 = 0x5 +IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 = 0x6 +IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING = 0x7 +IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL = 0x8 +IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY = 0x9 +IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE = 0xA +int32_t = int +SMU_THERMAL_MINIMUM_ALERT_TEMP = 0 +SMU_THERMAL_MAXIMUM_ALERT_TEMP = 255 +SMU_TEMPERATURE_UNITS_PER_CENTIGRADES = 1000 +SMU_FW_NAME_LEN = 0x24 +SMU_DPM_USER_PROFILE_RESTORE = (1 << 0) +SMU_CUSTOM_FAN_SPEED_RPM = (1 << 1) +SMU_CUSTOM_FAN_SPEED_PWM = (1 << 2) +SMU_THROTTLER_PPT0_BIT = 0 +SMU_THROTTLER_PPT1_BIT = 1 +SMU_THROTTLER_PPT2_BIT = 2 +SMU_THROTTLER_PPT3_BIT = 3 +SMU_THROTTLER_SPL_BIT = 4 +SMU_THROTTLER_FPPT_BIT = 5 +SMU_THROTTLER_SPPT_BIT = 6 +SMU_THROTTLER_SPPT_APU_BIT = 7 +SMU_THROTTLER_TDC_GFX_BIT = 16 +SMU_THROTTLER_TDC_SOC_BIT = 17 +SMU_THROTTLER_TDC_MEM_BIT = 18 +SMU_THROTTLER_TDC_VDD_BIT = 19 +SMU_THROTTLER_TDC_CVIP_BIT = 20 +SMU_THROTTLER_EDC_CPU_BIT = 21 +SMU_THROTTLER_EDC_GFX_BIT = 22 +SMU_THROTTLER_APCC_BIT = 23 +SMU_THROTTLER_TEMP_GPU_BIT = 32 +SMU_THROTTLER_TEMP_CORE_BIT = 33 +SMU_THROTTLER_TEMP_MEM_BIT = 34 +SMU_THROTTLER_TEMP_EDGE_BIT = 35 +SMU_THROTTLER_TEMP_HOTSPOT_BIT = 36 +SMU_THROTTLER_TEMP_SOC_BIT = 37 +SMU_THROTTLER_TEMP_VR_GFX_BIT = 38 +SMU_THROTTLER_TEMP_VR_SOC_BIT = 39 +SMU_THROTTLER_TEMP_VR_MEM0_BIT = 40 +SMU_THROTTLER_TEMP_VR_MEM1_BIT = 41 +SMU_THROTTLER_TEMP_LIQUID0_BIT = 42 +SMU_THROTTLER_TEMP_LIQUID1_BIT = 43 +SMU_THROTTLER_VRHOT0_BIT = 44 +SMU_THROTTLER_VRHOT1_BIT = 45 +SMU_THROTTLER_PROCHOT_CPU_BIT = 46 +SMU_THROTTLER_PROCHOT_GFX_BIT = 47 +SMU_THROTTLER_PPM_BIT = 56 +SMU_THROTTLER_FIT_BIT = 57 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/amd_gpu.py b/tinygrad/runtime/autogen/amd_gpu.py index 03812d8c16..003cba8258 100644 --- a/tinygrad/runtime/autogen/amd_gpu.py +++ b/tinygrad/runtime/autogen/amd_gpu.py @@ -1,22117 +1,13127 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # Variable ctypes.c_uint32 -SDMA_OP_FENCE = 5 # Variable ctypes.c_uint32 -SDMA_OP_TRAP = 6 # Variable ctypes.c_uint32 -SDMA_OP_POLL_REGMEM = 8 # Variable ctypes.c_uint32 -SDMA_OP_ATOMIC = 10 # Variable ctypes.c_uint32 -SDMA_OP_CONST_FILL = 11 # Variable ctypes.c_uint32 -SDMA_OP_TIMESTAMP = 13 # Variable ctypes.c_uint32 -SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # Variable ctypes.c_uint32 -SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 -SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 -class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('extra_info', ctypes.c_uint32, 16), +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('extra_info', ctypes.c_uint32,16), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_1_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_2_0._fields_ = [ - ('reserved_0', ctypes.c_uint32, 16), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_1', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0._fields_ = [ + ('reserved_0', ctypes.c_uint32,16), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_1', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_3_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_4_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_5_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG_6_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_COPY_LINEAR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), - ('COUNT_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), - ('PARAMETER_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), +rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION), + ('PARAMETER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION), ] - -SDMA_PKT_COPY_LINEAR = struct_SDMA_PKT_COPY_LINEAR_TAG -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG(Structure): - pass - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved', ctypes.c_uint32, 13), - ('element', ctypes.c_uint32, 3), +rocr_AMD_SDMA_PKT_COPY_LINEAR = rocr_AMD_SDMA_PKT_COPY_LINEAR_TAG +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved', ctypes.c_uint32,13), + ('element', ctypes.c_uint32,3), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0._fields_ = [ - ('src_addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0._fields_ = [ + ('src_addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0._fields_ = [ - ('src_addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0._fields_ = [ + ('src_addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0._fields_ = [ - ('src_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('src_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0._fields_ = [ + ('src_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('src_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0._fields_ = [ - ('src_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('src_pitch', ctypes.c_uint32, 19), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0._fields_ = [ + ('src_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('src_pitch', ctypes.c_uint32,19), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0._fields_ = [ - ('src_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0._fields_ = [ + ('src_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0._fields_ = [ - ('dst_offset_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_offset_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0._fields_ = [ + ('dst_offset_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('dst_offset_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0), - ('DW_8_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION_0), + ('DW_8_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0._fields_ = [ - ('dst_offset_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 2), - ('dst_pitch', ctypes.c_uint32, 19), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0._fields_ = [ + ('dst_offset_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,2), + ('dst_pitch', ctypes.c_uint32,19), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0), - ('DW_9_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION_0), + ('DW_9_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0._fields_ = [ - ('dst_slice_pitch', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0._fields_ = [ + ('dst_slice_pitch', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0), - ('DW_10_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION_0), + ('DW_10_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0._fields_ = [ - ('rect_x', ctypes.c_uint32, 14), - ('reserved_1', ctypes.c_uint32, 2), - ('rect_y', ctypes.c_uint32, 14), - ('reserved_2', ctypes.c_uint32, 2), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0._fields_ = [ + ('rect_x', ctypes.c_uint32,14), + ('reserved_1', ctypes.c_uint32,2), + ('rect_y', ctypes.c_uint32,14), + ('reserved_2', ctypes.c_uint32,2), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0), - ('DW_11_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION_0), + ('DW_11_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(Union): - pass - -class struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0(Structure): - pass - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0._fields_ = [ - ('rect_z', ctypes.c_uint32, 11), - ('reserved_1', ctypes.c_uint32, 5), - ('dst_swap', ctypes.c_uint32, 2), - ('reserved_2', ctypes.c_uint32, 6), - ('src_swap', ctypes.c_uint32, 2), - ('reserved_3', ctypes.c_uint32, 6), +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0._fields_ = [ + ('rect_z', ctypes.c_uint32,11), + ('reserved_1', ctypes.c_uint32,5), + ('dst_swap', ctypes.c_uint32,2), + ('reserved_2', ctypes.c_uint32,6), + ('src_swap', ctypes.c_uint32,2), + ('reserved_3', ctypes.c_uint32,6), ] - -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0), - ('DW_12_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION_0), + ('DW_12_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), - ('SRC_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), - ('SRC_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), - ('SRC_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), - ('SRC_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), - ('SRC_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), - ('DST_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), - ('DST_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), - ('DST_PARAMETER_3_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), - ('RECT_PARAMETER_1_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), - ('RECT_PARAMETER_2_UNION', union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION), + ('SRC_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION), + ('SRC_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION), + ('SRC_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION), + ('SRC_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION), + ('SRC_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION), + ('DST_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION), + ('DST_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION), + ('DST_PARAMETER_3_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION), + ('RECT_PARAMETER_1_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION), + ('RECT_PARAMETER_2_UNION', rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION), ] - -SDMA_PKT_COPY_LINEAR_RECT = struct_SDMA_PKT_COPY_LINEAR_RECT_TAG -class struct_SDMA_PKT_CONSTANT_FILL_TAG(Structure): - pass - -class union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('sw', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 12), - ('fillsize', ctypes.c_uint32, 2), +rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT = rocr_AMD_SDMA_PKT_COPY_LINEAR_RECT_TAG +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('sw', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,12), + ('fillsize', ctypes.c_uint32,2), ] - -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0._fields_ = [ - ('dst_addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0._fields_ = [ + ('dst_addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0._fields_ = [ - ('dst_addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0._fields_ = [ + ('dst_addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(Union): - pass - -class struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0._fields_ = [ - ('count', ctypes.c_uint32, 22), - ('reserved_0', ctypes.c_uint32, 10), +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0._fields_ = [ + ('count', ctypes.c_uint32,22), + ('reserved_0', ctypes.c_uint32,10), ] - -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_CONSTANT_FILL_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), - ('DST_ADDR_LO_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), - ('DST_ADDR_HI_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), - ('COUNT_UNION', union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), +rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION), + ('DST_ADDR_LO_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION), + ('DST_ADDR_HI_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION), + ('COUNT_UNION', rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION), ] - -SDMA_PKT_CONSTANT_FILL = struct_SDMA_PKT_CONSTANT_FILL_TAG -class struct_SDMA_PKT_FENCE_TAG(Structure): - pass - -class union_SDMA_PKT_FENCE_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('mtype', ctypes.c_uint32, 3), - ('gcc', ctypes.c_uint32, 1), - ('sys', ctypes.c_uint32, 1), - ('pad1', ctypes.c_uint32, 1), - ('snp', ctypes.c_uint32, 1), - ('gpa', ctypes.c_uint32, 1), - ('l2_policy', ctypes.c_uint32, 2), - ('reserved_0', ctypes.c_uint32, 6), +rocr_AMD_SDMA_PKT_CONSTANT_FILL = rocr_AMD_SDMA_PKT_CONSTANT_FILL_TAG +class rocr_AMD_SDMA_PKT_FENCE_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('mtype', ctypes.c_uint32,3), + ('gcc', ctypes.c_uint32,1), + ('sys', ctypes.c_uint32,1), + ('pad1', ctypes.c_uint32,1), + ('snp', ctypes.c_uint32,1), + ('gpa', ctypes.c_uint32,1), + ('l2_policy', ctypes.c_uint32,2), + ('reserved_0', ctypes.c_uint32,6), ] - -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_FENCE_TAG_DATA_UNION(Union): - pass - -class struct_SDMA_PKT_FENCE_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_FENCE_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG_3_0._fields_ = [ - ('data', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0._fields_ = [ + ('data', ctypes.c_uint32,32), ] - -union_SDMA_PKT_FENCE_TAG_DATA_UNION._pack_ = 1 # source:False -union_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_FENCE_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_FENCE_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_FENCE_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_FENCE_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), - ('DATA_UNION', union_SDMA_PKT_FENCE_TAG_DATA_UNION), +rocr_AMD_SDMA_PKT_FENCE_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION), + ('DATA_UNION', rocr_AMD_SDMA_PKT_FENCE_TAG_DATA_UNION), ] - -SDMA_PKT_FENCE = struct_SDMA_PKT_FENCE_TAG -class struct_SDMA_PKT_POLL_REGMEM_TAG(Structure): - pass - -class union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 10), - ('hdp_flush', ctypes.c_uint32, 1), - ('reserved_1', ctypes.c_uint32, 1), - ('func', ctypes.c_uint32, 3), - ('mem_poll', ctypes.c_uint32, 1), +rocr_AMD_SDMA_PKT_FENCE = rocr_AMD_SDMA_PKT_FENCE_TAG +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,10), + ('hdp_flush', ctypes.c_uint32,1), + ('reserved_1', ctypes.c_uint32,1), + ('func', ctypes.c_uint32,3), + ('mem_poll', ctypes.c_uint32,1), ] - -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_3_0._fields_ = [ - ('value', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0._fields_ = [ + ('value', ctypes.c_uint32,32), ] - -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_4_0._fields_ = [ - ('mask', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0._fields_ = [ + ('mask', ctypes.c_uint32,32), ] - -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(Union): - pass - -class struct_SDMA_PKT_POLL_REGMEM_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG_5_0._fields_ = [ - ('interval', ctypes.c_uint32, 16), - ('retry_count', ctypes.c_uint32, 12), - ('reserved_0', ctypes.c_uint32, 4), +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0._fields_ = [ + ('interval', ctypes.c_uint32,16), + ('retry_count', ctypes.c_uint32,12), + ('reserved_0', ctypes.c_uint32,4), ] - -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._pack_ = 1 # source:False -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_POLL_REGMEM_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_POLL_REGMEM_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), - ('VALUE_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), - ('MASK_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), - ('DW5_UNION', union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), +rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION), + ('VALUE_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION), + ('MASK_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION), + ('DW5_UNION', rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION), ] - -SDMA_PKT_POLL_REGMEM = struct_SDMA_PKT_POLL_REGMEM_TAG -class struct_SDMA_PKT_ATOMIC_TAG(Structure): - pass - -class union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('l', ctypes.c_uint32, 1), - ('reserved_0', ctypes.c_uint32, 8), - ('operation', ctypes.c_uint32, 7), +rocr_AMD_SDMA_PKT_POLL_REGMEM = rocr_AMD_SDMA_PKT_POLL_REGMEM_TAG +class rocr_AMD_SDMA_PKT_ATOMIC_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('l', ctypes.c_uint32,1), + ('reserved_0', ctypes.c_uint32,8), + ('operation', ctypes.c_uint32,7), ] - -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_3_0._fields_ = [ - ('src_data_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0._fields_ = [ + ('src_data_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_4_0._fields_ = [ - ('src_data_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0._fields_ = [ + ('src_data_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_5_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_5_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_5_0._fields_ = [ - ('cmp_data_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0._fields_ = [ + ('cmp_data_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_5_0), - ('DW_5_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION_0), + ('DW_5_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_6_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_6_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_6_0._fields_ = [ - ('cmp_data_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0._fields_ = [ + ('cmp_data_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_6_0), - ('DW_6_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION_0), + ('DW_6_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(Union): - pass - -class struct_SDMA_PKT_ATOMIC_TAG_7_0(Structure): - pass - -struct_SDMA_PKT_ATOMIC_TAG_7_0._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG_7_0._fields_ = [ - ('loop_interval', ctypes.c_uint32, 13), - ('reserved_0', ctypes.c_uint32, 19), +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0._fields_ = [ + ('loop_interval', ctypes.c_uint32,13), + ('reserved_0', ctypes.c_uint32,19), ] - -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._pack_ = 1 # source:False -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_ATOMIC_TAG_7_0), - ('DW_7_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION_0), + ('DW_7_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_ATOMIC_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_ATOMIC_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), - ('SRC_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), - ('SRC_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), - ('CMP_DATA_LO_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), - ('CMP_DATA_HI_UNION', union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), - ('LOOP_UNION', union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), +rocr_AMD_SDMA_PKT_ATOMIC_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION), + ('SRC_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION), + ('SRC_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION), + ('CMP_DATA_LO_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION), + ('CMP_DATA_HI_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION), + ('LOOP_UNION', rocr_AMD_SDMA_PKT_ATOMIC_TAG_LOOP_UNION), ] - -SDMA_PKT_ATOMIC = struct_SDMA_PKT_ATOMIC_TAG -class struct_SDMA_PKT_TIMESTAMP_TAG(Structure): - pass - -class union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), +rocr_AMD_SDMA_PKT_ATOMIC = rocr_AMD_SDMA_PKT_ATOMIC_TAG +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), ] - -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_1_0._fields_ = [ - ('addr_31_0', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0._fields_ = [ + ('addr_31_0', ctypes.c_uint32,32), ] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(Union): - pass - -class struct_SDMA_PKT_TIMESTAMP_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG_2_0._fields_ = [ - ('addr_63_32', ctypes.c_uint32, 32), +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0._fields_ = [ + ('addr_63_32', ctypes.c_uint32,32), ] - -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TIMESTAMP_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_TIMESTAMP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), - ('ADDR_LO_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), - ('ADDR_HI_UNION', union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), +rocr_AMD_SDMA_PKT_TIMESTAMP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION), + ('ADDR_LO_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION), + ('ADDR_HI_UNION', rocr_AMD_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION), ] - -SDMA_PKT_TIMESTAMP = struct_SDMA_PKT_TIMESTAMP_TAG -class struct_SDMA_PKT_TRAP_TAG(Structure): - pass - -class union_SDMA_PKT_TRAP_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('reserved_0', ctypes.c_uint32, 16), +rocr_AMD_SDMA_PKT_TIMESTAMP = rocr_AMD_SDMA_PKT_TIMESTAMP_TAG +class rocr_AMD_SDMA_PKT_TRAP_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('reserved_0', ctypes.c_uint32,16), ] - -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(Union): - pass - -class struct_SDMA_PKT_TRAP_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_TRAP_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG_1_0._fields_ = [ - ('int_ctx', ctypes.c_uint32, 28), - ('reserved_1', ctypes.c_uint32, 4), +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0._fields_ = [ + ('int_ctx', ctypes.c_uint32,28), + ('reserved_1', ctypes.c_uint32,4), ] - -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._pack_ = 1 # source:False -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_TRAP_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_TRAP_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_TRAP_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_TRAP_TAG_HEADER_UNION), - ('INT_CONTEXT_UNION', union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), +rocr_AMD_SDMA_PKT_TRAP_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_HEADER_UNION), + ('INT_CONTEXT_UNION', rocr_AMD_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION), ] - -SDMA_PKT_TRAP = struct_SDMA_PKT_TRAP_TAG -class struct_SDMA_PKT_HDP_FLUSH_TAG(Structure): - pass - -struct_SDMA_PKT_HDP_FLUSH_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ - ('DW_0_DATA', ctypes.c_uint32), - ('DW_1_DATA', ctypes.c_uint32), - ('DW_2_DATA', ctypes.c_uint32), - ('DW_3_DATA', ctypes.c_uint32), - ('DW_4_DATA', ctypes.c_uint32), - ('DW_5_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_TRAP = rocr_AMD_SDMA_PKT_TRAP_TAG +class rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG(Struct): pass +rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG._fields_ = [ + ('DW_0_DATA', ctypes.c_uint32), + ('DW_1_DATA', ctypes.c_uint32), + ('DW_2_DATA', ctypes.c_uint32), + ('DW_3_DATA', ctypes.c_uint32), + ('DW_4_DATA', ctypes.c_uint32), + ('DW_5_DATA', ctypes.c_uint32), ] - -SDMA_PKT_HDP_FLUSH = struct_SDMA_PKT_HDP_FLUSH_TAG -hdp_flush_cmd = struct_SDMA_PKT_HDP_FLUSH_TAG # Variable struct_SDMA_PKT_HDP_FLUSH_TAG -class struct_SDMA_PKT_GCR_TAG(Structure): - pass - -class union_SDMA_PKT_GCR_TAG_HEADER_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_0_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_0_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_0_0._fields_ = [ - ('op', ctypes.c_uint32, 8), - ('sub_op', ctypes.c_uint32, 8), - ('_2', ctypes.c_uint32, 16), +rocr_AMD_SDMA_PKT_HDP_FLUSH = rocr_AMD_SDMA_PKT_HDP_FLUSH_TAG +class rocr_AMD_SDMA_PKT_GCR_TAG(Struct): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0._fields_ = [ + ('op', ctypes.c_uint32,8), + ('sub_op', ctypes.c_uint32,8), + ('', ctypes.c_uint32,16), ] - -union_SDMA_PKT_GCR_TAG_HEADER_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_0_0), - ('DW_0_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION_0), + ('DW_0_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_GCR_TAG_WORD1_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_1_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_1_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_1_0._fields_ = [ - ('_0', ctypes.c_uint32, 7), - ('BaseVA_LO', ctypes.c_uint32, 25), +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0._fields_ = [ + ('', ctypes.c_uint32,7), + ('BaseVA_LO', ctypes.c_uint32,25), ] - -union_SDMA_PKT_GCR_TAG_WORD1_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_1_0), - ('DW_1_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION_0), + ('DW_1_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_GCR_TAG_WORD2_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_2_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_2_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_2_0._fields_ = [ - ('BaseVA_HI', ctypes.c_uint32, 16), - ('GCR_CONTROL_GLI_INV', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GLM_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLM_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_WB', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLK_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GLV_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL1_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_US', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32, 2), - ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_INV', ctypes.c_uint32, 1), - ('GCR_CONTROL_GL2_WB', ctypes.c_uint32, 1), +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0._fields_ = [ + ('BaseVA_HI', ctypes.c_uint32,16), + ('GCR_CONTROL_GLI_INV', ctypes.c_uint32,2), + ('GCR_CONTROL_GL1_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GLM_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLM_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_WB', ctypes.c_uint32,1), + ('GCR_CONTROL_GLK_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GLV_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL1_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_US', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_RANGE', ctypes.c_uint32,2), + ('GCR_CONTROL_GL2_DISCARD', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_INV', ctypes.c_uint32,1), + ('GCR_CONTROL_GL2_WB', ctypes.c_uint32,1), ] - -union_SDMA_PKT_GCR_TAG_WORD2_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_2_0), - ('DW_2_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION_0), + ('DW_2_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_GCR_TAG_WORD3_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_3_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_3_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_3_0._fields_ = [ - ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32, 1), - ('GCR_CONTROL_SEQ', ctypes.c_uint32, 2), - ('_2', ctypes.c_uint32, 4), - ('LimitVA_LO', ctypes.c_uint32, 25), +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0._fields_ = [ + ('GCR_CONTROL_RANGE_IS_PA', ctypes.c_uint32,1), + ('GCR_CONTROL_SEQ', ctypes.c_uint32,2), + ('', ctypes.c_uint32,4), + ('LimitVA_LO', ctypes.c_uint32,25), ] - -union_SDMA_PKT_GCR_TAG_WORD3_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_3_0), - ('DW_3_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION_0), + ('DW_3_DATA', ctypes.c_uint32), ] - -class union_SDMA_PKT_GCR_TAG_WORD4_UNION(Union): - pass - -class struct_SDMA_PKT_GCR_TAG_4_0(Structure): - pass - -struct_SDMA_PKT_GCR_TAG_4_0._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG_4_0._fields_ = [ - ('LimitVA_HI', ctypes.c_uint32, 16), - ('_1', ctypes.c_uint32, 8), - ('VMID', ctypes.c_uint32, 4), - ('_3', ctypes.c_uint32, 4), +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION(ctypes.Union): pass +class rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0(Struct): pass +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0._fields_ = [ + ('LimitVA_HI', ctypes.c_uint32,16), + ('', ctypes.c_uint32,8), + ('VMID', ctypes.c_uint32,4), + ('', ctypes.c_uint32,4), ] - -union_SDMA_PKT_GCR_TAG_WORD4_UNION._pack_ = 1 # source:False -union_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ('_0',) -union_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ - ('_0', struct_SDMA_PKT_GCR_TAG_4_0), - ('DW_4_DATA', ctypes.c_uint32), +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._anonymous_ = ['_0'] +rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION._fields_ = [ + ('_0', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION_0), + ('DW_4_DATA', ctypes.c_uint32), ] - -struct_SDMA_PKT_GCR_TAG._pack_ = 1 # source:False -struct_SDMA_PKT_GCR_TAG._fields_ = [ - ('HEADER_UNION', union_SDMA_PKT_GCR_TAG_HEADER_UNION), - ('WORD1_UNION', union_SDMA_PKT_GCR_TAG_WORD1_UNION), - ('WORD2_UNION', union_SDMA_PKT_GCR_TAG_WORD2_UNION), - ('WORD3_UNION', union_SDMA_PKT_GCR_TAG_WORD3_UNION), - ('WORD4_UNION', union_SDMA_PKT_GCR_TAG_WORD4_UNION), +rocr_AMD_SDMA_PKT_GCR_TAG._fields_ = [ + ('HEADER_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_HEADER_UNION), + ('WORD1_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD1_UNION), + ('WORD2_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD2_UNION), + ('WORD3_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD3_UNION), + ('WORD4_UNION', rocr_AMD_SDMA_PKT_GCR_TAG_WORD4_UNION), ] - -SDMA_PKT_GCR = struct_SDMA_PKT_GCR_TAG -NVD_H = True # macro -PACKET_TYPE0 = 0 # macro -PACKET_TYPE1 = 1 # macro -PACKET_TYPE2 = 2 # macro -PACKET_TYPE3 = 3 # macro -def CP_PACKET_GET_TYPE(h): # macro - return (((h)>>30)&3) -def CP_PACKET_GET_COUNT(h): # macro - return (((h)>>16)&0x3FFF) -def CP_PACKET0_GET_REG(h): # macro - return ((h)&0xFFFF) -def CP_PACKET3_GET_OPCODE(h): # macro - return (((h)>>8)&0xFF) -def PACKET0(reg, n): # macro - return ((0<<30)|((reg)&0xFFFF)|((n)&0x3FFF)<<16) -CP_PACKET2 = 0x80000000 # macro -PACKET2_PAD_SHIFT = 0 # macro -PACKET2_PAD_MASK = (0x3fffffff<<0) # macro -# def PACKET2(v): # macro -# return (0x80000000|REG_SET(PACKET2_PAD,(v))) -def PACKET3(op, n): # macro - return ((3<<30)|(((op)&0xFF)<<8)|((n)&0x3FFF)<<16) -def PACKET3_COMPUTE(op, n): # macro - return (PACKET3(op,n)|1<<1) -PACKET3_NOP = 0x10 # macro -PACKET3_SET_BASE = 0x11 # macro -def PACKET3_BASE_INDEX(x): # macro - return ((x)<<0) -CE_PARTITION_BASE = 3 # macro -PACKET3_CLEAR_STATE = 0x12 # macro -PACKET3_INDEX_BUFFER_SIZE = 0x13 # macro -PACKET3_DISPATCH_DIRECT = 0x15 # macro -PACKET3_DISPATCH_INDIRECT = 0x16 # macro -PACKET3_INDIRECT_BUFFER_END = 0x17 # macro -PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 # macro -PACKET3_ATOMIC_GDS = 0x1D # macro -PACKET3_ATOMIC_MEM = 0x1E # macro -PACKET3_OCCLUSION_QUERY = 0x1F # macro -PACKET3_SET_PREDICATION = 0x20 # macro -PACKET3_REG_RMW = 0x21 # macro -PACKET3_COND_EXEC = 0x22 # macro -PACKET3_PRED_EXEC = 0x23 # macro -PACKET3_DRAW_INDIRECT = 0x24 # macro -PACKET3_DRAW_INDEX_INDIRECT = 0x25 # macro -PACKET3_INDEX_BASE = 0x26 # macro -PACKET3_DRAW_INDEX_2 = 0x27 # macro -PACKET3_CONTEXT_CONTROL = 0x28 # macro -PACKET3_INDEX_TYPE = 0x2A # macro -PACKET3_DRAW_INDIRECT_MULTI = 0x2C # macro -PACKET3_DRAW_INDEX_AUTO = 0x2D # macro -PACKET3_NUM_INSTANCES = 0x2F # macro -PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 # macro -PACKET3_INDIRECT_BUFFER_PRIV = 0x32 # macro -PACKET3_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 # macro -PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 # macro -PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 # macro -PACKET3_DRAW_PREAMBLE = 0x36 # macro -PACKET3_WRITE_DATA = 0x37 # macro -def WRITE_DATA_DST_SEL(x): # macro - return ((x)<<8) -WR_ONE_ADDR = (1<<16) # macro -WR_CONFIRM = (1<<20) # macro -def WRITE_DATA_CACHE_POLICY(x): # macro - return ((x)<<25) -def WRITE_DATA_ENGINE_SEL(x): # macro - return ((x)<<30) -PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 # macro -PACKET3_MEM_SEMAPHORE = 0x39 # macro -PACKET3_SEM_USE_MAILBOX = (0x1<<16) # macro -PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1<<20) # macro -PACKET3_SEM_SEL_SIGNAL = (0x6<<29) # macro -PACKET3_SEM_SEL_WAIT = (0x7<<29) # macro -PACKET3_DRAW_INDEX_MULTI_INST = 0x3A # macro -PACKET3_COPY_DW = 0x3B # macro -PACKET3_WAIT_REG_MEM = 0x3C # macro -def WAIT_REG_MEM_FUNCTION(x): # macro - return ((x)<<0) -def WAIT_REG_MEM_MEM_SPACE(x): # macro - return ((x)<<4) -def WAIT_REG_MEM_OPERATION(x): # macro - return ((x)<<6) -def WAIT_REG_MEM_ENGINE(x): # macro - return ((x)<<8) -PACKET3_INDIRECT_BUFFER = 0x3F # macro -INDIRECT_BUFFER_VALID = (1<<23) # macro -def INDIRECT_BUFFER_CACHE_POLICY(x): # macro - return ((x)<<28) -def INDIRECT_BUFFER_PRE_ENB(x): # macro - return ((x)<<21) -def INDIRECT_BUFFER_PRE_RESUME(x): # macro - return ((x)<<30) -PACKET3_COND_INDIRECT_BUFFER = 0x3F # macro -PACKET3_COPY_DATA = 0x40 # macro -PACKET3_CP_DMA = 0x41 # macro -PACKET3_PFP_SYNC_ME = 0x42 # macro -PACKET3_SURFACE_SYNC = 0x43 # macro -PACKET3_ME_INITIALIZE = 0x44 # macro -PACKET3_COND_WRITE = 0x45 # macro -PACKET3_EVENT_WRITE = 0x46 # macro -def EVENT_TYPE(x): # macro - return ((x)<<0) -def EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_EVENT_WRITE_EOP = 0x47 # macro -PACKET3_EVENT_WRITE_EOS = 0x48 # macro -PACKET3_RELEASE_MEM = 0x49 # macro -def PACKET3_RELEASE_MEM_EVENT_TYPE(x): # macro - return ((x)<<0) -def PACKET3_RELEASE_MEM_EVENT_INDEX(x): # macro - return ((x)<<8) -PACKET3_RELEASE_MEM_GCR_GLM_WB = (1<<12) # macro -PACKET3_RELEASE_MEM_GCR_GLM_INV = (1<<13) # macro -PACKET3_RELEASE_MEM_GCR_GLV_INV = (1<<14) # macro -PACKET3_RELEASE_MEM_GCR_GL1_INV = (1<<15) # macro -PACKET3_RELEASE_MEM_GCR_GL2_US = (1<<16) # macro -PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1<<17) # macro -PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1<<19) # macro -PACKET3_RELEASE_MEM_GCR_GL2_INV = (1<<20) # macro -PACKET3_RELEASE_MEM_GCR_GL2_WB = (1<<21) # macro -PACKET3_RELEASE_MEM_GCR_SEQ = (1<<22) # macro -def PACKET3_RELEASE_MEM_CACHE_POLICY(x): # macro - return ((x)<<25) -PACKET3_RELEASE_MEM_EXECUTE = (1<<28) # macro -def PACKET3_RELEASE_MEM_DATA_SEL(x): # macro - return ((x)<<29) -def PACKET3_RELEASE_MEM_INT_SEL(x): # macro - return ((x)<<24) -def PACKET3_RELEASE_MEM_DST_SEL(x): # macro - return ((x)<<16) -PACKET3_PREAMBLE_CNTL = 0x4A # macro -PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2<<28) # macro -PACKET3_PREAMBLE_END_CLEAR_STATE = (3<<28) # macro -PACKET3_DMA_DATA = 0x50 # macro -def PACKET3_DMA_DATA_ENGINE(x): # macro - return ((x)<<0) -def PACKET3_DMA_DATA_SRC_CACHE_POLICY(x): # macro - return ((x)<<13) -def PACKET3_DMA_DATA_DST_SEL(x): # macro - return ((x)<<20) -def PACKET3_DMA_DATA_DST_CACHE_POLICY(x): # macro - return ((x)<<25) -def PACKET3_DMA_DATA_SRC_SEL(x): # macro - return ((x)<<29) -PACKET3_DMA_DATA_CP_SYNC = (1<<31) # macro -PACKET3_DMA_DATA_CMD_SAS = (1<<26) # macro -PACKET3_DMA_DATA_CMD_DAS = (1<<27) # macro -PACKET3_DMA_DATA_CMD_SAIC = (1<<28) # macro -PACKET3_DMA_DATA_CMD_DAIC = (1<<29) # macro -PACKET3_DMA_DATA_CMD_RAW_WAIT = (1<<30) # macro -PACKET3_CONTEXT_REG_RMW = 0x51 # macro -PACKET3_GFX_CNTX_UPDATE = 0x52 # macro -PACKET3_BLK_CNTX_UPDATE = 0x53 # macro -PACKET3_INCR_UPDT_STATE = 0x55 # macro -PACKET3_ACQUIRE_MEM = 0x58 # macro -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x): # macro - return ((x)<<0) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x): # macro - return ((x)<<2) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x): # macro - return ((x)<<4) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x): # macro - return ((x)<<5) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x): # macro - return ((x)<<6) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x): # macro - return ((x)<<7) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x): # macro - return ((x)<<8) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x): # macro - return ((x)<<9) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x): # macro - return ((x)<<10) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x): # macro - return ((x)<<11) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x): # macro - return ((x)<<13) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x): # macro - return ((x)<<14) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x): # macro - return ((x)<<15) -def PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x): # macro - return ((x)<<16) -PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1<<18) # macro -PACKET3_REWIND = 0x59 # macro -PACKET3_INTERRUPT = 0x5A # macro -PACKET3_GEN_PDEPTE = 0x5B # macro -PACKET3_INDIRECT_BUFFER_PASID = 0x5C # macro -PACKET3_PRIME_UTCL2 = 0x5D # macro -PACKET3_LOAD_UCONFIG_REG = 0x5E # macro -PACKET3_LOAD_SH_REG = 0x5F # macro -PACKET3_LOAD_CONFIG_REG = 0x60 # macro -PACKET3_LOAD_CONTEXT_REG = 0x61 # macro -PACKET3_LOAD_COMPUTE_STATE = 0x62 # macro -PACKET3_LOAD_SH_REG_INDEX = 0x63 # macro -PACKET3_SET_CONFIG_REG = 0x68 # macro -PACKET3_SET_CONFIG_REG_START = 0x00002000 # macro -PACKET3_SET_CONFIG_REG_END = 0x00002c00 # macro -PACKET3_SET_CONTEXT_REG = 0x69 # macro -PACKET3_SET_CONTEXT_REG_START = 0x0000a000 # macro -PACKET3_SET_CONTEXT_REG_END = 0x0000a400 # macro -PACKET3_SET_CONTEXT_REG_INDEX = 0x6A # macro -PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 # macro -PACKET3_SET_SH_REG_DI = 0x72 # macro -PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 # macro -PACKET3_SET_SH_REG_DI_MULTI = 0x74 # macro -PACKET3_GFX_PIPE_LOCK = 0x75 # macro -PACKET3_SET_SH_REG = 0x76 # macro -PACKET3_SET_SH_REG_START = 0x00002c00 # macro -PACKET3_SET_SH_REG_END = 0x00003000 # macro -PACKET3_SET_SH_REG_OFFSET = 0x77 # macro -PACKET3_SET_QUEUE_REG = 0x78 # macro -PACKET3_SET_UCONFIG_REG = 0x79 # macro -PACKET3_SET_UCONFIG_REG_START = 0x0000c000 # macro -PACKET3_SET_UCONFIG_REG_END = 0x0000c400 # macro -PACKET3_SET_UCONFIG_REG_INDEX = 0x7A # macro -PACKET3_FORWARD_HEADER = 0x7C # macro -PACKET3_SCRATCH_RAM_WRITE = 0x7D # macro -PACKET3_SCRATCH_RAM_READ = 0x7E # macro -PACKET3_LOAD_CONST_RAM = 0x80 # macro -PACKET3_WRITE_CONST_RAM = 0x81 # macro -PACKET3_DUMP_CONST_RAM = 0x83 # macro -PACKET3_INCREMENT_CE_COUNTER = 0x84 # macro -PACKET3_INCREMENT_DE_COUNTER = 0x85 # macro -PACKET3_WAIT_ON_CE_COUNTER = 0x86 # macro -PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 # macro -PACKET3_SWITCH_BUFFER = 0x8B # macro -PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C # macro -PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C # macro -PACKET3_DISPATCH_DRAW = 0x8D # macro -PACKET3_DISPATCH_DRAW_ACE = 0x8D # macro -PACKET3_GET_LOD_STATS = 0x8E # macro -PACKET3_DRAW_MULTI_PREAMBLE = 0x8F # macro -PACKET3_FRAME_CONTROL = 0x90 # macro -FRAME_TMZ = (1<<0) # macro -def FRAME_CMD(x): # macro - return ((x)<<28) -PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 # macro -PACKET3_WAIT_REG_MEM64 = 0x93 # macro -PACKET3_COND_PREEMPT = 0x94 # macro -PACKET3_HDP_FLUSH = 0x95 # macro -PACKET3_COPY_DATA_RB = 0x96 # macro -PACKET3_INVALIDATE_TLBS = 0x98 # macro -def PACKET3_INVALIDATE_TLBS_DST_SEL(x): # macro - return ((x)<<0) -def PACKET3_INVALIDATE_TLBS_ALL_HUB(x): # macro - return ((x)<<4) -def PACKET3_INVALIDATE_TLBS_PASID(x): # macro - return ((x)<<5) -PACKET3_AQL_PACKET = 0x99 # macro -PACKET3_DMA_DATA_FILL_MULTI = 0x9A # macro -PACKET3_SET_SH_REG_INDEX = 0x9B # macro -PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C # macro -PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D # macro -PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E # macro -PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F # macro -PACKET3_SET_RESOURCES = 0xA0 # macro -def PACKET3_SET_RESOURCES_VMID_MASK(x): # macro - return ((x)<<0) -def PACKET3_SET_RESOURCES_UNMAP_LATENTY(x): # macro - return ((x)<<16) -def PACKET3_SET_RESOURCES_QUEUE_TYPE(x): # macro - return ((x)<<29) -PACKET3_MAP_PROCESS = 0xA1 # macro -PACKET3_MAP_QUEUES = 0xA2 # macro -def PACKET3_MAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_MAP_QUEUES_VMID(x): # macro - return ((x)<<8) -def PACKET3_MAP_QUEUES_QUEUE(x): # macro - return ((x)<<13) -def PACKET3_MAP_QUEUES_PIPE(x): # macro - return ((x)<<16) -def PACKET3_MAP_QUEUES_ME(x): # macro - return ((x)<<18) -def PACKET3_MAP_QUEUES_QUEUE_TYPE(x): # macro - return ((x)<<21) -def PACKET3_MAP_QUEUES_ALLOC_FORMAT(x): # macro - return ((x)<<24) -def PACKET3_MAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_MAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_MAP_QUEUES_CHECK_DISABLE(x): # macro - return ((x)<<1) -def PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -PACKET3_UNMAP_QUEUES = 0xA3 # macro -def PACKET3_UNMAP_QUEUES_ACTION(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_QUEUE_SEL(x): # macro - return ((x)<<4) -def PACKET3_UNMAP_QUEUES_ENGINE_SEL(x): # macro - return ((x)<<26) -def PACKET3_UNMAP_QUEUES_NUM_QUEUES(x): # macro - return ((x)<<29) -def PACKET3_UNMAP_QUEUES_PASID(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_RB_WPTR(x): # macro - return ((x)<<0) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x): # macro - return ((x)<<2) -def PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x): # macro - return ((x)<<2) -PACKET3_QUERY_STATUS = 0xA4 # macro -def PACKET3_QUERY_STATUS_CONTEXT_ID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_INTERRUPT_SEL(x): # macro - return ((x)<<28) -def PACKET3_QUERY_STATUS_COMMAND(x): # macro - return ((x)<<30) -def PACKET3_QUERY_STATUS_PASID(x): # macro - return ((x)<<0) -def PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x): # macro - return ((x)<<2) -def PACKET3_QUERY_STATUS_ENG_SEL(x): # macro - return ((x)<<25) -PACKET3_RUN_LIST = 0xA5 # macro -PACKET3_MAP_PROCESS_VM = 0xA6 # macro -PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro -def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro - return ((x)<<0) -PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro -_gc_11_0_0_OFFSET_HEADER = True # macro -regSDMA0_DEC_START = 0x0000 # macro -regSDMA0_DEC_START_BASE_IDX = 0 # macro -regSDMA0_F32_MISC_CNTL = 0x000b # macro -regSDMA0_F32_MISC_CNTL_BASE_IDX = 0 # macro -regSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro -regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro -regSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro -regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro -regSDMA0_POWER_CNTL = 0x001a # macro -regSDMA0_POWER_CNTL_BASE_IDX = 0 # macro -regSDMA0_CNTL = 0x001c # macro -regSDMA0_CNTL_BASE_IDX = 0 # macro -regSDMA0_CHICKEN_BITS = 0x001d # macro -regSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro -regSDMA0_GB_ADDR_CONFIG = 0x001e # macro -regSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro -regSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro -regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -regSDMA0_RB_RPTR_FETCH = 0x0020 # macro -regSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro -regSDMA0_RB_RPTR_FETCH_HI = 0x0021 # macro -regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro -regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0022 # macro -regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro -regSDMA0_IB_OFFSET_FETCH = 0x0023 # macro -regSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro -regSDMA0_PROGRAM = 0x0024 # macro -regSDMA0_PROGRAM_BASE_IDX = 0 # macro -regSDMA0_STATUS_REG = 0x0025 # macro -regSDMA0_STATUS_REG_BASE_IDX = 0 # macro -regSDMA0_STATUS1_REG = 0x0026 # macro -regSDMA0_STATUS1_REG_BASE_IDX = 0 # macro -regSDMA0_CNTL1 = 0x0027 # macro -regSDMA0_CNTL1_BASE_IDX = 0 # macro -regSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro -regSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro -regSDMA0_UCODE_CHECKSUM = 0x0029 # macro -regSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro -regSDMA0_FREEZE = 0x002b # macro -regSDMA0_FREEZE_BASE_IDX = 0 # macro -regSDMA0_PROCESS_QUANTUM0 = 0x002c # macro -regSDMA0_PROCESS_QUANTUM0_BASE_IDX = 0 # macro -regSDMA0_PROCESS_QUANTUM1 = 0x002d # macro -regSDMA0_PROCESS_QUANTUM1_BASE_IDX = 0 # macro -regSDMA0_WATCHDOG_CNTL = 0x002e # macro -regSDMA0_WATCHDOG_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE_STATUS0 = 0x002f # macro -regSDMA0_QUEUE_STATUS0_BASE_IDX = 0 # macro -regSDMA0_EDC_CONFIG = 0x0032 # macro -regSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro -regSDMA0_BA_THRESHOLD = 0x0033 # macro -regSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro -regSDMA0_ID = 0x0034 # macro -regSDMA0_ID_BASE_IDX = 0 # macro -regSDMA0_VERSION = 0x0035 # macro -regSDMA0_VERSION_BASE_IDX = 0 # macro -regSDMA0_EDC_COUNTER = 0x0036 # macro -regSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro -regSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro -regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro -regSDMA0_STATUS2_REG = 0x0038 # macro -regSDMA0_STATUS2_REG_BASE_IDX = 0 # macro -regSDMA0_ATOMIC_CNTL = 0x0039 # macro -regSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro -regSDMA0_ATOMIC_PREOP_LO = 0x003a # macro -regSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro -regSDMA0_ATOMIC_PREOP_HI = 0x003b # macro -regSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro -regSDMA0_UTCL1_CNTL = 0x003c # macro -regSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WATERMK = 0x003d # macro -regSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro -regSDMA0_UTCL1_TIMEOUT = 0x003e # macro -regSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro -regSDMA0_UTCL1_PAGE = 0x003f # macro -regSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro -regSDMA0_UTCL1_RD_STATUS = 0x0040 # macro -regSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WR_STATUS = 0x0041 # macro -regSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro -regSDMA0_UTCL1_INV0 = 0x0042 # macro -regSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro -regSDMA0_UTCL1_INV1 = 0x0043 # macro -regSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro -regSDMA0_UTCL1_INV2 = 0x0044 # macro -regSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro -regSDMA0_UTCL1_RD_XNACK0 = 0x0045 # macro -regSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro -regSDMA0_UTCL1_RD_XNACK1 = 0x0046 # macro -regSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WR_XNACK0 = 0x0047 # macro -regSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro -regSDMA0_UTCL1_WR_XNACK1 = 0x0048 # macro -regSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro -regSDMA0_RELAX_ORDERING_LUT = 0x004a # macro -regSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro -regSDMA0_CHICKEN_BITS_2 = 0x004b # macro -regSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro -regSDMA0_STATUS3_REG = 0x004c # macro -regSDMA0_STATUS3_REG_BASE_IDX = 0 # macro -regSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro -regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro -regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_GLOBAL_QUANTUM = 0x004f # macro -regSDMA0_GLOBAL_QUANTUM_BASE_IDX = 0 # macro -regSDMA0_ERROR_LOG = 0x0050 # macro -regSDMA0_ERROR_LOG_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro -regSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro -regSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro -regSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro -regSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro -regSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro -regSDMA0_F32_COUNTER = 0x0055 # macro -regSDMA0_F32_COUNTER_BASE_IDX = 0 # macro -regSDMA0_CRD_CNTL = 0x005b # macro -regSDMA0_CRD_CNTL_BASE_IDX = 0 # macro -regSDMA0_RLC_CGCG_CTRL = 0x005c # macro -regSDMA0_RLC_CGCG_CTRL_BASE_IDX = 0 # macro -regSDMA0_AQL_STATUS = 0x005f # macro -regSDMA0_AQL_STATUS_BASE_IDX = 0 # macro -regSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro -regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro -regSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro -regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro -regSDMA0_TLBI_GCR_CNTL = 0x0062 # macro -regSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro -regSDMA0_TILING_CONFIG = 0x0063 # macro -regSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro -regSDMA0_INT_STATUS = 0x0070 # macro -regSDMA0_INT_STATUS_BASE_IDX = 0 # macro -regSDMA0_HOLE_ADDR_LO = 0x0072 # macro -regSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_HOLE_ADDR_HI = 0x0073 # macro -regSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_CLOCK_GATING_STATUS = 0x0075 # macro -regSDMA0_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro -regSDMA0_STATUS4_REG = 0x0076 # macro -regSDMA0_STATUS4_REG_BASE_IDX = 0 # macro -regSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro -regSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro -regSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro -regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro -regSDMA0_TIMESTAMP_CNTL = 0x0079 # macro -regSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro -regSDMA0_STATUS5_REG = 0x007a # macro -regSDMA0_STATUS5_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE_RESET_REQ = 0x007b # macro -regSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro -regSDMA0_STATUS6_REG = 0x007c # macro -regSDMA0_STATUS6_REG_BASE_IDX = 0 # macro -regSDMA0_UCODE1_CHECKSUM = 0x007d # macro -regSDMA0_UCODE1_CHECKSUM_BASE_IDX = 0 # macro -regSDMA0_CE_CTRL = 0x007e # macro -regSDMA0_CE_CTRL_BASE_IDX = 0 # macro -regSDMA0_FED_STATUS = 0x007f # macro -regSDMA0_FED_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_CNTL = 0x0080 # macro -regSDMA0_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_BASE = 0x0081 # macro -regSDMA0_QUEUE0_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_BASE_HI = 0x0082 # macro -regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR = 0x0083 # macro -regSDMA0_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR_HI = 0x0084 # macro -regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR = 0x0085 # macro -regSDMA0_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR_HI = 0x0086 # macro -regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_HI = 0x0088 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_LO = 0x0089 # macro -regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_CNTL = 0x008a # macro -regSDMA0_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_RPTR = 0x008b # macro -regSDMA0_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_OFFSET = 0x008c # macro -regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_BASE_LO = 0x008d # macro -regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_BASE_HI = 0x008e # macro -regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_SIZE = 0x008f # macro -regSDMA0_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_SKIP_CNTL = 0x0090 # macro -regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_CONTEXT_STATUS = 0x0091 # macro -regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DOORBELL = 0x0092 # macro -regSDMA0_QUEUE0_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DOORBELL_LOG = 0x00a9 # macro -regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DOORBELL_OFFSET = 0x00ab # macro -regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_CSA_ADDR_LO = 0x00ac # macro -regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_CSA_ADDR_HI = 0x00ad # macro -regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_SCHEDULE_CNTL = 0x00ae # macro -regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_IB_SUB_REMAIN = 0x00af # macro -regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_PREEMPT = 0x00b0 # macro -regSDMA0_QUEUE0_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_DUMMY_REG = 0x00b1 # macro -regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro -regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_AQL_CNTL = 0x00b4 # macro -regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MINOR_PTR_UPDATE = 0x00b5 # macro -regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_RB_PREEMPT = 0x00b6 # macro -regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA0 = 0x00c0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA1 = 0x00c1 # macro -regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA2 = 0x00c2 # macro -regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA3 = 0x00c3 # macro -regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA4 = 0x00c4 # macro -regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA5 = 0x00c5 # macro -regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA6 = 0x00c6 # macro -regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA7 = 0x00c7 # macro -regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA8 = 0x00c8 # macro -regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA9 = 0x00c9 # macro -regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_DATA10 = 0x00ca # macro -regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE0_MIDCMD_CNTL = 0x00cb # macro -regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_CNTL = 0x00d8 # macro -regSDMA0_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_BASE = 0x00d9 # macro -regSDMA0_QUEUE1_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_BASE_HI = 0x00da # macro -regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR = 0x00db # macro -regSDMA0_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR_HI = 0x00dc # macro -regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR = 0x00dd # macro -regSDMA0_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR_HI = 0x00de # macro -regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_HI = 0x00e0 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_LO = 0x00e1 # macro -regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_CNTL = 0x00e2 # macro -regSDMA0_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_RPTR = 0x00e3 # macro -regSDMA0_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_OFFSET = 0x00e4 # macro -regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_BASE_LO = 0x00e5 # macro -regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_BASE_HI = 0x00e6 # macro -regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_SIZE = 0x00e7 # macro -regSDMA0_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_SKIP_CNTL = 0x00e8 # macro -regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_CONTEXT_STATUS = 0x00e9 # macro -regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DOORBELL = 0x00ea # macro -regSDMA0_QUEUE1_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DOORBELL_LOG = 0x0101 # macro -regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DOORBELL_OFFSET = 0x0103 # macro -regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_CSA_ADDR_LO = 0x0104 # macro -regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_CSA_ADDR_HI = 0x0105 # macro -regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_SCHEDULE_CNTL = 0x0106 # macro -regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_IB_SUB_REMAIN = 0x0107 # macro -regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_PREEMPT = 0x0108 # macro -regSDMA0_QUEUE1_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_DUMMY_REG = 0x0109 # macro -regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x010a # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x010b # macro -regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_AQL_CNTL = 0x010c # macro -regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MINOR_PTR_UPDATE = 0x010d # macro -regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_RB_PREEMPT = 0x010e # macro -regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA0 = 0x0118 # macro -regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA1 = 0x0119 # macro -regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA2 = 0x011a # macro -regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA3 = 0x011b # macro -regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA4 = 0x011c # macro -regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA5 = 0x011d # macro -regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA6 = 0x011e # macro -regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA7 = 0x011f # macro -regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA8 = 0x0120 # macro -regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA9 = 0x0121 # macro -regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_DATA10 = 0x0122 # macro -regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE1_MIDCMD_CNTL = 0x0123 # macro -regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_CNTL = 0x0130 # macro -regSDMA0_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_BASE = 0x0131 # macro -regSDMA0_QUEUE2_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_BASE_HI = 0x0132 # macro -regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR = 0x0133 # macro -regSDMA0_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR_HI = 0x0134 # macro -regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR = 0x0135 # macro -regSDMA0_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR_HI = 0x0136 # macro -regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_HI = 0x0138 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_LO = 0x0139 # macro -regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_CNTL = 0x013a # macro -regSDMA0_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_RPTR = 0x013b # macro -regSDMA0_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_OFFSET = 0x013c # macro -regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_BASE_LO = 0x013d # macro -regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_BASE_HI = 0x013e # macro -regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_SIZE = 0x013f # macro -regSDMA0_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_SKIP_CNTL = 0x0140 # macro -regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_CONTEXT_STATUS = 0x0141 # macro -regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DOORBELL = 0x0142 # macro -regSDMA0_QUEUE2_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DOORBELL_LOG = 0x0159 # macro -regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DOORBELL_OFFSET = 0x015b # macro -regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_CSA_ADDR_LO = 0x015c # macro -regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_CSA_ADDR_HI = 0x015d # macro -regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_SCHEDULE_CNTL = 0x015e # macro -regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_IB_SUB_REMAIN = 0x015f # macro -regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_PREEMPT = 0x0160 # macro -regSDMA0_QUEUE2_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_DUMMY_REG = 0x0161 # macro -regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro -regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_AQL_CNTL = 0x0164 # macro -regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MINOR_PTR_UPDATE = 0x0165 # macro -regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_RB_PREEMPT = 0x0166 # macro -regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA0 = 0x0170 # macro -regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA1 = 0x0171 # macro -regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA2 = 0x0172 # macro -regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA3 = 0x0173 # macro -regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA4 = 0x0174 # macro -regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA5 = 0x0175 # macro -regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA6 = 0x0176 # macro -regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA7 = 0x0177 # macro -regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA8 = 0x0178 # macro -regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA9 = 0x0179 # macro -regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_DATA10 = 0x017a # macro -regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE2_MIDCMD_CNTL = 0x017b # macro -regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_CNTL = 0x0188 # macro -regSDMA0_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_BASE = 0x0189 # macro -regSDMA0_QUEUE3_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_BASE_HI = 0x018a # macro -regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR = 0x018b # macro -regSDMA0_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR_HI = 0x018c # macro -regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR = 0x018d # macro -regSDMA0_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR_HI = 0x018e # macro -regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_HI = 0x0190 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_LO = 0x0191 # macro -regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_CNTL = 0x0192 # macro -regSDMA0_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_RPTR = 0x0193 # macro -regSDMA0_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_OFFSET = 0x0194 # macro -regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_BASE_LO = 0x0195 # macro -regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_BASE_HI = 0x0196 # macro -regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_SIZE = 0x0197 # macro -regSDMA0_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_SKIP_CNTL = 0x0198 # macro -regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_CONTEXT_STATUS = 0x0199 # macro -regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DOORBELL = 0x019a # macro -regSDMA0_QUEUE3_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DOORBELL_LOG = 0x01b1 # macro -regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DOORBELL_OFFSET = 0x01b3 # macro -regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_CSA_ADDR_LO = 0x01b4 # macro -regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_CSA_ADDR_HI = 0x01b5 # macro -regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_SCHEDULE_CNTL = 0x01b6 # macro -regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_IB_SUB_REMAIN = 0x01b7 # macro -regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_PREEMPT = 0x01b8 # macro -regSDMA0_QUEUE3_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_DUMMY_REG = 0x01b9 # macro -regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro -regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_AQL_CNTL = 0x01bc # macro -regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MINOR_PTR_UPDATE = 0x01bd # macro -regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_RB_PREEMPT = 0x01be # macro -regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA0 = 0x01c8 # macro -regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA1 = 0x01c9 # macro -regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA2 = 0x01ca # macro -regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA3 = 0x01cb # macro -regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA4 = 0x01cc # macro -regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA5 = 0x01cd # macro -regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA6 = 0x01ce # macro -regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA7 = 0x01cf # macro -regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA8 = 0x01d0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA9 = 0x01d1 # macro -regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_DATA10 = 0x01d2 # macro -regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE3_MIDCMD_CNTL = 0x01d3 # macro -regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_CNTL = 0x01e0 # macro -regSDMA0_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_BASE = 0x01e1 # macro -regSDMA0_QUEUE4_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_BASE_HI = 0x01e2 # macro -regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR = 0x01e3 # macro -regSDMA0_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR_HI = 0x01e4 # macro -regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR = 0x01e5 # macro -regSDMA0_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR_HI = 0x01e6 # macro -regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_HI = 0x01e8 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_LO = 0x01e9 # macro -regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_CNTL = 0x01ea # macro -regSDMA0_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_RPTR = 0x01eb # macro -regSDMA0_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_OFFSET = 0x01ec # macro -regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_BASE_LO = 0x01ed # macro -regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_BASE_HI = 0x01ee # macro -regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_SIZE = 0x01ef # macro -regSDMA0_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_SKIP_CNTL = 0x01f0 # macro -regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_CONTEXT_STATUS = 0x01f1 # macro -regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DOORBELL = 0x01f2 # macro -regSDMA0_QUEUE4_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DOORBELL_LOG = 0x0209 # macro -regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DOORBELL_OFFSET = 0x020b # macro -regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_CSA_ADDR_LO = 0x020c # macro -regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_CSA_ADDR_HI = 0x020d # macro -regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_SCHEDULE_CNTL = 0x020e # macro -regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_IB_SUB_REMAIN = 0x020f # macro -regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_PREEMPT = 0x0210 # macro -regSDMA0_QUEUE4_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_DUMMY_REG = 0x0211 # macro -regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro -regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_AQL_CNTL = 0x0214 # macro -regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MINOR_PTR_UPDATE = 0x0215 # macro -regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_RB_PREEMPT = 0x0216 # macro -regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA0 = 0x0220 # macro -regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA1 = 0x0221 # macro -regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA2 = 0x0222 # macro -regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA3 = 0x0223 # macro -regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA4 = 0x0224 # macro -regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA5 = 0x0225 # macro -regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA6 = 0x0226 # macro -regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA7 = 0x0227 # macro -regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA8 = 0x0228 # macro -regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA9 = 0x0229 # macro -regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_DATA10 = 0x022a # macro -regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE4_MIDCMD_CNTL = 0x022b # macro -regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_CNTL = 0x0238 # macro -regSDMA0_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_BASE = 0x0239 # macro -regSDMA0_QUEUE5_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_BASE_HI = 0x023a # macro -regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR = 0x023b # macro -regSDMA0_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR_HI = 0x023c # macro -regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR = 0x023d # macro -regSDMA0_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR_HI = 0x023e # macro -regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_HI = 0x0240 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_LO = 0x0241 # macro -regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_CNTL = 0x0242 # macro -regSDMA0_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_RPTR = 0x0243 # macro -regSDMA0_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_OFFSET = 0x0244 # macro -regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_BASE_LO = 0x0245 # macro -regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_BASE_HI = 0x0246 # macro -regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_SIZE = 0x0247 # macro -regSDMA0_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_SKIP_CNTL = 0x0248 # macro -regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_CONTEXT_STATUS = 0x0249 # macro -regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DOORBELL = 0x024a # macro -regSDMA0_QUEUE5_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DOORBELL_LOG = 0x0261 # macro -regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DOORBELL_OFFSET = 0x0263 # macro -regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_CSA_ADDR_LO = 0x0264 # macro -regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_CSA_ADDR_HI = 0x0265 # macro -regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_SCHEDULE_CNTL = 0x0266 # macro -regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_IB_SUB_REMAIN = 0x0267 # macro -regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_PREEMPT = 0x0268 # macro -regSDMA0_QUEUE5_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_DUMMY_REG = 0x0269 # macro -regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x026a # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x026b # macro -regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_AQL_CNTL = 0x026c # macro -regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MINOR_PTR_UPDATE = 0x026d # macro -regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_RB_PREEMPT = 0x026e # macro -regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA0 = 0x0278 # macro -regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA1 = 0x0279 # macro -regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA2 = 0x027a # macro -regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA3 = 0x027b # macro -regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA4 = 0x027c # macro -regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA5 = 0x027d # macro -regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA6 = 0x027e # macro -regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA7 = 0x027f # macro -regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA8 = 0x0280 # macro -regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA9 = 0x0281 # macro -regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_DATA10 = 0x0282 # macro -regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE5_MIDCMD_CNTL = 0x0283 # macro -regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_CNTL = 0x0290 # macro -regSDMA0_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_BASE = 0x0291 # macro -regSDMA0_QUEUE6_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_BASE_HI = 0x0292 # macro -regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR = 0x0293 # macro -regSDMA0_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR_HI = 0x0294 # macro -regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR = 0x0295 # macro -regSDMA0_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR_HI = 0x0296 # macro -regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_HI = 0x0298 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_LO = 0x0299 # macro -regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_CNTL = 0x029a # macro -regSDMA0_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_RPTR = 0x029b # macro -regSDMA0_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_OFFSET = 0x029c # macro -regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_BASE_LO = 0x029d # macro -regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_BASE_HI = 0x029e # macro -regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_SIZE = 0x029f # macro -regSDMA0_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_SKIP_CNTL = 0x02a0 # macro -regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_CONTEXT_STATUS = 0x02a1 # macro -regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DOORBELL = 0x02a2 # macro -regSDMA0_QUEUE6_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DOORBELL_LOG = 0x02b9 # macro -regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DOORBELL_OFFSET = 0x02bb # macro -regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_CSA_ADDR_LO = 0x02bc # macro -regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_CSA_ADDR_HI = 0x02bd # macro -regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_SCHEDULE_CNTL = 0x02be # macro -regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_IB_SUB_REMAIN = 0x02bf # macro -regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_PREEMPT = 0x02c0 # macro -regSDMA0_QUEUE6_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_DUMMY_REG = 0x02c1 # macro -regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro -regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_AQL_CNTL = 0x02c4 # macro -regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MINOR_PTR_UPDATE = 0x02c5 # macro -regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_RB_PREEMPT = 0x02c6 # macro -regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA0 = 0x02d0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA1 = 0x02d1 # macro -regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA2 = 0x02d2 # macro -regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA3 = 0x02d3 # macro -regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA4 = 0x02d4 # macro -regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA5 = 0x02d5 # macro -regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA6 = 0x02d6 # macro -regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA7 = 0x02d7 # macro -regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA8 = 0x02d8 # macro -regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA9 = 0x02d9 # macro -regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_DATA10 = 0x02da # macro -regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE6_MIDCMD_CNTL = 0x02db # macro -regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_CNTL = 0x02e8 # macro -regSDMA0_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_BASE = 0x02e9 # macro -regSDMA0_QUEUE7_RB_BASE_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_BASE_HI = 0x02ea # macro -regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR = 0x02eb # macro -regSDMA0_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR_HI = 0x02ec # macro -regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR = 0x02ed # macro -regSDMA0_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR_HI = 0x02ee # macro -regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_HI = 0x02f0 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_LO = 0x02f1 # macro -regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_CNTL = 0x02f2 # macro -regSDMA0_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_RPTR = 0x02f3 # macro -regSDMA0_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_OFFSET = 0x02f4 # macro -regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_BASE_LO = 0x02f5 # macro -regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_BASE_HI = 0x02f6 # macro -regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_SIZE = 0x02f7 # macro -regSDMA0_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_SKIP_CNTL = 0x02f8 # macro -regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_CONTEXT_STATUS = 0x02f9 # macro -regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DOORBELL = 0x02fa # macro -regSDMA0_QUEUE7_DOORBELL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DOORBELL_LOG = 0x0311 # macro -regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DOORBELL_OFFSET = 0x0313 # macro -regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_CSA_ADDR_LO = 0x0314 # macro -regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_CSA_ADDR_HI = 0x0315 # macro -regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_SCHEDULE_CNTL = 0x0316 # macro -regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_IB_SUB_REMAIN = 0x0317 # macro -regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_PREEMPT = 0x0318 # macro -regSDMA0_QUEUE7_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_DUMMY_REG = 0x0319 # macro -regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x031a # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x031b # macro -regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_AQL_CNTL = 0x031c # macro -regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MINOR_PTR_UPDATE = 0x031d # macro -regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_RB_PREEMPT = 0x031e # macro -regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA0 = 0x0328 # macro -regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA1 = 0x0329 # macro -regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA2 = 0x032a # macro -regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA3 = 0x032b # macro -regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA4 = 0x032c # macro -regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA5 = 0x032d # macro -regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA6 = 0x032e # macro -regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA7 = 0x032f # macro -regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA8 = 0x0330 # macro -regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA9 = 0x0331 # macro -regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_DATA10 = 0x0332 # macro -regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA0_QUEUE7_MIDCMD_CNTL = 0x0333 # macro -regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_DEC_START = 0x0600 # macro -regSDMA1_DEC_START_BASE_IDX = 0 # macro -regSDMA1_F32_MISC_CNTL = 0x060b # macro -regSDMA1_F32_MISC_CNTL_BASE_IDX = 0 # macro -regSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro -regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro -regSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro -regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro -regSDMA1_POWER_CNTL = 0x061a # macro -regSDMA1_POWER_CNTL_BASE_IDX = 0 # macro -regSDMA1_CNTL = 0x061c # macro -regSDMA1_CNTL_BASE_IDX = 0 # macro -regSDMA1_CHICKEN_BITS = 0x061d # macro -regSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro -regSDMA1_GB_ADDR_CONFIG = 0x061e # macro -regSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro -regSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro -regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -regSDMA1_RB_RPTR_FETCH = 0x0620 # macro -regSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro -regSDMA1_RB_RPTR_FETCH_HI = 0x0621 # macro -regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro -regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0622 # macro -regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro -regSDMA1_IB_OFFSET_FETCH = 0x0623 # macro -regSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro -regSDMA1_PROGRAM = 0x0624 # macro -regSDMA1_PROGRAM_BASE_IDX = 0 # macro -regSDMA1_STATUS_REG = 0x0625 # macro -regSDMA1_STATUS_REG_BASE_IDX = 0 # macro -regSDMA1_STATUS1_REG = 0x0626 # macro -regSDMA1_STATUS1_REG_BASE_IDX = 0 # macro -regSDMA1_CNTL1 = 0x0627 # macro -regSDMA1_CNTL1_BASE_IDX = 0 # macro -regSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro -regSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro -regSDMA1_UCODE_CHECKSUM = 0x0629 # macro -regSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro -regSDMA1_FREEZE = 0x062b # macro -regSDMA1_FREEZE_BASE_IDX = 0 # macro -regSDMA1_PROCESS_QUANTUM0 = 0x062c # macro -regSDMA1_PROCESS_QUANTUM0_BASE_IDX = 0 # macro -regSDMA1_PROCESS_QUANTUM1 = 0x062d # macro -regSDMA1_PROCESS_QUANTUM1_BASE_IDX = 0 # macro -regSDMA1_WATCHDOG_CNTL = 0x062e # macro -regSDMA1_WATCHDOG_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE_STATUS0 = 0x062f # macro -regSDMA1_QUEUE_STATUS0_BASE_IDX = 0 # macro -regSDMA1_EDC_CONFIG = 0x0632 # macro -regSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro -regSDMA1_BA_THRESHOLD = 0x0633 # macro -regSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro -regSDMA1_ID = 0x0634 # macro -regSDMA1_ID_BASE_IDX = 0 # macro -regSDMA1_VERSION = 0x0635 # macro -regSDMA1_VERSION_BASE_IDX = 0 # macro -regSDMA1_EDC_COUNTER = 0x0636 # macro -regSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro -regSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro -regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro -regSDMA1_STATUS2_REG = 0x0638 # macro -regSDMA1_STATUS2_REG_BASE_IDX = 0 # macro -regSDMA1_ATOMIC_CNTL = 0x0639 # macro -regSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro -regSDMA1_ATOMIC_PREOP_LO = 0x063a # macro -regSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro -regSDMA1_ATOMIC_PREOP_HI = 0x063b # macro -regSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro -regSDMA1_UTCL1_CNTL = 0x063c # macro -regSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WATERMK = 0x063d # macro -regSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro -regSDMA1_UTCL1_TIMEOUT = 0x063e # macro -regSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro -regSDMA1_UTCL1_PAGE = 0x063f # macro -regSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro -regSDMA1_UTCL1_RD_STATUS = 0x0640 # macro -regSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WR_STATUS = 0x0641 # macro -regSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro -regSDMA1_UTCL1_INV0 = 0x0642 # macro -regSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro -regSDMA1_UTCL1_INV1 = 0x0643 # macro -regSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro -regSDMA1_UTCL1_INV2 = 0x0644 # macro -regSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro -regSDMA1_UTCL1_RD_XNACK0 = 0x0645 # macro -regSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro -regSDMA1_UTCL1_RD_XNACK1 = 0x0646 # macro -regSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WR_XNACK0 = 0x0647 # macro -regSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro -regSDMA1_UTCL1_WR_XNACK1 = 0x0648 # macro -regSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro -regSDMA1_RELAX_ORDERING_LUT = 0x064a # macro -regSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro -regSDMA1_CHICKEN_BITS_2 = 0x064b # macro -regSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro -regSDMA1_STATUS3_REG = 0x064c # macro -regSDMA1_STATUS3_REG_BASE_IDX = 0 # macro -regSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro -regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro -regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_GLOBAL_QUANTUM = 0x064f # macro -regSDMA1_GLOBAL_QUANTUM_BASE_IDX = 0 # macro -regSDMA1_ERROR_LOG = 0x0650 # macro -regSDMA1_ERROR_LOG_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro -regSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro -regSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro -regSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro -regSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro -regSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro -regSDMA1_F32_COUNTER = 0x0655 # macro -regSDMA1_F32_COUNTER_BASE_IDX = 0 # macro -regSDMA1_CRD_CNTL = 0x065b # macro -regSDMA1_CRD_CNTL_BASE_IDX = 0 # macro -regSDMA1_RLC_CGCG_CTRL = 0x065c # macro -regSDMA1_RLC_CGCG_CTRL_BASE_IDX = 0 # macro -regSDMA1_AQL_STATUS = 0x065f # macro -regSDMA1_AQL_STATUS_BASE_IDX = 0 # macro -regSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro -regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro -regSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro -regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro -regSDMA1_TLBI_GCR_CNTL = 0x0662 # macro -regSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro -regSDMA1_TILING_CONFIG = 0x0663 # macro -regSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro -regSDMA1_INT_STATUS = 0x0670 # macro -regSDMA1_INT_STATUS_BASE_IDX = 0 # macro -regSDMA1_HOLE_ADDR_LO = 0x0672 # macro -regSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_HOLE_ADDR_HI = 0x0673 # macro -regSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_CLOCK_GATING_STATUS = 0x0675 # macro -regSDMA1_CLOCK_GATING_STATUS_BASE_IDX = 0 # macro -regSDMA1_STATUS4_REG = 0x0676 # macro -regSDMA1_STATUS4_REG_BASE_IDX = 0 # macro -regSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro -regSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro -regSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro -regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro -regSDMA1_TIMESTAMP_CNTL = 0x0679 # macro -regSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro -regSDMA1_STATUS5_REG = 0x067a # macro -regSDMA1_STATUS5_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE_RESET_REQ = 0x067b # macro -regSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro -regSDMA1_STATUS6_REG = 0x067c # macro -regSDMA1_STATUS6_REG_BASE_IDX = 0 # macro -regSDMA1_UCODE1_CHECKSUM = 0x067d # macro -regSDMA1_UCODE1_CHECKSUM_BASE_IDX = 0 # macro -regSDMA1_CE_CTRL = 0x067e # macro -regSDMA1_CE_CTRL_BASE_IDX = 0 # macro -regSDMA1_FED_STATUS = 0x067f # macro -regSDMA1_FED_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_CNTL = 0x0680 # macro -regSDMA1_QUEUE0_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_BASE = 0x0681 # macro -regSDMA1_QUEUE0_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_BASE_HI = 0x0682 # macro -regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR = 0x0683 # macro -regSDMA1_QUEUE0_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR_HI = 0x0684 # macro -regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR = 0x0685 # macro -regSDMA1_QUEUE0_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR_HI = 0x0686 # macro -regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_HI = 0x0688 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_LO = 0x0689 # macro -regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_CNTL = 0x068a # macro -regSDMA1_QUEUE0_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_RPTR = 0x068b # macro -regSDMA1_QUEUE0_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_OFFSET = 0x068c # macro -regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_BASE_LO = 0x068d # macro -regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_BASE_HI = 0x068e # macro -regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_SIZE = 0x068f # macro -regSDMA1_QUEUE0_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_SKIP_CNTL = 0x0690 # macro -regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_CONTEXT_STATUS = 0x0691 # macro -regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DOORBELL = 0x0692 # macro -regSDMA1_QUEUE0_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DOORBELL_LOG = 0x06a9 # macro -regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DOORBELL_OFFSET = 0x06ab # macro -regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_CSA_ADDR_LO = 0x06ac # macro -regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_CSA_ADDR_HI = 0x06ad # macro -regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_SCHEDULE_CNTL = 0x06ae # macro -regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_IB_SUB_REMAIN = 0x06af # macro -regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_PREEMPT = 0x06b0 # macro -regSDMA1_QUEUE0_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_DUMMY_REG = 0x06b1 # macro -regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro -regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_AQL_CNTL = 0x06b4 # macro -regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MINOR_PTR_UPDATE = 0x06b5 # macro -regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_RB_PREEMPT = 0x06b6 # macro -regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA0 = 0x06c0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA1 = 0x06c1 # macro -regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA2 = 0x06c2 # macro -regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA3 = 0x06c3 # macro -regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA4 = 0x06c4 # macro -regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA5 = 0x06c5 # macro -regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA6 = 0x06c6 # macro -regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA7 = 0x06c7 # macro -regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA8 = 0x06c8 # macro -regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA9 = 0x06c9 # macro -regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_DATA10 = 0x06ca # macro -regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE0_MIDCMD_CNTL = 0x06cb # macro -regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_CNTL = 0x06d8 # macro -regSDMA1_QUEUE1_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_BASE = 0x06d9 # macro -regSDMA1_QUEUE1_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_BASE_HI = 0x06da # macro -regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR = 0x06db # macro -regSDMA1_QUEUE1_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR_HI = 0x06dc # macro -regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR = 0x06dd # macro -regSDMA1_QUEUE1_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR_HI = 0x06de # macro -regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_HI = 0x06e0 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_LO = 0x06e1 # macro -regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_CNTL = 0x06e2 # macro -regSDMA1_QUEUE1_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_RPTR = 0x06e3 # macro -regSDMA1_QUEUE1_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_OFFSET = 0x06e4 # macro -regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_BASE_LO = 0x06e5 # macro -regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_BASE_HI = 0x06e6 # macro -regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_SIZE = 0x06e7 # macro -regSDMA1_QUEUE1_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_SKIP_CNTL = 0x06e8 # macro -regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_CONTEXT_STATUS = 0x06e9 # macro -regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DOORBELL = 0x06ea # macro -regSDMA1_QUEUE1_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DOORBELL_LOG = 0x0701 # macro -regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DOORBELL_OFFSET = 0x0703 # macro -regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_CSA_ADDR_LO = 0x0704 # macro -regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_CSA_ADDR_HI = 0x0705 # macro -regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_SCHEDULE_CNTL = 0x0706 # macro -regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_IB_SUB_REMAIN = 0x0707 # macro -regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_PREEMPT = 0x0708 # macro -regSDMA1_QUEUE1_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_DUMMY_REG = 0x0709 # macro -regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x070a # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x070b # macro -regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_AQL_CNTL = 0x070c # macro -regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MINOR_PTR_UPDATE = 0x070d # macro -regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_RB_PREEMPT = 0x070e # macro -regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA0 = 0x0718 # macro -regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA1 = 0x0719 # macro -regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA2 = 0x071a # macro -regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA3 = 0x071b # macro -regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA4 = 0x071c # macro -regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA5 = 0x071d # macro -regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA6 = 0x071e # macro -regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA7 = 0x071f # macro -regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA8 = 0x0720 # macro -regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA9 = 0x0721 # macro -regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_DATA10 = 0x0722 # macro -regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE1_MIDCMD_CNTL = 0x0723 # macro -regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_CNTL = 0x0730 # macro -regSDMA1_QUEUE2_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_BASE = 0x0731 # macro -regSDMA1_QUEUE2_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_BASE_HI = 0x0732 # macro -regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR = 0x0733 # macro -regSDMA1_QUEUE2_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR_HI = 0x0734 # macro -regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR = 0x0735 # macro -regSDMA1_QUEUE2_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR_HI = 0x0736 # macro -regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_HI = 0x0738 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_LO = 0x0739 # macro -regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_CNTL = 0x073a # macro -regSDMA1_QUEUE2_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_RPTR = 0x073b # macro -regSDMA1_QUEUE2_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_OFFSET = 0x073c # macro -regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_BASE_LO = 0x073d # macro -regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_BASE_HI = 0x073e # macro -regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_SIZE = 0x073f # macro -regSDMA1_QUEUE2_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_SKIP_CNTL = 0x0740 # macro -regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_CONTEXT_STATUS = 0x0741 # macro -regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DOORBELL = 0x0742 # macro -regSDMA1_QUEUE2_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DOORBELL_LOG = 0x0759 # macro -regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DOORBELL_OFFSET = 0x075b # macro -regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_CSA_ADDR_LO = 0x075c # macro -regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_CSA_ADDR_HI = 0x075d # macro -regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_SCHEDULE_CNTL = 0x075e # macro -regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_IB_SUB_REMAIN = 0x075f # macro -regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_PREEMPT = 0x0760 # macro -regSDMA1_QUEUE2_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_DUMMY_REG = 0x0761 # macro -regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro -regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_AQL_CNTL = 0x0764 # macro -regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MINOR_PTR_UPDATE = 0x0765 # macro -regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_RB_PREEMPT = 0x0766 # macro -regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA0 = 0x0770 # macro -regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA1 = 0x0771 # macro -regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA2 = 0x0772 # macro -regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA3 = 0x0773 # macro -regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA4 = 0x0774 # macro -regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA5 = 0x0775 # macro -regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA6 = 0x0776 # macro -regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA7 = 0x0777 # macro -regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA8 = 0x0778 # macro -regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA9 = 0x0779 # macro -regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_DATA10 = 0x077a # macro -regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE2_MIDCMD_CNTL = 0x077b # macro -regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_CNTL = 0x0788 # macro -regSDMA1_QUEUE3_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_BASE = 0x0789 # macro -regSDMA1_QUEUE3_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_BASE_HI = 0x078a # macro -regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR = 0x078b # macro -regSDMA1_QUEUE3_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR_HI = 0x078c # macro -regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR = 0x078d # macro -regSDMA1_QUEUE3_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR_HI = 0x078e # macro -regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_HI = 0x0790 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_LO = 0x0791 # macro -regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_CNTL = 0x0792 # macro -regSDMA1_QUEUE3_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_RPTR = 0x0793 # macro -regSDMA1_QUEUE3_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_OFFSET = 0x0794 # macro -regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_BASE_LO = 0x0795 # macro -regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_BASE_HI = 0x0796 # macro -regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_SIZE = 0x0797 # macro -regSDMA1_QUEUE3_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_SKIP_CNTL = 0x0798 # macro -regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_CONTEXT_STATUS = 0x0799 # macro -regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DOORBELL = 0x079a # macro -regSDMA1_QUEUE3_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DOORBELL_LOG = 0x07b1 # macro -regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DOORBELL_OFFSET = 0x07b3 # macro -regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_CSA_ADDR_LO = 0x07b4 # macro -regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_CSA_ADDR_HI = 0x07b5 # macro -regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_SCHEDULE_CNTL = 0x07b6 # macro -regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_IB_SUB_REMAIN = 0x07b7 # macro -regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_PREEMPT = 0x07b8 # macro -regSDMA1_QUEUE3_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_DUMMY_REG = 0x07b9 # macro -regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro -regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_AQL_CNTL = 0x07bc # macro -regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MINOR_PTR_UPDATE = 0x07bd # macro -regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_RB_PREEMPT = 0x07be # macro -regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA0 = 0x07c8 # macro -regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA1 = 0x07c9 # macro -regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA2 = 0x07ca # macro -regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA3 = 0x07cb # macro -regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA4 = 0x07cc # macro -regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA5 = 0x07cd # macro -regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA6 = 0x07ce # macro -regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA7 = 0x07cf # macro -regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA8 = 0x07d0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA9 = 0x07d1 # macro -regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_DATA10 = 0x07d2 # macro -regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE3_MIDCMD_CNTL = 0x07d3 # macro -regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_CNTL = 0x07e0 # macro -regSDMA1_QUEUE4_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_BASE = 0x07e1 # macro -regSDMA1_QUEUE4_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_BASE_HI = 0x07e2 # macro -regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR = 0x07e3 # macro -regSDMA1_QUEUE4_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR_HI = 0x07e4 # macro -regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR = 0x07e5 # macro -regSDMA1_QUEUE4_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR_HI = 0x07e6 # macro -regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_HI = 0x07e8 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_LO = 0x07e9 # macro -regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_CNTL = 0x07ea # macro -regSDMA1_QUEUE4_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_RPTR = 0x07eb # macro -regSDMA1_QUEUE4_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_OFFSET = 0x07ec # macro -regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_BASE_LO = 0x07ed # macro -regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_BASE_HI = 0x07ee # macro -regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_SIZE = 0x07ef # macro -regSDMA1_QUEUE4_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_SKIP_CNTL = 0x07f0 # macro -regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_CONTEXT_STATUS = 0x07f1 # macro -regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DOORBELL = 0x07f2 # macro -regSDMA1_QUEUE4_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DOORBELL_LOG = 0x0809 # macro -regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DOORBELL_OFFSET = 0x080b # macro -regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_CSA_ADDR_LO = 0x080c # macro -regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_CSA_ADDR_HI = 0x080d # macro -regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_SCHEDULE_CNTL = 0x080e # macro -regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_IB_SUB_REMAIN = 0x080f # macro -regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_PREEMPT = 0x0810 # macro -regSDMA1_QUEUE4_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_DUMMY_REG = 0x0811 # macro -regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro -regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_AQL_CNTL = 0x0814 # macro -regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MINOR_PTR_UPDATE = 0x0815 # macro -regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_RB_PREEMPT = 0x0816 # macro -regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA0 = 0x0820 # macro -regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA1 = 0x0821 # macro -regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA2 = 0x0822 # macro -regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA3 = 0x0823 # macro -regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA4 = 0x0824 # macro -regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA5 = 0x0825 # macro -regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA6 = 0x0826 # macro -regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA7 = 0x0827 # macro -regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA8 = 0x0828 # macro -regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA9 = 0x0829 # macro -regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_DATA10 = 0x082a # macro -regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE4_MIDCMD_CNTL = 0x082b # macro -regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_CNTL = 0x0838 # macro -regSDMA1_QUEUE5_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_BASE = 0x0839 # macro -regSDMA1_QUEUE5_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_BASE_HI = 0x083a # macro -regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR = 0x083b # macro -regSDMA1_QUEUE5_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR_HI = 0x083c # macro -regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR = 0x083d # macro -regSDMA1_QUEUE5_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR_HI = 0x083e # macro -regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_HI = 0x0840 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_LO = 0x0841 # macro -regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_CNTL = 0x0842 # macro -regSDMA1_QUEUE5_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_RPTR = 0x0843 # macro -regSDMA1_QUEUE5_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_OFFSET = 0x0844 # macro -regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_BASE_LO = 0x0845 # macro -regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_BASE_HI = 0x0846 # macro -regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_SIZE = 0x0847 # macro -regSDMA1_QUEUE5_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_SKIP_CNTL = 0x0848 # macro -regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_CONTEXT_STATUS = 0x0849 # macro -regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DOORBELL = 0x084a # macro -regSDMA1_QUEUE5_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DOORBELL_LOG = 0x0861 # macro -regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DOORBELL_OFFSET = 0x0863 # macro -regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_CSA_ADDR_LO = 0x0864 # macro -regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_CSA_ADDR_HI = 0x0865 # macro -regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_SCHEDULE_CNTL = 0x0866 # macro -regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_IB_SUB_REMAIN = 0x0867 # macro -regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_PREEMPT = 0x0868 # macro -regSDMA1_QUEUE5_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_DUMMY_REG = 0x0869 # macro -regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x086a # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x086b # macro -regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_AQL_CNTL = 0x086c # macro -regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MINOR_PTR_UPDATE = 0x086d # macro -regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_RB_PREEMPT = 0x086e # macro -regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA0 = 0x0878 # macro -regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA1 = 0x0879 # macro -regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA2 = 0x087a # macro -regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA3 = 0x087b # macro -regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA4 = 0x087c # macro -regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA5 = 0x087d # macro -regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA6 = 0x087e # macro -regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA7 = 0x087f # macro -regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA8 = 0x0880 # macro -regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA9 = 0x0881 # macro -regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_DATA10 = 0x0882 # macro -regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE5_MIDCMD_CNTL = 0x0883 # macro -regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_CNTL = 0x0890 # macro -regSDMA1_QUEUE6_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_BASE = 0x0891 # macro -regSDMA1_QUEUE6_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_BASE_HI = 0x0892 # macro -regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR = 0x0893 # macro -regSDMA1_QUEUE6_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR_HI = 0x0894 # macro -regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR = 0x0895 # macro -regSDMA1_QUEUE6_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR_HI = 0x0896 # macro -regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_HI = 0x0898 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_LO = 0x0899 # macro -regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_CNTL = 0x089a # macro -regSDMA1_QUEUE6_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_RPTR = 0x089b # macro -regSDMA1_QUEUE6_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_OFFSET = 0x089c # macro -regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_BASE_LO = 0x089d # macro -regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_BASE_HI = 0x089e # macro -regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_SIZE = 0x089f # macro -regSDMA1_QUEUE6_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_SKIP_CNTL = 0x08a0 # macro -regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_CONTEXT_STATUS = 0x08a1 # macro -regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DOORBELL = 0x08a2 # macro -regSDMA1_QUEUE6_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DOORBELL_LOG = 0x08b9 # macro -regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DOORBELL_OFFSET = 0x08bb # macro -regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_CSA_ADDR_LO = 0x08bc # macro -regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_CSA_ADDR_HI = 0x08bd # macro -regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_SCHEDULE_CNTL = 0x08be # macro -regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_IB_SUB_REMAIN = 0x08bf # macro -regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_PREEMPT = 0x08c0 # macro -regSDMA1_QUEUE6_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_DUMMY_REG = 0x08c1 # macro -regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro -regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_AQL_CNTL = 0x08c4 # macro -regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MINOR_PTR_UPDATE = 0x08c5 # macro -regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_RB_PREEMPT = 0x08c6 # macro -regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA0 = 0x08d0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA1 = 0x08d1 # macro -regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA2 = 0x08d2 # macro -regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA3 = 0x08d3 # macro -regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA4 = 0x08d4 # macro -regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA5 = 0x08d5 # macro -regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA6 = 0x08d6 # macro -regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA7 = 0x08d7 # macro -regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA8 = 0x08d8 # macro -regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA9 = 0x08d9 # macro -regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_DATA10 = 0x08da # macro -regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE6_MIDCMD_CNTL = 0x08db # macro -regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_CNTL = 0x08e8 # macro -regSDMA1_QUEUE7_RB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_BASE = 0x08e9 # macro -regSDMA1_QUEUE7_RB_BASE_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_BASE_HI = 0x08ea # macro -regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR = 0x08eb # macro -regSDMA1_QUEUE7_RB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR_HI = 0x08ec # macro -regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR = 0x08ed # macro -regSDMA1_QUEUE7_RB_WPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR_HI = 0x08ee # macro -regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_HI = 0x08f0 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_LO = 0x08f1 # macro -regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_CNTL = 0x08f2 # macro -regSDMA1_QUEUE7_IB_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_RPTR = 0x08f3 # macro -regSDMA1_QUEUE7_IB_RPTR_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_OFFSET = 0x08f4 # macro -regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_BASE_LO = 0x08f5 # macro -regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_BASE_HI = 0x08f6 # macro -regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_SIZE = 0x08f7 # macro -regSDMA1_QUEUE7_IB_SIZE_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_SKIP_CNTL = 0x08f8 # macro -regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_CONTEXT_STATUS = 0x08f9 # macro -regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DOORBELL = 0x08fa # macro -regSDMA1_QUEUE7_DOORBELL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DOORBELL_LOG = 0x0911 # macro -regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DOORBELL_OFFSET = 0x0913 # macro -regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_CSA_ADDR_LO = 0x0914 # macro -regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_CSA_ADDR_HI = 0x0915 # macro -regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_SCHEDULE_CNTL = 0x0916 # macro -regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_IB_SUB_REMAIN = 0x0917 # macro -regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_PREEMPT = 0x0918 # macro -regSDMA1_QUEUE7_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_DUMMY_REG = 0x0919 # macro -regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x091a # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x091b # macro -regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_AQL_CNTL = 0x091c # macro -regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MINOR_PTR_UPDATE = 0x091d # macro -regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_RB_PREEMPT = 0x091e # macro -regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA0 = 0x0928 # macro -regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA1 = 0x0929 # macro -regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA2 = 0x092a # macro -regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA3 = 0x092b # macro -regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA4 = 0x092c # macro -regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA5 = 0x092d # macro -regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA6 = 0x092e # macro -regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA7 = 0x092f # macro -regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA8 = 0x0930 # macro -regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA9 = 0x0931 # macro -regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_DATA10 = 0x0932 # macro -regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 # macro -regSDMA1_QUEUE7_MIDCMD_CNTL = 0x0933 # macro -regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 # macro -regSDMA0_UCODE_ADDR = 0x5880 # macro -regSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA0_UCODE_DATA = 0x5881 # macro -regSDMA0_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA0_UCODE_SELFLOAD_CONTROL = 0x5882 # macro -regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro -regSDMA0_BROADCAST_UCODE_ADDR = 0x5886 # macro -regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA0_BROADCAST_UCODE_DATA = 0x5887 # macro -regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA0_F32_CNTL = 0x589a # macro -regSDMA0_F32_CNTL_BASE_IDX = 1 # macro -regSDMA1_UCODE_ADDR = 0x58a0 # macro -regSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA1_UCODE_DATA = 0x58a1 # macro -regSDMA1_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA1_UCODE_SELFLOAD_CONTROL = 0x58a2 # macro -regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 # macro -regSDMA1_BROADCAST_UCODE_ADDR = 0x58a6 # macro -regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro -regSDMA1_BROADCAST_UCODE_DATA = 0x58a7 # macro -regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro -regSDMA1_F32_CNTL = 0x58ba # macro -regSDMA1_F32_CNTL_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro -regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro -regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro -regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro -regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro -regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro -regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro -regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro -regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro -regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro -regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro -regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro -regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro -regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro -regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro -regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro -regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro -regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro -regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_LO = 0x3662 # macro -regSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER0_HI = 0x3663 # macro -regSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_LO = 0x3664 # macro -regSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSDMA0_PERFCOUNTER1_HI = 0x3665 # macro -regSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro -regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro -regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_LO = 0x366e # macro -regSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER0_HI = 0x366f # macro -regSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_LO = 0x3670 # macro -regSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSDMA1_PERFCOUNTER1_HI = 0x3671 # macro -regSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGRBM_CNTL = 0x0da0 # macro -regGRBM_CNTL_BASE_IDX = 0 # macro -regGRBM_SKEW_CNTL = 0x0da1 # macro -regGRBM_SKEW_CNTL_BASE_IDX = 0 # macro -regGRBM_STATUS2 = 0x0da2 # macro -regGRBM_STATUS2_BASE_IDX = 0 # macro -regGRBM_PWR_CNTL = 0x0da3 # macro -regGRBM_PWR_CNTL_BASE_IDX = 0 # macro -regGRBM_STATUS = 0x0da4 # macro -regGRBM_STATUS_BASE_IDX = 0 # macro -regGRBM_STATUS_SE0 = 0x0da5 # macro -regGRBM_STATUS_SE0_BASE_IDX = 0 # macro -regGRBM_STATUS_SE1 = 0x0da6 # macro -regGRBM_STATUS_SE1_BASE_IDX = 0 # macro -regGRBM_STATUS3 = 0x0da7 # macro -regGRBM_STATUS3_BASE_IDX = 0 # macro -regGRBM_SOFT_RESET = 0x0da8 # macro -regGRBM_SOFT_RESET_BASE_IDX = 0 # macro -regGRBM_GFX_CLKEN_CNTL = 0x0dac # macro -regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro -regGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro -regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro -regGRBM_STATUS_SE2 = 0x0dae # macro -regGRBM_STATUS_SE2_BASE_IDX = 0 # macro -regGRBM_STATUS_SE3 = 0x0daf # macro -regGRBM_STATUS_SE3_BASE_IDX = 0 # macro -regGRBM_STATUS_SE4 = 0x0db0 # macro -regGRBM_STATUS_SE4_BASE_IDX = 0 # macro -regGRBM_STATUS_SE5 = 0x0db1 # macro -regGRBM_STATUS_SE5_BASE_IDX = 0 # macro -regGRBM_READ_ERROR = 0x0db6 # macro -regGRBM_READ_ERROR_BASE_IDX = 0 # macro -regGRBM_READ_ERROR2 = 0x0db7 # macro -regGRBM_READ_ERROR2_BASE_IDX = 0 # macro -regGRBM_INT_CNTL = 0x0db8 # macro -regGRBM_INT_CNTL_BASE_IDX = 0 # macro -regGRBM_TRAP_OP = 0x0db9 # macro -regGRBM_TRAP_OP_BASE_IDX = 0 # macro -regGRBM_TRAP_ADDR = 0x0dba # macro -regGRBM_TRAP_ADDR_BASE_IDX = 0 # macro -regGRBM_TRAP_ADDR_MSK = 0x0dbb # macro -regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro -regGRBM_TRAP_WD = 0x0dbc # macro -regGRBM_TRAP_WD_BASE_IDX = 0 # macro -regGRBM_TRAP_WD_MSK = 0x0dbd # macro -regGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro -regGRBM_DSM_BYPASS = 0x0dbe # macro -regGRBM_DSM_BYPASS_BASE_IDX = 0 # macro -regGRBM_WRITE_ERROR = 0x0dbf # macro -regGRBM_WRITE_ERROR_BASE_IDX = 0 # macro -regGRBM_CHIP_REVISION = 0x0dc1 # macro -regGRBM_CHIP_REVISION_BASE_IDX = 0 # macro -regGRBM_IH_CREDIT = 0x0dc4 # macro -regGRBM_IH_CREDIT_BASE_IDX = 0 # macro -regGRBM_PWR_CNTL2 = 0x0dc5 # macro -regGRBM_PWR_CNTL2_BASE_IDX = 0 # macro -regGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro -regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro -regGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro -regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro -regGRBM_INVALID_PIPE = 0x0dc9 # macro -regGRBM_INVALID_PIPE_BASE_IDX = 0 # macro -regGRBM_FENCE_RANGE0 = 0x0dca # macro -regGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro -regGRBM_FENCE_RANGE1 = 0x0dcb # macro -regGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG0 = 0x0de0 # macro -regGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG1 = 0x0de1 # macro -regGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG2 = 0x0de2 # macro -regGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG3 = 0x0de3 # macro -regGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG4 = 0x0de4 # macro -regGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG5 = 0x0de5 # macro -regGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG6 = 0x0de6 # macro -regGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro -regGRBM_SCRATCH_REG7 = 0x0de7 # macro -regGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro -regVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro -regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro -regCP_CPC_DEBUG_CNTL = 0x0e20 # macro -regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 # macro -regCP_CPC_DEBUG_DATA = 0x0e21 # macro -regCP_CPC_DEBUG_DATA_BASE_IDX = 0 # macro -regCP_CPC_STATUS = 0x0e24 # macro -regCP_CPC_STATUS_BASE_IDX = 0 # macro -regCP_CPC_BUSY_STAT = 0x0e25 # macro -regCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro -regCP_CPC_STALLED_STAT1 = 0x0e26 # macro -regCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro -regCP_CPF_STATUS = 0x0e27 # macro -regCP_CPF_STATUS_BASE_IDX = 0 # macro -regCP_CPF_BUSY_STAT = 0x0e28 # macro -regCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro -regCP_CPF_STALLED_STAT1 = 0x0e29 # macro -regCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro -regCP_CPC_BUSY_STAT2 = 0x0e2a # macro -regCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro -regCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro -regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -regCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro -regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro -regCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro -regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro -regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_CPC_SCRATCH_INDEX = 0x0e30 # macro -regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro -regCP_CPC_SCRATCH_DATA = 0x0e31 # macro -regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro -regCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro -regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -regCP_CPF_BUSY_STAT2 = 0x0e33 # macro -regCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro -regCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro -regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro -regCP_STALLED_STAT3 = 0x0f3c # macro -regCP_STALLED_STAT3_BASE_IDX = 0 # macro -regCP_STALLED_STAT1 = 0x0f3d # macro -regCP_STALLED_STAT1_BASE_IDX = 0 # macro -regCP_STALLED_STAT2 = 0x0f3e # macro -regCP_STALLED_STAT2_BASE_IDX = 0 # macro -regCP_BUSY_STAT = 0x0f3f # macro -regCP_BUSY_STAT_BASE_IDX = 0 # macro -regCP_STAT = 0x0f40 # macro -regCP_STAT_BASE_IDX = 0 # macro -regCP_ME_HEADER_DUMP = 0x0f41 # macro -regCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_PFP_HEADER_DUMP = 0x0f42 # macro -regCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro -regCP_GRBM_FREE_COUNT = 0x0f43 # macro -regCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro -regCP_PFP_INSTR_PNTR = 0x0f45 # macro -regCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_ME_INSTR_PNTR = 0x0f46 # macro -regCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_MEC1_INSTR_PNTR = 0x0f48 # macro -regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_MEC2_INSTR_PNTR = 0x0f49 # macro -regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro -regCP_CSF_STAT = 0x0f54 # macro -regCP_CSF_STAT_BASE_IDX = 0 # macro -regCP_CNTX_STAT = 0x0f58 # macro -regCP_CNTX_STAT_BASE_IDX = 0 # macro -regCP_ME_PREEMPTION = 0x0f59 # macro -regCP_ME_PREEMPTION_BASE_IDX = 0 # macro -regCP_RB1_RPTR = 0x0f5f # macro -regCP_RB1_RPTR_BASE_IDX = 0 # macro -regCP_RB0_RPTR = 0x0f60 # macro -regCP_RB0_RPTR_BASE_IDX = 0 # macro -regCP_RB_RPTR = 0x0f60 # macro -regCP_RB_RPTR_BASE_IDX = 0 # macro -regCP_RB_WPTR_DELAY = 0x0f61 # macro -regCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro -regCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro -regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -regCP_ROQ1_THRESHOLDS = 0x0f75 # macro -regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro -regCP_ROQ2_THRESHOLDS = 0x0f76 # macro -regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro -regCP_STQ_THRESHOLDS = 0x0f77 # macro -regCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro -regCP_MEQ_THRESHOLDS = 0x0f79 # macro -regCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro -regCP_ROQ_AVAIL = 0x0f7a # macro -regCP_ROQ_AVAIL_BASE_IDX = 0 # macro -regCP_STQ_AVAIL = 0x0f7b # macro -regCP_STQ_AVAIL_BASE_IDX = 0 # macro -regCP_ROQ2_AVAIL = 0x0f7c # macro -regCP_ROQ2_AVAIL_BASE_IDX = 0 # macro -regCP_MEQ_AVAIL = 0x0f7d # macro -regCP_MEQ_AVAIL_BASE_IDX = 0 # macro -regCP_CMD_INDEX = 0x0f7e # macro -regCP_CMD_INDEX_BASE_IDX = 0 # macro -regCP_CMD_DATA = 0x0f7f # macro -regCP_CMD_DATA_BASE_IDX = 0 # macro -regCP_ROQ_RB_STAT = 0x0f80 # macro -regCP_ROQ_RB_STAT_BASE_IDX = 0 # macro -regCP_ROQ_IB1_STAT = 0x0f81 # macro -regCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro -regCP_ROQ_IB2_STAT = 0x0f82 # macro -regCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro -regCP_STQ_STAT = 0x0f83 # macro -regCP_STQ_STAT_BASE_IDX = 0 # macro -regCP_STQ_WR_STAT = 0x0f84 # macro -regCP_STQ_WR_STAT_BASE_IDX = 0 # macro -regCP_MEQ_STAT = 0x0f85 # macro -regCP_MEQ_STAT_BASE_IDX = 0 # macro -regCP_ROQ3_THRESHOLDS = 0x0f8c # macro -regCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro -regCP_ROQ_DB_STAT = 0x0f8d # macro -regCP_ROQ_DB_STAT_BASE_IDX = 0 # macro -regCP_DEBUG_CNTL = 0x0f98 # macro -regCP_DEBUG_CNTL_BASE_IDX = 0 # macro -regCP_DEBUG_DATA = 0x0f99 # macro -regCP_DEBUG_DATA_BASE_IDX = 0 # macro -regCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro -regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro -regVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro -regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro -regVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro -regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro -regVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro -regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro -regVGT_MC_LAT_CNTL = 0x0fd6 # macro -regVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro -regIA_UTCL1_STATUS_2 = 0x0fd7 # macro -regIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro -regWD_CNTL_STATUS = 0x0fdf # macro -regWD_CNTL_STATUS_BASE_IDX = 0 # macro -regCC_GC_PRIM_CONFIG = 0x0fe0 # macro -regCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro -regWD_QOS = 0x0fe2 # macro -regWD_QOS_BASE_IDX = 0 # macro -regWD_UTCL1_CNTL = 0x0fe3 # macro -regWD_UTCL1_CNTL_BASE_IDX = 0 # macro -regWD_UTCL1_STATUS = 0x0fe4 # macro -regWD_UTCL1_STATUS_BASE_IDX = 0 # macro -regIA_UTCL1_CNTL = 0x0fe6 # macro -regIA_UTCL1_CNTL_BASE_IDX = 0 # macro -regIA_UTCL1_STATUS = 0x0fe7 # macro -regIA_UTCL1_STATUS_BASE_IDX = 0 # macro -regCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro -regCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro -regGE_RATE_CNTL_1 = 0x0ff4 # macro -regGE_RATE_CNTL_1_BASE_IDX = 0 # macro -regGE_RATE_CNTL_2 = 0x0ff5 # macro -regGE_RATE_CNTL_2_BASE_IDX = 0 # macro -regVGT_SYS_CONFIG = 0x1003 # macro -regVGT_SYS_CONFIG_BASE_IDX = 0 # macro -regGE_PRIV_CONTROL = 0x1004 # macro -regGE_PRIV_CONTROL_BASE_IDX = 0 # macro -regGE_STATUS = 0x1005 # macro -regGE_STATUS_BASE_IDX = 0 # macro -regVGT_GS_MAX_WAVE_ID = 0x1009 # macro -regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro -regGFX_PIPE_CONTROL = 0x100d # macro -regGFX_PIPE_CONTROL_BASE_IDX = 0 # macro -regCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro -regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro -regGE2_SE_CNTL_STATUS = 0x1011 # macro -regGE2_SE_CNTL_STATUS_BASE_IDX = 0 # macro -regGE_SPI_IF_SAFE_REG = 0x1018 # macro -regGE_SPI_IF_SAFE_REG_BASE_IDX = 0 # macro -regGE_PA_IF_SAFE_REG = 0x1019 # macro -regGE_PA_IF_SAFE_REG_BASE_IDX = 0 # macro -regPA_CL_CNTL_STATUS = 0x1024 # macro -regPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro -regPA_CL_ENHANCE = 0x1025 # macro -regPA_CL_ENHANCE_BASE_IDX = 0 # macro -regPA_SU_CNTL_STATUS = 0x1034 # macro -regPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro -regPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro -regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro -regSQ_CONFIG = 0x10a0 # macro -regSQ_CONFIG_BASE_IDX = 0 # macro -regSQC_CONFIG = 0x10a1 # macro -regSQC_CONFIG_BASE_IDX = 0 # macro -regLDS_CONFIG = 0x10a2 # macro -regLDS_CONFIG_BASE_IDX = 0 # macro -regSQ_RANDOM_WAVE_PRI = 0x10a3 # macro -regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro -regSQG_STATUS = 0x10a4 # macro -regSQG_STATUS_BASE_IDX = 0 # macro -regSQ_FIFO_SIZES = 0x10a5 # macro -regSQ_FIFO_SIZES_BASE_IDX = 0 # macro -regSQ_DSM_CNTL = 0x10a6 # macro -regSQ_DSM_CNTL_BASE_IDX = 0 # macro -regSQ_DSM_CNTL2 = 0x10a7 # macro -regSQ_DSM_CNTL2_BASE_IDX = 0 # macro -regSP_CONFIG = 0x10ab # macro -regSP_CONFIG_BASE_IDX = 0 # macro -regSQ_ARB_CONFIG = 0x10ac # macro -regSQ_ARB_CONFIG_BASE_IDX = 0 # macro -regSQ_DEBUG_HOST_TRAP_STATUS = 0x10b6 # macro -regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX = 0 # macro -regSQG_GL1H_STATUS = 0x10b9 # macro -regSQG_GL1H_STATUS_BASE_IDX = 0 # macro -regSQG_CONFIG = 0x10ba # macro -regSQG_CONFIG_BASE_IDX = 0 # macro -regSQ_PERF_SNAPSHOT_CTRL = 0x10bb # macro -regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 # macro -regCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro -regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro -regSQ_INTERRUPT_AUTO_MASK = 0x10be # macro -regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro -regSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro -regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro -regSQ_WATCH0_ADDR_H = 0x10d0 # macro -regSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH0_ADDR_L = 0x10d1 # macro -regSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH0_CNTL = 0x10d2 # macro -regSQ_WATCH0_CNTL_BASE_IDX = 0 # macro -regSQ_WATCH1_ADDR_H = 0x10d3 # macro -regSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH1_ADDR_L = 0x10d4 # macro -regSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH1_CNTL = 0x10d5 # macro -regSQ_WATCH1_CNTL_BASE_IDX = 0 # macro -regSQ_WATCH2_ADDR_H = 0x10d6 # macro -regSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH2_ADDR_L = 0x10d7 # macro -regSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH2_CNTL = 0x10d8 # macro -regSQ_WATCH2_CNTL_BASE_IDX = 0 # macro -regSQ_WATCH3_ADDR_H = 0x10d9 # macro -regSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro -regSQ_WATCH3_ADDR_L = 0x10da # macro -regSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro -regSQ_WATCH3_CNTL = 0x10db # macro -regSQ_WATCH3_CNTL_BASE_IDX = 0 # macro -regSQ_IND_INDEX = 0x1118 # macro -regSQ_IND_INDEX_BASE_IDX = 0 # macro -regSQ_IND_DATA = 0x1119 # macro -regSQ_IND_DATA_BASE_IDX = 0 # macro -regSQ_CMD = 0x111b # macro -regSQ_CMD_BASE_IDX = 0 # macro -regSX_DEBUG_1 = 0x11b8 # macro -regSX_DEBUG_1_BASE_IDX = 0 # macro -regSPI_PS_MAX_WAVE_ID = 0x11da # macro -regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro -regSPI_GFX_CNTL = 0x11dc # macro -regSPI_GFX_CNTL_BASE_IDX = 0 # macro -regSPI_DSM_CNTL = 0x11e3 # macro -regSPI_DSM_CNTL_BASE_IDX = 0 # macro -regSPI_DSM_CNTL2 = 0x11e4 # macro -regSPI_DSM_CNTL2_BASE_IDX = 0 # macro -regSPI_EDC_CNT = 0x11e5 # macro -regSPI_EDC_CNT_BASE_IDX = 0 # macro -regSPI_CONFIG_PS_CU_EN = 0x11f2 # macro -regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_CNTL = 0x124a # macro -regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro -regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro -regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro -regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro -regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro -regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro -regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro -regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro -regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro -regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro -regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro -regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro -regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro -regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro -regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro -regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro -regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro -regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro -regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro -regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro -regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro -regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro -regSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro -regSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro -regSPI_LB_CTR_CTRL = 0x1274 # macro -regSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro -regSPI_LB_WGP_MASK = 0x1275 # macro -regSPI_LB_WGP_MASK_BASE_IDX = 0 # macro -regSPI_LB_DATA_REG = 0x1276 # macro -regSPI_LB_DATA_REG_BASE_IDX = 0 # macro -regSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro -regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro -regSPI_GDS_CREDITS = 0x1278 # macro -regSPI_GDS_CREDITS_BASE_IDX = 0 # macro -regSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro -regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro -regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro -regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro -regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro -regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro -regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro -regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro -regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro -regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro -regSPI_LB_DATA_WAVES = 0x1284 # macro -regSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro -regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro -regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro -regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro -regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro -regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro -regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro -regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro -regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro -regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro -regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro -regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro -regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro -regTD_STATUS = 0x12c6 # macro -regTD_STATUS_BASE_IDX = 0 # macro -regTD_DSM_CNTL = 0x12cf # macro -regTD_DSM_CNTL_BASE_IDX = 0 # macro -regTD_DSM_CNTL2 = 0x12d0 # macro -regTD_DSM_CNTL2_BASE_IDX = 0 # macro -regTD_SCRATCH = 0x12d3 # macro -regTD_SCRATCH_BASE_IDX = 0 # macro -regTA_CNTL = 0x12e1 # macro -regTA_CNTL_BASE_IDX = 0 # macro -regTA_CNTL_AUX = 0x12e2 # macro -regTA_CNTL_AUX_BASE_IDX = 0 # macro -regTA_CNTL2 = 0x12e5 # macro -regTA_CNTL2_BASE_IDX = 0 # macro -regTA_STATUS = 0x12e8 # macro -regTA_STATUS_BASE_IDX = 0 # macro -regTA_SCRATCH = 0x1304 # macro -regTA_SCRATCH_BASE_IDX = 0 # macro -regGDS_CONFIG = 0x1360 # macro -regGDS_CONFIG_BASE_IDX = 0 # macro -regGDS_CNTL_STATUS = 0x1361 # macro -regGDS_CNTL_STATUS_BASE_IDX = 0 # macro -regGDS_ENHANCE = 0x1362 # macro -regGDS_ENHANCE_BASE_IDX = 0 # macro -regGDS_PROTECTION_FAULT = 0x1363 # macro -regGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro -regGDS_VM_PROTECTION_FAULT = 0x1364 # macro -regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro -regGDS_EDC_CNT = 0x1365 # macro -regGDS_EDC_CNT_BASE_IDX = 0 # macro -regGDS_EDC_GRBM_CNT = 0x1366 # macro -regGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro -regGDS_EDC_OA_DED = 0x1367 # macro -regGDS_EDC_OA_DED_BASE_IDX = 0 # macro -regGDS_DSM_CNTL = 0x136a # macro -regGDS_DSM_CNTL_BASE_IDX = 0 # macro -regGDS_EDC_OA_PHY_CNT = 0x136b # macro -regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro -regGDS_EDC_OA_PIPE_CNT = 0x136c # macro -regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro -regGDS_DSM_CNTL2 = 0x136d # macro -regGDS_DSM_CNTL2_BASE_IDX = 0 # macro -regDB_DEBUG = 0x13ac # macro -regDB_DEBUG_BASE_IDX = 0 # macro -regDB_DEBUG2 = 0x13ad # macro -regDB_DEBUG2_BASE_IDX = 0 # macro -regDB_DEBUG3 = 0x13ae # macro -regDB_DEBUG3_BASE_IDX = 0 # macro -regDB_DEBUG4 = 0x13af # macro -regDB_DEBUG4_BASE_IDX = 0 # macro -regDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro -regDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro -regDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro -regDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro -regDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro -regDB_CREDIT_LIMIT = 0x13b4 # macro -regDB_CREDIT_LIMIT_BASE_IDX = 0 # macro -regDB_WATERMARKS = 0x13b5 # macro -regDB_WATERMARKS_BASE_IDX = 0 # macro -regDB_SUBTILE_CONTROL = 0x13b6 # macro -regDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro -regDB_FREE_CACHELINES = 0x13b7 # macro -regDB_FREE_CACHELINES_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH1 = 0x13b8 # macro -regDB_FIFO_DEPTH1_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH2 = 0x13b9 # macro -regDB_FIFO_DEPTH2_BASE_IDX = 0 # macro -regDB_LAST_OF_BURST_CONFIG = 0x13ba # macro -regDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro -regDB_RING_CONTROL = 0x13bb # macro -regDB_RING_CONTROL_BASE_IDX = 0 # macro -regDB_MEM_ARB_WATERMARKS = 0x13bc # macro -regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH3 = 0x13bd # macro -regDB_FIFO_DEPTH3_BASE_IDX = 0 # macro -regDB_DEBUG6 = 0x13be # macro -regDB_DEBUG6_BASE_IDX = 0 # macro -regDB_EXCEPTION_CONTROL = 0x13bf # macro -regDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro -regDB_DEBUG7 = 0x13d0 # macro -regDB_DEBUG7_BASE_IDX = 0 # macro -regDB_DEBUG5 = 0x13d1 # macro -regDB_DEBUG5_BASE_IDX = 0 # macro -regDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro -regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro -regDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro -regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro -regDB_FIFO_DEPTH4 = 0x13d9 # macro -regDB_FIFO_DEPTH4_BASE_IDX = 0 # macro -regCC_RB_REDUNDANCY = 0x13dc # macro -regCC_RB_REDUNDANCY_BASE_IDX = 0 # macro -regCC_RB_BACKEND_DISABLE = 0x13dd # macro -regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro -regGB_ADDR_CONFIG = 0x13de # macro -regGB_ADDR_CONFIG_BASE_IDX = 0 # macro -regGB_BACKEND_MAP = 0x13df # macro -regGB_BACKEND_MAP_BASE_IDX = 0 # macro -regGB_GPU_ID = 0x13e0 # macro -regGB_GPU_ID_BASE_IDX = 0 # macro -regCC_RB_DAISY_CHAIN = 0x13e1 # macro -regCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro -regGB_ADDR_CONFIG_READ = 0x13e2 # macro -regGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro -regCB_HW_CONTROL_4 = 0x1422 # macro -regCB_HW_CONTROL_4_BASE_IDX = 0 # macro -regCB_HW_CONTROL_3 = 0x1423 # macro -regCB_HW_CONTROL_3_BASE_IDX = 0 # macro -regCB_HW_CONTROL = 0x1424 # macro -regCB_HW_CONTROL_BASE_IDX = 0 # macro -regCB_HW_CONTROL_1 = 0x1425 # macro -regCB_HW_CONTROL_1_BASE_IDX = 0 # macro -regCB_HW_CONTROL_2 = 0x1426 # macro -regCB_HW_CONTROL_2_BASE_IDX = 0 # macro -regCB_DCC_CONFIG = 0x1427 # macro -regCB_DCC_CONFIG_BASE_IDX = 0 # macro -regCB_HW_MEM_ARBITER_RD = 0x1428 # macro -regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro -regCB_HW_MEM_ARBITER_WR = 0x1429 # macro -regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro -regCB_FGCG_SRAM_OVERRIDE = 0x142a # macro -regCB_FGCG_SRAM_OVERRIDE_BASE_IDX = 0 # macro -regCB_DCC_CONFIG2 = 0x142b # macro -regCB_DCC_CONFIG2_BASE_IDX = 0 # macro -regCHICKEN_BITS = 0x142d # macro -regCHICKEN_BITS_BASE_IDX = 0 # macro -regCB_CACHE_EVICT_POINTS = 0x142e # macro -regCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro -regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro -regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro -regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro -regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_LAZY = 0x17a6 # macro -regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_LAZY = 0x17a7 # macro -regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro -regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro -regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro -regGCEA_DRAM_PAGE_BURST = 0x17aa # macro -regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro -regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro -regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro -regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro -regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro -regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro -regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro -regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro -regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro -regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro -regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro -regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro -regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro -regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro -regGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro -regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro -regGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro -regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro -regGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro -regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro -regGCEA_IO_GROUP_BURST = 0x1883 # macro -regGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_AGE = 0x1884 # macro -regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_AGE = 0x1885 # macro -regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro -regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro -regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_FIXED = 0x1888 # macro -regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_FIXED = 0x1889 # macro -regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_URGENCY = 0x188a # macro -regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_URGENCY = 0x188b # macro -regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro -regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro -regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro -regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro -regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro -regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro -regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro -regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro -regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro -regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro -regGCEA_SDP_ARB_FINAL = 0x1896 # macro -regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 # macro -regGCEA_SDP_IO_PRIORITY = 0x1899 # macro -regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 # macro -regGCEA_SDP_CREDITS = 0x189a # macro -regGCEA_SDP_CREDITS_BASE_IDX = 0 # macro -regGCEA_SDP_TAG_RESERVE0 = 0x189b # macro -regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro -regGCEA_SDP_TAG_RESERVE1 = 0x189c # macro -regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro -regGCEA_SDP_VCC_RESERVE0 = 0x189d # macro -regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro -regGCEA_SDP_VCC_RESERVE1 = 0x189e # macro -regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro -regGCEA_MISC = 0x14a2 # macro -regGCEA_MISC_BASE_IDX = 0 # macro -regGCEA_LATENCY_SAMPLING = 0x14a3 # macro -regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro -regGCEA_MAM_CTRL2 = 0x14a9 # macro -regGCEA_MAM_CTRL2_BASE_IDX = 0 # macro -regGCEA_MAM_CTRL = 0x14ab # macro -regGCEA_MAM_CTRL_BASE_IDX = 0 # macro -regGCEA_EDC_CNT = 0x14b2 # macro -regGCEA_EDC_CNT_BASE_IDX = 0 # macro -regGCEA_EDC_CNT2 = 0x14b3 # macro -regGCEA_EDC_CNT2_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL = 0x14b4 # macro -regGCEA_DSM_CNTL_BASE_IDX = 0 # macro -regGCEA_DSM_CNTLA = 0x14b5 # macro -regGCEA_DSM_CNTLA_BASE_IDX = 0 # macro -regGCEA_DSM_CNTLB = 0x14b6 # macro -regGCEA_DSM_CNTLB_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL2 = 0x14b7 # macro -regGCEA_DSM_CNTL2_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL2A = 0x14b8 # macro -regGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro -regGCEA_DSM_CNTL2B = 0x14b9 # macro -regGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro -regGCEA_GL2C_XBR_CREDITS = 0x14ba # macro -regGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro -regGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro -regGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro -regGCEA_PROBE_CNTL = 0x14bc # macro -regGCEA_PROBE_CNTL_BASE_IDX = 0 # macro -regGCEA_PROBE_MAP = 0x14bd # macro -regGCEA_PROBE_MAP_BASE_IDX = 0 # macro -regGCEA_ERR_STATUS = 0x14be # macro -regGCEA_ERR_STATUS_BASE_IDX = 0 # macro -regGCEA_MISC2 = 0x14bf # macro -regGCEA_MISC2_BASE_IDX = 0 # macro -regGCEA_RRET_MEM_RESERVE = 0x1518 # macro -regGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro -regGCEA_EDC_CNT3 = 0x151a # macro -regGCEA_EDC_CNT3_BASE_IDX = 0 # macro -regGCEA_SDP_ENABLE = 0x151e # macro -regGCEA_SDP_ENABLE_BASE_IDX = 0 # macro -regSPI_PQEV_CTRL = 0x14c0 # macro -regSPI_PQEV_CTRL_BASE_IDX = 0 # macro -regSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro -regSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro -regRMI_GENERAL_CNTL = 0x1880 # macro -regRMI_GENERAL_CNTL_BASE_IDX = 1 # macro -regRMI_GENERAL_CNTL1 = 0x1881 # macro -regRMI_GENERAL_CNTL1_BASE_IDX = 1 # macro -regRMI_GENERAL_STATUS = 0x1882 # macro -regRMI_GENERAL_STATUS_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS0 = 0x1883 # macro -regRMI_SUBBLOCK_STATUS0_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS1 = 0x1884 # macro -regRMI_SUBBLOCK_STATUS1_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS2 = 0x1885 # macro -regRMI_SUBBLOCK_STATUS2_BASE_IDX = 1 # macro -regRMI_SUBBLOCK_STATUS3 = 0x1886 # macro -regRMI_SUBBLOCK_STATUS3_BASE_IDX = 1 # macro -regRMI_XBAR_CONFIG = 0x1887 # macro -regRMI_XBAR_CONFIG_BASE_IDX = 1 # macro -regRMI_PROBE_POP_LOGIC_CNTL = 0x1888 # macro -regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 1 # macro -regRMI_UTC_XNACK_N_MISC_CNTL = 0x1889 # macro -regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 1 # macro -regRMI_DEMUX_CNTL = 0x188a # macro -regRMI_DEMUX_CNTL_BASE_IDX = 1 # macro -regRMI_UTCL1_CNTL1 = 0x188b # macro -regRMI_UTCL1_CNTL1_BASE_IDX = 1 # macro -regRMI_UTCL1_CNTL2 = 0x188c # macro -regRMI_UTCL1_CNTL2_BASE_IDX = 1 # macro -regRMI_UTC_UNIT_CONFIG = 0x188d # macro -regRMI_UTC_UNIT_CONFIG_BASE_IDX = 1 # macro -regRMI_TCIW_FORMATTER0_CNTL = 0x188e # macro -regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 1 # macro -regRMI_TCIW_FORMATTER1_CNTL = 0x188f # macro -regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_CNTL = 0x1890 # macro -regRMI_SCOREBOARD_CNTL_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_STATUS0 = 0x1891 # macro -regRMI_SCOREBOARD_STATUS0_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_STATUS1 = 0x1892 # macro -regRMI_SCOREBOARD_STATUS1_BASE_IDX = 1 # macro -regRMI_SCOREBOARD_STATUS2 = 0x1893 # macro -regRMI_SCOREBOARD_STATUS2_BASE_IDX = 1 # macro -regRMI_XBAR_ARBITER_CONFIG = 0x1894 # macro -regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 1 # macro -regRMI_XBAR_ARBITER_CONFIG_1 = 0x1895 # macro -regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 1 # macro -regRMI_CLOCK_CNTRL = 0x1896 # macro -regRMI_CLOCK_CNTRL_BASE_IDX = 1 # macro -regRMI_UTCL1_STATUS = 0x1897 # macro -regRMI_UTCL1_STATUS_BASE_IDX = 1 # macro -regRMI_RB_GLX_CID_MAP = 0x1898 # macro -regRMI_RB_GLX_CID_MAP_BASE_IDX = 1 # macro -regRMI_SPARE = 0x189f # macro -regRMI_SPARE_BASE_IDX = 1 # macro -regRMI_SPARE_1 = 0x18a0 # macro -regRMI_SPARE_1_BASE_IDX = 1 # macro -regRMI_SPARE_2 = 0x18a1 # macro -regRMI_SPARE_2_BASE_IDX = 1 # macro -regCC_RMI_REDUNDANCY = 0x18a2 # macro -regCC_RMI_REDUNDANCY_BASE_IDX = 1 # macro -regGCR_PIO_CNTL = 0x1580 # macro -regGCR_PIO_CNTL_BASE_IDX = 0 # macro -regGCR_PIO_DATA = 0x1581 # macro -regGCR_PIO_DATA_BASE_IDX = 0 # macro -regPMM_CNTL = 0x1582 # macro -regPMM_CNTL_BASE_IDX = 0 # macro -regPMM_STATUS = 0x1583 # macro -regPMM_STATUS_BASE_IDX = 0 # macro -regUTCL1_CTRL_1 = 0x158c # macro -regUTCL1_CTRL_1_BASE_IDX = 0 # macro -regUTCL1_ALOG = 0x158f # macro -regUTCL1_ALOG_BASE_IDX = 0 # macro -regUTCL1_STATUS = 0x1594 # macro -regUTCL1_STATUS_BASE_IDX = 0 # macro -regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x15a4 # macro -regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro -regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x15a5 # macro -regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro -regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x15a6 # macro -regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro -regGCMC_VM_FB_OFFSET = 0x15a7 # macro -regGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x15a8 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x15a9 # macro -regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro -regGCMC_VM_STEERING = 0x15aa # macro -regGCMC_VM_STEERING_BASE_IDX = 0 # macro -regGCMC_MEM_POWER_LS = 0x15ac # macro -regGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x15ad # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x15ae # macro -regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x15af # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x15b0 # macro -regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro -regGCMC_VM_APT_CNTL = 0x15b1 # macro -regGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_START = 0x15b2 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_END = 0x15b3 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x15b4 # macro -regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro -regGCUTCL2_ICG_CTRL = 0x15b5 # macro -regGCUTCL2_ICG_CTRL_BASE_IDX = 0 # macro -regGCUTCL2_CGTT_BUSY_CTRL = 0x15b7 # macro -regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro -regGCMC_VM_FB_NOALLOC_CNTL = 0x15b8 # macro -regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro -regGCUTCL2_HARVEST_BYPASS_GROUPS = 0x15b9 # macro -regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro -regGCUTCL2_GROUP_RET_FAULT_STATUS = 0x15bb # macro -regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro -regGCVM_L2_CNTL = 0x15bc # macro -regGCVM_L2_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_CNTL2 = 0x15bd # macro -regGCVM_L2_CNTL2_BASE_IDX = 0 # macro -regGCVM_L2_CNTL3 = 0x15be # macro -regGCVM_L2_CNTL3_BASE_IDX = 0 # macro -regGCVM_L2_STATUS = 0x15bf # macro -regGCVM_L2_STATUS_BASE_IDX = 0 # macro -regGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro -regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro -regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_CNTL = 0x15c3 # macro -regGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro -regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro -regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro -regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro -regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro -regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro -regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro -regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro -regGCVM_L2_CNTL4 = 0x15d4 # macro -regGCVM_L2_CNTL4_BASE_IDX = 0 # macro -regGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro -regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro -regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro -regGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro -regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_ICG_CTRL = 0x15d9 # macro -regGCVM_L2_ICG_CTRL_BASE_IDX = 0 # macro -regGCVM_L2_CNTL5 = 0x15da # macro -regGCVM_L2_CNTL5_BASE_IDX = 0 # macro -regGCVM_L2_GCR_CNTL = 0x15db # macro -regGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro -regGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15dc # macro -regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro -regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15dd # macro -regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro -regGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15de # macro -regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro -regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15df # macro -regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro -regGCVM_L2_CGTT_BUSY_CTRL = 0x15e0 # macro -regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro -regGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e1 # macro -regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro -regGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e2 # macro -regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x15e5 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x15e6 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x15e7 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x15e8 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro -regGCVM_L2_BANK_SELECT_MASKS = 0x15e9 # macro -regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x15ea # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x15eb # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x15ec # macro -regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro -regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x15ed # macro -regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro -regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x15ee # macro -regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro -regGCMC_VM_FB_LOCATION_BASE = 0x1678 # macro -regGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro -regGCMC_VM_FB_LOCATION_TOP = 0x1679 # macro -regGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro -regGCMC_VM_AGP_TOP = 0x167a # macro -regGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro -regGCMC_VM_AGP_BOT = 0x167b # macro -regGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro -regGCMC_VM_AGP_BASE = 0x167c # macro -regGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x167d # macro -regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro -regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x167e # macro -regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro -regGCMC_VM_MX_L1_TLB_CNTL = 0x167f # macro -regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_CNTL = 0x1688 # macro -regGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_CNTL = 0x1689 # macro -regGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_CNTL = 0x168a # macro -regGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_CNTL = 0x168b # macro -regGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_CNTL = 0x168c # macro -regGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_CNTL = 0x168d # macro -regGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_CNTL = 0x168e # macro -regGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_CNTL = 0x168f # macro -regGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_CNTL = 0x1690 # macro -regGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_CNTL = 0x1691 # macro -regGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_CNTL = 0x1692 # macro -regGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_CNTL = 0x1693 # macro -regGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_CNTL = 0x1694 # macro -regGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_CNTL = 0x1695 # macro -regGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_CNTL = 0x1696 # macro -regGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_CNTL = 0x1697 # macro -regGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro -regGCVM_CONTEXTS_DISABLE = 0x1698 # macro -regGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_SEM = 0x1699 # macro -regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_SEM = 0x169a # macro -regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_SEM = 0x169b # macro -regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_SEM = 0x169c # macro -regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_SEM = 0x169d # macro -regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_SEM = 0x169e # macro -regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_SEM = 0x169f # macro -regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_SEM = 0x16a0 # macro -regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_SEM = 0x16a1 # macro -regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_SEM = 0x16a2 # macro -regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_SEM = 0x16a3 # macro -regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_SEM = 0x16a4 # macro -regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_SEM = 0x16a5 # macro -regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_SEM = 0x16a6 # macro -regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_SEM = 0x16a7 # macro -regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_SEM = 0x16a8 # macro -regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_SEM = 0x16a9 # macro -regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_SEM = 0x16aa # macro -regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_REQ = 0x16ab # macro -regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_REQ = 0x16ac # macro -regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_REQ = 0x16ad # macro -regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_REQ = 0x16ae # macro -regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_REQ = 0x16af # macro -regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_REQ = 0x16b0 # macro -regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_REQ = 0x16b1 # macro -regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_REQ = 0x16b2 # macro -regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_REQ = 0x16b3 # macro -regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_REQ = 0x16b4 # macro -regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_REQ = 0x16b5 # macro -regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_REQ = 0x16b6 # macro -regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_REQ = 0x16b7 # macro -regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_REQ = 0x16b8 # macro -regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_REQ = 0x16b9 # macro -regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_REQ = 0x16ba # macro -regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_REQ = 0x16bb # macro -regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_REQ = 0x16bc # macro -regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_ACK = 0x16bd # macro -regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_ACK = 0x16be # macro -regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_ACK = 0x16bf # macro -regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_ACK = 0x16c0 # macro -regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_ACK = 0x16c1 # macro -regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_ACK = 0x16c2 # macro -regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_ACK = 0x16c3 # macro -regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_ACK = 0x16c4 # macro -regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_ACK = 0x16c5 # macro -regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_ACK = 0x16c6 # macro -regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_ACK = 0x16c7 # macro -regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_ACK = 0x16c8 # macro -regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_ACK = 0x16c9 # macro -regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_ACK = 0x16ca # macro -regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_ACK = 0x16cb # macro -regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_ACK = 0x16cc # macro -regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_ACK = 0x16cd # macro -regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_ACK = 0x16ce # macro -regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x16cf # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x16d0 # macro -regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x16d1 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x16d2 # macro -regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x16d3 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x16d4 # macro -regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x16d5 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x16d6 # macro -regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x16d7 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x16d8 # macro -regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x16d9 # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x16da # macro -regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x16db # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x16dc # macro -regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x16dd # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x16de # macro -regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x16df # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x16e0 # macro -regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x16e1 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x16e2 # macro -regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x16e3 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x16e4 # macro -regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x16e5 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x16e6 # macro -regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x16e7 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x16e8 # macro -regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x16e9 # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x16ea # macro -regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x16eb # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x16ec # macro -regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x16ed # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x16ee # macro -regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x16ef # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x16f0 # macro -regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x16f1 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x16f2 # macro -regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f3 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f4 # macro -regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f5 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f6 # macro -regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f7 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f8 # macro -regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f9 # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fa # macro -regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fb # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fc # macro -regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fd # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fe # macro -regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x16ff # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1700 # macro -regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1701 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1702 # macro -regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1703 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1704 # macro -regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1705 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x1706 # macro -regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x1707 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x1708 # macro -regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x1709 # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x170a # macro -regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x170b # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x170c # macro -regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x170d # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x170e # macro -regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x170f # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1710 # macro -regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1711 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1712 # macro -regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1713 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1714 # macro -regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1715 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x1716 # macro -regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x1717 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x1718 # macro -regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x1719 # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x171a # macro -regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x171b # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x171c # macro -regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x171d # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x171e # macro -regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x171f # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1720 # macro -regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1721 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1722 # macro -regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1723 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1724 # macro -regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1725 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x1726 # macro -regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x1727 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x1728 # macro -regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x1729 # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x172a # macro -regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x172b # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x172c # macro -regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x172d # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x172e # macro -regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x172f # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x1730 # macro -regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x1731 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x1732 # macro -regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x1733 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x1734 # macro -regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x1735 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x1736 # macro -regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x1737 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x1738 # macro -regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x1739 # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x173a # macro -regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x173b # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x173c # macro -regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x173d # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x173e # macro -regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x173f # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x1740 # macro -regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x1741 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x1742 # macro -regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x1743 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x1744 # macro -regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x1745 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x1746 # macro -regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x1747 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x1748 # macro -regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x1749 # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x174a # macro -regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x174b # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x174c # macro -regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x174d # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x174e # macro -regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x174f # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x1750 # macro -regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x1751 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x1752 # macro -regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro -regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1753 # macro -regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1754 # macro -regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1755 # macro -regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1756 # macro -regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1757 # macro -regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1758 # macro -regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1759 # macro -regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175a # macro -regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175b # macro -regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175c # macro -regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175d # macro -regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175e # macro -regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175f # macro -regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1760 # macro -regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1761 # macro -regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1762 # macro -regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1763 # macro -regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro -regGCVML2_PERFCOUNTER2_0_LO = 0x34e0 # macro -regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_LO = 0x34e1 # macro -regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_HI = 0x34e2 # macro -regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_HI = 0x34e3 # macro -regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER_LO = 0x34e4 # macro -regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER_HI = 0x34e5 # macro -regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER_LO = 0x34e6 # macro -regGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER_HI = 0x34e7 # macro -regGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_SELECT = 0x3d20 # macro -regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_SELECT = 0x3d21 # macro -regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d22 # macro -regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d23 # macro -regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_0_MODE = 0x3d24 # macro -regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro -regGCVML2_PERFCOUNTER2_1_MODE = 0x3d25 # macro -regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d30 # macro -regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d31 # macro -regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d32 # macro -regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d33 # macro -regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d34 # macro -regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d35 # macro -regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d36 # macro -regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d37 # macro -regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro -regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d38 # macro -regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER0_CFG = 0x3d39 # macro -regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER1_CFG = 0x3d3a # macro -regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER2_CFG = 0x3d3b # macro -regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER3_CFG = 0x3d3c # macro -regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro -regGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d3d # macro -regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro -regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro -regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro -regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro -regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro -regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro -regGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro -regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro -regGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5e41 # macro -regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x5e44 # macro -regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_0 = 0x5e48 # macro -regGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_1 = 0x5e49 # macro -regGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_2 = 0x5e4a # macro -regGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_3 = 0x5e4b # macro -regGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_4 = 0x5e4c # macro -regGCMC_VM_MARC_BASE_LO_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_5 = 0x5e4d # macro -regGCMC_VM_MARC_BASE_LO_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_6 = 0x5e4e # macro -regGCMC_VM_MARC_BASE_LO_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_7 = 0x5e4f # macro -regGCMC_VM_MARC_BASE_LO_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_8 = 0x5e50 # macro -regGCMC_VM_MARC_BASE_LO_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_9 = 0x5e51 # macro -regGCMC_VM_MARC_BASE_LO_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_10 = 0x5e52 # macro -regGCMC_VM_MARC_BASE_LO_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_11 = 0x5e53 # macro -regGCMC_VM_MARC_BASE_LO_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_12 = 0x5e54 # macro -regGCMC_VM_MARC_BASE_LO_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_13 = 0x5e55 # macro -regGCMC_VM_MARC_BASE_LO_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_14 = 0x5e56 # macro -regGCMC_VM_MARC_BASE_LO_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_LO_15 = 0x5e57 # macro -regGCMC_VM_MARC_BASE_LO_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_0 = 0x5e58 # macro -regGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_1 = 0x5e59 # macro -regGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_2 = 0x5e5a # macro -regGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_3 = 0x5e5b # macro -regGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_4 = 0x5e5c # macro -regGCMC_VM_MARC_BASE_HI_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_5 = 0x5e5d # macro -regGCMC_VM_MARC_BASE_HI_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_6 = 0x5e5e # macro -regGCMC_VM_MARC_BASE_HI_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_7 = 0x5e5f # macro -regGCMC_VM_MARC_BASE_HI_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_8 = 0x5e60 # macro -regGCMC_VM_MARC_BASE_HI_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_9 = 0x5e61 # macro -regGCMC_VM_MARC_BASE_HI_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_10 = 0x5e62 # macro -regGCMC_VM_MARC_BASE_HI_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_11 = 0x5e63 # macro -regGCMC_VM_MARC_BASE_HI_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_12 = 0x5e64 # macro -regGCMC_VM_MARC_BASE_HI_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_13 = 0x5e65 # macro -regGCMC_VM_MARC_BASE_HI_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_14 = 0x5e66 # macro -regGCMC_VM_MARC_BASE_HI_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_BASE_HI_15 = 0x5e67 # macro -regGCMC_VM_MARC_BASE_HI_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_0 = 0x5e68 # macro -regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_1 = 0x5e69 # macro -regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_2 = 0x5e6a # macro -regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_3 = 0x5e6b # macro -regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_4 = 0x5e6c # macro -regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_5 = 0x5e6d # macro -regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_6 = 0x5e6e # macro -regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_7 = 0x5e6f # macro -regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_8 = 0x5e70 # macro -regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_9 = 0x5e71 # macro -regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_10 = 0x5e72 # macro -regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_11 = 0x5e73 # macro -regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_12 = 0x5e74 # macro -regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_13 = 0x5e75 # macro -regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_14 = 0x5e76 # macro -regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_LO_15 = 0x5e77 # macro -regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_0 = 0x5e78 # macro -regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_1 = 0x5e79 # macro -regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_2 = 0x5e7a # macro -regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_3 = 0x5e7b # macro -regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_4 = 0x5e7c # macro -regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_5 = 0x5e7d # macro -regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_6 = 0x5e7e # macro -regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_7 = 0x5e7f # macro -regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_8 = 0x5e80 # macro -regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_9 = 0x5e81 # macro -regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_10 = 0x5e82 # macro -regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_11 = 0x5e83 # macro -regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_12 = 0x5e84 # macro -regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_13 = 0x5e85 # macro -regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_14 = 0x5e86 # macro -regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_RELOC_HI_15 = 0x5e87 # macro -regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_0 = 0x5e88 # macro -regGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_1 = 0x5e89 # macro -regGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_2 = 0x5e8a # macro -regGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_3 = 0x5e8b # macro -regGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_4 = 0x5e8c # macro -regGCMC_VM_MARC_LEN_LO_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_5 = 0x5e8d # macro -regGCMC_VM_MARC_LEN_LO_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_6 = 0x5e8e # macro -regGCMC_VM_MARC_LEN_LO_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_7 = 0x5e8f # macro -regGCMC_VM_MARC_LEN_LO_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_8 = 0x5e90 # macro -regGCMC_VM_MARC_LEN_LO_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_9 = 0x5e91 # macro -regGCMC_VM_MARC_LEN_LO_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_10 = 0x5e92 # macro -regGCMC_VM_MARC_LEN_LO_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_11 = 0x5e93 # macro -regGCMC_VM_MARC_LEN_LO_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_12 = 0x5e94 # macro -regGCMC_VM_MARC_LEN_LO_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_13 = 0x5e95 # macro -regGCMC_VM_MARC_LEN_LO_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_14 = 0x5e96 # macro -regGCMC_VM_MARC_LEN_LO_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_LO_15 = 0x5e97 # macro -regGCMC_VM_MARC_LEN_LO_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_0 = 0x5e98 # macro -regGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_1 = 0x5e99 # macro -regGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_2 = 0x5e9a # macro -regGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_3 = 0x5e9b # macro -regGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_4 = 0x5e9c # macro -regGCMC_VM_MARC_LEN_HI_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_5 = 0x5e9d # macro -regGCMC_VM_MARC_LEN_HI_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_6 = 0x5e9e # macro -regGCMC_VM_MARC_LEN_HI_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_7 = 0x5e9f # macro -regGCMC_VM_MARC_LEN_HI_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_8 = 0x5ea0 # macro -regGCMC_VM_MARC_LEN_HI_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_9 = 0x5ea1 # macro -regGCMC_VM_MARC_LEN_HI_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_10 = 0x5ea2 # macro -regGCMC_VM_MARC_LEN_HI_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_11 = 0x5ea3 # macro -regGCMC_VM_MARC_LEN_HI_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_12 = 0x5ea4 # macro -regGCMC_VM_MARC_LEN_HI_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_13 = 0x5ea5 # macro -regGCMC_VM_MARC_LEN_HI_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_14 = 0x5ea6 # macro -regGCMC_VM_MARC_LEN_HI_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_LEN_HI_15 = 0x5ea7 # macro -regGCMC_VM_MARC_LEN_HI_15_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_0 = 0x5ea8 # macro -regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_1 = 0x5ea9 # macro -regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_2 = 0x5eaa # macro -regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_3 = 0x5eab # macro -regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_4 = 0x5eac # macro -regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_5 = 0x5ead # macro -regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_6 = 0x5eae # macro -regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_7 = 0x5eaf # macro -regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_8 = 0x5eb0 # macro -regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_9 = 0x5eb1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_10 = 0x5eb2 # macro -regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_11 = 0x5eb3 # macro -regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_12 = 0x5eb4 # macro -regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_13 = 0x5eb5 # macro -regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_14 = 0x5eb6 # macro -regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX = 1 # macro -regGCMC_VM_MARC_PFVF_MAPPING_15 = 0x5eb7 # macro -regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX = 1 # macro -regGCUTC_TRANSLATION_FAULT_CNTL0 = 0x5eb8 # macro -regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 1 # macro -regGCUTC_TRANSLATION_FAULT_CNTL1 = 0x5eb9 # macro -regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 1 # macro -regSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro -regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro -regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro -regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_PS = 0x19a8 # macro -regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_PS = 0x19a9 # macro -regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro -regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro -regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro -regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro -regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro -regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro -regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro -regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro -regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro -regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro -regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro -regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro -regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro -regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro -regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro -regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro -regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro -regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro -regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro -regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro -regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro -regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro -regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro -regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro -regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro -regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro -regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro -regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro -regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro -regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro -regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro -regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro -regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro -regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro -regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro -regSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro -regSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro -regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro -regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro -regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro -regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro -regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro -regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro -regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro -regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro -regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_GS = 0x1a28 # macro -regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_GS = 0x1a29 # macro -regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro -regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro -regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro -regSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro -regSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro -regSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro -regSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro -regSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro -regSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro -regSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro -regSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro -regSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro -regSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro -regSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro -regSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro -regSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro -regSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro -regSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro -regSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro -regSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro -regSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro -regSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro -regSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro -regSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro -regSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro -regSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro -regSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro -regSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro -regSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro -regSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro -regSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro -regSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro -regSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro -regSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro -regSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro -regSPI_SHADER_GS_MESHLET_DIM = 0x1a4c # macro -regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX = 0 # macro -regSPI_SHADER_GS_MESHLET_EXP_ALLOC = 0x1a4d # macro -regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX = 0 # macro -regSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro -regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro -regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro -regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro -regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro -regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_ES = 0x1a68 # macro -regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_ES = 0x1a69 # macro -regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro -regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro -regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro -regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro -regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro -regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro -regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro -regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro -regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro -regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro -regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro -regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro -regSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro -regSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro -regSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro -regSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro -regSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro -regSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro -regSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro -regSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro -regSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro -regSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro -regSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro -regSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro -regSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro -regSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro -regSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro -regSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro -regSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro -regSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro -regSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro -regSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro -regSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro -regSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro -regSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro -regSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro -regSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro -regSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro -regSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro -regSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro -regSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro -regSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro -regSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro -regSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro -regSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro -regSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro -regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro -regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro -regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro -regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro -regSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro -regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro -regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro -regSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro -regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro -regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro -regCOMPUTE_DIM_X = 0x1ba1 # macro -regCOMPUTE_DIM_X_BASE_IDX = 0 # macro -regCOMPUTE_DIM_Y = 0x1ba2 # macro -regCOMPUTE_DIM_Y_BASE_IDX = 0 # macro -regCOMPUTE_DIM_Z = 0x1ba3 # macro -regCOMPUTE_DIM_Z_BASE_IDX = 0 # macro -regCOMPUTE_START_X = 0x1ba4 # macro -regCOMPUTE_START_X_BASE_IDX = 0 # macro -regCOMPUTE_START_Y = 0x1ba5 # macro -regCOMPUTE_START_Y_BASE_IDX = 0 # macro -regCOMPUTE_START_Z = 0x1ba6 # macro -regCOMPUTE_START_Z_BASE_IDX = 0 # macro -regCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro -regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro -regCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro -regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro -regCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro -regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro -regCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro -regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro -regCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro -regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro -regCOMPUTE_PGM_LO = 0x1bac # macro -regCOMPUTE_PGM_LO_BASE_IDX = 0 # macro -regCOMPUTE_PGM_HI = 0x1bad # macro -regCOMPUTE_PGM_HI_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro -regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro -regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro -regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro -regCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro -regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro -regCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro -regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro -regCOMPUTE_VMID = 0x1bb4 # macro -regCOMPUTE_VMID_BASE_IDX = 0 # macro -regCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro -regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro -regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro -regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro -regCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro -regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro -regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro -regCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro -regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro -regCOMPUTE_RESTART_X = 0x1bbb # macro -regCOMPUTE_RESTART_X_BASE_IDX = 0 # macro -regCOMPUTE_RESTART_Y = 0x1bbc # macro -regCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro -regCOMPUTE_RESTART_Z = 0x1bbd # macro -regCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro -regCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro -regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro -regCOMPUTE_MISC_RESERVED = 0x1bbf # macro -regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_ID = 0x1bc0 # macro -regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro -regCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro -regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro -regCOMPUTE_REQ_CTRL = 0x1bc2 # macro -regCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro -regCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro -regCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro -regCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro -regCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro -regCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro -regCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro -regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro -regCOMPUTE_DDID_INDEX = 0x1bc9 # macro -regCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro -regCOMPUTE_SHADER_CHKSUM = 0x1bca # macro -regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE4 = 0x1bcb # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE5 = 0x1bcc # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE6 = 0x1bcd # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX = 0 # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE7 = 0x1bce # macro -regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_INTERLEAVE = 0x1bcf # macro -regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX = 0 # macro -regCOMPUTE_RELAUNCH = 0x1bd0 # macro -regCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bd1 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bd2 # macro -regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro -regCOMPUTE_RELAUNCH2 = 0x1bd3 # macro -regCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_0 = 0x1be0 # macro -regCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_1 = 0x1be1 # macro -regCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_2 = 0x1be2 # macro -regCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_3 = 0x1be3 # macro -regCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_4 = 0x1be4 # macro -regCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_5 = 0x1be5 # macro -regCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_6 = 0x1be6 # macro -regCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_7 = 0x1be7 # macro -regCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_8 = 0x1be8 # macro -regCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_9 = 0x1be9 # macro -regCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_10 = 0x1bea # macro -regCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_11 = 0x1beb # macro -regCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_12 = 0x1bec # macro -regCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_13 = 0x1bed # macro -regCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_14 = 0x1bee # macro -regCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro -regCOMPUTE_USER_DATA_15 = 0x1bef # macro -regCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro -regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro -regCOMPUTE_DISPATCH_END = 0x1c1e # macro -regCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro -regCOMPUTE_NOWHERE = 0x1c1f # macro -regCOMPUTE_NOWHERE_BASE_IDX = 0 # macro -regSH_RESERVED_REG0 = 0x1c20 # macro -regSH_RESERVED_REG0_BASE_IDX = 0 # macro -regSH_RESERVED_REG1 = 0x1c21 # macro -regSH_RESERVED_REG1_BASE_IDX = 0 # macro -regCP_CU_MASK_ADDR_LO = 0x1dd2 # macro -regCP_CU_MASK_ADDR_LO_BASE_IDX = 0 # macro -regCP_CU_MASK_ADDR_HI = 0x1dd3 # macro -regCP_CU_MASK_ADDR_HI_BASE_IDX = 0 # macro -regCP_CU_MASK_CNTL = 0x1dd4 # macro -regCP_CU_MASK_CNTL_BASE_IDX = 0 # macro -regCP_EOPQ_WAIT_TIME = 0x1dd5 # macro -regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro -regCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro -regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro -regCPC_INT_INFO = 0x1dd7 # macro -regCPC_INT_INFO_BASE_IDX = 0 # macro -regCP_VIRT_STATUS = 0x1dd8 # macro -regCP_VIRT_STATUS_BASE_IDX = 0 # macro -regCPC_INT_ADDR = 0x1dd9 # macro -regCPC_INT_ADDR_BASE_IDX = 0 # macro -regCPC_INT_PASID = 0x1dda # macro -regCPC_INT_PASID_BASE_IDX = 0 # macro -regCP_GFX_ERROR = 0x1ddb # macro -regCP_GFX_ERROR_BASE_IDX = 0 # macro -regCPG_UTCL1_CNTL = 0x1ddc # macro -regCPG_UTCL1_CNTL_BASE_IDX = 0 # macro -regCPC_UTCL1_CNTL = 0x1ddd # macro -regCPC_UTCL1_CNTL_BASE_IDX = 0 # macro -regCPF_UTCL1_CNTL = 0x1dde # macro -regCPF_UTCL1_CNTL_BASE_IDX = 0 # macro -regCP_AQL_SMM_STATUS = 0x1ddf # macro -regCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro -regCP_RB0_BASE = 0x1de0 # macro -regCP_RB0_BASE_BASE_IDX = 0 # macro -regCP_RB_BASE = 0x1de0 # macro -regCP_RB_BASE_BASE_IDX = 0 # macro -regCP_RB0_CNTL = 0x1de1 # macro -regCP_RB0_CNTL_BASE_IDX = 0 # macro -regCP_RB_CNTL = 0x1de1 # macro -regCP_RB_CNTL_BASE_IDX = 0 # macro -regCP_RB_RPTR_WR = 0x1de2 # macro -regCP_RB_RPTR_WR_BASE_IDX = 0 # macro -regCP_RB0_RPTR_ADDR = 0x1de3 # macro -regCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_RB_RPTR_ADDR = 0x1de3 # macro -regCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro -regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB_RPTR_ADDR_HI = 0x1de4 # macro -regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB0_BUFSZ_MASK = 0x1de5 # macro -regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro -regCP_RB_BUFSZ_MASK = 0x1de5 # macro -regCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro -regCP_INT_CNTL = 0x1de9 # macro -regCP_INT_CNTL_BASE_IDX = 0 # macro -regCP_INT_STATUS = 0x1dea # macro -regCP_INT_STATUS_BASE_IDX = 0 # macro -regCP_DEVICE_ID = 0x1deb # macro -regCP_DEVICE_ID_BASE_IDX = 0 # macro -regCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro -regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_RING_PRIORITY_CNTS = 0x1dec # macro -regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_ME0_PIPE0_PRIORITY = 0x1ded # macro -regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro -regCP_RING0_PRIORITY = 0x1ded # macro -regCP_RING0_PRIORITY_BASE_IDX = 0 # macro -regCP_ME0_PIPE1_PRIORITY = 0x1dee # macro -regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro -regCP_RING1_PRIORITY = 0x1dee # macro -regCP_RING1_PRIORITY_BASE_IDX = 0 # macro -regCP_FATAL_ERROR = 0x1df0 # macro -regCP_FATAL_ERROR_BASE_IDX = 0 # macro -regCP_RB_VMID = 0x1df1 # macro -regCP_RB_VMID_BASE_IDX = 0 # macro -regCP_ME0_PIPE0_VMID = 0x1df2 # macro -regCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro -regCP_ME0_PIPE1_VMID = 0x1df3 # macro -regCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro -regCP_RB0_WPTR = 0x1df4 # macro -regCP_RB0_WPTR_BASE_IDX = 0 # macro -regCP_RB_WPTR = 0x1df4 # macro -regCP_RB_WPTR_BASE_IDX = 0 # macro -regCP_RB0_WPTR_HI = 0x1df5 # macro -regCP_RB0_WPTR_HI_BASE_IDX = 0 # macro -regCP_RB_WPTR_HI = 0x1df5 # macro -regCP_RB_WPTR_HI_BASE_IDX = 0 # macro -regCP_RB1_WPTR = 0x1df6 # macro -regCP_RB1_WPTR_BASE_IDX = 0 # macro -regCP_RB1_WPTR_HI = 0x1df7 # macro -regCP_RB1_WPTR_HI_BASE_IDX = 0 # macro -regCP_PROCESS_QUANTUM = 0x1df9 # macro -regCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro -regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro -regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro -regCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro -regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro -regCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro -regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro -regCPG_UTCL1_ERROR = 0x1dfe # macro -regCPG_UTCL1_ERROR_BASE_IDX = 0 # macro -regCPC_UTCL1_ERROR = 0x1dff # macro -regCPC_UTCL1_ERROR_BASE_IDX = 0 # macro -regCP_RB1_BASE = 0x1e00 # macro -regCP_RB1_BASE_BASE_IDX = 0 # macro -regCP_RB1_CNTL = 0x1e01 # macro -regCP_RB1_CNTL_BASE_IDX = 0 # macro -regCP_RB1_RPTR_ADDR = 0x1e02 # macro -regCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro -regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB1_BUFSZ_MASK = 0x1e04 # macro -regCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro -regCP_INT_CNTL_RING0 = 0x1e0a # macro -regCP_INT_CNTL_RING0_BASE_IDX = 0 # macro -regCP_INT_CNTL_RING1 = 0x1e0b # macro -regCP_INT_CNTL_RING1_BASE_IDX = 0 # macro -regCP_INT_STATUS_RING0 = 0x1e0d # macro -regCP_INT_STATUS_RING0_BASE_IDX = 0 # macro -regCP_INT_STATUS_RING1 = 0x1e0e # macro -regCP_INT_STATUS_RING1_BASE_IDX = 0 # macro -regCP_ME_F32_INTERRUPT = 0x1e13 # macro -regCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_PFP_F32_INTERRUPT = 0x1e14 # macro -regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_MEC1_F32_INTERRUPT = 0x1e16 # macro -regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_MEC2_F32_INTERRUPT = 0x1e17 # macro -regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro -regCP_PWR_CNTL = 0x1e18 # macro -regCP_PWR_CNTL_BASE_IDX = 0 # macro -regCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro -regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro -regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro -regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro -regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro -regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro -regGB_EDC_MODE = 0x1e1e # macro -regGB_EDC_MODE_BASE_IDX = 0 # macro -regCP_DEBUG = 0x1e1f # macro -regCP_DEBUG_BASE_IDX = 0 # macro -regCP_CPC_DEBUG = 0x1e21 # macro -regCP_CPC_DEBUG_BASE_IDX = 0 # macro -regCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro -regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro -regCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro -regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro -regCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro -regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro -regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro -regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro -regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro -regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro -regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro -regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro -regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro -regCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro -regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro -regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro -regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro -regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro -regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro -regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro -regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro -regCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro -regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro -regCP_GFX_QUEUE_INDEX = 0x1e37 # macro -regCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro -regCC_GC_EDC_CONFIG = 0x1e38 # macro -regCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro -regCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro -regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro -regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro -regCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro -regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro -regCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro -regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro -regCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro -regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro -regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro -regCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro -regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro -regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro -regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro -regCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro -regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro -regCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro -regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_ME_PRGRM_CNTR_START = 0x1e45 # macro -regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro -regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro -regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro -regCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro -regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_ME_INTR_ROUTINE_START = 0x1e4a # macro -regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro -regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro -regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro -regCP_CONTEXT_CNTL = 0x1e4d # macro -regCP_CONTEXT_CNTL_BASE_IDX = 0 # macro -regCP_MAX_CONTEXT = 0x1e4e # macro -regCP_MAX_CONTEXT_BASE_IDX = 0 # macro -regCP_IQ_WAIT_TIME1 = 0x1e4f # macro -regCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro -regCP_IQ_WAIT_TIME2 = 0x1e50 # macro -regCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro -regCP_RB0_BASE_HI = 0x1e51 # macro -regCP_RB0_BASE_HI_BASE_IDX = 0 # macro -regCP_RB1_BASE_HI = 0x1e52 # macro -regCP_RB1_BASE_HI_BASE_IDX = 0 # macro -regCP_VMID_RESET = 0x1e53 # macro -regCP_VMID_RESET_BASE_IDX = 0 # macro -regCPC_INT_CNTL = 0x1e54 # macro -regCPC_INT_CNTL_BASE_IDX = 0 # macro -regCPC_INT_STATUS = 0x1e55 # macro -regCPC_INT_STATUS_BASE_IDX = 0 # macro -regCP_VMID_PREEMPT = 0x1e56 # macro -regCP_VMID_PREEMPT_BASE_IDX = 0 # macro -regCPC_INT_CNTX_ID = 0x1e57 # macro -regCPC_INT_CNTX_ID_BASE_IDX = 0 # macro -regCP_PQ_STATUS = 0x1e58 # macro -regCP_PQ_STATUS_BASE_IDX = 0 # macro -regCP_PFP_PRGRM_CNTR_START_HI = 0x1e59 # macro -regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro -regCP_MAX_DRAW_COUNT = 0x1e5c # macro -regCP_MAX_DRAW_COUNT_BASE_IDX = 0 # macro -regCP_MEC1_F32_INT_DIS = 0x1e5d # macro -regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro -regCP_MEC2_F32_INT_DIS = 0x1e5e # macro -regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro -regCP_VMID_STATUS = 0x1e5f # macro -regCP_VMID_STATUS_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro -regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro -regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro -regCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro -regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -regCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro -regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro -regCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro -regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro -regCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro -regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro -regCPC_OS_PIPES = 0x1e67 # macro -regCPC_OS_PIPES_BASE_IDX = 0 # macro -regCP_SUSPEND_RESUME_REQ = 0x1e68 # macro -regCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro -regCP_SUSPEND_CNTL = 0x1e69 # macro -regCP_SUSPEND_CNTL_BASE_IDX = 0 # macro -regCP_IQ_WAIT_TIME3 = 0x1e6a # macro -regCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro -regCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro -regCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCP_DDID_BASE_ADDR_LO = 0x1e6b # macro -regCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro -regCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_DDID_BASE_ADDR_HI = 0x1e6c # macro -regCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCPC_DDID_CNTL = 0x1e6d # macro -regCPC_DDID_CNTL_BASE_IDX = 0 # macro -regCP_DDID_CNTL = 0x1e6d # macro -regCP_DDID_CNTL_BASE_IDX = 0 # macro -regCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro -regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro -regCP_GFX_DDID_WPTR = 0x1e6f # macro -regCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro -regCP_GFX_DDID_RPTR = 0x1e70 # macro -regCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro -regCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro -regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro -regCP_GFX_HPD_STATUS0 = 0x1e72 # macro -regCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro -regCP_GFX_HPD_CONTROL0 = 0x1e73 # macro -regCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro -regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro -regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro -regCP_GFX_INDEX_MUTEX = 0x1e78 # macro -regCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro -regCP_ME_PRGRM_CNTR_START_HI = 0x1e79 # macro -regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX = 0 # macro -regCP_PFP_INTR_ROUTINE_START_HI = 0x1e7a # macro -regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro -regCP_ME_INTR_ROUTINE_START_HI = 0x1e7b # macro -regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX = 0 # macro -regCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro -regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro -regCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro -regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_GFX_HQD_ACTIVE = 0x1e80 # macro -regCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro -regCP_GFX_HQD_VMID = 0x1e81 # macro -regCP_GFX_HQD_VMID_BASE_IDX = 0 # macro -regCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro -regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro -regCP_GFX_HQD_QUANTUM = 0x1e85 # macro -regCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro -regCP_GFX_HQD_BASE = 0x1e86 # macro -regCP_GFX_HQD_BASE_BASE_IDX = 0 # macro -regCP_GFX_HQD_BASE_HI = 0x1e87 # macro -regCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro -regCP_GFX_HQD_RPTR = 0x1e88 # macro -regCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro -regCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro -regCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro -regCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro -regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro -regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro -regCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro -regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_CONTROL = 0x1e8d # macro -regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro -regCP_GFX_HQD_OFFSET = 0x1e8e # macro -regCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro -regCP_GFX_HQD_CNTL = 0x1e8f # macro -regCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro -regCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro -regCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro -regCP_GFX_HQD_WPTR = 0x1e91 # macro -regCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro -regCP_GFX_HQD_WPTR_HI = 0x1e92 # macro -regCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro -regCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro -regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro -regCP_GFX_HQD_MAPPED = 0x1e94 # macro -regCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro -regCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro -regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro -regCP_GFX_HQD_IQ_TIMER = 0x1e96 # macro -regCP_GFX_HQD_IQ_TIMER_BASE_IDX = 0 # macro -regCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro -regCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro -regCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro -regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro -regCP_GFX_MQD_CONTROL = 0x1e9a # macro -regCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_GFX_CONTROL = 0x1e9f # macro -regCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_GFX_STATUS = 0x1ea0 # macro -regCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro -regCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro -regCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_MASK = 0x1ec2 # macro -regCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH0_CNTL = 0x1ec3 # macro -regCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro -regCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro -regCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_MASK = 0x1ec6 # macro -regCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH1_CNTL = 0x1ec7 # macro -regCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro -regCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro -regCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_MASK = 0x1eca # macro -regCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH2_CNTL = 0x1ecb # macro -regCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro -regCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro -regCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_MASK = 0x1ece # macro -regCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro -regCP_DMA_WATCH3_CNTL = 0x1ecf # macro -regCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro -regCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro -regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro -regCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro -regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro -regCP_DMA_WATCH_STAT = 0x1ed2 # macro -regCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro -regCP_PFP_JT_STAT = 0x1ed3 # macro -regCP_PFP_JT_STAT_BASE_IDX = 0 # macro -regCP_MEC_JT_STAT = 0x1ed5 # macro -regCP_MEC_JT_STAT_BASE_IDX = 0 # macro -regCP_CPC_BUSY_HYSTERESIS = 0x1edb # macro -regCP_CPC_BUSY_HYSTERESIS_BASE_IDX = 0 # macro -regCP_CPF_BUSY_HYSTERESIS1 = 0x1edc # macro -regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro -regCP_CPF_BUSY_HYSTERESIS2 = 0x1edd # macro -regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro -regCP_CPG_BUSY_HYSTERESIS1 = 0x1ede # macro -regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX = 0 # macro -regCP_CPG_BUSY_HYSTERESIS2 = 0x1edf # macro -regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX = 0 # macro -regCP_RB_DOORBELL_CLEAR = 0x1f28 # macro -regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro -regCP_RB0_ACTIVE = 0x1f40 # macro -regCP_RB0_ACTIVE_BASE_IDX = 0 # macro -regCP_RB_ACTIVE = 0x1f40 # macro -regCP_RB_ACTIVE_BASE_IDX = 0 # macro -regCP_RB1_ACTIVE = 0x1f41 # macro -regCP_RB1_ACTIVE_BASE_IDX = 0 # macro -regCP_RB_STATUS = 0x1f43 # macro -regCP_RB_STATUS_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_INDEX = 0x1f44 # macro -regCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro -regCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro -regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro -regCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro -regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro -regCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro -regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro -regCP_SDMA_DMA_DONE = 0x1f4e # macro -regCP_SDMA_DMA_DONE_BASE_IDX = 0 # macro -regCP_PFP_SDMA_CS = 0x1f4f # macro -regCP_PFP_SDMA_CS_BASE_IDX = 0 # macro -regCP_ME_SDMA_CS = 0x1f50 # macro -regCP_ME_SDMA_CS_BASE_IDX = 0 # macro -regCPF_GCR_CNTL = 0x1f53 # macro -regCPF_GCR_CNTL_BASE_IDX = 0 # macro -regCPG_UTCL1_STATUS = 0x1f54 # macro -regCPG_UTCL1_STATUS_BASE_IDX = 0 # macro -regCPC_UTCL1_STATUS = 0x1f55 # macro -regCPC_UTCL1_STATUS_BASE_IDX = 0 # macro -regCPF_UTCL1_STATUS = 0x1f56 # macro -regCPF_UTCL1_STATUS_BASE_IDX = 0 # macro -regCP_SD_CNTL = 0x1f57 # macro -regCP_SD_CNTL_BASE_IDX = 0 # macro -regCP_SOFT_RESET_CNTL = 0x1f59 # macro -regCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro -regCP_CPC_GFX_CNTL = 0x1f5a # macro -regCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro -regSPI_ARB_PRIORITY = 0x1f60 # macro -regSPI_ARB_PRIORITY_BASE_IDX = 0 # macro -regSPI_ARB_CYCLES_0 = 0x1f61 # macro -regSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro -regSPI_ARB_CYCLES_1 = 0x1f62 # macro -regSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro -regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro -regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro -regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro -regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro -regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro -regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS4 = 0x1f6d # macro -regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS5 = 0x1f6e # macro -regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS6 = 0x1f6f # macro -regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 # macro -regSPI_WCL_PIPE_PERCENT_CS7 = 0x1f70 # macro -regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 # macro -regSPI_USER_ACCUM_VMID_CNTL = 0x1f71 # macro -regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro -regSPI_GDBG_PER_VMID_CNTL = 0x1f72 # macro -regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 # macro -regSPI_COMPUTE_QUEUE_RESET = 0x1f73 # macro -regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro -regSPI_COMPUTE_WF_CTX_SAVE = 0x1f74 # macro -regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro -regCP_HPD_UTCL1_CNTL = 0x1fa3 # macro -regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro -regCP_HPD_UTCL1_ERROR = 0x1fa7 # macro -regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro -regCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro -regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro -regCP_MQD_BASE_ADDR = 0x1fa9 # macro -regCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro -regCP_MQD_BASE_ADDR_HI = 0x1faa # macro -regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_ACTIVE = 0x1fab # macro -regCP_HQD_ACTIVE_BASE_IDX = 0 # macro -regCP_HQD_VMID = 0x1fac # macro -regCP_HQD_VMID_BASE_IDX = 0 # macro -regCP_HQD_PERSISTENT_STATE = 0x1fad # macro -regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro -regCP_HQD_PIPE_PRIORITY = 0x1fae # macro -regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro -regCP_HQD_QUEUE_PRIORITY = 0x1faf # macro -regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro -regCP_HQD_QUANTUM = 0x1fb0 # macro -regCP_HQD_QUANTUM_BASE_IDX = 0 # macro -regCP_HQD_PQ_BASE = 0x1fb1 # macro -regCP_HQD_PQ_BASE_BASE_IDX = 0 # macro -regCP_HQD_PQ_BASE_HI = 0x1fb2 # macro -regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro -regCP_HQD_PQ_RPTR = 0x1fb3 # macro -regCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro -regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro -regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro -regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_PQ_CONTROL = 0x1fba # macro -regCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_IB_BASE_ADDR = 0x1fbb # macro -regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro -regCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro -regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_IB_RPTR = 0x1fbd # macro -regCP_HQD_IB_RPTR_BASE_IDX = 0 # macro -regCP_HQD_IB_CONTROL = 0x1fbe # macro -regCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_IQ_TIMER = 0x1fbf # macro -regCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro -regCP_HQD_IQ_RPTR = 0x1fc0 # macro -regCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro -regCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro -regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro -regCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro -regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro -regCP_HQD_OFFLOAD = 0x1fc2 # macro -regCP_HQD_OFFLOAD_BASE_IDX = 0 # macro -regCP_HQD_SEMA_CMD = 0x1fc3 # macro -regCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro -regCP_HQD_MSG_TYPE = 0x1fc4 # macro -regCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro -regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro -regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro -regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro -regCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro -regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro -regCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro -regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro -regCP_HQD_HQ_STATUS0 = 0x1fc9 # macro -regCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro -regCP_HQD_HQ_CONTROL0 = 0x1fca # macro -regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro -regCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro -regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro -regCP_MQD_CONTROL = 0x1fcb # macro -regCP_MQD_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_HQ_STATUS1 = 0x1fcc # macro -regCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro -regCP_HQD_HQ_CONTROL1 = 0x1fcd # macro -regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro -regCP_HQD_EOP_BASE_ADDR = 0x1fce # macro -regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro -regCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro -regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_EOP_CONTROL = 0x1fd0 # macro -regCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_EOP_RPTR = 0x1fd1 # macro -regCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro -regCP_HQD_EOP_WPTR = 0x1fd2 # macro -regCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro -regCP_HQD_EOP_EVENTS = 0x1fd3 # macro -regCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro -regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro -regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro -regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro -regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro -regCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro -regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro -regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro -regCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro -regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro -regCP_HQD_ERROR = 0x1fdc # macro -regCP_HQD_ERROR_BASE_IDX = 0 # macro -regCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro -regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro -regCP_HQD_AQL_CONTROL = 0x1fde # macro -regCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_LO = 0x1fdf # macro -regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro -regCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro -regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro -regCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro -regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro -regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro -regCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro -regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro -regCP_HQD_DDID_RPTR = 0x1fe4 # macro -regCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro -regCP_HQD_DDID_WPTR = 0x1fe5 # macro -regCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro -regCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro -regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro -regCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro -regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro -regCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro -regCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro -regTCP_WATCH0_ADDR_H = 0x2048 # macro -regTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH0_ADDR_L = 0x2049 # macro -regTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH0_CNTL = 0x204a # macro -regTCP_WATCH0_CNTL_BASE_IDX = 0 # macro -regTCP_WATCH1_ADDR_H = 0x204b # macro -regTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH1_ADDR_L = 0x204c # macro -regTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH1_CNTL = 0x204d # macro -regTCP_WATCH1_CNTL_BASE_IDX = 0 # macro -regTCP_WATCH2_ADDR_H = 0x204e # macro -regTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH2_ADDR_L = 0x204f # macro -regTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH2_CNTL = 0x2050 # macro -regTCP_WATCH2_CNTL_BASE_IDX = 0 # macro -regTCP_WATCH3_ADDR_H = 0x2051 # macro -regTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro -regTCP_WATCH3_ADDR_L = 0x2052 # macro -regTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro -regTCP_WATCH3_CNTL = 0x2053 # macro -regTCP_WATCH3_CNTL_BASE_IDX = 0 # macro -regGDS_VMID0_BASE = 0x20a0 # macro -regGDS_VMID0_BASE_BASE_IDX = 0 # macro -regGDS_VMID0_SIZE = 0x20a1 # macro -regGDS_VMID0_SIZE_BASE_IDX = 0 # macro -regGDS_VMID1_BASE = 0x20a2 # macro -regGDS_VMID1_BASE_BASE_IDX = 0 # macro -regGDS_VMID1_SIZE = 0x20a3 # macro -regGDS_VMID1_SIZE_BASE_IDX = 0 # macro -regGDS_VMID2_BASE = 0x20a4 # macro -regGDS_VMID2_BASE_BASE_IDX = 0 # macro -regGDS_VMID2_SIZE = 0x20a5 # macro -regGDS_VMID2_SIZE_BASE_IDX = 0 # macro -regGDS_VMID3_BASE = 0x20a6 # macro -regGDS_VMID3_BASE_BASE_IDX = 0 # macro -regGDS_VMID3_SIZE = 0x20a7 # macro -regGDS_VMID3_SIZE_BASE_IDX = 0 # macro -regGDS_VMID4_BASE = 0x20a8 # macro -regGDS_VMID4_BASE_BASE_IDX = 0 # macro -regGDS_VMID4_SIZE = 0x20a9 # macro -regGDS_VMID4_SIZE_BASE_IDX = 0 # macro -regGDS_VMID5_BASE = 0x20aa # macro -regGDS_VMID5_BASE_BASE_IDX = 0 # macro -regGDS_VMID5_SIZE = 0x20ab # macro -regGDS_VMID5_SIZE_BASE_IDX = 0 # macro -regGDS_VMID6_BASE = 0x20ac # macro -regGDS_VMID6_BASE_BASE_IDX = 0 # macro -regGDS_VMID6_SIZE = 0x20ad # macro -regGDS_VMID6_SIZE_BASE_IDX = 0 # macro -regGDS_VMID7_BASE = 0x20ae # macro -regGDS_VMID7_BASE_BASE_IDX = 0 # macro -regGDS_VMID7_SIZE = 0x20af # macro -regGDS_VMID7_SIZE_BASE_IDX = 0 # macro -regGDS_VMID8_BASE = 0x20b0 # macro -regGDS_VMID8_BASE_BASE_IDX = 0 # macro -regGDS_VMID8_SIZE = 0x20b1 # macro -regGDS_VMID8_SIZE_BASE_IDX = 0 # macro -regGDS_VMID9_BASE = 0x20b2 # macro -regGDS_VMID9_BASE_BASE_IDX = 0 # macro -regGDS_VMID9_SIZE = 0x20b3 # macro -regGDS_VMID9_SIZE_BASE_IDX = 0 # macro -regGDS_VMID10_BASE = 0x20b4 # macro -regGDS_VMID10_BASE_BASE_IDX = 0 # macro -regGDS_VMID10_SIZE = 0x20b5 # macro -regGDS_VMID10_SIZE_BASE_IDX = 0 # macro -regGDS_VMID11_BASE = 0x20b6 # macro -regGDS_VMID11_BASE_BASE_IDX = 0 # macro -regGDS_VMID11_SIZE = 0x20b7 # macro -regGDS_VMID11_SIZE_BASE_IDX = 0 # macro -regGDS_VMID12_BASE = 0x20b8 # macro -regGDS_VMID12_BASE_BASE_IDX = 0 # macro -regGDS_VMID12_SIZE = 0x20b9 # macro -regGDS_VMID12_SIZE_BASE_IDX = 0 # macro -regGDS_VMID13_BASE = 0x20ba # macro -regGDS_VMID13_BASE_BASE_IDX = 0 # macro -regGDS_VMID13_SIZE = 0x20bb # macro -regGDS_VMID13_SIZE_BASE_IDX = 0 # macro -regGDS_VMID14_BASE = 0x20bc # macro -regGDS_VMID14_BASE_BASE_IDX = 0 # macro -regGDS_VMID14_SIZE = 0x20bd # macro -regGDS_VMID14_SIZE_BASE_IDX = 0 # macro -regGDS_VMID15_BASE = 0x20be # macro -regGDS_VMID15_BASE_BASE_IDX = 0 # macro -regGDS_VMID15_SIZE = 0x20bf # macro -regGDS_VMID15_SIZE_BASE_IDX = 0 # macro -regGDS_GWS_VMID0 = 0x20c0 # macro -regGDS_GWS_VMID0_BASE_IDX = 0 # macro -regGDS_GWS_VMID1 = 0x20c1 # macro -regGDS_GWS_VMID1_BASE_IDX = 0 # macro -regGDS_GWS_VMID2 = 0x20c2 # macro -regGDS_GWS_VMID2_BASE_IDX = 0 # macro -regGDS_GWS_VMID3 = 0x20c3 # macro -regGDS_GWS_VMID3_BASE_IDX = 0 # macro -regGDS_GWS_VMID4 = 0x20c4 # macro -regGDS_GWS_VMID4_BASE_IDX = 0 # macro -regGDS_GWS_VMID5 = 0x20c5 # macro -regGDS_GWS_VMID5_BASE_IDX = 0 # macro -regGDS_GWS_VMID6 = 0x20c6 # macro -regGDS_GWS_VMID6_BASE_IDX = 0 # macro -regGDS_GWS_VMID7 = 0x20c7 # macro -regGDS_GWS_VMID7_BASE_IDX = 0 # macro -regGDS_GWS_VMID8 = 0x20c8 # macro -regGDS_GWS_VMID8_BASE_IDX = 0 # macro -regGDS_GWS_VMID9 = 0x20c9 # macro -regGDS_GWS_VMID9_BASE_IDX = 0 # macro -regGDS_GWS_VMID10 = 0x20ca # macro -regGDS_GWS_VMID10_BASE_IDX = 0 # macro -regGDS_GWS_VMID11 = 0x20cb # macro -regGDS_GWS_VMID11_BASE_IDX = 0 # macro -regGDS_GWS_VMID12 = 0x20cc # macro -regGDS_GWS_VMID12_BASE_IDX = 0 # macro -regGDS_GWS_VMID13 = 0x20cd # macro -regGDS_GWS_VMID13_BASE_IDX = 0 # macro -regGDS_GWS_VMID14 = 0x20ce # macro -regGDS_GWS_VMID14_BASE_IDX = 0 # macro -regGDS_GWS_VMID15 = 0x20cf # macro -regGDS_GWS_VMID15_BASE_IDX = 0 # macro -regGDS_OA_VMID0 = 0x20d0 # macro -regGDS_OA_VMID0_BASE_IDX = 0 # macro -regGDS_OA_VMID1 = 0x20d1 # macro -regGDS_OA_VMID1_BASE_IDX = 0 # macro -regGDS_OA_VMID2 = 0x20d2 # macro -regGDS_OA_VMID2_BASE_IDX = 0 # macro -regGDS_OA_VMID3 = 0x20d3 # macro -regGDS_OA_VMID3_BASE_IDX = 0 # macro -regGDS_OA_VMID4 = 0x20d4 # macro -regGDS_OA_VMID4_BASE_IDX = 0 # macro -regGDS_OA_VMID5 = 0x20d5 # macro -regGDS_OA_VMID5_BASE_IDX = 0 # macro -regGDS_OA_VMID6 = 0x20d6 # macro -regGDS_OA_VMID6_BASE_IDX = 0 # macro -regGDS_OA_VMID7 = 0x20d7 # macro -regGDS_OA_VMID7_BASE_IDX = 0 # macro -regGDS_OA_VMID8 = 0x20d8 # macro -regGDS_OA_VMID8_BASE_IDX = 0 # macro -regGDS_OA_VMID9 = 0x20d9 # macro -regGDS_OA_VMID9_BASE_IDX = 0 # macro -regGDS_OA_VMID10 = 0x20da # macro -regGDS_OA_VMID10_BASE_IDX = 0 # macro -regGDS_OA_VMID11 = 0x20db # macro -regGDS_OA_VMID11_BASE_IDX = 0 # macro -regGDS_OA_VMID12 = 0x20dc # macro -regGDS_OA_VMID12_BASE_IDX = 0 # macro -regGDS_OA_VMID13 = 0x20dd # macro -regGDS_OA_VMID13_BASE_IDX = 0 # macro -regGDS_OA_VMID14 = 0x20de # macro -regGDS_OA_VMID14_BASE_IDX = 0 # macro -regGDS_OA_VMID15 = 0x20df # macro -regGDS_OA_VMID15_BASE_IDX = 0 # macro -regGDS_GWS_RESET0 = 0x20e4 # macro -regGDS_GWS_RESET0_BASE_IDX = 0 # macro -regGDS_GWS_RESET1 = 0x20e5 # macro -regGDS_GWS_RESET1_BASE_IDX = 0 # macro -regGDS_GWS_RESOURCE_RESET = 0x20e6 # macro -regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro -regGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro -regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro -regGDS_OA_RESET_MASK = 0x20e9 # macro -regGDS_OA_RESET_MASK_BASE_IDX = 0 # macro -regGDS_OA_RESET = 0x20ea # macro -regGDS_OA_RESET_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_STATUS = 0x20ed # macro -regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT0 = 0x20ee # macro -regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT1 = 0x20ef # macro -regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT2 = 0x20f0 # macro -regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro -regGDS_CS_CTXSW_CNT3 = 0x20f1 # macro -regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro -regGDS_GFX_CTXSW_STATUS = 0x20f2 # macro -regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT0 = 0x20f7 # macro -regGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT1 = 0x20f8 # macro -regGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT2 = 0x20f9 # macro -regGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_CNT3 = 0x20fa # macro -regGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro -regGDS_PS_CTXSW_IDX = 0x20fb # macro -regGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT0 = 0x2117 # macro -regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT1 = 0x2118 # macro -regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT2 = 0x2119 # macro -regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro -regGDS_GS_CTXSW_CNT3 = 0x211a # macro -regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro -regGDS_MEMORY_CLEAN = 0x211f # macro -regGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro -regGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro -regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro -regGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro -regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro -regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro -regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro -regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro -regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro -regGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro -regGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_FIXED = 0x2c08 # macro -regGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_FIXED = 0x2c09 # macro -regGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro -regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro -regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro -regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro -regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro -regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro -regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro -regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro -regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro -regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro -regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro -regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro -regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro -regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro -regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro -regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -regGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro -regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro -regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro -regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro -regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -regGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro -regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -regGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro -regGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro -regGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro -regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro -regGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro -regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUEUING = 0x2c22 # macro -regGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_FIXED = 0x2c23 # macro -regGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro -regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro -regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro -regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro -regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro -regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro -regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro -regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro -regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro -regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro -regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro -regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro -regGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro -regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro -regGUS_IO_GROUP_BURST = 0x2c30 # macro -regGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro -regGUS_DRAM_GROUP_BURST = 0x2c31 # macro -regGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro -regGUS_SDP_ARB_FINAL = 0x2c32 # macro -regGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro -regGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro -regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro -regGUS_SDP_CREDITS = 0x2c34 # macro -regGUS_SDP_CREDITS_BASE_IDX = 1 # macro -regGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro -regGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro -regGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro -regGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro -regGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro -regGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro -regGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro -regGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro -regGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro -regGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro -regGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro -regGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro -regGUS_SDP_REQ_CNTL = 0x2c3b # macro -regGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro -regGUS_MISC = 0x2c3c # macro -regGUS_MISC_BASE_IDX = 1 # macro -regGUS_LATENCY_SAMPLING = 0x2c3d # macro -regGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro -regGUS_ERR_STATUS = 0x2c3e # macro -regGUS_ERR_STATUS_BASE_IDX = 1 # macro -regGUS_MISC2 = 0x2c3f # macro -regGUS_MISC2_BASE_IDX = 1 # macro -regGUS_SDP_ENABLE = 0x2c45 # macro -regGUS_SDP_ENABLE_BASE_IDX = 1 # macro -regGUS_L1_CH0_CMD_IN = 0x2c46 # macro -regGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_CH0_CMD_OUT = 0x2c47 # macro -regGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_IN = 0x2c48 # macro -regGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_OUT = 0x2c49 # macro -regGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro -regGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro -regGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH1_CMD_IN = 0x2c4c # macro -regGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_CH1_CMD_OUT = 0x2c4d # macro -regGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_IN = 0x2c4e # macro -regGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_OUT = 0x2c4f # macro -regGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro -regGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro -regGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA0_CMD_IN = 0x2c52 # macro -regGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA0_CMD_OUT = 0x2c53 # macro -regGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_IN = 0x2c54 # macro -regGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_OUT = 0x2c55 # macro -regGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro -regGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro -regGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA1_CMD_IN = 0x2c58 # macro -regGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA1_CMD_OUT = 0x2c59 # macro -regGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_IN = 0x2c5a # macro -regGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_OUT = 0x2c5b # macro -regGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro -regGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro -regGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA2_CMD_IN = 0x2c5e # macro -regGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA2_CMD_OUT = 0x2c5f # macro -regGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_IN = 0x2c60 # macro -regGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_OUT = 0x2c61 # macro -regGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro -regGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro -regGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA3_CMD_IN = 0x2c64 # macro -regGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro -regGUS_L1_SA3_CMD_OUT = 0x2c65 # macro -regGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_IN = 0x2c66 # macro -regGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_OUT = 0x2c67 # macro -regGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro -regGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro -regGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro -regGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro -regGUS_MISC3 = 0x2c6a # macro -regGUS_MISC3_BASE_IDX = 1 # macro -regGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro -regGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro -regDB_RENDER_CONTROL = 0x0000 # macro -regDB_RENDER_CONTROL_BASE_IDX = 1 # macro -regDB_COUNT_CONTROL = 0x0001 # macro -regDB_COUNT_CONTROL_BASE_IDX = 1 # macro -regDB_DEPTH_VIEW = 0x0002 # macro -regDB_DEPTH_VIEW_BASE_IDX = 1 # macro -regDB_RENDER_OVERRIDE = 0x0003 # macro -regDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro -regDB_RENDER_OVERRIDE2 = 0x0004 # macro -regDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro -regDB_HTILE_DATA_BASE = 0x0005 # macro -regDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro -regDB_DEPTH_SIZE_XY = 0x0007 # macro -regDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro -regDB_DEPTH_BOUNDS_MIN = 0x0008 # macro -regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro -regDB_DEPTH_BOUNDS_MAX = 0x0009 # macro -regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro -regDB_STENCIL_CLEAR = 0x000a # macro -regDB_STENCIL_CLEAR_BASE_IDX = 1 # macro -regDB_DEPTH_CLEAR = 0x000b # macro -regDB_DEPTH_CLEAR_BASE_IDX = 1 # macro -regPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro -regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro -regPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro -regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro -regDB_RESERVED_REG_2 = 0x000f # macro -regDB_RESERVED_REG_2_BASE_IDX = 1 # macro -regDB_Z_INFO = 0x0010 # macro -regDB_Z_INFO_BASE_IDX = 1 # macro -regDB_STENCIL_INFO = 0x0011 # macro -regDB_STENCIL_INFO_BASE_IDX = 1 # macro -regDB_Z_READ_BASE = 0x0012 # macro -regDB_Z_READ_BASE_BASE_IDX = 1 # macro -regDB_STENCIL_READ_BASE = 0x0013 # macro -regDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro -regDB_Z_WRITE_BASE = 0x0014 # macro -regDB_Z_WRITE_BASE_BASE_IDX = 1 # macro -regDB_STENCIL_WRITE_BASE = 0x0015 # macro -regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro -regDB_RESERVED_REG_1 = 0x0016 # macro -regDB_RESERVED_REG_1_BASE_IDX = 1 # macro -regDB_RESERVED_REG_3 = 0x0017 # macro -regDB_RESERVED_REG_3_BASE_IDX = 1 # macro -regDB_Z_READ_BASE_HI = 0x001a # macro -regDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro -regDB_STENCIL_READ_BASE_HI = 0x001b # macro -regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro -regDB_Z_WRITE_BASE_HI = 0x001c # macro -regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro -regDB_STENCIL_WRITE_BASE_HI = 0x001d # macro -regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro -regDB_HTILE_DATA_BASE_HI = 0x001e # macro -regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro -regDB_RMI_L2_CACHE_CONTROL = 0x001f # macro -regDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro -regTA_BC_BASE_ADDR = 0x0020 # macro -regTA_BC_BASE_ADDR_BASE_IDX = 1 # macro -regTA_BC_BASE_ADDR_HI = 0x0021 # macro -regTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_0 = 0x007a # macro -regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_1 = 0x007b # macro -regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_2 = 0x007c # macro -regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_HI_3 = 0x007d # macro -regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_2 = 0x007e # macro -regCOHER_DEST_BASE_2_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_3 = 0x007f # macro -regCOHER_DEST_BASE_3_BASE_IDX = 1 # macro -regPA_SC_WINDOW_OFFSET = 0x0080 # macro -regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro -regPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro -regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro -regPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro -regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_RULE = 0x0083 # macro -regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_0_TL = 0x0084 # macro -regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_0_BR = 0x0085 # macro -regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_1_TL = 0x0086 # macro -regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_1_BR = 0x0087 # macro -regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_2_TL = 0x0088 # macro -regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_2_BR = 0x0089 # macro -regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_3_TL = 0x008a # macro -regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro -regPA_SC_CLIPRECT_3_BR = 0x008b # macro -regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro -regPA_SC_EDGERULE = 0x008c # macro -regPA_SC_EDGERULE_BASE_IDX = 1 # macro -regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro -regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro -regCB_TARGET_MASK = 0x008e # macro -regCB_TARGET_MASK_BASE_IDX = 1 # macro -regCB_SHADER_MASK = 0x008f # macro -regCB_SHADER_MASK_BASE_IDX = 1 # macro -regPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro -regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro -regPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro -regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_0 = 0x0092 # macro -regCOHER_DEST_BASE_0_BASE_IDX = 1 # macro -regCOHER_DEST_BASE_1 = 0x0093 # macro -regCOHER_DEST_BASE_1_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro -regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro -regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro -regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro -regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro -regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro -regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro -regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro -regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro -regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro -regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro -regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro -regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro -regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro -regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro -regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro -regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro -regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro -regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro -regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro -regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro -regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro -regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro -regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro -regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro -regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro -regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro -regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro -regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro -regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro -regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro -regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro -regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro -regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro -regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro -regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro -regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro -regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro -regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro -regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_3 = 0x00ba # macro -regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_3 = 0x00bb # macro -regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_4 = 0x00bc # macro -regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_4 = 0x00bd # macro -regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_5 = 0x00be # macro -regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_5 = 0x00bf # macro -regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro -regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro -regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro -regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro -regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro -regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro -regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro -regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro -regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro -regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro -regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_11 = 0x00ca # macro -regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_11 = 0x00cb # macro -regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_12 = 0x00cc # macro -regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_12 = 0x00cd # macro -regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_13 = 0x00ce # macro -regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_13 = 0x00cf # macro -regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro -regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro -regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro -regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro -regPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro -regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro -regPA_SC_RASTER_CONFIG = 0x00d4 # macro -regPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro -regPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro -regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro -regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro -regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro -regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro -regCP_PERFMON_CNTX_CNTL = 0x00d8 # macro -regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro -regCP_PIPEID = 0x00d9 # macro -regCP_PIPEID_BASE_IDX = 1 # macro -regCP_RINGID = 0x00d9 # macro -regCP_RINGID_BASE_IDX = 1 # macro -regCP_VMID = 0x00da # macro -regCP_VMID_BASE_IDX = 1 # macro -regCONTEXT_RESERVED_REG0 = 0x00db # macro -regCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro -regCONTEXT_RESERVED_REG1 = 0x00dc # macro -regCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro -regPA_SC_VRS_OVERRIDE_CNTL = 0x00f4 # macro -regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE = 0x00f5 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT = 0x00f6 # macro -regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY = 0x00f7 # macro -regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_CACHE_CNTL = 0x00f9 # macro -regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_BASE = 0x00fc # macro -regPA_SC_VRS_RATE_BASE_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_BASE_EXT = 0x00fd # macro -regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX = 1 # macro -regPA_SC_VRS_RATE_SIZE_XY = 0x00fe # macro -regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX = 1 # macro -regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro -regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro -regCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro -regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND_RED = 0x0105 # macro -regCB_BLEND_RED_BASE_IDX = 1 # macro -regCB_BLEND_GREEN = 0x0106 # macro -regCB_BLEND_GREEN_BASE_IDX = 1 # macro -regCB_BLEND_BLUE = 0x0107 # macro -regCB_BLEND_BLUE_BASE_IDX = 1 # macro -regCB_BLEND_ALPHA = 0x0108 # macro -regCB_BLEND_ALPHA_BASE_IDX = 1 # macro -regCB_FDCC_CONTROL = 0x0109 # macro -regCB_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COVERAGE_OUT_CONTROL = 0x010a # macro -regCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro -regDB_STENCIL_CONTROL = 0x010b # macro -regDB_STENCIL_CONTROL_BASE_IDX = 1 # macro -regDB_STENCILREFMASK = 0x010c # macro -regDB_STENCILREFMASK_BASE_IDX = 1 # macro -regDB_STENCILREFMASK_BF = 0x010d # macro -regDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE = 0x010f # macro -regPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET = 0x0110 # macro -regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE = 0x0111 # macro -regPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET = 0x0112 # macro -regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE = 0x0113 # macro -regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET = 0x0114 # macro -regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_1 = 0x0115 # macro -regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro -regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_1 = 0x0117 # macro -regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro -regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro -regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro -regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_2 = 0x011b # macro -regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_2 = 0x011c # macro -regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_2 = 0x011d # macro -regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_2 = 0x011e # macro -regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_2 = 0x011f # macro -regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro -regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_3 = 0x0121 # macro -regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro -regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_3 = 0x0123 # macro -regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro -regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro -regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro -regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_4 = 0x0127 # macro -regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro -regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_4 = 0x0129 # macro -regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_4 = 0x012a # macro -regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_4 = 0x012b # macro -regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro -regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_5 = 0x012d # macro -regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_5 = 0x012e # macro -regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_5 = 0x012f # macro -regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro -regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro -regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro -regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_6 = 0x0133 # macro -regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro -regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_6 = 0x0135 # macro -regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro -regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro -regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro -regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_7 = 0x0139 # macro -regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_7 = 0x013a # macro -regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_7 = 0x013b # macro -regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_7 = 0x013c # macro -regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_7 = 0x013d # macro -regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro -regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_8 = 0x013f # macro -regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro -regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_8 = 0x0141 # macro -regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro -regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro -regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro -regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_9 = 0x0145 # macro -regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro -regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_9 = 0x0147 # macro -regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro -regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro -regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro -regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_10 = 0x014b # macro -regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_10 = 0x014c # macro -regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_10 = 0x014d # macro -regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_10 = 0x014e # macro -regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_10 = 0x014f # macro -regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro -regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_11 = 0x0151 # macro -regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro -regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_11 = 0x0153 # macro -regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro -regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro -regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro -regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_12 = 0x0157 # macro -regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro -regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_12 = 0x0159 # macro -regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_12 = 0x015a # macro -regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_12 = 0x015b # macro -regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro -regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_13 = 0x015d # macro -regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_13 = 0x015e # macro -regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_13 = 0x015f # macro -regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro -regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro -regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro -regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_14 = 0x0163 # macro -regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro -regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_14 = 0x0165 # macro -regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro -regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro -regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro -regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro -regPA_CL_VPORT_XSCALE_15 = 0x0169 # macro -regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_XOFFSET_15 = 0x016a # macro -regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_YSCALE_15 = 0x016b # macro -regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_YOFFSET_15 = 0x016c # macro -regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZSCALE_15 = 0x016d # macro -regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro -regPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro -regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro -regPA_CL_UCP_0_X = 0x016f # macro -regPA_CL_UCP_0_X_BASE_IDX = 1 # macro -regPA_CL_UCP_0_Y = 0x0170 # macro -regPA_CL_UCP_0_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_0_Z = 0x0171 # macro -regPA_CL_UCP_0_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_0_W = 0x0172 # macro -regPA_CL_UCP_0_W_BASE_IDX = 1 # macro -regPA_CL_UCP_1_X = 0x0173 # macro -regPA_CL_UCP_1_X_BASE_IDX = 1 # macro -regPA_CL_UCP_1_Y = 0x0174 # macro -regPA_CL_UCP_1_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_1_Z = 0x0175 # macro -regPA_CL_UCP_1_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_1_W = 0x0176 # macro -regPA_CL_UCP_1_W_BASE_IDX = 1 # macro -regPA_CL_UCP_2_X = 0x0177 # macro -regPA_CL_UCP_2_X_BASE_IDX = 1 # macro -regPA_CL_UCP_2_Y = 0x0178 # macro -regPA_CL_UCP_2_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_2_Z = 0x0179 # macro -regPA_CL_UCP_2_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_2_W = 0x017a # macro -regPA_CL_UCP_2_W_BASE_IDX = 1 # macro -regPA_CL_UCP_3_X = 0x017b # macro -regPA_CL_UCP_3_X_BASE_IDX = 1 # macro -regPA_CL_UCP_3_Y = 0x017c # macro -regPA_CL_UCP_3_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_3_Z = 0x017d # macro -regPA_CL_UCP_3_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_3_W = 0x017e # macro -regPA_CL_UCP_3_W_BASE_IDX = 1 # macro -regPA_CL_UCP_4_X = 0x017f # macro -regPA_CL_UCP_4_X_BASE_IDX = 1 # macro -regPA_CL_UCP_4_Y = 0x0180 # macro -regPA_CL_UCP_4_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_4_Z = 0x0181 # macro -regPA_CL_UCP_4_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_4_W = 0x0182 # macro -regPA_CL_UCP_4_W_BASE_IDX = 1 # macro -regPA_CL_UCP_5_X = 0x0183 # macro -regPA_CL_UCP_5_X_BASE_IDX = 1 # macro -regPA_CL_UCP_5_Y = 0x0184 # macro -regPA_CL_UCP_5_Y_BASE_IDX = 1 # macro -regPA_CL_UCP_5_Z = 0x0185 # macro -regPA_CL_UCP_5_Z_BASE_IDX = 1 # macro -regPA_CL_UCP_5_W = 0x0186 # macro -regPA_CL_UCP_5_W_BASE_IDX = 1 # macro -regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro -regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro -regPA_RATE_CNTL = 0x0188 # macro -regPA_RATE_CNTL_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_0 = 0x0191 # macro -regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_1 = 0x0192 # macro -regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_2 = 0x0193 # macro -regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_3 = 0x0194 # macro -regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_4 = 0x0195 # macro -regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_5 = 0x0196 # macro -regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_6 = 0x0197 # macro -regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_7 = 0x0198 # macro -regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_8 = 0x0199 # macro -regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_9 = 0x019a # macro -regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_10 = 0x019b # macro -regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_11 = 0x019c # macro -regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_12 = 0x019d # macro -regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_13 = 0x019e # macro -regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_14 = 0x019f # macro -regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro -regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro -regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro -regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro -regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro -regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro -regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro -regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro -regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro -regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro -regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_25 = 0x01aa # macro -regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_26 = 0x01ab # macro -regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_27 = 0x01ac # macro -regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_28 = 0x01ad # macro -regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_29 = 0x01ae # macro -regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_30 = 0x01af # macro -regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro -regSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro -regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro -regSPI_VS_OUT_CONFIG = 0x01b1 # macro -regSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro -regSPI_PS_INPUT_ENA = 0x01b3 # macro -regSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro -regSPI_PS_INPUT_ADDR = 0x01b4 # macro -regSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro -regSPI_INTERP_CONTROL_0 = 0x01b5 # macro -regSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro -regSPI_PS_IN_CONTROL = 0x01b6 # macro -regSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro -regSPI_BARYC_CNTL = 0x01b8 # macro -regSPI_BARYC_CNTL_BASE_IDX = 1 # macro -regSPI_TMPRING_SIZE = 0x01ba # macro -regSPI_TMPRING_SIZE_BASE_IDX = 1 # macro -regSPI_GFX_SCRATCH_BASE_LO = 0x01bb # macro -regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regSPI_GFX_SCRATCH_BASE_HI = 0x01bc # macro -regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regSPI_SHADER_IDX_FORMAT = 0x01c2 # macro -regSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro -regSPI_SHADER_POS_FORMAT = 0x01c3 # macro -regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro -regSPI_SHADER_Z_FORMAT = 0x01c4 # macro -regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro -regSPI_SHADER_COL_FORMAT = 0x01c5 # macro -regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro -regSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro -regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro -regSX_PS_DOWNCONVERT = 0x01d5 # macro -regSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro -regSX_BLEND_OPT_EPSILON = 0x01d6 # macro -regSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro -regSX_BLEND_OPT_CONTROL = 0x01d7 # macro -regSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro -regSX_MRT0_BLEND_OPT = 0x01d8 # macro -regSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT1_BLEND_OPT = 0x01d9 # macro -regSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT2_BLEND_OPT = 0x01da # macro -regSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT3_BLEND_OPT = 0x01db # macro -regSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT4_BLEND_OPT = 0x01dc # macro -regSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT5_BLEND_OPT = 0x01dd # macro -regSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT6_BLEND_OPT = 0x01de # macro -regSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro -regSX_MRT7_BLEND_OPT = 0x01df # macro -regSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro -regCB_BLEND0_CONTROL = 0x01e0 # macro -regCB_BLEND0_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND1_CONTROL = 0x01e1 # macro -regCB_BLEND1_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND2_CONTROL = 0x01e2 # macro -regCB_BLEND2_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND3_CONTROL = 0x01e3 # macro -regCB_BLEND3_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND4_CONTROL = 0x01e4 # macro -regCB_BLEND4_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND5_CONTROL = 0x01e5 # macro -regCB_BLEND5_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND6_CONTROL = 0x01e6 # macro -regCB_BLEND6_CONTROL_BASE_IDX = 1 # macro -regCB_BLEND7_CONTROL = 0x01e7 # macro -regCB_BLEND7_CONTROL_BASE_IDX = 1 # macro -regGFX_COPY_STATE = 0x01f4 # macro -regGFX_COPY_STATE_BASE_IDX = 1 # macro -regPA_CL_POINT_X_RAD = 0x01f5 # macro -regPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro -regPA_CL_POINT_Y_RAD = 0x01f6 # macro -regPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro -regPA_CL_POINT_SIZE = 0x01f7 # macro -regPA_CL_POINT_SIZE_BASE_IDX = 1 # macro -regPA_CL_POINT_CULL_RAD = 0x01f8 # macro -regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro -regVGT_DMA_BASE_HI = 0x01f9 # macro -regVGT_DMA_BASE_HI_BASE_IDX = 1 # macro -regVGT_DMA_BASE = 0x01fa # macro -regVGT_DMA_BASE_BASE_IDX = 1 # macro -regVGT_DRAW_INITIATOR = 0x01fc # macro -regVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro -regVGT_EVENT_ADDRESS_REG = 0x01fe # macro -regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro -regGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro -regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro -regDB_DEPTH_CONTROL = 0x0200 # macro -regDB_DEPTH_CONTROL_BASE_IDX = 1 # macro -regDB_EQAA = 0x0201 # macro -regDB_EQAA_BASE_IDX = 1 # macro -regCB_COLOR_CONTROL = 0x0202 # macro -regCB_COLOR_CONTROL_BASE_IDX = 1 # macro -regDB_SHADER_CONTROL = 0x0203 # macro -regDB_SHADER_CONTROL_BASE_IDX = 1 # macro -regPA_CL_CLIP_CNTL = 0x0204 # macro -regPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro -regPA_SU_SC_MODE_CNTL = 0x0205 # macro -regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro -regPA_CL_VTE_CNTL = 0x0206 # macro -regPA_CL_VTE_CNTL_BASE_IDX = 1 # macro -regPA_CL_VS_OUT_CNTL = 0x0207 # macro -regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro -regPA_CL_NANINF_CNTL = 0x0208 # macro -regPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro -regPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro -regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro -regPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro -regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro -regPA_SU_PRIM_FILTER_CNTL = 0x020b # macro -regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro -regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro -regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro -regPA_CL_NGG_CNTL = 0x020e # macro -regPA_CL_NGG_CNTL_BASE_IDX = 1 # macro -regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro -regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro -regPA_STEREO_CNTL = 0x0210 # macro -regPA_STEREO_CNTL_BASE_IDX = 1 # macro -regPA_STATE_STEREO_X = 0x0211 # macro -regPA_STATE_STEREO_X_BASE_IDX = 1 # macro -regPA_CL_VRS_CNTL = 0x0212 # macro -regPA_CL_VRS_CNTL_BASE_IDX = 1 # macro -regPA_SU_POINT_SIZE = 0x0280 # macro -regPA_SU_POINT_SIZE_BASE_IDX = 1 # macro -regPA_SU_POINT_MINMAX = 0x0281 # macro -regPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro -regPA_SU_LINE_CNTL = 0x0282 # macro -regPA_SU_LINE_CNTL_BASE_IDX = 1 # macro -regPA_SC_LINE_STIPPLE = 0x0283 # macro -regPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro -regVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro -regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro -regVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro -regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro -regPA_SC_MODE_CNTL_0 = 0x0292 # macro -regPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_MODE_CNTL_1 = 0x0293 # macro -regPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro -regVGT_ENHANCE = 0x0294 # macro -regVGT_ENHANCE_BASE_IDX = 1 # macro -regIA_ENHANCE = 0x029c # macro -regIA_ENHANCE_BASE_IDX = 1 # macro -regVGT_DMA_SIZE = 0x029d # macro -regVGT_DMA_SIZE_BASE_IDX = 1 # macro -regVGT_DMA_MAX_SIZE = 0x029e # macro -regVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro -regVGT_DMA_INDEX_TYPE = 0x029f # macro -regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro -regWD_ENHANCE = 0x02a0 # macro -regWD_ENHANCE_BASE_IDX = 1 # macro -regVGT_PRIMITIVEID_EN = 0x02a1 # macro -regVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro -regVGT_DMA_NUM_INSTANCES = 0x02a2 # macro -regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro -regVGT_PRIMITIVEID_RESET = 0x02a3 # macro -regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro -regVGT_EVENT_INITIATOR = 0x02a4 # macro -regVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro -regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro -regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro -regVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro -regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro -regVGT_REUSE_OFF = 0x02ad # macro -regVGT_REUSE_OFF_BASE_IDX = 1 # macro -regDB_HTILE_SURFACE = 0x02af # macro -regDB_HTILE_SURFACE_BASE_IDX = 1 # macro -regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro -regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro -regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro -regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro -regDB_PRELOAD_CONTROL = 0x02b2 # macro -regDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro -regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro -regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro -regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro -regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro -regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro -regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro -regVGT_GS_MAX_VERT_OUT = 0x02ce # macro -regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro -regGE_NGG_SUBGRP_CNTL = 0x02d3 # macro -regGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro -regVGT_TESS_DISTRIBUTION = 0x02d4 # macro -regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro -regVGT_SHADER_STAGES_EN = 0x02d5 # macro -regVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro -regVGT_LS_HS_CONFIG = 0x02d6 # macro -regVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro -regVGT_TF_PARAM = 0x02db # macro -regVGT_TF_PARAM_BASE_IDX = 1 # macro -regDB_ALPHA_TO_MASK = 0x02dc # macro -regDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro -regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro -regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro -regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro -regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro -regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro -regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro -regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro -regVGT_GS_INSTANCE_CNT = 0x02e4 # macro -regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro -regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro -regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro -regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro -regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro -regPA_SC_LINE_CNTL = 0x02f7 # macro -regPA_SC_LINE_CNTL_BASE_IDX = 1 # macro -regPA_SC_AA_CONFIG = 0x02f8 # macro -regPA_SC_AA_CONFIG_BASE_IDX = 1 # macro -regPA_SU_VTX_CNTL = 0x02f9 # macro -regPA_SU_VTX_CNTL_BASE_IDX = 1 # macro -regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro -regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro -regPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro -regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro -regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro -regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro -regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro -regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro -regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro -regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro -regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro -regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro -regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro -regPA_SC_SHADER_CONTROL = 0x0310 # macro -regPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_0 = 0x0311 # macro -regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_1 = 0x0312 # macro -regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro -regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro -regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro -regPA_SC_NGG_MODE_CNTL = 0x0314 # macro -regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_2 = 0x0315 # macro -regPA_SC_BINNER_CNTL_2_BASE_IDX = 1 # macro -regCB_COLOR0_BASE = 0x0318 # macro -regCB_COLOR0_BASE_BASE_IDX = 1 # macro -regCB_COLOR0_VIEW = 0x031b # macro -regCB_COLOR0_VIEW_BASE_IDX = 1 # macro -regCB_COLOR0_INFO = 0x031c # macro -regCB_COLOR0_INFO_BASE_IDX = 1 # macro -regCB_COLOR0_ATTRIB = 0x031d # macro -regCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR0_FDCC_CONTROL = 0x031e # macro -regCB_COLOR0_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR0_DCC_BASE = 0x0325 # macro -regCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR1_BASE = 0x0327 # macro -regCB_COLOR1_BASE_BASE_IDX = 1 # macro -regCB_COLOR1_VIEW = 0x032a # macro -regCB_COLOR1_VIEW_BASE_IDX = 1 # macro -regCB_COLOR1_INFO = 0x032b # macro -regCB_COLOR1_INFO_BASE_IDX = 1 # macro -regCB_COLOR1_ATTRIB = 0x032c # macro -regCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR1_FDCC_CONTROL = 0x032d # macro -regCB_COLOR1_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR1_DCC_BASE = 0x0334 # macro -regCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR2_BASE = 0x0336 # macro -regCB_COLOR2_BASE_BASE_IDX = 1 # macro -regCB_COLOR2_VIEW = 0x0339 # macro -regCB_COLOR2_VIEW_BASE_IDX = 1 # macro -regCB_COLOR2_INFO = 0x033a # macro -regCB_COLOR2_INFO_BASE_IDX = 1 # macro -regCB_COLOR2_ATTRIB = 0x033b # macro -regCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR2_FDCC_CONTROL = 0x033c # macro -regCB_COLOR2_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR2_DCC_BASE = 0x0343 # macro -regCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR3_BASE = 0x0345 # macro -regCB_COLOR3_BASE_BASE_IDX = 1 # macro -regCB_COLOR3_VIEW = 0x0348 # macro -regCB_COLOR3_VIEW_BASE_IDX = 1 # macro -regCB_COLOR3_INFO = 0x0349 # macro -regCB_COLOR3_INFO_BASE_IDX = 1 # macro -regCB_COLOR3_ATTRIB = 0x034a # macro -regCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR3_FDCC_CONTROL = 0x034b # macro -regCB_COLOR3_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR3_DCC_BASE = 0x0352 # macro -regCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR4_BASE = 0x0354 # macro -regCB_COLOR4_BASE_BASE_IDX = 1 # macro -regCB_COLOR4_VIEW = 0x0357 # macro -regCB_COLOR4_VIEW_BASE_IDX = 1 # macro -regCB_COLOR4_INFO = 0x0358 # macro -regCB_COLOR4_INFO_BASE_IDX = 1 # macro -regCB_COLOR4_ATTRIB = 0x0359 # macro -regCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR4_FDCC_CONTROL = 0x035a # macro -regCB_COLOR4_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR4_DCC_BASE = 0x0361 # macro -regCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR5_BASE = 0x0363 # macro -regCB_COLOR5_BASE_BASE_IDX = 1 # macro -regCB_COLOR5_VIEW = 0x0366 # macro -regCB_COLOR5_VIEW_BASE_IDX = 1 # macro -regCB_COLOR5_INFO = 0x0367 # macro -regCB_COLOR5_INFO_BASE_IDX = 1 # macro -regCB_COLOR5_ATTRIB = 0x0368 # macro -regCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR5_FDCC_CONTROL = 0x0369 # macro -regCB_COLOR5_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR5_DCC_BASE = 0x0370 # macro -regCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR6_BASE = 0x0372 # macro -regCB_COLOR6_BASE_BASE_IDX = 1 # macro -regCB_COLOR6_VIEW = 0x0375 # macro -regCB_COLOR6_VIEW_BASE_IDX = 1 # macro -regCB_COLOR6_INFO = 0x0376 # macro -regCB_COLOR6_INFO_BASE_IDX = 1 # macro -regCB_COLOR6_ATTRIB = 0x0377 # macro -regCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR6_FDCC_CONTROL = 0x0378 # macro -regCB_COLOR6_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR6_DCC_BASE = 0x037f # macro -regCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR7_BASE = 0x0381 # macro -regCB_COLOR7_BASE_BASE_IDX = 1 # macro -regCB_COLOR7_VIEW = 0x0384 # macro -regCB_COLOR7_VIEW_BASE_IDX = 1 # macro -regCB_COLOR7_INFO = 0x0385 # macro -regCB_COLOR7_INFO_BASE_IDX = 1 # macro -regCB_COLOR7_ATTRIB = 0x0386 # macro -regCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro -regCB_COLOR7_FDCC_CONTROL = 0x0387 # macro -regCB_COLOR7_FDCC_CONTROL_BASE_IDX = 1 # macro -regCB_COLOR7_DCC_BASE = 0x038e # macro -regCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro -regCB_COLOR0_BASE_EXT = 0x0390 # macro -regCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR1_BASE_EXT = 0x0391 # macro -regCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR2_BASE_EXT = 0x0392 # macro -regCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR3_BASE_EXT = 0x0393 # macro -regCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR4_BASE_EXT = 0x0394 # macro -regCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR5_BASE_EXT = 0x0395 # macro -regCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR6_BASE_EXT = 0x0396 # macro -regCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR7_BASE_EXT = 0x0397 # macro -regCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro -regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro -regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro -regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro -regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro -regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro -regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro -regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR7_DCC_BASE_EXT = 0x03af # macro -regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro -regCB_COLOR0_ATTRIB2 = 0x03b0 # macro -regCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR1_ATTRIB2 = 0x03b1 # macro -regCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR2_ATTRIB2 = 0x03b2 # macro -regCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR3_ATTRIB2 = 0x03b3 # macro -regCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR4_ATTRIB2 = 0x03b4 # macro -regCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR5_ATTRIB2 = 0x03b5 # macro -regCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR6_ATTRIB2 = 0x03b6 # macro -regCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR7_ATTRIB2 = 0x03b7 # macro -regCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro -regCB_COLOR0_ATTRIB3 = 0x03b8 # macro -regCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR1_ATTRIB3 = 0x03b9 # macro -regCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR2_ATTRIB3 = 0x03ba # macro -regCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR3_ATTRIB3 = 0x03bb # macro -regCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR4_ATTRIB3 = 0x03bc # macro -regCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR5_ATTRIB3 = 0x03bd # macro -regCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR6_ATTRIB3 = 0x03be # macro -regCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro -regCB_COLOR7_ATTRIB3 = 0x03bf # macro -regCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro -regCONFIG_RESERVED_REG0 = 0x0800 # macro -regCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro -regCONFIG_RESERVED_REG1 = 0x0801 # macro -regCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro -regCP_MEC_CNTL = 0x0802 # macro -regCP_MEC_CNTL_BASE_IDX = 1 # macro -regCP_ME_CNTL = 0x0803 # macro -regCP_ME_CNTL_BASE_IDX = 1 # macro -regGRBM_GFX_CNTL = 0x0900 # macro -regGRBM_GFX_CNTL_BASE_IDX = 1 # macro -regGRBM_NOWHERE = 0x0901 # macro -regGRBM_NOWHERE_BASE_IDX = 1 # macro -regPA_SC_VRS_SURFACE_CNTL = 0x0940 # macro -regPA_SC_VRS_SURFACE_CNTL_BASE_IDX = 1 # macro -regPA_SC_ENHANCE = 0x0941 # macro -regPA_SC_ENHANCE_BASE_IDX = 1 # macro -regPA_SC_ENHANCE_1 = 0x0942 # macro -regPA_SC_ENHANCE_1_BASE_IDX = 1 # macro -regPA_SC_ENHANCE_2 = 0x0943 # macro -regPA_SC_ENHANCE_2_BASE_IDX = 1 # macro -regPA_SC_ENHANCE_3 = 0x0944 # macro -regPA_SC_ENHANCE_3_BASE_IDX = 1 # macro -regPA_SC_BINNER_CNTL_OVERRIDE = 0x0946 # macro -regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 1 # macro -regPA_SC_PBB_OVERRIDE_FLAG = 0x0947 # macro -regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 1 # macro -regPA_SC_DSM_CNTL = 0x0948 # macro -regPA_SC_DSM_CNTL_BASE_IDX = 1 # macro -regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x0949 # macro -regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 1 # macro -regPA_SC_FIFO_SIZE = 0x094a # macro -regPA_SC_FIFO_SIZE_BASE_IDX = 1 # macro -regPA_SC_IF_FIFO_SIZE = 0x094b # macro -regPA_SC_IF_FIFO_SIZE_BASE_IDX = 1 # macro -regPA_SC_PACKER_WAVE_ID_CNTL = 0x094c # macro -regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX = 1 # macro -regPA_SC_ATM_CNTL = 0x094d # macro -regPA_SC_ATM_CNTL_BASE_IDX = 1 # macro -regPA_SC_PKR_WAVE_TABLE_CNTL = 0x094e # macro -regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 1 # macro -regPA_SC_FORCE_EOV_MAX_CNTS = 0x094f # macro -regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_0 = 0x0950 # macro -regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_1 = 0x0951 # macro -regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_2 = 0x0952 # macro -regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 1 # macro -regPA_SC_BINNER_EVENT_CNTL_3 = 0x0953 # macro -regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 1 # macro -regPA_SC_BINNER_TIMEOUT_COUNTER = 0x0954 # macro -regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_0 = 0x0955 # macro -regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_1 = 0x0956 # macro -regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_2 = 0x0957 # macro -regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 1 # macro -regPA_SC_BINNER_PERF_CNTL_3 = 0x0958 # macro -regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x095b # macro -regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x095c # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_HV_LOCK = 0x095d # macro -regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 # macro -regPA_PH_INTERFACE_FIFO_SIZE = 0x095e # macro -regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 1 # macro -regPA_PH_ENHANCE = 0x095f # macro -regPA_PH_ENHANCE_BASE_IDX = 1 # macro -regPA_SC_VRS_SURFACE_CNTL_1 = 0x0960 # macro -regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX = 1 # macro -regSQ_RUNTIME_CONFIG = 0x09e0 # macro -regSQ_RUNTIME_CONFIG_BASE_IDX = 1 # macro -regSQ_DEBUG_STS_GLOBAL = 0x09e1 # macro -regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 1 # macro -regSQ_DEBUG_STS_GLOBAL2 = 0x09e2 # macro -regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 1 # macro -regSH_MEM_BASES = 0x09e3 # macro -regSH_MEM_BASES_BASE_IDX = 1 # macro -regSH_MEM_CONFIG = 0x09e4 # macro -regSH_MEM_CONFIG_BASE_IDX = 1 # macro -regSQ_DEBUG = 0x09e5 # macro -regSQ_DEBUG_BASE_IDX = 1 # macro -regSQ_SHADER_TBA_LO = 0x09e6 # macro -regSQ_SHADER_TBA_LO_BASE_IDX = 1 # macro -regSQ_SHADER_TBA_HI = 0x09e7 # macro -regSQ_SHADER_TBA_HI_BASE_IDX = 1 # macro -regSQ_SHADER_TMA_LO = 0x09e8 # macro -regSQ_SHADER_TMA_LO_BASE_IDX = 1 # macro -regSQ_SHADER_TMA_HI = 0x09e9 # macro -regSQ_SHADER_TMA_HI_BASE_IDX = 1 # macro -regCP_DEBUG_2 = 0x1800 # macro -regCP_DEBUG_2_BASE_IDX = 1 # macro -regCP_FETCHER_SOURCE = 0x1801 # macro -regCP_FETCHER_SOURCE_BASE_IDX = 1 # macro -regCP_HPD_MES_ROQ_OFFSETS = 0x1821 # macro -regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 1 # macro -regCP_HPD_ROQ_OFFSETS = 0x1821 # macro -regCP_HPD_ROQ_OFFSETS_BASE_IDX = 1 # macro -regCP_HPD_STATUS0 = 0x1822 # macro -regCP_HPD_STATUS0_BASE_IDX = 1 # macro -regDIDT_INDEX_AUTO_INCR_EN = 0x1900 # macro -regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 1 # macro -regDIDT_EDC_CTRL = 0x1901 # macro -regDIDT_EDC_CTRL_BASE_IDX = 1 # macro -regDIDT_EDC_THROTTLE_CTRL = 0x1902 # macro -regDIDT_EDC_THROTTLE_CTRL_BASE_IDX = 1 # macro -regDIDT_EDC_THRESHOLD = 0x1903 # macro -regDIDT_EDC_THRESHOLD_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_1_2 = 0x1904 # macro -regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_3_4 = 0x1905 # macro -regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_5_6 = 0x1906 # macro -regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regDIDT_EDC_STALL_PATTERN_7 = 0x1907 # macro -regDIDT_EDC_STALL_PATTERN_7_BASE_IDX = 1 # macro -regDIDT_EDC_STATUS = 0x1908 # macro -regDIDT_EDC_STATUS_BASE_IDX = 1 # macro -regDIDT_EDC_DYNAMIC_THRESHOLD_RO = 0x1909 # macro -regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX = 1 # macro -regDIDT_EDC_OVERFLOW = 0x190a # macro -regDIDT_EDC_OVERFLOW_BASE_IDX = 1 # macro -regDIDT_EDC_ROLLING_POWER_DELTA = 0x190b # macro -regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro -regDIDT_IND_INDEX = 0x190c # macro -regDIDT_IND_INDEX_BASE_IDX = 1 # macro -regDIDT_IND_DATA = 0x190d # macro -regDIDT_IND_DATA_BASE_IDX = 1 # macro -regSPI_GDBG_WAVE_CNTL = 0x1943 # macro -regSPI_GDBG_WAVE_CNTL_BASE_IDX = 1 # macro -regSPI_GDBG_TRAP_CONFIG = 0x1944 # macro -regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 1 # macro -regSPI_GDBG_WAVE_CNTL3 = 0x1945 # macro -regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 1 # macro -regSPI_ARB_CNTL_0 = 0x1949 # macro -regSPI_ARB_CNTL_0_BASE_IDX = 1 # macro -regSPI_FEATURE_CTRL = 0x194a # macro -regSPI_FEATURE_CTRL_BASE_IDX = 1 # macro -regSPI_SHADER_RSRC_LIMIT_CTRL = 0x194b # macro -regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 1 # macro -regSPI_COMPUTE_WF_CTX_SAVE_STATUS = 0x194e # macro -regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX = 1 # macro -regTCP_INVALIDATE = 0x19a0 # macro -regTCP_INVALIDATE_BASE_IDX = 1 # macro -regTCP_STATUS = 0x19a1 # macro -regTCP_STATUS_BASE_IDX = 1 # macro -regTCP_CNTL = 0x19a2 # macro -regTCP_CNTL_BASE_IDX = 1 # macro -regTCP_CNTL2 = 0x19a3 # macro -regTCP_CNTL2_BASE_IDX = 1 # macro -regTCP_DEBUG_INDEX = 0x19a5 # macro -regTCP_DEBUG_INDEX_BASE_IDX = 1 # macro -regTCP_DEBUG_DATA = 0x19a6 # macro -regTCP_DEBUG_DATA_BASE_IDX = 1 # macro -regGDS_ENHANCE2 = 0x19b0 # macro -regGDS_ENHANCE2_BASE_IDX = 1 # macro -regGDS_OA_CGPG_RESTORE = 0x19b1 # macro -regGDS_OA_CGPG_RESTORE_BASE_IDX = 1 # macro -regUTCL1_CTRL_0 = 0x1980 # macro -regUTCL1_CTRL_0_BASE_IDX = 1 # macro -regUTCL1_UTCL0_INVREQ_DISABLE = 0x1984 # macro -regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 1 # macro -regUTCL1_CTRL_2 = 0x1985 # macro -regUTCL1_CTRL_2_BASE_IDX = 1 # macro -regUTCL1_FIFO_SIZING = 0x1986 # macro -regUTCL1_FIFO_SIZING_BASE_IDX = 1 # macro -regGCRD_SA0_TARGETS_DISABLE = 0x1987 # macro -regGCRD_SA0_TARGETS_DISABLE_BASE_IDX = 1 # macro -regGCRD_SA1_TARGETS_DISABLE = 0x1989 # macro -regGCRD_SA1_TARGETS_DISABLE_BASE_IDX = 1 # macro -regGCRD_CREDIT_SAFE = 0x198a # macro -regGCRD_CREDIT_SAFE_BASE_IDX = 1 # macro -regGCR_GENERAL_CNTL = 0x1990 # macro -regGCR_GENERAL_CNTL_BASE_IDX = 1 # macro -regGCR_CMD_STATUS = 0x1992 # macro -regGCR_CMD_STATUS_BASE_IDX = 1 # macro -regGCR_SPARE = 0x1993 # macro -regGCR_SPARE_BASE_IDX = 1 # macro -regPMM_CNTL2 = 0x1999 # macro -regPMM_CNTL2_BASE_IDX = 1 # macro -regSEDC_GL1_GL2_OVERRIDES = 0x1ac0 # macro -regSEDC_GL1_GL2_OVERRIDES_BASE_IDX = 1 # macro -regGC_CAC_CTRL_1 = 0x1ad0 # macro -regGC_CAC_CTRL_1_BASE_IDX = 1 # macro -regGC_CAC_CTRL_2 = 0x1ad1 # macro -regGC_CAC_CTRL_2_BASE_IDX = 1 # macro -regGC_CAC_AGGR_LOWER = 0x1ad2 # macro -regGC_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regGC_CAC_AGGR_UPPER = 0x1ad3 # macro -regGC_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE0_CAC_AGGR_LOWER = 0x1ad4 # macro -regSE0_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE0_CAC_AGGR_UPPER = 0x1ad5 # macro -regSE0_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE1_CAC_AGGR_LOWER = 0x1ad6 # macro -regSE1_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE1_CAC_AGGR_UPPER = 0x1ad7 # macro -regSE1_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE2_CAC_AGGR_LOWER = 0x1ad8 # macro -regSE2_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE2_CAC_AGGR_UPPER = 0x1ad9 # macro -regSE2_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE3_CAC_AGGR_LOWER = 0x1ada # macro -regSE3_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE3_CAC_AGGR_UPPER = 0x1adb # macro -regSE3_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE4_CAC_AGGR_LOWER = 0x1adc # macro -regSE4_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE4_CAC_AGGR_UPPER = 0x1add # macro -regSE4_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regSE5_CAC_AGGR_LOWER = 0x1ade # macro -regSE5_CAC_AGGR_LOWER_BASE_IDX = 1 # macro -regSE5_CAC_AGGR_UPPER = 0x1adf # macro -regSE5_CAC_AGGR_UPPER_BASE_IDX = 1 # macro -regGC_CAC_AGGR_GFXCLK_CYCLE = 0x1ae4 # macro -regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE0_CAC_AGGR_GFXCLK_CYCLE = 0x1ae5 # macro -regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE1_CAC_AGGR_GFXCLK_CYCLE = 0x1ae6 # macro -regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE2_CAC_AGGR_GFXCLK_CYCLE = 0x1ae7 # macro -regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE3_CAC_AGGR_GFXCLK_CYCLE = 0x1ae8 # macro -regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE4_CAC_AGGR_GFXCLK_CYCLE = 0x1ae9 # macro -regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE5_CAC_AGGR_GFXCLK_CYCLE = 0x1aea # macro -regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regGC_EDC_CTRL = 0x1aed # macro -regGC_EDC_CTRL_BASE_IDX = 1 # macro -regGC_EDC_THRESHOLD = 0x1aee # macro -regGC_EDC_THRESHOLD_BASE_IDX = 1 # macro -regGC_EDC_STRETCH_CTRL = 0x1aef # macro -regGC_EDC_STRETCH_CTRL_BASE_IDX = 1 # macro -regGC_EDC_STRETCH_THRESHOLD = 0x1af0 # macro -regGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 1 # macro -regEDC_HYSTERESIS_CNTL = 0x1af1 # macro -regEDC_HYSTERESIS_CNTL_BASE_IDX = 1 # macro -regGC_THROTTLE_CTRL = 0x1af2 # macro -regGC_THROTTLE_CTRL_BASE_IDX = 1 # macro -regGC_THROTTLE_CTRL1 = 0x1af3 # macro -regGC_THROTTLE_CTRL1_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_CTRL = 0x1af4 # macro -regPCC_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_CTRL = 0x1af5 # macro -regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_1_2 = 0x1af6 # macro -regPCC_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_3_4 = 0x1af7 # macro -regPCC_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_5_6 = 0x1af8 # macro -regPCC_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regPCC_STALL_PATTERN_7 = 0x1af9 # macro -regPCC_STALL_PATTERN_7_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_1_2 = 0x1afa # macro -regPWRBRK_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_3_4 = 0x1afb # macro -regPWRBRK_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_5_6 = 0x1afc # macro -regPWRBRK_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regPWRBRK_STALL_PATTERN_7 = 0x1afd # macro -regPWRBRK_STALL_PATTERN_7_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_CTRL = 0x1afe # macro -regDIDT_STALL_PATTERN_CTRL_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_1_2 = 0x1aff # macro -regDIDT_STALL_PATTERN_1_2_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_3_4 = 0x1b00 # macro -regDIDT_STALL_PATTERN_3_4_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_5_6 = 0x1b01 # macro -regDIDT_STALL_PATTERN_5_6_BASE_IDX = 1 # macro -regDIDT_STALL_PATTERN_7 = 0x1b02 # macro -regDIDT_STALL_PATTERN_7_BASE_IDX = 1 # macro -regPCC_PWRBRK_HYSTERESIS_CTRL = 0x1b03 # macro -regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX = 1 # macro -regEDC_STRETCH_PERF_COUNTER = 0x1b04 # macro -regEDC_STRETCH_PERF_COUNTER_BASE_IDX = 1 # macro -regEDC_UNSTRETCH_PERF_COUNTER = 0x1b05 # macro -regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX = 1 # macro -regEDC_STRETCH_NUM_PERF_COUNTER = 0x1b06 # macro -regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX = 1 # macro -regGC_EDC_STATUS = 0x1b07 # macro -regGC_EDC_STATUS_BASE_IDX = 1 # macro -regGC_EDC_OVERFLOW = 0x1b08 # macro -regGC_EDC_OVERFLOW_BASE_IDX = 1 # macro -regGC_EDC_ROLLING_POWER_DELTA = 0x1b09 # macro -regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 # macro -regGC_THROTTLE_STATUS = 0x1b0a # macro -regGC_THROTTLE_STATUS_BASE_IDX = 1 # macro -regEDC_PERF_COUNTER = 0x1b0b # macro -regEDC_PERF_COUNTER_BASE_IDX = 1 # macro -regPCC_PERF_COUNTER = 0x1b0c # macro -regPCC_PERF_COUNTER_BASE_IDX = 1 # macro -regPWRBRK_PERF_COUNTER = 0x1b0d # macro -regPWRBRK_PERF_COUNTER_BASE_IDX = 1 # macro -regEDC_HYSTERESIS_STAT = 0x1b0e # macro -regEDC_HYSTERESIS_STAT_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CP_0 = 0x1b10 # macro -regGC_CAC_WEIGHT_CP_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CP_1 = 0x1b11 # macro -regGC_CAC_WEIGHT_CP_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_EA_0 = 0x1b12 # macro -regGC_CAC_WEIGHT_EA_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_EA_1 = 0x1b13 # macro -regGC_CAC_WEIGHT_EA_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_EA_2 = 0x1b14 # macro -regGC_CAC_WEIGHT_EA_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x1b15 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x1b16 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x1b17 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x1b18 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x1b19 # macro -regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x1b1a # macro -regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x1b1b # macro -regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x1b1c # macro -regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x1b1d # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x1b1e # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x1b1f # macro -regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GDS_0 = 0x1b20 # macro -regGC_CAC_WEIGHT_GDS_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GDS_1 = 0x1b21 # macro -regGC_CAC_WEIGHT_GDS_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GDS_2 = 0x1b22 # macro -regGC_CAC_WEIGHT_GDS_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_0 = 0x1b23 # macro -regGC_CAC_WEIGHT_GE_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_1 = 0x1b24 # macro -regGC_CAC_WEIGHT_GE_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_2 = 0x1b25 # macro -regGC_CAC_WEIGHT_GE_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_3 = 0x1b26 # macro -regGC_CAC_WEIGHT_GE_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_4 = 0x1b27 # macro -regGC_CAC_WEIGHT_GE_4_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_5 = 0x1b28 # macro -regGC_CAC_WEIGHT_GE_5_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GE_6 = 0x1b29 # macro -regGC_CAC_WEIGHT_GE_6_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PMM_0 = 0x1b2e # macro -regGC_CAC_WEIGHT_PMM_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GL2C_0 = 0x1b2f # macro -regGC_CAC_WEIGHT_GL2C_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GL2C_1 = 0x1b30 # macro -regGC_CAC_WEIGHT_GL2C_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GL2C_2 = 0x1b31 # macro -regGC_CAC_WEIGHT_GL2C_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_0 = 0x1b32 # macro -regGC_CAC_WEIGHT_PH_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_1 = 0x1b33 # macro -regGC_CAC_WEIGHT_PH_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_2 = 0x1b34 # macro -regGC_CAC_WEIGHT_PH_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_PH_3 = 0x1b35 # macro -regGC_CAC_WEIGHT_PH_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_0 = 0x1b36 # macro -regGC_CAC_WEIGHT_SDMA_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_1 = 0x1b37 # macro -regGC_CAC_WEIGHT_SDMA_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_2 = 0x1b38 # macro -regGC_CAC_WEIGHT_SDMA_2_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_3 = 0x1b39 # macro -regGC_CAC_WEIGHT_SDMA_3_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_4 = 0x1b3a # macro -regGC_CAC_WEIGHT_SDMA_4_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_SDMA_5 = 0x1b3b # macro -regGC_CAC_WEIGHT_SDMA_5_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CHC_0 = 0x1b3c # macro -regGC_CAC_WEIGHT_CHC_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_CHC_1 = 0x1b3d # macro -regGC_CAC_WEIGHT_CHC_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GUS_0 = 0x1b3e # macro -regGC_CAC_WEIGHT_GUS_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GUS_1 = 0x1b3f # macro -regGC_CAC_WEIGHT_GUS_1_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_RLC_0 = 0x1b40 # macro -regGC_CAC_WEIGHT_RLC_0_BASE_IDX = 1 # macro -regGC_CAC_WEIGHT_GRBM_0 = 0x1b44 # macro -regGC_CAC_WEIGHT_GRBM_0_BASE_IDX = 1 # macro -regGC_EDC_CLK_MONITOR_CTRL = 0x1b56 # macro -regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX = 1 # macro -regGC_CAC_IND_INDEX = 0x1b58 # macro -regGC_CAC_IND_INDEX_BASE_IDX = 1 # macro -regGC_CAC_IND_DATA = 0x1b59 # macro -regGC_CAC_IND_DATA_BASE_IDX = 1 # macro -regSE_CAC_CTRL_1 = 0x1b70 # macro -regSE_CAC_CTRL_1_BASE_IDX = 1 # macro -regSE_CAC_CTRL_2 = 0x1b71 # macro -regSE_CAC_CTRL_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TA_0 = 0x1b72 # macro -regSE_CAC_WEIGHT_TA_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_0 = 0x1b73 # macro -regSE_CAC_WEIGHT_TD_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_1 = 0x1b74 # macro -regSE_CAC_WEIGHT_TD_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_2 = 0x1b75 # macro -regSE_CAC_WEIGHT_TD_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_3 = 0x1b76 # macro -regSE_CAC_WEIGHT_TD_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_4 = 0x1b77 # macro -regSE_CAC_WEIGHT_TD_4_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TD_5 = 0x1b78 # macro -regSE_CAC_WEIGHT_TD_5_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_0 = 0x1b79 # macro -regSE_CAC_WEIGHT_TCP_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_1 = 0x1b7a # macro -regSE_CAC_WEIGHT_TCP_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_2 = 0x1b7b # macro -regSE_CAC_WEIGHT_TCP_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_TCP_3 = 0x1b7c # macro -regSE_CAC_WEIGHT_TCP_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQ_0 = 0x1b7d # macro -regSE_CAC_WEIGHT_SQ_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQ_1 = 0x1b7e # macro -regSE_CAC_WEIGHT_SQ_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQ_2 = 0x1b7f # macro -regSE_CAC_WEIGHT_SQ_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SP_0 = 0x1b80 # macro -regSE_CAC_WEIGHT_SP_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SP_1 = 0x1b81 # macro -regSE_CAC_WEIGHT_SP_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_0 = 0x1b82 # macro -regSE_CAC_WEIGHT_LDS_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_1 = 0x1b83 # macro -regSE_CAC_WEIGHT_LDS_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_2 = 0x1b84 # macro -regSE_CAC_WEIGHT_LDS_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_LDS_3 = 0x1b85 # macro -regSE_CAC_WEIGHT_LDS_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQC_0 = 0x1b87 # macro -regSE_CAC_WEIGHT_SQC_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SQC_1 = 0x1b88 # macro -regSE_CAC_WEIGHT_SQC_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CU_0 = 0x1b89 # macro -regSE_CAC_WEIGHT_CU_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_BCI_0 = 0x1b8a # macro -regSE_CAC_WEIGHT_BCI_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_0 = 0x1b8b # macro -regSE_CAC_WEIGHT_CB_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_1 = 0x1b8c # macro -regSE_CAC_WEIGHT_CB_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_2 = 0x1b8d # macro -regSE_CAC_WEIGHT_CB_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_3 = 0x1b8e # macro -regSE_CAC_WEIGHT_CB_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_4 = 0x1b8f # macro -regSE_CAC_WEIGHT_CB_4_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_5 = 0x1b90 # macro -regSE_CAC_WEIGHT_CB_5_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_6 = 0x1b91 # macro -regSE_CAC_WEIGHT_CB_6_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_7 = 0x1b92 # macro -regSE_CAC_WEIGHT_CB_7_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_8 = 0x1b93 # macro -regSE_CAC_WEIGHT_CB_8_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_9 = 0x1b94 # macro -regSE_CAC_WEIGHT_CB_9_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_10 = 0x1b95 # macro -regSE_CAC_WEIGHT_CB_10_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_CB_11 = 0x1b96 # macro -regSE_CAC_WEIGHT_CB_11_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_0 = 0x1b97 # macro -regSE_CAC_WEIGHT_DB_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_1 = 0x1b98 # macro -regSE_CAC_WEIGHT_DB_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_2 = 0x1b99 # macro -regSE_CAC_WEIGHT_DB_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_3 = 0x1b9a # macro -regSE_CAC_WEIGHT_DB_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_DB_4 = 0x1b9b # macro -regSE_CAC_WEIGHT_DB_4_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_RMI_0 = 0x1b9c # macro -regSE_CAC_WEIGHT_RMI_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_RMI_1 = 0x1b9d # macro -regSE_CAC_WEIGHT_RMI_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SX_0 = 0x1b9e # macro -regSE_CAC_WEIGHT_SX_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SXRB_0 = 0x1b9f # macro -regSE_CAC_WEIGHT_SXRB_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_UTCL1_0 = 0x1ba0 # macro -regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_GL1C_0 = 0x1ba1 # macro -regSE_CAC_WEIGHT_GL1C_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_GL1C_1 = 0x1ba2 # macro -regSE_CAC_WEIGHT_GL1C_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_GL1C_2 = 0x1ba3 # macro -regSE_CAC_WEIGHT_GL1C_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SPI_0 = 0x1ba4 # macro -regSE_CAC_WEIGHT_SPI_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SPI_1 = 0x1ba5 # macro -regSE_CAC_WEIGHT_SPI_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SPI_2 = 0x1ba6 # macro -regSE_CAC_WEIGHT_SPI_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PC_0 = 0x1ba7 # macro -regSE_CAC_WEIGHT_PC_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_0 = 0x1ba8 # macro -regSE_CAC_WEIGHT_PA_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_1 = 0x1ba9 # macro -regSE_CAC_WEIGHT_PA_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_2 = 0x1baa # macro -regSE_CAC_WEIGHT_PA_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_PA_3 = 0x1bab # macro -regSE_CAC_WEIGHT_PA_3_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_0 = 0x1bac # macro -regSE_CAC_WEIGHT_SC_0_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_1 = 0x1bad # macro -regSE_CAC_WEIGHT_SC_1_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_2 = 0x1bae # macro -regSE_CAC_WEIGHT_SC_2_BASE_IDX = 1 # macro -regSE_CAC_WEIGHT_SC_3 = 0x1baf # macro -regSE_CAC_WEIGHT_SC_3_BASE_IDX = 1 # macro -regSE_CAC_WINDOW_AGGR_VALUE = 0x1bb0 # macro -regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX = 1 # macro -regSE_CAC_WINDOW_GFXCLK_CYCLE = 0x1bb1 # macro -regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX = 1 # macro -regSE_CAC_IND_INDEX = 0x1bce # macro -regSE_CAC_IND_INDEX_BASE_IDX = 1 # macro -regSE_CAC_IND_DATA = 0x1bcf # macro -regSE_CAC_IND_DATA_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_0 = 0x1c00 # macro -regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_1 = 0x1c01 # macro -regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_2 = 0x1c02 # macro -regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_3 = 0x1c03 # macro -regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_4 = 0x1c04 # macro -regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_5 = 0x1c05 # macro -regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_6 = 0x1c06 # macro -regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_7 = 0x1c07 # macro -regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_8 = 0x1c08 # macro -regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_9 = 0x1c09 # macro -regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_10 = 0x1c0a # macro -regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_11 = 0x1c0b # macro -regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_12 = 0x1c0c # macro -regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_13 = 0x1c0d # macro -regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_14 = 0x1c0e # macro -regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_CU_15 = 0x1c0f # macro -regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1c10 # macro -regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1c11 # macro -regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1c12 # macro -regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1c13 # macro -regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1c14 # macro -regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1c15 # macro -regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1c16 # macro -regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1c17 # macro -regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1c18 # macro -regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1c19 # macro -regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x1c1a # macro -regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x1c1b # macro -regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x1c1c # macro -regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x1c1d # macro -regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x1c1e # macro -regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 1 # macro -regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x1c1f # macro -regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 1 # macro -regCP_EOP_DONE_ADDR_LO = 0x2000 # macro -regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro -regCP_EOP_DONE_ADDR_HI = 0x2001 # macro -regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro -regCP_EOP_DONE_DATA_LO = 0x2002 # macro -regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro -regCP_EOP_DONE_DATA_HI = 0x2003 # macro -regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro -regCP_EOP_LAST_FENCE_LO = 0x2004 # macro -regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro -regCP_EOP_LAST_FENCE_HI = 0x2005 # macro -regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro -regCP_PIPE_STATS_ADDR_LO = 0x2018 # macro -regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro -regCP_PIPE_STATS_ADDR_HI = 0x2019 # macro -regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro -regCP_VGT_IAVERT_COUNT_LO = 0x201a # macro -regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_IAVERT_COUNT_HI = 0x201b # macro -regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro -regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro -regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro -regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro -regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro -regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro -regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro -regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro -regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro -regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro -regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro -regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro -regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_PA_CINVOC_COUNT_LO = 0x2028 # macro -regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_PA_CINVOC_COUNT_HI = 0x2029 # macro -regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_PA_CPRIM_COUNT_LO = 0x202a # macro -regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_PA_CPRIM_COUNT_HI = 0x202b # macro -regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro -regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro -regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro -regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro -regCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro -regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro -regCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro -regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro -regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_VGT_ASINVOC_COUNT_LO = 0x2032 # macro -regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_VGT_ASINVOC_COUNT_HI = 0x2033 # macro -regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_PIPE_STATS_CONTROL = 0x203d # macro -regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro -regSCRATCH_REG0 = 0x2040 # macro -regSCRATCH_REG0_BASE_IDX = 1 # macro -regSCRATCH_REG1 = 0x2041 # macro -regSCRATCH_REG1_BASE_IDX = 1 # macro -regSCRATCH_REG2 = 0x2042 # macro -regSCRATCH_REG2_BASE_IDX = 1 # macro -regSCRATCH_REG3 = 0x2043 # macro -regSCRATCH_REG3_BASE_IDX = 1 # macro -regSCRATCH_REG4 = 0x2044 # macro -regSCRATCH_REG4_BASE_IDX = 1 # macro -regSCRATCH_REG5 = 0x2045 # macro -regSCRATCH_REG5_BASE_IDX = 1 # macro -regSCRATCH_REG6 = 0x2046 # macro -regSCRATCH_REG6_BASE_IDX = 1 # macro -regSCRATCH_REG7 = 0x2047 # macro -regSCRATCH_REG7_BASE_IDX = 1 # macro -regSCRATCH_REG_ATOMIC = 0x2048 # macro -regSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro -regSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro -regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro -regCP_APPEND_DDID_CNT = 0x204b # macro -regCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro -regCP_APPEND_DATA_HI = 0x204c # macro -regCP_APPEND_DATA_HI_BASE_IDX = 1 # macro -regCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro -regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro -regCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro -regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro -regCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro -regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -regCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro -regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro -regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro -regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -regCP_APPEND_ADDR_LO = 0x2058 # macro -regCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro -regCP_APPEND_ADDR_HI = 0x2059 # macro -regCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro -regCP_APPEND_DATA = 0x205a # macro -regCP_APPEND_DATA_BASE_IDX = 1 # macro -regCP_APPEND_DATA_LO = 0x205a # macro -regCP_APPEND_DATA_LO_BASE_IDX = 1 # macro -regCP_APPEND_LAST_CS_FENCE = 0x205b # macro -regCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro -regCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro -regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro -regCP_APPEND_LAST_PS_FENCE = 0x205c # macro -regCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro -regCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro -regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro -regCP_ATOMIC_PREOP_LO = 0x205d # macro -regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -regCP_ME_ATOMIC_PREOP_LO = 0x205d # macro -regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro -regCP_ATOMIC_PREOP_HI = 0x205e # macro -regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_ATOMIC_PREOP_HI = 0x205e # macro -regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro -regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro -regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro -regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro -regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro -regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro -regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro -regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro -regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro -regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro -regCP_ME_MC_WADDR_LO = 0x2069 # macro -regCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro -regCP_ME_MC_WADDR_HI = 0x206a # macro -regCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro -regCP_ME_MC_WDATA_LO = 0x206b # macro -regCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro -regCP_ME_MC_WDATA_HI = 0x206c # macro -regCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro -regCP_ME_MC_RADDR_LO = 0x206d # macro -regCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro -regCP_ME_MC_RADDR_HI = 0x206e # macro -regCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro -regCP_SEM_WAIT_TIMER = 0x206f # macro -regCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro -regCP_SIG_SEM_ADDR_LO = 0x2070 # macro -regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro -regCP_SIG_SEM_ADDR_HI = 0x2071 # macro -regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro -regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro -regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro -regCP_WAIT_SEM_ADDR_LO = 0x2075 # macro -regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro -regCP_WAIT_SEM_ADDR_HI = 0x2076 # macro -regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_CONTROL = 0x2077 # macro -regCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro -regCP_DMA_ME_CONTROL = 0x2078 # macro -regCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro -regCP_DMA_ME_SRC_ADDR = 0x2080 # macro -regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro -regCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro -regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_ME_DST_ADDR = 0x2082 # macro -regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro -regCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro -regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_ME_COMMAND = 0x2084 # macro -regCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro -regCP_DMA_PFP_SRC_ADDR = 0x2085 # macro -regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro -regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro -regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_DST_ADDR = 0x2087 # macro -regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro -regCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro -regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_COMMAND = 0x2089 # macro -regCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro -regCP_DMA_CNTL = 0x208a # macro -regCP_DMA_CNTL_BASE_IDX = 1 # macro -regCP_DMA_READ_TAGS = 0x208b # macro -regCP_DMA_READ_TAGS_BASE_IDX = 1 # macro -regCP_PFP_IB_CONTROL = 0x208d # macro -regCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro -regCP_PFP_LOAD_CONTROL = 0x208e # macro -regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro -regCP_SCRATCH_INDEX = 0x208f # macro -regCP_SCRATCH_INDEX_BASE_IDX = 1 # macro -regCP_SCRATCH_DATA = 0x2090 # macro -regCP_SCRATCH_DATA_BASE_IDX = 1 # macro -regCP_RB_OFFSET = 0x2091 # macro -regCP_RB_OFFSET_BASE_IDX = 1 # macro -regCP_IB2_OFFSET = 0x2093 # macro -regCP_IB2_OFFSET_BASE_IDX = 1 # macro -regCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro -regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro -regCP_IB2_PREAMBLE_END = 0x2097 # macro -regCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro -regCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro -regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro -regCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro -regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro -regCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro -regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro -regCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro -regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro -regCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro -regCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro -regCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro -regCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro -regUCONFIG_RESERVED_REG0 = 0x20a2 # macro -regUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro -regUCONFIG_RESERVED_REG1 = 0x20a3 # macro -regUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro -regCP_PA_MSPRIM_COUNT_LO = 0x20a4 # macro -regCP_PA_MSPRIM_COUNT_LO_BASE_IDX = 1 # macro -regCP_PA_MSPRIM_COUNT_HI = 0x20a5 # macro -regCP_PA_MSPRIM_COUNT_HI_BASE_IDX = 1 # macro -regCP_GE_MSINVOC_COUNT_LO = 0x20a6 # macro -regCP_GE_MSINVOC_COUNT_LO_BASE_IDX = 1 # macro -regCP_GE_MSINVOC_COUNT_HI = 0x20a7 # macro -regCP_GE_MSINVOC_COUNT_HI_BASE_IDX = 1 # macro -regCP_IB1_CMD_BUFSZ = 0x20c0 # macro -regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_IB2_CMD_BUFSZ = 0x20c1 # macro -regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_ST_CMD_BUFSZ = 0x20c2 # macro -regCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_IB1_BASE_LO = 0x20cc # macro -regCP_IB1_BASE_LO_BASE_IDX = 1 # macro -regCP_IB1_BASE_HI = 0x20cd # macro -regCP_IB1_BASE_HI_BASE_IDX = 1 # macro -regCP_IB1_BUFSZ = 0x20ce # macro -regCP_IB1_BUFSZ_BASE_IDX = 1 # macro -regCP_IB2_BASE_LO = 0x20cf # macro -regCP_IB2_BASE_LO_BASE_IDX = 1 # macro -regCP_IB2_BASE_HI = 0x20d0 # macro -regCP_IB2_BASE_HI_BASE_IDX = 1 # macro -regCP_IB2_BUFSZ = 0x20d1 # macro -regCP_IB2_BUFSZ_BASE_IDX = 1 # macro -regCP_ST_BASE_LO = 0x20d2 # macro -regCP_ST_BASE_LO_BASE_IDX = 1 # macro -regCP_ST_BASE_HI = 0x20d3 # macro -regCP_ST_BASE_HI_BASE_IDX = 1 # macro -regCP_ST_BUFSZ = 0x20d4 # macro -regCP_ST_BUFSZ_BASE_IDX = 1 # macro -regCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro -regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro -regCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro -regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro -regCP_EOP_DONE_CNTX_ID = 0x20d7 # macro -regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro -regCP_DB_BASE_LO = 0x20d8 # macro -regCP_DB_BASE_LO_BASE_IDX = 1 # macro -regCP_DB_BASE_HI = 0x20d9 # macro -regCP_DB_BASE_HI_BASE_IDX = 1 # macro -regCP_DB_BUFSZ = 0x20da # macro -regCP_DB_BUFSZ_BASE_IDX = 1 # macro -regCP_DB_CMD_BUFSZ = 0x20db # macro -regCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro -regCP_PFP_COMPLETION_STATUS = 0x20ec # macro -regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro -regCP_PRED_NOT_VISIBLE = 0x20ee # macro -regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro -regCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro -regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro -regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro -regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro -regCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro -regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro -regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro -regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro -regCP_DISPATCH_INDR_ADDR = 0x20f6 # macro -regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro -regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro -regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro -regCP_INDEX_BASE_ADDR = 0x20f8 # macro -regCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro -regCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro -regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro -regCP_INDEX_TYPE = 0x20fa # macro -regCP_INDEX_TYPE_BASE_IDX = 1 # macro -regCP_GDS_BKUP_ADDR = 0x20fb # macro -regCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro -regCP_GDS_BKUP_ADDR_HI = 0x20fc # macro -regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro -regCP_SAMPLE_STATUS = 0x20fd # macro -regCP_SAMPLE_STATUS_BASE_IDX = 1 # macro -regCP_ME_COHER_CNTL = 0x20fe # macro -regCP_ME_COHER_CNTL_BASE_IDX = 1 # macro -regCP_ME_COHER_SIZE = 0x20ff # macro -regCP_ME_COHER_SIZE_BASE_IDX = 1 # macro -regCP_ME_COHER_SIZE_HI = 0x2100 # macro -regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro -regCP_ME_COHER_BASE = 0x2101 # macro -regCP_ME_COHER_BASE_BASE_IDX = 1 # macro -regCP_ME_COHER_BASE_HI = 0x2102 # macro -regCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro -regCP_ME_COHER_STATUS = 0x2103 # macro -regCP_ME_COHER_STATUS_BASE_IDX = 1 # macro -regRLC_GPM_PERF_COUNT_0 = 0x2140 # macro -regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro -regRLC_GPM_PERF_COUNT_1 = 0x2141 # macro -regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro -regGRBM_GFX_INDEX = 0x2200 # macro -regGRBM_GFX_INDEX_BASE_IDX = 1 # macro -regVGT_PRIMITIVE_TYPE = 0x2242 # macro -regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro -regVGT_INDEX_TYPE = 0x2243 # macro -regVGT_INDEX_TYPE_BASE_IDX = 1 # macro -regGE_MIN_VTX_INDX = 0x2249 # macro -regGE_MIN_VTX_INDX_BASE_IDX = 1 # macro -regGE_INDX_OFFSET = 0x224a # macro -regGE_INDX_OFFSET_BASE_IDX = 1 # macro -regGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro -regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro -regVGT_NUM_INDICES = 0x224c # macro -regVGT_NUM_INDICES_BASE_IDX = 1 # macro -regVGT_NUM_INSTANCES = 0x224d # macro -regVGT_NUM_INSTANCES_BASE_IDX = 1 # macro -regVGT_TF_RING_SIZE = 0x224e # macro -regVGT_TF_RING_SIZE_BASE_IDX = 1 # macro -regVGT_HS_OFFCHIP_PARAM = 0x224f # macro -regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 # macro -regVGT_TF_MEMORY_BASE = 0x2250 # macro -regVGT_TF_MEMORY_BASE_BASE_IDX = 1 # macro -regGE_MAX_VTX_INDX = 0x2259 # macro -regGE_MAX_VTX_INDX_BASE_IDX = 1 # macro -regVGT_INSTANCE_BASE_ID = 0x225a # macro -regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro -regGE_CNTL = 0x225b # macro -regGE_CNTL_BASE_IDX = 1 # macro -regGE_USER_VGPR1 = 0x225c # macro -regGE_USER_VGPR1_BASE_IDX = 1 # macro -regGE_USER_VGPR2 = 0x225d # macro -regGE_USER_VGPR2_BASE_IDX = 1 # macro -regGE_USER_VGPR3 = 0x225e # macro -regGE_USER_VGPR3_BASE_IDX = 1 # macro -regGE_STEREO_CNTL = 0x225f # macro -regGE_STEREO_CNTL_BASE_IDX = 1 # macro -regGE_PC_ALLOC = 0x2260 # macro -regGE_PC_ALLOC_BASE_IDX = 1 # macro -regVGT_TF_MEMORY_BASE_HI = 0x2261 # macro -regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 # macro -regGE_USER_VGPR_EN = 0x2262 # macro -regGE_USER_VGPR_EN_BASE_IDX = 1 # macro -regGE_GS_FAST_LAUNCH_WG_DIM = 0x2264 # macro -regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX = 1 # macro -regGE_GS_FAST_LAUNCH_WG_DIM_1 = 0x2265 # macro -regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX = 1 # macro -regVGT_GS_OUT_PRIM_TYPE = 0x2266 # macro -regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro -regPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro -regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro -regPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro -regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro -regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro -regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro -regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro -regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro -regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro -regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro -regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro -regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro -regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro -regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro -regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro -regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro -regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro -regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro -regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro -regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_H = 0x22b1 # macro -regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_V = 0x22b2 # macro -regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro -regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro -regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro -regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro -regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro -regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro -regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro -regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro -regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro -regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro -regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro -regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro -regSQC_CACHES = 0x2348 # macro -regSQC_CACHES_BASE_IDX = 1 # macro -regTA_CS_BC_BASE_ADDR = 0x2380 # macro -regTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro -regTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro -regTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro -regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro -regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro -regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro -regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro -regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro -regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro -regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro -regDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro -regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro -regGDS_RD_ADDR = 0x2400 # macro -regGDS_RD_ADDR_BASE_IDX = 1 # macro -regGDS_RD_DATA = 0x2401 # macro -regGDS_RD_DATA_BASE_IDX = 1 # macro -regGDS_RD_BURST_ADDR = 0x2402 # macro -regGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro -regGDS_RD_BURST_COUNT = 0x2403 # macro -regGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro -regGDS_RD_BURST_DATA = 0x2404 # macro -regGDS_RD_BURST_DATA_BASE_IDX = 1 # macro -regGDS_WR_ADDR = 0x2405 # macro -regGDS_WR_ADDR_BASE_IDX = 1 # macro -regGDS_WR_DATA = 0x2406 # macro -regGDS_WR_DATA_BASE_IDX = 1 # macro -regGDS_WR_BURST_ADDR = 0x2407 # macro -regGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro -regGDS_WR_BURST_DATA = 0x2408 # macro -regGDS_WR_BURST_DATA_BASE_IDX = 1 # macro -regGDS_WRITE_COMPLETE = 0x2409 # macro -regGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro -regGDS_ATOM_CNTL = 0x240a # macro -regGDS_ATOM_CNTL_BASE_IDX = 1 # macro -regGDS_ATOM_COMPLETE = 0x240b # macro -regGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro -regGDS_ATOM_BASE = 0x240c # macro -regGDS_ATOM_BASE_BASE_IDX = 1 # macro -regGDS_ATOM_SIZE = 0x240d # macro -regGDS_ATOM_SIZE_BASE_IDX = 1 # macro -regGDS_ATOM_OFFSET0 = 0x240e # macro -regGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro -regGDS_ATOM_OFFSET1 = 0x240f # macro -regGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro -regGDS_ATOM_DST = 0x2410 # macro -regGDS_ATOM_DST_BASE_IDX = 1 # macro -regGDS_ATOM_OP = 0x2411 # macro -regGDS_ATOM_OP_BASE_IDX = 1 # macro -regGDS_ATOM_SRC0 = 0x2412 # macro -regGDS_ATOM_SRC0_BASE_IDX = 1 # macro -regGDS_ATOM_SRC0_U = 0x2413 # macro -regGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro -regGDS_ATOM_SRC1 = 0x2414 # macro -regGDS_ATOM_SRC1_BASE_IDX = 1 # macro -regGDS_ATOM_SRC1_U = 0x2415 # macro -regGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro -regGDS_ATOM_READ0 = 0x2416 # macro -regGDS_ATOM_READ0_BASE_IDX = 1 # macro -regGDS_ATOM_READ0_U = 0x2417 # macro -regGDS_ATOM_READ0_U_BASE_IDX = 1 # macro -regGDS_ATOM_READ1 = 0x2418 # macro -regGDS_ATOM_READ1_BASE_IDX = 1 # macro -regGDS_ATOM_READ1_U = 0x2419 # macro -regGDS_ATOM_READ1_U_BASE_IDX = 1 # macro -regGDS_GWS_RESOURCE_CNTL = 0x241a # macro -regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro -regGDS_GWS_RESOURCE = 0x241b # macro -regGDS_GWS_RESOURCE_BASE_IDX = 1 # macro -regGDS_GWS_RESOURCE_CNT = 0x241c # macro -regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro -regGDS_OA_CNTL = 0x241d # macro -regGDS_OA_CNTL_BASE_IDX = 1 # macro -regGDS_OA_COUNTER = 0x241e # macro -regGDS_OA_COUNTER_BASE_IDX = 1 # macro -regGDS_OA_ADDRESS = 0x241f # macro -regGDS_OA_ADDRESS_BASE_IDX = 1 # macro -regGDS_OA_INCDEC = 0x2420 # macro -regGDS_OA_INCDEC_BASE_IDX = 1 # macro -regGDS_OA_RING_SIZE = 0x2421 # macro -regGDS_OA_RING_SIZE_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_0 = 0x2422 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_1 = 0x2423 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_2 = 0x2424 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX = 1 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_3 = 0x2425 # macro -regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX = 1 # macro -regGDS_GS_0 = 0x2426 # macro -regGDS_GS_0_BASE_IDX = 1 # macro -regGDS_GS_1 = 0x2427 # macro -regGDS_GS_1_BASE_IDX = 1 # macro -regGDS_GS_2 = 0x2428 # macro -regGDS_GS_2_BASE_IDX = 1 # macro -regGDS_GS_3 = 0x2429 # macro -regGDS_GS_3_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_LO = 0x242a # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_HI = 0x242b # macro -regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_LO = 0x242c # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_HI = 0x242d # macro -regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_LO = 0x242e # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_HI = 0x242f # macro -regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_LO = 0x2430 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_HI = 0x2431 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_LO = 0x2432 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_HI = 0x2433 # macro -regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_LO = 0x2434 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_HI = 0x2435 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_LO = 0x2436 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_HI = 0x2437 # macro -regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_LO = 0x2438 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX = 1 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_HI = 0x2439 # macro -regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX = 1 # macro -regSPI_CONFIG_CNTL = 0x2440 # macro -regSPI_CONFIG_CNTL_BASE_IDX = 1 # macro -regSPI_CONFIG_CNTL_1 = 0x2441 # macro -regSPI_CONFIG_CNTL_1_BASE_IDX = 1 # macro -regSPI_CONFIG_CNTL_2 = 0x2442 # macro -regSPI_CONFIG_CNTL_2_BASE_IDX = 1 # macro -regSPI_WAVE_LIMIT_CNTL = 0x2443 # macro -regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 # macro -regSPI_GS_THROTTLE_CNTL1 = 0x2444 # macro -regSPI_GS_THROTTLE_CNTL1_BASE_IDX = 1 # macro -regSPI_GS_THROTTLE_CNTL2 = 0x2445 # macro -regSPI_GS_THROTTLE_CNTL2_BASE_IDX = 1 # macro -regSPI_ATTRIBUTE_RING_BASE = 0x2446 # macro -regSPI_ATTRIBUTE_RING_BASE_BASE_IDX = 1 # macro -regSPI_ATTRIBUTE_RING_SIZE = 0x2447 # macro -regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX = 1 # macro -regCP_MES_PRGRM_CNTR_START = 0x2800 # macro -regCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro -regCP_MES_INTR_ROUTINE_START = 0x2801 # macro -regCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro -regCP_MES_MTVEC_LO = 0x2801 # macro -regCP_MES_MTVEC_LO_BASE_IDX = 1 # macro -regCP_MES_INTR_ROUTINE_START_HI = 0x2802 # macro -regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX = 1 # macro -regCP_MES_MTVEC_HI = 0x2802 # macro -regCP_MES_MTVEC_HI_BASE_IDX = 1 # macro -regCP_MES_CNTL = 0x2807 # macro -regCP_MES_CNTL_BASE_IDX = 1 # macro -regCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro -regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro -regCP_MES_PIPE0_PRIORITY = 0x2809 # macro -regCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_PIPE1_PRIORITY = 0x280a # macro -regCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_PIPE2_PRIORITY = 0x280b # macro -regCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_PIPE3_PRIORITY = 0x280c # macro -regCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro -regCP_MES_HEADER_DUMP = 0x280d # macro -regCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro -regCP_MES_MIE_LO = 0x280e # macro -regCP_MES_MIE_LO_BASE_IDX = 1 # macro -regCP_MES_MIE_HI = 0x280f # macro -regCP_MES_MIE_HI_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT = 0x2810 # macro -regCP_MES_INTERRUPT_BASE_IDX = 1 # macro -regCP_MES_SCRATCH_INDEX = 0x2811 # macro -regCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro -regCP_MES_SCRATCH_DATA = 0x2812 # macro -regCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro -regCP_MES_INSTR_PNTR = 0x2813 # macro -regCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro -regCP_MES_MSCRATCH_HI = 0x2814 # macro -regCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro -regCP_MES_MSCRATCH_LO = 0x2815 # macro -regCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro -regCP_MES_MSTATUS_LO = 0x2816 # macro -regCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro -regCP_MES_MSTATUS_HI = 0x2817 # macro -regCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro -regCP_MES_MEPC_LO = 0x2818 # macro -regCP_MES_MEPC_LO_BASE_IDX = 1 # macro -regCP_MES_MEPC_HI = 0x2819 # macro -regCP_MES_MEPC_HI_BASE_IDX = 1 # macro -regCP_MES_MCAUSE_LO = 0x281a # macro -regCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro -regCP_MES_MCAUSE_HI = 0x281b # macro -regCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro -regCP_MES_MBADADDR_LO = 0x281c # macro -regCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro -regCP_MES_MBADADDR_HI = 0x281d # macro -regCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro -regCP_MES_MIP_LO = 0x281e # macro -regCP_MES_MIP_LO_BASE_IDX = 1 # macro -regCP_MES_MIP_HI = 0x281f # macro -regCP_MES_MIP_HI_BASE_IDX = 1 # macro -regCP_MES_IC_OP_CNTL = 0x2820 # macro -regCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_MES_MCYCLE_LO = 0x2826 # macro -regCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro -regCP_MES_MCYCLE_HI = 0x2827 # macro -regCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro -regCP_MES_MTIME_LO = 0x2828 # macro -regCP_MES_MTIME_LO_BASE_IDX = 1 # macro -regCP_MES_MTIME_HI = 0x2829 # macro -regCP_MES_MTIME_HI_BASE_IDX = 1 # macro -regCP_MES_MINSTRET_LO = 0x282a # macro -regCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro -regCP_MES_MINSTRET_HI = 0x282b # macro -regCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro -regCP_MES_MISA_LO = 0x282c # macro -regCP_MES_MISA_LO_BASE_IDX = 1 # macro -regCP_MES_MISA_HI = 0x282d # macro -regCP_MES_MISA_HI_BASE_IDX = 1 # macro -regCP_MES_MVENDORID_LO = 0x282e # macro -regCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro -regCP_MES_MVENDORID_HI = 0x282f # macro -regCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro -regCP_MES_MARCHID_LO = 0x2830 # macro -regCP_MES_MARCHID_LO_BASE_IDX = 1 # macro -regCP_MES_MARCHID_HI = 0x2831 # macro -regCP_MES_MARCHID_HI_BASE_IDX = 1 # macro -regCP_MES_MIMPID_LO = 0x2832 # macro -regCP_MES_MIMPID_LO_BASE_IDX = 1 # macro -regCP_MES_MIMPID_HI = 0x2833 # macro -regCP_MES_MIMPID_HI_BASE_IDX = 1 # macro -regCP_MES_MHARTID_LO = 0x2834 # macro -regCP_MES_MHARTID_LO_BASE_IDX = 1 # macro -regCP_MES_MHARTID_HI = 0x2835 # macro -regCP_MES_MHARTID_HI_BASE_IDX = 1 # macro -regCP_MES_DC_BASE_CNTL = 0x2836 # macro -regCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_OP_CNTL = 0x2837 # macro -regCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro -regCP_MES_MTIMECMP_LO = 0x2838 # macro -regCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro -regCP_MES_MTIMECMP_HI = 0x2839 # macro -regCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro -regCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro -regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro -regCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro -regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL1 = 0x283c # macro -regCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL2 = 0x283d # macro -regCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL3 = 0x283e # macro -regCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL4 = 0x283f # macro -regCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro -regCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro -regCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro -regCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro -regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR = 0x2842 # macro -regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX = 1 # macro -regCP_MES_GP0_LO = 0x2843 # macro -regCP_MES_GP0_LO_BASE_IDX = 1 # macro -regCP_MES_GP0_HI = 0x2844 # macro -regCP_MES_GP0_HI_BASE_IDX = 1 # macro -regCP_MES_GP1_LO = 0x2845 # macro -regCP_MES_GP1_LO_BASE_IDX = 1 # macro -regCP_MES_GP1_HI = 0x2846 # macro -regCP_MES_GP1_HI_BASE_IDX = 1 # macro -regCP_MES_GP2_LO = 0x2847 # macro -regCP_MES_GP2_LO_BASE_IDX = 1 # macro -regCP_MES_GP2_HI = 0x2848 # macro -regCP_MES_GP2_HI_BASE_IDX = 1 # macro -regCP_MES_GP3_LO = 0x2849 # macro -regCP_MES_GP3_LO_BASE_IDX = 1 # macro -regCP_MES_GP3_HI = 0x284a # macro -regCP_MES_GP3_HI_BASE_IDX = 1 # macro -regCP_MES_GP4_LO = 0x284b # macro -regCP_MES_GP4_LO_BASE_IDX = 1 # macro -regCP_MES_GP4_HI = 0x284c # macro -regCP_MES_GP4_HI_BASE_IDX = 1 # macro -regCP_MES_GP5_LO = 0x284d # macro -regCP_MES_GP5_LO_BASE_IDX = 1 # macro -regCP_MES_GP5_HI = 0x284e # macro -regCP_MES_GP5_HI_BASE_IDX = 1 # macro -regCP_MES_GP6_LO = 0x284f # macro -regCP_MES_GP6_LO_BASE_IDX = 1 # macro -regCP_MES_GP6_HI = 0x2850 # macro -regCP_MES_GP6_HI_BASE_IDX = 1 # macro -regCP_MES_GP7_LO = 0x2851 # macro -regCP_MES_GP7_LO_BASE_IDX = 1 # macro -regCP_MES_GP7_HI = 0x2852 # macro -regCP_MES_GP7_HI_BASE_IDX = 1 # macro -regCP_MES_GP8_LO = 0x2853 # macro -regCP_MES_GP8_LO_BASE_IDX = 1 # macro -regCP_MES_GP8_HI = 0x2854 # macro -regCP_MES_GP8_HI_BASE_IDX = 1 # macro -regCP_MES_GP9_LO = 0x2855 # macro -regCP_MES_GP9_LO_BASE_IDX = 1 # macro -regCP_MES_GP9_HI = 0x2856 # macro -regCP_MES_GP9_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_BASE0_LO = 0x2883 # macro -regCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_BASE0_HI = 0x2884 # macro -regCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_MASK0_LO = 0x2885 # macro -regCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_MASK0_HI = 0x2886 # macro -regCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_APERTURE = 0x2887 # macro -regCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_BASE_LO = 0x2888 # macro -regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_BASE_HI = 0x2889 # macro -regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_MASK_LO = 0x288a # macro -regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_MASK_HI = 0x288b # macro -regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro -regCP_MES_LOCAL_INSTR_APERTURE = 0x288c # macro -regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro -regCP_MES_LOCAL_SCRATCH_APERTURE = 0x288d # macro -regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro -regCP_MES_LOCAL_SCRATCH_BASE_LO = 0x288e # macro -regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_LOCAL_SCRATCH_BASE_HI = 0x288f # macro -regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_PERFCOUNT_CNTL = 0x2899 # macro -regCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro -regCP_MES_PENDING_INTERRUPT = 0x289a # macro -regCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro -regCP_MES_PRGRM_CNTR_START_HI = 0x289d # macro -regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_16 = 0x289f # macro -regCP_MES_INTERRUPT_DATA_16_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_17 = 0x28a0 # macro -regCP_MES_INTERRUPT_DATA_17_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_18 = 0x28a1 # macro -regCP_MES_INTERRUPT_DATA_18_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_19 = 0x28a2 # macro -regCP_MES_INTERRUPT_DATA_19_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_20 = 0x28a3 # macro -regCP_MES_INTERRUPT_DATA_20_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_21 = 0x28a4 # macro -regCP_MES_INTERRUPT_DATA_21_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_22 = 0x28a5 # macro -regCP_MES_INTERRUPT_DATA_22_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_23 = 0x28a6 # macro -regCP_MES_INTERRUPT_DATA_23_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_24 = 0x28a7 # macro -regCP_MES_INTERRUPT_DATA_24_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_25 = 0x28a8 # macro -regCP_MES_INTERRUPT_DATA_25_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_26 = 0x28a9 # macro -regCP_MES_INTERRUPT_DATA_26_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_27 = 0x28aa # macro -regCP_MES_INTERRUPT_DATA_27_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_28 = 0x28ab # macro -regCP_MES_INTERRUPT_DATA_28_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_29 = 0x28ac # macro -regCP_MES_INTERRUPT_DATA_29_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_30 = 0x28ad # macro -regCP_MES_INTERRUPT_DATA_30_BASE_IDX = 1 # macro -regCP_MES_INTERRUPT_DATA_31 = 0x28ae # macro -regCP_MES_INTERRUPT_DATA_31_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE0_BASE = 0x28af # macro -regCP_MES_DC_APERTURE0_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE0_MASK = 0x28b0 # macro -regCP_MES_DC_APERTURE0_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE0_CNTL = 0x28b1 # macro -regCP_MES_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE1_BASE = 0x28b2 # macro -regCP_MES_DC_APERTURE1_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE1_MASK = 0x28b3 # macro -regCP_MES_DC_APERTURE1_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE1_CNTL = 0x28b4 # macro -regCP_MES_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE2_BASE = 0x28b5 # macro -regCP_MES_DC_APERTURE2_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE2_MASK = 0x28b6 # macro -regCP_MES_DC_APERTURE2_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE2_CNTL = 0x28b7 # macro -regCP_MES_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE3_BASE = 0x28b8 # macro -regCP_MES_DC_APERTURE3_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE3_MASK = 0x28b9 # macro -regCP_MES_DC_APERTURE3_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE3_CNTL = 0x28ba # macro -regCP_MES_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE4_BASE = 0x28bb # macro -regCP_MES_DC_APERTURE4_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE4_MASK = 0x28bc # macro -regCP_MES_DC_APERTURE4_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE4_CNTL = 0x28bd # macro -regCP_MES_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE5_BASE = 0x28be # macro -regCP_MES_DC_APERTURE5_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE5_MASK = 0x28bf # macro -regCP_MES_DC_APERTURE5_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE5_CNTL = 0x28c0 # macro -regCP_MES_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE6_BASE = 0x28c1 # macro -regCP_MES_DC_APERTURE6_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE6_MASK = 0x28c2 # macro -regCP_MES_DC_APERTURE6_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE6_CNTL = 0x28c3 # macro -regCP_MES_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE7_BASE = 0x28c4 # macro -regCP_MES_DC_APERTURE7_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE7_MASK = 0x28c5 # macro -regCP_MES_DC_APERTURE7_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE7_CNTL = 0x28c6 # macro -regCP_MES_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE8_BASE = 0x28c7 # macro -regCP_MES_DC_APERTURE8_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE8_MASK = 0x28c8 # macro -regCP_MES_DC_APERTURE8_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE8_CNTL = 0x28c9 # macro -regCP_MES_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE9_BASE = 0x28ca # macro -regCP_MES_DC_APERTURE9_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE9_MASK = 0x28cb # macro -regCP_MES_DC_APERTURE9_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE9_CNTL = 0x28cc # macro -regCP_MES_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE10_BASE = 0x28cd # macro -regCP_MES_DC_APERTURE10_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE10_MASK = 0x28ce # macro -regCP_MES_DC_APERTURE10_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE10_CNTL = 0x28cf # macro -regCP_MES_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE11_BASE = 0x28d0 # macro -regCP_MES_DC_APERTURE11_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE11_MASK = 0x28d1 # macro -regCP_MES_DC_APERTURE11_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE11_CNTL = 0x28d2 # macro -regCP_MES_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE12_BASE = 0x28d3 # macro -regCP_MES_DC_APERTURE12_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE12_MASK = 0x28d4 # macro -regCP_MES_DC_APERTURE12_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE12_CNTL = 0x28d5 # macro -regCP_MES_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE13_BASE = 0x28d6 # macro -regCP_MES_DC_APERTURE13_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE13_MASK = 0x28d7 # macro -regCP_MES_DC_APERTURE13_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE13_CNTL = 0x28d8 # macro -regCP_MES_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE14_BASE = 0x28d9 # macro -regCP_MES_DC_APERTURE14_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE14_MASK = 0x28da # macro -regCP_MES_DC_APERTURE14_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE14_CNTL = 0x28db # macro -regCP_MES_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE15_BASE = 0x28dc # macro -regCP_MES_DC_APERTURE15_BASE_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE15_MASK = 0x28dd # macro -regCP_MES_DC_APERTURE15_MASK_BASE_IDX = 1 # macro -regCP_MES_DC_APERTURE15_CNTL = 0x28de # macro -regCP_MES_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro -regCP_MEC_RS64_PRGRM_CNTR_START = 0x2900 # macro -regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX = 1 # macro -regCP_MEC_MTVEC_LO = 0x2901 # macro -regCP_MEC_MTVEC_LO_BASE_IDX = 1 # macro -regCP_MEC_MTVEC_HI = 0x2902 # macro -regCP_MEC_MTVEC_HI_BASE_IDX = 1 # macro -regCP_MEC_ISA_CNTL = 0x2903 # macro -regCP_MEC_ISA_CNTL_BASE_IDX = 1 # macro -regCP_MEC_RS64_CNTL = 0x2904 # macro -regCP_MEC_RS64_CNTL_BASE_IDX = 1 # macro -regCP_MEC_MIE_LO = 0x2905 # macro -regCP_MEC_MIE_LO_BASE_IDX = 1 # macro -regCP_MEC_MIE_HI = 0x2906 # macro -regCP_MEC_MIE_HI_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT = 0x2907 # macro -regCP_MEC_RS64_INTERRUPT_BASE_IDX = 1 # macro -regCP_MEC_RS64_INSTR_PNTR = 0x2908 # macro -regCP_MEC_RS64_INSTR_PNTR_BASE_IDX = 1 # macro -regCP_MEC_MIP_LO = 0x2909 # macro -regCP_MEC_MIP_LO_BASE_IDX = 1 # macro -regCP_MEC_MIP_HI = 0x290a # macro -regCP_MEC_MIP_HI_BASE_IDX = 1 # macro -regCP_MEC_DC_BASE_CNTL = 0x290b # macro -regCP_MEC_DC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_OP_CNTL = 0x290c # macro -regCP_MEC_DC_OP_CNTL_BASE_IDX = 1 # macro -regCP_MEC_MTIMECMP_LO = 0x290d # macro -regCP_MEC_MTIMECMP_LO_BASE_IDX = 1 # macro -regCP_MEC_MTIMECMP_HI = 0x290e # macro -regCP_MEC_MTIMECMP_HI_BASE_IDX = 1 # macro -regCP_MEC_GP0_LO = 0x2910 # macro -regCP_MEC_GP0_LO_BASE_IDX = 1 # macro -regCP_MEC_GP0_HI = 0x2911 # macro -regCP_MEC_GP0_HI_BASE_IDX = 1 # macro -regCP_MEC_GP1_LO = 0x2912 # macro -regCP_MEC_GP1_LO_BASE_IDX = 1 # macro -regCP_MEC_GP1_HI = 0x2913 # macro -regCP_MEC_GP1_HI_BASE_IDX = 1 # macro -regCP_MEC_GP2_LO = 0x2914 # macro -regCP_MEC_GP2_LO_BASE_IDX = 1 # macro -regCP_MEC_GP2_HI = 0x2915 # macro -regCP_MEC_GP2_HI_BASE_IDX = 1 # macro -regCP_MEC_GP3_LO = 0x2916 # macro -regCP_MEC_GP3_LO_BASE_IDX = 1 # macro -regCP_MEC_GP3_HI = 0x2917 # macro -regCP_MEC_GP3_HI_BASE_IDX = 1 # macro -regCP_MEC_GP4_LO = 0x2918 # macro -regCP_MEC_GP4_LO_BASE_IDX = 1 # macro -regCP_MEC_GP4_HI = 0x2919 # macro -regCP_MEC_GP4_HI_BASE_IDX = 1 # macro -regCP_MEC_GP5_LO = 0x291a # macro -regCP_MEC_GP5_LO_BASE_IDX = 1 # macro -regCP_MEC_GP5_HI = 0x291b # macro -regCP_MEC_GP5_HI_BASE_IDX = 1 # macro -regCP_MEC_GP6_LO = 0x291c # macro -regCP_MEC_GP6_LO_BASE_IDX = 1 # macro -regCP_MEC_GP6_HI = 0x291d # macro -regCP_MEC_GP6_HI_BASE_IDX = 1 # macro -regCP_MEC_GP7_LO = 0x291e # macro -regCP_MEC_GP7_LO_BASE_IDX = 1 # macro -regCP_MEC_GP7_HI = 0x291f # macro -regCP_MEC_GP7_HI_BASE_IDX = 1 # macro -regCP_MEC_GP8_LO = 0x2920 # macro -regCP_MEC_GP8_LO_BASE_IDX = 1 # macro -regCP_MEC_GP8_HI = 0x2921 # macro -regCP_MEC_GP8_HI_BASE_IDX = 1 # macro -regCP_MEC_GP9_LO = 0x2922 # macro -regCP_MEC_GP9_LO_BASE_IDX = 1 # macro -regCP_MEC_GP9_HI = 0x2923 # macro -regCP_MEC_GP9_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_BASE0_LO = 0x2927 # macro -regCP_MEC_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_BASE0_HI = 0x2928 # macro -regCP_MEC_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_MASK0_LO = 0x2929 # macro -regCP_MEC_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_MASK0_HI = 0x292a # macro -regCP_MEC_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_APERTURE = 0x292b # macro -regCP_MEC_LOCAL_APERTURE_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_BASE_LO = 0x292c # macro -regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_BASE_HI = 0x292d # macro -regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_MASK_LO = 0x292e # macro -regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_MASK_HI = 0x292f # macro -regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_INSTR_APERTURE = 0x2930 # macro -regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_SCRATCH_APERTURE = 0x2931 # macro -regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_LO = 0x2932 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_HI = 0x2933 # macro -regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regCP_MEC_RS64_PERFCOUNT_CNTL = 0x2934 # macro -regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX = 1 # macro -regCP_MEC_RS64_PENDING_INTERRUPT = 0x2935 # macro -regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX = 1 # macro -regCP_MEC_RS64_PRGRM_CNTR_START_HI = 0x2938 # macro -regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_16 = 0x293a # macro -regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_17 = 0x293b # macro -regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_18 = 0x293c # macro -regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_19 = 0x293d # macro -regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_20 = 0x293e # macro -regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_21 = 0x293f # macro -regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_22 = 0x2940 # macro -regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_23 = 0x2941 # macro -regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_24 = 0x2942 # macro -regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_25 = 0x2943 # macro -regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_26 = 0x2944 # macro -regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_27 = 0x2945 # macro -regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_28 = 0x2946 # macro -regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_29 = 0x2947 # macro -regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_30 = 0x2948 # macro -regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX = 1 # macro -regCP_MEC_RS64_INTERRUPT_DATA_31 = 0x2949 # macro -regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE0_BASE = 0x294a # macro -regCP_MEC_DC_APERTURE0_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE0_MASK = 0x294b # macro -regCP_MEC_DC_APERTURE0_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE0_CNTL = 0x294c # macro -regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE1_BASE = 0x294d # macro -regCP_MEC_DC_APERTURE1_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE1_MASK = 0x294e # macro -regCP_MEC_DC_APERTURE1_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE1_CNTL = 0x294f # macro -regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE2_BASE = 0x2950 # macro -regCP_MEC_DC_APERTURE2_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE2_MASK = 0x2951 # macro -regCP_MEC_DC_APERTURE2_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE2_CNTL = 0x2952 # macro -regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE3_BASE = 0x2953 # macro -regCP_MEC_DC_APERTURE3_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE3_MASK = 0x2954 # macro -regCP_MEC_DC_APERTURE3_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE3_CNTL = 0x2955 # macro -regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE4_BASE = 0x2956 # macro -regCP_MEC_DC_APERTURE4_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE4_MASK = 0x2957 # macro -regCP_MEC_DC_APERTURE4_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE4_CNTL = 0x2958 # macro -regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE5_BASE = 0x2959 # macro -regCP_MEC_DC_APERTURE5_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE5_MASK = 0x295a # macro -regCP_MEC_DC_APERTURE5_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE5_CNTL = 0x295b # macro -regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE6_BASE = 0x295c # macro -regCP_MEC_DC_APERTURE6_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE6_MASK = 0x295d # macro -regCP_MEC_DC_APERTURE6_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE6_CNTL = 0x295e # macro -regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE7_BASE = 0x295f # macro -regCP_MEC_DC_APERTURE7_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE7_MASK = 0x2960 # macro -regCP_MEC_DC_APERTURE7_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE7_CNTL = 0x2961 # macro -regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE8_BASE = 0x2962 # macro -regCP_MEC_DC_APERTURE8_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE8_MASK = 0x2963 # macro -regCP_MEC_DC_APERTURE8_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE8_CNTL = 0x2964 # macro -regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE9_BASE = 0x2965 # macro -regCP_MEC_DC_APERTURE9_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE9_MASK = 0x2966 # macro -regCP_MEC_DC_APERTURE9_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE9_CNTL = 0x2967 # macro -regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE10_BASE = 0x2968 # macro -regCP_MEC_DC_APERTURE10_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE10_MASK = 0x2969 # macro -regCP_MEC_DC_APERTURE10_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE10_CNTL = 0x296a # macro -regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE11_BASE = 0x296b # macro -regCP_MEC_DC_APERTURE11_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE11_MASK = 0x296c # macro -regCP_MEC_DC_APERTURE11_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE11_CNTL = 0x296d # macro -regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE12_BASE = 0x296e # macro -regCP_MEC_DC_APERTURE12_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE12_MASK = 0x296f # macro -regCP_MEC_DC_APERTURE12_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE12_CNTL = 0x2970 # macro -regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE13_BASE = 0x2971 # macro -regCP_MEC_DC_APERTURE13_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE13_MASK = 0x2972 # macro -regCP_MEC_DC_APERTURE13_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE13_CNTL = 0x2973 # macro -regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE14_BASE = 0x2974 # macro -regCP_MEC_DC_APERTURE14_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE14_MASK = 0x2975 # macro -regCP_MEC_DC_APERTURE14_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE14_CNTL = 0x2976 # macro -regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE15_BASE = 0x2977 # macro -regCP_MEC_DC_APERTURE15_BASE_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE15_MASK = 0x2978 # macro -regCP_MEC_DC_APERTURE15_MASK_BASE_IDX = 1 # macro -regCP_MEC_DC_APERTURE15_CNTL = 0x2979 # macro -regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX = 1 # macro -regCP_CPC_IC_OP_CNTL = 0x297a # macro -regCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_GFX_CNTL = 0x2a00 # macro -regCP_GFX_CNTL_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTERRUPT0 = 0x2a01 # macro -regCP_GFX_RS64_INTERRUPT0_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTR_EN0 = 0x2a02 # macro -regCP_GFX_RS64_INTR_EN0_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTR_EN1 = 0x2a03 # macro -regCP_GFX_RS64_INTR_EN1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE_CNTL = 0x2a08 # macro -regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_OP_CNTL = 0x2a09 # macro -regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_BASE0_LO = 0x2a0a # macro -regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_BASE0_HI = 0x2a0b # macro -regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_MASK0_LO = 0x2a0c # macro -regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_MASK0_HI = 0x2a0d # macro -regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_APERTURE = 0x2a0e # macro -regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_LO = 0x2a0f # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_HI = 0x2a10 # macro -regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_LO = 0x2a11 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_HI = 0x2a12 # macro -regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_INSTR_APERTURE = 0x2a13 # macro -regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE = 0x2a14 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO = 0x2a15 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI = 0x2a16 # macro -regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_PERFCOUNT_CNTL0 = 0x2a1a # macro -regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_PERFCOUNT_CNTL1 = 0x2a1b # macro -regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_LO0 = 0x2a1c # macro -regCP_GFX_RS64_MIP_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_LO1 = 0x2a1d # macro -regCP_GFX_RS64_MIP_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_HI0 = 0x2a1e # macro -regCP_GFX_RS64_MIP_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIP_HI1 = 0x2a1f # macro -regCP_GFX_RS64_MIP_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_LO0 = 0x2a20 # macro -regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_LO1 = 0x2a21 # macro -regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_HI0 = 0x2a22 # macro -regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_MTIMECMP_HI1 = 0x2a23 # macro -regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_LO0 = 0x2a24 # macro -regCP_GFX_RS64_GP0_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_LO1 = 0x2a25 # macro -regCP_GFX_RS64_GP0_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_HI0 = 0x2a26 # macro -regCP_GFX_RS64_GP0_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP0_HI1 = 0x2a27 # macro -regCP_GFX_RS64_GP0_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_LO0 = 0x2a28 # macro -regCP_GFX_RS64_GP1_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_LO1 = 0x2a29 # macro -regCP_GFX_RS64_GP1_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_HI0 = 0x2a2a # macro -regCP_GFX_RS64_GP1_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP1_HI1 = 0x2a2b # macro -regCP_GFX_RS64_GP1_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_LO0 = 0x2a2c # macro -regCP_GFX_RS64_GP2_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_LO1 = 0x2a2d # macro -regCP_GFX_RS64_GP2_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_HI0 = 0x2a2e # macro -regCP_GFX_RS64_GP2_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP2_HI1 = 0x2a2f # macro -regCP_GFX_RS64_GP2_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_LO0 = 0x2a30 # macro -regCP_GFX_RS64_GP3_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_LO1 = 0x2a31 # macro -regCP_GFX_RS64_GP3_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_HI0 = 0x2a32 # macro -regCP_GFX_RS64_GP3_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP3_HI1 = 0x2a33 # macro -regCP_GFX_RS64_GP3_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_LO0 = 0x2a34 # macro -regCP_GFX_RS64_GP4_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_LO1 = 0x2a35 # macro -regCP_GFX_RS64_GP4_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_HI0 = 0x2a36 # macro -regCP_GFX_RS64_GP4_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP4_HI1 = 0x2a37 # macro -regCP_GFX_RS64_GP4_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_LO0 = 0x2a38 # macro -regCP_GFX_RS64_GP5_LO0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_LO1 = 0x2a39 # macro -regCP_GFX_RS64_GP5_LO1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_HI0 = 0x2a3a # macro -regCP_GFX_RS64_GP5_HI0_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP5_HI1 = 0x2a3b # macro -regCP_GFX_RS64_GP5_HI1_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP6_LO = 0x2a3c # macro -regCP_GFX_RS64_GP6_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP6_HI = 0x2a3d # macro -regCP_GFX_RS64_GP6_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP7_LO = 0x2a3e # macro -regCP_GFX_RS64_GP7_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP7_HI = 0x2a3f # macro -regCP_GFX_RS64_GP7_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP8_LO = 0x2a40 # macro -regCP_GFX_RS64_GP8_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP8_HI = 0x2a41 # macro -regCP_GFX_RS64_GP8_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP9_LO = 0x2a42 # macro -regCP_GFX_RS64_GP9_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_GP9_HI = 0x2a43 # macro -regCP_GFX_RS64_GP9_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_INSTR_PNTR0 = 0x2a44 # macro -regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX = 1 # macro -regCP_GFX_RS64_INSTR_PNTR1 = 0x2a45 # macro -regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX = 1 # macro -regCP_GFX_RS64_PENDING_INTERRUPT0 = 0x2a46 # macro -regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX = 1 # macro -regCP_GFX_RS64_PENDING_INTERRUPT1 = 0x2a47 # macro -regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE0 = 0x2a49 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_MASK0 = 0x2a4a # macro -regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL0 = 0x2a4b # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_BASE0 = 0x2a4c # macro -regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_MASK0 = 0x2a4d # macro -regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL0 = 0x2a4e # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_BASE0 = 0x2a4f # macro -regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK0 = 0x2a50 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL0 = 0x2a51 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE0 = 0x2a52 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK0 = 0x2a53 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL0 = 0x2a54 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE0 = 0x2a55 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK0 = 0x2a56 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL0 = 0x2a57 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE0 = 0x2a58 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK0 = 0x2a59 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL0 = 0x2a5a # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_BASE0 = 0x2a5b # macro -regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_MASK0 = 0x2a5c # macro -regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL0 = 0x2a5d # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_BASE0 = 0x2a5e # macro -regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_MASK0 = 0x2a5f # macro -regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL0 = 0x2a60 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE0 = 0x2a61 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK0 = 0x2a62 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL0 = 0x2a63 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE0 = 0x2a64 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK0 = 0x2a65 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL0 = 0x2a66 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE0 = 0x2a67 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK0 = 0x2a68 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL0 = 0x2a69 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_BASE0 = 0x2a6a # macro -regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_MASK0 = 0x2a6b # macro -regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL0 = 0x2a6c # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_BASE0 = 0x2a6d # macro -regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_MASK0 = 0x2a6e # macro -regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL0 = 0x2a6f # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE0 = 0x2a70 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK0 = 0x2a71 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL0 = 0x2a72 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE0 = 0x2a73 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK0 = 0x2a74 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL0 = 0x2a75 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE0 = 0x2a76 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK0 = 0x2a77 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL0 = 0x2a78 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE1 = 0x2a79 # macro -regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_MASK1 = 0x2a7a # macro -regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL1 = 0x2a7b # macro -regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_BASE1 = 0x2a7c # macro -regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_MASK1 = 0x2a7d # macro -regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL1 = 0x2a7e # macro -regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_BASE1 = 0x2a7f # macro -regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK1 = 0x2a80 # macro -regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL1 = 0x2a81 # macro -regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE1 = 0x2a82 # macro -regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK1 = 0x2a83 # macro -regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL1 = 0x2a84 # macro -regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE1 = 0x2a85 # macro -regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK1 = 0x2a86 # macro -regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL1 = 0x2a87 # macro -regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE1 = 0x2a88 # macro -regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK1 = 0x2a89 # macro -regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL1 = 0x2a8a # macro -regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_BASE1 = 0x2a8b # macro -regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_MASK1 = 0x2a8c # macro -regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL1 = 0x2a8d # macro -regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_BASE1 = 0x2a8e # macro -regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_MASK1 = 0x2a8f # macro -regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL1 = 0x2a90 # macro -regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE1 = 0x2a91 # macro -regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK1 = 0x2a92 # macro -regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL1 = 0x2a93 # macro -regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE1 = 0x2a94 # macro -regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK1 = 0x2a95 # macro -regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL1 = 0x2a96 # macro -regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE1 = 0x2a97 # macro -regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK1 = 0x2a98 # macro -regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL1 = 0x2a99 # macro -regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_BASE1 = 0x2a9a # macro -regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_MASK1 = 0x2a9b # macro -regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL1 = 0x2a9c # macro -regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_BASE1 = 0x2a9d # macro -regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_MASK1 = 0x2a9e # macro -regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL1 = 0x2a9f # macro -regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE1 = 0x2aa0 # macro -regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK1 = 0x2aa1 # macro -regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL1 = 0x2aa2 # macro -regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE1 = 0x2aa3 # macro -regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK1 = 0x2aa4 # macro -regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL1 = 0x2aa5 # macro -regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE1 = 0x2aa6 # macro -regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK1 = 0x2aa7 # macro -regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL1 = 0x2aa8 # macro -regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX = 1 # macro -regCP_GFX_RS64_INTERRUPT1 = 0x2aac # macro -regCP_GFX_RS64_INTERRUPT1_BASE_IDX = 1 # macro -regGL1_DRAM_BURST_MASK = 0x2d02 # macro -regGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro -regGL1_ARB_STATUS = 0x2d03 # macro -regGL1_ARB_STATUS_BASE_IDX = 1 # macro -regGL1I_GL1R_REP_FGCG_OVERRIDE = 0x2d05 # macro -regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro -regGL1C_STATUS = 0x2d41 # macro -regGL1C_STATUS_BASE_IDX = 1 # macro -regGL1C_UTCL0_CNTL1 = 0x2d42 # macro -regGL1C_UTCL0_CNTL1_BASE_IDX = 1 # macro -regGL1C_UTCL0_CNTL2 = 0x2d43 # macro -regGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro -regGL1C_UTCL0_STATUS = 0x2d44 # macro -regGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro -regGL1C_UTCL0_RETRY = 0x2d45 # macro -regGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro -regCH_ARB_CTRL = 0x2d80 # macro -regCH_ARB_CTRL_BASE_IDX = 1 # macro -regCH_DRAM_BURST_MASK = 0x2d82 # macro -regCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro -regCH_ARB_STATUS = 0x2d83 # macro -regCH_ARB_STATUS_BASE_IDX = 1 # macro -regCH_DRAM_BURST_CTRL = 0x2d84 # macro -regCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro -regCHA_CHC_CREDITS = 0x2d88 # macro -regCHA_CHC_CREDITS_BASE_IDX = 1 # macro -regCHA_CLIENT_FREE_DELAY = 0x2d89 # macro -regCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro -regCHI_CHR_REP_FGCG_OVERRIDE = 0x2d8c # macro -regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX = 1 # macro -regCH_VC5_ENABLE = 0x2d94 # macro -regCH_VC5_ENABLE_BASE_IDX = 1 # macro -regCHC_CTRL = 0x2dc0 # macro -regCHC_CTRL_BASE_IDX = 1 # macro -regCHC_STATUS = 0x2dc1 # macro -regCHC_STATUS_BASE_IDX = 1 # macro -regCHCG_CTRL = 0x2dc2 # macro -regCHCG_CTRL_BASE_IDX = 1 # macro -regCHCG_STATUS = 0x2dc3 # macro -regCHCG_STATUS_BASE_IDX = 1 # macro -regGL2C_CTRL = 0x2e00 # macro -regGL2C_CTRL_BASE_IDX = 1 # macro -regGL2C_CTRL2 = 0x2e01 # macro -regGL2C_CTRL2_BASE_IDX = 1 # macro -regGL2C_ADDR_MATCH_MASK = 0x2e03 # macro -regGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro -regGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro -regGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro -regGL2C_WBINVL2 = 0x2e05 # macro -regGL2C_WBINVL2_BASE_IDX = 1 # macro -regGL2C_SOFT_RESET = 0x2e06 # macro -regGL2C_SOFT_RESET_BASE_IDX = 1 # macro -regGL2C_CM_CTRL0 = 0x2e07 # macro -regGL2C_CM_CTRL0_BASE_IDX = 1 # macro -regGL2C_CM_CTRL1 = 0x2e08 # macro -regGL2C_CM_CTRL1_BASE_IDX = 1 # macro -regGL2C_CM_STALL = 0x2e09 # macro -regGL2C_CM_STALL_BASE_IDX = 1 # macro -regGL2C_CTRL3 = 0x2e0c # macro -regGL2C_CTRL3_BASE_IDX = 1 # macro -regGL2C_LB_CTR_CTRL = 0x2e0d # macro -regGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro -regGL2C_LB_DATA0 = 0x2e0e # macro -regGL2C_LB_DATA0_BASE_IDX = 1 # macro -regGL2C_LB_DATA1 = 0x2e0f # macro -regGL2C_LB_DATA1_BASE_IDX = 1 # macro -regGL2C_LB_DATA2 = 0x2e10 # macro -regGL2C_LB_DATA2_BASE_IDX = 1 # macro -regGL2C_LB_DATA3 = 0x2e11 # macro -regGL2C_LB_DATA3_BASE_IDX = 1 # macro -regGL2C_LB_CTR_SEL0 = 0x2e12 # macro -regGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro -regGL2C_LB_CTR_SEL1 = 0x2e13 # macro -regGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro -regGL2C_CTRL4 = 0x2e17 # macro -regGL2C_CTRL4_BASE_IDX = 1 # macro -regGL2C_DISCARD_STALL_CTRL = 0x2e18 # macro -regGL2C_DISCARD_STALL_CTRL_BASE_IDX = 1 # macro -regGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro -regGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro -regGL2A_ADDR_MATCH_MASK = 0x2e21 # macro -regGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro -regGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro -regGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro -regGL2A_PRIORITY_CTRL = 0x2e23 # macro -regGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro -regGL2A_RESP_THROTTLE_CTRL = 0x2e2a # macro -regGL2A_RESP_THROTTLE_CTRL_BASE_IDX = 1 # macro -regGL1H_ARB_CTRL = 0x2e40 # macro -regGL1H_ARB_CTRL_BASE_IDX = 1 # macro -regGL1H_GL1_CREDITS = 0x2e41 # macro -regGL1H_GL1_CREDITS_BASE_IDX = 1 # macro -regGL1H_BURST_MASK = 0x2e42 # macro -regGL1H_BURST_MASK_BASE_IDX = 1 # macro -regGL1H_BURST_CTRL = 0x2e43 # macro -regGL1H_BURST_CTRL_BASE_IDX = 1 # macro -regGL1H_ARB_STATUS = 0x2e44 # macro -regGL1H_ARB_STATUS_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER1_LO = 0x3000 # macro -regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER1_HI = 0x3001 # macro -regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_LO = 0x3002 # macro -regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_HI = 0x3003 # macro -regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER1_LO = 0x3004 # macro -regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER1_HI = 0x3005 # macro -regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_LO = 0x3006 # macro -regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_HI = 0x3007 # macro -regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER1_LO = 0x3008 # macro -regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER1_HI = 0x3009 # macro -regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_LO = 0x300a # macro -regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_HI = 0x300b # macro -regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCPF_LATENCY_STATS_DATA = 0x300c # macro -regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -regCPG_LATENCY_STATS_DATA = 0x300d # macro -regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -regCPC_LATENCY_STATS_DATA = 0x300e # macro -regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_LO = 0x3040 # macro -regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_HI = 0x3041 # macro -regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_LO = 0x3043 # macro -regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_HI = 0x3044 # macro -regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro -regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro -regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro -regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro -regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro -regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro -regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro -regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro -regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE4_PERFCOUNTER_LO = 0x304d # macro -regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE4_PERFCOUNTER_HI = 0x304e # macro -regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE5_PERFCOUNTER_LO = 0x304f # macro -regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE5_PERFCOUNTER_HI = 0x3050 # macro -regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGRBM_SE6_PERFCOUNTER_LO = 0x3051 # macro -regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGRBM_SE6_PERFCOUNTER_HI = 0x3052 # macro -regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_LO = 0x30a4 # macro -regGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_HI = 0x30a5 # macro -regGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_LO = 0x30a6 # macro -regGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_HI = 0x30a7 # macro -regGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_LO = 0x30a8 # macro -regGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_HI = 0x30a9 # macro -regGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_LO = 0x30aa # macro -regGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_HI = 0x30ab # macro -regGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro -regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro -regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro -regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro -regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro -regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro -regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro -regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro -regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro -regGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro -regGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro -regGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro -regGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro -regGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro -regGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro -regGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro -regGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_LO = 0x3100 # macro -regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_HI = 0x3101 # macro -regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_LO = 0x3102 # macro -regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_HI = 0x3103 # macro -regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_LO = 0x3104 # macro -regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_HI = 0x3105 # macro -regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_LO = 0x3106 # macro -regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_HI = 0x3107 # macro -regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_LO = 0x3140 # macro -regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_HI = 0x3141 # macro -regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER1_LO = 0x3142 # macro -regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER1_HI = 0x3143 # macro -regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER2_LO = 0x3144 # macro -regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER2_HI = 0x3145 # macro -regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER3_LO = 0x3146 # macro -regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER3_HI = 0x3147 # macro -regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER4_LO = 0x3148 # macro -regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER4_HI = 0x3149 # macro -regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER5_LO = 0x314a # macro -regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER5_HI = 0x314b # macro -regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER6_LO = 0x314c # macro -regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER6_HI = 0x314d # macro -regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER7_LO = 0x314e # macro -regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER7_HI = 0x314f # macro -regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_HI = 0x3180 # macro -regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_LO = 0x3181 # macro -regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_HI = 0x3182 # macro -regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_LO = 0x3183 # macro -regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_HI = 0x3184 # macro -regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_LO = 0x3185 # macro -regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_HI = 0x3186 # macro -regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_LO = 0x3187 # macro -regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER4_HI = 0x3188 # macro -regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER4_LO = 0x3189 # macro -regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER5_HI = 0x318a # macro -regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER5_LO = 0x318b # macro -regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_HI = 0x318c # macro -regPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_LO = 0x318d # macro -regPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_HI = 0x318e # macro -regPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_LO = 0x318f # macro -regPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_HI = 0x3190 # macro -regPC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_LO = 0x3191 # macro -regPC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_HI = 0x3192 # macro -regPC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_LO = 0x3193 # macro -regPC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER0_LO = 0x31c0 # macro -regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER1_LO = 0x31c2 # macro -regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER2_LO = 0x31c4 # macro -regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER3_LO = 0x31c6 # macro -regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER4_LO = 0x31c8 # macro -regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER5_LO = 0x31ca # macro -regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER6_LO = 0x31cc # macro -regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER7_LO = 0x31ce # macro -regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER0_LO = 0x31e4 # macro -regSQG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER0_HI = 0x31e5 # macro -regSQG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER1_LO = 0x31e6 # macro -regSQG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER1_HI = 0x31e7 # macro -regSQG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER2_LO = 0x31e8 # macro -regSQG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER2_HI = 0x31e9 # macro -regSQG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER3_LO = 0x31ea # macro -regSQG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER3_HI = 0x31eb # macro -regSQG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER4_LO = 0x31ec # macro -regSQG_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER4_HI = 0x31ed # macro -regSQG_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER5_LO = 0x31ee # macro -regSQG_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER5_HI = 0x31ef # macro -regSQG_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER6_LO = 0x31f0 # macro -regSQG_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER6_HI = 0x31f1 # macro -regSQG_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER7_LO = 0x31f2 # macro -regSQG_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER7_HI = 0x31f3 # macro -regSQG_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_LO = 0x3240 # macro -regSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_HI = 0x3241 # macro -regSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_LO = 0x3242 # macro -regSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_HI = 0x3243 # macro -regSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER2_LO = 0x3244 # macro -regSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER2_HI = 0x3245 # macro -regSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regSX_PERFCOUNTER3_LO = 0x3246 # macro -regSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regSX_PERFCOUNTER3_HI = 0x3247 # macro -regSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_LO = 0x3260 # macro -regGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_HI = 0x3261 # macro -regGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER_LO = 0x3262 # macro -regGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER_HI = 0x3263 # macro -regGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_LO = 0x3280 # macro -regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_HI = 0x3281 # macro -regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_LO = 0x3282 # macro -regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_HI = 0x3283 # macro -regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_LO = 0x3284 # macro -regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_HI = 0x3285 # macro -regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_LO = 0x3286 # macro -regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_HI = 0x3287 # macro -regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_LO = 0x32c0 # macro -regTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_HI = 0x32c1 # macro -regTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regTA_PERFCOUNTER1_LO = 0x32c2 # macro -regTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regTA_PERFCOUNTER1_HI = 0x32c3 # macro -regTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_LO = 0x3300 # macro -regTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_HI = 0x3301 # macro -regTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regTD_PERFCOUNTER1_LO = 0x3302 # macro -regTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regTD_PERFCOUNTER1_HI = 0x3303 # macro -regTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_LO = 0x3340 # macro -regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_HI = 0x3341 # macro -regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_LO = 0x3342 # macro -regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_HI = 0x3343 # macro -regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER2_LO = 0x3344 # macro -regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER2_HI = 0x3345 # macro -regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER3_LO = 0x3346 # macro -regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER3_HI = 0x3347 # macro -regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER_FILTER = 0x3348 # macro -regTCP_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER_FILTER2 = 0x3349 # macro -regTCP_PERFCOUNTER_FILTER2_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER_FILTER_EN = 0x334a # macro -regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_LO = 0x3380 # macro -regGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_HI = 0x3381 # macro -regGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_LO = 0x3382 # macro -regGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_HI = 0x3383 # macro -regGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER2_LO = 0x3384 # macro -regGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER2_HI = 0x3385 # macro -regGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER3_LO = 0x3386 # macro -regGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER3_HI = 0x3387 # macro -regGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_LO = 0x3390 # macro -regGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_HI = 0x3391 # macro -regGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_LO = 0x3392 # macro -regGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_HI = 0x3393 # macro -regGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER2_LO = 0x3394 # macro -regGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER2_HI = 0x3395 # macro -regGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER3_LO = 0x3396 # macro -regGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER3_HI = 0x3397 # macro -regGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_LO = 0x33a0 # macro -regGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_HI = 0x33a1 # macro -regGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER1_LO = 0x33a2 # macro -regGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER1_HI = 0x33a3 # macro -regGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER2_LO = 0x33a4 # macro -regGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER2_HI = 0x33a5 # macro -regGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER3_LO = 0x33a6 # macro -regGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER3_HI = 0x33a7 # macro -regGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_LO = 0x33c0 # macro -regCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_HI = 0x33c1 # macro -regCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER1_LO = 0x33c2 # macro -regCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER1_HI = 0x33c3 # macro -regCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER2_LO = 0x33c4 # macro -regCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER2_HI = 0x33c5 # macro -regCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER3_LO = 0x33c6 # macro -regCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER3_HI = 0x33c7 # macro -regCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_LO = 0x33c8 # macro -regCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_HI = 0x33c9 # macro -regCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER1_LO = 0x33ca # macro -regCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER1_HI = 0x33cb # macro -regCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER2_LO = 0x33cc # macro -regCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER2_HI = 0x33cd # macro -regCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER3_LO = 0x33ce # macro -regCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER3_HI = 0x33cf # macro -regCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_LO = 0x3406 # macro -regCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_HI = 0x3407 # macro -regCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER1_LO = 0x3408 # macro -regCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER1_HI = 0x3409 # macro -regCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER2_LO = 0x340a # macro -regCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER2_HI = 0x340b # macro -regCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCB_PERFCOUNTER3_LO = 0x340c # macro -regCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCB_PERFCOUNTER3_HI = 0x340d # macro -regCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_LO = 0x3440 # macro -regDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_HI = 0x3441 # macro -regDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_LO = 0x3442 # macro -regDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_HI = 0x3443 # macro -regDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER2_LO = 0x3444 # macro -regDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER2_HI = 0x3445 # macro -regDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regDB_PERFCOUNTER3_LO = 0x3446 # macro -regDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regDB_PERFCOUNTER3_HI = 0x3447 # macro -regDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER0_LO = 0x3480 # macro -regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER0_HI = 0x3481 # macro -regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER1_LO = 0x3482 # macro -regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER1_HI = 0x3483 # macro -regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_LO = 0x34c0 # macro -regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_HI = 0x34c1 # macro -regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER1_LO = 0x34c2 # macro -regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER1_HI = 0x34c3 # macro -regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_LO = 0x34c4 # macro -regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_HI = 0x34c5 # macro -regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER3_LO = 0x34c6 # macro -regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER3_HI = 0x34c7 # macro -regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_LO = 0x3520 # macro -regGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_HI = 0x3521 # macro -regGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER1_LO = 0x3522 # macro -regGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER1_HI = 0x3523 # macro -regGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_LO = 0x3580 # macro -regPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_HI = 0x3581 # macro -regPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_LO = 0x3582 # macro -regPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_HI = 0x3583 # macro -regPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_LO = 0x3584 # macro -regPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_HI = 0x3585 # macro -regPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_LO = 0x3586 # macro -regPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_HI = 0x3587 # macro -regPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER4_LO = 0x3588 # macro -regPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER4_HI = 0x3589 # macro -regPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER5_LO = 0x358a # macro -regPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER5_HI = 0x358b # macro -regPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER6_LO = 0x358c # macro -regPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER6_HI = 0x358d # macro -regPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER7_LO = 0x358e # macro -regPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER7_HI = 0x358f # macro -regPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER0_LO = 0x35a0 # macro -regUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER0_HI = 0x35a1 # macro -regUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER1_LO = 0x35a2 # macro -regUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER1_HI = 0x35a3 # macro -regUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER2_LO = 0x35a4 # macro -regUTCL1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER2_HI = 0x35a5 # macro -regUTCL1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER3_LO = 0x35a6 # macro -regUTCL1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER3_HI = 0x35a7 # macro -regUTCL1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_LO = 0x35c0 # macro -regGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_HI = 0x35c1 # macro -regGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER1_LO = 0x35c2 # macro -regGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER1_HI = 0x35c3 # macro -regGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER2_LO = 0x35c4 # macro -regGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER2_HI = 0x35c5 # macro -regGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER3_LO = 0x35c6 # macro -regGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER3_HI = 0x35c7 # macro -regGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_LO = 0x35d0 # macro -regGL1H_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_HI = 0x35d1 # macro -regGL1H_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER1_LO = 0x35d2 # macro -regGL1H_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER1_HI = 0x35d3 # macro -regGL1H_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER2_LO = 0x35d4 # macro -regGL1H_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER2_HI = 0x35d5 # macro -regGL1H_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER3_LO = 0x35d6 # macro -regGL1H_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER3_HI = 0x35d7 # macro -regGL1H_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_LO = 0x3600 # macro -regCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_HI = 0x3601 # macro -regCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER1_LO = 0x3602 # macro -regCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER1_HI = 0x3603 # macro -regCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER2_LO = 0x3604 # macro -regCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER2_HI = 0x3605 # macro -regCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER3_LO = 0x3606 # macro -regCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER3_HI = 0x3607 # macro -regCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_LO = 0x3640 # macro -regGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_HI = 0x3641 # macro -regGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER_LO = 0x3642 # macro -regGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER_HI = 0x3643 # macro -regGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER1_SELECT = 0x3800 # macro -regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro -regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCPG_PERFCOUNTER0_SELECT = 0x3802 # macro -regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER1_SELECT = 0x3803 # macro -regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro -regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER1_SELECT = 0x3805 # macro -regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro -regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCPF_PERFCOUNTER0_SELECT = 0x3807 # macro -regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCP_PERFMON_CNTL = 0x3808 # macro -regCP_PERFMON_CNTL_BASE_IDX = 1 # macro -regCPC_PERFCOUNTER0_SELECT = 0x3809 # macro -regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro -regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro -regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -regCPF_LATENCY_STATS_SELECT = 0x380c # macro -regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -regCPG_LATENCY_STATS_SELECT = 0x380d # macro -regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -regCPC_LATENCY_STATS_SELECT = 0x380e # macro -regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro -regCPC_TC_PERF_COUNTER_WINDOW_SELECT = 0x380f # macro -regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro -regCP_DRAW_OBJECT = 0x3810 # macro -regCP_DRAW_OBJECT_BASE_IDX = 1 # macro -regCP_DRAW_OBJECT_COUNTER = 0x3811 # macro -regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro -regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_HI = 0x3813 # macro -regCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_LO = 0x3814 # macro -regCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro -regCP_DRAW_WINDOW_CNTL = 0x3815 # macro -regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro -regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro -regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro -regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro -regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro -regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro -regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE4_PERFCOUNTER_SELECT = 0x3846 # macro -regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE5_PERFCOUNTER_SELECT = 0x3847 # macro -regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_SE6_PERFCOUNTER_SELECT = 0x3848 # macro -regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro -regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro -regGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro -regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro -regGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro -regGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro -regGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro -regGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro -regGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro -regGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_SELECT = 0x38aa # macro -regGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro -regGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro -regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro -regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro -regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro -regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro -regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro -regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro -regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro -regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro -regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro -regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro -regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro -regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro -regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro -regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro -regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro -regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro -regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro -regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro -regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro -regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro -regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro -regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro -regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro -regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro -regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro -regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro -regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro -regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro -regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro -regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro -regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro -regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro -regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_SELECT = 0x3980 # macro -regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_SELECT = 0x3981 # macro -regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_SELECT = 0x3982 # macro -regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_SELECT = 0x3983 # macro -regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro -regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro -regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro -regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro -regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER4_SELECT = 0x3988 # macro -regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER5_SELECT = 0x3989 # macro -regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regSPI_PERFCOUNTER_BINS = 0x398a # macro -regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_SELECT = 0x398c # macro -regPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_SELECT = 0x398d # macro -regPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_SELECT = 0x398e # macro -regPC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_SELECT = 0x398f # macro -regPC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPC_PERFCOUNTER0_SELECT1 = 0x3990 # macro -regPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPC_PERFCOUNTER1_SELECT1 = 0x3991 # macro -regPC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regPC_PERFCOUNTER2_SELECT1 = 0x3992 # macro -regPC_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regPC_PERFCOUNTER3_SELECT1 = 0x3993 # macro -regPC_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro -regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro -regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro -regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro -regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro -regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro -regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro -regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro -regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro -regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro -regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER10_SELECT = 0x39ca # macro -regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER11_SELECT = 0x39cb # macro -regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER12_SELECT = 0x39cc # macro -regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER13_SELECT = 0x39cd # macro -regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER14_SELECT = 0x39ce # macro -regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER15_SELECT = 0x39cf # macro -regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER0_SELECT = 0x39d0 # macro -regSQG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER1_SELECT = 0x39d1 # macro -regSQG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER2_SELECT = 0x39d2 # macro -regSQG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER3_SELECT = 0x39d3 # macro -regSQG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER4_SELECT = 0x39d4 # macro -regSQG_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER5_SELECT = 0x39d5 # macro -regSQG_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER6_SELECT = 0x39d6 # macro -regSQG_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER7_SELECT = 0x39d7 # macro -regSQG_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER_CTRL = 0x39d8 # macro -regSQG_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro -regSQG_PERFCOUNTER_CTRL2 = 0x39da # macro -regSQG_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro -regSQG_PERF_SAMPLE_FINISH = 0x39db # macro -regSQG_PERF_SAMPLE_FINISH_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER_CTRL = 0x39e0 # macro -regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro -regSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro -regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 # macro -regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 # macro -regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF1_BASE = 0x39ea # macro -regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_BUF1_SIZE = 0x39eb # macro -regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_CTRL = 0x39ec # macro -regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_MASK = 0x39ed # macro -regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_TOKEN_MASK = 0x39ee # macro -regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_WPTR = 0x39ef # macro -regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_STATUS = 0x39f4 # macro -regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_STATUS2 = 0x39f5 # macro -regSQ_THREAD_TRACE_STATUS2_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x39f6 # macro -regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x39f7 # macro -regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x39f8 # macro -regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x39f9 # macro -regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 1 # macro -regSQ_THREAD_TRACE_DROPPED_CNTR = 0x39fa # macro -regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro -regGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro -regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro -regGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro -regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro -regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro -regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_SELECT = 0x3a40 # macro -regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_SELECT = 0x3a41 # macro -regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER2_SELECT = 0x3a42 # macro -regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER3_SELECT = 0x3a43 # macro -regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro -regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro -regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro -regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro -regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro -regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro -regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro -regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro -regGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro -regGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro -regGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro -regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro -regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro -regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_SELECT = 0x3b00 # macro -regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro -regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regTD_PERFCOUNTER1_SELECT = 0x3b02 # macro -regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro -regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro -regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro -regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro -regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro -regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro -regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro -regGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro -regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro -regGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro -regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro -regGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro -regGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro -regGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro -regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro -regGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro -regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro -regGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro -regGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro -regGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro -regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro -regGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro -regGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro -regGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro -regCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro -regCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro -regCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro -regCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro -regCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro -regCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro -regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro -regCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro -regCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro -regCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER_FILTER = 0x3c00 # macro -regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_SELECT = 0x3c01 # macro -regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro -regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCB_PERFCOUNTER1_SELECT = 0x3c03 # macro -regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER2_SELECT = 0x3c04 # macro -regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCB_PERFCOUNTER3_SELECT = 0x3c05 # macro -regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_SELECT = 0x3c40 # macro -regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro -regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_SELECT = 0x3c42 # macro -regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro -regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regDB_PERFCOUNTER2_SELECT = 0x3c44 # macro -regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regDB_PERFCOUNTER3_SELECT = 0x3c46 # macro -regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_CNTL = 0x3c80 # macro -regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro -regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro -regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro -regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro -regRLC_SPM_RING_WRPTR = 0x3c84 # macro -regRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro -regRLC_SPM_RING_RDPTR = 0x3c85 # macro -regRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro -regRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro -regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro -regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c87 # macro -regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c88 # macro -regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c89 # macro -regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro -regRLC_SPM_SE_MUXSEL_ADDR = 0x3c8a # macro -regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_SE_MUXSEL_DATA = 0x3c8b # macro -regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c92 # macro -regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_DATA = 0x3c93 # macro -regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3c94 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3c95 # macro -regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c96 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c97 # macro -regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3c98 # macro -regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_STATUS = 0x3c99 # macro -regRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_CTRL = 0x3c9a # macro -regRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_MODE = 0x3c9b # macro -regRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro -regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro -regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro -regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro -regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3c9f # macro -regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro -regRLC_SPM_PAUSE = 0x3ca2 # macro -regRLC_SPM_PAUSE_BASE_IDX = 1 # macro -regRLC_SPM_STATUS = 0x3ca3 # macro -regRLC_SPM_STATUS_BASE_IDX = 1 # macro -regRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca4 # macro -regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro -regRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca5 # macro -regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro -regRLC_SPM_MODE = 0x3cad # macro -regRLC_SPM_MODE_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_REQ_DATA_LO = 0x3cae # macro -regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_REQ_DATA_HI = 0x3caf # macro -regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_REQ_OP = 0x3cb0 # macro -regRLC_SPM_RSPM_REQ_OP_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_RET_DATA = 0x3cb1 # macro -regRLC_SPM_RSPM_RET_DATA_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_RET_OP = 0x3cb2 # macro -regRLC_SPM_RSPM_RET_OP_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_LO = 0x3cb3 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_HI = 0x3cb4 # macro -regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_REQ_OP = 0x3cb5 # macro -regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_RET_DATA = 0x3cb6 # macro -regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX = 1 # macro -regRLC_SPM_SE_RSPM_RET_OP = 0x3cb7 # macro -regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_CMD = 0x3cb8 # macro -regRLC_SPM_RSPM_CMD_BASE_IDX = 1 # macro -regRLC_SPM_RSPM_CMD_ACK = 0x3cb9 # macro -regRLC_SPM_RSPM_CMD_ACK_BASE_IDX = 1 # macro -regRLC_SPM_SPARE = 0x3cbf # macro -regRLC_SPM_SPARE_BASE_IDX = 1 # macro -regRLC_PERFMON_CNTL = 0x3cc0 # macro -regRLC_PERFMON_CNTL_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro -regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro -regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro -regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro -regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro -regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro -regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro -regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro -regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro -regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro -regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro -regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro -regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro -regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regRMI_PERF_COUNTER_CNTL = 0x3d06 # macro -regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro -regGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro -regGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro -regGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro -regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro -regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro -regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro -regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro -regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro -regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro -regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro -regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro -regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro -regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro -regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro -regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER0_SELECT = 0x3da0 # macro -regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER1_SELECT = 0x3da1 # macro -regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER2_SELECT = 0x3da2 # macro -regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regUTCL1_PERFCOUNTER3_SELECT = 0x3da3 # macro -regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro -regGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro -regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro -regGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro -regGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro -regGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_SELECT = 0x3dd0 # macro -regGL1H_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER0_SELECT1 = 0x3dd1 # macro -regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER1_SELECT = 0x3dd2 # macro -regGL1H_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER2_SELECT = 0x3dd3 # macro -regGL1H_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGL1H_PERFCOUNTER3_SELECT = 0x3dd4 # macro -regGL1H_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro -regCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro -regCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro -regCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro -regCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro -regCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro -regGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro -regGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER2_MODE = 0x3e02 # macro -regGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER0_CFG = 0x3e03 # macro -regGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER1_CFG = 0x3e04 # macro -regGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro -regGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro -regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro -regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro -regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -regGRTAVFS_GENERAL_0 = 0x4b02 # macro -regGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro -regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro -regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro -regGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro -regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro -regGRTAVFS_TARG_FREQ = 0x4b06 # macro -regGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro -regGRTAVFS_TARG_VOLT = 0x4b07 # macro -regGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro -regGRTAVFS_SOFT_RESET = 0x4b0c # macro -regGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro -regGRTAVFS_PSM_CNTL = 0x4b0d # macro -regGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_CLK_CNTL = 0x4b0e # macro -regGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_REG_ADDR = 0x4b40 # macro -regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_WR_DATA = 0x4b41 # macro -regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -regGRTAVFS_SE_GENERAL_0 = 0x4b42 # macro -regGRTAVFS_SE_GENERAL_0_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_RD_DATA = 0x4b43 # macro -regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_REG_CTRL = 0x4b44 # macro -regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro -regGRTAVFS_SE_RTAVFS_REG_STATUS = 0x4b45 # macro -regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro -regGRTAVFS_SE_TARG_FREQ = 0x4b46 # macro -regGRTAVFS_SE_TARG_FREQ_BASE_IDX = 1 # macro -regGRTAVFS_SE_TARG_VOLT = 0x4b47 # macro -regGRTAVFS_SE_TARG_VOLT_BASE_IDX = 1 # macro -regGRTAVFS_SE_SOFT_RESET = 0x4b4c # macro -regGRTAVFS_SE_SOFT_RESET_BASE_IDX = 1 # macro -regGRTAVFS_SE_PSM_CNTL = 0x4b4d # macro -regGRTAVFS_SE_PSM_CNTL_BASE_IDX = 1 # macro -regGRTAVFS_SE_CLK_CNTL = 0x4b4e # macro -regGRTAVFS_SE_CLK_CNTL_BASE_IDX = 1 # macro -regRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro -regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro -regRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro -regRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro -regCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro -regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_PFP_UCODE_ADDR = 0x5814 # macro -regCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_HYP_PFP_UCODE_DATA = 0x5815 # macro -regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro -regCP_PFP_UCODE_DATA = 0x5815 # macro -regCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro -regCP_HYP_ME_UCODE_ADDR = 0x5816 # macro -regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_ME_RAM_RADDR = 0x5816 # macro -regCP_ME_RAM_RADDR_BASE_IDX = 1 # macro -regCP_ME_RAM_WADDR = 0x5816 # macro -regCP_ME_RAM_WADDR_BASE_IDX = 1 # macro -regCP_HYP_ME_UCODE_DATA = 0x5817 # macro -regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro -regCP_ME_RAM_DATA = 0x5817 # macro -regCP_ME_RAM_DATA_BASE_IDX = 1 # macro -regCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro -regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_MEC_ME1_UCODE_ADDR = 0x581a # macro -regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_HYP_MEC1_UCODE_DATA = 0x581b # macro -regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro -regCP_MEC_ME1_UCODE_DATA = 0x581b # macro -regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro -regCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro -regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_MEC_ME2_UCODE_ADDR = 0x581c # macro -regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro -regCP_HYP_MEC2_UCODE_DATA = 0x581d # macro -regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro -regCP_MEC_ME2_UCODE_DATA = 0x581d # macro -regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro -regCP_PFP_IC_BASE_LO = 0x5840 # macro -regCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_PFP_IC_BASE_HI = 0x5841 # macro -regCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_PFP_IC_BASE_CNTL = 0x5842 # macro -regCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_PFP_IC_OP_CNTL = 0x5843 # macro -regCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_ME_IC_BASE_LO = 0x5844 # macro -regCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_ME_IC_BASE_HI = 0x5845 # macro -regCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_ME_IC_BASE_CNTL = 0x5846 # macro -regCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_ME_IC_OP_CNTL = 0x5847 # macro -regCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro -regCP_CPC_IC_BASE_LO = 0x584c # macro -regCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_CPC_IC_BASE_HI = 0x584d # macro -regCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_CPC_IC_BASE_CNTL = 0x584e # macro -regCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MES_IC_BASE_LO = 0x5850 # macro -regCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_MIBASE_LO = 0x5850 # macro -regCP_MES_MIBASE_LO_BASE_IDX = 1 # macro -regCP_MES_IC_BASE_HI = 0x5851 # macro -regCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_MIBASE_HI = 0x5851 # macro -regCP_MES_MIBASE_HI_BASE_IDX = 1 # macro -regCP_MES_IC_BASE_CNTL = 0x5852 # macro -regCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro -regCP_MES_DC_BASE_LO = 0x5854 # macro -regCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro -regCP_MES_MDBASE_LO = 0x5854 # macro -regCP_MES_MDBASE_LO_BASE_IDX = 1 # macro -regCP_MES_DC_BASE_HI = 0x5855 # macro -regCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro -regCP_MES_MDBASE_HI = 0x5855 # macro -regCP_MES_MDBASE_HI_BASE_IDX = 1 # macro -regCP_MES_MIBOUND_LO = 0x585b # macro -regCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro -regCP_MES_MIBOUND_HI = 0x585c # macro -regCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro -regCP_MES_MDBOUND_LO = 0x585d # macro -regCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro -regCP_MES_MDBOUND_HI = 0x585e # macro -regCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE0_LO = 0x5863 # macro -regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE1_LO = 0x5864 # macro -regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE0_HI = 0x5865 # macro -regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_DC_BASE1_HI = 0x5866 # macro -regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIBOUND_LO = 0x586c # macro -regCP_GFX_RS64_MIBOUND_LO_BASE_IDX = 1 # macro -regCP_GFX_RS64_MIBOUND_HI = 0x586d # macro -regCP_GFX_RS64_MIBOUND_HI_BASE_IDX = 1 # macro -regCP_MEC_DC_BASE_LO = 0x5870 # macro -regCP_MEC_DC_BASE_LO_BASE_IDX = 1 # macro -regCP_MEC_MDBASE_LO = 0x5870 # macro -regCP_MEC_MDBASE_LO_BASE_IDX = 1 # macro -regCP_MEC_DC_BASE_HI = 0x5871 # macro -regCP_MEC_DC_BASE_HI_BASE_IDX = 1 # macro -regCP_MEC_MDBASE_HI = 0x5871 # macro -regCP_MEC_MDBASE_HI_BASE_IDX = 1 # macro -regCP_MEC_MIBOUND_LO = 0x5872 # macro -regCP_MEC_MIBOUND_LO_BASE_IDX = 1 # macro -regCP_MEC_MIBOUND_HI = 0x5873 # macro -regCP_MEC_MIBOUND_HI_BASE_IDX = 1 # macro -regCP_MEC_MDBOUND_LO = 0x5874 # macro -regCP_MEC_MDBOUND_LO_BASE_IDX = 1 # macro -regCP_MEC_MDBOUND_HI = 0x5875 # macro -regCP_MEC_MDBOUND_HI_BASE_IDX = 1 # macro -regRLC_CNTL = 0x4c00 # macro -regRLC_CNTL_BASE_IDX = 1 # macro -regRLC_F32_UCODE_VERSION = 0x4c03 # macro -regRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro -regRLC_STAT = 0x4c04 # macro -regRLC_STAT_BASE_IDX = 1 # macro -regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro -regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro -regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro -regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_0 = 0x4c0e # macro -regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_1 = 0x4c0f # macro -regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_2 = 0x4c10 # macro -regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_3 = 0x4c11 # macro -regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_INT_4 = 0x4c12 # macro -regRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_CTRL = 0x4c13 # macro -regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro -regRLC_GPM_TIMER_STAT = 0x4c14 # macro -regRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro -regRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro -regRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro -regRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro -regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro -regRLC_INT_STAT = 0x4c18 # macro -regRLC_INT_STAT_BASE_IDX = 1 # macro -regRLC_MGCG_CTRL = 0x4c1a # macro -regRLC_MGCG_CTRL_BASE_IDX = 1 # macro -regRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro -regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro -regRLC_PG_DELAY_2 = 0x4c1f # macro -regRLC_PG_DELAY_2_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro -regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro -regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro -regRLC_UCODE_CNTL = 0x4c27 # macro -regRLC_UCODE_CNTL_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_RESET = 0x4c28 # macro -regRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro -regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro -regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro -regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro -regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_INVALIDATE_CACHE = 0x4c2b # macro -regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro -regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro -regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro -regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro -regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_CTRL = 0x4c34 # macro -regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro -regRLC_CLK_COUNT_STAT = 0x4c35 # macro -regRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro -regRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro -regRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro -regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro -regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro -regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro -regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro -regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro -regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro -regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro -regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro -regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_32 = 0x4c42 # macro -regRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro -regRLC_PG_CNTL = 0x4c43 # macro -regRLC_PG_CNTL_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro -regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro -regRLC_GPM_THREAD_ENABLE = 0x4c45 # macro -regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro -regRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro -regRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro -regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro -regRLC_CGCG_CGLS_CTRL = 0x4c49 # macro -regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro -regRLC_CGCG_RAMP_CTRL = 0x4c4a # macro -regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro -regRLC_DYN_PG_STATUS = 0x4c4b # macro -regRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro -regRLC_DYN_PG_REQUEST = 0x4c4c # macro -regRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro -regRLC_PG_DELAY = 0x4c4d # macro -regRLC_PG_DELAY_BASE_IDX = 1 # macro -regRLC_WGP_STATUS = 0x4c4e # macro -regRLC_WGP_STATUS_BASE_IDX = 1 # macro -regRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro -regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro -regRLC_MAX_PG_WGP = 0x4c54 # macro -regRLC_MAX_PG_WGP_BASE_IDX = 1 # macro -regRLC_AUTO_PG_CTRL = 0x4c55 # macro -regRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro -regRLC_SERDES_RD_INDEX = 0x4c59 # macro -regRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_0 = 0x4c5a # macro -regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_1 = 0x4c5b # macro -regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_2 = 0x4c5c # macro -regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro -regRLC_SERDES_RD_DATA_3 = 0x4c5d # macro -regRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro -regRLC_SERDES_MASK = 0x4c5e # macro -regRLC_SERDES_MASK_BASE_IDX = 1 # macro -regRLC_SERDES_CTRL = 0x4c5f # macro -regRLC_SERDES_CTRL_BASE_IDX = 1 # macro -regRLC_SERDES_DATA = 0x4c60 # macro -regRLC_SERDES_DATA_BASE_IDX = 1 # macro -regRLC_SERDES_BUSY = 0x4c61 # macro -regRLC_SERDES_BUSY_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_0 = 0x4c63 # macro -regRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_1 = 0x4c64 # macro -regRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_2 = 0x4c65 # macro -regRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_3 = 0x4c66 # macro -regRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_4 = 0x4c67 # macro -regRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_5 = 0x4c68 # macro -regRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_6 = 0x4c69 # macro -regRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_7 = 0x4c6a # macro -regRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro -regRLC_STATIC_PG_STATUS = 0x4c6e # macro -regRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_16 = 0x4c76 # macro -regRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro -regRLC_PG_DELAY_3 = 0x4c78 # macro -regRLC_PG_DELAY_3_BASE_IDX = 1 # macro -regRLC_GPR_REG1 = 0x4c79 # macro -regRLC_GPR_REG1_BASE_IDX = 1 # macro -regRLC_GPR_REG2 = 0x4c7a # macro -regRLC_GPR_REG2_BASE_IDX = 1 # macro -regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro -regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro -regRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro -regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro -regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro -regRLC_SRM_CNTL = 0x4c80 # macro -regRLC_SRM_CNTL_BASE_IDX = 1 # macro -regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro -regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro -regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro -regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro -regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro -regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro -regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro -regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro -regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro -regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro -regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro -regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro -regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro -regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro -regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro -regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro -regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro -regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro -regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro -regRLC_SRM_STAT = 0x4c9b # macro -regRLC_SRM_STAT_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_8 = 0x4cad # macro -regRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_9 = 0x4cae # macro -regRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_10 = 0x4caf # macro -regRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_11 = 0x4cb0 # macro -regRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_12 = 0x4cb1 # macro -regRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro -regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro -regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro -regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro -regRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro -regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro -regRLC_UTCL1_STATUS_2 = 0x4cb6 # macro -regRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro -regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro -regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro -regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro -regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro -regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro -regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro -regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro -regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro -regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro -regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro -regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro -regRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro -regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro -regRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro -regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_0 = 0x4cc7 # macro -regRLC_SEMAPHORE_0_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_1 = 0x4cc8 # macro -regRLC_SEMAPHORE_1_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_2 = 0x4cc9 # macro -regRLC_SEMAPHORE_2_BASE_IDX = 1 # macro -regRLC_SEMAPHORE_3 = 0x4cca # macro -regRLC_SEMAPHORE_3_BASE_IDX = 1 # macro -regRLC_PACE_INT_STAT = 0x4ccc # macro -regRLC_PACE_INT_STAT_BASE_IDX = 1 # macro -regRLC_UTCL1_STATUS = 0x4cd4 # macro -regRLC_UTCL1_STATUS_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_0 = 0x4cd5 # macro -regRLC_R2I_CNTL_0_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_1 = 0x4cd6 # macro -regRLC_R2I_CNTL_1_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_2 = 0x4cd7 # macro -regRLC_R2I_CNTL_2_BASE_IDX = 1 # macro -regRLC_R2I_CNTL_3 = 0x4cd8 # macro -regRLC_R2I_CNTL_3_BASE_IDX = 1 # macro -regRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro -regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_13 = 0x4cdd # macro -regRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_14 = 0x4cde # macro -regRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro -regRLC_GPM_GENERAL_15 = 0x4cdf # macro -regRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro -regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro -regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro -regRLC_PACE_INT_DISABLE = 0x4ced # macro -regRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro -regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro -regRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro -regRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro -regRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro -regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro -regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro -regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro -regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro -regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro -regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro -regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro -regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4cfb # macro -regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4cfc # macro -regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro -regRLC_RLCV_SPARE_INT = 0x4d00 # macro -regRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_INT_0 = 0x4d04 # macro -regRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_INT_1 = 0x4d05 # macro -regRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_CTRL = 0x4d06 # macro -regRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro -regRLC_SMU_CLK_REQ = 0x4d08 # macro -regRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro -regRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro -regRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro -regRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro -regRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro -regRLC_SPARE = 0x4d0b # macro -regRLC_SPARE_BASE_IDX = 1 # macro -regRLC_SPP_CTRL = 0x4d0c # macro -regRLC_SPP_CTRL_BASE_IDX = 1 # macro -regRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro -regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro -regRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro -regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro -regRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro -regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro -regRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro -regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro -regRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro -regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro -regRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro -regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro -regRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro -regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro -regRLC_SPP_PROF_INFO_1 = 0x4d18 # macro -regRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro -regRLC_SPP_PROF_INFO_2 = 0x4d19 # macro -regRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro -regRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro -regRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro -regRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro -regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro -regRLC_SPP_STATUS = 0x4d1c # macro -regRLC_SPP_STATUS_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_0 = 0x4d1d # macro -regRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_1 = 0x4d1e # macro -regRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_2 = 0x4d1f # macro -regRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro -regRLC_SPP_PVT_STAT_3 = 0x4d20 # macro -regRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro -regRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro -regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro -regRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro -regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro -regRLC_SPP_PBB_INFO = 0x4d23 # macro -regRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro -regRLC_SPP_RESET = 0x4d24 # macro -regRLC_SPP_RESET_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro -regRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro -regRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro -regRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro -regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro -regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro -regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro -regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro -regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro -regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro -regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro -regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_CAC_MASK_CNTL = 0x4d45 # macro -regRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro -regRLC_POWER_RESIDENCY_CNTR_CTRL = 0x4d48 # macro -regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_CLK_RESIDENCY_CNTR_CTRL = 0x4d49 # macro -regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_DS_RESIDENCY_CNTR_CTRL = 0x4d4a # macro -regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_ULV_RESIDENCY_CNTR_CTRL = 0x4d4b # macro -regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_PCC_RESIDENCY_CNTR_CTRL = 0x4d4c # macro -regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_GENERAL_RESIDENCY_CNTR_CTRL = 0x4d4d # macro -regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 # macro -regRLC_POWER_RESIDENCY_EVENT_CNTR = 0x4d50 # macro -regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_CLK_RESIDENCY_EVENT_CNTR = 0x4d51 # macro -regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_DS_RESIDENCY_EVENT_CNTR = 0x4d52 # macro -regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_ULV_RESIDENCY_EVENT_CNTR = 0x4d53 # macro -regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_PCC_RESIDENCY_EVENT_CNTR = 0x4d54 # macro -regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_GENERAL_RESIDENCY_EVENT_CNTR = 0x4d55 # macro -regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 # macro -regRLC_POWER_RESIDENCY_REF_CNTR = 0x4d58 # macro -regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_CLK_RESIDENCY_REF_CNTR = 0x4d59 # macro -regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_DS_RESIDENCY_REF_CNTR = 0x4d5a # macro -regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_ULV_RESIDENCY_REF_CNTR = 0x4d5b # macro -regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_PCC_RESIDENCY_REF_CNTR = 0x4d5c # macro -regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_GENERAL_RESIDENCY_REF_CNTR = 0x4d5d # macro -regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_CTRL = 0x4d5e # macro -regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX = 1 # macro -regRLC_GFX_IH_ARBITER_STAT = 0x4d5f # macro -regRLC_GFX_IH_ARBITER_STAT_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_L = 0x4d60 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_H = 0x4d61 # macro -regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_SDMA_STAT = 0x4d62 # macro -regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX = 1 # macro -regRLC_GFX_IH_CLIENT_OTHER_STAT = 0x4d63 # macro -regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_DELAY_IND_ADDR = 0x4d64 # macro -regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_GLOBAL_DELAY_IND_DATA = 0x4d65 # macro -regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX = 1 # macro -regRLC_SPM_SE_DELAY_IND_ADDR = 0x4d66 # macro -regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX = 1 # macro -regRLC_SPM_SE_DELAY_IND_DATA = 0x4d67 # macro -regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX = 1 # macro -regRLC_LX6_CNTL = 0x4d80 # macro -regRLC_LX6_CNTL_BASE_IDX = 1 # macro -regRLC_XT_CORE_STATUS = 0x4dd4 # macro -regRLC_XT_CORE_STATUS_BASE_IDX = 1 # macro -regRLC_XT_CORE_INTERRUPT = 0x4dd5 # macro -regRLC_XT_CORE_INTERRUPT_BASE_IDX = 1 # macro -regRLC_XT_CORE_FAULT_INFO = 0x4dd6 # macro -regRLC_XT_CORE_FAULT_INFO_BASE_IDX = 1 # macro -regRLC_XT_CORE_ALT_RESET_VEC = 0x4dd7 # macro -regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX = 1 # macro -regRLC_XT_CORE_RESERVED = 0x4dd8 # macro -regRLC_XT_CORE_RESERVED_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_FORCE = 0x4dd9 # macro -regRLC_XT_INT_VEC_FORCE_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_CLEAR = 0x4dda # macro -regRLC_XT_INT_VEC_CLEAR_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_MUX_SEL = 0x4ddb # macro -regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX = 1 # macro -regRLC_XT_INT_VEC_MUX_INT_SEL = 0x4ddc # macro -regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro -regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro -regRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro -regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro -regRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro -regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro -regRLC_SPP_CAM_ADDR = 0x4de8 # macro -regRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro -regRLC_SPP_CAM_DATA = 0x4de9 # macro -regRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro -regRLC_SPP_CAM_EXT_ADDR = 0x4dea # macro -regRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro -regRLC_SPP_CAM_EXT_DATA = 0x4deb # macro -regRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_RANGE = 0x4df5 # macro -regRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_CNTL = 0x4df6 # macro -regRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_STAT = 0x4df7 # macro -regRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro -regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro -regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro -regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro -regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro -regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro -regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro -regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro -regRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro -regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro -regRLC_MEM_SLP_CNTL = 0x4e00 # macro -regRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro -regSMU_RLC_RESPONSE = 0x4e01 # macro -regSMU_RLC_RESPONSE_BASE_IDX = 1 # macro -regRLC_RLCV_SAFE_MODE = 0x4e02 # macro -regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro -regRLC_SMU_SAFE_MODE = 0x4e03 # macro -regRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro -regRLC_RLCV_COMMAND = 0x4e04 # macro -regRLC_RLCV_COMMAND_BASE_IDX = 1 # macro -regRLC_SMU_MESSAGE = 0x4e05 # macro -regRLC_SMU_MESSAGE_BASE_IDX = 1 # macro -regRLC_SMU_MESSAGE_1 = 0x4e06 # macro -regRLC_SMU_MESSAGE_1_BASE_IDX = 1 # macro -regRLC_SMU_MESSAGE_2 = 0x4e07 # macro -regRLC_SMU_MESSAGE_2_BASE_IDX = 1 # macro -regRLC_SRM_GPM_COMMAND = 0x4e08 # macro -regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro -regRLC_SRM_GPM_ABORT = 0x4e09 # macro -regRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro -regRLC_SMU_COMMAND = 0x4e0a # macro -regRLC_SMU_COMMAND_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_1 = 0x4e0b # macro -regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_2 = 0x4e0c # macro -regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_3 = 0x4e0d # macro -regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_4 = 0x4e0e # macro -regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro -regRLC_SMU_ARGUMENT_5 = 0x4e0f # macro -regRLC_SMU_ARGUMENT_5_BASE_IDX = 1 # macro -regRLC_IMU_BOOTLOAD_ADDR_HI = 0x4e10 # macro -regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro -regRLC_IMU_BOOTLOAD_ADDR_LO = 0x4e11 # macro -regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro -regRLC_IMU_BOOTLOAD_SIZE = 0x4e12 # macro -regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX = 1 # macro -regRLC_IMU_MISC = 0x4e16 # macro -regRLC_IMU_MISC_BASE_IDX = 1 # macro -regRLC_IMU_RESET_VECTOR = 0x4e17 # macro -regRLC_IMU_RESET_VECTOR_BASE_IDX = 1 # macro -regRLC_RLCS_DEC_START = 0x4e60 # macro -regRLC_RLCS_DEC_START_BASE_IDX = 1 # macro -regRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro -regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro -regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro -regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro -regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro -regRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro -regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro -regRLC_RLCS_CGCG_REQUEST = 0x4e66 # macro -regRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro -regRLC_RLCS_CGCG_STATUS = 0x4e67 # macro -regRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_SOC_DS_CNTL = 0x4e68 # macro -regRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_DS_CNTL = 0x4e69 # macro -regRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL = 0x4e6a # macro -regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX = 1 # macro -regRLC_GPM_STAT = 0x4e6b # macro -regRLC_GPM_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_STAT = 0x4e6b # macro -regRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6c # macro -regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro -regRLC_RLCS_DIDT_FORCE_STALL = 0x4e6d # macro -regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_CMD_STATUS = 0x4e6e # macro -regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e6f # macro -regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_SCH_BLOCK = 0x4e70 # macro -regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro -regRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e71 # macro -regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_STAT_2 = 0x4e72 # macro -regRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro -regRLC_RLCS_GRBM_SOFT_RESET = 0x4e73 # macro -regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro -regRLC_RLCS_PG_CHANGE_STATUS = 0x4e74 # macro -regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_PG_CHANGE_READ = 0x4e75 # macro -regRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro -regRLC_RLCS_IH_SEMAPHORE = 0x4e76 # macro -regRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro -regRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e77 # macro -regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro -regRLC_RLCS_WGP_STATUS = 0x4e78 # macro -regRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_WGP_READ = 0x4e79 # macro -regRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_CTRL_1 = 0x4e7a # macro -regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_CTRL_2 = 0x4e7b # macro -regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_INFO_1 = 0x4e7c # macro -regRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro -regRLC_RLCS_CP_INT_INFO_2 = 0x4e7d # macro -regRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_INT_CTRL = 0x4e7e # macro -regRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_INT_INFO_1 = 0x4e7f # macro -regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_INT_INFO_2 = 0x4e80 # macro -regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro -regRLC_RLCS_DSM_TRIG = 0x4e81 # macro -regRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro -regRLC_RLCS_BOOTLOAD_STATUS = 0x4e82 # macro -regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_POWER_BRAKE_CNTL = 0x4e83 # macro -regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4e84 # macro -regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4e85 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4e86 # macro -regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_CMP_IDLE_CNTL = 0x4e87 # macro -regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_0 = 0x4e88 # macro -regRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_1 = 0x4e89 # macro -regRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_2 = 0x4e8a # macro -regRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_3 = 0x4e8b # macro -regRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_4 = 0x4e8c # macro -regRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_5 = 0x4e8d # macro -regRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_6 = 0x4e8e # macro -regRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_7 = 0x4e8f # macro -regRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_8 = 0x4e90 # macro -regRLC_RLCS_GENERAL_8_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_9 = 0x4e91 # macro -regRLC_RLCS_GENERAL_9_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_10 = 0x4e92 # macro -regRLC_RLCS_GENERAL_10_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_11 = 0x4e93 # macro -regRLC_RLCS_GENERAL_11_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_12 = 0x4e94 # macro -regRLC_RLCS_GENERAL_12_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_13 = 0x4e95 # macro -regRLC_RLCS_GENERAL_13_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_14 = 0x4e96 # macro -regRLC_RLCS_GENERAL_14_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_15 = 0x4e97 # macro -regRLC_RLCS_GENERAL_15_BASE_IDX = 1 # macro -regRLC_RLCS_GENERAL_16 = 0x4e98 # macro -regRLC_RLCS_GENERAL_16_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro -regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro -regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro -regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro -regRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro -regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro -regRLC_RLCS_SPM_SQTT_MODE = 0x4ec9 # macro -regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro -regRLC_RLCS_CP_DMA_SRCID_OVER = 0x4eca # macro -regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4ecb # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4ecc # macro -regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_VIDCHG_CNTL = 0x4ecd # macro -regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_EDC_INT_CNTL = 0x4ece # macro -regRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_KMD_LOG_CNTL1 = 0x4ecf # macro -regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro -regRLC_RLCS_KMD_LOG_CNTL2 = 0x4ed0 # macro -regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ed1 # macro -regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ed2 # macro -regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_RLCS_SRM_SRCID_CNTL = 0x4ed3 # macro -regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_0 = 0x4ed4 # macro -regRLC_RLCS_GCR_DATA_0_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_1 = 0x4ed5 # macro -regRLC_RLCS_GCR_DATA_1_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_2 = 0x4ed6 # macro -regRLC_RLCS_GCR_DATA_2_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_DATA_3 = 0x4ed7 # macro -regRLC_RLCS_GCR_DATA_3_BASE_IDX = 1 # macro -regRLC_RLCS_GCR_STATUS = 0x4ed8 # macro -regRLC_RLCS_GCR_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4ed9 # macro -regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro -regRLC_RLCS_UTCL2_CNTL = 0x4eda # macro -regRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA0 = 0x4edb # macro -regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA1 = 0x4edc # macro -regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA2 = 0x4edd # macro -regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA3 = 0x4ede # macro -regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_DATA4 = 0x4edf # macro -regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_CONTROL = 0x4ee0 # macro -regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MSG_CNTL = 0x4ee1 # macro -regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_MSG_DATA0 = 0x4ee2 # macro -regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_MSG_CONTROL = 0x4ee3 # macro -regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_MSG_CNTL = 0x4ee4 # macro -regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 = 0x4ee5 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 = 0x4ee6 # macro -regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_MUTEX_CNTL = 0x4ee7 # macro -regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RLC_STATUS = 0x4ee8 # macro -regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_RLC_IMU_STATUS = 0x4ee9 # macro -regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_DATA_1 = 0x4eea # macro -regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_1_LSB = 0x4eeb # macro -regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_1_MSB = 0x4eec # macro -regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_DATA_0 = 0x4eed # macro -regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_0_LSB = 0x4eee # macro -regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_ADDR_0_MSB = 0x4eef # macro -regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_RAM_CNTL = 0x4ef0 # macro -regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_IMU_GFX_DOORBELL_FENCE = 0x4ef1 # macro -regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_CNTL_1 = 0x4ef3 # macro -regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_CNTL_2 = 0x4ef4 # macro -regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_STAT = 0x4ef5 # macro -regRLC_RLCS_SDMA_INT_STAT_BASE_IDX = 1 # macro -regRLC_RLCS_SDMA_INT_INFO = 0x4ef6 # macro -regRLC_RLCS_SDMA_INT_INFO_BASE_IDX = 1 # macro -regRLC_RLCS_PMM_CGCG_CNTL = 0x4ef7 # macro -regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_MEM_POWER_CTRL_LO = 0x4ef8 # macro -regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX = 1 # macro -regRLC_RLCS_GFX_RM_CNTL = 0x4efa # macro -regRLC_RLCS_GFX_RM_CNTL_BASE_IDX = 1 # macro -regRLC_RLCS_DEC_END = 0x4fff # macro -regRLC_RLCS_DEC_END_BASE_IDX = 1 # macro -regRLC_SAFE_MODE = 0x0980 # macro -regRLC_SAFE_MODE_BASE_IDX = 1 # macro -regRLC_SPM_SAMPLE_CNT = 0x0981 # macro -regRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro -regRLC_SPM_MC_CNTL = 0x0982 # macro -regRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro -regRLC_SPM_INT_CNTL = 0x0983 # macro -regRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro -regRLC_SPM_INT_STATUS = 0x0984 # macro -regRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro -regRLC_SPM_INT_INFO_1 = 0x0985 # macro -regRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro -regRLC_SPM_INT_INFO_2 = 0x0986 # macro -regRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro -regRLC_CSIB_ADDR_LO = 0x0987 # macro -regRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro -regRLC_CSIB_ADDR_HI = 0x0988 # macro -regRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro -regRLC_CSIB_LENGTH = 0x0989 # macro -regRLC_CSIB_LENGTH_BASE_IDX = 1 # macro -regRLC_CP_SCHEDULERS = 0x098a # macro -regRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro -regRLC_CP_EOF_INT = 0x098b # macro -regRLC_CP_EOF_INT_BASE_IDX = 1 # macro -regRLC_CP_EOF_INT_CNT = 0x098c # macro -regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro -regRLC_SPARE_INT_0 = 0x098d # macro -regRLC_SPARE_INT_0_BASE_IDX = 1 # macro -regRLC_SPARE_INT_1 = 0x098e # macro -regRLC_SPARE_INT_1_BASE_IDX = 1 # macro -regRLC_SPARE_INT_2 = 0x098f # macro -regRLC_SPARE_INT_2_BASE_IDX = 1 # macro -regRLC_PACE_SPARE_INT = 0x0990 # macro -regRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro -regRLC_PACE_SPARE_INT_1 = 0x0991 # macro -regRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro -regRLC_RLCV_SPARE_INT_1 = 0x0992 # macro -regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro -regCGTS_TCC_DISABLE = 0x5006 # macro -regCGTS_TCC_DISABLE_BASE_IDX = 1 # macro -regCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro -regCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_PA_CLK_CTRL = 0x5088 # macro -regCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL0 = 0x5089 # macro -regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL1 = 0x508a # macro -regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL2 = 0x508b # macro -regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro -regCGTT_SQG_CLK_CTRL = 0x508d # macro -regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro -regSQ_ALU_CLK_CTRL = 0x508e # macro -regSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro -regSQ_TEX_CLK_CTRL = 0x508f # macro -regSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro -regSQ_LDS_CLK_CTRL = 0x5090 # macro -regSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro -regICG_SP_CLK_CTRL = 0x5093 # macro -regICG_SP_CLK_CTRL_BASE_IDX = 1 # macro -regTA_CGTT_CTRL = 0x509d # macro -regTA_CGTT_CTRL_BASE_IDX = 1 # macro -regDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro -regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro -regCB_CGTT_SCLK_CTRL = 0x50a8 # macro -regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro -regCGTT_CP_CLK_CTRL = 0x50b0 # macro -regCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_CPF_CLK_CTRL = 0x50b1 # macro -regCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_CPC_CLK_CTRL = 0x50b2 # macro -regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_RLC_CLK_CTRL = 0x50b5 # macro -regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL3 = 0x50bc # macro -regCGTT_SC_CLK_CTRL3_BASE_IDX = 1 # macro -regCGTT_SC_CLK_CTRL4 = 0x50bd # macro -regCGTT_SC_CLK_CTRL4_BASE_IDX = 1 # macro -regGCEA_ICG_CTRL = 0x50c4 # macro -regGCEA_ICG_CTRL_BASE_IDX = 1 # macro -regGL1I_GL1R_MGCG_OVERRIDE = 0x50e4 # macro -regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX = 1 # macro -regGL1H_ICG_CTRL = 0x50e8 # macro -regGL1H_ICG_CTRL_BASE_IDX = 1 # macro -regCHI_CHR_MGCG_OVERRIDE = 0x50e9 # macro -regCHI_CHR_MGCG_OVERRIDE_BASE_IDX = 1 # macro -regICG_GL1C_CLK_CTRL = 0x50ec # macro -regICG_GL1C_CLK_CTRL_BASE_IDX = 1 # macro -regICG_GL1A_CTRL = 0x50f0 # macro -regICG_GL1A_CTRL_BASE_IDX = 1 # macro -regICG_CHA_CTRL = 0x50f1 # macro -regICG_CHA_CTRL_BASE_IDX = 1 # macro -regGUS_ICG_CTRL = 0x50f4 # macro -regGUS_ICG_CTRL_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL0 = 0x50f8 # macro -regCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL1 = 0x50f9 # macro -regCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL2 = 0x50fa # macro -regCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro -regCGTT_PH_CLK_CTRL3 = 0x50fb # macro -regCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro -regGFX_ICG_GL2C_CTRL = 0x50fc # macro -regGFX_ICG_GL2C_CTRL_BASE_IDX = 1 # macro -regGFX_ICG_GL2C_CTRL1 = 0x50fd # macro -regGFX_ICG_GL2C_CTRL1_BASE_IDX = 1 # macro -regICG_LDS_CLK_CTRL = 0x5114 # macro -regICG_LDS_CLK_CTRL_BASE_IDX = 1 # macro -regICG_CHC_CLK_CTRL = 0x5140 # macro -regICG_CHC_CLK_CTRL_BASE_IDX = 1 # macro -regICG_CHCG_CLK_CTRL = 0x5144 # macro -regICG_CHCG_CLK_CTRL_BASE_IDX = 1 # macro -regGFX_PIPE_PRIORITY = 0x587f # macro -regGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro -regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro -regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro -regGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro -regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro -regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro -regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro -regGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro -regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro -regGC_IH_COOKIE_0_PTR = 0x5a07 # macro -regGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro -regGRBM_SE_REMAP_CNTL = 0x5a08 # macro -regGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro -regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro -regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro -regRLC_SDMA0_STATUS = 0x5b18 # macro -regRLC_SDMA0_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA1_STATUS = 0x5b19 # macro -regRLC_SDMA1_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA2_STATUS = 0x5b1a # macro -regRLC_SDMA2_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA3_STATUS = 0x5b1b # macro -regRLC_SDMA3_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA0_BUSY_STATUS = 0x5b1c # macro -regRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA1_BUSY_STATUS = 0x5b1d # macro -regRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA2_BUSY_STATUS = 0x5b1e # macro -regRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_SDMA3_BUSY_STATUS = 0x5b1f # macro -regRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro -regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro -regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_INT_1 = 0x5b26 # macro -regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_CTRL = 0x5b27 # macro -regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro -regRLC_RLCV_TIMER_STAT = 0x5b28 # macro -regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro -regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VF_MASK = 0x5b2d # macro -regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro -regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro -regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro -regRLC_BUSY_CLK_CNTL = 0x5b30 # macro -regRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro -regRLC_CLK_CNTL = 0x5b31 # macro -regRLC_CLK_CNTL_BASE_IDX = 1 # macro -regRLC_PACE_TIMER_STAT = 0x5b33 # macro -regRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro -regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro -regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro -regRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro -regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro -regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro -regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_0 = 0x5b38 # macro -regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_3 = 0x5b3a # macro -regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_1 = 0x5b3b # macro -regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCH_2 = 0x5b3c # macro -regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro -regRLC_PACE_INT_FORCE = 0x5b3d # macro -regRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro -regRLC_PACE_INT_CLEAR = 0x5b3e # macro -regRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_INT_STAT = 0x5b3f # macro -regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro -regRLC_IH_COOKIE = 0x5b41 # macro -regRLC_IH_COOKIE_BASE_IDX = 1 # macro -regRLC_IH_COOKIE_CNTL = 0x5b42 # macro -regRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro -regRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro -regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro -regRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro -regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro -regRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro -regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro -regRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro -regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro -regRLC_GPU_IOV_F32_RESET = 0x5b47 # macro -regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro -regRLC_GPU_IOV_UCODE_ADDR = 0x5b48 # macro -regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_UCODE_DATA = 0x5b49 # macro -regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro -regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_F32_INVALIDATE_CACHE = 0x5b4b # macro -regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro -regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro -regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro -regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b50 # macro -regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SCRATCH_DATA = 0x5b51 # macro -regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro -regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro -regRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro -regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro -regRLC_GPM_UCODE_ADDR = 0x5b60 # macro -regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro -regRLC_GPM_UCODE_DATA = 0x5b61 # macro -regRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro -regRLC_GPM_IRAM_ADDR = 0x5b62 # macro -regRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_GPM_IRAM_DATA = 0x5b63 # macro -regRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_RLCP_IRAM_ADDR = 0x5b64 # macro -regRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_RLCP_IRAM_DATA = 0x5b65 # macro -regRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_RLCV_IRAM_ADDR = 0x5b66 # macro -regRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_RLCV_IRAM_DATA = 0x5b67 # macro -regRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_LX6_DRAM_ADDR = 0x5b68 # macro -regRLC_LX6_DRAM_ADDR_BASE_IDX = 1 # macro -regRLC_LX6_DRAM_DATA = 0x5b69 # macro -regRLC_LX6_DRAM_DATA_BASE_IDX = 1 # macro -regRLC_LX6_IRAM_ADDR = 0x5b6a # macro -regRLC_LX6_IRAM_ADDR_BASE_IDX = 1 # macro -regRLC_LX6_IRAM_DATA = 0x5b6b # macro -regRLC_LX6_IRAM_DATA_BASE_IDX = 1 # macro -regRLC_PACE_UCODE_ADDR = 0x5b6c # macro -regRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro -regRLC_PACE_UCODE_DATA = 0x5b6d # macro -regRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro -regRLC_GPM_SCRATCH_ADDR = 0x5b6e # macro -regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro -regRLC_GPM_SCRATCH_DATA = 0x5b6f # macro -regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro -regRLC_SRM_DRAM_ADDR = 0x5b71 # macro -regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro -regRLC_SRM_DRAM_DATA = 0x5b72 # macro -regRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro -regRLC_SRM_ARAM_ADDR = 0x5b73 # macro -regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro -regRLC_SRM_ARAM_DATA = 0x5b74 # macro -regRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro -regRLC_PACE_SCRATCH_ADDR = 0x5b77 # macro -regRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro -regRLC_PACE_SCRATCH_DATA = 0x5b78 # macro -regRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro -regRLC_GTS_OFFSET_LSB = 0x5b79 # macro -regRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro -regRLC_GTS_OFFSET_MSB = 0x5b7a # macro -regRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_0 = 0x5b80 # macro -regGL2_PIPE_STEER_0_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_1 = 0x5b81 # macro -regGL2_PIPE_STEER_1_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_2 = 0x5b82 # macro -regGL2_PIPE_STEER_2_BASE_IDX = 1 # macro -regGL2_PIPE_STEER_3 = 0x5b83 # macro -regGL2_PIPE_STEER_3_BASE_IDX = 1 # macro -regGL1_PIPE_STEER = 0x5b84 # macro -regGL1_PIPE_STEER_BASE_IDX = 1 # macro -regCH_PIPE_STEER = 0x5b88 # macro -regCH_PIPE_STEER_BASE_IDX = 1 # macro -regGC_USER_SHADER_ARRAY_CONFIG = 0x5b90 # macro -regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 1 # macro -regGC_USER_PRIM_CONFIG = 0x5b91 # macro -regGC_USER_PRIM_CONFIG_BASE_IDX = 1 # macro -regGC_USER_SA_UNIT_DISABLE = 0x5b92 # macro -regGC_USER_SA_UNIT_DISABLE_BASE_IDX = 1 # macro -regGC_USER_RB_REDUNDANCY = 0x5b93 # macro -regGC_USER_RB_REDUNDANCY_BASE_IDX = 1 # macro -regGC_USER_RB_BACKEND_DISABLE = 0x5b94 # macro -regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 1 # macro -regGC_USER_RMI_REDUNDANCY = 0x5b95 # macro -regGC_USER_RMI_REDUNDANCY_BASE_IDX = 1 # macro -regCGTS_USER_TCC_DISABLE = 0x5b96 # macro -regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro -regGC_USER_SHADER_RATE_CONFIG = 0x5b97 # macro -regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro -regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro -regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro -regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro -regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro -regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro -regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro -regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro -regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro -regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro -regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro -regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro -regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro -regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro -regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro -regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro -regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro -regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro -regCP_MES_DM_INDEX_ADDR = 0x5c00 # macro -regCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro -regCP_MES_DM_INDEX_DATA = 0x5c01 # macro -regCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro -regCP_MEC_DM_INDEX_ADDR = 0x5c02 # macro -regCP_MEC_DM_INDEX_ADDR_BASE_IDX = 1 # macro -regCP_MEC_DM_INDEX_DATA = 0x5c03 # macro -regCP_MEC_DM_INDEX_DATA_BASE_IDX = 1 # macro -regCP_GFX_RS64_DM_INDEX_ADDR = 0x5c04 # macro -regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX = 1 # macro -regCP_GFX_RS64_DM_INDEX_DATA = 0x5c05 # macro -regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX = 1 # macro -regCPG_PSP_DEBUG = 0x5c10 # macro -regCPG_PSP_DEBUG_BASE_IDX = 1 # macro -regCPC_PSP_DEBUG = 0x5c11 # macro -regCPC_PSP_DEBUG_BASE_IDX = 1 # macro -regGRBM_SEC_CNTL = 0x5e0d # macro -regGRBM_SEC_CNTL_BASE_IDX = 1 # macro -regGRBM_CAM_INDEX = 0x5e10 # macro -regGRBM_CAM_INDEX_BASE_IDX = 1 # macro -regGRBM_HYP_CAM_INDEX = 0x5e10 # macro -regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro -regGRBM_CAM_DATA = 0x5e11 # macro -regGRBM_CAM_DATA_BASE_IDX = 1 # macro -regGRBM_HYP_CAM_DATA = 0x5e11 # macro -regGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro -regGRBM_CAM_DATA_UPPER = 0x5e12 # macro -regGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro -regGRBM_HYP_CAM_DATA_UPPER = 0x5e12 # macro -regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro -regRLC_FWL_FIRST_VIOL_ADDR = 0x5f26 # macro -regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_0 = 0x4000 # macro -regGFX_IMU_C2PMSG_0_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_1 = 0x4001 # macro -regGFX_IMU_C2PMSG_1_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_2 = 0x4002 # macro -regGFX_IMU_C2PMSG_2_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_3 = 0x4003 # macro -regGFX_IMU_C2PMSG_3_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_4 = 0x4004 # macro -regGFX_IMU_C2PMSG_4_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_5 = 0x4005 # macro -regGFX_IMU_C2PMSG_5_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_6 = 0x4006 # macro -regGFX_IMU_C2PMSG_6_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_7 = 0x4007 # macro -regGFX_IMU_C2PMSG_7_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_8 = 0x4008 # macro -regGFX_IMU_C2PMSG_8_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_9 = 0x4009 # macro -regGFX_IMU_C2PMSG_9_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_10 = 0x400a # macro -regGFX_IMU_C2PMSG_10_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_11 = 0x400b # macro -regGFX_IMU_C2PMSG_11_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_12 = 0x400c # macro -regGFX_IMU_C2PMSG_12_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_13 = 0x400d # macro -regGFX_IMU_C2PMSG_13_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_14 = 0x400e # macro -regGFX_IMU_C2PMSG_14_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_15 = 0x400f # macro -regGFX_IMU_C2PMSG_15_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_16 = 0x4010 # macro -regGFX_IMU_C2PMSG_16_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_17 = 0x4011 # macro -regGFX_IMU_C2PMSG_17_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_18 = 0x4012 # macro -regGFX_IMU_C2PMSG_18_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_19 = 0x4013 # macro -regGFX_IMU_C2PMSG_19_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_20 = 0x4014 # macro -regGFX_IMU_C2PMSG_20_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_21 = 0x4015 # macro -regGFX_IMU_C2PMSG_21_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_22 = 0x4016 # macro -regGFX_IMU_C2PMSG_22_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_23 = 0x4017 # macro -regGFX_IMU_C2PMSG_23_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_24 = 0x4018 # macro -regGFX_IMU_C2PMSG_24_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_25 = 0x4019 # macro -regGFX_IMU_C2PMSG_25_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_26 = 0x401a # macro -regGFX_IMU_C2PMSG_26_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_27 = 0x401b # macro -regGFX_IMU_C2PMSG_27_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_28 = 0x401c # macro -regGFX_IMU_C2PMSG_28_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_29 = 0x401d # macro -regGFX_IMU_C2PMSG_29_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_30 = 0x401e # macro -regGFX_IMU_C2PMSG_30_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_31 = 0x401f # macro -regGFX_IMU_C2PMSG_31_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_32 = 0x4020 # macro -regGFX_IMU_C2PMSG_32_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_33 = 0x4021 # macro -regGFX_IMU_C2PMSG_33_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_34 = 0x4022 # macro -regGFX_IMU_C2PMSG_34_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_35 = 0x4023 # macro -regGFX_IMU_C2PMSG_35_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_36 = 0x4024 # macro -regGFX_IMU_C2PMSG_36_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_37 = 0x4025 # macro -regGFX_IMU_C2PMSG_37_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_38 = 0x4026 # macro -regGFX_IMU_C2PMSG_38_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_39 = 0x4027 # macro -regGFX_IMU_C2PMSG_39_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_40 = 0x4028 # macro -regGFX_IMU_C2PMSG_40_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_41 = 0x4029 # macro -regGFX_IMU_C2PMSG_41_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_42 = 0x402a # macro -regGFX_IMU_C2PMSG_42_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_43 = 0x402b # macro -regGFX_IMU_C2PMSG_43_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_44 = 0x402c # macro -regGFX_IMU_C2PMSG_44_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_45 = 0x402d # macro -regGFX_IMU_C2PMSG_45_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_46 = 0x402e # macro -regGFX_IMU_C2PMSG_46_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_47 = 0x402f # macro -regGFX_IMU_C2PMSG_47_BASE_IDX = 1 # macro -regGFX_IMU_MSG_FLAGS = 0x403f # macro -regGFX_IMU_MSG_FLAGS_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL0 = 0x4040 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL1 = 0x4041 # macro -regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_PWRMGT_IRQ_CTRL = 0x4042 # macro -regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_MP1_MUTEX = 0x4043 # macro -regGFX_IMU_MP1_MUTEX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_4 = 0x4046 # macro -regGFX_IMU_RLC_DATA_4_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_3 = 0x4047 # macro -regGFX_IMU_RLC_DATA_3_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_2 = 0x4048 # macro -regGFX_IMU_RLC_DATA_2_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_1 = 0x4049 # macro -regGFX_IMU_RLC_DATA_1_BASE_IDX = 1 # macro -regGFX_IMU_RLC_DATA_0 = 0x404a # macro -regGFX_IMU_RLC_DATA_0_BASE_IDX = 1 # macro -regGFX_IMU_RLC_CMD = 0x404b # macro -regGFX_IMU_RLC_CMD_BASE_IDX = 1 # macro -regGFX_IMU_RLC_MUTEX = 0x404c # macro -regGFX_IMU_RLC_MUTEX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_MSG_STATUS = 0x404f # macro -regGFX_IMU_RLC_MSG_STATUS_BASE_IDX = 1 # macro -regRLC_GFX_IMU_DATA_0 = 0x4052 # macro -regRLC_GFX_IMU_DATA_0_BASE_IDX = 1 # macro -regRLC_GFX_IMU_CMD = 0x4053 # macro -regRLC_GFX_IMU_CMD_BASE_IDX = 1 # macro -regGFX_IMU_RLC_STATUS = 0x4054 # macro -regGFX_IMU_RLC_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_STATUS = 0x4055 # macro -regGFX_IMU_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_SOC_DATA = 0x4059 # macro -regGFX_IMU_SOC_DATA_BASE_IDX = 1 # macro -regGFX_IMU_SOC_ADDR = 0x405a # macro -regGFX_IMU_SOC_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_SOC_REQ = 0x405b # macro -regGFX_IMU_SOC_REQ_BASE_IDX = 1 # macro -regGFX_IMU_VF_CTRL = 0x405c # macro -regGFX_IMU_VF_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_TELEMETRY = 0x4060 # macro -regGFX_IMU_TELEMETRY_BASE_IDX = 1 # macro -regGFX_IMU_TELEMETRY_DATA = 0x4061 # macro -regGFX_IMU_TELEMETRY_DATA_BASE_IDX = 1 # macro -regGFX_IMU_TELEMETRY_TEMPERATURE = 0x4062 # macro -regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_0 = 0x4068 # macro -regGFX_IMU_SCRATCH_0_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_1 = 0x4069 # macro -regGFX_IMU_SCRATCH_1_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_2 = 0x406a # macro -regGFX_IMU_SCRATCH_2_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_3 = 0x406b # macro -regGFX_IMU_SCRATCH_3_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_4 = 0x406c # macro -regGFX_IMU_SCRATCH_4_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_5 = 0x406d # macro -regGFX_IMU_SCRATCH_5_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_6 = 0x406e # macro -regGFX_IMU_SCRATCH_6_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_7 = 0x406f # macro -regGFX_IMU_SCRATCH_7_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_8 = 0x4070 # macro -regGFX_IMU_SCRATCH_8_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_9 = 0x4071 # macro -regGFX_IMU_SCRATCH_9_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_10 = 0x4072 # macro -regGFX_IMU_SCRATCH_10_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_11 = 0x4073 # macro -regGFX_IMU_SCRATCH_11_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_12 = 0x4074 # macro -regGFX_IMU_SCRATCH_12_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_13 = 0x4075 # macro -regGFX_IMU_SCRATCH_13_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_14 = 0x4076 # macro -regGFX_IMU_SCRATCH_14_BASE_IDX = 1 # macro -regGFX_IMU_SCRATCH_15 = 0x4077 # macro -regGFX_IMU_SCRATCH_15_BASE_IDX = 1 # macro -regGFX_IMU_FW_GTS_LO = 0x4078 # macro -regGFX_IMU_FW_GTS_LO_BASE_IDX = 1 # macro -regGFX_IMU_FW_GTS_HI = 0x4079 # macro -regGFX_IMU_FW_GTS_HI_BASE_IDX = 1 # macro -regGFX_IMU_GTS_OFFSET_LO = 0x407a # macro -regGFX_IMU_GTS_OFFSET_LO_BASE_IDX = 1 # macro -regGFX_IMU_GTS_OFFSET_HI = 0x407b # macro -regGFX_IMU_GTS_OFFSET_HI_BASE_IDX = 1 # macro -regGFX_IMU_RLC_GTS_OFFSET_LO = 0x407c # macro -regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX = 1 # macro -regGFX_IMU_RLC_GTS_OFFSET_HI = 0x407d # macro -regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX = 1 # macro -regGFX_IMU_CORE_INT_STATUS = 0x407f # macro -regGFX_IMU_CORE_INT_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_MASK = 0x4080 # macro -regGFX_IMU_PIC_INT_MASK_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_LVL = 0x4081 # macro -regGFX_IMU_PIC_INT_LVL_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_EDGE = 0x4082 # macro -regGFX_IMU_PIC_INT_EDGE_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_0 = 0x4083 # macro -regGFX_IMU_PIC_INT_PRI_0_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_1 = 0x4084 # macro -regGFX_IMU_PIC_INT_PRI_1_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_2 = 0x4085 # macro -regGFX_IMU_PIC_INT_PRI_2_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_3 = 0x4086 # macro -regGFX_IMU_PIC_INT_PRI_3_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_4 = 0x4087 # macro -regGFX_IMU_PIC_INT_PRI_4_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_5 = 0x4088 # macro -regGFX_IMU_PIC_INT_PRI_5_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_6 = 0x4089 # macro -regGFX_IMU_PIC_INT_PRI_6_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_PRI_7 = 0x408a # macro -regGFX_IMU_PIC_INT_PRI_7_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INT_STATUS = 0x408b # macro -regGFX_IMU_PIC_INT_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INTR = 0x408c # macro -regGFX_IMU_PIC_INTR_BASE_IDX = 1 # macro -regGFX_IMU_PIC_INTR_ID = 0x408d # macro -regGFX_IMU_PIC_INTR_ID_BASE_IDX = 1 # macro -regGFX_IMU_IH_CTRL_1 = 0x4090 # macro -regGFX_IMU_IH_CTRL_1_BASE_IDX = 1 # macro -regGFX_IMU_IH_CTRL_2 = 0x4091 # macro -regGFX_IMU_IH_CTRL_2_BASE_IDX = 1 # macro -regGFX_IMU_IH_CTRL_3 = 0x4092 # macro -regGFX_IMU_IH_CTRL_3_BASE_IDX = 1 # macro -regGFX_IMU_IH_STATUS = 0x4093 # macro -regGFX_IMU_IH_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_FUSESTRAP = 0x4094 # macro -regGFX_IMU_SMUIO_VIDCHG_CTRL = 0x4098 # macro -regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_GFXCLK_BYPASS_CTRL = 0x409c # macro -regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_CLK_CTRL = 0x409d # macro -regGFX_IMU_CLK_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_DOORBELL_CONTROL = 0x409e # macro -regGFX_IMU_DOORBELL_CONTROL_BASE_IDX = 1 # macro -regGFX_IMU_RLC_CG_CTRL = 0x40a0 # macro -regGFX_IMU_RLC_CG_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_RLC_THROTTLE_GFX = 0x40a1 # macro -regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RESET_VECTOR = 0x40a2 # macro -regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX = 1 # macro -regGFX_IMU_RLC_OVERRIDE = 0x40a3 # macro -regGFX_IMU_RLC_OVERRIDE_BASE_IDX = 1 # macro -regGFX_IMU_DPM_CONTROL = 0x40a8 # macro -regGFX_IMU_DPM_CONTROL_BASE_IDX = 1 # macro -regGFX_IMU_DPM_ACC = 0x40a9 # macro -regGFX_IMU_DPM_ACC_BASE_IDX = 1 # macro -regGFX_IMU_DPM_REF_COUNTER = 0x40aa # macro -regGFX_IMU_DPM_REF_COUNTER_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_INDEX = 0x40ac # macro -regGFX_IMU_RLC_RAM_INDEX_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_ADDR_HIGH = 0x40ad # macro -regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_ADDR_LOW = 0x40ae # macro -regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX = 1 # macro -regGFX_IMU_RLC_RAM_DATA = 0x40af # macro -regGFX_IMU_RLC_RAM_DATA_BASE_IDX = 1 # macro -regGFX_IMU_FENCE_CTRL = 0x40b0 # macro -regGFX_IMU_FENCE_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_FENCE_LOG_INIT = 0x40b1 # macro -regGFX_IMU_FENCE_LOG_INIT_BASE_IDX = 1 # macro -regGFX_IMU_FENCE_LOG_ADDR = 0x40b2 # macro -regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_PROGRAM_CTR = 0x40b5 # macro -regGFX_IMU_PROGRAM_CTR_BASE_IDX = 1 # macro -regGFX_IMU_CORE_CTRL = 0x40b6 # macro -regGFX_IMU_CORE_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_CORE_STATUS = 0x40b7 # macro -regGFX_IMU_CORE_STATUS_BASE_IDX = 1 # macro -regGFX_IMU_PWROKRAW = 0x40b8 # macro -regGFX_IMU_PWROKRAW_BASE_IDX = 1 # macro -regGFX_IMU_PWROK = 0x40b9 # macro -regGFX_IMU_PWROK_BASE_IDX = 1 # macro -regGFX_IMU_GAP_PWROK = 0x40ba # macro -regGFX_IMU_GAP_PWROK_BASE_IDX = 1 # macro -regGFX_IMU_RESETn = 0x40bb # macro -regGFX_IMU_RESETn_BASE_IDX = 1 # macro -regGFX_IMU_GFX_RESET_CTRL = 0x40bc # macro -regGFX_IMU_GFX_RESET_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_AEB_OVERRIDE = 0x40bd # macro -regGFX_IMU_AEB_OVERRIDE_BASE_IDX = 1 # macro -regGFX_IMU_VDCI_RESET_CTRL = 0x40be # macro -regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_GFX_ISO_CTRL = 0x40bf # macro -regGFX_IMU_GFX_ISO_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CTRL0 = 0x40c0 # macro -regGFX_IMU_TIMER0_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CTRL1 = 0x40c1 # macro -regGFX_IMU_TIMER0_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP_AUTOINC = 0x40c2 # macro -regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP_INTEN = 0x40c3 # macro -regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP0 = 0x40c4 # macro -regGFX_IMU_TIMER0_CMP0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP1 = 0x40c5 # macro -regGFX_IMU_TIMER0_CMP1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_CMP3 = 0x40c7 # macro -regGFX_IMU_TIMER0_CMP3_BASE_IDX = 1 # macro -regGFX_IMU_TIMER0_VALUE = 0x40c8 # macro -regGFX_IMU_TIMER0_VALUE_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CTRL0 = 0x40c9 # macro -regGFX_IMU_TIMER1_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CTRL1 = 0x40ca # macro -regGFX_IMU_TIMER1_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP_AUTOINC = 0x40cb # macro -regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP_INTEN = 0x40cc # macro -regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP0 = 0x40cd # macro -regGFX_IMU_TIMER1_CMP0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP1 = 0x40ce # macro -regGFX_IMU_TIMER1_CMP1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_CMP3 = 0x40d0 # macro -regGFX_IMU_TIMER1_CMP3_BASE_IDX = 1 # macro -regGFX_IMU_TIMER1_VALUE = 0x40d1 # macro -regGFX_IMU_TIMER1_VALUE_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CTRL0 = 0x40d2 # macro -regGFX_IMU_TIMER2_CTRL0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CTRL1 = 0x40d3 # macro -regGFX_IMU_TIMER2_CTRL1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP_AUTOINC = 0x40d4 # macro -regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP_INTEN = 0x40d5 # macro -regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP0 = 0x40d6 # macro -regGFX_IMU_TIMER2_CMP0_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP1 = 0x40d7 # macro -regGFX_IMU_TIMER2_CMP1_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_CMP3 = 0x40d9 # macro -regGFX_IMU_TIMER2_CMP3_BASE_IDX = 1 # macro -regGFX_IMU_TIMER2_VALUE = 0x40da # macro -regGFX_IMU_TIMER2_VALUE_BASE_IDX = 1 # macro -regGFX_IMU_FUSE_CTRL = 0x40e0 # macro -regGFX_IMU_FUSE_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_D_RAM_ADDR = 0x40fc # macro -regGFX_IMU_D_RAM_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_D_RAM_DATA = 0x40fd # macro -regGFX_IMU_D_RAM_DATA_BASE_IDX = 1 # macro -regGFX_IMU_GFX_IH_GASKET_CTRL = 0x40ff # macro -regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX = 1 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_HI = 0x5f81 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX = 1 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_LO = 0x5f82 # macro -regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX = 1 # macro -regGFX_IMU_RLC_BOOTLOADER_SIZE = 0x5f83 # macro -regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX = 1 # macro -regGFX_IMU_I_RAM_ADDR = 0x5f90 # macro -regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 # macro -regGFX_IMU_I_RAM_DATA = 0x5f91 # macro -regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 # macro -ixGC_CAC_ID = 0x0000 # macro -ixGC_CAC_CNTL = 0x0001 # macro -ixGC_CAC_ACC_CP0 = 0x0010 # macro -ixGC_CAC_ACC_CP1 = 0x0011 # macro -ixGC_CAC_ACC_CP2 = 0x0012 # macro -ixGC_CAC_ACC_EA0 = 0x0013 # macro -ixGC_CAC_ACC_EA1 = 0x0014 # macro -ixGC_CAC_ACC_EA2 = 0x0015 # macro -ixGC_CAC_ACC_EA3 = 0x0016 # macro -ixGC_CAC_ACC_EA4 = 0x0017 # macro -ixGC_CAC_ACC_EA5 = 0x0018 # macro -ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0019 # macro -ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x001a # macro -ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x001b # macro -ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x001c # macro -ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x001d # macro -ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x001e # macro -ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x001f # macro -ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x0020 # macro -ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x0021 # macro -ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0022 # macro -ixGC_CAC_ACC_UTCL2_VML20 = 0x0023 # macro -ixGC_CAC_ACC_UTCL2_VML21 = 0x0024 # macro -ixGC_CAC_ACC_UTCL2_VML22 = 0x0025 # macro -ixGC_CAC_ACC_UTCL2_VML23 = 0x0026 # macro -ixGC_CAC_ACC_UTCL2_VML24 = 0x0027 # macro -ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0028 # macro -ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0029 # macro -ixGC_CAC_ACC_UTCL2_WALKER2 = 0x002a # macro -ixGC_CAC_ACC_UTCL2_WALKER3 = 0x002b # macro -ixGC_CAC_ACC_UTCL2_WALKER4 = 0x002c # macro -ixGC_CAC_ACC_GDS0 = 0x002d # macro -ixGC_CAC_ACC_GDS1 = 0x002e # macro -ixGC_CAC_ACC_GDS2 = 0x002f # macro -ixGC_CAC_ACC_GDS3 = 0x0030 # macro -ixGC_CAC_ACC_GDS4 = 0x0031 # macro -ixGC_CAC_ACC_GE0 = 0x0032 # macro -ixGC_CAC_ACC_GE1 = 0x0033 # macro -ixGC_CAC_ACC_GE2 = 0x0034 # macro -ixGC_CAC_ACC_GE3 = 0x0035 # macro -ixGC_CAC_ACC_GE4 = 0x0036 # macro -ixGC_CAC_ACC_GE5 = 0x0037 # macro -ixGC_CAC_ACC_GE6 = 0x0038 # macro -ixGC_CAC_ACC_GE7 = 0x0039 # macro -ixGC_CAC_ACC_GE8 = 0x003a # macro -ixGC_CAC_ACC_GE9 = 0x003b # macro -ixGC_CAC_ACC_GE10 = 0x003c # macro -ixGC_CAC_ACC_GE11 = 0x003d # macro -ixGC_CAC_ACC_GE12 = 0x003e # macro -ixGC_CAC_ACC_GE13 = 0x003f # macro -ixGC_CAC_ACC_GE14 = 0x0040 # macro -ixGC_CAC_ACC_GE15 = 0x0041 # macro -ixGC_CAC_ACC_GE16 = 0x0042 # macro -ixGC_CAC_ACC_GE17 = 0x0043 # macro -ixGC_CAC_ACC_GE18 = 0x0044 # macro -ixGC_CAC_ACC_GE19 = 0x0045 # macro -ixGC_CAC_ACC_GE20 = 0x0046 # macro -ixGC_CAC_ACC_PMM0 = 0x0047 # macro -ixGC_CAC_ACC_GL2C0 = 0x0048 # macro -ixGC_CAC_ACC_GL2C1 = 0x0049 # macro -ixGC_CAC_ACC_GL2C2 = 0x004a # macro -ixGC_CAC_ACC_GL2C3 = 0x004b # macro -ixGC_CAC_ACC_GL2C4 = 0x004c # macro -ixGC_CAC_ACC_PH0 = 0x004d # macro -ixGC_CAC_ACC_PH1 = 0x004e # macro -ixGC_CAC_ACC_PH2 = 0x004f # macro -ixGC_CAC_ACC_PH3 = 0x0050 # macro -ixGC_CAC_ACC_PH4 = 0x0051 # macro -ixGC_CAC_ACC_PH5 = 0x0052 # macro -ixGC_CAC_ACC_PH6 = 0x0053 # macro -ixGC_CAC_ACC_PH7 = 0x0054 # macro -ixGC_CAC_ACC_SDMA0 = 0x0055 # macro -ixGC_CAC_ACC_SDMA1 = 0x0056 # macro -ixGC_CAC_ACC_SDMA2 = 0x0057 # macro -ixGC_CAC_ACC_SDMA3 = 0x0058 # macro -ixGC_CAC_ACC_SDMA4 = 0x0059 # macro -ixGC_CAC_ACC_SDMA5 = 0x005a # macro -ixGC_CAC_ACC_SDMA6 = 0x005b # macro -ixGC_CAC_ACC_SDMA7 = 0x005c # macro -ixGC_CAC_ACC_SDMA8 = 0x005d # macro -ixGC_CAC_ACC_SDMA9 = 0x005e # macro -ixGC_CAC_ACC_SDMA10 = 0x005f # macro -ixGC_CAC_ACC_SDMA11 = 0x0060 # macro -ixGC_CAC_ACC_CHC0 = 0x0061 # macro -ixGC_CAC_ACC_CHC1 = 0x0062 # macro -ixGC_CAC_ACC_CHC2 = 0x0063 # macro -ixGC_CAC_ACC_GUS0 = 0x0064 # macro -ixGC_CAC_ACC_GUS1 = 0x0065 # macro -ixGC_CAC_ACC_GUS2 = 0x0066 # macro -ixGC_CAC_ACC_RLC0 = 0x0067 # macro -ixRELEASE_TO_STALL_LUT_1_8 = 0x0100 # macro -ixRELEASE_TO_STALL_LUT_9_16 = 0x0101 # macro -ixRELEASE_TO_STALL_LUT_17_20 = 0x0102 # macro -ixSTALL_TO_RELEASE_LUT_1_4 = 0x0103 # macro -ixSTALL_TO_RELEASE_LUT_5_7 = 0x0104 # macro -ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0105 # macro -ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0106 # macro -ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0107 # macro -ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0108 # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0109 # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x010a # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x010b # macro -ixFIXED_PATTERN_PERF_COUNTER_1 = 0x010c # macro -ixFIXED_PATTERN_PERF_COUNTER_2 = 0x010d # macro -ixFIXED_PATTERN_PERF_COUNTER_3 = 0x010e # macro -ixFIXED_PATTERN_PERF_COUNTER_4 = 0x010f # macro -ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0110 # macro -ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0111 # macro -ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0112 # macro -ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0113 # macro -ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0114 # macro -ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0115 # macro -ixHW_LUT_UPDATE_STATUS = 0x0116 # macro -ixSE_CAC_ID = 0x0000 # macro -ixSE_CAC_CNTL = 0x0001 # macro -ixRTAVFS_REG0 = 0x0000 # macro -ixRTAVFS_REG1 = 0x0001 # macro -ixRTAVFS_REG2 = 0x0002 # macro -ixRTAVFS_REG3 = 0x0003 # macro -ixRTAVFS_REG4 = 0x0004 # macro -ixRTAVFS_REG5 = 0x0005 # macro -ixRTAVFS_REG6 = 0x0006 # macro -ixRTAVFS_REG7 = 0x0007 # macro -ixRTAVFS_REG8 = 0x0008 # macro -ixRTAVFS_REG9 = 0x0009 # macro -ixRTAVFS_REG10 = 0x000a # macro -ixRTAVFS_REG11 = 0x000b # macro -ixRTAVFS_REG12 = 0x000c # macro -ixRTAVFS_REG13 = 0x000d # macro -ixRTAVFS_REG14 = 0x000e # macro -ixRTAVFS_REG15 = 0x000f # macro -ixRTAVFS_REG16 = 0x0010 # macro -ixRTAVFS_REG17 = 0x0011 # macro -ixRTAVFS_REG18 = 0x0012 # macro -ixRTAVFS_REG19 = 0x0013 # macro -ixRTAVFS_REG20 = 0x0014 # macro -ixRTAVFS_REG21 = 0x0015 # macro -ixRTAVFS_REG22 = 0x0016 # macro -ixRTAVFS_REG23 = 0x0017 # macro -ixRTAVFS_REG24 = 0x0018 # macro -ixRTAVFS_REG25 = 0x0019 # macro -ixRTAVFS_REG26 = 0x001a # macro -ixRTAVFS_REG27 = 0x001b # macro -ixRTAVFS_REG28 = 0x001c # macro -ixRTAVFS_REG29 = 0x001d # macro -ixRTAVFS_REG30 = 0x001e # macro -ixRTAVFS_REG31 = 0x001f # macro -ixRTAVFS_REG32 = 0x0020 # macro -ixRTAVFS_REG33 = 0x0021 # macro -ixRTAVFS_REG34 = 0x0022 # macro -ixRTAVFS_REG35 = 0x0023 # macro -ixRTAVFS_REG36 = 0x0024 # macro -ixRTAVFS_REG37 = 0x0025 # macro -ixRTAVFS_REG38 = 0x0026 # macro -ixRTAVFS_REG39 = 0x0027 # macro -ixRTAVFS_REG40 = 0x0028 # macro -ixRTAVFS_REG41 = 0x0029 # macro -ixRTAVFS_REG42 = 0x002a # macro -ixRTAVFS_REG43 = 0x002b # macro -ixRTAVFS_REG44 = 0x002c # macro -ixRTAVFS_REG45 = 0x002d # macro -ixRTAVFS_REG46 = 0x002e # macro -ixRTAVFS_REG47 = 0x002f # macro -ixRTAVFS_REG48 = 0x0030 # macro -ixRTAVFS_REG49 = 0x0031 # macro -ixRTAVFS_REG50 = 0x0032 # macro -ixRTAVFS_REG51 = 0x0033 # macro -ixRTAVFS_REG52 = 0x0034 # macro -ixRTAVFS_REG53 = 0x0035 # macro -ixRTAVFS_REG54 = 0x0036 # macro -ixRTAVFS_REG55 = 0x0037 # macro -ixRTAVFS_REG56 = 0x0038 # macro -ixRTAVFS_REG57 = 0x0039 # macro -ixRTAVFS_REG58 = 0x003a # macro -ixRTAVFS_REG59 = 0x003b # macro -ixRTAVFS_REG60 = 0x003c # macro -ixRTAVFS_REG61 = 0x003d # macro -ixRTAVFS_REG62 = 0x003e # macro -ixRTAVFS_REG63 = 0x003f # macro -ixRTAVFS_REG64 = 0x0040 # macro -ixRTAVFS_REG65 = 0x0041 # macro -ixRTAVFS_REG66 = 0x0042 # macro -ixRTAVFS_REG67 = 0x0043 # macro -ixRTAVFS_REG68 = 0x0044 # macro -ixRTAVFS_REG69 = 0x0045 # macro -ixRTAVFS_REG70 = 0x0046 # macro -ixRTAVFS_REG71 = 0x0047 # macro -ixRTAVFS_REG72 = 0x0048 # macro -ixRTAVFS_REG73 = 0x0049 # macro -ixRTAVFS_REG74 = 0x004a # macro -ixRTAVFS_REG75 = 0x004b # macro -ixRTAVFS_REG76 = 0x004c # macro -ixRTAVFS_REG77 = 0x004d # macro -ixRTAVFS_REG78 = 0x004e # macro -ixRTAVFS_REG79 = 0x004f # macro -ixRTAVFS_REG80 = 0x0050 # macro -ixRTAVFS_REG81 = 0x0051 # macro -ixRTAVFS_REG82 = 0x0052 # macro -ixRTAVFS_REG83 = 0x0053 # macro -ixRTAVFS_REG84 = 0x0054 # macro -ixRTAVFS_REG85 = 0x0055 # macro -ixRTAVFS_REG86 = 0x0056 # macro -ixRTAVFS_REG87 = 0x0057 # macro -ixRTAVFS_REG88 = 0x0058 # macro -ixRTAVFS_REG89 = 0x0059 # macro -ixRTAVFS_REG90 = 0x005a # macro -ixRTAVFS_REG91 = 0x005b # macro -ixRTAVFS_REG92 = 0x005c # macro -ixRTAVFS_REG93 = 0x005d # macro -ixRTAVFS_REG94 = 0x005e # macro -ixRTAVFS_REG95 = 0x005f # macro -ixRTAVFS_REG96 = 0x0060 # macro -ixRTAVFS_REG97 = 0x0061 # macro -ixRTAVFS_REG98 = 0x0062 # macro -ixRTAVFS_REG99 = 0x0063 # macro -ixRTAVFS_REG100 = 0x0064 # macro -ixRTAVFS_REG101 = 0x0065 # macro -ixRTAVFS_REG102 = 0x0066 # macro -ixRTAVFS_REG103 = 0x0067 # macro -ixRTAVFS_REG104 = 0x0068 # macro -ixRTAVFS_REG105 = 0x0069 # macro -ixRTAVFS_REG106 = 0x006a # macro -ixRTAVFS_REG107 = 0x006b # macro -ixRTAVFS_REG108 = 0x006c # macro -ixRTAVFS_REG109 = 0x006d # macro -ixRTAVFS_REG110 = 0x006e # macro -ixRTAVFS_REG111 = 0x006f # macro -ixRTAVFS_REG112 = 0x0070 # macro -ixRTAVFS_REG113 = 0x0071 # macro -ixRTAVFS_REG114 = 0x0072 # macro -ixRTAVFS_REG115 = 0x0073 # macro -ixRTAVFS_REG116 = 0x0074 # macro -ixRTAVFS_REG117 = 0x0075 # macro -ixRTAVFS_REG118 = 0x0076 # macro -ixRTAVFS_REG119 = 0x0077 # macro -ixRTAVFS_REG120 = 0x0078 # macro -ixRTAVFS_REG121 = 0x0079 # macro -ixRTAVFS_REG122 = 0x007a # macro -ixRTAVFS_REG123 = 0x007b # macro -ixRTAVFS_REG124 = 0x007c # macro -ixRTAVFS_REG125 = 0x007d # macro -ixRTAVFS_REG126 = 0x007e # macro -ixRTAVFS_REG127 = 0x007f # macro -ixRTAVFS_REG128 = 0x0080 # macro -ixRTAVFS_REG129 = 0x0081 # macro -ixRTAVFS_REG130 = 0x0082 # macro -ixRTAVFS_REG131 = 0x0083 # macro -ixRTAVFS_REG132 = 0x0084 # macro -ixRTAVFS_REG133 = 0x0085 # macro -ixRTAVFS_REG134 = 0x0086 # macro -ixRTAVFS_REG135 = 0x0087 # macro -ixRTAVFS_REG136 = 0x0088 # macro -ixRTAVFS_REG137 = 0x0089 # macro -ixRTAVFS_REG138 = 0x008a # macro -ixRTAVFS_REG139 = 0x008b # macro -ixRTAVFS_REG140 = 0x008c # macro -ixRTAVFS_REG141 = 0x008d # macro -ixRTAVFS_REG142 = 0x008e # macro -ixRTAVFS_REG143 = 0x008f # macro -ixRTAVFS_REG144 = 0x0090 # macro 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= 0x00DC0000 # macro -MP0_BASE__INST0_SEG2 = 0x00E00000 # macro -MP0_BASE__INST0_SEG3 = 0x00E40000 # macro -MP0_BASE__INST0_SEG4 = 0x0243FC00 # macro -MP0_BASE__INST1_SEG0 = 0 # macro -MP0_BASE__INST1_SEG1 = 0 # macro -MP0_BASE__INST1_SEG2 = 0 # macro -MP0_BASE__INST1_SEG3 = 0 # macro -MP0_BASE__INST1_SEG4 = 0 # macro -MP0_BASE__INST2_SEG0 = 0 # macro -MP0_BASE__INST2_SEG1 = 0 # macro -MP0_BASE__INST2_SEG2 = 0 # macro -MP0_BASE__INST2_SEG3 = 0 # macro -MP0_BASE__INST2_SEG4 = 0 # macro -MP0_BASE__INST3_SEG0 = 0 # macro -MP0_BASE__INST3_SEG1 = 0 # macro -MP0_BASE__INST3_SEG2 = 0 # macro -MP0_BASE__INST3_SEG3 = 0 # macro -MP0_BASE__INST3_SEG4 = 0 # macro -MP0_BASE__INST4_SEG0 = 0 # macro -MP0_BASE__INST4_SEG1 = 0 # macro -MP0_BASE__INST4_SEG2 = 0 # macro -MP0_BASE__INST4_SEG3 = 0 # macro -MP0_BASE__INST4_SEG4 = 0 # macro -MP0_BASE__INST5_SEG0 = 0 # macro -MP0_BASE__INST5_SEG1 = 0 # macro -MP0_BASE__INST5_SEG2 = 0 # macro -MP0_BASE__INST5_SEG3 = 0 # macro -MP0_BASE__INST5_SEG4 = 0 # macro -MP0_BASE__INST6_SEG0 = 0 # macro -MP0_BASE__INST6_SEG1 = 0 # macro -MP0_BASE__INST6_SEG2 = 0 # macro -MP0_BASE__INST6_SEG3 = 0 # macro -MP0_BASE__INST6_SEG4 = 0 # macro -MP1_BASE__INST0_SEG0 = 0x00016000 # macro -MP1_BASE__INST0_SEG1 = 0x00DC0000 # macro -MP1_BASE__INST0_SEG2 = 0x00E00000 # macro -MP1_BASE__INST0_SEG3 = 0x00E40000 # macro -MP1_BASE__INST0_SEG4 = 0x0243FC00 # macro -MP1_BASE__INST1_SEG0 = 0 # macro -MP1_BASE__INST1_SEG1 = 0 # macro -MP1_BASE__INST1_SEG2 = 0 # macro -MP1_BASE__INST1_SEG3 = 0 # macro -MP1_BASE__INST1_SEG4 = 0 # macro -MP1_BASE__INST2_SEG0 = 0 # macro -MP1_BASE__INST2_SEG1 = 0 # macro -MP1_BASE__INST2_SEG2 = 0 # macro -MP1_BASE__INST2_SEG3 = 0 # macro -MP1_BASE__INST2_SEG4 = 0 # macro -MP1_BASE__INST3_SEG0 = 0 # macro -MP1_BASE__INST3_SEG1 = 0 # macro -MP1_BASE__INST3_SEG2 = 0 # macro -MP1_BASE__INST3_SEG3 = 0 # macro -MP1_BASE__INST3_SEG4 = 0 # macro -MP1_BASE__INST4_SEG0 = 0 # macro -MP1_BASE__INST4_SEG1 = 0 # macro -MP1_BASE__INST4_SEG2 = 0 # macro -MP1_BASE__INST4_SEG3 = 0 # macro -MP1_BASE__INST4_SEG4 = 0 # macro -MP1_BASE__INST5_SEG0 = 0 # macro -MP1_BASE__INST5_SEG1 = 0 # macro -MP1_BASE__INST5_SEG2 = 0 # macro -MP1_BASE__INST5_SEG3 = 0 # macro -MP1_BASE__INST5_SEG4 = 0 # macro -MP1_BASE__INST6_SEG0 = 0 # macro -MP1_BASE__INST6_SEG1 = 0 # macro -MP1_BASE__INST6_SEG2 = 0 # macro -MP1_BASE__INST6_SEG3 = 0 # macro -MP1_BASE__INST6_SEG4 = 0 # macro -NBIO_BASE__INST0_SEG0 = 0x00000000 # macro -NBIO_BASE__INST0_SEG1 = 0x00000014 # macro -NBIO_BASE__INST0_SEG2 = 0x00000D20 # macro -NBIO_BASE__INST0_SEG3 = 0x00010400 # macro -NBIO_BASE__INST0_SEG4 = 0x0241B000 # macro -NBIO_BASE__INST1_SEG0 = 0 # macro -NBIO_BASE__INST1_SEG1 = 0 # macro -NBIO_BASE__INST1_SEG2 = 0 # macro -NBIO_BASE__INST1_SEG3 = 0 # macro -NBIO_BASE__INST1_SEG4 = 0 # macro -NBIO_BASE__INST2_SEG0 = 0 # macro -NBIO_BASE__INST2_SEG1 = 0 # macro -NBIO_BASE__INST2_SEG2 = 0 # macro -NBIO_BASE__INST2_SEG3 = 0 # macro -NBIO_BASE__INST2_SEG4 = 0 # macro -NBIO_BASE__INST3_SEG0 = 0 # macro -NBIO_BASE__INST3_SEG1 = 0 # macro -NBIO_BASE__INST3_SEG2 = 0 # macro -NBIO_BASE__INST3_SEG3 = 0 # macro -NBIO_BASE__INST3_SEG4 = 0 # macro -NBIO_BASE__INST4_SEG0 = 0 # macro -NBIO_BASE__INST4_SEG1 = 0 # macro -NBIO_BASE__INST4_SEG2 = 0 # macro -NBIO_BASE__INST4_SEG3 = 0 # macro -NBIO_BASE__INST4_SEG4 = 0 # macro -NBIO_BASE__INST5_SEG0 = 0 # macro -NBIO_BASE__INST5_SEG1 = 0 # macro -NBIO_BASE__INST5_SEG2 = 0 # macro -NBIO_BASE__INST5_SEG3 = 0 # macro -NBIO_BASE__INST5_SEG4 = 0 # macro -NBIO_BASE__INST6_SEG0 = 0 # macro -NBIO_BASE__INST6_SEG1 = 0 # macro -NBIO_BASE__INST6_SEG2 = 0 # macro -NBIO_BASE__INST6_SEG3 = 0 # macro -NBIO_BASE__INST6_SEG4 = 0 # macro -OSSSYS_BASE__INST0_SEG0 = 0x000010A0 # macro -OSSSYS_BASE__INST0_SEG1 = 0x0240A000 # macro -OSSSYS_BASE__INST0_SEG2 = 0 # macro -OSSSYS_BASE__INST0_SEG3 = 0 # macro -OSSSYS_BASE__INST0_SEG4 = 0 # macro -OSSSYS_BASE__INST1_SEG0 = 0 # macro -OSSSYS_BASE__INST1_SEG1 = 0 # macro -OSSSYS_BASE__INST1_SEG2 = 0 # macro -OSSSYS_BASE__INST1_SEG3 = 0 # macro -OSSSYS_BASE__INST1_SEG4 = 0 # macro -OSSSYS_BASE__INST2_SEG0 = 0 # macro -OSSSYS_BASE__INST2_SEG1 = 0 # macro -OSSSYS_BASE__INST2_SEG2 = 0 # macro -OSSSYS_BASE__INST2_SEG3 = 0 # macro -OSSSYS_BASE__INST2_SEG4 = 0 # macro -OSSSYS_BASE__INST3_SEG0 = 0 # macro -OSSSYS_BASE__INST3_SEG1 = 0 # macro -OSSSYS_BASE__INST3_SEG2 = 0 # macro -OSSSYS_BASE__INST3_SEG3 = 0 # macro -OSSSYS_BASE__INST3_SEG4 = 0 # macro -OSSSYS_BASE__INST4_SEG0 = 0 # macro -OSSSYS_BASE__INST4_SEG1 = 0 # macro -OSSSYS_BASE__INST4_SEG2 = 0 # macro -OSSSYS_BASE__INST4_SEG3 = 0 # macro -OSSSYS_BASE__INST4_SEG4 = 0 # macro -OSSSYS_BASE__INST5_SEG0 = 0 # macro -OSSSYS_BASE__INST5_SEG1 = 0 # macro -OSSSYS_BASE__INST5_SEG2 = 0 # macro -OSSSYS_BASE__INST5_SEG3 = 0 # macro -OSSSYS_BASE__INST5_SEG4 = 0 # macro -OSSSYS_BASE__INST6_SEG0 = 0 # macro -OSSSYS_BASE__INST6_SEG1 = 0 # macro -OSSSYS_BASE__INST6_SEG2 = 0 # macro -OSSSYS_BASE__INST6_SEG3 = 0 # macro -OSSSYS_BASE__INST6_SEG4 = 0 # macro -PCIE0_BASE__INST0_SEG0 = 0x00000000 # macro -PCIE0_BASE__INST0_SEG1 = 0x00000014 # macro -PCIE0_BASE__INST0_SEG2 = 0x00000D20 # macro -PCIE0_BASE__INST0_SEG3 = 0x00010400 # macro -PCIE0_BASE__INST0_SEG4 = 0x0241B000 # macro -PCIE0_BASE__INST1_SEG0 = 0 # macro -PCIE0_BASE__INST1_SEG1 = 0 # macro -PCIE0_BASE__INST1_SEG2 = 0 # macro -PCIE0_BASE__INST1_SEG3 = 0 # macro -PCIE0_BASE__INST1_SEG4 = 0 # macro -PCIE0_BASE__INST2_SEG0 = 0 # macro -PCIE0_BASE__INST2_SEG1 = 0 # macro -PCIE0_BASE__INST2_SEG2 = 0 # macro -PCIE0_BASE__INST2_SEG3 = 0 # macro -PCIE0_BASE__INST2_SEG4 = 0 # macro -PCIE0_BASE__INST3_SEG0 = 0 # macro -PCIE0_BASE__INST3_SEG1 = 0 # macro -PCIE0_BASE__INST3_SEG2 = 0 # macro -PCIE0_BASE__INST3_SEG3 = 0 # macro -PCIE0_BASE__INST3_SEG4 = 0 # macro -PCIE0_BASE__INST4_SEG0 = 0 # macro -PCIE0_BASE__INST4_SEG1 = 0 # macro -PCIE0_BASE__INST4_SEG2 = 0 # macro -PCIE0_BASE__INST4_SEG3 = 0 # macro -PCIE0_BASE__INST4_SEG4 = 0 # macro -PCIE0_BASE__INST5_SEG0 = 0 # macro -PCIE0_BASE__INST5_SEG1 = 0 # macro -PCIE0_BASE__INST5_SEG2 = 0 # macro -PCIE0_BASE__INST5_SEG3 = 0 # macro -PCIE0_BASE__INST5_SEG4 = 0 # macro -PCIE0_BASE__INST6_SEG0 = 0 # macro -PCIE0_BASE__INST6_SEG1 = 0 # macro -PCIE0_BASE__INST6_SEG2 = 0 # macro -PCIE0_BASE__INST6_SEG3 = 0 # macro -PCIE0_BASE__INST6_SEG4 = 0 # macro -SDMA0_BASE__INST0_SEG0 = 0x00001260 # macro -SDMA0_BASE__INST0_SEG1 = 0x0000A000 # macro -SDMA0_BASE__INST0_SEG2 = 0x0001C000 # macro -SDMA0_BASE__INST0_SEG3 = 0x02402C00 # macro -SDMA0_BASE__INST0_SEG4 = 0 # macro -SDMA0_BASE__INST1_SEG0 = 0 # macro -SDMA0_BASE__INST1_SEG1 = 0 # macro -SDMA0_BASE__INST1_SEG2 = 0 # macro -SDMA0_BASE__INST1_SEG3 = 0 # macro -SDMA0_BASE__INST1_SEG4 = 0 # macro -SDMA0_BASE__INST2_SEG0 = 0 # macro -SDMA0_BASE__INST2_SEG1 = 0 # macro -SDMA0_BASE__INST2_SEG2 = 0 # macro -SDMA0_BASE__INST2_SEG3 = 0 # macro -SDMA0_BASE__INST2_SEG4 = 0 # macro -SDMA0_BASE__INST3_SEG0 = 0 # macro -SDMA0_BASE__INST3_SEG1 = 0 # macro -SDMA0_BASE__INST3_SEG2 = 0 # macro -SDMA0_BASE__INST3_SEG3 = 0 # macro -SDMA0_BASE__INST3_SEG4 = 0 # macro -SDMA0_BASE__INST4_SEG0 = 0 # macro -SDMA0_BASE__INST4_SEG1 = 0 # macro -SDMA0_BASE__INST4_SEG2 = 0 # macro -SDMA0_BASE__INST4_SEG3 = 0 # macro -SDMA0_BASE__INST4_SEG4 = 0 # macro -SDMA0_BASE__INST5_SEG0 = 0 # macro -SDMA0_BASE__INST5_SEG1 = 0 # macro -SDMA0_BASE__INST5_SEG2 = 0 # macro -SDMA0_BASE__INST5_SEG3 = 0 # macro -SDMA0_BASE__INST5_SEG4 = 0 # macro -SDMA0_BASE__INST6_SEG0 = 0 # macro -SDMA0_BASE__INST6_SEG1 = 0 # macro -SDMA0_BASE__INST6_SEG2 = 0 # macro -SDMA0_BASE__INST6_SEG3 = 0 # macro -SDMA0_BASE__INST6_SEG4 = 0 # macro -SDMA1_BASE__INST0_SEG0 = 0x00001260 # macro -SDMA1_BASE__INST0_SEG1 = 0x0000A000 # macro -SDMA1_BASE__INST0_SEG2 = 0x0001C000 # macro -SDMA1_BASE__INST0_SEG3 = 0x02402C00 # macro -SDMA1_BASE__INST0_SEG4 = 0 # macro -SDMA1_BASE__INST1_SEG0 = 0 # macro -SDMA1_BASE__INST1_SEG1 = 0 # macro -SDMA1_BASE__INST1_SEG2 = 0 # macro -SDMA1_BASE__INST1_SEG3 = 0 # macro -SDMA1_BASE__INST1_SEG4 = 0 # macro -SDMA1_BASE__INST2_SEG0 = 0 # macro -SDMA1_BASE__INST2_SEG1 = 0 # macro -SDMA1_BASE__INST2_SEG2 = 0 # macro -SDMA1_BASE__INST2_SEG3 = 0 # macro -SDMA1_BASE__INST2_SEG4 = 0 # macro -SDMA1_BASE__INST3_SEG0 = 0 # macro -SDMA1_BASE__INST3_SEG1 = 0 # macro -SDMA1_BASE__INST3_SEG2 = 0 # macro -SDMA1_BASE__INST3_SEG3 = 0 # macro -SDMA1_BASE__INST3_SEG4 = 0 # macro -SDMA1_BASE__INST4_SEG0 = 0 # macro -SDMA1_BASE__INST4_SEG1 = 0 # macro -SDMA1_BASE__INST4_SEG2 = 0 # macro -SDMA1_BASE__INST4_SEG3 = 0 # macro -SDMA1_BASE__INST4_SEG4 = 0 # macro -SDMA1_BASE__INST5_SEG0 = 0 # macro -SDMA1_BASE__INST5_SEG1 = 0 # macro -SDMA1_BASE__INST5_SEG2 = 0 # macro -SDMA1_BASE__INST5_SEG3 = 0 # macro -SDMA1_BASE__INST5_SEG4 = 0 # macro -SDMA1_BASE__INST6_SEG0 = 0 # macro -SDMA1_BASE__INST6_SEG1 = 0 # macro -SDMA1_BASE__INST6_SEG2 = 0 # macro -SDMA1_BASE__INST6_SEG3 = 0 # macro -SDMA1_BASE__INST6_SEG4 = 0 # macro -SMUIO_BASE__INST0_SEG0 = 0x00016800 # macro -SMUIO_BASE__INST0_SEG1 = 0x00016A00 # macro -SMUIO_BASE__INST0_SEG2 = 0x00440000 # macro -SMUIO_BASE__INST0_SEG3 = 0x02401000 # macro -SMUIO_BASE__INST0_SEG4 = 0 # macro -SMUIO_BASE__INST1_SEG0 = 0 # macro -SMUIO_BASE__INST1_SEG1 = 0 # macro -SMUIO_BASE__INST1_SEG2 = 0 # macro -SMUIO_BASE__INST1_SEG3 = 0 # macro -SMUIO_BASE__INST1_SEG4 = 0 # macro -SMUIO_BASE__INST2_SEG0 = 0 # macro -SMUIO_BASE__INST2_SEG1 = 0 # macro -SMUIO_BASE__INST2_SEG2 = 0 # macro -SMUIO_BASE__INST2_SEG3 = 0 # macro -SMUIO_BASE__INST2_SEG4 = 0 # macro -SMUIO_BASE__INST3_SEG0 = 0 # macro -SMUIO_BASE__INST3_SEG1 = 0 # macro -SMUIO_BASE__INST3_SEG2 = 0 # macro -SMUIO_BASE__INST3_SEG3 = 0 # macro -SMUIO_BASE__INST3_SEG4 = 0 # macro -SMUIO_BASE__INST4_SEG0 = 0 # macro -SMUIO_BASE__INST4_SEG1 = 0 # macro -SMUIO_BASE__INST4_SEG2 = 0 # macro -SMUIO_BASE__INST4_SEG3 = 0 # macro -SMUIO_BASE__INST4_SEG4 = 0 # macro -SMUIO_BASE__INST5_SEG0 = 0 # macro -SMUIO_BASE__INST5_SEG1 = 0 # macro -SMUIO_BASE__INST5_SEG2 = 0 # macro -SMUIO_BASE__INST5_SEG3 = 0 # macro -SMUIO_BASE__INST5_SEG4 = 0 # macro -SMUIO_BASE__INST6_SEG0 = 0 # macro -SMUIO_BASE__INST6_SEG1 = 0 # macro -SMUIO_BASE__INST6_SEG2 = 0 # macro -SMUIO_BASE__INST6_SEG3 = 0 # macro -SMUIO_BASE__INST6_SEG4 = 0 # macro -THM_BASE__INST0_SEG0 = 0x00016600 # macro -THM_BASE__INST0_SEG1 = 0x02400C00 # macro -THM_BASE__INST0_SEG2 = 0 # macro -THM_BASE__INST0_SEG3 = 0 # macro -THM_BASE__INST0_SEG4 = 0 # macro -THM_BASE__INST1_SEG0 = 0 # macro -THM_BASE__INST1_SEG1 = 0 # macro -THM_BASE__INST1_SEG2 = 0 # macro -THM_BASE__INST1_SEG3 = 0 # macro -THM_BASE__INST1_SEG4 = 0 # macro -THM_BASE__INST2_SEG0 = 0 # macro -THM_BASE__INST2_SEG1 = 0 # macro -THM_BASE__INST2_SEG2 = 0 # macro -THM_BASE__INST2_SEG3 = 0 # macro -THM_BASE__INST2_SEG4 = 0 # macro -THM_BASE__INST3_SEG0 = 0 # macro -THM_BASE__INST3_SEG1 = 0 # macro -THM_BASE__INST3_SEG2 = 0 # macro -THM_BASE__INST3_SEG3 = 0 # macro -THM_BASE__INST3_SEG4 = 0 # macro -THM_BASE__INST4_SEG0 = 0 # macro -THM_BASE__INST4_SEG1 = 0 # macro -THM_BASE__INST4_SEG2 = 0 # macro -THM_BASE__INST4_SEG3 = 0 # macro -THM_BASE__INST4_SEG4 = 0 # macro -THM_BASE__INST5_SEG0 = 0 # macro -THM_BASE__INST5_SEG1 = 0 # macro -THM_BASE__INST5_SEG2 = 0 # macro -THM_BASE__INST5_SEG3 = 0 # macro -THM_BASE__INST5_SEG4 = 0 # macro -THM_BASE__INST6_SEG0 = 0 # macro -THM_BASE__INST6_SEG1 = 0 # macro -THM_BASE__INST6_SEG2 = 0 # macro -THM_BASE__INST6_SEG3 = 0 # macro -THM_BASE__INST6_SEG4 = 0 # macro -UMC_BASE__INST0_SEG0 = 0x00014000 # macro -UMC_BASE__INST0_SEG1 = 0x02425800 # macro -UMC_BASE__INST0_SEG2 = 0 # macro -UMC_BASE__INST0_SEG3 = 0 # macro -UMC_BASE__INST0_SEG4 = 0 # macro -UMC_BASE__INST1_SEG0 = 0x00054000 # macro -UMC_BASE__INST1_SEG1 = 0x02425C00 # macro -UMC_BASE__INST1_SEG2 = 0 # macro -UMC_BASE__INST1_SEG3 = 0 # macro -UMC_BASE__INST1_SEG4 = 0 # macro -UMC_BASE__INST2_SEG0 = 0x00094000 # macro -UMC_BASE__INST2_SEG1 = 0x02426000 # macro -UMC_BASE__INST2_SEG2 = 0 # macro -UMC_BASE__INST2_SEG3 = 0 # macro -UMC_BASE__INST2_SEG4 = 0 # macro -UMC_BASE__INST3_SEG0 = 0x000D4000 # macro -UMC_BASE__INST3_SEG1 = 0x02426400 # macro -UMC_BASE__INST3_SEG2 = 0 # macro -UMC_BASE__INST3_SEG3 = 0 # macro -UMC_BASE__INST3_SEG4 = 0 # macro -UMC_BASE__INST4_SEG0 = 0x00114000 # macro -UMC_BASE__INST4_SEG1 = 0x02426800 # macro -UMC_BASE__INST4_SEG2 = 0 # macro -UMC_BASE__INST4_SEG3 = 0 # macro -UMC_BASE__INST4_SEG4 = 0 # macro -UMC_BASE__INST5_SEG0 = 0x00154000 # macro -UMC_BASE__INST5_SEG1 = 0x02426C00 # macro -UMC_BASE__INST5_SEG2 = 0 # macro -UMC_BASE__INST5_SEG3 = 0 # macro -UMC_BASE__INST5_SEG4 = 0 # macro -UMC_BASE__INST6_SEG0 = 0x00194000 # macro -UMC_BASE__INST6_SEG1 = 0x02427000 # macro -UMC_BASE__INST6_SEG2 = 0 # macro -UMC_BASE__INST6_SEG3 = 0 # macro -UMC_BASE__INST6_SEG4 = 0 # macro -USB0_BASE__INST0_SEG0 = 0x0242A800 # macro -USB0_BASE__INST0_SEG1 = 0x05B00000 # macro -USB0_BASE__INST0_SEG2 = 0 # macro -USB0_BASE__INST0_SEG3 = 0 # macro -USB0_BASE__INST0_SEG4 = 0 # macro -USB0_BASE__INST1_SEG0 = 0 # macro -USB0_BASE__INST1_SEG1 = 0 # macro -USB0_BASE__INST1_SEG2 = 0 # macro -USB0_BASE__INST1_SEG3 = 0 # macro -USB0_BASE__INST1_SEG4 = 0 # macro -USB0_BASE__INST2_SEG0 = 0 # macro -USB0_BASE__INST2_SEG1 = 0 # macro -USB0_BASE__INST2_SEG2 = 0 # macro -USB0_BASE__INST2_SEG3 = 0 # macro -USB0_BASE__INST2_SEG4 = 0 # macro -USB0_BASE__INST3_SEG0 = 0 # macro -USB0_BASE__INST3_SEG1 = 0 # macro -USB0_BASE__INST3_SEG2 = 0 # macro -USB0_BASE__INST3_SEG3 = 0 # macro -USB0_BASE__INST3_SEG4 = 0 # macro -USB0_BASE__INST4_SEG0 = 0 # macro -USB0_BASE__INST4_SEG1 = 0 # macro -USB0_BASE__INST4_SEG2 = 0 # macro -USB0_BASE__INST4_SEG3 = 0 # macro -USB0_BASE__INST4_SEG4 = 0 # macro -USB0_BASE__INST5_SEG0 = 0 # macro -USB0_BASE__INST5_SEG1 = 0 # macro -USB0_BASE__INST5_SEG2 = 0 # macro -USB0_BASE__INST5_SEG3 = 0 # macro -USB0_BASE__INST5_SEG4 = 0 # macro -USB0_BASE__INST6_SEG0 = 0 # macro -USB0_BASE__INST6_SEG1 = 0 # macro -USB0_BASE__INST6_SEG2 = 0 # macro -USB0_BASE__INST6_SEG3 = 0 # macro -USB0_BASE__INST6_SEG4 = 0 # macro -VCN_BASE__INST0_SEG0 = 0x00007800 # macro -VCN_BASE__INST0_SEG1 = 0x00007E00 # macro -VCN_BASE__INST0_SEG2 = 0x02403000 # macro -VCN_BASE__INST0_SEG3 = 0 # macro -VCN_BASE__INST0_SEG4 = 0 # macro -VCN_BASE__INST1_SEG0 = 0x00007B00 # macro -VCN_BASE__INST1_SEG1 = 0x00012000 # macro -VCN_BASE__INST1_SEG2 = 0x02445000 # macro -VCN_BASE__INST1_SEG3 = 0 # macro -VCN_BASE__INST1_SEG4 = 0 # macro -VCN_BASE__INST2_SEG0 = 0 # macro -VCN_BASE__INST2_SEG1 = 0 # macro -VCN_BASE__INST2_SEG2 = 0 # macro -VCN_BASE__INST2_SEG3 = 0 # macro -VCN_BASE__INST2_SEG4 = 0 # macro -VCN_BASE__INST3_SEG0 = 0 # macro -VCN_BASE__INST3_SEG1 = 0 # macro -VCN_BASE__INST3_SEG2 = 0 # macro -VCN_BASE__INST3_SEG3 = 0 # macro -VCN_BASE__INST3_SEG4 = 0 # macro -VCN_BASE__INST4_SEG0 = 0 # macro -VCN_BASE__INST4_SEG1 = 0 # macro -VCN_BASE__INST4_SEG2 = 0 # macro -VCN_BASE__INST4_SEG3 = 0 # macro -VCN_BASE__INST4_SEG4 = 0 # macro -VCN_BASE__INST5_SEG0 = 0 # macro -VCN_BASE__INST5_SEG1 = 0 # macro -VCN_BASE__INST5_SEG2 = 0 # macro -VCN_BASE__INST5_SEG3 = 0 # macro -VCN_BASE__INST5_SEG4 = 0 # macro -VCN_BASE__INST6_SEG0 = 0 # macro -VCN_BASE__INST6_SEG1 = 0 # macro -VCN_BASE__INST6_SEG2 = 0 # macro -VCN_BASE__INST6_SEG3 = 0 # macro -VCN_BASE__INST6_SEG4 = 0 # macro -class struct_IP_BASE_INSTANCE(Structure): - pass - -struct_IP_BASE_INSTANCE._pack_ = 1 # source:False -struct_IP_BASE_INSTANCE._fields_ = [ - ('segment', ctypes.c_uint32 * 5), +rocr_AMD_SDMA_PKT_GCR = rocr_AMD_SDMA_PKT_GCR_TAG +class IP_BASE_INSTANCE(Struct): pass +IP_BASE_INSTANCE._fields_ = [ + ('segment', (ctypes.c_uint32 * 5)), ] - -class struct_IP_BASE(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('instance', struct_IP_BASE_INSTANCE * 7), - ] - -__maybe_unused = struct_IP_BASE # Variable struct_IP_BASE -ATHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE -CLK_BASE = struct_IP_BASE # Variable struct_IP_BASE -DF_BASE = struct_IP_BASE # Variable struct_IP_BASE -DIO_BASE = struct_IP_BASE # Variable struct_IP_BASE -DCN_BASE = struct_IP_BASE # Variable struct_IP_BASE -DPCS_BASE = struct_IP_BASE # Variable struct_IP_BASE -FUSE_BASE = struct_IP_BASE # Variable struct_IP_BASE -GC_BASE = struct_IP_BASE # Variable struct_IP_BASE -HDA_BASE = struct_IP_BASE # Variable struct_IP_BASE -HDP_BASE = struct_IP_BASE # Variable struct_IP_BASE -MMHUB_BASE = struct_IP_BASE # Variable struct_IP_BASE -MP0_BASE = struct_IP_BASE # Variable struct_IP_BASE -MP1_BASE = struct_IP_BASE # Variable struct_IP_BASE -NBIO_BASE = struct_IP_BASE # Variable struct_IP_BASE -OSSSYS_BASE = struct_IP_BASE # Variable struct_IP_BASE -PCIE0_BASE = struct_IP_BASE # Variable struct_IP_BASE -SDMA0_BASE = struct_IP_BASE # Variable struct_IP_BASE -SDMA1_BASE = struct_IP_BASE # Variable struct_IP_BASE -SMUIO_BASE = struct_IP_BASE # Variable struct_IP_BASE -THM_BASE = struct_IP_BASE # Variable struct_IP_BASE -UMC_BASE = struct_IP_BASE # Variable struct_IP_BASE -USB0_BASE = struct_IP_BASE # Variable struct_IP_BASE -VCN_BASE = struct_IP_BASE # Variable struct_IP_BASE -__all__ = \ - ['ATHUB_BASE', 'ATHUB_BASE__INST0_SEG0', 'ATHUB_BASE__INST0_SEG1', - 'ATHUB_BASE__INST0_SEG2', 'ATHUB_BASE__INST0_SEG3', - 'ATHUB_BASE__INST0_SEG4', 'ATHUB_BASE__INST1_SEG0', - 'ATHUB_BASE__INST1_SEG1', 'ATHUB_BASE__INST1_SEG2', - 'ATHUB_BASE__INST1_SEG3', 'ATHUB_BASE__INST1_SEG4', - 'ATHUB_BASE__INST2_SEG0', 'ATHUB_BASE__INST2_SEG1', - 'ATHUB_BASE__INST2_SEG2', 'ATHUB_BASE__INST2_SEG3', - 'ATHUB_BASE__INST2_SEG4', 'ATHUB_BASE__INST3_SEG0', - 'ATHUB_BASE__INST3_SEG1', 'ATHUB_BASE__INST3_SEG2', - 'ATHUB_BASE__INST3_SEG3', 'ATHUB_BASE__INST3_SEG4', - 'ATHUB_BASE__INST4_SEG0', 'ATHUB_BASE__INST4_SEG1', - 'ATHUB_BASE__INST4_SEG2', 'ATHUB_BASE__INST4_SEG3', - 'ATHUB_BASE__INST4_SEG4', 'ATHUB_BASE__INST5_SEG0', - 'ATHUB_BASE__INST5_SEG1', 'ATHUB_BASE__INST5_SEG2', - 'ATHUB_BASE__INST5_SEG3', 'ATHUB_BASE__INST5_SEG4', - 'ATHUB_BASE__INST6_SEG0', 'ATHUB_BASE__INST6_SEG1', - 'ATHUB_BASE__INST6_SEG2', 'ATHUB_BASE__INST6_SEG3', - 'ATHUB_BASE__INST6_SEG4', 'CE_PARTITION_BASE', 'CLK_BASE', - 'CLK_BASE__INST0_SEG0', 'CLK_BASE__INST0_SEG1', - 'CLK_BASE__INST0_SEG2', 'CLK_BASE__INST0_SEG3', - 'CLK_BASE__INST0_SEG4', 'CLK_BASE__INST1_SEG0', - 'CLK_BASE__INST1_SEG1', 'CLK_BASE__INST1_SEG2', - 'CLK_BASE__INST1_SEG3', 'CLK_BASE__INST1_SEG4', - 'CLK_BASE__INST2_SEG0', 'CLK_BASE__INST2_SEG1', - 'CLK_BASE__INST2_SEG2', 'CLK_BASE__INST2_SEG3', - 'CLK_BASE__INST2_SEG4', 'CLK_BASE__INST3_SEG0', - 'CLK_BASE__INST3_SEG1', 'CLK_BASE__INST3_SEG2', - 'CLK_BASE__INST3_SEG3', 'CLK_BASE__INST3_SEG4', - 'CLK_BASE__INST4_SEG0', 'CLK_BASE__INST4_SEG1', - 'CLK_BASE__INST4_SEG2', 'CLK_BASE__INST4_SEG3', - 'CLK_BASE__INST4_SEG4', 'CLK_BASE__INST5_SEG0', - 'CLK_BASE__INST5_SEG1', 'CLK_BASE__INST5_SEG2', - 'CLK_BASE__INST5_SEG3', 'CLK_BASE__INST5_SEG4', - 'CLK_BASE__INST6_SEG0', 'CLK_BASE__INST6_SEG1', - 'CLK_BASE__INST6_SEG2', 'CLK_BASE__INST6_SEG3', - 'CLK_BASE__INST6_SEG4', 'CP_PACKET2', 'DCN_BASE', - 'DCN_BASE__INST0_SEG0', 'DCN_BASE__INST0_SEG1', - 'DCN_BASE__INST0_SEG2', 'DCN_BASE__INST0_SEG3', - 'DCN_BASE__INST0_SEG4', 'DCN_BASE__INST1_SEG0', - 'DCN_BASE__INST1_SEG1', 'DCN_BASE__INST1_SEG2', - 'DCN_BASE__INST1_SEG3', 'DCN_BASE__INST1_SEG4', - 'DCN_BASE__INST2_SEG0', 'DCN_BASE__INST2_SEG1', - 'DCN_BASE__INST2_SEG2', 'DCN_BASE__INST2_SEG3', - 'DCN_BASE__INST2_SEG4', 'DCN_BASE__INST3_SEG0', - 'DCN_BASE__INST3_SEG1', 'DCN_BASE__INST3_SEG2', - 'DCN_BASE__INST3_SEG3', 'DCN_BASE__INST3_SEG4', - 'DCN_BASE__INST4_SEG0', 'DCN_BASE__INST4_SEG1', - 'DCN_BASE__INST4_SEG2', 'DCN_BASE__INST4_SEG3', - 'DCN_BASE__INST4_SEG4', 'DCN_BASE__INST5_SEG0', - 'DCN_BASE__INST5_SEG1', 'DCN_BASE__INST5_SEG2', - 'DCN_BASE__INST5_SEG3', 'DCN_BASE__INST5_SEG4', - 'DCN_BASE__INST6_SEG0', 'DCN_BASE__INST6_SEG1', - 'DCN_BASE__INST6_SEG2', 'DCN_BASE__INST6_SEG3', - 'DCN_BASE__INST6_SEG4', 'DF_BASE', 'DF_BASE__INST0_SEG0', - 'DF_BASE__INST0_SEG1', 'DF_BASE__INST0_SEG2', - 'DF_BASE__INST0_SEG3', 'DF_BASE__INST0_SEG4', - 'DF_BASE__INST1_SEG0', 'DF_BASE__INST1_SEG1', - 'DF_BASE__INST1_SEG2', 'DF_BASE__INST1_SEG3', - 'DF_BASE__INST1_SEG4', 'DF_BASE__INST2_SEG0', - 'DF_BASE__INST2_SEG1', 'DF_BASE__INST2_SEG2', - 'DF_BASE__INST2_SEG3', 'DF_BASE__INST2_SEG4', - 'DF_BASE__INST3_SEG0', 'DF_BASE__INST3_SEG1', - 'DF_BASE__INST3_SEG2', 'DF_BASE__INST3_SEG3', - 'DF_BASE__INST3_SEG4', 'DF_BASE__INST4_SEG0', - 'DF_BASE__INST4_SEG1', 'DF_BASE__INST4_SEG2', - 'DF_BASE__INST4_SEG3', 'DF_BASE__INST4_SEG4', - 'DF_BASE__INST5_SEG0', 'DF_BASE__INST5_SEG1', - 'DF_BASE__INST5_SEG2', 'DF_BASE__INST5_SEG3', - 'DF_BASE__INST5_SEG4', 'DF_BASE__INST6_SEG0', - 'DF_BASE__INST6_SEG1', 'DF_BASE__INST6_SEG2', - 'DF_BASE__INST6_SEG3', 'DF_BASE__INST6_SEG4', 'DIO_BASE', - 'DIO_BASE__INST0_SEG0', 'DIO_BASE__INST0_SEG1', - 'DIO_BASE__INST0_SEG2', 'DIO_BASE__INST0_SEG3', - 'DIO_BASE__INST0_SEG4', 'DIO_BASE__INST1_SEG0', - 'DIO_BASE__INST1_SEG1', 'DIO_BASE__INST1_SEG2', - 'DIO_BASE__INST1_SEG3', 'DIO_BASE__INST1_SEG4', - 'DIO_BASE__INST2_SEG0', 'DIO_BASE__INST2_SEG1', - 'DIO_BASE__INST2_SEG2', 'DIO_BASE__INST2_SEG3', - 'DIO_BASE__INST2_SEG4', 'DIO_BASE__INST3_SEG0', - 'DIO_BASE__INST3_SEG1', 'DIO_BASE__INST3_SEG2', - 'DIO_BASE__INST3_SEG3', 'DIO_BASE__INST3_SEG4', - 'DIO_BASE__INST4_SEG0', 'DIO_BASE__INST4_SEG1', - 'DIO_BASE__INST4_SEG2', 'DIO_BASE__INST4_SEG3', - 'DIO_BASE__INST4_SEG4', 'DIO_BASE__INST5_SEG0', - 'DIO_BASE__INST5_SEG1', 'DIO_BASE__INST5_SEG2', - 'DIO_BASE__INST5_SEG3', 'DIO_BASE__INST5_SEG4', - 'DIO_BASE__INST6_SEG0', 'DIO_BASE__INST6_SEG1', - 'DIO_BASE__INST6_SEG2', 'DIO_BASE__INST6_SEG3', - 'DIO_BASE__INST6_SEG4', 'DPCS_BASE', 'DPCS_BASE__INST0_SEG0', - 'DPCS_BASE__INST0_SEG1', 'DPCS_BASE__INST0_SEG2', - 'DPCS_BASE__INST0_SEG3', 'DPCS_BASE__INST0_SEG4', - 'DPCS_BASE__INST1_SEG0', 'DPCS_BASE__INST1_SEG1', - 'DPCS_BASE__INST1_SEG2', 'DPCS_BASE__INST1_SEG3', - 'DPCS_BASE__INST1_SEG4', 'DPCS_BASE__INST2_SEG0', - 'DPCS_BASE__INST2_SEG1', 'DPCS_BASE__INST2_SEG2', - 'DPCS_BASE__INST2_SEG3', 'DPCS_BASE__INST2_SEG4', - 'DPCS_BASE__INST3_SEG0', 'DPCS_BASE__INST3_SEG1', - 'DPCS_BASE__INST3_SEG2', 'DPCS_BASE__INST3_SEG3', - 'DPCS_BASE__INST3_SEG4', 'DPCS_BASE__INST4_SEG0', - 'DPCS_BASE__INST4_SEG1', 'DPCS_BASE__INST4_SEG2', - 'DPCS_BASE__INST4_SEG3', 'DPCS_BASE__INST4_SEG4', - 'DPCS_BASE__INST5_SEG0', 'DPCS_BASE__INST5_SEG1', - 'DPCS_BASE__INST5_SEG2', 'DPCS_BASE__INST5_SEG3', - 'DPCS_BASE__INST5_SEG4', 'DPCS_BASE__INST6_SEG0', - 'DPCS_BASE__INST6_SEG1', 'DPCS_BASE__INST6_SEG2', - 'DPCS_BASE__INST6_SEG3', 'DPCS_BASE__INST6_SEG4', 'FRAME_TMZ', - 'FUSE_BASE', 'FUSE_BASE__INST0_SEG0', 'FUSE_BASE__INST0_SEG1', - 'FUSE_BASE__INST0_SEG2', 'FUSE_BASE__INST0_SEG3', - 'FUSE_BASE__INST0_SEG4', 'FUSE_BASE__INST1_SEG0', - 'FUSE_BASE__INST1_SEG1', 'FUSE_BASE__INST1_SEG2', - 'FUSE_BASE__INST1_SEG3', 'FUSE_BASE__INST1_SEG4', - 'FUSE_BASE__INST2_SEG0', 'FUSE_BASE__INST2_SEG1', - 'FUSE_BASE__INST2_SEG2', 'FUSE_BASE__INST2_SEG3', - 'FUSE_BASE__INST2_SEG4', 'FUSE_BASE__INST3_SEG0', - 'FUSE_BASE__INST3_SEG1', 'FUSE_BASE__INST3_SEG2', - 'FUSE_BASE__INST3_SEG3', 'FUSE_BASE__INST3_SEG4', - 'FUSE_BASE__INST4_SEG0', 'FUSE_BASE__INST4_SEG1', - 'FUSE_BASE__INST4_SEG2', 'FUSE_BASE__INST4_SEG3', - 'FUSE_BASE__INST4_SEG4', 'FUSE_BASE__INST5_SEG0', - 'FUSE_BASE__INST5_SEG1', 'FUSE_BASE__INST5_SEG2', - 'FUSE_BASE__INST5_SEG3', 'FUSE_BASE__INST5_SEG4', - 'FUSE_BASE__INST6_SEG0', 'FUSE_BASE__INST6_SEG1', - 'FUSE_BASE__INST6_SEG2', 'FUSE_BASE__INST6_SEG3', - 'FUSE_BASE__INST6_SEG4', 'GC_BASE', 'GC_BASE__INST0_SEG0', - 'GC_BASE__INST0_SEG1', 'GC_BASE__INST0_SEG2', - 'GC_BASE__INST0_SEG3', 'GC_BASE__INST0_SEG4', - 'GC_BASE__INST1_SEG0', 'GC_BASE__INST1_SEG1', - 'GC_BASE__INST1_SEG2', 'GC_BASE__INST1_SEG3', - 'GC_BASE__INST1_SEG4', 'GC_BASE__INST2_SEG0', - 'GC_BASE__INST2_SEG1', 'GC_BASE__INST2_SEG2', - 'GC_BASE__INST2_SEG3', 'GC_BASE__INST2_SEG4', - 'GC_BASE__INST3_SEG0', 'GC_BASE__INST3_SEG1', - 'GC_BASE__INST3_SEG2', 'GC_BASE__INST3_SEG3', - 'GC_BASE__INST3_SEG4', 'GC_BASE__INST4_SEG0', - 'GC_BASE__INST4_SEG1', 'GC_BASE__INST4_SEG2', - 'GC_BASE__INST4_SEG3', 'GC_BASE__INST4_SEG4', - 'GC_BASE__INST5_SEG0', 'GC_BASE__INST5_SEG1', - 'GC_BASE__INST5_SEG2', 'GC_BASE__INST5_SEG3', - 'GC_BASE__INST5_SEG4', 'GC_BASE__INST6_SEG0', - 'GC_BASE__INST6_SEG1', 'GC_BASE__INST6_SEG2', - 'GC_BASE__INST6_SEG3', 'GC_BASE__INST6_SEG4', 'HDA_BASE', - 'HDA_BASE__INST0_SEG0', 'HDA_BASE__INST0_SEG1', - 'HDA_BASE__INST0_SEG2', 'HDA_BASE__INST0_SEG3', - 'HDA_BASE__INST0_SEG4', 'HDA_BASE__INST1_SEG0', - 'HDA_BASE__INST1_SEG1', 'HDA_BASE__INST1_SEG2', - 'HDA_BASE__INST1_SEG3', 'HDA_BASE__INST1_SEG4', - 'HDA_BASE__INST2_SEG0', 'HDA_BASE__INST2_SEG1', - 'HDA_BASE__INST2_SEG2', 'HDA_BASE__INST2_SEG3', - 'HDA_BASE__INST2_SEG4', 'HDA_BASE__INST3_SEG0', - 'HDA_BASE__INST3_SEG1', 'HDA_BASE__INST3_SEG2', - 'HDA_BASE__INST3_SEG3', 'HDA_BASE__INST3_SEG4', - 'HDA_BASE__INST4_SEG0', 'HDA_BASE__INST4_SEG1', - 'HDA_BASE__INST4_SEG2', 'HDA_BASE__INST4_SEG3', - 'HDA_BASE__INST4_SEG4', 'HDA_BASE__INST5_SEG0', - 'HDA_BASE__INST5_SEG1', 'HDA_BASE__INST5_SEG2', - 'HDA_BASE__INST5_SEG3', 'HDA_BASE__INST5_SEG4', - 'HDA_BASE__INST6_SEG0', 'HDA_BASE__INST6_SEG1', - 'HDA_BASE__INST6_SEG2', 'HDA_BASE__INST6_SEG3', - 'HDA_BASE__INST6_SEG4', 'HDP_BASE', 'HDP_BASE__INST0_SEG0', - 'HDP_BASE__INST0_SEG1', 'HDP_BASE__INST0_SEG2', - 'HDP_BASE__INST0_SEG3', 'HDP_BASE__INST0_SEG4', - 'HDP_BASE__INST1_SEG0', 'HDP_BASE__INST1_SEG1', - 'HDP_BASE__INST1_SEG2', 'HDP_BASE__INST1_SEG3', - 'HDP_BASE__INST1_SEG4', 'HDP_BASE__INST2_SEG0', - 'HDP_BASE__INST2_SEG1', 'HDP_BASE__INST2_SEG2', - 'HDP_BASE__INST2_SEG3', 'HDP_BASE__INST2_SEG4', - 'HDP_BASE__INST3_SEG0', 'HDP_BASE__INST3_SEG1', - 'HDP_BASE__INST3_SEG2', 'HDP_BASE__INST3_SEG3', - 'HDP_BASE__INST3_SEG4', 'HDP_BASE__INST4_SEG0', - 'HDP_BASE__INST4_SEG1', 'HDP_BASE__INST4_SEG2', - 'HDP_BASE__INST4_SEG3', 'HDP_BASE__INST4_SEG4', - 'HDP_BASE__INST5_SEG0', 'HDP_BASE__INST5_SEG1', - 'HDP_BASE__INST5_SEG2', 'HDP_BASE__INST5_SEG3', - 'HDP_BASE__INST5_SEG4', 'HDP_BASE__INST6_SEG0', - 'HDP_BASE__INST6_SEG1', 'HDP_BASE__INST6_SEG2', - 'HDP_BASE__INST6_SEG3', 'HDP_BASE__INST6_SEG4', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', 'INDIRECT_BUFFER_VALID', - 'MAX_INSTANCE', 'MAX_SEGMENT', 'MMHUB_BASE', - 'MMHUB_BASE__INST0_SEG0', 'MMHUB_BASE__INST0_SEG1', - 'MMHUB_BASE__INST0_SEG2', 'MMHUB_BASE__INST0_SEG3', - 'MMHUB_BASE__INST0_SEG4', 'MMHUB_BASE__INST1_SEG0', - 'MMHUB_BASE__INST1_SEG1', 'MMHUB_BASE__INST1_SEG2', - 'MMHUB_BASE__INST1_SEG3', 'MMHUB_BASE__INST1_SEG4', - 'MMHUB_BASE__INST2_SEG0', 'MMHUB_BASE__INST2_SEG1', - 'MMHUB_BASE__INST2_SEG2', 'MMHUB_BASE__INST2_SEG3', - 'MMHUB_BASE__INST2_SEG4', 'MMHUB_BASE__INST3_SEG0', - 'MMHUB_BASE__INST3_SEG1', 'MMHUB_BASE__INST3_SEG2', - 'MMHUB_BASE__INST3_SEG3', 'MMHUB_BASE__INST3_SEG4', - 'MMHUB_BASE__INST4_SEG0', 'MMHUB_BASE__INST4_SEG1', - 'MMHUB_BASE__INST4_SEG2', 'MMHUB_BASE__INST4_SEG3', - 'MMHUB_BASE__INST4_SEG4', 'MMHUB_BASE__INST5_SEG0', - 'MMHUB_BASE__INST5_SEG1', 'MMHUB_BASE__INST5_SEG2', - 'MMHUB_BASE__INST5_SEG3', 'MMHUB_BASE__INST5_SEG4', - 'MMHUB_BASE__INST6_SEG0', 'MMHUB_BASE__INST6_SEG1', - 'MMHUB_BASE__INST6_SEG2', 'MMHUB_BASE__INST6_SEG3', - 'MMHUB_BASE__INST6_SEG4', 'MP0_BASE', 'MP0_BASE__INST0_SEG0', - 'MP0_BASE__INST0_SEG1', 'MP0_BASE__INST0_SEG2', - 'MP0_BASE__INST0_SEG3', 'MP0_BASE__INST0_SEG4', - 'MP0_BASE__INST1_SEG0', 'MP0_BASE__INST1_SEG1', - 'MP0_BASE__INST1_SEG2', 'MP0_BASE__INST1_SEG3', - 'MP0_BASE__INST1_SEG4', 'MP0_BASE__INST2_SEG0', - 'MP0_BASE__INST2_SEG1', 'MP0_BASE__INST2_SEG2', - 'MP0_BASE__INST2_SEG3', 'MP0_BASE__INST2_SEG4', - 'MP0_BASE__INST3_SEG0', 'MP0_BASE__INST3_SEG1', - 'MP0_BASE__INST3_SEG2', 'MP0_BASE__INST3_SEG3', - 'MP0_BASE__INST3_SEG4', 'MP0_BASE__INST4_SEG0', - 'MP0_BASE__INST4_SEG1', 'MP0_BASE__INST4_SEG2', - 'MP0_BASE__INST4_SEG3', 'MP0_BASE__INST4_SEG4', - 'MP0_BASE__INST5_SEG0', 'MP0_BASE__INST5_SEG1', - 'MP0_BASE__INST5_SEG2', 'MP0_BASE__INST5_SEG3', - 'MP0_BASE__INST5_SEG4', 'MP0_BASE__INST6_SEG0', - 'MP0_BASE__INST6_SEG1', 'MP0_BASE__INST6_SEG2', - 'MP0_BASE__INST6_SEG3', 'MP0_BASE__INST6_SEG4', 'MP1_BASE', - 'MP1_BASE__INST0_SEG0', 'MP1_BASE__INST0_SEG1', - 'MP1_BASE__INST0_SEG2', 'MP1_BASE__INST0_SEG3', - 'MP1_BASE__INST0_SEG4', 'MP1_BASE__INST1_SEG0', - 'MP1_BASE__INST1_SEG1', 'MP1_BASE__INST1_SEG2', - 'MP1_BASE__INST1_SEG3', 'MP1_BASE__INST1_SEG4', - 'MP1_BASE__INST2_SEG0', 'MP1_BASE__INST2_SEG1', - 'MP1_BASE__INST2_SEG2', 'MP1_BASE__INST2_SEG3', - 'MP1_BASE__INST2_SEG4', 'MP1_BASE__INST3_SEG0', - 'MP1_BASE__INST3_SEG1', 'MP1_BASE__INST3_SEG2', - 'MP1_BASE__INST3_SEG3', 'MP1_BASE__INST3_SEG4', - 'MP1_BASE__INST4_SEG0', 'MP1_BASE__INST4_SEG1', - 'MP1_BASE__INST4_SEG2', 'MP1_BASE__INST4_SEG3', - 'MP1_BASE__INST4_SEG4', 'MP1_BASE__INST5_SEG0', - 'MP1_BASE__INST5_SEG1', 'MP1_BASE__INST5_SEG2', - 'MP1_BASE__INST5_SEG3', 'MP1_BASE__INST5_SEG4', - 'MP1_BASE__INST6_SEG0', 'MP1_BASE__INST6_SEG1', - 'MP1_BASE__INST6_SEG2', 'MP1_BASE__INST6_SEG3', - 'MP1_BASE__INST6_SEG4', 'NBIO_BASE', 'NBIO_BASE__INST0_SEG0', - 'NBIO_BASE__INST0_SEG1', 'NBIO_BASE__INST0_SEG2', - 'NBIO_BASE__INST0_SEG3', 'NBIO_BASE__INST0_SEG4', - 'NBIO_BASE__INST1_SEG0', 'NBIO_BASE__INST1_SEG1', - 'NBIO_BASE__INST1_SEG2', 'NBIO_BASE__INST1_SEG3', - 'NBIO_BASE__INST1_SEG4', 'NBIO_BASE__INST2_SEG0', - 'NBIO_BASE__INST2_SEG1', 'NBIO_BASE__INST2_SEG2', - 'NBIO_BASE__INST2_SEG3', 'NBIO_BASE__INST2_SEG4', - 'NBIO_BASE__INST3_SEG0', 'NBIO_BASE__INST3_SEG1', - 'NBIO_BASE__INST3_SEG2', 'NBIO_BASE__INST3_SEG3', - 'NBIO_BASE__INST3_SEG4', 'NBIO_BASE__INST4_SEG0', - 'NBIO_BASE__INST4_SEG1', 'NBIO_BASE__INST4_SEG2', - 'NBIO_BASE__INST4_SEG3', 'NBIO_BASE__INST4_SEG4', - 'NBIO_BASE__INST5_SEG0', 'NBIO_BASE__INST5_SEG1', - 'NBIO_BASE__INST5_SEG2', 'NBIO_BASE__INST5_SEG3', - 'NBIO_BASE__INST5_SEG4', 'NBIO_BASE__INST6_SEG0', - 'NBIO_BASE__INST6_SEG1', 'NBIO_BASE__INST6_SEG2', - 'NBIO_BASE__INST6_SEG3', 'NBIO_BASE__INST6_SEG4', 'NVD_H', - 'OSSSYS_BASE', 'OSSSYS_BASE__INST0_SEG0', - 'OSSSYS_BASE__INST0_SEG1', 'OSSSYS_BASE__INST0_SEG2', - 'OSSSYS_BASE__INST0_SEG3', 'OSSSYS_BASE__INST0_SEG4', - 'OSSSYS_BASE__INST1_SEG0', 'OSSSYS_BASE__INST1_SEG1', - 'OSSSYS_BASE__INST1_SEG2', 'OSSSYS_BASE__INST1_SEG3', - 'OSSSYS_BASE__INST1_SEG4', 'OSSSYS_BASE__INST2_SEG0', - 'OSSSYS_BASE__INST2_SEG1', 'OSSSYS_BASE__INST2_SEG2', - 'OSSSYS_BASE__INST2_SEG3', 'OSSSYS_BASE__INST2_SEG4', - 'OSSSYS_BASE__INST3_SEG0', 'OSSSYS_BASE__INST3_SEG1', - 'OSSSYS_BASE__INST3_SEG2', 'OSSSYS_BASE__INST3_SEG3', - 'OSSSYS_BASE__INST3_SEG4', 'OSSSYS_BASE__INST4_SEG0', - 'OSSSYS_BASE__INST4_SEG1', 'OSSSYS_BASE__INST4_SEG2', - 'OSSSYS_BASE__INST4_SEG3', 'OSSSYS_BASE__INST4_SEG4', - 'OSSSYS_BASE__INST5_SEG0', 'OSSSYS_BASE__INST5_SEG1', - 'OSSSYS_BASE__INST5_SEG2', 'OSSSYS_BASE__INST5_SEG3', - 'OSSSYS_BASE__INST5_SEG4', 'OSSSYS_BASE__INST6_SEG0', - 'OSSSYS_BASE__INST6_SEG1', 'OSSSYS_BASE__INST6_SEG2', - 'OSSSYS_BASE__INST6_SEG3', 'OSSSYS_BASE__INST6_SEG4', - 'PACKET2_PAD_MASK', 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', - 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', 'PACKET3_AQL_PACKET', - 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM', - 'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE', - 'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER', - 'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT', - 'PACKET3_COND_WRITE', 'PACKET3_CONTEXT_CONTROL', - 'PACKET3_CONTEXT_REG_RMW', 'PACKET3_COPY_DATA', - 'PACKET3_COPY_DATA_RB', 'PACKET3_COPY_DW', 'PACKET3_CP_DMA', - 'PACKET3_DISPATCH_DIRECT', 'PACKET3_DISPATCH_DRAW', - 'PACKET3_DISPATCH_DRAW_ACE', 'PACKET3_DISPATCH_DRAW_PREAMBLE', - 'PACKET3_DISPATCH_DRAW_PREAMBLE_ACE', 'PACKET3_DISPATCH_INDIRECT', - 'PACKET3_DMA_DATA', 'PACKET3_DMA_DATA_CMD_DAIC', - 'PACKET3_DMA_DATA_CMD_DAS', 'PACKET3_DMA_DATA_CMD_RAW_WAIT', - 'PACKET3_DMA_DATA_CMD_SAIC', 'PACKET3_DMA_DATA_CMD_SAS', - 'PACKET3_DMA_DATA_CP_SYNC', 'PACKET3_DMA_DATA_FILL_MULTI', - 'PACKET3_DRAW_INDEX_2', 'PACKET3_DRAW_INDEX_AUTO', - 'PACKET3_DRAW_INDEX_INDIRECT', - 'PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDEX_INDIRECT_MULTI', - 'PACKET3_DRAW_INDEX_MULTI_AUTO', 'PACKET3_DRAW_INDEX_MULTI_INST', - 'PACKET3_DRAW_INDEX_OFFSET_2', 'PACKET3_DRAW_INDIRECT', - 'PACKET3_DRAW_INDIRECT_COUNT_MULTI', - 'PACKET3_DRAW_INDIRECT_MULTI', 'PACKET3_DRAW_MULTI_PREAMBLE', - 'PACKET3_DRAW_PREAMBLE', 'PACKET3_DUMP_CONST_RAM', - 'PACKET3_DUMP_CONST_RAM_OFFSET', 'PACKET3_EVENT_WRITE', - 'PACKET3_EVENT_WRITE_EOP', 'PACKET3_EVENT_WRITE_EOS', - 'PACKET3_FORWARD_HEADER', 'PACKET3_FRAME_CONTROL', - 'PACKET3_GEN_PDEPTE', 'PACKET3_GET_LOD_STATS', - 'PACKET3_GFX_CNTX_UPDATE', 'PACKET3_GFX_PIPE_LOCK', - 'PACKET3_HDP_FLUSH', 'PACKET3_INCREMENT_CE_COUNTER', - 'PACKET3_INCREMENT_DE_COUNTER', 'PACKET3_INCR_UPDT_STATE', - 'PACKET3_INDEX_ATTRIBUTES_INDIRECT', 'PACKET3_INDEX_BASE', - 'PACKET3_INDEX_BUFFER_SIZE', 'PACKET3_INDEX_TYPE', - 'PACKET3_INDIRECT_BUFFER', 'PACKET3_INDIRECT_BUFFER_CNST', - 'PACKET3_INDIRECT_BUFFER_CNST_END', 'PACKET3_INDIRECT_BUFFER_END', - 'PACKET3_INDIRECT_BUFFER_PASID', 'PACKET3_INDIRECT_BUFFER_PRIV', - 'PACKET3_INTERRUPT', 'PACKET3_INVALIDATE_TLBS', - 'PACKET3_LOAD_COMPUTE_STATE', 'PACKET3_LOAD_CONFIG_REG', - 'PACKET3_LOAD_CONST_RAM', 'PACKET3_LOAD_CONTEXT_REG', - 'PACKET3_LOAD_CONTEXT_REG_INDEX', 'PACKET3_LOAD_SH_REG', - 'PACKET3_LOAD_SH_REG_INDEX', 'PACKET3_LOAD_UCONFIG_REG', - 'PACKET3_MAP_PROCESS', 'PACKET3_MAP_PROCESS_VM', - 'PACKET3_MAP_QUEUES', 'PACKET3_MEM_SEMAPHORE', - 'PACKET3_ME_INITIALIZE', 'PACKET3_NOP', 'PACKET3_NUM_INSTANCES', - 'PACKET3_OCCLUSION_QUERY', 'PACKET3_PFP_SYNC_ME', - 'PACKET3_PREAMBLE_BEGIN_CLEAR_STATE', 'PACKET3_PREAMBLE_CNTL', - 'PACKET3_PREAMBLE_END_CLEAR_STATE', 'PACKET3_PRED_EXEC', - 'PACKET3_PRIME_UTCL2', 'PACKET3_QUERY_STATUS', 'PACKET3_REG_RMW', - 'PACKET3_RELEASE_MEM', 'PACKET3_RELEASE_MEM_EXECUTE', - 'PACKET3_RELEASE_MEM_GCR_GL1_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_DISCARD', - 'PACKET3_RELEASE_MEM_GCR_GL2_INV', - 'PACKET3_RELEASE_MEM_GCR_GL2_RANGE', - 'PACKET3_RELEASE_MEM_GCR_GL2_US', - 'PACKET3_RELEASE_MEM_GCR_GL2_WB', - 'PACKET3_RELEASE_MEM_GCR_GLM_INV', - 'PACKET3_RELEASE_MEM_GCR_GLM_WB', - 'PACKET3_RELEASE_MEM_GCR_GLV_INV', 'PACKET3_RELEASE_MEM_GCR_SEQ', - 'PACKET3_REWIND', 'PACKET3_RUN_LIST', 'PACKET3_SCRATCH_RAM_READ', - 'PACKET3_SCRATCH_RAM_WRITE', 'PACKET3_SEM_SEL_SIGNAL', - 'PACKET3_SEM_SEL_SIGNAL_TYPE', 'PACKET3_SEM_SEL_WAIT', - 'PACKET3_SEM_USE_MAILBOX', 'PACKET3_SET_BASE', - 'PACKET3_SET_CONFIG_REG', 'PACKET3_SET_CONFIG_REG_END', - 'PACKET3_SET_CONFIG_REG_START', 'PACKET3_SET_CONTEXT_REG', - 'PACKET3_SET_CONTEXT_REG_END', 'PACKET3_SET_CONTEXT_REG_INDEX', - 'PACKET3_SET_CONTEXT_REG_INDIRECT', - 'PACKET3_SET_CONTEXT_REG_START', 'PACKET3_SET_PREDICATION', - 'PACKET3_SET_QUEUE_REG', 'PACKET3_SET_Q_PREEMPTION_MODE', - 'PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM', - 'PACKET3_SET_RESOURCES', 'PACKET3_SET_SH_REG', - 'PACKET3_SET_SH_REG_DI', 'PACKET3_SET_SH_REG_DI_MULTI', - 'PACKET3_SET_SH_REG_END', 'PACKET3_SET_SH_REG_INDEX', - 'PACKET3_SET_SH_REG_OFFSET', 'PACKET3_SET_SH_REG_START', - 'PACKET3_SET_UCONFIG_REG', 'PACKET3_SET_UCONFIG_REG_END', - 'PACKET3_SET_UCONFIG_REG_INDEX', 'PACKET3_SET_UCONFIG_REG_START', - 'PACKET3_SET_VGPR_REG_DI_MULTI', 'PACKET3_STRMOUT_BUFFER_UPDATE', - 'PACKET3_SURFACE_SYNC', 'PACKET3_SWITCH_BUFFER', - 'PACKET3_UNMAP_QUEUES', 'PACKET3_WAIT_ON_CE_COUNTER', - 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM', - 'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM', - 'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1', - 'PACKET_TYPE2', 'PACKET_TYPE3', 'PCIE0_BASE', - 'PCIE0_BASE__INST0_SEG0', 'PCIE0_BASE__INST0_SEG1', - 'PCIE0_BASE__INST0_SEG2', 'PCIE0_BASE__INST0_SEG3', - 'PCIE0_BASE__INST0_SEG4', 'PCIE0_BASE__INST1_SEG0', - 'PCIE0_BASE__INST1_SEG1', 'PCIE0_BASE__INST1_SEG2', - 'PCIE0_BASE__INST1_SEG3', 'PCIE0_BASE__INST1_SEG4', - 'PCIE0_BASE__INST2_SEG0', 'PCIE0_BASE__INST2_SEG1', - 'PCIE0_BASE__INST2_SEG2', 'PCIE0_BASE__INST2_SEG3', - 'PCIE0_BASE__INST2_SEG4', 'PCIE0_BASE__INST3_SEG0', - 'PCIE0_BASE__INST3_SEG1', 'PCIE0_BASE__INST3_SEG2', - 'PCIE0_BASE__INST3_SEG3', 'PCIE0_BASE__INST3_SEG4', - 'PCIE0_BASE__INST4_SEG0', 'PCIE0_BASE__INST4_SEG1', - 'PCIE0_BASE__INST4_SEG2', 'PCIE0_BASE__INST4_SEG3', - 'PCIE0_BASE__INST4_SEG4', 'PCIE0_BASE__INST5_SEG0', - 'PCIE0_BASE__INST5_SEG1', 'PCIE0_BASE__INST5_SEG2', - 'PCIE0_BASE__INST5_SEG3', 'PCIE0_BASE__INST5_SEG4', - 'PCIE0_BASE__INST6_SEG0', 'PCIE0_BASE__INST6_SEG1', - 'PCIE0_BASE__INST6_SEG2', 'PCIE0_BASE__INST6_SEG3', - 'PCIE0_BASE__INST6_SEG4', 'SDMA0_BASE', 'SDMA0_BASE__INST0_SEG0', - 'SDMA0_BASE__INST0_SEG1', 'SDMA0_BASE__INST0_SEG2', - 'SDMA0_BASE__INST0_SEG3', 'SDMA0_BASE__INST0_SEG4', - 'SDMA0_BASE__INST1_SEG0', 'SDMA0_BASE__INST1_SEG1', - 'SDMA0_BASE__INST1_SEG2', 'SDMA0_BASE__INST1_SEG3', - 'SDMA0_BASE__INST1_SEG4', 'SDMA0_BASE__INST2_SEG0', - 'SDMA0_BASE__INST2_SEG1', 'SDMA0_BASE__INST2_SEG2', - 'SDMA0_BASE__INST2_SEG3', 'SDMA0_BASE__INST2_SEG4', - 'SDMA0_BASE__INST3_SEG0', 'SDMA0_BASE__INST3_SEG1', - 'SDMA0_BASE__INST3_SEG2', 'SDMA0_BASE__INST3_SEG3', - 'SDMA0_BASE__INST3_SEG4', 'SDMA0_BASE__INST4_SEG0', - 'SDMA0_BASE__INST4_SEG1', 'SDMA0_BASE__INST4_SEG2', - 'SDMA0_BASE__INST4_SEG3', 'SDMA0_BASE__INST4_SEG4', - 'SDMA0_BASE__INST5_SEG0', 'SDMA0_BASE__INST5_SEG1', - 'SDMA0_BASE__INST5_SEG2', 'SDMA0_BASE__INST5_SEG3', - 'SDMA0_BASE__INST5_SEG4', 'SDMA0_BASE__INST6_SEG0', - 'SDMA0_BASE__INST6_SEG1', 'SDMA0_BASE__INST6_SEG2', - 'SDMA0_BASE__INST6_SEG3', 'SDMA0_BASE__INST6_SEG4', 'SDMA1_BASE', - 'SDMA1_BASE__INST0_SEG0', 'SDMA1_BASE__INST0_SEG1', - 'SDMA1_BASE__INST0_SEG2', 'SDMA1_BASE__INST0_SEG3', - 'SDMA1_BASE__INST0_SEG4', 'SDMA1_BASE__INST1_SEG0', - 'SDMA1_BASE__INST1_SEG1', 'SDMA1_BASE__INST1_SEG2', - 'SDMA1_BASE__INST1_SEG3', 'SDMA1_BASE__INST1_SEG4', - 'SDMA1_BASE__INST2_SEG0', 'SDMA1_BASE__INST2_SEG1', - 'SDMA1_BASE__INST2_SEG2', 'SDMA1_BASE__INST2_SEG3', - 'SDMA1_BASE__INST2_SEG4', 'SDMA1_BASE__INST3_SEG0', - 'SDMA1_BASE__INST3_SEG1', 'SDMA1_BASE__INST3_SEG2', - 'SDMA1_BASE__INST3_SEG3', 'SDMA1_BASE__INST3_SEG4', - 'SDMA1_BASE__INST4_SEG0', 'SDMA1_BASE__INST4_SEG1', - 'SDMA1_BASE__INST4_SEG2', 'SDMA1_BASE__INST4_SEG3', - 'SDMA1_BASE__INST4_SEG4', 'SDMA1_BASE__INST5_SEG0', - 'SDMA1_BASE__INST5_SEG1', 'SDMA1_BASE__INST5_SEG2', - 'SDMA1_BASE__INST5_SEG3', 'SDMA1_BASE__INST5_SEG4', - 'SDMA1_BASE__INST6_SEG0', 'SDMA1_BASE__INST6_SEG1', - 'SDMA1_BASE__INST6_SEG2', 'SDMA1_BASE__INST6_SEG3', - 'SDMA1_BASE__INST6_SEG4', 'SDMA_ATOMIC_ADD64', 'SDMA_OP_ATOMIC', - 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', 'SDMA_OP_FENCE', - 'SDMA_OP_GCR', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_TIMESTAMP', - 'SDMA_OP_TRAP', 'SDMA_PKT_ATOMIC', 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_FENCE', 'SDMA_PKT_GCR', 'SDMA_PKT_HDP_FLUSH', - 'SDMA_PKT_POLL_REGMEM', 'SDMA_PKT_TIMESTAMP', 'SDMA_PKT_TRAP', - 'SDMA_SUBOP_COPY_LINEAR', 'SDMA_SUBOP_COPY_LINEAR_RECT', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_USER_GCR', - 'SMUIO_BASE', 'SMUIO_BASE__INST0_SEG0', 'SMUIO_BASE__INST0_SEG1', - 'SMUIO_BASE__INST0_SEG2', 'SMUIO_BASE__INST0_SEG3', - 'SMUIO_BASE__INST0_SEG4', 'SMUIO_BASE__INST1_SEG0', - 'SMUIO_BASE__INST1_SEG1', 'SMUIO_BASE__INST1_SEG2', - 'SMUIO_BASE__INST1_SEG3', 'SMUIO_BASE__INST1_SEG4', - 'SMUIO_BASE__INST2_SEG0', 'SMUIO_BASE__INST2_SEG1', - 'SMUIO_BASE__INST2_SEG2', 'SMUIO_BASE__INST2_SEG3', - 'SMUIO_BASE__INST2_SEG4', 'SMUIO_BASE__INST3_SEG0', - 'SMUIO_BASE__INST3_SEG1', 'SMUIO_BASE__INST3_SEG2', - 'SMUIO_BASE__INST3_SEG3', 'SMUIO_BASE__INST3_SEG4', - 'SMUIO_BASE__INST4_SEG0', 'SMUIO_BASE__INST4_SEG1', - 'SMUIO_BASE__INST4_SEG2', 'SMUIO_BASE__INST4_SEG3', - 'SMUIO_BASE__INST4_SEG4', 'SMUIO_BASE__INST5_SEG0', - 'SMUIO_BASE__INST5_SEG1', 'SMUIO_BASE__INST5_SEG2', - 'SMUIO_BASE__INST5_SEG3', 'SMUIO_BASE__INST5_SEG4', - 'SMUIO_BASE__INST6_SEG0', 'SMUIO_BASE__INST6_SEG1', - 'SMUIO_BASE__INST6_SEG2', 'SMUIO_BASE__INST6_SEG3', - 'SMUIO_BASE__INST6_SEG4', 'THM_BASE', 'THM_BASE__INST0_SEG0', - 'THM_BASE__INST0_SEG1', 'THM_BASE__INST0_SEG2', - 'THM_BASE__INST0_SEG3', 'THM_BASE__INST0_SEG4', - 'THM_BASE__INST1_SEG0', 'THM_BASE__INST1_SEG1', - 'THM_BASE__INST1_SEG2', 'THM_BASE__INST1_SEG3', - 'THM_BASE__INST1_SEG4', 'THM_BASE__INST2_SEG0', - 'THM_BASE__INST2_SEG1', 'THM_BASE__INST2_SEG2', - 'THM_BASE__INST2_SEG3', 'THM_BASE__INST2_SEG4', - 'THM_BASE__INST3_SEG0', 'THM_BASE__INST3_SEG1', - 'THM_BASE__INST3_SEG2', 'THM_BASE__INST3_SEG3', - 'THM_BASE__INST3_SEG4', 'THM_BASE__INST4_SEG0', - 'THM_BASE__INST4_SEG1', 'THM_BASE__INST4_SEG2', - 'THM_BASE__INST4_SEG3', 'THM_BASE__INST4_SEG4', - 'THM_BASE__INST5_SEG0', 'THM_BASE__INST5_SEG1', - 'THM_BASE__INST5_SEG2', 'THM_BASE__INST5_SEG3', - 'THM_BASE__INST5_SEG4', 'THM_BASE__INST6_SEG0', - 'THM_BASE__INST6_SEG1', 'THM_BASE__INST6_SEG2', - 'THM_BASE__INST6_SEG3', 'THM_BASE__INST6_SEG4', 'UMC_BASE', - 'UMC_BASE__INST0_SEG0', 'UMC_BASE__INST0_SEG1', - 'UMC_BASE__INST0_SEG2', 'UMC_BASE__INST0_SEG3', - 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'regCB_COLOR_CONTROL_BASE_IDX', - 'regCB_COVERAGE_OUT_CONTROL', - 'regCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'regCB_DCC_CONFIG', - 'regCB_DCC_CONFIG2', 'regCB_DCC_CONFIG2_BASE_IDX', - 'regCB_DCC_CONFIG_BASE_IDX', 'regCB_FDCC_CONTROL', - 'regCB_FDCC_CONTROL_BASE_IDX', 'regCB_FGCG_SRAM_OVERRIDE', - 'regCB_FGCG_SRAM_OVERRIDE_BASE_IDX', 'regCB_HW_CONTROL', - 'regCB_HW_CONTROL_1', 'regCB_HW_CONTROL_1_BASE_IDX', - 'regCB_HW_CONTROL_2', 'regCB_HW_CONTROL_2_BASE_IDX', - 'regCB_HW_CONTROL_3', 'regCB_HW_CONTROL_3_BASE_IDX', - 'regCB_HW_CONTROL_4', 'regCB_HW_CONTROL_4_BASE_IDX', - 'regCB_HW_CONTROL_BASE_IDX', 'regCB_HW_MEM_ARBITER_RD', - 'regCB_HW_MEM_ARBITER_RD_BASE_IDX', 'regCB_HW_MEM_ARBITER_WR', - 'regCB_HW_MEM_ARBITER_WR_BASE_IDX', 'regCB_PERFCOUNTER0_HI', - 'regCB_PERFCOUNTER0_HI_BASE_IDX', 'regCB_PERFCOUNTER0_LO', - 'regCB_PERFCOUNTER0_LO_BASE_IDX', 'regCB_PERFCOUNTER0_SELECT', - 'regCB_PERFCOUNTER0_SELECT1', - 'regCB_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCB_PERFCOUNTER0_SELECT_BASE_IDX', 'regCB_PERFCOUNTER1_HI', - 'regCB_PERFCOUNTER1_HI_BASE_IDX', 'regCB_PERFCOUNTER1_LO', - 'regCB_PERFCOUNTER1_LO_BASE_IDX', 'regCB_PERFCOUNTER1_SELECT', - 'regCB_PERFCOUNTER1_SELECT_BASE_IDX', 'regCB_PERFCOUNTER2_HI', - 'regCB_PERFCOUNTER2_HI_BASE_IDX', 'regCB_PERFCOUNTER2_LO', - 'regCB_PERFCOUNTER2_LO_BASE_IDX', 'regCB_PERFCOUNTER2_SELECT', - 'regCB_PERFCOUNTER2_SELECT_BASE_IDX', 'regCB_PERFCOUNTER3_HI', - 'regCB_PERFCOUNTER3_HI_BASE_IDX', 'regCB_PERFCOUNTER3_LO', - 'regCB_PERFCOUNTER3_LO_BASE_IDX', 'regCB_PERFCOUNTER3_SELECT', - 'regCB_PERFCOUNTER3_SELECT_BASE_IDX', 'regCB_PERFCOUNTER_FILTER', - 'regCB_PERFCOUNTER_FILTER_BASE_IDX', - 'regCB_RMI_GL2_CACHE_CONTROL', - 'regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'regCB_SHADER_MASK', - 'regCB_SHADER_MASK_BASE_IDX', 'regCB_TARGET_MASK', - 'regCB_TARGET_MASK_BASE_IDX', 'regCC_GC_EDC_CONFIG', - 'regCC_GC_EDC_CONFIG_BASE_IDX', 'regCC_GC_PRIM_CONFIG', - 'regCC_GC_PRIM_CONFIG_BASE_IDX', 'regCC_GC_SA_UNIT_DISABLE', - 'regCC_GC_SA_UNIT_DISABLE_BASE_IDX', - 'regCC_GC_SHADER_ARRAY_CONFIG', - 'regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX', - 'regCC_GC_SHADER_RATE_CONFIG', - 'regCC_GC_SHADER_RATE_CONFIG_BASE_IDX', - 'regCC_RB_BACKEND_DISABLE', 'regCC_RB_BACKEND_DISABLE_BASE_IDX', - 'regCC_RB_DAISY_CHAIN', 'regCC_RB_DAISY_CHAIN_BASE_IDX', - 'regCC_RB_REDUNDANCY', 'regCC_RB_REDUNDANCY_BASE_IDX', - 'regCC_RMI_REDUNDANCY', 'regCC_RMI_REDUNDANCY_BASE_IDX', - 'regCGTS_TCC_DISABLE', 'regCGTS_TCC_DISABLE_BASE_IDX', - 'regCGTS_USER_TCC_DISABLE', 'regCGTS_USER_TCC_DISABLE_BASE_IDX', - 'regCGTT_CPC_CLK_CTRL', 'regCGTT_CPC_CLK_CTRL_BASE_IDX', - 'regCGTT_CPF_CLK_CTRL', 'regCGTT_CPF_CLK_CTRL_BASE_IDX', - 'regCGTT_CP_CLK_CTRL', 'regCGTT_CP_CLK_CTRL_BASE_IDX', - 'regCGTT_GS_NGG_CLK_CTRL', 'regCGTT_GS_NGG_CLK_CTRL_BASE_IDX', - 'regCGTT_PA_CLK_CTRL', 'regCGTT_PA_CLK_CTRL_BASE_IDX', - 'regCGTT_PH_CLK_CTRL0', 'regCGTT_PH_CLK_CTRL0_BASE_IDX', - 'regCGTT_PH_CLK_CTRL1', 'regCGTT_PH_CLK_CTRL1_BASE_IDX', - 'regCGTT_PH_CLK_CTRL2', 'regCGTT_PH_CLK_CTRL2_BASE_IDX', - 'regCGTT_PH_CLK_CTRL3', 'regCGTT_PH_CLK_CTRL3_BASE_IDX', - 'regCGTT_RLC_CLK_CTRL', 'regCGTT_RLC_CLK_CTRL_BASE_IDX', - 'regCGTT_SC_CLK_CTRL0', 'regCGTT_SC_CLK_CTRL0_BASE_IDX', - 'regCGTT_SC_CLK_CTRL1', 'regCGTT_SC_CLK_CTRL1_BASE_IDX', - 'regCGTT_SC_CLK_CTRL2', 'regCGTT_SC_CLK_CTRL2_BASE_IDX', - 'regCGTT_SC_CLK_CTRL3', 'regCGTT_SC_CLK_CTRL3_BASE_IDX', - 'regCGTT_SC_CLK_CTRL4', 'regCGTT_SC_CLK_CTRL4_BASE_IDX', - 'regCGTT_SQG_CLK_CTRL', 'regCGTT_SQG_CLK_CTRL_BASE_IDX', - 'regCHA_CHC_CREDITS', 'regCHA_CHC_CREDITS_BASE_IDX', - 'regCHA_CLIENT_FREE_DELAY', 'regCHA_CLIENT_FREE_DELAY_BASE_IDX', - 'regCHA_PERFCOUNTER0_HI', 'regCHA_PERFCOUNTER0_HI_BASE_IDX', - 'regCHA_PERFCOUNTER0_LO', 'regCHA_PERFCOUNTER0_LO_BASE_IDX', - 'regCHA_PERFCOUNTER0_SELECT', 'regCHA_PERFCOUNTER0_SELECT1', - 'regCHA_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER1_HI', - 'regCHA_PERFCOUNTER1_HI_BASE_IDX', 'regCHA_PERFCOUNTER1_LO', - 'regCHA_PERFCOUNTER1_LO_BASE_IDX', 'regCHA_PERFCOUNTER1_SELECT', - 'regCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER2_HI', - 'regCHA_PERFCOUNTER2_HI_BASE_IDX', 'regCHA_PERFCOUNTER2_LO', - 'regCHA_PERFCOUNTER2_LO_BASE_IDX', 'regCHA_PERFCOUNTER2_SELECT', - 'regCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHA_PERFCOUNTER3_HI', - 'regCHA_PERFCOUNTER3_HI_BASE_IDX', 'regCHA_PERFCOUNTER3_LO', - 'regCHA_PERFCOUNTER3_LO_BASE_IDX', 'regCHA_PERFCOUNTER3_SELECT', - 'regCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_CTRL', - 'regCHCG_CTRL_BASE_IDX', 'regCHCG_PERFCOUNTER0_HI', - 'regCHCG_PERFCOUNTER0_HI_BASE_IDX', 'regCHCG_PERFCOUNTER0_LO', - 'regCHCG_PERFCOUNTER0_LO_BASE_IDX', 'regCHCG_PERFCOUNTER0_SELECT', - 'regCHCG_PERFCOUNTER0_SELECT1', - 'regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER1_HI', - 'regCHCG_PERFCOUNTER1_HI_BASE_IDX', 'regCHCG_PERFCOUNTER1_LO', - 'regCHCG_PERFCOUNTER1_LO_BASE_IDX', 'regCHCG_PERFCOUNTER1_SELECT', - 'regCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER2_HI', - 'regCHCG_PERFCOUNTER2_HI_BASE_IDX', 'regCHCG_PERFCOUNTER2_LO', - 'regCHCG_PERFCOUNTER2_LO_BASE_IDX', 'regCHCG_PERFCOUNTER2_SELECT', - 'regCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHCG_PERFCOUNTER3_HI', - 'regCHCG_PERFCOUNTER3_HI_BASE_IDX', 'regCHCG_PERFCOUNTER3_LO', - 'regCHCG_PERFCOUNTER3_LO_BASE_IDX', 'regCHCG_PERFCOUNTER3_SELECT', - 'regCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHCG_STATUS', - 'regCHCG_STATUS_BASE_IDX', 'regCHC_CTRL', 'regCHC_CTRL_BASE_IDX', - 'regCHC_PERFCOUNTER0_HI', 'regCHC_PERFCOUNTER0_HI_BASE_IDX', - 'regCHC_PERFCOUNTER0_LO', 'regCHC_PERFCOUNTER0_LO_BASE_IDX', - 'regCHC_PERFCOUNTER0_SELECT', 'regCHC_PERFCOUNTER0_SELECT1', - 'regCHC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER1_HI', - 'regCHC_PERFCOUNTER1_HI_BASE_IDX', 'regCHC_PERFCOUNTER1_LO', - 'regCHC_PERFCOUNTER1_LO_BASE_IDX', 'regCHC_PERFCOUNTER1_SELECT', - 'regCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER2_HI', - 'regCHC_PERFCOUNTER2_HI_BASE_IDX', 'regCHC_PERFCOUNTER2_LO', - 'regCHC_PERFCOUNTER2_LO_BASE_IDX', 'regCHC_PERFCOUNTER2_SELECT', - 'regCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'regCHC_PERFCOUNTER3_HI', - 'regCHC_PERFCOUNTER3_HI_BASE_IDX', 'regCHC_PERFCOUNTER3_LO', - 'regCHC_PERFCOUNTER3_LO_BASE_IDX', 'regCHC_PERFCOUNTER3_SELECT', - 'regCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'regCHC_STATUS', - 'regCHC_STATUS_BASE_IDX', 'regCHICKEN_BITS', - 'regCHICKEN_BITS_BASE_IDX', 'regCHI_CHR_MGCG_OVERRIDE', - 'regCHI_CHR_MGCG_OVERRIDE_BASE_IDX', - 'regCHI_CHR_REP_FGCG_OVERRIDE', - 'regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX', 'regCH_ARB_CTRL', - 'regCH_ARB_CTRL_BASE_IDX', 'regCH_ARB_STATUS', - 'regCH_ARB_STATUS_BASE_IDX', 'regCH_DRAM_BURST_CTRL', - 'regCH_DRAM_BURST_CTRL_BASE_IDX', 'regCH_DRAM_BURST_MASK', - 'regCH_DRAM_BURST_MASK_BASE_IDX', 'regCH_PIPE_STEER', - 'regCH_PIPE_STEER_BASE_IDX', 'regCH_VC5_ENABLE', - 'regCH_VC5_ENABLE_BASE_IDX', 'regCOHER_DEST_BASE_0', - 'regCOHER_DEST_BASE_0_BASE_IDX', 'regCOHER_DEST_BASE_1', - 'regCOHER_DEST_BASE_1_BASE_IDX', 'regCOHER_DEST_BASE_2', - 'regCOHER_DEST_BASE_2_BASE_IDX', 'regCOHER_DEST_BASE_3', - 'regCOHER_DEST_BASE_3_BASE_IDX', 'regCOHER_DEST_BASE_HI_0', - 'regCOHER_DEST_BASE_HI_0_BASE_IDX', 'regCOHER_DEST_BASE_HI_1', - 'regCOHER_DEST_BASE_HI_1_BASE_IDX', 'regCOHER_DEST_BASE_HI_2', - 'regCOHER_DEST_BASE_HI_2_BASE_IDX', 'regCOHER_DEST_BASE_HI_3', - 'regCOHER_DEST_BASE_HI_3_BASE_IDX', 'regCOMPUTE_DDID_INDEX', - 'regCOMPUTE_DDID_INDEX_BASE_IDX', 'regCOMPUTE_DESTINATION_EN_SE0', - 'regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX', - 'regCOMPUTE_DESTINATION_EN_SE1', - 'regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX', - 'regCOMPUTE_DESTINATION_EN_SE2', - 'regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX', - 'regCOMPUTE_DESTINATION_EN_SE3', - 'regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'regCOMPUTE_DIM_X', - 'regCOMPUTE_DIM_X_BASE_IDX', 'regCOMPUTE_DIM_Y', - 'regCOMPUTE_DIM_Y_BASE_IDX', 'regCOMPUTE_DIM_Z', - 'regCOMPUTE_DIM_Z_BASE_IDX', 'regCOMPUTE_DISPATCH_END', - 'regCOMPUTE_DISPATCH_END_BASE_IDX', 'regCOMPUTE_DISPATCH_ID', - 'regCOMPUTE_DISPATCH_ID_BASE_IDX', - 'regCOMPUTE_DISPATCH_INITIATOR', - 'regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX', - 'regCOMPUTE_DISPATCH_INTERLEAVE', - 'regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX', - 'regCOMPUTE_DISPATCH_PKT_ADDR_HI', - 'regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX', - 'regCOMPUTE_DISPATCH_PKT_ADDR_LO', - 'regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO', - 'regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX', - 'regCOMPUTE_DISPATCH_TUNNEL', - 'regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', 'regCOMPUTE_MISC_RESERVED', - 'regCOMPUTE_MISC_RESERVED_BASE_IDX', 'regCOMPUTE_NOWHERE', - 'regCOMPUTE_NOWHERE_BASE_IDX', 'regCOMPUTE_NUM_THREAD_X', - 'regCOMPUTE_NUM_THREAD_X_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Y', - 'regCOMPUTE_NUM_THREAD_Y_BASE_IDX', 'regCOMPUTE_NUM_THREAD_Z', - 'regCOMPUTE_NUM_THREAD_Z_BASE_IDX', 'regCOMPUTE_PERFCOUNT_ENABLE', - 'regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'regCOMPUTE_PGM_HI', - 'regCOMPUTE_PGM_HI_BASE_IDX', 'regCOMPUTE_PGM_LO', - 'regCOMPUTE_PGM_LO_BASE_IDX', 'regCOMPUTE_PGM_RSRC1', - 'regCOMPUTE_PGM_RSRC1_BASE_IDX', 'regCOMPUTE_PGM_RSRC2', - 'regCOMPUTE_PGM_RSRC2_BASE_IDX', 'regCOMPUTE_PGM_RSRC3', - 'regCOMPUTE_PGM_RSRC3_BASE_IDX', 'regCOMPUTE_PIPELINESTAT_ENABLE', - 'regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'regCOMPUTE_RELAUNCH', - 'regCOMPUTE_RELAUNCH2', 'regCOMPUTE_RELAUNCH2_BASE_IDX', - 'regCOMPUTE_RELAUNCH_BASE_IDX', 'regCOMPUTE_REQ_CTRL', - 'regCOMPUTE_REQ_CTRL_BASE_IDX', 'regCOMPUTE_RESOURCE_LIMITS', - 'regCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'regCOMPUTE_RESTART_X', - 'regCOMPUTE_RESTART_X_BASE_IDX', 'regCOMPUTE_RESTART_Y', - 'regCOMPUTE_RESTART_Y_BASE_IDX', 'regCOMPUTE_RESTART_Z', - 'regCOMPUTE_RESTART_Z_BASE_IDX', 'regCOMPUTE_SHADER_CHKSUM', - 'regCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'regCOMPUTE_START_X', - 'regCOMPUTE_START_X_BASE_IDX', 'regCOMPUTE_START_Y', - 'regCOMPUTE_START_Y_BASE_IDX', 'regCOMPUTE_START_Z', - 'regCOMPUTE_START_Z_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE0', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE1', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE2', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE3', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE4', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE5', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE6', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE7', - 'regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX', - 'regCOMPUTE_THREADGROUP_ID', 'regCOMPUTE_THREADGROUP_ID_BASE_IDX', - 'regCOMPUTE_THREAD_TRACE_ENABLE', - 'regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX', - 'regCOMPUTE_TMPRING_SIZE', 'regCOMPUTE_TMPRING_SIZE_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_0', 'regCOMPUTE_USER_ACCUM_0_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_1', 'regCOMPUTE_USER_ACCUM_1_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_2', 'regCOMPUTE_USER_ACCUM_2_BASE_IDX', - 'regCOMPUTE_USER_ACCUM_3', 'regCOMPUTE_USER_ACCUM_3_BASE_IDX', - 'regCOMPUTE_USER_DATA_0', 'regCOMPUTE_USER_DATA_0_BASE_IDX', - 'regCOMPUTE_USER_DATA_1', 'regCOMPUTE_USER_DATA_10', - 'regCOMPUTE_USER_DATA_10_BASE_IDX', 'regCOMPUTE_USER_DATA_11', - 'regCOMPUTE_USER_DATA_11_BASE_IDX', 'regCOMPUTE_USER_DATA_12', - 'regCOMPUTE_USER_DATA_12_BASE_IDX', 'regCOMPUTE_USER_DATA_13', - 'regCOMPUTE_USER_DATA_13_BASE_IDX', 'regCOMPUTE_USER_DATA_14', - 'regCOMPUTE_USER_DATA_14_BASE_IDX', 'regCOMPUTE_USER_DATA_15', - 'regCOMPUTE_USER_DATA_15_BASE_IDX', - 'regCOMPUTE_USER_DATA_1_BASE_IDX', 'regCOMPUTE_USER_DATA_2', - 'regCOMPUTE_USER_DATA_2_BASE_IDX', 'regCOMPUTE_USER_DATA_3', - 'regCOMPUTE_USER_DATA_3_BASE_IDX', 'regCOMPUTE_USER_DATA_4', - 'regCOMPUTE_USER_DATA_4_BASE_IDX', 'regCOMPUTE_USER_DATA_5', - 'regCOMPUTE_USER_DATA_5_BASE_IDX', 'regCOMPUTE_USER_DATA_6', - 'regCOMPUTE_USER_DATA_6_BASE_IDX', 'regCOMPUTE_USER_DATA_7', - 'regCOMPUTE_USER_DATA_7_BASE_IDX', 'regCOMPUTE_USER_DATA_8', - 'regCOMPUTE_USER_DATA_8_BASE_IDX', 'regCOMPUTE_USER_DATA_9', - 'regCOMPUTE_USER_DATA_9_BASE_IDX', 'regCOMPUTE_VMID', - 'regCOMPUTE_VMID_BASE_IDX', 'regCOMPUTE_WAVE_RESTORE_ADDR_HI', - 'regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX', - 'regCOMPUTE_WAVE_RESTORE_ADDR_LO', - 'regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX', - 'regCONFIG_RESERVED_REG0', 'regCONFIG_RESERVED_REG0_BASE_IDX', - 'regCONFIG_RESERVED_REG1', 'regCONFIG_RESERVED_REG1_BASE_IDX', - 'regCONTEXT_RESERVED_REG0', 'regCONTEXT_RESERVED_REG0_BASE_IDX', - 'regCONTEXT_RESERVED_REG1', 'regCONTEXT_RESERVED_REG1_BASE_IDX', - 'regCPC_DDID_BASE_ADDR_HI', 'regCPC_DDID_BASE_ADDR_HI_BASE_IDX', - 'regCPC_DDID_BASE_ADDR_LO', 'regCPC_DDID_BASE_ADDR_LO_BASE_IDX', - 'regCPC_DDID_CNTL', 'regCPC_DDID_CNTL_BASE_IDX', - 'regCPC_INT_ADDR', 'regCPC_INT_ADDR_BASE_IDX', 'regCPC_INT_CNTL', - 'regCPC_INT_CNTL_BASE_IDX', 'regCPC_INT_CNTX_ID', - 'regCPC_INT_CNTX_ID_BASE_IDX', 'regCPC_INT_INFO', - 'regCPC_INT_INFO_BASE_IDX', 'regCPC_INT_PASID', - 'regCPC_INT_PASID_BASE_IDX', 'regCPC_INT_STATUS', - 'regCPC_INT_STATUS_BASE_IDX', 'regCPC_LATENCY_STATS_DATA', - 'regCPC_LATENCY_STATS_DATA_BASE_IDX', - 'regCPC_LATENCY_STATS_SELECT', - 'regCPC_LATENCY_STATS_SELECT_BASE_IDX', 'regCPC_OS_PIPES', - 'regCPC_OS_PIPES_BASE_IDX', 'regCPC_PERFCOUNTER0_HI', - 'regCPC_PERFCOUNTER0_HI_BASE_IDX', 'regCPC_PERFCOUNTER0_LO', - 'regCPC_PERFCOUNTER0_LO_BASE_IDX', 'regCPC_PERFCOUNTER0_SELECT', - 'regCPC_PERFCOUNTER0_SELECT1', - 'regCPC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPC_PERFCOUNTER1_HI', - 'regCPC_PERFCOUNTER1_HI_BASE_IDX', 'regCPC_PERFCOUNTER1_LO', - 'regCPC_PERFCOUNTER1_LO_BASE_IDX', 'regCPC_PERFCOUNTER1_SELECT', - 'regCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPC_PSP_DEBUG', - 'regCPC_PSP_DEBUG_BASE_IDX', 'regCPC_SUSPEND_CNTL_STACK_OFFSET', - 'regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', - 'regCPC_SUSPEND_CNTL_STACK_SIZE', - 'regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO', - 'regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_CONTROL', - 'regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX', - 'regCPC_SUSPEND_CTX_SAVE_SIZE', - 'regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX', - 'regCPC_SUSPEND_WG_STATE_OFFSET', - 'regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX', - 'regCPC_TC_PERF_COUNTER_WINDOW_SELECT', - 'regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'regCPC_UTCL1_CNTL', 'regCPC_UTCL1_CNTL_BASE_IDX', - 'regCPC_UTCL1_ERROR', 'regCPC_UTCL1_ERROR_BASE_IDX', - 'regCPC_UTCL1_STATUS', 'regCPC_UTCL1_STATUS_BASE_IDX', - 'regCPF_GCR_CNTL', 'regCPF_GCR_CNTL_BASE_IDX', - 'regCPF_LATENCY_STATS_DATA', 'regCPF_LATENCY_STATS_DATA_BASE_IDX', - 'regCPF_LATENCY_STATS_SELECT', - 'regCPF_LATENCY_STATS_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER0_HI', - 'regCPF_PERFCOUNTER0_HI_BASE_IDX', 'regCPF_PERFCOUNTER0_LO', - 'regCPF_PERFCOUNTER0_LO_BASE_IDX', 'regCPF_PERFCOUNTER0_SELECT', - 'regCPF_PERFCOUNTER0_SELECT1', - 'regCPF_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPF_PERFCOUNTER1_HI', - 'regCPF_PERFCOUNTER1_HI_BASE_IDX', 'regCPF_PERFCOUNTER1_LO', - 'regCPF_PERFCOUNTER1_LO_BASE_IDX', 'regCPF_PERFCOUNTER1_SELECT', - 'regCPF_PERFCOUNTER1_SELECT_BASE_IDX', - 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT', - 'regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'regCPF_UTCL1_CNTL', 'regCPF_UTCL1_CNTL_BASE_IDX', - 'regCPF_UTCL1_STATUS', 'regCPF_UTCL1_STATUS_BASE_IDX', - 'regCPG_LATENCY_STATS_DATA', 'regCPG_LATENCY_STATS_DATA_BASE_IDX', - 'regCPG_LATENCY_STATS_SELECT', - 'regCPG_LATENCY_STATS_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER0_HI', - 'regCPG_PERFCOUNTER0_HI_BASE_IDX', 'regCPG_PERFCOUNTER0_LO', - 'regCPG_PERFCOUNTER0_LO_BASE_IDX', 'regCPG_PERFCOUNTER0_SELECT', - 'regCPG_PERFCOUNTER0_SELECT1', - 'regCPG_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'regCPG_PERFCOUNTER1_HI', - 'regCPG_PERFCOUNTER1_HI_BASE_IDX', 'regCPG_PERFCOUNTER1_LO', - 'regCPG_PERFCOUNTER1_LO_BASE_IDX', 'regCPG_PERFCOUNTER1_SELECT', - 'regCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'regCPG_PSP_DEBUG', - 'regCPG_PSP_DEBUG_BASE_IDX', 'regCPG_RCIU_CAM_DATA', - 'regCPG_RCIU_CAM_DATA_BASE_IDX', 'regCPG_RCIU_CAM_DATA_PHASE0', - 'regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX', - 'regCPG_RCIU_CAM_DATA_PHASE1', - 'regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX', - 'regCPG_RCIU_CAM_DATA_PHASE2', - 'regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'regCPG_RCIU_CAM_INDEX', - 'regCPG_RCIU_CAM_INDEX_BASE_IDX', - 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT', - 'regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', - 'regCPG_UTCL1_CNTL', 'regCPG_UTCL1_CNTL_BASE_IDX', - 'regCPG_UTCL1_ERROR', 'regCPG_UTCL1_ERROR_BASE_IDX', - 'regCPG_UTCL1_STATUS', 'regCPG_UTCL1_STATUS_BASE_IDX', - 'regCP_APPEND_ADDR_HI', 'regCP_APPEND_ADDR_HI_BASE_IDX', - 'regCP_APPEND_ADDR_LO', 'regCP_APPEND_ADDR_LO_BASE_IDX', - 'regCP_APPEND_CMD_ADDR_HI', 'regCP_APPEND_CMD_ADDR_HI_BASE_IDX', - 'regCP_APPEND_CMD_ADDR_LO', 'regCP_APPEND_CMD_ADDR_LO_BASE_IDX', - 'regCP_APPEND_DATA', 'regCP_APPEND_DATA_BASE_IDX', - 'regCP_APPEND_DATA_HI', 'regCP_APPEND_DATA_HI_BASE_IDX', - 'regCP_APPEND_DATA_LO', 'regCP_APPEND_DATA_LO_BASE_IDX', - 'regCP_APPEND_DDID_CNT', 'regCP_APPEND_DDID_CNT_BASE_IDX', - 'regCP_APPEND_LAST_CS_FENCE', - 'regCP_APPEND_LAST_CS_FENCE_BASE_IDX', - 'regCP_APPEND_LAST_CS_FENCE_HI', - 'regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX', - 'regCP_APPEND_LAST_CS_FENCE_LO', - 'regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX', - 'regCP_APPEND_LAST_PS_FENCE', - 'regCP_APPEND_LAST_PS_FENCE_BASE_IDX', - 'regCP_APPEND_LAST_PS_FENCE_HI', - 'regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX', - 'regCP_APPEND_LAST_PS_FENCE_LO', - 'regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'regCP_AQL_SMM_STATUS', - 'regCP_AQL_SMM_STATUS_BASE_IDX', 'regCP_ATOMIC_PREOP_HI', - 'regCP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_ATOMIC_PREOP_LO', - 'regCP_ATOMIC_PREOP_LO_BASE_IDX', 'regCP_BUSY_STAT', - 'regCP_BUSY_STAT_BASE_IDX', 'regCP_CMD_DATA', - 'regCP_CMD_DATA_BASE_IDX', 'regCP_CMD_INDEX', - 'regCP_CMD_INDEX_BASE_IDX', 'regCP_CNTX_STAT', - 'regCP_CNTX_STAT_BASE_IDX', 'regCP_CONTEXT_CNTL', - 'regCP_CONTEXT_CNTL_BASE_IDX', 'regCP_CPC_BUSY_HYSTERESIS', - 'regCP_CPC_BUSY_HYSTERESIS_BASE_IDX', 'regCP_CPC_BUSY_STAT', - 'regCP_CPC_BUSY_STAT2', 'regCP_CPC_BUSY_STAT2_BASE_IDX', - 'regCP_CPC_BUSY_STAT_BASE_IDX', 'regCP_CPC_DEBUG', - 'regCP_CPC_DEBUG_BASE_IDX', 'regCP_CPC_DEBUG_CNTL', - 'regCP_CPC_DEBUG_CNTL_BASE_IDX', 'regCP_CPC_DEBUG_DATA', - 'regCP_CPC_DEBUG_DATA_BASE_IDX', 'regCP_CPC_GFX_CNTL', - 'regCP_CPC_GFX_CNTL_BASE_IDX', 'regCP_CPC_GRBM_FREE_COUNT', - 'regCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPC_HALT_HYST_COUNT', - 'regCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'regCP_CPC_IC_BASE_CNTL', - 'regCP_CPC_IC_BASE_CNTL_BASE_IDX', 'regCP_CPC_IC_BASE_HI', - 'regCP_CPC_IC_BASE_HI_BASE_IDX', 'regCP_CPC_IC_BASE_LO', - 'regCP_CPC_IC_BASE_LO_BASE_IDX', 'regCP_CPC_IC_OP_CNTL', - 'regCP_CPC_IC_OP_CNTL_BASE_IDX', 'regCP_CPC_MGCG_SYNC_CNTL', - 'regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX', - 'regCP_CPC_PRIV_VIOLATION_ADDR', - 'regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', - 'regCP_CPC_SCRATCH_DATA', 'regCP_CPC_SCRATCH_DATA_BASE_IDX', - 'regCP_CPC_SCRATCH_INDEX', 'regCP_CPC_SCRATCH_INDEX_BASE_IDX', - 'regCP_CPC_STALLED_STAT1', 'regCP_CPC_STALLED_STAT1_BASE_IDX', - 'regCP_CPC_STATUS', 'regCP_CPC_STATUS_BASE_IDX', - 'regCP_CPF_BUSY_HYSTERESIS1', - 'regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX', - 'regCP_CPF_BUSY_HYSTERESIS2', - 'regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CPF_BUSY_STAT', - 'regCP_CPF_BUSY_STAT2', 'regCP_CPF_BUSY_STAT2_BASE_IDX', - 'regCP_CPF_BUSY_STAT_BASE_IDX', 'regCP_CPF_GRBM_FREE_COUNT', - 'regCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'regCP_CPF_STALLED_STAT1', - 'regCP_CPF_STALLED_STAT1_BASE_IDX', 'regCP_CPF_STATUS', - 'regCP_CPF_STATUS_BASE_IDX', 'regCP_CPG_BUSY_HYSTERESIS1', - 'regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX', - 'regCP_CPG_BUSY_HYSTERESIS2', - 'regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX', 'regCP_CSF_STAT', - 'regCP_CSF_STAT_BASE_IDX', 'regCP_CU_MASK_ADDR_HI', - 'regCP_CU_MASK_ADDR_HI_BASE_IDX', 'regCP_CU_MASK_ADDR_LO', - 'regCP_CU_MASK_ADDR_LO_BASE_IDX', 'regCP_CU_MASK_CNTL', - 'regCP_CU_MASK_CNTL_BASE_IDX', 'regCP_DB_BASE_HI', - 'regCP_DB_BASE_HI_BASE_IDX', 'regCP_DB_BASE_LO', - 'regCP_DB_BASE_LO_BASE_IDX', 'regCP_DB_BUFSZ', - 'regCP_DB_BUFSZ_BASE_IDX', 'regCP_DB_CMD_BUFSZ', - 'regCP_DB_CMD_BUFSZ_BASE_IDX', 'regCP_DDID_BASE_ADDR_HI', - 'regCP_DDID_BASE_ADDR_HI_BASE_IDX', 'regCP_DDID_BASE_ADDR_LO', - 'regCP_DDID_BASE_ADDR_LO_BASE_IDX', 'regCP_DDID_CNTL', - 'regCP_DDID_CNTL_BASE_IDX', 'regCP_DEBUG', 'regCP_DEBUG_2', - 'regCP_DEBUG_2_BASE_IDX', 'regCP_DEBUG_BASE_IDX', - 'regCP_DEBUG_CNTL', 'regCP_DEBUG_CNTL_BASE_IDX', - 'regCP_DEBUG_DATA', 'regCP_DEBUG_DATA_BASE_IDX', - 'regCP_DEVICE_ID', 'regCP_DEVICE_ID_BASE_IDX', - 'regCP_DISPATCH_INDR_ADDR', 'regCP_DISPATCH_INDR_ADDR_BASE_IDX', - 'regCP_DISPATCH_INDR_ADDR_HI', - 'regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'regCP_DMA_CNTL', - 'regCP_DMA_CNTL_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_HI', - 'regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_CMD_ADDR_LO', - 'regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_ME_COMMAND', - 'regCP_DMA_ME_COMMAND_BASE_IDX', 'regCP_DMA_ME_CONTROL', - 'regCP_DMA_ME_CONTROL_BASE_IDX', 'regCP_DMA_ME_DST_ADDR', - 'regCP_DMA_ME_DST_ADDR_BASE_IDX', 'regCP_DMA_ME_DST_ADDR_HI', - 'regCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR', - 'regCP_DMA_ME_SRC_ADDR_BASE_IDX', 'regCP_DMA_ME_SRC_ADDR_HI', - 'regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_HI', - 'regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_CMD_ADDR_LO', - 'regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'regCP_DMA_PFP_COMMAND', - 'regCP_DMA_PFP_COMMAND_BASE_IDX', 'regCP_DMA_PFP_CONTROL', - 'regCP_DMA_PFP_CONTROL_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR', - 'regCP_DMA_PFP_DST_ADDR_BASE_IDX', 'regCP_DMA_PFP_DST_ADDR_HI', - 'regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR', - 'regCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'regCP_DMA_PFP_SRC_ADDR_HI', - 'regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'regCP_DMA_READ_TAGS', - 'regCP_DMA_READ_TAGS_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_HI', - 'regCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH0_ADDR_LO', - 'regCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH0_CNTL', - 'regCP_DMA_WATCH0_CNTL_BASE_IDX', 'regCP_DMA_WATCH0_MASK', - 'regCP_DMA_WATCH0_MASK_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_HI', - 'regCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH1_ADDR_LO', - 'regCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH1_CNTL', - 'regCP_DMA_WATCH1_CNTL_BASE_IDX', 'regCP_DMA_WATCH1_MASK', - 'regCP_DMA_WATCH1_MASK_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_HI', - 'regCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH2_ADDR_LO', - 'regCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH2_CNTL', - 'regCP_DMA_WATCH2_CNTL_BASE_IDX', 'regCP_DMA_WATCH2_MASK', - 'regCP_DMA_WATCH2_MASK_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_HI', - 'regCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'regCP_DMA_WATCH3_ADDR_LO', - 'regCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'regCP_DMA_WATCH3_CNTL', - 'regCP_DMA_WATCH3_CNTL_BASE_IDX', 'regCP_DMA_WATCH3_MASK', - 'regCP_DMA_WATCH3_MASK_BASE_IDX', 'regCP_DMA_WATCH_STAT', - 'regCP_DMA_WATCH_STAT_ADDR_HI', - 'regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX', - 'regCP_DMA_WATCH_STAT_ADDR_LO', - 'regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX', - 'regCP_DMA_WATCH_STAT_BASE_IDX', 'regCP_DRAW_INDX_INDR_ADDR', - 'regCP_DRAW_INDX_INDR_ADDR_BASE_IDX', - 'regCP_DRAW_INDX_INDR_ADDR_HI', - 'regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'regCP_DRAW_OBJECT', - 'regCP_DRAW_OBJECT_BASE_IDX', 'regCP_DRAW_OBJECT_COUNTER', - 'regCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'regCP_DRAW_WINDOW_CNTL', - 'regCP_DRAW_WINDOW_CNTL_BASE_IDX', 'regCP_DRAW_WINDOW_HI', - 'regCP_DRAW_WINDOW_HI_BASE_IDX', 'regCP_DRAW_WINDOW_LO', - 'regCP_DRAW_WINDOW_LO_BASE_IDX', 'regCP_DRAW_WINDOW_MASK_HI', - 'regCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'regCP_ECC_FIRSTOCCURRENCE', - 'regCP_ECC_FIRSTOCCURRENCE_BASE_IDX', - 'regCP_ECC_FIRSTOCCURRENCE_RING0', - 'regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX', - 'regCP_ECC_FIRSTOCCURRENCE_RING1', - 'regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX', - 'regCP_EOPQ_WAIT_TIME', 'regCP_EOPQ_WAIT_TIME_BASE_IDX', - 'regCP_EOP_DONE_ADDR_HI', 'regCP_EOP_DONE_ADDR_HI_BASE_IDX', - 'regCP_EOP_DONE_ADDR_LO', 'regCP_EOP_DONE_ADDR_LO_BASE_IDX', - 'regCP_EOP_DONE_CNTX_ID', 'regCP_EOP_DONE_CNTX_ID_BASE_IDX', - 'regCP_EOP_DONE_DATA_CNTL', 'regCP_EOP_DONE_DATA_CNTL_BASE_IDX', - 'regCP_EOP_DONE_DATA_HI', 'regCP_EOP_DONE_DATA_HI_BASE_IDX', - 'regCP_EOP_DONE_DATA_LO', 'regCP_EOP_DONE_DATA_LO_BASE_IDX', - 'regCP_EOP_DONE_EVENT_CNTL', 'regCP_EOP_DONE_EVENT_CNTL_BASE_IDX', - 'regCP_EOP_LAST_FENCE_HI', 'regCP_EOP_LAST_FENCE_HI_BASE_IDX', - 'regCP_EOP_LAST_FENCE_LO', 'regCP_EOP_LAST_FENCE_LO_BASE_IDX', - 'regCP_FATAL_ERROR', 'regCP_FATAL_ERROR_BASE_IDX', - 'regCP_FETCHER_SOURCE', 'regCP_FETCHER_SOURCE_BASE_IDX', - 'regCP_GDS_ATOMIC0_PREOP_HI', - 'regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_GDS_ATOMIC0_PREOP_LO', - 'regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_GDS_ATOMIC1_PREOP_HI', - 'regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_GDS_ATOMIC1_PREOP_LO', - 'regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_GDS_BKUP_ADDR', - 'regCP_GDS_BKUP_ADDR_BASE_IDX', 'regCP_GDS_BKUP_ADDR_HI', - 'regCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_HI', - 'regCP_GE_MSINVOC_COUNT_HI_BASE_IDX', 'regCP_GE_MSINVOC_COUNT_LO', - 'regCP_GE_MSINVOC_COUNT_LO_BASE_IDX', 'regCP_GFX_CNTL', - 'regCP_GFX_CNTL_BASE_IDX', 'regCP_GFX_DDID_DELTA_RPT_COUNT', - 'regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX', - 'regCP_GFX_DDID_INFLIGHT_COUNT', - 'regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_GFX_DDID_RPTR', - 'regCP_GFX_DDID_RPTR_BASE_IDX', 'regCP_GFX_DDID_WPTR', - 'regCP_GFX_DDID_WPTR_BASE_IDX', 'regCP_GFX_ERROR', - 'regCP_GFX_ERROR_BASE_IDX', 'regCP_GFX_HPD_CONTROL0', - 'regCP_GFX_HPD_CONTROL0_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO', - 'regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO', - 'regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX', - 'regCP_GFX_HPD_STATUS0', 'regCP_GFX_HPD_STATUS0_BASE_IDX', - 'regCP_GFX_HQD_ACTIVE', 'regCP_GFX_HQD_ACTIVE_BASE_IDX', - 'regCP_GFX_HQD_BASE', 'regCP_GFX_HQD_BASE_BASE_IDX', - 'regCP_GFX_HQD_BASE_HI', 'regCP_GFX_HQD_BASE_HI_BASE_IDX', - 'regCP_GFX_HQD_CNTL', 'regCP_GFX_HQD_CNTL_BASE_IDX', - 'regCP_GFX_HQD_CSMD_RPTR', 'regCP_GFX_HQD_CSMD_RPTR_BASE_IDX', - 'regCP_GFX_HQD_DEQUEUE_REQUEST', - 'regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX', - 'regCP_GFX_HQD_HQ_CONTROL0', 'regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX', - 'regCP_GFX_HQD_HQ_STATUS0', 'regCP_GFX_HQD_HQ_STATUS0_BASE_IDX', - 'regCP_GFX_HQD_IQ_TIMER', 'regCP_GFX_HQD_IQ_TIMER_BASE_IDX', - 'regCP_GFX_HQD_MAPPED', 'regCP_GFX_HQD_MAPPED_BASE_IDX', - 'regCP_GFX_HQD_OFFSET', 'regCP_GFX_HQD_OFFSET_BASE_IDX', - 'regCP_GFX_HQD_QUANTUM', 'regCP_GFX_HQD_QUANTUM_BASE_IDX', - 'regCP_GFX_HQD_QUEUE_PRIORITY', - 'regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX', - 'regCP_GFX_HQD_QUE_MGR_CONTROL', - 'regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'regCP_GFX_HQD_RPTR', - 'regCP_GFX_HQD_RPTR_ADDR', 'regCP_GFX_HQD_RPTR_ADDR_BASE_IDX', - 'regCP_GFX_HQD_RPTR_ADDR_HI', - 'regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX', - 'regCP_GFX_HQD_RPTR_BASE_IDX', 'regCP_GFX_HQD_VMID', - 'regCP_GFX_HQD_VMID_BASE_IDX', 'regCP_GFX_HQD_WPTR', - 'regCP_GFX_HQD_WPTR_BASE_IDX', 'regCP_GFX_HQD_WPTR_HI', - 'regCP_GFX_HQD_WPTR_HI_BASE_IDX', 'regCP_GFX_INDEX_MUTEX', - 'regCP_GFX_INDEX_MUTEX_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR', - 'regCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'regCP_GFX_MQD_BASE_ADDR_HI', - 'regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_GFX_MQD_CONTROL', - 'regCP_GFX_MQD_CONTROL_BASE_IDX', 'regCP_GFX_QUEUE_INDEX', - 'regCP_GFX_QUEUE_INDEX_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_BASE0', - 'regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_BASE1', - 'regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_MASK0', - 'regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE0_MASK1', - 'regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_BASE0', - 'regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_BASE1', - 'regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_MASK0', - 'regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE10_MASK1', - 'regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_BASE0', - 'regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_BASE1', - 'regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_MASK0', - 'regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE11_MASK1', - 'regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_BASE0', - 'regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_BASE1', - 'regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_MASK0', - 'regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE12_MASK1', - 'regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_BASE0', - 'regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_BASE1', - 'regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_MASK0', - 'regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE13_MASK1', - 'regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_BASE0', - 'regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_BASE1', - 'regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_MASK0', - 'regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE14_MASK1', - 'regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_BASE0', - 'regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_BASE1', - 'regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_MASK0', - 'regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE15_MASK1', - 'regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_BASE0', - 'regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_BASE1', - 'regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_MASK0', - 'regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE1_MASK1', - 'regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_BASE0', - 'regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_BASE1', - 'regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_MASK0', - 'regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE2_MASK1', - 'regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_BASE0', - 'regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_BASE1', - 'regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_MASK0', - 'regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE3_MASK1', - 'regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_BASE0', - 'regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_BASE1', - 'regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_MASK0', - 'regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE4_MASK1', - 'regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_BASE0', - 'regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_BASE1', - 'regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_MASK0', - 'regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE5_MASK1', - 'regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_BASE0', - 'regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_BASE1', - 'regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_MASK0', - 'regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE6_MASK1', - 'regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_BASE0', - 'regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_BASE1', - 'regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_MASK0', - 'regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE7_MASK1', - 'regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_BASE0', - 'regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_BASE1', - 'regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_MASK0', - 'regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE8_MASK1', - 'regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_BASE0', - 'regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_BASE1', - 'regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL0', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL1', - 'regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_MASK0', - 'regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX', - 'regCP_GFX_RS64_DC_APERTURE9_MASK1', - 'regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE0_HI', - 'regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE0_LO', - 'regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE1_HI', - 'regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE1_LO', - 'regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX', - 'regCP_GFX_RS64_DC_BASE_CNTL', - 'regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX', - 'regCP_GFX_RS64_DC_OP_CNTL', 'regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX', - 'regCP_GFX_RS64_DM_INDEX_ADDR', - 'regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX', - 'regCP_GFX_RS64_DM_INDEX_DATA', - 'regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX', 'regCP_GFX_RS64_GP0_HI0', - 'regCP_GFX_RS64_GP0_HI0_BASE_IDX', 'regCP_GFX_RS64_GP0_HI1', - 'regCP_GFX_RS64_GP0_HI1_BASE_IDX', 'regCP_GFX_RS64_GP0_LO0', - 'regCP_GFX_RS64_GP0_LO0_BASE_IDX', 'regCP_GFX_RS64_GP0_LO1', - 'regCP_GFX_RS64_GP0_LO1_BASE_IDX', 'regCP_GFX_RS64_GP1_HI0', - 'regCP_GFX_RS64_GP1_HI0_BASE_IDX', 'regCP_GFX_RS64_GP1_HI1', - 'regCP_GFX_RS64_GP1_HI1_BASE_IDX', 'regCP_GFX_RS64_GP1_LO0', - 'regCP_GFX_RS64_GP1_LO0_BASE_IDX', 'regCP_GFX_RS64_GP1_LO1', - 'regCP_GFX_RS64_GP1_LO1_BASE_IDX', 'regCP_GFX_RS64_GP2_HI0', - 'regCP_GFX_RS64_GP2_HI0_BASE_IDX', 'regCP_GFX_RS64_GP2_HI1', - 'regCP_GFX_RS64_GP2_HI1_BASE_IDX', 'regCP_GFX_RS64_GP2_LO0', - 'regCP_GFX_RS64_GP2_LO0_BASE_IDX', 'regCP_GFX_RS64_GP2_LO1', - 'regCP_GFX_RS64_GP2_LO1_BASE_IDX', 'regCP_GFX_RS64_GP3_HI0', - 'regCP_GFX_RS64_GP3_HI0_BASE_IDX', 'regCP_GFX_RS64_GP3_HI1', - 'regCP_GFX_RS64_GP3_HI1_BASE_IDX', 'regCP_GFX_RS64_GP3_LO0', - 'regCP_GFX_RS64_GP3_LO0_BASE_IDX', 'regCP_GFX_RS64_GP3_LO1', - 'regCP_GFX_RS64_GP3_LO1_BASE_IDX', 'regCP_GFX_RS64_GP4_HI0', - 'regCP_GFX_RS64_GP4_HI0_BASE_IDX', 'regCP_GFX_RS64_GP4_HI1', - 'regCP_GFX_RS64_GP4_HI1_BASE_IDX', 'regCP_GFX_RS64_GP4_LO0', - 'regCP_GFX_RS64_GP4_LO0_BASE_IDX', 'regCP_GFX_RS64_GP4_LO1', - 'regCP_GFX_RS64_GP4_LO1_BASE_IDX', 'regCP_GFX_RS64_GP5_HI0', - 'regCP_GFX_RS64_GP5_HI0_BASE_IDX', 'regCP_GFX_RS64_GP5_HI1', - 'regCP_GFX_RS64_GP5_HI1_BASE_IDX', 'regCP_GFX_RS64_GP5_LO0', - 'regCP_GFX_RS64_GP5_LO0_BASE_IDX', 'regCP_GFX_RS64_GP5_LO1', - 'regCP_GFX_RS64_GP5_LO1_BASE_IDX', 'regCP_GFX_RS64_GP6_HI', - 'regCP_GFX_RS64_GP6_HI_BASE_IDX', 'regCP_GFX_RS64_GP6_LO', - 'regCP_GFX_RS64_GP6_LO_BASE_IDX', 'regCP_GFX_RS64_GP7_HI', - 'regCP_GFX_RS64_GP7_HI_BASE_IDX', 'regCP_GFX_RS64_GP7_LO', - 'regCP_GFX_RS64_GP7_LO_BASE_IDX', 'regCP_GFX_RS64_GP8_HI', - 'regCP_GFX_RS64_GP8_HI_BASE_IDX', 'regCP_GFX_RS64_GP8_LO', - 'regCP_GFX_RS64_GP8_LO_BASE_IDX', 'regCP_GFX_RS64_GP9_HI', - 'regCP_GFX_RS64_GP9_HI_BASE_IDX', 'regCP_GFX_RS64_GP9_LO', - 'regCP_GFX_RS64_GP9_LO_BASE_IDX', 'regCP_GFX_RS64_INSTR_PNTR0', - 'regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX', - 'regCP_GFX_RS64_INSTR_PNTR1', - 'regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX', - 'regCP_GFX_RS64_INTERRUPT0', 'regCP_GFX_RS64_INTERRUPT0_BASE_IDX', - 'regCP_GFX_RS64_INTERRUPT1', 'regCP_GFX_RS64_INTERRUPT1_BASE_IDX', - 'regCP_GFX_RS64_INTR_EN0', 'regCP_GFX_RS64_INTR_EN0_BASE_IDX', - 'regCP_GFX_RS64_INTR_EN1', 'regCP_GFX_RS64_INTR_EN1_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_APERTURE', - 'regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_BASE0_HI', - 'regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_BASE0_LO', - 'regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_APERTURE', - 'regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO', - 'regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO', - 'regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_MASK0_HI', - 'regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_MASK0_LO', - 'regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE', - 'regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO', - 'regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX', - 'regCP_GFX_RS64_MIBOUND_HI', 'regCP_GFX_RS64_MIBOUND_HI_BASE_IDX', - 'regCP_GFX_RS64_MIBOUND_LO', 'regCP_GFX_RS64_MIBOUND_LO_BASE_IDX', - 'regCP_GFX_RS64_MIP_HI0', 'regCP_GFX_RS64_MIP_HI0_BASE_IDX', - 'regCP_GFX_RS64_MIP_HI1', 'regCP_GFX_RS64_MIP_HI1_BASE_IDX', - 'regCP_GFX_RS64_MIP_LO0', 'regCP_GFX_RS64_MIP_LO0_BASE_IDX', - 'regCP_GFX_RS64_MIP_LO1', 'regCP_GFX_RS64_MIP_LO1_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_HI0', - 'regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_HI1', - 'regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_LO0', - 'regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX', - 'regCP_GFX_RS64_MTIMECMP_LO1', - 'regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX', - 'regCP_GFX_RS64_PENDING_INTERRUPT0', - 'regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX', - 'regCP_GFX_RS64_PENDING_INTERRUPT1', - 'regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX', - 'regCP_GFX_RS64_PERFCOUNT_CNTL0', - 'regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX', - 'regCP_GFX_RS64_PERFCOUNT_CNTL1', - 'regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX', - 'regCP_GPU_TIMESTAMP_OFFSET_HI', - 'regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX', - 'regCP_GPU_TIMESTAMP_OFFSET_LO', - 'regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'regCP_GRBM_FREE_COUNT', - 'regCP_GRBM_FREE_COUNT_BASE_IDX', 'regCP_HPD_MES_ROQ_OFFSETS', - 'regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_ROQ_OFFSETS', - 'regCP_HPD_ROQ_OFFSETS_BASE_IDX', 'regCP_HPD_STATUS0', - 'regCP_HPD_STATUS0_BASE_IDX', 'regCP_HPD_UTCL1_CNTL', - 'regCP_HPD_UTCL1_CNTL_BASE_IDX', 'regCP_HPD_UTCL1_ERROR', - 'regCP_HPD_UTCL1_ERROR_ADDR', - 'regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX', - 'regCP_HPD_UTCL1_ERROR_BASE_IDX', 'regCP_HQD_ACTIVE', - 'regCP_HQD_ACTIVE_BASE_IDX', 'regCP_HQD_AQL_CONTROL', - 'regCP_HQD_AQL_CONTROL_BASE_IDX', 'regCP_HQD_ATOMIC0_PREOP_HI', - 'regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_HQD_ATOMIC0_PREOP_LO', - 'regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_HQD_ATOMIC1_PREOP_HI', - 'regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_HQD_ATOMIC1_PREOP_LO', - 'regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX', - 'regCP_HQD_CNTL_STACK_OFFSET', - 'regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', - 'regCP_HQD_CNTL_STACK_SIZE', 'regCP_HQD_CNTL_STACK_SIZE_BASE_IDX', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO', - 'regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', - 'regCP_HQD_CTX_SAVE_CONTROL', - 'regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', 'regCP_HQD_CTX_SAVE_SIZE', - 'regCP_HQD_CTX_SAVE_SIZE_BASE_IDX', - 'regCP_HQD_DDID_DELTA_RPT_COUNT', - 'regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX', - 'regCP_HQD_DDID_INFLIGHT_COUNT', - 'regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'regCP_HQD_DDID_RPTR', - 'regCP_HQD_DDID_RPTR_BASE_IDX', 'regCP_HQD_DDID_WPTR', - 'regCP_HQD_DDID_WPTR_BASE_IDX', 'regCP_HQD_DEQUEUE_REQUEST', - 'regCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'regCP_HQD_DEQUEUE_STATUS', - 'regCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'regCP_HQD_DMA_OFFLOAD', - 'regCP_HQD_DMA_OFFLOAD_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR', - 'regCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'regCP_HQD_EOP_BASE_ADDR_HI', - 'regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_EOP_CONTROL', - 'regCP_HQD_EOP_CONTROL_BASE_IDX', 'regCP_HQD_EOP_EVENTS', - 'regCP_HQD_EOP_EVENTS_BASE_IDX', 'regCP_HQD_EOP_RPTR', - 'regCP_HQD_EOP_RPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR', - 'regCP_HQD_EOP_WPTR_BASE_IDX', 'regCP_HQD_EOP_WPTR_MEM', - 'regCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'regCP_HQD_ERROR', - 'regCP_HQD_ERROR_BASE_IDX', 'regCP_HQD_GDS_RESOURCE_STATE', - 'regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'regCP_HQD_GFX_CONTROL', - 'regCP_HQD_GFX_CONTROL_BASE_IDX', 'regCP_HQD_GFX_STATUS', - 'regCP_HQD_GFX_STATUS_BASE_IDX', 'regCP_HQD_HQ_CONTROL0', - 'regCP_HQD_HQ_CONTROL0_BASE_IDX', 'regCP_HQD_HQ_CONTROL1', - 'regCP_HQD_HQ_CONTROL1_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER0', - 'regCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'regCP_HQD_HQ_SCHEDULER1', - 'regCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'regCP_HQD_HQ_STATUS0', - 'regCP_HQD_HQ_STATUS0_BASE_IDX', 'regCP_HQD_HQ_STATUS1', - 'regCP_HQD_HQ_STATUS1_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR', - 'regCP_HQD_IB_BASE_ADDR_BASE_IDX', 'regCP_HQD_IB_BASE_ADDR_HI', - 'regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'regCP_HQD_IB_CONTROL', - 'regCP_HQD_IB_CONTROL_BASE_IDX', 'regCP_HQD_IB_RPTR', - 'regCP_HQD_IB_RPTR_BASE_IDX', 'regCP_HQD_IQ_RPTR', - 'regCP_HQD_IQ_RPTR_BASE_IDX', 'regCP_HQD_IQ_TIMER', - 'regCP_HQD_IQ_TIMER_BASE_IDX', 'regCP_HQD_MSG_TYPE', - 'regCP_HQD_MSG_TYPE_BASE_IDX', 'regCP_HQD_OFFLOAD', - 'regCP_HQD_OFFLOAD_BASE_IDX', 'regCP_HQD_PERSISTENT_STATE', - 'regCP_HQD_PERSISTENT_STATE_BASE_IDX', 'regCP_HQD_PIPE_PRIORITY', - 'regCP_HQD_PIPE_PRIORITY_BASE_IDX', 'regCP_HQD_PQ_BASE', - 'regCP_HQD_PQ_BASE_BASE_IDX', 'regCP_HQD_PQ_BASE_HI', - 'regCP_HQD_PQ_BASE_HI_BASE_IDX', 'regCP_HQD_PQ_CONTROL', - 'regCP_HQD_PQ_CONTROL_BASE_IDX', 'regCP_HQD_PQ_DOORBELL_CONTROL', - 'regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'regCP_HQD_PQ_RPTR', - 'regCP_HQD_PQ_RPTR_BASE_IDX', 'regCP_HQD_PQ_RPTR_REPORT_ADDR', - 'regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX', - 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI', - 'regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', - 'regCP_HQD_PQ_WPTR_HI', 'regCP_HQD_PQ_WPTR_HI_BASE_IDX', - 'regCP_HQD_PQ_WPTR_LO', 'regCP_HQD_PQ_WPTR_LO_BASE_IDX', - 'regCP_HQD_PQ_WPTR_POLL_ADDR', - 'regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX', - 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI', - 'regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'regCP_HQD_QUANTUM', - 'regCP_HQD_QUANTUM_BASE_IDX', 'regCP_HQD_QUEUE_PRIORITY', - 'regCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'regCP_HQD_SEMA_CMD', - 'regCP_HQD_SEMA_CMD_BASE_IDX', - 'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT', - 'regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX', - 'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET', - 'regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', - 'regCP_HQD_SUSPEND_WG_STATE_OFFSET', - 'regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'regCP_HQD_VMID', - 'regCP_HQD_VMID_BASE_IDX', 'regCP_HQD_WG_STATE_OFFSET', - 'regCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'regCP_HYP_MEC1_UCODE_ADDR', - 'regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC1_UCODE_DATA', - 'regCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'regCP_HYP_MEC2_UCODE_ADDR', - 'regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'regCP_HYP_MEC2_UCODE_DATA', - 'regCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'regCP_HYP_ME_UCODE_ADDR', - 'regCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'regCP_HYP_ME_UCODE_DATA', - 'regCP_HYP_ME_UCODE_DATA_BASE_IDX', 'regCP_HYP_PFP_UCODE_ADDR', - 'regCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_HYP_PFP_UCODE_DATA', - 'regCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'regCP_IB1_BASE_HI', - 'regCP_IB1_BASE_HI_BASE_IDX', 'regCP_IB1_BASE_LO', - 'regCP_IB1_BASE_LO_BASE_IDX', 'regCP_IB1_BUFSZ', - 'regCP_IB1_BUFSZ_BASE_IDX', 'regCP_IB1_CMD_BUFSZ', - 'regCP_IB1_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_BASE_HI', - 'regCP_IB2_BASE_HI_BASE_IDX', 'regCP_IB2_BASE_LO', - 'regCP_IB2_BASE_LO_BASE_IDX', 'regCP_IB2_BUFSZ', - 'regCP_IB2_BUFSZ_BASE_IDX', 'regCP_IB2_CMD_BUFSZ', - 'regCP_IB2_CMD_BUFSZ_BASE_IDX', 'regCP_IB2_OFFSET', - 'regCP_IB2_OFFSET_BASE_IDX', 'regCP_IB2_PREAMBLE_BEGIN', - 'regCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'regCP_IB2_PREAMBLE_END', - 'regCP_IB2_PREAMBLE_END_BASE_IDX', 'regCP_INDEX_BASE_ADDR', - 'regCP_INDEX_BASE_ADDR_BASE_IDX', 'regCP_INDEX_BASE_ADDR_HI', - 'regCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'regCP_INDEX_TYPE', - 'regCP_INDEX_TYPE_BASE_IDX', 'regCP_INT_CNTL', - 'regCP_INT_CNTL_BASE_IDX', 'regCP_INT_CNTL_RING0', - 'regCP_INT_CNTL_RING0_BASE_IDX', 'regCP_INT_CNTL_RING1', - 'regCP_INT_CNTL_RING1_BASE_IDX', 'regCP_INT_STATUS', - 'regCP_INT_STATUS_BASE_IDX', 'regCP_INT_STATUS_RING0', - 'regCP_INT_STATUS_RING0_BASE_IDX', 'regCP_INT_STATUS_RING1', - 'regCP_INT_STATUS_RING1_BASE_IDX', 'regCP_IQ_WAIT_TIME1', - 'regCP_IQ_WAIT_TIME1_BASE_IDX', 'regCP_IQ_WAIT_TIME2', - 'regCP_IQ_WAIT_TIME2_BASE_IDX', 'regCP_IQ_WAIT_TIME3', - 'regCP_IQ_WAIT_TIME3_BASE_IDX', 'regCP_MAX_CONTEXT', - 'regCP_MAX_CONTEXT_BASE_IDX', 'regCP_MAX_DRAW_COUNT', - 'regCP_MAX_DRAW_COUNT_BASE_IDX', 'regCP_ME0_PIPE0_PRIORITY', - 'regCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE0_VMID', - 'regCP_ME0_PIPE0_VMID_BASE_IDX', 'regCP_ME0_PIPE1_PRIORITY', - 'regCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME0_PIPE1_VMID', - 'regCP_ME0_PIPE1_VMID_BASE_IDX', 'regCP_ME0_PIPE_PRIORITY_CNTS', - 'regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_ME1_PIPE0_INT_CNTL', 'regCP_ME1_PIPE0_INT_CNTL_BASE_IDX', - 'regCP_ME1_PIPE0_INT_STATUS', - 'regCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE0_PRIORITY', - 'regCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE1_INT_CNTL', - 'regCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE1_INT_STATUS', - 'regCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE1_PRIORITY', - 'regCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE2_INT_CNTL', - 'regCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE2_INT_STATUS', - 'regCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE2_PRIORITY', - 'regCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME1_PIPE3_INT_CNTL', - 'regCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME1_PIPE3_INT_STATUS', - 'regCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME1_PIPE3_PRIORITY', - 'regCP_ME1_PIPE3_PRIORITY_BASE_IDX', - 'regCP_ME1_PIPE_PRIORITY_CNTS', - 'regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_ME2_PIPE0_INT_CNTL', 'regCP_ME2_PIPE0_INT_CNTL_BASE_IDX', - 'regCP_ME2_PIPE0_INT_STATUS', - 'regCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE0_PRIORITY', - 'regCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE1_INT_CNTL', - 'regCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE1_INT_STATUS', - 'regCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE1_PRIORITY', - 'regCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE2_INT_CNTL', - 'regCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE2_INT_STATUS', - 'regCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE2_PRIORITY', - 'regCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'regCP_ME2_PIPE3_INT_CNTL', - 'regCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'regCP_ME2_PIPE3_INT_STATUS', - 'regCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'regCP_ME2_PIPE3_PRIORITY', - 'regCP_ME2_PIPE3_PRIORITY_BASE_IDX', - 'regCP_ME2_PIPE_PRIORITY_CNTS', - 'regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_MEC1_F32_INTERRUPT', 'regCP_MEC1_F32_INTERRUPT_BASE_IDX', - 'regCP_MEC1_F32_INT_DIS', 'regCP_MEC1_F32_INT_DIS_BASE_IDX', - 'regCP_MEC1_INSTR_PNTR', 'regCP_MEC1_INSTR_PNTR_BASE_IDX', - 'regCP_MEC1_INTR_ROUTINE_START', - 'regCP_MEC1_INTR_ROUTINE_START_BASE_IDX', - 'regCP_MEC1_PRGRM_CNTR_START', - 'regCP_MEC1_PRGRM_CNTR_START_BASE_IDX', - 'regCP_MEC2_F32_INTERRUPT', 'regCP_MEC2_F32_INTERRUPT_BASE_IDX', - 'regCP_MEC2_F32_INT_DIS', 'regCP_MEC2_F32_INT_DIS_BASE_IDX', - 'regCP_MEC2_INSTR_PNTR', 'regCP_MEC2_INSTR_PNTR_BASE_IDX', - 'regCP_MEC2_INTR_ROUTINE_START', - 'regCP_MEC2_INTR_ROUTINE_START_BASE_IDX', - 'regCP_MEC2_PRGRM_CNTR_START', - 'regCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'regCP_MEC_CNTL', - 'regCP_MEC_CNTL_BASE_IDX', 'regCP_MEC_DC_APERTURE0_BASE', - 'regCP_MEC_DC_APERTURE0_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE0_CNTL', - 'regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE0_MASK', - 'regCP_MEC_DC_APERTURE0_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE10_BASE', - 'regCP_MEC_DC_APERTURE10_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE10_CNTL', - 'regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE10_MASK', - 'regCP_MEC_DC_APERTURE10_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE11_BASE', - 'regCP_MEC_DC_APERTURE11_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE11_CNTL', - 'regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE11_MASK', - 'regCP_MEC_DC_APERTURE11_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE12_BASE', - 'regCP_MEC_DC_APERTURE12_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE12_CNTL', - 'regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE12_MASK', - 'regCP_MEC_DC_APERTURE12_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE13_BASE', - 'regCP_MEC_DC_APERTURE13_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE13_CNTL', - 'regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE13_MASK', - 'regCP_MEC_DC_APERTURE13_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE14_BASE', - 'regCP_MEC_DC_APERTURE14_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE14_CNTL', - 'regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE14_MASK', - 'regCP_MEC_DC_APERTURE14_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE15_BASE', - 'regCP_MEC_DC_APERTURE15_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE15_CNTL', - 'regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE15_MASK', - 'regCP_MEC_DC_APERTURE15_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE1_BASE', - 'regCP_MEC_DC_APERTURE1_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE1_CNTL', - 'regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE1_MASK', - 'regCP_MEC_DC_APERTURE1_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE2_BASE', - 'regCP_MEC_DC_APERTURE2_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE2_CNTL', - 'regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE2_MASK', - 'regCP_MEC_DC_APERTURE2_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE3_BASE', - 'regCP_MEC_DC_APERTURE3_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE3_CNTL', - 'regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE3_MASK', - 'regCP_MEC_DC_APERTURE3_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE4_BASE', - 'regCP_MEC_DC_APERTURE4_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE4_CNTL', - 'regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE4_MASK', - 'regCP_MEC_DC_APERTURE4_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE5_BASE', - 'regCP_MEC_DC_APERTURE5_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE5_CNTL', - 'regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE5_MASK', - 'regCP_MEC_DC_APERTURE5_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE6_BASE', - 'regCP_MEC_DC_APERTURE6_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE6_CNTL', - 'regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE6_MASK', - 'regCP_MEC_DC_APERTURE6_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE7_BASE', - 'regCP_MEC_DC_APERTURE7_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE7_CNTL', - 'regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE7_MASK', - 'regCP_MEC_DC_APERTURE7_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE8_BASE', - 'regCP_MEC_DC_APERTURE8_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE8_CNTL', - 'regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE8_MASK', - 'regCP_MEC_DC_APERTURE8_MASK_BASE_IDX', - 'regCP_MEC_DC_APERTURE9_BASE', - 'regCP_MEC_DC_APERTURE9_BASE_BASE_IDX', - 'regCP_MEC_DC_APERTURE9_CNTL', - 'regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX', - 'regCP_MEC_DC_APERTURE9_MASK', - 'regCP_MEC_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MEC_DC_BASE_CNTL', - 'regCP_MEC_DC_BASE_CNTL_BASE_IDX', 'regCP_MEC_DC_BASE_HI', - 'regCP_MEC_DC_BASE_HI_BASE_IDX', 'regCP_MEC_DC_BASE_LO', - 'regCP_MEC_DC_BASE_LO_BASE_IDX', 'regCP_MEC_DC_OP_CNTL', - 'regCP_MEC_DC_OP_CNTL_BASE_IDX', 'regCP_MEC_DM_INDEX_ADDR', - 'regCP_MEC_DM_INDEX_ADDR_BASE_IDX', 'regCP_MEC_DM_INDEX_DATA', - 'regCP_MEC_DM_INDEX_DATA_BASE_IDX', - 'regCP_MEC_DOORBELL_RANGE_LOWER', - 'regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX', - 'regCP_MEC_DOORBELL_RANGE_UPPER', - 'regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_MEC_GP0_HI', - 'regCP_MEC_GP0_HI_BASE_IDX', 'regCP_MEC_GP0_LO', - 'regCP_MEC_GP0_LO_BASE_IDX', 'regCP_MEC_GP1_HI', - 'regCP_MEC_GP1_HI_BASE_IDX', 'regCP_MEC_GP1_LO', - 'regCP_MEC_GP1_LO_BASE_IDX', 'regCP_MEC_GP2_HI', - 'regCP_MEC_GP2_HI_BASE_IDX', 'regCP_MEC_GP2_LO', - 'regCP_MEC_GP2_LO_BASE_IDX', 'regCP_MEC_GP3_HI', - 'regCP_MEC_GP3_HI_BASE_IDX', 'regCP_MEC_GP3_LO', - 'regCP_MEC_GP3_LO_BASE_IDX', 'regCP_MEC_GP4_HI', - 'regCP_MEC_GP4_HI_BASE_IDX', 'regCP_MEC_GP4_LO', - 'regCP_MEC_GP4_LO_BASE_IDX', 'regCP_MEC_GP5_HI', - 'regCP_MEC_GP5_HI_BASE_IDX', 'regCP_MEC_GP5_LO', - 'regCP_MEC_GP5_LO_BASE_IDX', 'regCP_MEC_GP6_HI', - 'regCP_MEC_GP6_HI_BASE_IDX', 'regCP_MEC_GP6_LO', - 'regCP_MEC_GP6_LO_BASE_IDX', 'regCP_MEC_GP7_HI', - 'regCP_MEC_GP7_HI_BASE_IDX', 'regCP_MEC_GP7_LO', - 'regCP_MEC_GP7_LO_BASE_IDX', 'regCP_MEC_GP8_HI', - 'regCP_MEC_GP8_HI_BASE_IDX', 'regCP_MEC_GP8_LO', - 'regCP_MEC_GP8_LO_BASE_IDX', 'regCP_MEC_GP9_HI', - 'regCP_MEC_GP9_HI_BASE_IDX', 'regCP_MEC_GP9_LO', - 'regCP_MEC_GP9_LO_BASE_IDX', 'regCP_MEC_ISA_CNTL', - 'regCP_MEC_ISA_CNTL_BASE_IDX', 'regCP_MEC_JT_STAT', - 'regCP_MEC_JT_STAT_BASE_IDX', 'regCP_MEC_LOCAL_APERTURE', - 'regCP_MEC_LOCAL_APERTURE_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_HI', - 'regCP_MEC_LOCAL_BASE0_HI_BASE_IDX', 'regCP_MEC_LOCAL_BASE0_LO', - 'regCP_MEC_LOCAL_BASE0_LO_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_APERTURE', - 'regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_BASE_HI', - 'regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_BASE_LO', - 'regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_MASK_HI', - 'regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX', - 'regCP_MEC_LOCAL_INSTR_MASK_LO', - 'regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX', - 'regCP_MEC_LOCAL_MASK0_HI', 'regCP_MEC_LOCAL_MASK0_HI_BASE_IDX', - 'regCP_MEC_LOCAL_MASK0_LO', 'regCP_MEC_LOCAL_MASK0_LO_BASE_IDX', - 'regCP_MEC_LOCAL_SCRATCH_APERTURE', - 'regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX', - 'regCP_MEC_LOCAL_SCRATCH_BASE_HI', - 'regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX', - 'regCP_MEC_LOCAL_SCRATCH_BASE_LO', - 'regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX', 'regCP_MEC_MDBASE_HI', - 'regCP_MEC_MDBASE_HI_BASE_IDX', 'regCP_MEC_MDBASE_LO', - 'regCP_MEC_MDBASE_LO_BASE_IDX', 'regCP_MEC_MDBOUND_HI', - 'regCP_MEC_MDBOUND_HI_BASE_IDX', 'regCP_MEC_MDBOUND_LO', - 'regCP_MEC_MDBOUND_LO_BASE_IDX', 'regCP_MEC_ME1_HEADER_DUMP', - 'regCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME1_UCODE_ADDR', - 'regCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME1_UCODE_DATA', - 'regCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'regCP_MEC_ME2_HEADER_DUMP', - 'regCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'regCP_MEC_ME2_UCODE_ADDR', - 'regCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'regCP_MEC_ME2_UCODE_DATA', - 'regCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'regCP_MEC_MIBOUND_HI', - 'regCP_MEC_MIBOUND_HI_BASE_IDX', 'regCP_MEC_MIBOUND_LO', - 'regCP_MEC_MIBOUND_LO_BASE_IDX', 'regCP_MEC_MIE_HI', - 'regCP_MEC_MIE_HI_BASE_IDX', 'regCP_MEC_MIE_LO', - 'regCP_MEC_MIE_LO_BASE_IDX', 'regCP_MEC_MIP_HI', - 'regCP_MEC_MIP_HI_BASE_IDX', 'regCP_MEC_MIP_LO', - 'regCP_MEC_MIP_LO_BASE_IDX', 'regCP_MEC_MTIMECMP_HI', - 'regCP_MEC_MTIMECMP_HI_BASE_IDX', 'regCP_MEC_MTIMECMP_LO', - 'regCP_MEC_MTIMECMP_LO_BASE_IDX', 'regCP_MEC_MTVEC_HI', - 'regCP_MEC_MTVEC_HI_BASE_IDX', 'regCP_MEC_MTVEC_LO', - 'regCP_MEC_MTVEC_LO_BASE_IDX', 'regCP_MEC_RS64_CNTL', - 'regCP_MEC_RS64_CNTL_BASE_IDX', 'regCP_MEC_RS64_INSTR_PNTR', - 'regCP_MEC_RS64_INSTR_PNTR_BASE_IDX', 'regCP_MEC_RS64_INTERRUPT', - 'regCP_MEC_RS64_INTERRUPT_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_16', - 'regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_17', - 'regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_18', - 'regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_19', - 'regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_20', - 'regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_21', - 'regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_22', - 'regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_23', - 'regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_24', - 'regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_25', - 'regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_26', - 'regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_27', - 'regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_28', - 'regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_29', - 'regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_30', - 'regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX', - 'regCP_MEC_RS64_INTERRUPT_DATA_31', - 'regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX', - 'regCP_MEC_RS64_PENDING_INTERRUPT', - 'regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX', - 'regCP_MEC_RS64_PERFCOUNT_CNTL', - 'regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX', - 'regCP_MEC_RS64_PRGRM_CNTR_START', - 'regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX', - 'regCP_MEC_RS64_PRGRM_CNTR_START_HI', - 'regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_MEQ_AVAIL', - 'regCP_MEQ_AVAIL_BASE_IDX', 'regCP_MEQ_STAT', - 'regCP_MEQ_STAT_BASE_IDX', 'regCP_MEQ_THRESHOLDS', - 'regCP_MEQ_THRESHOLDS_BASE_IDX', 'regCP_MES_CNTL', - 'regCP_MES_CNTL_BASE_IDX', 'regCP_MES_DC_APERTURE0_BASE', - 'regCP_MES_DC_APERTURE0_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE0_CNTL', - 'regCP_MES_DC_APERTURE0_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE0_MASK', - 'regCP_MES_DC_APERTURE0_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE10_BASE', - 'regCP_MES_DC_APERTURE10_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE10_CNTL', - 'regCP_MES_DC_APERTURE10_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE10_MASK', - 'regCP_MES_DC_APERTURE10_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE11_BASE', - 'regCP_MES_DC_APERTURE11_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE11_CNTL', - 'regCP_MES_DC_APERTURE11_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE11_MASK', - 'regCP_MES_DC_APERTURE11_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE12_BASE', - 'regCP_MES_DC_APERTURE12_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE12_CNTL', - 'regCP_MES_DC_APERTURE12_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE12_MASK', - 'regCP_MES_DC_APERTURE12_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE13_BASE', - 'regCP_MES_DC_APERTURE13_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE13_CNTL', - 'regCP_MES_DC_APERTURE13_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE13_MASK', - 'regCP_MES_DC_APERTURE13_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE14_BASE', - 'regCP_MES_DC_APERTURE14_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE14_CNTL', - 'regCP_MES_DC_APERTURE14_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE14_MASK', - 'regCP_MES_DC_APERTURE14_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE15_BASE', - 'regCP_MES_DC_APERTURE15_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE15_CNTL', - 'regCP_MES_DC_APERTURE15_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE15_MASK', - 'regCP_MES_DC_APERTURE15_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE1_BASE', - 'regCP_MES_DC_APERTURE1_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE1_CNTL', - 'regCP_MES_DC_APERTURE1_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE1_MASK', - 'regCP_MES_DC_APERTURE1_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE2_BASE', - 'regCP_MES_DC_APERTURE2_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE2_CNTL', - 'regCP_MES_DC_APERTURE2_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE2_MASK', - 'regCP_MES_DC_APERTURE2_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE3_BASE', - 'regCP_MES_DC_APERTURE3_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE3_CNTL', - 'regCP_MES_DC_APERTURE3_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE3_MASK', - 'regCP_MES_DC_APERTURE3_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE4_BASE', - 'regCP_MES_DC_APERTURE4_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE4_CNTL', - 'regCP_MES_DC_APERTURE4_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE4_MASK', - 'regCP_MES_DC_APERTURE4_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE5_BASE', - 'regCP_MES_DC_APERTURE5_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE5_CNTL', - 'regCP_MES_DC_APERTURE5_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE5_MASK', - 'regCP_MES_DC_APERTURE5_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE6_BASE', - 'regCP_MES_DC_APERTURE6_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE6_CNTL', - 'regCP_MES_DC_APERTURE6_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE6_MASK', - 'regCP_MES_DC_APERTURE6_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE7_BASE', - 'regCP_MES_DC_APERTURE7_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE7_CNTL', - 'regCP_MES_DC_APERTURE7_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE7_MASK', - 'regCP_MES_DC_APERTURE7_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE8_BASE', - 'regCP_MES_DC_APERTURE8_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE8_CNTL', - 'regCP_MES_DC_APERTURE8_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE8_MASK', - 'regCP_MES_DC_APERTURE8_MASK_BASE_IDX', - 'regCP_MES_DC_APERTURE9_BASE', - 'regCP_MES_DC_APERTURE9_BASE_BASE_IDX', - 'regCP_MES_DC_APERTURE9_CNTL', - 'regCP_MES_DC_APERTURE9_CNTL_BASE_IDX', - 'regCP_MES_DC_APERTURE9_MASK', - 'regCP_MES_DC_APERTURE9_MASK_BASE_IDX', 'regCP_MES_DC_BASE_CNTL', - 'regCP_MES_DC_BASE_CNTL_BASE_IDX', 'regCP_MES_DC_BASE_HI', - 'regCP_MES_DC_BASE_HI_BASE_IDX', 'regCP_MES_DC_BASE_LO', - 'regCP_MES_DC_BASE_LO_BASE_IDX', 'regCP_MES_DC_OP_CNTL', - 'regCP_MES_DC_OP_CNTL_BASE_IDX', - 'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR', - 'regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX', - 'regCP_MES_DM_INDEX_ADDR', 'regCP_MES_DM_INDEX_ADDR_BASE_IDX', - 'regCP_MES_DM_INDEX_DATA', 'regCP_MES_DM_INDEX_DATA_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL1', - 'regCP_MES_DOORBELL_CONTROL1_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL2', - 'regCP_MES_DOORBELL_CONTROL2_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL3', - 'regCP_MES_DOORBELL_CONTROL3_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL4', - 'regCP_MES_DOORBELL_CONTROL4_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL5', - 'regCP_MES_DOORBELL_CONTROL5_BASE_IDX', - 'regCP_MES_DOORBELL_CONTROL6', - 'regCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'regCP_MES_GP0_HI', - 'regCP_MES_GP0_HI_BASE_IDX', 'regCP_MES_GP0_LO', - 'regCP_MES_GP0_LO_BASE_IDX', 'regCP_MES_GP1_HI', - 'regCP_MES_GP1_HI_BASE_IDX', 'regCP_MES_GP1_LO', - 'regCP_MES_GP1_LO_BASE_IDX', 'regCP_MES_GP2_HI', - 'regCP_MES_GP2_HI_BASE_IDX', 'regCP_MES_GP2_LO', - 'regCP_MES_GP2_LO_BASE_IDX', 'regCP_MES_GP3_HI', - 'regCP_MES_GP3_HI_BASE_IDX', 'regCP_MES_GP3_LO', - 'regCP_MES_GP3_LO_BASE_IDX', 'regCP_MES_GP4_HI', - 'regCP_MES_GP4_HI_BASE_IDX', 'regCP_MES_GP4_LO', - 'regCP_MES_GP4_LO_BASE_IDX', 'regCP_MES_GP5_HI', - 'regCP_MES_GP5_HI_BASE_IDX', 'regCP_MES_GP5_LO', - 'regCP_MES_GP5_LO_BASE_IDX', 'regCP_MES_GP6_HI', - 'regCP_MES_GP6_HI_BASE_IDX', 'regCP_MES_GP6_LO', - 'regCP_MES_GP6_LO_BASE_IDX', 'regCP_MES_GP7_HI', - 'regCP_MES_GP7_HI_BASE_IDX', 'regCP_MES_GP7_LO', - 'regCP_MES_GP7_LO_BASE_IDX', 'regCP_MES_GP8_HI', - 'regCP_MES_GP8_HI_BASE_IDX', 'regCP_MES_GP8_LO', - 'regCP_MES_GP8_LO_BASE_IDX', 'regCP_MES_GP9_HI', - 'regCP_MES_GP9_HI_BASE_IDX', 'regCP_MES_GP9_LO', - 'regCP_MES_GP9_LO_BASE_IDX', 'regCP_MES_HEADER_DUMP', - 'regCP_MES_HEADER_DUMP_BASE_IDX', 'regCP_MES_IC_BASE_CNTL', - 'regCP_MES_IC_BASE_CNTL_BASE_IDX', 'regCP_MES_IC_BASE_HI', - 'regCP_MES_IC_BASE_HI_BASE_IDX', 'regCP_MES_IC_BASE_LO', - 'regCP_MES_IC_BASE_LO_BASE_IDX', 'regCP_MES_IC_OP_CNTL', - 'regCP_MES_IC_OP_CNTL_BASE_IDX', 'regCP_MES_INSTR_PNTR', - 'regCP_MES_INSTR_PNTR_BASE_IDX', 'regCP_MES_INTERRUPT', - 'regCP_MES_INTERRUPT_BASE_IDX', 'regCP_MES_INTERRUPT_DATA_16', - 'regCP_MES_INTERRUPT_DATA_16_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_17', - 'regCP_MES_INTERRUPT_DATA_17_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_18', - 'regCP_MES_INTERRUPT_DATA_18_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_19', - 'regCP_MES_INTERRUPT_DATA_19_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_20', - 'regCP_MES_INTERRUPT_DATA_20_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_21', - 'regCP_MES_INTERRUPT_DATA_21_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_22', - 'regCP_MES_INTERRUPT_DATA_22_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_23', - 'regCP_MES_INTERRUPT_DATA_23_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_24', - 'regCP_MES_INTERRUPT_DATA_24_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_25', - 'regCP_MES_INTERRUPT_DATA_25_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_26', - 'regCP_MES_INTERRUPT_DATA_26_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_27', - 'regCP_MES_INTERRUPT_DATA_27_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_28', - 'regCP_MES_INTERRUPT_DATA_28_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_29', - 'regCP_MES_INTERRUPT_DATA_29_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_30', - 'regCP_MES_INTERRUPT_DATA_30_BASE_IDX', - 'regCP_MES_INTERRUPT_DATA_31', - 'regCP_MES_INTERRUPT_DATA_31_BASE_IDX', - 'regCP_MES_INTR_ROUTINE_START', - 'regCP_MES_INTR_ROUTINE_START_BASE_IDX', - 'regCP_MES_INTR_ROUTINE_START_HI', - 'regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX', - 'regCP_MES_LOCAL_APERTURE', 'regCP_MES_LOCAL_APERTURE_BASE_IDX', - 'regCP_MES_LOCAL_BASE0_HI', 'regCP_MES_LOCAL_BASE0_HI_BASE_IDX', - 'regCP_MES_LOCAL_BASE0_LO', 'regCP_MES_LOCAL_BASE0_LO_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_APERTURE', - 'regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_BASE_HI', - 'regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_BASE_LO', - 'regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_MASK_HI', - 'regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX', - 'regCP_MES_LOCAL_INSTR_MASK_LO', - 'regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX', - 'regCP_MES_LOCAL_MASK0_HI', 'regCP_MES_LOCAL_MASK0_HI_BASE_IDX', - 'regCP_MES_LOCAL_MASK0_LO', 'regCP_MES_LOCAL_MASK0_LO_BASE_IDX', - 'regCP_MES_LOCAL_SCRATCH_APERTURE', - 'regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX', - 'regCP_MES_LOCAL_SCRATCH_BASE_HI', - 'regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX', - 'regCP_MES_LOCAL_SCRATCH_BASE_LO', - 'regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX', - 'regCP_MES_MARCHID_HI', 'regCP_MES_MARCHID_HI_BASE_IDX', - 'regCP_MES_MARCHID_LO', 'regCP_MES_MARCHID_LO_BASE_IDX', - 'regCP_MES_MBADADDR_HI', 'regCP_MES_MBADADDR_HI_BASE_IDX', - 'regCP_MES_MBADADDR_LO', 'regCP_MES_MBADADDR_LO_BASE_IDX', - 'regCP_MES_MCAUSE_HI', 'regCP_MES_MCAUSE_HI_BASE_IDX', - 'regCP_MES_MCAUSE_LO', 'regCP_MES_MCAUSE_LO_BASE_IDX', - 'regCP_MES_MCYCLE_HI', 'regCP_MES_MCYCLE_HI_BASE_IDX', - 'regCP_MES_MCYCLE_LO', 'regCP_MES_MCYCLE_LO_BASE_IDX', - 'regCP_MES_MDBASE_HI', 'regCP_MES_MDBASE_HI_BASE_IDX', - 'regCP_MES_MDBASE_LO', 'regCP_MES_MDBASE_LO_BASE_IDX', - 'regCP_MES_MDBOUND_HI', 'regCP_MES_MDBOUND_HI_BASE_IDX', - 'regCP_MES_MDBOUND_LO', 'regCP_MES_MDBOUND_LO_BASE_IDX', - 'regCP_MES_MEPC_HI', 'regCP_MES_MEPC_HI_BASE_IDX', - 'regCP_MES_MEPC_LO', 'regCP_MES_MEPC_LO_BASE_IDX', - 'regCP_MES_MHARTID_HI', 'regCP_MES_MHARTID_HI_BASE_IDX', - 'regCP_MES_MHARTID_LO', 'regCP_MES_MHARTID_LO_BASE_IDX', - 'regCP_MES_MIBASE_HI', 'regCP_MES_MIBASE_HI_BASE_IDX', - 'regCP_MES_MIBASE_LO', 'regCP_MES_MIBASE_LO_BASE_IDX', - 'regCP_MES_MIBOUND_HI', 'regCP_MES_MIBOUND_HI_BASE_IDX', - 'regCP_MES_MIBOUND_LO', 'regCP_MES_MIBOUND_LO_BASE_IDX', - 'regCP_MES_MIE_HI', 'regCP_MES_MIE_HI_BASE_IDX', - 'regCP_MES_MIE_LO', 'regCP_MES_MIE_LO_BASE_IDX', - 'regCP_MES_MIMPID_HI', 'regCP_MES_MIMPID_HI_BASE_IDX', - 'regCP_MES_MIMPID_LO', 'regCP_MES_MIMPID_LO_BASE_IDX', - 'regCP_MES_MINSTRET_HI', 'regCP_MES_MINSTRET_HI_BASE_IDX', - 'regCP_MES_MINSTRET_LO', 'regCP_MES_MINSTRET_LO_BASE_IDX', - 'regCP_MES_MIP_HI', 'regCP_MES_MIP_HI_BASE_IDX', - 'regCP_MES_MIP_LO', 'regCP_MES_MIP_LO_BASE_IDX', - 'regCP_MES_MISA_HI', 'regCP_MES_MISA_HI_BASE_IDX', - 'regCP_MES_MISA_LO', 'regCP_MES_MISA_LO_BASE_IDX', - 'regCP_MES_MSCRATCH_HI', 'regCP_MES_MSCRATCH_HI_BASE_IDX', - 'regCP_MES_MSCRATCH_LO', 'regCP_MES_MSCRATCH_LO_BASE_IDX', - 'regCP_MES_MSTATUS_HI', 'regCP_MES_MSTATUS_HI_BASE_IDX', - 'regCP_MES_MSTATUS_LO', 'regCP_MES_MSTATUS_LO_BASE_IDX', - 'regCP_MES_MTIMECMP_HI', 'regCP_MES_MTIMECMP_HI_BASE_IDX', - 'regCP_MES_MTIMECMP_LO', 'regCP_MES_MTIMECMP_LO_BASE_IDX', - 'regCP_MES_MTIME_HI', 'regCP_MES_MTIME_HI_BASE_IDX', - 'regCP_MES_MTIME_LO', 'regCP_MES_MTIME_LO_BASE_IDX', - 'regCP_MES_MTVEC_HI', 'regCP_MES_MTVEC_HI_BASE_IDX', - 'regCP_MES_MTVEC_LO', 'regCP_MES_MTVEC_LO_BASE_IDX', - 'regCP_MES_MVENDORID_HI', 'regCP_MES_MVENDORID_HI_BASE_IDX', - 'regCP_MES_MVENDORID_LO', 'regCP_MES_MVENDORID_LO_BASE_IDX', - 'regCP_MES_PENDING_INTERRUPT', - 'regCP_MES_PENDING_INTERRUPT_BASE_IDX', - 'regCP_MES_PERFCOUNT_CNTL', 'regCP_MES_PERFCOUNT_CNTL_BASE_IDX', - 'regCP_MES_PIPE0_PRIORITY', 'regCP_MES_PIPE0_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE1_PRIORITY', 'regCP_MES_PIPE1_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE2_PRIORITY', 'regCP_MES_PIPE2_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE3_PRIORITY', 'regCP_MES_PIPE3_PRIORITY_BASE_IDX', - 'regCP_MES_PIPE_PRIORITY_CNTS', - 'regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX', - 'regCP_MES_PRGRM_CNTR_START', - 'regCP_MES_PRGRM_CNTR_START_BASE_IDX', - 'regCP_MES_PRGRM_CNTR_START_HI', - 'regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX', - 'regCP_MES_PROCESS_QUANTUM_PIPE0', - 'regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX', - 'regCP_MES_PROCESS_QUANTUM_PIPE1', - 'regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX', - 'regCP_MES_SCRATCH_DATA', 'regCP_MES_SCRATCH_DATA_BASE_IDX', - 'regCP_MES_SCRATCH_INDEX', 'regCP_MES_SCRATCH_INDEX_BASE_IDX', - 'regCP_ME_ATOMIC_PREOP_HI', 'regCP_ME_ATOMIC_PREOP_HI_BASE_IDX', - 'regCP_ME_ATOMIC_PREOP_LO', 'regCP_ME_ATOMIC_PREOP_LO_BASE_IDX', - 'regCP_ME_CNTL', 'regCP_ME_CNTL_BASE_IDX', 'regCP_ME_COHER_BASE', - 'regCP_ME_COHER_BASE_BASE_IDX', 'regCP_ME_COHER_BASE_HI', - 'regCP_ME_COHER_BASE_HI_BASE_IDX', 'regCP_ME_COHER_CNTL', - 'regCP_ME_COHER_CNTL_BASE_IDX', 'regCP_ME_COHER_SIZE', - 'regCP_ME_COHER_SIZE_BASE_IDX', 'regCP_ME_COHER_SIZE_HI', - 'regCP_ME_COHER_SIZE_HI_BASE_IDX', 'regCP_ME_COHER_STATUS', - 'regCP_ME_COHER_STATUS_BASE_IDX', 'regCP_ME_F32_INTERRUPT', - 'regCP_ME_F32_INTERRUPT_BASE_IDX', - 'regCP_ME_GDS_ATOMIC0_PREOP_HI', - 'regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_ME_GDS_ATOMIC0_PREOP_LO', - 'regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_ME_GDS_ATOMIC1_PREOP_HI', - 'regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_ME_GDS_ATOMIC1_PREOP_LO', - 'regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'regCP_ME_HEADER_DUMP', - 'regCP_ME_HEADER_DUMP_BASE_IDX', 'regCP_ME_IC_BASE_CNTL', - 'regCP_ME_IC_BASE_CNTL_BASE_IDX', 'regCP_ME_IC_BASE_HI', - 'regCP_ME_IC_BASE_HI_BASE_IDX', 'regCP_ME_IC_BASE_LO', - 'regCP_ME_IC_BASE_LO_BASE_IDX', 'regCP_ME_IC_OP_CNTL', - 'regCP_ME_IC_OP_CNTL_BASE_IDX', 'regCP_ME_INSTR_PNTR', - 'regCP_ME_INSTR_PNTR_BASE_IDX', 'regCP_ME_INTR_ROUTINE_START', - 'regCP_ME_INTR_ROUTINE_START_BASE_IDX', - 'regCP_ME_INTR_ROUTINE_START_HI', - 'regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_ME_MC_RADDR_HI', - 'regCP_ME_MC_RADDR_HI_BASE_IDX', 'regCP_ME_MC_RADDR_LO', - 'regCP_ME_MC_RADDR_LO_BASE_IDX', 'regCP_ME_MC_WADDR_HI', - 'regCP_ME_MC_WADDR_HI_BASE_IDX', 'regCP_ME_MC_WADDR_LO', - 'regCP_ME_MC_WADDR_LO_BASE_IDX', 'regCP_ME_MC_WDATA_HI', - 'regCP_ME_MC_WDATA_HI_BASE_IDX', 'regCP_ME_MC_WDATA_LO', - 'regCP_ME_MC_WDATA_LO_BASE_IDX', 'regCP_ME_PREEMPTION', - 'regCP_ME_PREEMPTION_BASE_IDX', 'regCP_ME_PRGRM_CNTR_START', - 'regCP_ME_PRGRM_CNTR_START_BASE_IDX', - 'regCP_ME_PRGRM_CNTR_START_HI', - 'regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_ME_RAM_DATA', - 'regCP_ME_RAM_DATA_BASE_IDX', 'regCP_ME_RAM_RADDR', - 'regCP_ME_RAM_RADDR_BASE_IDX', 'regCP_ME_RAM_WADDR', - 'regCP_ME_RAM_WADDR_BASE_IDX', 'regCP_ME_SDMA_CS', - 'regCP_ME_SDMA_CS_BASE_IDX', 'regCP_MQD_BASE_ADDR', - 'regCP_MQD_BASE_ADDR_BASE_IDX', 'regCP_MQD_BASE_ADDR_HI', - 'regCP_MQD_BASE_ADDR_HI_BASE_IDX', 'regCP_MQD_CONTROL', - 'regCP_MQD_CONTROL_BASE_IDX', 'regCP_PA_CINVOC_COUNT_HI', - 'regCP_PA_CINVOC_COUNT_HI_BASE_IDX', 'regCP_PA_CINVOC_COUNT_LO', - 'regCP_PA_CINVOC_COUNT_LO_BASE_IDX', 'regCP_PA_CPRIM_COUNT_HI', - 'regCP_PA_CPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_CPRIM_COUNT_LO', - 'regCP_PA_CPRIM_COUNT_LO_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_HI', - 'regCP_PA_MSPRIM_COUNT_HI_BASE_IDX', 'regCP_PA_MSPRIM_COUNT_LO', - 'regCP_PA_MSPRIM_COUNT_LO_BASE_IDX', 'regCP_PERFMON_CNTL', - 'regCP_PERFMON_CNTL_BASE_IDX', 'regCP_PERFMON_CNTX_CNTL', - 'regCP_PERFMON_CNTX_CNTL_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_HI', - 'regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', 'regCP_PFP_ATOMIC_PREOP_LO', - 'regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX', - 'regCP_PFP_COMPLETION_STATUS', - 'regCP_PFP_COMPLETION_STATUS_BASE_IDX', 'regCP_PFP_F32_INTERRUPT', - 'regCP_PFP_F32_INTERRUPT_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC0_PREOP_HI', - 'regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC0_PREOP_LO', - 'regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC1_PREOP_HI', - 'regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', - 'regCP_PFP_GDS_ATOMIC1_PREOP_LO', - 'regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', - 'regCP_PFP_HEADER_DUMP', 'regCP_PFP_HEADER_DUMP_BASE_IDX', - 'regCP_PFP_IB_CONTROL', 'regCP_PFP_IB_CONTROL_BASE_IDX', - 'regCP_PFP_IC_BASE_CNTL', 'regCP_PFP_IC_BASE_CNTL_BASE_IDX', - 'regCP_PFP_IC_BASE_HI', 'regCP_PFP_IC_BASE_HI_BASE_IDX', - 'regCP_PFP_IC_BASE_LO', 'regCP_PFP_IC_BASE_LO_BASE_IDX', - 'regCP_PFP_IC_OP_CNTL', 'regCP_PFP_IC_OP_CNTL_BASE_IDX', - 'regCP_PFP_INSTR_PNTR', 'regCP_PFP_INSTR_PNTR_BASE_IDX', - 'regCP_PFP_INTR_ROUTINE_START', - 'regCP_PFP_INTR_ROUTINE_START_BASE_IDX', - 'regCP_PFP_INTR_ROUTINE_START_HI', - 'regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX', 'regCP_PFP_JT_STAT', - 'regCP_PFP_JT_STAT_BASE_IDX', 'regCP_PFP_LOAD_CONTROL', - 'regCP_PFP_LOAD_CONTROL_BASE_IDX', 'regCP_PFP_METADATA_BASE_ADDR', - 'regCP_PFP_METADATA_BASE_ADDR_BASE_IDX', - 'regCP_PFP_METADATA_BASE_ADDR_HI', - 'regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX', - 'regCP_PFP_PRGRM_CNTR_START', - 'regCP_PFP_PRGRM_CNTR_START_BASE_IDX', - 'regCP_PFP_PRGRM_CNTR_START_HI', - 'regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX', 'regCP_PFP_SDMA_CS', - 'regCP_PFP_SDMA_CS_BASE_IDX', 'regCP_PFP_UCODE_ADDR', - 'regCP_PFP_UCODE_ADDR_BASE_IDX', 'regCP_PFP_UCODE_DATA', - 'regCP_PFP_UCODE_DATA_BASE_IDX', 'regCP_PIPEID', - 'regCP_PIPEID_BASE_IDX', 'regCP_PIPE_STATS_ADDR_HI', - 'regCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'regCP_PIPE_STATS_ADDR_LO', - 'regCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'regCP_PIPE_STATS_CONTROL', - 'regCP_PIPE_STATS_CONTROL_BASE_IDX', 'regCP_PQ_STATUS', - 'regCP_PQ_STATUS_BASE_IDX', 'regCP_PQ_WPTR_POLL_CNTL', - 'regCP_PQ_WPTR_POLL_CNTL1', 'regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX', - 'regCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'regCP_PRED_NOT_VISIBLE', - 'regCP_PRED_NOT_VISIBLE_BASE_IDX', 'regCP_PRIV_VIOLATION_ADDR', - 'regCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'regCP_PROCESS_QUANTUM', - 'regCP_PROCESS_QUANTUM_BASE_IDX', 'regCP_PWR_CNTL', - 'regCP_PWR_CNTL_BASE_IDX', 'regCP_RB0_ACTIVE', - 'regCP_RB0_ACTIVE_BASE_IDX', 'regCP_RB0_BASE', - 'regCP_RB0_BASE_BASE_IDX', 'regCP_RB0_BASE_HI', - 'regCP_RB0_BASE_HI_BASE_IDX', 'regCP_RB0_BUFSZ_MASK', - 'regCP_RB0_BUFSZ_MASK_BASE_IDX', 'regCP_RB0_CNTL', - 'regCP_RB0_CNTL_BASE_IDX', 'regCP_RB0_RPTR', - 'regCP_RB0_RPTR_ADDR', 'regCP_RB0_RPTR_ADDR_BASE_IDX', - 'regCP_RB0_RPTR_ADDR_HI', 'regCP_RB0_RPTR_ADDR_HI_BASE_IDX', - 'regCP_RB0_RPTR_BASE_IDX', 'regCP_RB0_WPTR', - 'regCP_RB0_WPTR_BASE_IDX', 'regCP_RB0_WPTR_HI', - 'regCP_RB0_WPTR_HI_BASE_IDX', 'regCP_RB1_ACTIVE', - 'regCP_RB1_ACTIVE_BASE_IDX', 'regCP_RB1_BASE', - 'regCP_RB1_BASE_BASE_IDX', 'regCP_RB1_BASE_HI', - 'regCP_RB1_BASE_HI_BASE_IDX', 'regCP_RB1_BUFSZ_MASK', - 'regCP_RB1_BUFSZ_MASK_BASE_IDX', 'regCP_RB1_CNTL', - 'regCP_RB1_CNTL_BASE_IDX', 'regCP_RB1_RPTR', - 'regCP_RB1_RPTR_ADDR', 'regCP_RB1_RPTR_ADDR_BASE_IDX', - 'regCP_RB1_RPTR_ADDR_HI', 'regCP_RB1_RPTR_ADDR_HI_BASE_IDX', - 'regCP_RB1_RPTR_BASE_IDX', 'regCP_RB1_WPTR', - 'regCP_RB1_WPTR_BASE_IDX', 'regCP_RB1_WPTR_HI', - 'regCP_RB1_WPTR_HI_BASE_IDX', 'regCP_RB_ACTIVE', - 'regCP_RB_ACTIVE_BASE_IDX', 'regCP_RB_BASE', - 'regCP_RB_BASE_BASE_IDX', 'regCP_RB_BUFSZ_MASK', - 'regCP_RB_BUFSZ_MASK_BASE_IDX', 'regCP_RB_CNTL', - 'regCP_RB_CNTL_BASE_IDX', 'regCP_RB_DOORBELL_CLEAR', - 'regCP_RB_DOORBELL_CLEAR_BASE_IDX', 'regCP_RB_DOORBELL_CONTROL', - 'regCP_RB_DOORBELL_CONTROL_BASE_IDX', - 'regCP_RB_DOORBELL_RANGE_LOWER', - 'regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX', - 'regCP_RB_DOORBELL_RANGE_UPPER', - 'regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'regCP_RB_OFFSET', - 'regCP_RB_OFFSET_BASE_IDX', 'regCP_RB_RPTR', 'regCP_RB_RPTR_ADDR', - 'regCP_RB_RPTR_ADDR_BASE_IDX', 'regCP_RB_RPTR_ADDR_HI', - 'regCP_RB_RPTR_ADDR_HI_BASE_IDX', 'regCP_RB_RPTR_BASE_IDX', - 'regCP_RB_RPTR_WR', 'regCP_RB_RPTR_WR_BASE_IDX', - 'regCP_RB_STATUS', 'regCP_RB_STATUS_BASE_IDX', 'regCP_RB_VMID', - 'regCP_RB_VMID_BASE_IDX', 'regCP_RB_WPTR', - 'regCP_RB_WPTR_BASE_IDX', 'regCP_RB_WPTR_DELAY', - 'regCP_RB_WPTR_DELAY_BASE_IDX', 'regCP_RB_WPTR_HI', - 'regCP_RB_WPTR_HI_BASE_IDX', 'regCP_RB_WPTR_POLL_ADDR_HI', - 'regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regCP_RB_WPTR_POLL_ADDR_LO', - 'regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', 'regCP_RB_WPTR_POLL_CNTL', - 'regCP_RB_WPTR_POLL_CNTL_BASE_IDX', 'regCP_RING0_PRIORITY', - 'regCP_RING0_PRIORITY_BASE_IDX', 'regCP_RING1_PRIORITY', - 'regCP_RING1_PRIORITY_BASE_IDX', 'regCP_RINGID', - 'regCP_RINGID_BASE_IDX', 'regCP_RING_PRIORITY_CNTS', - 'regCP_RING_PRIORITY_CNTS_BASE_IDX', 'regCP_ROQ1_THRESHOLDS', - 'regCP_ROQ1_THRESHOLDS_BASE_IDX', 'regCP_ROQ2_AVAIL', - 'regCP_ROQ2_AVAIL_BASE_IDX', 'regCP_ROQ2_THRESHOLDS', - 'regCP_ROQ2_THRESHOLDS_BASE_IDX', 'regCP_ROQ3_THRESHOLDS', - 'regCP_ROQ3_THRESHOLDS_BASE_IDX', 'regCP_ROQ_AVAIL', - 'regCP_ROQ_AVAIL_BASE_IDX', 'regCP_ROQ_DB_STAT', - 'regCP_ROQ_DB_STAT_BASE_IDX', 'regCP_ROQ_IB1_STAT', - 'regCP_ROQ_IB1_STAT_BASE_IDX', 'regCP_ROQ_IB2_STAT', - 'regCP_ROQ_IB2_STAT_BASE_IDX', 'regCP_ROQ_RB_STAT', - 'regCP_ROQ_RB_STAT_BASE_IDX', 'regCP_SAMPLE_STATUS', - 'regCP_SAMPLE_STATUS_BASE_IDX', 'regCP_SCRATCH_DATA', - 'regCP_SCRATCH_DATA_BASE_IDX', 'regCP_SCRATCH_INDEX', - 'regCP_SCRATCH_INDEX_BASE_IDX', 'regCP_SC_PSINVOC_COUNT0_HI', - 'regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', - 'regCP_SC_PSINVOC_COUNT0_LO', - 'regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', - 'regCP_SC_PSINVOC_COUNT1_HI', - 'regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', - 'regCP_SC_PSINVOC_COUNT1_LO', - 'regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'regCP_SDMA_DMA_DONE', - 'regCP_SDMA_DMA_DONE_BASE_IDX', 'regCP_SD_CNTL', - 'regCP_SD_CNTL_BASE_IDX', 'regCP_SEM_WAIT_TIMER', - 'regCP_SEM_WAIT_TIMER_BASE_IDX', 'regCP_SIG_SEM_ADDR_HI', - 'regCP_SIG_SEM_ADDR_HI_BASE_IDX', 'regCP_SIG_SEM_ADDR_LO', - 'regCP_SIG_SEM_ADDR_LO_BASE_IDX', 'regCP_SOFT_RESET_CNTL', - 'regCP_SOFT_RESET_CNTL_BASE_IDX', 'regCP_STALLED_STAT1', - 'regCP_STALLED_STAT1_BASE_IDX', 'regCP_STALLED_STAT2', - 'regCP_STALLED_STAT2_BASE_IDX', 'regCP_STALLED_STAT3', - 'regCP_STALLED_STAT3_BASE_IDX', 'regCP_STAT', - 'regCP_STAT_BASE_IDX', 'regCP_STQ_AVAIL', - 'regCP_STQ_AVAIL_BASE_IDX', 'regCP_STQ_STAT', - 'regCP_STQ_STAT_BASE_IDX', 'regCP_STQ_THRESHOLDS', - 'regCP_STQ_THRESHOLDS_BASE_IDX', 'regCP_STQ_WR_STAT', - 'regCP_STQ_WR_STAT_BASE_IDX', 'regCP_ST_BASE_HI', - 'regCP_ST_BASE_HI_BASE_IDX', 'regCP_ST_BASE_LO', - 'regCP_ST_BASE_LO_BASE_IDX', 'regCP_ST_BUFSZ', - 'regCP_ST_BUFSZ_BASE_IDX', 'regCP_ST_CMD_BUFSZ', - 'regCP_ST_CMD_BUFSZ_BASE_IDX', 'regCP_SUSPEND_CNTL', - 'regCP_SUSPEND_CNTL_BASE_IDX', 'regCP_SUSPEND_RESUME_REQ', - 'regCP_SUSPEND_RESUME_REQ_BASE_IDX', 'regCP_VGT_ASINVOC_COUNT_HI', - 'regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_ASINVOC_COUNT_LO', - 'regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_CSINVOC_COUNT_HI', - 'regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_CSINVOC_COUNT_LO', - 'regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_DSINVOC_COUNT_HI', - 'regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_DSINVOC_COUNT_LO', - 'regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_GSINVOC_COUNT_HI', - 'regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_GSINVOC_COUNT_LO', - 'regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_GSPRIM_COUNT_HI', 'regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', - 'regCP_VGT_GSPRIM_COUNT_LO', 'regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', - 'regCP_VGT_HSINVOC_COUNT_HI', - 'regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_HSINVOC_COUNT_LO', - 'regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', - 'regCP_VGT_IAPRIM_COUNT_HI', 'regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', - 'regCP_VGT_IAPRIM_COUNT_LO', 'regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', - 'regCP_VGT_IAVERT_COUNT_HI', 'regCP_VGT_IAVERT_COUNT_HI_BASE_IDX', - 'regCP_VGT_IAVERT_COUNT_LO', 'regCP_VGT_IAVERT_COUNT_LO_BASE_IDX', - 'regCP_VGT_VSINVOC_COUNT_HI', - 'regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', - 'regCP_VGT_VSINVOC_COUNT_LO', - 'regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'regCP_VIRT_STATUS', - 'regCP_VIRT_STATUS_BASE_IDX', 'regCP_VMID', 'regCP_VMID_BASE_IDX', - 'regCP_VMID_PREEMPT', 'regCP_VMID_PREEMPT_BASE_IDX', - 'regCP_VMID_RESET', 'regCP_VMID_RESET_BASE_IDX', - 'regCP_VMID_STATUS', 'regCP_VMID_STATUS_BASE_IDX', - 'regCP_WAIT_REG_MEM_TIMEOUT', - 'regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'regCP_WAIT_SEM_ADDR_HI', - 'regCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'regCP_WAIT_SEM_ADDR_LO', - 'regCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'regDB_ALPHA_TO_MASK', - 'regDB_ALPHA_TO_MASK_BASE_IDX', 'regDB_CGTT_CLK_CTRL_0', - 'regDB_CGTT_CLK_CTRL_0_BASE_IDX', 'regDB_COUNT_CONTROL', - 'regDB_COUNT_CONTROL_BASE_IDX', 'regDB_CREDIT_LIMIT', - 'regDB_CREDIT_LIMIT_BASE_IDX', 'regDB_DEBUG', 'regDB_DEBUG2', - 'regDB_DEBUG2_BASE_IDX', 'regDB_DEBUG3', 'regDB_DEBUG3_BASE_IDX', - 'regDB_DEBUG4', 'regDB_DEBUG4_BASE_IDX', 'regDB_DEBUG5', - 'regDB_DEBUG5_BASE_IDX', 'regDB_DEBUG6', 'regDB_DEBUG6_BASE_IDX', - 'regDB_DEBUG7', 'regDB_DEBUG7_BASE_IDX', 'regDB_DEBUG_BASE_IDX', - 'regDB_DEPTH_BOUNDS_MAX', 'regDB_DEPTH_BOUNDS_MAX_BASE_IDX', - 'regDB_DEPTH_BOUNDS_MIN', 'regDB_DEPTH_BOUNDS_MIN_BASE_IDX', - 'regDB_DEPTH_CLEAR', 'regDB_DEPTH_CLEAR_BASE_IDX', - 'regDB_DEPTH_CONTROL', 'regDB_DEPTH_CONTROL_BASE_IDX', - 'regDB_DEPTH_SIZE_XY', 'regDB_DEPTH_SIZE_XY_BASE_IDX', - 'regDB_DEPTH_VIEW', 'regDB_DEPTH_VIEW_BASE_IDX', 'regDB_EQAA', - 'regDB_EQAA_BASE_IDX', 'regDB_EQUAD_STUTTER_CONTROL', - 'regDB_EQUAD_STUTTER_CONTROL_BASE_IDX', - 'regDB_ETILE_STUTTER_CONTROL', - 'regDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'regDB_EXCEPTION_CONTROL', - 'regDB_EXCEPTION_CONTROL_BASE_IDX', - 'regDB_FGCG_INTERFACES_CLK_CTRL', - 'regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX', - 'regDB_FGCG_SRAMS_CLK_CTRL', 'regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX', - 'regDB_FIFO_DEPTH1', 'regDB_FIFO_DEPTH1_BASE_IDX', - 'regDB_FIFO_DEPTH2', 'regDB_FIFO_DEPTH2_BASE_IDX', - 'regDB_FIFO_DEPTH3', 'regDB_FIFO_DEPTH3_BASE_IDX', - 'regDB_FIFO_DEPTH4', 'regDB_FIFO_DEPTH4_BASE_IDX', - 'regDB_FREE_CACHELINES', 'regDB_FREE_CACHELINES_BASE_IDX', - 'regDB_HTILE_DATA_BASE', 'regDB_HTILE_DATA_BASE_BASE_IDX', - 'regDB_HTILE_DATA_BASE_HI', 'regDB_HTILE_DATA_BASE_HI_BASE_IDX', - 'regDB_HTILE_SURFACE', 'regDB_HTILE_SURFACE_BASE_IDX', - 'regDB_LAST_OF_BURST_CONFIG', - 'regDB_LAST_OF_BURST_CONFIG_BASE_IDX', - 'regDB_LQUAD_STUTTER_CONTROL', - 'regDB_LQUAD_STUTTER_CONTROL_BASE_IDX', - 'regDB_LTILE_STUTTER_CONTROL', - 'regDB_LTILE_STUTTER_CONTROL_BASE_IDX', - 'regDB_MEM_ARB_WATERMARKS', 'regDB_MEM_ARB_WATERMARKS_BASE_IDX', - 'regDB_OCCLUSION_COUNT0_HI', 'regDB_OCCLUSION_COUNT0_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT0_LOW', - 'regDB_OCCLUSION_COUNT0_LOW_BASE_IDX', - 'regDB_OCCLUSION_COUNT1_HI', 'regDB_OCCLUSION_COUNT1_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT1_LOW', - 'regDB_OCCLUSION_COUNT1_LOW_BASE_IDX', - 'regDB_OCCLUSION_COUNT2_HI', 'regDB_OCCLUSION_COUNT2_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT2_LOW', - 'regDB_OCCLUSION_COUNT2_LOW_BASE_IDX', - 'regDB_OCCLUSION_COUNT3_HI', 'regDB_OCCLUSION_COUNT3_HI_BASE_IDX', - 'regDB_OCCLUSION_COUNT3_LOW', - 'regDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'regDB_PERFCOUNTER0_HI', - 'regDB_PERFCOUNTER0_HI_BASE_IDX', 'regDB_PERFCOUNTER0_LO', - 'regDB_PERFCOUNTER0_LO_BASE_IDX', 'regDB_PERFCOUNTER0_SELECT', - 'regDB_PERFCOUNTER0_SELECT1', - 'regDB_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regDB_PERFCOUNTER0_SELECT_BASE_IDX', 'regDB_PERFCOUNTER1_HI', - 'regDB_PERFCOUNTER1_HI_BASE_IDX', 'regDB_PERFCOUNTER1_LO', - 'regDB_PERFCOUNTER1_LO_BASE_IDX', 'regDB_PERFCOUNTER1_SELECT', - 'regDB_PERFCOUNTER1_SELECT1', - 'regDB_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regDB_PERFCOUNTER1_SELECT_BASE_IDX', 'regDB_PERFCOUNTER2_HI', - 'regDB_PERFCOUNTER2_HI_BASE_IDX', 'regDB_PERFCOUNTER2_LO', - 'regDB_PERFCOUNTER2_LO_BASE_IDX', 'regDB_PERFCOUNTER2_SELECT', - 'regDB_PERFCOUNTER2_SELECT_BASE_IDX', 'regDB_PERFCOUNTER3_HI', - 'regDB_PERFCOUNTER3_HI_BASE_IDX', 'regDB_PERFCOUNTER3_LO', - 'regDB_PERFCOUNTER3_LO_BASE_IDX', 'regDB_PERFCOUNTER3_SELECT', - 'regDB_PERFCOUNTER3_SELECT_BASE_IDX', 'regDB_PRELOAD_CONTROL', - 'regDB_PRELOAD_CONTROL_BASE_IDX', 'regDB_RENDER_CONTROL', - 'regDB_RENDER_CONTROL_BASE_IDX', 'regDB_RENDER_OVERRIDE', - 'regDB_RENDER_OVERRIDE2', 'regDB_RENDER_OVERRIDE2_BASE_IDX', - 'regDB_RENDER_OVERRIDE_BASE_IDX', 'regDB_RESERVED_REG_1', - 'regDB_RESERVED_REG_1_BASE_IDX', 'regDB_RESERVED_REG_2', - 'regDB_RESERVED_REG_2_BASE_IDX', 'regDB_RESERVED_REG_3', - 'regDB_RESERVED_REG_3_BASE_IDX', 'regDB_RING_CONTROL', - 'regDB_RING_CONTROL_BASE_IDX', 'regDB_RMI_L2_CACHE_CONTROL', - 'regDB_RMI_L2_CACHE_CONTROL_BASE_IDX', 'regDB_SHADER_CONTROL', - 'regDB_SHADER_CONTROL_BASE_IDX', 'regDB_SRESULTS_COMPARE_STATE0', - 'regDB_SRESULTS_COMPARE_STATE0_BASE_IDX', - 'regDB_SRESULTS_COMPARE_STATE1', - 'regDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'regDB_STENCILREFMASK', - 'regDB_STENCILREFMASK_BASE_IDX', 'regDB_STENCILREFMASK_BF', - 'regDB_STENCILREFMASK_BF_BASE_IDX', 'regDB_STENCIL_CLEAR', - 'regDB_STENCIL_CLEAR_BASE_IDX', 'regDB_STENCIL_CONTROL', - 'regDB_STENCIL_CONTROL_BASE_IDX', 'regDB_STENCIL_INFO', - 'regDB_STENCIL_INFO_BASE_IDX', 'regDB_STENCIL_READ_BASE', - 'regDB_STENCIL_READ_BASE_BASE_IDX', 'regDB_STENCIL_READ_BASE_HI', - 'regDB_STENCIL_READ_BASE_HI_BASE_IDX', 'regDB_STENCIL_WRITE_BASE', - 'regDB_STENCIL_WRITE_BASE_BASE_IDX', - 'regDB_STENCIL_WRITE_BASE_HI', - 'regDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'regDB_SUBTILE_CONTROL', - 'regDB_SUBTILE_CONTROL_BASE_IDX', 'regDB_WATERMARKS', - 'regDB_WATERMARKS_BASE_IDX', 'regDB_Z_INFO', - 'regDB_Z_INFO_BASE_IDX', 'regDB_Z_READ_BASE', - 'regDB_Z_READ_BASE_BASE_IDX', 'regDB_Z_READ_BASE_HI', - 'regDB_Z_READ_BASE_HI_BASE_IDX', 'regDB_Z_WRITE_BASE', - 'regDB_Z_WRITE_BASE_BASE_IDX', 'regDB_Z_WRITE_BASE_HI', - 'regDB_Z_WRITE_BASE_HI_BASE_IDX', 'regDIDT_EDC_CTRL', - 'regDIDT_EDC_CTRL_BASE_IDX', 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO', - 'regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX', - 'regDIDT_EDC_OVERFLOW', 'regDIDT_EDC_OVERFLOW_BASE_IDX', - 'regDIDT_EDC_ROLLING_POWER_DELTA', - 'regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_1_2', - 'regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_3_4', - 'regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_5_6', - 'regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX', - 'regDIDT_EDC_STALL_PATTERN_7', - 'regDIDT_EDC_STALL_PATTERN_7_BASE_IDX', 'regDIDT_EDC_STATUS', - 'regDIDT_EDC_STATUS_BASE_IDX', 'regDIDT_EDC_THRESHOLD', - 'regDIDT_EDC_THRESHOLD_BASE_IDX', 'regDIDT_EDC_THROTTLE_CTRL', - 'regDIDT_EDC_THROTTLE_CTRL_BASE_IDX', - 'regDIDT_INDEX_AUTO_INCR_EN', - 'regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'regDIDT_IND_DATA', - 'regDIDT_IND_DATA_BASE_IDX', 'regDIDT_IND_INDEX', - 'regDIDT_IND_INDEX_BASE_IDX', 'regDIDT_STALL_PATTERN_1_2', - 'regDIDT_STALL_PATTERN_1_2_BASE_IDX', 'regDIDT_STALL_PATTERN_3_4', - 'regDIDT_STALL_PATTERN_3_4_BASE_IDX', 'regDIDT_STALL_PATTERN_5_6', - 'regDIDT_STALL_PATTERN_5_6_BASE_IDX', 'regDIDT_STALL_PATTERN_7', - 'regDIDT_STALL_PATTERN_7_BASE_IDX', 'regDIDT_STALL_PATTERN_CTRL', - 'regDIDT_STALL_PATTERN_CTRL_BASE_IDX', 'regEDC_HYSTERESIS_CNTL', - 'regEDC_HYSTERESIS_CNTL_BASE_IDX', 'regEDC_HYSTERESIS_STAT', - 'regEDC_HYSTERESIS_STAT_BASE_IDX', 'regEDC_PERF_COUNTER', - 'regEDC_PERF_COUNTER_BASE_IDX', 'regEDC_STRETCH_NUM_PERF_COUNTER', - 'regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX', - 'regEDC_STRETCH_PERF_COUNTER', - 'regEDC_STRETCH_PERF_COUNTER_BASE_IDX', - 'regEDC_UNSTRETCH_PERF_COUNTER', - 'regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX', 'regGB_ADDR_CONFIG', - 'regGB_ADDR_CONFIG_BASE_IDX', 'regGB_ADDR_CONFIG_READ', - 'regGB_ADDR_CONFIG_READ_BASE_IDX', 'regGB_BACKEND_MAP', - 'regGB_BACKEND_MAP_BASE_IDX', 'regGB_EDC_MODE', - 'regGB_EDC_MODE_BASE_IDX', 'regGB_GPU_ID', - 'regGB_GPU_ID_BASE_IDX', 'regGCEA_DRAM_PAGE_BURST', - 'regGCEA_DRAM_PAGE_BURST_BASE_IDX', 'regGCEA_DRAM_RD_CAM_CNTL', - 'regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX', - 'regGCEA_DRAM_RD_CLI2GRP_MAP0', - 'regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_DRAM_RD_CLI2GRP_MAP1', - 'regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_DRAM_RD_GRP2VC_MAP', - 'regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_RD_LAZY', - 'regGCEA_DRAM_RD_LAZY_BASE_IDX', 'regGCEA_DRAM_RD_PRI_AGE', - 'regGCEA_DRAM_RD_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_RD_PRI_FIXED', - 'regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI1', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI2', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI3', - 'regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_QUEUING', - 'regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX', - 'regGCEA_DRAM_RD_PRI_URGENCY', - 'regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', - 'regGCEA_DRAM_WR_CAM_CNTL', 'regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', - 'regGCEA_DRAM_WR_CLI2GRP_MAP0', - 'regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_DRAM_WR_CLI2GRP_MAP1', - 'regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_DRAM_WR_GRP2VC_MAP', - 'regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', 'regGCEA_DRAM_WR_LAZY', - 'regGCEA_DRAM_WR_LAZY_BASE_IDX', 'regGCEA_DRAM_WR_PRI_AGE', - 'regGCEA_DRAM_WR_PRI_AGE_BASE_IDX', 'regGCEA_DRAM_WR_PRI_FIXED', - 'regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI1', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI2', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI3', - 'regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_QUEUING', - 'regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX', - 'regGCEA_DRAM_WR_PRI_URGENCY', - 'regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'regGCEA_DSM_CNTL', - 'regGCEA_DSM_CNTL2', 'regGCEA_DSM_CNTL2A', - 'regGCEA_DSM_CNTL2A_BASE_IDX', 'regGCEA_DSM_CNTL2B', - 'regGCEA_DSM_CNTL2B_BASE_IDX', 'regGCEA_DSM_CNTL2_BASE_IDX', - 'regGCEA_DSM_CNTLA', 'regGCEA_DSM_CNTLA_BASE_IDX', - 'regGCEA_DSM_CNTLB', 'regGCEA_DSM_CNTLB_BASE_IDX', - 'regGCEA_DSM_CNTL_BASE_IDX', 'regGCEA_EDC_CNT', - 'regGCEA_EDC_CNT2', 'regGCEA_EDC_CNT2_BASE_IDX', - 'regGCEA_EDC_CNT3', 'regGCEA_EDC_CNT3_BASE_IDX', - 'regGCEA_EDC_CNT_BASE_IDX', 'regGCEA_ERR_STATUS', - 'regGCEA_ERR_STATUS_BASE_IDX', 'regGCEA_GL2C_XBR_CREDITS', - 'regGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'regGCEA_GL2C_XBR_MAXBURST', - 'regGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'regGCEA_ICG_CTRL', - 'regGCEA_ICG_CTRL_BASE_IDX', 'regGCEA_IO_GROUP_BURST', - 'regGCEA_IO_GROUP_BURST_BASE_IDX', 'regGCEA_IO_RD_CLI2GRP_MAP0', - 'regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_IO_RD_CLI2GRP_MAP1', - 'regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_IO_RD_COMBINE_FLUSH', - 'regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_RD_PRI_AGE', - 'regGCEA_IO_RD_PRI_AGE_BASE_IDX', 'regGCEA_IO_RD_PRI_FIXED', - 'regGCEA_IO_RD_PRI_FIXED_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUANT_PRI1', - 'regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUANT_PRI2', - 'regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUANT_PRI3', - 'regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_IO_RD_PRI_QUEUING', 'regGCEA_IO_RD_PRI_QUEUING_BASE_IDX', - 'regGCEA_IO_RD_PRI_URGENCY', 'regGCEA_IO_RD_PRI_URGENCY_BASE_IDX', - 'regGCEA_IO_RD_PRI_URGENCY_MASKING', - 'regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX', - 'regGCEA_IO_WR_CLI2GRP_MAP0', - 'regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX', - 'regGCEA_IO_WR_CLI2GRP_MAP1', - 'regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX', - 'regGCEA_IO_WR_COMBINE_FLUSH', - 'regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'regGCEA_IO_WR_PRI_AGE', - 'regGCEA_IO_WR_PRI_AGE_BASE_IDX', 'regGCEA_IO_WR_PRI_FIXED', - 'regGCEA_IO_WR_PRI_FIXED_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUANT_PRI1', - 'regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUANT_PRI2', - 'regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUANT_PRI3', - 'regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX', - 'regGCEA_IO_WR_PRI_QUEUING', 'regGCEA_IO_WR_PRI_QUEUING_BASE_IDX', - 'regGCEA_IO_WR_PRI_URGENCY', 'regGCEA_IO_WR_PRI_URGENCY_BASE_IDX', - 'regGCEA_IO_WR_PRI_URGENCY_MASKING', - 'regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX', - 'regGCEA_LATENCY_SAMPLING', 'regGCEA_LATENCY_SAMPLING_BASE_IDX', - 'regGCEA_MAM_CTRL', 'regGCEA_MAM_CTRL2', - 'regGCEA_MAM_CTRL2_BASE_IDX', 'regGCEA_MAM_CTRL_BASE_IDX', - 'regGCEA_MISC', 'regGCEA_MISC2', 'regGCEA_MISC2_BASE_IDX', - 'regGCEA_MISC_BASE_IDX', 'regGCEA_PERFCOUNTER0_CFG', - 'regGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER1_CFG', - 'regGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'regGCEA_PERFCOUNTER2_HI', - 'regGCEA_PERFCOUNTER2_HI_BASE_IDX', 'regGCEA_PERFCOUNTER2_LO', - 'regGCEA_PERFCOUNTER2_LO_BASE_IDX', 'regGCEA_PERFCOUNTER2_MODE', - 'regGCEA_PERFCOUNTER2_MODE_BASE_IDX', - 'regGCEA_PERFCOUNTER2_SELECT', 'regGCEA_PERFCOUNTER2_SELECT1', - 'regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'regGCEA_PERFCOUNTER_HI', - 'regGCEA_PERFCOUNTER_HI_BASE_IDX', 'regGCEA_PERFCOUNTER_LO', - 'regGCEA_PERFCOUNTER_LO_BASE_IDX', - 'regGCEA_PERFCOUNTER_RSLT_CNTL', - 'regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGCEA_PROBE_CNTL', - 'regGCEA_PROBE_CNTL_BASE_IDX', 'regGCEA_PROBE_MAP', - 'regGCEA_PROBE_MAP_BASE_IDX', 'regGCEA_RRET_MEM_RESERVE', - 'regGCEA_RRET_MEM_RESERVE_BASE_IDX', 'regGCEA_SDP_ARB_FINAL', - 'regGCEA_SDP_ARB_FINAL_BASE_IDX', 'regGCEA_SDP_CREDITS', - 'regGCEA_SDP_CREDITS_BASE_IDX', 'regGCEA_SDP_ENABLE', - 'regGCEA_SDP_ENABLE_BASE_IDX', 'regGCEA_SDP_IO_PRIORITY', - 'regGCEA_SDP_IO_PRIORITY_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE0', - 'regGCEA_SDP_TAG_RESERVE0_BASE_IDX', 'regGCEA_SDP_TAG_RESERVE1', - 'regGCEA_SDP_TAG_RESERVE1_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE0', - 'regGCEA_SDP_VCC_RESERVE0_BASE_IDX', 'regGCEA_SDP_VCC_RESERVE1', - 'regGCEA_SDP_VCC_RESERVE1_BASE_IDX', 'regGCMC_MEM_POWER_LS', - 'regGCMC_MEM_POWER_LS_BASE_IDX', 'regGCMC_VM_AGP_BASE', - 'regGCMC_VM_AGP_BASE_BASE_IDX', 'regGCMC_VM_AGP_BOT', - 'regGCMC_VM_AGP_BOT_BASE_IDX', 'regGCMC_VM_AGP_TOP', - 'regGCMC_VM_AGP_TOP_BASE_IDX', 'regGCMC_VM_APT_CNTL', - 'regGCMC_VM_APT_CNTL_BASE_IDX', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START', - 'regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', - 'regGCMC_VM_FB_LOCATION_BASE', - 'regGCMC_VM_FB_LOCATION_BASE_BASE_IDX', - 'regGCMC_VM_FB_LOCATION_TOP', - 'regGCMC_VM_FB_LOCATION_TOP_BASE_IDX', - 'regGCMC_VM_FB_NOALLOC_CNTL', - 'regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regGCMC_VM_FB_OFFSET', - 'regGCMC_VM_FB_OFFSET_BASE_IDX', 'regGCMC_VM_FB_SIZE_OFFSET_VF0', - 'regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF1', 'regGCMC_VM_FB_SIZE_OFFSET_VF10', - 'regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF11', - 'regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF12', - 'regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF13', - 'regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF14', - 'regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF15', - 'regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF2', - 'regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF3', - 'regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF4', - 'regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF5', - 'regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF6', - 'regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF7', - 'regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF8', - 'regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', - 'regGCMC_VM_FB_SIZE_OFFSET_VF9', - 'regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER0_CFG', - 'regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER1_CFG', - 'regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER2_CFG', - 'regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER3_CFG', - 'regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER4_CFG', - 'regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER5_CFG', - 'regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER6_CFG', - 'regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER7_CFG', - 'regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER_HI', - 'regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER_LO', - 'regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', - 'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL', - 'regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regGCMC_VM_LOCAL_FB_ADDRESS_END', - 'regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX', - 'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL', - 'regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX', - 'regGCMC_VM_LOCAL_FB_ADDRESS_START', - 'regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START', - 'regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_0', 'regGCMC_VM_MARC_BASE_HI_0_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_1', 'regGCMC_VM_MARC_BASE_HI_10', - 'regGCMC_VM_MARC_BASE_HI_10_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_11', - 'regGCMC_VM_MARC_BASE_HI_11_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_12', - 'regGCMC_VM_MARC_BASE_HI_12_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_13', - 'regGCMC_VM_MARC_BASE_HI_13_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_14', - 'regGCMC_VM_MARC_BASE_HI_14_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_15', - 'regGCMC_VM_MARC_BASE_HI_15_BASE_IDX', - 'regGCMC_VM_MARC_BASE_HI_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_2', - 'regGCMC_VM_MARC_BASE_HI_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_3', - 'regGCMC_VM_MARC_BASE_HI_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_4', - 'regGCMC_VM_MARC_BASE_HI_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_5', - 'regGCMC_VM_MARC_BASE_HI_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_6', - 'regGCMC_VM_MARC_BASE_HI_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_7', - 'regGCMC_VM_MARC_BASE_HI_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_8', - 'regGCMC_VM_MARC_BASE_HI_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_HI_9', - 'regGCMC_VM_MARC_BASE_HI_9_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_0', - 'regGCMC_VM_MARC_BASE_LO_0_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_1', - 'regGCMC_VM_MARC_BASE_LO_10', - 'regGCMC_VM_MARC_BASE_LO_10_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_11', - 'regGCMC_VM_MARC_BASE_LO_11_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_12', - 'regGCMC_VM_MARC_BASE_LO_12_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_13', - 'regGCMC_VM_MARC_BASE_LO_13_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_14', - 'regGCMC_VM_MARC_BASE_LO_14_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_15', - 'regGCMC_VM_MARC_BASE_LO_15_BASE_IDX', - 'regGCMC_VM_MARC_BASE_LO_1_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_2', - 'regGCMC_VM_MARC_BASE_LO_2_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_3', - 'regGCMC_VM_MARC_BASE_LO_3_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_4', - 'regGCMC_VM_MARC_BASE_LO_4_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_5', - 'regGCMC_VM_MARC_BASE_LO_5_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_6', - 'regGCMC_VM_MARC_BASE_LO_6_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_7', - 'regGCMC_VM_MARC_BASE_LO_7_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_8', - 'regGCMC_VM_MARC_BASE_LO_8_BASE_IDX', 'regGCMC_VM_MARC_BASE_LO_9', - 'regGCMC_VM_MARC_BASE_LO_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_0', - 'regGCMC_VM_MARC_LEN_HI_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_1', - 'regGCMC_VM_MARC_LEN_HI_10', 'regGCMC_VM_MARC_LEN_HI_10_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_11', 'regGCMC_VM_MARC_LEN_HI_11_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_12', 'regGCMC_VM_MARC_LEN_HI_12_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_13', 'regGCMC_VM_MARC_LEN_HI_13_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_14', 'regGCMC_VM_MARC_LEN_HI_14_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_15', 'regGCMC_VM_MARC_LEN_HI_15_BASE_IDX', - 'regGCMC_VM_MARC_LEN_HI_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_2', - 'regGCMC_VM_MARC_LEN_HI_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_3', - 'regGCMC_VM_MARC_LEN_HI_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_4', - 'regGCMC_VM_MARC_LEN_HI_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_5', - 'regGCMC_VM_MARC_LEN_HI_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_6', - 'regGCMC_VM_MARC_LEN_HI_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_7', - 'regGCMC_VM_MARC_LEN_HI_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_8', - 'regGCMC_VM_MARC_LEN_HI_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_HI_9', - 'regGCMC_VM_MARC_LEN_HI_9_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_0', - 'regGCMC_VM_MARC_LEN_LO_0_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_1', - 'regGCMC_VM_MARC_LEN_LO_10', 'regGCMC_VM_MARC_LEN_LO_10_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_11', 'regGCMC_VM_MARC_LEN_LO_11_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_12', 'regGCMC_VM_MARC_LEN_LO_12_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_13', 'regGCMC_VM_MARC_LEN_LO_13_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_14', 'regGCMC_VM_MARC_LEN_LO_14_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_15', 'regGCMC_VM_MARC_LEN_LO_15_BASE_IDX', - 'regGCMC_VM_MARC_LEN_LO_1_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_2', - 'regGCMC_VM_MARC_LEN_LO_2_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_3', - 'regGCMC_VM_MARC_LEN_LO_3_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_4', - 'regGCMC_VM_MARC_LEN_LO_4_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_5', - 'regGCMC_VM_MARC_LEN_LO_5_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_6', - 'regGCMC_VM_MARC_LEN_LO_6_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_7', - 'regGCMC_VM_MARC_LEN_LO_7_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_8', - 'regGCMC_VM_MARC_LEN_LO_8_BASE_IDX', 'regGCMC_VM_MARC_LEN_LO_9', - 'regGCMC_VM_MARC_LEN_LO_9_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_0', - 'regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_1', - 'regGCMC_VM_MARC_PFVF_MAPPING_10', - 'regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_11', - 'regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_12', - 'regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_13', - 'regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_14', - 'regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_15', - 'regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_2', - 'regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_3', - 'regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_4', - 'regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_5', - 'regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_6', - 'regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_7', - 'regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_8', - 'regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX', - 'regGCMC_VM_MARC_PFVF_MAPPING_9', - 'regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_0', - 'regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_1', 'regGCMC_VM_MARC_RELOC_HI_10', - 'regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_11', - 'regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_12', - 'regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_13', - 'regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_14', - 'regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_15', - 'regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_2', - 'regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_3', - 'regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_4', - 'regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_5', - 'regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_6', - 'regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_7', - 'regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_8', - 'regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_HI_9', - 'regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_0', - 'regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_1', 'regGCMC_VM_MARC_RELOC_LO_10', - 'regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_11', - 'regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_12', - 'regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_13', - 'regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_14', - 'regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_15', - 'regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_2', - 'regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_3', - 'regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_4', - 'regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_5', - 'regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_6', - 'regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_7', - 'regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_8', - 'regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX', - 'regGCMC_VM_MARC_RELOC_LO_9', - 'regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX', - 'regGCMC_VM_MX_L1_TLB_CNTL', 'regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX', - 'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2', - 'regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX', - 'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1', - 'regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX', - 'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2', - 'regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', - 'regGCMC_VM_STEERING', 'regGCMC_VM_STEERING_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', - 'regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR', - 'regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', - 'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR', - 'regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', - 'regGCRD_CREDIT_SAFE', 'regGCRD_CREDIT_SAFE_BASE_IDX', - 'regGCRD_SA0_TARGETS_DISABLE', - 'regGCRD_SA0_TARGETS_DISABLE_BASE_IDX', - 'regGCRD_SA1_TARGETS_DISABLE', - 'regGCRD_SA1_TARGETS_DISABLE_BASE_IDX', 'regGCR_CMD_STATUS', - 'regGCR_CMD_STATUS_BASE_IDX', 'regGCR_GENERAL_CNTL', - 'regGCR_GENERAL_CNTL_BASE_IDX', 'regGCR_PERFCOUNTER0_HI', - 'regGCR_PERFCOUNTER0_HI_BASE_IDX', 'regGCR_PERFCOUNTER0_LO', - 'regGCR_PERFCOUNTER0_LO_BASE_IDX', 'regGCR_PERFCOUNTER0_SELECT', - 'regGCR_PERFCOUNTER0_SELECT1', - 'regGCR_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'regGCR_PERFCOUNTER1_HI', - 'regGCR_PERFCOUNTER1_HI_BASE_IDX', 'regGCR_PERFCOUNTER1_LO', - 'regGCR_PERFCOUNTER1_LO_BASE_IDX', 'regGCR_PERFCOUNTER1_SELECT', - 'regGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'regGCR_PIO_CNTL', - 'regGCR_PIO_CNTL_BASE_IDX', 'regGCR_PIO_DATA', - 'regGCR_PIO_DATA_BASE_IDX', 'regGCR_SPARE', - 'regGCR_SPARE_BASE_IDX', 'regGCUTCL2_CGTT_BUSY_CTRL', - 'regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC', - 'regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX', - 'regGCUTCL2_GROUP_RET_FAULT_STATUS', - 'regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX', - 'regGCUTCL2_HARVEST_BYPASS_GROUPS', - 'regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', - 'regGCUTCL2_ICG_CTRL', 'regGCUTCL2_ICG_CTRL_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER0_CFG', - 'regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER1_CFG', - 'regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER2_CFG', - 'regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER3_CFG', - 'regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER_HI', 'regGCUTCL2_PERFCOUNTER_HI_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER_LO', 'regGCUTCL2_PERFCOUNTER_LO_BASE_IDX', - 'regGCUTCL2_PERFCOUNTER_RSLT_CNTL', - 'regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID', - 'regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', - 'regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', - 'regGCUTC_TRANSLATION_FAULT_CNTL0', - 'regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX', - 'regGCUTC_TRANSLATION_FAULT_CNTL1', - 'regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX', - 'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT', - 'regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_HI', - 'regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_LO', - 'regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_MODE', - 'regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_SELECT', - 'regGCVML2_PERFCOUNTER2_0_SELECT1', - 'regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_HI', - 'regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_LO', - 'regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_MODE', - 'regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_SELECT', - 'regGCVML2_PERFCOUNTER2_1_SELECT1', - 'regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX', - 'regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX', - 'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ', - 'regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX', - 'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT', - 'regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX', - 'regGCVML2_WALKER_MACRO_THROTTLE_TIME', - 'regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX', - 'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT', - 'regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX', - 'regGCVML2_WALKER_MICRO_THROTTLE_TIME', - 'regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX', - 'regGCVM_CONTEXT0_CNTL', 'regGCVM_CONTEXT0_CNTL_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT10_CNTL', 'regGCVM_CONTEXT10_CNTL_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT11_CNTL', 'regGCVM_CONTEXT11_CNTL_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT12_CNTL', 'regGCVM_CONTEXT12_CNTL_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT13_CNTL', 'regGCVM_CONTEXT13_CNTL_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT14_CNTL', 'regGCVM_CONTEXT14_CNTL_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT15_CNTL', 'regGCVM_CONTEXT15_CNTL_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT1_CNTL', 'regGCVM_CONTEXT1_CNTL_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT2_CNTL', 'regGCVM_CONTEXT2_CNTL_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT3_CNTL', 'regGCVM_CONTEXT3_CNTL_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT4_CNTL', 'regGCVM_CONTEXT4_CNTL_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT5_CNTL', 'regGCVM_CONTEXT5_CNTL_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT6_CNTL', 'regGCVM_CONTEXT6_CNTL_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT7_CNTL', 'regGCVM_CONTEXT7_CNTL_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT8_CNTL', 'regGCVM_CONTEXT8_CNTL_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT9_CNTL', 'regGCVM_CONTEXT9_CNTL_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', - 'regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', - 'regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', - 'regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', - 'regGCVM_CONTEXTS_DISABLE', 'regGCVM_CONTEXTS_DISABLE_BASE_IDX', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32', - 'regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', - 'regGCVM_DUMMY_PAGE_FAULT_CNTL', - 'regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', - 'regGCVM_INVALIDATE_CNTL', 'regGCVM_INVALIDATE_CNTL_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_ACK', - 'regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_REQ', - 'regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG0_SEM', - 'regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_ACK', - 'regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_REQ', - 'regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG10_SEM', - 'regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_ACK', - 'regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_REQ', - 'regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG11_SEM', - 'regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_ACK', - 'regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_REQ', - 'regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG12_SEM', - 'regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_ACK', - 'regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_REQ', - 'regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG13_SEM', - 'regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_ACK', - 'regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_REQ', - 'regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG14_SEM', - 'regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_ACK', - 'regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_REQ', - 'regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG15_SEM', - 'regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_ACK', - 'regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_REQ', - 'regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG16_SEM', - 'regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_ACK', - 'regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_REQ', - 'regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG17_SEM', - 'regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_ACK', - 'regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_REQ', - 'regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG1_SEM', - 'regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_ACK', - 'regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_REQ', - 'regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG2_SEM', - 'regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_ACK', - 'regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_REQ', - 'regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG3_SEM', - 'regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_ACK', - 'regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_REQ', - 'regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG4_SEM', - 'regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_ACK', - 'regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_REQ', - 'regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG5_SEM', - 'regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_ACK', - 'regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_REQ', - 'regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG6_SEM', - 'regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_ACK', - 'regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_REQ', - 'regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG7_SEM', - 'regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_ACK', - 'regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_REQ', - 'regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG8_SEM', - 'regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_ACK', - 'regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', - 'regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_REQ', - 'regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX', - 'regGCVM_INVALIDATE_ENG9_SEM', - 'regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX', - 'regGCVM_L2_BANK_SELECT_MASKS', - 'regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID2', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', - 'regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', - 'regGCVM_L2_CACHE_PARITY_CNTL', - 'regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX', - 'regGCVM_L2_CGTT_BUSY_CTRL', 'regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX', - 'regGCVM_L2_CNTL', 'regGCVM_L2_CNTL2', - 'regGCVM_L2_CNTL2_BASE_IDX', 'regGCVM_L2_CNTL3', - 'regGCVM_L2_CNTL3_BASE_IDX', 'regGCVM_L2_CNTL4', - 'regGCVM_L2_CNTL4_BASE_IDX', 'regGCVM_L2_CNTL5', - 'regGCVM_L2_CNTL5_BASE_IDX', 'regGCVM_L2_CNTL_BASE_IDX', - 'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', - 'regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', - 'regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', - 'regGCVM_L2_GCR_CNTL', 'regGCVM_L2_GCR_CNTL_BASE_IDX', - 'regGCVM_L2_ICG_CTRL', 'regGCVM_L2_ICG_CTRL_BASE_IDX', - 'regGCVM_L2_MM_GROUP_RT_CLASSES', - 'regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', - 'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', - 'regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32', - 'regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_CNTL', - 'regGCVM_L2_PROTECTION_FAULT_CNTL2', - 'regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', - 'regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4', - 'regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', - 'regGCVM_L2_PROTECTION_FAULT_STATUS', - 'regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', - 'regGCVM_L2_PTE_CACHE_DUMP_CNTL', - 'regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', - 'regGCVM_L2_PTE_CACHE_DUMP_READ', - 'regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regGCVM_L2_STATUS', - 'regGCVM_L2_STATUS_BASE_IDX', 'regGC_CAC_AGGR_GFXCLK_CYCLE', - 'regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regGC_CAC_AGGR_LOWER', - 'regGC_CAC_AGGR_LOWER_BASE_IDX', 'regGC_CAC_AGGR_UPPER', - 'regGC_CAC_AGGR_UPPER_BASE_IDX', 'regGC_CAC_CTRL_1', - 'regGC_CAC_CTRL_1_BASE_IDX', 'regGC_CAC_CTRL_2', - 'regGC_CAC_CTRL_2_BASE_IDX', 'regGC_CAC_IND_DATA', - 'regGC_CAC_IND_DATA_BASE_IDX', 'regGC_CAC_IND_INDEX', - 'regGC_CAC_IND_INDEX_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_0', - 'regGC_CAC_WEIGHT_CHC_0_BASE_IDX', 'regGC_CAC_WEIGHT_CHC_1', - 'regGC_CAC_WEIGHT_CHC_1_BASE_IDX', 'regGC_CAC_WEIGHT_CP_0', - 'regGC_CAC_WEIGHT_CP_0_BASE_IDX', 'regGC_CAC_WEIGHT_CP_1', - 'regGC_CAC_WEIGHT_CP_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_0', - 'regGC_CAC_WEIGHT_EA_0_BASE_IDX', 'regGC_CAC_WEIGHT_EA_1', - 'regGC_CAC_WEIGHT_EA_1_BASE_IDX', 'regGC_CAC_WEIGHT_EA_2', - 'regGC_CAC_WEIGHT_EA_2_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_0', - 'regGC_CAC_WEIGHT_GDS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_1', - 'regGC_CAC_WEIGHT_GDS_1_BASE_IDX', 'regGC_CAC_WEIGHT_GDS_2', - 'regGC_CAC_WEIGHT_GDS_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_0', - 'regGC_CAC_WEIGHT_GE_0_BASE_IDX', 'regGC_CAC_WEIGHT_GE_1', - 'regGC_CAC_WEIGHT_GE_1_BASE_IDX', 'regGC_CAC_WEIGHT_GE_2', - 'regGC_CAC_WEIGHT_GE_2_BASE_IDX', 'regGC_CAC_WEIGHT_GE_3', - 'regGC_CAC_WEIGHT_GE_3_BASE_IDX', 'regGC_CAC_WEIGHT_GE_4', - 'regGC_CAC_WEIGHT_GE_4_BASE_IDX', 'regGC_CAC_WEIGHT_GE_5', - 'regGC_CAC_WEIGHT_GE_5_BASE_IDX', 'regGC_CAC_WEIGHT_GE_6', - 'regGC_CAC_WEIGHT_GE_6_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_0', - 'regGC_CAC_WEIGHT_GL2C_0_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_1', - 'regGC_CAC_WEIGHT_GL2C_1_BASE_IDX', 'regGC_CAC_WEIGHT_GL2C_2', - 'regGC_CAC_WEIGHT_GL2C_2_BASE_IDX', 'regGC_CAC_WEIGHT_GRBM_0', - 'regGC_CAC_WEIGHT_GRBM_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_0', - 'regGC_CAC_WEIGHT_GUS_0_BASE_IDX', 'regGC_CAC_WEIGHT_GUS_1', - 'regGC_CAC_WEIGHT_GUS_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_0', - 'regGC_CAC_WEIGHT_PH_0_BASE_IDX', 'regGC_CAC_WEIGHT_PH_1', - 'regGC_CAC_WEIGHT_PH_1_BASE_IDX', 'regGC_CAC_WEIGHT_PH_2', - 'regGC_CAC_WEIGHT_PH_2_BASE_IDX', 'regGC_CAC_WEIGHT_PH_3', - 'regGC_CAC_WEIGHT_PH_3_BASE_IDX', 'regGC_CAC_WEIGHT_PMM_0', - 'regGC_CAC_WEIGHT_PMM_0_BASE_IDX', 'regGC_CAC_WEIGHT_RLC_0', - 'regGC_CAC_WEIGHT_RLC_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_0', - 'regGC_CAC_WEIGHT_SDMA_0_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_1', - 'regGC_CAC_WEIGHT_SDMA_1_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_2', - 'regGC_CAC_WEIGHT_SDMA_2_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_3', - 'regGC_CAC_WEIGHT_SDMA_3_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_4', - 'regGC_CAC_WEIGHT_SDMA_4_BASE_IDX', 'regGC_CAC_WEIGHT_SDMA_5', - 'regGC_CAC_WEIGHT_SDMA_5_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_0', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_1', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_2', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_3', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_4', - 'regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_VML2_0', - 'regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_VML2_1', - 'regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_VML2_2', - 'regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_0', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_1', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_2', - 'regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX', - 'regGC_EDC_CLK_MONITOR_CTRL', - 'regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX', 'regGC_EDC_CTRL', - 'regGC_EDC_CTRL_BASE_IDX', 'regGC_EDC_OVERFLOW', - 'regGC_EDC_OVERFLOW_BASE_IDX', 'regGC_EDC_ROLLING_POWER_DELTA', - 'regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'regGC_EDC_STATUS', - 'regGC_EDC_STATUS_BASE_IDX', 'regGC_EDC_STRETCH_CTRL', - 'regGC_EDC_STRETCH_CTRL_BASE_IDX', 'regGC_EDC_STRETCH_THRESHOLD', - 'regGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'regGC_EDC_THRESHOLD', - 'regGC_EDC_THRESHOLD_BASE_IDX', 'regGC_IH_COOKIE_0_PTR', - 'regGC_IH_COOKIE_0_PTR_BASE_IDX', 'regGC_THROTTLE_CTRL', - 'regGC_THROTTLE_CTRL1', 'regGC_THROTTLE_CTRL1_BASE_IDX', - 'regGC_THROTTLE_CTRL_BASE_IDX', 'regGC_THROTTLE_STATUS', - 'regGC_THROTTLE_STATUS_BASE_IDX', 'regGC_USER_PRIM_CONFIG', - 'regGC_USER_PRIM_CONFIG_BASE_IDX', - 'regGC_USER_RB_BACKEND_DISABLE', - 'regGC_USER_RB_BACKEND_DISABLE_BASE_IDX', - 'regGC_USER_RB_REDUNDANCY', 'regGC_USER_RB_REDUNDANCY_BASE_IDX', - 'regGC_USER_RMI_REDUNDANCY', 'regGC_USER_RMI_REDUNDANCY_BASE_IDX', - 'regGC_USER_SA_UNIT_DISABLE', - 'regGC_USER_SA_UNIT_DISABLE_BASE_IDX', - 'regGC_USER_SHADER_ARRAY_CONFIG', - 'regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX', - 'regGC_USER_SHADER_RATE_CONFIG', - 'regGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'regGDS_ATOM_BASE', - 'regGDS_ATOM_BASE_BASE_IDX', 'regGDS_ATOM_CNTL', - 'regGDS_ATOM_CNTL_BASE_IDX', 'regGDS_ATOM_COMPLETE', - 'regGDS_ATOM_COMPLETE_BASE_IDX', 'regGDS_ATOM_DST', - 'regGDS_ATOM_DST_BASE_IDX', 'regGDS_ATOM_OFFSET0', - 'regGDS_ATOM_OFFSET0_BASE_IDX', 'regGDS_ATOM_OFFSET1', - 'regGDS_ATOM_OFFSET1_BASE_IDX', 'regGDS_ATOM_OP', - 'regGDS_ATOM_OP_BASE_IDX', 'regGDS_ATOM_READ0', - 'regGDS_ATOM_READ0_BASE_IDX', 'regGDS_ATOM_READ0_U', - 'regGDS_ATOM_READ0_U_BASE_IDX', 'regGDS_ATOM_READ1', - 'regGDS_ATOM_READ1_BASE_IDX', 'regGDS_ATOM_READ1_U', - 'regGDS_ATOM_READ1_U_BASE_IDX', 'regGDS_ATOM_SIZE', - 'regGDS_ATOM_SIZE_BASE_IDX', 'regGDS_ATOM_SRC0', - 'regGDS_ATOM_SRC0_BASE_IDX', 'regGDS_ATOM_SRC0_U', - 'regGDS_ATOM_SRC0_U_BASE_IDX', 'regGDS_ATOM_SRC1', - 'regGDS_ATOM_SRC1_BASE_IDX', 'regGDS_ATOM_SRC1_U', - 'regGDS_ATOM_SRC1_U_BASE_IDX', 'regGDS_CNTL_STATUS', - 'regGDS_CNTL_STATUS_BASE_IDX', 'regGDS_COMPUTE_MAX_WAVE_ID', - 'regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'regGDS_CONFIG', - 'regGDS_CONFIG_BASE_IDX', 'regGDS_CS_CTXSW_CNT0', - 'regGDS_CS_CTXSW_CNT0_BASE_IDX', 'regGDS_CS_CTXSW_CNT1', - 'regGDS_CS_CTXSW_CNT1_BASE_IDX', 'regGDS_CS_CTXSW_CNT2', - 'regGDS_CS_CTXSW_CNT2_BASE_IDX', 'regGDS_CS_CTXSW_CNT3', - 'regGDS_CS_CTXSW_CNT3_BASE_IDX', 'regGDS_CS_CTXSW_STATUS', - 'regGDS_CS_CTXSW_STATUS_BASE_IDX', 'regGDS_DSM_CNTL', - 'regGDS_DSM_CNTL2', 'regGDS_DSM_CNTL2_BASE_IDX', - 'regGDS_DSM_CNTL_BASE_IDX', 'regGDS_EDC_CNT', - 'regGDS_EDC_CNT_BASE_IDX', 'regGDS_EDC_GRBM_CNT', - 'regGDS_EDC_GRBM_CNT_BASE_IDX', 'regGDS_EDC_OA_DED', - 'regGDS_EDC_OA_DED_BASE_IDX', 'regGDS_EDC_OA_PHY_CNT', - 'regGDS_EDC_OA_PHY_CNT_BASE_IDX', 'regGDS_EDC_OA_PIPE_CNT', - 'regGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'regGDS_ENHANCE', - 'regGDS_ENHANCE2', 'regGDS_ENHANCE2_BASE_IDX', - 'regGDS_ENHANCE_BASE_IDX', 'regGDS_GFX_CTXSW_STATUS', - 'regGDS_GFX_CTXSW_STATUS_BASE_IDX', 'regGDS_GS_0', - 'regGDS_GS_0_BASE_IDX', 'regGDS_GS_1', 'regGDS_GS_1_BASE_IDX', - 'regGDS_GS_2', 'regGDS_GS_2_BASE_IDX', 'regGDS_GS_3', - 'regGDS_GS_3_BASE_IDX', 'regGDS_GS_CTXSW_CNT0', - 'regGDS_GS_CTXSW_CNT0_BASE_IDX', 'regGDS_GS_CTXSW_CNT1', - 'regGDS_GS_CTXSW_CNT1_BASE_IDX', 'regGDS_GS_CTXSW_CNT2', - 'regGDS_GS_CTXSW_CNT2_BASE_IDX', 'regGDS_GS_CTXSW_CNT3', - 'regGDS_GS_CTXSW_CNT3_BASE_IDX', 'regGDS_GWS_RESET0', - 'regGDS_GWS_RESET0_BASE_IDX', 'regGDS_GWS_RESET1', - 'regGDS_GWS_RESET1_BASE_IDX', 'regGDS_GWS_RESOURCE', - 'regGDS_GWS_RESOURCE_BASE_IDX', 'regGDS_GWS_RESOURCE_CNT', - 'regGDS_GWS_RESOURCE_CNTL', 'regGDS_GWS_RESOURCE_CNTL_BASE_IDX', - 'regGDS_GWS_RESOURCE_CNT_BASE_IDX', 'regGDS_GWS_RESOURCE_RESET', - 'regGDS_GWS_RESOURCE_RESET_BASE_IDX', 'regGDS_GWS_VMID0', - 'regGDS_GWS_VMID0_BASE_IDX', 'regGDS_GWS_VMID1', - 'regGDS_GWS_VMID10', 'regGDS_GWS_VMID10_BASE_IDX', - 'regGDS_GWS_VMID11', 'regGDS_GWS_VMID11_BASE_IDX', - 'regGDS_GWS_VMID12', 'regGDS_GWS_VMID12_BASE_IDX', - 'regGDS_GWS_VMID13', 'regGDS_GWS_VMID13_BASE_IDX', - 'regGDS_GWS_VMID14', 'regGDS_GWS_VMID14_BASE_IDX', - 'regGDS_GWS_VMID15', 'regGDS_GWS_VMID15_BASE_IDX', - 'regGDS_GWS_VMID1_BASE_IDX', 'regGDS_GWS_VMID2', - 'regGDS_GWS_VMID2_BASE_IDX', 'regGDS_GWS_VMID3', - 'regGDS_GWS_VMID3_BASE_IDX', 'regGDS_GWS_VMID4', - 'regGDS_GWS_VMID4_BASE_IDX', 'regGDS_GWS_VMID5', - 'regGDS_GWS_VMID5_BASE_IDX', 'regGDS_GWS_VMID6', - 'regGDS_GWS_VMID6_BASE_IDX', 'regGDS_GWS_VMID7', - 'regGDS_GWS_VMID7_BASE_IDX', 'regGDS_GWS_VMID8', - 'regGDS_GWS_VMID8_BASE_IDX', 'regGDS_GWS_VMID9', - 'regGDS_GWS_VMID9_BASE_IDX', 'regGDS_MEMORY_CLEAN', - 'regGDS_MEMORY_CLEAN_BASE_IDX', 'regGDS_OA_ADDRESS', - 'regGDS_OA_ADDRESS_BASE_IDX', 'regGDS_OA_CGPG_RESTORE', - 'regGDS_OA_CGPG_RESTORE_BASE_IDX', 'regGDS_OA_CNTL', - 'regGDS_OA_CNTL_BASE_IDX', 'regGDS_OA_COUNTER', - 'regGDS_OA_COUNTER_BASE_IDX', 'regGDS_OA_INCDEC', - 'regGDS_OA_INCDEC_BASE_IDX', 'regGDS_OA_RESET', - 'regGDS_OA_RESET_BASE_IDX', 'regGDS_OA_RESET_MASK', - 'regGDS_OA_RESET_MASK_BASE_IDX', 'regGDS_OA_RING_SIZE', - 'regGDS_OA_RING_SIZE_BASE_IDX', 'regGDS_OA_VMID0', - 'regGDS_OA_VMID0_BASE_IDX', 'regGDS_OA_VMID1', 'regGDS_OA_VMID10', - 'regGDS_OA_VMID10_BASE_IDX', 'regGDS_OA_VMID11', - 'regGDS_OA_VMID11_BASE_IDX', 'regGDS_OA_VMID12', - 'regGDS_OA_VMID12_BASE_IDX', 'regGDS_OA_VMID13', - 'regGDS_OA_VMID13_BASE_IDX', 'regGDS_OA_VMID14', - 'regGDS_OA_VMID14_BASE_IDX', 'regGDS_OA_VMID15', - 'regGDS_OA_VMID15_BASE_IDX', 'regGDS_OA_VMID1_BASE_IDX', - 'regGDS_OA_VMID2', 'regGDS_OA_VMID2_BASE_IDX', 'regGDS_OA_VMID3', - 'regGDS_OA_VMID3_BASE_IDX', 'regGDS_OA_VMID4', - 'regGDS_OA_VMID4_BASE_IDX', 'regGDS_OA_VMID5', - 'regGDS_OA_VMID5_BASE_IDX', 'regGDS_OA_VMID6', - 'regGDS_OA_VMID6_BASE_IDX', 'regGDS_OA_VMID7', - 'regGDS_OA_VMID7_BASE_IDX', 'regGDS_OA_VMID8', - 'regGDS_OA_VMID8_BASE_IDX', 'regGDS_OA_VMID9', - 'regGDS_OA_VMID9_BASE_IDX', 'regGDS_PERFCOUNTER0_HI', - 'regGDS_PERFCOUNTER0_HI_BASE_IDX', 'regGDS_PERFCOUNTER0_LO', - 'regGDS_PERFCOUNTER0_LO_BASE_IDX', 'regGDS_PERFCOUNTER0_SELECT', - 'regGDS_PERFCOUNTER0_SELECT1', - 'regGDS_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER1_HI', - 'regGDS_PERFCOUNTER1_HI_BASE_IDX', 'regGDS_PERFCOUNTER1_LO', - 'regGDS_PERFCOUNTER1_LO_BASE_IDX', 'regGDS_PERFCOUNTER1_SELECT', - 'regGDS_PERFCOUNTER1_SELECT1', - 'regGDS_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER2_HI', - 'regGDS_PERFCOUNTER2_HI_BASE_IDX', 'regGDS_PERFCOUNTER2_LO', - 'regGDS_PERFCOUNTER2_LO_BASE_IDX', 'regGDS_PERFCOUNTER2_SELECT', - 'regGDS_PERFCOUNTER2_SELECT1', - 'regGDS_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGDS_PERFCOUNTER3_HI', - 'regGDS_PERFCOUNTER3_HI_BASE_IDX', 'regGDS_PERFCOUNTER3_LO', - 'regGDS_PERFCOUNTER3_LO_BASE_IDX', 'regGDS_PERFCOUNTER3_SELECT', - 'regGDS_PERFCOUNTER3_SELECT1', - 'regGDS_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'regGDS_PROTECTION_FAULT', - 'regGDS_PROTECTION_FAULT_BASE_IDX', 'regGDS_PS_CTXSW_CNT0', - 'regGDS_PS_CTXSW_CNT0_BASE_IDX', 'regGDS_PS_CTXSW_CNT1', - 'regGDS_PS_CTXSW_CNT1_BASE_IDX', 'regGDS_PS_CTXSW_CNT2', - 'regGDS_PS_CTXSW_CNT2_BASE_IDX', 'regGDS_PS_CTXSW_CNT3', - 'regGDS_PS_CTXSW_CNT3_BASE_IDX', 'regGDS_PS_CTXSW_IDX', - 'regGDS_PS_CTXSW_IDX_BASE_IDX', 'regGDS_RD_ADDR', - 'regGDS_RD_ADDR_BASE_IDX', 'regGDS_RD_BURST_ADDR', - 'regGDS_RD_BURST_ADDR_BASE_IDX', 'regGDS_RD_BURST_COUNT', - 'regGDS_RD_BURST_COUNT_BASE_IDX', 'regGDS_RD_BURST_DATA', - 'regGDS_RD_BURST_DATA_BASE_IDX', 'regGDS_RD_DATA', - 'regGDS_RD_DATA_BASE_IDX', 'regGDS_STRMOUT_DWORDS_WRITTEN_0', - 'regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX', - 'regGDS_STRMOUT_DWORDS_WRITTEN_1', - 'regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX', - 'regGDS_STRMOUT_DWORDS_WRITTEN_2', - 'regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX', - 'regGDS_STRMOUT_DWORDS_WRITTEN_3', - 'regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_HI', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_LO', - 'regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO', - 'regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX', 'regGDS_VMID0_BASE', - 'regGDS_VMID0_BASE_BASE_IDX', 'regGDS_VMID0_SIZE', - 'regGDS_VMID0_SIZE_BASE_IDX', 'regGDS_VMID10_BASE', - 'regGDS_VMID10_BASE_BASE_IDX', 'regGDS_VMID10_SIZE', - 'regGDS_VMID10_SIZE_BASE_IDX', 'regGDS_VMID11_BASE', - 'regGDS_VMID11_BASE_BASE_IDX', 'regGDS_VMID11_SIZE', - 'regGDS_VMID11_SIZE_BASE_IDX', 'regGDS_VMID12_BASE', - 'regGDS_VMID12_BASE_BASE_IDX', 'regGDS_VMID12_SIZE', - 'regGDS_VMID12_SIZE_BASE_IDX', 'regGDS_VMID13_BASE', - 'regGDS_VMID13_BASE_BASE_IDX', 'regGDS_VMID13_SIZE', - 'regGDS_VMID13_SIZE_BASE_IDX', 'regGDS_VMID14_BASE', - 'regGDS_VMID14_BASE_BASE_IDX', 'regGDS_VMID14_SIZE', - 'regGDS_VMID14_SIZE_BASE_IDX', 'regGDS_VMID15_BASE', - 'regGDS_VMID15_BASE_BASE_IDX', 'regGDS_VMID15_SIZE', - 'regGDS_VMID15_SIZE_BASE_IDX', 'regGDS_VMID1_BASE', - 'regGDS_VMID1_BASE_BASE_IDX', 'regGDS_VMID1_SIZE', - 'regGDS_VMID1_SIZE_BASE_IDX', 'regGDS_VMID2_BASE', - 'regGDS_VMID2_BASE_BASE_IDX', 'regGDS_VMID2_SIZE', - 'regGDS_VMID2_SIZE_BASE_IDX', 'regGDS_VMID3_BASE', - 'regGDS_VMID3_BASE_BASE_IDX', 'regGDS_VMID3_SIZE', - 'regGDS_VMID3_SIZE_BASE_IDX', 'regGDS_VMID4_BASE', - 'regGDS_VMID4_BASE_BASE_IDX', 'regGDS_VMID4_SIZE', - 'regGDS_VMID4_SIZE_BASE_IDX', 'regGDS_VMID5_BASE', - 'regGDS_VMID5_BASE_BASE_IDX', 'regGDS_VMID5_SIZE', - 'regGDS_VMID5_SIZE_BASE_IDX', 'regGDS_VMID6_BASE', - 'regGDS_VMID6_BASE_BASE_IDX', 'regGDS_VMID6_SIZE', - 'regGDS_VMID6_SIZE_BASE_IDX', 'regGDS_VMID7_BASE', - 'regGDS_VMID7_BASE_BASE_IDX', 'regGDS_VMID7_SIZE', - 'regGDS_VMID7_SIZE_BASE_IDX', 'regGDS_VMID8_BASE', - 'regGDS_VMID8_BASE_BASE_IDX', 'regGDS_VMID8_SIZE', - 'regGDS_VMID8_SIZE_BASE_IDX', 'regGDS_VMID9_BASE', - 'regGDS_VMID9_BASE_BASE_IDX', 'regGDS_VMID9_SIZE', - 'regGDS_VMID9_SIZE_BASE_IDX', 'regGDS_VM_PROTECTION_FAULT', - 'regGDS_VM_PROTECTION_FAULT_BASE_IDX', 'regGDS_WRITE_COMPLETE', - 'regGDS_WRITE_COMPLETE_BASE_IDX', 'regGDS_WR_ADDR', - 'regGDS_WR_ADDR_BASE_IDX', 'regGDS_WR_BURST_ADDR', - 'regGDS_WR_BURST_ADDR_BASE_IDX', 'regGDS_WR_BURST_DATA', - 'regGDS_WR_BURST_DATA_BASE_IDX', 'regGDS_WR_DATA', - 'regGDS_WR_DATA_BASE_IDX', 'regGE1_PERFCOUNTER0_HI', - 'regGE1_PERFCOUNTER0_HI_BASE_IDX', 'regGE1_PERFCOUNTER0_LO', - 'regGE1_PERFCOUNTER0_LO_BASE_IDX', 'regGE1_PERFCOUNTER0_SELECT', - 'regGE1_PERFCOUNTER0_SELECT1', - 'regGE1_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER1_HI', - 'regGE1_PERFCOUNTER1_HI_BASE_IDX', 'regGE1_PERFCOUNTER1_LO', - 'regGE1_PERFCOUNTER1_LO_BASE_IDX', 'regGE1_PERFCOUNTER1_SELECT', - 'regGE1_PERFCOUNTER1_SELECT1', - 'regGE1_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER2_HI', - 'regGE1_PERFCOUNTER2_HI_BASE_IDX', 'regGE1_PERFCOUNTER2_LO', - 'regGE1_PERFCOUNTER2_LO_BASE_IDX', 'regGE1_PERFCOUNTER2_SELECT', - 'regGE1_PERFCOUNTER2_SELECT1', - 'regGE1_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'regGE1_PERFCOUNTER3_HI', - 'regGE1_PERFCOUNTER3_HI_BASE_IDX', 'regGE1_PERFCOUNTER3_LO', - 'regGE1_PERFCOUNTER3_LO_BASE_IDX', 'regGE1_PERFCOUNTER3_SELECT', - 'regGE1_PERFCOUNTER3_SELECT1', - 'regGE1_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGE1_PERFCOUNTER3_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_HI', - 'regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_LO', - 'regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_SELECT', - 'regGE2_DIST_PERFCOUNTER0_SELECT1', - 'regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_HI', - 'regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_LO', - 'regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_SELECT', - 'regGE2_DIST_PERFCOUNTER1_SELECT1', - 'regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_HI', - 'regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_LO', - 'regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_SELECT', - 'regGE2_DIST_PERFCOUNTER2_SELECT1', - 'regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_HI', - 'regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_LO', - 'regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_SELECT', - 'regGE2_DIST_PERFCOUNTER3_SELECT1', - 'regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX', - 'regGE2_SE_CNTL_STATUS', 'regGE2_SE_CNTL_STATUS_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_HI', 'regGE2_SE_PERFCOUNTER0_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_LO', 'regGE2_SE_PERFCOUNTER0_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_SELECT', 'regGE2_SE_PERFCOUNTER0_SELECT1', - 'regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_HI', 'regGE2_SE_PERFCOUNTER1_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_LO', 'regGE2_SE_PERFCOUNTER1_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_SELECT', 'regGE2_SE_PERFCOUNTER1_SELECT1', - 'regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_HI', 'regGE2_SE_PERFCOUNTER2_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_LO', 'regGE2_SE_PERFCOUNTER2_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_SELECT', 'regGE2_SE_PERFCOUNTER2_SELECT1', - 'regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_HI', 'regGE2_SE_PERFCOUNTER3_HI_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_LO', 'regGE2_SE_PERFCOUNTER3_LO_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_SELECT', 'regGE2_SE_PERFCOUNTER3_SELECT1', - 'regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'regGE_CNTL', - 'regGE_CNTL_BASE_IDX', 'regGE_GS_FAST_LAUNCH_WG_DIM', - 'regGE_GS_FAST_LAUNCH_WG_DIM_1', - 'regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX', - 'regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX', 'regGE_INDX_OFFSET', - 'regGE_INDX_OFFSET_BASE_IDX', 'regGE_MAX_OUTPUT_PER_SUBGROUP', - 'regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'regGE_MAX_VTX_INDX', - 'regGE_MAX_VTX_INDX_BASE_IDX', 'regGE_MIN_VTX_INDX', - 'regGE_MIN_VTX_INDX_BASE_IDX', 'regGE_MULTI_PRIM_IB_RESET_EN', - 'regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'regGE_NGG_SUBGRP_CNTL', - 'regGE_NGG_SUBGRP_CNTL_BASE_IDX', 'regGE_PA_IF_SAFE_REG', - 'regGE_PA_IF_SAFE_REG_BASE_IDX', 'regGE_PC_ALLOC', - 'regGE_PC_ALLOC_BASE_IDX', 'regGE_PRIV_CONTROL', - 'regGE_PRIV_CONTROL_BASE_IDX', 'regGE_RATE_CNTL_1', - 'regGE_RATE_CNTL_1_BASE_IDX', 'regGE_RATE_CNTL_2', - 'regGE_RATE_CNTL_2_BASE_IDX', 'regGE_SPI_IF_SAFE_REG', - 'regGE_SPI_IF_SAFE_REG_BASE_IDX', 'regGE_STATUS', - 'regGE_STATUS_BASE_IDX', 'regGE_STEREO_CNTL', - 'regGE_STEREO_CNTL_BASE_IDX', 'regGE_USER_VGPR1', - 'regGE_USER_VGPR1_BASE_IDX', 'regGE_USER_VGPR2', - 'regGE_USER_VGPR2_BASE_IDX', 'regGE_USER_VGPR3', - 'regGE_USER_VGPR3_BASE_IDX', 'regGE_USER_VGPR_EN', - 'regGE_USER_VGPR_EN_BASE_IDX', 'regGFX_COPY_STATE', - 'regGFX_COPY_STATE_BASE_IDX', 'regGFX_ICG_GL2C_CTRL', - 'regGFX_ICG_GL2C_CTRL1', 'regGFX_ICG_GL2C_CTRL1_BASE_IDX', - 'regGFX_ICG_GL2C_CTRL_BASE_IDX', 'regGFX_IMU_AEB_OVERRIDE', - 'regGFX_IMU_AEB_OVERRIDE_BASE_IDX', 'regGFX_IMU_C2PMSG_0', - 'regGFX_IMU_C2PMSG_0_BASE_IDX', 'regGFX_IMU_C2PMSG_1', - 'regGFX_IMU_C2PMSG_10', 'regGFX_IMU_C2PMSG_10_BASE_IDX', - 'regGFX_IMU_C2PMSG_11', 'regGFX_IMU_C2PMSG_11_BASE_IDX', - 'regGFX_IMU_C2PMSG_12', 'regGFX_IMU_C2PMSG_12_BASE_IDX', - 'regGFX_IMU_C2PMSG_13', 'regGFX_IMU_C2PMSG_13_BASE_IDX', - 'regGFX_IMU_C2PMSG_14', 'regGFX_IMU_C2PMSG_14_BASE_IDX', - 'regGFX_IMU_C2PMSG_15', 'regGFX_IMU_C2PMSG_15_BASE_IDX', - 'regGFX_IMU_C2PMSG_16', 'regGFX_IMU_C2PMSG_16_BASE_IDX', - 'regGFX_IMU_C2PMSG_17', 'regGFX_IMU_C2PMSG_17_BASE_IDX', - 'regGFX_IMU_C2PMSG_18', 'regGFX_IMU_C2PMSG_18_BASE_IDX', - 'regGFX_IMU_C2PMSG_19', 'regGFX_IMU_C2PMSG_19_BASE_IDX', - 'regGFX_IMU_C2PMSG_1_BASE_IDX', 'regGFX_IMU_C2PMSG_2', - 'regGFX_IMU_C2PMSG_20', 'regGFX_IMU_C2PMSG_20_BASE_IDX', - 'regGFX_IMU_C2PMSG_21', 'regGFX_IMU_C2PMSG_21_BASE_IDX', - 'regGFX_IMU_C2PMSG_22', 'regGFX_IMU_C2PMSG_22_BASE_IDX', - 'regGFX_IMU_C2PMSG_23', 'regGFX_IMU_C2PMSG_23_BASE_IDX', - 'regGFX_IMU_C2PMSG_24', 'regGFX_IMU_C2PMSG_24_BASE_IDX', - 'regGFX_IMU_C2PMSG_25', 'regGFX_IMU_C2PMSG_25_BASE_IDX', - 'regGFX_IMU_C2PMSG_26', 'regGFX_IMU_C2PMSG_26_BASE_IDX', - 'regGFX_IMU_C2PMSG_27', 'regGFX_IMU_C2PMSG_27_BASE_IDX', - 'regGFX_IMU_C2PMSG_28', 'regGFX_IMU_C2PMSG_28_BASE_IDX', - 'regGFX_IMU_C2PMSG_29', 'regGFX_IMU_C2PMSG_29_BASE_IDX', - 'regGFX_IMU_C2PMSG_2_BASE_IDX', 'regGFX_IMU_C2PMSG_3', - 'regGFX_IMU_C2PMSG_30', 'regGFX_IMU_C2PMSG_30_BASE_IDX', - 'regGFX_IMU_C2PMSG_31', 'regGFX_IMU_C2PMSG_31_BASE_IDX', - 'regGFX_IMU_C2PMSG_32', 'regGFX_IMU_C2PMSG_32_BASE_IDX', - 'regGFX_IMU_C2PMSG_33', 'regGFX_IMU_C2PMSG_33_BASE_IDX', - 'regGFX_IMU_C2PMSG_34', 'regGFX_IMU_C2PMSG_34_BASE_IDX', - 'regGFX_IMU_C2PMSG_35', 'regGFX_IMU_C2PMSG_35_BASE_IDX', - 'regGFX_IMU_C2PMSG_36', 'regGFX_IMU_C2PMSG_36_BASE_IDX', - 'regGFX_IMU_C2PMSG_37', 'regGFX_IMU_C2PMSG_37_BASE_IDX', - 'regGFX_IMU_C2PMSG_38', 'regGFX_IMU_C2PMSG_38_BASE_IDX', - 'regGFX_IMU_C2PMSG_39', 'regGFX_IMU_C2PMSG_39_BASE_IDX', - 'regGFX_IMU_C2PMSG_3_BASE_IDX', 'regGFX_IMU_C2PMSG_4', - 'regGFX_IMU_C2PMSG_40', 'regGFX_IMU_C2PMSG_40_BASE_IDX', - 'regGFX_IMU_C2PMSG_41', 'regGFX_IMU_C2PMSG_41_BASE_IDX', - 'regGFX_IMU_C2PMSG_42', 'regGFX_IMU_C2PMSG_42_BASE_IDX', - 'regGFX_IMU_C2PMSG_43', 'regGFX_IMU_C2PMSG_43_BASE_IDX', - 'regGFX_IMU_C2PMSG_44', 'regGFX_IMU_C2PMSG_44_BASE_IDX', - 'regGFX_IMU_C2PMSG_45', 'regGFX_IMU_C2PMSG_45_BASE_IDX', - 'regGFX_IMU_C2PMSG_46', 'regGFX_IMU_C2PMSG_46_BASE_IDX', - 'regGFX_IMU_C2PMSG_47', 'regGFX_IMU_C2PMSG_47_BASE_IDX', - 'regGFX_IMU_C2PMSG_4_BASE_IDX', 'regGFX_IMU_C2PMSG_5', - 'regGFX_IMU_C2PMSG_5_BASE_IDX', 'regGFX_IMU_C2PMSG_6', - 'regGFX_IMU_C2PMSG_6_BASE_IDX', 'regGFX_IMU_C2PMSG_7', - 'regGFX_IMU_C2PMSG_7_BASE_IDX', 'regGFX_IMU_C2PMSG_8', - 'regGFX_IMU_C2PMSG_8_BASE_IDX', 'regGFX_IMU_C2PMSG_9', - 'regGFX_IMU_C2PMSG_9_BASE_IDX', 'regGFX_IMU_C2PMSG_ACCESS_CTRL0', - 'regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX', - 'regGFX_IMU_C2PMSG_ACCESS_CTRL1', - 'regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX', 'regGFX_IMU_CLK_CTRL', - 'regGFX_IMU_CLK_CTRL_BASE_IDX', 'regGFX_IMU_CORE_CTRL', - 'regGFX_IMU_CORE_CTRL_BASE_IDX', 'regGFX_IMU_CORE_INT_STATUS', - 'regGFX_IMU_CORE_INT_STATUS_BASE_IDX', 'regGFX_IMU_CORE_STATUS', - 'regGFX_IMU_CORE_STATUS_BASE_IDX', 'regGFX_IMU_DOORBELL_CONTROL', - 'regGFX_IMU_DOORBELL_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_ACC', - 'regGFX_IMU_DPM_ACC_BASE_IDX', 'regGFX_IMU_DPM_CONTROL', - 'regGFX_IMU_DPM_CONTROL_BASE_IDX', 'regGFX_IMU_DPM_REF_COUNTER', - 'regGFX_IMU_DPM_REF_COUNTER_BASE_IDX', 'regGFX_IMU_D_RAM_ADDR', - 'regGFX_IMU_D_RAM_ADDR_BASE_IDX', 'regGFX_IMU_D_RAM_DATA', - 'regGFX_IMU_D_RAM_DATA_BASE_IDX', 'regGFX_IMU_FENCE_CTRL', - 'regGFX_IMU_FENCE_CTRL_BASE_IDX', 'regGFX_IMU_FENCE_LOG_ADDR', - 'regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX', 'regGFX_IMU_FENCE_LOG_INIT', - 'regGFX_IMU_FENCE_LOG_INIT_BASE_IDX', 'regGFX_IMU_FUSESTRAP', - 'regGFX_IMU_FUSE_CTRL', 'regGFX_IMU_FUSE_CTRL_BASE_IDX', - 'regGFX_IMU_FW_GTS_HI', 'regGFX_IMU_FW_GTS_HI_BASE_IDX', - 'regGFX_IMU_FW_GTS_LO', 'regGFX_IMU_FW_GTS_LO_BASE_IDX', - 'regGFX_IMU_GAP_PWROK', 'regGFX_IMU_GAP_PWROK_BASE_IDX', - 'regGFX_IMU_GFXCLK_BYPASS_CTRL', - 'regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX', - 'regGFX_IMU_GFX_IH_GASKET_CTRL', - 'regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX', - 'regGFX_IMU_GFX_ISO_CTRL', 'regGFX_IMU_GFX_ISO_CTRL_BASE_IDX', - 'regGFX_IMU_GFX_RESET_CTRL', 'regGFX_IMU_GFX_RESET_CTRL_BASE_IDX', - 'regGFX_IMU_GTS_OFFSET_HI', 'regGFX_IMU_GTS_OFFSET_HI_BASE_IDX', - 'regGFX_IMU_GTS_OFFSET_LO', 'regGFX_IMU_GTS_OFFSET_LO_BASE_IDX', - 'regGFX_IMU_IH_CTRL_1', 'regGFX_IMU_IH_CTRL_1_BASE_IDX', - 'regGFX_IMU_IH_CTRL_2', 'regGFX_IMU_IH_CTRL_2_BASE_IDX', - 'regGFX_IMU_IH_CTRL_3', 'regGFX_IMU_IH_CTRL_3_BASE_IDX', - 'regGFX_IMU_IH_STATUS', 'regGFX_IMU_IH_STATUS_BASE_IDX', - 'regGFX_IMU_I_RAM_ADDR', 'regGFX_IMU_I_RAM_ADDR_BASE_IDX', - 'regGFX_IMU_I_RAM_DATA', 'regGFX_IMU_I_RAM_DATA_BASE_IDX', - 'regGFX_IMU_MP1_MUTEX', 'regGFX_IMU_MP1_MUTEX_BASE_IDX', - 'regGFX_IMU_MSG_FLAGS', 'regGFX_IMU_MSG_FLAGS_BASE_IDX', - 'regGFX_IMU_PIC_INTR', 'regGFX_IMU_PIC_INTR_BASE_IDX', - 'regGFX_IMU_PIC_INTR_ID', 'regGFX_IMU_PIC_INTR_ID_BASE_IDX', - 'regGFX_IMU_PIC_INT_EDGE', 'regGFX_IMU_PIC_INT_EDGE_BASE_IDX', - 'regGFX_IMU_PIC_INT_LVL', 'regGFX_IMU_PIC_INT_LVL_BASE_IDX', - 'regGFX_IMU_PIC_INT_MASK', 'regGFX_IMU_PIC_INT_MASK_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_0', 'regGFX_IMU_PIC_INT_PRI_0_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_1', 'regGFX_IMU_PIC_INT_PRI_1_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_2', 'regGFX_IMU_PIC_INT_PRI_2_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_3', 'regGFX_IMU_PIC_INT_PRI_3_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_4', 'regGFX_IMU_PIC_INT_PRI_4_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_5', 'regGFX_IMU_PIC_INT_PRI_5_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_6', 'regGFX_IMU_PIC_INT_PRI_6_BASE_IDX', - 'regGFX_IMU_PIC_INT_PRI_7', 'regGFX_IMU_PIC_INT_PRI_7_BASE_IDX', - 'regGFX_IMU_PIC_INT_STATUS', 'regGFX_IMU_PIC_INT_STATUS_BASE_IDX', - 'regGFX_IMU_PROGRAM_CTR', 'regGFX_IMU_PROGRAM_CTR_BASE_IDX', - 'regGFX_IMU_PWRMGT_IRQ_CTRL', - 'regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX', 'regGFX_IMU_PWROK', - 'regGFX_IMU_PWROKRAW', 'regGFX_IMU_PWROKRAW_BASE_IDX', - 'regGFX_IMU_PWROK_BASE_IDX', 'regGFX_IMU_RESETn', - 'regGFX_IMU_RESETn_BASE_IDX', 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI', - 'regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX', - 'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO', - 'regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX', - 'regGFX_IMU_RLC_BOOTLOADER_SIZE', - 'regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX', - 'regGFX_IMU_RLC_CG_CTRL', 'regGFX_IMU_RLC_CG_CTRL_BASE_IDX', - 'regGFX_IMU_RLC_CMD', 'regGFX_IMU_RLC_CMD_BASE_IDX', - 'regGFX_IMU_RLC_DATA_0', 'regGFX_IMU_RLC_DATA_0_BASE_IDX', - 'regGFX_IMU_RLC_DATA_1', 'regGFX_IMU_RLC_DATA_1_BASE_IDX', - 'regGFX_IMU_RLC_DATA_2', 'regGFX_IMU_RLC_DATA_2_BASE_IDX', - 'regGFX_IMU_RLC_DATA_3', 'regGFX_IMU_RLC_DATA_3_BASE_IDX', - 'regGFX_IMU_RLC_DATA_4', 'regGFX_IMU_RLC_DATA_4_BASE_IDX', - 'regGFX_IMU_RLC_GTS_OFFSET_HI', - 'regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX', - 'regGFX_IMU_RLC_GTS_OFFSET_LO', - 'regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX', - 'regGFX_IMU_RLC_MSG_STATUS', 'regGFX_IMU_RLC_MSG_STATUS_BASE_IDX', - 'regGFX_IMU_RLC_MUTEX', 'regGFX_IMU_RLC_MUTEX_BASE_IDX', - 'regGFX_IMU_RLC_OVERRIDE', 'regGFX_IMU_RLC_OVERRIDE_BASE_IDX', - 'regGFX_IMU_RLC_RAM_ADDR_HIGH', - 'regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX', - 'regGFX_IMU_RLC_RAM_ADDR_LOW', - 'regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX', 'regGFX_IMU_RLC_RAM_DATA', - 'regGFX_IMU_RLC_RAM_DATA_BASE_IDX', 'regGFX_IMU_RLC_RAM_INDEX', - 'regGFX_IMU_RLC_RAM_INDEX_BASE_IDX', - 'regGFX_IMU_RLC_RESET_VECTOR', - 'regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX', 'regGFX_IMU_RLC_STATUS', - 'regGFX_IMU_RLC_STATUS_BASE_IDX', 'regGFX_IMU_RLC_THROTTLE_GFX', - 'regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX', 'regGFX_IMU_SCRATCH_0', - 'regGFX_IMU_SCRATCH_0_BASE_IDX', 'regGFX_IMU_SCRATCH_1', - 'regGFX_IMU_SCRATCH_10', 'regGFX_IMU_SCRATCH_10_BASE_IDX', - 'regGFX_IMU_SCRATCH_11', 'regGFX_IMU_SCRATCH_11_BASE_IDX', - 'regGFX_IMU_SCRATCH_12', 'regGFX_IMU_SCRATCH_12_BASE_IDX', - 'regGFX_IMU_SCRATCH_13', 'regGFX_IMU_SCRATCH_13_BASE_IDX', - 'regGFX_IMU_SCRATCH_14', 'regGFX_IMU_SCRATCH_14_BASE_IDX', - 'regGFX_IMU_SCRATCH_15', 'regGFX_IMU_SCRATCH_15_BASE_IDX', - 'regGFX_IMU_SCRATCH_1_BASE_IDX', 'regGFX_IMU_SCRATCH_2', - 'regGFX_IMU_SCRATCH_2_BASE_IDX', 'regGFX_IMU_SCRATCH_3', - 'regGFX_IMU_SCRATCH_3_BASE_IDX', 'regGFX_IMU_SCRATCH_4', - 'regGFX_IMU_SCRATCH_4_BASE_IDX', 'regGFX_IMU_SCRATCH_5', - 'regGFX_IMU_SCRATCH_5_BASE_IDX', 'regGFX_IMU_SCRATCH_6', - 'regGFX_IMU_SCRATCH_6_BASE_IDX', 'regGFX_IMU_SCRATCH_7', - 'regGFX_IMU_SCRATCH_7_BASE_IDX', 'regGFX_IMU_SCRATCH_8', - 'regGFX_IMU_SCRATCH_8_BASE_IDX', 'regGFX_IMU_SCRATCH_9', - 'regGFX_IMU_SCRATCH_9_BASE_IDX', 'regGFX_IMU_SMUIO_VIDCHG_CTRL', - 'regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX', 'regGFX_IMU_SOC_ADDR', - 'regGFX_IMU_SOC_ADDR_BASE_IDX', 'regGFX_IMU_SOC_DATA', - 'regGFX_IMU_SOC_DATA_BASE_IDX', 'regGFX_IMU_SOC_REQ', - 'regGFX_IMU_SOC_REQ_BASE_IDX', 'regGFX_IMU_STATUS', - 'regGFX_IMU_STATUS_BASE_IDX', 'regGFX_IMU_TELEMETRY', - 'regGFX_IMU_TELEMETRY_BASE_IDX', 'regGFX_IMU_TELEMETRY_DATA', - 'regGFX_IMU_TELEMETRY_DATA_BASE_IDX', - 'regGFX_IMU_TELEMETRY_TEMPERATURE', - 'regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP0', 'regGFX_IMU_TIMER0_CMP0_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP1', 'regGFX_IMU_TIMER0_CMP1_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP3', 'regGFX_IMU_TIMER0_CMP3_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP_AUTOINC', - 'regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX', - 'regGFX_IMU_TIMER0_CMP_INTEN', - 'regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL0', - 'regGFX_IMU_TIMER0_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER0_CTRL1', - 'regGFX_IMU_TIMER0_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER0_VALUE', - 'regGFX_IMU_TIMER0_VALUE_BASE_IDX', 'regGFX_IMU_TIMER1_CMP0', - 'regGFX_IMU_TIMER1_CMP0_BASE_IDX', 'regGFX_IMU_TIMER1_CMP1', - 'regGFX_IMU_TIMER1_CMP1_BASE_IDX', 'regGFX_IMU_TIMER1_CMP3', - 'regGFX_IMU_TIMER1_CMP3_BASE_IDX', - 'regGFX_IMU_TIMER1_CMP_AUTOINC', - 'regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX', - 'regGFX_IMU_TIMER1_CMP_INTEN', - 'regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL0', - 'regGFX_IMU_TIMER1_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER1_CTRL1', - 'regGFX_IMU_TIMER1_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER1_VALUE', - 'regGFX_IMU_TIMER1_VALUE_BASE_IDX', 'regGFX_IMU_TIMER2_CMP0', - 'regGFX_IMU_TIMER2_CMP0_BASE_IDX', 'regGFX_IMU_TIMER2_CMP1', - 'regGFX_IMU_TIMER2_CMP1_BASE_IDX', 'regGFX_IMU_TIMER2_CMP3', - 'regGFX_IMU_TIMER2_CMP3_BASE_IDX', - 'regGFX_IMU_TIMER2_CMP_AUTOINC', - 'regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX', - 'regGFX_IMU_TIMER2_CMP_INTEN', - 'regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL0', - 'regGFX_IMU_TIMER2_CTRL0_BASE_IDX', 'regGFX_IMU_TIMER2_CTRL1', - 'regGFX_IMU_TIMER2_CTRL1_BASE_IDX', 'regGFX_IMU_TIMER2_VALUE', - 'regGFX_IMU_TIMER2_VALUE_BASE_IDX', 'regGFX_IMU_VDCI_RESET_CTRL', - 'regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX', 'regGFX_IMU_VF_CTRL', - 'regGFX_IMU_VF_CTRL_BASE_IDX', 'regGFX_PIPE_CONTROL', - 'regGFX_PIPE_CONTROL_BASE_IDX', 'regGFX_PIPE_PRIORITY', - 'regGFX_PIPE_PRIORITY_BASE_IDX', 'regGL1A_PERFCOUNTER0_HI', - 'regGL1A_PERFCOUNTER0_HI_BASE_IDX', 'regGL1A_PERFCOUNTER0_LO', - 'regGL1A_PERFCOUNTER0_LO_BASE_IDX', 'regGL1A_PERFCOUNTER0_SELECT', - 'regGL1A_PERFCOUNTER0_SELECT1', - 'regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER1_HI', - 'regGL1A_PERFCOUNTER1_HI_BASE_IDX', 'regGL1A_PERFCOUNTER1_LO', - 'regGL1A_PERFCOUNTER1_LO_BASE_IDX', 'regGL1A_PERFCOUNTER1_SELECT', - 'regGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER2_HI', - 'regGL1A_PERFCOUNTER2_HI_BASE_IDX', 'regGL1A_PERFCOUNTER2_LO', - 'regGL1A_PERFCOUNTER2_LO_BASE_IDX', 'regGL1A_PERFCOUNTER2_SELECT', - 'regGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1A_PERFCOUNTER3_HI', - 'regGL1A_PERFCOUNTER3_HI_BASE_IDX', 'regGL1A_PERFCOUNTER3_LO', - 'regGL1A_PERFCOUNTER3_LO_BASE_IDX', 'regGL1A_PERFCOUNTER3_SELECT', - 'regGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER0_HI', - 'regGL1C_PERFCOUNTER0_HI_BASE_IDX', 'regGL1C_PERFCOUNTER0_LO', - 'regGL1C_PERFCOUNTER0_LO_BASE_IDX', 'regGL1C_PERFCOUNTER0_SELECT', - 'regGL1C_PERFCOUNTER0_SELECT1', - 'regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER1_HI', - 'regGL1C_PERFCOUNTER1_HI_BASE_IDX', 'regGL1C_PERFCOUNTER1_LO', - 'regGL1C_PERFCOUNTER1_LO_BASE_IDX', 'regGL1C_PERFCOUNTER1_SELECT', - 'regGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER2_HI', - 'regGL1C_PERFCOUNTER2_HI_BASE_IDX', 'regGL1C_PERFCOUNTER2_LO', - 'regGL1C_PERFCOUNTER2_LO_BASE_IDX', 'regGL1C_PERFCOUNTER2_SELECT', - 'regGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1C_PERFCOUNTER3_HI', - 'regGL1C_PERFCOUNTER3_HI_BASE_IDX', 'regGL1C_PERFCOUNTER3_LO', - 'regGL1C_PERFCOUNTER3_LO_BASE_IDX', 'regGL1C_PERFCOUNTER3_SELECT', - 'regGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL1C_STATUS', - 'regGL1C_STATUS_BASE_IDX', 'regGL1C_UTCL0_CNTL1', - 'regGL1C_UTCL0_CNTL1_BASE_IDX', 'regGL1C_UTCL0_CNTL2', - 'regGL1C_UTCL0_CNTL2_BASE_IDX', 'regGL1C_UTCL0_RETRY', - 'regGL1C_UTCL0_RETRY_BASE_IDX', 'regGL1C_UTCL0_STATUS', - 'regGL1C_UTCL0_STATUS_BASE_IDX', 'regGL1H_ARB_CTRL', - 'regGL1H_ARB_CTRL_BASE_IDX', 'regGL1H_ARB_STATUS', - 'regGL1H_ARB_STATUS_BASE_IDX', 'regGL1H_BURST_CTRL', - 'regGL1H_BURST_CTRL_BASE_IDX', 'regGL1H_BURST_MASK', - 'regGL1H_BURST_MASK_BASE_IDX', 'regGL1H_GL1_CREDITS', - 'regGL1H_GL1_CREDITS_BASE_IDX', 'regGL1H_ICG_CTRL', - 'regGL1H_ICG_CTRL_BASE_IDX', 'regGL1H_PERFCOUNTER0_HI', - 'regGL1H_PERFCOUNTER0_HI_BASE_IDX', 'regGL1H_PERFCOUNTER0_LO', - 'regGL1H_PERFCOUNTER0_LO_BASE_IDX', 'regGL1H_PERFCOUNTER0_SELECT', - 'regGL1H_PERFCOUNTER0_SELECT1', - 'regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL1H_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER1_HI', - 'regGL1H_PERFCOUNTER1_HI_BASE_IDX', 'regGL1H_PERFCOUNTER1_LO', - 'regGL1H_PERFCOUNTER1_LO_BASE_IDX', 'regGL1H_PERFCOUNTER1_SELECT', - 'regGL1H_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER2_HI', - 'regGL1H_PERFCOUNTER2_HI_BASE_IDX', 'regGL1H_PERFCOUNTER2_LO', - 'regGL1H_PERFCOUNTER2_LO_BASE_IDX', 'regGL1H_PERFCOUNTER2_SELECT', - 'regGL1H_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL1H_PERFCOUNTER3_HI', - 'regGL1H_PERFCOUNTER3_HI_BASE_IDX', 'regGL1H_PERFCOUNTER3_LO', - 'regGL1H_PERFCOUNTER3_LO_BASE_IDX', 'regGL1H_PERFCOUNTER3_SELECT', - 'regGL1H_PERFCOUNTER3_SELECT_BASE_IDX', - 'regGL1I_GL1R_MGCG_OVERRIDE', - 'regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX', - 'regGL1I_GL1R_REP_FGCG_OVERRIDE', - 'regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX', 'regGL1_ARB_STATUS', - 'regGL1_ARB_STATUS_BASE_IDX', 'regGL1_DRAM_BURST_MASK', - 'regGL1_DRAM_BURST_MASK_BASE_IDX', 'regGL1_PIPE_STEER', - 'regGL1_PIPE_STEER_BASE_IDX', 'regGL2A_ADDR_MATCH_CTRL', - 'regGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'regGL2A_ADDR_MATCH_MASK', - 'regGL2A_ADDR_MATCH_MASK_BASE_IDX', 'regGL2A_ADDR_MATCH_SIZE', - 'regGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2A_PERFCOUNTER0_HI', - 'regGL2A_PERFCOUNTER0_HI_BASE_IDX', 'regGL2A_PERFCOUNTER0_LO', - 'regGL2A_PERFCOUNTER0_LO_BASE_IDX', 'regGL2A_PERFCOUNTER0_SELECT', - 'regGL2A_PERFCOUNTER0_SELECT1', - 'regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER1_HI', - 'regGL2A_PERFCOUNTER1_HI_BASE_IDX', 'regGL2A_PERFCOUNTER1_LO', - 'regGL2A_PERFCOUNTER1_LO_BASE_IDX', 'regGL2A_PERFCOUNTER1_SELECT', - 'regGL2A_PERFCOUNTER1_SELECT1', - 'regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER2_HI', - 'regGL2A_PERFCOUNTER2_HI_BASE_IDX', 'regGL2A_PERFCOUNTER2_LO', - 'regGL2A_PERFCOUNTER2_LO_BASE_IDX', 'regGL2A_PERFCOUNTER2_SELECT', - 'regGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2A_PERFCOUNTER3_HI', - 'regGL2A_PERFCOUNTER3_HI_BASE_IDX', 'regGL2A_PERFCOUNTER3_LO', - 'regGL2A_PERFCOUNTER3_LO_BASE_IDX', 'regGL2A_PERFCOUNTER3_SELECT', - 'regGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2A_PRIORITY_CTRL', - 'regGL2A_PRIORITY_CTRL_BASE_IDX', 'regGL2A_RESP_THROTTLE_CTRL', - 'regGL2A_RESP_THROTTLE_CTRL_BASE_IDX', 'regGL2C_ADDR_MATCH_MASK', - 'regGL2C_ADDR_MATCH_MASK_BASE_IDX', 'regGL2C_ADDR_MATCH_SIZE', - 'regGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'regGL2C_CM_CTRL0', - 'regGL2C_CM_CTRL0_BASE_IDX', 'regGL2C_CM_CTRL1', - 'regGL2C_CM_CTRL1_BASE_IDX', 'regGL2C_CM_STALL', - 'regGL2C_CM_STALL_BASE_IDX', 'regGL2C_CTRL', 'regGL2C_CTRL2', - 'regGL2C_CTRL2_BASE_IDX', 'regGL2C_CTRL3', - 'regGL2C_CTRL3_BASE_IDX', 'regGL2C_CTRL4', - 'regGL2C_CTRL4_BASE_IDX', 'regGL2C_CTRL_BASE_IDX', - 'regGL2C_DISCARD_STALL_CTRL', - 'regGL2C_DISCARD_STALL_CTRL_BASE_IDX', 'regGL2C_LB_CTR_CTRL', - 'regGL2C_LB_CTR_CTRL_BASE_IDX', 'regGL2C_LB_CTR_SEL0', - 'regGL2C_LB_CTR_SEL0_BASE_IDX', 'regGL2C_LB_CTR_SEL1', - 'regGL2C_LB_CTR_SEL1_BASE_IDX', 'regGL2C_LB_DATA0', - 'regGL2C_LB_DATA0_BASE_IDX', 'regGL2C_LB_DATA1', - 'regGL2C_LB_DATA1_BASE_IDX', 'regGL2C_LB_DATA2', - 'regGL2C_LB_DATA2_BASE_IDX', 'regGL2C_LB_DATA3', - 'regGL2C_LB_DATA3_BASE_IDX', 'regGL2C_PERFCOUNTER0_HI', - 'regGL2C_PERFCOUNTER0_HI_BASE_IDX', 'regGL2C_PERFCOUNTER0_LO', - 'regGL2C_PERFCOUNTER0_LO_BASE_IDX', 'regGL2C_PERFCOUNTER0_SELECT', - 'regGL2C_PERFCOUNTER0_SELECT1', - 'regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER1_HI', - 'regGL2C_PERFCOUNTER1_HI_BASE_IDX', 'regGL2C_PERFCOUNTER1_LO', - 'regGL2C_PERFCOUNTER1_LO_BASE_IDX', 'regGL2C_PERFCOUNTER1_SELECT', - 'regGL2C_PERFCOUNTER1_SELECT1', - 'regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER2_HI', - 'regGL2C_PERFCOUNTER2_HI_BASE_IDX', 'regGL2C_PERFCOUNTER2_LO', - 'regGL2C_PERFCOUNTER2_LO_BASE_IDX', 'regGL2C_PERFCOUNTER2_SELECT', - 'regGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'regGL2C_PERFCOUNTER3_HI', - 'regGL2C_PERFCOUNTER3_HI_BASE_IDX', 'regGL2C_PERFCOUNTER3_LO', - 'regGL2C_PERFCOUNTER3_LO_BASE_IDX', 'regGL2C_PERFCOUNTER3_SELECT', - 'regGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'regGL2C_SOFT_RESET', - 'regGL2C_SOFT_RESET_BASE_IDX', 'regGL2C_WBINVL2', - 'regGL2C_WBINVL2_BASE_IDX', 'regGL2_PIPE_STEER_0', - 'regGL2_PIPE_STEER_0_BASE_IDX', 'regGL2_PIPE_STEER_1', - 'regGL2_PIPE_STEER_1_BASE_IDX', 'regGL2_PIPE_STEER_2', - 'regGL2_PIPE_STEER_2_BASE_IDX', 'regGL2_PIPE_STEER_3', - 'regGL2_PIPE_STEER_3_BASE_IDX', 'regGRBM_CAM_DATA', - 'regGRBM_CAM_DATA_BASE_IDX', 'regGRBM_CAM_DATA_UPPER', - 'regGRBM_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_CAM_INDEX', - 'regGRBM_CAM_INDEX_BASE_IDX', 'regGRBM_CHIP_REVISION', - 'regGRBM_CHIP_REVISION_BASE_IDX', 'regGRBM_CNTL', - 'regGRBM_CNTL_BASE_IDX', 'regGRBM_DSM_BYPASS', - 'regGRBM_DSM_BYPASS_BASE_IDX', 'regGRBM_FENCE_RANGE0', - 'regGRBM_FENCE_RANGE0_BASE_IDX', 'regGRBM_FENCE_RANGE1', - 'regGRBM_FENCE_RANGE1_BASE_IDX', 'regGRBM_GFX_CLKEN_CNTL', - 'regGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL', - 'regGRBM_GFX_CNTL_BASE_IDX', 'regGRBM_GFX_CNTL_SR_DATA', - 'regGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'regGRBM_GFX_CNTL_SR_SELECT', - 'regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'regGRBM_GFX_INDEX', - 'regGRBM_GFX_INDEX_BASE_IDX', 'regGRBM_GFX_INDEX_SR_DATA', - 'regGRBM_GFX_INDEX_SR_DATA_BASE_IDX', - 'regGRBM_GFX_INDEX_SR_SELECT', - 'regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'regGRBM_HYP_CAM_DATA', - 'regGRBM_HYP_CAM_DATA_BASE_IDX', 'regGRBM_HYP_CAM_DATA_UPPER', - 'regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'regGRBM_HYP_CAM_INDEX', - 'regGRBM_HYP_CAM_INDEX_BASE_IDX', 'regGRBM_IH_CREDIT', - 'regGRBM_IH_CREDIT_BASE_IDX', 'regGRBM_INT_CNTL', - 'regGRBM_INT_CNTL_BASE_IDX', 'regGRBM_INVALID_PIPE', - 'regGRBM_INVALID_PIPE_BASE_IDX', 'regGRBM_NOWHERE', - 'regGRBM_NOWHERE_BASE_IDX', 'regGRBM_PERFCOUNTER0_HI', - 'regGRBM_PERFCOUNTER0_HI_BASE_IDX', 'regGRBM_PERFCOUNTER0_LO', - 'regGRBM_PERFCOUNTER0_LO_BASE_IDX', 'regGRBM_PERFCOUNTER0_SELECT', - 'regGRBM_PERFCOUNTER0_SELECT_BASE_IDX', - 'regGRBM_PERFCOUNTER0_SELECT_HI', - 'regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX', - 'regGRBM_PERFCOUNTER1_HI', 'regGRBM_PERFCOUNTER1_HI_BASE_IDX', - 'regGRBM_PERFCOUNTER1_LO', 'regGRBM_PERFCOUNTER1_LO_BASE_IDX', - 'regGRBM_PERFCOUNTER1_SELECT', - 'regGRBM_PERFCOUNTER1_SELECT_BASE_IDX', - 'regGRBM_PERFCOUNTER1_SELECT_HI', - 'regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'regGRBM_PWR_CNTL', - 'regGRBM_PWR_CNTL2', 'regGRBM_PWR_CNTL2_BASE_IDX', - 'regGRBM_PWR_CNTL_BASE_IDX', 'regGRBM_READ_ERROR', - 'regGRBM_READ_ERROR2', 'regGRBM_READ_ERROR2_BASE_IDX', - 'regGRBM_READ_ERROR_BASE_IDX', 'regGRBM_SCRATCH_REG0', - 'regGRBM_SCRATCH_REG0_BASE_IDX', 'regGRBM_SCRATCH_REG1', - 'regGRBM_SCRATCH_REG1_BASE_IDX', 'regGRBM_SCRATCH_REG2', - 'regGRBM_SCRATCH_REG2_BASE_IDX', 'regGRBM_SCRATCH_REG3', - 'regGRBM_SCRATCH_REG3_BASE_IDX', 'regGRBM_SCRATCH_REG4', - 'regGRBM_SCRATCH_REG4_BASE_IDX', 'regGRBM_SCRATCH_REG5', - 'regGRBM_SCRATCH_REG5_BASE_IDX', 'regGRBM_SCRATCH_REG6', - 'regGRBM_SCRATCH_REG6_BASE_IDX', 'regGRBM_SCRATCH_REG7', - 'regGRBM_SCRATCH_REG7_BASE_IDX', 'regGRBM_SE0_PERFCOUNTER_HI', - 'regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE0_PERFCOUNTER_LO', - 'regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE0_PERFCOUNTER_SELECT', - 'regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE1_PERFCOUNTER_HI', - 'regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE1_PERFCOUNTER_LO', - 'regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE1_PERFCOUNTER_SELECT', - 'regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE2_PERFCOUNTER_HI', - 'regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE2_PERFCOUNTER_LO', - 'regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE2_PERFCOUNTER_SELECT', - 'regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE3_PERFCOUNTER_HI', - 'regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE3_PERFCOUNTER_LO', - 'regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE3_PERFCOUNTER_SELECT', - 'regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE4_PERFCOUNTER_HI', - 'regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE4_PERFCOUNTER_LO', - 'regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE4_PERFCOUNTER_SELECT', - 'regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE5_PERFCOUNTER_HI', - 'regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE5_PERFCOUNTER_LO', - 'regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE5_PERFCOUNTER_SELECT', - 'regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX', - 'regGRBM_SE6_PERFCOUNTER_HI', - 'regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX', - 'regGRBM_SE6_PERFCOUNTER_LO', - 'regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX', - 'regGRBM_SE6_PERFCOUNTER_SELECT', - 'regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX', 'regGRBM_SEC_CNTL', - 'regGRBM_SEC_CNTL_BASE_IDX', 'regGRBM_SE_REMAP_CNTL', - 'regGRBM_SE_REMAP_CNTL_BASE_IDX', 'regGRBM_SKEW_CNTL', - 'regGRBM_SKEW_CNTL_BASE_IDX', 'regGRBM_SOFT_RESET', - 'regGRBM_SOFT_RESET_BASE_IDX', 'regGRBM_STATUS', - 'regGRBM_STATUS2', 'regGRBM_STATUS2_BASE_IDX', 'regGRBM_STATUS3', - 'regGRBM_STATUS3_BASE_IDX', 'regGRBM_STATUS_BASE_IDX', - 'regGRBM_STATUS_SE0', 'regGRBM_STATUS_SE0_BASE_IDX', - 'regGRBM_STATUS_SE1', 'regGRBM_STATUS_SE1_BASE_IDX', - 'regGRBM_STATUS_SE2', 'regGRBM_STATUS_SE2_BASE_IDX', - 'regGRBM_STATUS_SE3', 'regGRBM_STATUS_SE3_BASE_IDX', - 'regGRBM_STATUS_SE4', 'regGRBM_STATUS_SE4_BASE_IDX', - 'regGRBM_STATUS_SE5', 'regGRBM_STATUS_SE5_BASE_IDX', - 'regGRBM_TRAP_ADDR', 'regGRBM_TRAP_ADDR_BASE_IDX', - 'regGRBM_TRAP_ADDR_MSK', 'regGRBM_TRAP_ADDR_MSK_BASE_IDX', - 'regGRBM_TRAP_OP', 'regGRBM_TRAP_OP_BASE_IDX', 'regGRBM_TRAP_WD', - 'regGRBM_TRAP_WD_BASE_IDX', 'regGRBM_TRAP_WD_MSK', - 'regGRBM_TRAP_WD_MSK_BASE_IDX', 'regGRBM_UTCL2_INVAL_RANGE_END', - 'regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX', - 'regGRBM_UTCL2_INVAL_RANGE_START', - 'regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX', - 'regGRBM_WAIT_IDLE_CLOCKS', 'regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX', - 'regGRBM_WRITE_ERROR', 'regGRBM_WRITE_ERROR_BASE_IDX', - 'regGRTAVFS_CLK_CNTL', 'regGRTAVFS_CLK_CNTL_BASE_IDX', - 'regGRTAVFS_GENERAL_0', 'regGRTAVFS_GENERAL_0_BASE_IDX', - 'regGRTAVFS_PSM_CNTL', 'regGRTAVFS_PSM_CNTL_BASE_IDX', - 'regGRTAVFS_RTAVFS_RD_DATA', 'regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX', - 'regGRTAVFS_RTAVFS_REG_ADDR', - 'regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', - 'regGRTAVFS_RTAVFS_REG_CTRL', - 'regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX', - 'regGRTAVFS_RTAVFS_REG_STATUS', - 'regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX', - 'regGRTAVFS_RTAVFS_WR_DATA', 'regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX', - 'regGRTAVFS_SE_CLK_CNTL', 'regGRTAVFS_SE_CLK_CNTL_BASE_IDX', - 'regGRTAVFS_SE_GENERAL_0', 'regGRTAVFS_SE_GENERAL_0_BASE_IDX', - 'regGRTAVFS_SE_PSM_CNTL', 'regGRTAVFS_SE_PSM_CNTL_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_RD_DATA', - 'regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_REG_ADDR', - 'regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_REG_CTRL', - 'regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_REG_STATUS', - 'regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX', - 'regGRTAVFS_SE_RTAVFS_WR_DATA', - 'regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX', - 'regGRTAVFS_SE_SOFT_RESET', 'regGRTAVFS_SE_SOFT_RESET_BASE_IDX', - 'regGRTAVFS_SE_TARG_FREQ', 'regGRTAVFS_SE_TARG_FREQ_BASE_IDX', - 'regGRTAVFS_SE_TARG_VOLT', 'regGRTAVFS_SE_TARG_VOLT_BASE_IDX', - 'regGRTAVFS_SOFT_RESET', 'regGRTAVFS_SOFT_RESET_BASE_IDX', - 'regGRTAVFS_TARG_FREQ', 'regGRTAVFS_TARG_FREQ_BASE_IDX', - 'regGRTAVFS_TARG_VOLT', 'regGRTAVFS_TARG_VOLT_BASE_IDX', - 'regGUS_DRAM_COMBINE_FLUSH', 'regGUS_DRAM_COMBINE_FLUSH_BASE_IDX', - 'regGUS_DRAM_COMBINE_RD_WR_EN', - 'regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX', - 'regGUS_DRAM_GROUP_BURST', 'regGUS_DRAM_GROUP_BURST_BASE_IDX', - 'regGUS_DRAM_PRI_AGE_COEFF', 'regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX', - 'regGUS_DRAM_PRI_AGE_RATE', 'regGUS_DRAM_PRI_AGE_RATE_BASE_IDX', - 'regGUS_DRAM_PRI_FIXED', 'regGUS_DRAM_PRI_FIXED_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI1', - 'regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI2', - 'regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI3', - 'regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI4', - 'regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT1_PRI5', - 'regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI1', - 'regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI2', - 'regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI3', - 'regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI4', - 'regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX', - 'regGUS_DRAM_PRI_QUANT_PRI5', - 'regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', 'regGUS_DRAM_PRI_QUEUING', - 'regGUS_DRAM_PRI_QUEUING_BASE_IDX', - 'regGUS_DRAM_PRI_URGENCY_COEFF', - 'regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX', - 'regGUS_DRAM_PRI_URGENCY_MODE', - 'regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_ERR_STATUS', - 'regGUS_ERR_STATUS_BASE_IDX', 'regGUS_ICG_CTRL', - 'regGUS_ICG_CTRL_BASE_IDX', 'regGUS_IO_GROUP_BURST', - 'regGUS_IO_GROUP_BURST_BASE_IDX', 'regGUS_IO_RD_COMBINE_FLUSH', - 'regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX', - 'regGUS_IO_RD_PRI_AGE_COEFF', - 'regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX', - 'regGUS_IO_RD_PRI_AGE_RATE', 'regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX', - 'regGUS_IO_RD_PRI_FIXED', 'regGUS_IO_RD_PRI_FIXED_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI1', - 'regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI2', - 'regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI3', - 'regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT1_PRI4', - 'regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI1', - 'regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI2', - 'regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI3', - 'regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX', - 'regGUS_IO_RD_PRI_QUANT_PRI4', - 'regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX', - 'regGUS_IO_RD_PRI_QUEUING', 'regGUS_IO_RD_PRI_QUEUING_BASE_IDX', - 'regGUS_IO_RD_PRI_URGENCY_COEFF', - 'regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX', - 'regGUS_IO_RD_PRI_URGENCY_MODE', - 'regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX', - 'regGUS_IO_WR_COMBINE_FLUSH', - 'regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX', - 'regGUS_IO_WR_PRI_AGE_COEFF', - 'regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX', - 'regGUS_IO_WR_PRI_AGE_RATE', 'regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX', - 'regGUS_IO_WR_PRI_FIXED', 'regGUS_IO_WR_PRI_FIXED_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI1', - 'regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI2', - 'regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI3', - 'regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT1_PRI4', - 'regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI1', - 'regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI2', - 'regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI3', - 'regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX', - 'regGUS_IO_WR_PRI_QUANT_PRI4', - 'regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX', - 'regGUS_IO_WR_PRI_QUEUING', 'regGUS_IO_WR_PRI_QUEUING_BASE_IDX', - 'regGUS_IO_WR_PRI_URGENCY_COEFF', - 'regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX', - 'regGUS_IO_WR_PRI_URGENCY_MODE', - 'regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'regGUS_L1_CH0_CMD_IN', - 'regGUS_L1_CH0_CMD_IN_BASE_IDX', 'regGUS_L1_CH0_CMD_OUT', - 'regGUS_L1_CH0_CMD_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_IN', - 'regGUS_L1_CH0_DATA_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_OUT', - 'regGUS_L1_CH0_DATA_OUT_BASE_IDX', 'regGUS_L1_CH0_DATA_U_IN', - 'regGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH0_DATA_U_OUT', - 'regGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_CH1_CMD_IN', - 'regGUS_L1_CH1_CMD_IN_BASE_IDX', 'regGUS_L1_CH1_CMD_OUT', - 'regGUS_L1_CH1_CMD_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_IN', - 'regGUS_L1_CH1_DATA_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_OUT', - 'regGUS_L1_CH1_DATA_OUT_BASE_IDX', 'regGUS_L1_CH1_DATA_U_IN', - 'regGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'regGUS_L1_CH1_DATA_U_OUT', - 'regGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA0_CMD_IN', - 'regGUS_L1_SA0_CMD_IN_BASE_IDX', 'regGUS_L1_SA0_CMD_OUT', - 'regGUS_L1_SA0_CMD_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_IN', - 'regGUS_L1_SA0_DATA_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_OUT', - 'regGUS_L1_SA0_DATA_OUT_BASE_IDX', 'regGUS_L1_SA0_DATA_U_IN', - 'regGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA0_DATA_U_OUT', - 'regGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA1_CMD_IN', - 'regGUS_L1_SA1_CMD_IN_BASE_IDX', 'regGUS_L1_SA1_CMD_OUT', - 'regGUS_L1_SA1_CMD_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_IN', - 'regGUS_L1_SA1_DATA_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_OUT', - 'regGUS_L1_SA1_DATA_OUT_BASE_IDX', 'regGUS_L1_SA1_DATA_U_IN', - 'regGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA1_DATA_U_OUT', - 'regGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA2_CMD_IN', - 'regGUS_L1_SA2_CMD_IN_BASE_IDX', 'regGUS_L1_SA2_CMD_OUT', - 'regGUS_L1_SA2_CMD_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_IN', - 'regGUS_L1_SA2_DATA_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_OUT', - 'regGUS_L1_SA2_DATA_OUT_BASE_IDX', 'regGUS_L1_SA2_DATA_U_IN', - 'regGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA2_DATA_U_OUT', - 'regGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'regGUS_L1_SA3_CMD_IN', - 'regGUS_L1_SA3_CMD_IN_BASE_IDX', 'regGUS_L1_SA3_CMD_OUT', - 'regGUS_L1_SA3_CMD_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_IN', - 'regGUS_L1_SA3_DATA_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_OUT', - 'regGUS_L1_SA3_DATA_OUT_BASE_IDX', 'regGUS_L1_SA3_DATA_U_IN', - 'regGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'regGUS_L1_SA3_DATA_U_OUT', - 'regGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'regGUS_LATENCY_SAMPLING', - 'regGUS_LATENCY_SAMPLING_BASE_IDX', 'regGUS_MISC', 'regGUS_MISC2', - 'regGUS_MISC2_BASE_IDX', 'regGUS_MISC3', 'regGUS_MISC3_BASE_IDX', - 'regGUS_MISC_BASE_IDX', 'regGUS_PERFCOUNTER0_CFG', - 'regGUS_PERFCOUNTER0_CFG_BASE_IDX', 'regGUS_PERFCOUNTER1_CFG', - 'regGUS_PERFCOUNTER1_CFG_BASE_IDX', 'regGUS_PERFCOUNTER2_HI', - 'regGUS_PERFCOUNTER2_HI_BASE_IDX', 'regGUS_PERFCOUNTER2_LO', - 'regGUS_PERFCOUNTER2_LO_BASE_IDX', 'regGUS_PERFCOUNTER2_MODE', - 'regGUS_PERFCOUNTER2_MODE_BASE_IDX', 'regGUS_PERFCOUNTER2_SELECT', - 'regGUS_PERFCOUNTER2_SELECT1', - 'regGUS_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'regGUS_PERFCOUNTER_HI', - 'regGUS_PERFCOUNTER_HI_BASE_IDX', 'regGUS_PERFCOUNTER_LO', - 'regGUS_PERFCOUNTER_LO_BASE_IDX', 'regGUS_PERFCOUNTER_RSLT_CNTL', - 'regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regGUS_SDP_ARB_FINAL', - 'regGUS_SDP_ARB_FINAL_BASE_IDX', 'regGUS_SDP_CREDITS', - 'regGUS_SDP_CREDITS_BASE_IDX', 'regGUS_SDP_ENABLE', - 'regGUS_SDP_ENABLE_BASE_IDX', 'regGUS_SDP_QOS_VC_PRIORITY', - 'regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'regGUS_SDP_REQ_CNTL', - 'regGUS_SDP_REQ_CNTL_BASE_IDX', 'regGUS_SDP_TAG_RESERVE0', - 'regGUS_SDP_TAG_RESERVE0_BASE_IDX', 'regGUS_SDP_TAG_RESERVE1', - 'regGUS_SDP_TAG_RESERVE1_BASE_IDX', 'regGUS_SDP_VCC_RESERVE0', - 'regGUS_SDP_VCC_RESERVE0_BASE_IDX', 'regGUS_SDP_VCC_RESERVE1', - 'regGUS_SDP_VCC_RESERVE1_BASE_IDX', 'regGUS_SDP_VCD_RESERVE0', - 'regGUS_SDP_VCD_RESERVE0_BASE_IDX', 'regGUS_SDP_VCD_RESERVE1', - 'regGUS_SDP_VCD_RESERVE1_BASE_IDX', 'regGUS_WRRSP_FIFO_CNTL', - 'regGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'regIA_ENHANCE', - 'regIA_ENHANCE_BASE_IDX', 'regIA_UTCL1_CNTL', - 'regIA_UTCL1_CNTL_BASE_IDX', 'regIA_UTCL1_STATUS', - 'regIA_UTCL1_STATUS_2', 'regIA_UTCL1_STATUS_2_BASE_IDX', - 'regIA_UTCL1_STATUS_BASE_IDX', 'regICG_CHA_CTRL', - 'regICG_CHA_CTRL_BASE_IDX', 'regICG_CHCG_CLK_CTRL', - 'regICG_CHCG_CLK_CTRL_BASE_IDX', 'regICG_CHC_CLK_CTRL', - 'regICG_CHC_CLK_CTRL_BASE_IDX', 'regICG_GL1A_CTRL', - 'regICG_GL1A_CTRL_BASE_IDX', 'regICG_GL1C_CLK_CTRL', - 'regICG_GL1C_CLK_CTRL_BASE_IDX', 'regICG_LDS_CLK_CTRL', - 'regICG_LDS_CLK_CTRL_BASE_IDX', 'regICG_SP_CLK_CTRL', - 'regICG_SP_CLK_CTRL_BASE_IDX', 'regLDS_CONFIG', - 'regLDS_CONFIG_BASE_IDX', 'regPA_CL_CLIP_CNTL', - 'regPA_CL_CLIP_CNTL_BASE_IDX', 'regPA_CL_CNTL_STATUS', - 'regPA_CL_CNTL_STATUS_BASE_IDX', 'regPA_CL_ENHANCE', - 'regPA_CL_ENHANCE_BASE_IDX', 'regPA_CL_GB_HORZ_CLIP_ADJ', - 'regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_HORZ_DISC_ADJ', - 'regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_CLIP_ADJ', - 'regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'regPA_CL_GB_VERT_DISC_ADJ', - 'regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'regPA_CL_NANINF_CNTL', - 'regPA_CL_NANINF_CNTL_BASE_IDX', 'regPA_CL_NGG_CNTL', - 'regPA_CL_NGG_CNTL_BASE_IDX', 'regPA_CL_POINT_CULL_RAD', - 'regPA_CL_POINT_CULL_RAD_BASE_IDX', 'regPA_CL_POINT_SIZE', - 'regPA_CL_POINT_SIZE_BASE_IDX', 'regPA_CL_POINT_X_RAD', - 'regPA_CL_POINT_X_RAD_BASE_IDX', 'regPA_CL_POINT_Y_RAD', - 'regPA_CL_POINT_Y_RAD_BASE_IDX', 'regPA_CL_PROG_NEAR_CLIP_Z', - 'regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'regPA_CL_UCP_0_W', - 'regPA_CL_UCP_0_W_BASE_IDX', 'regPA_CL_UCP_0_X', - 'regPA_CL_UCP_0_X_BASE_IDX', 'regPA_CL_UCP_0_Y', - 'regPA_CL_UCP_0_Y_BASE_IDX', 'regPA_CL_UCP_0_Z', - 'regPA_CL_UCP_0_Z_BASE_IDX', 'regPA_CL_UCP_1_W', - 'regPA_CL_UCP_1_W_BASE_IDX', 'regPA_CL_UCP_1_X', - 'regPA_CL_UCP_1_X_BASE_IDX', 'regPA_CL_UCP_1_Y', - 'regPA_CL_UCP_1_Y_BASE_IDX', 'regPA_CL_UCP_1_Z', - 'regPA_CL_UCP_1_Z_BASE_IDX', 'regPA_CL_UCP_2_W', - 'regPA_CL_UCP_2_W_BASE_IDX', 'regPA_CL_UCP_2_X', - 'regPA_CL_UCP_2_X_BASE_IDX', 'regPA_CL_UCP_2_Y', - 'regPA_CL_UCP_2_Y_BASE_IDX', 'regPA_CL_UCP_2_Z', - 'regPA_CL_UCP_2_Z_BASE_IDX', 'regPA_CL_UCP_3_W', - 'regPA_CL_UCP_3_W_BASE_IDX', 'regPA_CL_UCP_3_X', - 'regPA_CL_UCP_3_X_BASE_IDX', 'regPA_CL_UCP_3_Y', - 'regPA_CL_UCP_3_Y_BASE_IDX', 'regPA_CL_UCP_3_Z', - 'regPA_CL_UCP_3_Z_BASE_IDX', 'regPA_CL_UCP_4_W', - 'regPA_CL_UCP_4_W_BASE_IDX', 'regPA_CL_UCP_4_X', - 'regPA_CL_UCP_4_X_BASE_IDX', 'regPA_CL_UCP_4_Y', - 'regPA_CL_UCP_4_Y_BASE_IDX', 'regPA_CL_UCP_4_Z', - 'regPA_CL_UCP_4_Z_BASE_IDX', 'regPA_CL_UCP_5_W', - 'regPA_CL_UCP_5_W_BASE_IDX', 'regPA_CL_UCP_5_X', - 'regPA_CL_UCP_5_X_BASE_IDX', 'regPA_CL_UCP_5_Y', - 'regPA_CL_UCP_5_Y_BASE_IDX', 'regPA_CL_UCP_5_Z', - 'regPA_CL_UCP_5_Z_BASE_IDX', 'regPA_CL_VPORT_XOFFSET', - 'regPA_CL_VPORT_XOFFSET_1', 'regPA_CL_VPORT_XOFFSET_10', - 'regPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_11', - 'regPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_12', - 'regPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_13', - 'regPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_14', - 'regPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_15', - 'regPA_CL_VPORT_XOFFSET_15_BASE_IDX', - 'regPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_2', - 'regPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_3', - 'regPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_4', - 'regPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_5', - 'regPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_6', - 'regPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_7', - 'regPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_8', - 'regPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_XOFFSET_9', - 'regPA_CL_VPORT_XOFFSET_9_BASE_IDX', - 'regPA_CL_VPORT_XOFFSET_BASE_IDX', 'regPA_CL_VPORT_XSCALE', - 'regPA_CL_VPORT_XSCALE_1', 'regPA_CL_VPORT_XSCALE_10', - 'regPA_CL_VPORT_XSCALE_10_BASE_IDX', 'regPA_CL_VPORT_XSCALE_11', - 'regPA_CL_VPORT_XSCALE_11_BASE_IDX', 'regPA_CL_VPORT_XSCALE_12', - 'regPA_CL_VPORT_XSCALE_12_BASE_IDX', 'regPA_CL_VPORT_XSCALE_13', - 'regPA_CL_VPORT_XSCALE_13_BASE_IDX', 'regPA_CL_VPORT_XSCALE_14', - 'regPA_CL_VPORT_XSCALE_14_BASE_IDX', 'regPA_CL_VPORT_XSCALE_15', - 'regPA_CL_VPORT_XSCALE_15_BASE_IDX', - 'regPA_CL_VPORT_XSCALE_1_BASE_IDX', 'regPA_CL_VPORT_XSCALE_2', - 'regPA_CL_VPORT_XSCALE_2_BASE_IDX', 'regPA_CL_VPORT_XSCALE_3', - 'regPA_CL_VPORT_XSCALE_3_BASE_IDX', 'regPA_CL_VPORT_XSCALE_4', - 'regPA_CL_VPORT_XSCALE_4_BASE_IDX', 'regPA_CL_VPORT_XSCALE_5', - 'regPA_CL_VPORT_XSCALE_5_BASE_IDX', 'regPA_CL_VPORT_XSCALE_6', - 'regPA_CL_VPORT_XSCALE_6_BASE_IDX', 'regPA_CL_VPORT_XSCALE_7', - 'regPA_CL_VPORT_XSCALE_7_BASE_IDX', 'regPA_CL_VPORT_XSCALE_8', - 'regPA_CL_VPORT_XSCALE_8_BASE_IDX', 'regPA_CL_VPORT_XSCALE_9', - 'regPA_CL_VPORT_XSCALE_9_BASE_IDX', - 'regPA_CL_VPORT_XSCALE_BASE_IDX', 'regPA_CL_VPORT_YOFFSET', - 'regPA_CL_VPORT_YOFFSET_1', 'regPA_CL_VPORT_YOFFSET_10', - 'regPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_11', - 'regPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_12', - 'regPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_13', - 'regPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_14', - 'regPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_15', - 'regPA_CL_VPORT_YOFFSET_15_BASE_IDX', - 'regPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_2', - 'regPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_3', - 'regPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_4', - 'regPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_5', - 'regPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_6', - 'regPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_7', - 'regPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_8', - 'regPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_YOFFSET_9', - 'regPA_CL_VPORT_YOFFSET_9_BASE_IDX', - 'regPA_CL_VPORT_YOFFSET_BASE_IDX', 'regPA_CL_VPORT_YSCALE', - 'regPA_CL_VPORT_YSCALE_1', 'regPA_CL_VPORT_YSCALE_10', - 'regPA_CL_VPORT_YSCALE_10_BASE_IDX', 'regPA_CL_VPORT_YSCALE_11', - 'regPA_CL_VPORT_YSCALE_11_BASE_IDX', 'regPA_CL_VPORT_YSCALE_12', - 'regPA_CL_VPORT_YSCALE_12_BASE_IDX', 'regPA_CL_VPORT_YSCALE_13', - 'regPA_CL_VPORT_YSCALE_13_BASE_IDX', 'regPA_CL_VPORT_YSCALE_14', - 'regPA_CL_VPORT_YSCALE_14_BASE_IDX', 'regPA_CL_VPORT_YSCALE_15', - 'regPA_CL_VPORT_YSCALE_15_BASE_IDX', - 'regPA_CL_VPORT_YSCALE_1_BASE_IDX', 'regPA_CL_VPORT_YSCALE_2', - 'regPA_CL_VPORT_YSCALE_2_BASE_IDX', 'regPA_CL_VPORT_YSCALE_3', - 'regPA_CL_VPORT_YSCALE_3_BASE_IDX', 'regPA_CL_VPORT_YSCALE_4', - 'regPA_CL_VPORT_YSCALE_4_BASE_IDX', 'regPA_CL_VPORT_YSCALE_5', - 'regPA_CL_VPORT_YSCALE_5_BASE_IDX', 'regPA_CL_VPORT_YSCALE_6', - 'regPA_CL_VPORT_YSCALE_6_BASE_IDX', 'regPA_CL_VPORT_YSCALE_7', - 'regPA_CL_VPORT_YSCALE_7_BASE_IDX', 'regPA_CL_VPORT_YSCALE_8', - 'regPA_CL_VPORT_YSCALE_8_BASE_IDX', 'regPA_CL_VPORT_YSCALE_9', - 'regPA_CL_VPORT_YSCALE_9_BASE_IDX', - 'regPA_CL_VPORT_YSCALE_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET', - 'regPA_CL_VPORT_ZOFFSET_1', 'regPA_CL_VPORT_ZOFFSET_10', - 'regPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_11', - 'regPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_12', - 'regPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_13', - 'regPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_14', - 'regPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_15', - 'regPA_CL_VPORT_ZOFFSET_15_BASE_IDX', - 'regPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_2', - 'regPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_3', - 'regPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_4', - 'regPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_5', - 'regPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_6', - 'regPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_7', - 'regPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_8', - 'regPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'regPA_CL_VPORT_ZOFFSET_9', - 'regPA_CL_VPORT_ZOFFSET_9_BASE_IDX', - 'regPA_CL_VPORT_ZOFFSET_BASE_IDX', 'regPA_CL_VPORT_ZSCALE', - 'regPA_CL_VPORT_ZSCALE_1', 'regPA_CL_VPORT_ZSCALE_10', - 'regPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_11', - 'regPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_12', - 'regPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_13', - 'regPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_14', - 'regPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_15', - 'regPA_CL_VPORT_ZSCALE_15_BASE_IDX', - 'regPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_2', - 'regPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_3', - 'regPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_4', - 'regPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_5', - 'regPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_6', - 'regPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_7', - 'regPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_8', - 'regPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'regPA_CL_VPORT_ZSCALE_9', - 'regPA_CL_VPORT_ZSCALE_9_BASE_IDX', - 'regPA_CL_VPORT_ZSCALE_BASE_IDX', 'regPA_CL_VRS_CNTL', - 'regPA_CL_VRS_CNTL_BASE_IDX', 'regPA_CL_VS_OUT_CNTL', - 'regPA_CL_VS_OUT_CNTL_BASE_IDX', 'regPA_CL_VTE_CNTL', - 'regPA_CL_VTE_CNTL_BASE_IDX', 'regPA_PH_ENHANCE', - 'regPA_PH_ENHANCE_BASE_IDX', 'regPA_PH_INTERFACE_FIFO_SIZE', - 'regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_HI', 'regPA_PH_PERFCOUNTER0_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_LO', 'regPA_PH_PERFCOUNTER0_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_SELECT', 'regPA_PH_PERFCOUNTER0_SELECT1', - 'regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_HI', 'regPA_PH_PERFCOUNTER1_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_LO', 'regPA_PH_PERFCOUNTER1_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_SELECT', 'regPA_PH_PERFCOUNTER1_SELECT1', - 'regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_HI', 'regPA_PH_PERFCOUNTER2_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_LO', 'regPA_PH_PERFCOUNTER2_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_SELECT', 'regPA_PH_PERFCOUNTER2_SELECT1', - 'regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_HI', 'regPA_PH_PERFCOUNTER3_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_LO', 'regPA_PH_PERFCOUNTER3_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_SELECT', 'regPA_PH_PERFCOUNTER3_SELECT1', - 'regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER4_HI', 'regPA_PH_PERFCOUNTER4_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER4_LO', 'regPA_PH_PERFCOUNTER4_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER4_SELECT', - 'regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER5_HI', 'regPA_PH_PERFCOUNTER5_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER5_LO', 'regPA_PH_PERFCOUNTER5_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER5_SELECT', - 'regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER6_HI', 'regPA_PH_PERFCOUNTER6_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER6_LO', 'regPA_PH_PERFCOUNTER6_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER6_SELECT', - 'regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX', - 'regPA_PH_PERFCOUNTER7_HI', 'regPA_PH_PERFCOUNTER7_HI_BASE_IDX', - 'regPA_PH_PERFCOUNTER7_LO', 'regPA_PH_PERFCOUNTER7_LO_BASE_IDX', - 'regPA_PH_PERFCOUNTER7_SELECT', - 'regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'regPA_RATE_CNTL', - 'regPA_RATE_CNTL_BASE_IDX', 'regPA_SC_AA_CONFIG', - 'regPA_SC_AA_CONFIG_BASE_IDX', 'regPA_SC_AA_MASK_X0Y0_X1Y0', - 'regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', - 'regPA_SC_AA_MASK_X0Y1_X1Y1', - 'regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3', - 'regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX', - 'regPA_SC_ATM_CNTL', 'regPA_SC_ATM_CNTL_BASE_IDX', - 'regPA_SC_BINNER_CNTL_0', 'regPA_SC_BINNER_CNTL_0_BASE_IDX', - 'regPA_SC_BINNER_CNTL_1', 'regPA_SC_BINNER_CNTL_1_BASE_IDX', - 'regPA_SC_BINNER_CNTL_2', 'regPA_SC_BINNER_CNTL_2_BASE_IDX', - 'regPA_SC_BINNER_CNTL_OVERRIDE', - 'regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_0', - 'regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_1', - 'regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_2', - 'regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX', - 'regPA_SC_BINNER_EVENT_CNTL_3', - 'regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_0', - 'regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_1', - 'regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_2', - 'regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX', - 'regPA_SC_BINNER_PERF_CNTL_3', - 'regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX', - 'regPA_SC_BINNER_TIMEOUT_COUNTER', - 'regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX', - 'regPA_SC_CENTROID_PRIORITY_0', - 'regPA_SC_CENTROID_PRIORITY_0_BASE_IDX', - 'regPA_SC_CENTROID_PRIORITY_1', - 'regPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'regPA_SC_CLIPRECT_0_BR', - 'regPA_SC_CLIPRECT_0_BR_BASE_IDX', 'regPA_SC_CLIPRECT_0_TL', - 'regPA_SC_CLIPRECT_0_TL_BASE_IDX', 'regPA_SC_CLIPRECT_1_BR', - 'regPA_SC_CLIPRECT_1_BR_BASE_IDX', 'regPA_SC_CLIPRECT_1_TL', - 'regPA_SC_CLIPRECT_1_TL_BASE_IDX', 'regPA_SC_CLIPRECT_2_BR', - 'regPA_SC_CLIPRECT_2_BR_BASE_IDX', 'regPA_SC_CLIPRECT_2_TL', - 'regPA_SC_CLIPRECT_2_TL_BASE_IDX', 'regPA_SC_CLIPRECT_3_BR', - 'regPA_SC_CLIPRECT_3_BR_BASE_IDX', 'regPA_SC_CLIPRECT_3_TL', - 'regPA_SC_CLIPRECT_3_TL_BASE_IDX', 'regPA_SC_CLIPRECT_RULE', - 'regPA_SC_CLIPRECT_RULE_BASE_IDX', - 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL', - 'regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX', - 'regPA_SC_DSM_CNTL', 'regPA_SC_DSM_CNTL_BASE_IDX', - 'regPA_SC_EDGERULE', 'regPA_SC_EDGERULE_BASE_IDX', - 'regPA_SC_ENHANCE', 'regPA_SC_ENHANCE_1', - 'regPA_SC_ENHANCE_1_BASE_IDX', 'regPA_SC_ENHANCE_2', - 'regPA_SC_ENHANCE_2_BASE_IDX', 'regPA_SC_ENHANCE_3', - 'regPA_SC_ENHANCE_3_BASE_IDX', 'regPA_SC_ENHANCE_BASE_IDX', - 'regPA_SC_FIFO_DEPTH_CNTL', 'regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX', - 'regPA_SC_FIFO_SIZE', 'regPA_SC_FIFO_SIZE_BASE_IDX', - 'regPA_SC_FORCE_EOV_MAX_CNTS', - 'regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX', - 'regPA_SC_GENERIC_SCISSOR_BR', - 'regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX', - 'regPA_SC_GENERIC_SCISSOR_TL', - 'regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_COUNT', - 'regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_H', 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN', - 'regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK', - 'regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE', - 'regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'regPA_SC_HP3D_TRAP_SCREEN_V', - 'regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'regPA_SC_IF_FIFO_SIZE', - 'regPA_SC_IF_FIFO_SIZE_BASE_IDX', 'regPA_SC_LINE_CNTL', - 'regPA_SC_LINE_CNTL_BASE_IDX', 'regPA_SC_LINE_STIPPLE', - 'regPA_SC_LINE_STIPPLE_BASE_IDX', 'regPA_SC_LINE_STIPPLE_STATE', - 'regPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'regPA_SC_MODE_CNTL_0', - 'regPA_SC_MODE_CNTL_0_BASE_IDX', 'regPA_SC_MODE_CNTL_1', - 'regPA_SC_MODE_CNTL_1_BASE_IDX', 'regPA_SC_NGG_MODE_CNTL', - 'regPA_SC_NGG_MODE_CNTL_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_COUNT', - 'regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_H', 'regPA_SC_P3D_TRAP_SCREEN_HV_EN', - 'regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK', - 'regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE', - 'regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'regPA_SC_P3D_TRAP_SCREEN_V', - 'regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX', - 'regPA_SC_PACKER_WAVE_ID_CNTL', - 'regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX', - 'regPA_SC_PBB_OVERRIDE_FLAG', - 'regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', 'regPA_SC_PERFCOUNTER0_HI', - 'regPA_SC_PERFCOUNTER0_HI_BASE_IDX', 'regPA_SC_PERFCOUNTER0_LO', - 'regPA_SC_PERFCOUNTER0_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER0_SELECT', 'regPA_SC_PERFCOUNTER0_SELECT1', - 'regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER1_HI', 'regPA_SC_PERFCOUNTER1_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER1_LO', 'regPA_SC_PERFCOUNTER1_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER1_SELECT', - 'regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER2_HI', 'regPA_SC_PERFCOUNTER2_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER2_LO', 'regPA_SC_PERFCOUNTER2_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER2_SELECT', - 'regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER3_HI', 'regPA_SC_PERFCOUNTER3_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER3_LO', 'regPA_SC_PERFCOUNTER3_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER3_SELECT', - 'regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER4_HI', 'regPA_SC_PERFCOUNTER4_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER4_LO', 'regPA_SC_PERFCOUNTER4_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER4_SELECT', - 'regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER5_HI', 'regPA_SC_PERFCOUNTER5_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER5_LO', 'regPA_SC_PERFCOUNTER5_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER5_SELECT', - 'regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER6_HI', 'regPA_SC_PERFCOUNTER6_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER6_LO', 'regPA_SC_PERFCOUNTER6_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER6_SELECT', - 'regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', - 'regPA_SC_PERFCOUNTER7_HI', 'regPA_SC_PERFCOUNTER7_HI_BASE_IDX', - 'regPA_SC_PERFCOUNTER7_LO', 'regPA_SC_PERFCOUNTER7_LO_BASE_IDX', - 'regPA_SC_PERFCOUNTER7_SELECT', - 'regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX', - 'regPA_SC_PKR_WAVE_TABLE_CNTL', - 'regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'regPA_SC_RASTER_CONFIG', - 'regPA_SC_RASTER_CONFIG_1', 'regPA_SC_RASTER_CONFIG_1_BASE_IDX', - 'regPA_SC_RASTER_CONFIG_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_CONTROL', - 'regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MAX_0', - 'regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MAX_1', - 'regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MIN_0', - 'regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX', - 'regPA_SC_SCREEN_EXTENT_MIN_1', - 'regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX', - 'regPA_SC_SCREEN_SCISSOR_BR', - 'regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX', - 'regPA_SC_SCREEN_SCISSOR_TL', - 'regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', 'regPA_SC_SHADER_CONTROL', - 'regPA_SC_SHADER_CONTROL_BASE_IDX', - 'regPA_SC_TILE_STEERING_CREST_OVERRIDE', - 'regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX', - 'regPA_SC_TILE_STEERING_OVERRIDE', - 'regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_COUNT', - 'regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', 'regPA_SC_TRAP_SCREEN_H', - 'regPA_SC_TRAP_SCREEN_HV_EN', - 'regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_HV_LOCK', - 'regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_H_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_OCCURRENCE', - 'regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX', - 'regPA_SC_TRAP_SCREEN_V', 'regPA_SC_TRAP_SCREEN_V_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_0_BR', - 'regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_0_TL', - 'regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_10_BR', - 'regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_10_TL', - 'regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_11_BR', - 'regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_11_TL', - 'regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_12_BR', - 'regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_12_TL', - 'regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_13_BR', - 'regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_13_TL', - 'regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_14_BR', - 'regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_14_TL', - 'regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_15_BR', - 'regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_15_TL', - 'regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_1_BR', - 'regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_1_TL', - 'regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_2_BR', - 'regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_2_TL', - 'regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_3_BR', - 'regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_3_TL', - 'regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_4_BR', - 'regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_4_TL', - 'regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_5_BR', - 'regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_5_TL', - 'regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_6_BR', - 'regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_6_TL', - 'regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_7_BR', - 'regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_7_TL', - 'regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_8_BR', - 'regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_8_TL', - 'regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_9_BR', - 'regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX', - 'regPA_SC_VPORT_SCISSOR_9_TL', - 'regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'regPA_SC_VPORT_ZMAX_0', - 'regPA_SC_VPORT_ZMAX_0_BASE_IDX', 'regPA_SC_VPORT_ZMAX_1', - 'regPA_SC_VPORT_ZMAX_10', 'regPA_SC_VPORT_ZMAX_10_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_11', 'regPA_SC_VPORT_ZMAX_11_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_12', 'regPA_SC_VPORT_ZMAX_12_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_13', 'regPA_SC_VPORT_ZMAX_13_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_14', 'regPA_SC_VPORT_ZMAX_14_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_15', 'regPA_SC_VPORT_ZMAX_15_BASE_IDX', - 'regPA_SC_VPORT_ZMAX_1_BASE_IDX', 'regPA_SC_VPORT_ZMAX_2', - 'regPA_SC_VPORT_ZMAX_2_BASE_IDX', 'regPA_SC_VPORT_ZMAX_3', - 'regPA_SC_VPORT_ZMAX_3_BASE_IDX', 'regPA_SC_VPORT_ZMAX_4', - 'regPA_SC_VPORT_ZMAX_4_BASE_IDX', 'regPA_SC_VPORT_ZMAX_5', - 'regPA_SC_VPORT_ZMAX_5_BASE_IDX', 'regPA_SC_VPORT_ZMAX_6', - 'regPA_SC_VPORT_ZMAX_6_BASE_IDX', 'regPA_SC_VPORT_ZMAX_7', - 'regPA_SC_VPORT_ZMAX_7_BASE_IDX', 'regPA_SC_VPORT_ZMAX_8', - 'regPA_SC_VPORT_ZMAX_8_BASE_IDX', 'regPA_SC_VPORT_ZMAX_9', - 'regPA_SC_VPORT_ZMAX_9_BASE_IDX', 'regPA_SC_VPORT_ZMIN_0', - 'regPA_SC_VPORT_ZMIN_0_BASE_IDX', 'regPA_SC_VPORT_ZMIN_1', - 'regPA_SC_VPORT_ZMIN_10', 'regPA_SC_VPORT_ZMIN_10_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_11', 'regPA_SC_VPORT_ZMIN_11_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_12', 'regPA_SC_VPORT_ZMIN_12_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_13', 'regPA_SC_VPORT_ZMIN_13_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_14', 'regPA_SC_VPORT_ZMIN_14_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_15', 'regPA_SC_VPORT_ZMIN_15_BASE_IDX', - 'regPA_SC_VPORT_ZMIN_1_BASE_IDX', 'regPA_SC_VPORT_ZMIN_2', - 'regPA_SC_VPORT_ZMIN_2_BASE_IDX', 'regPA_SC_VPORT_ZMIN_3', - 'regPA_SC_VPORT_ZMIN_3_BASE_IDX', 'regPA_SC_VPORT_ZMIN_4', - 'regPA_SC_VPORT_ZMIN_4_BASE_IDX', 'regPA_SC_VPORT_ZMIN_5', - 'regPA_SC_VPORT_ZMIN_5_BASE_IDX', 'regPA_SC_VPORT_ZMIN_6', - 'regPA_SC_VPORT_ZMIN_6_BASE_IDX', 'regPA_SC_VPORT_ZMIN_7', - 'regPA_SC_VPORT_ZMIN_7_BASE_IDX', 'regPA_SC_VPORT_ZMIN_8', - 'regPA_SC_VPORT_ZMIN_8_BASE_IDX', 'regPA_SC_VPORT_ZMIN_9', - 'regPA_SC_VPORT_ZMIN_9_BASE_IDX', 'regPA_SC_VRS_OVERRIDE_CNTL', - 'regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX', 'regPA_SC_VRS_RATE_BASE', - 'regPA_SC_VRS_RATE_BASE_BASE_IDX', 'regPA_SC_VRS_RATE_BASE_EXT', - 'regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX', - 'regPA_SC_VRS_RATE_CACHE_CNTL', - 'regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT', - 'regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX', - 'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY', - 'regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX', - 'regPA_SC_VRS_RATE_SIZE_XY', 'regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX', - 'regPA_SC_VRS_SURFACE_CNTL', 'regPA_SC_VRS_SURFACE_CNTL_1', - 'regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX', - 'regPA_SC_VRS_SURFACE_CNTL_BASE_IDX', 'regPA_SC_WINDOW_OFFSET', - 'regPA_SC_WINDOW_OFFSET_BASE_IDX', 'regPA_SC_WINDOW_SCISSOR_BR', - 'regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', - 'regPA_SC_WINDOW_SCISSOR_TL', - 'regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', 'regPA_STATE_STEREO_X', - 'regPA_STATE_STEREO_X_BASE_IDX', 'regPA_STEREO_CNTL', - 'regPA_STEREO_CNTL_BASE_IDX', 'regPA_SU_CNTL_STATUS', - 'regPA_SU_CNTL_STATUS_BASE_IDX', - 'regPA_SU_HARDWARE_SCREEN_OFFSET', - 'regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'regPA_SU_LINE_CNTL', - 'regPA_SU_LINE_CNTL_BASE_IDX', 'regPA_SU_LINE_STIPPLE_CNTL', - 'regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX', - 'regPA_SU_LINE_STIPPLE_SCALE', - 'regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX', - 'regPA_SU_LINE_STIPPLE_VALUE', - 'regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX', - 'regPA_SU_OVER_RASTERIZATION_CNTL', - 'regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_HI', 'regPA_SU_PERFCOUNTER0_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_LO', 'regPA_SU_PERFCOUNTER0_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_SELECT', 'regPA_SU_PERFCOUNTER0_SELECT1', - 'regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_HI', 'regPA_SU_PERFCOUNTER1_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_LO', 'regPA_SU_PERFCOUNTER1_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_SELECT', 'regPA_SU_PERFCOUNTER1_SELECT1', - 'regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_HI', 'regPA_SU_PERFCOUNTER2_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_LO', 'regPA_SU_PERFCOUNTER2_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_SELECT', 'regPA_SU_PERFCOUNTER2_SELECT1', - 'regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_HI', 'regPA_SU_PERFCOUNTER3_HI_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_LO', 'regPA_SU_PERFCOUNTER3_LO_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_SELECT', 'regPA_SU_PERFCOUNTER3_SELECT1', - 'regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'regPA_SU_POINT_MINMAX', - 'regPA_SU_POINT_MINMAX_BASE_IDX', 'regPA_SU_POINT_SIZE', - 'regPA_SU_POINT_SIZE_BASE_IDX', - 'regPA_SU_POLY_OFFSET_BACK_OFFSET', - 'regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX', - 'regPA_SU_POLY_OFFSET_BACK_SCALE', - 'regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX', - 'regPA_SU_POLY_OFFSET_CLAMP', - 'regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX', - 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL', - 'regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX', - 'regPA_SU_POLY_OFFSET_FRONT_OFFSET', - 'regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX', - 'regPA_SU_POLY_OFFSET_FRONT_SCALE', - 'regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX', - 'regPA_SU_PRIM_FILTER_CNTL', 'regPA_SU_PRIM_FILTER_CNTL_BASE_IDX', - 'regPA_SU_SC_MODE_CNTL', 'regPA_SU_SC_MODE_CNTL_BASE_IDX', - 'regPA_SU_SMALL_PRIM_FILTER_CNTL', - 'regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'regPA_SU_VTX_CNTL', - 'regPA_SU_VTX_CNTL_BASE_IDX', 'regPCC_PERF_COUNTER', - 'regPCC_PERF_COUNTER_BASE_IDX', 'regPCC_PWRBRK_HYSTERESIS_CTRL', - 'regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX', - 'regPCC_STALL_PATTERN_1_2', 'regPCC_STALL_PATTERN_1_2_BASE_IDX', - 'regPCC_STALL_PATTERN_3_4', 'regPCC_STALL_PATTERN_3_4_BASE_IDX', - 'regPCC_STALL_PATTERN_5_6', 'regPCC_STALL_PATTERN_5_6_BASE_IDX', - 'regPCC_STALL_PATTERN_7', 'regPCC_STALL_PATTERN_7_BASE_IDX', - 'regPCC_STALL_PATTERN_CTRL', 'regPCC_STALL_PATTERN_CTRL_BASE_IDX', - 'regPC_PERFCOUNTER0_HI', 'regPC_PERFCOUNTER0_HI_BASE_IDX', - 'regPC_PERFCOUNTER0_LO', 'regPC_PERFCOUNTER0_LO_BASE_IDX', - 'regPC_PERFCOUNTER0_SELECT', 'regPC_PERFCOUNTER0_SELECT1', - 'regPC_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER0_SELECT_BASE_IDX', 'regPC_PERFCOUNTER1_HI', - 'regPC_PERFCOUNTER1_HI_BASE_IDX', 'regPC_PERFCOUNTER1_LO', - 'regPC_PERFCOUNTER1_LO_BASE_IDX', 'regPC_PERFCOUNTER1_SELECT', - 'regPC_PERFCOUNTER1_SELECT1', - 'regPC_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER1_SELECT_BASE_IDX', 'regPC_PERFCOUNTER2_HI', - 'regPC_PERFCOUNTER2_HI_BASE_IDX', 'regPC_PERFCOUNTER2_LO', - 'regPC_PERFCOUNTER2_LO_BASE_IDX', 'regPC_PERFCOUNTER2_SELECT', - 'regPC_PERFCOUNTER2_SELECT1', - 'regPC_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER2_SELECT_BASE_IDX', 'regPC_PERFCOUNTER3_HI', - 'regPC_PERFCOUNTER3_HI_BASE_IDX', 'regPC_PERFCOUNTER3_LO', - 'regPC_PERFCOUNTER3_LO_BASE_IDX', 'regPC_PERFCOUNTER3_SELECT', - 'regPC_PERFCOUNTER3_SELECT1', - 'regPC_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regPC_PERFCOUNTER3_SELECT_BASE_IDX', 'regPMM_CNTL', - 'regPMM_CNTL2', 'regPMM_CNTL2_BASE_IDX', 'regPMM_CNTL_BASE_IDX', - 'regPMM_STATUS', 'regPMM_STATUS_BASE_IDX', - 'regPWRBRK_PERF_COUNTER', 'regPWRBRK_PERF_COUNTER_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_1_2', - 'regPWRBRK_STALL_PATTERN_1_2_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_3_4', - 'regPWRBRK_STALL_PATTERN_3_4_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_5_6', - 'regPWRBRK_STALL_PATTERN_5_6_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_7', 'regPWRBRK_STALL_PATTERN_7_BASE_IDX', - 'regPWRBRK_STALL_PATTERN_CTRL', - 'regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX', 'regRLC_AUTO_PG_CTRL', - 'regRLC_AUTO_PG_CTRL_BASE_IDX', 'regRLC_BUSY_CLK_CNTL', - 'regRLC_BUSY_CLK_CNTL_BASE_IDX', 'regRLC_CAC_MASK_CNTL', - 'regRLC_CAC_MASK_CNTL_BASE_IDX', 'regRLC_CAPTURE_GPU_CLOCK_COUNT', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX', - 'regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', - 'regRLC_CGCG_CGLS_CTRL', 'regRLC_CGCG_CGLS_CTRL_3D', - 'regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX', - 'regRLC_CGCG_CGLS_CTRL_BASE_IDX', 'regRLC_CGCG_RAMP_CTRL', - 'regRLC_CGCG_RAMP_CTRL_3D', 'regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX', - 'regRLC_CGCG_RAMP_CTRL_BASE_IDX', 'regRLC_CGTT_MGCG_OVERRIDE', - 'regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'regRLC_CLK_CNTL', - 'regRLC_CLK_CNTL_BASE_IDX', 'regRLC_CLK_COUNT_CTRL', - 'regRLC_CLK_COUNT_CTRL_BASE_IDX', 'regRLC_CLK_COUNT_GFXCLK_LSB', - 'regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX', - 'regRLC_CLK_COUNT_GFXCLK_MSB', - 'regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX', - 'regRLC_CLK_COUNT_REFCLK_LSB', - 'regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX', - 'regRLC_CLK_COUNT_REFCLK_MSB', - 'regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'regRLC_CLK_COUNT_STAT', - 'regRLC_CLK_COUNT_STAT_BASE_IDX', - 'regRLC_CLK_RESIDENCY_CNTR_CTRL', - 'regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_CLK_RESIDENCY_EVENT_CNTR', - 'regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_CLK_RESIDENCY_REF_CNTR', - 'regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_CNTL', - 'regRLC_CNTL_BASE_IDX', 'regRLC_CP_EOF_INT', - 'regRLC_CP_EOF_INT_BASE_IDX', 'regRLC_CP_EOF_INT_CNT', - 'regRLC_CP_EOF_INT_CNT_BASE_IDX', 'regRLC_CP_SCHEDULERS', - 'regRLC_CP_SCHEDULERS_BASE_IDX', 'regRLC_CP_STAT_INVAL_CTRL', - 'regRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'regRLC_CP_STAT_INVAL_STAT', - 'regRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'regRLC_CSIB_ADDR_HI', - 'regRLC_CSIB_ADDR_HI_BASE_IDX', 'regRLC_CSIB_ADDR_LO', - 'regRLC_CSIB_ADDR_LO_BASE_IDX', 'regRLC_CSIB_LENGTH', - 'regRLC_CSIB_LENGTH_BASE_IDX', 'regRLC_DS_RESIDENCY_CNTR_CTRL', - 'regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_DS_RESIDENCY_EVENT_CNTR', - 'regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_DS_RESIDENCY_REF_CNTR', - 'regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_DYN_PG_REQUEST', - 'regRLC_DYN_PG_REQUEST_BASE_IDX', 'regRLC_DYN_PG_STATUS', - 'regRLC_DYN_PG_STATUS_BASE_IDX', 'regRLC_F32_UCODE_VERSION', - 'regRLC_F32_UCODE_VERSION_BASE_IDX', 'regRLC_FWL_FIRST_VIOL_ADDR', - 'regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', - 'regRLC_GENERAL_RESIDENCY_CNTR_CTRL', - 'regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_GENERAL_RESIDENCY_EVENT_CNTR', - 'regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_GENERAL_RESIDENCY_REF_CNTR', - 'regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX', - 'regRLC_GFX_IH_ARBITER_STAT', - 'regRLC_GFX_IH_ARBITER_STAT_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_CTRL', 'regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_OTHER_STAT', - 'regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_SDMA_STAT', - 'regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_SE_STAT_H', - 'regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX', - 'regRLC_GFX_IH_CLIENT_SE_STAT_L', - 'regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX', 'regRLC_GFX_IMU_CMD', - 'regRLC_GFX_IMU_CMD_BASE_IDX', 'regRLC_GFX_IMU_DATA_0', - 'regRLC_GFX_IMU_DATA_0_BASE_IDX', 'regRLC_GPM_CP_DMA_COMPLETE_T0', - 'regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX', - 'regRLC_GPM_CP_DMA_COMPLETE_T1', - 'regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'regRLC_GPM_GENERAL_0', - 'regRLC_GPM_GENERAL_0_BASE_IDX', 'regRLC_GPM_GENERAL_1', - 'regRLC_GPM_GENERAL_10', 'regRLC_GPM_GENERAL_10_BASE_IDX', - 'regRLC_GPM_GENERAL_11', 'regRLC_GPM_GENERAL_11_BASE_IDX', - 'regRLC_GPM_GENERAL_12', 'regRLC_GPM_GENERAL_12_BASE_IDX', - 'regRLC_GPM_GENERAL_13', 'regRLC_GPM_GENERAL_13_BASE_IDX', - 'regRLC_GPM_GENERAL_14', 'regRLC_GPM_GENERAL_14_BASE_IDX', - 'regRLC_GPM_GENERAL_15', 'regRLC_GPM_GENERAL_15_BASE_IDX', - 'regRLC_GPM_GENERAL_16', 'regRLC_GPM_GENERAL_16_BASE_IDX', - 'regRLC_GPM_GENERAL_1_BASE_IDX', 'regRLC_GPM_GENERAL_2', - 'regRLC_GPM_GENERAL_2_BASE_IDX', 'regRLC_GPM_GENERAL_3', - 'regRLC_GPM_GENERAL_3_BASE_IDX', 'regRLC_GPM_GENERAL_4', - 'regRLC_GPM_GENERAL_4_BASE_IDX', 'regRLC_GPM_GENERAL_5', - 'regRLC_GPM_GENERAL_5_BASE_IDX', 'regRLC_GPM_GENERAL_6', - 'regRLC_GPM_GENERAL_6_BASE_IDX', 'regRLC_GPM_GENERAL_7', - 'regRLC_GPM_GENERAL_7_BASE_IDX', 'regRLC_GPM_GENERAL_8', - 'regRLC_GPM_GENERAL_8_BASE_IDX', 'regRLC_GPM_GENERAL_9', - 'regRLC_GPM_GENERAL_9_BASE_IDX', 'regRLC_GPM_INT_DISABLE_TH0', - 'regRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'regRLC_GPM_INT_FORCE_TH0', - 'regRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'regRLC_GPM_INT_STAT_TH0', - 'regRLC_GPM_INT_STAT_TH0_BASE_IDX', 'regRLC_GPM_IRAM_ADDR', - 'regRLC_GPM_IRAM_ADDR_BASE_IDX', 'regRLC_GPM_IRAM_DATA', - 'regRLC_GPM_IRAM_DATA_BASE_IDX', 'regRLC_GPM_LEGACY_INT_CLEAR', - 'regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX', - 'regRLC_GPM_LEGACY_INT_DISABLE', - 'regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX', - 'regRLC_GPM_LEGACY_INT_STAT', - 'regRLC_GPM_LEGACY_INT_STAT_BASE_IDX', 'regRLC_GPM_PERF_COUNT_0', - 'regRLC_GPM_PERF_COUNT_0_BASE_IDX', 'regRLC_GPM_PERF_COUNT_1', - 'regRLC_GPM_PERF_COUNT_1_BASE_IDX', 'regRLC_GPM_SCRATCH_ADDR', - 'regRLC_GPM_SCRATCH_ADDR_BASE_IDX', 'regRLC_GPM_SCRATCH_DATA', - 'regRLC_GPM_SCRATCH_DATA_BASE_IDX', 'regRLC_GPM_STAT', - 'regRLC_GPM_STAT_BASE_IDX', 'regRLC_GPM_THREAD_ENABLE', - 'regRLC_GPM_THREAD_ENABLE_BASE_IDX', - 'regRLC_GPM_THREAD_INVALIDATE_CACHE', - 'regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX', - 'regRLC_GPM_THREAD_PRIORITY', - 'regRLC_GPM_THREAD_PRIORITY_BASE_IDX', 'regRLC_GPM_THREAD_RESET', - 'regRLC_GPM_THREAD_RESET_BASE_IDX', 'regRLC_GPM_TIMER_CTRL', - 'regRLC_GPM_TIMER_CTRL_BASE_IDX', 'regRLC_GPM_TIMER_INT_0', - 'regRLC_GPM_TIMER_INT_0_BASE_IDX', 'regRLC_GPM_TIMER_INT_1', - 'regRLC_GPM_TIMER_INT_1_BASE_IDX', 'regRLC_GPM_TIMER_INT_2', - 'regRLC_GPM_TIMER_INT_2_BASE_IDX', 'regRLC_GPM_TIMER_INT_3', - 'regRLC_GPM_TIMER_INT_3_BASE_IDX', 'regRLC_GPM_TIMER_INT_4', - 'regRLC_GPM_TIMER_INT_4_BASE_IDX', 'regRLC_GPM_TIMER_STAT', - 'regRLC_GPM_TIMER_STAT_BASE_IDX', 'regRLC_GPM_UCODE_ADDR', - 'regRLC_GPM_UCODE_ADDR_BASE_IDX', 'regRLC_GPM_UCODE_DATA', - 'regRLC_GPM_UCODE_DATA_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_0', - 'regRLC_GPM_UTCL1_CNTL_0_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_1', - 'regRLC_GPM_UTCL1_CNTL_1_BASE_IDX', 'regRLC_GPM_UTCL1_CNTL_2', - 'regRLC_GPM_UTCL1_CNTL_2_BASE_IDX', - 'regRLC_GPM_UTCL1_TH0_ERROR_1', - 'regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX', - 'regRLC_GPM_UTCL1_TH0_ERROR_2', - 'regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX', - 'regRLC_GPM_UTCL1_TH1_ERROR_1', - 'regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX', - 'regRLC_GPM_UTCL1_TH1_ERROR_2', - 'regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX', - 'regRLC_GPM_UTCL1_TH2_ERROR_1', - 'regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX', - 'regRLC_GPM_UTCL1_TH2_ERROR_2', - 'regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'regRLC_GPR_REG1', - 'regRLC_GPR_REG1_BASE_IDX', 'regRLC_GPR_REG2', - 'regRLC_GPR_REG2_BASE_IDX', 'regRLC_GPU_CLOCK_32', - 'regRLC_GPU_CLOCK_32_BASE_IDX', 'regRLC_GPU_CLOCK_32_RES_SEL', - 'regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_LSB', 'regRLC_GPU_CLOCK_COUNT_LSB_1', - 'regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_LSB_2', - 'regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_MSB', 'regRLC_GPU_CLOCK_COUNT_MSB_1', - 'regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_MSB_2', - 'regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_SPM_LSB', - 'regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX', - 'regRLC_GPU_CLOCK_COUNT_SPM_MSB', - 'regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG1', 'regRLC_GPU_IOV_CFG_REG1_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG2', 'regRLC_GPU_IOV_CFG_REG2_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG6', 'regRLC_GPU_IOV_CFG_REG6_BASE_IDX', - 'regRLC_GPU_IOV_CFG_REG8', 'regRLC_GPU_IOV_CFG_REG8_BASE_IDX', - 'regRLC_GPU_IOV_F32_CNTL', 'regRLC_GPU_IOV_F32_CNTL_BASE_IDX', - 'regRLC_GPU_IOV_F32_INVALIDATE_CACHE', - 'regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX', - 'regRLC_GPU_IOV_F32_RESET', 'regRLC_GPU_IOV_F32_RESET_BASE_IDX', - 'regRLC_GPU_IOV_INT_DISABLE', - 'regRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'regRLC_GPU_IOV_INT_FORCE', - 'regRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'regRLC_GPU_IOV_INT_STAT', - 'regRLC_GPU_IOV_INT_STAT_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_CNTL', - 'regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR', - 'regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_RD_DATA', - 'regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR', - 'regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_PERF_CNT_WR_DATA', - 'regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX', - 'regRLC_GPU_IOV_RLC_RESPONSE', - 'regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'regRLC_GPU_IOV_SCH_0', - 'regRLC_GPU_IOV_SCH_0_BASE_IDX', 'regRLC_GPU_IOV_SCH_1', - 'regRLC_GPU_IOV_SCH_1_BASE_IDX', 'regRLC_GPU_IOV_SCH_2', - 'regRLC_GPU_IOV_SCH_2_BASE_IDX', 'regRLC_GPU_IOV_SCH_3', - 'regRLC_GPU_IOV_SCH_3_BASE_IDX', 'regRLC_GPU_IOV_SCH_BLOCK', - 'regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', - 'regRLC_GPU_IOV_SCRATCH_ADDR', - 'regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_SCRATCH_DATA', - 'regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX', - 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA0_STATUS', - 'regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA1_STATUS', - 'regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA2_STATUS', - 'regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA3_STATUS', - 'regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA4_STATUS', - 'regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA5_STATUS', - 'regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA6_STATUS', - 'regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS', - 'regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SDMA7_STATUS', - 'regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_SMU_RESPONSE', - 'regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', - 'regRLC_GPU_IOV_UCODE_ADDR', 'regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', - 'regRLC_GPU_IOV_UCODE_DATA', 'regRLC_GPU_IOV_UCODE_DATA_BASE_IDX', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET', - 'regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX', - 'regRLC_GPU_IOV_VF_ENABLE', 'regRLC_GPU_IOV_VF_ENABLE_BASE_IDX', - 'regRLC_GPU_IOV_VF_MASK', 'regRLC_GPU_IOV_VF_MASK_BASE_IDX', - 'regRLC_GPU_IOV_VM_BUSY_STATUS', - 'regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'regRLC_GTS_OFFSET_LSB', - 'regRLC_GTS_OFFSET_LSB_BASE_IDX', 'regRLC_GTS_OFFSET_MSB', - 'regRLC_GTS_OFFSET_MSB_BASE_IDX', 'regRLC_HYP_RLCG_UCODE_CHKSUM', - 'regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX', - 'regRLC_HYP_RLCP_UCODE_CHKSUM', - 'regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX', - 'regRLC_HYP_RLCV_UCODE_CHKSUM', - 'regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'regRLC_HYP_SEMAPHORE_0', - 'regRLC_HYP_SEMAPHORE_0_BASE_IDX', 'regRLC_HYP_SEMAPHORE_1', - 'regRLC_HYP_SEMAPHORE_1_BASE_IDX', 'regRLC_HYP_SEMAPHORE_2', - 'regRLC_HYP_SEMAPHORE_2_BASE_IDX', 'regRLC_HYP_SEMAPHORE_3', - 'regRLC_HYP_SEMAPHORE_3_BASE_IDX', 'regRLC_IH_COOKIE', - 'regRLC_IH_COOKIE_BASE_IDX', 'regRLC_IH_COOKIE_CNTL', - 'regRLC_IH_COOKIE_CNTL_BASE_IDX', 'regRLC_IMU_BOOTLOAD_ADDR_HI', - 'regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX', - 'regRLC_IMU_BOOTLOAD_ADDR_LO', - 'regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX', - 'regRLC_IMU_BOOTLOAD_SIZE', 'regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX', - 'regRLC_IMU_MISC', 'regRLC_IMU_MISC_BASE_IDX', - 'regRLC_IMU_RESET_VECTOR', 'regRLC_IMU_RESET_VECTOR_BASE_IDX', - 'regRLC_INT_STAT', 'regRLC_INT_STAT_BASE_IDX', - 'regRLC_JUMP_TABLE_RESTORE', 'regRLC_JUMP_TABLE_RESTORE_BASE_IDX', - 'regRLC_LX6_CNTL', 'regRLC_LX6_CNTL_BASE_IDX', - 'regRLC_LX6_DRAM_ADDR', 'regRLC_LX6_DRAM_ADDR_BASE_IDX', - 'regRLC_LX6_DRAM_DATA', 'regRLC_LX6_DRAM_DATA_BASE_IDX', - 'regRLC_LX6_IRAM_ADDR', 'regRLC_LX6_IRAM_ADDR_BASE_IDX', - 'regRLC_LX6_IRAM_DATA', 'regRLC_LX6_IRAM_DATA_BASE_IDX', - 'regRLC_MAX_PG_WGP', 'regRLC_MAX_PG_WGP_BASE_IDX', - 'regRLC_MEM_SLP_CNTL', 'regRLC_MEM_SLP_CNTL_BASE_IDX', - 'regRLC_MGCG_CTRL', 'regRLC_MGCG_CTRL_BASE_IDX', - 'regRLC_PACE_INT_CLEAR', 'regRLC_PACE_INT_CLEAR_BASE_IDX', - 'regRLC_PACE_INT_DISABLE', 'regRLC_PACE_INT_DISABLE_BASE_IDX', - 'regRLC_PACE_INT_FORCE', 'regRLC_PACE_INT_FORCE_BASE_IDX', - 'regRLC_PACE_INT_STAT', 'regRLC_PACE_INT_STAT_BASE_IDX', - 'regRLC_PACE_SCRATCH_ADDR', 'regRLC_PACE_SCRATCH_ADDR_BASE_IDX', - 'regRLC_PACE_SCRATCH_DATA', 'regRLC_PACE_SCRATCH_DATA_BASE_IDX', - 'regRLC_PACE_SPARE_INT', 'regRLC_PACE_SPARE_INT_1', - 'regRLC_PACE_SPARE_INT_1_BASE_IDX', - 'regRLC_PACE_SPARE_INT_BASE_IDX', 'regRLC_PACE_TIMER_CTRL', - 'regRLC_PACE_TIMER_CTRL_BASE_IDX', 'regRLC_PACE_TIMER_INT_0', - 'regRLC_PACE_TIMER_INT_0_BASE_IDX', 'regRLC_PACE_TIMER_INT_1', - 'regRLC_PACE_TIMER_INT_1_BASE_IDX', 'regRLC_PACE_TIMER_STAT', - 'regRLC_PACE_TIMER_STAT_BASE_IDX', 'regRLC_PACE_UCODE_ADDR', - 'regRLC_PACE_UCODE_ADDR_BASE_IDX', 'regRLC_PACE_UCODE_DATA', - 'regRLC_PACE_UCODE_DATA_BASE_IDX', - 'regRLC_PCC_RESIDENCY_CNTR_CTRL', - 'regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_PCC_RESIDENCY_EVENT_CNTR', - 'regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_PCC_RESIDENCY_REF_CNTR', - 'regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX', - 'regRLC_PERFCOUNTER0_HI', 'regRLC_PERFCOUNTER0_HI_BASE_IDX', - 'regRLC_PERFCOUNTER0_LO', 'regRLC_PERFCOUNTER0_LO_BASE_IDX', - 'regRLC_PERFCOUNTER0_SELECT', - 'regRLC_PERFCOUNTER0_SELECT_BASE_IDX', 'regRLC_PERFCOUNTER1_HI', - 'regRLC_PERFCOUNTER1_HI_BASE_IDX', 'regRLC_PERFCOUNTER1_LO', - 'regRLC_PERFCOUNTER1_LO_BASE_IDX', 'regRLC_PERFCOUNTER1_SELECT', - 'regRLC_PERFCOUNTER1_SELECT_BASE_IDX', 'regRLC_PERFMON_CNTL', - 'regRLC_PERFMON_CNTL_BASE_IDX', 'regRLC_PG_ALWAYS_ON_WGP_MASK', - 'regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'regRLC_PG_CNTL', - 'regRLC_PG_CNTL_BASE_IDX', 'regRLC_PG_DELAY', 'regRLC_PG_DELAY_2', - 'regRLC_PG_DELAY_2_BASE_IDX', 'regRLC_PG_DELAY_3', - 'regRLC_PG_DELAY_3_BASE_IDX', 'regRLC_PG_DELAY_BASE_IDX', - 'regRLC_POWER_RESIDENCY_CNTR_CTRL', - 'regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_POWER_RESIDENCY_EVENT_CNTR', - 'regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_POWER_RESIDENCY_REF_CNTR', - 'regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_R2I_CNTL_0', - 'regRLC_R2I_CNTL_0_BASE_IDX', 'regRLC_R2I_CNTL_1', - 'regRLC_R2I_CNTL_1_BASE_IDX', 'regRLC_R2I_CNTL_2', - 'regRLC_R2I_CNTL_2_BASE_IDX', 'regRLC_R2I_CNTL_3', - 'regRLC_R2I_CNTL_3_BASE_IDX', 'regRLC_REFCLOCK_TIMESTAMP_LSB', - 'regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX', - 'regRLC_REFCLOCK_TIMESTAMP_MSB', - 'regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX', - 'regRLC_RLCG_DOORBELL_0_DATA_HI', - 'regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_0_DATA_LO', - 'regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_1_DATA_HI', - 'regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_1_DATA_LO', - 'regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_2_DATA_HI', - 'regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_2_DATA_LO', - 'regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_3_DATA_HI', - 'regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_RLCG_DOORBELL_3_DATA_LO', - 'regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_RLCG_DOORBELL_CNTL', 'regRLC_RLCG_DOORBELL_CNTL_BASE_IDX', - 'regRLC_RLCG_DOORBELL_RANGE', - 'regRLC_RLCG_DOORBELL_RANGE_BASE_IDX', - 'regRLC_RLCG_DOORBELL_STAT', 'regRLC_RLCG_DOORBELL_STAT_BASE_IDX', - 'regRLC_RLCP_DOORBELL_0_DATA_HI', - 'regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_0_DATA_LO', - 'regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_1_DATA_HI', - 'regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_1_DATA_LO', - 'regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_2_DATA_HI', - 'regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_2_DATA_LO', - 'regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_3_DATA_HI', - 'regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_RLCP_DOORBELL_3_DATA_LO', - 'regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_RLCP_DOORBELL_CNTL', 'regRLC_RLCP_DOORBELL_CNTL_BASE_IDX', - 'regRLC_RLCP_DOORBELL_RANGE', - 'regRLC_RLCP_DOORBELL_RANGE_BASE_IDX', - 'regRLC_RLCP_DOORBELL_STAT', 'regRLC_RLCP_DOORBELL_STAT_BASE_IDX', - 'regRLC_RLCP_IRAM_ADDR', 'regRLC_RLCP_IRAM_ADDR_BASE_IDX', - 'regRLC_RLCP_IRAM_DATA', 'regRLC_RLCP_IRAM_DATA_BASE_IDX', - 'regRLC_RLCS_ABORTED_PD_SEQUENCE', - 'regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_1', - 'regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_2', - 'regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_3', - 'regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX', - 'regRLC_RLCS_AUXILIARY_REG_4', - 'regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS1', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS2', - 'regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX', - 'regRLC_RLCS_BOOTLOAD_STATUS', - 'regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX', - 'regRLC_RLCS_CGCG_REQUEST', 'regRLC_RLCS_CGCG_REQUEST_BASE_IDX', - 'regRLC_RLCS_CGCG_STATUS', 'regRLC_RLCS_CGCG_STATUS_BASE_IDX', - 'regRLC_RLCS_CMP_IDLE_CNTL', 'regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX', - 'regRLC_RLCS_CP_DMA_SRCID_OVER', - 'regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX', - 'regRLC_RLCS_CP_INT_CTRL_1', 'regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX', - 'regRLC_RLCS_CP_INT_CTRL_2', 'regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX', - 'regRLC_RLCS_CP_INT_INFO_1', 'regRLC_RLCS_CP_INT_INFO_1_BASE_IDX', - 'regRLC_RLCS_CP_INT_INFO_2', 'regRLC_RLCS_CP_INT_INFO_2_BASE_IDX', - 'regRLC_RLCS_DEC_DUMP_ADDR', 'regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX', - 'regRLC_RLCS_DEC_END', 'regRLC_RLCS_DEC_END_BASE_IDX', - 'regRLC_RLCS_DEC_START', 'regRLC_RLCS_DEC_START_BASE_IDX', - 'regRLC_RLCS_DIDT_FORCE_STALL', - 'regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'regRLC_RLCS_DSM_TRIG', - 'regRLC_RLCS_DSM_TRIG_BASE_IDX', 'regRLC_RLCS_EDC_INT_CNTL', - 'regRLC_RLCS_EDC_INT_CNTL_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_1', - 'regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_2', - 'regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_3', - 'regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX', - 'regRLC_RLCS_EXCEPTION_REG_4', - 'regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'regRLC_RLCS_GCR_DATA_0', - 'regRLC_RLCS_GCR_DATA_0_BASE_IDX', 'regRLC_RLCS_GCR_DATA_1', - 'regRLC_RLCS_GCR_DATA_1_BASE_IDX', 'regRLC_RLCS_GCR_DATA_2', - 'regRLC_RLCS_GCR_DATA_2_BASE_IDX', 'regRLC_RLCS_GCR_DATA_3', - 'regRLC_RLCS_GCR_DATA_3_BASE_IDX', 'regRLC_RLCS_GCR_STATUS', - 'regRLC_RLCS_GCR_STATUS_BASE_IDX', 'regRLC_RLCS_GENERAL_0', - 'regRLC_RLCS_GENERAL_0_BASE_IDX', 'regRLC_RLCS_GENERAL_1', - 'regRLC_RLCS_GENERAL_10', 'regRLC_RLCS_GENERAL_10_BASE_IDX', - 'regRLC_RLCS_GENERAL_11', 'regRLC_RLCS_GENERAL_11_BASE_IDX', - 'regRLC_RLCS_GENERAL_12', 'regRLC_RLCS_GENERAL_12_BASE_IDX', - 'regRLC_RLCS_GENERAL_13', 'regRLC_RLCS_GENERAL_13_BASE_IDX', - 'regRLC_RLCS_GENERAL_14', 'regRLC_RLCS_GENERAL_14_BASE_IDX', - 'regRLC_RLCS_GENERAL_15', 'regRLC_RLCS_GENERAL_15_BASE_IDX', - 'regRLC_RLCS_GENERAL_16', 'regRLC_RLCS_GENERAL_16_BASE_IDX', - 'regRLC_RLCS_GENERAL_1_BASE_IDX', 'regRLC_RLCS_GENERAL_2', - 'regRLC_RLCS_GENERAL_2_BASE_IDX', 'regRLC_RLCS_GENERAL_3', - 'regRLC_RLCS_GENERAL_3_BASE_IDX', 'regRLC_RLCS_GENERAL_4', - 'regRLC_RLCS_GENERAL_4_BASE_IDX', 'regRLC_RLCS_GENERAL_5', - 'regRLC_RLCS_GENERAL_5_BASE_IDX', 'regRLC_RLCS_GENERAL_6', - 'regRLC_RLCS_GENERAL_6_BASE_IDX', 'regRLC_RLCS_GENERAL_7', - 'regRLC_RLCS_GENERAL_7_BASE_IDX', 'regRLC_RLCS_GENERAL_8', - 'regRLC_RLCS_GENERAL_8_BASE_IDX', 'regRLC_RLCS_GENERAL_9', - 'regRLC_RLCS_GENERAL_9_BASE_IDX', - 'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL', - 'regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX', - 'regRLC_RLCS_GFX_DS_CNTL', 'regRLC_RLCS_GFX_DS_CNTL_BASE_IDX', - 'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO', - 'regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX', - 'regRLC_RLCS_GFX_RM_CNTL', 'regRLC_RLCS_GFX_RM_CNTL_BASE_IDX', - 'regRLC_RLCS_GPM_LEGACY_INT_DISABLE', - 'regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX', - 'regRLC_RLCS_GPM_LEGACY_INT_STAT', - 'regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX', - 'regRLC_RLCS_GPM_STAT', 'regRLC_RLCS_GPM_STAT_2', - 'regRLC_RLCS_GPM_STAT_2_BASE_IDX', - 'regRLC_RLCS_GPM_STAT_BASE_IDX', - 'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL', - 'regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX', - 'regRLC_RLCS_GRBM_IDLE_BUSY_STAT', - 'regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX', - 'regRLC_RLCS_GRBM_SOFT_RESET', - 'regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX', - 'regRLC_RLCS_IH_COOKIE_SEMAPHORE', - 'regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX', - 'regRLC_RLCS_IH_SEMAPHORE', 'regRLC_RLCS_IH_SEMAPHORE_BASE_IDX', - 'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE', - 'regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_0_LSB', - 'regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_0_MSB', - 'regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_1_LSB', - 'regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_ADDR_1_MSB', - 'regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_CNTL', 'regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_DATA_0', - 'regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX', - 'regRLC_RLCS_IMU_RAM_DATA_1', - 'regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_CNTL', - 'regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_CONTROL', - 'regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA0', - 'regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA1', - 'regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA2', - 'regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA3', - 'regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MSG_DATA4', - 'regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_MUTEX_CNTL', - 'regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_STATUS', - 'regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1', - 'regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX', - 'regRLC_RLCS_IMU_VIDCHG_CNTL', - 'regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX', - 'regRLC_RLCS_IOV_CMD_STATUS', - 'regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX', - 'regRLC_RLCS_IOV_CNTX_LOC_SIZE', - 'regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX', - 'regRLC_RLCS_IOV_SCH_BLOCK', 'regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX', - 'regRLC_RLCS_IOV_VM_BUSY_STATUS', - 'regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX', - 'regRLC_RLCS_KMD_LOG_CNTL1', 'regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX', - 'regRLC_RLCS_KMD_LOG_CNTL2', 'regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX', - 'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE', - 'regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX', - 'regRLC_RLCS_PG_CHANGE_READ', - 'regRLC_RLCS_PG_CHANGE_READ_BASE_IDX', - 'regRLC_RLCS_PG_CHANGE_STATUS', - 'regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX', - 'regRLC_RLCS_PMM_CGCG_CNTL', 'regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX', - 'regRLC_RLCS_POWER_BRAKE_CNTL', - 'regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX', - 'regRLC_RLCS_POWER_BRAKE_CNTL_TH1', - 'regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_MSG_CNTL', - 'regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_MSG_CONTROL', - 'regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_MSG_DATA0', - 'regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX', - 'regRLC_RLCS_RLC_IMU_STATUS', - 'regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_CNTL_1', - 'regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_CNTL_2', - 'regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_INFO', 'regRLC_RLCS_SDMA_INT_INFO_BASE_IDX', - 'regRLC_RLCS_SDMA_INT_STAT', 'regRLC_RLCS_SDMA_INT_STAT_BASE_IDX', - 'regRLC_RLCS_SOC_DS_CNTL', 'regRLC_RLCS_SOC_DS_CNTL_BASE_IDX', - 'regRLC_RLCS_SPM_INT_CTRL', 'regRLC_RLCS_SPM_INT_CTRL_BASE_IDX', - 'regRLC_RLCS_SPM_INT_INFO_1', - 'regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX', - 'regRLC_RLCS_SPM_INT_INFO_2', - 'regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX', - 'regRLC_RLCS_SPM_SQTT_MODE', 'regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX', - 'regRLC_RLCS_SRM_SRCID_CNTL', - 'regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'regRLC_RLCS_UTCL2_CNTL', - 'regRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'regRLC_RLCS_WGP_READ', - 'regRLC_RLCS_WGP_READ_BASE_IDX', 'regRLC_RLCS_WGP_STATUS', - 'regRLC_RLCS_WGP_STATUS_BASE_IDX', 'regRLC_RLCV_COMMAND', - 'regRLC_RLCV_COMMAND_BASE_IDX', 'regRLC_RLCV_DOORBELL_0_DATA_HI', - 'regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_0_DATA_LO', - 'regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_1_DATA_HI', - 'regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_1_DATA_LO', - 'regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_2_DATA_HI', - 'regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_2_DATA_LO', - 'regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_3_DATA_HI', - 'regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_RLCV_DOORBELL_3_DATA_LO', - 'regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_RLCV_DOORBELL_CNTL', 'regRLC_RLCV_DOORBELL_CNTL_BASE_IDX', - 'regRLC_RLCV_DOORBELL_RANGE', - 'regRLC_RLCV_DOORBELL_RANGE_BASE_IDX', - 'regRLC_RLCV_DOORBELL_STAT', 'regRLC_RLCV_DOORBELL_STAT_BASE_IDX', - 'regRLC_RLCV_IRAM_ADDR', 'regRLC_RLCV_IRAM_ADDR_BASE_IDX', - 'regRLC_RLCV_IRAM_DATA', 'regRLC_RLCV_IRAM_DATA_BASE_IDX', - 'regRLC_RLCV_SAFE_MODE', 'regRLC_RLCV_SAFE_MODE_BASE_IDX', - 'regRLC_RLCV_SPARE_INT', 'regRLC_RLCV_SPARE_INT_1', - 'regRLC_RLCV_SPARE_INT_1_BASE_IDX', - 'regRLC_RLCV_SPARE_INT_BASE_IDX', 'regRLC_RLCV_TIMER_CTRL', - 'regRLC_RLCV_TIMER_CTRL_BASE_IDX', 'regRLC_RLCV_TIMER_INT_0', - 'regRLC_RLCV_TIMER_INT_0_BASE_IDX', 'regRLC_RLCV_TIMER_INT_1', - 'regRLC_RLCV_TIMER_INT_1_BASE_IDX', 'regRLC_RLCV_TIMER_STAT', - 'regRLC_RLCV_TIMER_STAT_BASE_IDX', 'regRLC_SAFE_MODE', - 'regRLC_SAFE_MODE_BASE_IDX', 'regRLC_SDMA0_BUSY_STATUS', - 'regRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA0_STATUS', - 'regRLC_SDMA0_STATUS_BASE_IDX', 'regRLC_SDMA1_BUSY_STATUS', - 'regRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA1_STATUS', - 'regRLC_SDMA1_STATUS_BASE_IDX', 'regRLC_SDMA2_BUSY_STATUS', - 'regRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA2_STATUS', - 'regRLC_SDMA2_STATUS_BASE_IDX', 'regRLC_SDMA3_BUSY_STATUS', - 'regRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'regRLC_SDMA3_STATUS', - 'regRLC_SDMA3_STATUS_BASE_IDX', 'regRLC_SEMAPHORE_0', - 'regRLC_SEMAPHORE_0_BASE_IDX', 'regRLC_SEMAPHORE_1', - 'regRLC_SEMAPHORE_1_BASE_IDX', 'regRLC_SEMAPHORE_2', - 'regRLC_SEMAPHORE_2_BASE_IDX', 'regRLC_SEMAPHORE_3', - 'regRLC_SEMAPHORE_3_BASE_IDX', 'regRLC_SERDES_BUSY', - 'regRLC_SERDES_BUSY_BASE_IDX', 'regRLC_SERDES_CTRL', - 'regRLC_SERDES_CTRL_BASE_IDX', 'regRLC_SERDES_DATA', - 'regRLC_SERDES_DATA_BASE_IDX', 'regRLC_SERDES_MASK', - 'regRLC_SERDES_MASK_BASE_IDX', 'regRLC_SERDES_RD_DATA_0', - 'regRLC_SERDES_RD_DATA_0_BASE_IDX', 'regRLC_SERDES_RD_DATA_1', - 'regRLC_SERDES_RD_DATA_1_BASE_IDX', 'regRLC_SERDES_RD_DATA_2', - 'regRLC_SERDES_RD_DATA_2_BASE_IDX', 'regRLC_SERDES_RD_DATA_3', - 'regRLC_SERDES_RD_DATA_3_BASE_IDX', 'regRLC_SERDES_RD_INDEX', - 'regRLC_SERDES_RD_INDEX_BASE_IDX', 'regRLC_SMU_ARGUMENT_1', - 'regRLC_SMU_ARGUMENT_1_BASE_IDX', 'regRLC_SMU_ARGUMENT_2', - 'regRLC_SMU_ARGUMENT_2_BASE_IDX', 'regRLC_SMU_ARGUMENT_3', - 'regRLC_SMU_ARGUMENT_3_BASE_IDX', 'regRLC_SMU_ARGUMENT_4', - 'regRLC_SMU_ARGUMENT_4_BASE_IDX', 'regRLC_SMU_ARGUMENT_5', - 'regRLC_SMU_ARGUMENT_5_BASE_IDX', 'regRLC_SMU_CLK_REQ', - 'regRLC_SMU_CLK_REQ_BASE_IDX', 'regRLC_SMU_COMMAND', - 'regRLC_SMU_COMMAND_BASE_IDX', 'regRLC_SMU_MESSAGE', - 'regRLC_SMU_MESSAGE_1', 'regRLC_SMU_MESSAGE_1_BASE_IDX', - 'regRLC_SMU_MESSAGE_2', 'regRLC_SMU_MESSAGE_2_BASE_IDX', - 'regRLC_SMU_MESSAGE_BASE_IDX', 'regRLC_SMU_SAFE_MODE', - 'regRLC_SMU_SAFE_MODE_BASE_IDX', 'regRLC_SPARE', - 'regRLC_SPARE_BASE_IDX', 'regRLC_SPARE_INT_0', - 'regRLC_SPARE_INT_0_BASE_IDX', 'regRLC_SPARE_INT_1', - 'regRLC_SPARE_INT_1_BASE_IDX', 'regRLC_SPARE_INT_2', - 'regRLC_SPARE_INT_2_BASE_IDX', 'regRLC_SPM_ACCUM_CTRL', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET', - 'regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX', - 'regRLC_SPM_ACCUM_CTRLRAM_DATA', - 'regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX', - 'regRLC_SPM_ACCUM_CTRL_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS', - 'regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_ADDR', - 'regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_DATA', - 'regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX', - 'regRLC_SPM_ACCUM_DATARAM_WRCOUNT', - 'regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX', - 'regRLC_SPM_ACCUM_MODE', 'regRLC_SPM_ACCUM_MODE_BASE_IDX', - 'regRLC_SPM_ACCUM_SAMPLES_REQUESTED', - 'regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX', - 'regRLC_SPM_ACCUM_STATUS', 'regRLC_SPM_ACCUM_STATUS_BASE_IDX', - 'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR', - 'regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX', - 'regRLC_SPM_ACCUM_SWA_DATARAM_DATA', - 'regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX', - 'regRLC_SPM_ACCUM_THRESHOLD', - 'regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX', - 'regRLC_SPM_GFXCLOCK_HIGHCOUNT', - 'regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX', - 'regRLC_SPM_GFXCLOCK_LOWCOUNT', - 'regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX', - 'regRLC_SPM_GLOBAL_DELAY_IND_ADDR', - 'regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX', - 'regRLC_SPM_GLOBAL_DELAY_IND_DATA', - 'regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX', - 'regRLC_SPM_GLOBAL_MUXSEL_ADDR', - 'regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX', - 'regRLC_SPM_GLOBAL_MUXSEL_DATA', - 'regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'regRLC_SPM_INT_CNTL', - 'regRLC_SPM_INT_CNTL_BASE_IDX', 'regRLC_SPM_INT_INFO_1', - 'regRLC_SPM_INT_INFO_1_BASE_IDX', 'regRLC_SPM_INT_INFO_2', - 'regRLC_SPM_INT_INFO_2_BASE_IDX', 'regRLC_SPM_INT_STATUS', - 'regRLC_SPM_INT_STATUS_BASE_IDX', 'regRLC_SPM_MC_CNTL', - 'regRLC_SPM_MC_CNTL_BASE_IDX', 'regRLC_SPM_MODE', - 'regRLC_SPM_MODE_BASE_IDX', 'regRLC_SPM_PAUSE', - 'regRLC_SPM_PAUSE_BASE_IDX', 'regRLC_SPM_PERFMON_CNTL', - 'regRLC_SPM_PERFMON_CNTL_BASE_IDX', - 'regRLC_SPM_PERFMON_RING_BASE_HI', - 'regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX', - 'regRLC_SPM_PERFMON_RING_BASE_LO', - 'regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX', - 'regRLC_SPM_PERFMON_RING_SIZE', - 'regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX', - 'regRLC_SPM_PERFMON_SEGMENT_SIZE', - 'regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX', - 'regRLC_SPM_RING_RDPTR', 'regRLC_SPM_RING_RDPTR_BASE_IDX', - 'regRLC_SPM_RING_WRPTR', 'regRLC_SPM_RING_WRPTR_BASE_IDX', - 'regRLC_SPM_RSPM_CMD', 'regRLC_SPM_RSPM_CMD_ACK', - 'regRLC_SPM_RSPM_CMD_ACK_BASE_IDX', - 'regRLC_SPM_RSPM_CMD_BASE_IDX', 'regRLC_SPM_RSPM_REQ_DATA_HI', - 'regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX', - 'regRLC_SPM_RSPM_REQ_DATA_LO', - 'regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX', 'regRLC_SPM_RSPM_REQ_OP', - 'regRLC_SPM_RSPM_REQ_OP_BASE_IDX', 'regRLC_SPM_RSPM_RET_DATA', - 'regRLC_SPM_RSPM_RET_DATA_BASE_IDX', 'regRLC_SPM_RSPM_RET_OP', - 'regRLC_SPM_RSPM_RET_OP_BASE_IDX', 'regRLC_SPM_SAMPLE_CNT', - 'regRLC_SPM_SAMPLE_CNT_BASE_IDX', 'regRLC_SPM_SEGMENT_THRESHOLD', - 'regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX', - 'regRLC_SPM_SE_DELAY_IND_ADDR', - 'regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX', - 'regRLC_SPM_SE_DELAY_IND_DATA', - 'regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX', - 'regRLC_SPM_SE_MUXSEL_ADDR', 'regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX', - 'regRLC_SPM_SE_MUXSEL_DATA', 'regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX', - 'regRLC_SPM_SE_RSPM_REQ_DATA_HI', - 'regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX', - 'regRLC_SPM_SE_RSPM_REQ_DATA_LO', - 'regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX', - 'regRLC_SPM_SE_RSPM_REQ_OP', 'regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX', - 'regRLC_SPM_SE_RSPM_RET_DATA', - 'regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX', - 'regRLC_SPM_SE_RSPM_RET_OP', 'regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX', - 'regRLC_SPM_SPARE', 'regRLC_SPM_SPARE_BASE_IDX', - 'regRLC_SPM_STATUS', 'regRLC_SPM_STATUS_BASE_IDX', - 'regRLC_SPM_THREAD_TRACE_CTRL', - 'regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'regRLC_SPM_UTCL1_CNTL', - 'regRLC_SPM_UTCL1_CNTL_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_1', - 'regRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'regRLC_SPM_UTCL1_ERROR_2', - 'regRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'regRLC_SPP_CAM_ADDR', - 'regRLC_SPP_CAM_ADDR_BASE_IDX', 'regRLC_SPP_CAM_DATA', - 'regRLC_SPP_CAM_DATA_BASE_IDX', 'regRLC_SPP_CAM_EXT_ADDR', - 'regRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'regRLC_SPP_CAM_EXT_DATA', - 'regRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'regRLC_SPP_CTRL', - 'regRLC_SPP_CTRL_BASE_IDX', 'regRLC_SPP_GLOBAL_SH_ID', - 'regRLC_SPP_GLOBAL_SH_ID_BASE_IDX', - 'regRLC_SPP_GLOBAL_SH_ID_VALID', - 'regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX', - 'regRLC_SPP_INFLIGHT_RD_ADDR', - 'regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX', - 'regRLC_SPP_INFLIGHT_RD_DATA', - 'regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'regRLC_SPP_PBB_INFO', - 'regRLC_SPP_PBB_INFO_BASE_IDX', 'regRLC_SPP_PROF_INFO_1', - 'regRLC_SPP_PROF_INFO_1_BASE_IDX', 'regRLC_SPP_PROF_INFO_2', - 'regRLC_SPP_PROF_INFO_2_BASE_IDX', 'regRLC_SPP_PVT_LEVEL_MAX', - 'regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'regRLC_SPP_PVT_STAT_0', - 'regRLC_SPP_PVT_STAT_0_BASE_IDX', 'regRLC_SPP_PVT_STAT_1', - 'regRLC_SPP_PVT_STAT_1_BASE_IDX', 'regRLC_SPP_PVT_STAT_2', - 'regRLC_SPP_PVT_STAT_2_BASE_IDX', 'regRLC_SPP_PVT_STAT_3', - 'regRLC_SPP_PVT_STAT_3_BASE_IDX', 'regRLC_SPP_RESET', - 'regRLC_SPP_RESET_BASE_IDX', 'regRLC_SPP_SHADER_PROFILE_EN', - 'regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX', - 'regRLC_SPP_SSF_CAPTURE_EN', 'regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX', - 'regRLC_SPP_SSF_THRESHOLD_0', - 'regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX', - 'regRLC_SPP_SSF_THRESHOLD_1', - 'regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX', - 'regRLC_SPP_SSF_THRESHOLD_2', - 'regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX', - 'regRLC_SPP_STALL_STATE_UPDATE', - 'regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'regRLC_SPP_STATUS', - 'regRLC_SPP_STATUS_BASE_IDX', 'regRLC_SRM_ARAM_ADDR', - 'regRLC_SRM_ARAM_ADDR_BASE_IDX', 'regRLC_SRM_ARAM_DATA', - 'regRLC_SRM_ARAM_DATA_BASE_IDX', 'regRLC_SRM_CNTL', - 'regRLC_SRM_CNTL_BASE_IDX', 'regRLC_SRM_DRAM_ADDR', - 'regRLC_SRM_DRAM_ADDR_BASE_IDX', 'regRLC_SRM_DRAM_DATA', - 'regRLC_SRM_DRAM_DATA_BASE_IDX', 'regRLC_SRM_GPM_ABORT', - 'regRLC_SRM_GPM_ABORT_BASE_IDX', 'regRLC_SRM_GPM_COMMAND', - 'regRLC_SRM_GPM_COMMAND_BASE_IDX', - 'regRLC_SRM_GPM_COMMAND_STATUS', - 'regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_0', - 'regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_1', - 'regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_2', - 'regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_3', - 'regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_4', - 'regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_5', - 'regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_6', - 'regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_ADDR_7', - 'regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_0', - 'regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_1', - 'regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_2', - 'regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_3', - 'regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_4', - 'regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_5', - 'regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_6', - 'regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX', - 'regRLC_SRM_INDEX_CNTL_DATA_7', - 'regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'regRLC_SRM_STAT', - 'regRLC_SRM_STAT_BASE_IDX', 'regRLC_STAT', - 'regRLC_STATIC_PG_STATUS', 'regRLC_STATIC_PG_STATUS_BASE_IDX', - 'regRLC_STAT_BASE_IDX', 'regRLC_UCODE_CNTL', - 'regRLC_UCODE_CNTL_BASE_IDX', 'regRLC_ULV_RESIDENCY_CNTR_CTRL', - 'regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX', - 'regRLC_ULV_RESIDENCY_EVENT_CNTR', - 'regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX', - 'regRLC_ULV_RESIDENCY_REF_CNTR', - 'regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX', 'regRLC_UTCL1_STATUS', - 'regRLC_UTCL1_STATUS_2', 'regRLC_UTCL1_STATUS_2_BASE_IDX', - 'regRLC_UTCL1_STATUS_BASE_IDX', 'regRLC_WGP_STATUS', - 'regRLC_WGP_STATUS_BASE_IDX', 'regRLC_XT_CORE_ALT_RESET_VEC', - 'regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX', - 'regRLC_XT_CORE_FAULT_INFO', 'regRLC_XT_CORE_FAULT_INFO_BASE_IDX', - 'regRLC_XT_CORE_INTERRUPT', 'regRLC_XT_CORE_INTERRUPT_BASE_IDX', - 'regRLC_XT_CORE_RESERVED', 'regRLC_XT_CORE_RESERVED_BASE_IDX', - 'regRLC_XT_CORE_STATUS', 'regRLC_XT_CORE_STATUS_BASE_IDX', - 'regRLC_XT_DOORBELL_0_DATA_HI', - 'regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_0_DATA_LO', - 'regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_1_DATA_HI', - 'regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_1_DATA_LO', - 'regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_2_DATA_HI', - 'regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_2_DATA_LO', - 'regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_3_DATA_HI', - 'regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX', - 'regRLC_XT_DOORBELL_3_DATA_LO', - 'regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX', - 'regRLC_XT_DOORBELL_CNTL', 'regRLC_XT_DOORBELL_CNTL_BASE_IDX', - 'regRLC_XT_DOORBELL_RANGE', 'regRLC_XT_DOORBELL_RANGE_BASE_IDX', - 'regRLC_XT_DOORBELL_STAT', 'regRLC_XT_DOORBELL_STAT_BASE_IDX', - 'regRLC_XT_INT_VEC_CLEAR', 'regRLC_XT_INT_VEC_CLEAR_BASE_IDX', - 'regRLC_XT_INT_VEC_FORCE', 'regRLC_XT_INT_VEC_FORCE_BASE_IDX', - 'regRLC_XT_INT_VEC_MUX_INT_SEL', - 'regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX', - 'regRLC_XT_INT_VEC_MUX_SEL', 'regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX', - 'regRMI_CLOCK_CNTRL', 'regRMI_CLOCK_CNTRL_BASE_IDX', - 'regRMI_DEMUX_CNTL', 'regRMI_DEMUX_CNTL_BASE_IDX', - 'regRMI_GENERAL_CNTL', 'regRMI_GENERAL_CNTL1', - 'regRMI_GENERAL_CNTL1_BASE_IDX', 'regRMI_GENERAL_CNTL_BASE_IDX', - 'regRMI_GENERAL_STATUS', 'regRMI_GENERAL_STATUS_BASE_IDX', - 'regRMI_PERFCOUNTER0_HI', 'regRMI_PERFCOUNTER0_HI_BASE_IDX', - 'regRMI_PERFCOUNTER0_LO', 'regRMI_PERFCOUNTER0_LO_BASE_IDX', - 'regRMI_PERFCOUNTER0_SELECT', 'regRMI_PERFCOUNTER0_SELECT1', - 'regRMI_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER1_HI', - 'regRMI_PERFCOUNTER1_HI_BASE_IDX', 'regRMI_PERFCOUNTER1_LO', - 'regRMI_PERFCOUNTER1_LO_BASE_IDX', 'regRMI_PERFCOUNTER1_SELECT', - 'regRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER2_HI', - 'regRMI_PERFCOUNTER2_HI_BASE_IDX', 'regRMI_PERFCOUNTER2_LO', - 'regRMI_PERFCOUNTER2_LO_BASE_IDX', 'regRMI_PERFCOUNTER2_SELECT', - 'regRMI_PERFCOUNTER2_SELECT1', - 'regRMI_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'regRMI_PERFCOUNTER3_HI', - 'regRMI_PERFCOUNTER3_HI_BASE_IDX', 'regRMI_PERFCOUNTER3_LO', - 'regRMI_PERFCOUNTER3_LO_BASE_IDX', 'regRMI_PERFCOUNTER3_SELECT', - 'regRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'regRMI_PERF_COUNTER_CNTL', - 'regRMI_PERF_COUNTER_CNTL_BASE_IDX', - 'regRMI_PROBE_POP_LOGIC_CNTL', - 'regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'regRMI_RB_GLX_CID_MAP', - 'regRMI_RB_GLX_CID_MAP_BASE_IDX', 'regRMI_SCOREBOARD_CNTL', - 'regRMI_SCOREBOARD_CNTL_BASE_IDX', 'regRMI_SCOREBOARD_STATUS0', - 'regRMI_SCOREBOARD_STATUS0_BASE_IDX', 'regRMI_SCOREBOARD_STATUS1', - 'regRMI_SCOREBOARD_STATUS1_BASE_IDX', 'regRMI_SCOREBOARD_STATUS2', - 'regRMI_SCOREBOARD_STATUS2_BASE_IDX', 'regRMI_SPARE', - 'regRMI_SPARE_1', 'regRMI_SPARE_1_BASE_IDX', 'regRMI_SPARE_2', - 'regRMI_SPARE_2_BASE_IDX', 'regRMI_SPARE_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS0', 'regRMI_SUBBLOCK_STATUS0_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS1', 'regRMI_SUBBLOCK_STATUS1_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS2', 'regRMI_SUBBLOCK_STATUS2_BASE_IDX', - 'regRMI_SUBBLOCK_STATUS3', 'regRMI_SUBBLOCK_STATUS3_BASE_IDX', - 'regRMI_TCIW_FORMATTER0_CNTL', - 'regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX', - 'regRMI_TCIW_FORMATTER1_CNTL', - 'regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'regRMI_UTCL1_CNTL1', - 'regRMI_UTCL1_CNTL1_BASE_IDX', 'regRMI_UTCL1_CNTL2', - 'regRMI_UTCL1_CNTL2_BASE_IDX', 'regRMI_UTCL1_STATUS', - 'regRMI_UTCL1_STATUS_BASE_IDX', 'regRMI_UTC_UNIT_CONFIG', - 'regRMI_UTC_UNIT_CONFIG_BASE_IDX', 'regRMI_UTC_XNACK_N_MISC_CNTL', - 'regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX', - 'regRMI_XBAR_ARBITER_CONFIG', 'regRMI_XBAR_ARBITER_CONFIG_1', - 'regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX', - 'regRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'regRMI_XBAR_CONFIG', - 'regRMI_XBAR_CONFIG_BASE_IDX', 'regRTAVFS_RTAVFS_REG_ADDR', - 'regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'regRTAVFS_RTAVFS_WR_DATA', - 'regRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'regSCRATCH_REG0', - 'regSCRATCH_REG0_BASE_IDX', 'regSCRATCH_REG1', - 'regSCRATCH_REG1_BASE_IDX', 'regSCRATCH_REG2', - 'regSCRATCH_REG2_BASE_IDX', 'regSCRATCH_REG3', - 'regSCRATCH_REG3_BASE_IDX', 'regSCRATCH_REG4', - 'regSCRATCH_REG4_BASE_IDX', 'regSCRATCH_REG5', - 'regSCRATCH_REG5_BASE_IDX', 'regSCRATCH_REG6', - 'regSCRATCH_REG6_BASE_IDX', 'regSCRATCH_REG7', - 'regSCRATCH_REG7_BASE_IDX', 'regSCRATCH_REG_ATOMIC', - 'regSCRATCH_REG_ATOMIC_BASE_IDX', 'regSCRATCH_REG_CMPSWAP_ATOMIC', - 'regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'regSDMA0_AQL_STATUS', - 'regSDMA0_AQL_STATUS_BASE_IDX', 'regSDMA0_ATOMIC_CNTL', - 'regSDMA0_ATOMIC_CNTL_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_HI', - 'regSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA0_ATOMIC_PREOP_LO', - 'regSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA0_BA_THRESHOLD', - 'regSDMA0_BA_THRESHOLD_BASE_IDX', 'regSDMA0_BROADCAST_UCODE_ADDR', - 'regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX', - 'regSDMA0_BROADCAST_UCODE_DATA', - 'regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA0_CE_CTRL', - 'regSDMA0_CE_CTRL_BASE_IDX', 'regSDMA0_CHICKEN_BITS', - 'regSDMA0_CHICKEN_BITS_2', 'regSDMA0_CHICKEN_BITS_2_BASE_IDX', - 'regSDMA0_CHICKEN_BITS_BASE_IDX', 'regSDMA0_CLOCK_GATING_STATUS', - 'regSDMA0_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA0_CNTL', - 'regSDMA0_CNTL1', 'regSDMA0_CNTL1_BASE_IDX', - 'regSDMA0_CNTL_BASE_IDX', 'regSDMA0_CRD_CNTL', - 'regSDMA0_CRD_CNTL_BASE_IDX', 'regSDMA0_DEC_START', - 'regSDMA0_DEC_START_BASE_IDX', 'regSDMA0_EA_DBIT_ADDR_DATA', - 'regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX', - 'regSDMA0_EA_DBIT_ADDR_INDEX', - 'regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA0_EDC_CONFIG', - 'regSDMA0_EDC_CONFIG_BASE_IDX', 'regSDMA0_EDC_COUNTER', - 'regSDMA0_EDC_COUNTER_BASE_IDX', 'regSDMA0_EDC_COUNTER_CLEAR', - 'regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA0_ERROR_LOG', - 'regSDMA0_ERROR_LOG_BASE_IDX', 'regSDMA0_F32_CNTL', - 'regSDMA0_F32_CNTL_BASE_IDX', 'regSDMA0_F32_COUNTER', - 'regSDMA0_F32_COUNTER_BASE_IDX', 'regSDMA0_F32_MISC_CNTL', - 'regSDMA0_F32_MISC_CNTL_BASE_IDX', 'regSDMA0_FED_STATUS', - 'regSDMA0_FED_STATUS_BASE_IDX', 'regSDMA0_FREEZE', - 'regSDMA0_FREEZE_BASE_IDX', 'regSDMA0_GB_ADDR_CONFIG', - 'regSDMA0_GB_ADDR_CONFIG_BASE_IDX', - 'regSDMA0_GB_ADDR_CONFIG_READ', - 'regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX', - 'regSDMA0_GLOBAL_QUANTUM', 'regSDMA0_GLOBAL_QUANTUM_BASE_IDX', - 'regSDMA0_GLOBAL_TIMESTAMP_HI', - 'regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'regSDMA0_GLOBAL_TIMESTAMP_LO', - 'regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX', - 'regSDMA0_HBM_PAGE_CONFIG', 'regSDMA0_HBM_PAGE_CONFIG_BASE_IDX', - 'regSDMA0_HOLE_ADDR_HI', 'regSDMA0_HOLE_ADDR_HI_BASE_IDX', - 'regSDMA0_HOLE_ADDR_LO', 'regSDMA0_HOLE_ADDR_LO_BASE_IDX', - 'regSDMA0_IB_OFFSET_FETCH', 'regSDMA0_IB_OFFSET_FETCH_BASE_IDX', - 'regSDMA0_ID', 'regSDMA0_ID_BASE_IDX', 'regSDMA0_INT_STATUS', - 'regSDMA0_INT_STATUS_BASE_IDX', 'regSDMA0_PERFCNT_MISC_CNTL', - 'regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER0_CFG', - 'regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER1_CFG', - 'regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER_HI', - 'regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER_LO', - 'regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_HI', 'regSDMA0_PERFCOUNTER0_HI_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_LO', 'regSDMA0_PERFCOUNTER0_LO_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_SELECT', 'regSDMA0_PERFCOUNTER0_SELECT1', - 'regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_HI', 'regSDMA0_PERFCOUNTER1_HI_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_LO', 'regSDMA0_PERFCOUNTER1_LO_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_SELECT', 'regSDMA0_PERFCOUNTER1_SELECT1', - 'regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX', - 'regSDMA0_PHYSICAL_ADDR_HI', 'regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX', - 'regSDMA0_PHYSICAL_ADDR_LO', 'regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX', - 'regSDMA0_POWER_CNTL', 'regSDMA0_POWER_CNTL_BASE_IDX', - 'regSDMA0_PROCESS_QUANTUM0', 'regSDMA0_PROCESS_QUANTUM0_BASE_IDX', - 'regSDMA0_PROCESS_QUANTUM1', 'regSDMA0_PROCESS_QUANTUM1_BASE_IDX', - 'regSDMA0_PROGRAM', 'regSDMA0_PROGRAM_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG0', 'regSDMA0_PUB_DUMMY_REG0_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG1', 'regSDMA0_PUB_DUMMY_REG1_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG2', 'regSDMA0_PUB_DUMMY_REG2_BASE_IDX', - 'regSDMA0_PUB_DUMMY_REG3', 'regSDMA0_PUB_DUMMY_REG3_BASE_IDX', - 'regSDMA0_QUEUE0_CONTEXT_STATUS', - 'regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE0_CSA_ADDR_HI', - 'regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_CSA_ADDR_LO', - 'regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE0_DOORBELL', 'regSDMA0_QUEUE0_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE0_DOORBELL_LOG', - 'regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE0_DOORBELL_OFFSET', - 'regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE0_DUMMY_REG', 'regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE0_IB_BASE_HI', - 'regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE0_IB_BASE_LO', - 'regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE0_IB_CNTL', - 'regSDMA0_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_IB_OFFSET', - 'regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE0_IB_RPTR', - 'regSDMA0_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_IB_SIZE', - 'regSDMA0_QUEUE0_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE0_IB_SUB_REMAIN', - 'regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_CNTL', - 'regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA0', - 'regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA1', 'regSDMA0_QUEUE0_MIDCMD_DATA10', - 'regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA2', - 'regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA3', - 'regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA4', - 'regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA5', - 'regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA6', - 'regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA7', - 'regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA8', - 'regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE0_MIDCMD_DATA9', - 'regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE0_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE0_PREEMPT', 'regSDMA0_QUEUE0_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE0_RB_AQL_CNTL', - 'regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE', - 'regSDMA0_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE0_RB_BASE_HI', - 'regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_CNTL', - 'regSDMA0_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE0_RB_PREEMPT', - 'regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_RPTR_HI', - 'regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR', - 'regSDMA0_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE0_RB_WPTR_HI', - 'regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE0_SCHEDULE_CNTL', - 'regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE0_SKIP_CNTL', 'regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE1_CONTEXT_STATUS', - 'regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE1_CSA_ADDR_HI', - 'regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_CSA_ADDR_LO', - 'regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE1_DOORBELL', 'regSDMA0_QUEUE1_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE1_DOORBELL_LOG', - 'regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE1_DOORBELL_OFFSET', - 'regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE1_DUMMY_REG', 'regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE1_IB_BASE_HI', - 'regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE1_IB_BASE_LO', - 'regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE1_IB_CNTL', - 'regSDMA0_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_IB_OFFSET', - 'regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE1_IB_RPTR', - 'regSDMA0_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_IB_SIZE', - 'regSDMA0_QUEUE1_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE1_IB_SUB_REMAIN', - 'regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_CNTL', - 'regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA0', - 'regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA1', 'regSDMA0_QUEUE1_MIDCMD_DATA10', - 'regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA2', - 'regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA3', - 'regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA4', - 'regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA5', - 'regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA6', - 'regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA7', - 'regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA8', - 'regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE1_MIDCMD_DATA9', - 'regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE1_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE1_PREEMPT', 'regSDMA0_QUEUE1_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE1_RB_AQL_CNTL', - 'regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE', - 'regSDMA0_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE1_RB_BASE_HI', - 'regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_CNTL', - 'regSDMA0_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE1_RB_PREEMPT', - 'regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_RPTR_HI', - 'regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR', - 'regSDMA0_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE1_RB_WPTR_HI', - 'regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE1_SCHEDULE_CNTL', - 'regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE1_SKIP_CNTL', 'regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE2_CONTEXT_STATUS', - 'regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE2_CSA_ADDR_HI', - 'regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_CSA_ADDR_LO', - 'regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE2_DOORBELL', 'regSDMA0_QUEUE2_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE2_DOORBELL_LOG', - 'regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE2_DOORBELL_OFFSET', - 'regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE2_DUMMY_REG', 'regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE2_IB_BASE_HI', - 'regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE2_IB_BASE_LO', - 'regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE2_IB_CNTL', - 'regSDMA0_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_IB_OFFSET', - 'regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE2_IB_RPTR', - 'regSDMA0_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_IB_SIZE', - 'regSDMA0_QUEUE2_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE2_IB_SUB_REMAIN', - 'regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_CNTL', - 'regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA0', - 'regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA1', 'regSDMA0_QUEUE2_MIDCMD_DATA10', - 'regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA2', - 'regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA3', - 'regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA4', - 'regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA5', - 'regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA6', - 'regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA7', - 'regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA8', - 'regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE2_MIDCMD_DATA9', - 'regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE2_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE2_PREEMPT', 'regSDMA0_QUEUE2_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE2_RB_AQL_CNTL', - 'regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE', - 'regSDMA0_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE2_RB_BASE_HI', - 'regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_CNTL', - 'regSDMA0_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE2_RB_PREEMPT', - 'regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_RPTR_HI', - 'regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR', - 'regSDMA0_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE2_RB_WPTR_HI', - 'regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE2_SCHEDULE_CNTL', - 'regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE2_SKIP_CNTL', 'regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE3_CONTEXT_STATUS', - 'regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE3_CSA_ADDR_HI', - 'regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_CSA_ADDR_LO', - 'regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE3_DOORBELL', 'regSDMA0_QUEUE3_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE3_DOORBELL_LOG', - 'regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE3_DOORBELL_OFFSET', - 'regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE3_DUMMY_REG', 'regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE3_IB_BASE_HI', - 'regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE3_IB_BASE_LO', - 'regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE3_IB_CNTL', - 'regSDMA0_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_IB_OFFSET', - 'regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE3_IB_RPTR', - 'regSDMA0_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_IB_SIZE', - 'regSDMA0_QUEUE3_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE3_IB_SUB_REMAIN', - 'regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_CNTL', - 'regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA0', - 'regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA1', 'regSDMA0_QUEUE3_MIDCMD_DATA10', - 'regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA2', - 'regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA3', - 'regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA4', - 'regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA5', - 'regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA6', - 'regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA7', - 'regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA8', - 'regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE3_MIDCMD_DATA9', - 'regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE3_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE3_PREEMPT', 'regSDMA0_QUEUE3_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE3_RB_AQL_CNTL', - 'regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE', - 'regSDMA0_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE3_RB_BASE_HI', - 'regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_CNTL', - 'regSDMA0_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE3_RB_PREEMPT', - 'regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_RPTR_HI', - 'regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR', - 'regSDMA0_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE3_RB_WPTR_HI', - 'regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE3_SCHEDULE_CNTL', - 'regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE3_SKIP_CNTL', 'regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE4_CONTEXT_STATUS', - 'regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE4_CSA_ADDR_HI', - 'regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_CSA_ADDR_LO', - 'regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE4_DOORBELL', 'regSDMA0_QUEUE4_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE4_DOORBELL_LOG', - 'regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE4_DOORBELL_OFFSET', - 'regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE4_DUMMY_REG', 'regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE4_IB_BASE_HI', - 'regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE4_IB_BASE_LO', - 'regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE4_IB_CNTL', - 'regSDMA0_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_IB_OFFSET', - 'regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE4_IB_RPTR', - 'regSDMA0_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_IB_SIZE', - 'regSDMA0_QUEUE4_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE4_IB_SUB_REMAIN', - 'regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_CNTL', - 'regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA0', - 'regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA1', 'regSDMA0_QUEUE4_MIDCMD_DATA10', - 'regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA2', - 'regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA3', - 'regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA4', - 'regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA5', - 'regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA6', - 'regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA7', - 'regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA8', - 'regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE4_MIDCMD_DATA9', - 'regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE4_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE4_PREEMPT', 'regSDMA0_QUEUE4_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE4_RB_AQL_CNTL', - 'regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE', - 'regSDMA0_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE4_RB_BASE_HI', - 'regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_CNTL', - 'regSDMA0_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE4_RB_PREEMPT', - 'regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_RPTR_HI', - 'regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR', - 'regSDMA0_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE4_RB_WPTR_HI', - 'regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE4_SCHEDULE_CNTL', - 'regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE4_SKIP_CNTL', 'regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE5_CONTEXT_STATUS', - 'regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE5_CSA_ADDR_HI', - 'regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_CSA_ADDR_LO', - 'regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE5_DOORBELL', 'regSDMA0_QUEUE5_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE5_DOORBELL_LOG', - 'regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE5_DOORBELL_OFFSET', - 'regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE5_DUMMY_REG', 'regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE5_IB_BASE_HI', - 'regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE5_IB_BASE_LO', - 'regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE5_IB_CNTL', - 'regSDMA0_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_IB_OFFSET', - 'regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE5_IB_RPTR', - 'regSDMA0_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_IB_SIZE', - 'regSDMA0_QUEUE5_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE5_IB_SUB_REMAIN', - 'regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_CNTL', - 'regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA0', - 'regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA1', 'regSDMA0_QUEUE5_MIDCMD_DATA10', - 'regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA2', - 'regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA3', - 'regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA4', - 'regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA5', - 'regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA6', - 'regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA7', - 'regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA8', - 'regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE5_MIDCMD_DATA9', - 'regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE5_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE5_PREEMPT', 'regSDMA0_QUEUE5_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE5_RB_AQL_CNTL', - 'regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE', - 'regSDMA0_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE5_RB_BASE_HI', - 'regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_CNTL', - 'regSDMA0_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE5_RB_PREEMPT', - 'regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_RPTR_HI', - 'regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR', - 'regSDMA0_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE5_RB_WPTR_HI', - 'regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE5_SCHEDULE_CNTL', - 'regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE5_SKIP_CNTL', 'regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE6_CONTEXT_STATUS', - 'regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE6_CSA_ADDR_HI', - 'regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_CSA_ADDR_LO', - 'regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE6_DOORBELL', 'regSDMA0_QUEUE6_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE6_DOORBELL_LOG', - 'regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE6_DOORBELL_OFFSET', - 'regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE6_DUMMY_REG', 'regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE6_IB_BASE_HI', - 'regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE6_IB_BASE_LO', - 'regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE6_IB_CNTL', - 'regSDMA0_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_IB_OFFSET', - 'regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE6_IB_RPTR', - 'regSDMA0_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_IB_SIZE', - 'regSDMA0_QUEUE6_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE6_IB_SUB_REMAIN', - 'regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_CNTL', - 'regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA0', - 'regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA1', 'regSDMA0_QUEUE6_MIDCMD_DATA10', - 'regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA2', - 'regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA3', - 'regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA4', - 'regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA5', - 'regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA6', - 'regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA7', - 'regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA8', - 'regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE6_MIDCMD_DATA9', - 'regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE6_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE6_PREEMPT', 'regSDMA0_QUEUE6_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE6_RB_AQL_CNTL', - 'regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE', - 'regSDMA0_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE6_RB_BASE_HI', - 'regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_CNTL', - 'regSDMA0_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE6_RB_PREEMPT', - 'regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_RPTR_HI', - 'regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR', - 'regSDMA0_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE6_RB_WPTR_HI', - 'regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE6_SCHEDULE_CNTL', - 'regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE6_SKIP_CNTL', 'regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE7_CONTEXT_STATUS', - 'regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX', - 'regSDMA0_QUEUE7_CSA_ADDR_HI', - 'regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_CSA_ADDR_LO', - 'regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE7_DOORBELL', 'regSDMA0_QUEUE7_DOORBELL_BASE_IDX', - 'regSDMA0_QUEUE7_DOORBELL_LOG', - 'regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX', - 'regSDMA0_QUEUE7_DOORBELL_OFFSET', - 'regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA0_QUEUE7_DUMMY_REG', 'regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX', - 'regSDMA0_QUEUE7_IB_BASE_HI', - 'regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX', - 'regSDMA0_QUEUE7_IB_BASE_LO', - 'regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA0_QUEUE7_IB_CNTL', - 'regSDMA0_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_IB_OFFSET', - 'regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA0_QUEUE7_IB_RPTR', - 'regSDMA0_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_IB_SIZE', - 'regSDMA0_QUEUE7_IB_SIZE_BASE_IDX', - 'regSDMA0_QUEUE7_IB_SUB_REMAIN', - 'regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_CNTL', - 'regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA0', - 'regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA1', 'regSDMA0_QUEUE7_MIDCMD_DATA10', - 'regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA2', - 'regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA3', - 'regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA4', - 'regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA5', - 'regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA6', - 'regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA7', - 'regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA8', - 'regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX', - 'regSDMA0_QUEUE7_MIDCMD_DATA9', - 'regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX', - 'regSDMA0_QUEUE7_MINOR_PTR_UPDATE', - 'regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA0_QUEUE7_PREEMPT', 'regSDMA0_QUEUE7_PREEMPT_BASE_IDX', - 'regSDMA0_QUEUE7_RB_AQL_CNTL', - 'regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE', - 'regSDMA0_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA0_QUEUE7_RB_BASE_HI', - 'regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_CNTL', - 'regSDMA0_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA0_QUEUE7_RB_PREEMPT', - 'regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO', - 'regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_RPTR_HI', - 'regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR', - 'regSDMA0_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA0_QUEUE7_RB_WPTR_HI', - 'regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO', - 'regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA0_QUEUE7_SCHEDULE_CNTL', - 'regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA0_QUEUE7_SKIP_CNTL', 'regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX', - 'regSDMA0_QUEUE_RESET_REQ', 'regSDMA0_QUEUE_RESET_REQ_BASE_IDX', - 'regSDMA0_QUEUE_STATUS0', 'regSDMA0_QUEUE_STATUS0_BASE_IDX', - 'regSDMA0_RB_RPTR_FETCH', 'regSDMA0_RB_RPTR_FETCH_BASE_IDX', - 'regSDMA0_RB_RPTR_FETCH_HI', 'regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX', - 'regSDMA0_RELAX_ORDERING_LUT', - 'regSDMA0_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA0_RLC_CGCG_CTRL', - 'regSDMA0_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA0_SCRATCH_RAM_ADDR', - 'regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA0_SCRATCH_RAM_DATA', - 'regSDMA0_SCRATCH_RAM_DATA_BASE_IDX', - 'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL', - 'regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'regSDMA0_STATUS1_REG', 'regSDMA0_STATUS1_REG_BASE_IDX', - 'regSDMA0_STATUS2_REG', 'regSDMA0_STATUS2_REG_BASE_IDX', - 'regSDMA0_STATUS3_REG', 'regSDMA0_STATUS3_REG_BASE_IDX', - 'regSDMA0_STATUS4_REG', 'regSDMA0_STATUS4_REG_BASE_IDX', - 'regSDMA0_STATUS5_REG', 'regSDMA0_STATUS5_REG_BASE_IDX', - 'regSDMA0_STATUS6_REG', 'regSDMA0_STATUS6_REG_BASE_IDX', - 'regSDMA0_STATUS_REG', 'regSDMA0_STATUS_REG_BASE_IDX', - 'regSDMA0_TILING_CONFIG', 'regSDMA0_TILING_CONFIG_BASE_IDX', - 'regSDMA0_TIMESTAMP_CNTL', 'regSDMA0_TIMESTAMP_CNTL_BASE_IDX', - 'regSDMA0_TLBI_GCR_CNTL', 'regSDMA0_TLBI_GCR_CNTL_BASE_IDX', - 'regSDMA0_UCODE1_CHECKSUM', 'regSDMA0_UCODE1_CHECKSUM_BASE_IDX', - 'regSDMA0_UCODE_ADDR', 'regSDMA0_UCODE_ADDR_BASE_IDX', - 'regSDMA0_UCODE_CHECKSUM', 'regSDMA0_UCODE_CHECKSUM_BASE_IDX', - 'regSDMA0_UCODE_DATA', 'regSDMA0_UCODE_DATA_BASE_IDX', - 'regSDMA0_UCODE_SELFLOAD_CONTROL', - 'regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA0_UTCL1_CNTL', - 'regSDMA0_UTCL1_CNTL_BASE_IDX', 'regSDMA0_UTCL1_INV0', - 'regSDMA0_UTCL1_INV0_BASE_IDX', 'regSDMA0_UTCL1_INV1', - 'regSDMA0_UTCL1_INV1_BASE_IDX', 'regSDMA0_UTCL1_INV2', - 'regSDMA0_UTCL1_INV2_BASE_IDX', 'regSDMA0_UTCL1_PAGE', - 'regSDMA0_UTCL1_PAGE_BASE_IDX', 'regSDMA0_UTCL1_RD_STATUS', - 'regSDMA0_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK0', - 'regSDMA0_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_RD_XNACK1', - 'regSDMA0_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA0_UTCL1_TIMEOUT', - 'regSDMA0_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA0_UTCL1_WATERMK', - 'regSDMA0_UTCL1_WATERMK_BASE_IDX', 'regSDMA0_UTCL1_WR_STATUS', - 'regSDMA0_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK0', - 'regSDMA0_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA0_UTCL1_WR_XNACK1', - 'regSDMA0_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA0_VERSION', - 'regSDMA0_VERSION_BASE_IDX', 'regSDMA0_WATCHDOG_CNTL', - 'regSDMA0_WATCHDOG_CNTL_BASE_IDX', 'regSDMA1_AQL_STATUS', - 'regSDMA1_AQL_STATUS_BASE_IDX', 'regSDMA1_ATOMIC_CNTL', - 'regSDMA1_ATOMIC_CNTL_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_HI', - 'regSDMA1_ATOMIC_PREOP_HI_BASE_IDX', 'regSDMA1_ATOMIC_PREOP_LO', - 'regSDMA1_ATOMIC_PREOP_LO_BASE_IDX', 'regSDMA1_BA_THRESHOLD', - 'regSDMA1_BA_THRESHOLD_BASE_IDX', 'regSDMA1_BROADCAST_UCODE_ADDR', - 'regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX', - 'regSDMA1_BROADCAST_UCODE_DATA', - 'regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX', 'regSDMA1_CE_CTRL', - 'regSDMA1_CE_CTRL_BASE_IDX', 'regSDMA1_CHICKEN_BITS', - 'regSDMA1_CHICKEN_BITS_2', 'regSDMA1_CHICKEN_BITS_2_BASE_IDX', - 'regSDMA1_CHICKEN_BITS_BASE_IDX', 'regSDMA1_CLOCK_GATING_STATUS', - 'regSDMA1_CLOCK_GATING_STATUS_BASE_IDX', 'regSDMA1_CNTL', - 'regSDMA1_CNTL1', 'regSDMA1_CNTL1_BASE_IDX', - 'regSDMA1_CNTL_BASE_IDX', 'regSDMA1_CRD_CNTL', - 'regSDMA1_CRD_CNTL_BASE_IDX', 'regSDMA1_DEC_START', - 'regSDMA1_DEC_START_BASE_IDX', 'regSDMA1_EA_DBIT_ADDR_DATA', - 'regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX', - 'regSDMA1_EA_DBIT_ADDR_INDEX', - 'regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'regSDMA1_EDC_CONFIG', - 'regSDMA1_EDC_CONFIG_BASE_IDX', 'regSDMA1_EDC_COUNTER', - 'regSDMA1_EDC_COUNTER_BASE_IDX', 'regSDMA1_EDC_COUNTER_CLEAR', - 'regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'regSDMA1_ERROR_LOG', - 'regSDMA1_ERROR_LOG_BASE_IDX', 'regSDMA1_F32_CNTL', - 'regSDMA1_F32_CNTL_BASE_IDX', 'regSDMA1_F32_COUNTER', - 'regSDMA1_F32_COUNTER_BASE_IDX', 'regSDMA1_F32_MISC_CNTL', - 'regSDMA1_F32_MISC_CNTL_BASE_IDX', 'regSDMA1_FED_STATUS', - 'regSDMA1_FED_STATUS_BASE_IDX', 'regSDMA1_FREEZE', - 'regSDMA1_FREEZE_BASE_IDX', 'regSDMA1_GB_ADDR_CONFIG', - 'regSDMA1_GB_ADDR_CONFIG_BASE_IDX', - 'regSDMA1_GB_ADDR_CONFIG_READ', - 'regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX', - 'regSDMA1_GLOBAL_QUANTUM', 'regSDMA1_GLOBAL_QUANTUM_BASE_IDX', - 'regSDMA1_GLOBAL_TIMESTAMP_HI', - 'regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX', - 'regSDMA1_GLOBAL_TIMESTAMP_LO', - 'regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX', - 'regSDMA1_HBM_PAGE_CONFIG', 'regSDMA1_HBM_PAGE_CONFIG_BASE_IDX', - 'regSDMA1_HOLE_ADDR_HI', 'regSDMA1_HOLE_ADDR_HI_BASE_IDX', - 'regSDMA1_HOLE_ADDR_LO', 'regSDMA1_HOLE_ADDR_LO_BASE_IDX', - 'regSDMA1_IB_OFFSET_FETCH', 'regSDMA1_IB_OFFSET_FETCH_BASE_IDX', - 'regSDMA1_ID', 'regSDMA1_ID_BASE_IDX', 'regSDMA1_INT_STATUS', - 'regSDMA1_INT_STATUS_BASE_IDX', 'regSDMA1_PERFCNT_MISC_CNTL', - 'regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER0_CFG', - 'regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER1_CFG', - 'regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER_HI', - 'regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER_LO', - 'regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX', - 'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL', - 'regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_HI', 'regSDMA1_PERFCOUNTER0_HI_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_LO', 'regSDMA1_PERFCOUNTER0_LO_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_SELECT', 'regSDMA1_PERFCOUNTER0_SELECT1', - 'regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_HI', 'regSDMA1_PERFCOUNTER1_HI_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_LO', 'regSDMA1_PERFCOUNTER1_LO_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_SELECT', 'regSDMA1_PERFCOUNTER1_SELECT1', - 'regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX', - 'regSDMA1_PHYSICAL_ADDR_HI', 'regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX', - 'regSDMA1_PHYSICAL_ADDR_LO', 'regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX', - 'regSDMA1_POWER_CNTL', 'regSDMA1_POWER_CNTL_BASE_IDX', - 'regSDMA1_PROCESS_QUANTUM0', 'regSDMA1_PROCESS_QUANTUM0_BASE_IDX', - 'regSDMA1_PROCESS_QUANTUM1', 'regSDMA1_PROCESS_QUANTUM1_BASE_IDX', - 'regSDMA1_PROGRAM', 'regSDMA1_PROGRAM_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG0', 'regSDMA1_PUB_DUMMY_REG0_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG1', 'regSDMA1_PUB_DUMMY_REG1_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG2', 'regSDMA1_PUB_DUMMY_REG2_BASE_IDX', - 'regSDMA1_PUB_DUMMY_REG3', 'regSDMA1_PUB_DUMMY_REG3_BASE_IDX', - 'regSDMA1_QUEUE0_CONTEXT_STATUS', - 'regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE0_CSA_ADDR_HI', - 'regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_CSA_ADDR_LO', - 'regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE0_DOORBELL', 'regSDMA1_QUEUE0_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE0_DOORBELL_LOG', - 'regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE0_DOORBELL_OFFSET', - 'regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE0_DUMMY_REG', 'regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE0_IB_BASE_HI', - 'regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE0_IB_BASE_LO', - 'regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE0_IB_CNTL', - 'regSDMA1_QUEUE0_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_IB_OFFSET', - 'regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE0_IB_RPTR', - 'regSDMA1_QUEUE0_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_IB_SIZE', - 'regSDMA1_QUEUE0_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE0_IB_SUB_REMAIN', - 'regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_CNTL', - 'regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA0', - 'regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA1', 'regSDMA1_QUEUE0_MIDCMD_DATA10', - 'regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA2', - 'regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA3', - 'regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA4', - 'regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA5', - 'regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA6', - 'regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA7', - 'regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA8', - 'regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE0_MIDCMD_DATA9', - 'regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE0_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE0_PREEMPT', 'regSDMA1_QUEUE0_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE0_RB_AQL_CNTL', - 'regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE', - 'regSDMA1_QUEUE0_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE0_RB_BASE_HI', - 'regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_CNTL', - 'regSDMA1_QUEUE0_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE0_RB_PREEMPT', - 'regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE0_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_RPTR_HI', - 'regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR', - 'regSDMA1_QUEUE0_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE0_RB_WPTR_HI', - 'regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE0_SCHEDULE_CNTL', - 'regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE0_SKIP_CNTL', 'regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE1_CONTEXT_STATUS', - 'regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE1_CSA_ADDR_HI', - 'regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_CSA_ADDR_LO', - 'regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE1_DOORBELL', 'regSDMA1_QUEUE1_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE1_DOORBELL_LOG', - 'regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE1_DOORBELL_OFFSET', - 'regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE1_DUMMY_REG', 'regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE1_IB_BASE_HI', - 'regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE1_IB_BASE_LO', - 'regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE1_IB_CNTL', - 'regSDMA1_QUEUE1_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_IB_OFFSET', - 'regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE1_IB_RPTR', - 'regSDMA1_QUEUE1_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_IB_SIZE', - 'regSDMA1_QUEUE1_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE1_IB_SUB_REMAIN', - 'regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_CNTL', - 'regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA0', - 'regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA1', 'regSDMA1_QUEUE1_MIDCMD_DATA10', - 'regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA2', - 'regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA3', - 'regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA4', - 'regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA5', - 'regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA6', - 'regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA7', - 'regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA8', - 'regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE1_MIDCMD_DATA9', - 'regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE1_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE1_PREEMPT', 'regSDMA1_QUEUE1_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE1_RB_AQL_CNTL', - 'regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE', - 'regSDMA1_QUEUE1_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE1_RB_BASE_HI', - 'regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_CNTL', - 'regSDMA1_QUEUE1_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE1_RB_PREEMPT', - 'regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE1_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_RPTR_HI', - 'regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR', - 'regSDMA1_QUEUE1_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE1_RB_WPTR_HI', - 'regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE1_SCHEDULE_CNTL', - 'regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE1_SKIP_CNTL', 'regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE2_CONTEXT_STATUS', - 'regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE2_CSA_ADDR_HI', - 'regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_CSA_ADDR_LO', - 'regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE2_DOORBELL', 'regSDMA1_QUEUE2_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE2_DOORBELL_LOG', - 'regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE2_DOORBELL_OFFSET', - 'regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE2_DUMMY_REG', 'regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE2_IB_BASE_HI', - 'regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE2_IB_BASE_LO', - 'regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE2_IB_CNTL', - 'regSDMA1_QUEUE2_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_IB_OFFSET', - 'regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE2_IB_RPTR', - 'regSDMA1_QUEUE2_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_IB_SIZE', - 'regSDMA1_QUEUE2_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE2_IB_SUB_REMAIN', - 'regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_CNTL', - 'regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA0', - 'regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA1', 'regSDMA1_QUEUE2_MIDCMD_DATA10', - 'regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA2', - 'regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA3', - 'regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA4', - 'regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA5', - 'regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA6', - 'regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA7', - 'regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA8', - 'regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE2_MIDCMD_DATA9', - 'regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE2_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE2_PREEMPT', 'regSDMA1_QUEUE2_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE2_RB_AQL_CNTL', - 'regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE', - 'regSDMA1_QUEUE2_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE2_RB_BASE_HI', - 'regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_CNTL', - 'regSDMA1_QUEUE2_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE2_RB_PREEMPT', - 'regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE2_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_RPTR_HI', - 'regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR', - 'regSDMA1_QUEUE2_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE2_RB_WPTR_HI', - 'regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE2_SCHEDULE_CNTL', - 'regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE2_SKIP_CNTL', 'regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE3_CONTEXT_STATUS', - 'regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE3_CSA_ADDR_HI', - 'regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_CSA_ADDR_LO', - 'regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE3_DOORBELL', 'regSDMA1_QUEUE3_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE3_DOORBELL_LOG', - 'regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE3_DOORBELL_OFFSET', - 'regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE3_DUMMY_REG', 'regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE3_IB_BASE_HI', - 'regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE3_IB_BASE_LO', - 'regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE3_IB_CNTL', - 'regSDMA1_QUEUE3_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_IB_OFFSET', - 'regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE3_IB_RPTR', - 'regSDMA1_QUEUE3_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_IB_SIZE', - 'regSDMA1_QUEUE3_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE3_IB_SUB_REMAIN', - 'regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_CNTL', - 'regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA0', - 'regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA1', 'regSDMA1_QUEUE3_MIDCMD_DATA10', - 'regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA2', - 'regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA3', - 'regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA4', - 'regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA5', - 'regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA6', - 'regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA7', - 'regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA8', - 'regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE3_MIDCMD_DATA9', - 'regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE3_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE3_PREEMPT', 'regSDMA1_QUEUE3_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE3_RB_AQL_CNTL', - 'regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE', - 'regSDMA1_QUEUE3_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE3_RB_BASE_HI', - 'regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_CNTL', - 'regSDMA1_QUEUE3_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE3_RB_PREEMPT', - 'regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE3_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_RPTR_HI', - 'regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR', - 'regSDMA1_QUEUE3_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE3_RB_WPTR_HI', - 'regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE3_SCHEDULE_CNTL', - 'regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE3_SKIP_CNTL', 'regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE4_CONTEXT_STATUS', - 'regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE4_CSA_ADDR_HI', - 'regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_CSA_ADDR_LO', - 'regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE4_DOORBELL', 'regSDMA1_QUEUE4_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE4_DOORBELL_LOG', - 'regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE4_DOORBELL_OFFSET', - 'regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE4_DUMMY_REG', 'regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE4_IB_BASE_HI', - 'regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE4_IB_BASE_LO', - 'regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE4_IB_CNTL', - 'regSDMA1_QUEUE4_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_IB_OFFSET', - 'regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE4_IB_RPTR', - 'regSDMA1_QUEUE4_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_IB_SIZE', - 'regSDMA1_QUEUE4_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE4_IB_SUB_REMAIN', - 'regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_CNTL', - 'regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA0', - 'regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA1', 'regSDMA1_QUEUE4_MIDCMD_DATA10', - 'regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA2', - 'regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA3', - 'regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA4', - 'regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA5', - 'regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA6', - 'regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA7', - 'regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA8', - 'regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE4_MIDCMD_DATA9', - 'regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE4_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE4_PREEMPT', 'regSDMA1_QUEUE4_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE4_RB_AQL_CNTL', - 'regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE', - 'regSDMA1_QUEUE4_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE4_RB_BASE_HI', - 'regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_CNTL', - 'regSDMA1_QUEUE4_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE4_RB_PREEMPT', - 'regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE4_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_RPTR_HI', - 'regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR', - 'regSDMA1_QUEUE4_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE4_RB_WPTR_HI', - 'regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE4_SCHEDULE_CNTL', - 'regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE4_SKIP_CNTL', 'regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE5_CONTEXT_STATUS', - 'regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE5_CSA_ADDR_HI', - 'regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_CSA_ADDR_LO', - 'regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE5_DOORBELL', 'regSDMA1_QUEUE5_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE5_DOORBELL_LOG', - 'regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE5_DOORBELL_OFFSET', - 'regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE5_DUMMY_REG', 'regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE5_IB_BASE_HI', - 'regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE5_IB_BASE_LO', - 'regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE5_IB_CNTL', - 'regSDMA1_QUEUE5_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_IB_OFFSET', - 'regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE5_IB_RPTR', - 'regSDMA1_QUEUE5_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_IB_SIZE', - 'regSDMA1_QUEUE5_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE5_IB_SUB_REMAIN', - 'regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_CNTL', - 'regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA0', - 'regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA1', 'regSDMA1_QUEUE5_MIDCMD_DATA10', - 'regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA2', - 'regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA3', - 'regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA4', - 'regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA5', - 'regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA6', - 'regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA7', - 'regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA8', - 'regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE5_MIDCMD_DATA9', - 'regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE5_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE5_PREEMPT', 'regSDMA1_QUEUE5_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE5_RB_AQL_CNTL', - 'regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE', - 'regSDMA1_QUEUE5_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE5_RB_BASE_HI', - 'regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_CNTL', - 'regSDMA1_QUEUE5_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE5_RB_PREEMPT', - 'regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE5_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_RPTR_HI', - 'regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR', - 'regSDMA1_QUEUE5_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE5_RB_WPTR_HI', - 'regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE5_SCHEDULE_CNTL', - 'regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE5_SKIP_CNTL', 'regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE6_CONTEXT_STATUS', - 'regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE6_CSA_ADDR_HI', - 'regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_CSA_ADDR_LO', - 'regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE6_DOORBELL', 'regSDMA1_QUEUE6_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE6_DOORBELL_LOG', - 'regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE6_DOORBELL_OFFSET', - 'regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE6_DUMMY_REG', 'regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE6_IB_BASE_HI', - 'regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE6_IB_BASE_LO', - 'regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE6_IB_CNTL', - 'regSDMA1_QUEUE6_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_IB_OFFSET', - 'regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE6_IB_RPTR', - 'regSDMA1_QUEUE6_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_IB_SIZE', - 'regSDMA1_QUEUE6_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE6_IB_SUB_REMAIN', - 'regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_CNTL', - 'regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA0', - 'regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA1', 'regSDMA1_QUEUE6_MIDCMD_DATA10', - 'regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA2', - 'regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA3', - 'regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA4', - 'regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA5', - 'regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA6', - 'regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA7', - 'regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA8', - 'regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE6_MIDCMD_DATA9', - 'regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE6_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE6_PREEMPT', 'regSDMA1_QUEUE6_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE6_RB_AQL_CNTL', - 'regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE', - 'regSDMA1_QUEUE6_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE6_RB_BASE_HI', - 'regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_CNTL', - 'regSDMA1_QUEUE6_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE6_RB_PREEMPT', - 'regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE6_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_RPTR_HI', - 'regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR', - 'regSDMA1_QUEUE6_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE6_RB_WPTR_HI', - 'regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE6_SCHEDULE_CNTL', - 'regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE6_SKIP_CNTL', 'regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE7_CONTEXT_STATUS', - 'regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX', - 'regSDMA1_QUEUE7_CSA_ADDR_HI', - 'regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_CSA_ADDR_LO', - 'regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE7_DOORBELL', 'regSDMA1_QUEUE7_DOORBELL_BASE_IDX', - 'regSDMA1_QUEUE7_DOORBELL_LOG', - 'regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX', - 'regSDMA1_QUEUE7_DOORBELL_OFFSET', - 'regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX', - 'regSDMA1_QUEUE7_DUMMY_REG', 'regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX', - 'regSDMA1_QUEUE7_IB_BASE_HI', - 'regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX', - 'regSDMA1_QUEUE7_IB_BASE_LO', - 'regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX', 'regSDMA1_QUEUE7_IB_CNTL', - 'regSDMA1_QUEUE7_IB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_IB_OFFSET', - 'regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX', 'regSDMA1_QUEUE7_IB_RPTR', - 'regSDMA1_QUEUE7_IB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_IB_SIZE', - 'regSDMA1_QUEUE7_IB_SIZE_BASE_IDX', - 'regSDMA1_QUEUE7_IB_SUB_REMAIN', - 'regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_CNTL', - 'regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA0', - 'regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA1', 'regSDMA1_QUEUE7_MIDCMD_DATA10', - 'regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA2', - 'regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA3', - 'regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA4', - 'regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA5', - 'regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA6', - 'regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA7', - 'regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA8', - 'regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX', - 'regSDMA1_QUEUE7_MIDCMD_DATA9', - 'regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX', - 'regSDMA1_QUEUE7_MINOR_PTR_UPDATE', - 'regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX', - 'regSDMA1_QUEUE7_PREEMPT', 'regSDMA1_QUEUE7_PREEMPT_BASE_IDX', - 'regSDMA1_QUEUE7_RB_AQL_CNTL', - 'regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE', - 'regSDMA1_QUEUE7_RB_BASE_BASE_IDX', 'regSDMA1_QUEUE7_RB_BASE_HI', - 'regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_CNTL', - 'regSDMA1_QUEUE7_RB_CNTL_BASE_IDX', 'regSDMA1_QUEUE7_RB_PREEMPT', - 'regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO', - 'regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE7_RB_RPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_RPTR_HI', - 'regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR', - 'regSDMA1_QUEUE7_RB_WPTR_BASE_IDX', 'regSDMA1_QUEUE7_RB_WPTR_HI', - 'regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO', - 'regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', - 'regSDMA1_QUEUE7_SCHEDULE_CNTL', - 'regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX', - 'regSDMA1_QUEUE7_SKIP_CNTL', 'regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX', - 'regSDMA1_QUEUE_RESET_REQ', 'regSDMA1_QUEUE_RESET_REQ_BASE_IDX', - 'regSDMA1_QUEUE_STATUS0', 'regSDMA1_QUEUE_STATUS0_BASE_IDX', - 'regSDMA1_RB_RPTR_FETCH', 'regSDMA1_RB_RPTR_FETCH_BASE_IDX', - 'regSDMA1_RB_RPTR_FETCH_HI', 'regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX', - 'regSDMA1_RELAX_ORDERING_LUT', - 'regSDMA1_RELAX_ORDERING_LUT_BASE_IDX', 'regSDMA1_RLC_CGCG_CTRL', - 'regSDMA1_RLC_CGCG_CTRL_BASE_IDX', 'regSDMA1_SCRATCH_RAM_ADDR', - 'regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', 'regSDMA1_SCRATCH_RAM_DATA', - 'regSDMA1_SCRATCH_RAM_DATA_BASE_IDX', - 'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL', - 'regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', - 'regSDMA1_STATUS1_REG', 'regSDMA1_STATUS1_REG_BASE_IDX', - 'regSDMA1_STATUS2_REG', 'regSDMA1_STATUS2_REG_BASE_IDX', - 'regSDMA1_STATUS3_REG', 'regSDMA1_STATUS3_REG_BASE_IDX', - 'regSDMA1_STATUS4_REG', 'regSDMA1_STATUS4_REG_BASE_IDX', - 'regSDMA1_STATUS5_REG', 'regSDMA1_STATUS5_REG_BASE_IDX', - 'regSDMA1_STATUS6_REG', 'regSDMA1_STATUS6_REG_BASE_IDX', - 'regSDMA1_STATUS_REG', 'regSDMA1_STATUS_REG_BASE_IDX', - 'regSDMA1_TILING_CONFIG', 'regSDMA1_TILING_CONFIG_BASE_IDX', - 'regSDMA1_TIMESTAMP_CNTL', 'regSDMA1_TIMESTAMP_CNTL_BASE_IDX', - 'regSDMA1_TLBI_GCR_CNTL', 'regSDMA1_TLBI_GCR_CNTL_BASE_IDX', - 'regSDMA1_UCODE1_CHECKSUM', 'regSDMA1_UCODE1_CHECKSUM_BASE_IDX', - 'regSDMA1_UCODE_ADDR', 'regSDMA1_UCODE_ADDR_BASE_IDX', - 'regSDMA1_UCODE_CHECKSUM', 'regSDMA1_UCODE_CHECKSUM_BASE_IDX', - 'regSDMA1_UCODE_DATA', 'regSDMA1_UCODE_DATA_BASE_IDX', - 'regSDMA1_UCODE_SELFLOAD_CONTROL', - 'regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX', 'regSDMA1_UTCL1_CNTL', - 'regSDMA1_UTCL1_CNTL_BASE_IDX', 'regSDMA1_UTCL1_INV0', - 'regSDMA1_UTCL1_INV0_BASE_IDX', 'regSDMA1_UTCL1_INV1', - 'regSDMA1_UTCL1_INV1_BASE_IDX', 'regSDMA1_UTCL1_INV2', - 'regSDMA1_UTCL1_INV2_BASE_IDX', 'regSDMA1_UTCL1_PAGE', - 'regSDMA1_UTCL1_PAGE_BASE_IDX', 'regSDMA1_UTCL1_RD_STATUS', - 'regSDMA1_UTCL1_RD_STATUS_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK0', - 'regSDMA1_UTCL1_RD_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_RD_XNACK1', - 'regSDMA1_UTCL1_RD_XNACK1_BASE_IDX', 'regSDMA1_UTCL1_TIMEOUT', - 'regSDMA1_UTCL1_TIMEOUT_BASE_IDX', 'regSDMA1_UTCL1_WATERMK', - 'regSDMA1_UTCL1_WATERMK_BASE_IDX', 'regSDMA1_UTCL1_WR_STATUS', - 'regSDMA1_UTCL1_WR_STATUS_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK0', - 'regSDMA1_UTCL1_WR_XNACK0_BASE_IDX', 'regSDMA1_UTCL1_WR_XNACK1', - 'regSDMA1_UTCL1_WR_XNACK1_BASE_IDX', 'regSDMA1_VERSION', - 'regSDMA1_VERSION_BASE_IDX', 'regSDMA1_WATCHDOG_CNTL', - 'regSDMA1_WATCHDOG_CNTL_BASE_IDX', 'regSE0_CAC_AGGR_GFXCLK_CYCLE', - 'regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE0_CAC_AGGR_LOWER', - 'regSE0_CAC_AGGR_LOWER_BASE_IDX', 'regSE0_CAC_AGGR_UPPER', - 'regSE0_CAC_AGGR_UPPER_BASE_IDX', 'regSE1_CAC_AGGR_GFXCLK_CYCLE', - 'regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE1_CAC_AGGR_LOWER', - 'regSE1_CAC_AGGR_LOWER_BASE_IDX', 'regSE1_CAC_AGGR_UPPER', - 'regSE1_CAC_AGGR_UPPER_BASE_IDX', 'regSE2_CAC_AGGR_GFXCLK_CYCLE', - 'regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE2_CAC_AGGR_LOWER', - 'regSE2_CAC_AGGR_LOWER_BASE_IDX', 'regSE2_CAC_AGGR_UPPER', - 'regSE2_CAC_AGGR_UPPER_BASE_IDX', 'regSE3_CAC_AGGR_GFXCLK_CYCLE', - 'regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE3_CAC_AGGR_LOWER', - 'regSE3_CAC_AGGR_LOWER_BASE_IDX', 'regSE3_CAC_AGGR_UPPER', - 'regSE3_CAC_AGGR_UPPER_BASE_IDX', 'regSE4_CAC_AGGR_GFXCLK_CYCLE', - 'regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE4_CAC_AGGR_LOWER', - 'regSE4_CAC_AGGR_LOWER_BASE_IDX', 'regSE4_CAC_AGGR_UPPER', - 'regSE4_CAC_AGGR_UPPER_BASE_IDX', 'regSE5_CAC_AGGR_GFXCLK_CYCLE', - 'regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX', 'regSE5_CAC_AGGR_LOWER', - 'regSE5_CAC_AGGR_LOWER_BASE_IDX', 'regSE5_CAC_AGGR_UPPER', - 'regSE5_CAC_AGGR_UPPER_BASE_IDX', 'regSEDC_GL1_GL2_OVERRIDES', - 'regSEDC_GL1_GL2_OVERRIDES_BASE_IDX', 'regSE_CAC_CTRL_1', - 'regSE_CAC_CTRL_1_BASE_IDX', 'regSE_CAC_CTRL_2', - 'regSE_CAC_CTRL_2_BASE_IDX', 'regSE_CAC_IND_DATA', - 'regSE_CAC_IND_DATA_BASE_IDX', 'regSE_CAC_IND_INDEX', - 'regSE_CAC_IND_INDEX_BASE_IDX', 'regSE_CAC_WEIGHT_BCI_0', - 'regSE_CAC_WEIGHT_BCI_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_0', - 'regSE_CAC_WEIGHT_CB_0_BASE_IDX', 'regSE_CAC_WEIGHT_CB_1', - 'regSE_CAC_WEIGHT_CB_10', 'regSE_CAC_WEIGHT_CB_10_BASE_IDX', - 'regSE_CAC_WEIGHT_CB_11', 'regSE_CAC_WEIGHT_CB_11_BASE_IDX', - 'regSE_CAC_WEIGHT_CB_1_BASE_IDX', 'regSE_CAC_WEIGHT_CB_2', - 'regSE_CAC_WEIGHT_CB_2_BASE_IDX', 'regSE_CAC_WEIGHT_CB_3', - 'regSE_CAC_WEIGHT_CB_3_BASE_IDX', 'regSE_CAC_WEIGHT_CB_4', - 'regSE_CAC_WEIGHT_CB_4_BASE_IDX', 'regSE_CAC_WEIGHT_CB_5', - 'regSE_CAC_WEIGHT_CB_5_BASE_IDX', 'regSE_CAC_WEIGHT_CB_6', - 'regSE_CAC_WEIGHT_CB_6_BASE_IDX', 'regSE_CAC_WEIGHT_CB_7', - 'regSE_CAC_WEIGHT_CB_7_BASE_IDX', 'regSE_CAC_WEIGHT_CB_8', - 'regSE_CAC_WEIGHT_CB_8_BASE_IDX', 'regSE_CAC_WEIGHT_CB_9', - 'regSE_CAC_WEIGHT_CB_9_BASE_IDX', 'regSE_CAC_WEIGHT_CU_0', - 'regSE_CAC_WEIGHT_CU_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_0', - 'regSE_CAC_WEIGHT_DB_0_BASE_IDX', 'regSE_CAC_WEIGHT_DB_1', - 'regSE_CAC_WEIGHT_DB_1_BASE_IDX', 'regSE_CAC_WEIGHT_DB_2', - 'regSE_CAC_WEIGHT_DB_2_BASE_IDX', 'regSE_CAC_WEIGHT_DB_3', - 'regSE_CAC_WEIGHT_DB_3_BASE_IDX', 'regSE_CAC_WEIGHT_DB_4', - 'regSE_CAC_WEIGHT_DB_4_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_0', - 'regSE_CAC_WEIGHT_GL1C_0_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_1', - 'regSE_CAC_WEIGHT_GL1C_1_BASE_IDX', 'regSE_CAC_WEIGHT_GL1C_2', - 'regSE_CAC_WEIGHT_GL1C_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_0', - 'regSE_CAC_WEIGHT_LDS_0_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_1', - 'regSE_CAC_WEIGHT_LDS_1_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_2', - 'regSE_CAC_WEIGHT_LDS_2_BASE_IDX', 'regSE_CAC_WEIGHT_LDS_3', - 'regSE_CAC_WEIGHT_LDS_3_BASE_IDX', 'regSE_CAC_WEIGHT_PA_0', - 'regSE_CAC_WEIGHT_PA_0_BASE_IDX', 'regSE_CAC_WEIGHT_PA_1', - 'regSE_CAC_WEIGHT_PA_1_BASE_IDX', 'regSE_CAC_WEIGHT_PA_2', - 'regSE_CAC_WEIGHT_PA_2_BASE_IDX', 'regSE_CAC_WEIGHT_PA_3', - 'regSE_CAC_WEIGHT_PA_3_BASE_IDX', 'regSE_CAC_WEIGHT_PC_0', - 'regSE_CAC_WEIGHT_PC_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_0', - 'regSE_CAC_WEIGHT_RMI_0_BASE_IDX', 'regSE_CAC_WEIGHT_RMI_1', - 'regSE_CAC_WEIGHT_RMI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_0', - 'regSE_CAC_WEIGHT_SC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SC_1', - 'regSE_CAC_WEIGHT_SC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SC_2', - 'regSE_CAC_WEIGHT_SC_2_BASE_IDX', 'regSE_CAC_WEIGHT_SC_3', - 'regSE_CAC_WEIGHT_SC_3_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_0', - 'regSE_CAC_WEIGHT_SPI_0_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_1', - 'regSE_CAC_WEIGHT_SPI_1_BASE_IDX', 'regSE_CAC_WEIGHT_SPI_2', - 'regSE_CAC_WEIGHT_SPI_2_BASE_IDX', 'regSE_CAC_WEIGHT_SP_0', - 'regSE_CAC_WEIGHT_SP_0_BASE_IDX', 'regSE_CAC_WEIGHT_SP_1', - 'regSE_CAC_WEIGHT_SP_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_0', - 'regSE_CAC_WEIGHT_SQC_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQC_1', - 'regSE_CAC_WEIGHT_SQC_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_0', - 'regSE_CAC_WEIGHT_SQ_0_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_1', - 'regSE_CAC_WEIGHT_SQ_1_BASE_IDX', 'regSE_CAC_WEIGHT_SQ_2', - 'regSE_CAC_WEIGHT_SQ_2_BASE_IDX', 'regSE_CAC_WEIGHT_SXRB_0', - 'regSE_CAC_WEIGHT_SXRB_0_BASE_IDX', 'regSE_CAC_WEIGHT_SX_0', - 'regSE_CAC_WEIGHT_SX_0_BASE_IDX', 'regSE_CAC_WEIGHT_TA_0', - 'regSE_CAC_WEIGHT_TA_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_0', - 'regSE_CAC_WEIGHT_TCP_0_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_1', - 'regSE_CAC_WEIGHT_TCP_1_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_2', - 'regSE_CAC_WEIGHT_TCP_2_BASE_IDX', 'regSE_CAC_WEIGHT_TCP_3', - 'regSE_CAC_WEIGHT_TCP_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_0', - 'regSE_CAC_WEIGHT_TD_0_BASE_IDX', 'regSE_CAC_WEIGHT_TD_1', - 'regSE_CAC_WEIGHT_TD_1_BASE_IDX', 'regSE_CAC_WEIGHT_TD_2', - 'regSE_CAC_WEIGHT_TD_2_BASE_IDX', 'regSE_CAC_WEIGHT_TD_3', - 'regSE_CAC_WEIGHT_TD_3_BASE_IDX', 'regSE_CAC_WEIGHT_TD_4', - 'regSE_CAC_WEIGHT_TD_4_BASE_IDX', 'regSE_CAC_WEIGHT_TD_5', - 'regSE_CAC_WEIGHT_TD_5_BASE_IDX', 'regSE_CAC_WEIGHT_UTCL1_0', - 'regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX', - 'regSE_CAC_WINDOW_AGGR_VALUE', - 'regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX', - 'regSE_CAC_WINDOW_GFXCLK_CYCLE', - 'regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX', 'regSH_MEM_BASES', - 'regSH_MEM_BASES_BASE_IDX', 'regSH_MEM_CONFIG', - 'regSH_MEM_CONFIG_BASE_IDX', 'regSH_RESERVED_REG0', - 'regSH_RESERVED_REG0_BASE_IDX', 'regSH_RESERVED_REG1', - 'regSH_RESERVED_REG1_BASE_IDX', 'regSMU_RLC_RESPONSE', - 'regSMU_RLC_RESPONSE_BASE_IDX', 'regSPI_ARB_CNTL_0', - 'regSPI_ARB_CNTL_0_BASE_IDX', 'regSPI_ARB_CYCLES_0', - 'regSPI_ARB_CYCLES_0_BASE_IDX', 'regSPI_ARB_CYCLES_1', - 'regSPI_ARB_CYCLES_1_BASE_IDX', 'regSPI_ARB_PRIORITY', - 'regSPI_ARB_PRIORITY_BASE_IDX', 'regSPI_ATTRIBUTE_RING_BASE', - 'regSPI_ATTRIBUTE_RING_BASE_BASE_IDX', - 'regSPI_ATTRIBUTE_RING_SIZE', - 'regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX', 'regSPI_BARYC_CNTL', - 'regSPI_BARYC_CNTL_BASE_IDX', 'regSPI_COMPUTE_QUEUE_RESET', - 'regSPI_COMPUTE_QUEUE_RESET_BASE_IDX', - 'regSPI_COMPUTE_WF_CTX_SAVE', - 'regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', - 'regSPI_COMPUTE_WF_CTX_SAVE_STATUS', - 'regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX', - 'regSPI_CONFIG_CNTL', 'regSPI_CONFIG_CNTL_1', - 'regSPI_CONFIG_CNTL_1_BASE_IDX', 'regSPI_CONFIG_CNTL_2', - 'regSPI_CONFIG_CNTL_2_BASE_IDX', 'regSPI_CONFIG_CNTL_BASE_IDX', - 'regSPI_CONFIG_PS_CU_EN', 'regSPI_CONFIG_PS_CU_EN_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_0', - 'regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_1', - 'regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_2', - 'regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_COUNT_3', - 'regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX', - 'regSPI_CSQ_WF_ACTIVE_STATUS', - 'regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'regSPI_DSM_CNTL', - 'regSPI_DSM_CNTL2', 'regSPI_DSM_CNTL2_BASE_IDX', - 'regSPI_DSM_CNTL_BASE_IDX', 'regSPI_EDC_CNT', - 'regSPI_EDC_CNT_BASE_IDX', 'regSPI_EXP_THROTTLE_CTRL', - 'regSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'regSPI_FEATURE_CTRL', - 'regSPI_FEATURE_CTRL_BASE_IDX', 'regSPI_GDBG_PER_VMID_CNTL', - 'regSPI_GDBG_PER_VMID_CNTL_BASE_IDX', 'regSPI_GDBG_TRAP_CONFIG', - 'regSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'regSPI_GDBG_WAVE_CNTL', - 'regSPI_GDBG_WAVE_CNTL3', 'regSPI_GDBG_WAVE_CNTL3_BASE_IDX', - 'regSPI_GDBG_WAVE_CNTL_BASE_IDX', 'regSPI_GDS_CREDITS', - 'regSPI_GDS_CREDITS_BASE_IDX', 'regSPI_GFX_CNTL', - 'regSPI_GFX_CNTL_BASE_IDX', 'regSPI_GFX_SCRATCH_BASE_HI', - 'regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX', - 'regSPI_GFX_SCRATCH_BASE_LO', - 'regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL1', - 'regSPI_GS_THROTTLE_CNTL1_BASE_IDX', 'regSPI_GS_THROTTLE_CNTL2', - 'regSPI_GS_THROTTLE_CNTL2_BASE_IDX', 'regSPI_INTERP_CONTROL_0', - 'regSPI_INTERP_CONTROL_0_BASE_IDX', 'regSPI_LB_CTR_CTRL', - 'regSPI_LB_CTR_CTRL_BASE_IDX', 'regSPI_LB_DATA_REG', - 'regSPI_LB_DATA_REG_BASE_IDX', 'regSPI_LB_DATA_WAVES', - 'regSPI_LB_DATA_WAVES_BASE_IDX', 'regSPI_LB_WGP_MASK', - 'regSPI_LB_WGP_MASK_BASE_IDX', 'regSPI_P0_TRAP_SCREEN_GPR_MIN', - 'regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSBA_HI', - 'regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSBA_LO', - 'regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSMA_HI', - 'regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX', - 'regSPI_P0_TRAP_SCREEN_PSMA_LO', - 'regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_GPR_MIN', - 'regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSBA_HI', - 'regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSBA_LO', - 'regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSMA_HI', - 'regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX', - 'regSPI_P1_TRAP_SCREEN_PSMA_LO', - 'regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', - 'regSPI_PERFCOUNTER0_HI', 'regSPI_PERFCOUNTER0_HI_BASE_IDX', - 'regSPI_PERFCOUNTER0_LO', 'regSPI_PERFCOUNTER0_LO_BASE_IDX', - 'regSPI_PERFCOUNTER0_SELECT', 'regSPI_PERFCOUNTER0_SELECT1', - 'regSPI_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER1_HI', - 'regSPI_PERFCOUNTER1_HI_BASE_IDX', 'regSPI_PERFCOUNTER1_LO', - 'regSPI_PERFCOUNTER1_LO_BASE_IDX', 'regSPI_PERFCOUNTER1_SELECT', - 'regSPI_PERFCOUNTER1_SELECT1', - 'regSPI_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER2_HI', - 'regSPI_PERFCOUNTER2_HI_BASE_IDX', 'regSPI_PERFCOUNTER2_LO', - 'regSPI_PERFCOUNTER2_LO_BASE_IDX', 'regSPI_PERFCOUNTER2_SELECT', - 'regSPI_PERFCOUNTER2_SELECT1', - 'regSPI_PERFCOUNTER2_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER3_HI', - 'regSPI_PERFCOUNTER3_HI_BASE_IDX', 'regSPI_PERFCOUNTER3_LO', - 'regSPI_PERFCOUNTER3_LO_BASE_IDX', 'regSPI_PERFCOUNTER3_SELECT', - 'regSPI_PERFCOUNTER3_SELECT1', - 'regSPI_PERFCOUNTER3_SELECT1_BASE_IDX', - 'regSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER4_HI', - 'regSPI_PERFCOUNTER4_HI_BASE_IDX', 'regSPI_PERFCOUNTER4_LO', - 'regSPI_PERFCOUNTER4_LO_BASE_IDX', 'regSPI_PERFCOUNTER4_SELECT', - 'regSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER5_HI', - 'regSPI_PERFCOUNTER5_HI_BASE_IDX', 'regSPI_PERFCOUNTER5_LO', - 'regSPI_PERFCOUNTER5_LO_BASE_IDX', 'regSPI_PERFCOUNTER5_SELECT', - 'regSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'regSPI_PERFCOUNTER_BINS', - 'regSPI_PERFCOUNTER_BINS_BASE_IDX', - 'regSPI_PG_ENABLE_STATIC_WGP_MASK', - 'regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'regSPI_PQEV_CTRL', - 'regSPI_PQEV_CTRL_BASE_IDX', 'regSPI_PS_INPUT_ADDR', - 'regSPI_PS_INPUT_ADDR_BASE_IDX', 'regSPI_PS_INPUT_CNTL_0', - 'regSPI_PS_INPUT_CNTL_0_BASE_IDX', 'regSPI_PS_INPUT_CNTL_1', - 'regSPI_PS_INPUT_CNTL_10', 'regSPI_PS_INPUT_CNTL_10_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_11', 'regSPI_PS_INPUT_CNTL_11_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_12', 'regSPI_PS_INPUT_CNTL_12_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_13', 'regSPI_PS_INPUT_CNTL_13_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_14', 'regSPI_PS_INPUT_CNTL_14_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_15', 'regSPI_PS_INPUT_CNTL_15_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_16', 'regSPI_PS_INPUT_CNTL_16_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_17', 'regSPI_PS_INPUT_CNTL_17_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_18', 'regSPI_PS_INPUT_CNTL_18_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_19', 'regSPI_PS_INPUT_CNTL_19_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_1_BASE_IDX', 'regSPI_PS_INPUT_CNTL_2', - 'regSPI_PS_INPUT_CNTL_20', 'regSPI_PS_INPUT_CNTL_20_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_21', 'regSPI_PS_INPUT_CNTL_21_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_22', 'regSPI_PS_INPUT_CNTL_22_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_23', 'regSPI_PS_INPUT_CNTL_23_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_24', 'regSPI_PS_INPUT_CNTL_24_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_25', 'regSPI_PS_INPUT_CNTL_25_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_26', 'regSPI_PS_INPUT_CNTL_26_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_27', 'regSPI_PS_INPUT_CNTL_27_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_28', 'regSPI_PS_INPUT_CNTL_28_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_29', 'regSPI_PS_INPUT_CNTL_29_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_2_BASE_IDX', 'regSPI_PS_INPUT_CNTL_3', - 'regSPI_PS_INPUT_CNTL_30', 'regSPI_PS_INPUT_CNTL_30_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_31', 'regSPI_PS_INPUT_CNTL_31_BASE_IDX', - 'regSPI_PS_INPUT_CNTL_3_BASE_IDX', 'regSPI_PS_INPUT_CNTL_4', - 'regSPI_PS_INPUT_CNTL_4_BASE_IDX', 'regSPI_PS_INPUT_CNTL_5', - 'regSPI_PS_INPUT_CNTL_5_BASE_IDX', 'regSPI_PS_INPUT_CNTL_6', - 'regSPI_PS_INPUT_CNTL_6_BASE_IDX', 'regSPI_PS_INPUT_CNTL_7', - 'regSPI_PS_INPUT_CNTL_7_BASE_IDX', 'regSPI_PS_INPUT_CNTL_8', - 'regSPI_PS_INPUT_CNTL_8_BASE_IDX', 'regSPI_PS_INPUT_CNTL_9', - 'regSPI_PS_INPUT_CNTL_9_BASE_IDX', 'regSPI_PS_INPUT_ENA', - 'regSPI_PS_INPUT_ENA_BASE_IDX', 'regSPI_PS_IN_CONTROL', - 'regSPI_PS_IN_CONTROL_BASE_IDX', 'regSPI_PS_MAX_WAVE_ID', - 'regSPI_PS_MAX_WAVE_ID_BASE_IDX', 'regSPI_RESOURCE_RESERVE_CU_0', - 'regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_1', 'regSPI_RESOURCE_RESERVE_CU_10', - 'regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_11', - 'regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_12', - 'regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_13', - 'regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_14', - 'regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_15', - 'regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_2', - 'regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_3', - 'regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_4', - 'regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_5', - 'regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_6', - 'regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_7', - 'regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_8', - 'regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_CU_9', - 'regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_0', - 'regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_1', - 'regSPI_RESOURCE_RESERVE_EN_CU_10', - 'regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_11', - 'regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_12', - 'regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_13', - 'regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_14', - 'regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_15', - 'regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_2', - 'regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_3', - 'regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_4', - 'regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_5', - 'regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_6', - 'regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_7', - 'regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_8', - 'regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX', - 'regSPI_RESOURCE_RESERVE_EN_CU_9', - 'regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX', - 'regSPI_SHADER_COL_FORMAT', 'regSPI_SHADER_COL_FORMAT_BASE_IDX', - 'regSPI_SHADER_GS_MESHLET_DIM', - 'regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX', - 'regSPI_SHADER_GS_MESHLET_EXP_ALLOC', - 'regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX', - 'regSPI_SHADER_IDX_FORMAT', 'regSPI_SHADER_IDX_FORMAT_BASE_IDX', - 'regSPI_SHADER_PGM_CHKSUM_GS', - 'regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX', - 'regSPI_SHADER_PGM_CHKSUM_HS', - 'regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX', - 'regSPI_SHADER_PGM_CHKSUM_PS', - 'regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES', - 'regSPI_SHADER_PGM_HI_ES_BASE_IDX', 'regSPI_SHADER_PGM_HI_ES_GS', - 'regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_GS', - 'regSPI_SHADER_PGM_HI_GS_BASE_IDX', 'regSPI_SHADER_PGM_HI_HS', - 'regSPI_SHADER_PGM_HI_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS', - 'regSPI_SHADER_PGM_HI_LS_BASE_IDX', 'regSPI_SHADER_PGM_HI_LS_HS', - 'regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_HI_PS', - 'regSPI_SHADER_PGM_HI_PS_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES', - 'regSPI_SHADER_PGM_LO_ES_BASE_IDX', 'regSPI_SHADER_PGM_LO_ES_GS', - 'regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_GS', - 'regSPI_SHADER_PGM_LO_GS_BASE_IDX', 'regSPI_SHADER_PGM_LO_HS', - 'regSPI_SHADER_PGM_LO_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS', - 'regSPI_SHADER_PGM_LO_LS_BASE_IDX', 'regSPI_SHADER_PGM_LO_LS_HS', - 'regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'regSPI_SHADER_PGM_LO_PS', - 'regSPI_SHADER_PGM_LO_PS_BASE_IDX', 'regSPI_SHADER_PGM_RSRC1_GS', - 'regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC1_HS', - 'regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC1_PS', - 'regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC2_GS', - 'regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC2_HS', - 'regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC2_PS', - 'regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC3_GS', - 'regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC3_HS', - 'regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC3_PS', - 'regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC4_GS', - 'regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC4_HS', - 'regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX', - 'regSPI_SHADER_PGM_RSRC4_PS', - 'regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', 'regSPI_SHADER_POS_FORMAT', - 'regSPI_SHADER_POS_FORMAT_BASE_IDX', - 'regSPI_SHADER_REQ_CTRL_ESGS', - 'regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX', - 'regSPI_SHADER_REQ_CTRL_LSHS', - 'regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX', - 'regSPI_SHADER_REQ_CTRL_PS', 'regSPI_SHADER_REQ_CTRL_PS_BASE_IDX', - 'regSPI_SHADER_RSRC_LIMIT_CTRL', - 'regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_0', - 'regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_1', - 'regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_2', - 'regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_ESGS_3', - 'regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_0', - 'regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_1', - 'regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_2', - 'regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_LSHS_3', - 'regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_0', - 'regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_1', - 'regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_2', - 'regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX', - 'regSPI_SHADER_USER_ACCUM_PS_3', - 'regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_HI_GS', - 'regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_HI_HS', - 'regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_LO_GS', - 'regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_ADDR_LO_HS', - 'regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_0', - 'regSPI_SHADER_USER_DATA_GS_0_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_1', 'regSPI_SHADER_USER_DATA_GS_10', - 'regSPI_SHADER_USER_DATA_GS_10_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_11', - 'regSPI_SHADER_USER_DATA_GS_11_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_12', - 'regSPI_SHADER_USER_DATA_GS_12_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_13', - 'regSPI_SHADER_USER_DATA_GS_13_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_14', - 'regSPI_SHADER_USER_DATA_GS_14_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_15', - 'regSPI_SHADER_USER_DATA_GS_15_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_16', - 'regSPI_SHADER_USER_DATA_GS_16_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_17', - 'regSPI_SHADER_USER_DATA_GS_17_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_18', - 'regSPI_SHADER_USER_DATA_GS_18_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_19', - 'regSPI_SHADER_USER_DATA_GS_19_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_1_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_2', 'regSPI_SHADER_USER_DATA_GS_20', - 'regSPI_SHADER_USER_DATA_GS_20_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_21', - 'regSPI_SHADER_USER_DATA_GS_21_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_22', - 'regSPI_SHADER_USER_DATA_GS_22_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_23', - 'regSPI_SHADER_USER_DATA_GS_23_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_24', - 'regSPI_SHADER_USER_DATA_GS_24_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_25', - 'regSPI_SHADER_USER_DATA_GS_25_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_26', - 'regSPI_SHADER_USER_DATA_GS_26_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_27', - 'regSPI_SHADER_USER_DATA_GS_27_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_28', - 'regSPI_SHADER_USER_DATA_GS_28_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_29', - 'regSPI_SHADER_USER_DATA_GS_29_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_2_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_3', 'regSPI_SHADER_USER_DATA_GS_30', - 'regSPI_SHADER_USER_DATA_GS_30_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_31', - 'regSPI_SHADER_USER_DATA_GS_31_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_4', - 'regSPI_SHADER_USER_DATA_GS_4_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_5', - 'regSPI_SHADER_USER_DATA_GS_5_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_6', - 'regSPI_SHADER_USER_DATA_GS_6_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_7', - 'regSPI_SHADER_USER_DATA_GS_7_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_8', - 'regSPI_SHADER_USER_DATA_GS_8_BASE_IDX', - 'regSPI_SHADER_USER_DATA_GS_9', - 'regSPI_SHADER_USER_DATA_GS_9_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_0', - 'regSPI_SHADER_USER_DATA_HS_0_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_1', 'regSPI_SHADER_USER_DATA_HS_10', - 'regSPI_SHADER_USER_DATA_HS_10_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_11', - 'regSPI_SHADER_USER_DATA_HS_11_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_12', - 'regSPI_SHADER_USER_DATA_HS_12_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_13', - 'regSPI_SHADER_USER_DATA_HS_13_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_14', - 'regSPI_SHADER_USER_DATA_HS_14_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_15', - 'regSPI_SHADER_USER_DATA_HS_15_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_16', - 'regSPI_SHADER_USER_DATA_HS_16_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_17', - 'regSPI_SHADER_USER_DATA_HS_17_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_18', - 'regSPI_SHADER_USER_DATA_HS_18_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_19', - 'regSPI_SHADER_USER_DATA_HS_19_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_1_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_2', 'regSPI_SHADER_USER_DATA_HS_20', - 'regSPI_SHADER_USER_DATA_HS_20_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_21', - 'regSPI_SHADER_USER_DATA_HS_21_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_22', - 'regSPI_SHADER_USER_DATA_HS_22_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_23', - 'regSPI_SHADER_USER_DATA_HS_23_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_24', - 'regSPI_SHADER_USER_DATA_HS_24_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_25', - 'regSPI_SHADER_USER_DATA_HS_25_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_26', - 'regSPI_SHADER_USER_DATA_HS_26_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_27', - 'regSPI_SHADER_USER_DATA_HS_27_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_28', - 'regSPI_SHADER_USER_DATA_HS_28_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_29', - 'regSPI_SHADER_USER_DATA_HS_29_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_2_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_3', 'regSPI_SHADER_USER_DATA_HS_30', - 'regSPI_SHADER_USER_DATA_HS_30_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_31', - 'regSPI_SHADER_USER_DATA_HS_31_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_4', - 'regSPI_SHADER_USER_DATA_HS_4_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_5', - 'regSPI_SHADER_USER_DATA_HS_5_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_6', - 'regSPI_SHADER_USER_DATA_HS_6_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_7', - 'regSPI_SHADER_USER_DATA_HS_7_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_8', - 'regSPI_SHADER_USER_DATA_HS_8_BASE_IDX', - 'regSPI_SHADER_USER_DATA_HS_9', - 'regSPI_SHADER_USER_DATA_HS_9_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_0', - 'regSPI_SHADER_USER_DATA_PS_0_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_1', 'regSPI_SHADER_USER_DATA_PS_10', - 'regSPI_SHADER_USER_DATA_PS_10_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_11', - 'regSPI_SHADER_USER_DATA_PS_11_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_12', - 'regSPI_SHADER_USER_DATA_PS_12_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_13', - 'regSPI_SHADER_USER_DATA_PS_13_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_14', - 'regSPI_SHADER_USER_DATA_PS_14_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_15', - 'regSPI_SHADER_USER_DATA_PS_15_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_16', - 'regSPI_SHADER_USER_DATA_PS_16_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_17', - 'regSPI_SHADER_USER_DATA_PS_17_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_18', - 'regSPI_SHADER_USER_DATA_PS_18_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_19', - 'regSPI_SHADER_USER_DATA_PS_19_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_1_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_2', 'regSPI_SHADER_USER_DATA_PS_20', - 'regSPI_SHADER_USER_DATA_PS_20_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_21', - 'regSPI_SHADER_USER_DATA_PS_21_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_22', - 'regSPI_SHADER_USER_DATA_PS_22_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_23', - 'regSPI_SHADER_USER_DATA_PS_23_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_24', - 'regSPI_SHADER_USER_DATA_PS_24_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_25', - 'regSPI_SHADER_USER_DATA_PS_25_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_26', - 'regSPI_SHADER_USER_DATA_PS_26_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_27', - 'regSPI_SHADER_USER_DATA_PS_27_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_28', - 'regSPI_SHADER_USER_DATA_PS_28_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_29', - 'regSPI_SHADER_USER_DATA_PS_29_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_2_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_3', 'regSPI_SHADER_USER_DATA_PS_30', - 'regSPI_SHADER_USER_DATA_PS_30_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_31', - 'regSPI_SHADER_USER_DATA_PS_31_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_3_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_4', - 'regSPI_SHADER_USER_DATA_PS_4_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_5', - 'regSPI_SHADER_USER_DATA_PS_5_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_6', - 'regSPI_SHADER_USER_DATA_PS_6_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_7', - 'regSPI_SHADER_USER_DATA_PS_7_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_8', - 'regSPI_SHADER_USER_DATA_PS_8_BASE_IDX', - 'regSPI_SHADER_USER_DATA_PS_9', - 'regSPI_SHADER_USER_DATA_PS_9_BASE_IDX', 'regSPI_SHADER_Z_FORMAT', - 'regSPI_SHADER_Z_FORMAT_BASE_IDX', - 'regSPI_SX_EXPORT_BUFFER_SIZES', - 'regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX', - 'regSPI_SX_SCOREBOARD_BUFFER_SIZES', - 'regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', - 'regSPI_TMPRING_SIZE', 'regSPI_TMPRING_SIZE_BASE_IDX', - 'regSPI_USER_ACCUM_VMID_CNTL', - 'regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'regSPI_VS_OUT_CONFIG', - 'regSPI_VS_OUT_CONFIG_BASE_IDX', 'regSPI_WAVE_LIMIT_CNTL', - 'regSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'regSPI_WCL_PIPE_PERCENT_CS0', - 'regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS1', - 'regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS2', - 'regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS3', - 'regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS4', - 'regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS5', - 'regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS6', - 'regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_CS7', - 'regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_GFX', - 'regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX', - 'regSPI_WCL_PIPE_PERCENT_HP3D', - 'regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', - 'regSPI_WF_LIFETIME_CNTL', 'regSPI_WF_LIFETIME_CNTL_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_0', - 'regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_1', - 'regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_2', - 'regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_3', - 'regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_4', - 'regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', - 'regSPI_WF_LIFETIME_LIMIT_5', - 'regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_0', - 'regSPI_WF_LIFETIME_STATUS_0_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_11', - 'regSPI_WF_LIFETIME_STATUS_11_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_13', - 'regSPI_WF_LIFETIME_STATUS_13_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_14', - 'regSPI_WF_LIFETIME_STATUS_14_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_15', - 'regSPI_WF_LIFETIME_STATUS_15_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_16', - 'regSPI_WF_LIFETIME_STATUS_16_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_17', - 'regSPI_WF_LIFETIME_STATUS_17_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_18', - 'regSPI_WF_LIFETIME_STATUS_18_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_19', - 'regSPI_WF_LIFETIME_STATUS_19_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_2', 'regSPI_WF_LIFETIME_STATUS_20', - 'regSPI_WF_LIFETIME_STATUS_20_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_21', - 'regSPI_WF_LIFETIME_STATUS_21_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_2_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_4', - 'regSPI_WF_LIFETIME_STATUS_4_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_6', - 'regSPI_WF_LIFETIME_STATUS_6_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_7', - 'regSPI_WF_LIFETIME_STATUS_7_BASE_IDX', - 'regSPI_WF_LIFETIME_STATUS_9', - 'regSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'regSP_CONFIG', - 'regSP_CONFIG_BASE_IDX', 'regSQC_CACHES', - 'regSQC_CACHES_BASE_IDX', 'regSQC_CONFIG', - 'regSQC_CONFIG_BASE_IDX', 'regSQG_CONFIG', - 'regSQG_CONFIG_BASE_IDX', 'regSQG_GL1H_STATUS', - 'regSQG_GL1H_STATUS_BASE_IDX', 'regSQG_PERFCOUNTER0_HI', - 'regSQG_PERFCOUNTER0_HI_BASE_IDX', 'regSQG_PERFCOUNTER0_LO', - 'regSQG_PERFCOUNTER0_LO_BASE_IDX', 'regSQG_PERFCOUNTER0_SELECT', - 'regSQG_PERFCOUNTER0_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER1_HI', - 'regSQG_PERFCOUNTER1_HI_BASE_IDX', 'regSQG_PERFCOUNTER1_LO', - 'regSQG_PERFCOUNTER1_LO_BASE_IDX', 'regSQG_PERFCOUNTER1_SELECT', - 'regSQG_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER2_HI', - 'regSQG_PERFCOUNTER2_HI_BASE_IDX', 'regSQG_PERFCOUNTER2_LO', - 'regSQG_PERFCOUNTER2_LO_BASE_IDX', 'regSQG_PERFCOUNTER2_SELECT', - 'regSQG_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER3_HI', - 'regSQG_PERFCOUNTER3_HI_BASE_IDX', 'regSQG_PERFCOUNTER3_LO', - 'regSQG_PERFCOUNTER3_LO_BASE_IDX', 'regSQG_PERFCOUNTER3_SELECT', - 'regSQG_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER4_HI', - 'regSQG_PERFCOUNTER4_HI_BASE_IDX', 'regSQG_PERFCOUNTER4_LO', - 'regSQG_PERFCOUNTER4_LO_BASE_IDX', 'regSQG_PERFCOUNTER4_SELECT', - 'regSQG_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER5_HI', - 'regSQG_PERFCOUNTER5_HI_BASE_IDX', 'regSQG_PERFCOUNTER5_LO', - 'regSQG_PERFCOUNTER5_LO_BASE_IDX', 'regSQG_PERFCOUNTER5_SELECT', - 'regSQG_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER6_HI', - 'regSQG_PERFCOUNTER6_HI_BASE_IDX', 'regSQG_PERFCOUNTER6_LO', - 'regSQG_PERFCOUNTER6_LO_BASE_IDX', 'regSQG_PERFCOUNTER6_SELECT', - 'regSQG_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER7_HI', - 'regSQG_PERFCOUNTER7_HI_BASE_IDX', 'regSQG_PERFCOUNTER7_LO', - 'regSQG_PERFCOUNTER7_LO_BASE_IDX', 'regSQG_PERFCOUNTER7_SELECT', - 'regSQG_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQG_PERFCOUNTER_CTRL', - 'regSQG_PERFCOUNTER_CTRL2', 'regSQG_PERFCOUNTER_CTRL2_BASE_IDX', - 'regSQG_PERFCOUNTER_CTRL_BASE_IDX', 'regSQG_PERF_SAMPLE_FINISH', - 'regSQG_PERF_SAMPLE_FINISH_BASE_IDX', 'regSQG_STATUS', - 'regSQG_STATUS_BASE_IDX', 'regSQ_ALU_CLK_CTRL', - 'regSQ_ALU_CLK_CTRL_BASE_IDX', 'regSQ_ARB_CONFIG', - 'regSQ_ARB_CONFIG_BASE_IDX', 'regSQ_CMD', 'regSQ_CMD_BASE_IDX', - 'regSQ_CONFIG', 'regSQ_CONFIG_BASE_IDX', 'regSQ_DEBUG', - 'regSQ_DEBUG_BASE_IDX', 'regSQ_DEBUG_HOST_TRAP_STATUS', - 'regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX', 'regSQ_DEBUG_STS_GLOBAL', - 'regSQ_DEBUG_STS_GLOBAL2', 'regSQ_DEBUG_STS_GLOBAL2_BASE_IDX', - 'regSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'regSQ_DSM_CNTL', - 'regSQ_DSM_CNTL2', 'regSQ_DSM_CNTL2_BASE_IDX', - 'regSQ_DSM_CNTL_BASE_IDX', 'regSQ_FIFO_SIZES', - 'regSQ_FIFO_SIZES_BASE_IDX', 'regSQ_IND_DATA', - 'regSQ_IND_DATA_BASE_IDX', 'regSQ_IND_INDEX', - 'regSQ_IND_INDEX_BASE_IDX', 'regSQ_INTERRUPT_AUTO_MASK', - 'regSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'regSQ_INTERRUPT_MSG_CTRL', - 'regSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'regSQ_LDS_CLK_CTRL', - 'regSQ_LDS_CLK_CTRL_BASE_IDX', 'regSQ_PERFCOUNTER0_LO', - 'regSQ_PERFCOUNTER0_LO_BASE_IDX', 'regSQ_PERFCOUNTER0_SELECT', - 'regSQ_PERFCOUNTER0_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER10_SELECT', - 'regSQ_PERFCOUNTER10_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER11_SELECT', - 'regSQ_PERFCOUNTER11_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER12_SELECT', - 'regSQ_PERFCOUNTER12_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER13_SELECT', - 'regSQ_PERFCOUNTER13_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER14_SELECT', - 'regSQ_PERFCOUNTER14_SELECT_BASE_IDX', - 'regSQ_PERFCOUNTER15_SELECT', - 'regSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER1_LO', - 'regSQ_PERFCOUNTER1_LO_BASE_IDX', 'regSQ_PERFCOUNTER1_SELECT', - 'regSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER2_LO', - 'regSQ_PERFCOUNTER2_LO_BASE_IDX', 'regSQ_PERFCOUNTER2_SELECT', - 'regSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER3_LO', - 'regSQ_PERFCOUNTER3_LO_BASE_IDX', 'regSQ_PERFCOUNTER3_SELECT', - 'regSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER4_LO', - 'regSQ_PERFCOUNTER4_LO_BASE_IDX', 'regSQ_PERFCOUNTER4_SELECT', - 'regSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER5_LO', - 'regSQ_PERFCOUNTER5_LO_BASE_IDX', 'regSQ_PERFCOUNTER5_SELECT', - 'regSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER6_LO', - 'regSQ_PERFCOUNTER6_LO_BASE_IDX', 'regSQ_PERFCOUNTER6_SELECT', - 'regSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER7_LO', - 'regSQ_PERFCOUNTER7_LO_BASE_IDX', 'regSQ_PERFCOUNTER7_SELECT', - 'regSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER8_SELECT', - 'regSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER9_SELECT', - 'regSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'regSQ_PERFCOUNTER_CTRL', - 'regSQ_PERFCOUNTER_CTRL2', 'regSQ_PERFCOUNTER_CTRL2_BASE_IDX', - 'regSQ_PERFCOUNTER_CTRL_BASE_IDX', 'regSQ_PERF_SNAPSHOT_CTRL', - 'regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX', 'regSQ_RANDOM_WAVE_PRI', - 'regSQ_RANDOM_WAVE_PRI_BASE_IDX', 'regSQ_RUNTIME_CONFIG', - 'regSQ_RUNTIME_CONFIG_BASE_IDX', 'regSQ_SHADER_TBA_HI', - 'regSQ_SHADER_TBA_HI_BASE_IDX', 'regSQ_SHADER_TBA_LO', - 'regSQ_SHADER_TBA_LO_BASE_IDX', 'regSQ_SHADER_TMA_HI', - 'regSQ_SHADER_TMA_HI_BASE_IDX', 'regSQ_SHADER_TMA_LO', - 'regSQ_SHADER_TMA_LO_BASE_IDX', 'regSQ_TEX_CLK_CTRL', - 'regSQ_TEX_CLK_CTRL_BASE_IDX', 'regSQ_THREAD_TRACE_BUF0_BASE', - 'regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX', - 'regSQ_THREAD_TRACE_BUF0_SIZE', - 'regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX', - 'regSQ_THREAD_TRACE_BUF1_BASE', - 'regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX', - 'regSQ_THREAD_TRACE_BUF1_SIZE', - 'regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX', - 'regSQ_THREAD_TRACE_CTRL', 'regSQ_THREAD_TRACE_CTRL_BASE_IDX', - 'regSQ_THREAD_TRACE_DROPPED_CNTR', - 'regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_GFX_DRAW_CNTR', - 'regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_GFX_MARKER_CNTR', - 'regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR', - 'regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR', - 'regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX', - 'regSQ_THREAD_TRACE_MASK', 'regSQ_THREAD_TRACE_MASK_BASE_IDX', - 'regSQ_THREAD_TRACE_STATUS', 'regSQ_THREAD_TRACE_STATUS2', - 'regSQ_THREAD_TRACE_STATUS2_BASE_IDX', - 'regSQ_THREAD_TRACE_STATUS_BASE_IDX', - 'regSQ_THREAD_TRACE_TOKEN_MASK', - 'regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_0', - 'regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_1', - 'regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_2', - 'regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_3', - 'regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_4', - 'regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_5', - 'regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_6', - 'regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX', - 'regSQ_THREAD_TRACE_USERDATA_7', - 'regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX', - 'regSQ_THREAD_TRACE_WPTR', 'regSQ_THREAD_TRACE_WPTR_BASE_IDX', - 'regSQ_WATCH0_ADDR_H', 'regSQ_WATCH0_ADDR_H_BASE_IDX', - 'regSQ_WATCH0_ADDR_L', 'regSQ_WATCH0_ADDR_L_BASE_IDX', - 'regSQ_WATCH0_CNTL', 'regSQ_WATCH0_CNTL_BASE_IDX', - 'regSQ_WATCH1_ADDR_H', 'regSQ_WATCH1_ADDR_H_BASE_IDX', - 'regSQ_WATCH1_ADDR_L', 'regSQ_WATCH1_ADDR_L_BASE_IDX', - 'regSQ_WATCH1_CNTL', 'regSQ_WATCH1_CNTL_BASE_IDX', - 'regSQ_WATCH2_ADDR_H', 'regSQ_WATCH2_ADDR_H_BASE_IDX', - 'regSQ_WATCH2_ADDR_L', 'regSQ_WATCH2_ADDR_L_BASE_IDX', - 'regSQ_WATCH2_CNTL', 'regSQ_WATCH2_CNTL_BASE_IDX', - 'regSQ_WATCH3_ADDR_H', 'regSQ_WATCH3_ADDR_H_BASE_IDX', - 'regSQ_WATCH3_ADDR_L', 'regSQ_WATCH3_ADDR_L_BASE_IDX', - 'regSQ_WATCH3_CNTL', 'regSQ_WATCH3_CNTL_BASE_IDX', - 'regSX_BLEND_OPT_CONTROL', 'regSX_BLEND_OPT_CONTROL_BASE_IDX', - 'regSX_BLEND_OPT_EPSILON', 'regSX_BLEND_OPT_EPSILON_BASE_IDX', - 'regSX_DEBUG_1', 'regSX_DEBUG_1_BASE_IDX', 'regSX_MRT0_BLEND_OPT', - 'regSX_MRT0_BLEND_OPT_BASE_IDX', 'regSX_MRT1_BLEND_OPT', - 'regSX_MRT1_BLEND_OPT_BASE_IDX', 'regSX_MRT2_BLEND_OPT', - 'regSX_MRT2_BLEND_OPT_BASE_IDX', 'regSX_MRT3_BLEND_OPT', - 'regSX_MRT3_BLEND_OPT_BASE_IDX', 'regSX_MRT4_BLEND_OPT', - 'regSX_MRT4_BLEND_OPT_BASE_IDX', 'regSX_MRT5_BLEND_OPT', - 'regSX_MRT5_BLEND_OPT_BASE_IDX', 'regSX_MRT6_BLEND_OPT', - 'regSX_MRT6_BLEND_OPT_BASE_IDX', 'regSX_MRT7_BLEND_OPT', - 'regSX_MRT7_BLEND_OPT_BASE_IDX', 'regSX_PERFCOUNTER0_HI', - 'regSX_PERFCOUNTER0_HI_BASE_IDX', 'regSX_PERFCOUNTER0_LO', - 'regSX_PERFCOUNTER0_LO_BASE_IDX', 'regSX_PERFCOUNTER0_SELECT', - 'regSX_PERFCOUNTER0_SELECT1', - 'regSX_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regSX_PERFCOUNTER0_SELECT_BASE_IDX', 'regSX_PERFCOUNTER1_HI', - 'regSX_PERFCOUNTER1_HI_BASE_IDX', 'regSX_PERFCOUNTER1_LO', - 'regSX_PERFCOUNTER1_LO_BASE_IDX', 'regSX_PERFCOUNTER1_SELECT', - 'regSX_PERFCOUNTER1_SELECT1', - 'regSX_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regSX_PERFCOUNTER1_SELECT_BASE_IDX', 'regSX_PERFCOUNTER2_HI', - 'regSX_PERFCOUNTER2_HI_BASE_IDX', 'regSX_PERFCOUNTER2_LO', - 'regSX_PERFCOUNTER2_LO_BASE_IDX', 'regSX_PERFCOUNTER2_SELECT', - 'regSX_PERFCOUNTER2_SELECT_BASE_IDX', 'regSX_PERFCOUNTER3_HI', - 'regSX_PERFCOUNTER3_HI_BASE_IDX', 'regSX_PERFCOUNTER3_LO', - 'regSX_PERFCOUNTER3_LO_BASE_IDX', 'regSX_PERFCOUNTER3_SELECT', - 'regSX_PERFCOUNTER3_SELECT_BASE_IDX', 'regSX_PS_DOWNCONVERT', - 'regSX_PS_DOWNCONVERT_BASE_IDX', 'regSX_PS_DOWNCONVERT_CONTROL', - 'regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'regTA_BC_BASE_ADDR', - 'regTA_BC_BASE_ADDR_BASE_IDX', 'regTA_BC_BASE_ADDR_HI', - 'regTA_BC_BASE_ADDR_HI_BASE_IDX', 'regTA_CGTT_CTRL', - 'regTA_CGTT_CTRL_BASE_IDX', 'regTA_CNTL', 'regTA_CNTL2', - 'regTA_CNTL2_BASE_IDX', 'regTA_CNTL_AUX', - 'regTA_CNTL_AUX_BASE_IDX', 'regTA_CNTL_BASE_IDX', - 'regTA_CS_BC_BASE_ADDR', 'regTA_CS_BC_BASE_ADDR_BASE_IDX', - 'regTA_CS_BC_BASE_ADDR_HI', 'regTA_CS_BC_BASE_ADDR_HI_BASE_IDX', - 'regTA_PERFCOUNTER0_HI', 'regTA_PERFCOUNTER0_HI_BASE_IDX', - 'regTA_PERFCOUNTER0_LO', 'regTA_PERFCOUNTER0_LO_BASE_IDX', - 'regTA_PERFCOUNTER0_SELECT', 'regTA_PERFCOUNTER0_SELECT1', - 'regTA_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regTA_PERFCOUNTER0_SELECT_BASE_IDX', 'regTA_PERFCOUNTER1_HI', - 'regTA_PERFCOUNTER1_HI_BASE_IDX', 'regTA_PERFCOUNTER1_LO', - 'regTA_PERFCOUNTER1_LO_BASE_IDX', 'regTA_PERFCOUNTER1_SELECT', - 'regTA_PERFCOUNTER1_SELECT_BASE_IDX', 'regTA_SCRATCH', - 'regTA_SCRATCH_BASE_IDX', 'regTA_STATUS', 'regTA_STATUS_BASE_IDX', - 'regTCP_CNTL', 'regTCP_CNTL2', 'regTCP_CNTL2_BASE_IDX', - 'regTCP_CNTL_BASE_IDX', 'regTCP_DEBUG_DATA', - 'regTCP_DEBUG_DATA_BASE_IDX', 'regTCP_DEBUG_INDEX', - 'regTCP_DEBUG_INDEX_BASE_IDX', 'regTCP_INVALIDATE', - 'regTCP_INVALIDATE_BASE_IDX', 'regTCP_PERFCOUNTER0_HI', - 'regTCP_PERFCOUNTER0_HI_BASE_IDX', 'regTCP_PERFCOUNTER0_LO', - 'regTCP_PERFCOUNTER0_LO_BASE_IDX', 'regTCP_PERFCOUNTER0_SELECT', - 'regTCP_PERFCOUNTER0_SELECT1', - 'regTCP_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER1_HI', - 'regTCP_PERFCOUNTER1_HI_BASE_IDX', 'regTCP_PERFCOUNTER1_LO', - 'regTCP_PERFCOUNTER1_LO_BASE_IDX', 'regTCP_PERFCOUNTER1_SELECT', - 'regTCP_PERFCOUNTER1_SELECT1', - 'regTCP_PERFCOUNTER1_SELECT1_BASE_IDX', - 'regTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER2_HI', - 'regTCP_PERFCOUNTER2_HI_BASE_IDX', 'regTCP_PERFCOUNTER2_LO', - 'regTCP_PERFCOUNTER2_LO_BASE_IDX', 'regTCP_PERFCOUNTER2_SELECT', - 'regTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'regTCP_PERFCOUNTER3_HI', - 'regTCP_PERFCOUNTER3_HI_BASE_IDX', 'regTCP_PERFCOUNTER3_LO', - 'regTCP_PERFCOUNTER3_LO_BASE_IDX', 'regTCP_PERFCOUNTER3_SELECT', - 'regTCP_PERFCOUNTER3_SELECT_BASE_IDX', - 'regTCP_PERFCOUNTER_FILTER', 'regTCP_PERFCOUNTER_FILTER2', - 'regTCP_PERFCOUNTER_FILTER2_BASE_IDX', - 'regTCP_PERFCOUNTER_FILTER_BASE_IDX', - 'regTCP_PERFCOUNTER_FILTER_EN', - 'regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'regTCP_STATUS', - 'regTCP_STATUS_BASE_IDX', 'regTCP_WATCH0_ADDR_H', - 'regTCP_WATCH0_ADDR_H_BASE_IDX', 'regTCP_WATCH0_ADDR_L', - 'regTCP_WATCH0_ADDR_L_BASE_IDX', 'regTCP_WATCH0_CNTL', - 'regTCP_WATCH0_CNTL_BASE_IDX', 'regTCP_WATCH1_ADDR_H', - 'regTCP_WATCH1_ADDR_H_BASE_IDX', 'regTCP_WATCH1_ADDR_L', - 'regTCP_WATCH1_ADDR_L_BASE_IDX', 'regTCP_WATCH1_CNTL', - 'regTCP_WATCH1_CNTL_BASE_IDX', 'regTCP_WATCH2_ADDR_H', - 'regTCP_WATCH2_ADDR_H_BASE_IDX', 'regTCP_WATCH2_ADDR_L', - 'regTCP_WATCH2_ADDR_L_BASE_IDX', 'regTCP_WATCH2_CNTL', - 'regTCP_WATCH2_CNTL_BASE_IDX', 'regTCP_WATCH3_ADDR_H', - 'regTCP_WATCH3_ADDR_H_BASE_IDX', 'regTCP_WATCH3_ADDR_L', - 'regTCP_WATCH3_ADDR_L_BASE_IDX', 'regTCP_WATCH3_CNTL', - 'regTCP_WATCH3_CNTL_BASE_IDX', 'regTD_DSM_CNTL', - 'regTD_DSM_CNTL2', 'regTD_DSM_CNTL2_BASE_IDX', - 'regTD_DSM_CNTL_BASE_IDX', 'regTD_PERFCOUNTER0_HI', - 'regTD_PERFCOUNTER0_HI_BASE_IDX', 'regTD_PERFCOUNTER0_LO', - 'regTD_PERFCOUNTER0_LO_BASE_IDX', 'regTD_PERFCOUNTER0_SELECT', - 'regTD_PERFCOUNTER0_SELECT1', - 'regTD_PERFCOUNTER0_SELECT1_BASE_IDX', - 'regTD_PERFCOUNTER0_SELECT_BASE_IDX', 'regTD_PERFCOUNTER1_HI', - 'regTD_PERFCOUNTER1_HI_BASE_IDX', 'regTD_PERFCOUNTER1_LO', - 'regTD_PERFCOUNTER1_LO_BASE_IDX', 'regTD_PERFCOUNTER1_SELECT', - 'regTD_PERFCOUNTER1_SELECT_BASE_IDX', 'regTD_SCRATCH', - 'regTD_SCRATCH_BASE_IDX', 'regTD_STATUS', 'regTD_STATUS_BASE_IDX', - 'regUCONFIG_RESERVED_REG0', 'regUCONFIG_RESERVED_REG0_BASE_IDX', - 'regUCONFIG_RESERVED_REG1', 'regUCONFIG_RESERVED_REG1_BASE_IDX', - 'regUTCL1_ALOG', 'regUTCL1_ALOG_BASE_IDX', 'regUTCL1_CTRL_0', - 'regUTCL1_CTRL_0_BASE_IDX', 'regUTCL1_CTRL_1', - 'regUTCL1_CTRL_1_BASE_IDX', 'regUTCL1_CTRL_2', - 'regUTCL1_CTRL_2_BASE_IDX', 'regUTCL1_FIFO_SIZING', - 'regUTCL1_FIFO_SIZING_BASE_IDX', 'regUTCL1_PERFCOUNTER0_HI', - 'regUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'regUTCL1_PERFCOUNTER0_LO', - 'regUTCL1_PERFCOUNTER0_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER0_SELECT', - 'regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX', - 'regUTCL1_PERFCOUNTER1_HI', 'regUTCL1_PERFCOUNTER1_HI_BASE_IDX', - 'regUTCL1_PERFCOUNTER1_LO', 'regUTCL1_PERFCOUNTER1_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER1_SELECT', - 'regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX', - 'regUTCL1_PERFCOUNTER2_HI', 'regUTCL1_PERFCOUNTER2_HI_BASE_IDX', - 'regUTCL1_PERFCOUNTER2_LO', 'regUTCL1_PERFCOUNTER2_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER2_SELECT', - 'regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX', - 'regUTCL1_PERFCOUNTER3_HI', 'regUTCL1_PERFCOUNTER3_HI_BASE_IDX', - 'regUTCL1_PERFCOUNTER3_LO', 'regUTCL1_PERFCOUNTER3_LO_BASE_IDX', - 'regUTCL1_PERFCOUNTER3_SELECT', - 'regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX', 'regUTCL1_STATUS', - 'regUTCL1_STATUS_BASE_IDX', 'regUTCL1_UTCL0_INVREQ_DISABLE', - 'regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', 'regVGT_DMA_BASE', - 'regVGT_DMA_BASE_BASE_IDX', 'regVGT_DMA_BASE_HI', - 'regVGT_DMA_BASE_HI_BASE_IDX', 'regVGT_DMA_DATA_FIFO_DEPTH', - 'regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_INDEX_TYPE', - 'regVGT_DMA_INDEX_TYPE_BASE_IDX', 'regVGT_DMA_MAX_SIZE', - 'regVGT_DMA_MAX_SIZE_BASE_IDX', 'regVGT_DMA_NUM_INSTANCES', - 'regVGT_DMA_NUM_INSTANCES_BASE_IDX', 'regVGT_DMA_REQ_FIFO_DEPTH', - 'regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'regVGT_DMA_SIZE', - 'regVGT_DMA_SIZE_BASE_IDX', 'regVGT_DRAW_INITIATOR', - 'regVGT_DRAW_INITIATOR_BASE_IDX', 'regVGT_DRAW_INIT_FIFO_DEPTH', - 'regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', - 'regVGT_DRAW_PAYLOAD_CNTL', 'regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', - 'regVGT_ENHANCE', 'regVGT_ENHANCE_BASE_IDX', - 'regVGT_ESGS_RING_ITEMSIZE', 'regVGT_ESGS_RING_ITEMSIZE_BASE_IDX', - 'regVGT_EVENT_ADDRESS_REG', 'regVGT_EVENT_ADDRESS_REG_BASE_IDX', - 'regVGT_EVENT_INITIATOR', 'regVGT_EVENT_INITIATOR_BASE_IDX', - 'regVGT_GS_INSTANCE_CNT', 'regVGT_GS_INSTANCE_CNT_BASE_IDX', - 'regVGT_GS_MAX_VERT_OUT', 'regVGT_GS_MAX_VERT_OUT_BASE_IDX', - 'regVGT_GS_MAX_WAVE_ID', 'regVGT_GS_MAX_WAVE_ID_BASE_IDX', - 'regVGT_GS_OUT_PRIM_TYPE', 'regVGT_GS_OUT_PRIM_TYPE_BASE_IDX', - 'regVGT_HOS_MAX_TESS_LEVEL', 'regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', - 'regVGT_HOS_MIN_TESS_LEVEL', 'regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', - 'regVGT_HS_OFFCHIP_PARAM', 'regVGT_HS_OFFCHIP_PARAM_BASE_IDX', - 'regVGT_INDEX_TYPE', 'regVGT_INDEX_TYPE_BASE_IDX', - 'regVGT_INSTANCE_BASE_ID', 'regVGT_INSTANCE_BASE_ID_BASE_IDX', - 'regVGT_LS_HS_CONFIG', 'regVGT_LS_HS_CONFIG_BASE_IDX', - 'regVGT_MC_LAT_CNTL', 'regVGT_MC_LAT_CNTL_BASE_IDX', - 'regVGT_MULTI_PRIM_IB_RESET_INDX', - 'regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'regVGT_NUM_INDICES', - 'regVGT_NUM_INDICES_BASE_IDX', 'regVGT_NUM_INSTANCES', - 'regVGT_NUM_INSTANCES_BASE_IDX', 'regVGT_PRIMITIVEID_EN', - 'regVGT_PRIMITIVEID_EN_BASE_IDX', 'regVGT_PRIMITIVEID_RESET', - 'regVGT_PRIMITIVEID_RESET_BASE_IDX', 'regVGT_PRIMITIVE_TYPE', - 'regVGT_PRIMITIVE_TYPE_BASE_IDX', 'regVGT_REUSE_OFF', - 'regVGT_REUSE_OFF_BASE_IDX', 'regVGT_SHADER_STAGES_EN', - 'regVGT_SHADER_STAGES_EN_BASE_IDX', - 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE', - 'regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX', - 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET', - 'regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX', - 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE', - 'regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX', - 'regVGT_SYS_CONFIG', 'regVGT_SYS_CONFIG_BASE_IDX', - 'regVGT_TESS_DISTRIBUTION', 'regVGT_TESS_DISTRIBUTION_BASE_IDX', - 'regVGT_TF_MEMORY_BASE', 'regVGT_TF_MEMORY_BASE_BASE_IDX', - 'regVGT_TF_MEMORY_BASE_HI', 'regVGT_TF_MEMORY_BASE_HI_BASE_IDX', - 'regVGT_TF_PARAM', 'regVGT_TF_PARAM_BASE_IDX', - 'regVGT_TF_RING_SIZE', 'regVGT_TF_RING_SIZE_BASE_IDX', - 'regVIOLATION_DATA_ASYNC_VF_PROG', - 'regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'regWD_CNTL_STATUS', - 'regWD_CNTL_STATUS_BASE_IDX', 'regWD_ENHANCE', - 'regWD_ENHANCE_BASE_IDX', 'regWD_QOS', 'regWD_QOS_BASE_IDX', - 'regWD_UTCL1_CNTL', 'regWD_UTCL1_CNTL_BASE_IDX', - 'regWD_UTCL1_STATUS', 'regWD_UTCL1_STATUS_BASE_IDX', - 'struct_IP_BASE', 'struct_IP_BASE_INSTANCE', - 'struct_SDMA_PKT_ATOMIC_TAG', 'struct_SDMA_PKT_ATOMIC_TAG_0_0', - 'struct_SDMA_PKT_ATOMIC_TAG_1_0', - 'struct_SDMA_PKT_ATOMIC_TAG_2_0', - 'struct_SDMA_PKT_ATOMIC_TAG_3_0', - 'struct_SDMA_PKT_ATOMIC_TAG_4_0', - 'struct_SDMA_PKT_ATOMIC_TAG_5_0', - 'struct_SDMA_PKT_ATOMIC_TAG_6_0', - 'struct_SDMA_PKT_ATOMIC_TAG_7_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_0_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_1_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_2_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_3_0', - 'struct_SDMA_PKT_CONSTANT_FILL_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_10_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_11_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_12_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_6_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_7_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_8_0', - 'struct_SDMA_PKT_COPY_LINEAR_RECT_TAG_9_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_0_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_1_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_2_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_3_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_4_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_5_0', - 'struct_SDMA_PKT_COPY_LINEAR_TAG_6_0', - 'struct_SDMA_PKT_FENCE_TAG', 'struct_SDMA_PKT_FENCE_TAG_0_0', - 'struct_SDMA_PKT_FENCE_TAG_1_0', 'struct_SDMA_PKT_FENCE_TAG_2_0', - 'struct_SDMA_PKT_FENCE_TAG_3_0', 'struct_SDMA_PKT_GCR_TAG', - 'struct_SDMA_PKT_GCR_TAG_0_0', 'struct_SDMA_PKT_GCR_TAG_1_0', - 'struct_SDMA_PKT_GCR_TAG_2_0', 'struct_SDMA_PKT_GCR_TAG_3_0', - 'struct_SDMA_PKT_GCR_TAG_4_0', 'struct_SDMA_PKT_HDP_FLUSH_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_0_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_1_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_2_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_3_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_4_0', - 'struct_SDMA_PKT_POLL_REGMEM_TAG_5_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG', - 'struct_SDMA_PKT_TIMESTAMP_TAG_0_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', - 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', - 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_LO_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_HEADER_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_LOOP_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_HI_UNION', - 'union_SDMA_PKT_ATOMIC_TAG_SRC_DATA_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_COUNT_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DATA_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_CONSTANT_FILL_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_DST_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_RECT_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_1_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_2_UNION', - 'union_SDMA_PKT_COPY_LINEAR_RECT_TAG_SRC_PARAMETER_3_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_COUNT_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_DST_ADDR_LO_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_HEADER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_PARAMETER_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_HI_UNION', - 'union_SDMA_PKT_COPY_LINEAR_TAG_SRC_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_FENCE_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_FENCE_TAG_DATA_UNION', - 'union_SDMA_PKT_FENCE_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_HEADER_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD1_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD2_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD3_UNION', - 'union_SDMA_PKT_GCR_TAG_WORD4_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_DW5_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_HEADER_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_MASK_UNION', - 'union_SDMA_PKT_POLL_REGMEM_TAG_VALUE_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_HI_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', - 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] +class IP_BASE(Struct): pass +IP_BASE._fields_ = [ + ('instance', (IP_BASE_INSTANCE * 7)), +] +SDMA_OP_COPY = 1 +SDMA_OP_FENCE = 5 +SDMA_OP_TRAP = 6 +SDMA_OP_POLL_REGMEM = 8 +SDMA_OP_ATOMIC = 10 +SDMA_OP_CONST_FILL = 11 +SDMA_OP_TIMESTAMP = 13 +SDMA_OP_GCR = 17 +SDMA_SUBOP_COPY_LINEAR = 0 +SDMA_SUBOP_COPY_LINEAR_RECT = 4 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 +SDMA_SUBOP_USER_GCR = 1 +SDMA_ATOMIC_ADD64 = 47 +PACKET_TYPE0 = 0 +PACKET_TYPE1 = 1 +PACKET_TYPE2 = 2 +PACKET_TYPE3 = 3 +CP_PACKET_GET_TYPE = lambda h: (((h) >> 30) & 3) +CP_PACKET_GET_COUNT = lambda h: (((h) >> 16) & 0x3FFF) +CP_PACKET0_GET_REG = lambda h: ((h) & 0xFFFF) +CP_PACKET3_GET_OPCODE = lambda h: (((h) >> 8) & 0xFF) +PACKET0 = lambda reg,n: ((PACKET_TYPE0 << 30) | ((reg) & 0xFFFF) | ((n) & 0x3FFF) << 16) +CP_PACKET2 = 0x80000000 +PACKET2_PAD_SHIFT = 0 +PACKET2_PAD_MASK = (0x3fffffff << 0) +PACKET2 = lambda v: (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +PACKET3 = lambda op,n: ((PACKET_TYPE3 << 30) | (((op) & 0xFF) << 8) | ((n) & 0x3FFF) << 16) +PACKET3_COMPUTE = lambda op,n: (PACKET3(op, n) | 1 << 1) +PACKET3_NOP = 0x10 +PACKET3_SET_BASE = 0x11 +PACKET3_BASE_INDEX = lambda x: ((x) << 0) +CE_PARTITION_BASE = 3 +PACKET3_CLEAR_STATE = 0x12 +PACKET3_INDEX_BUFFER_SIZE = 0x13 +PACKET3_DISPATCH_DIRECT = 0x15 +PACKET3_DISPATCH_INDIRECT = 0x16 +PACKET3_INDIRECT_BUFFER_END = 0x17 +PACKET3_INDIRECT_BUFFER_CNST_END = 0x19 +PACKET3_ATOMIC_GDS = 0x1D +PACKET3_ATOMIC_MEM = 0x1E +PACKET3_OCCLUSION_QUERY = 0x1F +PACKET3_SET_PREDICATION = 0x20 +PACKET3_REG_RMW = 0x21 +PACKET3_COND_EXEC = 0x22 +PACKET3_PRED_EXEC = 0x23 +PACKET3_DRAW_INDIRECT = 0x24 +PACKET3_DRAW_INDEX_INDIRECT = 0x25 +PACKET3_INDEX_BASE = 0x26 +PACKET3_DRAW_INDEX_2 = 0x27 +PACKET3_CONTEXT_CONTROL = 0x28 +PACKET3_INDEX_TYPE = 0x2A +PACKET3_DRAW_INDIRECT_MULTI = 0x2C +PACKET3_DRAW_INDEX_AUTO = 0x2D +PACKET3_NUM_INSTANCES = 0x2F +PACKET3_DRAW_INDEX_MULTI_AUTO = 0x30 +PACKET3_INDIRECT_BUFFER_PRIV = 0x32 +PACKET3_INDIRECT_BUFFER_CNST = 0x33 +PACKET3_COND_INDIRECT_BUFFER_CNST = 0x33 +PACKET3_STRMOUT_BUFFER_UPDATE = 0x34 +PACKET3_DRAW_INDEX_OFFSET_2 = 0x35 +PACKET3_DRAW_PREAMBLE = 0x36 +PACKET3_WRITE_DATA = 0x37 +WRITE_DATA_DST_SEL = lambda x: ((x) << 8) +WR_ONE_ADDR = (1 << 16) +WR_CONFIRM = (1 << 20) +WRITE_DATA_CACHE_POLICY = lambda x: ((x) << 25) +WRITE_DATA_ENGINE_SEL = lambda x: ((x) << 30) +PACKET3_DRAW_INDEX_INDIRECT_MULTI = 0x38 +PACKET3_MEM_SEMAPHORE = 0x39 +PACKET3_SEM_USE_MAILBOX = (0x1 << 16) +PACKET3_SEM_SEL_SIGNAL_TYPE = (0x1 << 20) +PACKET3_SEM_SEL_SIGNAL = (0x6 << 29) +PACKET3_SEM_SEL_WAIT = (0x7 << 29) +PACKET3_DRAW_INDEX_MULTI_INST = 0x3A +PACKET3_COPY_DW = 0x3B +PACKET3_WAIT_REG_MEM = 0x3C +WAIT_REG_MEM_FUNCTION = lambda x: ((x) << 0) +WAIT_REG_MEM_MEM_SPACE = lambda x: ((x) << 4) +WAIT_REG_MEM_OPERATION = lambda x: ((x) << 6) +WAIT_REG_MEM_ENGINE = lambda x: ((x) << 8) +PACKET3_INDIRECT_BUFFER = 0x3F +INDIRECT_BUFFER_VALID = (1 << 23) +INDIRECT_BUFFER_CACHE_POLICY = lambda x: ((x) << 28) +INDIRECT_BUFFER_PRE_ENB = lambda x: ((x) << 21) +INDIRECT_BUFFER_PRE_RESUME = lambda x: ((x) << 30) +PACKET3_COND_INDIRECT_BUFFER = 0x3F +PACKET3_COPY_DATA = 0x40 +PACKET3_CP_DMA = 0x41 +PACKET3_PFP_SYNC_ME = 0x42 +PACKET3_SURFACE_SYNC = 0x43 +PACKET3_ME_INITIALIZE = 0x44 +PACKET3_COND_WRITE = 0x45 +PACKET3_EVENT_WRITE = 0x46 +EVENT_TYPE = lambda x: ((x) << 0) +EVENT_INDEX = lambda x: ((x) << 8) +PACKET3_EVENT_WRITE_EOP = 0x47 +PACKET3_EVENT_WRITE_EOS = 0x48 +PACKET3_RELEASE_MEM = 0x49 +PACKET3_RELEASE_MEM_EVENT_TYPE = lambda x: ((x) << 0) +PACKET3_RELEASE_MEM_EVENT_INDEX = lambda x: ((x) << 8) +PACKET3_RELEASE_MEM_GCR_GLM_WB = (1 << 12) +PACKET3_RELEASE_MEM_GCR_GLM_INV = (1 << 13) +PACKET3_RELEASE_MEM_GCR_GLV_INV = (1 << 14) +PACKET3_RELEASE_MEM_GCR_GL1_INV = (1 << 15) +PACKET3_RELEASE_MEM_GCR_GL2_US = (1 << 16) +PACKET3_RELEASE_MEM_GCR_GL2_RANGE = (1 << 17) +PACKET3_RELEASE_MEM_GCR_GL2_DISCARD = (1 << 19) +PACKET3_RELEASE_MEM_GCR_GL2_INV = (1 << 20) +PACKET3_RELEASE_MEM_GCR_GL2_WB = (1 << 21) +PACKET3_RELEASE_MEM_GCR_SEQ = (1 << 22) +PACKET3_RELEASE_MEM_CACHE_POLICY = lambda x: ((x) << 25) +PACKET3_RELEASE_MEM_EXECUTE = (1 << 28) +PACKET3_RELEASE_MEM_DATA_SEL = lambda x: ((x) << 29) +PACKET3_RELEASE_MEM_INT_SEL = lambda x: ((x) << 24) +PACKET3_RELEASE_MEM_DST_SEL = lambda x: ((x) << 16) +PACKET3_PREAMBLE_CNTL = 0x4A +PACKET3_PREAMBLE_BEGIN_CLEAR_STATE = (2 << 28) +PACKET3_PREAMBLE_END_CLEAR_STATE = (3 << 28) +PACKET3_DMA_DATA = 0x50 +PACKET3_DMA_DATA_ENGINE = lambda x: ((x) << 0) +PACKET3_DMA_DATA_SRC_CACHE_POLICY = lambda x: ((x) << 13) +PACKET3_DMA_DATA_DST_SEL = lambda x: ((x) << 20) +PACKET3_DMA_DATA_DST_CACHE_POLICY = lambda x: ((x) << 25) +PACKET3_DMA_DATA_SRC_SEL = lambda x: ((x) << 29) +PACKET3_DMA_DATA_CP_SYNC = (1 << 31) +PACKET3_DMA_DATA_CMD_SAS = (1 << 26) +PACKET3_DMA_DATA_CMD_DAS = (1 << 27) +PACKET3_DMA_DATA_CMD_SAIC = (1 << 28) +PACKET3_DMA_DATA_CMD_DAIC = (1 << 29) +PACKET3_DMA_DATA_CMD_RAW_WAIT = (1 << 30) +PACKET3_CONTEXT_REG_RMW = 0x51 +PACKET3_GFX_CNTX_UPDATE = 0x52 +PACKET3_BLK_CNTX_UPDATE = 0x53 +PACKET3_INCR_UPDT_STATE = 0x55 +PACKET3_ACQUIRE_MEM = 0x58 +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV = lambda x: ((x) << 0) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE = lambda x: ((x) << 2) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB = lambda x: ((x) << 4) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV = lambda x: ((x) << 5) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB = lambda x: ((x) << 6) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV = lambda x: ((x) << 7) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV = lambda x: ((x) << 8) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV = lambda x: ((x) << 9) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US = lambda x: ((x) << 10) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE = lambda x: ((x) << 11) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD = lambda x: ((x) << 13) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV = lambda x: ((x) << 14) +PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB = lambda x: ((x) << 15) +PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ = lambda x: ((x) << 16) +PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA = (1 << 18) +PACKET3_REWIND = 0x59 +PACKET3_INTERRUPT = 0x5A +PACKET3_GEN_PDEPTE = 0x5B +PACKET3_INDIRECT_BUFFER_PASID = 0x5C +PACKET3_PRIME_UTCL2 = 0x5D +PACKET3_LOAD_UCONFIG_REG = 0x5E +PACKET3_LOAD_SH_REG = 0x5F +PACKET3_LOAD_CONFIG_REG = 0x60 +PACKET3_LOAD_CONTEXT_REG = 0x61 +PACKET3_LOAD_COMPUTE_STATE = 0x62 +PACKET3_LOAD_SH_REG_INDEX = 0x63 +PACKET3_SET_CONFIG_REG = 0x68 +PACKET3_SET_CONFIG_REG_START = 0x00002000 +PACKET3_SET_CONFIG_REG_END = 0x00002c00 +PACKET3_SET_CONTEXT_REG = 0x69 +PACKET3_SET_CONTEXT_REG_START = 0x0000a000 +PACKET3_SET_CONTEXT_REG_END = 0x0000a400 +PACKET3_SET_CONTEXT_REG_INDEX = 0x6A +PACKET3_SET_VGPR_REG_DI_MULTI = 0x71 +PACKET3_SET_SH_REG_DI = 0x72 +PACKET3_SET_CONTEXT_REG_INDIRECT = 0x73 +PACKET3_SET_SH_REG_DI_MULTI = 0x74 +PACKET3_GFX_PIPE_LOCK = 0x75 +PACKET3_SET_SH_REG = 0x76 +PACKET3_SET_SH_REG_START = 0x00002c00 +PACKET3_SET_SH_REG_END = 0x00003000 +PACKET3_SET_SH_REG_OFFSET = 0x77 +PACKET3_SET_QUEUE_REG = 0x78 +PACKET3_SET_UCONFIG_REG = 0x79 +PACKET3_SET_UCONFIG_REG_START = 0x0000c000 +PACKET3_SET_UCONFIG_REG_END = 0x0000c400 +PACKET3_SET_UCONFIG_REG_INDEX = 0x7A +PACKET3_FORWARD_HEADER = 0x7C +PACKET3_SCRATCH_RAM_WRITE = 0x7D +PACKET3_SCRATCH_RAM_READ = 0x7E +PACKET3_LOAD_CONST_RAM = 0x80 +PACKET3_WRITE_CONST_RAM = 0x81 +PACKET3_DUMP_CONST_RAM = 0x83 +PACKET3_INCREMENT_CE_COUNTER = 0x84 +PACKET3_INCREMENT_DE_COUNTER = 0x85 +PACKET3_WAIT_ON_CE_COUNTER = 0x86 +PACKET3_WAIT_ON_DE_COUNTER_DIFF = 0x88 +PACKET3_SWITCH_BUFFER = 0x8B +PACKET3_DISPATCH_DRAW_PREAMBLE = 0x8C +PACKET3_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C +PACKET3_DISPATCH_DRAW = 0x8D +PACKET3_DISPATCH_DRAW_ACE = 0x8D +PACKET3_GET_LOD_STATS = 0x8E +PACKET3_DRAW_MULTI_PREAMBLE = 0x8F +PACKET3_FRAME_CONTROL = 0x90 +FRAME_TMZ = (1 << 0) +FRAME_CMD = lambda x: ((x) << 28) +PACKET3_INDEX_ATTRIBUTES_INDIRECT = 0x91 +PACKET3_WAIT_REG_MEM64 = 0x93 +PACKET3_COND_PREEMPT = 0x94 +PACKET3_HDP_FLUSH = 0x95 +PACKET3_COPY_DATA_RB = 0x96 +PACKET3_INVALIDATE_TLBS = 0x98 +PACKET3_INVALIDATE_TLBS_DST_SEL = lambda x: ((x) << 0) +PACKET3_INVALIDATE_TLBS_ALL_HUB = lambda x: ((x) << 4) +PACKET3_INVALIDATE_TLBS_PASID = lambda x: ((x) << 5) +PACKET3_AQL_PACKET = 0x99 +PACKET3_DMA_DATA_FILL_MULTI = 0x9A +PACKET3_SET_SH_REG_INDEX = 0x9B +PACKET3_DRAW_INDIRECT_COUNT_MULTI = 0x9C +PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI = 0x9D +PACKET3_DUMP_CONST_RAM_OFFSET = 0x9E +PACKET3_LOAD_CONTEXT_REG_INDEX = 0x9F +PACKET3_SET_RESOURCES = 0xA0 +PACKET3_SET_RESOURCES_VMID_MASK = lambda x: ((x) << 0) +PACKET3_SET_RESOURCES_UNMAP_LATENTY = lambda x: ((x) << 16) +PACKET3_SET_RESOURCES_QUEUE_TYPE = lambda x: ((x) << 29) +PACKET3_MAP_PROCESS = 0xA1 +PACKET3_MAP_QUEUES = 0xA2 +PACKET3_MAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) +PACKET3_MAP_QUEUES_VMID = lambda x: ((x) << 8) +PACKET3_MAP_QUEUES_QUEUE = lambda x: ((x) << 13) +PACKET3_MAP_QUEUES_PIPE = lambda x: ((x) << 16) +PACKET3_MAP_QUEUES_ME = lambda x: ((x) << 18) +PACKET3_MAP_QUEUES_QUEUE_TYPE = lambda x: ((x) << 21) +PACKET3_MAP_QUEUES_ALLOC_FORMAT = lambda x: ((x) << 24) +PACKET3_MAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) +PACKET3_MAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) +PACKET3_MAP_QUEUES_CHECK_DISABLE = lambda x: ((x) << 1) +PACKET3_MAP_QUEUES_DOORBELL_OFFSET = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES = 0xA3 +PACKET3_UNMAP_QUEUES_ACTION = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_QUEUE_SEL = lambda x: ((x) << 4) +PACKET3_UNMAP_QUEUES_ENGINE_SEL = lambda x: ((x) << 26) +PACKET3_UNMAP_QUEUES_NUM_QUEUES = lambda x: ((x) << 29) +PACKET3_UNMAP_QUEUES_PASID = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_RB_WPTR = lambda x: ((x) << 0) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2 = lambda x: ((x) << 2) +PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3 = lambda x: ((x) << 2) +PACKET3_QUERY_STATUS = 0xA4 +PACKET3_QUERY_STATUS_CONTEXT_ID = lambda x: ((x) << 0) +PACKET3_QUERY_STATUS_INTERRUPT_SEL = lambda x: ((x) << 28) +PACKET3_QUERY_STATUS_COMMAND = lambda x: ((x) << 30) +PACKET3_QUERY_STATUS_PASID = lambda x: ((x) << 0) +PACKET3_QUERY_STATUS_DOORBELL_OFFSET = lambda x: ((x) << 2) +PACKET3_QUERY_STATUS_ENG_SEL = lambda x: ((x) << 25) +PACKET3_RUN_LIST = 0xA5 +PACKET3_MAP_PROCESS_VM = 0xA6 +PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 +PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID = lambda x: ((x) << 0) +PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1 << 0) +regSDMA0_DEC_START = 0x0000 +regSDMA0_DEC_START_BASE_IDX = 0 +regSDMA0_F32_MISC_CNTL = 0x000b +regSDMA0_F32_MISC_CNTL_BASE_IDX = 0 +regSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f +regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 +regSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 +regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 +regSDMA0_POWER_CNTL = 0x001a +regSDMA0_POWER_CNTL_BASE_IDX = 0 +regSDMA0_CNTL = 0x001c +regSDMA0_CNTL_BASE_IDX = 0 +regSDMA0_CHICKEN_BITS = 0x001d +regSDMA0_CHICKEN_BITS_BASE_IDX = 0 +regSDMA0_GB_ADDR_CONFIG = 0x001e +regSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 +regSDMA0_GB_ADDR_CONFIG_READ = 0x001f +regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 +regSDMA0_RB_RPTR_FETCH = 0x0020 +regSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 +regSDMA0_RB_RPTR_FETCH_HI = 0x0021 +regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 +regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0022 +regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 +regSDMA0_IB_OFFSET_FETCH = 0x0023 +regSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 +regSDMA0_PROGRAM = 0x0024 +regSDMA0_PROGRAM_BASE_IDX = 0 +regSDMA0_STATUS_REG = 0x0025 +regSDMA0_STATUS_REG_BASE_IDX = 0 +regSDMA0_STATUS1_REG = 0x0026 +regSDMA0_STATUS1_REG_BASE_IDX = 0 +regSDMA0_CNTL1 = 0x0027 +regSDMA0_CNTL1_BASE_IDX = 0 +regSDMA0_HBM_PAGE_CONFIG = 0x0028 +regSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 +regSDMA0_UCODE_CHECKSUM = 0x0029 +regSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 +regSDMA0_FREEZE = 0x002b +regSDMA0_FREEZE_BASE_IDX = 0 +regSDMA0_PROCESS_QUANTUM0 = 0x002c +regSDMA0_PROCESS_QUANTUM0_BASE_IDX = 0 +regSDMA0_PROCESS_QUANTUM1 = 0x002d +regSDMA0_PROCESS_QUANTUM1_BASE_IDX = 0 +regSDMA0_WATCHDOG_CNTL = 0x002e +regSDMA0_WATCHDOG_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE_STATUS0 = 0x002f +regSDMA0_QUEUE_STATUS0_BASE_IDX = 0 +regSDMA0_EDC_CONFIG = 0x0032 +regSDMA0_EDC_CONFIG_BASE_IDX = 0 +regSDMA0_BA_THRESHOLD = 0x0033 +regSDMA0_BA_THRESHOLD_BASE_IDX = 0 +regSDMA0_ID = 0x0034 +regSDMA0_ID_BASE_IDX = 0 +regSDMA0_VERSION = 0x0035 +regSDMA0_VERSION_BASE_IDX = 0 +regSDMA0_EDC_COUNTER = 0x0036 +regSDMA0_EDC_COUNTER_BASE_IDX = 0 +regSDMA0_EDC_COUNTER_CLEAR = 0x0037 +regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 +regSDMA0_STATUS2_REG = 0x0038 +regSDMA0_STATUS2_REG_BASE_IDX = 0 +regSDMA0_ATOMIC_CNTL = 0x0039 +regSDMA0_ATOMIC_CNTL_BASE_IDX = 0 +regSDMA0_ATOMIC_PREOP_LO = 0x003a +regSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 +regSDMA0_ATOMIC_PREOP_HI = 0x003b +regSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 +regSDMA0_UTCL1_CNTL = 0x003c +regSDMA0_UTCL1_CNTL_BASE_IDX = 0 +regSDMA0_UTCL1_WATERMK = 0x003d +regSDMA0_UTCL1_WATERMK_BASE_IDX = 0 +regSDMA0_UTCL1_TIMEOUT = 0x003e +regSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 +regSDMA0_UTCL1_PAGE = 0x003f +regSDMA0_UTCL1_PAGE_BASE_IDX = 0 +regSDMA0_UTCL1_RD_STATUS = 0x0040 +regSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 +regSDMA0_UTCL1_WR_STATUS = 0x0041 +regSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 +regSDMA0_UTCL1_INV0 = 0x0042 +regSDMA0_UTCL1_INV0_BASE_IDX = 0 +regSDMA0_UTCL1_INV1 = 0x0043 +regSDMA0_UTCL1_INV1_BASE_IDX = 0 +regSDMA0_UTCL1_INV2 = 0x0044 +regSDMA0_UTCL1_INV2_BASE_IDX = 0 +regSDMA0_UTCL1_RD_XNACK0 = 0x0045 +regSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 +regSDMA0_UTCL1_RD_XNACK1 = 0x0046 +regSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 +regSDMA0_UTCL1_WR_XNACK0 = 0x0047 +regSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 +regSDMA0_UTCL1_WR_XNACK1 = 0x0048 +regSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 +regSDMA0_RELAX_ORDERING_LUT = 0x004a +regSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 +regSDMA0_CHICKEN_BITS_2 = 0x004b +regSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 +regSDMA0_STATUS3_REG = 0x004c +regSDMA0_STATUS3_REG_BASE_IDX = 0 +regSDMA0_PHYSICAL_ADDR_LO = 0x004d +regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 +regSDMA0_PHYSICAL_ADDR_HI = 0x004e +regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 +regSDMA0_GLOBAL_QUANTUM = 0x004f +regSDMA0_GLOBAL_QUANTUM_BASE_IDX = 0 +regSDMA0_ERROR_LOG = 0x0050 +regSDMA0_ERROR_LOG_BASE_IDX = 0 +regSDMA0_PUB_DUMMY_REG0 = 0x0051 +regSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 +regSDMA0_PUB_DUMMY_REG1 = 0x0052 +regSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 +regSDMA0_PUB_DUMMY_REG2 = 0x0053 +regSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 +regSDMA0_PUB_DUMMY_REG3 = 0x0054 +regSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 +regSDMA0_F32_COUNTER = 0x0055 +regSDMA0_F32_COUNTER_BASE_IDX = 0 +regSDMA0_CRD_CNTL = 0x005b +regSDMA0_CRD_CNTL_BASE_IDX = 0 +regSDMA0_RLC_CGCG_CTRL = 0x005c +regSDMA0_RLC_CGCG_CTRL_BASE_IDX = 0 +regSDMA0_AQL_STATUS = 0x005f +regSDMA0_AQL_STATUS_BASE_IDX = 0 +regSDMA0_EA_DBIT_ADDR_DATA = 0x0060 +regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 +regSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 +regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 +regSDMA0_TLBI_GCR_CNTL = 0x0062 +regSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 +regSDMA0_TILING_CONFIG = 0x0063 +regSDMA0_TILING_CONFIG_BASE_IDX = 0 +regSDMA0_INT_STATUS = 0x0070 +regSDMA0_INT_STATUS_BASE_IDX = 0 +regSDMA0_HOLE_ADDR_LO = 0x0072 +regSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 +regSDMA0_HOLE_ADDR_HI = 0x0073 +regSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 +regSDMA0_CLOCK_GATING_STATUS = 0x0075 +regSDMA0_CLOCK_GATING_STATUS_BASE_IDX = 0 +regSDMA0_STATUS4_REG = 0x0076 +regSDMA0_STATUS4_REG_BASE_IDX = 0 +regSDMA0_SCRATCH_RAM_DATA = 0x0077 +regSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 +regSDMA0_SCRATCH_RAM_ADDR = 0x0078 +regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 +regSDMA0_TIMESTAMP_CNTL = 0x0079 +regSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 +regSDMA0_STATUS5_REG = 0x007a +regSDMA0_STATUS5_REG_BASE_IDX = 0 +regSDMA0_QUEUE_RESET_REQ = 0x007b +regSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 +regSDMA0_STATUS6_REG = 0x007c +regSDMA0_STATUS6_REG_BASE_IDX = 0 +regSDMA0_UCODE1_CHECKSUM = 0x007d +regSDMA0_UCODE1_CHECKSUM_BASE_IDX = 0 +regSDMA0_CE_CTRL = 0x007e +regSDMA0_CE_CTRL_BASE_IDX = 0 +regSDMA0_FED_STATUS = 0x007f +regSDMA0_FED_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_CNTL = 0x0080 +regSDMA0_QUEUE0_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_BASE = 0x0081 +regSDMA0_QUEUE0_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_BASE_HI = 0x0082 +regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_RPTR = 0x0083 +regSDMA0_QUEUE0_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_RPTR_HI = 0x0084 +regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_WPTR = 0x0085 +regSDMA0_QUEUE0_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_WPTR_HI = 0x0086 +regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_RPTR_ADDR_HI = 0x0088 +regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_RPTR_ADDR_LO = 0x0089 +regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_CNTL = 0x008a +regSDMA0_QUEUE0_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_RPTR = 0x008b +regSDMA0_QUEUE0_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_OFFSET = 0x008c +regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_BASE_LO = 0x008d +regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_BASE_HI = 0x008e +regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_SIZE = 0x008f +regSDMA0_QUEUE0_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE0_SKIP_CNTL = 0x0090 +regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE0_CONTEXT_STATUS = 0x0091 +regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE0_DOORBELL = 0x0092 +regSDMA0_QUEUE0_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE0_DOORBELL_LOG = 0x00a9 +regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE0_DOORBELL_OFFSET = 0x00ab +regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE0_CSA_ADDR_LO = 0x00ac +regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE0_CSA_ADDR_HI = 0x00ad +regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_SCHEDULE_CNTL = 0x00ae +regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE0_IB_SUB_REMAIN = 0x00af +regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE0_PREEMPT = 0x00b0 +regSDMA0_QUEUE0_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE0_DUMMY_REG = 0x00b1 +regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x00b2 +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x00b3 +regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_AQL_CNTL = 0x00b4 +regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE0_MINOR_PTR_UPDATE = 0x00b5 +regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE0_RB_PREEMPT = 0x00b6 +regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA0 = 0x00c0 +regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA1 = 0x00c1 +regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA2 = 0x00c2 +regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA3 = 0x00c3 +regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA4 = 0x00c4 +regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA5 = 0x00c5 +regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA6 = 0x00c6 +regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA7 = 0x00c7 +regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA8 = 0x00c8 +regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA9 = 0x00c9 +regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_DATA10 = 0x00ca +regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE0_MIDCMD_CNTL = 0x00cb +regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_CNTL = 0x00d8 +regSDMA0_QUEUE1_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_BASE = 0x00d9 +regSDMA0_QUEUE1_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_BASE_HI = 0x00da +regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_RPTR = 0x00db +regSDMA0_QUEUE1_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_RPTR_HI = 0x00dc +regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_WPTR = 0x00dd +regSDMA0_QUEUE1_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_WPTR_HI = 0x00de +regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_RPTR_ADDR_HI = 0x00e0 +regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_RPTR_ADDR_LO = 0x00e1 +regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_CNTL = 0x00e2 +regSDMA0_QUEUE1_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_RPTR = 0x00e3 +regSDMA0_QUEUE1_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_OFFSET = 0x00e4 +regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_BASE_LO = 0x00e5 +regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_BASE_HI = 0x00e6 +regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_SIZE = 0x00e7 +regSDMA0_QUEUE1_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE1_SKIP_CNTL = 0x00e8 +regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE1_CONTEXT_STATUS = 0x00e9 +regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE1_DOORBELL = 0x00ea +regSDMA0_QUEUE1_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE1_DOORBELL_LOG = 0x0101 +regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE1_DOORBELL_OFFSET = 0x0103 +regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE1_CSA_ADDR_LO = 0x0104 +regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE1_CSA_ADDR_HI = 0x0105 +regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_SCHEDULE_CNTL = 0x0106 +regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE1_IB_SUB_REMAIN = 0x0107 +regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE1_PREEMPT = 0x0108 +regSDMA0_QUEUE1_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE1_DUMMY_REG = 0x0109 +regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x010a +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x010b +regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_AQL_CNTL = 0x010c +regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE1_MINOR_PTR_UPDATE = 0x010d +regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE1_RB_PREEMPT = 0x010e +regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA0 = 0x0118 +regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA1 = 0x0119 +regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA2 = 0x011a +regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA3 = 0x011b +regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA4 = 0x011c +regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA5 = 0x011d +regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA6 = 0x011e +regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA7 = 0x011f +regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA8 = 0x0120 +regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA9 = 0x0121 +regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_DATA10 = 0x0122 +regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE1_MIDCMD_CNTL = 0x0123 +regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_CNTL = 0x0130 +regSDMA0_QUEUE2_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_BASE = 0x0131 +regSDMA0_QUEUE2_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_BASE_HI = 0x0132 +regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_RPTR = 0x0133 +regSDMA0_QUEUE2_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_RPTR_HI = 0x0134 +regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_WPTR = 0x0135 +regSDMA0_QUEUE2_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_WPTR_HI = 0x0136 +regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_RPTR_ADDR_HI = 0x0138 +regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_RPTR_ADDR_LO = 0x0139 +regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_CNTL = 0x013a +regSDMA0_QUEUE2_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_RPTR = 0x013b +regSDMA0_QUEUE2_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_OFFSET = 0x013c +regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_BASE_LO = 0x013d +regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_BASE_HI = 0x013e +regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_SIZE = 0x013f +regSDMA0_QUEUE2_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE2_SKIP_CNTL = 0x0140 +regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE2_CONTEXT_STATUS = 0x0141 +regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE2_DOORBELL = 0x0142 +regSDMA0_QUEUE2_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE2_DOORBELL_LOG = 0x0159 +regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE2_DOORBELL_OFFSET = 0x015b +regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE2_CSA_ADDR_LO = 0x015c +regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE2_CSA_ADDR_HI = 0x015d +regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_SCHEDULE_CNTL = 0x015e +regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE2_IB_SUB_REMAIN = 0x015f +regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE2_PREEMPT = 0x0160 +regSDMA0_QUEUE2_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE2_DUMMY_REG = 0x0161 +regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0162 +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0163 +regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_AQL_CNTL = 0x0164 +regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE2_MINOR_PTR_UPDATE = 0x0165 +regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE2_RB_PREEMPT = 0x0166 +regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA0 = 0x0170 +regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA1 = 0x0171 +regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA2 = 0x0172 +regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA3 = 0x0173 +regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA4 = 0x0174 +regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA5 = 0x0175 +regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA6 = 0x0176 +regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA7 = 0x0177 +regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA8 = 0x0178 +regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA9 = 0x0179 +regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_DATA10 = 0x017a +regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE2_MIDCMD_CNTL = 0x017b +regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_CNTL = 0x0188 +regSDMA0_QUEUE3_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_BASE = 0x0189 +regSDMA0_QUEUE3_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_BASE_HI = 0x018a +regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_RPTR = 0x018b +regSDMA0_QUEUE3_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_RPTR_HI = 0x018c +regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_WPTR = 0x018d +regSDMA0_QUEUE3_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_WPTR_HI = 0x018e +regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_RPTR_ADDR_HI = 0x0190 +regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_RPTR_ADDR_LO = 0x0191 +regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_CNTL = 0x0192 +regSDMA0_QUEUE3_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_RPTR = 0x0193 +regSDMA0_QUEUE3_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_OFFSET = 0x0194 +regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_BASE_LO = 0x0195 +regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_BASE_HI = 0x0196 +regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_SIZE = 0x0197 +regSDMA0_QUEUE3_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE3_SKIP_CNTL = 0x0198 +regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE3_CONTEXT_STATUS = 0x0199 +regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE3_DOORBELL = 0x019a +regSDMA0_QUEUE3_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE3_DOORBELL_LOG = 0x01b1 +regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE3_DOORBELL_OFFSET = 0x01b3 +regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE3_CSA_ADDR_LO = 0x01b4 +regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE3_CSA_ADDR_HI = 0x01b5 +regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_SCHEDULE_CNTL = 0x01b6 +regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE3_IB_SUB_REMAIN = 0x01b7 +regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE3_PREEMPT = 0x01b8 +regSDMA0_QUEUE3_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE3_DUMMY_REG = 0x01b9 +regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x01ba +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x01bb +regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_AQL_CNTL = 0x01bc +regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE3_MINOR_PTR_UPDATE = 0x01bd +regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE3_RB_PREEMPT = 0x01be +regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA0 = 0x01c8 +regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA1 = 0x01c9 +regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA2 = 0x01ca +regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA3 = 0x01cb +regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA4 = 0x01cc +regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA5 = 0x01cd +regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA6 = 0x01ce +regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA7 = 0x01cf +regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA8 = 0x01d0 +regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA9 = 0x01d1 +regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_DATA10 = 0x01d2 +regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE3_MIDCMD_CNTL = 0x01d3 +regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_CNTL = 0x01e0 +regSDMA0_QUEUE4_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_BASE = 0x01e1 +regSDMA0_QUEUE4_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_BASE_HI = 0x01e2 +regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_RPTR = 0x01e3 +regSDMA0_QUEUE4_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_RPTR_HI = 0x01e4 +regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_WPTR = 0x01e5 +regSDMA0_QUEUE4_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_WPTR_HI = 0x01e6 +regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_RPTR_ADDR_HI = 0x01e8 +regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_RPTR_ADDR_LO = 0x01e9 +regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_CNTL = 0x01ea +regSDMA0_QUEUE4_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_RPTR = 0x01eb +regSDMA0_QUEUE4_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_OFFSET = 0x01ec +regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_BASE_LO = 0x01ed +regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_BASE_HI = 0x01ee +regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_SIZE = 0x01ef +regSDMA0_QUEUE4_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE4_SKIP_CNTL = 0x01f0 +regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE4_CONTEXT_STATUS = 0x01f1 +regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE4_DOORBELL = 0x01f2 +regSDMA0_QUEUE4_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE4_DOORBELL_LOG = 0x0209 +regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE4_DOORBELL_OFFSET = 0x020b +regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE4_CSA_ADDR_LO = 0x020c +regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE4_CSA_ADDR_HI = 0x020d +regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_SCHEDULE_CNTL = 0x020e +regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE4_IB_SUB_REMAIN = 0x020f +regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE4_PREEMPT = 0x0210 +regSDMA0_QUEUE4_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE4_DUMMY_REG = 0x0211 +regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0212 +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0213 +regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_AQL_CNTL = 0x0214 +regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE4_MINOR_PTR_UPDATE = 0x0215 +regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE4_RB_PREEMPT = 0x0216 +regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA0 = 0x0220 +regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA1 = 0x0221 +regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA2 = 0x0222 +regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA3 = 0x0223 +regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA4 = 0x0224 +regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA5 = 0x0225 +regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA6 = 0x0226 +regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA7 = 0x0227 +regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA8 = 0x0228 +regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA9 = 0x0229 +regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_DATA10 = 0x022a +regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE4_MIDCMD_CNTL = 0x022b +regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_CNTL = 0x0238 +regSDMA0_QUEUE5_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_BASE = 0x0239 +regSDMA0_QUEUE5_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_BASE_HI = 0x023a +regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_RPTR = 0x023b +regSDMA0_QUEUE5_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_RPTR_HI = 0x023c +regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_WPTR = 0x023d +regSDMA0_QUEUE5_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_WPTR_HI = 0x023e +regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_RPTR_ADDR_HI = 0x0240 +regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_RPTR_ADDR_LO = 0x0241 +regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_CNTL = 0x0242 +regSDMA0_QUEUE5_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_RPTR = 0x0243 +regSDMA0_QUEUE5_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_OFFSET = 0x0244 +regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_BASE_LO = 0x0245 +regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_BASE_HI = 0x0246 +regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_SIZE = 0x0247 +regSDMA0_QUEUE5_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE5_SKIP_CNTL = 0x0248 +regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE5_CONTEXT_STATUS = 0x0249 +regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE5_DOORBELL = 0x024a +regSDMA0_QUEUE5_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE5_DOORBELL_LOG = 0x0261 +regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE5_DOORBELL_OFFSET = 0x0263 +regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE5_CSA_ADDR_LO = 0x0264 +regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE5_CSA_ADDR_HI = 0x0265 +regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_SCHEDULE_CNTL = 0x0266 +regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE5_IB_SUB_REMAIN = 0x0267 +regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE5_PREEMPT = 0x0268 +regSDMA0_QUEUE5_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE5_DUMMY_REG = 0x0269 +regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x026a +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x026b +regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_AQL_CNTL = 0x026c +regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE5_MINOR_PTR_UPDATE = 0x026d +regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE5_RB_PREEMPT = 0x026e +regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA0 = 0x0278 +regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA1 = 0x0279 +regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA2 = 0x027a +regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA3 = 0x027b +regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA4 = 0x027c +regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA5 = 0x027d +regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA6 = 0x027e +regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA7 = 0x027f +regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA8 = 0x0280 +regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA9 = 0x0281 +regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_DATA10 = 0x0282 +regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE5_MIDCMD_CNTL = 0x0283 +regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_CNTL = 0x0290 +regSDMA0_QUEUE6_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_BASE = 0x0291 +regSDMA0_QUEUE6_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_BASE_HI = 0x0292 +regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_RPTR = 0x0293 +regSDMA0_QUEUE6_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_RPTR_HI = 0x0294 +regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_WPTR = 0x0295 +regSDMA0_QUEUE6_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_WPTR_HI = 0x0296 +regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_RPTR_ADDR_HI = 0x0298 +regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_RPTR_ADDR_LO = 0x0299 +regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_CNTL = 0x029a +regSDMA0_QUEUE6_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_RPTR = 0x029b +regSDMA0_QUEUE6_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_OFFSET = 0x029c +regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_BASE_LO = 0x029d +regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_BASE_HI = 0x029e +regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_SIZE = 0x029f +regSDMA0_QUEUE6_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE6_SKIP_CNTL = 0x02a0 +regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE6_CONTEXT_STATUS = 0x02a1 +regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE6_DOORBELL = 0x02a2 +regSDMA0_QUEUE6_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE6_DOORBELL_LOG = 0x02b9 +regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE6_DOORBELL_OFFSET = 0x02bb +regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE6_CSA_ADDR_LO = 0x02bc +regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE6_CSA_ADDR_HI = 0x02bd +regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_SCHEDULE_CNTL = 0x02be +regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE6_IB_SUB_REMAIN = 0x02bf +regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE6_PREEMPT = 0x02c0 +regSDMA0_QUEUE6_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE6_DUMMY_REG = 0x02c1 +regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x02c2 +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x02c3 +regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_AQL_CNTL = 0x02c4 +regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE6_MINOR_PTR_UPDATE = 0x02c5 +regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE6_RB_PREEMPT = 0x02c6 +regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA0 = 0x02d0 +regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA1 = 0x02d1 +regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA2 = 0x02d2 +regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA3 = 0x02d3 +regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA4 = 0x02d4 +regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA5 = 0x02d5 +regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA6 = 0x02d6 +regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA7 = 0x02d7 +regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA8 = 0x02d8 +regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA9 = 0x02d9 +regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_DATA10 = 0x02da +regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE6_MIDCMD_CNTL = 0x02db +regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_CNTL = 0x02e8 +regSDMA0_QUEUE7_RB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_BASE = 0x02e9 +regSDMA0_QUEUE7_RB_BASE_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_BASE_HI = 0x02ea +regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_RPTR = 0x02eb +regSDMA0_QUEUE7_RB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_RPTR_HI = 0x02ec +regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_WPTR = 0x02ed +regSDMA0_QUEUE7_RB_WPTR_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_WPTR_HI = 0x02ee +regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_RPTR_ADDR_HI = 0x02f0 +regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_RPTR_ADDR_LO = 0x02f1 +regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_CNTL = 0x02f2 +regSDMA0_QUEUE7_IB_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_RPTR = 0x02f3 +regSDMA0_QUEUE7_IB_RPTR_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_OFFSET = 0x02f4 +regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_BASE_LO = 0x02f5 +regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_BASE_HI = 0x02f6 +regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_SIZE = 0x02f7 +regSDMA0_QUEUE7_IB_SIZE_BASE_IDX = 0 +regSDMA0_QUEUE7_SKIP_CNTL = 0x02f8 +regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE7_CONTEXT_STATUS = 0x02f9 +regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA0_QUEUE7_DOORBELL = 0x02fa +regSDMA0_QUEUE7_DOORBELL_BASE_IDX = 0 +regSDMA0_QUEUE7_DOORBELL_LOG = 0x0311 +regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 +regSDMA0_QUEUE7_DOORBELL_OFFSET = 0x0313 +regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA0_QUEUE7_CSA_ADDR_LO = 0x0314 +regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE7_CSA_ADDR_HI = 0x0315 +regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_SCHEDULE_CNTL = 0x0316 +regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE7_IB_SUB_REMAIN = 0x0317 +regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA0_QUEUE7_PREEMPT = 0x0318 +regSDMA0_QUEUE7_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE7_DUMMY_REG = 0x0319 +regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x031a +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x031b +regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_AQL_CNTL = 0x031c +regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA0_QUEUE7_MINOR_PTR_UPDATE = 0x031d +regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA0_QUEUE7_RB_PREEMPT = 0x031e +regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA0 = 0x0328 +regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA1 = 0x0329 +regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA2 = 0x032a +regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA3 = 0x032b +regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA4 = 0x032c +regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA5 = 0x032d +regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA6 = 0x032e +regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA7 = 0x032f +regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA8 = 0x0330 +regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA9 = 0x0331 +regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_DATA10 = 0x0332 +regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA0_QUEUE7_MIDCMD_CNTL = 0x0333 +regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_DEC_START = 0x0600 +regSDMA1_DEC_START_BASE_IDX = 0 +regSDMA1_F32_MISC_CNTL = 0x060b +regSDMA1_F32_MISC_CNTL_BASE_IDX = 0 +regSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f +regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 +regSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 +regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 +regSDMA1_POWER_CNTL = 0x061a +regSDMA1_POWER_CNTL_BASE_IDX = 0 +regSDMA1_CNTL = 0x061c +regSDMA1_CNTL_BASE_IDX = 0 +regSDMA1_CHICKEN_BITS = 0x061d +regSDMA1_CHICKEN_BITS_BASE_IDX = 0 +regSDMA1_GB_ADDR_CONFIG = 0x061e +regSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 +regSDMA1_GB_ADDR_CONFIG_READ = 0x061f +regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 +regSDMA1_RB_RPTR_FETCH = 0x0620 +regSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 +regSDMA1_RB_RPTR_FETCH_HI = 0x0621 +regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 +regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0622 +regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 +regSDMA1_IB_OFFSET_FETCH = 0x0623 +regSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 +regSDMA1_PROGRAM = 0x0624 +regSDMA1_PROGRAM_BASE_IDX = 0 +regSDMA1_STATUS_REG = 0x0625 +regSDMA1_STATUS_REG_BASE_IDX = 0 +regSDMA1_STATUS1_REG = 0x0626 +regSDMA1_STATUS1_REG_BASE_IDX = 0 +regSDMA1_CNTL1 = 0x0627 +regSDMA1_CNTL1_BASE_IDX = 0 +regSDMA1_HBM_PAGE_CONFIG = 0x0628 +regSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 +regSDMA1_UCODE_CHECKSUM = 0x0629 +regSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 +regSDMA1_FREEZE = 0x062b +regSDMA1_FREEZE_BASE_IDX = 0 +regSDMA1_PROCESS_QUANTUM0 = 0x062c +regSDMA1_PROCESS_QUANTUM0_BASE_IDX = 0 +regSDMA1_PROCESS_QUANTUM1 = 0x062d +regSDMA1_PROCESS_QUANTUM1_BASE_IDX = 0 +regSDMA1_WATCHDOG_CNTL = 0x062e +regSDMA1_WATCHDOG_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE_STATUS0 = 0x062f +regSDMA1_QUEUE_STATUS0_BASE_IDX = 0 +regSDMA1_EDC_CONFIG = 0x0632 +regSDMA1_EDC_CONFIG_BASE_IDX = 0 +regSDMA1_BA_THRESHOLD = 0x0633 +regSDMA1_BA_THRESHOLD_BASE_IDX = 0 +regSDMA1_ID = 0x0634 +regSDMA1_ID_BASE_IDX = 0 +regSDMA1_VERSION = 0x0635 +regSDMA1_VERSION_BASE_IDX = 0 +regSDMA1_EDC_COUNTER = 0x0636 +regSDMA1_EDC_COUNTER_BASE_IDX = 0 +regSDMA1_EDC_COUNTER_CLEAR = 0x0637 +regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 +regSDMA1_STATUS2_REG = 0x0638 +regSDMA1_STATUS2_REG_BASE_IDX = 0 +regSDMA1_ATOMIC_CNTL = 0x0639 +regSDMA1_ATOMIC_CNTL_BASE_IDX = 0 +regSDMA1_ATOMIC_PREOP_LO = 0x063a +regSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 +regSDMA1_ATOMIC_PREOP_HI = 0x063b +regSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 +regSDMA1_UTCL1_CNTL = 0x063c +regSDMA1_UTCL1_CNTL_BASE_IDX = 0 +regSDMA1_UTCL1_WATERMK = 0x063d +regSDMA1_UTCL1_WATERMK_BASE_IDX = 0 +regSDMA1_UTCL1_TIMEOUT = 0x063e +regSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 +regSDMA1_UTCL1_PAGE = 0x063f +regSDMA1_UTCL1_PAGE_BASE_IDX = 0 +regSDMA1_UTCL1_RD_STATUS = 0x0640 +regSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 +regSDMA1_UTCL1_WR_STATUS = 0x0641 +regSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 +regSDMA1_UTCL1_INV0 = 0x0642 +regSDMA1_UTCL1_INV0_BASE_IDX = 0 +regSDMA1_UTCL1_INV1 = 0x0643 +regSDMA1_UTCL1_INV1_BASE_IDX = 0 +regSDMA1_UTCL1_INV2 = 0x0644 +regSDMA1_UTCL1_INV2_BASE_IDX = 0 +regSDMA1_UTCL1_RD_XNACK0 = 0x0645 +regSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 +regSDMA1_UTCL1_RD_XNACK1 = 0x0646 +regSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 +regSDMA1_UTCL1_WR_XNACK0 = 0x0647 +regSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 +regSDMA1_UTCL1_WR_XNACK1 = 0x0648 +regSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 +regSDMA1_RELAX_ORDERING_LUT = 0x064a +regSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 +regSDMA1_CHICKEN_BITS_2 = 0x064b +regSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 +regSDMA1_STATUS3_REG = 0x064c +regSDMA1_STATUS3_REG_BASE_IDX = 0 +regSDMA1_PHYSICAL_ADDR_LO = 0x064d +regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 +regSDMA1_PHYSICAL_ADDR_HI = 0x064e +regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 +regSDMA1_GLOBAL_QUANTUM = 0x064f +regSDMA1_GLOBAL_QUANTUM_BASE_IDX = 0 +regSDMA1_ERROR_LOG = 0x0650 +regSDMA1_ERROR_LOG_BASE_IDX = 0 +regSDMA1_PUB_DUMMY_REG0 = 0x0651 +regSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 +regSDMA1_PUB_DUMMY_REG1 = 0x0652 +regSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 +regSDMA1_PUB_DUMMY_REG2 = 0x0653 +regSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 +regSDMA1_PUB_DUMMY_REG3 = 0x0654 +regSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 +regSDMA1_F32_COUNTER = 0x0655 +regSDMA1_F32_COUNTER_BASE_IDX = 0 +regSDMA1_CRD_CNTL = 0x065b +regSDMA1_CRD_CNTL_BASE_IDX = 0 +regSDMA1_RLC_CGCG_CTRL = 0x065c +regSDMA1_RLC_CGCG_CTRL_BASE_IDX = 0 +regSDMA1_AQL_STATUS = 0x065f +regSDMA1_AQL_STATUS_BASE_IDX = 0 +regSDMA1_EA_DBIT_ADDR_DATA = 0x0660 +regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 +regSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 +regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 +regSDMA1_TLBI_GCR_CNTL = 0x0662 +regSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 +regSDMA1_TILING_CONFIG = 0x0663 +regSDMA1_TILING_CONFIG_BASE_IDX = 0 +regSDMA1_INT_STATUS = 0x0670 +regSDMA1_INT_STATUS_BASE_IDX = 0 +regSDMA1_HOLE_ADDR_LO = 0x0672 +regSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 +regSDMA1_HOLE_ADDR_HI = 0x0673 +regSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 +regSDMA1_CLOCK_GATING_STATUS = 0x0675 +regSDMA1_CLOCK_GATING_STATUS_BASE_IDX = 0 +regSDMA1_STATUS4_REG = 0x0676 +regSDMA1_STATUS4_REG_BASE_IDX = 0 +regSDMA1_SCRATCH_RAM_DATA = 0x0677 +regSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 +regSDMA1_SCRATCH_RAM_ADDR = 0x0678 +regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 +regSDMA1_TIMESTAMP_CNTL = 0x0679 +regSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 +regSDMA1_STATUS5_REG = 0x067a +regSDMA1_STATUS5_REG_BASE_IDX = 0 +regSDMA1_QUEUE_RESET_REQ = 0x067b +regSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 +regSDMA1_STATUS6_REG = 0x067c +regSDMA1_STATUS6_REG_BASE_IDX = 0 +regSDMA1_UCODE1_CHECKSUM = 0x067d +regSDMA1_UCODE1_CHECKSUM_BASE_IDX = 0 +regSDMA1_CE_CTRL = 0x067e +regSDMA1_CE_CTRL_BASE_IDX = 0 +regSDMA1_FED_STATUS = 0x067f +regSDMA1_FED_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_CNTL = 0x0680 +regSDMA1_QUEUE0_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_BASE = 0x0681 +regSDMA1_QUEUE0_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_BASE_HI = 0x0682 +regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_RPTR = 0x0683 +regSDMA1_QUEUE0_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_RPTR_HI = 0x0684 +regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_WPTR = 0x0685 +regSDMA1_QUEUE0_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_WPTR_HI = 0x0686 +regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_RPTR_ADDR_HI = 0x0688 +regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_RPTR_ADDR_LO = 0x0689 +regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_CNTL = 0x068a +regSDMA1_QUEUE0_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_RPTR = 0x068b +regSDMA1_QUEUE0_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_OFFSET = 0x068c +regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_BASE_LO = 0x068d +regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_BASE_HI = 0x068e +regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_SIZE = 0x068f +regSDMA1_QUEUE0_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE0_SKIP_CNTL = 0x0690 +regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE0_CONTEXT_STATUS = 0x0691 +regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE0_DOORBELL = 0x0692 +regSDMA1_QUEUE0_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE0_DOORBELL_LOG = 0x06a9 +regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE0_DOORBELL_OFFSET = 0x06ab +regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE0_CSA_ADDR_LO = 0x06ac +regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE0_CSA_ADDR_HI = 0x06ad +regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_SCHEDULE_CNTL = 0x06ae +regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE0_IB_SUB_REMAIN = 0x06af +regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE0_PREEMPT = 0x06b0 +regSDMA1_QUEUE0_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE0_DUMMY_REG = 0x06b1 +regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI = 0x06b2 +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO = 0x06b3 +regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_AQL_CNTL = 0x06b4 +regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE0_MINOR_PTR_UPDATE = 0x06b5 +regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE0_RB_PREEMPT = 0x06b6 +regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA0 = 0x06c0 +regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA1 = 0x06c1 +regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA2 = 0x06c2 +regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA3 = 0x06c3 +regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA4 = 0x06c4 +regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA5 = 0x06c5 +regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA6 = 0x06c6 +regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA7 = 0x06c7 +regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA8 = 0x06c8 +regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA9 = 0x06c9 +regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_DATA10 = 0x06ca +regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE0_MIDCMD_CNTL = 0x06cb +regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_CNTL = 0x06d8 +regSDMA1_QUEUE1_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_BASE = 0x06d9 +regSDMA1_QUEUE1_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_BASE_HI = 0x06da +regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_RPTR = 0x06db +regSDMA1_QUEUE1_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_RPTR_HI = 0x06dc +regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_WPTR = 0x06dd +regSDMA1_QUEUE1_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_WPTR_HI = 0x06de +regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_RPTR_ADDR_HI = 0x06e0 +regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_RPTR_ADDR_LO = 0x06e1 +regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_CNTL = 0x06e2 +regSDMA1_QUEUE1_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_RPTR = 0x06e3 +regSDMA1_QUEUE1_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_OFFSET = 0x06e4 +regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_BASE_LO = 0x06e5 +regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_BASE_HI = 0x06e6 +regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_SIZE = 0x06e7 +regSDMA1_QUEUE1_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE1_SKIP_CNTL = 0x06e8 +regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE1_CONTEXT_STATUS = 0x06e9 +regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE1_DOORBELL = 0x06ea +regSDMA1_QUEUE1_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE1_DOORBELL_LOG = 0x0701 +regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE1_DOORBELL_OFFSET = 0x0703 +regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE1_CSA_ADDR_LO = 0x0704 +regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE1_CSA_ADDR_HI = 0x0705 +regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_SCHEDULE_CNTL = 0x0706 +regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE1_IB_SUB_REMAIN = 0x0707 +regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE1_PREEMPT = 0x0708 +regSDMA1_QUEUE1_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE1_DUMMY_REG = 0x0709 +regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI = 0x070a +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO = 0x070b +regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_AQL_CNTL = 0x070c +regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE1_MINOR_PTR_UPDATE = 0x070d +regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE1_RB_PREEMPT = 0x070e +regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA0 = 0x0718 +regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA1 = 0x0719 +regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA2 = 0x071a +regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA3 = 0x071b +regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA4 = 0x071c +regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA5 = 0x071d +regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA6 = 0x071e +regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA7 = 0x071f +regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA8 = 0x0720 +regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA9 = 0x0721 +regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_DATA10 = 0x0722 +regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE1_MIDCMD_CNTL = 0x0723 +regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_CNTL = 0x0730 +regSDMA1_QUEUE2_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_BASE = 0x0731 +regSDMA1_QUEUE2_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_BASE_HI = 0x0732 +regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_RPTR = 0x0733 +regSDMA1_QUEUE2_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_RPTR_HI = 0x0734 +regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_WPTR = 0x0735 +regSDMA1_QUEUE2_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_WPTR_HI = 0x0736 +regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_RPTR_ADDR_HI = 0x0738 +regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_RPTR_ADDR_LO = 0x0739 +regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_CNTL = 0x073a +regSDMA1_QUEUE2_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_RPTR = 0x073b +regSDMA1_QUEUE2_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_OFFSET = 0x073c +regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_BASE_LO = 0x073d +regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_BASE_HI = 0x073e +regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_SIZE = 0x073f +regSDMA1_QUEUE2_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE2_SKIP_CNTL = 0x0740 +regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE2_CONTEXT_STATUS = 0x0741 +regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE2_DOORBELL = 0x0742 +regSDMA1_QUEUE2_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE2_DOORBELL_LOG = 0x0759 +regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE2_DOORBELL_OFFSET = 0x075b +regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE2_CSA_ADDR_LO = 0x075c +regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE2_CSA_ADDR_HI = 0x075d +regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_SCHEDULE_CNTL = 0x075e +regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE2_IB_SUB_REMAIN = 0x075f +regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE2_PREEMPT = 0x0760 +regSDMA1_QUEUE2_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE2_DUMMY_REG = 0x0761 +regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI = 0x0762 +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO = 0x0763 +regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_AQL_CNTL = 0x0764 +regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE2_MINOR_PTR_UPDATE = 0x0765 +regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE2_RB_PREEMPT = 0x0766 +regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA0 = 0x0770 +regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA1 = 0x0771 +regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA2 = 0x0772 +regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA3 = 0x0773 +regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA4 = 0x0774 +regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA5 = 0x0775 +regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA6 = 0x0776 +regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA7 = 0x0777 +regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA8 = 0x0778 +regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA9 = 0x0779 +regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_DATA10 = 0x077a +regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE2_MIDCMD_CNTL = 0x077b +regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_CNTL = 0x0788 +regSDMA1_QUEUE3_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_BASE = 0x0789 +regSDMA1_QUEUE3_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_BASE_HI = 0x078a +regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_RPTR = 0x078b +regSDMA1_QUEUE3_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_RPTR_HI = 0x078c +regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_WPTR = 0x078d +regSDMA1_QUEUE3_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_WPTR_HI = 0x078e +regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_RPTR_ADDR_HI = 0x0790 +regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_RPTR_ADDR_LO = 0x0791 +regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_CNTL = 0x0792 +regSDMA1_QUEUE3_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_RPTR = 0x0793 +regSDMA1_QUEUE3_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_OFFSET = 0x0794 +regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_BASE_LO = 0x0795 +regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_BASE_HI = 0x0796 +regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_SIZE = 0x0797 +regSDMA1_QUEUE3_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE3_SKIP_CNTL = 0x0798 +regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE3_CONTEXT_STATUS = 0x0799 +regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE3_DOORBELL = 0x079a +regSDMA1_QUEUE3_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE3_DOORBELL_LOG = 0x07b1 +regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE3_DOORBELL_OFFSET = 0x07b3 +regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE3_CSA_ADDR_LO = 0x07b4 +regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE3_CSA_ADDR_HI = 0x07b5 +regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_SCHEDULE_CNTL = 0x07b6 +regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE3_IB_SUB_REMAIN = 0x07b7 +regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE3_PREEMPT = 0x07b8 +regSDMA1_QUEUE3_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE3_DUMMY_REG = 0x07b9 +regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI = 0x07ba +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO = 0x07bb +regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_AQL_CNTL = 0x07bc +regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE3_MINOR_PTR_UPDATE = 0x07bd +regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE3_RB_PREEMPT = 0x07be +regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA0 = 0x07c8 +regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA1 = 0x07c9 +regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA2 = 0x07ca +regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA3 = 0x07cb +regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA4 = 0x07cc +regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA5 = 0x07cd +regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA6 = 0x07ce +regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA7 = 0x07cf +regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA8 = 0x07d0 +regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA9 = 0x07d1 +regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_DATA10 = 0x07d2 +regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE3_MIDCMD_CNTL = 0x07d3 +regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_CNTL = 0x07e0 +regSDMA1_QUEUE4_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_BASE = 0x07e1 +regSDMA1_QUEUE4_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_BASE_HI = 0x07e2 +regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_RPTR = 0x07e3 +regSDMA1_QUEUE4_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_RPTR_HI = 0x07e4 +regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_WPTR = 0x07e5 +regSDMA1_QUEUE4_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_WPTR_HI = 0x07e6 +regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_RPTR_ADDR_HI = 0x07e8 +regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_RPTR_ADDR_LO = 0x07e9 +regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_CNTL = 0x07ea +regSDMA1_QUEUE4_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_RPTR = 0x07eb +regSDMA1_QUEUE4_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_OFFSET = 0x07ec +regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_BASE_LO = 0x07ed +regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_BASE_HI = 0x07ee +regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_SIZE = 0x07ef +regSDMA1_QUEUE4_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE4_SKIP_CNTL = 0x07f0 +regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE4_CONTEXT_STATUS = 0x07f1 +regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE4_DOORBELL = 0x07f2 +regSDMA1_QUEUE4_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE4_DOORBELL_LOG = 0x0809 +regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE4_DOORBELL_OFFSET = 0x080b +regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE4_CSA_ADDR_LO = 0x080c +regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE4_CSA_ADDR_HI = 0x080d +regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_SCHEDULE_CNTL = 0x080e +regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE4_IB_SUB_REMAIN = 0x080f +regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE4_PREEMPT = 0x0810 +regSDMA1_QUEUE4_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE4_DUMMY_REG = 0x0811 +regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI = 0x0812 +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO = 0x0813 +regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_AQL_CNTL = 0x0814 +regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE4_MINOR_PTR_UPDATE = 0x0815 +regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE4_RB_PREEMPT = 0x0816 +regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA0 = 0x0820 +regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA1 = 0x0821 +regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA2 = 0x0822 +regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA3 = 0x0823 +regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA4 = 0x0824 +regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA5 = 0x0825 +regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA6 = 0x0826 +regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA7 = 0x0827 +regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA8 = 0x0828 +regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA9 = 0x0829 +regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_DATA10 = 0x082a +regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE4_MIDCMD_CNTL = 0x082b +regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_CNTL = 0x0838 +regSDMA1_QUEUE5_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_BASE = 0x0839 +regSDMA1_QUEUE5_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_BASE_HI = 0x083a +regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_RPTR = 0x083b +regSDMA1_QUEUE5_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_RPTR_HI = 0x083c +regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_WPTR = 0x083d +regSDMA1_QUEUE5_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_WPTR_HI = 0x083e +regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_RPTR_ADDR_HI = 0x0840 +regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_RPTR_ADDR_LO = 0x0841 +regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_CNTL = 0x0842 +regSDMA1_QUEUE5_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_RPTR = 0x0843 +regSDMA1_QUEUE5_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_OFFSET = 0x0844 +regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_BASE_LO = 0x0845 +regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_BASE_HI = 0x0846 +regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_SIZE = 0x0847 +regSDMA1_QUEUE5_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE5_SKIP_CNTL = 0x0848 +regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE5_CONTEXT_STATUS = 0x0849 +regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE5_DOORBELL = 0x084a +regSDMA1_QUEUE5_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE5_DOORBELL_LOG = 0x0861 +regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE5_DOORBELL_OFFSET = 0x0863 +regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE5_CSA_ADDR_LO = 0x0864 +regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE5_CSA_ADDR_HI = 0x0865 +regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_SCHEDULE_CNTL = 0x0866 +regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE5_IB_SUB_REMAIN = 0x0867 +regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE5_PREEMPT = 0x0868 +regSDMA1_QUEUE5_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE5_DUMMY_REG = 0x0869 +regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI = 0x086a +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO = 0x086b +regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_AQL_CNTL = 0x086c +regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE5_MINOR_PTR_UPDATE = 0x086d +regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE5_RB_PREEMPT = 0x086e +regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA0 = 0x0878 +regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA1 = 0x0879 +regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA2 = 0x087a +regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA3 = 0x087b +regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA4 = 0x087c +regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA5 = 0x087d +regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA6 = 0x087e +regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA7 = 0x087f +regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA8 = 0x0880 +regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA9 = 0x0881 +regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_DATA10 = 0x0882 +regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE5_MIDCMD_CNTL = 0x0883 +regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_CNTL = 0x0890 +regSDMA1_QUEUE6_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_BASE = 0x0891 +regSDMA1_QUEUE6_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_BASE_HI = 0x0892 +regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_RPTR = 0x0893 +regSDMA1_QUEUE6_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_RPTR_HI = 0x0894 +regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_WPTR = 0x0895 +regSDMA1_QUEUE6_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_WPTR_HI = 0x0896 +regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_RPTR_ADDR_HI = 0x0898 +regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_RPTR_ADDR_LO = 0x0899 +regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_CNTL = 0x089a +regSDMA1_QUEUE6_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_RPTR = 0x089b +regSDMA1_QUEUE6_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_OFFSET = 0x089c +regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_BASE_LO = 0x089d +regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_BASE_HI = 0x089e +regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_SIZE = 0x089f +regSDMA1_QUEUE6_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE6_SKIP_CNTL = 0x08a0 +regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE6_CONTEXT_STATUS = 0x08a1 +regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE6_DOORBELL = 0x08a2 +regSDMA1_QUEUE6_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE6_DOORBELL_LOG = 0x08b9 +regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE6_DOORBELL_OFFSET = 0x08bb +regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE6_CSA_ADDR_LO = 0x08bc +regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE6_CSA_ADDR_HI = 0x08bd +regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_SCHEDULE_CNTL = 0x08be +regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE6_IB_SUB_REMAIN = 0x08bf +regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE6_PREEMPT = 0x08c0 +regSDMA1_QUEUE6_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE6_DUMMY_REG = 0x08c1 +regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI = 0x08c2 +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO = 0x08c3 +regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_AQL_CNTL = 0x08c4 +regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE6_MINOR_PTR_UPDATE = 0x08c5 +regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE6_RB_PREEMPT = 0x08c6 +regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA0 = 0x08d0 +regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA1 = 0x08d1 +regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA2 = 0x08d2 +regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA3 = 0x08d3 +regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA4 = 0x08d4 +regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA5 = 0x08d5 +regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA6 = 0x08d6 +regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA7 = 0x08d7 +regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA8 = 0x08d8 +regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA9 = 0x08d9 +regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_DATA10 = 0x08da +regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE6_MIDCMD_CNTL = 0x08db +regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_CNTL = 0x08e8 +regSDMA1_QUEUE7_RB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_BASE = 0x08e9 +regSDMA1_QUEUE7_RB_BASE_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_BASE_HI = 0x08ea +regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_RPTR = 0x08eb +regSDMA1_QUEUE7_RB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_RPTR_HI = 0x08ec +regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_WPTR = 0x08ed +regSDMA1_QUEUE7_RB_WPTR_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_WPTR_HI = 0x08ee +regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_RPTR_ADDR_HI = 0x08f0 +regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_RPTR_ADDR_LO = 0x08f1 +regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_CNTL = 0x08f2 +regSDMA1_QUEUE7_IB_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_RPTR = 0x08f3 +regSDMA1_QUEUE7_IB_RPTR_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_OFFSET = 0x08f4 +regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_BASE_LO = 0x08f5 +regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_BASE_HI = 0x08f6 +regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_SIZE = 0x08f7 +regSDMA1_QUEUE7_IB_SIZE_BASE_IDX = 0 +regSDMA1_QUEUE7_SKIP_CNTL = 0x08f8 +regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE7_CONTEXT_STATUS = 0x08f9 +regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX = 0 +regSDMA1_QUEUE7_DOORBELL = 0x08fa +regSDMA1_QUEUE7_DOORBELL_BASE_IDX = 0 +regSDMA1_QUEUE7_DOORBELL_LOG = 0x0911 +regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX = 0 +regSDMA1_QUEUE7_DOORBELL_OFFSET = 0x0913 +regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX = 0 +regSDMA1_QUEUE7_CSA_ADDR_LO = 0x0914 +regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE7_CSA_ADDR_HI = 0x0915 +regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_SCHEDULE_CNTL = 0x0916 +regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE7_IB_SUB_REMAIN = 0x0917 +regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX = 0 +regSDMA1_QUEUE7_PREEMPT = 0x0918 +regSDMA1_QUEUE7_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE7_DUMMY_REG = 0x0919 +regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI = 0x091a +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO = 0x091b +regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_AQL_CNTL = 0x091c +regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX = 0 +regSDMA1_QUEUE7_MINOR_PTR_UPDATE = 0x091d +regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX = 0 +regSDMA1_QUEUE7_RB_PREEMPT = 0x091e +regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA0 = 0x0928 +regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA1 = 0x0929 +regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA2 = 0x092a +regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA3 = 0x092b +regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA4 = 0x092c +regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA5 = 0x092d +regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA6 = 0x092e +regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA7 = 0x092f +regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA8 = 0x0930 +regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA9 = 0x0931 +regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_DATA10 = 0x0932 +regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX = 0 +regSDMA1_QUEUE7_MIDCMD_CNTL = 0x0933 +regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX = 0 +regSDMA0_UCODE_ADDR = 0x5880 +regSDMA0_UCODE_ADDR_BASE_IDX = 1 +regSDMA0_UCODE_DATA = 0x5881 +regSDMA0_UCODE_DATA_BASE_IDX = 1 +regSDMA0_UCODE_SELFLOAD_CONTROL = 0x5882 +regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 +regSDMA0_BROADCAST_UCODE_ADDR = 0x5886 +regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 +regSDMA0_BROADCAST_UCODE_DATA = 0x5887 +regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 +regSDMA0_F32_CNTL = 0x589a +regSDMA0_F32_CNTL_BASE_IDX = 1 +regSDMA1_UCODE_ADDR = 0x58a0 +regSDMA1_UCODE_ADDR_BASE_IDX = 1 +regSDMA1_UCODE_DATA = 0x58a1 +regSDMA1_UCODE_DATA_BASE_IDX = 1 +regSDMA1_UCODE_SELFLOAD_CONTROL = 0x58a2 +regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX = 1 +regSDMA1_BROADCAST_UCODE_ADDR = 0x58a6 +regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX = 1 +regSDMA1_BROADCAST_UCODE_DATA = 0x58a7 +regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX = 1 +regSDMA1_F32_CNTL = 0x58ba +regSDMA1_F32_CNTL_BASE_IDX = 1 +regSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 +regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 +regSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 +regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 +regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 +regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 +regSDMA0_PERFCNT_MISC_CNTL = 0x3e23 +regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 +regSDMA0_PERFCOUNTER0_SELECT = 0x3e24 +regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 +regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regSDMA0_PERFCOUNTER1_SELECT = 0x3e26 +regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 +regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c +regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 +regSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d +regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 +regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e +regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 +regSDMA1_PERFCNT_MISC_CNTL = 0x3e2f +regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 +regSDMA1_PERFCOUNTER0_SELECT = 0x3e30 +regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 +regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regSDMA1_PERFCOUNTER1_SELECT = 0x3e32 +regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 +regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 +regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 +regSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 +regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 +regSDMA0_PERFCOUNTER0_LO = 0x3662 +regSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 +regSDMA0_PERFCOUNTER0_HI = 0x3663 +regSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 +regSDMA0_PERFCOUNTER1_LO = 0x3664 +regSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 +regSDMA0_PERFCOUNTER1_HI = 0x3665 +regSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 +regSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c +regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 +regSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d +regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 +regSDMA1_PERFCOUNTER0_LO = 0x366e +regSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 +regSDMA1_PERFCOUNTER0_HI = 0x366f +regSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 +regSDMA1_PERFCOUNTER1_LO = 0x3670 +regSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 +regSDMA1_PERFCOUNTER1_HI = 0x3671 +regSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 +regGRBM_CNTL = 0x0da0 +regGRBM_CNTL_BASE_IDX = 0 +regGRBM_SKEW_CNTL = 0x0da1 +regGRBM_SKEW_CNTL_BASE_IDX = 0 +regGRBM_STATUS2 = 0x0da2 +regGRBM_STATUS2_BASE_IDX = 0 +regGRBM_PWR_CNTL = 0x0da3 +regGRBM_PWR_CNTL_BASE_IDX = 0 +regGRBM_STATUS = 0x0da4 +regGRBM_STATUS_BASE_IDX = 0 +regGRBM_STATUS_SE0 = 0x0da5 +regGRBM_STATUS_SE0_BASE_IDX = 0 +regGRBM_STATUS_SE1 = 0x0da6 +regGRBM_STATUS_SE1_BASE_IDX = 0 +regGRBM_STATUS3 = 0x0da7 +regGRBM_STATUS3_BASE_IDX = 0 +regGRBM_SOFT_RESET = 0x0da8 +regGRBM_SOFT_RESET_BASE_IDX = 0 +regGRBM_GFX_CLKEN_CNTL = 0x0dac +regGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 +regGRBM_WAIT_IDLE_CLOCKS = 0x0dad +regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 +regGRBM_STATUS_SE2 = 0x0dae +regGRBM_STATUS_SE2_BASE_IDX = 0 +regGRBM_STATUS_SE3 = 0x0daf +regGRBM_STATUS_SE3_BASE_IDX = 0 +regGRBM_STATUS_SE4 = 0x0db0 +regGRBM_STATUS_SE4_BASE_IDX = 0 +regGRBM_STATUS_SE5 = 0x0db1 +regGRBM_STATUS_SE5_BASE_IDX = 0 +regGRBM_READ_ERROR = 0x0db6 +regGRBM_READ_ERROR_BASE_IDX = 0 +regGRBM_READ_ERROR2 = 0x0db7 +regGRBM_READ_ERROR2_BASE_IDX = 0 +regGRBM_INT_CNTL = 0x0db8 +regGRBM_INT_CNTL_BASE_IDX = 0 +regGRBM_TRAP_OP = 0x0db9 +regGRBM_TRAP_OP_BASE_IDX = 0 +regGRBM_TRAP_ADDR = 0x0dba +regGRBM_TRAP_ADDR_BASE_IDX = 0 +regGRBM_TRAP_ADDR_MSK = 0x0dbb +regGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 +regGRBM_TRAP_WD = 0x0dbc +regGRBM_TRAP_WD_BASE_IDX = 0 +regGRBM_TRAP_WD_MSK = 0x0dbd +regGRBM_TRAP_WD_MSK_BASE_IDX = 0 +regGRBM_DSM_BYPASS = 0x0dbe +regGRBM_DSM_BYPASS_BASE_IDX = 0 +regGRBM_WRITE_ERROR = 0x0dbf +regGRBM_WRITE_ERROR_BASE_IDX = 0 +regGRBM_CHIP_REVISION = 0x0dc1 +regGRBM_CHIP_REVISION_BASE_IDX = 0 +regGRBM_IH_CREDIT = 0x0dc4 +regGRBM_IH_CREDIT_BASE_IDX = 0 +regGRBM_PWR_CNTL2 = 0x0dc5 +regGRBM_PWR_CNTL2_BASE_IDX = 0 +regGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 +regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 +regGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 +regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 +regGRBM_INVALID_PIPE = 0x0dc9 +regGRBM_INVALID_PIPE_BASE_IDX = 0 +regGRBM_FENCE_RANGE0 = 0x0dca +regGRBM_FENCE_RANGE0_BASE_IDX = 0 +regGRBM_FENCE_RANGE1 = 0x0dcb +regGRBM_FENCE_RANGE1_BASE_IDX = 0 +regGRBM_SCRATCH_REG0 = 0x0de0 +regGRBM_SCRATCH_REG0_BASE_IDX = 0 +regGRBM_SCRATCH_REG1 = 0x0de1 +regGRBM_SCRATCH_REG1_BASE_IDX = 0 +regGRBM_SCRATCH_REG2 = 0x0de2 +regGRBM_SCRATCH_REG2_BASE_IDX = 0 +regGRBM_SCRATCH_REG3 = 0x0de3 +regGRBM_SCRATCH_REG3_BASE_IDX = 0 +regGRBM_SCRATCH_REG4 = 0x0de4 +regGRBM_SCRATCH_REG4_BASE_IDX = 0 +regGRBM_SCRATCH_REG5 = 0x0de5 +regGRBM_SCRATCH_REG5_BASE_IDX = 0 +regGRBM_SCRATCH_REG6 = 0x0de6 +regGRBM_SCRATCH_REG6_BASE_IDX = 0 +regGRBM_SCRATCH_REG7 = 0x0de7 +regGRBM_SCRATCH_REG7_BASE_IDX = 0 +regVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 +regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 +regCP_CPC_DEBUG_CNTL = 0x0e20 +regCP_CPC_DEBUG_CNTL_BASE_IDX = 0 +regCP_CPC_DEBUG_DATA = 0x0e21 +regCP_CPC_DEBUG_DATA_BASE_IDX = 0 +regCP_CPC_STATUS = 0x0e24 +regCP_CPC_STATUS_BASE_IDX = 0 +regCP_CPC_BUSY_STAT = 0x0e25 +regCP_CPC_BUSY_STAT_BASE_IDX = 0 +regCP_CPC_STALLED_STAT1 = 0x0e26 +regCP_CPC_STALLED_STAT1_BASE_IDX = 0 +regCP_CPF_STATUS = 0x0e27 +regCP_CPF_STATUS_BASE_IDX = 0 +regCP_CPF_BUSY_STAT = 0x0e28 +regCP_CPF_BUSY_STAT_BASE_IDX = 0 +regCP_CPF_STALLED_STAT1 = 0x0e29 +regCP_CPF_STALLED_STAT1_BASE_IDX = 0 +regCP_CPC_BUSY_STAT2 = 0x0e2a +regCP_CPC_BUSY_STAT2_BASE_IDX = 0 +regCP_CPC_GRBM_FREE_COUNT = 0x0e2b +regCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 +regCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c +regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 +regCP_MEC_ME1_HEADER_DUMP = 0x0e2e +regCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 +regCP_MEC_ME2_HEADER_DUMP = 0x0e2f +regCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 +regCP_CPC_SCRATCH_INDEX = 0x0e30 +regCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 +regCP_CPC_SCRATCH_DATA = 0x0e31 +regCP_CPC_SCRATCH_DATA_BASE_IDX = 0 +regCP_CPF_GRBM_FREE_COUNT = 0x0e32 +regCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 +regCP_CPF_BUSY_STAT2 = 0x0e33 +regCP_CPF_BUSY_STAT2_BASE_IDX = 0 +regCP_CPC_HALT_HYST_COUNT = 0x0e47 +regCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 +regCP_STALLED_STAT3 = 0x0f3c +regCP_STALLED_STAT3_BASE_IDX = 0 +regCP_STALLED_STAT1 = 0x0f3d +regCP_STALLED_STAT1_BASE_IDX = 0 +regCP_STALLED_STAT2 = 0x0f3e +regCP_STALLED_STAT2_BASE_IDX = 0 +regCP_BUSY_STAT = 0x0f3f +regCP_BUSY_STAT_BASE_IDX = 0 +regCP_STAT = 0x0f40 +regCP_STAT_BASE_IDX = 0 +regCP_ME_HEADER_DUMP = 0x0f41 +regCP_ME_HEADER_DUMP_BASE_IDX = 0 +regCP_PFP_HEADER_DUMP = 0x0f42 +regCP_PFP_HEADER_DUMP_BASE_IDX = 0 +regCP_GRBM_FREE_COUNT = 0x0f43 +regCP_GRBM_FREE_COUNT_BASE_IDX = 0 +regCP_PFP_INSTR_PNTR = 0x0f45 +regCP_PFP_INSTR_PNTR_BASE_IDX = 0 +regCP_ME_INSTR_PNTR = 0x0f46 +regCP_ME_INSTR_PNTR_BASE_IDX = 0 +regCP_MEC1_INSTR_PNTR = 0x0f48 +regCP_MEC1_INSTR_PNTR_BASE_IDX = 0 +regCP_MEC2_INSTR_PNTR = 0x0f49 +regCP_MEC2_INSTR_PNTR_BASE_IDX = 0 +regCP_CSF_STAT = 0x0f54 +regCP_CSF_STAT_BASE_IDX = 0 +regCP_CNTX_STAT = 0x0f58 +regCP_CNTX_STAT_BASE_IDX = 0 +regCP_ME_PREEMPTION = 0x0f59 +regCP_ME_PREEMPTION_BASE_IDX = 0 +regCP_RB1_RPTR = 0x0f5f +regCP_RB1_RPTR_BASE_IDX = 0 +regCP_RB0_RPTR = 0x0f60 +regCP_RB0_RPTR_BASE_IDX = 0 +regCP_RB_RPTR = 0x0f60 +regCP_RB_RPTR_BASE_IDX = 0 +regCP_RB_WPTR_DELAY = 0x0f61 +regCP_RB_WPTR_DELAY_BASE_IDX = 0 +regCP_RB_WPTR_POLL_CNTL = 0x0f62 +regCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 +regCP_ROQ1_THRESHOLDS = 0x0f75 +regCP_ROQ1_THRESHOLDS_BASE_IDX = 0 +regCP_ROQ2_THRESHOLDS = 0x0f76 +regCP_ROQ2_THRESHOLDS_BASE_IDX = 0 +regCP_STQ_THRESHOLDS = 0x0f77 +regCP_STQ_THRESHOLDS_BASE_IDX = 0 +regCP_MEQ_THRESHOLDS = 0x0f79 +regCP_MEQ_THRESHOLDS_BASE_IDX = 0 +regCP_ROQ_AVAIL = 0x0f7a +regCP_ROQ_AVAIL_BASE_IDX = 0 +regCP_STQ_AVAIL = 0x0f7b +regCP_STQ_AVAIL_BASE_IDX = 0 +regCP_ROQ2_AVAIL = 0x0f7c +regCP_ROQ2_AVAIL_BASE_IDX = 0 +regCP_MEQ_AVAIL = 0x0f7d +regCP_MEQ_AVAIL_BASE_IDX = 0 +regCP_CMD_INDEX = 0x0f7e +regCP_CMD_INDEX_BASE_IDX = 0 +regCP_CMD_DATA = 0x0f7f +regCP_CMD_DATA_BASE_IDX = 0 +regCP_ROQ_RB_STAT = 0x0f80 +regCP_ROQ_RB_STAT_BASE_IDX = 0 +regCP_ROQ_IB1_STAT = 0x0f81 +regCP_ROQ_IB1_STAT_BASE_IDX = 0 +regCP_ROQ_IB2_STAT = 0x0f82 +regCP_ROQ_IB2_STAT_BASE_IDX = 0 +regCP_STQ_STAT = 0x0f83 +regCP_STQ_STAT_BASE_IDX = 0 +regCP_STQ_WR_STAT = 0x0f84 +regCP_STQ_WR_STAT_BASE_IDX = 0 +regCP_MEQ_STAT = 0x0f85 +regCP_MEQ_STAT_BASE_IDX = 0 +regCP_ROQ3_THRESHOLDS = 0x0f8c +regCP_ROQ3_THRESHOLDS_BASE_IDX = 0 +regCP_ROQ_DB_STAT = 0x0f8d +regCP_ROQ_DB_STAT_BASE_IDX = 0 +regCP_DEBUG_CNTL = 0x0f98 +regCP_DEBUG_CNTL_BASE_IDX = 0 +regCP_DEBUG_DATA = 0x0f99 +regCP_DEBUG_DATA_BASE_IDX = 0 +regCP_PRIV_VIOLATION_ADDR = 0x0f9a +regCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 +regVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd +regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 +regVGT_DMA_REQ_FIFO_DEPTH = 0x0fce +regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 +regVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf +regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 +regVGT_MC_LAT_CNTL = 0x0fd6 +regVGT_MC_LAT_CNTL_BASE_IDX = 0 +regIA_UTCL1_STATUS_2 = 0x0fd7 +regIA_UTCL1_STATUS_2_BASE_IDX = 0 +regWD_CNTL_STATUS = 0x0fdf +regWD_CNTL_STATUS_BASE_IDX = 0 +regCC_GC_PRIM_CONFIG = 0x0fe0 +regCC_GC_PRIM_CONFIG_BASE_IDX = 0 +regWD_QOS = 0x0fe2 +regWD_QOS_BASE_IDX = 0 +regWD_UTCL1_CNTL = 0x0fe3 +regWD_UTCL1_CNTL_BASE_IDX = 0 +regWD_UTCL1_STATUS = 0x0fe4 +regWD_UTCL1_STATUS_BASE_IDX = 0 +regIA_UTCL1_CNTL = 0x0fe6 +regIA_UTCL1_CNTL_BASE_IDX = 0 +regIA_UTCL1_STATUS = 0x0fe7 +regIA_UTCL1_STATUS_BASE_IDX = 0 +regCC_GC_SA_UNIT_DISABLE = 0x0fe9 +regCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 +regGE_RATE_CNTL_1 = 0x0ff4 +regGE_RATE_CNTL_1_BASE_IDX = 0 +regGE_RATE_CNTL_2 = 0x0ff5 +regGE_RATE_CNTL_2_BASE_IDX = 0 +regVGT_SYS_CONFIG = 0x1003 +regVGT_SYS_CONFIG_BASE_IDX = 0 +regGE_PRIV_CONTROL = 0x1004 +regGE_PRIV_CONTROL_BASE_IDX = 0 +regGE_STATUS = 0x1005 +regGE_STATUS_BASE_IDX = 0 +regVGT_GS_MAX_WAVE_ID = 0x1009 +regVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 +regGFX_PIPE_CONTROL = 0x100d +regGFX_PIPE_CONTROL_BASE_IDX = 0 +regCC_GC_SHADER_ARRAY_CONFIG = 0x100f +regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 +regGE2_SE_CNTL_STATUS = 0x1011 +regGE2_SE_CNTL_STATUS_BASE_IDX = 0 +regGE_SPI_IF_SAFE_REG = 0x1018 +regGE_SPI_IF_SAFE_REG_BASE_IDX = 0 +regGE_PA_IF_SAFE_REG = 0x1019 +regGE_PA_IF_SAFE_REG_BASE_IDX = 0 +regPA_CL_CNTL_STATUS = 0x1024 +regPA_CL_CNTL_STATUS_BASE_IDX = 0 +regPA_CL_ENHANCE = 0x1025 +regPA_CL_ENHANCE_BASE_IDX = 0 +regPA_SU_CNTL_STATUS = 0x1034 +regPA_SU_CNTL_STATUS_BASE_IDX = 0 +regPA_SC_FIFO_DEPTH_CNTL = 0x1035 +regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 +regSQ_CONFIG = 0x10a0 +regSQ_CONFIG_BASE_IDX = 0 +regSQC_CONFIG = 0x10a1 +regSQC_CONFIG_BASE_IDX = 0 +regLDS_CONFIG = 0x10a2 +regLDS_CONFIG_BASE_IDX = 0 +regSQ_RANDOM_WAVE_PRI = 0x10a3 +regSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 +regSQG_STATUS = 0x10a4 +regSQG_STATUS_BASE_IDX = 0 +regSQ_FIFO_SIZES = 0x10a5 +regSQ_FIFO_SIZES_BASE_IDX = 0 +regSQ_DSM_CNTL = 0x10a6 +regSQ_DSM_CNTL_BASE_IDX = 0 +regSQ_DSM_CNTL2 = 0x10a7 +regSQ_DSM_CNTL2_BASE_IDX = 0 +regSP_CONFIG = 0x10ab +regSP_CONFIG_BASE_IDX = 0 +regSQ_ARB_CONFIG = 0x10ac +regSQ_ARB_CONFIG_BASE_IDX = 0 +regSQ_DEBUG_HOST_TRAP_STATUS = 0x10b6 +regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX = 0 +regSQG_GL1H_STATUS = 0x10b9 +regSQG_GL1H_STATUS_BASE_IDX = 0 +regSQG_CONFIG = 0x10ba +regSQG_CONFIG_BASE_IDX = 0 +regSQ_PERF_SNAPSHOT_CTRL = 0x10bb +regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX = 0 +regCC_GC_SHADER_RATE_CONFIG = 0x10bc +regCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 +regSQ_INTERRUPT_AUTO_MASK = 0x10be +regSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 +regSQ_INTERRUPT_MSG_CTRL = 0x10bf +regSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 +regSQ_WATCH0_ADDR_H = 0x10d0 +regSQ_WATCH0_ADDR_H_BASE_IDX = 0 +regSQ_WATCH0_ADDR_L = 0x10d1 +regSQ_WATCH0_ADDR_L_BASE_IDX = 0 +regSQ_WATCH0_CNTL = 0x10d2 +regSQ_WATCH0_CNTL_BASE_IDX = 0 +regSQ_WATCH1_ADDR_H = 0x10d3 +regSQ_WATCH1_ADDR_H_BASE_IDX = 0 +regSQ_WATCH1_ADDR_L = 0x10d4 +regSQ_WATCH1_ADDR_L_BASE_IDX = 0 +regSQ_WATCH1_CNTL = 0x10d5 +regSQ_WATCH1_CNTL_BASE_IDX = 0 +regSQ_WATCH2_ADDR_H = 0x10d6 +regSQ_WATCH2_ADDR_H_BASE_IDX = 0 +regSQ_WATCH2_ADDR_L = 0x10d7 +regSQ_WATCH2_ADDR_L_BASE_IDX = 0 +regSQ_WATCH2_CNTL = 0x10d8 +regSQ_WATCH2_CNTL_BASE_IDX = 0 +regSQ_WATCH3_ADDR_H = 0x10d9 +regSQ_WATCH3_ADDR_H_BASE_IDX = 0 +regSQ_WATCH3_ADDR_L = 0x10da +regSQ_WATCH3_ADDR_L_BASE_IDX = 0 +regSQ_WATCH3_CNTL = 0x10db +regSQ_WATCH3_CNTL_BASE_IDX = 0 +regSQ_IND_INDEX = 0x1118 +regSQ_IND_INDEX_BASE_IDX = 0 +regSQ_IND_DATA = 0x1119 +regSQ_IND_DATA_BASE_IDX = 0 +regSQ_CMD = 0x111b +regSQ_CMD_BASE_IDX = 0 +regSX_DEBUG_1 = 0x11b8 +regSX_DEBUG_1_BASE_IDX = 0 +regSPI_PS_MAX_WAVE_ID = 0x11da +regSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 +regSPI_GFX_CNTL = 0x11dc +regSPI_GFX_CNTL_BASE_IDX = 0 +regSPI_DSM_CNTL = 0x11e3 +regSPI_DSM_CNTL_BASE_IDX = 0 +regSPI_DSM_CNTL2 = 0x11e4 +regSPI_DSM_CNTL2_BASE_IDX = 0 +regSPI_EDC_CNT = 0x11e5 +regSPI_EDC_CNT_BASE_IDX = 0 +regSPI_CONFIG_PS_CU_EN = 0x11f2 +regSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 +regSPI_WF_LIFETIME_CNTL = 0x124a +regSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 +regSPI_WF_LIFETIME_LIMIT_0 = 0x124b +regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 +regSPI_WF_LIFETIME_LIMIT_1 = 0x124c +regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 +regSPI_WF_LIFETIME_LIMIT_2 = 0x124d +regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 +regSPI_WF_LIFETIME_LIMIT_3 = 0x124e +regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 +regSPI_WF_LIFETIME_LIMIT_4 = 0x124f +regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 +regSPI_WF_LIFETIME_LIMIT_5 = 0x1250 +regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_0 = 0x1255 +regSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_2 = 0x1257 +regSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_4 = 0x1259 +regSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_6 = 0x125b +regSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_7 = 0x125c +regSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_9 = 0x125e +regSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_11 = 0x1260 +regSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_13 = 0x1262 +regSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_14 = 0x1263 +regSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_15 = 0x1264 +regSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_16 = 0x1265 +regSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_17 = 0x1266 +regSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_18 = 0x1267 +regSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_19 = 0x1268 +regSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_20 = 0x1269 +regSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 +regSPI_WF_LIFETIME_STATUS_21 = 0x126b +regSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 +regSPI_LB_CTR_CTRL = 0x1274 +regSPI_LB_CTR_CTRL_BASE_IDX = 0 +regSPI_LB_WGP_MASK = 0x1275 +regSPI_LB_WGP_MASK_BASE_IDX = 0 +regSPI_LB_DATA_REG = 0x1276 +regSPI_LB_DATA_REG_BASE_IDX = 0 +regSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 +regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 +regSPI_GDS_CREDITS = 0x1278 +regSPI_GDS_CREDITS_BASE_IDX = 0 +regSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 +regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 +regSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a +regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 +regSPI_CSQ_WF_ACTIVE_STATUS = 0x127b +regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 +regSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c +regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 +regSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d +regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 +regSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e +regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 +regSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f +regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 +regSPI_LB_DATA_WAVES = 0x1284 +regSPI_LB_DATA_WAVES_BASE_IDX = 0 +regSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c +regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 +regSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d +regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 +regSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e +regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 +regSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f +regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 +regSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 +regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 +regSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 +regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 +regSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 +regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 +regSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 +regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 +regSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 +regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 +regSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 +regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 +regTD_STATUS = 0x12c6 +regTD_STATUS_BASE_IDX = 0 +regTD_DSM_CNTL = 0x12cf +regTD_DSM_CNTL_BASE_IDX = 0 +regTD_DSM_CNTL2 = 0x12d0 +regTD_DSM_CNTL2_BASE_IDX = 0 +regTD_SCRATCH = 0x12d3 +regTD_SCRATCH_BASE_IDX = 0 +regTA_CNTL = 0x12e1 +regTA_CNTL_BASE_IDX = 0 +regTA_CNTL_AUX = 0x12e2 +regTA_CNTL_AUX_BASE_IDX = 0 +regTA_CNTL2 = 0x12e5 +regTA_CNTL2_BASE_IDX = 0 +regTA_STATUS = 0x12e8 +regTA_STATUS_BASE_IDX = 0 +regTA_SCRATCH = 0x1304 +regTA_SCRATCH_BASE_IDX = 0 +regGDS_CONFIG = 0x1360 +regGDS_CONFIG_BASE_IDX = 0 +regGDS_CNTL_STATUS = 0x1361 +regGDS_CNTL_STATUS_BASE_IDX = 0 +regGDS_ENHANCE = 0x1362 +regGDS_ENHANCE_BASE_IDX = 0 +regGDS_PROTECTION_FAULT = 0x1363 +regGDS_PROTECTION_FAULT_BASE_IDX = 0 +regGDS_VM_PROTECTION_FAULT = 0x1364 +regGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 +regGDS_EDC_CNT = 0x1365 +regGDS_EDC_CNT_BASE_IDX = 0 +regGDS_EDC_GRBM_CNT = 0x1366 +regGDS_EDC_GRBM_CNT_BASE_IDX = 0 +regGDS_EDC_OA_DED = 0x1367 +regGDS_EDC_OA_DED_BASE_IDX = 0 +regGDS_DSM_CNTL = 0x136a +regGDS_DSM_CNTL_BASE_IDX = 0 +regGDS_EDC_OA_PHY_CNT = 0x136b +regGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 +regGDS_EDC_OA_PIPE_CNT = 0x136c +regGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 +regGDS_DSM_CNTL2 = 0x136d +regGDS_DSM_CNTL2_BASE_IDX = 0 +regDB_DEBUG = 0x13ac +regDB_DEBUG_BASE_IDX = 0 +regDB_DEBUG2 = 0x13ad +regDB_DEBUG2_BASE_IDX = 0 +regDB_DEBUG3 = 0x13ae +regDB_DEBUG3_BASE_IDX = 0 +regDB_DEBUG4 = 0x13af +regDB_DEBUG4_BASE_IDX = 0 +regDB_ETILE_STUTTER_CONTROL = 0x13b0 +regDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 +regDB_LTILE_STUTTER_CONTROL = 0x13b1 +regDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 +regDB_EQUAD_STUTTER_CONTROL = 0x13b2 +regDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 +regDB_LQUAD_STUTTER_CONTROL = 0x13b3 +regDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 +regDB_CREDIT_LIMIT = 0x13b4 +regDB_CREDIT_LIMIT_BASE_IDX = 0 +regDB_WATERMARKS = 0x13b5 +regDB_WATERMARKS_BASE_IDX = 0 +regDB_SUBTILE_CONTROL = 0x13b6 +regDB_SUBTILE_CONTROL_BASE_IDX = 0 +regDB_FREE_CACHELINES = 0x13b7 +regDB_FREE_CACHELINES_BASE_IDX = 0 +regDB_FIFO_DEPTH1 = 0x13b8 +regDB_FIFO_DEPTH1_BASE_IDX = 0 +regDB_FIFO_DEPTH2 = 0x13b9 +regDB_FIFO_DEPTH2_BASE_IDX = 0 +regDB_LAST_OF_BURST_CONFIG = 0x13ba +regDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 +regDB_RING_CONTROL = 0x13bb +regDB_RING_CONTROL_BASE_IDX = 0 +regDB_MEM_ARB_WATERMARKS = 0x13bc +regDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 +regDB_FIFO_DEPTH3 = 0x13bd +regDB_FIFO_DEPTH3_BASE_IDX = 0 +regDB_DEBUG6 = 0x13be +regDB_DEBUG6_BASE_IDX = 0 +regDB_EXCEPTION_CONTROL = 0x13bf +regDB_EXCEPTION_CONTROL_BASE_IDX = 0 +regDB_DEBUG7 = 0x13d0 +regDB_DEBUG7_BASE_IDX = 0 +regDB_DEBUG5 = 0x13d1 +regDB_DEBUG5_BASE_IDX = 0 +regDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 +regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 +regDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 +regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 +regDB_FIFO_DEPTH4 = 0x13d9 +regDB_FIFO_DEPTH4_BASE_IDX = 0 +regCC_RB_REDUNDANCY = 0x13dc +regCC_RB_REDUNDANCY_BASE_IDX = 0 +regCC_RB_BACKEND_DISABLE = 0x13dd +regCC_RB_BACKEND_DISABLE_BASE_IDX = 0 +regGB_ADDR_CONFIG = 0x13de +regGB_ADDR_CONFIG_BASE_IDX = 0 +regGB_BACKEND_MAP = 0x13df +regGB_BACKEND_MAP_BASE_IDX = 0 +regGB_GPU_ID = 0x13e0 +regGB_GPU_ID_BASE_IDX = 0 +regCC_RB_DAISY_CHAIN = 0x13e1 +regCC_RB_DAISY_CHAIN_BASE_IDX = 0 +regGB_ADDR_CONFIG_READ = 0x13e2 +regGB_ADDR_CONFIG_READ_BASE_IDX = 0 +regCB_HW_CONTROL_4 = 0x1422 +regCB_HW_CONTROL_4_BASE_IDX = 0 +regCB_HW_CONTROL_3 = 0x1423 +regCB_HW_CONTROL_3_BASE_IDX = 0 +regCB_HW_CONTROL = 0x1424 +regCB_HW_CONTROL_BASE_IDX = 0 +regCB_HW_CONTROL_1 = 0x1425 +regCB_HW_CONTROL_1_BASE_IDX = 0 +regCB_HW_CONTROL_2 = 0x1426 +regCB_HW_CONTROL_2_BASE_IDX = 0 +regCB_DCC_CONFIG = 0x1427 +regCB_DCC_CONFIG_BASE_IDX = 0 +regCB_HW_MEM_ARBITER_RD = 0x1428 +regCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 +regCB_HW_MEM_ARBITER_WR = 0x1429 +regCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 +regCB_FGCG_SRAM_OVERRIDE = 0x142a +regCB_FGCG_SRAM_OVERRIDE_BASE_IDX = 0 +regCB_DCC_CONFIG2 = 0x142b +regCB_DCC_CONFIG2_BASE_IDX = 0 +regCHICKEN_BITS = 0x142d +regCHICKEN_BITS_BASE_IDX = 0 +regCB_CACHE_EVICT_POINTS = 0x142e +regCB_CACHE_EVICT_POINTS_BASE_IDX = 0 +regGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 +regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 +regGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 +regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 +regGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 +regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 +regGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 +regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 +regGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 +regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 +regGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 +regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 +regGCEA_DRAM_RD_LAZY = 0x17a6 +regGCEA_DRAM_RD_LAZY_BASE_IDX = 0 +regGCEA_DRAM_WR_LAZY = 0x17a7 +regGCEA_DRAM_WR_LAZY_BASE_IDX = 0 +regGCEA_DRAM_RD_CAM_CNTL = 0x17a8 +regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 +regGCEA_DRAM_WR_CAM_CNTL = 0x17a9 +regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 +regGCEA_DRAM_PAGE_BURST = 0x17aa +regGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_AGE = 0x17ab +regGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_AGE = 0x17ac +regGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_QUEUING = 0x17ad +regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_QUEUING = 0x17ae +regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_FIXED = 0x17af +regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_FIXED = 0x17b0 +regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 +regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 +regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 +regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 +regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 +regGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 +regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 +regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 +regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 +regGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 +regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 +regGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d +regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 +regGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e +regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 +regGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f +regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 +regGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 +regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 +regGCEA_IO_RD_COMBINE_FLUSH = 0x1881 +regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 +regGCEA_IO_WR_COMBINE_FLUSH = 0x1882 +regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 +regGCEA_IO_GROUP_BURST = 0x1883 +regGCEA_IO_GROUP_BURST_BASE_IDX = 0 +regGCEA_IO_RD_PRI_AGE = 0x1884 +regGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 +regGCEA_IO_WR_PRI_AGE = 0x1885 +regGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 +regGCEA_IO_RD_PRI_QUEUING = 0x1886 +regGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 +regGCEA_IO_WR_PRI_QUEUING = 0x1887 +regGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 +regGCEA_IO_RD_PRI_FIXED = 0x1888 +regGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 +regGCEA_IO_WR_PRI_FIXED = 0x1889 +regGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 +regGCEA_IO_RD_PRI_URGENCY = 0x188a +regGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 +regGCEA_IO_WR_PRI_URGENCY = 0x188b +regGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 +regGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c +regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 +regGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d +regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 +regGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e +regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 +regGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f +regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 +regGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 +regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 +regGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 +regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 +regGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 +regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 +regGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 +regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 +regGCEA_SDP_ARB_FINAL = 0x1896 +regGCEA_SDP_ARB_FINAL_BASE_IDX = 0 +regGCEA_SDP_IO_PRIORITY = 0x1899 +regGCEA_SDP_IO_PRIORITY_BASE_IDX = 0 +regGCEA_SDP_CREDITS = 0x189a +regGCEA_SDP_CREDITS_BASE_IDX = 0 +regGCEA_SDP_TAG_RESERVE0 = 0x189b +regGCEA_SDP_TAG_RESERVE0_BASE_IDX = 0 +regGCEA_SDP_TAG_RESERVE1 = 0x189c +regGCEA_SDP_TAG_RESERVE1_BASE_IDX = 0 +regGCEA_SDP_VCC_RESERVE0 = 0x189d +regGCEA_SDP_VCC_RESERVE0_BASE_IDX = 0 +regGCEA_SDP_VCC_RESERVE1 = 0x189e +regGCEA_SDP_VCC_RESERVE1_BASE_IDX = 0 +regGCEA_MISC = 0x14a2 +regGCEA_MISC_BASE_IDX = 0 +regGCEA_LATENCY_SAMPLING = 0x14a3 +regGCEA_LATENCY_SAMPLING_BASE_IDX = 0 +regGCEA_MAM_CTRL2 = 0x14a9 +regGCEA_MAM_CTRL2_BASE_IDX = 0 +regGCEA_MAM_CTRL = 0x14ab +regGCEA_MAM_CTRL_BASE_IDX = 0 +regGCEA_EDC_CNT = 0x14b2 +regGCEA_EDC_CNT_BASE_IDX = 0 +regGCEA_EDC_CNT2 = 0x14b3 +regGCEA_EDC_CNT2_BASE_IDX = 0 +regGCEA_DSM_CNTL = 0x14b4 +regGCEA_DSM_CNTL_BASE_IDX = 0 +regGCEA_DSM_CNTLA = 0x14b5 +regGCEA_DSM_CNTLA_BASE_IDX = 0 +regGCEA_DSM_CNTLB = 0x14b6 +regGCEA_DSM_CNTLB_BASE_IDX = 0 +regGCEA_DSM_CNTL2 = 0x14b7 +regGCEA_DSM_CNTL2_BASE_IDX = 0 +regGCEA_DSM_CNTL2A = 0x14b8 +regGCEA_DSM_CNTL2A_BASE_IDX = 0 +regGCEA_DSM_CNTL2B = 0x14b9 +regGCEA_DSM_CNTL2B_BASE_IDX = 0 +regGCEA_GL2C_XBR_CREDITS = 0x14ba +regGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 +regGCEA_GL2C_XBR_MAXBURST = 0x14bb +regGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 +regGCEA_PROBE_CNTL = 0x14bc +regGCEA_PROBE_CNTL_BASE_IDX = 0 +regGCEA_PROBE_MAP = 0x14bd +regGCEA_PROBE_MAP_BASE_IDX = 0 +regGCEA_ERR_STATUS = 0x14be +regGCEA_ERR_STATUS_BASE_IDX = 0 +regGCEA_MISC2 = 0x14bf +regGCEA_MISC2_BASE_IDX = 0 +regGCEA_RRET_MEM_RESERVE = 0x1518 +regGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 +regGCEA_EDC_CNT3 = 0x151a +regGCEA_EDC_CNT3_BASE_IDX = 0 +regGCEA_SDP_ENABLE = 0x151e +regGCEA_SDP_ENABLE_BASE_IDX = 0 +regSPI_PQEV_CTRL = 0x14c0 +regSPI_PQEV_CTRL_BASE_IDX = 0 +regSPI_EXP_THROTTLE_CTRL = 0x14c3 +regSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 +regRMI_GENERAL_CNTL = 0x1880 +regRMI_GENERAL_CNTL_BASE_IDX = 1 +regRMI_GENERAL_CNTL1 = 0x1881 +regRMI_GENERAL_CNTL1_BASE_IDX = 1 +regRMI_GENERAL_STATUS = 0x1882 +regRMI_GENERAL_STATUS_BASE_IDX = 1 +regRMI_SUBBLOCK_STATUS0 = 0x1883 +regRMI_SUBBLOCK_STATUS0_BASE_IDX = 1 +regRMI_SUBBLOCK_STATUS1 = 0x1884 +regRMI_SUBBLOCK_STATUS1_BASE_IDX = 1 +regRMI_SUBBLOCK_STATUS2 = 0x1885 +regRMI_SUBBLOCK_STATUS2_BASE_IDX = 1 +regRMI_SUBBLOCK_STATUS3 = 0x1886 +regRMI_SUBBLOCK_STATUS3_BASE_IDX = 1 +regRMI_XBAR_CONFIG = 0x1887 +regRMI_XBAR_CONFIG_BASE_IDX = 1 +regRMI_PROBE_POP_LOGIC_CNTL = 0x1888 +regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 1 +regRMI_UTC_XNACK_N_MISC_CNTL = 0x1889 +regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 1 +regRMI_DEMUX_CNTL = 0x188a +regRMI_DEMUX_CNTL_BASE_IDX = 1 +regRMI_UTCL1_CNTL1 = 0x188b +regRMI_UTCL1_CNTL1_BASE_IDX = 1 +regRMI_UTCL1_CNTL2 = 0x188c +regRMI_UTCL1_CNTL2_BASE_IDX = 1 +regRMI_UTC_UNIT_CONFIG = 0x188d +regRMI_UTC_UNIT_CONFIG_BASE_IDX = 1 +regRMI_TCIW_FORMATTER0_CNTL = 0x188e +regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 1 +regRMI_TCIW_FORMATTER1_CNTL = 0x188f +regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 1 +regRMI_SCOREBOARD_CNTL = 0x1890 +regRMI_SCOREBOARD_CNTL_BASE_IDX = 1 +regRMI_SCOREBOARD_STATUS0 = 0x1891 +regRMI_SCOREBOARD_STATUS0_BASE_IDX = 1 +regRMI_SCOREBOARD_STATUS1 = 0x1892 +regRMI_SCOREBOARD_STATUS1_BASE_IDX = 1 +regRMI_SCOREBOARD_STATUS2 = 0x1893 +regRMI_SCOREBOARD_STATUS2_BASE_IDX = 1 +regRMI_XBAR_ARBITER_CONFIG = 0x1894 +regRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 1 +regRMI_XBAR_ARBITER_CONFIG_1 = 0x1895 +regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 1 +regRMI_CLOCK_CNTRL = 0x1896 +regRMI_CLOCK_CNTRL_BASE_IDX = 1 +regRMI_UTCL1_STATUS = 0x1897 +regRMI_UTCL1_STATUS_BASE_IDX = 1 +regRMI_RB_GLX_CID_MAP = 0x1898 +regRMI_RB_GLX_CID_MAP_BASE_IDX = 1 +regRMI_SPARE = 0x189f +regRMI_SPARE_BASE_IDX = 1 +regRMI_SPARE_1 = 0x18a0 +regRMI_SPARE_1_BASE_IDX = 1 +regRMI_SPARE_2 = 0x18a1 +regRMI_SPARE_2_BASE_IDX = 1 +regCC_RMI_REDUNDANCY = 0x18a2 +regCC_RMI_REDUNDANCY_BASE_IDX = 1 +regGCR_PIO_CNTL = 0x1580 +regGCR_PIO_CNTL_BASE_IDX = 0 +regGCR_PIO_DATA = 0x1581 +regGCR_PIO_DATA_BASE_IDX = 0 +regPMM_CNTL = 0x1582 +regPMM_CNTL_BASE_IDX = 0 +regPMM_STATUS = 0x1583 +regPMM_STATUS_BASE_IDX = 0 +regUTCL1_CTRL_1 = 0x158c +regUTCL1_CTRL_1_BASE_IDX = 0 +regUTCL1_ALOG = 0x158f +regUTCL1_ALOG_BASE_IDX = 0 +regUTCL1_STATUS = 0x1594 +regUTCL1_STATUS_BASE_IDX = 0 +regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x15a4 +regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 +regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x15a5 +regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 +regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x15a6 +regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 +regGCMC_VM_FB_OFFSET = 0x15a7 +regGCMC_VM_FB_OFFSET_BASE_IDX = 0 +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x15a8 +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x15a9 +regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 +regGCMC_VM_STEERING = 0x15aa +regGCMC_VM_STEERING_BASE_IDX = 0 +regGCMC_MEM_POWER_LS = 0x15ac +regGCMC_MEM_POWER_LS_BASE_IDX = 0 +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x15ad +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x15ae +regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x15af +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x15b0 +regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 +regGCMC_VM_APT_CNTL = 0x15b1 +regGCMC_VM_APT_CNTL_BASE_IDX = 0 +regGCMC_VM_LOCAL_FB_ADDRESS_START = 0x15b2 +regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 +regGCMC_VM_LOCAL_FB_ADDRESS_END = 0x15b3 +regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 +regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x15b4 +regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 +regGCUTCL2_ICG_CTRL = 0x15b5 +regGCUTCL2_ICG_CTRL_BASE_IDX = 0 +regGCUTCL2_CGTT_BUSY_CTRL = 0x15b7 +regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 +regGCMC_VM_FB_NOALLOC_CNTL = 0x15b8 +regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 +regGCUTCL2_HARVEST_BYPASS_GROUPS = 0x15b9 +regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 +regGCUTCL2_GROUP_RET_FAULT_STATUS = 0x15bb +regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 +regGCVM_L2_CNTL = 0x15bc +regGCVM_L2_CNTL_BASE_IDX = 0 +regGCVM_L2_CNTL2 = 0x15bd +regGCVM_L2_CNTL2_BASE_IDX = 0 +regGCVM_L2_CNTL3 = 0x15be +regGCVM_L2_CNTL3_BASE_IDX = 0 +regGCVM_L2_STATUS = 0x15bf +regGCVM_L2_STATUS_BASE_IDX = 0 +regGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 +regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 +regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 +regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 +regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 +regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_CNTL = 0x15c3 +regGCVM_INVALIDATE_CNTL_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 +regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 +regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 +regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 +regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 +regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 +regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca +regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc +regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 +regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 +regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 +regGCVM_L2_CNTL4 = 0x15d4 +regGCVM_L2_CNTL4_BASE_IDX = 0 +regGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 +regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 +regGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 +regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 +regGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 +regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 +regGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 +regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 +regGCVM_L2_ICG_CTRL = 0x15d9 +regGCVM_L2_ICG_CTRL_BASE_IDX = 0 +regGCVM_L2_CNTL5 = 0x15da +regGCVM_L2_CNTL5_BASE_IDX = 0 +regGCVM_L2_GCR_CNTL = 0x15db +regGCVM_L2_GCR_CNTL_BASE_IDX = 0 +regGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15dc +regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 +regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15dd +regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 +regGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15de +regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 +regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15df +regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 +regGCVM_L2_CGTT_BUSY_CTRL = 0x15e0 +regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 +regGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e1 +regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 +regGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e2 +regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x15e5 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x15e6 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x15e7 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x15e8 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 +regGCVM_L2_BANK_SELECT_MASKS = 0x15e9 +regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 +regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x15ea +regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x15eb +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x15ec +regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 +regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x15ed +regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 +regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x15ee +regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 +regGCMC_VM_FB_LOCATION_BASE = 0x1678 +regGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 +regGCMC_VM_FB_LOCATION_TOP = 0x1679 +regGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 +regGCMC_VM_AGP_TOP = 0x167a +regGCMC_VM_AGP_TOP_BASE_IDX = 0 +regGCMC_VM_AGP_BOT = 0x167b +regGCMC_VM_AGP_BOT_BASE_IDX = 0 +regGCMC_VM_AGP_BASE = 0x167c +regGCMC_VM_AGP_BASE_BASE_IDX = 0 +regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x167d +regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 +regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x167e +regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 +regGCMC_VM_MX_L1_TLB_CNTL = 0x167f +regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT0_CNTL = 0x1688 +regGCVM_CONTEXT0_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT1_CNTL = 0x1689 +regGCVM_CONTEXT1_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT2_CNTL = 0x168a +regGCVM_CONTEXT2_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT3_CNTL = 0x168b +regGCVM_CONTEXT3_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT4_CNTL = 0x168c +regGCVM_CONTEXT4_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT5_CNTL = 0x168d +regGCVM_CONTEXT5_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT6_CNTL = 0x168e +regGCVM_CONTEXT6_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT7_CNTL = 0x168f +regGCVM_CONTEXT7_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT8_CNTL = 0x1690 +regGCVM_CONTEXT8_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT9_CNTL = 0x1691 +regGCVM_CONTEXT9_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT10_CNTL = 0x1692 +regGCVM_CONTEXT10_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT11_CNTL = 0x1693 +regGCVM_CONTEXT11_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT12_CNTL = 0x1694 +regGCVM_CONTEXT12_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT13_CNTL = 0x1695 +regGCVM_CONTEXT13_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT14_CNTL = 0x1696 +regGCVM_CONTEXT14_CNTL_BASE_IDX = 0 +regGCVM_CONTEXT15_CNTL = 0x1697 +regGCVM_CONTEXT15_CNTL_BASE_IDX = 0 +regGCVM_CONTEXTS_DISABLE = 0x1698 +regGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG0_SEM = 0x1699 +regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG1_SEM = 0x169a +regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG2_SEM = 0x169b +regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG3_SEM = 0x169c +regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG4_SEM = 0x169d +regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG5_SEM = 0x169e +regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG6_SEM = 0x169f +regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG7_SEM = 0x16a0 +regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG8_SEM = 0x16a1 +regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG9_SEM = 0x16a2 +regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG10_SEM = 0x16a3 +regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG11_SEM = 0x16a4 +regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG12_SEM = 0x16a5 +regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG13_SEM = 0x16a6 +regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG14_SEM = 0x16a7 +regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG15_SEM = 0x16a8 +regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG16_SEM = 0x16a9 +regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG17_SEM = 0x16aa +regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG0_REQ = 0x16ab +regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG1_REQ = 0x16ac +regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG2_REQ = 0x16ad +regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG3_REQ = 0x16ae +regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG4_REQ = 0x16af +regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG5_REQ = 0x16b0 +regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG6_REQ = 0x16b1 +regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG7_REQ = 0x16b2 +regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG8_REQ = 0x16b3 +regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG9_REQ = 0x16b4 +regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG10_REQ = 0x16b5 +regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG11_REQ = 0x16b6 +regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG12_REQ = 0x16b7 +regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG13_REQ = 0x16b8 +regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG14_REQ = 0x16b9 +regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG15_REQ = 0x16ba +regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG16_REQ = 0x16bb +regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG17_REQ = 0x16bc +regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG0_ACK = 0x16bd +regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG1_ACK = 0x16be +regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG2_ACK = 0x16bf +regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG3_ACK = 0x16c0 +regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG4_ACK = 0x16c1 +regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG5_ACK = 0x16c2 +regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG6_ACK = 0x16c3 +regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG7_ACK = 0x16c4 +regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG8_ACK = 0x16c5 +regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG9_ACK = 0x16c6 +regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG10_ACK = 0x16c7 +regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG11_ACK = 0x16c8 +regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG12_ACK = 0x16c9 +regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG13_ACK = 0x16ca +regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG14_ACK = 0x16cb +regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG15_ACK = 0x16cc +regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG16_ACK = 0x16cd +regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG17_ACK = 0x16ce +regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x16cf +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x16d0 +regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x16d1 +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x16d2 +regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x16d3 +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x16d4 +regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x16d5 +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x16d6 +regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x16d7 +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x16d8 +regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x16d9 +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x16da +regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x16db +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x16dc +regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x16dd +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x16de +regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x16df +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x16e0 +regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x16e1 +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x16e2 +regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x16e3 +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x16e4 +regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x16e5 +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x16e6 +regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x16e7 +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x16e8 +regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x16e9 +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x16ea +regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x16eb +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x16ec +regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x16ed +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x16ee +regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x16ef +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x16f0 +regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x16f1 +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x16f2 +regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f3 +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f4 +regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f5 +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f6 +regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f7 +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x16f8 +regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x16f9 +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fa +regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fb +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fc +regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x16fd +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x16fe +regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x16ff +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1700 +regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1701 +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1702 +regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1703 +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1704 +regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1705 +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x1706 +regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x1707 +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x1708 +regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x1709 +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x170a +regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x170b +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x170c +regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x170d +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x170e +regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x170f +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1710 +regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1711 +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1712 +regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1713 +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1714 +regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1715 +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x1716 +regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x1717 +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x1718 +regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x1719 +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x171a +regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x171b +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x171c +regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x171d +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x171e +regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x171f +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1720 +regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1721 +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1722 +regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1723 +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1724 +regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1725 +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x1726 +regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x1727 +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x1728 +regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x1729 +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x172a +regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x172b +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x172c +regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x172d +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x172e +regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x172f +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x1730 +regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x1731 +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x1732 +regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x1733 +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x1734 +regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x1735 +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x1736 +regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x1737 +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x1738 +regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x1739 +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x173a +regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x173b +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x173c +regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x173d +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x173e +regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x173f +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x1740 +regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x1741 +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x1742 +regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x1743 +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x1744 +regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x1745 +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x1746 +regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x1747 +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x1748 +regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x1749 +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x174a +regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x174b +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x174c +regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x174d +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x174e +regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x174f +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x1750 +regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x1751 +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x1752 +regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 +regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1753 +regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1754 +regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1755 +regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1756 +regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1757 +regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1758 +regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1759 +regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175a +regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175b +regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175c +regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175d +regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175e +regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x175f +regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1760 +regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1761 +regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1762 +regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x1763 +regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 +regGCVML2_PERFCOUNTER2_0_LO = 0x34e0 +regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_1_LO = 0x34e1 +regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_0_HI = 0x34e2 +regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_1_HI = 0x34e3 +regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER_LO = 0x34e4 +regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER_HI = 0x34e5 +regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER_LO = 0x34e6 +regGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER_HI = 0x34e7 +regGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_0_SELECT = 0x3d20 +regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_1_SELECT = 0x3d21 +regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d22 +regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d23 +regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_0_MODE = 0x3d24 +regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 +regGCVML2_PERFCOUNTER2_1_MODE = 0x3d25 +regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d30 +regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d31 +regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d32 +regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d33 +regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d34 +regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d35 +regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d36 +regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d37 +regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 +regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d38 +regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER0_CFG = 0x3d39 +regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER1_CFG = 0x3d3a +regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER2_CFG = 0x3d3b +regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER3_CFG = 0x3d3c +regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 +regGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d3d +regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 +regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 +regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 +regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 +regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 +regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 +regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 +regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 +regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 +regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 +regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a +regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b +regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c +regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d +regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e +regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 +regGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f +regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 +regGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5e41 +regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x5e44 +regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_0 = 0x5e48 +regGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_1 = 0x5e49 +regGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_2 = 0x5e4a +regGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_3 = 0x5e4b +regGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_4 = 0x5e4c +regGCMC_VM_MARC_BASE_LO_4_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_5 = 0x5e4d +regGCMC_VM_MARC_BASE_LO_5_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_6 = 0x5e4e +regGCMC_VM_MARC_BASE_LO_6_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_7 = 0x5e4f +regGCMC_VM_MARC_BASE_LO_7_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_8 = 0x5e50 +regGCMC_VM_MARC_BASE_LO_8_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_9 = 0x5e51 +regGCMC_VM_MARC_BASE_LO_9_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_10 = 0x5e52 +regGCMC_VM_MARC_BASE_LO_10_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_11 = 0x5e53 +regGCMC_VM_MARC_BASE_LO_11_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_12 = 0x5e54 +regGCMC_VM_MARC_BASE_LO_12_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_13 = 0x5e55 +regGCMC_VM_MARC_BASE_LO_13_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_14 = 0x5e56 +regGCMC_VM_MARC_BASE_LO_14_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_LO_15 = 0x5e57 +regGCMC_VM_MARC_BASE_LO_15_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_0 = 0x5e58 +regGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_1 = 0x5e59 +regGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_2 = 0x5e5a +regGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_3 = 0x5e5b +regGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_4 = 0x5e5c +regGCMC_VM_MARC_BASE_HI_4_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_5 = 0x5e5d +regGCMC_VM_MARC_BASE_HI_5_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_6 = 0x5e5e +regGCMC_VM_MARC_BASE_HI_6_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_7 = 0x5e5f +regGCMC_VM_MARC_BASE_HI_7_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_8 = 0x5e60 +regGCMC_VM_MARC_BASE_HI_8_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_9 = 0x5e61 +regGCMC_VM_MARC_BASE_HI_9_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_10 = 0x5e62 +regGCMC_VM_MARC_BASE_HI_10_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_11 = 0x5e63 +regGCMC_VM_MARC_BASE_HI_11_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_12 = 0x5e64 +regGCMC_VM_MARC_BASE_HI_12_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_13 = 0x5e65 +regGCMC_VM_MARC_BASE_HI_13_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_14 = 0x5e66 +regGCMC_VM_MARC_BASE_HI_14_BASE_IDX = 1 +regGCMC_VM_MARC_BASE_HI_15 = 0x5e67 +regGCMC_VM_MARC_BASE_HI_15_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_0 = 0x5e68 +regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_1 = 0x5e69 +regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_2 = 0x5e6a +regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_3 = 0x5e6b +regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_4 = 0x5e6c +regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_5 = 0x5e6d +regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_6 = 0x5e6e +regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_7 = 0x5e6f +regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_8 = 0x5e70 +regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_9 = 0x5e71 +regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_10 = 0x5e72 +regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_11 = 0x5e73 +regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_12 = 0x5e74 +regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_13 = 0x5e75 +regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_14 = 0x5e76 +regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_LO_15 = 0x5e77 +regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_0 = 0x5e78 +regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_1 = 0x5e79 +regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_2 = 0x5e7a +regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_3 = 0x5e7b +regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_4 = 0x5e7c +regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_5 = 0x5e7d +regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_6 = 0x5e7e +regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_7 = 0x5e7f +regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_8 = 0x5e80 +regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_9 = 0x5e81 +regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_10 = 0x5e82 +regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_11 = 0x5e83 +regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_12 = 0x5e84 +regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_13 = 0x5e85 +regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_14 = 0x5e86 +regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX = 1 +regGCMC_VM_MARC_RELOC_HI_15 = 0x5e87 +regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_0 = 0x5e88 +regGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_1 = 0x5e89 +regGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_2 = 0x5e8a +regGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_3 = 0x5e8b +regGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_4 = 0x5e8c +regGCMC_VM_MARC_LEN_LO_4_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_5 = 0x5e8d +regGCMC_VM_MARC_LEN_LO_5_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_6 = 0x5e8e +regGCMC_VM_MARC_LEN_LO_6_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_7 = 0x5e8f +regGCMC_VM_MARC_LEN_LO_7_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_8 = 0x5e90 +regGCMC_VM_MARC_LEN_LO_8_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_9 = 0x5e91 +regGCMC_VM_MARC_LEN_LO_9_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_10 = 0x5e92 +regGCMC_VM_MARC_LEN_LO_10_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_11 = 0x5e93 +regGCMC_VM_MARC_LEN_LO_11_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_12 = 0x5e94 +regGCMC_VM_MARC_LEN_LO_12_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_13 = 0x5e95 +regGCMC_VM_MARC_LEN_LO_13_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_14 = 0x5e96 +regGCMC_VM_MARC_LEN_LO_14_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_LO_15 = 0x5e97 +regGCMC_VM_MARC_LEN_LO_15_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_0 = 0x5e98 +regGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_1 = 0x5e99 +regGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_2 = 0x5e9a +regGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_3 = 0x5e9b +regGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_4 = 0x5e9c +regGCMC_VM_MARC_LEN_HI_4_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_5 = 0x5e9d +regGCMC_VM_MARC_LEN_HI_5_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_6 = 0x5e9e +regGCMC_VM_MARC_LEN_HI_6_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_7 = 0x5e9f +regGCMC_VM_MARC_LEN_HI_7_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_8 = 0x5ea0 +regGCMC_VM_MARC_LEN_HI_8_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_9 = 0x5ea1 +regGCMC_VM_MARC_LEN_HI_9_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_10 = 0x5ea2 +regGCMC_VM_MARC_LEN_HI_10_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_11 = 0x5ea3 +regGCMC_VM_MARC_LEN_HI_11_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_12 = 0x5ea4 +regGCMC_VM_MARC_LEN_HI_12_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_13 = 0x5ea5 +regGCMC_VM_MARC_LEN_HI_13_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_14 = 0x5ea6 +regGCMC_VM_MARC_LEN_HI_14_BASE_IDX = 1 +regGCMC_VM_MARC_LEN_HI_15 = 0x5ea7 +regGCMC_VM_MARC_LEN_HI_15_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_0 = 0x5ea8 +regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_1 = 0x5ea9 +regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_2 = 0x5eaa +regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_3 = 0x5eab +regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_4 = 0x5eac +regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_5 = 0x5ead +regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_6 = 0x5eae +regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_7 = 0x5eaf +regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_8 = 0x5eb0 +regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_9 = 0x5eb1 +regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_10 = 0x5eb2 +regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_11 = 0x5eb3 +regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_12 = 0x5eb4 +regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_13 = 0x5eb5 +regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_14 = 0x5eb6 +regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX = 1 +regGCMC_VM_MARC_PFVF_MAPPING_15 = 0x5eb7 +regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX = 1 +regGCUTC_TRANSLATION_FAULT_CNTL0 = 0x5eb8 +regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 1 +regGCUTC_TRANSLATION_FAULT_CNTL1 = 0x5eb9 +regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 1 +regSPI_SHADER_PGM_RSRC4_PS = 0x19a1 +regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 +regSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 +regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC3_PS = 0x19a7 +regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_PS = 0x19a8 +regSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_PS = 0x19a9 +regSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC1_PS = 0x19aa +regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC2_PS = 0x19ab +regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_0 = 0x19ac +regSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_1 = 0x19ad +regSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_2 = 0x19ae +regSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_3 = 0x19af +regSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_4 = 0x19b0 +regSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_5 = 0x19b1 +regSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_6 = 0x19b2 +regSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_7 = 0x19b3 +regSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_8 = 0x19b4 +regSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_9 = 0x19b5 +regSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_10 = 0x19b6 +regSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_11 = 0x19b7 +regSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_12 = 0x19b8 +regSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_13 = 0x19b9 +regSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_14 = 0x19ba +regSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_15 = 0x19bb +regSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_16 = 0x19bc +regSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_17 = 0x19bd +regSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_18 = 0x19be +regSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_19 = 0x19bf +regSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_20 = 0x19c0 +regSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_21 = 0x19c1 +regSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_22 = 0x19c2 +regSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_23 = 0x19c3 +regSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_24 = 0x19c4 +regSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_25 = 0x19c5 +regSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_26 = 0x19c6 +regSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_27 = 0x19c7 +regSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_28 = 0x19c8 +regSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_29 = 0x19c9 +regSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_30 = 0x19ca +regSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_PS_31 = 0x19cb +regSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 +regSPI_SHADER_REQ_CTRL_PS = 0x19d0 +regSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 +regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 +regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 +regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 +regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 +regSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 +regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC4_GS = 0x1a21 +regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 +regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 +regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_ES_GS = 0x1a24 +regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_ES_GS = 0x1a25 +regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC3_GS = 0x1a27 +regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_GS = 0x1a28 +regSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_GS = 0x1a29 +regSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC1_GS = 0x1a2a +regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC2_GS = 0x1a2b +regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_0 = 0x1a2c +regSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_1 = 0x1a2d +regSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_2 = 0x1a2e +regSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_3 = 0x1a2f +regSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_4 = 0x1a30 +regSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_5 = 0x1a31 +regSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_6 = 0x1a32 +regSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_7 = 0x1a33 +regSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_8 = 0x1a34 +regSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_9 = 0x1a35 +regSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_10 = 0x1a36 +regSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_11 = 0x1a37 +regSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_12 = 0x1a38 +regSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_13 = 0x1a39 +regSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_14 = 0x1a3a +regSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_15 = 0x1a3b +regSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_16 = 0x1a3c +regSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_17 = 0x1a3d +regSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_18 = 0x1a3e +regSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_19 = 0x1a3f +regSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_20 = 0x1a40 +regSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_21 = 0x1a41 +regSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_22 = 0x1a42 +regSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_23 = 0x1a43 +regSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_24 = 0x1a44 +regSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_25 = 0x1a45 +regSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_26 = 0x1a46 +regSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_27 = 0x1a47 +regSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_28 = 0x1a48 +regSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_29 = 0x1a49 +regSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_30 = 0x1a4a +regSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_GS_31 = 0x1a4b +regSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 +regSPI_SHADER_GS_MESHLET_DIM = 0x1a4c +regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX = 0 +regSPI_SHADER_GS_MESHLET_EXP_ALLOC = 0x1a4d +regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX = 0 +regSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 +regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 +regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 +regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 +regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 +regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_ES = 0x1a68 +regSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_ES = 0x1a69 +regSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 +regSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 +regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 +regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 +regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 +regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 +regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 +regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 +regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_HS = 0x1aa8 +regSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_HS = 0x1aa9 +regSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC1_HS = 0x1aaa +regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 +regSPI_SHADER_PGM_RSRC2_HS = 0x1aab +regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_0 = 0x1aac +regSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_1 = 0x1aad +regSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_2 = 0x1aae +regSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_3 = 0x1aaf +regSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 +regSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 +regSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 +regSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 +regSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 +regSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 +regSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 +regSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 +regSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 +regSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 +regSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_14 = 0x1aba +regSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_15 = 0x1abb +regSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_16 = 0x1abc +regSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_17 = 0x1abd +regSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_18 = 0x1abe +regSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_19 = 0x1abf +regSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 +regSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 +regSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 +regSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 +regSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 +regSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 +regSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 +regSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 +regSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 +regSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 +regSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_30 = 0x1aca +regSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 +regSPI_SHADER_USER_DATA_HS_31 = 0x1acb +regSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 +regSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 +regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 +regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 +regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 +regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 +regSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 +regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 +regSPI_SHADER_PGM_LO_LS = 0x1ae8 +regSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 +regSPI_SHADER_PGM_HI_LS = 0x1ae9 +regSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 +regCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 +regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 +regCOMPUTE_DIM_X = 0x1ba1 +regCOMPUTE_DIM_X_BASE_IDX = 0 +regCOMPUTE_DIM_Y = 0x1ba2 +regCOMPUTE_DIM_Y_BASE_IDX = 0 +regCOMPUTE_DIM_Z = 0x1ba3 +regCOMPUTE_DIM_Z_BASE_IDX = 0 +regCOMPUTE_START_X = 0x1ba4 +regCOMPUTE_START_X_BASE_IDX = 0 +regCOMPUTE_START_Y = 0x1ba5 +regCOMPUTE_START_Y_BASE_IDX = 0 +regCOMPUTE_START_Z = 0x1ba6 +regCOMPUTE_START_Z_BASE_IDX = 0 +regCOMPUTE_NUM_THREAD_X = 0x1ba7 +regCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 +regCOMPUTE_NUM_THREAD_Y = 0x1ba8 +regCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 +regCOMPUTE_NUM_THREAD_Z = 0x1ba9 +regCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 +regCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa +regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 +regCOMPUTE_PERFCOUNT_ENABLE = 0x1bab +regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 +regCOMPUTE_PGM_LO = 0x1bac +regCOMPUTE_PGM_LO_BASE_IDX = 0 +regCOMPUTE_PGM_HI = 0x1bad +regCOMPUTE_PGM_HI_BASE_IDX = 0 +regCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae +regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 +regCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf +regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 +regCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 +regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 +regCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 +regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 +regCOMPUTE_PGM_RSRC1 = 0x1bb2 +regCOMPUTE_PGM_RSRC1_BASE_IDX = 0 +regCOMPUTE_PGM_RSRC2 = 0x1bb3 +regCOMPUTE_PGM_RSRC2_BASE_IDX = 0 +regCOMPUTE_VMID = 0x1bb4 +regCOMPUTE_VMID_BASE_IDX = 0 +regCOMPUTE_RESOURCE_LIMITS = 0x1bb5 +regCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 +regCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 +regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 +regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 +regCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 +regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 +regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 +regCOMPUTE_TMPRING_SIZE = 0x1bb8 +regCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 +regCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 +regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 +regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 +regCOMPUTE_DESTINATION_EN_SE3 = 0x1bba +regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba +regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 +regCOMPUTE_RESTART_X = 0x1bbb +regCOMPUTE_RESTART_X_BASE_IDX = 0 +regCOMPUTE_RESTART_Y = 0x1bbc +regCOMPUTE_RESTART_Y_BASE_IDX = 0 +regCOMPUTE_RESTART_Z = 0x1bbd +regCOMPUTE_RESTART_Z_BASE_IDX = 0 +regCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe +regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 +regCOMPUTE_MISC_RESERVED = 0x1bbf +regCOMPUTE_MISC_RESERVED_BASE_IDX = 0 +regCOMPUTE_DISPATCH_ID = 0x1bc0 +regCOMPUTE_DISPATCH_ID_BASE_IDX = 0 +regCOMPUTE_THREADGROUP_ID = 0x1bc1 +regCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 +regCOMPUTE_REQ_CTRL = 0x1bc2 +regCOMPUTE_REQ_CTRL_BASE_IDX = 0 +regCOMPUTE_USER_ACCUM_0 = 0x1bc4 +regCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 +regCOMPUTE_USER_ACCUM_1 = 0x1bc5 +regCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 +regCOMPUTE_USER_ACCUM_2 = 0x1bc6 +regCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 +regCOMPUTE_USER_ACCUM_3 = 0x1bc7 +regCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 +regCOMPUTE_PGM_RSRC3 = 0x1bc8 +regCOMPUTE_PGM_RSRC3_BASE_IDX = 0 +regCOMPUTE_DDID_INDEX = 0x1bc9 +regCOMPUTE_DDID_INDEX_BASE_IDX = 0 +regCOMPUTE_SHADER_CHKSUM = 0x1bca +regCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE4 = 0x1bcb +regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE5 = 0x1bcc +regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE6 = 0x1bcd +regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX = 0 +regCOMPUTE_STATIC_THREAD_MGMT_SE7 = 0x1bce +regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX = 0 +regCOMPUTE_DISPATCH_INTERLEAVE = 0x1bcf +regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX = 0 +regCOMPUTE_RELAUNCH = 0x1bd0 +regCOMPUTE_RELAUNCH_BASE_IDX = 0 +regCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bd1 +regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 +regCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bd2 +regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 +regCOMPUTE_RELAUNCH2 = 0x1bd3 +regCOMPUTE_RELAUNCH2_BASE_IDX = 0 +regCOMPUTE_USER_DATA_0 = 0x1be0 +regCOMPUTE_USER_DATA_0_BASE_IDX = 0 +regCOMPUTE_USER_DATA_1 = 0x1be1 +regCOMPUTE_USER_DATA_1_BASE_IDX = 0 +regCOMPUTE_USER_DATA_2 = 0x1be2 +regCOMPUTE_USER_DATA_2_BASE_IDX = 0 +regCOMPUTE_USER_DATA_3 = 0x1be3 +regCOMPUTE_USER_DATA_3_BASE_IDX = 0 +regCOMPUTE_USER_DATA_4 = 0x1be4 +regCOMPUTE_USER_DATA_4_BASE_IDX = 0 +regCOMPUTE_USER_DATA_5 = 0x1be5 +regCOMPUTE_USER_DATA_5_BASE_IDX = 0 +regCOMPUTE_USER_DATA_6 = 0x1be6 +regCOMPUTE_USER_DATA_6_BASE_IDX = 0 +regCOMPUTE_USER_DATA_7 = 0x1be7 +regCOMPUTE_USER_DATA_7_BASE_IDX = 0 +regCOMPUTE_USER_DATA_8 = 0x1be8 +regCOMPUTE_USER_DATA_8_BASE_IDX = 0 +regCOMPUTE_USER_DATA_9 = 0x1be9 +regCOMPUTE_USER_DATA_9_BASE_IDX = 0 +regCOMPUTE_USER_DATA_10 = 0x1bea +regCOMPUTE_USER_DATA_10_BASE_IDX = 0 +regCOMPUTE_USER_DATA_11 = 0x1beb +regCOMPUTE_USER_DATA_11_BASE_IDX = 0 +regCOMPUTE_USER_DATA_12 = 0x1bec +regCOMPUTE_USER_DATA_12_BASE_IDX = 0 +regCOMPUTE_USER_DATA_13 = 0x1bed +regCOMPUTE_USER_DATA_13_BASE_IDX = 0 +regCOMPUTE_USER_DATA_14 = 0x1bee +regCOMPUTE_USER_DATA_14_BASE_IDX = 0 +regCOMPUTE_USER_DATA_15 = 0x1bef +regCOMPUTE_USER_DATA_15_BASE_IDX = 0 +regCOMPUTE_DISPATCH_TUNNEL = 0x1c1d +regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 +regCOMPUTE_DISPATCH_END = 0x1c1e +regCOMPUTE_DISPATCH_END_BASE_IDX = 0 +regCOMPUTE_NOWHERE = 0x1c1f +regCOMPUTE_NOWHERE_BASE_IDX = 0 +regSH_RESERVED_REG0 = 0x1c20 +regSH_RESERVED_REG0_BASE_IDX = 0 +regSH_RESERVED_REG1 = 0x1c21 +regSH_RESERVED_REG1_BASE_IDX = 0 +regCP_CU_MASK_ADDR_LO = 0x1dd2 +regCP_CU_MASK_ADDR_LO_BASE_IDX = 0 +regCP_CU_MASK_ADDR_HI = 0x1dd3 +regCP_CU_MASK_ADDR_HI_BASE_IDX = 0 +regCP_CU_MASK_CNTL = 0x1dd4 +regCP_CU_MASK_CNTL_BASE_IDX = 0 +regCP_EOPQ_WAIT_TIME = 0x1dd5 +regCP_EOPQ_WAIT_TIME_BASE_IDX = 0 +regCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 +regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 +regCPC_INT_INFO = 0x1dd7 +regCPC_INT_INFO_BASE_IDX = 0 +regCP_VIRT_STATUS = 0x1dd8 +regCP_VIRT_STATUS_BASE_IDX = 0 +regCPC_INT_ADDR = 0x1dd9 +regCPC_INT_ADDR_BASE_IDX = 0 +regCPC_INT_PASID = 0x1dda +regCPC_INT_PASID_BASE_IDX = 0 +regCP_GFX_ERROR = 0x1ddb +regCP_GFX_ERROR_BASE_IDX = 0 +regCPG_UTCL1_CNTL = 0x1ddc +regCPG_UTCL1_CNTL_BASE_IDX = 0 +regCPC_UTCL1_CNTL = 0x1ddd +regCPC_UTCL1_CNTL_BASE_IDX = 0 +regCPF_UTCL1_CNTL = 0x1dde +regCPF_UTCL1_CNTL_BASE_IDX = 0 +regCP_AQL_SMM_STATUS = 0x1ddf +regCP_AQL_SMM_STATUS_BASE_IDX = 0 +regCP_RB0_BASE = 0x1de0 +regCP_RB0_BASE_BASE_IDX = 0 +regCP_RB_BASE = 0x1de0 +regCP_RB_BASE_BASE_IDX = 0 +regCP_RB0_CNTL = 0x1de1 +regCP_RB0_CNTL_BASE_IDX = 0 +regCP_RB_CNTL = 0x1de1 +regCP_RB_CNTL_BASE_IDX = 0 +regCP_RB_RPTR_WR = 0x1de2 +regCP_RB_RPTR_WR_BASE_IDX = 0 +regCP_RB0_RPTR_ADDR = 0x1de3 +regCP_RB0_RPTR_ADDR_BASE_IDX = 0 +regCP_RB_RPTR_ADDR = 0x1de3 +regCP_RB_RPTR_ADDR_BASE_IDX = 0 +regCP_RB0_RPTR_ADDR_HI = 0x1de4 +regCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 +regCP_RB_RPTR_ADDR_HI = 0x1de4 +regCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 +regCP_RB0_BUFSZ_MASK = 0x1de5 +regCP_RB0_BUFSZ_MASK_BASE_IDX = 0 +regCP_RB_BUFSZ_MASK = 0x1de5 +regCP_RB_BUFSZ_MASK_BASE_IDX = 0 +regCP_INT_CNTL = 0x1de9 +regCP_INT_CNTL_BASE_IDX = 0 +regCP_INT_STATUS = 0x1dea +regCP_INT_STATUS_BASE_IDX = 0 +regCP_DEVICE_ID = 0x1deb +regCP_DEVICE_ID_BASE_IDX = 0 +regCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec +regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 +regCP_RING_PRIORITY_CNTS = 0x1dec +regCP_RING_PRIORITY_CNTS_BASE_IDX = 0 +regCP_ME0_PIPE0_PRIORITY = 0x1ded +regCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 +regCP_RING0_PRIORITY = 0x1ded +regCP_RING0_PRIORITY_BASE_IDX = 0 +regCP_ME0_PIPE1_PRIORITY = 0x1dee +regCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 +regCP_RING1_PRIORITY = 0x1dee +regCP_RING1_PRIORITY_BASE_IDX = 0 +regCP_FATAL_ERROR = 0x1df0 +regCP_FATAL_ERROR_BASE_IDX = 0 +regCP_RB_VMID = 0x1df1 +regCP_RB_VMID_BASE_IDX = 0 +regCP_ME0_PIPE0_VMID = 0x1df2 +regCP_ME0_PIPE0_VMID_BASE_IDX = 0 +regCP_ME0_PIPE1_VMID = 0x1df3 +regCP_ME0_PIPE1_VMID_BASE_IDX = 0 +regCP_RB0_WPTR = 0x1df4 +regCP_RB0_WPTR_BASE_IDX = 0 +regCP_RB_WPTR = 0x1df4 +regCP_RB_WPTR_BASE_IDX = 0 +regCP_RB0_WPTR_HI = 0x1df5 +regCP_RB0_WPTR_HI_BASE_IDX = 0 +regCP_RB_WPTR_HI = 0x1df5 +regCP_RB_WPTR_HI_BASE_IDX = 0 +regCP_RB1_WPTR = 0x1df6 +regCP_RB1_WPTR_BASE_IDX = 0 +regCP_RB1_WPTR_HI = 0x1df7 +regCP_RB1_WPTR_HI_BASE_IDX = 0 +regCP_PROCESS_QUANTUM = 0x1df9 +regCP_PROCESS_QUANTUM_BASE_IDX = 0 +regCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa +regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 +regCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb +regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 +regCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc +regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 +regCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd +regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 +regCPG_UTCL1_ERROR = 0x1dfe +regCPG_UTCL1_ERROR_BASE_IDX = 0 +regCPC_UTCL1_ERROR = 0x1dff +regCPC_UTCL1_ERROR_BASE_IDX = 0 +regCP_RB1_BASE = 0x1e00 +regCP_RB1_BASE_BASE_IDX = 0 +regCP_RB1_CNTL = 0x1e01 +regCP_RB1_CNTL_BASE_IDX = 0 +regCP_RB1_RPTR_ADDR = 0x1e02 +regCP_RB1_RPTR_ADDR_BASE_IDX = 0 +regCP_RB1_RPTR_ADDR_HI = 0x1e03 +regCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 +regCP_RB1_BUFSZ_MASK = 0x1e04 +regCP_RB1_BUFSZ_MASK_BASE_IDX = 0 +regCP_INT_CNTL_RING0 = 0x1e0a +regCP_INT_CNTL_RING0_BASE_IDX = 0 +regCP_INT_CNTL_RING1 = 0x1e0b +regCP_INT_CNTL_RING1_BASE_IDX = 0 +regCP_INT_STATUS_RING0 = 0x1e0d +regCP_INT_STATUS_RING0_BASE_IDX = 0 +regCP_INT_STATUS_RING1 = 0x1e0e +regCP_INT_STATUS_RING1_BASE_IDX = 0 +regCP_ME_F32_INTERRUPT = 0x1e13 +regCP_ME_F32_INTERRUPT_BASE_IDX = 0 +regCP_PFP_F32_INTERRUPT = 0x1e14 +regCP_PFP_F32_INTERRUPT_BASE_IDX = 0 +regCP_MEC1_F32_INTERRUPT = 0x1e16 +regCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 +regCP_MEC2_F32_INTERRUPT = 0x1e17 +regCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 +regCP_PWR_CNTL = 0x1e18 +regCP_PWR_CNTL_BASE_IDX = 0 +regCP_ECC_FIRSTOCCURRENCE = 0x1e1a +regCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 +regCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b +regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 +regCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c +regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 +regGB_EDC_MODE = 0x1e1e +regGB_EDC_MODE_BASE_IDX = 0 +regCP_DEBUG = 0x1e1f +regCP_DEBUG_BASE_IDX = 0 +regCP_CPC_DEBUG = 0x1e21 +regCP_CPC_DEBUG_BASE_IDX = 0 +regCP_PQ_WPTR_POLL_CNTL = 0x1e23 +regCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 +regCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 +regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 +regCP_ME1_PIPE0_INT_CNTL = 0x1e25 +regCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 +regCP_ME1_PIPE1_INT_CNTL = 0x1e26 +regCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 +regCP_ME1_PIPE2_INT_CNTL = 0x1e27 +regCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 +regCP_ME1_PIPE3_INT_CNTL = 0x1e28 +regCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 +regCP_ME2_PIPE0_INT_CNTL = 0x1e29 +regCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 +regCP_ME2_PIPE1_INT_CNTL = 0x1e2a +regCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 +regCP_ME2_PIPE2_INT_CNTL = 0x1e2b +regCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 +regCP_ME2_PIPE3_INT_CNTL = 0x1e2c +regCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 +regCP_ME1_PIPE0_INT_STATUS = 0x1e2d +regCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 +regCP_ME1_PIPE1_INT_STATUS = 0x1e2e +regCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 +regCP_ME1_PIPE2_INT_STATUS = 0x1e2f +regCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 +regCP_ME1_PIPE3_INT_STATUS = 0x1e30 +regCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 +regCP_ME2_PIPE0_INT_STATUS = 0x1e31 +regCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 +regCP_ME2_PIPE1_INT_STATUS = 0x1e32 +regCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 +regCP_ME2_PIPE2_INT_STATUS = 0x1e33 +regCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 +regCP_ME2_PIPE3_INT_STATUS = 0x1e34 +regCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 +regCP_GFX_QUEUE_INDEX = 0x1e37 +regCP_GFX_QUEUE_INDEX_BASE_IDX = 0 +regCC_GC_EDC_CONFIG = 0x1e38 +regCC_GC_EDC_CONFIG_BASE_IDX = 0 +regCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 +regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 +regCP_ME1_PIPE0_PRIORITY = 0x1e3a +regCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 +regCP_ME1_PIPE1_PRIORITY = 0x1e3b +regCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 +regCP_ME1_PIPE2_PRIORITY = 0x1e3c +regCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 +regCP_ME1_PIPE3_PRIORITY = 0x1e3d +regCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 +regCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e +regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 +regCP_ME2_PIPE0_PRIORITY = 0x1e3f +regCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 +regCP_ME2_PIPE1_PRIORITY = 0x1e40 +regCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 +regCP_ME2_PIPE2_PRIORITY = 0x1e41 +regCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 +regCP_ME2_PIPE3_PRIORITY = 0x1e42 +regCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 +regCP_PFP_PRGRM_CNTR_START = 0x1e44 +regCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 +regCP_ME_PRGRM_CNTR_START = 0x1e45 +regCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 +regCP_MEC1_PRGRM_CNTR_START = 0x1e46 +regCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 +regCP_MEC2_PRGRM_CNTR_START = 0x1e47 +regCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 +regCP_PFP_INTR_ROUTINE_START = 0x1e49 +regCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 +regCP_ME_INTR_ROUTINE_START = 0x1e4a +regCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 +regCP_MEC1_INTR_ROUTINE_START = 0x1e4b +regCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 +regCP_MEC2_INTR_ROUTINE_START = 0x1e4c +regCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 +regCP_CONTEXT_CNTL = 0x1e4d +regCP_CONTEXT_CNTL_BASE_IDX = 0 +regCP_MAX_CONTEXT = 0x1e4e +regCP_MAX_CONTEXT_BASE_IDX = 0 +regCP_IQ_WAIT_TIME1 = 0x1e4f +regCP_IQ_WAIT_TIME1_BASE_IDX = 0 +regCP_IQ_WAIT_TIME2 = 0x1e50 +regCP_IQ_WAIT_TIME2_BASE_IDX = 0 +regCP_RB0_BASE_HI = 0x1e51 +regCP_RB0_BASE_HI_BASE_IDX = 0 +regCP_RB1_BASE_HI = 0x1e52 +regCP_RB1_BASE_HI_BASE_IDX = 0 +regCP_VMID_RESET = 0x1e53 +regCP_VMID_RESET_BASE_IDX = 0 +regCPC_INT_CNTL = 0x1e54 +regCPC_INT_CNTL_BASE_IDX = 0 +regCPC_INT_STATUS = 0x1e55 +regCPC_INT_STATUS_BASE_IDX = 0 +regCP_VMID_PREEMPT = 0x1e56 +regCP_VMID_PREEMPT_BASE_IDX = 0 +regCPC_INT_CNTX_ID = 0x1e57 +regCPC_INT_CNTX_ID_BASE_IDX = 0 +regCP_PQ_STATUS = 0x1e58 +regCP_PQ_STATUS_BASE_IDX = 0 +regCP_PFP_PRGRM_CNTR_START_HI = 0x1e59 +regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX = 0 +regCP_MAX_DRAW_COUNT = 0x1e5c +regCP_MAX_DRAW_COUNT_BASE_IDX = 0 +regCP_MEC1_F32_INT_DIS = 0x1e5d +regCP_MEC1_F32_INT_DIS_BASE_IDX = 0 +regCP_MEC2_F32_INT_DIS = 0x1e5e +regCP_MEC2_F32_INT_DIS_BASE_IDX = 0 +regCP_VMID_STATUS = 0x1e5f +regCP_VMID_STATUS_BASE_IDX = 0 +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 +regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 +regCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 +regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 +regCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 +regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 +regCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 +regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 +regCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 +regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 +regCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 +regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 +regCPC_OS_PIPES = 0x1e67 +regCPC_OS_PIPES_BASE_IDX = 0 +regCP_SUSPEND_RESUME_REQ = 0x1e68 +regCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 +regCP_SUSPEND_CNTL = 0x1e69 +regCP_SUSPEND_CNTL_BASE_IDX = 0 +regCP_IQ_WAIT_TIME3 = 0x1e6a +regCP_IQ_WAIT_TIME3_BASE_IDX = 0 +regCPC_DDID_BASE_ADDR_LO = 0x1e6b +regCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 +regCP_DDID_BASE_ADDR_LO = 0x1e6b +regCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 +regCPC_DDID_BASE_ADDR_HI = 0x1e6c +regCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 +regCP_DDID_BASE_ADDR_HI = 0x1e6c +regCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 +regCPC_DDID_CNTL = 0x1e6d +regCPC_DDID_CNTL_BASE_IDX = 0 +regCP_DDID_CNTL = 0x1e6d +regCP_DDID_CNTL_BASE_IDX = 0 +regCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e +regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 +regCP_GFX_DDID_WPTR = 0x1e6f +regCP_GFX_DDID_WPTR_BASE_IDX = 0 +regCP_GFX_DDID_RPTR = 0x1e70 +regCP_GFX_DDID_RPTR_BASE_IDX = 0 +regCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 +regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 +regCP_GFX_HPD_STATUS0 = 0x1e72 +regCP_GFX_HPD_STATUS0_BASE_IDX = 0 +regCP_GFX_HPD_CONTROL0 = 0x1e73 +regCP_GFX_HPD_CONTROL0_BASE_IDX = 0 +regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 +regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 +regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 +regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 +regCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 +regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 +regCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 +regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 +regCP_GFX_INDEX_MUTEX = 0x1e78 +regCP_GFX_INDEX_MUTEX_BASE_IDX = 0 +regCP_ME_PRGRM_CNTR_START_HI = 0x1e79 +regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX = 0 +regCP_PFP_INTR_ROUTINE_START_HI = 0x1e7a +regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX = 0 +regCP_ME_INTR_ROUTINE_START_HI = 0x1e7b +regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX = 0 +regCP_GFX_MQD_BASE_ADDR = 0x1e7e +regCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 +regCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f +regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 +regCP_GFX_HQD_ACTIVE = 0x1e80 +regCP_GFX_HQD_ACTIVE_BASE_IDX = 0 +regCP_GFX_HQD_VMID = 0x1e81 +regCP_GFX_HQD_VMID_BASE_IDX = 0 +regCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 +regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 +regCP_GFX_HQD_QUANTUM = 0x1e85 +regCP_GFX_HQD_QUANTUM_BASE_IDX = 0 +regCP_GFX_HQD_BASE = 0x1e86 +regCP_GFX_HQD_BASE_BASE_IDX = 0 +regCP_GFX_HQD_BASE_HI = 0x1e87 +regCP_GFX_HQD_BASE_HI_BASE_IDX = 0 +regCP_GFX_HQD_RPTR = 0x1e88 +regCP_GFX_HQD_RPTR_BASE_IDX = 0 +regCP_GFX_HQD_RPTR_ADDR = 0x1e89 +regCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 +regCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a +regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 +regCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b +regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 +regCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c +regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regCP_RB_DOORBELL_CONTROL = 0x1e8d +regCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 +regCP_GFX_HQD_OFFSET = 0x1e8e +regCP_GFX_HQD_OFFSET_BASE_IDX = 0 +regCP_GFX_HQD_CNTL = 0x1e8f +regCP_GFX_HQD_CNTL_BASE_IDX = 0 +regCP_GFX_HQD_CSMD_RPTR = 0x1e90 +regCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 +regCP_GFX_HQD_WPTR = 0x1e91 +regCP_GFX_HQD_WPTR_BASE_IDX = 0 +regCP_GFX_HQD_WPTR_HI = 0x1e92 +regCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 +regCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 +regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 +regCP_GFX_HQD_MAPPED = 0x1e94 +regCP_GFX_HQD_MAPPED_BASE_IDX = 0 +regCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 +regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 +regCP_GFX_HQD_IQ_TIMER = 0x1e96 +regCP_GFX_HQD_IQ_TIMER_BASE_IDX = 0 +regCP_GFX_HQD_HQ_STATUS0 = 0x1e98 +regCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 +regCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 +regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 +regCP_GFX_MQD_CONTROL = 0x1e9a +regCP_GFX_MQD_CONTROL_BASE_IDX = 0 +regCP_HQD_GFX_CONTROL = 0x1e9f +regCP_HQD_GFX_CONTROL_BASE_IDX = 0 +regCP_HQD_GFX_STATUS = 0x1ea0 +regCP_HQD_GFX_STATUS_BASE_IDX = 0 +regCP_DMA_WATCH0_ADDR_LO = 0x1ec0 +regCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 +regCP_DMA_WATCH0_ADDR_HI = 0x1ec1 +regCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 +regCP_DMA_WATCH0_MASK = 0x1ec2 +regCP_DMA_WATCH0_MASK_BASE_IDX = 0 +regCP_DMA_WATCH0_CNTL = 0x1ec3 +regCP_DMA_WATCH0_CNTL_BASE_IDX = 0 +regCP_DMA_WATCH1_ADDR_LO = 0x1ec4 +regCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 +regCP_DMA_WATCH1_ADDR_HI = 0x1ec5 +regCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 +regCP_DMA_WATCH1_MASK = 0x1ec6 +regCP_DMA_WATCH1_MASK_BASE_IDX = 0 +regCP_DMA_WATCH1_CNTL = 0x1ec7 +regCP_DMA_WATCH1_CNTL_BASE_IDX = 0 +regCP_DMA_WATCH2_ADDR_LO = 0x1ec8 +regCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 +regCP_DMA_WATCH2_ADDR_HI = 0x1ec9 +regCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 +regCP_DMA_WATCH2_MASK = 0x1eca +regCP_DMA_WATCH2_MASK_BASE_IDX = 0 +regCP_DMA_WATCH2_CNTL = 0x1ecb +regCP_DMA_WATCH2_CNTL_BASE_IDX = 0 +regCP_DMA_WATCH3_ADDR_LO = 0x1ecc +regCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 +regCP_DMA_WATCH3_ADDR_HI = 0x1ecd +regCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 +regCP_DMA_WATCH3_MASK = 0x1ece +regCP_DMA_WATCH3_MASK_BASE_IDX = 0 +regCP_DMA_WATCH3_CNTL = 0x1ecf +regCP_DMA_WATCH3_CNTL_BASE_IDX = 0 +regCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 +regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 +regCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 +regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 +regCP_DMA_WATCH_STAT = 0x1ed2 +regCP_DMA_WATCH_STAT_BASE_IDX = 0 +regCP_PFP_JT_STAT = 0x1ed3 +regCP_PFP_JT_STAT_BASE_IDX = 0 +regCP_MEC_JT_STAT = 0x1ed5 +regCP_MEC_JT_STAT_BASE_IDX = 0 +regCP_CPC_BUSY_HYSTERESIS = 0x1edb +regCP_CPC_BUSY_HYSTERESIS_BASE_IDX = 0 +regCP_CPF_BUSY_HYSTERESIS1 = 0x1edc +regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX = 0 +regCP_CPF_BUSY_HYSTERESIS2 = 0x1edd +regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX = 0 +regCP_CPG_BUSY_HYSTERESIS1 = 0x1ede +regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX = 0 +regCP_CPG_BUSY_HYSTERESIS2 = 0x1edf +regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX = 0 +regCP_RB_DOORBELL_CLEAR = 0x1f28 +regCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 +regCP_RB0_ACTIVE = 0x1f40 +regCP_RB0_ACTIVE_BASE_IDX = 0 +regCP_RB_ACTIVE = 0x1f40 +regCP_RB_ACTIVE_BASE_IDX = 0 +regCP_RB1_ACTIVE = 0x1f41 +regCP_RB1_ACTIVE_BASE_IDX = 0 +regCP_RB_STATUS = 0x1f43 +regCP_RB_STATUS_BASE_IDX = 0 +regCPG_RCIU_CAM_INDEX = 0x1f44 +regCPG_RCIU_CAM_INDEX_BASE_IDX = 0 +regCPG_RCIU_CAM_DATA = 0x1f45 +regCPG_RCIU_CAM_DATA_BASE_IDX = 0 +regCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 +regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 +regCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 +regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 +regCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 +regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 +regCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c +regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 +regCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d +regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 +regCP_SDMA_DMA_DONE = 0x1f4e +regCP_SDMA_DMA_DONE_BASE_IDX = 0 +regCP_PFP_SDMA_CS = 0x1f4f +regCP_PFP_SDMA_CS_BASE_IDX = 0 +regCP_ME_SDMA_CS = 0x1f50 +regCP_ME_SDMA_CS_BASE_IDX = 0 +regCPF_GCR_CNTL = 0x1f53 +regCPF_GCR_CNTL_BASE_IDX = 0 +regCPG_UTCL1_STATUS = 0x1f54 +regCPG_UTCL1_STATUS_BASE_IDX = 0 +regCPC_UTCL1_STATUS = 0x1f55 +regCPC_UTCL1_STATUS_BASE_IDX = 0 +regCPF_UTCL1_STATUS = 0x1f56 +regCPF_UTCL1_STATUS_BASE_IDX = 0 +regCP_SD_CNTL = 0x1f57 +regCP_SD_CNTL_BASE_IDX = 0 +regCP_SOFT_RESET_CNTL = 0x1f59 +regCP_SOFT_RESET_CNTL_BASE_IDX = 0 +regCP_CPC_GFX_CNTL = 0x1f5a +regCP_CPC_GFX_CNTL_BASE_IDX = 0 +regSPI_ARB_PRIORITY = 0x1f60 +regSPI_ARB_PRIORITY_BASE_IDX = 0 +regSPI_ARB_CYCLES_0 = 0x1f61 +regSPI_ARB_CYCLES_0_BASE_IDX = 0 +regSPI_ARB_CYCLES_1 = 0x1f62 +regSPI_ARB_CYCLES_1_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 +regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 +regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 +regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a +regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b +regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c +regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS4 = 0x1f6d +regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS5 = 0x1f6e +regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS6 = 0x1f6f +regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX = 0 +regSPI_WCL_PIPE_PERCENT_CS7 = 0x1f70 +regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX = 0 +regSPI_USER_ACCUM_VMID_CNTL = 0x1f71 +regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 +regSPI_GDBG_PER_VMID_CNTL = 0x1f72 +regSPI_GDBG_PER_VMID_CNTL_BASE_IDX = 0 +regSPI_COMPUTE_QUEUE_RESET = 0x1f73 +regSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 +regSPI_COMPUTE_WF_CTX_SAVE = 0x1f74 +regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 +regCP_HPD_UTCL1_CNTL = 0x1fa3 +regCP_HPD_UTCL1_CNTL_BASE_IDX = 0 +regCP_HPD_UTCL1_ERROR = 0x1fa7 +regCP_HPD_UTCL1_ERROR_BASE_IDX = 0 +regCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 +regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 +regCP_MQD_BASE_ADDR = 0x1fa9 +regCP_MQD_BASE_ADDR_BASE_IDX = 0 +regCP_MQD_BASE_ADDR_HI = 0x1faa +regCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 +regCP_HQD_ACTIVE = 0x1fab +regCP_HQD_ACTIVE_BASE_IDX = 0 +regCP_HQD_VMID = 0x1fac +regCP_HQD_VMID_BASE_IDX = 0 +regCP_HQD_PERSISTENT_STATE = 0x1fad +regCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 +regCP_HQD_PIPE_PRIORITY = 0x1fae +regCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 +regCP_HQD_QUEUE_PRIORITY = 0x1faf +regCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 +regCP_HQD_QUANTUM = 0x1fb0 +regCP_HQD_QUANTUM_BASE_IDX = 0 +regCP_HQD_PQ_BASE = 0x1fb1 +regCP_HQD_PQ_BASE_BASE_IDX = 0 +regCP_HQD_PQ_BASE_HI = 0x1fb2 +regCP_HQD_PQ_BASE_HI_BASE_IDX = 0 +regCP_HQD_PQ_RPTR = 0x1fb3 +regCP_HQD_PQ_RPTR_BASE_IDX = 0 +regCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 +regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 +regCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 +regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 +regCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 +regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 +regCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 +regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 +regCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 +regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 +regCP_HQD_PQ_CONTROL = 0x1fba +regCP_HQD_PQ_CONTROL_BASE_IDX = 0 +regCP_HQD_IB_BASE_ADDR = 0x1fbb +regCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 +regCP_HQD_IB_BASE_ADDR_HI = 0x1fbc +regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 +regCP_HQD_IB_RPTR = 0x1fbd +regCP_HQD_IB_RPTR_BASE_IDX = 0 +regCP_HQD_IB_CONTROL = 0x1fbe +regCP_HQD_IB_CONTROL_BASE_IDX = 0 +regCP_HQD_IQ_TIMER = 0x1fbf +regCP_HQD_IQ_TIMER_BASE_IDX = 0 +regCP_HQD_IQ_RPTR = 0x1fc0 +regCP_HQD_IQ_RPTR_BASE_IDX = 0 +regCP_HQD_DEQUEUE_REQUEST = 0x1fc1 +regCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 +regCP_HQD_DMA_OFFLOAD = 0x1fc2 +regCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 +regCP_HQD_OFFLOAD = 0x1fc2 +regCP_HQD_OFFLOAD_BASE_IDX = 0 +regCP_HQD_SEMA_CMD = 0x1fc3 +regCP_HQD_SEMA_CMD_BASE_IDX = 0 +regCP_HQD_MSG_TYPE = 0x1fc4 +regCP_HQD_MSG_TYPE_BASE_IDX = 0 +regCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 +regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 +regCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 +regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 +regCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 +regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 +regCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 +regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 +regCP_HQD_HQ_SCHEDULER0 = 0x1fc9 +regCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 +regCP_HQD_HQ_STATUS0 = 0x1fc9 +regCP_HQD_HQ_STATUS0_BASE_IDX = 0 +regCP_HQD_HQ_CONTROL0 = 0x1fca +regCP_HQD_HQ_CONTROL0_BASE_IDX = 0 +regCP_HQD_HQ_SCHEDULER1 = 0x1fca +regCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 +regCP_MQD_CONTROL = 0x1fcb +regCP_MQD_CONTROL_BASE_IDX = 0 +regCP_HQD_HQ_STATUS1 = 0x1fcc +regCP_HQD_HQ_STATUS1_BASE_IDX = 0 +regCP_HQD_HQ_CONTROL1 = 0x1fcd +regCP_HQD_HQ_CONTROL1_BASE_IDX = 0 +regCP_HQD_EOP_BASE_ADDR = 0x1fce +regCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 +regCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf +regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 +regCP_HQD_EOP_CONTROL = 0x1fd0 +regCP_HQD_EOP_CONTROL_BASE_IDX = 0 +regCP_HQD_EOP_RPTR = 0x1fd1 +regCP_HQD_EOP_RPTR_BASE_IDX = 0 +regCP_HQD_EOP_WPTR = 0x1fd2 +regCP_HQD_EOP_WPTR_BASE_IDX = 0 +regCP_HQD_EOP_EVENTS = 0x1fd3 +regCP_HQD_EOP_EVENTS_BASE_IDX = 0 +regCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 +regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 +regCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 +regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 +regCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 +regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 +regCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 +regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 +regCP_HQD_CNTL_STACK_SIZE = 0x1fd8 +regCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 +regCP_HQD_WG_STATE_OFFSET = 0x1fd9 +regCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 +regCP_HQD_CTX_SAVE_SIZE = 0x1fda +regCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 +regCP_HQD_GDS_RESOURCE_STATE = 0x1fdb +regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 +regCP_HQD_ERROR = 0x1fdc +regCP_HQD_ERROR_BASE_IDX = 0 +regCP_HQD_EOP_WPTR_MEM = 0x1fdd +regCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 +regCP_HQD_AQL_CONTROL = 0x1fde +regCP_HQD_AQL_CONTROL_BASE_IDX = 0 +regCP_HQD_PQ_WPTR_LO = 0x1fdf +regCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 +regCP_HQD_PQ_WPTR_HI = 0x1fe0 +regCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 +regCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 +regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 +regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 +regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 +regCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 +regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 +regCP_HQD_DDID_RPTR = 0x1fe4 +regCP_HQD_DDID_RPTR_BASE_IDX = 0 +regCP_HQD_DDID_WPTR = 0x1fe5 +regCP_HQD_DDID_WPTR_BASE_IDX = 0 +regCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 +regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 +regCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 +regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 +regCP_HQD_DEQUEUE_STATUS = 0x1fe8 +regCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 +regTCP_WATCH0_ADDR_H = 0x2048 +regTCP_WATCH0_ADDR_H_BASE_IDX = 0 +regTCP_WATCH0_ADDR_L = 0x2049 +regTCP_WATCH0_ADDR_L_BASE_IDX = 0 +regTCP_WATCH0_CNTL = 0x204a +regTCP_WATCH0_CNTL_BASE_IDX = 0 +regTCP_WATCH1_ADDR_H = 0x204b +regTCP_WATCH1_ADDR_H_BASE_IDX = 0 +regTCP_WATCH1_ADDR_L = 0x204c +regTCP_WATCH1_ADDR_L_BASE_IDX = 0 +regTCP_WATCH1_CNTL = 0x204d +regTCP_WATCH1_CNTL_BASE_IDX = 0 +regTCP_WATCH2_ADDR_H = 0x204e +regTCP_WATCH2_ADDR_H_BASE_IDX = 0 +regTCP_WATCH2_ADDR_L = 0x204f +regTCP_WATCH2_ADDR_L_BASE_IDX = 0 +regTCP_WATCH2_CNTL = 0x2050 +regTCP_WATCH2_CNTL_BASE_IDX = 0 +regTCP_WATCH3_ADDR_H = 0x2051 +regTCP_WATCH3_ADDR_H_BASE_IDX = 0 +regTCP_WATCH3_ADDR_L = 0x2052 +regTCP_WATCH3_ADDR_L_BASE_IDX = 0 +regTCP_WATCH3_CNTL = 0x2053 +regTCP_WATCH3_CNTL_BASE_IDX = 0 +regGDS_VMID0_BASE = 0x20a0 +regGDS_VMID0_BASE_BASE_IDX = 0 +regGDS_VMID0_SIZE = 0x20a1 +regGDS_VMID0_SIZE_BASE_IDX = 0 +regGDS_VMID1_BASE = 0x20a2 +regGDS_VMID1_BASE_BASE_IDX = 0 +regGDS_VMID1_SIZE = 0x20a3 +regGDS_VMID1_SIZE_BASE_IDX = 0 +regGDS_VMID2_BASE = 0x20a4 +regGDS_VMID2_BASE_BASE_IDX = 0 +regGDS_VMID2_SIZE = 0x20a5 +regGDS_VMID2_SIZE_BASE_IDX = 0 +regGDS_VMID3_BASE = 0x20a6 +regGDS_VMID3_BASE_BASE_IDX = 0 +regGDS_VMID3_SIZE = 0x20a7 +regGDS_VMID3_SIZE_BASE_IDX = 0 +regGDS_VMID4_BASE = 0x20a8 +regGDS_VMID4_BASE_BASE_IDX = 0 +regGDS_VMID4_SIZE = 0x20a9 +regGDS_VMID4_SIZE_BASE_IDX = 0 +regGDS_VMID5_BASE = 0x20aa +regGDS_VMID5_BASE_BASE_IDX = 0 +regGDS_VMID5_SIZE = 0x20ab +regGDS_VMID5_SIZE_BASE_IDX = 0 +regGDS_VMID6_BASE = 0x20ac +regGDS_VMID6_BASE_BASE_IDX = 0 +regGDS_VMID6_SIZE = 0x20ad +regGDS_VMID6_SIZE_BASE_IDX = 0 +regGDS_VMID7_BASE = 0x20ae +regGDS_VMID7_BASE_BASE_IDX = 0 +regGDS_VMID7_SIZE = 0x20af +regGDS_VMID7_SIZE_BASE_IDX = 0 +regGDS_VMID8_BASE = 0x20b0 +regGDS_VMID8_BASE_BASE_IDX = 0 +regGDS_VMID8_SIZE = 0x20b1 +regGDS_VMID8_SIZE_BASE_IDX = 0 +regGDS_VMID9_BASE = 0x20b2 +regGDS_VMID9_BASE_BASE_IDX = 0 +regGDS_VMID9_SIZE = 0x20b3 +regGDS_VMID9_SIZE_BASE_IDX = 0 +regGDS_VMID10_BASE = 0x20b4 +regGDS_VMID10_BASE_BASE_IDX = 0 +regGDS_VMID10_SIZE = 0x20b5 +regGDS_VMID10_SIZE_BASE_IDX = 0 +regGDS_VMID11_BASE = 0x20b6 +regGDS_VMID11_BASE_BASE_IDX = 0 +regGDS_VMID11_SIZE = 0x20b7 +regGDS_VMID11_SIZE_BASE_IDX = 0 +regGDS_VMID12_BASE = 0x20b8 +regGDS_VMID12_BASE_BASE_IDX = 0 +regGDS_VMID12_SIZE = 0x20b9 +regGDS_VMID12_SIZE_BASE_IDX = 0 +regGDS_VMID13_BASE = 0x20ba +regGDS_VMID13_BASE_BASE_IDX = 0 +regGDS_VMID13_SIZE = 0x20bb +regGDS_VMID13_SIZE_BASE_IDX = 0 +regGDS_VMID14_BASE = 0x20bc +regGDS_VMID14_BASE_BASE_IDX = 0 +regGDS_VMID14_SIZE = 0x20bd +regGDS_VMID14_SIZE_BASE_IDX = 0 +regGDS_VMID15_BASE = 0x20be +regGDS_VMID15_BASE_BASE_IDX = 0 +regGDS_VMID15_SIZE = 0x20bf +regGDS_VMID15_SIZE_BASE_IDX = 0 +regGDS_GWS_VMID0 = 0x20c0 +regGDS_GWS_VMID0_BASE_IDX = 0 +regGDS_GWS_VMID1 = 0x20c1 +regGDS_GWS_VMID1_BASE_IDX = 0 +regGDS_GWS_VMID2 = 0x20c2 +regGDS_GWS_VMID2_BASE_IDX = 0 +regGDS_GWS_VMID3 = 0x20c3 +regGDS_GWS_VMID3_BASE_IDX = 0 +regGDS_GWS_VMID4 = 0x20c4 +regGDS_GWS_VMID4_BASE_IDX = 0 +regGDS_GWS_VMID5 = 0x20c5 +regGDS_GWS_VMID5_BASE_IDX = 0 +regGDS_GWS_VMID6 = 0x20c6 +regGDS_GWS_VMID6_BASE_IDX = 0 +regGDS_GWS_VMID7 = 0x20c7 +regGDS_GWS_VMID7_BASE_IDX = 0 +regGDS_GWS_VMID8 = 0x20c8 +regGDS_GWS_VMID8_BASE_IDX = 0 +regGDS_GWS_VMID9 = 0x20c9 +regGDS_GWS_VMID9_BASE_IDX = 0 +regGDS_GWS_VMID10 = 0x20ca +regGDS_GWS_VMID10_BASE_IDX = 0 +regGDS_GWS_VMID11 = 0x20cb +regGDS_GWS_VMID11_BASE_IDX = 0 +regGDS_GWS_VMID12 = 0x20cc +regGDS_GWS_VMID12_BASE_IDX = 0 +regGDS_GWS_VMID13 = 0x20cd +regGDS_GWS_VMID13_BASE_IDX = 0 +regGDS_GWS_VMID14 = 0x20ce +regGDS_GWS_VMID14_BASE_IDX = 0 +regGDS_GWS_VMID15 = 0x20cf +regGDS_GWS_VMID15_BASE_IDX = 0 +regGDS_OA_VMID0 = 0x20d0 +regGDS_OA_VMID0_BASE_IDX = 0 +regGDS_OA_VMID1 = 0x20d1 +regGDS_OA_VMID1_BASE_IDX = 0 +regGDS_OA_VMID2 = 0x20d2 +regGDS_OA_VMID2_BASE_IDX = 0 +regGDS_OA_VMID3 = 0x20d3 +regGDS_OA_VMID3_BASE_IDX = 0 +regGDS_OA_VMID4 = 0x20d4 +regGDS_OA_VMID4_BASE_IDX = 0 +regGDS_OA_VMID5 = 0x20d5 +regGDS_OA_VMID5_BASE_IDX = 0 +regGDS_OA_VMID6 = 0x20d6 +regGDS_OA_VMID6_BASE_IDX = 0 +regGDS_OA_VMID7 = 0x20d7 +regGDS_OA_VMID7_BASE_IDX = 0 +regGDS_OA_VMID8 = 0x20d8 +regGDS_OA_VMID8_BASE_IDX = 0 +regGDS_OA_VMID9 = 0x20d9 +regGDS_OA_VMID9_BASE_IDX = 0 +regGDS_OA_VMID10 = 0x20da +regGDS_OA_VMID10_BASE_IDX = 0 +regGDS_OA_VMID11 = 0x20db +regGDS_OA_VMID11_BASE_IDX = 0 +regGDS_OA_VMID12 = 0x20dc +regGDS_OA_VMID12_BASE_IDX = 0 +regGDS_OA_VMID13 = 0x20dd +regGDS_OA_VMID13_BASE_IDX = 0 +regGDS_OA_VMID14 = 0x20de +regGDS_OA_VMID14_BASE_IDX = 0 +regGDS_OA_VMID15 = 0x20df +regGDS_OA_VMID15_BASE_IDX = 0 +regGDS_GWS_RESET0 = 0x20e4 +regGDS_GWS_RESET0_BASE_IDX = 0 +regGDS_GWS_RESET1 = 0x20e5 +regGDS_GWS_RESET1_BASE_IDX = 0 +regGDS_GWS_RESOURCE_RESET = 0x20e6 +regGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 +regGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 +regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 +regGDS_OA_RESET_MASK = 0x20e9 +regGDS_OA_RESET_MASK_BASE_IDX = 0 +regGDS_OA_RESET = 0x20ea +regGDS_OA_RESET_BASE_IDX = 0 +regGDS_CS_CTXSW_STATUS = 0x20ed +regGDS_CS_CTXSW_STATUS_BASE_IDX = 0 +regGDS_CS_CTXSW_CNT0 = 0x20ee +regGDS_CS_CTXSW_CNT0_BASE_IDX = 0 +regGDS_CS_CTXSW_CNT1 = 0x20ef +regGDS_CS_CTXSW_CNT1_BASE_IDX = 0 +regGDS_CS_CTXSW_CNT2 = 0x20f0 +regGDS_CS_CTXSW_CNT2_BASE_IDX = 0 +regGDS_CS_CTXSW_CNT3 = 0x20f1 +regGDS_CS_CTXSW_CNT3_BASE_IDX = 0 +regGDS_GFX_CTXSW_STATUS = 0x20f2 +regGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 +regGDS_PS_CTXSW_CNT0 = 0x20f7 +regGDS_PS_CTXSW_CNT0_BASE_IDX = 0 +regGDS_PS_CTXSW_CNT1 = 0x20f8 +regGDS_PS_CTXSW_CNT1_BASE_IDX = 0 +regGDS_PS_CTXSW_CNT2 = 0x20f9 +regGDS_PS_CTXSW_CNT2_BASE_IDX = 0 +regGDS_PS_CTXSW_CNT3 = 0x20fa +regGDS_PS_CTXSW_CNT3_BASE_IDX = 0 +regGDS_PS_CTXSW_IDX = 0x20fb +regGDS_PS_CTXSW_IDX_BASE_IDX = 0 +regGDS_GS_CTXSW_CNT0 = 0x2117 +regGDS_GS_CTXSW_CNT0_BASE_IDX = 0 +regGDS_GS_CTXSW_CNT1 = 0x2118 +regGDS_GS_CTXSW_CNT1_BASE_IDX = 0 +regGDS_GS_CTXSW_CNT2 = 0x2119 +regGDS_GS_CTXSW_CNT2_BASE_IDX = 0 +regGDS_GS_CTXSW_CNT3 = 0x211a +regGDS_GS_CTXSW_CNT3_BASE_IDX = 0 +regGDS_MEMORY_CLEAN = 0x211f +regGDS_MEMORY_CLEAN_BASE_IDX = 0 +regGUS_IO_RD_COMBINE_FLUSH = 0x2c00 +regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 +regGUS_IO_WR_COMBINE_FLUSH = 0x2c01 +regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 +regGUS_IO_RD_PRI_AGE_RATE = 0x2c02 +regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 +regGUS_IO_WR_PRI_AGE_RATE = 0x2c03 +regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 +regGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 +regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 +regGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 +regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUEUING = 0x2c06 +regGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUEUING = 0x2c07 +regGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 +regGUS_IO_RD_PRI_FIXED = 0x2c08 +regGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 +regGUS_IO_WR_PRI_FIXED = 0x2c09 +regGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 +regGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a +regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 +regGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b +regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 +regGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c +regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 +regGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d +regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e +regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f +regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 +regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 +regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 +regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 +regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 +regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 +regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 +regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 +regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 +regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 +regGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 +regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a +regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b +regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c +regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 +regGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d +regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 +regGUS_DRAM_COMBINE_FLUSH = 0x2c1e +regGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 +regGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f +regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 +regGUS_DRAM_PRI_AGE_RATE = 0x2c20 +regGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 +regGUS_DRAM_PRI_AGE_COEFF = 0x2c21 +regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 +regGUS_DRAM_PRI_QUEUING = 0x2c22 +regGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 +regGUS_DRAM_PRI_FIXED = 0x2c23 +regGUS_DRAM_PRI_FIXED_BASE_IDX = 1 +regGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 +regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 +regGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 +regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 +regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 +regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 +regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 +regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a +regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b +regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c +regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d +regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e +regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 +regGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f +regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 +regGUS_IO_GROUP_BURST = 0x2c30 +regGUS_IO_GROUP_BURST_BASE_IDX = 1 +regGUS_DRAM_GROUP_BURST = 0x2c31 +regGUS_DRAM_GROUP_BURST_BASE_IDX = 1 +regGUS_SDP_ARB_FINAL = 0x2c32 +regGUS_SDP_ARB_FINAL_BASE_IDX = 1 +regGUS_SDP_QOS_VC_PRIORITY = 0x2c33 +regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 +regGUS_SDP_CREDITS = 0x2c34 +regGUS_SDP_CREDITS_BASE_IDX = 1 +regGUS_SDP_TAG_RESERVE0 = 0x2c35 +regGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 +regGUS_SDP_TAG_RESERVE1 = 0x2c36 +regGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 +regGUS_SDP_VCC_RESERVE0 = 0x2c37 +regGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 +regGUS_SDP_VCC_RESERVE1 = 0x2c38 +regGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 +regGUS_SDP_VCD_RESERVE0 = 0x2c39 +regGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 +regGUS_SDP_VCD_RESERVE1 = 0x2c3a +regGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 +regGUS_SDP_REQ_CNTL = 0x2c3b +regGUS_SDP_REQ_CNTL_BASE_IDX = 1 +regGUS_MISC = 0x2c3c +regGUS_MISC_BASE_IDX = 1 +regGUS_LATENCY_SAMPLING = 0x2c3d +regGUS_LATENCY_SAMPLING_BASE_IDX = 1 +regGUS_ERR_STATUS = 0x2c3e +regGUS_ERR_STATUS_BASE_IDX = 1 +regGUS_MISC2 = 0x2c3f +regGUS_MISC2_BASE_IDX = 1 +regGUS_SDP_ENABLE = 0x2c45 +regGUS_SDP_ENABLE_BASE_IDX = 1 +regGUS_L1_CH0_CMD_IN = 0x2c46 +regGUS_L1_CH0_CMD_IN_BASE_IDX = 1 +regGUS_L1_CH0_CMD_OUT = 0x2c47 +regGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 +regGUS_L1_CH0_DATA_IN = 0x2c48 +regGUS_L1_CH0_DATA_IN_BASE_IDX = 1 +regGUS_L1_CH0_DATA_OUT = 0x2c49 +regGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 +regGUS_L1_CH0_DATA_U_IN = 0x2c4a +regGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 +regGUS_L1_CH0_DATA_U_OUT = 0x2c4b +regGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 +regGUS_L1_CH1_CMD_IN = 0x2c4c +regGUS_L1_CH1_CMD_IN_BASE_IDX = 1 +regGUS_L1_CH1_CMD_OUT = 0x2c4d +regGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 +regGUS_L1_CH1_DATA_IN = 0x2c4e +regGUS_L1_CH1_DATA_IN_BASE_IDX = 1 +regGUS_L1_CH1_DATA_OUT = 0x2c4f +regGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 +regGUS_L1_CH1_DATA_U_IN = 0x2c50 +regGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 +regGUS_L1_CH1_DATA_U_OUT = 0x2c51 +regGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 +regGUS_L1_SA0_CMD_IN = 0x2c52 +regGUS_L1_SA0_CMD_IN_BASE_IDX = 1 +regGUS_L1_SA0_CMD_OUT = 0x2c53 +regGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 +regGUS_L1_SA0_DATA_IN = 0x2c54 +regGUS_L1_SA0_DATA_IN_BASE_IDX = 1 +regGUS_L1_SA0_DATA_OUT = 0x2c55 +regGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 +regGUS_L1_SA0_DATA_U_IN = 0x2c56 +regGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 +regGUS_L1_SA0_DATA_U_OUT = 0x2c57 +regGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 +regGUS_L1_SA1_CMD_IN = 0x2c58 +regGUS_L1_SA1_CMD_IN_BASE_IDX = 1 +regGUS_L1_SA1_CMD_OUT = 0x2c59 +regGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 +regGUS_L1_SA1_DATA_IN = 0x2c5a +regGUS_L1_SA1_DATA_IN_BASE_IDX = 1 +regGUS_L1_SA1_DATA_OUT = 0x2c5b +regGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 +regGUS_L1_SA1_DATA_U_IN = 0x2c5c +regGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 +regGUS_L1_SA1_DATA_U_OUT = 0x2c5d +regGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 +regGUS_L1_SA2_CMD_IN = 0x2c5e +regGUS_L1_SA2_CMD_IN_BASE_IDX = 1 +regGUS_L1_SA2_CMD_OUT = 0x2c5f +regGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 +regGUS_L1_SA2_DATA_IN = 0x2c60 +regGUS_L1_SA2_DATA_IN_BASE_IDX = 1 +regGUS_L1_SA2_DATA_OUT = 0x2c61 +regGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 +regGUS_L1_SA2_DATA_U_IN = 0x2c62 +regGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 +regGUS_L1_SA2_DATA_U_OUT = 0x2c63 +regGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 +regGUS_L1_SA3_CMD_IN = 0x2c64 +regGUS_L1_SA3_CMD_IN_BASE_IDX = 1 +regGUS_L1_SA3_CMD_OUT = 0x2c65 +regGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 +regGUS_L1_SA3_DATA_IN = 0x2c66 +regGUS_L1_SA3_DATA_IN_BASE_IDX = 1 +regGUS_L1_SA3_DATA_OUT = 0x2c67 +regGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 +regGUS_L1_SA3_DATA_U_IN = 0x2c68 +regGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 +regGUS_L1_SA3_DATA_U_OUT = 0x2c69 +regGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 +regGUS_MISC3 = 0x2c6a +regGUS_MISC3_BASE_IDX = 1 +regGUS_WRRSP_FIFO_CNTL = 0x2c6b +regGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 +regDB_RENDER_CONTROL = 0x0000 +regDB_RENDER_CONTROL_BASE_IDX = 1 +regDB_COUNT_CONTROL = 0x0001 +regDB_COUNT_CONTROL_BASE_IDX = 1 +regDB_DEPTH_VIEW = 0x0002 +regDB_DEPTH_VIEW_BASE_IDX = 1 +regDB_RENDER_OVERRIDE = 0x0003 +regDB_RENDER_OVERRIDE_BASE_IDX = 1 +regDB_RENDER_OVERRIDE2 = 0x0004 +regDB_RENDER_OVERRIDE2_BASE_IDX = 1 +regDB_HTILE_DATA_BASE = 0x0005 +regDB_HTILE_DATA_BASE_BASE_IDX = 1 +regDB_DEPTH_SIZE_XY = 0x0007 +regDB_DEPTH_SIZE_XY_BASE_IDX = 1 +regDB_DEPTH_BOUNDS_MIN = 0x0008 +regDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 +regDB_DEPTH_BOUNDS_MAX = 0x0009 +regDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 +regDB_STENCIL_CLEAR = 0x000a +regDB_STENCIL_CLEAR_BASE_IDX = 1 +regDB_DEPTH_CLEAR = 0x000b +regDB_DEPTH_CLEAR_BASE_IDX = 1 +regPA_SC_SCREEN_SCISSOR_TL = 0x000c +regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 +regPA_SC_SCREEN_SCISSOR_BR = 0x000d +regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 +regDB_RESERVED_REG_2 = 0x000f +regDB_RESERVED_REG_2_BASE_IDX = 1 +regDB_Z_INFO = 0x0010 +regDB_Z_INFO_BASE_IDX = 1 +regDB_STENCIL_INFO = 0x0011 +regDB_STENCIL_INFO_BASE_IDX = 1 +regDB_Z_READ_BASE = 0x0012 +regDB_Z_READ_BASE_BASE_IDX = 1 +regDB_STENCIL_READ_BASE = 0x0013 +regDB_STENCIL_READ_BASE_BASE_IDX = 1 +regDB_Z_WRITE_BASE = 0x0014 +regDB_Z_WRITE_BASE_BASE_IDX = 1 +regDB_STENCIL_WRITE_BASE = 0x0015 +regDB_STENCIL_WRITE_BASE_BASE_IDX = 1 +regDB_RESERVED_REG_1 = 0x0016 +regDB_RESERVED_REG_1_BASE_IDX = 1 +regDB_RESERVED_REG_3 = 0x0017 +regDB_RESERVED_REG_3_BASE_IDX = 1 +regDB_Z_READ_BASE_HI = 0x001a +regDB_Z_READ_BASE_HI_BASE_IDX = 1 +regDB_STENCIL_READ_BASE_HI = 0x001b +regDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 +regDB_Z_WRITE_BASE_HI = 0x001c +regDB_Z_WRITE_BASE_HI_BASE_IDX = 1 +regDB_STENCIL_WRITE_BASE_HI = 0x001d +regDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 +regDB_HTILE_DATA_BASE_HI = 0x001e +regDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 +regDB_RMI_L2_CACHE_CONTROL = 0x001f +regDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 +regTA_BC_BASE_ADDR = 0x0020 +regTA_BC_BASE_ADDR_BASE_IDX = 1 +regTA_BC_BASE_ADDR_HI = 0x0021 +regTA_BC_BASE_ADDR_HI_BASE_IDX = 1 +regCOHER_DEST_BASE_HI_0 = 0x007a +regCOHER_DEST_BASE_HI_0_BASE_IDX = 1 +regCOHER_DEST_BASE_HI_1 = 0x007b +regCOHER_DEST_BASE_HI_1_BASE_IDX = 1 +regCOHER_DEST_BASE_HI_2 = 0x007c +regCOHER_DEST_BASE_HI_2_BASE_IDX = 1 +regCOHER_DEST_BASE_HI_3 = 0x007d +regCOHER_DEST_BASE_HI_3_BASE_IDX = 1 +regCOHER_DEST_BASE_2 = 0x007e +regCOHER_DEST_BASE_2_BASE_IDX = 1 +regCOHER_DEST_BASE_3 = 0x007f +regCOHER_DEST_BASE_3_BASE_IDX = 1 +regPA_SC_WINDOW_OFFSET = 0x0080 +regPA_SC_WINDOW_OFFSET_BASE_IDX = 1 +regPA_SC_WINDOW_SCISSOR_TL = 0x0081 +regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 +regPA_SC_WINDOW_SCISSOR_BR = 0x0082 +regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 +regPA_SC_CLIPRECT_RULE = 0x0083 +regPA_SC_CLIPRECT_RULE_BASE_IDX = 1 +regPA_SC_CLIPRECT_0_TL = 0x0084 +regPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 +regPA_SC_CLIPRECT_0_BR = 0x0085 +regPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 +regPA_SC_CLIPRECT_1_TL = 0x0086 +regPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 +regPA_SC_CLIPRECT_1_BR = 0x0087 +regPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 +regPA_SC_CLIPRECT_2_TL = 0x0088 +regPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 +regPA_SC_CLIPRECT_2_BR = 0x0089 +regPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 +regPA_SC_CLIPRECT_3_TL = 0x008a +regPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 +regPA_SC_CLIPRECT_3_BR = 0x008b +regPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 +regPA_SC_EDGERULE = 0x008c +regPA_SC_EDGERULE_BASE_IDX = 1 +regPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d +regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 +regCB_TARGET_MASK = 0x008e +regCB_TARGET_MASK_BASE_IDX = 1 +regCB_SHADER_MASK = 0x008f +regCB_SHADER_MASK_BASE_IDX = 1 +regPA_SC_GENERIC_SCISSOR_TL = 0x0090 +regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 +regPA_SC_GENERIC_SCISSOR_BR = 0x0091 +regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 +regCOHER_DEST_BASE_0 = 0x0092 +regCOHER_DEST_BASE_0_BASE_IDX = 1 +regCOHER_DEST_BASE_1 = 0x0093 +regCOHER_DEST_BASE_1_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_0_TL = 0x0094 +regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_0_BR = 0x0095 +regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_1_TL = 0x0096 +regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_1_BR = 0x0097 +regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_2_TL = 0x0098 +regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_2_BR = 0x0099 +regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_3_TL = 0x009a +regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_3_BR = 0x009b +regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_4_TL = 0x009c +regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_4_BR = 0x009d +regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_5_TL = 0x009e +regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_5_BR = 0x009f +regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 +regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 +regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 +regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 +regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 +regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 +regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 +regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 +regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 +regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 +regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_11_TL = 0x00aa +regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_11_BR = 0x00ab +regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_12_TL = 0x00ac +regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_12_BR = 0x00ad +regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_13_TL = 0x00ae +regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_13_BR = 0x00af +regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 +regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 +regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 +regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 +regPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 +regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_0 = 0x00b4 +regPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_0 = 0x00b5 +regPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_1 = 0x00b6 +regPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_1 = 0x00b7 +regPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_2 = 0x00b8 +regPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_2 = 0x00b9 +regPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_3 = 0x00ba +regPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_3 = 0x00bb +regPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_4 = 0x00bc +regPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_4 = 0x00bd +regPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_5 = 0x00be +regPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_5 = 0x00bf +regPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_6 = 0x00c0 +regPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_6 = 0x00c1 +regPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_7 = 0x00c2 +regPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_7 = 0x00c3 +regPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_8 = 0x00c4 +regPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_8 = 0x00c5 +regPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_9 = 0x00c6 +regPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_9 = 0x00c7 +regPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_10 = 0x00c8 +regPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_10 = 0x00c9 +regPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_11 = 0x00ca +regPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_11 = 0x00cb +regPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_12 = 0x00cc +regPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_12 = 0x00cd +regPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_13 = 0x00ce +regPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_13 = 0x00cf +regPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_14 = 0x00d0 +regPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_14 = 0x00d1 +regPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 +regPA_SC_VPORT_ZMIN_15 = 0x00d2 +regPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 +regPA_SC_VPORT_ZMAX_15 = 0x00d3 +regPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 +regPA_SC_RASTER_CONFIG = 0x00d4 +regPA_SC_RASTER_CONFIG_BASE_IDX = 1 +regPA_SC_RASTER_CONFIG_1 = 0x00d5 +regPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 +regPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 +regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 +regPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 +regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 +regCP_PERFMON_CNTX_CNTL = 0x00d8 +regCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 +regCP_PIPEID = 0x00d9 +regCP_PIPEID_BASE_IDX = 1 +regCP_RINGID = 0x00d9 +regCP_RINGID_BASE_IDX = 1 +regCP_VMID = 0x00da +regCP_VMID_BASE_IDX = 1 +regCONTEXT_RESERVED_REG0 = 0x00db +regCONTEXT_RESERVED_REG0_BASE_IDX = 1 +regCONTEXT_RESERVED_REG1 = 0x00dc +regCONTEXT_RESERVED_REG1_BASE_IDX = 1 +regPA_SC_VRS_OVERRIDE_CNTL = 0x00f4 +regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX = 1 +regPA_SC_VRS_RATE_FEEDBACK_BASE = 0x00f5 +regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX = 1 +regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT = 0x00f6 +regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX = 1 +regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY = 0x00f7 +regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX = 1 +regPA_SC_VRS_RATE_CACHE_CNTL = 0x00f9 +regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX = 1 +regPA_SC_VRS_RATE_BASE = 0x00fc +regPA_SC_VRS_RATE_BASE_BASE_IDX = 1 +regPA_SC_VRS_RATE_BASE_EXT = 0x00fd +regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX = 1 +regPA_SC_VRS_RATE_SIZE_XY = 0x00fe +regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX = 1 +regVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 +regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 +regCB_RMI_GL2_CACHE_CONTROL = 0x0104 +regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 +regCB_BLEND_RED = 0x0105 +regCB_BLEND_RED_BASE_IDX = 1 +regCB_BLEND_GREEN = 0x0106 +regCB_BLEND_GREEN_BASE_IDX = 1 +regCB_BLEND_BLUE = 0x0107 +regCB_BLEND_BLUE_BASE_IDX = 1 +regCB_BLEND_ALPHA = 0x0108 +regCB_BLEND_ALPHA_BASE_IDX = 1 +regCB_FDCC_CONTROL = 0x0109 +regCB_FDCC_CONTROL_BASE_IDX = 1 +regCB_COVERAGE_OUT_CONTROL = 0x010a +regCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 +regDB_STENCIL_CONTROL = 0x010b +regDB_STENCIL_CONTROL_BASE_IDX = 1 +regDB_STENCILREFMASK = 0x010c +regDB_STENCILREFMASK_BASE_IDX = 1 +regDB_STENCILREFMASK_BF = 0x010d +regDB_STENCILREFMASK_BF_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE = 0x010f +regPA_CL_VPORT_XSCALE_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET = 0x0110 +regPA_CL_VPORT_XOFFSET_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE = 0x0111 +regPA_CL_VPORT_YSCALE_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET = 0x0112 +regPA_CL_VPORT_YOFFSET_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE = 0x0113 +regPA_CL_VPORT_ZSCALE_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET = 0x0114 +regPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_1 = 0x0115 +regPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_1 = 0x0116 +regPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_1 = 0x0117 +regPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_1 = 0x0118 +regPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_1 = 0x0119 +regPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_1 = 0x011a +regPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_2 = 0x011b +regPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_2 = 0x011c +regPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_2 = 0x011d +regPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_2 = 0x011e +regPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_2 = 0x011f +regPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_2 = 0x0120 +regPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_3 = 0x0121 +regPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_3 = 0x0122 +regPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_3 = 0x0123 +regPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_3 = 0x0124 +regPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_3 = 0x0125 +regPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_3 = 0x0126 +regPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_4 = 0x0127 +regPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_4 = 0x0128 +regPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_4 = 0x0129 +regPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_4 = 0x012a +regPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_4 = 0x012b +regPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_4 = 0x012c +regPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_5 = 0x012d +regPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_5 = 0x012e +regPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_5 = 0x012f +regPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_5 = 0x0130 +regPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_5 = 0x0131 +regPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_5 = 0x0132 +regPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_6 = 0x0133 +regPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_6 = 0x0134 +regPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_6 = 0x0135 +regPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_6 = 0x0136 +regPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_6 = 0x0137 +regPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_6 = 0x0138 +regPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_7 = 0x0139 +regPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_7 = 0x013a +regPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_7 = 0x013b +regPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_7 = 0x013c +regPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_7 = 0x013d +regPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_7 = 0x013e +regPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_8 = 0x013f +regPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_8 = 0x0140 +regPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_8 = 0x0141 +regPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_8 = 0x0142 +regPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_8 = 0x0143 +regPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_8 = 0x0144 +regPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_9 = 0x0145 +regPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_9 = 0x0146 +regPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_9 = 0x0147 +regPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_9 = 0x0148 +regPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_9 = 0x0149 +regPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_9 = 0x014a +regPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_10 = 0x014b +regPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_10 = 0x014c +regPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_10 = 0x014d +regPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_10 = 0x014e +regPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_10 = 0x014f +regPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_10 = 0x0150 +regPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_11 = 0x0151 +regPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_11 = 0x0152 +regPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_11 = 0x0153 +regPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_11 = 0x0154 +regPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_11 = 0x0155 +regPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_11 = 0x0156 +regPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_12 = 0x0157 +regPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_12 = 0x0158 +regPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_12 = 0x0159 +regPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_12 = 0x015a +regPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_12 = 0x015b +regPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_12 = 0x015c +regPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_13 = 0x015d +regPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_13 = 0x015e +regPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_13 = 0x015f +regPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_13 = 0x0160 +regPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_13 = 0x0161 +regPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_13 = 0x0162 +regPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_14 = 0x0163 +regPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_14 = 0x0164 +regPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_14 = 0x0165 +regPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_14 = 0x0166 +regPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_14 = 0x0167 +regPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_14 = 0x0168 +regPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 +regPA_CL_VPORT_XSCALE_15 = 0x0169 +regPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 +regPA_CL_VPORT_XOFFSET_15 = 0x016a +regPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 +regPA_CL_VPORT_YSCALE_15 = 0x016b +regPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 +regPA_CL_VPORT_YOFFSET_15 = 0x016c +regPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 +regPA_CL_VPORT_ZSCALE_15 = 0x016d +regPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 +regPA_CL_VPORT_ZOFFSET_15 = 0x016e +regPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 +regPA_CL_UCP_0_X = 0x016f +regPA_CL_UCP_0_X_BASE_IDX = 1 +regPA_CL_UCP_0_Y = 0x0170 +regPA_CL_UCP_0_Y_BASE_IDX = 1 +regPA_CL_UCP_0_Z = 0x0171 +regPA_CL_UCP_0_Z_BASE_IDX = 1 +regPA_CL_UCP_0_W = 0x0172 +regPA_CL_UCP_0_W_BASE_IDX = 1 +regPA_CL_UCP_1_X = 0x0173 +regPA_CL_UCP_1_X_BASE_IDX = 1 +regPA_CL_UCP_1_Y = 0x0174 +regPA_CL_UCP_1_Y_BASE_IDX = 1 +regPA_CL_UCP_1_Z = 0x0175 +regPA_CL_UCP_1_Z_BASE_IDX = 1 +regPA_CL_UCP_1_W = 0x0176 +regPA_CL_UCP_1_W_BASE_IDX = 1 +regPA_CL_UCP_2_X = 0x0177 +regPA_CL_UCP_2_X_BASE_IDX = 1 +regPA_CL_UCP_2_Y = 0x0178 +regPA_CL_UCP_2_Y_BASE_IDX = 1 +regPA_CL_UCP_2_Z = 0x0179 +regPA_CL_UCP_2_Z_BASE_IDX = 1 +regPA_CL_UCP_2_W = 0x017a +regPA_CL_UCP_2_W_BASE_IDX = 1 +regPA_CL_UCP_3_X = 0x017b +regPA_CL_UCP_3_X_BASE_IDX = 1 +regPA_CL_UCP_3_Y = 0x017c +regPA_CL_UCP_3_Y_BASE_IDX = 1 +regPA_CL_UCP_3_Z = 0x017d +regPA_CL_UCP_3_Z_BASE_IDX = 1 +regPA_CL_UCP_3_W = 0x017e +regPA_CL_UCP_3_W_BASE_IDX = 1 +regPA_CL_UCP_4_X = 0x017f +regPA_CL_UCP_4_X_BASE_IDX = 1 +regPA_CL_UCP_4_Y = 0x0180 +regPA_CL_UCP_4_Y_BASE_IDX = 1 +regPA_CL_UCP_4_Z = 0x0181 +regPA_CL_UCP_4_Z_BASE_IDX = 1 +regPA_CL_UCP_4_W = 0x0182 +regPA_CL_UCP_4_W_BASE_IDX = 1 +regPA_CL_UCP_5_X = 0x0183 +regPA_CL_UCP_5_X_BASE_IDX = 1 +regPA_CL_UCP_5_Y = 0x0184 +regPA_CL_UCP_5_Y_BASE_IDX = 1 +regPA_CL_UCP_5_Z = 0x0185 +regPA_CL_UCP_5_Z_BASE_IDX = 1 +regPA_CL_UCP_5_W = 0x0186 +regPA_CL_UCP_5_W_BASE_IDX = 1 +regPA_CL_PROG_NEAR_CLIP_Z = 0x0187 +regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 +regPA_RATE_CNTL = 0x0188 +regPA_RATE_CNTL_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_0 = 0x0191 +regSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_1 = 0x0192 +regSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_2 = 0x0193 +regSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_3 = 0x0194 +regSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_4 = 0x0195 +regSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_5 = 0x0196 +regSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_6 = 0x0197 +regSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_7 = 0x0198 +regSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_8 = 0x0199 +regSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_9 = 0x019a +regSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_10 = 0x019b +regSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_11 = 0x019c +regSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_12 = 0x019d +regSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_13 = 0x019e +regSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_14 = 0x019f +regSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_15 = 0x01a0 +regSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_16 = 0x01a1 +regSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_17 = 0x01a2 +regSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_18 = 0x01a3 +regSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_19 = 0x01a4 +regSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_20 = 0x01a5 +regSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_21 = 0x01a6 +regSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_22 = 0x01a7 +regSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_23 = 0x01a8 +regSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_24 = 0x01a9 +regSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_25 = 0x01aa +regSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_26 = 0x01ab +regSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_27 = 0x01ac +regSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_28 = 0x01ad +regSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_29 = 0x01ae +regSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_30 = 0x01af +regSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 +regSPI_PS_INPUT_CNTL_31 = 0x01b0 +regSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 +regSPI_VS_OUT_CONFIG = 0x01b1 +regSPI_VS_OUT_CONFIG_BASE_IDX = 1 +regSPI_PS_INPUT_ENA = 0x01b3 +regSPI_PS_INPUT_ENA_BASE_IDX = 1 +regSPI_PS_INPUT_ADDR = 0x01b4 +regSPI_PS_INPUT_ADDR_BASE_IDX = 1 +regSPI_INTERP_CONTROL_0 = 0x01b5 +regSPI_INTERP_CONTROL_0_BASE_IDX = 1 +regSPI_PS_IN_CONTROL = 0x01b6 +regSPI_PS_IN_CONTROL_BASE_IDX = 1 +regSPI_BARYC_CNTL = 0x01b8 +regSPI_BARYC_CNTL_BASE_IDX = 1 +regSPI_TMPRING_SIZE = 0x01ba +regSPI_TMPRING_SIZE_BASE_IDX = 1 +regSPI_GFX_SCRATCH_BASE_LO = 0x01bb +regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX = 1 +regSPI_GFX_SCRATCH_BASE_HI = 0x01bc +regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX = 1 +regSPI_SHADER_IDX_FORMAT = 0x01c2 +regSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 +regSPI_SHADER_POS_FORMAT = 0x01c3 +regSPI_SHADER_POS_FORMAT_BASE_IDX = 1 +regSPI_SHADER_Z_FORMAT = 0x01c4 +regSPI_SHADER_Z_FORMAT_BASE_IDX = 1 +regSPI_SHADER_COL_FORMAT = 0x01c5 +regSPI_SHADER_COL_FORMAT_BASE_IDX = 1 +regSX_PS_DOWNCONVERT_CONTROL = 0x01d4 +regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 +regSX_PS_DOWNCONVERT = 0x01d5 +regSX_PS_DOWNCONVERT_BASE_IDX = 1 +regSX_BLEND_OPT_EPSILON = 0x01d6 +regSX_BLEND_OPT_EPSILON_BASE_IDX = 1 +regSX_BLEND_OPT_CONTROL = 0x01d7 +regSX_BLEND_OPT_CONTROL_BASE_IDX = 1 +regSX_MRT0_BLEND_OPT = 0x01d8 +regSX_MRT0_BLEND_OPT_BASE_IDX = 1 +regSX_MRT1_BLEND_OPT = 0x01d9 +regSX_MRT1_BLEND_OPT_BASE_IDX = 1 +regSX_MRT2_BLEND_OPT = 0x01da +regSX_MRT2_BLEND_OPT_BASE_IDX = 1 +regSX_MRT3_BLEND_OPT = 0x01db +regSX_MRT3_BLEND_OPT_BASE_IDX = 1 +regSX_MRT4_BLEND_OPT = 0x01dc +regSX_MRT4_BLEND_OPT_BASE_IDX = 1 +regSX_MRT5_BLEND_OPT = 0x01dd +regSX_MRT5_BLEND_OPT_BASE_IDX = 1 +regSX_MRT6_BLEND_OPT = 0x01de +regSX_MRT6_BLEND_OPT_BASE_IDX = 1 +regSX_MRT7_BLEND_OPT = 0x01df +regSX_MRT7_BLEND_OPT_BASE_IDX = 1 +regCB_BLEND0_CONTROL = 0x01e0 +regCB_BLEND0_CONTROL_BASE_IDX = 1 +regCB_BLEND1_CONTROL = 0x01e1 +regCB_BLEND1_CONTROL_BASE_IDX = 1 +regCB_BLEND2_CONTROL = 0x01e2 +regCB_BLEND2_CONTROL_BASE_IDX = 1 +regCB_BLEND3_CONTROL = 0x01e3 +regCB_BLEND3_CONTROL_BASE_IDX = 1 +regCB_BLEND4_CONTROL = 0x01e4 +regCB_BLEND4_CONTROL_BASE_IDX = 1 +regCB_BLEND5_CONTROL = 0x01e5 +regCB_BLEND5_CONTROL_BASE_IDX = 1 +regCB_BLEND6_CONTROL = 0x01e6 +regCB_BLEND6_CONTROL_BASE_IDX = 1 +regCB_BLEND7_CONTROL = 0x01e7 +regCB_BLEND7_CONTROL_BASE_IDX = 1 +regGFX_COPY_STATE = 0x01f4 +regGFX_COPY_STATE_BASE_IDX = 1 +regPA_CL_POINT_X_RAD = 0x01f5 +regPA_CL_POINT_X_RAD_BASE_IDX = 1 +regPA_CL_POINT_Y_RAD = 0x01f6 +regPA_CL_POINT_Y_RAD_BASE_IDX = 1 +regPA_CL_POINT_SIZE = 0x01f7 +regPA_CL_POINT_SIZE_BASE_IDX = 1 +regPA_CL_POINT_CULL_RAD = 0x01f8 +regPA_CL_POINT_CULL_RAD_BASE_IDX = 1 +regVGT_DMA_BASE_HI = 0x01f9 +regVGT_DMA_BASE_HI_BASE_IDX = 1 +regVGT_DMA_BASE = 0x01fa +regVGT_DMA_BASE_BASE_IDX = 1 +regVGT_DRAW_INITIATOR = 0x01fc +regVGT_DRAW_INITIATOR_BASE_IDX = 1 +regVGT_EVENT_ADDRESS_REG = 0x01fe +regVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 +regGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff +regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 +regDB_DEPTH_CONTROL = 0x0200 +regDB_DEPTH_CONTROL_BASE_IDX = 1 +regDB_EQAA = 0x0201 +regDB_EQAA_BASE_IDX = 1 +regCB_COLOR_CONTROL = 0x0202 +regCB_COLOR_CONTROL_BASE_IDX = 1 +regDB_SHADER_CONTROL = 0x0203 +regDB_SHADER_CONTROL_BASE_IDX = 1 +regPA_CL_CLIP_CNTL = 0x0204 +regPA_CL_CLIP_CNTL_BASE_IDX = 1 +regPA_SU_SC_MODE_CNTL = 0x0205 +regPA_SU_SC_MODE_CNTL_BASE_IDX = 1 +regPA_CL_VTE_CNTL = 0x0206 +regPA_CL_VTE_CNTL_BASE_IDX = 1 +regPA_CL_VS_OUT_CNTL = 0x0207 +regPA_CL_VS_OUT_CNTL_BASE_IDX = 1 +regPA_CL_NANINF_CNTL = 0x0208 +regPA_CL_NANINF_CNTL_BASE_IDX = 1 +regPA_SU_LINE_STIPPLE_CNTL = 0x0209 +regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 +regPA_SU_LINE_STIPPLE_SCALE = 0x020a +regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 +regPA_SU_PRIM_FILTER_CNTL = 0x020b +regPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 +regPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c +regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 +regPA_CL_NGG_CNTL = 0x020e +regPA_CL_NGG_CNTL_BASE_IDX = 1 +regPA_SU_OVER_RASTERIZATION_CNTL = 0x020f +regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 +regPA_STEREO_CNTL = 0x0210 +regPA_STEREO_CNTL_BASE_IDX = 1 +regPA_STATE_STEREO_X = 0x0211 +regPA_STATE_STEREO_X_BASE_IDX = 1 +regPA_CL_VRS_CNTL = 0x0212 +regPA_CL_VRS_CNTL_BASE_IDX = 1 +regPA_SU_POINT_SIZE = 0x0280 +regPA_SU_POINT_SIZE_BASE_IDX = 1 +regPA_SU_POINT_MINMAX = 0x0281 +regPA_SU_POINT_MINMAX_BASE_IDX = 1 +regPA_SU_LINE_CNTL = 0x0282 +regPA_SU_LINE_CNTL_BASE_IDX = 1 +regPA_SC_LINE_STIPPLE = 0x0283 +regPA_SC_LINE_STIPPLE_BASE_IDX = 1 +regVGT_HOS_MAX_TESS_LEVEL = 0x0286 +regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 +regVGT_HOS_MIN_TESS_LEVEL = 0x0287 +regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 +regPA_SC_MODE_CNTL_0 = 0x0292 +regPA_SC_MODE_CNTL_0_BASE_IDX = 1 +regPA_SC_MODE_CNTL_1 = 0x0293 +regPA_SC_MODE_CNTL_1_BASE_IDX = 1 +regVGT_ENHANCE = 0x0294 +regVGT_ENHANCE_BASE_IDX = 1 +regIA_ENHANCE = 0x029c +regIA_ENHANCE_BASE_IDX = 1 +regVGT_DMA_SIZE = 0x029d +regVGT_DMA_SIZE_BASE_IDX = 1 +regVGT_DMA_MAX_SIZE = 0x029e +regVGT_DMA_MAX_SIZE_BASE_IDX = 1 +regVGT_DMA_INDEX_TYPE = 0x029f +regVGT_DMA_INDEX_TYPE_BASE_IDX = 1 +regWD_ENHANCE = 0x02a0 +regWD_ENHANCE_BASE_IDX = 1 +regVGT_PRIMITIVEID_EN = 0x02a1 +regVGT_PRIMITIVEID_EN_BASE_IDX = 1 +regVGT_DMA_NUM_INSTANCES = 0x02a2 +regVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 +regVGT_PRIMITIVEID_RESET = 0x02a3 +regVGT_PRIMITIVEID_RESET_BASE_IDX = 1 +regVGT_EVENT_INITIATOR = 0x02a4 +regVGT_EVENT_INITIATOR_BASE_IDX = 1 +regVGT_DRAW_PAYLOAD_CNTL = 0x02a6 +regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 +regVGT_ESGS_RING_ITEMSIZE = 0x02ab +regVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 +regVGT_REUSE_OFF = 0x02ad +regVGT_REUSE_OFF_BASE_IDX = 1 +regDB_HTILE_SURFACE = 0x02af +regDB_HTILE_SURFACE_BASE_IDX = 1 +regDB_SRESULTS_COMPARE_STATE0 = 0x02b0 +regDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 +regDB_SRESULTS_COMPARE_STATE1 = 0x02b1 +regDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 +regDB_PRELOAD_CONTROL = 0x02b2 +regDB_PRELOAD_CONTROL_BASE_IDX = 1 +regVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca +regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 +regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb +regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 +regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc +regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 +regVGT_GS_MAX_VERT_OUT = 0x02ce +regVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 +regGE_NGG_SUBGRP_CNTL = 0x02d3 +regGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 +regVGT_TESS_DISTRIBUTION = 0x02d4 +regVGT_TESS_DISTRIBUTION_BASE_IDX = 1 +regVGT_SHADER_STAGES_EN = 0x02d5 +regVGT_SHADER_STAGES_EN_BASE_IDX = 1 +regVGT_LS_HS_CONFIG = 0x02d6 +regVGT_LS_HS_CONFIG_BASE_IDX = 1 +regVGT_TF_PARAM = 0x02db +regVGT_TF_PARAM_BASE_IDX = 1 +regDB_ALPHA_TO_MASK = 0x02dc +regDB_ALPHA_TO_MASK_BASE_IDX = 1 +regPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de +regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 +regPA_SU_POLY_OFFSET_CLAMP = 0x02df +regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 +regPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 +regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 +regPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 +regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 +regPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 +regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 +regPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 +regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 +regVGT_GS_INSTANCE_CNT = 0x02e4 +regVGT_GS_INSTANCE_CNT_BASE_IDX = 1 +regPA_SC_CENTROID_PRIORITY_0 = 0x02f5 +regPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 +regPA_SC_CENTROID_PRIORITY_1 = 0x02f6 +regPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 +regPA_SC_LINE_CNTL = 0x02f7 +regPA_SC_LINE_CNTL_BASE_IDX = 1 +regPA_SC_AA_CONFIG = 0x02f8 +regPA_SC_AA_CONFIG_BASE_IDX = 1 +regPA_SU_VTX_CNTL = 0x02f9 +regPA_SU_VTX_CNTL_BASE_IDX = 1 +regPA_CL_GB_VERT_CLIP_ADJ = 0x02fa +regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 +regPA_CL_GB_VERT_DISC_ADJ = 0x02fb +regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 +regPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc +regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 +regPA_CL_GB_HORZ_DISC_ADJ = 0x02fd +regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d +regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 +regPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e +regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 +regPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f +regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 +regPA_SC_SHADER_CONTROL = 0x0310 +regPA_SC_SHADER_CONTROL_BASE_IDX = 1 +regPA_SC_BINNER_CNTL_0 = 0x0311 +regPA_SC_BINNER_CNTL_0_BASE_IDX = 1 +regPA_SC_BINNER_CNTL_1 = 0x0312 +regPA_SC_BINNER_CNTL_1_BASE_IDX = 1 +regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 +regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 +regPA_SC_NGG_MODE_CNTL = 0x0314 +regPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 +regPA_SC_BINNER_CNTL_2 = 0x0315 +regPA_SC_BINNER_CNTL_2_BASE_IDX = 1 +regCB_COLOR0_BASE = 0x0318 +regCB_COLOR0_BASE_BASE_IDX = 1 +regCB_COLOR0_VIEW = 0x031b +regCB_COLOR0_VIEW_BASE_IDX = 1 +regCB_COLOR0_INFO = 0x031c +regCB_COLOR0_INFO_BASE_IDX = 1 +regCB_COLOR0_ATTRIB = 0x031d +regCB_COLOR0_ATTRIB_BASE_IDX = 1 +regCB_COLOR0_FDCC_CONTROL = 0x031e +regCB_COLOR0_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR0_DCC_BASE = 0x0325 +regCB_COLOR0_DCC_BASE_BASE_IDX = 1 +regCB_COLOR1_BASE = 0x0327 +regCB_COLOR1_BASE_BASE_IDX = 1 +regCB_COLOR1_VIEW = 0x032a +regCB_COLOR1_VIEW_BASE_IDX = 1 +regCB_COLOR1_INFO = 0x032b +regCB_COLOR1_INFO_BASE_IDX = 1 +regCB_COLOR1_ATTRIB = 0x032c +regCB_COLOR1_ATTRIB_BASE_IDX = 1 +regCB_COLOR1_FDCC_CONTROL = 0x032d +regCB_COLOR1_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR1_DCC_BASE = 0x0334 +regCB_COLOR1_DCC_BASE_BASE_IDX = 1 +regCB_COLOR2_BASE = 0x0336 +regCB_COLOR2_BASE_BASE_IDX = 1 +regCB_COLOR2_VIEW = 0x0339 +regCB_COLOR2_VIEW_BASE_IDX = 1 +regCB_COLOR2_INFO = 0x033a +regCB_COLOR2_INFO_BASE_IDX = 1 +regCB_COLOR2_ATTRIB = 0x033b +regCB_COLOR2_ATTRIB_BASE_IDX = 1 +regCB_COLOR2_FDCC_CONTROL = 0x033c +regCB_COLOR2_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR2_DCC_BASE = 0x0343 +regCB_COLOR2_DCC_BASE_BASE_IDX = 1 +regCB_COLOR3_BASE = 0x0345 +regCB_COLOR3_BASE_BASE_IDX = 1 +regCB_COLOR3_VIEW = 0x0348 +regCB_COLOR3_VIEW_BASE_IDX = 1 +regCB_COLOR3_INFO = 0x0349 +regCB_COLOR3_INFO_BASE_IDX = 1 +regCB_COLOR3_ATTRIB = 0x034a +regCB_COLOR3_ATTRIB_BASE_IDX = 1 +regCB_COLOR3_FDCC_CONTROL = 0x034b +regCB_COLOR3_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR3_DCC_BASE = 0x0352 +regCB_COLOR3_DCC_BASE_BASE_IDX = 1 +regCB_COLOR4_BASE = 0x0354 +regCB_COLOR4_BASE_BASE_IDX = 1 +regCB_COLOR4_VIEW = 0x0357 +regCB_COLOR4_VIEW_BASE_IDX = 1 +regCB_COLOR4_INFO = 0x0358 +regCB_COLOR4_INFO_BASE_IDX = 1 +regCB_COLOR4_ATTRIB = 0x0359 +regCB_COLOR4_ATTRIB_BASE_IDX = 1 +regCB_COLOR4_FDCC_CONTROL = 0x035a +regCB_COLOR4_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR4_DCC_BASE = 0x0361 +regCB_COLOR4_DCC_BASE_BASE_IDX = 1 +regCB_COLOR5_BASE = 0x0363 +regCB_COLOR5_BASE_BASE_IDX = 1 +regCB_COLOR5_VIEW = 0x0366 +regCB_COLOR5_VIEW_BASE_IDX = 1 +regCB_COLOR5_INFO = 0x0367 +regCB_COLOR5_INFO_BASE_IDX = 1 +regCB_COLOR5_ATTRIB = 0x0368 +regCB_COLOR5_ATTRIB_BASE_IDX = 1 +regCB_COLOR5_FDCC_CONTROL = 0x0369 +regCB_COLOR5_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR5_DCC_BASE = 0x0370 +regCB_COLOR5_DCC_BASE_BASE_IDX = 1 +regCB_COLOR6_BASE = 0x0372 +regCB_COLOR6_BASE_BASE_IDX = 1 +regCB_COLOR6_VIEW = 0x0375 +regCB_COLOR6_VIEW_BASE_IDX = 1 +regCB_COLOR6_INFO = 0x0376 +regCB_COLOR6_INFO_BASE_IDX = 1 +regCB_COLOR6_ATTRIB = 0x0377 +regCB_COLOR6_ATTRIB_BASE_IDX = 1 +regCB_COLOR6_FDCC_CONTROL = 0x0378 +regCB_COLOR6_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR6_DCC_BASE = 0x037f +regCB_COLOR6_DCC_BASE_BASE_IDX = 1 +regCB_COLOR7_BASE = 0x0381 +regCB_COLOR7_BASE_BASE_IDX = 1 +regCB_COLOR7_VIEW = 0x0384 +regCB_COLOR7_VIEW_BASE_IDX = 1 +regCB_COLOR7_INFO = 0x0385 +regCB_COLOR7_INFO_BASE_IDX = 1 +regCB_COLOR7_ATTRIB = 0x0386 +regCB_COLOR7_ATTRIB_BASE_IDX = 1 +regCB_COLOR7_FDCC_CONTROL = 0x0387 +regCB_COLOR7_FDCC_CONTROL_BASE_IDX = 1 +regCB_COLOR7_DCC_BASE = 0x038e +regCB_COLOR7_DCC_BASE_BASE_IDX = 1 +regCB_COLOR0_BASE_EXT = 0x0390 +regCB_COLOR0_BASE_EXT_BASE_IDX = 1 +regCB_COLOR1_BASE_EXT = 0x0391 +regCB_COLOR1_BASE_EXT_BASE_IDX = 1 +regCB_COLOR2_BASE_EXT = 0x0392 +regCB_COLOR2_BASE_EXT_BASE_IDX = 1 +regCB_COLOR3_BASE_EXT = 0x0393 +regCB_COLOR3_BASE_EXT_BASE_IDX = 1 +regCB_COLOR4_BASE_EXT = 0x0394 +regCB_COLOR4_BASE_EXT_BASE_IDX = 1 +regCB_COLOR5_BASE_EXT = 0x0395 +regCB_COLOR5_BASE_EXT_BASE_IDX = 1 +regCB_COLOR6_BASE_EXT = 0x0396 +regCB_COLOR6_BASE_EXT_BASE_IDX = 1 +regCB_COLOR7_BASE_EXT = 0x0397 +regCB_COLOR7_BASE_EXT_BASE_IDX = 1 +regCB_COLOR0_DCC_BASE_EXT = 0x03a8 +regCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR1_DCC_BASE_EXT = 0x03a9 +regCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR2_DCC_BASE_EXT = 0x03aa +regCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR3_DCC_BASE_EXT = 0x03ab +regCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR4_DCC_BASE_EXT = 0x03ac +regCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR5_DCC_BASE_EXT = 0x03ad +regCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR6_DCC_BASE_EXT = 0x03ae +regCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR7_DCC_BASE_EXT = 0x03af +regCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 +regCB_COLOR0_ATTRIB2 = 0x03b0 +regCB_COLOR0_ATTRIB2_BASE_IDX = 1 +regCB_COLOR1_ATTRIB2 = 0x03b1 +regCB_COLOR1_ATTRIB2_BASE_IDX = 1 +regCB_COLOR2_ATTRIB2 = 0x03b2 +regCB_COLOR2_ATTRIB2_BASE_IDX = 1 +regCB_COLOR3_ATTRIB2 = 0x03b3 +regCB_COLOR3_ATTRIB2_BASE_IDX = 1 +regCB_COLOR4_ATTRIB2 = 0x03b4 +regCB_COLOR4_ATTRIB2_BASE_IDX = 1 +regCB_COLOR5_ATTRIB2 = 0x03b5 +regCB_COLOR5_ATTRIB2_BASE_IDX = 1 +regCB_COLOR6_ATTRIB2 = 0x03b6 +regCB_COLOR6_ATTRIB2_BASE_IDX = 1 +regCB_COLOR7_ATTRIB2 = 0x03b7 +regCB_COLOR7_ATTRIB2_BASE_IDX = 1 +regCB_COLOR0_ATTRIB3 = 0x03b8 +regCB_COLOR0_ATTRIB3_BASE_IDX = 1 +regCB_COLOR1_ATTRIB3 = 0x03b9 +regCB_COLOR1_ATTRIB3_BASE_IDX = 1 +regCB_COLOR2_ATTRIB3 = 0x03ba +regCB_COLOR2_ATTRIB3_BASE_IDX = 1 +regCB_COLOR3_ATTRIB3 = 0x03bb +regCB_COLOR3_ATTRIB3_BASE_IDX = 1 +regCB_COLOR4_ATTRIB3 = 0x03bc +regCB_COLOR4_ATTRIB3_BASE_IDX = 1 +regCB_COLOR5_ATTRIB3 = 0x03bd +regCB_COLOR5_ATTRIB3_BASE_IDX = 1 +regCB_COLOR6_ATTRIB3 = 0x03be +regCB_COLOR6_ATTRIB3_BASE_IDX = 1 +regCB_COLOR7_ATTRIB3 = 0x03bf +regCB_COLOR7_ATTRIB3_BASE_IDX = 1 +regCONFIG_RESERVED_REG0 = 0x0800 +regCONFIG_RESERVED_REG0_BASE_IDX = 1 +regCONFIG_RESERVED_REG1 = 0x0801 +regCONFIG_RESERVED_REG1_BASE_IDX = 1 +regCP_MEC_CNTL = 0x0802 +regCP_MEC_CNTL_BASE_IDX = 1 +regCP_ME_CNTL = 0x0803 +regCP_ME_CNTL_BASE_IDX = 1 +regGRBM_GFX_CNTL = 0x0900 +regGRBM_GFX_CNTL_BASE_IDX = 1 +regGRBM_NOWHERE = 0x0901 +regGRBM_NOWHERE_BASE_IDX = 1 +regPA_SC_VRS_SURFACE_CNTL = 0x0940 +regPA_SC_VRS_SURFACE_CNTL_BASE_IDX = 1 +regPA_SC_ENHANCE = 0x0941 +regPA_SC_ENHANCE_BASE_IDX = 1 +regPA_SC_ENHANCE_1 = 0x0942 +regPA_SC_ENHANCE_1_BASE_IDX = 1 +regPA_SC_ENHANCE_2 = 0x0943 +regPA_SC_ENHANCE_2_BASE_IDX = 1 +regPA_SC_ENHANCE_3 = 0x0944 +regPA_SC_ENHANCE_3_BASE_IDX = 1 +regPA_SC_BINNER_CNTL_OVERRIDE = 0x0946 +regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 1 +regPA_SC_PBB_OVERRIDE_FLAG = 0x0947 +regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 1 +regPA_SC_DSM_CNTL = 0x0948 +regPA_SC_DSM_CNTL_BASE_IDX = 1 +regPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x0949 +regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 1 +regPA_SC_FIFO_SIZE = 0x094a +regPA_SC_FIFO_SIZE_BASE_IDX = 1 +regPA_SC_IF_FIFO_SIZE = 0x094b +regPA_SC_IF_FIFO_SIZE_BASE_IDX = 1 +regPA_SC_PACKER_WAVE_ID_CNTL = 0x094c +regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX = 1 +regPA_SC_ATM_CNTL = 0x094d +regPA_SC_ATM_CNTL_BASE_IDX = 1 +regPA_SC_PKR_WAVE_TABLE_CNTL = 0x094e +regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 1 +regPA_SC_FORCE_EOV_MAX_CNTS = 0x094f +regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 1 +regPA_SC_BINNER_EVENT_CNTL_0 = 0x0950 +regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 1 +regPA_SC_BINNER_EVENT_CNTL_1 = 0x0951 +regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 1 +regPA_SC_BINNER_EVENT_CNTL_2 = 0x0952 +regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 1 +regPA_SC_BINNER_EVENT_CNTL_3 = 0x0953 +regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 1 +regPA_SC_BINNER_TIMEOUT_COUNTER = 0x0954 +regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 1 +regPA_SC_BINNER_PERF_CNTL_0 = 0x0955 +regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 1 +regPA_SC_BINNER_PERF_CNTL_1 = 0x0956 +regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 1 +regPA_SC_BINNER_PERF_CNTL_2 = 0x0957 +regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 1 +regPA_SC_BINNER_PERF_CNTL_3 = 0x0958 +regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 1 +regPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x095b +regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 +regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x095c +regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 +regPA_SC_TRAP_SCREEN_HV_LOCK = 0x095d +regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 1 +regPA_PH_INTERFACE_FIFO_SIZE = 0x095e +regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 1 +regPA_PH_ENHANCE = 0x095f +regPA_PH_ENHANCE_BASE_IDX = 1 +regPA_SC_VRS_SURFACE_CNTL_1 = 0x0960 +regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX = 1 +regSQ_RUNTIME_CONFIG = 0x09e0 +regSQ_RUNTIME_CONFIG_BASE_IDX = 1 +regSQ_DEBUG_STS_GLOBAL = 0x09e1 +regSQ_DEBUG_STS_GLOBAL_BASE_IDX = 1 +regSQ_DEBUG_STS_GLOBAL2 = 0x09e2 +regSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 1 +regSH_MEM_BASES = 0x09e3 +regSH_MEM_BASES_BASE_IDX = 1 +regSH_MEM_CONFIG = 0x09e4 +regSH_MEM_CONFIG_BASE_IDX = 1 +regSQ_DEBUG = 0x09e5 +regSQ_DEBUG_BASE_IDX = 1 +regSQ_SHADER_TBA_LO = 0x09e6 +regSQ_SHADER_TBA_LO_BASE_IDX = 1 +regSQ_SHADER_TBA_HI = 0x09e7 +regSQ_SHADER_TBA_HI_BASE_IDX = 1 +regSQ_SHADER_TMA_LO = 0x09e8 +regSQ_SHADER_TMA_LO_BASE_IDX = 1 +regSQ_SHADER_TMA_HI = 0x09e9 +regSQ_SHADER_TMA_HI_BASE_IDX = 1 +regCP_DEBUG_2 = 0x1800 +regCP_DEBUG_2_BASE_IDX = 1 +regCP_FETCHER_SOURCE = 0x1801 +regCP_FETCHER_SOURCE_BASE_IDX = 1 +regCP_HPD_MES_ROQ_OFFSETS = 0x1821 +regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 1 +regCP_HPD_ROQ_OFFSETS = 0x1821 +regCP_HPD_ROQ_OFFSETS_BASE_IDX = 1 +regCP_HPD_STATUS0 = 0x1822 +regCP_HPD_STATUS0_BASE_IDX = 1 +regDIDT_INDEX_AUTO_INCR_EN = 0x1900 +regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 1 +regDIDT_EDC_CTRL = 0x1901 +regDIDT_EDC_CTRL_BASE_IDX = 1 +regDIDT_EDC_THROTTLE_CTRL = 0x1902 +regDIDT_EDC_THROTTLE_CTRL_BASE_IDX = 1 +regDIDT_EDC_THRESHOLD = 0x1903 +regDIDT_EDC_THRESHOLD_BASE_IDX = 1 +regDIDT_EDC_STALL_PATTERN_1_2 = 0x1904 +regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX = 1 +regDIDT_EDC_STALL_PATTERN_3_4 = 0x1905 +regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX = 1 +regDIDT_EDC_STALL_PATTERN_5_6 = 0x1906 +regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX = 1 +regDIDT_EDC_STALL_PATTERN_7 = 0x1907 +regDIDT_EDC_STALL_PATTERN_7_BASE_IDX = 1 +regDIDT_EDC_STATUS = 0x1908 +regDIDT_EDC_STATUS_BASE_IDX = 1 +regDIDT_EDC_DYNAMIC_THRESHOLD_RO = 0x1909 +regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX = 1 +regDIDT_EDC_OVERFLOW = 0x190a +regDIDT_EDC_OVERFLOW_BASE_IDX = 1 +regDIDT_EDC_ROLLING_POWER_DELTA = 0x190b +regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 +regDIDT_IND_INDEX = 0x190c +regDIDT_IND_INDEX_BASE_IDX = 1 +regDIDT_IND_DATA = 0x190d +regDIDT_IND_DATA_BASE_IDX = 1 +regSPI_GDBG_WAVE_CNTL = 0x1943 +regSPI_GDBG_WAVE_CNTL_BASE_IDX = 1 +regSPI_GDBG_TRAP_CONFIG = 0x1944 +regSPI_GDBG_TRAP_CONFIG_BASE_IDX = 1 +regSPI_GDBG_WAVE_CNTL3 = 0x1945 +regSPI_GDBG_WAVE_CNTL3_BASE_IDX = 1 +regSPI_ARB_CNTL_0 = 0x1949 +regSPI_ARB_CNTL_0_BASE_IDX = 1 +regSPI_FEATURE_CTRL = 0x194a +regSPI_FEATURE_CTRL_BASE_IDX = 1 +regSPI_SHADER_RSRC_LIMIT_CTRL = 0x194b +regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 1 +regSPI_COMPUTE_WF_CTX_SAVE_STATUS = 0x194e +regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX = 1 +regTCP_INVALIDATE = 0x19a0 +regTCP_INVALIDATE_BASE_IDX = 1 +regTCP_STATUS = 0x19a1 +regTCP_STATUS_BASE_IDX = 1 +regTCP_CNTL = 0x19a2 +regTCP_CNTL_BASE_IDX = 1 +regTCP_CNTL2 = 0x19a3 +regTCP_CNTL2_BASE_IDX = 1 +regTCP_DEBUG_INDEX = 0x19a5 +regTCP_DEBUG_INDEX_BASE_IDX = 1 +regTCP_DEBUG_DATA = 0x19a6 +regTCP_DEBUG_DATA_BASE_IDX = 1 +regGDS_ENHANCE2 = 0x19b0 +regGDS_ENHANCE2_BASE_IDX = 1 +regGDS_OA_CGPG_RESTORE = 0x19b1 +regGDS_OA_CGPG_RESTORE_BASE_IDX = 1 +regUTCL1_CTRL_0 = 0x1980 +regUTCL1_CTRL_0_BASE_IDX = 1 +regUTCL1_UTCL0_INVREQ_DISABLE = 0x1984 +regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 1 +regUTCL1_CTRL_2 = 0x1985 +regUTCL1_CTRL_2_BASE_IDX = 1 +regUTCL1_FIFO_SIZING = 0x1986 +regUTCL1_FIFO_SIZING_BASE_IDX = 1 +regGCRD_SA0_TARGETS_DISABLE = 0x1987 +regGCRD_SA0_TARGETS_DISABLE_BASE_IDX = 1 +regGCRD_SA1_TARGETS_DISABLE = 0x1989 +regGCRD_SA1_TARGETS_DISABLE_BASE_IDX = 1 +regGCRD_CREDIT_SAFE = 0x198a +regGCRD_CREDIT_SAFE_BASE_IDX = 1 +regGCR_GENERAL_CNTL = 0x1990 +regGCR_GENERAL_CNTL_BASE_IDX = 1 +regGCR_CMD_STATUS = 0x1992 +regGCR_CMD_STATUS_BASE_IDX = 1 +regGCR_SPARE = 0x1993 +regGCR_SPARE_BASE_IDX = 1 +regPMM_CNTL2 = 0x1999 +regPMM_CNTL2_BASE_IDX = 1 +regSEDC_GL1_GL2_OVERRIDES = 0x1ac0 +regSEDC_GL1_GL2_OVERRIDES_BASE_IDX = 1 +regGC_CAC_CTRL_1 = 0x1ad0 +regGC_CAC_CTRL_1_BASE_IDX = 1 +regGC_CAC_CTRL_2 = 0x1ad1 +regGC_CAC_CTRL_2_BASE_IDX = 1 +regGC_CAC_AGGR_LOWER = 0x1ad2 +regGC_CAC_AGGR_LOWER_BASE_IDX = 1 +regGC_CAC_AGGR_UPPER = 0x1ad3 +regGC_CAC_AGGR_UPPER_BASE_IDX = 1 +regSE0_CAC_AGGR_LOWER = 0x1ad4 +regSE0_CAC_AGGR_LOWER_BASE_IDX = 1 +regSE0_CAC_AGGR_UPPER = 0x1ad5 +regSE0_CAC_AGGR_UPPER_BASE_IDX = 1 +regSE1_CAC_AGGR_LOWER = 0x1ad6 +regSE1_CAC_AGGR_LOWER_BASE_IDX = 1 +regSE1_CAC_AGGR_UPPER = 0x1ad7 +regSE1_CAC_AGGR_UPPER_BASE_IDX = 1 +regSE2_CAC_AGGR_LOWER = 0x1ad8 +regSE2_CAC_AGGR_LOWER_BASE_IDX = 1 +regSE2_CAC_AGGR_UPPER = 0x1ad9 +regSE2_CAC_AGGR_UPPER_BASE_IDX = 1 +regSE3_CAC_AGGR_LOWER = 0x1ada +regSE3_CAC_AGGR_LOWER_BASE_IDX = 1 +regSE3_CAC_AGGR_UPPER = 0x1adb +regSE3_CAC_AGGR_UPPER_BASE_IDX = 1 +regSE4_CAC_AGGR_LOWER = 0x1adc +regSE4_CAC_AGGR_LOWER_BASE_IDX = 1 +regSE4_CAC_AGGR_UPPER = 0x1add +regSE4_CAC_AGGR_UPPER_BASE_IDX = 1 +regSE5_CAC_AGGR_LOWER = 0x1ade +regSE5_CAC_AGGR_LOWER_BASE_IDX = 1 +regSE5_CAC_AGGR_UPPER = 0x1adf +regSE5_CAC_AGGR_UPPER_BASE_IDX = 1 +regGC_CAC_AGGR_GFXCLK_CYCLE = 0x1ae4 +regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regSE0_CAC_AGGR_GFXCLK_CYCLE = 0x1ae5 +regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regSE1_CAC_AGGR_GFXCLK_CYCLE = 0x1ae6 +regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regSE2_CAC_AGGR_GFXCLK_CYCLE = 0x1ae7 +regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regSE3_CAC_AGGR_GFXCLK_CYCLE = 0x1ae8 +regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regSE4_CAC_AGGR_GFXCLK_CYCLE = 0x1ae9 +regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regSE5_CAC_AGGR_GFXCLK_CYCLE = 0x1aea +regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX = 1 +regGC_EDC_CTRL = 0x1aed +regGC_EDC_CTRL_BASE_IDX = 1 +regGC_EDC_THRESHOLD = 0x1aee +regGC_EDC_THRESHOLD_BASE_IDX = 1 +regGC_EDC_STRETCH_CTRL = 0x1aef +regGC_EDC_STRETCH_CTRL_BASE_IDX = 1 +regGC_EDC_STRETCH_THRESHOLD = 0x1af0 +regGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 1 +regEDC_HYSTERESIS_CNTL = 0x1af1 +regEDC_HYSTERESIS_CNTL_BASE_IDX = 1 +regGC_THROTTLE_CTRL = 0x1af2 +regGC_THROTTLE_CTRL_BASE_IDX = 1 +regGC_THROTTLE_CTRL1 = 0x1af3 +regGC_THROTTLE_CTRL1_BASE_IDX = 1 +regPCC_STALL_PATTERN_CTRL = 0x1af4 +regPCC_STALL_PATTERN_CTRL_BASE_IDX = 1 +regPWRBRK_STALL_PATTERN_CTRL = 0x1af5 +regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX = 1 +regPCC_STALL_PATTERN_1_2 = 0x1af6 +regPCC_STALL_PATTERN_1_2_BASE_IDX = 1 +regPCC_STALL_PATTERN_3_4 = 0x1af7 +regPCC_STALL_PATTERN_3_4_BASE_IDX = 1 +regPCC_STALL_PATTERN_5_6 = 0x1af8 +regPCC_STALL_PATTERN_5_6_BASE_IDX = 1 +regPCC_STALL_PATTERN_7 = 0x1af9 +regPCC_STALL_PATTERN_7_BASE_IDX = 1 +regPWRBRK_STALL_PATTERN_1_2 = 0x1afa +regPWRBRK_STALL_PATTERN_1_2_BASE_IDX = 1 +regPWRBRK_STALL_PATTERN_3_4 = 0x1afb +regPWRBRK_STALL_PATTERN_3_4_BASE_IDX = 1 +regPWRBRK_STALL_PATTERN_5_6 = 0x1afc +regPWRBRK_STALL_PATTERN_5_6_BASE_IDX = 1 +regPWRBRK_STALL_PATTERN_7 = 0x1afd +regPWRBRK_STALL_PATTERN_7_BASE_IDX = 1 +regDIDT_STALL_PATTERN_CTRL = 0x1afe +regDIDT_STALL_PATTERN_CTRL_BASE_IDX = 1 +regDIDT_STALL_PATTERN_1_2 = 0x1aff +regDIDT_STALL_PATTERN_1_2_BASE_IDX = 1 +regDIDT_STALL_PATTERN_3_4 = 0x1b00 +regDIDT_STALL_PATTERN_3_4_BASE_IDX = 1 +regDIDT_STALL_PATTERN_5_6 = 0x1b01 +regDIDT_STALL_PATTERN_5_6_BASE_IDX = 1 +regDIDT_STALL_PATTERN_7 = 0x1b02 +regDIDT_STALL_PATTERN_7_BASE_IDX = 1 +regPCC_PWRBRK_HYSTERESIS_CTRL = 0x1b03 +regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX = 1 +regEDC_STRETCH_PERF_COUNTER = 0x1b04 +regEDC_STRETCH_PERF_COUNTER_BASE_IDX = 1 +regEDC_UNSTRETCH_PERF_COUNTER = 0x1b05 +regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX = 1 +regEDC_STRETCH_NUM_PERF_COUNTER = 0x1b06 +regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX = 1 +regGC_EDC_STATUS = 0x1b07 +regGC_EDC_STATUS_BASE_IDX = 1 +regGC_EDC_OVERFLOW = 0x1b08 +regGC_EDC_OVERFLOW_BASE_IDX = 1 +regGC_EDC_ROLLING_POWER_DELTA = 0x1b09 +regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 1 +regGC_THROTTLE_STATUS = 0x1b0a +regGC_THROTTLE_STATUS_BASE_IDX = 1 +regEDC_PERF_COUNTER = 0x1b0b +regEDC_PERF_COUNTER_BASE_IDX = 1 +regPCC_PERF_COUNTER = 0x1b0c +regPCC_PERF_COUNTER_BASE_IDX = 1 +regPWRBRK_PERF_COUNTER = 0x1b0d +regPWRBRK_PERF_COUNTER_BASE_IDX = 1 +regEDC_HYSTERESIS_STAT = 0x1b0e +regEDC_HYSTERESIS_STAT_BASE_IDX = 1 +regGC_CAC_WEIGHT_CP_0 = 0x1b10 +regGC_CAC_WEIGHT_CP_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_CP_1 = 0x1b11 +regGC_CAC_WEIGHT_CP_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_EA_0 = 0x1b12 +regGC_CAC_WEIGHT_EA_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_EA_1 = 0x1b13 +regGC_CAC_WEIGHT_EA_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_EA_2 = 0x1b14 +regGC_CAC_WEIGHT_EA_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x1b15 +regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x1b16 +regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x1b17 +regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x1b18 +regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x1b19 +regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x1b1a +regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x1b1b +regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x1b1c +regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x1b1d +regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x1b1e +regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x1b1f +regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_GDS_0 = 0x1b20 +regGC_CAC_WEIGHT_GDS_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_GDS_1 = 0x1b21 +regGC_CAC_WEIGHT_GDS_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_GDS_2 = 0x1b22 +regGC_CAC_WEIGHT_GDS_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_0 = 0x1b23 +regGC_CAC_WEIGHT_GE_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_1 = 0x1b24 +regGC_CAC_WEIGHT_GE_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_2 = 0x1b25 +regGC_CAC_WEIGHT_GE_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_3 = 0x1b26 +regGC_CAC_WEIGHT_GE_3_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_4 = 0x1b27 +regGC_CAC_WEIGHT_GE_4_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_5 = 0x1b28 +regGC_CAC_WEIGHT_GE_5_BASE_IDX = 1 +regGC_CAC_WEIGHT_GE_6 = 0x1b29 +regGC_CAC_WEIGHT_GE_6_BASE_IDX = 1 +regGC_CAC_WEIGHT_PMM_0 = 0x1b2e +regGC_CAC_WEIGHT_PMM_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_GL2C_0 = 0x1b2f +regGC_CAC_WEIGHT_GL2C_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_GL2C_1 = 0x1b30 +regGC_CAC_WEIGHT_GL2C_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_GL2C_2 = 0x1b31 +regGC_CAC_WEIGHT_GL2C_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_PH_0 = 0x1b32 +regGC_CAC_WEIGHT_PH_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_PH_1 = 0x1b33 +regGC_CAC_WEIGHT_PH_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_PH_2 = 0x1b34 +regGC_CAC_WEIGHT_PH_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_PH_3 = 0x1b35 +regGC_CAC_WEIGHT_PH_3_BASE_IDX = 1 +regGC_CAC_WEIGHT_SDMA_0 = 0x1b36 +regGC_CAC_WEIGHT_SDMA_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_SDMA_1 = 0x1b37 +regGC_CAC_WEIGHT_SDMA_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_SDMA_2 = 0x1b38 +regGC_CAC_WEIGHT_SDMA_2_BASE_IDX = 1 +regGC_CAC_WEIGHT_SDMA_3 = 0x1b39 +regGC_CAC_WEIGHT_SDMA_3_BASE_IDX = 1 +regGC_CAC_WEIGHT_SDMA_4 = 0x1b3a +regGC_CAC_WEIGHT_SDMA_4_BASE_IDX = 1 +regGC_CAC_WEIGHT_SDMA_5 = 0x1b3b +regGC_CAC_WEIGHT_SDMA_5_BASE_IDX = 1 +regGC_CAC_WEIGHT_CHC_0 = 0x1b3c +regGC_CAC_WEIGHT_CHC_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_CHC_1 = 0x1b3d +regGC_CAC_WEIGHT_CHC_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_GUS_0 = 0x1b3e +regGC_CAC_WEIGHT_GUS_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_GUS_1 = 0x1b3f +regGC_CAC_WEIGHT_GUS_1_BASE_IDX = 1 +regGC_CAC_WEIGHT_RLC_0 = 0x1b40 +regGC_CAC_WEIGHT_RLC_0_BASE_IDX = 1 +regGC_CAC_WEIGHT_GRBM_0 = 0x1b44 +regGC_CAC_WEIGHT_GRBM_0_BASE_IDX = 1 +regGC_EDC_CLK_MONITOR_CTRL = 0x1b56 +regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX = 1 +regGC_CAC_IND_INDEX = 0x1b58 +regGC_CAC_IND_INDEX_BASE_IDX = 1 +regGC_CAC_IND_DATA = 0x1b59 +regGC_CAC_IND_DATA_BASE_IDX = 1 +regSE_CAC_CTRL_1 = 0x1b70 +regSE_CAC_CTRL_1_BASE_IDX = 1 +regSE_CAC_CTRL_2 = 0x1b71 +regSE_CAC_CTRL_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_TA_0 = 0x1b72 +regSE_CAC_WEIGHT_TA_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_TD_0 = 0x1b73 +regSE_CAC_WEIGHT_TD_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_TD_1 = 0x1b74 +regSE_CAC_WEIGHT_TD_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_TD_2 = 0x1b75 +regSE_CAC_WEIGHT_TD_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_TD_3 = 0x1b76 +regSE_CAC_WEIGHT_TD_3_BASE_IDX = 1 +regSE_CAC_WEIGHT_TD_4 = 0x1b77 +regSE_CAC_WEIGHT_TD_4_BASE_IDX = 1 +regSE_CAC_WEIGHT_TD_5 = 0x1b78 +regSE_CAC_WEIGHT_TD_5_BASE_IDX = 1 +regSE_CAC_WEIGHT_TCP_0 = 0x1b79 +regSE_CAC_WEIGHT_TCP_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_TCP_1 = 0x1b7a +regSE_CAC_WEIGHT_TCP_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_TCP_2 = 0x1b7b +regSE_CAC_WEIGHT_TCP_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_TCP_3 = 0x1b7c +regSE_CAC_WEIGHT_TCP_3_BASE_IDX = 1 +regSE_CAC_WEIGHT_SQ_0 = 0x1b7d +regSE_CAC_WEIGHT_SQ_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_SQ_1 = 0x1b7e +regSE_CAC_WEIGHT_SQ_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_SQ_2 = 0x1b7f +regSE_CAC_WEIGHT_SQ_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_SP_0 = 0x1b80 +regSE_CAC_WEIGHT_SP_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_SP_1 = 0x1b81 +regSE_CAC_WEIGHT_SP_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_LDS_0 = 0x1b82 +regSE_CAC_WEIGHT_LDS_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_LDS_1 = 0x1b83 +regSE_CAC_WEIGHT_LDS_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_LDS_2 = 0x1b84 +regSE_CAC_WEIGHT_LDS_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_LDS_3 = 0x1b85 +regSE_CAC_WEIGHT_LDS_3_BASE_IDX = 1 +regSE_CAC_WEIGHT_SQC_0 = 0x1b87 +regSE_CAC_WEIGHT_SQC_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_SQC_1 = 0x1b88 +regSE_CAC_WEIGHT_SQC_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_CU_0 = 0x1b89 +regSE_CAC_WEIGHT_CU_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_BCI_0 = 0x1b8a +regSE_CAC_WEIGHT_BCI_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_0 = 0x1b8b +regSE_CAC_WEIGHT_CB_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_1 = 0x1b8c +regSE_CAC_WEIGHT_CB_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_2 = 0x1b8d +regSE_CAC_WEIGHT_CB_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_3 = 0x1b8e +regSE_CAC_WEIGHT_CB_3_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_4 = 0x1b8f +regSE_CAC_WEIGHT_CB_4_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_5 = 0x1b90 +regSE_CAC_WEIGHT_CB_5_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_6 = 0x1b91 +regSE_CAC_WEIGHT_CB_6_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_7 = 0x1b92 +regSE_CAC_WEIGHT_CB_7_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_8 = 0x1b93 +regSE_CAC_WEIGHT_CB_8_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_9 = 0x1b94 +regSE_CAC_WEIGHT_CB_9_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_10 = 0x1b95 +regSE_CAC_WEIGHT_CB_10_BASE_IDX = 1 +regSE_CAC_WEIGHT_CB_11 = 0x1b96 +regSE_CAC_WEIGHT_CB_11_BASE_IDX = 1 +regSE_CAC_WEIGHT_DB_0 = 0x1b97 +regSE_CAC_WEIGHT_DB_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_DB_1 = 0x1b98 +regSE_CAC_WEIGHT_DB_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_DB_2 = 0x1b99 +regSE_CAC_WEIGHT_DB_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_DB_3 = 0x1b9a +regSE_CAC_WEIGHT_DB_3_BASE_IDX = 1 +regSE_CAC_WEIGHT_DB_4 = 0x1b9b +regSE_CAC_WEIGHT_DB_4_BASE_IDX = 1 +regSE_CAC_WEIGHT_RMI_0 = 0x1b9c +regSE_CAC_WEIGHT_RMI_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_RMI_1 = 0x1b9d +regSE_CAC_WEIGHT_RMI_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_SX_0 = 0x1b9e +regSE_CAC_WEIGHT_SX_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_SXRB_0 = 0x1b9f +regSE_CAC_WEIGHT_SXRB_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_UTCL1_0 = 0x1ba0 +regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_GL1C_0 = 0x1ba1 +regSE_CAC_WEIGHT_GL1C_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_GL1C_1 = 0x1ba2 +regSE_CAC_WEIGHT_GL1C_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_GL1C_2 = 0x1ba3 +regSE_CAC_WEIGHT_GL1C_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_SPI_0 = 0x1ba4 +regSE_CAC_WEIGHT_SPI_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_SPI_1 = 0x1ba5 +regSE_CAC_WEIGHT_SPI_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_SPI_2 = 0x1ba6 +regSE_CAC_WEIGHT_SPI_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_PC_0 = 0x1ba7 +regSE_CAC_WEIGHT_PC_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_PA_0 = 0x1ba8 +regSE_CAC_WEIGHT_PA_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_PA_1 = 0x1ba9 +regSE_CAC_WEIGHT_PA_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_PA_2 = 0x1baa +regSE_CAC_WEIGHT_PA_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_PA_3 = 0x1bab +regSE_CAC_WEIGHT_PA_3_BASE_IDX = 1 +regSE_CAC_WEIGHT_SC_0 = 0x1bac +regSE_CAC_WEIGHT_SC_0_BASE_IDX = 1 +regSE_CAC_WEIGHT_SC_1 = 0x1bad +regSE_CAC_WEIGHT_SC_1_BASE_IDX = 1 +regSE_CAC_WEIGHT_SC_2 = 0x1bae +regSE_CAC_WEIGHT_SC_2_BASE_IDX = 1 +regSE_CAC_WEIGHT_SC_3 = 0x1baf +regSE_CAC_WEIGHT_SC_3_BASE_IDX = 1 +regSE_CAC_WINDOW_AGGR_VALUE = 0x1bb0 +regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX = 1 +regSE_CAC_WINDOW_GFXCLK_CYCLE = 0x1bb1 +regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX = 1 +regSE_CAC_IND_INDEX = 0x1bce +regSE_CAC_IND_INDEX_BASE_IDX = 1 +regSE_CAC_IND_DATA = 0x1bcf +regSE_CAC_IND_DATA_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_0 = 0x1c00 +regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_1 = 0x1c01 +regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_2 = 0x1c02 +regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_3 = 0x1c03 +regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_4 = 0x1c04 +regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_5 = 0x1c05 +regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_6 = 0x1c06 +regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_7 = 0x1c07 +regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_8 = 0x1c08 +regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_9 = 0x1c09 +regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_10 = 0x1c0a +regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_11 = 0x1c0b +regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_12 = 0x1c0c +regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_13 = 0x1c0d +regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_14 = 0x1c0e +regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_CU_15 = 0x1c0f +regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1c10 +regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1c11 +regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1c12 +regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1c13 +regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1c14 +regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1c15 +regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1c16 +regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1c17 +regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1c18 +regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1c19 +regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_10 = 0x1c1a +regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_11 = 0x1c1b +regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_12 = 0x1c1c +regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_13 = 0x1c1d +regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_14 = 0x1c1e +regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX = 1 +regSPI_RESOURCE_RESERVE_EN_CU_15 = 0x1c1f +regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX = 1 +regCP_EOP_DONE_ADDR_LO = 0x2000 +regCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 +regCP_EOP_DONE_ADDR_HI = 0x2001 +regCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 +regCP_EOP_DONE_DATA_LO = 0x2002 +regCP_EOP_DONE_DATA_LO_BASE_IDX = 1 +regCP_EOP_DONE_DATA_HI = 0x2003 +regCP_EOP_DONE_DATA_HI_BASE_IDX = 1 +regCP_EOP_LAST_FENCE_LO = 0x2004 +regCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 +regCP_EOP_LAST_FENCE_HI = 0x2005 +regCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 +regCP_PIPE_STATS_ADDR_LO = 0x2018 +regCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 +regCP_PIPE_STATS_ADDR_HI = 0x2019 +regCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 +regCP_VGT_IAVERT_COUNT_LO = 0x201a +regCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 +regCP_VGT_IAVERT_COUNT_HI = 0x201b +regCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 +regCP_VGT_IAPRIM_COUNT_LO = 0x201c +regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 +regCP_VGT_IAPRIM_COUNT_HI = 0x201d +regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 +regCP_VGT_GSPRIM_COUNT_LO = 0x201e +regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 +regCP_VGT_GSPRIM_COUNT_HI = 0x201f +regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 +regCP_VGT_VSINVOC_COUNT_LO = 0x2020 +regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 +regCP_VGT_VSINVOC_COUNT_HI = 0x2021 +regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 +regCP_VGT_GSINVOC_COUNT_LO = 0x2022 +regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 +regCP_VGT_GSINVOC_COUNT_HI = 0x2023 +regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 +regCP_VGT_HSINVOC_COUNT_LO = 0x2024 +regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 +regCP_VGT_HSINVOC_COUNT_HI = 0x2025 +regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 +regCP_VGT_DSINVOC_COUNT_LO = 0x2026 +regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 +regCP_VGT_DSINVOC_COUNT_HI = 0x2027 +regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 +regCP_PA_CINVOC_COUNT_LO = 0x2028 +regCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 +regCP_PA_CINVOC_COUNT_HI = 0x2029 +regCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 +regCP_PA_CPRIM_COUNT_LO = 0x202a +regCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 +regCP_PA_CPRIM_COUNT_HI = 0x202b +regCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 +regCP_SC_PSINVOC_COUNT0_LO = 0x202c +regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 +regCP_SC_PSINVOC_COUNT0_HI = 0x202d +regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 +regCP_SC_PSINVOC_COUNT1_LO = 0x202e +regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 +regCP_SC_PSINVOC_COUNT1_HI = 0x202f +regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 +regCP_VGT_CSINVOC_COUNT_LO = 0x2030 +regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 +regCP_VGT_CSINVOC_COUNT_HI = 0x2031 +regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 +regCP_VGT_ASINVOC_COUNT_LO = 0x2032 +regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX = 1 +regCP_VGT_ASINVOC_COUNT_HI = 0x2033 +regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX = 1 +regCP_PIPE_STATS_CONTROL = 0x203d +regCP_PIPE_STATS_CONTROL_BASE_IDX = 1 +regSCRATCH_REG0 = 0x2040 +regSCRATCH_REG0_BASE_IDX = 1 +regSCRATCH_REG1 = 0x2041 +regSCRATCH_REG1_BASE_IDX = 1 +regSCRATCH_REG2 = 0x2042 +regSCRATCH_REG2_BASE_IDX = 1 +regSCRATCH_REG3 = 0x2043 +regSCRATCH_REG3_BASE_IDX = 1 +regSCRATCH_REG4 = 0x2044 +regSCRATCH_REG4_BASE_IDX = 1 +regSCRATCH_REG5 = 0x2045 +regSCRATCH_REG5_BASE_IDX = 1 +regSCRATCH_REG6 = 0x2046 +regSCRATCH_REG6_BASE_IDX = 1 +regSCRATCH_REG7 = 0x2047 +regSCRATCH_REG7_BASE_IDX = 1 +regSCRATCH_REG_ATOMIC = 0x2048 +regSCRATCH_REG_ATOMIC_BASE_IDX = 1 +regSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 +regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 +regCP_APPEND_DDID_CNT = 0x204b +regCP_APPEND_DDID_CNT_BASE_IDX = 1 +regCP_APPEND_DATA_HI = 0x204c +regCP_APPEND_DATA_HI_BASE_IDX = 1 +regCP_APPEND_LAST_CS_FENCE_HI = 0x204d +regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 +regCP_APPEND_LAST_PS_FENCE_HI = 0x204e +regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 +regCP_PFP_ATOMIC_PREOP_LO = 0x2052 +regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 +regCP_PFP_ATOMIC_PREOP_HI = 0x2053 +regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 +regCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 +regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 +regCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 +regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 +regCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 +regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 +regCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 +regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 +regCP_APPEND_ADDR_LO = 0x2058 +regCP_APPEND_ADDR_LO_BASE_IDX = 1 +regCP_APPEND_ADDR_HI = 0x2059 +regCP_APPEND_ADDR_HI_BASE_IDX = 1 +regCP_APPEND_DATA = 0x205a +regCP_APPEND_DATA_BASE_IDX = 1 +regCP_APPEND_DATA_LO = 0x205a +regCP_APPEND_DATA_LO_BASE_IDX = 1 +regCP_APPEND_LAST_CS_FENCE = 0x205b +regCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 +regCP_APPEND_LAST_CS_FENCE_LO = 0x205b +regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 +regCP_APPEND_LAST_PS_FENCE = 0x205c +regCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 +regCP_APPEND_LAST_PS_FENCE_LO = 0x205c +regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 +regCP_ATOMIC_PREOP_LO = 0x205d +regCP_ATOMIC_PREOP_LO_BASE_IDX = 1 +regCP_ME_ATOMIC_PREOP_LO = 0x205d +regCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 +regCP_ATOMIC_PREOP_HI = 0x205e +regCP_ATOMIC_PREOP_HI_BASE_IDX = 1 +regCP_ME_ATOMIC_PREOP_HI = 0x205e +regCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 +regCP_GDS_ATOMIC0_PREOP_LO = 0x205f +regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 +regCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f +regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 +regCP_GDS_ATOMIC0_PREOP_HI = 0x2060 +regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 +regCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 +regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 +regCP_GDS_ATOMIC1_PREOP_LO = 0x2061 +regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 +regCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 +regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 +regCP_GDS_ATOMIC1_PREOP_HI = 0x2062 +regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 +regCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 +regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 +regCP_ME_MC_WADDR_LO = 0x2069 +regCP_ME_MC_WADDR_LO_BASE_IDX = 1 +regCP_ME_MC_WADDR_HI = 0x206a +regCP_ME_MC_WADDR_HI_BASE_IDX = 1 +regCP_ME_MC_WDATA_LO = 0x206b +regCP_ME_MC_WDATA_LO_BASE_IDX = 1 +regCP_ME_MC_WDATA_HI = 0x206c +regCP_ME_MC_WDATA_HI_BASE_IDX = 1 +regCP_ME_MC_RADDR_LO = 0x206d +regCP_ME_MC_RADDR_LO_BASE_IDX = 1 +regCP_ME_MC_RADDR_HI = 0x206e +regCP_ME_MC_RADDR_HI_BASE_IDX = 1 +regCP_SEM_WAIT_TIMER = 0x206f +regCP_SEM_WAIT_TIMER_BASE_IDX = 1 +regCP_SIG_SEM_ADDR_LO = 0x2070 +regCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 +regCP_SIG_SEM_ADDR_HI = 0x2071 +regCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 +regCP_WAIT_REG_MEM_TIMEOUT = 0x2074 +regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 +regCP_WAIT_SEM_ADDR_LO = 0x2075 +regCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 +regCP_WAIT_SEM_ADDR_HI = 0x2076 +regCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 +regCP_DMA_PFP_CONTROL = 0x2077 +regCP_DMA_PFP_CONTROL_BASE_IDX = 1 +regCP_DMA_ME_CONTROL = 0x2078 +regCP_DMA_ME_CONTROL_BASE_IDX = 1 +regCP_DMA_ME_SRC_ADDR = 0x2080 +regCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 +regCP_DMA_ME_SRC_ADDR_HI = 0x2081 +regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 +regCP_DMA_ME_DST_ADDR = 0x2082 +regCP_DMA_ME_DST_ADDR_BASE_IDX = 1 +regCP_DMA_ME_DST_ADDR_HI = 0x2083 +regCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 +regCP_DMA_ME_COMMAND = 0x2084 +regCP_DMA_ME_COMMAND_BASE_IDX = 1 +regCP_DMA_PFP_SRC_ADDR = 0x2085 +regCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 +regCP_DMA_PFP_SRC_ADDR_HI = 0x2086 +regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 +regCP_DMA_PFP_DST_ADDR = 0x2087 +regCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 +regCP_DMA_PFP_DST_ADDR_HI = 0x2088 +regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 +regCP_DMA_PFP_COMMAND = 0x2089 +regCP_DMA_PFP_COMMAND_BASE_IDX = 1 +regCP_DMA_CNTL = 0x208a +regCP_DMA_CNTL_BASE_IDX = 1 +regCP_DMA_READ_TAGS = 0x208b +regCP_DMA_READ_TAGS_BASE_IDX = 1 +regCP_PFP_IB_CONTROL = 0x208d +regCP_PFP_IB_CONTROL_BASE_IDX = 1 +regCP_PFP_LOAD_CONTROL = 0x208e +regCP_PFP_LOAD_CONTROL_BASE_IDX = 1 +regCP_SCRATCH_INDEX = 0x208f +regCP_SCRATCH_INDEX_BASE_IDX = 1 +regCP_SCRATCH_DATA = 0x2090 +regCP_SCRATCH_DATA_BASE_IDX = 1 +regCP_RB_OFFSET = 0x2091 +regCP_RB_OFFSET_BASE_IDX = 1 +regCP_IB2_OFFSET = 0x2093 +regCP_IB2_OFFSET_BASE_IDX = 1 +regCP_IB2_PREAMBLE_BEGIN = 0x2096 +regCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 +regCP_IB2_PREAMBLE_END = 0x2097 +regCP_IB2_PREAMBLE_END_BASE_IDX = 1 +regCP_DMA_ME_CMD_ADDR_LO = 0x209c +regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 +regCP_DMA_ME_CMD_ADDR_HI = 0x209d +regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 +regCP_DMA_PFP_CMD_ADDR_LO = 0x209e +regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 +regCP_DMA_PFP_CMD_ADDR_HI = 0x209f +regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 +regCP_APPEND_CMD_ADDR_LO = 0x20a0 +regCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 +regCP_APPEND_CMD_ADDR_HI = 0x20a1 +regCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 +regUCONFIG_RESERVED_REG0 = 0x20a2 +regUCONFIG_RESERVED_REG0_BASE_IDX = 1 +regUCONFIG_RESERVED_REG1 = 0x20a3 +regUCONFIG_RESERVED_REG1_BASE_IDX = 1 +regCP_PA_MSPRIM_COUNT_LO = 0x20a4 +regCP_PA_MSPRIM_COUNT_LO_BASE_IDX = 1 +regCP_PA_MSPRIM_COUNT_HI = 0x20a5 +regCP_PA_MSPRIM_COUNT_HI_BASE_IDX = 1 +regCP_GE_MSINVOC_COUNT_LO = 0x20a6 +regCP_GE_MSINVOC_COUNT_LO_BASE_IDX = 1 +regCP_GE_MSINVOC_COUNT_HI = 0x20a7 +regCP_GE_MSINVOC_COUNT_HI_BASE_IDX = 1 +regCP_IB1_CMD_BUFSZ = 0x20c0 +regCP_IB1_CMD_BUFSZ_BASE_IDX = 1 +regCP_IB2_CMD_BUFSZ = 0x20c1 +regCP_IB2_CMD_BUFSZ_BASE_IDX = 1 +regCP_ST_CMD_BUFSZ = 0x20c2 +regCP_ST_CMD_BUFSZ_BASE_IDX = 1 +regCP_IB1_BASE_LO = 0x20cc +regCP_IB1_BASE_LO_BASE_IDX = 1 +regCP_IB1_BASE_HI = 0x20cd +regCP_IB1_BASE_HI_BASE_IDX = 1 +regCP_IB1_BUFSZ = 0x20ce +regCP_IB1_BUFSZ_BASE_IDX = 1 +regCP_IB2_BASE_LO = 0x20cf +regCP_IB2_BASE_LO_BASE_IDX = 1 +regCP_IB2_BASE_HI = 0x20d0 +regCP_IB2_BASE_HI_BASE_IDX = 1 +regCP_IB2_BUFSZ = 0x20d1 +regCP_IB2_BUFSZ_BASE_IDX = 1 +regCP_ST_BASE_LO = 0x20d2 +regCP_ST_BASE_LO_BASE_IDX = 1 +regCP_ST_BASE_HI = 0x20d3 +regCP_ST_BASE_HI_BASE_IDX = 1 +regCP_ST_BUFSZ = 0x20d4 +regCP_ST_BUFSZ_BASE_IDX = 1 +regCP_EOP_DONE_EVENT_CNTL = 0x20d5 +regCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 +regCP_EOP_DONE_DATA_CNTL = 0x20d6 +regCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 +regCP_EOP_DONE_CNTX_ID = 0x20d7 +regCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 +regCP_DB_BASE_LO = 0x20d8 +regCP_DB_BASE_LO_BASE_IDX = 1 +regCP_DB_BASE_HI = 0x20d9 +regCP_DB_BASE_HI_BASE_IDX = 1 +regCP_DB_BUFSZ = 0x20da +regCP_DB_BUFSZ_BASE_IDX = 1 +regCP_DB_CMD_BUFSZ = 0x20db +regCP_DB_CMD_BUFSZ_BASE_IDX = 1 +regCP_PFP_COMPLETION_STATUS = 0x20ec +regCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 +regCP_PRED_NOT_VISIBLE = 0x20ee +regCP_PRED_NOT_VISIBLE_BASE_IDX = 1 +regCP_PFP_METADATA_BASE_ADDR = 0x20f0 +regCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 +regCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 +regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 +regCP_DRAW_INDX_INDR_ADDR = 0x20f4 +regCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 +regCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 +regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 +regCP_DISPATCH_INDR_ADDR = 0x20f6 +regCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 +regCP_DISPATCH_INDR_ADDR_HI = 0x20f7 +regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 +regCP_INDEX_BASE_ADDR = 0x20f8 +regCP_INDEX_BASE_ADDR_BASE_IDX = 1 +regCP_INDEX_BASE_ADDR_HI = 0x20f9 +regCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 +regCP_INDEX_TYPE = 0x20fa +regCP_INDEX_TYPE_BASE_IDX = 1 +regCP_GDS_BKUP_ADDR = 0x20fb +regCP_GDS_BKUP_ADDR_BASE_IDX = 1 +regCP_GDS_BKUP_ADDR_HI = 0x20fc +regCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 +regCP_SAMPLE_STATUS = 0x20fd +regCP_SAMPLE_STATUS_BASE_IDX = 1 +regCP_ME_COHER_CNTL = 0x20fe +regCP_ME_COHER_CNTL_BASE_IDX = 1 +regCP_ME_COHER_SIZE = 0x20ff +regCP_ME_COHER_SIZE_BASE_IDX = 1 +regCP_ME_COHER_SIZE_HI = 0x2100 +regCP_ME_COHER_SIZE_HI_BASE_IDX = 1 +regCP_ME_COHER_BASE = 0x2101 +regCP_ME_COHER_BASE_BASE_IDX = 1 +regCP_ME_COHER_BASE_HI = 0x2102 +regCP_ME_COHER_BASE_HI_BASE_IDX = 1 +regCP_ME_COHER_STATUS = 0x2103 +regCP_ME_COHER_STATUS_BASE_IDX = 1 +regRLC_GPM_PERF_COUNT_0 = 0x2140 +regRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 +regRLC_GPM_PERF_COUNT_1 = 0x2141 +regRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 +regGRBM_GFX_INDEX = 0x2200 +regGRBM_GFX_INDEX_BASE_IDX = 1 +regVGT_PRIMITIVE_TYPE = 0x2242 +regVGT_PRIMITIVE_TYPE_BASE_IDX = 1 +regVGT_INDEX_TYPE = 0x2243 +regVGT_INDEX_TYPE_BASE_IDX = 1 +regGE_MIN_VTX_INDX = 0x2249 +regGE_MIN_VTX_INDX_BASE_IDX = 1 +regGE_INDX_OFFSET = 0x224a +regGE_INDX_OFFSET_BASE_IDX = 1 +regGE_MULTI_PRIM_IB_RESET_EN = 0x224b +regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 +regVGT_NUM_INDICES = 0x224c +regVGT_NUM_INDICES_BASE_IDX = 1 +regVGT_NUM_INSTANCES = 0x224d +regVGT_NUM_INSTANCES_BASE_IDX = 1 +regVGT_TF_RING_SIZE = 0x224e +regVGT_TF_RING_SIZE_BASE_IDX = 1 +regVGT_HS_OFFCHIP_PARAM = 0x224f +regVGT_HS_OFFCHIP_PARAM_BASE_IDX = 1 +regVGT_TF_MEMORY_BASE = 0x2250 +regVGT_TF_MEMORY_BASE_BASE_IDX = 1 +regGE_MAX_VTX_INDX = 0x2259 +regGE_MAX_VTX_INDX_BASE_IDX = 1 +regVGT_INSTANCE_BASE_ID = 0x225a +regVGT_INSTANCE_BASE_ID_BASE_IDX = 1 +regGE_CNTL = 0x225b +regGE_CNTL_BASE_IDX = 1 +regGE_USER_VGPR1 = 0x225c +regGE_USER_VGPR1_BASE_IDX = 1 +regGE_USER_VGPR2 = 0x225d +regGE_USER_VGPR2_BASE_IDX = 1 +regGE_USER_VGPR3 = 0x225e +regGE_USER_VGPR3_BASE_IDX = 1 +regGE_STEREO_CNTL = 0x225f +regGE_STEREO_CNTL_BASE_IDX = 1 +regGE_PC_ALLOC = 0x2260 +regGE_PC_ALLOC_BASE_IDX = 1 +regVGT_TF_MEMORY_BASE_HI = 0x2261 +regVGT_TF_MEMORY_BASE_HI_BASE_IDX = 1 +regGE_USER_VGPR_EN = 0x2262 +regGE_USER_VGPR_EN_BASE_IDX = 1 +regGE_GS_FAST_LAUNCH_WG_DIM = 0x2264 +regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX = 1 +regGE_GS_FAST_LAUNCH_WG_DIM_1 = 0x2265 +regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX = 1 +regVGT_GS_OUT_PRIM_TYPE = 0x2266 +regVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 +regPA_SU_LINE_STIPPLE_VALUE = 0x2280 +regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 +regPA_SC_LINE_STIPPLE_STATE = 0x2281 +regPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 +regPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 +regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 +regPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 +regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 +regPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 +regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 +regPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b +regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 +regPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 +regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 +regPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 +regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 +regPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 +regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 +regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 +regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 +regPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 +regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 +regPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 +regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 +regPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 +regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 +regPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa +regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 +regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab +regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 +regPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac +regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 +regPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 +regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 +regPA_SC_TRAP_SCREEN_H = 0x22b1 +regPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 +regPA_SC_TRAP_SCREEN_V = 0x22b2 +regPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 +regPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 +regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 +regPA_SC_TRAP_SCREEN_COUNT = 0x22b4 +regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_0 = 0x2340 +regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_1 = 0x2341 +regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_2 = 0x2342 +regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_3 = 0x2343 +regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_4 = 0x2344 +regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_5 = 0x2345 +regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_6 = 0x2346 +regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 +regSQ_THREAD_TRACE_USERDATA_7 = 0x2347 +regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 +regSQC_CACHES = 0x2348 +regSQC_CACHES_BASE_IDX = 1 +regTA_CS_BC_BASE_ADDR = 0x2380 +regTA_CS_BC_BASE_ADDR_BASE_IDX = 1 +regTA_CS_BC_BASE_ADDR_HI = 0x2381 +regTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 +regDB_OCCLUSION_COUNT0_LOW = 0x23c0 +regDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 +regDB_OCCLUSION_COUNT0_HI = 0x23c1 +regDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 +regDB_OCCLUSION_COUNT1_LOW = 0x23c2 +regDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 +regDB_OCCLUSION_COUNT1_HI = 0x23c3 +regDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 +regDB_OCCLUSION_COUNT2_LOW = 0x23c4 +regDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 +regDB_OCCLUSION_COUNT2_HI = 0x23c5 +regDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 +regDB_OCCLUSION_COUNT3_LOW = 0x23c6 +regDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 +regDB_OCCLUSION_COUNT3_HI = 0x23c7 +regDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 +regGDS_RD_ADDR = 0x2400 +regGDS_RD_ADDR_BASE_IDX = 1 +regGDS_RD_DATA = 0x2401 +regGDS_RD_DATA_BASE_IDX = 1 +regGDS_RD_BURST_ADDR = 0x2402 +regGDS_RD_BURST_ADDR_BASE_IDX = 1 +regGDS_RD_BURST_COUNT = 0x2403 +regGDS_RD_BURST_COUNT_BASE_IDX = 1 +regGDS_RD_BURST_DATA = 0x2404 +regGDS_RD_BURST_DATA_BASE_IDX = 1 +regGDS_WR_ADDR = 0x2405 +regGDS_WR_ADDR_BASE_IDX = 1 +regGDS_WR_DATA = 0x2406 +regGDS_WR_DATA_BASE_IDX = 1 +regGDS_WR_BURST_ADDR = 0x2407 +regGDS_WR_BURST_ADDR_BASE_IDX = 1 +regGDS_WR_BURST_DATA = 0x2408 +regGDS_WR_BURST_DATA_BASE_IDX = 1 +regGDS_WRITE_COMPLETE = 0x2409 +regGDS_WRITE_COMPLETE_BASE_IDX = 1 +regGDS_ATOM_CNTL = 0x240a +regGDS_ATOM_CNTL_BASE_IDX = 1 +regGDS_ATOM_COMPLETE = 0x240b +regGDS_ATOM_COMPLETE_BASE_IDX = 1 +regGDS_ATOM_BASE = 0x240c +regGDS_ATOM_BASE_BASE_IDX = 1 +regGDS_ATOM_SIZE = 0x240d +regGDS_ATOM_SIZE_BASE_IDX = 1 +regGDS_ATOM_OFFSET0 = 0x240e +regGDS_ATOM_OFFSET0_BASE_IDX = 1 +regGDS_ATOM_OFFSET1 = 0x240f +regGDS_ATOM_OFFSET1_BASE_IDX = 1 +regGDS_ATOM_DST = 0x2410 +regGDS_ATOM_DST_BASE_IDX = 1 +regGDS_ATOM_OP = 0x2411 +regGDS_ATOM_OP_BASE_IDX = 1 +regGDS_ATOM_SRC0 = 0x2412 +regGDS_ATOM_SRC0_BASE_IDX = 1 +regGDS_ATOM_SRC0_U = 0x2413 +regGDS_ATOM_SRC0_U_BASE_IDX = 1 +regGDS_ATOM_SRC1 = 0x2414 +regGDS_ATOM_SRC1_BASE_IDX = 1 +regGDS_ATOM_SRC1_U = 0x2415 +regGDS_ATOM_SRC1_U_BASE_IDX = 1 +regGDS_ATOM_READ0 = 0x2416 +regGDS_ATOM_READ0_BASE_IDX = 1 +regGDS_ATOM_READ0_U = 0x2417 +regGDS_ATOM_READ0_U_BASE_IDX = 1 +regGDS_ATOM_READ1 = 0x2418 +regGDS_ATOM_READ1_BASE_IDX = 1 +regGDS_ATOM_READ1_U = 0x2419 +regGDS_ATOM_READ1_U_BASE_IDX = 1 +regGDS_GWS_RESOURCE_CNTL = 0x241a +regGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 +regGDS_GWS_RESOURCE = 0x241b +regGDS_GWS_RESOURCE_BASE_IDX = 1 +regGDS_GWS_RESOURCE_CNT = 0x241c +regGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 +regGDS_OA_CNTL = 0x241d +regGDS_OA_CNTL_BASE_IDX = 1 +regGDS_OA_COUNTER = 0x241e +regGDS_OA_COUNTER_BASE_IDX = 1 +regGDS_OA_ADDRESS = 0x241f +regGDS_OA_ADDRESS_BASE_IDX = 1 +regGDS_OA_INCDEC = 0x2420 +regGDS_OA_INCDEC_BASE_IDX = 1 +regGDS_OA_RING_SIZE = 0x2421 +regGDS_OA_RING_SIZE_BASE_IDX = 1 +regGDS_STRMOUT_DWORDS_WRITTEN_0 = 0x2422 +regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX = 1 +regGDS_STRMOUT_DWORDS_WRITTEN_1 = 0x2423 +regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX = 1 +regGDS_STRMOUT_DWORDS_WRITTEN_2 = 0x2424 +regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX = 1 +regGDS_STRMOUT_DWORDS_WRITTEN_3 = 0x2425 +regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX = 1 +regGDS_GS_0 = 0x2426 +regGDS_GS_0_BASE_IDX = 1 +regGDS_GS_1 = 0x2427 +regGDS_GS_1_BASE_IDX = 1 +regGDS_GS_2 = 0x2428 +regGDS_GS_2_BASE_IDX = 1 +regGDS_GS_3 = 0x2429 +regGDS_GS_3_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_0_LO = 0x242a +regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_0_HI = 0x242b +regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_0_LO = 0x242c +regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_0_HI = 0x242d +regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_1_LO = 0x242e +regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_1_HI = 0x242f +regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_1_LO = 0x2430 +regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_1_HI = 0x2431 +regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_2_LO = 0x2432 +regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_2_HI = 0x2433 +regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_2_LO = 0x2434 +regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_2_HI = 0x2435 +regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_3_LO = 0x2436 +regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_NEEDED_3_HI = 0x2437 +regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_3_LO = 0x2438 +regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX = 1 +regGDS_STRMOUT_PRIMS_WRITTEN_3_HI = 0x2439 +regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX = 1 +regSPI_CONFIG_CNTL = 0x2440 +regSPI_CONFIG_CNTL_BASE_IDX = 1 +regSPI_CONFIG_CNTL_1 = 0x2441 +regSPI_CONFIG_CNTL_1_BASE_IDX = 1 +regSPI_CONFIG_CNTL_2 = 0x2442 +regSPI_CONFIG_CNTL_2_BASE_IDX = 1 +regSPI_WAVE_LIMIT_CNTL = 0x2443 +regSPI_WAVE_LIMIT_CNTL_BASE_IDX = 1 +regSPI_GS_THROTTLE_CNTL1 = 0x2444 +regSPI_GS_THROTTLE_CNTL1_BASE_IDX = 1 +regSPI_GS_THROTTLE_CNTL2 = 0x2445 +regSPI_GS_THROTTLE_CNTL2_BASE_IDX = 1 +regSPI_ATTRIBUTE_RING_BASE = 0x2446 +regSPI_ATTRIBUTE_RING_BASE_BASE_IDX = 1 +regSPI_ATTRIBUTE_RING_SIZE = 0x2447 +regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX = 1 +regCP_MES_PRGRM_CNTR_START = 0x2800 +regCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 +regCP_MES_INTR_ROUTINE_START = 0x2801 +regCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 +regCP_MES_MTVEC_LO = 0x2801 +regCP_MES_MTVEC_LO_BASE_IDX = 1 +regCP_MES_INTR_ROUTINE_START_HI = 0x2802 +regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX = 1 +regCP_MES_MTVEC_HI = 0x2802 +regCP_MES_MTVEC_HI_BASE_IDX = 1 +regCP_MES_CNTL = 0x2807 +regCP_MES_CNTL_BASE_IDX = 1 +regCP_MES_PIPE_PRIORITY_CNTS = 0x2808 +regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 +regCP_MES_PIPE0_PRIORITY = 0x2809 +regCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 +regCP_MES_PIPE1_PRIORITY = 0x280a +regCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 +regCP_MES_PIPE2_PRIORITY = 0x280b +regCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 +regCP_MES_PIPE3_PRIORITY = 0x280c +regCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 +regCP_MES_HEADER_DUMP = 0x280d +regCP_MES_HEADER_DUMP_BASE_IDX = 1 +regCP_MES_MIE_LO = 0x280e +regCP_MES_MIE_LO_BASE_IDX = 1 +regCP_MES_MIE_HI = 0x280f +regCP_MES_MIE_HI_BASE_IDX = 1 +regCP_MES_INTERRUPT = 0x2810 +regCP_MES_INTERRUPT_BASE_IDX = 1 +regCP_MES_SCRATCH_INDEX = 0x2811 +regCP_MES_SCRATCH_INDEX_BASE_IDX = 1 +regCP_MES_SCRATCH_DATA = 0x2812 +regCP_MES_SCRATCH_DATA_BASE_IDX = 1 +regCP_MES_INSTR_PNTR = 0x2813 +regCP_MES_INSTR_PNTR_BASE_IDX = 1 +regCP_MES_MSCRATCH_HI = 0x2814 +regCP_MES_MSCRATCH_HI_BASE_IDX = 1 +regCP_MES_MSCRATCH_LO = 0x2815 +regCP_MES_MSCRATCH_LO_BASE_IDX = 1 +regCP_MES_MSTATUS_LO = 0x2816 +regCP_MES_MSTATUS_LO_BASE_IDX = 1 +regCP_MES_MSTATUS_HI = 0x2817 +regCP_MES_MSTATUS_HI_BASE_IDX = 1 +regCP_MES_MEPC_LO = 0x2818 +regCP_MES_MEPC_LO_BASE_IDX = 1 +regCP_MES_MEPC_HI = 0x2819 +regCP_MES_MEPC_HI_BASE_IDX = 1 +regCP_MES_MCAUSE_LO = 0x281a +regCP_MES_MCAUSE_LO_BASE_IDX = 1 +regCP_MES_MCAUSE_HI = 0x281b +regCP_MES_MCAUSE_HI_BASE_IDX = 1 +regCP_MES_MBADADDR_LO = 0x281c +regCP_MES_MBADADDR_LO_BASE_IDX = 1 +regCP_MES_MBADADDR_HI = 0x281d +regCP_MES_MBADADDR_HI_BASE_IDX = 1 +regCP_MES_MIP_LO = 0x281e +regCP_MES_MIP_LO_BASE_IDX = 1 +regCP_MES_MIP_HI = 0x281f +regCP_MES_MIP_HI_BASE_IDX = 1 +regCP_MES_IC_OP_CNTL = 0x2820 +regCP_MES_IC_OP_CNTL_BASE_IDX = 1 +regCP_MES_MCYCLE_LO = 0x2826 +regCP_MES_MCYCLE_LO_BASE_IDX = 1 +regCP_MES_MCYCLE_HI = 0x2827 +regCP_MES_MCYCLE_HI_BASE_IDX = 1 +regCP_MES_MTIME_LO = 0x2828 +regCP_MES_MTIME_LO_BASE_IDX = 1 +regCP_MES_MTIME_HI = 0x2829 +regCP_MES_MTIME_HI_BASE_IDX = 1 +regCP_MES_MINSTRET_LO = 0x282a +regCP_MES_MINSTRET_LO_BASE_IDX = 1 +regCP_MES_MINSTRET_HI = 0x282b +regCP_MES_MINSTRET_HI_BASE_IDX = 1 +regCP_MES_MISA_LO = 0x282c +regCP_MES_MISA_LO_BASE_IDX = 1 +regCP_MES_MISA_HI = 0x282d +regCP_MES_MISA_HI_BASE_IDX = 1 +regCP_MES_MVENDORID_LO = 0x282e +regCP_MES_MVENDORID_LO_BASE_IDX = 1 +regCP_MES_MVENDORID_HI = 0x282f +regCP_MES_MVENDORID_HI_BASE_IDX = 1 +regCP_MES_MARCHID_LO = 0x2830 +regCP_MES_MARCHID_LO_BASE_IDX = 1 +regCP_MES_MARCHID_HI = 0x2831 +regCP_MES_MARCHID_HI_BASE_IDX = 1 +regCP_MES_MIMPID_LO = 0x2832 +regCP_MES_MIMPID_LO_BASE_IDX = 1 +regCP_MES_MIMPID_HI = 0x2833 +regCP_MES_MIMPID_HI_BASE_IDX = 1 +regCP_MES_MHARTID_LO = 0x2834 +regCP_MES_MHARTID_LO_BASE_IDX = 1 +regCP_MES_MHARTID_HI = 0x2835 +regCP_MES_MHARTID_HI_BASE_IDX = 1 +regCP_MES_DC_BASE_CNTL = 0x2836 +regCP_MES_DC_BASE_CNTL_BASE_IDX = 1 +regCP_MES_DC_OP_CNTL = 0x2837 +regCP_MES_DC_OP_CNTL_BASE_IDX = 1 +regCP_MES_MTIMECMP_LO = 0x2838 +regCP_MES_MTIMECMP_LO_BASE_IDX = 1 +regCP_MES_MTIMECMP_HI = 0x2839 +regCP_MES_MTIMECMP_HI_BASE_IDX = 1 +regCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a +regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 +regCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b +regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 +regCP_MES_DOORBELL_CONTROL1 = 0x283c +regCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 +regCP_MES_DOORBELL_CONTROL2 = 0x283d +regCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 +regCP_MES_DOORBELL_CONTROL3 = 0x283e +regCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 +regCP_MES_DOORBELL_CONTROL4 = 0x283f +regCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 +regCP_MES_DOORBELL_CONTROL5 = 0x2840 +regCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 +regCP_MES_DOORBELL_CONTROL6 = 0x2841 +regCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 +regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR = 0x2842 +regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX = 1 +regCP_MES_GP0_LO = 0x2843 +regCP_MES_GP0_LO_BASE_IDX = 1 +regCP_MES_GP0_HI = 0x2844 +regCP_MES_GP0_HI_BASE_IDX = 1 +regCP_MES_GP1_LO = 0x2845 +regCP_MES_GP1_LO_BASE_IDX = 1 +regCP_MES_GP1_HI = 0x2846 +regCP_MES_GP1_HI_BASE_IDX = 1 +regCP_MES_GP2_LO = 0x2847 +regCP_MES_GP2_LO_BASE_IDX = 1 +regCP_MES_GP2_HI = 0x2848 +regCP_MES_GP2_HI_BASE_IDX = 1 +regCP_MES_GP3_LO = 0x2849 +regCP_MES_GP3_LO_BASE_IDX = 1 +regCP_MES_GP3_HI = 0x284a +regCP_MES_GP3_HI_BASE_IDX = 1 +regCP_MES_GP4_LO = 0x284b +regCP_MES_GP4_LO_BASE_IDX = 1 +regCP_MES_GP4_HI = 0x284c +regCP_MES_GP4_HI_BASE_IDX = 1 +regCP_MES_GP5_LO = 0x284d +regCP_MES_GP5_LO_BASE_IDX = 1 +regCP_MES_GP5_HI = 0x284e +regCP_MES_GP5_HI_BASE_IDX = 1 +regCP_MES_GP6_LO = 0x284f +regCP_MES_GP6_LO_BASE_IDX = 1 +regCP_MES_GP6_HI = 0x2850 +regCP_MES_GP6_HI_BASE_IDX = 1 +regCP_MES_GP7_LO = 0x2851 +regCP_MES_GP7_LO_BASE_IDX = 1 +regCP_MES_GP7_HI = 0x2852 +regCP_MES_GP7_HI_BASE_IDX = 1 +regCP_MES_GP8_LO = 0x2853 +regCP_MES_GP8_LO_BASE_IDX = 1 +regCP_MES_GP8_HI = 0x2854 +regCP_MES_GP8_HI_BASE_IDX = 1 +regCP_MES_GP9_LO = 0x2855 +regCP_MES_GP9_LO_BASE_IDX = 1 +regCP_MES_GP9_HI = 0x2856 +regCP_MES_GP9_HI_BASE_IDX = 1 +regCP_MES_LOCAL_BASE0_LO = 0x2883 +regCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 +regCP_MES_LOCAL_BASE0_HI = 0x2884 +regCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 +regCP_MES_LOCAL_MASK0_LO = 0x2885 +regCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 +regCP_MES_LOCAL_MASK0_HI = 0x2886 +regCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 +regCP_MES_LOCAL_APERTURE = 0x2887 +regCP_MES_LOCAL_APERTURE_BASE_IDX = 1 +regCP_MES_LOCAL_INSTR_BASE_LO = 0x2888 +regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 +regCP_MES_LOCAL_INSTR_BASE_HI = 0x2889 +regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 +regCP_MES_LOCAL_INSTR_MASK_LO = 0x288a +regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 +regCP_MES_LOCAL_INSTR_MASK_HI = 0x288b +regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 +regCP_MES_LOCAL_INSTR_APERTURE = 0x288c +regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX = 1 +regCP_MES_LOCAL_SCRATCH_APERTURE = 0x288d +regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 +regCP_MES_LOCAL_SCRATCH_BASE_LO = 0x288e +regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 +regCP_MES_LOCAL_SCRATCH_BASE_HI = 0x288f +regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 +regCP_MES_PERFCOUNT_CNTL = 0x2899 +regCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 +regCP_MES_PENDING_INTERRUPT = 0x289a +regCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 +regCP_MES_PRGRM_CNTR_START_HI = 0x289d +regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_16 = 0x289f +regCP_MES_INTERRUPT_DATA_16_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_17 = 0x28a0 +regCP_MES_INTERRUPT_DATA_17_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_18 = 0x28a1 +regCP_MES_INTERRUPT_DATA_18_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_19 = 0x28a2 +regCP_MES_INTERRUPT_DATA_19_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_20 = 0x28a3 +regCP_MES_INTERRUPT_DATA_20_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_21 = 0x28a4 +regCP_MES_INTERRUPT_DATA_21_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_22 = 0x28a5 +regCP_MES_INTERRUPT_DATA_22_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_23 = 0x28a6 +regCP_MES_INTERRUPT_DATA_23_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_24 = 0x28a7 +regCP_MES_INTERRUPT_DATA_24_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_25 = 0x28a8 +regCP_MES_INTERRUPT_DATA_25_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_26 = 0x28a9 +regCP_MES_INTERRUPT_DATA_26_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_27 = 0x28aa +regCP_MES_INTERRUPT_DATA_27_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_28 = 0x28ab +regCP_MES_INTERRUPT_DATA_28_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_29 = 0x28ac +regCP_MES_INTERRUPT_DATA_29_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_30 = 0x28ad +regCP_MES_INTERRUPT_DATA_30_BASE_IDX = 1 +regCP_MES_INTERRUPT_DATA_31 = 0x28ae +regCP_MES_INTERRUPT_DATA_31_BASE_IDX = 1 +regCP_MES_DC_APERTURE0_BASE = 0x28af +regCP_MES_DC_APERTURE0_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE0_MASK = 0x28b0 +regCP_MES_DC_APERTURE0_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE0_CNTL = 0x28b1 +regCP_MES_DC_APERTURE0_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE1_BASE = 0x28b2 +regCP_MES_DC_APERTURE1_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE1_MASK = 0x28b3 +regCP_MES_DC_APERTURE1_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE1_CNTL = 0x28b4 +regCP_MES_DC_APERTURE1_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE2_BASE = 0x28b5 +regCP_MES_DC_APERTURE2_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE2_MASK = 0x28b6 +regCP_MES_DC_APERTURE2_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE2_CNTL = 0x28b7 +regCP_MES_DC_APERTURE2_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE3_BASE = 0x28b8 +regCP_MES_DC_APERTURE3_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE3_MASK = 0x28b9 +regCP_MES_DC_APERTURE3_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE3_CNTL = 0x28ba +regCP_MES_DC_APERTURE3_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE4_BASE = 0x28bb +regCP_MES_DC_APERTURE4_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE4_MASK = 0x28bc +regCP_MES_DC_APERTURE4_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE4_CNTL = 0x28bd +regCP_MES_DC_APERTURE4_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE5_BASE = 0x28be +regCP_MES_DC_APERTURE5_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE5_MASK = 0x28bf +regCP_MES_DC_APERTURE5_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE5_CNTL = 0x28c0 +regCP_MES_DC_APERTURE5_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE6_BASE = 0x28c1 +regCP_MES_DC_APERTURE6_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE6_MASK = 0x28c2 +regCP_MES_DC_APERTURE6_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE6_CNTL = 0x28c3 +regCP_MES_DC_APERTURE6_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE7_BASE = 0x28c4 +regCP_MES_DC_APERTURE7_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE7_MASK = 0x28c5 +regCP_MES_DC_APERTURE7_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE7_CNTL = 0x28c6 +regCP_MES_DC_APERTURE7_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE8_BASE = 0x28c7 +regCP_MES_DC_APERTURE8_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE8_MASK = 0x28c8 +regCP_MES_DC_APERTURE8_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE8_CNTL = 0x28c9 +regCP_MES_DC_APERTURE8_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE9_BASE = 0x28ca +regCP_MES_DC_APERTURE9_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE9_MASK = 0x28cb +regCP_MES_DC_APERTURE9_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE9_CNTL = 0x28cc +regCP_MES_DC_APERTURE9_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE10_BASE = 0x28cd +regCP_MES_DC_APERTURE10_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE10_MASK = 0x28ce +regCP_MES_DC_APERTURE10_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE10_CNTL = 0x28cf +regCP_MES_DC_APERTURE10_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE11_BASE = 0x28d0 +regCP_MES_DC_APERTURE11_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE11_MASK = 0x28d1 +regCP_MES_DC_APERTURE11_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE11_CNTL = 0x28d2 +regCP_MES_DC_APERTURE11_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE12_BASE = 0x28d3 +regCP_MES_DC_APERTURE12_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE12_MASK = 0x28d4 +regCP_MES_DC_APERTURE12_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE12_CNTL = 0x28d5 +regCP_MES_DC_APERTURE12_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE13_BASE = 0x28d6 +regCP_MES_DC_APERTURE13_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE13_MASK = 0x28d7 +regCP_MES_DC_APERTURE13_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE13_CNTL = 0x28d8 +regCP_MES_DC_APERTURE13_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE14_BASE = 0x28d9 +regCP_MES_DC_APERTURE14_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE14_MASK = 0x28da +regCP_MES_DC_APERTURE14_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE14_CNTL = 0x28db +regCP_MES_DC_APERTURE14_CNTL_BASE_IDX = 1 +regCP_MES_DC_APERTURE15_BASE = 0x28dc +regCP_MES_DC_APERTURE15_BASE_BASE_IDX = 1 +regCP_MES_DC_APERTURE15_MASK = 0x28dd +regCP_MES_DC_APERTURE15_MASK_BASE_IDX = 1 +regCP_MES_DC_APERTURE15_CNTL = 0x28de +regCP_MES_DC_APERTURE15_CNTL_BASE_IDX = 1 +regCP_MEC_RS64_PRGRM_CNTR_START = 0x2900 +regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX = 1 +regCP_MEC_MTVEC_LO = 0x2901 +regCP_MEC_MTVEC_LO_BASE_IDX = 1 +regCP_MEC_MTVEC_HI = 0x2902 +regCP_MEC_MTVEC_HI_BASE_IDX = 1 +regCP_MEC_ISA_CNTL = 0x2903 +regCP_MEC_ISA_CNTL_BASE_IDX = 1 +regCP_MEC_RS64_CNTL = 0x2904 +regCP_MEC_RS64_CNTL_BASE_IDX = 1 +regCP_MEC_MIE_LO = 0x2905 +regCP_MEC_MIE_LO_BASE_IDX = 1 +regCP_MEC_MIE_HI = 0x2906 +regCP_MEC_MIE_HI_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT = 0x2907 +regCP_MEC_RS64_INTERRUPT_BASE_IDX = 1 +regCP_MEC_RS64_INSTR_PNTR = 0x2908 +regCP_MEC_RS64_INSTR_PNTR_BASE_IDX = 1 +regCP_MEC_MIP_LO = 0x2909 +regCP_MEC_MIP_LO_BASE_IDX = 1 +regCP_MEC_MIP_HI = 0x290a +regCP_MEC_MIP_HI_BASE_IDX = 1 +regCP_MEC_DC_BASE_CNTL = 0x290b +regCP_MEC_DC_BASE_CNTL_BASE_IDX = 1 +regCP_MEC_DC_OP_CNTL = 0x290c +regCP_MEC_DC_OP_CNTL_BASE_IDX = 1 +regCP_MEC_MTIMECMP_LO = 0x290d +regCP_MEC_MTIMECMP_LO_BASE_IDX = 1 +regCP_MEC_MTIMECMP_HI = 0x290e +regCP_MEC_MTIMECMP_HI_BASE_IDX = 1 +regCP_MEC_GP0_LO = 0x2910 +regCP_MEC_GP0_LO_BASE_IDX = 1 +regCP_MEC_GP0_HI = 0x2911 +regCP_MEC_GP0_HI_BASE_IDX = 1 +regCP_MEC_GP1_LO = 0x2912 +regCP_MEC_GP1_LO_BASE_IDX = 1 +regCP_MEC_GP1_HI = 0x2913 +regCP_MEC_GP1_HI_BASE_IDX = 1 +regCP_MEC_GP2_LO = 0x2914 +regCP_MEC_GP2_LO_BASE_IDX = 1 +regCP_MEC_GP2_HI = 0x2915 +regCP_MEC_GP2_HI_BASE_IDX = 1 +regCP_MEC_GP3_LO = 0x2916 +regCP_MEC_GP3_LO_BASE_IDX = 1 +regCP_MEC_GP3_HI = 0x2917 +regCP_MEC_GP3_HI_BASE_IDX = 1 +regCP_MEC_GP4_LO = 0x2918 +regCP_MEC_GP4_LO_BASE_IDX = 1 +regCP_MEC_GP4_HI = 0x2919 +regCP_MEC_GP4_HI_BASE_IDX = 1 +regCP_MEC_GP5_LO = 0x291a +regCP_MEC_GP5_LO_BASE_IDX = 1 +regCP_MEC_GP5_HI = 0x291b +regCP_MEC_GP5_HI_BASE_IDX = 1 +regCP_MEC_GP6_LO = 0x291c +regCP_MEC_GP6_LO_BASE_IDX = 1 +regCP_MEC_GP6_HI = 0x291d +regCP_MEC_GP6_HI_BASE_IDX = 1 +regCP_MEC_GP7_LO = 0x291e +regCP_MEC_GP7_LO_BASE_IDX = 1 +regCP_MEC_GP7_HI = 0x291f +regCP_MEC_GP7_HI_BASE_IDX = 1 +regCP_MEC_GP8_LO = 0x2920 +regCP_MEC_GP8_LO_BASE_IDX = 1 +regCP_MEC_GP8_HI = 0x2921 +regCP_MEC_GP8_HI_BASE_IDX = 1 +regCP_MEC_GP9_LO = 0x2922 +regCP_MEC_GP9_LO_BASE_IDX = 1 +regCP_MEC_GP9_HI = 0x2923 +regCP_MEC_GP9_HI_BASE_IDX = 1 +regCP_MEC_LOCAL_BASE0_LO = 0x2927 +regCP_MEC_LOCAL_BASE0_LO_BASE_IDX = 1 +regCP_MEC_LOCAL_BASE0_HI = 0x2928 +regCP_MEC_LOCAL_BASE0_HI_BASE_IDX = 1 +regCP_MEC_LOCAL_MASK0_LO = 0x2929 +regCP_MEC_LOCAL_MASK0_LO_BASE_IDX = 1 +regCP_MEC_LOCAL_MASK0_HI = 0x292a +regCP_MEC_LOCAL_MASK0_HI_BASE_IDX = 1 +regCP_MEC_LOCAL_APERTURE = 0x292b +regCP_MEC_LOCAL_APERTURE_BASE_IDX = 1 +regCP_MEC_LOCAL_INSTR_BASE_LO = 0x292c +regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 +regCP_MEC_LOCAL_INSTR_BASE_HI = 0x292d +regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 +regCP_MEC_LOCAL_INSTR_MASK_LO = 0x292e +regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 +regCP_MEC_LOCAL_INSTR_MASK_HI = 0x292f +regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 +regCP_MEC_LOCAL_INSTR_APERTURE = 0x2930 +regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX = 1 +regCP_MEC_LOCAL_SCRATCH_APERTURE = 0x2931 +regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 +regCP_MEC_LOCAL_SCRATCH_BASE_LO = 0x2932 +regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 +regCP_MEC_LOCAL_SCRATCH_BASE_HI = 0x2933 +regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 +regCP_MEC_RS64_PERFCOUNT_CNTL = 0x2934 +regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX = 1 +regCP_MEC_RS64_PENDING_INTERRUPT = 0x2935 +regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX = 1 +regCP_MEC_RS64_PRGRM_CNTR_START_HI = 0x2938 +regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_16 = 0x293a +regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_17 = 0x293b +regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_18 = 0x293c +regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_19 = 0x293d +regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_20 = 0x293e +regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_21 = 0x293f +regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_22 = 0x2940 +regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_23 = 0x2941 +regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_24 = 0x2942 +regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_25 = 0x2943 +regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_26 = 0x2944 +regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_27 = 0x2945 +regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_28 = 0x2946 +regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_29 = 0x2947 +regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_30 = 0x2948 +regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX = 1 +regCP_MEC_RS64_INTERRUPT_DATA_31 = 0x2949 +regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX = 1 +regCP_MEC_DC_APERTURE0_BASE = 0x294a +regCP_MEC_DC_APERTURE0_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE0_MASK = 0x294b +regCP_MEC_DC_APERTURE0_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE0_CNTL = 0x294c +regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE1_BASE = 0x294d +regCP_MEC_DC_APERTURE1_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE1_MASK = 0x294e +regCP_MEC_DC_APERTURE1_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE1_CNTL = 0x294f +regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE2_BASE = 0x2950 +regCP_MEC_DC_APERTURE2_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE2_MASK = 0x2951 +regCP_MEC_DC_APERTURE2_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE2_CNTL = 0x2952 +regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE3_BASE = 0x2953 +regCP_MEC_DC_APERTURE3_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE3_MASK = 0x2954 +regCP_MEC_DC_APERTURE3_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE3_CNTL = 0x2955 +regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE4_BASE = 0x2956 +regCP_MEC_DC_APERTURE4_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE4_MASK = 0x2957 +regCP_MEC_DC_APERTURE4_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE4_CNTL = 0x2958 +regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE5_BASE = 0x2959 +regCP_MEC_DC_APERTURE5_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE5_MASK = 0x295a +regCP_MEC_DC_APERTURE5_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE5_CNTL = 0x295b +regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE6_BASE = 0x295c +regCP_MEC_DC_APERTURE6_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE6_MASK = 0x295d +regCP_MEC_DC_APERTURE6_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE6_CNTL = 0x295e +regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE7_BASE = 0x295f +regCP_MEC_DC_APERTURE7_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE7_MASK = 0x2960 +regCP_MEC_DC_APERTURE7_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE7_CNTL = 0x2961 +regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE8_BASE = 0x2962 +regCP_MEC_DC_APERTURE8_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE8_MASK = 0x2963 +regCP_MEC_DC_APERTURE8_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE8_CNTL = 0x2964 +regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE9_BASE = 0x2965 +regCP_MEC_DC_APERTURE9_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE9_MASK = 0x2966 +regCP_MEC_DC_APERTURE9_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE9_CNTL = 0x2967 +regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE10_BASE = 0x2968 +regCP_MEC_DC_APERTURE10_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE10_MASK = 0x2969 +regCP_MEC_DC_APERTURE10_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE10_CNTL = 0x296a +regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE11_BASE = 0x296b +regCP_MEC_DC_APERTURE11_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE11_MASK = 0x296c +regCP_MEC_DC_APERTURE11_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE11_CNTL = 0x296d +regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE12_BASE = 0x296e +regCP_MEC_DC_APERTURE12_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE12_MASK = 0x296f +regCP_MEC_DC_APERTURE12_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE12_CNTL = 0x2970 +regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE13_BASE = 0x2971 +regCP_MEC_DC_APERTURE13_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE13_MASK = 0x2972 +regCP_MEC_DC_APERTURE13_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE13_CNTL = 0x2973 +regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE14_BASE = 0x2974 +regCP_MEC_DC_APERTURE14_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE14_MASK = 0x2975 +regCP_MEC_DC_APERTURE14_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE14_CNTL = 0x2976 +regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX = 1 +regCP_MEC_DC_APERTURE15_BASE = 0x2977 +regCP_MEC_DC_APERTURE15_BASE_BASE_IDX = 1 +regCP_MEC_DC_APERTURE15_MASK = 0x2978 +regCP_MEC_DC_APERTURE15_MASK_BASE_IDX = 1 +regCP_MEC_DC_APERTURE15_CNTL = 0x2979 +regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX = 1 +regCP_CPC_IC_OP_CNTL = 0x297a +regCP_CPC_IC_OP_CNTL_BASE_IDX = 1 +regCP_GFX_CNTL = 0x2a00 +regCP_GFX_CNTL_BASE_IDX = 1 +regCP_GFX_RS64_INTERRUPT0 = 0x2a01 +regCP_GFX_RS64_INTERRUPT0_BASE_IDX = 1 +regCP_GFX_RS64_INTR_EN0 = 0x2a02 +regCP_GFX_RS64_INTR_EN0_BASE_IDX = 1 +regCP_GFX_RS64_INTR_EN1 = 0x2a03 +regCP_GFX_RS64_INTR_EN1_BASE_IDX = 1 +regCP_GFX_RS64_DC_BASE_CNTL = 0x2a08 +regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX = 1 +regCP_GFX_RS64_DC_OP_CNTL = 0x2a09 +regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_BASE0_LO = 0x2a0a +regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_BASE0_HI = 0x2a0b +regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_MASK0_LO = 0x2a0c +regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_MASK0_HI = 0x2a0d +regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_APERTURE = 0x2a0e +regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_INSTR_BASE_LO = 0x2a0f +regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_INSTR_BASE_HI = 0x2a10 +regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_INSTR_MASK_LO = 0x2a11 +regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_INSTR_MASK_HI = 0x2a12 +regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_INSTR_APERTURE = 0x2a13 +regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE = 0x2a14 +regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO = 0x2a15 +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX = 1 +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI = 0x2a16 +regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX = 1 +regCP_GFX_RS64_PERFCOUNT_CNTL0 = 0x2a1a +regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_PERFCOUNT_CNTL1 = 0x2a1b +regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_MIP_LO0 = 0x2a1c +regCP_GFX_RS64_MIP_LO0_BASE_IDX = 1 +regCP_GFX_RS64_MIP_LO1 = 0x2a1d +regCP_GFX_RS64_MIP_LO1_BASE_IDX = 1 +regCP_GFX_RS64_MIP_HI0 = 0x2a1e +regCP_GFX_RS64_MIP_HI0_BASE_IDX = 1 +regCP_GFX_RS64_MIP_HI1 = 0x2a1f +regCP_GFX_RS64_MIP_HI1_BASE_IDX = 1 +regCP_GFX_RS64_MTIMECMP_LO0 = 0x2a20 +regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX = 1 +regCP_GFX_RS64_MTIMECMP_LO1 = 0x2a21 +regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX = 1 +regCP_GFX_RS64_MTIMECMP_HI0 = 0x2a22 +regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX = 1 +regCP_GFX_RS64_MTIMECMP_HI1 = 0x2a23 +regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP0_LO0 = 0x2a24 +regCP_GFX_RS64_GP0_LO0_BASE_IDX = 1 +regCP_GFX_RS64_GP0_LO1 = 0x2a25 +regCP_GFX_RS64_GP0_LO1_BASE_IDX = 1 +regCP_GFX_RS64_GP0_HI0 = 0x2a26 +regCP_GFX_RS64_GP0_HI0_BASE_IDX = 1 +regCP_GFX_RS64_GP0_HI1 = 0x2a27 +regCP_GFX_RS64_GP0_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP1_LO0 = 0x2a28 +regCP_GFX_RS64_GP1_LO0_BASE_IDX = 1 +regCP_GFX_RS64_GP1_LO1 = 0x2a29 +regCP_GFX_RS64_GP1_LO1_BASE_IDX = 1 +regCP_GFX_RS64_GP1_HI0 = 0x2a2a +regCP_GFX_RS64_GP1_HI0_BASE_IDX = 1 +regCP_GFX_RS64_GP1_HI1 = 0x2a2b +regCP_GFX_RS64_GP1_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP2_LO0 = 0x2a2c +regCP_GFX_RS64_GP2_LO0_BASE_IDX = 1 +regCP_GFX_RS64_GP2_LO1 = 0x2a2d +regCP_GFX_RS64_GP2_LO1_BASE_IDX = 1 +regCP_GFX_RS64_GP2_HI0 = 0x2a2e +regCP_GFX_RS64_GP2_HI0_BASE_IDX = 1 +regCP_GFX_RS64_GP2_HI1 = 0x2a2f +regCP_GFX_RS64_GP2_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP3_LO0 = 0x2a30 +regCP_GFX_RS64_GP3_LO0_BASE_IDX = 1 +regCP_GFX_RS64_GP3_LO1 = 0x2a31 +regCP_GFX_RS64_GP3_LO1_BASE_IDX = 1 +regCP_GFX_RS64_GP3_HI0 = 0x2a32 +regCP_GFX_RS64_GP3_HI0_BASE_IDX = 1 +regCP_GFX_RS64_GP3_HI1 = 0x2a33 +regCP_GFX_RS64_GP3_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP4_LO0 = 0x2a34 +regCP_GFX_RS64_GP4_LO0_BASE_IDX = 1 +regCP_GFX_RS64_GP4_LO1 = 0x2a35 +regCP_GFX_RS64_GP4_LO1_BASE_IDX = 1 +regCP_GFX_RS64_GP4_HI0 = 0x2a36 +regCP_GFX_RS64_GP4_HI0_BASE_IDX = 1 +regCP_GFX_RS64_GP4_HI1 = 0x2a37 +regCP_GFX_RS64_GP4_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP5_LO0 = 0x2a38 +regCP_GFX_RS64_GP5_LO0_BASE_IDX = 1 +regCP_GFX_RS64_GP5_LO1 = 0x2a39 +regCP_GFX_RS64_GP5_LO1_BASE_IDX = 1 +regCP_GFX_RS64_GP5_HI0 = 0x2a3a +regCP_GFX_RS64_GP5_HI0_BASE_IDX = 1 +regCP_GFX_RS64_GP5_HI1 = 0x2a3b +regCP_GFX_RS64_GP5_HI1_BASE_IDX = 1 +regCP_GFX_RS64_GP6_LO = 0x2a3c +regCP_GFX_RS64_GP6_LO_BASE_IDX = 1 +regCP_GFX_RS64_GP6_HI = 0x2a3d +regCP_GFX_RS64_GP6_HI_BASE_IDX = 1 +regCP_GFX_RS64_GP7_LO = 0x2a3e +regCP_GFX_RS64_GP7_LO_BASE_IDX = 1 +regCP_GFX_RS64_GP7_HI = 0x2a3f +regCP_GFX_RS64_GP7_HI_BASE_IDX = 1 +regCP_GFX_RS64_GP8_LO = 0x2a40 +regCP_GFX_RS64_GP8_LO_BASE_IDX = 1 +regCP_GFX_RS64_GP8_HI = 0x2a41 +regCP_GFX_RS64_GP8_HI_BASE_IDX = 1 +regCP_GFX_RS64_GP9_LO = 0x2a42 +regCP_GFX_RS64_GP9_LO_BASE_IDX = 1 +regCP_GFX_RS64_GP9_HI = 0x2a43 +regCP_GFX_RS64_GP9_HI_BASE_IDX = 1 +regCP_GFX_RS64_INSTR_PNTR0 = 0x2a44 +regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX = 1 +regCP_GFX_RS64_INSTR_PNTR1 = 0x2a45 +regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX = 1 +regCP_GFX_RS64_PENDING_INTERRUPT0 = 0x2a46 +regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX = 1 +regCP_GFX_RS64_PENDING_INTERRUPT1 = 0x2a47 +regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE0_BASE0 = 0x2a49 +regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE0_MASK0 = 0x2a4a +regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE0_CNTL0 = 0x2a4b +regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE1_BASE0 = 0x2a4c +regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE1_MASK0 = 0x2a4d +regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE1_CNTL0 = 0x2a4e +regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE2_BASE0 = 0x2a4f +regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE2_MASK0 = 0x2a50 +regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE2_CNTL0 = 0x2a51 +regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE3_BASE0 = 0x2a52 +regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE3_MASK0 = 0x2a53 +regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE3_CNTL0 = 0x2a54 +regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE4_BASE0 = 0x2a55 +regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE4_MASK0 = 0x2a56 +regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE4_CNTL0 = 0x2a57 +regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE5_BASE0 = 0x2a58 +regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE5_MASK0 = 0x2a59 +regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE5_CNTL0 = 0x2a5a +regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE6_BASE0 = 0x2a5b +regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE6_MASK0 = 0x2a5c +regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE6_CNTL0 = 0x2a5d +regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE7_BASE0 = 0x2a5e +regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE7_MASK0 = 0x2a5f +regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE7_CNTL0 = 0x2a60 +regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE8_BASE0 = 0x2a61 +regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE8_MASK0 = 0x2a62 +regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE8_CNTL0 = 0x2a63 +regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE9_BASE0 = 0x2a64 +regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE9_MASK0 = 0x2a65 +regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE9_CNTL0 = 0x2a66 +regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE10_BASE0 = 0x2a67 +regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE10_MASK0 = 0x2a68 +regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE10_CNTL0 = 0x2a69 +regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE11_BASE0 = 0x2a6a +regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE11_MASK0 = 0x2a6b +regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE11_CNTL0 = 0x2a6c +regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE12_BASE0 = 0x2a6d +regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE12_MASK0 = 0x2a6e +regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE12_CNTL0 = 0x2a6f +regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE13_BASE0 = 0x2a70 +regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE13_MASK0 = 0x2a71 +regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE13_CNTL0 = 0x2a72 +regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE14_BASE0 = 0x2a73 +regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE14_MASK0 = 0x2a74 +regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE14_CNTL0 = 0x2a75 +regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE15_BASE0 = 0x2a76 +regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE15_MASK0 = 0x2a77 +regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE15_CNTL0 = 0x2a78 +regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE0_BASE1 = 0x2a79 +regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE0_MASK1 = 0x2a7a +regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE0_CNTL1 = 0x2a7b +regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE1_BASE1 = 0x2a7c +regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE1_MASK1 = 0x2a7d +regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE1_CNTL1 = 0x2a7e +regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE2_BASE1 = 0x2a7f +regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE2_MASK1 = 0x2a80 +regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE2_CNTL1 = 0x2a81 +regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE3_BASE1 = 0x2a82 +regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE3_MASK1 = 0x2a83 +regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE3_CNTL1 = 0x2a84 +regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE4_BASE1 = 0x2a85 +regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE4_MASK1 = 0x2a86 +regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE4_CNTL1 = 0x2a87 +regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE5_BASE1 = 0x2a88 +regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE5_MASK1 = 0x2a89 +regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE5_CNTL1 = 0x2a8a +regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE6_BASE1 = 0x2a8b +regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE6_MASK1 = 0x2a8c +regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE6_CNTL1 = 0x2a8d +regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE7_BASE1 = 0x2a8e +regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE7_MASK1 = 0x2a8f +regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE7_CNTL1 = 0x2a90 +regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE8_BASE1 = 0x2a91 +regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE8_MASK1 = 0x2a92 +regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE8_CNTL1 = 0x2a93 +regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE9_BASE1 = 0x2a94 +regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE9_MASK1 = 0x2a95 +regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE9_CNTL1 = 0x2a96 +regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE10_BASE1 = 0x2a97 +regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE10_MASK1 = 0x2a98 +regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE10_CNTL1 = 0x2a99 +regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE11_BASE1 = 0x2a9a +regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE11_MASK1 = 0x2a9b +regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE11_CNTL1 = 0x2a9c +regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE12_BASE1 = 0x2a9d +regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE12_MASK1 = 0x2a9e +regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE12_CNTL1 = 0x2a9f +regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE13_BASE1 = 0x2aa0 +regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE13_MASK1 = 0x2aa1 +regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE13_CNTL1 = 0x2aa2 +regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE14_BASE1 = 0x2aa3 +regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE14_MASK1 = 0x2aa4 +regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE14_CNTL1 = 0x2aa5 +regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE15_BASE1 = 0x2aa6 +regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE15_MASK1 = 0x2aa7 +regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX = 1 +regCP_GFX_RS64_DC_APERTURE15_CNTL1 = 0x2aa8 +regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX = 1 +regCP_GFX_RS64_INTERRUPT1 = 0x2aac +regCP_GFX_RS64_INTERRUPT1_BASE_IDX = 1 +regGL1_DRAM_BURST_MASK = 0x2d02 +regGL1_DRAM_BURST_MASK_BASE_IDX = 1 +regGL1_ARB_STATUS = 0x2d03 +regGL1_ARB_STATUS_BASE_IDX = 1 +regGL1I_GL1R_REP_FGCG_OVERRIDE = 0x2d05 +regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX = 1 +regGL1C_STATUS = 0x2d41 +regGL1C_STATUS_BASE_IDX = 1 +regGL1C_UTCL0_CNTL1 = 0x2d42 +regGL1C_UTCL0_CNTL1_BASE_IDX = 1 +regGL1C_UTCL0_CNTL2 = 0x2d43 +regGL1C_UTCL0_CNTL2_BASE_IDX = 1 +regGL1C_UTCL0_STATUS = 0x2d44 +regGL1C_UTCL0_STATUS_BASE_IDX = 1 +regGL1C_UTCL0_RETRY = 0x2d45 +regGL1C_UTCL0_RETRY_BASE_IDX = 1 +regCH_ARB_CTRL = 0x2d80 +regCH_ARB_CTRL_BASE_IDX = 1 +regCH_DRAM_BURST_MASK = 0x2d82 +regCH_DRAM_BURST_MASK_BASE_IDX = 1 +regCH_ARB_STATUS = 0x2d83 +regCH_ARB_STATUS_BASE_IDX = 1 +regCH_DRAM_BURST_CTRL = 0x2d84 +regCH_DRAM_BURST_CTRL_BASE_IDX = 1 +regCHA_CHC_CREDITS = 0x2d88 +regCHA_CHC_CREDITS_BASE_IDX = 1 +regCHA_CLIENT_FREE_DELAY = 0x2d89 +regCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 +regCHI_CHR_REP_FGCG_OVERRIDE = 0x2d8c +regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX = 1 +regCH_VC5_ENABLE = 0x2d94 +regCH_VC5_ENABLE_BASE_IDX = 1 +regCHC_CTRL = 0x2dc0 +regCHC_CTRL_BASE_IDX = 1 +regCHC_STATUS = 0x2dc1 +regCHC_STATUS_BASE_IDX = 1 +regCHCG_CTRL = 0x2dc2 +regCHCG_CTRL_BASE_IDX = 1 +regCHCG_STATUS = 0x2dc3 +regCHCG_STATUS_BASE_IDX = 1 +regGL2C_CTRL = 0x2e00 +regGL2C_CTRL_BASE_IDX = 1 +regGL2C_CTRL2 = 0x2e01 +regGL2C_CTRL2_BASE_IDX = 1 +regGL2C_ADDR_MATCH_MASK = 0x2e03 +regGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 +regGL2C_ADDR_MATCH_SIZE = 0x2e04 +regGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 +regGL2C_WBINVL2 = 0x2e05 +regGL2C_WBINVL2_BASE_IDX = 1 +regGL2C_SOFT_RESET = 0x2e06 +regGL2C_SOFT_RESET_BASE_IDX = 1 +regGL2C_CM_CTRL0 = 0x2e07 +regGL2C_CM_CTRL0_BASE_IDX = 1 +regGL2C_CM_CTRL1 = 0x2e08 +regGL2C_CM_CTRL1_BASE_IDX = 1 +regGL2C_CM_STALL = 0x2e09 +regGL2C_CM_STALL_BASE_IDX = 1 +regGL2C_CTRL3 = 0x2e0c +regGL2C_CTRL3_BASE_IDX = 1 +regGL2C_LB_CTR_CTRL = 0x2e0d +regGL2C_LB_CTR_CTRL_BASE_IDX = 1 +regGL2C_LB_DATA0 = 0x2e0e +regGL2C_LB_DATA0_BASE_IDX = 1 +regGL2C_LB_DATA1 = 0x2e0f +regGL2C_LB_DATA1_BASE_IDX = 1 +regGL2C_LB_DATA2 = 0x2e10 +regGL2C_LB_DATA2_BASE_IDX = 1 +regGL2C_LB_DATA3 = 0x2e11 +regGL2C_LB_DATA3_BASE_IDX = 1 +regGL2C_LB_CTR_SEL0 = 0x2e12 +regGL2C_LB_CTR_SEL0_BASE_IDX = 1 +regGL2C_LB_CTR_SEL1 = 0x2e13 +regGL2C_LB_CTR_SEL1_BASE_IDX = 1 +regGL2C_CTRL4 = 0x2e17 +regGL2C_CTRL4_BASE_IDX = 1 +regGL2C_DISCARD_STALL_CTRL = 0x2e18 +regGL2C_DISCARD_STALL_CTRL_BASE_IDX = 1 +regGL2A_ADDR_MATCH_CTRL = 0x2e20 +regGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 +regGL2A_ADDR_MATCH_MASK = 0x2e21 +regGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 +regGL2A_ADDR_MATCH_SIZE = 0x2e22 +regGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 +regGL2A_PRIORITY_CTRL = 0x2e23 +regGL2A_PRIORITY_CTRL_BASE_IDX = 1 +regGL2A_RESP_THROTTLE_CTRL = 0x2e2a +regGL2A_RESP_THROTTLE_CTRL_BASE_IDX = 1 +regGL1H_ARB_CTRL = 0x2e40 +regGL1H_ARB_CTRL_BASE_IDX = 1 +regGL1H_GL1_CREDITS = 0x2e41 +regGL1H_GL1_CREDITS_BASE_IDX = 1 +regGL1H_BURST_MASK = 0x2e42 +regGL1H_BURST_MASK_BASE_IDX = 1 +regGL1H_BURST_CTRL = 0x2e43 +regGL1H_BURST_CTRL_BASE_IDX = 1 +regGL1H_ARB_STATUS = 0x2e44 +regGL1H_ARB_STATUS_BASE_IDX = 1 +regCPG_PERFCOUNTER1_LO = 0x3000 +regCPG_PERFCOUNTER1_LO_BASE_IDX = 1 +regCPG_PERFCOUNTER1_HI = 0x3001 +regCPG_PERFCOUNTER1_HI_BASE_IDX = 1 +regCPG_PERFCOUNTER0_LO = 0x3002 +regCPG_PERFCOUNTER0_LO_BASE_IDX = 1 +regCPG_PERFCOUNTER0_HI = 0x3003 +regCPG_PERFCOUNTER0_HI_BASE_IDX = 1 +regCPC_PERFCOUNTER1_LO = 0x3004 +regCPC_PERFCOUNTER1_LO_BASE_IDX = 1 +regCPC_PERFCOUNTER1_HI = 0x3005 +regCPC_PERFCOUNTER1_HI_BASE_IDX = 1 +regCPC_PERFCOUNTER0_LO = 0x3006 +regCPC_PERFCOUNTER0_LO_BASE_IDX = 1 +regCPC_PERFCOUNTER0_HI = 0x3007 +regCPC_PERFCOUNTER0_HI_BASE_IDX = 1 +regCPF_PERFCOUNTER1_LO = 0x3008 +regCPF_PERFCOUNTER1_LO_BASE_IDX = 1 +regCPF_PERFCOUNTER1_HI = 0x3009 +regCPF_PERFCOUNTER1_HI_BASE_IDX = 1 +regCPF_PERFCOUNTER0_LO = 0x300a +regCPF_PERFCOUNTER0_LO_BASE_IDX = 1 +regCPF_PERFCOUNTER0_HI = 0x300b +regCPF_PERFCOUNTER0_HI_BASE_IDX = 1 +regCPF_LATENCY_STATS_DATA = 0x300c +regCPF_LATENCY_STATS_DATA_BASE_IDX = 1 +regCPG_LATENCY_STATS_DATA = 0x300d +regCPG_LATENCY_STATS_DATA_BASE_IDX = 1 +regCPC_LATENCY_STATS_DATA = 0x300e +regCPC_LATENCY_STATS_DATA_BASE_IDX = 1 +regGRBM_PERFCOUNTER0_LO = 0x3040 +regGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 +regGRBM_PERFCOUNTER0_HI = 0x3041 +regGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 +regGRBM_PERFCOUNTER1_LO = 0x3043 +regGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 +regGRBM_PERFCOUNTER1_HI = 0x3044 +regGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 +regGRBM_SE0_PERFCOUNTER_LO = 0x3045 +regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE0_PERFCOUNTER_HI = 0x3046 +regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 +regGRBM_SE1_PERFCOUNTER_LO = 0x3047 +regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE1_PERFCOUNTER_HI = 0x3048 +regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 +regGRBM_SE2_PERFCOUNTER_LO = 0x3049 +regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE2_PERFCOUNTER_HI = 0x304a +regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 +regGRBM_SE3_PERFCOUNTER_LO = 0x304b +regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE3_PERFCOUNTER_HI = 0x304c +regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 +regGRBM_SE4_PERFCOUNTER_LO = 0x304d +regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE4_PERFCOUNTER_HI = 0x304e +regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX = 1 +regGRBM_SE5_PERFCOUNTER_LO = 0x304f +regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE5_PERFCOUNTER_HI = 0x3050 +regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX = 1 +regGRBM_SE6_PERFCOUNTER_LO = 0x3051 +regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX = 1 +regGRBM_SE6_PERFCOUNTER_HI = 0x3052 +regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX = 1 +regGE1_PERFCOUNTER0_LO = 0x30a4 +regGE1_PERFCOUNTER0_LO_BASE_IDX = 1 +regGE1_PERFCOUNTER0_HI = 0x30a5 +regGE1_PERFCOUNTER0_HI_BASE_IDX = 1 +regGE1_PERFCOUNTER1_LO = 0x30a6 +regGE1_PERFCOUNTER1_LO_BASE_IDX = 1 +regGE1_PERFCOUNTER1_HI = 0x30a7 +regGE1_PERFCOUNTER1_HI_BASE_IDX = 1 +regGE1_PERFCOUNTER2_LO = 0x30a8 +regGE1_PERFCOUNTER2_LO_BASE_IDX = 1 +regGE1_PERFCOUNTER2_HI = 0x30a9 +regGE1_PERFCOUNTER2_HI_BASE_IDX = 1 +regGE1_PERFCOUNTER3_LO = 0x30aa +regGE1_PERFCOUNTER3_LO_BASE_IDX = 1 +regGE1_PERFCOUNTER3_HI = 0x30ab +regGE1_PERFCOUNTER3_HI_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER0_LO = 0x30ac +regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER0_HI = 0x30ad +regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER1_LO = 0x30ae +regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER1_HI = 0x30af +regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER2_LO = 0x30b0 +regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER2_HI = 0x30b1 +regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER3_LO = 0x30b2 +regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER3_HI = 0x30b3 +regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER0_LO = 0x30b4 +regGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER0_HI = 0x30b5 +regGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER1_LO = 0x30b6 +regGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER1_HI = 0x30b7 +regGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER2_LO = 0x30b8 +regGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER2_HI = 0x30b9 +regGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER3_LO = 0x30ba +regGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER3_HI = 0x30bb +regGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 +regPA_SU_PERFCOUNTER0_LO = 0x3100 +regPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 +regPA_SU_PERFCOUNTER0_HI = 0x3101 +regPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 +regPA_SU_PERFCOUNTER1_LO = 0x3102 +regPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 +regPA_SU_PERFCOUNTER1_HI = 0x3103 +regPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 +regPA_SU_PERFCOUNTER2_LO = 0x3104 +regPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 +regPA_SU_PERFCOUNTER2_HI = 0x3105 +regPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 +regPA_SU_PERFCOUNTER3_LO = 0x3106 +regPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 +regPA_SU_PERFCOUNTER3_HI = 0x3107 +regPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER0_LO = 0x3140 +regPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER0_HI = 0x3141 +regPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER1_LO = 0x3142 +regPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER1_HI = 0x3143 +regPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER2_LO = 0x3144 +regPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER2_HI = 0x3145 +regPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER3_LO = 0x3146 +regPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER3_HI = 0x3147 +regPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER4_LO = 0x3148 +regPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER4_HI = 0x3149 +regPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER5_LO = 0x314a +regPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER5_HI = 0x314b +regPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER6_LO = 0x314c +regPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER6_HI = 0x314d +regPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 +regPA_SC_PERFCOUNTER7_LO = 0x314e +regPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 +regPA_SC_PERFCOUNTER7_HI = 0x314f +regPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER0_HI = 0x3180 +regSPI_PERFCOUNTER0_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER0_LO = 0x3181 +regSPI_PERFCOUNTER0_LO_BASE_IDX = 1 +regSPI_PERFCOUNTER1_HI = 0x3182 +regSPI_PERFCOUNTER1_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER1_LO = 0x3183 +regSPI_PERFCOUNTER1_LO_BASE_IDX = 1 +regSPI_PERFCOUNTER2_HI = 0x3184 +regSPI_PERFCOUNTER2_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER2_LO = 0x3185 +regSPI_PERFCOUNTER2_LO_BASE_IDX = 1 +regSPI_PERFCOUNTER3_HI = 0x3186 +regSPI_PERFCOUNTER3_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER3_LO = 0x3187 +regSPI_PERFCOUNTER3_LO_BASE_IDX = 1 +regSPI_PERFCOUNTER4_HI = 0x3188 +regSPI_PERFCOUNTER4_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER4_LO = 0x3189 +regSPI_PERFCOUNTER4_LO_BASE_IDX = 1 +regSPI_PERFCOUNTER5_HI = 0x318a +regSPI_PERFCOUNTER5_HI_BASE_IDX = 1 +regSPI_PERFCOUNTER5_LO = 0x318b +regSPI_PERFCOUNTER5_LO_BASE_IDX = 1 +regPC_PERFCOUNTER0_HI = 0x318c +regPC_PERFCOUNTER0_HI_BASE_IDX = 1 +regPC_PERFCOUNTER0_LO = 0x318d +regPC_PERFCOUNTER0_LO_BASE_IDX = 1 +regPC_PERFCOUNTER1_HI = 0x318e +regPC_PERFCOUNTER1_HI_BASE_IDX = 1 +regPC_PERFCOUNTER1_LO = 0x318f +regPC_PERFCOUNTER1_LO_BASE_IDX = 1 +regPC_PERFCOUNTER2_HI = 0x3190 +regPC_PERFCOUNTER2_HI_BASE_IDX = 1 +regPC_PERFCOUNTER2_LO = 0x3191 +regPC_PERFCOUNTER2_LO_BASE_IDX = 1 +regPC_PERFCOUNTER3_HI = 0x3192 +regPC_PERFCOUNTER3_HI_BASE_IDX = 1 +regPC_PERFCOUNTER3_LO = 0x3193 +regPC_PERFCOUNTER3_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER0_LO = 0x31c0 +regSQ_PERFCOUNTER0_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER1_LO = 0x31c2 +regSQ_PERFCOUNTER1_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER2_LO = 0x31c4 +regSQ_PERFCOUNTER2_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER3_LO = 0x31c6 +regSQ_PERFCOUNTER3_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER4_LO = 0x31c8 +regSQ_PERFCOUNTER4_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER5_LO = 0x31ca +regSQ_PERFCOUNTER5_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER6_LO = 0x31cc +regSQ_PERFCOUNTER6_LO_BASE_IDX = 1 +regSQ_PERFCOUNTER7_LO = 0x31ce +regSQ_PERFCOUNTER7_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER0_LO = 0x31e4 +regSQG_PERFCOUNTER0_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER0_HI = 0x31e5 +regSQG_PERFCOUNTER0_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER1_LO = 0x31e6 +regSQG_PERFCOUNTER1_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER1_HI = 0x31e7 +regSQG_PERFCOUNTER1_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER2_LO = 0x31e8 +regSQG_PERFCOUNTER2_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER2_HI = 0x31e9 +regSQG_PERFCOUNTER2_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER3_LO = 0x31ea +regSQG_PERFCOUNTER3_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER3_HI = 0x31eb +regSQG_PERFCOUNTER3_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER4_LO = 0x31ec +regSQG_PERFCOUNTER4_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER4_HI = 0x31ed +regSQG_PERFCOUNTER4_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER5_LO = 0x31ee +regSQG_PERFCOUNTER5_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER5_HI = 0x31ef +regSQG_PERFCOUNTER5_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER6_LO = 0x31f0 +regSQG_PERFCOUNTER6_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER6_HI = 0x31f1 +regSQG_PERFCOUNTER6_HI_BASE_IDX = 1 +regSQG_PERFCOUNTER7_LO = 0x31f2 +regSQG_PERFCOUNTER7_LO_BASE_IDX = 1 +regSQG_PERFCOUNTER7_HI = 0x31f3 +regSQG_PERFCOUNTER7_HI_BASE_IDX = 1 +regSX_PERFCOUNTER0_LO = 0x3240 +regSX_PERFCOUNTER0_LO_BASE_IDX = 1 +regSX_PERFCOUNTER0_HI = 0x3241 +regSX_PERFCOUNTER0_HI_BASE_IDX = 1 +regSX_PERFCOUNTER1_LO = 0x3242 +regSX_PERFCOUNTER1_LO_BASE_IDX = 1 +regSX_PERFCOUNTER1_HI = 0x3243 +regSX_PERFCOUNTER1_HI_BASE_IDX = 1 +regSX_PERFCOUNTER2_LO = 0x3244 +regSX_PERFCOUNTER2_LO_BASE_IDX = 1 +regSX_PERFCOUNTER2_HI = 0x3245 +regSX_PERFCOUNTER2_HI_BASE_IDX = 1 +regSX_PERFCOUNTER3_LO = 0x3246 +regSX_PERFCOUNTER3_LO_BASE_IDX = 1 +regSX_PERFCOUNTER3_HI = 0x3247 +regSX_PERFCOUNTER3_HI_BASE_IDX = 1 +regGCEA_PERFCOUNTER2_LO = 0x3260 +regGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 +regGCEA_PERFCOUNTER2_HI = 0x3261 +regGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 +regGCEA_PERFCOUNTER_LO = 0x3262 +regGCEA_PERFCOUNTER_LO_BASE_IDX = 1 +regGCEA_PERFCOUNTER_HI = 0x3263 +regGCEA_PERFCOUNTER_HI_BASE_IDX = 1 +regGDS_PERFCOUNTER0_LO = 0x3280 +regGDS_PERFCOUNTER0_LO_BASE_IDX = 1 +regGDS_PERFCOUNTER0_HI = 0x3281 +regGDS_PERFCOUNTER0_HI_BASE_IDX = 1 +regGDS_PERFCOUNTER1_LO = 0x3282 +regGDS_PERFCOUNTER1_LO_BASE_IDX = 1 +regGDS_PERFCOUNTER1_HI = 0x3283 +regGDS_PERFCOUNTER1_HI_BASE_IDX = 1 +regGDS_PERFCOUNTER2_LO = 0x3284 +regGDS_PERFCOUNTER2_LO_BASE_IDX = 1 +regGDS_PERFCOUNTER2_HI = 0x3285 +regGDS_PERFCOUNTER2_HI_BASE_IDX = 1 +regGDS_PERFCOUNTER3_LO = 0x3286 +regGDS_PERFCOUNTER3_LO_BASE_IDX = 1 +regGDS_PERFCOUNTER3_HI = 0x3287 +regGDS_PERFCOUNTER3_HI_BASE_IDX = 1 +regTA_PERFCOUNTER0_LO = 0x32c0 +regTA_PERFCOUNTER0_LO_BASE_IDX = 1 +regTA_PERFCOUNTER0_HI = 0x32c1 +regTA_PERFCOUNTER0_HI_BASE_IDX = 1 +regTA_PERFCOUNTER1_LO = 0x32c2 +regTA_PERFCOUNTER1_LO_BASE_IDX = 1 +regTA_PERFCOUNTER1_HI = 0x32c3 +regTA_PERFCOUNTER1_HI_BASE_IDX = 1 +regTD_PERFCOUNTER0_LO = 0x3300 +regTD_PERFCOUNTER0_LO_BASE_IDX = 1 +regTD_PERFCOUNTER0_HI = 0x3301 +regTD_PERFCOUNTER0_HI_BASE_IDX = 1 +regTD_PERFCOUNTER1_LO = 0x3302 +regTD_PERFCOUNTER1_LO_BASE_IDX = 1 +regTD_PERFCOUNTER1_HI = 0x3303 +regTD_PERFCOUNTER1_HI_BASE_IDX = 1 +regTCP_PERFCOUNTER0_LO = 0x3340 +regTCP_PERFCOUNTER0_LO_BASE_IDX = 1 +regTCP_PERFCOUNTER0_HI = 0x3341 +regTCP_PERFCOUNTER0_HI_BASE_IDX = 1 +regTCP_PERFCOUNTER1_LO = 0x3342 +regTCP_PERFCOUNTER1_LO_BASE_IDX = 1 +regTCP_PERFCOUNTER1_HI = 0x3343 +regTCP_PERFCOUNTER1_HI_BASE_IDX = 1 +regTCP_PERFCOUNTER2_LO = 0x3344 +regTCP_PERFCOUNTER2_LO_BASE_IDX = 1 +regTCP_PERFCOUNTER2_HI = 0x3345 +regTCP_PERFCOUNTER2_HI_BASE_IDX = 1 +regTCP_PERFCOUNTER3_LO = 0x3346 +regTCP_PERFCOUNTER3_LO_BASE_IDX = 1 +regTCP_PERFCOUNTER3_HI = 0x3347 +regTCP_PERFCOUNTER3_HI_BASE_IDX = 1 +regTCP_PERFCOUNTER_FILTER = 0x3348 +regTCP_PERFCOUNTER_FILTER_BASE_IDX = 1 +regTCP_PERFCOUNTER_FILTER2 = 0x3349 +regTCP_PERFCOUNTER_FILTER2_BASE_IDX = 1 +regTCP_PERFCOUNTER_FILTER_EN = 0x334a +regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 1 +regGL2C_PERFCOUNTER0_LO = 0x3380 +regGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 +regGL2C_PERFCOUNTER0_HI = 0x3381 +regGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 +regGL2C_PERFCOUNTER1_LO = 0x3382 +regGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 +regGL2C_PERFCOUNTER1_HI = 0x3383 +regGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 +regGL2C_PERFCOUNTER2_LO = 0x3384 +regGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 +regGL2C_PERFCOUNTER2_HI = 0x3385 +regGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 +regGL2C_PERFCOUNTER3_LO = 0x3386 +regGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 +regGL2C_PERFCOUNTER3_HI = 0x3387 +regGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 +regGL2A_PERFCOUNTER0_LO = 0x3390 +regGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 +regGL2A_PERFCOUNTER0_HI = 0x3391 +regGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 +regGL2A_PERFCOUNTER1_LO = 0x3392 +regGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 +regGL2A_PERFCOUNTER1_HI = 0x3393 +regGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 +regGL2A_PERFCOUNTER2_LO = 0x3394 +regGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 +regGL2A_PERFCOUNTER2_HI = 0x3395 +regGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 +regGL2A_PERFCOUNTER3_LO = 0x3396 +regGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 +regGL2A_PERFCOUNTER3_HI = 0x3397 +regGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 +regGL1C_PERFCOUNTER0_LO = 0x33a0 +regGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 +regGL1C_PERFCOUNTER0_HI = 0x33a1 +regGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 +regGL1C_PERFCOUNTER1_LO = 0x33a2 +regGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 +regGL1C_PERFCOUNTER1_HI = 0x33a3 +regGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 +regGL1C_PERFCOUNTER2_LO = 0x33a4 +regGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 +regGL1C_PERFCOUNTER2_HI = 0x33a5 +regGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 +regGL1C_PERFCOUNTER3_LO = 0x33a6 +regGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 +regGL1C_PERFCOUNTER3_HI = 0x33a7 +regGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 +regCHC_PERFCOUNTER0_LO = 0x33c0 +regCHC_PERFCOUNTER0_LO_BASE_IDX = 1 +regCHC_PERFCOUNTER0_HI = 0x33c1 +regCHC_PERFCOUNTER0_HI_BASE_IDX = 1 +regCHC_PERFCOUNTER1_LO = 0x33c2 +regCHC_PERFCOUNTER1_LO_BASE_IDX = 1 +regCHC_PERFCOUNTER1_HI = 0x33c3 +regCHC_PERFCOUNTER1_HI_BASE_IDX = 1 +regCHC_PERFCOUNTER2_LO = 0x33c4 +regCHC_PERFCOUNTER2_LO_BASE_IDX = 1 +regCHC_PERFCOUNTER2_HI = 0x33c5 +regCHC_PERFCOUNTER2_HI_BASE_IDX = 1 +regCHC_PERFCOUNTER3_LO = 0x33c6 +regCHC_PERFCOUNTER3_LO_BASE_IDX = 1 +regCHC_PERFCOUNTER3_HI = 0x33c7 +regCHC_PERFCOUNTER3_HI_BASE_IDX = 1 +regCHCG_PERFCOUNTER0_LO = 0x33c8 +regCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 +regCHCG_PERFCOUNTER0_HI = 0x33c9 +regCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 +regCHCG_PERFCOUNTER1_LO = 0x33ca +regCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 +regCHCG_PERFCOUNTER1_HI = 0x33cb +regCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 +regCHCG_PERFCOUNTER2_LO = 0x33cc +regCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 +regCHCG_PERFCOUNTER2_HI = 0x33cd +regCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 +regCHCG_PERFCOUNTER3_LO = 0x33ce +regCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 +regCHCG_PERFCOUNTER3_HI = 0x33cf +regCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 +regCB_PERFCOUNTER0_LO = 0x3406 +regCB_PERFCOUNTER0_LO_BASE_IDX = 1 +regCB_PERFCOUNTER0_HI = 0x3407 +regCB_PERFCOUNTER0_HI_BASE_IDX = 1 +regCB_PERFCOUNTER1_LO = 0x3408 +regCB_PERFCOUNTER1_LO_BASE_IDX = 1 +regCB_PERFCOUNTER1_HI = 0x3409 +regCB_PERFCOUNTER1_HI_BASE_IDX = 1 +regCB_PERFCOUNTER2_LO = 0x340a +regCB_PERFCOUNTER2_LO_BASE_IDX = 1 +regCB_PERFCOUNTER2_HI = 0x340b +regCB_PERFCOUNTER2_HI_BASE_IDX = 1 +regCB_PERFCOUNTER3_LO = 0x340c +regCB_PERFCOUNTER3_LO_BASE_IDX = 1 +regCB_PERFCOUNTER3_HI = 0x340d +regCB_PERFCOUNTER3_HI_BASE_IDX = 1 +regDB_PERFCOUNTER0_LO = 0x3440 +regDB_PERFCOUNTER0_LO_BASE_IDX = 1 +regDB_PERFCOUNTER0_HI = 0x3441 +regDB_PERFCOUNTER0_HI_BASE_IDX = 1 +regDB_PERFCOUNTER1_LO = 0x3442 +regDB_PERFCOUNTER1_LO_BASE_IDX = 1 +regDB_PERFCOUNTER1_HI = 0x3443 +regDB_PERFCOUNTER1_HI_BASE_IDX = 1 +regDB_PERFCOUNTER2_LO = 0x3444 +regDB_PERFCOUNTER2_LO_BASE_IDX = 1 +regDB_PERFCOUNTER2_HI = 0x3445 +regDB_PERFCOUNTER2_HI_BASE_IDX = 1 +regDB_PERFCOUNTER3_LO = 0x3446 +regDB_PERFCOUNTER3_LO_BASE_IDX = 1 +regDB_PERFCOUNTER3_HI = 0x3447 +regDB_PERFCOUNTER3_HI_BASE_IDX = 1 +regRLC_PERFCOUNTER0_LO = 0x3480 +regRLC_PERFCOUNTER0_LO_BASE_IDX = 1 +regRLC_PERFCOUNTER0_HI = 0x3481 +regRLC_PERFCOUNTER0_HI_BASE_IDX = 1 +regRLC_PERFCOUNTER1_LO = 0x3482 +regRLC_PERFCOUNTER1_LO_BASE_IDX = 1 +regRLC_PERFCOUNTER1_HI = 0x3483 +regRLC_PERFCOUNTER1_HI_BASE_IDX = 1 +regRMI_PERFCOUNTER0_LO = 0x34c0 +regRMI_PERFCOUNTER0_LO_BASE_IDX = 1 +regRMI_PERFCOUNTER0_HI = 0x34c1 +regRMI_PERFCOUNTER0_HI_BASE_IDX = 1 +regRMI_PERFCOUNTER1_LO = 0x34c2 +regRMI_PERFCOUNTER1_LO_BASE_IDX = 1 +regRMI_PERFCOUNTER1_HI = 0x34c3 +regRMI_PERFCOUNTER1_HI_BASE_IDX = 1 +regRMI_PERFCOUNTER2_LO = 0x34c4 +regRMI_PERFCOUNTER2_LO_BASE_IDX = 1 +regRMI_PERFCOUNTER2_HI = 0x34c5 +regRMI_PERFCOUNTER2_HI_BASE_IDX = 1 +regRMI_PERFCOUNTER3_LO = 0x34c6 +regRMI_PERFCOUNTER3_LO_BASE_IDX = 1 +regRMI_PERFCOUNTER3_HI = 0x34c7 +regRMI_PERFCOUNTER3_HI_BASE_IDX = 1 +regGCR_PERFCOUNTER0_LO = 0x3520 +regGCR_PERFCOUNTER0_LO_BASE_IDX = 1 +regGCR_PERFCOUNTER0_HI = 0x3521 +regGCR_PERFCOUNTER0_HI_BASE_IDX = 1 +regGCR_PERFCOUNTER1_LO = 0x3522 +regGCR_PERFCOUNTER1_LO_BASE_IDX = 1 +regGCR_PERFCOUNTER1_HI = 0x3523 +regGCR_PERFCOUNTER1_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER0_LO = 0x3580 +regPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER0_HI = 0x3581 +regPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER1_LO = 0x3582 +regPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER1_HI = 0x3583 +regPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER2_LO = 0x3584 +regPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER2_HI = 0x3585 +regPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER3_LO = 0x3586 +regPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER3_HI = 0x3587 +regPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER4_LO = 0x3588 +regPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER4_HI = 0x3589 +regPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER5_LO = 0x358a +regPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER5_HI = 0x358b +regPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER6_LO = 0x358c +regPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER6_HI = 0x358d +regPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 +regPA_PH_PERFCOUNTER7_LO = 0x358e +regPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 +regPA_PH_PERFCOUNTER7_HI = 0x358f +regPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 +regUTCL1_PERFCOUNTER0_LO = 0x35a0 +regUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 +regUTCL1_PERFCOUNTER0_HI = 0x35a1 +regUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 +regUTCL1_PERFCOUNTER1_LO = 0x35a2 +regUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 +regUTCL1_PERFCOUNTER1_HI = 0x35a3 +regUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 +regUTCL1_PERFCOUNTER2_LO = 0x35a4 +regUTCL1_PERFCOUNTER2_LO_BASE_IDX = 1 +regUTCL1_PERFCOUNTER2_HI = 0x35a5 +regUTCL1_PERFCOUNTER2_HI_BASE_IDX = 1 +regUTCL1_PERFCOUNTER3_LO = 0x35a6 +regUTCL1_PERFCOUNTER3_LO_BASE_IDX = 1 +regUTCL1_PERFCOUNTER3_HI = 0x35a7 +regUTCL1_PERFCOUNTER3_HI_BASE_IDX = 1 +regGL1A_PERFCOUNTER0_LO = 0x35c0 +regGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 +regGL1A_PERFCOUNTER0_HI = 0x35c1 +regGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 +regGL1A_PERFCOUNTER1_LO = 0x35c2 +regGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 +regGL1A_PERFCOUNTER1_HI = 0x35c3 +regGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 +regGL1A_PERFCOUNTER2_LO = 0x35c4 +regGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 +regGL1A_PERFCOUNTER2_HI = 0x35c5 +regGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 +regGL1A_PERFCOUNTER3_LO = 0x35c6 +regGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 +regGL1A_PERFCOUNTER3_HI = 0x35c7 +regGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 +regGL1H_PERFCOUNTER0_LO = 0x35d0 +regGL1H_PERFCOUNTER0_LO_BASE_IDX = 1 +regGL1H_PERFCOUNTER0_HI = 0x35d1 +regGL1H_PERFCOUNTER0_HI_BASE_IDX = 1 +regGL1H_PERFCOUNTER1_LO = 0x35d2 +regGL1H_PERFCOUNTER1_LO_BASE_IDX = 1 +regGL1H_PERFCOUNTER1_HI = 0x35d3 +regGL1H_PERFCOUNTER1_HI_BASE_IDX = 1 +regGL1H_PERFCOUNTER2_LO = 0x35d4 +regGL1H_PERFCOUNTER2_LO_BASE_IDX = 1 +regGL1H_PERFCOUNTER2_HI = 0x35d5 +regGL1H_PERFCOUNTER2_HI_BASE_IDX = 1 +regGL1H_PERFCOUNTER3_LO = 0x35d6 +regGL1H_PERFCOUNTER3_LO_BASE_IDX = 1 +regGL1H_PERFCOUNTER3_HI = 0x35d7 +regGL1H_PERFCOUNTER3_HI_BASE_IDX = 1 +regCHA_PERFCOUNTER0_LO = 0x3600 +regCHA_PERFCOUNTER0_LO_BASE_IDX = 1 +regCHA_PERFCOUNTER0_HI = 0x3601 +regCHA_PERFCOUNTER0_HI_BASE_IDX = 1 +regCHA_PERFCOUNTER1_LO = 0x3602 +regCHA_PERFCOUNTER1_LO_BASE_IDX = 1 +regCHA_PERFCOUNTER1_HI = 0x3603 +regCHA_PERFCOUNTER1_HI_BASE_IDX = 1 +regCHA_PERFCOUNTER2_LO = 0x3604 +regCHA_PERFCOUNTER2_LO_BASE_IDX = 1 +regCHA_PERFCOUNTER2_HI = 0x3605 +regCHA_PERFCOUNTER2_HI_BASE_IDX = 1 +regCHA_PERFCOUNTER3_LO = 0x3606 +regCHA_PERFCOUNTER3_LO_BASE_IDX = 1 +regCHA_PERFCOUNTER3_HI = 0x3607 +regCHA_PERFCOUNTER3_HI_BASE_IDX = 1 +regGUS_PERFCOUNTER2_LO = 0x3640 +regGUS_PERFCOUNTER2_LO_BASE_IDX = 1 +regGUS_PERFCOUNTER2_HI = 0x3641 +regGUS_PERFCOUNTER2_HI_BASE_IDX = 1 +regGUS_PERFCOUNTER_LO = 0x3642 +regGUS_PERFCOUNTER_LO_BASE_IDX = 1 +regGUS_PERFCOUNTER_HI = 0x3643 +regGUS_PERFCOUNTER_HI_BASE_IDX = 1 +regCPG_PERFCOUNTER1_SELECT = 0x3800 +regCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCPG_PERFCOUNTER0_SELECT1 = 0x3801 +regCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCPG_PERFCOUNTER0_SELECT = 0x3802 +regCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCPC_PERFCOUNTER1_SELECT = 0x3803 +regCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCPC_PERFCOUNTER0_SELECT1 = 0x3804 +regCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCPF_PERFCOUNTER1_SELECT = 0x3805 +regCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCPF_PERFCOUNTER0_SELECT1 = 0x3806 +regCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCPF_PERFCOUNTER0_SELECT = 0x3807 +regCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCP_PERFMON_CNTL = 0x3808 +regCP_PERFMON_CNTL_BASE_IDX = 1 +regCPC_PERFCOUNTER0_SELECT = 0x3809 +regCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a +regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 +regCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b +regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 +regCPF_LATENCY_STATS_SELECT = 0x380c +regCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 +regCPG_LATENCY_STATS_SELECT = 0x380d +regCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 +regCPC_LATENCY_STATS_SELECT = 0x380e +regCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 +regCPC_TC_PERF_COUNTER_WINDOW_SELECT = 0x380f +regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 +regCP_DRAW_OBJECT = 0x3810 +regCP_DRAW_OBJECT_BASE_IDX = 1 +regCP_DRAW_OBJECT_COUNTER = 0x3811 +regCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 +regCP_DRAW_WINDOW_MASK_HI = 0x3812 +regCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 +regCP_DRAW_WINDOW_HI = 0x3813 +regCP_DRAW_WINDOW_HI_BASE_IDX = 1 +regCP_DRAW_WINDOW_LO = 0x3814 +regCP_DRAW_WINDOW_LO_BASE_IDX = 1 +regCP_DRAW_WINDOW_CNTL = 0x3815 +regCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 +regGRBM_PERFCOUNTER0_SELECT = 0x3840 +regGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGRBM_PERFCOUNTER1_SELECT = 0x3841 +regGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 +regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 +regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 +regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 +regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_SE4_PERFCOUNTER_SELECT = 0x3846 +regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_SE5_PERFCOUNTER_SELECT = 0x3847 +regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_SE6_PERFCOUNTER_SELECT = 0x3848 +regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX = 1 +regGRBM_PERFCOUNTER0_SELECT_HI = 0x384d +regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 +regGRBM_PERFCOUNTER1_SELECT_HI = 0x384e +regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 +regGE1_PERFCOUNTER0_SELECT = 0x38a4 +regGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGE1_PERFCOUNTER0_SELECT1 = 0x38a5 +regGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGE1_PERFCOUNTER1_SELECT = 0x38a6 +regGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGE1_PERFCOUNTER1_SELECT1 = 0x38a7 +regGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGE1_PERFCOUNTER2_SELECT = 0x38a8 +regGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGE1_PERFCOUNTER2_SELECT1 = 0x38a9 +regGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regGE1_PERFCOUNTER3_SELECT = 0x38aa +regGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGE1_PERFCOUNTER3_SELECT1 = 0x38ab +regGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac +regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad +regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae +regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af +regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 +regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 +regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 +regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 +regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 +regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 +regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 +regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 +regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 +regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 +regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER3_SELECT = 0x38ba +regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb +regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regPA_SU_PERFCOUNTER0_SELECT = 0x3900 +regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 +regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regPA_SU_PERFCOUNTER1_SELECT = 0x3902 +regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 +regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regPA_SU_PERFCOUNTER2_SELECT = 0x3904 +regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 +regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regPA_SU_PERFCOUNTER3_SELECT = 0x3906 +regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 +regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regPA_SC_PERFCOUNTER0_SELECT = 0x3940 +regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 +regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regPA_SC_PERFCOUNTER1_SELECT = 0x3942 +regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER2_SELECT = 0x3943 +regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER3_SELECT = 0x3944 +regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER4_SELECT = 0x3945 +regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER5_SELECT = 0x3946 +regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER6_SELECT = 0x3947 +regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 +regPA_SC_PERFCOUNTER7_SELECT = 0x3948 +regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER0_SELECT = 0x3980 +regSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER1_SELECT = 0x3981 +regSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER2_SELECT = 0x3982 +regSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER3_SELECT = 0x3983 +regSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER0_SELECT1 = 0x3984 +regSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regSPI_PERFCOUNTER1_SELECT1 = 0x3985 +regSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regSPI_PERFCOUNTER2_SELECT1 = 0x3986 +regSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regSPI_PERFCOUNTER3_SELECT1 = 0x3987 +regSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regSPI_PERFCOUNTER4_SELECT = 0x3988 +regSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER5_SELECT = 0x3989 +regSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 +regSPI_PERFCOUNTER_BINS = 0x398a +regSPI_PERFCOUNTER_BINS_BASE_IDX = 1 +regPC_PERFCOUNTER0_SELECT = 0x398c +regPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regPC_PERFCOUNTER1_SELECT = 0x398d +regPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regPC_PERFCOUNTER2_SELECT = 0x398e +regPC_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regPC_PERFCOUNTER3_SELECT = 0x398f +regPC_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regPC_PERFCOUNTER0_SELECT1 = 0x3990 +regPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regPC_PERFCOUNTER1_SELECT1 = 0x3991 +regPC_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regPC_PERFCOUNTER2_SELECT1 = 0x3992 +regPC_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regPC_PERFCOUNTER3_SELECT1 = 0x3993 +regPC_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regSQ_PERFCOUNTER0_SELECT = 0x39c0 +regSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER1_SELECT = 0x39c1 +regSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER2_SELECT = 0x39c2 +regSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER3_SELECT = 0x39c3 +regSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER4_SELECT = 0x39c4 +regSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER5_SELECT = 0x39c5 +regSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER6_SELECT = 0x39c6 +regSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER7_SELECT = 0x39c7 +regSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER8_SELECT = 0x39c8 +regSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER9_SELECT = 0x39c9 +regSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER10_SELECT = 0x39ca +regSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER11_SELECT = 0x39cb +regSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER12_SELECT = 0x39cc +regSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER13_SELECT = 0x39cd +regSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER14_SELECT = 0x39ce +regSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 +regSQ_PERFCOUNTER15_SELECT = 0x39cf +regSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER0_SELECT = 0x39d0 +regSQG_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER1_SELECT = 0x39d1 +regSQG_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER2_SELECT = 0x39d2 +regSQG_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER3_SELECT = 0x39d3 +regSQG_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER4_SELECT = 0x39d4 +regSQG_PERFCOUNTER4_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER5_SELECT = 0x39d5 +regSQG_PERFCOUNTER5_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER6_SELECT = 0x39d6 +regSQG_PERFCOUNTER6_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER7_SELECT = 0x39d7 +regSQG_PERFCOUNTER7_SELECT_BASE_IDX = 1 +regSQG_PERFCOUNTER_CTRL = 0x39d8 +regSQG_PERFCOUNTER_CTRL_BASE_IDX = 1 +regSQG_PERFCOUNTER_CTRL2 = 0x39da +regSQG_PERFCOUNTER_CTRL2_BASE_IDX = 1 +regSQG_PERF_SAMPLE_FINISH = 0x39db +regSQG_PERF_SAMPLE_FINISH_BASE_IDX = 1 +regSQ_PERFCOUNTER_CTRL = 0x39e0 +regSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 +regSQ_PERFCOUNTER_CTRL2 = 0x39e2 +regSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 +regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 +regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 1 +regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 +regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 1 +regSQ_THREAD_TRACE_BUF1_BASE = 0x39ea +regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 1 +regSQ_THREAD_TRACE_BUF1_SIZE = 0x39eb +regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 1 +regSQ_THREAD_TRACE_CTRL = 0x39ec +regSQ_THREAD_TRACE_CTRL_BASE_IDX = 1 +regSQ_THREAD_TRACE_MASK = 0x39ed +regSQ_THREAD_TRACE_MASK_BASE_IDX = 1 +regSQ_THREAD_TRACE_TOKEN_MASK = 0x39ee +regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 1 +regSQ_THREAD_TRACE_WPTR = 0x39ef +regSQ_THREAD_TRACE_WPTR_BASE_IDX = 1 +regSQ_THREAD_TRACE_STATUS = 0x39f4 +regSQ_THREAD_TRACE_STATUS_BASE_IDX = 1 +regSQ_THREAD_TRACE_STATUS2 = 0x39f5 +regSQ_THREAD_TRACE_STATUS2_BASE_IDX = 1 +regSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x39f6 +regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 1 +regSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x39f7 +regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 1 +regSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x39f8 +regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 1 +regSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x39f9 +regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 1 +regSQ_THREAD_TRACE_DROPPED_CNTR = 0x39fa +regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 1 +regGCEA_PERFCOUNTER2_SELECT = 0x3a00 +regGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 +regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regGCEA_PERFCOUNTER2_MODE = 0x3a02 +regGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 +regGCEA_PERFCOUNTER0_CFG = 0x3a03 +regGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 +regGCEA_PERFCOUNTER1_CFG = 0x3a04 +regGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 +regGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 +regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 +regSX_PERFCOUNTER0_SELECT = 0x3a40 +regSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regSX_PERFCOUNTER1_SELECT = 0x3a41 +regSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regSX_PERFCOUNTER2_SELECT = 0x3a42 +regSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regSX_PERFCOUNTER3_SELECT = 0x3a43 +regSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regSX_PERFCOUNTER0_SELECT1 = 0x3a44 +regSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regSX_PERFCOUNTER1_SELECT1 = 0x3a45 +regSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGDS_PERFCOUNTER0_SELECT = 0x3a80 +regGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGDS_PERFCOUNTER1_SELECT = 0x3a81 +regGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGDS_PERFCOUNTER2_SELECT = 0x3a82 +regGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGDS_PERFCOUNTER3_SELECT = 0x3a83 +regGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGDS_PERFCOUNTER0_SELECT1 = 0x3a84 +regGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGDS_PERFCOUNTER1_SELECT1 = 0x3a85 +regGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGDS_PERFCOUNTER2_SELECT1 = 0x3a86 +regGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regGDS_PERFCOUNTER3_SELECT1 = 0x3a87 +regGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regTA_PERFCOUNTER0_SELECT = 0x3ac0 +regTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regTA_PERFCOUNTER0_SELECT1 = 0x3ac1 +regTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regTA_PERFCOUNTER1_SELECT = 0x3ac2 +regTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regTD_PERFCOUNTER0_SELECT = 0x3b00 +regTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regTD_PERFCOUNTER0_SELECT1 = 0x3b01 +regTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regTD_PERFCOUNTER1_SELECT = 0x3b02 +regTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regTCP_PERFCOUNTER0_SELECT = 0x3b40 +regTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regTCP_PERFCOUNTER0_SELECT1 = 0x3b41 +regTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regTCP_PERFCOUNTER1_SELECT = 0x3b42 +regTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regTCP_PERFCOUNTER1_SELECT1 = 0x3b43 +regTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regTCP_PERFCOUNTER2_SELECT = 0x3b44 +regTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regTCP_PERFCOUNTER3_SELECT = 0x3b45 +regTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGL2C_PERFCOUNTER0_SELECT = 0x3b80 +regGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 +regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGL2C_PERFCOUNTER1_SELECT = 0x3b82 +regGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 +regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGL2C_PERFCOUNTER2_SELECT = 0x3b84 +regGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGL2C_PERFCOUNTER3_SELECT = 0x3b85 +regGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGL2A_PERFCOUNTER0_SELECT = 0x3b90 +regGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 +regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGL2A_PERFCOUNTER1_SELECT = 0x3b92 +regGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 +regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regGL2A_PERFCOUNTER2_SELECT = 0x3b94 +regGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGL2A_PERFCOUNTER3_SELECT = 0x3b95 +regGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGL1C_PERFCOUNTER0_SELECT = 0x3ba0 +regGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 +regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGL1C_PERFCOUNTER1_SELECT = 0x3ba2 +regGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGL1C_PERFCOUNTER2_SELECT = 0x3ba3 +regGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGL1C_PERFCOUNTER3_SELECT = 0x3ba4 +regGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regCHC_PERFCOUNTER0_SELECT = 0x3bc0 +regCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 +regCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCHC_PERFCOUNTER1_SELECT = 0x3bc2 +regCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCHC_PERFCOUNTER2_SELECT = 0x3bc3 +regCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regCHC_PERFCOUNTER3_SELECT = 0x3bc4 +regCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regCHCG_PERFCOUNTER0_SELECT = 0x3bc6 +regCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 +regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCHCG_PERFCOUNTER1_SELECT = 0x3bc8 +regCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCHCG_PERFCOUNTER2_SELECT = 0x3bc9 +regCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regCHCG_PERFCOUNTER3_SELECT = 0x3bca +regCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regCB_PERFCOUNTER_FILTER = 0x3c00 +regCB_PERFCOUNTER_FILTER_BASE_IDX = 1 +regCB_PERFCOUNTER0_SELECT = 0x3c01 +regCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCB_PERFCOUNTER0_SELECT1 = 0x3c02 +regCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCB_PERFCOUNTER1_SELECT = 0x3c03 +regCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCB_PERFCOUNTER2_SELECT = 0x3c04 +regCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regCB_PERFCOUNTER3_SELECT = 0x3c05 +regCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regDB_PERFCOUNTER0_SELECT = 0x3c40 +regDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regDB_PERFCOUNTER0_SELECT1 = 0x3c41 +regDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regDB_PERFCOUNTER1_SELECT = 0x3c42 +regDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regDB_PERFCOUNTER1_SELECT1 = 0x3c43 +regDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regDB_PERFCOUNTER2_SELECT = 0x3c44 +regDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regDB_PERFCOUNTER3_SELECT = 0x3c46 +regDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regRLC_SPM_PERFMON_CNTL = 0x3c80 +regRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 +regRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 +regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 +regRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 +regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 +regRLC_SPM_PERFMON_RING_SIZE = 0x3c83 +regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 +regRLC_SPM_RING_WRPTR = 0x3c84 +regRLC_SPM_RING_WRPTR_BASE_IDX = 1 +regRLC_SPM_RING_RDPTR = 0x3c85 +regRLC_SPM_RING_RDPTR_BASE_IDX = 1 +regRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 +regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 +regRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c87 +regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 +regRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c88 +regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 +regRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c89 +regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 +regRLC_SPM_SE_MUXSEL_ADDR = 0x3c8a +regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 +regRLC_SPM_SE_MUXSEL_DATA = 0x3c8b +regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 +regRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c92 +regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 +regRLC_SPM_ACCUM_DATARAM_DATA = 0x3c93 +regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 +regRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3c94 +regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 +regRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3c95 +regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 +regRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c96 +regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 +regRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c97 +regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 +regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3c98 +regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 +regRLC_SPM_ACCUM_STATUS = 0x3c99 +regRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 +regRLC_SPM_ACCUM_CTRL = 0x3c9a +regRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 +regRLC_SPM_ACCUM_MODE = 0x3c9b +regRLC_SPM_ACCUM_MODE_BASE_IDX = 1 +regRLC_SPM_ACCUM_THRESHOLD = 0x3c9c +regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 +regRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d +regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 +regRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e +regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 +regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3c9f +regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 +regRLC_SPM_PAUSE = 0x3ca2 +regRLC_SPM_PAUSE_BASE_IDX = 1 +regRLC_SPM_STATUS = 0x3ca3 +regRLC_SPM_STATUS_BASE_IDX = 1 +regRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca4 +regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 +regRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca5 +regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 +regRLC_SPM_MODE = 0x3cad +regRLC_SPM_MODE_BASE_IDX = 1 +regRLC_SPM_RSPM_REQ_DATA_LO = 0x3cae +regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX = 1 +regRLC_SPM_RSPM_REQ_DATA_HI = 0x3caf +regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX = 1 +regRLC_SPM_RSPM_REQ_OP = 0x3cb0 +regRLC_SPM_RSPM_REQ_OP_BASE_IDX = 1 +regRLC_SPM_RSPM_RET_DATA = 0x3cb1 +regRLC_SPM_RSPM_RET_DATA_BASE_IDX = 1 +regRLC_SPM_RSPM_RET_OP = 0x3cb2 +regRLC_SPM_RSPM_RET_OP_BASE_IDX = 1 +regRLC_SPM_SE_RSPM_REQ_DATA_LO = 0x3cb3 +regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX = 1 +regRLC_SPM_SE_RSPM_REQ_DATA_HI = 0x3cb4 +regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX = 1 +regRLC_SPM_SE_RSPM_REQ_OP = 0x3cb5 +regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX = 1 +regRLC_SPM_SE_RSPM_RET_DATA = 0x3cb6 +regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX = 1 +regRLC_SPM_SE_RSPM_RET_OP = 0x3cb7 +regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX = 1 +regRLC_SPM_RSPM_CMD = 0x3cb8 +regRLC_SPM_RSPM_CMD_BASE_IDX = 1 +regRLC_SPM_RSPM_CMD_ACK = 0x3cb9 +regRLC_SPM_RSPM_CMD_ACK_BASE_IDX = 1 +regRLC_SPM_SPARE = 0x3cbf +regRLC_SPM_SPARE_BASE_IDX = 1 +regRLC_PERFMON_CNTL = 0x3cc0 +regRLC_PERFMON_CNTL_BASE_IDX = 1 +regRLC_PERFCOUNTER0_SELECT = 0x3cc1 +regRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regRLC_PERFCOUNTER1_SELECT = 0x3cc2 +regRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 +regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 +regRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 +regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 +regRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 +regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 +regRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 +regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 +regRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 +regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 +regRMI_PERFCOUNTER0_SELECT = 0x3d00 +regRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regRMI_PERFCOUNTER0_SELECT1 = 0x3d01 +regRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regRMI_PERFCOUNTER1_SELECT = 0x3d02 +regRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regRMI_PERFCOUNTER2_SELECT = 0x3d03 +regRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regRMI_PERFCOUNTER2_SELECT1 = 0x3d04 +regRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regRMI_PERFCOUNTER3_SELECT = 0x3d05 +regRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regRMI_PERF_COUNTER_CNTL = 0x3d06 +regRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 +regGCR_PERFCOUNTER0_SELECT = 0x3d60 +regGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGCR_PERFCOUNTER0_SELECT1 = 0x3d61 +regGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGCR_PERFCOUNTER1_SELECT = 0x3d62 +regGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER0_SELECT = 0x3d80 +regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 +regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regPA_PH_PERFCOUNTER1_SELECT = 0x3d82 +regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER2_SELECT = 0x3d83 +regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER3_SELECT = 0x3d84 +regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER4_SELECT = 0x3d85 +regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER5_SELECT = 0x3d86 +regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER6_SELECT = 0x3d87 +regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER7_SELECT = 0x3d88 +regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 +regPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 +regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 +regPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 +regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 +regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 +regUTCL1_PERFCOUNTER0_SELECT = 0x3da0 +regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regUTCL1_PERFCOUNTER1_SELECT = 0x3da1 +regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regUTCL1_PERFCOUNTER2_SELECT = 0x3da2 +regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regUTCL1_PERFCOUNTER3_SELECT = 0x3da3 +regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGL1A_PERFCOUNTER0_SELECT = 0x3dc0 +regGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 +regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGL1A_PERFCOUNTER1_SELECT = 0x3dc2 +regGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGL1A_PERFCOUNTER2_SELECT = 0x3dc3 +regGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGL1A_PERFCOUNTER3_SELECT = 0x3dc4 +regGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGL1H_PERFCOUNTER0_SELECT = 0x3dd0 +regGL1H_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regGL1H_PERFCOUNTER0_SELECT1 = 0x3dd1 +regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regGL1H_PERFCOUNTER1_SELECT = 0x3dd2 +regGL1H_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regGL1H_PERFCOUNTER2_SELECT = 0x3dd3 +regGL1H_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGL1H_PERFCOUNTER3_SELECT = 0x3dd4 +regGL1H_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regCHA_PERFCOUNTER0_SELECT = 0x3de0 +regCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 +regCHA_PERFCOUNTER0_SELECT1 = 0x3de1 +regCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 +regCHA_PERFCOUNTER1_SELECT = 0x3de2 +regCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 +regCHA_PERFCOUNTER2_SELECT = 0x3de3 +regCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regCHA_PERFCOUNTER3_SELECT = 0x3de4 +regCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 +regGUS_PERFCOUNTER2_SELECT = 0x3e00 +regGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 +regGUS_PERFCOUNTER2_SELECT1 = 0x3e01 +regGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 +regGUS_PERFCOUNTER2_MODE = 0x3e02 +regGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 +regGUS_PERFCOUNTER0_CFG = 0x3e03 +regGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 +regGUS_PERFCOUNTER1_CFG = 0x3e04 +regGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 +regGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 +regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 +regGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 +regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 +regGRTAVFS_RTAVFS_WR_DATA = 0x4b01 +regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 +regGRTAVFS_GENERAL_0 = 0x4b02 +regGRTAVFS_GENERAL_0_BASE_IDX = 1 +regGRTAVFS_RTAVFS_RD_DATA = 0x4b03 +regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 +regGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 +regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 +regGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 +regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 +regGRTAVFS_TARG_FREQ = 0x4b06 +regGRTAVFS_TARG_FREQ_BASE_IDX = 1 +regGRTAVFS_TARG_VOLT = 0x4b07 +regGRTAVFS_TARG_VOLT_BASE_IDX = 1 +regGRTAVFS_SOFT_RESET = 0x4b0c +regGRTAVFS_SOFT_RESET_BASE_IDX = 1 +regGRTAVFS_PSM_CNTL = 0x4b0d +regGRTAVFS_PSM_CNTL_BASE_IDX = 1 +regGRTAVFS_CLK_CNTL = 0x4b0e +regGRTAVFS_CLK_CNTL_BASE_IDX = 1 +regGRTAVFS_SE_RTAVFS_REG_ADDR = 0x4b40 +regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX = 1 +regGRTAVFS_SE_RTAVFS_WR_DATA = 0x4b41 +regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX = 1 +regGRTAVFS_SE_GENERAL_0 = 0x4b42 +regGRTAVFS_SE_GENERAL_0_BASE_IDX = 1 +regGRTAVFS_SE_RTAVFS_RD_DATA = 0x4b43 +regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX = 1 +regGRTAVFS_SE_RTAVFS_REG_CTRL = 0x4b44 +regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX = 1 +regGRTAVFS_SE_RTAVFS_REG_STATUS = 0x4b45 +regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX = 1 +regGRTAVFS_SE_TARG_FREQ = 0x4b46 +regGRTAVFS_SE_TARG_FREQ_BASE_IDX = 1 +regGRTAVFS_SE_TARG_VOLT = 0x4b47 +regGRTAVFS_SE_TARG_VOLT_BASE_IDX = 1 +regGRTAVFS_SE_SOFT_RESET = 0x4b4c +regGRTAVFS_SE_SOFT_RESET_BASE_IDX = 1 +regGRTAVFS_SE_PSM_CNTL = 0x4b4d +regGRTAVFS_SE_PSM_CNTL_BASE_IDX = 1 +regGRTAVFS_SE_CLK_CNTL = 0x4b4e +regGRTAVFS_SE_CLK_CNTL_BASE_IDX = 1 +regRTAVFS_RTAVFS_REG_ADDR = 0x4b00 +regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 +regRTAVFS_RTAVFS_WR_DATA = 0x4b01 +regRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 +regCP_HYP_PFP_UCODE_ADDR = 0x5814 +regCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 +regCP_PFP_UCODE_ADDR = 0x5814 +regCP_PFP_UCODE_ADDR_BASE_IDX = 1 +regCP_HYP_PFP_UCODE_DATA = 0x5815 +regCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 +regCP_PFP_UCODE_DATA = 0x5815 +regCP_PFP_UCODE_DATA_BASE_IDX = 1 +regCP_HYP_ME_UCODE_ADDR = 0x5816 +regCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 +regCP_ME_RAM_RADDR = 0x5816 +regCP_ME_RAM_RADDR_BASE_IDX = 1 +regCP_ME_RAM_WADDR = 0x5816 +regCP_ME_RAM_WADDR_BASE_IDX = 1 +regCP_HYP_ME_UCODE_DATA = 0x5817 +regCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 +regCP_ME_RAM_DATA = 0x5817 +regCP_ME_RAM_DATA_BASE_IDX = 1 +regCP_HYP_MEC1_UCODE_ADDR = 0x581a +regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 +regCP_MEC_ME1_UCODE_ADDR = 0x581a +regCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 +regCP_HYP_MEC1_UCODE_DATA = 0x581b +regCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 +regCP_MEC_ME1_UCODE_DATA = 0x581b +regCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 +regCP_HYP_MEC2_UCODE_ADDR = 0x581c +regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 +regCP_MEC_ME2_UCODE_ADDR = 0x581c +regCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 +regCP_HYP_MEC2_UCODE_DATA = 0x581d +regCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 +regCP_MEC_ME2_UCODE_DATA = 0x581d +regCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 +regCP_PFP_IC_BASE_LO = 0x5840 +regCP_PFP_IC_BASE_LO_BASE_IDX = 1 +regCP_PFP_IC_BASE_HI = 0x5841 +regCP_PFP_IC_BASE_HI_BASE_IDX = 1 +regCP_PFP_IC_BASE_CNTL = 0x5842 +regCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 +regCP_PFP_IC_OP_CNTL = 0x5843 +regCP_PFP_IC_OP_CNTL_BASE_IDX = 1 +regCP_ME_IC_BASE_LO = 0x5844 +regCP_ME_IC_BASE_LO_BASE_IDX = 1 +regCP_ME_IC_BASE_HI = 0x5845 +regCP_ME_IC_BASE_HI_BASE_IDX = 1 +regCP_ME_IC_BASE_CNTL = 0x5846 +regCP_ME_IC_BASE_CNTL_BASE_IDX = 1 +regCP_ME_IC_OP_CNTL = 0x5847 +regCP_ME_IC_OP_CNTL_BASE_IDX = 1 +regCP_CPC_IC_BASE_LO = 0x584c +regCP_CPC_IC_BASE_LO_BASE_IDX = 1 +regCP_CPC_IC_BASE_HI = 0x584d +regCP_CPC_IC_BASE_HI_BASE_IDX = 1 +regCP_CPC_IC_BASE_CNTL = 0x584e +regCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 +regCP_MES_IC_BASE_LO = 0x5850 +regCP_MES_IC_BASE_LO_BASE_IDX = 1 +regCP_MES_MIBASE_LO = 0x5850 +regCP_MES_MIBASE_LO_BASE_IDX = 1 +regCP_MES_IC_BASE_HI = 0x5851 +regCP_MES_IC_BASE_HI_BASE_IDX = 1 +regCP_MES_MIBASE_HI = 0x5851 +regCP_MES_MIBASE_HI_BASE_IDX = 1 +regCP_MES_IC_BASE_CNTL = 0x5852 +regCP_MES_IC_BASE_CNTL_BASE_IDX = 1 +regCP_MES_DC_BASE_LO = 0x5854 +regCP_MES_DC_BASE_LO_BASE_IDX = 1 +regCP_MES_MDBASE_LO = 0x5854 +regCP_MES_MDBASE_LO_BASE_IDX = 1 +regCP_MES_DC_BASE_HI = 0x5855 +regCP_MES_DC_BASE_HI_BASE_IDX = 1 +regCP_MES_MDBASE_HI = 0x5855 +regCP_MES_MDBASE_HI_BASE_IDX = 1 +regCP_MES_MIBOUND_LO = 0x585b +regCP_MES_MIBOUND_LO_BASE_IDX = 1 +regCP_MES_MIBOUND_HI = 0x585c +regCP_MES_MIBOUND_HI_BASE_IDX = 1 +regCP_MES_MDBOUND_LO = 0x585d +regCP_MES_MDBOUND_LO_BASE_IDX = 1 +regCP_MES_MDBOUND_HI = 0x585e +regCP_MES_MDBOUND_HI_BASE_IDX = 1 +regCP_GFX_RS64_DC_BASE0_LO = 0x5863 +regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX = 1 +regCP_GFX_RS64_DC_BASE1_LO = 0x5864 +regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX = 1 +regCP_GFX_RS64_DC_BASE0_HI = 0x5865 +regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX = 1 +regCP_GFX_RS64_DC_BASE1_HI = 0x5866 +regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX = 1 +regCP_GFX_RS64_MIBOUND_LO = 0x586c +regCP_GFX_RS64_MIBOUND_LO_BASE_IDX = 1 +regCP_GFX_RS64_MIBOUND_HI = 0x586d +regCP_GFX_RS64_MIBOUND_HI_BASE_IDX = 1 +regCP_MEC_DC_BASE_LO = 0x5870 +regCP_MEC_DC_BASE_LO_BASE_IDX = 1 +regCP_MEC_MDBASE_LO = 0x5870 +regCP_MEC_MDBASE_LO_BASE_IDX = 1 +regCP_MEC_DC_BASE_HI = 0x5871 +regCP_MEC_DC_BASE_HI_BASE_IDX = 1 +regCP_MEC_MDBASE_HI = 0x5871 +regCP_MEC_MDBASE_HI_BASE_IDX = 1 +regCP_MEC_MIBOUND_LO = 0x5872 +regCP_MEC_MIBOUND_LO_BASE_IDX = 1 +regCP_MEC_MIBOUND_HI = 0x5873 +regCP_MEC_MIBOUND_HI_BASE_IDX = 1 +regCP_MEC_MDBOUND_LO = 0x5874 +regCP_MEC_MDBOUND_LO_BASE_IDX = 1 +regCP_MEC_MDBOUND_HI = 0x5875 +regCP_MEC_MDBOUND_HI_BASE_IDX = 1 +regRLC_CNTL = 0x4c00 +regRLC_CNTL_BASE_IDX = 1 +regRLC_F32_UCODE_VERSION = 0x4c03 +regRLC_F32_UCODE_VERSION_BASE_IDX = 1 +regRLC_STAT = 0x4c04 +regRLC_STAT_BASE_IDX = 1 +regRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c +regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 +regRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d +regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 +regRLC_GPM_TIMER_INT_0 = 0x4c0e +regRLC_GPM_TIMER_INT_0_BASE_IDX = 1 +regRLC_GPM_TIMER_INT_1 = 0x4c0f +regRLC_GPM_TIMER_INT_1_BASE_IDX = 1 +regRLC_GPM_TIMER_INT_2 = 0x4c10 +regRLC_GPM_TIMER_INT_2_BASE_IDX = 1 +regRLC_GPM_TIMER_INT_3 = 0x4c11 +regRLC_GPM_TIMER_INT_3_BASE_IDX = 1 +regRLC_GPM_TIMER_INT_4 = 0x4c12 +regRLC_GPM_TIMER_INT_4_BASE_IDX = 1 +regRLC_GPM_TIMER_CTRL = 0x4c13 +regRLC_GPM_TIMER_CTRL_BASE_IDX = 1 +regRLC_GPM_TIMER_STAT = 0x4c14 +regRLC_GPM_TIMER_STAT_BASE_IDX = 1 +regRLC_GPM_LEGACY_INT_STAT = 0x4c16 +regRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 +regRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 +regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 +regRLC_INT_STAT = 0x4c18 +regRLC_INT_STAT_BASE_IDX = 1 +regRLC_MGCG_CTRL = 0x4c1a +regRLC_MGCG_CTRL_BASE_IDX = 1 +regRLC_JUMP_TABLE_RESTORE = 0x4c1e +regRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 +regRLC_PG_DELAY_2 = 0x4c1f +regRLC_PG_DELAY_2_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 +regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 +regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 +regRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 +regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 +regRLC_UCODE_CNTL = 0x4c27 +regRLC_UCODE_CNTL_BASE_IDX = 1 +regRLC_GPM_THREAD_RESET = 0x4c28 +regRLC_GPM_THREAD_RESET_BASE_IDX = 1 +regRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 +regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 +regRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a +regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 +regRLC_GPM_THREAD_INVALIDATE_CACHE = 0x4c2b +regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX = 1 +regRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 +regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 +regRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 +regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 +regRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 +regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 +regRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 +regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 +regRLC_CLK_COUNT_CTRL = 0x4c34 +regRLC_CLK_COUNT_CTRL_BASE_IDX = 1 +regRLC_CLK_COUNT_STAT = 0x4c35 +regRLC_CLK_COUNT_STAT_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_CNTL = 0x4c36 +regRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_STAT = 0x4c37 +regRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 +regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 +regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a +regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b +regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c +regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d +regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e +regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f +regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 +regRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 +regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 +regRLC_GPU_CLOCK_32 = 0x4c42 +regRLC_GPU_CLOCK_32_BASE_IDX = 1 +regRLC_PG_CNTL = 0x4c43 +regRLC_PG_CNTL_BASE_IDX = 1 +regRLC_GPM_THREAD_PRIORITY = 0x4c44 +regRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 +regRLC_GPM_THREAD_ENABLE = 0x4c45 +regRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 +regRLC_RLCG_DOORBELL_RANGE = 0x4c47 +regRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 +regRLC_CGTT_MGCG_OVERRIDE = 0x4c48 +regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 +regRLC_CGCG_CGLS_CTRL = 0x4c49 +regRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 +regRLC_CGCG_RAMP_CTRL = 0x4c4a +regRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 +regRLC_DYN_PG_STATUS = 0x4c4b +regRLC_DYN_PG_STATUS_BASE_IDX = 1 +regRLC_DYN_PG_REQUEST = 0x4c4c +regRLC_DYN_PG_REQUEST_BASE_IDX = 1 +regRLC_PG_DELAY = 0x4c4d +regRLC_PG_DELAY_BASE_IDX = 1 +regRLC_WGP_STATUS = 0x4c4e +regRLC_WGP_STATUS_BASE_IDX = 1 +regRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 +regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 +regRLC_MAX_PG_WGP = 0x4c54 +regRLC_MAX_PG_WGP_BASE_IDX = 1 +regRLC_AUTO_PG_CTRL = 0x4c55 +regRLC_AUTO_PG_CTRL_BASE_IDX = 1 +regRLC_SERDES_RD_INDEX = 0x4c59 +regRLC_SERDES_RD_INDEX_BASE_IDX = 1 +regRLC_SERDES_RD_DATA_0 = 0x4c5a +regRLC_SERDES_RD_DATA_0_BASE_IDX = 1 +regRLC_SERDES_RD_DATA_1 = 0x4c5b +regRLC_SERDES_RD_DATA_1_BASE_IDX = 1 +regRLC_SERDES_RD_DATA_2 = 0x4c5c +regRLC_SERDES_RD_DATA_2_BASE_IDX = 1 +regRLC_SERDES_RD_DATA_3 = 0x4c5d +regRLC_SERDES_RD_DATA_3_BASE_IDX = 1 +regRLC_SERDES_MASK = 0x4c5e +regRLC_SERDES_MASK_BASE_IDX = 1 +regRLC_SERDES_CTRL = 0x4c5f +regRLC_SERDES_CTRL_BASE_IDX = 1 +regRLC_SERDES_DATA = 0x4c60 +regRLC_SERDES_DATA_BASE_IDX = 1 +regRLC_SERDES_BUSY = 0x4c61 +regRLC_SERDES_BUSY_BASE_IDX = 1 +regRLC_GPM_GENERAL_0 = 0x4c63 +regRLC_GPM_GENERAL_0_BASE_IDX = 1 +regRLC_GPM_GENERAL_1 = 0x4c64 +regRLC_GPM_GENERAL_1_BASE_IDX = 1 +regRLC_GPM_GENERAL_2 = 0x4c65 +regRLC_GPM_GENERAL_2_BASE_IDX = 1 +regRLC_GPM_GENERAL_3 = 0x4c66 +regRLC_GPM_GENERAL_3_BASE_IDX = 1 +regRLC_GPM_GENERAL_4 = 0x4c67 +regRLC_GPM_GENERAL_4_BASE_IDX = 1 +regRLC_GPM_GENERAL_5 = 0x4c68 +regRLC_GPM_GENERAL_5_BASE_IDX = 1 +regRLC_GPM_GENERAL_6 = 0x4c69 +regRLC_GPM_GENERAL_6_BASE_IDX = 1 +regRLC_GPM_GENERAL_7 = 0x4c6a +regRLC_GPM_GENERAL_7_BASE_IDX = 1 +regRLC_STATIC_PG_STATUS = 0x4c6e +regRLC_STATIC_PG_STATUS_BASE_IDX = 1 +regRLC_GPM_GENERAL_16 = 0x4c76 +regRLC_GPM_GENERAL_16_BASE_IDX = 1 +regRLC_PG_DELAY_3 = 0x4c78 +regRLC_PG_DELAY_3_BASE_IDX = 1 +regRLC_GPR_REG1 = 0x4c79 +regRLC_GPR_REG1_BASE_IDX = 1 +regRLC_GPR_REG2 = 0x4c7a +regRLC_GPR_REG2_BASE_IDX = 1 +regRLC_GPM_INT_DISABLE_TH0 = 0x4c7c +regRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 +regRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d +regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 +regRLC_GPM_INT_FORCE_TH0 = 0x4c7e +regRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 +regRLC_SRM_CNTL = 0x4c80 +regRLC_SRM_CNTL_BASE_IDX = 1 +regRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 +regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b +regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c +regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d +regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e +regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f +regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 +regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 +regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 +regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 +regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 +regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 +regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 +regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 +regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 +regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 +regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 +regRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a +regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 +regRLC_SRM_STAT = 0x4c9b +regRLC_SRM_STAT_BASE_IDX = 1 +regRLC_GPM_GENERAL_8 = 0x4cad +regRLC_GPM_GENERAL_8_BASE_IDX = 1 +regRLC_GPM_GENERAL_9 = 0x4cae +regRLC_GPM_GENERAL_9_BASE_IDX = 1 +regRLC_GPM_GENERAL_10 = 0x4caf +regRLC_GPM_GENERAL_10_BASE_IDX = 1 +regRLC_GPM_GENERAL_11 = 0x4cb0 +regRLC_GPM_GENERAL_11_BASE_IDX = 1 +regRLC_GPM_GENERAL_12 = 0x4cb1 +regRLC_GPM_GENERAL_12_BASE_IDX = 1 +regRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 +regRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 +regRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 +regRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 +regRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 +regRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 +regRLC_SPM_UTCL1_CNTL = 0x4cb5 +regRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 +regRLC_UTCL1_STATUS_2 = 0x4cb6 +regRLC_UTCL1_STATUS_2_BASE_IDX = 1 +regRLC_SPM_UTCL1_ERROR_1 = 0x4cbc +regRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 +regRLC_SPM_UTCL1_ERROR_2 = 0x4cbd +regRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 +regRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe +regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 +regRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 +regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 +regRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 +regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 +regRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 +regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 +regRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 +regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 +regRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 +regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 +regRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 +regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 +regRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 +regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 +regRLC_SEMAPHORE_0 = 0x4cc7 +regRLC_SEMAPHORE_0_BASE_IDX = 1 +regRLC_SEMAPHORE_1 = 0x4cc8 +regRLC_SEMAPHORE_1_BASE_IDX = 1 +regRLC_SEMAPHORE_2 = 0x4cc9 +regRLC_SEMAPHORE_2_BASE_IDX = 1 +regRLC_SEMAPHORE_3 = 0x4cca +regRLC_SEMAPHORE_3_BASE_IDX = 1 +regRLC_PACE_INT_STAT = 0x4ccc +regRLC_PACE_INT_STAT_BASE_IDX = 1 +regRLC_UTCL1_STATUS = 0x4cd4 +regRLC_UTCL1_STATUS_BASE_IDX = 1 +regRLC_R2I_CNTL_0 = 0x4cd5 +regRLC_R2I_CNTL_0_BASE_IDX = 1 +regRLC_R2I_CNTL_1 = 0x4cd6 +regRLC_R2I_CNTL_1_BASE_IDX = 1 +regRLC_R2I_CNTL_2 = 0x4cd7 +regRLC_R2I_CNTL_2_BASE_IDX = 1 +regRLC_R2I_CNTL_3 = 0x4cd8 +regRLC_R2I_CNTL_3_BASE_IDX = 1 +regRLC_GPM_INT_STAT_TH0 = 0x4cdc +regRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 +regRLC_GPM_GENERAL_13 = 0x4cdd +regRLC_GPM_GENERAL_13_BASE_IDX = 1 +regRLC_GPM_GENERAL_14 = 0x4cde +regRLC_GPM_GENERAL_14_BASE_IDX = 1 +regRLC_GPM_GENERAL_15 = 0x4cdf +regRLC_GPM_GENERAL_15_BASE_IDX = 1 +regRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea +regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb +regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec +regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 +regRLC_PACE_INT_DISABLE = 0x4ced +regRLC_PACE_INT_DISABLE_BASE_IDX = 1 +regRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef +regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_RANGE = 0x4cf0 +regRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_CNTL = 0x4cf1 +regRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_STAT = 0x4cf2 +regRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 +regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 +regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 +regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 +regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 +regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 +regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 +regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 +regRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa +regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4cfb +regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4cfc +regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 +regRLC_RLCV_SPARE_INT = 0x4d00 +regRLC_RLCV_SPARE_INT_BASE_IDX = 1 +regRLC_PACE_TIMER_INT_0 = 0x4d04 +regRLC_PACE_TIMER_INT_0_BASE_IDX = 1 +regRLC_PACE_TIMER_INT_1 = 0x4d05 +regRLC_PACE_TIMER_INT_1_BASE_IDX = 1 +regRLC_PACE_TIMER_CTRL = 0x4d06 +regRLC_PACE_TIMER_CTRL_BASE_IDX = 1 +regRLC_SMU_CLK_REQ = 0x4d08 +regRLC_SMU_CLK_REQ_BASE_IDX = 1 +regRLC_CP_STAT_INVAL_STAT = 0x4d09 +regRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 +regRLC_CP_STAT_INVAL_CTRL = 0x4d0a +regRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 +regRLC_SPARE = 0x4d0b +regRLC_SPARE_BASE_IDX = 1 +regRLC_SPP_CTRL = 0x4d0c +regRLC_SPP_CTRL_BASE_IDX = 1 +regRLC_SPP_SHADER_PROFILE_EN = 0x4d0d +regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 +regRLC_SPP_SSF_CAPTURE_EN = 0x4d0e +regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 +regRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f +regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 +regRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 +regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 +regRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 +regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 +regRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 +regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 +regRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 +regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 +regRLC_SPP_PROF_INFO_1 = 0x4d18 +regRLC_SPP_PROF_INFO_1_BASE_IDX = 1 +regRLC_SPP_PROF_INFO_2 = 0x4d19 +regRLC_SPP_PROF_INFO_2_BASE_IDX = 1 +regRLC_SPP_GLOBAL_SH_ID = 0x4d1a +regRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 +regRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b +regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 +regRLC_SPP_STATUS = 0x4d1c +regRLC_SPP_STATUS_BASE_IDX = 1 +regRLC_SPP_PVT_STAT_0 = 0x4d1d +regRLC_SPP_PVT_STAT_0_BASE_IDX = 1 +regRLC_SPP_PVT_STAT_1 = 0x4d1e +regRLC_SPP_PVT_STAT_1_BASE_IDX = 1 +regRLC_SPP_PVT_STAT_2 = 0x4d1f +regRLC_SPP_PVT_STAT_2_BASE_IDX = 1 +regRLC_SPP_PVT_STAT_3 = 0x4d20 +regRLC_SPP_PVT_STAT_3_BASE_IDX = 1 +regRLC_SPP_PVT_LEVEL_MAX = 0x4d21 +regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 +regRLC_SPP_STALL_STATE_UPDATE = 0x4d22 +regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 +regRLC_SPP_PBB_INFO = 0x4d23 +regRLC_SPP_PBB_INFO_BASE_IDX = 1 +regRLC_SPP_RESET = 0x4d24 +regRLC_SPP_RESET_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_RANGE = 0x4d26 +regRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_CNTL = 0x4d27 +regRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_STAT = 0x4d28 +regRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 +regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a +regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b +regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c +regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d +regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e +regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f +regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 +regRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 +regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 +regRLC_CAC_MASK_CNTL = 0x4d45 +regRLC_CAC_MASK_CNTL_BASE_IDX = 1 +regRLC_POWER_RESIDENCY_CNTR_CTRL = 0x4d48 +regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 +regRLC_CLK_RESIDENCY_CNTR_CTRL = 0x4d49 +regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 +regRLC_DS_RESIDENCY_CNTR_CTRL = 0x4d4a +regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 +regRLC_ULV_RESIDENCY_CNTR_CTRL = 0x4d4b +regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 +regRLC_PCC_RESIDENCY_CNTR_CTRL = 0x4d4c +regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 +regRLC_GENERAL_RESIDENCY_CNTR_CTRL = 0x4d4d +regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX = 1 +regRLC_POWER_RESIDENCY_EVENT_CNTR = 0x4d50 +regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 +regRLC_CLK_RESIDENCY_EVENT_CNTR = 0x4d51 +regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 +regRLC_DS_RESIDENCY_EVENT_CNTR = 0x4d52 +regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 +regRLC_ULV_RESIDENCY_EVENT_CNTR = 0x4d53 +regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 +regRLC_PCC_RESIDENCY_EVENT_CNTR = 0x4d54 +regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 +regRLC_GENERAL_RESIDENCY_EVENT_CNTR = 0x4d55 +regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX = 1 +regRLC_POWER_RESIDENCY_REF_CNTR = 0x4d58 +regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX = 1 +regRLC_CLK_RESIDENCY_REF_CNTR = 0x4d59 +regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX = 1 +regRLC_DS_RESIDENCY_REF_CNTR = 0x4d5a +regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX = 1 +regRLC_ULV_RESIDENCY_REF_CNTR = 0x4d5b +regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX = 1 +regRLC_PCC_RESIDENCY_REF_CNTR = 0x4d5c +regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX = 1 +regRLC_GENERAL_RESIDENCY_REF_CNTR = 0x4d5d +regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX = 1 +regRLC_GFX_IH_CLIENT_CTRL = 0x4d5e +regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX = 1 +regRLC_GFX_IH_ARBITER_STAT = 0x4d5f +regRLC_GFX_IH_ARBITER_STAT_BASE_IDX = 1 +regRLC_GFX_IH_CLIENT_SE_STAT_L = 0x4d60 +regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX = 1 +regRLC_GFX_IH_CLIENT_SE_STAT_H = 0x4d61 +regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX = 1 +regRLC_GFX_IH_CLIENT_SDMA_STAT = 0x4d62 +regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX = 1 +regRLC_GFX_IH_CLIENT_OTHER_STAT = 0x4d63 +regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX = 1 +regRLC_SPM_GLOBAL_DELAY_IND_ADDR = 0x4d64 +regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX = 1 +regRLC_SPM_GLOBAL_DELAY_IND_DATA = 0x4d65 +regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX = 1 +regRLC_SPM_SE_DELAY_IND_ADDR = 0x4d66 +regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX = 1 +regRLC_SPM_SE_DELAY_IND_DATA = 0x4d67 +regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX = 1 +regRLC_LX6_CNTL = 0x4d80 +regRLC_LX6_CNTL_BASE_IDX = 1 +regRLC_XT_CORE_STATUS = 0x4dd4 +regRLC_XT_CORE_STATUS_BASE_IDX = 1 +regRLC_XT_CORE_INTERRUPT = 0x4dd5 +regRLC_XT_CORE_INTERRUPT_BASE_IDX = 1 +regRLC_XT_CORE_FAULT_INFO = 0x4dd6 +regRLC_XT_CORE_FAULT_INFO_BASE_IDX = 1 +regRLC_XT_CORE_ALT_RESET_VEC = 0x4dd7 +regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX = 1 +regRLC_XT_CORE_RESERVED = 0x4dd8 +regRLC_XT_CORE_RESERVED_BASE_IDX = 1 +regRLC_XT_INT_VEC_FORCE = 0x4dd9 +regRLC_XT_INT_VEC_FORCE_BASE_IDX = 1 +regRLC_XT_INT_VEC_CLEAR = 0x4dda +regRLC_XT_INT_VEC_CLEAR_BASE_IDX = 1 +regRLC_XT_INT_VEC_MUX_SEL = 0x4ddb +regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX = 1 +regRLC_XT_INT_VEC_MUX_INT_SEL = 0x4ddc +regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 +regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 +regRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 +regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 +regRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 +regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 +regRLC_SPP_CAM_ADDR = 0x4de8 +regRLC_SPP_CAM_ADDR_BASE_IDX = 1 +regRLC_SPP_CAM_DATA = 0x4de9 +regRLC_SPP_CAM_DATA_BASE_IDX = 1 +regRLC_SPP_CAM_EXT_ADDR = 0x4dea +regRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 +regRLC_SPP_CAM_EXT_DATA = 0x4deb +regRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 +regRLC_XT_DOORBELL_RANGE = 0x4df5 +regRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 +regRLC_XT_DOORBELL_CNTL = 0x4df6 +regRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 +regRLC_XT_DOORBELL_STAT = 0x4df7 +regRLC_XT_DOORBELL_STAT_BASE_IDX = 1 +regRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 +regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 +regRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 +regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 +regRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa +regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 +regRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb +regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 +regRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc +regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 +regRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd +regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 +regRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe +regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 +regRLC_XT_DOORBELL_3_DATA_HI = 0x4dff +regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 +regRLC_MEM_SLP_CNTL = 0x4e00 +regRLC_MEM_SLP_CNTL_BASE_IDX = 1 +regSMU_RLC_RESPONSE = 0x4e01 +regSMU_RLC_RESPONSE_BASE_IDX = 1 +regRLC_RLCV_SAFE_MODE = 0x4e02 +regRLC_RLCV_SAFE_MODE_BASE_IDX = 1 +regRLC_SMU_SAFE_MODE = 0x4e03 +regRLC_SMU_SAFE_MODE_BASE_IDX = 1 +regRLC_RLCV_COMMAND = 0x4e04 +regRLC_RLCV_COMMAND_BASE_IDX = 1 +regRLC_SMU_MESSAGE = 0x4e05 +regRLC_SMU_MESSAGE_BASE_IDX = 1 +regRLC_SMU_MESSAGE_1 = 0x4e06 +regRLC_SMU_MESSAGE_1_BASE_IDX = 1 +regRLC_SMU_MESSAGE_2 = 0x4e07 +regRLC_SMU_MESSAGE_2_BASE_IDX = 1 +regRLC_SRM_GPM_COMMAND = 0x4e08 +regRLC_SRM_GPM_COMMAND_BASE_IDX = 1 +regRLC_SRM_GPM_ABORT = 0x4e09 +regRLC_SRM_GPM_ABORT_BASE_IDX = 1 +regRLC_SMU_COMMAND = 0x4e0a +regRLC_SMU_COMMAND_BASE_IDX = 1 +regRLC_SMU_ARGUMENT_1 = 0x4e0b +regRLC_SMU_ARGUMENT_1_BASE_IDX = 1 +regRLC_SMU_ARGUMENT_2 = 0x4e0c +regRLC_SMU_ARGUMENT_2_BASE_IDX = 1 +regRLC_SMU_ARGUMENT_3 = 0x4e0d +regRLC_SMU_ARGUMENT_3_BASE_IDX = 1 +regRLC_SMU_ARGUMENT_4 = 0x4e0e +regRLC_SMU_ARGUMENT_4_BASE_IDX = 1 +regRLC_SMU_ARGUMENT_5 = 0x4e0f +regRLC_SMU_ARGUMENT_5_BASE_IDX = 1 +regRLC_IMU_BOOTLOAD_ADDR_HI = 0x4e10 +regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX = 1 +regRLC_IMU_BOOTLOAD_ADDR_LO = 0x4e11 +regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX = 1 +regRLC_IMU_BOOTLOAD_SIZE = 0x4e12 +regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX = 1 +regRLC_IMU_MISC = 0x4e16 +regRLC_IMU_MISC_BASE_IDX = 1 +regRLC_IMU_RESET_VECTOR = 0x4e17 +regRLC_IMU_RESET_VECTOR_BASE_IDX = 1 +regRLC_RLCS_DEC_START = 0x4e60 +regRLC_RLCS_DEC_START_BASE_IDX = 1 +regRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 +regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 +regRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 +regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 +regRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 +regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 +regRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 +regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 +regRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 +regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 +regRLC_RLCS_CGCG_REQUEST = 0x4e66 +regRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 +regRLC_RLCS_CGCG_STATUS = 0x4e67 +regRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 +regRLC_RLCS_SOC_DS_CNTL = 0x4e68 +regRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 +regRLC_RLCS_GFX_DS_CNTL = 0x4e69 +regRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 +regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL = 0x4e6a +regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX = 1 +regRLC_GPM_STAT = 0x4e6b +regRLC_GPM_STAT_BASE_IDX = 1 +regRLC_RLCS_GPM_STAT = 0x4e6b +regRLC_RLCS_GPM_STAT_BASE_IDX = 1 +regRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6c +regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 +regRLC_RLCS_DIDT_FORCE_STALL = 0x4e6d +regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 +regRLC_RLCS_IOV_CMD_STATUS = 0x4e6e +regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 +regRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e6f +regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 +regRLC_RLCS_IOV_SCH_BLOCK = 0x4e70 +regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 +regRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e71 +regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 +regRLC_RLCS_GPM_STAT_2 = 0x4e72 +regRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 +regRLC_RLCS_GRBM_SOFT_RESET = 0x4e73 +regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 +regRLC_RLCS_PG_CHANGE_STATUS = 0x4e74 +regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 +regRLC_RLCS_PG_CHANGE_READ = 0x4e75 +regRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 +regRLC_RLCS_IH_SEMAPHORE = 0x4e76 +regRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 +regRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e77 +regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 +regRLC_RLCS_WGP_STATUS = 0x4e78 +regRLC_RLCS_WGP_STATUS_BASE_IDX = 1 +regRLC_RLCS_WGP_READ = 0x4e79 +regRLC_RLCS_WGP_READ_BASE_IDX = 1 +regRLC_RLCS_CP_INT_CTRL_1 = 0x4e7a +regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 +regRLC_RLCS_CP_INT_CTRL_2 = 0x4e7b +regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 +regRLC_RLCS_CP_INT_INFO_1 = 0x4e7c +regRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 +regRLC_RLCS_CP_INT_INFO_2 = 0x4e7d +regRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 +regRLC_RLCS_SPM_INT_CTRL = 0x4e7e +regRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 +regRLC_RLCS_SPM_INT_INFO_1 = 0x4e7f +regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 +regRLC_RLCS_SPM_INT_INFO_2 = 0x4e80 +regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 +regRLC_RLCS_DSM_TRIG = 0x4e81 +regRLC_RLCS_DSM_TRIG_BASE_IDX = 1 +regRLC_RLCS_BOOTLOAD_STATUS = 0x4e82 +regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 +regRLC_RLCS_POWER_BRAKE_CNTL = 0x4e83 +regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 +regRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4e84 +regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 +regRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4e85 +regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 +regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4e86 +regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 +regRLC_RLCS_CMP_IDLE_CNTL = 0x4e87 +regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 +regRLC_RLCS_GENERAL_0 = 0x4e88 +regRLC_RLCS_GENERAL_0_BASE_IDX = 1 +regRLC_RLCS_GENERAL_1 = 0x4e89 +regRLC_RLCS_GENERAL_1_BASE_IDX = 1 +regRLC_RLCS_GENERAL_2 = 0x4e8a +regRLC_RLCS_GENERAL_2_BASE_IDX = 1 +regRLC_RLCS_GENERAL_3 = 0x4e8b +regRLC_RLCS_GENERAL_3_BASE_IDX = 1 +regRLC_RLCS_GENERAL_4 = 0x4e8c +regRLC_RLCS_GENERAL_4_BASE_IDX = 1 +regRLC_RLCS_GENERAL_5 = 0x4e8d +regRLC_RLCS_GENERAL_5_BASE_IDX = 1 +regRLC_RLCS_GENERAL_6 = 0x4e8e +regRLC_RLCS_GENERAL_6_BASE_IDX = 1 +regRLC_RLCS_GENERAL_7 = 0x4e8f +regRLC_RLCS_GENERAL_7_BASE_IDX = 1 +regRLC_RLCS_GENERAL_8 = 0x4e90 +regRLC_RLCS_GENERAL_8_BASE_IDX = 1 +regRLC_RLCS_GENERAL_9 = 0x4e91 +regRLC_RLCS_GENERAL_9_BASE_IDX = 1 +regRLC_RLCS_GENERAL_10 = 0x4e92 +regRLC_RLCS_GENERAL_10_BASE_IDX = 1 +regRLC_RLCS_GENERAL_11 = 0x4e93 +regRLC_RLCS_GENERAL_11_BASE_IDX = 1 +regRLC_RLCS_GENERAL_12 = 0x4e94 +regRLC_RLCS_GENERAL_12_BASE_IDX = 1 +regRLC_RLCS_GENERAL_13 = 0x4e95 +regRLC_RLCS_GENERAL_13_BASE_IDX = 1 +regRLC_RLCS_GENERAL_14 = 0x4e96 +regRLC_RLCS_GENERAL_14_BASE_IDX = 1 +regRLC_RLCS_GENERAL_15 = 0x4e97 +regRLC_RLCS_GENERAL_15_BASE_IDX = 1 +regRLC_RLCS_GENERAL_16 = 0x4e98 +regRLC_RLCS_GENERAL_16_BASE_IDX = 1 +regRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 +regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 +regRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 +regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 +regRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 +regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 +regRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 +regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 +regRLC_RLCS_SPM_SQTT_MODE = 0x4ec9 +regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 +regRLC_RLCS_CP_DMA_SRCID_OVER = 0x4eca +regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 +regRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4ecb +regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 +regRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4ecc +regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 +regRLC_RLCS_IMU_VIDCHG_CNTL = 0x4ecd +regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX = 1 +regRLC_RLCS_EDC_INT_CNTL = 0x4ece +regRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 +regRLC_RLCS_KMD_LOG_CNTL1 = 0x4ecf +regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 +regRLC_RLCS_KMD_LOG_CNTL2 = 0x4ed0 +regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 +regRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ed1 +regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 +regRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ed2 +regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 +regRLC_RLCS_SRM_SRCID_CNTL = 0x4ed3 +regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 +regRLC_RLCS_GCR_DATA_0 = 0x4ed4 +regRLC_RLCS_GCR_DATA_0_BASE_IDX = 1 +regRLC_RLCS_GCR_DATA_1 = 0x4ed5 +regRLC_RLCS_GCR_DATA_1_BASE_IDX = 1 +regRLC_RLCS_GCR_DATA_2 = 0x4ed6 +regRLC_RLCS_GCR_DATA_2_BASE_IDX = 1 +regRLC_RLCS_GCR_DATA_3 = 0x4ed7 +regRLC_RLCS_GCR_DATA_3_BASE_IDX = 1 +regRLC_RLCS_GCR_STATUS = 0x4ed8 +regRLC_RLCS_GCR_STATUS_BASE_IDX = 1 +regRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4ed9 +regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 +regRLC_RLCS_UTCL2_CNTL = 0x4eda +regRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_DATA0 = 0x4edb +regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_DATA1 = 0x4edc +regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_DATA2 = 0x4edd +regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_DATA3 = 0x4ede +regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_DATA4 = 0x4edf +regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_CONTROL = 0x4ee0 +regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MSG_CNTL = 0x4ee1 +regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX = 1 +regRLC_RLCS_RLC_IMU_MSG_DATA0 = 0x4ee2 +regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX = 1 +regRLC_RLCS_RLC_IMU_MSG_CONTROL = 0x4ee3 +regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX = 1 +regRLC_RLCS_RLC_IMU_MSG_CNTL = 0x4ee4 +regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 = 0x4ee5 +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 = 0x4ee6 +regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_MUTEX_CNTL = 0x4ee7 +regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX = 1 +regRLC_RLCS_IMU_RLC_STATUS = 0x4ee8 +regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX = 1 +regRLC_RLCS_RLC_IMU_STATUS = 0x4ee9 +regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_DATA_1 = 0x4eea +regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_ADDR_1_LSB = 0x4eeb +regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_ADDR_1_MSB = 0x4eec +regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_DATA_0 = 0x4eed +regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_ADDR_0_LSB = 0x4eee +regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_ADDR_0_MSB = 0x4eef +regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX = 1 +regRLC_RLCS_IMU_RAM_CNTL = 0x4ef0 +regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX = 1 +regRLC_RLCS_IMU_GFX_DOORBELL_FENCE = 0x4ef1 +regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX = 1 +regRLC_RLCS_SDMA_INT_CNTL_1 = 0x4ef3 +regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX = 1 +regRLC_RLCS_SDMA_INT_CNTL_2 = 0x4ef4 +regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX = 1 +regRLC_RLCS_SDMA_INT_STAT = 0x4ef5 +regRLC_RLCS_SDMA_INT_STAT_BASE_IDX = 1 +regRLC_RLCS_SDMA_INT_INFO = 0x4ef6 +regRLC_RLCS_SDMA_INT_INFO_BASE_IDX = 1 +regRLC_RLCS_PMM_CGCG_CNTL = 0x4ef7 +regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX = 1 +regRLC_RLCS_GFX_MEM_POWER_CTRL_LO = 0x4ef8 +regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX = 1 +regRLC_RLCS_GFX_RM_CNTL = 0x4efa +regRLC_RLCS_GFX_RM_CNTL_BASE_IDX = 1 +regRLC_RLCS_DEC_END = 0x4fff +regRLC_RLCS_DEC_END_BASE_IDX = 1 +regRLC_SAFE_MODE = 0x0980 +regRLC_SAFE_MODE_BASE_IDX = 1 +regRLC_SPM_SAMPLE_CNT = 0x0981 +regRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 +regRLC_SPM_MC_CNTL = 0x0982 +regRLC_SPM_MC_CNTL_BASE_IDX = 1 +regRLC_SPM_INT_CNTL = 0x0983 +regRLC_SPM_INT_CNTL_BASE_IDX = 1 +regRLC_SPM_INT_STATUS = 0x0984 +regRLC_SPM_INT_STATUS_BASE_IDX = 1 +regRLC_SPM_INT_INFO_1 = 0x0985 +regRLC_SPM_INT_INFO_1_BASE_IDX = 1 +regRLC_SPM_INT_INFO_2 = 0x0986 +regRLC_SPM_INT_INFO_2_BASE_IDX = 1 +regRLC_CSIB_ADDR_LO = 0x0987 +regRLC_CSIB_ADDR_LO_BASE_IDX = 1 +regRLC_CSIB_ADDR_HI = 0x0988 +regRLC_CSIB_ADDR_HI_BASE_IDX = 1 +regRLC_CSIB_LENGTH = 0x0989 +regRLC_CSIB_LENGTH_BASE_IDX = 1 +regRLC_CP_SCHEDULERS = 0x098a +regRLC_CP_SCHEDULERS_BASE_IDX = 1 +regRLC_CP_EOF_INT = 0x098b +regRLC_CP_EOF_INT_BASE_IDX = 1 +regRLC_CP_EOF_INT_CNT = 0x098c +regRLC_CP_EOF_INT_CNT_BASE_IDX = 1 +regRLC_SPARE_INT_0 = 0x098d +regRLC_SPARE_INT_0_BASE_IDX = 1 +regRLC_SPARE_INT_1 = 0x098e +regRLC_SPARE_INT_1_BASE_IDX = 1 +regRLC_SPARE_INT_2 = 0x098f +regRLC_SPARE_INT_2_BASE_IDX = 1 +regRLC_PACE_SPARE_INT = 0x0990 +regRLC_PACE_SPARE_INT_BASE_IDX = 1 +regRLC_PACE_SPARE_INT_1 = 0x0991 +regRLC_PACE_SPARE_INT_1_BASE_IDX = 1 +regRLC_RLCV_SPARE_INT_1 = 0x0992 +regRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 +regCGTS_TCC_DISABLE = 0x5006 +regCGTS_TCC_DISABLE_BASE_IDX = 1 +regCGTT_GS_NGG_CLK_CTRL = 0x5087 +regCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 +regCGTT_PA_CLK_CTRL = 0x5088 +regCGTT_PA_CLK_CTRL_BASE_IDX = 1 +regCGTT_SC_CLK_CTRL0 = 0x5089 +regCGTT_SC_CLK_CTRL0_BASE_IDX = 1 +regCGTT_SC_CLK_CTRL1 = 0x508a +regCGTT_SC_CLK_CTRL1_BASE_IDX = 1 +regCGTT_SC_CLK_CTRL2 = 0x508b +regCGTT_SC_CLK_CTRL2_BASE_IDX = 1 +regCGTT_SQG_CLK_CTRL = 0x508d +regCGTT_SQG_CLK_CTRL_BASE_IDX = 1 +regSQ_ALU_CLK_CTRL = 0x508e +regSQ_ALU_CLK_CTRL_BASE_IDX = 1 +regSQ_TEX_CLK_CTRL = 0x508f +regSQ_TEX_CLK_CTRL_BASE_IDX = 1 +regSQ_LDS_CLK_CTRL = 0x5090 +regSQ_LDS_CLK_CTRL_BASE_IDX = 1 +regICG_SP_CLK_CTRL = 0x5093 +regICG_SP_CLK_CTRL_BASE_IDX = 1 +regTA_CGTT_CTRL = 0x509d +regTA_CGTT_CTRL_BASE_IDX = 1 +regDB_CGTT_CLK_CTRL_0 = 0x50a4 +regDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 +regCB_CGTT_SCLK_CTRL = 0x50a8 +regCB_CGTT_SCLK_CTRL_BASE_IDX = 1 +regCGTT_CP_CLK_CTRL = 0x50b0 +regCGTT_CP_CLK_CTRL_BASE_IDX = 1 +regCGTT_CPF_CLK_CTRL = 0x50b1 +regCGTT_CPF_CLK_CTRL_BASE_IDX = 1 +regCGTT_CPC_CLK_CTRL = 0x50b2 +regCGTT_CPC_CLK_CTRL_BASE_IDX = 1 +regCGTT_RLC_CLK_CTRL = 0x50b5 +regCGTT_RLC_CLK_CTRL_BASE_IDX = 1 +regCGTT_SC_CLK_CTRL3 = 0x50bc +regCGTT_SC_CLK_CTRL3_BASE_IDX = 1 +regCGTT_SC_CLK_CTRL4 = 0x50bd +regCGTT_SC_CLK_CTRL4_BASE_IDX = 1 +regGCEA_ICG_CTRL = 0x50c4 +regGCEA_ICG_CTRL_BASE_IDX = 1 +regGL1I_GL1R_MGCG_OVERRIDE = 0x50e4 +regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX = 1 +regGL1H_ICG_CTRL = 0x50e8 +regGL1H_ICG_CTRL_BASE_IDX = 1 +regCHI_CHR_MGCG_OVERRIDE = 0x50e9 +regCHI_CHR_MGCG_OVERRIDE_BASE_IDX = 1 +regICG_GL1C_CLK_CTRL = 0x50ec +regICG_GL1C_CLK_CTRL_BASE_IDX = 1 +regICG_GL1A_CTRL = 0x50f0 +regICG_GL1A_CTRL_BASE_IDX = 1 +regICG_CHA_CTRL = 0x50f1 +regICG_CHA_CTRL_BASE_IDX = 1 +regGUS_ICG_CTRL = 0x50f4 +regGUS_ICG_CTRL_BASE_IDX = 1 +regCGTT_PH_CLK_CTRL0 = 0x50f8 +regCGTT_PH_CLK_CTRL0_BASE_IDX = 1 +regCGTT_PH_CLK_CTRL1 = 0x50f9 +regCGTT_PH_CLK_CTRL1_BASE_IDX = 1 +regCGTT_PH_CLK_CTRL2 = 0x50fa +regCGTT_PH_CLK_CTRL2_BASE_IDX = 1 +regCGTT_PH_CLK_CTRL3 = 0x50fb +regCGTT_PH_CLK_CTRL3_BASE_IDX = 1 +regGFX_ICG_GL2C_CTRL = 0x50fc +regGFX_ICG_GL2C_CTRL_BASE_IDX = 1 +regGFX_ICG_GL2C_CTRL1 = 0x50fd +regGFX_ICG_GL2C_CTRL1_BASE_IDX = 1 +regICG_LDS_CLK_CTRL = 0x5114 +regICG_LDS_CLK_CTRL_BASE_IDX = 1 +regICG_CHC_CLK_CTRL = 0x5140 +regICG_CHC_CLK_CTRL_BASE_IDX = 1 +regICG_CHCG_CLK_CTRL = 0x5144 +regICG_CHCG_CLK_CTRL_BASE_IDX = 1 +regGFX_PIPE_PRIORITY = 0x587f +regGFX_PIPE_PRIORITY_BASE_IDX = 1 +regGRBM_GFX_INDEX_SR_SELECT = 0x5a00 +regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 +regGRBM_GFX_INDEX_SR_DATA = 0x5a01 +regGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 +regGRBM_GFX_CNTL_SR_SELECT = 0x5a02 +regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 +regGRBM_GFX_CNTL_SR_DATA = 0x5a03 +regGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 +regGC_IH_COOKIE_0_PTR = 0x5a07 +regGC_IH_COOKIE_0_PTR_BASE_IDX = 1 +regGRBM_SE_REMAP_CNTL = 0x5a08 +regGRBM_SE_REMAP_CNTL_BASE_IDX = 1 +regRLC_GPU_IOV_VF_ENABLE = 0x5b00 +regRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 +regRLC_GPU_IOV_CFG_REG6 = 0x5b06 +regRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 +regRLC_SDMA0_STATUS = 0x5b18 +regRLC_SDMA0_STATUS_BASE_IDX = 1 +regRLC_SDMA1_STATUS = 0x5b19 +regRLC_SDMA1_STATUS_BASE_IDX = 1 +regRLC_SDMA2_STATUS = 0x5b1a +regRLC_SDMA2_STATUS_BASE_IDX = 1 +regRLC_SDMA3_STATUS = 0x5b1b +regRLC_SDMA3_STATUS_BASE_IDX = 1 +regRLC_SDMA0_BUSY_STATUS = 0x5b1c +regRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 +regRLC_SDMA1_BUSY_STATUS = 0x5b1d +regRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 +regRLC_SDMA2_BUSY_STATUS = 0x5b1e +regRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 +regRLC_SDMA3_BUSY_STATUS = 0x5b1f +regRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_CFG_REG8 = 0x5b20 +regRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 +regRLC_RLCV_TIMER_INT_0 = 0x5b25 +regRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 +regRLC_RLCV_TIMER_INT_1 = 0x5b26 +regRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 +regRLC_RLCV_TIMER_CTRL = 0x5b27 +regRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 +regRLC_RLCV_TIMER_STAT = 0x5b28 +regRLC_RLCV_TIMER_STAT_BASE_IDX = 1 +regRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a +regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b +regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 +regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c +regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 +regRLC_GPU_IOV_VF_MASK = 0x5b2d +regRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 +regRLC_HYP_SEMAPHORE_0 = 0x5b2e +regRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 +regRLC_HYP_SEMAPHORE_1 = 0x5b2f +regRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 +regRLC_BUSY_CLK_CNTL = 0x5b30 +regRLC_BUSY_CLK_CNTL_BASE_IDX = 1 +regRLC_CLK_CNTL = 0x5b31 +regRLC_CLK_CNTL_BASE_IDX = 1 +regRLC_PACE_TIMER_STAT = 0x5b33 +regRLC_PACE_TIMER_STAT_BASE_IDX = 1 +regRLC_GPU_IOV_SCH_BLOCK = 0x5b34 +regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 +regRLC_GPU_IOV_CFG_REG1 = 0x5b35 +regRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 +regRLC_GPU_IOV_CFG_REG2 = 0x5b36 +regRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 +regRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 +regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SCH_0 = 0x5b38 +regRLC_GPU_IOV_SCH_0_BASE_IDX = 1 +regRLC_GPU_IOV_SCH_3 = 0x5b3a +regRLC_GPU_IOV_SCH_3_BASE_IDX = 1 +regRLC_GPU_IOV_SCH_1 = 0x5b3b +regRLC_GPU_IOV_SCH_1_BASE_IDX = 1 +regRLC_GPU_IOV_SCH_2 = 0x5b3c +regRLC_GPU_IOV_SCH_2_BASE_IDX = 1 +regRLC_PACE_INT_FORCE = 0x5b3d +regRLC_PACE_INT_FORCE_BASE_IDX = 1 +regRLC_PACE_INT_CLEAR = 0x5b3e +regRLC_PACE_INT_CLEAR_BASE_IDX = 1 +regRLC_GPU_IOV_INT_STAT = 0x5b3f +regRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 +regRLC_IH_COOKIE = 0x5b41 +regRLC_IH_COOKIE_BASE_IDX = 1 +regRLC_IH_COOKIE_CNTL = 0x5b42 +regRLC_IH_COOKIE_CNTL_BASE_IDX = 1 +regRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 +regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 +regRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 +regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 +regRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 +regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 +regRLC_GPU_IOV_F32_CNTL = 0x5b46 +regRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 +regRLC_GPU_IOV_F32_RESET = 0x5b47 +regRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 +regRLC_GPU_IOV_UCODE_ADDR = 0x5b48 +regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 +regRLC_GPU_IOV_UCODE_DATA = 0x5b49 +regRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 +regRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a +regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 +regRLC_GPU_IOV_F32_INVALIDATE_CACHE = 0x5b4b +regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX = 1 +regRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d +regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 +regRLC_GPU_IOV_INT_DISABLE = 0x5b4e +regRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 +regRLC_GPU_IOV_INT_FORCE = 0x5b4f +regRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 +regRLC_GPU_IOV_SCRATCH_ADDR = 0x5b50 +regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 +regRLC_GPU_IOV_SCRATCH_DATA = 0x5b51 +regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 +regRLC_HYP_SEMAPHORE_2 = 0x5b52 +regRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 +regRLC_HYP_SEMAPHORE_3 = 0x5b53 +regRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 +regRLC_GPM_UCODE_ADDR = 0x5b60 +regRLC_GPM_UCODE_ADDR_BASE_IDX = 1 +regRLC_GPM_UCODE_DATA = 0x5b61 +regRLC_GPM_UCODE_DATA_BASE_IDX = 1 +regRLC_GPM_IRAM_ADDR = 0x5b62 +regRLC_GPM_IRAM_ADDR_BASE_IDX = 1 +regRLC_GPM_IRAM_DATA = 0x5b63 +regRLC_GPM_IRAM_DATA_BASE_IDX = 1 +regRLC_RLCP_IRAM_ADDR = 0x5b64 +regRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 +regRLC_RLCP_IRAM_DATA = 0x5b65 +regRLC_RLCP_IRAM_DATA_BASE_IDX = 1 +regRLC_RLCV_IRAM_ADDR = 0x5b66 +regRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 +regRLC_RLCV_IRAM_DATA = 0x5b67 +regRLC_RLCV_IRAM_DATA_BASE_IDX = 1 +regRLC_LX6_DRAM_ADDR = 0x5b68 +regRLC_LX6_DRAM_ADDR_BASE_IDX = 1 +regRLC_LX6_DRAM_DATA = 0x5b69 +regRLC_LX6_DRAM_DATA_BASE_IDX = 1 +regRLC_LX6_IRAM_ADDR = 0x5b6a +regRLC_LX6_IRAM_ADDR_BASE_IDX = 1 +regRLC_LX6_IRAM_DATA = 0x5b6b +regRLC_LX6_IRAM_DATA_BASE_IDX = 1 +regRLC_PACE_UCODE_ADDR = 0x5b6c +regRLC_PACE_UCODE_ADDR_BASE_IDX = 1 +regRLC_PACE_UCODE_DATA = 0x5b6d +regRLC_PACE_UCODE_DATA_BASE_IDX = 1 +regRLC_GPM_SCRATCH_ADDR = 0x5b6e +regRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 +regRLC_GPM_SCRATCH_DATA = 0x5b6f +regRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 +regRLC_SRM_DRAM_ADDR = 0x5b71 +regRLC_SRM_DRAM_ADDR_BASE_IDX = 1 +regRLC_SRM_DRAM_DATA = 0x5b72 +regRLC_SRM_DRAM_DATA_BASE_IDX = 1 +regRLC_SRM_ARAM_ADDR = 0x5b73 +regRLC_SRM_ARAM_ADDR_BASE_IDX = 1 +regRLC_SRM_ARAM_DATA = 0x5b74 +regRLC_SRM_ARAM_DATA_BASE_IDX = 1 +regRLC_PACE_SCRATCH_ADDR = 0x5b77 +regRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 +regRLC_PACE_SCRATCH_DATA = 0x5b78 +regRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 +regRLC_GTS_OFFSET_LSB = 0x5b79 +regRLC_GTS_OFFSET_LSB_BASE_IDX = 1 +regRLC_GTS_OFFSET_MSB = 0x5b7a +regRLC_GTS_OFFSET_MSB_BASE_IDX = 1 +regGL2_PIPE_STEER_0 = 0x5b80 +regGL2_PIPE_STEER_0_BASE_IDX = 1 +regGL2_PIPE_STEER_1 = 0x5b81 +regGL2_PIPE_STEER_1_BASE_IDX = 1 +regGL2_PIPE_STEER_2 = 0x5b82 +regGL2_PIPE_STEER_2_BASE_IDX = 1 +regGL2_PIPE_STEER_3 = 0x5b83 +regGL2_PIPE_STEER_3_BASE_IDX = 1 +regGL1_PIPE_STEER = 0x5b84 +regGL1_PIPE_STEER_BASE_IDX = 1 +regCH_PIPE_STEER = 0x5b88 +regCH_PIPE_STEER_BASE_IDX = 1 +regGC_USER_SHADER_ARRAY_CONFIG = 0x5b90 +regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 1 +regGC_USER_PRIM_CONFIG = 0x5b91 +regGC_USER_PRIM_CONFIG_BASE_IDX = 1 +regGC_USER_SA_UNIT_DISABLE = 0x5b92 +regGC_USER_SA_UNIT_DISABLE_BASE_IDX = 1 +regGC_USER_RB_REDUNDANCY = 0x5b93 +regGC_USER_RB_REDUNDANCY_BASE_IDX = 1 +regGC_USER_RB_BACKEND_DISABLE = 0x5b94 +regGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 1 +regGC_USER_RMI_REDUNDANCY = 0x5b95 +regGC_USER_RMI_REDUNDANCY_BASE_IDX = 1 +regCGTS_USER_TCC_DISABLE = 0x5b96 +regCGTS_USER_TCC_DISABLE_BASE_IDX = 1 +regGC_USER_SHADER_RATE_CONFIG = 0x5b97 +regGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 +regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 +regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 +regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 +regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 +regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 +regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 +regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 +regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 +regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 +regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca +regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb +regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc +regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd +regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce +regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 +regRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf +regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 +regCP_MES_DM_INDEX_ADDR = 0x5c00 +regCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 +regCP_MES_DM_INDEX_DATA = 0x5c01 +regCP_MES_DM_INDEX_DATA_BASE_IDX = 1 +regCP_MEC_DM_INDEX_ADDR = 0x5c02 +regCP_MEC_DM_INDEX_ADDR_BASE_IDX = 1 +regCP_MEC_DM_INDEX_DATA = 0x5c03 +regCP_MEC_DM_INDEX_DATA_BASE_IDX = 1 +regCP_GFX_RS64_DM_INDEX_ADDR = 0x5c04 +regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX = 1 +regCP_GFX_RS64_DM_INDEX_DATA = 0x5c05 +regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX = 1 +regCPG_PSP_DEBUG = 0x5c10 +regCPG_PSP_DEBUG_BASE_IDX = 1 +regCPC_PSP_DEBUG = 0x5c11 +regCPC_PSP_DEBUG_BASE_IDX = 1 +regGRBM_SEC_CNTL = 0x5e0d +regGRBM_SEC_CNTL_BASE_IDX = 1 +regGRBM_CAM_INDEX = 0x5e10 +regGRBM_CAM_INDEX_BASE_IDX = 1 +regGRBM_HYP_CAM_INDEX = 0x5e10 +regGRBM_HYP_CAM_INDEX_BASE_IDX = 1 +regGRBM_CAM_DATA = 0x5e11 +regGRBM_CAM_DATA_BASE_IDX = 1 +regGRBM_HYP_CAM_DATA = 0x5e11 +regGRBM_HYP_CAM_DATA_BASE_IDX = 1 +regGRBM_CAM_DATA_UPPER = 0x5e12 +regGRBM_CAM_DATA_UPPER_BASE_IDX = 1 +regGRBM_HYP_CAM_DATA_UPPER = 0x5e12 +regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 +regRLC_FWL_FIRST_VIOL_ADDR = 0x5f26 +regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 +regGFX_IMU_C2PMSG_0 = 0x4000 +regGFX_IMU_C2PMSG_0_BASE_IDX = 1 +regGFX_IMU_C2PMSG_1 = 0x4001 +regGFX_IMU_C2PMSG_1_BASE_IDX = 1 +regGFX_IMU_C2PMSG_2 = 0x4002 +regGFX_IMU_C2PMSG_2_BASE_IDX = 1 +regGFX_IMU_C2PMSG_3 = 0x4003 +regGFX_IMU_C2PMSG_3_BASE_IDX = 1 +regGFX_IMU_C2PMSG_4 = 0x4004 +regGFX_IMU_C2PMSG_4_BASE_IDX = 1 +regGFX_IMU_C2PMSG_5 = 0x4005 +regGFX_IMU_C2PMSG_5_BASE_IDX = 1 +regGFX_IMU_C2PMSG_6 = 0x4006 +regGFX_IMU_C2PMSG_6_BASE_IDX = 1 +regGFX_IMU_C2PMSG_7 = 0x4007 +regGFX_IMU_C2PMSG_7_BASE_IDX = 1 +regGFX_IMU_C2PMSG_8 = 0x4008 +regGFX_IMU_C2PMSG_8_BASE_IDX = 1 +regGFX_IMU_C2PMSG_9 = 0x4009 +regGFX_IMU_C2PMSG_9_BASE_IDX = 1 +regGFX_IMU_C2PMSG_10 = 0x400a +regGFX_IMU_C2PMSG_10_BASE_IDX = 1 +regGFX_IMU_C2PMSG_11 = 0x400b +regGFX_IMU_C2PMSG_11_BASE_IDX = 1 +regGFX_IMU_C2PMSG_12 = 0x400c +regGFX_IMU_C2PMSG_12_BASE_IDX = 1 +regGFX_IMU_C2PMSG_13 = 0x400d +regGFX_IMU_C2PMSG_13_BASE_IDX = 1 +regGFX_IMU_C2PMSG_14 = 0x400e +regGFX_IMU_C2PMSG_14_BASE_IDX = 1 +regGFX_IMU_C2PMSG_15 = 0x400f +regGFX_IMU_C2PMSG_15_BASE_IDX = 1 +regGFX_IMU_C2PMSG_16 = 0x4010 +regGFX_IMU_C2PMSG_16_BASE_IDX = 1 +regGFX_IMU_C2PMSG_17 = 0x4011 +regGFX_IMU_C2PMSG_17_BASE_IDX = 1 +regGFX_IMU_C2PMSG_18 = 0x4012 +regGFX_IMU_C2PMSG_18_BASE_IDX = 1 +regGFX_IMU_C2PMSG_19 = 0x4013 +regGFX_IMU_C2PMSG_19_BASE_IDX = 1 +regGFX_IMU_C2PMSG_20 = 0x4014 +regGFX_IMU_C2PMSG_20_BASE_IDX = 1 +regGFX_IMU_C2PMSG_21 = 0x4015 +regGFX_IMU_C2PMSG_21_BASE_IDX = 1 +regGFX_IMU_C2PMSG_22 = 0x4016 +regGFX_IMU_C2PMSG_22_BASE_IDX = 1 +regGFX_IMU_C2PMSG_23 = 0x4017 +regGFX_IMU_C2PMSG_23_BASE_IDX = 1 +regGFX_IMU_C2PMSG_24 = 0x4018 +regGFX_IMU_C2PMSG_24_BASE_IDX = 1 +regGFX_IMU_C2PMSG_25 = 0x4019 +regGFX_IMU_C2PMSG_25_BASE_IDX = 1 +regGFX_IMU_C2PMSG_26 = 0x401a +regGFX_IMU_C2PMSG_26_BASE_IDX = 1 +regGFX_IMU_C2PMSG_27 = 0x401b +regGFX_IMU_C2PMSG_27_BASE_IDX = 1 +regGFX_IMU_C2PMSG_28 = 0x401c +regGFX_IMU_C2PMSG_28_BASE_IDX = 1 +regGFX_IMU_C2PMSG_29 = 0x401d +regGFX_IMU_C2PMSG_29_BASE_IDX = 1 +regGFX_IMU_C2PMSG_30 = 0x401e +regGFX_IMU_C2PMSG_30_BASE_IDX = 1 +regGFX_IMU_C2PMSG_31 = 0x401f +regGFX_IMU_C2PMSG_31_BASE_IDX = 1 +regGFX_IMU_C2PMSG_32 = 0x4020 +regGFX_IMU_C2PMSG_32_BASE_IDX = 1 +regGFX_IMU_C2PMSG_33 = 0x4021 +regGFX_IMU_C2PMSG_33_BASE_IDX = 1 +regGFX_IMU_C2PMSG_34 = 0x4022 +regGFX_IMU_C2PMSG_34_BASE_IDX = 1 +regGFX_IMU_C2PMSG_35 = 0x4023 +regGFX_IMU_C2PMSG_35_BASE_IDX = 1 +regGFX_IMU_C2PMSG_36 = 0x4024 +regGFX_IMU_C2PMSG_36_BASE_IDX = 1 +regGFX_IMU_C2PMSG_37 = 0x4025 +regGFX_IMU_C2PMSG_37_BASE_IDX = 1 +regGFX_IMU_C2PMSG_38 = 0x4026 +regGFX_IMU_C2PMSG_38_BASE_IDX = 1 +regGFX_IMU_C2PMSG_39 = 0x4027 +regGFX_IMU_C2PMSG_39_BASE_IDX = 1 +regGFX_IMU_C2PMSG_40 = 0x4028 +regGFX_IMU_C2PMSG_40_BASE_IDX = 1 +regGFX_IMU_C2PMSG_41 = 0x4029 +regGFX_IMU_C2PMSG_41_BASE_IDX = 1 +regGFX_IMU_C2PMSG_42 = 0x402a +regGFX_IMU_C2PMSG_42_BASE_IDX = 1 +regGFX_IMU_C2PMSG_43 = 0x402b +regGFX_IMU_C2PMSG_43_BASE_IDX = 1 +regGFX_IMU_C2PMSG_44 = 0x402c +regGFX_IMU_C2PMSG_44_BASE_IDX = 1 +regGFX_IMU_C2PMSG_45 = 0x402d +regGFX_IMU_C2PMSG_45_BASE_IDX = 1 +regGFX_IMU_C2PMSG_46 = 0x402e +regGFX_IMU_C2PMSG_46_BASE_IDX = 1 +regGFX_IMU_C2PMSG_47 = 0x402f +regGFX_IMU_C2PMSG_47_BASE_IDX = 1 +regGFX_IMU_MSG_FLAGS = 0x403f +regGFX_IMU_MSG_FLAGS_BASE_IDX = 1 +regGFX_IMU_C2PMSG_ACCESS_CTRL0 = 0x4040 +regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX = 1 +regGFX_IMU_C2PMSG_ACCESS_CTRL1 = 0x4041 +regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX = 1 +regGFX_IMU_PWRMGT_IRQ_CTRL = 0x4042 +regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX = 1 +regGFX_IMU_MP1_MUTEX = 0x4043 +regGFX_IMU_MP1_MUTEX_BASE_IDX = 1 +regGFX_IMU_RLC_DATA_4 = 0x4046 +regGFX_IMU_RLC_DATA_4_BASE_IDX = 1 +regGFX_IMU_RLC_DATA_3 = 0x4047 +regGFX_IMU_RLC_DATA_3_BASE_IDX = 1 +regGFX_IMU_RLC_DATA_2 = 0x4048 +regGFX_IMU_RLC_DATA_2_BASE_IDX = 1 +regGFX_IMU_RLC_DATA_1 = 0x4049 +regGFX_IMU_RLC_DATA_1_BASE_IDX = 1 +regGFX_IMU_RLC_DATA_0 = 0x404a +regGFX_IMU_RLC_DATA_0_BASE_IDX = 1 +regGFX_IMU_RLC_CMD = 0x404b +regGFX_IMU_RLC_CMD_BASE_IDX = 1 +regGFX_IMU_RLC_MUTEX = 0x404c +regGFX_IMU_RLC_MUTEX_BASE_IDX = 1 +regGFX_IMU_RLC_MSG_STATUS = 0x404f +regGFX_IMU_RLC_MSG_STATUS_BASE_IDX = 1 +regRLC_GFX_IMU_DATA_0 = 0x4052 +regRLC_GFX_IMU_DATA_0_BASE_IDX = 1 +regRLC_GFX_IMU_CMD = 0x4053 +regRLC_GFX_IMU_CMD_BASE_IDX = 1 +regGFX_IMU_RLC_STATUS = 0x4054 +regGFX_IMU_RLC_STATUS_BASE_IDX = 1 +regGFX_IMU_STATUS = 0x4055 +regGFX_IMU_STATUS_BASE_IDX = 1 +regGFX_IMU_SOC_DATA = 0x4059 +regGFX_IMU_SOC_DATA_BASE_IDX = 1 +regGFX_IMU_SOC_ADDR = 0x405a +regGFX_IMU_SOC_ADDR_BASE_IDX = 1 +regGFX_IMU_SOC_REQ = 0x405b +regGFX_IMU_SOC_REQ_BASE_IDX = 1 +regGFX_IMU_VF_CTRL = 0x405c +regGFX_IMU_VF_CTRL_BASE_IDX = 1 +regGFX_IMU_TELEMETRY = 0x4060 +regGFX_IMU_TELEMETRY_BASE_IDX = 1 +regGFX_IMU_TELEMETRY_DATA = 0x4061 +regGFX_IMU_TELEMETRY_DATA_BASE_IDX = 1 +regGFX_IMU_TELEMETRY_TEMPERATURE = 0x4062 +regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX = 1 +regGFX_IMU_SCRATCH_0 = 0x4068 +regGFX_IMU_SCRATCH_0_BASE_IDX = 1 +regGFX_IMU_SCRATCH_1 = 0x4069 +regGFX_IMU_SCRATCH_1_BASE_IDX = 1 +regGFX_IMU_SCRATCH_2 = 0x406a +regGFX_IMU_SCRATCH_2_BASE_IDX = 1 +regGFX_IMU_SCRATCH_3 = 0x406b +regGFX_IMU_SCRATCH_3_BASE_IDX = 1 +regGFX_IMU_SCRATCH_4 = 0x406c +regGFX_IMU_SCRATCH_4_BASE_IDX = 1 +regGFX_IMU_SCRATCH_5 = 0x406d +regGFX_IMU_SCRATCH_5_BASE_IDX = 1 +regGFX_IMU_SCRATCH_6 = 0x406e +regGFX_IMU_SCRATCH_6_BASE_IDX = 1 +regGFX_IMU_SCRATCH_7 = 0x406f +regGFX_IMU_SCRATCH_7_BASE_IDX = 1 +regGFX_IMU_SCRATCH_8 = 0x4070 +regGFX_IMU_SCRATCH_8_BASE_IDX = 1 +regGFX_IMU_SCRATCH_9 = 0x4071 +regGFX_IMU_SCRATCH_9_BASE_IDX = 1 +regGFX_IMU_SCRATCH_10 = 0x4072 +regGFX_IMU_SCRATCH_10_BASE_IDX = 1 +regGFX_IMU_SCRATCH_11 = 0x4073 +regGFX_IMU_SCRATCH_11_BASE_IDX = 1 +regGFX_IMU_SCRATCH_12 = 0x4074 +regGFX_IMU_SCRATCH_12_BASE_IDX = 1 +regGFX_IMU_SCRATCH_13 = 0x4075 +regGFX_IMU_SCRATCH_13_BASE_IDX = 1 +regGFX_IMU_SCRATCH_14 = 0x4076 +regGFX_IMU_SCRATCH_14_BASE_IDX = 1 +regGFX_IMU_SCRATCH_15 = 0x4077 +regGFX_IMU_SCRATCH_15_BASE_IDX = 1 +regGFX_IMU_FW_GTS_LO = 0x4078 +regGFX_IMU_FW_GTS_LO_BASE_IDX = 1 +regGFX_IMU_FW_GTS_HI = 0x4079 +regGFX_IMU_FW_GTS_HI_BASE_IDX = 1 +regGFX_IMU_GTS_OFFSET_LO = 0x407a +regGFX_IMU_GTS_OFFSET_LO_BASE_IDX = 1 +regGFX_IMU_GTS_OFFSET_HI = 0x407b +regGFX_IMU_GTS_OFFSET_HI_BASE_IDX = 1 +regGFX_IMU_RLC_GTS_OFFSET_LO = 0x407c +regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX = 1 +regGFX_IMU_RLC_GTS_OFFSET_HI = 0x407d +regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX = 1 +regGFX_IMU_CORE_INT_STATUS = 0x407f +regGFX_IMU_CORE_INT_STATUS_BASE_IDX = 1 +regGFX_IMU_PIC_INT_MASK = 0x4080 +regGFX_IMU_PIC_INT_MASK_BASE_IDX = 1 +regGFX_IMU_PIC_INT_LVL = 0x4081 +regGFX_IMU_PIC_INT_LVL_BASE_IDX = 1 +regGFX_IMU_PIC_INT_EDGE = 0x4082 +regGFX_IMU_PIC_INT_EDGE_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_0 = 0x4083 +regGFX_IMU_PIC_INT_PRI_0_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_1 = 0x4084 +regGFX_IMU_PIC_INT_PRI_1_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_2 = 0x4085 +regGFX_IMU_PIC_INT_PRI_2_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_3 = 0x4086 +regGFX_IMU_PIC_INT_PRI_3_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_4 = 0x4087 +regGFX_IMU_PIC_INT_PRI_4_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_5 = 0x4088 +regGFX_IMU_PIC_INT_PRI_5_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_6 = 0x4089 +regGFX_IMU_PIC_INT_PRI_6_BASE_IDX = 1 +regGFX_IMU_PIC_INT_PRI_7 = 0x408a +regGFX_IMU_PIC_INT_PRI_7_BASE_IDX = 1 +regGFX_IMU_PIC_INT_STATUS = 0x408b +regGFX_IMU_PIC_INT_STATUS_BASE_IDX = 1 +regGFX_IMU_PIC_INTR = 0x408c +regGFX_IMU_PIC_INTR_BASE_IDX = 1 +regGFX_IMU_PIC_INTR_ID = 0x408d +regGFX_IMU_PIC_INTR_ID_BASE_IDX = 1 +regGFX_IMU_IH_CTRL_1 = 0x4090 +regGFX_IMU_IH_CTRL_1_BASE_IDX = 1 +regGFX_IMU_IH_CTRL_2 = 0x4091 +regGFX_IMU_IH_CTRL_2_BASE_IDX = 1 +regGFX_IMU_IH_CTRL_3 = 0x4092 +regGFX_IMU_IH_CTRL_3_BASE_IDX = 1 +regGFX_IMU_IH_STATUS = 0x4093 +regGFX_IMU_IH_STATUS_BASE_IDX = 1 +regGFX_IMU_FUSESTRAP = 0x4094 +regGFX_IMU_SMUIO_VIDCHG_CTRL = 0x4098 +regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 +regGFX_IMU_GFXCLK_BYPASS_CTRL = 0x409c +regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX = 1 +regGFX_IMU_CLK_CTRL = 0x409d +regGFX_IMU_CLK_CTRL_BASE_IDX = 1 +regGFX_IMU_DOORBELL_CONTROL = 0x409e +regGFX_IMU_DOORBELL_CONTROL_BASE_IDX = 1 +regGFX_IMU_RLC_CG_CTRL = 0x40a0 +regGFX_IMU_RLC_CG_CTRL_BASE_IDX = 1 +regGFX_IMU_RLC_THROTTLE_GFX = 0x40a1 +regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX = 1 +regGFX_IMU_RLC_RESET_VECTOR = 0x40a2 +regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX = 1 +regGFX_IMU_RLC_OVERRIDE = 0x40a3 +regGFX_IMU_RLC_OVERRIDE_BASE_IDX = 1 +regGFX_IMU_DPM_CONTROL = 0x40a8 +regGFX_IMU_DPM_CONTROL_BASE_IDX = 1 +regGFX_IMU_DPM_ACC = 0x40a9 +regGFX_IMU_DPM_ACC_BASE_IDX = 1 +regGFX_IMU_DPM_REF_COUNTER = 0x40aa +regGFX_IMU_DPM_REF_COUNTER_BASE_IDX = 1 +regGFX_IMU_RLC_RAM_INDEX = 0x40ac +regGFX_IMU_RLC_RAM_INDEX_BASE_IDX = 1 +regGFX_IMU_RLC_RAM_ADDR_HIGH = 0x40ad +regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX = 1 +regGFX_IMU_RLC_RAM_ADDR_LOW = 0x40ae +regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX = 1 +regGFX_IMU_RLC_RAM_DATA = 0x40af +regGFX_IMU_RLC_RAM_DATA_BASE_IDX = 1 +regGFX_IMU_FENCE_CTRL = 0x40b0 +regGFX_IMU_FENCE_CTRL_BASE_IDX = 1 +regGFX_IMU_FENCE_LOG_INIT = 0x40b1 +regGFX_IMU_FENCE_LOG_INIT_BASE_IDX = 1 +regGFX_IMU_FENCE_LOG_ADDR = 0x40b2 +regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX = 1 +regGFX_IMU_PROGRAM_CTR = 0x40b5 +regGFX_IMU_PROGRAM_CTR_BASE_IDX = 1 +regGFX_IMU_CORE_CTRL = 0x40b6 +regGFX_IMU_CORE_CTRL_BASE_IDX = 1 +regGFX_IMU_CORE_STATUS = 0x40b7 +regGFX_IMU_CORE_STATUS_BASE_IDX = 1 +regGFX_IMU_PWROKRAW = 0x40b8 +regGFX_IMU_PWROKRAW_BASE_IDX = 1 +regGFX_IMU_PWROK = 0x40b9 +regGFX_IMU_PWROK_BASE_IDX = 1 +regGFX_IMU_GAP_PWROK = 0x40ba +regGFX_IMU_GAP_PWROK_BASE_IDX = 1 +regGFX_IMU_RESETn = 0x40bb +regGFX_IMU_RESETn_BASE_IDX = 1 +regGFX_IMU_GFX_RESET_CTRL = 0x40bc +regGFX_IMU_GFX_RESET_CTRL_BASE_IDX = 1 +regGFX_IMU_AEB_OVERRIDE = 0x40bd +regGFX_IMU_AEB_OVERRIDE_BASE_IDX = 1 +regGFX_IMU_VDCI_RESET_CTRL = 0x40be +regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX = 1 +regGFX_IMU_GFX_ISO_CTRL = 0x40bf +regGFX_IMU_GFX_ISO_CTRL_BASE_IDX = 1 +regGFX_IMU_TIMER0_CTRL0 = 0x40c0 +regGFX_IMU_TIMER0_CTRL0_BASE_IDX = 1 +regGFX_IMU_TIMER0_CTRL1 = 0x40c1 +regGFX_IMU_TIMER0_CTRL1_BASE_IDX = 1 +regGFX_IMU_TIMER0_CMP_AUTOINC = 0x40c2 +regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX = 1 +regGFX_IMU_TIMER0_CMP_INTEN = 0x40c3 +regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX = 1 +regGFX_IMU_TIMER0_CMP0 = 0x40c4 +regGFX_IMU_TIMER0_CMP0_BASE_IDX = 1 +regGFX_IMU_TIMER0_CMP1 = 0x40c5 +regGFX_IMU_TIMER0_CMP1_BASE_IDX = 1 +regGFX_IMU_TIMER0_CMP3 = 0x40c7 +regGFX_IMU_TIMER0_CMP3_BASE_IDX = 1 +regGFX_IMU_TIMER0_VALUE = 0x40c8 +regGFX_IMU_TIMER0_VALUE_BASE_IDX = 1 +regGFX_IMU_TIMER1_CTRL0 = 0x40c9 +regGFX_IMU_TIMER1_CTRL0_BASE_IDX = 1 +regGFX_IMU_TIMER1_CTRL1 = 0x40ca +regGFX_IMU_TIMER1_CTRL1_BASE_IDX = 1 +regGFX_IMU_TIMER1_CMP_AUTOINC = 0x40cb +regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX = 1 +regGFX_IMU_TIMER1_CMP_INTEN = 0x40cc +regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX = 1 +regGFX_IMU_TIMER1_CMP0 = 0x40cd +regGFX_IMU_TIMER1_CMP0_BASE_IDX = 1 +regGFX_IMU_TIMER1_CMP1 = 0x40ce +regGFX_IMU_TIMER1_CMP1_BASE_IDX = 1 +regGFX_IMU_TIMER1_CMP3 = 0x40d0 +regGFX_IMU_TIMER1_CMP3_BASE_IDX = 1 +regGFX_IMU_TIMER1_VALUE = 0x40d1 +regGFX_IMU_TIMER1_VALUE_BASE_IDX = 1 +regGFX_IMU_TIMER2_CTRL0 = 0x40d2 +regGFX_IMU_TIMER2_CTRL0_BASE_IDX = 1 +regGFX_IMU_TIMER2_CTRL1 = 0x40d3 +regGFX_IMU_TIMER2_CTRL1_BASE_IDX = 1 +regGFX_IMU_TIMER2_CMP_AUTOINC = 0x40d4 +regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX = 1 +regGFX_IMU_TIMER2_CMP_INTEN = 0x40d5 +regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX = 1 +regGFX_IMU_TIMER2_CMP0 = 0x40d6 +regGFX_IMU_TIMER2_CMP0_BASE_IDX = 1 +regGFX_IMU_TIMER2_CMP1 = 0x40d7 +regGFX_IMU_TIMER2_CMP1_BASE_IDX = 1 +regGFX_IMU_TIMER2_CMP3 = 0x40d9 +regGFX_IMU_TIMER2_CMP3_BASE_IDX = 1 +regGFX_IMU_TIMER2_VALUE = 0x40da +regGFX_IMU_TIMER2_VALUE_BASE_IDX = 1 +regGFX_IMU_FUSE_CTRL = 0x40e0 +regGFX_IMU_FUSE_CTRL_BASE_IDX = 1 +regGFX_IMU_D_RAM_ADDR = 0x40fc +regGFX_IMU_D_RAM_ADDR_BASE_IDX = 1 +regGFX_IMU_D_RAM_DATA = 0x40fd +regGFX_IMU_D_RAM_DATA_BASE_IDX = 1 +regGFX_IMU_GFX_IH_GASKET_CTRL = 0x40ff +regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX = 1 +regGFX_IMU_RLC_BOOTLOADER_ADDR_HI = 0x5f81 +regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX = 1 +regGFX_IMU_RLC_BOOTLOADER_ADDR_LO = 0x5f82 +regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX = 1 +regGFX_IMU_RLC_BOOTLOADER_SIZE = 0x5f83 +regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX = 1 +regGFX_IMU_I_RAM_ADDR = 0x5f90 +regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 +regGFX_IMU_I_RAM_DATA = 0x5f91 +regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 +ixGC_CAC_ID = 0x0000 +ixGC_CAC_CNTL = 0x0001 +ixGC_CAC_ACC_CP0 = 0x0010 +ixGC_CAC_ACC_CP1 = 0x0011 +ixGC_CAC_ACC_CP2 = 0x0012 +ixGC_CAC_ACC_EA0 = 0x0013 +ixGC_CAC_ACC_EA1 = 0x0014 +ixGC_CAC_ACC_EA2 = 0x0015 +ixGC_CAC_ACC_EA3 = 0x0016 +ixGC_CAC_ACC_EA4 = 0x0017 +ixGC_CAC_ACC_EA5 = 0x0018 +ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0019 +ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x001a +ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x001b +ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x001c +ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x001d +ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x001e +ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x001f +ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x0020 +ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x0021 +ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0022 +ixGC_CAC_ACC_UTCL2_VML20 = 0x0023 +ixGC_CAC_ACC_UTCL2_VML21 = 0x0024 +ixGC_CAC_ACC_UTCL2_VML22 = 0x0025 +ixGC_CAC_ACC_UTCL2_VML23 = 0x0026 +ixGC_CAC_ACC_UTCL2_VML24 = 0x0027 +ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0028 +ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0029 +ixGC_CAC_ACC_UTCL2_WALKER2 = 0x002a +ixGC_CAC_ACC_UTCL2_WALKER3 = 0x002b +ixGC_CAC_ACC_UTCL2_WALKER4 = 0x002c +ixGC_CAC_ACC_GDS0 = 0x002d +ixGC_CAC_ACC_GDS1 = 0x002e +ixGC_CAC_ACC_GDS2 = 0x002f +ixGC_CAC_ACC_GDS3 = 0x0030 +ixGC_CAC_ACC_GDS4 = 0x0031 +ixGC_CAC_ACC_GE0 = 0x0032 +ixGC_CAC_ACC_GE1 = 0x0033 +ixGC_CAC_ACC_GE2 = 0x0034 +ixGC_CAC_ACC_GE3 = 0x0035 +ixGC_CAC_ACC_GE4 = 0x0036 +ixGC_CAC_ACC_GE5 = 0x0037 +ixGC_CAC_ACC_GE6 = 0x0038 +ixGC_CAC_ACC_GE7 = 0x0039 +ixGC_CAC_ACC_GE8 = 0x003a +ixGC_CAC_ACC_GE9 = 0x003b +ixGC_CAC_ACC_GE10 = 0x003c +ixGC_CAC_ACC_GE11 = 0x003d +ixGC_CAC_ACC_GE12 = 0x003e +ixGC_CAC_ACC_GE13 = 0x003f +ixGC_CAC_ACC_GE14 = 0x0040 +ixGC_CAC_ACC_GE15 = 0x0041 +ixGC_CAC_ACC_GE16 = 0x0042 +ixGC_CAC_ACC_GE17 = 0x0043 +ixGC_CAC_ACC_GE18 = 0x0044 +ixGC_CAC_ACC_GE19 = 0x0045 +ixGC_CAC_ACC_GE20 = 0x0046 +ixGC_CAC_ACC_PMM0 = 0x0047 +ixGC_CAC_ACC_GL2C0 = 0x0048 +ixGC_CAC_ACC_GL2C1 = 0x0049 +ixGC_CAC_ACC_GL2C2 = 0x004a +ixGC_CAC_ACC_GL2C3 = 0x004b +ixGC_CAC_ACC_GL2C4 = 0x004c +ixGC_CAC_ACC_PH0 = 0x004d +ixGC_CAC_ACC_PH1 = 0x004e +ixGC_CAC_ACC_PH2 = 0x004f +ixGC_CAC_ACC_PH3 = 0x0050 +ixGC_CAC_ACC_PH4 = 0x0051 +ixGC_CAC_ACC_PH5 = 0x0052 +ixGC_CAC_ACC_PH6 = 0x0053 +ixGC_CAC_ACC_PH7 = 0x0054 +ixGC_CAC_ACC_SDMA0 = 0x0055 +ixGC_CAC_ACC_SDMA1 = 0x0056 +ixGC_CAC_ACC_SDMA2 = 0x0057 +ixGC_CAC_ACC_SDMA3 = 0x0058 +ixGC_CAC_ACC_SDMA4 = 0x0059 +ixGC_CAC_ACC_SDMA5 = 0x005a +ixGC_CAC_ACC_SDMA6 = 0x005b +ixGC_CAC_ACC_SDMA7 = 0x005c +ixGC_CAC_ACC_SDMA8 = 0x005d +ixGC_CAC_ACC_SDMA9 = 0x005e +ixGC_CAC_ACC_SDMA10 = 0x005f +ixGC_CAC_ACC_SDMA11 = 0x0060 +ixGC_CAC_ACC_CHC0 = 0x0061 +ixGC_CAC_ACC_CHC1 = 0x0062 +ixGC_CAC_ACC_CHC2 = 0x0063 +ixGC_CAC_ACC_GUS0 = 0x0064 +ixGC_CAC_ACC_GUS1 = 0x0065 +ixGC_CAC_ACC_GUS2 = 0x0066 +ixGC_CAC_ACC_RLC0 = 0x0067 +ixRELEASE_TO_STALL_LUT_1_8 = 0x0100 +ixRELEASE_TO_STALL_LUT_9_16 = 0x0101 +ixRELEASE_TO_STALL_LUT_17_20 = 0x0102 +ixSTALL_TO_RELEASE_LUT_1_4 = 0x0103 +ixSTALL_TO_RELEASE_LUT_5_7 = 0x0104 +ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0105 +ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0106 +ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0107 +ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0108 +ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0109 +ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x010a +ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x010b +ixFIXED_PATTERN_PERF_COUNTER_1 = 0x010c +ixFIXED_PATTERN_PERF_COUNTER_2 = 0x010d +ixFIXED_PATTERN_PERF_COUNTER_3 = 0x010e +ixFIXED_PATTERN_PERF_COUNTER_4 = 0x010f +ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0110 +ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0111 +ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0112 +ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0113 +ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0114 +ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0115 +ixHW_LUT_UPDATE_STATUS = 0x0116 +ixSE_CAC_ID = 0x0000 +ixSE_CAC_CNTL = 0x0001 +ixRTAVFS_REG0 = 0x0000 +ixRTAVFS_REG1 = 0x0001 +ixRTAVFS_REG2 = 0x0002 +ixRTAVFS_REG3 = 0x0003 +ixRTAVFS_REG4 = 0x0004 +ixRTAVFS_REG5 = 0x0005 +ixRTAVFS_REG6 = 0x0006 +ixRTAVFS_REG7 = 0x0007 +ixRTAVFS_REG8 = 0x0008 +ixRTAVFS_REG9 = 0x0009 +ixRTAVFS_REG10 = 0x000a +ixRTAVFS_REG11 = 0x000b +ixRTAVFS_REG12 = 0x000c +ixRTAVFS_REG13 = 0x000d +ixRTAVFS_REG14 = 0x000e +ixRTAVFS_REG15 = 0x000f +ixRTAVFS_REG16 = 0x0010 +ixRTAVFS_REG17 = 0x0011 +ixRTAVFS_REG18 = 0x0012 +ixRTAVFS_REG19 = 0x0013 +ixRTAVFS_REG20 = 0x0014 +ixRTAVFS_REG21 = 0x0015 +ixRTAVFS_REG22 = 0x0016 +ixRTAVFS_REG23 = 0x0017 +ixRTAVFS_REG24 = 0x0018 +ixRTAVFS_REG25 = 0x0019 +ixRTAVFS_REG26 = 0x001a +ixRTAVFS_REG27 = 0x001b +ixRTAVFS_REG28 = 0x001c +ixRTAVFS_REG29 = 0x001d +ixRTAVFS_REG30 = 0x001e +ixRTAVFS_REG31 = 0x001f +ixRTAVFS_REG32 = 0x0020 +ixRTAVFS_REG33 = 0x0021 +ixRTAVFS_REG34 = 0x0022 +ixRTAVFS_REG35 = 0x0023 +ixRTAVFS_REG36 = 0x0024 +ixRTAVFS_REG37 = 0x0025 +ixRTAVFS_REG38 = 0x0026 +ixRTAVFS_REG39 = 0x0027 +ixRTAVFS_REG40 = 0x0028 +ixRTAVFS_REG41 = 0x0029 +ixRTAVFS_REG42 = 0x002a +ixRTAVFS_REG43 = 0x002b +ixRTAVFS_REG44 = 0x002c +ixRTAVFS_REG45 = 0x002d +ixRTAVFS_REG46 = 0x002e +ixRTAVFS_REG47 = 0x002f +ixRTAVFS_REG48 = 0x0030 +ixRTAVFS_REG49 = 0x0031 +ixRTAVFS_REG50 = 0x0032 +ixRTAVFS_REG51 = 0x0033 +ixRTAVFS_REG52 = 0x0034 +ixRTAVFS_REG53 = 0x0035 +ixRTAVFS_REG54 = 0x0036 +ixRTAVFS_REG55 = 0x0037 +ixRTAVFS_REG56 = 0x0038 +ixRTAVFS_REG57 = 0x0039 +ixRTAVFS_REG58 = 0x003a +ixRTAVFS_REG59 = 0x003b +ixRTAVFS_REG60 = 0x003c +ixRTAVFS_REG61 = 0x003d +ixRTAVFS_REG62 = 0x003e +ixRTAVFS_REG63 = 0x003f +ixRTAVFS_REG64 = 0x0040 +ixRTAVFS_REG65 = 0x0041 +ixRTAVFS_REG66 = 0x0042 +ixRTAVFS_REG67 = 0x0043 +ixRTAVFS_REG68 = 0x0044 +ixRTAVFS_REG69 = 0x0045 +ixRTAVFS_REG70 = 0x0046 +ixRTAVFS_REG71 = 0x0047 +ixRTAVFS_REG72 = 0x0048 +ixRTAVFS_REG73 = 0x0049 +ixRTAVFS_REG74 = 0x004a +ixRTAVFS_REG75 = 0x004b +ixRTAVFS_REG76 = 0x004c +ixRTAVFS_REG77 = 0x004d +ixRTAVFS_REG78 = 0x004e +ixRTAVFS_REG79 = 0x004f +ixRTAVFS_REG80 = 0x0050 +ixRTAVFS_REG81 = 0x0051 +ixRTAVFS_REG82 = 0x0052 +ixRTAVFS_REG83 = 0x0053 +ixRTAVFS_REG84 = 0x0054 +ixRTAVFS_REG85 = 0x0055 +ixRTAVFS_REG86 = 0x0056 +ixRTAVFS_REG87 = 0x0057 +ixRTAVFS_REG88 = 0x0058 +ixRTAVFS_REG89 = 0x0059 +ixRTAVFS_REG90 = 0x005a +ixRTAVFS_REG91 = 0x005b +ixRTAVFS_REG92 = 0x005c +ixRTAVFS_REG93 = 0x005d +ixRTAVFS_REG94 = 0x005e +ixRTAVFS_REG95 = 0x005f +ixRTAVFS_REG96 = 0x0060 +ixRTAVFS_REG97 = 0x0061 +ixRTAVFS_REG98 = 0x0062 +ixRTAVFS_REG99 = 0x0063 +ixRTAVFS_REG100 = 0x0064 +ixRTAVFS_REG101 = 0x0065 +ixRTAVFS_REG102 = 0x0066 +ixRTAVFS_REG103 = 0x0067 +ixRTAVFS_REG104 = 0x0068 +ixRTAVFS_REG105 = 0x0069 +ixRTAVFS_REG106 = 0x006a +ixRTAVFS_REG107 = 0x006b +ixRTAVFS_REG108 = 0x006c +ixRTAVFS_REG109 = 0x006d +ixRTAVFS_REG110 = 0x006e +ixRTAVFS_REG111 = 0x006f +ixRTAVFS_REG112 = 0x0070 +ixRTAVFS_REG113 = 0x0071 +ixRTAVFS_REG114 = 0x0072 +ixRTAVFS_REG115 = 0x0073 +ixRTAVFS_REG116 = 0x0074 +ixRTAVFS_REG117 = 0x0075 +ixRTAVFS_REG118 = 0x0076 +ixRTAVFS_REG119 = 0x0077 +ixRTAVFS_REG120 = 0x0078 +ixRTAVFS_REG121 = 0x0079 +ixRTAVFS_REG122 = 0x007a +ixRTAVFS_REG123 = 0x007b +ixRTAVFS_REG124 = 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+VCN_BASE__INST2_SEG1 = 0 +VCN_BASE__INST2_SEG2 = 0 +VCN_BASE__INST2_SEG3 = 0 +VCN_BASE__INST2_SEG4 = 0 +VCN_BASE__INST3_SEG0 = 0 +VCN_BASE__INST3_SEG1 = 0 +VCN_BASE__INST3_SEG2 = 0 +VCN_BASE__INST3_SEG3 = 0 +VCN_BASE__INST3_SEG4 = 0 +VCN_BASE__INST4_SEG0 = 0 +VCN_BASE__INST4_SEG1 = 0 +VCN_BASE__INST4_SEG2 = 0 +VCN_BASE__INST4_SEG3 = 0 +VCN_BASE__INST4_SEG4 = 0 +VCN_BASE__INST5_SEG0 = 0 +VCN_BASE__INST5_SEG1 = 0 +VCN_BASE__INST5_SEG2 = 0 +VCN_BASE__INST5_SEG3 = 0 +VCN_BASE__INST5_SEG4 = 0 +VCN_BASE__INST6_SEG0 = 0 +VCN_BASE__INST6_SEG1 = 0 +VCN_BASE__INST6_SEG2 = 0 +VCN_BASE__INST6_SEG3 = 0 +VCN_BASE__INST6_SEG4 = 0 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/comgr.py b/tinygrad/runtime/autogen/comgr.py index 55779420a8..52123722d7 100644 --- a/tinygrad/runtime/autogen/comgr.py +++ b/tinygrad/runtime/autogen/comgr.py @@ -1,923 +1,405 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os -PATHS_TO_TRY = [ - '/opt/rocm/lib/libamd_comgr.so', - os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so', - '/usr/local/lib/libamd_comgr.dylib', - '/opt/homebrew/lib/libamd_comgr.dylib', -] -def _try_dlopen_amd_comgr(): - library = ctypes.util.find_library("amd_comgr") - if library: - try: return ctypes.CDLL(library) - except OSError: pass - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass +import ctypes, os +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +def dll(): + try: return ctypes.CDLL(unwrap(os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libamd_comgr.so')) + except: pass + try: return ctypes.CDLL(unwrap('/usr/local/lib/libamd_comgr.dylib')) + except: pass + try: return ctypes.CDLL(unwrap('/opt/homebrew/lib/libamd_comgr.dylib')) + except: pass return None +dll = dll() +amd_comgr_status_s = CEnum(ctypes.c_uint32) +AMD_COMGR_STATUS_SUCCESS = amd_comgr_status_s.define('AMD_COMGR_STATUS_SUCCESS', 0) +AMD_COMGR_STATUS_ERROR = amd_comgr_status_s.define('AMD_COMGR_STATUS_ERROR', 1) +AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = amd_comgr_status_s.define('AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', 2) +AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = amd_comgr_status_s.define('AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', 3) -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libamd_comgr.so'] = _try_dlopen_amd_comgr() -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - - -# values for enumeration 'amd_comgr_status_s' -amd_comgr_status_s__enumvalues = { - 0: 'AMD_COMGR_STATUS_SUCCESS', - 1: 'AMD_COMGR_STATUS_ERROR', - 2: 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 3: 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', -} -AMD_COMGR_STATUS_SUCCESS = 0 -AMD_COMGR_STATUS_ERROR = 1 -AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = 2 -AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = 3 -amd_comgr_status_s = ctypes.c_uint32 # enum amd_comgr_status_t = amd_comgr_status_s -amd_comgr_status_t__enumvalues = amd_comgr_status_s__enumvalues +amd_comgr_language_s = CEnum(ctypes.c_uint32) +AMD_COMGR_LANGUAGE_NONE = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_NONE', 0) +AMD_COMGR_LANGUAGE_OPENCL_1_2 = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_OPENCL_1_2', 1) +AMD_COMGR_LANGUAGE_OPENCL_2_0 = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_OPENCL_2_0', 2) +AMD_COMGR_LANGUAGE_HC = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_HC', 3) +AMD_COMGR_LANGUAGE_HIP = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_HIP', 4) +AMD_COMGR_LANGUAGE_LLVM_IR = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_LLVM_IR', 5) +AMD_COMGR_LANGUAGE_LAST = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_LAST', 5) -# values for enumeration 'amd_comgr_language_s' -amd_comgr_language_s__enumvalues = { - 0: 'AMD_COMGR_LANGUAGE_NONE', - 1: 'AMD_COMGR_LANGUAGE_OPENCL_1_2', - 2: 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 3: 'AMD_COMGR_LANGUAGE_HC', - 4: 'AMD_COMGR_LANGUAGE_HIP', - 5: 'AMD_COMGR_LANGUAGE_LLVM_IR', - 5: 'AMD_COMGR_LANGUAGE_LAST', -} -AMD_COMGR_LANGUAGE_NONE = 0 -AMD_COMGR_LANGUAGE_OPENCL_1_2 = 1 -AMD_COMGR_LANGUAGE_OPENCL_2_0 = 2 -AMD_COMGR_LANGUAGE_HC = 3 -AMD_COMGR_LANGUAGE_HIP = 4 -AMD_COMGR_LANGUAGE_LLVM_IR = 5 -AMD_COMGR_LANGUAGE_LAST = 5 -amd_comgr_language_s = ctypes.c_uint32 # enum amd_comgr_language_t = amd_comgr_language_s -amd_comgr_language_t__enumvalues = amd_comgr_language_s__enumvalues -try: - amd_comgr_status_string = _libraries['libamd_comgr.so'].amd_comgr_status_string - amd_comgr_status_string.restype = amd_comgr_status_t - amd_comgr_status_string.argtypes = [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_version = _libraries['libamd_comgr.so'].amd_comgr_get_version - amd_comgr_get_version.restype = None - amd_comgr_get_version.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass +# amd_comgr_status_t amd_comgr_status_string(amd_comgr_status_t status, const char **status_string) +try: (amd_comgr_status_string:=dll.amd_comgr_status_string).restype, amd_comgr_status_string.argtypes = amd_comgr_status_t, [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass -# values for enumeration 'amd_comgr_data_kind_s' -amd_comgr_data_kind_s__enumvalues = { - 0: 'AMD_COMGR_DATA_KIND_UNDEF', - 1: 'AMD_COMGR_DATA_KIND_SOURCE', - 2: 'AMD_COMGR_DATA_KIND_INCLUDE', - 3: 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 4: 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 5: 'AMD_COMGR_DATA_KIND_LOG', - 6: 'AMD_COMGR_DATA_KIND_BC', - 7: 'AMD_COMGR_DATA_KIND_RELOCATABLE', - 8: 'AMD_COMGR_DATA_KIND_EXECUTABLE', - 9: 'AMD_COMGR_DATA_KIND_BYTES', - 16: 'AMD_COMGR_DATA_KIND_FATBIN', - 17: 'AMD_COMGR_DATA_KIND_AR', - 18: 'AMD_COMGR_DATA_KIND_BC_BUNDLE', - 19: 'AMD_COMGR_DATA_KIND_AR_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_LAST', -} -AMD_COMGR_DATA_KIND_UNDEF = 0 -AMD_COMGR_DATA_KIND_SOURCE = 1 -AMD_COMGR_DATA_KIND_INCLUDE = 2 -AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = 3 -AMD_COMGR_DATA_KIND_DIAGNOSTIC = 4 -AMD_COMGR_DATA_KIND_LOG = 5 -AMD_COMGR_DATA_KIND_BC = 6 -AMD_COMGR_DATA_KIND_RELOCATABLE = 7 -AMD_COMGR_DATA_KIND_EXECUTABLE = 8 -AMD_COMGR_DATA_KIND_BYTES = 9 -AMD_COMGR_DATA_KIND_FATBIN = 16 -AMD_COMGR_DATA_KIND_AR = 17 -AMD_COMGR_DATA_KIND_BC_BUNDLE = 18 -AMD_COMGR_DATA_KIND_AR_BUNDLE = 19 -AMD_COMGR_DATA_KIND_OBJ_BUNDLE = 20 -AMD_COMGR_DATA_KIND_LAST = 20 -amd_comgr_data_kind_s = ctypes.c_uint32 # enum -amd_comgr_data_kind_t = amd_comgr_data_kind_s -amd_comgr_data_kind_t__enumvalues = amd_comgr_data_kind_s__enumvalues -class struct_amd_comgr_data_s(Structure): - pass - -struct_amd_comgr_data_s._pack_ = 1 # source:False -struct_amd_comgr_data_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_t = struct_amd_comgr_data_s -class struct_amd_comgr_data_set_s(Structure): - pass - -struct_amd_comgr_data_set_s._pack_ = 1 # source:False -struct_amd_comgr_data_set_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_set_t = struct_amd_comgr_data_set_s -class struct_amd_comgr_action_info_s(Structure): - pass - -struct_amd_comgr_action_info_s._pack_ = 1 # source:False -struct_amd_comgr_action_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_action_info_t = struct_amd_comgr_action_info_s -class struct_amd_comgr_metadata_node_s(Structure): - pass - -struct_amd_comgr_metadata_node_s._pack_ = 1 # source:False -struct_amd_comgr_metadata_node_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_metadata_node_t = struct_amd_comgr_metadata_node_s -class struct_amd_comgr_symbol_s(Structure): - pass - -struct_amd_comgr_symbol_s._pack_ = 1 # source:False -struct_amd_comgr_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbol_t = struct_amd_comgr_symbol_s -class struct_amd_comgr_disassembly_info_s(Structure): - pass - -struct_amd_comgr_disassembly_info_s._pack_ = 1 # source:False -struct_amd_comgr_disassembly_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_disassembly_info_t = struct_amd_comgr_disassembly_info_s -class struct_amd_comgr_symbolizer_info_s(Structure): - pass - -struct_amd_comgr_symbolizer_info_s._pack_ = 1 # source:False -struct_amd_comgr_symbolizer_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbolizer_info_t = struct_amd_comgr_symbolizer_info_s -try: - amd_comgr_get_isa_count = _libraries['libamd_comgr.so'].amd_comgr_get_isa_count - amd_comgr_get_isa_count.restype = amd_comgr_status_t - amd_comgr_get_isa_count.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass size_t = ctypes.c_uint64 -try: - amd_comgr_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_isa_name - amd_comgr_get_isa_name.restype = amd_comgr_status_t - amd_comgr_get_isa_name.argtypes = [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_isa_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_isa_metadata - amd_comgr_get_isa_metadata.restype = amd_comgr_status_t - amd_comgr_get_isa_metadata.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_create_data = _libraries['libamd_comgr.so'].amd_comgr_create_data - amd_comgr_create_data.restype = amd_comgr_status_t - amd_comgr_create_data.argtypes = [amd_comgr_data_kind_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_release_data = _libraries['libamd_comgr.so'].amd_comgr_release_data - amd_comgr_release_data.restype = amd_comgr_status_t - amd_comgr_release_data.argtypes = [amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_get_data_kind = _libraries['libamd_comgr.so'].amd_comgr_get_data_kind - amd_comgr_get_data_kind.restype = amd_comgr_status_t - amd_comgr_get_data_kind.argtypes = [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_s)] -except AttributeError: - pass -try: - amd_comgr_set_data = _libraries['libamd_comgr.so'].amd_comgr_set_data - amd_comgr_set_data.restype = amd_comgr_status_t - amd_comgr_set_data.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass +# void amd_comgr_get_version(size_t *major, size_t *minor) +try: (amd_comgr_get_version:=dll.amd_comgr_get_version).restype, amd_comgr_get_version.argtypes = None, [ctypes.POINTER(size_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +amd_comgr_data_kind_s = CEnum(ctypes.c_uint32) +AMD_COMGR_DATA_KIND_UNDEF = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_UNDEF', 0) +AMD_COMGR_DATA_KIND_SOURCE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_SOURCE', 1) +AMD_COMGR_DATA_KIND_INCLUDE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_INCLUDE', 2) +AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', 3) +AMD_COMGR_DATA_KIND_DIAGNOSTIC = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_DIAGNOSTIC', 4) +AMD_COMGR_DATA_KIND_LOG = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_LOG', 5) +AMD_COMGR_DATA_KIND_BC = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_BC', 6) +AMD_COMGR_DATA_KIND_RELOCATABLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_RELOCATABLE', 7) +AMD_COMGR_DATA_KIND_EXECUTABLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_EXECUTABLE', 8) +AMD_COMGR_DATA_KIND_BYTES = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_BYTES', 9) +AMD_COMGR_DATA_KIND_FATBIN = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_FATBIN', 16) +AMD_COMGR_DATA_KIND_AR = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_AR', 17) +AMD_COMGR_DATA_KIND_BC_BUNDLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_BC_BUNDLE', 18) +AMD_COMGR_DATA_KIND_AR_BUNDLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_AR_BUNDLE', 19) +AMD_COMGR_DATA_KIND_OBJ_BUNDLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_OBJ_BUNDLE', 20) +AMD_COMGR_DATA_KIND_LAST = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_LAST', 20) + +amd_comgr_data_kind_t = amd_comgr_data_kind_s +class amd_comgr_data_s(Struct): pass uint64_t = ctypes.c_uint64 -try: - amd_comgr_set_data_from_file_slice = _libraries['libamd_comgr.so'].amd_comgr_set_data_from_file_slice - amd_comgr_set_data_from_file_slice.restype = amd_comgr_status_t - amd_comgr_set_data_from_file_slice.argtypes = [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] -except AttributeError: - pass -try: - amd_comgr_set_data_name = _libraries['libamd_comgr.so'].amd_comgr_set_data_name - amd_comgr_set_data_name.restype = amd_comgr_status_t - amd_comgr_set_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data = _libraries['libamd_comgr.so'].amd_comgr_get_data - amd_comgr_get_data.restype = amd_comgr_status_t - amd_comgr_get_data.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_name - amd_comgr_get_data_name.restype = amd_comgr_status_t - amd_comgr_get_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_isa_name - amd_comgr_get_data_isa_name.restype = amd_comgr_status_t - amd_comgr_get_data_isa_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_create_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_create_symbolizer_info - amd_comgr_create_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_create_symbolizer_info.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_symbolizer_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_symbolizer_info - amd_comgr_destroy_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_destroy_symbolizer_info.argtypes = [amd_comgr_symbolizer_info_t] -except AttributeError: - pass -try: - amd_comgr_symbolize = _libraries['libamd_comgr.so'].amd_comgr_symbolize - amd_comgr_symbolize.restype = amd_comgr_status_t - amd_comgr_symbolize.argtypes = [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_get_data_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_data_metadata - amd_comgr_get_data_metadata.restype = amd_comgr_status_t - amd_comgr_get_data_metadata.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_metadata = _libraries['libamd_comgr.so'].amd_comgr_destroy_metadata - amd_comgr_destroy_metadata.restype = amd_comgr_status_t - amd_comgr_destroy_metadata.argtypes = [amd_comgr_metadata_node_t] -except AttributeError: - pass -try: - amd_comgr_create_data_set = _libraries['libamd_comgr.so'].amd_comgr_create_data_set - amd_comgr_create_data_set.restype = amd_comgr_status_t - amd_comgr_create_data_set.argtypes = [ctypes.POINTER(struct_amd_comgr_data_set_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_data_set = _libraries['libamd_comgr.so'].amd_comgr_destroy_data_set - amd_comgr_destroy_data_set.restype = amd_comgr_status_t - amd_comgr_destroy_data_set.argtypes = [amd_comgr_data_set_t] -except AttributeError: - pass -try: - amd_comgr_data_set_add = _libraries['libamd_comgr.so'].amd_comgr_data_set_add - amd_comgr_data_set_add.restype = amd_comgr_status_t - amd_comgr_data_set_add.argtypes = [amd_comgr_data_set_t, amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_data_set_remove = _libraries['libamd_comgr.so'].amd_comgr_data_set_remove - amd_comgr_data_set_remove.restype = amd_comgr_status_t - amd_comgr_data_set_remove.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t] -except AttributeError: - pass -try: - amd_comgr_action_data_count = _libraries['libamd_comgr.so'].amd_comgr_action_data_count - amd_comgr_action_data_count.restype = amd_comgr_status_t - amd_comgr_action_data_count.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_data_get_data = _libraries['libamd_comgr.so'].amd_comgr_action_data_get_data - amd_comgr_action_data_get_data.restype = amd_comgr_status_t - amd_comgr_action_data_get_data.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_create_action_info = _libraries['libamd_comgr.so'].amd_comgr_create_action_info - amd_comgr_create_action_info.restype = amd_comgr_status_t - amd_comgr_create_action_info.argtypes = [ctypes.POINTER(struct_amd_comgr_action_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_action_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_action_info - amd_comgr_destroy_action_info.restype = amd_comgr_status_t - amd_comgr_destroy_action_info.argtypes = [amd_comgr_action_info_t] -except AttributeError: - pass -try: - amd_comgr_action_info_set_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_isa_name - amd_comgr_action_info_set_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_set_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_isa_name - amd_comgr_action_info_get_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_get_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_language - amd_comgr_action_info_set_language.restype = amd_comgr_status_t - amd_comgr_action_info_set_language.argtypes = [amd_comgr_action_info_t, amd_comgr_language_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_language - amd_comgr_action_info_get_language.restype = amd_comgr_status_t - amd_comgr_action_info_get_language.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_s)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_options = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_options - amd_comgr_action_info_set_options.restype = amd_comgr_status_t - amd_comgr_action_info_set_options.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_options = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_options - amd_comgr_action_info_get_options.restype = amd_comgr_status_t - amd_comgr_action_info_get_options.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_option_list = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_option_list - amd_comgr_action_info_set_option_list.restype = amd_comgr_status_t - amd_comgr_action_info_set_option_list.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_count - amd_comgr_action_info_get_option_list_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_item = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_item - amd_comgr_action_info_get_option_list_item.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_item.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_bundle_entry_ids = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_bundle_entry_ids - amd_comgr_action_info_set_bundle_entry_ids.restype = amd_comgr_status_t - amd_comgr_action_info_set_bundle_entry_ids.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id_count - amd_comgr_action_info_get_bundle_entry_id_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id - amd_comgr_action_info_get_bundle_entry_id.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_working_directory_path - amd_comgr_action_info_set_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_set_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_working_directory_path - amd_comgr_action_info_get_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_get_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_logging - amd_comgr_action_info_set_logging.restype = amd_comgr_status_t - amd_comgr_action_info_set_logging.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_get_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_logging - amd_comgr_action_info_get_logging.restype = amd_comgr_status_t - amd_comgr_action_info_get_logging.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_action_kind_s' -amd_comgr_action_kind_s__enumvalues = { - 0: 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 1: 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 2: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 3: 'AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES', - 4: 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 5: 'AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC', - 6: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 7: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 8: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 9: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 10: 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 11: 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 12: 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 13: 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 14: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN', - 15: 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 16: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 17: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 18: 'AMD_COMGR_ACTION_UNBUNDLE', - 18: 'AMD_COMGR_ACTION_LAST', -} -AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = 0 -AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = 1 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = 2 -AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES = 3 -AMD_COMGR_ACTION_LINK_BC_TO_BC = 4 -AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC = 5 -AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = 6 -AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = 7 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = 8 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = 9 -AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = 10 -AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = 11 -AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = 12 -AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = 13 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN = 14 -AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = 15 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = 16 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = 17 -AMD_COMGR_ACTION_UNBUNDLE = 18 -AMD_COMGR_ACTION_LAST = 18 -amd_comgr_action_kind_s = ctypes.c_uint32 # enum -amd_comgr_action_kind_t = amd_comgr_action_kind_s -amd_comgr_action_kind_t__enumvalues = amd_comgr_action_kind_s__enumvalues -try: - amd_comgr_do_action = _libraries['libamd_comgr.so'].amd_comgr_do_action - amd_comgr_do_action.restype = amd_comgr_status_t - amd_comgr_do_action.argtypes = [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_metadata_kind_s' -amd_comgr_metadata_kind_s__enumvalues = { - 0: 'AMD_COMGR_METADATA_KIND_NULL', - 1: 'AMD_COMGR_METADATA_KIND_STRING', - 2: 'AMD_COMGR_METADATA_KIND_MAP', - 3: 'AMD_COMGR_METADATA_KIND_LIST', - 3: 'AMD_COMGR_METADATA_KIND_LAST', -} -AMD_COMGR_METADATA_KIND_NULL = 0 -AMD_COMGR_METADATA_KIND_STRING = 1 -AMD_COMGR_METADATA_KIND_MAP = 2 -AMD_COMGR_METADATA_KIND_LIST = 3 -AMD_COMGR_METADATA_KIND_LAST = 3 -amd_comgr_metadata_kind_s = ctypes.c_uint32 # enum -amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s -amd_comgr_metadata_kind_t__enumvalues = amd_comgr_metadata_kind_s__enumvalues -try: - amd_comgr_get_metadata_kind = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_kind - amd_comgr_get_metadata_kind.restype = amd_comgr_status_t - amd_comgr_get_metadata_kind.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_string = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_string - amd_comgr_get_metadata_string.restype = amd_comgr_status_t - amd_comgr_get_metadata_string.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_map_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_map_size - amd_comgr_get_metadata_map_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_map_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_iterate_map_metadata = _libraries['libamd_comgr.so'].amd_comgr_iterate_map_metadata - amd_comgr_iterate_map_metadata.restype = amd_comgr_status_t - amd_comgr_iterate_map_metadata.argtypes = [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_metadata_node_s, struct_amd_comgr_metadata_node_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_metadata_lookup = _libraries['libamd_comgr.so'].amd_comgr_metadata_lookup - amd_comgr_metadata_lookup.restype = amd_comgr_status_t - amd_comgr_metadata_lookup.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_list_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_list_size - amd_comgr_get_metadata_list_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_list_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_index_list_metadata = _libraries['libamd_comgr.so'].amd_comgr_index_list_metadata - amd_comgr_index_list_metadata.restype = amd_comgr_status_t - amd_comgr_index_list_metadata.argtypes = [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_iterate_symbols = _libraries['libamd_comgr.so'].amd_comgr_iterate_symbols - amd_comgr_iterate_symbols.restype = amd_comgr_status_t - amd_comgr_iterate_symbols.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_symbol_lookup = _libraries['libamd_comgr.so'].amd_comgr_symbol_lookup - amd_comgr_symbol_lookup.restype = amd_comgr_status_t - amd_comgr_symbol_lookup.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_symbol_type_s' -amd_comgr_symbol_type_s__enumvalues = { - -1: 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', - 0: 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 1: 'AMD_COMGR_SYMBOL_TYPE_OBJECT', - 2: 'AMD_COMGR_SYMBOL_TYPE_FUNC', - 3: 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 4: 'AMD_COMGR_SYMBOL_TYPE_FILE', - 5: 'AMD_COMGR_SYMBOL_TYPE_COMMON', - 10: 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', -} -AMD_COMGR_SYMBOL_TYPE_UNKNOWN = -1 -AMD_COMGR_SYMBOL_TYPE_NOTYPE = 0 -AMD_COMGR_SYMBOL_TYPE_OBJECT = 1 -AMD_COMGR_SYMBOL_TYPE_FUNC = 2 -AMD_COMGR_SYMBOL_TYPE_SECTION = 3 -AMD_COMGR_SYMBOL_TYPE_FILE = 4 -AMD_COMGR_SYMBOL_TYPE_COMMON = 5 -AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = 10 -amd_comgr_symbol_type_s = ctypes.c_int32 # enum -amd_comgr_symbol_type_t = amd_comgr_symbol_type_s -amd_comgr_symbol_type_t__enumvalues = amd_comgr_symbol_type_s__enumvalues - -# values for enumeration 'amd_comgr_symbol_info_s' -amd_comgr_symbol_info_s__enumvalues = { - 0: 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', - 1: 'AMD_COMGR_SYMBOL_INFO_NAME', - 2: 'AMD_COMGR_SYMBOL_INFO_TYPE', - 3: 'AMD_COMGR_SYMBOL_INFO_SIZE', - 4: 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 5: 'AMD_COMGR_SYMBOL_INFO_VALUE', - 5: 'AMD_COMGR_SYMBOL_INFO_LAST', -} -AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = 0 -AMD_COMGR_SYMBOL_INFO_NAME = 1 -AMD_COMGR_SYMBOL_INFO_TYPE = 2 -AMD_COMGR_SYMBOL_INFO_SIZE = 3 -AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = 4 -AMD_COMGR_SYMBOL_INFO_VALUE = 5 -AMD_COMGR_SYMBOL_INFO_LAST = 5 -amd_comgr_symbol_info_s = ctypes.c_uint32 # enum -amd_comgr_symbol_info_t = amd_comgr_symbol_info_s -amd_comgr_symbol_info_t__enumvalues = amd_comgr_symbol_info_s__enumvalues -try: - amd_comgr_symbol_get_info = _libraries['libamd_comgr.so'].amd_comgr_symbol_get_info - amd_comgr_symbol_get_info.restype = amd_comgr_status_t - amd_comgr_symbol_get_info.argtypes = [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_create_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_create_disassembly_info - amd_comgr_create_disassembly_info.restype = amd_comgr_status_t - amd_comgr_create_disassembly_info.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(ctypes.c_char), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_disassembly_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_disassembly_info - amd_comgr_destroy_disassembly_info.restype = amd_comgr_status_t - amd_comgr_destroy_disassembly_info.argtypes = [amd_comgr_disassembly_info_t] -except AttributeError: - pass -try: - amd_comgr_disassemble_instruction = _libraries['libamd_comgr.so'].amd_comgr_disassemble_instruction - amd_comgr_disassemble_instruction.restype = amd_comgr_status_t - amd_comgr_disassemble_instruction.argtypes = [amd_comgr_disassembly_info_t, uint64_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_demangle_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_demangle_symbol_name - amd_comgr_demangle_symbol_name.restype = amd_comgr_status_t - amd_comgr_demangle_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_populate_mangled_names = _libraries['libamd_comgr.so'].amd_comgr_populate_mangled_names - amd_comgr_populate_mangled_names.restype = amd_comgr_status_t - amd_comgr_populate_mangled_names.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_get_mangled_name = _libraries['libamd_comgr.so'].amd_comgr_get_mangled_name - amd_comgr_get_mangled_name.restype = amd_comgr_status_t - amd_comgr_get_mangled_name.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_populate_name_expression_map = _libraries['libamd_comgr.so'].amd_comgr_populate_name_expression_map - amd_comgr_populate_name_expression_map.restype = amd_comgr_status_t - amd_comgr_populate_name_expression_map.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_map_name_expression_to_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_map_name_expression_to_symbol_name - amd_comgr_map_name_expression_to_symbol_name.restype = amd_comgr_status_t - amd_comgr_map_name_expression_to_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_code_object_info_s(Structure): - pass - -struct_code_object_info_s._pack_ = 1 # source:False -struct_code_object_info_s._fields_ = [ - ('isa', ctypes.POINTER(ctypes.c_char)), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), +amd_comgr_data_s._fields_ = [ + ('handle', uint64_t), ] +amd_comgr_data_t = amd_comgr_data_s +class amd_comgr_data_set_s(Struct): pass +amd_comgr_data_set_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_data_set_t = amd_comgr_data_set_s +class amd_comgr_action_info_s(Struct): pass +amd_comgr_action_info_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_action_info_t = amd_comgr_action_info_s +class amd_comgr_metadata_node_s(Struct): pass +amd_comgr_metadata_node_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_metadata_node_t = amd_comgr_metadata_node_s +class amd_comgr_symbol_s(Struct): pass +amd_comgr_symbol_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_symbol_t = amd_comgr_symbol_s +class amd_comgr_disassembly_info_s(Struct): pass +amd_comgr_disassembly_info_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_disassembly_info_t = amd_comgr_disassembly_info_s +class amd_comgr_symbolizer_info_s(Struct): pass +amd_comgr_symbolizer_info_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_symbolizer_info_t = amd_comgr_symbolizer_info_s +# amd_comgr_status_t amd_comgr_get_isa_count(size_t *count) +try: (amd_comgr_get_isa_count:=dll.amd_comgr_get_isa_count).restype, amd_comgr_get_isa_count.argtypes = amd_comgr_status_t, [ctypes.POINTER(size_t)] +except AttributeError: pass -amd_comgr_code_object_info_t = struct_code_object_info_s -try: - amd_comgr_lookup_code_object = _libraries['libamd_comgr.so'].amd_comgr_lookup_code_object - amd_comgr_lookup_code_object.restype = amd_comgr_status_t - amd_comgr_lookup_code_object.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_code_object_info_s), size_t] -except AttributeError: - pass -try: - amd_comgr_map_elf_virtual_address_to_code_object_offset = _libraries['libamd_comgr.so'].amd_comgr_map_elf_virtual_address_to_code_object_offset - amd_comgr_map_elf_virtual_address_to_code_object_offset.restype = amd_comgr_status_t - amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = [amd_comgr_data_t, uint64_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -__all__ = \ - ['AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES', - 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_LAST', 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC', - 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 'AMD_COMGR_ACTION_UNBUNDLE', 'AMD_COMGR_DATA_KIND_AR', - 'AMD_COMGR_DATA_KIND_AR_BUNDLE', 'AMD_COMGR_DATA_KIND_BC', - 'AMD_COMGR_DATA_KIND_BC_BUNDLE', 'AMD_COMGR_DATA_KIND_BYTES', - 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 'AMD_COMGR_DATA_KIND_EXECUTABLE', 'AMD_COMGR_DATA_KIND_FATBIN', - 'AMD_COMGR_DATA_KIND_INCLUDE', 'AMD_COMGR_DATA_KIND_LAST', - 'AMD_COMGR_DATA_KIND_LOG', 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 'AMD_COMGR_DATA_KIND_RELOCATABLE', 'AMD_COMGR_DATA_KIND_SOURCE', - 'AMD_COMGR_DATA_KIND_UNDEF', 'AMD_COMGR_LANGUAGE_HC', - 'AMD_COMGR_LANGUAGE_HIP', 'AMD_COMGR_LANGUAGE_LAST', - 'AMD_COMGR_LANGUAGE_LLVM_IR', 'AMD_COMGR_LANGUAGE_NONE', - 'AMD_COMGR_LANGUAGE_OPENCL_1_2', 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 'AMD_COMGR_METADATA_KIND_LAST', 'AMD_COMGR_METADATA_KIND_LIST', - 'AMD_COMGR_METADATA_KIND_MAP', 'AMD_COMGR_METADATA_KIND_NULL', - 'AMD_COMGR_METADATA_KIND_STRING', 'AMD_COMGR_STATUS_ERROR', - 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', - 'AMD_COMGR_STATUS_SUCCESS', 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 'AMD_COMGR_SYMBOL_INFO_LAST', 'AMD_COMGR_SYMBOL_INFO_NAME', - 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 'AMD_COMGR_SYMBOL_INFO_SIZE', - 'AMD_COMGR_SYMBOL_INFO_TYPE', 'AMD_COMGR_SYMBOL_INFO_VALUE', - 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', - 'AMD_COMGR_SYMBOL_TYPE_COMMON', 'AMD_COMGR_SYMBOL_TYPE_FILE', - 'AMD_COMGR_SYMBOL_TYPE_FUNC', 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 'AMD_COMGR_SYMBOL_TYPE_OBJECT', 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', 'amd_comgr_action_data_count', - 'amd_comgr_action_data_get_data', - 'amd_comgr_action_info_get_bundle_entry_id', - 'amd_comgr_action_info_get_bundle_entry_id_count', - 'amd_comgr_action_info_get_isa_name', - 'amd_comgr_action_info_get_language', - 'amd_comgr_action_info_get_logging', - 'amd_comgr_action_info_get_option_list_count', - 'amd_comgr_action_info_get_option_list_item', - 'amd_comgr_action_info_get_options', - 'amd_comgr_action_info_get_working_directory_path', - 'amd_comgr_action_info_set_bundle_entry_ids', - 'amd_comgr_action_info_set_isa_name', - 'amd_comgr_action_info_set_language', - 'amd_comgr_action_info_set_logging', - 'amd_comgr_action_info_set_option_list', - 'amd_comgr_action_info_set_options', - 'amd_comgr_action_info_set_working_directory_path', - 'amd_comgr_action_info_t', 'amd_comgr_action_kind_s', - 'amd_comgr_action_kind_t', 'amd_comgr_action_kind_t__enumvalues', - 'amd_comgr_code_object_info_t', 'amd_comgr_create_action_info', - 'amd_comgr_create_data', 'amd_comgr_create_data_set', - 'amd_comgr_create_disassembly_info', - 'amd_comgr_create_symbolizer_info', 'amd_comgr_data_kind_s', - 'amd_comgr_data_kind_t', 'amd_comgr_data_kind_t__enumvalues', - 'amd_comgr_data_set_add', 'amd_comgr_data_set_remove', - 'amd_comgr_data_set_t', 'amd_comgr_data_t', - 'amd_comgr_demangle_symbol_name', 'amd_comgr_destroy_action_info', - 'amd_comgr_destroy_data_set', - 'amd_comgr_destroy_disassembly_info', - 'amd_comgr_destroy_metadata', 'amd_comgr_destroy_symbolizer_info', - 'amd_comgr_disassemble_instruction', - 'amd_comgr_disassembly_info_t', 'amd_comgr_do_action', - 'amd_comgr_get_data', 'amd_comgr_get_data_isa_name', - 'amd_comgr_get_data_kind', 'amd_comgr_get_data_metadata', - 'amd_comgr_get_data_name', 'amd_comgr_get_isa_count', - 'amd_comgr_get_isa_metadata', 'amd_comgr_get_isa_name', - 'amd_comgr_get_mangled_name', 'amd_comgr_get_metadata_kind', - 'amd_comgr_get_metadata_list_size', - 'amd_comgr_get_metadata_map_size', - 'amd_comgr_get_metadata_string', 'amd_comgr_get_version', - 'amd_comgr_index_list_metadata', 'amd_comgr_iterate_map_metadata', - 'amd_comgr_iterate_symbols', 'amd_comgr_language_s', - 'amd_comgr_language_t', 'amd_comgr_language_t__enumvalues', - 'amd_comgr_lookup_code_object', - 'amd_comgr_map_elf_virtual_address_to_code_object_offset', - 'amd_comgr_map_name_expression_to_symbol_name', - 'amd_comgr_metadata_kind_s', 'amd_comgr_metadata_kind_t', - 'amd_comgr_metadata_kind_t__enumvalues', - 'amd_comgr_metadata_lookup', 'amd_comgr_metadata_node_t', - 'amd_comgr_populate_mangled_names', - 'amd_comgr_populate_name_expression_map', - 'amd_comgr_release_data', 'amd_comgr_set_data', - 'amd_comgr_set_data_from_file_slice', 'amd_comgr_set_data_name', - 'amd_comgr_status_s', 'amd_comgr_status_string', - 'amd_comgr_status_t', 'amd_comgr_status_t__enumvalues', - 'amd_comgr_symbol_get_info', 'amd_comgr_symbol_info_s', - 'amd_comgr_symbol_info_t', 'amd_comgr_symbol_info_t__enumvalues', - 'amd_comgr_symbol_lookup', 'amd_comgr_symbol_t', - 'amd_comgr_symbol_type_s', 'amd_comgr_symbol_type_t', - 'amd_comgr_symbol_type_t__enumvalues', 'amd_comgr_symbolize', - 'amd_comgr_symbolizer_info_t', 'size_t', - 'struct_amd_comgr_action_info_s', 'struct_amd_comgr_data_s', - 'struct_amd_comgr_data_set_s', - 'struct_amd_comgr_disassembly_info_s', - 'struct_amd_comgr_metadata_node_s', 'struct_amd_comgr_symbol_s', - 'struct_amd_comgr_symbolizer_info_s', 'struct_code_object_info_s', - 'uint64_t'] +# amd_comgr_status_t amd_comgr_get_isa_name(size_t index, const char **isa_name) +try: (amd_comgr_get_isa_name:=dll.amd_comgr_get_isa_name).restype, amd_comgr_get_isa_name.argtypes = amd_comgr_status_t, [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_isa_metadata(const char *isa_name, amd_comgr_metadata_node_t *metadata) +try: (amd_comgr_get_isa_metadata:=dll.amd_comgr_get_isa_metadata).restype, amd_comgr_get_isa_metadata.argtypes = amd_comgr_status_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_data(amd_comgr_data_kind_t kind, amd_comgr_data_t *data) +try: (amd_comgr_create_data:=dll.amd_comgr_create_data).restype, amd_comgr_create_data.argtypes = amd_comgr_status_t, [amd_comgr_data_kind_t, ctypes.POINTER(amd_comgr_data_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_release_data(amd_comgr_data_t data) +try: (amd_comgr_release_data:=dll.amd_comgr_release_data).restype, amd_comgr_release_data.argtypes = amd_comgr_status_t, [amd_comgr_data_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_kind(amd_comgr_data_t data, amd_comgr_data_kind_t *kind) +try: (amd_comgr_get_data_kind:=dll.amd_comgr_get_data_kind).restype, amd_comgr_get_data_kind.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_set_data(amd_comgr_data_t data, size_t size, const char *bytes) +try: (amd_comgr_set_data:=dll.amd_comgr_set_data).restype, amd_comgr_set_data.argtypes = amd_comgr_status_t, [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_set_data_from_file_slice(amd_comgr_data_t data, int file_descriptor, uint64_t offset, uint64_t size) +try: (amd_comgr_set_data_from_file_slice:=dll.amd_comgr_set_data_from_file_slice).restype, amd_comgr_set_data_from_file_slice.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_set_data_name(amd_comgr_data_t data, const char *name) +try: (amd_comgr_set_data_name:=dll.amd_comgr_set_data_name).restype, amd_comgr_set_data_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data(amd_comgr_data_t data, size_t *size, char *bytes) +try: (amd_comgr_get_data:=dll.amd_comgr_get_data).restype, amd_comgr_get_data.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_name(amd_comgr_data_t data, size_t *size, char *name) +try: (amd_comgr_get_data_name:=dll.amd_comgr_get_data_name).restype, amd_comgr_get_data_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_isa_name(amd_comgr_data_t data, size_t *size, char *isa_name) +try: (amd_comgr_get_data_isa_name:=dll.amd_comgr_get_data_isa_name).restype, amd_comgr_get_data_isa_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_symbolizer_info(amd_comgr_data_t code_object, void (*print_symbol_callback)(const char *, void *), amd_comgr_symbolizer_info_t *symbolizer_info) +try: (amd_comgr_create_symbolizer_info:=dll.amd_comgr_create_symbolizer_info).restype, amd_comgr_create_symbolizer_info.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p), ctypes.POINTER(amd_comgr_symbolizer_info_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_symbolizer_info(amd_comgr_symbolizer_info_t symbolizer_info) +try: (amd_comgr_destroy_symbolizer_info:=dll.amd_comgr_destroy_symbolizer_info).restype, amd_comgr_destroy_symbolizer_info.argtypes = amd_comgr_status_t, [amd_comgr_symbolizer_info_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_symbolize(amd_comgr_symbolizer_info_t symbolizer_info, uint64_t address, bool is_code, void *user_data) +try: (amd_comgr_symbolize:=dll.amd_comgr_symbolize).restype, amd_comgr_symbolize.argtypes = amd_comgr_status_t, [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_metadata(amd_comgr_data_t data, amd_comgr_metadata_node_t *metadata) +try: (amd_comgr_get_data_metadata:=dll.amd_comgr_get_data_metadata).restype, amd_comgr_get_data_metadata.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_metadata(amd_comgr_metadata_node_t metadata) +try: (amd_comgr_destroy_metadata:=dll.amd_comgr_destroy_metadata).restype, amd_comgr_destroy_metadata.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_data_set(amd_comgr_data_set_t *data_set) +try: (amd_comgr_create_data_set:=dll.amd_comgr_create_data_set).restype, amd_comgr_create_data_set.argtypes = amd_comgr_status_t, [ctypes.POINTER(amd_comgr_data_set_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_data_set(amd_comgr_data_set_t data_set) +try: (amd_comgr_destroy_data_set:=dll.amd_comgr_destroy_data_set).restype, amd_comgr_destroy_data_set.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_data_set_add(amd_comgr_data_set_t data_set, amd_comgr_data_t data) +try: (amd_comgr_data_set_add:=dll.amd_comgr_data_set_add).restype, amd_comgr_data_set_add.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_data_set_remove(amd_comgr_data_set_t data_set, amd_comgr_data_kind_t data_kind) +try: (amd_comgr_data_set_remove:=dll.amd_comgr_data_set_remove).restype, amd_comgr_data_set_remove.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_kind_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_data_count(amd_comgr_data_set_t data_set, amd_comgr_data_kind_t data_kind, size_t *count) +try: (amd_comgr_action_data_count:=dll.amd_comgr_action_data_count).restype, amd_comgr_action_data_count.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_data_get_data(amd_comgr_data_set_t data_set, amd_comgr_data_kind_t data_kind, size_t index, amd_comgr_data_t *data) +try: (amd_comgr_action_data_get_data:=dll.amd_comgr_action_data_get_data).restype, amd_comgr_action_data_get_data.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(amd_comgr_data_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_action_info(amd_comgr_action_info_t *action_info) +try: (amd_comgr_create_action_info:=dll.amd_comgr_create_action_info).restype, amd_comgr_create_action_info.argtypes = amd_comgr_status_t, [ctypes.POINTER(amd_comgr_action_info_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_action_info(amd_comgr_action_info_t action_info) +try: (amd_comgr_destroy_action_info:=dll.amd_comgr_destroy_action_info).restype, amd_comgr_destroy_action_info.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_isa_name(amd_comgr_action_info_t action_info, const char *isa_name) +try: (amd_comgr_action_info_set_isa_name:=dll.amd_comgr_action_info_set_isa_name).restype, amd_comgr_action_info_set_isa_name.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_isa_name(amd_comgr_action_info_t action_info, size_t *size, char *isa_name) +try: (amd_comgr_action_info_get_isa_name:=dll.amd_comgr_action_info_get_isa_name).restype, amd_comgr_action_info_get_isa_name.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_language(amd_comgr_action_info_t action_info, amd_comgr_language_t language) +try: (amd_comgr_action_info_set_language:=dll.amd_comgr_action_info_set_language).restype, amd_comgr_action_info_set_language.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, amd_comgr_language_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_language(amd_comgr_action_info_t action_info, amd_comgr_language_t *language) +try: (amd_comgr_action_info_get_language:=dll.amd_comgr_action_info_get_language).restype, amd_comgr_action_info_get_language.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_t)] +except AttributeError: pass + +# __attribute__((deprecated("Will be removed in Comgr v3.0 (Rocm v6.0). Use amd_comgr_action_info_set_option_list() instead"))) amd_comgr_status_t amd_comgr_action_info_set_options(amd_comgr_action_info_t action_info, const char *options) +try: (amd_comgr_action_info_set_options:=dll.amd_comgr_action_info_set_options).restype, amd_comgr_action_info_set_options.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# __attribute__((deprecated("Will be removed in Comgr v3.0 (Rocm v6.0). Use amd_comgr_action_info_get_option_list_count() and amd_comgr_action_info_get_option_list_item() instead"))) amd_comgr_status_t amd_comgr_action_info_get_options(amd_comgr_action_info_t action_info, size_t *size, char *options) +try: (amd_comgr_action_info_get_options:=dll.amd_comgr_action_info_get_options).restype, amd_comgr_action_info_get_options.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_option_list(amd_comgr_action_info_t action_info, const char *options[], size_t count) +try: (amd_comgr_action_info_set_option_list:=dll.amd_comgr_action_info_set_option_list).restype, amd_comgr_action_info_set_option_list.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, (ctypes.POINTER(ctypes.c_char) * 0), size_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_option_list_count(amd_comgr_action_info_t action_info, size_t *count) +try: (amd_comgr_action_info_get_option_list_count:=dll.amd_comgr_action_info_get_option_list_count).restype, amd_comgr_action_info_get_option_list_count.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_option_list_item(amd_comgr_action_info_t action_info, size_t index, size_t *size, char *option) +try: (amd_comgr_action_info_get_option_list_item:=dll.amd_comgr_action_info_get_option_list_item).restype, amd_comgr_action_info_get_option_list_item.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, size_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_bundle_entry_ids(amd_comgr_action_info_t action_info, const char *bundle_entry_ids[], size_t count) +try: (amd_comgr_action_info_set_bundle_entry_ids:=dll.amd_comgr_action_info_set_bundle_entry_ids).restype, amd_comgr_action_info_set_bundle_entry_ids.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, (ctypes.POINTER(ctypes.c_char) * 0), size_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_bundle_entry_id_count(amd_comgr_action_info_t action_info, size_t *count) +try: (amd_comgr_action_info_get_bundle_entry_id_count:=dll.amd_comgr_action_info_get_bundle_entry_id_count).restype, amd_comgr_action_info_get_bundle_entry_id_count.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_bundle_entry_id(amd_comgr_action_info_t action_info, size_t index, size_t *size, char *bundle_entry_id) +try: (amd_comgr_action_info_get_bundle_entry_id:=dll.amd_comgr_action_info_get_bundle_entry_id).restype, amd_comgr_action_info_get_bundle_entry_id.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, size_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_working_directory_path(amd_comgr_action_info_t action_info, const char *path) +try: (amd_comgr_action_info_set_working_directory_path:=dll.amd_comgr_action_info_set_working_directory_path).restype, amd_comgr_action_info_set_working_directory_path.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_working_directory_path(amd_comgr_action_info_t action_info, size_t *size, char *path) +try: (amd_comgr_action_info_get_working_directory_path:=dll.amd_comgr_action_info_get_working_directory_path).restype, amd_comgr_action_info_get_working_directory_path.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_logging(amd_comgr_action_info_t action_info, bool logging) +try: (amd_comgr_action_info_set_logging:=dll.amd_comgr_action_info_set_logging).restype, amd_comgr_action_info_set_logging.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.c_bool] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_logging(amd_comgr_action_info_t action_info, bool *logging) +try: (amd_comgr_action_info_get_logging:=dll.amd_comgr_action_info_get_logging).restype, amd_comgr_action_info_get_logging.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +amd_comgr_action_kind_s = CEnum(ctypes.c_uint32) +AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', 0) +AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', 1) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', 2) +AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_ADD_DEVICE_LIBRARIES', 3) +AMD_COMGR_ACTION_LINK_BC_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LINK_BC_TO_BC', 4) +AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_OPTIMIZE_BC_TO_BC', 5) +AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', 6) +AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', 7) +AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', 8) +AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', 9) +AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', 10) +AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', 11) +AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', 12) +AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', 13) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_FATBIN', 14) +AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', 15) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', 16) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', 17) +AMD_COMGR_ACTION_UNBUNDLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_UNBUNDLE', 18) +AMD_COMGR_ACTION_LAST = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LAST', 18) + +amd_comgr_action_kind_t = amd_comgr_action_kind_s +# amd_comgr_status_t amd_comgr_do_action(amd_comgr_action_kind_t kind, amd_comgr_action_info_t info, amd_comgr_data_set_t input, amd_comgr_data_set_t result) +try: (amd_comgr_do_action:=dll.amd_comgr_do_action).restype, amd_comgr_do_action.argtypes = amd_comgr_status_t, [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] +except AttributeError: pass + +amd_comgr_metadata_kind_s = CEnum(ctypes.c_uint32) +AMD_COMGR_METADATA_KIND_NULL = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_NULL', 0) +AMD_COMGR_METADATA_KIND_STRING = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_STRING', 1) +AMD_COMGR_METADATA_KIND_MAP = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_MAP', 2) +AMD_COMGR_METADATA_KIND_LIST = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_LIST', 3) +AMD_COMGR_METADATA_KIND_LAST = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_LAST', 3) + +amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s +# amd_comgr_status_t amd_comgr_get_metadata_kind(amd_comgr_metadata_node_t metadata, amd_comgr_metadata_kind_t *kind) +try: (amd_comgr_get_metadata_kind:=dll.amd_comgr_get_metadata_kind).restype, amd_comgr_get_metadata_kind.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_metadata_string(amd_comgr_metadata_node_t metadata, size_t *size, char *string) +try: (amd_comgr_get_metadata_string:=dll.amd_comgr_get_metadata_string).restype, amd_comgr_get_metadata_string.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_metadata_map_size(amd_comgr_metadata_node_t metadata, size_t *size) +try: (amd_comgr_get_metadata_map_size:=dll.amd_comgr_get_metadata_map_size).restype, amd_comgr_get_metadata_map_size.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_iterate_map_metadata(amd_comgr_metadata_node_t metadata, amd_comgr_status_t (*callback)(amd_comgr_metadata_node_t, amd_comgr_metadata_node_t, void *), void *user_data) +try: (amd_comgr_iterate_map_metadata:=dll.amd_comgr_iterate_map_metadata).restype, amd_comgr_iterate_map_metadata.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_t, amd_comgr_metadata_node_t, amd_comgr_metadata_node_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_metadata_lookup(amd_comgr_metadata_node_t metadata, const char *key, amd_comgr_metadata_node_t *value) +try: (amd_comgr_metadata_lookup:=dll.amd_comgr_metadata_lookup).restype, amd_comgr_metadata_lookup.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_metadata_list_size(amd_comgr_metadata_node_t metadata, size_t *size) +try: (amd_comgr_get_metadata_list_size:=dll.amd_comgr_get_metadata_list_size).restype, amd_comgr_get_metadata_list_size.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_index_list_metadata(amd_comgr_metadata_node_t metadata, size_t index, amd_comgr_metadata_node_t *value) +try: (amd_comgr_index_list_metadata:=dll.amd_comgr_index_list_metadata).restype, amd_comgr_index_list_metadata.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_iterate_symbols(amd_comgr_data_t data, amd_comgr_status_t (*callback)(amd_comgr_symbol_t, void *), void *user_data) +try: (amd_comgr_iterate_symbols:=dll.amd_comgr_iterate_symbols).restype, amd_comgr_iterate_symbols.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_t, amd_comgr_symbol_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_symbol_lookup(amd_comgr_data_t data, const char *name, amd_comgr_symbol_t *symbol) +try: (amd_comgr_symbol_lookup:=dll.amd_comgr_symbol_lookup).restype, amd_comgr_symbol_lookup.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(amd_comgr_symbol_t)] +except AttributeError: pass + +amd_comgr_symbol_type_s = CEnum(ctypes.c_int32) +AMD_COMGR_SYMBOL_TYPE_UNKNOWN = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_UNKNOWN', -1) +AMD_COMGR_SYMBOL_TYPE_NOTYPE = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_NOTYPE', 0) +AMD_COMGR_SYMBOL_TYPE_OBJECT = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_OBJECT', 1) +AMD_COMGR_SYMBOL_TYPE_FUNC = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_FUNC', 2) +AMD_COMGR_SYMBOL_TYPE_SECTION = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_SECTION', 3) +AMD_COMGR_SYMBOL_TYPE_FILE = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_FILE', 4) +AMD_COMGR_SYMBOL_TYPE_COMMON = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_COMMON', 5) +AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', 10) + +amd_comgr_symbol_type_t = amd_comgr_symbol_type_s +amd_comgr_symbol_info_s = CEnum(ctypes.c_uint32) +AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 0) +AMD_COMGR_SYMBOL_INFO_NAME = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_NAME', 1) +AMD_COMGR_SYMBOL_INFO_TYPE = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_TYPE', 2) +AMD_COMGR_SYMBOL_INFO_SIZE = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_SIZE', 3) +AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', 4) +AMD_COMGR_SYMBOL_INFO_VALUE = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_VALUE', 5) +AMD_COMGR_SYMBOL_INFO_LAST = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_LAST', 5) + +amd_comgr_symbol_info_t = amd_comgr_symbol_info_s +# amd_comgr_status_t amd_comgr_symbol_get_info(amd_comgr_symbol_t symbol, amd_comgr_symbol_info_t attribute, void *value) +try: (amd_comgr_symbol_get_info:=dll.amd_comgr_symbol_get_info).restype, amd_comgr_symbol_get_info.argtypes = amd_comgr_status_t, [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_disassembly_info(const char *isa_name, uint64_t (*read_memory_callback)(uint64_t, char *, uint64_t, void *), void (*print_instruction_callback)(const char *, void *), void (*print_address_annotation_callback)(uint64_t, void *), amd_comgr_disassembly_info_t *disassembly_info) +try: (amd_comgr_create_disassembly_info:=dll.amd_comgr_create_disassembly_info).restype, amd_comgr_create_disassembly_info.argtypes = amd_comgr_status_t, [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(uint64_t, uint64_t, ctypes.POINTER(ctypes.c_char), uint64_t, ctypes.c_void_p), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p), ctypes.CFUNCTYPE(None, uint64_t, ctypes.c_void_p), ctypes.POINTER(amd_comgr_disassembly_info_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_disassembly_info(amd_comgr_disassembly_info_t disassembly_info) +try: (amd_comgr_destroy_disassembly_info:=dll.amd_comgr_destroy_disassembly_info).restype, amd_comgr_destroy_disassembly_info.argtypes = amd_comgr_status_t, [amd_comgr_disassembly_info_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_disassemble_instruction(amd_comgr_disassembly_info_t disassembly_info, uint64_t address, void *user_data, uint64_t *size) +try: (amd_comgr_disassemble_instruction:=dll.amd_comgr_disassemble_instruction).restype, amd_comgr_disassemble_instruction.argtypes = amd_comgr_status_t, [amd_comgr_disassembly_info_t, uint64_t, ctypes.c_void_p, ctypes.POINTER(uint64_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_demangle_symbol_name(amd_comgr_data_t mangled_symbol_name, amd_comgr_data_t *demangled_symbol_name) +try: (amd_comgr_demangle_symbol_name:=dll.amd_comgr_demangle_symbol_name).restype, amd_comgr_demangle_symbol_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_populate_mangled_names(amd_comgr_data_t data, size_t *count) +try: (amd_comgr_populate_mangled_names:=dll.amd_comgr_populate_mangled_names).restype, amd_comgr_populate_mangled_names.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_mangled_name(amd_comgr_data_t data, size_t index, size_t *size, char *mangled_name) +try: (amd_comgr_get_mangled_name:=dll.amd_comgr_get_mangled_name).restype, amd_comgr_get_mangled_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, size_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_populate_name_expression_map(amd_comgr_data_t data, size_t *count) +try: (amd_comgr_populate_name_expression_map:=dll.amd_comgr_populate_name_expression_map).restype, amd_comgr_populate_name_expression_map.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_map_name_expression_to_symbol_name(amd_comgr_data_t data, size_t *size, char *name_expression, char *symbol_name) +try: (amd_comgr_map_name_expression_to_symbol_name:=dll.amd_comgr_map_name_expression_to_symbol_name).restype, amd_comgr_map_name_expression_to_symbol_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class code_object_info_s(Struct): pass +code_object_info_s._fields_ = [ + ('isa', ctypes.POINTER(ctypes.c_char)), + ('size', size_t), + ('offset', uint64_t), +] +amd_comgr_code_object_info_t = code_object_info_s +# amd_comgr_status_t amd_comgr_lookup_code_object(amd_comgr_data_t data, amd_comgr_code_object_info_t *info_list, size_t info_list_size) +try: (amd_comgr_lookup_code_object:=dll.amd_comgr_lookup_code_object).restype, amd_comgr_lookup_code_object.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_code_object_info_t), size_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_map_elf_virtual_address_to_code_object_offset(amd_comgr_data_t data, uint64_t elf_virtual_address, uint64_t *code_object_offset, uint64_t *slice_size, bool *nobits) +try: (amd_comgr_map_elf_virtual_address_to_code_object_offset:=dll.amd_comgr_map_elf_virtual_address_to_code_object_offset).restype, amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = amd_comgr_status_t, [amd_comgr_data_t, uint64_t, ctypes.POINTER(uint64_t), ctypes.POINTER(uint64_t), ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +AMD_COMGR_DEPRECATED = lambda msg: __attribute__((deprecated(msg))) +AMD_COMGR_INTERFACE_VERSION_MAJOR = 2 +AMD_COMGR_INTERFACE_VERSION_MINOR = 8 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/comgr_3.py b/tinygrad/runtime/autogen/comgr_3.py index 0fb7c920e9..ddffa4b702 100644 --- a/tinygrad/runtime/autogen/comgr_3.py +++ b/tinygrad/runtime/autogen/comgr_3.py @@ -1,906 +1,399 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os -PATHS_TO_TRY = [ - '/opt/rocm/lib/libamd_comgr.so', - os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so', - '/usr/local/lib/libamd_comgr.dylib', - '/opt/homebrew/lib/libamd_comgr.dylib', -] -def _try_dlopen_amd_comgr(): - library = ctypes.util.find_library("amd_comgr") - if library: return ctypes.CDLL(library) - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass +import ctypes, os +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +def dll(): + try: return ctypes.CDLL(unwrap(os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libamd_comgr.so')) + except: pass + try: return ctypes.CDLL(unwrap('/usr/local/lib/libamd_comgr.dylib')) + except: pass + try: return ctypes.CDLL(unwrap('/opt/homebrew/lib/libamd_comgr.dylib')) + except: pass return None +dll = dll() +amd_comgr_status_s = CEnum(ctypes.c_uint32) +AMD_COMGR_STATUS_SUCCESS = amd_comgr_status_s.define('AMD_COMGR_STATUS_SUCCESS', 0) +AMD_COMGR_STATUS_ERROR = amd_comgr_status_s.define('AMD_COMGR_STATUS_ERROR', 1) +AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = amd_comgr_status_s.define('AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', 2) +AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = amd_comgr_status_s.define('AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', 3) -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libamd_comgr.so'] = _try_dlopen_amd_comgr() -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - - -# values for enumeration 'amd_comgr_status_s' -amd_comgr_status_s__enumvalues = { - 0: 'AMD_COMGR_STATUS_SUCCESS', - 1: 'AMD_COMGR_STATUS_ERROR', - 2: 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 3: 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', -} -AMD_COMGR_STATUS_SUCCESS = 0 -AMD_COMGR_STATUS_ERROR = 1 -AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = 2 -AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = 3 -amd_comgr_status_s = ctypes.c_uint32 # enum amd_comgr_status_t = amd_comgr_status_s -amd_comgr_status_t__enumvalues = amd_comgr_status_s__enumvalues +amd_comgr_language_s = CEnum(ctypes.c_uint32) +AMD_COMGR_LANGUAGE_NONE = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_NONE', 0) +AMD_COMGR_LANGUAGE_OPENCL_1_2 = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_OPENCL_1_2', 1) +AMD_COMGR_LANGUAGE_OPENCL_2_0 = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_OPENCL_2_0', 2) +AMD_COMGR_LANGUAGE_HIP = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_HIP', 3) +AMD_COMGR_LANGUAGE_LLVM_IR = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_LLVM_IR', 4) +AMD_COMGR_LANGUAGE_LAST = amd_comgr_language_s.define('AMD_COMGR_LANGUAGE_LAST', 4) -# values for enumeration 'amd_comgr_language_s' -amd_comgr_language_s__enumvalues = { - 0: 'AMD_COMGR_LANGUAGE_NONE', - 1: 'AMD_COMGR_LANGUAGE_OPENCL_1_2', - 2: 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 3: 'AMD_COMGR_LANGUAGE_HIP', - 4: 'AMD_COMGR_LANGUAGE_LLVM_IR', - 4: 'AMD_COMGR_LANGUAGE_LAST', -} -AMD_COMGR_LANGUAGE_NONE = 0 -AMD_COMGR_LANGUAGE_OPENCL_1_2 = 1 -AMD_COMGR_LANGUAGE_OPENCL_2_0 = 2 -AMD_COMGR_LANGUAGE_HIP = 3 -AMD_COMGR_LANGUAGE_LLVM_IR = 4 -AMD_COMGR_LANGUAGE_LAST = 4 -amd_comgr_language_s = ctypes.c_uint32 # enum amd_comgr_language_t = amd_comgr_language_s -amd_comgr_language_t__enumvalues = amd_comgr_language_s__enumvalues -try: - amd_comgr_status_string = _libraries['libamd_comgr.so'].amd_comgr_status_string - amd_comgr_status_string.restype = amd_comgr_status_t - amd_comgr_status_string.argtypes = [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_version = _libraries['libamd_comgr.so'].amd_comgr_get_version - amd_comgr_get_version.restype = None - amd_comgr_get_version.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass +# amd_comgr_status_t amd_comgr_status_string(amd_comgr_status_t status, const char **status_string) +try: (amd_comgr_status_string:=dll.amd_comgr_status_string).restype, amd_comgr_status_string.argtypes = amd_comgr_status_t, [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass -# values for enumeration 'amd_comgr_data_kind_s' -amd_comgr_data_kind_s__enumvalues = { - 0: 'AMD_COMGR_DATA_KIND_UNDEF', - 1: 'AMD_COMGR_DATA_KIND_SOURCE', - 2: 'AMD_COMGR_DATA_KIND_INCLUDE', - 3: 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 4: 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 5: 'AMD_COMGR_DATA_KIND_LOG', - 6: 'AMD_COMGR_DATA_KIND_BC', - 7: 'AMD_COMGR_DATA_KIND_RELOCATABLE', - 8: 'AMD_COMGR_DATA_KIND_EXECUTABLE', - 9: 'AMD_COMGR_DATA_KIND_BYTES', - 16: 'AMD_COMGR_DATA_KIND_FATBIN', - 17: 'AMD_COMGR_DATA_KIND_AR', - 18: 'AMD_COMGR_DATA_KIND_BC_BUNDLE', - 19: 'AMD_COMGR_DATA_KIND_AR_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 21: 'AMD_COMGR_DATA_KIND_SPIRV', - 21: 'AMD_COMGR_DATA_KIND_LAST', -} -AMD_COMGR_DATA_KIND_UNDEF = 0 -AMD_COMGR_DATA_KIND_SOURCE = 1 -AMD_COMGR_DATA_KIND_INCLUDE = 2 -AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = 3 -AMD_COMGR_DATA_KIND_DIAGNOSTIC = 4 -AMD_COMGR_DATA_KIND_LOG = 5 -AMD_COMGR_DATA_KIND_BC = 6 -AMD_COMGR_DATA_KIND_RELOCATABLE = 7 -AMD_COMGR_DATA_KIND_EXECUTABLE = 8 -AMD_COMGR_DATA_KIND_BYTES = 9 -AMD_COMGR_DATA_KIND_FATBIN = 16 -AMD_COMGR_DATA_KIND_AR = 17 -AMD_COMGR_DATA_KIND_BC_BUNDLE = 18 -AMD_COMGR_DATA_KIND_AR_BUNDLE = 19 -AMD_COMGR_DATA_KIND_OBJ_BUNDLE = 20 -AMD_COMGR_DATA_KIND_SPIRV = 21 -AMD_COMGR_DATA_KIND_LAST = 21 -amd_comgr_data_kind_s = ctypes.c_uint32 # enum -amd_comgr_data_kind_t = amd_comgr_data_kind_s -amd_comgr_data_kind_t__enumvalues = amd_comgr_data_kind_s__enumvalues -class struct_amd_comgr_data_s(Structure): - pass - -struct_amd_comgr_data_s._pack_ = 1 # source:False -struct_amd_comgr_data_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_t = struct_amd_comgr_data_s -class struct_amd_comgr_data_set_s(Structure): - pass - -struct_amd_comgr_data_set_s._pack_ = 1 # source:False -struct_amd_comgr_data_set_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_set_t = struct_amd_comgr_data_set_s -class struct_amd_comgr_action_info_s(Structure): - pass - -struct_amd_comgr_action_info_s._pack_ = 1 # source:False -struct_amd_comgr_action_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_action_info_t = struct_amd_comgr_action_info_s -class struct_amd_comgr_metadata_node_s(Structure): - pass - -struct_amd_comgr_metadata_node_s._pack_ = 1 # source:False -struct_amd_comgr_metadata_node_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_metadata_node_t = struct_amd_comgr_metadata_node_s -class struct_amd_comgr_symbol_s(Structure): - pass - -struct_amd_comgr_symbol_s._pack_ = 1 # source:False -struct_amd_comgr_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbol_t = struct_amd_comgr_symbol_s -class struct_amd_comgr_disassembly_info_s(Structure): - pass - -struct_amd_comgr_disassembly_info_s._pack_ = 1 # source:False -struct_amd_comgr_disassembly_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_disassembly_info_t = struct_amd_comgr_disassembly_info_s -class struct_amd_comgr_symbolizer_info_s(Structure): - pass - -struct_amd_comgr_symbolizer_info_s._pack_ = 1 # source:False -struct_amd_comgr_symbolizer_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbolizer_info_t = struct_amd_comgr_symbolizer_info_s -try: - amd_comgr_get_isa_count = _libraries['libamd_comgr.so'].amd_comgr_get_isa_count - amd_comgr_get_isa_count.restype = amd_comgr_status_t - amd_comgr_get_isa_count.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass size_t = ctypes.c_uint64 -try: - amd_comgr_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_isa_name - amd_comgr_get_isa_name.restype = amd_comgr_status_t - amd_comgr_get_isa_name.argtypes = [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_isa_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_isa_metadata - amd_comgr_get_isa_metadata.restype = amd_comgr_status_t - amd_comgr_get_isa_metadata.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_create_data = _libraries['libamd_comgr.so'].amd_comgr_create_data - amd_comgr_create_data.restype = amd_comgr_status_t - amd_comgr_create_data.argtypes = [amd_comgr_data_kind_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_release_data = _libraries['libamd_comgr.so'].amd_comgr_release_data - amd_comgr_release_data.restype = amd_comgr_status_t - amd_comgr_release_data.argtypes = [amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_get_data_kind = _libraries['libamd_comgr.so'].amd_comgr_get_data_kind - amd_comgr_get_data_kind.restype = amd_comgr_status_t - amd_comgr_get_data_kind.argtypes = [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_s)] -except AttributeError: - pass -try: - amd_comgr_set_data = _libraries['libamd_comgr.so'].amd_comgr_set_data - amd_comgr_set_data.restype = amd_comgr_status_t - amd_comgr_set_data.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass +# void amd_comgr_get_version(size_t *major, size_t *minor) +try: (amd_comgr_get_version:=dll.amd_comgr_get_version).restype, amd_comgr_get_version.argtypes = None, [ctypes.POINTER(size_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +amd_comgr_data_kind_s = CEnum(ctypes.c_uint32) +AMD_COMGR_DATA_KIND_UNDEF = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_UNDEF', 0) +AMD_COMGR_DATA_KIND_SOURCE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_SOURCE', 1) +AMD_COMGR_DATA_KIND_INCLUDE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_INCLUDE', 2) +AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', 3) +AMD_COMGR_DATA_KIND_DIAGNOSTIC = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_DIAGNOSTIC', 4) +AMD_COMGR_DATA_KIND_LOG = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_LOG', 5) +AMD_COMGR_DATA_KIND_BC = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_BC', 6) +AMD_COMGR_DATA_KIND_RELOCATABLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_RELOCATABLE', 7) +AMD_COMGR_DATA_KIND_EXECUTABLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_EXECUTABLE', 8) +AMD_COMGR_DATA_KIND_BYTES = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_BYTES', 9) +AMD_COMGR_DATA_KIND_FATBIN = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_FATBIN', 16) +AMD_COMGR_DATA_KIND_AR = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_AR', 17) +AMD_COMGR_DATA_KIND_BC_BUNDLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_BC_BUNDLE', 18) +AMD_COMGR_DATA_KIND_AR_BUNDLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_AR_BUNDLE', 19) +AMD_COMGR_DATA_KIND_OBJ_BUNDLE = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_OBJ_BUNDLE', 20) +AMD_COMGR_DATA_KIND_SPIRV = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_SPIRV', 21) +AMD_COMGR_DATA_KIND_LAST = amd_comgr_data_kind_s.define('AMD_COMGR_DATA_KIND_LAST', 21) + +amd_comgr_data_kind_t = amd_comgr_data_kind_s +class amd_comgr_data_s(Struct): pass uint64_t = ctypes.c_uint64 -try: - amd_comgr_set_data_from_file_slice = _libraries['libamd_comgr.so'].amd_comgr_set_data_from_file_slice - amd_comgr_set_data_from_file_slice.restype = amd_comgr_status_t - amd_comgr_set_data_from_file_slice.argtypes = [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] -except AttributeError: - pass -try: - amd_comgr_set_data_name = _libraries['libamd_comgr.so'].amd_comgr_set_data_name - amd_comgr_set_data_name.restype = amd_comgr_status_t - amd_comgr_set_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data = _libraries['libamd_comgr.so'].amd_comgr_get_data - amd_comgr_get_data.restype = amd_comgr_status_t - amd_comgr_get_data.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_name - amd_comgr_get_data_name.restype = amd_comgr_status_t - amd_comgr_get_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_isa_name - amd_comgr_get_data_isa_name.restype = amd_comgr_status_t - amd_comgr_get_data_isa_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_create_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_create_symbolizer_info - amd_comgr_create_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_create_symbolizer_info.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_symbolizer_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_symbolizer_info - amd_comgr_destroy_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_destroy_symbolizer_info.argtypes = [amd_comgr_symbolizer_info_t] -except AttributeError: - pass -try: - amd_comgr_symbolize = _libraries['libamd_comgr.so'].amd_comgr_symbolize - amd_comgr_symbolize.restype = amd_comgr_status_t - amd_comgr_symbolize.argtypes = [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_get_data_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_data_metadata - amd_comgr_get_data_metadata.restype = amd_comgr_status_t - amd_comgr_get_data_metadata.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_metadata = _libraries['libamd_comgr.so'].amd_comgr_destroy_metadata - amd_comgr_destroy_metadata.restype = amd_comgr_status_t - amd_comgr_destroy_metadata.argtypes = [amd_comgr_metadata_node_t] -except AttributeError: - pass -try: - amd_comgr_create_data_set = _libraries['libamd_comgr.so'].amd_comgr_create_data_set - amd_comgr_create_data_set.restype = amd_comgr_status_t - amd_comgr_create_data_set.argtypes = [ctypes.POINTER(struct_amd_comgr_data_set_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_data_set = _libraries['libamd_comgr.so'].amd_comgr_destroy_data_set - amd_comgr_destroy_data_set.restype = amd_comgr_status_t - amd_comgr_destroy_data_set.argtypes = [amd_comgr_data_set_t] -except AttributeError: - pass -try: - amd_comgr_data_set_add = _libraries['libamd_comgr.so'].amd_comgr_data_set_add - amd_comgr_data_set_add.restype = amd_comgr_status_t - amd_comgr_data_set_add.argtypes = [amd_comgr_data_set_t, amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_data_set_remove = _libraries['libamd_comgr.so'].amd_comgr_data_set_remove - amd_comgr_data_set_remove.restype = amd_comgr_status_t - amd_comgr_data_set_remove.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t] -except AttributeError: - pass -try: - amd_comgr_action_data_count = _libraries['libamd_comgr.so'].amd_comgr_action_data_count - amd_comgr_action_data_count.restype = amd_comgr_status_t - amd_comgr_action_data_count.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_data_get_data = _libraries['libamd_comgr.so'].amd_comgr_action_data_get_data - amd_comgr_action_data_get_data.restype = amd_comgr_status_t - amd_comgr_action_data_get_data.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_create_action_info = _libraries['libamd_comgr.so'].amd_comgr_create_action_info - amd_comgr_create_action_info.restype = amd_comgr_status_t - amd_comgr_create_action_info.argtypes = [ctypes.POINTER(struct_amd_comgr_action_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_action_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_action_info - amd_comgr_destroy_action_info.restype = amd_comgr_status_t - amd_comgr_destroy_action_info.argtypes = [amd_comgr_action_info_t] -except AttributeError: - pass -try: - amd_comgr_action_info_set_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_isa_name - amd_comgr_action_info_set_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_set_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_isa_name - amd_comgr_action_info_get_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_get_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_language - amd_comgr_action_info_set_language.restype = amd_comgr_status_t - amd_comgr_action_info_set_language.argtypes = [amd_comgr_action_info_t, amd_comgr_language_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_language - amd_comgr_action_info_get_language.restype = amd_comgr_status_t - amd_comgr_action_info_get_language.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_s)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_option_list = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_option_list - amd_comgr_action_info_set_option_list.restype = amd_comgr_status_t - amd_comgr_action_info_set_option_list.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_count - amd_comgr_action_info_get_option_list_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_item = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_item - amd_comgr_action_info_get_option_list_item.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_item.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_bundle_entry_ids = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_bundle_entry_ids - amd_comgr_action_info_set_bundle_entry_ids.restype = amd_comgr_status_t - amd_comgr_action_info_set_bundle_entry_ids.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id_count - amd_comgr_action_info_get_bundle_entry_id_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id - amd_comgr_action_info_get_bundle_entry_id.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_device_lib_linking = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_device_lib_linking - amd_comgr_action_info_set_device_lib_linking.restype = amd_comgr_status_t - amd_comgr_action_info_set_device_lib_linking.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_set_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_working_directory_path - amd_comgr_action_info_set_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_set_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_working_directory_path - amd_comgr_action_info_get_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_get_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_logging - amd_comgr_action_info_set_logging.restype = amd_comgr_status_t - amd_comgr_action_info_set_logging.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_get_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_logging - amd_comgr_action_info_get_logging.restype = amd_comgr_status_t - amd_comgr_action_info_get_logging.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_action_kind_s' -amd_comgr_action_kind_s__enumvalues = { - 0: 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 1: 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 2: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 3: 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 4: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 5: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 6: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 7: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 8: 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 9: 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 10: 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 11: 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 12: 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 13: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 14: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 15: 'AMD_COMGR_ACTION_UNBUNDLE', - 19: 'AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', - 19: 'AMD_COMGR_ACTION_LAST', -} -AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = 0 -AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = 1 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = 2 -AMD_COMGR_ACTION_LINK_BC_TO_BC = 3 -AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = 4 -AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = 5 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = 6 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = 7 -AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = 8 -AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = 9 -AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = 10 -AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = 11 -AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = 12 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = 13 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = 14 -AMD_COMGR_ACTION_UNBUNDLE = 15 -AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC = 19 -AMD_COMGR_ACTION_LAST = 19 -amd_comgr_action_kind_s = ctypes.c_uint32 # enum -amd_comgr_action_kind_t = amd_comgr_action_kind_s -amd_comgr_action_kind_t__enumvalues = amd_comgr_action_kind_s__enumvalues -try: - amd_comgr_do_action = _libraries['libamd_comgr.so'].amd_comgr_do_action - amd_comgr_do_action.restype = amd_comgr_status_t - amd_comgr_do_action.argtypes = [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_metadata_kind_s' -amd_comgr_metadata_kind_s__enumvalues = { - 0: 'AMD_COMGR_METADATA_KIND_NULL', - 1: 'AMD_COMGR_METADATA_KIND_STRING', - 2: 'AMD_COMGR_METADATA_KIND_MAP', - 3: 'AMD_COMGR_METADATA_KIND_LIST', - 3: 'AMD_COMGR_METADATA_KIND_LAST', -} -AMD_COMGR_METADATA_KIND_NULL = 0 -AMD_COMGR_METADATA_KIND_STRING = 1 -AMD_COMGR_METADATA_KIND_MAP = 2 -AMD_COMGR_METADATA_KIND_LIST = 3 -AMD_COMGR_METADATA_KIND_LAST = 3 -amd_comgr_metadata_kind_s = ctypes.c_uint32 # enum -amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s -amd_comgr_metadata_kind_t__enumvalues = amd_comgr_metadata_kind_s__enumvalues -try: - amd_comgr_get_metadata_kind = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_kind - amd_comgr_get_metadata_kind.restype = amd_comgr_status_t - amd_comgr_get_metadata_kind.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_string = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_string - amd_comgr_get_metadata_string.restype = amd_comgr_status_t - amd_comgr_get_metadata_string.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_map_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_map_size - amd_comgr_get_metadata_map_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_map_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_iterate_map_metadata = _libraries['libamd_comgr.so'].amd_comgr_iterate_map_metadata - amd_comgr_iterate_map_metadata.restype = amd_comgr_status_t - amd_comgr_iterate_map_metadata.argtypes = [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_metadata_node_s, struct_amd_comgr_metadata_node_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_metadata_lookup = _libraries['libamd_comgr.so'].amd_comgr_metadata_lookup - amd_comgr_metadata_lookup.restype = amd_comgr_status_t - amd_comgr_metadata_lookup.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_list_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_list_size - amd_comgr_get_metadata_list_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_list_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_index_list_metadata = _libraries['libamd_comgr.so'].amd_comgr_index_list_metadata - amd_comgr_index_list_metadata.restype = amd_comgr_status_t - amd_comgr_index_list_metadata.argtypes = [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_iterate_symbols = _libraries['libamd_comgr.so'].amd_comgr_iterate_symbols - amd_comgr_iterate_symbols.restype = amd_comgr_status_t - amd_comgr_iterate_symbols.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_symbol_lookup = _libraries['libamd_comgr.so'].amd_comgr_symbol_lookup - amd_comgr_symbol_lookup.restype = amd_comgr_status_t - amd_comgr_symbol_lookup.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_symbol_type_s' -amd_comgr_symbol_type_s__enumvalues = { - -1: 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', - 0: 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 1: 'AMD_COMGR_SYMBOL_TYPE_OBJECT', - 2: 'AMD_COMGR_SYMBOL_TYPE_FUNC', - 3: 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 4: 'AMD_COMGR_SYMBOL_TYPE_FILE', - 5: 'AMD_COMGR_SYMBOL_TYPE_COMMON', - 10: 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', -} -AMD_COMGR_SYMBOL_TYPE_UNKNOWN = -1 -AMD_COMGR_SYMBOL_TYPE_NOTYPE = 0 -AMD_COMGR_SYMBOL_TYPE_OBJECT = 1 -AMD_COMGR_SYMBOL_TYPE_FUNC = 2 -AMD_COMGR_SYMBOL_TYPE_SECTION = 3 -AMD_COMGR_SYMBOL_TYPE_FILE = 4 -AMD_COMGR_SYMBOL_TYPE_COMMON = 5 -AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = 10 -amd_comgr_symbol_type_s = ctypes.c_int32 # enum -amd_comgr_symbol_type_t = amd_comgr_symbol_type_s -amd_comgr_symbol_type_t__enumvalues = amd_comgr_symbol_type_s__enumvalues - -# values for enumeration 'amd_comgr_symbol_info_s' -amd_comgr_symbol_info_s__enumvalues = { - 0: 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', - 1: 'AMD_COMGR_SYMBOL_INFO_NAME', - 2: 'AMD_COMGR_SYMBOL_INFO_TYPE', - 3: 'AMD_COMGR_SYMBOL_INFO_SIZE', - 4: 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 5: 'AMD_COMGR_SYMBOL_INFO_VALUE', - 5: 'AMD_COMGR_SYMBOL_INFO_LAST', -} -AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = 0 -AMD_COMGR_SYMBOL_INFO_NAME = 1 -AMD_COMGR_SYMBOL_INFO_TYPE = 2 -AMD_COMGR_SYMBOL_INFO_SIZE = 3 -AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = 4 -AMD_COMGR_SYMBOL_INFO_VALUE = 5 -AMD_COMGR_SYMBOL_INFO_LAST = 5 -amd_comgr_symbol_info_s = ctypes.c_uint32 # enum -amd_comgr_symbol_info_t = amd_comgr_symbol_info_s -amd_comgr_symbol_info_t__enumvalues = amd_comgr_symbol_info_s__enumvalues -try: - amd_comgr_symbol_get_info = _libraries['libamd_comgr.so'].amd_comgr_symbol_get_info - amd_comgr_symbol_get_info.restype = amd_comgr_status_t - amd_comgr_symbol_get_info.argtypes = [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_create_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_create_disassembly_info - amd_comgr_create_disassembly_info.restype = amd_comgr_status_t - amd_comgr_create_disassembly_info.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(ctypes.c_char), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_disassembly_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_disassembly_info - amd_comgr_destroy_disassembly_info.restype = amd_comgr_status_t - amd_comgr_destroy_disassembly_info.argtypes = [amd_comgr_disassembly_info_t] -except AttributeError: - pass -try: - amd_comgr_disassemble_instruction = _libraries['libamd_comgr.so'].amd_comgr_disassemble_instruction - amd_comgr_disassemble_instruction.restype = amd_comgr_status_t - amd_comgr_disassemble_instruction.argtypes = [amd_comgr_disassembly_info_t, uint64_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_demangle_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_demangle_symbol_name - amd_comgr_demangle_symbol_name.restype = amd_comgr_status_t - amd_comgr_demangle_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_populate_mangled_names = _libraries['libamd_comgr.so'].amd_comgr_populate_mangled_names - amd_comgr_populate_mangled_names.restype = amd_comgr_status_t - amd_comgr_populate_mangled_names.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_get_mangled_name = _libraries['libamd_comgr.so'].amd_comgr_get_mangled_name - amd_comgr_get_mangled_name.restype = amd_comgr_status_t - amd_comgr_get_mangled_name.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_populate_name_expression_map = _libraries['libamd_comgr.so'].amd_comgr_populate_name_expression_map - amd_comgr_populate_name_expression_map.restype = amd_comgr_status_t - amd_comgr_populate_name_expression_map.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_map_name_expression_to_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_map_name_expression_to_symbol_name - amd_comgr_map_name_expression_to_symbol_name.restype = amd_comgr_status_t - amd_comgr_map_name_expression_to_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_code_object_info_s(Structure): - pass - -struct_code_object_info_s._pack_ = 1 # source:False -struct_code_object_info_s._fields_ = [ - ('isa', ctypes.POINTER(ctypes.c_char)), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), +amd_comgr_data_s._fields_ = [ + ('handle', uint64_t), ] +amd_comgr_data_t = amd_comgr_data_s +class amd_comgr_data_set_s(Struct): pass +amd_comgr_data_set_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_data_set_t = amd_comgr_data_set_s +class amd_comgr_action_info_s(Struct): pass +amd_comgr_action_info_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_action_info_t = amd_comgr_action_info_s +class amd_comgr_metadata_node_s(Struct): pass +amd_comgr_metadata_node_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_metadata_node_t = amd_comgr_metadata_node_s +class amd_comgr_symbol_s(Struct): pass +amd_comgr_symbol_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_symbol_t = amd_comgr_symbol_s +class amd_comgr_disassembly_info_s(Struct): pass +amd_comgr_disassembly_info_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_disassembly_info_t = amd_comgr_disassembly_info_s +class amd_comgr_symbolizer_info_s(Struct): pass +amd_comgr_symbolizer_info_s._fields_ = [ + ('handle', uint64_t), +] +amd_comgr_symbolizer_info_t = amd_comgr_symbolizer_info_s +# amd_comgr_status_t amd_comgr_get_isa_count(size_t *count) +try: (amd_comgr_get_isa_count:=dll.amd_comgr_get_isa_count).restype, amd_comgr_get_isa_count.argtypes = amd_comgr_status_t, [ctypes.POINTER(size_t)] +except AttributeError: pass -amd_comgr_code_object_info_t = struct_code_object_info_s -try: - amd_comgr_lookup_code_object = _libraries['libamd_comgr.so'].amd_comgr_lookup_code_object - amd_comgr_lookup_code_object.restype = amd_comgr_status_t - amd_comgr_lookup_code_object.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_code_object_info_s), size_t] -except AttributeError: - pass -try: - amd_comgr_map_elf_virtual_address_to_code_object_offset = _libraries['libamd_comgr.so'].amd_comgr_map_elf_virtual_address_to_code_object_offset - amd_comgr_map_elf_virtual_address_to_code_object_offset.restype = amd_comgr_status_t - amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = [amd_comgr_data_t, uint64_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -__all__ = \ - ['AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_LAST', 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 'AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', - 'AMD_COMGR_ACTION_UNBUNDLE', 'AMD_COMGR_DATA_KIND_AR', - 'AMD_COMGR_DATA_KIND_AR_BUNDLE', 'AMD_COMGR_DATA_KIND_BC', - 'AMD_COMGR_DATA_KIND_BC_BUNDLE', 'AMD_COMGR_DATA_KIND_BYTES', - 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 'AMD_COMGR_DATA_KIND_EXECUTABLE', 'AMD_COMGR_DATA_KIND_FATBIN', - 'AMD_COMGR_DATA_KIND_INCLUDE', 'AMD_COMGR_DATA_KIND_LAST', - 'AMD_COMGR_DATA_KIND_LOG', 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 'AMD_COMGR_DATA_KIND_RELOCATABLE', 'AMD_COMGR_DATA_KIND_SOURCE', - 'AMD_COMGR_DATA_KIND_SPIRV', 'AMD_COMGR_DATA_KIND_UNDEF', - 'AMD_COMGR_LANGUAGE_HIP', 'AMD_COMGR_LANGUAGE_LAST', - 'AMD_COMGR_LANGUAGE_LLVM_IR', 'AMD_COMGR_LANGUAGE_NONE', - 'AMD_COMGR_LANGUAGE_OPENCL_1_2', 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 'AMD_COMGR_METADATA_KIND_LAST', 'AMD_COMGR_METADATA_KIND_LIST', - 'AMD_COMGR_METADATA_KIND_MAP', 'AMD_COMGR_METADATA_KIND_NULL', - 'AMD_COMGR_METADATA_KIND_STRING', 'AMD_COMGR_STATUS_ERROR', - 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', - 'AMD_COMGR_STATUS_SUCCESS', 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 'AMD_COMGR_SYMBOL_INFO_LAST', 'AMD_COMGR_SYMBOL_INFO_NAME', - 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 'AMD_COMGR_SYMBOL_INFO_SIZE', - 'AMD_COMGR_SYMBOL_INFO_TYPE', 'AMD_COMGR_SYMBOL_INFO_VALUE', - 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', - 'AMD_COMGR_SYMBOL_TYPE_COMMON', 'AMD_COMGR_SYMBOL_TYPE_FILE', - 'AMD_COMGR_SYMBOL_TYPE_FUNC', 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 'AMD_COMGR_SYMBOL_TYPE_OBJECT', 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', 'amd_comgr_action_data_count', - 'amd_comgr_action_data_get_data', - 'amd_comgr_action_info_get_bundle_entry_id', - 'amd_comgr_action_info_get_bundle_entry_id_count', - 'amd_comgr_action_info_get_isa_name', - 'amd_comgr_action_info_get_language', - 'amd_comgr_action_info_get_logging', - 'amd_comgr_action_info_get_option_list_count', - 'amd_comgr_action_info_get_option_list_item', - 'amd_comgr_action_info_get_working_directory_path', - 'amd_comgr_action_info_set_bundle_entry_ids', - 'amd_comgr_action_info_set_device_lib_linking', - 'amd_comgr_action_info_set_isa_name', - 'amd_comgr_action_info_set_language', - 'amd_comgr_action_info_set_logging', - 'amd_comgr_action_info_set_option_list', - 'amd_comgr_action_info_set_working_directory_path', - 'amd_comgr_action_info_t', 'amd_comgr_action_kind_s', - 'amd_comgr_action_kind_t', 'amd_comgr_action_kind_t__enumvalues', - 'amd_comgr_code_object_info_t', 'amd_comgr_create_action_info', - 'amd_comgr_create_data', 'amd_comgr_create_data_set', - 'amd_comgr_create_disassembly_info', - 'amd_comgr_create_symbolizer_info', 'amd_comgr_data_kind_s', - 'amd_comgr_data_kind_t', 'amd_comgr_data_kind_t__enumvalues', - 'amd_comgr_data_set_add', 'amd_comgr_data_set_remove', - 'amd_comgr_data_set_t', 'amd_comgr_data_t', - 'amd_comgr_demangle_symbol_name', 'amd_comgr_destroy_action_info', - 'amd_comgr_destroy_data_set', - 'amd_comgr_destroy_disassembly_info', - 'amd_comgr_destroy_metadata', 'amd_comgr_destroy_symbolizer_info', - 'amd_comgr_disassemble_instruction', - 'amd_comgr_disassembly_info_t', 'amd_comgr_do_action', - 'amd_comgr_get_data', 'amd_comgr_get_data_isa_name', - 'amd_comgr_get_data_kind', 'amd_comgr_get_data_metadata', - 'amd_comgr_get_data_name', 'amd_comgr_get_isa_count', - 'amd_comgr_get_isa_metadata', 'amd_comgr_get_isa_name', - 'amd_comgr_get_mangled_name', 'amd_comgr_get_metadata_kind', - 'amd_comgr_get_metadata_list_size', - 'amd_comgr_get_metadata_map_size', - 'amd_comgr_get_metadata_string', 'amd_comgr_get_version', - 'amd_comgr_index_list_metadata', 'amd_comgr_iterate_map_metadata', - 'amd_comgr_iterate_symbols', 'amd_comgr_language_s', - 'amd_comgr_language_t', 'amd_comgr_language_t__enumvalues', - 'amd_comgr_lookup_code_object', - 'amd_comgr_map_elf_virtual_address_to_code_object_offset', - 'amd_comgr_map_name_expression_to_symbol_name', - 'amd_comgr_metadata_kind_s', 'amd_comgr_metadata_kind_t', - 'amd_comgr_metadata_kind_t__enumvalues', - 'amd_comgr_metadata_lookup', 'amd_comgr_metadata_node_t', - 'amd_comgr_populate_mangled_names', - 'amd_comgr_populate_name_expression_map', - 'amd_comgr_release_data', 'amd_comgr_set_data', - 'amd_comgr_set_data_from_file_slice', 'amd_comgr_set_data_name', - 'amd_comgr_status_s', 'amd_comgr_status_string', - 'amd_comgr_status_t', 'amd_comgr_status_t__enumvalues', - 'amd_comgr_symbol_get_info', 'amd_comgr_symbol_info_s', - 'amd_comgr_symbol_info_t', 'amd_comgr_symbol_info_t__enumvalues', - 'amd_comgr_symbol_lookup', 'amd_comgr_symbol_t', - 'amd_comgr_symbol_type_s', 'amd_comgr_symbol_type_t', - 'amd_comgr_symbol_type_t__enumvalues', 'amd_comgr_symbolize', - 'amd_comgr_symbolizer_info_t', 'size_t', - 'struct_amd_comgr_action_info_s', 'struct_amd_comgr_data_s', - 'struct_amd_comgr_data_set_s', - 'struct_amd_comgr_disassembly_info_s', - 'struct_amd_comgr_metadata_node_s', 'struct_amd_comgr_symbol_s', - 'struct_amd_comgr_symbolizer_info_s', 'struct_code_object_info_s', - 'uint64_t'] +# amd_comgr_status_t amd_comgr_get_isa_name(size_t index, const char **isa_name) +try: (amd_comgr_get_isa_name:=dll.amd_comgr_get_isa_name).restype, amd_comgr_get_isa_name.argtypes = amd_comgr_status_t, [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_isa_metadata(const char *isa_name, amd_comgr_metadata_node_t *metadata) +try: (amd_comgr_get_isa_metadata:=dll.amd_comgr_get_isa_metadata).restype, amd_comgr_get_isa_metadata.argtypes = amd_comgr_status_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_data(amd_comgr_data_kind_t kind, amd_comgr_data_t *data) +try: (amd_comgr_create_data:=dll.amd_comgr_create_data).restype, amd_comgr_create_data.argtypes = amd_comgr_status_t, [amd_comgr_data_kind_t, ctypes.POINTER(amd_comgr_data_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_release_data(amd_comgr_data_t data) +try: (amd_comgr_release_data:=dll.amd_comgr_release_data).restype, amd_comgr_release_data.argtypes = amd_comgr_status_t, [amd_comgr_data_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_kind(amd_comgr_data_t data, amd_comgr_data_kind_t *kind) +try: (amd_comgr_get_data_kind:=dll.amd_comgr_get_data_kind).restype, amd_comgr_get_data_kind.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_set_data(amd_comgr_data_t data, size_t size, const char *bytes) +try: (amd_comgr_set_data:=dll.amd_comgr_set_data).restype, amd_comgr_set_data.argtypes = amd_comgr_status_t, [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_set_data_from_file_slice(amd_comgr_data_t data, int file_descriptor, uint64_t offset, uint64_t size) +try: (amd_comgr_set_data_from_file_slice:=dll.amd_comgr_set_data_from_file_slice).restype, amd_comgr_set_data_from_file_slice.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_set_data_name(amd_comgr_data_t data, const char *name) +try: (amd_comgr_set_data_name:=dll.amd_comgr_set_data_name).restype, amd_comgr_set_data_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data(amd_comgr_data_t data, size_t *size, char *bytes) +try: (amd_comgr_get_data:=dll.amd_comgr_get_data).restype, amd_comgr_get_data.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_name(amd_comgr_data_t data, size_t *size, char *name) +try: (amd_comgr_get_data_name:=dll.amd_comgr_get_data_name).restype, amd_comgr_get_data_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_isa_name(amd_comgr_data_t data, size_t *size, char *isa_name) +try: (amd_comgr_get_data_isa_name:=dll.amd_comgr_get_data_isa_name).restype, amd_comgr_get_data_isa_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_symbolizer_info(amd_comgr_data_t code_object, void (*print_symbol_callback)(const char *, void *), amd_comgr_symbolizer_info_t *symbolizer_info) +try: (amd_comgr_create_symbolizer_info:=dll.amd_comgr_create_symbolizer_info).restype, amd_comgr_create_symbolizer_info.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p), ctypes.POINTER(amd_comgr_symbolizer_info_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_symbolizer_info(amd_comgr_symbolizer_info_t symbolizer_info) +try: (amd_comgr_destroy_symbolizer_info:=dll.amd_comgr_destroy_symbolizer_info).restype, amd_comgr_destroy_symbolizer_info.argtypes = amd_comgr_status_t, [amd_comgr_symbolizer_info_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_symbolize(amd_comgr_symbolizer_info_t symbolizer_info, uint64_t address, bool is_code, void *user_data) +try: (amd_comgr_symbolize:=dll.amd_comgr_symbolize).restype, amd_comgr_symbolize.argtypes = amd_comgr_status_t, [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_data_metadata(amd_comgr_data_t data, amd_comgr_metadata_node_t *metadata) +try: (amd_comgr_get_data_metadata:=dll.amd_comgr_get_data_metadata).restype, amd_comgr_get_data_metadata.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_metadata(amd_comgr_metadata_node_t metadata) +try: (amd_comgr_destroy_metadata:=dll.amd_comgr_destroy_metadata).restype, amd_comgr_destroy_metadata.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_data_set(amd_comgr_data_set_t *data_set) +try: (amd_comgr_create_data_set:=dll.amd_comgr_create_data_set).restype, amd_comgr_create_data_set.argtypes = amd_comgr_status_t, [ctypes.POINTER(amd_comgr_data_set_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_data_set(amd_comgr_data_set_t data_set) +try: (amd_comgr_destroy_data_set:=dll.amd_comgr_destroy_data_set).restype, amd_comgr_destroy_data_set.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_data_set_add(amd_comgr_data_set_t data_set, amd_comgr_data_t data) +try: (amd_comgr_data_set_add:=dll.amd_comgr_data_set_add).restype, amd_comgr_data_set_add.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_data_set_remove(amd_comgr_data_set_t data_set, amd_comgr_data_kind_t data_kind) +try: (amd_comgr_data_set_remove:=dll.amd_comgr_data_set_remove).restype, amd_comgr_data_set_remove.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_kind_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_data_count(amd_comgr_data_set_t data_set, amd_comgr_data_kind_t data_kind, size_t *count) +try: (amd_comgr_action_data_count:=dll.amd_comgr_action_data_count).restype, amd_comgr_action_data_count.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_data_get_data(amd_comgr_data_set_t data_set, amd_comgr_data_kind_t data_kind, size_t index, amd_comgr_data_t *data) +try: (amd_comgr_action_data_get_data:=dll.amd_comgr_action_data_get_data).restype, amd_comgr_action_data_get_data.argtypes = amd_comgr_status_t, [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(amd_comgr_data_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_action_info(amd_comgr_action_info_t *action_info) +try: (amd_comgr_create_action_info:=dll.amd_comgr_create_action_info).restype, amd_comgr_create_action_info.argtypes = amd_comgr_status_t, [ctypes.POINTER(amd_comgr_action_info_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_action_info(amd_comgr_action_info_t action_info) +try: (amd_comgr_destroy_action_info:=dll.amd_comgr_destroy_action_info).restype, amd_comgr_destroy_action_info.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_isa_name(amd_comgr_action_info_t action_info, const char *isa_name) +try: (amd_comgr_action_info_set_isa_name:=dll.amd_comgr_action_info_set_isa_name).restype, amd_comgr_action_info_set_isa_name.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_isa_name(amd_comgr_action_info_t action_info, size_t *size, char *isa_name) +try: (amd_comgr_action_info_get_isa_name:=dll.amd_comgr_action_info_get_isa_name).restype, amd_comgr_action_info_get_isa_name.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_language(amd_comgr_action_info_t action_info, amd_comgr_language_t language) +try: (amd_comgr_action_info_set_language:=dll.amd_comgr_action_info_set_language).restype, amd_comgr_action_info_set_language.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, amd_comgr_language_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_language(amd_comgr_action_info_t action_info, amd_comgr_language_t *language) +try: (amd_comgr_action_info_get_language:=dll.amd_comgr_action_info_get_language).restype, amd_comgr_action_info_get_language.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_option_list(amd_comgr_action_info_t action_info, const char *options[], size_t count) +try: (amd_comgr_action_info_set_option_list:=dll.amd_comgr_action_info_set_option_list).restype, amd_comgr_action_info_set_option_list.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, (ctypes.POINTER(ctypes.c_char) * 0), size_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_option_list_count(amd_comgr_action_info_t action_info, size_t *count) +try: (amd_comgr_action_info_get_option_list_count:=dll.amd_comgr_action_info_get_option_list_count).restype, amd_comgr_action_info_get_option_list_count.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_option_list_item(amd_comgr_action_info_t action_info, size_t index, size_t *size, char *option) +try: (amd_comgr_action_info_get_option_list_item:=dll.amd_comgr_action_info_get_option_list_item).restype, amd_comgr_action_info_get_option_list_item.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, size_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_bundle_entry_ids(amd_comgr_action_info_t action_info, const char *bundle_entry_ids[], size_t count) +try: (amd_comgr_action_info_set_bundle_entry_ids:=dll.amd_comgr_action_info_set_bundle_entry_ids).restype, amd_comgr_action_info_set_bundle_entry_ids.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, (ctypes.POINTER(ctypes.c_char) * 0), size_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_bundle_entry_id_count(amd_comgr_action_info_t action_info, size_t *count) +try: (amd_comgr_action_info_get_bundle_entry_id_count:=dll.amd_comgr_action_info_get_bundle_entry_id_count).restype, amd_comgr_action_info_get_bundle_entry_id_count.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_bundle_entry_id(amd_comgr_action_info_t action_info, size_t index, size_t *size, char *bundle_entry_id) +try: (amd_comgr_action_info_get_bundle_entry_id:=dll.amd_comgr_action_info_get_bundle_entry_id).restype, amd_comgr_action_info_get_bundle_entry_id.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, size_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_device_lib_linking(amd_comgr_action_info_t action_info, bool should_link_device_libs) +try: (amd_comgr_action_info_set_device_lib_linking:=dll.amd_comgr_action_info_set_device_lib_linking).restype, amd_comgr_action_info_set_device_lib_linking.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.c_bool] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_working_directory_path(amd_comgr_action_info_t action_info, const char *path) +try: (amd_comgr_action_info_set_working_directory_path:=dll.amd_comgr_action_info_set_working_directory_path).restype, amd_comgr_action_info_set_working_directory_path.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_working_directory_path(amd_comgr_action_info_t action_info, size_t *size, char *path) +try: (amd_comgr_action_info_get_working_directory_path:=dll.amd_comgr_action_info_get_working_directory_path).restype, amd_comgr_action_info_get_working_directory_path.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_set_logging(amd_comgr_action_info_t action_info, bool logging) +try: (amd_comgr_action_info_set_logging:=dll.amd_comgr_action_info_set_logging).restype, amd_comgr_action_info_set_logging.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.c_bool] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_action_info_get_logging(amd_comgr_action_info_t action_info, bool *logging) +try: (amd_comgr_action_info_get_logging:=dll.amd_comgr_action_info_get_logging).restype, amd_comgr_action_info_get_logging.argtypes = amd_comgr_status_t, [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +amd_comgr_action_kind_s = CEnum(ctypes.c_uint32) +AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', 0) +AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', 1) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', 2) +AMD_COMGR_ACTION_LINK_BC_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LINK_BC_TO_BC', 3) +AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', 4) +AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', 5) +AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', 6) +AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', 7) +AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', 8) +AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', 9) +AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', 10) +AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', 11) +AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', 12) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', 13) +AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', 14) +AMD_COMGR_ACTION_UNBUNDLE = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_UNBUNDLE', 15) +AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', 19) +AMD_COMGR_ACTION_LAST = amd_comgr_action_kind_s.define('AMD_COMGR_ACTION_LAST', 19) + +amd_comgr_action_kind_t = amd_comgr_action_kind_s +# amd_comgr_status_t amd_comgr_do_action(amd_comgr_action_kind_t kind, amd_comgr_action_info_t info, amd_comgr_data_set_t input, amd_comgr_data_set_t result) +try: (amd_comgr_do_action:=dll.amd_comgr_do_action).restype, amd_comgr_do_action.argtypes = amd_comgr_status_t, [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] +except AttributeError: pass + +amd_comgr_metadata_kind_s = CEnum(ctypes.c_uint32) +AMD_COMGR_METADATA_KIND_NULL = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_NULL', 0) +AMD_COMGR_METADATA_KIND_STRING = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_STRING', 1) +AMD_COMGR_METADATA_KIND_MAP = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_MAP', 2) +AMD_COMGR_METADATA_KIND_LIST = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_LIST', 3) +AMD_COMGR_METADATA_KIND_LAST = amd_comgr_metadata_kind_s.define('AMD_COMGR_METADATA_KIND_LAST', 3) + +amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s +# amd_comgr_status_t amd_comgr_get_metadata_kind(amd_comgr_metadata_node_t metadata, amd_comgr_metadata_kind_t *kind) +try: (amd_comgr_get_metadata_kind:=dll.amd_comgr_get_metadata_kind).restype, amd_comgr_get_metadata_kind.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_metadata_string(amd_comgr_metadata_node_t metadata, size_t *size, char *string) +try: (amd_comgr_get_metadata_string:=dll.amd_comgr_get_metadata_string).restype, amd_comgr_get_metadata_string.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_metadata_map_size(amd_comgr_metadata_node_t metadata, size_t *size) +try: (amd_comgr_get_metadata_map_size:=dll.amd_comgr_get_metadata_map_size).restype, amd_comgr_get_metadata_map_size.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_iterate_map_metadata(amd_comgr_metadata_node_t metadata, amd_comgr_status_t (*callback)(amd_comgr_metadata_node_t, amd_comgr_metadata_node_t, void *), void *user_data) +try: (amd_comgr_iterate_map_metadata:=dll.amd_comgr_iterate_map_metadata).restype, amd_comgr_iterate_map_metadata.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_t, amd_comgr_metadata_node_t, amd_comgr_metadata_node_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_metadata_lookup(amd_comgr_metadata_node_t metadata, const char *key, amd_comgr_metadata_node_t *value) +try: (amd_comgr_metadata_lookup:=dll.amd_comgr_metadata_lookup).restype, amd_comgr_metadata_lookup.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_metadata_list_size(amd_comgr_metadata_node_t metadata, size_t *size) +try: (amd_comgr_get_metadata_list_size:=dll.amd_comgr_get_metadata_list_size).restype, amd_comgr_get_metadata_list_size.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_index_list_metadata(amd_comgr_metadata_node_t metadata, size_t index, amd_comgr_metadata_node_t *value) +try: (amd_comgr_index_list_metadata:=dll.amd_comgr_index_list_metadata).restype, amd_comgr_index_list_metadata.argtypes = amd_comgr_status_t, [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(amd_comgr_metadata_node_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_iterate_symbols(amd_comgr_data_t data, amd_comgr_status_t (*callback)(amd_comgr_symbol_t, void *), void *user_data) +try: (amd_comgr_iterate_symbols:=dll.amd_comgr_iterate_symbols).restype, amd_comgr_iterate_symbols.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_t, amd_comgr_symbol_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_symbol_lookup(amd_comgr_data_t data, const char *name, amd_comgr_symbol_t *symbol) +try: (amd_comgr_symbol_lookup:=dll.amd_comgr_symbol_lookup).restype, amd_comgr_symbol_lookup.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(amd_comgr_symbol_t)] +except AttributeError: pass + +amd_comgr_symbol_type_s = CEnum(ctypes.c_int32) +AMD_COMGR_SYMBOL_TYPE_UNKNOWN = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_UNKNOWN', -1) +AMD_COMGR_SYMBOL_TYPE_NOTYPE = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_NOTYPE', 0) +AMD_COMGR_SYMBOL_TYPE_OBJECT = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_OBJECT', 1) +AMD_COMGR_SYMBOL_TYPE_FUNC = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_FUNC', 2) +AMD_COMGR_SYMBOL_TYPE_SECTION = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_SECTION', 3) +AMD_COMGR_SYMBOL_TYPE_FILE = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_FILE', 4) +AMD_COMGR_SYMBOL_TYPE_COMMON = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_COMMON', 5) +AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = amd_comgr_symbol_type_s.define('AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', 10) + +amd_comgr_symbol_type_t = amd_comgr_symbol_type_s +amd_comgr_symbol_info_s = CEnum(ctypes.c_uint32) +AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 0) +AMD_COMGR_SYMBOL_INFO_NAME = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_NAME', 1) +AMD_COMGR_SYMBOL_INFO_TYPE = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_TYPE', 2) +AMD_COMGR_SYMBOL_INFO_SIZE = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_SIZE', 3) +AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', 4) +AMD_COMGR_SYMBOL_INFO_VALUE = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_VALUE', 5) +AMD_COMGR_SYMBOL_INFO_LAST = amd_comgr_symbol_info_s.define('AMD_COMGR_SYMBOL_INFO_LAST', 5) + +amd_comgr_symbol_info_t = amd_comgr_symbol_info_s +# amd_comgr_status_t amd_comgr_symbol_get_info(amd_comgr_symbol_t symbol, amd_comgr_symbol_info_t attribute, void *value) +try: (amd_comgr_symbol_get_info:=dll.amd_comgr_symbol_get_info).restype, amd_comgr_symbol_get_info.argtypes = amd_comgr_status_t, [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.c_void_p] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_create_disassembly_info(const char *isa_name, uint64_t (*read_memory_callback)(uint64_t, char *, uint64_t, void *), void (*print_instruction_callback)(const char *, void *), void (*print_address_annotation_callback)(uint64_t, void *), amd_comgr_disassembly_info_t *disassembly_info) +try: (amd_comgr_create_disassembly_info:=dll.amd_comgr_create_disassembly_info).restype, amd_comgr_create_disassembly_info.argtypes = amd_comgr_status_t, [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(uint64_t, uint64_t, ctypes.POINTER(ctypes.c_char), uint64_t, ctypes.c_void_p), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p), ctypes.CFUNCTYPE(None, uint64_t, ctypes.c_void_p), ctypes.POINTER(amd_comgr_disassembly_info_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_destroy_disassembly_info(amd_comgr_disassembly_info_t disassembly_info) +try: (amd_comgr_destroy_disassembly_info:=dll.amd_comgr_destroy_disassembly_info).restype, amd_comgr_destroy_disassembly_info.argtypes = amd_comgr_status_t, [amd_comgr_disassembly_info_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_disassemble_instruction(amd_comgr_disassembly_info_t disassembly_info, uint64_t address, void *user_data, uint64_t *size) +try: (amd_comgr_disassemble_instruction:=dll.amd_comgr_disassemble_instruction).restype, amd_comgr_disassemble_instruction.argtypes = amd_comgr_status_t, [amd_comgr_disassembly_info_t, uint64_t, ctypes.c_void_p, ctypes.POINTER(uint64_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_demangle_symbol_name(amd_comgr_data_t mangled_symbol_name, amd_comgr_data_t *demangled_symbol_name) +try: (amd_comgr_demangle_symbol_name:=dll.amd_comgr_demangle_symbol_name).restype, amd_comgr_demangle_symbol_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_populate_mangled_names(amd_comgr_data_t data, size_t *count) +try: (amd_comgr_populate_mangled_names:=dll.amd_comgr_populate_mangled_names).restype, amd_comgr_populate_mangled_names.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_get_mangled_name(amd_comgr_data_t data, size_t index, size_t *size, char *mangled_name) +try: (amd_comgr_get_mangled_name:=dll.amd_comgr_get_mangled_name).restype, amd_comgr_get_mangled_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, size_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_populate_name_expression_map(amd_comgr_data_t data, size_t *count) +try: (amd_comgr_populate_name_expression_map:=dll.amd_comgr_populate_name_expression_map).restype, amd_comgr_populate_name_expression_map.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_map_name_expression_to_symbol_name(amd_comgr_data_t data, size_t *size, char *name_expression, char *symbol_name) +try: (amd_comgr_map_name_expression_to_symbol_name:=dll.amd_comgr_map_name_expression_to_symbol_name).restype, amd_comgr_map_name_expression_to_symbol_name.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class code_object_info_s(Struct): pass +code_object_info_s._fields_ = [ + ('isa', ctypes.POINTER(ctypes.c_char)), + ('size', size_t), + ('offset', uint64_t), +] +amd_comgr_code_object_info_t = code_object_info_s +# amd_comgr_status_t amd_comgr_lookup_code_object(amd_comgr_data_t data, amd_comgr_code_object_info_t *info_list, size_t info_list_size) +try: (amd_comgr_lookup_code_object:=dll.amd_comgr_lookup_code_object).restype, amd_comgr_lookup_code_object.argtypes = amd_comgr_status_t, [amd_comgr_data_t, ctypes.POINTER(amd_comgr_code_object_info_t), size_t] +except AttributeError: pass + +# amd_comgr_status_t amd_comgr_map_elf_virtual_address_to_code_object_offset(amd_comgr_data_t data, uint64_t elf_virtual_address, uint64_t *code_object_offset, uint64_t *slice_size, bool *nobits) +try: (amd_comgr_map_elf_virtual_address_to_code_object_offset:=dll.amd_comgr_map_elf_virtual_address_to_code_object_offset).restype, amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = amd_comgr_status_t, [amd_comgr_data_t, uint64_t, ctypes.POINTER(uint64_t), ctypes.POINTER(uint64_t), ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +AMD_COMGR_DEPRECATED = lambda msg: __attribute__((deprecated(msg))) +AMD_COMGR_INTERFACE_VERSION_MAJOR = 3 +AMD_COMGR_INTERFACE_VERSION_MINOR = 0 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/cuda.py b/tinygrad/runtime/autogen/cuda.py index c29d6af34d..b1d22f808f 100644 --- a/tinygrad/runtime/autogen/cuda.py +++ b/tinygrad/runtime/autogen/cuda.py @@ -1,154 +1,13 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__CUDA_API_VERSION_INTERNAL'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libcuda.so'] = ctypes.CDLL(ctypes.util.find_library('cuda')) - +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(find_library('cuda'))) + except: pass + return None +dll = dll() cuuint32_t = ctypes.c_uint32 cuuint64_t = ctypes.c_uint64 @@ -156,7539 +15,3923 @@ CUdeviceptr_v2 = ctypes.c_uint64 CUdeviceptr = ctypes.c_uint64 CUdevice_v1 = ctypes.c_int32 CUdevice = ctypes.c_int32 -class struct_CUctx_st(Structure): - pass - +class struct_CUctx_st(Struct): pass CUcontext = ctypes.POINTER(struct_CUctx_st) -class struct_CUmod_st(Structure): - pass - +class struct_CUmod_st(Struct): pass CUmodule = ctypes.POINTER(struct_CUmod_st) -class struct_CUfunc_st(Structure): - pass - +class struct_CUfunc_st(Struct): pass CUfunction = ctypes.POINTER(struct_CUfunc_st) -class struct_CUlib_st(Structure): - pass - +class struct_CUlib_st(Struct): pass CUlibrary = ctypes.POINTER(struct_CUlib_st) -class struct_CUkern_st(Structure): - pass - +class struct_CUkern_st(Struct): pass CUkernel = ctypes.POINTER(struct_CUkern_st) -class struct_CUarray_st(Structure): - pass - +class struct_CUarray_st(Struct): pass CUarray = ctypes.POINTER(struct_CUarray_st) -class struct_CUmipmappedArray_st(Structure): - pass - +class struct_CUmipmappedArray_st(Struct): pass CUmipmappedArray = ctypes.POINTER(struct_CUmipmappedArray_st) -class struct_CUtexref_st(Structure): - pass - +class struct_CUtexref_st(Struct): pass CUtexref = ctypes.POINTER(struct_CUtexref_st) -class struct_CUsurfref_st(Structure): - pass - +class struct_CUsurfref_st(Struct): pass CUsurfref = ctypes.POINTER(struct_CUsurfref_st) -class struct_CUevent_st(Structure): - pass - +class struct_CUevent_st(Struct): pass CUevent = ctypes.POINTER(struct_CUevent_st) -class struct_CUstream_st(Structure): - pass - +class struct_CUstream_st(Struct): pass CUstream = ctypes.POINTER(struct_CUstream_st) -class struct_CUgraphicsResource_st(Structure): - pass - +class struct_CUgraphicsResource_st(Struct): pass CUgraphicsResource = ctypes.POINTER(struct_CUgraphicsResource_st) CUtexObject_v1 = ctypes.c_uint64 CUtexObject = ctypes.c_uint64 CUsurfObject_v1 = ctypes.c_uint64 CUsurfObject = ctypes.c_uint64 -class struct_CUextMemory_st(Structure): - pass - +class struct_CUextMemory_st(Struct): pass CUexternalMemory = ctypes.POINTER(struct_CUextMemory_st) -class struct_CUextSemaphore_st(Structure): - pass - +class struct_CUextSemaphore_st(Struct): pass CUexternalSemaphore = ctypes.POINTER(struct_CUextSemaphore_st) -class struct_CUgraph_st(Structure): - pass - +class struct_CUgraph_st(Struct): pass CUgraph = ctypes.POINTER(struct_CUgraph_st) -class struct_CUgraphNode_st(Structure): - pass - +class struct_CUgraphNode_st(Struct): pass CUgraphNode = ctypes.POINTER(struct_CUgraphNode_st) -class struct_CUgraphExec_st(Structure): - pass - +class struct_CUgraphExec_st(Struct): pass CUgraphExec = ctypes.POINTER(struct_CUgraphExec_st) -class struct_CUmemPoolHandle_st(Structure): - pass - +class struct_CUmemPoolHandle_st(Struct): pass CUmemoryPool = ctypes.POINTER(struct_CUmemPoolHandle_st) -class struct_CUuserObject_st(Structure): - pass - +class struct_CUuserObject_st(Struct): pass CUuserObject = ctypes.POINTER(struct_CUuserObject_st) -class struct_CUuuid_st(Structure): - pass - -struct_CUuuid_st._pack_ = 1 # source:False +class struct_CUuuid_st(Struct): pass struct_CUuuid_st._fields_ = [ - ('bytes', ctypes.c_char * 16), + ('bytes', (ctypes.c_char * 16)), ] - CUuuid = struct_CUuuid_st -class struct_CUipcEventHandle_st(Structure): - pass - -struct_CUipcEventHandle_st._pack_ = 1 # source:False +class struct_CUipcEventHandle_st(Struct): pass struct_CUipcEventHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), + ('reserved', (ctypes.c_char * 64)), ] - CUipcEventHandle_v1 = struct_CUipcEventHandle_st CUipcEventHandle = struct_CUipcEventHandle_st -class struct_CUipcMemHandle_st(Structure): - pass - -struct_CUipcMemHandle_st._pack_ = 1 # source:False +class struct_CUipcMemHandle_st(Struct): pass struct_CUipcMemHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), + ('reserved', (ctypes.c_char * 64)), ] - CUipcMemHandle_v1 = struct_CUipcMemHandle_st CUipcMemHandle = struct_CUipcMemHandle_st +enum_CUipcMem_flags_enum = CEnum(ctypes.c_uint32) +CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS = enum_CUipcMem_flags_enum.define('CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS', 1) -# values for enumeration 'CUipcMem_flags_enum' -CUipcMem_flags_enum__enumvalues = { - 1: 'CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS', -} -CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS = 1 -CUipcMem_flags_enum = ctypes.c_uint32 # enum -CUipcMem_flags = CUipcMem_flags_enum -CUipcMem_flags__enumvalues = CUipcMem_flags_enum__enumvalues +CUipcMem_flags = enum_CUipcMem_flags_enum +enum_CUmemAttach_flags_enum = CEnum(ctypes.c_uint32) +CU_MEM_ATTACH_GLOBAL = enum_CUmemAttach_flags_enum.define('CU_MEM_ATTACH_GLOBAL', 1) +CU_MEM_ATTACH_HOST = enum_CUmemAttach_flags_enum.define('CU_MEM_ATTACH_HOST', 2) +CU_MEM_ATTACH_SINGLE = enum_CUmemAttach_flags_enum.define('CU_MEM_ATTACH_SINGLE', 4) -# values for enumeration 'CUmemAttach_flags_enum' -CUmemAttach_flags_enum__enumvalues = { - 1: 'CU_MEM_ATTACH_GLOBAL', - 2: 'CU_MEM_ATTACH_HOST', - 4: 'CU_MEM_ATTACH_SINGLE', -} -CU_MEM_ATTACH_GLOBAL = 1 -CU_MEM_ATTACH_HOST = 2 -CU_MEM_ATTACH_SINGLE = 4 -CUmemAttach_flags_enum = ctypes.c_uint32 # enum -CUmemAttach_flags = CUmemAttach_flags_enum -CUmemAttach_flags__enumvalues = CUmemAttach_flags_enum__enumvalues +CUmemAttach_flags = enum_CUmemAttach_flags_enum +enum_CUctx_flags_enum = CEnum(ctypes.c_uint32) +CU_CTX_SCHED_AUTO = enum_CUctx_flags_enum.define('CU_CTX_SCHED_AUTO', 0) +CU_CTX_SCHED_SPIN = enum_CUctx_flags_enum.define('CU_CTX_SCHED_SPIN', 1) +CU_CTX_SCHED_YIELD = enum_CUctx_flags_enum.define('CU_CTX_SCHED_YIELD', 2) +CU_CTX_SCHED_BLOCKING_SYNC = enum_CUctx_flags_enum.define('CU_CTX_SCHED_BLOCKING_SYNC', 4) +CU_CTX_BLOCKING_SYNC = enum_CUctx_flags_enum.define('CU_CTX_BLOCKING_SYNC', 4) +CU_CTX_SCHED_MASK = enum_CUctx_flags_enum.define('CU_CTX_SCHED_MASK', 7) +CU_CTX_MAP_HOST = enum_CUctx_flags_enum.define('CU_CTX_MAP_HOST', 8) +CU_CTX_LMEM_RESIZE_TO_MAX = enum_CUctx_flags_enum.define('CU_CTX_LMEM_RESIZE_TO_MAX', 16) +CU_CTX_FLAGS_MASK = enum_CUctx_flags_enum.define('CU_CTX_FLAGS_MASK', 31) -# values for enumeration 'CUctx_flags_enum' -CUctx_flags_enum__enumvalues = { - 0: 'CU_CTX_SCHED_AUTO', - 1: 'CU_CTX_SCHED_SPIN', - 2: 'CU_CTX_SCHED_YIELD', - 4: 'CU_CTX_SCHED_BLOCKING_SYNC', - 4: 'CU_CTX_BLOCKING_SYNC', - 7: 'CU_CTX_SCHED_MASK', - 8: 'CU_CTX_MAP_HOST', - 16: 'CU_CTX_LMEM_RESIZE_TO_MAX', - 31: 'CU_CTX_FLAGS_MASK', -} -CU_CTX_SCHED_AUTO = 0 -CU_CTX_SCHED_SPIN = 1 -CU_CTX_SCHED_YIELD = 2 -CU_CTX_SCHED_BLOCKING_SYNC = 4 -CU_CTX_BLOCKING_SYNC = 4 -CU_CTX_SCHED_MASK = 7 -CU_CTX_MAP_HOST = 8 -CU_CTX_LMEM_RESIZE_TO_MAX = 16 -CU_CTX_FLAGS_MASK = 31 -CUctx_flags_enum = ctypes.c_uint32 # enum -CUctx_flags = CUctx_flags_enum -CUctx_flags__enumvalues = CUctx_flags_enum__enumvalues +CUctx_flags = enum_CUctx_flags_enum +enum_CUevent_sched_flags_enum = CEnum(ctypes.c_uint32) +CU_EVENT_SCHED_AUTO = enum_CUevent_sched_flags_enum.define('CU_EVENT_SCHED_AUTO', 0) +CU_EVENT_SCHED_SPIN = enum_CUevent_sched_flags_enum.define('CU_EVENT_SCHED_SPIN', 1) +CU_EVENT_SCHED_YIELD = enum_CUevent_sched_flags_enum.define('CU_EVENT_SCHED_YIELD', 2) +CU_EVENT_SCHED_BLOCKING_SYNC = enum_CUevent_sched_flags_enum.define('CU_EVENT_SCHED_BLOCKING_SYNC', 4) -# values for enumeration 'CUevent_sched_flags_enum' -CUevent_sched_flags_enum__enumvalues = { - 0: 'CU_EVENT_SCHED_AUTO', - 1: 'CU_EVENT_SCHED_SPIN', - 2: 'CU_EVENT_SCHED_YIELD', - 4: 'CU_EVENT_SCHED_BLOCKING_SYNC', -} -CU_EVENT_SCHED_AUTO = 0 -CU_EVENT_SCHED_SPIN = 1 -CU_EVENT_SCHED_YIELD = 2 -CU_EVENT_SCHED_BLOCKING_SYNC = 4 -CUevent_sched_flags_enum = ctypes.c_uint32 # enum -CUevent_sched_flags = CUevent_sched_flags_enum -CUevent_sched_flags__enumvalues = CUevent_sched_flags_enum__enumvalues +CUevent_sched_flags = enum_CUevent_sched_flags_enum +enum_cl_event_flags_enum = CEnum(ctypes.c_uint32) +NVCL_EVENT_SCHED_AUTO = enum_cl_event_flags_enum.define('NVCL_EVENT_SCHED_AUTO', 0) +NVCL_EVENT_SCHED_SPIN = enum_cl_event_flags_enum.define('NVCL_EVENT_SCHED_SPIN', 1) +NVCL_EVENT_SCHED_YIELD = enum_cl_event_flags_enum.define('NVCL_EVENT_SCHED_YIELD', 2) +NVCL_EVENT_SCHED_BLOCKING_SYNC = enum_cl_event_flags_enum.define('NVCL_EVENT_SCHED_BLOCKING_SYNC', 4) -# values for enumeration 'cl_event_flags_enum' -cl_event_flags_enum__enumvalues = { - 0: 'NVCL_EVENT_SCHED_AUTO', - 1: 'NVCL_EVENT_SCHED_SPIN', - 2: 'NVCL_EVENT_SCHED_YIELD', - 4: 'NVCL_EVENT_SCHED_BLOCKING_SYNC', -} -NVCL_EVENT_SCHED_AUTO = 0 -NVCL_EVENT_SCHED_SPIN = 1 -NVCL_EVENT_SCHED_YIELD = 2 -NVCL_EVENT_SCHED_BLOCKING_SYNC = 4 -cl_event_flags_enum = ctypes.c_uint32 # enum -cl_event_flags = cl_event_flags_enum -cl_event_flags__enumvalues = cl_event_flags_enum__enumvalues +cl_event_flags = enum_cl_event_flags_enum +enum_cl_context_flags_enum = CEnum(ctypes.c_uint32) +NVCL_CTX_SCHED_AUTO = enum_cl_context_flags_enum.define('NVCL_CTX_SCHED_AUTO', 0) +NVCL_CTX_SCHED_SPIN = enum_cl_context_flags_enum.define('NVCL_CTX_SCHED_SPIN', 1) +NVCL_CTX_SCHED_YIELD = enum_cl_context_flags_enum.define('NVCL_CTX_SCHED_YIELD', 2) +NVCL_CTX_SCHED_BLOCKING_SYNC = enum_cl_context_flags_enum.define('NVCL_CTX_SCHED_BLOCKING_SYNC', 4) -# values for enumeration 'cl_context_flags_enum' -cl_context_flags_enum__enumvalues = { - 0: 'NVCL_CTX_SCHED_AUTO', - 1: 'NVCL_CTX_SCHED_SPIN', - 2: 'NVCL_CTX_SCHED_YIELD', - 4: 'NVCL_CTX_SCHED_BLOCKING_SYNC', -} -NVCL_CTX_SCHED_AUTO = 0 -NVCL_CTX_SCHED_SPIN = 1 -NVCL_CTX_SCHED_YIELD = 2 -NVCL_CTX_SCHED_BLOCKING_SYNC = 4 -cl_context_flags_enum = ctypes.c_uint32 # enum -cl_context_flags = cl_context_flags_enum -cl_context_flags__enumvalues = cl_context_flags_enum__enumvalues +cl_context_flags = enum_cl_context_flags_enum +enum_CUstream_flags_enum = CEnum(ctypes.c_uint32) +CU_STREAM_DEFAULT = enum_CUstream_flags_enum.define('CU_STREAM_DEFAULT', 0) +CU_STREAM_NON_BLOCKING = enum_CUstream_flags_enum.define('CU_STREAM_NON_BLOCKING', 1) -# values for enumeration 'CUstream_flags_enum' -CUstream_flags_enum__enumvalues = { - 0: 'CU_STREAM_DEFAULT', - 1: 'CU_STREAM_NON_BLOCKING', -} -CU_STREAM_DEFAULT = 0 -CU_STREAM_NON_BLOCKING = 1 -CUstream_flags_enum = ctypes.c_uint32 # enum -CUstream_flags = CUstream_flags_enum -CUstream_flags__enumvalues = CUstream_flags_enum__enumvalues +CUstream_flags = enum_CUstream_flags_enum +enum_CUevent_flags_enum = CEnum(ctypes.c_uint32) +CU_EVENT_DEFAULT = enum_CUevent_flags_enum.define('CU_EVENT_DEFAULT', 0) +CU_EVENT_BLOCKING_SYNC = enum_CUevent_flags_enum.define('CU_EVENT_BLOCKING_SYNC', 1) +CU_EVENT_DISABLE_TIMING = enum_CUevent_flags_enum.define('CU_EVENT_DISABLE_TIMING', 2) +CU_EVENT_INTERPROCESS = enum_CUevent_flags_enum.define('CU_EVENT_INTERPROCESS', 4) -# values for enumeration 'CUevent_flags_enum' -CUevent_flags_enum__enumvalues = { - 0: 'CU_EVENT_DEFAULT', - 1: 'CU_EVENT_BLOCKING_SYNC', - 2: 'CU_EVENT_DISABLE_TIMING', - 4: 'CU_EVENT_INTERPROCESS', -} -CU_EVENT_DEFAULT = 0 -CU_EVENT_BLOCKING_SYNC = 1 -CU_EVENT_DISABLE_TIMING = 2 -CU_EVENT_INTERPROCESS = 4 -CUevent_flags_enum = ctypes.c_uint32 # enum -CUevent_flags = CUevent_flags_enum -CUevent_flags__enumvalues = CUevent_flags_enum__enumvalues +CUevent_flags = enum_CUevent_flags_enum +enum_CUevent_record_flags_enum = CEnum(ctypes.c_uint32) +CU_EVENT_RECORD_DEFAULT = enum_CUevent_record_flags_enum.define('CU_EVENT_RECORD_DEFAULT', 0) +CU_EVENT_RECORD_EXTERNAL = enum_CUevent_record_flags_enum.define('CU_EVENT_RECORD_EXTERNAL', 1) -# values for enumeration 'CUevent_record_flags_enum' -CUevent_record_flags_enum__enumvalues = { - 0: 'CU_EVENT_RECORD_DEFAULT', - 1: 'CU_EVENT_RECORD_EXTERNAL', -} -CU_EVENT_RECORD_DEFAULT = 0 -CU_EVENT_RECORD_EXTERNAL = 1 -CUevent_record_flags_enum = ctypes.c_uint32 # enum -CUevent_record_flags = CUevent_record_flags_enum -CUevent_record_flags__enumvalues = CUevent_record_flags_enum__enumvalues +CUevent_record_flags = enum_CUevent_record_flags_enum +enum_CUevent_wait_flags_enum = CEnum(ctypes.c_uint32) +CU_EVENT_WAIT_DEFAULT = enum_CUevent_wait_flags_enum.define('CU_EVENT_WAIT_DEFAULT', 0) +CU_EVENT_WAIT_EXTERNAL = enum_CUevent_wait_flags_enum.define('CU_EVENT_WAIT_EXTERNAL', 1) -# values for enumeration 'CUevent_wait_flags_enum' -CUevent_wait_flags_enum__enumvalues = { - 0: 'CU_EVENT_WAIT_DEFAULT', - 1: 'CU_EVENT_WAIT_EXTERNAL', -} -CU_EVENT_WAIT_DEFAULT = 0 -CU_EVENT_WAIT_EXTERNAL = 1 -CUevent_wait_flags_enum = ctypes.c_uint32 # enum -CUevent_wait_flags = CUevent_wait_flags_enum -CUevent_wait_flags__enumvalues = CUevent_wait_flags_enum__enumvalues +CUevent_wait_flags = enum_CUevent_wait_flags_enum +enum_CUstreamWaitValue_flags_enum = CEnum(ctypes.c_uint32) +CU_STREAM_WAIT_VALUE_GEQ = enum_CUstreamWaitValue_flags_enum.define('CU_STREAM_WAIT_VALUE_GEQ', 0) +CU_STREAM_WAIT_VALUE_EQ = enum_CUstreamWaitValue_flags_enum.define('CU_STREAM_WAIT_VALUE_EQ', 1) +CU_STREAM_WAIT_VALUE_AND = enum_CUstreamWaitValue_flags_enum.define('CU_STREAM_WAIT_VALUE_AND', 2) +CU_STREAM_WAIT_VALUE_NOR = enum_CUstreamWaitValue_flags_enum.define('CU_STREAM_WAIT_VALUE_NOR', 3) +CU_STREAM_WAIT_VALUE_FLUSH = enum_CUstreamWaitValue_flags_enum.define('CU_STREAM_WAIT_VALUE_FLUSH', 1073741824) -# values for enumeration 'CUstreamWaitValue_flags_enum' -CUstreamWaitValue_flags_enum__enumvalues = { - 0: 'CU_STREAM_WAIT_VALUE_GEQ', - 1: 'CU_STREAM_WAIT_VALUE_EQ', - 2: 'CU_STREAM_WAIT_VALUE_AND', - 3: 'CU_STREAM_WAIT_VALUE_NOR', - 1073741824: 'CU_STREAM_WAIT_VALUE_FLUSH', -} -CU_STREAM_WAIT_VALUE_GEQ = 0 -CU_STREAM_WAIT_VALUE_EQ = 1 -CU_STREAM_WAIT_VALUE_AND = 2 -CU_STREAM_WAIT_VALUE_NOR = 3 -CU_STREAM_WAIT_VALUE_FLUSH = 1073741824 -CUstreamWaitValue_flags_enum = ctypes.c_uint32 # enum -CUstreamWaitValue_flags = CUstreamWaitValue_flags_enum -CUstreamWaitValue_flags__enumvalues = CUstreamWaitValue_flags_enum__enumvalues +CUstreamWaitValue_flags = enum_CUstreamWaitValue_flags_enum +enum_CUstreamWriteValue_flags_enum = CEnum(ctypes.c_uint32) +CU_STREAM_WRITE_VALUE_DEFAULT = enum_CUstreamWriteValue_flags_enum.define('CU_STREAM_WRITE_VALUE_DEFAULT', 0) +CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER = enum_CUstreamWriteValue_flags_enum.define('CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER', 1) -# values for enumeration 'CUstreamWriteValue_flags_enum' -CUstreamWriteValue_flags_enum__enumvalues = { - 0: 'CU_STREAM_WRITE_VALUE_DEFAULT', - 1: 'CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER', -} -CU_STREAM_WRITE_VALUE_DEFAULT = 0 -CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER = 1 -CUstreamWriteValue_flags_enum = ctypes.c_uint32 # enum -CUstreamWriteValue_flags = CUstreamWriteValue_flags_enum -CUstreamWriteValue_flags__enumvalues = CUstreamWriteValue_flags_enum__enumvalues +CUstreamWriteValue_flags = enum_CUstreamWriteValue_flags_enum +enum_CUstreamBatchMemOpType_enum = CEnum(ctypes.c_uint32) +CU_STREAM_MEM_OP_WAIT_VALUE_32 = enum_CUstreamBatchMemOpType_enum.define('CU_STREAM_MEM_OP_WAIT_VALUE_32', 1) +CU_STREAM_MEM_OP_WRITE_VALUE_32 = enum_CUstreamBatchMemOpType_enum.define('CU_STREAM_MEM_OP_WRITE_VALUE_32', 2) +CU_STREAM_MEM_OP_WAIT_VALUE_64 = enum_CUstreamBatchMemOpType_enum.define('CU_STREAM_MEM_OP_WAIT_VALUE_64', 4) +CU_STREAM_MEM_OP_WRITE_VALUE_64 = enum_CUstreamBatchMemOpType_enum.define('CU_STREAM_MEM_OP_WRITE_VALUE_64', 5) +CU_STREAM_MEM_OP_BARRIER = enum_CUstreamBatchMemOpType_enum.define('CU_STREAM_MEM_OP_BARRIER', 6) +CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES = enum_CUstreamBatchMemOpType_enum.define('CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES', 3) -# values for enumeration 'CUstreamBatchMemOpType_enum' -CUstreamBatchMemOpType_enum__enumvalues = { - 1: 'CU_STREAM_MEM_OP_WAIT_VALUE_32', - 2: 'CU_STREAM_MEM_OP_WRITE_VALUE_32', - 4: 'CU_STREAM_MEM_OP_WAIT_VALUE_64', - 5: 'CU_STREAM_MEM_OP_WRITE_VALUE_64', - 6: 'CU_STREAM_MEM_OP_BARRIER', - 3: 'CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES', -} -CU_STREAM_MEM_OP_WAIT_VALUE_32 = 1 -CU_STREAM_MEM_OP_WRITE_VALUE_32 = 2 -CU_STREAM_MEM_OP_WAIT_VALUE_64 = 4 -CU_STREAM_MEM_OP_WRITE_VALUE_64 = 5 -CU_STREAM_MEM_OP_BARRIER = 6 -CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES = 3 -CUstreamBatchMemOpType_enum = ctypes.c_uint32 # enum -CUstreamBatchMemOpType = CUstreamBatchMemOpType_enum -CUstreamBatchMemOpType__enumvalues = CUstreamBatchMemOpType_enum__enumvalues +CUstreamBatchMemOpType = enum_CUstreamBatchMemOpType_enum +enum_CUstreamMemoryBarrier_flags_enum = CEnum(ctypes.c_uint32) +CU_STREAM_MEMORY_BARRIER_TYPE_SYS = enum_CUstreamMemoryBarrier_flags_enum.define('CU_STREAM_MEMORY_BARRIER_TYPE_SYS', 0) +CU_STREAM_MEMORY_BARRIER_TYPE_GPU = enum_CUstreamMemoryBarrier_flags_enum.define('CU_STREAM_MEMORY_BARRIER_TYPE_GPU', 1) -# values for enumeration 'CUstreamMemoryBarrier_flags_enum' -CUstreamMemoryBarrier_flags_enum__enumvalues = { - 0: 'CU_STREAM_MEMORY_BARRIER_TYPE_SYS', - 1: 'CU_STREAM_MEMORY_BARRIER_TYPE_GPU', -} -CU_STREAM_MEMORY_BARRIER_TYPE_SYS = 0 -CU_STREAM_MEMORY_BARRIER_TYPE_GPU = 1 -CUstreamMemoryBarrier_flags_enum = ctypes.c_uint32 # enum -CUstreamMemoryBarrier_flags = CUstreamMemoryBarrier_flags_enum -CUstreamMemoryBarrier_flags__enumvalues = CUstreamMemoryBarrier_flags_enum__enumvalues -class union_CUstreamBatchMemOpParams_union(Union): - pass - -class struct_CUstreamMemOpWaitValueParams_st(Structure): - pass - -class union_CUstreamMemOpWaitValueParams_st_0(Union): - pass - -union_CUstreamMemOpWaitValueParams_st_0._pack_ = 1 # source:False -union_CUstreamMemOpWaitValueParams_st_0._fields_ = [ - ('value', ctypes.c_uint32), - ('value64', ctypes.c_uint64), +CUstreamMemoryBarrier_flags = enum_CUstreamMemoryBarrier_flags_enum +class union_CUstreamBatchMemOpParams_union(ctypes.Union): pass +class struct_CUstreamMemOpWaitValueParams_st(Struct): pass +class struct_CUstreamMemOpWaitValueParams_st_0(ctypes.Union): pass +struct_CUstreamMemOpWaitValueParams_st_0._fields_ = [ + ('value', cuuint32_t), + ('value64', cuuint64_t), ] - -struct_CUstreamMemOpWaitValueParams_st._pack_ = 1 # source:False -struct_CUstreamMemOpWaitValueParams_st._anonymous_ = ('_0',) +struct_CUstreamMemOpWaitValueParams_st._anonymous_ = ['_0'] struct_CUstreamMemOpWaitValueParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('address', ctypes.c_uint64), - ('_0', union_CUstreamMemOpWaitValueParams_st_0), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('alias', ctypes.c_uint64), + ('operation', CUstreamBatchMemOpType), + ('address', CUdeviceptr), + ('_0', struct_CUstreamMemOpWaitValueParams_st_0), + ('flags', ctypes.c_uint32), + ('alias', CUdeviceptr), ] - -class struct_CUstreamMemOpWriteValueParams_st(Structure): - pass - -class union_CUstreamMemOpWriteValueParams_st_0(Union): - pass - -union_CUstreamMemOpWriteValueParams_st_0._pack_ = 1 # source:False -union_CUstreamMemOpWriteValueParams_st_0._fields_ = [ - ('value', ctypes.c_uint32), - ('value64', ctypes.c_uint64), +class struct_CUstreamMemOpWriteValueParams_st(Struct): pass +class struct_CUstreamMemOpWriteValueParams_st_0(ctypes.Union): pass +struct_CUstreamMemOpWriteValueParams_st_0._fields_ = [ + ('value', cuuint32_t), + ('value64', cuuint64_t), ] - -struct_CUstreamMemOpWriteValueParams_st._pack_ = 1 # source:False -struct_CUstreamMemOpWriteValueParams_st._anonymous_ = ('_0',) +struct_CUstreamMemOpWriteValueParams_st._anonymous_ = ['_0'] struct_CUstreamMemOpWriteValueParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('address', ctypes.c_uint64), - ('_0', union_CUstreamMemOpWriteValueParams_st_0), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('alias', ctypes.c_uint64), + ('operation', CUstreamBatchMemOpType), + ('address', CUdeviceptr), + ('_0', struct_CUstreamMemOpWriteValueParams_st_0), + ('flags', ctypes.c_uint32), + ('alias', CUdeviceptr), ] - -class struct_CUstreamMemOpFlushRemoteWritesParams_st(Structure): - pass - -struct_CUstreamMemOpFlushRemoteWritesParams_st._pack_ = 1 # source:False +class struct_CUstreamMemOpFlushRemoteWritesParams_st(Struct): pass struct_CUstreamMemOpFlushRemoteWritesParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('flags', ctypes.c_uint32), + ('operation', CUstreamBatchMemOpType), + ('flags', ctypes.c_uint32), ] - -class struct_CUstreamMemOpMemoryBarrierParams_st(Structure): - pass - -struct_CUstreamMemOpMemoryBarrierParams_st._pack_ = 1 # source:False +class struct_CUstreamMemOpMemoryBarrierParams_st(Struct): pass struct_CUstreamMemOpMemoryBarrierParams_st._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('flags', ctypes.c_uint32), + ('operation', CUstreamBatchMemOpType), + ('flags', ctypes.c_uint32), ] - -union_CUstreamBatchMemOpParams_union._pack_ = 1 # source:False union_CUstreamBatchMemOpParams_union._fields_ = [ - ('operation', CUstreamBatchMemOpType), - ('waitValue', struct_CUstreamMemOpWaitValueParams_st), - ('writeValue', struct_CUstreamMemOpWriteValueParams_st), - ('flushRemoteWrites', struct_CUstreamMemOpFlushRemoteWritesParams_st), - ('memoryBarrier', struct_CUstreamMemOpMemoryBarrierParams_st), - ('pad', ctypes.c_uint64 * 6), + ('operation', CUstreamBatchMemOpType), + ('waitValue', struct_CUstreamMemOpWaitValueParams_st), + ('writeValue', struct_CUstreamMemOpWriteValueParams_st), + ('flushRemoteWrites', struct_CUstreamMemOpFlushRemoteWritesParams_st), + ('memoryBarrier', struct_CUstreamMemOpMemoryBarrierParams_st), + ('pad', (cuuint64_t * 6)), ] - CUstreamBatchMemOpParams_v1 = union_CUstreamBatchMemOpParams_union CUstreamBatchMemOpParams = union_CUstreamBatchMemOpParams_union -class struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st(Struct): pass struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st._fields_ = [ - ('ctx', ctypes.POINTER(struct_CUctx_st)), - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('paramArray', ctypes.POINTER(union_CUstreamBatchMemOpParams_union)), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('ctx', CUcontext), + ('count', ctypes.c_uint32), + ('paramArray', ctypes.POINTER(CUstreamBatchMemOpParams)), + ('flags', ctypes.c_uint32), ] - CUDA_BATCH_MEM_OP_NODE_PARAMS = struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st +enum_CUoccupancy_flags_enum = CEnum(ctypes.c_uint32) +CU_OCCUPANCY_DEFAULT = enum_CUoccupancy_flags_enum.define('CU_OCCUPANCY_DEFAULT', 0) +CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE = enum_CUoccupancy_flags_enum.define('CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE', 1) -# values for enumeration 'CUoccupancy_flags_enum' -CUoccupancy_flags_enum__enumvalues = { - 0: 'CU_OCCUPANCY_DEFAULT', - 1: 'CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE', -} -CU_OCCUPANCY_DEFAULT = 0 -CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE = 1 -CUoccupancy_flags_enum = ctypes.c_uint32 # enum -CUoccupancy_flags = CUoccupancy_flags_enum -CUoccupancy_flags__enumvalues = CUoccupancy_flags_enum__enumvalues +CUoccupancy_flags = enum_CUoccupancy_flags_enum +enum_CUstreamUpdateCaptureDependencies_flags_enum = CEnum(ctypes.c_uint32) +CU_STREAM_ADD_CAPTURE_DEPENDENCIES = enum_CUstreamUpdateCaptureDependencies_flags_enum.define('CU_STREAM_ADD_CAPTURE_DEPENDENCIES', 0) +CU_STREAM_SET_CAPTURE_DEPENDENCIES = enum_CUstreamUpdateCaptureDependencies_flags_enum.define('CU_STREAM_SET_CAPTURE_DEPENDENCIES', 1) -# values for enumeration 'CUstreamUpdateCaptureDependencies_flags_enum' -CUstreamUpdateCaptureDependencies_flags_enum__enumvalues = { - 0: 'CU_STREAM_ADD_CAPTURE_DEPENDENCIES', - 1: 'CU_STREAM_SET_CAPTURE_DEPENDENCIES', -} -CU_STREAM_ADD_CAPTURE_DEPENDENCIES = 0 -CU_STREAM_SET_CAPTURE_DEPENDENCIES = 1 -CUstreamUpdateCaptureDependencies_flags_enum = ctypes.c_uint32 # enum -CUstreamUpdateCaptureDependencies_flags = CUstreamUpdateCaptureDependencies_flags_enum -CUstreamUpdateCaptureDependencies_flags__enumvalues = CUstreamUpdateCaptureDependencies_flags_enum__enumvalues +CUstreamUpdateCaptureDependencies_flags = enum_CUstreamUpdateCaptureDependencies_flags_enum +enum_CUarray_format_enum = CEnum(ctypes.c_uint32) +CU_AD_FORMAT_UNSIGNED_INT8 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNSIGNED_INT8', 1) +CU_AD_FORMAT_UNSIGNED_INT16 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNSIGNED_INT16', 2) +CU_AD_FORMAT_UNSIGNED_INT32 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNSIGNED_INT32', 3) +CU_AD_FORMAT_SIGNED_INT8 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SIGNED_INT8', 8) +CU_AD_FORMAT_SIGNED_INT16 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SIGNED_INT16', 9) +CU_AD_FORMAT_SIGNED_INT32 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SIGNED_INT32', 10) +CU_AD_FORMAT_HALF = enum_CUarray_format_enum.define('CU_AD_FORMAT_HALF', 16) +CU_AD_FORMAT_FLOAT = enum_CUarray_format_enum.define('CU_AD_FORMAT_FLOAT', 32) +CU_AD_FORMAT_NV12 = enum_CUarray_format_enum.define('CU_AD_FORMAT_NV12', 176) +CU_AD_FORMAT_UNORM_INT8X1 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNORM_INT8X1', 192) +CU_AD_FORMAT_UNORM_INT8X2 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNORM_INT8X2', 193) +CU_AD_FORMAT_UNORM_INT8X4 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNORM_INT8X4', 194) +CU_AD_FORMAT_UNORM_INT16X1 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNORM_INT16X1', 195) +CU_AD_FORMAT_UNORM_INT16X2 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNORM_INT16X2', 196) +CU_AD_FORMAT_UNORM_INT16X4 = enum_CUarray_format_enum.define('CU_AD_FORMAT_UNORM_INT16X4', 197) +CU_AD_FORMAT_SNORM_INT8X1 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SNORM_INT8X1', 198) +CU_AD_FORMAT_SNORM_INT8X2 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SNORM_INT8X2', 199) +CU_AD_FORMAT_SNORM_INT8X4 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SNORM_INT8X4', 200) +CU_AD_FORMAT_SNORM_INT16X1 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SNORM_INT16X1', 201) +CU_AD_FORMAT_SNORM_INT16X2 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SNORM_INT16X2', 202) +CU_AD_FORMAT_SNORM_INT16X4 = enum_CUarray_format_enum.define('CU_AD_FORMAT_SNORM_INT16X4', 203) +CU_AD_FORMAT_BC1_UNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC1_UNORM', 145) +CU_AD_FORMAT_BC1_UNORM_SRGB = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC1_UNORM_SRGB', 146) +CU_AD_FORMAT_BC2_UNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC2_UNORM', 147) +CU_AD_FORMAT_BC2_UNORM_SRGB = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC2_UNORM_SRGB', 148) +CU_AD_FORMAT_BC3_UNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC3_UNORM', 149) +CU_AD_FORMAT_BC3_UNORM_SRGB = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC3_UNORM_SRGB', 150) +CU_AD_FORMAT_BC4_UNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC4_UNORM', 151) +CU_AD_FORMAT_BC4_SNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC4_SNORM', 152) +CU_AD_FORMAT_BC5_UNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC5_UNORM', 153) +CU_AD_FORMAT_BC5_SNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC5_SNORM', 154) +CU_AD_FORMAT_BC6H_UF16 = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC6H_UF16', 155) +CU_AD_FORMAT_BC6H_SF16 = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC6H_SF16', 156) +CU_AD_FORMAT_BC7_UNORM = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC7_UNORM', 157) +CU_AD_FORMAT_BC7_UNORM_SRGB = enum_CUarray_format_enum.define('CU_AD_FORMAT_BC7_UNORM_SRGB', 158) -# values for enumeration 'CUarray_format_enum' -CUarray_format_enum__enumvalues = { - 1: 'CU_AD_FORMAT_UNSIGNED_INT8', - 2: 'CU_AD_FORMAT_UNSIGNED_INT16', - 3: 'CU_AD_FORMAT_UNSIGNED_INT32', - 8: 'CU_AD_FORMAT_SIGNED_INT8', - 9: 'CU_AD_FORMAT_SIGNED_INT16', - 10: 'CU_AD_FORMAT_SIGNED_INT32', - 16: 'CU_AD_FORMAT_HALF', - 32: 'CU_AD_FORMAT_FLOAT', - 176: 'CU_AD_FORMAT_NV12', - 192: 'CU_AD_FORMAT_UNORM_INT8X1', - 193: 'CU_AD_FORMAT_UNORM_INT8X2', - 194: 'CU_AD_FORMAT_UNORM_INT8X4', - 195: 'CU_AD_FORMAT_UNORM_INT16X1', - 196: 'CU_AD_FORMAT_UNORM_INT16X2', - 197: 'CU_AD_FORMAT_UNORM_INT16X4', - 198: 'CU_AD_FORMAT_SNORM_INT8X1', - 199: 'CU_AD_FORMAT_SNORM_INT8X2', - 200: 'CU_AD_FORMAT_SNORM_INT8X4', - 201: 'CU_AD_FORMAT_SNORM_INT16X1', - 202: 'CU_AD_FORMAT_SNORM_INT16X2', - 203: 'CU_AD_FORMAT_SNORM_INT16X4', - 145: 'CU_AD_FORMAT_BC1_UNORM', - 146: 'CU_AD_FORMAT_BC1_UNORM_SRGB', - 147: 'CU_AD_FORMAT_BC2_UNORM', - 148: 'CU_AD_FORMAT_BC2_UNORM_SRGB', - 149: 'CU_AD_FORMAT_BC3_UNORM', - 150: 'CU_AD_FORMAT_BC3_UNORM_SRGB', - 151: 'CU_AD_FORMAT_BC4_UNORM', - 152: 'CU_AD_FORMAT_BC4_SNORM', - 153: 'CU_AD_FORMAT_BC5_UNORM', - 154: 'CU_AD_FORMAT_BC5_SNORM', - 155: 'CU_AD_FORMAT_BC6H_UF16', - 156: 'CU_AD_FORMAT_BC6H_SF16', - 157: 'CU_AD_FORMAT_BC7_UNORM', - 158: 'CU_AD_FORMAT_BC7_UNORM_SRGB', -} -CU_AD_FORMAT_UNSIGNED_INT8 = 1 -CU_AD_FORMAT_UNSIGNED_INT16 = 2 -CU_AD_FORMAT_UNSIGNED_INT32 = 3 -CU_AD_FORMAT_SIGNED_INT8 = 8 -CU_AD_FORMAT_SIGNED_INT16 = 9 -CU_AD_FORMAT_SIGNED_INT32 = 10 -CU_AD_FORMAT_HALF = 16 -CU_AD_FORMAT_FLOAT = 32 -CU_AD_FORMAT_NV12 = 176 -CU_AD_FORMAT_UNORM_INT8X1 = 192 -CU_AD_FORMAT_UNORM_INT8X2 = 193 -CU_AD_FORMAT_UNORM_INT8X4 = 194 -CU_AD_FORMAT_UNORM_INT16X1 = 195 -CU_AD_FORMAT_UNORM_INT16X2 = 196 -CU_AD_FORMAT_UNORM_INT16X4 = 197 -CU_AD_FORMAT_SNORM_INT8X1 = 198 -CU_AD_FORMAT_SNORM_INT8X2 = 199 -CU_AD_FORMAT_SNORM_INT8X4 = 200 -CU_AD_FORMAT_SNORM_INT16X1 = 201 -CU_AD_FORMAT_SNORM_INT16X2 = 202 -CU_AD_FORMAT_SNORM_INT16X4 = 203 -CU_AD_FORMAT_BC1_UNORM = 145 -CU_AD_FORMAT_BC1_UNORM_SRGB = 146 -CU_AD_FORMAT_BC2_UNORM = 147 -CU_AD_FORMAT_BC2_UNORM_SRGB = 148 -CU_AD_FORMAT_BC3_UNORM = 149 -CU_AD_FORMAT_BC3_UNORM_SRGB = 150 -CU_AD_FORMAT_BC4_UNORM = 151 -CU_AD_FORMAT_BC4_SNORM = 152 -CU_AD_FORMAT_BC5_UNORM = 153 -CU_AD_FORMAT_BC5_SNORM = 154 -CU_AD_FORMAT_BC6H_UF16 = 155 -CU_AD_FORMAT_BC6H_SF16 = 156 -CU_AD_FORMAT_BC7_UNORM = 157 -CU_AD_FORMAT_BC7_UNORM_SRGB = 158 -CUarray_format_enum = ctypes.c_uint32 # enum -CUarray_format = CUarray_format_enum -CUarray_format__enumvalues = CUarray_format_enum__enumvalues +CUarray_format = enum_CUarray_format_enum +enum_CUaddress_mode_enum = CEnum(ctypes.c_uint32) +CU_TR_ADDRESS_MODE_WRAP = enum_CUaddress_mode_enum.define('CU_TR_ADDRESS_MODE_WRAP', 0) +CU_TR_ADDRESS_MODE_CLAMP = enum_CUaddress_mode_enum.define('CU_TR_ADDRESS_MODE_CLAMP', 1) +CU_TR_ADDRESS_MODE_MIRROR = enum_CUaddress_mode_enum.define('CU_TR_ADDRESS_MODE_MIRROR', 2) +CU_TR_ADDRESS_MODE_BORDER = enum_CUaddress_mode_enum.define('CU_TR_ADDRESS_MODE_BORDER', 3) -# values for enumeration 'CUaddress_mode_enum' -CUaddress_mode_enum__enumvalues = { - 0: 'CU_TR_ADDRESS_MODE_WRAP', - 1: 'CU_TR_ADDRESS_MODE_CLAMP', - 2: 'CU_TR_ADDRESS_MODE_MIRROR', - 3: 'CU_TR_ADDRESS_MODE_BORDER', -} -CU_TR_ADDRESS_MODE_WRAP = 0 -CU_TR_ADDRESS_MODE_CLAMP = 1 -CU_TR_ADDRESS_MODE_MIRROR = 2 -CU_TR_ADDRESS_MODE_BORDER = 3 -CUaddress_mode_enum = ctypes.c_uint32 # enum -CUaddress_mode = CUaddress_mode_enum -CUaddress_mode__enumvalues = CUaddress_mode_enum__enumvalues +CUaddress_mode = enum_CUaddress_mode_enum +enum_CUfilter_mode_enum = CEnum(ctypes.c_uint32) +CU_TR_FILTER_MODE_POINT = enum_CUfilter_mode_enum.define('CU_TR_FILTER_MODE_POINT', 0) +CU_TR_FILTER_MODE_LINEAR = enum_CUfilter_mode_enum.define('CU_TR_FILTER_MODE_LINEAR', 1) -# values for enumeration 'CUfilter_mode_enum' -CUfilter_mode_enum__enumvalues = { - 0: 'CU_TR_FILTER_MODE_POINT', - 1: 'CU_TR_FILTER_MODE_LINEAR', -} -CU_TR_FILTER_MODE_POINT = 0 -CU_TR_FILTER_MODE_LINEAR = 1 -CUfilter_mode_enum = ctypes.c_uint32 # enum -CUfilter_mode = CUfilter_mode_enum -CUfilter_mode__enumvalues = CUfilter_mode_enum__enumvalues +CUfilter_mode = enum_CUfilter_mode_enum +enum_CUdevice_attribute_enum = CEnum(ctypes.c_uint32) +CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK', 1) +CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X', 2) +CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y', 3) +CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z', 4) +CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X', 5) +CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y', 6) +CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z', 7) +CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK', 8) +CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK', 8) +CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY', 9) +CU_DEVICE_ATTRIBUTE_WARP_SIZE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_WARP_SIZE', 10) +CU_DEVICE_ATTRIBUTE_MAX_PITCH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_PITCH', 11) +CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK', 12) +CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK', 12) +CU_DEVICE_ATTRIBUTE_CLOCK_RATE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CLOCK_RATE', 13) +CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT', 14) +CU_DEVICE_ATTRIBUTE_GPU_OVERLAP = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GPU_OVERLAP', 15) +CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT', 16) +CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT', 17) +CU_DEVICE_ATTRIBUTE_INTEGRATED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_INTEGRATED', 18) +CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY', 19) +CU_DEVICE_ATTRIBUTE_COMPUTE_MODE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_COMPUTE_MODE', 20) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH', 21) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH', 22) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT', 23) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH', 24) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT', 25) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH', 26) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH', 27) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT', 28) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS', 29) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH', 27) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT', 28) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES', 29) +CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT', 30) +CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS', 31) +CU_DEVICE_ATTRIBUTE_ECC_ENABLED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_ECC_ENABLED', 32) +CU_DEVICE_ATTRIBUTE_PCI_BUS_ID = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_PCI_BUS_ID', 33) +CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID', 34) +CU_DEVICE_ATTRIBUTE_TCC_DRIVER = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_TCC_DRIVER', 35) +CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE', 36) +CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH', 37) +CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE', 38) +CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR', 39) +CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT', 40) +CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING', 41) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH', 42) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS', 43) +CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER', 44) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH', 45) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT', 46) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE', 47) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE', 48) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE', 49) +CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID', 50) +CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT', 51) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH', 52) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH', 53) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS', 54) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH', 55) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH', 56) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT', 57) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH', 58) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT', 59) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH', 60) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH', 61) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS', 62) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH', 63) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT', 64) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS', 65) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH', 66) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH', 67) +CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS', 68) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH', 69) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH', 70) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT', 71) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH', 72) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH', 73) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT', 74) +CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR', 75) +CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR', 76) +CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH', 77) +CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED', 78) +CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED', 79) +CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED', 80) +CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR', 81) +CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR', 82) +CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY', 83) +CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD', 84) +CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID', 85) +CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED', 86) +CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO', 87) +CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS', 88) +CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS', 89) +CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED', 90) +CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM', 91) +CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1 = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1', 92) +CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1 = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1', 93) +CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1 = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1', 94) +CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH', 95) +CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH', 96) +CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN', 97) +CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES', 98) +CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED', 99) +CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES', 100) +CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST', 101) +CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED', 102) +CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED', 102) +CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED', 103) +CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED', 104) +CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED', 105) +CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR', 106) +CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED', 107) +CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE', 108) +CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE', 109) +CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED', 110) +CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK', 111) +CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED', 112) +CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED', 113) +CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED', 114) +CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED', 115) +CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED', 116) +CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS', 117) +CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING', 118) +CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES', 119) +CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH', 120) +CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED', 121) +CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS', 122) +CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR', 123) +CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED', 124) +CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED', 125) +CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT', 126) +CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED', 127) +CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS', 129) +CU_DEVICE_ATTRIBUTE_MAX = enum_CUdevice_attribute_enum.define('CU_DEVICE_ATTRIBUTE_MAX', 130) -# values for enumeration 'CUdevice_attribute_enum' -CUdevice_attribute_enum__enumvalues = { - 1: 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 2: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X', - 3: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y', - 4: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z', - 5: 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X', - 6: 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y', - 7: 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z', - 8: 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK', - 8: 'CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK', - 9: 'CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY', - 10: 'CU_DEVICE_ATTRIBUTE_WARP_SIZE', - 11: 'CU_DEVICE_ATTRIBUTE_MAX_PITCH', - 12: 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK', - 12: 'CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK', - 13: 'CU_DEVICE_ATTRIBUTE_CLOCK_RATE', - 14: 'CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT', - 15: 'CU_DEVICE_ATTRIBUTE_GPU_OVERLAP', - 16: 'CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT', - 17: 'CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT', - 18: 'CU_DEVICE_ATTRIBUTE_INTEGRATED', - 19: 'CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY', - 20: 'CU_DEVICE_ATTRIBUTE_COMPUTE_MODE', - 21: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH', - 22: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH', - 23: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT', - 24: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH', - 25: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT', - 26: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH', - 27: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH', - 28: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT', - 29: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS', - 27: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH', - 28: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT', - 29: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES', - 30: 'CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT', - 31: 'CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS', - 32: 'CU_DEVICE_ATTRIBUTE_ECC_ENABLED', - 33: 'CU_DEVICE_ATTRIBUTE_PCI_BUS_ID', - 34: 'CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID', - 35: 'CU_DEVICE_ATTRIBUTE_TCC_DRIVER', - 36: 'CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE', - 37: 'CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH', - 38: 'CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE', - 39: 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR', - 40: 'CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT', - 41: 'CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING', - 42: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH', - 43: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS', - 44: 'CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER', - 45: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH', - 46: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT', - 47: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE', - 48: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE', - 49: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE', - 50: 'CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID', - 51: 'CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT', - 52: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH', - 53: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH', - 54: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS', - 55: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH', - 56: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH', - 57: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT', - 58: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH', - 59: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT', - 60: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH', - 61: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH', - 62: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS', - 63: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH', - 64: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT', - 65: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS', - 66: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH', - 67: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH', - 68: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS', - 69: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH', - 70: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH', - 71: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT', - 72: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH', - 73: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH', - 74: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT', - 75: 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR', - 76: 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR', - 77: 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH', - 78: 'CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED', - 79: 'CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED', - 80: 'CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED', - 81: 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR', - 82: 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR', - 83: 'CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY', - 84: 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD', - 85: 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID', - 86: 'CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED', - 87: 'CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO', - 88: 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS', - 89: 'CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS', - 90: 'CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED', - 91: 'CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM', - 92: 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1', - 93: 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1', - 94: 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1', - 95: 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH', - 96: 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH', - 97: 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN', - 98: 'CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES', - 99: 'CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED', - 100: 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES', - 101: 'CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST', - 102: 'CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED', - 102: 'CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED', - 103: 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED', - 104: 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED', - 105: 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED', - 106: 'CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR', - 107: 'CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED', - 108: 'CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE', - 109: 'CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE', - 110: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED', - 111: 'CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK', - 112: 'CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED', - 113: 'CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED', - 114: 'CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED', - 115: 'CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED', - 116: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED', - 117: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS', - 118: 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING', - 119: 'CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES', - 120: 'CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH', - 121: 'CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED', - 122: 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS', - 123: 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR', - 124: 'CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED', - 125: 'CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED', - 126: 'CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT', - 127: 'CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED', - 129: 'CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS', - 130: 'CU_DEVICE_ATTRIBUTE_MAX', -} -CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 1 -CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X = 2 -CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y = 3 -CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z = 4 -CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X = 5 -CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y = 6 -CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z = 7 -CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK = 8 -CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK = 8 -CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY = 9 -CU_DEVICE_ATTRIBUTE_WARP_SIZE = 10 -CU_DEVICE_ATTRIBUTE_MAX_PITCH = 11 -CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK = 12 -CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK = 12 -CU_DEVICE_ATTRIBUTE_CLOCK_RATE = 13 -CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT = 14 -CU_DEVICE_ATTRIBUTE_GPU_OVERLAP = 15 -CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT = 16 -CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT = 17 -CU_DEVICE_ATTRIBUTE_INTEGRATED = 18 -CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY = 19 -CU_DEVICE_ATTRIBUTE_COMPUTE_MODE = 20 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH = 21 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH = 22 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT = 23 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH = 24 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT = 25 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH = 26 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH = 27 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT = 28 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS = 29 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH = 27 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT = 28 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES = 29 -CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT = 30 -CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS = 31 -CU_DEVICE_ATTRIBUTE_ECC_ENABLED = 32 -CU_DEVICE_ATTRIBUTE_PCI_BUS_ID = 33 -CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID = 34 -CU_DEVICE_ATTRIBUTE_TCC_DRIVER = 35 -CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE = 36 -CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH = 37 -CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE = 38 -CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR = 39 -CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT = 40 -CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING = 41 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH = 42 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS = 43 -CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER = 44 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH = 45 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT = 46 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE = 47 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE = 48 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE = 49 -CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID = 50 -CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT = 51 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH = 52 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH = 53 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS = 54 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH = 55 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH = 56 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT = 57 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH = 58 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT = 59 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH = 60 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH = 61 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS = 62 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH = 63 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT = 64 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS = 65 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH = 66 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH = 67 -CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS = 68 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH = 69 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH = 70 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT = 71 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH = 72 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH = 73 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT = 74 -CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR = 75 -CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR = 76 -CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH = 77 -CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED = 78 -CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED = 79 -CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED = 80 -CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR = 81 -CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR = 82 -CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY = 83 -CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD = 84 -CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID = 85 -CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED = 86 -CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO = 87 -CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS = 88 -CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS = 89 -CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED = 90 -CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM = 91 -CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1 = 92 -CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1 = 93 -CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1 = 94 -CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH = 95 -CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH = 96 -CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN = 97 -CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES = 98 -CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED = 99 -CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES = 100 -CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST = 101 -CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED = 102 -CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED = 102 -CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED = 103 -CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED = 104 -CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED = 105 -CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR = 106 -CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED = 107 -CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE = 108 -CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE = 109 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED = 110 -CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK = 111 -CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED = 112 -CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED = 113 -CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED = 114 -CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED = 115 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED = 116 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS = 117 -CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING = 118 -CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES = 119 -CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH = 120 -CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED = 121 -CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS = 122 -CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR = 123 -CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED = 124 -CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED = 125 -CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT = 126 -CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED = 127 -CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS = 129 -CU_DEVICE_ATTRIBUTE_MAX = 130 -CUdevice_attribute_enum = ctypes.c_uint32 # enum -CUdevice_attribute = CUdevice_attribute_enum -CUdevice_attribute__enumvalues = CUdevice_attribute_enum__enumvalues -class struct_CUdevprop_st(Structure): - pass - -struct_CUdevprop_st._pack_ = 1 # source:False +CUdevice_attribute = enum_CUdevice_attribute_enum +class struct_CUdevprop_st(Struct): pass struct_CUdevprop_st._fields_ = [ - ('maxThreadsPerBlock', ctypes.c_int32), - ('maxThreadsDim', ctypes.c_int32 * 3), - ('maxGridSize', ctypes.c_int32 * 3), - ('sharedMemPerBlock', ctypes.c_int32), - ('totalConstantMemory', ctypes.c_int32), - ('SIMDWidth', ctypes.c_int32), - ('memPitch', ctypes.c_int32), - ('regsPerBlock', ctypes.c_int32), - ('clockRate', ctypes.c_int32), - ('textureAlign', ctypes.c_int32), + ('maxThreadsPerBlock', ctypes.c_int32), + ('maxThreadsDim', (ctypes.c_int32 * 3)), + ('maxGridSize', (ctypes.c_int32 * 3)), + ('sharedMemPerBlock', ctypes.c_int32), + ('totalConstantMemory', ctypes.c_int32), + ('SIMDWidth', ctypes.c_int32), + ('memPitch', ctypes.c_int32), + ('regsPerBlock', ctypes.c_int32), + ('clockRate', ctypes.c_int32), + ('textureAlign', ctypes.c_int32), ] - CUdevprop_v1 = struct_CUdevprop_st CUdevprop = struct_CUdevprop_st +enum_CUpointer_attribute_enum = CEnum(ctypes.c_uint32) +CU_POINTER_ATTRIBUTE_CONTEXT = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_CONTEXT', 1) +CU_POINTER_ATTRIBUTE_MEMORY_TYPE = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_MEMORY_TYPE', 2) +CU_POINTER_ATTRIBUTE_DEVICE_POINTER = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_DEVICE_POINTER', 3) +CU_POINTER_ATTRIBUTE_HOST_POINTER = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_HOST_POINTER', 4) +CU_POINTER_ATTRIBUTE_P2P_TOKENS = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_P2P_TOKENS', 5) +CU_POINTER_ATTRIBUTE_SYNC_MEMOPS = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_SYNC_MEMOPS', 6) +CU_POINTER_ATTRIBUTE_BUFFER_ID = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_BUFFER_ID', 7) +CU_POINTER_ATTRIBUTE_IS_MANAGED = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_IS_MANAGED', 8) +CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL', 9) +CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE', 10) +CU_POINTER_ATTRIBUTE_RANGE_START_ADDR = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_RANGE_START_ADDR', 11) +CU_POINTER_ATTRIBUTE_RANGE_SIZE = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_RANGE_SIZE', 12) +CU_POINTER_ATTRIBUTE_MAPPED = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_MAPPED', 13) +CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', 14) +CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', 15) +CU_POINTER_ATTRIBUTE_ACCESS_FLAGS = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_ACCESS_FLAGS', 16) +CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', 17) +CU_POINTER_ATTRIBUTE_MAPPING_SIZE = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_MAPPING_SIZE', 18) +CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR', 19) +CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID = enum_CUpointer_attribute_enum.define('CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID', 20) -# values for enumeration 'CUpointer_attribute_enum' -CUpointer_attribute_enum__enumvalues = { - 1: 'CU_POINTER_ATTRIBUTE_CONTEXT', - 2: 'CU_POINTER_ATTRIBUTE_MEMORY_TYPE', - 3: 'CU_POINTER_ATTRIBUTE_DEVICE_POINTER', - 4: 'CU_POINTER_ATTRIBUTE_HOST_POINTER', - 5: 'CU_POINTER_ATTRIBUTE_P2P_TOKENS', - 6: 'CU_POINTER_ATTRIBUTE_SYNC_MEMOPS', - 7: 'CU_POINTER_ATTRIBUTE_BUFFER_ID', - 8: 'CU_POINTER_ATTRIBUTE_IS_MANAGED', - 9: 'CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 10: 'CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE', - 11: 'CU_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 12: 'CU_POINTER_ATTRIBUTE_RANGE_SIZE', - 13: 'CU_POINTER_ATTRIBUTE_MAPPED', - 14: 'CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 15: 'CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 16: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 17: 'CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', - 18: 'CU_POINTER_ATTRIBUTE_MAPPING_SIZE', - 19: 'CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR', - 20: 'CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID', -} -CU_POINTER_ATTRIBUTE_CONTEXT = 1 -CU_POINTER_ATTRIBUTE_MEMORY_TYPE = 2 -CU_POINTER_ATTRIBUTE_DEVICE_POINTER = 3 -CU_POINTER_ATTRIBUTE_HOST_POINTER = 4 -CU_POINTER_ATTRIBUTE_P2P_TOKENS = 5 -CU_POINTER_ATTRIBUTE_SYNC_MEMOPS = 6 -CU_POINTER_ATTRIBUTE_BUFFER_ID = 7 -CU_POINTER_ATTRIBUTE_IS_MANAGED = 8 -CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL = 9 -CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE = 10 -CU_POINTER_ATTRIBUTE_RANGE_START_ADDR = 11 -CU_POINTER_ATTRIBUTE_RANGE_SIZE = 12 -CU_POINTER_ATTRIBUTE_MAPPED = 13 -CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES = 14 -CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE = 15 -CU_POINTER_ATTRIBUTE_ACCESS_FLAGS = 16 -CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE = 17 -CU_POINTER_ATTRIBUTE_MAPPING_SIZE = 18 -CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR = 19 -CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID = 20 -CUpointer_attribute_enum = ctypes.c_uint32 # enum -CUpointer_attribute = CUpointer_attribute_enum -CUpointer_attribute__enumvalues = CUpointer_attribute_enum__enumvalues +CUpointer_attribute = enum_CUpointer_attribute_enum +enum_CUfunction_attribute_enum = CEnum(ctypes.c_uint32) +CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', 0) +CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', 1) +CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', 2) +CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', 3) +CU_FUNC_ATTRIBUTE_NUM_REGS = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_NUM_REGS', 4) +CU_FUNC_ATTRIBUTE_PTX_VERSION = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_PTX_VERSION', 5) +CU_FUNC_ATTRIBUTE_BINARY_VERSION = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_BINARY_VERSION', 6) +CU_FUNC_ATTRIBUTE_CACHE_MODE_CA = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_CACHE_MODE_CA', 7) +CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', 8) +CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', 9) +CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET', 10) +CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH', 11) +CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT', 12) +CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH', 13) +CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED', 14) +CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', 15) +CU_FUNC_ATTRIBUTE_MAX = enum_CUfunction_attribute_enum.define('CU_FUNC_ATTRIBUTE_MAX', 16) -# values for enumeration 'CUfunction_attribute_enum' -CUfunction_attribute_enum__enumvalues = { - 0: 'CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 1: 'CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', - 2: 'CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 3: 'CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', - 4: 'CU_FUNC_ATTRIBUTE_NUM_REGS', - 5: 'CU_FUNC_ATTRIBUTE_PTX_VERSION', - 6: 'CU_FUNC_ATTRIBUTE_BINARY_VERSION', - 7: 'CU_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 8: 'CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 9: 'CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 10: 'CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET', - 11: 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH', - 12: 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT', - 13: 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH', - 14: 'CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED', - 15: 'CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 16: 'CU_FUNC_ATTRIBUTE_MAX', -} -CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 0 -CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES = 1 -CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES = 2 -CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES = 3 -CU_FUNC_ATTRIBUTE_NUM_REGS = 4 -CU_FUNC_ATTRIBUTE_PTX_VERSION = 5 -CU_FUNC_ATTRIBUTE_BINARY_VERSION = 6 -CU_FUNC_ATTRIBUTE_CACHE_MODE_CA = 7 -CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES = 8 -CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT = 9 -CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET = 10 -CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH = 11 -CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT = 12 -CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH = 13 -CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED = 14 -CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE = 15 -CU_FUNC_ATTRIBUTE_MAX = 16 -CUfunction_attribute_enum = ctypes.c_uint32 # enum -CUfunction_attribute = CUfunction_attribute_enum -CUfunction_attribute__enumvalues = CUfunction_attribute_enum__enumvalues +CUfunction_attribute = enum_CUfunction_attribute_enum +enum_CUfunc_cache_enum = CEnum(ctypes.c_uint32) +CU_FUNC_CACHE_PREFER_NONE = enum_CUfunc_cache_enum.define('CU_FUNC_CACHE_PREFER_NONE', 0) +CU_FUNC_CACHE_PREFER_SHARED = enum_CUfunc_cache_enum.define('CU_FUNC_CACHE_PREFER_SHARED', 1) +CU_FUNC_CACHE_PREFER_L1 = enum_CUfunc_cache_enum.define('CU_FUNC_CACHE_PREFER_L1', 2) +CU_FUNC_CACHE_PREFER_EQUAL = enum_CUfunc_cache_enum.define('CU_FUNC_CACHE_PREFER_EQUAL', 3) -# values for enumeration 'CUfunc_cache_enum' -CUfunc_cache_enum__enumvalues = { - 0: 'CU_FUNC_CACHE_PREFER_NONE', - 1: 'CU_FUNC_CACHE_PREFER_SHARED', - 2: 'CU_FUNC_CACHE_PREFER_L1', - 3: 'CU_FUNC_CACHE_PREFER_EQUAL', -} -CU_FUNC_CACHE_PREFER_NONE = 0 -CU_FUNC_CACHE_PREFER_SHARED = 1 -CU_FUNC_CACHE_PREFER_L1 = 2 -CU_FUNC_CACHE_PREFER_EQUAL = 3 -CUfunc_cache_enum = ctypes.c_uint32 # enum -CUfunc_cache = CUfunc_cache_enum -CUfunc_cache__enumvalues = CUfunc_cache_enum__enumvalues +CUfunc_cache = enum_CUfunc_cache_enum +enum_CUsharedconfig_enum = CEnum(ctypes.c_uint32) +CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE = enum_CUsharedconfig_enum.define('CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE', 0) +CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE = enum_CUsharedconfig_enum.define('CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE', 1) +CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE = enum_CUsharedconfig_enum.define('CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE', 2) -# values for enumeration 'CUsharedconfig_enum' -CUsharedconfig_enum__enumvalues = { - 0: 'CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE', - 1: 'CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE', - 2: 'CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE', -} -CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE = 0 -CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE = 1 -CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE = 2 -CUsharedconfig_enum = ctypes.c_uint32 # enum -CUsharedconfig = CUsharedconfig_enum -CUsharedconfig__enumvalues = CUsharedconfig_enum__enumvalues +CUsharedconfig = enum_CUsharedconfig_enum +enum_CUshared_carveout_enum = CEnum(ctypes.c_int32) +CU_SHAREDMEM_CARVEOUT_DEFAULT = enum_CUshared_carveout_enum.define('CU_SHAREDMEM_CARVEOUT_DEFAULT', -1) +CU_SHAREDMEM_CARVEOUT_MAX_SHARED = enum_CUshared_carveout_enum.define('CU_SHAREDMEM_CARVEOUT_MAX_SHARED', 100) +CU_SHAREDMEM_CARVEOUT_MAX_L1 = enum_CUshared_carveout_enum.define('CU_SHAREDMEM_CARVEOUT_MAX_L1', 0) -# values for enumeration 'CUshared_carveout_enum' -CUshared_carveout_enum__enumvalues = { - -1: 'CU_SHAREDMEM_CARVEOUT_DEFAULT', - 100: 'CU_SHAREDMEM_CARVEOUT_MAX_SHARED', - 0: 'CU_SHAREDMEM_CARVEOUT_MAX_L1', -} -CU_SHAREDMEM_CARVEOUT_DEFAULT = -1 -CU_SHAREDMEM_CARVEOUT_MAX_SHARED = 100 -CU_SHAREDMEM_CARVEOUT_MAX_L1 = 0 -CUshared_carveout_enum = ctypes.c_int32 # enum -CUshared_carveout = CUshared_carveout_enum -CUshared_carveout__enumvalues = CUshared_carveout_enum__enumvalues +CUshared_carveout = enum_CUshared_carveout_enum +enum_CUmemorytype_enum = CEnum(ctypes.c_uint32) +CU_MEMORYTYPE_HOST = enum_CUmemorytype_enum.define('CU_MEMORYTYPE_HOST', 1) +CU_MEMORYTYPE_DEVICE = enum_CUmemorytype_enum.define('CU_MEMORYTYPE_DEVICE', 2) +CU_MEMORYTYPE_ARRAY = enum_CUmemorytype_enum.define('CU_MEMORYTYPE_ARRAY', 3) +CU_MEMORYTYPE_UNIFIED = enum_CUmemorytype_enum.define('CU_MEMORYTYPE_UNIFIED', 4) -# values for enumeration 'CUmemorytype_enum' -CUmemorytype_enum__enumvalues = { - 1: 'CU_MEMORYTYPE_HOST', - 2: 'CU_MEMORYTYPE_DEVICE', - 3: 'CU_MEMORYTYPE_ARRAY', - 4: 'CU_MEMORYTYPE_UNIFIED', -} -CU_MEMORYTYPE_HOST = 1 -CU_MEMORYTYPE_DEVICE = 2 -CU_MEMORYTYPE_ARRAY = 3 -CU_MEMORYTYPE_UNIFIED = 4 -CUmemorytype_enum = ctypes.c_uint32 # enum -CUmemorytype = CUmemorytype_enum -CUmemorytype__enumvalues = CUmemorytype_enum__enumvalues +CUmemorytype = enum_CUmemorytype_enum +enum_CUcomputemode_enum = CEnum(ctypes.c_uint32) +CU_COMPUTEMODE_DEFAULT = enum_CUcomputemode_enum.define('CU_COMPUTEMODE_DEFAULT', 0) +CU_COMPUTEMODE_PROHIBITED = enum_CUcomputemode_enum.define('CU_COMPUTEMODE_PROHIBITED', 2) +CU_COMPUTEMODE_EXCLUSIVE_PROCESS = enum_CUcomputemode_enum.define('CU_COMPUTEMODE_EXCLUSIVE_PROCESS', 3) -# values for enumeration 'CUcomputemode_enum' -CUcomputemode_enum__enumvalues = { - 0: 'CU_COMPUTEMODE_DEFAULT', - 2: 'CU_COMPUTEMODE_PROHIBITED', - 3: 'CU_COMPUTEMODE_EXCLUSIVE_PROCESS', -} -CU_COMPUTEMODE_DEFAULT = 0 -CU_COMPUTEMODE_PROHIBITED = 2 -CU_COMPUTEMODE_EXCLUSIVE_PROCESS = 3 -CUcomputemode_enum = ctypes.c_uint32 # enum -CUcomputemode = CUcomputemode_enum -CUcomputemode__enumvalues = CUcomputemode_enum__enumvalues +CUcomputemode = enum_CUcomputemode_enum +enum_CUmem_advise_enum = CEnum(ctypes.c_uint32) +CU_MEM_ADVISE_SET_READ_MOSTLY = enum_CUmem_advise_enum.define('CU_MEM_ADVISE_SET_READ_MOSTLY', 1) +CU_MEM_ADVISE_UNSET_READ_MOSTLY = enum_CUmem_advise_enum.define('CU_MEM_ADVISE_UNSET_READ_MOSTLY', 2) +CU_MEM_ADVISE_SET_PREFERRED_LOCATION = enum_CUmem_advise_enum.define('CU_MEM_ADVISE_SET_PREFERRED_LOCATION', 3) +CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION = enum_CUmem_advise_enum.define('CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION', 4) +CU_MEM_ADVISE_SET_ACCESSED_BY = enum_CUmem_advise_enum.define('CU_MEM_ADVISE_SET_ACCESSED_BY', 5) +CU_MEM_ADVISE_UNSET_ACCESSED_BY = enum_CUmem_advise_enum.define('CU_MEM_ADVISE_UNSET_ACCESSED_BY', 6) -# values for enumeration 'CUmem_advise_enum' -CUmem_advise_enum__enumvalues = { - 1: 'CU_MEM_ADVISE_SET_READ_MOSTLY', - 2: 'CU_MEM_ADVISE_UNSET_READ_MOSTLY', - 3: 'CU_MEM_ADVISE_SET_PREFERRED_LOCATION', - 4: 'CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION', - 5: 'CU_MEM_ADVISE_SET_ACCESSED_BY', - 6: 'CU_MEM_ADVISE_UNSET_ACCESSED_BY', -} -CU_MEM_ADVISE_SET_READ_MOSTLY = 1 -CU_MEM_ADVISE_UNSET_READ_MOSTLY = 2 -CU_MEM_ADVISE_SET_PREFERRED_LOCATION = 3 -CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION = 4 -CU_MEM_ADVISE_SET_ACCESSED_BY = 5 -CU_MEM_ADVISE_UNSET_ACCESSED_BY = 6 -CUmem_advise_enum = ctypes.c_uint32 # enum -CUmem_advise = CUmem_advise_enum -CUmem_advise__enumvalues = CUmem_advise_enum__enumvalues +CUmem_advise = enum_CUmem_advise_enum +enum_CUmem_range_attribute_enum = CEnum(ctypes.c_uint32) +CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY = enum_CUmem_range_attribute_enum.define('CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY', 1) +CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION = enum_CUmem_range_attribute_enum.define('CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION', 2) +CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY = enum_CUmem_range_attribute_enum.define('CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY', 3) +CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION = enum_CUmem_range_attribute_enum.define('CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION', 4) -# values for enumeration 'CUmem_range_attribute_enum' -CUmem_range_attribute_enum__enumvalues = { - 1: 'CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY', - 2: 'CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION', - 3: 'CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY', - 4: 'CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION', -} -CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY = 1 -CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION = 2 -CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY = 3 -CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION = 4 -CUmem_range_attribute_enum = ctypes.c_uint32 # enum -CUmem_range_attribute = CUmem_range_attribute_enum -CUmem_range_attribute__enumvalues = CUmem_range_attribute_enum__enumvalues +CUmem_range_attribute = enum_CUmem_range_attribute_enum +enum_CUjit_option_enum = CEnum(ctypes.c_uint32) +CU_JIT_MAX_REGISTERS = enum_CUjit_option_enum.define('CU_JIT_MAX_REGISTERS', 0) +CU_JIT_THREADS_PER_BLOCK = enum_CUjit_option_enum.define('CU_JIT_THREADS_PER_BLOCK', 1) +CU_JIT_WALL_TIME = enum_CUjit_option_enum.define('CU_JIT_WALL_TIME', 2) +CU_JIT_INFO_LOG_BUFFER = enum_CUjit_option_enum.define('CU_JIT_INFO_LOG_BUFFER', 3) +CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES = enum_CUjit_option_enum.define('CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES', 4) +CU_JIT_ERROR_LOG_BUFFER = enum_CUjit_option_enum.define('CU_JIT_ERROR_LOG_BUFFER', 5) +CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES = enum_CUjit_option_enum.define('CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', 6) +CU_JIT_OPTIMIZATION_LEVEL = enum_CUjit_option_enum.define('CU_JIT_OPTIMIZATION_LEVEL', 7) +CU_JIT_TARGET_FROM_CUCONTEXT = enum_CUjit_option_enum.define('CU_JIT_TARGET_FROM_CUCONTEXT', 8) +CU_JIT_TARGET = enum_CUjit_option_enum.define('CU_JIT_TARGET', 9) +CU_JIT_FALLBACK_STRATEGY = enum_CUjit_option_enum.define('CU_JIT_FALLBACK_STRATEGY', 10) +CU_JIT_GENERATE_DEBUG_INFO = enum_CUjit_option_enum.define('CU_JIT_GENERATE_DEBUG_INFO', 11) +CU_JIT_LOG_VERBOSE = enum_CUjit_option_enum.define('CU_JIT_LOG_VERBOSE', 12) +CU_JIT_GENERATE_LINE_INFO = enum_CUjit_option_enum.define('CU_JIT_GENERATE_LINE_INFO', 13) +CU_JIT_CACHE_MODE = enum_CUjit_option_enum.define('CU_JIT_CACHE_MODE', 14) +CU_JIT_NEW_SM3X_OPT = enum_CUjit_option_enum.define('CU_JIT_NEW_SM3X_OPT', 15) +CU_JIT_FAST_COMPILE = enum_CUjit_option_enum.define('CU_JIT_FAST_COMPILE', 16) +CU_JIT_GLOBAL_SYMBOL_NAMES = enum_CUjit_option_enum.define('CU_JIT_GLOBAL_SYMBOL_NAMES', 17) +CU_JIT_GLOBAL_SYMBOL_ADDRESSES = enum_CUjit_option_enum.define('CU_JIT_GLOBAL_SYMBOL_ADDRESSES', 18) +CU_JIT_GLOBAL_SYMBOL_COUNT = enum_CUjit_option_enum.define('CU_JIT_GLOBAL_SYMBOL_COUNT', 19) +CU_JIT_LTO = enum_CUjit_option_enum.define('CU_JIT_LTO', 20) +CU_JIT_FTZ = enum_CUjit_option_enum.define('CU_JIT_FTZ', 21) +CU_JIT_PREC_DIV = enum_CUjit_option_enum.define('CU_JIT_PREC_DIV', 22) +CU_JIT_PREC_SQRT = enum_CUjit_option_enum.define('CU_JIT_PREC_SQRT', 23) +CU_JIT_FMA = enum_CUjit_option_enum.define('CU_JIT_FMA', 24) +CU_JIT_REFERENCED_KERNEL_NAMES = enum_CUjit_option_enum.define('CU_JIT_REFERENCED_KERNEL_NAMES', 25) +CU_JIT_REFERENCED_KERNEL_COUNT = enum_CUjit_option_enum.define('CU_JIT_REFERENCED_KERNEL_COUNT', 26) +CU_JIT_REFERENCED_VARIABLE_NAMES = enum_CUjit_option_enum.define('CU_JIT_REFERENCED_VARIABLE_NAMES', 27) +CU_JIT_REFERENCED_VARIABLE_COUNT = enum_CUjit_option_enum.define('CU_JIT_REFERENCED_VARIABLE_COUNT', 28) +CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES = enum_CUjit_option_enum.define('CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES', 29) +CU_JIT_POSITION_INDEPENDENT_CODE = enum_CUjit_option_enum.define('CU_JIT_POSITION_INDEPENDENT_CODE', 30) +CU_JIT_NUM_OPTIONS = enum_CUjit_option_enum.define('CU_JIT_NUM_OPTIONS', 31) -# values for enumeration 'CUjit_option_enum' -CUjit_option_enum__enumvalues = { - 0: 'CU_JIT_MAX_REGISTERS', - 1: 'CU_JIT_THREADS_PER_BLOCK', - 2: 'CU_JIT_WALL_TIME', - 3: 'CU_JIT_INFO_LOG_BUFFER', - 4: 'CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES', - 5: 'CU_JIT_ERROR_LOG_BUFFER', - 6: 'CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', - 7: 'CU_JIT_OPTIMIZATION_LEVEL', - 8: 'CU_JIT_TARGET_FROM_CUCONTEXT', - 9: 'CU_JIT_TARGET', - 10: 'CU_JIT_FALLBACK_STRATEGY', - 11: 'CU_JIT_GENERATE_DEBUG_INFO', - 12: 'CU_JIT_LOG_VERBOSE', - 13: 'CU_JIT_GENERATE_LINE_INFO', - 14: 'CU_JIT_CACHE_MODE', - 15: 'CU_JIT_NEW_SM3X_OPT', - 16: 'CU_JIT_FAST_COMPILE', - 17: 'CU_JIT_GLOBAL_SYMBOL_NAMES', - 18: 'CU_JIT_GLOBAL_SYMBOL_ADDRESSES', - 19: 'CU_JIT_GLOBAL_SYMBOL_COUNT', - 20: 'CU_JIT_LTO', - 21: 'CU_JIT_FTZ', - 22: 'CU_JIT_PREC_DIV', - 23: 'CU_JIT_PREC_SQRT', - 24: 'CU_JIT_FMA', - 25: 'CU_JIT_REFERENCED_KERNEL_NAMES', - 26: 'CU_JIT_REFERENCED_KERNEL_COUNT', - 27: 'CU_JIT_REFERENCED_VARIABLE_NAMES', - 28: 'CU_JIT_REFERENCED_VARIABLE_COUNT', - 29: 'CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES', - 30: 'CU_JIT_POSITION_INDEPENDENT_CODE', - 31: 'CU_JIT_NUM_OPTIONS', -} -CU_JIT_MAX_REGISTERS = 0 -CU_JIT_THREADS_PER_BLOCK = 1 -CU_JIT_WALL_TIME = 2 -CU_JIT_INFO_LOG_BUFFER = 3 -CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES = 4 -CU_JIT_ERROR_LOG_BUFFER = 5 -CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES = 6 -CU_JIT_OPTIMIZATION_LEVEL = 7 -CU_JIT_TARGET_FROM_CUCONTEXT = 8 -CU_JIT_TARGET = 9 -CU_JIT_FALLBACK_STRATEGY = 10 -CU_JIT_GENERATE_DEBUG_INFO = 11 -CU_JIT_LOG_VERBOSE = 12 -CU_JIT_GENERATE_LINE_INFO = 13 -CU_JIT_CACHE_MODE = 14 -CU_JIT_NEW_SM3X_OPT = 15 -CU_JIT_FAST_COMPILE = 16 -CU_JIT_GLOBAL_SYMBOL_NAMES = 17 -CU_JIT_GLOBAL_SYMBOL_ADDRESSES = 18 -CU_JIT_GLOBAL_SYMBOL_COUNT = 19 -CU_JIT_LTO = 20 -CU_JIT_FTZ = 21 -CU_JIT_PREC_DIV = 22 -CU_JIT_PREC_SQRT = 23 -CU_JIT_FMA = 24 -CU_JIT_REFERENCED_KERNEL_NAMES = 25 -CU_JIT_REFERENCED_KERNEL_COUNT = 26 -CU_JIT_REFERENCED_VARIABLE_NAMES = 27 -CU_JIT_REFERENCED_VARIABLE_COUNT = 28 -CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES = 29 -CU_JIT_POSITION_INDEPENDENT_CODE = 30 -CU_JIT_NUM_OPTIONS = 31 -CUjit_option_enum = ctypes.c_uint32 # enum -CUjit_option = CUjit_option_enum -CUjit_option__enumvalues = CUjit_option_enum__enumvalues +CUjit_option = enum_CUjit_option_enum +enum_CUjit_target_enum = CEnum(ctypes.c_uint32) +CU_TARGET_COMPUTE_30 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_30', 30) +CU_TARGET_COMPUTE_32 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_32', 32) +CU_TARGET_COMPUTE_35 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_35', 35) +CU_TARGET_COMPUTE_37 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_37', 37) +CU_TARGET_COMPUTE_50 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_50', 50) +CU_TARGET_COMPUTE_52 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_52', 52) +CU_TARGET_COMPUTE_53 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_53', 53) +CU_TARGET_COMPUTE_60 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_60', 60) +CU_TARGET_COMPUTE_61 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_61', 61) +CU_TARGET_COMPUTE_62 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_62', 62) +CU_TARGET_COMPUTE_70 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_70', 70) +CU_TARGET_COMPUTE_72 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_72', 72) +CU_TARGET_COMPUTE_75 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_75', 75) +CU_TARGET_COMPUTE_80 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_80', 80) +CU_TARGET_COMPUTE_86 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_86', 86) +CU_TARGET_COMPUTE_87 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_87', 87) +CU_TARGET_COMPUTE_89 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_89', 89) +CU_TARGET_COMPUTE_90 = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_90', 90) +CU_TARGET_COMPUTE_90A = enum_CUjit_target_enum.define('CU_TARGET_COMPUTE_90A', 65626) -# values for enumeration 'CUjit_target_enum' -CUjit_target_enum__enumvalues = { - 30: 'CU_TARGET_COMPUTE_30', - 32: 'CU_TARGET_COMPUTE_32', - 35: 'CU_TARGET_COMPUTE_35', - 37: 'CU_TARGET_COMPUTE_37', - 50: 'CU_TARGET_COMPUTE_50', - 52: 'CU_TARGET_COMPUTE_52', - 53: 'CU_TARGET_COMPUTE_53', - 60: 'CU_TARGET_COMPUTE_60', - 61: 'CU_TARGET_COMPUTE_61', - 62: 'CU_TARGET_COMPUTE_62', - 70: 'CU_TARGET_COMPUTE_70', - 72: 'CU_TARGET_COMPUTE_72', - 75: 'CU_TARGET_COMPUTE_75', - 80: 'CU_TARGET_COMPUTE_80', - 86: 'CU_TARGET_COMPUTE_86', - 87: 'CU_TARGET_COMPUTE_87', - 89: 'CU_TARGET_COMPUTE_89', - 90: 'CU_TARGET_COMPUTE_90', - 65626: 'CU_TARGET_COMPUTE_90A', -} -CU_TARGET_COMPUTE_30 = 30 -CU_TARGET_COMPUTE_32 = 32 -CU_TARGET_COMPUTE_35 = 35 -CU_TARGET_COMPUTE_37 = 37 -CU_TARGET_COMPUTE_50 = 50 -CU_TARGET_COMPUTE_52 = 52 -CU_TARGET_COMPUTE_53 = 53 -CU_TARGET_COMPUTE_60 = 60 -CU_TARGET_COMPUTE_61 = 61 -CU_TARGET_COMPUTE_62 = 62 -CU_TARGET_COMPUTE_70 = 70 -CU_TARGET_COMPUTE_72 = 72 -CU_TARGET_COMPUTE_75 = 75 -CU_TARGET_COMPUTE_80 = 80 -CU_TARGET_COMPUTE_86 = 86 -CU_TARGET_COMPUTE_87 = 87 -CU_TARGET_COMPUTE_89 = 89 -CU_TARGET_COMPUTE_90 = 90 -CU_TARGET_COMPUTE_90A = 65626 -CUjit_target_enum = ctypes.c_uint32 # enum -CUjit_target = CUjit_target_enum -CUjit_target__enumvalues = CUjit_target_enum__enumvalues +CUjit_target = enum_CUjit_target_enum +enum_CUjit_fallback_enum = CEnum(ctypes.c_uint32) +CU_PREFER_PTX = enum_CUjit_fallback_enum.define('CU_PREFER_PTX', 0) +CU_PREFER_BINARY = enum_CUjit_fallback_enum.define('CU_PREFER_BINARY', 1) -# values for enumeration 'CUjit_fallback_enum' -CUjit_fallback_enum__enumvalues = { - 0: 'CU_PREFER_PTX', - 1: 'CU_PREFER_BINARY', -} -CU_PREFER_PTX = 0 -CU_PREFER_BINARY = 1 -CUjit_fallback_enum = ctypes.c_uint32 # enum -CUjit_fallback = CUjit_fallback_enum -CUjit_fallback__enumvalues = CUjit_fallback_enum__enumvalues +CUjit_fallback = enum_CUjit_fallback_enum +enum_CUjit_cacheMode_enum = CEnum(ctypes.c_uint32) +CU_JIT_CACHE_OPTION_NONE = enum_CUjit_cacheMode_enum.define('CU_JIT_CACHE_OPTION_NONE', 0) +CU_JIT_CACHE_OPTION_CG = enum_CUjit_cacheMode_enum.define('CU_JIT_CACHE_OPTION_CG', 1) +CU_JIT_CACHE_OPTION_CA = enum_CUjit_cacheMode_enum.define('CU_JIT_CACHE_OPTION_CA', 2) -# values for enumeration 'CUjit_cacheMode_enum' -CUjit_cacheMode_enum__enumvalues = { - 0: 'CU_JIT_CACHE_OPTION_NONE', - 1: 'CU_JIT_CACHE_OPTION_CG', - 2: 'CU_JIT_CACHE_OPTION_CA', -} -CU_JIT_CACHE_OPTION_NONE = 0 -CU_JIT_CACHE_OPTION_CG = 1 -CU_JIT_CACHE_OPTION_CA = 2 -CUjit_cacheMode_enum = ctypes.c_uint32 # enum -CUjit_cacheMode = CUjit_cacheMode_enum -CUjit_cacheMode__enumvalues = CUjit_cacheMode_enum__enumvalues - -# values for enumeration 'CUjitInputType_enum' -CUjitInputType_enum__enumvalues = { - 0: 'CU_JIT_INPUT_CUBIN', - 1: 'CU_JIT_INPUT_PTX', - 2: 'CU_JIT_INPUT_FATBINARY', - 3: 'CU_JIT_INPUT_OBJECT', - 4: 'CU_JIT_INPUT_LIBRARY', - 5: 'CU_JIT_INPUT_NVVM', - 6: 'CU_JIT_NUM_INPUT_TYPES', -} -CU_JIT_INPUT_CUBIN = 0 -CU_JIT_INPUT_PTX = 1 -CU_JIT_INPUT_FATBINARY = 2 -CU_JIT_INPUT_OBJECT = 3 -CU_JIT_INPUT_LIBRARY = 4 -CU_JIT_INPUT_NVVM = 5 -CU_JIT_NUM_INPUT_TYPES = 6 -CUjitInputType_enum = ctypes.c_uint32 # enum -CUjitInputType = CUjitInputType_enum -CUjitInputType__enumvalues = CUjitInputType_enum__enumvalues -class struct_CUlinkState_st(Structure): - pass +CUjit_cacheMode = enum_CUjit_cacheMode_enum +enum_CUjitInputType_enum = CEnum(ctypes.c_uint32) +CU_JIT_INPUT_CUBIN = enum_CUjitInputType_enum.define('CU_JIT_INPUT_CUBIN', 0) +CU_JIT_INPUT_PTX = enum_CUjitInputType_enum.define('CU_JIT_INPUT_PTX', 1) +CU_JIT_INPUT_FATBINARY = enum_CUjitInputType_enum.define('CU_JIT_INPUT_FATBINARY', 2) +CU_JIT_INPUT_OBJECT = enum_CUjitInputType_enum.define('CU_JIT_INPUT_OBJECT', 3) +CU_JIT_INPUT_LIBRARY = enum_CUjitInputType_enum.define('CU_JIT_INPUT_LIBRARY', 4) +CU_JIT_INPUT_NVVM = enum_CUjitInputType_enum.define('CU_JIT_INPUT_NVVM', 5) +CU_JIT_NUM_INPUT_TYPES = enum_CUjitInputType_enum.define('CU_JIT_NUM_INPUT_TYPES', 6) +CUjitInputType = enum_CUjitInputType_enum +class struct_CUlinkState_st(Struct): pass CUlinkState = ctypes.POINTER(struct_CUlinkState_st) +enum_CUgraphicsRegisterFlags_enum = CEnum(ctypes.c_uint32) +CU_GRAPHICS_REGISTER_FLAGS_NONE = enum_CUgraphicsRegisterFlags_enum.define('CU_GRAPHICS_REGISTER_FLAGS_NONE', 0) +CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY = enum_CUgraphicsRegisterFlags_enum.define('CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY', 1) +CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD = enum_CUgraphicsRegisterFlags_enum.define('CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD', 2) +CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST = enum_CUgraphicsRegisterFlags_enum.define('CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST', 4) +CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER = enum_CUgraphicsRegisterFlags_enum.define('CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER', 8) -# values for enumeration 'CUgraphicsRegisterFlags_enum' -CUgraphicsRegisterFlags_enum__enumvalues = { - 0: 'CU_GRAPHICS_REGISTER_FLAGS_NONE', - 1: 'CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY', - 2: 'CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD', - 4: 'CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST', - 8: 'CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER', -} -CU_GRAPHICS_REGISTER_FLAGS_NONE = 0 -CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY = 1 -CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD = 2 -CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST = 4 -CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER = 8 -CUgraphicsRegisterFlags_enum = ctypes.c_uint32 # enum -CUgraphicsRegisterFlags = CUgraphicsRegisterFlags_enum -CUgraphicsRegisterFlags__enumvalues = CUgraphicsRegisterFlags_enum__enumvalues +CUgraphicsRegisterFlags = enum_CUgraphicsRegisterFlags_enum +enum_CUgraphicsMapResourceFlags_enum = CEnum(ctypes.c_uint32) +CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE = enum_CUgraphicsMapResourceFlags_enum.define('CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE', 0) +CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY = enum_CUgraphicsMapResourceFlags_enum.define('CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY', 1) +CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD = enum_CUgraphicsMapResourceFlags_enum.define('CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD', 2) -# values for enumeration 'CUgraphicsMapResourceFlags_enum' -CUgraphicsMapResourceFlags_enum__enumvalues = { - 0: 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE', - 1: 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY', - 2: 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD', -} -CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE = 0 -CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY = 1 -CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD = 2 -CUgraphicsMapResourceFlags_enum = ctypes.c_uint32 # enum -CUgraphicsMapResourceFlags = CUgraphicsMapResourceFlags_enum -CUgraphicsMapResourceFlags__enumvalues = CUgraphicsMapResourceFlags_enum__enumvalues +CUgraphicsMapResourceFlags = enum_CUgraphicsMapResourceFlags_enum +enum_CUarray_cubemap_face_enum = CEnum(ctypes.c_uint32) +CU_CUBEMAP_FACE_POSITIVE_X = enum_CUarray_cubemap_face_enum.define('CU_CUBEMAP_FACE_POSITIVE_X', 0) +CU_CUBEMAP_FACE_NEGATIVE_X = enum_CUarray_cubemap_face_enum.define('CU_CUBEMAP_FACE_NEGATIVE_X', 1) +CU_CUBEMAP_FACE_POSITIVE_Y = enum_CUarray_cubemap_face_enum.define('CU_CUBEMAP_FACE_POSITIVE_Y', 2) +CU_CUBEMAP_FACE_NEGATIVE_Y = enum_CUarray_cubemap_face_enum.define('CU_CUBEMAP_FACE_NEGATIVE_Y', 3) +CU_CUBEMAP_FACE_POSITIVE_Z = enum_CUarray_cubemap_face_enum.define('CU_CUBEMAP_FACE_POSITIVE_Z', 4) +CU_CUBEMAP_FACE_NEGATIVE_Z = enum_CUarray_cubemap_face_enum.define('CU_CUBEMAP_FACE_NEGATIVE_Z', 5) -# values for enumeration 'CUarray_cubemap_face_enum' -CUarray_cubemap_face_enum__enumvalues = { - 0: 'CU_CUBEMAP_FACE_POSITIVE_X', - 1: 'CU_CUBEMAP_FACE_NEGATIVE_X', - 2: 'CU_CUBEMAP_FACE_POSITIVE_Y', - 3: 'CU_CUBEMAP_FACE_NEGATIVE_Y', - 4: 'CU_CUBEMAP_FACE_POSITIVE_Z', - 5: 'CU_CUBEMAP_FACE_NEGATIVE_Z', -} -CU_CUBEMAP_FACE_POSITIVE_X = 0 -CU_CUBEMAP_FACE_NEGATIVE_X = 1 -CU_CUBEMAP_FACE_POSITIVE_Y = 2 -CU_CUBEMAP_FACE_NEGATIVE_Y = 3 -CU_CUBEMAP_FACE_POSITIVE_Z = 4 -CU_CUBEMAP_FACE_NEGATIVE_Z = 5 -CUarray_cubemap_face_enum = ctypes.c_uint32 # enum -CUarray_cubemap_face = CUarray_cubemap_face_enum -CUarray_cubemap_face__enumvalues = CUarray_cubemap_face_enum__enumvalues +CUarray_cubemap_face = enum_CUarray_cubemap_face_enum +enum_CUlimit_enum = CEnum(ctypes.c_uint32) +CU_LIMIT_STACK_SIZE = enum_CUlimit_enum.define('CU_LIMIT_STACK_SIZE', 0) +CU_LIMIT_PRINTF_FIFO_SIZE = enum_CUlimit_enum.define('CU_LIMIT_PRINTF_FIFO_SIZE', 1) +CU_LIMIT_MALLOC_HEAP_SIZE = enum_CUlimit_enum.define('CU_LIMIT_MALLOC_HEAP_SIZE', 2) +CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH = enum_CUlimit_enum.define('CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH', 3) +CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT = enum_CUlimit_enum.define('CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT', 4) +CU_LIMIT_MAX_L2_FETCH_GRANULARITY = enum_CUlimit_enum.define('CU_LIMIT_MAX_L2_FETCH_GRANULARITY', 5) +CU_LIMIT_PERSISTING_L2_CACHE_SIZE = enum_CUlimit_enum.define('CU_LIMIT_PERSISTING_L2_CACHE_SIZE', 6) +CU_LIMIT_MAX = enum_CUlimit_enum.define('CU_LIMIT_MAX', 7) -# values for enumeration 'CUlimit_enum' -CUlimit_enum__enumvalues = { - 0: 'CU_LIMIT_STACK_SIZE', - 1: 'CU_LIMIT_PRINTF_FIFO_SIZE', - 2: 'CU_LIMIT_MALLOC_HEAP_SIZE', - 3: 'CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH', - 4: 'CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT', - 5: 'CU_LIMIT_MAX_L2_FETCH_GRANULARITY', - 6: 'CU_LIMIT_PERSISTING_L2_CACHE_SIZE', - 7: 'CU_LIMIT_MAX', -} -CU_LIMIT_STACK_SIZE = 0 -CU_LIMIT_PRINTF_FIFO_SIZE = 1 -CU_LIMIT_MALLOC_HEAP_SIZE = 2 -CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH = 3 -CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT = 4 -CU_LIMIT_MAX_L2_FETCH_GRANULARITY = 5 -CU_LIMIT_PERSISTING_L2_CACHE_SIZE = 6 -CU_LIMIT_MAX = 7 -CUlimit_enum = ctypes.c_uint32 # enum -CUlimit = CUlimit_enum -CUlimit__enumvalues = CUlimit_enum__enumvalues +CUlimit = enum_CUlimit_enum +enum_CUresourcetype_enum = CEnum(ctypes.c_uint32) +CU_RESOURCE_TYPE_ARRAY = enum_CUresourcetype_enum.define('CU_RESOURCE_TYPE_ARRAY', 0) +CU_RESOURCE_TYPE_MIPMAPPED_ARRAY = enum_CUresourcetype_enum.define('CU_RESOURCE_TYPE_MIPMAPPED_ARRAY', 1) +CU_RESOURCE_TYPE_LINEAR = enum_CUresourcetype_enum.define('CU_RESOURCE_TYPE_LINEAR', 2) +CU_RESOURCE_TYPE_PITCH2D = enum_CUresourcetype_enum.define('CU_RESOURCE_TYPE_PITCH2D', 3) -# values for enumeration 'CUresourcetype_enum' -CUresourcetype_enum__enumvalues = { - 0: 'CU_RESOURCE_TYPE_ARRAY', - 1: 'CU_RESOURCE_TYPE_MIPMAPPED_ARRAY', - 2: 'CU_RESOURCE_TYPE_LINEAR', - 3: 'CU_RESOURCE_TYPE_PITCH2D', -} -CU_RESOURCE_TYPE_ARRAY = 0 -CU_RESOURCE_TYPE_MIPMAPPED_ARRAY = 1 -CU_RESOURCE_TYPE_LINEAR = 2 -CU_RESOURCE_TYPE_PITCH2D = 3 -CUresourcetype_enum = ctypes.c_uint32 # enum -CUresourcetype = CUresourcetype_enum -CUresourcetype__enumvalues = CUresourcetype_enum__enumvalues -CUhostFn = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) +CUresourcetype = enum_CUresourcetype_enum +CUhostFn = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +enum_CUaccessProperty_enum = CEnum(ctypes.c_uint32) +CU_ACCESS_PROPERTY_NORMAL = enum_CUaccessProperty_enum.define('CU_ACCESS_PROPERTY_NORMAL', 0) +CU_ACCESS_PROPERTY_STREAMING = enum_CUaccessProperty_enum.define('CU_ACCESS_PROPERTY_STREAMING', 1) +CU_ACCESS_PROPERTY_PERSISTING = enum_CUaccessProperty_enum.define('CU_ACCESS_PROPERTY_PERSISTING', 2) -# values for enumeration 'CUaccessProperty_enum' -CUaccessProperty_enum__enumvalues = { - 0: 'CU_ACCESS_PROPERTY_NORMAL', - 1: 'CU_ACCESS_PROPERTY_STREAMING', - 2: 'CU_ACCESS_PROPERTY_PERSISTING', -} -CU_ACCESS_PROPERTY_NORMAL = 0 -CU_ACCESS_PROPERTY_STREAMING = 1 -CU_ACCESS_PROPERTY_PERSISTING = 2 -CUaccessProperty_enum = ctypes.c_uint32 # enum -CUaccessProperty = CUaccessProperty_enum -CUaccessProperty__enumvalues = CUaccessProperty_enum__enumvalues -class struct_CUaccessPolicyWindow_st(Structure): - pass - -struct_CUaccessPolicyWindow_st._pack_ = 1 # source:False +CUaccessProperty = enum_CUaccessProperty_enum +class struct_CUaccessPolicyWindow_st(Struct): pass +size_t = ctypes.c_uint64 struct_CUaccessPolicyWindow_st._fields_ = [ - ('base_ptr', ctypes.POINTER(None)), - ('num_bytes', ctypes.c_uint64), - ('hitRatio', ctypes.c_float), - ('hitProp', CUaccessProperty), - ('missProp', CUaccessProperty), - ('PADDING_0', ctypes.c_ubyte * 4), + ('base_ptr', ctypes.c_void_p), + ('num_bytes', size_t), + ('hitRatio', ctypes.c_float), + ('hitProp', CUaccessProperty), + ('missProp', CUaccessProperty), ] - CUaccessPolicyWindow_v1 = struct_CUaccessPolicyWindow_st CUaccessPolicyWindow = struct_CUaccessPolicyWindow_st -class struct_CUDA_KERNEL_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_KERNEL_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_KERNEL_NODE_PARAMS_st(Struct): pass struct_CUDA_KERNEL_NODE_PARAMS_st._fields_ = [ - ('func', ctypes.POINTER(struct_CUfunc_st)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), - ('extra', ctypes.POINTER(ctypes.POINTER(None))), + ('func', CUfunction), + ('gridDimX', ctypes.c_uint32), + ('gridDimY', ctypes.c_uint32), + ('gridDimZ', ctypes.c_uint32), + ('blockDimX', ctypes.c_uint32), + ('blockDimY', ctypes.c_uint32), + ('blockDimZ', ctypes.c_uint32), + ('sharedMemBytes', ctypes.c_uint32), + ('kernelParams', ctypes.POINTER(ctypes.c_void_p)), + ('extra', ctypes.POINTER(ctypes.c_void_p)), ] - CUDA_KERNEL_NODE_PARAMS_v1 = struct_CUDA_KERNEL_NODE_PARAMS_st -class struct_CUDA_KERNEL_NODE_PARAMS_v2_st(Structure): - pass - -struct_CUDA_KERNEL_NODE_PARAMS_v2_st._pack_ = 1 # source:False +class struct_CUDA_KERNEL_NODE_PARAMS_v2_st(Struct): pass struct_CUDA_KERNEL_NODE_PARAMS_v2_st._fields_ = [ - ('func', ctypes.POINTER(struct_CUfunc_st)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), - ('extra', ctypes.POINTER(ctypes.POINTER(None))), - ('kern', ctypes.POINTER(struct_CUkern_st)), - ('ctx', ctypes.POINTER(struct_CUctx_st)), + ('func', CUfunction), + ('gridDimX', ctypes.c_uint32), + ('gridDimY', ctypes.c_uint32), + ('gridDimZ', ctypes.c_uint32), + ('blockDimX', ctypes.c_uint32), + ('blockDimY', ctypes.c_uint32), + ('blockDimZ', ctypes.c_uint32), + ('sharedMemBytes', ctypes.c_uint32), + ('kernelParams', ctypes.POINTER(ctypes.c_void_p)), + ('extra', ctypes.POINTER(ctypes.c_void_p)), + ('kern', CUkernel), + ('ctx', CUcontext), ] - CUDA_KERNEL_NODE_PARAMS_v2 = struct_CUDA_KERNEL_NODE_PARAMS_v2_st CUDA_KERNEL_NODE_PARAMS = struct_CUDA_KERNEL_NODE_PARAMS_v2_st -class struct_CUDA_MEMSET_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_MEMSET_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_MEMSET_NODE_PARAMS_st(Struct): pass struct_CUDA_MEMSET_NODE_PARAMS_st._fields_ = [ - ('dst', ctypes.c_uint64), - ('pitch', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('elementSize', ctypes.c_uint32), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), + ('dst', CUdeviceptr), + ('pitch', size_t), + ('value', ctypes.c_uint32), + ('elementSize', ctypes.c_uint32), + ('width', size_t), + ('height', size_t), ] - CUDA_MEMSET_NODE_PARAMS_v1 = struct_CUDA_MEMSET_NODE_PARAMS_st CUDA_MEMSET_NODE_PARAMS = struct_CUDA_MEMSET_NODE_PARAMS_st -class struct_CUDA_HOST_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_HOST_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_HOST_NODE_PARAMS_st(Struct): pass struct_CUDA_HOST_NODE_PARAMS_st._fields_ = [ - ('fn', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('userData', ctypes.POINTER(None)), + ('fn', CUhostFn), + ('userData', ctypes.c_void_p), ] - CUDA_HOST_NODE_PARAMS_v1 = struct_CUDA_HOST_NODE_PARAMS_st CUDA_HOST_NODE_PARAMS = struct_CUDA_HOST_NODE_PARAMS_st +enum_CUgraphNodeType_enum = CEnum(ctypes.c_uint32) +CU_GRAPH_NODE_TYPE_KERNEL = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_KERNEL', 0) +CU_GRAPH_NODE_TYPE_MEMCPY = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_MEMCPY', 1) +CU_GRAPH_NODE_TYPE_MEMSET = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_MEMSET', 2) +CU_GRAPH_NODE_TYPE_HOST = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_HOST', 3) +CU_GRAPH_NODE_TYPE_GRAPH = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_GRAPH', 4) +CU_GRAPH_NODE_TYPE_EMPTY = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_EMPTY', 5) +CU_GRAPH_NODE_TYPE_WAIT_EVENT = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_WAIT_EVENT', 6) +CU_GRAPH_NODE_TYPE_EVENT_RECORD = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_EVENT_RECORD', 7) +CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL', 8) +CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT', 9) +CU_GRAPH_NODE_TYPE_MEM_ALLOC = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_MEM_ALLOC', 10) +CU_GRAPH_NODE_TYPE_MEM_FREE = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_MEM_FREE', 11) +CU_GRAPH_NODE_TYPE_BATCH_MEM_OP = enum_CUgraphNodeType_enum.define('CU_GRAPH_NODE_TYPE_BATCH_MEM_OP', 12) -# values for enumeration 'CUgraphNodeType_enum' -CUgraphNodeType_enum__enumvalues = { - 0: 'CU_GRAPH_NODE_TYPE_KERNEL', - 1: 'CU_GRAPH_NODE_TYPE_MEMCPY', - 2: 'CU_GRAPH_NODE_TYPE_MEMSET', - 3: 'CU_GRAPH_NODE_TYPE_HOST', - 4: 'CU_GRAPH_NODE_TYPE_GRAPH', - 5: 'CU_GRAPH_NODE_TYPE_EMPTY', - 6: 'CU_GRAPH_NODE_TYPE_WAIT_EVENT', - 7: 'CU_GRAPH_NODE_TYPE_EVENT_RECORD', - 8: 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL', - 9: 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT', - 10: 'CU_GRAPH_NODE_TYPE_MEM_ALLOC', - 11: 'CU_GRAPH_NODE_TYPE_MEM_FREE', - 12: 'CU_GRAPH_NODE_TYPE_BATCH_MEM_OP', -} -CU_GRAPH_NODE_TYPE_KERNEL = 0 -CU_GRAPH_NODE_TYPE_MEMCPY = 1 -CU_GRAPH_NODE_TYPE_MEMSET = 2 -CU_GRAPH_NODE_TYPE_HOST = 3 -CU_GRAPH_NODE_TYPE_GRAPH = 4 -CU_GRAPH_NODE_TYPE_EMPTY = 5 -CU_GRAPH_NODE_TYPE_WAIT_EVENT = 6 -CU_GRAPH_NODE_TYPE_EVENT_RECORD = 7 -CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL = 8 -CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT = 9 -CU_GRAPH_NODE_TYPE_MEM_ALLOC = 10 -CU_GRAPH_NODE_TYPE_MEM_FREE = 11 -CU_GRAPH_NODE_TYPE_BATCH_MEM_OP = 12 -CUgraphNodeType_enum = ctypes.c_uint32 # enum -CUgraphNodeType = CUgraphNodeType_enum -CUgraphNodeType__enumvalues = CUgraphNodeType_enum__enumvalues +CUgraphNodeType = enum_CUgraphNodeType_enum +enum_CUgraphInstantiateResult_enum = CEnum(ctypes.c_uint32) +CUDA_GRAPH_INSTANTIATE_SUCCESS = enum_CUgraphInstantiateResult_enum.define('CUDA_GRAPH_INSTANTIATE_SUCCESS', 0) +CUDA_GRAPH_INSTANTIATE_ERROR = enum_CUgraphInstantiateResult_enum.define('CUDA_GRAPH_INSTANTIATE_ERROR', 1) +CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE = enum_CUgraphInstantiateResult_enum.define('CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE', 2) +CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED = enum_CUgraphInstantiateResult_enum.define('CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED', 3) +CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED = enum_CUgraphInstantiateResult_enum.define('CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED', 4) -# values for enumeration 'CUgraphInstantiateResult_enum' -CUgraphInstantiateResult_enum__enumvalues = { - 0: 'CUDA_GRAPH_INSTANTIATE_SUCCESS', - 1: 'CUDA_GRAPH_INSTANTIATE_ERROR', - 2: 'CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE', - 3: 'CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED', - 4: 'CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED', -} -CUDA_GRAPH_INSTANTIATE_SUCCESS = 0 -CUDA_GRAPH_INSTANTIATE_ERROR = 1 -CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE = 2 -CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED = 3 -CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED = 4 -CUgraphInstantiateResult_enum = ctypes.c_uint32 # enum -CUgraphInstantiateResult = CUgraphInstantiateResult_enum -CUgraphInstantiateResult__enumvalues = CUgraphInstantiateResult_enum__enumvalues -class struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st(Structure): - pass - -struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st._pack_ = 1 # source:False +CUgraphInstantiateResult = enum_CUgraphInstantiateResult_enum +class struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st(Struct): pass struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st._fields_ = [ - ('flags', ctypes.c_uint64), - ('hUploadStream', ctypes.POINTER(struct_CUstream_st)), - ('hErrNode_out', ctypes.POINTER(struct_CUgraphNode_st)), - ('result_out', CUgraphInstantiateResult), - ('PADDING_0', ctypes.c_ubyte * 4), + ('flags', cuuint64_t), + ('hUploadStream', CUstream), + ('hErrNode_out', CUgraphNode), + ('result_out', CUgraphInstantiateResult), ] - CUDA_GRAPH_INSTANTIATE_PARAMS = struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st +enum_CUsynchronizationPolicy_enum = CEnum(ctypes.c_uint32) +CU_SYNC_POLICY_AUTO = enum_CUsynchronizationPolicy_enum.define('CU_SYNC_POLICY_AUTO', 1) +CU_SYNC_POLICY_SPIN = enum_CUsynchronizationPolicy_enum.define('CU_SYNC_POLICY_SPIN', 2) +CU_SYNC_POLICY_YIELD = enum_CUsynchronizationPolicy_enum.define('CU_SYNC_POLICY_YIELD', 3) +CU_SYNC_POLICY_BLOCKING_SYNC = enum_CUsynchronizationPolicy_enum.define('CU_SYNC_POLICY_BLOCKING_SYNC', 4) -# values for enumeration 'CUsynchronizationPolicy_enum' -CUsynchronizationPolicy_enum__enumvalues = { - 1: 'CU_SYNC_POLICY_AUTO', - 2: 'CU_SYNC_POLICY_SPIN', - 3: 'CU_SYNC_POLICY_YIELD', - 4: 'CU_SYNC_POLICY_BLOCKING_SYNC', -} -CU_SYNC_POLICY_AUTO = 1 -CU_SYNC_POLICY_SPIN = 2 -CU_SYNC_POLICY_YIELD = 3 -CU_SYNC_POLICY_BLOCKING_SYNC = 4 -CUsynchronizationPolicy_enum = ctypes.c_uint32 # enum -CUsynchronizationPolicy = CUsynchronizationPolicy_enum -CUsynchronizationPolicy__enumvalues = CUsynchronizationPolicy_enum__enumvalues +CUsynchronizationPolicy = enum_CUsynchronizationPolicy_enum +enum_CUclusterSchedulingPolicy_enum = CEnum(ctypes.c_uint32) +CU_CLUSTER_SCHEDULING_POLICY_DEFAULT = enum_CUclusterSchedulingPolicy_enum.define('CU_CLUSTER_SCHEDULING_POLICY_DEFAULT', 0) +CU_CLUSTER_SCHEDULING_POLICY_SPREAD = enum_CUclusterSchedulingPolicy_enum.define('CU_CLUSTER_SCHEDULING_POLICY_SPREAD', 1) +CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING = enum_CUclusterSchedulingPolicy_enum.define('CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING', 2) -# values for enumeration 'CUclusterSchedulingPolicy_enum' -CUclusterSchedulingPolicy_enum__enumvalues = { - 0: 'CU_CLUSTER_SCHEDULING_POLICY_DEFAULT', - 1: 'CU_CLUSTER_SCHEDULING_POLICY_SPREAD', - 2: 'CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING', -} -CU_CLUSTER_SCHEDULING_POLICY_DEFAULT = 0 -CU_CLUSTER_SCHEDULING_POLICY_SPREAD = 1 -CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING = 2 -CUclusterSchedulingPolicy_enum = ctypes.c_uint32 # enum -CUclusterSchedulingPolicy = CUclusterSchedulingPolicy_enum -CUclusterSchedulingPolicy__enumvalues = CUclusterSchedulingPolicy_enum__enumvalues +CUclusterSchedulingPolicy = enum_CUclusterSchedulingPolicy_enum +enum_CUlaunchMemSyncDomain_enum = CEnum(ctypes.c_uint32) +CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT = enum_CUlaunchMemSyncDomain_enum.define('CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT', 0) +CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE = enum_CUlaunchMemSyncDomain_enum.define('CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE', 1) -# values for enumeration 'CUlaunchMemSyncDomain_enum' -CUlaunchMemSyncDomain_enum__enumvalues = { - 0: 'CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT', - 1: 'CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE', -} -CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT = 0 -CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE = 1 -CUlaunchMemSyncDomain_enum = ctypes.c_uint32 # enum -CUlaunchMemSyncDomain = CUlaunchMemSyncDomain_enum -CUlaunchMemSyncDomain__enumvalues = CUlaunchMemSyncDomain_enum__enumvalues -class struct_CUlaunchMemSyncDomainMap_st(Structure): - pass - -struct_CUlaunchMemSyncDomainMap_st._pack_ = 1 # source:False +CUlaunchMemSyncDomain = enum_CUlaunchMemSyncDomain_enum +class struct_CUlaunchMemSyncDomainMap_st(Struct): pass struct_CUlaunchMemSyncDomainMap_st._fields_ = [ - ('default_', ctypes.c_ubyte), - ('remote', ctypes.c_ubyte), + ('default_', ctypes.c_ubyte), + ('remote', ctypes.c_ubyte), ] - CUlaunchMemSyncDomainMap = struct_CUlaunchMemSyncDomainMap_st +enum_CUlaunchAttributeID_enum = CEnum(ctypes.c_uint32) +CU_LAUNCH_ATTRIBUTE_IGNORE = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_IGNORE', 0) +CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW', 1) +CU_LAUNCH_ATTRIBUTE_COOPERATIVE = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_COOPERATIVE', 2) +CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY', 3) +CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION', 4) +CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', 5) +CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION', 6) +CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT', 7) +CU_LAUNCH_ATTRIBUTE_PRIORITY = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_PRIORITY', 8) +CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP', 9) +CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN = enum_CUlaunchAttributeID_enum.define('CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN', 10) -# values for enumeration 'CUlaunchAttributeID_enum' -CUlaunchAttributeID_enum__enumvalues = { - 0: 'CU_LAUNCH_ATTRIBUTE_IGNORE', - 1: 'CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW', - 2: 'CU_LAUNCH_ATTRIBUTE_COOPERATIVE', - 3: 'CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY', - 4: 'CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION', - 5: 'CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 6: 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION', - 7: 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT', - 8: 'CU_LAUNCH_ATTRIBUTE_PRIORITY', - 9: 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP', - 10: 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN', -} -CU_LAUNCH_ATTRIBUTE_IGNORE = 0 -CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW = 1 -CU_LAUNCH_ATTRIBUTE_COOPERATIVE = 2 -CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY = 3 -CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION = 4 -CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE = 5 -CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION = 6 -CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT = 7 -CU_LAUNCH_ATTRIBUTE_PRIORITY = 8 -CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP = 9 -CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN = 10 -CUlaunchAttributeID_enum = ctypes.c_uint32 # enum -CUlaunchAttributeID = CUlaunchAttributeID_enum -CUlaunchAttributeID__enumvalues = CUlaunchAttributeID_enum__enumvalues -class union_CUlaunchAttributeValue_union(Union): - pass - -class struct_CUlaunchAttributeValue_union_clusterDim(Structure): - pass - -struct_CUlaunchAttributeValue_union_clusterDim._pack_ = 1 # source:False -struct_CUlaunchAttributeValue_union_clusterDim._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), +CUlaunchAttributeID = enum_CUlaunchAttributeID_enum +class union_CUlaunchAttributeValue_union(ctypes.Union): pass +class union_CUlaunchAttributeValue_union_clusterDim(Struct): pass +union_CUlaunchAttributeValue_union_clusterDim._fields_ = [ + ('x', ctypes.c_uint32), + ('y', ctypes.c_uint32), + ('z', ctypes.c_uint32), ] - -class struct_CUlaunchAttributeValue_union_programmaticEvent(Structure): - pass - -struct_CUlaunchAttributeValue_union_programmaticEvent._pack_ = 1 # source:False -struct_CUlaunchAttributeValue_union_programmaticEvent._fields_ = [ - ('event', ctypes.POINTER(struct_CUevent_st)), - ('flags', ctypes.c_int32), - ('triggerAtBlockStart', ctypes.c_int32), +class union_CUlaunchAttributeValue_union_programmaticEvent(Struct): pass +union_CUlaunchAttributeValue_union_programmaticEvent._fields_ = [ + ('event', CUevent), + ('flags', ctypes.c_int32), + ('triggerAtBlockStart', ctypes.c_int32), ] - -union_CUlaunchAttributeValue_union._pack_ = 1 # source:False union_CUlaunchAttributeValue_union._fields_ = [ - ('pad', ctypes.c_char * 64), - ('accessPolicyWindow', CUaccessPolicyWindow), - ('cooperative', ctypes.c_int32), - ('syncPolicy', CUsynchronizationPolicy), - ('clusterDim', struct_CUlaunchAttributeValue_union_clusterDim), - ('clusterSchedulingPolicyPreference', CUclusterSchedulingPolicy), - ('programmaticStreamSerializationAllowed', ctypes.c_int32), - ('programmaticEvent', struct_CUlaunchAttributeValue_union_programmaticEvent), - ('priority', ctypes.c_int32), - ('memSyncDomainMap', CUlaunchMemSyncDomainMap), - ('memSyncDomain', CUlaunchMemSyncDomain), - ('PADDING_0', ctypes.c_ubyte * 60), + ('pad', (ctypes.c_char * 64)), + ('accessPolicyWindow', CUaccessPolicyWindow), + ('cooperative', ctypes.c_int32), + ('syncPolicy', CUsynchronizationPolicy), + ('clusterDim', union_CUlaunchAttributeValue_union_clusterDim), + ('clusterSchedulingPolicyPreference', CUclusterSchedulingPolicy), + ('programmaticStreamSerializationAllowed', ctypes.c_int32), + ('programmaticEvent', union_CUlaunchAttributeValue_union_programmaticEvent), + ('priority', ctypes.c_int32), + ('memSyncDomainMap', CUlaunchMemSyncDomainMap), + ('memSyncDomain', CUlaunchMemSyncDomain), ] - CUlaunchAttributeValue = union_CUlaunchAttributeValue_union -class struct_CUlaunchAttribute_st(Structure): - pass - -struct_CUlaunchAttribute_st._pack_ = 1 # source:False +class struct_CUlaunchAttribute_st(Struct): pass struct_CUlaunchAttribute_st._fields_ = [ - ('id', CUlaunchAttributeID), - ('pad', ctypes.c_char * 4), - ('value', CUlaunchAttributeValue), + ('id', CUlaunchAttributeID), + ('pad', (ctypes.c_char * 4)), + ('value', CUlaunchAttributeValue), ] - CUlaunchAttribute = struct_CUlaunchAttribute_st -class struct_CUlaunchConfig_st(Structure): - pass - -struct_CUlaunchConfig_st._pack_ = 1 # source:False +class struct_CUlaunchConfig_st(Struct): pass struct_CUlaunchConfig_st._fields_ = [ - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hStream', ctypes.POINTER(struct_CUstream_st)), - ('attrs', ctypes.POINTER(struct_CUlaunchAttribute_st)), - ('numAttrs', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('gridDimX', ctypes.c_uint32), + ('gridDimY', ctypes.c_uint32), + ('gridDimZ', ctypes.c_uint32), + ('blockDimX', ctypes.c_uint32), + ('blockDimY', ctypes.c_uint32), + ('blockDimZ', ctypes.c_uint32), + ('sharedMemBytes', ctypes.c_uint32), + ('hStream', CUstream), + ('attrs', ctypes.POINTER(CUlaunchAttribute)), + ('numAttrs', ctypes.c_uint32), ] - CUlaunchConfig = struct_CUlaunchConfig_st -CUkernelNodeAttrID = CUlaunchAttributeID_enum -CUkernelNodeAttrID__enumvalues = CUlaunchAttributeID_enum__enumvalues +CUkernelNodeAttrID = enum_CUlaunchAttributeID_enum CUkernelNodeAttrValue_v1 = union_CUlaunchAttributeValue_union CUkernelNodeAttrValue = union_CUlaunchAttributeValue_union +enum_CUstreamCaptureStatus_enum = CEnum(ctypes.c_uint32) +CU_STREAM_CAPTURE_STATUS_NONE = enum_CUstreamCaptureStatus_enum.define('CU_STREAM_CAPTURE_STATUS_NONE', 0) +CU_STREAM_CAPTURE_STATUS_ACTIVE = enum_CUstreamCaptureStatus_enum.define('CU_STREAM_CAPTURE_STATUS_ACTIVE', 1) +CU_STREAM_CAPTURE_STATUS_INVALIDATED = enum_CUstreamCaptureStatus_enum.define('CU_STREAM_CAPTURE_STATUS_INVALIDATED', 2) -# values for enumeration 'CUstreamCaptureStatus_enum' -CUstreamCaptureStatus_enum__enumvalues = { - 0: 'CU_STREAM_CAPTURE_STATUS_NONE', - 1: 'CU_STREAM_CAPTURE_STATUS_ACTIVE', - 2: 'CU_STREAM_CAPTURE_STATUS_INVALIDATED', -} -CU_STREAM_CAPTURE_STATUS_NONE = 0 -CU_STREAM_CAPTURE_STATUS_ACTIVE = 1 -CU_STREAM_CAPTURE_STATUS_INVALIDATED = 2 -CUstreamCaptureStatus_enum = ctypes.c_uint32 # enum -CUstreamCaptureStatus = CUstreamCaptureStatus_enum -CUstreamCaptureStatus__enumvalues = CUstreamCaptureStatus_enum__enumvalues +CUstreamCaptureStatus = enum_CUstreamCaptureStatus_enum +enum_CUstreamCaptureMode_enum = CEnum(ctypes.c_uint32) +CU_STREAM_CAPTURE_MODE_GLOBAL = enum_CUstreamCaptureMode_enum.define('CU_STREAM_CAPTURE_MODE_GLOBAL', 0) +CU_STREAM_CAPTURE_MODE_THREAD_LOCAL = enum_CUstreamCaptureMode_enum.define('CU_STREAM_CAPTURE_MODE_THREAD_LOCAL', 1) +CU_STREAM_CAPTURE_MODE_RELAXED = enum_CUstreamCaptureMode_enum.define('CU_STREAM_CAPTURE_MODE_RELAXED', 2) -# values for enumeration 'CUstreamCaptureMode_enum' -CUstreamCaptureMode_enum__enumvalues = { - 0: 'CU_STREAM_CAPTURE_MODE_GLOBAL', - 1: 'CU_STREAM_CAPTURE_MODE_THREAD_LOCAL', - 2: 'CU_STREAM_CAPTURE_MODE_RELAXED', -} -CU_STREAM_CAPTURE_MODE_GLOBAL = 0 -CU_STREAM_CAPTURE_MODE_THREAD_LOCAL = 1 -CU_STREAM_CAPTURE_MODE_RELAXED = 2 -CUstreamCaptureMode_enum = ctypes.c_uint32 # enum -CUstreamCaptureMode = CUstreamCaptureMode_enum -CUstreamCaptureMode__enumvalues = CUstreamCaptureMode_enum__enumvalues -CUstreamAttrID = CUlaunchAttributeID_enum -CUstreamAttrID__enumvalues = CUlaunchAttributeID_enum__enumvalues +CUstreamCaptureMode = enum_CUstreamCaptureMode_enum +CUstreamAttrID = enum_CUlaunchAttributeID_enum CUstreamAttrValue_v1 = union_CUlaunchAttributeValue_union CUstreamAttrValue = union_CUlaunchAttributeValue_union +enum_CUdriverProcAddress_flags_enum = CEnum(ctypes.c_uint32) +CU_GET_PROC_ADDRESS_DEFAULT = enum_CUdriverProcAddress_flags_enum.define('CU_GET_PROC_ADDRESS_DEFAULT', 0) +CU_GET_PROC_ADDRESS_LEGACY_STREAM = enum_CUdriverProcAddress_flags_enum.define('CU_GET_PROC_ADDRESS_LEGACY_STREAM', 1) +CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM = enum_CUdriverProcAddress_flags_enum.define('CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM', 2) -# values for enumeration 'CUdriverProcAddress_flags_enum' -CUdriverProcAddress_flags_enum__enumvalues = { - 0: 'CU_GET_PROC_ADDRESS_DEFAULT', - 1: 'CU_GET_PROC_ADDRESS_LEGACY_STREAM', - 2: 'CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM', -} -CU_GET_PROC_ADDRESS_DEFAULT = 0 -CU_GET_PROC_ADDRESS_LEGACY_STREAM = 1 -CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM = 2 -CUdriverProcAddress_flags_enum = ctypes.c_uint32 # enum -CUdriverProcAddress_flags = CUdriverProcAddress_flags_enum -CUdriverProcAddress_flags__enumvalues = CUdriverProcAddress_flags_enum__enumvalues +CUdriverProcAddress_flags = enum_CUdriverProcAddress_flags_enum +enum_CUdriverProcAddressQueryResult_enum = CEnum(ctypes.c_uint32) +CU_GET_PROC_ADDRESS_SUCCESS = enum_CUdriverProcAddressQueryResult_enum.define('CU_GET_PROC_ADDRESS_SUCCESS', 0) +CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND = enum_CUdriverProcAddressQueryResult_enum.define('CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND', 1) +CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT = enum_CUdriverProcAddressQueryResult_enum.define('CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT', 2) -# values for enumeration 'CUdriverProcAddressQueryResult_enum' -CUdriverProcAddressQueryResult_enum__enumvalues = { - 0: 'CU_GET_PROC_ADDRESS_SUCCESS', - 1: 'CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND', - 2: 'CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT', -} -CU_GET_PROC_ADDRESS_SUCCESS = 0 -CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND = 1 -CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT = 2 -CUdriverProcAddressQueryResult_enum = ctypes.c_uint32 # enum -CUdriverProcAddressQueryResult = CUdriverProcAddressQueryResult_enum -CUdriverProcAddressQueryResult__enumvalues = CUdriverProcAddressQueryResult_enum__enumvalues +CUdriverProcAddressQueryResult = enum_CUdriverProcAddressQueryResult_enum +enum_CUexecAffinityType_enum = CEnum(ctypes.c_uint32) +CU_EXEC_AFFINITY_TYPE_SM_COUNT = enum_CUexecAffinityType_enum.define('CU_EXEC_AFFINITY_TYPE_SM_COUNT', 0) +CU_EXEC_AFFINITY_TYPE_MAX = enum_CUexecAffinityType_enum.define('CU_EXEC_AFFINITY_TYPE_MAX', 1) -# values for enumeration 'CUexecAffinityType_enum' -CUexecAffinityType_enum__enumvalues = { - 0: 'CU_EXEC_AFFINITY_TYPE_SM_COUNT', - 1: 'CU_EXEC_AFFINITY_TYPE_MAX', -} -CU_EXEC_AFFINITY_TYPE_SM_COUNT = 0 -CU_EXEC_AFFINITY_TYPE_MAX = 1 -CUexecAffinityType_enum = ctypes.c_uint32 # enum -CUexecAffinityType = CUexecAffinityType_enum -CUexecAffinityType__enumvalues = CUexecAffinityType_enum__enumvalues -class struct_CUexecAffinitySmCount_st(Structure): - pass - -struct_CUexecAffinitySmCount_st._pack_ = 1 # source:False +CUexecAffinityType = enum_CUexecAffinityType_enum +class struct_CUexecAffinitySmCount_st(Struct): pass struct_CUexecAffinitySmCount_st._fields_ = [ - ('val', ctypes.c_uint32), + ('val', ctypes.c_uint32), ] - CUexecAffinitySmCount_v1 = struct_CUexecAffinitySmCount_st CUexecAffinitySmCount = struct_CUexecAffinitySmCount_st -class struct_CUexecAffinityParam_st(Structure): - pass - -class union_CUexecAffinityParam_st_param(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('smCount', CUexecAffinitySmCount), - ] - -struct_CUexecAffinityParam_st._pack_ = 1 # source:False -struct_CUexecAffinityParam_st._fields_ = [ - ('type', CUexecAffinityType), - ('param', union_CUexecAffinityParam_st_param), +class struct_CUexecAffinityParam_st(Struct): pass +class struct_CUexecAffinityParam_st_param(ctypes.Union): pass +struct_CUexecAffinityParam_st_param._fields_ = [ + ('smCount', CUexecAffinitySmCount), +] +struct_CUexecAffinityParam_st._fields_ = [ + ('type', CUexecAffinityType), + ('param', struct_CUexecAffinityParam_st_param), ] - CUexecAffinityParam_v1 = struct_CUexecAffinityParam_st CUexecAffinityParam = struct_CUexecAffinityParam_st +enum_CUlibraryOption_enum = CEnum(ctypes.c_uint32) +CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE = enum_CUlibraryOption_enum.define('CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE', 0) +CU_LIBRARY_BINARY_IS_PRESERVED = enum_CUlibraryOption_enum.define('CU_LIBRARY_BINARY_IS_PRESERVED', 1) +CU_LIBRARY_NUM_OPTIONS = enum_CUlibraryOption_enum.define('CU_LIBRARY_NUM_OPTIONS', 2) -# values for enumeration 'CUlibraryOption_enum' -CUlibraryOption_enum__enumvalues = { - 0: 'CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE', - 1: 'CU_LIBRARY_BINARY_IS_PRESERVED', - 2: 'CU_LIBRARY_NUM_OPTIONS', -} -CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE = 0 -CU_LIBRARY_BINARY_IS_PRESERVED = 1 -CU_LIBRARY_NUM_OPTIONS = 2 -CUlibraryOption_enum = ctypes.c_uint32 # enum -CUlibraryOption = CUlibraryOption_enum -CUlibraryOption__enumvalues = CUlibraryOption_enum__enumvalues -class struct_CUlibraryHostUniversalFunctionAndDataTable_st(Structure): - pass - -struct_CUlibraryHostUniversalFunctionAndDataTable_st._pack_ = 1 # source:False +CUlibraryOption = enum_CUlibraryOption_enum +class struct_CUlibraryHostUniversalFunctionAndDataTable_st(Struct): pass struct_CUlibraryHostUniversalFunctionAndDataTable_st._fields_ = [ - ('functionTable', ctypes.POINTER(None)), - ('functionWindowSize', ctypes.c_uint64), - ('dataTable', ctypes.POINTER(None)), - ('dataWindowSize', ctypes.c_uint64), + ('functionTable', ctypes.c_void_p), + ('functionWindowSize', size_t), + ('dataTable', ctypes.c_void_p), + ('dataWindowSize', size_t), ] - CUlibraryHostUniversalFunctionAndDataTable = struct_CUlibraryHostUniversalFunctionAndDataTable_st +enum_cudaError_enum = CEnum(ctypes.c_uint32) +CUDA_SUCCESS = enum_cudaError_enum.define('CUDA_SUCCESS', 0) +CUDA_ERROR_INVALID_VALUE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_VALUE', 1) +CUDA_ERROR_OUT_OF_MEMORY = enum_cudaError_enum.define('CUDA_ERROR_OUT_OF_MEMORY', 2) +CUDA_ERROR_NOT_INITIALIZED = enum_cudaError_enum.define('CUDA_ERROR_NOT_INITIALIZED', 3) +CUDA_ERROR_DEINITIALIZED = enum_cudaError_enum.define('CUDA_ERROR_DEINITIALIZED', 4) +CUDA_ERROR_PROFILER_DISABLED = enum_cudaError_enum.define('CUDA_ERROR_PROFILER_DISABLED', 5) +CUDA_ERROR_PROFILER_NOT_INITIALIZED = enum_cudaError_enum.define('CUDA_ERROR_PROFILER_NOT_INITIALIZED', 6) +CUDA_ERROR_PROFILER_ALREADY_STARTED = enum_cudaError_enum.define('CUDA_ERROR_PROFILER_ALREADY_STARTED', 7) +CUDA_ERROR_PROFILER_ALREADY_STOPPED = enum_cudaError_enum.define('CUDA_ERROR_PROFILER_ALREADY_STOPPED', 8) +CUDA_ERROR_STUB_LIBRARY = enum_cudaError_enum.define('CUDA_ERROR_STUB_LIBRARY', 34) +CUDA_ERROR_DEVICE_UNAVAILABLE = enum_cudaError_enum.define('CUDA_ERROR_DEVICE_UNAVAILABLE', 46) +CUDA_ERROR_NO_DEVICE = enum_cudaError_enum.define('CUDA_ERROR_NO_DEVICE', 100) +CUDA_ERROR_INVALID_DEVICE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_DEVICE', 101) +CUDA_ERROR_DEVICE_NOT_LICENSED = enum_cudaError_enum.define('CUDA_ERROR_DEVICE_NOT_LICENSED', 102) +CUDA_ERROR_INVALID_IMAGE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_IMAGE', 200) +CUDA_ERROR_INVALID_CONTEXT = enum_cudaError_enum.define('CUDA_ERROR_INVALID_CONTEXT', 201) +CUDA_ERROR_CONTEXT_ALREADY_CURRENT = enum_cudaError_enum.define('CUDA_ERROR_CONTEXT_ALREADY_CURRENT', 202) +CUDA_ERROR_MAP_FAILED = enum_cudaError_enum.define('CUDA_ERROR_MAP_FAILED', 205) +CUDA_ERROR_UNMAP_FAILED = enum_cudaError_enum.define('CUDA_ERROR_UNMAP_FAILED', 206) +CUDA_ERROR_ARRAY_IS_MAPPED = enum_cudaError_enum.define('CUDA_ERROR_ARRAY_IS_MAPPED', 207) +CUDA_ERROR_ALREADY_MAPPED = enum_cudaError_enum.define('CUDA_ERROR_ALREADY_MAPPED', 208) +CUDA_ERROR_NO_BINARY_FOR_GPU = enum_cudaError_enum.define('CUDA_ERROR_NO_BINARY_FOR_GPU', 209) +CUDA_ERROR_ALREADY_ACQUIRED = enum_cudaError_enum.define('CUDA_ERROR_ALREADY_ACQUIRED', 210) +CUDA_ERROR_NOT_MAPPED = enum_cudaError_enum.define('CUDA_ERROR_NOT_MAPPED', 211) +CUDA_ERROR_NOT_MAPPED_AS_ARRAY = enum_cudaError_enum.define('CUDA_ERROR_NOT_MAPPED_AS_ARRAY', 212) +CUDA_ERROR_NOT_MAPPED_AS_POINTER = enum_cudaError_enum.define('CUDA_ERROR_NOT_MAPPED_AS_POINTER', 213) +CUDA_ERROR_ECC_UNCORRECTABLE = enum_cudaError_enum.define('CUDA_ERROR_ECC_UNCORRECTABLE', 214) +CUDA_ERROR_UNSUPPORTED_LIMIT = enum_cudaError_enum.define('CUDA_ERROR_UNSUPPORTED_LIMIT', 215) +CUDA_ERROR_CONTEXT_ALREADY_IN_USE = enum_cudaError_enum.define('CUDA_ERROR_CONTEXT_ALREADY_IN_USE', 216) +CUDA_ERROR_PEER_ACCESS_UNSUPPORTED = enum_cudaError_enum.define('CUDA_ERROR_PEER_ACCESS_UNSUPPORTED', 217) +CUDA_ERROR_INVALID_PTX = enum_cudaError_enum.define('CUDA_ERROR_INVALID_PTX', 218) +CUDA_ERROR_INVALID_GRAPHICS_CONTEXT = enum_cudaError_enum.define('CUDA_ERROR_INVALID_GRAPHICS_CONTEXT', 219) +CUDA_ERROR_NVLINK_UNCORRECTABLE = enum_cudaError_enum.define('CUDA_ERROR_NVLINK_UNCORRECTABLE', 220) +CUDA_ERROR_JIT_COMPILER_NOT_FOUND = enum_cudaError_enum.define('CUDA_ERROR_JIT_COMPILER_NOT_FOUND', 221) +CUDA_ERROR_UNSUPPORTED_PTX_VERSION = enum_cudaError_enum.define('CUDA_ERROR_UNSUPPORTED_PTX_VERSION', 222) +CUDA_ERROR_JIT_COMPILATION_DISABLED = enum_cudaError_enum.define('CUDA_ERROR_JIT_COMPILATION_DISABLED', 223) +CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY = enum_cudaError_enum.define('CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY', 224) +CUDA_ERROR_INVALID_SOURCE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_SOURCE', 300) +CUDA_ERROR_FILE_NOT_FOUND = enum_cudaError_enum.define('CUDA_ERROR_FILE_NOT_FOUND', 301) +CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND = enum_cudaError_enum.define('CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND', 302) +CUDA_ERROR_SHARED_OBJECT_INIT_FAILED = enum_cudaError_enum.define('CUDA_ERROR_SHARED_OBJECT_INIT_FAILED', 303) +CUDA_ERROR_OPERATING_SYSTEM = enum_cudaError_enum.define('CUDA_ERROR_OPERATING_SYSTEM', 304) +CUDA_ERROR_INVALID_HANDLE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_HANDLE', 400) +CUDA_ERROR_ILLEGAL_STATE = enum_cudaError_enum.define('CUDA_ERROR_ILLEGAL_STATE', 401) +CUDA_ERROR_NOT_FOUND = enum_cudaError_enum.define('CUDA_ERROR_NOT_FOUND', 500) +CUDA_ERROR_NOT_READY = enum_cudaError_enum.define('CUDA_ERROR_NOT_READY', 600) +CUDA_ERROR_ILLEGAL_ADDRESS = enum_cudaError_enum.define('CUDA_ERROR_ILLEGAL_ADDRESS', 700) +CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES = enum_cudaError_enum.define('CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES', 701) +CUDA_ERROR_LAUNCH_TIMEOUT = enum_cudaError_enum.define('CUDA_ERROR_LAUNCH_TIMEOUT', 702) +CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING = enum_cudaError_enum.define('CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING', 703) +CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED = enum_cudaError_enum.define('CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED', 704) +CUDA_ERROR_PEER_ACCESS_NOT_ENABLED = enum_cudaError_enum.define('CUDA_ERROR_PEER_ACCESS_NOT_ENABLED', 705) +CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE = enum_cudaError_enum.define('CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE', 708) +CUDA_ERROR_CONTEXT_IS_DESTROYED = enum_cudaError_enum.define('CUDA_ERROR_CONTEXT_IS_DESTROYED', 709) +CUDA_ERROR_ASSERT = enum_cudaError_enum.define('CUDA_ERROR_ASSERT', 710) +CUDA_ERROR_TOO_MANY_PEERS = enum_cudaError_enum.define('CUDA_ERROR_TOO_MANY_PEERS', 711) +CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED = enum_cudaError_enum.define('CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED', 712) +CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED = enum_cudaError_enum.define('CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED', 713) +CUDA_ERROR_HARDWARE_STACK_ERROR = enum_cudaError_enum.define('CUDA_ERROR_HARDWARE_STACK_ERROR', 714) +CUDA_ERROR_ILLEGAL_INSTRUCTION = enum_cudaError_enum.define('CUDA_ERROR_ILLEGAL_INSTRUCTION', 715) +CUDA_ERROR_MISALIGNED_ADDRESS = enum_cudaError_enum.define('CUDA_ERROR_MISALIGNED_ADDRESS', 716) +CUDA_ERROR_INVALID_ADDRESS_SPACE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_ADDRESS_SPACE', 717) +CUDA_ERROR_INVALID_PC = enum_cudaError_enum.define('CUDA_ERROR_INVALID_PC', 718) +CUDA_ERROR_LAUNCH_FAILED = enum_cudaError_enum.define('CUDA_ERROR_LAUNCH_FAILED', 719) +CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE = enum_cudaError_enum.define('CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE', 720) +CUDA_ERROR_NOT_PERMITTED = enum_cudaError_enum.define('CUDA_ERROR_NOT_PERMITTED', 800) +CUDA_ERROR_NOT_SUPPORTED = enum_cudaError_enum.define('CUDA_ERROR_NOT_SUPPORTED', 801) +CUDA_ERROR_SYSTEM_NOT_READY = enum_cudaError_enum.define('CUDA_ERROR_SYSTEM_NOT_READY', 802) +CUDA_ERROR_SYSTEM_DRIVER_MISMATCH = enum_cudaError_enum.define('CUDA_ERROR_SYSTEM_DRIVER_MISMATCH', 803) +CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE = enum_cudaError_enum.define('CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE', 804) +CUDA_ERROR_MPS_CONNECTION_FAILED = enum_cudaError_enum.define('CUDA_ERROR_MPS_CONNECTION_FAILED', 805) +CUDA_ERROR_MPS_RPC_FAILURE = enum_cudaError_enum.define('CUDA_ERROR_MPS_RPC_FAILURE', 806) +CUDA_ERROR_MPS_SERVER_NOT_READY = enum_cudaError_enum.define('CUDA_ERROR_MPS_SERVER_NOT_READY', 807) +CUDA_ERROR_MPS_MAX_CLIENTS_REACHED = enum_cudaError_enum.define('CUDA_ERROR_MPS_MAX_CLIENTS_REACHED', 808) +CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED = enum_cudaError_enum.define('CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED', 809) +CUDA_ERROR_MPS_CLIENT_TERMINATED = enum_cudaError_enum.define('CUDA_ERROR_MPS_CLIENT_TERMINATED', 810) +CUDA_ERROR_CDP_NOT_SUPPORTED = enum_cudaError_enum.define('CUDA_ERROR_CDP_NOT_SUPPORTED', 811) +CUDA_ERROR_CDP_VERSION_MISMATCH = enum_cudaError_enum.define('CUDA_ERROR_CDP_VERSION_MISMATCH', 812) +CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED', 900) +CUDA_ERROR_STREAM_CAPTURE_INVALIDATED = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_INVALIDATED', 901) +CUDA_ERROR_STREAM_CAPTURE_MERGE = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_MERGE', 902) +CUDA_ERROR_STREAM_CAPTURE_UNMATCHED = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_UNMATCHED', 903) +CUDA_ERROR_STREAM_CAPTURE_UNJOINED = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_UNJOINED', 904) +CUDA_ERROR_STREAM_CAPTURE_ISOLATION = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_ISOLATION', 905) +CUDA_ERROR_STREAM_CAPTURE_IMPLICIT = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_IMPLICIT', 906) +CUDA_ERROR_CAPTURED_EVENT = enum_cudaError_enum.define('CUDA_ERROR_CAPTURED_EVENT', 907) +CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD = enum_cudaError_enum.define('CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD', 908) +CUDA_ERROR_TIMEOUT = enum_cudaError_enum.define('CUDA_ERROR_TIMEOUT', 909) +CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE = enum_cudaError_enum.define('CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE', 910) +CUDA_ERROR_EXTERNAL_DEVICE = enum_cudaError_enum.define('CUDA_ERROR_EXTERNAL_DEVICE', 911) +CUDA_ERROR_INVALID_CLUSTER_SIZE = enum_cudaError_enum.define('CUDA_ERROR_INVALID_CLUSTER_SIZE', 912) +CUDA_ERROR_UNKNOWN = enum_cudaError_enum.define('CUDA_ERROR_UNKNOWN', 999) -# values for enumeration 'cudaError_enum' -cudaError_enum__enumvalues = { - 0: 'CUDA_SUCCESS', - 1: 'CUDA_ERROR_INVALID_VALUE', - 2: 'CUDA_ERROR_OUT_OF_MEMORY', - 3: 'CUDA_ERROR_NOT_INITIALIZED', - 4: 'CUDA_ERROR_DEINITIALIZED', - 5: 'CUDA_ERROR_PROFILER_DISABLED', - 6: 'CUDA_ERROR_PROFILER_NOT_INITIALIZED', - 7: 'CUDA_ERROR_PROFILER_ALREADY_STARTED', - 8: 'CUDA_ERROR_PROFILER_ALREADY_STOPPED', - 34: 'CUDA_ERROR_STUB_LIBRARY', - 46: 'CUDA_ERROR_DEVICE_UNAVAILABLE', - 100: 'CUDA_ERROR_NO_DEVICE', - 101: 'CUDA_ERROR_INVALID_DEVICE', - 102: 'CUDA_ERROR_DEVICE_NOT_LICENSED', - 200: 'CUDA_ERROR_INVALID_IMAGE', - 201: 'CUDA_ERROR_INVALID_CONTEXT', - 202: 'CUDA_ERROR_CONTEXT_ALREADY_CURRENT', - 205: 'CUDA_ERROR_MAP_FAILED', - 206: 'CUDA_ERROR_UNMAP_FAILED', - 207: 'CUDA_ERROR_ARRAY_IS_MAPPED', - 208: 'CUDA_ERROR_ALREADY_MAPPED', - 209: 'CUDA_ERROR_NO_BINARY_FOR_GPU', - 210: 'CUDA_ERROR_ALREADY_ACQUIRED', - 211: 'CUDA_ERROR_NOT_MAPPED', - 212: 'CUDA_ERROR_NOT_MAPPED_AS_ARRAY', - 213: 'CUDA_ERROR_NOT_MAPPED_AS_POINTER', - 214: 'CUDA_ERROR_ECC_UNCORRECTABLE', - 215: 'CUDA_ERROR_UNSUPPORTED_LIMIT', - 216: 'CUDA_ERROR_CONTEXT_ALREADY_IN_USE', - 217: 'CUDA_ERROR_PEER_ACCESS_UNSUPPORTED', - 218: 'CUDA_ERROR_INVALID_PTX', - 219: 'CUDA_ERROR_INVALID_GRAPHICS_CONTEXT', - 220: 'CUDA_ERROR_NVLINK_UNCORRECTABLE', - 221: 'CUDA_ERROR_JIT_COMPILER_NOT_FOUND', - 222: 'CUDA_ERROR_UNSUPPORTED_PTX_VERSION', - 223: 'CUDA_ERROR_JIT_COMPILATION_DISABLED', - 224: 'CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY', - 300: 'CUDA_ERROR_INVALID_SOURCE', - 301: 'CUDA_ERROR_FILE_NOT_FOUND', - 302: 'CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND', - 303: 'CUDA_ERROR_SHARED_OBJECT_INIT_FAILED', - 304: 'CUDA_ERROR_OPERATING_SYSTEM', - 400: 'CUDA_ERROR_INVALID_HANDLE', - 401: 'CUDA_ERROR_ILLEGAL_STATE', - 500: 'CUDA_ERROR_NOT_FOUND', - 600: 'CUDA_ERROR_NOT_READY', - 700: 'CUDA_ERROR_ILLEGAL_ADDRESS', - 701: 'CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES', - 702: 'CUDA_ERROR_LAUNCH_TIMEOUT', - 703: 'CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING', - 704: 'CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED', - 705: 'CUDA_ERROR_PEER_ACCESS_NOT_ENABLED', - 708: 'CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE', - 709: 'CUDA_ERROR_CONTEXT_IS_DESTROYED', - 710: 'CUDA_ERROR_ASSERT', - 711: 'CUDA_ERROR_TOO_MANY_PEERS', - 712: 'CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED', - 713: 'CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED', - 714: 'CUDA_ERROR_HARDWARE_STACK_ERROR', - 715: 'CUDA_ERROR_ILLEGAL_INSTRUCTION', - 716: 'CUDA_ERROR_MISALIGNED_ADDRESS', - 717: 'CUDA_ERROR_INVALID_ADDRESS_SPACE', - 718: 'CUDA_ERROR_INVALID_PC', - 719: 'CUDA_ERROR_LAUNCH_FAILED', - 720: 'CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE', - 800: 'CUDA_ERROR_NOT_PERMITTED', - 801: 'CUDA_ERROR_NOT_SUPPORTED', - 802: 'CUDA_ERROR_SYSTEM_NOT_READY', - 803: 'CUDA_ERROR_SYSTEM_DRIVER_MISMATCH', - 804: 'CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE', - 805: 'CUDA_ERROR_MPS_CONNECTION_FAILED', - 806: 'CUDA_ERROR_MPS_RPC_FAILURE', - 807: 'CUDA_ERROR_MPS_SERVER_NOT_READY', - 808: 'CUDA_ERROR_MPS_MAX_CLIENTS_REACHED', - 809: 'CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED', - 810: 'CUDA_ERROR_MPS_CLIENT_TERMINATED', - 811: 'CUDA_ERROR_CDP_NOT_SUPPORTED', - 812: 'CUDA_ERROR_CDP_VERSION_MISMATCH', - 900: 'CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED', - 901: 'CUDA_ERROR_STREAM_CAPTURE_INVALIDATED', - 902: 'CUDA_ERROR_STREAM_CAPTURE_MERGE', - 903: 'CUDA_ERROR_STREAM_CAPTURE_UNMATCHED', - 904: 'CUDA_ERROR_STREAM_CAPTURE_UNJOINED', - 905: 'CUDA_ERROR_STREAM_CAPTURE_ISOLATION', - 906: 'CUDA_ERROR_STREAM_CAPTURE_IMPLICIT', - 907: 'CUDA_ERROR_CAPTURED_EVENT', - 908: 'CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD', - 909: 'CUDA_ERROR_TIMEOUT', - 910: 'CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE', - 911: 'CUDA_ERROR_EXTERNAL_DEVICE', - 912: 'CUDA_ERROR_INVALID_CLUSTER_SIZE', - 999: 'CUDA_ERROR_UNKNOWN', -} -CUDA_SUCCESS = 0 -CUDA_ERROR_INVALID_VALUE = 1 -CUDA_ERROR_OUT_OF_MEMORY = 2 -CUDA_ERROR_NOT_INITIALIZED = 3 -CUDA_ERROR_DEINITIALIZED = 4 -CUDA_ERROR_PROFILER_DISABLED = 5 -CUDA_ERROR_PROFILER_NOT_INITIALIZED = 6 -CUDA_ERROR_PROFILER_ALREADY_STARTED = 7 -CUDA_ERROR_PROFILER_ALREADY_STOPPED = 8 -CUDA_ERROR_STUB_LIBRARY = 34 -CUDA_ERROR_DEVICE_UNAVAILABLE = 46 -CUDA_ERROR_NO_DEVICE = 100 -CUDA_ERROR_INVALID_DEVICE = 101 -CUDA_ERROR_DEVICE_NOT_LICENSED = 102 -CUDA_ERROR_INVALID_IMAGE = 200 -CUDA_ERROR_INVALID_CONTEXT = 201 -CUDA_ERROR_CONTEXT_ALREADY_CURRENT = 202 -CUDA_ERROR_MAP_FAILED = 205 -CUDA_ERROR_UNMAP_FAILED = 206 -CUDA_ERROR_ARRAY_IS_MAPPED = 207 -CUDA_ERROR_ALREADY_MAPPED = 208 -CUDA_ERROR_NO_BINARY_FOR_GPU = 209 -CUDA_ERROR_ALREADY_ACQUIRED = 210 -CUDA_ERROR_NOT_MAPPED = 211 -CUDA_ERROR_NOT_MAPPED_AS_ARRAY = 212 -CUDA_ERROR_NOT_MAPPED_AS_POINTER = 213 -CUDA_ERROR_ECC_UNCORRECTABLE = 214 -CUDA_ERROR_UNSUPPORTED_LIMIT = 215 -CUDA_ERROR_CONTEXT_ALREADY_IN_USE = 216 -CUDA_ERROR_PEER_ACCESS_UNSUPPORTED = 217 -CUDA_ERROR_INVALID_PTX = 218 -CUDA_ERROR_INVALID_GRAPHICS_CONTEXT = 219 -CUDA_ERROR_NVLINK_UNCORRECTABLE = 220 -CUDA_ERROR_JIT_COMPILER_NOT_FOUND = 221 -CUDA_ERROR_UNSUPPORTED_PTX_VERSION = 222 -CUDA_ERROR_JIT_COMPILATION_DISABLED = 223 -CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY = 224 -CUDA_ERROR_INVALID_SOURCE = 300 -CUDA_ERROR_FILE_NOT_FOUND = 301 -CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND = 302 -CUDA_ERROR_SHARED_OBJECT_INIT_FAILED = 303 -CUDA_ERROR_OPERATING_SYSTEM = 304 -CUDA_ERROR_INVALID_HANDLE = 400 -CUDA_ERROR_ILLEGAL_STATE = 401 -CUDA_ERROR_NOT_FOUND = 500 -CUDA_ERROR_NOT_READY = 600 -CUDA_ERROR_ILLEGAL_ADDRESS = 700 -CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES = 701 -CUDA_ERROR_LAUNCH_TIMEOUT = 702 -CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING = 703 -CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED = 704 -CUDA_ERROR_PEER_ACCESS_NOT_ENABLED = 705 -CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE = 708 -CUDA_ERROR_CONTEXT_IS_DESTROYED = 709 -CUDA_ERROR_ASSERT = 710 -CUDA_ERROR_TOO_MANY_PEERS = 711 -CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED = 712 -CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED = 713 -CUDA_ERROR_HARDWARE_STACK_ERROR = 714 -CUDA_ERROR_ILLEGAL_INSTRUCTION = 715 -CUDA_ERROR_MISALIGNED_ADDRESS = 716 -CUDA_ERROR_INVALID_ADDRESS_SPACE = 717 -CUDA_ERROR_INVALID_PC = 718 -CUDA_ERROR_LAUNCH_FAILED = 719 -CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE = 720 -CUDA_ERROR_NOT_PERMITTED = 800 -CUDA_ERROR_NOT_SUPPORTED = 801 -CUDA_ERROR_SYSTEM_NOT_READY = 802 -CUDA_ERROR_SYSTEM_DRIVER_MISMATCH = 803 -CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE = 804 -CUDA_ERROR_MPS_CONNECTION_FAILED = 805 -CUDA_ERROR_MPS_RPC_FAILURE = 806 -CUDA_ERROR_MPS_SERVER_NOT_READY = 807 -CUDA_ERROR_MPS_MAX_CLIENTS_REACHED = 808 -CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED = 809 -CUDA_ERROR_MPS_CLIENT_TERMINATED = 810 -CUDA_ERROR_CDP_NOT_SUPPORTED = 811 -CUDA_ERROR_CDP_VERSION_MISMATCH = 812 -CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED = 900 -CUDA_ERROR_STREAM_CAPTURE_INVALIDATED = 901 -CUDA_ERROR_STREAM_CAPTURE_MERGE = 902 -CUDA_ERROR_STREAM_CAPTURE_UNMATCHED = 903 -CUDA_ERROR_STREAM_CAPTURE_UNJOINED = 904 -CUDA_ERROR_STREAM_CAPTURE_ISOLATION = 905 -CUDA_ERROR_STREAM_CAPTURE_IMPLICIT = 906 -CUDA_ERROR_CAPTURED_EVENT = 907 -CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD = 908 -CUDA_ERROR_TIMEOUT = 909 -CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE = 910 -CUDA_ERROR_EXTERNAL_DEVICE = 911 -CUDA_ERROR_INVALID_CLUSTER_SIZE = 912 -CUDA_ERROR_UNKNOWN = 999 -cudaError_enum = ctypes.c_uint32 # enum -CUresult = cudaError_enum -CUresult__enumvalues = cudaError_enum__enumvalues +CUresult = enum_cudaError_enum +enum_CUdevice_P2PAttribute_enum = CEnum(ctypes.c_uint32) +CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK = enum_CUdevice_P2PAttribute_enum.define('CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK', 1) +CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED = enum_CUdevice_P2PAttribute_enum.define('CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED', 2) +CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED = enum_CUdevice_P2PAttribute_enum.define('CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED', 3) +CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED = enum_CUdevice_P2PAttribute_enum.define('CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED', 4) +CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED = enum_CUdevice_P2PAttribute_enum.define('CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED', 4) -# values for enumeration 'CUdevice_P2PAttribute_enum' -CUdevice_P2PAttribute_enum__enumvalues = { - 1: 'CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK', - 2: 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED', - 3: 'CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED', - 4: 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED', - 4: 'CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED', -} -CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK = 1 -CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED = 2 -CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED = 3 -CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED = 4 -CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED = 4 -CUdevice_P2PAttribute_enum = ctypes.c_uint32 # enum -CUdevice_P2PAttribute = CUdevice_P2PAttribute_enum -CUdevice_P2PAttribute__enumvalues = CUdevice_P2PAttribute_enum__enumvalues -CUstreamCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_CUstream_st), cudaError_enum, ctypes.POINTER(None)) +CUdevice_P2PAttribute = enum_CUdevice_P2PAttribute_enum +CUstreamCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_CUstream_st), enum_cudaError_enum, ctypes.c_void_p) CUoccupancyB2DSize = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_int32) -class struct_CUDA_MEMCPY2D_st(Structure): - pass - -struct_CUDA_MEMCPY2D_st._pack_ = 1 # source:False +class struct_CUDA_MEMCPY2D_st(Struct): pass struct_CUDA_MEMCPY2D_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint64), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('srcPitch', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstMemoryType', CUmemorytype), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint64), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('dstPitch', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), + ('srcXInBytes', size_t), + ('srcY', size_t), + ('srcMemoryType', CUmemorytype), + ('srcHost', ctypes.c_void_p), + ('srcDevice', CUdeviceptr), + ('srcArray', CUarray), + ('srcPitch', size_t), + ('dstXInBytes', size_t), + ('dstY', size_t), + ('dstMemoryType', CUmemorytype), + ('dstHost', ctypes.c_void_p), + ('dstDevice', CUdeviceptr), + ('dstArray', CUarray), + ('dstPitch', size_t), + ('WidthInBytes', size_t), + ('Height', size_t), ] - CUDA_MEMCPY2D_v2 = struct_CUDA_MEMCPY2D_st CUDA_MEMCPY2D = struct_CUDA_MEMCPY2D_st -class struct_CUDA_MEMCPY3D_st(Structure): - pass - -struct_CUDA_MEMCPY3D_st._pack_ = 1 # source:False +class struct_CUDA_MEMCPY3D_st(Struct): pass struct_CUDA_MEMCPY3D_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcZ', ctypes.c_uint64), - ('srcLOD', ctypes.c_uint64), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint64), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved0', ctypes.POINTER(None)), - ('srcPitch', ctypes.c_uint64), - ('srcHeight', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstZ', ctypes.c_uint64), - ('dstLOD', ctypes.c_uint64), - ('dstMemoryType', CUmemorytype), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint64), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved1', ctypes.POINTER(None)), - ('dstPitch', ctypes.c_uint64), - ('dstHeight', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), + ('srcXInBytes', size_t), + ('srcY', size_t), + ('srcZ', size_t), + ('srcLOD', size_t), + ('srcMemoryType', CUmemorytype), + ('srcHost', ctypes.c_void_p), + ('srcDevice', CUdeviceptr), + ('srcArray', CUarray), + ('reserved0', ctypes.c_void_p), + ('srcPitch', size_t), + ('srcHeight', size_t), + ('dstXInBytes', size_t), + ('dstY', size_t), + ('dstZ', size_t), + ('dstLOD', size_t), + ('dstMemoryType', CUmemorytype), + ('dstHost', ctypes.c_void_p), + ('dstDevice', CUdeviceptr), + ('dstArray', CUarray), + ('reserved1', ctypes.c_void_p), + ('dstPitch', size_t), + ('dstHeight', size_t), + ('WidthInBytes', size_t), + ('Height', size_t), + ('Depth', size_t), ] - CUDA_MEMCPY3D_v2 = struct_CUDA_MEMCPY3D_st CUDA_MEMCPY3D = struct_CUDA_MEMCPY3D_st -class struct_CUDA_MEMCPY3D_PEER_st(Structure): - pass - -struct_CUDA_MEMCPY3D_PEER_st._pack_ = 1 # source:False +class struct_CUDA_MEMCPY3D_PEER_st(Struct): pass struct_CUDA_MEMCPY3D_PEER_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcZ', ctypes.c_uint64), - ('srcLOD', ctypes.c_uint64), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint64), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('srcContext', ctypes.POINTER(struct_CUctx_st)), - ('srcPitch', ctypes.c_uint64), - ('srcHeight', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstZ', ctypes.c_uint64), - ('dstLOD', ctypes.c_uint64), - ('dstMemoryType', CUmemorytype), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint64), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('dstContext', ctypes.POINTER(struct_CUctx_st)), - ('dstPitch', ctypes.c_uint64), - ('dstHeight', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), + ('srcXInBytes', size_t), + ('srcY', size_t), + ('srcZ', size_t), + ('srcLOD', size_t), + ('srcMemoryType', CUmemorytype), + ('srcHost', ctypes.c_void_p), + ('srcDevice', CUdeviceptr), + ('srcArray', CUarray), + ('srcContext', CUcontext), + ('srcPitch', size_t), + ('srcHeight', size_t), + ('dstXInBytes', size_t), + ('dstY', size_t), + ('dstZ', size_t), + ('dstLOD', size_t), + ('dstMemoryType', CUmemorytype), + ('dstHost', ctypes.c_void_p), + ('dstDevice', CUdeviceptr), + ('dstArray', CUarray), + ('dstContext', CUcontext), + ('dstPitch', size_t), + ('dstHeight', size_t), + ('WidthInBytes', size_t), + ('Height', size_t), + ('Depth', size_t), ] - CUDA_MEMCPY3D_PEER_v1 = struct_CUDA_MEMCPY3D_PEER_st CUDA_MEMCPY3D_PEER = struct_CUDA_MEMCPY3D_PEER_st -class struct_CUDA_ARRAY_DESCRIPTOR_st(Structure): - pass - -struct_CUDA_ARRAY_DESCRIPTOR_st._pack_ = 1 # source:False +class struct_CUDA_ARRAY_DESCRIPTOR_st(Struct): pass struct_CUDA_ARRAY_DESCRIPTOR_st._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), + ('Width', size_t), + ('Height', size_t), + ('Format', CUarray_format), + ('NumChannels', ctypes.c_uint32), ] - CUDA_ARRAY_DESCRIPTOR_v2 = struct_CUDA_ARRAY_DESCRIPTOR_st CUDA_ARRAY_DESCRIPTOR = struct_CUDA_ARRAY_DESCRIPTOR_st -class struct_CUDA_ARRAY3D_DESCRIPTOR_st(Structure): - pass - -struct_CUDA_ARRAY3D_DESCRIPTOR_st._pack_ = 1 # source:False +class struct_CUDA_ARRAY3D_DESCRIPTOR_st(Struct): pass struct_CUDA_ARRAY3D_DESCRIPTOR_st._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('Width', size_t), + ('Height', size_t), + ('Depth', size_t), + ('Format', CUarray_format), + ('NumChannels', ctypes.c_uint32), + ('Flags', ctypes.c_uint32), ] - CUDA_ARRAY3D_DESCRIPTOR_v2 = struct_CUDA_ARRAY3D_DESCRIPTOR_st CUDA_ARRAY3D_DESCRIPTOR = struct_CUDA_ARRAY3D_DESCRIPTOR_st -class struct_CUDA_ARRAY_SPARSE_PROPERTIES_st(Structure): - pass - -class struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent(Structure): - pass - -struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent._pack_ = 1 # source:False +class struct_CUDA_ARRAY_SPARSE_PROPERTIES_st(Struct): pass +class struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent(Struct): pass struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depth', ctypes.c_uint32), + ('width', ctypes.c_uint32), + ('height', ctypes.c_uint32), + ('depth', ctypes.c_uint32), ] - -struct_CUDA_ARRAY_SPARSE_PROPERTIES_st._pack_ = 1 # source:False struct_CUDA_ARRAY_SPARSE_PROPERTIES_st._fields_ = [ - ('tileExtent', struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent), - ('miptailFirstLevel', ctypes.c_uint32), - ('miptailSize', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 4), - ('PADDING_0', ctypes.c_ubyte * 4), + ('tileExtent', struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent), + ('miptailFirstLevel', ctypes.c_uint32), + ('miptailSize', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 4)), ] - CUDA_ARRAY_SPARSE_PROPERTIES_v1 = struct_CUDA_ARRAY_SPARSE_PROPERTIES_st CUDA_ARRAY_SPARSE_PROPERTIES = struct_CUDA_ARRAY_SPARSE_PROPERTIES_st -class struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st(Structure): - pass - -struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st._pack_ = 1 # source:False +class struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st(Struct): pass struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st._fields_ = [ - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('reserved', ctypes.c_uint32 * 4), + ('size', size_t), + ('alignment', size_t), + ('reserved', (ctypes.c_uint32 * 4)), ] - CUDA_ARRAY_MEMORY_REQUIREMENTS_v1 = struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st CUDA_ARRAY_MEMORY_REQUIREMENTS = struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st -class struct_CUDA_RESOURCE_DESC_st(Structure): - pass - -class union_CUDA_RESOURCE_DESC_st_res(Union): - pass - -class struct_CUDA_RESOURCE_DESC_st_0_array(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_array._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_array._fields_ = [ - ('hArray', ctypes.POINTER(struct_CUarray_st)), +class struct_CUDA_RESOURCE_DESC_st(Struct): pass +class struct_CUDA_RESOURCE_DESC_st_res(ctypes.Union): pass +class struct_CUDA_RESOURCE_DESC_st_res_array(Struct): pass +struct_CUDA_RESOURCE_DESC_st_res_array._fields_ = [ + ('hArray', CUarray), ] - -class struct_CUDA_RESOURCE_DESC_st_0_mipmap(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_mipmap._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_mipmap._fields_ = [ - ('hMipmappedArray', ctypes.POINTER(struct_CUmipmappedArray_st)), +class struct_CUDA_RESOURCE_DESC_st_res_mipmap(Struct): pass +struct_CUDA_RESOURCE_DESC_st_res_mipmap._fields_ = [ + ('hMipmappedArray', CUmipmappedArray), ] - -class struct_CUDA_RESOURCE_DESC_st_0_linear(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_linear._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_linear._fields_ = [ - ('devPtr', ctypes.c_uint64), - ('format', CUarray_format), - ('numChannels', ctypes.c_uint32), - ('sizeInBytes', ctypes.c_uint64), +class struct_CUDA_RESOURCE_DESC_st_res_linear(Struct): pass +struct_CUDA_RESOURCE_DESC_st_res_linear._fields_ = [ + ('devPtr', CUdeviceptr), + ('format', CUarray_format), + ('numChannels', ctypes.c_uint32), + ('sizeInBytes', size_t), ] - -class struct_CUDA_RESOURCE_DESC_st_0_pitch2D(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_pitch2D._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_pitch2D._fields_ = [ - ('devPtr', ctypes.c_uint64), - ('format', CUarray_format), - ('numChannels', ctypes.c_uint32), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('pitchInBytes', ctypes.c_uint64), +class struct_CUDA_RESOURCE_DESC_st_res_pitch2D(Struct): pass +struct_CUDA_RESOURCE_DESC_st_res_pitch2D._fields_ = [ + ('devPtr', CUdeviceptr), + ('format', CUarray_format), + ('numChannels', ctypes.c_uint32), + ('width', size_t), + ('height', size_t), + ('pitchInBytes', size_t), ] - -class struct_CUDA_RESOURCE_DESC_st_0_reserved(Structure): - pass - -struct_CUDA_RESOURCE_DESC_st_0_reserved._pack_ = 1 # source:False -struct_CUDA_RESOURCE_DESC_st_0_reserved._fields_ = [ - ('reserved', ctypes.c_int32 * 32), +class struct_CUDA_RESOURCE_DESC_st_res_reserved(Struct): pass +struct_CUDA_RESOURCE_DESC_st_res_reserved._fields_ = [ + ('reserved', (ctypes.c_int32 * 32)), ] - -union_CUDA_RESOURCE_DESC_st_res._pack_ = 1 # source:False -union_CUDA_RESOURCE_DESC_st_res._fields_ = [ - ('array', struct_CUDA_RESOURCE_DESC_st_0_array), - ('mipmap', struct_CUDA_RESOURCE_DESC_st_0_mipmap), - ('linear', struct_CUDA_RESOURCE_DESC_st_0_linear), - ('pitch2D', struct_CUDA_RESOURCE_DESC_st_0_pitch2D), - ('reserved', struct_CUDA_RESOURCE_DESC_st_0_reserved), +struct_CUDA_RESOURCE_DESC_st_res._fields_ = [ + ('array', struct_CUDA_RESOURCE_DESC_st_res_array), + ('mipmap', struct_CUDA_RESOURCE_DESC_st_res_mipmap), + ('linear', struct_CUDA_RESOURCE_DESC_st_res_linear), + ('pitch2D', struct_CUDA_RESOURCE_DESC_st_res_pitch2D), + ('reserved', struct_CUDA_RESOURCE_DESC_st_res_reserved), ] - -struct_CUDA_RESOURCE_DESC_st._pack_ = 1 # source:False struct_CUDA_RESOURCE_DESC_st._fields_ = [ - ('resType', CUresourcetype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('res', union_CUDA_RESOURCE_DESC_st_res), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('resType', CUresourcetype), + ('res', struct_CUDA_RESOURCE_DESC_st_res), + ('flags', ctypes.c_uint32), ] - CUDA_RESOURCE_DESC_v1 = struct_CUDA_RESOURCE_DESC_st CUDA_RESOURCE_DESC = struct_CUDA_RESOURCE_DESC_st -class struct_CUDA_TEXTURE_DESC_st(Structure): - pass - -struct_CUDA_TEXTURE_DESC_st._pack_ = 1 # source:False +class struct_CUDA_TEXTURE_DESC_st(Struct): pass struct_CUDA_TEXTURE_DESC_st._fields_ = [ - ('addressMode', CUaddress_mode_enum * 3), - ('filterMode', CUfilter_mode), - ('flags', ctypes.c_uint32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', CUfilter_mode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), - ('borderColor', ctypes.c_float * 4), - ('reserved', ctypes.c_int32 * 12), + ('addressMode', (CUaddress_mode * 3)), + ('filterMode', CUfilter_mode), + ('flags', ctypes.c_uint32), + ('maxAnisotropy', ctypes.c_uint32), + ('mipmapFilterMode', CUfilter_mode), + ('mipmapLevelBias', ctypes.c_float), + ('minMipmapLevelClamp', ctypes.c_float), + ('maxMipmapLevelClamp', ctypes.c_float), + ('borderColor', (ctypes.c_float * 4)), + ('reserved', (ctypes.c_int32 * 12)), ] - CUDA_TEXTURE_DESC_v1 = struct_CUDA_TEXTURE_DESC_st CUDA_TEXTURE_DESC = struct_CUDA_TEXTURE_DESC_st +enum_CUresourceViewFormat_enum = CEnum(ctypes.c_uint32) +CU_RES_VIEW_FORMAT_NONE = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_NONE', 0) +CU_RES_VIEW_FORMAT_UINT_1X8 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_1X8', 1) +CU_RES_VIEW_FORMAT_UINT_2X8 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_2X8', 2) +CU_RES_VIEW_FORMAT_UINT_4X8 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_4X8', 3) +CU_RES_VIEW_FORMAT_SINT_1X8 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_1X8', 4) +CU_RES_VIEW_FORMAT_SINT_2X8 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_2X8', 5) +CU_RES_VIEW_FORMAT_SINT_4X8 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_4X8', 6) +CU_RES_VIEW_FORMAT_UINT_1X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_1X16', 7) +CU_RES_VIEW_FORMAT_UINT_2X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_2X16', 8) +CU_RES_VIEW_FORMAT_UINT_4X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_4X16', 9) +CU_RES_VIEW_FORMAT_SINT_1X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_1X16', 10) +CU_RES_VIEW_FORMAT_SINT_2X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_2X16', 11) +CU_RES_VIEW_FORMAT_SINT_4X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_4X16', 12) +CU_RES_VIEW_FORMAT_UINT_1X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_1X32', 13) +CU_RES_VIEW_FORMAT_UINT_2X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_2X32', 14) +CU_RES_VIEW_FORMAT_UINT_4X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UINT_4X32', 15) +CU_RES_VIEW_FORMAT_SINT_1X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_1X32', 16) +CU_RES_VIEW_FORMAT_SINT_2X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_2X32', 17) +CU_RES_VIEW_FORMAT_SINT_4X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SINT_4X32', 18) +CU_RES_VIEW_FORMAT_FLOAT_1X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_FLOAT_1X16', 19) +CU_RES_VIEW_FORMAT_FLOAT_2X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_FLOAT_2X16', 20) +CU_RES_VIEW_FORMAT_FLOAT_4X16 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_FLOAT_4X16', 21) +CU_RES_VIEW_FORMAT_FLOAT_1X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_FLOAT_1X32', 22) +CU_RES_VIEW_FORMAT_FLOAT_2X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_FLOAT_2X32', 23) +CU_RES_VIEW_FORMAT_FLOAT_4X32 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_FLOAT_4X32', 24) +CU_RES_VIEW_FORMAT_UNSIGNED_BC1 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC1', 25) +CU_RES_VIEW_FORMAT_UNSIGNED_BC2 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC2', 26) +CU_RES_VIEW_FORMAT_UNSIGNED_BC3 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC3', 27) +CU_RES_VIEW_FORMAT_UNSIGNED_BC4 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC4', 28) +CU_RES_VIEW_FORMAT_SIGNED_BC4 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SIGNED_BC4', 29) +CU_RES_VIEW_FORMAT_UNSIGNED_BC5 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC5', 30) +CU_RES_VIEW_FORMAT_SIGNED_BC5 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SIGNED_BC5', 31) +CU_RES_VIEW_FORMAT_UNSIGNED_BC6H = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC6H', 32) +CU_RES_VIEW_FORMAT_SIGNED_BC6H = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_SIGNED_BC6H', 33) +CU_RES_VIEW_FORMAT_UNSIGNED_BC7 = enum_CUresourceViewFormat_enum.define('CU_RES_VIEW_FORMAT_UNSIGNED_BC7', 34) -# values for enumeration 'CUresourceViewFormat_enum' -CUresourceViewFormat_enum__enumvalues = { - 0: 'CU_RES_VIEW_FORMAT_NONE', - 1: 'CU_RES_VIEW_FORMAT_UINT_1X8', - 2: 'CU_RES_VIEW_FORMAT_UINT_2X8', - 3: 'CU_RES_VIEW_FORMAT_UINT_4X8', - 4: 'CU_RES_VIEW_FORMAT_SINT_1X8', - 5: 'CU_RES_VIEW_FORMAT_SINT_2X8', - 6: 'CU_RES_VIEW_FORMAT_SINT_4X8', - 7: 'CU_RES_VIEW_FORMAT_UINT_1X16', - 8: 'CU_RES_VIEW_FORMAT_UINT_2X16', - 9: 'CU_RES_VIEW_FORMAT_UINT_4X16', - 10: 'CU_RES_VIEW_FORMAT_SINT_1X16', - 11: 'CU_RES_VIEW_FORMAT_SINT_2X16', - 12: 'CU_RES_VIEW_FORMAT_SINT_4X16', - 13: 'CU_RES_VIEW_FORMAT_UINT_1X32', - 14: 'CU_RES_VIEW_FORMAT_UINT_2X32', - 15: 'CU_RES_VIEW_FORMAT_UINT_4X32', - 16: 'CU_RES_VIEW_FORMAT_SINT_1X32', - 17: 'CU_RES_VIEW_FORMAT_SINT_2X32', - 18: 'CU_RES_VIEW_FORMAT_SINT_4X32', - 19: 'CU_RES_VIEW_FORMAT_FLOAT_1X16', - 20: 'CU_RES_VIEW_FORMAT_FLOAT_2X16', - 21: 'CU_RES_VIEW_FORMAT_FLOAT_4X16', - 22: 'CU_RES_VIEW_FORMAT_FLOAT_1X32', - 23: 'CU_RES_VIEW_FORMAT_FLOAT_2X32', - 24: 'CU_RES_VIEW_FORMAT_FLOAT_4X32', - 25: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC1', - 26: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC2', - 27: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC3', - 28: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC4', - 29: 'CU_RES_VIEW_FORMAT_SIGNED_BC4', - 30: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC5', - 31: 'CU_RES_VIEW_FORMAT_SIGNED_BC5', - 32: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 33: 'CU_RES_VIEW_FORMAT_SIGNED_BC6H', - 34: 'CU_RES_VIEW_FORMAT_UNSIGNED_BC7', -} -CU_RES_VIEW_FORMAT_NONE = 0 -CU_RES_VIEW_FORMAT_UINT_1X8 = 1 -CU_RES_VIEW_FORMAT_UINT_2X8 = 2 -CU_RES_VIEW_FORMAT_UINT_4X8 = 3 -CU_RES_VIEW_FORMAT_SINT_1X8 = 4 -CU_RES_VIEW_FORMAT_SINT_2X8 = 5 -CU_RES_VIEW_FORMAT_SINT_4X8 = 6 -CU_RES_VIEW_FORMAT_UINT_1X16 = 7 -CU_RES_VIEW_FORMAT_UINT_2X16 = 8 -CU_RES_VIEW_FORMAT_UINT_4X16 = 9 -CU_RES_VIEW_FORMAT_SINT_1X16 = 10 -CU_RES_VIEW_FORMAT_SINT_2X16 = 11 -CU_RES_VIEW_FORMAT_SINT_4X16 = 12 -CU_RES_VIEW_FORMAT_UINT_1X32 = 13 -CU_RES_VIEW_FORMAT_UINT_2X32 = 14 -CU_RES_VIEW_FORMAT_UINT_4X32 = 15 -CU_RES_VIEW_FORMAT_SINT_1X32 = 16 -CU_RES_VIEW_FORMAT_SINT_2X32 = 17 -CU_RES_VIEW_FORMAT_SINT_4X32 = 18 -CU_RES_VIEW_FORMAT_FLOAT_1X16 = 19 -CU_RES_VIEW_FORMAT_FLOAT_2X16 = 20 -CU_RES_VIEW_FORMAT_FLOAT_4X16 = 21 -CU_RES_VIEW_FORMAT_FLOAT_1X32 = 22 -CU_RES_VIEW_FORMAT_FLOAT_2X32 = 23 -CU_RES_VIEW_FORMAT_FLOAT_4X32 = 24 -CU_RES_VIEW_FORMAT_UNSIGNED_BC1 = 25 -CU_RES_VIEW_FORMAT_UNSIGNED_BC2 = 26 -CU_RES_VIEW_FORMAT_UNSIGNED_BC3 = 27 -CU_RES_VIEW_FORMAT_UNSIGNED_BC4 = 28 -CU_RES_VIEW_FORMAT_SIGNED_BC4 = 29 -CU_RES_VIEW_FORMAT_UNSIGNED_BC5 = 30 -CU_RES_VIEW_FORMAT_SIGNED_BC5 = 31 -CU_RES_VIEW_FORMAT_UNSIGNED_BC6H = 32 -CU_RES_VIEW_FORMAT_SIGNED_BC6H = 33 -CU_RES_VIEW_FORMAT_UNSIGNED_BC7 = 34 -CUresourceViewFormat_enum = ctypes.c_uint32 # enum -CUresourceViewFormat = CUresourceViewFormat_enum -CUresourceViewFormat__enumvalues = CUresourceViewFormat_enum__enumvalues -class struct_CUDA_RESOURCE_VIEW_DESC_st(Structure): - pass - -struct_CUDA_RESOURCE_VIEW_DESC_st._pack_ = 1 # source:False +CUresourceViewFormat = enum_CUresourceViewFormat_enum +class struct_CUDA_RESOURCE_VIEW_DESC_st(Struct): pass struct_CUDA_RESOURCE_VIEW_DESC_st._fields_ = [ - ('format', CUresourceViewFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('firstMipmapLevel', ctypes.c_uint32), - ('lastMipmapLevel', ctypes.c_uint32), - ('firstLayer', ctypes.c_uint32), - ('lastLayer', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), + ('format', CUresourceViewFormat), + ('width', size_t), + ('height', size_t), + ('depth', size_t), + ('firstMipmapLevel', ctypes.c_uint32), + ('lastMipmapLevel', ctypes.c_uint32), + ('firstLayer', ctypes.c_uint32), + ('lastLayer', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_RESOURCE_VIEW_DESC_v1 = struct_CUDA_RESOURCE_VIEW_DESC_st CUDA_RESOURCE_VIEW_DESC = struct_CUDA_RESOURCE_VIEW_DESC_st -class struct_CUtensorMap_st(Structure): - pass - -struct_CUtensorMap_st._pack_ = 1 # source:False +class struct_CUtensorMap_st(Struct): pass struct_CUtensorMap_st._fields_ = [ - ('opaque', ctypes.c_uint64 * 16), + ('opaque', (cuuint64_t * 16)), ] - CUtensorMap = struct_CUtensorMap_st +enum_CUtensorMapDataType_enum = CEnum(ctypes.c_uint32) +CU_TENSOR_MAP_DATA_TYPE_UINT8 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_UINT8', 0) +CU_TENSOR_MAP_DATA_TYPE_UINT16 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_UINT16', 1) +CU_TENSOR_MAP_DATA_TYPE_UINT32 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_UINT32', 2) +CU_TENSOR_MAP_DATA_TYPE_INT32 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_INT32', 3) +CU_TENSOR_MAP_DATA_TYPE_UINT64 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_UINT64', 4) +CU_TENSOR_MAP_DATA_TYPE_INT64 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_INT64', 5) +CU_TENSOR_MAP_DATA_TYPE_FLOAT16 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_FLOAT16', 6) +CU_TENSOR_MAP_DATA_TYPE_FLOAT32 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_FLOAT32', 7) +CU_TENSOR_MAP_DATA_TYPE_FLOAT64 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_FLOAT64', 8) +CU_TENSOR_MAP_DATA_TYPE_BFLOAT16 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_BFLOAT16', 9) +CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ', 10) +CU_TENSOR_MAP_DATA_TYPE_TFLOAT32 = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_TFLOAT32', 11) +CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ = enum_CUtensorMapDataType_enum.define('CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ', 12) -# values for enumeration 'CUtensorMapDataType_enum' -CUtensorMapDataType_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_DATA_TYPE_UINT8', - 1: 'CU_TENSOR_MAP_DATA_TYPE_UINT16', - 2: 'CU_TENSOR_MAP_DATA_TYPE_UINT32', - 3: 'CU_TENSOR_MAP_DATA_TYPE_INT32', - 4: 'CU_TENSOR_MAP_DATA_TYPE_UINT64', - 5: 'CU_TENSOR_MAP_DATA_TYPE_INT64', - 6: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT16', - 7: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32', - 8: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT64', - 9: 'CU_TENSOR_MAP_DATA_TYPE_BFLOAT16', - 10: 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ', - 11: 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32', - 12: 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ', -} -CU_TENSOR_MAP_DATA_TYPE_UINT8 = 0 -CU_TENSOR_MAP_DATA_TYPE_UINT16 = 1 -CU_TENSOR_MAP_DATA_TYPE_UINT32 = 2 -CU_TENSOR_MAP_DATA_TYPE_INT32 = 3 -CU_TENSOR_MAP_DATA_TYPE_UINT64 = 4 -CU_TENSOR_MAP_DATA_TYPE_INT64 = 5 -CU_TENSOR_MAP_DATA_TYPE_FLOAT16 = 6 -CU_TENSOR_MAP_DATA_TYPE_FLOAT32 = 7 -CU_TENSOR_MAP_DATA_TYPE_FLOAT64 = 8 -CU_TENSOR_MAP_DATA_TYPE_BFLOAT16 = 9 -CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ = 10 -CU_TENSOR_MAP_DATA_TYPE_TFLOAT32 = 11 -CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ = 12 -CUtensorMapDataType_enum = ctypes.c_uint32 # enum -CUtensorMapDataType = CUtensorMapDataType_enum -CUtensorMapDataType__enumvalues = CUtensorMapDataType_enum__enumvalues +CUtensorMapDataType = enum_CUtensorMapDataType_enum +enum_CUtensorMapInterleave_enum = CEnum(ctypes.c_uint32) +CU_TENSOR_MAP_INTERLEAVE_NONE = enum_CUtensorMapInterleave_enum.define('CU_TENSOR_MAP_INTERLEAVE_NONE', 0) +CU_TENSOR_MAP_INTERLEAVE_16B = enum_CUtensorMapInterleave_enum.define('CU_TENSOR_MAP_INTERLEAVE_16B', 1) +CU_TENSOR_MAP_INTERLEAVE_32B = enum_CUtensorMapInterleave_enum.define('CU_TENSOR_MAP_INTERLEAVE_32B', 2) -# values for enumeration 'CUtensorMapInterleave_enum' -CUtensorMapInterleave_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_INTERLEAVE_NONE', - 1: 'CU_TENSOR_MAP_INTERLEAVE_16B', - 2: 'CU_TENSOR_MAP_INTERLEAVE_32B', -} -CU_TENSOR_MAP_INTERLEAVE_NONE = 0 -CU_TENSOR_MAP_INTERLEAVE_16B = 1 -CU_TENSOR_MAP_INTERLEAVE_32B = 2 -CUtensorMapInterleave_enum = ctypes.c_uint32 # enum -CUtensorMapInterleave = CUtensorMapInterleave_enum -CUtensorMapInterleave__enumvalues = CUtensorMapInterleave_enum__enumvalues +CUtensorMapInterleave = enum_CUtensorMapInterleave_enum +enum_CUtensorMapSwizzle_enum = CEnum(ctypes.c_uint32) +CU_TENSOR_MAP_SWIZZLE_NONE = enum_CUtensorMapSwizzle_enum.define('CU_TENSOR_MAP_SWIZZLE_NONE', 0) +CU_TENSOR_MAP_SWIZZLE_32B = enum_CUtensorMapSwizzle_enum.define('CU_TENSOR_MAP_SWIZZLE_32B', 1) +CU_TENSOR_MAP_SWIZZLE_64B = enum_CUtensorMapSwizzle_enum.define('CU_TENSOR_MAP_SWIZZLE_64B', 2) +CU_TENSOR_MAP_SWIZZLE_128B = enum_CUtensorMapSwizzle_enum.define('CU_TENSOR_MAP_SWIZZLE_128B', 3) -# values for enumeration 'CUtensorMapSwizzle_enum' -CUtensorMapSwizzle_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_SWIZZLE_NONE', - 1: 'CU_TENSOR_MAP_SWIZZLE_32B', - 2: 'CU_TENSOR_MAP_SWIZZLE_64B', - 3: 'CU_TENSOR_MAP_SWIZZLE_128B', -} -CU_TENSOR_MAP_SWIZZLE_NONE = 0 -CU_TENSOR_MAP_SWIZZLE_32B = 1 -CU_TENSOR_MAP_SWIZZLE_64B = 2 -CU_TENSOR_MAP_SWIZZLE_128B = 3 -CUtensorMapSwizzle_enum = ctypes.c_uint32 # enum -CUtensorMapSwizzle = CUtensorMapSwizzle_enum -CUtensorMapSwizzle__enumvalues = CUtensorMapSwizzle_enum__enumvalues +CUtensorMapSwizzle = enum_CUtensorMapSwizzle_enum +enum_CUtensorMapL2promotion_enum = CEnum(ctypes.c_uint32) +CU_TENSOR_MAP_L2_PROMOTION_NONE = enum_CUtensorMapL2promotion_enum.define('CU_TENSOR_MAP_L2_PROMOTION_NONE', 0) +CU_TENSOR_MAP_L2_PROMOTION_L2_64B = enum_CUtensorMapL2promotion_enum.define('CU_TENSOR_MAP_L2_PROMOTION_L2_64B', 1) +CU_TENSOR_MAP_L2_PROMOTION_L2_128B = enum_CUtensorMapL2promotion_enum.define('CU_TENSOR_MAP_L2_PROMOTION_L2_128B', 2) +CU_TENSOR_MAP_L2_PROMOTION_L2_256B = enum_CUtensorMapL2promotion_enum.define('CU_TENSOR_MAP_L2_PROMOTION_L2_256B', 3) -# values for enumeration 'CUtensorMapL2promotion_enum' -CUtensorMapL2promotion_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_L2_PROMOTION_NONE', - 1: 'CU_TENSOR_MAP_L2_PROMOTION_L2_64B', - 2: 'CU_TENSOR_MAP_L2_PROMOTION_L2_128B', - 3: 'CU_TENSOR_MAP_L2_PROMOTION_L2_256B', -} -CU_TENSOR_MAP_L2_PROMOTION_NONE = 0 -CU_TENSOR_MAP_L2_PROMOTION_L2_64B = 1 -CU_TENSOR_MAP_L2_PROMOTION_L2_128B = 2 -CU_TENSOR_MAP_L2_PROMOTION_L2_256B = 3 -CUtensorMapL2promotion_enum = ctypes.c_uint32 # enum -CUtensorMapL2promotion = CUtensorMapL2promotion_enum -CUtensorMapL2promotion__enumvalues = CUtensorMapL2promotion_enum__enumvalues +CUtensorMapL2promotion = enum_CUtensorMapL2promotion_enum +enum_CUtensorMapFloatOOBfill_enum = CEnum(ctypes.c_uint32) +CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE = enum_CUtensorMapFloatOOBfill_enum.define('CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE', 0) +CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA = enum_CUtensorMapFloatOOBfill_enum.define('CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA', 1) -# values for enumeration 'CUtensorMapFloatOOBfill_enum' -CUtensorMapFloatOOBfill_enum__enumvalues = { - 0: 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE', - 1: 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA', -} -CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE = 0 -CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA = 1 -CUtensorMapFloatOOBfill_enum = ctypes.c_uint32 # enum -CUtensorMapFloatOOBfill = CUtensorMapFloatOOBfill_enum -CUtensorMapFloatOOBfill__enumvalues = CUtensorMapFloatOOBfill_enum__enumvalues -class struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st(Structure): - pass - -struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st._pack_ = 1 # source:False +CUtensorMapFloatOOBfill = enum_CUtensorMapFloatOOBfill_enum +class struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st(Struct): pass struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st._fields_ = [ - ('p2pToken', ctypes.c_uint64), - ('vaSpaceToken', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('p2pToken', ctypes.c_uint64), + ('vaSpaceToken', ctypes.c_uint32), ] - CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_v1 = struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st CUDA_POINTER_ATTRIBUTE_P2P_TOKENS = struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st +enum_CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum = CEnum(ctypes.c_uint32) +CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE = enum_CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum.define('CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE', 0) +CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ = enum_CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum.define('CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ', 1) +CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE = enum_CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum.define('CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE', 3) -# values for enumeration 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum' -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum__enumvalues = { - 0: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE', - 1: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ', - 3: 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE', -} -CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE = 0 -CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ = 1 -CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE = 3 -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum = ctypes.c_uint32 # enum -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS = CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum -CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS__enumvalues = CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum__enumvalues -class struct_CUDA_LAUNCH_PARAMS_st(Structure): - pass - -struct_CUDA_LAUNCH_PARAMS_st._pack_ = 1 # source:False +CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS = enum_CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum +class struct_CUDA_LAUNCH_PARAMS_st(Struct): pass struct_CUDA_LAUNCH_PARAMS_st._fields_ = [ - ('function', ctypes.POINTER(struct_CUfunc_st)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hStream', ctypes.POINTER(struct_CUstream_st)), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), + ('function', CUfunction), + ('gridDimX', ctypes.c_uint32), + ('gridDimY', ctypes.c_uint32), + ('gridDimZ', ctypes.c_uint32), + ('blockDimX', ctypes.c_uint32), + ('blockDimY', ctypes.c_uint32), + ('blockDimZ', ctypes.c_uint32), + ('sharedMemBytes', ctypes.c_uint32), + ('hStream', CUstream), + ('kernelParams', ctypes.POINTER(ctypes.c_void_p)), ] - CUDA_LAUNCH_PARAMS_v1 = struct_CUDA_LAUNCH_PARAMS_st CUDA_LAUNCH_PARAMS = struct_CUDA_LAUNCH_PARAMS_st +enum_CUexternalMemoryHandleType_enum = CEnum(ctypes.c_uint32) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD', 1) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32 = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32', 2) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT', 3) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP', 4) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE', 5) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE', 6) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT', 7) +CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF = enum_CUexternalMemoryHandleType_enum.define('CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF', 8) -# values for enumeration 'CUexternalMemoryHandleType_enum' -CUexternalMemoryHandleType_enum__enumvalues = { - 1: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD', - 2: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32', - 3: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 4: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP', - 5: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE', - 6: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE', - 7: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT', - 8: 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF', -} -CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD = 1 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32 = 2 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT = 3 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP = 4 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE = 5 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE = 6 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT = 7 -CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF = 8 -CUexternalMemoryHandleType_enum = ctypes.c_uint32 # enum -CUexternalMemoryHandleType = CUexternalMemoryHandleType_enum -CUexternalMemoryHandleType__enumvalues = CUexternalMemoryHandleType_enum__enumvalues -class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st(Structure): - pass - -class union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle(Union): - pass - -class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32(Structure): - pass - -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), +CUexternalMemoryHandleType = enum_CUexternalMemoryHandleType_enum +class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st(Struct): pass +class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle(ctypes.Union): pass +class struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle_win32(Struct): pass +struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle_win32._fields_ = [ + ('handle', ctypes.c_void_p), + ('name', ctypes.c_void_p), ] - -union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle._pack_ = 1 # source:False -union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32), - ('nvSciBufObject', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), +struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle._fields_ = [ + ('fd', ctypes.c_int32), + ('win32', struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle_win32), + ('nvSciBufObject', ctypes.c_void_p), ] - -struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st._pack_ = 1 # source:False struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st._fields_ = [ - ('type', CUexternalMemoryHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), + ('type', CUexternalMemoryHandleType), + ('handle', struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_EXTERNAL_MEMORY_HANDLE_DESC_v1 = struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st CUDA_EXTERNAL_MEMORY_HANDLE_DESC = struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st -class struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st(Structure): - pass - -struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st._pack_ = 1 # source:False +class struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st(Struct): pass struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), + ('offset', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_EXTERNAL_MEMORY_BUFFER_DESC_v1 = struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st CUDA_EXTERNAL_MEMORY_BUFFER_DESC = struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st -class struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st(Structure): - pass - -struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st._pack_ = 1 # source:False +class struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st(Struct): pass struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('arrayDesc', CUDA_ARRAY3D_DESCRIPTOR), - ('numLevels', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), + ('offset', ctypes.c_uint64), + ('arrayDesc', CUDA_ARRAY3D_DESCRIPTOR), + ('numLevels', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_v1 = struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC = struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st +enum_CUexternalSemaphoreHandleType_enum = CEnum(ctypes.c_uint32) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD', 1) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32 = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32', 2) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT', 3) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE', 4) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE', 5) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC', 6) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX', 7) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT', 8) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD', 9) +CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32 = enum_CUexternalSemaphoreHandleType_enum.define('CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32', 10) -# values for enumeration 'CUexternalSemaphoreHandleType_enum' -CUexternalSemaphoreHandleType_enum__enumvalues = { - 1: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD', - 2: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32', - 3: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 4: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE', - 5: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE', - 6: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC', - 7: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX', - 8: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT', - 9: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD', - 10: 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32', -} -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD = 1 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32 = 2 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT = 3 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE = 4 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE = 5 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC = 6 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX = 7 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT = 8 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD = 9 -CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32 = 10 -CUexternalSemaphoreHandleType_enum = ctypes.c_uint32 # enum -CUexternalSemaphoreHandleType = CUexternalSemaphoreHandleType_enum -CUexternalSemaphoreHandleType__enumvalues = CUexternalSemaphoreHandleType_enum__enumvalues -class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st(Structure): - pass - -class union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle(Union): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), +CUexternalSemaphoreHandleType = enum_CUexternalSemaphoreHandleType_enum +class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st(Struct): pass +class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle(ctypes.Union): pass +class struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle_win32(Struct): pass +struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle_win32._fields_ = [ + ('handle', ctypes.c_void_p), + ('name', ctypes.c_void_p), ] - -union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle._pack_ = 1 # source:False -union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32), - ('nvSciSyncObj', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), +struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle._fields_ = [ + ('fd', ctypes.c_int32), + ('win32', struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle_win32), + ('nvSciSyncObj', ctypes.c_void_p), ] - -struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st._pack_ = 1 # source:False struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st._fields_ = [ - ('type', CUexternalSemaphoreHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), + ('type', CUexternalSemaphoreHandleType), + ('handle', struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_v1 = struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC = struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), +class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st(Struct): pass +class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params(Struct): pass +class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_fence(Struct): pass +struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_fence._fields_ = [ + ('value', ctypes.c_uint64), ] - -class union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync(Union): - pass - -union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync._pack_ = 1 # source:False -union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), +class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_nvSciSync(ctypes.Union): pass +struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_nvSciSync._fields_ = [ + ('fence', ctypes.c_void_p), + ('reserved', ctypes.c_uint64), ] - -class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), +class struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_keyedMutex(Struct): pass +struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_keyedMutex._fields_ = [ + ('key', ctypes.c_uint64), ] - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params._pack_ = 1 # source:False struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params._fields_ = [ - ('fence', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence), - ('nvSciSync', union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync), - ('keyedMutex', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 12), + ('fence', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_fence), + ('nvSciSync', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_nvSciSync), + ('keyedMutex', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params_keyedMutex), + ('reserved', (ctypes.c_uint32 * 12)), ] - -struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st._pack_ = 1 # source:False struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st._fields_ = [ - ('params', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), + ('params', struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_v1 = struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS = struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params(Structure): - pass - -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), +class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st(Struct): pass +class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params(Struct): pass +class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_fence(Struct): pass +struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_fence._fields_ = [ + ('value', ctypes.c_uint64), ] - -class union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync(Union): - pass - -union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync._pack_ = 1 # source:False -union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), +class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_nvSciSync(ctypes.Union): pass +struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_nvSciSync._fields_ = [ + ('fence', ctypes.c_void_p), + ('reserved', ctypes.c_uint64), ] - -class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex(Structure): - pass - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex._pack_ = 1 # source:False -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), - ('timeoutMs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_keyedMutex(Struct): pass +struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_keyedMutex._fields_ = [ + ('key', ctypes.c_uint64), + ('timeoutMs', ctypes.c_uint32), ] - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params._pack_ = 1 # source:False struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params._fields_ = [ - ('fence', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence), - ('nvSciSync', union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync), - ('keyedMutex', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 10), + ('fence', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_fence), + ('nvSciSync', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_nvSciSync), + ('keyedMutex', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params_keyedMutex), + ('reserved', (ctypes.c_uint32 * 10)), ] - -struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st._pack_ = 1 # source:False struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st._fields_ = [ - ('params', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), + ('params', struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), ] - CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_v1 = struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS = struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st -class struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st(Struct): pass struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st))), - ('paramsArray', ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('extSemArray', ctypes.POINTER(CUexternalSemaphore)), + ('paramsArray', ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS)), + ('numExtSems', ctypes.c_uint32), ] - CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_v1 = struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st CUDA_EXT_SEM_SIGNAL_NODE_PARAMS = struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st -class struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st(Struct): pass struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st))), - ('paramsArray', ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('extSemArray', ctypes.POINTER(CUexternalSemaphore)), + ('paramsArray', ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS)), + ('numExtSems', ctypes.c_uint32), ] - CUDA_EXT_SEM_WAIT_NODE_PARAMS_v1 = struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st CUDA_EXT_SEM_WAIT_NODE_PARAMS = struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st CUmemGenericAllocationHandle_v1 = ctypes.c_uint64 CUmemGenericAllocationHandle = ctypes.c_uint64 +enum_CUmemAllocationHandleType_enum = CEnum(ctypes.c_uint32) +CU_MEM_HANDLE_TYPE_NONE = enum_CUmemAllocationHandleType_enum.define('CU_MEM_HANDLE_TYPE_NONE', 0) +CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR = enum_CUmemAllocationHandleType_enum.define('CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR', 1) +CU_MEM_HANDLE_TYPE_WIN32 = enum_CUmemAllocationHandleType_enum.define('CU_MEM_HANDLE_TYPE_WIN32', 2) +CU_MEM_HANDLE_TYPE_WIN32_KMT = enum_CUmemAllocationHandleType_enum.define('CU_MEM_HANDLE_TYPE_WIN32_KMT', 4) +CU_MEM_HANDLE_TYPE_MAX = enum_CUmemAllocationHandleType_enum.define('CU_MEM_HANDLE_TYPE_MAX', 2147483647) -# values for enumeration 'CUmemAllocationHandleType_enum' -CUmemAllocationHandleType_enum__enumvalues = { - 0: 'CU_MEM_HANDLE_TYPE_NONE', - 1: 'CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR', - 2: 'CU_MEM_HANDLE_TYPE_WIN32', - 4: 'CU_MEM_HANDLE_TYPE_WIN32_KMT', - 2147483647: 'CU_MEM_HANDLE_TYPE_MAX', -} -CU_MEM_HANDLE_TYPE_NONE = 0 -CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR = 1 -CU_MEM_HANDLE_TYPE_WIN32 = 2 -CU_MEM_HANDLE_TYPE_WIN32_KMT = 4 -CU_MEM_HANDLE_TYPE_MAX = 2147483647 -CUmemAllocationHandleType_enum = ctypes.c_uint32 # enum -CUmemAllocationHandleType = CUmemAllocationHandleType_enum -CUmemAllocationHandleType__enumvalues = CUmemAllocationHandleType_enum__enumvalues +CUmemAllocationHandleType = enum_CUmemAllocationHandleType_enum +enum_CUmemAccess_flags_enum = CEnum(ctypes.c_uint32) +CU_MEM_ACCESS_FLAGS_PROT_NONE = enum_CUmemAccess_flags_enum.define('CU_MEM_ACCESS_FLAGS_PROT_NONE', 0) +CU_MEM_ACCESS_FLAGS_PROT_READ = enum_CUmemAccess_flags_enum.define('CU_MEM_ACCESS_FLAGS_PROT_READ', 1) +CU_MEM_ACCESS_FLAGS_PROT_READWRITE = enum_CUmemAccess_flags_enum.define('CU_MEM_ACCESS_FLAGS_PROT_READWRITE', 3) +CU_MEM_ACCESS_FLAGS_PROT_MAX = enum_CUmemAccess_flags_enum.define('CU_MEM_ACCESS_FLAGS_PROT_MAX', 2147483647) -# values for enumeration 'CUmemAccess_flags_enum' -CUmemAccess_flags_enum__enumvalues = { - 0: 'CU_MEM_ACCESS_FLAGS_PROT_NONE', - 1: 'CU_MEM_ACCESS_FLAGS_PROT_READ', - 3: 'CU_MEM_ACCESS_FLAGS_PROT_READWRITE', - 2147483647: 'CU_MEM_ACCESS_FLAGS_PROT_MAX', -} -CU_MEM_ACCESS_FLAGS_PROT_NONE = 0 -CU_MEM_ACCESS_FLAGS_PROT_READ = 1 -CU_MEM_ACCESS_FLAGS_PROT_READWRITE = 3 -CU_MEM_ACCESS_FLAGS_PROT_MAX = 2147483647 -CUmemAccess_flags_enum = ctypes.c_uint32 # enum -CUmemAccess_flags = CUmemAccess_flags_enum -CUmemAccess_flags__enumvalues = CUmemAccess_flags_enum__enumvalues +CUmemAccess_flags = enum_CUmemAccess_flags_enum +enum_CUmemLocationType_enum = CEnum(ctypes.c_uint32) +CU_MEM_LOCATION_TYPE_INVALID = enum_CUmemLocationType_enum.define('CU_MEM_LOCATION_TYPE_INVALID', 0) +CU_MEM_LOCATION_TYPE_DEVICE = enum_CUmemLocationType_enum.define('CU_MEM_LOCATION_TYPE_DEVICE', 1) +CU_MEM_LOCATION_TYPE_MAX = enum_CUmemLocationType_enum.define('CU_MEM_LOCATION_TYPE_MAX', 2147483647) -# values for enumeration 'CUmemLocationType_enum' -CUmemLocationType_enum__enumvalues = { - 0: 'CU_MEM_LOCATION_TYPE_INVALID', - 1: 'CU_MEM_LOCATION_TYPE_DEVICE', - 2147483647: 'CU_MEM_LOCATION_TYPE_MAX', -} -CU_MEM_LOCATION_TYPE_INVALID = 0 -CU_MEM_LOCATION_TYPE_DEVICE = 1 -CU_MEM_LOCATION_TYPE_MAX = 2147483647 -CUmemLocationType_enum = ctypes.c_uint32 # enum -CUmemLocationType = CUmemLocationType_enum -CUmemLocationType__enumvalues = CUmemLocationType_enum__enumvalues +CUmemLocationType = enum_CUmemLocationType_enum +enum_CUmemAllocationType_enum = CEnum(ctypes.c_uint32) +CU_MEM_ALLOCATION_TYPE_INVALID = enum_CUmemAllocationType_enum.define('CU_MEM_ALLOCATION_TYPE_INVALID', 0) +CU_MEM_ALLOCATION_TYPE_PINNED = enum_CUmemAllocationType_enum.define('CU_MEM_ALLOCATION_TYPE_PINNED', 1) +CU_MEM_ALLOCATION_TYPE_MAX = enum_CUmemAllocationType_enum.define('CU_MEM_ALLOCATION_TYPE_MAX', 2147483647) -# values for enumeration 'CUmemAllocationType_enum' -CUmemAllocationType_enum__enumvalues = { - 0: 'CU_MEM_ALLOCATION_TYPE_INVALID', - 1: 'CU_MEM_ALLOCATION_TYPE_PINNED', - 2147483647: 'CU_MEM_ALLOCATION_TYPE_MAX', -} -CU_MEM_ALLOCATION_TYPE_INVALID = 0 -CU_MEM_ALLOCATION_TYPE_PINNED = 1 -CU_MEM_ALLOCATION_TYPE_MAX = 2147483647 -CUmemAllocationType_enum = ctypes.c_uint32 # enum -CUmemAllocationType = CUmemAllocationType_enum -CUmemAllocationType__enumvalues = CUmemAllocationType_enum__enumvalues +CUmemAllocationType = enum_CUmemAllocationType_enum +enum_CUmemAllocationGranularity_flags_enum = CEnum(ctypes.c_uint32) +CU_MEM_ALLOC_GRANULARITY_MINIMUM = enum_CUmemAllocationGranularity_flags_enum.define('CU_MEM_ALLOC_GRANULARITY_MINIMUM', 0) +CU_MEM_ALLOC_GRANULARITY_RECOMMENDED = enum_CUmemAllocationGranularity_flags_enum.define('CU_MEM_ALLOC_GRANULARITY_RECOMMENDED', 1) -# values for enumeration 'CUmemAllocationGranularity_flags_enum' -CUmemAllocationGranularity_flags_enum__enumvalues = { - 0: 'CU_MEM_ALLOC_GRANULARITY_MINIMUM', - 1: 'CU_MEM_ALLOC_GRANULARITY_RECOMMENDED', -} -CU_MEM_ALLOC_GRANULARITY_MINIMUM = 0 -CU_MEM_ALLOC_GRANULARITY_RECOMMENDED = 1 -CUmemAllocationGranularity_flags_enum = ctypes.c_uint32 # enum -CUmemAllocationGranularity_flags = CUmemAllocationGranularity_flags_enum -CUmemAllocationGranularity_flags__enumvalues = CUmemAllocationGranularity_flags_enum__enumvalues +CUmemAllocationGranularity_flags = enum_CUmemAllocationGranularity_flags_enum +enum_CUmemRangeHandleType_enum = CEnum(ctypes.c_uint32) +CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD = enum_CUmemRangeHandleType_enum.define('CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD', 1) +CU_MEM_RANGE_HANDLE_TYPE_MAX = enum_CUmemRangeHandleType_enum.define('CU_MEM_RANGE_HANDLE_TYPE_MAX', 2147483647) -# values for enumeration 'CUmemRangeHandleType_enum' -CUmemRangeHandleType_enum__enumvalues = { - 1: 'CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD', - 2147483647: 'CU_MEM_RANGE_HANDLE_TYPE_MAX', -} -CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD = 1 -CU_MEM_RANGE_HANDLE_TYPE_MAX = 2147483647 -CUmemRangeHandleType_enum = ctypes.c_uint32 # enum -CUmemRangeHandleType = CUmemRangeHandleType_enum -CUmemRangeHandleType__enumvalues = CUmemRangeHandleType_enum__enumvalues +CUmemRangeHandleType = enum_CUmemRangeHandleType_enum +enum_CUarraySparseSubresourceType_enum = CEnum(ctypes.c_uint32) +CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL = enum_CUarraySparseSubresourceType_enum.define('CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL', 0) +CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL = enum_CUarraySparseSubresourceType_enum.define('CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL', 1) -# values for enumeration 'CUarraySparseSubresourceType_enum' -CUarraySparseSubresourceType_enum__enumvalues = { - 0: 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL', - 1: 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL', -} -CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL = 0 -CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL = 1 -CUarraySparseSubresourceType_enum = ctypes.c_uint32 # enum -CUarraySparseSubresourceType = CUarraySparseSubresourceType_enum -CUarraySparseSubresourceType__enumvalues = CUarraySparseSubresourceType_enum__enumvalues +CUarraySparseSubresourceType = enum_CUarraySparseSubresourceType_enum +enum_CUmemOperationType_enum = CEnum(ctypes.c_uint32) +CU_MEM_OPERATION_TYPE_MAP = enum_CUmemOperationType_enum.define('CU_MEM_OPERATION_TYPE_MAP', 1) +CU_MEM_OPERATION_TYPE_UNMAP = enum_CUmemOperationType_enum.define('CU_MEM_OPERATION_TYPE_UNMAP', 2) -# values for enumeration 'CUmemOperationType_enum' -CUmemOperationType_enum__enumvalues = { - 1: 'CU_MEM_OPERATION_TYPE_MAP', - 2: 'CU_MEM_OPERATION_TYPE_UNMAP', -} -CU_MEM_OPERATION_TYPE_MAP = 1 -CU_MEM_OPERATION_TYPE_UNMAP = 2 -CUmemOperationType_enum = ctypes.c_uint32 # enum -CUmemOperationType = CUmemOperationType_enum -CUmemOperationType__enumvalues = CUmemOperationType_enum__enumvalues +CUmemOperationType = enum_CUmemOperationType_enum +enum_CUmemHandleType_enum = CEnum(ctypes.c_uint32) +CU_MEM_HANDLE_TYPE_GENERIC = enum_CUmemHandleType_enum.define('CU_MEM_HANDLE_TYPE_GENERIC', 0) -# values for enumeration 'CUmemHandleType_enum' -CUmemHandleType_enum__enumvalues = { - 0: 'CU_MEM_HANDLE_TYPE_GENERIC', -} -CU_MEM_HANDLE_TYPE_GENERIC = 0 -CUmemHandleType_enum = ctypes.c_uint32 # enum -CUmemHandleType = CUmemHandleType_enum -CUmemHandleType__enumvalues = CUmemHandleType_enum__enumvalues -class struct_CUarrayMapInfo_st(Structure): - pass - -class union_CUarrayMapInfo_st_resource(Union): - pass - -union_CUarrayMapInfo_st_resource._pack_ = 1 # source:False -union_CUarrayMapInfo_st_resource._fields_ = [ - ('mipmap', ctypes.POINTER(struct_CUmipmappedArray_st)), - ('array', ctypes.POINTER(struct_CUarray_st)), +CUmemHandleType = enum_CUmemHandleType_enum +class struct_CUarrayMapInfo_st(Struct): pass +class struct_CUarrayMapInfo_st_resource(ctypes.Union): pass +struct_CUarrayMapInfo_st_resource._fields_ = [ + ('mipmap', CUmipmappedArray), + ('array', CUarray), ] - -class union_CUarrayMapInfo_st_subresource(Union): - pass - -class struct_CUarrayMapInfo_st_1_sparseLevel(Structure): - pass - -struct_CUarrayMapInfo_st_1_sparseLevel._pack_ = 1 # source:False -struct_CUarrayMapInfo_st_1_sparseLevel._fields_ = [ - ('level', ctypes.c_uint32), - ('layer', ctypes.c_uint32), - ('offsetX', ctypes.c_uint32), - ('offsetY', ctypes.c_uint32), - ('offsetZ', ctypes.c_uint32), - ('extentWidth', ctypes.c_uint32), - ('extentHeight', ctypes.c_uint32), - ('extentDepth', ctypes.c_uint32), +class struct_CUarrayMapInfo_st_subresource(ctypes.Union): pass +class struct_CUarrayMapInfo_st_subresource_sparseLevel(Struct): pass +struct_CUarrayMapInfo_st_subresource_sparseLevel._fields_ = [ + ('level', ctypes.c_uint32), + ('layer', ctypes.c_uint32), + ('offsetX', ctypes.c_uint32), + ('offsetY', ctypes.c_uint32), + ('offsetZ', ctypes.c_uint32), + ('extentWidth', ctypes.c_uint32), + ('extentHeight', ctypes.c_uint32), + ('extentDepth', ctypes.c_uint32), ] - -class struct_CUarrayMapInfo_st_1_miptail(Structure): - pass - -struct_CUarrayMapInfo_st_1_miptail._pack_ = 1 # source:False -struct_CUarrayMapInfo_st_1_miptail._fields_ = [ - ('layer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), +class struct_CUarrayMapInfo_st_subresource_miptail(Struct): pass +struct_CUarrayMapInfo_st_subresource_miptail._fields_ = [ + ('layer', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('size', ctypes.c_uint64), ] - -union_CUarrayMapInfo_st_subresource._pack_ = 1 # source:False -union_CUarrayMapInfo_st_subresource._fields_ = [ - ('sparseLevel', struct_CUarrayMapInfo_st_1_sparseLevel), - ('miptail', struct_CUarrayMapInfo_st_1_miptail), - ('PADDING_0', ctypes.c_ubyte * 8), +struct_CUarrayMapInfo_st_subresource._fields_ = [ + ('sparseLevel', struct_CUarrayMapInfo_st_subresource_sparseLevel), + ('miptail', struct_CUarrayMapInfo_st_subresource_miptail), ] - -class union_CUarrayMapInfo_st_memHandle(Union): - pass - -union_CUarrayMapInfo_st_memHandle._pack_ = 1 # source:False -union_CUarrayMapInfo_st_memHandle._fields_ = [ - ('memHandle', ctypes.c_uint64), +class struct_CUarrayMapInfo_st_memHandle(ctypes.Union): pass +struct_CUarrayMapInfo_st_memHandle._fields_ = [ + ('memHandle', CUmemGenericAllocationHandle), ] - -struct_CUarrayMapInfo_st._pack_ = 1 # source:False struct_CUarrayMapInfo_st._fields_ = [ - ('resourceType', CUresourcetype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resource', union_CUarrayMapInfo_st_resource), - ('subresourceType', CUarraySparseSubresourceType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('subresource', union_CUarrayMapInfo_st_subresource), - ('memOperationType', CUmemOperationType), - ('memHandleType', CUmemHandleType), - ('memHandle', union_CUarrayMapInfo_st_memHandle), - ('offset', ctypes.c_uint64), - ('deviceBitMask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 2), + ('resourceType', CUresourcetype), + ('resource', struct_CUarrayMapInfo_st_resource), + ('subresourceType', CUarraySparseSubresourceType), + ('subresource', struct_CUarrayMapInfo_st_subresource), + ('memOperationType', CUmemOperationType), + ('memHandleType', CUmemHandleType), + ('memHandle', struct_CUarrayMapInfo_st_memHandle), + ('offset', ctypes.c_uint64), + ('deviceBitMask', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 2)), ] - CUarrayMapInfo_v1 = struct_CUarrayMapInfo_st CUarrayMapInfo = struct_CUarrayMapInfo_st -class struct_CUmemLocation_st(Structure): - pass - -struct_CUmemLocation_st._pack_ = 1 # source:False +class struct_CUmemLocation_st(Struct): pass struct_CUmemLocation_st._fields_ = [ - ('type', CUmemLocationType), - ('id', ctypes.c_int32), + ('type', CUmemLocationType), + ('id', ctypes.c_int32), ] - CUmemLocation_v1 = struct_CUmemLocation_st CUmemLocation = struct_CUmemLocation_st +enum_CUmemAllocationCompType_enum = CEnum(ctypes.c_uint32) +CU_MEM_ALLOCATION_COMP_NONE = enum_CUmemAllocationCompType_enum.define('CU_MEM_ALLOCATION_COMP_NONE', 0) +CU_MEM_ALLOCATION_COMP_GENERIC = enum_CUmemAllocationCompType_enum.define('CU_MEM_ALLOCATION_COMP_GENERIC', 1) -# values for enumeration 'CUmemAllocationCompType_enum' -CUmemAllocationCompType_enum__enumvalues = { - 0: 'CU_MEM_ALLOCATION_COMP_NONE', - 1: 'CU_MEM_ALLOCATION_COMP_GENERIC', -} -CU_MEM_ALLOCATION_COMP_NONE = 0 -CU_MEM_ALLOCATION_COMP_GENERIC = 1 -CUmemAllocationCompType_enum = ctypes.c_uint32 # enum -CUmemAllocationCompType = CUmemAllocationCompType_enum -CUmemAllocationCompType__enumvalues = CUmemAllocationCompType_enum__enumvalues -class struct_CUmemAllocationProp_st(Structure): - pass - -class struct_CUmemAllocationProp_st_allocFlags(Structure): - pass - -struct_CUmemAllocationProp_st_allocFlags._pack_ = 1 # source:False +CUmemAllocationCompType = enum_CUmemAllocationCompType_enum +class struct_CUmemAllocationProp_st(Struct): pass +class struct_CUmemAllocationProp_st_allocFlags(Struct): pass struct_CUmemAllocationProp_st_allocFlags._fields_ = [ - ('compressionType', ctypes.c_ubyte), - ('gpuDirectRDMACapable', ctypes.c_ubyte), - ('usage', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 4), + ('compressionType', ctypes.c_ubyte), + ('gpuDirectRDMACapable', ctypes.c_ubyte), + ('usage', ctypes.c_uint16), + ('reserved', (ctypes.c_ubyte * 4)), ] - -struct_CUmemAllocationProp_st._pack_ = 1 # source:False struct_CUmemAllocationProp_st._fields_ = [ - ('type', CUmemAllocationType), - ('requestedHandleTypes', CUmemAllocationHandleType), - ('location', CUmemLocation), - ('win32HandleMetaData', ctypes.POINTER(None)), - ('allocFlags', struct_CUmemAllocationProp_st_allocFlags), + ('type', CUmemAllocationType), + ('requestedHandleTypes', CUmemAllocationHandleType), + ('location', CUmemLocation), + ('win32HandleMetaData', ctypes.c_void_p), + ('allocFlags', struct_CUmemAllocationProp_st_allocFlags), ] - CUmemAllocationProp_v1 = struct_CUmemAllocationProp_st CUmemAllocationProp = struct_CUmemAllocationProp_st -class struct_CUmemAccessDesc_st(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('location', CUmemLocation), - ('flags', CUmemAccess_flags), - ] - +class struct_CUmemAccessDesc_st(Struct): pass +struct_CUmemAccessDesc_st._fields_ = [ + ('location', CUmemLocation), + ('flags', CUmemAccess_flags), +] CUmemAccessDesc_v1 = struct_CUmemAccessDesc_st CUmemAccessDesc = struct_CUmemAccessDesc_st +enum_CUgraphExecUpdateResult_enum = CEnum(ctypes.c_uint32) +CU_GRAPH_EXEC_UPDATE_SUCCESS = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_SUCCESS', 0) +CU_GRAPH_EXEC_UPDATE_ERROR = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR', 1) +CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED', 2) +CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED', 3) +CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED', 4) +CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED', 5) +CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED', 6) +CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE', 7) +CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED = enum_CUgraphExecUpdateResult_enum.define('CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED', 8) -# values for enumeration 'CUgraphExecUpdateResult_enum' -CUgraphExecUpdateResult_enum__enumvalues = { - 0: 'CU_GRAPH_EXEC_UPDATE_SUCCESS', - 1: 'CU_GRAPH_EXEC_UPDATE_ERROR', - 2: 'CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED', - 3: 'CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED', - 4: 'CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED', - 5: 'CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED', - 6: 'CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED', - 7: 'CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE', - 8: 'CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED', -} -CU_GRAPH_EXEC_UPDATE_SUCCESS = 0 -CU_GRAPH_EXEC_UPDATE_ERROR = 1 -CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED = 2 -CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED = 3 -CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED = 4 -CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED = 5 -CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED = 6 -CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE = 7 -CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED = 8 -CUgraphExecUpdateResult_enum = ctypes.c_uint32 # enum -CUgraphExecUpdateResult = CUgraphExecUpdateResult_enum -CUgraphExecUpdateResult__enumvalues = CUgraphExecUpdateResult_enum__enumvalues -class struct_CUgraphExecUpdateResultInfo_st(Structure): - pass - -struct_CUgraphExecUpdateResultInfo_st._pack_ = 1 # source:False +CUgraphExecUpdateResult = enum_CUgraphExecUpdateResult_enum +class struct_CUgraphExecUpdateResultInfo_st(Struct): pass struct_CUgraphExecUpdateResultInfo_st._fields_ = [ - ('result', CUgraphExecUpdateResult), - ('PADDING_0', ctypes.c_ubyte * 4), - ('errorNode', ctypes.POINTER(struct_CUgraphNode_st)), - ('errorFromNode', ctypes.POINTER(struct_CUgraphNode_st)), + ('result', CUgraphExecUpdateResult), + ('errorNode', CUgraphNode), + ('errorFromNode', CUgraphNode), ] - CUgraphExecUpdateResultInfo_v1 = struct_CUgraphExecUpdateResultInfo_st CUgraphExecUpdateResultInfo = struct_CUgraphExecUpdateResultInfo_st +enum_CUmemPool_attribute_enum = CEnum(ctypes.c_uint32) +CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES', 1) +CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC', 2) +CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES', 3) +CU_MEMPOOL_ATTR_RELEASE_THRESHOLD = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_RELEASE_THRESHOLD', 4) +CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT', 5) +CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH', 6) +CU_MEMPOOL_ATTR_USED_MEM_CURRENT = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_USED_MEM_CURRENT', 7) +CU_MEMPOOL_ATTR_USED_MEM_HIGH = enum_CUmemPool_attribute_enum.define('CU_MEMPOOL_ATTR_USED_MEM_HIGH', 8) -# values for enumeration 'CUmemPool_attribute_enum' -CUmemPool_attribute_enum__enumvalues = { - 1: 'CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES', - 2: 'CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC', - 3: 'CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES', - 4: 'CU_MEMPOOL_ATTR_RELEASE_THRESHOLD', - 5: 'CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT', - 6: 'CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH', - 7: 'CU_MEMPOOL_ATTR_USED_MEM_CURRENT', - 8: 'CU_MEMPOOL_ATTR_USED_MEM_HIGH', -} -CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES = 1 -CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC = 2 -CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES = 3 -CU_MEMPOOL_ATTR_RELEASE_THRESHOLD = 4 -CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT = 5 -CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH = 6 -CU_MEMPOOL_ATTR_USED_MEM_CURRENT = 7 -CU_MEMPOOL_ATTR_USED_MEM_HIGH = 8 -CUmemPool_attribute_enum = ctypes.c_uint32 # enum -CUmemPool_attribute = CUmemPool_attribute_enum -CUmemPool_attribute__enumvalues = CUmemPool_attribute_enum__enumvalues -class struct_CUmemPoolProps_st(Structure): - pass - -struct_CUmemPoolProps_st._pack_ = 1 # source:False +CUmemPool_attribute = enum_CUmemPool_attribute_enum +class struct_CUmemPoolProps_st(Struct): pass struct_CUmemPoolProps_st._fields_ = [ - ('allocType', CUmemAllocationType), - ('handleTypes', CUmemAllocationHandleType), - ('location', CUmemLocation), - ('win32SecurityAttributes', ctypes.POINTER(None)), - ('reserved', ctypes.c_ubyte * 64), + ('allocType', CUmemAllocationType), + ('handleTypes', CUmemAllocationHandleType), + ('location', CUmemLocation), + ('win32SecurityAttributes', ctypes.c_void_p), + ('reserved', (ctypes.c_ubyte * 64)), ] - CUmemPoolProps_v1 = struct_CUmemPoolProps_st CUmemPoolProps = struct_CUmemPoolProps_st -class struct_CUmemPoolPtrExportData_st(Structure): - pass - -struct_CUmemPoolPtrExportData_st._pack_ = 1 # source:False +class struct_CUmemPoolPtrExportData_st(Struct): pass struct_CUmemPoolPtrExportData_st._fields_ = [ - ('reserved', ctypes.c_ubyte * 64), + ('reserved', (ctypes.c_ubyte * 64)), ] - CUmemPoolPtrExportData_v1 = struct_CUmemPoolPtrExportData_st CUmemPoolPtrExportData = struct_CUmemPoolPtrExportData_st -class struct_CUDA_MEM_ALLOC_NODE_PARAMS_st(Structure): - pass - -struct_CUDA_MEM_ALLOC_NODE_PARAMS_st._pack_ = 1 # source:False +class struct_CUDA_MEM_ALLOC_NODE_PARAMS_st(Struct): pass struct_CUDA_MEM_ALLOC_NODE_PARAMS_st._fields_ = [ - ('poolProps', CUmemPoolProps), - ('accessDescs', ctypes.POINTER(struct_CUmemAccessDesc_st)), - ('accessDescCount', ctypes.c_uint64), - ('bytesize', ctypes.c_uint64), - ('dptr', ctypes.c_uint64), + ('poolProps', CUmemPoolProps), + ('accessDescs', ctypes.POINTER(CUmemAccessDesc)), + ('accessDescCount', size_t), + ('bytesize', size_t), + ('dptr', CUdeviceptr), ] - CUDA_MEM_ALLOC_NODE_PARAMS = struct_CUDA_MEM_ALLOC_NODE_PARAMS_st +enum_CUgraphMem_attribute_enum = CEnum(ctypes.c_uint32) +CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT = enum_CUgraphMem_attribute_enum.define('CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT', 0) +CU_GRAPH_MEM_ATTR_USED_MEM_HIGH = enum_CUgraphMem_attribute_enum.define('CU_GRAPH_MEM_ATTR_USED_MEM_HIGH', 1) +CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT = enum_CUgraphMem_attribute_enum.define('CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT', 2) +CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH = enum_CUgraphMem_attribute_enum.define('CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH', 3) -# values for enumeration 'CUgraphMem_attribute_enum' -CUgraphMem_attribute_enum__enumvalues = { - 0: 'CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT', - 1: 'CU_GRAPH_MEM_ATTR_USED_MEM_HIGH', - 2: 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT', - 3: 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH', -} -CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT = 0 -CU_GRAPH_MEM_ATTR_USED_MEM_HIGH = 1 -CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT = 2 -CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH = 3 -CUgraphMem_attribute_enum = ctypes.c_uint32 # enum -CUgraphMem_attribute = CUgraphMem_attribute_enum -CUgraphMem_attribute__enumvalues = CUgraphMem_attribute_enum__enumvalues +CUgraphMem_attribute = enum_CUgraphMem_attribute_enum +enum_CUflushGPUDirectRDMAWritesOptions_enum = CEnum(ctypes.c_uint32) +CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST = enum_CUflushGPUDirectRDMAWritesOptions_enum.define('CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST', 1) +CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS = enum_CUflushGPUDirectRDMAWritesOptions_enum.define('CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS', 2) -# values for enumeration 'CUflushGPUDirectRDMAWritesOptions_enum' -CUflushGPUDirectRDMAWritesOptions_enum__enumvalues = { - 1: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST', - 2: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS', -} -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST = 1 -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS = 2 -CUflushGPUDirectRDMAWritesOptions_enum = ctypes.c_uint32 # enum -CUflushGPUDirectRDMAWritesOptions = CUflushGPUDirectRDMAWritesOptions_enum -CUflushGPUDirectRDMAWritesOptions__enumvalues = CUflushGPUDirectRDMAWritesOptions_enum__enumvalues +CUflushGPUDirectRDMAWritesOptions = enum_CUflushGPUDirectRDMAWritesOptions_enum +enum_CUGPUDirectRDMAWritesOrdering_enum = CEnum(ctypes.c_uint32) +CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE = enum_CUGPUDirectRDMAWritesOrdering_enum.define('CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE', 0) +CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER = enum_CUGPUDirectRDMAWritesOrdering_enum.define('CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER', 100) +CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES = enum_CUGPUDirectRDMAWritesOrdering_enum.define('CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES', 200) -# values for enumeration 'CUGPUDirectRDMAWritesOrdering_enum' -CUGPUDirectRDMAWritesOrdering_enum__enumvalues = { - 0: 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE', - 100: 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER', - 200: 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES', -} -CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE = 0 -CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER = 100 -CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES = 200 -CUGPUDirectRDMAWritesOrdering_enum = ctypes.c_uint32 # enum -CUGPUDirectRDMAWritesOrdering = CUGPUDirectRDMAWritesOrdering_enum -CUGPUDirectRDMAWritesOrdering__enumvalues = CUGPUDirectRDMAWritesOrdering_enum__enumvalues +CUGPUDirectRDMAWritesOrdering = enum_CUGPUDirectRDMAWritesOrdering_enum +enum_CUflushGPUDirectRDMAWritesScope_enum = CEnum(ctypes.c_uint32) +CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER = enum_CUflushGPUDirectRDMAWritesScope_enum.define('CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER', 100) +CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES = enum_CUflushGPUDirectRDMAWritesScope_enum.define('CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES', 200) -# values for enumeration 'CUflushGPUDirectRDMAWritesScope_enum' -CUflushGPUDirectRDMAWritesScope_enum__enumvalues = { - 100: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER', - 200: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES', -} -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER = 100 -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES = 200 -CUflushGPUDirectRDMAWritesScope_enum = ctypes.c_uint32 # enum -CUflushGPUDirectRDMAWritesScope = CUflushGPUDirectRDMAWritesScope_enum -CUflushGPUDirectRDMAWritesScope__enumvalues = CUflushGPUDirectRDMAWritesScope_enum__enumvalues +CUflushGPUDirectRDMAWritesScope = enum_CUflushGPUDirectRDMAWritesScope_enum +enum_CUflushGPUDirectRDMAWritesTarget_enum = CEnum(ctypes.c_uint32) +CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX = enum_CUflushGPUDirectRDMAWritesTarget_enum.define('CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX', 0) -# values for enumeration 'CUflushGPUDirectRDMAWritesTarget_enum' -CUflushGPUDirectRDMAWritesTarget_enum__enumvalues = { - 0: 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX', -} -CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX = 0 -CUflushGPUDirectRDMAWritesTarget_enum = ctypes.c_uint32 # enum -CUflushGPUDirectRDMAWritesTarget = CUflushGPUDirectRDMAWritesTarget_enum -CUflushGPUDirectRDMAWritesTarget__enumvalues = CUflushGPUDirectRDMAWritesTarget_enum__enumvalues +CUflushGPUDirectRDMAWritesTarget = enum_CUflushGPUDirectRDMAWritesTarget_enum +enum_CUgraphDebugDot_flags_enum = CEnum(ctypes.c_uint32) +CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE', 1) +CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES', 2) +CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS', 4) +CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS', 8) +CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS', 16) +CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS', 32) +CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS', 64) +CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS', 128) +CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS', 256) +CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES', 512) +CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES', 1024) +CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS', 2048) +CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS', 4096) +CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS', 8192) +CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO = enum_CUgraphDebugDot_flags_enum.define('CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO', 16384) -# values for enumeration 'CUgraphDebugDot_flags_enum' -CUgraphDebugDot_flags_enum__enumvalues = { - 1: 'CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE', - 2: 'CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES', - 4: 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS', - 8: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS', - 16: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS', - 32: 'CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS', - 64: 'CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS', - 128: 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS', - 256: 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS', - 512: 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES', - 1024: 'CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES', - 2048: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS', - 4096: 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS', - 8192: 'CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS', - 16384: 'CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO', -} -CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE = 1 -CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES = 2 -CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS = 4 -CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS = 8 -CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS = 16 -CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS = 32 -CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS = 64 -CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS = 128 -CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS = 256 -CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES = 512 -CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES = 1024 -CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS = 2048 -CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS = 4096 -CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS = 8192 -CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO = 16384 -CUgraphDebugDot_flags_enum = ctypes.c_uint32 # enum -CUgraphDebugDot_flags = CUgraphDebugDot_flags_enum -CUgraphDebugDot_flags__enumvalues = CUgraphDebugDot_flags_enum__enumvalues +CUgraphDebugDot_flags = enum_CUgraphDebugDot_flags_enum +enum_CUuserObject_flags_enum = CEnum(ctypes.c_uint32) +CU_USER_OBJECT_NO_DESTRUCTOR_SYNC = enum_CUuserObject_flags_enum.define('CU_USER_OBJECT_NO_DESTRUCTOR_SYNC', 1) -# values for enumeration 'CUuserObject_flags_enum' -CUuserObject_flags_enum__enumvalues = { - 1: 'CU_USER_OBJECT_NO_DESTRUCTOR_SYNC', -} -CU_USER_OBJECT_NO_DESTRUCTOR_SYNC = 1 -CUuserObject_flags_enum = ctypes.c_uint32 # enum -CUuserObject_flags = CUuserObject_flags_enum -CUuserObject_flags__enumvalues = CUuserObject_flags_enum__enumvalues +CUuserObject_flags = enum_CUuserObject_flags_enum +enum_CUuserObjectRetain_flags_enum = CEnum(ctypes.c_uint32) +CU_GRAPH_USER_OBJECT_MOVE = enum_CUuserObjectRetain_flags_enum.define('CU_GRAPH_USER_OBJECT_MOVE', 1) -# values for enumeration 'CUuserObjectRetain_flags_enum' -CUuserObjectRetain_flags_enum__enumvalues = { - 1: 'CU_GRAPH_USER_OBJECT_MOVE', -} -CU_GRAPH_USER_OBJECT_MOVE = 1 -CUuserObjectRetain_flags_enum = ctypes.c_uint32 # enum -CUuserObjectRetain_flags = CUuserObjectRetain_flags_enum -CUuserObjectRetain_flags__enumvalues = CUuserObjectRetain_flags_enum__enumvalues +CUuserObjectRetain_flags = enum_CUuserObjectRetain_flags_enum +enum_CUgraphInstantiate_flags_enum = CEnum(ctypes.c_uint32) +CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH = enum_CUgraphInstantiate_flags_enum.define('CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH', 1) +CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD = enum_CUgraphInstantiate_flags_enum.define('CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD', 2) +CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH = enum_CUgraphInstantiate_flags_enum.define('CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH', 4) +CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY = enum_CUgraphInstantiate_flags_enum.define('CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY', 8) -# values for enumeration 'CUgraphInstantiate_flags_enum' -CUgraphInstantiate_flags_enum__enumvalues = { - 1: 'CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH', - 2: 'CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD', - 4: 'CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH', - 8: 'CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY', -} -CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH = 1 -CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD = 2 -CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH = 4 -CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY = 8 -CUgraphInstantiate_flags_enum = ctypes.c_uint32 # enum -CUgraphInstantiate_flags = CUgraphInstantiate_flags_enum -CUgraphInstantiate_flags__enumvalues = CUgraphInstantiate_flags_enum__enumvalues -try: - cuGetErrorString = _libraries['libcuda.so'].cuGetErrorString - cuGetErrorString.restype = CUresult - cuGetErrorString.argtypes = [CUresult, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - cuGetErrorName = _libraries['libcuda.so'].cuGetErrorName - cuGetErrorName.restype = CUresult - cuGetErrorName.argtypes = [CUresult, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - cuInit = _libraries['libcuda.so'].cuInit - cuInit.restype = CUresult - cuInit.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - cuDriverGetVersion = _libraries['libcuda.so'].cuDriverGetVersion - cuDriverGetVersion.restype = CUresult - cuDriverGetVersion.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuDeviceGet = _libraries['libcuda.so'].cuDeviceGet - cuDeviceGet.restype = CUresult - cuDeviceGet.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32] -except AttributeError: - pass -try: - cuDeviceGetCount = _libraries['libcuda.so'].cuDeviceGetCount - cuDeviceGetCount.restype = CUresult - cuDeviceGetCount.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuDeviceGetName = _libraries['libcuda.so'].cuDeviceGetName - cuDeviceGetName.restype = CUresult - cuDeviceGetName.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, CUdevice] -except AttributeError: - pass -try: - cuDeviceGetUuid = _libraries['libcuda.so'].cuDeviceGetUuid - cuDeviceGetUuid.restype = CUresult - cuDeviceGetUuid.argtypes = [ctypes.POINTER(struct_CUuuid_st), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetUuid_v2 = _libraries['libcuda.so'].cuDeviceGetUuid_v2 - cuDeviceGetUuid_v2.restype = CUresult - cuDeviceGetUuid_v2.argtypes = [ctypes.POINTER(struct_CUuuid_st), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetLuid = _libraries['libcuda.so'].cuDeviceGetLuid - cuDeviceGetLuid.restype = CUresult - cuDeviceGetLuid.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32), CUdevice] -except AttributeError: - pass -try: - cuDeviceTotalMem_v2 = _libraries['libcuda.so'].cuDeviceTotalMem_v2 - cuDeviceTotalMem_v2.restype = CUresult - cuDeviceTotalMem_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetTexture1DLinearMaxWidth = _libraries['libcuda.so'].cuDeviceGetTexture1DLinearMaxWidth - cuDeviceGetTexture1DLinearMaxWidth.restype = CUresult - cuDeviceGetTexture1DLinearMaxWidth.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUarray_format, ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuDeviceGetAttribute = _libraries['libcuda.so'].cuDeviceGetAttribute - cuDeviceGetAttribute.restype = CUresult - cuDeviceGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUdevice_attribute, CUdevice] -except AttributeError: - pass -try: - cuDeviceGetNvSciSyncAttributes = _libraries['libcuda.so'].cuDeviceGetNvSciSyncAttributes - cuDeviceGetNvSciSyncAttributes.restype = CUresult - cuDeviceGetNvSciSyncAttributes.argtypes = [ctypes.POINTER(None), CUdevice, ctypes.c_int32] -except AttributeError: - pass -try: - cuDeviceSetMemPool = _libraries['libcuda.so'].cuDeviceSetMemPool - cuDeviceSetMemPool.restype = CUresult - cuDeviceSetMemPool.argtypes = [CUdevice, CUmemoryPool] -except AttributeError: - pass -try: - cuDeviceGetMemPool = _libraries['libcuda.so'].cuDeviceGetMemPool - cuDeviceGetMemPool.restype = CUresult - cuDeviceGetMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetDefaultMemPool = _libraries['libcuda.so'].cuDeviceGetDefaultMemPool - cuDeviceGetDefaultMemPool.restype = CUresult - cuDeviceGetDefaultMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), CUdevice] -except AttributeError: - pass -try: - cuDeviceGetExecAffinitySupport = _libraries['libcuda.so'].cuDeviceGetExecAffinitySupport - cuDeviceGetExecAffinitySupport.restype = CUresult - cuDeviceGetExecAffinitySupport.argtypes = [ctypes.POINTER(ctypes.c_int32), CUexecAffinityType, CUdevice] -except AttributeError: - pass -try: - cuFlushGPUDirectRDMAWrites = _libraries['libcuda.so'].cuFlushGPUDirectRDMAWrites - cuFlushGPUDirectRDMAWrites.restype = CUresult - cuFlushGPUDirectRDMAWrites.argtypes = [CUflushGPUDirectRDMAWritesTarget, CUflushGPUDirectRDMAWritesScope] -except AttributeError: - pass -try: - cuDeviceGetProperties = _libraries['libcuda.so'].cuDeviceGetProperties - cuDeviceGetProperties.restype = CUresult - cuDeviceGetProperties.argtypes = [ctypes.POINTER(struct_CUdevprop_st), CUdevice] -except AttributeError: - pass -try: - cuDeviceComputeCapability = _libraries['libcuda.so'].cuDeviceComputeCapability - cuDeviceComputeCapability.restype = CUresult - cuDeviceComputeCapability.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxRetain = _libraries['libcuda.so'].cuDevicePrimaryCtxRetain - cuDevicePrimaryCtxRetain.restype = CUresult - cuDevicePrimaryCtxRetain.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxRelease_v2 = _libraries['libcuda.so'].cuDevicePrimaryCtxRelease_v2 - cuDevicePrimaryCtxRelease_v2.restype = CUresult - cuDevicePrimaryCtxRelease_v2.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxSetFlags_v2 = _libraries['libcuda.so'].cuDevicePrimaryCtxSetFlags_v2 - cuDevicePrimaryCtxSetFlags_v2.restype = CUresult - cuDevicePrimaryCtxSetFlags_v2.argtypes = [CUdevice, ctypes.c_uint32] -except AttributeError: - pass -try: - cuDevicePrimaryCtxGetState = _libraries['libcuda.so'].cuDevicePrimaryCtxGetState - cuDevicePrimaryCtxGetState.restype = CUresult - cuDevicePrimaryCtxGetState.argtypes = [CUdevice, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuDevicePrimaryCtxReset_v2 = _libraries['libcuda.so'].cuDevicePrimaryCtxReset_v2 - cuDevicePrimaryCtxReset_v2.restype = CUresult - cuDevicePrimaryCtxReset_v2.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuCtxCreate_v2 = _libraries['libcuda.so'].cuCtxCreate_v2 - cuCtxCreate_v2.restype = CUresult - cuCtxCreate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuCtxCreate_v3 = _libraries['libcuda.so'].cuCtxCreate_v3 - cuCtxCreate_v3.restype = CUresult - cuCtxCreate_v3.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.POINTER(struct_CUexecAffinityParam_st), ctypes.c_int32, ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuCtxDestroy_v2 = _libraries['libcuda.so'].cuCtxDestroy_v2 - cuCtxDestroy_v2.restype = CUresult - cuCtxDestroy_v2.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxPushCurrent_v2 = _libraries['libcuda.so'].cuCtxPushCurrent_v2 - cuCtxPushCurrent_v2.restype = CUresult - cuCtxPushCurrent_v2.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxPopCurrent_v2 = _libraries['libcuda.so'].cuCtxPopCurrent_v2 - cuCtxPopCurrent_v2.restype = CUresult - cuCtxPopCurrent_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuCtxSetCurrent = _libraries['libcuda.so'].cuCtxSetCurrent - cuCtxSetCurrent.restype = CUresult - cuCtxSetCurrent.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxGetCurrent = _libraries['libcuda.so'].cuCtxGetCurrent - cuCtxGetCurrent.restype = CUresult - cuCtxGetCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuCtxGetDevice = _libraries['libcuda.so'].cuCtxGetDevice - cuCtxGetDevice.restype = CUresult - cuCtxGetDevice.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuCtxGetFlags = _libraries['libcuda.so'].cuCtxGetFlags - cuCtxGetFlags.restype = CUresult - cuCtxGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuCtxGetId = _libraries['libcuda.so'].cuCtxGetId - cuCtxGetId.restype = CUresult - cuCtxGetId.argtypes = [CUcontext, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuCtxSynchronize = _libraries['libcuda.so'].cuCtxSynchronize - cuCtxSynchronize.restype = CUresult - cuCtxSynchronize.argtypes = [] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - cuCtxSetLimit = _libraries['libcuda.so'].cuCtxSetLimit - cuCtxSetLimit.restype = CUresult - cuCtxSetLimit.argtypes = [CUlimit, size_t] -except AttributeError: - pass -try: - cuCtxGetLimit = _libraries['libcuda.so'].cuCtxGetLimit - cuCtxGetLimit.restype = CUresult - cuCtxGetLimit.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUlimit] -except AttributeError: - pass -try: - cuCtxGetCacheConfig = _libraries['libcuda.so'].cuCtxGetCacheConfig - cuCtxGetCacheConfig.restype = CUresult - cuCtxGetCacheConfig.argtypes = [ctypes.POINTER(CUfunc_cache_enum)] -except AttributeError: - pass -try: - cuCtxSetCacheConfig = _libraries['libcuda.so'].cuCtxSetCacheConfig - cuCtxSetCacheConfig.restype = CUresult - cuCtxSetCacheConfig.argtypes = [CUfunc_cache] -except AttributeError: - pass -try: - cuCtxGetSharedMemConfig = _libraries['libcuda.so'].cuCtxGetSharedMemConfig - cuCtxGetSharedMemConfig.restype = CUresult - cuCtxGetSharedMemConfig.argtypes = [ctypes.POINTER(CUsharedconfig_enum)] -except AttributeError: - pass -try: - cuCtxSetSharedMemConfig = _libraries['libcuda.so'].cuCtxSetSharedMemConfig - cuCtxSetSharedMemConfig.restype = CUresult - cuCtxSetSharedMemConfig.argtypes = [CUsharedconfig] -except AttributeError: - pass -try: - cuCtxGetApiVersion = _libraries['libcuda.so'].cuCtxGetApiVersion - cuCtxGetApiVersion.restype = CUresult - cuCtxGetApiVersion.argtypes = [CUcontext, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuCtxGetStreamPriorityRange = _libraries['libcuda.so'].cuCtxGetStreamPriorityRange - cuCtxGetStreamPriorityRange.restype = CUresult - cuCtxGetStreamPriorityRange.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuCtxResetPersistingL2Cache = _libraries['libcuda.so'].cuCtxResetPersistingL2Cache - cuCtxResetPersistingL2Cache.restype = CUresult - cuCtxResetPersistingL2Cache.argtypes = [] -except AttributeError: - pass -try: - cuCtxGetExecAffinity = _libraries['libcuda.so'].cuCtxGetExecAffinity - cuCtxGetExecAffinity.restype = CUresult - cuCtxGetExecAffinity.argtypes = [ctypes.POINTER(struct_CUexecAffinityParam_st), CUexecAffinityType] -except AttributeError: - pass -try: - cuCtxAttach = _libraries['libcuda.so'].cuCtxAttach - cuCtxAttach.restype = CUresult - cuCtxAttach.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuCtxDetach = _libraries['libcuda.so'].cuCtxDetach - cuCtxDetach.restype = CUresult - cuCtxDetach.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuModuleLoad = _libraries['libcuda.so'].cuModuleLoad - cuModuleLoad.restype = CUresult - cuModuleLoad.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuModuleLoadData = _libraries['libcuda.so'].cuModuleLoadData - cuModuleLoadData.restype = CUresult - cuModuleLoadData.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuModuleLoadDataEx = _libraries['libcuda.so'].cuModuleLoadDataEx - cuModuleLoadDataEx.restype = CUresult - cuModuleLoadDataEx.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(None), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuModuleLoadFatBinary = _libraries['libcuda.so'].cuModuleLoadFatBinary - cuModuleLoadFatBinary.restype = CUresult - cuModuleLoadFatBinary.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuModuleUnload = _libraries['libcuda.so'].cuModuleUnload - cuModuleUnload.restype = CUresult - cuModuleUnload.argtypes = [CUmodule] -except AttributeError: - pass +CUgraphInstantiate_flags = enum_CUgraphInstantiate_flags_enum +# CUresult cuGetErrorString(CUresult error, const char **pStr) +try: (cuGetErrorString:=dll.cuGetErrorString).restype, cuGetErrorString.argtypes = CUresult, [CUresult, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# CUresult cuGetErrorName(CUresult error, const char **pStr) +try: (cuGetErrorName:=dll.cuGetErrorName).restype, cuGetErrorName.argtypes = CUresult, [CUresult, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# CUresult cuInit(unsigned int Flags) +try: (cuInit:=dll.cuInit).restype, cuInit.argtypes = CUresult, [ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuDriverGetVersion(int *driverVersion) +try: (cuDriverGetVersion:=dll.cuDriverGetVersion).restype, cuDriverGetVersion.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# CUresult cuDeviceGet(CUdevice *device, int ordinal) +try: (cuDeviceGet:=dll.cuDeviceGet).restype, cuDeviceGet.argtypes = CUresult, [ctypes.POINTER(CUdevice), ctypes.c_int32] +except AttributeError: pass + +# CUresult cuDeviceGetCount(int *count) +try: (cuDeviceGetCount:=dll.cuDeviceGetCount).restype, cuDeviceGetCount.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# CUresult cuDeviceGetName(char *name, int len, CUdevice dev) +try: (cuDeviceGetName:=dll.cuDeviceGetName).restype, cuDeviceGetName.argtypes = CUresult, [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetUuid(CUuuid *uuid, CUdevice dev) +try: (cuDeviceGetUuid:=dll.cuDeviceGetUuid).restype, cuDeviceGetUuid.argtypes = CUresult, [ctypes.POINTER(CUuuid), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetUuid_v2(CUuuid *uuid, CUdevice dev) +try: (cuDeviceGetUuid_v2:=dll.cuDeviceGetUuid_v2).restype, cuDeviceGetUuid_v2.argtypes = CUresult, [ctypes.POINTER(CUuuid), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetLuid(char *luid, unsigned int *deviceNodeMask, CUdevice dev) +try: (cuDeviceGetLuid:=dll.cuDeviceGetLuid).restype, cuDeviceGetLuid.argtypes = CUresult, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceTotalMem_v2(size_t *bytes, CUdevice dev) +try: (cuDeviceTotalMem_v2:=dll.cuDeviceTotalMem_v2).restype, cuDeviceTotalMem_v2.argtypes = CUresult, [ctypes.POINTER(size_t), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetTexture1DLinearMaxWidth(size_t *maxWidthInElements, CUarray_format format, unsigned int numChannels, CUdevice dev) +try: (cuDeviceGetTexture1DLinearMaxWidth:=dll.cuDeviceGetTexture1DLinearMaxWidth).restype, cuDeviceGetTexture1DLinearMaxWidth.argtypes = CUresult, [ctypes.POINTER(size_t), CUarray_format, ctypes.c_uint32, CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetAttribute(int *pi, CUdevice_attribute attrib, CUdevice dev) +try: (cuDeviceGetAttribute:=dll.cuDeviceGetAttribute).restype, cuDeviceGetAttribute.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUdevice_attribute, CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetNvSciSyncAttributes(void *nvSciSyncAttrList, CUdevice dev, int flags) +try: (cuDeviceGetNvSciSyncAttributes:=dll.cuDeviceGetNvSciSyncAttributes).restype, cuDeviceGetNvSciSyncAttributes.argtypes = CUresult, [ctypes.c_void_p, CUdevice, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuDeviceSetMemPool(CUdevice dev, CUmemoryPool pool) +try: (cuDeviceSetMemPool:=dll.cuDeviceSetMemPool).restype, cuDeviceSetMemPool.argtypes = CUresult, [CUdevice, CUmemoryPool] +except AttributeError: pass + +# CUresult cuDeviceGetMemPool(CUmemoryPool *pool, CUdevice dev) +try: (cuDeviceGetMemPool:=dll.cuDeviceGetMemPool).restype, cuDeviceGetMemPool.argtypes = CUresult, [ctypes.POINTER(CUmemoryPool), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetDefaultMemPool(CUmemoryPool *pool_out, CUdevice dev) +try: (cuDeviceGetDefaultMemPool:=dll.cuDeviceGetDefaultMemPool).restype, cuDeviceGetDefaultMemPool.argtypes = CUresult, [ctypes.POINTER(CUmemoryPool), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetExecAffinitySupport(int *pi, CUexecAffinityType type, CUdevice dev) +try: (cuDeviceGetExecAffinitySupport:=dll.cuDeviceGetExecAffinitySupport).restype, cuDeviceGetExecAffinitySupport.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUexecAffinityType, CUdevice] +except AttributeError: pass + +# CUresult cuFlushGPUDirectRDMAWrites(CUflushGPUDirectRDMAWritesTarget target, CUflushGPUDirectRDMAWritesScope scope) +try: (cuFlushGPUDirectRDMAWrites:=dll.cuFlushGPUDirectRDMAWrites).restype, cuFlushGPUDirectRDMAWrites.argtypes = CUresult, [CUflushGPUDirectRDMAWritesTarget, CUflushGPUDirectRDMAWritesScope] +except AttributeError: pass + +# CUresult cuDeviceGetProperties(CUdevprop *prop, CUdevice dev) +try: (cuDeviceGetProperties:=dll.cuDeviceGetProperties).restype, cuDeviceGetProperties.argtypes = CUresult, [ctypes.POINTER(CUdevprop), CUdevice] +except AttributeError: pass + +# CUresult cuDeviceComputeCapability(int *major, int *minor, CUdevice dev) +try: (cuDeviceComputeCapability:=dll.cuDeviceComputeCapability).restype, cuDeviceComputeCapability.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUdevice] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxRetain(CUcontext *pctx, CUdevice dev) +try: (cuDevicePrimaryCtxRetain:=dll.cuDevicePrimaryCtxRetain).restype, cuDevicePrimaryCtxRetain.argtypes = CUresult, [ctypes.POINTER(CUcontext), CUdevice] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxRelease_v2(CUdevice dev) +try: (cuDevicePrimaryCtxRelease_v2:=dll.cuDevicePrimaryCtxRelease_v2).restype, cuDevicePrimaryCtxRelease_v2.argtypes = CUresult, [CUdevice] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxSetFlags_v2(CUdevice dev, unsigned int flags) +try: (cuDevicePrimaryCtxSetFlags_v2:=dll.cuDevicePrimaryCtxSetFlags_v2).restype, cuDevicePrimaryCtxSetFlags_v2.argtypes = CUresult, [CUdevice, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxGetState(CUdevice dev, unsigned int *flags, int *active) +try: (cuDevicePrimaryCtxGetState:=dll.cuDevicePrimaryCtxGetState).restype, cuDevicePrimaryCtxGetState.argtypes = CUresult, [CUdevice, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxReset_v2(CUdevice dev) +try: (cuDevicePrimaryCtxReset_v2:=dll.cuDevicePrimaryCtxReset_v2).restype, cuDevicePrimaryCtxReset_v2.argtypes = CUresult, [CUdevice] +except AttributeError: pass + +# CUresult cuCtxCreate_v2(CUcontext *pctx, unsigned int flags, CUdevice dev) +try: (cuCtxCreate_v2:=dll.cuCtxCreate_v2).restype, cuCtxCreate_v2.argtypes = CUresult, [ctypes.POINTER(CUcontext), ctypes.c_uint32, CUdevice] +except AttributeError: pass + +# CUresult cuCtxCreate_v3(CUcontext *pctx, CUexecAffinityParam *paramsArray, int numParams, unsigned int flags, CUdevice dev) +try: (cuCtxCreate_v3:=dll.cuCtxCreate_v3).restype, cuCtxCreate_v3.argtypes = CUresult, [ctypes.POINTER(CUcontext), ctypes.POINTER(CUexecAffinityParam), ctypes.c_int32, ctypes.c_uint32, CUdevice] +except AttributeError: pass + +# CUresult cuCtxDestroy_v2(CUcontext ctx) +try: (cuCtxDestroy_v2:=dll.cuCtxDestroy_v2).restype, cuCtxDestroy_v2.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuCtxPushCurrent_v2(CUcontext ctx) +try: (cuCtxPushCurrent_v2:=dll.cuCtxPushCurrent_v2).restype, cuCtxPushCurrent_v2.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuCtxPopCurrent_v2(CUcontext *pctx) +try: (cuCtxPopCurrent_v2:=dll.cuCtxPopCurrent_v2).restype, cuCtxPopCurrent_v2.argtypes = CUresult, [ctypes.POINTER(CUcontext)] +except AttributeError: pass + +# CUresult cuCtxSetCurrent(CUcontext ctx) +try: (cuCtxSetCurrent:=dll.cuCtxSetCurrent).restype, cuCtxSetCurrent.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuCtxGetCurrent(CUcontext *pctx) +try: (cuCtxGetCurrent:=dll.cuCtxGetCurrent).restype, cuCtxGetCurrent.argtypes = CUresult, [ctypes.POINTER(CUcontext)] +except AttributeError: pass + +# CUresult cuCtxGetDevice(CUdevice *device) +try: (cuCtxGetDevice:=dll.cuCtxGetDevice).restype, cuCtxGetDevice.argtypes = CUresult, [ctypes.POINTER(CUdevice)] +except AttributeError: pass + +# CUresult cuCtxGetFlags(unsigned int *flags) +try: (cuCtxGetFlags:=dll.cuCtxGetFlags).restype, cuCtxGetFlags.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# CUresult cuCtxGetId(CUcontext ctx, unsigned long long *ctxId) +try: (cuCtxGetId:=dll.cuCtxGetId).restype, cuCtxGetId.argtypes = CUresult, [CUcontext, ctypes.POINTER(ctypes.c_uint64)] +except AttributeError: pass + +# CUresult cuCtxSynchronize(void) +try: (cuCtxSynchronize:=dll.cuCtxSynchronize).restype, cuCtxSynchronize.argtypes = CUresult, [] +except AttributeError: pass + +# CUresult cuCtxSetLimit(CUlimit limit, size_t value) +try: (cuCtxSetLimit:=dll.cuCtxSetLimit).restype, cuCtxSetLimit.argtypes = CUresult, [CUlimit, size_t] +except AttributeError: pass + +# CUresult cuCtxGetLimit(size_t *pvalue, CUlimit limit) +try: (cuCtxGetLimit:=dll.cuCtxGetLimit).restype, cuCtxGetLimit.argtypes = CUresult, [ctypes.POINTER(size_t), CUlimit] +except AttributeError: pass + +# CUresult cuCtxGetCacheConfig(CUfunc_cache *pconfig) +try: (cuCtxGetCacheConfig:=dll.cuCtxGetCacheConfig).restype, cuCtxGetCacheConfig.argtypes = CUresult, [ctypes.POINTER(CUfunc_cache)] +except AttributeError: pass + +# CUresult cuCtxSetCacheConfig(CUfunc_cache config) +try: (cuCtxSetCacheConfig:=dll.cuCtxSetCacheConfig).restype, cuCtxSetCacheConfig.argtypes = CUresult, [CUfunc_cache] +except AttributeError: pass + +# CUresult cuCtxGetSharedMemConfig(CUsharedconfig *pConfig) +try: (cuCtxGetSharedMemConfig:=dll.cuCtxGetSharedMemConfig).restype, cuCtxGetSharedMemConfig.argtypes = CUresult, [ctypes.POINTER(CUsharedconfig)] +except AttributeError: pass + +# CUresult cuCtxSetSharedMemConfig(CUsharedconfig config) +try: (cuCtxSetSharedMemConfig:=dll.cuCtxSetSharedMemConfig).restype, cuCtxSetSharedMemConfig.argtypes = CUresult, [CUsharedconfig] +except AttributeError: pass + +# CUresult cuCtxGetApiVersion(CUcontext ctx, unsigned int *version) +try: (cuCtxGetApiVersion:=dll.cuCtxGetApiVersion).restype, cuCtxGetApiVersion.argtypes = CUresult, [CUcontext, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# CUresult cuCtxGetStreamPriorityRange(int *leastPriority, int *greatestPriority) +try: (cuCtxGetStreamPriorityRange:=dll.cuCtxGetStreamPriorityRange).restype, cuCtxGetStreamPriorityRange.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# CUresult cuCtxResetPersistingL2Cache(void) +try: (cuCtxResetPersistingL2Cache:=dll.cuCtxResetPersistingL2Cache).restype, cuCtxResetPersistingL2Cache.argtypes = CUresult, [] +except AttributeError: pass + +# CUresult cuCtxGetExecAffinity(CUexecAffinityParam *pExecAffinity, CUexecAffinityType type) +try: (cuCtxGetExecAffinity:=dll.cuCtxGetExecAffinity).restype, cuCtxGetExecAffinity.argtypes = CUresult, [ctypes.POINTER(CUexecAffinityParam), CUexecAffinityType] +except AttributeError: pass + +# CUresult cuCtxAttach(CUcontext *pctx, unsigned int flags) +try: (cuCtxAttach:=dll.cuCtxAttach).restype, cuCtxAttach.argtypes = CUresult, [ctypes.POINTER(CUcontext), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuCtxDetach(CUcontext ctx) +try: (cuCtxDetach:=dll.cuCtxDetach).restype, cuCtxDetach.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuModuleLoad(CUmodule *module, const char *fname) +try: (cuModuleLoad:=dll.cuModuleLoad).restype, cuModuleLoad.argtypes = CUresult, [ctypes.POINTER(CUmodule), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuModuleLoadData(CUmodule *module, const void *image) +try: (cuModuleLoadData:=dll.cuModuleLoadData).restype, cuModuleLoadData.argtypes = CUresult, [ctypes.POINTER(CUmodule), ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuModuleLoadDataEx(CUmodule *module, const void *image, unsigned int numOptions, CUjit_option *options, void **optionValues) +try: (cuModuleLoadDataEx:=dll.cuModuleLoadDataEx).restype, cuModuleLoadDataEx.argtypes = CUresult, [ctypes.POINTER(CUmodule), ctypes.c_void_p, ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuModuleLoadFatBinary(CUmodule *module, const void *fatCubin) +try: (cuModuleLoadFatBinary:=dll.cuModuleLoadFatBinary).restype, cuModuleLoadFatBinary.argtypes = CUresult, [ctypes.POINTER(CUmodule), ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuModuleUnload(CUmodule hmod) +try: (cuModuleUnload:=dll.cuModuleUnload).restype, cuModuleUnload.argtypes = CUresult, [CUmodule] +except AttributeError: pass + +enum_CUmoduleLoadingMode_enum = CEnum(ctypes.c_uint32) +CU_MODULE_EAGER_LOADING = enum_CUmoduleLoadingMode_enum.define('CU_MODULE_EAGER_LOADING', 1) +CU_MODULE_LAZY_LOADING = enum_CUmoduleLoadingMode_enum.define('CU_MODULE_LAZY_LOADING', 2) + +CUmoduleLoadingMode = enum_CUmoduleLoadingMode_enum +# CUresult cuModuleGetLoadingMode(CUmoduleLoadingMode *mode) +try: (cuModuleGetLoadingMode:=dll.cuModuleGetLoadingMode).restype, cuModuleGetLoadingMode.argtypes = CUresult, [ctypes.POINTER(CUmoduleLoadingMode)] +except AttributeError: pass + +# CUresult cuModuleGetFunction(CUfunction *hfunc, CUmodule hmod, const char *name) +try: (cuModuleGetFunction:=dll.cuModuleGetFunction).restype, cuModuleGetFunction.argtypes = CUresult, [ctypes.POINTER(CUfunction), CUmodule, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuModuleGetGlobal_v2(CUdeviceptr *dptr, size_t *bytes, CUmodule hmod, const char *name) +try: (cuModuleGetGlobal_v2:=dll.cuModuleGetGlobal_v2).restype, cuModuleGetGlobal_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.POINTER(size_t), CUmodule, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuLinkCreate_v2(unsigned int numOptions, CUjit_option *options, void **optionValues, CUlinkState *stateOut) +try: (cuLinkCreate_v2:=dll.cuLinkCreate_v2).restype, cuLinkCreate_v2.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(CUlinkState)] +except AttributeError: pass + +# CUresult cuLinkAddData_v2(CUlinkState state, CUjitInputType type, void *data, size_t size, const char *name, unsigned int numOptions, CUjit_option *options, void **optionValues) +try: (cuLinkAddData_v2:=dll.cuLinkAddData_v2).restype, cuLinkAddData_v2.argtypes = CUresult, [CUlinkState, CUjitInputType, ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLinkAddFile_v2(CUlinkState state, CUjitInputType type, const char *path, unsigned int numOptions, CUjit_option *options, void **optionValues) +try: (cuLinkAddFile_v2:=dll.cuLinkAddFile_v2).restype, cuLinkAddFile_v2.argtypes = CUresult, [CUlinkState, CUjitInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLinkComplete(CUlinkState state, void **cubinOut, size_t *sizeOut) +try: (cuLinkComplete:=dll.cuLinkComplete).restype, cuLinkComplete.argtypes = CUresult, [CUlinkState, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuLinkDestroy(CUlinkState state) +try: (cuLinkDestroy:=dll.cuLinkDestroy).restype, cuLinkDestroy.argtypes = CUresult, [CUlinkState] +except AttributeError: pass + +# CUresult cuModuleGetTexRef(CUtexref *pTexRef, CUmodule hmod, const char *name) +try: (cuModuleGetTexRef:=dll.cuModuleGetTexRef).restype, cuModuleGetTexRef.argtypes = CUresult, [ctypes.POINTER(CUtexref), CUmodule, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuModuleGetSurfRef(CUsurfref *pSurfRef, CUmodule hmod, const char *name) +try: (cuModuleGetSurfRef:=dll.cuModuleGetSurfRef).restype, cuModuleGetSurfRef.argtypes = CUresult, [ctypes.POINTER(CUsurfref), CUmodule, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuLibraryLoadData(CUlibrary *library, const void *code, CUjit_option *jitOptions, void **jitOptionsValues, unsigned int numJitOptions, CUlibraryOption *libraryOptions, void **libraryOptionValues, unsigned int numLibraryOptions) +try: (cuLibraryLoadData:=dll.cuLibraryLoadData).restype, cuLibraryLoadData.argtypes = CUresult, [ctypes.POINTER(CUlibrary), ctypes.c_void_p, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p), ctypes.c_uint32, ctypes.POINTER(CUlibraryOption), ctypes.POINTER(ctypes.c_void_p), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuLibraryLoadFromFile(CUlibrary *library, const char *fileName, CUjit_option *jitOptions, void **jitOptionsValues, unsigned int numJitOptions, CUlibraryOption *libraryOptions, void **libraryOptionValues, unsigned int numLibraryOptions) +try: (cuLibraryLoadFromFile:=dll.cuLibraryLoadFromFile).restype, cuLibraryLoadFromFile.argtypes = CUresult, [ctypes.POINTER(CUlibrary), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p), ctypes.c_uint32, ctypes.POINTER(CUlibraryOption), ctypes.POINTER(ctypes.c_void_p), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuLibraryUnload(CUlibrary library) +try: (cuLibraryUnload:=dll.cuLibraryUnload).restype, cuLibraryUnload.argtypes = CUresult, [CUlibrary] +except AttributeError: pass + +# CUresult cuLibraryGetKernel(CUkernel *pKernel, CUlibrary library, const char *name) +try: (cuLibraryGetKernel:=dll.cuLibraryGetKernel).restype, cuLibraryGetKernel.argtypes = CUresult, [ctypes.POINTER(CUkernel), CUlibrary, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuLibraryGetModule(CUmodule *pMod, CUlibrary library) +try: (cuLibraryGetModule:=dll.cuLibraryGetModule).restype, cuLibraryGetModule.argtypes = CUresult, [ctypes.POINTER(CUmodule), CUlibrary] +except AttributeError: pass + +# CUresult cuKernelGetFunction(CUfunction *pFunc, CUkernel kernel) +try: (cuKernelGetFunction:=dll.cuKernelGetFunction).restype, cuKernelGetFunction.argtypes = CUresult, [ctypes.POINTER(CUfunction), CUkernel] +except AttributeError: pass + +# CUresult cuLibraryGetGlobal(CUdeviceptr *dptr, size_t *bytes, CUlibrary library, const char *name) +try: (cuLibraryGetGlobal:=dll.cuLibraryGetGlobal).restype, cuLibraryGetGlobal.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.POINTER(size_t), CUlibrary, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuLibraryGetManaged(CUdeviceptr *dptr, size_t *bytes, CUlibrary library, const char *name) +try: (cuLibraryGetManaged:=dll.cuLibraryGetManaged).restype, cuLibraryGetManaged.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.POINTER(size_t), CUlibrary, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuLibraryGetUnifiedFunction(void **fptr, CUlibrary library, const char *symbol) +try: (cuLibraryGetUnifiedFunction:=dll.cuLibraryGetUnifiedFunction).restype, cuLibraryGetUnifiedFunction.argtypes = CUresult, [ctypes.POINTER(ctypes.c_void_p), CUlibrary, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuKernelGetAttribute(int *pi, CUfunction_attribute attrib, CUkernel kernel, CUdevice dev) +try: (cuKernelGetAttribute:=dll.cuKernelGetAttribute).restype, cuKernelGetAttribute.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUfunction_attribute, CUkernel, CUdevice] +except AttributeError: pass + +# CUresult cuKernelSetAttribute(CUfunction_attribute attrib, int val, CUkernel kernel, CUdevice dev) +try: (cuKernelSetAttribute:=dll.cuKernelSetAttribute).restype, cuKernelSetAttribute.argtypes = CUresult, [CUfunction_attribute, ctypes.c_int32, CUkernel, CUdevice] +except AttributeError: pass + +# CUresult cuKernelSetCacheConfig(CUkernel kernel, CUfunc_cache config, CUdevice dev) +try: (cuKernelSetCacheConfig:=dll.cuKernelSetCacheConfig).restype, cuKernelSetCacheConfig.argtypes = CUresult, [CUkernel, CUfunc_cache, CUdevice] +except AttributeError: pass + +# CUresult cuMemGetInfo_v2(size_t *free, size_t *total) +try: (cuMemGetInfo_v2:=dll.cuMemGetInfo_v2).restype, cuMemGetInfo_v2.argtypes = CUresult, [ctypes.POINTER(size_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuMemAlloc_v2(CUdeviceptr *dptr, size_t bytesize) +try: (cuMemAlloc_v2:=dll.cuMemAlloc_v2).restype, cuMemAlloc_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t] +except AttributeError: pass + +# CUresult cuMemAllocPitch_v2(CUdeviceptr *dptr, size_t *pPitch, size_t WidthInBytes, size_t Height, unsigned int ElementSizeBytes) +try: (cuMemAllocPitch_v2:=dll.cuMemAllocPitch_v2).restype, cuMemAllocPitch_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.POINTER(size_t), size_t, size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemFree_v2(CUdeviceptr dptr) +try: (cuMemFree_v2:=dll.cuMemFree_v2).restype, cuMemFree_v2.argtypes = CUresult, [CUdeviceptr] +except AttributeError: pass + +# CUresult cuMemGetAddressRange_v2(CUdeviceptr *pbase, size_t *psize, CUdeviceptr dptr) +try: (cuMemGetAddressRange_v2:=dll.cuMemGetAddressRange_v2).restype, cuMemGetAddressRange_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.POINTER(size_t), CUdeviceptr] +except AttributeError: pass + +# CUresult cuMemAllocHost_v2(void **pp, size_t bytesize) +try: (cuMemAllocHost_v2:=dll.cuMemAllocHost_v2).restype, cuMemAllocHost_v2.argtypes = CUresult, [ctypes.POINTER(ctypes.c_void_p), size_t] +except AttributeError: pass + +# CUresult cuMemFreeHost(void *p) +try: (cuMemFreeHost:=dll.cuMemFreeHost).restype, cuMemFreeHost.argtypes = CUresult, [ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuMemHostAlloc(void **pp, size_t bytesize, unsigned int Flags) +try: (cuMemHostAlloc:=dll.cuMemHostAlloc).restype, cuMemHostAlloc.argtypes = CUresult, [ctypes.POINTER(ctypes.c_void_p), size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemHostGetDevicePointer_v2(CUdeviceptr *pdptr, void *p, unsigned int Flags) +try: (cuMemHostGetDevicePointer_v2:=dll.cuMemHostGetDevicePointer_v2).restype, cuMemHostGetDevicePointer_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemHostGetFlags(unsigned int *pFlags, void *p) +try: (cuMemHostGetFlags:=dll.cuMemHostGetFlags).restype, cuMemHostGetFlags.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint32), ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuMemAllocManaged(CUdeviceptr *dptr, size_t bytesize, unsigned int flags) +try: (cuMemAllocManaged:=dll.cuMemAllocManaged).restype, cuMemAllocManaged.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuDeviceGetByPCIBusId(CUdevice *dev, const char *pciBusId) +try: (cuDeviceGetByPCIBusId:=dll.cuDeviceGetByPCIBusId).restype, cuDeviceGetByPCIBusId.argtypes = CUresult, [ctypes.POINTER(CUdevice), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuDeviceGetPCIBusId(char *pciBusId, int len, CUdevice dev) +try: (cuDeviceGetPCIBusId:=dll.cuDeviceGetPCIBusId).restype, cuDeviceGetPCIBusId.argtypes = CUresult, [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, CUdevice] +except AttributeError: pass + +# CUresult cuIpcGetEventHandle(CUipcEventHandle *pHandle, CUevent event) +try: (cuIpcGetEventHandle:=dll.cuIpcGetEventHandle).restype, cuIpcGetEventHandle.argtypes = CUresult, [ctypes.POINTER(CUipcEventHandle), CUevent] +except AttributeError: pass + +# CUresult cuIpcOpenEventHandle(CUevent *phEvent, CUipcEventHandle handle) +try: (cuIpcOpenEventHandle:=dll.cuIpcOpenEventHandle).restype, cuIpcOpenEventHandle.argtypes = CUresult, [ctypes.POINTER(CUevent), CUipcEventHandle] +except AttributeError: pass + +# CUresult cuIpcGetMemHandle(CUipcMemHandle *pHandle, CUdeviceptr dptr) +try: (cuIpcGetMemHandle:=dll.cuIpcGetMemHandle).restype, cuIpcGetMemHandle.argtypes = CUresult, [ctypes.POINTER(CUipcMemHandle), CUdeviceptr] +except AttributeError: pass + +# CUresult cuIpcOpenMemHandle_v2(CUdeviceptr *pdptr, CUipcMemHandle handle, unsigned int Flags) +try: (cuIpcOpenMemHandle_v2:=dll.cuIpcOpenMemHandle_v2).restype, cuIpcOpenMemHandle_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), CUipcMemHandle, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuIpcCloseMemHandle(CUdeviceptr dptr) +try: (cuIpcCloseMemHandle:=dll.cuIpcCloseMemHandle).restype, cuIpcCloseMemHandle.argtypes = CUresult, [CUdeviceptr] +except AttributeError: pass + +# CUresult cuMemHostRegister_v2(void *p, size_t bytesize, unsigned int Flags) +try: (cuMemHostRegister_v2:=dll.cuMemHostRegister_v2).restype, cuMemHostRegister_v2.argtypes = CUresult, [ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemHostUnregister(void *p) +try: (cuMemHostUnregister:=dll.cuMemHostUnregister).restype, cuMemHostUnregister.argtypes = CUresult, [ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuMemcpy_ptds(CUdeviceptr dst, CUdeviceptr src, size_t ByteCount) +try: (cuMemcpy_ptds:=dll.cuMemcpy_ptds).restype, cuMemcpy_ptds.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyPeer_ptds(CUdeviceptr dstDevice, CUcontext dstContext, CUdeviceptr srcDevice, CUcontext srcContext, size_t ByteCount) +try: (cuMemcpyPeer_ptds:=dll.cuMemcpyPeer_ptds).restype, cuMemcpyPeer_ptds.argtypes = CUresult, [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t] +except AttributeError: pass + +# CUresult cuMemcpyHtoD_v2_ptds(CUdeviceptr dstDevice, const void *srcHost, size_t ByteCount) +try: (cuMemcpyHtoD_v2_ptds:=dll.cuMemcpyHtoD_v2_ptds).restype, cuMemcpyHtoD_v2_ptds.argtypes = CUresult, [CUdeviceptr, ctypes.c_void_p, size_t] +except AttributeError: pass + +# CUresult cuMemcpyDtoH_v2_ptds(void *dstHost, CUdeviceptr srcDevice, size_t ByteCount) +try: (cuMemcpyDtoH_v2_ptds:=dll.cuMemcpyDtoH_v2_ptds).restype, cuMemcpyDtoH_v2_ptds.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyDtoD_v2_ptds(CUdeviceptr dstDevice, CUdeviceptr srcDevice, size_t ByteCount) +try: (cuMemcpyDtoD_v2_ptds:=dll.cuMemcpyDtoD_v2_ptds).restype, cuMemcpyDtoD_v2_ptds.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyDtoA_v2_ptds(CUarray dstArray, size_t dstOffset, CUdeviceptr srcDevice, size_t ByteCount) +try: (cuMemcpyDtoA_v2_ptds:=dll.cuMemcpyDtoA_v2_ptds).restype, cuMemcpyDtoA_v2_ptds.argtypes = CUresult, [CUarray, size_t, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAtoD_v2_ptds(CUdeviceptr dstDevice, CUarray srcArray, size_t srcOffset, size_t ByteCount) +try: (cuMemcpyAtoD_v2_ptds:=dll.cuMemcpyAtoD_v2_ptds).restype, cuMemcpyAtoD_v2_ptds.argtypes = CUresult, [CUdeviceptr, CUarray, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpyHtoA_v2_ptds(CUarray dstArray, size_t dstOffset, const void *srcHost, size_t ByteCount) +try: (cuMemcpyHtoA_v2_ptds:=dll.cuMemcpyHtoA_v2_ptds).restype, cuMemcpyHtoA_v2_ptds.argtypes = CUresult, [CUarray, size_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAtoH_v2_ptds(void *dstHost, CUarray srcArray, size_t srcOffset, size_t ByteCount) +try: (cuMemcpyAtoH_v2_ptds:=dll.cuMemcpyAtoH_v2_ptds).restype, cuMemcpyAtoH_v2_ptds.argtypes = CUresult, [ctypes.c_void_p, CUarray, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAtoA_v2_ptds(CUarray dstArray, size_t dstOffset, CUarray srcArray, size_t srcOffset, size_t ByteCount) +try: (cuMemcpyAtoA_v2_ptds:=dll.cuMemcpyAtoA_v2_ptds).restype, cuMemcpyAtoA_v2_ptds.argtypes = CUresult, [CUarray, size_t, CUarray, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpy2D_v2_ptds(const CUDA_MEMCPY2D *pCopy) +try: (cuMemcpy2D_v2_ptds:=dll.cuMemcpy2D_v2_ptds).restype, cuMemcpy2D_v2_ptds.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D)] +except AttributeError: pass + +# CUresult cuMemcpy2DUnaligned_v2_ptds(const CUDA_MEMCPY2D *pCopy) +try: (cuMemcpy2DUnaligned_v2_ptds:=dll.cuMemcpy2DUnaligned_v2_ptds).restype, cuMemcpy2DUnaligned_v2_ptds.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D)] +except AttributeError: pass + +# CUresult cuMemcpy3D_v2_ptds(const CUDA_MEMCPY3D *pCopy) +try: (cuMemcpy3D_v2_ptds:=dll.cuMemcpy3D_v2_ptds).restype, cuMemcpy3D_v2_ptds.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D)] +except AttributeError: pass + +# CUresult cuMemcpy3DPeer_ptds(const CUDA_MEMCPY3D_PEER *pCopy) +try: (cuMemcpy3DPeer_ptds:=dll.cuMemcpy3DPeer_ptds).restype, cuMemcpy3DPeer_ptds.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D_PEER)] +except AttributeError: pass + +# CUresult cuMemcpyAsync_ptsz(CUdeviceptr dst, CUdeviceptr src, size_t ByteCount, CUstream hStream) +try: (cuMemcpyAsync_ptsz:=dll.cuMemcpyAsync_ptsz).restype, cuMemcpyAsync_ptsz.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyPeerAsync_ptsz(CUdeviceptr dstDevice, CUcontext dstContext, CUdeviceptr srcDevice, CUcontext srcContext, size_t ByteCount, CUstream hStream) +try: (cuMemcpyPeerAsync_ptsz:=dll.cuMemcpyPeerAsync_ptsz).restype, cuMemcpyPeerAsync_ptsz.argtypes = CUresult, [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyHtoDAsync_v2_ptsz(CUdeviceptr dstDevice, const void *srcHost, size_t ByteCount, CUstream hStream) +try: (cuMemcpyHtoDAsync_v2_ptsz:=dll.cuMemcpyHtoDAsync_v2_ptsz).restype, cuMemcpyHtoDAsync_v2_ptsz.argtypes = CUresult, [CUdeviceptr, ctypes.c_void_p, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyDtoHAsync_v2_ptsz(void *dstHost, CUdeviceptr srcDevice, size_t ByteCount, CUstream hStream) +try: (cuMemcpyDtoHAsync_v2_ptsz:=dll.cuMemcpyDtoHAsync_v2_ptsz).restype, cuMemcpyDtoHAsync_v2_ptsz.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyDtoDAsync_v2_ptsz(CUdeviceptr dstDevice, CUdeviceptr srcDevice, size_t ByteCount, CUstream hStream) +try: (cuMemcpyDtoDAsync_v2_ptsz:=dll.cuMemcpyDtoDAsync_v2_ptsz).restype, cuMemcpyDtoDAsync_v2_ptsz.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyHtoAAsync_v2_ptsz(CUarray dstArray, size_t dstOffset, const void *srcHost, size_t ByteCount, CUstream hStream) +try: (cuMemcpyHtoAAsync_v2_ptsz:=dll.cuMemcpyHtoAAsync_v2_ptsz).restype, cuMemcpyHtoAAsync_v2_ptsz.argtypes = CUresult, [CUarray, size_t, ctypes.c_void_p, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyAtoHAsync_v2_ptsz(void *dstHost, CUarray srcArray, size_t srcOffset, size_t ByteCount, CUstream hStream) +try: (cuMemcpyAtoHAsync_v2_ptsz:=dll.cuMemcpyAtoHAsync_v2_ptsz).restype, cuMemcpyAtoHAsync_v2_ptsz.argtypes = CUresult, [ctypes.c_void_p, CUarray, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpy2DAsync_v2_ptsz(const CUDA_MEMCPY2D *pCopy, CUstream hStream) +try: (cuMemcpy2DAsync_v2_ptsz:=dll.cuMemcpy2DAsync_v2_ptsz).restype, cuMemcpy2DAsync_v2_ptsz.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D), CUstream] +except AttributeError: pass + +# CUresult cuMemcpy3DAsync_v2_ptsz(const CUDA_MEMCPY3D *pCopy, CUstream hStream) +try: (cuMemcpy3DAsync_v2_ptsz:=dll.cuMemcpy3DAsync_v2_ptsz).restype, cuMemcpy3DAsync_v2_ptsz.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D), CUstream] +except AttributeError: pass + +# CUresult cuMemcpy3DPeerAsync_ptsz(const CUDA_MEMCPY3D_PEER *pCopy, CUstream hStream) +try: (cuMemcpy3DPeerAsync_ptsz:=dll.cuMemcpy3DPeerAsync_ptsz).restype, cuMemcpy3DPeerAsync_ptsz.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D_PEER), CUstream] +except AttributeError: pass + +# CUresult cuMemsetD8_v2_ptds(CUdeviceptr dstDevice, unsigned char uc, size_t N) +try: (cuMemsetD8_v2_ptds:=dll.cuMemsetD8_v2_ptds).restype, cuMemsetD8_v2_ptds.argtypes = CUresult, [CUdeviceptr, ctypes.c_ubyte, size_t] +except AttributeError: pass + +# CUresult cuMemsetD16_v2_ptds(CUdeviceptr dstDevice, unsigned short us, size_t N) +try: (cuMemsetD16_v2_ptds:=dll.cuMemsetD16_v2_ptds).restype, cuMemsetD16_v2_ptds.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint16, size_t] +except AttributeError: pass + +# CUresult cuMemsetD32_v2_ptds(CUdeviceptr dstDevice, unsigned int ui, size_t N) +try: (cuMemsetD32_v2_ptds:=dll.cuMemsetD32_v2_ptds).restype, cuMemsetD32_v2_ptds.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint32, size_t] +except AttributeError: pass + +# CUresult cuMemsetD2D8_v2_ptds(CUdeviceptr dstDevice, size_t dstPitch, unsigned char uc, size_t Width, size_t Height) +try: (cuMemsetD2D8_v2_ptds:=dll.cuMemsetD2D8_v2_ptds).restype, cuMemsetD2D8_v2_ptds.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemsetD2D16_v2_ptds(CUdeviceptr dstDevice, size_t dstPitch, unsigned short us, size_t Width, size_t Height) +try: (cuMemsetD2D16_v2_ptds:=dll.cuMemsetD2D16_v2_ptds).restype, cuMemsetD2D16_v2_ptds.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemsetD2D32_v2_ptds(CUdeviceptr dstDevice, size_t dstPitch, unsigned int ui, size_t Width, size_t Height) +try: (cuMemsetD2D32_v2_ptds:=dll.cuMemsetD2D32_v2_ptds).restype, cuMemsetD2D32_v2_ptds.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemsetD8Async_ptsz(CUdeviceptr dstDevice, unsigned char uc, size_t N, CUstream hStream) +try: (cuMemsetD8Async_ptsz:=dll.cuMemsetD8Async_ptsz).restype, cuMemsetD8Async_ptsz.argtypes = CUresult, [CUdeviceptr, ctypes.c_ubyte, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD16Async_ptsz(CUdeviceptr dstDevice, unsigned short us, size_t N, CUstream hStream) +try: (cuMemsetD16Async_ptsz:=dll.cuMemsetD16Async_ptsz).restype, cuMemsetD16Async_ptsz.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint16, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD32Async_ptsz(CUdeviceptr dstDevice, unsigned int ui, size_t N, CUstream hStream) +try: (cuMemsetD32Async_ptsz:=dll.cuMemsetD32Async_ptsz).restype, cuMemsetD32Async_ptsz.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint32, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD2D8Async_ptsz(CUdeviceptr dstDevice, size_t dstPitch, unsigned char uc, size_t Width, size_t Height, CUstream hStream) +try: (cuMemsetD2D8Async_ptsz:=dll.cuMemsetD2D8Async_ptsz).restype, cuMemsetD2D8Async_ptsz.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD2D16Async_ptsz(CUdeviceptr dstDevice, size_t dstPitch, unsigned short us, size_t Width, size_t Height, CUstream hStream) +try: (cuMemsetD2D16Async_ptsz:=dll.cuMemsetD2D16Async_ptsz).restype, cuMemsetD2D16Async_ptsz.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD2D32Async_ptsz(CUdeviceptr dstDevice, size_t dstPitch, unsigned int ui, size_t Width, size_t Height, CUstream hStream) +try: (cuMemsetD2D32Async_ptsz:=dll.cuMemsetD2D32Async_ptsz).restype, cuMemsetD2D32Async_ptsz.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuArrayCreate_v2(CUarray *pHandle, const CUDA_ARRAY_DESCRIPTOR *pAllocateArray) +try: (cuArrayCreate_v2:=dll.cuArrayCreate_v2).restype, cuArrayCreate_v2.argtypes = CUresult, [ctypes.POINTER(CUarray), ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR)] +except AttributeError: pass + +# CUresult cuArrayGetDescriptor_v2(CUDA_ARRAY_DESCRIPTOR *pArrayDescriptor, CUarray hArray) +try: (cuArrayGetDescriptor_v2:=dll.cuArrayGetDescriptor_v2).restype, cuArrayGetDescriptor_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR), CUarray] +except AttributeError: pass + +# CUresult cuArrayGetSparseProperties(CUDA_ARRAY_SPARSE_PROPERTIES *sparseProperties, CUarray array) +try: (cuArrayGetSparseProperties:=dll.cuArrayGetSparseProperties).restype, cuArrayGetSparseProperties.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY_SPARSE_PROPERTIES), CUarray] +except AttributeError: pass + +# CUresult cuMipmappedArrayGetSparseProperties(CUDA_ARRAY_SPARSE_PROPERTIES *sparseProperties, CUmipmappedArray mipmap) +try: (cuMipmappedArrayGetSparseProperties:=dll.cuMipmappedArrayGetSparseProperties).restype, cuMipmappedArrayGetSparseProperties.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY_SPARSE_PROPERTIES), CUmipmappedArray] +except AttributeError: pass + +# CUresult cuArrayGetMemoryRequirements(CUDA_ARRAY_MEMORY_REQUIREMENTS *memoryRequirements, CUarray array, CUdevice device) +try: (cuArrayGetMemoryRequirements:=dll.cuArrayGetMemoryRequirements).restype, cuArrayGetMemoryRequirements.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY_MEMORY_REQUIREMENTS), CUarray, CUdevice] +except AttributeError: pass + +# CUresult cuMipmappedArrayGetMemoryRequirements(CUDA_ARRAY_MEMORY_REQUIREMENTS *memoryRequirements, CUmipmappedArray mipmap, CUdevice device) +try: (cuMipmappedArrayGetMemoryRequirements:=dll.cuMipmappedArrayGetMemoryRequirements).restype, cuMipmappedArrayGetMemoryRequirements.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY_MEMORY_REQUIREMENTS), CUmipmappedArray, CUdevice] +except AttributeError: pass + +# CUresult cuArrayGetPlane(CUarray *pPlaneArray, CUarray hArray, unsigned int planeIdx) +try: (cuArrayGetPlane:=dll.cuArrayGetPlane).restype, cuArrayGetPlane.argtypes = CUresult, [ctypes.POINTER(CUarray), CUarray, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuArrayDestroy(CUarray hArray) +try: (cuArrayDestroy:=dll.cuArrayDestroy).restype, cuArrayDestroy.argtypes = CUresult, [CUarray] +except AttributeError: pass + +# CUresult cuArray3DCreate_v2(CUarray *pHandle, const CUDA_ARRAY3D_DESCRIPTOR *pAllocateArray) +try: (cuArray3DCreate_v2:=dll.cuArray3DCreate_v2).restype, cuArray3DCreate_v2.argtypes = CUresult, [ctypes.POINTER(CUarray), ctypes.POINTER(CUDA_ARRAY3D_DESCRIPTOR)] +except AttributeError: pass + +# CUresult cuArray3DGetDescriptor_v2(CUDA_ARRAY3D_DESCRIPTOR *pArrayDescriptor, CUarray hArray) +try: (cuArray3DGetDescriptor_v2:=dll.cuArray3DGetDescriptor_v2).restype, cuArray3DGetDescriptor_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY3D_DESCRIPTOR), CUarray] +except AttributeError: pass + +# CUresult cuMipmappedArrayCreate(CUmipmappedArray *pHandle, const CUDA_ARRAY3D_DESCRIPTOR *pMipmappedArrayDesc, unsigned int numMipmapLevels) +try: (cuMipmappedArrayCreate:=dll.cuMipmappedArrayCreate).restype, cuMipmappedArrayCreate.argtypes = CUresult, [ctypes.POINTER(CUmipmappedArray), ctypes.POINTER(CUDA_ARRAY3D_DESCRIPTOR), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMipmappedArrayGetLevel(CUarray *pLevelArray, CUmipmappedArray hMipmappedArray, unsigned int level) +try: (cuMipmappedArrayGetLevel:=dll.cuMipmappedArrayGetLevel).restype, cuMipmappedArrayGetLevel.argtypes = CUresult, [ctypes.POINTER(CUarray), CUmipmappedArray, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMipmappedArrayDestroy(CUmipmappedArray hMipmappedArray) +try: (cuMipmappedArrayDestroy:=dll.cuMipmappedArrayDestroy).restype, cuMipmappedArrayDestroy.argtypes = CUresult, [CUmipmappedArray] +except AttributeError: pass + +# CUresult cuMemGetHandleForAddressRange(void *handle, CUdeviceptr dptr, size_t size, CUmemRangeHandleType handleType, unsigned long long flags) +try: (cuMemGetHandleForAddressRange:=dll.cuMemGetHandleForAddressRange).restype, cuMemGetHandleForAddressRange.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr, size_t, CUmemRangeHandleType, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemAddressReserve(CUdeviceptr *ptr, size_t size, size_t alignment, CUdeviceptr addr, unsigned long long flags) +try: (cuMemAddressReserve:=dll.cuMemAddressReserve).restype, cuMemAddressReserve.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t, size_t, CUdeviceptr, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemAddressFree(CUdeviceptr ptr, size_t size) +try: (cuMemAddressFree:=dll.cuMemAddressFree).restype, cuMemAddressFree.argtypes = CUresult, [CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemCreate(CUmemGenericAllocationHandle *handle, size_t size, const CUmemAllocationProp *prop, unsigned long long flags) +try: (cuMemCreate:=dll.cuMemCreate).restype, cuMemCreate.argtypes = CUresult, [ctypes.POINTER(CUmemGenericAllocationHandle), size_t, ctypes.POINTER(CUmemAllocationProp), ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemRelease(CUmemGenericAllocationHandle handle) +try: (cuMemRelease:=dll.cuMemRelease).restype, cuMemRelease.argtypes = CUresult, [CUmemGenericAllocationHandle] +except AttributeError: pass + +# CUresult cuMemMap(CUdeviceptr ptr, size_t size, size_t offset, CUmemGenericAllocationHandle handle, unsigned long long flags) +try: (cuMemMap:=dll.cuMemMap).restype, cuMemMap.argtypes = CUresult, [CUdeviceptr, size_t, size_t, CUmemGenericAllocationHandle, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemMapArrayAsync_ptsz(CUarrayMapInfo *mapInfoList, unsigned int count, CUstream hStream) +try: (cuMemMapArrayAsync_ptsz:=dll.cuMemMapArrayAsync_ptsz).restype, cuMemMapArrayAsync_ptsz.argtypes = CUresult, [ctypes.POINTER(CUarrayMapInfo), ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemUnmap(CUdeviceptr ptr, size_t size) +try: (cuMemUnmap:=dll.cuMemUnmap).restype, cuMemUnmap.argtypes = CUresult, [CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemSetAccess(CUdeviceptr ptr, size_t size, const CUmemAccessDesc *desc, size_t count) +try: (cuMemSetAccess:=dll.cuMemSetAccess).restype, cuMemSetAccess.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.POINTER(CUmemAccessDesc), size_t] +except AttributeError: pass + +# CUresult cuMemGetAccess(unsigned long long *flags, const CUmemLocation *location, CUdeviceptr ptr) +try: (cuMemGetAccess:=dll.cuMemGetAccess).restype, cuMemGetAccess.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(CUmemLocation), CUdeviceptr] +except AttributeError: pass + +# CUresult cuMemExportToShareableHandle(void *shareableHandle, CUmemGenericAllocationHandle handle, CUmemAllocationHandleType handleType, unsigned long long flags) +try: (cuMemExportToShareableHandle:=dll.cuMemExportToShareableHandle).restype, cuMemExportToShareableHandle.argtypes = CUresult, [ctypes.c_void_p, CUmemGenericAllocationHandle, CUmemAllocationHandleType, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemImportFromShareableHandle(CUmemGenericAllocationHandle *handle, void *osHandle, CUmemAllocationHandleType shHandleType) +try: (cuMemImportFromShareableHandle:=dll.cuMemImportFromShareableHandle).restype, cuMemImportFromShareableHandle.argtypes = CUresult, [ctypes.POINTER(CUmemGenericAllocationHandle), ctypes.c_void_p, CUmemAllocationHandleType] +except AttributeError: pass + +# CUresult cuMemGetAllocationGranularity(size_t *granularity, const CUmemAllocationProp *prop, CUmemAllocationGranularity_flags option) +try: (cuMemGetAllocationGranularity:=dll.cuMemGetAllocationGranularity).restype, cuMemGetAllocationGranularity.argtypes = CUresult, [ctypes.POINTER(size_t), ctypes.POINTER(CUmemAllocationProp), CUmemAllocationGranularity_flags] +except AttributeError: pass + +# CUresult cuMemGetAllocationPropertiesFromHandle(CUmemAllocationProp *prop, CUmemGenericAllocationHandle handle) +try: (cuMemGetAllocationPropertiesFromHandle:=dll.cuMemGetAllocationPropertiesFromHandle).restype, cuMemGetAllocationPropertiesFromHandle.argtypes = CUresult, [ctypes.POINTER(CUmemAllocationProp), CUmemGenericAllocationHandle] +except AttributeError: pass + +# CUresult cuMemRetainAllocationHandle(CUmemGenericAllocationHandle *handle, void *addr) +try: (cuMemRetainAllocationHandle:=dll.cuMemRetainAllocationHandle).restype, cuMemRetainAllocationHandle.argtypes = CUresult, [ctypes.POINTER(CUmemGenericAllocationHandle), ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuMemFreeAsync_ptsz(CUdeviceptr dptr, CUstream hStream) +try: (cuMemFreeAsync_ptsz:=dll.cuMemFreeAsync_ptsz).restype, cuMemFreeAsync_ptsz.argtypes = CUresult, [CUdeviceptr, CUstream] +except AttributeError: pass + +# CUresult cuMemAllocAsync_ptsz(CUdeviceptr *dptr, size_t bytesize, CUstream hStream) +try: (cuMemAllocAsync_ptsz:=dll.cuMemAllocAsync_ptsz).restype, cuMemAllocAsync_ptsz.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemPoolTrimTo(CUmemoryPool pool, size_t minBytesToKeep) +try: (cuMemPoolTrimTo:=dll.cuMemPoolTrimTo).restype, cuMemPoolTrimTo.argtypes = CUresult, [CUmemoryPool, size_t] +except AttributeError: pass + +# CUresult cuMemPoolSetAttribute(CUmemoryPool pool, CUmemPool_attribute attr, void *value) +try: (cuMemPoolSetAttribute:=dll.cuMemPoolSetAttribute).restype, cuMemPoolSetAttribute.argtypes = CUresult, [CUmemoryPool, CUmemPool_attribute, ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuMemPoolGetAttribute(CUmemoryPool pool, CUmemPool_attribute attr, void *value) +try: (cuMemPoolGetAttribute:=dll.cuMemPoolGetAttribute).restype, cuMemPoolGetAttribute.argtypes = CUresult, [CUmemoryPool, CUmemPool_attribute, ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuMemPoolSetAccess(CUmemoryPool pool, const CUmemAccessDesc *map, size_t count) +try: (cuMemPoolSetAccess:=dll.cuMemPoolSetAccess).restype, cuMemPoolSetAccess.argtypes = CUresult, [CUmemoryPool, ctypes.POINTER(CUmemAccessDesc), size_t] +except AttributeError: pass + +# CUresult cuMemPoolGetAccess(CUmemAccess_flags *flags, CUmemoryPool memPool, CUmemLocation *location) +try: (cuMemPoolGetAccess:=dll.cuMemPoolGetAccess).restype, cuMemPoolGetAccess.argtypes = CUresult, [ctypes.POINTER(CUmemAccess_flags), CUmemoryPool, ctypes.POINTER(CUmemLocation)] +except AttributeError: pass + +# CUresult cuMemPoolCreate(CUmemoryPool *pool, const CUmemPoolProps *poolProps) +try: (cuMemPoolCreate:=dll.cuMemPoolCreate).restype, cuMemPoolCreate.argtypes = CUresult, [ctypes.POINTER(CUmemoryPool), ctypes.POINTER(CUmemPoolProps)] +except AttributeError: pass + +# CUresult cuMemPoolDestroy(CUmemoryPool pool) +try: (cuMemPoolDestroy:=dll.cuMemPoolDestroy).restype, cuMemPoolDestroy.argtypes = CUresult, [CUmemoryPool] +except AttributeError: pass + +# CUresult cuMemAllocFromPoolAsync_ptsz(CUdeviceptr *dptr, size_t bytesize, CUmemoryPool pool, CUstream hStream) +try: (cuMemAllocFromPoolAsync_ptsz:=dll.cuMemAllocFromPoolAsync_ptsz).restype, cuMemAllocFromPoolAsync_ptsz.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t, CUmemoryPool, CUstream] +except AttributeError: pass + +# CUresult cuMemPoolExportToShareableHandle(void *handle_out, CUmemoryPool pool, CUmemAllocationHandleType handleType, unsigned long long flags) +try: (cuMemPoolExportToShareableHandle:=dll.cuMemPoolExportToShareableHandle).restype, cuMemPoolExportToShareableHandle.argtypes = CUresult, [ctypes.c_void_p, CUmemoryPool, CUmemAllocationHandleType, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemPoolImportFromShareableHandle(CUmemoryPool *pool_out, void *handle, CUmemAllocationHandleType handleType, unsigned long long flags) +try: (cuMemPoolImportFromShareableHandle:=dll.cuMemPoolImportFromShareableHandle).restype, cuMemPoolImportFromShareableHandle.argtypes = CUresult, [ctypes.POINTER(CUmemoryPool), ctypes.c_void_p, CUmemAllocationHandleType, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuMemPoolExportPointer(CUmemPoolPtrExportData *shareData_out, CUdeviceptr ptr) +try: (cuMemPoolExportPointer:=dll.cuMemPoolExportPointer).restype, cuMemPoolExportPointer.argtypes = CUresult, [ctypes.POINTER(CUmemPoolPtrExportData), CUdeviceptr] +except AttributeError: pass + +# CUresult cuMemPoolImportPointer(CUdeviceptr *ptr_out, CUmemoryPool pool, CUmemPoolPtrExportData *shareData) +try: (cuMemPoolImportPointer:=dll.cuMemPoolImportPointer).restype, cuMemPoolImportPointer.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), CUmemoryPool, ctypes.POINTER(CUmemPoolPtrExportData)] +except AttributeError: pass + +# CUresult cuPointerGetAttribute(void *data, CUpointer_attribute attribute, CUdeviceptr ptr) +try: (cuPointerGetAttribute:=dll.cuPointerGetAttribute).restype, cuPointerGetAttribute.argtypes = CUresult, [ctypes.c_void_p, CUpointer_attribute, CUdeviceptr] +except AttributeError: pass + +# CUresult cuMemPrefetchAsync_ptsz(CUdeviceptr devPtr, size_t count, CUdevice dstDevice, CUstream hStream) +try: (cuMemPrefetchAsync_ptsz:=dll.cuMemPrefetchAsync_ptsz).restype, cuMemPrefetchAsync_ptsz.argtypes = CUresult, [CUdeviceptr, size_t, CUdevice, CUstream] +except AttributeError: pass + +# CUresult cuMemAdvise(CUdeviceptr devPtr, size_t count, CUmem_advise advice, CUdevice device) +try: (cuMemAdvise:=dll.cuMemAdvise).restype, cuMemAdvise.argtypes = CUresult, [CUdeviceptr, size_t, CUmem_advise, CUdevice] +except AttributeError: pass + +# CUresult cuMemRangeGetAttribute(void *data, size_t dataSize, CUmem_range_attribute attribute, CUdeviceptr devPtr, size_t count) +try: (cuMemRangeGetAttribute:=dll.cuMemRangeGetAttribute).restype, cuMemRangeGetAttribute.argtypes = CUresult, [ctypes.c_void_p, size_t, CUmem_range_attribute, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemRangeGetAttributes(void **data, size_t *dataSizes, CUmem_range_attribute *attributes, size_t numAttributes, CUdeviceptr devPtr, size_t count) +try: (cuMemRangeGetAttributes:=dll.cuMemRangeGetAttributes).restype, cuMemRangeGetAttributes.argtypes = CUresult, [ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t), ctypes.POINTER(CUmem_range_attribute), size_t, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuPointerSetAttribute(const void *value, CUpointer_attribute attribute, CUdeviceptr ptr) +try: (cuPointerSetAttribute:=dll.cuPointerSetAttribute).restype, cuPointerSetAttribute.argtypes = CUresult, [ctypes.c_void_p, CUpointer_attribute, CUdeviceptr] +except AttributeError: pass + +# CUresult cuPointerGetAttributes(unsigned int numAttributes, CUpointer_attribute *attributes, void **data, CUdeviceptr ptr) +try: (cuPointerGetAttributes:=dll.cuPointerGetAttributes).restype, cuPointerGetAttributes.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUpointer_attribute), ctypes.POINTER(ctypes.c_void_p), CUdeviceptr] +except AttributeError: pass + +# CUresult cuStreamCreate(CUstream *phStream, unsigned int Flags) +try: (cuStreamCreate:=dll.cuStreamCreate).restype, cuStreamCreate.argtypes = CUresult, [ctypes.POINTER(CUstream), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamCreateWithPriority(CUstream *phStream, unsigned int flags, int priority) +try: (cuStreamCreateWithPriority:=dll.cuStreamCreateWithPriority).restype, cuStreamCreateWithPriority.argtypes = CUresult, [ctypes.POINTER(CUstream), ctypes.c_uint32, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuStreamGetPriority_ptsz(CUstream hStream, int *priority) +try: (cuStreamGetPriority_ptsz:=dll.cuStreamGetPriority_ptsz).restype, cuStreamGetPriority_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# CUresult cuStreamGetFlags_ptsz(CUstream hStream, unsigned int *flags) +try: (cuStreamGetFlags_ptsz:=dll.cuStreamGetFlags_ptsz).restype, cuStreamGetFlags_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# CUresult cuStreamGetId_ptsz(CUstream hStream, unsigned long long *streamId) +try: (cuStreamGetId_ptsz:=dll.cuStreamGetId_ptsz).restype, cuStreamGetId_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(ctypes.c_uint64)] +except AttributeError: pass + +# CUresult cuStreamGetCtx_ptsz(CUstream hStream, CUcontext *pctx) +try: (cuStreamGetCtx_ptsz:=dll.cuStreamGetCtx_ptsz).restype, cuStreamGetCtx_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(CUcontext)] +except AttributeError: pass + +# CUresult cuStreamWaitEvent_ptsz(CUstream hStream, CUevent hEvent, unsigned int Flags) +try: (cuStreamWaitEvent_ptsz:=dll.cuStreamWaitEvent_ptsz).restype, cuStreamWaitEvent_ptsz.argtypes = CUresult, [CUstream, CUevent, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamAddCallback_ptsz(CUstream hStream, CUstreamCallback callback, void *userData, unsigned int flags) +try: (cuStreamAddCallback_ptsz:=dll.cuStreamAddCallback_ptsz).restype, cuStreamAddCallback_ptsz.argtypes = CUresult, [CUstream, CUstreamCallback, ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamBeginCapture_v2_ptsz(CUstream hStream, CUstreamCaptureMode mode) +try: (cuStreamBeginCapture_v2_ptsz:=dll.cuStreamBeginCapture_v2_ptsz).restype, cuStreamBeginCapture_v2_ptsz.argtypes = CUresult, [CUstream, CUstreamCaptureMode] +except AttributeError: pass + +# CUresult cuThreadExchangeStreamCaptureMode(CUstreamCaptureMode *mode) +try: (cuThreadExchangeStreamCaptureMode:=dll.cuThreadExchangeStreamCaptureMode).restype, cuThreadExchangeStreamCaptureMode.argtypes = CUresult, [ctypes.POINTER(CUstreamCaptureMode)] +except AttributeError: pass + +# CUresult cuStreamEndCapture_ptsz(CUstream hStream, CUgraph *phGraph) +try: (cuStreamEndCapture_ptsz:=dll.cuStreamEndCapture_ptsz).restype, cuStreamEndCapture_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(CUgraph)] +except AttributeError: pass + +# CUresult cuStreamIsCapturing_ptsz(CUstream hStream, CUstreamCaptureStatus *captureStatus) +try: (cuStreamIsCapturing_ptsz:=dll.cuStreamIsCapturing_ptsz).restype, cuStreamIsCapturing_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(CUstreamCaptureStatus)] +except AttributeError: pass + +# CUresult cuStreamGetCaptureInfo_v2_ptsz(CUstream hStream, CUstreamCaptureStatus *captureStatus_out, cuuint64_t *id_out, CUgraph *graph_out, const CUgraphNode **dependencies_out, size_t *numDependencies_out) +try: (cuStreamGetCaptureInfo_v2_ptsz:=dll.cuStreamGetCaptureInfo_v2_ptsz).restype, cuStreamGetCaptureInfo_v2_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(CUstreamCaptureStatus), ctypes.POINTER(cuuint64_t), ctypes.POINTER(CUgraph), ctypes.POINTER(ctypes.POINTER(CUgraphNode)), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuStreamUpdateCaptureDependencies_ptsz(CUstream hStream, CUgraphNode *dependencies, size_t numDependencies, unsigned int flags) +try: (cuStreamUpdateCaptureDependencies_ptsz:=dll.cuStreamUpdateCaptureDependencies_ptsz).restype, cuStreamUpdateCaptureDependencies_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(CUgraphNode), size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamAttachMemAsync_ptsz(CUstream hStream, CUdeviceptr dptr, size_t length, unsigned int flags) +try: (cuStreamAttachMemAsync_ptsz:=dll.cuStreamAttachMemAsync_ptsz).restype, cuStreamAttachMemAsync_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamQuery_ptsz(CUstream hStream) +try: (cuStreamQuery_ptsz:=dll.cuStreamQuery_ptsz).restype, cuStreamQuery_ptsz.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuStreamSynchronize_ptsz(CUstream hStream) +try: (cuStreamSynchronize_ptsz:=dll.cuStreamSynchronize_ptsz).restype, cuStreamSynchronize_ptsz.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuStreamDestroy_v2(CUstream hStream) +try: (cuStreamDestroy_v2:=dll.cuStreamDestroy_v2).restype, cuStreamDestroy_v2.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuStreamCopyAttributes_ptsz(CUstream dst, CUstream src) +try: (cuStreamCopyAttributes_ptsz:=dll.cuStreamCopyAttributes_ptsz).restype, cuStreamCopyAttributes_ptsz.argtypes = CUresult, [CUstream, CUstream] +except AttributeError: pass + +# CUresult cuStreamGetAttribute_ptsz(CUstream hStream, CUstreamAttrID attr, CUstreamAttrValue *value_out) +try: (cuStreamGetAttribute_ptsz:=dll.cuStreamGetAttribute_ptsz).restype, cuStreamGetAttribute_ptsz.argtypes = CUresult, [CUstream, CUstreamAttrID, ctypes.POINTER(CUstreamAttrValue)] +except AttributeError: pass + +# CUresult cuStreamSetAttribute_ptsz(CUstream hStream, CUstreamAttrID attr, const CUstreamAttrValue *value) +try: (cuStreamSetAttribute_ptsz:=dll.cuStreamSetAttribute_ptsz).restype, cuStreamSetAttribute_ptsz.argtypes = CUresult, [CUstream, CUstreamAttrID, ctypes.POINTER(CUstreamAttrValue)] +except AttributeError: pass + +# CUresult cuEventCreate(CUevent *phEvent, unsigned int Flags) +try: (cuEventCreate:=dll.cuEventCreate).restype, cuEventCreate.argtypes = CUresult, [ctypes.POINTER(CUevent), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuEventRecord_ptsz(CUevent hEvent, CUstream hStream) +try: (cuEventRecord_ptsz:=dll.cuEventRecord_ptsz).restype, cuEventRecord_ptsz.argtypes = CUresult, [CUevent, CUstream] +except AttributeError: pass + +# CUresult cuEventRecordWithFlags_ptsz(CUevent hEvent, CUstream hStream, unsigned int flags) +try: (cuEventRecordWithFlags_ptsz:=dll.cuEventRecordWithFlags_ptsz).restype, cuEventRecordWithFlags_ptsz.argtypes = CUresult, [CUevent, CUstream, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuEventQuery(CUevent hEvent) +try: (cuEventQuery:=dll.cuEventQuery).restype, cuEventQuery.argtypes = CUresult, [CUevent] +except AttributeError: pass + +# CUresult cuEventSynchronize(CUevent hEvent) +try: (cuEventSynchronize:=dll.cuEventSynchronize).restype, cuEventSynchronize.argtypes = CUresult, [CUevent] +except AttributeError: pass + +# CUresult cuEventDestroy_v2(CUevent hEvent) +try: (cuEventDestroy_v2:=dll.cuEventDestroy_v2).restype, cuEventDestroy_v2.argtypes = CUresult, [CUevent] +except AttributeError: pass + +# CUresult cuEventElapsedTime(float *pMilliseconds, CUevent hStart, CUevent hEnd) +try: (cuEventElapsedTime:=dll.cuEventElapsedTime).restype, cuEventElapsedTime.argtypes = CUresult, [ctypes.POINTER(ctypes.c_float), CUevent, CUevent] +except AttributeError: pass + +# CUresult cuImportExternalMemory(CUexternalMemory *extMem_out, const CUDA_EXTERNAL_MEMORY_HANDLE_DESC *memHandleDesc) +try: (cuImportExternalMemory:=dll.cuImportExternalMemory).restype, cuImportExternalMemory.argtypes = CUresult, [ctypes.POINTER(CUexternalMemory), ctypes.POINTER(CUDA_EXTERNAL_MEMORY_HANDLE_DESC)] +except AttributeError: pass + +# CUresult cuExternalMemoryGetMappedBuffer(CUdeviceptr *devPtr, CUexternalMemory extMem, const CUDA_EXTERNAL_MEMORY_BUFFER_DESC *bufferDesc) +try: (cuExternalMemoryGetMappedBuffer:=dll.cuExternalMemoryGetMappedBuffer).restype, cuExternalMemoryGetMappedBuffer.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), CUexternalMemory, ctypes.POINTER(CUDA_EXTERNAL_MEMORY_BUFFER_DESC)] +except AttributeError: pass + +# CUresult cuExternalMemoryGetMappedMipmappedArray(CUmipmappedArray *mipmap, CUexternalMemory extMem, const CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC *mipmapDesc) +try: (cuExternalMemoryGetMappedMipmappedArray:=dll.cuExternalMemoryGetMappedMipmappedArray).restype, cuExternalMemoryGetMappedMipmappedArray.argtypes = CUresult, [ctypes.POINTER(CUmipmappedArray), CUexternalMemory, ctypes.POINTER(CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC)] +except AttributeError: pass + +# CUresult cuDestroyExternalMemory(CUexternalMemory extMem) +try: (cuDestroyExternalMemory:=dll.cuDestroyExternalMemory).restype, cuDestroyExternalMemory.argtypes = CUresult, [CUexternalMemory] +except AttributeError: pass + +# CUresult cuImportExternalSemaphore(CUexternalSemaphore *extSem_out, const CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC *semHandleDesc) +try: (cuImportExternalSemaphore:=dll.cuImportExternalSemaphore).restype, cuImportExternalSemaphore.argtypes = CUresult, [ctypes.POINTER(CUexternalSemaphore), ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC)] +except AttributeError: pass + +# CUresult cuSignalExternalSemaphoresAsync_ptsz(const CUexternalSemaphore *extSemArray, const CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS *paramsArray, unsigned int numExtSems, CUstream stream) +try: (cuSignalExternalSemaphoresAsync_ptsz:=dll.cuSignalExternalSemaphoresAsync_ptsz).restype, cuSignalExternalSemaphoresAsync_ptsz.argtypes = CUresult, [ctypes.POINTER(CUexternalSemaphore), ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS), ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuWaitExternalSemaphoresAsync_ptsz(const CUexternalSemaphore *extSemArray, const CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS *paramsArray, unsigned int numExtSems, CUstream stream) +try: (cuWaitExternalSemaphoresAsync_ptsz:=dll.cuWaitExternalSemaphoresAsync_ptsz).restype, cuWaitExternalSemaphoresAsync_ptsz.argtypes = CUresult, [ctypes.POINTER(CUexternalSemaphore), ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS), ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuDestroyExternalSemaphore(CUexternalSemaphore extSem) +try: (cuDestroyExternalSemaphore:=dll.cuDestroyExternalSemaphore).restype, cuDestroyExternalSemaphore.argtypes = CUresult, [CUexternalSemaphore] +except AttributeError: pass + +# CUresult cuStreamWaitValue32_v2_ptsz(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWaitValue32_v2_ptsz:=dll.cuStreamWaitValue32_v2_ptsz).restype, cuStreamWaitValue32_v2_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue64_v2_ptsz(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWaitValue64_v2_ptsz:=dll.cuStreamWaitValue64_v2_ptsz).restype, cuStreamWaitValue64_v2_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue32_v2_ptsz(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWriteValue32_v2_ptsz:=dll.cuStreamWriteValue32_v2_ptsz).restype, cuStreamWriteValue32_v2_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue64_v2_ptsz(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWriteValue64_v2_ptsz:=dll.cuStreamWriteValue64_v2_ptsz).restype, cuStreamWriteValue64_v2_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamBatchMemOp_v2_ptsz(CUstream stream, unsigned int count, CUstreamBatchMemOpParams *paramArray, unsigned int flags) +try: (cuStreamBatchMemOp_v2_ptsz:=dll.cuStreamBatchMemOp_v2_ptsz).restype, cuStreamBatchMemOp_v2_ptsz.argtypes = CUresult, [CUstream, ctypes.c_uint32, ctypes.POINTER(CUstreamBatchMemOpParams), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuFuncGetAttribute(int *pi, CUfunction_attribute attrib, CUfunction hfunc) +try: (cuFuncGetAttribute:=dll.cuFuncGetAttribute).restype, cuFuncGetAttribute.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUfunction_attribute, CUfunction] +except AttributeError: pass + +# CUresult cuFuncSetAttribute(CUfunction hfunc, CUfunction_attribute attrib, int value) +try: (cuFuncSetAttribute:=dll.cuFuncSetAttribute).restype, cuFuncSetAttribute.argtypes = CUresult, [CUfunction, CUfunction_attribute, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuFuncSetCacheConfig(CUfunction hfunc, CUfunc_cache config) +try: (cuFuncSetCacheConfig:=dll.cuFuncSetCacheConfig).restype, cuFuncSetCacheConfig.argtypes = CUresult, [CUfunction, CUfunc_cache] +except AttributeError: pass + +# CUresult cuFuncSetSharedMemConfig(CUfunction hfunc, CUsharedconfig config) +try: (cuFuncSetSharedMemConfig:=dll.cuFuncSetSharedMemConfig).restype, cuFuncSetSharedMemConfig.argtypes = CUresult, [CUfunction, CUsharedconfig] +except AttributeError: pass + +# CUresult cuFuncGetModule(CUmodule *hmod, CUfunction hfunc) +try: (cuFuncGetModule:=dll.cuFuncGetModule).restype, cuFuncGetModule.argtypes = CUresult, [ctypes.POINTER(CUmodule), CUfunction] +except AttributeError: pass + +# CUresult cuLaunchKernel_ptsz(CUfunction f, unsigned int gridDimX, unsigned int gridDimY, unsigned int gridDimZ, unsigned int blockDimX, unsigned int blockDimY, unsigned int blockDimZ, unsigned int sharedMemBytes, CUstream hStream, void **kernelParams, void **extra) +try: (cuLaunchKernel_ptsz:=dll.cuLaunchKernel_ptsz).restype, cuLaunchKernel_ptsz.argtypes = CUresult, [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLaunchKernelEx_ptsz(const CUlaunchConfig *config, CUfunction f, void **kernelParams, void **extra) +try: (cuLaunchKernelEx_ptsz:=dll.cuLaunchKernelEx_ptsz).restype, cuLaunchKernelEx_ptsz.argtypes = CUresult, [ctypes.POINTER(CUlaunchConfig), CUfunction, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLaunchCooperativeKernel_ptsz(CUfunction f, unsigned int gridDimX, unsigned int gridDimY, unsigned int gridDimZ, unsigned int blockDimX, unsigned int blockDimY, unsigned int blockDimZ, unsigned int sharedMemBytes, CUstream hStream, void **kernelParams) +try: (cuLaunchCooperativeKernel_ptsz:=dll.cuLaunchCooperativeKernel_ptsz).restype, cuLaunchCooperativeKernel_ptsz.argtypes = CUresult, [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLaunchCooperativeKernelMultiDevice(CUDA_LAUNCH_PARAMS *launchParamsList, unsigned int numDevices, unsigned int flags) +try: (cuLaunchCooperativeKernelMultiDevice:=dll.cuLaunchCooperativeKernelMultiDevice).restype, cuLaunchCooperativeKernelMultiDevice.argtypes = CUresult, [ctypes.POINTER(CUDA_LAUNCH_PARAMS), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuLaunchHostFunc_ptsz(CUstream hStream, CUhostFn fn, void *userData) +try: (cuLaunchHostFunc_ptsz:=dll.cuLaunchHostFunc_ptsz).restype, cuLaunchHostFunc_ptsz.argtypes = CUresult, [CUstream, CUhostFn, ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuFuncSetBlockShape(CUfunction hfunc, int x, int y, int z) +try: (cuFuncSetBlockShape:=dll.cuFuncSetBlockShape).restype, cuFuncSetBlockShape.argtypes = CUresult, [CUfunction, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuFuncSetSharedSize(CUfunction hfunc, unsigned int bytes) +try: (cuFuncSetSharedSize:=dll.cuFuncSetSharedSize).restype, cuFuncSetSharedSize.argtypes = CUresult, [CUfunction, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuParamSetSize(CUfunction hfunc, unsigned int numbytes) +try: (cuParamSetSize:=dll.cuParamSetSize).restype, cuParamSetSize.argtypes = CUresult, [CUfunction, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuParamSeti(CUfunction hfunc, int offset, unsigned int value) +try: (cuParamSeti:=dll.cuParamSeti).restype, cuParamSeti.argtypes = CUresult, [CUfunction, ctypes.c_int32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuParamSetf(CUfunction hfunc, int offset, float value) +try: (cuParamSetf:=dll.cuParamSetf).restype, cuParamSetf.argtypes = CUresult, [CUfunction, ctypes.c_int32, ctypes.c_float] +except AttributeError: pass + +# CUresult cuParamSetv(CUfunction hfunc, int offset, void *ptr, unsigned int numbytes) +try: (cuParamSetv:=dll.cuParamSetv).restype, cuParamSetv.argtypes = CUresult, [CUfunction, ctypes.c_int32, ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuLaunch(CUfunction f) +try: (cuLaunch:=dll.cuLaunch).restype, cuLaunch.argtypes = CUresult, [CUfunction] +except AttributeError: pass + +# CUresult cuLaunchGrid(CUfunction f, int grid_width, int grid_height) +try: (cuLaunchGrid:=dll.cuLaunchGrid).restype, cuLaunchGrid.argtypes = CUresult, [CUfunction, ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuLaunchGridAsync(CUfunction f, int grid_width, int grid_height, CUstream hStream) +try: (cuLaunchGridAsync:=dll.cuLaunchGridAsync).restype, cuLaunchGridAsync.argtypes = CUresult, [CUfunction, ctypes.c_int32, ctypes.c_int32, CUstream] +except AttributeError: pass + +# CUresult cuParamSetTexRef(CUfunction hfunc, int texunit, CUtexref hTexRef) +try: (cuParamSetTexRef:=dll.cuParamSetTexRef).restype, cuParamSetTexRef.argtypes = CUresult, [CUfunction, ctypes.c_int32, CUtexref] +except AttributeError: pass + +# CUresult cuGraphCreate(CUgraph *phGraph, unsigned int flags) +try: (cuGraphCreate:=dll.cuGraphCreate).restype, cuGraphCreate.argtypes = CUresult, [ctypes.POINTER(CUgraph), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphAddKernelNode_v2(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_KERNEL_NODE_PARAMS *nodeParams) +try: (cuGraphAddKernelNode_v2:=dll.cuGraphAddKernelNode_v2).restype, cuGraphAddKernelNode_v2.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphKernelNodeGetParams_v2(CUgraphNode hNode, CUDA_KERNEL_NODE_PARAMS *nodeParams) +try: (cuGraphKernelNodeGetParams_v2:=dll.cuGraphKernelNodeGetParams_v2).restype, cuGraphKernelNodeGetParams_v2.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphKernelNodeSetParams_v2(CUgraphNode hNode, const CUDA_KERNEL_NODE_PARAMS *nodeParams) +try: (cuGraphKernelNodeSetParams_v2:=dll.cuGraphKernelNodeSetParams_v2).restype, cuGraphKernelNodeSetParams_v2.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddMemcpyNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_MEMCPY3D *copyParams, CUcontext ctx) +try: (cuGraphAddMemcpyNode:=dll.cuGraphAddMemcpyNode).restype, cuGraphAddMemcpyNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_MEMCPY3D), CUcontext] +except AttributeError: pass + +# CUresult cuGraphMemcpyNodeGetParams(CUgraphNode hNode, CUDA_MEMCPY3D *nodeParams) +try: (cuGraphMemcpyNodeGetParams:=dll.cuGraphMemcpyNodeGetParams).restype, cuGraphMemcpyNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_MEMCPY3D)] +except AttributeError: pass + +# CUresult cuGraphMemcpyNodeSetParams(CUgraphNode hNode, const CUDA_MEMCPY3D *nodeParams) +try: (cuGraphMemcpyNodeSetParams:=dll.cuGraphMemcpyNodeSetParams).restype, cuGraphMemcpyNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_MEMCPY3D)] +except AttributeError: pass + +# CUresult cuGraphAddMemsetNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_MEMSET_NODE_PARAMS *memsetParams, CUcontext ctx) +try: (cuGraphAddMemsetNode:=dll.cuGraphAddMemsetNode).restype, cuGraphAddMemsetNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_MEMSET_NODE_PARAMS), CUcontext] +except AttributeError: pass + +# CUresult cuGraphMemsetNodeGetParams(CUgraphNode hNode, CUDA_MEMSET_NODE_PARAMS *nodeParams) +try: (cuGraphMemsetNodeGetParams:=dll.cuGraphMemsetNodeGetParams).restype, cuGraphMemsetNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_MEMSET_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphMemsetNodeSetParams(CUgraphNode hNode, const CUDA_MEMSET_NODE_PARAMS *nodeParams) +try: (cuGraphMemsetNodeSetParams:=dll.cuGraphMemsetNodeSetParams).restype, cuGraphMemsetNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_MEMSET_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddHostNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_HOST_NODE_PARAMS *nodeParams) +try: (cuGraphAddHostNode:=dll.cuGraphAddHostNode).restype, cuGraphAddHostNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_HOST_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphHostNodeGetParams(CUgraphNode hNode, CUDA_HOST_NODE_PARAMS *nodeParams) +try: (cuGraphHostNodeGetParams:=dll.cuGraphHostNodeGetParams).restype, cuGraphHostNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_HOST_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphHostNodeSetParams(CUgraphNode hNode, const CUDA_HOST_NODE_PARAMS *nodeParams) +try: (cuGraphHostNodeSetParams:=dll.cuGraphHostNodeSetParams).restype, cuGraphHostNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_HOST_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddChildGraphNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, CUgraph childGraph) +try: (cuGraphAddChildGraphNode:=dll.cuGraphAddChildGraphNode).restype, cuGraphAddChildGraphNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, CUgraph] +except AttributeError: pass + +# CUresult cuGraphChildGraphNodeGetGraph(CUgraphNode hNode, CUgraph *phGraph) +try: (cuGraphChildGraphNodeGetGraph:=dll.cuGraphChildGraphNodeGetGraph).restype, cuGraphChildGraphNodeGetGraph.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUgraph)] +except AttributeError: pass + +# CUresult cuGraphAddEmptyNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies) +try: (cuGraphAddEmptyNode:=dll.cuGraphAddEmptyNode).restype, cuGraphAddEmptyNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t] +except AttributeError: pass + +# CUresult cuGraphAddEventRecordNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, CUevent event) +try: (cuGraphAddEventRecordNode:=dll.cuGraphAddEventRecordNode).restype, cuGraphAddEventRecordNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, CUevent] +except AttributeError: pass + +# CUresult cuGraphEventRecordNodeGetEvent(CUgraphNode hNode, CUevent *event_out) +try: (cuGraphEventRecordNodeGetEvent:=dll.cuGraphEventRecordNodeGetEvent).restype, cuGraphEventRecordNodeGetEvent.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUevent)] +except AttributeError: pass + +# CUresult cuGraphEventRecordNodeSetEvent(CUgraphNode hNode, CUevent event) +try: (cuGraphEventRecordNodeSetEvent:=dll.cuGraphEventRecordNodeSetEvent).restype, cuGraphEventRecordNodeSetEvent.argtypes = CUresult, [CUgraphNode, CUevent] +except AttributeError: pass + +# CUresult cuGraphAddEventWaitNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, CUevent event) +try: (cuGraphAddEventWaitNode:=dll.cuGraphAddEventWaitNode).restype, cuGraphAddEventWaitNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, CUevent] +except AttributeError: pass + +# CUresult cuGraphEventWaitNodeGetEvent(CUgraphNode hNode, CUevent *event_out) +try: (cuGraphEventWaitNodeGetEvent:=dll.cuGraphEventWaitNodeGetEvent).restype, cuGraphEventWaitNodeGetEvent.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUevent)] +except AttributeError: pass + +# CUresult cuGraphEventWaitNodeSetEvent(CUgraphNode hNode, CUevent event) +try: (cuGraphEventWaitNodeSetEvent:=dll.cuGraphEventWaitNodeSetEvent).restype, cuGraphEventWaitNodeSetEvent.argtypes = CUresult, [CUgraphNode, CUevent] +except AttributeError: pass + +# CUresult cuGraphAddExternalSemaphoresSignalNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_EXT_SEM_SIGNAL_NODE_PARAMS *nodeParams) +try: (cuGraphAddExternalSemaphoresSignalNode:=dll.cuGraphAddExternalSemaphoresSignalNode).restype, cuGraphAddExternalSemaphoresSignalNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_EXT_SEM_SIGNAL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExternalSemaphoresSignalNodeGetParams(CUgraphNode hNode, CUDA_EXT_SEM_SIGNAL_NODE_PARAMS *params_out) +try: (cuGraphExternalSemaphoresSignalNodeGetParams:=dll.cuGraphExternalSemaphoresSignalNodeGetParams).restype, cuGraphExternalSemaphoresSignalNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_EXT_SEM_SIGNAL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExternalSemaphoresSignalNodeSetParams(CUgraphNode hNode, const CUDA_EXT_SEM_SIGNAL_NODE_PARAMS *nodeParams) +try: (cuGraphExternalSemaphoresSignalNodeSetParams:=dll.cuGraphExternalSemaphoresSignalNodeSetParams).restype, cuGraphExternalSemaphoresSignalNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_EXT_SEM_SIGNAL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddExternalSemaphoresWaitNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_EXT_SEM_WAIT_NODE_PARAMS *nodeParams) +try: (cuGraphAddExternalSemaphoresWaitNode:=dll.cuGraphAddExternalSemaphoresWaitNode).restype, cuGraphAddExternalSemaphoresWaitNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_EXT_SEM_WAIT_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExternalSemaphoresWaitNodeGetParams(CUgraphNode hNode, CUDA_EXT_SEM_WAIT_NODE_PARAMS *params_out) +try: (cuGraphExternalSemaphoresWaitNodeGetParams:=dll.cuGraphExternalSemaphoresWaitNodeGetParams).restype, cuGraphExternalSemaphoresWaitNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_EXT_SEM_WAIT_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExternalSemaphoresWaitNodeSetParams(CUgraphNode hNode, const CUDA_EXT_SEM_WAIT_NODE_PARAMS *nodeParams) +try: (cuGraphExternalSemaphoresWaitNodeSetParams:=dll.cuGraphExternalSemaphoresWaitNodeSetParams).restype, cuGraphExternalSemaphoresWaitNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_EXT_SEM_WAIT_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddBatchMemOpNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_BATCH_MEM_OP_NODE_PARAMS *nodeParams) +try: (cuGraphAddBatchMemOpNode:=dll.cuGraphAddBatchMemOpNode).restype, cuGraphAddBatchMemOpNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_BATCH_MEM_OP_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphBatchMemOpNodeGetParams(CUgraphNode hNode, CUDA_BATCH_MEM_OP_NODE_PARAMS *nodeParams_out) +try: (cuGraphBatchMemOpNodeGetParams:=dll.cuGraphBatchMemOpNodeGetParams).restype, cuGraphBatchMemOpNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_BATCH_MEM_OP_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphBatchMemOpNodeSetParams(CUgraphNode hNode, const CUDA_BATCH_MEM_OP_NODE_PARAMS *nodeParams) +try: (cuGraphBatchMemOpNodeSetParams:=dll.cuGraphBatchMemOpNodeSetParams).restype, cuGraphBatchMemOpNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_BATCH_MEM_OP_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExecBatchMemOpNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_BATCH_MEM_OP_NODE_PARAMS *nodeParams) +try: (cuGraphExecBatchMemOpNodeSetParams:=dll.cuGraphExecBatchMemOpNodeSetParams).restype, cuGraphExecBatchMemOpNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_BATCH_MEM_OP_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddMemAllocNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, CUDA_MEM_ALLOC_NODE_PARAMS *nodeParams) +try: (cuGraphAddMemAllocNode:=dll.cuGraphAddMemAllocNode).restype, cuGraphAddMemAllocNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_MEM_ALLOC_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphMemAllocNodeGetParams(CUgraphNode hNode, CUDA_MEM_ALLOC_NODE_PARAMS *params_out) +try: (cuGraphMemAllocNodeGetParams:=dll.cuGraphMemAllocNodeGetParams).restype, cuGraphMemAllocNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_MEM_ALLOC_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphAddMemFreeNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, CUdeviceptr dptr) +try: (cuGraphAddMemFreeNode:=dll.cuGraphAddMemFreeNode).restype, cuGraphAddMemFreeNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, CUdeviceptr] +except AttributeError: pass + +# CUresult cuGraphMemFreeNodeGetParams(CUgraphNode hNode, CUdeviceptr *dptr_out) +try: (cuGraphMemFreeNodeGetParams:=dll.cuGraphMemFreeNodeGetParams).restype, cuGraphMemFreeNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUdeviceptr)] +except AttributeError: pass + +# CUresult cuDeviceGraphMemTrim(CUdevice device) +try: (cuDeviceGraphMemTrim:=dll.cuDeviceGraphMemTrim).restype, cuDeviceGraphMemTrim.argtypes = CUresult, [CUdevice] +except AttributeError: pass + +# CUresult cuDeviceGetGraphMemAttribute(CUdevice device, CUgraphMem_attribute attr, void *value) +try: (cuDeviceGetGraphMemAttribute:=dll.cuDeviceGetGraphMemAttribute).restype, cuDeviceGetGraphMemAttribute.argtypes = CUresult, [CUdevice, CUgraphMem_attribute, ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuDeviceSetGraphMemAttribute(CUdevice device, CUgraphMem_attribute attr, void *value) +try: (cuDeviceSetGraphMemAttribute:=dll.cuDeviceSetGraphMemAttribute).restype, cuDeviceSetGraphMemAttribute.argtypes = CUresult, [CUdevice, CUgraphMem_attribute, ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuGraphClone(CUgraph *phGraphClone, CUgraph originalGraph) +try: (cuGraphClone:=dll.cuGraphClone).restype, cuGraphClone.argtypes = CUresult, [ctypes.POINTER(CUgraph), CUgraph] +except AttributeError: pass + +# CUresult cuGraphNodeFindInClone(CUgraphNode *phNode, CUgraphNode hOriginalNode, CUgraph hClonedGraph) +try: (cuGraphNodeFindInClone:=dll.cuGraphNodeFindInClone).restype, cuGraphNodeFindInClone.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraphNode, CUgraph] +except AttributeError: pass + +# CUresult cuGraphNodeGetType(CUgraphNode hNode, CUgraphNodeType *type) +try: (cuGraphNodeGetType:=dll.cuGraphNodeGetType).restype, cuGraphNodeGetType.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUgraphNodeType)] +except AttributeError: pass + +# CUresult cuGraphGetNodes(CUgraph hGraph, CUgraphNode *nodes, size_t *numNodes) +try: (cuGraphGetNodes:=dll.cuGraphGetNodes).restype, cuGraphGetNodes.argtypes = CUresult, [CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuGraphGetRootNodes(CUgraph hGraph, CUgraphNode *rootNodes, size_t *numRootNodes) +try: (cuGraphGetRootNodes:=dll.cuGraphGetRootNodes).restype, cuGraphGetRootNodes.argtypes = CUresult, [CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuGraphGetEdges(CUgraph hGraph, CUgraphNode *from, CUgraphNode *to, size_t *numEdges) +try: (cuGraphGetEdges:=dll.cuGraphGetEdges).restype, cuGraphGetEdges.argtypes = CUresult, [CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(CUgraphNode), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuGraphNodeGetDependencies(CUgraphNode hNode, CUgraphNode *dependencies, size_t *numDependencies) +try: (cuGraphNodeGetDependencies:=dll.cuGraphNodeGetDependencies).restype, cuGraphNodeGetDependencies.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUgraphNode), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuGraphNodeGetDependentNodes(CUgraphNode hNode, CUgraphNode *dependentNodes, size_t *numDependentNodes) +try: (cuGraphNodeGetDependentNodes:=dll.cuGraphNodeGetDependentNodes).restype, cuGraphNodeGetDependentNodes.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUgraphNode), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuGraphAddDependencies(CUgraph hGraph, const CUgraphNode *from, const CUgraphNode *to, size_t numDependencies) +try: (cuGraphAddDependencies:=dll.cuGraphAddDependencies).restype, cuGraphAddDependencies.argtypes = CUresult, [CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(CUgraphNode), size_t] +except AttributeError: pass + +# CUresult cuGraphRemoveDependencies(CUgraph hGraph, const CUgraphNode *from, const CUgraphNode *to, size_t numDependencies) +try: (cuGraphRemoveDependencies:=dll.cuGraphRemoveDependencies).restype, cuGraphRemoveDependencies.argtypes = CUresult, [CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(CUgraphNode), size_t] +except AttributeError: pass + +# CUresult cuGraphDestroyNode(CUgraphNode hNode) +try: (cuGraphDestroyNode:=dll.cuGraphDestroyNode).restype, cuGraphDestroyNode.argtypes = CUresult, [CUgraphNode] +except AttributeError: pass + +# CUresult cuGraphInstantiateWithFlags(CUgraphExec *phGraphExec, CUgraph hGraph, unsigned long long flags) +try: (cuGraphInstantiateWithFlags:=dll.cuGraphInstantiateWithFlags).restype, cuGraphInstantiateWithFlags.argtypes = CUresult, [ctypes.POINTER(CUgraphExec), CUgraph, ctypes.c_uint64] +except AttributeError: pass + +# CUresult cuGraphInstantiateWithParams_ptsz(CUgraphExec *phGraphExec, CUgraph hGraph, CUDA_GRAPH_INSTANTIATE_PARAMS *instantiateParams) +try: (cuGraphInstantiateWithParams_ptsz:=dll.cuGraphInstantiateWithParams_ptsz).restype, cuGraphInstantiateWithParams_ptsz.argtypes = CUresult, [ctypes.POINTER(CUgraphExec), CUgraph, ctypes.POINTER(CUDA_GRAPH_INSTANTIATE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExecGetFlags(CUgraphExec hGraphExec, cuuint64_t *flags) +try: (cuGraphExecGetFlags:=dll.cuGraphExecGetFlags).restype, cuGraphExecGetFlags.argtypes = CUresult, [CUgraphExec, ctypes.POINTER(cuuint64_t)] +except AttributeError: pass + +# CUresult cuGraphExecKernelNodeSetParams_v2(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_KERNEL_NODE_PARAMS *nodeParams) +try: (cuGraphExecKernelNodeSetParams_v2:=dll.cuGraphExecKernelNodeSetParams_v2).restype, cuGraphExecKernelNodeSetParams_v2.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExecMemcpyNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_MEMCPY3D *copyParams, CUcontext ctx) +try: (cuGraphExecMemcpyNodeSetParams:=dll.cuGraphExecMemcpyNodeSetParams).restype, cuGraphExecMemcpyNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_MEMCPY3D), CUcontext] +except AttributeError: pass + +# CUresult cuGraphExecMemsetNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_MEMSET_NODE_PARAMS *memsetParams, CUcontext ctx) +try: (cuGraphExecMemsetNodeSetParams:=dll.cuGraphExecMemsetNodeSetParams).restype, cuGraphExecMemsetNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_MEMSET_NODE_PARAMS), CUcontext] +except AttributeError: pass + +# CUresult cuGraphExecHostNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_HOST_NODE_PARAMS *nodeParams) +try: (cuGraphExecHostNodeSetParams:=dll.cuGraphExecHostNodeSetParams).restype, cuGraphExecHostNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_HOST_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExecChildGraphNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, CUgraph childGraph) +try: (cuGraphExecChildGraphNodeSetParams:=dll.cuGraphExecChildGraphNodeSetParams).restype, cuGraphExecChildGraphNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, CUgraph] +except AttributeError: pass + +# CUresult cuGraphExecEventRecordNodeSetEvent(CUgraphExec hGraphExec, CUgraphNode hNode, CUevent event) +try: (cuGraphExecEventRecordNodeSetEvent:=dll.cuGraphExecEventRecordNodeSetEvent).restype, cuGraphExecEventRecordNodeSetEvent.argtypes = CUresult, [CUgraphExec, CUgraphNode, CUevent] +except AttributeError: pass + +# CUresult cuGraphExecEventWaitNodeSetEvent(CUgraphExec hGraphExec, CUgraphNode hNode, CUevent event) +try: (cuGraphExecEventWaitNodeSetEvent:=dll.cuGraphExecEventWaitNodeSetEvent).restype, cuGraphExecEventWaitNodeSetEvent.argtypes = CUresult, [CUgraphExec, CUgraphNode, CUevent] +except AttributeError: pass + +# CUresult cuGraphExecExternalSemaphoresSignalNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_EXT_SEM_SIGNAL_NODE_PARAMS *nodeParams) +try: (cuGraphExecExternalSemaphoresSignalNodeSetParams:=dll.cuGraphExecExternalSemaphoresSignalNodeSetParams).restype, cuGraphExecExternalSemaphoresSignalNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_EXT_SEM_SIGNAL_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExecExternalSemaphoresWaitNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_EXT_SEM_WAIT_NODE_PARAMS *nodeParams) +try: (cuGraphExecExternalSemaphoresWaitNodeSetParams:=dll.cuGraphExecExternalSemaphoresWaitNodeSetParams).restype, cuGraphExecExternalSemaphoresWaitNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_EXT_SEM_WAIT_NODE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphNodeSetEnabled(CUgraphExec hGraphExec, CUgraphNode hNode, unsigned int isEnabled) +try: (cuGraphNodeSetEnabled:=dll.cuGraphNodeSetEnabled).restype, cuGraphNodeSetEnabled.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphNodeGetEnabled(CUgraphExec hGraphExec, CUgraphNode hNode, unsigned int *isEnabled) +try: (cuGraphNodeGetEnabled:=dll.cuGraphNodeGetEnabled).restype, cuGraphNodeGetEnabled.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# CUresult cuGraphUpload_ptsz(CUgraphExec hGraphExec, CUstream hStream) +try: (cuGraphUpload_ptsz:=dll.cuGraphUpload_ptsz).restype, cuGraphUpload_ptsz.argtypes = CUresult, [CUgraphExec, CUstream] +except AttributeError: pass + +# CUresult cuGraphLaunch_ptsz(CUgraphExec hGraphExec, CUstream hStream) +try: (cuGraphLaunch_ptsz:=dll.cuGraphLaunch_ptsz).restype, cuGraphLaunch_ptsz.argtypes = CUresult, [CUgraphExec, CUstream] +except AttributeError: pass + +# CUresult cuGraphExecDestroy(CUgraphExec hGraphExec) +try: (cuGraphExecDestroy:=dll.cuGraphExecDestroy).restype, cuGraphExecDestroy.argtypes = CUresult, [CUgraphExec] +except AttributeError: pass + +# CUresult cuGraphDestroy(CUgraph hGraph) +try: (cuGraphDestroy:=dll.cuGraphDestroy).restype, cuGraphDestroy.argtypes = CUresult, [CUgraph] +except AttributeError: pass + +# CUresult cuGraphExecUpdate_v2(CUgraphExec hGraphExec, CUgraph hGraph, CUgraphExecUpdateResultInfo *resultInfo) +try: (cuGraphExecUpdate_v2:=dll.cuGraphExecUpdate_v2).restype, cuGraphExecUpdate_v2.argtypes = CUresult, [CUgraphExec, CUgraph, ctypes.POINTER(CUgraphExecUpdateResultInfo)] +except AttributeError: pass + +# CUresult cuGraphKernelNodeCopyAttributes(CUgraphNode dst, CUgraphNode src) +try: (cuGraphKernelNodeCopyAttributes:=dll.cuGraphKernelNodeCopyAttributes).restype, cuGraphKernelNodeCopyAttributes.argtypes = CUresult, [CUgraphNode, CUgraphNode] +except AttributeError: pass + +# CUresult cuGraphKernelNodeGetAttribute(CUgraphNode hNode, CUkernelNodeAttrID attr, CUkernelNodeAttrValue *value_out) +try: (cuGraphKernelNodeGetAttribute:=dll.cuGraphKernelNodeGetAttribute).restype, cuGraphKernelNodeGetAttribute.argtypes = CUresult, [CUgraphNode, CUkernelNodeAttrID, ctypes.POINTER(CUkernelNodeAttrValue)] +except AttributeError: pass + +# CUresult cuGraphKernelNodeSetAttribute(CUgraphNode hNode, CUkernelNodeAttrID attr, const CUkernelNodeAttrValue *value) +try: (cuGraphKernelNodeSetAttribute:=dll.cuGraphKernelNodeSetAttribute).restype, cuGraphKernelNodeSetAttribute.argtypes = CUresult, [CUgraphNode, CUkernelNodeAttrID, ctypes.POINTER(CUkernelNodeAttrValue)] +except AttributeError: pass + +# CUresult cuGraphDebugDotPrint(CUgraph hGraph, const char *path, unsigned int flags) +try: (cuGraphDebugDotPrint:=dll.cuGraphDebugDotPrint).restype, cuGraphDebugDotPrint.argtypes = CUresult, [CUgraph, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuUserObjectCreate(CUuserObject *object_out, void *ptr, CUhostFn destroy, unsigned int initialRefcount, unsigned int flags) +try: (cuUserObjectCreate:=dll.cuUserObjectCreate).restype, cuUserObjectCreate.argtypes = CUresult, [ctypes.POINTER(CUuserObject), ctypes.c_void_p, CUhostFn, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuUserObjectRetain(CUuserObject object, unsigned int count) +try: (cuUserObjectRetain:=dll.cuUserObjectRetain).restype, cuUserObjectRetain.argtypes = CUresult, [CUuserObject, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuUserObjectRelease(CUuserObject object, unsigned int count) +try: (cuUserObjectRelease:=dll.cuUserObjectRelease).restype, cuUserObjectRelease.argtypes = CUresult, [CUuserObject, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphRetainUserObject(CUgraph graph, CUuserObject object, unsigned int count, unsigned int flags) +try: (cuGraphRetainUserObject:=dll.cuGraphRetainUserObject).restype, cuGraphRetainUserObject.argtypes = CUresult, [CUgraph, CUuserObject, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphReleaseUserObject(CUgraph graph, CUuserObject object, unsigned int count) +try: (cuGraphReleaseUserObject:=dll.cuGraphReleaseUserObject).restype, cuGraphReleaseUserObject.argtypes = CUresult, [CUgraph, CUuserObject, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuOccupancyMaxActiveBlocksPerMultiprocessor(int *numBlocks, CUfunction func, int blockSize, size_t dynamicSMemSize) +try: (cuOccupancyMaxActiveBlocksPerMultiprocessor:=dll.cuOccupancyMaxActiveBlocksPerMultiprocessor).restype, cuOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.c_int32, size_t] +except AttributeError: pass + +# CUresult cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags(int *numBlocks, CUfunction func, int blockSize, size_t dynamicSMemSize, unsigned int flags) +try: (cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags:=dll.cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags).restype, cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.c_int32, size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuOccupancyMaxPotentialBlockSize(int *minGridSize, int *blockSize, CUfunction func, CUoccupancyB2DSize blockSizeToDynamicSMemSize, size_t dynamicSMemSize, int blockSizeLimit) +try: (cuOccupancyMaxPotentialBlockSize:=dll.cuOccupancyMaxPotentialBlockSize).restype, cuOccupancyMaxPotentialBlockSize.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUfunction, CUoccupancyB2DSize, size_t, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuOccupancyMaxPotentialBlockSizeWithFlags(int *minGridSize, int *blockSize, CUfunction func, CUoccupancyB2DSize blockSizeToDynamicSMemSize, size_t dynamicSMemSize, int blockSizeLimit, unsigned int flags) +try: (cuOccupancyMaxPotentialBlockSizeWithFlags:=dll.cuOccupancyMaxPotentialBlockSizeWithFlags).restype, cuOccupancyMaxPotentialBlockSizeWithFlags.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUfunction, CUoccupancyB2DSize, size_t, ctypes.c_int32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuOccupancyAvailableDynamicSMemPerBlock(size_t *dynamicSmemSize, CUfunction func, int numBlocks, int blockSize) +try: (cuOccupancyAvailableDynamicSMemPerBlock:=dll.cuOccupancyAvailableDynamicSMemPerBlock).restype, cuOccupancyAvailableDynamicSMemPerBlock.argtypes = CUresult, [ctypes.POINTER(size_t), CUfunction, ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuOccupancyMaxPotentialClusterSize(int *clusterSize, CUfunction func, const CUlaunchConfig *config) +try: (cuOccupancyMaxPotentialClusterSize:=dll.cuOccupancyMaxPotentialClusterSize).restype, cuOccupancyMaxPotentialClusterSize.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.POINTER(CUlaunchConfig)] +except AttributeError: pass + +# CUresult cuOccupancyMaxActiveClusters(int *numClusters, CUfunction func, const CUlaunchConfig *config) +try: (cuOccupancyMaxActiveClusters:=dll.cuOccupancyMaxActiveClusters).restype, cuOccupancyMaxActiveClusters.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.POINTER(CUlaunchConfig)] +except AttributeError: pass + +# CUresult cuTexRefSetArray(CUtexref hTexRef, CUarray hArray, unsigned int Flags) +try: (cuTexRefSetArray:=dll.cuTexRefSetArray).restype, cuTexRefSetArray.argtypes = CUresult, [CUtexref, CUarray, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuTexRefSetMipmappedArray(CUtexref hTexRef, CUmipmappedArray hMipmappedArray, unsigned int Flags) +try: (cuTexRefSetMipmappedArray:=dll.cuTexRefSetMipmappedArray).restype, cuTexRefSetMipmappedArray.argtypes = CUresult, [CUtexref, CUmipmappedArray, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuTexRefSetAddress_v2(size_t *ByteOffset, CUtexref hTexRef, CUdeviceptr dptr, size_t bytes) +try: (cuTexRefSetAddress_v2:=dll.cuTexRefSetAddress_v2).restype, cuTexRefSetAddress_v2.argtypes = CUresult, [ctypes.POINTER(size_t), CUtexref, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuTexRefSetAddress2D_v3(CUtexref hTexRef, const CUDA_ARRAY_DESCRIPTOR *desc, CUdeviceptr dptr, size_t Pitch) +try: (cuTexRefSetAddress2D_v3:=dll.cuTexRefSetAddress2D_v3).restype, cuTexRefSetAddress2D_v3.argtypes = CUresult, [CUtexref, ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR), CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuTexRefSetFormat(CUtexref hTexRef, CUarray_format fmt, int NumPackedComponents) +try: (cuTexRefSetFormat:=dll.cuTexRefSetFormat).restype, cuTexRefSetFormat.argtypes = CUresult, [CUtexref, CUarray_format, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuTexRefSetAddressMode(CUtexref hTexRef, int dim, CUaddress_mode am) +try: (cuTexRefSetAddressMode:=dll.cuTexRefSetAddressMode).restype, cuTexRefSetAddressMode.argtypes = CUresult, [CUtexref, ctypes.c_int32, CUaddress_mode] +except AttributeError: pass + +# CUresult cuTexRefSetFilterMode(CUtexref hTexRef, CUfilter_mode fm) +try: (cuTexRefSetFilterMode:=dll.cuTexRefSetFilterMode).restype, cuTexRefSetFilterMode.argtypes = CUresult, [CUtexref, CUfilter_mode] +except AttributeError: pass + +# CUresult cuTexRefSetMipmapFilterMode(CUtexref hTexRef, CUfilter_mode fm) +try: (cuTexRefSetMipmapFilterMode:=dll.cuTexRefSetMipmapFilterMode).restype, cuTexRefSetMipmapFilterMode.argtypes = CUresult, [CUtexref, CUfilter_mode] +except AttributeError: pass + +# CUresult cuTexRefSetMipmapLevelBias(CUtexref hTexRef, float bias) +try: (cuTexRefSetMipmapLevelBias:=dll.cuTexRefSetMipmapLevelBias).restype, cuTexRefSetMipmapLevelBias.argtypes = CUresult, [CUtexref, ctypes.c_float] +except AttributeError: pass + +# CUresult cuTexRefSetMipmapLevelClamp(CUtexref hTexRef, float minMipmapLevelClamp, float maxMipmapLevelClamp) +try: (cuTexRefSetMipmapLevelClamp:=dll.cuTexRefSetMipmapLevelClamp).restype, cuTexRefSetMipmapLevelClamp.argtypes = CUresult, [CUtexref, ctypes.c_float, ctypes.c_float] +except AttributeError: pass + +# CUresult cuTexRefSetMaxAnisotropy(CUtexref hTexRef, unsigned int maxAniso) +try: (cuTexRefSetMaxAnisotropy:=dll.cuTexRefSetMaxAnisotropy).restype, cuTexRefSetMaxAnisotropy.argtypes = CUresult, [CUtexref, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuTexRefSetBorderColor(CUtexref hTexRef, float *pBorderColor) +try: (cuTexRefSetBorderColor:=dll.cuTexRefSetBorderColor).restype, cuTexRefSetBorderColor.argtypes = CUresult, [CUtexref, ctypes.POINTER(ctypes.c_float)] +except AttributeError: pass + +# CUresult cuTexRefSetFlags(CUtexref hTexRef, unsigned int Flags) +try: (cuTexRefSetFlags:=dll.cuTexRefSetFlags).restype, cuTexRefSetFlags.argtypes = CUresult, [CUtexref, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuTexRefGetAddress_v2(CUdeviceptr *pdptr, CUtexref hTexRef) +try: (cuTexRefGetAddress_v2:=dll.cuTexRefGetAddress_v2).restype, cuTexRefGetAddress_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetArray(CUarray *phArray, CUtexref hTexRef) +try: (cuTexRefGetArray:=dll.cuTexRefGetArray).restype, cuTexRefGetArray.argtypes = CUresult, [ctypes.POINTER(CUarray), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetMipmappedArray(CUmipmappedArray *phMipmappedArray, CUtexref hTexRef) +try: (cuTexRefGetMipmappedArray:=dll.cuTexRefGetMipmappedArray).restype, cuTexRefGetMipmappedArray.argtypes = CUresult, [ctypes.POINTER(CUmipmappedArray), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetAddressMode(CUaddress_mode *pam, CUtexref hTexRef, int dim) +try: (cuTexRefGetAddressMode:=dll.cuTexRefGetAddressMode).restype, cuTexRefGetAddressMode.argtypes = CUresult, [ctypes.POINTER(CUaddress_mode), CUtexref, ctypes.c_int32] +except AttributeError: pass + +# CUresult cuTexRefGetFilterMode(CUfilter_mode *pfm, CUtexref hTexRef) +try: (cuTexRefGetFilterMode:=dll.cuTexRefGetFilterMode).restype, cuTexRefGetFilterMode.argtypes = CUresult, [ctypes.POINTER(CUfilter_mode), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetFormat(CUarray_format *pFormat, int *pNumChannels, CUtexref hTexRef) +try: (cuTexRefGetFormat:=dll.cuTexRefGetFormat).restype, cuTexRefGetFormat.argtypes = CUresult, [ctypes.POINTER(CUarray_format), ctypes.POINTER(ctypes.c_int32), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetMipmapFilterMode(CUfilter_mode *pfm, CUtexref hTexRef) +try: (cuTexRefGetMipmapFilterMode:=dll.cuTexRefGetMipmapFilterMode).restype, cuTexRefGetMipmapFilterMode.argtypes = CUresult, [ctypes.POINTER(CUfilter_mode), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetMipmapLevelBias(float *pbias, CUtexref hTexRef) +try: (cuTexRefGetMipmapLevelBias:=dll.cuTexRefGetMipmapLevelBias).restype, cuTexRefGetMipmapLevelBias.argtypes = CUresult, [ctypes.POINTER(ctypes.c_float), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetMipmapLevelClamp(float *pminMipmapLevelClamp, float *pmaxMipmapLevelClamp, CUtexref hTexRef) +try: (cuTexRefGetMipmapLevelClamp:=dll.cuTexRefGetMipmapLevelClamp).restype, cuTexRefGetMipmapLevelClamp.argtypes = CUresult, [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(ctypes.c_float), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetMaxAnisotropy(int *pmaxAniso, CUtexref hTexRef) +try: (cuTexRefGetMaxAnisotropy:=dll.cuTexRefGetMaxAnisotropy).restype, cuTexRefGetMaxAnisotropy.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetBorderColor(float *pBorderColor, CUtexref hTexRef) +try: (cuTexRefGetBorderColor:=dll.cuTexRefGetBorderColor).restype, cuTexRefGetBorderColor.argtypes = CUresult, [ctypes.POINTER(ctypes.c_float), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefGetFlags(unsigned int *pFlags, CUtexref hTexRef) +try: (cuTexRefGetFlags:=dll.cuTexRefGetFlags).restype, cuTexRefGetFlags.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint32), CUtexref] +except AttributeError: pass + +# CUresult cuTexRefCreate(CUtexref *pTexRef) +try: (cuTexRefCreate:=dll.cuTexRefCreate).restype, cuTexRefCreate.argtypes = CUresult, [ctypes.POINTER(CUtexref)] +except AttributeError: pass + +# CUresult cuTexRefDestroy(CUtexref hTexRef) +try: (cuTexRefDestroy:=dll.cuTexRefDestroy).restype, cuTexRefDestroy.argtypes = CUresult, [CUtexref] +except AttributeError: pass + +# CUresult cuSurfRefSetArray(CUsurfref hSurfRef, CUarray hArray, unsigned int Flags) +try: (cuSurfRefSetArray:=dll.cuSurfRefSetArray).restype, cuSurfRefSetArray.argtypes = CUresult, [CUsurfref, CUarray, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuSurfRefGetArray(CUarray *phArray, CUsurfref hSurfRef) +try: (cuSurfRefGetArray:=dll.cuSurfRefGetArray).restype, cuSurfRefGetArray.argtypes = CUresult, [ctypes.POINTER(CUarray), CUsurfref] +except AttributeError: pass + +# CUresult cuTexObjectCreate(CUtexObject *pTexObject, const CUDA_RESOURCE_DESC *pResDesc, const CUDA_TEXTURE_DESC *pTexDesc, const CUDA_RESOURCE_VIEW_DESC *pResViewDesc) +try: (cuTexObjectCreate:=dll.cuTexObjectCreate).restype, cuTexObjectCreate.argtypes = CUresult, [ctypes.POINTER(CUtexObject), ctypes.POINTER(CUDA_RESOURCE_DESC), ctypes.POINTER(CUDA_TEXTURE_DESC), ctypes.POINTER(CUDA_RESOURCE_VIEW_DESC)] +except AttributeError: pass + +# CUresult cuTexObjectDestroy(CUtexObject texObject) +try: (cuTexObjectDestroy:=dll.cuTexObjectDestroy).restype, cuTexObjectDestroy.argtypes = CUresult, [CUtexObject] +except AttributeError: pass + +# CUresult cuTexObjectGetResourceDesc(CUDA_RESOURCE_DESC *pResDesc, CUtexObject texObject) +try: (cuTexObjectGetResourceDesc:=dll.cuTexObjectGetResourceDesc).restype, cuTexObjectGetResourceDesc.argtypes = CUresult, [ctypes.POINTER(CUDA_RESOURCE_DESC), CUtexObject] +except AttributeError: pass + +# CUresult cuTexObjectGetTextureDesc(CUDA_TEXTURE_DESC *pTexDesc, CUtexObject texObject) +try: (cuTexObjectGetTextureDesc:=dll.cuTexObjectGetTextureDesc).restype, cuTexObjectGetTextureDesc.argtypes = CUresult, [ctypes.POINTER(CUDA_TEXTURE_DESC), CUtexObject] +except AttributeError: pass + +# CUresult cuTexObjectGetResourceViewDesc(CUDA_RESOURCE_VIEW_DESC *pResViewDesc, CUtexObject texObject) +try: (cuTexObjectGetResourceViewDesc:=dll.cuTexObjectGetResourceViewDesc).restype, cuTexObjectGetResourceViewDesc.argtypes = CUresult, [ctypes.POINTER(CUDA_RESOURCE_VIEW_DESC), CUtexObject] +except AttributeError: pass + +# CUresult cuSurfObjectCreate(CUsurfObject *pSurfObject, const CUDA_RESOURCE_DESC *pResDesc) +try: (cuSurfObjectCreate:=dll.cuSurfObjectCreate).restype, cuSurfObjectCreate.argtypes = CUresult, [ctypes.POINTER(CUsurfObject), ctypes.POINTER(CUDA_RESOURCE_DESC)] +except AttributeError: pass + +# CUresult cuSurfObjectDestroy(CUsurfObject surfObject) +try: (cuSurfObjectDestroy:=dll.cuSurfObjectDestroy).restype, cuSurfObjectDestroy.argtypes = CUresult, [CUsurfObject] +except AttributeError: pass + +# CUresult cuSurfObjectGetResourceDesc(CUDA_RESOURCE_DESC *pResDesc, CUsurfObject surfObject) +try: (cuSurfObjectGetResourceDesc:=dll.cuSurfObjectGetResourceDesc).restype, cuSurfObjectGetResourceDesc.argtypes = CUresult, [ctypes.POINTER(CUDA_RESOURCE_DESC), CUsurfObject] +except AttributeError: pass + +# CUresult cuTensorMapEncodeTiled(CUtensorMap *tensorMap, CUtensorMapDataType tensorDataType, cuuint32_t tensorRank, void *globalAddress, const cuuint64_t *globalDim, const cuuint64_t *globalStrides, const cuuint32_t *boxDim, const cuuint32_t *elementStrides, CUtensorMapInterleave interleave, CUtensorMapSwizzle swizzle, CUtensorMapL2promotion l2Promotion, CUtensorMapFloatOOBfill oobFill) +try: (cuTensorMapEncodeTiled:=dll.cuTensorMapEncodeTiled).restype, cuTensorMapEncodeTiled.argtypes = CUresult, [ctypes.POINTER(CUtensorMap), CUtensorMapDataType, cuuint32_t, ctypes.c_void_p, ctypes.POINTER(cuuint64_t), ctypes.POINTER(cuuint64_t), ctypes.POINTER(cuuint32_t), ctypes.POINTER(cuuint32_t), CUtensorMapInterleave, CUtensorMapSwizzle, CUtensorMapL2promotion, CUtensorMapFloatOOBfill] +except AttributeError: pass + +# CUresult cuTensorMapEncodeIm2col(CUtensorMap *tensorMap, CUtensorMapDataType tensorDataType, cuuint32_t tensorRank, void *globalAddress, const cuuint64_t *globalDim, const cuuint64_t *globalStrides, const int *pixelBoxLowerCorner, const int *pixelBoxUpperCorner, cuuint32_t channelsPerPixel, cuuint32_t pixelsPerColumn, const cuuint32_t *elementStrides, CUtensorMapInterleave interleave, CUtensorMapSwizzle swizzle, CUtensorMapL2promotion l2Promotion, CUtensorMapFloatOOBfill oobFill) +try: (cuTensorMapEncodeIm2col:=dll.cuTensorMapEncodeIm2col).restype, cuTensorMapEncodeIm2col.argtypes = CUresult, [ctypes.POINTER(CUtensorMap), CUtensorMapDataType, cuuint32_t, ctypes.c_void_p, ctypes.POINTER(cuuint64_t), ctypes.POINTER(cuuint64_t), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), cuuint32_t, cuuint32_t, ctypes.POINTER(cuuint32_t), CUtensorMapInterleave, CUtensorMapSwizzle, CUtensorMapL2promotion, CUtensorMapFloatOOBfill] +except AttributeError: pass + +# CUresult cuTensorMapReplaceAddress(CUtensorMap *tensorMap, void *globalAddress) +try: (cuTensorMapReplaceAddress:=dll.cuTensorMapReplaceAddress).restype, cuTensorMapReplaceAddress.argtypes = CUresult, [ctypes.POINTER(CUtensorMap), ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuDeviceCanAccessPeer(int *canAccessPeer, CUdevice dev, CUdevice peerDev) +try: (cuDeviceCanAccessPeer:=dll.cuDeviceCanAccessPeer).restype, cuDeviceCanAccessPeer.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUdevice, CUdevice] +except AttributeError: pass + +# CUresult cuCtxEnablePeerAccess(CUcontext peerContext, unsigned int Flags) +try: (cuCtxEnablePeerAccess:=dll.cuCtxEnablePeerAccess).restype, cuCtxEnablePeerAccess.argtypes = CUresult, [CUcontext, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuCtxDisablePeerAccess(CUcontext peerContext) +try: (cuCtxDisablePeerAccess:=dll.cuCtxDisablePeerAccess).restype, cuCtxDisablePeerAccess.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuDeviceGetP2PAttribute(int *value, CUdevice_P2PAttribute attrib, CUdevice srcDevice, CUdevice dstDevice) +try: (cuDeviceGetP2PAttribute:=dll.cuDeviceGetP2PAttribute).restype, cuDeviceGetP2PAttribute.argtypes = CUresult, [ctypes.POINTER(ctypes.c_int32), CUdevice_P2PAttribute, CUdevice, CUdevice] +except AttributeError: pass + +# CUresult cuGraphicsUnregisterResource(CUgraphicsResource resource) +try: (cuGraphicsUnregisterResource:=dll.cuGraphicsUnregisterResource).restype, cuGraphicsUnregisterResource.argtypes = CUresult, [CUgraphicsResource] +except AttributeError: pass + +# CUresult cuGraphicsSubResourceGetMappedArray(CUarray *pArray, CUgraphicsResource resource, unsigned int arrayIndex, unsigned int mipLevel) +try: (cuGraphicsSubResourceGetMappedArray:=dll.cuGraphicsSubResourceGetMappedArray).restype, cuGraphicsSubResourceGetMappedArray.argtypes = CUresult, [ctypes.POINTER(CUarray), CUgraphicsResource, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphicsResourceGetMappedMipmappedArray(CUmipmappedArray *pMipmappedArray, CUgraphicsResource resource) +try: (cuGraphicsResourceGetMappedMipmappedArray:=dll.cuGraphicsResourceGetMappedMipmappedArray).restype, cuGraphicsResourceGetMappedMipmappedArray.argtypes = CUresult, [ctypes.POINTER(CUmipmappedArray), CUgraphicsResource] +except AttributeError: pass + +# CUresult cuGraphicsResourceGetMappedPointer_v2(CUdeviceptr *pDevPtr, size_t *pSize, CUgraphicsResource resource) +try: (cuGraphicsResourceGetMappedPointer_v2:=dll.cuGraphicsResourceGetMappedPointer_v2).restype, cuGraphicsResourceGetMappedPointer_v2.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), ctypes.POINTER(size_t), CUgraphicsResource] +except AttributeError: pass + +# CUresult cuGraphicsResourceSetMapFlags_v2(CUgraphicsResource resource, unsigned int flags) +try: (cuGraphicsResourceSetMapFlags_v2:=dll.cuGraphicsResourceSetMapFlags_v2).restype, cuGraphicsResourceSetMapFlags_v2.argtypes = CUresult, [CUgraphicsResource, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphicsMapResources_ptsz(unsigned int count, CUgraphicsResource *resources, CUstream hStream) +try: (cuGraphicsMapResources_ptsz:=dll.cuGraphicsMapResources_ptsz).restype, cuGraphicsMapResources_ptsz.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUgraphicsResource), CUstream] +except AttributeError: pass + +# CUresult cuGraphicsUnmapResources_ptsz(unsigned int count, CUgraphicsResource *resources, CUstream hStream) +try: (cuGraphicsUnmapResources_ptsz:=dll.cuGraphicsUnmapResources_ptsz).restype, cuGraphicsUnmapResources_ptsz.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUgraphicsResource), CUstream] +except AttributeError: pass + +# CUresult cuGetProcAddress_v2(const char *symbol, void **pfn, int cudaVersion, cuuint64_t flags, CUdriverProcAddressQueryResult *symbolStatus) +try: (cuGetProcAddress_v2:=dll.cuGetProcAddress_v2).restype, cuGetProcAddress_v2.argtypes = CUresult, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_void_p), ctypes.c_int32, cuuint64_t, ctypes.POINTER(CUdriverProcAddressQueryResult)] +except AttributeError: pass + +# CUresult cuGetExportTable(const void **ppExportTable, const CUuuid *pExportTableId) +try: (cuGetExportTable:=dll.cuGetExportTable).restype, cuGetExportTable.argtypes = CUresult, [ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(CUuuid)] +except AttributeError: pass + +# CUresult cuMemHostRegister(void *p, size_t bytesize, unsigned int Flags) +try: (cuMemHostRegister:=dll.cuMemHostRegister).restype, cuMemHostRegister.argtypes = CUresult, [ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphicsResourceSetMapFlags(CUgraphicsResource resource, unsigned int flags) +try: (cuGraphicsResourceSetMapFlags:=dll.cuGraphicsResourceSetMapFlags).restype, cuGraphicsResourceSetMapFlags.argtypes = CUresult, [CUgraphicsResource, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuLinkCreate(unsigned int numOptions, CUjit_option *options, void **optionValues, CUlinkState *stateOut) +try: (cuLinkCreate:=dll.cuLinkCreate).restype, cuLinkCreate.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(CUlinkState)] +except AttributeError: pass + +# CUresult cuLinkAddData(CUlinkState state, CUjitInputType type, void *data, size_t size, const char *name, unsigned int numOptions, CUjit_option *options, void **optionValues) +try: (cuLinkAddData:=dll.cuLinkAddData).restype, cuLinkAddData.argtypes = CUresult, [CUlinkState, CUjitInputType, ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLinkAddFile(CUlinkState state, CUjitInputType type, const char *path, unsigned int numOptions, CUjit_option *options, void **optionValues) +try: (cuLinkAddFile:=dll.cuLinkAddFile).restype, cuLinkAddFile.argtypes = CUresult, [CUlinkState, CUjitInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuTexRefSetAddress2D_v2(CUtexref hTexRef, const CUDA_ARRAY_DESCRIPTOR *desc, CUdeviceptr dptr, size_t Pitch) +try: (cuTexRefSetAddress2D_v2:=dll.cuTexRefSetAddress2D_v2).restype, cuTexRefSetAddress2D_v2.argtypes = CUresult, [CUtexref, ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR), CUdeviceptr, size_t] +except AttributeError: pass -# values for enumeration 'CUmoduleLoadingMode_enum' -CUmoduleLoadingMode_enum__enumvalues = { - 1: 'CU_MODULE_EAGER_LOADING', - 2: 'CU_MODULE_LAZY_LOADING', -} -CU_MODULE_EAGER_LOADING = 1 -CU_MODULE_LAZY_LOADING = 2 -CUmoduleLoadingMode_enum = ctypes.c_uint32 # enum -CUmoduleLoadingMode = CUmoduleLoadingMode_enum -CUmoduleLoadingMode__enumvalues = CUmoduleLoadingMode_enum__enumvalues -try: - cuModuleGetLoadingMode = _libraries['libcuda.so'].cuModuleGetLoadingMode - cuModuleGetLoadingMode.restype = CUresult - cuModuleGetLoadingMode.argtypes = [ctypes.POINTER(CUmoduleLoadingMode_enum)] -except AttributeError: - pass -try: - cuModuleGetFunction = _libraries['libcuda.so'].cuModuleGetFunction - cuModuleGetFunction.restype = CUresult - cuModuleGetFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUfunc_st)), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuModuleGetGlobal_v2 = _libraries['libcuda.so'].cuModuleGetGlobal_v2 - cuModuleGetGlobal_v2.restype = CUresult - cuModuleGetGlobal_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLinkCreate_v2 = _libraries['libcuda.so'].cuLinkCreate_v2 - cuLinkCreate_v2.restype = CUresult - cuLinkCreate_v2.argtypes = [ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(struct_CUlinkState_st))] -except AttributeError: - pass -try: - cuLinkAddData_v2 = _libraries['libcuda.so'].cuLinkAddData_v2 - cuLinkAddData_v2.restype = CUresult - cuLinkAddData_v2.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLinkAddFile_v2 = _libraries['libcuda.so'].cuLinkAddFile_v2 - cuLinkAddFile_v2.restype = CUresult - cuLinkAddFile_v2.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLinkComplete = _libraries['libcuda.so'].cuLinkComplete - cuLinkComplete.restype = CUresult - cuLinkComplete.argtypes = [CUlinkState, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuLinkDestroy = _libraries['libcuda.so'].cuLinkDestroy - cuLinkDestroy.restype = CUresult - cuLinkDestroy.argtypes = [CUlinkState] -except AttributeError: - pass -try: - cuModuleGetTexRef = _libraries['libcuda.so'].cuModuleGetTexRef - cuModuleGetTexRef.restype = CUresult - cuModuleGetTexRef.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUtexref_st)), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuModuleGetSurfRef = _libraries['libcuda.so'].cuModuleGetSurfRef - cuModuleGetSurfRef.restype = CUresult - cuModuleGetSurfRef.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUsurfref_st)), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryLoadData = _libraries['libcuda.so'].cuLibraryLoadData - cuLibraryLoadData.restype = CUresult - cuLibraryLoadData.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUlib_st)), ctypes.POINTER(None), ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32, ctypes.POINTER(CUlibraryOption_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuLibraryLoadFromFile = _libraries['libcuda.so'].cuLibraryLoadFromFile - cuLibraryLoadFromFile.restype = CUresult - cuLibraryLoadFromFile.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUlib_st)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32, ctypes.POINTER(CUlibraryOption_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuLibraryUnload = _libraries['libcuda.so'].cuLibraryUnload - cuLibraryUnload.restype = CUresult - cuLibraryUnload.argtypes = [CUlibrary] -except AttributeError: - pass -try: - cuLibraryGetKernel = _libraries['libcuda.so'].cuLibraryGetKernel - cuLibraryGetKernel.restype = CUresult - cuLibraryGetKernel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUkern_st)), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryGetModule = _libraries['libcuda.so'].cuLibraryGetModule - cuLibraryGetModule.restype = CUresult - cuLibraryGetModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), CUlibrary] -except AttributeError: - pass -try: - cuKernelGetFunction = _libraries['libcuda.so'].cuKernelGetFunction - cuKernelGetFunction.restype = CUresult - cuKernelGetFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUfunc_st)), CUkernel] -except AttributeError: - pass -try: - cuLibraryGetGlobal = _libraries['libcuda.so'].cuLibraryGetGlobal - cuLibraryGetGlobal.restype = CUresult - cuLibraryGetGlobal.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryGetManaged = _libraries['libcuda.so'].cuLibraryGetManaged - cuLibraryGetManaged.restype = CUresult - cuLibraryGetManaged.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuLibraryGetUnifiedFunction = _libraries['libcuda.so'].cuLibraryGetUnifiedFunction - cuLibraryGetUnifiedFunction.restype = CUresult - cuLibraryGetUnifiedFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), CUlibrary, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuKernelGetAttribute = _libraries['libcuda.so'].cuKernelGetAttribute - cuKernelGetAttribute.restype = CUresult - cuKernelGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction_attribute, CUkernel, CUdevice] -except AttributeError: - pass -try: - cuKernelSetAttribute = _libraries['libcuda.so'].cuKernelSetAttribute - cuKernelSetAttribute.restype = CUresult - cuKernelSetAttribute.argtypes = [CUfunction_attribute, ctypes.c_int32, CUkernel, CUdevice] -except AttributeError: - pass -try: - cuKernelSetCacheConfig = _libraries['libcuda.so'].cuKernelSetCacheConfig - cuKernelSetCacheConfig.restype = CUresult - cuKernelSetCacheConfig.argtypes = [CUkernel, CUfunc_cache, CUdevice] -except AttributeError: - pass -try: - cuMemGetInfo_v2 = _libraries['libcuda.so'].cuMemGetInfo_v2 - cuMemGetInfo_v2.restype = CUresult - cuMemGetInfo_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuMemAlloc_v2 = _libraries['libcuda.so'].cuMemAlloc_v2 - cuMemAlloc_v2.restype = CUresult - cuMemAlloc_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t] -except AttributeError: - pass -try: - cuMemAllocPitch_v2 = _libraries['libcuda.so'].cuMemAllocPitch_v2 - cuMemAllocPitch_v2.restype = CUresult - cuMemAllocPitch_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemFree_v2 = _libraries['libcuda.so'].cuMemFree_v2 - cuMemFree_v2.restype = CUresult - cuMemFree_v2.argtypes = [CUdeviceptr] -except AttributeError: - pass -try: - cuMemGetAddressRange_v2 = _libraries['libcuda.so'].cuMemGetAddressRange_v2 - cuMemGetAddressRange_v2.restype = CUresult - cuMemGetAddressRange_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUdeviceptr] -except AttributeError: - pass -try: - cuMemAllocHost_v2 = _libraries['libcuda.so'].cuMemAllocHost_v2 - cuMemAllocHost_v2.restype = CUresult - cuMemAllocHost_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - cuMemFreeHost = _libraries['libcuda.so'].cuMemFreeHost - cuMemFreeHost.restype = CUresult - cuMemFreeHost.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemHostAlloc = _libraries['libcuda.so'].cuMemHostAlloc - cuMemHostAlloc.restype = CUresult - cuMemHostAlloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostGetDevicePointer_v2 = _libraries['libcuda.so'].cuMemHostGetDevicePointer_v2 - cuMemHostGetDevicePointer_v2.restype = CUresult - cuMemHostGetDevicePointer_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostGetFlags = _libraries['libcuda.so'].cuMemHostGetFlags - cuMemHostGetFlags.restype = CUresult - cuMemHostGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemAllocManaged = _libraries['libcuda.so'].cuMemAllocManaged - cuMemAllocManaged.restype = CUresult - cuMemAllocManaged.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuDeviceGetByPCIBusId = _libraries['libcuda.so'].cuDeviceGetByPCIBusId - cuDeviceGetByPCIBusId.restype = CUresult - cuDeviceGetByPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuDeviceGetPCIBusId = _libraries['libcuda.so'].cuDeviceGetPCIBusId - cuDeviceGetPCIBusId.restype = CUresult - cuDeviceGetPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, CUdevice] -except AttributeError: - pass -try: - cuIpcGetEventHandle = _libraries['libcuda.so'].cuIpcGetEventHandle - cuIpcGetEventHandle.restype = CUresult - cuIpcGetEventHandle.argtypes = [ctypes.POINTER(struct_CUipcEventHandle_st), CUevent] -except AttributeError: - pass -try: - cuIpcOpenEventHandle = _libraries['libcuda.so'].cuIpcOpenEventHandle - cuIpcOpenEventHandle.restype = CUresult - cuIpcOpenEventHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUevent_st)), CUipcEventHandle] -except AttributeError: - pass -try: - cuIpcGetMemHandle = _libraries['libcuda.so'].cuIpcGetMemHandle - cuIpcGetMemHandle.restype = CUresult - cuIpcGetMemHandle.argtypes = [ctypes.POINTER(struct_CUipcMemHandle_st), CUdeviceptr] -except AttributeError: - pass -try: - cuIpcOpenMemHandle_v2 = _libraries['libcuda.so'].cuIpcOpenMemHandle_v2 - cuIpcOpenMemHandle_v2.restype = CUresult - cuIpcOpenMemHandle_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUipcMemHandle, ctypes.c_uint32] -except AttributeError: - pass -try: - cuIpcCloseMemHandle = _libraries['libcuda.so'].cuIpcCloseMemHandle - cuIpcCloseMemHandle.restype = CUresult - cuIpcCloseMemHandle.argtypes = [CUdeviceptr] -except AttributeError: - pass -try: - cuMemHostRegister_v2 = _libraries['libcuda.so'].cuMemHostRegister_v2 - cuMemHostRegister_v2.restype = CUresult - cuMemHostRegister_v2.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostUnregister = _libraries['libcuda.so'].cuMemHostUnregister - cuMemHostUnregister.restype = CUresult - cuMemHostUnregister.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemcpy_ptds = _libraries['libcuda.so'].cuMemcpy_ptds - cuMemcpy_ptds.restype = CUresult - cuMemcpy_ptds.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyPeer_ptds = _libraries['libcuda.so'].cuMemcpyPeer_ptds - cuMemcpyPeer_ptds.restype = CUresult - cuMemcpyPeer_ptds.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoD_v2_ptds = _libraries['libcuda.so'].cuMemcpyHtoD_v2_ptds - cuMemcpyHtoD_v2_ptds.restype = CUresult - cuMemcpyHtoD_v2_ptds.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyDtoH_v2_ptds = _libraries['libcuda.so'].cuMemcpyDtoH_v2_ptds - cuMemcpyDtoH_v2_ptds.restype = CUresult - cuMemcpyDtoH_v2_ptds.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoD_v2_ptds = _libraries['libcuda.so'].cuMemcpyDtoD_v2_ptds - cuMemcpyDtoD_v2_ptds.restype = CUresult - cuMemcpyDtoD_v2_ptds.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoA_v2_ptds = _libraries['libcuda.so'].cuMemcpyDtoA_v2_ptds - cuMemcpyDtoA_v2_ptds.restype = CUresult - cuMemcpyDtoA_v2_ptds.argtypes = [CUarray, size_t, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoD_v2_ptds = _libraries['libcuda.so'].cuMemcpyAtoD_v2_ptds - cuMemcpyAtoD_v2_ptds.restype = CUresult - cuMemcpyAtoD_v2_ptds.argtypes = [CUdeviceptr, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoA_v2_ptds = _libraries['libcuda.so'].cuMemcpyHtoA_v2_ptds - cuMemcpyHtoA_v2_ptds.restype = CUresult - cuMemcpyHtoA_v2_ptds.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyAtoH_v2_ptds = _libraries['libcuda.so'].cuMemcpyAtoH_v2_ptds - cuMemcpyAtoH_v2_ptds.restype = CUresult - cuMemcpyAtoH_v2_ptds.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoA_v2_ptds = _libraries['libcuda.so'].cuMemcpyAtoA_v2_ptds - cuMemcpyAtoA_v2_ptds.restype = CUresult - cuMemcpyAtoA_v2_ptds.argtypes = [CUarray, size_t, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpy2D_v2_ptds = _libraries['libcuda.so'].cuMemcpy2D_v2_ptds - cuMemcpy2D_v2_ptds.restype = CUresult - cuMemcpy2D_v2_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy2DUnaligned_v2_ptds = _libraries['libcuda.so'].cuMemcpy2DUnaligned_v2_ptds - cuMemcpy2DUnaligned_v2_ptds.restype = CUresult - cuMemcpy2DUnaligned_v2_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy3D_v2_ptds = _libraries['libcuda.so'].cuMemcpy3D_v2_ptds - cuMemcpy3D_v2_ptds.restype = CUresult - cuMemcpy3D_v2_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuMemcpy3DPeer_ptds = _libraries['libcuda.so'].cuMemcpy3DPeer_ptds - cuMemcpy3DPeer_ptds.restype = CUresult - cuMemcpy3DPeer_ptds.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st)] -except AttributeError: - pass -try: - cuMemcpyAsync_ptsz = _libraries['libcuda.so'].cuMemcpyAsync_ptsz - cuMemcpyAsync_ptsz.restype = CUresult - cuMemcpyAsync_ptsz.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyPeerAsync_ptsz = _libraries['libcuda.so'].cuMemcpyPeerAsync_ptsz - cuMemcpyPeerAsync_ptsz.restype = CUresult - cuMemcpyPeerAsync_ptsz.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyHtoDAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyHtoDAsync_v2_ptsz - cuMemcpyHtoDAsync_v2_ptsz.restype = CUresult - cuMemcpyHtoDAsync_v2_ptsz.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoHAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyDtoHAsync_v2_ptsz - cuMemcpyDtoHAsync_v2_ptsz.restype = CUresult - cuMemcpyDtoHAsync_v2_ptsz.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoDAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyDtoDAsync_v2_ptsz - cuMemcpyDtoDAsync_v2_ptsz.restype = CUresult - cuMemcpyDtoDAsync_v2_ptsz.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyHtoAAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyHtoAAsync_v2_ptsz - cuMemcpyHtoAAsync_v2_ptsz.restype = CUresult - cuMemcpyHtoAAsync_v2_ptsz.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyAtoHAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpyAtoHAsync_v2_ptsz - cuMemcpyAtoHAsync_v2_ptsz.restype = CUresult - cuMemcpyAtoHAsync_v2_ptsz.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy2DAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpy2DAsync_v2_ptsz - cuMemcpy2DAsync_v2_ptsz.restype = CUresult - cuMemcpy2DAsync_v2_ptsz.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DAsync_v2_ptsz = _libraries['libcuda.so'].cuMemcpy3DAsync_v2_ptsz - cuMemcpy3DAsync_v2_ptsz.restype = CUresult - cuMemcpy3DAsync_v2_ptsz.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DPeerAsync_ptsz = _libraries['libcuda.so'].cuMemcpy3DPeerAsync_ptsz - cuMemcpy3DPeerAsync_ptsz.restype = CUresult - cuMemcpy3DPeerAsync_ptsz.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8_v2_ptds = _libraries['libcuda.so'].cuMemsetD8_v2_ptds - cuMemsetD8_v2_ptds.restype = CUresult - cuMemsetD8_v2_ptds.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t] -except AttributeError: - pass -try: - cuMemsetD16_v2_ptds = _libraries['libcuda.so'].cuMemsetD16_v2_ptds - cuMemsetD16_v2_ptds.restype = CUresult - cuMemsetD16_v2_ptds.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t] -except AttributeError: - pass -try: - cuMemsetD32_v2_ptds = _libraries['libcuda.so'].cuMemsetD32_v2_ptds - cuMemsetD32_v2_ptds.restype = CUresult - cuMemsetD32_v2_ptds.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t] -except AttributeError: - pass -try: - cuMemsetD2D8_v2_ptds = _libraries['libcuda.so'].cuMemsetD2D8_v2_ptds - cuMemsetD2D8_v2_ptds.restype = CUresult - cuMemsetD2D8_v2_ptds.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D16_v2_ptds = _libraries['libcuda.so'].cuMemsetD2D16_v2_ptds - cuMemsetD2D16_v2_ptds.restype = CUresult - cuMemsetD2D16_v2_ptds.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D32_v2_ptds = _libraries['libcuda.so'].cuMemsetD2D32_v2_ptds - cuMemsetD2D32_v2_ptds.restype = CUresult - cuMemsetD2D32_v2_ptds.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD8Async_ptsz = _libraries['libcuda.so'].cuMemsetD8Async_ptsz - cuMemsetD8Async_ptsz.restype = CUresult - cuMemsetD8Async_ptsz.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD16Async_ptsz = _libraries['libcuda.so'].cuMemsetD16Async_ptsz - cuMemsetD16Async_ptsz.restype = CUresult - cuMemsetD16Async_ptsz.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD32Async_ptsz = _libraries['libcuda.so'].cuMemsetD32Async_ptsz - cuMemsetD32Async_ptsz.restype = CUresult - cuMemsetD32Async_ptsz.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D8Async_ptsz = _libraries['libcuda.so'].cuMemsetD2D8Async_ptsz - cuMemsetD2D8Async_ptsz.restype = CUresult - cuMemsetD2D8Async_ptsz.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D16Async_ptsz = _libraries['libcuda.so'].cuMemsetD2D16Async_ptsz - cuMemsetD2D16Async_ptsz.restype = CUresult - cuMemsetD2D16Async_ptsz.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D32Async_ptsz = _libraries['libcuda.so'].cuMemsetD2D32Async_ptsz - cuMemsetD2D32Async_ptsz.restype = CUresult - cuMemsetD2D32Async_ptsz.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuArrayCreate_v2 = _libraries['libcuda.so'].cuArrayCreate_v2 - cuArrayCreate_v2.restype = CUresult - cuArrayCreate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st)] -except AttributeError: - pass -try: - cuArrayGetDescriptor_v2 = _libraries['libcuda.so'].cuArrayGetDescriptor_v2 - cuArrayGetDescriptor_v2.restype = CUresult - cuArrayGetDescriptor_v2.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st), CUarray] -except AttributeError: - pass -try: - cuArrayGetSparseProperties = _libraries['libcuda.so'].cuArrayGetSparseProperties - cuArrayGetSparseProperties.restype = CUresult - cuArrayGetSparseProperties.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_SPARSE_PROPERTIES_st), CUarray] -except AttributeError: - pass -try: - cuMipmappedArrayGetSparseProperties = _libraries['libcuda.so'].cuMipmappedArrayGetSparseProperties - cuMipmappedArrayGetSparseProperties.restype = CUresult - cuMipmappedArrayGetSparseProperties.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_SPARSE_PROPERTIES_st), CUmipmappedArray] -except AttributeError: - pass -try: - cuArrayGetMemoryRequirements = _libraries['libcuda.so'].cuArrayGetMemoryRequirements - cuArrayGetMemoryRequirements.restype = CUresult - cuArrayGetMemoryRequirements.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st), CUarray, CUdevice] -except AttributeError: - pass -try: - cuMipmappedArrayGetMemoryRequirements = _libraries['libcuda.so'].cuMipmappedArrayGetMemoryRequirements - cuMipmappedArrayGetMemoryRequirements.restype = CUresult - cuMipmappedArrayGetMemoryRequirements.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st), CUmipmappedArray, CUdevice] -except AttributeError: - pass -try: - cuArrayGetPlane = _libraries['libcuda.so'].cuArrayGetPlane - cuArrayGetPlane.restype = CUresult - cuArrayGetPlane.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUarray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuArrayDestroy = _libraries['libcuda.so'].cuArrayDestroy - cuArrayDestroy.restype = CUresult - cuArrayDestroy.argtypes = [CUarray] -except AttributeError: - pass -try: - cuArray3DCreate_v2 = _libraries['libcuda.so'].cuArray3DCreate_v2 - cuArray3DCreate_v2.restype = CUresult - cuArray3DCreate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_st)] -except AttributeError: - pass -try: - cuArray3DGetDescriptor_v2 = _libraries['libcuda.so'].cuArray3DGetDescriptor_v2 - cuArray3DGetDescriptor_v2.restype = CUresult - cuArray3DGetDescriptor_v2.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_st), CUarray] -except AttributeError: - pass -try: - cuMipmappedArrayCreate = _libraries['libcuda.so'].cuMipmappedArrayCreate - cuMipmappedArrayCreate.restype = CUresult - cuMipmappedArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_st), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMipmappedArrayGetLevel = _libraries['libcuda.so'].cuMipmappedArrayGetLevel - cuMipmappedArrayGetLevel.restype = CUresult - cuMipmappedArrayGetLevel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUmipmappedArray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMipmappedArrayDestroy = _libraries['libcuda.so'].cuMipmappedArrayDestroy - cuMipmappedArrayDestroy.restype = CUresult - cuMipmappedArrayDestroy.argtypes = [CUmipmappedArray] -except AttributeError: - pass -try: - cuMemGetHandleForAddressRange = _libraries['libcuda.so'].cuMemGetHandleForAddressRange - cuMemGetHandleForAddressRange.restype = CUresult - cuMemGetHandleForAddressRange.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t, CUmemRangeHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemAddressReserve = _libraries['libcuda.so'].cuMemAddressReserve - cuMemAddressReserve.restype = CUresult - cuMemAddressReserve.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, size_t, CUdeviceptr, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemAddressFree = _libraries['libcuda.so'].cuMemAddressFree - cuMemAddressFree.restype = CUresult - cuMemAddressFree.argtypes = [CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemCreate = _libraries['libcuda.so'].cuMemCreate - cuMemCreate.restype = CUresult - cuMemCreate.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, ctypes.POINTER(struct_CUmemAllocationProp_st), ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemRelease = _libraries['libcuda.so'].cuMemRelease - cuMemRelease.restype = CUresult - cuMemRelease.argtypes = [CUmemGenericAllocationHandle] -except AttributeError: - pass -try: - cuMemMap = _libraries['libcuda.so'].cuMemMap - cuMemMap.restype = CUresult - cuMemMap.argtypes = [CUdeviceptr, size_t, size_t, CUmemGenericAllocationHandle, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemMapArrayAsync_ptsz = _libraries['libcuda.so'].cuMemMapArrayAsync_ptsz - cuMemMapArrayAsync_ptsz.restype = CUresult - cuMemMapArrayAsync_ptsz.argtypes = [ctypes.POINTER(struct_CUarrayMapInfo_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemUnmap = _libraries['libcuda.so'].cuMemUnmap - cuMemUnmap.restype = CUresult - cuMemUnmap.argtypes = [CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemSetAccess = _libraries['libcuda.so'].cuMemSetAccess - cuMemSetAccess.restype = CUresult - cuMemSetAccess.argtypes = [CUdeviceptr, size_t, ctypes.POINTER(struct_CUmemAccessDesc_st), size_t] -except AttributeError: - pass -try: - cuMemGetAccess = _libraries['libcuda.so'].cuMemGetAccess - cuMemGetAccess.restype = CUresult - cuMemGetAccess.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUmemLocation_st), CUdeviceptr] -except AttributeError: - pass -try: - cuMemExportToShareableHandle = _libraries['libcuda.so'].cuMemExportToShareableHandle - cuMemExportToShareableHandle.restype = CUresult - cuMemExportToShareableHandle.argtypes = [ctypes.POINTER(None), CUmemGenericAllocationHandle, CUmemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemImportFromShareableHandle = _libraries['libcuda.so'].cuMemImportFromShareableHandle - cuMemImportFromShareableHandle.restype = CUresult - cuMemImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None), CUmemAllocationHandleType] -except AttributeError: - pass -try: - cuMemGetAllocationGranularity = _libraries['libcuda.so'].cuMemGetAllocationGranularity - cuMemGetAllocationGranularity.restype = CUresult - cuMemGetAllocationGranularity.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUmemAllocationProp_st), CUmemAllocationGranularity_flags] -except AttributeError: - pass -try: - cuMemGetAllocationPropertiesFromHandle = _libraries['libcuda.so'].cuMemGetAllocationPropertiesFromHandle - cuMemGetAllocationPropertiesFromHandle.restype = CUresult - cuMemGetAllocationPropertiesFromHandle.argtypes = [ctypes.POINTER(struct_CUmemAllocationProp_st), CUmemGenericAllocationHandle] -except AttributeError: - pass -try: - cuMemRetainAllocationHandle = _libraries['libcuda.so'].cuMemRetainAllocationHandle - cuMemRetainAllocationHandle.restype = CUresult - cuMemRetainAllocationHandle.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemFreeAsync_ptsz = _libraries['libcuda.so'].cuMemFreeAsync_ptsz - cuMemFreeAsync_ptsz.restype = CUresult - cuMemFreeAsync_ptsz.argtypes = [CUdeviceptr, CUstream] -except AttributeError: - pass -try: - cuMemAllocAsync_ptsz = _libraries['libcuda.so'].cuMemAllocAsync_ptsz - cuMemAllocAsync_ptsz.restype = CUresult - cuMemAllocAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUstream] -except AttributeError: - pass -try: - cuMemPoolTrimTo = _libraries['libcuda.so'].cuMemPoolTrimTo - cuMemPoolTrimTo.restype = CUresult - cuMemPoolTrimTo.argtypes = [CUmemoryPool, size_t] -except AttributeError: - pass -try: - cuMemPoolSetAttribute = _libraries['libcuda.so'].cuMemPoolSetAttribute - cuMemPoolSetAttribute.restype = CUresult - cuMemPoolSetAttribute.argtypes = [CUmemoryPool, CUmemPool_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemPoolGetAttribute = _libraries['libcuda.so'].cuMemPoolGetAttribute - cuMemPoolGetAttribute.restype = CUresult - cuMemPoolGetAttribute.argtypes = [CUmemoryPool, CUmemPool_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuMemPoolSetAccess = _libraries['libcuda.so'].cuMemPoolSetAccess - cuMemPoolSetAccess.restype = CUresult - cuMemPoolSetAccess.argtypes = [CUmemoryPool, ctypes.POINTER(struct_CUmemAccessDesc_st), size_t] -except AttributeError: - pass -try: - cuMemPoolGetAccess = _libraries['libcuda.so'].cuMemPoolGetAccess - cuMemPoolGetAccess.restype = CUresult - cuMemPoolGetAccess.argtypes = [ctypes.POINTER(CUmemAccess_flags_enum), CUmemoryPool, ctypes.POINTER(struct_CUmemLocation_st)] -except AttributeError: - pass -try: - cuMemPoolCreate = _libraries['libcuda.so'].cuMemPoolCreate - cuMemPoolCreate.restype = CUresult - cuMemPoolCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), ctypes.POINTER(struct_CUmemPoolProps_st)] -except AttributeError: - pass -try: - cuMemPoolDestroy = _libraries['libcuda.so'].cuMemPoolDestroy - cuMemPoolDestroy.restype = CUresult - cuMemPoolDestroy.argtypes = [CUmemoryPool] -except AttributeError: - pass -try: - cuMemAllocFromPoolAsync_ptsz = _libraries['libcuda.so'].cuMemAllocFromPoolAsync_ptsz - cuMemAllocFromPoolAsync_ptsz.restype = CUresult - cuMemAllocFromPoolAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUmemoryPool, CUstream] -except AttributeError: - pass -try: - cuMemPoolExportToShareableHandle = _libraries['libcuda.so'].cuMemPoolExportToShareableHandle - cuMemPoolExportToShareableHandle.restype = CUresult - cuMemPoolExportToShareableHandle.argtypes = [ctypes.POINTER(None), CUmemoryPool, CUmemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemPoolImportFromShareableHandle = _libraries['libcuda.so'].cuMemPoolImportFromShareableHandle - cuMemPoolImportFromShareableHandle.restype = CUresult - cuMemPoolImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmemPoolHandle_st)), ctypes.POINTER(None), CUmemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - cuMemPoolExportPointer = _libraries['libcuda.so'].cuMemPoolExportPointer - cuMemPoolExportPointer.restype = CUresult - cuMemPoolExportPointer.argtypes = [ctypes.POINTER(struct_CUmemPoolPtrExportData_st), CUdeviceptr] -except AttributeError: - pass -try: - cuMemPoolImportPointer = _libraries['libcuda.so'].cuMemPoolImportPointer - cuMemPoolImportPointer.restype = CUresult - cuMemPoolImportPointer.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUmemoryPool, ctypes.POINTER(struct_CUmemPoolPtrExportData_st)] -except AttributeError: - pass -try: - cuPointerGetAttribute = _libraries['libcuda.so'].cuPointerGetAttribute - cuPointerGetAttribute.restype = CUresult - cuPointerGetAttribute.argtypes = [ctypes.POINTER(None), CUpointer_attribute, CUdeviceptr] -except AttributeError: - pass -try: - cuMemPrefetchAsync_ptsz = _libraries['libcuda.so'].cuMemPrefetchAsync_ptsz - cuMemPrefetchAsync_ptsz.restype = CUresult - cuMemPrefetchAsync_ptsz.argtypes = [CUdeviceptr, size_t, CUdevice, CUstream] -except AttributeError: - pass -try: - cuMemAdvise = _libraries['libcuda.so'].cuMemAdvise - cuMemAdvise.restype = CUresult - cuMemAdvise.argtypes = [CUdeviceptr, size_t, CUmem_advise, CUdevice] -except AttributeError: - pass -try: - cuMemRangeGetAttribute = _libraries['libcuda.so'].cuMemRangeGetAttribute - cuMemRangeGetAttribute.restype = CUresult - cuMemRangeGetAttribute.argtypes = [ctypes.POINTER(None), size_t, CUmem_range_attribute, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemRangeGetAttributes = _libraries['libcuda.so'].cuMemRangeGetAttributes - cuMemRangeGetAttributes.restype = CUresult - cuMemRangeGetAttributes.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(CUmem_range_attribute_enum), size_t, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuPointerSetAttribute = _libraries['libcuda.so'].cuPointerSetAttribute - cuPointerSetAttribute.restype = CUresult - cuPointerSetAttribute.argtypes = [ctypes.POINTER(None), CUpointer_attribute, CUdeviceptr] -except AttributeError: - pass -try: - cuPointerGetAttributes = _libraries['libcuda.so'].cuPointerGetAttributes - cuPointerGetAttributes.restype = CUresult - cuPointerGetAttributes.argtypes = [ctypes.c_uint32, ctypes.POINTER(CUpointer_attribute_enum), ctypes.POINTER(ctypes.POINTER(None)), CUdeviceptr] -except AttributeError: - pass -try: - cuStreamCreate = _libraries['libcuda.so'].cuStreamCreate - cuStreamCreate.restype = CUresult - cuStreamCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUstream_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamCreateWithPriority = _libraries['libcuda.so'].cuStreamCreateWithPriority - cuStreamCreateWithPriority.restype = CUresult - cuStreamCreateWithPriority.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUstream_st)), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - cuStreamGetPriority_ptsz = _libraries['libcuda.so'].cuStreamGetPriority_ptsz - cuStreamGetPriority_ptsz.restype = CUresult - cuStreamGetPriority_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuStreamGetFlags_ptsz = _libraries['libcuda.so'].cuStreamGetFlags_ptsz - cuStreamGetFlags_ptsz.restype = CUresult - cuStreamGetFlags_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuStreamGetId_ptsz = _libraries['libcuda.so'].cuStreamGetId_ptsz - cuStreamGetId_ptsz.restype = CUresult - cuStreamGetId_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetCtx_ptsz = _libraries['libcuda.so'].cuStreamGetCtx_ptsz - cuStreamGetCtx_ptsz.restype = CUresult - cuStreamGetCtx_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuStreamWaitEvent_ptsz = _libraries['libcuda.so'].cuStreamWaitEvent_ptsz - cuStreamWaitEvent_ptsz.restype = CUresult - cuStreamWaitEvent_ptsz.argtypes = [CUstream, CUevent, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAddCallback_ptsz = _libraries['libcuda.so'].cuStreamAddCallback_ptsz - cuStreamAddCallback_ptsz.restype = CUresult - cuStreamAddCallback_ptsz.argtypes = [CUstream, CUstreamCallback, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBeginCapture_v2_ptsz = _libraries['libcuda.so'].cuStreamBeginCapture_v2_ptsz - cuStreamBeginCapture_v2_ptsz.restype = CUresult - cuStreamBeginCapture_v2_ptsz.argtypes = [CUstream, CUstreamCaptureMode] -except AttributeError: - pass -try: - cuThreadExchangeStreamCaptureMode = _libraries['libcuda.so'].cuThreadExchangeStreamCaptureMode - cuThreadExchangeStreamCaptureMode.restype = CUresult - cuThreadExchangeStreamCaptureMode.argtypes = [ctypes.POINTER(CUstreamCaptureMode_enum)] -except AttributeError: - pass -try: - cuStreamEndCapture_ptsz = _libraries['libcuda.so'].cuStreamEndCapture_ptsz - cuStreamEndCapture_ptsz.restype = CUresult - cuStreamEndCapture_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st))] -except AttributeError: - pass -try: - cuStreamIsCapturing_ptsz = _libraries['libcuda.so'].cuStreamIsCapturing_ptsz - cuStreamIsCapturing_ptsz.restype = CUresult - cuStreamIsCapturing_ptsz.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo_v2_ptsz = _libraries['libcuda.so'].cuStreamGetCaptureInfo_v2_ptsz - cuStreamGetCaptureInfo_v2_ptsz.restype = CUresult - cuStreamGetCaptureInfo_v2_ptsz.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st))), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamUpdateCaptureDependencies_ptsz = _libraries['libcuda.so'].cuStreamUpdateCaptureDependencies_ptsz - cuStreamUpdateCaptureDependencies_ptsz.restype = CUresult - cuStreamUpdateCaptureDependencies_ptsz.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAttachMemAsync_ptsz = _libraries['libcuda.so'].cuStreamAttachMemAsync_ptsz - cuStreamAttachMemAsync_ptsz.restype = CUresult - cuStreamAttachMemAsync_ptsz.argtypes = [CUstream, CUdeviceptr, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamQuery_ptsz = _libraries['libcuda.so'].cuStreamQuery_ptsz - cuStreamQuery_ptsz.restype = CUresult - cuStreamQuery_ptsz.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamSynchronize_ptsz = _libraries['libcuda.so'].cuStreamSynchronize_ptsz - cuStreamSynchronize_ptsz.restype = CUresult - cuStreamSynchronize_ptsz.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamDestroy_v2 = _libraries['libcuda.so'].cuStreamDestroy_v2 - cuStreamDestroy_v2.restype = CUresult - cuStreamDestroy_v2.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamCopyAttributes_ptsz = _libraries['libcuda.so'].cuStreamCopyAttributes_ptsz - cuStreamCopyAttributes_ptsz.restype = CUresult - cuStreamCopyAttributes_ptsz.argtypes = [CUstream, CUstream] -except AttributeError: - pass -try: - cuStreamGetAttribute_ptsz = _libraries['libcuda.so'].cuStreamGetAttribute_ptsz - cuStreamGetAttribute_ptsz.restype = CUresult - cuStreamGetAttribute_ptsz.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuStreamSetAttribute_ptsz = _libraries['libcuda.so'].cuStreamSetAttribute_ptsz - cuStreamSetAttribute_ptsz.restype = CUresult - cuStreamSetAttribute_ptsz.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuEventCreate = _libraries['libcuda.so'].cuEventCreate - cuEventCreate.restype = CUresult - cuEventCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUevent_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuEventRecord_ptsz = _libraries['libcuda.so'].cuEventRecord_ptsz - cuEventRecord_ptsz.restype = CUresult - cuEventRecord_ptsz.argtypes = [CUevent, CUstream] -except AttributeError: - pass -try: - cuEventRecordWithFlags_ptsz = _libraries['libcuda.so'].cuEventRecordWithFlags_ptsz - cuEventRecordWithFlags_ptsz.restype = CUresult - cuEventRecordWithFlags_ptsz.argtypes = [CUevent, CUstream, ctypes.c_uint32] -except AttributeError: - pass -try: - cuEventQuery = _libraries['libcuda.so'].cuEventQuery - cuEventQuery.restype = CUresult - cuEventQuery.argtypes = [CUevent] -except AttributeError: - pass -try: - cuEventSynchronize = _libraries['libcuda.so'].cuEventSynchronize - cuEventSynchronize.restype = CUresult - cuEventSynchronize.argtypes = [CUevent] -except AttributeError: - pass -try: - cuEventDestroy_v2 = _libraries['libcuda.so'].cuEventDestroy_v2 - cuEventDestroy_v2.restype = CUresult - cuEventDestroy_v2.argtypes = [CUevent] -except AttributeError: - pass -try: - cuEventElapsedTime = _libraries['libcuda.so'].cuEventElapsedTime - cuEventElapsedTime.restype = CUresult - cuEventElapsedTime.argtypes = [ctypes.POINTER(ctypes.c_float), CUevent, CUevent] -except AttributeError: - pass -try: - cuImportExternalMemory = _libraries['libcuda.so'].cuImportExternalMemory - cuImportExternalMemory.restype = CUresult - cuImportExternalMemory.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextMemory_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st)] -except AttributeError: - pass -try: - cuExternalMemoryGetMappedBuffer = _libraries['libcuda.so'].cuExternalMemoryGetMappedBuffer - cuExternalMemoryGetMappedBuffer.restype = CUresult - cuExternalMemoryGetMappedBuffer.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUexternalMemory, ctypes.POINTER(struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st)] -except AttributeError: - pass -try: - cuExternalMemoryGetMappedMipmappedArray = _libraries['libcuda.so'].cuExternalMemoryGetMappedMipmappedArray - cuExternalMemoryGetMappedMipmappedArray.restype = CUresult - cuExternalMemoryGetMappedMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), CUexternalMemory, ctypes.POINTER(struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st)] -except AttributeError: - pass -try: - cuDestroyExternalMemory = _libraries['libcuda.so'].cuDestroyExternalMemory - cuDestroyExternalMemory.restype = CUresult - cuDestroyExternalMemory.argtypes = [CUexternalMemory] -except AttributeError: - pass -try: - cuImportExternalSemaphore = _libraries['libcuda.so'].cuImportExternalSemaphore - cuImportExternalSemaphore.restype = CUresult - cuImportExternalSemaphore.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st)] -except AttributeError: - pass -try: - cuSignalExternalSemaphoresAsync_ptsz = _libraries['libcuda.so'].cuSignalExternalSemaphoresAsync_ptsz - cuSignalExternalSemaphoresAsync_ptsz.restype = CUresult - cuSignalExternalSemaphoresAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuWaitExternalSemaphoresAsync_ptsz = _libraries['libcuda.so'].cuWaitExternalSemaphoresAsync_ptsz - cuWaitExternalSemaphoresAsync_ptsz.restype = CUresult - cuWaitExternalSemaphoresAsync_ptsz.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuDestroyExternalSemaphore = _libraries['libcuda.so'].cuDestroyExternalSemaphore - cuDestroyExternalSemaphore.restype = CUresult - cuDestroyExternalSemaphore.argtypes = [CUexternalSemaphore] -except AttributeError: - pass -try: - cuStreamWaitValue32_v2_ptsz = _libraries['libcuda.so'].cuStreamWaitValue32_v2_ptsz - cuStreamWaitValue32_v2_ptsz.restype = CUresult - cuStreamWaitValue32_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64_v2_ptsz = _libraries['libcuda.so'].cuStreamWaitValue64_v2_ptsz - cuStreamWaitValue64_v2_ptsz.restype = CUresult - cuStreamWaitValue64_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue32_v2_ptsz = _libraries['libcuda.so'].cuStreamWriteValue32_v2_ptsz - cuStreamWriteValue32_v2_ptsz.restype = CUresult - cuStreamWriteValue32_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64_v2_ptsz = _libraries['libcuda.so'].cuStreamWriteValue64_v2_ptsz - cuStreamWriteValue64_v2_ptsz.restype = CUresult - cuStreamWriteValue64_v2_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp_v2_ptsz = _libraries['libcuda.so'].cuStreamBatchMemOp_v2_ptsz - cuStreamBatchMemOp_v2_ptsz.restype = CUresult - cuStreamBatchMemOp_v2_ptsz.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuFuncGetAttribute = _libraries['libcuda.so'].cuFuncGetAttribute - cuFuncGetAttribute.restype = CUresult - cuFuncGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction_attribute, CUfunction] -except AttributeError: - pass -try: - cuFuncSetAttribute = _libraries['libcuda.so'].cuFuncSetAttribute - cuFuncSetAttribute.restype = CUresult - cuFuncSetAttribute.argtypes = [CUfunction, CUfunction_attribute, ctypes.c_int32] -except AttributeError: - pass -try: - cuFuncSetCacheConfig = _libraries['libcuda.so'].cuFuncSetCacheConfig - cuFuncSetCacheConfig.restype = CUresult - cuFuncSetCacheConfig.argtypes = [CUfunction, CUfunc_cache] -except AttributeError: - pass -try: - cuFuncSetSharedMemConfig = _libraries['libcuda.so'].cuFuncSetSharedMemConfig - cuFuncSetSharedMemConfig.restype = CUresult - cuFuncSetSharedMemConfig.argtypes = [CUfunction, CUsharedconfig] -except AttributeError: - pass -try: - cuFuncGetModule = _libraries['libcuda.so'].cuFuncGetModule - cuFuncGetModule.restype = CUresult - cuFuncGetModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmod_st)), CUfunction] -except AttributeError: - pass -try: - cuLaunchKernel_ptsz = _libraries['libcuda.so'].cuLaunchKernel_ptsz - cuLaunchKernel_ptsz.restype = CUresult - cuLaunchKernel_ptsz.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchKernelEx_ptsz = _libraries['libcuda.so'].cuLaunchKernelEx_ptsz - cuLaunchKernelEx_ptsz.restype = CUresult - cuLaunchKernelEx_ptsz.argtypes = [ctypes.POINTER(struct_CUlaunchConfig_st), CUfunction, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchCooperativeKernel_ptsz = _libraries['libcuda.so'].cuLaunchCooperativeKernel_ptsz - cuLaunchCooperativeKernel_ptsz.restype = CUresult - cuLaunchCooperativeKernel_ptsz.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchCooperativeKernelMultiDevice = _libraries['libcuda.so'].cuLaunchCooperativeKernelMultiDevice - cuLaunchCooperativeKernelMultiDevice.restype = CUresult - cuLaunchCooperativeKernelMultiDevice.argtypes = [ctypes.POINTER(struct_CUDA_LAUNCH_PARAMS_st), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuLaunchHostFunc_ptsz = _libraries['libcuda.so'].cuLaunchHostFunc_ptsz - cuLaunchHostFunc_ptsz.restype = CUresult - cuLaunchHostFunc_ptsz.argtypes = [CUstream, CUhostFn, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuFuncSetBlockShape = _libraries['libcuda.so'].cuFuncSetBlockShape - cuFuncSetBlockShape.restype = CUresult - cuFuncSetBlockShape.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - cuFuncSetSharedSize = _libraries['libcuda.so'].cuFuncSetSharedSize - cuFuncSetSharedSize.restype = CUresult - cuFuncSetSharedSize.argtypes = [CUfunction, ctypes.c_uint32] -except AttributeError: - pass -try: - cuParamSetSize = _libraries['libcuda.so'].cuParamSetSize - cuParamSetSize.restype = CUresult - cuParamSetSize.argtypes = [CUfunction, ctypes.c_uint32] -except AttributeError: - pass -try: - cuParamSeti = _libraries['libcuda.so'].cuParamSeti - cuParamSeti.restype = CUresult - cuParamSeti.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuParamSetf = _libraries['libcuda.so'].cuParamSetf - cuParamSetf.restype = CUresult - cuParamSetf.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_float] -except AttributeError: - pass -try: - cuParamSetv = _libraries['libcuda.so'].cuParamSetv - cuParamSetv.restype = CUresult - cuParamSetv.argtypes = [CUfunction, ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuLaunch = _libraries['libcuda.so'].cuLaunch - cuLaunch.restype = CUresult - cuLaunch.argtypes = [CUfunction] -except AttributeError: - pass -try: - cuLaunchGrid = _libraries['libcuda.so'].cuLaunchGrid - cuLaunchGrid.restype = CUresult - cuLaunchGrid.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - cuLaunchGridAsync = _libraries['libcuda.so'].cuLaunchGridAsync - cuLaunchGridAsync.restype = CUresult - cuLaunchGridAsync.argtypes = [CUfunction, ctypes.c_int32, ctypes.c_int32, CUstream] -except AttributeError: - pass -try: - cuParamSetTexRef = _libraries['libcuda.so'].cuParamSetTexRef - cuParamSetTexRef.restype = CUresult - cuParamSetTexRef.argtypes = [CUfunction, ctypes.c_int32, CUtexref] -except AttributeError: - pass -try: - cuGraphCreate = _libraries['libcuda.so'].cuGraphCreate - cuGraphCreate.restype = CUresult - cuGraphCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphAddKernelNode_v2 = _libraries['libcuda.so'].cuGraphAddKernelNode_v2 - cuGraphAddKernelNode_v2.restype = CUresult - cuGraphAddKernelNode_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeGetParams_v2 = _libraries['libcuda.so'].cuGraphKernelNodeGetParams_v2 - cuGraphKernelNodeGetParams_v2.restype = CUresult - cuGraphKernelNodeGetParams_v2.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeSetParams_v2 = _libraries['libcuda.so'].cuGraphKernelNodeSetParams_v2 - cuGraphKernelNodeSetParams_v2.restype = CUresult - cuGraphKernelNodeSetParams_v2.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphAddMemcpyNode = _libraries['libcuda.so'].cuGraphAddMemcpyNode - cuGraphAddMemcpyNode.restype = CUresult - cuGraphAddMemcpyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUcontext] -except AttributeError: - pass -try: - cuGraphMemcpyNodeGetParams = _libraries['libcuda.so'].cuGraphMemcpyNodeGetParams - cuGraphMemcpyNodeGetParams.restype = CUresult - cuGraphMemcpyNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuGraphMemcpyNodeSetParams = _libraries['libcuda.so'].cuGraphMemcpyNodeSetParams - cuGraphMemcpyNodeSetParams.restype = CUresult - cuGraphMemcpyNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuGraphAddMemsetNode = _libraries['libcuda.so'].cuGraphAddMemsetNode - cuGraphAddMemsetNode.restype = CUresult - cuGraphAddMemsetNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st), CUcontext] -except AttributeError: - pass -try: - cuGraphMemsetNodeGetParams = _libraries['libcuda.so'].cuGraphMemsetNodeGetParams - cuGraphMemsetNodeGetParams.restype = CUresult - cuGraphMemsetNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphMemsetNodeSetParams = _libraries['libcuda.so'].cuGraphMemsetNodeSetParams - cuGraphMemsetNodeSetParams.restype = CUresult - cuGraphMemsetNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddHostNode = _libraries['libcuda.so'].cuGraphAddHostNode - cuGraphAddHostNode.restype = CUresult - cuGraphAddHostNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphHostNodeGetParams = _libraries['libcuda.so'].cuGraphHostNodeGetParams - cuGraphHostNodeGetParams.restype = CUresult - cuGraphHostNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphHostNodeSetParams = _libraries['libcuda.so'].cuGraphHostNodeSetParams - cuGraphHostNodeSetParams.restype = CUresult - cuGraphHostNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddChildGraphNode = _libraries['libcuda.so'].cuGraphAddChildGraphNode - cuGraphAddChildGraphNode.restype = CUresult - cuGraphAddChildGraphNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUgraph] -except AttributeError: - pass -try: - cuGraphChildGraphNodeGetGraph = _libraries['libcuda.so'].cuGraphChildGraphNodeGetGraph - cuGraphChildGraphNodeGetGraph.restype = CUresult - cuGraphChildGraphNodeGetGraph.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st))] -except AttributeError: - pass -try: - cuGraphAddEmptyNode = _libraries['libcuda.so'].cuGraphAddEmptyNode - cuGraphAddEmptyNode.restype = CUresult - cuGraphAddEmptyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t] -except AttributeError: - pass -try: - cuGraphAddEventRecordNode = _libraries['libcuda.so'].cuGraphAddEventRecordNode - cuGraphAddEventRecordNode.restype = CUresult - cuGraphAddEventRecordNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUevent] -except AttributeError: - pass -try: - cuGraphEventRecordNodeGetEvent = _libraries['libcuda.so'].cuGraphEventRecordNodeGetEvent - cuGraphEventRecordNodeGetEvent.restype = CUresult - cuGraphEventRecordNodeGetEvent.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUevent_st))] -except AttributeError: - pass -try: - cuGraphEventRecordNodeSetEvent = _libraries['libcuda.so'].cuGraphEventRecordNodeSetEvent - cuGraphEventRecordNodeSetEvent.restype = CUresult - cuGraphEventRecordNodeSetEvent.argtypes = [CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphAddEventWaitNode = _libraries['libcuda.so'].cuGraphAddEventWaitNode - cuGraphAddEventWaitNode.restype = CUresult - cuGraphAddEventWaitNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUevent] -except AttributeError: - pass -try: - cuGraphEventWaitNodeGetEvent = _libraries['libcuda.so'].cuGraphEventWaitNodeGetEvent - cuGraphEventWaitNodeGetEvent.restype = CUresult - cuGraphEventWaitNodeGetEvent.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUevent_st))] -except AttributeError: - pass -try: - cuGraphEventWaitNodeSetEvent = _libraries['libcuda.so'].cuGraphEventWaitNodeSetEvent - cuGraphEventWaitNodeSetEvent.restype = CUresult - cuGraphEventWaitNodeSetEvent.argtypes = [CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphAddExternalSemaphoresSignalNode = _libraries['libcuda.so'].cuGraphAddExternalSemaphoresSignalNode - cuGraphAddExternalSemaphoresSignalNode.restype = CUresult - cuGraphAddExternalSemaphoresSignalNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresSignalNodeGetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresSignalNodeGetParams - cuGraphExternalSemaphoresSignalNodeGetParams.restype = CUresult - cuGraphExternalSemaphoresSignalNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresSignalNodeSetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresSignalNodeSetParams - cuGraphExternalSemaphoresSignalNodeSetParams.restype = CUresult - cuGraphExternalSemaphoresSignalNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddExternalSemaphoresWaitNode = _libraries['libcuda.so'].cuGraphAddExternalSemaphoresWaitNode - cuGraphAddExternalSemaphoresWaitNode.restype = CUresult - cuGraphAddExternalSemaphoresWaitNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresWaitNodeGetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresWaitNodeGetParams - cuGraphExternalSemaphoresWaitNodeGetParams.restype = CUresult - cuGraphExternalSemaphoresWaitNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExternalSemaphoresWaitNodeSetParams = _libraries['libcuda.so'].cuGraphExternalSemaphoresWaitNodeSetParams - cuGraphExternalSemaphoresWaitNodeSetParams.restype = CUresult - cuGraphExternalSemaphoresWaitNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddBatchMemOpNode = _libraries['libcuda.so'].cuGraphAddBatchMemOpNode - cuGraphAddBatchMemOpNode.restype = CUresult - cuGraphAddBatchMemOpNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphBatchMemOpNodeGetParams = _libraries['libcuda.so'].cuGraphBatchMemOpNodeGetParams - cuGraphBatchMemOpNodeGetParams.restype = CUresult - cuGraphBatchMemOpNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphBatchMemOpNodeSetParams = _libraries['libcuda.so'].cuGraphBatchMemOpNodeSetParams - cuGraphBatchMemOpNodeSetParams.restype = CUresult - cuGraphBatchMemOpNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecBatchMemOpNodeSetParams = _libraries['libcuda.so'].cuGraphExecBatchMemOpNodeSetParams - cuGraphExecBatchMemOpNodeSetParams.restype = CUresult - cuGraphExecBatchMemOpNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddMemAllocNode = _libraries['libcuda.so'].cuGraphAddMemAllocNode - cuGraphAddMemAllocNode.restype = CUresult - cuGraphAddMemAllocNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_MEM_ALLOC_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphMemAllocNodeGetParams = _libraries['libcuda.so'].cuGraphMemAllocNodeGetParams - cuGraphMemAllocNodeGetParams.restype = CUresult - cuGraphMemAllocNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_MEM_ALLOC_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphAddMemFreeNode = _libraries['libcuda.so'].cuGraphAddMemFreeNode - cuGraphAddMemFreeNode.restype = CUresult - cuGraphAddMemFreeNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, CUdeviceptr] -except AttributeError: - pass -try: - cuGraphMemFreeNodeGetParams = _libraries['libcuda.so'].cuGraphMemFreeNodeGetParams - cuGraphMemFreeNodeGetParams.restype = CUresult - cuGraphMemFreeNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuDeviceGraphMemTrim = _libraries['libcuda.so'].cuDeviceGraphMemTrim - cuDeviceGraphMemTrim.restype = CUresult - cuDeviceGraphMemTrim.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDeviceGetGraphMemAttribute = _libraries['libcuda.so'].cuDeviceGetGraphMemAttribute - cuDeviceGetGraphMemAttribute.restype = CUresult - cuDeviceGetGraphMemAttribute.argtypes = [CUdevice, CUgraphMem_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuDeviceSetGraphMemAttribute = _libraries['libcuda.so'].cuDeviceSetGraphMemAttribute - cuDeviceSetGraphMemAttribute.restype = CUresult - cuDeviceSetGraphMemAttribute.argtypes = [CUdevice, CUgraphMem_attribute, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuGraphClone = _libraries['libcuda.so'].cuGraphClone - cuGraphClone.restype = CUresult - cuGraphClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), CUgraph] -except AttributeError: - pass -try: - cuGraphNodeFindInClone = _libraries['libcuda.so'].cuGraphNodeFindInClone - cuGraphNodeFindInClone.restype = CUresult - cuGraphNodeFindInClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraphNode, CUgraph] -except AttributeError: - pass -try: - cuGraphNodeGetType = _libraries['libcuda.so'].cuGraphNodeGetType - cuGraphNodeGetType.restype = CUresult - cuGraphNodeGetType.argtypes = [CUgraphNode, ctypes.POINTER(CUgraphNodeType_enum)] -except AttributeError: - pass -try: - cuGraphGetNodes = _libraries['libcuda.so'].cuGraphGetNodes - cuGraphGetNodes.restype = CUresult - cuGraphGetNodes.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphGetRootNodes = _libraries['libcuda.so'].cuGraphGetRootNodes - cuGraphGetRootNodes.restype = CUresult - cuGraphGetRootNodes.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphGetEdges = _libraries['libcuda.so'].cuGraphGetEdges - cuGraphGetEdges.restype = CUresult - cuGraphGetEdges.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphNodeGetDependencies = _libraries['libcuda.so'].cuGraphNodeGetDependencies - cuGraphNodeGetDependencies.restype = CUresult - cuGraphNodeGetDependencies.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphNodeGetDependentNodes = _libraries['libcuda.so'].cuGraphNodeGetDependentNodes - cuGraphNodeGetDependentNodes.restype = CUresult - cuGraphNodeGetDependentNodes.argtypes = [CUgraphNode, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphAddDependencies = _libraries['libcuda.so'].cuGraphAddDependencies - cuGraphAddDependencies.restype = CUresult - cuGraphAddDependencies.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t] -except AttributeError: - pass -try: - cuGraphRemoveDependencies = _libraries['libcuda.so'].cuGraphRemoveDependencies - cuGraphRemoveDependencies.restype = CUresult - cuGraphRemoveDependencies.argtypes = [CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t] -except AttributeError: - pass -try: - cuGraphDestroyNode = _libraries['libcuda.so'].cuGraphDestroyNode - cuGraphDestroyNode.restype = CUresult - cuGraphDestroyNode.argtypes = [CUgraphNode] -except AttributeError: - pass -try: - cuGraphInstantiateWithFlags = _libraries['libcuda.so'].cuGraphInstantiateWithFlags - cuGraphInstantiateWithFlags.restype = CUresult - cuGraphInstantiateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.c_uint64] -except AttributeError: - pass -try: - cuGraphInstantiateWithParams_ptsz = _libraries['libcuda.so'].cuGraphInstantiateWithParams_ptsz - cuGraphInstantiateWithParams_ptsz.restype = CUresult - cuGraphInstantiateWithParams_ptsz.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecGetFlags = _libraries['libcuda.so'].cuGraphExecGetFlags - cuGraphExecGetFlags.restype = CUresult - cuGraphExecGetFlags.argtypes = [CUgraphExec, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphExecKernelNodeSetParams_v2 = _libraries['libcuda.so'].cuGraphExecKernelNodeSetParams_v2 - cuGraphExecKernelNodeSetParams_v2.restype = CUresult - cuGraphExecKernelNodeSetParams_v2.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_v2_st)] -except AttributeError: - pass -try: - cuGraphExecMemcpyNodeSetParams = _libraries['libcuda.so'].cuGraphExecMemcpyNodeSetParams - cuGraphExecMemcpyNodeSetParams.restype = CUresult - cuGraphExecMemcpyNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUcontext] -except AttributeError: - pass -try: - cuGraphExecMemsetNodeSetParams = _libraries['libcuda.so'].cuGraphExecMemsetNodeSetParams - cuGraphExecMemsetNodeSetParams.restype = CUresult - cuGraphExecMemsetNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_MEMSET_NODE_PARAMS_st), CUcontext] -except AttributeError: - pass -try: - cuGraphExecHostNodeSetParams = _libraries['libcuda.so'].cuGraphExecHostNodeSetParams - cuGraphExecHostNodeSetParams.restype = CUresult - cuGraphExecHostNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_HOST_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecChildGraphNodeSetParams = _libraries['libcuda.so'].cuGraphExecChildGraphNodeSetParams - cuGraphExecChildGraphNodeSetParams.restype = CUresult - cuGraphExecChildGraphNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, CUgraph] -except AttributeError: - pass -try: - cuGraphExecEventRecordNodeSetEvent = _libraries['libcuda.so'].cuGraphExecEventRecordNodeSetEvent - cuGraphExecEventRecordNodeSetEvent.restype = CUresult - cuGraphExecEventRecordNodeSetEvent.argtypes = [CUgraphExec, CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphExecEventWaitNodeSetEvent = _libraries['libcuda.so'].cuGraphExecEventWaitNodeSetEvent - cuGraphExecEventWaitNodeSetEvent.restype = CUresult - cuGraphExecEventWaitNodeSetEvent.argtypes = [CUgraphExec, CUgraphNode, CUevent] -except AttributeError: - pass -try: - cuGraphExecExternalSemaphoresSignalNodeSetParams = _libraries['libcuda.so'].cuGraphExecExternalSemaphoresSignalNodeSetParams - cuGraphExecExternalSemaphoresSignalNodeSetParams.restype = CUresult - cuGraphExecExternalSemaphoresSignalNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecExternalSemaphoresWaitNodeSetParams = _libraries['libcuda.so'].cuGraphExecExternalSemaphoresWaitNodeSetParams - cuGraphExecExternalSemaphoresWaitNodeSetParams.restype = CUresult - cuGraphExecExternalSemaphoresWaitNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphNodeSetEnabled = _libraries['libcuda.so'].cuGraphNodeSetEnabled - cuGraphNodeSetEnabled.restype = CUresult - cuGraphNodeSetEnabled.argtypes = [CUgraphExec, CUgraphNode, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphNodeGetEnabled = _libraries['libcuda.so'].cuGraphNodeGetEnabled - cuGraphNodeGetEnabled.restype = CUresult - cuGraphNodeGetEnabled.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuGraphUpload_ptsz = _libraries['libcuda.so'].cuGraphUpload_ptsz - cuGraphUpload_ptsz.restype = CUresult - cuGraphUpload_ptsz.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuGraphLaunch_ptsz = _libraries['libcuda.so'].cuGraphLaunch_ptsz - cuGraphLaunch_ptsz.restype = CUresult - cuGraphLaunch_ptsz.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuGraphExecDestroy = _libraries['libcuda.so'].cuGraphExecDestroy - cuGraphExecDestroy.restype = CUresult - cuGraphExecDestroy.argtypes = [CUgraphExec] -except AttributeError: - pass -try: - cuGraphDestroy = _libraries['libcuda.so'].cuGraphDestroy - cuGraphDestroy.restype = CUresult - cuGraphDestroy.argtypes = [CUgraph] -except AttributeError: - pass -try: - cuGraphExecUpdate_v2 = _libraries['libcuda.so'].cuGraphExecUpdate_v2 - cuGraphExecUpdate_v2.restype = CUresult - cuGraphExecUpdate_v2.argtypes = [CUgraphExec, CUgraph, ctypes.POINTER(struct_CUgraphExecUpdateResultInfo_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeCopyAttributes = _libraries['libcuda.so'].cuGraphKernelNodeCopyAttributes - cuGraphKernelNodeCopyAttributes.restype = CUresult - cuGraphKernelNodeCopyAttributes.argtypes = [CUgraphNode, CUgraphNode] -except AttributeError: - pass -try: - cuGraphKernelNodeGetAttribute = _libraries['libcuda.so'].cuGraphKernelNodeGetAttribute - cuGraphKernelNodeGetAttribute.restype = CUresult - cuGraphKernelNodeGetAttribute.argtypes = [CUgraphNode, CUkernelNodeAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuGraphKernelNodeSetAttribute = _libraries['libcuda.so'].cuGraphKernelNodeSetAttribute - cuGraphKernelNodeSetAttribute.restype = CUresult - cuGraphKernelNodeSetAttribute.argtypes = [CUgraphNode, CUkernelNodeAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuGraphDebugDotPrint = _libraries['libcuda.so'].cuGraphDebugDotPrint - cuGraphDebugDotPrint.restype = CUresult - cuGraphDebugDotPrint.argtypes = [CUgraph, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - cuUserObjectCreate = _libraries['libcuda.so'].cuUserObjectCreate - cuUserObjectCreate.restype = CUresult - cuUserObjectCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUuserObject_st)), ctypes.POINTER(None), CUhostFn, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuUserObjectRetain = _libraries['libcuda.so'].cuUserObjectRetain - cuUserObjectRetain.restype = CUresult - cuUserObjectRetain.argtypes = [CUuserObject, ctypes.c_uint32] -except AttributeError: - pass -try: - cuUserObjectRelease = _libraries['libcuda.so'].cuUserObjectRelease - cuUserObjectRelease.restype = CUresult - cuUserObjectRelease.argtypes = [CUuserObject, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphRetainUserObject = _libraries['libcuda.so'].cuGraphRetainUserObject - cuGraphRetainUserObject.restype = CUresult - cuGraphRetainUserObject.argtypes = [CUgraph, CUuserObject, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphReleaseUserObject = _libraries['libcuda.so'].cuGraphReleaseUserObject - cuGraphReleaseUserObject.restype = CUresult - cuGraphReleaseUserObject.argtypes = [CUgraph, CUuserObject, ctypes.c_uint32] -except AttributeError: - pass -try: - cuOccupancyMaxActiveBlocksPerMultiprocessor = _libraries['libcuda.so'].cuOccupancyMaxActiveBlocksPerMultiprocessor - cuOccupancyMaxActiveBlocksPerMultiprocessor.restype = CUresult - cuOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.c_int32, size_t] -except AttributeError: - pass -try: - cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags = _libraries['libcuda.so'].cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags - cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.restype = CUresult - cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.c_int32, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuOccupancyMaxPotentialBlockSize = _libraries['libcuda.so'].cuOccupancyMaxPotentialBlockSize - cuOccupancyMaxPotentialBlockSize.restype = CUresult - cuOccupancyMaxPotentialBlockSize.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUfunction, CUoccupancyB2DSize, size_t, ctypes.c_int32] -except AttributeError: - pass -try: - cuOccupancyMaxPotentialBlockSizeWithFlags = _libraries['libcuda.so'].cuOccupancyMaxPotentialBlockSizeWithFlags - cuOccupancyMaxPotentialBlockSizeWithFlags.restype = CUresult - cuOccupancyMaxPotentialBlockSizeWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), CUfunction, CUoccupancyB2DSize, size_t, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuOccupancyAvailableDynamicSMemPerBlock = _libraries['libcuda.so'].cuOccupancyAvailableDynamicSMemPerBlock - cuOccupancyAvailableDynamicSMemPerBlock.restype = CUresult - cuOccupancyAvailableDynamicSMemPerBlock.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUfunction, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - cuOccupancyMaxPotentialClusterSize = _libraries['libcuda.so'].cuOccupancyMaxPotentialClusterSize - cuOccupancyMaxPotentialClusterSize.restype = CUresult - cuOccupancyMaxPotentialClusterSize.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.POINTER(struct_CUlaunchConfig_st)] -except AttributeError: - pass -try: - cuOccupancyMaxActiveClusters = _libraries['libcuda.so'].cuOccupancyMaxActiveClusters - cuOccupancyMaxActiveClusters.restype = CUresult - cuOccupancyMaxActiveClusters.argtypes = [ctypes.POINTER(ctypes.c_int32), CUfunction, ctypes.POINTER(struct_CUlaunchConfig_st)] -except AttributeError: - pass -try: - cuTexRefSetArray = _libraries['libcuda.so'].cuTexRefSetArray - cuTexRefSetArray.restype = CUresult - cuTexRefSetArray.argtypes = [CUtexref, CUarray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetMipmappedArray = _libraries['libcuda.so'].cuTexRefSetMipmappedArray - cuTexRefSetMipmappedArray.restype = CUresult - cuTexRefSetMipmappedArray.argtypes = [CUtexref, CUmipmappedArray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetAddress_v2 = _libraries['libcuda.so'].cuTexRefSetAddress_v2 - cuTexRefSetAddress_v2.restype = CUresult - cuTexRefSetAddress_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUtexref, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuTexRefSetAddress2D_v3 = _libraries['libcuda.so'].cuTexRefSetAddress2D_v3 - cuTexRefSetAddress2D_v3.restype = CUresult - cuTexRefSetAddress2D_v3.argtypes = [CUtexref, ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st), CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuTexRefSetFormat = _libraries['libcuda.so'].cuTexRefSetFormat - cuTexRefSetFormat.restype = CUresult - cuTexRefSetFormat.argtypes = [CUtexref, CUarray_format, ctypes.c_int32] -except AttributeError: - pass -try: - cuTexRefSetAddressMode = _libraries['libcuda.so'].cuTexRefSetAddressMode - cuTexRefSetAddressMode.restype = CUresult - cuTexRefSetAddressMode.argtypes = [CUtexref, ctypes.c_int32, CUaddress_mode] -except AttributeError: - pass -try: - cuTexRefSetFilterMode = _libraries['libcuda.so'].cuTexRefSetFilterMode - cuTexRefSetFilterMode.restype = CUresult - cuTexRefSetFilterMode.argtypes = [CUtexref, CUfilter_mode] -except AttributeError: - pass -try: - cuTexRefSetMipmapFilterMode = _libraries['libcuda.so'].cuTexRefSetMipmapFilterMode - cuTexRefSetMipmapFilterMode.restype = CUresult - cuTexRefSetMipmapFilterMode.argtypes = [CUtexref, CUfilter_mode] -except AttributeError: - pass -try: - cuTexRefSetMipmapLevelBias = _libraries['libcuda.so'].cuTexRefSetMipmapLevelBias - cuTexRefSetMipmapLevelBias.restype = CUresult - cuTexRefSetMipmapLevelBias.argtypes = [CUtexref, ctypes.c_float] -except AttributeError: - pass -try: - cuTexRefSetMipmapLevelClamp = _libraries['libcuda.so'].cuTexRefSetMipmapLevelClamp - cuTexRefSetMipmapLevelClamp.restype = CUresult - cuTexRefSetMipmapLevelClamp.argtypes = [CUtexref, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - cuTexRefSetMaxAnisotropy = _libraries['libcuda.so'].cuTexRefSetMaxAnisotropy - cuTexRefSetMaxAnisotropy.restype = CUresult - cuTexRefSetMaxAnisotropy.argtypes = [CUtexref, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetBorderColor = _libraries['libcuda.so'].cuTexRefSetBorderColor - cuTexRefSetBorderColor.restype = CUresult - cuTexRefSetBorderColor.argtypes = [CUtexref, ctypes.POINTER(ctypes.c_float)] -except AttributeError: - pass -try: - cuTexRefSetFlags = _libraries['libcuda.so'].cuTexRefSetFlags - cuTexRefSetFlags.restype = CUresult - cuTexRefSetFlags.argtypes = [CUtexref, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefGetAddress_v2 = _libraries['libcuda.so'].cuTexRefGetAddress_v2 - cuTexRefGetAddress_v2.restype = CUresult - cuTexRefGetAddress_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetArray = _libraries['libcuda.so'].cuTexRefGetArray - cuTexRefGetArray.restype = CUresult - cuTexRefGetArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmappedArray = _libraries['libcuda.so'].cuTexRefGetMipmappedArray - cuTexRefGetMipmappedArray.restype = CUresult - cuTexRefGetMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetAddressMode = _libraries['libcuda.so'].cuTexRefGetAddressMode - cuTexRefGetAddressMode.restype = CUresult - cuTexRefGetAddressMode.argtypes = [ctypes.POINTER(CUaddress_mode_enum), CUtexref, ctypes.c_int32] -except AttributeError: - pass -try: - cuTexRefGetFilterMode = _libraries['libcuda.so'].cuTexRefGetFilterMode - cuTexRefGetFilterMode.restype = CUresult - cuTexRefGetFilterMode.argtypes = [ctypes.POINTER(CUfilter_mode_enum), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetFormat = _libraries['libcuda.so'].cuTexRefGetFormat - cuTexRefGetFormat.restype = CUresult - cuTexRefGetFormat.argtypes = [ctypes.POINTER(CUarray_format_enum), ctypes.POINTER(ctypes.c_int32), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmapFilterMode = _libraries['libcuda.so'].cuTexRefGetMipmapFilterMode - cuTexRefGetMipmapFilterMode.restype = CUresult - cuTexRefGetMipmapFilterMode.argtypes = [ctypes.POINTER(CUfilter_mode_enum), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmapLevelBias = _libraries['libcuda.so'].cuTexRefGetMipmapLevelBias - cuTexRefGetMipmapLevelBias.restype = CUresult - cuTexRefGetMipmapLevelBias.argtypes = [ctypes.POINTER(ctypes.c_float), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMipmapLevelClamp = _libraries['libcuda.so'].cuTexRefGetMipmapLevelClamp - cuTexRefGetMipmapLevelClamp.restype = CUresult - cuTexRefGetMipmapLevelClamp.argtypes = [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(ctypes.c_float), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetMaxAnisotropy = _libraries['libcuda.so'].cuTexRefGetMaxAnisotropy - cuTexRefGetMaxAnisotropy.restype = CUresult - cuTexRefGetMaxAnisotropy.argtypes = [ctypes.POINTER(ctypes.c_int32), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetBorderColor = _libraries['libcuda.so'].cuTexRefGetBorderColor - cuTexRefGetBorderColor.restype = CUresult - cuTexRefGetBorderColor.argtypes = [ctypes.POINTER(ctypes.c_float), CUtexref] -except AttributeError: - pass -try: - cuTexRefGetFlags = _libraries['libcuda.so'].cuTexRefGetFlags - cuTexRefGetFlags.restype = CUresult - cuTexRefGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUtexref] -except AttributeError: - pass -try: - cuTexRefCreate = _libraries['libcuda.so'].cuTexRefCreate - cuTexRefCreate.restype = CUresult - cuTexRefCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUtexref_st))] -except AttributeError: - pass -try: - cuTexRefDestroy = _libraries['libcuda.so'].cuTexRefDestroy - cuTexRefDestroy.restype = CUresult - cuTexRefDestroy.argtypes = [CUtexref] -except AttributeError: - pass -try: - cuSurfRefSetArray = _libraries['libcuda.so'].cuSurfRefSetArray - cuSurfRefSetArray.restype = CUresult - cuSurfRefSetArray.argtypes = [CUsurfref, CUarray, ctypes.c_uint32] -except AttributeError: - pass -try: - cuSurfRefGetArray = _libraries['libcuda.so'].cuSurfRefGetArray - cuSurfRefGetArray.restype = CUresult - cuSurfRefGetArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUsurfref] -except AttributeError: - pass -try: - cuTexObjectCreate = _libraries['libcuda.so'].cuTexObjectCreate - cuTexObjectCreate.restype = CUresult - cuTexObjectCreate.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st), ctypes.POINTER(struct_CUDA_TEXTURE_DESC_st), ctypes.POINTER(struct_CUDA_RESOURCE_VIEW_DESC_st)] -except AttributeError: - pass -try: - cuTexObjectDestroy = _libraries['libcuda.so'].cuTexObjectDestroy - cuTexObjectDestroy.restype = CUresult - cuTexObjectDestroy.argtypes = [CUtexObject] -except AttributeError: - pass -try: - cuTexObjectGetResourceDesc = _libraries['libcuda.so'].cuTexObjectGetResourceDesc - cuTexObjectGetResourceDesc.restype = CUresult - cuTexObjectGetResourceDesc.argtypes = [ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st), CUtexObject] -except AttributeError: - pass -try: - cuTexObjectGetTextureDesc = _libraries['libcuda.so'].cuTexObjectGetTextureDesc - cuTexObjectGetTextureDesc.restype = CUresult - cuTexObjectGetTextureDesc.argtypes = [ctypes.POINTER(struct_CUDA_TEXTURE_DESC_st), CUtexObject] -except AttributeError: - pass -try: - cuTexObjectGetResourceViewDesc = _libraries['libcuda.so'].cuTexObjectGetResourceViewDesc - cuTexObjectGetResourceViewDesc.restype = CUresult - cuTexObjectGetResourceViewDesc.argtypes = [ctypes.POINTER(struct_CUDA_RESOURCE_VIEW_DESC_st), CUtexObject] -except AttributeError: - pass -try: - cuSurfObjectCreate = _libraries['libcuda.so'].cuSurfObjectCreate - cuSurfObjectCreate.restype = CUresult - cuSurfObjectCreate.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st)] -except AttributeError: - pass -try: - cuSurfObjectDestroy = _libraries['libcuda.so'].cuSurfObjectDestroy - cuSurfObjectDestroy.restype = CUresult - cuSurfObjectDestroy.argtypes = [CUsurfObject] -except AttributeError: - pass -try: - cuSurfObjectGetResourceDesc = _libraries['libcuda.so'].cuSurfObjectGetResourceDesc - cuSurfObjectGetResourceDesc.restype = CUresult - cuSurfObjectGetResourceDesc.argtypes = [ctypes.POINTER(struct_CUDA_RESOURCE_DESC_st), CUsurfObject] -except AttributeError: - pass -try: - cuTensorMapEncodeTiled = _libraries['libcuda.so'].cuTensorMapEncodeTiled - cuTensorMapEncodeTiled.restype = CUresult - cuTensorMapEncodeTiled.argtypes = [ctypes.POINTER(struct_CUtensorMap_st), CUtensorMapDataType, cuuint32_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUtensorMapInterleave, CUtensorMapSwizzle, CUtensorMapL2promotion, CUtensorMapFloatOOBfill] -except AttributeError: - pass -try: - cuTensorMapEncodeIm2col = _libraries['libcuda.so'].cuTensorMapEncodeIm2col - cuTensorMapEncodeIm2col.restype = CUresult - cuTensorMapEncodeIm2col.argtypes = [ctypes.POINTER(struct_CUtensorMap_st), CUtensorMapDataType, cuuint32_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), cuuint32_t, cuuint32_t, ctypes.POINTER(ctypes.c_uint32), CUtensorMapInterleave, CUtensorMapSwizzle, CUtensorMapL2promotion, CUtensorMapFloatOOBfill] -except AttributeError: - pass -try: - cuTensorMapReplaceAddress = _libraries['libcuda.so'].cuTensorMapReplaceAddress - cuTensorMapReplaceAddress.restype = CUresult - cuTensorMapReplaceAddress.argtypes = [ctypes.POINTER(struct_CUtensorMap_st), ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuDeviceCanAccessPeer = _libraries['libcuda.so'].cuDeviceCanAccessPeer - cuDeviceCanAccessPeer.restype = CUresult - cuDeviceCanAccessPeer.argtypes = [ctypes.POINTER(ctypes.c_int32), CUdevice, CUdevice] -except AttributeError: - pass -try: - cuCtxEnablePeerAccess = _libraries['libcuda.so'].cuCtxEnablePeerAccess - cuCtxEnablePeerAccess.restype = CUresult - cuCtxEnablePeerAccess.argtypes = [CUcontext, ctypes.c_uint32] -except AttributeError: - pass -try: - cuCtxDisablePeerAccess = _libraries['libcuda.so'].cuCtxDisablePeerAccess - cuCtxDisablePeerAccess.restype = CUresult - cuCtxDisablePeerAccess.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuDeviceGetP2PAttribute = _libraries['libcuda.so'].cuDeviceGetP2PAttribute - cuDeviceGetP2PAttribute.restype = CUresult - cuDeviceGetP2PAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), CUdevice_P2PAttribute, CUdevice, CUdevice] -except AttributeError: - pass -try: - cuGraphicsUnregisterResource = _libraries['libcuda.so'].cuGraphicsUnregisterResource - cuGraphicsUnregisterResource.restype = CUresult - cuGraphicsUnregisterResource.argtypes = [CUgraphicsResource] -except AttributeError: - pass -try: - cuGraphicsSubResourceGetMappedArray = _libraries['libcuda.so'].cuGraphicsSubResourceGetMappedArray - cuGraphicsSubResourceGetMappedArray.restype = CUresult - cuGraphicsSubResourceGetMappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), CUgraphicsResource, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphicsResourceGetMappedMipmappedArray = _libraries['libcuda.so'].cuGraphicsResourceGetMappedMipmappedArray - cuGraphicsResourceGetMappedMipmappedArray.restype = CUresult - cuGraphicsResourceGetMappedMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUmipmappedArray_st)), CUgraphicsResource] -except AttributeError: - pass -try: - cuGraphicsResourceGetMappedPointer_v2 = _libraries['libcuda.so'].cuGraphicsResourceGetMappedPointer_v2 - cuGraphicsResourceGetMappedPointer_v2.restype = CUresult - cuGraphicsResourceGetMappedPointer_v2.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), CUgraphicsResource] -except AttributeError: - pass -try: - cuGraphicsResourceSetMapFlags_v2 = _libraries['libcuda.so'].cuGraphicsResourceSetMapFlags_v2 - cuGraphicsResourceSetMapFlags_v2.restype = CUresult - cuGraphicsResourceSetMapFlags_v2.argtypes = [CUgraphicsResource, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphicsMapResources_ptsz = _libraries['libcuda.so'].cuGraphicsMapResources_ptsz - cuGraphicsMapResources_ptsz.restype = CUresult - cuGraphicsMapResources_ptsz.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuGraphicsUnmapResources_ptsz = _libraries['libcuda.so'].cuGraphicsUnmapResources_ptsz - cuGraphicsUnmapResources_ptsz.restype = CUresult - cuGraphicsUnmapResources_ptsz.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuGetProcAddress_v2 = _libraries['libcuda.so'].cuGetProcAddress_v2 - cuGetProcAddress_v2.restype = CUresult - cuGetProcAddress_v2.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_int32, cuuint64_t, ctypes.POINTER(CUdriverProcAddressQueryResult_enum)] -except AttributeError: - pass -try: - cuGetExportTable = _libraries['libcuda.so'].cuGetExportTable - cuGetExportTable.restype = CUresult - cuGetExportTable.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_CUuuid_st)] -except AttributeError: - pass -try: - cuMemHostRegister = _libraries['libcuda.so'].cuMemHostRegister - cuMemHostRegister.restype = CUresult - cuMemHostRegister.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphicsResourceSetMapFlags = _libraries['libcuda.so'].cuGraphicsResourceSetMapFlags - cuGraphicsResourceSetMapFlags.restype = CUresult - cuGraphicsResourceSetMapFlags.argtypes = [CUgraphicsResource, ctypes.c_uint32] -except AttributeError: - pass -try: - cuLinkCreate = _libraries['libcuda.so'].cuLinkCreate - cuLinkCreate.restype = CUresult - cuLinkCreate.argtypes = [ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(struct_CUlinkState_st))] -except AttributeError: - pass -try: - cuLinkAddData = _libraries['libcuda.so'].cuLinkAddData - cuLinkAddData.restype = CUresult - cuLinkAddData.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLinkAddFile = _libraries['libcuda.so'].cuLinkAddFile - cuLinkAddFile.restype = CUresult - cuLinkAddFile.argtypes = [CUlinkState, CUjitInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(CUjit_option_enum), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuTexRefSetAddress2D_v2 = _libraries['libcuda.so'].cuTexRefSetAddress2D_v2 - cuTexRefSetAddress2D_v2.restype = CUresult - cuTexRefSetAddress2D_v2.argtypes = [CUtexref, ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_st), CUdeviceptr, size_t] -except AttributeError: - pass CUdeviceptr_v1 = ctypes.c_uint32 -class struct_CUDA_MEMCPY2D_v1_st(Structure): - pass - -struct_CUDA_MEMCPY2D_v1_st._pack_ = 1 # source:False +class struct_CUDA_MEMCPY2D_v1_st(Struct): pass struct_CUDA_MEMCPY2D_v1_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint32), - ('srcY', ctypes.c_uint32), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('srcPitch', ctypes.c_uint32), - ('dstXInBytes', ctypes.c_uint32), - ('dstY', ctypes.c_uint32), - ('dstMemoryType', CUmemorytype), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('dstPitch', ctypes.c_uint32), - ('WidthInBytes', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), + ('srcXInBytes', ctypes.c_uint32), + ('srcY', ctypes.c_uint32), + ('srcMemoryType', CUmemorytype), + ('srcHost', ctypes.c_void_p), + ('srcDevice', CUdeviceptr_v1), + ('srcArray', CUarray), + ('srcPitch', ctypes.c_uint32), + ('dstXInBytes', ctypes.c_uint32), + ('dstY', ctypes.c_uint32), + ('dstMemoryType', CUmemorytype), + ('dstHost', ctypes.c_void_p), + ('dstDevice', CUdeviceptr_v1), + ('dstArray', CUarray), + ('dstPitch', ctypes.c_uint32), + ('WidthInBytes', ctypes.c_uint32), + ('Height', ctypes.c_uint32), ] - CUDA_MEMCPY2D_v1 = struct_CUDA_MEMCPY2D_v1_st -class struct_CUDA_MEMCPY3D_v1_st(Structure): - pass - -struct_CUDA_MEMCPY3D_v1_st._pack_ = 1 # source:False +class struct_CUDA_MEMCPY3D_v1_st(Struct): pass struct_CUDA_MEMCPY3D_v1_st._fields_ = [ - ('srcXInBytes', ctypes.c_uint32), - ('srcY', ctypes.c_uint32), - ('srcZ', ctypes.c_uint32), - ('srcLOD', ctypes.c_uint32), - ('srcMemoryType', CUmemorytype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('srcArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved0', ctypes.POINTER(None)), - ('srcPitch', ctypes.c_uint32), - ('srcHeight', ctypes.c_uint32), - ('dstXInBytes', ctypes.c_uint32), - ('dstY', ctypes.c_uint32), - ('dstZ', ctypes.c_uint32), - ('dstLOD', ctypes.c_uint32), - ('dstMemoryType', CUmemorytype), - ('PADDING_2', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), - ('dstArray', ctypes.POINTER(struct_CUarray_st)), - ('reserved1', ctypes.POINTER(None)), - ('dstPitch', ctypes.c_uint32), - ('dstHeight', ctypes.c_uint32), - ('WidthInBytes', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('Depth', ctypes.c_uint32), - ('PADDING_4', ctypes.c_ubyte * 4), + ('srcXInBytes', ctypes.c_uint32), + ('srcY', ctypes.c_uint32), + ('srcZ', ctypes.c_uint32), + ('srcLOD', ctypes.c_uint32), + ('srcMemoryType', CUmemorytype), + ('srcHost', ctypes.c_void_p), + ('srcDevice', CUdeviceptr_v1), + ('srcArray', CUarray), + ('reserved0', ctypes.c_void_p), + ('srcPitch', ctypes.c_uint32), + ('srcHeight', ctypes.c_uint32), + ('dstXInBytes', ctypes.c_uint32), + ('dstY', ctypes.c_uint32), + ('dstZ', ctypes.c_uint32), + ('dstLOD', ctypes.c_uint32), + ('dstMemoryType', CUmemorytype), + ('dstHost', ctypes.c_void_p), + ('dstDevice', CUdeviceptr_v1), + ('dstArray', CUarray), + ('reserved1', ctypes.c_void_p), + ('dstPitch', ctypes.c_uint32), + ('dstHeight', ctypes.c_uint32), + ('WidthInBytes', ctypes.c_uint32), + ('Height', ctypes.c_uint32), + ('Depth', ctypes.c_uint32), ] - CUDA_MEMCPY3D_v1 = struct_CUDA_MEMCPY3D_v1_st -class struct_CUDA_ARRAY_DESCRIPTOR_v1_st(Structure): - pass - -struct_CUDA_ARRAY_DESCRIPTOR_v1_st._pack_ = 1 # source:False +class struct_CUDA_ARRAY_DESCRIPTOR_v1_st(Struct): pass struct_CUDA_ARRAY_DESCRIPTOR_v1_st._fields_ = [ - ('Width', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), + ('Width', ctypes.c_uint32), + ('Height', ctypes.c_uint32), + ('Format', CUarray_format), + ('NumChannels', ctypes.c_uint32), ] - CUDA_ARRAY_DESCRIPTOR_v1 = struct_CUDA_ARRAY_DESCRIPTOR_v1_st -class struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st(Structure): - pass - -struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st._pack_ = 1 # source:False +class struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st(Struct): pass struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st._fields_ = [ - ('Width', ctypes.c_uint32), - ('Height', ctypes.c_uint32), - ('Depth', ctypes.c_uint32), - ('Format', CUarray_format), - ('NumChannels', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), + ('Width', ctypes.c_uint32), + ('Height', ctypes.c_uint32), + ('Depth', ctypes.c_uint32), + ('Format', CUarray_format), + ('NumChannels', ctypes.c_uint32), + ('Flags', ctypes.c_uint32), ] - CUDA_ARRAY3D_DESCRIPTOR_v1 = struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st -try: - cuDeviceTotalMem = _libraries['libcuda.so'].cuDeviceTotalMem - cuDeviceTotalMem.restype = CUresult - cuDeviceTotalMem.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUdevice] -except AttributeError: - pass -try: - cuCtxCreate = _libraries['libcuda.so'].cuCtxCreate - cuCtxCreate.restype = CUresult - cuCtxCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st)), ctypes.c_uint32, CUdevice] -except AttributeError: - pass -try: - cuModuleGetGlobal = _libraries['libcuda.so'].cuModuleGetGlobal - cuModuleGetGlobal.restype = CUresult - cuModuleGetGlobal.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUmodule, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - cuMemGetInfo = _libraries['libcuda.so'].cuMemGetInfo - cuMemGetInfo.restype = CUresult - cuMemGetInfo.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuMemAlloc = _libraries['libcuda.so'].cuMemAlloc - cuMemAlloc.restype = CUresult - cuMemAlloc.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemAllocPitch = _libraries['libcuda.so'].cuMemAllocPitch - cuMemAllocPitch.restype = CUresult - cuMemAllocPitch.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemFree = _libraries['libcuda.so'].cuMemFree - cuMemFree.restype = CUresult - cuMemFree.argtypes = [CUdeviceptr_v1] -except AttributeError: - pass -try: - cuMemGetAddressRange = _libraries['libcuda.so'].cuMemGetAddressRange - cuMemGetAddressRange.restype = CUresult - cuMemGetAddressRange.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUdeviceptr_v1] -except AttributeError: - pass -try: - cuMemAllocHost = _libraries['libcuda.so'].cuMemAllocHost - cuMemAllocHost.restype = CUresult - cuMemAllocHost.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemHostGetDevicePointer = _libraries['libcuda.so'].cuMemHostGetDevicePointer - cuMemHostGetDevicePointer.restype = CUresult - cuMemHostGetDevicePointer.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoD = _libraries['libcuda.so'].cuMemcpyHtoD - cuMemcpyHtoD.restype = CUresult - cuMemcpyHtoD.argtypes = [CUdeviceptr_v1, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyDtoH = _libraries['libcuda.so'].cuMemcpyDtoH - cuMemcpyDtoH.restype = CUresult - cuMemcpyDtoH.argtypes = [ctypes.POINTER(None), CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyDtoD = _libraries['libcuda.so'].cuMemcpyDtoD - cuMemcpyDtoD.restype = CUresult - cuMemcpyDtoD.argtypes = [CUdeviceptr_v1, CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyDtoA = _libraries['libcuda.so'].cuMemcpyDtoA - cuMemcpyDtoA.restype = CUresult - cuMemcpyDtoA.argtypes = [CUarray, ctypes.c_uint32, CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyAtoD = _libraries['libcuda.so'].cuMemcpyAtoD - cuMemcpyAtoD.restype = CUresult - cuMemcpyAtoD.argtypes = [CUdeviceptr_v1, CUarray, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoA = _libraries['libcuda.so'].cuMemcpyHtoA - cuMemcpyHtoA.restype = CUresult - cuMemcpyHtoA.argtypes = [CUarray, ctypes.c_uint32, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyAtoH = _libraries['libcuda.so'].cuMemcpyAtoH - cuMemcpyAtoH.restype = CUresult - cuMemcpyAtoH.argtypes = [ctypes.POINTER(None), CUarray, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyAtoA = _libraries['libcuda.so'].cuMemcpyAtoA - cuMemcpyAtoA.restype = CUresult - cuMemcpyAtoA.argtypes = [CUarray, ctypes.c_uint32, CUarray, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoAAsync = _libraries['libcuda.so'].cuMemcpyHtoAAsync - cuMemcpyHtoAAsync.restype = CUresult - cuMemcpyHtoAAsync.argtypes = [CUarray, ctypes.c_uint32, ctypes.POINTER(None), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpyAtoHAsync = _libraries['libcuda.so'].cuMemcpyAtoHAsync - cuMemcpyAtoHAsync.restype = CUresult - cuMemcpyAtoHAsync.argtypes = [ctypes.POINTER(None), CUarray, ctypes.c_uint32, ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpy2D = _libraries['libcuda.so'].cuMemcpy2D - cuMemcpy2D.restype = CUresult - cuMemcpy2D.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_v1_st)] -except AttributeError: - pass -try: - cuMemcpy2DUnaligned = _libraries['libcuda.so'].cuMemcpy2DUnaligned - cuMemcpy2DUnaligned.restype = CUresult - cuMemcpy2DUnaligned.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_v1_st)] -except AttributeError: - pass -try: - cuMemcpy3D = _libraries['libcuda.so'].cuMemcpy3D - cuMemcpy3D.restype = CUresult - cuMemcpy3D.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_v1_st)] -except AttributeError: - pass -try: - cuMemcpyHtoDAsync = _libraries['libcuda.so'].cuMemcpyHtoDAsync - cuMemcpyHtoDAsync.restype = CUresult - cuMemcpyHtoDAsync.argtypes = [CUdeviceptr_v1, ctypes.POINTER(None), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoHAsync = _libraries['libcuda.so'].cuMemcpyDtoHAsync - cuMemcpyDtoHAsync.restype = CUresult - cuMemcpyDtoHAsync.argtypes = [ctypes.POINTER(None), CUdeviceptr_v1, ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoDAsync = _libraries['libcuda.so'].cuMemcpyDtoDAsync - cuMemcpyDtoDAsync.restype = CUresult - cuMemcpyDtoDAsync.argtypes = [CUdeviceptr_v1, CUdeviceptr_v1, ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemcpy2DAsync = _libraries['libcuda.so'].cuMemcpy2DAsync - cuMemcpy2DAsync.restype = CUresult - cuMemcpy2DAsync.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_v1_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DAsync = _libraries['libcuda.so'].cuMemcpy3DAsync - cuMemcpy3DAsync.restype = CUresult - cuMemcpy3DAsync.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_v1_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8 = _libraries['libcuda.so'].cuMemsetD8 - cuMemsetD8.restype = CUresult - cuMemsetD8.argtypes = [CUdeviceptr_v1, ctypes.c_ubyte, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD16 = _libraries['libcuda.so'].cuMemsetD16 - cuMemsetD16.restype = CUresult - cuMemsetD16.argtypes = [CUdeviceptr_v1, ctypes.c_uint16, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD32 = _libraries['libcuda.so'].cuMemsetD32 - cuMemsetD32.restype = CUresult - cuMemsetD32.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD2D8 = _libraries['libcuda.so'].cuMemsetD2D8 - cuMemsetD2D8.restype = CUresult - cuMemsetD2D8.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_ubyte, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD2D16 = _libraries['libcuda.so'].cuMemsetD2D16 - cuMemsetD2D16.restype = CUresult - cuMemsetD2D16.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint16, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemsetD2D32 = _libraries['libcuda.so'].cuMemsetD2D32 - cuMemsetD2D32.restype = CUresult - cuMemsetD2D32.argtypes = [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - cuArrayCreate = _libraries['libcuda.so'].cuArrayCreate - cuArrayCreate.restype = CUresult - cuArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_v1_st)] -except AttributeError: - pass -try: - cuArrayGetDescriptor = _libraries['libcuda.so'].cuArrayGetDescriptor - cuArrayGetDescriptor.restype = CUresult - cuArrayGetDescriptor.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_v1_st), CUarray] -except AttributeError: - pass -try: - cuArray3DCreate = _libraries['libcuda.so'].cuArray3DCreate - cuArray3DCreate.restype = CUresult - cuArray3DCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUarray_st)), ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st)] -except AttributeError: - pass -try: - cuArray3DGetDescriptor = _libraries['libcuda.so'].cuArray3DGetDescriptor - cuArray3DGetDescriptor.restype = CUresult - cuArray3DGetDescriptor.argtypes = [ctypes.POINTER(struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st), CUarray] -except AttributeError: - pass -try: - cuTexRefSetAddress = _libraries['libcuda.so'].cuTexRefSetAddress - cuTexRefSetAddress.restype = CUresult - cuTexRefSetAddress.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUtexref, CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefSetAddress2D = _libraries['libcuda.so'].cuTexRefSetAddress2D - cuTexRefSetAddress2D.restype = CUresult - cuTexRefSetAddress2D.argtypes = [CUtexref, ctypes.POINTER(struct_CUDA_ARRAY_DESCRIPTOR_v1_st), CUdeviceptr_v1, ctypes.c_uint32] -except AttributeError: - pass -try: - cuTexRefGetAddress = _libraries['libcuda.so'].cuTexRefGetAddress - cuTexRefGetAddress.restype = CUresult - cuTexRefGetAddress.argtypes = [ctypes.POINTER(ctypes.c_uint32), CUtexref] -except AttributeError: - pass -try: - cuGraphicsResourceGetMappedPointer = _libraries['libcuda.so'].cuGraphicsResourceGetMappedPointer - cuGraphicsResourceGetMappedPointer.restype = CUresult - cuGraphicsResourceGetMappedPointer.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), CUgraphicsResource] -except AttributeError: - pass -try: - cuCtxDestroy = _libraries['libcuda.so'].cuCtxDestroy - cuCtxDestroy.restype = CUresult - cuCtxDestroy.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuCtxPopCurrent = _libraries['libcuda.so'].cuCtxPopCurrent - cuCtxPopCurrent.restype = CUresult - cuCtxPopCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuCtxPushCurrent = _libraries['libcuda.so'].cuCtxPushCurrent - cuCtxPushCurrent.restype = CUresult - cuCtxPushCurrent.argtypes = [CUcontext] -except AttributeError: - pass -try: - cuStreamDestroy = _libraries['libcuda.so'].cuStreamDestroy - cuStreamDestroy.restype = CUresult - cuStreamDestroy.argtypes = [CUstream] -except AttributeError: - pass -try: - cuEventDestroy = _libraries['libcuda.so'].cuEventDestroy - cuEventDestroy.restype = CUresult - cuEventDestroy.argtypes = [CUevent] -except AttributeError: - pass -try: - cuDevicePrimaryCtxRelease = _libraries['libcuda.so'].cuDevicePrimaryCtxRelease - cuDevicePrimaryCtxRelease.restype = CUresult - cuDevicePrimaryCtxRelease.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxReset = _libraries['libcuda.so'].cuDevicePrimaryCtxReset - cuDevicePrimaryCtxReset.restype = CUresult - cuDevicePrimaryCtxReset.argtypes = [CUdevice] -except AttributeError: - pass -try: - cuDevicePrimaryCtxSetFlags = _libraries['libcuda.so'].cuDevicePrimaryCtxSetFlags - cuDevicePrimaryCtxSetFlags.restype = CUresult - cuDevicePrimaryCtxSetFlags.argtypes = [CUdevice, ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemcpyHtoD_v2 = _libraries['libcuda.so'].cuMemcpyHtoD_v2 - cuMemcpyHtoD_v2.restype = CUresult - cuMemcpyHtoD_v2.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyDtoH_v2 = _libraries['libcuda.so'].cuMemcpyDtoH_v2 - cuMemcpyDtoH_v2.restype = CUresult - cuMemcpyDtoH_v2.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoD_v2 = _libraries['libcuda.so'].cuMemcpyDtoD_v2 - cuMemcpyDtoD_v2.restype = CUresult - cuMemcpyDtoD_v2.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyDtoA_v2 = _libraries['libcuda.so'].cuMemcpyDtoA_v2 - cuMemcpyDtoA_v2.restype = CUresult - cuMemcpyDtoA_v2.argtypes = [CUarray, size_t, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoD_v2 = _libraries['libcuda.so'].cuMemcpyAtoD_v2 - cuMemcpyAtoD_v2.restype = CUresult - cuMemcpyAtoD_v2.argtypes = [CUdeviceptr, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoA_v2 = _libraries['libcuda.so'].cuMemcpyHtoA_v2 - cuMemcpyHtoA_v2.restype = CUresult - cuMemcpyHtoA_v2.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - cuMemcpyAtoH_v2 = _libraries['libcuda.so'].cuMemcpyAtoH_v2 - cuMemcpyAtoH_v2.restype = CUresult - cuMemcpyAtoH_v2.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyAtoA_v2 = _libraries['libcuda.so'].cuMemcpyAtoA_v2 - cuMemcpyAtoA_v2.restype = CUresult - cuMemcpyAtoA_v2.argtypes = [CUarray, size_t, CUarray, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpyHtoAAsync_v2 = _libraries['libcuda.so'].cuMemcpyHtoAAsync_v2 - cuMemcpyHtoAAsync_v2.restype = CUresult - cuMemcpyHtoAAsync_v2.argtypes = [CUarray, size_t, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyAtoHAsync_v2 = _libraries['libcuda.so'].cuMemcpyAtoHAsync_v2 - cuMemcpyAtoHAsync_v2.restype = CUresult - cuMemcpyAtoHAsync_v2.argtypes = [ctypes.POINTER(None), CUarray, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy2D_v2 = _libraries['libcuda.so'].cuMemcpy2D_v2 - cuMemcpy2D_v2.restype = CUresult - cuMemcpy2D_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy2DUnaligned_v2 = _libraries['libcuda.so'].cuMemcpy2DUnaligned_v2 - cuMemcpy2DUnaligned_v2.restype = CUresult - cuMemcpy2DUnaligned_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st)] -except AttributeError: - pass -try: - cuMemcpy3D_v2 = _libraries['libcuda.so'].cuMemcpy3D_v2 - cuMemcpy3D_v2.restype = CUresult - cuMemcpy3D_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st)] -except AttributeError: - pass -try: - cuMemcpyHtoDAsync_v2 = _libraries['libcuda.so'].cuMemcpyHtoDAsync_v2 - cuMemcpyHtoDAsync_v2.restype = CUresult - cuMemcpyHtoDAsync_v2.argtypes = [CUdeviceptr, ctypes.POINTER(None), size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoHAsync_v2 = _libraries['libcuda.so'].cuMemcpyDtoHAsync_v2 - cuMemcpyDtoHAsync_v2.restype = CUresult - cuMemcpyDtoHAsync_v2.argtypes = [ctypes.POINTER(None), CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyDtoDAsync_v2 = _libraries['libcuda.so'].cuMemcpyDtoDAsync_v2 - cuMemcpyDtoDAsync_v2.restype = CUresult - cuMemcpyDtoDAsync_v2.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy2DAsync_v2 = _libraries['libcuda.so'].cuMemcpy2DAsync_v2 - cuMemcpy2DAsync_v2.restype = CUresult - cuMemcpy2DAsync_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY2D_st), CUstream] -except AttributeError: - pass -try: - cuMemcpy3DAsync_v2 = _libraries['libcuda.so'].cuMemcpy3DAsync_v2 - cuMemcpy3DAsync_v2.restype = CUresult - cuMemcpy3DAsync_v2.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8_v2 = _libraries['libcuda.so'].cuMemsetD8_v2 - cuMemsetD8_v2.restype = CUresult - cuMemsetD8_v2.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t] -except AttributeError: - pass -try: - cuMemsetD16_v2 = _libraries['libcuda.so'].cuMemsetD16_v2 - cuMemsetD16_v2.restype = CUresult - cuMemsetD16_v2.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t] -except AttributeError: - pass -try: - cuMemsetD32_v2 = _libraries['libcuda.so'].cuMemsetD32_v2 - cuMemsetD32_v2.restype = CUresult - cuMemsetD32_v2.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t] -except AttributeError: - pass -try: - cuMemsetD2D8_v2 = _libraries['libcuda.so'].cuMemsetD2D8_v2 - cuMemsetD2D8_v2.restype = CUresult - cuMemsetD2D8_v2.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D16_v2 = _libraries['libcuda.so'].cuMemsetD2D16_v2 - cuMemsetD2D16_v2.restype = CUresult - cuMemsetD2D16_v2.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t] -except AttributeError: - pass -try: - cuMemsetD2D32_v2 = _libraries['libcuda.so'].cuMemsetD2D32_v2 - cuMemsetD2D32_v2.restype = CUresult - cuMemsetD2D32_v2.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t] -except AttributeError: - pass -try: - cuMemcpy = _libraries['libcuda.so'].cuMemcpy - cuMemcpy.restype = CUresult - cuMemcpy.argtypes = [CUdeviceptr, CUdeviceptr, size_t] -except AttributeError: - pass -try: - cuMemcpyAsync = _libraries['libcuda.so'].cuMemcpyAsync - cuMemcpyAsync.restype = CUresult - cuMemcpyAsync.argtypes = [CUdeviceptr, CUdeviceptr, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpyPeer = _libraries['libcuda.so'].cuMemcpyPeer - cuMemcpyPeer.restype = CUresult - cuMemcpyPeer.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t] -except AttributeError: - pass -try: - cuMemcpyPeerAsync = _libraries['libcuda.so'].cuMemcpyPeerAsync - cuMemcpyPeerAsync.restype = CUresult - cuMemcpyPeerAsync.argtypes = [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t, CUstream] -except AttributeError: - pass -try: - cuMemcpy3DPeer = _libraries['libcuda.so'].cuMemcpy3DPeer - cuMemcpy3DPeer.restype = CUresult - cuMemcpy3DPeer.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st)] -except AttributeError: - pass -try: - cuMemcpy3DPeerAsync = _libraries['libcuda.so'].cuMemcpy3DPeerAsync - cuMemcpy3DPeerAsync.restype = CUresult - cuMemcpy3DPeerAsync.argtypes = [ctypes.POINTER(struct_CUDA_MEMCPY3D_PEER_st), CUstream] -except AttributeError: - pass -try: - cuMemsetD8Async = _libraries['libcuda.so'].cuMemsetD8Async - cuMemsetD8Async.restype = CUresult - cuMemsetD8Async.argtypes = [CUdeviceptr, ctypes.c_ubyte, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD16Async = _libraries['libcuda.so'].cuMemsetD16Async - cuMemsetD16Async.restype = CUresult - cuMemsetD16Async.argtypes = [CUdeviceptr, ctypes.c_uint16, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD32Async = _libraries['libcuda.so'].cuMemsetD32Async - cuMemsetD32Async.restype = CUresult - cuMemsetD32Async.argtypes = [CUdeviceptr, ctypes.c_uint32, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D8Async = _libraries['libcuda.so'].cuMemsetD2D8Async - cuMemsetD2D8Async.restype = CUresult - cuMemsetD2D8Async.argtypes = [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D16Async = _libraries['libcuda.so'].cuMemsetD2D16Async - cuMemsetD2D16Async.restype = CUresult - cuMemsetD2D16Async.argtypes = [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuMemsetD2D32Async = _libraries['libcuda.so'].cuMemsetD2D32Async - cuMemsetD2D32Async.restype = CUresult - cuMemsetD2D32Async.argtypes = [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t, CUstream] -except AttributeError: - pass -try: - cuStreamGetPriority = _libraries['libcuda.so'].cuStreamGetPriority - cuStreamGetPriority.restype = CUresult - cuStreamGetPriority.argtypes = [CUstream, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - cuStreamGetId = _libraries['libcuda.so'].cuStreamGetId - cuStreamGetId.restype = CUresult - cuStreamGetId.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetFlags = _libraries['libcuda.so'].cuStreamGetFlags - cuStreamGetFlags.restype = CUresult - cuStreamGetFlags.argtypes = [CUstream, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - cuStreamGetCtx = _libraries['libcuda.so'].cuStreamGetCtx - cuStreamGetCtx.restype = CUresult - cuStreamGetCtx.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUctx_st))] -except AttributeError: - pass -try: - cuStreamWaitEvent = _libraries['libcuda.so'].cuStreamWaitEvent - cuStreamWaitEvent.restype = CUresult - cuStreamWaitEvent.argtypes = [CUstream, CUevent, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAddCallback = _libraries['libcuda.so'].cuStreamAddCallback - cuStreamAddCallback.restype = CUresult - cuStreamAddCallback.argtypes = [CUstream, CUstreamCallback, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamAttachMemAsync = _libraries['libcuda.so'].cuStreamAttachMemAsync - cuStreamAttachMemAsync.restype = CUresult - cuStreamAttachMemAsync.argtypes = [CUstream, CUdeviceptr, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamQuery = _libraries['libcuda.so'].cuStreamQuery - cuStreamQuery.restype = CUresult - cuStreamQuery.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamSynchronize = _libraries['libcuda.so'].cuStreamSynchronize - cuStreamSynchronize.restype = CUresult - cuStreamSynchronize.argtypes = [CUstream] -except AttributeError: - pass -try: - cuEventRecord = _libraries['libcuda.so'].cuEventRecord - cuEventRecord.restype = CUresult - cuEventRecord.argtypes = [CUevent, CUstream] -except AttributeError: - pass -try: - cuEventRecordWithFlags = _libraries['libcuda.so'].cuEventRecordWithFlags - cuEventRecordWithFlags.restype = CUresult - cuEventRecordWithFlags.argtypes = [CUevent, CUstream, ctypes.c_uint32] -except AttributeError: - pass -try: - cuLaunchKernel = _libraries['libcuda.so'].cuLaunchKernel - cuLaunchKernel.restype = CUresult - cuLaunchKernel.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchKernelEx = _libraries['libcuda.so'].cuLaunchKernelEx - cuLaunchKernelEx.restype = CUresult - cuLaunchKernelEx.argtypes = [ctypes.POINTER(struct_CUlaunchConfig_st), CUfunction, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuLaunchHostFunc = _libraries['libcuda.so'].cuLaunchHostFunc - cuLaunchHostFunc.restype = CUresult - cuLaunchHostFunc.argtypes = [CUstream, CUhostFn, ctypes.POINTER(None)] -except AttributeError: - pass -try: - cuGraphicsMapResources = _libraries['libcuda.so'].cuGraphicsMapResources - cuGraphicsMapResources.restype = CUresult - cuGraphicsMapResources.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuGraphicsUnmapResources = _libraries['libcuda.so'].cuGraphicsUnmapResources - cuGraphicsUnmapResources.restype = CUresult - cuGraphicsUnmapResources.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_CUgraphicsResource_st)), CUstream] -except AttributeError: - pass -try: - cuStreamWriteValue32 = _libraries['libcuda.so'].cuStreamWriteValue32 - cuStreamWriteValue32.restype = CUresult - cuStreamWriteValue32.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue32 = _libraries['libcuda.so'].cuStreamWaitValue32 - cuStreamWaitValue32.restype = CUresult - cuStreamWaitValue32.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64 = _libraries['libcuda.so'].cuStreamWriteValue64 - cuStreamWriteValue64.restype = CUresult - cuStreamWriteValue64.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64 = _libraries['libcuda.so'].cuStreamWaitValue64 - cuStreamWaitValue64.restype = CUresult - cuStreamWaitValue64.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp = _libraries['libcuda.so'].cuStreamBatchMemOp - cuStreamBatchMemOp.restype = CUresult - cuStreamBatchMemOp.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue32_ptsz = _libraries['libcuda.so'].cuStreamWriteValue32_ptsz - cuStreamWriteValue32_ptsz.restype = CUresult - cuStreamWriteValue32_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue32_ptsz = _libraries['libcuda.so'].cuStreamWaitValue32_ptsz - cuStreamWaitValue32_ptsz.restype = CUresult - cuStreamWaitValue32_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64_ptsz = _libraries['libcuda.so'].cuStreamWriteValue64_ptsz - cuStreamWriteValue64_ptsz.restype = CUresult - cuStreamWriteValue64_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64_ptsz = _libraries['libcuda.so'].cuStreamWaitValue64_ptsz - cuStreamWaitValue64_ptsz.restype = CUresult - cuStreamWaitValue64_ptsz.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp_ptsz = _libraries['libcuda.so'].cuStreamBatchMemOp_ptsz - cuStreamBatchMemOp_ptsz.restype = CUresult - cuStreamBatchMemOp_ptsz.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue32_v2 = _libraries['libcuda.so'].cuStreamWriteValue32_v2 - cuStreamWriteValue32_v2.restype = CUresult - cuStreamWriteValue32_v2.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue32_v2 = _libraries['libcuda.so'].cuStreamWaitValue32_v2 - cuStreamWaitValue32_v2.restype = CUresult - cuStreamWaitValue32_v2.argtypes = [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWriteValue64_v2 = _libraries['libcuda.so'].cuStreamWriteValue64_v2 - cuStreamWriteValue64_v2.restype = CUresult - cuStreamWriteValue64_v2.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamWaitValue64_v2 = _libraries['libcuda.so'].cuStreamWaitValue64_v2 - cuStreamWaitValue64_v2.restype = CUresult - cuStreamWaitValue64_v2.argtypes = [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuStreamBatchMemOp_v2 = _libraries['libcuda.so'].cuStreamBatchMemOp_v2 - cuStreamBatchMemOp_v2.restype = CUresult - cuStreamBatchMemOp_v2.argtypes = [CUstream, ctypes.c_uint32, ctypes.POINTER(union_CUstreamBatchMemOpParams_union), ctypes.c_uint32] -except AttributeError: - pass -try: - cuMemPrefetchAsync = _libraries['libcuda.so'].cuMemPrefetchAsync - cuMemPrefetchAsync.restype = CUresult - cuMemPrefetchAsync.argtypes = [CUdeviceptr, size_t, CUdevice, CUstream] -except AttributeError: - pass -try: - cuLaunchCooperativeKernel = _libraries['libcuda.so'].cuLaunchCooperativeKernel - cuLaunchCooperativeKernel.restype = CUresult - cuLaunchCooperativeKernel.argtypes = [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - cuSignalExternalSemaphoresAsync = _libraries['libcuda.so'].cuSignalExternalSemaphoresAsync - cuSignalExternalSemaphoresAsync.restype = CUresult - cuSignalExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuWaitExternalSemaphoresAsync = _libraries['libcuda.so'].cuWaitExternalSemaphoresAsync - cuWaitExternalSemaphoresAsync.restype = CUresult - cuWaitExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUextSemaphore_st)), ctypes.POINTER(struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuStreamBeginCapture = _libraries['libcuda.so'].cuStreamBeginCapture - cuStreamBeginCapture.restype = CUresult - cuStreamBeginCapture.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamBeginCapture_ptsz = _libraries['libcuda.so'].cuStreamBeginCapture_ptsz - cuStreamBeginCapture_ptsz.restype = CUresult - cuStreamBeginCapture_ptsz.argtypes = [CUstream] -except AttributeError: - pass -try: - cuStreamBeginCapture_v2 = _libraries['libcuda.so'].cuStreamBeginCapture_v2 - cuStreamBeginCapture_v2.restype = CUresult - cuStreamBeginCapture_v2.argtypes = [CUstream, CUstreamCaptureMode] -except AttributeError: - pass -try: - cuStreamEndCapture = _libraries['libcuda.so'].cuStreamEndCapture - cuStreamEndCapture.restype = CUresult - cuStreamEndCapture.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st))] -except AttributeError: - pass -try: - cuStreamIsCapturing = _libraries['libcuda.so'].cuStreamIsCapturing - cuStreamIsCapturing.restype = CUresult - cuStreamIsCapturing.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo = _libraries['libcuda.so'].cuStreamGetCaptureInfo - cuStreamGetCaptureInfo.restype = CUresult - cuStreamGetCaptureInfo.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo_ptsz = _libraries['libcuda.so'].cuStreamGetCaptureInfo_ptsz - cuStreamGetCaptureInfo_ptsz.restype = CUresult - cuStreamGetCaptureInfo_ptsz.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuStreamGetCaptureInfo_v2 = _libraries['libcuda.so'].cuStreamGetCaptureInfo_v2 - cuStreamGetCaptureInfo_v2.restype = CUresult - cuStreamGetCaptureInfo_v2.argtypes = [CUstream, ctypes.POINTER(CUstreamCaptureStatus_enum), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_CUgraph_st)), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st))), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - cuGraphAddKernelNode = _libraries['libcuda.so'].cuGraphAddKernelNode - cuGraphAddKernelNode.restype = CUresult - cuGraphAddKernelNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeGetParams = _libraries['libcuda.so'].cuGraphKernelNodeGetParams - cuGraphKernelNodeGetParams.restype = CUresult - cuGraphKernelNodeGetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphKernelNodeSetParams = _libraries['libcuda.so'].cuGraphKernelNodeSetParams - cuGraphKernelNodeSetParams.restype = CUresult - cuGraphKernelNodeSetParams.argtypes = [CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecKernelNodeSetParams = _libraries['libcuda.so'].cuGraphExecKernelNodeSetParams - cuGraphExecKernelNodeSetParams.restype = CUresult - cuGraphExecKernelNodeSetParams.argtypes = [CUgraphExec, CUgraphNode, ctypes.POINTER(struct_CUDA_KERNEL_NODE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphInstantiateWithParams = _libraries['libcuda.so'].cuGraphInstantiateWithParams - cuGraphInstantiateWithParams.restype = CUresult - cuGraphInstantiateWithParams.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st)] -except AttributeError: - pass -try: - cuGraphExecUpdate = _libraries['libcuda.so'].cuGraphExecUpdate - cuGraphExecUpdate.restype = CUresult - cuGraphExecUpdate.argtypes = [CUgraphExec, CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(CUgraphExecUpdateResult_enum)] -except AttributeError: - pass -try: - cuGraphUpload = _libraries['libcuda.so'].cuGraphUpload - cuGraphUpload.restype = CUresult - cuGraphUpload.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuGraphLaunch = _libraries['libcuda.so'].cuGraphLaunch - cuGraphLaunch.restype = CUresult - cuGraphLaunch.argtypes = [CUgraphExec, CUstream] -except AttributeError: - pass -try: - cuStreamCopyAttributes = _libraries['libcuda.so'].cuStreamCopyAttributes - cuStreamCopyAttributes.restype = CUresult - cuStreamCopyAttributes.argtypes = [CUstream, CUstream] -except AttributeError: - pass -try: - cuStreamGetAttribute = _libraries['libcuda.so'].cuStreamGetAttribute - cuStreamGetAttribute.restype = CUresult - cuStreamGetAttribute.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuStreamSetAttribute = _libraries['libcuda.so'].cuStreamSetAttribute - cuStreamSetAttribute.restype = CUresult - cuStreamSetAttribute.argtypes = [CUstream, CUstreamAttrID, ctypes.POINTER(union_CUlaunchAttributeValue_union)] -except AttributeError: - pass -try: - cuIpcOpenMemHandle = _libraries['libcuda.so'].cuIpcOpenMemHandle - cuIpcOpenMemHandle.restype = CUresult - cuIpcOpenMemHandle.argtypes = [ctypes.POINTER(ctypes.c_uint64), CUipcMemHandle, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGraphInstantiate = _libraries['libcuda.so'].cuGraphInstantiate - cuGraphInstantiate.restype = CUresult - cuGraphInstantiate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - cuGraphInstantiate_v2 = _libraries['libcuda.so'].cuGraphInstantiate_v2 - cuGraphInstantiate_v2.restype = CUresult - cuGraphInstantiate_v2.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_CUgraphExec_st)), CUgraph, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - cuMemMapArrayAsync = _libraries['libcuda.so'].cuMemMapArrayAsync - cuMemMapArrayAsync.restype = CUresult - cuMemMapArrayAsync.argtypes = [ctypes.POINTER(struct_CUarrayMapInfo_st), ctypes.c_uint32, CUstream] -except AttributeError: - pass -try: - cuMemFreeAsync = _libraries['libcuda.so'].cuMemFreeAsync - cuMemFreeAsync.restype = CUresult - cuMemFreeAsync.argtypes = [CUdeviceptr, CUstream] -except AttributeError: - pass -try: - cuMemAllocAsync = _libraries['libcuda.so'].cuMemAllocAsync - cuMemAllocAsync.restype = CUresult - cuMemAllocAsync.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUstream] -except AttributeError: - pass -try: - cuMemAllocFromPoolAsync = _libraries['libcuda.so'].cuMemAllocFromPoolAsync - cuMemAllocFromPoolAsync.restype = CUresult - cuMemAllocFromPoolAsync.argtypes = [ctypes.POINTER(ctypes.c_uint64), size_t, CUmemoryPool, CUstream] -except AttributeError: - pass -try: - cuStreamUpdateCaptureDependencies = _libraries['libcuda.so'].cuStreamUpdateCaptureDependencies - cuStreamUpdateCaptureDependencies.restype = CUresult - cuStreamUpdateCaptureDependencies.argtypes = [CUstream, ctypes.POINTER(ctypes.POINTER(struct_CUgraphNode_st)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - cuGetProcAddress = _libraries['libcuda.so'].cuGetProcAddress - cuGetProcAddress.restype = CUresult - cuGetProcAddress.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_int32, cuuint64_t] -except AttributeError: - pass -__all__ = \ - ['CUDA_ARRAY3D_DESCRIPTOR', 'CUDA_ARRAY3D_DESCRIPTOR_v1', - 'CUDA_ARRAY3D_DESCRIPTOR_v2', 'CUDA_ARRAY_DESCRIPTOR', - 'CUDA_ARRAY_DESCRIPTOR_v1', 'CUDA_ARRAY_DESCRIPTOR_v2', - 'CUDA_ARRAY_MEMORY_REQUIREMENTS', - 'CUDA_ARRAY_MEMORY_REQUIREMENTS_v1', - 'CUDA_ARRAY_SPARSE_PROPERTIES', 'CUDA_ARRAY_SPARSE_PROPERTIES_v1', - 'CUDA_BATCH_MEM_OP_NODE_PARAMS', 'CUDA_ERROR_ALREADY_ACQUIRED', - 'CUDA_ERROR_ALREADY_MAPPED', 'CUDA_ERROR_ARRAY_IS_MAPPED', - 'CUDA_ERROR_ASSERT', 'CUDA_ERROR_CAPTURED_EVENT', - 'CUDA_ERROR_CDP_NOT_SUPPORTED', 'CUDA_ERROR_CDP_VERSION_MISMATCH', - 'CUDA_ERROR_COMPAT_NOT_SUPPORTED_ON_DEVICE', - 'CUDA_ERROR_CONTEXT_ALREADY_CURRENT', - 'CUDA_ERROR_CONTEXT_ALREADY_IN_USE', - 'CUDA_ERROR_CONTEXT_IS_DESTROYED', - 'CUDA_ERROR_COOPERATIVE_LAUNCH_TOO_LARGE', - 'CUDA_ERROR_DEINITIALIZED', 'CUDA_ERROR_DEVICE_NOT_LICENSED', - 'CUDA_ERROR_DEVICE_UNAVAILABLE', 'CUDA_ERROR_ECC_UNCORRECTABLE', - 'CUDA_ERROR_EXTERNAL_DEVICE', 'CUDA_ERROR_FILE_NOT_FOUND', - 'CUDA_ERROR_GRAPH_EXEC_UPDATE_FAILURE', - 'CUDA_ERROR_HARDWARE_STACK_ERROR', - 'CUDA_ERROR_HOST_MEMORY_ALREADY_REGISTERED', - 'CUDA_ERROR_HOST_MEMORY_NOT_REGISTERED', - 'CUDA_ERROR_ILLEGAL_ADDRESS', 'CUDA_ERROR_ILLEGAL_INSTRUCTION', - 'CUDA_ERROR_ILLEGAL_STATE', 'CUDA_ERROR_INVALID_ADDRESS_SPACE', - 'CUDA_ERROR_INVALID_CLUSTER_SIZE', 'CUDA_ERROR_INVALID_CONTEXT', - 'CUDA_ERROR_INVALID_DEVICE', - 'CUDA_ERROR_INVALID_GRAPHICS_CONTEXT', - 'CUDA_ERROR_INVALID_HANDLE', 'CUDA_ERROR_INVALID_IMAGE', - 'CUDA_ERROR_INVALID_PC', 'CUDA_ERROR_INVALID_PTX', - 'CUDA_ERROR_INVALID_SOURCE', 'CUDA_ERROR_INVALID_VALUE', - 'CUDA_ERROR_JIT_COMPILATION_DISABLED', - 'CUDA_ERROR_JIT_COMPILER_NOT_FOUND', 'CUDA_ERROR_LAUNCH_FAILED', - 'CUDA_ERROR_LAUNCH_INCOMPATIBLE_TEXTURING', - 'CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES', 'CUDA_ERROR_LAUNCH_TIMEOUT', - 'CUDA_ERROR_MAP_FAILED', 'CUDA_ERROR_MISALIGNED_ADDRESS', - 'CUDA_ERROR_MPS_CLIENT_TERMINATED', - 'CUDA_ERROR_MPS_CONNECTION_FAILED', - 'CUDA_ERROR_MPS_MAX_CLIENTS_REACHED', - 'CUDA_ERROR_MPS_MAX_CONNECTIONS_REACHED', - 'CUDA_ERROR_MPS_RPC_FAILURE', 'CUDA_ERROR_MPS_SERVER_NOT_READY', - 'CUDA_ERROR_NOT_FOUND', 'CUDA_ERROR_NOT_INITIALIZED', - 'CUDA_ERROR_NOT_MAPPED', 'CUDA_ERROR_NOT_MAPPED_AS_ARRAY', - 'CUDA_ERROR_NOT_MAPPED_AS_POINTER', 'CUDA_ERROR_NOT_PERMITTED', - 'CUDA_ERROR_NOT_READY', 'CUDA_ERROR_NOT_SUPPORTED', - 'CUDA_ERROR_NO_BINARY_FOR_GPU', 'CUDA_ERROR_NO_DEVICE', - 'CUDA_ERROR_NVLINK_UNCORRECTABLE', 'CUDA_ERROR_OPERATING_SYSTEM', - 'CUDA_ERROR_OUT_OF_MEMORY', - 'CUDA_ERROR_PEER_ACCESS_ALREADY_ENABLED', - 'CUDA_ERROR_PEER_ACCESS_NOT_ENABLED', - 'CUDA_ERROR_PEER_ACCESS_UNSUPPORTED', - 'CUDA_ERROR_PRIMARY_CONTEXT_ACTIVE', - 'CUDA_ERROR_PROFILER_ALREADY_STARTED', - 'CUDA_ERROR_PROFILER_ALREADY_STOPPED', - 'CUDA_ERROR_PROFILER_DISABLED', - 'CUDA_ERROR_PROFILER_NOT_INITIALIZED', - 'CUDA_ERROR_SHARED_OBJECT_INIT_FAILED', - 'CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND', - 'CUDA_ERROR_STREAM_CAPTURE_IMPLICIT', - 'CUDA_ERROR_STREAM_CAPTURE_INVALIDATED', - 'CUDA_ERROR_STREAM_CAPTURE_ISOLATION', - 'CUDA_ERROR_STREAM_CAPTURE_MERGE', - 'CUDA_ERROR_STREAM_CAPTURE_UNJOINED', - 'CUDA_ERROR_STREAM_CAPTURE_UNMATCHED', - 'CUDA_ERROR_STREAM_CAPTURE_UNSUPPORTED', - 'CUDA_ERROR_STREAM_CAPTURE_WRONG_THREAD', - 'CUDA_ERROR_STUB_LIBRARY', 'CUDA_ERROR_SYSTEM_DRIVER_MISMATCH', - 'CUDA_ERROR_SYSTEM_NOT_READY', 'CUDA_ERROR_TIMEOUT', - 'CUDA_ERROR_TOO_MANY_PEERS', 'CUDA_ERROR_UNKNOWN', - 'CUDA_ERROR_UNMAP_FAILED', 'CUDA_ERROR_UNSUPPORTED_EXEC_AFFINITY', - 'CUDA_ERROR_UNSUPPORTED_LIMIT', - 'CUDA_ERROR_UNSUPPORTED_PTX_VERSION', - 'CUDA_EXTERNAL_MEMORY_BUFFER_DESC', - 'CUDA_EXTERNAL_MEMORY_BUFFER_DESC_v1', - 'CUDA_EXTERNAL_MEMORY_HANDLE_DESC', - 'CUDA_EXTERNAL_MEMORY_HANDLE_DESC_v1', - 'CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC', - 'CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_v1', - 'CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC', - 'CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_v1', - 'CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS', - 'CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_v1', - 'CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS', - 'CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_v1', - 'CUDA_EXT_SEM_SIGNAL_NODE_PARAMS', - 'CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_v1', - 'CUDA_EXT_SEM_WAIT_NODE_PARAMS', - 'CUDA_EXT_SEM_WAIT_NODE_PARAMS_v1', - 'CUDA_GRAPH_INSTANTIATE_ERROR', - 'CUDA_GRAPH_INSTANTIATE_FLAG_AUTO_FREE_ON_LAUNCH', - 'CUDA_GRAPH_INSTANTIATE_FLAG_DEVICE_LAUNCH', - 'CUDA_GRAPH_INSTANTIATE_FLAG_UPLOAD', - 'CUDA_GRAPH_INSTANTIATE_FLAG_USE_NODE_PRIORITY', - 'CUDA_GRAPH_INSTANTIATE_INVALID_STRUCTURE', - 'CUDA_GRAPH_INSTANTIATE_MULTIPLE_CTXS_NOT_SUPPORTED', - 'CUDA_GRAPH_INSTANTIATE_NODE_OPERATION_NOT_SUPPORTED', - 'CUDA_GRAPH_INSTANTIATE_PARAMS', 'CUDA_GRAPH_INSTANTIATE_SUCCESS', - 'CUDA_HOST_NODE_PARAMS', 'CUDA_HOST_NODE_PARAMS_v1', - 'CUDA_KERNEL_NODE_PARAMS', 'CUDA_KERNEL_NODE_PARAMS_v1', - 'CUDA_KERNEL_NODE_PARAMS_v2', 'CUDA_LAUNCH_PARAMS', - 'CUDA_LAUNCH_PARAMS_v1', 'CUDA_MEMCPY2D', 'CUDA_MEMCPY2D_v1', - 'CUDA_MEMCPY2D_v2', 'CUDA_MEMCPY3D', 'CUDA_MEMCPY3D_PEER', - 'CUDA_MEMCPY3D_PEER_v1', 'CUDA_MEMCPY3D_v1', 'CUDA_MEMCPY3D_v2', - 'CUDA_MEMSET_NODE_PARAMS', 'CUDA_MEMSET_NODE_PARAMS_v1', - 'CUDA_MEM_ALLOC_NODE_PARAMS', - 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS__enumvalues', - 'CUDA_POINTER_ATTRIBUTE_ACCESS_FLAGS_enum', - 'CUDA_POINTER_ATTRIBUTE_P2P_TOKENS', - 'CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_v1', 'CUDA_RESOURCE_DESC', - 'CUDA_RESOURCE_DESC_v1', 'CUDA_RESOURCE_VIEW_DESC', - 'CUDA_RESOURCE_VIEW_DESC_v1', 'CUDA_SUCCESS', 'CUDA_TEXTURE_DESC', - 'CUDA_TEXTURE_DESC_v1', 'CUGPUDirectRDMAWritesOrdering', - 'CUGPUDirectRDMAWritesOrdering__enumvalues', - 'CUGPUDirectRDMAWritesOrdering_enum', 'CU_ACCESS_PROPERTY_NORMAL', - 'CU_ACCESS_PROPERTY_PERSISTING', 'CU_ACCESS_PROPERTY_STREAMING', - 'CU_AD_FORMAT_BC1_UNORM', 'CU_AD_FORMAT_BC1_UNORM_SRGB', - 'CU_AD_FORMAT_BC2_UNORM', 'CU_AD_FORMAT_BC2_UNORM_SRGB', - 'CU_AD_FORMAT_BC3_UNORM', 'CU_AD_FORMAT_BC3_UNORM_SRGB', - 'CU_AD_FORMAT_BC4_SNORM', 'CU_AD_FORMAT_BC4_UNORM', - 'CU_AD_FORMAT_BC5_SNORM', 'CU_AD_FORMAT_BC5_UNORM', - 'CU_AD_FORMAT_BC6H_SF16', 'CU_AD_FORMAT_BC6H_UF16', - 'CU_AD_FORMAT_BC7_UNORM', 'CU_AD_FORMAT_BC7_UNORM_SRGB', - 'CU_AD_FORMAT_FLOAT', 'CU_AD_FORMAT_HALF', 'CU_AD_FORMAT_NV12', - 'CU_AD_FORMAT_SIGNED_INT16', 'CU_AD_FORMAT_SIGNED_INT32', - 'CU_AD_FORMAT_SIGNED_INT8', 'CU_AD_FORMAT_SNORM_INT16X1', - 'CU_AD_FORMAT_SNORM_INT16X2', 'CU_AD_FORMAT_SNORM_INT16X4', - 'CU_AD_FORMAT_SNORM_INT8X1', 'CU_AD_FORMAT_SNORM_INT8X2', - 'CU_AD_FORMAT_SNORM_INT8X4', 'CU_AD_FORMAT_UNORM_INT16X1', - 'CU_AD_FORMAT_UNORM_INT16X2', 'CU_AD_FORMAT_UNORM_INT16X4', - 'CU_AD_FORMAT_UNORM_INT8X1', 'CU_AD_FORMAT_UNORM_INT8X2', - 'CU_AD_FORMAT_UNORM_INT8X4', 'CU_AD_FORMAT_UNSIGNED_INT16', - 'CU_AD_FORMAT_UNSIGNED_INT32', 'CU_AD_FORMAT_UNSIGNED_INT8', - 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_MIPTAIL', - 'CU_ARRAY_SPARSE_SUBRESOURCE_TYPE_SPARSE_LEVEL', - 'CU_CLUSTER_SCHEDULING_POLICY_DEFAULT', - 'CU_CLUSTER_SCHEDULING_POLICY_LOAD_BALANCING', - 'CU_CLUSTER_SCHEDULING_POLICY_SPREAD', 'CU_COMPUTEMODE_DEFAULT', - 'CU_COMPUTEMODE_EXCLUSIVE_PROCESS', 'CU_COMPUTEMODE_PROHIBITED', - 'CU_CTX_BLOCKING_SYNC', 'CU_CTX_FLAGS_MASK', - 'CU_CTX_LMEM_RESIZE_TO_MAX', 'CU_CTX_MAP_HOST', - 'CU_CTX_SCHED_AUTO', 'CU_CTX_SCHED_BLOCKING_SYNC', - 'CU_CTX_SCHED_MASK', 'CU_CTX_SCHED_SPIN', 'CU_CTX_SCHED_YIELD', - 'CU_CUBEMAP_FACE_NEGATIVE_X', 'CU_CUBEMAP_FACE_NEGATIVE_Y', - 'CU_CUBEMAP_FACE_NEGATIVE_Z', 'CU_CUBEMAP_FACE_POSITIVE_X', - 'CU_CUBEMAP_FACE_POSITIVE_Y', 'CU_CUBEMAP_FACE_POSITIVE_Z', - 'CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT', - 'CU_DEVICE_ATTRIBUTE_CAN_FLUSH_REMOTE_WRITES', - 'CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY', - 'CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_64_BIT_STREAM_MEM_OPS_V1', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_HOST_POINTER_FOR_REGISTERED_MEM', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_MEM_OPS_V1', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR', - 'CU_DEVICE_ATTRIBUTE_CAN_USE_STREAM_WAIT_VALUE_NOR_V1', - 'CU_DEVICE_ATTRIBUTE_CLOCK_RATE', - 'CU_DEVICE_ATTRIBUTE_CLUSTER_LAUNCH', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_MODE', - 'CU_DEVICE_ATTRIBUTE_COMPUTE_PREEMPTION_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS', - 'CU_DEVICE_ATTRIBUTE_CONCURRENT_MANAGED_ACCESS', - 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_LAUNCH', - 'CU_DEVICE_ATTRIBUTE_COOPERATIVE_MULTI_DEVICE_LAUNCH', - 'CU_DEVICE_ATTRIBUTE_DEFERRED_MAPPING_CUDA_ARRAY_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_DIRECT_MANAGED_MEM_ACCESS_FROM_HOST', - 'CU_DEVICE_ATTRIBUTE_DMA_BUF_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_ECC_ENABLED', - 'CU_DEVICE_ATTRIBUTE_GENERIC_COMPRESSION_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_FLUSH_WRITES_OPTIONS', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WITH_CUDA_VMM_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_GPU_DIRECT_RDMA_WRITES_ORDERING', - 'CU_DEVICE_ATTRIBUTE_GPU_OVERLAP', - 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_HANDLE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HANDLE_TYPE_WIN32_KMT_HANDLE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HOST_NATIVE_ATOMIC_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_HOST_REGISTER_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_INTEGRATED', - 'CU_DEVICE_ATTRIBUTE_IPC_EVENT_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT', - 'CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE', - 'CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY', 'CU_DEVICE_ATTRIBUTE_MAX', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH', - 'CU_DEVICE_ATTRIBUTE_MAX_ACCESS_POLICY_WINDOW_SIZE', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCKS_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y', - 'CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z', - 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X', - 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y', - 'CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z', - 'CU_DEVICE_ATTRIBUTE_MAX_PERSISTING_L2_CACHE_SIZE', - 'CU_DEVICE_ATTRIBUTE_MAX_PITCH', - 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK_OPTIN', - 'CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR', - 'CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE', - 'CU_DEVICE_ATTRIBUTE_MEMORY_POOLS_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_MEMPOOL_SUPPORTED_HANDLE_TYPES', - 'CU_DEVICE_ATTRIBUTE_MEM_SYNC_DOMAIN_COUNT', - 'CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT', - 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD', - 'CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID', - 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS', - 'CU_DEVICE_ATTRIBUTE_PAGEABLE_MEMORY_ACCESS_USES_HOST_PAGE_TABLES', - 'CU_DEVICE_ATTRIBUTE_PCI_BUS_ID', - 'CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID', - 'CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID', - 'CU_DEVICE_ATTRIBUTE_READ_ONLY_HOST_REGISTER_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_RESERVED_SHARED_MEMORY_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK', - 'CU_DEVICE_ATTRIBUTE_SINGLE_TO_DOUBLE_PRECISION_PERF_RATIO', - 'CU_DEVICE_ATTRIBUTE_SPARSE_CUDA_ARRAY_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT', - 'CU_DEVICE_ATTRIBUTE_TCC_DRIVER', - 'CU_DEVICE_ATTRIBUTE_TENSOR_MAP_ACCESS_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT', - 'CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT', - 'CU_DEVICE_ATTRIBUTE_TIMELINE_SEMAPHORE_INTEROP_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY', - 'CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING', - 'CU_DEVICE_ATTRIBUTE_UNIFIED_FUNCTION_POINTERS', - 'CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED', - 'CU_DEVICE_ATTRIBUTE_WARP_SIZE', - 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_ACCESS_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_ACCESS_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_CUDA_ARRAY_ACCESS_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_NATIVE_ATOMIC_SUPPORTED', - 'CU_DEVICE_P2P_ATTRIBUTE_PERFORMANCE_RANK', - 'CU_EVENT_BLOCKING_SYNC', 'CU_EVENT_DEFAULT', - 'CU_EVENT_DISABLE_TIMING', 'CU_EVENT_INTERPROCESS', - 'CU_EVENT_RECORD_DEFAULT', 'CU_EVENT_RECORD_EXTERNAL', - 'CU_EVENT_SCHED_AUTO', 'CU_EVENT_SCHED_BLOCKING_SYNC', - 'CU_EVENT_SCHED_SPIN', 'CU_EVENT_SCHED_YIELD', - 'CU_EVENT_WAIT_DEFAULT', 'CU_EVENT_WAIT_EXTERNAL', - 'CU_EXEC_AFFINITY_TYPE_MAX', 'CU_EXEC_AFFINITY_TYPE_SM_COUNT', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D11_RESOURCE_KMT', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_HEAP', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_D3D12_RESOURCE', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_NVSCIBUF', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32', - 'CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_FENCE', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D11_KEYED_MUTEX_KMT', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_D3D12_FENCE', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_NVSCISYNC', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_WIN32_KMT', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_FD', - 'CU_EXTERNAL_SEMAPHORE_HANDLE_TYPE_TIMELINE_SEMAPHORE_WIN32', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_HOST', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_OPTION_MEMOPS', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_ALL_DEVICES', - 'CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER', - 'CU_FUNC_ATTRIBUTE_BINARY_VERSION', - 'CU_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 'CU_FUNC_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 'CU_FUNC_ATTRIBUTE_CLUSTER_SIZE_MUST_BE_SET', - 'CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 'CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', 'CU_FUNC_ATTRIBUTE_MAX', - 'CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 'CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 'CU_FUNC_ATTRIBUTE_NON_PORTABLE_CLUSTER_SIZE_ALLOWED', - 'CU_FUNC_ATTRIBUTE_NUM_REGS', - 'CU_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 'CU_FUNC_ATTRIBUTE_PTX_VERSION', - 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_DEPTH', - 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_HEIGHT', - 'CU_FUNC_ATTRIBUTE_REQUIRED_CLUSTER_WIDTH', - 'CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', - 'CU_FUNC_CACHE_PREFER_EQUAL', 'CU_FUNC_CACHE_PREFER_L1', - 'CU_FUNC_CACHE_PREFER_NONE', 'CU_FUNC_CACHE_PREFER_SHARED', - 'CU_GET_PROC_ADDRESS_DEFAULT', - 'CU_GET_PROC_ADDRESS_LEGACY_STREAM', - 'CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM', - 'CU_GET_PROC_ADDRESS_SUCCESS', - 'CU_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND', - 'CU_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT', - 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_ALL_DEVICES', - 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_NONE', - 'CU_GPU_DIRECT_RDMA_WRITES_ORDERING_OWNER', - 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE', - 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY', - 'CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD', - 'CU_GRAPHICS_REGISTER_FLAGS_NONE', - 'CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY', - 'CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST', - 'CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER', - 'CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD', - 'CU_GRAPH_DEBUG_DOT_FLAGS_BATCH_MEM_OP_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EVENT_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EXTRA_TOPO_INFO', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_SIGNAL_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_EXT_SEMAS_WAIT_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_HANDLES', - 'CU_GRAPH_DEBUG_DOT_FLAGS_HOST_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_ATTRIBUTES', - 'CU_GRAPH_DEBUG_DOT_FLAGS_KERNEL_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMCPY_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEMSET_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_ALLOC_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_MEM_FREE_NODE_PARAMS', - 'CU_GRAPH_DEBUG_DOT_FLAGS_RUNTIME_TYPES', - 'CU_GRAPH_DEBUG_DOT_FLAGS_VERBOSE', 'CU_GRAPH_EXEC_UPDATE_ERROR', - 'CU_GRAPH_EXEC_UPDATE_ERROR_ATTRIBUTES_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_FUNCTION_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_NODE_TYPE_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_NOT_SUPPORTED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_PARAMETERS_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_TOPOLOGY_CHANGED', - 'CU_GRAPH_EXEC_UPDATE_ERROR_UNSUPPORTED_FUNCTION_CHANGE', - 'CU_GRAPH_EXEC_UPDATE_SUCCESS', - 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_CURRENT', - 'CU_GRAPH_MEM_ATTR_RESERVED_MEM_HIGH', - 'CU_GRAPH_MEM_ATTR_USED_MEM_CURRENT', - 'CU_GRAPH_MEM_ATTR_USED_MEM_HIGH', - 'CU_GRAPH_NODE_TYPE_BATCH_MEM_OP', 'CU_GRAPH_NODE_TYPE_EMPTY', - 'CU_GRAPH_NODE_TYPE_EVENT_RECORD', - 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_SIGNAL', - 'CU_GRAPH_NODE_TYPE_EXT_SEMAS_WAIT', 'CU_GRAPH_NODE_TYPE_GRAPH', - 'CU_GRAPH_NODE_TYPE_HOST', 'CU_GRAPH_NODE_TYPE_KERNEL', - 'CU_GRAPH_NODE_TYPE_MEMCPY', 'CU_GRAPH_NODE_TYPE_MEMSET', - 'CU_GRAPH_NODE_TYPE_MEM_ALLOC', 'CU_GRAPH_NODE_TYPE_MEM_FREE', - 'CU_GRAPH_NODE_TYPE_WAIT_EVENT', 'CU_GRAPH_USER_OBJECT_MOVE', - 'CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS', 'CU_JIT_CACHE_MODE', - 'CU_JIT_CACHE_OPTION_CA', 'CU_JIT_CACHE_OPTION_CG', - 'CU_JIT_CACHE_OPTION_NONE', 'CU_JIT_ERROR_LOG_BUFFER', - 'CU_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', 'CU_JIT_FALLBACK_STRATEGY', - 'CU_JIT_FAST_COMPILE', 'CU_JIT_FMA', 'CU_JIT_FTZ', - 'CU_JIT_GENERATE_DEBUG_INFO', 'CU_JIT_GENERATE_LINE_INFO', - 'CU_JIT_GLOBAL_SYMBOL_ADDRESSES', 'CU_JIT_GLOBAL_SYMBOL_COUNT', - 'CU_JIT_GLOBAL_SYMBOL_NAMES', 'CU_JIT_INFO_LOG_BUFFER', - 'CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES', 'CU_JIT_INPUT_CUBIN', - 'CU_JIT_INPUT_FATBINARY', 'CU_JIT_INPUT_LIBRARY', - 'CU_JIT_INPUT_NVVM', 'CU_JIT_INPUT_OBJECT', 'CU_JIT_INPUT_PTX', - 'CU_JIT_LOG_VERBOSE', 'CU_JIT_LTO', 'CU_JIT_MAX_REGISTERS', - 'CU_JIT_NEW_SM3X_OPT', 'CU_JIT_NUM_INPUT_TYPES', - 'CU_JIT_NUM_OPTIONS', 'CU_JIT_OPTIMIZATION_LEVEL', - 'CU_JIT_OPTIMIZE_UNUSED_DEVICE_VARIABLES', - 'CU_JIT_POSITION_INDEPENDENT_CODE', 'CU_JIT_PREC_DIV', - 'CU_JIT_PREC_SQRT', 'CU_JIT_REFERENCED_KERNEL_COUNT', - 'CU_JIT_REFERENCED_KERNEL_NAMES', - 'CU_JIT_REFERENCED_VARIABLE_COUNT', - 'CU_JIT_REFERENCED_VARIABLE_NAMES', 'CU_JIT_TARGET', - 'CU_JIT_TARGET_FROM_CUCONTEXT', 'CU_JIT_THREADS_PER_BLOCK', - 'CU_JIT_WALL_TIME', 'CU_LAUNCH_ATTRIBUTE_ACCESS_POLICY_WINDOW', - 'CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION', - 'CU_LAUNCH_ATTRIBUTE_CLUSTER_SCHEDULING_POLICY_PREFERENCE', - 'CU_LAUNCH_ATTRIBUTE_COOPERATIVE', 'CU_LAUNCH_ATTRIBUTE_IGNORE', - 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN', - 'CU_LAUNCH_ATTRIBUTE_MEM_SYNC_DOMAIN_MAP', - 'CU_LAUNCH_ATTRIBUTE_PRIORITY', - 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_EVENT', - 'CU_LAUNCH_ATTRIBUTE_PROGRAMMATIC_STREAM_SERIALIZATION', - 'CU_LAUNCH_ATTRIBUTE_SYNCHRONIZATION_POLICY', - 'CU_LAUNCH_MEM_SYNC_DOMAIN_DEFAULT', - 'CU_LAUNCH_MEM_SYNC_DOMAIN_REMOTE', - 'CU_LIBRARY_BINARY_IS_PRESERVED', - 'CU_LIBRARY_HOST_UNIVERSAL_FUNCTION_AND_DATA_TABLE', - 'CU_LIBRARY_NUM_OPTIONS', - 'CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT', - 'CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH', 'CU_LIMIT_MALLOC_HEAP_SIZE', - 'CU_LIMIT_MAX', 'CU_LIMIT_MAX_L2_FETCH_GRANULARITY', - 'CU_LIMIT_PERSISTING_L2_CACHE_SIZE', 'CU_LIMIT_PRINTF_FIFO_SIZE', - 'CU_LIMIT_STACK_SIZE', 'CU_MEMORYTYPE_ARRAY', - 'CU_MEMORYTYPE_DEVICE', 'CU_MEMORYTYPE_HOST', - 'CU_MEMORYTYPE_UNIFIED', 'CU_MEMPOOL_ATTR_RELEASE_THRESHOLD', - 'CU_MEMPOOL_ATTR_RESERVED_MEM_CURRENT', - 'CU_MEMPOOL_ATTR_RESERVED_MEM_HIGH', - 'CU_MEMPOOL_ATTR_REUSE_ALLOW_INTERNAL_DEPENDENCIES', - 'CU_MEMPOOL_ATTR_REUSE_ALLOW_OPPORTUNISTIC', - 'CU_MEMPOOL_ATTR_REUSE_FOLLOW_EVENT_DEPENDENCIES', - 'CU_MEMPOOL_ATTR_USED_MEM_CURRENT', - 'CU_MEMPOOL_ATTR_USED_MEM_HIGH', 'CU_MEM_ACCESS_FLAGS_PROT_MAX', - 'CU_MEM_ACCESS_FLAGS_PROT_NONE', 'CU_MEM_ACCESS_FLAGS_PROT_READ', - 'CU_MEM_ACCESS_FLAGS_PROT_READWRITE', - 'CU_MEM_ADVISE_SET_ACCESSED_BY', - 'CU_MEM_ADVISE_SET_PREFERRED_LOCATION', - 'CU_MEM_ADVISE_SET_READ_MOSTLY', - 'CU_MEM_ADVISE_UNSET_ACCESSED_BY', - 'CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION', - 'CU_MEM_ADVISE_UNSET_READ_MOSTLY', - 'CU_MEM_ALLOCATION_COMP_GENERIC', 'CU_MEM_ALLOCATION_COMP_NONE', - 'CU_MEM_ALLOCATION_TYPE_INVALID', 'CU_MEM_ALLOCATION_TYPE_MAX', - 'CU_MEM_ALLOCATION_TYPE_PINNED', - 'CU_MEM_ALLOC_GRANULARITY_MINIMUM', - 'CU_MEM_ALLOC_GRANULARITY_RECOMMENDED', 'CU_MEM_ATTACH_GLOBAL', - 'CU_MEM_ATTACH_HOST', 'CU_MEM_ATTACH_SINGLE', - 'CU_MEM_HANDLE_TYPE_GENERIC', 'CU_MEM_HANDLE_TYPE_MAX', - 'CU_MEM_HANDLE_TYPE_NONE', - 'CU_MEM_HANDLE_TYPE_POSIX_FILE_DESCRIPTOR', - 'CU_MEM_HANDLE_TYPE_WIN32', 'CU_MEM_HANDLE_TYPE_WIN32_KMT', - 'CU_MEM_LOCATION_TYPE_DEVICE', 'CU_MEM_LOCATION_TYPE_INVALID', - 'CU_MEM_LOCATION_TYPE_MAX', 'CU_MEM_OPERATION_TYPE_MAP', - 'CU_MEM_OPERATION_TYPE_UNMAP', - 'CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY', - 'CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION', - 'CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION', - 'CU_MEM_RANGE_ATTRIBUTE_READ_MOSTLY', - 'CU_MEM_RANGE_HANDLE_TYPE_DMA_BUF_FD', - 'CU_MEM_RANGE_HANDLE_TYPE_MAX', 'CU_MODULE_EAGER_LOADING', - 'CU_MODULE_LAZY_LOADING', 'CU_OCCUPANCY_DEFAULT', - 'CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_NONE', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READ', - 'CU_POINTER_ATTRIBUTE_ACCESS_FLAG_READWRITE', - 'CU_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 'CU_POINTER_ATTRIBUTE_BUFFER_ID', 'CU_POINTER_ATTRIBUTE_CONTEXT', - 'CU_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 'CU_POINTER_ATTRIBUTE_DEVICE_POINTER', - 'CU_POINTER_ATTRIBUTE_HOST_POINTER', - 'CU_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 'CU_POINTER_ATTRIBUTE_IS_LEGACY_CUDA_IPC_CAPABLE', - 'CU_POINTER_ATTRIBUTE_IS_MANAGED', 'CU_POINTER_ATTRIBUTE_MAPPED', - 'CU_POINTER_ATTRIBUTE_MAPPING_BASE_ADDR', - 'CU_POINTER_ATTRIBUTE_MAPPING_SIZE', - 'CU_POINTER_ATTRIBUTE_MEMORY_BLOCK_ID', - 'CU_POINTER_ATTRIBUTE_MEMORY_TYPE', - 'CU_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', - 'CU_POINTER_ATTRIBUTE_P2P_TOKENS', - 'CU_POINTER_ATTRIBUTE_RANGE_SIZE', - 'CU_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 'CU_POINTER_ATTRIBUTE_SYNC_MEMOPS', 'CU_PREFER_BINARY', - 'CU_PREFER_PTX', 'CU_RESOURCE_TYPE_ARRAY', - 'CU_RESOURCE_TYPE_LINEAR', 'CU_RESOURCE_TYPE_MIPMAPPED_ARRAY', - 'CU_RESOURCE_TYPE_PITCH2D', 'CU_RES_VIEW_FORMAT_FLOAT_1X16', - 'CU_RES_VIEW_FORMAT_FLOAT_1X32', 'CU_RES_VIEW_FORMAT_FLOAT_2X16', - 'CU_RES_VIEW_FORMAT_FLOAT_2X32', 'CU_RES_VIEW_FORMAT_FLOAT_4X16', - 'CU_RES_VIEW_FORMAT_FLOAT_4X32', 'CU_RES_VIEW_FORMAT_NONE', - 'CU_RES_VIEW_FORMAT_SIGNED_BC4', 'CU_RES_VIEW_FORMAT_SIGNED_BC5', - 'CU_RES_VIEW_FORMAT_SIGNED_BC6H', 'CU_RES_VIEW_FORMAT_SINT_1X16', - 'CU_RES_VIEW_FORMAT_SINT_1X32', 'CU_RES_VIEW_FORMAT_SINT_1X8', - 'CU_RES_VIEW_FORMAT_SINT_2X16', 'CU_RES_VIEW_FORMAT_SINT_2X32', - 'CU_RES_VIEW_FORMAT_SINT_2X8', 'CU_RES_VIEW_FORMAT_SINT_4X16', - 'CU_RES_VIEW_FORMAT_SINT_4X32', 'CU_RES_VIEW_FORMAT_SINT_4X8', - 'CU_RES_VIEW_FORMAT_UINT_1X16', 'CU_RES_VIEW_FORMAT_UINT_1X32', - 'CU_RES_VIEW_FORMAT_UINT_1X8', 'CU_RES_VIEW_FORMAT_UINT_2X16', - 'CU_RES_VIEW_FORMAT_UINT_2X32', 'CU_RES_VIEW_FORMAT_UINT_2X8', - 'CU_RES_VIEW_FORMAT_UINT_4X16', 'CU_RES_VIEW_FORMAT_UINT_4X32', - 'CU_RES_VIEW_FORMAT_UINT_4X8', 'CU_RES_VIEW_FORMAT_UNSIGNED_BC1', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC2', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC3', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC4', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC5', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 'CU_RES_VIEW_FORMAT_UNSIGNED_BC7', - 'CU_SHAREDMEM_CARVEOUT_DEFAULT', 'CU_SHAREDMEM_CARVEOUT_MAX_L1', - 'CU_SHAREDMEM_CARVEOUT_MAX_SHARED', - 'CU_SHARED_MEM_CONFIG_DEFAULT_BANK_SIZE', - 'CU_SHARED_MEM_CONFIG_EIGHT_BYTE_BANK_SIZE', - 'CU_SHARED_MEM_CONFIG_FOUR_BYTE_BANK_SIZE', - 'CU_STREAM_ADD_CAPTURE_DEPENDENCIES', - 'CU_STREAM_CAPTURE_MODE_GLOBAL', 'CU_STREAM_CAPTURE_MODE_RELAXED', - 'CU_STREAM_CAPTURE_MODE_THREAD_LOCAL', - 'CU_STREAM_CAPTURE_STATUS_ACTIVE', - 'CU_STREAM_CAPTURE_STATUS_INVALIDATED', - 'CU_STREAM_CAPTURE_STATUS_NONE', 'CU_STREAM_DEFAULT', - 'CU_STREAM_MEMORY_BARRIER_TYPE_GPU', - 'CU_STREAM_MEMORY_BARRIER_TYPE_SYS', 'CU_STREAM_MEM_OP_BARRIER', - 'CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES', - 'CU_STREAM_MEM_OP_WAIT_VALUE_32', - 'CU_STREAM_MEM_OP_WAIT_VALUE_64', - 'CU_STREAM_MEM_OP_WRITE_VALUE_32', - 'CU_STREAM_MEM_OP_WRITE_VALUE_64', 'CU_STREAM_NON_BLOCKING', - 'CU_STREAM_SET_CAPTURE_DEPENDENCIES', 'CU_STREAM_WAIT_VALUE_AND', - 'CU_STREAM_WAIT_VALUE_EQ', 'CU_STREAM_WAIT_VALUE_FLUSH', - 'CU_STREAM_WAIT_VALUE_GEQ', 'CU_STREAM_WAIT_VALUE_NOR', - 'CU_STREAM_WRITE_VALUE_DEFAULT', - 'CU_STREAM_WRITE_VALUE_NO_MEMORY_BARRIER', 'CU_SYNC_POLICY_AUTO', - 'CU_SYNC_POLICY_BLOCKING_SYNC', 'CU_SYNC_POLICY_SPIN', - 'CU_SYNC_POLICY_YIELD', 'CU_TARGET_COMPUTE_30', - 'CU_TARGET_COMPUTE_32', 'CU_TARGET_COMPUTE_35', - 'CU_TARGET_COMPUTE_37', 'CU_TARGET_COMPUTE_50', - 'CU_TARGET_COMPUTE_52', 'CU_TARGET_COMPUTE_53', - 'CU_TARGET_COMPUTE_60', 'CU_TARGET_COMPUTE_61', - 'CU_TARGET_COMPUTE_62', 'CU_TARGET_COMPUTE_70', - 'CU_TARGET_COMPUTE_72', 'CU_TARGET_COMPUTE_75', - 'CU_TARGET_COMPUTE_80', 'CU_TARGET_COMPUTE_86', - 'CU_TARGET_COMPUTE_87', 'CU_TARGET_COMPUTE_89', - 'CU_TARGET_COMPUTE_90', 'CU_TARGET_COMPUTE_90A', - 'CU_TENSOR_MAP_DATA_TYPE_BFLOAT16', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT16', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT32_FTZ', - 'CU_TENSOR_MAP_DATA_TYPE_FLOAT64', - 'CU_TENSOR_MAP_DATA_TYPE_INT32', 'CU_TENSOR_MAP_DATA_TYPE_INT64', - 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32', - 'CU_TENSOR_MAP_DATA_TYPE_TFLOAT32_FTZ', - 'CU_TENSOR_MAP_DATA_TYPE_UINT16', - 'CU_TENSOR_MAP_DATA_TYPE_UINT32', - 'CU_TENSOR_MAP_DATA_TYPE_UINT64', 'CU_TENSOR_MAP_DATA_TYPE_UINT8', - 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NAN_REQUEST_ZERO_FMA', - 'CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE', - 'CU_TENSOR_MAP_INTERLEAVE_16B', 'CU_TENSOR_MAP_INTERLEAVE_32B', - 'CU_TENSOR_MAP_INTERLEAVE_NONE', - 'CU_TENSOR_MAP_L2_PROMOTION_L2_128B', - 'CU_TENSOR_MAP_L2_PROMOTION_L2_256B', - 'CU_TENSOR_MAP_L2_PROMOTION_L2_64B', - 'CU_TENSOR_MAP_L2_PROMOTION_NONE', 'CU_TENSOR_MAP_SWIZZLE_128B', - 'CU_TENSOR_MAP_SWIZZLE_32B', 'CU_TENSOR_MAP_SWIZZLE_64B', - 'CU_TENSOR_MAP_SWIZZLE_NONE', 'CU_TR_ADDRESS_MODE_BORDER', - 'CU_TR_ADDRESS_MODE_CLAMP', 'CU_TR_ADDRESS_MODE_MIRROR', - 'CU_TR_ADDRESS_MODE_WRAP', 'CU_TR_FILTER_MODE_LINEAR', - 'CU_TR_FILTER_MODE_POINT', 'CU_USER_OBJECT_NO_DESTRUCTOR_SYNC', - 'CUaccessPolicyWindow', 'CUaccessPolicyWindow_v1', - 'CUaccessProperty', 'CUaccessProperty__enumvalues', - 'CUaccessProperty_enum', 'CUaddress_mode', - 'CUaddress_mode__enumvalues', 'CUaddress_mode_enum', 'CUarray', - 'CUarrayMapInfo', 'CUarrayMapInfo_v1', - 'CUarraySparseSubresourceType', - 'CUarraySparseSubresourceType__enumvalues', - 'CUarraySparseSubresourceType_enum', 'CUarray_cubemap_face', - 'CUarray_cubemap_face__enumvalues', 'CUarray_cubemap_face_enum', - 'CUarray_format', 'CUarray_format__enumvalues', - 'CUarray_format_enum', 'CUclusterSchedulingPolicy', - 'CUclusterSchedulingPolicy__enumvalues', - 'CUclusterSchedulingPolicy_enum', 'CUcomputemode', - 'CUcomputemode__enumvalues', 'CUcomputemode_enum', 'CUcontext', - 'CUctx_flags', 'CUctx_flags__enumvalues', 'CUctx_flags_enum', - 'CUdevice', 'CUdevice_P2PAttribute', - 'CUdevice_P2PAttribute__enumvalues', 'CUdevice_P2PAttribute_enum', - 'CUdevice_attribute', 'CUdevice_attribute__enumvalues', - 'CUdevice_attribute_enum', 'CUdevice_v1', 'CUdeviceptr', - 'CUdeviceptr_v1', 'CUdeviceptr_v2', 'CUdevprop', 'CUdevprop_v1', - 'CUdriverProcAddressQueryResult', - 'CUdriverProcAddressQueryResult__enumvalues', - 'CUdriverProcAddressQueryResult_enum', - 'CUdriverProcAddress_flags', - 'CUdriverProcAddress_flags__enumvalues', - 'CUdriverProcAddress_flags_enum', 'CUevent', 'CUevent_flags', - 'CUevent_flags__enumvalues', 'CUevent_flags_enum', - 'CUevent_record_flags', 'CUevent_record_flags__enumvalues', - 'CUevent_record_flags_enum', 'CUevent_sched_flags', - 'CUevent_sched_flags__enumvalues', 'CUevent_sched_flags_enum', - 'CUevent_wait_flags', 'CUevent_wait_flags__enumvalues', - 'CUevent_wait_flags_enum', 'CUexecAffinityParam', - 'CUexecAffinityParam_v1', 'CUexecAffinitySmCount', - 'CUexecAffinitySmCount_v1', 'CUexecAffinityType', - 'CUexecAffinityType__enumvalues', 'CUexecAffinityType_enum', - 'CUexternalMemory', 'CUexternalMemoryHandleType', - 'CUexternalMemoryHandleType__enumvalues', - 'CUexternalMemoryHandleType_enum', 'CUexternalSemaphore', - 'CUexternalSemaphoreHandleType', - 'CUexternalSemaphoreHandleType__enumvalues', - 'CUexternalSemaphoreHandleType_enum', 'CUfilter_mode', - 'CUfilter_mode__enumvalues', 'CUfilter_mode_enum', - 'CUflushGPUDirectRDMAWritesOptions', - 'CUflushGPUDirectRDMAWritesOptions__enumvalues', - 'CUflushGPUDirectRDMAWritesOptions_enum', - 'CUflushGPUDirectRDMAWritesScope', - 'CUflushGPUDirectRDMAWritesScope__enumvalues', - 'CUflushGPUDirectRDMAWritesScope_enum', - 'CUflushGPUDirectRDMAWritesTarget', - 'CUflushGPUDirectRDMAWritesTarget__enumvalues', - 'CUflushGPUDirectRDMAWritesTarget_enum', 'CUfunc_cache', - 'CUfunc_cache__enumvalues', 'CUfunc_cache_enum', 'CUfunction', - 'CUfunction_attribute', 'CUfunction_attribute__enumvalues', - 'CUfunction_attribute_enum', 'CUgraph', 'CUgraphDebugDot_flags', - 'CUgraphDebugDot_flags__enumvalues', 'CUgraphDebugDot_flags_enum', - 'CUgraphExec', 'CUgraphExecUpdateResult', - 'CUgraphExecUpdateResultInfo', 'CUgraphExecUpdateResultInfo_v1', - 'CUgraphExecUpdateResult__enumvalues', - 'CUgraphExecUpdateResult_enum', 'CUgraphInstantiateResult', - 'CUgraphInstantiateResult__enumvalues', - 'CUgraphInstantiateResult_enum', 'CUgraphInstantiate_flags', - 'CUgraphInstantiate_flags__enumvalues', - 'CUgraphInstantiate_flags_enum', 'CUgraphMem_attribute', - 'CUgraphMem_attribute__enumvalues', 'CUgraphMem_attribute_enum', - 'CUgraphNode', 'CUgraphNodeType', 'CUgraphNodeType__enumvalues', - 'CUgraphNodeType_enum', 'CUgraphicsMapResourceFlags', - 'CUgraphicsMapResourceFlags__enumvalues', - 'CUgraphicsMapResourceFlags_enum', 'CUgraphicsRegisterFlags', - 'CUgraphicsRegisterFlags__enumvalues', - 'CUgraphicsRegisterFlags_enum', 'CUgraphicsResource', 'CUhostFn', - 'CUipcEventHandle', 'CUipcEventHandle_v1', 'CUipcMemHandle', - 'CUipcMemHandle_v1', 'CUipcMem_flags', - 'CUipcMem_flags__enumvalues', 'CUipcMem_flags_enum', - 'CUjitInputType', 'CUjitInputType__enumvalues', - 'CUjitInputType_enum', 'CUjit_cacheMode', - 'CUjit_cacheMode__enumvalues', 'CUjit_cacheMode_enum', - 'CUjit_fallback', 'CUjit_fallback__enumvalues', - 'CUjit_fallback_enum', 'CUjit_option', 'CUjit_option__enumvalues', - 'CUjit_option_enum', 'CUjit_target', 'CUjit_target__enumvalues', - 'CUjit_target_enum', 'CUkernel', 'CUkernelNodeAttrID', - 'CUkernelNodeAttrID__enumvalues', 'CUkernelNodeAttrValue', - 'CUkernelNodeAttrValue_v1', 'CUlaunchAttribute', - 'CUlaunchAttributeID', 'CUlaunchAttributeID__enumvalues', - 'CUlaunchAttributeID_enum', 'CUlaunchAttributeValue', - 'CUlaunchConfig', 'CUlaunchMemSyncDomain', - 'CUlaunchMemSyncDomainMap', 'CUlaunchMemSyncDomain__enumvalues', - 'CUlaunchMemSyncDomain_enum', 'CUlibrary', - 'CUlibraryHostUniversalFunctionAndDataTable', 'CUlibraryOption', - 'CUlibraryOption__enumvalues', 'CUlibraryOption_enum', 'CUlimit', - 'CUlimit__enumvalues', 'CUlimit_enum', 'CUlinkState', - 'CUmemAccessDesc', 'CUmemAccessDesc_v1', 'CUmemAccess_flags', - 'CUmemAccess_flags__enumvalues', 'CUmemAccess_flags_enum', - 'CUmemAllocationCompType', 'CUmemAllocationCompType__enumvalues', - 'CUmemAllocationCompType_enum', - 'CUmemAllocationGranularity_flags', - 'CUmemAllocationGranularity_flags__enumvalues', - 'CUmemAllocationGranularity_flags_enum', - 'CUmemAllocationHandleType', - 'CUmemAllocationHandleType__enumvalues', - 'CUmemAllocationHandleType_enum', 'CUmemAllocationProp', - 'CUmemAllocationProp_v1', 'CUmemAllocationType', - 'CUmemAllocationType__enumvalues', 'CUmemAllocationType_enum', - 'CUmemAttach_flags', 'CUmemAttach_flags__enumvalues', - 'CUmemAttach_flags_enum', 'CUmemGenericAllocationHandle', - 'CUmemGenericAllocationHandle_v1', 'CUmemHandleType', - 'CUmemHandleType__enumvalues', 'CUmemHandleType_enum', - 'CUmemLocation', 'CUmemLocationType', - 'CUmemLocationType__enumvalues', 'CUmemLocationType_enum', - 'CUmemLocation_v1', 'CUmemOperationType', - 'CUmemOperationType__enumvalues', 'CUmemOperationType_enum', - 'CUmemPoolProps', 'CUmemPoolProps_v1', 'CUmemPoolPtrExportData', - 'CUmemPoolPtrExportData_v1', 'CUmemPool_attribute', - 'CUmemPool_attribute__enumvalues', 'CUmemPool_attribute_enum', - 'CUmemRangeHandleType', 'CUmemRangeHandleType__enumvalues', - 'CUmemRangeHandleType_enum', 'CUmem_advise', - 'CUmem_advise__enumvalues', 'CUmem_advise_enum', - 'CUmem_range_attribute', 'CUmem_range_attribute__enumvalues', - 'CUmem_range_attribute_enum', 'CUmemoryPool', 'CUmemorytype', - 'CUmemorytype__enumvalues', 'CUmemorytype_enum', - 'CUmipmappedArray', 'CUmodule', 'CUmoduleLoadingMode', - 'CUmoduleLoadingMode__enumvalues', 'CUmoduleLoadingMode_enum', - 'CUoccupancyB2DSize', 'CUoccupancy_flags', - 'CUoccupancy_flags__enumvalues', 'CUoccupancy_flags_enum', - 'CUpointer_attribute', 'CUpointer_attribute__enumvalues', - 'CUpointer_attribute_enum', 'CUresourceViewFormat', - 'CUresourceViewFormat__enumvalues', 'CUresourceViewFormat_enum', - 'CUresourcetype', 'CUresourcetype__enumvalues', - 'CUresourcetype_enum', 'CUresult', 'CUresult__enumvalues', - 'CUshared_carveout', 'CUshared_carveout__enumvalues', - 'CUshared_carveout_enum', 'CUsharedconfig', - 'CUsharedconfig__enumvalues', 'CUsharedconfig_enum', 'CUstream', - 'CUstreamAttrID', 'CUstreamAttrID__enumvalues', - 'CUstreamAttrValue', 'CUstreamAttrValue_v1', - 'CUstreamBatchMemOpParams', 'CUstreamBatchMemOpParams_v1', - 'CUstreamBatchMemOpType', 'CUstreamBatchMemOpType__enumvalues', - 'CUstreamBatchMemOpType_enum', 'CUstreamCallback', - 'CUstreamCaptureMode', 'CUstreamCaptureMode__enumvalues', - 'CUstreamCaptureMode_enum', 'CUstreamCaptureStatus', - 'CUstreamCaptureStatus__enumvalues', 'CUstreamCaptureStatus_enum', - 'CUstreamMemoryBarrier_flags', - 'CUstreamMemoryBarrier_flags__enumvalues', - 'CUstreamMemoryBarrier_flags_enum', - 'CUstreamUpdateCaptureDependencies_flags', - 'CUstreamUpdateCaptureDependencies_flags__enumvalues', - 'CUstreamUpdateCaptureDependencies_flags_enum', - 'CUstreamWaitValue_flags', 'CUstreamWaitValue_flags__enumvalues', - 'CUstreamWaitValue_flags_enum', 'CUstreamWriteValue_flags', - 'CUstreamWriteValue_flags__enumvalues', - 'CUstreamWriteValue_flags_enum', 'CUstream_flags', - 'CUstream_flags__enumvalues', 'CUstream_flags_enum', - 'CUsurfObject', 'CUsurfObject_v1', 'CUsurfref', - 'CUsynchronizationPolicy', 'CUsynchronizationPolicy__enumvalues', - 'CUsynchronizationPolicy_enum', 'CUtensorMap', - 'CUtensorMapDataType', 'CUtensorMapDataType__enumvalues', - 'CUtensorMapDataType_enum', 'CUtensorMapFloatOOBfill', - 'CUtensorMapFloatOOBfill__enumvalues', - 'CUtensorMapFloatOOBfill_enum', 'CUtensorMapInterleave', - 'CUtensorMapInterleave__enumvalues', 'CUtensorMapInterleave_enum', - 'CUtensorMapL2promotion', 'CUtensorMapL2promotion__enumvalues', - 'CUtensorMapL2promotion_enum', 'CUtensorMapSwizzle', - 'CUtensorMapSwizzle__enumvalues', 'CUtensorMapSwizzle_enum', - 'CUtexObject', 'CUtexObject_v1', 'CUtexref', 'CUuserObject', - 'CUuserObjectRetain_flags', - 'CUuserObjectRetain_flags__enumvalues', - 'CUuserObjectRetain_flags_enum', 'CUuserObject_flags', - 'CUuserObject_flags__enumvalues', 'CUuserObject_flags_enum', - 'CUuuid', 'NVCL_CTX_SCHED_AUTO', 'NVCL_CTX_SCHED_BLOCKING_SYNC', - 'NVCL_CTX_SCHED_SPIN', 'NVCL_CTX_SCHED_YIELD', - 'NVCL_EVENT_SCHED_AUTO', 'NVCL_EVENT_SCHED_BLOCKING_SYNC', - 'NVCL_EVENT_SCHED_SPIN', 'NVCL_EVENT_SCHED_YIELD', - 'cl_context_flags', 'cl_context_flags__enumvalues', - 'cl_context_flags_enum', 'cl_event_flags', - 'cl_event_flags__enumvalues', 'cl_event_flags_enum', - 'cuArray3DCreate', 'cuArray3DCreate_v2', 'cuArray3DGetDescriptor', - 'cuArray3DGetDescriptor_v2', 'cuArrayCreate', 'cuArrayCreate_v2', - 'cuArrayDestroy', 'cuArrayGetDescriptor', - 'cuArrayGetDescriptor_v2', 'cuArrayGetMemoryRequirements', - 'cuArrayGetPlane', 'cuArrayGetSparseProperties', 'cuCtxAttach', - 'cuCtxCreate', 'cuCtxCreate_v2', 'cuCtxCreate_v3', 'cuCtxDestroy', - 'cuCtxDestroy_v2', 'cuCtxDetach', 'cuCtxDisablePeerAccess', - 'cuCtxEnablePeerAccess', 'cuCtxGetApiVersion', - 'cuCtxGetCacheConfig', 'cuCtxGetCurrent', 'cuCtxGetDevice', - 'cuCtxGetExecAffinity', 'cuCtxGetFlags', 'cuCtxGetId', - 'cuCtxGetLimit', 'cuCtxGetSharedMemConfig', - 'cuCtxGetStreamPriorityRange', 'cuCtxPopCurrent', - 'cuCtxPopCurrent_v2', 'cuCtxPushCurrent', 'cuCtxPushCurrent_v2', - 'cuCtxResetPersistingL2Cache', 'cuCtxSetCacheConfig', - 'cuCtxSetCurrent', 'cuCtxSetLimit', 'cuCtxSetSharedMemConfig', - 'cuCtxSynchronize', 'cuDestroyExternalMemory', - 'cuDestroyExternalSemaphore', 'cuDeviceCanAccessPeer', - 'cuDeviceComputeCapability', 'cuDeviceGet', - 'cuDeviceGetAttribute', 'cuDeviceGetByPCIBusId', - 'cuDeviceGetCount', 'cuDeviceGetDefaultMemPool', - 'cuDeviceGetExecAffinitySupport', 'cuDeviceGetGraphMemAttribute', - 'cuDeviceGetLuid', 'cuDeviceGetMemPool', 'cuDeviceGetName', - 'cuDeviceGetNvSciSyncAttributes', 'cuDeviceGetP2PAttribute', - 'cuDeviceGetPCIBusId', 'cuDeviceGetProperties', - 'cuDeviceGetTexture1DLinearMaxWidth', 'cuDeviceGetUuid', - 'cuDeviceGetUuid_v2', 'cuDeviceGraphMemTrim', - 'cuDevicePrimaryCtxGetState', 'cuDevicePrimaryCtxRelease', - 'cuDevicePrimaryCtxRelease_v2', 'cuDevicePrimaryCtxReset', - 'cuDevicePrimaryCtxReset_v2', 'cuDevicePrimaryCtxRetain', - 'cuDevicePrimaryCtxSetFlags', 'cuDevicePrimaryCtxSetFlags_v2', - 'cuDeviceSetGraphMemAttribute', 'cuDeviceSetMemPool', - 'cuDeviceTotalMem', 'cuDeviceTotalMem_v2', 'cuDriverGetVersion', - 'cuEventCreate', 'cuEventDestroy', 'cuEventDestroy_v2', - 'cuEventElapsedTime', 'cuEventQuery', 'cuEventRecord', - 'cuEventRecordWithFlags', 'cuEventRecordWithFlags_ptsz', - 'cuEventRecord_ptsz', 'cuEventSynchronize', - 'cuExternalMemoryGetMappedBuffer', - 'cuExternalMemoryGetMappedMipmappedArray', - 'cuFlushGPUDirectRDMAWrites', 'cuFuncGetAttribute', - 'cuFuncGetModule', 'cuFuncSetAttribute', 'cuFuncSetBlockShape', - 'cuFuncSetCacheConfig', 'cuFuncSetSharedMemConfig', - 'cuFuncSetSharedSize', 'cuGetErrorName', 'cuGetErrorString', - 'cuGetExportTable', 'cuGetProcAddress', 'cuGetProcAddress_v2', - 'cuGraphAddBatchMemOpNode', 'cuGraphAddChildGraphNode', - 'cuGraphAddDependencies', 'cuGraphAddEmptyNode', - 'cuGraphAddEventRecordNode', 'cuGraphAddEventWaitNode', - 'cuGraphAddExternalSemaphoresSignalNode', - 'cuGraphAddExternalSemaphoresWaitNode', 'cuGraphAddHostNode', - 'cuGraphAddKernelNode', 'cuGraphAddKernelNode_v2', - 'cuGraphAddMemAllocNode', 'cuGraphAddMemFreeNode', - 'cuGraphAddMemcpyNode', 'cuGraphAddMemsetNode', - 'cuGraphBatchMemOpNodeGetParams', - 'cuGraphBatchMemOpNodeSetParams', 'cuGraphChildGraphNodeGetGraph', - 'cuGraphClone', 'cuGraphCreate', 'cuGraphDebugDotPrint', - 'cuGraphDestroy', 'cuGraphDestroyNode', - 'cuGraphEventRecordNodeGetEvent', - 'cuGraphEventRecordNodeSetEvent', 'cuGraphEventWaitNodeGetEvent', - 'cuGraphEventWaitNodeSetEvent', - 'cuGraphExecBatchMemOpNodeSetParams', - 'cuGraphExecChildGraphNodeSetParams', 'cuGraphExecDestroy', - 'cuGraphExecEventRecordNodeSetEvent', - 'cuGraphExecEventWaitNodeSetEvent', - 'cuGraphExecExternalSemaphoresSignalNodeSetParams', - 'cuGraphExecExternalSemaphoresWaitNodeSetParams', - 'cuGraphExecGetFlags', 'cuGraphExecHostNodeSetParams', - 'cuGraphExecKernelNodeSetParams', - 'cuGraphExecKernelNodeSetParams_v2', - 'cuGraphExecMemcpyNodeSetParams', - 'cuGraphExecMemsetNodeSetParams', 'cuGraphExecUpdate', - 'cuGraphExecUpdate_v2', - 'cuGraphExternalSemaphoresSignalNodeGetParams', - 'cuGraphExternalSemaphoresSignalNodeSetParams', - 'cuGraphExternalSemaphoresWaitNodeGetParams', - 'cuGraphExternalSemaphoresWaitNodeSetParams', 'cuGraphGetEdges', - 'cuGraphGetNodes', 'cuGraphGetRootNodes', - 'cuGraphHostNodeGetParams', 'cuGraphHostNodeSetParams', - 'cuGraphInstantiate', 'cuGraphInstantiateWithFlags', - 'cuGraphInstantiateWithParams', - 'cuGraphInstantiateWithParams_ptsz', 'cuGraphInstantiate_v2', - 'cuGraphKernelNodeCopyAttributes', - 'cuGraphKernelNodeGetAttribute', 'cuGraphKernelNodeGetParams', - 'cuGraphKernelNodeGetParams_v2', 'cuGraphKernelNodeSetAttribute', - 'cuGraphKernelNodeSetParams', 'cuGraphKernelNodeSetParams_v2', - 'cuGraphLaunch', 'cuGraphLaunch_ptsz', - 'cuGraphMemAllocNodeGetParams', 'cuGraphMemFreeNodeGetParams', - 'cuGraphMemcpyNodeGetParams', 'cuGraphMemcpyNodeSetParams', - 'cuGraphMemsetNodeGetParams', 'cuGraphMemsetNodeSetParams', - 'cuGraphNodeFindInClone', 'cuGraphNodeGetDependencies', - 'cuGraphNodeGetDependentNodes', 'cuGraphNodeGetEnabled', - 'cuGraphNodeGetType', 'cuGraphNodeSetEnabled', - 'cuGraphReleaseUserObject', 'cuGraphRemoveDependencies', - 'cuGraphRetainUserObject', 'cuGraphUpload', 'cuGraphUpload_ptsz', - 'cuGraphicsMapResources', 'cuGraphicsMapResources_ptsz', - 'cuGraphicsResourceGetMappedMipmappedArray', - 'cuGraphicsResourceGetMappedPointer', - 'cuGraphicsResourceGetMappedPointer_v2', - 'cuGraphicsResourceSetMapFlags', - 'cuGraphicsResourceSetMapFlags_v2', - 'cuGraphicsSubResourceGetMappedArray', 'cuGraphicsUnmapResources', - 'cuGraphicsUnmapResources_ptsz', 'cuGraphicsUnregisterResource', - 'cuImportExternalMemory', 'cuImportExternalSemaphore', 'cuInit', - 'cuIpcCloseMemHandle', 'cuIpcGetEventHandle', 'cuIpcGetMemHandle', - 'cuIpcOpenEventHandle', 'cuIpcOpenMemHandle', - 'cuIpcOpenMemHandle_v2', 'cuKernelGetAttribute', - 'cuKernelGetFunction', 'cuKernelSetAttribute', - 'cuKernelSetCacheConfig', 'cuLaunch', 'cuLaunchCooperativeKernel', - 'cuLaunchCooperativeKernelMultiDevice', - 'cuLaunchCooperativeKernel_ptsz', 'cuLaunchGrid', - 'cuLaunchGridAsync', 'cuLaunchHostFunc', 'cuLaunchHostFunc_ptsz', - 'cuLaunchKernel', 'cuLaunchKernelEx', 'cuLaunchKernelEx_ptsz', - 'cuLaunchKernel_ptsz', 'cuLibraryGetGlobal', 'cuLibraryGetKernel', - 'cuLibraryGetManaged', 'cuLibraryGetModule', - 'cuLibraryGetUnifiedFunction', 'cuLibraryLoadData', - 'cuLibraryLoadFromFile', 'cuLibraryUnload', 'cuLinkAddData', - 'cuLinkAddData_v2', 'cuLinkAddFile', 'cuLinkAddFile_v2', - 'cuLinkComplete', 'cuLinkCreate', 'cuLinkCreate_v2', - 'cuLinkDestroy', 'cuMemAddressFree', 'cuMemAddressReserve', - 'cuMemAdvise', 'cuMemAlloc', 'cuMemAllocAsync', - 'cuMemAllocAsync_ptsz', 'cuMemAllocFromPoolAsync', - 'cuMemAllocFromPoolAsync_ptsz', 'cuMemAllocHost', - 'cuMemAllocHost_v2', 'cuMemAllocManaged', 'cuMemAllocPitch', - 'cuMemAllocPitch_v2', 'cuMemAlloc_v2', 'cuMemCreate', - 'cuMemExportToShareableHandle', 'cuMemFree', 'cuMemFreeAsync', - 'cuMemFreeAsync_ptsz', 'cuMemFreeHost', 'cuMemFree_v2', - 'cuMemGetAccess', 'cuMemGetAddressRange', - 'cuMemGetAddressRange_v2', 'cuMemGetAllocationGranularity', - 'cuMemGetAllocationPropertiesFromHandle', - 'cuMemGetHandleForAddressRange', 'cuMemGetInfo', - 'cuMemGetInfo_v2', 'cuMemHostAlloc', 'cuMemHostGetDevicePointer', - 'cuMemHostGetDevicePointer_v2', 'cuMemHostGetFlags', - 'cuMemHostRegister', 'cuMemHostRegister_v2', - 'cuMemHostUnregister', 'cuMemImportFromShareableHandle', - 'cuMemMap', 'cuMemMapArrayAsync', 'cuMemMapArrayAsync_ptsz', - 'cuMemPoolCreate', 'cuMemPoolDestroy', 'cuMemPoolExportPointer', - 'cuMemPoolExportToShareableHandle', 'cuMemPoolGetAccess', - 'cuMemPoolGetAttribute', 'cuMemPoolImportFromShareableHandle', - 'cuMemPoolImportPointer', 'cuMemPoolSetAccess', - 'cuMemPoolSetAttribute', 'cuMemPoolTrimTo', 'cuMemPrefetchAsync', - 'cuMemPrefetchAsync_ptsz', 'cuMemRangeGetAttribute', - 'cuMemRangeGetAttributes', 'cuMemRelease', - 'cuMemRetainAllocationHandle', 'cuMemSetAccess', 'cuMemUnmap', - 'cuMemcpy', 'cuMemcpy2D', 'cuMemcpy2DAsync', 'cuMemcpy2DAsync_v2', - 'cuMemcpy2DAsync_v2_ptsz', 'cuMemcpy2DUnaligned', - 'cuMemcpy2DUnaligned_v2', 'cuMemcpy2DUnaligned_v2_ptds', - 'cuMemcpy2D_v2', 'cuMemcpy2D_v2_ptds', 'cuMemcpy3D', - 'cuMemcpy3DAsync', 'cuMemcpy3DAsync_v2', - 'cuMemcpy3DAsync_v2_ptsz', 'cuMemcpy3DPeer', - 'cuMemcpy3DPeerAsync', 'cuMemcpy3DPeerAsync_ptsz', - 'cuMemcpy3DPeer_ptds', 'cuMemcpy3D_v2', 'cuMemcpy3D_v2_ptds', - 'cuMemcpyAsync', 'cuMemcpyAsync_ptsz', 'cuMemcpyAtoA', - 'cuMemcpyAtoA_v2', 'cuMemcpyAtoA_v2_ptds', 'cuMemcpyAtoD', - 'cuMemcpyAtoD_v2', 'cuMemcpyAtoD_v2_ptds', 'cuMemcpyAtoH', - 'cuMemcpyAtoHAsync', 'cuMemcpyAtoHAsync_v2', - 'cuMemcpyAtoHAsync_v2_ptsz', 'cuMemcpyAtoH_v2', - 'cuMemcpyAtoH_v2_ptds', 'cuMemcpyDtoA', 'cuMemcpyDtoA_v2', - 'cuMemcpyDtoA_v2_ptds', 'cuMemcpyDtoD', 'cuMemcpyDtoDAsync', - 'cuMemcpyDtoDAsync_v2', 'cuMemcpyDtoDAsync_v2_ptsz', - 'cuMemcpyDtoD_v2', 'cuMemcpyDtoD_v2_ptds', 'cuMemcpyDtoH', - 'cuMemcpyDtoHAsync', 'cuMemcpyDtoHAsync_v2', - 'cuMemcpyDtoHAsync_v2_ptsz', 'cuMemcpyDtoH_v2', - 'cuMemcpyDtoH_v2_ptds', 'cuMemcpyHtoA', 'cuMemcpyHtoAAsync', - 'cuMemcpyHtoAAsync_v2', 'cuMemcpyHtoAAsync_v2_ptsz', - 'cuMemcpyHtoA_v2', 'cuMemcpyHtoA_v2_ptds', 'cuMemcpyHtoD', - 'cuMemcpyHtoDAsync', 'cuMemcpyHtoDAsync_v2', - 'cuMemcpyHtoDAsync_v2_ptsz', 'cuMemcpyHtoD_v2', - 'cuMemcpyHtoD_v2_ptds', 'cuMemcpyPeer', 'cuMemcpyPeerAsync', - 'cuMemcpyPeerAsync_ptsz', 'cuMemcpyPeer_ptds', 'cuMemcpy_ptds', - 'cuMemsetD16', 'cuMemsetD16Async', 'cuMemsetD16Async_ptsz', - 'cuMemsetD16_v2', 'cuMemsetD16_v2_ptds', 'cuMemsetD2D16', - 'cuMemsetD2D16Async', 'cuMemsetD2D16Async_ptsz', - 'cuMemsetD2D16_v2', 'cuMemsetD2D16_v2_ptds', 'cuMemsetD2D32', - 'cuMemsetD2D32Async', 'cuMemsetD2D32Async_ptsz', - 'cuMemsetD2D32_v2', 'cuMemsetD2D32_v2_ptds', 'cuMemsetD2D8', - 'cuMemsetD2D8Async', 'cuMemsetD2D8Async_ptsz', 'cuMemsetD2D8_v2', - 'cuMemsetD2D8_v2_ptds', 'cuMemsetD32', 'cuMemsetD32Async', - 'cuMemsetD32Async_ptsz', 'cuMemsetD32_v2', 'cuMemsetD32_v2_ptds', - 'cuMemsetD8', 'cuMemsetD8Async', 'cuMemsetD8Async_ptsz', - 'cuMemsetD8_v2', 'cuMemsetD8_v2_ptds', 'cuMipmappedArrayCreate', - 'cuMipmappedArrayDestroy', 'cuMipmappedArrayGetLevel', - 'cuMipmappedArrayGetMemoryRequirements', - 'cuMipmappedArrayGetSparseProperties', 'cuModuleGetFunction', - 'cuModuleGetGlobal', 'cuModuleGetGlobal_v2', - 'cuModuleGetLoadingMode', 'cuModuleGetSurfRef', - 'cuModuleGetTexRef', 'cuModuleLoad', 'cuModuleLoadData', - 'cuModuleLoadDataEx', 'cuModuleLoadFatBinary', 'cuModuleUnload', - 'cuOccupancyAvailableDynamicSMemPerBlock', - 'cuOccupancyMaxActiveBlocksPerMultiprocessor', - 'cuOccupancyMaxActiveBlocksPerMultiprocessorWithFlags', - 'cuOccupancyMaxActiveClusters', - 'cuOccupancyMaxPotentialBlockSize', - 'cuOccupancyMaxPotentialBlockSizeWithFlags', - 'cuOccupancyMaxPotentialClusterSize', 'cuParamSetSize', - 'cuParamSetTexRef', 'cuParamSetf', 'cuParamSeti', 'cuParamSetv', - 'cuPointerGetAttribute', 'cuPointerGetAttributes', - 'cuPointerSetAttribute', 'cuSignalExternalSemaphoresAsync', - 'cuSignalExternalSemaphoresAsync_ptsz', 'cuStreamAddCallback', - 'cuStreamAddCallback_ptsz', 'cuStreamAttachMemAsync', - 'cuStreamAttachMemAsync_ptsz', 'cuStreamBatchMemOp', - 'cuStreamBatchMemOp_ptsz', 'cuStreamBatchMemOp_v2', - 'cuStreamBatchMemOp_v2_ptsz', 'cuStreamBeginCapture', - 'cuStreamBeginCapture_ptsz', 'cuStreamBeginCapture_v2', - 'cuStreamBeginCapture_v2_ptsz', 'cuStreamCopyAttributes', - 'cuStreamCopyAttributes_ptsz', 'cuStreamCreate', - 'cuStreamCreateWithPriority', 'cuStreamDestroy', - 'cuStreamDestroy_v2', 'cuStreamEndCapture', - 'cuStreamEndCapture_ptsz', 'cuStreamGetAttribute', - 'cuStreamGetAttribute_ptsz', 'cuStreamGetCaptureInfo', - 'cuStreamGetCaptureInfo_ptsz', 'cuStreamGetCaptureInfo_v2', - 'cuStreamGetCaptureInfo_v2_ptsz', 'cuStreamGetCtx', - 'cuStreamGetCtx_ptsz', 'cuStreamGetFlags', - 'cuStreamGetFlags_ptsz', 'cuStreamGetId', 'cuStreamGetId_ptsz', - 'cuStreamGetPriority', 'cuStreamGetPriority_ptsz', - 'cuStreamIsCapturing', 'cuStreamIsCapturing_ptsz', - 'cuStreamQuery', 'cuStreamQuery_ptsz', 'cuStreamSetAttribute', - 'cuStreamSetAttribute_ptsz', 'cuStreamSynchronize', - 'cuStreamSynchronize_ptsz', 'cuStreamUpdateCaptureDependencies', - 'cuStreamUpdateCaptureDependencies_ptsz', 'cuStreamWaitEvent', - 'cuStreamWaitEvent_ptsz', 'cuStreamWaitValue32', - 'cuStreamWaitValue32_ptsz', 'cuStreamWaitValue32_v2', - 'cuStreamWaitValue32_v2_ptsz', 'cuStreamWaitValue64', - 'cuStreamWaitValue64_ptsz', 'cuStreamWaitValue64_v2', - 'cuStreamWaitValue64_v2_ptsz', 'cuStreamWriteValue32', - 'cuStreamWriteValue32_ptsz', 'cuStreamWriteValue32_v2', - 'cuStreamWriteValue32_v2_ptsz', 'cuStreamWriteValue64', - 'cuStreamWriteValue64_ptsz', 'cuStreamWriteValue64_v2', - 'cuStreamWriteValue64_v2_ptsz', 'cuSurfObjectCreate', - 'cuSurfObjectDestroy', 'cuSurfObjectGetResourceDesc', - 'cuSurfRefGetArray', 'cuSurfRefSetArray', - 'cuTensorMapEncodeIm2col', 'cuTensorMapEncodeTiled', - 'cuTensorMapReplaceAddress', 'cuTexObjectCreate', - 'cuTexObjectDestroy', 'cuTexObjectGetResourceDesc', - 'cuTexObjectGetResourceViewDesc', 'cuTexObjectGetTextureDesc', - 'cuTexRefCreate', 'cuTexRefDestroy', 'cuTexRefGetAddress', - 'cuTexRefGetAddressMode', 'cuTexRefGetAddress_v2', - 'cuTexRefGetArray', 'cuTexRefGetBorderColor', - 'cuTexRefGetFilterMode', 'cuTexRefGetFlags', 'cuTexRefGetFormat', - 'cuTexRefGetMaxAnisotropy', 'cuTexRefGetMipmapFilterMode', - 'cuTexRefGetMipmapLevelBias', 'cuTexRefGetMipmapLevelClamp', - 'cuTexRefGetMipmappedArray', 'cuTexRefSetAddress', - 'cuTexRefSetAddress2D', 'cuTexRefSetAddress2D_v2', - 'cuTexRefSetAddress2D_v3', 'cuTexRefSetAddressMode', - 'cuTexRefSetAddress_v2', 'cuTexRefSetArray', - 'cuTexRefSetBorderColor', 'cuTexRefSetFilterMode', - 'cuTexRefSetFlags', 'cuTexRefSetFormat', - 'cuTexRefSetMaxAnisotropy', 'cuTexRefSetMipmapFilterMode', - 'cuTexRefSetMipmapLevelBias', 'cuTexRefSetMipmapLevelClamp', - 'cuTexRefSetMipmappedArray', 'cuThreadExchangeStreamCaptureMode', - 'cuUserObjectCreate', 'cuUserObjectRelease', 'cuUserObjectRetain', - 'cuWaitExternalSemaphoresAsync', - 'cuWaitExternalSemaphoresAsync_ptsz', 'cudaError_enum', - 'cuuint32_t', 'cuuint64_t', 'size_t', - 'struct_CUDA_ARRAY3D_DESCRIPTOR_st', - 'struct_CUDA_ARRAY3D_DESCRIPTOR_v1_st', - 'struct_CUDA_ARRAY_DESCRIPTOR_st', - 'struct_CUDA_ARRAY_DESCRIPTOR_v1_st', - 'struct_CUDA_ARRAY_MEMORY_REQUIREMENTS_st', - 'struct_CUDA_ARRAY_SPARSE_PROPERTIES_st', - 'struct_CUDA_ARRAY_SPARSE_PROPERTIES_st_tileExtent', - 'struct_CUDA_BATCH_MEM_OP_NODE_PARAMS_st', - 'struct_CUDA_EXTERNAL_MEMORY_BUFFER_DESC_st', - 'struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st', - 'struct_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_0_win32', - 'struct_CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_0_win32', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_fence', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_keyedMutex', - 'struct_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_params', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_fence', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_keyedMutex', - 'struct_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_params', - 'struct_CUDA_EXT_SEM_SIGNAL_NODE_PARAMS_st', - 'struct_CUDA_EXT_SEM_WAIT_NODE_PARAMS_st', - 'struct_CUDA_GRAPH_INSTANTIATE_PARAMS_st', - 'struct_CUDA_HOST_NODE_PARAMS_st', - 'struct_CUDA_KERNEL_NODE_PARAMS_st', - 'struct_CUDA_KERNEL_NODE_PARAMS_v2_st', - 'struct_CUDA_LAUNCH_PARAMS_st', 'struct_CUDA_MEMCPY2D_st', - 'struct_CUDA_MEMCPY2D_v1_st', 'struct_CUDA_MEMCPY3D_PEER_st', - 'struct_CUDA_MEMCPY3D_st', 'struct_CUDA_MEMCPY3D_v1_st', - 'struct_CUDA_MEMSET_NODE_PARAMS_st', - 'struct_CUDA_MEM_ALLOC_NODE_PARAMS_st', - 'struct_CUDA_POINTER_ATTRIBUTE_P2P_TOKENS_st', - 'struct_CUDA_RESOURCE_DESC_st', - 'struct_CUDA_RESOURCE_DESC_st_0_array', - 'struct_CUDA_RESOURCE_DESC_st_0_linear', - 'struct_CUDA_RESOURCE_DESC_st_0_mipmap', - 'struct_CUDA_RESOURCE_DESC_st_0_pitch2D', - 'struct_CUDA_RESOURCE_DESC_st_0_reserved', - 'struct_CUDA_RESOURCE_VIEW_DESC_st', - 'struct_CUDA_TEXTURE_DESC_st', 'struct_CUaccessPolicyWindow_st', - 'struct_CUarrayMapInfo_st', 'struct_CUarrayMapInfo_st_1_miptail', - 'struct_CUarrayMapInfo_st_1_sparseLevel', 'struct_CUarray_st', - 'struct_CUctx_st', 'struct_CUdevprop_st', 'struct_CUevent_st', - 'struct_CUexecAffinityParam_st', - 'struct_CUexecAffinitySmCount_st', 'struct_CUextMemory_st', - 'struct_CUextSemaphore_st', 'struct_CUfunc_st', - 'struct_CUgraphExecUpdateResultInfo_st', 'struct_CUgraphExec_st', - 'struct_CUgraphNode_st', 'struct_CUgraph_st', - 'struct_CUgraphicsResource_st', 'struct_CUipcEventHandle_st', - 'struct_CUipcMemHandle_st', 'struct_CUkern_st', - 'struct_CUlaunchAttributeValue_union_clusterDim', - 'struct_CUlaunchAttributeValue_union_programmaticEvent', - 'struct_CUlaunchAttribute_st', 'struct_CUlaunchConfig_st', - 'struct_CUlaunchMemSyncDomainMap_st', 'struct_CUlib_st', - 'struct_CUlibraryHostUniversalFunctionAndDataTable_st', - 'struct_CUlinkState_st', 'struct_CUmemAccessDesc_st', - 'struct_CUmemAllocationProp_st', - 'struct_CUmemAllocationProp_st_allocFlags', - 'struct_CUmemLocation_st', 'struct_CUmemPoolHandle_st', - 'struct_CUmemPoolProps_st', 'struct_CUmemPoolPtrExportData_st', - 'struct_CUmipmappedArray_st', 'struct_CUmod_st', - 'struct_CUstreamMemOpFlushRemoteWritesParams_st', - 'struct_CUstreamMemOpMemoryBarrierParams_st', - 'struct_CUstreamMemOpWaitValueParams_st', - 'struct_CUstreamMemOpWriteValueParams_st', 'struct_CUstream_st', - 'struct_CUsurfref_st', 'struct_CUtensorMap_st', - 'struct_CUtexref_st', 'struct_CUuserObject_st', - 'struct_CUuuid_st', - 'union_CUDA_EXTERNAL_MEMORY_HANDLE_DESC_st_handle', - 'union_CUDA_EXTERNAL_SEMAPHORE_HANDLE_DESC_st_handle', - 'union_CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS_st_0_nvSciSync', - 'union_CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS_st_0_nvSciSync', - 'union_CUDA_RESOURCE_DESC_st_res', - 'union_CUarrayMapInfo_st_memHandle', - 'union_CUarrayMapInfo_st_resource', - 'union_CUarrayMapInfo_st_subresource', - 'union_CUexecAffinityParam_st_param', - 'union_CUlaunchAttributeValue_union', - 'union_CUstreamBatchMemOpParams_union', - 'union_CUstreamMemOpWaitValueParams_st_0', - 'union_CUstreamMemOpWriteValueParams_st_0'] +# CUresult cuDeviceTotalMem(unsigned int *bytes, CUdevice dev) +try: (cuDeviceTotalMem:=dll.cuDeviceTotalMem).restype, cuDeviceTotalMem.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint32), CUdevice] +except AttributeError: pass + +# CUresult cuCtxCreate(CUcontext *pctx, unsigned int flags, CUdevice dev) +try: (cuCtxCreate:=dll.cuCtxCreate).restype, cuCtxCreate.argtypes = CUresult, [ctypes.POINTER(CUcontext), ctypes.c_uint32, CUdevice] +except AttributeError: pass + +# CUresult cuModuleGetGlobal(CUdeviceptr_v1 *dptr, unsigned int *bytes, CUmodule hmod, const char *name) +try: (cuModuleGetGlobal:=dll.cuModuleGetGlobal).restype, cuModuleGetGlobal.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), ctypes.POINTER(ctypes.c_uint32), CUmodule, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# CUresult cuMemGetInfo(unsigned int *free, unsigned int *total) +try: (cuMemGetInfo:=dll.cuMemGetInfo).restype, cuMemGetInfo.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# CUresult cuMemAlloc(CUdeviceptr_v1 *dptr, unsigned int bytesize) +try: (cuMemAlloc:=dll.cuMemAlloc).restype, cuMemAlloc.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemAllocPitch(CUdeviceptr_v1 *dptr, unsigned int *pPitch, unsigned int WidthInBytes, unsigned int Height, unsigned int ElementSizeBytes) +try: (cuMemAllocPitch:=dll.cuMemAllocPitch).restype, cuMemAllocPitch.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemFree(CUdeviceptr_v1 dptr) +try: (cuMemFree:=dll.cuMemFree).restype, cuMemFree.argtypes = CUresult, [CUdeviceptr_v1] +except AttributeError: pass + +# CUresult cuMemGetAddressRange(CUdeviceptr_v1 *pbase, unsigned int *psize, CUdeviceptr_v1 dptr) +try: (cuMemGetAddressRange:=dll.cuMemGetAddressRange).restype, cuMemGetAddressRange.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), ctypes.POINTER(ctypes.c_uint32), CUdeviceptr_v1] +except AttributeError: pass + +# CUresult cuMemAllocHost(void **pp, unsigned int bytesize) +try: (cuMemAllocHost:=dll.cuMemAllocHost).restype, cuMemAllocHost.argtypes = CUresult, [ctypes.POINTER(ctypes.c_void_p), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemHostGetDevicePointer(CUdeviceptr_v1 *pdptr, void *p, unsigned int Flags) +try: (cuMemHostGetDevicePointer:=dll.cuMemHostGetDevicePointer).restype, cuMemHostGetDevicePointer.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyHtoD(CUdeviceptr_v1 dstDevice, const void *srcHost, unsigned int ByteCount) +try: (cuMemcpyHtoD:=dll.cuMemcpyHtoD).restype, cuMemcpyHtoD.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyDtoH(void *dstHost, CUdeviceptr_v1 srcDevice, unsigned int ByteCount) +try: (cuMemcpyDtoH:=dll.cuMemcpyDtoH).restype, cuMemcpyDtoH.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr_v1, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyDtoD(CUdeviceptr_v1 dstDevice, CUdeviceptr_v1 srcDevice, unsigned int ByteCount) +try: (cuMemcpyDtoD:=dll.cuMemcpyDtoD).restype, cuMemcpyDtoD.argtypes = CUresult, [CUdeviceptr_v1, CUdeviceptr_v1, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyDtoA(CUarray dstArray, unsigned int dstOffset, CUdeviceptr_v1 srcDevice, unsigned int ByteCount) +try: (cuMemcpyDtoA:=dll.cuMemcpyDtoA).restype, cuMemcpyDtoA.argtypes = CUresult, [CUarray, ctypes.c_uint32, CUdeviceptr_v1, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyAtoD(CUdeviceptr_v1 dstDevice, CUarray srcArray, unsigned int srcOffset, unsigned int ByteCount) +try: (cuMemcpyAtoD:=dll.cuMemcpyAtoD).restype, cuMemcpyAtoD.argtypes = CUresult, [CUdeviceptr_v1, CUarray, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyHtoA(CUarray dstArray, unsigned int dstOffset, const void *srcHost, unsigned int ByteCount) +try: (cuMemcpyHtoA:=dll.cuMemcpyHtoA).restype, cuMemcpyHtoA.argtypes = CUresult, [CUarray, ctypes.c_uint32, ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyAtoH(void *dstHost, CUarray srcArray, unsigned int srcOffset, unsigned int ByteCount) +try: (cuMemcpyAtoH:=dll.cuMemcpyAtoH).restype, cuMemcpyAtoH.argtypes = CUresult, [ctypes.c_void_p, CUarray, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyAtoA(CUarray dstArray, unsigned int dstOffset, CUarray srcArray, unsigned int srcOffset, unsigned int ByteCount) +try: (cuMemcpyAtoA:=dll.cuMemcpyAtoA).restype, cuMemcpyAtoA.argtypes = CUresult, [CUarray, ctypes.c_uint32, CUarray, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyHtoAAsync(CUarray dstArray, unsigned int dstOffset, const void *srcHost, unsigned int ByteCount, CUstream hStream) +try: (cuMemcpyHtoAAsync:=dll.cuMemcpyHtoAAsync).restype, cuMemcpyHtoAAsync.argtypes = CUresult, [CUarray, ctypes.c_uint32, ctypes.c_void_p, ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyAtoHAsync(void *dstHost, CUarray srcArray, unsigned int srcOffset, unsigned int ByteCount, CUstream hStream) +try: (cuMemcpyAtoHAsync:=dll.cuMemcpyAtoHAsync).restype, cuMemcpyAtoHAsync.argtypes = CUresult, [ctypes.c_void_p, CUarray, ctypes.c_uint32, ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemcpy2D(const CUDA_MEMCPY2D_v1 *pCopy) +try: (cuMemcpy2D:=dll.cuMemcpy2D).restype, cuMemcpy2D.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D_v1)] +except AttributeError: pass + +# CUresult cuMemcpy2DUnaligned(const CUDA_MEMCPY2D_v1 *pCopy) +try: (cuMemcpy2DUnaligned:=dll.cuMemcpy2DUnaligned).restype, cuMemcpy2DUnaligned.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D_v1)] +except AttributeError: pass + +# CUresult cuMemcpy3D(const CUDA_MEMCPY3D_v1 *pCopy) +try: (cuMemcpy3D:=dll.cuMemcpy3D).restype, cuMemcpy3D.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D_v1)] +except AttributeError: pass + +# CUresult cuMemcpyHtoDAsync(CUdeviceptr_v1 dstDevice, const void *srcHost, unsigned int ByteCount, CUstream hStream) +try: (cuMemcpyHtoDAsync:=dll.cuMemcpyHtoDAsync).restype, cuMemcpyHtoDAsync.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_void_p, ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyDtoHAsync(void *dstHost, CUdeviceptr_v1 srcDevice, unsigned int ByteCount, CUstream hStream) +try: (cuMemcpyDtoHAsync:=dll.cuMemcpyDtoHAsync).restype, cuMemcpyDtoHAsync.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr_v1, ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyDtoDAsync(CUdeviceptr_v1 dstDevice, CUdeviceptr_v1 srcDevice, unsigned int ByteCount, CUstream hStream) +try: (cuMemcpyDtoDAsync:=dll.cuMemcpyDtoDAsync).restype, cuMemcpyDtoDAsync.argtypes = CUresult, [CUdeviceptr_v1, CUdeviceptr_v1, ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemcpy2DAsync(const CUDA_MEMCPY2D_v1 *pCopy, CUstream hStream) +try: (cuMemcpy2DAsync:=dll.cuMemcpy2DAsync).restype, cuMemcpy2DAsync.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D_v1), CUstream] +except AttributeError: pass + +# CUresult cuMemcpy3DAsync(const CUDA_MEMCPY3D_v1 *pCopy, CUstream hStream) +try: (cuMemcpy3DAsync:=dll.cuMemcpy3DAsync).restype, cuMemcpy3DAsync.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D_v1), CUstream] +except AttributeError: pass + +# CUresult cuMemsetD8(CUdeviceptr_v1 dstDevice, unsigned char uc, unsigned int N) +try: (cuMemsetD8:=dll.cuMemsetD8).restype, cuMemsetD8.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_ubyte, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemsetD16(CUdeviceptr_v1 dstDevice, unsigned short us, unsigned int N) +try: (cuMemsetD16:=dll.cuMemsetD16).restype, cuMemsetD16.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_uint16, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemsetD32(CUdeviceptr_v1 dstDevice, unsigned int ui, unsigned int N) +try: (cuMemsetD32:=dll.cuMemsetD32).restype, cuMemsetD32.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemsetD2D8(CUdeviceptr_v1 dstDevice, unsigned int dstPitch, unsigned char uc, unsigned int Width, unsigned int Height) +try: (cuMemsetD2D8:=dll.cuMemsetD2D8).restype, cuMemsetD2D8.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_ubyte, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemsetD2D16(CUdeviceptr_v1 dstDevice, unsigned int dstPitch, unsigned short us, unsigned int Width, unsigned int Height) +try: (cuMemsetD2D16:=dll.cuMemsetD2D16).restype, cuMemsetD2D16.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint16, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemsetD2D32(CUdeviceptr_v1 dstDevice, unsigned int dstPitch, unsigned int ui, unsigned int Width, unsigned int Height) +try: (cuMemsetD2D32:=dll.cuMemsetD2D32).restype, cuMemsetD2D32.argtypes = CUresult, [CUdeviceptr_v1, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuArrayCreate(CUarray *pHandle, const CUDA_ARRAY_DESCRIPTOR_v1 *pAllocateArray) +try: (cuArrayCreate:=dll.cuArrayCreate).restype, cuArrayCreate.argtypes = CUresult, [ctypes.POINTER(CUarray), ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR_v1)] +except AttributeError: pass + +# CUresult cuArrayGetDescriptor(CUDA_ARRAY_DESCRIPTOR_v1 *pArrayDescriptor, CUarray hArray) +try: (cuArrayGetDescriptor:=dll.cuArrayGetDescriptor).restype, cuArrayGetDescriptor.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR_v1), CUarray] +except AttributeError: pass + +# CUresult cuArray3DCreate(CUarray *pHandle, const CUDA_ARRAY3D_DESCRIPTOR_v1 *pAllocateArray) +try: (cuArray3DCreate:=dll.cuArray3DCreate).restype, cuArray3DCreate.argtypes = CUresult, [ctypes.POINTER(CUarray), ctypes.POINTER(CUDA_ARRAY3D_DESCRIPTOR_v1)] +except AttributeError: pass + +# CUresult cuArray3DGetDescriptor(CUDA_ARRAY3D_DESCRIPTOR_v1 *pArrayDescriptor, CUarray hArray) +try: (cuArray3DGetDescriptor:=dll.cuArray3DGetDescriptor).restype, cuArray3DGetDescriptor.argtypes = CUresult, [ctypes.POINTER(CUDA_ARRAY3D_DESCRIPTOR_v1), CUarray] +except AttributeError: pass + +# CUresult cuTexRefSetAddress(unsigned int *ByteOffset, CUtexref hTexRef, CUdeviceptr_v1 dptr, unsigned int bytes) +try: (cuTexRefSetAddress:=dll.cuTexRefSetAddress).restype, cuTexRefSetAddress.argtypes = CUresult, [ctypes.POINTER(ctypes.c_uint32), CUtexref, CUdeviceptr_v1, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuTexRefSetAddress2D(CUtexref hTexRef, const CUDA_ARRAY_DESCRIPTOR_v1 *desc, CUdeviceptr_v1 dptr, unsigned int Pitch) +try: (cuTexRefSetAddress2D:=dll.cuTexRefSetAddress2D).restype, cuTexRefSetAddress2D.argtypes = CUresult, [CUtexref, ctypes.POINTER(CUDA_ARRAY_DESCRIPTOR_v1), CUdeviceptr_v1, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuTexRefGetAddress(CUdeviceptr_v1 *pdptr, CUtexref hTexRef) +try: (cuTexRefGetAddress:=dll.cuTexRefGetAddress).restype, cuTexRefGetAddress.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), CUtexref] +except AttributeError: pass + +# CUresult cuGraphicsResourceGetMappedPointer(CUdeviceptr_v1 *pDevPtr, unsigned int *pSize, CUgraphicsResource resource) +try: (cuGraphicsResourceGetMappedPointer:=dll.cuGraphicsResourceGetMappedPointer).restype, cuGraphicsResourceGetMappedPointer.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr_v1), ctypes.POINTER(ctypes.c_uint32), CUgraphicsResource] +except AttributeError: pass + +# CUresult cuCtxDestroy(CUcontext ctx) +try: (cuCtxDestroy:=dll.cuCtxDestroy).restype, cuCtxDestroy.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuCtxPopCurrent(CUcontext *pctx) +try: (cuCtxPopCurrent:=dll.cuCtxPopCurrent).restype, cuCtxPopCurrent.argtypes = CUresult, [ctypes.POINTER(CUcontext)] +except AttributeError: pass + +# CUresult cuCtxPushCurrent(CUcontext ctx) +try: (cuCtxPushCurrent:=dll.cuCtxPushCurrent).restype, cuCtxPushCurrent.argtypes = CUresult, [CUcontext] +except AttributeError: pass + +# CUresult cuStreamDestroy(CUstream hStream) +try: (cuStreamDestroy:=dll.cuStreamDestroy).restype, cuStreamDestroy.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuEventDestroy(CUevent hEvent) +try: (cuEventDestroy:=dll.cuEventDestroy).restype, cuEventDestroy.argtypes = CUresult, [CUevent] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxRelease(CUdevice dev) +try: (cuDevicePrimaryCtxRelease:=dll.cuDevicePrimaryCtxRelease).restype, cuDevicePrimaryCtxRelease.argtypes = CUresult, [CUdevice] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxReset(CUdevice dev) +try: (cuDevicePrimaryCtxReset:=dll.cuDevicePrimaryCtxReset).restype, cuDevicePrimaryCtxReset.argtypes = CUresult, [CUdevice] +except AttributeError: pass + +# CUresult cuDevicePrimaryCtxSetFlags(CUdevice dev, unsigned int flags) +try: (cuDevicePrimaryCtxSetFlags:=dll.cuDevicePrimaryCtxSetFlags).restype, cuDevicePrimaryCtxSetFlags.argtypes = CUresult, [CUdevice, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemcpyHtoD_v2(CUdeviceptr dstDevice, const void *srcHost, size_t ByteCount) +try: (cuMemcpyHtoD_v2:=dll.cuMemcpyHtoD_v2).restype, cuMemcpyHtoD_v2.argtypes = CUresult, [CUdeviceptr, ctypes.c_void_p, size_t] +except AttributeError: pass + +# CUresult cuMemcpyDtoH_v2(void *dstHost, CUdeviceptr srcDevice, size_t ByteCount) +try: (cuMemcpyDtoH_v2:=dll.cuMemcpyDtoH_v2).restype, cuMemcpyDtoH_v2.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyDtoD_v2(CUdeviceptr dstDevice, CUdeviceptr srcDevice, size_t ByteCount) +try: (cuMemcpyDtoD_v2:=dll.cuMemcpyDtoD_v2).restype, cuMemcpyDtoD_v2.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyDtoA_v2(CUarray dstArray, size_t dstOffset, CUdeviceptr srcDevice, size_t ByteCount) +try: (cuMemcpyDtoA_v2:=dll.cuMemcpyDtoA_v2).restype, cuMemcpyDtoA_v2.argtypes = CUresult, [CUarray, size_t, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAtoD_v2(CUdeviceptr dstDevice, CUarray srcArray, size_t srcOffset, size_t ByteCount) +try: (cuMemcpyAtoD_v2:=dll.cuMemcpyAtoD_v2).restype, cuMemcpyAtoD_v2.argtypes = CUresult, [CUdeviceptr, CUarray, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpyHtoA_v2(CUarray dstArray, size_t dstOffset, const void *srcHost, size_t ByteCount) +try: (cuMemcpyHtoA_v2:=dll.cuMemcpyHtoA_v2).restype, cuMemcpyHtoA_v2.argtypes = CUresult, [CUarray, size_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAtoH_v2(void *dstHost, CUarray srcArray, size_t srcOffset, size_t ByteCount) +try: (cuMemcpyAtoH_v2:=dll.cuMemcpyAtoH_v2).restype, cuMemcpyAtoH_v2.argtypes = CUresult, [ctypes.c_void_p, CUarray, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAtoA_v2(CUarray dstArray, size_t dstOffset, CUarray srcArray, size_t srcOffset, size_t ByteCount) +try: (cuMemcpyAtoA_v2:=dll.cuMemcpyAtoA_v2).restype, cuMemcpyAtoA_v2.argtypes = CUresult, [CUarray, size_t, CUarray, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpyHtoAAsync_v2(CUarray dstArray, size_t dstOffset, const void *srcHost, size_t ByteCount, CUstream hStream) +try: (cuMemcpyHtoAAsync_v2:=dll.cuMemcpyHtoAAsync_v2).restype, cuMemcpyHtoAAsync_v2.argtypes = CUresult, [CUarray, size_t, ctypes.c_void_p, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyAtoHAsync_v2(void *dstHost, CUarray srcArray, size_t srcOffset, size_t ByteCount, CUstream hStream) +try: (cuMemcpyAtoHAsync_v2:=dll.cuMemcpyAtoHAsync_v2).restype, cuMemcpyAtoHAsync_v2.argtypes = CUresult, [ctypes.c_void_p, CUarray, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpy2D_v2(const CUDA_MEMCPY2D *pCopy) +try: (cuMemcpy2D_v2:=dll.cuMemcpy2D_v2).restype, cuMemcpy2D_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D)] +except AttributeError: pass + +# CUresult cuMemcpy2DUnaligned_v2(const CUDA_MEMCPY2D *pCopy) +try: (cuMemcpy2DUnaligned_v2:=dll.cuMemcpy2DUnaligned_v2).restype, cuMemcpy2DUnaligned_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D)] +except AttributeError: pass + +# CUresult cuMemcpy3D_v2(const CUDA_MEMCPY3D *pCopy) +try: (cuMemcpy3D_v2:=dll.cuMemcpy3D_v2).restype, cuMemcpy3D_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D)] +except AttributeError: pass + +# CUresult cuMemcpyHtoDAsync_v2(CUdeviceptr dstDevice, const void *srcHost, size_t ByteCount, CUstream hStream) +try: (cuMemcpyHtoDAsync_v2:=dll.cuMemcpyHtoDAsync_v2).restype, cuMemcpyHtoDAsync_v2.argtypes = CUresult, [CUdeviceptr, ctypes.c_void_p, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyDtoHAsync_v2(void *dstHost, CUdeviceptr srcDevice, size_t ByteCount, CUstream hStream) +try: (cuMemcpyDtoHAsync_v2:=dll.cuMemcpyDtoHAsync_v2).restype, cuMemcpyDtoHAsync_v2.argtypes = CUresult, [ctypes.c_void_p, CUdeviceptr, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyDtoDAsync_v2(CUdeviceptr dstDevice, CUdeviceptr srcDevice, size_t ByteCount, CUstream hStream) +try: (cuMemcpyDtoDAsync_v2:=dll.cuMemcpyDtoDAsync_v2).restype, cuMemcpyDtoDAsync_v2.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpy2DAsync_v2(const CUDA_MEMCPY2D *pCopy, CUstream hStream) +try: (cuMemcpy2DAsync_v2:=dll.cuMemcpy2DAsync_v2).restype, cuMemcpy2DAsync_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY2D), CUstream] +except AttributeError: pass + +# CUresult cuMemcpy3DAsync_v2(const CUDA_MEMCPY3D *pCopy, CUstream hStream) +try: (cuMemcpy3DAsync_v2:=dll.cuMemcpy3DAsync_v2).restype, cuMemcpy3DAsync_v2.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D), CUstream] +except AttributeError: pass + +# CUresult cuMemsetD8_v2(CUdeviceptr dstDevice, unsigned char uc, size_t N) +try: (cuMemsetD8_v2:=dll.cuMemsetD8_v2).restype, cuMemsetD8_v2.argtypes = CUresult, [CUdeviceptr, ctypes.c_ubyte, size_t] +except AttributeError: pass + +# CUresult cuMemsetD16_v2(CUdeviceptr dstDevice, unsigned short us, size_t N) +try: (cuMemsetD16_v2:=dll.cuMemsetD16_v2).restype, cuMemsetD16_v2.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint16, size_t] +except AttributeError: pass + +# CUresult cuMemsetD32_v2(CUdeviceptr dstDevice, unsigned int ui, size_t N) +try: (cuMemsetD32_v2:=dll.cuMemsetD32_v2).restype, cuMemsetD32_v2.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint32, size_t] +except AttributeError: pass + +# CUresult cuMemsetD2D8_v2(CUdeviceptr dstDevice, size_t dstPitch, unsigned char uc, size_t Width, size_t Height) +try: (cuMemsetD2D8_v2:=dll.cuMemsetD2D8_v2).restype, cuMemsetD2D8_v2.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemsetD2D16_v2(CUdeviceptr dstDevice, size_t dstPitch, unsigned short us, size_t Width, size_t Height) +try: (cuMemsetD2D16_v2:=dll.cuMemsetD2D16_v2).restype, cuMemsetD2D16_v2.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemsetD2D32_v2(CUdeviceptr dstDevice, size_t dstPitch, unsigned int ui, size_t Width, size_t Height) +try: (cuMemsetD2D32_v2:=dll.cuMemsetD2D32_v2).restype, cuMemsetD2D32_v2.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t] +except AttributeError: pass + +# CUresult cuMemcpy(CUdeviceptr dst, CUdeviceptr src, size_t ByteCount) +try: (cuMemcpy:=dll.cuMemcpy).restype, cuMemcpy.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t] +except AttributeError: pass + +# CUresult cuMemcpyAsync(CUdeviceptr dst, CUdeviceptr src, size_t ByteCount, CUstream hStream) +try: (cuMemcpyAsync:=dll.cuMemcpyAsync).restype, cuMemcpyAsync.argtypes = CUresult, [CUdeviceptr, CUdeviceptr, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpyPeer(CUdeviceptr dstDevice, CUcontext dstContext, CUdeviceptr srcDevice, CUcontext srcContext, size_t ByteCount) +try: (cuMemcpyPeer:=dll.cuMemcpyPeer).restype, cuMemcpyPeer.argtypes = CUresult, [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t] +except AttributeError: pass + +# CUresult cuMemcpyPeerAsync(CUdeviceptr dstDevice, CUcontext dstContext, CUdeviceptr srcDevice, CUcontext srcContext, size_t ByteCount, CUstream hStream) +try: (cuMemcpyPeerAsync:=dll.cuMemcpyPeerAsync).restype, cuMemcpyPeerAsync.argtypes = CUresult, [CUdeviceptr, CUcontext, CUdeviceptr, CUcontext, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemcpy3DPeer(const CUDA_MEMCPY3D_PEER *pCopy) +try: (cuMemcpy3DPeer:=dll.cuMemcpy3DPeer).restype, cuMemcpy3DPeer.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D_PEER)] +except AttributeError: pass + +# CUresult cuMemcpy3DPeerAsync(const CUDA_MEMCPY3D_PEER *pCopy, CUstream hStream) +try: (cuMemcpy3DPeerAsync:=dll.cuMemcpy3DPeerAsync).restype, cuMemcpy3DPeerAsync.argtypes = CUresult, [ctypes.POINTER(CUDA_MEMCPY3D_PEER), CUstream] +except AttributeError: pass + +# CUresult cuMemsetD8Async(CUdeviceptr dstDevice, unsigned char uc, size_t N, CUstream hStream) +try: (cuMemsetD8Async:=dll.cuMemsetD8Async).restype, cuMemsetD8Async.argtypes = CUresult, [CUdeviceptr, ctypes.c_ubyte, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD16Async(CUdeviceptr dstDevice, unsigned short us, size_t N, CUstream hStream) +try: (cuMemsetD16Async:=dll.cuMemsetD16Async).restype, cuMemsetD16Async.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint16, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD32Async(CUdeviceptr dstDevice, unsigned int ui, size_t N, CUstream hStream) +try: (cuMemsetD32Async:=dll.cuMemsetD32Async).restype, cuMemsetD32Async.argtypes = CUresult, [CUdeviceptr, ctypes.c_uint32, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD2D8Async(CUdeviceptr dstDevice, size_t dstPitch, unsigned char uc, size_t Width, size_t Height, CUstream hStream) +try: (cuMemsetD2D8Async:=dll.cuMemsetD2D8Async).restype, cuMemsetD2D8Async.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_ubyte, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD2D16Async(CUdeviceptr dstDevice, size_t dstPitch, unsigned short us, size_t Width, size_t Height, CUstream hStream) +try: (cuMemsetD2D16Async:=dll.cuMemsetD2D16Async).restype, cuMemsetD2D16Async.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint16, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemsetD2D32Async(CUdeviceptr dstDevice, size_t dstPitch, unsigned int ui, size_t Width, size_t Height, CUstream hStream) +try: (cuMemsetD2D32Async:=dll.cuMemsetD2D32Async).restype, cuMemsetD2D32Async.argtypes = CUresult, [CUdeviceptr, size_t, ctypes.c_uint32, size_t, size_t, CUstream] +except AttributeError: pass + +# CUresult cuStreamGetPriority(CUstream hStream, int *priority) +try: (cuStreamGetPriority:=dll.cuStreamGetPriority).restype, cuStreamGetPriority.argtypes = CUresult, [CUstream, ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# CUresult cuStreamGetId(CUstream hStream, unsigned long long *streamId) +try: (cuStreamGetId:=dll.cuStreamGetId).restype, cuStreamGetId.argtypes = CUresult, [CUstream, ctypes.POINTER(ctypes.c_uint64)] +except AttributeError: pass + +# CUresult cuStreamGetFlags(CUstream hStream, unsigned int *flags) +try: (cuStreamGetFlags:=dll.cuStreamGetFlags).restype, cuStreamGetFlags.argtypes = CUresult, [CUstream, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# CUresult cuStreamGetCtx(CUstream hStream, CUcontext *pctx) +try: (cuStreamGetCtx:=dll.cuStreamGetCtx).restype, cuStreamGetCtx.argtypes = CUresult, [CUstream, ctypes.POINTER(CUcontext)] +except AttributeError: pass + +# CUresult cuStreamWaitEvent(CUstream hStream, CUevent hEvent, unsigned int Flags) +try: (cuStreamWaitEvent:=dll.cuStreamWaitEvent).restype, cuStreamWaitEvent.argtypes = CUresult, [CUstream, CUevent, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamAddCallback(CUstream hStream, CUstreamCallback callback, void *userData, unsigned int flags) +try: (cuStreamAddCallback:=dll.cuStreamAddCallback).restype, cuStreamAddCallback.argtypes = CUresult, [CUstream, CUstreamCallback, ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamAttachMemAsync(CUstream hStream, CUdeviceptr dptr, size_t length, unsigned int flags) +try: (cuStreamAttachMemAsync:=dll.cuStreamAttachMemAsync).restype, cuStreamAttachMemAsync.argtypes = CUresult, [CUstream, CUdeviceptr, size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamQuery(CUstream hStream) +try: (cuStreamQuery:=dll.cuStreamQuery).restype, cuStreamQuery.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuStreamSynchronize(CUstream hStream) +try: (cuStreamSynchronize:=dll.cuStreamSynchronize).restype, cuStreamSynchronize.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuEventRecord(CUevent hEvent, CUstream hStream) +try: (cuEventRecord:=dll.cuEventRecord).restype, cuEventRecord.argtypes = CUresult, [CUevent, CUstream] +except AttributeError: pass + +# CUresult cuEventRecordWithFlags(CUevent hEvent, CUstream hStream, unsigned int flags) +try: (cuEventRecordWithFlags:=dll.cuEventRecordWithFlags).restype, cuEventRecordWithFlags.argtypes = CUresult, [CUevent, CUstream, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuLaunchKernel(CUfunction f, unsigned int gridDimX, unsigned int gridDimY, unsigned int gridDimZ, unsigned int blockDimX, unsigned int blockDimY, unsigned int blockDimZ, unsigned int sharedMemBytes, CUstream hStream, void **kernelParams, void **extra) +try: (cuLaunchKernel:=dll.cuLaunchKernel).restype, cuLaunchKernel.argtypes = CUresult, [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLaunchKernelEx(const CUlaunchConfig *config, CUfunction f, void **kernelParams, void **extra) +try: (cuLaunchKernelEx:=dll.cuLaunchKernelEx).restype, cuLaunchKernelEx.argtypes = CUresult, [ctypes.POINTER(CUlaunchConfig), CUfunction, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuLaunchHostFunc(CUstream hStream, CUhostFn fn, void *userData) +try: (cuLaunchHostFunc:=dll.cuLaunchHostFunc).restype, cuLaunchHostFunc.argtypes = CUresult, [CUstream, CUhostFn, ctypes.c_void_p] +except AttributeError: pass + +# CUresult cuGraphicsMapResources(unsigned int count, CUgraphicsResource *resources, CUstream hStream) +try: (cuGraphicsMapResources:=dll.cuGraphicsMapResources).restype, cuGraphicsMapResources.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUgraphicsResource), CUstream] +except AttributeError: pass + +# CUresult cuGraphicsUnmapResources(unsigned int count, CUgraphicsResource *resources, CUstream hStream) +try: (cuGraphicsUnmapResources:=dll.cuGraphicsUnmapResources).restype, cuGraphicsUnmapResources.argtypes = CUresult, [ctypes.c_uint32, ctypes.POINTER(CUgraphicsResource), CUstream] +except AttributeError: pass + +# CUresult cuStreamWriteValue32(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWriteValue32:=dll.cuStreamWriteValue32).restype, cuStreamWriteValue32.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue32(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWaitValue32:=dll.cuStreamWaitValue32).restype, cuStreamWaitValue32.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue64(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWriteValue64:=dll.cuStreamWriteValue64).restype, cuStreamWriteValue64.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue64(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWaitValue64:=dll.cuStreamWaitValue64).restype, cuStreamWaitValue64.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamBatchMemOp(CUstream stream, unsigned int count, CUstreamBatchMemOpParams *paramArray, unsigned int flags) +try: (cuStreamBatchMemOp:=dll.cuStreamBatchMemOp).restype, cuStreamBatchMemOp.argtypes = CUresult, [CUstream, ctypes.c_uint32, ctypes.POINTER(CUstreamBatchMemOpParams), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue32_ptsz(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWriteValue32_ptsz:=dll.cuStreamWriteValue32_ptsz).restype, cuStreamWriteValue32_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue32_ptsz(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWaitValue32_ptsz:=dll.cuStreamWaitValue32_ptsz).restype, cuStreamWaitValue32_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue64_ptsz(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWriteValue64_ptsz:=dll.cuStreamWriteValue64_ptsz).restype, cuStreamWriteValue64_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue64_ptsz(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWaitValue64_ptsz:=dll.cuStreamWaitValue64_ptsz).restype, cuStreamWaitValue64_ptsz.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamBatchMemOp_ptsz(CUstream stream, unsigned int count, CUstreamBatchMemOpParams *paramArray, unsigned int flags) +try: (cuStreamBatchMemOp_ptsz:=dll.cuStreamBatchMemOp_ptsz).restype, cuStreamBatchMemOp_ptsz.argtypes = CUresult, [CUstream, ctypes.c_uint32, ctypes.POINTER(CUstreamBatchMemOpParams), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue32_v2(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWriteValue32_v2:=dll.cuStreamWriteValue32_v2).restype, cuStreamWriteValue32_v2.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue32_v2(CUstream stream, CUdeviceptr addr, cuuint32_t value, unsigned int flags) +try: (cuStreamWaitValue32_v2:=dll.cuStreamWaitValue32_v2).restype, cuStreamWaitValue32_v2.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint32_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWriteValue64_v2(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWriteValue64_v2:=dll.cuStreamWriteValue64_v2).restype, cuStreamWriteValue64_v2.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamWaitValue64_v2(CUstream stream, CUdeviceptr addr, cuuint64_t value, unsigned int flags) +try: (cuStreamWaitValue64_v2:=dll.cuStreamWaitValue64_v2).restype, cuStreamWaitValue64_v2.argtypes = CUresult, [CUstream, CUdeviceptr, cuuint64_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuStreamBatchMemOp_v2(CUstream stream, unsigned int count, CUstreamBatchMemOpParams *paramArray, unsigned int flags) +try: (cuStreamBatchMemOp_v2:=dll.cuStreamBatchMemOp_v2).restype, cuStreamBatchMemOp_v2.argtypes = CUresult, [CUstream, ctypes.c_uint32, ctypes.POINTER(CUstreamBatchMemOpParams), ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuMemPrefetchAsync(CUdeviceptr devPtr, size_t count, CUdevice dstDevice, CUstream hStream) +try: (cuMemPrefetchAsync:=dll.cuMemPrefetchAsync).restype, cuMemPrefetchAsync.argtypes = CUresult, [CUdeviceptr, size_t, CUdevice, CUstream] +except AttributeError: pass + +# CUresult cuLaunchCooperativeKernel(CUfunction f, unsigned int gridDimX, unsigned int gridDimY, unsigned int gridDimZ, unsigned int blockDimX, unsigned int blockDimY, unsigned int blockDimZ, unsigned int sharedMemBytes, CUstream hStream, void **kernelParams) +try: (cuLaunchCooperativeKernel:=dll.cuLaunchCooperativeKernel).restype, cuLaunchCooperativeKernel.argtypes = CUresult, [CUfunction, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, CUstream, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# CUresult cuSignalExternalSemaphoresAsync(const CUexternalSemaphore *extSemArray, const CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS *paramsArray, unsigned int numExtSems, CUstream stream) +try: (cuSignalExternalSemaphoresAsync:=dll.cuSignalExternalSemaphoresAsync).restype, cuSignalExternalSemaphoresAsync.argtypes = CUresult, [ctypes.POINTER(CUexternalSemaphore), ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_SIGNAL_PARAMS), ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuWaitExternalSemaphoresAsync(const CUexternalSemaphore *extSemArray, const CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS *paramsArray, unsigned int numExtSems, CUstream stream) +try: (cuWaitExternalSemaphoresAsync:=dll.cuWaitExternalSemaphoresAsync).restype, cuWaitExternalSemaphoresAsync.argtypes = CUresult, [ctypes.POINTER(CUexternalSemaphore), ctypes.POINTER(CUDA_EXTERNAL_SEMAPHORE_WAIT_PARAMS), ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuStreamBeginCapture(CUstream hStream) +try: (cuStreamBeginCapture:=dll.cuStreamBeginCapture).restype, cuStreamBeginCapture.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuStreamBeginCapture_ptsz(CUstream hStream) +try: (cuStreamBeginCapture_ptsz:=dll.cuStreamBeginCapture_ptsz).restype, cuStreamBeginCapture_ptsz.argtypes = CUresult, [CUstream] +except AttributeError: pass + +# CUresult cuStreamBeginCapture_v2(CUstream hStream, CUstreamCaptureMode mode) +try: (cuStreamBeginCapture_v2:=dll.cuStreamBeginCapture_v2).restype, cuStreamBeginCapture_v2.argtypes = CUresult, [CUstream, CUstreamCaptureMode] +except AttributeError: pass + +# CUresult cuStreamEndCapture(CUstream hStream, CUgraph *phGraph) +try: (cuStreamEndCapture:=dll.cuStreamEndCapture).restype, cuStreamEndCapture.argtypes = CUresult, [CUstream, ctypes.POINTER(CUgraph)] +except AttributeError: pass + +# CUresult cuStreamIsCapturing(CUstream hStream, CUstreamCaptureStatus *captureStatus) +try: (cuStreamIsCapturing:=dll.cuStreamIsCapturing).restype, cuStreamIsCapturing.argtypes = CUresult, [CUstream, ctypes.POINTER(CUstreamCaptureStatus)] +except AttributeError: pass + +# CUresult cuStreamGetCaptureInfo(CUstream hStream, CUstreamCaptureStatus *captureStatus_out, cuuint64_t *id_out) +try: (cuStreamGetCaptureInfo:=dll.cuStreamGetCaptureInfo).restype, cuStreamGetCaptureInfo.argtypes = CUresult, [CUstream, ctypes.POINTER(CUstreamCaptureStatus), ctypes.POINTER(cuuint64_t)] +except AttributeError: pass + +# CUresult cuStreamGetCaptureInfo_ptsz(CUstream hStream, CUstreamCaptureStatus *captureStatus_out, cuuint64_t *id_out) +try: (cuStreamGetCaptureInfo_ptsz:=dll.cuStreamGetCaptureInfo_ptsz).restype, cuStreamGetCaptureInfo_ptsz.argtypes = CUresult, [CUstream, ctypes.POINTER(CUstreamCaptureStatus), ctypes.POINTER(cuuint64_t)] +except AttributeError: pass + +# CUresult cuStreamGetCaptureInfo_v2(CUstream hStream, CUstreamCaptureStatus *captureStatus_out, cuuint64_t *id_out, CUgraph *graph_out, const CUgraphNode **dependencies_out, size_t *numDependencies_out) +try: (cuStreamGetCaptureInfo_v2:=dll.cuStreamGetCaptureInfo_v2).restype, cuStreamGetCaptureInfo_v2.argtypes = CUresult, [CUstream, ctypes.POINTER(CUstreamCaptureStatus), ctypes.POINTER(cuuint64_t), ctypes.POINTER(CUgraph), ctypes.POINTER(ctypes.POINTER(CUgraphNode)), ctypes.POINTER(size_t)] +except AttributeError: pass + +# CUresult cuGraphAddKernelNode(CUgraphNode *phGraphNode, CUgraph hGraph, const CUgraphNode *dependencies, size_t numDependencies, const CUDA_KERNEL_NODE_PARAMS_v1 *nodeParams) +try: (cuGraphAddKernelNode:=dll.cuGraphAddKernelNode).restype, cuGraphAddKernelNode.argtypes = CUresult, [ctypes.POINTER(CUgraphNode), CUgraph, ctypes.POINTER(CUgraphNode), size_t, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS_v1)] +except AttributeError: pass + +# CUresult cuGraphKernelNodeGetParams(CUgraphNode hNode, CUDA_KERNEL_NODE_PARAMS_v1 *nodeParams) +try: (cuGraphKernelNodeGetParams:=dll.cuGraphKernelNodeGetParams).restype, cuGraphKernelNodeGetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS_v1)] +except AttributeError: pass + +# CUresult cuGraphKernelNodeSetParams(CUgraphNode hNode, const CUDA_KERNEL_NODE_PARAMS_v1 *nodeParams) +try: (cuGraphKernelNodeSetParams:=dll.cuGraphKernelNodeSetParams).restype, cuGraphKernelNodeSetParams.argtypes = CUresult, [CUgraphNode, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS_v1)] +except AttributeError: pass + +# CUresult cuGraphExecKernelNodeSetParams(CUgraphExec hGraphExec, CUgraphNode hNode, const CUDA_KERNEL_NODE_PARAMS_v1 *nodeParams) +try: (cuGraphExecKernelNodeSetParams:=dll.cuGraphExecKernelNodeSetParams).restype, cuGraphExecKernelNodeSetParams.argtypes = CUresult, [CUgraphExec, CUgraphNode, ctypes.POINTER(CUDA_KERNEL_NODE_PARAMS_v1)] +except AttributeError: pass + +# CUresult cuGraphInstantiateWithParams(CUgraphExec *phGraphExec, CUgraph hGraph, CUDA_GRAPH_INSTANTIATE_PARAMS *instantiateParams) +try: (cuGraphInstantiateWithParams:=dll.cuGraphInstantiateWithParams).restype, cuGraphInstantiateWithParams.argtypes = CUresult, [ctypes.POINTER(CUgraphExec), CUgraph, ctypes.POINTER(CUDA_GRAPH_INSTANTIATE_PARAMS)] +except AttributeError: pass + +# CUresult cuGraphExecUpdate(CUgraphExec hGraphExec, CUgraph hGraph, CUgraphNode *hErrorNode_out, CUgraphExecUpdateResult *updateResult_out) +try: (cuGraphExecUpdate:=dll.cuGraphExecUpdate).restype, cuGraphExecUpdate.argtypes = CUresult, [CUgraphExec, CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(CUgraphExecUpdateResult)] +except AttributeError: pass + +# CUresult cuGraphUpload(CUgraphExec hGraph, CUstream hStream) +try: (cuGraphUpload:=dll.cuGraphUpload).restype, cuGraphUpload.argtypes = CUresult, [CUgraphExec, CUstream] +except AttributeError: pass + +# CUresult cuGraphLaunch(CUgraphExec hGraph, CUstream hStream) +try: (cuGraphLaunch:=dll.cuGraphLaunch).restype, cuGraphLaunch.argtypes = CUresult, [CUgraphExec, CUstream] +except AttributeError: pass + +# CUresult cuStreamCopyAttributes(CUstream dstStream, CUstream srcStream) +try: (cuStreamCopyAttributes:=dll.cuStreamCopyAttributes).restype, cuStreamCopyAttributes.argtypes = CUresult, [CUstream, CUstream] +except AttributeError: pass + +# CUresult cuStreamGetAttribute(CUstream hStream, CUstreamAttrID attr, CUstreamAttrValue *value) +try: (cuStreamGetAttribute:=dll.cuStreamGetAttribute).restype, cuStreamGetAttribute.argtypes = CUresult, [CUstream, CUstreamAttrID, ctypes.POINTER(CUstreamAttrValue)] +except AttributeError: pass + +# CUresult cuStreamSetAttribute(CUstream hStream, CUstreamAttrID attr, const CUstreamAttrValue *param) +try: (cuStreamSetAttribute:=dll.cuStreamSetAttribute).restype, cuStreamSetAttribute.argtypes = CUresult, [CUstream, CUstreamAttrID, ctypes.POINTER(CUstreamAttrValue)] +except AttributeError: pass + +# CUresult cuIpcOpenMemHandle(CUdeviceptr *pdptr, CUipcMemHandle handle, unsigned int Flags) +try: (cuIpcOpenMemHandle:=dll.cuIpcOpenMemHandle).restype, cuIpcOpenMemHandle.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), CUipcMemHandle, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGraphInstantiate(CUgraphExec *phGraphExec, CUgraph hGraph, CUgraphNode *phErrorNode, char *logBuffer, size_t bufferSize) +try: (cuGraphInstantiate:=dll.cuGraphInstantiate).restype, cuGraphInstantiate.argtypes = CUresult, [ctypes.POINTER(CUgraphExec), CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# CUresult cuGraphInstantiate_v2(CUgraphExec *phGraphExec, CUgraph hGraph, CUgraphNode *phErrorNode, char *logBuffer, size_t bufferSize) +try: (cuGraphInstantiate_v2:=dll.cuGraphInstantiate_v2).restype, cuGraphInstantiate_v2.argtypes = CUresult, [ctypes.POINTER(CUgraphExec), CUgraph, ctypes.POINTER(CUgraphNode), ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# CUresult cuMemMapArrayAsync(CUarrayMapInfo *mapInfoList, unsigned int count, CUstream hStream) +try: (cuMemMapArrayAsync:=dll.cuMemMapArrayAsync).restype, cuMemMapArrayAsync.argtypes = CUresult, [ctypes.POINTER(CUarrayMapInfo), ctypes.c_uint32, CUstream] +except AttributeError: pass + +# CUresult cuMemFreeAsync(CUdeviceptr dptr, CUstream hStream) +try: (cuMemFreeAsync:=dll.cuMemFreeAsync).restype, cuMemFreeAsync.argtypes = CUresult, [CUdeviceptr, CUstream] +except AttributeError: pass + +# CUresult cuMemAllocAsync(CUdeviceptr *dptr, size_t bytesize, CUstream hStream) +try: (cuMemAllocAsync:=dll.cuMemAllocAsync).restype, cuMemAllocAsync.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t, CUstream] +except AttributeError: pass + +# CUresult cuMemAllocFromPoolAsync(CUdeviceptr *dptr, size_t bytesize, CUmemoryPool pool, CUstream hStream) +try: (cuMemAllocFromPoolAsync:=dll.cuMemAllocFromPoolAsync).restype, cuMemAllocFromPoolAsync.argtypes = CUresult, [ctypes.POINTER(CUdeviceptr), size_t, CUmemoryPool, CUstream] +except AttributeError: pass + +# CUresult cuStreamUpdateCaptureDependencies(CUstream hStream, CUgraphNode *dependencies, size_t numDependencies, unsigned int flags) +try: (cuStreamUpdateCaptureDependencies:=dll.cuStreamUpdateCaptureDependencies).restype, cuStreamUpdateCaptureDependencies.argtypes = CUresult, [CUstream, ctypes.POINTER(CUgraphNode), size_t, ctypes.c_uint32] +except AttributeError: pass + +# CUresult cuGetProcAddress(const char *symbol, void **pfn, int cudaVersion, cuuint64_t flags) +try: (cuGetProcAddress:=dll.cuGetProcAddress).restype, cuGetProcAddress.argtypes = CUresult, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_void_p), ctypes.c_int32, cuuint64_t] +except AttributeError: pass + diff --git a/tinygrad/runtime/autogen/hip.py b/tinygrad/runtime/autogen/hip.py index a6d3b8df0a..d709b86109 100644 --- a/tinygrad/runtime/autogen/hip.py +++ b/tinygrad/runtime/autogen/hip.py @@ -1,5911 +1,3349 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes, os - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries['libamdhip64.so'] = ctypes.CDLL(os.getenv('ROCM_PATH', '/opt/rocm/')+'/lib/libamdhip64.so') - - - -# values for enumeration 'c__Ea_HIP_SUCCESS' -c__Ea_HIP_SUCCESS__enumvalues = { - 0: 'HIP_SUCCESS', - 1: 'HIP_ERROR_INVALID_VALUE', - 2: 'HIP_ERROR_NOT_INITIALIZED', - 3: 'HIP_ERROR_LAUNCH_OUT_OF_RESOURCES', -} -HIP_SUCCESS = 0 -HIP_ERROR_INVALID_VALUE = 1 -HIP_ERROR_NOT_INITIALIZED = 2 -HIP_ERROR_LAUNCH_OUT_OF_RESOURCES = 3 -c__Ea_HIP_SUCCESS = ctypes.c_uint32 # enum -class struct_c__SA_hipDeviceArch_t(Structure): - pass - -struct_c__SA_hipDeviceArch_t._pack_ = 1 # source:False -struct_c__SA_hipDeviceArch_t._fields_ = [ - ('hasGlobalInt32Atomics', ctypes.c_uint32, 1), - ('hasGlobalFloatAtomicExch', ctypes.c_uint32, 1), - ('hasSharedInt32Atomics', ctypes.c_uint32, 1), - ('hasSharedFloatAtomicExch', ctypes.c_uint32, 1), - ('hasFloatAtomicAdd', ctypes.c_uint32, 1), - ('hasGlobalInt64Atomics', ctypes.c_uint32, 1), - ('hasSharedInt64Atomics', ctypes.c_uint32, 1), - ('hasDoubles', ctypes.c_uint32, 1), - ('hasWarpVote', ctypes.c_uint32, 1), - ('hasWarpBallot', ctypes.c_uint32, 1), - ('hasWarpShuffle', ctypes.c_uint32, 1), - ('hasFunnelShift', ctypes.c_uint32, 1), - ('hasThreadFenceSystem', ctypes.c_uint32, 1), - ('hasSyncThreadsExt', ctypes.c_uint32, 1), - ('hasSurfaceFuncs', ctypes.c_uint32, 1), - ('has3dGrid', ctypes.c_uint32, 1), - ('hasDynamicParallelism', ctypes.c_uint32, 1), - ('PADDING_0', ctypes.c_uint16, 15), -] - -hipDeviceArch_t = struct_c__SA_hipDeviceArch_t -class struct_hipUUID_t(Structure): - pass - -struct_hipUUID_t._pack_ = 1 # source:False -struct_hipUUID_t._fields_ = [ - ('bytes', ctypes.c_char * 16), -] - -hipUUID = struct_hipUUID_t -class struct_hipDeviceProp_tR0600(Structure): - pass - -struct_hipDeviceProp_tR0600._pack_ = 1 # source:False -struct_hipDeviceProp_tR0600._fields_ = [ - ('name', ctypes.c_char * 256), - ('uuid', hipUUID), - ('luid', ctypes.c_char * 8), - ('luidDeviceNodeMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalGlobalMem', ctypes.c_uint64), - ('sharedMemPerBlock', ctypes.c_uint64), - ('regsPerBlock', ctypes.c_int32), - ('warpSize', ctypes.c_int32), - ('memPitch', ctypes.c_uint64), - ('maxThreadsPerBlock', ctypes.c_int32), - ('maxThreadsDim', ctypes.c_int32 * 3), - ('maxGridSize', ctypes.c_int32 * 3), - ('clockRate', ctypes.c_int32), - ('totalConstMem', ctypes.c_uint64), - ('major', ctypes.c_int32), - ('minor', ctypes.c_int32), - ('textureAlignment', ctypes.c_uint64), - ('texturePitchAlignment', ctypes.c_uint64), - ('deviceOverlap', ctypes.c_int32), - ('multiProcessorCount', ctypes.c_int32), - ('kernelExecTimeoutEnabled', ctypes.c_int32), - ('integrated', ctypes.c_int32), - ('canMapHostMemory', ctypes.c_int32), - ('computeMode', ctypes.c_int32), - ('maxTexture1D', ctypes.c_int32), - ('maxTexture1DMipmap', ctypes.c_int32), - ('maxTexture1DLinear', ctypes.c_int32), - ('maxTexture2D', ctypes.c_int32 * 2), - ('maxTexture2DMipmap', ctypes.c_int32 * 2), - ('maxTexture2DLinear', ctypes.c_int32 * 3), - ('maxTexture2DGather', ctypes.c_int32 * 2), - ('maxTexture3D', ctypes.c_int32 * 3), - ('maxTexture3DAlt', ctypes.c_int32 * 3), - ('maxTextureCubemap', ctypes.c_int32), - ('maxTexture1DLayered', ctypes.c_int32 * 2), - ('maxTexture2DLayered', ctypes.c_int32 * 3), - ('maxTextureCubemapLayered', ctypes.c_int32 * 2), - ('maxSurface1D', ctypes.c_int32), - ('maxSurface2D', ctypes.c_int32 * 2), - ('maxSurface3D', ctypes.c_int32 * 3), - ('maxSurface1DLayered', ctypes.c_int32 * 2), - ('maxSurface2DLayered', ctypes.c_int32 * 3), - ('maxSurfaceCubemap', ctypes.c_int32), - ('maxSurfaceCubemapLayered', ctypes.c_int32 * 2), - ('surfaceAlignment', ctypes.c_uint64), - ('concurrentKernels', ctypes.c_int32), - ('ECCEnabled', ctypes.c_int32), - ('pciBusID', ctypes.c_int32), - ('pciDeviceID', ctypes.c_int32), - ('pciDomainID', ctypes.c_int32), - ('tccDriver', ctypes.c_int32), - ('asyncEngineCount', ctypes.c_int32), - ('unifiedAddressing', ctypes.c_int32), - ('memoryClockRate', ctypes.c_int32), - ('memoryBusWidth', ctypes.c_int32), - ('l2CacheSize', ctypes.c_int32), - ('persistingL2CacheMaxSize', ctypes.c_int32), - ('maxThreadsPerMultiProcessor', ctypes.c_int32), - ('streamPrioritiesSupported', ctypes.c_int32), - ('globalL1CacheSupported', ctypes.c_int32), - ('localL1CacheSupported', ctypes.c_int32), - ('sharedMemPerMultiprocessor', ctypes.c_uint64), - ('regsPerMultiprocessor', ctypes.c_int32), - ('managedMemory', ctypes.c_int32), - ('isMultiGpuBoard', ctypes.c_int32), - ('multiGpuBoardGroupID', ctypes.c_int32), - ('hostNativeAtomicSupported', ctypes.c_int32), - ('singleToDoublePrecisionPerfRatio', ctypes.c_int32), - ('pageableMemoryAccess', ctypes.c_int32), - ('concurrentManagedAccess', ctypes.c_int32), - ('computePreemptionSupported', ctypes.c_int32), - ('canUseHostPointerForRegisteredMem', ctypes.c_int32), - ('cooperativeLaunch', ctypes.c_int32), - ('cooperativeMultiDeviceLaunch', ctypes.c_int32), - ('sharedMemPerBlockOptin', ctypes.c_uint64), - ('pageableMemoryAccessUsesHostPageTables', ctypes.c_int32), - ('directManagedMemAccessFromHost', ctypes.c_int32), - ('maxBlocksPerMultiProcessor', ctypes.c_int32), - ('accessPolicyMaxWindowSize', ctypes.c_int32), - ('reservedSharedMemPerBlock', ctypes.c_uint64), - ('hostRegisterSupported', ctypes.c_int32), - ('sparseHipArraySupported', ctypes.c_int32), - ('hostRegisterReadOnlySupported', ctypes.c_int32), - ('timelineSemaphoreInteropSupported', ctypes.c_int32), - ('memoryPoolsSupported', ctypes.c_int32), - ('gpuDirectRDMASupported', ctypes.c_int32), - ('gpuDirectRDMAFlushWritesOptions', ctypes.c_uint32), - ('gpuDirectRDMAWritesOrdering', ctypes.c_int32), - ('memoryPoolSupportedHandleTypes', ctypes.c_uint32), - ('deferredMappingHipArraySupported', ctypes.c_int32), - ('ipcEventSupported', ctypes.c_int32), - ('clusterLaunch', ctypes.c_int32), - ('unifiedFunctionPointers', ctypes.c_int32), - ('reserved', ctypes.c_int32 * 63), - ('hipReserved', ctypes.c_int32 * 32), - ('gcnArchName', ctypes.c_char * 256), - ('maxSharedMemoryPerMultiProcessor', ctypes.c_uint64), - ('clockInstructionRate', ctypes.c_int32), - ('arch', hipDeviceArch_t), - ('hdpMemFlushCntl', ctypes.POINTER(ctypes.c_uint32)), - ('hdpRegFlushCntl', ctypes.POINTER(ctypes.c_uint32)), - ('cooperativeMultiDeviceUnmatchedFunc', ctypes.c_int32), - ('cooperativeMultiDeviceUnmatchedGridDim', ctypes.c_int32), - ('cooperativeMultiDeviceUnmatchedBlockDim', ctypes.c_int32), - ('cooperativeMultiDeviceUnmatchedSharedMem', ctypes.c_int32), - ('isLargeBar', ctypes.c_int32), - ('asicRevision', ctypes.c_int32), -] - -hipDeviceProp_tR0600 = struct_hipDeviceProp_tR0600 - -# values for enumeration 'hipMemoryType' -hipMemoryType__enumvalues = { - 0: 'hipMemoryTypeUnregistered', - 1: 'hipMemoryTypeHost', - 2: 'hipMemoryTypeDevice', - 3: 'hipMemoryTypeManaged', - 10: 'hipMemoryTypeArray', - 11: 'hipMemoryTypeUnified', -} -hipMemoryTypeUnregistered = 0 -hipMemoryTypeHost = 1 -hipMemoryTypeDevice = 2 -hipMemoryTypeManaged = 3 -hipMemoryTypeArray = 10 -hipMemoryTypeUnified = 11 -hipMemoryType = ctypes.c_uint32 # enum -class struct_hipPointerAttribute_t(Structure): - pass - -struct_hipPointerAttribute_t._pack_ = 1 # source:False -struct_hipPointerAttribute_t._fields_ = [ - ('type', hipMemoryType), - ('device', ctypes.c_int32), - ('devicePointer', ctypes.POINTER(None)), - ('hostPointer', ctypes.POINTER(None)), - ('isManaged', ctypes.c_int32), - ('allocationFlags', ctypes.c_uint32), -] - -hipPointerAttribute_t = struct_hipPointerAttribute_t - -# values for enumeration 'hipError_t' -hipError_t__enumvalues = { - 0: 'hipSuccess', - 1: 'hipErrorInvalidValue', - 2: 'hipErrorOutOfMemory', - 2: 'hipErrorMemoryAllocation', - 3: 'hipErrorNotInitialized', - 3: 'hipErrorInitializationError', - 4: 'hipErrorDeinitialized', - 5: 'hipErrorProfilerDisabled', - 6: 'hipErrorProfilerNotInitialized', - 7: 'hipErrorProfilerAlreadyStarted', - 8: 'hipErrorProfilerAlreadyStopped', - 9: 'hipErrorInvalidConfiguration', - 12: 'hipErrorInvalidPitchValue', - 13: 'hipErrorInvalidSymbol', - 17: 'hipErrorInvalidDevicePointer', - 21: 'hipErrorInvalidMemcpyDirection', - 35: 'hipErrorInsufficientDriver', - 52: 'hipErrorMissingConfiguration', - 53: 'hipErrorPriorLaunchFailure', - 98: 'hipErrorInvalidDeviceFunction', - 100: 'hipErrorNoDevice', - 101: 'hipErrorInvalidDevice', - 200: 'hipErrorInvalidImage', - 201: 'hipErrorInvalidContext', - 202: 'hipErrorContextAlreadyCurrent', - 205: 'hipErrorMapFailed', - 205: 'hipErrorMapBufferObjectFailed', - 206: 'hipErrorUnmapFailed', - 207: 'hipErrorArrayIsMapped', - 208: 'hipErrorAlreadyMapped', - 209: 'hipErrorNoBinaryForGpu', - 210: 'hipErrorAlreadyAcquired', - 211: 'hipErrorNotMapped', - 212: 'hipErrorNotMappedAsArray', - 213: 'hipErrorNotMappedAsPointer', - 214: 'hipErrorECCNotCorrectable', - 215: 'hipErrorUnsupportedLimit', - 216: 'hipErrorContextAlreadyInUse', - 217: 'hipErrorPeerAccessUnsupported', - 218: 'hipErrorInvalidKernelFile', - 219: 'hipErrorInvalidGraphicsContext', - 300: 'hipErrorInvalidSource', - 301: 'hipErrorFileNotFound', - 302: 'hipErrorSharedObjectSymbolNotFound', - 303: 'hipErrorSharedObjectInitFailed', - 304: 'hipErrorOperatingSystem', - 400: 'hipErrorInvalidHandle', - 400: 'hipErrorInvalidResourceHandle', - 401: 'hipErrorIllegalState', - 500: 'hipErrorNotFound', - 600: 'hipErrorNotReady', - 700: 'hipErrorIllegalAddress', - 701: 'hipErrorLaunchOutOfResources', - 702: 'hipErrorLaunchTimeOut', - 704: 'hipErrorPeerAccessAlreadyEnabled', - 705: 'hipErrorPeerAccessNotEnabled', - 708: 'hipErrorSetOnActiveProcess', - 709: 'hipErrorContextIsDestroyed', - 710: 'hipErrorAssert', - 712: 'hipErrorHostMemoryAlreadyRegistered', - 713: 'hipErrorHostMemoryNotRegistered', - 719: 'hipErrorLaunchFailure', - 720: 'hipErrorCooperativeLaunchTooLarge', - 801: 'hipErrorNotSupported', - 900: 'hipErrorStreamCaptureUnsupported', - 901: 'hipErrorStreamCaptureInvalidated', - 902: 'hipErrorStreamCaptureMerge', - 903: 'hipErrorStreamCaptureUnmatched', - 904: 'hipErrorStreamCaptureUnjoined', - 905: 'hipErrorStreamCaptureIsolation', - 906: 'hipErrorStreamCaptureImplicit', - 907: 'hipErrorCapturedEvent', - 908: 'hipErrorStreamCaptureWrongThread', - 910: 'hipErrorGraphExecUpdateFailure', - 999: 'hipErrorUnknown', - 1052: 'hipErrorRuntimeMemory', - 1053: 'hipErrorRuntimeOther', - 1054: 'hipErrorTbd', -} -hipSuccess = 0 -hipErrorInvalidValue = 1 -hipErrorOutOfMemory = 2 -hipErrorMemoryAllocation = 2 -hipErrorNotInitialized = 3 -hipErrorInitializationError = 3 -hipErrorDeinitialized = 4 -hipErrorProfilerDisabled = 5 -hipErrorProfilerNotInitialized = 6 -hipErrorProfilerAlreadyStarted = 7 -hipErrorProfilerAlreadyStopped = 8 -hipErrorInvalidConfiguration = 9 -hipErrorInvalidPitchValue = 12 -hipErrorInvalidSymbol = 13 -hipErrorInvalidDevicePointer = 17 -hipErrorInvalidMemcpyDirection = 21 -hipErrorInsufficientDriver = 35 -hipErrorMissingConfiguration = 52 -hipErrorPriorLaunchFailure = 53 -hipErrorInvalidDeviceFunction = 98 -hipErrorNoDevice = 100 -hipErrorInvalidDevice = 101 -hipErrorInvalidImage = 200 -hipErrorInvalidContext = 201 -hipErrorContextAlreadyCurrent = 202 -hipErrorMapFailed = 205 -hipErrorMapBufferObjectFailed = 205 -hipErrorUnmapFailed = 206 -hipErrorArrayIsMapped = 207 -hipErrorAlreadyMapped = 208 -hipErrorNoBinaryForGpu = 209 -hipErrorAlreadyAcquired = 210 -hipErrorNotMapped = 211 -hipErrorNotMappedAsArray = 212 -hipErrorNotMappedAsPointer = 213 -hipErrorECCNotCorrectable = 214 -hipErrorUnsupportedLimit = 215 -hipErrorContextAlreadyInUse = 216 -hipErrorPeerAccessUnsupported = 217 -hipErrorInvalidKernelFile = 218 -hipErrorInvalidGraphicsContext = 219 -hipErrorInvalidSource = 300 -hipErrorFileNotFound = 301 -hipErrorSharedObjectSymbolNotFound = 302 -hipErrorSharedObjectInitFailed = 303 -hipErrorOperatingSystem = 304 -hipErrorInvalidHandle = 400 -hipErrorInvalidResourceHandle = 400 -hipErrorIllegalState = 401 -hipErrorNotFound = 500 -hipErrorNotReady = 600 -hipErrorIllegalAddress = 700 -hipErrorLaunchOutOfResources = 701 -hipErrorLaunchTimeOut = 702 -hipErrorPeerAccessAlreadyEnabled = 704 -hipErrorPeerAccessNotEnabled = 705 -hipErrorSetOnActiveProcess = 708 -hipErrorContextIsDestroyed = 709 -hipErrorAssert = 710 -hipErrorHostMemoryAlreadyRegistered = 712 -hipErrorHostMemoryNotRegistered = 713 -hipErrorLaunchFailure = 719 -hipErrorCooperativeLaunchTooLarge = 720 -hipErrorNotSupported = 801 -hipErrorStreamCaptureUnsupported = 900 -hipErrorStreamCaptureInvalidated = 901 -hipErrorStreamCaptureMerge = 902 -hipErrorStreamCaptureUnmatched = 903 -hipErrorStreamCaptureUnjoined = 904 -hipErrorStreamCaptureIsolation = 905 -hipErrorStreamCaptureImplicit = 906 -hipErrorCapturedEvent = 907 -hipErrorStreamCaptureWrongThread = 908 -hipErrorGraphExecUpdateFailure = 910 -hipErrorUnknown = 999 -hipErrorRuntimeMemory = 1052 -hipErrorRuntimeOther = 1053 -hipErrorTbd = 1054 -hipError_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipDeviceAttribute_t' -hipDeviceAttribute_t__enumvalues = { - 0: 'hipDeviceAttributeCudaCompatibleBegin', - 0: 'hipDeviceAttributeEccEnabled', - 1: 'hipDeviceAttributeAccessPolicyMaxWindowSize', - 2: 'hipDeviceAttributeAsyncEngineCount', - 3: 'hipDeviceAttributeCanMapHostMemory', - 4: 'hipDeviceAttributeCanUseHostPointerForRegisteredMem', - 5: 'hipDeviceAttributeClockRate', - 6: 'hipDeviceAttributeComputeMode', - 7: 'hipDeviceAttributeComputePreemptionSupported', - 8: 'hipDeviceAttributeConcurrentKernels', - 9: 'hipDeviceAttributeConcurrentManagedAccess', - 10: 'hipDeviceAttributeCooperativeLaunch', - 11: 'hipDeviceAttributeCooperativeMultiDeviceLaunch', - 12: 'hipDeviceAttributeDeviceOverlap', - 13: 'hipDeviceAttributeDirectManagedMemAccessFromHost', - 14: 'hipDeviceAttributeGlobalL1CacheSupported', - 15: 'hipDeviceAttributeHostNativeAtomicSupported', - 16: 'hipDeviceAttributeIntegrated', - 17: 'hipDeviceAttributeIsMultiGpuBoard', - 18: 'hipDeviceAttributeKernelExecTimeout', - 19: 'hipDeviceAttributeL2CacheSize', - 20: 'hipDeviceAttributeLocalL1CacheSupported', - 21: 'hipDeviceAttributeLuid', - 22: 'hipDeviceAttributeLuidDeviceNodeMask', - 23: 'hipDeviceAttributeComputeCapabilityMajor', - 24: 'hipDeviceAttributeManagedMemory', - 25: 'hipDeviceAttributeMaxBlocksPerMultiProcessor', - 26: 'hipDeviceAttributeMaxBlockDimX', - 27: 'hipDeviceAttributeMaxBlockDimY', - 28: 'hipDeviceAttributeMaxBlockDimZ', - 29: 'hipDeviceAttributeMaxGridDimX', - 30: 'hipDeviceAttributeMaxGridDimY', - 31: 'hipDeviceAttributeMaxGridDimZ', - 32: 'hipDeviceAttributeMaxSurface1D', - 33: 'hipDeviceAttributeMaxSurface1DLayered', - 34: 'hipDeviceAttributeMaxSurface2D', - 35: 'hipDeviceAttributeMaxSurface2DLayered', - 36: 'hipDeviceAttributeMaxSurface3D', - 37: 'hipDeviceAttributeMaxSurfaceCubemap', - 38: 'hipDeviceAttributeMaxSurfaceCubemapLayered', - 39: 'hipDeviceAttributeMaxTexture1DWidth', - 40: 'hipDeviceAttributeMaxTexture1DLayered', - 41: 'hipDeviceAttributeMaxTexture1DLinear', - 42: 'hipDeviceAttributeMaxTexture1DMipmap', - 43: 'hipDeviceAttributeMaxTexture2DWidth', - 44: 'hipDeviceAttributeMaxTexture2DHeight', - 45: 'hipDeviceAttributeMaxTexture2DGather', - 46: 'hipDeviceAttributeMaxTexture2DLayered', - 47: 'hipDeviceAttributeMaxTexture2DLinear', - 48: 'hipDeviceAttributeMaxTexture2DMipmap', - 49: 'hipDeviceAttributeMaxTexture3DWidth', - 50: 'hipDeviceAttributeMaxTexture3DHeight', - 51: 'hipDeviceAttributeMaxTexture3DDepth', - 52: 'hipDeviceAttributeMaxTexture3DAlt', - 53: 'hipDeviceAttributeMaxTextureCubemap', - 54: 'hipDeviceAttributeMaxTextureCubemapLayered', - 55: 'hipDeviceAttributeMaxThreadsDim', - 56: 'hipDeviceAttributeMaxThreadsPerBlock', - 57: 'hipDeviceAttributeMaxThreadsPerMultiProcessor', - 58: 'hipDeviceAttributeMaxPitch', - 59: 'hipDeviceAttributeMemoryBusWidth', - 60: 'hipDeviceAttributeMemoryClockRate', - 61: 'hipDeviceAttributeComputeCapabilityMinor', - 62: 'hipDeviceAttributeMultiGpuBoardGroupID', - 63: 'hipDeviceAttributeMultiprocessorCount', - 64: 'hipDeviceAttributeUnused1', - 65: 'hipDeviceAttributePageableMemoryAccess', - 66: 'hipDeviceAttributePageableMemoryAccessUsesHostPageTables', - 67: 'hipDeviceAttributePciBusId', - 68: 'hipDeviceAttributePciDeviceId', - 69: 'hipDeviceAttributePciDomainID', - 70: 'hipDeviceAttributePersistingL2CacheMaxSize', - 71: 'hipDeviceAttributeMaxRegistersPerBlock', - 72: 'hipDeviceAttributeMaxRegistersPerMultiprocessor', - 73: 'hipDeviceAttributeReservedSharedMemPerBlock', - 74: 'hipDeviceAttributeMaxSharedMemoryPerBlock', - 75: 'hipDeviceAttributeSharedMemPerBlockOptin', - 76: 'hipDeviceAttributeSharedMemPerMultiprocessor', - 77: 'hipDeviceAttributeSingleToDoublePrecisionPerfRatio', - 78: 'hipDeviceAttributeStreamPrioritiesSupported', - 79: 'hipDeviceAttributeSurfaceAlignment', - 80: 'hipDeviceAttributeTccDriver', - 81: 'hipDeviceAttributeTextureAlignment', - 82: 'hipDeviceAttributeTexturePitchAlignment', - 83: 'hipDeviceAttributeTotalConstantMemory', - 84: 'hipDeviceAttributeTotalGlobalMem', - 85: 'hipDeviceAttributeUnifiedAddressing', - 86: 'hipDeviceAttributeUnused2', - 87: 'hipDeviceAttributeWarpSize', - 88: 'hipDeviceAttributeMemoryPoolsSupported', - 89: 'hipDeviceAttributeVirtualMemoryManagementSupported', - 90: 'hipDeviceAttributeHostRegisterSupported', - 9999: 'hipDeviceAttributeCudaCompatibleEnd', - 10000: 'hipDeviceAttributeAmdSpecificBegin', - 10000: 'hipDeviceAttributeClockInstructionRate', - 10001: 'hipDeviceAttributeUnused3', - 10002: 'hipDeviceAttributeMaxSharedMemoryPerMultiprocessor', - 10003: 'hipDeviceAttributeUnused4', - 10004: 'hipDeviceAttributeUnused5', - 10005: 'hipDeviceAttributeHdpMemFlushCntl', - 10006: 'hipDeviceAttributeHdpRegFlushCntl', - 10007: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc', - 10008: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim', - 10009: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim', - 10010: 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem', - 10011: 'hipDeviceAttributeIsLargeBar', - 10012: 'hipDeviceAttributeAsicRevision', - 10013: 'hipDeviceAttributeCanUseStreamWaitValue', - 10014: 'hipDeviceAttributeImageSupport', - 10015: 'hipDeviceAttributePhysicalMultiProcessorCount', - 10016: 'hipDeviceAttributeFineGrainSupport', - 10017: 'hipDeviceAttributeWallClockRate', - 19999: 'hipDeviceAttributeAmdSpecificEnd', - 20000: 'hipDeviceAttributeVendorSpecificBegin', -} -hipDeviceAttributeCudaCompatibleBegin = 0 -hipDeviceAttributeEccEnabled = 0 -hipDeviceAttributeAccessPolicyMaxWindowSize = 1 -hipDeviceAttributeAsyncEngineCount = 2 -hipDeviceAttributeCanMapHostMemory = 3 -hipDeviceAttributeCanUseHostPointerForRegisteredMem = 4 -hipDeviceAttributeClockRate = 5 -hipDeviceAttributeComputeMode = 6 -hipDeviceAttributeComputePreemptionSupported = 7 -hipDeviceAttributeConcurrentKernels = 8 -hipDeviceAttributeConcurrentManagedAccess = 9 -hipDeviceAttributeCooperativeLaunch = 10 -hipDeviceAttributeCooperativeMultiDeviceLaunch = 11 -hipDeviceAttributeDeviceOverlap = 12 -hipDeviceAttributeDirectManagedMemAccessFromHost = 13 -hipDeviceAttributeGlobalL1CacheSupported = 14 -hipDeviceAttributeHostNativeAtomicSupported = 15 -hipDeviceAttributeIntegrated = 16 -hipDeviceAttributeIsMultiGpuBoard = 17 -hipDeviceAttributeKernelExecTimeout = 18 -hipDeviceAttributeL2CacheSize = 19 -hipDeviceAttributeLocalL1CacheSupported = 20 -hipDeviceAttributeLuid = 21 -hipDeviceAttributeLuidDeviceNodeMask = 22 -hipDeviceAttributeComputeCapabilityMajor = 23 -hipDeviceAttributeManagedMemory = 24 -hipDeviceAttributeMaxBlocksPerMultiProcessor = 25 -hipDeviceAttributeMaxBlockDimX = 26 -hipDeviceAttributeMaxBlockDimY = 27 -hipDeviceAttributeMaxBlockDimZ = 28 -hipDeviceAttributeMaxGridDimX = 29 -hipDeviceAttributeMaxGridDimY = 30 -hipDeviceAttributeMaxGridDimZ = 31 -hipDeviceAttributeMaxSurface1D = 32 -hipDeviceAttributeMaxSurface1DLayered = 33 -hipDeviceAttributeMaxSurface2D = 34 -hipDeviceAttributeMaxSurface2DLayered = 35 -hipDeviceAttributeMaxSurface3D = 36 -hipDeviceAttributeMaxSurfaceCubemap = 37 -hipDeviceAttributeMaxSurfaceCubemapLayered = 38 -hipDeviceAttributeMaxTexture1DWidth = 39 -hipDeviceAttributeMaxTexture1DLayered = 40 -hipDeviceAttributeMaxTexture1DLinear = 41 -hipDeviceAttributeMaxTexture1DMipmap = 42 -hipDeviceAttributeMaxTexture2DWidth = 43 -hipDeviceAttributeMaxTexture2DHeight = 44 -hipDeviceAttributeMaxTexture2DGather = 45 -hipDeviceAttributeMaxTexture2DLayered = 46 -hipDeviceAttributeMaxTexture2DLinear = 47 -hipDeviceAttributeMaxTexture2DMipmap = 48 -hipDeviceAttributeMaxTexture3DWidth = 49 -hipDeviceAttributeMaxTexture3DHeight = 50 -hipDeviceAttributeMaxTexture3DDepth = 51 -hipDeviceAttributeMaxTexture3DAlt = 52 -hipDeviceAttributeMaxTextureCubemap = 53 -hipDeviceAttributeMaxTextureCubemapLayered = 54 -hipDeviceAttributeMaxThreadsDim = 55 -hipDeviceAttributeMaxThreadsPerBlock = 56 -hipDeviceAttributeMaxThreadsPerMultiProcessor = 57 -hipDeviceAttributeMaxPitch = 58 -hipDeviceAttributeMemoryBusWidth = 59 -hipDeviceAttributeMemoryClockRate = 60 -hipDeviceAttributeComputeCapabilityMinor = 61 -hipDeviceAttributeMultiGpuBoardGroupID = 62 -hipDeviceAttributeMultiprocessorCount = 63 -hipDeviceAttributeUnused1 = 64 -hipDeviceAttributePageableMemoryAccess = 65 -hipDeviceAttributePageableMemoryAccessUsesHostPageTables = 66 -hipDeviceAttributePciBusId = 67 -hipDeviceAttributePciDeviceId = 68 -hipDeviceAttributePciDomainID = 69 -hipDeviceAttributePersistingL2CacheMaxSize = 70 -hipDeviceAttributeMaxRegistersPerBlock = 71 -hipDeviceAttributeMaxRegistersPerMultiprocessor = 72 -hipDeviceAttributeReservedSharedMemPerBlock = 73 -hipDeviceAttributeMaxSharedMemoryPerBlock = 74 -hipDeviceAttributeSharedMemPerBlockOptin = 75 -hipDeviceAttributeSharedMemPerMultiprocessor = 76 -hipDeviceAttributeSingleToDoublePrecisionPerfRatio = 77 -hipDeviceAttributeStreamPrioritiesSupported = 78 -hipDeviceAttributeSurfaceAlignment = 79 -hipDeviceAttributeTccDriver = 80 -hipDeviceAttributeTextureAlignment = 81 -hipDeviceAttributeTexturePitchAlignment = 82 -hipDeviceAttributeTotalConstantMemory = 83 -hipDeviceAttributeTotalGlobalMem = 84 -hipDeviceAttributeUnifiedAddressing = 85 -hipDeviceAttributeUnused2 = 86 -hipDeviceAttributeWarpSize = 87 -hipDeviceAttributeMemoryPoolsSupported = 88 -hipDeviceAttributeVirtualMemoryManagementSupported = 89 -hipDeviceAttributeHostRegisterSupported = 90 -hipDeviceAttributeCudaCompatibleEnd = 9999 -hipDeviceAttributeAmdSpecificBegin = 10000 -hipDeviceAttributeClockInstructionRate = 10000 -hipDeviceAttributeUnused3 = 10001 -hipDeviceAttributeMaxSharedMemoryPerMultiprocessor = 10002 -hipDeviceAttributeUnused4 = 10003 -hipDeviceAttributeUnused5 = 10004 -hipDeviceAttributeHdpMemFlushCntl = 10005 -hipDeviceAttributeHdpRegFlushCntl = 10006 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc = 10007 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim = 10008 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim = 10009 -hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem = 10010 -hipDeviceAttributeIsLargeBar = 10011 -hipDeviceAttributeAsicRevision = 10012 -hipDeviceAttributeCanUseStreamWaitValue = 10013 -hipDeviceAttributeImageSupport = 10014 -hipDeviceAttributePhysicalMultiProcessorCount = 10015 -hipDeviceAttributeFineGrainSupport = 10016 -hipDeviceAttributeWallClockRate = 10017 -hipDeviceAttributeAmdSpecificEnd = 19999 -hipDeviceAttributeVendorSpecificBegin = 20000 -hipDeviceAttribute_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipComputeMode' -hipComputeMode__enumvalues = { - 0: 'hipComputeModeDefault', - 1: 'hipComputeModeExclusive', - 2: 'hipComputeModeProhibited', - 3: 'hipComputeModeExclusiveProcess', -} -hipComputeModeDefault = 0 -hipComputeModeExclusive = 1 -hipComputeModeProhibited = 2 -hipComputeModeExclusiveProcess = 3 -hipComputeMode = ctypes.c_uint32 # enum -hipDeviceptr_t = ctypes.POINTER(None) - -# values for enumeration 'hipChannelFormatKind' -hipChannelFormatKind__enumvalues = { - 0: 'hipChannelFormatKindSigned', - 1: 'hipChannelFormatKindUnsigned', - 2: 'hipChannelFormatKindFloat', - 3: 'hipChannelFormatKindNone', -} -hipChannelFormatKindSigned = 0 -hipChannelFormatKindUnsigned = 1 -hipChannelFormatKindFloat = 2 -hipChannelFormatKindNone = 3 -hipChannelFormatKind = ctypes.c_uint32 # enum -class struct_hipChannelFormatDesc(Structure): - pass - -struct_hipChannelFormatDesc._pack_ = 1 # source:False -struct_hipChannelFormatDesc._fields_ = [ - ('x', ctypes.c_int32), - ('y', ctypes.c_int32), - ('z', ctypes.c_int32), - ('w', ctypes.c_int32), - ('f', hipChannelFormatKind), -] - -hipChannelFormatDesc = struct_hipChannelFormatDesc -class struct_hipArray(Structure): - pass - -hipArray_t = ctypes.POINTER(struct_hipArray) -hipArray_const_t = ctypes.POINTER(struct_hipArray) - -# values for enumeration 'hipArray_Format' -hipArray_Format__enumvalues = { - 1: 'HIP_AD_FORMAT_UNSIGNED_INT8', - 2: 'HIP_AD_FORMAT_UNSIGNED_INT16', - 3: 'HIP_AD_FORMAT_UNSIGNED_INT32', - 8: 'HIP_AD_FORMAT_SIGNED_INT8', - 9: 'HIP_AD_FORMAT_SIGNED_INT16', - 10: 'HIP_AD_FORMAT_SIGNED_INT32', - 16: 'HIP_AD_FORMAT_HALF', - 32: 'HIP_AD_FORMAT_FLOAT', -} -HIP_AD_FORMAT_UNSIGNED_INT8 = 1 -HIP_AD_FORMAT_UNSIGNED_INT16 = 2 -HIP_AD_FORMAT_UNSIGNED_INT32 = 3 -HIP_AD_FORMAT_SIGNED_INT8 = 8 -HIP_AD_FORMAT_SIGNED_INT16 = 9 -HIP_AD_FORMAT_SIGNED_INT32 = 10 -HIP_AD_FORMAT_HALF = 16 -HIP_AD_FORMAT_FLOAT = 32 -hipArray_Format = ctypes.c_uint32 # enum -class struct_HIP_ARRAY_DESCRIPTOR(Structure): - pass - -struct_HIP_ARRAY_DESCRIPTOR._pack_ = 1 # source:False -struct_HIP_ARRAY_DESCRIPTOR._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Format', hipArray_Format), - ('NumChannels', ctypes.c_uint32), -] - -HIP_ARRAY_DESCRIPTOR = struct_HIP_ARRAY_DESCRIPTOR -class struct_HIP_ARRAY3D_DESCRIPTOR(Structure): - pass - -struct_HIP_ARRAY3D_DESCRIPTOR._pack_ = 1 # source:False -struct_HIP_ARRAY3D_DESCRIPTOR._fields_ = [ - ('Width', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), - ('Format', hipArray_Format), - ('NumChannels', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -HIP_ARRAY3D_DESCRIPTOR = struct_HIP_ARRAY3D_DESCRIPTOR -class struct_hip_Memcpy2D(Structure): - pass - -struct_hip_Memcpy2D._pack_ = 1 # source:False -struct_hip_Memcpy2D._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcMemoryType', hipMemoryType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.POINTER(None)), - ('srcArray', ctypes.POINTER(struct_hipArray)), - ('srcPitch', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstMemoryType', hipMemoryType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.POINTER(None)), - ('dstArray', ctypes.POINTER(struct_hipArray)), - ('dstPitch', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), -] - -hip_Memcpy2D = struct_hip_Memcpy2D -class struct_hipMipmappedArray(Structure): - pass - -struct_hipMipmappedArray._pack_ = 1 # source:False -struct_hipMipmappedArray._fields_ = [ - ('data', ctypes.POINTER(None)), - ('desc', struct_hipChannelFormatDesc), - ('type', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depth', ctypes.c_uint32), - ('min_mipmap_level', ctypes.c_uint32), - ('max_mipmap_level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('format', hipArray_Format), - ('num_channels', ctypes.c_uint32), -] - -hipMipmappedArray = struct_hipMipmappedArray -hipMipmappedArray_t = ctypes.POINTER(struct_hipMipmappedArray) -hipmipmappedArray = ctypes.POINTER(struct_hipMipmappedArray) -hipMipmappedArray_const_t = ctypes.POINTER(struct_hipMipmappedArray) - -# values for enumeration 'hipResourceType' -hipResourceType__enumvalues = { - 0: 'hipResourceTypeArray', - 1: 'hipResourceTypeMipmappedArray', - 2: 'hipResourceTypeLinear', - 3: 'hipResourceTypePitch2D', -} -hipResourceTypeArray = 0 -hipResourceTypeMipmappedArray = 1 -hipResourceTypeLinear = 2 -hipResourceTypePitch2D = 3 -hipResourceType = ctypes.c_uint32 # enum - -# values for enumeration 'HIPresourcetype_enum' -HIPresourcetype_enum__enumvalues = { - 0: 'HIP_RESOURCE_TYPE_ARRAY', - 1: 'HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY', - 2: 'HIP_RESOURCE_TYPE_LINEAR', - 3: 'HIP_RESOURCE_TYPE_PITCH2D', -} -HIP_RESOURCE_TYPE_ARRAY = 0 -HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY = 1 -HIP_RESOURCE_TYPE_LINEAR = 2 -HIP_RESOURCE_TYPE_PITCH2D = 3 -HIPresourcetype_enum = ctypes.c_uint32 # enum -HIPresourcetype = HIPresourcetype_enum -HIPresourcetype__enumvalues = HIPresourcetype_enum__enumvalues -hipResourcetype = HIPresourcetype_enum -hipResourcetype__enumvalues = HIPresourcetype_enum__enumvalues - -# values for enumeration 'HIPaddress_mode_enum' -HIPaddress_mode_enum__enumvalues = { - 0: 'HIP_TR_ADDRESS_MODE_WRAP', - 1: 'HIP_TR_ADDRESS_MODE_CLAMP', - 2: 'HIP_TR_ADDRESS_MODE_MIRROR', - 3: 'HIP_TR_ADDRESS_MODE_BORDER', -} -HIP_TR_ADDRESS_MODE_WRAP = 0 -HIP_TR_ADDRESS_MODE_CLAMP = 1 -HIP_TR_ADDRESS_MODE_MIRROR = 2 -HIP_TR_ADDRESS_MODE_BORDER = 3 -HIPaddress_mode_enum = ctypes.c_uint32 # enum -HIPaddress_mode = HIPaddress_mode_enum -HIPaddress_mode__enumvalues = HIPaddress_mode_enum__enumvalues - -# values for enumeration 'HIPfilter_mode_enum' -HIPfilter_mode_enum__enumvalues = { - 0: 'HIP_TR_FILTER_MODE_POINT', - 1: 'HIP_TR_FILTER_MODE_LINEAR', -} -HIP_TR_FILTER_MODE_POINT = 0 -HIP_TR_FILTER_MODE_LINEAR = 1 -HIPfilter_mode_enum = ctypes.c_uint32 # enum -HIPfilter_mode = HIPfilter_mode_enum -HIPfilter_mode__enumvalues = HIPfilter_mode_enum__enumvalues -class struct_HIP_TEXTURE_DESC_st(Structure): - pass - -struct_HIP_TEXTURE_DESC_st._pack_ = 1 # source:False -struct_HIP_TEXTURE_DESC_st._fields_ = [ - ('addressMode', HIPaddress_mode_enum * 3), - ('filterMode', HIPfilter_mode), - ('flags', ctypes.c_uint32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', HIPfilter_mode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), - ('borderColor', ctypes.c_float * 4), - ('reserved', ctypes.c_int32 * 12), -] - -HIP_TEXTURE_DESC = struct_HIP_TEXTURE_DESC_st - -# values for enumeration 'hipResourceViewFormat' -hipResourceViewFormat__enumvalues = { - 0: 'hipResViewFormatNone', - 1: 'hipResViewFormatUnsignedChar1', - 2: 'hipResViewFormatUnsignedChar2', - 3: 'hipResViewFormatUnsignedChar4', - 4: 'hipResViewFormatSignedChar1', - 5: 'hipResViewFormatSignedChar2', - 6: 'hipResViewFormatSignedChar4', - 7: 'hipResViewFormatUnsignedShort1', - 8: 'hipResViewFormatUnsignedShort2', - 9: 'hipResViewFormatUnsignedShort4', - 10: 'hipResViewFormatSignedShort1', - 11: 'hipResViewFormatSignedShort2', - 12: 'hipResViewFormatSignedShort4', - 13: 'hipResViewFormatUnsignedInt1', - 14: 'hipResViewFormatUnsignedInt2', - 15: 'hipResViewFormatUnsignedInt4', - 16: 'hipResViewFormatSignedInt1', - 17: 'hipResViewFormatSignedInt2', - 18: 'hipResViewFormatSignedInt4', - 19: 'hipResViewFormatHalf1', - 20: 'hipResViewFormatHalf2', - 21: 'hipResViewFormatHalf4', - 22: 'hipResViewFormatFloat1', - 23: 'hipResViewFormatFloat2', - 24: 'hipResViewFormatFloat4', - 25: 'hipResViewFormatUnsignedBlockCompressed1', - 26: 'hipResViewFormatUnsignedBlockCompressed2', - 27: 'hipResViewFormatUnsignedBlockCompressed3', - 28: 'hipResViewFormatUnsignedBlockCompressed4', - 29: 'hipResViewFormatSignedBlockCompressed4', - 30: 'hipResViewFormatUnsignedBlockCompressed5', - 31: 'hipResViewFormatSignedBlockCompressed5', - 32: 'hipResViewFormatUnsignedBlockCompressed6H', - 33: 'hipResViewFormatSignedBlockCompressed6H', - 34: 'hipResViewFormatUnsignedBlockCompressed7', -} -hipResViewFormatNone = 0 -hipResViewFormatUnsignedChar1 = 1 -hipResViewFormatUnsignedChar2 = 2 -hipResViewFormatUnsignedChar4 = 3 -hipResViewFormatSignedChar1 = 4 -hipResViewFormatSignedChar2 = 5 -hipResViewFormatSignedChar4 = 6 -hipResViewFormatUnsignedShort1 = 7 -hipResViewFormatUnsignedShort2 = 8 -hipResViewFormatUnsignedShort4 = 9 -hipResViewFormatSignedShort1 = 10 -hipResViewFormatSignedShort2 = 11 -hipResViewFormatSignedShort4 = 12 -hipResViewFormatUnsignedInt1 = 13 -hipResViewFormatUnsignedInt2 = 14 -hipResViewFormatUnsignedInt4 = 15 -hipResViewFormatSignedInt1 = 16 -hipResViewFormatSignedInt2 = 17 -hipResViewFormatSignedInt4 = 18 -hipResViewFormatHalf1 = 19 -hipResViewFormatHalf2 = 20 -hipResViewFormatHalf4 = 21 -hipResViewFormatFloat1 = 22 -hipResViewFormatFloat2 = 23 -hipResViewFormatFloat4 = 24 -hipResViewFormatUnsignedBlockCompressed1 = 25 -hipResViewFormatUnsignedBlockCompressed2 = 26 -hipResViewFormatUnsignedBlockCompressed3 = 27 -hipResViewFormatUnsignedBlockCompressed4 = 28 -hipResViewFormatSignedBlockCompressed4 = 29 -hipResViewFormatUnsignedBlockCompressed5 = 30 -hipResViewFormatSignedBlockCompressed5 = 31 -hipResViewFormatUnsignedBlockCompressed6H = 32 -hipResViewFormatSignedBlockCompressed6H = 33 -hipResViewFormatUnsignedBlockCompressed7 = 34 -hipResourceViewFormat = ctypes.c_uint32 # enum - -# values for enumeration 'HIPresourceViewFormat_enum' -HIPresourceViewFormat_enum__enumvalues = { - 0: 'HIP_RES_VIEW_FORMAT_NONE', - 1: 'HIP_RES_VIEW_FORMAT_UINT_1X8', - 2: 'HIP_RES_VIEW_FORMAT_UINT_2X8', - 3: 'HIP_RES_VIEW_FORMAT_UINT_4X8', - 4: 'HIP_RES_VIEW_FORMAT_SINT_1X8', - 5: 'HIP_RES_VIEW_FORMAT_SINT_2X8', - 6: 'HIP_RES_VIEW_FORMAT_SINT_4X8', - 7: 'HIP_RES_VIEW_FORMAT_UINT_1X16', - 8: 'HIP_RES_VIEW_FORMAT_UINT_2X16', - 9: 'HIP_RES_VIEW_FORMAT_UINT_4X16', - 10: 'HIP_RES_VIEW_FORMAT_SINT_1X16', - 11: 'HIP_RES_VIEW_FORMAT_SINT_2X16', - 12: 'HIP_RES_VIEW_FORMAT_SINT_4X16', - 13: 'HIP_RES_VIEW_FORMAT_UINT_1X32', - 14: 'HIP_RES_VIEW_FORMAT_UINT_2X32', - 15: 'HIP_RES_VIEW_FORMAT_UINT_4X32', - 16: 'HIP_RES_VIEW_FORMAT_SINT_1X32', - 17: 'HIP_RES_VIEW_FORMAT_SINT_2X32', - 18: 'HIP_RES_VIEW_FORMAT_SINT_4X32', - 19: 'HIP_RES_VIEW_FORMAT_FLOAT_1X16', - 20: 'HIP_RES_VIEW_FORMAT_FLOAT_2X16', - 21: 'HIP_RES_VIEW_FORMAT_FLOAT_4X16', - 22: 'HIP_RES_VIEW_FORMAT_FLOAT_1X32', - 23: 'HIP_RES_VIEW_FORMAT_FLOAT_2X32', - 24: 'HIP_RES_VIEW_FORMAT_FLOAT_4X32', - 25: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC1', - 26: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC2', - 27: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC3', - 28: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC4', - 29: 'HIP_RES_VIEW_FORMAT_SIGNED_BC4', - 30: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC5', - 31: 'HIP_RES_VIEW_FORMAT_SIGNED_BC5', - 32: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 33: 'HIP_RES_VIEW_FORMAT_SIGNED_BC6H', - 34: 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC7', -} -HIP_RES_VIEW_FORMAT_NONE = 0 -HIP_RES_VIEW_FORMAT_UINT_1X8 = 1 -HIP_RES_VIEW_FORMAT_UINT_2X8 = 2 -HIP_RES_VIEW_FORMAT_UINT_4X8 = 3 -HIP_RES_VIEW_FORMAT_SINT_1X8 = 4 -HIP_RES_VIEW_FORMAT_SINT_2X8 = 5 -HIP_RES_VIEW_FORMAT_SINT_4X8 = 6 -HIP_RES_VIEW_FORMAT_UINT_1X16 = 7 -HIP_RES_VIEW_FORMAT_UINT_2X16 = 8 -HIP_RES_VIEW_FORMAT_UINT_4X16 = 9 -HIP_RES_VIEW_FORMAT_SINT_1X16 = 10 -HIP_RES_VIEW_FORMAT_SINT_2X16 = 11 -HIP_RES_VIEW_FORMAT_SINT_4X16 = 12 -HIP_RES_VIEW_FORMAT_UINT_1X32 = 13 -HIP_RES_VIEW_FORMAT_UINT_2X32 = 14 -HIP_RES_VIEW_FORMAT_UINT_4X32 = 15 -HIP_RES_VIEW_FORMAT_SINT_1X32 = 16 -HIP_RES_VIEW_FORMAT_SINT_2X32 = 17 -HIP_RES_VIEW_FORMAT_SINT_4X32 = 18 -HIP_RES_VIEW_FORMAT_FLOAT_1X16 = 19 -HIP_RES_VIEW_FORMAT_FLOAT_2X16 = 20 -HIP_RES_VIEW_FORMAT_FLOAT_4X16 = 21 -HIP_RES_VIEW_FORMAT_FLOAT_1X32 = 22 -HIP_RES_VIEW_FORMAT_FLOAT_2X32 = 23 -HIP_RES_VIEW_FORMAT_FLOAT_4X32 = 24 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC1 = 25 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC2 = 26 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC3 = 27 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC4 = 28 -HIP_RES_VIEW_FORMAT_SIGNED_BC4 = 29 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC5 = 30 -HIP_RES_VIEW_FORMAT_SIGNED_BC5 = 31 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H = 32 -HIP_RES_VIEW_FORMAT_SIGNED_BC6H = 33 -HIP_RES_VIEW_FORMAT_UNSIGNED_BC7 = 34 -HIPresourceViewFormat_enum = ctypes.c_uint32 # enum -HIPresourceViewFormat = HIPresourceViewFormat_enum -HIPresourceViewFormat__enumvalues = HIPresourceViewFormat_enum__enumvalues -class struct_hipResourceDesc(Structure): - pass - -class union_hipResourceDesc_res(Union): - pass - -class struct_hipResourceDesc_0_array(Structure): - pass - -struct_hipResourceDesc_0_array._pack_ = 1 # source:False -struct_hipResourceDesc_0_array._fields_ = [ - ('array', ctypes.POINTER(struct_hipArray)), -] - -class struct_hipResourceDesc_0_mipmap(Structure): - pass - -struct_hipResourceDesc_0_mipmap._pack_ = 1 # source:False -struct_hipResourceDesc_0_mipmap._fields_ = [ - ('mipmap', ctypes.POINTER(struct_hipMipmappedArray)), -] - -class struct_hipResourceDesc_0_linear(Structure): - pass - -struct_hipResourceDesc_0_linear._pack_ = 1 # source:False -struct_hipResourceDesc_0_linear._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('desc', struct_hipChannelFormatDesc), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sizeInBytes', ctypes.c_uint64), -] - -class struct_hipResourceDesc_0_pitch2D(Structure): - pass - -struct_hipResourceDesc_0_pitch2D._pack_ = 1 # source:False -struct_hipResourceDesc_0_pitch2D._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('desc', struct_hipChannelFormatDesc), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('pitchInBytes', ctypes.c_uint64), -] - -union_hipResourceDesc_res._pack_ = 1 # source:False -union_hipResourceDesc_res._fields_ = [ - ('array', struct_hipResourceDesc_0_array), - ('mipmap', struct_hipResourceDesc_0_mipmap), - ('linear', struct_hipResourceDesc_0_linear), - ('pitch2D', struct_hipResourceDesc_0_pitch2D), -] - -struct_hipResourceDesc._pack_ = 1 # source:False -struct_hipResourceDesc._fields_ = [ - ('resType', hipResourceType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('res', union_hipResourceDesc_res), -] - -hipResourceDesc = struct_hipResourceDesc -class struct_HIP_RESOURCE_DESC_st(Structure): - pass - -class union_HIP_RESOURCE_DESC_st_res(Union): - pass - -class struct_HIP_RESOURCE_DESC_st_0_array(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_array._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_array._fields_ = [ - ('hArray', ctypes.POINTER(struct_hipArray)), -] - -class struct_HIP_RESOURCE_DESC_st_0_mipmap(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_mipmap._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_mipmap._fields_ = [ - ('hMipmappedArray', ctypes.POINTER(struct_hipMipmappedArray)), -] - -class struct_HIP_RESOURCE_DESC_st_0_linear(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_linear._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_linear._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('format', hipArray_Format), - ('numChannels', ctypes.c_uint32), - ('sizeInBytes', ctypes.c_uint64), -] - -class struct_HIP_RESOURCE_DESC_st_0_pitch2D(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_pitch2D._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_pitch2D._fields_ = [ - ('devPtr', ctypes.POINTER(None)), - ('format', hipArray_Format), - ('numChannels', ctypes.c_uint32), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('pitchInBytes', ctypes.c_uint64), -] - -class struct_HIP_RESOURCE_DESC_st_0_reserved(Structure): - pass - -struct_HIP_RESOURCE_DESC_st_0_reserved._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st_0_reserved._fields_ = [ - ('reserved', ctypes.c_int32 * 32), -] - -union_HIP_RESOURCE_DESC_st_res._pack_ = 1 # source:False -union_HIP_RESOURCE_DESC_st_res._fields_ = [ - ('array', struct_HIP_RESOURCE_DESC_st_0_array), - ('mipmap', struct_HIP_RESOURCE_DESC_st_0_mipmap), - ('linear', struct_HIP_RESOURCE_DESC_st_0_linear), - ('pitch2D', struct_HIP_RESOURCE_DESC_st_0_pitch2D), - ('reserved', struct_HIP_RESOURCE_DESC_st_0_reserved), -] - -struct_HIP_RESOURCE_DESC_st._pack_ = 1 # source:False -struct_HIP_RESOURCE_DESC_st._fields_ = [ - ('resType', HIPresourcetype), - ('PADDING_0', ctypes.c_ubyte * 4), - ('res', union_HIP_RESOURCE_DESC_st_res), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -HIP_RESOURCE_DESC = struct_HIP_RESOURCE_DESC_st -class struct_hipResourceViewDesc(Structure): - pass - -struct_hipResourceViewDesc._pack_ = 1 # source:False -struct_hipResourceViewDesc._fields_ = [ - ('format', hipResourceViewFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('firstMipmapLevel', ctypes.c_uint32), - ('lastMipmapLevel', ctypes.c_uint32), - ('firstLayer', ctypes.c_uint32), - ('lastLayer', ctypes.c_uint32), -] - -class struct_HIP_RESOURCE_VIEW_DESC_st(Structure): - pass - -struct_HIP_RESOURCE_VIEW_DESC_st._pack_ = 1 # source:False -struct_HIP_RESOURCE_VIEW_DESC_st._fields_ = [ - ('format', HIPresourceViewFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('firstMipmapLevel', ctypes.c_uint32), - ('lastMipmapLevel', ctypes.c_uint32), - ('firstLayer', ctypes.c_uint32), - ('lastLayer', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), -] - -HIP_RESOURCE_VIEW_DESC = struct_HIP_RESOURCE_VIEW_DESC_st - -# values for enumeration 'hipMemcpyKind' -hipMemcpyKind__enumvalues = { - 0: 'hipMemcpyHostToHost', - 1: 'hipMemcpyHostToDevice', - 2: 'hipMemcpyDeviceToHost', - 3: 'hipMemcpyDeviceToDevice', - 4: 'hipMemcpyDefault', -} -hipMemcpyHostToHost = 0 -hipMemcpyHostToDevice = 1 -hipMemcpyDeviceToHost = 2 -hipMemcpyDeviceToDevice = 3 -hipMemcpyDefault = 4 -hipMemcpyKind = ctypes.c_uint32 # enum -class struct_hipPitchedPtr(Structure): - pass - -struct_hipPitchedPtr._pack_ = 1 # source:False -struct_hipPitchedPtr._fields_ = [ - ('ptr', ctypes.POINTER(None)), - ('pitch', ctypes.c_uint64), - ('xsize', ctypes.c_uint64), - ('ysize', ctypes.c_uint64), -] - -hipPitchedPtr = struct_hipPitchedPtr -class struct_hipExtent(Structure): - pass - -struct_hipExtent._pack_ = 1 # source:False -struct_hipExtent._fields_ = [ - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), -] - -hipExtent = struct_hipExtent -class struct_hipPos(Structure): - pass - -struct_hipPos._pack_ = 1 # source:False -struct_hipPos._fields_ = [ - ('x', ctypes.c_uint64), - ('y', ctypes.c_uint64), - ('z', ctypes.c_uint64), -] - -hipPos = struct_hipPos -class struct_hipMemcpy3DParms(Structure): - pass - -struct_hipMemcpy3DParms._pack_ = 1 # source:False -struct_hipMemcpy3DParms._fields_ = [ - ('srcArray', ctypes.POINTER(struct_hipArray)), - ('srcPos', struct_hipPos), - ('srcPtr', struct_hipPitchedPtr), - ('dstArray', ctypes.POINTER(struct_hipArray)), - ('dstPos', struct_hipPos), - ('dstPtr', struct_hipPitchedPtr), - ('extent', struct_hipExtent), - ('kind', hipMemcpyKind), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipMemcpy3DParms = struct_hipMemcpy3DParms -class struct_HIP_MEMCPY3D(Structure): - pass - -struct_HIP_MEMCPY3D._pack_ = 1 # source:False -struct_HIP_MEMCPY3D._fields_ = [ - ('srcXInBytes', ctypes.c_uint64), - ('srcY', ctypes.c_uint64), - ('srcZ', ctypes.c_uint64), - ('srcLOD', ctypes.c_uint64), - ('srcMemoryType', hipMemoryType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcHost', ctypes.POINTER(None)), - ('srcDevice', ctypes.POINTER(None)), - ('srcArray', ctypes.POINTER(struct_hipArray)), - ('srcPitch', ctypes.c_uint64), - ('srcHeight', ctypes.c_uint64), - ('dstXInBytes', ctypes.c_uint64), - ('dstY', ctypes.c_uint64), - ('dstZ', ctypes.c_uint64), - ('dstLOD', ctypes.c_uint64), - ('dstMemoryType', hipMemoryType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dstHost', ctypes.POINTER(None)), - ('dstDevice', ctypes.POINTER(None)), - ('dstArray', ctypes.POINTER(struct_hipArray)), - ('dstPitch', ctypes.c_uint64), - ('dstHeight', ctypes.c_uint64), - ('WidthInBytes', ctypes.c_uint64), - ('Height', ctypes.c_uint64), - ('Depth', ctypes.c_uint64), -] - -HIP_MEMCPY3D = struct_HIP_MEMCPY3D -size_t = ctypes.c_uint64 -try: - make_hipPitchedPtr = _libraries['FIXME_STUB'].make_hipPitchedPtr - make_hipPitchedPtr.restype = struct_hipPitchedPtr - make_hipPitchedPtr.argtypes = [ctypes.POINTER(None), size_t, size_t, size_t] -except AttributeError: - pass -try: - make_hipPos = _libraries['FIXME_STUB'].make_hipPos - make_hipPos.restype = struct_hipPos - make_hipPos.argtypes = [size_t, size_t, size_t] -except AttributeError: - pass -try: - make_hipExtent = _libraries['FIXME_STUB'].make_hipExtent - make_hipExtent.restype = struct_hipExtent - make_hipExtent.argtypes = [size_t, size_t, size_t] -except AttributeError: - pass - -# values for enumeration 'hipFunction_attribute' -hipFunction_attribute__enumvalues = { - 0: 'HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 1: 'HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', - 2: 'HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 3: 'HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', - 4: 'HIP_FUNC_ATTRIBUTE_NUM_REGS', - 5: 'HIP_FUNC_ATTRIBUTE_PTX_VERSION', - 6: 'HIP_FUNC_ATTRIBUTE_BINARY_VERSION', - 7: 'HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 8: 'HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 9: 'HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 10: 'HIP_FUNC_ATTRIBUTE_MAX', -} -HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK = 0 -HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES = 1 -HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES = 2 -HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES = 3 -HIP_FUNC_ATTRIBUTE_NUM_REGS = 4 -HIP_FUNC_ATTRIBUTE_PTX_VERSION = 5 -HIP_FUNC_ATTRIBUTE_BINARY_VERSION = 6 -HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA = 7 -HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES = 8 -HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT = 9 -HIP_FUNC_ATTRIBUTE_MAX = 10 -hipFunction_attribute = ctypes.c_uint32 # enum - -# values for enumeration 'hipPointer_attribute' -hipPointer_attribute__enumvalues = { - 1: 'HIP_POINTER_ATTRIBUTE_CONTEXT', - 2: 'HIP_POINTER_ATTRIBUTE_MEMORY_TYPE', - 3: 'HIP_POINTER_ATTRIBUTE_DEVICE_POINTER', - 4: 'HIP_POINTER_ATTRIBUTE_HOST_POINTER', - 5: 'HIP_POINTER_ATTRIBUTE_P2P_TOKENS', - 6: 'HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS', - 7: 'HIP_POINTER_ATTRIBUTE_BUFFER_ID', - 8: 'HIP_POINTER_ATTRIBUTE_IS_MANAGED', - 9: 'HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 10: 'HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE', - 11: 'HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 12: 'HIP_POINTER_ATTRIBUTE_RANGE_SIZE', - 13: 'HIP_POINTER_ATTRIBUTE_MAPPED', - 14: 'HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 15: 'HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 16: 'HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 17: 'HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', -} -HIP_POINTER_ATTRIBUTE_CONTEXT = 1 -HIP_POINTER_ATTRIBUTE_MEMORY_TYPE = 2 -HIP_POINTER_ATTRIBUTE_DEVICE_POINTER = 3 -HIP_POINTER_ATTRIBUTE_HOST_POINTER = 4 -HIP_POINTER_ATTRIBUTE_P2P_TOKENS = 5 -HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS = 6 -HIP_POINTER_ATTRIBUTE_BUFFER_ID = 7 -HIP_POINTER_ATTRIBUTE_IS_MANAGED = 8 -HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL = 9 -HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE = 10 -HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR = 11 -HIP_POINTER_ATTRIBUTE_RANGE_SIZE = 12 -HIP_POINTER_ATTRIBUTE_MAPPED = 13 -HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES = 14 -HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE = 15 -HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS = 16 -HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE = 17 -hipPointer_attribute = ctypes.c_uint32 # enum -try: - hip_init = _libraries['FIXME_STUB'].hip_init - hip_init.restype = hipError_t - hip_init.argtypes = [] -except AttributeError: - pass -class struct_ihipCtx_t(Structure): - pass - -hipCtx_t = ctypes.POINTER(struct_ihipCtx_t) -hipDevice_t = ctypes.c_int32 - -# values for enumeration 'hipDeviceP2PAttr' -hipDeviceP2PAttr__enumvalues = { - 0: 'hipDevP2PAttrPerformanceRank', - 1: 'hipDevP2PAttrAccessSupported', - 2: 'hipDevP2PAttrNativeAtomicSupported', - 3: 'hipDevP2PAttrHipArrayAccessSupported', -} -hipDevP2PAttrPerformanceRank = 0 -hipDevP2PAttrAccessSupported = 1 -hipDevP2PAttrNativeAtomicSupported = 2 -hipDevP2PAttrHipArrayAccessSupported = 3 -hipDeviceP2PAttr = ctypes.c_uint32 # enum -class struct_ihipStream_t(Structure): - pass - -hipStream_t = ctypes.POINTER(struct_ihipStream_t) -class struct_hipIpcMemHandle_st(Structure): - pass - -struct_hipIpcMemHandle_st._pack_ = 1 # source:False -struct_hipIpcMemHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), -] - -hipIpcMemHandle_t = struct_hipIpcMemHandle_st -class struct_hipIpcEventHandle_st(Structure): - pass - -struct_hipIpcEventHandle_st._pack_ = 1 # source:False -struct_hipIpcEventHandle_st._fields_ = [ - ('reserved', ctypes.c_char * 64), -] - -hipIpcEventHandle_t = struct_hipIpcEventHandle_st -class struct_ihipModule_t(Structure): - pass - -hipModule_t = ctypes.POINTER(struct_ihipModule_t) -class struct_ihipModuleSymbol_t(Structure): - pass - -hipFunction_t = ctypes.POINTER(struct_ihipModuleSymbol_t) -class struct_ihipMemPoolHandle_t(Structure): - pass - -hipMemPool_t = ctypes.POINTER(struct_ihipMemPoolHandle_t) -class struct_hipFuncAttributes(Structure): - pass - -struct_hipFuncAttributes._pack_ = 1 # source:False -struct_hipFuncAttributes._fields_ = [ - ('binaryVersion', ctypes.c_int32), - ('cacheModeCA', ctypes.c_int32), - ('constSizeBytes', ctypes.c_uint64), - ('localSizeBytes', ctypes.c_uint64), - ('maxDynamicSharedSizeBytes', ctypes.c_int32), - ('maxThreadsPerBlock', ctypes.c_int32), - ('numRegs', ctypes.c_int32), - ('preferredShmemCarveout', ctypes.c_int32), - ('ptxVersion', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sharedSizeBytes', ctypes.c_uint64), -] - -hipFuncAttributes = struct_hipFuncAttributes -class struct_ihipEvent_t(Structure): - pass - -hipEvent_t = ctypes.POINTER(struct_ihipEvent_t) - -# values for enumeration 'hipLimit_t' -hipLimit_t__enumvalues = { - 0: 'hipLimitStackSize', - 1: 'hipLimitPrintfFifoSize', - 2: 'hipLimitMallocHeapSize', - 3: 'hipLimitRange', -} -hipLimitStackSize = 0 -hipLimitPrintfFifoSize = 1 -hipLimitMallocHeapSize = 2 -hipLimitRange = 3 -hipLimit_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemoryAdvise' -hipMemoryAdvise__enumvalues = { - 1: 'hipMemAdviseSetReadMostly', - 2: 'hipMemAdviseUnsetReadMostly', - 3: 'hipMemAdviseSetPreferredLocation', - 4: 'hipMemAdviseUnsetPreferredLocation', - 5: 'hipMemAdviseSetAccessedBy', - 6: 'hipMemAdviseUnsetAccessedBy', - 100: 'hipMemAdviseSetCoarseGrain', - 101: 'hipMemAdviseUnsetCoarseGrain', -} -hipMemAdviseSetReadMostly = 1 -hipMemAdviseUnsetReadMostly = 2 -hipMemAdviseSetPreferredLocation = 3 -hipMemAdviseUnsetPreferredLocation = 4 -hipMemAdviseSetAccessedBy = 5 -hipMemAdviseUnsetAccessedBy = 6 -hipMemAdviseSetCoarseGrain = 100 -hipMemAdviseUnsetCoarseGrain = 101 -hipMemoryAdvise = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemRangeCoherencyMode' -hipMemRangeCoherencyMode__enumvalues = { - 0: 'hipMemRangeCoherencyModeFineGrain', - 1: 'hipMemRangeCoherencyModeCoarseGrain', - 2: 'hipMemRangeCoherencyModeIndeterminate', -} -hipMemRangeCoherencyModeFineGrain = 0 -hipMemRangeCoherencyModeCoarseGrain = 1 -hipMemRangeCoherencyModeIndeterminate = 2 -hipMemRangeCoherencyMode = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemRangeAttribute' -hipMemRangeAttribute__enumvalues = { - 1: 'hipMemRangeAttributeReadMostly', - 2: 'hipMemRangeAttributePreferredLocation', - 3: 'hipMemRangeAttributeAccessedBy', - 4: 'hipMemRangeAttributeLastPrefetchLocation', - 100: 'hipMemRangeAttributeCoherencyMode', -} -hipMemRangeAttributeReadMostly = 1 -hipMemRangeAttributePreferredLocation = 2 -hipMemRangeAttributeAccessedBy = 3 -hipMemRangeAttributeLastPrefetchLocation = 4 -hipMemRangeAttributeCoherencyMode = 100 -hipMemRangeAttribute = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemPoolAttr' -hipMemPoolAttr__enumvalues = { - 1: 'hipMemPoolReuseFollowEventDependencies', - 2: 'hipMemPoolReuseAllowOpportunistic', - 3: 'hipMemPoolReuseAllowInternalDependencies', - 4: 'hipMemPoolAttrReleaseThreshold', - 5: 'hipMemPoolAttrReservedMemCurrent', - 6: 'hipMemPoolAttrReservedMemHigh', - 7: 'hipMemPoolAttrUsedMemCurrent', - 8: 'hipMemPoolAttrUsedMemHigh', -} -hipMemPoolReuseFollowEventDependencies = 1 -hipMemPoolReuseAllowOpportunistic = 2 -hipMemPoolReuseAllowInternalDependencies = 3 -hipMemPoolAttrReleaseThreshold = 4 -hipMemPoolAttrReservedMemCurrent = 5 -hipMemPoolAttrReservedMemHigh = 6 -hipMemPoolAttrUsedMemCurrent = 7 -hipMemPoolAttrUsedMemHigh = 8 -hipMemPoolAttr = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemLocationType' -hipMemLocationType__enumvalues = { - 0: 'hipMemLocationTypeInvalid', - 1: 'hipMemLocationTypeDevice', -} -hipMemLocationTypeInvalid = 0 -hipMemLocationTypeDevice = 1 -hipMemLocationType = ctypes.c_uint32 # enum -class struct_hipMemLocation(Structure): - pass - -struct_hipMemLocation._pack_ = 1 # source:False -struct_hipMemLocation._fields_ = [ - ('type', hipMemLocationType), - ('id', ctypes.c_int32), -] - -hipMemLocation = struct_hipMemLocation - -# values for enumeration 'hipMemAccessFlags' -hipMemAccessFlags__enumvalues = { - 0: 'hipMemAccessFlagsProtNone', - 1: 'hipMemAccessFlagsProtRead', - 3: 'hipMemAccessFlagsProtReadWrite', -} -hipMemAccessFlagsProtNone = 0 -hipMemAccessFlagsProtRead = 1 -hipMemAccessFlagsProtReadWrite = 3 -hipMemAccessFlags = ctypes.c_uint32 # enum -class struct_hipMemAccessDesc(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('location', hipMemLocation), - ('flags', hipMemAccessFlags), - ] - -hipMemAccessDesc = struct_hipMemAccessDesc - -# values for enumeration 'hipMemAllocationType' -hipMemAllocationType__enumvalues = { - 0: 'hipMemAllocationTypeInvalid', - 1: 'hipMemAllocationTypePinned', - 2147483647: 'hipMemAllocationTypeMax', -} -hipMemAllocationTypeInvalid = 0 -hipMemAllocationTypePinned = 1 -hipMemAllocationTypeMax = 2147483647 -hipMemAllocationType = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemAllocationHandleType' -hipMemAllocationHandleType__enumvalues = { - 0: 'hipMemHandleTypeNone', - 1: 'hipMemHandleTypePosixFileDescriptor', - 2: 'hipMemHandleTypeWin32', - 4: 'hipMemHandleTypeWin32Kmt', -} -hipMemHandleTypeNone = 0 -hipMemHandleTypePosixFileDescriptor = 1 -hipMemHandleTypeWin32 = 2 -hipMemHandleTypeWin32Kmt = 4 -hipMemAllocationHandleType = ctypes.c_uint32 # enum -class struct_hipMemPoolProps(Structure): - pass - -struct_hipMemPoolProps._pack_ = 1 # source:False -struct_hipMemPoolProps._fields_ = [ - ('allocType', hipMemAllocationType), - ('handleTypes', hipMemAllocationHandleType), - ('location', hipMemLocation), - ('win32SecurityAttributes', ctypes.POINTER(None)), - ('reserved', ctypes.c_ubyte * 64), -] - -hipMemPoolProps = struct_hipMemPoolProps -class struct_hipMemPoolPtrExportData(Structure): - pass - -struct_hipMemPoolPtrExportData._pack_ = 1 # source:False -struct_hipMemPoolPtrExportData._fields_ = [ - ('reserved', ctypes.c_ubyte * 64), -] - -hipMemPoolPtrExportData = struct_hipMemPoolPtrExportData - -# values for enumeration 'hipJitOption' -hipJitOption__enumvalues = { - 0: 'hipJitOptionMaxRegisters', - 1: 'hipJitOptionThreadsPerBlock', - 2: 'hipJitOptionWallTime', - 3: 'hipJitOptionInfoLogBuffer', - 4: 'hipJitOptionInfoLogBufferSizeBytes', - 5: 'hipJitOptionErrorLogBuffer', - 6: 'hipJitOptionErrorLogBufferSizeBytes', - 7: 'hipJitOptionOptimizationLevel', - 8: 'hipJitOptionTargetFromContext', - 9: 'hipJitOptionTarget', - 10: 'hipJitOptionFallbackStrategy', - 11: 'hipJitOptionGenerateDebugInfo', - 12: 'hipJitOptionLogVerbose', - 13: 'hipJitOptionGenerateLineInfo', - 14: 'hipJitOptionCacheMode', - 15: 'hipJitOptionSm3xOpt', - 16: 'hipJitOptionFastCompile', - 17: 'hipJitOptionNumOptions', -} -hipJitOptionMaxRegisters = 0 -hipJitOptionThreadsPerBlock = 1 -hipJitOptionWallTime = 2 -hipJitOptionInfoLogBuffer = 3 -hipJitOptionInfoLogBufferSizeBytes = 4 -hipJitOptionErrorLogBuffer = 5 -hipJitOptionErrorLogBufferSizeBytes = 6 -hipJitOptionOptimizationLevel = 7 -hipJitOptionTargetFromContext = 8 -hipJitOptionTarget = 9 -hipJitOptionFallbackStrategy = 10 -hipJitOptionGenerateDebugInfo = 11 -hipJitOptionLogVerbose = 12 -hipJitOptionGenerateLineInfo = 13 -hipJitOptionCacheMode = 14 -hipJitOptionSm3xOpt = 15 -hipJitOptionFastCompile = 16 -hipJitOptionNumOptions = 17 -hipJitOption = ctypes.c_uint32 # enum - -# values for enumeration 'hipFuncAttribute' -hipFuncAttribute__enumvalues = { - 8: 'hipFuncAttributeMaxDynamicSharedMemorySize', - 9: 'hipFuncAttributePreferredSharedMemoryCarveout', - 10: 'hipFuncAttributeMax', -} -hipFuncAttributeMaxDynamicSharedMemorySize = 8 -hipFuncAttributePreferredSharedMemoryCarveout = 9 -hipFuncAttributeMax = 10 -hipFuncAttribute = ctypes.c_uint32 # enum - -# values for enumeration 'hipFuncCache_t' -hipFuncCache_t__enumvalues = { - 0: 'hipFuncCachePreferNone', - 1: 'hipFuncCachePreferShared', - 2: 'hipFuncCachePreferL1', - 3: 'hipFuncCachePreferEqual', -} -hipFuncCachePreferNone = 0 -hipFuncCachePreferShared = 1 -hipFuncCachePreferL1 = 2 -hipFuncCachePreferEqual = 3 -hipFuncCache_t = ctypes.c_uint32 # enum - -# values for enumeration 'hipSharedMemConfig' -hipSharedMemConfig__enumvalues = { - 0: 'hipSharedMemBankSizeDefault', - 1: 'hipSharedMemBankSizeFourByte', - 2: 'hipSharedMemBankSizeEightByte', -} -hipSharedMemBankSizeDefault = 0 -hipSharedMemBankSizeFourByte = 1 -hipSharedMemBankSizeEightByte = 2 -hipSharedMemConfig = ctypes.c_uint32 # enum -class struct_dim3(Structure): - pass - -struct_dim3._pack_ = 1 # source:False -struct_dim3._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), -] - -dim3 = struct_dim3 -class struct_hipLaunchParams_t(Structure): - pass - -struct_hipLaunchParams_t._pack_ = 1 # source:False -struct_hipLaunchParams_t._fields_ = [ - ('func', ctypes.POINTER(None)), - ('gridDim', dim3), - ('blockDim', dim3), - ('args', ctypes.POINTER(ctypes.POINTER(None))), - ('sharedMem', ctypes.c_uint64), - ('stream', ctypes.POINTER(struct_ihipStream_t)), -] - -hipLaunchParams = struct_hipLaunchParams_t -class struct_hipFunctionLaunchParams_t(Structure): - pass - -struct_hipFunctionLaunchParams_t._pack_ = 1 # source:False -struct_hipFunctionLaunchParams_t._fields_ = [ - ('function', ctypes.POINTER(struct_ihipModuleSymbol_t)), - ('gridDimX', ctypes.c_uint32), - ('gridDimY', ctypes.c_uint32), - ('gridDimZ', ctypes.c_uint32), - ('blockDimX', ctypes.c_uint32), - ('blockDimY', ctypes.c_uint32), - ('blockDimZ', ctypes.c_uint32), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hStream', ctypes.POINTER(struct_ihipStream_t)), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), -] - -hipFunctionLaunchParams = struct_hipFunctionLaunchParams_t - -# values for enumeration 'hipExternalMemoryHandleType_enum' -hipExternalMemoryHandleType_enum__enumvalues = { - 1: 'hipExternalMemoryHandleTypeOpaqueFd', - 2: 'hipExternalMemoryHandleTypeOpaqueWin32', - 3: 'hipExternalMemoryHandleTypeOpaqueWin32Kmt', - 4: 'hipExternalMemoryHandleTypeD3D12Heap', - 5: 'hipExternalMemoryHandleTypeD3D12Resource', - 6: 'hipExternalMemoryHandleTypeD3D11Resource', - 7: 'hipExternalMemoryHandleTypeD3D11ResourceKmt', - 8: 'hipExternalMemoryHandleTypeNvSciBuf', -} -hipExternalMemoryHandleTypeOpaqueFd = 1 -hipExternalMemoryHandleTypeOpaqueWin32 = 2 -hipExternalMemoryHandleTypeOpaqueWin32Kmt = 3 -hipExternalMemoryHandleTypeD3D12Heap = 4 -hipExternalMemoryHandleTypeD3D12Resource = 5 -hipExternalMemoryHandleTypeD3D11Resource = 6 -hipExternalMemoryHandleTypeD3D11ResourceKmt = 7 -hipExternalMemoryHandleTypeNvSciBuf = 8 -hipExternalMemoryHandleType_enum = ctypes.c_uint32 # enum -hipExternalMemoryHandleType = hipExternalMemoryHandleType_enum -hipExternalMemoryHandleType__enumvalues = hipExternalMemoryHandleType_enum__enumvalues -class struct_hipExternalMemoryHandleDesc_st(Structure): - pass - -class union_hipExternalMemoryHandleDesc_st_handle(Union): - pass - -class struct_hipExternalMemoryHandleDesc_st_0_win32(Structure): - pass - -struct_hipExternalMemoryHandleDesc_st_0_win32._pack_ = 1 # source:False -struct_hipExternalMemoryHandleDesc_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), -] - -union_hipExternalMemoryHandleDesc_st_handle._pack_ = 1 # source:False -union_hipExternalMemoryHandleDesc_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_hipExternalMemoryHandleDesc_st_0_win32), - ('nvSciBufObject', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_hipExternalMemoryHandleDesc_st._pack_ = 1 # source:False -struct_hipExternalMemoryHandleDesc_st._fields_ = [ - ('type', hipExternalMemoryHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_hipExternalMemoryHandleDesc_st_handle), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -hipExternalMemoryHandleDesc = struct_hipExternalMemoryHandleDesc_st -class struct_hipExternalMemoryBufferDesc_st(Structure): - pass - -struct_hipExternalMemoryBufferDesc_st._pack_ = 1 # source:False -struct_hipExternalMemoryBufferDesc_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalMemoryBufferDesc = struct_hipExternalMemoryBufferDesc_st -class struct_hipExternalMemoryMipmappedArrayDesc_st(Structure): - pass - -struct_hipExternalMemoryMipmappedArrayDesc_st._pack_ = 1 # source:False -struct_hipExternalMemoryMipmappedArrayDesc_st._fields_ = [ - ('offset', ctypes.c_uint64), - ('formatDesc', hipChannelFormatDesc), - ('PADDING_0', ctypes.c_ubyte * 4), - ('extent', hipExtent), - ('flags', ctypes.c_uint32), - ('numLevels', ctypes.c_uint32), -] - -hipExternalMemoryMipmappedArrayDesc = struct_hipExternalMemoryMipmappedArrayDesc_st -hipExternalMemory_t = ctypes.POINTER(None) - -# values for enumeration 'hipExternalSemaphoreHandleType_enum' -hipExternalSemaphoreHandleType_enum__enumvalues = { - 1: 'hipExternalSemaphoreHandleTypeOpaqueFd', - 2: 'hipExternalSemaphoreHandleTypeOpaqueWin32', - 3: 'hipExternalSemaphoreHandleTypeOpaqueWin32Kmt', - 4: 'hipExternalSemaphoreHandleTypeD3D12Fence', - 5: 'hipExternalSemaphoreHandleTypeD3D11Fence', - 6: 'hipExternalSemaphoreHandleTypeNvSciSync', - 7: 'hipExternalSemaphoreHandleTypeKeyedMutex', - 8: 'hipExternalSemaphoreHandleTypeKeyedMutexKmt', - 9: 'hipExternalSemaphoreHandleTypeTimelineSemaphoreFd', - 10: 'hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32', -} -hipExternalSemaphoreHandleTypeOpaqueFd = 1 -hipExternalSemaphoreHandleTypeOpaqueWin32 = 2 -hipExternalSemaphoreHandleTypeOpaqueWin32Kmt = 3 -hipExternalSemaphoreHandleTypeD3D12Fence = 4 -hipExternalSemaphoreHandleTypeD3D11Fence = 5 -hipExternalSemaphoreHandleTypeNvSciSync = 6 -hipExternalSemaphoreHandleTypeKeyedMutex = 7 -hipExternalSemaphoreHandleTypeKeyedMutexKmt = 8 -hipExternalSemaphoreHandleTypeTimelineSemaphoreFd = 9 -hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32 = 10 -hipExternalSemaphoreHandleType_enum = ctypes.c_uint32 # enum -hipExternalSemaphoreHandleType = hipExternalSemaphoreHandleType_enum -hipExternalSemaphoreHandleType__enumvalues = hipExternalSemaphoreHandleType_enum__enumvalues -class struct_hipExternalSemaphoreHandleDesc_st(Structure): - pass - -class union_hipExternalSemaphoreHandleDesc_st_handle(Union): - pass - -class struct_hipExternalSemaphoreHandleDesc_st_0_win32(Structure): - pass - -struct_hipExternalSemaphoreHandleDesc_st_0_win32._pack_ = 1 # source:False -struct_hipExternalSemaphoreHandleDesc_st_0_win32._fields_ = [ - ('handle', ctypes.POINTER(None)), - ('name', ctypes.POINTER(None)), -] - -union_hipExternalSemaphoreHandleDesc_st_handle._pack_ = 1 # source:False -union_hipExternalSemaphoreHandleDesc_st_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('win32', struct_hipExternalSemaphoreHandleDesc_st_0_win32), - ('NvSciSyncObj', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_hipExternalSemaphoreHandleDesc_st._pack_ = 1 # source:False -struct_hipExternalSemaphoreHandleDesc_st._fields_ = [ - ('type', hipExternalSemaphoreHandleType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('handle', union_hipExternalSemaphoreHandleDesc_st_handle), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreHandleDesc = struct_hipExternalSemaphoreHandleDesc_st -hipExternalSemaphore_t = ctypes.POINTER(None) -class struct_hipExternalSemaphoreSignalParams_st(Structure): - pass - -class struct_hipExternalSemaphoreSignalParams_st_params(Structure): - pass - -class struct_hipExternalSemaphoreSignalParams_st_0_fence(Structure): - pass - -struct_hipExternalSemaphoreSignalParams_st_0_fence._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), -] - -class union_hipExternalSemaphoreSignalParams_st_0_nvSciSync(Union): - pass - -union_hipExternalSemaphoreSignalParams_st_0_nvSciSync._pack_ = 1 # source:False -union_hipExternalSemaphoreSignalParams_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), -] - -class struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex(Structure): - pass - -struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), -] - -struct_hipExternalSemaphoreSignalParams_st_params._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st_params._fields_ = [ - ('fence', struct_hipExternalSemaphoreSignalParams_st_0_fence), - ('nvSciSync', union_hipExternalSemaphoreSignalParams_st_0_nvSciSync), - ('keyedMutex', struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 12), -] - -struct_hipExternalSemaphoreSignalParams_st._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalParams_st._fields_ = [ - ('params', struct_hipExternalSemaphoreSignalParams_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreSignalParams = struct_hipExternalSemaphoreSignalParams_st -class struct_hipExternalSemaphoreWaitParams_st(Structure): - pass - -class struct_hipExternalSemaphoreWaitParams_st_params(Structure): - pass - -class struct_hipExternalSemaphoreWaitParams_st_0_fence(Structure): - pass - -struct_hipExternalSemaphoreWaitParams_st_0_fence._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st_0_fence._fields_ = [ - ('value', ctypes.c_uint64), -] - -class union_hipExternalSemaphoreWaitParams_st_0_nvSciSync(Union): - pass - -union_hipExternalSemaphoreWaitParams_st_0_nvSciSync._pack_ = 1 # source:False -union_hipExternalSemaphoreWaitParams_st_0_nvSciSync._fields_ = [ - ('fence', ctypes.POINTER(None)), - ('reserved', ctypes.c_uint64), -] - -class struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex(Structure): - pass - -struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex._fields_ = [ - ('key', ctypes.c_uint64), - ('timeoutMs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_hipExternalSemaphoreWaitParams_st_params._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st_params._fields_ = [ - ('fence', struct_hipExternalSemaphoreWaitParams_st_0_fence), - ('nvSciSync', union_hipExternalSemaphoreWaitParams_st_0_nvSciSync), - ('keyedMutex', struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex), - ('reserved', ctypes.c_uint32 * 10), -] - -struct_hipExternalSemaphoreWaitParams_st._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitParams_st._fields_ = [ - ('params', struct_hipExternalSemaphoreWaitParams_st_params), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreWaitParams = struct_hipExternalSemaphoreWaitParams_st -try: - __hipGetPCH = _libraries['libamdhip64.so'].__hipGetPCH - __hipGetPCH.restype = None - __hipGetPCH.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass - -# values for enumeration 'hipGraphicsRegisterFlags' -hipGraphicsRegisterFlags__enumvalues = { - 0: 'hipGraphicsRegisterFlagsNone', - 1: 'hipGraphicsRegisterFlagsReadOnly', - 2: 'hipGraphicsRegisterFlagsWriteDiscard', - 4: 'hipGraphicsRegisterFlagsSurfaceLoadStore', - 8: 'hipGraphicsRegisterFlagsTextureGather', -} -hipGraphicsRegisterFlagsNone = 0 -hipGraphicsRegisterFlagsReadOnly = 1 -hipGraphicsRegisterFlagsWriteDiscard = 2 -hipGraphicsRegisterFlagsSurfaceLoadStore = 4 -hipGraphicsRegisterFlagsTextureGather = 8 -hipGraphicsRegisterFlags = ctypes.c_uint32 # enum -class struct__hipGraphicsResource(Structure): - pass - -hipGraphicsResource = struct__hipGraphicsResource -hipGraphicsResource_t = ctypes.POINTER(struct__hipGraphicsResource) -class struct_ihipGraph(Structure): - pass - -hipGraph_t = ctypes.POINTER(struct_ihipGraph) -class struct_hipGraphNode(Structure): - pass - -hipGraphNode_t = ctypes.POINTER(struct_hipGraphNode) -class struct_hipGraphExec(Structure): - pass - -hipGraphExec_t = ctypes.POINTER(struct_hipGraphExec) -class struct_hipUserObject(Structure): - pass - -hipUserObject_t = ctypes.POINTER(struct_hipUserObject) - -# values for enumeration 'hipGraphNodeType' -hipGraphNodeType__enumvalues = { - 0: 'hipGraphNodeTypeKernel', - 1: 'hipGraphNodeTypeMemcpy', - 2: 'hipGraphNodeTypeMemset', - 3: 'hipGraphNodeTypeHost', - 4: 'hipGraphNodeTypeGraph', - 5: 'hipGraphNodeTypeEmpty', - 6: 'hipGraphNodeTypeWaitEvent', - 7: 'hipGraphNodeTypeEventRecord', - 8: 'hipGraphNodeTypeExtSemaphoreSignal', - 9: 'hipGraphNodeTypeExtSemaphoreWait', - 10: 'hipGraphNodeTypeMemAlloc', - 11: 'hipGraphNodeTypeMemFree', - 12: 'hipGraphNodeTypeMemcpyFromSymbol', - 13: 'hipGraphNodeTypeMemcpyToSymbol', - 14: 'hipGraphNodeTypeCount', -} -hipGraphNodeTypeKernel = 0 -hipGraphNodeTypeMemcpy = 1 -hipGraphNodeTypeMemset = 2 -hipGraphNodeTypeHost = 3 -hipGraphNodeTypeGraph = 4 -hipGraphNodeTypeEmpty = 5 -hipGraphNodeTypeWaitEvent = 6 -hipGraphNodeTypeEventRecord = 7 -hipGraphNodeTypeExtSemaphoreSignal = 8 -hipGraphNodeTypeExtSemaphoreWait = 9 -hipGraphNodeTypeMemAlloc = 10 -hipGraphNodeTypeMemFree = 11 -hipGraphNodeTypeMemcpyFromSymbol = 12 -hipGraphNodeTypeMemcpyToSymbol = 13 -hipGraphNodeTypeCount = 14 -hipGraphNodeType = ctypes.c_uint32 # enum -hipHostFn_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -class struct_hipHostNodeParams(Structure): - pass - -struct_hipHostNodeParams._pack_ = 1 # source:False -struct_hipHostNodeParams._fields_ = [ - ('fn', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('userData', ctypes.POINTER(None)), -] - -hipHostNodeParams = struct_hipHostNodeParams -class struct_hipKernelNodeParams(Structure): - pass - -struct_hipKernelNodeParams._pack_ = 1 # source:False -struct_hipKernelNodeParams._fields_ = [ - ('blockDim', dim3), - ('PADDING_0', ctypes.c_ubyte * 4), - ('extra', ctypes.POINTER(ctypes.POINTER(None))), - ('func', ctypes.POINTER(None)), - ('gridDim', dim3), - ('PADDING_1', ctypes.c_ubyte * 4), - ('kernelParams', ctypes.POINTER(ctypes.POINTER(None))), - ('sharedMemBytes', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -hipKernelNodeParams = struct_hipKernelNodeParams -class struct_hipMemsetParams(Structure): - pass - -struct_hipMemsetParams._pack_ = 1 # source:False -struct_hipMemsetParams._fields_ = [ - ('dst', ctypes.POINTER(None)), - ('elementSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('height', ctypes.c_uint64), - ('pitch', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), -] - -hipMemsetParams = struct_hipMemsetParams -class struct_hipMemAllocNodeParams(Structure): - pass - -struct_hipMemAllocNodeParams._pack_ = 1 # source:False -struct_hipMemAllocNodeParams._fields_ = [ - ('poolProps', hipMemPoolProps), - ('accessDescs', ctypes.POINTER(struct_hipMemAccessDesc)), - ('accessDescCount', ctypes.c_uint64), - ('bytesize', ctypes.c_uint64), - ('dptr', ctypes.POINTER(None)), -] - -hipMemAllocNodeParams = struct_hipMemAllocNodeParams - -# values for enumeration 'hipKernelNodeAttrID' -hipKernelNodeAttrID__enumvalues = { - 1: 'hipKernelNodeAttributeAccessPolicyWindow', - 2: 'hipKernelNodeAttributeCooperative', -} -hipKernelNodeAttributeAccessPolicyWindow = 1 -hipKernelNodeAttributeCooperative = 2 -hipKernelNodeAttrID = ctypes.c_uint32 # enum - -# values for enumeration 'hipAccessProperty' -hipAccessProperty__enumvalues = { - 0: 'hipAccessPropertyNormal', - 1: 'hipAccessPropertyStreaming', - 2: 'hipAccessPropertyPersisting', -} -hipAccessPropertyNormal = 0 -hipAccessPropertyStreaming = 1 -hipAccessPropertyPersisting = 2 -hipAccessProperty = ctypes.c_uint32 # enum -class struct_hipAccessPolicyWindow(Structure): - pass - -struct_hipAccessPolicyWindow._pack_ = 1 # source:False -struct_hipAccessPolicyWindow._fields_ = [ - ('base_ptr', ctypes.POINTER(None)), - ('hitProp', hipAccessProperty), - ('hitRatio', ctypes.c_float), - ('missProp', hipAccessProperty), - ('PADDING_0', ctypes.c_ubyte * 4), - ('num_bytes', ctypes.c_uint64), -] - -hipAccessPolicyWindow = struct_hipAccessPolicyWindow -class union_hipKernelNodeAttrValue(Union): - pass - -union_hipKernelNodeAttrValue._pack_ = 1 # source:False -union_hipKernelNodeAttrValue._fields_ = [ - ('accessPolicyWindow', hipAccessPolicyWindow), - ('cooperative', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 28), -] - -hipKernelNodeAttrValue = union_hipKernelNodeAttrValue - -# values for enumeration 'hipGraphExecUpdateResult' -hipGraphExecUpdateResult__enumvalues = { - 0: 'hipGraphExecUpdateSuccess', - 1: 'hipGraphExecUpdateError', - 2: 'hipGraphExecUpdateErrorTopologyChanged', - 3: 'hipGraphExecUpdateErrorNodeTypeChanged', - 4: 'hipGraphExecUpdateErrorFunctionChanged', - 5: 'hipGraphExecUpdateErrorParametersChanged', - 6: 'hipGraphExecUpdateErrorNotSupported', - 7: 'hipGraphExecUpdateErrorUnsupportedFunctionChange', -} -hipGraphExecUpdateSuccess = 0 -hipGraphExecUpdateError = 1 -hipGraphExecUpdateErrorTopologyChanged = 2 -hipGraphExecUpdateErrorNodeTypeChanged = 3 -hipGraphExecUpdateErrorFunctionChanged = 4 -hipGraphExecUpdateErrorParametersChanged = 5 -hipGraphExecUpdateErrorNotSupported = 6 -hipGraphExecUpdateErrorUnsupportedFunctionChange = 7 -hipGraphExecUpdateResult = ctypes.c_uint32 # enum - -# values for enumeration 'hipStreamCaptureMode' -hipStreamCaptureMode__enumvalues = { - 0: 'hipStreamCaptureModeGlobal', - 1: 'hipStreamCaptureModeThreadLocal', - 2: 'hipStreamCaptureModeRelaxed', -} -hipStreamCaptureModeGlobal = 0 -hipStreamCaptureModeThreadLocal = 1 -hipStreamCaptureModeRelaxed = 2 -hipStreamCaptureMode = ctypes.c_uint32 # enum - -# values for enumeration 'hipStreamCaptureStatus' -hipStreamCaptureStatus__enumvalues = { - 0: 'hipStreamCaptureStatusNone', - 1: 'hipStreamCaptureStatusActive', - 2: 'hipStreamCaptureStatusInvalidated', -} -hipStreamCaptureStatusNone = 0 -hipStreamCaptureStatusActive = 1 -hipStreamCaptureStatusInvalidated = 2 -hipStreamCaptureStatus = ctypes.c_uint32 # enum - -# values for enumeration 'hipStreamUpdateCaptureDependenciesFlags' -hipStreamUpdateCaptureDependenciesFlags__enumvalues = { - 0: 'hipStreamAddCaptureDependencies', - 1: 'hipStreamSetCaptureDependencies', -} -hipStreamAddCaptureDependencies = 0 -hipStreamSetCaptureDependencies = 1 -hipStreamUpdateCaptureDependenciesFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipGraphMemAttributeType' -hipGraphMemAttributeType__enumvalues = { - 0: 'hipGraphMemAttrUsedMemCurrent', - 1: 'hipGraphMemAttrUsedMemHigh', - 2: 'hipGraphMemAttrReservedMemCurrent', - 3: 'hipGraphMemAttrReservedMemHigh', -} -hipGraphMemAttrUsedMemCurrent = 0 -hipGraphMemAttrUsedMemHigh = 1 -hipGraphMemAttrReservedMemCurrent = 2 -hipGraphMemAttrReservedMemHigh = 3 -hipGraphMemAttributeType = ctypes.c_uint32 # enum - -# values for enumeration 'hipUserObjectFlags' -hipUserObjectFlags__enumvalues = { - 1: 'hipUserObjectNoDestructorSync', -} -hipUserObjectNoDestructorSync = 1 -hipUserObjectFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipUserObjectRetainFlags' -hipUserObjectRetainFlags__enumvalues = { - 1: 'hipGraphUserObjectMove', -} -hipGraphUserObjectMove = 1 -hipUserObjectRetainFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipGraphInstantiateFlags' -hipGraphInstantiateFlags__enumvalues = { - 1: 'hipGraphInstantiateFlagAutoFreeOnLaunch', - 2: 'hipGraphInstantiateFlagUpload', - 4: 'hipGraphInstantiateFlagDeviceLaunch', - 8: 'hipGraphInstantiateFlagUseNodePriority', -} -hipGraphInstantiateFlagAutoFreeOnLaunch = 1 -hipGraphInstantiateFlagUpload = 2 -hipGraphInstantiateFlagDeviceLaunch = 4 -hipGraphInstantiateFlagUseNodePriority = 8 -hipGraphInstantiateFlags = ctypes.c_uint32 # enum - -# values for enumeration 'hipGraphDebugDotFlags' -hipGraphDebugDotFlags__enumvalues = { - 1: 'hipGraphDebugDotFlagsVerbose', - 4: 'hipGraphDebugDotFlagsKernelNodeParams', - 8: 'hipGraphDebugDotFlagsMemcpyNodeParams', - 16: 'hipGraphDebugDotFlagsMemsetNodeParams', - 32: 'hipGraphDebugDotFlagsHostNodeParams', - 64: 'hipGraphDebugDotFlagsEventNodeParams', - 128: 'hipGraphDebugDotFlagsExtSemasSignalNodeParams', - 256: 'hipGraphDebugDotFlagsExtSemasWaitNodeParams', - 512: 'hipGraphDebugDotFlagsKernelNodeAttributes', - 1024: 'hipGraphDebugDotFlagsHandles', -} -hipGraphDebugDotFlagsVerbose = 1 -hipGraphDebugDotFlagsKernelNodeParams = 4 -hipGraphDebugDotFlagsMemcpyNodeParams = 8 -hipGraphDebugDotFlagsMemsetNodeParams = 16 -hipGraphDebugDotFlagsHostNodeParams = 32 -hipGraphDebugDotFlagsEventNodeParams = 64 -hipGraphDebugDotFlagsExtSemasSignalNodeParams = 128 -hipGraphDebugDotFlagsExtSemasWaitNodeParams = 256 -hipGraphDebugDotFlagsKernelNodeAttributes = 512 -hipGraphDebugDotFlagsHandles = 1024 -hipGraphDebugDotFlags = ctypes.c_uint32 # enum -class struct_hipMemAllocationProp(Structure): - pass - -class struct_hipMemAllocationProp_allocFlags(Structure): - pass - -struct_hipMemAllocationProp_allocFlags._pack_ = 1 # source:False -struct_hipMemAllocationProp_allocFlags._fields_ = [ - ('compressionType', ctypes.c_ubyte), - ('gpuDirectRDMACapable', ctypes.c_ubyte), - ('usage', ctypes.c_uint16), -] - -struct_hipMemAllocationProp._pack_ = 1 # source:False -struct_hipMemAllocationProp._fields_ = [ - ('type', hipMemAllocationType), - ('requestedHandleType', hipMemAllocationHandleType), - ('location', hipMemLocation), - ('win32HandleMetaData', ctypes.POINTER(None)), - ('allocFlags', struct_hipMemAllocationProp_allocFlags), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipMemAllocationProp = struct_hipMemAllocationProp -class struct_hipExternalSemaphoreSignalNodeParams(Structure): - pass - -struct_hipExternalSemaphoreSignalNodeParams._pack_ = 1 # source:False -struct_hipExternalSemaphoreSignalNodeParams._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(None))), - ('paramsArray', ctypes.POINTER(struct_hipExternalSemaphoreSignalParams_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreSignalNodeParams = struct_hipExternalSemaphoreSignalNodeParams -class struct_hipExternalSemaphoreWaitNodeParams(Structure): - pass - -struct_hipExternalSemaphoreWaitNodeParams._pack_ = 1 # source:False -struct_hipExternalSemaphoreWaitNodeParams._fields_ = [ - ('extSemArray', ctypes.POINTER(ctypes.POINTER(None))), - ('paramsArray', ctypes.POINTER(struct_hipExternalSemaphoreWaitParams_st)), - ('numExtSems', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -hipExternalSemaphoreWaitNodeParams = struct_hipExternalSemaphoreWaitNodeParams -class struct_ihipMemGenericAllocationHandle(Structure): - pass - -hipMemGenericAllocationHandle_t = ctypes.POINTER(struct_ihipMemGenericAllocationHandle) - -# values for enumeration 'hipMemAllocationGranularity_flags' -hipMemAllocationGranularity_flags__enumvalues = { - 0: 'hipMemAllocationGranularityMinimum', - 1: 'hipMemAllocationGranularityRecommended', -} -hipMemAllocationGranularityMinimum = 0 -hipMemAllocationGranularityRecommended = 1 -hipMemAllocationGranularity_flags = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemHandleType' -hipMemHandleType__enumvalues = { - 0: 'hipMemHandleTypeGeneric', -} -hipMemHandleTypeGeneric = 0 -hipMemHandleType = ctypes.c_uint32 # enum - -# values for enumeration 'hipMemOperationType' -hipMemOperationType__enumvalues = { - 1: 'hipMemOperationTypeMap', - 2: 'hipMemOperationTypeUnmap', -} -hipMemOperationTypeMap = 1 -hipMemOperationTypeUnmap = 2 -hipMemOperationType = ctypes.c_uint32 # enum - -# values for enumeration 'hipArraySparseSubresourceType' -hipArraySparseSubresourceType__enumvalues = { - 0: 'hipArraySparseSubresourceTypeSparseLevel', - 1: 'hipArraySparseSubresourceTypeMiptail', -} -hipArraySparseSubresourceTypeSparseLevel = 0 -hipArraySparseSubresourceTypeMiptail = 1 -hipArraySparseSubresourceType = ctypes.c_uint32 # enum -class struct_hipArrayMapInfo(Structure): - pass - -class union_hipArrayMapInfo_resource(Union): - pass - -union_hipArrayMapInfo_resource._pack_ = 1 # source:False -union_hipArrayMapInfo_resource._fields_ = [ - ('mipmap', hipMipmappedArray), - ('array', ctypes.POINTER(struct_hipArray)), - ('PADDING_0', ctypes.c_ubyte * 56), -] - -class union_hipArrayMapInfo_subresource(Union): - pass - -class struct_hipArrayMapInfo_1_sparseLevel(Structure): - pass - -struct_hipArrayMapInfo_1_sparseLevel._pack_ = 1 # source:False -struct_hipArrayMapInfo_1_sparseLevel._fields_ = [ - ('level', ctypes.c_uint32), - ('layer', ctypes.c_uint32), - ('offsetX', ctypes.c_uint32), - ('offsetY', ctypes.c_uint32), - ('offsetZ', ctypes.c_uint32), - ('extentWidth', ctypes.c_uint32), - ('extentHeight', ctypes.c_uint32), - ('extentDepth', ctypes.c_uint32), -] - -class struct_hipArrayMapInfo_1_miptail(Structure): - pass - -struct_hipArrayMapInfo_1_miptail._pack_ = 1 # source:False -struct_hipArrayMapInfo_1_miptail._fields_ = [ - ('layer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -union_hipArrayMapInfo_subresource._pack_ = 1 # source:False -union_hipArrayMapInfo_subresource._fields_ = [ - ('sparseLevel', struct_hipArrayMapInfo_1_sparseLevel), - ('miptail', struct_hipArrayMapInfo_1_miptail), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -class union_hipArrayMapInfo_memHandle(Union): - pass - -union_hipArrayMapInfo_memHandle._pack_ = 1 # source:False -union_hipArrayMapInfo_memHandle._fields_ = [ - ('memHandle', ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), -] - -struct_hipArrayMapInfo._pack_ = 1 # source:False -struct_hipArrayMapInfo._fields_ = [ - ('resourceType', hipResourceType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resource', union_hipArrayMapInfo_resource), - ('subresourceType', hipArraySparseSubresourceType), - ('PADDING_1', ctypes.c_ubyte * 4), - ('subresource', union_hipArrayMapInfo_subresource), - ('memOperationType', hipMemOperationType), - ('memHandleType', hipMemHandleType), - ('memHandle', union_hipArrayMapInfo_memHandle), - ('offset', ctypes.c_uint64), - ('deviceBitMask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32 * 2), -] - -hipArrayMapInfo = struct_hipArrayMapInfo -try: - hipInit = _libraries['libamdhip64.so'].hipInit - hipInit.restype = hipError_t - hipInit.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - hipDriverGetVersion = _libraries['libamdhip64.so'].hipDriverGetVersion - hipDriverGetVersion.restype = hipError_t - hipDriverGetVersion.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipRuntimeGetVersion = _libraries['libamdhip64.so'].hipRuntimeGetVersion - hipRuntimeGetVersion.restype = hipError_t - hipRuntimeGetVersion.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipDeviceGet = _libraries['libamdhip64.so'].hipDeviceGet - hipDeviceGet.restype = hipError_t - hipDeviceGet.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceComputeCapability = _libraries['libamdhip64.so'].hipDeviceComputeCapability - hipDeviceComputeCapability.restype = hipError_t - hipDeviceComputeCapability.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipDevice_t] -except AttributeError: - pass -try: - hipDeviceGetName = _libraries['libamdhip64.so'].hipDeviceGetName - hipDeviceGetName.restype = hipError_t - hipDeviceGetName.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, hipDevice_t] -except AttributeError: - pass -try: - hipDeviceGetUuid = _libraries['libamdhip64.so'].hipDeviceGetUuid - hipDeviceGetUuid.restype = hipError_t - hipDeviceGetUuid.argtypes = [ctypes.POINTER(struct_hipUUID_t), hipDevice_t] -except AttributeError: - pass -try: - hipDeviceGetP2PAttribute = _libraries['libamdhip64.so'].hipDeviceGetP2PAttribute - hipDeviceGetP2PAttribute.restype = hipError_t - hipDeviceGetP2PAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), hipDeviceP2PAttr, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetPCIBusId = _libraries['libamdhip64.so'].hipDeviceGetPCIBusId - hipDeviceGetPCIBusId.restype = hipError_t - hipDeviceGetPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetByPCIBusId = _libraries['libamdhip64.so'].hipDeviceGetByPCIBusId - hipDeviceGetByPCIBusId.restype = hipError_t - hipDeviceGetByPCIBusId.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipDeviceTotalMem = _libraries['libamdhip64.so'].hipDeviceTotalMem - hipDeviceTotalMem.restype = hipError_t - hipDeviceTotalMem.argtypes = [ctypes.POINTER(ctypes.c_uint64), hipDevice_t] -except AttributeError: - pass -try: - hipDeviceSynchronize = _libraries['libamdhip64.so'].hipDeviceSynchronize - hipDeviceSynchronize.restype = hipError_t - hipDeviceSynchronize.argtypes = [] -except AttributeError: - pass -try: - hipDeviceReset = _libraries['libamdhip64.so'].hipDeviceReset - hipDeviceReset.restype = hipError_t - hipDeviceReset.argtypes = [] -except AttributeError: - pass -try: - hipSetDevice = _libraries['libamdhip64.so'].hipSetDevice - hipSetDevice.restype = hipError_t - hipSetDevice.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hipGetDevice = _libraries['libamdhip64.so'].hipGetDevice - hipGetDevice.restype = hipError_t - hipGetDevice.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipGetDeviceCount = _libraries['libamdhip64.so'].hipGetDeviceCount - hipGetDeviceCount.restype = hipError_t - hipGetDeviceCount.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipDeviceGetAttribute = _libraries['libamdhip64.so'].hipDeviceGetAttribute - hipDeviceGetAttribute.restype = hipError_t - hipDeviceGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), hipDeviceAttribute_t, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetDefaultMemPool = _libraries['libamdhip64.so'].hipDeviceGetDefaultMemPool - hipDeviceGetDefaultMemPool.restype = hipError_t - hipDeviceGetDefaultMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceSetMemPool = _libraries['libamdhip64.so'].hipDeviceSetMemPool - hipDeviceSetMemPool.restype = hipError_t - hipDeviceSetMemPool.argtypes = [ctypes.c_int32, hipMemPool_t] -except AttributeError: - pass -try: - hipDeviceGetMemPool = _libraries['libamdhip64.so'].hipDeviceGetMemPool - hipDeviceGetMemPool.restype = hipError_t - hipDeviceGetMemPool.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.c_int32] -except AttributeError: - pass -try: - hipGetDevicePropertiesR0600 = _libraries['libamdhip64.so'].hipGetDevicePropertiesR0600 - hipGetDevicePropertiesR0600.restype = hipError_t - hipGetDevicePropertiesR0600.argtypes = [ctypes.POINTER(struct_hipDeviceProp_tR0600), ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceSetCacheConfig = _libraries['libamdhip64.so'].hipDeviceSetCacheConfig - hipDeviceSetCacheConfig.restype = hipError_t - hipDeviceSetCacheConfig.argtypes = [hipFuncCache_t] -except AttributeError: - pass -try: - hipDeviceGetCacheConfig = _libraries['libamdhip64.so'].hipDeviceGetCacheConfig - hipDeviceGetCacheConfig.restype = hipError_t - hipDeviceGetCacheConfig.argtypes = [ctypes.POINTER(hipFuncCache_t)] -except AttributeError: - pass -try: - hipDeviceGetLimit = _libraries['libamdhip64.so'].hipDeviceGetLimit - hipDeviceGetLimit.restype = hipError_t - hipDeviceGetLimit.argtypes = [ctypes.POINTER(ctypes.c_uint64), hipLimit_t] -except AttributeError: - pass -try: - hipDeviceSetLimit = _libraries['libamdhip64.so'].hipDeviceSetLimit - hipDeviceSetLimit.restype = hipError_t - hipDeviceSetLimit.argtypes = [hipLimit_t, size_t] -except AttributeError: - pass -try: - hipDeviceGetSharedMemConfig = _libraries['libamdhip64.so'].hipDeviceGetSharedMemConfig - hipDeviceGetSharedMemConfig.restype = hipError_t - hipDeviceGetSharedMemConfig.argtypes = [ctypes.POINTER(hipSharedMemConfig)] -except AttributeError: - pass -try: - hipGetDeviceFlags = _libraries['libamdhip64.so'].hipGetDeviceFlags - hipGetDeviceFlags.restype = hipError_t - hipGetDeviceFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipDeviceSetSharedMemConfig = _libraries['libamdhip64.so'].hipDeviceSetSharedMemConfig - hipDeviceSetSharedMemConfig.restype = hipError_t - hipDeviceSetSharedMemConfig.argtypes = [hipSharedMemConfig] -except AttributeError: - pass -try: - hipSetDeviceFlags = _libraries['libamdhip64.so'].hipSetDeviceFlags - hipSetDeviceFlags.restype = hipError_t - hipSetDeviceFlags.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - hipChooseDeviceR0600 = _libraries['libamdhip64.so'].hipChooseDeviceR0600 - hipChooseDeviceR0600.restype = hipError_t - hipChooseDeviceR0600.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(struct_hipDeviceProp_tR0600)] -except AttributeError: - pass -try: - hipExtGetLinkTypeAndHopCount = _libraries['libamdhip64.so'].hipExtGetLinkTypeAndHopCount - hipExtGetLinkTypeAndHopCount.restype = hipError_t - hipExtGetLinkTypeAndHopCount.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipIpcGetMemHandle = _libraries['libamdhip64.so'].hipIpcGetMemHandle - hipIpcGetMemHandle.restype = hipError_t - hipIpcGetMemHandle.argtypes = [ctypes.POINTER(struct_hipIpcMemHandle_st), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipIpcOpenMemHandle = _libraries['libamdhip64.so'].hipIpcOpenMemHandle - hipIpcOpenMemHandle.restype = hipError_t - hipIpcOpenMemHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), hipIpcMemHandle_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipIpcCloseMemHandle = _libraries['libamdhip64.so'].hipIpcCloseMemHandle - hipIpcCloseMemHandle.restype = hipError_t - hipIpcCloseMemHandle.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipIpcGetEventHandle = _libraries['libamdhip64.so'].hipIpcGetEventHandle - hipIpcGetEventHandle.restype = hipError_t - hipIpcGetEventHandle.argtypes = [ctypes.POINTER(struct_hipIpcEventHandle_st), hipEvent_t] -except AttributeError: - pass -try: - hipIpcOpenEventHandle = _libraries['libamdhip64.so'].hipIpcOpenEventHandle - hipIpcOpenEventHandle.restype = hipError_t - hipIpcOpenEventHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t)), hipIpcEventHandle_t] -except AttributeError: - pass -try: - hipFuncSetAttribute = _libraries['libamdhip64.so'].hipFuncSetAttribute - hipFuncSetAttribute.restype = hipError_t - hipFuncSetAttribute.argtypes = [ctypes.POINTER(None), hipFuncAttribute, ctypes.c_int32] -except AttributeError: - pass -try: - hipFuncSetCacheConfig = _libraries['libamdhip64.so'].hipFuncSetCacheConfig - hipFuncSetCacheConfig.restype = hipError_t - hipFuncSetCacheConfig.argtypes = [ctypes.POINTER(None), hipFuncCache_t] -except AttributeError: - pass -try: - hipFuncSetSharedMemConfig = _libraries['libamdhip64.so'].hipFuncSetSharedMemConfig - hipFuncSetSharedMemConfig.restype = hipError_t - hipFuncSetSharedMemConfig.argtypes = [ctypes.POINTER(None), hipSharedMemConfig] -except AttributeError: - pass -try: - hipGetLastError = _libraries['libamdhip64.so'].hipGetLastError - hipGetLastError.restype = hipError_t - hipGetLastError.argtypes = [] -except AttributeError: - pass -try: - hipExtGetLastError = _libraries['libamdhip64.so'].hipExtGetLastError - hipExtGetLastError.restype = hipError_t - hipExtGetLastError.argtypes = [] -except AttributeError: - pass -try: - hipPeekAtLastError = _libraries['libamdhip64.so'].hipPeekAtLastError - hipPeekAtLastError.restype = hipError_t - hipPeekAtLastError.argtypes = [] -except AttributeError: - pass -try: - hipGetErrorName = _libraries['libamdhip64.so'].hipGetErrorName - hipGetErrorName.restype = ctypes.POINTER(ctypes.c_char) - hipGetErrorName.argtypes = [hipError_t] -except AttributeError: - pass -try: - hipGetErrorString = _libraries['libamdhip64.so'].hipGetErrorString - hipGetErrorString.restype = ctypes.POINTER(ctypes.c_char) - hipGetErrorString.argtypes = [hipError_t] -except AttributeError: - pass -try: - hipDrvGetErrorName = _libraries['libamdhip64.so'].hipDrvGetErrorName - hipDrvGetErrorName.restype = hipError_t - hipDrvGetErrorName.argtypes = [hipError_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hipDrvGetErrorString = _libraries['libamdhip64.so'].hipDrvGetErrorString - hipDrvGetErrorString.restype = hipError_t - hipDrvGetErrorString.argtypes = [hipError_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hipStreamCreate = _libraries['libamdhip64.so'].hipStreamCreate - hipStreamCreate.restype = hipError_t - hipStreamCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t))] -except AttributeError: - pass -try: - hipStreamCreateWithFlags = _libraries['libamdhip64.so'].hipStreamCreateWithFlags - hipStreamCreateWithFlags.restype = hipError_t - hipStreamCreateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t)), ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamCreateWithPriority = _libraries['libamdhip64.so'].hipStreamCreateWithPriority - hipStreamCreateWithPriority.restype = hipError_t - hipStreamCreateWithPriority.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t)), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceGetStreamPriorityRange = _libraries['libamdhip64.so'].hipDeviceGetStreamPriorityRange - hipDeviceGetStreamPriorityRange.restype = hipError_t - hipDeviceGetStreamPriorityRange.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipStreamDestroy = _libraries['libamdhip64.so'].hipStreamDestroy - hipStreamDestroy.restype = hipError_t - hipStreamDestroy.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamQuery = _libraries['libamdhip64.so'].hipStreamQuery - hipStreamQuery.restype = hipError_t - hipStreamQuery.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamSynchronize = _libraries['libamdhip64.so'].hipStreamSynchronize - hipStreamSynchronize.restype = hipError_t - hipStreamSynchronize.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamWaitEvent = _libraries['libamdhip64.so'].hipStreamWaitEvent - hipStreamWaitEvent.restype = hipError_t - hipStreamWaitEvent.argtypes = [hipStream_t, hipEvent_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamGetFlags = _libraries['libamdhip64.so'].hipStreamGetFlags - hipStreamGetFlags.restype = hipError_t - hipStreamGetFlags.argtypes = [hipStream_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipStreamGetPriority = _libraries['libamdhip64.so'].hipStreamGetPriority - hipStreamGetPriority.restype = hipError_t - hipStreamGetPriority.argtypes = [hipStream_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipStreamGetDevice = _libraries['libamdhip64.so'].hipStreamGetDevice - hipStreamGetDevice.restype = hipError_t - hipStreamGetDevice.argtypes = [hipStream_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +def dll(): + try: return ctypes.CDLL(unwrap(os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libamdhip64.so')) + except: pass + return None +dll = dll() + +hipError_t = CEnum(ctypes.c_uint32) +hipSuccess = hipError_t.define('hipSuccess', 0) +hipErrorInvalidValue = hipError_t.define('hipErrorInvalidValue', 1) +hipErrorOutOfMemory = hipError_t.define('hipErrorOutOfMemory', 2) +hipErrorMemoryAllocation = hipError_t.define('hipErrorMemoryAllocation', 2) +hipErrorNotInitialized = hipError_t.define('hipErrorNotInitialized', 3) +hipErrorInitializationError = hipError_t.define('hipErrorInitializationError', 3) +hipErrorDeinitialized = hipError_t.define('hipErrorDeinitialized', 4) +hipErrorProfilerDisabled = hipError_t.define('hipErrorProfilerDisabled', 5) +hipErrorProfilerNotInitialized = hipError_t.define('hipErrorProfilerNotInitialized', 6) +hipErrorProfilerAlreadyStarted = hipError_t.define('hipErrorProfilerAlreadyStarted', 7) +hipErrorProfilerAlreadyStopped = hipError_t.define('hipErrorProfilerAlreadyStopped', 8) +hipErrorInvalidConfiguration = hipError_t.define('hipErrorInvalidConfiguration', 9) +hipErrorInvalidPitchValue = hipError_t.define('hipErrorInvalidPitchValue', 12) +hipErrorInvalidSymbol = hipError_t.define('hipErrorInvalidSymbol', 13) +hipErrorInvalidDevicePointer = hipError_t.define('hipErrorInvalidDevicePointer', 17) +hipErrorInvalidMemcpyDirection = hipError_t.define('hipErrorInvalidMemcpyDirection', 21) +hipErrorInsufficientDriver = hipError_t.define('hipErrorInsufficientDriver', 35) +hipErrorMissingConfiguration = hipError_t.define('hipErrorMissingConfiguration', 52) +hipErrorPriorLaunchFailure = hipError_t.define('hipErrorPriorLaunchFailure', 53) +hipErrorInvalidDeviceFunction = hipError_t.define('hipErrorInvalidDeviceFunction', 98) +hipErrorNoDevice = hipError_t.define('hipErrorNoDevice', 100) +hipErrorInvalidDevice = hipError_t.define('hipErrorInvalidDevice', 101) +hipErrorInvalidImage = hipError_t.define('hipErrorInvalidImage', 200) +hipErrorInvalidContext = hipError_t.define('hipErrorInvalidContext', 201) +hipErrorContextAlreadyCurrent = hipError_t.define('hipErrorContextAlreadyCurrent', 202) +hipErrorMapFailed = hipError_t.define('hipErrorMapFailed', 205) +hipErrorMapBufferObjectFailed = hipError_t.define('hipErrorMapBufferObjectFailed', 205) +hipErrorUnmapFailed = hipError_t.define('hipErrorUnmapFailed', 206) +hipErrorArrayIsMapped = hipError_t.define('hipErrorArrayIsMapped', 207) +hipErrorAlreadyMapped = hipError_t.define('hipErrorAlreadyMapped', 208) +hipErrorNoBinaryForGpu = hipError_t.define('hipErrorNoBinaryForGpu', 209) +hipErrorAlreadyAcquired = hipError_t.define('hipErrorAlreadyAcquired', 210) +hipErrorNotMapped = hipError_t.define('hipErrorNotMapped', 211) +hipErrorNotMappedAsArray = hipError_t.define('hipErrorNotMappedAsArray', 212) +hipErrorNotMappedAsPointer = hipError_t.define('hipErrorNotMappedAsPointer', 213) +hipErrorECCNotCorrectable = hipError_t.define('hipErrorECCNotCorrectable', 214) +hipErrorUnsupportedLimit = hipError_t.define('hipErrorUnsupportedLimit', 215) +hipErrorContextAlreadyInUse = hipError_t.define('hipErrorContextAlreadyInUse', 216) +hipErrorPeerAccessUnsupported = hipError_t.define('hipErrorPeerAccessUnsupported', 217) +hipErrorInvalidKernelFile = hipError_t.define('hipErrorInvalidKernelFile', 218) +hipErrorInvalidGraphicsContext = hipError_t.define('hipErrorInvalidGraphicsContext', 219) +hipErrorInvalidSource = hipError_t.define('hipErrorInvalidSource', 300) +hipErrorFileNotFound = hipError_t.define('hipErrorFileNotFound', 301) +hipErrorSharedObjectSymbolNotFound = hipError_t.define('hipErrorSharedObjectSymbolNotFound', 302) +hipErrorSharedObjectInitFailed = hipError_t.define('hipErrorSharedObjectInitFailed', 303) +hipErrorOperatingSystem = hipError_t.define('hipErrorOperatingSystem', 304) +hipErrorInvalidHandle = hipError_t.define('hipErrorInvalidHandle', 400) +hipErrorInvalidResourceHandle = hipError_t.define('hipErrorInvalidResourceHandle', 400) +hipErrorIllegalState = hipError_t.define('hipErrorIllegalState', 401) +hipErrorNotFound = hipError_t.define('hipErrorNotFound', 500) +hipErrorNotReady = hipError_t.define('hipErrorNotReady', 600) +hipErrorIllegalAddress = hipError_t.define('hipErrorIllegalAddress', 700) +hipErrorLaunchOutOfResources = hipError_t.define('hipErrorLaunchOutOfResources', 701) +hipErrorLaunchTimeOut = hipError_t.define('hipErrorLaunchTimeOut', 702) +hipErrorPeerAccessAlreadyEnabled = hipError_t.define('hipErrorPeerAccessAlreadyEnabled', 704) +hipErrorPeerAccessNotEnabled = hipError_t.define('hipErrorPeerAccessNotEnabled', 705) +hipErrorSetOnActiveProcess = hipError_t.define('hipErrorSetOnActiveProcess', 708) +hipErrorContextIsDestroyed = hipError_t.define('hipErrorContextIsDestroyed', 709) +hipErrorAssert = hipError_t.define('hipErrorAssert', 710) +hipErrorHostMemoryAlreadyRegistered = hipError_t.define('hipErrorHostMemoryAlreadyRegistered', 712) +hipErrorHostMemoryNotRegistered = hipError_t.define('hipErrorHostMemoryNotRegistered', 713) +hipErrorLaunchFailure = hipError_t.define('hipErrorLaunchFailure', 719) +hipErrorCooperativeLaunchTooLarge = hipError_t.define('hipErrorCooperativeLaunchTooLarge', 720) +hipErrorNotSupported = hipError_t.define('hipErrorNotSupported', 801) +hipErrorStreamCaptureUnsupported = hipError_t.define('hipErrorStreamCaptureUnsupported', 900) +hipErrorStreamCaptureInvalidated = hipError_t.define('hipErrorStreamCaptureInvalidated', 901) +hipErrorStreamCaptureMerge = hipError_t.define('hipErrorStreamCaptureMerge', 902) +hipErrorStreamCaptureUnmatched = hipError_t.define('hipErrorStreamCaptureUnmatched', 903) +hipErrorStreamCaptureUnjoined = hipError_t.define('hipErrorStreamCaptureUnjoined', 904) +hipErrorStreamCaptureIsolation = hipError_t.define('hipErrorStreamCaptureIsolation', 905) +hipErrorStreamCaptureImplicit = hipError_t.define('hipErrorStreamCaptureImplicit', 906) +hipErrorCapturedEvent = hipError_t.define('hipErrorCapturedEvent', 907) +hipErrorStreamCaptureWrongThread = hipError_t.define('hipErrorStreamCaptureWrongThread', 908) +hipErrorGraphExecUpdateFailure = hipError_t.define('hipErrorGraphExecUpdateFailure', 910) +hipErrorUnknown = hipError_t.define('hipErrorUnknown', 999) +hipErrorRuntimeMemory = hipError_t.define('hipErrorRuntimeMemory', 1052) +hipErrorRuntimeOther = hipError_t.define('hipErrorRuntimeOther', 1053) +hipErrorTbd = hipError_t.define('hipErrorTbd', 1054) + +class ihipModuleSymbol_t(Struct): pass +hipFunction_t = ctypes.POINTER(ihipModuleSymbol_t) uint32_t = ctypes.c_uint32 -try: - hipExtStreamCreateWithCUMask = _libraries['libamdhip64.so'].hipExtStreamCreateWithCUMask - hipExtStreamCreateWithCUMask.restype = hipError_t - hipExtStreamCreateWithCUMask.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t)), uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipExtStreamGetCUMask = _libraries['libamdhip64.so'].hipExtStreamGetCUMask - hipExtStreamGetCUMask.restype = hipError_t - hipExtStreamGetCUMask.argtypes = [hipStream_t, uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -hipStreamCallback_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ihipStream_t), hipError_t, ctypes.POINTER(None)) -try: - hipStreamAddCallback = _libraries['libamdhip64.so'].hipStreamAddCallback - hipStreamAddCallback.restype = hipError_t - hipStreamAddCallback.argtypes = [hipStream_t, hipStreamCallback_t, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamWaitValue32 = _libraries['libamdhip64.so'].hipStreamWaitValue32 - hipStreamWaitValue32.restype = hipError_t - hipStreamWaitValue32.argtypes = [hipStream_t, ctypes.POINTER(None), uint32_t, ctypes.c_uint32, uint32_t] -except AttributeError: - pass +size_t = ctypes.c_uint64 +class ihipStream_t(Struct): pass +hipStream_t = ctypes.POINTER(ihipStream_t) +class ihipEvent_t(Struct): pass +hipEvent_t = ctypes.POINTER(ihipEvent_t) +# __attribute__((visibility("default"))) hipError_t hipExtModuleLaunchKernel(hipFunction_t f, uint32_t globalWorkSizeX, uint32_t globalWorkSizeY, uint32_t globalWorkSizeZ, uint32_t localWorkSizeX, uint32_t localWorkSizeY, uint32_t localWorkSizeZ, size_t sharedMemBytes, hipStream_t hStream, void **kernelParams, void **extra, hipEvent_t startEvent = __null, hipEvent_t stopEvent = __null, uint32_t flags = 0) +try: (hipExtModuleLaunchKernel:=dll.hipExtModuleLaunchKernel).restype, hipExtModuleLaunchKernel.argtypes = hipError_t, [hipFunction_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, size_t, hipStream_t, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p), hipEvent_t, hipEvent_t, uint32_t] +except AttributeError: pass + +# __attribute__((deprecated("use hipExtModuleLaunchKernel instead"))) __attribute__((visibility("default"))) hipError_t hipHccModuleLaunchKernel(hipFunction_t f, uint32_t globalWorkSizeX, uint32_t globalWorkSizeY, uint32_t globalWorkSizeZ, uint32_t localWorkSizeX, uint32_t localWorkSizeY, uint32_t localWorkSizeZ, size_t sharedMemBytes, hipStream_t hStream, void **kernelParams, void **extra, hipEvent_t startEvent = __null, hipEvent_t stopEvent = __null) +try: (hipHccModuleLaunchKernel:=dll.hipHccModuleLaunchKernel).restype, hipHccModuleLaunchKernel.argtypes = hipError_t, [hipFunction_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, size_t, hipStream_t, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p), hipEvent_t, hipEvent_t] +except AttributeError: pass + +class dim3(Struct): pass +dim3._fields_ = [ + ('x', uint32_t), + ('y', uint32_t), + ('z', uint32_t), +] +# hipError_t hipExtLaunchKernel(const void *function_address, dim3 numBlocks, dim3 dimBlocks, void **args, size_t sharedMemBytes, hipStream_t stream, hipEvent_t startEvent, hipEvent_t stopEvent, int flags) +try: (hipExtLaunchKernel:=dll.hipExtLaunchKernel).restype, hipExtLaunchKernel.argtypes = hipError_t, [ctypes.c_void_p, dim3, dim3, ctypes.POINTER(ctypes.c_void_p), size_t, hipStream_t, hipEvent_t, hipEvent_t, ctypes.c_int32] +except AttributeError: pass + +hiprtcResult = CEnum(ctypes.c_uint32) +HIPRTC_SUCCESS = hiprtcResult.define('HIPRTC_SUCCESS', 0) +HIPRTC_ERROR_OUT_OF_MEMORY = hiprtcResult.define('HIPRTC_ERROR_OUT_OF_MEMORY', 1) +HIPRTC_ERROR_PROGRAM_CREATION_FAILURE = hiprtcResult.define('HIPRTC_ERROR_PROGRAM_CREATION_FAILURE', 2) +HIPRTC_ERROR_INVALID_INPUT = hiprtcResult.define('HIPRTC_ERROR_INVALID_INPUT', 3) +HIPRTC_ERROR_INVALID_PROGRAM = hiprtcResult.define('HIPRTC_ERROR_INVALID_PROGRAM', 4) +HIPRTC_ERROR_INVALID_OPTION = hiprtcResult.define('HIPRTC_ERROR_INVALID_OPTION', 5) +HIPRTC_ERROR_COMPILATION = hiprtcResult.define('HIPRTC_ERROR_COMPILATION', 6) +HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE = hiprtcResult.define('HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE', 7) +HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION = hiprtcResult.define('HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', 8) +HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION = hiprtcResult.define('HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', 9) +HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID = hiprtcResult.define('HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID', 10) +HIPRTC_ERROR_INTERNAL_ERROR = hiprtcResult.define('HIPRTC_ERROR_INTERNAL_ERROR', 11) +HIPRTC_ERROR_LINKING = hiprtcResult.define('HIPRTC_ERROR_LINKING', 100) + +hiprtcJIT_option = CEnum(ctypes.c_uint32) +HIPRTC_JIT_MAX_REGISTERS = hiprtcJIT_option.define('HIPRTC_JIT_MAX_REGISTERS', 0) +HIPRTC_JIT_THREADS_PER_BLOCK = hiprtcJIT_option.define('HIPRTC_JIT_THREADS_PER_BLOCK', 1) +HIPRTC_JIT_WALL_TIME = hiprtcJIT_option.define('HIPRTC_JIT_WALL_TIME', 2) +HIPRTC_JIT_INFO_LOG_BUFFER = hiprtcJIT_option.define('HIPRTC_JIT_INFO_LOG_BUFFER', 3) +HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES = hiprtcJIT_option.define('HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES', 4) +HIPRTC_JIT_ERROR_LOG_BUFFER = hiprtcJIT_option.define('HIPRTC_JIT_ERROR_LOG_BUFFER', 5) +HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES = hiprtcJIT_option.define('HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', 6) +HIPRTC_JIT_OPTIMIZATION_LEVEL = hiprtcJIT_option.define('HIPRTC_JIT_OPTIMIZATION_LEVEL', 7) +HIPRTC_JIT_TARGET_FROM_HIPCONTEXT = hiprtcJIT_option.define('HIPRTC_JIT_TARGET_FROM_HIPCONTEXT', 8) +HIPRTC_JIT_TARGET = hiprtcJIT_option.define('HIPRTC_JIT_TARGET', 9) +HIPRTC_JIT_FALLBACK_STRATEGY = hiprtcJIT_option.define('HIPRTC_JIT_FALLBACK_STRATEGY', 10) +HIPRTC_JIT_GENERATE_DEBUG_INFO = hiprtcJIT_option.define('HIPRTC_JIT_GENERATE_DEBUG_INFO', 11) +HIPRTC_JIT_LOG_VERBOSE = hiprtcJIT_option.define('HIPRTC_JIT_LOG_VERBOSE', 12) +HIPRTC_JIT_GENERATE_LINE_INFO = hiprtcJIT_option.define('HIPRTC_JIT_GENERATE_LINE_INFO', 13) +HIPRTC_JIT_CACHE_MODE = hiprtcJIT_option.define('HIPRTC_JIT_CACHE_MODE', 14) +HIPRTC_JIT_NEW_SM3X_OPT = hiprtcJIT_option.define('HIPRTC_JIT_NEW_SM3X_OPT', 15) +HIPRTC_JIT_FAST_COMPILE = hiprtcJIT_option.define('HIPRTC_JIT_FAST_COMPILE', 16) +HIPRTC_JIT_GLOBAL_SYMBOL_NAMES = hiprtcJIT_option.define('HIPRTC_JIT_GLOBAL_SYMBOL_NAMES', 17) +HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS = hiprtcJIT_option.define('HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS', 18) +HIPRTC_JIT_GLOBAL_SYMBOL_COUNT = hiprtcJIT_option.define('HIPRTC_JIT_GLOBAL_SYMBOL_COUNT', 19) +HIPRTC_JIT_LTO = hiprtcJIT_option.define('HIPRTC_JIT_LTO', 20) +HIPRTC_JIT_FTZ = hiprtcJIT_option.define('HIPRTC_JIT_FTZ', 21) +HIPRTC_JIT_PREC_DIV = hiprtcJIT_option.define('HIPRTC_JIT_PREC_DIV', 22) +HIPRTC_JIT_PREC_SQRT = hiprtcJIT_option.define('HIPRTC_JIT_PREC_SQRT', 23) +HIPRTC_JIT_FMA = hiprtcJIT_option.define('HIPRTC_JIT_FMA', 24) +HIPRTC_JIT_NUM_OPTIONS = hiprtcJIT_option.define('HIPRTC_JIT_NUM_OPTIONS', 25) +HIPRTC_JIT_IR_TO_ISA_OPT_EXT = hiprtcJIT_option.define('HIPRTC_JIT_IR_TO_ISA_OPT_EXT', 10000) +HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT = hiprtcJIT_option.define('HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT', 10001) + +hiprtcJITInputType = CEnum(ctypes.c_uint32) +HIPRTC_JIT_INPUT_CUBIN = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_CUBIN', 0) +HIPRTC_JIT_INPUT_PTX = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_PTX', 1) +HIPRTC_JIT_INPUT_FATBINARY = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_FATBINARY', 2) +HIPRTC_JIT_INPUT_OBJECT = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_OBJECT', 3) +HIPRTC_JIT_INPUT_LIBRARY = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_LIBRARY', 4) +HIPRTC_JIT_INPUT_NVVM = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_NVVM', 5) +HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES = hiprtcJITInputType.define('HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES', 6) +HIPRTC_JIT_INPUT_LLVM_BITCODE = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_LLVM_BITCODE', 100) +HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE', 101) +HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE = hiprtcJITInputType.define('HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE', 102) +HIPRTC_JIT_NUM_INPUT_TYPES = hiprtcJITInputType.define('HIPRTC_JIT_NUM_INPUT_TYPES', 9) + +class ihiprtcLinkState(Struct): pass +hiprtcLinkState = ctypes.POINTER(ihiprtcLinkState) +# const char *hiprtcGetErrorString(hiprtcResult result) +try: (hiprtcGetErrorString:=dll.hiprtcGetErrorString).restype, hiprtcGetErrorString.argtypes = ctypes.POINTER(ctypes.c_char), [hiprtcResult] +except AttributeError: pass + +# hiprtcResult hiprtcVersion(int *major, int *minor) +try: (hiprtcVersion:=dll.hiprtcVersion).restype, hiprtcVersion.argtypes = hiprtcResult, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +class _hiprtcProgram(Struct): pass +hiprtcProgram = ctypes.POINTER(_hiprtcProgram) +# hiprtcResult hiprtcAddNameExpression(hiprtcProgram prog, const char *name_expression) +try: (hiprtcAddNameExpression:=dll.hiprtcAddNameExpression).restype, hiprtcAddNameExpression.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hiprtcResult hiprtcCompileProgram(hiprtcProgram prog, int numOptions, const char **options) +try: (hiprtcCompileProgram:=dll.hiprtcCompileProgram).restype, hiprtcCompileProgram.argtypes = hiprtcResult, [hiprtcProgram, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# hiprtcResult hiprtcCreateProgram(hiprtcProgram *prog, const char *src, const char *name, int numHeaders, const char **headers, const char **includeNames) +try: (hiprtcCreateProgram:=dll.hiprtcCreateProgram).restype, hiprtcCreateProgram.argtypes = hiprtcResult, [ctypes.POINTER(hiprtcProgram), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# hiprtcResult hiprtcDestroyProgram(hiprtcProgram *prog) +try: (hiprtcDestroyProgram:=dll.hiprtcDestroyProgram).restype, hiprtcDestroyProgram.argtypes = hiprtcResult, [ctypes.POINTER(hiprtcProgram)] +except AttributeError: pass + +# hiprtcResult hiprtcGetLoweredName(hiprtcProgram prog, const char *name_expression, const char **lowered_name) +try: (hiprtcGetLoweredName:=dll.hiprtcGetLoweredName).restype, hiprtcGetLoweredName.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# hiprtcResult hiprtcGetProgramLog(hiprtcProgram prog, char *log) +try: (hiprtcGetProgramLog:=dll.hiprtcGetProgramLog).restype, hiprtcGetProgramLog.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hiprtcResult hiprtcGetProgramLogSize(hiprtcProgram prog, size_t *logSizeRet) +try: (hiprtcGetProgramLogSize:=dll.hiprtcGetProgramLogSize).restype, hiprtcGetProgramLogSize.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# hiprtcResult hiprtcGetCode(hiprtcProgram prog, char *code) +try: (hiprtcGetCode:=dll.hiprtcGetCode).restype, hiprtcGetCode.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hiprtcResult hiprtcGetCodeSize(hiprtcProgram prog, size_t *codeSizeRet) +try: (hiprtcGetCodeSize:=dll.hiprtcGetCodeSize).restype, hiprtcGetCodeSize.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# hiprtcResult hiprtcGetBitcode(hiprtcProgram prog, char *bitcode) +try: (hiprtcGetBitcode:=dll.hiprtcGetBitcode).restype, hiprtcGetBitcode.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hiprtcResult hiprtcGetBitcodeSize(hiprtcProgram prog, size_t *bitcode_size) +try: (hiprtcGetBitcodeSize:=dll.hiprtcGetBitcodeSize).restype, hiprtcGetBitcodeSize.argtypes = hiprtcResult, [hiprtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# hiprtcResult hiprtcLinkCreate(unsigned int num_options, hiprtcJIT_option *option_ptr, void **option_vals_pptr, hiprtcLinkState *hip_link_state_ptr) +try: (hiprtcLinkCreate:=dll.hiprtcLinkCreate).restype, hiprtcLinkCreate.argtypes = hiprtcResult, [ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(hiprtcLinkState)] +except AttributeError: pass + +# hiprtcResult hiprtcLinkAddFile(hiprtcLinkState hip_link_state, hiprtcJITInputType input_type, const char *file_path, unsigned int num_options, hiprtcJIT_option *options_ptr, void **option_values) +try: (hiprtcLinkAddFile:=dll.hiprtcLinkAddFile).restype, hiprtcLinkAddFile.argtypes = hiprtcResult, [hiprtcLinkState, hiprtcJITInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hiprtcResult hiprtcLinkAddData(hiprtcLinkState hip_link_state, hiprtcJITInputType input_type, void *image, size_t image_size, const char *name, unsigned int num_options, hiprtcJIT_option *options_ptr, void **option_values) +try: (hiprtcLinkAddData:=dll.hiprtcLinkAddData).restype, hiprtcLinkAddData.argtypes = hiprtcResult, [hiprtcLinkState, hiprtcJITInputType, ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hiprtcResult hiprtcLinkComplete(hiprtcLinkState hip_link_state, void **bin_out, size_t *size_out) +try: (hiprtcLinkComplete:=dll.hiprtcLinkComplete).restype, hiprtcLinkComplete.argtypes = hiprtcResult, [hiprtcLinkState, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hiprtcResult hiprtcLinkDestroy(hiprtcLinkState hip_link_state) +try: (hiprtcLinkDestroy:=dll.hiprtcLinkDestroy).restype, hiprtcLinkDestroy.argtypes = hiprtcResult, [hiprtcLinkState] +except AttributeError: pass + +_anonenum0 = CEnum(ctypes.c_uint32) +HIP_SUCCESS = _anonenum0.define('HIP_SUCCESS', 0) +HIP_ERROR_INVALID_VALUE = _anonenum0.define('HIP_ERROR_INVALID_VALUE', 1) +HIP_ERROR_NOT_INITIALIZED = _anonenum0.define('HIP_ERROR_NOT_INITIALIZED', 2) +HIP_ERROR_LAUNCH_OUT_OF_RESOURCES = _anonenum0.define('HIP_ERROR_LAUNCH_OUT_OF_RESOURCES', 3) + +class hipDeviceArch_t(Struct): pass +hipDeviceArch_t._fields_ = [ + ('hasGlobalInt32Atomics', ctypes.c_uint32,1), + ('hasGlobalFloatAtomicExch', ctypes.c_uint32,1), + ('hasSharedInt32Atomics', ctypes.c_uint32,1), + ('hasSharedFloatAtomicExch', ctypes.c_uint32,1), + ('hasFloatAtomicAdd', ctypes.c_uint32,1), + ('hasGlobalInt64Atomics', ctypes.c_uint32,1), + ('hasSharedInt64Atomics', ctypes.c_uint32,1), + ('hasDoubles', ctypes.c_uint32,1), + ('hasWarpVote', ctypes.c_uint32,1), + ('hasWarpBallot', ctypes.c_uint32,1), + ('hasWarpShuffle', ctypes.c_uint32,1), + ('hasFunnelShift', ctypes.c_uint32,1), + ('hasThreadFenceSystem', ctypes.c_uint32,1), + ('hasSyncThreadsExt', ctypes.c_uint32,1), + ('hasSurfaceFuncs', ctypes.c_uint32,1), + ('has3dGrid', ctypes.c_uint32,1), + ('hasDynamicParallelism', ctypes.c_uint32,1), +] +class hipUUID_t(Struct): pass +hipUUID_t._fields_ = [ + ('bytes', (ctypes.c_char * 16)), +] +hipUUID = hipUUID_t +class hipDeviceProp_tR0600(Struct): pass +hipDeviceProp_tR0600._fields_ = [ + ('name', (ctypes.c_char * 256)), + ('uuid', hipUUID), + ('luid', (ctypes.c_char * 8)), + ('luidDeviceNodeMask', ctypes.c_uint32), + ('totalGlobalMem', size_t), + ('sharedMemPerBlock', size_t), + ('regsPerBlock', ctypes.c_int32), + ('warpSize', ctypes.c_int32), + ('memPitch', size_t), + ('maxThreadsPerBlock', ctypes.c_int32), + ('maxThreadsDim', (ctypes.c_int32 * 3)), + ('maxGridSize', (ctypes.c_int32 * 3)), + ('clockRate', ctypes.c_int32), + ('totalConstMem', size_t), + ('major', ctypes.c_int32), + ('minor', ctypes.c_int32), + ('textureAlignment', size_t), + ('texturePitchAlignment', size_t), + ('deviceOverlap', ctypes.c_int32), + ('multiProcessorCount', ctypes.c_int32), + ('kernelExecTimeoutEnabled', ctypes.c_int32), + ('integrated', ctypes.c_int32), + ('canMapHostMemory', ctypes.c_int32), + ('computeMode', ctypes.c_int32), + ('maxTexture1D', ctypes.c_int32), + ('maxTexture1DMipmap', ctypes.c_int32), + ('maxTexture1DLinear', ctypes.c_int32), + ('maxTexture2D', (ctypes.c_int32 * 2)), + ('maxTexture2DMipmap', (ctypes.c_int32 * 2)), + ('maxTexture2DLinear', (ctypes.c_int32 * 3)), + ('maxTexture2DGather', (ctypes.c_int32 * 2)), + ('maxTexture3D', (ctypes.c_int32 * 3)), + ('maxTexture3DAlt', (ctypes.c_int32 * 3)), + ('maxTextureCubemap', ctypes.c_int32), + ('maxTexture1DLayered', (ctypes.c_int32 * 2)), + ('maxTexture2DLayered', (ctypes.c_int32 * 3)), + ('maxTextureCubemapLayered', (ctypes.c_int32 * 2)), + ('maxSurface1D', ctypes.c_int32), + ('maxSurface2D', (ctypes.c_int32 * 2)), + ('maxSurface3D', (ctypes.c_int32 * 3)), + ('maxSurface1DLayered', (ctypes.c_int32 * 2)), + ('maxSurface2DLayered', (ctypes.c_int32 * 3)), + ('maxSurfaceCubemap', ctypes.c_int32), + ('maxSurfaceCubemapLayered', (ctypes.c_int32 * 2)), + ('surfaceAlignment', size_t), + ('concurrentKernels', ctypes.c_int32), + ('ECCEnabled', ctypes.c_int32), + ('pciBusID', ctypes.c_int32), + ('pciDeviceID', ctypes.c_int32), + ('pciDomainID', ctypes.c_int32), + ('tccDriver', ctypes.c_int32), + ('asyncEngineCount', ctypes.c_int32), + ('unifiedAddressing', ctypes.c_int32), + ('memoryClockRate', ctypes.c_int32), + ('memoryBusWidth', ctypes.c_int32), + ('l2CacheSize', ctypes.c_int32), + ('persistingL2CacheMaxSize', ctypes.c_int32), + ('maxThreadsPerMultiProcessor', ctypes.c_int32), + ('streamPrioritiesSupported', ctypes.c_int32), + ('globalL1CacheSupported', ctypes.c_int32), + ('localL1CacheSupported', ctypes.c_int32), + ('sharedMemPerMultiprocessor', size_t), + ('regsPerMultiprocessor', ctypes.c_int32), + ('managedMemory', ctypes.c_int32), + ('isMultiGpuBoard', ctypes.c_int32), + ('multiGpuBoardGroupID', ctypes.c_int32), + ('hostNativeAtomicSupported', ctypes.c_int32), + ('singleToDoublePrecisionPerfRatio', ctypes.c_int32), + ('pageableMemoryAccess', ctypes.c_int32), + ('concurrentManagedAccess', ctypes.c_int32), + ('computePreemptionSupported', ctypes.c_int32), + ('canUseHostPointerForRegisteredMem', ctypes.c_int32), + ('cooperativeLaunch', ctypes.c_int32), + ('cooperativeMultiDeviceLaunch', ctypes.c_int32), + ('sharedMemPerBlockOptin', size_t), + ('pageableMemoryAccessUsesHostPageTables', ctypes.c_int32), + ('directManagedMemAccessFromHost', ctypes.c_int32), + ('maxBlocksPerMultiProcessor', ctypes.c_int32), + ('accessPolicyMaxWindowSize', ctypes.c_int32), + ('reservedSharedMemPerBlock', size_t), + ('hostRegisterSupported', ctypes.c_int32), + ('sparseHipArraySupported', ctypes.c_int32), + ('hostRegisterReadOnlySupported', ctypes.c_int32), + ('timelineSemaphoreInteropSupported', ctypes.c_int32), + ('memoryPoolsSupported', ctypes.c_int32), + ('gpuDirectRDMASupported', ctypes.c_int32), + ('gpuDirectRDMAFlushWritesOptions', ctypes.c_uint32), + ('gpuDirectRDMAWritesOrdering', ctypes.c_int32), + ('memoryPoolSupportedHandleTypes', ctypes.c_uint32), + ('deferredMappingHipArraySupported', ctypes.c_int32), + ('ipcEventSupported', ctypes.c_int32), + ('clusterLaunch', ctypes.c_int32), + ('unifiedFunctionPointers', ctypes.c_int32), + ('reserved', (ctypes.c_int32 * 63)), + ('hipReserved', (ctypes.c_int32 * 32)), + ('gcnArchName', (ctypes.c_char * 256)), + ('maxSharedMemoryPerMultiProcessor', size_t), + ('clockInstructionRate', ctypes.c_int32), + ('arch', hipDeviceArch_t), + ('hdpMemFlushCntl', ctypes.POINTER(ctypes.c_uint32)), + ('hdpRegFlushCntl', ctypes.POINTER(ctypes.c_uint32)), + ('cooperativeMultiDeviceUnmatchedFunc', ctypes.c_int32), + ('cooperativeMultiDeviceUnmatchedGridDim', ctypes.c_int32), + ('cooperativeMultiDeviceUnmatchedBlockDim', ctypes.c_int32), + ('cooperativeMultiDeviceUnmatchedSharedMem', ctypes.c_int32), + ('isLargeBar', ctypes.c_int32), + ('asicRevision', ctypes.c_int32), +] +hipMemoryType = CEnum(ctypes.c_uint32) +hipMemoryTypeUnregistered = hipMemoryType.define('hipMemoryTypeUnregistered', 0) +hipMemoryTypeHost = hipMemoryType.define('hipMemoryTypeHost', 1) +hipMemoryTypeDevice = hipMemoryType.define('hipMemoryTypeDevice', 2) +hipMemoryTypeManaged = hipMemoryType.define('hipMemoryTypeManaged', 3) +hipMemoryTypeArray = hipMemoryType.define('hipMemoryTypeArray', 10) +hipMemoryTypeUnified = hipMemoryType.define('hipMemoryTypeUnified', 11) + +class hipPointerAttribute_t(Struct): pass +hipPointerAttribute_t._fields_ = [ + ('type', hipMemoryType), + ('device', ctypes.c_int32), + ('devicePointer', ctypes.c_void_p), + ('hostPointer', ctypes.c_void_p), + ('isManaged', ctypes.c_int32), + ('allocationFlags', ctypes.c_uint32), +] +hipDeviceAttribute_t = CEnum(ctypes.c_uint32) +hipDeviceAttributeCudaCompatibleBegin = hipDeviceAttribute_t.define('hipDeviceAttributeCudaCompatibleBegin', 0) +hipDeviceAttributeEccEnabled = hipDeviceAttribute_t.define('hipDeviceAttributeEccEnabled', 0) +hipDeviceAttributeAccessPolicyMaxWindowSize = hipDeviceAttribute_t.define('hipDeviceAttributeAccessPolicyMaxWindowSize', 1) +hipDeviceAttributeAsyncEngineCount = hipDeviceAttribute_t.define('hipDeviceAttributeAsyncEngineCount', 2) +hipDeviceAttributeCanMapHostMemory = hipDeviceAttribute_t.define('hipDeviceAttributeCanMapHostMemory', 3) +hipDeviceAttributeCanUseHostPointerForRegisteredMem = hipDeviceAttribute_t.define('hipDeviceAttributeCanUseHostPointerForRegisteredMem', 4) +hipDeviceAttributeClockRate = hipDeviceAttribute_t.define('hipDeviceAttributeClockRate', 5) +hipDeviceAttributeComputeMode = hipDeviceAttribute_t.define('hipDeviceAttributeComputeMode', 6) +hipDeviceAttributeComputePreemptionSupported = hipDeviceAttribute_t.define('hipDeviceAttributeComputePreemptionSupported', 7) +hipDeviceAttributeConcurrentKernels = hipDeviceAttribute_t.define('hipDeviceAttributeConcurrentKernels', 8) +hipDeviceAttributeConcurrentManagedAccess = hipDeviceAttribute_t.define('hipDeviceAttributeConcurrentManagedAccess', 9) +hipDeviceAttributeCooperativeLaunch = hipDeviceAttribute_t.define('hipDeviceAttributeCooperativeLaunch', 10) +hipDeviceAttributeCooperativeMultiDeviceLaunch = hipDeviceAttribute_t.define('hipDeviceAttributeCooperativeMultiDeviceLaunch', 11) +hipDeviceAttributeDeviceOverlap = hipDeviceAttribute_t.define('hipDeviceAttributeDeviceOverlap', 12) +hipDeviceAttributeDirectManagedMemAccessFromHost = hipDeviceAttribute_t.define('hipDeviceAttributeDirectManagedMemAccessFromHost', 13) +hipDeviceAttributeGlobalL1CacheSupported = hipDeviceAttribute_t.define('hipDeviceAttributeGlobalL1CacheSupported', 14) +hipDeviceAttributeHostNativeAtomicSupported = hipDeviceAttribute_t.define('hipDeviceAttributeHostNativeAtomicSupported', 15) +hipDeviceAttributeIntegrated = hipDeviceAttribute_t.define('hipDeviceAttributeIntegrated', 16) +hipDeviceAttributeIsMultiGpuBoard = hipDeviceAttribute_t.define('hipDeviceAttributeIsMultiGpuBoard', 17) +hipDeviceAttributeKernelExecTimeout = hipDeviceAttribute_t.define('hipDeviceAttributeKernelExecTimeout', 18) +hipDeviceAttributeL2CacheSize = hipDeviceAttribute_t.define('hipDeviceAttributeL2CacheSize', 19) +hipDeviceAttributeLocalL1CacheSupported = hipDeviceAttribute_t.define('hipDeviceAttributeLocalL1CacheSupported', 20) +hipDeviceAttributeLuid = hipDeviceAttribute_t.define('hipDeviceAttributeLuid', 21) +hipDeviceAttributeLuidDeviceNodeMask = hipDeviceAttribute_t.define('hipDeviceAttributeLuidDeviceNodeMask', 22) +hipDeviceAttributeComputeCapabilityMajor = hipDeviceAttribute_t.define('hipDeviceAttributeComputeCapabilityMajor', 23) +hipDeviceAttributeManagedMemory = hipDeviceAttribute_t.define('hipDeviceAttributeManagedMemory', 24) +hipDeviceAttributeMaxBlocksPerMultiProcessor = hipDeviceAttribute_t.define('hipDeviceAttributeMaxBlocksPerMultiProcessor', 25) +hipDeviceAttributeMaxBlockDimX = hipDeviceAttribute_t.define('hipDeviceAttributeMaxBlockDimX', 26) +hipDeviceAttributeMaxBlockDimY = hipDeviceAttribute_t.define('hipDeviceAttributeMaxBlockDimY', 27) +hipDeviceAttributeMaxBlockDimZ = hipDeviceAttribute_t.define('hipDeviceAttributeMaxBlockDimZ', 28) +hipDeviceAttributeMaxGridDimX = hipDeviceAttribute_t.define('hipDeviceAttributeMaxGridDimX', 29) +hipDeviceAttributeMaxGridDimY = hipDeviceAttribute_t.define('hipDeviceAttributeMaxGridDimY', 30) +hipDeviceAttributeMaxGridDimZ = hipDeviceAttribute_t.define('hipDeviceAttributeMaxGridDimZ', 31) +hipDeviceAttributeMaxSurface1D = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurface1D', 32) +hipDeviceAttributeMaxSurface1DLayered = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurface1DLayered', 33) +hipDeviceAttributeMaxSurface2D = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurface2D', 34) +hipDeviceAttributeMaxSurface2DLayered = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurface2DLayered', 35) +hipDeviceAttributeMaxSurface3D = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurface3D', 36) +hipDeviceAttributeMaxSurfaceCubemap = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurfaceCubemap', 37) +hipDeviceAttributeMaxSurfaceCubemapLayered = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSurfaceCubemapLayered', 38) +hipDeviceAttributeMaxTexture1DWidth = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture1DWidth', 39) +hipDeviceAttributeMaxTexture1DLayered = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture1DLayered', 40) +hipDeviceAttributeMaxTexture1DLinear = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture1DLinear', 41) +hipDeviceAttributeMaxTexture1DMipmap = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture1DMipmap', 42) +hipDeviceAttributeMaxTexture2DWidth = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture2DWidth', 43) +hipDeviceAttributeMaxTexture2DHeight = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture2DHeight', 44) +hipDeviceAttributeMaxTexture2DGather = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture2DGather', 45) +hipDeviceAttributeMaxTexture2DLayered = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture2DLayered', 46) +hipDeviceAttributeMaxTexture2DLinear = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture2DLinear', 47) +hipDeviceAttributeMaxTexture2DMipmap = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture2DMipmap', 48) +hipDeviceAttributeMaxTexture3DWidth = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture3DWidth', 49) +hipDeviceAttributeMaxTexture3DHeight = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture3DHeight', 50) +hipDeviceAttributeMaxTexture3DDepth = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture3DDepth', 51) +hipDeviceAttributeMaxTexture3DAlt = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTexture3DAlt', 52) +hipDeviceAttributeMaxTextureCubemap = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTextureCubemap', 53) +hipDeviceAttributeMaxTextureCubemapLayered = hipDeviceAttribute_t.define('hipDeviceAttributeMaxTextureCubemapLayered', 54) +hipDeviceAttributeMaxThreadsDim = hipDeviceAttribute_t.define('hipDeviceAttributeMaxThreadsDim', 55) +hipDeviceAttributeMaxThreadsPerBlock = hipDeviceAttribute_t.define('hipDeviceAttributeMaxThreadsPerBlock', 56) +hipDeviceAttributeMaxThreadsPerMultiProcessor = hipDeviceAttribute_t.define('hipDeviceAttributeMaxThreadsPerMultiProcessor', 57) +hipDeviceAttributeMaxPitch = hipDeviceAttribute_t.define('hipDeviceAttributeMaxPitch', 58) +hipDeviceAttributeMemoryBusWidth = hipDeviceAttribute_t.define('hipDeviceAttributeMemoryBusWidth', 59) +hipDeviceAttributeMemoryClockRate = hipDeviceAttribute_t.define('hipDeviceAttributeMemoryClockRate', 60) +hipDeviceAttributeComputeCapabilityMinor = hipDeviceAttribute_t.define('hipDeviceAttributeComputeCapabilityMinor', 61) +hipDeviceAttributeMultiGpuBoardGroupID = hipDeviceAttribute_t.define('hipDeviceAttributeMultiGpuBoardGroupID', 62) +hipDeviceAttributeMultiprocessorCount = hipDeviceAttribute_t.define('hipDeviceAttributeMultiprocessorCount', 63) +hipDeviceAttributeUnused1 = hipDeviceAttribute_t.define('hipDeviceAttributeUnused1', 64) +hipDeviceAttributePageableMemoryAccess = hipDeviceAttribute_t.define('hipDeviceAttributePageableMemoryAccess', 65) +hipDeviceAttributePageableMemoryAccessUsesHostPageTables = hipDeviceAttribute_t.define('hipDeviceAttributePageableMemoryAccessUsesHostPageTables', 66) +hipDeviceAttributePciBusId = hipDeviceAttribute_t.define('hipDeviceAttributePciBusId', 67) +hipDeviceAttributePciDeviceId = hipDeviceAttribute_t.define('hipDeviceAttributePciDeviceId', 68) +hipDeviceAttributePciDomainID = hipDeviceAttribute_t.define('hipDeviceAttributePciDomainID', 69) +hipDeviceAttributePersistingL2CacheMaxSize = hipDeviceAttribute_t.define('hipDeviceAttributePersistingL2CacheMaxSize', 70) +hipDeviceAttributeMaxRegistersPerBlock = hipDeviceAttribute_t.define('hipDeviceAttributeMaxRegistersPerBlock', 71) +hipDeviceAttributeMaxRegistersPerMultiprocessor = hipDeviceAttribute_t.define('hipDeviceAttributeMaxRegistersPerMultiprocessor', 72) +hipDeviceAttributeReservedSharedMemPerBlock = hipDeviceAttribute_t.define('hipDeviceAttributeReservedSharedMemPerBlock', 73) +hipDeviceAttributeMaxSharedMemoryPerBlock = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSharedMemoryPerBlock', 74) +hipDeviceAttributeSharedMemPerBlockOptin = hipDeviceAttribute_t.define('hipDeviceAttributeSharedMemPerBlockOptin', 75) +hipDeviceAttributeSharedMemPerMultiprocessor = hipDeviceAttribute_t.define('hipDeviceAttributeSharedMemPerMultiprocessor', 76) +hipDeviceAttributeSingleToDoublePrecisionPerfRatio = hipDeviceAttribute_t.define('hipDeviceAttributeSingleToDoublePrecisionPerfRatio', 77) +hipDeviceAttributeStreamPrioritiesSupported = hipDeviceAttribute_t.define('hipDeviceAttributeStreamPrioritiesSupported', 78) +hipDeviceAttributeSurfaceAlignment = hipDeviceAttribute_t.define('hipDeviceAttributeSurfaceAlignment', 79) +hipDeviceAttributeTccDriver = hipDeviceAttribute_t.define('hipDeviceAttributeTccDriver', 80) +hipDeviceAttributeTextureAlignment = hipDeviceAttribute_t.define('hipDeviceAttributeTextureAlignment', 81) +hipDeviceAttributeTexturePitchAlignment = hipDeviceAttribute_t.define('hipDeviceAttributeTexturePitchAlignment', 82) +hipDeviceAttributeTotalConstantMemory = hipDeviceAttribute_t.define('hipDeviceAttributeTotalConstantMemory', 83) +hipDeviceAttributeTotalGlobalMem = hipDeviceAttribute_t.define('hipDeviceAttributeTotalGlobalMem', 84) +hipDeviceAttributeUnifiedAddressing = hipDeviceAttribute_t.define('hipDeviceAttributeUnifiedAddressing', 85) +hipDeviceAttributeUnused2 = hipDeviceAttribute_t.define('hipDeviceAttributeUnused2', 86) +hipDeviceAttributeWarpSize = hipDeviceAttribute_t.define('hipDeviceAttributeWarpSize', 87) +hipDeviceAttributeMemoryPoolsSupported = hipDeviceAttribute_t.define('hipDeviceAttributeMemoryPoolsSupported', 88) +hipDeviceAttributeVirtualMemoryManagementSupported = hipDeviceAttribute_t.define('hipDeviceAttributeVirtualMemoryManagementSupported', 89) +hipDeviceAttributeHostRegisterSupported = hipDeviceAttribute_t.define('hipDeviceAttributeHostRegisterSupported', 90) +hipDeviceAttributeMemoryPoolSupportedHandleTypes = hipDeviceAttribute_t.define('hipDeviceAttributeMemoryPoolSupportedHandleTypes', 91) +hipDeviceAttributeCudaCompatibleEnd = hipDeviceAttribute_t.define('hipDeviceAttributeCudaCompatibleEnd', 9999) +hipDeviceAttributeAmdSpecificBegin = hipDeviceAttribute_t.define('hipDeviceAttributeAmdSpecificBegin', 10000) +hipDeviceAttributeClockInstructionRate = hipDeviceAttribute_t.define('hipDeviceAttributeClockInstructionRate', 10000) +hipDeviceAttributeUnused3 = hipDeviceAttribute_t.define('hipDeviceAttributeUnused3', 10001) +hipDeviceAttributeMaxSharedMemoryPerMultiprocessor = hipDeviceAttribute_t.define('hipDeviceAttributeMaxSharedMemoryPerMultiprocessor', 10002) +hipDeviceAttributeUnused4 = hipDeviceAttribute_t.define('hipDeviceAttributeUnused4', 10003) +hipDeviceAttributeUnused5 = hipDeviceAttribute_t.define('hipDeviceAttributeUnused5', 10004) +hipDeviceAttributeHdpMemFlushCntl = hipDeviceAttribute_t.define('hipDeviceAttributeHdpMemFlushCntl', 10005) +hipDeviceAttributeHdpRegFlushCntl = hipDeviceAttribute_t.define('hipDeviceAttributeHdpRegFlushCntl', 10006) +hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc = hipDeviceAttribute_t.define('hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc', 10007) +hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim = hipDeviceAttribute_t.define('hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim', 10008) +hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim = hipDeviceAttribute_t.define('hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim', 10009) +hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem = hipDeviceAttribute_t.define('hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem', 10010) +hipDeviceAttributeIsLargeBar = hipDeviceAttribute_t.define('hipDeviceAttributeIsLargeBar', 10011) +hipDeviceAttributeAsicRevision = hipDeviceAttribute_t.define('hipDeviceAttributeAsicRevision', 10012) +hipDeviceAttributeCanUseStreamWaitValue = hipDeviceAttribute_t.define('hipDeviceAttributeCanUseStreamWaitValue', 10013) +hipDeviceAttributeImageSupport = hipDeviceAttribute_t.define('hipDeviceAttributeImageSupport', 10014) +hipDeviceAttributePhysicalMultiProcessorCount = hipDeviceAttribute_t.define('hipDeviceAttributePhysicalMultiProcessorCount', 10015) +hipDeviceAttributeFineGrainSupport = hipDeviceAttribute_t.define('hipDeviceAttributeFineGrainSupport', 10016) +hipDeviceAttributeWallClockRate = hipDeviceAttribute_t.define('hipDeviceAttributeWallClockRate', 10017) +hipDeviceAttributeAmdSpecificEnd = hipDeviceAttribute_t.define('hipDeviceAttributeAmdSpecificEnd', 19999) +hipDeviceAttributeVendorSpecificBegin = hipDeviceAttribute_t.define('hipDeviceAttributeVendorSpecificBegin', 20000) + +hipDriverProcAddressQueryResult = CEnum(ctypes.c_uint32) +HIP_GET_PROC_ADDRESS_SUCCESS = hipDriverProcAddressQueryResult.define('HIP_GET_PROC_ADDRESS_SUCCESS', 0) +HIP_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND = hipDriverProcAddressQueryResult.define('HIP_GET_PROC_ADDRESS_SYMBOL_NOT_FOUND', 1) +HIP_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT = hipDriverProcAddressQueryResult.define('HIP_GET_PROC_ADDRESS_VERSION_NOT_SUFFICIENT', 2) + +hipComputeMode = CEnum(ctypes.c_uint32) +hipComputeModeDefault = hipComputeMode.define('hipComputeModeDefault', 0) +hipComputeModeExclusive = hipComputeMode.define('hipComputeModeExclusive', 1) +hipComputeModeProhibited = hipComputeMode.define('hipComputeModeProhibited', 2) +hipComputeModeExclusiveProcess = hipComputeMode.define('hipComputeModeExclusiveProcess', 3) + +hipFlushGPUDirectRDMAWritesOptions = CEnum(ctypes.c_uint32) +hipFlushGPUDirectRDMAWritesOptionHost = hipFlushGPUDirectRDMAWritesOptions.define('hipFlushGPUDirectRDMAWritesOptionHost', 1) +hipFlushGPUDirectRDMAWritesOptionMemOps = hipFlushGPUDirectRDMAWritesOptions.define('hipFlushGPUDirectRDMAWritesOptionMemOps', 2) + +hipGPUDirectRDMAWritesOrdering = CEnum(ctypes.c_uint32) +hipGPUDirectRDMAWritesOrderingNone = hipGPUDirectRDMAWritesOrdering.define('hipGPUDirectRDMAWritesOrderingNone', 0) +hipGPUDirectRDMAWritesOrderingOwner = hipGPUDirectRDMAWritesOrdering.define('hipGPUDirectRDMAWritesOrderingOwner', 100) +hipGPUDirectRDMAWritesOrderingAllDevices = hipGPUDirectRDMAWritesOrdering.define('hipGPUDirectRDMAWritesOrderingAllDevices', 200) + +# hipError_t hip_init() +try: (hip_init:=dll.hip_init).restype, hip_init.argtypes = hipError_t, [] +except AttributeError: pass + +class ihipCtx_t(Struct): pass +hipCtx_t = ctypes.POINTER(ihipCtx_t) +hipDevice_t = ctypes.c_int32 +hipDeviceP2PAttr = CEnum(ctypes.c_uint32) +hipDevP2PAttrPerformanceRank = hipDeviceP2PAttr.define('hipDevP2PAttrPerformanceRank', 0) +hipDevP2PAttrAccessSupported = hipDeviceP2PAttr.define('hipDevP2PAttrAccessSupported', 1) +hipDevP2PAttrNativeAtomicSupported = hipDeviceP2PAttr.define('hipDevP2PAttrNativeAtomicSupported', 2) +hipDevP2PAttrHipArrayAccessSupported = hipDeviceP2PAttr.define('hipDevP2PAttrHipArrayAccessSupported', 3) + +class hipIpcMemHandle_st(Struct): pass +hipIpcMemHandle_st._fields_ = [ + ('reserved', (ctypes.c_char * 64)), +] +hipIpcMemHandle_t = hipIpcMemHandle_st +class hipIpcEventHandle_st(Struct): pass +hipIpcEventHandle_st._fields_ = [ + ('reserved', (ctypes.c_char * 64)), +] +hipIpcEventHandle_t = hipIpcEventHandle_st +class ihipModule_t(Struct): pass +hipModule_t = ctypes.POINTER(ihipModule_t) +class ihipMemPoolHandle_t(Struct): pass +hipMemPool_t = ctypes.POINTER(ihipMemPoolHandle_t) +class hipFuncAttributes(Struct): pass +hipFuncAttributes._fields_ = [ + ('binaryVersion', ctypes.c_int32), + ('cacheModeCA', ctypes.c_int32), + ('constSizeBytes', size_t), + ('localSizeBytes', size_t), + ('maxDynamicSharedSizeBytes', ctypes.c_int32), + ('maxThreadsPerBlock', ctypes.c_int32), + ('numRegs', ctypes.c_int32), + ('preferredShmemCarveout', ctypes.c_int32), + ('ptxVersion', ctypes.c_int32), + ('sharedSizeBytes', size_t), +] +hipLimit_t = CEnum(ctypes.c_uint32) +hipLimitStackSize = hipLimit_t.define('hipLimitStackSize', 0) +hipLimitPrintfFifoSize = hipLimit_t.define('hipLimitPrintfFifoSize', 1) +hipLimitMallocHeapSize = hipLimit_t.define('hipLimitMallocHeapSize', 2) +hipLimitRange = hipLimit_t.define('hipLimitRange', 3) + +hipMemoryAdvise = CEnum(ctypes.c_uint32) +hipMemAdviseSetReadMostly = hipMemoryAdvise.define('hipMemAdviseSetReadMostly', 1) +hipMemAdviseUnsetReadMostly = hipMemoryAdvise.define('hipMemAdviseUnsetReadMostly', 2) +hipMemAdviseSetPreferredLocation = hipMemoryAdvise.define('hipMemAdviseSetPreferredLocation', 3) +hipMemAdviseUnsetPreferredLocation = hipMemoryAdvise.define('hipMemAdviseUnsetPreferredLocation', 4) +hipMemAdviseSetAccessedBy = hipMemoryAdvise.define('hipMemAdviseSetAccessedBy', 5) +hipMemAdviseUnsetAccessedBy = hipMemoryAdvise.define('hipMemAdviseUnsetAccessedBy', 6) +hipMemAdviseSetCoarseGrain = hipMemoryAdvise.define('hipMemAdviseSetCoarseGrain', 100) +hipMemAdviseUnsetCoarseGrain = hipMemoryAdvise.define('hipMemAdviseUnsetCoarseGrain', 101) + +hipMemRangeCoherencyMode = CEnum(ctypes.c_uint32) +hipMemRangeCoherencyModeFineGrain = hipMemRangeCoherencyMode.define('hipMemRangeCoherencyModeFineGrain', 0) +hipMemRangeCoherencyModeCoarseGrain = hipMemRangeCoherencyMode.define('hipMemRangeCoherencyModeCoarseGrain', 1) +hipMemRangeCoherencyModeIndeterminate = hipMemRangeCoherencyMode.define('hipMemRangeCoherencyModeIndeterminate', 2) + +hipMemRangeAttribute = CEnum(ctypes.c_uint32) +hipMemRangeAttributeReadMostly = hipMemRangeAttribute.define('hipMemRangeAttributeReadMostly', 1) +hipMemRangeAttributePreferredLocation = hipMemRangeAttribute.define('hipMemRangeAttributePreferredLocation', 2) +hipMemRangeAttributeAccessedBy = hipMemRangeAttribute.define('hipMemRangeAttributeAccessedBy', 3) +hipMemRangeAttributeLastPrefetchLocation = hipMemRangeAttribute.define('hipMemRangeAttributeLastPrefetchLocation', 4) +hipMemRangeAttributeCoherencyMode = hipMemRangeAttribute.define('hipMemRangeAttributeCoherencyMode', 100) + +hipMemPoolAttr = CEnum(ctypes.c_uint32) +hipMemPoolReuseFollowEventDependencies = hipMemPoolAttr.define('hipMemPoolReuseFollowEventDependencies', 1) +hipMemPoolReuseAllowOpportunistic = hipMemPoolAttr.define('hipMemPoolReuseAllowOpportunistic', 2) +hipMemPoolReuseAllowInternalDependencies = hipMemPoolAttr.define('hipMemPoolReuseAllowInternalDependencies', 3) +hipMemPoolAttrReleaseThreshold = hipMemPoolAttr.define('hipMemPoolAttrReleaseThreshold', 4) +hipMemPoolAttrReservedMemCurrent = hipMemPoolAttr.define('hipMemPoolAttrReservedMemCurrent', 5) +hipMemPoolAttrReservedMemHigh = hipMemPoolAttr.define('hipMemPoolAttrReservedMemHigh', 6) +hipMemPoolAttrUsedMemCurrent = hipMemPoolAttr.define('hipMemPoolAttrUsedMemCurrent', 7) +hipMemPoolAttrUsedMemHigh = hipMemPoolAttr.define('hipMemPoolAttrUsedMemHigh', 8) + +hipMemLocationType = CEnum(ctypes.c_uint32) +hipMemLocationTypeInvalid = hipMemLocationType.define('hipMemLocationTypeInvalid', 0) +hipMemLocationTypeDevice = hipMemLocationType.define('hipMemLocationTypeDevice', 1) + +class hipMemLocation(Struct): pass +hipMemLocation._fields_ = [ + ('type', hipMemLocationType), + ('id', ctypes.c_int32), +] +hipMemAccessFlags = CEnum(ctypes.c_uint32) +hipMemAccessFlagsProtNone = hipMemAccessFlags.define('hipMemAccessFlagsProtNone', 0) +hipMemAccessFlagsProtRead = hipMemAccessFlags.define('hipMemAccessFlagsProtRead', 1) +hipMemAccessFlagsProtReadWrite = hipMemAccessFlags.define('hipMemAccessFlagsProtReadWrite', 3) + +class hipMemAccessDesc(Struct): pass +hipMemAccessDesc._fields_ = [ + ('location', hipMemLocation), + ('flags', hipMemAccessFlags), +] +hipMemAllocationType = CEnum(ctypes.c_uint32) +hipMemAllocationTypeInvalid = hipMemAllocationType.define('hipMemAllocationTypeInvalid', 0) +hipMemAllocationTypePinned = hipMemAllocationType.define('hipMemAllocationTypePinned', 1) +hipMemAllocationTypeMax = hipMemAllocationType.define('hipMemAllocationTypeMax', 2147483647) + +hipMemAllocationHandleType = CEnum(ctypes.c_uint32) +hipMemHandleTypeNone = hipMemAllocationHandleType.define('hipMemHandleTypeNone', 0) +hipMemHandleTypePosixFileDescriptor = hipMemAllocationHandleType.define('hipMemHandleTypePosixFileDescriptor', 1) +hipMemHandleTypeWin32 = hipMemAllocationHandleType.define('hipMemHandleTypeWin32', 2) +hipMemHandleTypeWin32Kmt = hipMemAllocationHandleType.define('hipMemHandleTypeWin32Kmt', 4) + +class hipMemPoolProps(Struct): pass +hipMemPoolProps._fields_ = [ + ('allocType', hipMemAllocationType), + ('handleTypes', hipMemAllocationHandleType), + ('location', hipMemLocation), + ('win32SecurityAttributes', ctypes.c_void_p), + ('maxSize', size_t), + ('reserved', (ctypes.c_ubyte * 56)), +] +class hipMemPoolPtrExportData(Struct): pass +hipMemPoolPtrExportData._fields_ = [ + ('reserved', (ctypes.c_ubyte * 64)), +] +hipJitOption = CEnum(ctypes.c_uint32) +hipJitOptionMaxRegisters = hipJitOption.define('hipJitOptionMaxRegisters', 0) +hipJitOptionThreadsPerBlock = hipJitOption.define('hipJitOptionThreadsPerBlock', 1) +hipJitOptionWallTime = hipJitOption.define('hipJitOptionWallTime', 2) +hipJitOptionInfoLogBuffer = hipJitOption.define('hipJitOptionInfoLogBuffer', 3) +hipJitOptionInfoLogBufferSizeBytes = hipJitOption.define('hipJitOptionInfoLogBufferSizeBytes', 4) +hipJitOptionErrorLogBuffer = hipJitOption.define('hipJitOptionErrorLogBuffer', 5) +hipJitOptionErrorLogBufferSizeBytes = hipJitOption.define('hipJitOptionErrorLogBufferSizeBytes', 6) +hipJitOptionOptimizationLevel = hipJitOption.define('hipJitOptionOptimizationLevel', 7) +hipJitOptionTargetFromContext = hipJitOption.define('hipJitOptionTargetFromContext', 8) +hipJitOptionTarget = hipJitOption.define('hipJitOptionTarget', 9) +hipJitOptionFallbackStrategy = hipJitOption.define('hipJitOptionFallbackStrategy', 10) +hipJitOptionGenerateDebugInfo = hipJitOption.define('hipJitOptionGenerateDebugInfo', 11) +hipJitOptionLogVerbose = hipJitOption.define('hipJitOptionLogVerbose', 12) +hipJitOptionGenerateLineInfo = hipJitOption.define('hipJitOptionGenerateLineInfo', 13) +hipJitOptionCacheMode = hipJitOption.define('hipJitOptionCacheMode', 14) +hipJitOptionSm3xOpt = hipJitOption.define('hipJitOptionSm3xOpt', 15) +hipJitOptionFastCompile = hipJitOption.define('hipJitOptionFastCompile', 16) +hipJitOptionNumOptions = hipJitOption.define('hipJitOptionNumOptions', 17) + +hipFuncAttribute = CEnum(ctypes.c_uint32) +hipFuncAttributeMaxDynamicSharedMemorySize = hipFuncAttribute.define('hipFuncAttributeMaxDynamicSharedMemorySize', 8) +hipFuncAttributePreferredSharedMemoryCarveout = hipFuncAttribute.define('hipFuncAttributePreferredSharedMemoryCarveout', 9) +hipFuncAttributeMax = hipFuncAttribute.define('hipFuncAttributeMax', 10) + +hipFuncCache_t = CEnum(ctypes.c_uint32) +hipFuncCachePreferNone = hipFuncCache_t.define('hipFuncCachePreferNone', 0) +hipFuncCachePreferShared = hipFuncCache_t.define('hipFuncCachePreferShared', 1) +hipFuncCachePreferL1 = hipFuncCache_t.define('hipFuncCachePreferL1', 2) +hipFuncCachePreferEqual = hipFuncCache_t.define('hipFuncCachePreferEqual', 3) + +hipSharedMemConfig = CEnum(ctypes.c_uint32) +hipSharedMemBankSizeDefault = hipSharedMemConfig.define('hipSharedMemBankSizeDefault', 0) +hipSharedMemBankSizeFourByte = hipSharedMemConfig.define('hipSharedMemBankSizeFourByte', 1) +hipSharedMemBankSizeEightByte = hipSharedMemConfig.define('hipSharedMemBankSizeEightByte', 2) + +class hipLaunchParams_t(Struct): pass +hipLaunchParams_t._fields_ = [ + ('func', ctypes.c_void_p), + ('gridDim', dim3), + ('blockDim', dim3), + ('args', ctypes.POINTER(ctypes.c_void_p)), + ('sharedMem', size_t), + ('stream', hipStream_t), +] +hipLaunchParams = hipLaunchParams_t +class hipFunctionLaunchParams_t(Struct): pass +hipFunctionLaunchParams_t._fields_ = [ + ('function', hipFunction_t), + ('gridDimX', ctypes.c_uint32), + ('gridDimY', ctypes.c_uint32), + ('gridDimZ', ctypes.c_uint32), + ('blockDimX', ctypes.c_uint32), + ('blockDimY', ctypes.c_uint32), + ('blockDimZ', ctypes.c_uint32), + ('sharedMemBytes', ctypes.c_uint32), + ('hStream', hipStream_t), + ('kernelParams', ctypes.POINTER(ctypes.c_void_p)), +] +hipFunctionLaunchParams = hipFunctionLaunchParams_t +hipExternalMemoryHandleType_enum = CEnum(ctypes.c_uint32) +hipExternalMemoryHandleTypeOpaqueFd = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeOpaqueFd', 1) +hipExternalMemoryHandleTypeOpaqueWin32 = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeOpaqueWin32', 2) +hipExternalMemoryHandleTypeOpaqueWin32Kmt = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeOpaqueWin32Kmt', 3) +hipExternalMemoryHandleTypeD3D12Heap = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeD3D12Heap', 4) +hipExternalMemoryHandleTypeD3D12Resource = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeD3D12Resource', 5) +hipExternalMemoryHandleTypeD3D11Resource = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeD3D11Resource', 6) +hipExternalMemoryHandleTypeD3D11ResourceKmt = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeD3D11ResourceKmt', 7) +hipExternalMemoryHandleTypeNvSciBuf = hipExternalMemoryHandleType_enum.define('hipExternalMemoryHandleTypeNvSciBuf', 8) + +hipExternalMemoryHandleType = hipExternalMemoryHandleType_enum +class hipExternalMemoryHandleDesc_st(Struct): pass +class hipExternalMemoryHandleDesc_st_handle(ctypes.Union): pass +class hipExternalMemoryHandleDesc_st_handle_win32(Struct): pass +hipExternalMemoryHandleDesc_st_handle_win32._fields_ = [ + ('handle', ctypes.c_void_p), + ('name', ctypes.c_void_p), +] +hipExternalMemoryHandleDesc_st_handle._fields_ = [ + ('fd', ctypes.c_int32), + ('win32', hipExternalMemoryHandleDesc_st_handle_win32), + ('nvSciBufObject', ctypes.c_void_p), +] +hipExternalMemoryHandleDesc_st._fields_ = [ + ('type', hipExternalMemoryHandleType), + ('handle', hipExternalMemoryHandleDesc_st_handle), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), +] +hipExternalMemoryHandleDesc = hipExternalMemoryHandleDesc_st +class hipExternalMemoryBufferDesc_st(Struct): pass +hipExternalMemoryBufferDesc_st._fields_ = [ + ('offset', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), +] +hipExternalMemoryBufferDesc = hipExternalMemoryBufferDesc_st +class hipExternalMemoryMipmappedArrayDesc_st(Struct): pass +class hipChannelFormatDesc(Struct): pass +hipChannelFormatKind = CEnum(ctypes.c_uint32) +hipChannelFormatKindSigned = hipChannelFormatKind.define('hipChannelFormatKindSigned', 0) +hipChannelFormatKindUnsigned = hipChannelFormatKind.define('hipChannelFormatKindUnsigned', 1) +hipChannelFormatKindFloat = hipChannelFormatKind.define('hipChannelFormatKindFloat', 2) +hipChannelFormatKindNone = hipChannelFormatKind.define('hipChannelFormatKindNone', 3) + +hipChannelFormatDesc._fields_ = [ + ('x', ctypes.c_int32), + ('y', ctypes.c_int32), + ('z', ctypes.c_int32), + ('w', ctypes.c_int32), + ('f', hipChannelFormatKind), +] +class hipExtent(Struct): pass +hipExtent._fields_ = [ + ('width', size_t), + ('height', size_t), + ('depth', size_t), +] +hipExternalMemoryMipmappedArrayDesc_st._fields_ = [ + ('offset', ctypes.c_uint64), + ('formatDesc', hipChannelFormatDesc), + ('extent', hipExtent), + ('flags', ctypes.c_uint32), + ('numLevels', ctypes.c_uint32), +] +hipExternalMemoryMipmappedArrayDesc = hipExternalMemoryMipmappedArrayDesc_st +hipExternalMemory_t = ctypes.c_void_p +hipExternalSemaphoreHandleType_enum = CEnum(ctypes.c_uint32) +hipExternalSemaphoreHandleTypeOpaqueFd = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeOpaqueFd', 1) +hipExternalSemaphoreHandleTypeOpaqueWin32 = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeOpaqueWin32', 2) +hipExternalSemaphoreHandleTypeOpaqueWin32Kmt = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeOpaqueWin32Kmt', 3) +hipExternalSemaphoreHandleTypeD3D12Fence = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeD3D12Fence', 4) +hipExternalSemaphoreHandleTypeD3D11Fence = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeD3D11Fence', 5) +hipExternalSemaphoreHandleTypeNvSciSync = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeNvSciSync', 6) +hipExternalSemaphoreHandleTypeKeyedMutex = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeKeyedMutex', 7) +hipExternalSemaphoreHandleTypeKeyedMutexKmt = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeKeyedMutexKmt', 8) +hipExternalSemaphoreHandleTypeTimelineSemaphoreFd = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeTimelineSemaphoreFd', 9) +hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32 = hipExternalSemaphoreHandleType_enum.define('hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32', 10) + +hipExternalSemaphoreHandleType = hipExternalSemaphoreHandleType_enum +class hipExternalSemaphoreHandleDesc_st(Struct): pass +class hipExternalSemaphoreHandleDesc_st_handle(ctypes.Union): pass +class hipExternalSemaphoreHandleDesc_st_handle_win32(Struct): pass +hipExternalSemaphoreHandleDesc_st_handle_win32._fields_ = [ + ('handle', ctypes.c_void_p), + ('name', ctypes.c_void_p), +] +hipExternalSemaphoreHandleDesc_st_handle._fields_ = [ + ('fd', ctypes.c_int32), + ('win32', hipExternalSemaphoreHandleDesc_st_handle_win32), + ('NvSciSyncObj', ctypes.c_void_p), +] +hipExternalSemaphoreHandleDesc_st._fields_ = [ + ('type', hipExternalSemaphoreHandleType), + ('handle', hipExternalSemaphoreHandleDesc_st_handle), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), +] +hipExternalSemaphoreHandleDesc = hipExternalSemaphoreHandleDesc_st +hipExternalSemaphore_t = ctypes.c_void_p +class hipExternalSemaphoreSignalParams_st(Struct): pass +class hipExternalSemaphoreSignalParams_st_params(Struct): pass +class hipExternalSemaphoreSignalParams_st_params_fence(Struct): pass +hipExternalSemaphoreSignalParams_st_params_fence._fields_ = [ + ('value', ctypes.c_uint64), +] +class hipExternalSemaphoreSignalParams_st_params_nvSciSync(ctypes.Union): pass +hipExternalSemaphoreSignalParams_st_params_nvSciSync._fields_ = [ + ('fence', ctypes.c_void_p), + ('reserved', ctypes.c_uint64), +] +class hipExternalSemaphoreSignalParams_st_params_keyedMutex(Struct): pass +hipExternalSemaphoreSignalParams_st_params_keyedMutex._fields_ = [ + ('key', ctypes.c_uint64), +] +hipExternalSemaphoreSignalParams_st_params._fields_ = [ + ('fence', hipExternalSemaphoreSignalParams_st_params_fence), + ('nvSciSync', hipExternalSemaphoreSignalParams_st_params_nvSciSync), + ('keyedMutex', hipExternalSemaphoreSignalParams_st_params_keyedMutex), + ('reserved', (ctypes.c_uint32 * 12)), +] +hipExternalSemaphoreSignalParams_st._fields_ = [ + ('params', hipExternalSemaphoreSignalParams_st_params), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), +] +hipExternalSemaphoreSignalParams = hipExternalSemaphoreSignalParams_st +class hipExternalSemaphoreWaitParams_st(Struct): pass +class hipExternalSemaphoreWaitParams_st_params(Struct): pass +class hipExternalSemaphoreWaitParams_st_params_fence(Struct): pass +hipExternalSemaphoreWaitParams_st_params_fence._fields_ = [ + ('value', ctypes.c_uint64), +] +class hipExternalSemaphoreWaitParams_st_params_nvSciSync(ctypes.Union): pass +hipExternalSemaphoreWaitParams_st_params_nvSciSync._fields_ = [ + ('fence', ctypes.c_void_p), + ('reserved', ctypes.c_uint64), +] +class hipExternalSemaphoreWaitParams_st_params_keyedMutex(Struct): pass +hipExternalSemaphoreWaitParams_st_params_keyedMutex._fields_ = [ + ('key', ctypes.c_uint64), + ('timeoutMs', ctypes.c_uint32), +] +hipExternalSemaphoreWaitParams_st_params._fields_ = [ + ('fence', hipExternalSemaphoreWaitParams_st_params_fence), + ('nvSciSync', hipExternalSemaphoreWaitParams_st_params_nvSciSync), + ('keyedMutex', hipExternalSemaphoreWaitParams_st_params_keyedMutex), + ('reserved', (ctypes.c_uint32 * 10)), +] +hipExternalSemaphoreWaitParams_st._fields_ = [ + ('params', hipExternalSemaphoreWaitParams_st_params), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), +] +hipExternalSemaphoreWaitParams = hipExternalSemaphoreWaitParams_st +# void __hipGetPCH(const char **pch, unsigned int *size) +try: (__hipGetPCH:=dll.__hipGetPCH).restype, __hipGetPCH.argtypes = None, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +hipGraphicsRegisterFlags = CEnum(ctypes.c_uint32) +hipGraphicsRegisterFlagsNone = hipGraphicsRegisterFlags.define('hipGraphicsRegisterFlagsNone', 0) +hipGraphicsRegisterFlagsReadOnly = hipGraphicsRegisterFlags.define('hipGraphicsRegisterFlagsReadOnly', 1) +hipGraphicsRegisterFlagsWriteDiscard = hipGraphicsRegisterFlags.define('hipGraphicsRegisterFlagsWriteDiscard', 2) +hipGraphicsRegisterFlagsSurfaceLoadStore = hipGraphicsRegisterFlags.define('hipGraphicsRegisterFlagsSurfaceLoadStore', 4) +hipGraphicsRegisterFlagsTextureGather = hipGraphicsRegisterFlags.define('hipGraphicsRegisterFlagsTextureGather', 8) + +class _hipGraphicsResource(Struct): pass +hipGraphicsResource = _hipGraphicsResource +hipGraphicsResource_t = ctypes.POINTER(_hipGraphicsResource) +class ihipGraph(Struct): pass +hipGraph_t = ctypes.POINTER(ihipGraph) +class hipGraphNode(Struct): pass +hipGraphNode_t = ctypes.POINTER(hipGraphNode) +class hipGraphExec(Struct): pass +hipGraphExec_t = ctypes.POINTER(hipGraphExec) +class hipUserObject(Struct): pass +hipUserObject_t = ctypes.POINTER(hipUserObject) +hipGraphNodeType = CEnum(ctypes.c_uint32) +hipGraphNodeTypeKernel = hipGraphNodeType.define('hipGraphNodeTypeKernel', 0) +hipGraphNodeTypeMemcpy = hipGraphNodeType.define('hipGraphNodeTypeMemcpy', 1) +hipGraphNodeTypeMemset = hipGraphNodeType.define('hipGraphNodeTypeMemset', 2) +hipGraphNodeTypeHost = hipGraphNodeType.define('hipGraphNodeTypeHost', 3) +hipGraphNodeTypeGraph = hipGraphNodeType.define('hipGraphNodeTypeGraph', 4) +hipGraphNodeTypeEmpty = hipGraphNodeType.define('hipGraphNodeTypeEmpty', 5) +hipGraphNodeTypeWaitEvent = hipGraphNodeType.define('hipGraphNodeTypeWaitEvent', 6) +hipGraphNodeTypeEventRecord = hipGraphNodeType.define('hipGraphNodeTypeEventRecord', 7) +hipGraphNodeTypeExtSemaphoreSignal = hipGraphNodeType.define('hipGraphNodeTypeExtSemaphoreSignal', 8) +hipGraphNodeTypeExtSemaphoreWait = hipGraphNodeType.define('hipGraphNodeTypeExtSemaphoreWait', 9) +hipGraphNodeTypeMemAlloc = hipGraphNodeType.define('hipGraphNodeTypeMemAlloc', 10) +hipGraphNodeTypeMemFree = hipGraphNodeType.define('hipGraphNodeTypeMemFree', 11) +hipGraphNodeTypeMemcpyFromSymbol = hipGraphNodeType.define('hipGraphNodeTypeMemcpyFromSymbol', 12) +hipGraphNodeTypeMemcpyToSymbol = hipGraphNodeType.define('hipGraphNodeTypeMemcpyToSymbol', 13) +hipGraphNodeTypeCount = hipGraphNodeType.define('hipGraphNodeTypeCount', 14) + +hipHostFn_t = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +class hipHostNodeParams(Struct): pass +hipHostNodeParams._fields_ = [ + ('fn', hipHostFn_t), + ('userData', ctypes.c_void_p), +] +class hipKernelNodeParams(Struct): pass +hipKernelNodeParams._fields_ = [ + ('blockDim', dim3), + ('extra', ctypes.POINTER(ctypes.c_void_p)), + ('func', ctypes.c_void_p), + ('gridDim', dim3), + ('kernelParams', ctypes.POINTER(ctypes.c_void_p)), + ('sharedMemBytes', ctypes.c_uint32), +] +class hipMemsetParams(Struct): pass +hipMemsetParams._fields_ = [ + ('dst', ctypes.c_void_p), + ('elementSize', ctypes.c_uint32), + ('height', size_t), + ('pitch', size_t), + ('value', ctypes.c_uint32), + ('width', size_t), +] +class hipMemAllocNodeParams(Struct): pass +hipMemAllocNodeParams._fields_ = [ + ('poolProps', hipMemPoolProps), + ('accessDescs', ctypes.POINTER(hipMemAccessDesc)), + ('accessDescCount', size_t), + ('bytesize', size_t), + ('dptr', ctypes.c_void_p), +] +hipAccessProperty = CEnum(ctypes.c_uint32) +hipAccessPropertyNormal = hipAccessProperty.define('hipAccessPropertyNormal', 0) +hipAccessPropertyStreaming = hipAccessProperty.define('hipAccessPropertyStreaming', 1) +hipAccessPropertyPersisting = hipAccessProperty.define('hipAccessPropertyPersisting', 2) + +class hipAccessPolicyWindow(Struct): pass +hipAccessPolicyWindow._fields_ = [ + ('base_ptr', ctypes.c_void_p), + ('hitProp', hipAccessProperty), + ('hitRatio', ctypes.c_float), + ('missProp', hipAccessProperty), + ('num_bytes', size_t), +] +hipLaunchAttributeID = CEnum(ctypes.c_uint32) +hipLaunchAttributeAccessPolicyWindow = hipLaunchAttributeID.define('hipLaunchAttributeAccessPolicyWindow', 1) +hipLaunchAttributeCooperative = hipLaunchAttributeID.define('hipLaunchAttributeCooperative', 2) +hipLaunchAttributePriority = hipLaunchAttributeID.define('hipLaunchAttributePriority', 8) + +class hipLaunchAttributeValue(ctypes.Union): pass +hipLaunchAttributeValue._fields_ = [ + ('accessPolicyWindow', hipAccessPolicyWindow), + ('cooperative', ctypes.c_int32), + ('priority', ctypes.c_int32), +] +class HIP_MEMSET_NODE_PARAMS(Struct): pass +hipDeviceptr_t = ctypes.c_void_p +HIP_MEMSET_NODE_PARAMS._fields_ = [ + ('dst', hipDeviceptr_t), + ('pitch', size_t), + ('value', ctypes.c_uint32), + ('elementSize', ctypes.c_uint32), + ('width', size_t), + ('height', size_t), +] +hipGraphExecUpdateResult = CEnum(ctypes.c_uint32) +hipGraphExecUpdateSuccess = hipGraphExecUpdateResult.define('hipGraphExecUpdateSuccess', 0) +hipGraphExecUpdateError = hipGraphExecUpdateResult.define('hipGraphExecUpdateError', 1) +hipGraphExecUpdateErrorTopologyChanged = hipGraphExecUpdateResult.define('hipGraphExecUpdateErrorTopologyChanged', 2) +hipGraphExecUpdateErrorNodeTypeChanged = hipGraphExecUpdateResult.define('hipGraphExecUpdateErrorNodeTypeChanged', 3) +hipGraphExecUpdateErrorFunctionChanged = hipGraphExecUpdateResult.define('hipGraphExecUpdateErrorFunctionChanged', 4) +hipGraphExecUpdateErrorParametersChanged = hipGraphExecUpdateResult.define('hipGraphExecUpdateErrorParametersChanged', 5) +hipGraphExecUpdateErrorNotSupported = hipGraphExecUpdateResult.define('hipGraphExecUpdateErrorNotSupported', 6) +hipGraphExecUpdateErrorUnsupportedFunctionChange = hipGraphExecUpdateResult.define('hipGraphExecUpdateErrorUnsupportedFunctionChange', 7) + +hipStreamCaptureMode = CEnum(ctypes.c_uint32) +hipStreamCaptureModeGlobal = hipStreamCaptureMode.define('hipStreamCaptureModeGlobal', 0) +hipStreamCaptureModeThreadLocal = hipStreamCaptureMode.define('hipStreamCaptureModeThreadLocal', 1) +hipStreamCaptureModeRelaxed = hipStreamCaptureMode.define('hipStreamCaptureModeRelaxed', 2) + +hipStreamCaptureStatus = CEnum(ctypes.c_uint32) +hipStreamCaptureStatusNone = hipStreamCaptureStatus.define('hipStreamCaptureStatusNone', 0) +hipStreamCaptureStatusActive = hipStreamCaptureStatus.define('hipStreamCaptureStatusActive', 1) +hipStreamCaptureStatusInvalidated = hipStreamCaptureStatus.define('hipStreamCaptureStatusInvalidated', 2) + +hipStreamUpdateCaptureDependenciesFlags = CEnum(ctypes.c_uint32) +hipStreamAddCaptureDependencies = hipStreamUpdateCaptureDependenciesFlags.define('hipStreamAddCaptureDependencies', 0) +hipStreamSetCaptureDependencies = hipStreamUpdateCaptureDependenciesFlags.define('hipStreamSetCaptureDependencies', 1) + +hipGraphMemAttributeType = CEnum(ctypes.c_uint32) +hipGraphMemAttrUsedMemCurrent = hipGraphMemAttributeType.define('hipGraphMemAttrUsedMemCurrent', 0) +hipGraphMemAttrUsedMemHigh = hipGraphMemAttributeType.define('hipGraphMemAttrUsedMemHigh', 1) +hipGraphMemAttrReservedMemCurrent = hipGraphMemAttributeType.define('hipGraphMemAttrReservedMemCurrent', 2) +hipGraphMemAttrReservedMemHigh = hipGraphMemAttributeType.define('hipGraphMemAttrReservedMemHigh', 3) + +hipUserObjectFlags = CEnum(ctypes.c_uint32) +hipUserObjectNoDestructorSync = hipUserObjectFlags.define('hipUserObjectNoDestructorSync', 1) + +hipUserObjectRetainFlags = CEnum(ctypes.c_uint32) +hipGraphUserObjectMove = hipUserObjectRetainFlags.define('hipGraphUserObjectMove', 1) + +hipGraphInstantiateFlags = CEnum(ctypes.c_uint32) +hipGraphInstantiateFlagAutoFreeOnLaunch = hipGraphInstantiateFlags.define('hipGraphInstantiateFlagAutoFreeOnLaunch', 1) +hipGraphInstantiateFlagUpload = hipGraphInstantiateFlags.define('hipGraphInstantiateFlagUpload', 2) +hipGraphInstantiateFlagDeviceLaunch = hipGraphInstantiateFlags.define('hipGraphInstantiateFlagDeviceLaunch', 4) +hipGraphInstantiateFlagUseNodePriority = hipGraphInstantiateFlags.define('hipGraphInstantiateFlagUseNodePriority', 8) + +hipGraphDebugDotFlags = CEnum(ctypes.c_uint32) +hipGraphDebugDotFlagsVerbose = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsVerbose', 1) +hipGraphDebugDotFlagsKernelNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsKernelNodeParams', 4) +hipGraphDebugDotFlagsMemcpyNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsMemcpyNodeParams', 8) +hipGraphDebugDotFlagsMemsetNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsMemsetNodeParams', 16) +hipGraphDebugDotFlagsHostNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsHostNodeParams', 32) +hipGraphDebugDotFlagsEventNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsEventNodeParams', 64) +hipGraphDebugDotFlagsExtSemasSignalNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsExtSemasSignalNodeParams', 128) +hipGraphDebugDotFlagsExtSemasWaitNodeParams = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsExtSemasWaitNodeParams', 256) +hipGraphDebugDotFlagsKernelNodeAttributes = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsKernelNodeAttributes', 512) +hipGraphDebugDotFlagsHandles = hipGraphDebugDotFlags.define('hipGraphDebugDotFlagsHandles', 1024) + +hipGraphInstantiateResult = CEnum(ctypes.c_uint32) +hipGraphInstantiateSuccess = hipGraphInstantiateResult.define('hipGraphInstantiateSuccess', 0) +hipGraphInstantiateError = hipGraphInstantiateResult.define('hipGraphInstantiateError', 1) +hipGraphInstantiateInvalidStructure = hipGraphInstantiateResult.define('hipGraphInstantiateInvalidStructure', 2) +hipGraphInstantiateNodeOperationNotSupported = hipGraphInstantiateResult.define('hipGraphInstantiateNodeOperationNotSupported', 3) +hipGraphInstantiateMultipleDevicesNotSupported = hipGraphInstantiateResult.define('hipGraphInstantiateMultipleDevicesNotSupported', 4) + +class hipGraphInstantiateParams(Struct): pass +hipGraphInstantiateParams._fields_ = [ + ('errNode_out', hipGraphNode_t), + ('flags', ctypes.c_uint64), + ('result_out', hipGraphInstantiateResult), + ('uploadStream', hipStream_t), +] +class hipMemAllocationProp(Struct): pass +class hipMemAllocationProp_allocFlags(Struct): pass +hipMemAllocationProp_allocFlags._fields_ = [ + ('compressionType', ctypes.c_ubyte), + ('gpuDirectRDMACapable', ctypes.c_ubyte), + ('usage', ctypes.c_uint16), +] +hipMemAllocationProp._fields_ = [ + ('type', hipMemAllocationType), + ('requestedHandleType', hipMemAllocationHandleType), + ('location', hipMemLocation), + ('win32HandleMetaData', ctypes.c_void_p), + ('allocFlags', hipMemAllocationProp_allocFlags), +] +class hipExternalSemaphoreSignalNodeParams(Struct): pass +hipExternalSemaphoreSignalNodeParams._fields_ = [ + ('extSemArray', ctypes.POINTER(hipExternalSemaphore_t)), + ('paramsArray', ctypes.POINTER(hipExternalSemaphoreSignalParams)), + ('numExtSems', ctypes.c_uint32), +] +class hipExternalSemaphoreWaitNodeParams(Struct): pass +hipExternalSemaphoreWaitNodeParams._fields_ = [ + ('extSemArray', ctypes.POINTER(hipExternalSemaphore_t)), + ('paramsArray', ctypes.POINTER(hipExternalSemaphoreWaitParams)), + ('numExtSems', ctypes.c_uint32), +] +class ihipMemGenericAllocationHandle(Struct): pass +hipMemGenericAllocationHandle_t = ctypes.POINTER(ihipMemGenericAllocationHandle) +hipMemAllocationGranularity_flags = CEnum(ctypes.c_uint32) +hipMemAllocationGranularityMinimum = hipMemAllocationGranularity_flags.define('hipMemAllocationGranularityMinimum', 0) +hipMemAllocationGranularityRecommended = hipMemAllocationGranularity_flags.define('hipMemAllocationGranularityRecommended', 1) + +hipMemHandleType = CEnum(ctypes.c_uint32) +hipMemHandleTypeGeneric = hipMemHandleType.define('hipMemHandleTypeGeneric', 0) + +hipMemOperationType = CEnum(ctypes.c_uint32) +hipMemOperationTypeMap = hipMemOperationType.define('hipMemOperationTypeMap', 1) +hipMemOperationTypeUnmap = hipMemOperationType.define('hipMemOperationTypeUnmap', 2) + +hipArraySparseSubresourceType = CEnum(ctypes.c_uint32) +hipArraySparseSubresourceTypeSparseLevel = hipArraySparseSubresourceType.define('hipArraySparseSubresourceTypeSparseLevel', 0) +hipArraySparseSubresourceTypeMiptail = hipArraySparseSubresourceType.define('hipArraySparseSubresourceTypeMiptail', 1) + +class hipArrayMapInfo(Struct): pass +hipResourceType = CEnum(ctypes.c_uint32) +hipResourceTypeArray = hipResourceType.define('hipResourceTypeArray', 0) +hipResourceTypeMipmappedArray = hipResourceType.define('hipResourceTypeMipmappedArray', 1) +hipResourceTypeLinear = hipResourceType.define('hipResourceTypeLinear', 2) +hipResourceTypePitch2D = hipResourceType.define('hipResourceTypePitch2D', 3) + +class hipArrayMapInfo_resource(ctypes.Union): pass +class hipMipmappedArray(Struct): pass +hipArray_Format = CEnum(ctypes.c_uint32) +HIP_AD_FORMAT_UNSIGNED_INT8 = hipArray_Format.define('HIP_AD_FORMAT_UNSIGNED_INT8', 1) +HIP_AD_FORMAT_UNSIGNED_INT16 = hipArray_Format.define('HIP_AD_FORMAT_UNSIGNED_INT16', 2) +HIP_AD_FORMAT_UNSIGNED_INT32 = hipArray_Format.define('HIP_AD_FORMAT_UNSIGNED_INT32', 3) +HIP_AD_FORMAT_SIGNED_INT8 = hipArray_Format.define('HIP_AD_FORMAT_SIGNED_INT8', 8) +HIP_AD_FORMAT_SIGNED_INT16 = hipArray_Format.define('HIP_AD_FORMAT_SIGNED_INT16', 9) +HIP_AD_FORMAT_SIGNED_INT32 = hipArray_Format.define('HIP_AD_FORMAT_SIGNED_INT32', 10) +HIP_AD_FORMAT_HALF = hipArray_Format.define('HIP_AD_FORMAT_HALF', 16) +HIP_AD_FORMAT_FLOAT = hipArray_Format.define('HIP_AD_FORMAT_FLOAT', 32) + +hipMipmappedArray._fields_ = [ + ('data', ctypes.c_void_p), + ('desc', hipChannelFormatDesc), + ('type', ctypes.c_uint32), + ('width', ctypes.c_uint32), + ('height', ctypes.c_uint32), + ('depth', ctypes.c_uint32), + ('min_mipmap_level', ctypes.c_uint32), + ('max_mipmap_level', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('format', hipArray_Format), + ('num_channels', ctypes.c_uint32), +] +class hipArray(Struct): pass +hipArray_t = ctypes.POINTER(hipArray) +hipArrayMapInfo_resource._fields_ = [ + ('mipmap', hipMipmappedArray), + ('array', hipArray_t), +] +class hipArrayMapInfo_subresource(ctypes.Union): pass +class hipArrayMapInfo_subresource_sparseLevel(Struct): pass +hipArrayMapInfo_subresource_sparseLevel._fields_ = [ + ('level', ctypes.c_uint32), + ('layer', ctypes.c_uint32), + ('offsetX', ctypes.c_uint32), + ('offsetY', ctypes.c_uint32), + ('offsetZ', ctypes.c_uint32), + ('extentWidth', ctypes.c_uint32), + ('extentHeight', ctypes.c_uint32), + ('extentDepth', ctypes.c_uint32), +] +class hipArrayMapInfo_subresource_miptail(Struct): pass +hipArrayMapInfo_subresource_miptail._fields_ = [ + ('layer', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('size', ctypes.c_uint64), +] +hipArrayMapInfo_subresource._fields_ = [ + ('sparseLevel', hipArrayMapInfo_subresource_sparseLevel), + ('miptail', hipArrayMapInfo_subresource_miptail), +] +class hipArrayMapInfo_memHandle(ctypes.Union): pass +hipArrayMapInfo_memHandle._fields_ = [ + ('memHandle', hipMemGenericAllocationHandle_t), +] +hipArrayMapInfo._fields_ = [ + ('resourceType', hipResourceType), + ('resource', hipArrayMapInfo_resource), + ('subresourceType', hipArraySparseSubresourceType), + ('subresource', hipArrayMapInfo_subresource), + ('memOperationType', hipMemOperationType), + ('memHandleType', hipMemHandleType), + ('memHandle', hipArrayMapInfo_memHandle), + ('offset', ctypes.c_uint64), + ('deviceBitMask', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 2)), +] +class hipMemcpyNodeParams(Struct): pass +class hipMemcpy3DParms(Struct): pass +class hipPos(Struct): pass +hipPos._fields_ = [ + ('x', size_t), + ('y', size_t), + ('z', size_t), +] +class hipPitchedPtr(Struct): pass +hipPitchedPtr._fields_ = [ + ('ptr', ctypes.c_void_p), + ('pitch', size_t), + ('xsize', size_t), + ('ysize', size_t), +] +hipMemcpyKind = CEnum(ctypes.c_uint32) +hipMemcpyHostToHost = hipMemcpyKind.define('hipMemcpyHostToHost', 0) +hipMemcpyHostToDevice = hipMemcpyKind.define('hipMemcpyHostToDevice', 1) +hipMemcpyDeviceToHost = hipMemcpyKind.define('hipMemcpyDeviceToHost', 2) +hipMemcpyDeviceToDevice = hipMemcpyKind.define('hipMemcpyDeviceToDevice', 3) +hipMemcpyDefault = hipMemcpyKind.define('hipMemcpyDefault', 4) +hipMemcpyDeviceToDeviceNoCU = hipMemcpyKind.define('hipMemcpyDeviceToDeviceNoCU', 1024) + +hipMemcpy3DParms._fields_ = [ + ('srcArray', hipArray_t), + ('srcPos', hipPos), + ('srcPtr', hipPitchedPtr), + ('dstArray', hipArray_t), + ('dstPos', hipPos), + ('dstPtr', hipPitchedPtr), + ('extent', hipExtent), + ('kind', hipMemcpyKind), +] +hipMemcpyNodeParams._fields_ = [ + ('flags', ctypes.c_int32), + ('reserved', (ctypes.c_int32 * 3)), + ('copyParams', hipMemcpy3DParms), +] +class hipChildGraphNodeParams(Struct): pass +hipChildGraphNodeParams._fields_ = [ + ('graph', hipGraph_t), +] +class hipEventWaitNodeParams(Struct): pass +hipEventWaitNodeParams._fields_ = [ + ('event', hipEvent_t), +] +class hipEventRecordNodeParams(Struct): pass +hipEventRecordNodeParams._fields_ = [ + ('event', hipEvent_t), +] +class hipMemFreeNodeParams(Struct): pass +hipMemFreeNodeParams._fields_ = [ + ('dptr', ctypes.c_void_p), +] +class hipGraphNodeParams(Struct): pass +class hipGraphNodeParams_0(ctypes.Union): pass +hipGraphNodeParams_0._fields_ = [ + ('reserved1', (ctypes.c_int64 * 29)), + ('kernel', hipKernelNodeParams), + ('memcpy', hipMemcpyNodeParams), + ('memset', hipMemsetParams), + ('host', hipHostNodeParams), + ('graph', hipChildGraphNodeParams), + ('eventWait', hipEventWaitNodeParams), + ('eventRecord', hipEventRecordNodeParams), + ('extSemSignal', hipExternalSemaphoreSignalNodeParams), + ('extSemWait', hipExternalSemaphoreWaitNodeParams), + ('alloc', hipMemAllocNodeParams), + ('free', hipMemFreeNodeParams), +] +hipGraphNodeParams._anonymous_ = ['_0'] +hipGraphNodeParams._fields_ = [ + ('type', hipGraphNodeType), + ('reserved0', (ctypes.c_int32 * 3)), + ('_0', hipGraphNodeParams_0), + ('reserved2', ctypes.c_int64), +] +hipGraphDependencyType = CEnum(ctypes.c_uint32) +hipGraphDependencyTypeDefault = hipGraphDependencyType.define('hipGraphDependencyTypeDefault', 0) +hipGraphDependencyTypeProgrammatic = hipGraphDependencyType.define('hipGraphDependencyTypeProgrammatic', 1) + +class hipGraphEdgeData(Struct): pass +hipGraphEdgeData._fields_ = [ + ('from_port', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 5)), + ('to_port', ctypes.c_ubyte), + ('type', ctypes.c_ubyte), +] +# hipError_t hipInit(unsigned int flags) +try: (hipInit:=dll.hipInit).restype, hipInit.argtypes = hipError_t, [ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipDriverGetVersion(int *driverVersion) +try: (hipDriverGetVersion:=dll.hipDriverGetVersion).restype, hipDriverGetVersion.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# hipError_t hipRuntimeGetVersion(int *runtimeVersion) +try: (hipRuntimeGetVersion:=dll.hipRuntimeGetVersion).restype, hipRuntimeGetVersion.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# hipError_t hipDeviceGet(hipDevice_t *device, int ordinal) +try: (hipDeviceGet:=dll.hipDeviceGet).restype, hipDeviceGet.argtypes = hipError_t, [ctypes.POINTER(hipDevice_t), ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceComputeCapability(int *major, int *minor, hipDevice_t device) +try: (hipDeviceComputeCapability:=dll.hipDeviceComputeCapability).restype, hipDeviceComputeCapability.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipDevice_t] +except AttributeError: pass + +# hipError_t hipDeviceGetName(char *name, int len, hipDevice_t device) +try: (hipDeviceGetName:=dll.hipDeviceGetName).restype, hipDeviceGetName.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, hipDevice_t] +except AttributeError: pass + +# hipError_t hipDeviceGetUuid(hipUUID *uuid, hipDevice_t device) +try: (hipDeviceGetUuid:=dll.hipDeviceGetUuid).restype, hipDeviceGetUuid.argtypes = hipError_t, [ctypes.POINTER(hipUUID), hipDevice_t] +except AttributeError: pass + +# hipError_t hipDeviceGetP2PAttribute(int *value, hipDeviceP2PAttr attr, int srcDevice, int dstDevice) +try: (hipDeviceGetP2PAttribute:=dll.hipDeviceGetP2PAttribute).restype, hipDeviceGetP2PAttribute.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), hipDeviceP2PAttr, ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceGetPCIBusId(char *pciBusId, int len, int device) +try: (hipDeviceGetPCIBusId:=dll.hipDeviceGetPCIBusId).restype, hipDeviceGetPCIBusId.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceGetByPCIBusId(int *device, const char *pciBusId) +try: (hipDeviceGetByPCIBusId:=dll.hipDeviceGetByPCIBusId).restype, hipDeviceGetByPCIBusId.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hipError_t hipDeviceTotalMem(size_t *bytes, hipDevice_t device) +try: (hipDeviceTotalMem:=dll.hipDeviceTotalMem).restype, hipDeviceTotalMem.argtypes = hipError_t, [ctypes.POINTER(size_t), hipDevice_t] +except AttributeError: pass + +# hipError_t hipDeviceSynchronize() +try: (hipDeviceSynchronize:=dll.hipDeviceSynchronize).restype, hipDeviceSynchronize.argtypes = hipError_t, [] +except AttributeError: pass + +# hipError_t hipDeviceReset() +try: (hipDeviceReset:=dll.hipDeviceReset).restype, hipDeviceReset.argtypes = hipError_t, [] +except AttributeError: pass + +# hipError_t hipSetDevice(int deviceId) +try: (hipSetDevice:=dll.hipSetDevice).restype, hipSetDevice.argtypes = hipError_t, [ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipSetValidDevices(int *device_arr, int len) +try: (hipSetValidDevices:=dll.hipSetValidDevices).restype, hipSetValidDevices.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipGetDevice(int *deviceId) +try: (hipGetDevice:=dll.hipGetDevice).restype, hipGetDevice.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# hipError_t hipGetDeviceCount(int *count) +try: (hipGetDeviceCount:=dll.hipGetDeviceCount).restype, hipGetDeviceCount.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# hipError_t hipDeviceGetAttribute(int *pi, hipDeviceAttribute_t attr, int deviceId) +try: (hipDeviceGetAttribute:=dll.hipDeviceGetAttribute).restype, hipDeviceGetAttribute.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), hipDeviceAttribute_t, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceGetDefaultMemPool(hipMemPool_t *mem_pool, int device) +try: (hipDeviceGetDefaultMemPool:=dll.hipDeviceGetDefaultMemPool).restype, hipDeviceGetDefaultMemPool.argtypes = hipError_t, [ctypes.POINTER(hipMemPool_t), ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceSetMemPool(int device, hipMemPool_t mem_pool) +try: (hipDeviceSetMemPool:=dll.hipDeviceSetMemPool).restype, hipDeviceSetMemPool.argtypes = hipError_t, [ctypes.c_int32, hipMemPool_t] +except AttributeError: pass + +# hipError_t hipDeviceGetMemPool(hipMemPool_t *mem_pool, int device) +try: (hipDeviceGetMemPool:=dll.hipDeviceGetMemPool).restype, hipDeviceGetMemPool.argtypes = hipError_t, [ctypes.POINTER(hipMemPool_t), ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipGetDevicePropertiesR0600(hipDeviceProp_tR0600 *prop, int deviceId) +try: (hipGetDevicePropertiesR0600:=dll.hipGetDevicePropertiesR0600).restype, hipGetDevicePropertiesR0600.argtypes = hipError_t, [ctypes.POINTER(hipDeviceProp_tR0600), ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceSetCacheConfig(hipFuncCache_t cacheConfig) +try: (hipDeviceSetCacheConfig:=dll.hipDeviceSetCacheConfig).restype, hipDeviceSetCacheConfig.argtypes = hipError_t, [hipFuncCache_t] +except AttributeError: pass + +# hipError_t hipDeviceGetCacheConfig(hipFuncCache_t *cacheConfig) +try: (hipDeviceGetCacheConfig:=dll.hipDeviceGetCacheConfig).restype, hipDeviceGetCacheConfig.argtypes = hipError_t, [ctypes.POINTER(hipFuncCache_t)] +except AttributeError: pass + +# hipError_t hipDeviceGetLimit(size_t *pValue, enum hipLimit_t limit) +try: (hipDeviceGetLimit:=dll.hipDeviceGetLimit).restype, hipDeviceGetLimit.argtypes = hipError_t, [ctypes.POINTER(size_t), hipLimit_t] +except AttributeError: pass + +# hipError_t hipDeviceSetLimit(enum hipLimit_t limit, size_t value) +try: (hipDeviceSetLimit:=dll.hipDeviceSetLimit).restype, hipDeviceSetLimit.argtypes = hipError_t, [hipLimit_t, size_t] +except AttributeError: pass + +# hipError_t hipDeviceGetSharedMemConfig(hipSharedMemConfig *pConfig) +try: (hipDeviceGetSharedMemConfig:=dll.hipDeviceGetSharedMemConfig).restype, hipDeviceGetSharedMemConfig.argtypes = hipError_t, [ctypes.POINTER(hipSharedMemConfig)] +except AttributeError: pass + +# hipError_t hipGetDeviceFlags(unsigned int *flags) +try: (hipGetDeviceFlags:=dll.hipGetDeviceFlags).restype, hipGetDeviceFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# hipError_t hipDeviceSetSharedMemConfig(hipSharedMemConfig config) +try: (hipDeviceSetSharedMemConfig:=dll.hipDeviceSetSharedMemConfig).restype, hipDeviceSetSharedMemConfig.argtypes = hipError_t, [hipSharedMemConfig] +except AttributeError: pass + +# hipError_t hipSetDeviceFlags(unsigned int flags) +try: (hipSetDeviceFlags:=dll.hipSetDeviceFlags).restype, hipSetDeviceFlags.argtypes = hipError_t, [ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipChooseDeviceR0600(int *device, const hipDeviceProp_tR0600 *prop) +try: (hipChooseDeviceR0600:=dll.hipChooseDeviceR0600).restype, hipChooseDeviceR0600.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(hipDeviceProp_tR0600)] +except AttributeError: pass + +# hipError_t hipExtGetLinkTypeAndHopCount(int device1, int device2, uint32_t *linktype, uint32_t *hopcount) +try: (hipExtGetLinkTypeAndHopCount:=dll.hipExtGetLinkTypeAndHopCount).restype, hipExtGetLinkTypeAndHopCount.argtypes = hipError_t, [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(uint32_t), ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# hipError_t hipIpcGetMemHandle(hipIpcMemHandle_t *handle, void *devPtr) +try: (hipIpcGetMemHandle:=dll.hipIpcGetMemHandle).restype, hipIpcGetMemHandle.argtypes = hipError_t, [ctypes.POINTER(hipIpcMemHandle_t), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipIpcOpenMemHandle(void **devPtr, hipIpcMemHandle_t handle, unsigned int flags) +try: (hipIpcOpenMemHandle:=dll.hipIpcOpenMemHandle).restype, hipIpcOpenMemHandle.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), hipIpcMemHandle_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipIpcCloseMemHandle(void *devPtr) +try: (hipIpcCloseMemHandle:=dll.hipIpcCloseMemHandle).restype, hipIpcCloseMemHandle.argtypes = hipError_t, [ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipIpcGetEventHandle(hipIpcEventHandle_t *handle, hipEvent_t event) +try: (hipIpcGetEventHandle:=dll.hipIpcGetEventHandle).restype, hipIpcGetEventHandle.argtypes = hipError_t, [ctypes.POINTER(hipIpcEventHandle_t), hipEvent_t] +except AttributeError: pass + +# hipError_t hipIpcOpenEventHandle(hipEvent_t *event, hipIpcEventHandle_t handle) +try: (hipIpcOpenEventHandle:=dll.hipIpcOpenEventHandle).restype, hipIpcOpenEventHandle.argtypes = hipError_t, [ctypes.POINTER(hipEvent_t), hipIpcEventHandle_t] +except AttributeError: pass + +# hipError_t hipFuncSetAttribute(const void *func, hipFuncAttribute attr, int value) +try: (hipFuncSetAttribute:=dll.hipFuncSetAttribute).restype, hipFuncSetAttribute.argtypes = hipError_t, [ctypes.c_void_p, hipFuncAttribute, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipFuncSetCacheConfig(const void *func, hipFuncCache_t config) +try: (hipFuncSetCacheConfig:=dll.hipFuncSetCacheConfig).restype, hipFuncSetCacheConfig.argtypes = hipError_t, [ctypes.c_void_p, hipFuncCache_t] +except AttributeError: pass + +# hipError_t hipFuncSetSharedMemConfig(const void *func, hipSharedMemConfig config) +try: (hipFuncSetSharedMemConfig:=dll.hipFuncSetSharedMemConfig).restype, hipFuncSetSharedMemConfig.argtypes = hipError_t, [ctypes.c_void_p, hipSharedMemConfig] +except AttributeError: pass + +# hipError_t hipGetLastError() +try: (hipGetLastError:=dll.hipGetLastError).restype, hipGetLastError.argtypes = hipError_t, [] +except AttributeError: pass + +# hipError_t hipExtGetLastError() +try: (hipExtGetLastError:=dll.hipExtGetLastError).restype, hipExtGetLastError.argtypes = hipError_t, [] +except AttributeError: pass + +# hipError_t hipPeekAtLastError() +try: (hipPeekAtLastError:=dll.hipPeekAtLastError).restype, hipPeekAtLastError.argtypes = hipError_t, [] +except AttributeError: pass + +# const char *hipGetErrorName(hipError_t hip_error) +try: (hipGetErrorName:=dll.hipGetErrorName).restype, hipGetErrorName.argtypes = ctypes.POINTER(ctypes.c_char), [hipError_t] +except AttributeError: pass + +# const char *hipGetErrorString(hipError_t hipError) +try: (hipGetErrorString:=dll.hipGetErrorString).restype, hipGetErrorString.argtypes = ctypes.POINTER(ctypes.c_char), [hipError_t] +except AttributeError: pass + +# hipError_t hipDrvGetErrorName(hipError_t hipError, const char **errorString) +try: (hipDrvGetErrorName:=dll.hipDrvGetErrorName).restype, hipDrvGetErrorName.argtypes = hipError_t, [hipError_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# hipError_t hipDrvGetErrorString(hipError_t hipError, const char **errorString) +try: (hipDrvGetErrorString:=dll.hipDrvGetErrorString).restype, hipDrvGetErrorString.argtypes = hipError_t, [hipError_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# hipError_t hipStreamCreate(hipStream_t *stream) +try: (hipStreamCreate:=dll.hipStreamCreate).restype, hipStreamCreate.argtypes = hipError_t, [ctypes.POINTER(hipStream_t)] +except AttributeError: pass + +# hipError_t hipStreamCreateWithFlags(hipStream_t *stream, unsigned int flags) +try: (hipStreamCreateWithFlags:=dll.hipStreamCreateWithFlags).restype, hipStreamCreateWithFlags.argtypes = hipError_t, [ctypes.POINTER(hipStream_t), ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipStreamCreateWithPriority(hipStream_t *stream, unsigned int flags, int priority) +try: (hipStreamCreateWithPriority:=dll.hipStreamCreateWithPriority).restype, hipStreamCreateWithPriority.argtypes = hipError_t, [ctypes.POINTER(hipStream_t), ctypes.c_uint32, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceGetStreamPriorityRange(int *leastPriority, int *greatestPriority) +try: (hipDeviceGetStreamPriorityRange:=dll.hipDeviceGetStreamPriorityRange).restype, hipDeviceGetStreamPriorityRange.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# hipError_t hipStreamDestroy(hipStream_t stream) +try: (hipStreamDestroy:=dll.hipStreamDestroy).restype, hipStreamDestroy.argtypes = hipError_t, [hipStream_t] +except AttributeError: pass + +# hipError_t hipStreamQuery(hipStream_t stream) +try: (hipStreamQuery:=dll.hipStreamQuery).restype, hipStreamQuery.argtypes = hipError_t, [hipStream_t] +except AttributeError: pass + +# hipError_t hipStreamSynchronize(hipStream_t stream) +try: (hipStreamSynchronize:=dll.hipStreamSynchronize).restype, hipStreamSynchronize.argtypes = hipError_t, [hipStream_t] +except AttributeError: pass + +# hipError_t hipStreamWaitEvent(hipStream_t stream, hipEvent_t event, unsigned int flags = 0) +try: (hipStreamWaitEvent:=dll.hipStreamWaitEvent).restype, hipStreamWaitEvent.argtypes = hipError_t, [hipStream_t, hipEvent_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipStreamGetFlags(hipStream_t stream, unsigned int *flags) +try: (hipStreamGetFlags:=dll.hipStreamGetFlags).restype, hipStreamGetFlags.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# hipError_t hipStreamGetPriority(hipStream_t stream, int *priority) +try: (hipStreamGetPriority:=dll.hipStreamGetPriority).restype, hipStreamGetPriority.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# hipError_t hipStreamGetDevice(hipStream_t stream, hipDevice_t *device) +try: (hipStreamGetDevice:=dll.hipStreamGetDevice).restype, hipStreamGetDevice.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(hipDevice_t)] +except AttributeError: pass + +# hipError_t hipExtStreamCreateWithCUMask(hipStream_t *stream, uint32_t cuMaskSize, const uint32_t *cuMask) +try: (hipExtStreamCreateWithCUMask:=dll.hipExtStreamCreateWithCUMask).restype, hipExtStreamCreateWithCUMask.argtypes = hipError_t, [ctypes.POINTER(hipStream_t), uint32_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# hipError_t hipExtStreamGetCUMask(hipStream_t stream, uint32_t cuMaskSize, uint32_t *cuMask) +try: (hipExtStreamGetCUMask:=dll.hipExtStreamGetCUMask).restype, hipExtStreamGetCUMask.argtypes = hipError_t, [hipStream_t, uint32_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +hipStreamCallback_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(ihipStream_t), hipError_t, ctypes.c_void_p) +# hipError_t hipStreamAddCallback(hipStream_t stream, hipStreamCallback_t callback, void *userData, unsigned int flags) +try: (hipStreamAddCallback:=dll.hipStreamAddCallback).restype, hipStreamAddCallback.argtypes = hipError_t, [hipStream_t, hipStreamCallback_t, ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipStreamWaitValue32(hipStream_t stream, void *ptr, uint32_t value, unsigned int flags, uint32_t mask = 4294967295U) +try: (hipStreamWaitValue32:=dll.hipStreamWaitValue32).restype, hipStreamWaitValue32.argtypes = hipError_t, [hipStream_t, ctypes.c_void_p, uint32_t, ctypes.c_uint32, uint32_t] +except AttributeError: pass + uint64_t = ctypes.c_uint64 -try: - hipStreamWaitValue64 = _libraries['libamdhip64.so'].hipStreamWaitValue64 - hipStreamWaitValue64.restype = hipError_t - hipStreamWaitValue64.argtypes = [hipStream_t, ctypes.POINTER(None), uint64_t, ctypes.c_uint32, uint64_t] -except AttributeError: - pass -try: - hipStreamWriteValue32 = _libraries['libamdhip64.so'].hipStreamWriteValue32 - hipStreamWriteValue32.restype = hipError_t - hipStreamWriteValue32.argtypes = [hipStream_t, ctypes.POINTER(None), uint32_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipStreamWriteValue64 = _libraries['libamdhip64.so'].hipStreamWriteValue64 - hipStreamWriteValue64.restype = hipError_t - hipStreamWriteValue64.argtypes = [hipStream_t, ctypes.POINTER(None), uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipEventCreateWithFlags = _libraries['libamdhip64.so'].hipEventCreateWithFlags - hipEventCreateWithFlags.restype = hipError_t - hipEventCreateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t)), ctypes.c_uint32] -except AttributeError: - pass -try: - hipEventCreate = _libraries['libamdhip64.so'].hipEventCreate - hipEventCreate.restype = hipError_t - hipEventCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t))] -except AttributeError: - pass -try: - hipEventRecord = _libraries['libamdhip64.so'].hipEventRecord - hipEventRecord.restype = hipError_t - hipEventRecord.argtypes = [hipEvent_t, hipStream_t] -except AttributeError: - pass -try: - hipEventDestroy = _libraries['libamdhip64.so'].hipEventDestroy - hipEventDestroy.restype = hipError_t - hipEventDestroy.argtypes = [hipEvent_t] -except AttributeError: - pass -try: - hipEventSynchronize = _libraries['libamdhip64.so'].hipEventSynchronize - hipEventSynchronize.restype = hipError_t - hipEventSynchronize.argtypes = [hipEvent_t] -except AttributeError: - pass -try: - hipEventElapsedTime = _libraries['libamdhip64.so'].hipEventElapsedTime - hipEventElapsedTime.restype = hipError_t - hipEventElapsedTime.argtypes = [ctypes.POINTER(ctypes.c_float), hipEvent_t, hipEvent_t] -except AttributeError: - pass -try: - hipEventQuery = _libraries['libamdhip64.so'].hipEventQuery - hipEventQuery.restype = hipError_t - hipEventQuery.argtypes = [hipEvent_t] -except AttributeError: - pass -try: - hipPointerSetAttribute = _libraries['libamdhip64.so'].hipPointerSetAttribute - hipPointerSetAttribute.restype = hipError_t - hipPointerSetAttribute.argtypes = [ctypes.POINTER(None), hipPointer_attribute, hipDeviceptr_t] -except AttributeError: - pass -try: - hipPointerGetAttributes = _libraries['libamdhip64.so'].hipPointerGetAttributes - hipPointerGetAttributes.restype = hipError_t - hipPointerGetAttributes.argtypes = [ctypes.POINTER(struct_hipPointerAttribute_t), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipPointerGetAttribute = _libraries['libamdhip64.so'].hipPointerGetAttribute - hipPointerGetAttribute.restype = hipError_t - hipPointerGetAttribute.argtypes = [ctypes.POINTER(None), hipPointer_attribute, hipDeviceptr_t] -except AttributeError: - pass -try: - hipDrvPointerGetAttributes = _libraries['libamdhip64.so'].hipDrvPointerGetAttributes - hipDrvPointerGetAttributes.restype = hipError_t - hipDrvPointerGetAttributes.argtypes = [ctypes.c_uint32, ctypes.POINTER(hipPointer_attribute), ctypes.POINTER(ctypes.POINTER(None)), hipDeviceptr_t] -except AttributeError: - pass -try: - hipImportExternalSemaphore = _libraries['libamdhip64.so'].hipImportExternalSemaphore - hipImportExternalSemaphore.restype = hipError_t - hipImportExternalSemaphore.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalSemaphoreHandleDesc_st)] -except AttributeError: - pass -try: - hipSignalExternalSemaphoresAsync = _libraries['libamdhip64.so'].hipSignalExternalSemaphoresAsync - hipSignalExternalSemaphoresAsync.restype = hipError_t - hipSignalExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalSemaphoreSignalParams_st), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipWaitExternalSemaphoresAsync = _libraries['libamdhip64.so'].hipWaitExternalSemaphoresAsync - hipWaitExternalSemaphoresAsync.restype = hipError_t - hipWaitExternalSemaphoresAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalSemaphoreWaitParams_st), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipDestroyExternalSemaphore = _libraries['libamdhip64.so'].hipDestroyExternalSemaphore - hipDestroyExternalSemaphore.restype = hipError_t - hipDestroyExternalSemaphore.argtypes = [hipExternalSemaphore_t] -except AttributeError: - pass -try: - hipImportExternalMemory = _libraries['libamdhip64.so'].hipImportExternalMemory - hipImportExternalMemory.restype = hipError_t - hipImportExternalMemory.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_hipExternalMemoryHandleDesc_st)] -except AttributeError: - pass -try: - hipExternalMemoryGetMappedBuffer = _libraries['libamdhip64.so'].hipExternalMemoryGetMappedBuffer - hipExternalMemoryGetMappedBuffer.restype = hipError_t - hipExternalMemoryGetMappedBuffer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), hipExternalMemory_t, ctypes.POINTER(struct_hipExternalMemoryBufferDesc_st)] -except AttributeError: - pass -try: - hipDestroyExternalMemory = _libraries['libamdhip64.so'].hipDestroyExternalMemory - hipDestroyExternalMemory.restype = hipError_t - hipDestroyExternalMemory.argtypes = [hipExternalMemory_t] -except AttributeError: - pass -try: - hipExternalMemoryGetMappedMipmappedArray = _libraries['FIXME_STUB'].hipExternalMemoryGetMappedMipmappedArray - hipExternalMemoryGetMappedMipmappedArray.restype = hipError_t - hipExternalMemoryGetMappedMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), hipExternalMemory_t, ctypes.POINTER(struct_hipExternalMemoryMipmappedArrayDesc_st)] -except AttributeError: - pass -try: - hipMalloc = _libraries['libamdhip64.so'].hipMalloc - hipMalloc.restype = hipError_t - hipMalloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - hipExtMallocWithFlags = _libraries['libamdhip64.so'].hipExtMallocWithFlags - hipExtMallocWithFlags.restype = hipError_t - hipExtMallocWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMallocHost = _libraries['libamdhip64.so'].hipMallocHost - hipMallocHost.restype = hipError_t - hipMallocHost.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - hipMemAllocHost = _libraries['libamdhip64.so'].hipMemAllocHost - hipMemAllocHost.restype = hipError_t - hipMemAllocHost.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t] -except AttributeError: - pass -try: - hipHostMalloc = _libraries['libamdhip64.so'].hipHostMalloc - hipHostMalloc.restype = hipError_t - hipHostMalloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMallocManaged = _libraries['libamdhip64.so'].hipMallocManaged - hipMallocManaged.restype = hipError_t - hipMallocManaged.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMemPrefetchAsync = _libraries['libamdhip64.so'].hipMemPrefetchAsync - hipMemPrefetchAsync.restype = hipError_t - hipMemPrefetchAsync.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, hipStream_t] -except AttributeError: - pass -try: - hipMemAdvise = _libraries['libamdhip64.so'].hipMemAdvise - hipMemAdvise.restype = hipError_t - hipMemAdvise.argtypes = [ctypes.POINTER(None), size_t, hipMemoryAdvise, ctypes.c_int32] -except AttributeError: - pass -try: - hipMemRangeGetAttribute = _libraries['libamdhip64.so'].hipMemRangeGetAttribute - hipMemRangeGetAttribute.restype = hipError_t - hipMemRangeGetAttribute.argtypes = [ctypes.POINTER(None), size_t, hipMemRangeAttribute, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemRangeGetAttributes = _libraries['libamdhip64.so'].hipMemRangeGetAttributes - hipMemRangeGetAttributes.restype = hipError_t - hipMemRangeGetAttributes.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(hipMemRangeAttribute), size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipStreamAttachMemAsync = _libraries['libamdhip64.so'].hipStreamAttachMemAsync - hipStreamAttachMemAsync.restype = hipError_t - hipStreamAttachMemAsync.argtypes = [hipStream_t, ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMallocAsync = _libraries['libamdhip64.so'].hipMallocAsync - hipMallocAsync.restype = hipError_t - hipMallocAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, hipStream_t] -except AttributeError: - pass -try: - hipFreeAsync = _libraries['libamdhip64.so'].hipFreeAsync - hipFreeAsync.restype = hipError_t - hipFreeAsync.argtypes = [ctypes.POINTER(None), hipStream_t] -except AttributeError: - pass -try: - hipMemPoolTrimTo = _libraries['libamdhip64.so'].hipMemPoolTrimTo - hipMemPoolTrimTo.restype = hipError_t - hipMemPoolTrimTo.argtypes = [hipMemPool_t, size_t] -except AttributeError: - pass -try: - hipMemPoolSetAttribute = _libraries['libamdhip64.so'].hipMemPoolSetAttribute - hipMemPoolSetAttribute.restype = hipError_t - hipMemPoolSetAttribute.argtypes = [hipMemPool_t, hipMemPoolAttr, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemPoolGetAttribute = _libraries['libamdhip64.so'].hipMemPoolGetAttribute - hipMemPoolGetAttribute.restype = hipError_t - hipMemPoolGetAttribute.argtypes = [hipMemPool_t, hipMemPoolAttr, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemPoolSetAccess = _libraries['libamdhip64.so'].hipMemPoolSetAccess - hipMemPoolSetAccess.restype = hipError_t - hipMemPoolSetAccess.argtypes = [hipMemPool_t, ctypes.POINTER(struct_hipMemAccessDesc), size_t] -except AttributeError: - pass -try: - hipMemPoolGetAccess = _libraries['libamdhip64.so'].hipMemPoolGetAccess - hipMemPoolGetAccess.restype = hipError_t - hipMemPoolGetAccess.argtypes = [ctypes.POINTER(hipMemAccessFlags), hipMemPool_t, ctypes.POINTER(struct_hipMemLocation)] -except AttributeError: - pass -try: - hipMemPoolCreate = _libraries['libamdhip64.so'].hipMemPoolCreate - hipMemPoolCreate.restype = hipError_t - hipMemPoolCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.POINTER(struct_hipMemPoolProps)] -except AttributeError: - pass -try: - hipMemPoolDestroy = _libraries['libamdhip64.so'].hipMemPoolDestroy - hipMemPoolDestroy.restype = hipError_t - hipMemPoolDestroy.argtypes = [hipMemPool_t] -except AttributeError: - pass -try: - hipMallocFromPoolAsync = _libraries['libamdhip64.so'].hipMallocFromPoolAsync - hipMallocFromPoolAsync.restype = hipError_t - hipMallocFromPoolAsync.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, hipMemPool_t, hipStream_t] -except AttributeError: - pass -try: - hipMemPoolExportToShareableHandle = _libraries['libamdhip64.so'].hipMemPoolExportToShareableHandle - hipMemPoolExportToShareableHandle.restype = hipError_t - hipMemPoolExportToShareableHandle.argtypes = [ctypes.POINTER(None), hipMemPool_t, hipMemAllocationHandleType, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMemPoolImportFromShareableHandle = _libraries['libamdhip64.so'].hipMemPoolImportFromShareableHandle - hipMemPoolImportFromShareableHandle.restype = hipError_t - hipMemPoolImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemPoolHandle_t)), ctypes.POINTER(None), hipMemAllocationHandleType, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMemPoolExportPointer = _libraries['libamdhip64.so'].hipMemPoolExportPointer - hipMemPoolExportPointer.restype = hipError_t - hipMemPoolExportPointer.argtypes = [ctypes.POINTER(struct_hipMemPoolPtrExportData), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemPoolImportPointer = _libraries['libamdhip64.so'].hipMemPoolImportPointer - hipMemPoolImportPointer.restype = hipError_t - hipMemPoolImportPointer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), hipMemPool_t, ctypes.POINTER(struct_hipMemPoolPtrExportData)] -except AttributeError: - pass -try: - hipHostAlloc = _libraries['libamdhip64.so'].hipHostAlloc - hipHostAlloc.restype = hipError_t - hipHostAlloc.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipHostGetDevicePointer = _libraries['libamdhip64.so'].hipHostGetDevicePointer - hipHostGetDevicePointer.restype = hipError_t - hipHostGetDevicePointer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - hipHostGetFlags = _libraries['libamdhip64.so'].hipHostGetFlags - hipHostGetFlags.restype = hipError_t - hipHostGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipHostRegister = _libraries['libamdhip64.so'].hipHostRegister - hipHostRegister.restype = hipError_t - hipHostRegister.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipHostUnregister = _libraries['libamdhip64.so'].hipHostUnregister - hipHostUnregister.restype = hipError_t - hipHostUnregister.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMallocPitch = _libraries['libamdhip64.so'].hipMallocPitch - hipMallocPitch.restype = hipError_t - hipMallocPitch.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), size_t, size_t] -except AttributeError: - pass -try: - hipMemAllocPitch = _libraries['libamdhip64.so'].hipMemAllocPitch - hipMemAllocPitch.restype = hipError_t - hipMemAllocPitch.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipFree = _libraries['libamdhip64.so'].hipFree - hipFree.restype = hipError_t - hipFree.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipFreeHost = _libraries['libamdhip64.so'].hipFreeHost - hipFreeHost.restype = hipError_t - hipFreeHost.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipHostFree = _libraries['libamdhip64.so'].hipHostFree - hipHostFree.restype = hipError_t - hipHostFree.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemcpy = _libraries['libamdhip64.so'].hipMemcpy - hipMemcpy.restype = hipError_t - hipMemcpy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyWithStream = _libraries['libamdhip64.so'].hipMemcpyWithStream - hipMemcpyWithStream.restype = hipError_t - hipMemcpyWithStream.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyHtoD = _libraries['libamdhip64.so'].hipMemcpyHtoD - hipMemcpyHtoD.restype = hipError_t - hipMemcpyHtoD.argtypes = [hipDeviceptr_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemcpyDtoH = _libraries['libamdhip64.so'].hipMemcpyDtoH - hipMemcpyDtoH.restype = hipError_t - hipMemcpyDtoH.argtypes = [ctypes.POINTER(None), hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipMemcpyDtoD = _libraries['libamdhip64.so'].hipMemcpyDtoD - hipMemcpyDtoD.restype = hipError_t - hipMemcpyDtoD.argtypes = [hipDeviceptr_t, hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipMemcpyHtoDAsync = _libraries['libamdhip64.so'].hipMemcpyHtoDAsync - hipMemcpyHtoDAsync.restype = hipError_t - hipMemcpyHtoDAsync.argtypes = [hipDeviceptr_t, ctypes.POINTER(None), size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyDtoHAsync = _libraries['libamdhip64.so'].hipMemcpyDtoHAsync - hipMemcpyDtoHAsync.restype = hipError_t - hipMemcpyDtoHAsync.argtypes = [ctypes.POINTER(None), hipDeviceptr_t, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyDtoDAsync = _libraries['libamdhip64.so'].hipMemcpyDtoDAsync - hipMemcpyDtoDAsync.restype = hipError_t - hipMemcpyDtoDAsync.argtypes = [hipDeviceptr_t, hipDeviceptr_t, size_t, hipStream_t] -except AttributeError: - pass -try: - hipModuleGetGlobal = _libraries['libamdhip64.so'].hipModuleGetGlobal - hipModuleGetGlobal.restype = hipError_t - hipModuleGetGlobal.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), hipModule_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipGetSymbolAddress = _libraries['libamdhip64.so'].hipGetSymbolAddress - hipGetSymbolAddress.restype = hipError_t - hipGetSymbolAddress.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipGetSymbolSize = _libraries['libamdhip64.so'].hipGetSymbolSize - hipGetSymbolSize.restype = hipError_t - hipGetSymbolSize.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemcpyToSymbol = _libraries['libamdhip64.so'].hipMemcpyToSymbol - hipMemcpyToSymbol.restype = hipError_t - hipMemcpyToSymbol.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyToSymbolAsync = _libraries['libamdhip64.so'].hipMemcpyToSymbolAsync - hipMemcpyToSymbolAsync.restype = hipError_t - hipMemcpyToSymbolAsync.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyFromSymbol = _libraries['libamdhip64.so'].hipMemcpyFromSymbol - hipMemcpyFromSymbol.restype = hipError_t - hipMemcpyFromSymbol.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyFromSymbolAsync = _libraries['libamdhip64.so'].hipMemcpyFromSymbolAsync - hipMemcpyFromSymbolAsync.restype = hipError_t - hipMemcpyFromSymbolAsync.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyAsync = _libraries['libamdhip64.so'].hipMemcpyAsync - hipMemcpyAsync.restype = hipError_t - hipMemcpyAsync.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemset = _libraries['libamdhip64.so'].hipMemset - hipMemset.restype = hipError_t - hipMemset.argtypes = [ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipMemsetD8 = _libraries['libamdhip64.so'].hipMemsetD8 - hipMemsetD8.restype = hipError_t - hipMemsetD8.argtypes = [hipDeviceptr_t, ctypes.c_ubyte, size_t] -except AttributeError: - pass -try: - hipMemsetD8Async = _libraries['libamdhip64.so'].hipMemsetD8Async - hipMemsetD8Async.restype = hipError_t - hipMemsetD8Async.argtypes = [hipDeviceptr_t, ctypes.c_ubyte, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemsetD16 = _libraries['libamdhip64.so'].hipMemsetD16 - hipMemsetD16.restype = hipError_t - hipMemsetD16.argtypes = [hipDeviceptr_t, ctypes.c_uint16, size_t] -except AttributeError: - pass -try: - hipMemsetD16Async = _libraries['libamdhip64.so'].hipMemsetD16Async - hipMemsetD16Async.restype = hipError_t - hipMemsetD16Async.argtypes = [hipDeviceptr_t, ctypes.c_uint16, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemsetD32 = _libraries['libamdhip64.so'].hipMemsetD32 - hipMemsetD32.restype = hipError_t - hipMemsetD32.argtypes = [hipDeviceptr_t, ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipMemsetAsync = _libraries['libamdhip64.so'].hipMemsetAsync - hipMemsetAsync.restype = hipError_t - hipMemsetAsync.argtypes = [ctypes.POINTER(None), ctypes.c_int32, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemsetD32Async = _libraries['libamdhip64.so'].hipMemsetD32Async - hipMemsetD32Async.restype = hipError_t - hipMemsetD32Async.argtypes = [hipDeviceptr_t, ctypes.c_int32, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemset2D = _libraries['libamdhip64.so'].hipMemset2D - hipMemset2D.restype = hipError_t - hipMemset2D.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, size_t, size_t] -except AttributeError: - pass -try: - hipMemset2DAsync = _libraries['libamdhip64.so'].hipMemset2DAsync - hipMemset2DAsync.restype = hipError_t - hipMemset2DAsync.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_int32, size_t, size_t, hipStream_t] -except AttributeError: - pass -try: - hipMemset3D = _libraries['libamdhip64.so'].hipMemset3D - hipMemset3D.restype = hipError_t - hipMemset3D.argtypes = [hipPitchedPtr, ctypes.c_int32, hipExtent] -except AttributeError: - pass -try: - hipMemset3DAsync = _libraries['libamdhip64.so'].hipMemset3DAsync - hipMemset3DAsync.restype = hipError_t - hipMemset3DAsync.argtypes = [hipPitchedPtr, ctypes.c_int32, hipExtent, hipStream_t] -except AttributeError: - pass -try: - hipMemGetInfo = _libraries['libamdhip64.so'].hipMemGetInfo - hipMemGetInfo.restype = hipError_t - hipMemGetInfo.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipMemPtrGetInfo = _libraries['libamdhip64.so'].hipMemPtrGetInfo - hipMemPtrGetInfo.restype = hipError_t - hipMemPtrGetInfo.argtypes = [ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipMallocArray = _libraries['libamdhip64.so'].hipMallocArray - hipMallocArray.restype = hipError_t - hipMallocArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_hipChannelFormatDesc), size_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipArrayCreate = _libraries['libamdhip64.so'].hipArrayCreate - hipArrayCreate.restype = hipError_t - hipArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_HIP_ARRAY_DESCRIPTOR)] -except AttributeError: - pass -try: - hipArrayDestroy = _libraries['libamdhip64.so'].hipArrayDestroy - hipArrayDestroy.restype = hipError_t - hipArrayDestroy.argtypes = [hipArray_t] -except AttributeError: - pass -try: - hipArray3DCreate = _libraries['libamdhip64.so'].hipArray3DCreate - hipArray3DCreate.restype = hipError_t - hipArray3DCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_HIP_ARRAY3D_DESCRIPTOR)] -except AttributeError: - pass -try: - hipMalloc3D = _libraries['libamdhip64.so'].hipMalloc3D - hipMalloc3D.restype = hipError_t - hipMalloc3D.argtypes = [ctypes.POINTER(struct_hipPitchedPtr), hipExtent] -except AttributeError: - pass -try: - hipFreeArray = _libraries['libamdhip64.so'].hipFreeArray - hipFreeArray.restype = hipError_t - hipFreeArray.argtypes = [hipArray_t] -except AttributeError: - pass -try: - hipMalloc3DArray = _libraries['libamdhip64.so'].hipMalloc3DArray - hipMalloc3DArray.restype = hipError_t - hipMalloc3DArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), ctypes.POINTER(struct_hipChannelFormatDesc), struct_hipExtent, ctypes.c_uint32] -except AttributeError: - pass -try: - hipArrayGetInfo = _libraries['libamdhip64.so'].hipArrayGetInfo - hipArrayGetInfo.restype = hipError_t - hipArrayGetInfo.argtypes = [ctypes.POINTER(struct_hipChannelFormatDesc), ctypes.POINTER(struct_hipExtent), ctypes.POINTER(ctypes.c_uint32), hipArray_t] -except AttributeError: - pass -try: - hipArrayGetDescriptor = _libraries['libamdhip64.so'].hipArrayGetDescriptor - hipArrayGetDescriptor.restype = hipError_t - hipArrayGetDescriptor.argtypes = [ctypes.POINTER(struct_HIP_ARRAY_DESCRIPTOR), hipArray_t] -except AttributeError: - pass -try: - hipArray3DGetDescriptor = _libraries['libamdhip64.so'].hipArray3DGetDescriptor - hipArray3DGetDescriptor.restype = hipError_t - hipArray3DGetDescriptor.argtypes = [ctypes.POINTER(struct_HIP_ARRAY3D_DESCRIPTOR), hipArray_t] -except AttributeError: - pass -try: - hipMemcpy2D = _libraries['libamdhip64.so'].hipMemcpy2D - hipMemcpy2D.restype = hipError_t - hipMemcpy2D.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyParam2D = _libraries['libamdhip64.so'].hipMemcpyParam2D - hipMemcpyParam2D.restype = hipError_t - hipMemcpyParam2D.argtypes = [ctypes.POINTER(struct_hip_Memcpy2D)] -except AttributeError: - pass -try: - hipMemcpyParam2DAsync = _libraries['libamdhip64.so'].hipMemcpyParam2DAsync - hipMemcpyParam2DAsync.restype = hipError_t - hipMemcpyParam2DAsync.argtypes = [ctypes.POINTER(struct_hip_Memcpy2D), hipStream_t] -except AttributeError: - pass -try: - hipMemcpy2DAsync = _libraries['libamdhip64.so'].hipMemcpy2DAsync - hipMemcpy2DAsync.restype = hipError_t - hipMemcpy2DAsync.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpy2DToArray = _libraries['libamdhip64.so'].hipMemcpy2DToArray - hipMemcpy2DToArray.restype = hipError_t - hipMemcpy2DToArray.argtypes = [hipArray_t, size_t, size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpy2DToArrayAsync = _libraries['libamdhip64.so'].hipMemcpy2DToArrayAsync - hipMemcpy2DToArrayAsync.restype = hipError_t - hipMemcpy2DToArrayAsync.argtypes = [hipArray_t, size_t, size_t, ctypes.POINTER(None), size_t, size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyToArray = _libraries['libamdhip64.so'].hipMemcpyToArray - hipMemcpyToArray.restype = hipError_t - hipMemcpyToArray.argtypes = [hipArray_t, size_t, size_t, ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpyFromArray = _libraries['libamdhip64.so'].hipMemcpyFromArray - hipMemcpyFromArray.restype = hipError_t - hipMemcpyFromArray.argtypes = [ctypes.POINTER(None), hipArray_const_t, size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpy2DFromArray = _libraries['libamdhip64.so'].hipMemcpy2DFromArray - hipMemcpy2DFromArray.restype = hipError_t - hipMemcpy2DFromArray.argtypes = [ctypes.POINTER(None), size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipMemcpy2DFromArrayAsync = _libraries['libamdhip64.so'].hipMemcpy2DFromArrayAsync - hipMemcpy2DFromArrayAsync.restype = hipError_t - hipMemcpy2DFromArrayAsync.argtypes = [ctypes.POINTER(None), size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind, hipStream_t] -except AttributeError: - pass -try: - hipMemcpyAtoH = _libraries['libamdhip64.so'].hipMemcpyAtoH - hipMemcpyAtoH.restype = hipError_t - hipMemcpyAtoH.argtypes = [ctypes.POINTER(None), hipArray_t, size_t, size_t] -except AttributeError: - pass -try: - hipMemcpyHtoA = _libraries['libamdhip64.so'].hipMemcpyHtoA - hipMemcpyHtoA.restype = hipError_t - hipMemcpyHtoA.argtypes = [hipArray_t, size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemcpy3D = _libraries['libamdhip64.so'].hipMemcpy3D - hipMemcpy3D.restype = hipError_t - hipMemcpy3D.argtypes = [ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipMemcpy3DAsync = _libraries['libamdhip64.so'].hipMemcpy3DAsync - hipMemcpy3DAsync.restype = hipError_t - hipMemcpy3DAsync.argtypes = [ctypes.POINTER(struct_hipMemcpy3DParms), hipStream_t] -except AttributeError: - pass -try: - hipDrvMemcpy3D = _libraries['libamdhip64.so'].hipDrvMemcpy3D - hipDrvMemcpy3D.restype = hipError_t - hipDrvMemcpy3D.argtypes = [ctypes.POINTER(struct_HIP_MEMCPY3D)] -except AttributeError: - pass -try: - hipDrvMemcpy3DAsync = _libraries['libamdhip64.so'].hipDrvMemcpy3DAsync - hipDrvMemcpy3DAsync.restype = hipError_t - hipDrvMemcpy3DAsync.argtypes = [ctypes.POINTER(struct_HIP_MEMCPY3D), hipStream_t] -except AttributeError: - pass -try: - hipDeviceCanAccessPeer = _libraries['libamdhip64.so'].hipDeviceCanAccessPeer - hipDeviceCanAccessPeer.restype = hipError_t - hipDeviceCanAccessPeer.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - hipDeviceEnablePeerAccess = _libraries['libamdhip64.so'].hipDeviceEnablePeerAccess - hipDeviceEnablePeerAccess.restype = hipError_t - hipDeviceEnablePeerAccess.argtypes = [ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipDeviceDisablePeerAccess = _libraries['libamdhip64.so'].hipDeviceDisablePeerAccess - hipDeviceDisablePeerAccess.restype = hipError_t - hipDeviceDisablePeerAccess.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hipMemGetAddressRange = _libraries['libamdhip64.so'].hipMemGetAddressRange - hipMemGetAddressRange.restype = hipError_t - hipMemGetAddressRange.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), hipDeviceptr_t] -except AttributeError: - pass -try: - hipMemcpyPeer = _libraries['libamdhip64.so'].hipMemcpyPeer - hipMemcpyPeer.restype = hipError_t - hipMemcpyPeer.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipMemcpyPeerAsync = _libraries['libamdhip64.so'].hipMemcpyPeerAsync - hipMemcpyPeerAsync.restype = hipError_t - hipMemcpyPeerAsync.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, size_t, hipStream_t] -except AttributeError: - pass -try: - hipCtxCreate = _libraries['libamdhip64.so'].hipCtxCreate - hipCtxCreate.restype = hipError_t - hipCtxCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t)), ctypes.c_uint32, hipDevice_t] -except AttributeError: - pass -try: - hipCtxDestroy = _libraries['libamdhip64.so'].hipCtxDestroy - hipCtxDestroy.restype = hipError_t - hipCtxDestroy.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipCtxPopCurrent = _libraries['libamdhip64.so'].hipCtxPopCurrent - hipCtxPopCurrent.restype = hipError_t - hipCtxPopCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t))] -except AttributeError: - pass -try: - hipCtxPushCurrent = _libraries['libamdhip64.so'].hipCtxPushCurrent - hipCtxPushCurrent.restype = hipError_t - hipCtxPushCurrent.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipCtxSetCurrent = _libraries['libamdhip64.so'].hipCtxSetCurrent - hipCtxSetCurrent.restype = hipError_t - hipCtxSetCurrent.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipCtxGetCurrent = _libraries['libamdhip64.so'].hipCtxGetCurrent - hipCtxGetCurrent.restype = hipError_t - hipCtxGetCurrent.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t))] -except AttributeError: - pass -try: - hipCtxGetDevice = _libraries['libamdhip64.so'].hipCtxGetDevice - hipCtxGetDevice.restype = hipError_t - hipCtxGetDevice.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipCtxGetApiVersion = _libraries['libamdhip64.so'].hipCtxGetApiVersion - hipCtxGetApiVersion.restype = hipError_t - hipCtxGetApiVersion.argtypes = [hipCtx_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipCtxGetCacheConfig = _libraries['libamdhip64.so'].hipCtxGetCacheConfig - hipCtxGetCacheConfig.restype = hipError_t - hipCtxGetCacheConfig.argtypes = [ctypes.POINTER(hipFuncCache_t)] -except AttributeError: - pass -try: - hipCtxSetCacheConfig = _libraries['libamdhip64.so'].hipCtxSetCacheConfig - hipCtxSetCacheConfig.restype = hipError_t - hipCtxSetCacheConfig.argtypes = [hipFuncCache_t] -except AttributeError: - pass -try: - hipCtxSetSharedMemConfig = _libraries['libamdhip64.so'].hipCtxSetSharedMemConfig - hipCtxSetSharedMemConfig.restype = hipError_t - hipCtxSetSharedMemConfig.argtypes = [hipSharedMemConfig] -except AttributeError: - pass -try: - hipCtxGetSharedMemConfig = _libraries['libamdhip64.so'].hipCtxGetSharedMemConfig - hipCtxGetSharedMemConfig.restype = hipError_t - hipCtxGetSharedMemConfig.argtypes = [ctypes.POINTER(hipSharedMemConfig)] -except AttributeError: - pass -try: - hipCtxSynchronize = _libraries['libamdhip64.so'].hipCtxSynchronize - hipCtxSynchronize.restype = hipError_t - hipCtxSynchronize.argtypes = [] -except AttributeError: - pass -try: - hipCtxGetFlags = _libraries['libamdhip64.so'].hipCtxGetFlags - hipCtxGetFlags.restype = hipError_t - hipCtxGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipCtxEnablePeerAccess = _libraries['libamdhip64.so'].hipCtxEnablePeerAccess - hipCtxEnablePeerAccess.restype = hipError_t - hipCtxEnablePeerAccess.argtypes = [hipCtx_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipCtxDisablePeerAccess = _libraries['libamdhip64.so'].hipCtxDisablePeerAccess - hipCtxDisablePeerAccess.restype = hipError_t - hipCtxDisablePeerAccess.argtypes = [hipCtx_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxGetState = _libraries['libamdhip64.so'].hipDevicePrimaryCtxGetState - hipDevicePrimaryCtxGetState.restype = hipError_t - hipDevicePrimaryCtxGetState.argtypes = [hipDevice_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - hipDevicePrimaryCtxRelease = _libraries['libamdhip64.so'].hipDevicePrimaryCtxRelease - hipDevicePrimaryCtxRelease.restype = hipError_t - hipDevicePrimaryCtxRelease.argtypes = [hipDevice_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxRetain = _libraries['libamdhip64.so'].hipDevicePrimaryCtxRetain - hipDevicePrimaryCtxRetain.restype = hipError_t - hipDevicePrimaryCtxRetain.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipCtx_t)), hipDevice_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxReset = _libraries['libamdhip64.so'].hipDevicePrimaryCtxReset - hipDevicePrimaryCtxReset.restype = hipError_t - hipDevicePrimaryCtxReset.argtypes = [hipDevice_t] -except AttributeError: - pass -try: - hipDevicePrimaryCtxSetFlags = _libraries['libamdhip64.so'].hipDevicePrimaryCtxSetFlags - hipDevicePrimaryCtxSetFlags.restype = hipError_t - hipDevicePrimaryCtxSetFlags.argtypes = [hipDevice_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipModuleLoad = _libraries['libamdhip64.so'].hipModuleLoad - hipModuleLoad.restype = hipError_t - hipModuleLoad.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModule_t)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipModuleUnload = _libraries['libamdhip64.so'].hipModuleUnload - hipModuleUnload.restype = hipError_t - hipModuleUnload.argtypes = [hipModule_t] -except AttributeError: - pass -try: - hipModuleGetFunction = _libraries['libamdhip64.so'].hipModuleGetFunction - hipModuleGetFunction.restype = hipError_t - hipModuleGetFunction.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModuleSymbol_t)), hipModule_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipFuncGetAttributes = _libraries['libamdhip64.so'].hipFuncGetAttributes - hipFuncGetAttributes.restype = hipError_t - hipFuncGetAttributes.argtypes = [ctypes.POINTER(struct_hipFuncAttributes), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipFuncGetAttribute = _libraries['libamdhip64.so'].hipFuncGetAttribute - hipFuncGetAttribute.restype = hipError_t - hipFuncGetAttribute.argtypes = [ctypes.POINTER(ctypes.c_int32), hipFunction_attribute, hipFunction_t] -except AttributeError: - pass -class struct_textureReference(Structure): - pass +# hipError_t hipStreamWaitValue64(hipStream_t stream, void *ptr, uint64_t value, unsigned int flags, uint64_t mask = 18446744073709551615UL) +try: (hipStreamWaitValue64:=dll.hipStreamWaitValue64).restype, hipStreamWaitValue64.argtypes = hipError_t, [hipStream_t, ctypes.c_void_p, uint64_t, ctypes.c_uint32, uint64_t] +except AttributeError: pass -class struct___hip_texture(Structure): - pass +# hipError_t hipStreamWriteValue32(hipStream_t stream, void *ptr, uint32_t value, unsigned int flags) +try: (hipStreamWriteValue32:=dll.hipStreamWriteValue32).restype, hipStreamWriteValue32.argtypes = hipError_t, [hipStream_t, ctypes.c_void_p, uint32_t, ctypes.c_uint32] +except AttributeError: pass +# hipError_t hipStreamWriteValue64(hipStream_t stream, void *ptr, uint64_t value, unsigned int flags) +try: (hipStreamWriteValue64:=dll.hipStreamWriteValue64).restype, hipStreamWriteValue64.argtypes = hipError_t, [hipStream_t, ctypes.c_void_p, uint64_t, ctypes.c_uint32] +except AttributeError: pass -# values for enumeration 'hipTextureReadMode' -hipTextureReadMode__enumvalues = { - 0: 'hipReadModeElementType', - 1: 'hipReadModeNormalizedFloat', -} -hipReadModeElementType = 0 -hipReadModeNormalizedFloat = 1 -hipTextureReadMode = ctypes.c_uint32 # enum +# hipError_t hipEventCreateWithFlags(hipEvent_t *event, unsigned int flags) +try: (hipEventCreateWithFlags:=dll.hipEventCreateWithFlags).restype, hipEventCreateWithFlags.argtypes = hipError_t, [ctypes.POINTER(hipEvent_t), ctypes.c_uint32] +except AttributeError: pass -# values for enumeration 'hipTextureFilterMode' -hipTextureFilterMode__enumvalues = { - 0: 'hipFilterModePoint', - 1: 'hipFilterModeLinear', -} -hipFilterModePoint = 0 -hipFilterModeLinear = 1 -hipTextureFilterMode = ctypes.c_uint32 # enum +# hipError_t hipEventCreate(hipEvent_t *event) +try: (hipEventCreate:=dll.hipEventCreate).restype, hipEventCreate.argtypes = hipError_t, [ctypes.POINTER(hipEvent_t)] +except AttributeError: pass -# values for enumeration 'hipTextureAddressMode' -hipTextureAddressMode__enumvalues = { - 0: 'hipAddressModeWrap', - 1: 'hipAddressModeClamp', - 2: 'hipAddressModeMirror', - 3: 'hipAddressModeBorder', -} -hipAddressModeWrap = 0 -hipAddressModeClamp = 1 -hipAddressModeMirror = 2 -hipAddressModeBorder = 3 -hipTextureAddressMode = ctypes.c_uint32 # enum -struct_textureReference._pack_ = 1 # source:False -struct_textureReference._fields_ = [ - ('normalized', ctypes.c_int32), - ('readMode', hipTextureReadMode), - ('filterMode', hipTextureFilterMode), - ('addressMode', hipTextureAddressMode * 3), - ('channelDesc', struct_hipChannelFormatDesc), - ('sRGB', ctypes.c_int32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', hipTextureFilterMode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), - ('PADDING_0', ctypes.c_ubyte * 4), - ('textureObject', ctypes.POINTER(struct___hip_texture)), - ('numChannels', ctypes.c_int32), - ('format', hipArray_Format), +# hipError_t hipEventRecord(hipEvent_t event, hipStream_t stream = __null) +try: (hipEventRecord:=dll.hipEventRecord).restype, hipEventRecord.argtypes = hipError_t, [hipEvent_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipEventDestroy(hipEvent_t event) +try: (hipEventDestroy:=dll.hipEventDestroy).restype, hipEventDestroy.argtypes = hipError_t, [hipEvent_t] +except AttributeError: pass + +# hipError_t hipEventSynchronize(hipEvent_t event) +try: (hipEventSynchronize:=dll.hipEventSynchronize).restype, hipEventSynchronize.argtypes = hipError_t, [hipEvent_t] +except AttributeError: pass + +# hipError_t hipEventElapsedTime(float *ms, hipEvent_t start, hipEvent_t stop) +try: (hipEventElapsedTime:=dll.hipEventElapsedTime).restype, hipEventElapsedTime.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_float), hipEvent_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipEventQuery(hipEvent_t event) +try: (hipEventQuery:=dll.hipEventQuery).restype, hipEventQuery.argtypes = hipError_t, [hipEvent_t] +except AttributeError: pass + +hipPointer_attribute = CEnum(ctypes.c_uint32) +HIP_POINTER_ATTRIBUTE_CONTEXT = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_CONTEXT', 1) +HIP_POINTER_ATTRIBUTE_MEMORY_TYPE = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_MEMORY_TYPE', 2) +HIP_POINTER_ATTRIBUTE_DEVICE_POINTER = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_DEVICE_POINTER', 3) +HIP_POINTER_ATTRIBUTE_HOST_POINTER = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_HOST_POINTER', 4) +HIP_POINTER_ATTRIBUTE_P2P_TOKENS = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_P2P_TOKENS', 5) +HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS', 6) +HIP_POINTER_ATTRIBUTE_BUFFER_ID = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_BUFFER_ID', 7) +HIP_POINTER_ATTRIBUTE_IS_MANAGED = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_IS_MANAGED', 8) +HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL', 9) +HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE', 10) +HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR', 11) +HIP_POINTER_ATTRIBUTE_RANGE_SIZE = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_RANGE_SIZE', 12) +HIP_POINTER_ATTRIBUTE_MAPPED = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_MAPPED', 13) +HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', 14) +HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', 15) +HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS', 16) +HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE = hipPointer_attribute.define('HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', 17) + +# hipError_t hipPointerSetAttribute(const void *value, hipPointer_attribute attribute, hipDeviceptr_t ptr) +try: (hipPointerSetAttribute:=dll.hipPointerSetAttribute).restype, hipPointerSetAttribute.argtypes = hipError_t, [ctypes.c_void_p, hipPointer_attribute, hipDeviceptr_t] +except AttributeError: pass + +# hipError_t hipPointerGetAttributes(hipPointerAttribute_t *attributes, const void *ptr) +try: (hipPointerGetAttributes:=dll.hipPointerGetAttributes).restype, hipPointerGetAttributes.argtypes = hipError_t, [ctypes.POINTER(hipPointerAttribute_t), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipPointerGetAttribute(void *data, hipPointer_attribute attribute, hipDeviceptr_t ptr) +try: (hipPointerGetAttribute:=dll.hipPointerGetAttribute).restype, hipPointerGetAttribute.argtypes = hipError_t, [ctypes.c_void_p, hipPointer_attribute, hipDeviceptr_t] +except AttributeError: pass + +# hipError_t hipDrvPointerGetAttributes(unsigned int numAttributes, hipPointer_attribute *attributes, void **data, hipDeviceptr_t ptr) +try: (hipDrvPointerGetAttributes:=dll.hipDrvPointerGetAttributes).restype, hipDrvPointerGetAttributes.argtypes = hipError_t, [ctypes.c_uint32, ctypes.POINTER(hipPointer_attribute), ctypes.POINTER(ctypes.c_void_p), hipDeviceptr_t] +except AttributeError: pass + +# hipError_t hipImportExternalSemaphore(hipExternalSemaphore_t *extSem_out, const hipExternalSemaphoreHandleDesc *semHandleDesc) +try: (hipImportExternalSemaphore:=dll.hipImportExternalSemaphore).restype, hipImportExternalSemaphore.argtypes = hipError_t, [ctypes.POINTER(hipExternalSemaphore_t), ctypes.POINTER(hipExternalSemaphoreHandleDesc)] +except AttributeError: pass + +# hipError_t hipSignalExternalSemaphoresAsync(const hipExternalSemaphore_t *extSemArray, const hipExternalSemaphoreSignalParams *paramsArray, unsigned int numExtSems, hipStream_t stream) +try: (hipSignalExternalSemaphoresAsync:=dll.hipSignalExternalSemaphoresAsync).restype, hipSignalExternalSemaphoresAsync.argtypes = hipError_t, [ctypes.POINTER(hipExternalSemaphore_t), ctypes.POINTER(hipExternalSemaphoreSignalParams), ctypes.c_uint32, hipStream_t] +except AttributeError: pass + +# hipError_t hipWaitExternalSemaphoresAsync(const hipExternalSemaphore_t *extSemArray, const hipExternalSemaphoreWaitParams *paramsArray, unsigned int numExtSems, hipStream_t stream) +try: (hipWaitExternalSemaphoresAsync:=dll.hipWaitExternalSemaphoresAsync).restype, hipWaitExternalSemaphoresAsync.argtypes = hipError_t, [ctypes.POINTER(hipExternalSemaphore_t), ctypes.POINTER(hipExternalSemaphoreWaitParams), ctypes.c_uint32, hipStream_t] +except AttributeError: pass + +# hipError_t hipDestroyExternalSemaphore(hipExternalSemaphore_t extSem) +try: (hipDestroyExternalSemaphore:=dll.hipDestroyExternalSemaphore).restype, hipDestroyExternalSemaphore.argtypes = hipError_t, [hipExternalSemaphore_t] +except AttributeError: pass + +# hipError_t hipImportExternalMemory(hipExternalMemory_t *extMem_out, const hipExternalMemoryHandleDesc *memHandleDesc) +try: (hipImportExternalMemory:=dll.hipImportExternalMemory).restype, hipImportExternalMemory.argtypes = hipError_t, [ctypes.POINTER(hipExternalMemory_t), ctypes.POINTER(hipExternalMemoryHandleDesc)] +except AttributeError: pass + +# hipError_t hipExternalMemoryGetMappedBuffer(void **devPtr, hipExternalMemory_t extMem, const hipExternalMemoryBufferDesc *bufferDesc) +try: (hipExternalMemoryGetMappedBuffer:=dll.hipExternalMemoryGetMappedBuffer).restype, hipExternalMemoryGetMappedBuffer.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), hipExternalMemory_t, ctypes.POINTER(hipExternalMemoryBufferDesc)] +except AttributeError: pass + +# hipError_t hipDestroyExternalMemory(hipExternalMemory_t extMem) +try: (hipDestroyExternalMemory:=dll.hipDestroyExternalMemory).restype, hipDestroyExternalMemory.argtypes = hipError_t, [hipExternalMemory_t] +except AttributeError: pass + +hipMipmappedArray_t = ctypes.POINTER(hipMipmappedArray) +# hipError_t hipExternalMemoryGetMappedMipmappedArray(hipMipmappedArray_t *mipmap, hipExternalMemory_t extMem, const hipExternalMemoryMipmappedArrayDesc *mipmapDesc) +try: (hipExternalMemoryGetMappedMipmappedArray:=dll.hipExternalMemoryGetMappedMipmappedArray).restype, hipExternalMemoryGetMappedMipmappedArray.argtypes = hipError_t, [ctypes.POINTER(hipMipmappedArray_t), hipExternalMemory_t, ctypes.POINTER(hipExternalMemoryMipmappedArrayDesc)] +except AttributeError: pass + +# hipError_t hipMalloc(void **ptr, size_t size) +try: (hipMalloc:=dll.hipMalloc).restype, hipMalloc.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t] +except AttributeError: pass + +# hipError_t hipExtMallocWithFlags(void **ptr, size_t sizeBytes, unsigned int flags) +try: (hipExtMallocWithFlags:=dll.hipExtMallocWithFlags).restype, hipExtMallocWithFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, ctypes.c_uint32] +except AttributeError: pass + +# __attribute__((deprecated("use hipHostMalloc instead"))) hipError_t hipMallocHost(void **ptr, size_t size) +try: (hipMallocHost:=dll.hipMallocHost).restype, hipMallocHost.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t] +except AttributeError: pass + +# __attribute__((deprecated("use hipHostMalloc instead"))) hipError_t hipMemAllocHost(void **ptr, size_t size) +try: (hipMemAllocHost:=dll.hipMemAllocHost).restype, hipMemAllocHost.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t] +except AttributeError: pass + +# hipError_t hipHostMalloc(void **ptr, size_t size, unsigned int flags) +try: (hipHostMalloc:=dll.hipHostMalloc).restype, hipHostMalloc.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMallocManaged(void **dev_ptr, size_t size, unsigned int flags = 1) +try: (hipMallocManaged:=dll.hipMallocManaged).restype, hipMallocManaged.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMemPrefetchAsync(const void *dev_ptr, size_t count, int device, hipStream_t stream = 0) +try: (hipMemPrefetchAsync:=dll.hipMemPrefetchAsync).restype, hipMemPrefetchAsync.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.c_int32, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemAdvise(const void *dev_ptr, size_t count, hipMemoryAdvise advice, int device) +try: (hipMemAdvise:=dll.hipMemAdvise).restype, hipMemAdvise.argtypes = hipError_t, [ctypes.c_void_p, size_t, hipMemoryAdvise, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipMemRangeGetAttribute(void *data, size_t data_size, hipMemRangeAttribute attribute, const void *dev_ptr, size_t count) +try: (hipMemRangeGetAttribute:=dll.hipMemRangeGetAttribute).restype, hipMemRangeGetAttribute.argtypes = hipError_t, [ctypes.c_void_p, size_t, hipMemRangeAttribute, ctypes.c_void_p, size_t] +except AttributeError: pass + +# hipError_t hipMemRangeGetAttributes(void **data, size_t *data_sizes, hipMemRangeAttribute *attributes, size_t num_attributes, const void *dev_ptr, size_t count) +try: (hipMemRangeGetAttributes:=dll.hipMemRangeGetAttributes).restype, hipMemRangeGetAttributes.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t), ctypes.POINTER(hipMemRangeAttribute), size_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# hipError_t hipStreamAttachMemAsync(hipStream_t stream, void *dev_ptr, size_t length = 0, unsigned int flags = 4) +try: (hipStreamAttachMemAsync:=dll.hipStreamAttachMemAsync).restype, hipStreamAttachMemAsync.argtypes = hipError_t, [hipStream_t, ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMallocAsync(void **dev_ptr, size_t size, hipStream_t stream) +try: (hipMallocAsync:=dll.hipMallocAsync).restype, hipMallocAsync.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipFreeAsync(void *dev_ptr, hipStream_t stream) +try: (hipFreeAsync:=dll.hipFreeAsync).restype, hipFreeAsync.argtypes = hipError_t, [ctypes.c_void_p, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemPoolTrimTo(hipMemPool_t mem_pool, size_t min_bytes_to_hold) +try: (hipMemPoolTrimTo:=dll.hipMemPoolTrimTo).restype, hipMemPoolTrimTo.argtypes = hipError_t, [hipMemPool_t, size_t] +except AttributeError: pass + +# hipError_t hipMemPoolSetAttribute(hipMemPool_t mem_pool, hipMemPoolAttr attr, void *value) +try: (hipMemPoolSetAttribute:=dll.hipMemPoolSetAttribute).restype, hipMemPoolSetAttribute.argtypes = hipError_t, [hipMemPool_t, hipMemPoolAttr, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMemPoolGetAttribute(hipMemPool_t mem_pool, hipMemPoolAttr attr, void *value) +try: (hipMemPoolGetAttribute:=dll.hipMemPoolGetAttribute).restype, hipMemPoolGetAttribute.argtypes = hipError_t, [hipMemPool_t, hipMemPoolAttr, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMemPoolSetAccess(hipMemPool_t mem_pool, const hipMemAccessDesc *desc_list, size_t count) +try: (hipMemPoolSetAccess:=dll.hipMemPoolSetAccess).restype, hipMemPoolSetAccess.argtypes = hipError_t, [hipMemPool_t, ctypes.POINTER(hipMemAccessDesc), size_t] +except AttributeError: pass + +# hipError_t hipMemPoolGetAccess(hipMemAccessFlags *flags, hipMemPool_t mem_pool, hipMemLocation *location) +try: (hipMemPoolGetAccess:=dll.hipMemPoolGetAccess).restype, hipMemPoolGetAccess.argtypes = hipError_t, [ctypes.POINTER(hipMemAccessFlags), hipMemPool_t, ctypes.POINTER(hipMemLocation)] +except AttributeError: pass + +# hipError_t hipMemPoolCreate(hipMemPool_t *mem_pool, const hipMemPoolProps *pool_props) +try: (hipMemPoolCreate:=dll.hipMemPoolCreate).restype, hipMemPoolCreate.argtypes = hipError_t, [ctypes.POINTER(hipMemPool_t), ctypes.POINTER(hipMemPoolProps)] +except AttributeError: pass + +# hipError_t hipMemPoolDestroy(hipMemPool_t mem_pool) +try: (hipMemPoolDestroy:=dll.hipMemPoolDestroy).restype, hipMemPoolDestroy.argtypes = hipError_t, [hipMemPool_t] +except AttributeError: pass + +# hipError_t hipMallocFromPoolAsync(void **dev_ptr, size_t size, hipMemPool_t mem_pool, hipStream_t stream) +try: (hipMallocFromPoolAsync:=dll.hipMallocFromPoolAsync).restype, hipMallocFromPoolAsync.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, hipMemPool_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemPoolExportToShareableHandle(void *shared_handle, hipMemPool_t mem_pool, hipMemAllocationHandleType handle_type, unsigned int flags) +try: (hipMemPoolExportToShareableHandle:=dll.hipMemPoolExportToShareableHandle).restype, hipMemPoolExportToShareableHandle.argtypes = hipError_t, [ctypes.c_void_p, hipMemPool_t, hipMemAllocationHandleType, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMemPoolImportFromShareableHandle(hipMemPool_t *mem_pool, void *shared_handle, hipMemAllocationHandleType handle_type, unsigned int flags) +try: (hipMemPoolImportFromShareableHandle:=dll.hipMemPoolImportFromShareableHandle).restype, hipMemPoolImportFromShareableHandle.argtypes = hipError_t, [ctypes.POINTER(hipMemPool_t), ctypes.c_void_p, hipMemAllocationHandleType, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMemPoolExportPointer(hipMemPoolPtrExportData *export_data, void *dev_ptr) +try: (hipMemPoolExportPointer:=dll.hipMemPoolExportPointer).restype, hipMemPoolExportPointer.argtypes = hipError_t, [ctypes.POINTER(hipMemPoolPtrExportData), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMemPoolImportPointer(void **dev_ptr, hipMemPool_t mem_pool, hipMemPoolPtrExportData *export_data) +try: (hipMemPoolImportPointer:=dll.hipMemPoolImportPointer).restype, hipMemPoolImportPointer.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), hipMemPool_t, ctypes.POINTER(hipMemPoolPtrExportData)] +except AttributeError: pass + +# __attribute__((deprecated("use hipHostMalloc instead"))) hipError_t hipHostAlloc(void **ptr, size_t size, unsigned int flags) +try: (hipHostAlloc:=dll.hipHostAlloc).restype, hipHostAlloc.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipHostGetDevicePointer(void **devPtr, void *hstPtr, unsigned int flags) +try: (hipHostGetDevicePointer:=dll.hipHostGetDevicePointer).restype, hipHostGetDevicePointer.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipHostGetFlags(unsigned int *flagsPtr, void *hostPtr) +try: (hipHostGetFlags:=dll.hipHostGetFlags).restype, hipHostGetFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_uint32), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipHostRegister(void *hostPtr, size_t sizeBytes, unsigned int flags) +try: (hipHostRegister:=dll.hipHostRegister).restype, hipHostRegister.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipHostUnregister(void *hostPtr) +try: (hipHostUnregister:=dll.hipHostUnregister).restype, hipHostUnregister.argtypes = hipError_t, [ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMallocPitch(void **ptr, size_t *pitch, size_t width, size_t height) +try: (hipMallocPitch:=dll.hipMallocPitch).restype, hipMallocPitch.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t), size_t, size_t] +except AttributeError: pass + +# hipError_t hipMemAllocPitch(hipDeviceptr_t *dptr, size_t *pitch, size_t widthInBytes, size_t height, unsigned int elementSizeBytes) +try: (hipMemAllocPitch:=dll.hipMemAllocPitch).restype, hipMemAllocPitch.argtypes = hipError_t, [ctypes.POINTER(hipDeviceptr_t), ctypes.POINTER(size_t), size_t, size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipFree(void *ptr) +try: (hipFree:=dll.hipFree).restype, hipFree.argtypes = hipError_t, [ctypes.c_void_p] +except AttributeError: pass + +# __attribute__((deprecated("use hipHostFree instead"))) hipError_t hipFreeHost(void *ptr) +try: (hipFreeHost:=dll.hipFreeHost).restype, hipFreeHost.argtypes = hipError_t, [ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipHostFree(void *ptr) +try: (hipHostFree:=dll.hipHostFree).restype, hipHostFree.argtypes = hipError_t, [ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMemcpy(void *dst, const void *src, size_t sizeBytes, hipMemcpyKind kind) +try: (hipMemcpy:=dll.hipMemcpy).restype, hipMemcpy.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipMemcpyWithStream(void *dst, const void *src, size_t sizeBytes, hipMemcpyKind kind, hipStream_t stream) +try: (hipMemcpyWithStream:=dll.hipMemcpyWithStream).restype, hipMemcpyWithStream.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyHtoD(hipDeviceptr_t dst, void *src, size_t sizeBytes) +try: (hipMemcpyHtoD:=dll.hipMemcpyHtoD).restype, hipMemcpyHtoD.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyDtoH(void *dst, hipDeviceptr_t src, size_t sizeBytes) +try: (hipMemcpyDtoH:=dll.hipMemcpyDtoH).restype, hipMemcpyDtoH.argtypes = hipError_t, [ctypes.c_void_p, hipDeviceptr_t, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyDtoD(hipDeviceptr_t dst, hipDeviceptr_t src, size_t sizeBytes) +try: (hipMemcpyDtoD:=dll.hipMemcpyDtoD).restype, hipMemcpyDtoD.argtypes = hipError_t, [hipDeviceptr_t, hipDeviceptr_t, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyAtoD(hipDeviceptr_t dstDevice, hipArray_t srcArray, size_t srcOffset, size_t ByteCount) +try: (hipMemcpyAtoD:=dll.hipMemcpyAtoD).restype, hipMemcpyAtoD.argtypes = hipError_t, [hipDeviceptr_t, hipArray_t, size_t, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyDtoA(hipArray_t dstArray, size_t dstOffset, hipDeviceptr_t srcDevice, size_t ByteCount) +try: (hipMemcpyDtoA:=dll.hipMemcpyDtoA).restype, hipMemcpyDtoA.argtypes = hipError_t, [hipArray_t, size_t, hipDeviceptr_t, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyAtoA(hipArray_t dstArray, size_t dstOffset, hipArray_t srcArray, size_t srcOffset, size_t ByteCount) +try: (hipMemcpyAtoA:=dll.hipMemcpyAtoA).restype, hipMemcpyAtoA.argtypes = hipError_t, [hipArray_t, size_t, hipArray_t, size_t, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyHtoDAsync(hipDeviceptr_t dst, void *src, size_t sizeBytes, hipStream_t stream) +try: (hipMemcpyHtoDAsync:=dll.hipMemcpyHtoDAsync).restype, hipMemcpyHtoDAsync.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_void_p, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyDtoHAsync(void *dst, hipDeviceptr_t src, size_t sizeBytes, hipStream_t stream) +try: (hipMemcpyDtoHAsync:=dll.hipMemcpyDtoHAsync).restype, hipMemcpyDtoHAsync.argtypes = hipError_t, [ctypes.c_void_p, hipDeviceptr_t, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyDtoDAsync(hipDeviceptr_t dst, hipDeviceptr_t src, size_t sizeBytes, hipStream_t stream) +try: (hipMemcpyDtoDAsync:=dll.hipMemcpyDtoDAsync).restype, hipMemcpyDtoDAsync.argtypes = hipError_t, [hipDeviceptr_t, hipDeviceptr_t, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyAtoHAsync(void *dstHost, hipArray_t srcArray, size_t srcOffset, size_t ByteCount, hipStream_t stream) +try: (hipMemcpyAtoHAsync:=dll.hipMemcpyAtoHAsync).restype, hipMemcpyAtoHAsync.argtypes = hipError_t, [ctypes.c_void_p, hipArray_t, size_t, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyHtoAAsync(hipArray_t dstArray, size_t dstOffset, const void *srcHost, size_t ByteCount, hipStream_t stream) +try: (hipMemcpyHtoAAsync:=dll.hipMemcpyHtoAAsync).restype, hipMemcpyHtoAAsync.argtypes = hipError_t, [hipArray_t, size_t, ctypes.c_void_p, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipModuleGetGlobal(hipDeviceptr_t *dptr, size_t *bytes, hipModule_t hmod, const char *name) +try: (hipModuleGetGlobal:=dll.hipModuleGetGlobal).restype, hipModuleGetGlobal.argtypes = hipError_t, [ctypes.POINTER(hipDeviceptr_t), ctypes.POINTER(size_t), hipModule_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hipError_t hipGetSymbolAddress(void **devPtr, const void *symbol) +try: (hipGetSymbolAddress:=dll.hipGetSymbolAddress).restype, hipGetSymbolAddress.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipGetSymbolSize(size_t *size, const void *symbol) +try: (hipGetSymbolSize:=dll.hipGetSymbolSize).restype, hipGetSymbolSize.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipGetProcAddress(const char *symbol, void **pfn, int hipVersion, uint64_t flags, hipDriverProcAddressQueryResult *symbolStatus) +try: (hipGetProcAddress:=dll.hipGetProcAddress).restype, hipGetProcAddress.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_void_p), ctypes.c_int32, uint64_t, ctypes.POINTER(hipDriverProcAddressQueryResult)] +except AttributeError: pass + +# hipError_t hipMemcpyToSymbol(const void *symbol, const void *src, size_t sizeBytes, size_t offset = 0, hipMemcpyKind kind = hipMemcpyHostToDevice) +try: (hipMemcpyToSymbol:=dll.hipMemcpyToSymbol).restype, hipMemcpyToSymbol.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipMemcpyToSymbolAsync(const void *symbol, const void *src, size_t sizeBytes, size_t offset, hipMemcpyKind kind, hipStream_t stream = 0) +try: (hipMemcpyToSymbolAsync:=dll.hipMemcpyToSymbolAsync).restype, hipMemcpyToSymbolAsync.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyFromSymbol(void *dst, const void *symbol, size_t sizeBytes, size_t offset = 0, hipMemcpyKind kind = hipMemcpyDeviceToHost) +try: (hipMemcpyFromSymbol:=dll.hipMemcpyFromSymbol).restype, hipMemcpyFromSymbol.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipMemcpyFromSymbolAsync(void *dst, const void *symbol, size_t sizeBytes, size_t offset, hipMemcpyKind kind, hipStream_t stream = 0) +try: (hipMemcpyFromSymbolAsync:=dll.hipMemcpyFromSymbolAsync).restype, hipMemcpyFromSymbolAsync.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyAsync(void *dst, const void *src, size_t sizeBytes, hipMemcpyKind kind, hipStream_t stream = 0) +try: (hipMemcpyAsync:=dll.hipMemcpyAsync).restype, hipMemcpyAsync.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_void_p, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemset(void *dst, int value, size_t sizeBytes) +try: (hipMemset:=dll.hipMemset).restype, hipMemset.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_int32, size_t] +except AttributeError: pass + +# hipError_t hipMemsetD8(hipDeviceptr_t dest, unsigned char value, size_t count) +try: (hipMemsetD8:=dll.hipMemsetD8).restype, hipMemsetD8.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_ubyte, size_t] +except AttributeError: pass + +# hipError_t hipMemsetD8Async(hipDeviceptr_t dest, unsigned char value, size_t count, hipStream_t stream = 0) +try: (hipMemsetD8Async:=dll.hipMemsetD8Async).restype, hipMemsetD8Async.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_ubyte, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemsetD16(hipDeviceptr_t dest, unsigned short value, size_t count) +try: (hipMemsetD16:=dll.hipMemsetD16).restype, hipMemsetD16.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_uint16, size_t] +except AttributeError: pass + +# hipError_t hipMemsetD16Async(hipDeviceptr_t dest, unsigned short value, size_t count, hipStream_t stream = 0) +try: (hipMemsetD16Async:=dll.hipMemsetD16Async).restype, hipMemsetD16Async.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_uint16, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemsetD32(hipDeviceptr_t dest, int value, size_t count) +try: (hipMemsetD32:=dll.hipMemsetD32).restype, hipMemsetD32.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_int32, size_t] +except AttributeError: pass + +# hipError_t hipMemsetAsync(void *dst, int value, size_t sizeBytes, hipStream_t stream = 0) +try: (hipMemsetAsync:=dll.hipMemsetAsync).restype, hipMemsetAsync.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_int32, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemsetD32Async(hipDeviceptr_t dst, int value, size_t count, hipStream_t stream = 0) +try: (hipMemsetD32Async:=dll.hipMemsetD32Async).restype, hipMemsetD32Async.argtypes = hipError_t, [hipDeviceptr_t, ctypes.c_int32, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemset2D(void *dst, size_t pitch, int value, size_t width, size_t height) +try: (hipMemset2D:=dll.hipMemset2D).restype, hipMemset2D.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.c_int32, size_t, size_t] +except AttributeError: pass + +# hipError_t hipMemset2DAsync(void *dst, size_t pitch, int value, size_t width, size_t height, hipStream_t stream = 0) +try: (hipMemset2DAsync:=dll.hipMemset2DAsync).restype, hipMemset2DAsync.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.c_int32, size_t, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemset3D(hipPitchedPtr pitchedDevPtr, int value, hipExtent extent) +try: (hipMemset3D:=dll.hipMemset3D).restype, hipMemset3D.argtypes = hipError_t, [hipPitchedPtr, ctypes.c_int32, hipExtent] +except AttributeError: pass + +# hipError_t hipMemset3DAsync(hipPitchedPtr pitchedDevPtr, int value, hipExtent extent, hipStream_t stream = 0) +try: (hipMemset3DAsync:=dll.hipMemset3DAsync).restype, hipMemset3DAsync.argtypes = hipError_t, [hipPitchedPtr, ctypes.c_int32, hipExtent, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemGetInfo(size_t *free, size_t *total) +try: (hipMemGetInfo:=dll.hipMemGetInfo).restype, hipMemGetInfo.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipMemPtrGetInfo(void *ptr, size_t *size) +try: (hipMemPtrGetInfo:=dll.hipMemPtrGetInfo).restype, hipMemPtrGetInfo.argtypes = hipError_t, [ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipMallocArray(hipArray_t *array, const hipChannelFormatDesc *desc, size_t width, size_t height = 0, unsigned int flags = 0) +try: (hipMallocArray:=dll.hipMallocArray).restype, hipMallocArray.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), ctypes.POINTER(hipChannelFormatDesc), size_t, size_t, ctypes.c_uint32] +except AttributeError: pass + +class HIP_ARRAY_DESCRIPTOR(Struct): pass +HIP_ARRAY_DESCRIPTOR._fields_ = [ + ('Width', size_t), + ('Height', size_t), + ('Format', hipArray_Format), + ('NumChannels', ctypes.c_uint32), ] +# hipError_t hipArrayCreate(hipArray_t *pHandle, const HIP_ARRAY_DESCRIPTOR *pAllocateArray) +try: (hipArrayCreate:=dll.hipArrayCreate).restype, hipArrayCreate.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), ctypes.POINTER(HIP_ARRAY_DESCRIPTOR)] +except AttributeError: pass -try: - hipModuleGetTexRef = _libraries['libamdhip64.so'].hipModuleGetTexRef - hipModuleGetTexRef.restype = hipError_t - hipModuleGetTexRef.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_textureReference)), hipModule_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hipModuleLoadData = _libraries['libamdhip64.so'].hipModuleLoadData - hipModuleLoadData.restype = hipError_t - hipModuleLoadData.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModule_t)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipModuleLoadDataEx = _libraries['libamdhip64.so'].hipModuleLoadDataEx - hipModuleLoadDataEx.restype = hipError_t - hipModuleLoadDataEx.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipModule_t)), ctypes.POINTER(None), ctypes.c_uint32, ctypes.POINTER(hipJitOption), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hipModuleLaunchKernel = _libraries['libamdhip64.so'].hipModuleLaunchKernel - hipModuleLaunchKernel.restype = hipError_t - hipModuleLaunchKernel.argtypes = [hipFunction_t, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, hipStream_t, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hipModuleLaunchCooperativeKernel = _libraries['libamdhip64.so'].hipModuleLaunchCooperativeKernel - hipModuleLaunchCooperativeKernel.restype = hipError_t - hipModuleLaunchCooperativeKernel.argtypes = [hipFunction_t, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, hipStream_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hipModuleLaunchCooperativeKernelMultiDevice = _libraries['libamdhip64.so'].hipModuleLaunchCooperativeKernelMultiDevice - hipModuleLaunchCooperativeKernelMultiDevice.restype = hipError_t - hipModuleLaunchCooperativeKernelMultiDevice.argtypes = [ctypes.POINTER(struct_hipFunctionLaunchParams_t), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipLaunchCooperativeKernel = _libraries['libamdhip64.so'].hipLaunchCooperativeKernel - hipLaunchCooperativeKernel.restype = hipError_t - hipLaunchCooperativeKernel.argtypes = [ctypes.POINTER(None), dim3, dim3, ctypes.POINTER(ctypes.POINTER(None)), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipLaunchCooperativeKernelMultiDevice = _libraries['libamdhip64.so'].hipLaunchCooperativeKernelMultiDevice - hipLaunchCooperativeKernelMultiDevice.restype = hipError_t - hipLaunchCooperativeKernelMultiDevice.argtypes = [ctypes.POINTER(struct_hipLaunchParams_t), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipExtLaunchMultiKernelMultiDevice = _libraries['libamdhip64.so'].hipExtLaunchMultiKernelMultiDevice - hipExtLaunchMultiKernelMultiDevice.restype = hipError_t - hipExtLaunchMultiKernelMultiDevice.argtypes = [ctypes.POINTER(struct_hipLaunchParams_t), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipModuleOccupancyMaxPotentialBlockSize = _libraries['libamdhip64.so'].hipModuleOccupancyMaxPotentialBlockSize - hipModuleOccupancyMaxPotentialBlockSize.restype = hipError_t - hipModuleOccupancyMaxPotentialBlockSize.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipFunction_t, size_t, ctypes.c_int32] -except AttributeError: - pass -try: - hipModuleOccupancyMaxPotentialBlockSizeWithFlags = _libraries['libamdhip64.so'].hipModuleOccupancyMaxPotentialBlockSizeWithFlags - hipModuleOccupancyMaxPotentialBlockSizeWithFlags.restype = hipError_t - hipModuleOccupancyMaxPotentialBlockSizeWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipFunction_t, size_t, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipModuleOccupancyMaxActiveBlocksPerMultiprocessor = _libraries['libamdhip64.so'].hipModuleOccupancyMaxActiveBlocksPerMultiprocessor - hipModuleOccupancyMaxActiveBlocksPerMultiprocessor.restype = hipError_t - hipModuleOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = [ctypes.POINTER(ctypes.c_int32), hipFunction_t, ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags = _libraries['libamdhip64.so'].hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags - hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.restype = hipError_t - hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), hipFunction_t, ctypes.c_int32, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipOccupancyMaxActiveBlocksPerMultiprocessor = _libraries['libamdhip64.so'].hipOccupancyMaxActiveBlocksPerMultiprocessor - hipOccupancyMaxActiveBlocksPerMultiprocessor.restype = hipError_t - hipOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(None), ctypes.c_int32, size_t] -except AttributeError: - pass -try: - hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags = _libraries['libamdhip64.so'].hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags - hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.restype = hipError_t - hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(None), ctypes.c_int32, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipOccupancyMaxPotentialBlockSize = _libraries['libamdhip64.so'].hipOccupancyMaxPotentialBlockSize - hipOccupancyMaxPotentialBlockSize.restype = hipError_t - hipOccupancyMaxPotentialBlockSize.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - hipProfilerStart = _libraries['libamdhip64.so'].hipProfilerStart - hipProfilerStart.restype = hipError_t - hipProfilerStart.argtypes = [] -except AttributeError: - pass -try: - hipProfilerStop = _libraries['libamdhip64.so'].hipProfilerStop - hipProfilerStop.restype = hipError_t - hipProfilerStop.argtypes = [] -except AttributeError: - pass -try: - hipConfigureCall = _libraries['libamdhip64.so'].hipConfigureCall - hipConfigureCall.restype = hipError_t - hipConfigureCall.argtypes = [dim3, dim3, size_t, hipStream_t] -except AttributeError: - pass -try: - hipSetupArgument = _libraries['libamdhip64.so'].hipSetupArgument - hipSetupArgument.restype = hipError_t - hipSetupArgument.argtypes = [ctypes.POINTER(None), size_t, size_t] -except AttributeError: - pass -try: - hipLaunchByPtr = _libraries['libamdhip64.so'].hipLaunchByPtr - hipLaunchByPtr.restype = hipError_t - hipLaunchByPtr.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - __hipPushCallConfiguration = _libraries['libamdhip64.so'].__hipPushCallConfiguration - __hipPushCallConfiguration.restype = hipError_t - __hipPushCallConfiguration.argtypes = [dim3, dim3, size_t, hipStream_t] -except AttributeError: - pass -try: - __hipPopCallConfiguration = _libraries['libamdhip64.so'].__hipPopCallConfiguration - __hipPopCallConfiguration.restype = hipError_t - __hipPopCallConfiguration.argtypes = [ctypes.POINTER(struct_dim3), ctypes.POINTER(struct_dim3), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_ihipStream_t))] -except AttributeError: - pass -try: - hipLaunchKernel = _libraries['libamdhip64.so'].hipLaunchKernel - hipLaunchKernel.restype = hipError_t - hipLaunchKernel.argtypes = [ctypes.POINTER(None), dim3, dim3, ctypes.POINTER(ctypes.POINTER(None)), size_t, hipStream_t] -except AttributeError: - pass -try: - hipLaunchHostFunc = _libraries['libamdhip64.so'].hipLaunchHostFunc - hipLaunchHostFunc.restype = hipError_t - hipLaunchHostFunc.argtypes = [hipStream_t, hipHostFn_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDrvMemcpy2DUnaligned = _libraries['libamdhip64.so'].hipDrvMemcpy2DUnaligned - hipDrvMemcpy2DUnaligned.restype = hipError_t - hipDrvMemcpy2DUnaligned.argtypes = [ctypes.POINTER(struct_hip_Memcpy2D)] -except AttributeError: - pass -try: - hipExtLaunchKernel = _libraries['libamdhip64.so'].hipExtLaunchKernel - hipExtLaunchKernel.restype = hipError_t - hipExtLaunchKernel.argtypes = [ctypes.POINTER(None), dim3, dim3, ctypes.POINTER(ctypes.POINTER(None)), size_t, hipStream_t, hipEvent_t, hipEvent_t, ctypes.c_int32] -except AttributeError: - pass -class struct_hipTextureDesc(Structure): - pass +# hipError_t hipArrayDestroy(hipArray_t array) +try: (hipArrayDestroy:=dll.hipArrayDestroy).restype, hipArrayDestroy.argtypes = hipError_t, [hipArray_t] +except AttributeError: pass -struct_hipTextureDesc._pack_ = 1 # source:False -struct_hipTextureDesc._fields_ = [ - ('addressMode', hipTextureAddressMode * 3), - ('filterMode', hipTextureFilterMode), - ('readMode', hipTextureReadMode), - ('sRGB', ctypes.c_int32), - ('borderColor', ctypes.c_float * 4), - ('normalizedCoords', ctypes.c_int32), - ('maxAnisotropy', ctypes.c_uint32), - ('mipmapFilterMode', hipTextureFilterMode), - ('mipmapLevelBias', ctypes.c_float), - ('minMipmapLevelClamp', ctypes.c_float), - ('maxMipmapLevelClamp', ctypes.c_float), +class HIP_ARRAY3D_DESCRIPTOR(Struct): pass +HIP_ARRAY3D_DESCRIPTOR._fields_ = [ + ('Width', size_t), + ('Height', size_t), + ('Depth', size_t), + ('Format', hipArray_Format), + ('NumChannels', ctypes.c_uint32), + ('Flags', ctypes.c_uint32), ] +# hipError_t hipArray3DCreate(hipArray_t *array, const HIP_ARRAY3D_DESCRIPTOR *pAllocateArray) +try: (hipArray3DCreate:=dll.hipArray3DCreate).restype, hipArray3DCreate.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), ctypes.POINTER(HIP_ARRAY3D_DESCRIPTOR)] +except AttributeError: pass -try: - hipCreateTextureObject = _libraries['libamdhip64.so'].hipCreateTextureObject - hipCreateTextureObject.restype = hipError_t - hipCreateTextureObject.argtypes = [ctypes.POINTER(ctypes.POINTER(struct___hip_texture)), ctypes.POINTER(struct_hipResourceDesc), ctypes.POINTER(struct_hipTextureDesc), ctypes.POINTER(struct_hipResourceViewDesc)] -except AttributeError: - pass -hipTextureObject_t = ctypes.POINTER(struct___hip_texture) -try: - hipDestroyTextureObject = _libraries['libamdhip64.so'].hipDestroyTextureObject - hipDestroyTextureObject.restype = hipError_t - hipDestroyTextureObject.argtypes = [hipTextureObject_t] -except AttributeError: - pass -try: - hipGetChannelDesc = _libraries['libamdhip64.so'].hipGetChannelDesc - hipGetChannelDesc.restype = hipError_t - hipGetChannelDesc.argtypes = [ctypes.POINTER(struct_hipChannelFormatDesc), hipArray_const_t] -except AttributeError: - pass -try: - hipGetTextureObjectResourceDesc = _libraries['libamdhip64.so'].hipGetTextureObjectResourceDesc - hipGetTextureObjectResourceDesc.restype = hipError_t - hipGetTextureObjectResourceDesc.argtypes = [ctypes.POINTER(struct_hipResourceDesc), hipTextureObject_t] -except AttributeError: - pass -try: - hipGetTextureObjectResourceViewDesc = _libraries['libamdhip64.so'].hipGetTextureObjectResourceViewDesc - hipGetTextureObjectResourceViewDesc.restype = hipError_t - hipGetTextureObjectResourceViewDesc.argtypes = [ctypes.POINTER(struct_hipResourceViewDesc), hipTextureObject_t] -except AttributeError: - pass -try: - hipGetTextureObjectTextureDesc = _libraries['libamdhip64.so'].hipGetTextureObjectTextureDesc - hipGetTextureObjectTextureDesc.restype = hipError_t - hipGetTextureObjectTextureDesc.argtypes = [ctypes.POINTER(struct_hipTextureDesc), hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectCreate = _libraries['libamdhip64.so'].hipTexObjectCreate - hipTexObjectCreate.restype = hipError_t - hipTexObjectCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct___hip_texture)), ctypes.POINTER(struct_HIP_RESOURCE_DESC_st), ctypes.POINTER(struct_HIP_TEXTURE_DESC_st), ctypes.POINTER(struct_HIP_RESOURCE_VIEW_DESC_st)] -except AttributeError: - pass -try: - hipTexObjectDestroy = _libraries['libamdhip64.so'].hipTexObjectDestroy - hipTexObjectDestroy.restype = hipError_t - hipTexObjectDestroy.argtypes = [hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectGetResourceDesc = _libraries['libamdhip64.so'].hipTexObjectGetResourceDesc - hipTexObjectGetResourceDesc.restype = hipError_t - hipTexObjectGetResourceDesc.argtypes = [ctypes.POINTER(struct_HIP_RESOURCE_DESC_st), hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectGetResourceViewDesc = _libraries['libamdhip64.so'].hipTexObjectGetResourceViewDesc - hipTexObjectGetResourceViewDesc.restype = hipError_t - hipTexObjectGetResourceViewDesc.argtypes = [ctypes.POINTER(struct_HIP_RESOURCE_VIEW_DESC_st), hipTextureObject_t] -except AttributeError: - pass -try: - hipTexObjectGetTextureDesc = _libraries['libamdhip64.so'].hipTexObjectGetTextureDesc - hipTexObjectGetTextureDesc.restype = hipError_t - hipTexObjectGetTextureDesc.argtypes = [ctypes.POINTER(struct_HIP_TEXTURE_DESC_st), hipTextureObject_t] -except AttributeError: - pass -try: - hipMallocMipmappedArray = _libraries['libamdhip64.so'].hipMallocMipmappedArray - hipMallocMipmappedArray.restype = hipError_t - hipMallocMipmappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), ctypes.POINTER(struct_hipChannelFormatDesc), struct_hipExtent, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipFreeMipmappedArray = _libraries['libamdhip64.so'].hipFreeMipmappedArray - hipFreeMipmappedArray.restype = hipError_t - hipFreeMipmappedArray.argtypes = [hipMipmappedArray_t] -except AttributeError: - pass -try: - hipGetMipmappedArrayLevel = _libraries['libamdhip64.so'].hipGetMipmappedArrayLevel - hipGetMipmappedArrayLevel.restype = hipError_t - hipGetMipmappedArrayLevel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), hipMipmappedArray_const_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipMipmappedArrayCreate = _libraries['libamdhip64.so'].hipMipmappedArrayCreate - hipMipmappedArrayCreate.restype = hipError_t - hipMipmappedArrayCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), ctypes.POINTER(struct_HIP_ARRAY3D_DESCRIPTOR), ctypes.c_uint32] -except AttributeError: - pass -try: - hipMipmappedArrayDestroy = _libraries['libamdhip64.so'].hipMipmappedArrayDestroy - hipMipmappedArrayDestroy.restype = hipError_t - hipMipmappedArrayDestroy.argtypes = [hipMipmappedArray_t] -except AttributeError: - pass -try: - hipMipmappedArrayGetLevel = _libraries['libamdhip64.so'].hipMipmappedArrayGetLevel - hipMipmappedArrayGetLevel.restype = hipError_t - hipMipmappedArrayGetLevel.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), hipMipmappedArray_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipBindTextureToMipmappedArray = _libraries['libamdhip64.so'].hipBindTextureToMipmappedArray - hipBindTextureToMipmappedArray.restype = hipError_t - hipBindTextureToMipmappedArray.argtypes = [ctypes.POINTER(struct_textureReference), hipMipmappedArray_const_t, ctypes.POINTER(struct_hipChannelFormatDesc)] -except AttributeError: - pass -try: - hipGetTextureReference = _libraries['libamdhip64.so'].hipGetTextureReference - hipGetTextureReference.restype = hipError_t - hipGetTextureReference.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_textureReference)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipTexRefSetAddressMode = _libraries['libamdhip64.so'].hipTexRefSetAddressMode - hipTexRefSetAddressMode.restype = hipError_t - hipTexRefSetAddressMode.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_int32, hipTextureAddressMode] -except AttributeError: - pass -try: - hipTexRefSetArray = _libraries['libamdhip64.so'].hipTexRefSetArray - hipTexRefSetArray.restype = hipError_t - hipTexRefSetArray.argtypes = [ctypes.POINTER(struct_textureReference), hipArray_const_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipTexRefSetFilterMode = _libraries['libamdhip64.so'].hipTexRefSetFilterMode - hipTexRefSetFilterMode.restype = hipError_t - hipTexRefSetFilterMode.argtypes = [ctypes.POINTER(struct_textureReference), hipTextureFilterMode] -except AttributeError: - pass -try: - hipTexRefSetFlags = _libraries['libamdhip64.so'].hipTexRefSetFlags - hipTexRefSetFlags.restype = hipError_t - hipTexRefSetFlags.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_uint32] -except AttributeError: - pass -try: - hipTexRefSetFormat = _libraries['libamdhip64.so'].hipTexRefSetFormat - hipTexRefSetFormat.restype = hipError_t - hipTexRefSetFormat.argtypes = [ctypes.POINTER(struct_textureReference), hipArray_Format, ctypes.c_int32] -except AttributeError: - pass -try: - hipBindTexture = _libraries['libamdhip64.so'].hipBindTexture - hipBindTexture.restype = hipError_t - hipBindTexture.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference), ctypes.POINTER(None), ctypes.POINTER(struct_hipChannelFormatDesc), size_t] -except AttributeError: - pass -try: - hipBindTexture2D = _libraries['libamdhip64.so'].hipBindTexture2D - hipBindTexture2D.restype = hipError_t - hipBindTexture2D.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference), ctypes.POINTER(None), ctypes.POINTER(struct_hipChannelFormatDesc), size_t, size_t, size_t] -except AttributeError: - pass -try: - hipBindTextureToArray = _libraries['libamdhip64.so'].hipBindTextureToArray - hipBindTextureToArray.restype = hipError_t - hipBindTextureToArray.argtypes = [ctypes.POINTER(struct_textureReference), hipArray_const_t, ctypes.POINTER(struct_hipChannelFormatDesc)] -except AttributeError: - pass -try: - hipGetTextureAlignmentOffset = _libraries['libamdhip64.so'].hipGetTextureAlignmentOffset - hipGetTextureAlignmentOffset.restype = hipError_t - hipGetTextureAlignmentOffset.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipUnbindTexture = _libraries['libamdhip64.so'].hipUnbindTexture - hipUnbindTexture.restype = hipError_t - hipUnbindTexture.argtypes = [ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetAddress = _libraries['libamdhip64.so'].hipTexRefGetAddress - hipTexRefGetAddress.restype = hipError_t - hipTexRefGetAddress.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetAddressMode = _libraries['libamdhip64.so'].hipTexRefGetAddressMode - hipTexRefGetAddressMode.restype = hipError_t - hipTexRefGetAddressMode.argtypes = [ctypes.POINTER(hipTextureAddressMode), ctypes.POINTER(struct_textureReference), ctypes.c_int32] -except AttributeError: - pass -try: - hipTexRefGetFilterMode = _libraries['libamdhip64.so'].hipTexRefGetFilterMode - hipTexRefGetFilterMode.restype = hipError_t - hipTexRefGetFilterMode.argtypes = [ctypes.POINTER(hipTextureFilterMode), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetFlags = _libraries['libamdhip64.so'].hipTexRefGetFlags - hipTexRefGetFlags.restype = hipError_t - hipTexRefGetFlags.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetFormat = _libraries['libamdhip64.so'].hipTexRefGetFormat - hipTexRefGetFormat.restype = hipError_t - hipTexRefGetFormat.argtypes = [ctypes.POINTER(hipArray_Format), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMaxAnisotropy = _libraries['libamdhip64.so'].hipTexRefGetMaxAnisotropy - hipTexRefGetMaxAnisotropy.restype = hipError_t - hipTexRefGetMaxAnisotropy.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipmapFilterMode = _libraries['libamdhip64.so'].hipTexRefGetMipmapFilterMode - hipTexRefGetMipmapFilterMode.restype = hipError_t - hipTexRefGetMipmapFilterMode.argtypes = [ctypes.POINTER(hipTextureFilterMode), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipmapLevelBias = _libraries['libamdhip64.so'].hipTexRefGetMipmapLevelBias - hipTexRefGetMipmapLevelBias.restype = hipError_t - hipTexRefGetMipmapLevelBias.argtypes = [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipmapLevelClamp = _libraries['libamdhip64.so'].hipTexRefGetMipmapLevelClamp - hipTexRefGetMipmapLevelClamp.restype = hipError_t - hipTexRefGetMipmapLevelClamp.argtypes = [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(ctypes.c_float), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefGetMipMappedArray = _libraries['FIXME_STUB'].hipTexRefGetMipMappedArray - hipTexRefGetMipMappedArray.restype = hipError_t - hipTexRefGetMipMappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipMipmappedArray)), ctypes.POINTER(struct_textureReference)] -except AttributeError: - pass -try: - hipTexRefSetAddress = _libraries['libamdhip64.so'].hipTexRefSetAddress - hipTexRefSetAddress.restype = hipError_t - hipTexRefSetAddress.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_textureReference), hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipTexRefSetAddress2D = _libraries['libamdhip64.so'].hipTexRefSetAddress2D - hipTexRefSetAddress2D.restype = hipError_t - hipTexRefSetAddress2D.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.POINTER(struct_HIP_ARRAY_DESCRIPTOR), hipDeviceptr_t, size_t] -except AttributeError: - pass -try: - hipTexRefSetMaxAnisotropy = _libraries['libamdhip64.so'].hipTexRefSetMaxAnisotropy - hipTexRefSetMaxAnisotropy.restype = hipError_t - hipTexRefSetMaxAnisotropy.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_uint32] -except AttributeError: - pass -try: - hipTexRefSetBorderColor = _libraries['libamdhip64.so'].hipTexRefSetBorderColor - hipTexRefSetBorderColor.restype = hipError_t - hipTexRefSetBorderColor.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.POINTER(ctypes.c_float)] -except AttributeError: - pass -try: - hipTexRefSetMipmapFilterMode = _libraries['libamdhip64.so'].hipTexRefSetMipmapFilterMode - hipTexRefSetMipmapFilterMode.restype = hipError_t - hipTexRefSetMipmapFilterMode.argtypes = [ctypes.POINTER(struct_textureReference), hipTextureFilterMode] -except AttributeError: - pass -try: - hipTexRefSetMipmapLevelBias = _libraries['libamdhip64.so'].hipTexRefSetMipmapLevelBias - hipTexRefSetMipmapLevelBias.restype = hipError_t - hipTexRefSetMipmapLevelBias.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_float] -except AttributeError: - pass -try: - hipTexRefSetMipmapLevelClamp = _libraries['libamdhip64.so'].hipTexRefSetMipmapLevelClamp - hipTexRefSetMipmapLevelClamp.restype = hipError_t - hipTexRefSetMipmapLevelClamp.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - hipTexRefSetMipmappedArray = _libraries['libamdhip64.so'].hipTexRefSetMipmappedArray - hipTexRefSetMipmappedArray.restype = hipError_t - hipTexRefSetMipmappedArray.argtypes = [ctypes.POINTER(struct_textureReference), ctypes.POINTER(struct_hipMipmappedArray), ctypes.c_uint32] -except AttributeError: - pass -try: - hipApiName = _libraries['libamdhip64.so'].hipApiName - hipApiName.restype = ctypes.POINTER(ctypes.c_char) - hipApiName.argtypes = [uint32_t] -except AttributeError: - pass -try: - hipKernelNameRef = _libraries['libamdhip64.so'].hipKernelNameRef - hipKernelNameRef.restype = ctypes.POINTER(ctypes.c_char) - hipKernelNameRef.argtypes = [hipFunction_t] -except AttributeError: - pass -try: - hipKernelNameRefByPtr = _libraries['libamdhip64.so'].hipKernelNameRefByPtr - hipKernelNameRefByPtr.restype = ctypes.POINTER(ctypes.c_char) - hipKernelNameRefByPtr.argtypes = [ctypes.POINTER(None), hipStream_t] -except AttributeError: - pass -try: - hipGetStreamDeviceId = _libraries['libamdhip64.so'].hipGetStreamDeviceId - hipGetStreamDeviceId.restype = ctypes.c_int32 - hipGetStreamDeviceId.argtypes = [hipStream_t] -except AttributeError: - pass -try: - hipStreamBeginCapture = _libraries['libamdhip64.so'].hipStreamBeginCapture - hipStreamBeginCapture.restype = hipError_t - hipStreamBeginCapture.argtypes = [hipStream_t, hipStreamCaptureMode] -except AttributeError: - pass -try: - hipStreamEndCapture = _libraries['libamdhip64.so'].hipStreamEndCapture - hipStreamEndCapture.restype = hipError_t - hipStreamEndCapture.argtypes = [hipStream_t, ctypes.POINTER(ctypes.POINTER(struct_ihipGraph))] -except AttributeError: - pass -try: - hipStreamGetCaptureInfo = _libraries['libamdhip64.so'].hipStreamGetCaptureInfo - hipStreamGetCaptureInfo.restype = hipError_t - hipStreamGetCaptureInfo.argtypes = [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipStreamGetCaptureInfo_v2 = _libraries['libamdhip64.so'].hipStreamGetCaptureInfo_v2 - hipStreamGetCaptureInfo_v2.restype = hipError_t - hipStreamGetCaptureInfo_v2.argtypes = [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(struct_ihipGraph)), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode))), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipStreamIsCapturing = _libraries['libamdhip64.so'].hipStreamIsCapturing - hipStreamIsCapturing.restype = hipError_t - hipStreamIsCapturing.argtypes = [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus)] -except AttributeError: - pass -try: - hipStreamUpdateCaptureDependencies = _libraries['libamdhip64.so'].hipStreamUpdateCaptureDependencies - hipStreamUpdateCaptureDependencies.restype = hipError_t - hipStreamUpdateCaptureDependencies.argtypes = [hipStream_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipThreadExchangeStreamCaptureMode = _libraries['libamdhip64.so'].hipThreadExchangeStreamCaptureMode - hipThreadExchangeStreamCaptureMode.restype = hipError_t - hipThreadExchangeStreamCaptureMode.argtypes = [ctypes.POINTER(hipStreamCaptureMode)] -except AttributeError: - pass -try: - hipGraphCreate = _libraries['libamdhip64.so'].hipGraphCreate - hipGraphCreate.restype = hipError_t - hipGraphCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipGraph)), ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphDestroy = _libraries['libamdhip64.so'].hipGraphDestroy - hipGraphDestroy.restype = hipError_t - hipGraphDestroy.argtypes = [hipGraph_t] -except AttributeError: - pass -try: - hipGraphAddDependencies = _libraries['libamdhip64.so'].hipGraphAddDependencies - hipGraphAddDependencies.restype = hipError_t - hipGraphAddDependencies.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t] -except AttributeError: - pass -try: - hipGraphRemoveDependencies = _libraries['libamdhip64.so'].hipGraphRemoveDependencies - hipGraphRemoveDependencies.restype = hipError_t - hipGraphRemoveDependencies.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t] -except AttributeError: - pass -try: - hipGraphGetEdges = _libraries['libamdhip64.so'].hipGraphGetEdges - hipGraphGetEdges.restype = hipError_t - hipGraphGetEdges.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphGetNodes = _libraries['libamdhip64.so'].hipGraphGetNodes - hipGraphGetNodes.restype = hipError_t - hipGraphGetNodes.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphGetRootNodes = _libraries['libamdhip64.so'].hipGraphGetRootNodes - hipGraphGetRootNodes.restype = hipError_t - hipGraphGetRootNodes.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphNodeGetDependencies = _libraries['libamdhip64.so'].hipGraphNodeGetDependencies - hipGraphNodeGetDependencies.restype = hipError_t - hipGraphNodeGetDependencies.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphNodeGetDependentNodes = _libraries['libamdhip64.so'].hipGraphNodeGetDependentNodes - hipGraphNodeGetDependentNodes.restype = hipError_t - hipGraphNodeGetDependentNodes.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hipGraphNodeGetType = _libraries['libamdhip64.so'].hipGraphNodeGetType - hipGraphNodeGetType.restype = hipError_t - hipGraphNodeGetType.argtypes = [hipGraphNode_t, ctypes.POINTER(hipGraphNodeType)] -except AttributeError: - pass -try: - hipGraphDestroyNode = _libraries['libamdhip64.so'].hipGraphDestroyNode - hipGraphDestroyNode.restype = hipError_t - hipGraphDestroyNode.argtypes = [hipGraphNode_t] -except AttributeError: - pass -try: - hipGraphClone = _libraries['libamdhip64.so'].hipGraphClone - hipGraphClone.restype = hipError_t - hipGraphClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipGraph)), hipGraph_t] -except AttributeError: - pass -try: - hipGraphNodeFindInClone = _libraries['libamdhip64.so'].hipGraphNodeFindInClone - hipGraphNodeFindInClone.restype = hipError_t - hipGraphNodeFindInClone.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraphNode_t, hipGraph_t] -except AttributeError: - pass -try: - hipGraphInstantiate = _libraries['libamdhip64.so'].hipGraphInstantiate - hipGraphInstantiate.restype = hipError_t - hipGraphInstantiate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphExec)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - hipGraphInstantiateWithFlags = _libraries['libamdhip64.so'].hipGraphInstantiateWithFlags - hipGraphInstantiateWithFlags.restype = hipError_t - hipGraphInstantiateWithFlags.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphExec)), hipGraph_t, ctypes.c_uint64] -except AttributeError: - pass -try: - hipGraphLaunch = _libraries['libamdhip64.so'].hipGraphLaunch - hipGraphLaunch.restype = hipError_t - hipGraphLaunch.argtypes = [hipGraphExec_t, hipStream_t] -except AttributeError: - pass -try: - hipGraphUpload = _libraries['libamdhip64.so'].hipGraphUpload - hipGraphUpload.restype = hipError_t - hipGraphUpload.argtypes = [hipGraphExec_t, hipStream_t] -except AttributeError: - pass -try: - hipGraphExecDestroy = _libraries['libamdhip64.so'].hipGraphExecDestroy - hipGraphExecDestroy.restype = hipError_t - hipGraphExecDestroy.argtypes = [hipGraphExec_t] -except AttributeError: - pass -try: - hipGraphExecUpdate = _libraries['libamdhip64.so'].hipGraphExecUpdate - hipGraphExecUpdate.restype = hipError_t - hipGraphExecUpdate.argtypes = [hipGraphExec_t, hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), ctypes.POINTER(hipGraphExecUpdateResult)] -except AttributeError: - pass -try: - hipGraphAddKernelNode = _libraries['libamdhip64.so'].hipGraphAddKernelNode - hipGraphAddKernelNode.restype = hipError_t - hipGraphAddKernelNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipGraphKernelNodeGetParams = _libraries['libamdhip64.so'].hipGraphKernelNodeGetParams - hipGraphKernelNodeGetParams.restype = hipError_t - hipGraphKernelNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipGraphKernelNodeSetParams = _libraries['libamdhip64.so'].hipGraphKernelNodeSetParams - hipGraphKernelNodeSetParams.restype = hipError_t - hipGraphKernelNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipGraphExecKernelNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecKernelNodeSetParams - hipGraphExecKernelNodeSetParams.restype = hipError_t - hipGraphExecKernelNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipKernelNodeParams)] -except AttributeError: - pass -try: - hipDrvGraphAddMemcpyNode = _libraries['FIXME_STUB'].hipDrvGraphAddMemcpyNode - hipDrvGraphAddMemcpyNode.restype = hipError_t - hipDrvGraphAddMemcpyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_HIP_MEMCPY3D), hipCtx_t] -except AttributeError: - pass -try: - hipGraphAddMemcpyNode = _libraries['libamdhip64.so'].hipGraphAddMemcpyNode - hipGraphAddMemcpyNode.restype = hipError_t - hipGraphAddMemcpyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphMemcpyNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemcpyNodeGetParams - hipGraphMemcpyNodeGetParams.restype = hipError_t - hipGraphMemcpyNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParams = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParams - hipGraphMemcpyNodeSetParams.restype = hipError_t - hipGraphMemcpyNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphKernelNodeSetAttribute = _libraries['libamdhip64.so'].hipGraphKernelNodeSetAttribute - hipGraphKernelNodeSetAttribute.restype = hipError_t - hipGraphKernelNodeSetAttribute.argtypes = [hipGraphNode_t, hipKernelNodeAttrID, ctypes.POINTER(union_hipKernelNodeAttrValue)] -except AttributeError: - pass -try: - hipGraphKernelNodeGetAttribute = _libraries['libamdhip64.so'].hipGraphKernelNodeGetAttribute - hipGraphKernelNodeGetAttribute.restype = hipError_t - hipGraphKernelNodeGetAttribute.argtypes = [hipGraphNode_t, hipKernelNodeAttrID, ctypes.POINTER(union_hipKernelNodeAttrValue)] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParams - hipGraphExecMemcpyNodeSetParams.restype = hipError_t - hipGraphExecMemcpyNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipMemcpy3DParms)] -except AttributeError: - pass -try: - hipGraphAddMemcpyNode1D = _libraries['libamdhip64.so'].hipGraphAddMemcpyNode1D - hipGraphAddMemcpyNode1D.restype = hipError_t - hipGraphAddMemcpyNode1D.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParams1D = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParams1D - hipGraphMemcpyNodeSetParams1D.restype = hipError_t - hipGraphMemcpyNodeSetParams1D.argtypes = [hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParams1D = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParams1D - hipGraphExecMemcpyNodeSetParams1D.restype = hipError_t - hipGraphExecMemcpyNodeSetParams1D.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphAddMemcpyNodeFromSymbol = _libraries['libamdhip64.so'].hipGraphAddMemcpyNodeFromSymbol - hipGraphAddMemcpyNodeFromSymbol.restype = hipError_t - hipGraphAddMemcpyNodeFromSymbol.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParamsFromSymbol = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParamsFromSymbol - hipGraphMemcpyNodeSetParamsFromSymbol.restype = hipError_t - hipGraphMemcpyNodeSetParamsFromSymbol.argtypes = [hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParamsFromSymbol = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParamsFromSymbol - hipGraphExecMemcpyNodeSetParamsFromSymbol.restype = hipError_t - hipGraphExecMemcpyNodeSetParamsFromSymbol.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphAddMemcpyNodeToSymbol = _libraries['libamdhip64.so'].hipGraphAddMemcpyNodeToSymbol - hipGraphAddMemcpyNodeToSymbol.restype = hipError_t - hipGraphAddMemcpyNodeToSymbol.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphMemcpyNodeSetParamsToSymbol = _libraries['libamdhip64.so'].hipGraphMemcpyNodeSetParamsToSymbol - hipGraphMemcpyNodeSetParamsToSymbol.restype = hipError_t - hipGraphMemcpyNodeSetParamsToSymbol.argtypes = [hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphExecMemcpyNodeSetParamsToSymbol = _libraries['libamdhip64.so'].hipGraphExecMemcpyNodeSetParamsToSymbol - hipGraphExecMemcpyNodeSetParamsToSymbol.restype = hipError_t - hipGraphExecMemcpyNodeSetParamsToSymbol.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, hipMemcpyKind] -except AttributeError: - pass -try: - hipGraphAddMemsetNode = _libraries['libamdhip64.so'].hipGraphAddMemsetNode - hipGraphAddMemsetNode.restype = hipError_t - hipGraphAddMemsetNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphMemsetNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemsetNodeGetParams - hipGraphMemsetNodeGetParams.restype = hipError_t - hipGraphMemsetNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphMemsetNodeSetParams = _libraries['libamdhip64.so'].hipGraphMemsetNodeSetParams - hipGraphMemsetNodeSetParams.restype = hipError_t - hipGraphMemsetNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphExecMemsetNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecMemsetNodeSetParams - hipGraphExecMemsetNodeSetParams.restype = hipError_t - hipGraphExecMemsetNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipMemsetParams)] -except AttributeError: - pass -try: - hipGraphAddHostNode = _libraries['libamdhip64.so'].hipGraphAddHostNode - hipGraphAddHostNode.restype = hipError_t - hipGraphAddHostNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphHostNodeGetParams = _libraries['libamdhip64.so'].hipGraphHostNodeGetParams - hipGraphHostNodeGetParams.restype = hipError_t - hipGraphHostNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphHostNodeSetParams = _libraries['libamdhip64.so'].hipGraphHostNodeSetParams - hipGraphHostNodeSetParams.restype = hipError_t - hipGraphHostNodeSetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphExecHostNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecHostNodeSetParams - hipGraphExecHostNodeSetParams.restype = hipError_t - hipGraphExecHostNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(struct_hipHostNodeParams)] -except AttributeError: - pass -try: - hipGraphAddChildGraphNode = _libraries['libamdhip64.so'].hipGraphAddChildGraphNode - hipGraphAddChildGraphNode.restype = hipError_t - hipGraphAddChildGraphNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, hipGraph_t] -except AttributeError: - pass -try: - hipGraphChildGraphNodeGetGraph = _libraries['libamdhip64.so'].hipGraphChildGraphNodeGetGraph - hipGraphChildGraphNodeGetGraph.restype = hipError_t - hipGraphChildGraphNodeGetGraph.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_ihipGraph))] -except AttributeError: - pass -try: - hipGraphExecChildGraphNodeSetParams = _libraries['libamdhip64.so'].hipGraphExecChildGraphNodeSetParams - hipGraphExecChildGraphNodeSetParams.restype = hipError_t - hipGraphExecChildGraphNodeSetParams.argtypes = [hipGraphExec_t, hipGraphNode_t, hipGraph_t] -except AttributeError: - pass -try: - hipGraphAddEmptyNode = _libraries['libamdhip64.so'].hipGraphAddEmptyNode - hipGraphAddEmptyNode.restype = hipError_t - hipGraphAddEmptyNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t] -except AttributeError: - pass -try: - hipGraphAddEventRecordNode = _libraries['libamdhip64.so'].hipGraphAddEventRecordNode - hipGraphAddEventRecordNode.restype = hipError_t - hipGraphAddEventRecordNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphEventRecordNodeGetEvent = _libraries['libamdhip64.so'].hipGraphEventRecordNodeGetEvent - hipGraphEventRecordNodeGetEvent.restype = hipError_t - hipGraphEventRecordNodeGetEvent.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t))] -except AttributeError: - pass -try: - hipGraphEventRecordNodeSetEvent = _libraries['libamdhip64.so'].hipGraphEventRecordNodeSetEvent - hipGraphEventRecordNodeSetEvent.restype = hipError_t - hipGraphEventRecordNodeSetEvent.argtypes = [hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphExecEventRecordNodeSetEvent = _libraries['libamdhip64.so'].hipGraphExecEventRecordNodeSetEvent - hipGraphExecEventRecordNodeSetEvent.restype = hipError_t - hipGraphExecEventRecordNodeSetEvent.argtypes = [hipGraphExec_t, hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphAddEventWaitNode = _libraries['libamdhip64.so'].hipGraphAddEventWaitNode - hipGraphAddEventWaitNode.restype = hipError_t - hipGraphAddEventWaitNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphEventWaitNodeGetEvent = _libraries['libamdhip64.so'].hipGraphEventWaitNodeGetEvent - hipGraphEventWaitNodeGetEvent.restype = hipError_t - hipGraphEventWaitNodeGetEvent.argtypes = [hipGraphNode_t, ctypes.POINTER(ctypes.POINTER(struct_ihipEvent_t))] -except AttributeError: - pass -try: - hipGraphEventWaitNodeSetEvent = _libraries['libamdhip64.so'].hipGraphEventWaitNodeSetEvent - hipGraphEventWaitNodeSetEvent.restype = hipError_t - hipGraphEventWaitNodeSetEvent.argtypes = [hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphExecEventWaitNodeSetEvent = _libraries['libamdhip64.so'].hipGraphExecEventWaitNodeSetEvent - hipGraphExecEventWaitNodeSetEvent.restype = hipError_t - hipGraphExecEventWaitNodeSetEvent.argtypes = [hipGraphExec_t, hipGraphNode_t, hipEvent_t] -except AttributeError: - pass -try: - hipGraphAddMemAllocNode = _libraries['libamdhip64.so'].hipGraphAddMemAllocNode - hipGraphAddMemAllocNode.restype = hipError_t - hipGraphAddMemAllocNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(struct_hipMemAllocNodeParams)] -except AttributeError: - pass -try: - hipGraphMemAllocNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemAllocNodeGetParams - hipGraphMemAllocNodeGetParams.restype = hipError_t - hipGraphMemAllocNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(struct_hipMemAllocNodeParams)] -except AttributeError: - pass -try: - hipGraphAddMemFreeNode = _libraries['libamdhip64.so'].hipGraphAddMemFreeNode - hipGraphAddMemFreeNode.restype = hipError_t - hipGraphAddMemFreeNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), hipGraph_t, ctypes.POINTER(ctypes.POINTER(struct_hipGraphNode)), size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipGraphMemFreeNodeGetParams = _libraries['libamdhip64.so'].hipGraphMemFreeNodeGetParams - hipGraphMemFreeNodeGetParams.restype = hipError_t - hipGraphMemFreeNodeGetParams.argtypes = [hipGraphNode_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDeviceGetGraphMemAttribute = _libraries['libamdhip64.so'].hipDeviceGetGraphMemAttribute - hipDeviceGetGraphMemAttribute.restype = hipError_t - hipDeviceGetGraphMemAttribute.argtypes = [ctypes.c_int32, hipGraphMemAttributeType, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDeviceSetGraphMemAttribute = _libraries['libamdhip64.so'].hipDeviceSetGraphMemAttribute - hipDeviceSetGraphMemAttribute.restype = hipError_t - hipDeviceSetGraphMemAttribute.argtypes = [ctypes.c_int32, hipGraphMemAttributeType, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipDeviceGraphMemTrim = _libraries['libamdhip64.so'].hipDeviceGraphMemTrim - hipDeviceGraphMemTrim.restype = hipError_t - hipDeviceGraphMemTrim.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hipUserObjectCreate = _libraries['libamdhip64.so'].hipUserObjectCreate - hipUserObjectCreate.restype = hipError_t - hipUserObjectCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipUserObject)), ctypes.POINTER(None), hipHostFn_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipUserObjectRelease = _libraries['libamdhip64.so'].hipUserObjectRelease - hipUserObjectRelease.restype = hipError_t - hipUserObjectRelease.argtypes = [hipUserObject_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipUserObjectRetain = _libraries['libamdhip64.so'].hipUserObjectRetain - hipUserObjectRetain.restype = hipError_t - hipUserObjectRetain.argtypes = [hipUserObject_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphRetainUserObject = _libraries['libamdhip64.so'].hipGraphRetainUserObject - hipGraphRetainUserObject.restype = hipError_t - hipGraphRetainUserObject.argtypes = [hipGraph_t, hipUserObject_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphReleaseUserObject = _libraries['libamdhip64.so'].hipGraphReleaseUserObject - hipGraphReleaseUserObject.restype = hipError_t - hipGraphReleaseUserObject.argtypes = [hipGraph_t, hipUserObject_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphDebugDotPrint = _libraries['libamdhip64.so'].hipGraphDebugDotPrint - hipGraphDebugDotPrint.restype = hipError_t - hipGraphDebugDotPrint.argtypes = [hipGraph_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphKernelNodeCopyAttributes = _libraries['libamdhip64.so'].hipGraphKernelNodeCopyAttributes - hipGraphKernelNodeCopyAttributes.restype = hipError_t - hipGraphKernelNodeCopyAttributes.argtypes = [hipGraphNode_t, hipGraphNode_t] -except AttributeError: - pass -try: - hipGraphNodeSetEnabled = _libraries['libamdhip64.so'].hipGraphNodeSetEnabled - hipGraphNodeSetEnabled.restype = hipError_t - hipGraphNodeSetEnabled.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphNodeGetEnabled = _libraries['libamdhip64.so'].hipGraphNodeGetEnabled - hipGraphNodeGetEnabled.restype = hipError_t - hipGraphNodeGetEnabled.argtypes = [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hipMemAddressFree = _libraries['libamdhip64.so'].hipMemAddressFree - hipMemAddressFree.restype = hipError_t - hipMemAddressFree.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipMemAddressReserve = _libraries['libamdhip64.so'].hipMemAddressReserve - hipMemAddressReserve.restype = hipError_t - hipMemAddressReserve.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, size_t, ctypes.POINTER(None), ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemCreate = _libraries['libamdhip64.so'].hipMemCreate - hipMemCreate.restype = hipError_t - hipMemCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), size_t, ctypes.POINTER(struct_hipMemAllocationProp), ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemExportToShareableHandle = _libraries['libamdhip64.so'].hipMemExportToShareableHandle - hipMemExportToShareableHandle.restype = hipError_t - hipMemExportToShareableHandle.argtypes = [ctypes.POINTER(None), hipMemGenericAllocationHandle_t, hipMemAllocationHandleType, ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemGetAccess = _libraries['libamdhip64.so'].hipMemGetAccess - hipMemGetAccess.restype = hipError_t - hipMemGetAccess.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_hipMemLocation), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemGetAllocationGranularity = _libraries['libamdhip64.so'].hipMemGetAllocationGranularity - hipMemGetAllocationGranularity.restype = hipError_t - hipMemGetAllocationGranularity.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(struct_hipMemAllocationProp), hipMemAllocationGranularity_flags] -except AttributeError: - pass -try: - hipMemGetAllocationPropertiesFromHandle = _libraries['libamdhip64.so'].hipMemGetAllocationPropertiesFromHandle - hipMemGetAllocationPropertiesFromHandle.restype = hipError_t - hipMemGetAllocationPropertiesFromHandle.argtypes = [ctypes.POINTER(struct_hipMemAllocationProp), hipMemGenericAllocationHandle_t] -except AttributeError: - pass -try: - hipMemImportFromShareableHandle = _libraries['libamdhip64.so'].hipMemImportFromShareableHandle - hipMemImportFromShareableHandle.restype = hipError_t - hipMemImportFromShareableHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), ctypes.POINTER(None), hipMemAllocationHandleType] -except AttributeError: - pass -try: - hipMemMap = _libraries['libamdhip64.so'].hipMemMap - hipMemMap.restype = hipError_t - hipMemMap.argtypes = [ctypes.POINTER(None), size_t, size_t, hipMemGenericAllocationHandle_t, ctypes.c_uint64] -except AttributeError: - pass -try: - hipMemMapArrayAsync = _libraries['libamdhip64.so'].hipMemMapArrayAsync - hipMemMapArrayAsync.restype = hipError_t - hipMemMapArrayAsync.argtypes = [ctypes.POINTER(struct_hipArrayMapInfo), ctypes.c_uint32, hipStream_t] -except AttributeError: - pass -try: - hipMemRelease = _libraries['libamdhip64.so'].hipMemRelease - hipMemRelease.restype = hipError_t - hipMemRelease.argtypes = [hipMemGenericAllocationHandle_t] -except AttributeError: - pass -try: - hipMemRetainAllocationHandle = _libraries['libamdhip64.so'].hipMemRetainAllocationHandle - hipMemRetainAllocationHandle.restype = hipError_t - hipMemRetainAllocationHandle.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ihipMemGenericAllocationHandle)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hipMemSetAccess = _libraries['libamdhip64.so'].hipMemSetAccess - hipMemSetAccess.restype = hipError_t - hipMemSetAccess.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hipMemAccessDesc), size_t] -except AttributeError: - pass -try: - hipMemUnmap = _libraries['libamdhip64.so'].hipMemUnmap - hipMemUnmap.restype = hipError_t - hipMemUnmap.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hipGraphicsMapResources = _libraries['libamdhip64.so'].hipGraphicsMapResources - hipGraphicsMapResources.restype = hipError_t - hipGraphicsMapResources.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(struct__hipGraphicsResource)), hipStream_t] -except AttributeError: - pass -try: - hipGraphicsSubResourceGetMappedArray = _libraries['libamdhip64.so'].hipGraphicsSubResourceGetMappedArray - hipGraphicsSubResourceGetMappedArray.restype = hipError_t - hipGraphicsSubResourceGetMappedArray.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_hipArray)), hipGraphicsResource_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - hipGraphicsResourceGetMappedPointer = _libraries['libamdhip64.so'].hipGraphicsResourceGetMappedPointer - hipGraphicsResourceGetMappedPointer.restype = hipError_t - hipGraphicsResourceGetMappedPointer.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), hipGraphicsResource_t] -except AttributeError: - pass -try: - hipGraphicsUnmapResources = _libraries['libamdhip64.so'].hipGraphicsUnmapResources - hipGraphicsUnmapResources.restype = hipError_t - hipGraphicsUnmapResources.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(struct__hipGraphicsResource)), hipStream_t] -except AttributeError: - pass -try: - hipGraphicsUnregisterResource = _libraries['libamdhip64.so'].hipGraphicsUnregisterResource - hipGraphicsUnregisterResource.restype = hipError_t - hipGraphicsUnregisterResource.argtypes = [hipGraphicsResource_t] -except AttributeError: - pass -class struct___hip_surface(Structure): - pass +# hipError_t hipMalloc3D(hipPitchedPtr *pitchedDevPtr, hipExtent extent) +try: (hipMalloc3D:=dll.hipMalloc3D).restype, hipMalloc3D.argtypes = hipError_t, [ctypes.POINTER(hipPitchedPtr), hipExtent] +except AttributeError: pass -try: - hipCreateSurfaceObject = _libraries['libamdhip64.so'].hipCreateSurfaceObject - hipCreateSurfaceObject.restype = hipError_t - hipCreateSurfaceObject.argtypes = [ctypes.POINTER(ctypes.POINTER(struct___hip_surface)), ctypes.POINTER(struct_hipResourceDesc)] -except AttributeError: - pass -hipSurfaceObject_t = ctypes.POINTER(struct___hip_surface) -try: - hipDestroySurfaceObject = _libraries['libamdhip64.so'].hipDestroySurfaceObject - hipDestroySurfaceObject.restype = hipError_t - hipDestroySurfaceObject.argtypes = [hipSurfaceObject_t] -except AttributeError: - pass -try: - hipExtModuleLaunchKernel = _libraries['FIXME_STUB'].hipExtModuleLaunchKernel - hipExtModuleLaunchKernel.restype = hipError_t - hipExtModuleLaunchKernel.argtypes = [hipFunction_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, size_t, hipStream_t, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None)), hipEvent_t, hipEvent_t, uint32_t] -except AttributeError: - pass -try: - hipHccModuleLaunchKernel = _libraries['FIXME_STUB'].hipHccModuleLaunchKernel - hipHccModuleLaunchKernel.restype = hipError_t - hipHccModuleLaunchKernel.argtypes = [hipFunction_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, size_t, hipStream_t, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(None)), hipEvent_t, hipEvent_t] -except AttributeError: - pass +# hipError_t hipFreeArray(hipArray_t array) +try: (hipFreeArray:=dll.hipFreeArray).restype, hipFreeArray.argtypes = hipError_t, [hipArray_t] +except AttributeError: pass -# values for enumeration 'hiprtcResult' -hiprtcResult__enumvalues = { - 0: 'HIPRTC_SUCCESS', - 1: 'HIPRTC_ERROR_OUT_OF_MEMORY', - 2: 'HIPRTC_ERROR_PROGRAM_CREATION_FAILURE', - 3: 'HIPRTC_ERROR_INVALID_INPUT', - 4: 'HIPRTC_ERROR_INVALID_PROGRAM', - 5: 'HIPRTC_ERROR_INVALID_OPTION', - 6: 'HIPRTC_ERROR_COMPILATION', - 7: 'HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 8: 'HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 9: 'HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 10: 'HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 11: 'HIPRTC_ERROR_INTERNAL_ERROR', - 100: 'HIPRTC_ERROR_LINKING', -} -HIPRTC_SUCCESS = 0 -HIPRTC_ERROR_OUT_OF_MEMORY = 1 -HIPRTC_ERROR_PROGRAM_CREATION_FAILURE = 2 -HIPRTC_ERROR_INVALID_INPUT = 3 -HIPRTC_ERROR_INVALID_PROGRAM = 4 -HIPRTC_ERROR_INVALID_OPTION = 5 -HIPRTC_ERROR_COMPILATION = 6 -HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE = 7 -HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION = 8 -HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION = 9 -HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID = 10 -HIPRTC_ERROR_INTERNAL_ERROR = 11 -HIPRTC_ERROR_LINKING = 100 -hiprtcResult = ctypes.c_uint32 # enum +# hipError_t hipMalloc3DArray(hipArray_t *array, const struct hipChannelFormatDesc *desc, struct hipExtent extent, unsigned int flags) +try: (hipMalloc3DArray:=dll.hipMalloc3DArray).restype, hipMalloc3DArray.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), ctypes.POINTER(hipChannelFormatDesc), hipExtent, ctypes.c_uint32] +except AttributeError: pass -# values for enumeration 'hiprtcJIT_option' -hiprtcJIT_option__enumvalues = { - 0: 'HIPRTC_JIT_MAX_REGISTERS', - 1: 'HIPRTC_JIT_THREADS_PER_BLOCK', - 2: 'HIPRTC_JIT_WALL_TIME', - 3: 'HIPRTC_JIT_INFO_LOG_BUFFER', - 4: 'HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES', - 5: 'HIPRTC_JIT_ERROR_LOG_BUFFER', - 6: 'HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', - 7: 'HIPRTC_JIT_OPTIMIZATION_LEVEL', - 8: 'HIPRTC_JIT_TARGET_FROM_HIPCONTEXT', - 9: 'HIPRTC_JIT_TARGET', - 10: 'HIPRTC_JIT_FALLBACK_STRATEGY', - 11: 'HIPRTC_JIT_GENERATE_DEBUG_INFO', - 12: 'HIPRTC_JIT_LOG_VERBOSE', - 13: 'HIPRTC_JIT_GENERATE_LINE_INFO', - 14: 'HIPRTC_JIT_CACHE_MODE', - 15: 'HIPRTC_JIT_NEW_SM3X_OPT', - 16: 'HIPRTC_JIT_FAST_COMPILE', - 17: 'HIPRTC_JIT_GLOBAL_SYMBOL_NAMES', - 18: 'HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS', - 19: 'HIPRTC_JIT_GLOBAL_SYMBOL_COUNT', - 20: 'HIPRTC_JIT_LTO', - 21: 'HIPRTC_JIT_FTZ', - 22: 'HIPRTC_JIT_PREC_DIV', - 23: 'HIPRTC_JIT_PREC_SQRT', - 24: 'HIPRTC_JIT_FMA', - 25: 'HIPRTC_JIT_NUM_OPTIONS', - 10000: 'HIPRTC_JIT_IR_TO_ISA_OPT_EXT', - 10001: 'HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT', -} -HIPRTC_JIT_MAX_REGISTERS = 0 -HIPRTC_JIT_THREADS_PER_BLOCK = 1 -HIPRTC_JIT_WALL_TIME = 2 -HIPRTC_JIT_INFO_LOG_BUFFER = 3 -HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES = 4 -HIPRTC_JIT_ERROR_LOG_BUFFER = 5 -HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES = 6 -HIPRTC_JIT_OPTIMIZATION_LEVEL = 7 -HIPRTC_JIT_TARGET_FROM_HIPCONTEXT = 8 -HIPRTC_JIT_TARGET = 9 -HIPRTC_JIT_FALLBACK_STRATEGY = 10 -HIPRTC_JIT_GENERATE_DEBUG_INFO = 11 -HIPRTC_JIT_LOG_VERBOSE = 12 -HIPRTC_JIT_GENERATE_LINE_INFO = 13 -HIPRTC_JIT_CACHE_MODE = 14 -HIPRTC_JIT_NEW_SM3X_OPT = 15 -HIPRTC_JIT_FAST_COMPILE = 16 -HIPRTC_JIT_GLOBAL_SYMBOL_NAMES = 17 -HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS = 18 -HIPRTC_JIT_GLOBAL_SYMBOL_COUNT = 19 -HIPRTC_JIT_LTO = 20 -HIPRTC_JIT_FTZ = 21 -HIPRTC_JIT_PREC_DIV = 22 -HIPRTC_JIT_PREC_SQRT = 23 -HIPRTC_JIT_FMA = 24 -HIPRTC_JIT_NUM_OPTIONS = 25 -HIPRTC_JIT_IR_TO_ISA_OPT_EXT = 10000 -HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT = 10001 -hiprtcJIT_option = ctypes.c_uint32 # enum +# hipError_t hipArrayGetInfo(hipChannelFormatDesc *desc, hipExtent *extent, unsigned int *flags, hipArray_t array) +try: (hipArrayGetInfo:=dll.hipArrayGetInfo).restype, hipArrayGetInfo.argtypes = hipError_t, [ctypes.POINTER(hipChannelFormatDesc), ctypes.POINTER(hipExtent), ctypes.POINTER(ctypes.c_uint32), hipArray_t] +except AttributeError: pass -# values for enumeration 'hiprtcJITInputType' -hiprtcJITInputType__enumvalues = { - 0: 'HIPRTC_JIT_INPUT_CUBIN', - 1: 'HIPRTC_JIT_INPUT_PTX', - 2: 'HIPRTC_JIT_INPUT_FATBINARY', - 3: 'HIPRTC_JIT_INPUT_OBJECT', - 4: 'HIPRTC_JIT_INPUT_LIBRARY', - 5: 'HIPRTC_JIT_INPUT_NVVM', - 6: 'HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES', - 100: 'HIPRTC_JIT_INPUT_LLVM_BITCODE', - 101: 'HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE', - 102: 'HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE', - 9: 'HIPRTC_JIT_NUM_INPUT_TYPES', -} -HIPRTC_JIT_INPUT_CUBIN = 0 -HIPRTC_JIT_INPUT_PTX = 1 -HIPRTC_JIT_INPUT_FATBINARY = 2 -HIPRTC_JIT_INPUT_OBJECT = 3 -HIPRTC_JIT_INPUT_LIBRARY = 4 -HIPRTC_JIT_INPUT_NVVM = 5 -HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES = 6 -HIPRTC_JIT_INPUT_LLVM_BITCODE = 100 -HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE = 101 -HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE = 102 -HIPRTC_JIT_NUM_INPUT_TYPES = 9 -hiprtcJITInputType = ctypes.c_uint32 # enum -class struct_ihiprtcLinkState(Structure): - pass +# hipError_t hipArrayGetDescriptor(HIP_ARRAY_DESCRIPTOR *pArrayDescriptor, hipArray_t array) +try: (hipArrayGetDescriptor:=dll.hipArrayGetDescriptor).restype, hipArrayGetDescriptor.argtypes = hipError_t, [ctypes.POINTER(HIP_ARRAY_DESCRIPTOR), hipArray_t] +except AttributeError: pass -hiprtcLinkState = ctypes.POINTER(struct_ihiprtcLinkState) -try: - hiprtcGetErrorString = _libraries['libamdhip64.so'].hiprtcGetErrorString - hiprtcGetErrorString.restype = ctypes.POINTER(ctypes.c_char) - hiprtcGetErrorString.argtypes = [hiprtcResult] -except AttributeError: - pass -try: - hiprtcVersion = _libraries['libamdhip64.so'].hiprtcVersion - hiprtcVersion.restype = hiprtcResult - hiprtcVersion.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -class struct__hiprtcProgram(Structure): - pass +# hipError_t hipArray3DGetDescriptor(HIP_ARRAY3D_DESCRIPTOR *pArrayDescriptor, hipArray_t array) +try: (hipArray3DGetDescriptor:=dll.hipArray3DGetDescriptor).restype, hipArray3DGetDescriptor.argtypes = hipError_t, [ctypes.POINTER(HIP_ARRAY3D_DESCRIPTOR), hipArray_t] +except AttributeError: pass -hiprtcProgram = ctypes.POINTER(struct__hiprtcProgram) -try: - hiprtcAddNameExpression = _libraries['libamdhip64.so'].hiprtcAddNameExpression - hiprtcAddNameExpression.restype = hiprtcResult - hiprtcAddNameExpression.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcCompileProgram = _libraries['libamdhip64.so'].hiprtcCompileProgram - hiprtcCompileProgram.restype = hiprtcResult - hiprtcCompileProgram.argtypes = [hiprtcProgram, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hiprtcCreateProgram = _libraries['libamdhip64.so'].hiprtcCreateProgram - hiprtcCreateProgram.restype = hiprtcResult - hiprtcCreateProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__hiprtcProgram)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hiprtcDestroyProgram = _libraries['libamdhip64.so'].hiprtcDestroyProgram - hiprtcDestroyProgram.restype = hiprtcResult - hiprtcDestroyProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__hiprtcProgram))] -except AttributeError: - pass -try: - hiprtcGetLoweredName = _libraries['libamdhip64.so'].hiprtcGetLoweredName - hiprtcGetLoweredName.restype = hiprtcResult - hiprtcGetLoweredName.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hiprtcGetProgramLog = _libraries['libamdhip64.so'].hiprtcGetProgramLog - hiprtcGetProgramLog.restype = hiprtcResult - hiprtcGetProgramLog.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcGetProgramLogSize = _libraries['libamdhip64.so'].hiprtcGetProgramLogSize - hiprtcGetProgramLogSize.restype = hiprtcResult - hiprtcGetProgramLogSize.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcGetCode = _libraries['libamdhip64.so'].hiprtcGetCode - hiprtcGetCode.restype = hiprtcResult - hiprtcGetCode.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcGetCodeSize = _libraries['libamdhip64.so'].hiprtcGetCodeSize - hiprtcGetCodeSize.restype = hiprtcResult - hiprtcGetCodeSize.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcGetBitcode = _libraries['libamdhip64.so'].hiprtcGetBitcode - hiprtcGetBitcode.restype = hiprtcResult - hiprtcGetBitcode.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - hiprtcGetBitcodeSize = _libraries['libamdhip64.so'].hiprtcGetBitcodeSize - hiprtcGetBitcodeSize.restype = hiprtcResult - hiprtcGetBitcodeSize.argtypes = [hiprtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcLinkCreate = _libraries['libamdhip64.so'].hiprtcLinkCreate - hiprtcLinkCreate.restype = hiprtcResult - hiprtcLinkCreate.argtypes = [ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.POINTER(struct_ihiprtcLinkState))] -except AttributeError: - pass -try: - hiprtcLinkAddFile = _libraries['libamdhip64.so'].hiprtcLinkAddFile - hiprtcLinkAddFile.restype = hiprtcResult - hiprtcLinkAddFile.argtypes = [hiprtcLinkState, hiprtcJITInputType, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hiprtcLinkAddData = _libraries['libamdhip64.so'].hiprtcLinkAddData - hiprtcLinkAddData.restype = hiprtcResult - hiprtcLinkAddData.argtypes = [hiprtcLinkState, hiprtcJITInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(hiprtcJIT_option), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hiprtcLinkComplete = _libraries['libamdhip64.so'].hiprtcLinkComplete - hiprtcLinkComplete.restype = hiprtcResult - hiprtcLinkComplete.argtypes = [hiprtcLinkState, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hiprtcLinkDestroy = _libraries['libamdhip64.so'].hiprtcLinkDestroy - hiprtcLinkDestroy.restype = hiprtcResult - hiprtcLinkDestroy.argtypes = [hiprtcLinkState] -except AttributeError: - pass -__all__ = \ - ['HIPRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 'HIPRTC_ERROR_COMPILATION', 'HIPRTC_ERROR_INTERNAL_ERROR', - 'HIPRTC_ERROR_INVALID_INPUT', 'HIPRTC_ERROR_INVALID_OPTION', - 'HIPRTC_ERROR_INVALID_PROGRAM', 'HIPRTC_ERROR_LINKING', - 'HIPRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 'HIPRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 'HIPRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 'HIPRTC_ERROR_OUT_OF_MEMORY', - 'HIPRTC_ERROR_PROGRAM_CREATION_FAILURE', 'HIPRTC_JIT_CACHE_MODE', - 'HIPRTC_JIT_ERROR_LOG_BUFFER', - 'HIPRTC_JIT_ERROR_LOG_BUFFER_SIZE_BYTES', - 'HIPRTC_JIT_FALLBACK_STRATEGY', 'HIPRTC_JIT_FAST_COMPILE', - 'HIPRTC_JIT_FMA', 'HIPRTC_JIT_FTZ', - 'HIPRTC_JIT_GENERATE_DEBUG_INFO', 'HIPRTC_JIT_GENERATE_LINE_INFO', - 'HIPRTC_JIT_GLOBAL_SYMBOL_ADDRESS', - 'HIPRTC_JIT_GLOBAL_SYMBOL_COUNT', - 'HIPRTC_JIT_GLOBAL_SYMBOL_NAMES', 'HIPRTC_JIT_INFO_LOG_BUFFER', - 'HIPRTC_JIT_INFO_LOG_BUFFER_SIZE_BYTES', 'HIPRTC_JIT_INPUT_CUBIN', - 'HIPRTC_JIT_INPUT_FATBINARY', 'HIPRTC_JIT_INPUT_LIBRARY', - 'HIPRTC_JIT_INPUT_LLVM_ARCHIVES_OF_BUNDLED_BITCODE', - 'HIPRTC_JIT_INPUT_LLVM_BITCODE', - 'HIPRTC_JIT_INPUT_LLVM_BUNDLED_BITCODE', 'HIPRTC_JIT_INPUT_NVVM', - 'HIPRTC_JIT_INPUT_OBJECT', 'HIPRTC_JIT_INPUT_PTX', - 'HIPRTC_JIT_IR_TO_ISA_OPT_COUNT_EXT', - 'HIPRTC_JIT_IR_TO_ISA_OPT_EXT', 'HIPRTC_JIT_LOG_VERBOSE', - 'HIPRTC_JIT_LTO', 'HIPRTC_JIT_MAX_REGISTERS', - 'HIPRTC_JIT_NEW_SM3X_OPT', 'HIPRTC_JIT_NUM_INPUT_TYPES', - 'HIPRTC_JIT_NUM_LEGACY_INPUT_TYPES', 'HIPRTC_JIT_NUM_OPTIONS', - 'HIPRTC_JIT_OPTIMIZATION_LEVEL', 'HIPRTC_JIT_PREC_DIV', - 'HIPRTC_JIT_PREC_SQRT', 'HIPRTC_JIT_TARGET', - 'HIPRTC_JIT_TARGET_FROM_HIPCONTEXT', - 'HIPRTC_JIT_THREADS_PER_BLOCK', 'HIPRTC_JIT_WALL_TIME', - 'HIPRTC_SUCCESS', 'HIP_AD_FORMAT_FLOAT', 'HIP_AD_FORMAT_HALF', - 'HIP_AD_FORMAT_SIGNED_INT16', 'HIP_AD_FORMAT_SIGNED_INT32', - 'HIP_AD_FORMAT_SIGNED_INT8', 'HIP_AD_FORMAT_UNSIGNED_INT16', - 'HIP_AD_FORMAT_UNSIGNED_INT32', 'HIP_AD_FORMAT_UNSIGNED_INT8', - 'HIP_ARRAY3D_DESCRIPTOR', 'HIP_ARRAY_DESCRIPTOR', - 'HIP_ERROR_INVALID_VALUE', 'HIP_ERROR_LAUNCH_OUT_OF_RESOURCES', - 'HIP_ERROR_NOT_INITIALIZED', 'HIP_FUNC_ATTRIBUTE_BINARY_VERSION', - 'HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA', - 'HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', - 'HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', 'HIP_FUNC_ATTRIBUTE_MAX', - 'HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', - 'HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', - 'HIP_FUNC_ATTRIBUTE_NUM_REGS', - 'HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', - 'HIP_FUNC_ATTRIBUTE_PTX_VERSION', - 'HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', 'HIP_MEMCPY3D', - 'HIP_POINTER_ATTRIBUTE_ACCESS_FLAGS', - 'HIP_POINTER_ATTRIBUTE_ALLOWED_HANDLE_TYPES', - 'HIP_POINTER_ATTRIBUTE_BUFFER_ID', - 'HIP_POINTER_ATTRIBUTE_CONTEXT', - 'HIP_POINTER_ATTRIBUTE_DEVICE_ORDINAL', - 'HIP_POINTER_ATTRIBUTE_DEVICE_POINTER', - 'HIP_POINTER_ATTRIBUTE_HOST_POINTER', - 'HIP_POINTER_ATTRIBUTE_IS_GPU_DIRECT_RDMA_CAPABLE', - 'HIP_POINTER_ATTRIBUTE_IS_LEGACY_HIP_IPC_CAPABLE', - 'HIP_POINTER_ATTRIBUTE_IS_MANAGED', - 'HIP_POINTER_ATTRIBUTE_MAPPED', - 'HIP_POINTER_ATTRIBUTE_MEMORY_TYPE', - 'HIP_POINTER_ATTRIBUTE_MEMPOOL_HANDLE', - 'HIP_POINTER_ATTRIBUTE_P2P_TOKENS', - 'HIP_POINTER_ATTRIBUTE_RANGE_SIZE', - 'HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR', - 'HIP_POINTER_ATTRIBUTE_SYNC_MEMOPS', 'HIP_RESOURCE_DESC', - 'HIP_RESOURCE_TYPE_ARRAY', 'HIP_RESOURCE_TYPE_LINEAR', - 'HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY', 'HIP_RESOURCE_TYPE_PITCH2D', - 'HIP_RESOURCE_VIEW_DESC', 'HIP_RES_VIEW_FORMAT_FLOAT_1X16', - 'HIP_RES_VIEW_FORMAT_FLOAT_1X32', - 'HIP_RES_VIEW_FORMAT_FLOAT_2X16', - 'HIP_RES_VIEW_FORMAT_FLOAT_2X32', - 'HIP_RES_VIEW_FORMAT_FLOAT_4X16', - 'HIP_RES_VIEW_FORMAT_FLOAT_4X32', 'HIP_RES_VIEW_FORMAT_NONE', - 'HIP_RES_VIEW_FORMAT_SIGNED_BC4', - 'HIP_RES_VIEW_FORMAT_SIGNED_BC5', - 'HIP_RES_VIEW_FORMAT_SIGNED_BC6H', - 'HIP_RES_VIEW_FORMAT_SINT_1X16', 'HIP_RES_VIEW_FORMAT_SINT_1X32', - 'HIP_RES_VIEW_FORMAT_SINT_1X8', 'HIP_RES_VIEW_FORMAT_SINT_2X16', - 'HIP_RES_VIEW_FORMAT_SINT_2X32', 'HIP_RES_VIEW_FORMAT_SINT_2X8', - 'HIP_RES_VIEW_FORMAT_SINT_4X16', 'HIP_RES_VIEW_FORMAT_SINT_4X32', - 'HIP_RES_VIEW_FORMAT_SINT_4X8', 'HIP_RES_VIEW_FORMAT_UINT_1X16', - 'HIP_RES_VIEW_FORMAT_UINT_1X32', 'HIP_RES_VIEW_FORMAT_UINT_1X8', - 'HIP_RES_VIEW_FORMAT_UINT_2X16', 'HIP_RES_VIEW_FORMAT_UINT_2X32', - 'HIP_RES_VIEW_FORMAT_UINT_2X8', 'HIP_RES_VIEW_FORMAT_UINT_4X16', - 'HIP_RES_VIEW_FORMAT_UINT_4X32', 'HIP_RES_VIEW_FORMAT_UINT_4X8', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC1', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC2', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC3', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC4', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC5', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H', - 'HIP_RES_VIEW_FORMAT_UNSIGNED_BC7', 'HIP_SUCCESS', - 'HIP_TEXTURE_DESC', 'HIP_TR_ADDRESS_MODE_BORDER', - 'HIP_TR_ADDRESS_MODE_CLAMP', 'HIP_TR_ADDRESS_MODE_MIRROR', - 'HIP_TR_ADDRESS_MODE_WRAP', 'HIP_TR_FILTER_MODE_LINEAR', - 'HIP_TR_FILTER_MODE_POINT', 'HIPaddress_mode', - 'HIPaddress_mode__enumvalues', 'HIPaddress_mode_enum', - 'HIPfilter_mode', 'HIPfilter_mode__enumvalues', - 'HIPfilter_mode_enum', 'HIPresourceViewFormat', - 'HIPresourceViewFormat__enumvalues', 'HIPresourceViewFormat_enum', - 'HIPresourcetype', 'HIPresourcetype__enumvalues', - 'HIPresourcetype_enum', '__hipGetPCH', - '__hipPopCallConfiguration', '__hipPushCallConfiguration', - 'c__Ea_HIP_SUCCESS', 'dim3', 'hipAccessPolicyWindow', - 'hipAccessProperty', 'hipAccessPropertyNormal', - 'hipAccessPropertyPersisting', 'hipAccessPropertyStreaming', - 'hipAddressModeBorder', 'hipAddressModeClamp', - 'hipAddressModeMirror', 'hipAddressModeWrap', 'hipApiName', - 'hipArray3DCreate', 'hipArray3DGetDescriptor', 'hipArrayCreate', - 'hipArrayDestroy', 'hipArrayGetDescriptor', 'hipArrayGetInfo', - 'hipArrayMapInfo', 'hipArraySparseSubresourceType', - 'hipArraySparseSubresourceTypeMiptail', - 'hipArraySparseSubresourceTypeSparseLevel', 'hipArray_Format', - 'hipArray_const_t', 'hipArray_t', 'hipBindTexture', - 'hipBindTexture2D', 'hipBindTextureToArray', - 'hipBindTextureToMipmappedArray', 'hipChannelFormatDesc', - 'hipChannelFormatKind', 'hipChannelFormatKindFloat', - 'hipChannelFormatKindNone', 'hipChannelFormatKindSigned', - 'hipChannelFormatKindUnsigned', 'hipChooseDeviceR0600', - 'hipComputeMode', 'hipComputeModeDefault', - 'hipComputeModeExclusive', 'hipComputeModeExclusiveProcess', - 'hipComputeModeProhibited', 'hipConfigureCall', - 'hipCreateSurfaceObject', 'hipCreateTextureObject', - 'hipCtxCreate', 'hipCtxDestroy', 'hipCtxDisablePeerAccess', - 'hipCtxEnablePeerAccess', 'hipCtxGetApiVersion', - 'hipCtxGetCacheConfig', 'hipCtxGetCurrent', 'hipCtxGetDevice', - 'hipCtxGetFlags', 'hipCtxGetSharedMemConfig', 'hipCtxPopCurrent', - 'hipCtxPushCurrent', 'hipCtxSetCacheConfig', 'hipCtxSetCurrent', - 'hipCtxSetSharedMemConfig', 'hipCtxSynchronize', 'hipCtx_t', - 'hipDestroyExternalMemory', 'hipDestroyExternalSemaphore', - 'hipDestroySurfaceObject', 'hipDestroyTextureObject', - 'hipDevP2PAttrAccessSupported', - 'hipDevP2PAttrHipArrayAccessSupported', - 'hipDevP2PAttrNativeAtomicSupported', - 'hipDevP2PAttrPerformanceRank', 'hipDeviceArch_t', - 'hipDeviceAttributeAccessPolicyMaxWindowSize', - 'hipDeviceAttributeAmdSpecificBegin', - 'hipDeviceAttributeAmdSpecificEnd', - 'hipDeviceAttributeAsicRevision', - 'hipDeviceAttributeAsyncEngineCount', - 'hipDeviceAttributeCanMapHostMemory', - 'hipDeviceAttributeCanUseHostPointerForRegisteredMem', - 'hipDeviceAttributeCanUseStreamWaitValue', - 'hipDeviceAttributeClockInstructionRate', - 'hipDeviceAttributeClockRate', - 'hipDeviceAttributeComputeCapabilityMajor', - 'hipDeviceAttributeComputeCapabilityMinor', - 'hipDeviceAttributeComputeMode', - 'hipDeviceAttributeComputePreemptionSupported', - 'hipDeviceAttributeConcurrentKernels', - 'hipDeviceAttributeConcurrentManagedAccess', - 'hipDeviceAttributeCooperativeLaunch', - 'hipDeviceAttributeCooperativeMultiDeviceLaunch', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedBlockDim', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedFunc', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedGridDim', - 'hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem', - 'hipDeviceAttributeCudaCompatibleBegin', - 'hipDeviceAttributeCudaCompatibleEnd', - 'hipDeviceAttributeDeviceOverlap', - 'hipDeviceAttributeDirectManagedMemAccessFromHost', - 'hipDeviceAttributeEccEnabled', - 'hipDeviceAttributeFineGrainSupport', - 'hipDeviceAttributeGlobalL1CacheSupported', - 'hipDeviceAttributeHdpMemFlushCntl', - 'hipDeviceAttributeHdpRegFlushCntl', - 'hipDeviceAttributeHostNativeAtomicSupported', - 'hipDeviceAttributeHostRegisterSupported', - 'hipDeviceAttributeImageSupport', 'hipDeviceAttributeIntegrated', - 'hipDeviceAttributeIsLargeBar', - 'hipDeviceAttributeIsMultiGpuBoard', - 'hipDeviceAttributeKernelExecTimeout', - 'hipDeviceAttributeL2CacheSize', - 'hipDeviceAttributeLocalL1CacheSupported', - 'hipDeviceAttributeLuid', 'hipDeviceAttributeLuidDeviceNodeMask', - 'hipDeviceAttributeManagedMemory', - 'hipDeviceAttributeMaxBlockDimX', - 'hipDeviceAttributeMaxBlockDimY', - 'hipDeviceAttributeMaxBlockDimZ', - 'hipDeviceAttributeMaxBlocksPerMultiProcessor', - 'hipDeviceAttributeMaxGridDimX', 'hipDeviceAttributeMaxGridDimY', - 'hipDeviceAttributeMaxGridDimZ', 'hipDeviceAttributeMaxPitch', - 'hipDeviceAttributeMaxRegistersPerBlock', - 'hipDeviceAttributeMaxRegistersPerMultiprocessor', - 'hipDeviceAttributeMaxSharedMemoryPerBlock', - 'hipDeviceAttributeMaxSharedMemoryPerMultiprocessor', - 'hipDeviceAttributeMaxSurface1D', - 'hipDeviceAttributeMaxSurface1DLayered', - 'hipDeviceAttributeMaxSurface2D', - 'hipDeviceAttributeMaxSurface2DLayered', - 'hipDeviceAttributeMaxSurface3D', - 'hipDeviceAttributeMaxSurfaceCubemap', - 'hipDeviceAttributeMaxSurfaceCubemapLayered', - 'hipDeviceAttributeMaxTexture1DLayered', - 'hipDeviceAttributeMaxTexture1DLinear', - 'hipDeviceAttributeMaxTexture1DMipmap', - 'hipDeviceAttributeMaxTexture1DWidth', - 'hipDeviceAttributeMaxTexture2DGather', - 'hipDeviceAttributeMaxTexture2DHeight', - 'hipDeviceAttributeMaxTexture2DLayered', - 'hipDeviceAttributeMaxTexture2DLinear', - 'hipDeviceAttributeMaxTexture2DMipmap', - 'hipDeviceAttributeMaxTexture2DWidth', - 'hipDeviceAttributeMaxTexture3DAlt', - 'hipDeviceAttributeMaxTexture3DDepth', - 'hipDeviceAttributeMaxTexture3DHeight', - 'hipDeviceAttributeMaxTexture3DWidth', - 'hipDeviceAttributeMaxTextureCubemap', - 'hipDeviceAttributeMaxTextureCubemapLayered', - 'hipDeviceAttributeMaxThreadsDim', - 'hipDeviceAttributeMaxThreadsPerBlock', - 'hipDeviceAttributeMaxThreadsPerMultiProcessor', - 'hipDeviceAttributeMemoryBusWidth', - 'hipDeviceAttributeMemoryClockRate', - 'hipDeviceAttributeMemoryPoolsSupported', - 'hipDeviceAttributeMultiGpuBoardGroupID', - 'hipDeviceAttributeMultiprocessorCount', - 'hipDeviceAttributePageableMemoryAccess', - 'hipDeviceAttributePageableMemoryAccessUsesHostPageTables', - 'hipDeviceAttributePciBusId', 'hipDeviceAttributePciDeviceId', - 'hipDeviceAttributePciDomainID', - 'hipDeviceAttributePersistingL2CacheMaxSize', - 'hipDeviceAttributePhysicalMultiProcessorCount', - 'hipDeviceAttributeReservedSharedMemPerBlock', - 'hipDeviceAttributeSharedMemPerBlockOptin', - 'hipDeviceAttributeSharedMemPerMultiprocessor', - 'hipDeviceAttributeSingleToDoublePrecisionPerfRatio', - 'hipDeviceAttributeStreamPrioritiesSupported', - 'hipDeviceAttributeSurfaceAlignment', - 'hipDeviceAttributeTccDriver', - 'hipDeviceAttributeTextureAlignment', - 'hipDeviceAttributeTexturePitchAlignment', - 'hipDeviceAttributeTotalConstantMemory', - 'hipDeviceAttributeTotalGlobalMem', - 'hipDeviceAttributeUnifiedAddressing', - 'hipDeviceAttributeUnused1', 'hipDeviceAttributeUnused2', - 'hipDeviceAttributeUnused3', 'hipDeviceAttributeUnused4', - 'hipDeviceAttributeUnused5', - 'hipDeviceAttributeVendorSpecificBegin', - 'hipDeviceAttributeVirtualMemoryManagementSupported', - 'hipDeviceAttributeWallClockRate', 'hipDeviceAttributeWarpSize', - 'hipDeviceAttribute_t', 'hipDeviceCanAccessPeer', - 'hipDeviceComputeCapability', 'hipDeviceDisablePeerAccess', - 'hipDeviceEnablePeerAccess', 'hipDeviceGet', - 'hipDeviceGetAttribute', 'hipDeviceGetByPCIBusId', - 'hipDeviceGetCacheConfig', 'hipDeviceGetDefaultMemPool', - 'hipDeviceGetGraphMemAttribute', 'hipDeviceGetLimit', - 'hipDeviceGetMemPool', 'hipDeviceGetName', - 'hipDeviceGetP2PAttribute', 'hipDeviceGetPCIBusId', - 'hipDeviceGetSharedMemConfig', 'hipDeviceGetStreamPriorityRange', - 'hipDeviceGetUuid', 'hipDeviceGraphMemTrim', 'hipDeviceP2PAttr', - 'hipDevicePrimaryCtxGetState', 'hipDevicePrimaryCtxRelease', - 'hipDevicePrimaryCtxReset', 'hipDevicePrimaryCtxRetain', - 'hipDevicePrimaryCtxSetFlags', 'hipDeviceProp_tR0600', - 'hipDeviceReset', 'hipDeviceSetCacheConfig', - 'hipDeviceSetGraphMemAttribute', 'hipDeviceSetLimit', - 'hipDeviceSetMemPool', 'hipDeviceSetSharedMemConfig', - 'hipDeviceSynchronize', 'hipDeviceTotalMem', 'hipDevice_t', - 'hipDeviceptr_t', 'hipDriverGetVersion', 'hipDrvGetErrorName', - 'hipDrvGetErrorString', 'hipDrvGraphAddMemcpyNode', - 'hipDrvMemcpy2DUnaligned', 'hipDrvMemcpy3D', - 'hipDrvMemcpy3DAsync', 'hipDrvPointerGetAttributes', - 'hipErrorAlreadyAcquired', 'hipErrorAlreadyMapped', - 'hipErrorArrayIsMapped', 'hipErrorAssert', - 'hipErrorCapturedEvent', 'hipErrorContextAlreadyCurrent', - 'hipErrorContextAlreadyInUse', 'hipErrorContextIsDestroyed', - 'hipErrorCooperativeLaunchTooLarge', 'hipErrorDeinitialized', - 'hipErrorECCNotCorrectable', 'hipErrorFileNotFound', - 'hipErrorGraphExecUpdateFailure', - 'hipErrorHostMemoryAlreadyRegistered', - 'hipErrorHostMemoryNotRegistered', 'hipErrorIllegalAddress', - 'hipErrorIllegalState', 'hipErrorInitializationError', - 'hipErrorInsufficientDriver', 'hipErrorInvalidConfiguration', - 'hipErrorInvalidContext', 'hipErrorInvalidDevice', - 'hipErrorInvalidDeviceFunction', 'hipErrorInvalidDevicePointer', - 'hipErrorInvalidGraphicsContext', 'hipErrorInvalidHandle', - 'hipErrorInvalidImage', 'hipErrorInvalidKernelFile', - 'hipErrorInvalidMemcpyDirection', 'hipErrorInvalidPitchValue', - 'hipErrorInvalidResourceHandle', 'hipErrorInvalidSource', - 'hipErrorInvalidSymbol', 'hipErrorInvalidValue', - 'hipErrorLaunchFailure', 'hipErrorLaunchOutOfResources', - 'hipErrorLaunchTimeOut', 'hipErrorMapBufferObjectFailed', - 'hipErrorMapFailed', 'hipErrorMemoryAllocation', - 'hipErrorMissingConfiguration', 'hipErrorNoBinaryForGpu', - 'hipErrorNoDevice', 'hipErrorNotFound', 'hipErrorNotInitialized', - 'hipErrorNotMapped', 'hipErrorNotMappedAsArray', - 'hipErrorNotMappedAsPointer', 'hipErrorNotReady', - 'hipErrorNotSupported', 'hipErrorOperatingSystem', - 'hipErrorOutOfMemory', 'hipErrorPeerAccessAlreadyEnabled', - 'hipErrorPeerAccessNotEnabled', 'hipErrorPeerAccessUnsupported', - 'hipErrorPriorLaunchFailure', 'hipErrorProfilerAlreadyStarted', - 'hipErrorProfilerAlreadyStopped', 'hipErrorProfilerDisabled', - 'hipErrorProfilerNotInitialized', 'hipErrorRuntimeMemory', - 'hipErrorRuntimeOther', 'hipErrorSetOnActiveProcess', - 'hipErrorSharedObjectInitFailed', - 'hipErrorSharedObjectSymbolNotFound', - 'hipErrorStreamCaptureImplicit', - 'hipErrorStreamCaptureInvalidated', - 'hipErrorStreamCaptureIsolation', 'hipErrorStreamCaptureMerge', - 'hipErrorStreamCaptureUnjoined', 'hipErrorStreamCaptureUnmatched', - 'hipErrorStreamCaptureUnsupported', - 'hipErrorStreamCaptureWrongThread', 'hipErrorTbd', - 'hipErrorUnknown', 'hipErrorUnmapFailed', - 'hipErrorUnsupportedLimit', 'hipError_t', 'hipEventCreate', - 'hipEventCreateWithFlags', 'hipEventDestroy', - 'hipEventElapsedTime', 'hipEventQuery', 'hipEventRecord', - 'hipEventSynchronize', 'hipEvent_t', 'hipExtGetLastError', - 'hipExtGetLinkTypeAndHopCount', 'hipExtLaunchKernel', - 'hipExtLaunchMultiKernelMultiDevice', 'hipExtMallocWithFlags', - 'hipExtModuleLaunchKernel', 'hipExtStreamCreateWithCUMask', - 'hipExtStreamGetCUMask', 'hipExtent', - 'hipExternalMemoryBufferDesc', 'hipExternalMemoryGetMappedBuffer', - 'hipExternalMemoryGetMappedMipmappedArray', - 'hipExternalMemoryHandleDesc', 'hipExternalMemoryHandleType', - 'hipExternalMemoryHandleTypeD3D11Resource', - 'hipExternalMemoryHandleTypeD3D11ResourceKmt', - 'hipExternalMemoryHandleTypeD3D12Heap', - 'hipExternalMemoryHandleTypeD3D12Resource', - 'hipExternalMemoryHandleTypeNvSciBuf', - 'hipExternalMemoryHandleTypeOpaqueFd', - 'hipExternalMemoryHandleTypeOpaqueWin32', - 'hipExternalMemoryHandleTypeOpaqueWin32Kmt', - 'hipExternalMemoryHandleType__enumvalues', - 'hipExternalMemoryHandleType_enum', - 'hipExternalMemoryMipmappedArrayDesc', 'hipExternalMemory_t', - 'hipExternalSemaphoreHandleDesc', - 'hipExternalSemaphoreHandleType', - 'hipExternalSemaphoreHandleTypeD3D11Fence', - 'hipExternalSemaphoreHandleTypeD3D12Fence', - 'hipExternalSemaphoreHandleTypeKeyedMutex', - 'hipExternalSemaphoreHandleTypeKeyedMutexKmt', - 'hipExternalSemaphoreHandleTypeNvSciSync', - 'hipExternalSemaphoreHandleTypeOpaqueFd', - 'hipExternalSemaphoreHandleTypeOpaqueWin32', - 'hipExternalSemaphoreHandleTypeOpaqueWin32Kmt', - 'hipExternalSemaphoreHandleTypeTimelineSemaphoreFd', - 'hipExternalSemaphoreHandleTypeTimelineSemaphoreWin32', - 'hipExternalSemaphoreHandleType__enumvalues', - 'hipExternalSemaphoreHandleType_enum', - 'hipExternalSemaphoreSignalNodeParams', - 'hipExternalSemaphoreSignalParams', - 'hipExternalSemaphoreWaitNodeParams', - 'hipExternalSemaphoreWaitParams', 'hipExternalSemaphore_t', - 'hipFilterModeLinear', 'hipFilterModePoint', 'hipFree', - 'hipFreeArray', 'hipFreeAsync', 'hipFreeHost', - 'hipFreeMipmappedArray', 'hipFuncAttribute', - 'hipFuncAttributeMax', - 'hipFuncAttributeMaxDynamicSharedMemorySize', - 'hipFuncAttributePreferredSharedMemoryCarveout', - 'hipFuncAttributes', 'hipFuncCachePreferEqual', - 'hipFuncCachePreferL1', 'hipFuncCachePreferNone', - 'hipFuncCachePreferShared', 'hipFuncCache_t', - 'hipFuncGetAttribute', 'hipFuncGetAttributes', - 'hipFuncSetAttribute', 'hipFuncSetCacheConfig', - 'hipFuncSetSharedMemConfig', 'hipFunctionLaunchParams', - 'hipFunction_attribute', 'hipFunction_t', 'hipGetChannelDesc', - 'hipGetDevice', 'hipGetDeviceCount', 'hipGetDeviceFlags', - 'hipGetDevicePropertiesR0600', 'hipGetErrorName', - 'hipGetErrorString', 'hipGetLastError', - 'hipGetMipmappedArrayLevel', 'hipGetStreamDeviceId', - 'hipGetSymbolAddress', 'hipGetSymbolSize', - 'hipGetTextureAlignmentOffset', 'hipGetTextureObjectResourceDesc', - 'hipGetTextureObjectResourceViewDesc', - 'hipGetTextureObjectTextureDesc', 'hipGetTextureReference', - 'hipGraphAddChildGraphNode', 'hipGraphAddDependencies', - 'hipGraphAddEmptyNode', 'hipGraphAddEventRecordNode', - 'hipGraphAddEventWaitNode', 'hipGraphAddHostNode', - 'hipGraphAddKernelNode', 'hipGraphAddMemAllocNode', - 'hipGraphAddMemFreeNode', 'hipGraphAddMemcpyNode', - 'hipGraphAddMemcpyNode1D', 'hipGraphAddMemcpyNodeFromSymbol', - 'hipGraphAddMemcpyNodeToSymbol', 'hipGraphAddMemsetNode', - 'hipGraphChildGraphNodeGetGraph', 'hipGraphClone', - 'hipGraphCreate', 'hipGraphDebugDotFlags', - 'hipGraphDebugDotFlagsEventNodeParams', - 'hipGraphDebugDotFlagsExtSemasSignalNodeParams', - 'hipGraphDebugDotFlagsExtSemasWaitNodeParams', - 'hipGraphDebugDotFlagsHandles', - 'hipGraphDebugDotFlagsHostNodeParams', - 'hipGraphDebugDotFlagsKernelNodeAttributes', - 'hipGraphDebugDotFlagsKernelNodeParams', - 'hipGraphDebugDotFlagsMemcpyNodeParams', - 'hipGraphDebugDotFlagsMemsetNodeParams', - 'hipGraphDebugDotFlagsVerbose', 'hipGraphDebugDotPrint', - 'hipGraphDestroy', 'hipGraphDestroyNode', - 'hipGraphEventRecordNodeGetEvent', - 'hipGraphEventRecordNodeSetEvent', - 'hipGraphEventWaitNodeGetEvent', 'hipGraphEventWaitNodeSetEvent', - 'hipGraphExecChildGraphNodeSetParams', 'hipGraphExecDestroy', - 'hipGraphExecEventRecordNodeSetEvent', - 'hipGraphExecEventWaitNodeSetEvent', - 'hipGraphExecHostNodeSetParams', - 'hipGraphExecKernelNodeSetParams', - 'hipGraphExecMemcpyNodeSetParams', - 'hipGraphExecMemcpyNodeSetParams1D', - 'hipGraphExecMemcpyNodeSetParamsFromSymbol', - 'hipGraphExecMemcpyNodeSetParamsToSymbol', - 'hipGraphExecMemsetNodeSetParams', 'hipGraphExecUpdate', - 'hipGraphExecUpdateError', - 'hipGraphExecUpdateErrorFunctionChanged', - 'hipGraphExecUpdateErrorNodeTypeChanged', - 'hipGraphExecUpdateErrorNotSupported', - 'hipGraphExecUpdateErrorParametersChanged', - 'hipGraphExecUpdateErrorTopologyChanged', - 'hipGraphExecUpdateErrorUnsupportedFunctionChange', - 'hipGraphExecUpdateResult', 'hipGraphExecUpdateSuccess', - 'hipGraphExec_t', 'hipGraphGetEdges', 'hipGraphGetNodes', - 'hipGraphGetRootNodes', 'hipGraphHostNodeGetParams', - 'hipGraphHostNodeSetParams', 'hipGraphInstantiate', - 'hipGraphInstantiateFlagAutoFreeOnLaunch', - 'hipGraphInstantiateFlagDeviceLaunch', - 'hipGraphInstantiateFlagUpload', - 'hipGraphInstantiateFlagUseNodePriority', - 'hipGraphInstantiateFlags', 'hipGraphInstantiateWithFlags', - 'hipGraphKernelNodeCopyAttributes', - 'hipGraphKernelNodeGetAttribute', 'hipGraphKernelNodeGetParams', - 'hipGraphKernelNodeSetAttribute', 'hipGraphKernelNodeSetParams', - 'hipGraphLaunch', 'hipGraphMemAllocNodeGetParams', - 'hipGraphMemAttrReservedMemCurrent', - 'hipGraphMemAttrReservedMemHigh', 'hipGraphMemAttrUsedMemCurrent', - 'hipGraphMemAttrUsedMemHigh', 'hipGraphMemAttributeType', - 'hipGraphMemFreeNodeGetParams', 'hipGraphMemcpyNodeGetParams', - 'hipGraphMemcpyNodeSetParams', 'hipGraphMemcpyNodeSetParams1D', - 'hipGraphMemcpyNodeSetParamsFromSymbol', - 'hipGraphMemcpyNodeSetParamsToSymbol', - 'hipGraphMemsetNodeGetParams', 'hipGraphMemsetNodeSetParams', - 'hipGraphNodeFindInClone', 'hipGraphNodeGetDependencies', - 'hipGraphNodeGetDependentNodes', 'hipGraphNodeGetEnabled', - 'hipGraphNodeGetType', 'hipGraphNodeSetEnabled', - 'hipGraphNodeType', 'hipGraphNodeTypeCount', - 'hipGraphNodeTypeEmpty', 'hipGraphNodeTypeEventRecord', - 'hipGraphNodeTypeExtSemaphoreSignal', - 'hipGraphNodeTypeExtSemaphoreWait', 'hipGraphNodeTypeGraph', - 'hipGraphNodeTypeHost', 'hipGraphNodeTypeKernel', - 'hipGraphNodeTypeMemAlloc', 'hipGraphNodeTypeMemFree', - 'hipGraphNodeTypeMemcpy', 'hipGraphNodeTypeMemcpyFromSymbol', - 'hipGraphNodeTypeMemcpyToSymbol', 'hipGraphNodeTypeMemset', - 'hipGraphNodeTypeWaitEvent', 'hipGraphNode_t', - 'hipGraphReleaseUserObject', 'hipGraphRemoveDependencies', - 'hipGraphRetainUserObject', 'hipGraphUpload', - 'hipGraphUserObjectMove', 'hipGraph_t', 'hipGraphicsMapResources', - 'hipGraphicsRegisterFlags', 'hipGraphicsRegisterFlagsNone', - 'hipGraphicsRegisterFlagsReadOnly', - 'hipGraphicsRegisterFlagsSurfaceLoadStore', - 'hipGraphicsRegisterFlagsTextureGather', - 'hipGraphicsRegisterFlagsWriteDiscard', 'hipGraphicsResource', - 'hipGraphicsResourceGetMappedPointer', 'hipGraphicsResource_t', - 'hipGraphicsSubResourceGetMappedArray', - 'hipGraphicsUnmapResources', 'hipGraphicsUnregisterResource', - 'hipHccModuleLaunchKernel', 'hipHostAlloc', 'hipHostFn_t', - 'hipHostFree', 'hipHostGetDevicePointer', 'hipHostGetFlags', - 'hipHostMalloc', 'hipHostNodeParams', 'hipHostRegister', - 'hipHostUnregister', 'hipImportExternalMemory', - 'hipImportExternalSemaphore', 'hipInit', 'hipIpcCloseMemHandle', - 'hipIpcEventHandle_t', 'hipIpcGetEventHandle', - 'hipIpcGetMemHandle', 'hipIpcMemHandle_t', - 'hipIpcOpenEventHandle', 'hipIpcOpenMemHandle', 'hipJitOption', - 'hipJitOptionCacheMode', 'hipJitOptionErrorLogBuffer', - 'hipJitOptionErrorLogBufferSizeBytes', - 'hipJitOptionFallbackStrategy', 'hipJitOptionFastCompile', - 'hipJitOptionGenerateDebugInfo', 'hipJitOptionGenerateLineInfo', - 'hipJitOptionInfoLogBuffer', 'hipJitOptionInfoLogBufferSizeBytes', - 'hipJitOptionLogVerbose', 'hipJitOptionMaxRegisters', - 'hipJitOptionNumOptions', 'hipJitOptionOptimizationLevel', - 'hipJitOptionSm3xOpt', 'hipJitOptionTarget', - 'hipJitOptionTargetFromContext', 'hipJitOptionThreadsPerBlock', - 'hipJitOptionWallTime', 'hipKernelNameRef', - 'hipKernelNameRefByPtr', 'hipKernelNodeAttrID', - 'hipKernelNodeAttrValue', - 'hipKernelNodeAttributeAccessPolicyWindow', - 'hipKernelNodeAttributeCooperative', 'hipKernelNodeParams', - 'hipLaunchByPtr', 'hipLaunchCooperativeKernel', - 'hipLaunchCooperativeKernelMultiDevice', 'hipLaunchHostFunc', - 'hipLaunchKernel', 'hipLaunchParams', 'hipLimitMallocHeapSize', - 'hipLimitPrintfFifoSize', 'hipLimitRange', 'hipLimitStackSize', - 'hipLimit_t', 'hipMalloc', 'hipMalloc3D', 'hipMalloc3DArray', - 'hipMallocArray', 'hipMallocAsync', 'hipMallocFromPoolAsync', - 'hipMallocHost', 'hipMallocManaged', 'hipMallocMipmappedArray', - 'hipMallocPitch', 'hipMemAccessDesc', 'hipMemAccessFlags', - 'hipMemAccessFlagsProtNone', 'hipMemAccessFlagsProtRead', - 'hipMemAccessFlagsProtReadWrite', 'hipMemAddressFree', - 'hipMemAddressReserve', 'hipMemAdvise', - 'hipMemAdviseSetAccessedBy', 'hipMemAdviseSetCoarseGrain', - 'hipMemAdviseSetPreferredLocation', 'hipMemAdviseSetReadMostly', - 'hipMemAdviseUnsetAccessedBy', 'hipMemAdviseUnsetCoarseGrain', - 'hipMemAdviseUnsetPreferredLocation', - 'hipMemAdviseUnsetReadMostly', 'hipMemAllocHost', - 'hipMemAllocNodeParams', 'hipMemAllocPitch', - 'hipMemAllocationGranularityMinimum', - 'hipMemAllocationGranularityRecommended', - 'hipMemAllocationGranularity_flags', 'hipMemAllocationHandleType', - 'hipMemAllocationProp', 'hipMemAllocationType', - 'hipMemAllocationTypeInvalid', 'hipMemAllocationTypeMax', - 'hipMemAllocationTypePinned', 'hipMemCreate', - 'hipMemExportToShareableHandle', - 'hipMemGenericAllocationHandle_t', 'hipMemGetAccess', - 'hipMemGetAddressRange', 'hipMemGetAllocationGranularity', - 'hipMemGetAllocationPropertiesFromHandle', 'hipMemGetInfo', - 'hipMemHandleType', 'hipMemHandleTypeGeneric', - 'hipMemHandleTypeNone', 'hipMemHandleTypePosixFileDescriptor', - 'hipMemHandleTypeWin32', 'hipMemHandleTypeWin32Kmt', - 'hipMemImportFromShareableHandle', 'hipMemLocation', - 'hipMemLocationType', 'hipMemLocationTypeDevice', - 'hipMemLocationTypeInvalid', 'hipMemMap', 'hipMemMapArrayAsync', - 'hipMemOperationType', 'hipMemOperationTypeMap', - 'hipMemOperationTypeUnmap', 'hipMemPoolAttr', - 'hipMemPoolAttrReleaseThreshold', - 'hipMemPoolAttrReservedMemCurrent', - 'hipMemPoolAttrReservedMemHigh', 'hipMemPoolAttrUsedMemCurrent', - 'hipMemPoolAttrUsedMemHigh', 'hipMemPoolCreate', - 'hipMemPoolDestroy', 'hipMemPoolExportPointer', - 'hipMemPoolExportToShareableHandle', 'hipMemPoolGetAccess', - 'hipMemPoolGetAttribute', 'hipMemPoolImportFromShareableHandle', - 'hipMemPoolImportPointer', 'hipMemPoolProps', - 'hipMemPoolPtrExportData', - 'hipMemPoolReuseAllowInternalDependencies', - 'hipMemPoolReuseAllowOpportunistic', - 'hipMemPoolReuseFollowEventDependencies', 'hipMemPoolSetAccess', - 'hipMemPoolSetAttribute', 'hipMemPoolTrimTo', 'hipMemPool_t', - 'hipMemPrefetchAsync', 'hipMemPtrGetInfo', 'hipMemRangeAttribute', - 'hipMemRangeAttributeAccessedBy', - 'hipMemRangeAttributeCoherencyMode', - 'hipMemRangeAttributeLastPrefetchLocation', - 'hipMemRangeAttributePreferredLocation', - 'hipMemRangeAttributeReadMostly', 'hipMemRangeCoherencyMode', - 'hipMemRangeCoherencyModeCoarseGrain', - 'hipMemRangeCoherencyModeFineGrain', - 'hipMemRangeCoherencyModeIndeterminate', - 'hipMemRangeGetAttribute', 'hipMemRangeGetAttributes', - 'hipMemRelease', 'hipMemRetainAllocationHandle', - 'hipMemSetAccess', 'hipMemUnmap', 'hipMemcpy', 'hipMemcpy2D', - 'hipMemcpy2DAsync', 'hipMemcpy2DFromArray', - 'hipMemcpy2DFromArrayAsync', 'hipMemcpy2DToArray', - 'hipMemcpy2DToArrayAsync', 'hipMemcpy3D', 'hipMemcpy3DAsync', - 'hipMemcpy3DParms', 'hipMemcpyAsync', 'hipMemcpyAtoH', - 'hipMemcpyDefault', 'hipMemcpyDeviceToDevice', - 'hipMemcpyDeviceToHost', 'hipMemcpyDtoD', 'hipMemcpyDtoDAsync', - 'hipMemcpyDtoH', 'hipMemcpyDtoHAsync', 'hipMemcpyFromArray', - 'hipMemcpyFromSymbol', 'hipMemcpyFromSymbolAsync', - 'hipMemcpyHostToDevice', 'hipMemcpyHostToHost', 'hipMemcpyHtoA', - 'hipMemcpyHtoD', 'hipMemcpyHtoDAsync', 'hipMemcpyKind', - 'hipMemcpyParam2D', 'hipMemcpyParam2DAsync', 'hipMemcpyPeer', - 'hipMemcpyPeerAsync', 'hipMemcpyToArray', 'hipMemcpyToSymbol', - 'hipMemcpyToSymbolAsync', 'hipMemcpyWithStream', - 'hipMemoryAdvise', 'hipMemoryType', 'hipMemoryTypeArray', - 'hipMemoryTypeDevice', 'hipMemoryTypeHost', - 'hipMemoryTypeManaged', 'hipMemoryTypeUnified', - 'hipMemoryTypeUnregistered', 'hipMemset', 'hipMemset2D', - 'hipMemset2DAsync', 'hipMemset3D', 'hipMemset3DAsync', - 'hipMemsetAsync', 'hipMemsetD16', 'hipMemsetD16Async', - 'hipMemsetD32', 'hipMemsetD32Async', 'hipMemsetD8', - 'hipMemsetD8Async', 'hipMemsetParams', 'hipMipmappedArray', - 'hipMipmappedArrayCreate', 'hipMipmappedArrayDestroy', - 'hipMipmappedArrayGetLevel', 'hipMipmappedArray_const_t', - 'hipMipmappedArray_t', 'hipModuleGetFunction', - 'hipModuleGetGlobal', 'hipModuleGetTexRef', - 'hipModuleLaunchCooperativeKernel', - 'hipModuleLaunchCooperativeKernelMultiDevice', - 'hipModuleLaunchKernel', 'hipModuleLoad', 'hipModuleLoadData', - 'hipModuleLoadDataEx', - 'hipModuleOccupancyMaxActiveBlocksPerMultiprocessor', - 'hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags', - 'hipModuleOccupancyMaxPotentialBlockSize', - 'hipModuleOccupancyMaxPotentialBlockSizeWithFlags', - 'hipModuleUnload', 'hipModule_t', - 'hipOccupancyMaxActiveBlocksPerMultiprocessor', - 'hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags', - 'hipOccupancyMaxPotentialBlockSize', 'hipPeekAtLastError', - 'hipPitchedPtr', 'hipPointerAttribute_t', - 'hipPointerGetAttribute', 'hipPointerGetAttributes', - 'hipPointerSetAttribute', 'hipPointer_attribute', 'hipPos', - 'hipProfilerStart', 'hipProfilerStop', 'hipReadModeElementType', - 'hipReadModeNormalizedFloat', 'hipResViewFormatFloat1', - 'hipResViewFormatFloat2', 'hipResViewFormatFloat4', - 'hipResViewFormatHalf1', 'hipResViewFormatHalf2', - 'hipResViewFormatHalf4', 'hipResViewFormatNone', - 'hipResViewFormatSignedBlockCompressed4', - 'hipResViewFormatSignedBlockCompressed5', - 'hipResViewFormatSignedBlockCompressed6H', - 'hipResViewFormatSignedChar1', 'hipResViewFormatSignedChar2', - 'hipResViewFormatSignedChar4', 'hipResViewFormatSignedInt1', - 'hipResViewFormatSignedInt2', 'hipResViewFormatSignedInt4', - 'hipResViewFormatSignedShort1', 'hipResViewFormatSignedShort2', - 'hipResViewFormatSignedShort4', - 'hipResViewFormatUnsignedBlockCompressed1', - 'hipResViewFormatUnsignedBlockCompressed2', - 'hipResViewFormatUnsignedBlockCompressed3', - 'hipResViewFormatUnsignedBlockCompressed4', - 'hipResViewFormatUnsignedBlockCompressed5', - 'hipResViewFormatUnsignedBlockCompressed6H', - 'hipResViewFormatUnsignedBlockCompressed7', - 'hipResViewFormatUnsignedChar1', 'hipResViewFormatUnsignedChar2', - 'hipResViewFormatUnsignedChar4', 'hipResViewFormatUnsignedInt1', - 'hipResViewFormatUnsignedInt2', 'hipResViewFormatUnsignedInt4', - 'hipResViewFormatUnsignedShort1', - 'hipResViewFormatUnsignedShort2', - 'hipResViewFormatUnsignedShort4', 'hipResourceDesc', - 'hipResourceType', 'hipResourceTypeArray', - 'hipResourceTypeLinear', 'hipResourceTypeMipmappedArray', - 'hipResourceTypePitch2D', 'hipResourceViewFormat', - 'hipResourcetype', 'hipResourcetype__enumvalues', - 'hipRuntimeGetVersion', 'hipSetDevice', 'hipSetDeviceFlags', - 'hipSetupArgument', 'hipSharedMemBankSizeDefault', - 'hipSharedMemBankSizeEightByte', 'hipSharedMemBankSizeFourByte', - 'hipSharedMemConfig', 'hipSignalExternalSemaphoresAsync', - 'hipStreamAddCallback', 'hipStreamAddCaptureDependencies', - 'hipStreamAttachMemAsync', 'hipStreamBeginCapture', - 'hipStreamCallback_t', 'hipStreamCaptureMode', - 'hipStreamCaptureModeGlobal', 'hipStreamCaptureModeRelaxed', - 'hipStreamCaptureModeThreadLocal', 'hipStreamCaptureStatus', - 'hipStreamCaptureStatusActive', - 'hipStreamCaptureStatusInvalidated', 'hipStreamCaptureStatusNone', - 'hipStreamCreate', 'hipStreamCreateWithFlags', - 'hipStreamCreateWithPriority', 'hipStreamDestroy', - 'hipStreamEndCapture', 'hipStreamGetCaptureInfo', - 'hipStreamGetCaptureInfo_v2', 'hipStreamGetDevice', - 'hipStreamGetFlags', 'hipStreamGetPriority', - 'hipStreamIsCapturing', 'hipStreamQuery', - 'hipStreamSetCaptureDependencies', 'hipStreamSynchronize', - 'hipStreamUpdateCaptureDependencies', - 'hipStreamUpdateCaptureDependenciesFlags', 'hipStreamWaitEvent', - 'hipStreamWaitValue32', 'hipStreamWaitValue64', - 'hipStreamWriteValue32', 'hipStreamWriteValue64', 'hipStream_t', - 'hipSuccess', 'hipSurfaceObject_t', 'hipTexObjectCreate', - 'hipTexObjectDestroy', 'hipTexObjectGetResourceDesc', - 'hipTexObjectGetResourceViewDesc', 'hipTexObjectGetTextureDesc', - 'hipTexRefGetAddress', 'hipTexRefGetAddressMode', - 'hipTexRefGetFilterMode', 'hipTexRefGetFlags', - 'hipTexRefGetFormat', 'hipTexRefGetMaxAnisotropy', - 'hipTexRefGetMipMappedArray', 'hipTexRefGetMipmapFilterMode', - 'hipTexRefGetMipmapLevelBias', 'hipTexRefGetMipmapLevelClamp', - 'hipTexRefSetAddress', 'hipTexRefSetAddress2D', - 'hipTexRefSetAddressMode', 'hipTexRefSetArray', - 'hipTexRefSetBorderColor', 'hipTexRefSetFilterMode', - 'hipTexRefSetFlags', 'hipTexRefSetFormat', - 'hipTexRefSetMaxAnisotropy', 'hipTexRefSetMipmapFilterMode', - 'hipTexRefSetMipmapLevelBias', 'hipTexRefSetMipmapLevelClamp', - 'hipTexRefSetMipmappedArray', 'hipTextureAddressMode', - 'hipTextureFilterMode', 'hipTextureObject_t', - 'hipTextureReadMode', 'hipThreadExchangeStreamCaptureMode', - 'hipUUID', 'hipUnbindTexture', 'hipUserObjectCreate', - 'hipUserObjectFlags', 'hipUserObjectNoDestructorSync', - 'hipUserObjectRelease', 'hipUserObjectRetain', - 'hipUserObjectRetainFlags', 'hipUserObject_t', - 'hipWaitExternalSemaphoresAsync', 'hip_Memcpy2D', 'hip_init', - 'hipmipmappedArray', 'hiprtcAddNameExpression', - 'hiprtcCompileProgram', 'hiprtcCreateProgram', - 'hiprtcDestroyProgram', 'hiprtcGetBitcode', - 'hiprtcGetBitcodeSize', 'hiprtcGetCode', 'hiprtcGetCodeSize', - 'hiprtcGetErrorString', 'hiprtcGetLoweredName', - 'hiprtcGetProgramLog', 'hiprtcGetProgramLogSize', - 'hiprtcJITInputType', 'hiprtcJIT_option', 'hiprtcLinkAddData', - 'hiprtcLinkAddFile', 'hiprtcLinkComplete', 'hiprtcLinkCreate', - 'hiprtcLinkDestroy', 'hiprtcLinkState', 'hiprtcProgram', - 'hiprtcResult', 'hiprtcVersion', 'make_hipExtent', - 'make_hipPitchedPtr', 'make_hipPos', 'size_t', - 'struct_HIP_ARRAY3D_DESCRIPTOR', 'struct_HIP_ARRAY_DESCRIPTOR', - 'struct_HIP_MEMCPY3D', 'struct_HIP_RESOURCE_DESC_st', - 'struct_HIP_RESOURCE_DESC_st_0_array', - 'struct_HIP_RESOURCE_DESC_st_0_linear', - 'struct_HIP_RESOURCE_DESC_st_0_mipmap', - 'struct_HIP_RESOURCE_DESC_st_0_pitch2D', - 'struct_HIP_RESOURCE_DESC_st_0_reserved', - 'struct_HIP_RESOURCE_VIEW_DESC_st', 'struct_HIP_TEXTURE_DESC_st', - 'struct___hip_surface', 'struct___hip_texture', - 'struct__hipGraphicsResource', 'struct__hiprtcProgram', - 'struct_c__SA_hipDeviceArch_t', 'struct_dim3', - 'struct_hipAccessPolicyWindow', 'struct_hipArray', - 'struct_hipArrayMapInfo', 'struct_hipArrayMapInfo_1_miptail', - 'struct_hipArrayMapInfo_1_sparseLevel', - 'struct_hipChannelFormatDesc', 'struct_hipDeviceProp_tR0600', - 'struct_hipExtent', 'struct_hipExternalMemoryBufferDesc_st', - 'struct_hipExternalMemoryHandleDesc_st', - 'struct_hipExternalMemoryHandleDesc_st_0_win32', - 'struct_hipExternalMemoryMipmappedArrayDesc_st', - 'struct_hipExternalSemaphoreHandleDesc_st', - 'struct_hipExternalSemaphoreHandleDesc_st_0_win32', - 'struct_hipExternalSemaphoreSignalNodeParams', - 'struct_hipExternalSemaphoreSignalParams_st', - 'struct_hipExternalSemaphoreSignalParams_st_0_fence', - 'struct_hipExternalSemaphoreSignalParams_st_0_keyedMutex', - 'struct_hipExternalSemaphoreSignalParams_st_params', - 'struct_hipExternalSemaphoreWaitNodeParams', - 'struct_hipExternalSemaphoreWaitParams_st', - 'struct_hipExternalSemaphoreWaitParams_st_0_fence', - 'struct_hipExternalSemaphoreWaitParams_st_0_keyedMutex', - 'struct_hipExternalSemaphoreWaitParams_st_params', - 'struct_hipFuncAttributes', 'struct_hipFunctionLaunchParams_t', - 'struct_hipGraphExec', 'struct_hipGraphNode', - 'struct_hipHostNodeParams', 'struct_hipIpcEventHandle_st', - 'struct_hipIpcMemHandle_st', 'struct_hipKernelNodeParams', - 'struct_hipLaunchParams_t', 'struct_hipMemAccessDesc', - 'struct_hipMemAllocNodeParams', 'struct_hipMemAllocationProp', - 'struct_hipMemAllocationProp_allocFlags', 'struct_hipMemLocation', - 'struct_hipMemPoolProps', 'struct_hipMemPoolPtrExportData', - 'struct_hipMemcpy3DParms', 'struct_hipMemsetParams', - 'struct_hipMipmappedArray', 'struct_hipPitchedPtr', - 'struct_hipPointerAttribute_t', 'struct_hipPos', - 'struct_hipResourceDesc', 'struct_hipResourceDesc_0_array', - 'struct_hipResourceDesc_0_linear', - 'struct_hipResourceDesc_0_mipmap', - 'struct_hipResourceDesc_0_pitch2D', 'struct_hipResourceViewDesc', - 'struct_hipTextureDesc', 'struct_hipUUID_t', - 'struct_hipUserObject', 'struct_hip_Memcpy2D', 'struct_ihipCtx_t', - 'struct_ihipEvent_t', 'struct_ihipGraph', - 'struct_ihipMemGenericAllocationHandle', - 'struct_ihipMemPoolHandle_t', 'struct_ihipModuleSymbol_t', - 'struct_ihipModule_t', 'struct_ihipStream_t', - 'struct_ihiprtcLinkState', 'struct_textureReference', 'uint32_t', - 'uint64_t', 'union_HIP_RESOURCE_DESC_st_res', - 'union_hipArrayMapInfo_memHandle', - 'union_hipArrayMapInfo_resource', - 'union_hipArrayMapInfo_subresource', - 'union_hipExternalMemoryHandleDesc_st_handle', - 'union_hipExternalSemaphoreHandleDesc_st_handle', - 'union_hipExternalSemaphoreSignalParams_st_0_nvSciSync', - 'union_hipExternalSemaphoreWaitParams_st_0_nvSciSync', - 'union_hipKernelNodeAttrValue', 'union_hipResourceDesc_res'] -hipDeviceProp_t = hipDeviceProp_tR0600 +# hipError_t hipMemcpy2D(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, hipMemcpyKind kind) +try: (hipMemcpy2D:=dll.hipMemcpy2D).restype, hipMemcpy2D.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.c_void_p, size_t, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +class hip_Memcpy2D(Struct): pass +hip_Memcpy2D._fields_ = [ + ('srcXInBytes', size_t), + ('srcY', size_t), + ('srcMemoryType', hipMemoryType), + ('srcHost', ctypes.c_void_p), + ('srcDevice', hipDeviceptr_t), + ('srcArray', hipArray_t), + ('srcPitch', size_t), + ('dstXInBytes', size_t), + ('dstY', size_t), + ('dstMemoryType', hipMemoryType), + ('dstHost', ctypes.c_void_p), + ('dstDevice', hipDeviceptr_t), + ('dstArray', hipArray_t), + ('dstPitch', size_t), + ('WidthInBytes', size_t), + ('Height', size_t), +] +# hipError_t hipMemcpyParam2D(const hip_Memcpy2D *pCopy) +try: (hipMemcpyParam2D:=dll.hipMemcpyParam2D).restype, hipMemcpyParam2D.argtypes = hipError_t, [ctypes.POINTER(hip_Memcpy2D)] +except AttributeError: pass + +# hipError_t hipMemcpyParam2DAsync(const hip_Memcpy2D *pCopy, hipStream_t stream = 0) +try: (hipMemcpyParam2DAsync:=dll.hipMemcpyParam2DAsync).restype, hipMemcpyParam2DAsync.argtypes = hipError_t, [ctypes.POINTER(hip_Memcpy2D), hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpy2DAsync(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, hipMemcpyKind kind, hipStream_t stream = 0) +try: (hipMemcpy2DAsync:=dll.hipMemcpy2DAsync).restype, hipMemcpy2DAsync.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.c_void_p, size_t, size_t, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpy2DToArray(hipArray_t dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, hipMemcpyKind kind) +try: (hipMemcpy2DToArray:=dll.hipMemcpy2DToArray).restype, hipMemcpy2DToArray.argtypes = hipError_t, [hipArray_t, size_t, size_t, ctypes.c_void_p, size_t, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipMemcpy2DToArrayAsync(hipArray_t dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, hipMemcpyKind kind, hipStream_t stream = 0) +try: (hipMemcpy2DToArrayAsync:=dll.hipMemcpy2DToArrayAsync).restype, hipMemcpy2DToArrayAsync.argtypes = hipError_t, [hipArray_t, size_t, size_t, ctypes.c_void_p, size_t, size_t, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +class const_hipArray(Struct): pass +hipArray_const_t = ctypes.POINTER(const_hipArray) +# hipError_t hipMemcpy2DArrayToArray(hipArray_t dst, size_t wOffsetDst, size_t hOffsetDst, hipArray_const_t src, size_t wOffsetSrc, size_t hOffsetSrc, size_t width, size_t height, hipMemcpyKind kind) +try: (hipMemcpy2DArrayToArray:=dll.hipMemcpy2DArrayToArray).restype, hipMemcpy2DArrayToArray.argtypes = hipError_t, [hipArray_t, size_t, size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipMemcpyToArray(hipArray_t dst, size_t wOffset, size_t hOffset, const void *src, size_t count, hipMemcpyKind kind) +try: (hipMemcpyToArray:=dll.hipMemcpyToArray).restype, hipMemcpyToArray.argtypes = hipError_t, [hipArray_t, size_t, size_t, ctypes.c_void_p, size_t, hipMemcpyKind] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipMemcpyFromArray(void *dst, hipArray_const_t srcArray, size_t wOffset, size_t hOffset, size_t count, hipMemcpyKind kind) +try: (hipMemcpyFromArray:=dll.hipMemcpyFromArray).restype, hipMemcpyFromArray.argtypes = hipError_t, [ctypes.c_void_p, hipArray_const_t, size_t, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipMemcpy2DFromArray(void *dst, size_t dpitch, hipArray_const_t src, size_t wOffset, size_t hOffset, size_t width, size_t height, hipMemcpyKind kind) +try: (hipMemcpy2DFromArray:=dll.hipMemcpy2DFromArray).restype, hipMemcpy2DFromArray.argtypes = hipError_t, [ctypes.c_void_p, size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipMemcpy2DFromArrayAsync(void *dst, size_t dpitch, hipArray_const_t src, size_t wOffset, size_t hOffset, size_t width, size_t height, hipMemcpyKind kind, hipStream_t stream = 0) +try: (hipMemcpy2DFromArrayAsync:=dll.hipMemcpy2DFromArrayAsync).restype, hipMemcpy2DFromArrayAsync.argtypes = hipError_t, [ctypes.c_void_p, size_t, hipArray_const_t, size_t, size_t, size_t, size_t, hipMemcpyKind, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemcpyAtoH(void *dst, hipArray_t srcArray, size_t srcOffset, size_t count) +try: (hipMemcpyAtoH:=dll.hipMemcpyAtoH).restype, hipMemcpyAtoH.argtypes = hipError_t, [ctypes.c_void_p, hipArray_t, size_t, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyHtoA(hipArray_t dstArray, size_t dstOffset, const void *srcHost, size_t count) +try: (hipMemcpyHtoA:=dll.hipMemcpyHtoA).restype, hipMemcpyHtoA.argtypes = hipError_t, [hipArray_t, size_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# hipError_t hipMemcpy3D(const struct hipMemcpy3DParms *p) +try: (hipMemcpy3D:=dll.hipMemcpy3D).restype, hipMemcpy3D.argtypes = hipError_t, [ctypes.POINTER(hipMemcpy3DParms)] +except AttributeError: pass + +# hipError_t hipMemcpy3DAsync(const struct hipMemcpy3DParms *p, hipStream_t stream = 0) +try: (hipMemcpy3DAsync:=dll.hipMemcpy3DAsync).restype, hipMemcpy3DAsync.argtypes = hipError_t, [ctypes.POINTER(hipMemcpy3DParms), hipStream_t] +except AttributeError: pass + +class HIP_MEMCPY3D(Struct): pass +HIP_MEMCPY3D._fields_ = [ + ('srcXInBytes', size_t), + ('srcY', size_t), + ('srcZ', size_t), + ('srcLOD', size_t), + ('srcMemoryType', hipMemoryType), + ('srcHost', ctypes.c_void_p), + ('srcDevice', hipDeviceptr_t), + ('srcArray', hipArray_t), + ('srcPitch', size_t), + ('srcHeight', size_t), + ('dstXInBytes', size_t), + ('dstY', size_t), + ('dstZ', size_t), + ('dstLOD', size_t), + ('dstMemoryType', hipMemoryType), + ('dstHost', ctypes.c_void_p), + ('dstDevice', hipDeviceptr_t), + ('dstArray', hipArray_t), + ('dstPitch', size_t), + ('dstHeight', size_t), + ('WidthInBytes', size_t), + ('Height', size_t), + ('Depth', size_t), +] +# hipError_t hipDrvMemcpy3D(const HIP_MEMCPY3D *pCopy) +try: (hipDrvMemcpy3D:=dll.hipDrvMemcpy3D).restype, hipDrvMemcpy3D.argtypes = hipError_t, [ctypes.POINTER(HIP_MEMCPY3D)] +except AttributeError: pass + +# hipError_t hipDrvMemcpy3DAsync(const HIP_MEMCPY3D *pCopy, hipStream_t stream) +try: (hipDrvMemcpy3DAsync:=dll.hipDrvMemcpy3DAsync).restype, hipDrvMemcpy3DAsync.argtypes = hipError_t, [ctypes.POINTER(HIP_MEMCPY3D), hipStream_t] +except AttributeError: pass + +# hipError_t hipDeviceCanAccessPeer(int *canAccessPeer, int deviceId, int peerDeviceId) +try: (hipDeviceCanAccessPeer:=dll.hipDeviceCanAccessPeer).restype, hipDeviceCanAccessPeer.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipDeviceEnablePeerAccess(int peerDeviceId, unsigned int flags) +try: (hipDeviceEnablePeerAccess:=dll.hipDeviceEnablePeerAccess).restype, hipDeviceEnablePeerAccess.argtypes = hipError_t, [ctypes.c_int32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipDeviceDisablePeerAccess(int peerDeviceId) +try: (hipDeviceDisablePeerAccess:=dll.hipDeviceDisablePeerAccess).restype, hipDeviceDisablePeerAccess.argtypes = hipError_t, [ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipMemGetAddressRange(hipDeviceptr_t *pbase, size_t *psize, hipDeviceptr_t dptr) +try: (hipMemGetAddressRange:=dll.hipMemGetAddressRange).restype, hipMemGetAddressRange.argtypes = hipError_t, [ctypes.POINTER(hipDeviceptr_t), ctypes.POINTER(size_t), hipDeviceptr_t] +except AttributeError: pass + +# hipError_t hipMemcpyPeer(void *dst, int dstDeviceId, const void *src, int srcDeviceId, size_t sizeBytes) +try: (hipMemcpyPeer:=dll.hipMemcpyPeer).restype, hipMemcpyPeer.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_int32, ctypes.c_void_p, ctypes.c_int32, size_t] +except AttributeError: pass + +# hipError_t hipMemcpyPeerAsync(void *dst, int dstDeviceId, const void *src, int srcDevice, size_t sizeBytes, hipStream_t stream = 0) +try: (hipMemcpyPeerAsync:=dll.hipMemcpyPeerAsync).restype, hipMemcpyPeerAsync.argtypes = hipError_t, [ctypes.c_void_p, ctypes.c_int32, ctypes.c_void_p, ctypes.c_int32, size_t, hipStream_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxCreate(hipCtx_t *ctx, unsigned int flags, hipDevice_t device) +try: (hipCtxCreate:=dll.hipCtxCreate).restype, hipCtxCreate.argtypes = hipError_t, [ctypes.POINTER(hipCtx_t), ctypes.c_uint32, hipDevice_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxDestroy(hipCtx_t ctx) +try: (hipCtxDestroy:=dll.hipCtxDestroy).restype, hipCtxDestroy.argtypes = hipError_t, [hipCtx_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxPopCurrent(hipCtx_t *ctx) +try: (hipCtxPopCurrent:=dll.hipCtxPopCurrent).restype, hipCtxPopCurrent.argtypes = hipError_t, [ctypes.POINTER(hipCtx_t)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxPushCurrent(hipCtx_t ctx) +try: (hipCtxPushCurrent:=dll.hipCtxPushCurrent).restype, hipCtxPushCurrent.argtypes = hipError_t, [hipCtx_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxSetCurrent(hipCtx_t ctx) +try: (hipCtxSetCurrent:=dll.hipCtxSetCurrent).restype, hipCtxSetCurrent.argtypes = hipError_t, [hipCtx_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxGetCurrent(hipCtx_t *ctx) +try: (hipCtxGetCurrent:=dll.hipCtxGetCurrent).restype, hipCtxGetCurrent.argtypes = hipError_t, [ctypes.POINTER(hipCtx_t)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxGetDevice(hipDevice_t *device) +try: (hipCtxGetDevice:=dll.hipCtxGetDevice).restype, hipCtxGetDevice.argtypes = hipError_t, [ctypes.POINTER(hipDevice_t)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxGetApiVersion(hipCtx_t ctx, int *apiVersion) +try: (hipCtxGetApiVersion:=dll.hipCtxGetApiVersion).restype, hipCtxGetApiVersion.argtypes = hipError_t, [hipCtx_t, ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxGetCacheConfig(hipFuncCache_t *cacheConfig) +try: (hipCtxGetCacheConfig:=dll.hipCtxGetCacheConfig).restype, hipCtxGetCacheConfig.argtypes = hipError_t, [ctypes.POINTER(hipFuncCache_t)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxSetCacheConfig(hipFuncCache_t cacheConfig) +try: (hipCtxSetCacheConfig:=dll.hipCtxSetCacheConfig).restype, hipCtxSetCacheConfig.argtypes = hipError_t, [hipFuncCache_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxSetSharedMemConfig(hipSharedMemConfig config) +try: (hipCtxSetSharedMemConfig:=dll.hipCtxSetSharedMemConfig).restype, hipCtxSetSharedMemConfig.argtypes = hipError_t, [hipSharedMemConfig] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxGetSharedMemConfig(hipSharedMemConfig *pConfig) +try: (hipCtxGetSharedMemConfig:=dll.hipCtxGetSharedMemConfig).restype, hipCtxGetSharedMemConfig.argtypes = hipError_t, [ctypes.POINTER(hipSharedMemConfig)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxSynchronize() +try: (hipCtxSynchronize:=dll.hipCtxSynchronize).restype, hipCtxSynchronize.argtypes = hipError_t, [] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxGetFlags(unsigned int *flags) +try: (hipCtxGetFlags:=dll.hipCtxGetFlags).restype, hipCtxGetFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxEnablePeerAccess(hipCtx_t peerCtx, unsigned int flags) +try: (hipCtxEnablePeerAccess:=dll.hipCtxEnablePeerAccess).restype, hipCtxEnablePeerAccess.argtypes = hipError_t, [hipCtx_t, ctypes.c_uint32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipCtxDisablePeerAccess(hipCtx_t peerCtx) +try: (hipCtxDisablePeerAccess:=dll.hipCtxDisablePeerAccess).restype, hipCtxDisablePeerAccess.argtypes = hipError_t, [hipCtx_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipDevicePrimaryCtxGetState(hipDevice_t dev, unsigned int *flags, int *active) +try: (hipDevicePrimaryCtxGetState:=dll.hipDevicePrimaryCtxGetState).restype, hipDevicePrimaryCtxGetState.argtypes = hipError_t, [hipDevice_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipDevicePrimaryCtxRelease(hipDevice_t dev) +try: (hipDevicePrimaryCtxRelease:=dll.hipDevicePrimaryCtxRelease).restype, hipDevicePrimaryCtxRelease.argtypes = hipError_t, [hipDevice_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipDevicePrimaryCtxRetain(hipCtx_t *pctx, hipDevice_t dev) +try: (hipDevicePrimaryCtxRetain:=dll.hipDevicePrimaryCtxRetain).restype, hipDevicePrimaryCtxRetain.argtypes = hipError_t, [ctypes.POINTER(hipCtx_t), hipDevice_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipDevicePrimaryCtxReset(hipDevice_t dev) +try: (hipDevicePrimaryCtxReset:=dll.hipDevicePrimaryCtxReset).restype, hipDevicePrimaryCtxReset.argtypes = hipError_t, [hipDevice_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipDevicePrimaryCtxSetFlags(hipDevice_t dev, unsigned int flags) +try: (hipDevicePrimaryCtxSetFlags:=dll.hipDevicePrimaryCtxSetFlags).restype, hipDevicePrimaryCtxSetFlags.argtypes = hipError_t, [hipDevice_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipModuleLoad(hipModule_t *module, const char *fname) +try: (hipModuleLoad:=dll.hipModuleLoad).restype, hipModuleLoad.argtypes = hipError_t, [ctypes.POINTER(hipModule_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hipError_t hipModuleUnload(hipModule_t module) +try: (hipModuleUnload:=dll.hipModuleUnload).restype, hipModuleUnload.argtypes = hipError_t, [hipModule_t] +except AttributeError: pass + +# hipError_t hipModuleGetFunction(hipFunction_t *function, hipModule_t module, const char *kname) +try: (hipModuleGetFunction:=dll.hipModuleGetFunction).restype, hipModuleGetFunction.argtypes = hipError_t, [ctypes.POINTER(hipFunction_t), hipModule_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hipError_t hipFuncGetAttributes(struct hipFuncAttributes *attr, const void *func) +try: (hipFuncGetAttributes:=dll.hipFuncGetAttributes).restype, hipFuncGetAttributes.argtypes = hipError_t, [ctypes.POINTER(hipFuncAttributes), ctypes.c_void_p] +except AttributeError: pass + +hipFunction_attribute = CEnum(ctypes.c_uint32) +HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK', 0) +HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES', 1) +HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_CONST_SIZE_BYTES', 2) +HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES', 3) +HIP_FUNC_ATTRIBUTE_NUM_REGS = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_NUM_REGS', 4) +HIP_FUNC_ATTRIBUTE_PTX_VERSION = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_PTX_VERSION', 5) +HIP_FUNC_ATTRIBUTE_BINARY_VERSION = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_BINARY_VERSION', 6) +HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_CACHE_MODE_CA', 7) +HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES', 8) +HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_PREFERRED_SHARED_MEMORY_CARVEOUT', 9) +HIP_FUNC_ATTRIBUTE_MAX = hipFunction_attribute.define('HIP_FUNC_ATTRIBUTE_MAX', 10) + +# hipError_t hipFuncGetAttribute(int *value, hipFunction_attribute attrib, hipFunction_t hfunc) +try: (hipFuncGetAttribute:=dll.hipFuncGetAttribute).restype, hipFuncGetAttribute.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), hipFunction_attribute, hipFunction_t] +except AttributeError: pass + +# hipError_t hipGetFuncBySymbol(hipFunction_t *functionPtr, const void *symbolPtr) +try: (hipGetFuncBySymbol:=dll.hipGetFuncBySymbol).restype, hipGetFuncBySymbol.argtypes = hipError_t, [ctypes.POINTER(hipFunction_t), ctypes.c_void_p] +except AttributeError: pass + +class textureReference(Struct): pass +hipTextureReadMode = CEnum(ctypes.c_uint32) +hipReadModeElementType = hipTextureReadMode.define('hipReadModeElementType', 0) +hipReadModeNormalizedFloat = hipTextureReadMode.define('hipReadModeNormalizedFloat', 1) + +hipTextureFilterMode = CEnum(ctypes.c_uint32) +hipFilterModePoint = hipTextureFilterMode.define('hipFilterModePoint', 0) +hipFilterModeLinear = hipTextureFilterMode.define('hipFilterModeLinear', 1) + +hipTextureAddressMode = CEnum(ctypes.c_uint32) +hipAddressModeWrap = hipTextureAddressMode.define('hipAddressModeWrap', 0) +hipAddressModeClamp = hipTextureAddressMode.define('hipAddressModeClamp', 1) +hipAddressModeMirror = hipTextureAddressMode.define('hipAddressModeMirror', 2) +hipAddressModeBorder = hipTextureAddressMode.define('hipAddressModeBorder', 3) + +class __hip_texture(Struct): pass +hipTextureObject_t = ctypes.POINTER(__hip_texture) +textureReference._fields_ = [ + ('normalized', ctypes.c_int32), + ('readMode', hipTextureReadMode), + ('filterMode', hipTextureFilterMode), + ('addressMode', (hipTextureAddressMode * 3)), + ('channelDesc', hipChannelFormatDesc), + ('sRGB', ctypes.c_int32), + ('maxAnisotropy', ctypes.c_uint32), + ('mipmapFilterMode', hipTextureFilterMode), + ('mipmapLevelBias', ctypes.c_float), + ('minMipmapLevelClamp', ctypes.c_float), + ('maxMipmapLevelClamp', ctypes.c_float), + ('textureObject', hipTextureObject_t), + ('numChannels', ctypes.c_int32), + ('format', hipArray_Format), +] +# hipError_t hipModuleGetTexRef(textureReference **texRef, hipModule_t hmod, const char *name) +try: (hipModuleGetTexRef:=dll.hipModuleGetTexRef).restype, hipModuleGetTexRef.argtypes = hipError_t, [ctypes.POINTER(ctypes.POINTER(textureReference)), hipModule_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# hipError_t hipModuleLoadData(hipModule_t *module, const void *image) +try: (hipModuleLoadData:=dll.hipModuleLoadData).restype, hipModuleLoadData.argtypes = hipError_t, [ctypes.POINTER(hipModule_t), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipModuleLoadDataEx(hipModule_t *module, const void *image, unsigned int numOptions, hipJitOption *options, void **optionValues) +try: (hipModuleLoadDataEx:=dll.hipModuleLoadDataEx).restype, hipModuleLoadDataEx.argtypes = hipError_t, [ctypes.POINTER(hipModule_t), ctypes.c_void_p, ctypes.c_uint32, ctypes.POINTER(hipJitOption), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hipError_t hipModuleLaunchKernel(hipFunction_t f, unsigned int gridDimX, unsigned int gridDimY, unsigned int gridDimZ, unsigned int blockDimX, unsigned int blockDimY, unsigned int blockDimZ, unsigned int sharedMemBytes, hipStream_t stream, void **kernelParams, void **extra) +try: (hipModuleLaunchKernel:=dll.hipModuleLaunchKernel).restype, hipModuleLaunchKernel.argtypes = hipError_t, [hipFunction_t, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, hipStream_t, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hipError_t hipModuleLaunchCooperativeKernel(hipFunction_t f, unsigned int gridDimX, unsigned int gridDimY, unsigned int gridDimZ, unsigned int blockDimX, unsigned int blockDimY, unsigned int blockDimZ, unsigned int sharedMemBytes, hipStream_t stream, void **kernelParams) +try: (hipModuleLaunchCooperativeKernel:=dll.hipModuleLaunchCooperativeKernel).restype, hipModuleLaunchCooperativeKernel.argtypes = hipError_t, [hipFunction_t, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, hipStream_t, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hipError_t hipModuleLaunchCooperativeKernelMultiDevice(hipFunctionLaunchParams *launchParamsList, unsigned int numDevices, unsigned int flags) +try: (hipModuleLaunchCooperativeKernelMultiDevice:=dll.hipModuleLaunchCooperativeKernelMultiDevice).restype, hipModuleLaunchCooperativeKernelMultiDevice.argtypes = hipError_t, [ctypes.POINTER(hipFunctionLaunchParams), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipLaunchCooperativeKernel(const void *f, dim3 gridDim, dim3 blockDimX, void **kernelParams, unsigned int sharedMemBytes, hipStream_t stream) +try: (hipLaunchCooperativeKernel:=dll.hipLaunchCooperativeKernel).restype, hipLaunchCooperativeKernel.argtypes = hipError_t, [ctypes.c_void_p, dim3, dim3, ctypes.POINTER(ctypes.c_void_p), ctypes.c_uint32, hipStream_t] +except AttributeError: pass + +# hipError_t hipLaunchCooperativeKernelMultiDevice(hipLaunchParams *launchParamsList, int numDevices, unsigned int flags) +try: (hipLaunchCooperativeKernelMultiDevice:=dll.hipLaunchCooperativeKernelMultiDevice).restype, hipLaunchCooperativeKernelMultiDevice.argtypes = hipError_t, [ctypes.POINTER(hipLaunchParams), ctypes.c_int32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipExtLaunchMultiKernelMultiDevice(hipLaunchParams *launchParamsList, int numDevices, unsigned int flags) +try: (hipExtLaunchMultiKernelMultiDevice:=dll.hipExtLaunchMultiKernelMultiDevice).restype, hipExtLaunchMultiKernelMultiDevice.argtypes = hipError_t, [ctypes.POINTER(hipLaunchParams), ctypes.c_int32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipModuleOccupancyMaxPotentialBlockSize(int *gridSize, int *blockSize, hipFunction_t f, size_t dynSharedMemPerBlk, int blockSizeLimit) +try: (hipModuleOccupancyMaxPotentialBlockSize:=dll.hipModuleOccupancyMaxPotentialBlockSize).restype, hipModuleOccupancyMaxPotentialBlockSize.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipFunction_t, size_t, ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipModuleOccupancyMaxPotentialBlockSizeWithFlags(int *gridSize, int *blockSize, hipFunction_t f, size_t dynSharedMemPerBlk, int blockSizeLimit, unsigned int flags) +try: (hipModuleOccupancyMaxPotentialBlockSizeWithFlags:=dll.hipModuleOccupancyMaxPotentialBlockSizeWithFlags).restype, hipModuleOccupancyMaxPotentialBlockSizeWithFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), hipFunction_t, size_t, ctypes.c_int32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipModuleOccupancyMaxActiveBlocksPerMultiprocessor(int *numBlocks, hipFunction_t f, int blockSize, size_t dynSharedMemPerBlk) +try: (hipModuleOccupancyMaxActiveBlocksPerMultiprocessor:=dll.hipModuleOccupancyMaxActiveBlocksPerMultiprocessor).restype, hipModuleOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), hipFunction_t, ctypes.c_int32, size_t] +except AttributeError: pass + +# hipError_t hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags(int *numBlocks, hipFunction_t f, int blockSize, size_t dynSharedMemPerBlk, unsigned int flags) +try: (hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags:=dll.hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags).restype, hipModuleOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), hipFunction_t, ctypes.c_int32, size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipOccupancyMaxActiveBlocksPerMultiprocessor(int *numBlocks, const void *f, int blockSize, size_t dynSharedMemPerBlk) +try: (hipOccupancyMaxActiveBlocksPerMultiprocessor:=dll.hipOccupancyMaxActiveBlocksPerMultiprocessor).restype, hipOccupancyMaxActiveBlocksPerMultiprocessor.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.c_void_p, ctypes.c_int32, size_t] +except AttributeError: pass + +# hipError_t hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags(int *numBlocks, const void *f, int blockSize, size_t dynSharedMemPerBlk, unsigned int flags = 0) +try: (hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags:=dll.hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags).restype, hipOccupancyMaxActiveBlocksPerMultiprocessorWithFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.c_void_p, ctypes.c_int32, size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipOccupancyMaxPotentialBlockSize(int *gridSize, int *blockSize, const void *f, size_t dynSharedMemPerBlk, int blockSizeLimit) +try: (hipOccupancyMaxPotentialBlockSize:=dll.hipOccupancyMaxPotentialBlockSize).restype, hipOccupancyMaxPotentialBlockSize.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.c_void_p, size_t, ctypes.c_int32] +except AttributeError: pass + +# __attribute__((deprecated("use roctracer/rocTX instead"))) hipError_t hipProfilerStart() +try: (hipProfilerStart:=dll.hipProfilerStart).restype, hipProfilerStart.argtypes = hipError_t, [] +except AttributeError: pass + +# __attribute__((deprecated("use roctracer/rocTX instead"))) hipError_t hipProfilerStop() +try: (hipProfilerStop:=dll.hipProfilerStop).restype, hipProfilerStop.argtypes = hipError_t, [] +except AttributeError: pass + +# hipError_t hipConfigureCall(dim3 gridDim, dim3 blockDim, size_t sharedMem = 0, hipStream_t stream = 0) +try: (hipConfigureCall:=dll.hipConfigureCall).restype, hipConfigureCall.argtypes = hipError_t, [dim3, dim3, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipSetupArgument(const void *arg, size_t size, size_t offset) +try: (hipSetupArgument:=dll.hipSetupArgument).restype, hipSetupArgument.argtypes = hipError_t, [ctypes.c_void_p, size_t, size_t] +except AttributeError: pass + +# hipError_t hipLaunchByPtr(const void *func) +try: (hipLaunchByPtr:=dll.hipLaunchByPtr).restype, hipLaunchByPtr.argtypes = hipError_t, [ctypes.c_void_p] +except AttributeError: pass + +# hipError_t __hipPushCallConfiguration(dim3 gridDim, dim3 blockDim, size_t sharedMem = 0, hipStream_t stream = 0) +try: (__hipPushCallConfiguration:=dll.__hipPushCallConfiguration).restype, __hipPushCallConfiguration.argtypes = hipError_t, [dim3, dim3, size_t, hipStream_t] +except AttributeError: pass + +# hipError_t __hipPopCallConfiguration(dim3 *gridDim, dim3 *blockDim, size_t *sharedMem, hipStream_t *stream) +try: (__hipPopCallConfiguration:=dll.__hipPopCallConfiguration).restype, __hipPopCallConfiguration.argtypes = hipError_t, [ctypes.POINTER(dim3), ctypes.POINTER(dim3), ctypes.POINTER(size_t), ctypes.POINTER(hipStream_t)] +except AttributeError: pass + +# hipError_t hipLaunchKernel(const void *function_address, dim3 numBlocks, dim3 dimBlocks, void **args, size_t sharedMemBytes = 0, hipStream_t stream = 0) +try: (hipLaunchKernel:=dll.hipLaunchKernel).restype, hipLaunchKernel.argtypes = hipError_t, [ctypes.c_void_p, dim3, dim3, ctypes.POINTER(ctypes.c_void_p), size_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipLaunchHostFunc(hipStream_t stream, hipHostFn_t fn, void *userData) +try: (hipLaunchHostFunc:=dll.hipLaunchHostFunc).restype, hipLaunchHostFunc.argtypes = hipError_t, [hipStream_t, hipHostFn_t, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipDrvMemcpy2DUnaligned(const hip_Memcpy2D *pCopy) +try: (hipDrvMemcpy2DUnaligned:=dll.hipDrvMemcpy2DUnaligned).restype, hipDrvMemcpy2DUnaligned.argtypes = hipError_t, [ctypes.POINTER(hip_Memcpy2D)] +except AttributeError: pass + +# hipError_t hipExtLaunchKernel(const void *function_address, dim3 numBlocks, dim3 dimBlocks, void **args, size_t sharedMemBytes, hipStream_t stream, hipEvent_t startEvent, hipEvent_t stopEvent, int flags) +try: (hipExtLaunchKernel:=dll.hipExtLaunchKernel).restype, hipExtLaunchKernel.argtypes = hipError_t, [ctypes.c_void_p, dim3, dim3, ctypes.POINTER(ctypes.c_void_p), size_t, hipStream_t, hipEvent_t, hipEvent_t, ctypes.c_int32] +except AttributeError: pass + +class hipResourceDesc(Struct): pass +class hipResourceDesc_res(ctypes.Union): pass +class hipResourceDesc_res_array(Struct): pass +hipResourceDesc_res_array._fields_ = [ + ('array', hipArray_t), +] +class hipResourceDesc_res_mipmap(Struct): pass +hipResourceDesc_res_mipmap._fields_ = [ + ('mipmap', hipMipmappedArray_t), +] +class hipResourceDesc_res_linear(Struct): pass +hipResourceDesc_res_linear._fields_ = [ + ('devPtr', ctypes.c_void_p), + ('desc', hipChannelFormatDesc), + ('sizeInBytes', size_t), +] +class hipResourceDesc_res_pitch2D(Struct): pass +hipResourceDesc_res_pitch2D._fields_ = [ + ('devPtr', ctypes.c_void_p), + ('desc', hipChannelFormatDesc), + ('width', size_t), + ('height', size_t), + ('pitchInBytes', size_t), +] +hipResourceDesc_res._fields_ = [ + ('array', hipResourceDesc_res_array), + ('mipmap', hipResourceDesc_res_mipmap), + ('linear', hipResourceDesc_res_linear), + ('pitch2D', hipResourceDesc_res_pitch2D), +] +hipResourceDesc._fields_ = [ + ('resType', hipResourceType), + ('res', hipResourceDesc_res), +] +class hipTextureDesc(Struct): pass +hipTextureDesc._fields_ = [ + ('addressMode', (hipTextureAddressMode * 3)), + ('filterMode', hipTextureFilterMode), + ('readMode', hipTextureReadMode), + ('sRGB', ctypes.c_int32), + ('borderColor', (ctypes.c_float * 4)), + ('normalizedCoords', ctypes.c_int32), + ('maxAnisotropy', ctypes.c_uint32), + ('mipmapFilterMode', hipTextureFilterMode), + ('mipmapLevelBias', ctypes.c_float), + ('minMipmapLevelClamp', ctypes.c_float), + ('maxMipmapLevelClamp', ctypes.c_float), +] +class hipResourceViewDesc(Struct): pass +hipResourceViewFormat = CEnum(ctypes.c_uint32) +hipResViewFormatNone = hipResourceViewFormat.define('hipResViewFormatNone', 0) +hipResViewFormatUnsignedChar1 = hipResourceViewFormat.define('hipResViewFormatUnsignedChar1', 1) +hipResViewFormatUnsignedChar2 = hipResourceViewFormat.define('hipResViewFormatUnsignedChar2', 2) +hipResViewFormatUnsignedChar4 = hipResourceViewFormat.define('hipResViewFormatUnsignedChar4', 3) +hipResViewFormatSignedChar1 = hipResourceViewFormat.define('hipResViewFormatSignedChar1', 4) +hipResViewFormatSignedChar2 = hipResourceViewFormat.define('hipResViewFormatSignedChar2', 5) +hipResViewFormatSignedChar4 = hipResourceViewFormat.define('hipResViewFormatSignedChar4', 6) +hipResViewFormatUnsignedShort1 = hipResourceViewFormat.define('hipResViewFormatUnsignedShort1', 7) +hipResViewFormatUnsignedShort2 = hipResourceViewFormat.define('hipResViewFormatUnsignedShort2', 8) +hipResViewFormatUnsignedShort4 = hipResourceViewFormat.define('hipResViewFormatUnsignedShort4', 9) +hipResViewFormatSignedShort1 = hipResourceViewFormat.define('hipResViewFormatSignedShort1', 10) +hipResViewFormatSignedShort2 = hipResourceViewFormat.define('hipResViewFormatSignedShort2', 11) +hipResViewFormatSignedShort4 = hipResourceViewFormat.define('hipResViewFormatSignedShort4', 12) +hipResViewFormatUnsignedInt1 = hipResourceViewFormat.define('hipResViewFormatUnsignedInt1', 13) +hipResViewFormatUnsignedInt2 = hipResourceViewFormat.define('hipResViewFormatUnsignedInt2', 14) +hipResViewFormatUnsignedInt4 = hipResourceViewFormat.define('hipResViewFormatUnsignedInt4', 15) +hipResViewFormatSignedInt1 = hipResourceViewFormat.define('hipResViewFormatSignedInt1', 16) +hipResViewFormatSignedInt2 = hipResourceViewFormat.define('hipResViewFormatSignedInt2', 17) +hipResViewFormatSignedInt4 = hipResourceViewFormat.define('hipResViewFormatSignedInt4', 18) +hipResViewFormatHalf1 = hipResourceViewFormat.define('hipResViewFormatHalf1', 19) +hipResViewFormatHalf2 = hipResourceViewFormat.define('hipResViewFormatHalf2', 20) +hipResViewFormatHalf4 = hipResourceViewFormat.define('hipResViewFormatHalf4', 21) +hipResViewFormatFloat1 = hipResourceViewFormat.define('hipResViewFormatFloat1', 22) +hipResViewFormatFloat2 = hipResourceViewFormat.define('hipResViewFormatFloat2', 23) +hipResViewFormatFloat4 = hipResourceViewFormat.define('hipResViewFormatFloat4', 24) +hipResViewFormatUnsignedBlockCompressed1 = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed1', 25) +hipResViewFormatUnsignedBlockCompressed2 = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed2', 26) +hipResViewFormatUnsignedBlockCompressed3 = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed3', 27) +hipResViewFormatUnsignedBlockCompressed4 = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed4', 28) +hipResViewFormatSignedBlockCompressed4 = hipResourceViewFormat.define('hipResViewFormatSignedBlockCompressed4', 29) +hipResViewFormatUnsignedBlockCompressed5 = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed5', 30) +hipResViewFormatSignedBlockCompressed5 = hipResourceViewFormat.define('hipResViewFormatSignedBlockCompressed5', 31) +hipResViewFormatUnsignedBlockCompressed6H = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed6H', 32) +hipResViewFormatSignedBlockCompressed6H = hipResourceViewFormat.define('hipResViewFormatSignedBlockCompressed6H', 33) +hipResViewFormatUnsignedBlockCompressed7 = hipResourceViewFormat.define('hipResViewFormatUnsignedBlockCompressed7', 34) + +hipResourceViewDesc._fields_ = [ + ('format', hipResourceViewFormat), + ('width', size_t), + ('height', size_t), + ('depth', size_t), + ('firstMipmapLevel', ctypes.c_uint32), + ('lastMipmapLevel', ctypes.c_uint32), + ('firstLayer', ctypes.c_uint32), + ('lastLayer', ctypes.c_uint32), +] +# hipError_t hipCreateTextureObject(hipTextureObject_t *pTexObject, const hipResourceDesc *pResDesc, const hipTextureDesc *pTexDesc, const struct hipResourceViewDesc *pResViewDesc) +try: (hipCreateTextureObject:=dll.hipCreateTextureObject).restype, hipCreateTextureObject.argtypes = hipError_t, [ctypes.POINTER(hipTextureObject_t), ctypes.POINTER(hipResourceDesc), ctypes.POINTER(hipTextureDesc), ctypes.POINTER(hipResourceViewDesc)] +except AttributeError: pass + +# hipError_t hipDestroyTextureObject(hipTextureObject_t textureObject) +try: (hipDestroyTextureObject:=dll.hipDestroyTextureObject).restype, hipDestroyTextureObject.argtypes = hipError_t, [hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipGetChannelDesc(hipChannelFormatDesc *desc, hipArray_const_t array) +try: (hipGetChannelDesc:=dll.hipGetChannelDesc).restype, hipGetChannelDesc.argtypes = hipError_t, [ctypes.POINTER(hipChannelFormatDesc), hipArray_const_t] +except AttributeError: pass + +# hipError_t hipGetTextureObjectResourceDesc(hipResourceDesc *pResDesc, hipTextureObject_t textureObject) +try: (hipGetTextureObjectResourceDesc:=dll.hipGetTextureObjectResourceDesc).restype, hipGetTextureObjectResourceDesc.argtypes = hipError_t, [ctypes.POINTER(hipResourceDesc), hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipGetTextureObjectResourceViewDesc(struct hipResourceViewDesc *pResViewDesc, hipTextureObject_t textureObject) +try: (hipGetTextureObjectResourceViewDesc:=dll.hipGetTextureObjectResourceViewDesc).restype, hipGetTextureObjectResourceViewDesc.argtypes = hipError_t, [ctypes.POINTER(hipResourceViewDesc), hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipGetTextureObjectTextureDesc(hipTextureDesc *pTexDesc, hipTextureObject_t textureObject) +try: (hipGetTextureObjectTextureDesc:=dll.hipGetTextureObjectTextureDesc).restype, hipGetTextureObjectTextureDesc.argtypes = hipError_t, [ctypes.POINTER(hipTextureDesc), hipTextureObject_t] +except AttributeError: pass + +class HIP_RESOURCE_DESC_st(Struct): pass +HIP_RESOURCE_DESC = HIP_RESOURCE_DESC_st +HIPresourcetype_enum = CEnum(ctypes.c_uint32) +HIP_RESOURCE_TYPE_ARRAY = HIPresourcetype_enum.define('HIP_RESOURCE_TYPE_ARRAY', 0) +HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY = HIPresourcetype_enum.define('HIP_RESOURCE_TYPE_MIPMAPPED_ARRAY', 1) +HIP_RESOURCE_TYPE_LINEAR = HIPresourcetype_enum.define('HIP_RESOURCE_TYPE_LINEAR', 2) +HIP_RESOURCE_TYPE_PITCH2D = HIPresourcetype_enum.define('HIP_RESOURCE_TYPE_PITCH2D', 3) + +HIPresourcetype = HIPresourcetype_enum +class HIP_RESOURCE_DESC_st_res(ctypes.Union): pass +class HIP_RESOURCE_DESC_st_res_array(Struct): pass +HIP_RESOURCE_DESC_st_res_array._fields_ = [ + ('hArray', hipArray_t), +] +class HIP_RESOURCE_DESC_st_res_mipmap(Struct): pass +HIP_RESOURCE_DESC_st_res_mipmap._fields_ = [ + ('hMipmappedArray', hipMipmappedArray_t), +] +class HIP_RESOURCE_DESC_st_res_linear(Struct): pass +HIP_RESOURCE_DESC_st_res_linear._fields_ = [ + ('devPtr', hipDeviceptr_t), + ('format', hipArray_Format), + ('numChannels', ctypes.c_uint32), + ('sizeInBytes', size_t), +] +class HIP_RESOURCE_DESC_st_res_pitch2D(Struct): pass +HIP_RESOURCE_DESC_st_res_pitch2D._fields_ = [ + ('devPtr', hipDeviceptr_t), + ('format', hipArray_Format), + ('numChannels', ctypes.c_uint32), + ('width', size_t), + ('height', size_t), + ('pitchInBytes', size_t), +] +class HIP_RESOURCE_DESC_st_res_reserved(Struct): pass +HIP_RESOURCE_DESC_st_res_reserved._fields_ = [ + ('reserved', (ctypes.c_int32 * 32)), +] +HIP_RESOURCE_DESC_st_res._fields_ = [ + ('array', HIP_RESOURCE_DESC_st_res_array), + ('mipmap', HIP_RESOURCE_DESC_st_res_mipmap), + ('linear', HIP_RESOURCE_DESC_st_res_linear), + ('pitch2D', HIP_RESOURCE_DESC_st_res_pitch2D), + ('reserved', HIP_RESOURCE_DESC_st_res_reserved), +] +HIP_RESOURCE_DESC_st._fields_ = [ + ('resType', HIPresourcetype), + ('res', HIP_RESOURCE_DESC_st_res), + ('flags', ctypes.c_uint32), +] +class HIP_TEXTURE_DESC_st(Struct): pass +HIP_TEXTURE_DESC = HIP_TEXTURE_DESC_st +HIPaddress_mode_enum = CEnum(ctypes.c_uint32) +HIP_TR_ADDRESS_MODE_WRAP = HIPaddress_mode_enum.define('HIP_TR_ADDRESS_MODE_WRAP', 0) +HIP_TR_ADDRESS_MODE_CLAMP = HIPaddress_mode_enum.define('HIP_TR_ADDRESS_MODE_CLAMP', 1) +HIP_TR_ADDRESS_MODE_MIRROR = HIPaddress_mode_enum.define('HIP_TR_ADDRESS_MODE_MIRROR', 2) +HIP_TR_ADDRESS_MODE_BORDER = HIPaddress_mode_enum.define('HIP_TR_ADDRESS_MODE_BORDER', 3) + +HIPaddress_mode = HIPaddress_mode_enum +HIPfilter_mode_enum = CEnum(ctypes.c_uint32) +HIP_TR_FILTER_MODE_POINT = HIPfilter_mode_enum.define('HIP_TR_FILTER_MODE_POINT', 0) +HIP_TR_FILTER_MODE_LINEAR = HIPfilter_mode_enum.define('HIP_TR_FILTER_MODE_LINEAR', 1) + +HIPfilter_mode = HIPfilter_mode_enum +HIP_TEXTURE_DESC_st._fields_ = [ + ('addressMode', (HIPaddress_mode * 3)), + ('filterMode', HIPfilter_mode), + ('flags', ctypes.c_uint32), + ('maxAnisotropy', ctypes.c_uint32), + ('mipmapFilterMode', HIPfilter_mode), + ('mipmapLevelBias', ctypes.c_float), + ('minMipmapLevelClamp', ctypes.c_float), + ('maxMipmapLevelClamp', ctypes.c_float), + ('borderColor', (ctypes.c_float * 4)), + ('reserved', (ctypes.c_int32 * 12)), +] +class HIP_RESOURCE_VIEW_DESC_st(Struct): pass +HIP_RESOURCE_VIEW_DESC = HIP_RESOURCE_VIEW_DESC_st +HIPresourceViewFormat_enum = CEnum(ctypes.c_uint32) +HIP_RES_VIEW_FORMAT_NONE = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_NONE', 0) +HIP_RES_VIEW_FORMAT_UINT_1X8 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_1X8', 1) +HIP_RES_VIEW_FORMAT_UINT_2X8 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_2X8', 2) +HIP_RES_VIEW_FORMAT_UINT_4X8 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_4X8', 3) +HIP_RES_VIEW_FORMAT_SINT_1X8 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_1X8', 4) +HIP_RES_VIEW_FORMAT_SINT_2X8 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_2X8', 5) +HIP_RES_VIEW_FORMAT_SINT_4X8 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_4X8', 6) +HIP_RES_VIEW_FORMAT_UINT_1X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_1X16', 7) +HIP_RES_VIEW_FORMAT_UINT_2X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_2X16', 8) +HIP_RES_VIEW_FORMAT_UINT_4X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_4X16', 9) +HIP_RES_VIEW_FORMAT_SINT_1X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_1X16', 10) +HIP_RES_VIEW_FORMAT_SINT_2X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_2X16', 11) +HIP_RES_VIEW_FORMAT_SINT_4X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_4X16', 12) +HIP_RES_VIEW_FORMAT_UINT_1X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_1X32', 13) +HIP_RES_VIEW_FORMAT_UINT_2X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_2X32', 14) +HIP_RES_VIEW_FORMAT_UINT_4X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UINT_4X32', 15) +HIP_RES_VIEW_FORMAT_SINT_1X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_1X32', 16) +HIP_RES_VIEW_FORMAT_SINT_2X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_2X32', 17) +HIP_RES_VIEW_FORMAT_SINT_4X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SINT_4X32', 18) +HIP_RES_VIEW_FORMAT_FLOAT_1X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_FLOAT_1X16', 19) +HIP_RES_VIEW_FORMAT_FLOAT_2X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_FLOAT_2X16', 20) +HIP_RES_VIEW_FORMAT_FLOAT_4X16 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_FLOAT_4X16', 21) +HIP_RES_VIEW_FORMAT_FLOAT_1X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_FLOAT_1X32', 22) +HIP_RES_VIEW_FORMAT_FLOAT_2X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_FLOAT_2X32', 23) +HIP_RES_VIEW_FORMAT_FLOAT_4X32 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_FLOAT_4X32', 24) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC1 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC1', 25) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC2 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC2', 26) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC3 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC3', 27) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC4 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC4', 28) +HIP_RES_VIEW_FORMAT_SIGNED_BC4 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SIGNED_BC4', 29) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC5 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC5', 30) +HIP_RES_VIEW_FORMAT_SIGNED_BC5 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SIGNED_BC5', 31) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC6H', 32) +HIP_RES_VIEW_FORMAT_SIGNED_BC6H = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_SIGNED_BC6H', 33) +HIP_RES_VIEW_FORMAT_UNSIGNED_BC7 = HIPresourceViewFormat_enum.define('HIP_RES_VIEW_FORMAT_UNSIGNED_BC7', 34) + +HIPresourceViewFormat = HIPresourceViewFormat_enum +HIP_RESOURCE_VIEW_DESC_st._fields_ = [ + ('format', HIPresourceViewFormat), + ('width', size_t), + ('height', size_t), + ('depth', size_t), + ('firstMipmapLevel', ctypes.c_uint32), + ('lastMipmapLevel', ctypes.c_uint32), + ('firstLayer', ctypes.c_uint32), + ('lastLayer', ctypes.c_uint32), + ('reserved', (ctypes.c_uint32 * 16)), +] +# hipError_t hipTexObjectCreate(hipTextureObject_t *pTexObject, const HIP_RESOURCE_DESC *pResDesc, const HIP_TEXTURE_DESC *pTexDesc, const HIP_RESOURCE_VIEW_DESC *pResViewDesc) +try: (hipTexObjectCreate:=dll.hipTexObjectCreate).restype, hipTexObjectCreate.argtypes = hipError_t, [ctypes.POINTER(hipTextureObject_t), ctypes.POINTER(HIP_RESOURCE_DESC), ctypes.POINTER(HIP_TEXTURE_DESC), ctypes.POINTER(HIP_RESOURCE_VIEW_DESC)] +except AttributeError: pass + +# hipError_t hipTexObjectDestroy(hipTextureObject_t texObject) +try: (hipTexObjectDestroy:=dll.hipTexObjectDestroy).restype, hipTexObjectDestroy.argtypes = hipError_t, [hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipTexObjectGetResourceDesc(HIP_RESOURCE_DESC *pResDesc, hipTextureObject_t texObject) +try: (hipTexObjectGetResourceDesc:=dll.hipTexObjectGetResourceDesc).restype, hipTexObjectGetResourceDesc.argtypes = hipError_t, [ctypes.POINTER(HIP_RESOURCE_DESC), hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipTexObjectGetResourceViewDesc(HIP_RESOURCE_VIEW_DESC *pResViewDesc, hipTextureObject_t texObject) +try: (hipTexObjectGetResourceViewDesc:=dll.hipTexObjectGetResourceViewDesc).restype, hipTexObjectGetResourceViewDesc.argtypes = hipError_t, [ctypes.POINTER(HIP_RESOURCE_VIEW_DESC), hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipTexObjectGetTextureDesc(HIP_TEXTURE_DESC *pTexDesc, hipTextureObject_t texObject) +try: (hipTexObjectGetTextureDesc:=dll.hipTexObjectGetTextureDesc).restype, hipTexObjectGetTextureDesc.argtypes = hipError_t, [ctypes.POINTER(HIP_TEXTURE_DESC), hipTextureObject_t] +except AttributeError: pass + +# hipError_t hipMallocMipmappedArray(hipMipmappedArray_t *mipmappedArray, const struct hipChannelFormatDesc *desc, struct hipExtent extent, unsigned int numLevels, unsigned int flags = 0) +try: (hipMallocMipmappedArray:=dll.hipMallocMipmappedArray).restype, hipMallocMipmappedArray.argtypes = hipError_t, [ctypes.POINTER(hipMipmappedArray_t), ctypes.POINTER(hipChannelFormatDesc), hipExtent, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipFreeMipmappedArray(hipMipmappedArray_t mipmappedArray) +try: (hipFreeMipmappedArray:=dll.hipFreeMipmappedArray).restype, hipFreeMipmappedArray.argtypes = hipError_t, [hipMipmappedArray_t] +except AttributeError: pass + +class const_hipMipmappedArray(Struct): pass +const_hipMipmappedArray._fields_ = [ + ('data', ctypes.c_void_p), + ('desc', hipChannelFormatDesc), + ('type', ctypes.c_uint32), + ('width', ctypes.c_uint32), + ('height', ctypes.c_uint32), + ('depth', ctypes.c_uint32), + ('min_mipmap_level', ctypes.c_uint32), + ('max_mipmap_level', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('format', hipArray_Format), + ('num_channels', ctypes.c_uint32), +] +hipMipmappedArray_const_t = ctypes.POINTER(const_hipMipmappedArray) +# hipError_t hipGetMipmappedArrayLevel(hipArray_t *levelArray, hipMipmappedArray_const_t mipmappedArray, unsigned int level) +try: (hipGetMipmappedArrayLevel:=dll.hipGetMipmappedArrayLevel).restype, hipGetMipmappedArrayLevel.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), hipMipmappedArray_const_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMipmappedArrayCreate(hipMipmappedArray_t *pHandle, HIP_ARRAY3D_DESCRIPTOR *pMipmappedArrayDesc, unsigned int numMipmapLevels) +try: (hipMipmappedArrayCreate:=dll.hipMipmappedArrayCreate).restype, hipMipmappedArrayCreate.argtypes = hipError_t, [ctypes.POINTER(hipMipmappedArray_t), ctypes.POINTER(HIP_ARRAY3D_DESCRIPTOR), ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipMipmappedArrayDestroy(hipMipmappedArray_t hMipmappedArray) +try: (hipMipmappedArrayDestroy:=dll.hipMipmappedArrayDestroy).restype, hipMipmappedArrayDestroy.argtypes = hipError_t, [hipMipmappedArray_t] +except AttributeError: pass + +# hipError_t hipMipmappedArrayGetLevel(hipArray_t *pLevelArray, hipMipmappedArray_t hMipMappedArray, unsigned int level) +try: (hipMipmappedArrayGetLevel:=dll.hipMipmappedArrayGetLevel).restype, hipMipmappedArrayGetLevel.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), hipMipmappedArray_t, ctypes.c_uint32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipBindTextureToMipmappedArray(const textureReference *tex, hipMipmappedArray_const_t mipmappedArray, const hipChannelFormatDesc *desc) +try: (hipBindTextureToMipmappedArray:=dll.hipBindTextureToMipmappedArray).restype, hipBindTextureToMipmappedArray.argtypes = hipError_t, [ctypes.POINTER(textureReference), hipMipmappedArray_const_t, ctypes.POINTER(hipChannelFormatDesc)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipGetTextureReference(const textureReference **texref, const void *symbol) +try: (hipGetTextureReference:=dll.hipGetTextureReference).restype, hipGetTextureReference.argtypes = hipError_t, [ctypes.POINTER(ctypes.POINTER(textureReference)), ctypes.c_void_p] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetBorderColor(float *pBorderColor, const textureReference *texRef) +try: (hipTexRefGetBorderColor:=dll.hipTexRefGetBorderColor).restype, hipTexRefGetBorderColor.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetArray(hipArray_t *pArray, const textureReference *texRef) +try: (hipTexRefGetArray:=dll.hipTexRefGetArray).restype, hipTexRefGetArray.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetAddressMode(textureReference *texRef, int dim, enum hipTextureAddressMode am) +try: (hipTexRefSetAddressMode:=dll.hipTexRefSetAddressMode).restype, hipTexRefSetAddressMode.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.c_int32, hipTextureAddressMode] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetArray(textureReference *tex, hipArray_const_t array, unsigned int flags) +try: (hipTexRefSetArray:=dll.hipTexRefSetArray).restype, hipTexRefSetArray.argtypes = hipError_t, [ctypes.POINTER(textureReference), hipArray_const_t, ctypes.c_uint32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetFilterMode(textureReference *texRef, enum hipTextureFilterMode fm) +try: (hipTexRefSetFilterMode:=dll.hipTexRefSetFilterMode).restype, hipTexRefSetFilterMode.argtypes = hipError_t, [ctypes.POINTER(textureReference), hipTextureFilterMode] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetFlags(textureReference *texRef, unsigned int Flags) +try: (hipTexRefSetFlags:=dll.hipTexRefSetFlags).restype, hipTexRefSetFlags.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.c_uint32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetFormat(textureReference *texRef, hipArray_Format fmt, int NumPackedComponents) +try: (hipTexRefSetFormat:=dll.hipTexRefSetFormat).restype, hipTexRefSetFormat.argtypes = hipError_t, [ctypes.POINTER(textureReference), hipArray_Format, ctypes.c_int32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipBindTexture(size_t *offset, const textureReference *tex, const void *devPtr, const hipChannelFormatDesc *desc, size_t size = (2147483647 * 2U + 1U)) +try: (hipBindTexture:=dll.hipBindTexture).restype, hipBindTexture.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.POINTER(textureReference), ctypes.c_void_p, ctypes.POINTER(hipChannelFormatDesc), size_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipBindTexture2D(size_t *offset, const textureReference *tex, const void *devPtr, const hipChannelFormatDesc *desc, size_t width, size_t height, size_t pitch) +try: (hipBindTexture2D:=dll.hipBindTexture2D).restype, hipBindTexture2D.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.POINTER(textureReference), ctypes.c_void_p, ctypes.POINTER(hipChannelFormatDesc), size_t, size_t, size_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipBindTextureToArray(const textureReference *tex, hipArray_const_t array, const hipChannelFormatDesc *desc) +try: (hipBindTextureToArray:=dll.hipBindTextureToArray).restype, hipBindTextureToArray.argtypes = hipError_t, [ctypes.POINTER(textureReference), hipArray_const_t, ctypes.POINTER(hipChannelFormatDesc)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipGetTextureAlignmentOffset(size_t *offset, const textureReference *texref) +try: (hipGetTextureAlignmentOffset:=dll.hipGetTextureAlignmentOffset).restype, hipGetTextureAlignmentOffset.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipUnbindTexture(const textureReference *tex) +try: (hipUnbindTexture:=dll.hipUnbindTexture).restype, hipUnbindTexture.argtypes = hipError_t, [ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetAddress(hipDeviceptr_t *dev_ptr, const textureReference *texRef) +try: (hipTexRefGetAddress:=dll.hipTexRefGetAddress).restype, hipTexRefGetAddress.argtypes = hipError_t, [ctypes.POINTER(hipDeviceptr_t), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetAddressMode(enum hipTextureAddressMode *pam, const textureReference *texRef, int dim) +try: (hipTexRefGetAddressMode:=dll.hipTexRefGetAddressMode).restype, hipTexRefGetAddressMode.argtypes = hipError_t, [ctypes.POINTER(hipTextureAddressMode), ctypes.POINTER(textureReference), ctypes.c_int32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetFilterMode(enum hipTextureFilterMode *pfm, const textureReference *texRef) +try: (hipTexRefGetFilterMode:=dll.hipTexRefGetFilterMode).restype, hipTexRefGetFilterMode.argtypes = hipError_t, [ctypes.POINTER(hipTextureFilterMode), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetFlags(unsigned int *pFlags, const textureReference *texRef) +try: (hipTexRefGetFlags:=dll.hipTexRefGetFlags).restype, hipTexRefGetFlags.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetFormat(hipArray_Format *pFormat, int *pNumChannels, const textureReference *texRef) +try: (hipTexRefGetFormat:=dll.hipTexRefGetFormat).restype, hipTexRefGetFormat.argtypes = hipError_t, [ctypes.POINTER(hipArray_Format), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetMaxAnisotropy(int *pmaxAnsio, const textureReference *texRef) +try: (hipTexRefGetMaxAnisotropy:=dll.hipTexRefGetMaxAnisotropy).restype, hipTexRefGetMaxAnisotropy.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetMipmapFilterMode(enum hipTextureFilterMode *pfm, const textureReference *texRef) +try: (hipTexRefGetMipmapFilterMode:=dll.hipTexRefGetMipmapFilterMode).restype, hipTexRefGetMipmapFilterMode.argtypes = hipError_t, [ctypes.POINTER(hipTextureFilterMode), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetMipmapLevelBias(float *pbias, const textureReference *texRef) +try: (hipTexRefGetMipmapLevelBias:=dll.hipTexRefGetMipmapLevelBias).restype, hipTexRefGetMipmapLevelBias.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetMipmapLevelClamp(float *pminMipmapLevelClamp, float *pmaxMipmapLevelClamp, const textureReference *texRef) +try: (hipTexRefGetMipmapLevelClamp:=dll.hipTexRefGetMipmapLevelClamp).restype, hipTexRefGetMipmapLevelClamp.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_float), ctypes.POINTER(ctypes.c_float), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefGetMipMappedArray(hipMipmappedArray_t *pArray, const textureReference *texRef) +try: (hipTexRefGetMipMappedArray:=dll.hipTexRefGetMipMappedArray).restype, hipTexRefGetMipMappedArray.argtypes = hipError_t, [ctypes.POINTER(hipMipmappedArray_t), ctypes.POINTER(textureReference)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetAddress(size_t *ByteOffset, textureReference *texRef, hipDeviceptr_t dptr, size_t bytes) +try: (hipTexRefSetAddress:=dll.hipTexRefSetAddress).restype, hipTexRefSetAddress.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.POINTER(textureReference), hipDeviceptr_t, size_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetAddress2D(textureReference *texRef, const HIP_ARRAY_DESCRIPTOR *desc, hipDeviceptr_t dptr, size_t Pitch) +try: (hipTexRefSetAddress2D:=dll.hipTexRefSetAddress2D).restype, hipTexRefSetAddress2D.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.POINTER(HIP_ARRAY_DESCRIPTOR), hipDeviceptr_t, size_t] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetMaxAnisotropy(textureReference *texRef, unsigned int maxAniso) +try: (hipTexRefSetMaxAnisotropy:=dll.hipTexRefSetMaxAnisotropy).restype, hipTexRefSetMaxAnisotropy.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.c_uint32] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetBorderColor(textureReference *texRef, float *pBorderColor) +try: (hipTexRefSetBorderColor:=dll.hipTexRefSetBorderColor).restype, hipTexRefSetBorderColor.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.POINTER(ctypes.c_float)] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetMipmapFilterMode(textureReference *texRef, enum hipTextureFilterMode fm) +try: (hipTexRefSetMipmapFilterMode:=dll.hipTexRefSetMipmapFilterMode).restype, hipTexRefSetMipmapFilterMode.argtypes = hipError_t, [ctypes.POINTER(textureReference), hipTextureFilterMode] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetMipmapLevelBias(textureReference *texRef, float bias) +try: (hipTexRefSetMipmapLevelBias:=dll.hipTexRefSetMipmapLevelBias).restype, hipTexRefSetMipmapLevelBias.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.c_float] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetMipmapLevelClamp(textureReference *texRef, float minMipMapLevelClamp, float maxMipMapLevelClamp) +try: (hipTexRefSetMipmapLevelClamp:=dll.hipTexRefSetMipmapLevelClamp).restype, hipTexRefSetMipmapLevelClamp.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.c_float, ctypes.c_float] +except AttributeError: pass + +# __attribute__((deprecated("This API is marked as deprecated and may not be supported in future releases. For more details please refer https://github.com/ROCm/HIP/blob/develop/docs/reference/deprecated_api_list.md"))) hipError_t hipTexRefSetMipmappedArray(textureReference *texRef, struct hipMipmappedArray *mipmappedArray, unsigned int Flags) +try: (hipTexRefSetMipmappedArray:=dll.hipTexRefSetMipmappedArray).restype, hipTexRefSetMipmappedArray.argtypes = hipError_t, [ctypes.POINTER(textureReference), ctypes.POINTER(hipMipmappedArray), ctypes.c_uint32] +except AttributeError: pass + +# const char *hipApiName(uint32_t id) +try: (hipApiName:=dll.hipApiName).restype, hipApiName.argtypes = ctypes.POINTER(ctypes.c_char), [uint32_t] +except AttributeError: pass + +# const char *hipKernelNameRef(const hipFunction_t f) +try: (hipKernelNameRef:=dll.hipKernelNameRef).restype, hipKernelNameRef.argtypes = ctypes.POINTER(ctypes.c_char), [hipFunction_t] +except AttributeError: pass + +# const char *hipKernelNameRefByPtr(const void *hostFunction, hipStream_t stream) +try: (hipKernelNameRefByPtr:=dll.hipKernelNameRefByPtr).restype, hipKernelNameRefByPtr.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_void_p, hipStream_t] +except AttributeError: pass + +# int hipGetStreamDeviceId(hipStream_t stream) +try: (hipGetStreamDeviceId:=dll.hipGetStreamDeviceId).restype, hipGetStreamDeviceId.argtypes = ctypes.c_int32, [hipStream_t] +except AttributeError: pass + +# hipError_t hipStreamBeginCapture(hipStream_t stream, hipStreamCaptureMode mode) +try: (hipStreamBeginCapture:=dll.hipStreamBeginCapture).restype, hipStreamBeginCapture.argtypes = hipError_t, [hipStream_t, hipStreamCaptureMode] +except AttributeError: pass + +# hipError_t hipStreamBeginCaptureToGraph(hipStream_t stream, hipGraph_t graph, const hipGraphNode_t *dependencies, const hipGraphEdgeData *dependencyData, size_t numDependencies, hipStreamCaptureMode mode) +try: (hipStreamBeginCaptureToGraph:=dll.hipStreamBeginCaptureToGraph).restype, hipStreamBeginCaptureToGraph.argtypes = hipError_t, [hipStream_t, hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(hipGraphEdgeData), size_t, hipStreamCaptureMode] +except AttributeError: pass + +# hipError_t hipStreamEndCapture(hipStream_t stream, hipGraph_t *pGraph) +try: (hipStreamEndCapture:=dll.hipStreamEndCapture).restype, hipStreamEndCapture.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(hipGraph_t)] +except AttributeError: pass + +# hipError_t hipStreamGetCaptureInfo(hipStream_t stream, hipStreamCaptureStatus *pCaptureStatus, unsigned long long *pId) +try: (hipStreamGetCaptureInfo:=dll.hipStreamGetCaptureInfo).restype, hipStreamGetCaptureInfo.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus), ctypes.POINTER(ctypes.c_uint64)] +except AttributeError: pass + +# hipError_t hipStreamGetCaptureInfo_v2(hipStream_t stream, hipStreamCaptureStatus *captureStatus_out, unsigned long long *id_out = 0, hipGraph_t *graph_out = 0, const hipGraphNode_t **dependencies_out = 0, size_t *numDependencies_out = 0) +try: (hipStreamGetCaptureInfo_v2:=dll.hipStreamGetCaptureInfo_v2).restype, hipStreamGetCaptureInfo_v2.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(hipGraph_t), ctypes.POINTER(ctypes.POINTER(hipGraphNode_t)), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipStreamIsCapturing(hipStream_t stream, hipStreamCaptureStatus *pCaptureStatus) +try: (hipStreamIsCapturing:=dll.hipStreamIsCapturing).restype, hipStreamIsCapturing.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(hipStreamCaptureStatus)] +except AttributeError: pass + +# hipError_t hipStreamUpdateCaptureDependencies(hipStream_t stream, hipGraphNode_t *dependencies, size_t numDependencies, unsigned int flags = 0) +try: (hipStreamUpdateCaptureDependencies:=dll.hipStreamUpdateCaptureDependencies).restype, hipStreamUpdateCaptureDependencies.argtypes = hipError_t, [hipStream_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipThreadExchangeStreamCaptureMode(hipStreamCaptureMode *mode) +try: (hipThreadExchangeStreamCaptureMode:=dll.hipThreadExchangeStreamCaptureMode).restype, hipThreadExchangeStreamCaptureMode.argtypes = hipError_t, [ctypes.POINTER(hipStreamCaptureMode)] +except AttributeError: pass + +# hipError_t hipGraphCreate(hipGraph_t *pGraph, unsigned int flags) +try: (hipGraphCreate:=dll.hipGraphCreate).restype, hipGraphCreate.argtypes = hipError_t, [ctypes.POINTER(hipGraph_t), ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphDestroy(hipGraph_t graph) +try: (hipGraphDestroy:=dll.hipGraphDestroy).restype, hipGraphDestroy.argtypes = hipError_t, [hipGraph_t] +except AttributeError: pass + +# hipError_t hipGraphAddDependencies(hipGraph_t graph, const hipGraphNode_t *from, const hipGraphNode_t *to, size_t numDependencies) +try: (hipGraphAddDependencies:=dll.hipGraphAddDependencies).restype, hipGraphAddDependencies.argtypes = hipError_t, [hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(hipGraphNode_t), size_t] +except AttributeError: pass + +# hipError_t hipGraphRemoveDependencies(hipGraph_t graph, const hipGraphNode_t *from, const hipGraphNode_t *to, size_t numDependencies) +try: (hipGraphRemoveDependencies:=dll.hipGraphRemoveDependencies).restype, hipGraphRemoveDependencies.argtypes = hipError_t, [hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(hipGraphNode_t), size_t] +except AttributeError: pass + +# hipError_t hipGraphGetEdges(hipGraph_t graph, hipGraphNode_t *from, hipGraphNode_t *to, size_t *numEdges) +try: (hipGraphGetEdges:=dll.hipGraphGetEdges).restype, hipGraphGetEdges.argtypes = hipError_t, [hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipGraphGetNodes(hipGraph_t graph, hipGraphNode_t *nodes, size_t *numNodes) +try: (hipGraphGetNodes:=dll.hipGraphGetNodes).restype, hipGraphGetNodes.argtypes = hipError_t, [hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipGraphGetRootNodes(hipGraph_t graph, hipGraphNode_t *pRootNodes, size_t *pNumRootNodes) +try: (hipGraphGetRootNodes:=dll.hipGraphGetRootNodes).restype, hipGraphGetRootNodes.argtypes = hipError_t, [hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipGraphNodeGetDependencies(hipGraphNode_t node, hipGraphNode_t *pDependencies, size_t *pNumDependencies) +try: (hipGraphNodeGetDependencies:=dll.hipGraphNodeGetDependencies).restype, hipGraphNodeGetDependencies.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipGraphNodeGetDependentNodes(hipGraphNode_t node, hipGraphNode_t *pDependentNodes, size_t *pNumDependentNodes) +try: (hipGraphNodeGetDependentNodes:=dll.hipGraphNodeGetDependentNodes).restype, hipGraphNodeGetDependentNodes.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(size_t)] +except AttributeError: pass + +# hipError_t hipGraphNodeGetType(hipGraphNode_t node, hipGraphNodeType *pType) +try: (hipGraphNodeGetType:=dll.hipGraphNodeGetType).restype, hipGraphNodeGetType.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipGraphNodeType)] +except AttributeError: pass + +# hipError_t hipGraphDestroyNode(hipGraphNode_t node) +try: (hipGraphDestroyNode:=dll.hipGraphDestroyNode).restype, hipGraphDestroyNode.argtypes = hipError_t, [hipGraphNode_t] +except AttributeError: pass + +# hipError_t hipGraphClone(hipGraph_t *pGraphClone, hipGraph_t originalGraph) +try: (hipGraphClone:=dll.hipGraphClone).restype, hipGraphClone.argtypes = hipError_t, [ctypes.POINTER(hipGraph_t), hipGraph_t] +except AttributeError: pass + +# hipError_t hipGraphNodeFindInClone(hipGraphNode_t *pNode, hipGraphNode_t originalNode, hipGraph_t clonedGraph) +try: (hipGraphNodeFindInClone:=dll.hipGraphNodeFindInClone).restype, hipGraphNodeFindInClone.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraphNode_t, hipGraph_t] +except AttributeError: pass + +# hipError_t hipGraphInstantiate(hipGraphExec_t *pGraphExec, hipGraph_t graph, hipGraphNode_t *pErrorNode, char *pLogBuffer, size_t bufferSize) +try: (hipGraphInstantiate:=dll.hipGraphInstantiate).restype, hipGraphInstantiate.argtypes = hipError_t, [ctypes.POINTER(hipGraphExec_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# hipError_t hipGraphInstantiateWithFlags(hipGraphExec_t *pGraphExec, hipGraph_t graph, unsigned long long flags) +try: (hipGraphInstantiateWithFlags:=dll.hipGraphInstantiateWithFlags).restype, hipGraphInstantiateWithFlags.argtypes = hipError_t, [ctypes.POINTER(hipGraphExec_t), hipGraph_t, ctypes.c_uint64] +except AttributeError: pass + +# hipError_t hipGraphInstantiateWithParams(hipGraphExec_t *pGraphExec, hipGraph_t graph, hipGraphInstantiateParams *instantiateParams) +try: (hipGraphInstantiateWithParams:=dll.hipGraphInstantiateWithParams).restype, hipGraphInstantiateWithParams.argtypes = hipError_t, [ctypes.POINTER(hipGraphExec_t), hipGraph_t, ctypes.POINTER(hipGraphInstantiateParams)] +except AttributeError: pass + +# hipError_t hipGraphLaunch(hipGraphExec_t graphExec, hipStream_t stream) +try: (hipGraphLaunch:=dll.hipGraphLaunch).restype, hipGraphLaunch.argtypes = hipError_t, [hipGraphExec_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipGraphUpload(hipGraphExec_t graphExec, hipStream_t stream) +try: (hipGraphUpload:=dll.hipGraphUpload).restype, hipGraphUpload.argtypes = hipError_t, [hipGraphExec_t, hipStream_t] +except AttributeError: pass + +# hipError_t hipGraphAddNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, hipGraphNodeParams *nodeParams) +try: (hipGraphAddNode:=dll.hipGraphAddNode).restype, hipGraphAddNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipGraphNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExecDestroy(hipGraphExec_t graphExec) +try: (hipGraphExecDestroy:=dll.hipGraphExecDestroy).restype, hipGraphExecDestroy.argtypes = hipError_t, [hipGraphExec_t] +except AttributeError: pass + +# hipError_t hipGraphExecUpdate(hipGraphExec_t hGraphExec, hipGraph_t hGraph, hipGraphNode_t *hErrorNode_out, hipGraphExecUpdateResult *updateResult_out) +try: (hipGraphExecUpdate:=dll.hipGraphExecUpdate).restype, hipGraphExecUpdate.argtypes = hipError_t, [hipGraphExec_t, hipGraph_t, ctypes.POINTER(hipGraphNode_t), ctypes.POINTER(hipGraphExecUpdateResult)] +except AttributeError: pass + +# hipError_t hipGraphAddKernelNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const hipKernelNodeParams *pNodeParams) +try: (hipGraphAddKernelNode:=dll.hipGraphAddKernelNode).restype, hipGraphAddKernelNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipKernelNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphKernelNodeGetParams(hipGraphNode_t node, hipKernelNodeParams *pNodeParams) +try: (hipGraphKernelNodeGetParams:=dll.hipGraphKernelNodeGetParams).restype, hipGraphKernelNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipKernelNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphKernelNodeSetParams(hipGraphNode_t node, const hipKernelNodeParams *pNodeParams) +try: (hipGraphKernelNodeSetParams:=dll.hipGraphKernelNodeSetParams).restype, hipGraphKernelNodeSetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipKernelNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExecKernelNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t node, const hipKernelNodeParams *pNodeParams) +try: (hipGraphExecKernelNodeSetParams:=dll.hipGraphExecKernelNodeSetParams).restype, hipGraphExecKernelNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(hipKernelNodeParams)] +except AttributeError: pass + +# hipError_t hipDrvGraphAddMemcpyNode(hipGraphNode_t *phGraphNode, hipGraph_t hGraph, const hipGraphNode_t *dependencies, size_t numDependencies, const HIP_MEMCPY3D *copyParams, hipCtx_t ctx) +try: (hipDrvGraphAddMemcpyNode:=dll.hipDrvGraphAddMemcpyNode).restype, hipDrvGraphAddMemcpyNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(HIP_MEMCPY3D), hipCtx_t] +except AttributeError: pass + +# hipError_t hipGraphAddMemcpyNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const hipMemcpy3DParms *pCopyParams) +try: (hipGraphAddMemcpyNode:=dll.hipGraphAddMemcpyNode).restype, hipGraphAddMemcpyNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipMemcpy3DParms)] +except AttributeError: pass + +# hipError_t hipGraphMemcpyNodeGetParams(hipGraphNode_t node, hipMemcpy3DParms *pNodeParams) +try: (hipGraphMemcpyNodeGetParams:=dll.hipGraphMemcpyNodeGetParams).restype, hipGraphMemcpyNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipMemcpy3DParms)] +except AttributeError: pass + +# hipError_t hipGraphMemcpyNodeSetParams(hipGraphNode_t node, const hipMemcpy3DParms *pNodeParams) +try: (hipGraphMemcpyNodeSetParams:=dll.hipGraphMemcpyNodeSetParams).restype, hipGraphMemcpyNodeSetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipMemcpy3DParms)] +except AttributeError: pass + +# hipError_t hipGraphKernelNodeSetAttribute(hipGraphNode_t hNode, hipLaunchAttributeID attr, const hipLaunchAttributeValue *value) +try: (hipGraphKernelNodeSetAttribute:=dll.hipGraphKernelNodeSetAttribute).restype, hipGraphKernelNodeSetAttribute.argtypes = hipError_t, [hipGraphNode_t, hipLaunchAttributeID, ctypes.POINTER(hipLaunchAttributeValue)] +except AttributeError: pass + +# hipError_t hipGraphKernelNodeGetAttribute(hipGraphNode_t hNode, hipLaunchAttributeID attr, hipLaunchAttributeValue *value) +try: (hipGraphKernelNodeGetAttribute:=dll.hipGraphKernelNodeGetAttribute).restype, hipGraphKernelNodeGetAttribute.argtypes = hipError_t, [hipGraphNode_t, hipLaunchAttributeID, ctypes.POINTER(hipLaunchAttributeValue)] +except AttributeError: pass + +# hipError_t hipGraphExecMemcpyNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t node, hipMemcpy3DParms *pNodeParams) +try: (hipGraphExecMemcpyNodeSetParams:=dll.hipGraphExecMemcpyNodeSetParams).restype, hipGraphExecMemcpyNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(hipMemcpy3DParms)] +except AttributeError: pass + +# hipError_t hipGraphAddMemcpyNode1D(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, void *dst, const void *src, size_t count, hipMemcpyKind kind) +try: (hipGraphAddMemcpyNode1D:=dll.hipGraphAddMemcpyNode1D).restype, hipGraphAddMemcpyNode1D.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.c_void_p, ctypes.c_void_p, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphMemcpyNodeSetParams1D(hipGraphNode_t node, void *dst, const void *src, size_t count, hipMemcpyKind kind) +try: (hipGraphMemcpyNodeSetParams1D:=dll.hipGraphMemcpyNodeSetParams1D).restype, hipGraphMemcpyNodeSetParams1D.argtypes = hipError_t, [hipGraphNode_t, ctypes.c_void_p, ctypes.c_void_p, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphExecMemcpyNodeSetParams1D(hipGraphExec_t hGraphExec, hipGraphNode_t node, void *dst, const void *src, size_t count, hipMemcpyKind kind) +try: (hipGraphExecMemcpyNodeSetParams1D:=dll.hipGraphExecMemcpyNodeSetParams1D).restype, hipGraphExecMemcpyNodeSetParams1D.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.c_void_p, ctypes.c_void_p, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphAddMemcpyNodeFromSymbol(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, void *dst, const void *symbol, size_t count, size_t offset, hipMemcpyKind kind) +try: (hipGraphAddMemcpyNodeFromSymbol:=dll.hipGraphAddMemcpyNodeFromSymbol).restype, hipGraphAddMemcpyNodeFromSymbol.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphMemcpyNodeSetParamsFromSymbol(hipGraphNode_t node, void *dst, const void *symbol, size_t count, size_t offset, hipMemcpyKind kind) +try: (hipGraphMemcpyNodeSetParamsFromSymbol:=dll.hipGraphMemcpyNodeSetParamsFromSymbol).restype, hipGraphMemcpyNodeSetParamsFromSymbol.argtypes = hipError_t, [hipGraphNode_t, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphExecMemcpyNodeSetParamsFromSymbol(hipGraphExec_t hGraphExec, hipGraphNode_t node, void *dst, const void *symbol, size_t count, size_t offset, hipMemcpyKind kind) +try: (hipGraphExecMemcpyNodeSetParamsFromSymbol:=dll.hipGraphExecMemcpyNodeSetParamsFromSymbol).restype, hipGraphExecMemcpyNodeSetParamsFromSymbol.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphAddMemcpyNodeToSymbol(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const void *symbol, const void *src, size_t count, size_t offset, hipMemcpyKind kind) +try: (hipGraphAddMemcpyNodeToSymbol:=dll.hipGraphAddMemcpyNodeToSymbol).restype, hipGraphAddMemcpyNodeToSymbol.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphMemcpyNodeSetParamsToSymbol(hipGraphNode_t node, const void *symbol, const void *src, size_t count, size_t offset, hipMemcpyKind kind) +try: (hipGraphMemcpyNodeSetParamsToSymbol:=dll.hipGraphMemcpyNodeSetParamsToSymbol).restype, hipGraphMemcpyNodeSetParamsToSymbol.argtypes = hipError_t, [hipGraphNode_t, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphExecMemcpyNodeSetParamsToSymbol(hipGraphExec_t hGraphExec, hipGraphNode_t node, const void *symbol, const void *src, size_t count, size_t offset, hipMemcpyKind kind) +try: (hipGraphExecMemcpyNodeSetParamsToSymbol:=dll.hipGraphExecMemcpyNodeSetParamsToSymbol).restype, hipGraphExecMemcpyNodeSetParamsToSymbol.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, hipMemcpyKind] +except AttributeError: pass + +# hipError_t hipGraphAddMemsetNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const hipMemsetParams *pMemsetParams) +try: (hipGraphAddMemsetNode:=dll.hipGraphAddMemsetNode).restype, hipGraphAddMemsetNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipMemsetParams)] +except AttributeError: pass + +# hipError_t hipGraphMemsetNodeGetParams(hipGraphNode_t node, hipMemsetParams *pNodeParams) +try: (hipGraphMemsetNodeGetParams:=dll.hipGraphMemsetNodeGetParams).restype, hipGraphMemsetNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipMemsetParams)] +except AttributeError: pass + +# hipError_t hipGraphMemsetNodeSetParams(hipGraphNode_t node, const hipMemsetParams *pNodeParams) +try: (hipGraphMemsetNodeSetParams:=dll.hipGraphMemsetNodeSetParams).restype, hipGraphMemsetNodeSetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipMemsetParams)] +except AttributeError: pass + +# hipError_t hipGraphExecMemsetNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t node, const hipMemsetParams *pNodeParams) +try: (hipGraphExecMemsetNodeSetParams:=dll.hipGraphExecMemsetNodeSetParams).restype, hipGraphExecMemsetNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(hipMemsetParams)] +except AttributeError: pass + +# hipError_t hipGraphAddHostNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const hipHostNodeParams *pNodeParams) +try: (hipGraphAddHostNode:=dll.hipGraphAddHostNode).restype, hipGraphAddHostNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipHostNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphHostNodeGetParams(hipGraphNode_t node, hipHostNodeParams *pNodeParams) +try: (hipGraphHostNodeGetParams:=dll.hipGraphHostNodeGetParams).restype, hipGraphHostNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipHostNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphHostNodeSetParams(hipGraphNode_t node, const hipHostNodeParams *pNodeParams) +try: (hipGraphHostNodeSetParams:=dll.hipGraphHostNodeSetParams).restype, hipGraphHostNodeSetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipHostNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExecHostNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t node, const hipHostNodeParams *pNodeParams) +try: (hipGraphExecHostNodeSetParams:=dll.hipGraphExecHostNodeSetParams).restype, hipGraphExecHostNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(hipHostNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphAddChildGraphNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, hipGraph_t childGraph) +try: (hipGraphAddChildGraphNode:=dll.hipGraphAddChildGraphNode).restype, hipGraphAddChildGraphNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, hipGraph_t] +except AttributeError: pass + +# hipError_t hipGraphChildGraphNodeGetGraph(hipGraphNode_t node, hipGraph_t *pGraph) +try: (hipGraphChildGraphNodeGetGraph:=dll.hipGraphChildGraphNodeGetGraph).restype, hipGraphChildGraphNodeGetGraph.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipGraph_t)] +except AttributeError: pass + +# hipError_t hipGraphExecChildGraphNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t node, hipGraph_t childGraph) +try: (hipGraphExecChildGraphNodeSetParams:=dll.hipGraphExecChildGraphNodeSetParams).restype, hipGraphExecChildGraphNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, hipGraph_t] +except AttributeError: pass + +# hipError_t hipGraphAddEmptyNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies) +try: (hipGraphAddEmptyNode:=dll.hipGraphAddEmptyNode).restype, hipGraphAddEmptyNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t] +except AttributeError: pass + +# hipError_t hipGraphAddEventRecordNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, hipEvent_t event) +try: (hipGraphAddEventRecordNode:=dll.hipGraphAddEventRecordNode).restype, hipGraphAddEventRecordNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipGraphEventRecordNodeGetEvent(hipGraphNode_t node, hipEvent_t *event_out) +try: (hipGraphEventRecordNodeGetEvent:=dll.hipGraphEventRecordNodeGetEvent).restype, hipGraphEventRecordNodeGetEvent.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipEvent_t)] +except AttributeError: pass + +# hipError_t hipGraphEventRecordNodeSetEvent(hipGraphNode_t node, hipEvent_t event) +try: (hipGraphEventRecordNodeSetEvent:=dll.hipGraphEventRecordNodeSetEvent).restype, hipGraphEventRecordNodeSetEvent.argtypes = hipError_t, [hipGraphNode_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipGraphExecEventRecordNodeSetEvent(hipGraphExec_t hGraphExec, hipGraphNode_t hNode, hipEvent_t event) +try: (hipGraphExecEventRecordNodeSetEvent:=dll.hipGraphExecEventRecordNodeSetEvent).restype, hipGraphExecEventRecordNodeSetEvent.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipGraphAddEventWaitNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, hipEvent_t event) +try: (hipGraphAddEventWaitNode:=dll.hipGraphAddEventWaitNode).restype, hipGraphAddEventWaitNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipGraphEventWaitNodeGetEvent(hipGraphNode_t node, hipEvent_t *event_out) +try: (hipGraphEventWaitNodeGetEvent:=dll.hipGraphEventWaitNodeGetEvent).restype, hipGraphEventWaitNodeGetEvent.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipEvent_t)] +except AttributeError: pass + +# hipError_t hipGraphEventWaitNodeSetEvent(hipGraphNode_t node, hipEvent_t event) +try: (hipGraphEventWaitNodeSetEvent:=dll.hipGraphEventWaitNodeSetEvent).restype, hipGraphEventWaitNodeSetEvent.argtypes = hipError_t, [hipGraphNode_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipGraphExecEventWaitNodeSetEvent(hipGraphExec_t hGraphExec, hipGraphNode_t hNode, hipEvent_t event) +try: (hipGraphExecEventWaitNodeSetEvent:=dll.hipGraphExecEventWaitNodeSetEvent).restype, hipGraphExecEventWaitNodeSetEvent.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, hipEvent_t] +except AttributeError: pass + +# hipError_t hipGraphAddMemAllocNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, hipMemAllocNodeParams *pNodeParams) +try: (hipGraphAddMemAllocNode:=dll.hipGraphAddMemAllocNode).restype, hipGraphAddMemAllocNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipMemAllocNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphMemAllocNodeGetParams(hipGraphNode_t node, hipMemAllocNodeParams *pNodeParams) +try: (hipGraphMemAllocNodeGetParams:=dll.hipGraphMemAllocNodeGetParams).restype, hipGraphMemAllocNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipMemAllocNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphAddMemFreeNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, void *dev_ptr) +try: (hipGraphAddMemFreeNode:=dll.hipGraphAddMemFreeNode).restype, hipGraphAddMemFreeNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipGraphMemFreeNodeGetParams(hipGraphNode_t node, void *dev_ptr) +try: (hipGraphMemFreeNodeGetParams:=dll.hipGraphMemFreeNodeGetParams).restype, hipGraphMemFreeNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipDeviceGetGraphMemAttribute(int device, hipGraphMemAttributeType attr, void *value) +try: (hipDeviceGetGraphMemAttribute:=dll.hipDeviceGetGraphMemAttribute).restype, hipDeviceGetGraphMemAttribute.argtypes = hipError_t, [ctypes.c_int32, hipGraphMemAttributeType, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipDeviceSetGraphMemAttribute(int device, hipGraphMemAttributeType attr, void *value) +try: (hipDeviceSetGraphMemAttribute:=dll.hipDeviceSetGraphMemAttribute).restype, hipDeviceSetGraphMemAttribute.argtypes = hipError_t, [ctypes.c_int32, hipGraphMemAttributeType, ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipDeviceGraphMemTrim(int device) +try: (hipDeviceGraphMemTrim:=dll.hipDeviceGraphMemTrim).restype, hipDeviceGraphMemTrim.argtypes = hipError_t, [ctypes.c_int32] +except AttributeError: pass + +# hipError_t hipUserObjectCreate(hipUserObject_t *object_out, void *ptr, hipHostFn_t destroy, unsigned int initialRefcount, unsigned int flags) +try: (hipUserObjectCreate:=dll.hipUserObjectCreate).restype, hipUserObjectCreate.argtypes = hipError_t, [ctypes.POINTER(hipUserObject_t), ctypes.c_void_p, hipHostFn_t, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipUserObjectRelease(hipUserObject_t object, unsigned int count = 1) +try: (hipUserObjectRelease:=dll.hipUserObjectRelease).restype, hipUserObjectRelease.argtypes = hipError_t, [hipUserObject_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipUserObjectRetain(hipUserObject_t object, unsigned int count = 1) +try: (hipUserObjectRetain:=dll.hipUserObjectRetain).restype, hipUserObjectRetain.argtypes = hipError_t, [hipUserObject_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphRetainUserObject(hipGraph_t graph, hipUserObject_t object, unsigned int count = 1, unsigned int flags = 0) +try: (hipGraphRetainUserObject:=dll.hipGraphRetainUserObject).restype, hipGraphRetainUserObject.argtypes = hipError_t, [hipGraph_t, hipUserObject_t, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphReleaseUserObject(hipGraph_t graph, hipUserObject_t object, unsigned int count = 1) +try: (hipGraphReleaseUserObject:=dll.hipGraphReleaseUserObject).restype, hipGraphReleaseUserObject.argtypes = hipError_t, [hipGraph_t, hipUserObject_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphDebugDotPrint(hipGraph_t graph, const char *path, unsigned int flags) +try: (hipGraphDebugDotPrint:=dll.hipGraphDebugDotPrint).restype, hipGraphDebugDotPrint.argtypes = hipError_t, [hipGraph_t, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphKernelNodeCopyAttributes(hipGraphNode_t hSrc, hipGraphNode_t hDst) +try: (hipGraphKernelNodeCopyAttributes:=dll.hipGraphKernelNodeCopyAttributes).restype, hipGraphKernelNodeCopyAttributes.argtypes = hipError_t, [hipGraphNode_t, hipGraphNode_t] +except AttributeError: pass + +# hipError_t hipGraphNodeSetEnabled(hipGraphExec_t hGraphExec, hipGraphNode_t hNode, unsigned int isEnabled) +try: (hipGraphNodeSetEnabled:=dll.hipGraphNodeSetEnabled).restype, hipGraphNodeSetEnabled.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphNodeGetEnabled(hipGraphExec_t hGraphExec, hipGraphNode_t hNode, unsigned int *isEnabled) +try: (hipGraphNodeGetEnabled:=dll.hipGraphNodeGetEnabled).restype, hipGraphNodeGetEnabled.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# hipError_t hipGraphAddExternalSemaphoresWaitNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const hipExternalSemaphoreWaitNodeParams *nodeParams) +try: (hipGraphAddExternalSemaphoresWaitNode:=dll.hipGraphAddExternalSemaphoresWaitNode).restype, hipGraphAddExternalSemaphoresWaitNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipExternalSemaphoreWaitNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphAddExternalSemaphoresSignalNode(hipGraphNode_t *pGraphNode, hipGraph_t graph, const hipGraphNode_t *pDependencies, size_t numDependencies, const hipExternalSemaphoreSignalNodeParams *nodeParams) +try: (hipGraphAddExternalSemaphoresSignalNode:=dll.hipGraphAddExternalSemaphoresSignalNode).restype, hipGraphAddExternalSemaphoresSignalNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(hipExternalSemaphoreSignalNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExternalSemaphoresSignalNodeSetParams(hipGraphNode_t hNode, const hipExternalSemaphoreSignalNodeParams *nodeParams) +try: (hipGraphExternalSemaphoresSignalNodeSetParams:=dll.hipGraphExternalSemaphoresSignalNodeSetParams).restype, hipGraphExternalSemaphoresSignalNodeSetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipExternalSemaphoreSignalNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExternalSemaphoresWaitNodeSetParams(hipGraphNode_t hNode, const hipExternalSemaphoreWaitNodeParams *nodeParams) +try: (hipGraphExternalSemaphoresWaitNodeSetParams:=dll.hipGraphExternalSemaphoresWaitNodeSetParams).restype, hipGraphExternalSemaphoresWaitNodeSetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipExternalSemaphoreWaitNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExternalSemaphoresSignalNodeGetParams(hipGraphNode_t hNode, hipExternalSemaphoreSignalNodeParams *params_out) +try: (hipGraphExternalSemaphoresSignalNodeGetParams:=dll.hipGraphExternalSemaphoresSignalNodeGetParams).restype, hipGraphExternalSemaphoresSignalNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipExternalSemaphoreSignalNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExternalSemaphoresWaitNodeGetParams(hipGraphNode_t hNode, hipExternalSemaphoreWaitNodeParams *params_out) +try: (hipGraphExternalSemaphoresWaitNodeGetParams:=dll.hipGraphExternalSemaphoresWaitNodeGetParams).restype, hipGraphExternalSemaphoresWaitNodeGetParams.argtypes = hipError_t, [hipGraphNode_t, ctypes.POINTER(hipExternalSemaphoreWaitNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExecExternalSemaphoresSignalNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t hNode, const hipExternalSemaphoreSignalNodeParams *nodeParams) +try: (hipGraphExecExternalSemaphoresSignalNodeSetParams:=dll.hipGraphExecExternalSemaphoresSignalNodeSetParams).restype, hipGraphExecExternalSemaphoresSignalNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(hipExternalSemaphoreSignalNodeParams)] +except AttributeError: pass + +# hipError_t hipGraphExecExternalSemaphoresWaitNodeSetParams(hipGraphExec_t hGraphExec, hipGraphNode_t hNode, const hipExternalSemaphoreWaitNodeParams *nodeParams) +try: (hipGraphExecExternalSemaphoresWaitNodeSetParams:=dll.hipGraphExecExternalSemaphoresWaitNodeSetParams).restype, hipGraphExecExternalSemaphoresWaitNodeSetParams.argtypes = hipError_t, [hipGraphExec_t, hipGraphNode_t, ctypes.POINTER(hipExternalSemaphoreWaitNodeParams)] +except AttributeError: pass + +# hipError_t hipDrvGraphAddMemsetNode(hipGraphNode_t *phGraphNode, hipGraph_t hGraph, const hipGraphNode_t *dependencies, size_t numDependencies, const HIP_MEMSET_NODE_PARAMS *memsetParams, hipCtx_t ctx) +try: (hipDrvGraphAddMemsetNode:=dll.hipDrvGraphAddMemsetNode).restype, hipDrvGraphAddMemsetNode.argtypes = hipError_t, [ctypes.POINTER(hipGraphNode_t), hipGraph_t, ctypes.POINTER(hipGraphNode_t), size_t, ctypes.POINTER(HIP_MEMSET_NODE_PARAMS), hipCtx_t] +except AttributeError: pass + +# hipError_t hipMemAddressFree(void *devPtr, size_t size) +try: (hipMemAddressFree:=dll.hipMemAddressFree).restype, hipMemAddressFree.argtypes = hipError_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# hipError_t hipMemAddressReserve(void **ptr, size_t size, size_t alignment, void *addr, unsigned long long flags) +try: (hipMemAddressReserve:=dll.hipMemAddressReserve).restype, hipMemAddressReserve.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), size_t, size_t, ctypes.c_void_p, ctypes.c_uint64] +except AttributeError: pass + +# hipError_t hipMemCreate(hipMemGenericAllocationHandle_t *handle, size_t size, const hipMemAllocationProp *prop, unsigned long long flags) +try: (hipMemCreate:=dll.hipMemCreate).restype, hipMemCreate.argtypes = hipError_t, [ctypes.POINTER(hipMemGenericAllocationHandle_t), size_t, ctypes.POINTER(hipMemAllocationProp), ctypes.c_uint64] +except AttributeError: pass + +# hipError_t hipMemExportToShareableHandle(void *shareableHandle, hipMemGenericAllocationHandle_t handle, hipMemAllocationHandleType handleType, unsigned long long flags) +try: (hipMemExportToShareableHandle:=dll.hipMemExportToShareableHandle).restype, hipMemExportToShareableHandle.argtypes = hipError_t, [ctypes.c_void_p, hipMemGenericAllocationHandle_t, hipMemAllocationHandleType, ctypes.c_uint64] +except AttributeError: pass + +# hipError_t hipMemGetAccess(unsigned long long *flags, const hipMemLocation *location, void *ptr) +try: (hipMemGetAccess:=dll.hipMemGetAccess).restype, hipMemGetAccess.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(hipMemLocation), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMemGetAllocationGranularity(size_t *granularity, const hipMemAllocationProp *prop, hipMemAllocationGranularity_flags option) +try: (hipMemGetAllocationGranularity:=dll.hipMemGetAllocationGranularity).restype, hipMemGetAllocationGranularity.argtypes = hipError_t, [ctypes.POINTER(size_t), ctypes.POINTER(hipMemAllocationProp), hipMemAllocationGranularity_flags] +except AttributeError: pass + +# hipError_t hipMemGetAllocationPropertiesFromHandle(hipMemAllocationProp *prop, hipMemGenericAllocationHandle_t handle) +try: (hipMemGetAllocationPropertiesFromHandle:=dll.hipMemGetAllocationPropertiesFromHandle).restype, hipMemGetAllocationPropertiesFromHandle.argtypes = hipError_t, [ctypes.POINTER(hipMemAllocationProp), hipMemGenericAllocationHandle_t] +except AttributeError: pass + +# hipError_t hipMemImportFromShareableHandle(hipMemGenericAllocationHandle_t *handle, void *osHandle, hipMemAllocationHandleType shHandleType) +try: (hipMemImportFromShareableHandle:=dll.hipMemImportFromShareableHandle).restype, hipMemImportFromShareableHandle.argtypes = hipError_t, [ctypes.POINTER(hipMemGenericAllocationHandle_t), ctypes.c_void_p, hipMemAllocationHandleType] +except AttributeError: pass + +# hipError_t hipMemMap(void *ptr, size_t size, size_t offset, hipMemGenericAllocationHandle_t handle, unsigned long long flags) +try: (hipMemMap:=dll.hipMemMap).restype, hipMemMap.argtypes = hipError_t, [ctypes.c_void_p, size_t, size_t, hipMemGenericAllocationHandle_t, ctypes.c_uint64] +except AttributeError: pass + +# hipError_t hipMemMapArrayAsync(hipArrayMapInfo *mapInfoList, unsigned int count, hipStream_t stream) +try: (hipMemMapArrayAsync:=dll.hipMemMapArrayAsync).restype, hipMemMapArrayAsync.argtypes = hipError_t, [ctypes.POINTER(hipArrayMapInfo), ctypes.c_uint32, hipStream_t] +except AttributeError: pass + +# hipError_t hipMemRelease(hipMemGenericAllocationHandle_t handle) +try: (hipMemRelease:=dll.hipMemRelease).restype, hipMemRelease.argtypes = hipError_t, [hipMemGenericAllocationHandle_t] +except AttributeError: pass + +# hipError_t hipMemRetainAllocationHandle(hipMemGenericAllocationHandle_t *handle, void *addr) +try: (hipMemRetainAllocationHandle:=dll.hipMemRetainAllocationHandle).restype, hipMemRetainAllocationHandle.argtypes = hipError_t, [ctypes.POINTER(hipMemGenericAllocationHandle_t), ctypes.c_void_p] +except AttributeError: pass + +# hipError_t hipMemSetAccess(void *ptr, size_t size, const hipMemAccessDesc *desc, size_t count) +try: (hipMemSetAccess:=dll.hipMemSetAccess).restype, hipMemSetAccess.argtypes = hipError_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hipMemAccessDesc), size_t] +except AttributeError: pass + +# hipError_t hipMemUnmap(void *ptr, size_t size) +try: (hipMemUnmap:=dll.hipMemUnmap).restype, hipMemUnmap.argtypes = hipError_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# hipError_t hipGraphicsMapResources(int count, hipGraphicsResource_t *resources, hipStream_t stream = 0) +try: (hipGraphicsMapResources:=dll.hipGraphicsMapResources).restype, hipGraphicsMapResources.argtypes = hipError_t, [ctypes.c_int32, ctypes.POINTER(hipGraphicsResource_t), hipStream_t] +except AttributeError: pass + +# hipError_t hipGraphicsSubResourceGetMappedArray(hipArray_t *array, hipGraphicsResource_t resource, unsigned int arrayIndex, unsigned int mipLevel) +try: (hipGraphicsSubResourceGetMappedArray:=dll.hipGraphicsSubResourceGetMappedArray).restype, hipGraphicsSubResourceGetMappedArray.argtypes = hipError_t, [ctypes.POINTER(hipArray_t), hipGraphicsResource_t, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# hipError_t hipGraphicsResourceGetMappedPointer(void **devPtr, size_t *size, hipGraphicsResource_t resource) +try: (hipGraphicsResourceGetMappedPointer:=dll.hipGraphicsResourceGetMappedPointer).restype, hipGraphicsResourceGetMappedPointer.argtypes = hipError_t, [ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t), hipGraphicsResource_t] +except AttributeError: pass + +# hipError_t hipGraphicsUnmapResources(int count, hipGraphicsResource_t *resources, hipStream_t stream = 0) +try: (hipGraphicsUnmapResources:=dll.hipGraphicsUnmapResources).restype, hipGraphicsUnmapResources.argtypes = hipError_t, [ctypes.c_int32, ctypes.POINTER(hipGraphicsResource_t), hipStream_t] +except AttributeError: pass + +# hipError_t hipGraphicsUnregisterResource(hipGraphicsResource_t resource) +try: (hipGraphicsUnregisterResource:=dll.hipGraphicsUnregisterResource).restype, hipGraphicsUnregisterResource.argtypes = hipError_t, [hipGraphicsResource_t] +except AttributeError: pass + +class __hip_surface(Struct): pass +hipSurfaceObject_t = ctypes.POINTER(__hip_surface) +# hipError_t hipCreateSurfaceObject(hipSurfaceObject_t *pSurfObject, const hipResourceDesc *pResDesc) +try: (hipCreateSurfaceObject:=dll.hipCreateSurfaceObject).restype, hipCreateSurfaceObject.argtypes = hipError_t, [ctypes.POINTER(hipSurfaceObject_t), ctypes.POINTER(hipResourceDesc)] +except AttributeError: pass + +# hipError_t hipDestroySurfaceObject(hipSurfaceObject_t surfaceObject) +try: (hipDestroySurfaceObject:=dll.hipDestroySurfaceObject).restype, hipDestroySurfaceObject.argtypes = hipError_t, [hipSurfaceObject_t] +except AttributeError: pass + +hipmipmappedArray = ctypes.POINTER(hipMipmappedArray) +hipResourcetype = HIPresourcetype_enum hipGetDeviceProperties = hipGetDevicePropertiesR0600 +hipDeviceProp_t = hipDeviceProp_tR0600 +hipChooseDevice = hipChooseDeviceR0600 +GENERIC_GRID_LAUNCH = 1 +DEPRECATED = lambda msg: __attribute__ ((deprecated(msg))) +hipIpcMemLazyEnablePeerAccess = 0x01 +HIP_IPC_HANDLE_SIZE = 64 +hipStreamDefault = 0x00 +hipStreamNonBlocking = 0x01 +hipEventDefault = 0x0 +hipEventBlockingSync = 0x1 +hipEventDisableTiming = 0x2 +hipEventInterprocess = 0x4 +hipEventDisableSystemFence = 0x20000000 +hipEventReleaseToDevice = 0x40000000 +hipEventReleaseToSystem = 0x80000000 +hipHostMallocDefault = 0x0 +hipHostMallocPortable = 0x1 +hipHostMallocMapped = 0x2 +hipHostMallocWriteCombined = 0x4 +hipHostMallocNumaUser = 0x20000000 +hipHostMallocCoherent = 0x40000000 +hipHostMallocNonCoherent = 0x80000000 +hipMemAttachGlobal = 0x01 +hipMemAttachHost = 0x02 +hipMemAttachSingle = 0x04 +hipDeviceMallocDefault = 0x0 +hipDeviceMallocFinegrained = 0x1 +hipMallocSignalMemory = 0x2 +hipDeviceMallocUncached = 0x3 +hipDeviceMallocContiguous = 0x4 +hipHostRegisterDefault = 0x0 +hipHostRegisterPortable = 0x1 +hipHostRegisterMapped = 0x2 +hipHostRegisterIoMemory = 0x4 +hipHostRegisterReadOnly = 0x08 +hipExtHostRegisterCoarseGrained = 0x8 +hipDeviceScheduleAuto = 0x0 +hipDeviceScheduleSpin = 0x1 +hipDeviceScheduleYield = 0x2 +hipDeviceScheduleBlockingSync = 0x4 +hipDeviceScheduleMask = 0x7 +hipDeviceMapHost = 0x8 +hipDeviceLmemResizeToMax = 0x10 +hipArrayDefault = 0x00 +hipArrayLayered = 0x01 +hipArraySurfaceLoadStore = 0x02 +hipArrayCubemap = 0x04 +hipArrayTextureGather = 0x08 +hipOccupancyDefault = 0x00 +hipOccupancyDisableCachingOverride = 0x01 +hipCooperativeLaunchMultiDeviceNoPreSync = 0x01 +hipCooperativeLaunchMultiDeviceNoPostSync = 0x02 +hipExtAnyOrderLaunch = 0x01 +hipStreamWaitValueGte = 0x0 +hipStreamWaitValueEq = 0x1 +hipStreamWaitValueAnd = 0x2 +hipStreamWaitValueNor = 0x3 +hipExternalMemoryDedicated = 0x1 +hipKernelNodeAttrID = hipLaunchAttributeID +hipKernelNodeAttributeAccessPolicyWindow = hipLaunchAttributeAccessPolicyWindow +hipKernelNodeAttributeCooperative = hipLaunchAttributeCooperative +hipKernelNodeAttributePriority = hipLaunchAttributePriority +hipKernelNodeAttrValue = hipLaunchAttributeValue +hipGraphKernelNodePortDefault = 0 +hipGraphKernelNodePortLaunchCompletion = 2 +hipGraphKernelNodePortProgrammatic = 1 +USE_PEER_NON_UNIFIED = 1 +HIP_TRSA_OVERRIDE_FORMAT = 0x01 +HIP_TRSF_READ_AS_INTEGER = 0x01 +HIP_TRSF_NORMALIZED_COORDINATES = 0x02 +HIP_TRSF_SRGB = 0x10 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/hsa.py b/tinygrad/runtime/autogen/hsa.py index 31a9843cb8..5019e4d954 100644 --- a/tinygrad/runtime/autogen/hsa.py +++ b/tinygrad/runtime/autogen/hsa.py @@ -1,5936 +1,2663 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/opt/rocm/include'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os +import ctypes, os +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(os.getenv('ROCM_PATH', '/opt/rocm')+'/lib/libhsa-runtime64.so')) + except: pass + try: return ctypes.CDLL(unwrap(find_library('hsa-runtime64'))) + except: pass + return None +dll = dll() +hsa_status_t = CEnum(ctypes.c_uint32) +HSA_STATUS_SUCCESS = hsa_status_t.define('HSA_STATUS_SUCCESS', 0) +HSA_STATUS_INFO_BREAK = hsa_status_t.define('HSA_STATUS_INFO_BREAK', 1) +HSA_STATUS_ERROR = hsa_status_t.define('HSA_STATUS_ERROR', 4096) +HSA_STATUS_ERROR_INVALID_ARGUMENT = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_ARGUMENT', 4097) +HSA_STATUS_ERROR_INVALID_QUEUE_CREATION = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_QUEUE_CREATION', 4098) +HSA_STATUS_ERROR_INVALID_ALLOCATION = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_ALLOCATION', 4099) +HSA_STATUS_ERROR_INVALID_AGENT = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_AGENT', 4100) +HSA_STATUS_ERROR_INVALID_REGION = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_REGION', 4101) +HSA_STATUS_ERROR_INVALID_SIGNAL = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_SIGNAL', 4102) +HSA_STATUS_ERROR_INVALID_QUEUE = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_QUEUE', 4103) +HSA_STATUS_ERROR_OUT_OF_RESOURCES = hsa_status_t.define('HSA_STATUS_ERROR_OUT_OF_RESOURCES', 4104) +HSA_STATUS_ERROR_INVALID_PACKET_FORMAT = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_PACKET_FORMAT', 4105) +HSA_STATUS_ERROR_RESOURCE_FREE = hsa_status_t.define('HSA_STATUS_ERROR_RESOURCE_FREE', 4106) +HSA_STATUS_ERROR_NOT_INITIALIZED = hsa_status_t.define('HSA_STATUS_ERROR_NOT_INITIALIZED', 4107) +HSA_STATUS_ERROR_REFCOUNT_OVERFLOW = hsa_status_t.define('HSA_STATUS_ERROR_REFCOUNT_OVERFLOW', 4108) +HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS = hsa_status_t.define('HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS', 4109) +HSA_STATUS_ERROR_INVALID_INDEX = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_INDEX', 4110) +HSA_STATUS_ERROR_INVALID_ISA = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_ISA', 4111) +HSA_STATUS_ERROR_INVALID_ISA_NAME = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_ISA_NAME', 4119) +HSA_STATUS_ERROR_INVALID_CODE_OBJECT = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_CODE_OBJECT', 4112) +HSA_STATUS_ERROR_INVALID_EXECUTABLE = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_EXECUTABLE', 4113) +HSA_STATUS_ERROR_FROZEN_EXECUTABLE = hsa_status_t.define('HSA_STATUS_ERROR_FROZEN_EXECUTABLE', 4114) +HSA_STATUS_ERROR_INVALID_SYMBOL_NAME = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_SYMBOL_NAME', 4115) +HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED = hsa_status_t.define('HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED', 4116) +HSA_STATUS_ERROR_VARIABLE_UNDEFINED = hsa_status_t.define('HSA_STATUS_ERROR_VARIABLE_UNDEFINED', 4117) +HSA_STATUS_ERROR_EXCEPTION = hsa_status_t.define('HSA_STATUS_ERROR_EXCEPTION', 4118) +HSA_STATUS_ERROR_INVALID_CODE_SYMBOL = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_CODE_SYMBOL', 4120) +HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL', 4121) +HSA_STATUS_ERROR_INVALID_FILE = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_FILE', 4128) +HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER', 4129) +HSA_STATUS_ERROR_INVALID_CACHE = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_CACHE', 4130) +HSA_STATUS_ERROR_INVALID_WAVEFRONT = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_WAVEFRONT', 4131) +HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP', 4132) +HSA_STATUS_ERROR_INVALID_RUNTIME_STATE = hsa_status_t.define('HSA_STATUS_ERROR_INVALID_RUNTIME_STATE', 4133) +HSA_STATUS_ERROR_FATAL = hsa_status_t.define('HSA_STATUS_ERROR_FATAL', 4134) -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value +# hsa_status_t hsa_status_string(hsa_status_t status, const char **status_string) +try: (hsa_status_string:=dll.hsa_status_string).restype, hsa_status_string.argtypes = hsa_status_t, [hsa_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libhsa-runtime64.so'] = ctypes.CDLL(os.getenv('ROCM_PATH')+'/lib/libhsa-runtime64.so' if os.getenv('ROCM_PATH') else ctypes.util.find_library('hsa-runtime64')) -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') - - - -# values for enumeration 'c__EA_hsa_status_t' -c__EA_hsa_status_t__enumvalues = { - 0: 'HSA_STATUS_SUCCESS', - 1: 'HSA_STATUS_INFO_BREAK', - 4096: 'HSA_STATUS_ERROR', - 4097: 'HSA_STATUS_ERROR_INVALID_ARGUMENT', - 4098: 'HSA_STATUS_ERROR_INVALID_QUEUE_CREATION', - 4099: 'HSA_STATUS_ERROR_INVALID_ALLOCATION', - 4100: 'HSA_STATUS_ERROR_INVALID_AGENT', - 4101: 'HSA_STATUS_ERROR_INVALID_REGION', - 4102: 'HSA_STATUS_ERROR_INVALID_SIGNAL', - 4103: 'HSA_STATUS_ERROR_INVALID_QUEUE', - 4104: 'HSA_STATUS_ERROR_OUT_OF_RESOURCES', - 4105: 'HSA_STATUS_ERROR_INVALID_PACKET_FORMAT', - 4106: 'HSA_STATUS_ERROR_RESOURCE_FREE', - 4107: 'HSA_STATUS_ERROR_NOT_INITIALIZED', - 4108: 'HSA_STATUS_ERROR_REFCOUNT_OVERFLOW', - 4109: 'HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS', - 4110: 'HSA_STATUS_ERROR_INVALID_INDEX', - 4111: 'HSA_STATUS_ERROR_INVALID_ISA', - 4119: 'HSA_STATUS_ERROR_INVALID_ISA_NAME', - 4112: 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT', - 4113: 'HSA_STATUS_ERROR_INVALID_EXECUTABLE', - 4114: 'HSA_STATUS_ERROR_FROZEN_EXECUTABLE', - 4115: 'HSA_STATUS_ERROR_INVALID_SYMBOL_NAME', - 4116: 'HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED', - 4117: 'HSA_STATUS_ERROR_VARIABLE_UNDEFINED', - 4118: 'HSA_STATUS_ERROR_EXCEPTION', - 4120: 'HSA_STATUS_ERROR_INVALID_CODE_SYMBOL', - 4121: 'HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL', - 4128: 'HSA_STATUS_ERROR_INVALID_FILE', - 4129: 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER', - 4130: 'HSA_STATUS_ERROR_INVALID_CACHE', - 4131: 'HSA_STATUS_ERROR_INVALID_WAVEFRONT', - 4132: 'HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP', - 4133: 'HSA_STATUS_ERROR_INVALID_RUNTIME_STATE', - 4134: 'HSA_STATUS_ERROR_FATAL', -} -HSA_STATUS_SUCCESS = 0 -HSA_STATUS_INFO_BREAK = 1 -HSA_STATUS_ERROR = 4096 -HSA_STATUS_ERROR_INVALID_ARGUMENT = 4097 -HSA_STATUS_ERROR_INVALID_QUEUE_CREATION = 4098 -HSA_STATUS_ERROR_INVALID_ALLOCATION = 4099 -HSA_STATUS_ERROR_INVALID_AGENT = 4100 -HSA_STATUS_ERROR_INVALID_REGION = 4101 -HSA_STATUS_ERROR_INVALID_SIGNAL = 4102 -HSA_STATUS_ERROR_INVALID_QUEUE = 4103 -HSA_STATUS_ERROR_OUT_OF_RESOURCES = 4104 -HSA_STATUS_ERROR_INVALID_PACKET_FORMAT = 4105 -HSA_STATUS_ERROR_RESOURCE_FREE = 4106 -HSA_STATUS_ERROR_NOT_INITIALIZED = 4107 -HSA_STATUS_ERROR_REFCOUNT_OVERFLOW = 4108 -HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS = 4109 -HSA_STATUS_ERROR_INVALID_INDEX = 4110 -HSA_STATUS_ERROR_INVALID_ISA = 4111 -HSA_STATUS_ERROR_INVALID_ISA_NAME = 4119 -HSA_STATUS_ERROR_INVALID_CODE_OBJECT = 4112 -HSA_STATUS_ERROR_INVALID_EXECUTABLE = 4113 -HSA_STATUS_ERROR_FROZEN_EXECUTABLE = 4114 -HSA_STATUS_ERROR_INVALID_SYMBOL_NAME = 4115 -HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED = 4116 -HSA_STATUS_ERROR_VARIABLE_UNDEFINED = 4117 -HSA_STATUS_ERROR_EXCEPTION = 4118 -HSA_STATUS_ERROR_INVALID_CODE_SYMBOL = 4120 -HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL = 4121 -HSA_STATUS_ERROR_INVALID_FILE = 4128 -HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER = 4129 -HSA_STATUS_ERROR_INVALID_CACHE = 4130 -HSA_STATUS_ERROR_INVALID_WAVEFRONT = 4131 -HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP = 4132 -HSA_STATUS_ERROR_INVALID_RUNTIME_STATE = 4133 -HSA_STATUS_ERROR_FATAL = 4134 -c__EA_hsa_status_t = ctypes.c_uint32 # enum -hsa_status_t = c__EA_hsa_status_t -hsa_status_t__enumvalues = c__EA_hsa_status_t__enumvalues -try: - hsa_status_string = _libraries['libhsa-runtime64.so'].hsa_status_string - hsa_status_string.restype = hsa_status_t - hsa_status_string.argtypes = [hsa_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -class struct_hsa_dim3_s(Structure): - pass - -struct_hsa_dim3_s._pack_ = 1 # source:False +class struct_hsa_dim3_s(Struct): pass +uint32_t = ctypes.c_uint32 struct_hsa_dim3_s._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), + ('x', uint32_t), + ('y', uint32_t), + ('z', uint32_t), ] - hsa_dim3_t = struct_hsa_dim3_s +hsa_access_permission_t = CEnum(ctypes.c_uint32) +HSA_ACCESS_PERMISSION_NONE = hsa_access_permission_t.define('HSA_ACCESS_PERMISSION_NONE', 0) +HSA_ACCESS_PERMISSION_RO = hsa_access_permission_t.define('HSA_ACCESS_PERMISSION_RO', 1) +HSA_ACCESS_PERMISSION_WO = hsa_access_permission_t.define('HSA_ACCESS_PERMISSION_WO', 2) +HSA_ACCESS_PERMISSION_RW = hsa_access_permission_t.define('HSA_ACCESS_PERMISSION_RW', 3) -# values for enumeration 'c__EA_hsa_access_permission_t' -c__EA_hsa_access_permission_t__enumvalues = { - 0: 'HSA_ACCESS_PERMISSION_NONE', - 1: 'HSA_ACCESS_PERMISSION_RO', - 2: 'HSA_ACCESS_PERMISSION_WO', - 3: 'HSA_ACCESS_PERMISSION_RW', -} -HSA_ACCESS_PERMISSION_NONE = 0 -HSA_ACCESS_PERMISSION_RO = 1 -HSA_ACCESS_PERMISSION_WO = 2 -HSA_ACCESS_PERMISSION_RW = 3 -c__EA_hsa_access_permission_t = ctypes.c_uint32 # enum -hsa_access_permission_t = c__EA_hsa_access_permission_t -hsa_access_permission_t__enumvalues = c__EA_hsa_access_permission_t__enumvalues hsa_file_t = ctypes.c_int32 -try: - hsa_init = _libraries['libhsa-runtime64.so'].hsa_init - hsa_init.restype = hsa_status_t - hsa_init.argtypes = [] -except AttributeError: - pass -try: - hsa_shut_down = _libraries['libhsa-runtime64.so'].hsa_shut_down - hsa_shut_down.restype = hsa_status_t - hsa_shut_down.argtypes = [] -except AttributeError: - pass +# hsa_status_t hsa_init() +try: (hsa_init:=dll.hsa_init).restype, hsa_init.argtypes = hsa_status_t, [] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_endianness_t' -c__EA_hsa_endianness_t__enumvalues = { - 0: 'HSA_ENDIANNESS_LITTLE', - 1: 'HSA_ENDIANNESS_BIG', -} -HSA_ENDIANNESS_LITTLE = 0 -HSA_ENDIANNESS_BIG = 1 -c__EA_hsa_endianness_t = ctypes.c_uint32 # enum -hsa_endianness_t = c__EA_hsa_endianness_t -hsa_endianness_t__enumvalues = c__EA_hsa_endianness_t__enumvalues +# hsa_status_t hsa_shut_down() +try: (hsa_shut_down:=dll.hsa_shut_down).restype, hsa_shut_down.argtypes = hsa_status_t, [] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_machine_model_t' -c__EA_hsa_machine_model_t__enumvalues = { - 0: 'HSA_MACHINE_MODEL_SMALL', - 1: 'HSA_MACHINE_MODEL_LARGE', -} -HSA_MACHINE_MODEL_SMALL = 0 -HSA_MACHINE_MODEL_LARGE = 1 -c__EA_hsa_machine_model_t = ctypes.c_uint32 # enum -hsa_machine_model_t = c__EA_hsa_machine_model_t -hsa_machine_model_t__enumvalues = c__EA_hsa_machine_model_t__enumvalues +hsa_endianness_t = CEnum(ctypes.c_uint32) +HSA_ENDIANNESS_LITTLE = hsa_endianness_t.define('HSA_ENDIANNESS_LITTLE', 0) +HSA_ENDIANNESS_BIG = hsa_endianness_t.define('HSA_ENDIANNESS_BIG', 1) -# values for enumeration 'c__EA_hsa_profile_t' -c__EA_hsa_profile_t__enumvalues = { - 0: 'HSA_PROFILE_BASE', - 1: 'HSA_PROFILE_FULL', -} -HSA_PROFILE_BASE = 0 -HSA_PROFILE_FULL = 1 -c__EA_hsa_profile_t = ctypes.c_uint32 # enum -hsa_profile_t = c__EA_hsa_profile_t -hsa_profile_t__enumvalues = c__EA_hsa_profile_t__enumvalues +hsa_machine_model_t = CEnum(ctypes.c_uint32) +HSA_MACHINE_MODEL_SMALL = hsa_machine_model_t.define('HSA_MACHINE_MODEL_SMALL', 0) +HSA_MACHINE_MODEL_LARGE = hsa_machine_model_t.define('HSA_MACHINE_MODEL_LARGE', 1) -# values for enumeration 'c__EA_hsa_system_info_t' -c__EA_hsa_system_info_t__enumvalues = { - 0: 'HSA_SYSTEM_INFO_VERSION_MAJOR', - 1: 'HSA_SYSTEM_INFO_VERSION_MINOR', - 2: 'HSA_SYSTEM_INFO_TIMESTAMP', - 3: 'HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY', - 4: 'HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT', - 5: 'HSA_SYSTEM_INFO_ENDIANNESS', - 6: 'HSA_SYSTEM_INFO_MACHINE_MODEL', - 7: 'HSA_SYSTEM_INFO_EXTENSIONS', - 512: 'HSA_AMD_SYSTEM_INFO_BUILD_VERSION', - 513: 'HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED', - 514: 'HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT', - 515: 'HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED', - 516: 'HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED', - 517: 'HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED', - 518: 'HSA_AMD_SYSTEM_INFO_XNACK_ENABLED', - 519: 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR', - 520: 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR', -} -HSA_SYSTEM_INFO_VERSION_MAJOR = 0 -HSA_SYSTEM_INFO_VERSION_MINOR = 1 -HSA_SYSTEM_INFO_TIMESTAMP = 2 -HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY = 3 -HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT = 4 -HSA_SYSTEM_INFO_ENDIANNESS = 5 -HSA_SYSTEM_INFO_MACHINE_MODEL = 6 -HSA_SYSTEM_INFO_EXTENSIONS = 7 -HSA_AMD_SYSTEM_INFO_BUILD_VERSION = 512 -HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED = 513 -HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT = 514 -HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED = 515 -HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED = 516 -HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED = 517 -HSA_AMD_SYSTEM_INFO_XNACK_ENABLED = 518 -HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR = 519 -HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR = 520 -c__EA_hsa_system_info_t = ctypes.c_uint32 # enum -hsa_system_info_t = c__EA_hsa_system_info_t -hsa_system_info_t__enumvalues = c__EA_hsa_system_info_t__enumvalues -try: - hsa_system_get_info = _libraries['libhsa-runtime64.so'].hsa_system_get_info - hsa_system_get_info.restype = hsa_status_t - hsa_system_get_info.argtypes = [hsa_system_info_t, ctypes.POINTER(None)] -except AttributeError: - pass +hsa_profile_t = CEnum(ctypes.c_uint32) +HSA_PROFILE_BASE = hsa_profile_t.define('HSA_PROFILE_BASE', 0) +HSA_PROFILE_FULL = hsa_profile_t.define('HSA_PROFILE_FULL', 1) + +hsa_system_info_t = CEnum(ctypes.c_uint32) +HSA_SYSTEM_INFO_VERSION_MAJOR = hsa_system_info_t.define('HSA_SYSTEM_INFO_VERSION_MAJOR', 0) +HSA_SYSTEM_INFO_VERSION_MINOR = hsa_system_info_t.define('HSA_SYSTEM_INFO_VERSION_MINOR', 1) +HSA_SYSTEM_INFO_TIMESTAMP = hsa_system_info_t.define('HSA_SYSTEM_INFO_TIMESTAMP', 2) +HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY = hsa_system_info_t.define('HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY', 3) +HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT = hsa_system_info_t.define('HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT', 4) +HSA_SYSTEM_INFO_ENDIANNESS = hsa_system_info_t.define('HSA_SYSTEM_INFO_ENDIANNESS', 5) +HSA_SYSTEM_INFO_MACHINE_MODEL = hsa_system_info_t.define('HSA_SYSTEM_INFO_MACHINE_MODEL', 6) +HSA_SYSTEM_INFO_EXTENSIONS = hsa_system_info_t.define('HSA_SYSTEM_INFO_EXTENSIONS', 7) +HSA_AMD_SYSTEM_INFO_BUILD_VERSION = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_BUILD_VERSION', 512) +HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED', 513) +HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT', 514) +HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED', 515) +HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED', 516) +HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED', 517) +HSA_AMD_SYSTEM_INFO_XNACK_ENABLED = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_XNACK_ENABLED', 518) +HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR', 519) +HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR = hsa_system_info_t.define('HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR', 520) + +# hsa_status_t hsa_system_get_info(hsa_system_info_t attribute, void *value) +try: (hsa_system_get_info:=dll.hsa_system_get_info).restype, hsa_system_get_info.argtypes = hsa_status_t, [hsa_system_info_t, ctypes.c_void_p] +except AttributeError: pass + +hsa_extension_t = CEnum(ctypes.c_uint32) +HSA_EXTENSION_FINALIZER = hsa_extension_t.define('HSA_EXTENSION_FINALIZER', 0) +HSA_EXTENSION_IMAGES = hsa_extension_t.define('HSA_EXTENSION_IMAGES', 1) +HSA_EXTENSION_PERFORMANCE_COUNTERS = hsa_extension_t.define('HSA_EXTENSION_PERFORMANCE_COUNTERS', 2) +HSA_EXTENSION_PROFILING_EVENTS = hsa_extension_t.define('HSA_EXTENSION_PROFILING_EVENTS', 3) +HSA_EXTENSION_STD_LAST = hsa_extension_t.define('HSA_EXTENSION_STD_LAST', 3) +HSA_AMD_FIRST_EXTENSION = hsa_extension_t.define('HSA_AMD_FIRST_EXTENSION', 512) +HSA_EXTENSION_AMD_PROFILER = hsa_extension_t.define('HSA_EXTENSION_AMD_PROFILER', 512) +HSA_EXTENSION_AMD_LOADER = hsa_extension_t.define('HSA_EXTENSION_AMD_LOADER', 513) +HSA_EXTENSION_AMD_AQLPROFILE = hsa_extension_t.define('HSA_EXTENSION_AMD_AQLPROFILE', 514) +HSA_EXTENSION_AMD_PC_SAMPLING = hsa_extension_t.define('HSA_EXTENSION_AMD_PC_SAMPLING', 515) +HSA_AMD_LAST_EXTENSION = hsa_extension_t.define('HSA_AMD_LAST_EXTENSION', 515) -# values for enumeration 'c__EA_hsa_extension_t' -c__EA_hsa_extension_t__enumvalues = { - 0: 'HSA_EXTENSION_FINALIZER', - 1: 'HSA_EXTENSION_IMAGES', - 2: 'HSA_EXTENSION_PERFORMANCE_COUNTERS', - 3: 'HSA_EXTENSION_PROFILING_EVENTS', - 3: 'HSA_EXTENSION_STD_LAST', - 512: 'HSA_AMD_FIRST_EXTENSION', - 512: 'HSA_EXTENSION_AMD_PROFILER', - 513: 'HSA_EXTENSION_AMD_LOADER', - 514: 'HSA_EXTENSION_AMD_AQLPROFILE', - 515: 'HSA_EXTENSION_AMD_PC_SAMPLING', - 515: 'HSA_AMD_LAST_EXTENSION', -} -HSA_EXTENSION_FINALIZER = 0 -HSA_EXTENSION_IMAGES = 1 -HSA_EXTENSION_PERFORMANCE_COUNTERS = 2 -HSA_EXTENSION_PROFILING_EVENTS = 3 -HSA_EXTENSION_STD_LAST = 3 -HSA_AMD_FIRST_EXTENSION = 512 -HSA_EXTENSION_AMD_PROFILER = 512 -HSA_EXTENSION_AMD_LOADER = 513 -HSA_EXTENSION_AMD_AQLPROFILE = 514 -HSA_EXTENSION_AMD_PC_SAMPLING = 515 -HSA_AMD_LAST_EXTENSION = 515 -c__EA_hsa_extension_t = ctypes.c_uint32 # enum -hsa_extension_t = c__EA_hsa_extension_t -hsa_extension_t__enumvalues = c__EA_hsa_extension_t__enumvalues uint16_t = ctypes.c_uint16 -try: - hsa_extension_get_name = _libraries['libhsa-runtime64.so'].hsa_extension_get_name - hsa_extension_get_name.restype = hsa_status_t - hsa_extension_get_name.argtypes = [uint16_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - hsa_system_extension_supported = _libraries['libhsa-runtime64.so'].hsa_system_extension_supported - hsa_system_extension_supported.restype = hsa_status_t - hsa_system_extension_supported.argtypes = [uint16_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_system_major_extension_supported = _libraries['libhsa-runtime64.so'].hsa_system_major_extension_supported - hsa_system_major_extension_supported.restype = hsa_status_t - hsa_system_major_extension_supported.argtypes = [uint16_t, uint16_t, ctypes.POINTER(ctypes.c_uint16), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_system_get_extension_table = _libraries['libhsa-runtime64.so'].hsa_system_get_extension_table - hsa_system_get_extension_table.restype = hsa_status_t - hsa_system_get_extension_table.argtypes = [uint16_t, uint16_t, uint16_t, ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_extension_get_name(uint16_t extension, const char **name) +try: (hsa_extension_get_name:=dll.hsa_extension_get_name).restype, hsa_extension_get_name.argtypes = hsa_status_t, [uint16_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# hsa_status_t hsa_system_extension_supported(uint16_t extension, uint16_t version_major, uint16_t version_minor, bool *result) +try: (hsa_system_extension_supported:=dll.hsa_system_extension_supported).restype, hsa_system_extension_supported.argtypes = hsa_status_t, [uint16_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +# hsa_status_t hsa_system_major_extension_supported(uint16_t extension, uint16_t version_major, uint16_t *version_minor, bool *result) +try: (hsa_system_major_extension_supported:=dll.hsa_system_major_extension_supported).restype, hsa_system_major_extension_supported.argtypes = hsa_status_t, [uint16_t, uint16_t, ctypes.POINTER(uint16_t), ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +# hsa_status_t hsa_system_get_extension_table(uint16_t extension, uint16_t version_major, uint16_t version_minor, void *table) +try: (hsa_system_get_extension_table:=dll.hsa_system_get_extension_table).restype, hsa_system_get_extension_table.argtypes = hsa_status_t, [uint16_t, uint16_t, uint16_t, ctypes.c_void_p] +except AttributeError: pass + size_t = ctypes.c_uint64 -try: - hsa_system_get_major_extension_table = _libraries['libhsa-runtime64.so'].hsa_system_get_major_extension_table - hsa_system_get_major_extension_table.restype = hsa_status_t - hsa_system_get_major_extension_table.argtypes = [uint16_t, uint16_t, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_agent_s(Structure): - pass +# hsa_status_t hsa_system_get_major_extension_table(uint16_t extension, uint16_t version_major, size_t table_length, void *table) +try: (hsa_system_get_major_extension_table:=dll.hsa_system_get_major_extension_table).restype, hsa_system_get_major_extension_table.argtypes = hsa_status_t, [uint16_t, uint16_t, size_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_agent_s._pack_ = 1 # source:False +class struct_hsa_agent_s(Struct): pass +uint64_t = ctypes.c_uint64 struct_hsa_agent_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_agent_t = struct_hsa_agent_s +hsa_agent_feature_t = CEnum(ctypes.c_uint32) +HSA_AGENT_FEATURE_KERNEL_DISPATCH = hsa_agent_feature_t.define('HSA_AGENT_FEATURE_KERNEL_DISPATCH', 1) +HSA_AGENT_FEATURE_AGENT_DISPATCH = hsa_agent_feature_t.define('HSA_AGENT_FEATURE_AGENT_DISPATCH', 2) -# values for enumeration 'c__EA_hsa_agent_feature_t' -c__EA_hsa_agent_feature_t__enumvalues = { - 1: 'HSA_AGENT_FEATURE_KERNEL_DISPATCH', - 2: 'HSA_AGENT_FEATURE_AGENT_DISPATCH', -} -HSA_AGENT_FEATURE_KERNEL_DISPATCH = 1 -HSA_AGENT_FEATURE_AGENT_DISPATCH = 2 -c__EA_hsa_agent_feature_t = ctypes.c_uint32 # enum -hsa_agent_feature_t = c__EA_hsa_agent_feature_t -hsa_agent_feature_t__enumvalues = c__EA_hsa_agent_feature_t__enumvalues +hsa_device_type_t = CEnum(ctypes.c_uint32) +HSA_DEVICE_TYPE_CPU = hsa_device_type_t.define('HSA_DEVICE_TYPE_CPU', 0) +HSA_DEVICE_TYPE_GPU = hsa_device_type_t.define('HSA_DEVICE_TYPE_GPU', 1) +HSA_DEVICE_TYPE_DSP = hsa_device_type_t.define('HSA_DEVICE_TYPE_DSP', 2) -# values for enumeration 'c__EA_hsa_device_type_t' -c__EA_hsa_device_type_t__enumvalues = { - 0: 'HSA_DEVICE_TYPE_CPU', - 1: 'HSA_DEVICE_TYPE_GPU', - 2: 'HSA_DEVICE_TYPE_DSP', -} -HSA_DEVICE_TYPE_CPU = 0 -HSA_DEVICE_TYPE_GPU = 1 -HSA_DEVICE_TYPE_DSP = 2 -c__EA_hsa_device_type_t = ctypes.c_uint32 # enum -hsa_device_type_t = c__EA_hsa_device_type_t -hsa_device_type_t__enumvalues = c__EA_hsa_device_type_t__enumvalues +hsa_default_float_rounding_mode_t = CEnum(ctypes.c_uint32) +HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT = hsa_default_float_rounding_mode_t.define('HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT', 0) +HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO = hsa_default_float_rounding_mode_t.define('HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO', 1) +HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR = hsa_default_float_rounding_mode_t.define('HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR', 2) -# values for enumeration 'c__EA_hsa_default_float_rounding_mode_t' -c__EA_hsa_default_float_rounding_mode_t__enumvalues = { - 0: 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT', - 1: 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO', - 2: 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR', -} -HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT = 0 -HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO = 1 -HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR = 2 -c__EA_hsa_default_float_rounding_mode_t = ctypes.c_uint32 # enum -hsa_default_float_rounding_mode_t = c__EA_hsa_default_float_rounding_mode_t -hsa_default_float_rounding_mode_t__enumvalues = c__EA_hsa_default_float_rounding_mode_t__enumvalues +hsa_agent_info_t = CEnum(ctypes.c_uint32) +HSA_AGENT_INFO_NAME = hsa_agent_info_t.define('HSA_AGENT_INFO_NAME', 0) +HSA_AGENT_INFO_VENDOR_NAME = hsa_agent_info_t.define('HSA_AGENT_INFO_VENDOR_NAME', 1) +HSA_AGENT_INFO_FEATURE = hsa_agent_info_t.define('HSA_AGENT_INFO_FEATURE', 2) +HSA_AGENT_INFO_MACHINE_MODEL = hsa_agent_info_t.define('HSA_AGENT_INFO_MACHINE_MODEL', 3) +HSA_AGENT_INFO_PROFILE = hsa_agent_info_t.define('HSA_AGENT_INFO_PROFILE', 4) +HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = hsa_agent_info_t.define('HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', 5) +HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = hsa_agent_info_t.define('HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', 23) +HSA_AGENT_INFO_FAST_F16_OPERATION = hsa_agent_info_t.define('HSA_AGENT_INFO_FAST_F16_OPERATION', 24) +HSA_AGENT_INFO_WAVEFRONT_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_WAVEFRONT_SIZE', 6) +HSA_AGENT_INFO_WORKGROUP_MAX_DIM = hsa_agent_info_t.define('HSA_AGENT_INFO_WORKGROUP_MAX_DIM', 7) +HSA_AGENT_INFO_WORKGROUP_MAX_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_WORKGROUP_MAX_SIZE', 8) +HSA_AGENT_INFO_GRID_MAX_DIM = hsa_agent_info_t.define('HSA_AGENT_INFO_GRID_MAX_DIM', 9) +HSA_AGENT_INFO_GRID_MAX_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_GRID_MAX_SIZE', 10) +HSA_AGENT_INFO_FBARRIER_MAX_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_FBARRIER_MAX_SIZE', 11) +HSA_AGENT_INFO_QUEUES_MAX = hsa_agent_info_t.define('HSA_AGENT_INFO_QUEUES_MAX', 12) +HSA_AGENT_INFO_QUEUE_MIN_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_QUEUE_MIN_SIZE', 13) +HSA_AGENT_INFO_QUEUE_MAX_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_QUEUE_MAX_SIZE', 14) +HSA_AGENT_INFO_QUEUE_TYPE = hsa_agent_info_t.define('HSA_AGENT_INFO_QUEUE_TYPE', 15) +HSA_AGENT_INFO_NODE = hsa_agent_info_t.define('HSA_AGENT_INFO_NODE', 16) +HSA_AGENT_INFO_DEVICE = hsa_agent_info_t.define('HSA_AGENT_INFO_DEVICE', 17) +HSA_AGENT_INFO_CACHE_SIZE = hsa_agent_info_t.define('HSA_AGENT_INFO_CACHE_SIZE', 18) +HSA_AGENT_INFO_ISA = hsa_agent_info_t.define('HSA_AGENT_INFO_ISA', 19) +HSA_AGENT_INFO_EXTENSIONS = hsa_agent_info_t.define('HSA_AGENT_INFO_EXTENSIONS', 20) +HSA_AGENT_INFO_VERSION_MAJOR = hsa_agent_info_t.define('HSA_AGENT_INFO_VERSION_MAJOR', 21) +HSA_AGENT_INFO_VERSION_MINOR = hsa_agent_info_t.define('HSA_AGENT_INFO_VERSION_MINOR', 22) +HSA_AGENT_INFO_LAST = hsa_agent_info_t.define('HSA_AGENT_INFO_LAST', 2147483647) -# values for enumeration 'c__EA_hsa_agent_info_t' -c__EA_hsa_agent_info_t__enumvalues = { - 0: 'HSA_AGENT_INFO_NAME', - 1: 'HSA_AGENT_INFO_VENDOR_NAME', - 2: 'HSA_AGENT_INFO_FEATURE', - 3: 'HSA_AGENT_INFO_MACHINE_MODEL', - 4: 'HSA_AGENT_INFO_PROFILE', - 5: 'HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 23: 'HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 24: 'HSA_AGENT_INFO_FAST_F16_OPERATION', - 6: 'HSA_AGENT_INFO_WAVEFRONT_SIZE', - 7: 'HSA_AGENT_INFO_WORKGROUP_MAX_DIM', - 8: 'HSA_AGENT_INFO_WORKGROUP_MAX_SIZE', - 9: 'HSA_AGENT_INFO_GRID_MAX_DIM', - 10: 'HSA_AGENT_INFO_GRID_MAX_SIZE', - 11: 'HSA_AGENT_INFO_FBARRIER_MAX_SIZE', - 12: 'HSA_AGENT_INFO_QUEUES_MAX', - 13: 'HSA_AGENT_INFO_QUEUE_MIN_SIZE', - 14: 'HSA_AGENT_INFO_QUEUE_MAX_SIZE', - 15: 'HSA_AGENT_INFO_QUEUE_TYPE', - 16: 'HSA_AGENT_INFO_NODE', - 17: 'HSA_AGENT_INFO_DEVICE', - 18: 'HSA_AGENT_INFO_CACHE_SIZE', - 19: 'HSA_AGENT_INFO_ISA', - 20: 'HSA_AGENT_INFO_EXTENSIONS', - 21: 'HSA_AGENT_INFO_VERSION_MAJOR', - 22: 'HSA_AGENT_INFO_VERSION_MINOR', - 2147483647: 'HSA_AGENT_INFO_LAST', -} -HSA_AGENT_INFO_NAME = 0 -HSA_AGENT_INFO_VENDOR_NAME = 1 -HSA_AGENT_INFO_FEATURE = 2 -HSA_AGENT_INFO_MACHINE_MODEL = 3 -HSA_AGENT_INFO_PROFILE = 4 -HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 5 -HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = 23 -HSA_AGENT_INFO_FAST_F16_OPERATION = 24 -HSA_AGENT_INFO_WAVEFRONT_SIZE = 6 -HSA_AGENT_INFO_WORKGROUP_MAX_DIM = 7 -HSA_AGENT_INFO_WORKGROUP_MAX_SIZE = 8 -HSA_AGENT_INFO_GRID_MAX_DIM = 9 -HSA_AGENT_INFO_GRID_MAX_SIZE = 10 -HSA_AGENT_INFO_FBARRIER_MAX_SIZE = 11 -HSA_AGENT_INFO_QUEUES_MAX = 12 -HSA_AGENT_INFO_QUEUE_MIN_SIZE = 13 -HSA_AGENT_INFO_QUEUE_MAX_SIZE = 14 -HSA_AGENT_INFO_QUEUE_TYPE = 15 -HSA_AGENT_INFO_NODE = 16 -HSA_AGENT_INFO_DEVICE = 17 -HSA_AGENT_INFO_CACHE_SIZE = 18 -HSA_AGENT_INFO_ISA = 19 -HSA_AGENT_INFO_EXTENSIONS = 20 -HSA_AGENT_INFO_VERSION_MAJOR = 21 -HSA_AGENT_INFO_VERSION_MINOR = 22 -HSA_AGENT_INFO_LAST = 2147483647 -c__EA_hsa_agent_info_t = ctypes.c_uint32 # enum -hsa_agent_info_t = c__EA_hsa_agent_info_t -hsa_agent_info_t__enumvalues = c__EA_hsa_agent_info_t__enumvalues -try: - hsa_agent_get_info = _libraries['libhsa-runtime64.so'].hsa_agent_get_info - hsa_agent_get_info.restype = hsa_status_t - hsa_agent_get_info.argtypes = [hsa_agent_t, hsa_agent_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_iterate_agents = _libraries['libhsa-runtime64.so'].hsa_iterate_agents - hsa_iterate_agents.restype = hsa_status_t - hsa_iterate_agents.argtypes = [ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_agent_get_info(hsa_agent_t agent, hsa_agent_info_t attribute, void *value) +try: (hsa_agent_get_info:=dll.hsa_agent_get_info).restype, hsa_agent_get_info.argtypes = hsa_status_t, [hsa_agent_t, hsa_agent_info_t, ctypes.c_void_p] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_exception_policy_t' -c__EA_hsa_exception_policy_t__enumvalues = { - 1: 'HSA_EXCEPTION_POLICY_BREAK', - 2: 'HSA_EXCEPTION_POLICY_DETECT', -} -HSA_EXCEPTION_POLICY_BREAK = 1 -HSA_EXCEPTION_POLICY_DETECT = 2 -c__EA_hsa_exception_policy_t = ctypes.c_uint32 # enum -hsa_exception_policy_t = c__EA_hsa_exception_policy_t -hsa_exception_policy_t__enumvalues = c__EA_hsa_exception_policy_t__enumvalues -try: - hsa_agent_get_exception_policies = _libraries['libhsa-runtime64.so'].hsa_agent_get_exception_policies - hsa_agent_get_exception_policies.restype = hsa_status_t - hsa_agent_get_exception_policies.argtypes = [hsa_agent_t, hsa_profile_t, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -class struct_hsa_cache_s(Structure): - pass +# hsa_status_t hsa_iterate_agents(hsa_status_t (*callback)(hsa_agent_t, void *), void *data) +try: (hsa_iterate_agents:=dll.hsa_iterate_agents).restype, hsa_iterate_agents.argtypes = hsa_status_t, [ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass -struct_hsa_cache_s._pack_ = 1 # source:False +hsa_exception_policy_t = CEnum(ctypes.c_uint32) +HSA_EXCEPTION_POLICY_BREAK = hsa_exception_policy_t.define('HSA_EXCEPTION_POLICY_BREAK', 1) +HSA_EXCEPTION_POLICY_DETECT = hsa_exception_policy_t.define('HSA_EXCEPTION_POLICY_DETECT', 2) + +# hsa_status_t hsa_agent_get_exception_policies(hsa_agent_t agent, hsa_profile_t profile, uint16_t *mask) +try: (hsa_agent_get_exception_policies:=dll.hsa_agent_get_exception_policies).restype, hsa_agent_get_exception_policies.argtypes = hsa_status_t, [hsa_agent_t, hsa_profile_t, ctypes.POINTER(uint16_t)] +except AttributeError: pass + +class struct_hsa_cache_s(Struct): pass struct_hsa_cache_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_cache_t = struct_hsa_cache_s +hsa_cache_info_t = CEnum(ctypes.c_uint32) +HSA_CACHE_INFO_NAME_LENGTH = hsa_cache_info_t.define('HSA_CACHE_INFO_NAME_LENGTH', 0) +HSA_CACHE_INFO_NAME = hsa_cache_info_t.define('HSA_CACHE_INFO_NAME', 1) +HSA_CACHE_INFO_LEVEL = hsa_cache_info_t.define('HSA_CACHE_INFO_LEVEL', 2) +HSA_CACHE_INFO_SIZE = hsa_cache_info_t.define('HSA_CACHE_INFO_SIZE', 3) -# values for enumeration 'c__EA_hsa_cache_info_t' -c__EA_hsa_cache_info_t__enumvalues = { - 0: 'HSA_CACHE_INFO_NAME_LENGTH', - 1: 'HSA_CACHE_INFO_NAME', - 2: 'HSA_CACHE_INFO_LEVEL', - 3: 'HSA_CACHE_INFO_SIZE', -} -HSA_CACHE_INFO_NAME_LENGTH = 0 -HSA_CACHE_INFO_NAME = 1 -HSA_CACHE_INFO_LEVEL = 2 -HSA_CACHE_INFO_SIZE = 3 -c__EA_hsa_cache_info_t = ctypes.c_uint32 # enum -hsa_cache_info_t = c__EA_hsa_cache_info_t -hsa_cache_info_t__enumvalues = c__EA_hsa_cache_info_t__enumvalues -try: - hsa_cache_get_info = _libraries['libhsa-runtime64.so'].hsa_cache_get_info - hsa_cache_get_info.restype = hsa_status_t - hsa_cache_get_info.argtypes = [hsa_cache_t, hsa_cache_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_agent_iterate_caches = _libraries['libhsa-runtime64.so'].hsa_agent_iterate_caches - hsa_agent_iterate_caches.restype = hsa_status_t - hsa_agent_iterate_caches.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_cache_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_agent_extension_supported = _libraries['libhsa-runtime64.so'].hsa_agent_extension_supported - hsa_agent_extension_supported.restype = hsa_status_t - hsa_agent_extension_supported.argtypes = [uint16_t, hsa_agent_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_agent_major_extension_supported = _libraries['libhsa-runtime64.so'].hsa_agent_major_extension_supported - hsa_agent_major_extension_supported.restype = hsa_status_t - hsa_agent_major_extension_supported.argtypes = [uint16_t, hsa_agent_t, uint16_t, ctypes.POINTER(ctypes.c_uint16), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -class struct_hsa_signal_s(Structure): - pass +# hsa_status_t hsa_cache_get_info(hsa_cache_t cache, hsa_cache_info_t attribute, void *value) +try: (hsa_cache_get_info:=dll.hsa_cache_get_info).restype, hsa_cache_get_info.argtypes = hsa_status_t, [hsa_cache_t, hsa_cache_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_signal_s._pack_ = 1 # source:False +# hsa_status_t hsa_agent_iterate_caches(hsa_agent_t agent, hsa_status_t (*callback)(hsa_cache_t, void *), void *data) +try: (hsa_agent_iterate_caches:=dll.hsa_agent_iterate_caches).restype, hsa_agent_iterate_caches.argtypes = hsa_status_t, [hsa_agent_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_cache_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_agent_extension_supported(uint16_t extension, hsa_agent_t agent, uint16_t version_major, uint16_t version_minor, bool *result) +try: (hsa_agent_extension_supported:=dll.hsa_agent_extension_supported).restype, hsa_agent_extension_supported.argtypes = hsa_status_t, [uint16_t, hsa_agent_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +# hsa_status_t hsa_agent_major_extension_supported(uint16_t extension, hsa_agent_t agent, uint16_t version_major, uint16_t *version_minor, bool *result) +try: (hsa_agent_major_extension_supported:=dll.hsa_agent_major_extension_supported).restype, hsa_agent_major_extension_supported.argtypes = hsa_status_t, [uint16_t, hsa_agent_t, uint16_t, ctypes.POINTER(uint16_t), ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +class struct_hsa_signal_s(Struct): pass struct_hsa_signal_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_signal_t = struct_hsa_signal_s hsa_signal_value_t = ctypes.c_int64 -uint32_t = ctypes.c_uint32 -try: - hsa_signal_create = _libraries['libhsa-runtime64.so'].hsa_signal_create - hsa_signal_create.restype = hsa_status_t - hsa_signal_create.argtypes = [hsa_signal_value_t, uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(struct_hsa_signal_s)] -except AttributeError: - pass -try: - hsa_signal_destroy = _libraries['libhsa-runtime64.so'].hsa_signal_destroy - hsa_signal_destroy.restype = hsa_status_t - hsa_signal_destroy.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_load_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_load_scacquire - hsa_signal_load_scacquire.restype = hsa_signal_value_t - hsa_signal_load_scacquire.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_load_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_load_relaxed - hsa_signal_load_relaxed.restype = hsa_signal_value_t - hsa_signal_load_relaxed.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_load_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_load_acquire - hsa_signal_load_acquire.restype = hsa_signal_value_t - hsa_signal_load_acquire.argtypes = [hsa_signal_t] -except AttributeError: - pass -try: - hsa_signal_store_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_store_relaxed - hsa_signal_store_relaxed.restype = None - hsa_signal_store_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_store_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_store_screlease - hsa_signal_store_screlease.restype = None - hsa_signal_store_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_store_release = _libraries['libhsa-runtime64.so'].hsa_signal_store_release - hsa_signal_store_release.restype = None - hsa_signal_store_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_silent_store_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_silent_store_relaxed - hsa_signal_silent_store_relaxed.restype = None - hsa_signal_silent_store_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_silent_store_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_silent_store_screlease - hsa_signal_silent_store_screlease.restype = None - hsa_signal_silent_store_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_scacq_screl - hsa_signal_exchange_scacq_screl.restype = hsa_signal_value_t - hsa_signal_exchange_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_acq_rel - hsa_signal_exchange_acq_rel.restype = hsa_signal_value_t - hsa_signal_exchange_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_scacquire - hsa_signal_exchange_scacquire.restype = hsa_signal_value_t - hsa_signal_exchange_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_acquire - hsa_signal_exchange_acquire.restype = hsa_signal_value_t - hsa_signal_exchange_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_relaxed - hsa_signal_exchange_relaxed.restype = hsa_signal_value_t - hsa_signal_exchange_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_screlease - hsa_signal_exchange_screlease.restype = hsa_signal_value_t - hsa_signal_exchange_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_exchange_release = _libraries['libhsa-runtime64.so'].hsa_signal_exchange_release - hsa_signal_exchange_release.restype = hsa_signal_value_t - hsa_signal_exchange_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_cas_scacq_screl - hsa_signal_cas_scacq_screl.restype = hsa_signal_value_t - hsa_signal_cas_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_cas_acq_rel - hsa_signal_cas_acq_rel.restype = hsa_signal_value_t - hsa_signal_cas_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_cas_scacquire - hsa_signal_cas_scacquire.restype = hsa_signal_value_t - hsa_signal_cas_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_cas_acquire - hsa_signal_cas_acquire.restype = hsa_signal_value_t - hsa_signal_cas_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_cas_relaxed - hsa_signal_cas_relaxed.restype = hsa_signal_value_t - hsa_signal_cas_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_cas_screlease - hsa_signal_cas_screlease.restype = hsa_signal_value_t - hsa_signal_cas_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_cas_release = _libraries['libhsa-runtime64.so'].hsa_signal_cas_release - hsa_signal_cas_release.restype = hsa_signal_value_t - hsa_signal_cas_release.argtypes = [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_add_scacq_screl - hsa_signal_add_scacq_screl.restype = None - hsa_signal_add_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_add_acq_rel - hsa_signal_add_acq_rel.restype = None - hsa_signal_add_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_add_scacquire - hsa_signal_add_scacquire.restype = None - hsa_signal_add_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_add_acquire - hsa_signal_add_acquire.restype = None - hsa_signal_add_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_add_relaxed - hsa_signal_add_relaxed.restype = None - hsa_signal_add_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_add_screlease - hsa_signal_add_screlease.restype = None - hsa_signal_add_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_add_release = _libraries['libhsa-runtime64.so'].hsa_signal_add_release - hsa_signal_add_release.restype = None - hsa_signal_add_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_scacq_screl - hsa_signal_subtract_scacq_screl.restype = None - hsa_signal_subtract_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_acq_rel - hsa_signal_subtract_acq_rel.restype = None - hsa_signal_subtract_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_scacquire - hsa_signal_subtract_scacquire.restype = None - hsa_signal_subtract_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_acquire - hsa_signal_subtract_acquire.restype = None - hsa_signal_subtract_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_relaxed - hsa_signal_subtract_relaxed.restype = None - hsa_signal_subtract_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_screlease - hsa_signal_subtract_screlease.restype = None - hsa_signal_subtract_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_subtract_release = _libraries['libhsa-runtime64.so'].hsa_signal_subtract_release - hsa_signal_subtract_release.restype = None - hsa_signal_subtract_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_and_scacq_screl - hsa_signal_and_scacq_screl.restype = None - hsa_signal_and_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_and_acq_rel - hsa_signal_and_acq_rel.restype = None - hsa_signal_and_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_and_scacquire - hsa_signal_and_scacquire.restype = None - hsa_signal_and_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_and_acquire - hsa_signal_and_acquire.restype = None - hsa_signal_and_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_and_relaxed - hsa_signal_and_relaxed.restype = None - hsa_signal_and_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_and_screlease - hsa_signal_and_screlease.restype = None - hsa_signal_and_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_and_release = _libraries['libhsa-runtime64.so'].hsa_signal_and_release - hsa_signal_and_release.restype = None - hsa_signal_and_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_or_scacq_screl - hsa_signal_or_scacq_screl.restype = None - hsa_signal_or_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_or_acq_rel - hsa_signal_or_acq_rel.restype = None - hsa_signal_or_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_or_scacquire - hsa_signal_or_scacquire.restype = None - hsa_signal_or_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_or_acquire - hsa_signal_or_acquire.restype = None - hsa_signal_or_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_or_relaxed - hsa_signal_or_relaxed.restype = None - hsa_signal_or_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_or_screlease - hsa_signal_or_screlease.restype = None - hsa_signal_or_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_or_release = _libraries['libhsa-runtime64.so'].hsa_signal_or_release - hsa_signal_or_release.restype = None - hsa_signal_or_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_signal_xor_scacq_screl - hsa_signal_xor_scacq_screl.restype = None - hsa_signal_xor_scacq_screl.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_acq_rel = _libraries['libhsa-runtime64.so'].hsa_signal_xor_acq_rel - hsa_signal_xor_acq_rel.restype = None - hsa_signal_xor_acq_rel.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_xor_scacquire - hsa_signal_xor_scacquire.restype = None - hsa_signal_xor_scacquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_xor_acquire - hsa_signal_xor_acquire.restype = None - hsa_signal_xor_acquire.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_xor_relaxed - hsa_signal_xor_relaxed.restype = None - hsa_signal_xor_relaxed.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_screlease = _libraries['libhsa-runtime64.so'].hsa_signal_xor_screlease - hsa_signal_xor_screlease.restype = None - hsa_signal_xor_screlease.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass -try: - hsa_signal_xor_release = _libraries['libhsa-runtime64.so'].hsa_signal_xor_release - hsa_signal_xor_release.restype = None - hsa_signal_xor_release.argtypes = [hsa_signal_t, hsa_signal_value_t] -except AttributeError: - pass +# hsa_status_t hsa_signal_create(hsa_signal_value_t initial_value, uint32_t num_consumers, const hsa_agent_t *consumers, hsa_signal_t *signal) +try: (hsa_signal_create:=dll.hsa_signal_create).restype, hsa_signal_create.argtypes = hsa_status_t, [hsa_signal_value_t, uint32_t, ctypes.POINTER(hsa_agent_t), ctypes.POINTER(hsa_signal_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_signal_condition_t' -c__EA_hsa_signal_condition_t__enumvalues = { - 0: 'HSA_SIGNAL_CONDITION_EQ', - 1: 'HSA_SIGNAL_CONDITION_NE', - 2: 'HSA_SIGNAL_CONDITION_LT', - 3: 'HSA_SIGNAL_CONDITION_GTE', -} -HSA_SIGNAL_CONDITION_EQ = 0 -HSA_SIGNAL_CONDITION_NE = 1 -HSA_SIGNAL_CONDITION_LT = 2 -HSA_SIGNAL_CONDITION_GTE = 3 -c__EA_hsa_signal_condition_t = ctypes.c_uint32 # enum -hsa_signal_condition_t = c__EA_hsa_signal_condition_t -hsa_signal_condition_t__enumvalues = c__EA_hsa_signal_condition_t__enumvalues +# hsa_status_t hsa_signal_destroy(hsa_signal_t signal) +try: (hsa_signal_destroy:=dll.hsa_signal_destroy).restype, hsa_signal_destroy.argtypes = hsa_status_t, [hsa_signal_t] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_wait_state_t' -c__EA_hsa_wait_state_t__enumvalues = { - 0: 'HSA_WAIT_STATE_BLOCKED', - 1: 'HSA_WAIT_STATE_ACTIVE', -} -HSA_WAIT_STATE_BLOCKED = 0 -HSA_WAIT_STATE_ACTIVE = 1 -c__EA_hsa_wait_state_t = ctypes.c_uint32 # enum -hsa_wait_state_t = c__EA_hsa_wait_state_t -hsa_wait_state_t__enumvalues = c__EA_hsa_wait_state_t__enumvalues -uint64_t = ctypes.c_uint64 -try: - hsa_signal_wait_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_wait_scacquire - hsa_signal_wait_scacquire.restype = hsa_signal_value_t - hsa_signal_wait_scacquire.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] -except AttributeError: - pass -try: - hsa_signal_wait_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_wait_relaxed - hsa_signal_wait_relaxed.restype = hsa_signal_value_t - hsa_signal_wait_relaxed.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] -except AttributeError: - pass -try: - hsa_signal_wait_acquire = _libraries['libhsa-runtime64.so'].hsa_signal_wait_acquire - hsa_signal_wait_acquire.restype = hsa_signal_value_t - hsa_signal_wait_acquire.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] -except AttributeError: - pass -class struct_hsa_signal_group_s(Structure): - pass +# hsa_signal_value_t hsa_signal_load_scacquire(hsa_signal_t signal) +try: (hsa_signal_load_scacquire:=dll.hsa_signal_load_scacquire).restype, hsa_signal_load_scacquire.argtypes = hsa_signal_value_t, [hsa_signal_t] +except AttributeError: pass -struct_hsa_signal_group_s._pack_ = 1 # source:False +# hsa_signal_value_t hsa_signal_load_relaxed(hsa_signal_t signal) +try: (hsa_signal_load_relaxed:=dll.hsa_signal_load_relaxed).restype, hsa_signal_load_relaxed.argtypes = hsa_signal_value_t, [hsa_signal_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_load_acquire(hsa_signal_t signal) +try: (hsa_signal_load_acquire:=dll.hsa_signal_load_acquire).restype, hsa_signal_load_acquire.argtypes = hsa_signal_value_t, [hsa_signal_t] +except AttributeError: pass + +# void hsa_signal_store_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_store_relaxed:=dll.hsa_signal_store_relaxed).restype, hsa_signal_store_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_store_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_store_screlease:=dll.hsa_signal_store_screlease).restype, hsa_signal_store_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_store_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_store_release:=dll.hsa_signal_store_release).restype, hsa_signal_store_release.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_silent_store_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_silent_store_relaxed:=dll.hsa_signal_silent_store_relaxed).restype, hsa_signal_silent_store_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_silent_store_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_silent_store_screlease:=dll.hsa_signal_silent_store_screlease).restype, hsa_signal_silent_store_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_scacq_screl(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_scacq_screl:=dll.hsa_signal_exchange_scacq_screl).restype, hsa_signal_exchange_scacq_screl.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_acq_rel(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_acq_rel:=dll.hsa_signal_exchange_acq_rel).restype, hsa_signal_exchange_acq_rel.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_scacquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_scacquire:=dll.hsa_signal_exchange_scacquire).restype, hsa_signal_exchange_scacquire.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_acquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_acquire:=dll.hsa_signal_exchange_acquire).restype, hsa_signal_exchange_acquire.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_relaxed:=dll.hsa_signal_exchange_relaxed).restype, hsa_signal_exchange_relaxed.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_screlease:=dll.hsa_signal_exchange_screlease).restype, hsa_signal_exchange_screlease.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_exchange_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_exchange_release:=dll.hsa_signal_exchange_release).restype, hsa_signal_exchange_release.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_scacq_screl(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_scacq_screl:=dll.hsa_signal_cas_scacq_screl).restype, hsa_signal_cas_scacq_screl.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_acq_rel(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_acq_rel:=dll.hsa_signal_cas_acq_rel).restype, hsa_signal_cas_acq_rel.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_scacquire(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_scacquire:=dll.hsa_signal_cas_scacquire).restype, hsa_signal_cas_scacquire.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_acquire(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_acquire:=dll.hsa_signal_cas_acquire).restype, hsa_signal_cas_acquire.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_relaxed(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_relaxed:=dll.hsa_signal_cas_relaxed).restype, hsa_signal_cas_relaxed.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_screlease(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_screlease:=dll.hsa_signal_cas_screlease).restype, hsa_signal_cas_screlease.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_cas_release(hsa_signal_t signal, hsa_signal_value_t expected, hsa_signal_value_t value) +try: (hsa_signal_cas_release:=dll.hsa_signal_cas_release).restype, hsa_signal_cas_release.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_value_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_scacq_screl(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_scacq_screl:=dll.hsa_signal_add_scacq_screl).restype, hsa_signal_add_scacq_screl.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_acq_rel(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_acq_rel:=dll.hsa_signal_add_acq_rel).restype, hsa_signal_add_acq_rel.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_scacquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_scacquire:=dll.hsa_signal_add_scacquire).restype, hsa_signal_add_scacquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_acquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_acquire:=dll.hsa_signal_add_acquire).restype, hsa_signal_add_acquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_relaxed:=dll.hsa_signal_add_relaxed).restype, hsa_signal_add_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_screlease:=dll.hsa_signal_add_screlease).restype, hsa_signal_add_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_add_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_add_release:=dll.hsa_signal_add_release).restype, hsa_signal_add_release.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_scacq_screl(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_scacq_screl:=dll.hsa_signal_subtract_scacq_screl).restype, hsa_signal_subtract_scacq_screl.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_acq_rel(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_acq_rel:=dll.hsa_signal_subtract_acq_rel).restype, hsa_signal_subtract_acq_rel.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_scacquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_scacquire:=dll.hsa_signal_subtract_scacquire).restype, hsa_signal_subtract_scacquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_acquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_acquire:=dll.hsa_signal_subtract_acquire).restype, hsa_signal_subtract_acquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_relaxed:=dll.hsa_signal_subtract_relaxed).restype, hsa_signal_subtract_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_screlease:=dll.hsa_signal_subtract_screlease).restype, hsa_signal_subtract_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_subtract_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_subtract_release:=dll.hsa_signal_subtract_release).restype, hsa_signal_subtract_release.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_scacq_screl(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_scacq_screl:=dll.hsa_signal_and_scacq_screl).restype, hsa_signal_and_scacq_screl.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_acq_rel(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_acq_rel:=dll.hsa_signal_and_acq_rel).restype, hsa_signal_and_acq_rel.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_scacquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_scacquire:=dll.hsa_signal_and_scacquire).restype, hsa_signal_and_scacquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_acquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_acquire:=dll.hsa_signal_and_acquire).restype, hsa_signal_and_acquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_relaxed:=dll.hsa_signal_and_relaxed).restype, hsa_signal_and_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_screlease:=dll.hsa_signal_and_screlease).restype, hsa_signal_and_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_and_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_and_release:=dll.hsa_signal_and_release).restype, hsa_signal_and_release.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_scacq_screl(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_scacq_screl:=dll.hsa_signal_or_scacq_screl).restype, hsa_signal_or_scacq_screl.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_acq_rel(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_acq_rel:=dll.hsa_signal_or_acq_rel).restype, hsa_signal_or_acq_rel.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_scacquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_scacquire:=dll.hsa_signal_or_scacquire).restype, hsa_signal_or_scacquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_acquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_acquire:=dll.hsa_signal_or_acquire).restype, hsa_signal_or_acquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_relaxed:=dll.hsa_signal_or_relaxed).restype, hsa_signal_or_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_screlease:=dll.hsa_signal_or_screlease).restype, hsa_signal_or_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_or_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_or_release:=dll.hsa_signal_or_release).restype, hsa_signal_or_release.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_scacq_screl(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_scacq_screl:=dll.hsa_signal_xor_scacq_screl).restype, hsa_signal_xor_scacq_screl.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_acq_rel(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_acq_rel:=dll.hsa_signal_xor_acq_rel).restype, hsa_signal_xor_acq_rel.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_scacquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_scacquire:=dll.hsa_signal_xor_scacquire).restype, hsa_signal_xor_scacquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_acquire(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_acquire:=dll.hsa_signal_xor_acquire).restype, hsa_signal_xor_acquire.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_relaxed(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_relaxed:=dll.hsa_signal_xor_relaxed).restype, hsa_signal_xor_relaxed.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_screlease(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_screlease:=dll.hsa_signal_xor_screlease).restype, hsa_signal_xor_screlease.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +# void hsa_signal_xor_release(hsa_signal_t signal, hsa_signal_value_t value) +try: (hsa_signal_xor_release:=dll.hsa_signal_xor_release).restype, hsa_signal_xor_release.argtypes = None, [hsa_signal_t, hsa_signal_value_t] +except AttributeError: pass + +hsa_signal_condition_t = CEnum(ctypes.c_uint32) +HSA_SIGNAL_CONDITION_EQ = hsa_signal_condition_t.define('HSA_SIGNAL_CONDITION_EQ', 0) +HSA_SIGNAL_CONDITION_NE = hsa_signal_condition_t.define('HSA_SIGNAL_CONDITION_NE', 1) +HSA_SIGNAL_CONDITION_LT = hsa_signal_condition_t.define('HSA_SIGNAL_CONDITION_LT', 2) +HSA_SIGNAL_CONDITION_GTE = hsa_signal_condition_t.define('HSA_SIGNAL_CONDITION_GTE', 3) + +hsa_wait_state_t = CEnum(ctypes.c_uint32) +HSA_WAIT_STATE_BLOCKED = hsa_wait_state_t.define('HSA_WAIT_STATE_BLOCKED', 0) +HSA_WAIT_STATE_ACTIVE = hsa_wait_state_t.define('HSA_WAIT_STATE_ACTIVE', 1) + +# hsa_signal_value_t hsa_signal_wait_scacquire(hsa_signal_t signal, hsa_signal_condition_t condition, hsa_signal_value_t compare_value, uint64_t timeout_hint, hsa_wait_state_t wait_state_hint) +try: (hsa_signal_wait_scacquire:=dll.hsa_signal_wait_scacquire).restype, hsa_signal_wait_scacquire.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_wait_relaxed(hsa_signal_t signal, hsa_signal_condition_t condition, hsa_signal_value_t compare_value, uint64_t timeout_hint, hsa_wait_state_t wait_state_hint) +try: (hsa_signal_wait_relaxed:=dll.hsa_signal_wait_relaxed).restype, hsa_signal_wait_relaxed.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] +except AttributeError: pass + +# hsa_signal_value_t hsa_signal_wait_acquire(hsa_signal_t signal, hsa_signal_condition_t condition, hsa_signal_value_t compare_value, uint64_t timeout_hint, hsa_wait_state_t wait_state_hint) +try: (hsa_signal_wait_acquire:=dll.hsa_signal_wait_acquire).restype, hsa_signal_wait_acquire.argtypes = hsa_signal_value_t, [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, uint64_t, hsa_wait_state_t] +except AttributeError: pass + +class struct_hsa_signal_group_s(Struct): pass struct_hsa_signal_group_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_signal_group_t = struct_hsa_signal_group_s -try: - hsa_signal_group_create = _libraries['libhsa-runtime64.so'].hsa_signal_group_create - hsa_signal_group_create.restype = hsa_status_t - hsa_signal_group_create.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_signal_s), uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(struct_hsa_signal_group_s)] -except AttributeError: - pass -try: - hsa_signal_group_destroy = _libraries['libhsa-runtime64.so'].hsa_signal_group_destroy - hsa_signal_group_destroy.restype = hsa_status_t - hsa_signal_group_destroy.argtypes = [hsa_signal_group_t] -except AttributeError: - pass -try: - hsa_signal_group_wait_any_scacquire = _libraries['libhsa-runtime64.so'].hsa_signal_group_wait_any_scacquire - hsa_signal_group_wait_any_scacquire.restype = hsa_status_t - hsa_signal_group_wait_any_scacquire.argtypes = [hsa_signal_group_t, ctypes.POINTER(c__EA_hsa_signal_condition_t), ctypes.POINTER(ctypes.c_int64), hsa_wait_state_t, ctypes.POINTER(struct_hsa_signal_s), ctypes.POINTER(ctypes.c_int64)] -except AttributeError: - pass -try: - hsa_signal_group_wait_any_relaxed = _libraries['libhsa-runtime64.so'].hsa_signal_group_wait_any_relaxed - hsa_signal_group_wait_any_relaxed.restype = hsa_status_t - hsa_signal_group_wait_any_relaxed.argtypes = [hsa_signal_group_t, ctypes.POINTER(c__EA_hsa_signal_condition_t), ctypes.POINTER(ctypes.c_int64), hsa_wait_state_t, ctypes.POINTER(struct_hsa_signal_s), ctypes.POINTER(ctypes.c_int64)] -except AttributeError: - pass -class struct_hsa_region_s(Structure): - pass +# hsa_status_t hsa_signal_group_create(uint32_t num_signals, const hsa_signal_t *signals, uint32_t num_consumers, const hsa_agent_t *consumers, hsa_signal_group_t *signal_group) +try: (hsa_signal_group_create:=dll.hsa_signal_group_create).restype, hsa_signal_group_create.argtypes = hsa_status_t, [uint32_t, ctypes.POINTER(hsa_signal_t), uint32_t, ctypes.POINTER(hsa_agent_t), ctypes.POINTER(hsa_signal_group_t)] +except AttributeError: pass -struct_hsa_region_s._pack_ = 1 # source:False +# hsa_status_t hsa_signal_group_destroy(hsa_signal_group_t signal_group) +try: (hsa_signal_group_destroy:=dll.hsa_signal_group_destroy).restype, hsa_signal_group_destroy.argtypes = hsa_status_t, [hsa_signal_group_t] +except AttributeError: pass + +# hsa_status_t hsa_signal_group_wait_any_scacquire(hsa_signal_group_t signal_group, const hsa_signal_condition_t *conditions, const hsa_signal_value_t *compare_values, hsa_wait_state_t wait_state_hint, hsa_signal_t *signal, hsa_signal_value_t *value) +try: (hsa_signal_group_wait_any_scacquire:=dll.hsa_signal_group_wait_any_scacquire).restype, hsa_signal_group_wait_any_scacquire.argtypes = hsa_status_t, [hsa_signal_group_t, ctypes.POINTER(hsa_signal_condition_t), ctypes.POINTER(hsa_signal_value_t), hsa_wait_state_t, ctypes.POINTER(hsa_signal_t), ctypes.POINTER(hsa_signal_value_t)] +except AttributeError: pass + +# hsa_status_t hsa_signal_group_wait_any_relaxed(hsa_signal_group_t signal_group, const hsa_signal_condition_t *conditions, const hsa_signal_value_t *compare_values, hsa_wait_state_t wait_state_hint, hsa_signal_t *signal, hsa_signal_value_t *value) +try: (hsa_signal_group_wait_any_relaxed:=dll.hsa_signal_group_wait_any_relaxed).restype, hsa_signal_group_wait_any_relaxed.argtypes = hsa_status_t, [hsa_signal_group_t, ctypes.POINTER(hsa_signal_condition_t), ctypes.POINTER(hsa_signal_value_t), hsa_wait_state_t, ctypes.POINTER(hsa_signal_t), ctypes.POINTER(hsa_signal_value_t)] +except AttributeError: pass + +class struct_hsa_region_s(Struct): pass struct_hsa_region_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_region_t = struct_hsa_region_s +hsa_queue_type_t = CEnum(ctypes.c_uint32) +HSA_QUEUE_TYPE_MULTI = hsa_queue_type_t.define('HSA_QUEUE_TYPE_MULTI', 0) +HSA_QUEUE_TYPE_SINGLE = hsa_queue_type_t.define('HSA_QUEUE_TYPE_SINGLE', 1) +HSA_QUEUE_TYPE_COOPERATIVE = hsa_queue_type_t.define('HSA_QUEUE_TYPE_COOPERATIVE', 2) -# values for enumeration 'c__EA_hsa_queue_type_t' -c__EA_hsa_queue_type_t__enumvalues = { - 0: 'HSA_QUEUE_TYPE_MULTI', - 1: 'HSA_QUEUE_TYPE_SINGLE', - 2: 'HSA_QUEUE_TYPE_COOPERATIVE', -} -HSA_QUEUE_TYPE_MULTI = 0 -HSA_QUEUE_TYPE_SINGLE = 1 -HSA_QUEUE_TYPE_COOPERATIVE = 2 -c__EA_hsa_queue_type_t = ctypes.c_uint32 # enum -hsa_queue_type_t = c__EA_hsa_queue_type_t -hsa_queue_type_t__enumvalues = c__EA_hsa_queue_type_t__enumvalues hsa_queue_type32_t = ctypes.c_uint32 +hsa_queue_feature_t = CEnum(ctypes.c_uint32) +HSA_QUEUE_FEATURE_KERNEL_DISPATCH = hsa_queue_feature_t.define('HSA_QUEUE_FEATURE_KERNEL_DISPATCH', 1) +HSA_QUEUE_FEATURE_AGENT_DISPATCH = hsa_queue_feature_t.define('HSA_QUEUE_FEATURE_AGENT_DISPATCH', 2) -# values for enumeration 'c__EA_hsa_queue_feature_t' -c__EA_hsa_queue_feature_t__enumvalues = { - 1: 'HSA_QUEUE_FEATURE_KERNEL_DISPATCH', - 2: 'HSA_QUEUE_FEATURE_AGENT_DISPATCH', -} -HSA_QUEUE_FEATURE_KERNEL_DISPATCH = 1 -HSA_QUEUE_FEATURE_AGENT_DISPATCH = 2 -c__EA_hsa_queue_feature_t = ctypes.c_uint32 # enum -hsa_queue_feature_t = c__EA_hsa_queue_feature_t -hsa_queue_feature_t__enumvalues = c__EA_hsa_queue_feature_t__enumvalues -class struct_hsa_queue_s(Structure): - pass - -struct_hsa_queue_s._pack_ = 1 # source:False +class struct_hsa_queue_s(Struct): pass struct_hsa_queue_s._fields_ = [ - ('type', ctypes.c_uint32), - ('features', ctypes.c_uint32), - ('base_address', ctypes.POINTER(None)), - ('doorbell_signal', hsa_signal_t), - ('size', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('id', ctypes.c_uint64), + ('type', hsa_queue_type32_t), + ('features', uint32_t), + ('base_address', ctypes.c_void_p), + ('doorbell_signal', hsa_signal_t), + ('size', uint32_t), + ('reserved1', uint32_t), + ('id', uint64_t), ] - hsa_queue_t = struct_hsa_queue_s -try: - hsa_queue_create = _libraries['libhsa-runtime64.so'].hsa_queue_create - hsa_queue_create.restype = hsa_status_t - hsa_queue_create.argtypes = [hsa_agent_t, uint32_t, hsa_queue_type32_t, ctypes.CFUNCTYPE(None, c__EA_hsa_status_t, ctypes.POINTER(struct_hsa_queue_s), ctypes.POINTER(None)), ctypes.POINTER(None), uint32_t, uint32_t, ctypes.POINTER(ctypes.POINTER(struct_hsa_queue_s))] -except AttributeError: - pass -try: - hsa_soft_queue_create = _libraries['libhsa-runtime64.so'].hsa_soft_queue_create - hsa_soft_queue_create.restype = hsa_status_t - hsa_soft_queue_create.argtypes = [hsa_region_t, uint32_t, hsa_queue_type32_t, uint32_t, hsa_signal_t, ctypes.POINTER(ctypes.POINTER(struct_hsa_queue_s))] -except AttributeError: - pass -try: - hsa_queue_destroy = _libraries['libhsa-runtime64.so'].hsa_queue_destroy - hsa_queue_destroy.restype = hsa_status_t - hsa_queue_destroy.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_inactivate = _libraries['libhsa-runtime64.so'].hsa_queue_inactivate - hsa_queue_inactivate.restype = hsa_status_t - hsa_queue_inactivate.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_read_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_read_index_acquire - hsa_queue_load_read_index_acquire.restype = uint64_t - hsa_queue_load_read_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_read_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_read_index_scacquire - hsa_queue_load_read_index_scacquire.restype = uint64_t - hsa_queue_load_read_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_read_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_load_read_index_relaxed - hsa_queue_load_read_index_relaxed.restype = uint64_t - hsa_queue_load_read_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_write_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_write_index_acquire - hsa_queue_load_write_index_acquire.restype = uint64_t - hsa_queue_load_write_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_write_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_load_write_index_scacquire - hsa_queue_load_write_index_scacquire.restype = uint64_t - hsa_queue_load_write_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_load_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_load_write_index_relaxed - hsa_queue_load_write_index_relaxed.restype = uint64_t - hsa_queue_load_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s)] -except AttributeError: - pass -try: - hsa_queue_store_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_store_write_index_relaxed - hsa_queue_store_write_index_relaxed.restype = None - hsa_queue_store_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_write_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_store_write_index_release - hsa_queue_store_write_index_release.restype = None - hsa_queue_store_write_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_write_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_store_write_index_screlease - hsa_queue_store_write_index_screlease.restype = None - hsa_queue_store_write_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_acq_rel = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_acq_rel - hsa_queue_cas_write_index_acq_rel.restype = uint64_t - hsa_queue_cas_write_index_acq_rel.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_scacq_screl - hsa_queue_cas_write_index_scacq_screl.restype = uint64_t - hsa_queue_cas_write_index_scacq_screl.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_acquire - hsa_queue_cas_write_index_acquire.restype = uint64_t - hsa_queue_cas_write_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_scacquire - hsa_queue_cas_write_index_scacquire.restype = uint64_t - hsa_queue_cas_write_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_relaxed - hsa_queue_cas_write_index_relaxed.restype = uint64_t - hsa_queue_cas_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_release - hsa_queue_cas_write_index_release.restype = uint64_t - hsa_queue_cas_write_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_cas_write_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_cas_write_index_screlease - hsa_queue_cas_write_index_screlease.restype = uint64_t - hsa_queue_cas_write_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_acq_rel = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_acq_rel - hsa_queue_add_write_index_acq_rel.restype = uint64_t - hsa_queue_add_write_index_acq_rel.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_scacq_screl = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_scacq_screl - hsa_queue_add_write_index_scacq_screl.restype = uint64_t - hsa_queue_add_write_index_scacq_screl.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_acquire = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_acquire - hsa_queue_add_write_index_acquire.restype = uint64_t - hsa_queue_add_write_index_acquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_scacquire = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_scacquire - hsa_queue_add_write_index_scacquire.restype = uint64_t - hsa_queue_add_write_index_scacquire.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_relaxed - hsa_queue_add_write_index_relaxed.restype = uint64_t - hsa_queue_add_write_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_release - hsa_queue_add_write_index_release.restype = uint64_t - hsa_queue_add_write_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_add_write_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_add_write_index_screlease - hsa_queue_add_write_index_screlease.restype = uint64_t - hsa_queue_add_write_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_read_index_relaxed = _libraries['libhsa-runtime64.so'].hsa_queue_store_read_index_relaxed - hsa_queue_store_read_index_relaxed.restype = None - hsa_queue_store_read_index_relaxed.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_read_index_release = _libraries['libhsa-runtime64.so'].hsa_queue_store_read_index_release - hsa_queue_store_read_index_release.restype = None - hsa_queue_store_read_index_release.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass -try: - hsa_queue_store_read_index_screlease = _libraries['libhsa-runtime64.so'].hsa_queue_store_read_index_screlease - hsa_queue_store_read_index_screlease.restype = None - hsa_queue_store_read_index_screlease.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint64_t] -except AttributeError: - pass +# hsa_status_t hsa_queue_create(hsa_agent_t agent, uint32_t size, hsa_queue_type32_t type, void (*callback)(hsa_status_t, hsa_queue_t *, void *), void *data, uint32_t private_segment_size, uint32_t group_segment_size, hsa_queue_t **queue) +try: (hsa_queue_create:=dll.hsa_queue_create).restype, hsa_queue_create.argtypes = hsa_status_t, [hsa_agent_t, uint32_t, hsa_queue_type32_t, ctypes.CFUNCTYPE(None, hsa_status_t, ctypes.POINTER(hsa_queue_t), ctypes.c_void_p), ctypes.c_void_p, uint32_t, uint32_t, ctypes.POINTER(ctypes.POINTER(hsa_queue_t))] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_packet_type_t' -c__EA_hsa_packet_type_t__enumvalues = { - 0: 'HSA_PACKET_TYPE_VENDOR_SPECIFIC', - 1: 'HSA_PACKET_TYPE_INVALID', - 2: 'HSA_PACKET_TYPE_KERNEL_DISPATCH', - 3: 'HSA_PACKET_TYPE_BARRIER_AND', - 4: 'HSA_PACKET_TYPE_AGENT_DISPATCH', - 5: 'HSA_PACKET_TYPE_BARRIER_OR', -} -HSA_PACKET_TYPE_VENDOR_SPECIFIC = 0 -HSA_PACKET_TYPE_INVALID = 1 -HSA_PACKET_TYPE_KERNEL_DISPATCH = 2 -HSA_PACKET_TYPE_BARRIER_AND = 3 -HSA_PACKET_TYPE_AGENT_DISPATCH = 4 -HSA_PACKET_TYPE_BARRIER_OR = 5 -c__EA_hsa_packet_type_t = ctypes.c_uint32 # enum -hsa_packet_type_t = c__EA_hsa_packet_type_t -hsa_packet_type_t__enumvalues = c__EA_hsa_packet_type_t__enumvalues +# hsa_status_t hsa_soft_queue_create(hsa_region_t region, uint32_t size, hsa_queue_type32_t type, uint32_t features, hsa_signal_t doorbell_signal, hsa_queue_t **queue) +try: (hsa_soft_queue_create:=dll.hsa_soft_queue_create).restype, hsa_soft_queue_create.argtypes = hsa_status_t, [hsa_region_t, uint32_t, hsa_queue_type32_t, uint32_t, hsa_signal_t, ctypes.POINTER(ctypes.POINTER(hsa_queue_t))] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_fence_scope_t' -c__EA_hsa_fence_scope_t__enumvalues = { - 0: 'HSA_FENCE_SCOPE_NONE', - 1: 'HSA_FENCE_SCOPE_AGENT', - 2: 'HSA_FENCE_SCOPE_SYSTEM', -} -HSA_FENCE_SCOPE_NONE = 0 -HSA_FENCE_SCOPE_AGENT = 1 -HSA_FENCE_SCOPE_SYSTEM = 2 -c__EA_hsa_fence_scope_t = ctypes.c_uint32 # enum -hsa_fence_scope_t = c__EA_hsa_fence_scope_t -hsa_fence_scope_t__enumvalues = c__EA_hsa_fence_scope_t__enumvalues +# hsa_status_t hsa_queue_destroy(hsa_queue_t *queue) +try: (hsa_queue_destroy:=dll.hsa_queue_destroy).restype, hsa_queue_destroy.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_packet_header_t' -c__EA_hsa_packet_header_t__enumvalues = { - 0: 'HSA_PACKET_HEADER_TYPE', - 8: 'HSA_PACKET_HEADER_BARRIER', - 9: 'HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE', - 9: 'HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE', - 11: 'HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE', - 11: 'HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE', -} -HSA_PACKET_HEADER_TYPE = 0 -HSA_PACKET_HEADER_BARRIER = 8 -HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE = 9 -HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE = 9 -HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE = 11 -HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE = 11 -c__EA_hsa_packet_header_t = ctypes.c_uint32 # enum -hsa_packet_header_t = c__EA_hsa_packet_header_t -hsa_packet_header_t__enumvalues = c__EA_hsa_packet_header_t__enumvalues +# hsa_status_t hsa_queue_inactivate(hsa_queue_t *queue) +try: (hsa_queue_inactivate:=dll.hsa_queue_inactivate).restype, hsa_queue_inactivate.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_packet_header_width_t' -c__EA_hsa_packet_header_width_t__enumvalues = { - 8: 'HSA_PACKET_HEADER_WIDTH_TYPE', - 1: 'HSA_PACKET_HEADER_WIDTH_BARRIER', - 2: 'HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE', - 2: 'HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE', - 2: 'HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE', - 2: 'HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE', -} -HSA_PACKET_HEADER_WIDTH_TYPE = 8 -HSA_PACKET_HEADER_WIDTH_BARRIER = 1 -HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE = 2 -HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE = 2 -HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE = 2 -HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE = 2 -c__EA_hsa_packet_header_width_t = ctypes.c_uint32 # enum -hsa_packet_header_width_t = c__EA_hsa_packet_header_width_t -hsa_packet_header_width_t__enumvalues = c__EA_hsa_packet_header_width_t__enumvalues +# uint64_t hsa_queue_load_read_index_acquire(const hsa_queue_t *queue) +try: (hsa_queue_load_read_index_acquire:=dll.hsa_queue_load_read_index_acquire).restype, hsa_queue_load_read_index_acquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_kernel_dispatch_packet_setup_t' -c__EA_hsa_kernel_dispatch_packet_setup_t__enumvalues = { - 0: 'HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS', -} -HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS = 0 -c__EA_hsa_kernel_dispatch_packet_setup_t = ctypes.c_uint32 # enum -hsa_kernel_dispatch_packet_setup_t = c__EA_hsa_kernel_dispatch_packet_setup_t -hsa_kernel_dispatch_packet_setup_t__enumvalues = c__EA_hsa_kernel_dispatch_packet_setup_t__enumvalues +# uint64_t hsa_queue_load_read_index_scacquire(const hsa_queue_t *queue) +try: (hsa_queue_load_read_index_scacquire:=dll.hsa_queue_load_read_index_scacquire).restype, hsa_queue_load_read_index_scacquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_kernel_dispatch_packet_setup_width_t' -c__EA_hsa_kernel_dispatch_packet_setup_width_t__enumvalues = { - 2: 'HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS', -} -HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS = 2 -c__EA_hsa_kernel_dispatch_packet_setup_width_t = ctypes.c_uint32 # enum -hsa_kernel_dispatch_packet_setup_width_t = c__EA_hsa_kernel_dispatch_packet_setup_width_t -hsa_kernel_dispatch_packet_setup_width_t__enumvalues = c__EA_hsa_kernel_dispatch_packet_setup_width_t__enumvalues -class struct_hsa_kernel_dispatch_packet_s(Structure): - pass +# uint64_t hsa_queue_load_read_index_relaxed(const hsa_queue_t *queue) +try: (hsa_queue_load_read_index_relaxed:=dll.hsa_queue_load_read_index_relaxed).restype, hsa_queue_load_read_index_relaxed.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass -struct_hsa_kernel_dispatch_packet_s._pack_ = 1 # source:False +# uint64_t hsa_queue_load_write_index_acquire(const hsa_queue_t *queue) +try: (hsa_queue_load_write_index_acquire:=dll.hsa_queue_load_write_index_acquire).restype, hsa_queue_load_write_index_acquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass + +# uint64_t hsa_queue_load_write_index_scacquire(const hsa_queue_t *queue) +try: (hsa_queue_load_write_index_scacquire:=dll.hsa_queue_load_write_index_scacquire).restype, hsa_queue_load_write_index_scacquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass + +# uint64_t hsa_queue_load_write_index_relaxed(const hsa_queue_t *queue) +try: (hsa_queue_load_write_index_relaxed:=dll.hsa_queue_load_write_index_relaxed).restype, hsa_queue_load_write_index_relaxed.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t)] +except AttributeError: pass + +# void hsa_queue_store_write_index_relaxed(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_store_write_index_relaxed:=dll.hsa_queue_store_write_index_relaxed).restype, hsa_queue_store_write_index_relaxed.argtypes = None, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# void hsa_queue_store_write_index_release(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_store_write_index_release:=dll.hsa_queue_store_write_index_release).restype, hsa_queue_store_write_index_release.argtypes = None, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# void hsa_queue_store_write_index_screlease(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_store_write_index_screlease:=dll.hsa_queue_store_write_index_screlease).restype, hsa_queue_store_write_index_screlease.argtypes = None, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_acq_rel(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_acq_rel:=dll.hsa_queue_cas_write_index_acq_rel).restype, hsa_queue_cas_write_index_acq_rel.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_scacq_screl(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_scacq_screl:=dll.hsa_queue_cas_write_index_scacq_screl).restype, hsa_queue_cas_write_index_scacq_screl.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_acquire(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_acquire:=dll.hsa_queue_cas_write_index_acquire).restype, hsa_queue_cas_write_index_acquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_scacquire(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_scacquire:=dll.hsa_queue_cas_write_index_scacquire).restype, hsa_queue_cas_write_index_scacquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_relaxed(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_relaxed:=dll.hsa_queue_cas_write_index_relaxed).restype, hsa_queue_cas_write_index_relaxed.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_release(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_release:=dll.hsa_queue_cas_write_index_release).restype, hsa_queue_cas_write_index_release.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_cas_write_index_screlease(const hsa_queue_t *queue, uint64_t expected, uint64_t value) +try: (hsa_queue_cas_write_index_screlease:=dll.hsa_queue_cas_write_index_screlease).restype, hsa_queue_cas_write_index_screlease.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t, uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_acq_rel(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_acq_rel:=dll.hsa_queue_add_write_index_acq_rel).restype, hsa_queue_add_write_index_acq_rel.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_scacq_screl(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_scacq_screl:=dll.hsa_queue_add_write_index_scacq_screl).restype, hsa_queue_add_write_index_scacq_screl.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_acquire(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_acquire:=dll.hsa_queue_add_write_index_acquire).restype, hsa_queue_add_write_index_acquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_scacquire(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_scacquire:=dll.hsa_queue_add_write_index_scacquire).restype, hsa_queue_add_write_index_scacquire.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_relaxed(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_relaxed:=dll.hsa_queue_add_write_index_relaxed).restype, hsa_queue_add_write_index_relaxed.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_release(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_release:=dll.hsa_queue_add_write_index_release).restype, hsa_queue_add_write_index_release.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# uint64_t hsa_queue_add_write_index_screlease(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_add_write_index_screlease:=dll.hsa_queue_add_write_index_screlease).restype, hsa_queue_add_write_index_screlease.argtypes = uint64_t, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# void hsa_queue_store_read_index_relaxed(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_store_read_index_relaxed:=dll.hsa_queue_store_read_index_relaxed).restype, hsa_queue_store_read_index_relaxed.argtypes = None, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# void hsa_queue_store_read_index_release(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_store_read_index_release:=dll.hsa_queue_store_read_index_release).restype, hsa_queue_store_read_index_release.argtypes = None, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +# void hsa_queue_store_read_index_screlease(const hsa_queue_t *queue, uint64_t value) +try: (hsa_queue_store_read_index_screlease:=dll.hsa_queue_store_read_index_screlease).restype, hsa_queue_store_read_index_screlease.argtypes = None, [ctypes.POINTER(hsa_queue_t), uint64_t] +except AttributeError: pass + +hsa_packet_type_t = CEnum(ctypes.c_uint32) +HSA_PACKET_TYPE_VENDOR_SPECIFIC = hsa_packet_type_t.define('HSA_PACKET_TYPE_VENDOR_SPECIFIC', 0) +HSA_PACKET_TYPE_INVALID = hsa_packet_type_t.define('HSA_PACKET_TYPE_INVALID', 1) +HSA_PACKET_TYPE_KERNEL_DISPATCH = hsa_packet_type_t.define('HSA_PACKET_TYPE_KERNEL_DISPATCH', 2) +HSA_PACKET_TYPE_BARRIER_AND = hsa_packet_type_t.define('HSA_PACKET_TYPE_BARRIER_AND', 3) +HSA_PACKET_TYPE_AGENT_DISPATCH = hsa_packet_type_t.define('HSA_PACKET_TYPE_AGENT_DISPATCH', 4) +HSA_PACKET_TYPE_BARRIER_OR = hsa_packet_type_t.define('HSA_PACKET_TYPE_BARRIER_OR', 5) + +hsa_fence_scope_t = CEnum(ctypes.c_uint32) +HSA_FENCE_SCOPE_NONE = hsa_fence_scope_t.define('HSA_FENCE_SCOPE_NONE', 0) +HSA_FENCE_SCOPE_AGENT = hsa_fence_scope_t.define('HSA_FENCE_SCOPE_AGENT', 1) +HSA_FENCE_SCOPE_SYSTEM = hsa_fence_scope_t.define('HSA_FENCE_SCOPE_SYSTEM', 2) + +hsa_packet_header_t = CEnum(ctypes.c_uint32) +HSA_PACKET_HEADER_TYPE = hsa_packet_header_t.define('HSA_PACKET_HEADER_TYPE', 0) +HSA_PACKET_HEADER_BARRIER = hsa_packet_header_t.define('HSA_PACKET_HEADER_BARRIER', 8) +HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE = hsa_packet_header_t.define('HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE', 9) +HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE = hsa_packet_header_t.define('HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE', 9) +HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE = hsa_packet_header_t.define('HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE', 11) +HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE = hsa_packet_header_t.define('HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE', 11) + +hsa_packet_header_width_t = CEnum(ctypes.c_uint32) +HSA_PACKET_HEADER_WIDTH_TYPE = hsa_packet_header_width_t.define('HSA_PACKET_HEADER_WIDTH_TYPE', 8) +HSA_PACKET_HEADER_WIDTH_BARRIER = hsa_packet_header_width_t.define('HSA_PACKET_HEADER_WIDTH_BARRIER', 1) +HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE = hsa_packet_header_width_t.define('HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE', 2) +HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE = hsa_packet_header_width_t.define('HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE', 2) +HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE = hsa_packet_header_width_t.define('HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE', 2) +HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE = hsa_packet_header_width_t.define('HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE', 2) + +hsa_kernel_dispatch_packet_setup_t = CEnum(ctypes.c_uint32) +HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS = hsa_kernel_dispatch_packet_setup_t.define('HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS', 0) + +hsa_kernel_dispatch_packet_setup_width_t = CEnum(ctypes.c_uint32) +HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS = hsa_kernel_dispatch_packet_setup_width_t.define('HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS', 2) + +class struct_hsa_kernel_dispatch_packet_s(Struct): pass struct_hsa_kernel_dispatch_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('setup', ctypes.c_uint16), - ('workgroup_size_x', ctypes.c_uint16), - ('workgroup_size_y', ctypes.c_uint16), - ('workgroup_size_z', ctypes.c_uint16), - ('reserved0', ctypes.c_uint16), - ('grid_size_x', ctypes.c_uint32), - ('grid_size_y', ctypes.c_uint32), - ('grid_size_z', ctypes.c_uint32), - ('private_segment_size', ctypes.c_uint32), - ('group_segment_size', ctypes.c_uint32), - ('kernel_object', ctypes.c_uint64), - ('kernarg_address', ctypes.POINTER(None)), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), + ('header', uint16_t), + ('setup', uint16_t), + ('workgroup_size_x', uint16_t), + ('workgroup_size_y', uint16_t), + ('workgroup_size_z', uint16_t), + ('reserved0', uint16_t), + ('grid_size_x', uint32_t), + ('grid_size_y', uint32_t), + ('grid_size_z', uint32_t), + ('private_segment_size', uint32_t), + ('group_segment_size', uint32_t), + ('kernel_object', uint64_t), + ('kernarg_address', ctypes.c_void_p), + ('reserved2', uint64_t), + ('completion_signal', hsa_signal_t), ] - hsa_kernel_dispatch_packet_t = struct_hsa_kernel_dispatch_packet_s -class struct_hsa_agent_dispatch_packet_s(Structure): - pass - -struct_hsa_agent_dispatch_packet_s._pack_ = 1 # source:False +class struct_hsa_agent_dispatch_packet_s(Struct): pass struct_hsa_agent_dispatch_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('type', ctypes.c_uint16), - ('reserved0', ctypes.c_uint32), - ('return_address', ctypes.POINTER(None)), - ('arg', ctypes.c_uint64 * 4), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), + ('header', uint16_t), + ('type', uint16_t), + ('reserved0', uint32_t), + ('return_address', ctypes.c_void_p), + ('arg', (uint64_t * 4)), + ('reserved2', uint64_t), + ('completion_signal', hsa_signal_t), ] - hsa_agent_dispatch_packet_t = struct_hsa_agent_dispatch_packet_s -class struct_hsa_barrier_and_packet_s(Structure): - pass - -struct_hsa_barrier_and_packet_s._pack_ = 1 # source:False +class struct_hsa_barrier_and_packet_s(Struct): pass struct_hsa_barrier_and_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('reserved0', ctypes.c_uint16), - ('reserved1', ctypes.c_uint32), - ('dep_signal', struct_hsa_signal_s * 5), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), + ('header', uint16_t), + ('reserved0', uint16_t), + ('reserved1', uint32_t), + ('dep_signal', (hsa_signal_t * 5)), + ('reserved2', uint64_t), + ('completion_signal', hsa_signal_t), ] - hsa_barrier_and_packet_t = struct_hsa_barrier_and_packet_s -class struct_hsa_barrier_or_packet_s(Structure): - pass - -struct_hsa_barrier_or_packet_s._pack_ = 1 # source:False +class struct_hsa_barrier_or_packet_s(Struct): pass struct_hsa_barrier_or_packet_s._fields_ = [ - ('header', ctypes.c_uint16), - ('reserved0', ctypes.c_uint16), - ('reserved1', ctypes.c_uint32), - ('dep_signal', struct_hsa_signal_s * 5), - ('reserved2', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), + ('header', uint16_t), + ('reserved0', uint16_t), + ('reserved1', uint32_t), + ('dep_signal', (hsa_signal_t * 5)), + ('reserved2', uint64_t), + ('completion_signal', hsa_signal_t), ] - hsa_barrier_or_packet_t = struct_hsa_barrier_or_packet_s +hsa_region_segment_t = CEnum(ctypes.c_uint32) +HSA_REGION_SEGMENT_GLOBAL = hsa_region_segment_t.define('HSA_REGION_SEGMENT_GLOBAL', 0) +HSA_REGION_SEGMENT_READONLY = hsa_region_segment_t.define('HSA_REGION_SEGMENT_READONLY', 1) +HSA_REGION_SEGMENT_PRIVATE = hsa_region_segment_t.define('HSA_REGION_SEGMENT_PRIVATE', 2) +HSA_REGION_SEGMENT_GROUP = hsa_region_segment_t.define('HSA_REGION_SEGMENT_GROUP', 3) +HSA_REGION_SEGMENT_KERNARG = hsa_region_segment_t.define('HSA_REGION_SEGMENT_KERNARG', 4) -# values for enumeration 'c__EA_hsa_region_segment_t' -c__EA_hsa_region_segment_t__enumvalues = { - 0: 'HSA_REGION_SEGMENT_GLOBAL', - 1: 'HSA_REGION_SEGMENT_READONLY', - 2: 'HSA_REGION_SEGMENT_PRIVATE', - 3: 'HSA_REGION_SEGMENT_GROUP', - 4: 'HSA_REGION_SEGMENT_KERNARG', -} -HSA_REGION_SEGMENT_GLOBAL = 0 -HSA_REGION_SEGMENT_READONLY = 1 -HSA_REGION_SEGMENT_PRIVATE = 2 -HSA_REGION_SEGMENT_GROUP = 3 -HSA_REGION_SEGMENT_KERNARG = 4 -c__EA_hsa_region_segment_t = ctypes.c_uint32 # enum -hsa_region_segment_t = c__EA_hsa_region_segment_t -hsa_region_segment_t__enumvalues = c__EA_hsa_region_segment_t__enumvalues +hsa_region_global_flag_t = CEnum(ctypes.c_uint32) +HSA_REGION_GLOBAL_FLAG_KERNARG = hsa_region_global_flag_t.define('HSA_REGION_GLOBAL_FLAG_KERNARG', 1) +HSA_REGION_GLOBAL_FLAG_FINE_GRAINED = hsa_region_global_flag_t.define('HSA_REGION_GLOBAL_FLAG_FINE_GRAINED', 2) +HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED = hsa_region_global_flag_t.define('HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED', 4) +HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED = hsa_region_global_flag_t.define('HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', 8) -# values for enumeration 'c__EA_hsa_region_global_flag_t' -c__EA_hsa_region_global_flag_t__enumvalues = { - 1: 'HSA_REGION_GLOBAL_FLAG_KERNARG', - 2: 'HSA_REGION_GLOBAL_FLAG_FINE_GRAINED', - 4: 'HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED', - 8: 'HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', -} -HSA_REGION_GLOBAL_FLAG_KERNARG = 1 -HSA_REGION_GLOBAL_FLAG_FINE_GRAINED = 2 -HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED = 4 -HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED = 8 -c__EA_hsa_region_global_flag_t = ctypes.c_uint32 # enum -hsa_region_global_flag_t = c__EA_hsa_region_global_flag_t -hsa_region_global_flag_t__enumvalues = c__EA_hsa_region_global_flag_t__enumvalues +hsa_region_info_t = CEnum(ctypes.c_uint32) +HSA_REGION_INFO_SEGMENT = hsa_region_info_t.define('HSA_REGION_INFO_SEGMENT', 0) +HSA_REGION_INFO_GLOBAL_FLAGS = hsa_region_info_t.define('HSA_REGION_INFO_GLOBAL_FLAGS', 1) +HSA_REGION_INFO_SIZE = hsa_region_info_t.define('HSA_REGION_INFO_SIZE', 2) +HSA_REGION_INFO_ALLOC_MAX_SIZE = hsa_region_info_t.define('HSA_REGION_INFO_ALLOC_MAX_SIZE', 4) +HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE = hsa_region_info_t.define('HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE', 8) +HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED = hsa_region_info_t.define('HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED', 5) +HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE = hsa_region_info_t.define('HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE', 6) +HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT = hsa_region_info_t.define('HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT', 7) -# values for enumeration 'c__EA_hsa_region_info_t' -c__EA_hsa_region_info_t__enumvalues = { - 0: 'HSA_REGION_INFO_SEGMENT', - 1: 'HSA_REGION_INFO_GLOBAL_FLAGS', - 2: 'HSA_REGION_INFO_SIZE', - 4: 'HSA_REGION_INFO_ALLOC_MAX_SIZE', - 8: 'HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE', - 5: 'HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED', - 6: 'HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE', - 7: 'HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT', -} -HSA_REGION_INFO_SEGMENT = 0 -HSA_REGION_INFO_GLOBAL_FLAGS = 1 -HSA_REGION_INFO_SIZE = 2 -HSA_REGION_INFO_ALLOC_MAX_SIZE = 4 -HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE = 8 -HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED = 5 -HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE = 6 -HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT = 7 -c__EA_hsa_region_info_t = ctypes.c_uint32 # enum -hsa_region_info_t = c__EA_hsa_region_info_t -hsa_region_info_t__enumvalues = c__EA_hsa_region_info_t__enumvalues -try: - hsa_region_get_info = _libraries['libhsa-runtime64.so'].hsa_region_get_info - hsa_region_get_info.restype = hsa_status_t - hsa_region_get_info.argtypes = [hsa_region_t, hsa_region_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_agent_iterate_regions = _libraries['libhsa-runtime64.so'].hsa_agent_iterate_regions - hsa_agent_iterate_regions.restype = hsa_status_t - hsa_agent_iterate_regions.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_region_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_memory_allocate = _libraries['libhsa-runtime64.so'].hsa_memory_allocate - hsa_memory_allocate.restype = hsa_status_t - hsa_memory_allocate.argtypes = [hsa_region_t, size_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_memory_free = _libraries['libhsa-runtime64.so'].hsa_memory_free - hsa_memory_free.restype = hsa_status_t - hsa_memory_free.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_memory_copy = _libraries['libhsa-runtime64.so'].hsa_memory_copy - hsa_memory_copy.restype = hsa_status_t - hsa_memory_copy.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hsa_memory_assign_agent = _libraries['libhsa-runtime64.so'].hsa_memory_assign_agent - hsa_memory_assign_agent.restype = hsa_status_t - hsa_memory_assign_agent.argtypes = [ctypes.POINTER(None), hsa_agent_t, hsa_access_permission_t] -except AttributeError: - pass -try: - hsa_memory_register = _libraries['libhsa-runtime64.so'].hsa_memory_register - hsa_memory_register.restype = hsa_status_t - hsa_memory_register.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - hsa_memory_deregister = _libraries['libhsa-runtime64.so'].hsa_memory_deregister - hsa_memory_deregister.restype = hsa_status_t - hsa_memory_deregister.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_hsa_isa_s(Structure): - pass +# hsa_status_t hsa_region_get_info(hsa_region_t region, hsa_region_info_t attribute, void *value) +try: (hsa_region_get_info:=dll.hsa_region_get_info).restype, hsa_region_get_info.argtypes = hsa_status_t, [hsa_region_t, hsa_region_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_isa_s._pack_ = 1 # source:False +# hsa_status_t hsa_agent_iterate_regions(hsa_agent_t agent, hsa_status_t (*callback)(hsa_region_t, void *), void *data) +try: (hsa_agent_iterate_regions:=dll.hsa_agent_iterate_regions).restype, hsa_agent_iterate_regions.argtypes = hsa_status_t, [hsa_agent_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_region_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_memory_allocate(hsa_region_t region, size_t size, void **ptr) +try: (hsa_memory_allocate:=dll.hsa_memory_allocate).restype, hsa_memory_allocate.argtypes = hsa_status_t, [hsa_region_t, size_t, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hsa_status_t hsa_memory_free(void *ptr) +try: (hsa_memory_free:=dll.hsa_memory_free).restype, hsa_memory_free.argtypes = hsa_status_t, [ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_memory_copy(void *dst, const void *src, size_t size) +try: (hsa_memory_copy:=dll.hsa_memory_copy).restype, hsa_memory_copy.argtypes = hsa_status_t, [ctypes.c_void_p, ctypes.c_void_p, size_t] +except AttributeError: pass + +# hsa_status_t hsa_memory_assign_agent(void *ptr, hsa_agent_t agent, hsa_access_permission_t access) +try: (hsa_memory_assign_agent:=dll.hsa_memory_assign_agent).restype, hsa_memory_assign_agent.argtypes = hsa_status_t, [ctypes.c_void_p, hsa_agent_t, hsa_access_permission_t] +except AttributeError: pass + +# hsa_status_t hsa_memory_register(void *ptr, size_t size) +try: (hsa_memory_register:=dll.hsa_memory_register).restype, hsa_memory_register.argtypes = hsa_status_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# hsa_status_t hsa_memory_deregister(void *ptr, size_t size) +try: (hsa_memory_deregister:=dll.hsa_memory_deregister).restype, hsa_memory_deregister.argtypes = hsa_status_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +class struct_hsa_isa_s(Struct): pass struct_hsa_isa_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_isa_t = struct_hsa_isa_s -try: - hsa_isa_from_name = _libraries['libhsa-runtime64.so'].hsa_isa_from_name - hsa_isa_from_name.restype = hsa_status_t - hsa_isa_from_name.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_isa_s)] -except AttributeError: - pass -try: - hsa_agent_iterate_isas = _libraries['libhsa-runtime64.so'].hsa_agent_iterate_isas - hsa_agent_iterate_isas.restype = hsa_status_t - hsa_agent_iterate_isas.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_isa_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_isa_from_name(const char *name, hsa_isa_t *isa) +try: (hsa_isa_from_name:=dll.hsa_isa_from_name).restype, hsa_isa_from_name.argtypes = hsa_status_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_isa_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_isa_info_t' -c__EA_hsa_isa_info_t__enumvalues = { - 0: 'HSA_ISA_INFO_NAME_LENGTH', - 1: 'HSA_ISA_INFO_NAME', - 2: 'HSA_ISA_INFO_CALL_CONVENTION_COUNT', - 3: 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE', - 4: 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT', - 5: 'HSA_ISA_INFO_MACHINE_MODELS', - 6: 'HSA_ISA_INFO_PROFILES', - 7: 'HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES', - 8: 'HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 9: 'HSA_ISA_INFO_FAST_F16_OPERATION', - 12: 'HSA_ISA_INFO_WORKGROUP_MAX_DIM', - 13: 'HSA_ISA_INFO_WORKGROUP_MAX_SIZE', - 14: 'HSA_ISA_INFO_GRID_MAX_DIM', - 16: 'HSA_ISA_INFO_GRID_MAX_SIZE', - 17: 'HSA_ISA_INFO_FBARRIER_MAX_SIZE', -} -HSA_ISA_INFO_NAME_LENGTH = 0 -HSA_ISA_INFO_NAME = 1 -HSA_ISA_INFO_CALL_CONVENTION_COUNT = 2 -HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE = 3 -HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT = 4 -HSA_ISA_INFO_MACHINE_MODELS = 5 -HSA_ISA_INFO_PROFILES = 6 -HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES = 7 -HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = 8 -HSA_ISA_INFO_FAST_F16_OPERATION = 9 -HSA_ISA_INFO_WORKGROUP_MAX_DIM = 12 -HSA_ISA_INFO_WORKGROUP_MAX_SIZE = 13 -HSA_ISA_INFO_GRID_MAX_DIM = 14 -HSA_ISA_INFO_GRID_MAX_SIZE = 16 -HSA_ISA_INFO_FBARRIER_MAX_SIZE = 17 -c__EA_hsa_isa_info_t = ctypes.c_uint32 # enum -hsa_isa_info_t = c__EA_hsa_isa_info_t -hsa_isa_info_t__enumvalues = c__EA_hsa_isa_info_t__enumvalues -try: - hsa_isa_get_info = _libraries['libhsa-runtime64.so'].hsa_isa_get_info - hsa_isa_get_info.restype = hsa_status_t - hsa_isa_get_info.argtypes = [hsa_isa_t, hsa_isa_info_t, uint32_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_get_info_alt = _libraries['libhsa-runtime64.so'].hsa_isa_get_info_alt - hsa_isa_get_info_alt.restype = hsa_status_t - hsa_isa_get_info_alt.argtypes = [hsa_isa_t, hsa_isa_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_get_exception_policies = _libraries['libhsa-runtime64.so'].hsa_isa_get_exception_policies - hsa_isa_get_exception_policies.restype = hsa_status_t - hsa_isa_get_exception_policies.argtypes = [hsa_isa_t, hsa_profile_t, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass +# hsa_status_t hsa_agent_iterate_isas(hsa_agent_t agent, hsa_status_t (*callback)(hsa_isa_t, void *), void *data) +try: (hsa_agent_iterate_isas:=dll.hsa_agent_iterate_isas).restype, hsa_agent_iterate_isas.argtypes = hsa_status_t, [hsa_agent_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_isa_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_fp_type_t' -c__EA_hsa_fp_type_t__enumvalues = { - 1: 'HSA_FP_TYPE_16', - 2: 'HSA_FP_TYPE_32', - 4: 'HSA_FP_TYPE_64', -} -HSA_FP_TYPE_16 = 1 -HSA_FP_TYPE_32 = 2 -HSA_FP_TYPE_64 = 4 -c__EA_hsa_fp_type_t = ctypes.c_uint32 # enum -hsa_fp_type_t = c__EA_hsa_fp_type_t -hsa_fp_type_t__enumvalues = c__EA_hsa_fp_type_t__enumvalues +hsa_isa_info_t = CEnum(ctypes.c_uint32) +HSA_ISA_INFO_NAME_LENGTH = hsa_isa_info_t.define('HSA_ISA_INFO_NAME_LENGTH', 0) +HSA_ISA_INFO_NAME = hsa_isa_info_t.define('HSA_ISA_INFO_NAME', 1) +HSA_ISA_INFO_CALL_CONVENTION_COUNT = hsa_isa_info_t.define('HSA_ISA_INFO_CALL_CONVENTION_COUNT', 2) +HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE = hsa_isa_info_t.define('HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE', 3) +HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT = hsa_isa_info_t.define('HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT', 4) +HSA_ISA_INFO_MACHINE_MODELS = hsa_isa_info_t.define('HSA_ISA_INFO_MACHINE_MODELS', 5) +HSA_ISA_INFO_PROFILES = hsa_isa_info_t.define('HSA_ISA_INFO_PROFILES', 6) +HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES = hsa_isa_info_t.define('HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES', 7) +HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES = hsa_isa_info_t.define('HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', 8) +HSA_ISA_INFO_FAST_F16_OPERATION = hsa_isa_info_t.define('HSA_ISA_INFO_FAST_F16_OPERATION', 9) +HSA_ISA_INFO_WORKGROUP_MAX_DIM = hsa_isa_info_t.define('HSA_ISA_INFO_WORKGROUP_MAX_DIM', 12) +HSA_ISA_INFO_WORKGROUP_MAX_SIZE = hsa_isa_info_t.define('HSA_ISA_INFO_WORKGROUP_MAX_SIZE', 13) +HSA_ISA_INFO_GRID_MAX_DIM = hsa_isa_info_t.define('HSA_ISA_INFO_GRID_MAX_DIM', 14) +HSA_ISA_INFO_GRID_MAX_SIZE = hsa_isa_info_t.define('HSA_ISA_INFO_GRID_MAX_SIZE', 16) +HSA_ISA_INFO_FBARRIER_MAX_SIZE = hsa_isa_info_t.define('HSA_ISA_INFO_FBARRIER_MAX_SIZE', 17) -# values for enumeration 'c__EA_hsa_flush_mode_t' -c__EA_hsa_flush_mode_t__enumvalues = { - 1: 'HSA_FLUSH_MODE_FTZ', - 2: 'HSA_FLUSH_MODE_NON_FTZ', -} -HSA_FLUSH_MODE_FTZ = 1 -HSA_FLUSH_MODE_NON_FTZ = 2 -c__EA_hsa_flush_mode_t = ctypes.c_uint32 # enum -hsa_flush_mode_t = c__EA_hsa_flush_mode_t -hsa_flush_mode_t__enumvalues = c__EA_hsa_flush_mode_t__enumvalues +# hsa_status_t hsa_isa_get_info(hsa_isa_t isa, hsa_isa_info_t attribute, uint32_t index, void *value) +try: (hsa_isa_get_info:=dll.hsa_isa_get_info).restype, hsa_isa_get_info.argtypes = hsa_status_t, [hsa_isa_t, hsa_isa_info_t, uint32_t, ctypes.c_void_p] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_round_method_t' -c__EA_hsa_round_method_t__enumvalues = { - 1: 'HSA_ROUND_METHOD_SINGLE', - 2: 'HSA_ROUND_METHOD_DOUBLE', -} -HSA_ROUND_METHOD_SINGLE = 1 -HSA_ROUND_METHOD_DOUBLE = 2 -c__EA_hsa_round_method_t = ctypes.c_uint32 # enum -hsa_round_method_t = c__EA_hsa_round_method_t -hsa_round_method_t__enumvalues = c__EA_hsa_round_method_t__enumvalues -try: - hsa_isa_get_round_method = _libraries['libhsa-runtime64.so'].hsa_isa_get_round_method - hsa_isa_get_round_method.restype = hsa_status_t - hsa_isa_get_round_method.argtypes = [hsa_isa_t, hsa_fp_type_t, hsa_flush_mode_t, ctypes.POINTER(c__EA_hsa_round_method_t)] -except AttributeError: - pass -class struct_hsa_wavefront_s(Structure): - pass +# hsa_status_t hsa_isa_get_info_alt(hsa_isa_t isa, hsa_isa_info_t attribute, void *value) +try: (hsa_isa_get_info_alt:=dll.hsa_isa_get_info_alt).restype, hsa_isa_get_info_alt.argtypes = hsa_status_t, [hsa_isa_t, hsa_isa_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_wavefront_s._pack_ = 1 # source:False +# hsa_status_t hsa_isa_get_exception_policies(hsa_isa_t isa, hsa_profile_t profile, uint16_t *mask) +try: (hsa_isa_get_exception_policies:=dll.hsa_isa_get_exception_policies).restype, hsa_isa_get_exception_policies.argtypes = hsa_status_t, [hsa_isa_t, hsa_profile_t, ctypes.POINTER(uint16_t)] +except AttributeError: pass + +hsa_fp_type_t = CEnum(ctypes.c_uint32) +HSA_FP_TYPE_16 = hsa_fp_type_t.define('HSA_FP_TYPE_16', 1) +HSA_FP_TYPE_32 = hsa_fp_type_t.define('HSA_FP_TYPE_32', 2) +HSA_FP_TYPE_64 = hsa_fp_type_t.define('HSA_FP_TYPE_64', 4) + +hsa_flush_mode_t = CEnum(ctypes.c_uint32) +HSA_FLUSH_MODE_FTZ = hsa_flush_mode_t.define('HSA_FLUSH_MODE_FTZ', 1) +HSA_FLUSH_MODE_NON_FTZ = hsa_flush_mode_t.define('HSA_FLUSH_MODE_NON_FTZ', 2) + +hsa_round_method_t = CEnum(ctypes.c_uint32) +HSA_ROUND_METHOD_SINGLE = hsa_round_method_t.define('HSA_ROUND_METHOD_SINGLE', 1) +HSA_ROUND_METHOD_DOUBLE = hsa_round_method_t.define('HSA_ROUND_METHOD_DOUBLE', 2) + +# hsa_status_t hsa_isa_get_round_method(hsa_isa_t isa, hsa_fp_type_t fp_type, hsa_flush_mode_t flush_mode, hsa_round_method_t *round_method) +try: (hsa_isa_get_round_method:=dll.hsa_isa_get_round_method).restype, hsa_isa_get_round_method.argtypes = hsa_status_t, [hsa_isa_t, hsa_fp_type_t, hsa_flush_mode_t, ctypes.POINTER(hsa_round_method_t)] +except AttributeError: pass + +class struct_hsa_wavefront_s(Struct): pass struct_hsa_wavefront_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_wavefront_t = struct_hsa_wavefront_s +hsa_wavefront_info_t = CEnum(ctypes.c_uint32) +HSA_WAVEFRONT_INFO_SIZE = hsa_wavefront_info_t.define('HSA_WAVEFRONT_INFO_SIZE', 0) -# values for enumeration 'c__EA_hsa_wavefront_info_t' -c__EA_hsa_wavefront_info_t__enumvalues = { - 0: 'HSA_WAVEFRONT_INFO_SIZE', -} -HSA_WAVEFRONT_INFO_SIZE = 0 -c__EA_hsa_wavefront_info_t = ctypes.c_uint32 # enum -hsa_wavefront_info_t = c__EA_hsa_wavefront_info_t -hsa_wavefront_info_t__enumvalues = c__EA_hsa_wavefront_info_t__enumvalues -try: - hsa_wavefront_get_info = _libraries['libhsa-runtime64.so'].hsa_wavefront_get_info - hsa_wavefront_get_info.restype = hsa_status_t - hsa_wavefront_get_info.argtypes = [hsa_wavefront_t, hsa_wavefront_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_iterate_wavefronts = _libraries['libhsa-runtime64.so'].hsa_isa_iterate_wavefronts - hsa_isa_iterate_wavefronts.restype = hsa_status_t - hsa_isa_iterate_wavefronts.argtypes = [hsa_isa_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_wavefront_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_isa_compatible = _libraries['libhsa-runtime64.so'].hsa_isa_compatible - hsa_isa_compatible.restype = hsa_status_t - hsa_isa_compatible.argtypes = [hsa_isa_t, hsa_isa_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -class struct_hsa_code_object_reader_s(Structure): - pass +# hsa_status_t hsa_wavefront_get_info(hsa_wavefront_t wavefront, hsa_wavefront_info_t attribute, void *value) +try: (hsa_wavefront_get_info:=dll.hsa_wavefront_get_info).restype, hsa_wavefront_get_info.argtypes = hsa_status_t, [hsa_wavefront_t, hsa_wavefront_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_code_object_reader_s._pack_ = 1 # source:False +# hsa_status_t hsa_isa_iterate_wavefronts(hsa_isa_t isa, hsa_status_t (*callback)(hsa_wavefront_t, void *), void *data) +try: (hsa_isa_iterate_wavefronts:=dll.hsa_isa_iterate_wavefronts).restype, hsa_isa_iterate_wavefronts.argtypes = hsa_status_t, [hsa_isa_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_wavefront_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_isa_compatible(hsa_isa_t code_object_isa, hsa_isa_t agent_isa, bool *result) +try: (hsa_isa_compatible:=dll.hsa_isa_compatible).restype, hsa_isa_compatible.argtypes = hsa_status_t, [hsa_isa_t, hsa_isa_t, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +class struct_hsa_code_object_reader_s(Struct): pass struct_hsa_code_object_reader_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_code_object_reader_t = struct_hsa_code_object_reader_s -try: - hsa_code_object_reader_create_from_file = _libraries['libhsa-runtime64.so'].hsa_code_object_reader_create_from_file - hsa_code_object_reader_create_from_file.restype = hsa_status_t - hsa_code_object_reader_create_from_file.argtypes = [hsa_file_t, ctypes.POINTER(struct_hsa_code_object_reader_s)] -except AttributeError: - pass -try: - hsa_code_object_reader_create_from_memory = _libraries['libhsa-runtime64.so'].hsa_code_object_reader_create_from_memory - hsa_code_object_reader_create_from_memory.restype = hsa_status_t - hsa_code_object_reader_create_from_memory.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_code_object_reader_s)] -except AttributeError: - pass -try: - hsa_code_object_reader_destroy = _libraries['libhsa-runtime64.so'].hsa_code_object_reader_destroy - hsa_code_object_reader_destroy.restype = hsa_status_t - hsa_code_object_reader_destroy.argtypes = [hsa_code_object_reader_t] -except AttributeError: - pass -class struct_hsa_executable_s(Structure): - pass +# hsa_status_t hsa_code_object_reader_create_from_file(hsa_file_t file, hsa_code_object_reader_t *code_object_reader) +try: (hsa_code_object_reader_create_from_file:=dll.hsa_code_object_reader_create_from_file).restype, hsa_code_object_reader_create_from_file.argtypes = hsa_status_t, [hsa_file_t, ctypes.POINTER(hsa_code_object_reader_t)] +except AttributeError: pass -struct_hsa_executable_s._pack_ = 1 # source:False +# hsa_status_t hsa_code_object_reader_create_from_memory(const void *code_object, size_t size, hsa_code_object_reader_t *code_object_reader) +try: (hsa_code_object_reader_create_from_memory:=dll.hsa_code_object_reader_create_from_memory).restype, hsa_code_object_reader_create_from_memory.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_code_object_reader_t)] +except AttributeError: pass + +# hsa_status_t hsa_code_object_reader_destroy(hsa_code_object_reader_t code_object_reader) +try: (hsa_code_object_reader_destroy:=dll.hsa_code_object_reader_destroy).restype, hsa_code_object_reader_destroy.argtypes = hsa_status_t, [hsa_code_object_reader_t] +except AttributeError: pass + +class struct_hsa_executable_s(Struct): pass struct_hsa_executable_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_executable_t = struct_hsa_executable_s +hsa_executable_state_t = CEnum(ctypes.c_uint32) +HSA_EXECUTABLE_STATE_UNFROZEN = hsa_executable_state_t.define('HSA_EXECUTABLE_STATE_UNFROZEN', 0) +HSA_EXECUTABLE_STATE_FROZEN = hsa_executable_state_t.define('HSA_EXECUTABLE_STATE_FROZEN', 1) -# values for enumeration 'c__EA_hsa_executable_state_t' -c__EA_hsa_executable_state_t__enumvalues = { - 0: 'HSA_EXECUTABLE_STATE_UNFROZEN', - 1: 'HSA_EXECUTABLE_STATE_FROZEN', -} -HSA_EXECUTABLE_STATE_UNFROZEN = 0 -HSA_EXECUTABLE_STATE_FROZEN = 1 -c__EA_hsa_executable_state_t = ctypes.c_uint32 # enum -hsa_executable_state_t = c__EA_hsa_executable_state_t -hsa_executable_state_t__enumvalues = c__EA_hsa_executable_state_t__enumvalues -try: - hsa_executable_create = _libraries['libhsa-runtime64.so'].hsa_executable_create - hsa_executable_create.restype = hsa_status_t - hsa_executable_create.argtypes = [hsa_profile_t, hsa_executable_state_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_executable_s)] -except AttributeError: - pass -try: - hsa_executable_create_alt = _libraries['libhsa-runtime64.so'].hsa_executable_create_alt - hsa_executable_create_alt.restype = hsa_status_t - hsa_executable_create_alt.argtypes = [hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_executable_s)] -except AttributeError: - pass -try: - hsa_executable_destroy = _libraries['libhsa-runtime64.so'].hsa_executable_destroy - hsa_executable_destroy.restype = hsa_status_t - hsa_executable_destroy.argtypes = [hsa_executable_t] -except AttributeError: - pass -class struct_hsa_loaded_code_object_s(Structure): - pass +# hsa_status_t hsa_executable_create(hsa_profile_t profile, hsa_executable_state_t executable_state, const char *options, hsa_executable_t *executable) +try: (hsa_executable_create:=dll.hsa_executable_create).restype, hsa_executable_create.argtypes = hsa_status_t, [hsa_profile_t, hsa_executable_state_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_executable_t)] +except AttributeError: pass -struct_hsa_loaded_code_object_s._pack_ = 1 # source:False +# hsa_status_t hsa_executable_create_alt(hsa_profile_t profile, hsa_default_float_rounding_mode_t default_float_rounding_mode, const char *options, hsa_executable_t *executable) +try: (hsa_executable_create_alt:=dll.hsa_executable_create_alt).restype, hsa_executable_create_alt.argtypes = hsa_status_t, [hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_executable_t)] +except AttributeError: pass + +# hsa_status_t hsa_executable_destroy(hsa_executable_t executable) +try: (hsa_executable_destroy:=dll.hsa_executable_destroy).restype, hsa_executable_destroy.argtypes = hsa_status_t, [hsa_executable_t] +except AttributeError: pass + +class struct_hsa_loaded_code_object_s(Struct): pass struct_hsa_loaded_code_object_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_loaded_code_object_t = struct_hsa_loaded_code_object_s -try: - hsa_executable_load_program_code_object = _libraries['libhsa-runtime64.so'].hsa_executable_load_program_code_object - hsa_executable_load_program_code_object.restype = hsa_status_t - hsa_executable_load_program_code_object.argtypes = [hsa_executable_t, hsa_code_object_reader_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_loaded_code_object_s)] -except AttributeError: - pass -try: - hsa_executable_load_agent_code_object = _libraries['libhsa-runtime64.so'].hsa_executable_load_agent_code_object - hsa_executable_load_agent_code_object.restype = hsa_status_t - hsa_executable_load_agent_code_object.argtypes = [hsa_executable_t, hsa_agent_t, hsa_code_object_reader_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_loaded_code_object_s)] -except AttributeError: - pass -try: - hsa_executable_freeze = _libraries['libhsa-runtime64.so'].hsa_executable_freeze - hsa_executable_freeze.restype = hsa_status_t - hsa_executable_freeze.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass +# hsa_status_t hsa_executable_load_program_code_object(hsa_executable_t executable, hsa_code_object_reader_t code_object_reader, const char *options, hsa_loaded_code_object_t *loaded_code_object) +try: (hsa_executable_load_program_code_object:=dll.hsa_executable_load_program_code_object).restype, hsa_executable_load_program_code_object.argtypes = hsa_status_t, [hsa_executable_t, hsa_code_object_reader_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_loaded_code_object_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_executable_info_t' -c__EA_hsa_executable_info_t__enumvalues = { - 1: 'HSA_EXECUTABLE_INFO_PROFILE', - 2: 'HSA_EXECUTABLE_INFO_STATE', - 3: 'HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE', -} -HSA_EXECUTABLE_INFO_PROFILE = 1 -HSA_EXECUTABLE_INFO_STATE = 2 -HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 3 -c__EA_hsa_executable_info_t = ctypes.c_uint32 # enum -hsa_executable_info_t = c__EA_hsa_executable_info_t -hsa_executable_info_t__enumvalues = c__EA_hsa_executable_info_t__enumvalues -try: - hsa_executable_get_info = _libraries['libhsa-runtime64.so'].hsa_executable_get_info - hsa_executable_get_info.restype = hsa_status_t - hsa_executable_get_info.argtypes = [hsa_executable_t, hsa_executable_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_global_variable_define = _libraries['libhsa-runtime64.so'].hsa_executable_global_variable_define - hsa_executable_global_variable_define.restype = hsa_status_t - hsa_executable_global_variable_define.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_agent_global_variable_define = _libraries['libhsa-runtime64.so'].hsa_executable_agent_global_variable_define - hsa_executable_agent_global_variable_define.restype = hsa_status_t - hsa_executable_agent_global_variable_define.argtypes = [hsa_executable_t, hsa_agent_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_readonly_variable_define = _libraries['libhsa-runtime64.so'].hsa_executable_readonly_variable_define - hsa_executable_readonly_variable_define.restype = hsa_status_t - hsa_executable_readonly_variable_define.argtypes = [hsa_executable_t, hsa_agent_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_validate = _libraries['libhsa-runtime64.so'].hsa_executable_validate - hsa_executable_validate.restype = hsa_status_t - hsa_executable_validate.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hsa_executable_validate_alt = _libraries['libhsa-runtime64.so'].hsa_executable_validate_alt - hsa_executable_validate_alt.restype = hsa_status_t - hsa_executable_validate_alt.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -class struct_hsa_executable_symbol_s(Structure): - pass +# hsa_status_t hsa_executable_load_agent_code_object(hsa_executable_t executable, hsa_agent_t agent, hsa_code_object_reader_t code_object_reader, const char *options, hsa_loaded_code_object_t *loaded_code_object) +try: (hsa_executable_load_agent_code_object:=dll.hsa_executable_load_agent_code_object).restype, hsa_executable_load_agent_code_object.argtypes = hsa_status_t, [hsa_executable_t, hsa_agent_t, hsa_code_object_reader_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_loaded_code_object_t)] +except AttributeError: pass -struct_hsa_executable_symbol_s._pack_ = 1 # source:False +# hsa_status_t hsa_executable_freeze(hsa_executable_t executable, const char *options) +try: (hsa_executable_freeze:=dll.hsa_executable_freeze).restype, hsa_executable_freeze.argtypes = hsa_status_t, [hsa_executable_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +hsa_executable_info_t = CEnum(ctypes.c_uint32) +HSA_EXECUTABLE_INFO_PROFILE = hsa_executable_info_t.define('HSA_EXECUTABLE_INFO_PROFILE', 1) +HSA_EXECUTABLE_INFO_STATE = hsa_executable_info_t.define('HSA_EXECUTABLE_INFO_STATE', 2) +HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE = hsa_executable_info_t.define('HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE', 3) + +# hsa_status_t hsa_executable_get_info(hsa_executable_t executable, hsa_executable_info_t attribute, void *value) +try: (hsa_executable_get_info:=dll.hsa_executable_get_info).restype, hsa_executable_get_info.argtypes = hsa_status_t, [hsa_executable_t, hsa_executable_info_t, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_global_variable_define(hsa_executable_t executable, const char *variable_name, void *address) +try: (hsa_executable_global_variable_define:=dll.hsa_executable_global_variable_define).restype, hsa_executable_global_variable_define.argtypes = hsa_status_t, [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_agent_global_variable_define(hsa_executable_t executable, hsa_agent_t agent, const char *variable_name, void *address) +try: (hsa_executable_agent_global_variable_define:=dll.hsa_executable_agent_global_variable_define).restype, hsa_executable_agent_global_variable_define.argtypes = hsa_status_t, [hsa_executable_t, hsa_agent_t, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_readonly_variable_define(hsa_executable_t executable, hsa_agent_t agent, const char *variable_name, void *address) +try: (hsa_executable_readonly_variable_define:=dll.hsa_executable_readonly_variable_define).restype, hsa_executable_readonly_variable_define.argtypes = hsa_status_t, [hsa_executable_t, hsa_agent_t, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_validate(hsa_executable_t executable, uint32_t *result) +try: (hsa_executable_validate:=dll.hsa_executable_validate).restype, hsa_executable_validate.argtypes = hsa_status_t, [hsa_executable_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# hsa_status_t hsa_executable_validate_alt(hsa_executable_t executable, const char *options, uint32_t *result) +try: (hsa_executable_validate_alt:=dll.hsa_executable_validate_alt).restype, hsa_executable_validate_alt.argtypes = hsa_status_t, [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(uint32_t)] +except AttributeError: pass + +class struct_hsa_executable_symbol_s(Struct): pass struct_hsa_executable_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_executable_symbol_t = struct_hsa_executable_symbol_s int32_t = ctypes.c_int32 -try: - hsa_executable_get_symbol = _libraries['libhsa-runtime64.so'].hsa_executable_get_symbol - hsa_executable_get_symbol.restype = hsa_status_t - hsa_executable_get_symbol.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), hsa_agent_t, int32_t, ctypes.POINTER(struct_hsa_executable_symbol_s)] -except AttributeError: - pass -try: - hsa_executable_get_symbol_by_name = _libraries['libhsa-runtime64.so'].hsa_executable_get_symbol_by_name - hsa_executable_get_symbol_by_name.restype = hsa_status_t - hsa_executable_get_symbol_by_name.argtypes = [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(struct_hsa_executable_symbol_s)] -except AttributeError: - pass +# hsa_status_t hsa_executable_get_symbol(hsa_executable_t executable, const char *module_name, const char *symbol_name, hsa_agent_t agent, int32_t call_convention, hsa_executable_symbol_t *symbol) +try: (hsa_executable_get_symbol:=dll.hsa_executable_get_symbol).restype, hsa_executable_get_symbol.argtypes = hsa_status_t, [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), hsa_agent_t, int32_t, ctypes.POINTER(hsa_executable_symbol_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_symbol_kind_t' -c__EA_hsa_symbol_kind_t__enumvalues = { - 0: 'HSA_SYMBOL_KIND_VARIABLE', - 1: 'HSA_SYMBOL_KIND_KERNEL', - 2: 'HSA_SYMBOL_KIND_INDIRECT_FUNCTION', -} -HSA_SYMBOL_KIND_VARIABLE = 0 -HSA_SYMBOL_KIND_KERNEL = 1 -HSA_SYMBOL_KIND_INDIRECT_FUNCTION = 2 -c__EA_hsa_symbol_kind_t = ctypes.c_uint32 # enum -hsa_symbol_kind_t = c__EA_hsa_symbol_kind_t -hsa_symbol_kind_t__enumvalues = c__EA_hsa_symbol_kind_t__enumvalues +# hsa_status_t hsa_executable_get_symbol_by_name(hsa_executable_t executable, const char *symbol_name, const hsa_agent_t *agent, hsa_executable_symbol_t *symbol) +try: (hsa_executable_get_symbol_by_name:=dll.hsa_executable_get_symbol_by_name).restype, hsa_executable_get_symbol_by_name.argtypes = hsa_status_t, [hsa_executable_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_agent_t), ctypes.POINTER(hsa_executable_symbol_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_symbol_linkage_t' -c__EA_hsa_symbol_linkage_t__enumvalues = { - 0: 'HSA_SYMBOL_LINKAGE_MODULE', - 1: 'HSA_SYMBOL_LINKAGE_PROGRAM', -} -HSA_SYMBOL_LINKAGE_MODULE = 0 -HSA_SYMBOL_LINKAGE_PROGRAM = 1 -c__EA_hsa_symbol_linkage_t = ctypes.c_uint32 # enum -hsa_symbol_linkage_t = c__EA_hsa_symbol_linkage_t -hsa_symbol_linkage_t__enumvalues = c__EA_hsa_symbol_linkage_t__enumvalues +hsa_symbol_kind_t = CEnum(ctypes.c_uint32) +HSA_SYMBOL_KIND_VARIABLE = hsa_symbol_kind_t.define('HSA_SYMBOL_KIND_VARIABLE', 0) +HSA_SYMBOL_KIND_KERNEL = hsa_symbol_kind_t.define('HSA_SYMBOL_KIND_KERNEL', 1) +HSA_SYMBOL_KIND_INDIRECT_FUNCTION = hsa_symbol_kind_t.define('HSA_SYMBOL_KIND_INDIRECT_FUNCTION', 2) -# values for enumeration 'c__EA_hsa_variable_allocation_t' -c__EA_hsa_variable_allocation_t__enumvalues = { - 0: 'HSA_VARIABLE_ALLOCATION_AGENT', - 1: 'HSA_VARIABLE_ALLOCATION_PROGRAM', -} -HSA_VARIABLE_ALLOCATION_AGENT = 0 -HSA_VARIABLE_ALLOCATION_PROGRAM = 1 -c__EA_hsa_variable_allocation_t = ctypes.c_uint32 # enum -hsa_variable_allocation_t = c__EA_hsa_variable_allocation_t -hsa_variable_allocation_t__enumvalues = c__EA_hsa_variable_allocation_t__enumvalues +hsa_symbol_linkage_t = CEnum(ctypes.c_uint32) +HSA_SYMBOL_LINKAGE_MODULE = hsa_symbol_linkage_t.define('HSA_SYMBOL_LINKAGE_MODULE', 0) +HSA_SYMBOL_LINKAGE_PROGRAM = hsa_symbol_linkage_t.define('HSA_SYMBOL_LINKAGE_PROGRAM', 1) -# values for enumeration 'c__EA_hsa_variable_segment_t' -c__EA_hsa_variable_segment_t__enumvalues = { - 0: 'HSA_VARIABLE_SEGMENT_GLOBAL', - 1: 'HSA_VARIABLE_SEGMENT_READONLY', -} -HSA_VARIABLE_SEGMENT_GLOBAL = 0 -HSA_VARIABLE_SEGMENT_READONLY = 1 -c__EA_hsa_variable_segment_t = ctypes.c_uint32 # enum -hsa_variable_segment_t = c__EA_hsa_variable_segment_t -hsa_variable_segment_t__enumvalues = c__EA_hsa_variable_segment_t__enumvalues +hsa_variable_allocation_t = CEnum(ctypes.c_uint32) +HSA_VARIABLE_ALLOCATION_AGENT = hsa_variable_allocation_t.define('HSA_VARIABLE_ALLOCATION_AGENT', 0) +HSA_VARIABLE_ALLOCATION_PROGRAM = hsa_variable_allocation_t.define('HSA_VARIABLE_ALLOCATION_PROGRAM', 1) -# values for enumeration 'c__EA_hsa_executable_symbol_info_t' -c__EA_hsa_executable_symbol_info_t__enumvalues = { - 0: 'HSA_EXECUTABLE_SYMBOL_INFO_TYPE', - 1: 'HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH', - 2: 'HSA_EXECUTABLE_SYMBOL_INFO_NAME', - 3: 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 4: 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME', - 20: 'HSA_EXECUTABLE_SYMBOL_INFO_AGENT', - 21: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS', - 5: 'HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE', - 17: 'HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION', - 6: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 7: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT', - 8: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 9: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE', - 10: 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST', - 22: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT', - 11: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 12: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 13: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 14: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 15: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 18: 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 23: 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT', - 16: 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', -} -HSA_EXECUTABLE_SYMBOL_INFO_TYPE = 0 -HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH = 1 -HSA_EXECUTABLE_SYMBOL_INFO_NAME = 2 -HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH = 3 -HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME = 4 -HSA_EXECUTABLE_SYMBOL_INFO_AGENT = 20 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS = 21 -HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE = 5 -HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION = 17 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION = 6 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT = 7 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT = 8 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE = 9 -HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST = 10 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT = 22 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = 11 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = 12 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = 13 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = 14 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = 15 -HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION = 18 -HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT = 23 -HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = 16 -c__EA_hsa_executable_symbol_info_t = ctypes.c_uint32 # enum -hsa_executable_symbol_info_t = c__EA_hsa_executable_symbol_info_t -hsa_executable_symbol_info_t__enumvalues = c__EA_hsa_executable_symbol_info_t__enumvalues -try: - hsa_executable_symbol_get_info = _libraries['libhsa-runtime64.so'].hsa_executable_symbol_get_info - hsa_executable_symbol_get_info.restype = hsa_status_t - hsa_executable_symbol_get_info.argtypes = [hsa_executable_symbol_t, hsa_executable_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_iterate_symbols = _libraries['libhsa-runtime64.so'].hsa_executable_iterate_symbols - hsa_executable_iterate_symbols.restype = hsa_status_t - hsa_executable_iterate_symbols.argtypes = [hsa_executable_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_executable_s, struct_hsa_executable_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_iterate_agent_symbols = _libraries['libhsa-runtime64.so'].hsa_executable_iterate_agent_symbols - hsa_executable_iterate_agent_symbols.restype = hsa_status_t - hsa_executable_iterate_agent_symbols.argtypes = [hsa_executable_t, hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_executable_s, struct_hsa_agent_s, struct_hsa_executable_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_iterate_program_symbols = _libraries['libhsa-runtime64.so'].hsa_executable_iterate_program_symbols - hsa_executable_iterate_program_symbols.restype = hsa_status_t - hsa_executable_iterate_program_symbols.argtypes = [hsa_executable_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_executable_s, struct_hsa_executable_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_code_object_s(Structure): - pass +hsa_variable_segment_t = CEnum(ctypes.c_uint32) +HSA_VARIABLE_SEGMENT_GLOBAL = hsa_variable_segment_t.define('HSA_VARIABLE_SEGMENT_GLOBAL', 0) +HSA_VARIABLE_SEGMENT_READONLY = hsa_variable_segment_t.define('HSA_VARIABLE_SEGMENT_READONLY', 1) -struct_hsa_code_object_s._pack_ = 1 # source:False +hsa_executable_symbol_info_t = CEnum(ctypes.c_uint32) +HSA_EXECUTABLE_SYMBOL_INFO_TYPE = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_TYPE', 0) +HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH', 1) +HSA_EXECUTABLE_SYMBOL_INFO_NAME = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_NAME', 2) +HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH', 3) +HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME', 4) +HSA_EXECUTABLE_SYMBOL_INFO_AGENT = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_AGENT', 20) +HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS', 21) +HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE', 5) +HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION', 17) +HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION', 6) +HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT', 7) +HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT', 8) +HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE', 9) +HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST', 10) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT', 22) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', 11) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', 12) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', 13) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', 14) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', 15) +HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', 18) +HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT', 23) +HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = hsa_executable_symbol_info_t.define('HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', 16) + +# hsa_status_t hsa_executable_symbol_get_info(hsa_executable_symbol_t executable_symbol, hsa_executable_symbol_info_t attribute, void *value) +try: (hsa_executable_symbol_get_info:=dll.hsa_executable_symbol_get_info).restype, hsa_executable_symbol_get_info.argtypes = hsa_status_t, [hsa_executable_symbol_t, hsa_executable_symbol_info_t, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_iterate_symbols(hsa_executable_t executable, hsa_status_t (*callback)(hsa_executable_t, hsa_executable_symbol_t, void *), void *data) +try: (hsa_executable_iterate_symbols:=dll.hsa_executable_iterate_symbols).restype, hsa_executable_iterate_symbols.argtypes = hsa_status_t, [hsa_executable_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_executable_t, hsa_executable_symbol_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_iterate_agent_symbols(hsa_executable_t executable, hsa_agent_t agent, hsa_status_t (*callback)(hsa_executable_t, hsa_agent_t, hsa_executable_symbol_t, void *), void *data) +try: (hsa_executable_iterate_agent_symbols:=dll.hsa_executable_iterate_agent_symbols).restype, hsa_executable_iterate_agent_symbols.argtypes = hsa_status_t, [hsa_executable_t, hsa_agent_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_executable_t, hsa_agent_t, hsa_executable_symbol_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_iterate_program_symbols(hsa_executable_t executable, hsa_status_t (*callback)(hsa_executable_t, hsa_executable_symbol_t, void *), void *data) +try: (hsa_executable_iterate_program_symbols:=dll.hsa_executable_iterate_program_symbols).restype, hsa_executable_iterate_program_symbols.argtypes = hsa_status_t, [hsa_executable_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_executable_t, hsa_executable_symbol_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +class struct_hsa_code_object_s(Struct): pass struct_hsa_code_object_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_code_object_t = struct_hsa_code_object_s -class struct_hsa_callback_data_s(Structure): - pass - -struct_hsa_callback_data_s._pack_ = 1 # source:False +class struct_hsa_callback_data_s(Struct): pass struct_hsa_callback_data_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_callback_data_t = struct_hsa_callback_data_s -try: - hsa_code_object_serialize = _libraries['libhsa-runtime64.so'].hsa_code_object_serialize - hsa_code_object_serialize.restype = hsa_status_t - hsa_code_object_serialize.argtypes = [hsa_code_object_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_uint64, struct_hsa_callback_data_s, ctypes.POINTER(ctypes.POINTER(None))), hsa_callback_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hsa_code_object_deserialize = _libraries['libhsa-runtime64.so'].hsa_code_object_deserialize - hsa_code_object_deserialize.restype = hsa_status_t - hsa_code_object_deserialize.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_code_object_s)] -except AttributeError: - pass -try: - hsa_code_object_destroy = _libraries['libhsa-runtime64.so'].hsa_code_object_destroy - hsa_code_object_destroy.restype = hsa_status_t - hsa_code_object_destroy.argtypes = [hsa_code_object_t] -except AttributeError: - pass +# hsa_status_t hsa_code_object_serialize(hsa_code_object_t code_object, hsa_status_t (*alloc_callback)(size_t, hsa_callback_data_t, void **), hsa_callback_data_t callback_data, const char *options, void **serialized_code_object, size_t *serialized_code_object_size) +try: (hsa_code_object_serialize:=dll.hsa_code_object_serialize).restype, hsa_code_object_serialize.argtypes = hsa_status_t, [hsa_code_object_t, ctypes.CFUNCTYPE(hsa_status_t, size_t, hsa_callback_data_t, ctypes.POINTER(ctypes.c_void_p)), hsa_callback_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_code_object_type_t' -c__EA_hsa_code_object_type_t__enumvalues = { - 0: 'HSA_CODE_OBJECT_TYPE_PROGRAM', -} -HSA_CODE_OBJECT_TYPE_PROGRAM = 0 -c__EA_hsa_code_object_type_t = ctypes.c_uint32 # enum -hsa_code_object_type_t = c__EA_hsa_code_object_type_t -hsa_code_object_type_t__enumvalues = c__EA_hsa_code_object_type_t__enumvalues +# hsa_status_t hsa_code_object_deserialize(void *serialized_code_object, size_t serialized_code_object_size, const char *options, hsa_code_object_t *code_object) +try: (hsa_code_object_deserialize:=dll.hsa_code_object_deserialize).restype, hsa_code_object_deserialize.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_code_object_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_code_object_info_t' -c__EA_hsa_code_object_info_t__enumvalues = { - 0: 'HSA_CODE_OBJECT_INFO_VERSION', - 1: 'HSA_CODE_OBJECT_INFO_TYPE', - 2: 'HSA_CODE_OBJECT_INFO_ISA', - 3: 'HSA_CODE_OBJECT_INFO_MACHINE_MODEL', - 4: 'HSA_CODE_OBJECT_INFO_PROFILE', - 5: 'HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', -} -HSA_CODE_OBJECT_INFO_VERSION = 0 -HSA_CODE_OBJECT_INFO_TYPE = 1 -HSA_CODE_OBJECT_INFO_ISA = 2 -HSA_CODE_OBJECT_INFO_MACHINE_MODEL = 3 -HSA_CODE_OBJECT_INFO_PROFILE = 4 -HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 5 -c__EA_hsa_code_object_info_t = ctypes.c_uint32 # enum -hsa_code_object_info_t = c__EA_hsa_code_object_info_t -hsa_code_object_info_t__enumvalues = c__EA_hsa_code_object_info_t__enumvalues -try: - hsa_code_object_get_info = _libraries['libhsa-runtime64.so'].hsa_code_object_get_info - hsa_code_object_get_info.restype = hsa_status_t - hsa_code_object_get_info.argtypes = [hsa_code_object_t, hsa_code_object_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_executable_load_code_object = _libraries['libhsa-runtime64.so'].hsa_executable_load_code_object - hsa_executable_load_code_object.restype = hsa_status_t - hsa_executable_load_code_object.argtypes = [hsa_executable_t, hsa_agent_t, hsa_code_object_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_hsa_code_symbol_s(Structure): - pass +# hsa_status_t hsa_code_object_destroy(hsa_code_object_t code_object) +try: (hsa_code_object_destroy:=dll.hsa_code_object_destroy).restype, hsa_code_object_destroy.argtypes = hsa_status_t, [hsa_code_object_t] +except AttributeError: pass -struct_hsa_code_symbol_s._pack_ = 1 # source:False +hsa_code_object_type_t = CEnum(ctypes.c_uint32) +HSA_CODE_OBJECT_TYPE_PROGRAM = hsa_code_object_type_t.define('HSA_CODE_OBJECT_TYPE_PROGRAM', 0) + +hsa_code_object_info_t = CEnum(ctypes.c_uint32) +HSA_CODE_OBJECT_INFO_VERSION = hsa_code_object_info_t.define('HSA_CODE_OBJECT_INFO_VERSION', 0) +HSA_CODE_OBJECT_INFO_TYPE = hsa_code_object_info_t.define('HSA_CODE_OBJECT_INFO_TYPE', 1) +HSA_CODE_OBJECT_INFO_ISA = hsa_code_object_info_t.define('HSA_CODE_OBJECT_INFO_ISA', 2) +HSA_CODE_OBJECT_INFO_MACHINE_MODEL = hsa_code_object_info_t.define('HSA_CODE_OBJECT_INFO_MACHINE_MODEL', 3) +HSA_CODE_OBJECT_INFO_PROFILE = hsa_code_object_info_t.define('HSA_CODE_OBJECT_INFO_PROFILE', 4) +HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE = hsa_code_object_info_t.define('HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', 5) + +# hsa_status_t hsa_code_object_get_info(hsa_code_object_t code_object, hsa_code_object_info_t attribute, void *value) +try: (hsa_code_object_get_info:=dll.hsa_code_object_get_info).restype, hsa_code_object_get_info.argtypes = hsa_status_t, [hsa_code_object_t, hsa_code_object_info_t, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_executable_load_code_object(hsa_executable_t executable, hsa_agent_t agent, hsa_code_object_t code_object, const char *options) +try: (hsa_executable_load_code_object:=dll.hsa_executable_load_code_object).restype, hsa_executable_load_code_object.argtypes = hsa_status_t, [hsa_executable_t, hsa_agent_t, hsa_code_object_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class struct_hsa_code_symbol_s(Struct): pass struct_hsa_code_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_code_symbol_t = struct_hsa_code_symbol_s -try: - hsa_code_object_get_symbol = _libraries['libhsa-runtime64.so'].hsa_code_object_get_symbol - hsa_code_object_get_symbol.restype = hsa_status_t - hsa_code_object_get_symbol.argtypes = [hsa_code_object_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_code_symbol_s)] -except AttributeError: - pass -try: - hsa_code_object_get_symbol_from_name = _libraries['libhsa-runtime64.so'].hsa_code_object_get_symbol_from_name - hsa_code_object_get_symbol_from_name.restype = hsa_status_t - hsa_code_object_get_symbol_from_name.argtypes = [hsa_code_object_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_code_symbol_s)] -except AttributeError: - pass +# hsa_status_t hsa_code_object_get_symbol(hsa_code_object_t code_object, const char *symbol_name, hsa_code_symbol_t *symbol) +try: (hsa_code_object_get_symbol:=dll.hsa_code_object_get_symbol).restype, hsa_code_object_get_symbol.argtypes = hsa_status_t, [hsa_code_object_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_code_symbol_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_code_symbol_info_t' -c__EA_hsa_code_symbol_info_t__enumvalues = { - 0: 'HSA_CODE_SYMBOL_INFO_TYPE', - 1: 'HSA_CODE_SYMBOL_INFO_NAME_LENGTH', - 2: 'HSA_CODE_SYMBOL_INFO_NAME', - 3: 'HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 4: 'HSA_CODE_SYMBOL_INFO_MODULE_NAME', - 5: 'HSA_CODE_SYMBOL_INFO_LINKAGE', - 17: 'HSA_CODE_SYMBOL_INFO_IS_DEFINITION', - 6: 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 7: 'HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT', - 8: 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 9: 'HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE', - 10: 'HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST', - 11: 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 12: 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 13: 'HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 14: 'HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 15: 'HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 18: 'HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 16: 'HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', - 19: 'HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE', -} -HSA_CODE_SYMBOL_INFO_TYPE = 0 -HSA_CODE_SYMBOL_INFO_NAME_LENGTH = 1 -HSA_CODE_SYMBOL_INFO_NAME = 2 -HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH = 3 -HSA_CODE_SYMBOL_INFO_MODULE_NAME = 4 -HSA_CODE_SYMBOL_INFO_LINKAGE = 5 -HSA_CODE_SYMBOL_INFO_IS_DEFINITION = 17 -HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION = 6 -HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT = 7 -HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT = 8 -HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE = 9 -HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST = 10 -HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = 11 -HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = 12 -HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = 13 -HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = 14 -HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = 15 -HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION = 18 -HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = 16 -HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE = 19 -c__EA_hsa_code_symbol_info_t = ctypes.c_uint32 # enum -hsa_code_symbol_info_t = c__EA_hsa_code_symbol_info_t -hsa_code_symbol_info_t__enumvalues = c__EA_hsa_code_symbol_info_t__enumvalues -try: - hsa_code_symbol_get_info = _libraries['libhsa-runtime64.so'].hsa_code_symbol_get_info - hsa_code_symbol_get_info.restype = hsa_status_t - hsa_code_symbol_get_info.argtypes = [hsa_code_symbol_t, hsa_code_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_code_object_iterate_symbols = _libraries['libhsa-runtime64.so'].hsa_code_object_iterate_symbols - hsa_code_object_iterate_symbols.restype = hsa_status_t - hsa_code_object_iterate_symbols.argtypes = [hsa_code_object_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_code_object_s, struct_hsa_code_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_code_object_get_symbol_from_name(hsa_code_object_t code_object, const char *module_name, const char *symbol_name, hsa_code_symbol_t *symbol) +try: (hsa_code_object_get_symbol_from_name:=dll.hsa_code_object_get_symbol_from_name).restype, hsa_code_object_get_symbol_from_name.argtypes = hsa_status_t, [hsa_code_object_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_code_symbol_t)] +except AttributeError: pass -# values for enumeration 'c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED' -c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED__enumvalues = { - 12288: 'HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', - 12289: 'HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED', - 12290: 'HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED', - 12291: 'HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED', -} -HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED = 12288 -HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED = 12289 -HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED = 12290 -HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED = 12291 -c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED = ctypes.c_uint32 # enum +hsa_code_symbol_info_t = CEnum(ctypes.c_uint32) +HSA_CODE_SYMBOL_INFO_TYPE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_TYPE', 0) +HSA_CODE_SYMBOL_INFO_NAME_LENGTH = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_NAME_LENGTH', 1) +HSA_CODE_SYMBOL_INFO_NAME = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_NAME', 2) +HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH', 3) +HSA_CODE_SYMBOL_INFO_MODULE_NAME = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_MODULE_NAME', 4) +HSA_CODE_SYMBOL_INFO_LINKAGE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_LINKAGE', 5) +HSA_CODE_SYMBOL_INFO_IS_DEFINITION = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_IS_DEFINITION', 17) +HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION', 6) +HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT', 7) +HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT', 8) +HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE', 9) +HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST', 10) +HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', 11) +HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', 12) +HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', 13) +HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', 14) +HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', 15) +HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', 18) +HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', 16) +HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE = hsa_code_symbol_info_t.define('HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE', 19) -# values for enumeration 'c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS' -c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS__enumvalues = { - 12288: 'HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', - 12289: 'HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS', - 12290: 'HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS', - 12291: 'HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS', - 12292: 'HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS', - 12293: 'HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS', - 12294: 'HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS', - 12295: 'HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS', - 12296: 'HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS', - 12297: 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES', - 12298: 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES', - 12299: 'HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS', - 12300: 'HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT', -} -HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS = 12288 -HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS = 12289 -HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS = 12290 -HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS = 12291 -HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS = 12292 -HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS = 12293 -HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS = 12294 -HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS = 12295 -HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS = 12296 -HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES = 12297 -HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES = 12298 -HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS = 12299 -HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT = 12300 -c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS = ctypes.c_uint32 # enum -class struct_hsa_ext_image_s(Structure): - pass +# hsa_status_t hsa_code_symbol_get_info(hsa_code_symbol_t code_symbol, hsa_code_symbol_info_t attribute, void *value) +try: (hsa_code_symbol_get_info:=dll.hsa_code_symbol_get_info).restype, hsa_code_symbol_get_info.argtypes = hsa_status_t, [hsa_code_symbol_t, hsa_code_symbol_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_ext_image_s._pack_ = 1 # source:False -struct_hsa_ext_image_s._fields_ = [ - ('handle', ctypes.c_uint64), -] +# hsa_status_t hsa_code_object_iterate_symbols(hsa_code_object_t code_object, hsa_status_t (*callback)(hsa_code_object_t, hsa_code_symbol_t, void *), void *data) +try: (hsa_code_object_iterate_symbols:=dll.hsa_code_object_iterate_symbols).restype, hsa_code_object_iterate_symbols.argtypes = hsa_status_t, [hsa_code_object_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_code_object_t, hsa_code_symbol_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass -hsa_ext_image_t = struct_hsa_ext_image_s - -# values for enumeration 'c__EA_hsa_ext_image_geometry_t' -c__EA_hsa_ext_image_geometry_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_GEOMETRY_1D', - 1: 'HSA_EXT_IMAGE_GEOMETRY_2D', - 2: 'HSA_EXT_IMAGE_GEOMETRY_3D', - 3: 'HSA_EXT_IMAGE_GEOMETRY_1DA', - 4: 'HSA_EXT_IMAGE_GEOMETRY_2DA', - 5: 'HSA_EXT_IMAGE_GEOMETRY_1DB', - 6: 'HSA_EXT_IMAGE_GEOMETRY_2DDEPTH', - 7: 'HSA_EXT_IMAGE_GEOMETRY_2DADEPTH', -} -HSA_EXT_IMAGE_GEOMETRY_1D = 0 -HSA_EXT_IMAGE_GEOMETRY_2D = 1 -HSA_EXT_IMAGE_GEOMETRY_3D = 2 -HSA_EXT_IMAGE_GEOMETRY_1DA = 3 -HSA_EXT_IMAGE_GEOMETRY_2DA = 4 -HSA_EXT_IMAGE_GEOMETRY_1DB = 5 -HSA_EXT_IMAGE_GEOMETRY_2DDEPTH = 6 -HSA_EXT_IMAGE_GEOMETRY_2DADEPTH = 7 -c__EA_hsa_ext_image_geometry_t = ctypes.c_uint32 # enum -hsa_ext_image_geometry_t = c__EA_hsa_ext_image_geometry_t -hsa_ext_image_geometry_t__enumvalues = c__EA_hsa_ext_image_geometry_t__enumvalues - -# values for enumeration 'c__EA_hsa_ext_image_channel_type_t' -c__EA_hsa_ext_image_channel_type_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8', - 1: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16', - 2: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8', - 3: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16', - 4: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24', - 5: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555', - 6: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565', - 7: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010', - 8: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8', - 9: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16', - 10: 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32', - 11: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8', - 12: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16', - 13: 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32', - 14: 'HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT', - 15: 'HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT', -} -HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8 = 0 -HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16 = 1 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8 = 2 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16 = 3 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24 = 4 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555 = 5 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565 = 6 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010 = 7 -HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = 8 -HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = 9 -HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = 10 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = 11 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = 12 -HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = 13 -HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT = 14 -HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT = 15 -c__EA_hsa_ext_image_channel_type_t = ctypes.c_uint32 # enum -hsa_ext_image_channel_type_t = c__EA_hsa_ext_image_channel_type_t -hsa_ext_image_channel_type_t__enumvalues = c__EA_hsa_ext_image_channel_type_t__enumvalues -hsa_ext_image_channel_type32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_ext_image_channel_order_t' -c__EA_hsa_ext_image_channel_order_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_CHANNEL_ORDER_A', - 1: 'HSA_EXT_IMAGE_CHANNEL_ORDER_R', - 2: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RX', - 3: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RG', - 4: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGX', - 5: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RA', - 6: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGB', - 7: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX', - 8: 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA', - 9: 'HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA', - 10: 'HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB', - 11: 'HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR', - 12: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB', - 13: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX', - 14: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA', - 15: 'HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA', - 16: 'HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY', - 17: 'HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE', - 18: 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH', - 19: 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL', -} -HSA_EXT_IMAGE_CHANNEL_ORDER_A = 0 -HSA_EXT_IMAGE_CHANNEL_ORDER_R = 1 -HSA_EXT_IMAGE_CHANNEL_ORDER_RX = 2 -HSA_EXT_IMAGE_CHANNEL_ORDER_RG = 3 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGX = 4 -HSA_EXT_IMAGE_CHANNEL_ORDER_RA = 5 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGB = 6 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX = 7 -HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA = 8 -HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA = 9 -HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB = 10 -HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR = 11 -HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB = 12 -HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX = 13 -HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA = 14 -HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA = 15 -HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY = 16 -HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE = 17 -HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH = 18 -HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = 19 -c__EA_hsa_ext_image_channel_order_t = ctypes.c_uint32 # enum -hsa_ext_image_channel_order_t = c__EA_hsa_ext_image_channel_order_t -hsa_ext_image_channel_order_t__enumvalues = c__EA_hsa_ext_image_channel_order_t__enumvalues -hsa_ext_image_channel_order32_t = ctypes.c_uint32 -class struct_hsa_ext_image_format_s(Structure): - pass - -struct_hsa_ext_image_format_s._pack_ = 1 # source:False -struct_hsa_ext_image_format_s._fields_ = [ - ('channel_type', ctypes.c_uint32), - ('channel_order', ctypes.c_uint32), -] - -hsa_ext_image_format_t = struct_hsa_ext_image_format_s -class struct_hsa_ext_image_descriptor_s(Structure): - pass - -struct_hsa_ext_image_descriptor_s._pack_ = 1 # source:False -struct_hsa_ext_image_descriptor_s._fields_ = [ - ('geometry', hsa_ext_image_geometry_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('width', ctypes.c_uint64), - ('height', ctypes.c_uint64), - ('depth', ctypes.c_uint64), - ('array_size', ctypes.c_uint64), - ('format', hsa_ext_image_format_t), -] - -hsa_ext_image_descriptor_t = struct_hsa_ext_image_descriptor_s - -# values for enumeration 'c__EA_hsa_ext_image_capability_t' -c__EA_hsa_ext_image_capability_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED', - 1: 'HSA_EXT_IMAGE_CAPABILITY_READ_ONLY', - 2: 'HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY', - 4: 'HSA_EXT_IMAGE_CAPABILITY_READ_WRITE', - 8: 'HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE', - 16: 'HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT', -} -HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED = 0 -HSA_EXT_IMAGE_CAPABILITY_READ_ONLY = 1 -HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY = 2 -HSA_EXT_IMAGE_CAPABILITY_READ_WRITE = 4 -HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE = 8 -HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT = 16 -c__EA_hsa_ext_image_capability_t = ctypes.c_uint32 # enum -hsa_ext_image_capability_t = c__EA_hsa_ext_image_capability_t -hsa_ext_image_capability_t__enumvalues = c__EA_hsa_ext_image_capability_t__enumvalues - -# values for enumeration 'c__EA_hsa_ext_image_data_layout_t' -c__EA_hsa_ext_image_data_layout_t__enumvalues = { - 0: 'HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE', - 1: 'HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR', -} -HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE = 0 -HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR = 1 -c__EA_hsa_ext_image_data_layout_t = ctypes.c_uint32 # enum -hsa_ext_image_data_layout_t = c__EA_hsa_ext_image_data_layout_t -hsa_ext_image_data_layout_t__enumvalues = c__EA_hsa_ext_image_data_layout_t__enumvalues -try: - hsa_ext_image_get_capability = _libraries['libhsa-runtime64.so'].hsa_ext_image_get_capability - hsa_ext_image_get_capability.restype = hsa_status_t - hsa_ext_image_get_capability.argtypes = [hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hsa_ext_image_get_capability_with_layout = _libraries['libhsa-runtime64.so'].hsa_ext_image_get_capability_with_layout - hsa_ext_image_get_capability_with_layout.restype = hsa_status_t - hsa_ext_image_get_capability_with_layout.argtypes = [hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), hsa_ext_image_data_layout_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -class struct_hsa_ext_image_data_info_s(Structure): - pass - -struct_hsa_ext_image_data_info_s._pack_ = 1 # source:False -struct_hsa_ext_image_data_info_s._fields_ = [ - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), -] - -hsa_ext_image_data_info_t = struct_hsa_ext_image_data_info_s -try: - hsa_ext_image_data_get_info = _libraries['libhsa-runtime64.so'].hsa_ext_image_data_get_info - hsa_ext_image_data_get_info.restype = hsa_status_t - hsa_ext_image_data_get_info.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s)] -except AttributeError: - pass -try: - hsa_ext_image_data_get_info_with_layout = _libraries['libhsa-runtime64.so'].hsa_ext_image_data_get_info_with_layout - hsa_ext_image_data_get_info_with_layout.restype = hsa_status_t - hsa_ext_image_data_get_info_with_layout.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s)] -except AttributeError: - pass -try: - hsa_ext_image_create = _libraries['libhsa-runtime64.so'].hsa_ext_image_create - hsa_ext_image_create.restype = hsa_status_t - hsa_ext_image_create.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s)] -except AttributeError: - pass -try: - hsa_ext_image_create_with_layout = _libraries['libhsa-runtime64.so'].hsa_ext_image_create_with_layout - hsa_ext_image_create_with_layout.restype = hsa_status_t - hsa_ext_image_create_with_layout.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(struct_hsa_ext_image_s)] -except AttributeError: - pass -try: - hsa_ext_image_destroy = _libraries['libhsa-runtime64.so'].hsa_ext_image_destroy - hsa_ext_image_destroy.restype = hsa_status_t - hsa_ext_image_destroy.argtypes = [hsa_agent_t, hsa_ext_image_t] -except AttributeError: - pass -try: - hsa_ext_image_copy = _libraries['libhsa-runtime64.so'].hsa_ext_image_copy - hsa_ext_image_copy.restype = hsa_status_t - hsa_ext_image_copy.argtypes = [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(struct_hsa_dim3_s), hsa_ext_image_t, ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s)] -except AttributeError: - pass -class struct_hsa_ext_image_region_s(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('offset', hsa_dim3_t), - ('range', hsa_dim3_t), - ] - -hsa_ext_image_region_t = struct_hsa_ext_image_region_s -try: - hsa_ext_image_import = _libraries['libhsa-runtime64.so'].hsa_ext_image_import - hsa_ext_image_import.restype = hsa_status_t - hsa_ext_image_import.argtypes = [hsa_agent_t, ctypes.POINTER(None), size_t, size_t, hsa_ext_image_t, ctypes.POINTER(struct_hsa_ext_image_region_s)] -except AttributeError: - pass -try: - hsa_ext_image_export = _libraries['libhsa-runtime64.so'].hsa_ext_image_export - hsa_ext_image_export.restype = hsa_status_t - hsa_ext_image_export.argtypes = [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(None), size_t, size_t, ctypes.POINTER(struct_hsa_ext_image_region_s)] -except AttributeError: - pass -try: - hsa_ext_image_clear = _libraries['libhsa-runtime64.so'].hsa_ext_image_clear - hsa_ext_image_clear.restype = hsa_status_t - hsa_ext_image_clear.argtypes = [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(None), ctypes.POINTER(struct_hsa_ext_image_region_s)] -except AttributeError: - pass -class struct_hsa_ext_sampler_s(Structure): - pass - -struct_hsa_ext_sampler_s._pack_ = 1 # source:False -struct_hsa_ext_sampler_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -hsa_ext_sampler_t = struct_hsa_ext_sampler_s - -# values for enumeration 'c__EA_hsa_ext_sampler_addressing_mode_t' -c__EA_hsa_ext_sampler_addressing_mode_t__enumvalues = { - 0: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED', - 1: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE', - 2: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER', - 3: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT', - 4: 'HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT', -} -HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED = 0 -HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE = 1 -HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER = 2 -HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT = 3 -HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT = 4 -c__EA_hsa_ext_sampler_addressing_mode_t = ctypes.c_uint32 # enum -hsa_ext_sampler_addressing_mode_t = c__EA_hsa_ext_sampler_addressing_mode_t -hsa_ext_sampler_addressing_mode_t__enumvalues = c__EA_hsa_ext_sampler_addressing_mode_t__enumvalues -hsa_ext_sampler_addressing_mode32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_ext_sampler_coordinate_mode_t' -c__EA_hsa_ext_sampler_coordinate_mode_t__enumvalues = { - 0: 'HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED', - 1: 'HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED', -} -HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED = 0 -HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED = 1 -c__EA_hsa_ext_sampler_coordinate_mode_t = ctypes.c_uint32 # enum -hsa_ext_sampler_coordinate_mode_t = c__EA_hsa_ext_sampler_coordinate_mode_t -hsa_ext_sampler_coordinate_mode_t__enumvalues = c__EA_hsa_ext_sampler_coordinate_mode_t__enumvalues -hsa_ext_sampler_coordinate_mode32_t = ctypes.c_uint32 - -# values for enumeration 'c__EA_hsa_ext_sampler_filter_mode_t' -c__EA_hsa_ext_sampler_filter_mode_t__enumvalues = { - 0: 'HSA_EXT_SAMPLER_FILTER_MODE_NEAREST', - 1: 'HSA_EXT_SAMPLER_FILTER_MODE_LINEAR', -} -HSA_EXT_SAMPLER_FILTER_MODE_NEAREST = 0 -HSA_EXT_SAMPLER_FILTER_MODE_LINEAR = 1 -c__EA_hsa_ext_sampler_filter_mode_t = ctypes.c_uint32 # enum -hsa_ext_sampler_filter_mode_t = c__EA_hsa_ext_sampler_filter_mode_t -hsa_ext_sampler_filter_mode_t__enumvalues = c__EA_hsa_ext_sampler_filter_mode_t__enumvalues -hsa_ext_sampler_filter_mode32_t = ctypes.c_uint32 -class struct_hsa_ext_sampler_descriptor_s(Structure): - pass - -struct_hsa_ext_sampler_descriptor_s._pack_ = 1 # source:False -struct_hsa_ext_sampler_descriptor_s._fields_ = [ - ('coordinate_mode', ctypes.c_uint32), - ('filter_mode', ctypes.c_uint32), - ('address_mode', ctypes.c_uint32), -] - -hsa_ext_sampler_descriptor_t = struct_hsa_ext_sampler_descriptor_s -try: - hsa_ext_sampler_create = _libraries['libhsa-runtime64.so'].hsa_ext_sampler_create - hsa_ext_sampler_create.restype = hsa_status_t - hsa_ext_sampler_create.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_sampler_descriptor_s), ctypes.POINTER(struct_hsa_ext_sampler_s)] -except AttributeError: - pass -try: - hsa_ext_sampler_destroy = _libraries['libhsa-runtime64.so'].hsa_ext_sampler_destroy - hsa_ext_sampler_destroy.restype = hsa_status_t - hsa_ext_sampler_destroy.argtypes = [hsa_agent_t, hsa_ext_sampler_t] -except AttributeError: - pass -class struct_hsa_ext_images_1_00_pfn_s(Structure): - pass - -struct_hsa_ext_images_1_00_pfn_s._pack_ = 1 # source:False -struct_hsa_ext_images_1_00_pfn_s._fields_ = [ - ('hsa_ext_image_get_capability', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, c__EA_hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), ctypes.POINTER(ctypes.c_uint32))), - ('hsa_ext_image_data_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s))), - ('hsa_ext_image_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s))), - ('hsa_ext_image_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s)), - ('hsa_ext_image_copy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s))), - ('hsa_ext_image_import', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_export', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_clear', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_sampler_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_sampler_descriptor_s), ctypes.POINTER(struct_hsa_ext_sampler_s))), - ('hsa_ext_sampler_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_sampler_s)), -] - -hsa_ext_images_1_00_pfn_t = struct_hsa_ext_images_1_00_pfn_s -class struct_hsa_ext_images_1_pfn_s(Structure): - pass - -struct_hsa_ext_images_1_pfn_s._pack_ = 1 # source:False -struct_hsa_ext_images_1_pfn_s._fields_ = [ - ('hsa_ext_image_get_capability', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, c__EA_hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), ctypes.POINTER(ctypes.c_uint32))), - ('hsa_ext_image_data_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_data_info_s))), - ('hsa_ext_image_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), c__EA_hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s))), - ('hsa_ext_image_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s)), - ('hsa_ext_image_copy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s))), - ('hsa_ext_image_import', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, struct_hsa_ext_image_s, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_export', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_image_clear', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_image_s, ctypes.POINTER(None), ctypes.POINTER(struct_hsa_ext_image_region_s))), - ('hsa_ext_sampler_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_sampler_descriptor_s), ctypes.POINTER(struct_hsa_ext_sampler_s))), - ('hsa_ext_sampler_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_hsa_ext_sampler_s)), - ('hsa_ext_image_get_capability_with_layout', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, c__EA_hsa_ext_image_geometry_t, ctypes.POINTER(struct_hsa_ext_image_format_s), c__EA_hsa_ext_image_data_layout_t, ctypes.POINTER(ctypes.c_uint32))), - ('hsa_ext_image_data_get_info_with_layout', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), c__EA_hsa_access_permission_t, c__EA_hsa_ext_image_data_layout_t, ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_data_info_s))), - ('hsa_ext_image_create_with_layout', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(None), c__EA_hsa_access_permission_t, c__EA_hsa_ext_image_data_layout_t, ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(struct_hsa_ext_image_s))), -] - -hsa_ext_images_1_pfn_t = struct_hsa_ext_images_1_pfn_s -try: - hsa_flag_isset64 = _libraries['FIXME_STUB'].hsa_flag_isset64 - hsa_flag_isset64.restype = ctypes.c_bool - hsa_flag_isset64.argtypes = [ctypes.POINTER(ctypes.c_ubyte), uint32_t] -except AttributeError: - pass hsa_signal_condition32_t = ctypes.c_uint32 +hsa_amd_packet_type_t = CEnum(ctypes.c_uint32) +HSA_AMD_PACKET_TYPE_BARRIER_VALUE = hsa_amd_packet_type_t.define('HSA_AMD_PACKET_TYPE_BARRIER_VALUE', 2) -# values for enumeration 'c__EA_hsa_amd_packet_type_t' -c__EA_hsa_amd_packet_type_t__enumvalues = { - 2: 'HSA_AMD_PACKET_TYPE_BARRIER_VALUE', -} -HSA_AMD_PACKET_TYPE_BARRIER_VALUE = 2 -c__EA_hsa_amd_packet_type_t = ctypes.c_uint32 # enum -hsa_amd_packet_type_t = c__EA_hsa_amd_packet_type_t -hsa_amd_packet_type_t__enumvalues = c__EA_hsa_amd_packet_type_t__enumvalues hsa_amd_packet_type8_t = ctypes.c_ubyte -class struct_hsa_amd_packet_header_s(Structure): - pass - -struct_hsa_amd_packet_header_s._pack_ = 1 # source:False +class struct_hsa_amd_packet_header_s(Struct): pass +uint8_t = ctypes.c_ubyte struct_hsa_amd_packet_header_s._fields_ = [ - ('header', ctypes.c_uint16), - ('AmdFormat', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), + ('header', uint16_t), + ('AmdFormat', hsa_amd_packet_type8_t), + ('reserved', uint8_t), ] - hsa_amd_vendor_packet_header_t = struct_hsa_amd_packet_header_s -class struct_hsa_amd_barrier_value_packet_s(Structure): - pass - -struct_hsa_amd_barrier_value_packet_s._pack_ = 1 # source:False +class struct_hsa_amd_barrier_value_packet_s(Struct): pass struct_hsa_amd_barrier_value_packet_s._fields_ = [ - ('header', hsa_amd_vendor_packet_header_t), - ('reserved0', ctypes.c_uint32), - ('signal', hsa_signal_t), - ('value', ctypes.c_int64), - ('mask', ctypes.c_int64), - ('cond', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('reserved2', ctypes.c_uint64), - ('reserved3', ctypes.c_uint64), - ('completion_signal', hsa_signal_t), + ('header', hsa_amd_vendor_packet_header_t), + ('reserved0', uint32_t), + ('signal', hsa_signal_t), + ('value', hsa_signal_value_t), + ('mask', hsa_signal_value_t), + ('cond', hsa_signal_condition32_t), + ('reserved1', uint32_t), + ('reserved2', uint64_t), + ('reserved3', uint64_t), + ('completion_signal', hsa_signal_t), ] - hsa_amd_barrier_value_packet_t = struct_hsa_amd_barrier_value_packet_s +_anonenum0 = CEnum(ctypes.c_uint32) +HSA_STATUS_ERROR_INVALID_MEMORY_POOL = _anonenum0.define('HSA_STATUS_ERROR_INVALID_MEMORY_POOL', 40) +HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION = _anonenum0.define('HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION', 41) +HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION = _anonenum0.define('HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION', 42) +HSA_STATUS_ERROR_MEMORY_FAULT = _anonenum0.define('HSA_STATUS_ERROR_MEMORY_FAULT', 43) +HSA_STATUS_CU_MASK_REDUCED = _anonenum0.define('HSA_STATUS_CU_MASK_REDUCED', 44) +HSA_STATUS_ERROR_OUT_OF_REGISTERS = _anonenum0.define('HSA_STATUS_ERROR_OUT_OF_REGISTERS', 45) +HSA_STATUS_ERROR_RESOURCE_BUSY = _anonenum0.define('HSA_STATUS_ERROR_RESOURCE_BUSY', 46) -# values for enumeration 'c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL' -c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL__enumvalues = { - 40: 'HSA_STATUS_ERROR_INVALID_MEMORY_POOL', - 41: 'HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION', - 42: 'HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION', - 43: 'HSA_STATUS_ERROR_MEMORY_FAULT', - 44: 'HSA_STATUS_CU_MASK_REDUCED', - 45: 'HSA_STATUS_ERROR_OUT_OF_REGISTERS', - 46: 'HSA_STATUS_ERROR_RESOURCE_BUSY', -} -HSA_STATUS_ERROR_INVALID_MEMORY_POOL = 40 -HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION = 41 -HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION = 42 -HSA_STATUS_ERROR_MEMORY_FAULT = 43 -HSA_STATUS_CU_MASK_REDUCED = 44 -HSA_STATUS_ERROR_OUT_OF_REGISTERS = 45 -HSA_STATUS_ERROR_RESOURCE_BUSY = 46 -c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL = ctypes.c_uint32 # enum +hsa_amd_iommu_version_t = CEnum(ctypes.c_uint32) +HSA_IOMMU_SUPPORT_NONE = hsa_amd_iommu_version_t.define('HSA_IOMMU_SUPPORT_NONE', 0) +HSA_IOMMU_SUPPORT_V2 = hsa_amd_iommu_version_t.define('HSA_IOMMU_SUPPORT_V2', 1) -# values for enumeration 'c__EA_hsa_amd_iommu_version_t' -c__EA_hsa_amd_iommu_version_t__enumvalues = { - 0: 'HSA_IOMMU_SUPPORT_NONE', - 1: 'HSA_IOMMU_SUPPORT_V2', -} -HSA_IOMMU_SUPPORT_NONE = 0 -HSA_IOMMU_SUPPORT_V2 = 1 -c__EA_hsa_amd_iommu_version_t = ctypes.c_uint32 # enum -hsa_amd_iommu_version_t = c__EA_hsa_amd_iommu_version_t -hsa_amd_iommu_version_t__enumvalues = c__EA_hsa_amd_iommu_version_t__enumvalues +enum_hsa_amd_agent_info_s = CEnum(ctypes.c_uint32) +HSA_AMD_AGENT_INFO_CHIP_ID = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_CHIP_ID', 40960) +HSA_AMD_AGENT_INFO_CACHELINE_SIZE = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_CACHELINE_SIZE', 40961) +HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT', 40962) +HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY', 40963) +HSA_AMD_AGENT_INFO_DRIVER_NODE_ID = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_DRIVER_NODE_ID', 40964) +HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS', 40965) +HSA_AMD_AGENT_INFO_BDFID = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_BDFID', 40966) +HSA_AMD_AGENT_INFO_MEMORY_WIDTH = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MEMORY_WIDTH', 40967) +HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY', 40968) +HSA_AMD_AGENT_INFO_PRODUCT_NAME = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_PRODUCT_NAME', 40969) +HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU', 40970) +HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU', 40971) +HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES', 40972) +HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE', 40973) +HSA_AMD_AGENT_INFO_HDP_FLUSH = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_HDP_FLUSH', 40974) +HSA_AMD_AGENT_INFO_DOMAIN = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_DOMAIN', 40975) +HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES', 40976) +HSA_AMD_AGENT_INFO_UUID = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_UUID', 40977) +HSA_AMD_AGENT_INFO_ASIC_REVISION = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_ASIC_REVISION', 40978) +HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS', 40979) +HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT', 40980) +HSA_AMD_AGENT_INFO_MEMORY_AVAIL = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MEMORY_AVAIL', 40981) +HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY', 40982) +HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID', 41223) +HSA_AMD_AGENT_INFO_UCODE_VERSION = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_UCODE_VERSION', 41224) +HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION', 41225) +HSA_AMD_AGENT_INFO_NUM_SDMA_ENG = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NUM_SDMA_ENG', 41226) +HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG', 41227) +HSA_AMD_AGENT_INFO_IOMMU_SUPPORT = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_IOMMU_SUPPORT', 41232) +HSA_AMD_AGENT_INFO_NUM_XCC = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NUM_XCC', 41233) +HSA_AMD_AGENT_INFO_DRIVER_UID = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_DRIVER_UID', 41234) +HSA_AMD_AGENT_INFO_NEAREST_CPU = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_NEAREST_CPU', 41235) +HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES', 41236) +HSA_AMD_AGENT_INFO_AQL_EXTENSIONS = enum_hsa_amd_agent_info_s.define('HSA_AMD_AGENT_INFO_AQL_EXTENSIONS', 41237) -# values for enumeration 'hsa_amd_agent_info_s' -hsa_amd_agent_info_s__enumvalues = { - 40960: 'HSA_AMD_AGENT_INFO_CHIP_ID', - 40961: 'HSA_AMD_AGENT_INFO_CACHELINE_SIZE', - 40962: 'HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT', - 40963: 'HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY', - 40964: 'HSA_AMD_AGENT_INFO_DRIVER_NODE_ID', - 40965: 'HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS', - 40966: 'HSA_AMD_AGENT_INFO_BDFID', - 40967: 'HSA_AMD_AGENT_INFO_MEMORY_WIDTH', - 40968: 'HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY', - 40969: 'HSA_AMD_AGENT_INFO_PRODUCT_NAME', - 40970: 'HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU', - 40971: 'HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU', - 40972: 'HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES', - 40973: 'HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE', - 40974: 'HSA_AMD_AGENT_INFO_HDP_FLUSH', - 40975: 'HSA_AMD_AGENT_INFO_DOMAIN', - 40976: 'HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES', - 40977: 'HSA_AMD_AGENT_INFO_UUID', - 40978: 'HSA_AMD_AGENT_INFO_ASIC_REVISION', - 40979: 'HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS', - 40980: 'HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT', - 40981: 'HSA_AMD_AGENT_INFO_MEMORY_AVAIL', - 40982: 'HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY', - 41223: 'HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID', - 41224: 'HSA_AMD_AGENT_INFO_UCODE_VERSION', - 41225: 'HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION', - 41226: 'HSA_AMD_AGENT_INFO_NUM_SDMA_ENG', - 41227: 'HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG', - 41232: 'HSA_AMD_AGENT_INFO_IOMMU_SUPPORT', - 41233: 'HSA_AMD_AGENT_INFO_NUM_XCC', - 41234: 'HSA_AMD_AGENT_INFO_DRIVER_UID', - 41235: 'HSA_AMD_AGENT_INFO_NEAREST_CPU', - 41236: 'HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES', - 41237: 'HSA_AMD_AGENT_INFO_AQL_EXTENSIONS', -} -HSA_AMD_AGENT_INFO_CHIP_ID = 40960 -HSA_AMD_AGENT_INFO_CACHELINE_SIZE = 40961 -HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT = 40962 -HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY = 40963 -HSA_AMD_AGENT_INFO_DRIVER_NODE_ID = 40964 -HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS = 40965 -HSA_AMD_AGENT_INFO_BDFID = 40966 -HSA_AMD_AGENT_INFO_MEMORY_WIDTH = 40967 -HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY = 40968 -HSA_AMD_AGENT_INFO_PRODUCT_NAME = 40969 -HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU = 40970 -HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU = 40971 -HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES = 40972 -HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE = 40973 -HSA_AMD_AGENT_INFO_HDP_FLUSH = 40974 -HSA_AMD_AGENT_INFO_DOMAIN = 40975 -HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES = 40976 -HSA_AMD_AGENT_INFO_UUID = 40977 -HSA_AMD_AGENT_INFO_ASIC_REVISION = 40978 -HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS = 40979 -HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT = 40980 -HSA_AMD_AGENT_INFO_MEMORY_AVAIL = 40981 -HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY = 40982 -HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID = 41223 -HSA_AMD_AGENT_INFO_UCODE_VERSION = 41224 -HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION = 41225 -HSA_AMD_AGENT_INFO_NUM_SDMA_ENG = 41226 -HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG = 41227 -HSA_AMD_AGENT_INFO_IOMMU_SUPPORT = 41232 -HSA_AMD_AGENT_INFO_NUM_XCC = 41233 -HSA_AMD_AGENT_INFO_DRIVER_UID = 41234 -HSA_AMD_AGENT_INFO_NEAREST_CPU = 41235 -HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES = 41236 -HSA_AMD_AGENT_INFO_AQL_EXTENSIONS = 41237 -hsa_amd_agent_info_s = ctypes.c_uint32 # enum -hsa_amd_agent_info_t = hsa_amd_agent_info_s -hsa_amd_agent_info_t__enumvalues = hsa_amd_agent_info_s__enumvalues +hsa_amd_agent_info_t = enum_hsa_amd_agent_info_s +enum_hsa_amd_agent_memory_properties_s = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU = enum_hsa_amd_agent_memory_properties_s.define('HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU', 1) -# values for enumeration 'hsa_amd_agent_memory_properties_s' -hsa_amd_agent_memory_properties_s__enumvalues = { - 1: 'HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU', -} -HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU = 1 -hsa_amd_agent_memory_properties_s = ctypes.c_uint32 # enum -hsa_amd_agent_memory_properties_t = hsa_amd_agent_memory_properties_s -hsa_amd_agent_memory_properties_t__enumvalues = hsa_amd_agent_memory_properties_s__enumvalues +hsa_amd_agent_memory_properties_t = enum_hsa_amd_agent_memory_properties_s +enum_hsa_amd_sdma_engine_id = CEnum(ctypes.c_uint32) +HSA_AMD_SDMA_ENGINE_0 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_0', 1) +HSA_AMD_SDMA_ENGINE_1 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_1', 2) +HSA_AMD_SDMA_ENGINE_2 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_2', 4) +HSA_AMD_SDMA_ENGINE_3 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_3', 8) +HSA_AMD_SDMA_ENGINE_4 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_4', 16) +HSA_AMD_SDMA_ENGINE_5 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_5', 32) +HSA_AMD_SDMA_ENGINE_6 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_6', 64) +HSA_AMD_SDMA_ENGINE_7 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_7', 128) +HSA_AMD_SDMA_ENGINE_8 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_8', 256) +HSA_AMD_SDMA_ENGINE_9 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_9', 512) +HSA_AMD_SDMA_ENGINE_10 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_10', 1024) +HSA_AMD_SDMA_ENGINE_11 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_11', 2048) +HSA_AMD_SDMA_ENGINE_12 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_12', 4096) +HSA_AMD_SDMA_ENGINE_13 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_13', 8192) +HSA_AMD_SDMA_ENGINE_14 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_14', 16384) +HSA_AMD_SDMA_ENGINE_15 = enum_hsa_amd_sdma_engine_id.define('HSA_AMD_SDMA_ENGINE_15', 32768) -# values for enumeration 'hsa_amd_sdma_engine_id' -hsa_amd_sdma_engine_id__enumvalues = { - 1: 'HSA_AMD_SDMA_ENGINE_0', - 2: 'HSA_AMD_SDMA_ENGINE_1', - 4: 'HSA_AMD_SDMA_ENGINE_2', - 8: 'HSA_AMD_SDMA_ENGINE_3', - 16: 'HSA_AMD_SDMA_ENGINE_4', - 32: 'HSA_AMD_SDMA_ENGINE_5', - 64: 'HSA_AMD_SDMA_ENGINE_6', - 128: 'HSA_AMD_SDMA_ENGINE_7', - 256: 'HSA_AMD_SDMA_ENGINE_8', - 512: 'HSA_AMD_SDMA_ENGINE_9', - 1024: 'HSA_AMD_SDMA_ENGINE_10', - 2048: 'HSA_AMD_SDMA_ENGINE_11', - 4096: 'HSA_AMD_SDMA_ENGINE_12', - 8192: 'HSA_AMD_SDMA_ENGINE_13', - 16384: 'HSA_AMD_SDMA_ENGINE_14', - 32768: 'HSA_AMD_SDMA_ENGINE_15', -} -HSA_AMD_SDMA_ENGINE_0 = 1 -HSA_AMD_SDMA_ENGINE_1 = 2 -HSA_AMD_SDMA_ENGINE_2 = 4 -HSA_AMD_SDMA_ENGINE_3 = 8 -HSA_AMD_SDMA_ENGINE_4 = 16 -HSA_AMD_SDMA_ENGINE_5 = 32 -HSA_AMD_SDMA_ENGINE_6 = 64 -HSA_AMD_SDMA_ENGINE_7 = 128 -HSA_AMD_SDMA_ENGINE_8 = 256 -HSA_AMD_SDMA_ENGINE_9 = 512 -HSA_AMD_SDMA_ENGINE_10 = 1024 -HSA_AMD_SDMA_ENGINE_11 = 2048 -HSA_AMD_SDMA_ENGINE_12 = 4096 -HSA_AMD_SDMA_ENGINE_13 = 8192 -HSA_AMD_SDMA_ENGINE_14 = 16384 -HSA_AMD_SDMA_ENGINE_15 = 32768 -hsa_amd_sdma_engine_id = ctypes.c_uint32 # enum -hsa_amd_sdma_engine_id_t = hsa_amd_sdma_engine_id -hsa_amd_sdma_engine_id_t__enumvalues = hsa_amd_sdma_engine_id__enumvalues -class struct_hsa_amd_hdp_flush_s(Structure): - pass - -struct_hsa_amd_hdp_flush_s._pack_ = 1 # source:False +hsa_amd_sdma_engine_id_t = enum_hsa_amd_sdma_engine_id +class struct_hsa_amd_hdp_flush_s(Struct): pass struct_hsa_amd_hdp_flush_s._fields_ = [ - ('HDP_MEM_FLUSH_CNTL', ctypes.POINTER(ctypes.c_uint32)), - ('HDP_REG_FLUSH_CNTL', ctypes.POINTER(ctypes.c_uint32)), + ('HDP_MEM_FLUSH_CNTL', ctypes.POINTER(uint32_t)), + ('HDP_REG_FLUSH_CNTL', ctypes.POINTER(uint32_t)), ] - hsa_amd_hdp_flush_t = struct_hsa_amd_hdp_flush_s +enum_hsa_amd_region_info_s = CEnum(ctypes.c_uint32) +HSA_AMD_REGION_INFO_HOST_ACCESSIBLE = enum_hsa_amd_region_info_s.define('HSA_AMD_REGION_INFO_HOST_ACCESSIBLE', 40960) +HSA_AMD_REGION_INFO_BASE = enum_hsa_amd_region_info_s.define('HSA_AMD_REGION_INFO_BASE', 40961) +HSA_AMD_REGION_INFO_BUS_WIDTH = enum_hsa_amd_region_info_s.define('HSA_AMD_REGION_INFO_BUS_WIDTH', 40962) +HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY = enum_hsa_amd_region_info_s.define('HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY', 40963) -# values for enumeration 'hsa_amd_region_info_s' -hsa_amd_region_info_s__enumvalues = { - 40960: 'HSA_AMD_REGION_INFO_HOST_ACCESSIBLE', - 40961: 'HSA_AMD_REGION_INFO_BASE', - 40962: 'HSA_AMD_REGION_INFO_BUS_WIDTH', - 40963: 'HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY', -} -HSA_AMD_REGION_INFO_HOST_ACCESSIBLE = 40960 -HSA_AMD_REGION_INFO_BASE = 40961 -HSA_AMD_REGION_INFO_BUS_WIDTH = 40962 -HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY = 40963 -hsa_amd_region_info_s = ctypes.c_uint32 # enum -hsa_amd_region_info_t = hsa_amd_region_info_s -hsa_amd_region_info_t__enumvalues = hsa_amd_region_info_s__enumvalues +hsa_amd_region_info_t = enum_hsa_amd_region_info_s +enum_hsa_amd_coherency_type_s = CEnum(ctypes.c_uint32) +HSA_AMD_COHERENCY_TYPE_COHERENT = enum_hsa_amd_coherency_type_s.define('HSA_AMD_COHERENCY_TYPE_COHERENT', 0) +HSA_AMD_COHERENCY_TYPE_NONCOHERENT = enum_hsa_amd_coherency_type_s.define('HSA_AMD_COHERENCY_TYPE_NONCOHERENT', 1) -# values for enumeration 'hsa_amd_coherency_type_s' -hsa_amd_coherency_type_s__enumvalues = { - 0: 'HSA_AMD_COHERENCY_TYPE_COHERENT', - 1: 'HSA_AMD_COHERENCY_TYPE_NONCOHERENT', -} -HSA_AMD_COHERENCY_TYPE_COHERENT = 0 -HSA_AMD_COHERENCY_TYPE_NONCOHERENT = 1 -hsa_amd_coherency_type_s = ctypes.c_uint32 # enum -hsa_amd_coherency_type_t = hsa_amd_coherency_type_s -hsa_amd_coherency_type_t__enumvalues = hsa_amd_coherency_type_s__enumvalues -try: - hsa_amd_coherency_get_type = _libraries['libhsa-runtime64.so'].hsa_amd_coherency_get_type - hsa_amd_coherency_get_type.restype = hsa_status_t - hsa_amd_coherency_get_type.argtypes = [hsa_agent_t, ctypes.POINTER(hsa_amd_coherency_type_s)] -except AttributeError: - pass -try: - hsa_amd_coherency_set_type = _libraries['libhsa-runtime64.so'].hsa_amd_coherency_set_type - hsa_amd_coherency_set_type.restype = hsa_status_t - hsa_amd_coherency_set_type.argtypes = [hsa_agent_t, hsa_amd_coherency_type_t] -except AttributeError: - pass -class struct_hsa_amd_profiling_dispatch_time_s(Structure): - pass +hsa_amd_coherency_type_t = enum_hsa_amd_coherency_type_s +# hsa_status_t hsa_amd_coherency_get_type(hsa_agent_t agent, hsa_amd_coherency_type_t *type) +try: (hsa_amd_coherency_get_type:=dll.hsa_amd_coherency_get_type).restype, hsa_amd_coherency_get_type.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_amd_coherency_type_t)] +except AttributeError: pass -struct_hsa_amd_profiling_dispatch_time_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_coherency_set_type(hsa_agent_t agent, hsa_amd_coherency_type_t type) +try: (hsa_amd_coherency_set_type:=dll.hsa_amd_coherency_set_type).restype, hsa_amd_coherency_set_type.argtypes = hsa_status_t, [hsa_agent_t, hsa_amd_coherency_type_t] +except AttributeError: pass + +class struct_hsa_amd_profiling_dispatch_time_s(Struct): pass struct_hsa_amd_profiling_dispatch_time_s._fields_ = [ - ('start', ctypes.c_uint64), - ('end', ctypes.c_uint64), + ('start', uint64_t), + ('end', uint64_t), ] - hsa_amd_profiling_dispatch_time_t = struct_hsa_amd_profiling_dispatch_time_s -class struct_hsa_amd_profiling_async_copy_time_s(Structure): - pass - -struct_hsa_amd_profiling_async_copy_time_s._pack_ = 1 # source:False +class struct_hsa_amd_profiling_async_copy_time_s(Struct): pass struct_hsa_amd_profiling_async_copy_time_s._fields_ = [ - ('start', ctypes.c_uint64), - ('end', ctypes.c_uint64), + ('start', uint64_t), + ('end', uint64_t), ] - hsa_amd_profiling_async_copy_time_t = struct_hsa_amd_profiling_async_copy_time_s -try: - hsa_amd_profiling_set_profiler_enabled = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_set_profiler_enabled - hsa_amd_profiling_set_profiler_enabled.restype = hsa_status_t - hsa_amd_profiling_set_profiler_enabled.argtypes = [ctypes.POINTER(struct_hsa_queue_s), ctypes.c_int32] -except AttributeError: - pass -try: - hsa_amd_profiling_async_copy_enable = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_async_copy_enable - hsa_amd_profiling_async_copy_enable.restype = hsa_status_t - hsa_amd_profiling_async_copy_enable.argtypes = [ctypes.c_bool] -except AttributeError: - pass -try: - hsa_amd_profiling_get_dispatch_time = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_get_dispatch_time - hsa_amd_profiling_get_dispatch_time.restype = hsa_status_t - hsa_amd_profiling_get_dispatch_time.argtypes = [hsa_agent_t, hsa_signal_t, ctypes.POINTER(struct_hsa_amd_profiling_dispatch_time_s)] -except AttributeError: - pass -try: - hsa_amd_profiling_get_async_copy_time = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_get_async_copy_time - hsa_amd_profiling_get_async_copy_time.restype = hsa_status_t - hsa_amd_profiling_get_async_copy_time.argtypes = [hsa_signal_t, ctypes.POINTER(struct_hsa_amd_profiling_async_copy_time_s)] -except AttributeError: - pass -try: - hsa_amd_profiling_convert_tick_to_system_domain = _libraries['libhsa-runtime64.so'].hsa_amd_profiling_convert_tick_to_system_domain - hsa_amd_profiling_convert_tick_to_system_domain.restype = hsa_status_t - hsa_amd_profiling_convert_tick_to_system_domain.argtypes = [hsa_agent_t, uint64_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass +# hsa_status_t hsa_amd_profiling_set_profiler_enabled(hsa_queue_t *queue, int enable) +try: (hsa_amd_profiling_set_profiler_enabled:=dll.hsa_amd_profiling_set_profiler_enabled).restype, hsa_amd_profiling_set_profiler_enabled.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t), ctypes.c_int32] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_amd_signal_attribute_t' -c__EA_hsa_amd_signal_attribute_t__enumvalues = { - 1: 'HSA_AMD_SIGNAL_AMD_GPU_ONLY', - 2: 'HSA_AMD_SIGNAL_IPC', -} -HSA_AMD_SIGNAL_AMD_GPU_ONLY = 1 -HSA_AMD_SIGNAL_IPC = 2 -c__EA_hsa_amd_signal_attribute_t = ctypes.c_uint32 # enum -hsa_amd_signal_attribute_t = c__EA_hsa_amd_signal_attribute_t -hsa_amd_signal_attribute_t__enumvalues = c__EA_hsa_amd_signal_attribute_t__enumvalues -try: - hsa_amd_signal_create = _libraries['libhsa-runtime64.so'].hsa_amd_signal_create - hsa_amd_signal_create.restype = hsa_status_t - hsa_amd_signal_create.argtypes = [hsa_signal_value_t, uint32_t, ctypes.POINTER(struct_hsa_agent_s), uint64_t, ctypes.POINTER(struct_hsa_signal_s)] -except AttributeError: - pass -try: - hsa_amd_signal_value_pointer = _libraries['libhsa-runtime64.so'].hsa_amd_signal_value_pointer - hsa_amd_signal_value_pointer.restype = hsa_status_t - hsa_amd_signal_value_pointer.argtypes = [hsa_signal_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_int64))] -except AttributeError: - pass -hsa_amd_signal_handler = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_int64, ctypes.POINTER(None)) -try: - hsa_amd_signal_async_handler = _libraries['libhsa-runtime64.so'].hsa_amd_signal_async_handler - hsa_amd_signal_async_handler.restype = hsa_status_t - hsa_amd_signal_async_handler.argtypes = [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, hsa_amd_signal_handler, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_async_function = _libraries['libhsa-runtime64.so'].hsa_amd_async_function - hsa_amd_async_function.restype = hsa_status_t - hsa_amd_async_function.argtypes = [ctypes.CFUNCTYPE(None, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_signal_wait_any = _libraries['libhsa-runtime64.so'].hsa_amd_signal_wait_any - hsa_amd_signal_wait_any.restype = uint32_t - hsa_amd_signal_wait_any.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_signal_s), ctypes.POINTER(c__EA_hsa_signal_condition_t), ctypes.POINTER(ctypes.c_int64), uint64_t, hsa_wait_state_t, ctypes.POINTER(ctypes.c_int64)] -except AttributeError: - pass -try: - hsa_amd_image_get_info_max_dim = _libraries['libhsa-runtime64.so'].hsa_amd_image_get_info_max_dim - hsa_amd_image_get_info_max_dim.restype = hsa_status_t - hsa_amd_image_get_info_max_dim.argtypes = [hsa_agent_t, hsa_agent_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_queue_cu_set_mask = _libraries['libhsa-runtime64.so'].hsa_amd_queue_cu_set_mask - hsa_amd_queue_cu_set_mask.restype = hsa_status_t - hsa_amd_queue_cu_set_mask.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - hsa_amd_queue_cu_get_mask = _libraries['libhsa-runtime64.so'].hsa_amd_queue_cu_get_mask - hsa_amd_queue_cu_get_mask.restype = hsa_status_t - hsa_amd_queue_cu_get_mask.argtypes = [ctypes.POINTER(struct_hsa_queue_s), uint32_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass +# hsa_status_t hsa_amd_profiling_async_copy_enable(bool enable) +try: (hsa_amd_profiling_async_copy_enable:=dll.hsa_amd_profiling_async_copy_enable).restype, hsa_amd_profiling_async_copy_enable.argtypes = hsa_status_t, [ctypes.c_bool] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_amd_segment_t' -c__EA_hsa_amd_segment_t__enumvalues = { - 0: 'HSA_AMD_SEGMENT_GLOBAL', - 1: 'HSA_AMD_SEGMENT_READONLY', - 2: 'HSA_AMD_SEGMENT_PRIVATE', - 3: 'HSA_AMD_SEGMENT_GROUP', -} -HSA_AMD_SEGMENT_GLOBAL = 0 -HSA_AMD_SEGMENT_READONLY = 1 -HSA_AMD_SEGMENT_PRIVATE = 2 -HSA_AMD_SEGMENT_GROUP = 3 -c__EA_hsa_amd_segment_t = ctypes.c_uint32 # enum -hsa_amd_segment_t = c__EA_hsa_amd_segment_t -hsa_amd_segment_t__enumvalues = c__EA_hsa_amd_segment_t__enumvalues -class struct_hsa_amd_memory_pool_s(Structure): - pass +# hsa_status_t hsa_amd_profiling_get_dispatch_time(hsa_agent_t agent, hsa_signal_t signal, hsa_amd_profiling_dispatch_time_t *time) +try: (hsa_amd_profiling_get_dispatch_time:=dll.hsa_amd_profiling_get_dispatch_time).restype, hsa_amd_profiling_get_dispatch_time.argtypes = hsa_status_t, [hsa_agent_t, hsa_signal_t, ctypes.POINTER(hsa_amd_profiling_dispatch_time_t)] +except AttributeError: pass -struct_hsa_amd_memory_pool_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_profiling_get_async_copy_time(hsa_signal_t signal, hsa_amd_profiling_async_copy_time_t *time) +try: (hsa_amd_profiling_get_async_copy_time:=dll.hsa_amd_profiling_get_async_copy_time).restype, hsa_amd_profiling_get_async_copy_time.argtypes = hsa_status_t, [hsa_signal_t, ctypes.POINTER(hsa_amd_profiling_async_copy_time_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_profiling_convert_tick_to_system_domain(hsa_agent_t agent, uint64_t agent_tick, uint64_t *system_tick) +try: (hsa_amd_profiling_convert_tick_to_system_domain:=dll.hsa_amd_profiling_convert_tick_to_system_domain).restype, hsa_amd_profiling_convert_tick_to_system_domain.argtypes = hsa_status_t, [hsa_agent_t, uint64_t, ctypes.POINTER(uint64_t)] +except AttributeError: pass + +hsa_amd_signal_attribute_t = CEnum(ctypes.c_uint32) +HSA_AMD_SIGNAL_AMD_GPU_ONLY = hsa_amd_signal_attribute_t.define('HSA_AMD_SIGNAL_AMD_GPU_ONLY', 1) +HSA_AMD_SIGNAL_IPC = hsa_amd_signal_attribute_t.define('HSA_AMD_SIGNAL_IPC', 2) + +# hsa_status_t hsa_amd_signal_create(hsa_signal_value_t initial_value, uint32_t num_consumers, const hsa_agent_t *consumers, uint64_t attributes, hsa_signal_t *signal) +try: (hsa_amd_signal_create:=dll.hsa_amd_signal_create).restype, hsa_amd_signal_create.argtypes = hsa_status_t, [hsa_signal_value_t, uint32_t, ctypes.POINTER(hsa_agent_t), uint64_t, ctypes.POINTER(hsa_signal_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_signal_value_pointer(hsa_signal_t signal, volatile hsa_signal_value_t **value_ptr) +try: (hsa_amd_signal_value_pointer:=dll.hsa_amd_signal_value_pointer).restype, hsa_amd_signal_value_pointer.argtypes = hsa_status_t, [hsa_signal_t, ctypes.POINTER(ctypes.POINTER(hsa_signal_value_t))] +except AttributeError: pass + +hsa_amd_signal_handler = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_int64, ctypes.c_void_p) +# hsa_status_t hsa_amd_signal_async_handler(hsa_signal_t signal, hsa_signal_condition_t cond, hsa_signal_value_t value, hsa_amd_signal_handler handler, void *arg) +try: (hsa_amd_signal_async_handler:=dll.hsa_amd_signal_async_handler).restype, hsa_amd_signal_async_handler.argtypes = hsa_status_t, [hsa_signal_t, hsa_signal_condition_t, hsa_signal_value_t, hsa_amd_signal_handler, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_async_function(void (*callback)(void *), void *arg) +try: (hsa_amd_async_function:=dll.hsa_amd_async_function).restype, hsa_amd_async_function.argtypes = hsa_status_t, [ctypes.CFUNCTYPE(None, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# uint32_t hsa_amd_signal_wait_any(uint32_t signal_count, hsa_signal_t *signals, hsa_signal_condition_t *conds, hsa_signal_value_t *values, uint64_t timeout_hint, hsa_wait_state_t wait_hint, hsa_signal_value_t *satisfying_value) +try: (hsa_amd_signal_wait_any:=dll.hsa_amd_signal_wait_any).restype, hsa_amd_signal_wait_any.argtypes = uint32_t, [uint32_t, ctypes.POINTER(hsa_signal_t), ctypes.POINTER(hsa_signal_condition_t), ctypes.POINTER(hsa_signal_value_t), uint64_t, hsa_wait_state_t, ctypes.POINTER(hsa_signal_value_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_image_get_info_max_dim(hsa_agent_t agent, hsa_agent_info_t attribute, void *value) +try: (hsa_amd_image_get_info_max_dim:=dll.hsa_amd_image_get_info_max_dim).restype, hsa_amd_image_get_info_max_dim.argtypes = hsa_status_t, [hsa_agent_t, hsa_agent_info_t, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_queue_cu_set_mask(const hsa_queue_t *queue, uint32_t num_cu_mask_count, const uint32_t *cu_mask) +try: (hsa_amd_queue_cu_set_mask:=dll.hsa_amd_queue_cu_set_mask).restype, hsa_amd_queue_cu_set_mask.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t), uint32_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_queue_cu_get_mask(const hsa_queue_t *queue, uint32_t num_cu_mask_count, uint32_t *cu_mask) +try: (hsa_amd_queue_cu_get_mask:=dll.hsa_amd_queue_cu_get_mask).restype, hsa_amd_queue_cu_get_mask.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t), uint32_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +hsa_amd_segment_t = CEnum(ctypes.c_uint32) +HSA_AMD_SEGMENT_GLOBAL = hsa_amd_segment_t.define('HSA_AMD_SEGMENT_GLOBAL', 0) +HSA_AMD_SEGMENT_READONLY = hsa_amd_segment_t.define('HSA_AMD_SEGMENT_READONLY', 1) +HSA_AMD_SEGMENT_PRIVATE = hsa_amd_segment_t.define('HSA_AMD_SEGMENT_PRIVATE', 2) +HSA_AMD_SEGMENT_GROUP = hsa_amd_segment_t.define('HSA_AMD_SEGMENT_GROUP', 3) + +class struct_hsa_amd_memory_pool_s(Struct): pass struct_hsa_amd_memory_pool_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_amd_memory_pool_t = struct_hsa_amd_memory_pool_s +enum_hsa_amd_memory_pool_global_flag_s = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT = enum_hsa_amd_memory_pool_global_flag_s.define('HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT', 1) +HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED = enum_hsa_amd_memory_pool_global_flag_s.define('HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED', 2) +HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED = enum_hsa_amd_memory_pool_global_flag_s.define('HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED', 4) +HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED = enum_hsa_amd_memory_pool_global_flag_s.define('HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', 8) -# values for enumeration 'hsa_amd_memory_pool_global_flag_s' -hsa_amd_memory_pool_global_flag_s__enumvalues = { - 1: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT', - 2: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED', - 4: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED', - 8: 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', -} -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT = 1 -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED = 2 -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED = 4 -HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED = 8 -hsa_amd_memory_pool_global_flag_s = ctypes.c_uint32 # enum -hsa_amd_memory_pool_global_flag_t = hsa_amd_memory_pool_global_flag_s -hsa_amd_memory_pool_global_flag_t__enumvalues = hsa_amd_memory_pool_global_flag_s__enumvalues +hsa_amd_memory_pool_global_flag_t = enum_hsa_amd_memory_pool_global_flag_s +enum_hsa_amd_memory_pool_location_s = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_POOL_LOCATION_CPU = enum_hsa_amd_memory_pool_location_s.define('HSA_AMD_MEMORY_POOL_LOCATION_CPU', 0) +HSA_AMD_MEMORY_POOL_LOCATION_GPU = enum_hsa_amd_memory_pool_location_s.define('HSA_AMD_MEMORY_POOL_LOCATION_GPU', 1) -# values for enumeration 'hsa_amd_memory_pool_location_s' -hsa_amd_memory_pool_location_s__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_LOCATION_CPU', - 1: 'HSA_AMD_MEMORY_POOL_LOCATION_GPU', -} -HSA_AMD_MEMORY_POOL_LOCATION_CPU = 0 -HSA_AMD_MEMORY_POOL_LOCATION_GPU = 1 -hsa_amd_memory_pool_location_s = ctypes.c_uint32 # enum -hsa_amd_memory_pool_location_t = hsa_amd_memory_pool_location_s -hsa_amd_memory_pool_location_t__enumvalues = hsa_amd_memory_pool_location_s__enumvalues +hsa_amd_memory_pool_location_t = enum_hsa_amd_memory_pool_location_s +hsa_amd_memory_pool_info_t = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_POOL_INFO_SEGMENT = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_SEGMENT', 0) +HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS', 1) +HSA_AMD_MEMORY_POOL_INFO_SIZE = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_SIZE', 2) +HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED', 5) +HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE', 6) +HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT', 7) +HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL', 15) +HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE', 16) +HSA_AMD_MEMORY_POOL_INFO_LOCATION = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_LOCATION', 17) +HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE = hsa_amd_memory_pool_info_t.define('HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE', 18) -# values for enumeration 'c__EA_hsa_amd_memory_pool_info_t' -c__EA_hsa_amd_memory_pool_info_t__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_INFO_SEGMENT', - 1: 'HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS', - 2: 'HSA_AMD_MEMORY_POOL_INFO_SIZE', - 5: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED', - 6: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE', - 7: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT', - 15: 'HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL', - 16: 'HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE', - 17: 'HSA_AMD_MEMORY_POOL_INFO_LOCATION', - 18: 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE', -} -HSA_AMD_MEMORY_POOL_INFO_SEGMENT = 0 -HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS = 1 -HSA_AMD_MEMORY_POOL_INFO_SIZE = 2 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED = 5 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE = 6 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT = 7 -HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL = 15 -HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE = 16 -HSA_AMD_MEMORY_POOL_INFO_LOCATION = 17 -HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE = 18 -c__EA_hsa_amd_memory_pool_info_t = ctypes.c_uint32 # enum -hsa_amd_memory_pool_info_t = c__EA_hsa_amd_memory_pool_info_t -hsa_amd_memory_pool_info_t__enumvalues = c__EA_hsa_amd_memory_pool_info_t__enumvalues +enum_hsa_amd_memory_pool_flag_s = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_POOL_STANDARD_FLAG = enum_hsa_amd_memory_pool_flag_s.define('HSA_AMD_MEMORY_POOL_STANDARD_FLAG', 0) +HSA_AMD_MEMORY_POOL_PCIE_FLAG = enum_hsa_amd_memory_pool_flag_s.define('HSA_AMD_MEMORY_POOL_PCIE_FLAG', 1) +HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG = enum_hsa_amd_memory_pool_flag_s.define('HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG', 2) -# values for enumeration 'hsa_amd_memory_pool_flag_s' -hsa_amd_memory_pool_flag_s__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_STANDARD_FLAG', - 1: 'HSA_AMD_MEMORY_POOL_PCIE_FLAG', - 2: 'HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG', -} -HSA_AMD_MEMORY_POOL_STANDARD_FLAG = 0 -HSA_AMD_MEMORY_POOL_PCIE_FLAG = 1 -HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG = 2 -hsa_amd_memory_pool_flag_s = ctypes.c_uint32 # enum -hsa_amd_memory_pool_flag_t = hsa_amd_memory_pool_flag_s -hsa_amd_memory_pool_flag_t__enumvalues = hsa_amd_memory_pool_flag_s__enumvalues -try: - hsa_amd_memory_pool_get_info = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_get_info - hsa_amd_memory_pool_get_info.restype = hsa_status_t - hsa_amd_memory_pool_get_info.argtypes = [hsa_amd_memory_pool_t, hsa_amd_memory_pool_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_agent_iterate_memory_pools = _libraries['libhsa-runtime64.so'].hsa_amd_agent_iterate_memory_pools - hsa_amd_agent_iterate_memory_pools.restype = hsa_status_t - hsa_amd_agent_iterate_memory_pools.argtypes = [hsa_agent_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_amd_memory_pool_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_pool_allocate = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_allocate - hsa_amd_memory_pool_allocate.restype = hsa_status_t - hsa_amd_memory_pool_allocate.argtypes = [hsa_amd_memory_pool_t, size_t, uint32_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_memory_pool_free = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_free - hsa_amd_memory_pool_free.restype = hsa_status_t - hsa_amd_memory_pool_free.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_async_copy = _libraries['libhsa-runtime64.so'].hsa_amd_memory_async_copy - hsa_amd_memory_async_copy.restype = hsa_status_t - hsa_amd_memory_async_copy.argtypes = [ctypes.POINTER(None), hsa_agent_t, ctypes.POINTER(None), hsa_agent_t, size_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t] -except AttributeError: - pass -try: - hsa_amd_memory_async_copy_on_engine = _libraries['libhsa-runtime64.so'].hsa_amd_memory_async_copy_on_engine - hsa_amd_memory_async_copy_on_engine.restype = hsa_status_t - hsa_amd_memory_async_copy_on_engine.argtypes = [ctypes.POINTER(None), hsa_agent_t, ctypes.POINTER(None), hsa_agent_t, size_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t, hsa_amd_sdma_engine_id_t, ctypes.c_bool] -except AttributeError: - pass -try: - hsa_amd_memory_copy_engine_status = _libraries['libhsa-runtime64.so'].hsa_amd_memory_copy_engine_status - hsa_amd_memory_copy_engine_status.restype = hsa_status_t - hsa_amd_memory_copy_engine_status.argtypes = [hsa_agent_t, hsa_agent_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -class struct_hsa_pitched_ptr_s(Structure): - pass +hsa_amd_memory_pool_flag_t = enum_hsa_amd_memory_pool_flag_s +# hsa_status_t hsa_amd_memory_pool_get_info(hsa_amd_memory_pool_t memory_pool, hsa_amd_memory_pool_info_t attribute, void *value) +try: (hsa_amd_memory_pool_get_info:=dll.hsa_amd_memory_pool_get_info).restype, hsa_amd_memory_pool_get_info.argtypes = hsa_status_t, [hsa_amd_memory_pool_t, hsa_amd_memory_pool_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_pitched_ptr_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_agent_iterate_memory_pools(hsa_agent_t agent, hsa_status_t (*callback)(hsa_amd_memory_pool_t, void *), void *data) +try: (hsa_amd_agent_iterate_memory_pools:=dll.hsa_amd_agent_iterate_memory_pools).restype, hsa_amd_agent_iterate_memory_pools.argtypes = hsa_status_t, [hsa_agent_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_amd_memory_pool_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_pool_allocate(hsa_amd_memory_pool_t memory_pool, size_t size, uint32_t flags, void **ptr) +try: (hsa_amd_memory_pool_allocate:=dll.hsa_amd_memory_pool_allocate).restype, hsa_amd_memory_pool_allocate.argtypes = hsa_status_t, [hsa_amd_memory_pool_t, size_t, uint32_t, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_pool_free(void *ptr) +try: (hsa_amd_memory_pool_free:=dll.hsa_amd_memory_pool_free).restype, hsa_amd_memory_pool_free.argtypes = hsa_status_t, [ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_async_copy(void *dst, hsa_agent_t dst_agent, const void *src, hsa_agent_t src_agent, size_t size, uint32_t num_dep_signals, const hsa_signal_t *dep_signals, hsa_signal_t completion_signal) +try: (hsa_amd_memory_async_copy:=dll.hsa_amd_memory_async_copy).restype, hsa_amd_memory_async_copy.argtypes = hsa_status_t, [ctypes.c_void_p, hsa_agent_t, ctypes.c_void_p, hsa_agent_t, size_t, uint32_t, ctypes.POINTER(hsa_signal_t), hsa_signal_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_async_copy_on_engine(void *dst, hsa_agent_t dst_agent, const void *src, hsa_agent_t src_agent, size_t size, uint32_t num_dep_signals, const hsa_signal_t *dep_signals, hsa_signal_t completion_signal, hsa_amd_sdma_engine_id_t engine_id, bool force_copy_on_sdma) +try: (hsa_amd_memory_async_copy_on_engine:=dll.hsa_amd_memory_async_copy_on_engine).restype, hsa_amd_memory_async_copy_on_engine.argtypes = hsa_status_t, [ctypes.c_void_p, hsa_agent_t, ctypes.c_void_p, hsa_agent_t, size_t, uint32_t, ctypes.POINTER(hsa_signal_t), hsa_signal_t, hsa_amd_sdma_engine_id_t, ctypes.c_bool] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_copy_engine_status(hsa_agent_t dst_agent, hsa_agent_t src_agent, uint32_t *engine_ids_mask) +try: (hsa_amd_memory_copy_engine_status:=dll.hsa_amd_memory_copy_engine_status).restype, hsa_amd_memory_copy_engine_status.argtypes = hsa_status_t, [hsa_agent_t, hsa_agent_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +class struct_hsa_pitched_ptr_s(Struct): pass struct_hsa_pitched_ptr_s._fields_ = [ - ('base', ctypes.POINTER(None)), - ('pitch', ctypes.c_uint64), - ('slice', ctypes.c_uint64), + ('base', ctypes.c_void_p), + ('pitch', size_t), + ('slice', size_t), ] - hsa_pitched_ptr_t = struct_hsa_pitched_ptr_s +hsa_amd_copy_direction_t = CEnum(ctypes.c_uint32) +hsaHostToHost = hsa_amd_copy_direction_t.define('hsaHostToHost', 0) +hsaHostToDevice = hsa_amd_copy_direction_t.define('hsaHostToDevice', 1) +hsaDeviceToHost = hsa_amd_copy_direction_t.define('hsaDeviceToHost', 2) +hsaDeviceToDevice = hsa_amd_copy_direction_t.define('hsaDeviceToDevice', 3) -# values for enumeration 'c__EA_hsa_amd_copy_direction_t' -c__EA_hsa_amd_copy_direction_t__enumvalues = { - 0: 'hsaHostToHost', - 1: 'hsaHostToDevice', - 2: 'hsaDeviceToHost', - 3: 'hsaDeviceToDevice', -} -hsaHostToHost = 0 -hsaHostToDevice = 1 -hsaDeviceToHost = 2 -hsaDeviceToDevice = 3 -c__EA_hsa_amd_copy_direction_t = ctypes.c_uint32 # enum -hsa_amd_copy_direction_t = c__EA_hsa_amd_copy_direction_t -hsa_amd_copy_direction_t__enumvalues = c__EA_hsa_amd_copy_direction_t__enumvalues -try: - hsa_amd_memory_async_copy_rect = _libraries['libhsa-runtime64.so'].hsa_amd_memory_async_copy_rect - hsa_amd_memory_async_copy_rect.restype = hsa_status_t - hsa_amd_memory_async_copy_rect.argtypes = [ctypes.POINTER(struct_hsa_pitched_ptr_s), ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_pitched_ptr_s), ctypes.POINTER(struct_hsa_dim3_s), ctypes.POINTER(struct_hsa_dim3_s), hsa_agent_t, hsa_amd_copy_direction_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t] -except AttributeError: - pass +# hsa_status_t hsa_amd_memory_async_copy_rect(const hsa_pitched_ptr_t *dst, const hsa_dim3_t *dst_offset, const hsa_pitched_ptr_t *src, const hsa_dim3_t *src_offset, const hsa_dim3_t *range, hsa_agent_t copy_agent, hsa_amd_copy_direction_t dir, uint32_t num_dep_signals, const hsa_signal_t *dep_signals, hsa_signal_t completion_signal) +try: (hsa_amd_memory_async_copy_rect:=dll.hsa_amd_memory_async_copy_rect).restype, hsa_amd_memory_async_copy_rect.argtypes = hsa_status_t, [ctypes.POINTER(hsa_pitched_ptr_t), ctypes.POINTER(hsa_dim3_t), ctypes.POINTER(hsa_pitched_ptr_t), ctypes.POINTER(hsa_dim3_t), ctypes.POINTER(hsa_dim3_t), hsa_agent_t, hsa_amd_copy_direction_t, uint32_t, ctypes.POINTER(hsa_signal_t), hsa_signal_t] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_amd_memory_pool_access_t' -c__EA_hsa_amd_memory_pool_access_t__enumvalues = { - 0: 'HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED', - 1: 'HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT', - 2: 'HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT', -} -HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED = 0 -HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT = 1 -HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT = 2 -c__EA_hsa_amd_memory_pool_access_t = ctypes.c_uint32 # enum -hsa_amd_memory_pool_access_t = c__EA_hsa_amd_memory_pool_access_t -hsa_amd_memory_pool_access_t__enumvalues = c__EA_hsa_amd_memory_pool_access_t__enumvalues +hsa_amd_memory_pool_access_t = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED = hsa_amd_memory_pool_access_t.define('HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED', 0) +HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT = hsa_amd_memory_pool_access_t.define('HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT', 1) +HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT = hsa_amd_memory_pool_access_t.define('HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT', 2) -# values for enumeration 'c__EA_hsa_amd_link_info_type_t' -c__EA_hsa_amd_link_info_type_t__enumvalues = { - 0: 'HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT', - 1: 'HSA_AMD_LINK_INFO_TYPE_QPI', - 2: 'HSA_AMD_LINK_INFO_TYPE_PCIE', - 3: 'HSA_AMD_LINK_INFO_TYPE_INFINBAND', - 4: 'HSA_AMD_LINK_INFO_TYPE_XGMI', -} -HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT = 0 -HSA_AMD_LINK_INFO_TYPE_QPI = 1 -HSA_AMD_LINK_INFO_TYPE_PCIE = 2 -HSA_AMD_LINK_INFO_TYPE_INFINBAND = 3 -HSA_AMD_LINK_INFO_TYPE_XGMI = 4 -c__EA_hsa_amd_link_info_type_t = ctypes.c_uint32 # enum -hsa_amd_link_info_type_t = c__EA_hsa_amd_link_info_type_t -hsa_amd_link_info_type_t__enumvalues = c__EA_hsa_amd_link_info_type_t__enumvalues -class struct_hsa_amd_memory_pool_link_info_s(Structure): - pass +hsa_amd_link_info_type_t = CEnum(ctypes.c_uint32) +HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT = hsa_amd_link_info_type_t.define('HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT', 0) +HSA_AMD_LINK_INFO_TYPE_QPI = hsa_amd_link_info_type_t.define('HSA_AMD_LINK_INFO_TYPE_QPI', 1) +HSA_AMD_LINK_INFO_TYPE_PCIE = hsa_amd_link_info_type_t.define('HSA_AMD_LINK_INFO_TYPE_PCIE', 2) +HSA_AMD_LINK_INFO_TYPE_INFINBAND = hsa_amd_link_info_type_t.define('HSA_AMD_LINK_INFO_TYPE_INFINBAND', 3) +HSA_AMD_LINK_INFO_TYPE_XGMI = hsa_amd_link_info_type_t.define('HSA_AMD_LINK_INFO_TYPE_XGMI', 4) -struct_hsa_amd_memory_pool_link_info_s._pack_ = 1 # source:False +class struct_hsa_amd_memory_pool_link_info_s(Struct): pass struct_hsa_amd_memory_pool_link_info_s._fields_ = [ - ('min_latency', ctypes.c_uint32), - ('max_latency', ctypes.c_uint32), - ('min_bandwidth', ctypes.c_uint32), - ('max_bandwidth', ctypes.c_uint32), - ('atomic_support_32bit', ctypes.c_bool), - ('atomic_support_64bit', ctypes.c_bool), - ('coherent_support', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), - ('link_type', hsa_amd_link_info_type_t), - ('numa_distance', ctypes.c_uint32), + ('min_latency', uint32_t), + ('max_latency', uint32_t), + ('min_bandwidth', uint32_t), + ('max_bandwidth', uint32_t), + ('atomic_support_32bit', ctypes.c_bool), + ('atomic_support_64bit', ctypes.c_bool), + ('coherent_support', ctypes.c_bool), + ('link_type', hsa_amd_link_info_type_t), + ('numa_distance', uint32_t), ] - hsa_amd_memory_pool_link_info_t = struct_hsa_amd_memory_pool_link_info_s +hsa_amd_agent_memory_pool_info_t = CEnum(ctypes.c_uint32) +HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS = hsa_amd_agent_memory_pool_info_t.define('HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS', 0) +HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS = hsa_amd_agent_memory_pool_info_t.define('HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS', 1) +HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO = hsa_amd_agent_memory_pool_info_t.define('HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO', 2) -# values for enumeration 'c__EA_hsa_amd_agent_memory_pool_info_t' -c__EA_hsa_amd_agent_memory_pool_info_t__enumvalues = { - 0: 'HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS', - 1: 'HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS', - 2: 'HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO', -} -HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS = 0 -HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS = 1 -HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO = 2 -c__EA_hsa_amd_agent_memory_pool_info_t = ctypes.c_uint32 # enum -hsa_amd_agent_memory_pool_info_t = c__EA_hsa_amd_agent_memory_pool_info_t -hsa_amd_agent_memory_pool_info_t__enumvalues = c__EA_hsa_amd_agent_memory_pool_info_t__enumvalues -try: - hsa_amd_agent_memory_pool_get_info = _libraries['libhsa-runtime64.so'].hsa_amd_agent_memory_pool_get_info - hsa_amd_agent_memory_pool_get_info.restype = hsa_status_t - hsa_amd_agent_memory_pool_get_info.argtypes = [hsa_agent_t, hsa_amd_memory_pool_t, hsa_amd_agent_memory_pool_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_agents_allow_access = _libraries['libhsa-runtime64.so'].hsa_amd_agents_allow_access - hsa_amd_agents_allow_access.restype = hsa_status_t - hsa_amd_agents_allow_access.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_pool_can_migrate = _libraries['libhsa-runtime64.so'].hsa_amd_memory_pool_can_migrate - hsa_amd_memory_pool_can_migrate.restype = hsa_status_t - hsa_amd_memory_pool_can_migrate.argtypes = [hsa_amd_memory_pool_t, hsa_amd_memory_pool_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_amd_memory_migrate = _libraries['libhsa-runtime64.so'].hsa_amd_memory_migrate - hsa_amd_memory_migrate.restype = hsa_status_t - hsa_amd_memory_migrate.argtypes = [ctypes.POINTER(None), hsa_amd_memory_pool_t, uint32_t] -except AttributeError: - pass -try: - hsa_amd_memory_lock = _libraries['libhsa-runtime64.so'].hsa_amd_memory_lock - hsa_amd_memory_lock.restype = hsa_status_t - hsa_amd_memory_lock.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_memory_lock_to_pool = _libraries['libhsa-runtime64.so'].hsa_amd_memory_lock_to_pool - hsa_amd_memory_lock_to_pool.restype = hsa_status_t - hsa_amd_memory_lock_to_pool.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.c_int32, hsa_amd_memory_pool_t, uint32_t, ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_memory_unlock = _libraries['libhsa-runtime64.so'].hsa_amd_memory_unlock - hsa_amd_memory_unlock.restype = hsa_status_t - hsa_amd_memory_unlock.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_memory_fill = _libraries['libhsa-runtime64.so'].hsa_amd_memory_fill - hsa_amd_memory_fill.restype = hsa_status_t - hsa_amd_memory_fill.argtypes = [ctypes.POINTER(None), uint32_t, size_t] -except AttributeError: - pass -try: - hsa_amd_interop_map_buffer = _libraries['libhsa-runtime64.so'].hsa_amd_interop_map_buffer - hsa_amd_interop_map_buffer.restype = hsa_status_t - hsa_amd_interop_map_buffer.argtypes = [uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.c_int32, uint32_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_interop_unmap_buffer = _libraries['libhsa-runtime64.so'].hsa_amd_interop_unmap_buffer - hsa_amd_interop_unmap_buffer.restype = hsa_status_t - hsa_amd_interop_unmap_buffer.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_amd_image_descriptor_s(Structure): - pass +# hsa_status_t hsa_amd_agent_memory_pool_get_info(hsa_agent_t agent, hsa_amd_memory_pool_t memory_pool, hsa_amd_agent_memory_pool_info_t attribute, void *value) +try: (hsa_amd_agent_memory_pool_get_info:=dll.hsa_amd_agent_memory_pool_get_info).restype, hsa_amd_agent_memory_pool_get_info.argtypes = hsa_status_t, [hsa_agent_t, hsa_amd_memory_pool_t, hsa_amd_agent_memory_pool_info_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_amd_image_descriptor_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_agents_allow_access(uint32_t num_agents, const hsa_agent_t *agents, const uint32_t *flags, const void *ptr) +try: (hsa_amd_agents_allow_access:=dll.hsa_amd_agents_allow_access).restype, hsa_amd_agents_allow_access.argtypes = hsa_status_t, [uint32_t, ctypes.POINTER(hsa_agent_t), ctypes.POINTER(uint32_t), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_pool_can_migrate(hsa_amd_memory_pool_t src_memory_pool, hsa_amd_memory_pool_t dst_memory_pool, bool *result) +try: (hsa_amd_memory_pool_can_migrate:=dll.hsa_amd_memory_pool_can_migrate).restype, hsa_amd_memory_pool_can_migrate.argtypes = hsa_status_t, [hsa_amd_memory_pool_t, hsa_amd_memory_pool_t, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_migrate(const void *ptr, hsa_amd_memory_pool_t memory_pool, uint32_t flags) +try: (hsa_amd_memory_migrate:=dll.hsa_amd_memory_migrate).restype, hsa_amd_memory_migrate.argtypes = hsa_status_t, [ctypes.c_void_p, hsa_amd_memory_pool_t, uint32_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_lock(void *host_ptr, size_t size, hsa_agent_t *agents, int num_agent, void **agent_ptr) +try: (hsa_amd_memory_lock:=dll.hsa_amd_memory_lock).restype, hsa_amd_memory_lock.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_agent_t), ctypes.c_int32, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_lock_to_pool(void *host_ptr, size_t size, hsa_agent_t *agents, int num_agent, hsa_amd_memory_pool_t pool, uint32_t flags, void **agent_ptr) +try: (hsa_amd_memory_lock_to_pool:=dll.hsa_amd_memory_lock_to_pool).restype, hsa_amd_memory_lock_to_pool.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_agent_t), ctypes.c_int32, hsa_amd_memory_pool_t, uint32_t, ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_unlock(void *host_ptr) +try: (hsa_amd_memory_unlock:=dll.hsa_amd_memory_unlock).restype, hsa_amd_memory_unlock.argtypes = hsa_status_t, [ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_memory_fill(void *ptr, uint32_t value, size_t count) +try: (hsa_amd_memory_fill:=dll.hsa_amd_memory_fill).restype, hsa_amd_memory_fill.argtypes = hsa_status_t, [ctypes.c_void_p, uint32_t, size_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_interop_map_buffer(uint32_t num_agents, hsa_agent_t *agents, int interop_handle, uint32_t flags, size_t *size, void **ptr, size_t *metadata_size, const void **metadata) +try: (hsa_amd_interop_map_buffer:=dll.hsa_amd_interop_map_buffer).restype, hsa_amd_interop_map_buffer.argtypes = hsa_status_t, [uint32_t, ctypes.POINTER(hsa_agent_t), ctypes.c_int32, uint32_t, ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hsa_status_t hsa_amd_interop_unmap_buffer(void *ptr) +try: (hsa_amd_interop_unmap_buffer:=dll.hsa_amd_interop_unmap_buffer).restype, hsa_amd_interop_unmap_buffer.argtypes = hsa_status_t, [ctypes.c_void_p] +except AttributeError: pass + +class struct_hsa_amd_image_descriptor_s(Struct): pass struct_hsa_amd_image_descriptor_s._fields_ = [ - ('version', ctypes.c_uint32), - ('deviceID', ctypes.c_uint32), - ('data', ctypes.c_uint32 * 1), + ('version', uint32_t), + ('deviceID', uint32_t), + ('data', (uint32_t * 1)), ] - hsa_amd_image_descriptor_t = struct_hsa_amd_image_descriptor_s -try: - hsa_amd_image_create = _libraries['libhsa-runtime64.so'].hsa_amd_image_create - hsa_amd_image_create.restype = hsa_status_t - hsa_amd_image_create.argtypes = [hsa_agent_t, ctypes.POINTER(struct_hsa_ext_image_descriptor_s), ctypes.POINTER(struct_hsa_amd_image_descriptor_s), ctypes.POINTER(None), hsa_access_permission_t, ctypes.POINTER(struct_hsa_ext_image_s)] -except AttributeError: - pass +class struct_hsa_ext_image_descriptor_s(Struct): pass +hsa_ext_image_descriptor_t = struct_hsa_ext_image_descriptor_s +hsa_ext_image_geometry_t = CEnum(ctypes.c_uint32) +HSA_EXT_IMAGE_GEOMETRY_1D = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_1D', 0) +HSA_EXT_IMAGE_GEOMETRY_2D = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_2D', 1) +HSA_EXT_IMAGE_GEOMETRY_3D = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_3D', 2) +HSA_EXT_IMAGE_GEOMETRY_1DA = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_1DA', 3) +HSA_EXT_IMAGE_GEOMETRY_2DA = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_2DA', 4) +HSA_EXT_IMAGE_GEOMETRY_1DB = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_1DB', 5) +HSA_EXT_IMAGE_GEOMETRY_2DDEPTH = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_2DDEPTH', 6) +HSA_EXT_IMAGE_GEOMETRY_2DADEPTH = hsa_ext_image_geometry_t.define('HSA_EXT_IMAGE_GEOMETRY_2DADEPTH', 7) -# values for enumeration 'c__EA_hsa_amd_pointer_type_t' -c__EA_hsa_amd_pointer_type_t__enumvalues = { - 0: 'HSA_EXT_POINTER_TYPE_UNKNOWN', - 1: 'HSA_EXT_POINTER_TYPE_HSA', - 2: 'HSA_EXT_POINTER_TYPE_LOCKED', - 3: 'HSA_EXT_POINTER_TYPE_GRAPHICS', - 4: 'HSA_EXT_POINTER_TYPE_IPC', -} -HSA_EXT_POINTER_TYPE_UNKNOWN = 0 -HSA_EXT_POINTER_TYPE_HSA = 1 -HSA_EXT_POINTER_TYPE_LOCKED = 2 -HSA_EXT_POINTER_TYPE_GRAPHICS = 3 -HSA_EXT_POINTER_TYPE_IPC = 4 -c__EA_hsa_amd_pointer_type_t = ctypes.c_uint32 # enum -hsa_amd_pointer_type_t = c__EA_hsa_amd_pointer_type_t -hsa_amd_pointer_type_t__enumvalues = c__EA_hsa_amd_pointer_type_t__enumvalues -class struct_hsa_amd_pointer_info_s(Structure): - pass +class struct_hsa_ext_image_format_s(Struct): pass +hsa_ext_image_format_t = struct_hsa_ext_image_format_s +hsa_ext_image_channel_type32_t = ctypes.c_uint32 +hsa_ext_image_channel_order32_t = ctypes.c_uint32 +struct_hsa_ext_image_format_s._fields_ = [ + ('channel_type', hsa_ext_image_channel_type32_t), + ('channel_order', hsa_ext_image_channel_order32_t), +] +struct_hsa_ext_image_descriptor_s._fields_ = [ + ('geometry', hsa_ext_image_geometry_t), + ('width', size_t), + ('height', size_t), + ('depth', size_t), + ('array_size', size_t), + ('format', hsa_ext_image_format_t), +] +class struct_hsa_ext_image_s(Struct): pass +hsa_ext_image_t = struct_hsa_ext_image_s +struct_hsa_ext_image_s._fields_ = [ + ('handle', uint64_t), +] +# hsa_status_t hsa_amd_image_create(hsa_agent_t agent, const hsa_ext_image_descriptor_t *image_descriptor, const hsa_amd_image_descriptor_t *image_layout, const void *image_data, hsa_access_permission_t access_permission, hsa_ext_image_t *image) +try: (hsa_amd_image_create:=dll.hsa_amd_image_create).restype, hsa_amd_image_create.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), ctypes.POINTER(hsa_amd_image_descriptor_t), ctypes.c_void_p, hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_t)] +except AttributeError: pass -struct_hsa_amd_pointer_info_s._pack_ = 1 # source:False +hsa_amd_pointer_type_t = CEnum(ctypes.c_uint32) +HSA_EXT_POINTER_TYPE_UNKNOWN = hsa_amd_pointer_type_t.define('HSA_EXT_POINTER_TYPE_UNKNOWN', 0) +HSA_EXT_POINTER_TYPE_HSA = hsa_amd_pointer_type_t.define('HSA_EXT_POINTER_TYPE_HSA', 1) +HSA_EXT_POINTER_TYPE_LOCKED = hsa_amd_pointer_type_t.define('HSA_EXT_POINTER_TYPE_LOCKED', 2) +HSA_EXT_POINTER_TYPE_GRAPHICS = hsa_amd_pointer_type_t.define('HSA_EXT_POINTER_TYPE_GRAPHICS', 3) +HSA_EXT_POINTER_TYPE_IPC = hsa_amd_pointer_type_t.define('HSA_EXT_POINTER_TYPE_IPC', 4) + +class struct_hsa_amd_pointer_info_s(Struct): pass struct_hsa_amd_pointer_info_s._fields_ = [ - ('size', ctypes.c_uint32), - ('type', hsa_amd_pointer_type_t), - ('agentBaseAddress', ctypes.POINTER(None)), - ('hostBaseAddress', ctypes.POINTER(None)), - ('sizeInBytes', ctypes.c_uint64), - ('userData', ctypes.POINTER(None)), - ('agentOwner', hsa_agent_t), - ('global_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('size', uint32_t), + ('type', hsa_amd_pointer_type_t), + ('agentBaseAddress', ctypes.c_void_p), + ('hostBaseAddress', ctypes.c_void_p), + ('sizeInBytes', size_t), + ('userData', ctypes.c_void_p), + ('agentOwner', hsa_agent_t), + ('global_flags', uint32_t), ] - hsa_amd_pointer_info_t = struct_hsa_amd_pointer_info_s -try: - hsa_amd_pointer_info = _libraries['libhsa-runtime64.so'].hsa_amd_pointer_info - hsa_amd_pointer_info.restype = hsa_status_t - hsa_amd_pointer_info.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_hsa_amd_pointer_info_s), ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.POINTER(struct_hsa_agent_s))] -except AttributeError: - pass -try: - hsa_amd_pointer_info_set_userdata = _libraries['libhsa-runtime64.so'].hsa_amd_pointer_info_set_userdata - hsa_amd_pointer_info_set_userdata.restype = hsa_status_t - hsa_amd_pointer_info_set_userdata.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None)] -except AttributeError: - pass -class struct_hsa_amd_ipc_memory_s(Structure): - pass +# hsa_status_t hsa_amd_pointer_info(const void *ptr, hsa_amd_pointer_info_t *info, void *(*alloc)(size_t), uint32_t *num_agents_accessible, hsa_agent_t **accessible) +try: (hsa_amd_pointer_info:=dll.hsa_amd_pointer_info).restype, hsa_amd_pointer_info.argtypes = hsa_status_t, [ctypes.c_void_p, ctypes.POINTER(hsa_amd_pointer_info_t), ctypes.CFUNCTYPE(ctypes.c_void_p, size_t), ctypes.POINTER(uint32_t), ctypes.POINTER(ctypes.POINTER(hsa_agent_t))] +except AttributeError: pass -struct_hsa_amd_ipc_memory_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_pointer_info_set_userdata(const void *ptr, void *userdata) +try: (hsa_amd_pointer_info_set_userdata:=dll.hsa_amd_pointer_info_set_userdata).restype, hsa_amd_pointer_info_set_userdata.argtypes = hsa_status_t, [ctypes.c_void_p, ctypes.c_void_p] +except AttributeError: pass + +class struct_hsa_amd_ipc_memory_s(Struct): pass struct_hsa_amd_ipc_memory_s._fields_ = [ - ('handle', ctypes.c_uint32 * 8), + ('handle', (uint32_t * 8)), ] - hsa_amd_ipc_memory_t = struct_hsa_amd_ipc_memory_s -try: - hsa_amd_ipc_memory_create = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_memory_create - hsa_amd_ipc_memory_create.restype = hsa_status_t - hsa_amd_ipc_memory_create.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_ipc_memory_s)] -except AttributeError: - pass -try: - hsa_amd_ipc_memory_attach = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_memory_attach - hsa_amd_ipc_memory_attach.restype = hsa_status_t - hsa_amd_ipc_memory_attach.argtypes = [ctypes.POINTER(struct_hsa_amd_ipc_memory_s), size_t, uint32_t, ctypes.POINTER(struct_hsa_agent_s), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - hsa_amd_ipc_memory_detach = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_memory_detach - hsa_amd_ipc_memory_detach.restype = hsa_status_t - hsa_amd_ipc_memory_detach.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_amd_ipc_memory_create(void *ptr, size_t len, hsa_amd_ipc_memory_t *handle) +try: (hsa_amd_ipc_memory_create:=dll.hsa_amd_ipc_memory_create).restype, hsa_amd_ipc_memory_create.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_amd_ipc_memory_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_ipc_memory_attach(const hsa_amd_ipc_memory_t *handle, size_t len, uint32_t num_agents, const hsa_agent_t *mapping_agents, void **mapped_ptr) +try: (hsa_amd_ipc_memory_attach:=dll.hsa_amd_ipc_memory_attach).restype, hsa_amd_ipc_memory_attach.argtypes = hsa_status_t, [ctypes.POINTER(hsa_amd_ipc_memory_t), size_t, uint32_t, ctypes.POINTER(hsa_agent_t), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# hsa_status_t hsa_amd_ipc_memory_detach(void *mapped_ptr) +try: (hsa_amd_ipc_memory_detach:=dll.hsa_amd_ipc_memory_detach).restype, hsa_amd_ipc_memory_detach.argtypes = hsa_status_t, [ctypes.c_void_p] +except AttributeError: pass + hsa_amd_ipc_signal_t = struct_hsa_amd_ipc_memory_s -try: - hsa_amd_ipc_signal_create = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_signal_create - hsa_amd_ipc_signal_create.restype = hsa_status_t - hsa_amd_ipc_signal_create.argtypes = [hsa_signal_t, ctypes.POINTER(struct_hsa_amd_ipc_memory_s)] -except AttributeError: - pass -try: - hsa_amd_ipc_signal_attach = _libraries['libhsa-runtime64.so'].hsa_amd_ipc_signal_attach - hsa_amd_ipc_signal_attach.restype = hsa_status_t - hsa_amd_ipc_signal_attach.argtypes = [ctypes.POINTER(struct_hsa_amd_ipc_memory_s), ctypes.POINTER(struct_hsa_signal_s)] -except AttributeError: - pass +# hsa_status_t hsa_amd_ipc_signal_create(hsa_signal_t signal, hsa_amd_ipc_signal_t *handle) +try: (hsa_amd_ipc_signal_create:=dll.hsa_amd_ipc_signal_create).restype, hsa_amd_ipc_signal_create.argtypes = hsa_status_t, [hsa_signal_t, ctypes.POINTER(hsa_amd_ipc_signal_t)] +except AttributeError: pass -# values for enumeration 'hsa_amd_event_type_s' -hsa_amd_event_type_s__enumvalues = { - 0: 'HSA_AMD_GPU_MEMORY_FAULT_EVENT', - 1: 'HSA_AMD_GPU_HW_EXCEPTION_EVENT', -} -HSA_AMD_GPU_MEMORY_FAULT_EVENT = 0 -HSA_AMD_GPU_HW_EXCEPTION_EVENT = 1 -hsa_amd_event_type_s = ctypes.c_uint32 # enum -hsa_amd_event_type_t = hsa_amd_event_type_s -hsa_amd_event_type_t__enumvalues = hsa_amd_event_type_s__enumvalues +# hsa_status_t hsa_amd_ipc_signal_attach(const hsa_amd_ipc_signal_t *handle, hsa_signal_t *signal) +try: (hsa_amd_ipc_signal_attach:=dll.hsa_amd_ipc_signal_attach).restype, hsa_amd_ipc_signal_attach.argtypes = hsa_status_t, [ctypes.POINTER(hsa_amd_ipc_signal_t), ctypes.POINTER(hsa_signal_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_amd_memory_fault_reason_t' -c__EA_hsa_amd_memory_fault_reason_t__enumvalues = { - 1: 'HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT', - 2: 'HSA_AMD_MEMORY_FAULT_READ_ONLY', - 4: 'HSA_AMD_MEMORY_FAULT_NX', - 8: 'HSA_AMD_MEMORY_FAULT_HOST_ONLY', - 16: 'HSA_AMD_MEMORY_FAULT_DRAMECC', - 32: 'HSA_AMD_MEMORY_FAULT_IMPRECISE', - 64: 'HSA_AMD_MEMORY_FAULT_SRAMECC', - 2147483648: 'HSA_AMD_MEMORY_FAULT_HANG', -} -HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT = 1 -HSA_AMD_MEMORY_FAULT_READ_ONLY = 2 -HSA_AMD_MEMORY_FAULT_NX = 4 -HSA_AMD_MEMORY_FAULT_HOST_ONLY = 8 -HSA_AMD_MEMORY_FAULT_DRAMECC = 16 -HSA_AMD_MEMORY_FAULT_IMPRECISE = 32 -HSA_AMD_MEMORY_FAULT_SRAMECC = 64 -HSA_AMD_MEMORY_FAULT_HANG = 2147483648 -c__EA_hsa_amd_memory_fault_reason_t = ctypes.c_uint32 # enum -hsa_amd_memory_fault_reason_t = c__EA_hsa_amd_memory_fault_reason_t -hsa_amd_memory_fault_reason_t__enumvalues = c__EA_hsa_amd_memory_fault_reason_t__enumvalues -class struct_hsa_amd_gpu_memory_fault_info_s(Structure): - pass +enum_hsa_amd_event_type_s = CEnum(ctypes.c_uint32) +HSA_AMD_GPU_MEMORY_FAULT_EVENT = enum_hsa_amd_event_type_s.define('HSA_AMD_GPU_MEMORY_FAULT_EVENT', 0) +HSA_AMD_GPU_HW_EXCEPTION_EVENT = enum_hsa_amd_event_type_s.define('HSA_AMD_GPU_HW_EXCEPTION_EVENT', 1) -struct_hsa_amd_gpu_memory_fault_info_s._pack_ = 1 # source:False +hsa_amd_event_type_t = enum_hsa_amd_event_type_s +hsa_amd_memory_fault_reason_t = CEnum(ctypes.c_uint32) +HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT', 1) +HSA_AMD_MEMORY_FAULT_READ_ONLY = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_READ_ONLY', 2) +HSA_AMD_MEMORY_FAULT_NX = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_NX', 4) +HSA_AMD_MEMORY_FAULT_HOST_ONLY = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_HOST_ONLY', 8) +HSA_AMD_MEMORY_FAULT_DRAMECC = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_DRAMECC', 16) +HSA_AMD_MEMORY_FAULT_IMPRECISE = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_IMPRECISE', 32) +HSA_AMD_MEMORY_FAULT_SRAMECC = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_SRAMECC', 64) +HSA_AMD_MEMORY_FAULT_HANG = hsa_amd_memory_fault_reason_t.define('HSA_AMD_MEMORY_FAULT_HANG', 2147483648) + +class struct_hsa_amd_gpu_memory_fault_info_s(Struct): pass struct_hsa_amd_gpu_memory_fault_info_s._fields_ = [ - ('agent', hsa_agent_t), - ('virtual_address', ctypes.c_uint64), - ('fault_reason_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('agent', hsa_agent_t), + ('virtual_address', uint64_t), + ('fault_reason_mask', uint32_t), ] - hsa_amd_gpu_memory_fault_info_t = struct_hsa_amd_gpu_memory_fault_info_s +hsa_amd_hw_exception_reset_type_t = CEnum(ctypes.c_uint32) +HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER = hsa_amd_hw_exception_reset_type_t.define('HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER', 1) -# values for enumeration 'c__EA_hsa_amd_hw_exception_reset_type_t' -c__EA_hsa_amd_hw_exception_reset_type_t__enumvalues = { - 1: 'HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER', -} -HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER = 1 -c__EA_hsa_amd_hw_exception_reset_type_t = ctypes.c_uint32 # enum -hsa_amd_hw_exception_reset_type_t = c__EA_hsa_amd_hw_exception_reset_type_t -hsa_amd_hw_exception_reset_type_t__enumvalues = c__EA_hsa_amd_hw_exception_reset_type_t__enumvalues - -# values for enumeration 'c__EA_hsa_amd_hw_exception_reset_cause_t' -c__EA_hsa_amd_hw_exception_reset_cause_t__enumvalues = { - 1: 'HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG', - 2: 'HSA_AMD_HW_EXCEPTION_CAUSE_ECC', -} -HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG = 1 -HSA_AMD_HW_EXCEPTION_CAUSE_ECC = 2 -c__EA_hsa_amd_hw_exception_reset_cause_t = ctypes.c_uint32 # enum -hsa_amd_hw_exception_reset_cause_t = c__EA_hsa_amd_hw_exception_reset_cause_t -hsa_amd_hw_exception_reset_cause_t__enumvalues = c__EA_hsa_amd_hw_exception_reset_cause_t__enumvalues -class struct_hsa_amd_gpu_hw_exception_info_s(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('agent', hsa_agent_t), - ('reset_type', hsa_amd_hw_exception_reset_type_t), - ('reset_cause', hsa_amd_hw_exception_reset_cause_t), - ] +hsa_amd_hw_exception_reset_cause_t = CEnum(ctypes.c_uint32) +HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG = hsa_amd_hw_exception_reset_cause_t.define('HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG', 1) +HSA_AMD_HW_EXCEPTION_CAUSE_ECC = hsa_amd_hw_exception_reset_cause_t.define('HSA_AMD_HW_EXCEPTION_CAUSE_ECC', 2) +class struct_hsa_amd_gpu_hw_exception_info_s(Struct): pass +struct_hsa_amd_gpu_hw_exception_info_s._fields_ = [ + ('agent', hsa_agent_t), + ('reset_type', hsa_amd_hw_exception_reset_type_t), + ('reset_cause', hsa_amd_hw_exception_reset_cause_t), +] hsa_amd_gpu_hw_exception_info_t = struct_hsa_amd_gpu_hw_exception_info_s -class struct_hsa_amd_event_s(Structure): - pass - -class union_hsa_amd_event_s_0(Union): - pass - -union_hsa_amd_event_s_0._pack_ = 1 # source:False -union_hsa_amd_event_s_0._fields_ = [ - ('memory_fault', hsa_amd_gpu_memory_fault_info_t), - ('hw_exception', hsa_amd_gpu_hw_exception_info_t), - ('PADDING_0', ctypes.c_ubyte * 8), +class struct_hsa_amd_event_s(Struct): pass +class struct_hsa_amd_event_s_0(ctypes.Union): pass +struct_hsa_amd_event_s_0._fields_ = [ + ('memory_fault', hsa_amd_gpu_memory_fault_info_t), + ('hw_exception', hsa_amd_gpu_hw_exception_info_t), ] - -struct_hsa_amd_event_s._pack_ = 1 # source:False -struct_hsa_amd_event_s._anonymous_ = ('_0',) +struct_hsa_amd_event_s._anonymous_ = ['_0'] struct_hsa_amd_event_s._fields_ = [ - ('event_type', hsa_amd_event_type_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_hsa_amd_event_s_0), + ('event_type', hsa_amd_event_type_t), + ('_0', struct_hsa_amd_event_s_0), ] - hsa_amd_event_t = struct_hsa_amd_event_s -hsa_amd_system_event_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_hsa_amd_event_s), ctypes.POINTER(None)) -try: - hsa_amd_register_system_event_handler = _libraries['libhsa-runtime64.so'].hsa_amd_register_system_event_handler - hsa_amd_register_system_event_handler.restype = hsa_status_t - hsa_amd_register_system_event_handler.argtypes = [hsa_amd_system_event_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass +class const_struct_hsa_amd_event_s(Struct): pass +const_struct_hsa_amd_event_s._anonymous_ = ['_0'] +const_struct_hsa_amd_event_s._fields_ = [ + ('event_type', hsa_amd_event_type_t), + ('_0', struct_hsa_amd_event_s_0), +] +hsa_amd_system_event_callback_t = ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(const_struct_hsa_amd_event_s), ctypes.c_void_p) +# hsa_status_t hsa_amd_register_system_event_handler(hsa_amd_system_event_callback_t callback, void *data) +try: (hsa_amd_register_system_event_handler:=dll.hsa_amd_register_system_event_handler).restype, hsa_amd_register_system_event_handler.argtypes = hsa_status_t, [hsa_amd_system_event_callback_t, ctypes.c_void_p] +except AttributeError: pass -# values for enumeration 'hsa_amd_queue_priority_s' -hsa_amd_queue_priority_s__enumvalues = { - 0: 'HSA_AMD_QUEUE_PRIORITY_LOW', - 1: 'HSA_AMD_QUEUE_PRIORITY_NORMAL', - 2: 'HSA_AMD_QUEUE_PRIORITY_HIGH', -} -HSA_AMD_QUEUE_PRIORITY_LOW = 0 -HSA_AMD_QUEUE_PRIORITY_NORMAL = 1 -HSA_AMD_QUEUE_PRIORITY_HIGH = 2 -hsa_amd_queue_priority_s = ctypes.c_uint32 # enum -hsa_amd_queue_priority_t = hsa_amd_queue_priority_s -hsa_amd_queue_priority_t__enumvalues = hsa_amd_queue_priority_s__enumvalues -try: - hsa_amd_queue_set_priority = _libraries['libhsa-runtime64.so'].hsa_amd_queue_set_priority - hsa_amd_queue_set_priority.restype = hsa_status_t - hsa_amd_queue_set_priority.argtypes = [ctypes.POINTER(struct_hsa_queue_s), hsa_amd_queue_priority_t] -except AttributeError: - pass -hsa_amd_deallocation_callback_t = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None)) -try: - hsa_amd_register_deallocation_callback = _libraries['libhsa-runtime64.so'].hsa_amd_register_deallocation_callback - hsa_amd_register_deallocation_callback.restype = hsa_status_t - hsa_amd_register_deallocation_callback.argtypes = [ctypes.POINTER(None), hsa_amd_deallocation_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_deregister_deallocation_callback = _libraries['libhsa-runtime64.so'].hsa_amd_deregister_deallocation_callback - hsa_amd_deregister_deallocation_callback.restype = hsa_status_t - hsa_amd_deregister_deallocation_callback.argtypes = [ctypes.POINTER(None), hsa_amd_deallocation_callback_t] -except AttributeError: - pass +enum_hsa_amd_queue_priority_s = CEnum(ctypes.c_uint32) +HSA_AMD_QUEUE_PRIORITY_LOW = enum_hsa_amd_queue_priority_s.define('HSA_AMD_QUEUE_PRIORITY_LOW', 0) +HSA_AMD_QUEUE_PRIORITY_NORMAL = enum_hsa_amd_queue_priority_s.define('HSA_AMD_QUEUE_PRIORITY_NORMAL', 1) +HSA_AMD_QUEUE_PRIORITY_HIGH = enum_hsa_amd_queue_priority_s.define('HSA_AMD_QUEUE_PRIORITY_HIGH', 2) -# values for enumeration 'hsa_amd_svm_model_s' -hsa_amd_svm_model_s__enumvalues = { - 0: 'HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED', - 1: 'HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED', - 2: 'HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE', -} -HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED = 0 -HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED = 1 -HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE = 2 -hsa_amd_svm_model_s = ctypes.c_uint32 # enum -hsa_amd_svm_model_t = hsa_amd_svm_model_s -hsa_amd_svm_model_t__enumvalues = hsa_amd_svm_model_s__enumvalues +hsa_amd_queue_priority_t = enum_hsa_amd_queue_priority_s +# hsa_status_t hsa_amd_queue_set_priority(hsa_queue_t *queue, hsa_amd_queue_priority_t priority) +try: (hsa_amd_queue_set_priority:=dll.hsa_amd_queue_set_priority).restype, hsa_amd_queue_set_priority.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t), hsa_amd_queue_priority_t] +except AttributeError: pass -# values for enumeration 'hsa_amd_svm_attribute_s' -hsa_amd_svm_attribute_s__enumvalues = { - 0: 'HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG', - 1: 'HSA_AMD_SVM_ATTRIB_READ_ONLY', - 2: 'HSA_AMD_SVM_ATTRIB_HIVE_LOCAL', - 3: 'HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY', - 4: 'HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION', - 5: 'HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION', - 6: 'HSA_AMD_SVM_ATTRIB_READ_MOSTLY', - 7: 'HSA_AMD_SVM_ATTRIB_GPU_EXEC', - 512: 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE', - 513: 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE', - 514: 'HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS', - 515: 'HSA_AMD_SVM_ATTRIB_ACCESS_QUERY', -} -HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG = 0 -HSA_AMD_SVM_ATTRIB_READ_ONLY = 1 -HSA_AMD_SVM_ATTRIB_HIVE_LOCAL = 2 -HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY = 3 -HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION = 4 -HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION = 5 -HSA_AMD_SVM_ATTRIB_READ_MOSTLY = 6 -HSA_AMD_SVM_ATTRIB_GPU_EXEC = 7 -HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE = 512 -HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE = 513 -HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS = 514 -HSA_AMD_SVM_ATTRIB_ACCESS_QUERY = 515 -hsa_amd_svm_attribute_s = ctypes.c_uint32 # enum -hsa_amd_svm_attribute_t = hsa_amd_svm_attribute_s -hsa_amd_svm_attribute_t__enumvalues = hsa_amd_svm_attribute_s__enumvalues -class struct_hsa_amd_svm_attribute_pair_s(Structure): - pass +hsa_amd_deallocation_callback_t = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_void_p) +# hsa_status_t hsa_amd_register_deallocation_callback(void *ptr, hsa_amd_deallocation_callback_t callback, void *user_data) +try: (hsa_amd_register_deallocation_callback:=dll.hsa_amd_register_deallocation_callback).restype, hsa_amd_register_deallocation_callback.argtypes = hsa_status_t, [ctypes.c_void_p, hsa_amd_deallocation_callback_t, ctypes.c_void_p] +except AttributeError: pass -struct_hsa_amd_svm_attribute_pair_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_deregister_deallocation_callback(void *ptr, hsa_amd_deallocation_callback_t callback) +try: (hsa_amd_deregister_deallocation_callback:=dll.hsa_amd_deregister_deallocation_callback).restype, hsa_amd_deregister_deallocation_callback.argtypes = hsa_status_t, [ctypes.c_void_p, hsa_amd_deallocation_callback_t] +except AttributeError: pass + +enum_hsa_amd_svm_model_s = CEnum(ctypes.c_uint32) +HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED = enum_hsa_amd_svm_model_s.define('HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED', 0) +HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED = enum_hsa_amd_svm_model_s.define('HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED', 1) +HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE = enum_hsa_amd_svm_model_s.define('HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE', 2) + +hsa_amd_svm_model_t = enum_hsa_amd_svm_model_s +enum_hsa_amd_svm_attribute_s = CEnum(ctypes.c_uint32) +HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG', 0) +HSA_AMD_SVM_ATTRIB_READ_ONLY = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_READ_ONLY', 1) +HSA_AMD_SVM_ATTRIB_HIVE_LOCAL = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_HIVE_LOCAL', 2) +HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY', 3) +HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION', 4) +HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION', 5) +HSA_AMD_SVM_ATTRIB_READ_MOSTLY = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_READ_MOSTLY', 6) +HSA_AMD_SVM_ATTRIB_GPU_EXEC = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_GPU_EXEC', 7) +HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE', 512) +HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE', 513) +HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS', 514) +HSA_AMD_SVM_ATTRIB_ACCESS_QUERY = enum_hsa_amd_svm_attribute_s.define('HSA_AMD_SVM_ATTRIB_ACCESS_QUERY', 515) + +hsa_amd_svm_attribute_t = enum_hsa_amd_svm_attribute_s +class struct_hsa_amd_svm_attribute_pair_s(Struct): pass struct_hsa_amd_svm_attribute_pair_s._fields_ = [ - ('attribute', ctypes.c_uint64), - ('value', ctypes.c_uint64), + ('attribute', uint64_t), + ('value', uint64_t), ] - hsa_amd_svm_attribute_pair_t = struct_hsa_amd_svm_attribute_pair_s -try: - hsa_amd_svm_attributes_set = _libraries['libhsa-runtime64.so'].hsa_amd_svm_attributes_set - hsa_amd_svm_attributes_set.restype = hsa_status_t - hsa_amd_svm_attributes_set.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_svm_attribute_pair_s), size_t] -except AttributeError: - pass -try: - hsa_amd_svm_attributes_get = _libraries['libhsa-runtime64.so'].hsa_amd_svm_attributes_get - hsa_amd_svm_attributes_get.restype = hsa_status_t - hsa_amd_svm_attributes_get.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_svm_attribute_pair_s), size_t] -except AttributeError: - pass -try: - hsa_amd_svm_prefetch_async = _libraries['libhsa-runtime64.so'].hsa_amd_svm_prefetch_async - hsa_amd_svm_prefetch_async.restype = hsa_status_t - hsa_amd_svm_prefetch_async.argtypes = [ctypes.POINTER(None), size_t, hsa_agent_t, uint32_t, ctypes.POINTER(struct_hsa_signal_s), hsa_signal_t] -except AttributeError: - pass -try: - hsa_amd_spm_acquire = _libraries['libhsa-runtime64.so'].hsa_amd_spm_acquire - hsa_amd_spm_acquire.restype = hsa_status_t - hsa_amd_spm_acquire.argtypes = [hsa_agent_t] -except AttributeError: - pass -try: - hsa_amd_spm_release = _libraries['libhsa-runtime64.so'].hsa_amd_spm_release - hsa_amd_spm_release.restype = hsa_status_t - hsa_amd_spm_release.argtypes = [hsa_agent_t] -except AttributeError: - pass -try: - hsa_amd_spm_set_dest_buffer = _libraries['libhsa-runtime64.so'].hsa_amd_spm_set_dest_buffer - hsa_amd_spm_set_dest_buffer.restype = hsa_status_t - hsa_amd_spm_set_dest_buffer.argtypes = [hsa_agent_t, size_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -try: - hsa_amd_portable_export_dmabuf = _libraries['libhsa-runtime64.so'].hsa_amd_portable_export_dmabuf - hsa_amd_portable_export_dmabuf.restype = hsa_status_t - hsa_amd_portable_export_dmabuf.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - hsa_amd_portable_close_dmabuf = _libraries['libhsa-runtime64.so'].hsa_amd_portable_close_dmabuf - hsa_amd_portable_close_dmabuf.restype = hsa_status_t - hsa_amd_portable_close_dmabuf.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - hsa_amd_vmem_address_reserve = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_address_reserve - hsa_amd_vmem_address_reserve.restype = hsa_status_t - hsa_amd_vmem_address_reserve.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_address_reserve_align = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_address_reserve_align - hsa_amd_vmem_address_reserve_align.restype = hsa_status_t - hsa_amd_vmem_address_reserve_align.argtypes = [ctypes.POINTER(ctypes.POINTER(None)), size_t, uint64_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_address_free = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_address_free - hsa_amd_vmem_address_free.restype = hsa_status_t - hsa_amd_vmem_address_free.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_hsa_amd_vmem_alloc_handle_s(Structure): - pass +# hsa_status_t hsa_amd_svm_attributes_set(void *ptr, size_t size, hsa_amd_svm_attribute_pair_t *attribute_list, size_t attribute_count) +try: (hsa_amd_svm_attributes_set:=dll.hsa_amd_svm_attributes_set).restype, hsa_amd_svm_attributes_set.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_amd_svm_attribute_pair_t), size_t] +except AttributeError: pass -struct_hsa_amd_vmem_alloc_handle_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_svm_attributes_get(void *ptr, size_t size, hsa_amd_svm_attribute_pair_t *attribute_list, size_t attribute_count) +try: (hsa_amd_svm_attributes_get:=dll.hsa_amd_svm_attributes_get).restype, hsa_amd_svm_attributes_get.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_amd_svm_attribute_pair_t), size_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_svm_prefetch_async(void *ptr, size_t size, hsa_agent_t agent, uint32_t num_dep_signals, const hsa_signal_t *dep_signals, hsa_signal_t completion_signal) +try: (hsa_amd_svm_prefetch_async:=dll.hsa_amd_svm_prefetch_async).restype, hsa_amd_svm_prefetch_async.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, hsa_agent_t, uint32_t, ctypes.POINTER(hsa_signal_t), hsa_signal_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_spm_acquire(hsa_agent_t preferred_agent) +try: (hsa_amd_spm_acquire:=dll.hsa_amd_spm_acquire).restype, hsa_amd_spm_acquire.argtypes = hsa_status_t, [hsa_agent_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_spm_release(hsa_agent_t preferred_agent) +try: (hsa_amd_spm_release:=dll.hsa_amd_spm_release).restype, hsa_amd_spm_release.argtypes = hsa_status_t, [hsa_agent_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_spm_set_dest_buffer(hsa_agent_t preferred_agent, size_t size_in_bytes, uint32_t *timeout, uint32_t *size_copied, void *dest, bool *is_data_loss) +try: (hsa_amd_spm_set_dest_buffer:=dll.hsa_amd_spm_set_dest_buffer).restype, hsa_amd_spm_set_dest_buffer.argtypes = hsa_status_t, [hsa_agent_t, size_t, ctypes.POINTER(uint32_t), ctypes.POINTER(uint32_t), ctypes.c_void_p, ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass + +# hsa_status_t hsa_amd_portable_export_dmabuf(const void *ptr, size_t size, int *dmabuf, uint64_t *offset) +try: (hsa_amd_portable_export_dmabuf:=dll.hsa_amd_portable_export_dmabuf).restype, hsa_amd_portable_export_dmabuf.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(uint64_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_portable_close_dmabuf(int dmabuf) +try: (hsa_amd_portable_close_dmabuf:=dll.hsa_amd_portable_close_dmabuf).restype, hsa_amd_portable_close_dmabuf.argtypes = hsa_status_t, [ctypes.c_int32] +except AttributeError: pass + +# hsa_status_t hsa_amd_vmem_address_reserve(void **va, size_t size, uint64_t address, uint64_t flags) +try: (hsa_amd_vmem_address_reserve:=dll.hsa_amd_vmem_address_reserve).restype, hsa_amd_vmem_address_reserve.argtypes = hsa_status_t, [ctypes.POINTER(ctypes.c_void_p), size_t, uint64_t, uint64_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_vmem_address_reserve_align(void **va, size_t size, uint64_t address, uint64_t alignment, uint64_t flags) +try: (hsa_amd_vmem_address_reserve_align:=dll.hsa_amd_vmem_address_reserve_align).restype, hsa_amd_vmem_address_reserve_align.argtypes = hsa_status_t, [ctypes.POINTER(ctypes.c_void_p), size_t, uint64_t, uint64_t, uint64_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_vmem_address_free(void *va, size_t size) +try: (hsa_amd_vmem_address_free:=dll.hsa_amd_vmem_address_free).restype, hsa_amd_vmem_address_free.argtypes = hsa_status_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +class struct_hsa_amd_vmem_alloc_handle_s(Struct): pass struct_hsa_amd_vmem_alloc_handle_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_amd_vmem_alloc_handle_t = struct_hsa_amd_vmem_alloc_handle_s +hsa_amd_memory_type_t = CEnum(ctypes.c_uint32) +MEMORY_TYPE_NONE = hsa_amd_memory_type_t.define('MEMORY_TYPE_NONE', 0) +MEMORY_TYPE_PINNED = hsa_amd_memory_type_t.define('MEMORY_TYPE_PINNED', 1) -# values for enumeration 'c__EA_hsa_amd_memory_type_t' -c__EA_hsa_amd_memory_type_t__enumvalues = { - 0: 'MEMORY_TYPE_NONE', - 1: 'MEMORY_TYPE_PINNED', -} -MEMORY_TYPE_NONE = 0 -MEMORY_TYPE_PINNED = 1 -c__EA_hsa_amd_memory_type_t = ctypes.c_uint32 # enum -hsa_amd_memory_type_t = c__EA_hsa_amd_memory_type_t -hsa_amd_memory_type_t__enumvalues = c__EA_hsa_amd_memory_type_t__enumvalues -try: - hsa_amd_vmem_handle_create = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_handle_create - hsa_amd_vmem_handle_create.restype = hsa_status_t - hsa_amd_vmem_handle_create.argtypes = [hsa_amd_memory_pool_t, size_t, hsa_amd_memory_type_t, uint64_t, ctypes.POINTER(struct_hsa_amd_vmem_alloc_handle_s)] -except AttributeError: - pass -try: - hsa_amd_vmem_handle_release = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_handle_release - hsa_amd_vmem_handle_release.restype = hsa_status_t - hsa_amd_vmem_handle_release.argtypes = [hsa_amd_vmem_alloc_handle_t] -except AttributeError: - pass -try: - hsa_amd_vmem_map = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_map - hsa_amd_vmem_map.restype = hsa_status_t - hsa_amd_vmem_map.argtypes = [ctypes.POINTER(None), size_t, size_t, hsa_amd_vmem_alloc_handle_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_unmap = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_unmap - hsa_amd_vmem_unmap.restype = hsa_status_t - hsa_amd_vmem_unmap.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_hsa_amd_memory_access_desc_s(Structure): - pass +# hsa_status_t hsa_amd_vmem_handle_create(hsa_amd_memory_pool_t pool, size_t size, hsa_amd_memory_type_t type, uint64_t flags, hsa_amd_vmem_alloc_handle_t *memory_handle) +try: (hsa_amd_vmem_handle_create:=dll.hsa_amd_vmem_handle_create).restype, hsa_amd_vmem_handle_create.argtypes = hsa_status_t, [hsa_amd_memory_pool_t, size_t, hsa_amd_memory_type_t, uint64_t, ctypes.POINTER(hsa_amd_vmem_alloc_handle_t)] +except AttributeError: pass -struct_hsa_amd_memory_access_desc_s._pack_ = 1 # source:False +# hsa_status_t hsa_amd_vmem_handle_release(hsa_amd_vmem_alloc_handle_t memory_handle) +try: (hsa_amd_vmem_handle_release:=dll.hsa_amd_vmem_handle_release).restype, hsa_amd_vmem_handle_release.argtypes = hsa_status_t, [hsa_amd_vmem_alloc_handle_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_vmem_map(void *va, size_t size, size_t in_offset, hsa_amd_vmem_alloc_handle_t memory_handle, uint64_t flags) +try: (hsa_amd_vmem_map:=dll.hsa_amd_vmem_map).restype, hsa_amd_vmem_map.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, size_t, hsa_amd_vmem_alloc_handle_t, uint64_t] +except AttributeError: pass + +# hsa_status_t hsa_amd_vmem_unmap(void *va, size_t size) +try: (hsa_amd_vmem_unmap:=dll.hsa_amd_vmem_unmap).restype, hsa_amd_vmem_unmap.argtypes = hsa_status_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +class struct_hsa_amd_memory_access_desc_s(Struct): pass struct_hsa_amd_memory_access_desc_s._fields_ = [ - ('permissions', hsa_access_permission_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('agent_handle', hsa_agent_t), + ('permissions', hsa_access_permission_t), + ('agent_handle', hsa_agent_t), ] - hsa_amd_memory_access_desc_t = struct_hsa_amd_memory_access_desc_s -try: - hsa_amd_vmem_set_access = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_set_access - hsa_amd_vmem_set_access.restype = hsa_status_t - hsa_amd_vmem_set_access.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(struct_hsa_amd_memory_access_desc_s), size_t] -except AttributeError: - pass -try: - hsa_amd_vmem_get_access = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_get_access - hsa_amd_vmem_get_access.restype = hsa_status_t - hsa_amd_vmem_get_access.argtypes = [ctypes.POINTER(None), ctypes.POINTER(c__EA_hsa_access_permission_t), hsa_agent_t] -except AttributeError: - pass -try: - hsa_amd_vmem_export_shareable_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_export_shareable_handle - hsa_amd_vmem_export_shareable_handle.restype = hsa_status_t - hsa_amd_vmem_export_shareable_handle.argtypes = [ctypes.POINTER(ctypes.c_int32), hsa_amd_vmem_alloc_handle_t, uint64_t] -except AttributeError: - pass -try: - hsa_amd_vmem_import_shareable_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_import_shareable_handle - hsa_amd_vmem_import_shareable_handle.restype = hsa_status_t - hsa_amd_vmem_import_shareable_handle.argtypes = [ctypes.c_int32, ctypes.POINTER(struct_hsa_amd_vmem_alloc_handle_s)] -except AttributeError: - pass -try: - hsa_amd_vmem_retain_alloc_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_retain_alloc_handle - hsa_amd_vmem_retain_alloc_handle.restype = hsa_status_t - hsa_amd_vmem_retain_alloc_handle.argtypes = [ctypes.POINTER(struct_hsa_amd_vmem_alloc_handle_s), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_amd_vmem_get_alloc_properties_from_handle = _libraries['libhsa-runtime64.so'].hsa_amd_vmem_get_alloc_properties_from_handle - hsa_amd_vmem_get_alloc_properties_from_handle.restype = hsa_status_t - hsa_amd_vmem_get_alloc_properties_from_handle.argtypes = [hsa_amd_vmem_alloc_handle_t, ctypes.POINTER(struct_hsa_amd_memory_pool_s), ctypes.POINTER(c__EA_hsa_amd_memory_type_t)] -except AttributeError: - pass -try: - hsa_amd_agent_set_async_scratch_limit = _libraries['libhsa-runtime64.so'].hsa_amd_agent_set_async_scratch_limit - hsa_amd_agent_set_async_scratch_limit.restype = hsa_status_t - hsa_amd_agent_set_async_scratch_limit.argtypes = [hsa_agent_t, size_t] -except AttributeError: - pass +# hsa_status_t hsa_amd_vmem_set_access(void *va, size_t size, const hsa_amd_memory_access_desc_t *desc, size_t desc_cnt) +try: (hsa_amd_vmem_set_access:=dll.hsa_amd_vmem_set_access).restype, hsa_amd_vmem_set_access.argtypes = hsa_status_t, [ctypes.c_void_p, size_t, ctypes.POINTER(hsa_amd_memory_access_desc_t), size_t] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_queue_info_attribute_t' -c__EA_hsa_queue_info_attribute_t__enumvalues = { - 0: 'HSA_AMD_QUEUE_INFO_AGENT', - 1: 'HSA_AMD_QUEUE_INFO_DOORBELL_ID', -} -HSA_AMD_QUEUE_INFO_AGENT = 0 -HSA_AMD_QUEUE_INFO_DOORBELL_ID = 1 -c__EA_hsa_queue_info_attribute_t = ctypes.c_uint32 # enum -hsa_queue_info_attribute_t = c__EA_hsa_queue_info_attribute_t -hsa_queue_info_attribute_t__enumvalues = c__EA_hsa_queue_info_attribute_t__enumvalues -try: - hsa_amd_queue_get_info = _libraries['libhsa-runtime64.so'].hsa_amd_queue_get_info - hsa_amd_queue_get_info.restype = hsa_status_t - hsa_amd_queue_get_info.argtypes = [ctypes.POINTER(struct_hsa_queue_s), hsa_queue_info_attribute_t, ctypes.POINTER(None)] -except AttributeError: - pass -amd_queue_properties32_t = ctypes.c_uint32 +# hsa_status_t hsa_amd_vmem_get_access(void *va, hsa_access_permission_t *perms, hsa_agent_t agent_handle) +try: (hsa_amd_vmem_get_access:=dll.hsa_amd_vmem_get_access).restype, hsa_amd_vmem_get_access.argtypes = hsa_status_t, [ctypes.c_void_p, ctypes.POINTER(hsa_access_permission_t), hsa_agent_t] +except AttributeError: pass -# values for enumeration 'amd_queue_properties_t' -amd_queue_properties_t__enumvalues = { - 0: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER', - 1: 'AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH', - 2: 'AMD_QUEUE_PROPERTIES_IS_PTR64', - 2: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH', - 4: 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS', - 3: 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH', - 8: 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING', - 4: 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT', - 1: 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH', - 16: 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE', - 5: 'AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT', - 27: 'AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH', - -32: 'AMD_QUEUE_PROPERTIES_RESERVED1', -} -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT = 0 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH = 1 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER = 1 -AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT = 1 -AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH = 1 -AMD_QUEUE_PROPERTIES_IS_PTR64 = 2 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT = 2 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH = 1 -AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS = 4 -AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT = 3 -AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH = 1 -AMD_QUEUE_PROPERTIES_ENABLE_PROFILING = 8 -AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT = 4 -AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH = 1 -AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE = 16 -AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT = 5 -AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH = 27 -AMD_QUEUE_PROPERTIES_RESERVED1 = -32 -amd_queue_properties_t = ctypes.c_int32 # enum -amd_queue_capabilities32_t = ctypes.c_uint32 +# hsa_status_t hsa_amd_vmem_export_shareable_handle(int *dmabuf_fd, hsa_amd_vmem_alloc_handle_t handle, uint64_t flags) +try: (hsa_amd_vmem_export_shareable_handle:=dll.hsa_amd_vmem_export_shareable_handle).restype, hsa_amd_vmem_export_shareable_handle.argtypes = hsa_status_t, [ctypes.POINTER(ctypes.c_int32), hsa_amd_vmem_alloc_handle_t, uint64_t] +except AttributeError: pass -# values for enumeration 'amd_queue_capabilities_t' -amd_queue_capabilities_t__enumvalues = { - 0: 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT', - 1: 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH', - 1: 'AMD_QUEUE_CAPS_ASYNC_RECLAIM', -} -AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT = 0 -AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH = 1 -AMD_QUEUE_CAPS_ASYNC_RECLAIM = 1 -amd_queue_capabilities_t = ctypes.c_uint32 # enum -class struct_amd_queue_s(Structure): - pass +# hsa_status_t hsa_amd_vmem_import_shareable_handle(int dmabuf_fd, hsa_amd_vmem_alloc_handle_t *handle) +try: (hsa_amd_vmem_import_shareable_handle:=dll.hsa_amd_vmem_import_shareable_handle).restype, hsa_amd_vmem_import_shareable_handle.argtypes = hsa_status_t, [ctypes.c_int32, ctypes.POINTER(hsa_amd_vmem_alloc_handle_t)] +except AttributeError: pass -struct_amd_queue_s._pack_ = 1 # source:False -struct_amd_queue_s._fields_ = [ - ('hsa_queue', hsa_queue_t), - ('caps', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32 * 3), - ('write_dispatch_id', ctypes.c_uint64), - ('group_segment_aperture_base_hi', ctypes.c_uint32), - ('private_segment_aperture_base_hi', ctypes.c_uint32), - ('max_cu_id', ctypes.c_uint32), - ('max_wave_id', ctypes.c_uint32), - ('max_legacy_doorbell_dispatch_id_plus_1', ctypes.c_uint64), - ('legacy_doorbell_lock', ctypes.c_uint32), - ('reserved2', ctypes.c_uint32 * 9), - ('read_dispatch_id', ctypes.c_uint64), - ('read_dispatch_id_field_base_byte_offset', ctypes.c_uint32), - ('compute_tmpring_size', ctypes.c_uint32), - ('scratch_resource_descriptor', ctypes.c_uint32 * 4), - ('scratch_backing_memory_location', ctypes.c_uint64), - ('scratch_backing_memory_byte_size', ctypes.c_uint64), - ('scratch_wave64_lane_byte_size', ctypes.c_uint32), - ('queue_properties', ctypes.c_uint32), - ('scratch_last_used_index', ctypes.c_uint64), - ('queue_inactive_signal', hsa_signal_t), - ('reserved4', ctypes.c_uint32 * 2), - ('alt_scratch_last_used_index', ctypes.c_uint64), - ('alt_scratch_backing_memory_location', ctypes.c_uint64), - ('alt_scratch_backing_memory_byte_size', ctypes.c_uint64), - ('alt_scratch_dispatch_limit_x', ctypes.c_uint32), - ('alt_scratch_dispatch_limit_y', ctypes.c_uint32), - ('alt_scratch_dispatch_limit_z', ctypes.c_uint32), - ('alt_scratch_wave64_lane_byte_size', ctypes.c_uint32), - ('alt_compute_tmpring_size', ctypes.c_uint32), - ('reserved5', ctypes.c_uint32), -] +# hsa_status_t hsa_amd_vmem_retain_alloc_handle(hsa_amd_vmem_alloc_handle_t *memory_handle, void *addr) +try: (hsa_amd_vmem_retain_alloc_handle:=dll.hsa_amd_vmem_retain_alloc_handle).restype, hsa_amd_vmem_retain_alloc_handle.argtypes = hsa_status_t, [ctypes.POINTER(hsa_amd_vmem_alloc_handle_t), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_amd_vmem_get_alloc_properties_from_handle(hsa_amd_vmem_alloc_handle_t memory_handle, hsa_amd_memory_pool_t *pool, hsa_amd_memory_type_t *type) +try: (hsa_amd_vmem_get_alloc_properties_from_handle:=dll.hsa_amd_vmem_get_alloc_properties_from_handle).restype, hsa_amd_vmem_get_alloc_properties_from_handle.argtypes = hsa_status_t, [hsa_amd_vmem_alloc_handle_t, ctypes.POINTER(hsa_amd_memory_pool_t), ctypes.POINTER(hsa_amd_memory_type_t)] +except AttributeError: pass + +# hsa_status_t hsa_amd_agent_set_async_scratch_limit(hsa_agent_t agent, size_t threshold) +try: (hsa_amd_agent_set_async_scratch_limit:=dll.hsa_amd_agent_set_async_scratch_limit).restype, hsa_amd_agent_set_async_scratch_limit.argtypes = hsa_status_t, [hsa_agent_t, size_t] +except AttributeError: pass + +hsa_queue_info_attribute_t = CEnum(ctypes.c_uint32) +HSA_AMD_QUEUE_INFO_AGENT = hsa_queue_info_attribute_t.define('HSA_AMD_QUEUE_INFO_AGENT', 0) +HSA_AMD_QUEUE_INFO_DOORBELL_ID = hsa_queue_info_attribute_t.define('HSA_AMD_QUEUE_INFO_DOORBELL_ID', 1) + +# hsa_status_t hsa_amd_queue_get_info(hsa_queue_t *queue, hsa_queue_info_attribute_t attribute, void *value) +try: (hsa_amd_queue_get_info:=dll.hsa_amd_queue_get_info).restype, hsa_amd_queue_get_info.argtypes = hsa_status_t, [ctypes.POINTER(hsa_queue_t), hsa_queue_info_attribute_t, ctypes.c_void_p] +except AttributeError: pass -amd_queue_t = struct_amd_queue_s amd_signal_kind64_t = ctypes.c_int64 +enum_amd_signal_kind_t = CEnum(ctypes.c_int32) +AMD_SIGNAL_KIND_INVALID = enum_amd_signal_kind_t.define('AMD_SIGNAL_KIND_INVALID', 0) +AMD_SIGNAL_KIND_USER = enum_amd_signal_kind_t.define('AMD_SIGNAL_KIND_USER', 1) +AMD_SIGNAL_KIND_DOORBELL = enum_amd_signal_kind_t.define('AMD_SIGNAL_KIND_DOORBELL', -1) +AMD_SIGNAL_KIND_LEGACY_DOORBELL = enum_amd_signal_kind_t.define('AMD_SIGNAL_KIND_LEGACY_DOORBELL', -2) -# values for enumeration 'amd_signal_kind_t' -amd_signal_kind_t__enumvalues = { - 0: 'AMD_SIGNAL_KIND_INVALID', - 1: 'AMD_SIGNAL_KIND_USER', - -1: 'AMD_SIGNAL_KIND_DOORBELL', - -2: 'AMD_SIGNAL_KIND_LEGACY_DOORBELL', -} -AMD_SIGNAL_KIND_INVALID = 0 -AMD_SIGNAL_KIND_USER = 1 -AMD_SIGNAL_KIND_DOORBELL = -1 -AMD_SIGNAL_KIND_LEGACY_DOORBELL = -2 -amd_signal_kind_t = ctypes.c_int32 # enum -class struct_amd_signal_s(Structure): - pass - -class union_amd_signal_s_0(Union): - pass - -union_amd_signal_s_0._pack_ = 1 # source:False -union_amd_signal_s_0._fields_ = [ - ('value', ctypes.c_int64), - ('legacy_hardware_doorbell_ptr', ctypes.POINTER(ctypes.c_uint32)), - ('hardware_doorbell_ptr', ctypes.POINTER(ctypes.c_uint64)), +class struct_amd_signal_s(Struct): pass +class struct_amd_signal_s_0(ctypes.Union): pass +int64_t = ctypes.c_int64 +struct_amd_signal_s_0._fields_ = [ + ('value', int64_t), + ('legacy_hardware_doorbell_ptr', ctypes.POINTER(uint32_t)), + ('hardware_doorbell_ptr', ctypes.POINTER(uint64_t)), ] - -class union_amd_signal_s_1(Union): - pass - -union_amd_signal_s_1._pack_ = 1 # source:False -union_amd_signal_s_1._fields_ = [ - ('queue_ptr', ctypes.POINTER(struct_amd_queue_s)), - ('reserved2', ctypes.c_uint64), +class struct_amd_signal_s_1(ctypes.Union): pass +class struct_amd_queue_s(Struct): pass +amd_queue_t = struct_amd_queue_s +amd_queue_properties32_t = ctypes.c_uint32 +struct_amd_queue_s._fields_ = [ + ('hsa_queue', hsa_queue_t), + ('caps', uint32_t), + ('reserved1', (uint32_t * 3)), + ('write_dispatch_id', uint64_t), + ('group_segment_aperture_base_hi', uint32_t), + ('private_segment_aperture_base_hi', uint32_t), + ('max_cu_id', uint32_t), + ('max_wave_id', uint32_t), + ('max_legacy_doorbell_dispatch_id_plus_1', uint64_t), + ('legacy_doorbell_lock', uint32_t), + ('reserved2', (uint32_t * 9)), + ('read_dispatch_id', uint64_t), + ('read_dispatch_id_field_base_byte_offset', uint32_t), + ('compute_tmpring_size', uint32_t), + ('scratch_resource_descriptor', (uint32_t * 4)), + ('scratch_backing_memory_location', uint64_t), + ('scratch_backing_memory_byte_size', uint64_t), + ('scratch_wave64_lane_byte_size', uint32_t), + ('queue_properties', amd_queue_properties32_t), + ('scratch_last_used_index', uint64_t), + ('queue_inactive_signal', hsa_signal_t), + ('reserved4', (uint32_t * 2)), + ('alt_scratch_last_used_index', uint64_t), + ('alt_scratch_backing_memory_location', uint64_t), + ('alt_scratch_backing_memory_byte_size', uint64_t), + ('alt_scratch_dispatch_limit_x', uint32_t), + ('alt_scratch_dispatch_limit_y', uint32_t), + ('alt_scratch_dispatch_limit_z', uint32_t), + ('alt_scratch_wave64_lane_byte_size', uint32_t), + ('alt_compute_tmpring_size', uint32_t), + ('reserved5', uint32_t), ] - -struct_amd_signal_s._pack_ = 1 # source:False -struct_amd_signal_s._anonymous_ = ('_0', '_1',) +struct_amd_signal_s_1._fields_ = [ + ('queue_ptr', ctypes.POINTER(amd_queue_t)), + ('reserved2', uint64_t), +] +struct_amd_signal_s._anonymous_ = ['_0', '_1'] struct_amd_signal_s._fields_ = [ - ('kind', ctypes.c_int64), - ('_0', union_amd_signal_s_0), - ('event_mailbox_ptr', ctypes.c_uint64), - ('event_id', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('start_ts', ctypes.c_uint64), - ('end_ts', ctypes.c_uint64), - ('_1', union_amd_signal_s_1), - ('reserved3', ctypes.c_uint32 * 2), + ('kind', amd_signal_kind64_t), + ('_0', struct_amd_signal_s_0), + ('event_mailbox_ptr', uint64_t), + ('event_id', uint32_t), + ('reserved1', uint32_t), + ('start_ts', uint64_t), + ('end_ts', uint64_t), + ('_1', struct_amd_signal_s_1), + ('reserved3', (uint32_t * 2)), ] - amd_signal_t = struct_amd_signal_s +enum_amd_queue_properties_t = CEnum(ctypes.c_int32) +AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT', 0) +AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH', 1) +AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER', 1) +AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT', 1) +AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH', 1) +AMD_QUEUE_PROPERTIES_IS_PTR64 = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_IS_PTR64', 2) +AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT', 2) +AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH', 1) +AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS', 4) +AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT', 3) +AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH', 1) +AMD_QUEUE_PROPERTIES_ENABLE_PROFILING = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_ENABLE_PROFILING', 8) +AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT', 4) +AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH', 1) +AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE', 16) +AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT', 5) +AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH', 27) +AMD_QUEUE_PROPERTIES_RESERVED1 = enum_amd_queue_properties_t.define('AMD_QUEUE_PROPERTIES_RESERVED1', -32) + +amd_queue_capabilities32_t = ctypes.c_uint32 +enum_amd_queue_capabilities_t = CEnum(ctypes.c_uint32) +AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT = enum_amd_queue_capabilities_t.define('AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT', 0) +AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH = enum_amd_queue_capabilities_t.define('AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH', 1) +AMD_QUEUE_CAPS_ASYNC_RECLAIM = enum_amd_queue_capabilities_t.define('AMD_QUEUE_CAPS_ASYNC_RECLAIM', 1) + amd_kernel_code_version32_t = ctypes.c_uint32 +enum_amd_kernel_code_version_t = CEnum(ctypes.c_uint32) +AMD_KERNEL_CODE_VERSION_MAJOR = enum_amd_kernel_code_version_t.define('AMD_KERNEL_CODE_VERSION_MAJOR', 1) +AMD_KERNEL_CODE_VERSION_MINOR = enum_amd_kernel_code_version_t.define('AMD_KERNEL_CODE_VERSION_MINOR', 1) -# values for enumeration 'amd_kernel_code_version_t' -amd_kernel_code_version_t__enumvalues = { - 1: 'AMD_KERNEL_CODE_VERSION_MAJOR', - 1: 'AMD_KERNEL_CODE_VERSION_MINOR', -} -AMD_KERNEL_CODE_VERSION_MAJOR = 1 -AMD_KERNEL_CODE_VERSION_MINOR = 1 -amd_kernel_code_version_t = ctypes.c_uint32 # enum amd_machine_kind16_t = ctypes.c_uint16 +enum_amd_machine_kind_t = CEnum(ctypes.c_uint32) +AMD_MACHINE_KIND_UNDEFINED = enum_amd_machine_kind_t.define('AMD_MACHINE_KIND_UNDEFINED', 0) +AMD_MACHINE_KIND_AMDGPU = enum_amd_machine_kind_t.define('AMD_MACHINE_KIND_AMDGPU', 1) -# values for enumeration 'amd_machine_kind_t' -amd_machine_kind_t__enumvalues = { - 0: 'AMD_MACHINE_KIND_UNDEFINED', - 1: 'AMD_MACHINE_KIND_AMDGPU', -} -AMD_MACHINE_KIND_UNDEFINED = 0 -AMD_MACHINE_KIND_AMDGPU = 1 -amd_machine_kind_t = ctypes.c_uint32 # enum amd_machine_version16_t = ctypes.c_uint16 +enum_amd_float_round_mode_t = CEnum(ctypes.c_uint32) +AMD_FLOAT_ROUND_MODE_NEAREST_EVEN = enum_amd_float_round_mode_t.define('AMD_FLOAT_ROUND_MODE_NEAREST_EVEN', 0) +AMD_FLOAT_ROUND_MODE_PLUS_INFINITY = enum_amd_float_round_mode_t.define('AMD_FLOAT_ROUND_MODE_PLUS_INFINITY', 1) +AMD_FLOAT_ROUND_MODE_MINUS_INFINITY = enum_amd_float_round_mode_t.define('AMD_FLOAT_ROUND_MODE_MINUS_INFINITY', 2) +AMD_FLOAT_ROUND_MODE_ZERO = enum_amd_float_round_mode_t.define('AMD_FLOAT_ROUND_MODE_ZERO', 3) -# values for enumeration 'amd_float_round_mode_t' -amd_float_round_mode_t__enumvalues = { - 0: 'AMD_FLOAT_ROUND_MODE_NEAREST_EVEN', - 1: 'AMD_FLOAT_ROUND_MODE_PLUS_INFINITY', - 2: 'AMD_FLOAT_ROUND_MODE_MINUS_INFINITY', - 3: 'AMD_FLOAT_ROUND_MODE_ZERO', -} -AMD_FLOAT_ROUND_MODE_NEAREST_EVEN = 0 -AMD_FLOAT_ROUND_MODE_PLUS_INFINITY = 1 -AMD_FLOAT_ROUND_MODE_MINUS_INFINITY = 2 -AMD_FLOAT_ROUND_MODE_ZERO = 3 -amd_float_round_mode_t = ctypes.c_uint32 # enum +enum_amd_float_denorm_mode_t = CEnum(ctypes.c_uint32) +AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT = enum_amd_float_denorm_mode_t.define('AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT', 0) +AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT = enum_amd_float_denorm_mode_t.define('AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT', 1) +AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE = enum_amd_float_denorm_mode_t.define('AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE', 2) +AMD_FLOAT_DENORM_MODE_NO_FLUSH = enum_amd_float_denorm_mode_t.define('AMD_FLOAT_DENORM_MODE_NO_FLUSH', 3) -# values for enumeration 'amd_float_denorm_mode_t' -amd_float_denorm_mode_t__enumvalues = { - 0: 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT', - 1: 'AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT', - 2: 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE', - 3: 'AMD_FLOAT_DENORM_MODE_NO_FLUSH', -} -AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT = 0 -AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT = 1 -AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE = 2 -AMD_FLOAT_DENORM_MODE_NO_FLUSH = 3 -amd_float_denorm_mode_t = ctypes.c_uint32 # enum amd_compute_pgm_rsrc_one32_t = ctypes.c_uint32 +enum_amd_compute_pgm_rsrc_one_t = CEnum(ctypes.c_int32) +AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT', 0) +AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH', 6) +AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT', 63) +AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT', 6) +AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH', 4) +AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT', 960) +AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT', 10) +AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH', 2) +AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY', 3072) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT', 12) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH', 2) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32 = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32', 12288) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT', 14) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH', 2) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64 = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64', 49152) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT', 16) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH', 2) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32 = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32', 196608) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT', 18) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH', 2) +AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64 = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64', 786432) +AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT', 20) +AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_ONE_PRIV = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_PRIV', 1048576) +AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT', 21) +AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP', 2097152) +AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT', 22) +AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE', 4194304) +AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT', 23) +AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE', 8388608) +AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT', 24) +AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_ONE_BULKY = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_BULKY', 16777216) +AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT', 25) +AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER', 33554432) +AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT', 26) +AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH', 6) +AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1 = enum_amd_compute_pgm_rsrc_one_t.define('AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1', -67108864) -# values for enumeration 'amd_compute_pgm_rsrc_one_t' -amd_compute_pgm_rsrc_one_t__enumvalues = { - 0: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT', - 6: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH', - 63: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT', - 6: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT', - 4: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH', - 960: 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT', - 10: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH', - 3072: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY', - 12: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH', - 12288: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32', - 14: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH', - 49152: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64', - 16: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH', - 196608: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32', - 18: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH', - 786432: 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64', - 20: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH', - 1048576: 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV', - 21: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH', - 2097152: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP', - 22: 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH', - 4194304: 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE', - 23: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH', - 8388608: 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE', - 24: 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH', - 16777216: 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY', - 25: 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH', - 33554432: 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER', - 26: 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT', - 6: 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH', - -67108864: 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1', -} -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT = 0 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH = 6 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT = 63 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT = 6 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH = 4 -AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT = 960 -AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT = 10 -AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY = 3072 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT = 12 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32 = 12288 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT = 14 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64 = 49152 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT = 16 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32 = 196608 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT = 18 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64 = 786432 -AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT = 20 -AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_PRIV = 1048576 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT = 21 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP = 2097152 -AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT = 22 -AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE = 4194304 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT = 23 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE = 8388608 -AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT = 24 -AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_BULKY = 16777216 -AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT = 25 -AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER = 33554432 -AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT = 26 -AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH = 6 -AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1 = -67108864 -amd_compute_pgm_rsrc_one_t = ctypes.c_int32 # enum +enum_amd_system_vgpr_workitem_id_t = CEnum(ctypes.c_uint32) +AMD_SYSTEM_VGPR_WORKITEM_ID_X = enum_amd_system_vgpr_workitem_id_t.define('AMD_SYSTEM_VGPR_WORKITEM_ID_X', 0) +AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y = enum_amd_system_vgpr_workitem_id_t.define('AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y', 1) +AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = enum_amd_system_vgpr_workitem_id_t.define('AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z', 2) +AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = enum_amd_system_vgpr_workitem_id_t.define('AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED', 3) -# values for enumeration 'amd_system_vgpr_workitem_id_t' -amd_system_vgpr_workitem_id_t__enumvalues = { - 0: 'AMD_SYSTEM_VGPR_WORKITEM_ID_X', - 1: 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y', - 2: 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z', - 3: 'AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED', -} -AMD_SYSTEM_VGPR_WORKITEM_ID_X = 0 -AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y = 1 -AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2 -AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 -amd_system_vgpr_workitem_id_t = ctypes.c_uint32 # enum amd_compute_pgm_rsrc_two32_t = ctypes.c_uint32 +enum_amd_compute_pgm_rsrc_two_t = CEnum(ctypes.c_int32) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT', 0) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET', 1) +AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT', 1) +AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH', 5) +AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT', 62) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT', 6) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER', 64) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT', 7) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X', 128) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT', 8) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y', 256) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT', 9) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z', 512) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT', 10) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO', 1024) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT', 11) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH', 2) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID', 6144) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT', 13) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH', 8192) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT', 14) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION', 16384) +AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT', 15) +AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH', 9) +AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE', 16744448) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT', 24) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION', 16777216) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT', 25) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE', 33554432) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT', 26) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO', 67108864) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT', 27) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW', 134217728) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT', 28) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW', 268435456) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT', 29) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT', 536870912) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT', 30) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO', 1073741824) +AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT', 31) +AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH', 1) +AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1 = enum_amd_compute_pgm_rsrc_two_t.define('AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1', -2147483648) -# values for enumeration 'amd_compute_pgm_rsrc_two_t' -amd_compute_pgm_rsrc_two_t__enumvalues = { - 0: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT', - 5: 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH', - 62: 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT', - 6: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH', - 64: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER', - 7: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH', - 128: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X', - 8: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH', - 256: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y', - 9: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH', - 512: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z', - 10: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH', - 1024: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO', - 11: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT', - 2: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH', - 6144: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID', - 13: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH', - 8192: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH', - 14: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH', - 16384: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION', - 15: 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT', - 9: 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH', - 16744448: 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE', - 24: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH', - 16777216: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION', - 25: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH', - 33554432: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE', - 26: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH', - 67108864: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO', - 27: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH', - 134217728: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW', - 28: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH', - 268435456: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW', - 29: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH', - 536870912: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT', - 30: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH', - 1073741824: 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO', - 31: 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT', - 1: 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH', - -2147483648: 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1', -} -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT = 0 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 1 -AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT = 1 -AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH = 5 -AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT = 62 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT = 6 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER = 64 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT = 7 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X = 128 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT = 8 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y = 256 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT = 9 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z = 512 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT = 10 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO = 1024 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT = 11 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH = 2 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID = 6144 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT = 13 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH = 8192 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT = 14 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION = 16384 -AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT = 15 -AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH = 9 -AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE = 16744448 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT = 24 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION = 16777216 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT = 25 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE = 33554432 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT = 26 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO = 67108864 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT = 27 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW = 134217728 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT = 28 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW = 268435456 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT = 29 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT = 536870912 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT = 30 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO = 1073741824 -AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT = 31 -AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH = 1 -AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1 = -2147483648 -amd_compute_pgm_rsrc_two_t = ctypes.c_int32 # enum +enum_amd_element_byte_size_t = CEnum(ctypes.c_uint32) +AMD_ELEMENT_BYTE_SIZE_2 = enum_amd_element_byte_size_t.define('AMD_ELEMENT_BYTE_SIZE_2', 0) +AMD_ELEMENT_BYTE_SIZE_4 = enum_amd_element_byte_size_t.define('AMD_ELEMENT_BYTE_SIZE_4', 1) +AMD_ELEMENT_BYTE_SIZE_8 = enum_amd_element_byte_size_t.define('AMD_ELEMENT_BYTE_SIZE_8', 2) +AMD_ELEMENT_BYTE_SIZE_16 = enum_amd_element_byte_size_t.define('AMD_ELEMENT_BYTE_SIZE_16', 3) -# values for enumeration 'amd_element_byte_size_t' -amd_element_byte_size_t__enumvalues = { - 0: 'AMD_ELEMENT_BYTE_SIZE_2', - 1: 'AMD_ELEMENT_BYTE_SIZE_4', - 2: 'AMD_ELEMENT_BYTE_SIZE_8', - 3: 'AMD_ELEMENT_BYTE_SIZE_16', -} -AMD_ELEMENT_BYTE_SIZE_2 = 0 -AMD_ELEMENT_BYTE_SIZE_4 = 1 -AMD_ELEMENT_BYTE_SIZE_8 = 2 -AMD_ELEMENT_BYTE_SIZE_16 = 3 -amd_element_byte_size_t = ctypes.c_uint32 # enum amd_kernel_code_properties32_t = ctypes.c_uint32 +enum_amd_kernel_code_properties_t = CEnum(ctypes.c_int32) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT', 0) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR', 2) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT', 2) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR', 4) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT', 3) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR', 8) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT', 4) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID', 16) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT', 5) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT', 32) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT', 6) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE', 64) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT', 7) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X', 128) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT', 8) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y', 256) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT', 9) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z', 512) +AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT', 10) +AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH', 6) +AMD_KERNEL_CODE_PROPERTIES_RESERVED1 = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_RESERVED1', 64512) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT', 16) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS', 65536) +AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT', 17) +AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH', 2) +AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE', 393216) +AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT', 19) +AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_IS_PTR64 = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_PTR64', 524288) +AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT', 20) +AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK', 1048576) +AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT', 21) +AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED', 2097152) +AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT', 22) +AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH', 1) +AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED', 4194304) +AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT', 23) +AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH', 9) +AMD_KERNEL_CODE_PROPERTIES_RESERVED2 = enum_amd_kernel_code_properties_t.define('AMD_KERNEL_CODE_PROPERTIES_RESERVED2', -8388608) -# values for enumeration 'amd_kernel_code_properties_t' -amd_kernel_code_properties_t__enumvalues = { - 0: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH', - 2: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR', - 2: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH', - 4: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR', - 3: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH', - 8: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR', - 4: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH', - 16: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID', - 5: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH', - 32: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT', - 6: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH', - 64: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE', - 7: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH', - 128: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X', - 8: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH', - 256: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y', - 9: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH', - 512: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z', - 10: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT', - 6: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH', - 64512: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1', - 16: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH', - 65536: 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS', - 17: 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT', - 2: 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH', - 393216: 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE', - 19: 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH', - 524288: 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64', - 20: 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH', - 1048576: 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK', - 21: 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH', - 2097152: 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED', - 22: 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT', - 1: 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH', - 4194304: 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED', - 23: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT', - 9: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH', - -8388608: 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2', -} -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT = 0 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR = 2 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT = 2 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR = 4 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT = 3 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR = 8 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT = 4 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID = 16 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT = 5 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT = 32 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT = 6 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE = 64 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT = 7 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X = 128 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT = 8 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y = 256 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT = 9 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z = 512 -AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT = 10 -AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH = 6 -AMD_KERNEL_CODE_PROPERTIES_RESERVED1 = 64512 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT = 16 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS = 65536 -AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT = 17 -AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH = 2 -AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE = 393216 -AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT = 19 -AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_PTR64 = 524288 -AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT = 20 -AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK = 1048576 -AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT = 21 -AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED = 2097152 -AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT = 22 -AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH = 1 -AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED = 4194304 -AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT = 23 -AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH = 9 -AMD_KERNEL_CODE_PROPERTIES_RESERVED2 = -8388608 -amd_kernel_code_properties_t = ctypes.c_int32 # enum amd_powertwo8_t = ctypes.c_ubyte +enum_amd_powertwo_t = CEnum(ctypes.c_uint32) +AMD_POWERTWO_1 = enum_amd_powertwo_t.define('AMD_POWERTWO_1', 0) +AMD_POWERTWO_2 = enum_amd_powertwo_t.define('AMD_POWERTWO_2', 1) +AMD_POWERTWO_4 = enum_amd_powertwo_t.define('AMD_POWERTWO_4', 2) +AMD_POWERTWO_8 = enum_amd_powertwo_t.define('AMD_POWERTWO_8', 3) +AMD_POWERTWO_16 = enum_amd_powertwo_t.define('AMD_POWERTWO_16', 4) +AMD_POWERTWO_32 = enum_amd_powertwo_t.define('AMD_POWERTWO_32', 5) +AMD_POWERTWO_64 = enum_amd_powertwo_t.define('AMD_POWERTWO_64', 6) +AMD_POWERTWO_128 = enum_amd_powertwo_t.define('AMD_POWERTWO_128', 7) +AMD_POWERTWO_256 = enum_amd_powertwo_t.define('AMD_POWERTWO_256', 8) -# values for enumeration 'amd_powertwo_t' -amd_powertwo_t__enumvalues = { - 0: 'AMD_POWERTWO_1', - 1: 'AMD_POWERTWO_2', - 2: 'AMD_POWERTWO_4', - 3: 'AMD_POWERTWO_8', - 4: 'AMD_POWERTWO_16', - 5: 'AMD_POWERTWO_32', - 6: 'AMD_POWERTWO_64', - 7: 'AMD_POWERTWO_128', - 8: 'AMD_POWERTWO_256', -} -AMD_POWERTWO_1 = 0 -AMD_POWERTWO_2 = 1 -AMD_POWERTWO_4 = 2 -AMD_POWERTWO_8 = 3 -AMD_POWERTWO_16 = 4 -AMD_POWERTWO_32 = 5 -AMD_POWERTWO_64 = 6 -AMD_POWERTWO_128 = 7 -AMD_POWERTWO_256 = 8 -amd_powertwo_t = ctypes.c_uint32 # enum amd_enabled_control_directive64_t = ctypes.c_uint64 +enum_amd_enabled_control_directive_t = CEnum(ctypes.c_uint32) +AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS', 1) +AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS', 2) +AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE', 4) +AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE', 8) +AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE', 16) +AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM', 32) +AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE', 64) +AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE', 128) +AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS = enum_amd_enabled_control_directive_t.define('AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS', 256) -# values for enumeration 'amd_enabled_control_directive_t' -amd_enabled_control_directive_t__enumvalues = { - 1: 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS', - 2: 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS', - 4: 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE', - 8: 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE', - 16: 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE', - 32: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM', - 64: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE', - 128: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE', - 256: 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS', -} -AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS = 1 -AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS = 2 -AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE = 4 -AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE = 8 -AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE = 16 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM = 32 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE = 64 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE = 128 -AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS = 256 -amd_enabled_control_directive_t = ctypes.c_uint32 # enum amd_exception_kind16_t = ctypes.c_uint16 +enum_amd_exception_kind_t = CEnum(ctypes.c_uint32) +AMD_EXCEPTION_KIND_INVALID_OPERATION = enum_amd_exception_kind_t.define('AMD_EXCEPTION_KIND_INVALID_OPERATION', 1) +AMD_EXCEPTION_KIND_DIVISION_BY_ZERO = enum_amd_exception_kind_t.define('AMD_EXCEPTION_KIND_DIVISION_BY_ZERO', 2) +AMD_EXCEPTION_KIND_OVERFLOW = enum_amd_exception_kind_t.define('AMD_EXCEPTION_KIND_OVERFLOW', 4) +AMD_EXCEPTION_KIND_UNDERFLOW = enum_amd_exception_kind_t.define('AMD_EXCEPTION_KIND_UNDERFLOW', 8) +AMD_EXCEPTION_KIND_INEXACT = enum_amd_exception_kind_t.define('AMD_EXCEPTION_KIND_INEXACT', 16) -# values for enumeration 'amd_exception_kind_t' -amd_exception_kind_t__enumvalues = { - 1: 'AMD_EXCEPTION_KIND_INVALID_OPERATION', - 2: 'AMD_EXCEPTION_KIND_DIVISION_BY_ZERO', - 4: 'AMD_EXCEPTION_KIND_OVERFLOW', - 8: 'AMD_EXCEPTION_KIND_UNDERFLOW', - 16: 'AMD_EXCEPTION_KIND_INEXACT', -} -AMD_EXCEPTION_KIND_INVALID_OPERATION = 1 -AMD_EXCEPTION_KIND_DIVISION_BY_ZERO = 2 -AMD_EXCEPTION_KIND_OVERFLOW = 4 -AMD_EXCEPTION_KIND_UNDERFLOW = 8 -AMD_EXCEPTION_KIND_INEXACT = 16 -amd_exception_kind_t = ctypes.c_uint32 # enum -class struct_amd_control_directives_s(Structure): - pass - -struct_amd_control_directives_s._pack_ = 1 # source:False +class struct_amd_control_directives_s(Struct): pass struct_amd_control_directives_s._fields_ = [ - ('enabled_control_directives', ctypes.c_uint64), - ('enable_break_exceptions', ctypes.c_uint16), - ('enable_detect_exceptions', ctypes.c_uint16), - ('max_dynamic_group_size', ctypes.c_uint32), - ('max_flat_grid_size', ctypes.c_uint64), - ('max_flat_workgroup_size', ctypes.c_uint32), - ('required_dim', ctypes.c_ubyte), - ('reserved1', ctypes.c_ubyte * 3), - ('required_grid_size', ctypes.c_uint64 * 3), - ('required_workgroup_size', ctypes.c_uint32 * 3), - ('reserved2', ctypes.c_ubyte * 60), + ('enabled_control_directives', amd_enabled_control_directive64_t), + ('enable_break_exceptions', uint16_t), + ('enable_detect_exceptions', uint16_t), + ('max_dynamic_group_size', uint32_t), + ('max_flat_grid_size', uint64_t), + ('max_flat_workgroup_size', uint32_t), + ('required_dim', uint8_t), + ('reserved1', (uint8_t * 3)), + ('required_grid_size', (uint64_t * 3)), + ('required_workgroup_size', (uint32_t * 3)), + ('reserved2', (uint8_t * 60)), ] - amd_control_directives_t = struct_amd_control_directives_s -class struct_amd_kernel_code_s(Structure): - pass - -struct_amd_kernel_code_s._pack_ = 1 # source:False +class struct_amd_kernel_code_s(Struct): pass struct_amd_kernel_code_s._fields_ = [ - ('amd_kernel_code_version_major', ctypes.c_uint32), - ('amd_kernel_code_version_minor', ctypes.c_uint32), - ('amd_machine_kind', ctypes.c_uint16), - ('amd_machine_version_major', ctypes.c_uint16), - ('amd_machine_version_minor', ctypes.c_uint16), - ('amd_machine_version_stepping', ctypes.c_uint16), - ('kernel_code_entry_byte_offset', ctypes.c_int64), - ('kernel_code_prefetch_byte_offset', ctypes.c_int64), - ('kernel_code_prefetch_byte_size', ctypes.c_uint64), - ('max_scratch_backing_memory_byte_size', ctypes.c_uint64), - ('compute_pgm_rsrc1', ctypes.c_uint32), - ('compute_pgm_rsrc2', ctypes.c_uint32), - ('kernel_code_properties', ctypes.c_uint32), - ('workitem_private_segment_byte_size', ctypes.c_uint32), - ('workgroup_group_segment_byte_size', ctypes.c_uint32), - ('gds_segment_byte_size', ctypes.c_uint32), - ('kernarg_segment_byte_size', ctypes.c_uint64), - ('workgroup_fbarrier_count', ctypes.c_uint32), - ('wavefront_sgpr_count', ctypes.c_uint16), - ('workitem_vgpr_count', ctypes.c_uint16), - ('reserved_vgpr_first', ctypes.c_uint16), - ('reserved_vgpr_count', ctypes.c_uint16), - ('reserved_sgpr_first', ctypes.c_uint16), - ('reserved_sgpr_count', ctypes.c_uint16), - ('debug_wavefront_private_segment_offset_sgpr', ctypes.c_uint16), - ('debug_private_segment_buffer_sgpr', ctypes.c_uint16), - ('kernarg_segment_alignment', ctypes.c_ubyte), - ('group_segment_alignment', ctypes.c_ubyte), - ('private_segment_alignment', ctypes.c_ubyte), - ('wavefront_size', ctypes.c_ubyte), - ('call_convention', ctypes.c_int32), - ('reserved1', ctypes.c_ubyte * 12), - ('runtime_loader_kernel_symbol', ctypes.c_uint64), - ('control_directives', amd_control_directives_t), + ('amd_kernel_code_version_major', amd_kernel_code_version32_t), + ('amd_kernel_code_version_minor', amd_kernel_code_version32_t), + ('amd_machine_kind', amd_machine_kind16_t), + ('amd_machine_version_major', amd_machine_version16_t), + ('amd_machine_version_minor', amd_machine_version16_t), + ('amd_machine_version_stepping', amd_machine_version16_t), + ('kernel_code_entry_byte_offset', int64_t), + ('kernel_code_prefetch_byte_offset', int64_t), + ('kernel_code_prefetch_byte_size', uint64_t), + ('max_scratch_backing_memory_byte_size', uint64_t), + ('compute_pgm_rsrc1', amd_compute_pgm_rsrc_one32_t), + ('compute_pgm_rsrc2', amd_compute_pgm_rsrc_two32_t), + ('kernel_code_properties', amd_kernel_code_properties32_t), + ('workitem_private_segment_byte_size', uint32_t), + ('workgroup_group_segment_byte_size', uint32_t), + ('gds_segment_byte_size', uint32_t), + ('kernarg_segment_byte_size', uint64_t), + ('workgroup_fbarrier_count', uint32_t), + ('wavefront_sgpr_count', uint16_t), + ('workitem_vgpr_count', uint16_t), + ('reserved_vgpr_first', uint16_t), + ('reserved_vgpr_count', uint16_t), + ('reserved_sgpr_first', uint16_t), + ('reserved_sgpr_count', uint16_t), + ('debug_wavefront_private_segment_offset_sgpr', uint16_t), + ('debug_private_segment_buffer_sgpr', uint16_t), + ('kernarg_segment_alignment', amd_powertwo8_t), + ('group_segment_alignment', amd_powertwo8_t), + ('private_segment_alignment', amd_powertwo8_t), + ('wavefront_size', amd_powertwo8_t), + ('call_convention', int32_t), + ('reserved1', (uint8_t * 12)), + ('runtime_loader_kernel_symbol', uint64_t), + ('control_directives', amd_control_directives_t), ] - amd_kernel_code_t = struct_amd_kernel_code_s -class struct_amd_runtime_loader_debug_info_s(Structure): - pass - -struct_amd_runtime_loader_debug_info_s._pack_ = 1 # source:False +class struct_amd_runtime_loader_debug_info_s(Struct): pass struct_amd_runtime_loader_debug_info_s._fields_ = [ - ('elf_raw', ctypes.POINTER(None)), - ('elf_size', ctypes.c_uint64), - ('kernel_name', ctypes.POINTER(ctypes.c_char)), - ('owning_segment', ctypes.POINTER(None)), + ('elf_raw', ctypes.c_void_p), + ('elf_size', size_t), + ('kernel_name', ctypes.POINTER(ctypes.c_char)), + ('owning_segment', ctypes.c_void_p), ] - amd_runtime_loader_debug_info_t = struct_amd_runtime_loader_debug_info_s -class struct_BrigModuleHeader(Structure): - pass - +class struct_BrigModuleHeader(Struct): pass BrigModule_t = ctypes.POINTER(struct_BrigModuleHeader) +_anonenum1 = CEnum(ctypes.c_uint32) +HSA_EXT_STATUS_ERROR_INVALID_PROGRAM = _anonenum1.define('HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', 8192) +HSA_EXT_STATUS_ERROR_INVALID_MODULE = _anonenum1.define('HSA_EXT_STATUS_ERROR_INVALID_MODULE', 8193) +HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE = _anonenum1.define('HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE', 8194) +HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED = _anonenum1.define('HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED', 8195) +HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH = _anonenum1.define('HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH', 8196) +HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED = _anonenum1.define('HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED', 8197) +HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH = _anonenum1.define('HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH', 8198) -# values for enumeration 'c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM' -c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM__enumvalues = { - 8192: 'HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', - 8193: 'HSA_EXT_STATUS_ERROR_INVALID_MODULE', - 8194: 'HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE', - 8195: 'HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED', - 8196: 'HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH', - 8197: 'HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED', - 8198: 'HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH', -} -HSA_EXT_STATUS_ERROR_INVALID_PROGRAM = 8192 -HSA_EXT_STATUS_ERROR_INVALID_MODULE = 8193 -HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE = 8194 -HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED = 8195 -HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH = 8196 -HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED = 8197 -HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH = 8198 -c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM = ctypes.c_uint32 # enum hsa_ext_module_t = ctypes.POINTER(struct_BrigModuleHeader) -class struct_hsa_ext_program_s(Structure): - pass - -struct_hsa_ext_program_s._pack_ = 1 # source:False +class struct_hsa_ext_program_s(Struct): pass struct_hsa_ext_program_s._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64_t), ] - hsa_ext_program_t = struct_hsa_ext_program_s -try: - hsa_ext_program_create = _libraries['libhsa-runtime64.so'].hsa_ext_program_create - hsa_ext_program_create.restype = hsa_status_t - hsa_ext_program_create.argtypes = [hsa_machine_model_t, hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_ext_program_s)] -except AttributeError: - pass -try: - hsa_ext_program_destroy = _libraries['libhsa-runtime64.so'].hsa_ext_program_destroy - hsa_ext_program_destroy.restype = hsa_status_t - hsa_ext_program_destroy.argtypes = [hsa_ext_program_t] -except AttributeError: - pass -try: - hsa_ext_program_add_module = _libraries['libhsa-runtime64.so'].hsa_ext_program_add_module - hsa_ext_program_add_module.restype = hsa_status_t - hsa_ext_program_add_module.argtypes = [hsa_ext_program_t, hsa_ext_module_t] -except AttributeError: - pass -try: - hsa_ext_program_iterate_modules = _libraries['libhsa-runtime64.so'].hsa_ext_program_iterate_modules - hsa_ext_program_iterate_modules.restype = hsa_status_t - hsa_ext_program_iterate_modules.argtypes = [hsa_ext_program_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.POINTER(struct_BrigModuleHeader), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_ext_program_create(hsa_machine_model_t machine_model, hsa_profile_t profile, hsa_default_float_rounding_mode_t default_float_rounding_mode, const char *options, hsa_ext_program_t *program) +try: (hsa_ext_program_create:=dll.hsa_ext_program_create).restype, hsa_ext_program_create.argtypes = hsa_status_t, [hsa_machine_model_t, hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_ext_program_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_ext_program_info_t' -c__EA_hsa_ext_program_info_t__enumvalues = { - 0: 'HSA_EXT_PROGRAM_INFO_MACHINE_MODEL', - 1: 'HSA_EXT_PROGRAM_INFO_PROFILE', - 2: 'HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE', -} -HSA_EXT_PROGRAM_INFO_MACHINE_MODEL = 0 -HSA_EXT_PROGRAM_INFO_PROFILE = 1 -HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE = 2 -c__EA_hsa_ext_program_info_t = ctypes.c_uint32 # enum -hsa_ext_program_info_t = c__EA_hsa_ext_program_info_t -hsa_ext_program_info_t__enumvalues = c__EA_hsa_ext_program_info_t__enumvalues -try: - hsa_ext_program_get_info = _libraries['libhsa-runtime64.so'].hsa_ext_program_get_info - hsa_ext_program_get_info.restype = hsa_status_t - hsa_ext_program_get_info.argtypes = [hsa_ext_program_t, hsa_ext_program_info_t, ctypes.POINTER(None)] -except AttributeError: - pass +# hsa_status_t hsa_ext_program_destroy(hsa_ext_program_t program) +try: (hsa_ext_program_destroy:=dll.hsa_ext_program_destroy).restype, hsa_ext_program_destroy.argtypes = hsa_status_t, [hsa_ext_program_t] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_ext_finalizer_call_convention_t' -c__EA_hsa_ext_finalizer_call_convention_t__enumvalues = { - -1: 'HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO', -} -HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO = -1 -c__EA_hsa_ext_finalizer_call_convention_t = ctypes.c_int32 # enum -hsa_ext_finalizer_call_convention_t = c__EA_hsa_ext_finalizer_call_convention_t -hsa_ext_finalizer_call_convention_t__enumvalues = c__EA_hsa_ext_finalizer_call_convention_t__enumvalues -class struct_hsa_ext_control_directives_s(Structure): - pass +# hsa_status_t hsa_ext_program_add_module(hsa_ext_program_t program, hsa_ext_module_t module) +try: (hsa_ext_program_add_module:=dll.hsa_ext_program_add_module).restype, hsa_ext_program_add_module.argtypes = hsa_status_t, [hsa_ext_program_t, hsa_ext_module_t] +except AttributeError: pass -struct_hsa_ext_control_directives_s._pack_ = 1 # source:False +# hsa_status_t hsa_ext_program_iterate_modules(hsa_ext_program_t program, hsa_status_t (*callback)(hsa_ext_program_t, hsa_ext_module_t, void *), void *data) +try: (hsa_ext_program_iterate_modules:=dll.hsa_ext_program_iterate_modules).restype, hsa_ext_program_iterate_modules.argtypes = hsa_status_t, [hsa_ext_program_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t, hsa_ext_module_t, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +hsa_ext_program_info_t = CEnum(ctypes.c_uint32) +HSA_EXT_PROGRAM_INFO_MACHINE_MODEL = hsa_ext_program_info_t.define('HSA_EXT_PROGRAM_INFO_MACHINE_MODEL', 0) +HSA_EXT_PROGRAM_INFO_PROFILE = hsa_ext_program_info_t.define('HSA_EXT_PROGRAM_INFO_PROFILE', 1) +HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE = hsa_ext_program_info_t.define('HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE', 2) + +# hsa_status_t hsa_ext_program_get_info(hsa_ext_program_t program, hsa_ext_program_info_t attribute, void *value) +try: (hsa_ext_program_get_info:=dll.hsa_ext_program_get_info).restype, hsa_ext_program_get_info.argtypes = hsa_status_t, [hsa_ext_program_t, hsa_ext_program_info_t, ctypes.c_void_p] +except AttributeError: pass + +hsa_ext_finalizer_call_convention_t = CEnum(ctypes.c_int32) +HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO = hsa_ext_finalizer_call_convention_t.define('HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO', -1) + +class struct_hsa_ext_control_directives_s(Struct): pass struct_hsa_ext_control_directives_s._fields_ = [ - ('control_directives_mask', ctypes.c_uint64), - ('break_exceptions_mask', ctypes.c_uint16), - ('detect_exceptions_mask', ctypes.c_uint16), - ('max_dynamic_group_size', ctypes.c_uint32), - ('max_flat_grid_size', ctypes.c_uint64), - ('max_flat_workgroup_size', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), - ('required_grid_size', ctypes.c_uint64 * 3), - ('required_workgroup_size', hsa_dim3_t), - ('required_dim', ctypes.c_ubyte), - ('reserved2', ctypes.c_ubyte * 75), + ('control_directives_mask', uint64_t), + ('break_exceptions_mask', uint16_t), + ('detect_exceptions_mask', uint16_t), + ('max_dynamic_group_size', uint32_t), + ('max_flat_grid_size', uint64_t), + ('max_flat_workgroup_size', uint32_t), + ('reserved1', uint32_t), + ('required_grid_size', (uint64_t * 3)), + ('required_workgroup_size', hsa_dim3_t), + ('required_dim', uint8_t), + ('reserved2', (uint8_t * 75)), ] - hsa_ext_control_directives_t = struct_hsa_ext_control_directives_s -try: - hsa_ext_program_finalize = _libraries['libhsa-runtime64.so'].hsa_ext_program_finalize - hsa_ext_program_finalize.restype = hsa_status_t - hsa_ext_program_finalize.argtypes = [hsa_ext_program_t, hsa_isa_t, int32_t, hsa_ext_control_directives_t, ctypes.POINTER(ctypes.c_char), hsa_code_object_type_t, ctypes.POINTER(struct_hsa_code_object_s)] -except AttributeError: - pass -class struct_hsa_ext_finalizer_1_00_pfn_s(Structure): - pass +# hsa_status_t hsa_ext_program_finalize(hsa_ext_program_t program, hsa_isa_t isa, int32_t call_convention, hsa_ext_control_directives_t control_directives, const char *options, hsa_code_object_type_t code_object_type, hsa_code_object_t *code_object) +try: (hsa_ext_program_finalize:=dll.hsa_ext_program_finalize).restype, hsa_ext_program_finalize.argtypes = hsa_status_t, [hsa_ext_program_t, hsa_isa_t, int32_t, hsa_ext_control_directives_t, ctypes.POINTER(ctypes.c_char), hsa_code_object_type_t, ctypes.POINTER(hsa_code_object_t)] +except AttributeError: pass -struct_hsa_ext_finalizer_1_00_pfn_s._pack_ = 1 # source:False +class struct_hsa_ext_finalizer_1_00_pfn_s(Struct): pass struct_hsa_ext_finalizer_1_00_pfn_s._fields_ = [ - ('hsa_ext_program_create', ctypes.CFUNCTYPE(c__EA_hsa_status_t, c__EA_hsa_machine_model_t, c__EA_hsa_profile_t, c__EA_hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_hsa_ext_program_s))), - ('hsa_ext_program_destroy', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s)), - ('hsa_ext_program_add_module', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.POINTER(struct_BrigModuleHeader))), - ('hsa_ext_program_iterate_modules', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, ctypes.POINTER(struct_BrigModuleHeader), ctypes.POINTER(None)), ctypes.POINTER(None))), - ('hsa_ext_program_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, c__EA_hsa_ext_program_info_t, ctypes.POINTER(None))), - ('hsa_ext_program_finalize', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_ext_program_s, struct_hsa_isa_s, ctypes.c_int32, struct_hsa_ext_control_directives_s, ctypes.POINTER(ctypes.c_char), c__EA_hsa_code_object_type_t, ctypes.POINTER(struct_hsa_code_object_s))), + ('hsa_ext_program_create', ctypes.CFUNCTYPE(hsa_status_t, hsa_machine_model_t, hsa_profile_t, hsa_default_float_rounding_mode_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(hsa_ext_program_t))), + ('hsa_ext_program_destroy', ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t)), + ('hsa_ext_program_add_module', ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t, hsa_ext_module_t)), + ('hsa_ext_program_iterate_modules', ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t, ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t, hsa_ext_module_t, ctypes.c_void_p), ctypes.c_void_p)), + ('hsa_ext_program_get_info', ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t, hsa_ext_program_info_t, ctypes.c_void_p)), + ('hsa_ext_program_finalize', ctypes.CFUNCTYPE(hsa_status_t, hsa_ext_program_t, hsa_isa_t, int32_t, hsa_ext_control_directives_t, ctypes.POINTER(ctypes.c_char), hsa_code_object_type_t, ctypes.POINTER(hsa_code_object_t))), ] - hsa_ext_finalizer_1_00_pfn_t = struct_hsa_ext_finalizer_1_00_pfn_s -try: - hsa_ven_amd_aqlprofile_version_major = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_version_major - hsa_ven_amd_aqlprofile_version_major.restype = uint32_t - hsa_ven_amd_aqlprofile_version_major.argtypes = [] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_version_minor = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_version_minor - hsa_ven_amd_aqlprofile_version_minor.restype = uint32_t - hsa_ven_amd_aqlprofile_version_minor.argtypes = [] -except AttributeError: - pass +_anonenum2 = CEnum(ctypes.c_uint32) +HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED = _anonenum2.define('HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', 12288) +HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED = _anonenum2.define('HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED', 12289) +HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED = _anonenum2.define('HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED', 12290) +HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED = _anonenum2.define('HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED', 12291) -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_event_type_t' -c__EA_hsa_ven_amd_aqlprofile_event_type_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC', - 1: 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE', -} -HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC = 0 -HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE = 1 -c__EA_hsa_ven_amd_aqlprofile_event_type_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_event_type_t = c__EA_hsa_ven_amd_aqlprofile_event_type_t -hsa_ven_amd_aqlprofile_event_type_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_event_type_t__enumvalues +_anonenum3 = CEnum(ctypes.c_uint32) +HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', 12288) +HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS', 12289) +HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS', 12290) +HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS', 12291) +HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS', 12292) +HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS', 12293) +HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS', 12294) +HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS', 12295) +HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS', 12296) +HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES = _anonenum3.define('HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES', 12297) +HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES = _anonenum3.define('HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES', 12298) +HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS = _anonenum3.define('HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS', 12299) +HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT = _anonenum3.define('HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT', 12300) -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_block_name_t' -c__EA_hsa_ven_amd_aqlprofile_block_name_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC', - 1: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF', - 2: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS', - 3: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM', - 4: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE', - 5: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI', - 6: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ', - 7: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS', - 8: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM', - 9: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX', - 10: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA', - 11: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA', - 12: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC', - 13: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP', - 14: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD', - 15: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB', - 16: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB', - 17: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM', - 18: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ', - 19: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2', - 20: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR', - 21: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC', - 22: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2', - 23: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA', - 24: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB', - 25: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA', - 26: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A', - 27: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C', - 28: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A', - 29: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C', - 30: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR', - 31: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS', - 32: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC', - 33: 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA', - 34: 'HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER', -} -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC = 0 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF = 1 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS = 2 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM = 3 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE = 4 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI = 5 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ = 6 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS = 7 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM = 8 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX = 9 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA = 10 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA = 11 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC = 12 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP = 13 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD = 14 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB = 15 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB = 16 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM = 17 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ = 18 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2 = 19 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR = 20 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC = 21 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2 = 22 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA = 23 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB = 24 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA = 25 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A = 26 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C = 27 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A = 28 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C = 29 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR = 30 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS = 31 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC = 32 -HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA = 33 -HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER = 34 -c__EA_hsa_ven_amd_aqlprofile_block_name_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_block_name_t = c__EA_hsa_ven_amd_aqlprofile_block_name_t -hsa_ven_amd_aqlprofile_block_name_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_block_name_t__enumvalues -class struct_c__SA_hsa_ven_amd_aqlprofile_event_t(Structure): - pass +hsa_ext_image_channel_type_t = CEnum(ctypes.c_uint32) +HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8', 0) +HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16', 1) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8', 2) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16', 3) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24', 4) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555', 5) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565', 6) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010', 7) +HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8', 8) +HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16', 9) +HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32', 10) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8', 11) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16', 12) +HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32', 13) +HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT', 14) +HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT = hsa_ext_image_channel_type_t.define('HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT', 15) -struct_c__SA_hsa_ven_amd_aqlprofile_event_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_event_t._fields_ = [ - ('block_name', hsa_ven_amd_aqlprofile_block_name_t), - ('block_index', ctypes.c_uint32), - ('counter_id', ctypes.c_uint32), +hsa_ext_image_channel_order_t = CEnum(ctypes.c_uint32) +HSA_EXT_IMAGE_CHANNEL_ORDER_A = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_A', 0) +HSA_EXT_IMAGE_CHANNEL_ORDER_R = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_R', 1) +HSA_EXT_IMAGE_CHANNEL_ORDER_RX = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RX', 2) +HSA_EXT_IMAGE_CHANNEL_ORDER_RG = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RG', 3) +HSA_EXT_IMAGE_CHANNEL_ORDER_RGX = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RGX', 4) +HSA_EXT_IMAGE_CHANNEL_ORDER_RA = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RA', 5) +HSA_EXT_IMAGE_CHANNEL_ORDER_RGB = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RGB', 6) +HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX', 7) +HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA', 8) +HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA', 9) +HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB', 10) +HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR', 11) +HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB', 12) +HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX', 13) +HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA', 14) +HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA', 15) +HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY', 16) +HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE', 17) +HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH', 18) +HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = hsa_ext_image_channel_order_t.define('HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL', 19) + +hsa_ext_image_capability_t = CEnum(ctypes.c_uint32) +HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED = hsa_ext_image_capability_t.define('HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED', 0) +HSA_EXT_IMAGE_CAPABILITY_READ_ONLY = hsa_ext_image_capability_t.define('HSA_EXT_IMAGE_CAPABILITY_READ_ONLY', 1) +HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY = hsa_ext_image_capability_t.define('HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY', 2) +HSA_EXT_IMAGE_CAPABILITY_READ_WRITE = hsa_ext_image_capability_t.define('HSA_EXT_IMAGE_CAPABILITY_READ_WRITE', 4) +HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE = hsa_ext_image_capability_t.define('HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE', 8) +HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT = hsa_ext_image_capability_t.define('HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT', 16) + +hsa_ext_image_data_layout_t = CEnum(ctypes.c_uint32) +HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE = hsa_ext_image_data_layout_t.define('HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE', 0) +HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR = hsa_ext_image_data_layout_t.define('HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR', 1) + +# hsa_status_t hsa_ext_image_get_capability(hsa_agent_t agent, hsa_ext_image_geometry_t geometry, const hsa_ext_image_format_t *image_format, uint32_t *capability_mask) +try: (hsa_ext_image_get_capability:=dll.hsa_ext_image_get_capability).restype, hsa_ext_image_get_capability.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(hsa_ext_image_format_t), ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# hsa_status_t hsa_ext_image_get_capability_with_layout(hsa_agent_t agent, hsa_ext_image_geometry_t geometry, const hsa_ext_image_format_t *image_format, hsa_ext_image_data_layout_t image_data_layout, uint32_t *capability_mask) +try: (hsa_ext_image_get_capability_with_layout:=dll.hsa_ext_image_get_capability_with_layout).restype, hsa_ext_image_get_capability_with_layout.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(hsa_ext_image_format_t), hsa_ext_image_data_layout_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +class struct_hsa_ext_image_data_info_s(Struct): pass +struct_hsa_ext_image_data_info_s._fields_ = [ + ('size', size_t), + ('alignment', size_t), ] +hsa_ext_image_data_info_t = struct_hsa_ext_image_data_info_s +# hsa_status_t hsa_ext_image_data_get_info(hsa_agent_t agent, const hsa_ext_image_descriptor_t *image_descriptor, hsa_access_permission_t access_permission, hsa_ext_image_data_info_t *image_data_info) +try: (hsa_ext_image_data_get_info:=dll.hsa_ext_image_data_get_info).restype, hsa_ext_image_data_get_info.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_data_info_t)] +except AttributeError: pass -hsa_ven_amd_aqlprofile_event_t = struct_c__SA_hsa_ven_amd_aqlprofile_event_t -try: - hsa_ven_amd_aqlprofile_validate_event = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_validate_event - hsa_ven_amd_aqlprofile_validate_event.restype = hsa_status_t - hsa_ven_amd_aqlprofile_validate_event.argtypes = [hsa_agent_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_event_t), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass +# hsa_status_t hsa_ext_image_data_get_info_with_layout(hsa_agent_t agent, const hsa_ext_image_descriptor_t *image_descriptor, hsa_access_permission_t access_permission, hsa_ext_image_data_layout_t image_data_layout, size_t image_data_row_pitch, size_t image_data_slice_pitch, hsa_ext_image_data_info_t *image_data_info) +try: (hsa_ext_image_data_get_info_with_layout:=dll.hsa_ext_image_data_get_info_with_layout).restype, hsa_ext_image_data_get_info_with_layout.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(hsa_ext_image_data_info_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_parameter_name_t' -c__EA_hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET', - 1: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK', - 2: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK', - 3: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK', - 4: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2', - 5: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK', - 6: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE', - 7: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT', - 8: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION', - 9: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE', - 10: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE', - 240: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK', - 241: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL', - 242: 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME', -} -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET = 0 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK = 1 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK = 2 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK = 3 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2 = 4 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK = 5 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE = 6 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT = 7 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION = 8 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE = 9 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE = 10 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK = 240 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL = 241 -HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME = 242 -c__EA_hsa_ven_amd_aqlprofile_parameter_name_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_parameter_name_t = c__EA_hsa_ven_amd_aqlprofile_parameter_name_t -hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues -class struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t(Structure): - pass +# hsa_status_t hsa_ext_image_create(hsa_agent_t agent, const hsa_ext_image_descriptor_t *image_descriptor, const void *image_data, hsa_access_permission_t access_permission, hsa_ext_image_t *image) +try: (hsa_ext_image_create:=dll.hsa_ext_image_create).restype, hsa_ext_image_create.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), ctypes.c_void_p, hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_t)] +except AttributeError: pass -struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t._fields_ = [ - ('parameter_name', hsa_ven_amd_aqlprofile_parameter_name_t), - ('value', ctypes.c_uint32), +# hsa_status_t hsa_ext_image_create_with_layout(hsa_agent_t agent, const hsa_ext_image_descriptor_t *image_descriptor, const void *image_data, hsa_access_permission_t access_permission, hsa_ext_image_data_layout_t image_data_layout, size_t image_data_row_pitch, size_t image_data_slice_pitch, hsa_ext_image_t *image) +try: (hsa_ext_image_create_with_layout:=dll.hsa_ext_image_create_with_layout).restype, hsa_ext_image_create_with_layout.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), ctypes.c_void_p, hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(hsa_ext_image_t)] +except AttributeError: pass + +# hsa_status_t hsa_ext_image_destroy(hsa_agent_t agent, hsa_ext_image_t image) +try: (hsa_ext_image_destroy:=dll.hsa_ext_image_destroy).restype, hsa_ext_image_destroy.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_image_t] +except AttributeError: pass + +# hsa_status_t hsa_ext_image_copy(hsa_agent_t agent, hsa_ext_image_t src_image, const hsa_dim3_t *src_offset, hsa_ext_image_t dst_image, const hsa_dim3_t *dst_offset, const hsa_dim3_t *range) +try: (hsa_ext_image_copy:=dll.hsa_ext_image_copy).restype, hsa_ext_image_copy.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(hsa_dim3_t), hsa_ext_image_t, ctypes.POINTER(hsa_dim3_t), ctypes.POINTER(hsa_dim3_t)] +except AttributeError: pass + +class struct_hsa_ext_image_region_s(Struct): pass +struct_hsa_ext_image_region_s._fields_ = [ + ('offset', hsa_dim3_t), + ('range', hsa_dim3_t), ] +hsa_ext_image_region_t = struct_hsa_ext_image_region_s +# hsa_status_t hsa_ext_image_import(hsa_agent_t agent, const void *src_memory, size_t src_row_pitch, size_t src_slice_pitch, hsa_ext_image_t dst_image, const hsa_ext_image_region_t *image_region) +try: (hsa_ext_image_import:=dll.hsa_ext_image_import).restype, hsa_ext_image_import.argtypes = hsa_status_t, [hsa_agent_t, ctypes.c_void_p, size_t, size_t, hsa_ext_image_t, ctypes.POINTER(hsa_ext_image_region_t)] +except AttributeError: pass -hsa_ven_amd_aqlprofile_parameter_t = struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t +# hsa_status_t hsa_ext_image_export(hsa_agent_t agent, hsa_ext_image_t src_image, void *dst_memory, size_t dst_row_pitch, size_t dst_slice_pitch, const hsa_ext_image_region_t *image_region) +try: (hsa_ext_image_export:=dll.hsa_ext_image_export).restype, hsa_ext_image_export.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_image_t, ctypes.c_void_p, size_t, size_t, ctypes.POINTER(hsa_ext_image_region_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t' -c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0', - 1: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1', - 2: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2', - 3: 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3', -} -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0 = 0 -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1 = 1 -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2 = 2 -HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3 = 3 -c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_att_marker_channel_t = c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t -hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues -class struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t(Structure): - pass +# hsa_status_t hsa_ext_image_clear(hsa_agent_t agent, hsa_ext_image_t image, const void *data, const hsa_ext_image_region_t *image_region) +try: (hsa_ext_image_clear:=dll.hsa_ext_image_clear).restype, hsa_ext_image_clear.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_image_t, ctypes.c_void_p, ctypes.POINTER(hsa_ext_image_region_t)] +except AttributeError: pass -struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t._fields_ = [ - ('ptr', ctypes.POINTER(None)), - ('size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class struct_hsa_ext_sampler_s(Struct): pass +struct_hsa_ext_sampler_s._fields_ = [ + ('handle', uint64_t), ] +hsa_ext_sampler_t = struct_hsa_ext_sampler_s +hsa_ext_sampler_addressing_mode_t = CEnum(ctypes.c_uint32) +HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED = hsa_ext_sampler_addressing_mode_t.define('HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED', 0) +HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE = hsa_ext_sampler_addressing_mode_t.define('HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE', 1) +HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER = hsa_ext_sampler_addressing_mode_t.define('HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER', 2) +HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT = hsa_ext_sampler_addressing_mode_t.define('HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT', 3) +HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT = hsa_ext_sampler_addressing_mode_t.define('HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT', 4) -hsa_ven_amd_aqlprofile_descriptor_t = struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t -class struct_c__SA_hsa_ven_amd_aqlprofile_profile_t(Structure): - pass +hsa_ext_sampler_addressing_mode32_t = ctypes.c_uint32 +hsa_ext_sampler_coordinate_mode_t = CEnum(ctypes.c_uint32) +HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED = hsa_ext_sampler_coordinate_mode_t.define('HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED', 0) +HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED = hsa_ext_sampler_coordinate_mode_t.define('HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED', 1) -struct_c__SA_hsa_ven_amd_aqlprofile_profile_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_profile_t._fields_ = [ - ('agent', hsa_agent_t), - ('type', hsa_ven_amd_aqlprofile_event_type_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('events', ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_event_t)), - ('event_count', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('parameters', ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t)), - ('parameter_count', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('output_buffer', hsa_ven_amd_aqlprofile_descriptor_t), - ('command_buffer', hsa_ven_amd_aqlprofile_descriptor_t), +hsa_ext_sampler_coordinate_mode32_t = ctypes.c_uint32 +hsa_ext_sampler_filter_mode_t = CEnum(ctypes.c_uint32) +HSA_EXT_SAMPLER_FILTER_MODE_NEAREST = hsa_ext_sampler_filter_mode_t.define('HSA_EXT_SAMPLER_FILTER_MODE_NEAREST', 0) +HSA_EXT_SAMPLER_FILTER_MODE_LINEAR = hsa_ext_sampler_filter_mode_t.define('HSA_EXT_SAMPLER_FILTER_MODE_LINEAR', 1) + +hsa_ext_sampler_filter_mode32_t = ctypes.c_uint32 +class struct_hsa_ext_sampler_descriptor_s(Struct): pass +struct_hsa_ext_sampler_descriptor_s._fields_ = [ + ('coordinate_mode', hsa_ext_sampler_coordinate_mode32_t), + ('filter_mode', hsa_ext_sampler_filter_mode32_t), + ('address_mode', hsa_ext_sampler_addressing_mode32_t), ] +hsa_ext_sampler_descriptor_t = struct_hsa_ext_sampler_descriptor_s +# hsa_status_t hsa_ext_sampler_create(hsa_agent_t agent, const hsa_ext_sampler_descriptor_t *sampler_descriptor, hsa_ext_sampler_t *sampler) +try: (hsa_ext_sampler_create:=dll.hsa_ext_sampler_create).restype, hsa_ext_sampler_create.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ext_sampler_descriptor_t), ctypes.POINTER(hsa_ext_sampler_t)] +except AttributeError: pass -hsa_ven_amd_aqlprofile_profile_t = struct_c__SA_hsa_ven_amd_aqlprofile_profile_t -class struct_c__SA_hsa_ext_amd_aql_pm4_packet_t(Structure): - pass +# hsa_status_t hsa_ext_sampler_destroy(hsa_agent_t agent, hsa_ext_sampler_t sampler) +try: (hsa_ext_sampler_destroy:=dll.hsa_ext_sampler_destroy).restype, hsa_ext_sampler_destroy.argtypes = hsa_status_t, [hsa_agent_t, hsa_ext_sampler_t] +except AttributeError: pass -struct_c__SA_hsa_ext_amd_aql_pm4_packet_t._pack_ = 1 # source:False -struct_c__SA_hsa_ext_amd_aql_pm4_packet_t._fields_ = [ - ('header', ctypes.c_uint16), - ('pm4_command', ctypes.c_uint16 * 27), - ('completion_signal', hsa_signal_t), +class struct_hsa_ext_images_1_00_pfn_s(Struct): pass +struct_hsa_ext_images_1_00_pfn_s._fields_ = [ + ('hsa_ext_image_get_capability', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(hsa_ext_image_format_t), ctypes.POINTER(uint32_t))), + ('hsa_ext_image_data_get_info', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_data_info_t))), + ('hsa_ext_image_create', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), ctypes.c_void_p, hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_t))), + ('hsa_ext_image_destroy', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t)), + ('hsa_ext_image_copy', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(hsa_dim3_t), hsa_ext_image_t, ctypes.POINTER(hsa_dim3_t), ctypes.POINTER(hsa_dim3_t))), + ('hsa_ext_image_import', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.c_void_p, size_t, size_t, hsa_ext_image_t, ctypes.POINTER(hsa_ext_image_region_t))), + ('hsa_ext_image_export', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t, ctypes.c_void_p, size_t, size_t, ctypes.POINTER(hsa_ext_image_region_t))), + ('hsa_ext_image_clear', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t, ctypes.c_void_p, ctypes.POINTER(hsa_ext_image_region_t))), + ('hsa_ext_sampler_create', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_sampler_descriptor_t), ctypes.POINTER(hsa_ext_sampler_t))), + ('hsa_ext_sampler_destroy', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_sampler_t)), ] - -hsa_ext_amd_aql_pm4_packet_t = struct_c__SA_hsa_ext_amd_aql_pm4_packet_t -try: - hsa_ven_amd_aqlprofile_start = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_start - hsa_ven_amd_aqlprofile_start.restype = hsa_status_t - hsa_ven_amd_aqlprofile_start.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_stop = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_stop - hsa_ven_amd_aqlprofile_stop.restype = hsa_status_t - hsa_ven_amd_aqlprofile_stop.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_read = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_read - hsa_ven_amd_aqlprofile_read.restype = hsa_status_t - hsa_ven_amd_aqlprofile_read.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t)] -except AttributeError: - pass -HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE = 192 # Variable ctypes.c_uint32 -try: - hsa_ven_amd_aqlprofile_legacy_get_pm4 = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_legacy_get_pm4 - hsa_ven_amd_aqlprofile_legacy_get_pm4.restype = hsa_status_t - hsa_ven_amd_aqlprofile_legacy_get_pm4.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_att_marker = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_att_marker - hsa_ven_amd_aqlprofile_att_marker.restype = hsa_status_t - hsa_ven_amd_aqlprofile_att_marker.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), uint32_t, hsa_ven_amd_aqlprofile_att_marker_channel_t] -except AttributeError: - pass -class struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t(Structure): - pass - -class union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0(Union): - pass - -class struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data._fields_ = [ - ('event', hsa_ven_amd_aqlprofile_event_t), - ('PADDING_0', ctypes.c_ubyte * 4), - ('result', ctypes.c_uint64), +hsa_ext_images_1_00_pfn_t = struct_hsa_ext_images_1_00_pfn_s +class struct_hsa_ext_images_1_pfn_s(Struct): pass +struct_hsa_ext_images_1_pfn_s._fields_ = [ + ('hsa_ext_image_get_capability', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(hsa_ext_image_format_t), ctypes.POINTER(uint32_t))), + ('hsa_ext_image_data_get_info', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_data_info_t))), + ('hsa_ext_image_create', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), ctypes.c_void_p, hsa_access_permission_t, ctypes.POINTER(hsa_ext_image_t))), + ('hsa_ext_image_destroy', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t)), + ('hsa_ext_image_copy', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t, ctypes.POINTER(hsa_dim3_t), hsa_ext_image_t, ctypes.POINTER(hsa_dim3_t), ctypes.POINTER(hsa_dim3_t))), + ('hsa_ext_image_import', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.c_void_p, size_t, size_t, hsa_ext_image_t, ctypes.POINTER(hsa_ext_image_region_t))), + ('hsa_ext_image_export', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t, ctypes.c_void_p, size_t, size_t, ctypes.POINTER(hsa_ext_image_region_t))), + ('hsa_ext_image_clear', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_t, ctypes.c_void_p, ctypes.POINTER(hsa_ext_image_region_t))), + ('hsa_ext_sampler_create', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_sampler_descriptor_t), ctypes.POINTER(hsa_ext_sampler_t))), + ('hsa_ext_sampler_destroy', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_sampler_t)), + ('hsa_ext_image_get_capability_with_layout', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ext_image_geometry_t, ctypes.POINTER(hsa_ext_image_format_t), hsa_ext_image_data_layout_t, ctypes.POINTER(uint32_t))), + ('hsa_ext_image_data_get_info_with_layout', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(hsa_ext_image_data_info_t))), + ('hsa_ext_image_create_with_layout', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ext_image_descriptor_t), ctypes.c_void_p, hsa_access_permission_t, hsa_ext_image_data_layout_t, size_t, size_t, ctypes.POINTER(hsa_ext_image_t))), ] +hsa_ext_images_1_pfn_t = struct_hsa_ext_images_1_pfn_s +# uint32_t hsa_ven_amd_aqlprofile_version_major() +try: (hsa_ven_amd_aqlprofile_version_major:=dll.hsa_ven_amd_aqlprofile_version_major).restype, hsa_ven_amd_aqlprofile_version_major.argtypes = uint32_t, [] +except AttributeError: pass -union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0._pack_ = 1 # source:False -union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0._fields_ = [ - ('pmc_data', struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data), - ('trace_data', hsa_ven_amd_aqlprofile_descriptor_t), - ('PADDING_0', ctypes.c_ubyte * 8), +# uint32_t hsa_ven_amd_aqlprofile_version_minor() +try: (hsa_ven_amd_aqlprofile_version_minor:=dll.hsa_ven_amd_aqlprofile_version_minor).restype, hsa_ven_amd_aqlprofile_version_minor.argtypes = uint32_t, [] +except AttributeError: pass + +hsa_ven_amd_aqlprofile_event_type_t = CEnum(ctypes.c_uint32) +HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC = hsa_ven_amd_aqlprofile_event_type_t.define('HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC', 0) +HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE = hsa_ven_amd_aqlprofile_event_type_t.define('HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE', 1) + +hsa_ven_amd_aqlprofile_block_name_t = CEnum(ctypes.c_uint32) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC', 0) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF', 1) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS', 2) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM', 3) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE', 4) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI', 5) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ', 6) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS', 7) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM', 8) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX', 9) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA', 10) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA', 11) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC', 12) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP', 13) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD', 14) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB', 15) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB', 16) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM', 17) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ', 18) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2 = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2', 19) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR', 20) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC', 21) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2 = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2', 22) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA', 23) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB', 24) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA', 25) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A', 26) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C', 27) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A', 28) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C', 29) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR', 30) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS', 31) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC', 32) +HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA', 33) +HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER = hsa_ven_amd_aqlprofile_block_name_t.define('HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER', 34) + +class hsa_ven_amd_aqlprofile_event_t(Struct): pass +hsa_ven_amd_aqlprofile_event_t._fields_ = [ + ('block_name', hsa_ven_amd_aqlprofile_block_name_t), + ('block_index', uint32_t), + ('counter_id', uint32_t), ] +# hsa_status_t hsa_ven_amd_aqlprofile_validate_event(hsa_agent_t agent, const hsa_ven_amd_aqlprofile_event_t *event, bool *result) +try: (hsa_ven_amd_aqlprofile_validate_event:=dll.hsa_ven_amd_aqlprofile_validate_event).restype, hsa_ven_amd_aqlprofile_validate_event.argtypes = hsa_status_t, [hsa_agent_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_event_t), ctypes.POINTER(ctypes.c_bool)] +except AttributeError: pass -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t._anonymous_ = ('_0',) -struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t._fields_ = [ - ('sample_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0), +hsa_ven_amd_aqlprofile_parameter_name_t = CEnum(ctypes.c_uint32) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET', 0) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK', 1) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK', 2) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK', 3) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2 = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2', 4) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK', 5) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE', 6) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT', 7) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION', 8) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE', 9) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE', 10) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK', 240) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL', 241) +HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME = hsa_ven_amd_aqlprofile_parameter_name_t.define('HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME', 242) + +class hsa_ven_amd_aqlprofile_parameter_t(Struct): pass +hsa_ven_amd_aqlprofile_parameter_t._fields_ = [ + ('parameter_name', hsa_ven_amd_aqlprofile_parameter_name_t), + ('value', uint32_t), ] +hsa_ven_amd_aqlprofile_att_marker_channel_t = CEnum(ctypes.c_uint32) +HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0 = hsa_ven_amd_aqlprofile_att_marker_channel_t.define('HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0', 0) +HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1 = hsa_ven_amd_aqlprofile_att_marker_channel_t.define('HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1', 1) +HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2 = hsa_ven_amd_aqlprofile_att_marker_channel_t.define('HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2', 2) +HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3 = hsa_ven_amd_aqlprofile_att_marker_channel_t.define('HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3', 3) -hsa_ven_amd_aqlprofile_info_data_t = struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t -class struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t(Structure): - pass - -struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t._pack_ = 1 # source:False -struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t._fields_ = [ - ('name', ctypes.POINTER(ctypes.c_char)), - ('id', ctypes.c_uint32), - ('instance_count', ctypes.c_uint32), +class hsa_ven_amd_aqlprofile_descriptor_t(Struct): pass +hsa_ven_amd_aqlprofile_descriptor_t._fields_ = [ + ('ptr', ctypes.c_void_p), + ('size', uint32_t), ] +class hsa_ven_amd_aqlprofile_profile_t(Struct): pass +hsa_ven_amd_aqlprofile_profile_t._fields_ = [ + ('agent', hsa_agent_t), + ('type', hsa_ven_amd_aqlprofile_event_type_t), + ('events', ctypes.POINTER(hsa_ven_amd_aqlprofile_event_t)), + ('event_count', uint32_t), + ('parameters', ctypes.POINTER(hsa_ven_amd_aqlprofile_parameter_t)), + ('parameter_count', uint32_t), + ('output_buffer', hsa_ven_amd_aqlprofile_descriptor_t), + ('command_buffer', hsa_ven_amd_aqlprofile_descriptor_t), +] +class hsa_ext_amd_aql_pm4_packet_t(Struct): pass +hsa_ext_amd_aql_pm4_packet_t._fields_ = [ + ('header', uint16_t), + ('pm4_command', (uint16_t * 27)), + ('completion_signal', hsa_signal_t), +] +# hsa_status_t hsa_ven_amd_aqlprofile_start(hsa_ven_amd_aqlprofile_profile_t *profile, hsa_ext_amd_aql_pm4_packet_t *aql_start_packet) +try: (hsa_ven_amd_aqlprofile_start:=dll.hsa_ven_amd_aqlprofile_start).restype, hsa_ven_amd_aqlprofile_start.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t)] +except AttributeError: pass -hsa_ven_amd_aqlprofile_id_query_t = struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t +# hsa_status_t hsa_ven_amd_aqlprofile_stop(const hsa_ven_amd_aqlprofile_profile_t *profile, hsa_ext_amd_aql_pm4_packet_t *aql_stop_packet) +try: (hsa_ven_amd_aqlprofile_stop:=dll.hsa_ven_amd_aqlprofile_stop).restype, hsa_ven_amd_aqlprofile_stop.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t)] +except AttributeError: pass -# values for enumeration 'c__EA_hsa_ven_amd_aqlprofile_info_type_t' -c__EA_hsa_ven_amd_aqlprofile_info_type_t__enumvalues = { - 0: 'HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE', - 1: 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE', - 2: 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA', - 3: 'HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA', - 4: 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS', - 5: 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID', - 6: 'HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD', - 7: 'HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD', -} -HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE = 0 -HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE = 1 -HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA = 2 -HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA = 3 -HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS = 4 -HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID = 5 -HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD = 6 -HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD = 7 -c__EA_hsa_ven_amd_aqlprofile_info_type_t = ctypes.c_uint32 # enum -hsa_ven_amd_aqlprofile_info_type_t = c__EA_hsa_ven_amd_aqlprofile_info_type_t -hsa_ven_amd_aqlprofile_info_type_t__enumvalues = c__EA_hsa_ven_amd_aqlprofile_info_type_t__enumvalues -hsa_ven_amd_aqlprofile_data_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, c__EA_hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t), ctypes.POINTER(None)) -try: - hsa_ven_amd_aqlprofile_get_info = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_get_info - hsa_ven_amd_aqlprofile_get_info.restype = hsa_status_t - hsa_ven_amd_aqlprofile_get_info.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_iterate_data = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_iterate_data - hsa_ven_amd_aqlprofile_iterate_data.restype = hsa_status_t - hsa_ven_amd_aqlprofile_iterate_data.argtypes = [ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_data_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - hsa_ven_amd_aqlprofile_error_string = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_error_string - hsa_ven_amd_aqlprofile_error_string.restype = hsa_status_t - hsa_ven_amd_aqlprofile_error_string.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -hsa_ven_amd_aqlprofile_eventname_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_char)) -try: - hsa_ven_amd_aqlprofile_iterate_event_ids = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_iterate_event_ids - hsa_ven_amd_aqlprofile_iterate_event_ids.restype = hsa_status_t - hsa_ven_amd_aqlprofile_iterate_event_ids.argtypes = [hsa_ven_amd_aqlprofile_eventname_callback_t] -except AttributeError: - pass -hsa_ven_amd_aqlprofile_coordinate_callback_t = ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)) -try: - hsa_ven_amd_aqlprofile_iterate_event_coord = _libraries['FIXME_STUB'].hsa_ven_amd_aqlprofile_iterate_event_coord - hsa_ven_amd_aqlprofile_iterate_event_coord.restype = hsa_status_t - hsa_ven_amd_aqlprofile_iterate_event_coord.argtypes = [hsa_agent_t, hsa_ven_amd_aqlprofile_event_t, uint32_t, hsa_ven_amd_aqlprofile_coordinate_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -kAqlProfileLib = 'libhsa-amd-aqlprofile64.so' # Variable ctypes.c_char * 27 -class struct_hsa_ven_amd_aqlprofile_1_00_pfn_s(Structure): - pass +# hsa_status_t hsa_ven_amd_aqlprofile_read(const hsa_ven_amd_aqlprofile_profile_t *profile, hsa_ext_amd_aql_pm4_packet_t *aql_read_packet) +try: (hsa_ven_amd_aqlprofile_read:=dll.hsa_ven_amd_aqlprofile_read).restype, hsa_ven_amd_aqlprofile_read.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t)] +except AttributeError: pass -struct_hsa_ven_amd_aqlprofile_1_00_pfn_s._pack_ = 1 # source:False +try: HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE = ctypes.c_uint32.in_dll(dll, 'HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE') +except (ValueError,AttributeError): pass +# hsa_status_t hsa_ven_amd_aqlprofile_legacy_get_pm4(const hsa_ext_amd_aql_pm4_packet_t *aql_packet, void *data) +try: (hsa_ven_amd_aqlprofile_legacy_get_pm4:=dll.hsa_ven_amd_aqlprofile_legacy_get_pm4).restype, hsa_ven_amd_aqlprofile_legacy_get_pm4.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t), ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_ven_amd_aqlprofile_att_marker(hsa_ven_amd_aqlprofile_profile_t *profile, hsa_ext_amd_aql_pm4_packet_t *aql_marker_packet, uint32_t data, hsa_ven_amd_aqlprofile_att_marker_channel_t channel) +try: (hsa_ven_amd_aqlprofile_att_marker:=dll.hsa_ven_amd_aqlprofile_att_marker).restype, hsa_ven_amd_aqlprofile_att_marker.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t), uint32_t, hsa_ven_amd_aqlprofile_att_marker_channel_t] +except AttributeError: pass + +class hsa_ven_amd_aqlprofile_info_data_t(Struct): pass +class hsa_ven_amd_aqlprofile_info_data_t_0(ctypes.Union): pass +class hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data(Struct): pass +hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data._fields_ = [ + ('event', hsa_ven_amd_aqlprofile_event_t), + ('result', uint64_t), +] +hsa_ven_amd_aqlprofile_info_data_t_0._fields_ = [ + ('pmc_data', hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data), + ('trace_data', hsa_ven_amd_aqlprofile_descriptor_t), +] +hsa_ven_amd_aqlprofile_info_data_t._anonymous_ = ['_0'] +hsa_ven_amd_aqlprofile_info_data_t._fields_ = [ + ('sample_id', uint32_t), + ('_0', hsa_ven_amd_aqlprofile_info_data_t_0), +] +class hsa_ven_amd_aqlprofile_id_query_t(Struct): pass +hsa_ven_amd_aqlprofile_id_query_t._fields_ = [ + ('name', ctypes.POINTER(ctypes.c_char)), + ('id', uint32_t), + ('instance_count', uint32_t), +] +hsa_ven_amd_aqlprofile_info_type_t = CEnum(ctypes.c_uint32) +HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE', 0) +HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE', 1) +HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA', 2) +HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA', 3) +HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS', 4) +HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID', 5) +HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD', 6) +HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD = hsa_ven_amd_aqlprofile_info_type_t.define('HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD', 7) + +hsa_ven_amd_aqlprofile_data_callback_t = ctypes.CFUNCTYPE(hsa_status_t, hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_info_data_t), ctypes.c_void_p) +# hsa_status_t hsa_ven_amd_aqlprofile_get_info(const hsa_ven_amd_aqlprofile_profile_t *profile, hsa_ven_amd_aqlprofile_info_type_t attribute, void *value) +try: (hsa_ven_amd_aqlprofile_get_info:=dll.hsa_ven_amd_aqlprofile_get_info).restype, hsa_ven_amd_aqlprofile_get_info.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_info_type_t, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_ven_amd_aqlprofile_iterate_data(const hsa_ven_amd_aqlprofile_profile_t *profile, hsa_ven_amd_aqlprofile_data_callback_t callback, void *data) +try: (hsa_ven_amd_aqlprofile_iterate_data:=dll.hsa_ven_amd_aqlprofile_iterate_data).restype, hsa_ven_amd_aqlprofile_iterate_data.argtypes = hsa_status_t, [ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_data_callback_t, ctypes.c_void_p] +except AttributeError: pass + +# hsa_status_t hsa_ven_amd_aqlprofile_error_string(const char **str) +try: (hsa_ven_amd_aqlprofile_error_string:=dll.hsa_ven_amd_aqlprofile_error_string).restype, hsa_ven_amd_aqlprofile_error_string.argtypes = hsa_status_t, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +hsa_ven_amd_aqlprofile_eventname_callback_t = ctypes.CFUNCTYPE(hsa_status_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_char)) +# hsa_status_t hsa_ven_amd_aqlprofile_iterate_event_ids(hsa_ven_amd_aqlprofile_eventname_callback_t) +try: (hsa_ven_amd_aqlprofile_iterate_event_ids:=dll.hsa_ven_amd_aqlprofile_iterate_event_ids).restype, hsa_ven_amd_aqlprofile_iterate_event_ids.argtypes = hsa_status_t, [hsa_ven_amd_aqlprofile_eventname_callback_t] +except AttributeError: pass + +hsa_ven_amd_aqlprofile_coordinate_callback_t = ctypes.CFUNCTYPE(hsa_status_t, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p) +# hsa_status_t hsa_ven_amd_aqlprofile_iterate_event_coord(hsa_agent_t agent, hsa_ven_amd_aqlprofile_event_t event, uint32_t sample_id, hsa_ven_amd_aqlprofile_coordinate_callback_t callback, void *userdata) +try: (hsa_ven_amd_aqlprofile_iterate_event_coord:=dll.hsa_ven_amd_aqlprofile_iterate_event_coord).restype, hsa_ven_amd_aqlprofile_iterate_event_coord.argtypes = hsa_status_t, [hsa_agent_t, hsa_ven_amd_aqlprofile_event_t, uint32_t, hsa_ven_amd_aqlprofile_coordinate_callback_t, ctypes.c_void_p] +except AttributeError: pass + +class struct_hsa_ven_amd_aqlprofile_1_00_pfn_s(Struct): pass struct_hsa_ven_amd_aqlprofile_1_00_pfn_s._fields_ = [ - ('hsa_ven_amd_aqlprofile_version_major', ctypes.CFUNCTYPE(ctypes.c_uint32)), - ('hsa_ven_amd_aqlprofile_version_minor', ctypes.CFUNCTYPE(ctypes.c_uint32)), - ('hsa_ven_amd_aqlprofile_error_string', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)))), - ('hsa_ven_amd_aqlprofile_validate_event', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_event_t), ctypes.POINTER(ctypes.c_bool))), - ('hsa_ven_amd_aqlprofile_start', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t))), - ('hsa_ven_amd_aqlprofile_stop', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t))), - ('hsa_ven_amd_aqlprofile_read', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t))), - ('hsa_ven_amd_aqlprofile_legacy_get_pm4', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_get_info', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), c__EA_hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_iterate_data', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.CFUNCTYPE(c__EA_hsa_status_t, c__EA_hsa_ven_amd_aqlprofile_info_type_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t), ctypes.POINTER(None)), ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_iterate_event_ids', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_char)))), - ('hsa_ven_amd_aqlprofile_iterate_event_coord', ctypes.CFUNCTYPE(c__EA_hsa_status_t, struct_hsa_agent_s, struct_c__SA_hsa_ven_amd_aqlprofile_event_t, ctypes.c_uint32, ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(None))), - ('hsa_ven_amd_aqlprofile_att_marker', ctypes.CFUNCTYPE(c__EA_hsa_status_t, ctypes.POINTER(struct_c__SA_hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(struct_c__SA_hsa_ext_amd_aql_pm4_packet_t), ctypes.c_uint32, c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t)), + ('hsa_ven_amd_aqlprofile_version_major', ctypes.CFUNCTYPE(uint32_t)), + ('hsa_ven_amd_aqlprofile_version_minor', ctypes.CFUNCTYPE(uint32_t)), + ('hsa_ven_amd_aqlprofile_error_string', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)))), + ('hsa_ven_amd_aqlprofile_validate_event', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_event_t), ctypes.POINTER(ctypes.c_bool))), + ('hsa_ven_amd_aqlprofile_start', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t))), + ('hsa_ven_amd_aqlprofile_stop', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t))), + ('hsa_ven_amd_aqlprofile_read', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t))), + ('hsa_ven_amd_aqlprofile_legacy_get_pm4', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t), ctypes.c_void_p)), + ('hsa_ven_amd_aqlprofile_get_info', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_info_type_t, ctypes.c_void_p)), + ('hsa_ven_amd_aqlprofile_iterate_data', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), hsa_ven_amd_aqlprofile_data_callback_t, ctypes.c_void_p)), + ('hsa_ven_amd_aqlprofile_iterate_event_ids', ctypes.CFUNCTYPE(hsa_status_t, hsa_ven_amd_aqlprofile_eventname_callback_t)), + ('hsa_ven_amd_aqlprofile_iterate_event_coord', ctypes.CFUNCTYPE(hsa_status_t, hsa_agent_t, hsa_ven_amd_aqlprofile_event_t, uint32_t, hsa_ven_amd_aqlprofile_coordinate_callback_t, ctypes.c_void_p)), + ('hsa_ven_amd_aqlprofile_att_marker', ctypes.CFUNCTYPE(hsa_status_t, ctypes.POINTER(hsa_ven_amd_aqlprofile_profile_t), ctypes.POINTER(hsa_ext_amd_aql_pm4_packet_t), uint32_t, hsa_ven_amd_aqlprofile_att_marker_channel_t)), ] - hsa_ven_amd_aqlprofile_1_00_pfn_t = struct_hsa_ven_amd_aqlprofile_1_00_pfn_s hsa_ven_amd_aqlprofile_pfn_t = struct_hsa_ven_amd_aqlprofile_1_00_pfn_s -__all__ = \ - ['AMD_COMPUTE_PGM_RSRC_ONE_BULKY', - 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_BULKY_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER', - 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE', - 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_PRIV_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1', - 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_ONE_RESERVED1_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE', - 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1', - 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1_WIDTH', - 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT', - 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT', - 'AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_WIDTH', - 'AMD_ELEMENT_BYTE_SIZE_16', 'AMD_ELEMENT_BYTE_SIZE_2', - 'AMD_ELEMENT_BYTE_SIZE_4', 'AMD_ELEMENT_BYTE_SIZE_8', - 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS', - 'AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS', - 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE', - 'AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS', - 'AMD_EXCEPTION_KIND_DIVISION_BY_ZERO', - 'AMD_EXCEPTION_KIND_INEXACT', - 'AMD_EXCEPTION_KIND_INVALID_OPERATION', - 'AMD_EXCEPTION_KIND_OVERFLOW', 'AMD_EXCEPTION_KIND_UNDERFLOW', - 'AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT', - 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE', - 'AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT', - 'AMD_FLOAT_DENORM_MODE_NO_FLUSH', - 'AMD_FLOAT_ROUND_MODE_MINUS_INFINITY', - 'AMD_FLOAT_ROUND_MODE_NEAREST_EVEN', - 'AMD_FLOAT_ROUND_MODE_PLUS_INFINITY', 'AMD_FLOAT_ROUND_MODE_ZERO', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64', - 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_PTR64_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED', - 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE', - 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED1_WIDTH', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_SHIFT', - 'AMD_KERNEL_CODE_PROPERTIES_RESERVED2_WIDTH', - 'AMD_KERNEL_CODE_VERSION_MAJOR', 'AMD_KERNEL_CODE_VERSION_MINOR', - 'AMD_MACHINE_KIND_AMDGPU', 'AMD_MACHINE_KIND_UNDEFINED', - 'AMD_POWERTWO_1', 'AMD_POWERTWO_128', 'AMD_POWERTWO_16', - 'AMD_POWERTWO_2', 'AMD_POWERTWO_256', 'AMD_POWERTWO_32', - 'AMD_POWERTWO_4', 'AMD_POWERTWO_64', 'AMD_POWERTWO_8', - 'AMD_QUEUE_CAPS_ASYNC_RECLAIM', - 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_SHIFT', - 'AMD_QUEUE_CAPS_ASYNC_RECLAIM_WIDTH', - 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING', - 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_SHIFT', - 'AMD_QUEUE_PROPERTIES_ENABLE_PROFILING_WIDTH', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_SHIFT', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_DEBUG_SGPRS_WIDTH', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_SHIFT', - 'AMD_QUEUE_PROPERTIES_ENABLE_TRAP_HANDLER_WIDTH', - 'AMD_QUEUE_PROPERTIES_IS_PTR64', - 'AMD_QUEUE_PROPERTIES_IS_PTR64_SHIFT', - 'AMD_QUEUE_PROPERTIES_IS_PTR64_WIDTH', - 'AMD_QUEUE_PROPERTIES_RESERVED1', - 'AMD_QUEUE_PROPERTIES_RESERVED1_SHIFT', - 'AMD_QUEUE_PROPERTIES_RESERVED1_WIDTH', - 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE', - 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_SHIFT', - 'AMD_QUEUE_PROPERTIES_USE_SCRATCH_ONCE_WIDTH', - 'AMD_SIGNAL_KIND_DOORBELL', 'AMD_SIGNAL_KIND_INVALID', - 'AMD_SIGNAL_KIND_LEGACY_DOORBELL', 'AMD_SIGNAL_KIND_USER', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_X', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y', - 'AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z', 'BrigModule_t', - 'HSA_ACCESS_PERMISSION_NONE', 'HSA_ACCESS_PERMISSION_RO', - 'HSA_ACCESS_PERMISSION_RW', 'HSA_ACCESS_PERMISSION_WO', - 'HSA_AGENT_FEATURE_AGENT_DISPATCH', - 'HSA_AGENT_FEATURE_KERNEL_DISPATCH', - 'HSA_AGENT_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 'HSA_AGENT_INFO_CACHE_SIZE', - 'HSA_AGENT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_AGENT_INFO_DEVICE', 'HSA_AGENT_INFO_EXTENSIONS', - 'HSA_AGENT_INFO_FAST_F16_OPERATION', - 'HSA_AGENT_INFO_FBARRIER_MAX_SIZE', 'HSA_AGENT_INFO_FEATURE', - 'HSA_AGENT_INFO_GRID_MAX_DIM', 'HSA_AGENT_INFO_GRID_MAX_SIZE', - 'HSA_AGENT_INFO_ISA', 'HSA_AGENT_INFO_LAST', - 'HSA_AGENT_INFO_MACHINE_MODEL', 'HSA_AGENT_INFO_NAME', - 'HSA_AGENT_INFO_NODE', 'HSA_AGENT_INFO_PROFILE', - 'HSA_AGENT_INFO_QUEUES_MAX', 'HSA_AGENT_INFO_QUEUE_MAX_SIZE', - 'HSA_AGENT_INFO_QUEUE_MIN_SIZE', 'HSA_AGENT_INFO_QUEUE_TYPE', - 'HSA_AGENT_INFO_VENDOR_NAME', 'HSA_AGENT_INFO_VERSION_MAJOR', - 'HSA_AGENT_INFO_VERSION_MINOR', 'HSA_AGENT_INFO_WAVEFRONT_SIZE', - 'HSA_AGENT_INFO_WORKGROUP_MAX_DIM', - 'HSA_AGENT_INFO_WORKGROUP_MAX_SIZE', - 'HSA_AMD_AGENT_INFO_AQL_EXTENSIONS', - 'HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID', - 'HSA_AMD_AGENT_INFO_ASIC_REVISION', 'HSA_AMD_AGENT_INFO_BDFID', - 'HSA_AMD_AGENT_INFO_CACHELINE_SIZE', 'HSA_AMD_AGENT_INFO_CHIP_ID', - 'HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT', - 'HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT', - 'HSA_AMD_AGENT_INFO_COOPERATIVE_QUEUES', - 'HSA_AMD_AGENT_INFO_DOMAIN', 'HSA_AMD_AGENT_INFO_DRIVER_NODE_ID', - 'HSA_AMD_AGENT_INFO_DRIVER_UID', 'HSA_AMD_AGENT_INFO_HDP_FLUSH', - 'HSA_AMD_AGENT_INFO_IOMMU_SUPPORT', - 'HSA_AMD_AGENT_INFO_MAX_ADDRESS_WATCH_POINTS', - 'HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY', - 'HSA_AMD_AGENT_INFO_MAX_WAVES_PER_CU', - 'HSA_AMD_AGENT_INFO_MEMORY_AVAIL', - 'HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY', - 'HSA_AMD_AGENT_INFO_MEMORY_PROPERTIES', - 'HSA_AMD_AGENT_INFO_MEMORY_WIDTH', - 'HSA_AMD_AGENT_INFO_NEAREST_CPU', - 'HSA_AMD_AGENT_INFO_NUM_SDMA_ENG', - 'HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG', - 'HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE', - 'HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES', - 'HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU', - 'HSA_AMD_AGENT_INFO_NUM_XCC', 'HSA_AMD_AGENT_INFO_PRODUCT_NAME', - 'HSA_AMD_AGENT_INFO_SDMA_UCODE_VERSION', - 'HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS', - 'HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY', - 'HSA_AMD_AGENT_INFO_UCODE_VERSION', 'HSA_AMD_AGENT_INFO_UUID', - 'HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS', - 'HSA_AMD_AGENT_MEMORY_POOL_INFO_LINK_INFO', - 'HSA_AMD_AGENT_MEMORY_POOL_INFO_NUM_LINK_HOPS', - 'HSA_AMD_COHERENCY_TYPE_COHERENT', - 'HSA_AMD_COHERENCY_TYPE_NONCOHERENT', 'HSA_AMD_FIRST_EXTENSION', - 'HSA_AMD_GPU_HW_EXCEPTION_EVENT', - 'HSA_AMD_GPU_MEMORY_FAULT_EVENT', - 'HSA_AMD_HW_EXCEPTION_CAUSE_ECC', - 'HSA_AMD_HW_EXCEPTION_CAUSE_GPU_HANG', - 'HSA_AMD_HW_EXCEPTION_RESET_TYPE_OTHER', 'HSA_AMD_LAST_EXTENSION', - 'HSA_AMD_LINK_INFO_TYPE_HYPERTRANSPORT', - 'HSA_AMD_LINK_INFO_TYPE_INFINBAND', 'HSA_AMD_LINK_INFO_TYPE_PCIE', - 'HSA_AMD_LINK_INFO_TYPE_QPI', 'HSA_AMD_LINK_INFO_TYPE_XGMI', - 'HSA_AMD_MEMORY_FAULT_DRAMECC', 'HSA_AMD_MEMORY_FAULT_HANG', - 'HSA_AMD_MEMORY_FAULT_HOST_ONLY', - 'HSA_AMD_MEMORY_FAULT_IMPRECISE', 'HSA_AMD_MEMORY_FAULT_NX', - 'HSA_AMD_MEMORY_FAULT_PAGE_NOT_PRESENT', - 'HSA_AMD_MEMORY_FAULT_READ_ONLY', 'HSA_AMD_MEMORY_FAULT_SRAMECC', - 'HSA_AMD_MEMORY_POOL_ACCESS_ALLOWED_BY_DEFAULT', - 'HSA_AMD_MEMORY_POOL_ACCESS_DISALLOWED_BY_DEFAULT', - 'HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED', - 'HSA_AMD_MEMORY_POOL_CONTIGUOUS_FLAG', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_FINE_GRAINED', - 'HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_KERNARG_INIT', - 'HSA_AMD_MEMORY_POOL_INFO_ACCESSIBLE_BY_ALL', - 'HSA_AMD_MEMORY_POOL_INFO_ALLOC_MAX_SIZE', - 'HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS', - 'HSA_AMD_MEMORY_POOL_INFO_LOCATION', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALIGNMENT', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_ALLOWED', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE', - 'HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_REC_GRANULE', - 'HSA_AMD_MEMORY_POOL_INFO_SEGMENT', - 'HSA_AMD_MEMORY_POOL_INFO_SIZE', - 'HSA_AMD_MEMORY_POOL_LOCATION_CPU', - 'HSA_AMD_MEMORY_POOL_LOCATION_GPU', - 'HSA_AMD_MEMORY_POOL_PCIE_FLAG', - 'HSA_AMD_MEMORY_POOL_STANDARD_FLAG', - 'HSA_AMD_MEMORY_PROPERTY_AGENT_IS_APU', - 'HSA_AMD_PACKET_TYPE_BARRIER_VALUE', 'HSA_AMD_QUEUE_INFO_AGENT', - 'HSA_AMD_QUEUE_INFO_DOORBELL_ID', 'HSA_AMD_QUEUE_PRIORITY_HIGH', - 'HSA_AMD_QUEUE_PRIORITY_LOW', 'HSA_AMD_QUEUE_PRIORITY_NORMAL', - 'HSA_AMD_REGION_INFO_BASE', 'HSA_AMD_REGION_INFO_BUS_WIDTH', - 'HSA_AMD_REGION_INFO_HOST_ACCESSIBLE', - 'HSA_AMD_REGION_INFO_MAX_CLOCK_FREQUENCY', - 'HSA_AMD_SDMA_ENGINE_0', 'HSA_AMD_SDMA_ENGINE_1', - 'HSA_AMD_SDMA_ENGINE_10', 'HSA_AMD_SDMA_ENGINE_11', - 'HSA_AMD_SDMA_ENGINE_12', 'HSA_AMD_SDMA_ENGINE_13', - 'HSA_AMD_SDMA_ENGINE_14', 'HSA_AMD_SDMA_ENGINE_15', - 'HSA_AMD_SDMA_ENGINE_2', 'HSA_AMD_SDMA_ENGINE_3', - 'HSA_AMD_SDMA_ENGINE_4', 'HSA_AMD_SDMA_ENGINE_5', - 'HSA_AMD_SDMA_ENGINE_6', 'HSA_AMD_SDMA_ENGINE_7', - 'HSA_AMD_SDMA_ENGINE_8', 'HSA_AMD_SDMA_ENGINE_9', - 'HSA_AMD_SEGMENT_GLOBAL', 'HSA_AMD_SEGMENT_GROUP', - 'HSA_AMD_SEGMENT_PRIVATE', 'HSA_AMD_SEGMENT_READONLY', - 'HSA_AMD_SIGNAL_AMD_GPU_ONLY', 'HSA_AMD_SIGNAL_IPC', - 'HSA_AMD_SVM_ATTRIB_ACCESS_QUERY', - 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE', - 'HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE', - 'HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS', - 'HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG', 'HSA_AMD_SVM_ATTRIB_GPU_EXEC', - 'HSA_AMD_SVM_ATTRIB_HIVE_LOCAL', - 'HSA_AMD_SVM_ATTRIB_MIGRATION_GRANULARITY', - 'HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION', - 'HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION', - 'HSA_AMD_SVM_ATTRIB_READ_MOSTLY', 'HSA_AMD_SVM_ATTRIB_READ_ONLY', - 'HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED', - 'HSA_AMD_SVM_GLOBAL_FLAG_FINE_GRAINED', - 'HSA_AMD_SVM_GLOBAL_FLAG_INDETERMINATE', - 'HSA_AMD_SYSTEM_INFO_BUILD_VERSION', - 'HSA_AMD_SYSTEM_INFO_DMABUF_SUPPORTED', - 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MAJOR', - 'HSA_AMD_SYSTEM_INFO_EXT_VERSION_MINOR', - 'HSA_AMD_SYSTEM_INFO_MWAITX_ENABLED', - 'HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT', - 'HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED', - 'HSA_AMD_SYSTEM_INFO_VIRTUAL_MEM_API_SUPPORTED', - 'HSA_AMD_SYSTEM_INFO_XNACK_ENABLED', 'HSA_CACHE_INFO_LEVEL', - 'HSA_CACHE_INFO_NAME', 'HSA_CACHE_INFO_NAME_LENGTH', - 'HSA_CACHE_INFO_SIZE', - 'HSA_CODE_OBJECT_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_CODE_OBJECT_INFO_ISA', 'HSA_CODE_OBJECT_INFO_MACHINE_MODEL', - 'HSA_CODE_OBJECT_INFO_PROFILE', 'HSA_CODE_OBJECT_INFO_TYPE', - 'HSA_CODE_OBJECT_INFO_VERSION', 'HSA_CODE_OBJECT_TYPE_PROGRAM', - 'HSA_CODE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', - 'HSA_CODE_SYMBOL_INFO_IS_DEFINITION', - 'HSA_CODE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 'HSA_CODE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 'HSA_CODE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 'HSA_CODE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 'HSA_CODE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 'HSA_CODE_SYMBOL_INFO_KERNEL_WAVEFRONT_SIZE', - 'HSA_CODE_SYMBOL_INFO_LINKAGE', - 'HSA_CODE_SYMBOL_INFO_MODULE_NAME', - 'HSA_CODE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 'HSA_CODE_SYMBOL_INFO_NAME', 'HSA_CODE_SYMBOL_INFO_NAME_LENGTH', - 'HSA_CODE_SYMBOL_INFO_TYPE', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_IS_CONST', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_SEGMENT', - 'HSA_CODE_SYMBOL_INFO_VARIABLE_SIZE', - 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_DEFAULT', - 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_NEAR', - 'HSA_DEFAULT_FLOAT_ROUNDING_MODE_ZERO', 'HSA_DEVICE_TYPE_CPU', - 'HSA_DEVICE_TYPE_DSP', 'HSA_DEVICE_TYPE_GPU', - 'HSA_ENDIANNESS_BIG', 'HSA_ENDIANNESS_LITTLE', - 'HSA_EXCEPTION_POLICY_BREAK', 'HSA_EXCEPTION_POLICY_DETECT', - 'HSA_EXECUTABLE_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_EXECUTABLE_INFO_PROFILE', 'HSA_EXECUTABLE_INFO_STATE', - 'HSA_EXECUTABLE_STATE_FROZEN', 'HSA_EXECUTABLE_STATE_UNFROZEN', - 'HSA_EXECUTABLE_SYMBOL_INFO_AGENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_CALL_CONVENTION', - 'HSA_EXECUTABLE_SYMBOL_INFO_INDIRECT_FUNCTION_OBJECT', - 'HSA_EXECUTABLE_SYMBOL_INFO_IS_DEFINITION', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_CALL_CONVENTION', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_DYNAMIC_CALLSTACK', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_GROUP_SEGMENT_SIZE', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_ALIGNMENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_KERNARG_SEGMENT_SIZE', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT', - 'HSA_EXECUTABLE_SYMBOL_INFO_KERNEL_PRIVATE_SEGMENT_SIZE', - 'HSA_EXECUTABLE_SYMBOL_INFO_LINKAGE', - 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME', - 'HSA_EXECUTABLE_SYMBOL_INFO_MODULE_NAME_LENGTH', - 'HSA_EXECUTABLE_SYMBOL_INFO_NAME', - 'HSA_EXECUTABLE_SYMBOL_INFO_NAME_LENGTH', - 'HSA_EXECUTABLE_SYMBOL_INFO_TYPE', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ADDRESS', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALIGNMENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_ALLOCATION', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_IS_CONST', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SEGMENT', - 'HSA_EXECUTABLE_SYMBOL_INFO_VARIABLE_SIZE', - 'HSA_EXTENSION_AMD_AQLPROFILE', 'HSA_EXTENSION_AMD_LOADER', - 'HSA_EXTENSION_AMD_PC_SAMPLING', 'HSA_EXTENSION_AMD_PROFILER', - 'HSA_EXTENSION_FINALIZER', 'HSA_EXTENSION_IMAGES', - 'HSA_EXTENSION_PERFORMANCE_COUNTERS', - 'HSA_EXTENSION_PROFILING_EVENTS', 'HSA_EXTENSION_STD_LAST', - 'HSA_EXT_AGENT_INFO_IMAGE_1DA_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_1DB_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2DADEPTH_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2DA_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2DDEPTH_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_2D_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_3D_MAX_ELEMENTS', - 'HSA_EXT_AGENT_INFO_IMAGE_ARRAY_MAX_LAYERS', - 'HSA_EXT_AGENT_INFO_IMAGE_LINEAR_ROW_PITCH_ALIGNMENT', - 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RD_HANDLES', - 'HSA_EXT_AGENT_INFO_MAX_IMAGE_RORW_HANDLES', - 'HSA_EXT_AGENT_INFO_MAX_SAMPLER_HANDLERS', - 'HSA_EXT_FINALIZER_CALL_CONVENTION_AUTO', - 'HSA_EXT_IMAGE_CAPABILITY_ACCESS_INVARIANT_DATA_LAYOUT', - 'HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED', - 'HSA_EXT_IMAGE_CAPABILITY_READ_MODIFY_WRITE', - 'HSA_EXT_IMAGE_CAPABILITY_READ_ONLY', - 'HSA_EXT_IMAGE_CAPABILITY_READ_WRITE', - 'HSA_EXT_IMAGE_CAPABILITY_WRITE_ONLY', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_A', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_R', 'HSA_EXT_IMAGE_CHANNEL_ORDER_RA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RG', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGB', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RGX', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_RX', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA', - 'HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_FLOAT', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_HALF_FLOAT', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT32', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SIGNED_INT8', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_SNORM_INT8', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT24', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_INT8', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32', - 'HSA_EXT_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8', - 'HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR', - 'HSA_EXT_IMAGE_DATA_LAYOUT_OPAQUE', 'HSA_EXT_IMAGE_GEOMETRY_1D', - 'HSA_EXT_IMAGE_GEOMETRY_1DA', 'HSA_EXT_IMAGE_GEOMETRY_1DB', - 'HSA_EXT_IMAGE_GEOMETRY_2D', 'HSA_EXT_IMAGE_GEOMETRY_2DA', - 'HSA_EXT_IMAGE_GEOMETRY_2DADEPTH', - 'HSA_EXT_IMAGE_GEOMETRY_2DDEPTH', 'HSA_EXT_IMAGE_GEOMETRY_3D', - 'HSA_EXT_POINTER_TYPE_GRAPHICS', 'HSA_EXT_POINTER_TYPE_HSA', - 'HSA_EXT_POINTER_TYPE_IPC', 'HSA_EXT_POINTER_TYPE_LOCKED', - 'HSA_EXT_POINTER_TYPE_UNKNOWN', - 'HSA_EXT_PROGRAM_INFO_DEFAULT_FLOAT_ROUNDING_MODE', - 'HSA_EXT_PROGRAM_INFO_MACHINE_MODEL', - 'HSA_EXT_PROGRAM_INFO_PROFILE', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT', - 'HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED', - 'HSA_EXT_SAMPLER_COORDINATE_MODE_NORMALIZED', - 'HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED', - 'HSA_EXT_SAMPLER_FILTER_MODE_LINEAR', - 'HSA_EXT_SAMPLER_FILTER_MODE_NEAREST', - 'HSA_EXT_STATUS_ERROR_DIRECTIVE_MISMATCH', - 'HSA_EXT_STATUS_ERROR_FINALIZATION_FAILED', - 'HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_IMAGE_SIZE_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_INCOMPATIBLE_MODULE', - 'HSA_EXT_STATUS_ERROR_INVALID_MODULE', - 'HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', - 'HSA_EXT_STATUS_ERROR_MODULE_ALREADY_INCLUDED', - 'HSA_EXT_STATUS_ERROR_SAMPLER_DESCRIPTOR_UNSUPPORTED', - 'HSA_EXT_STATUS_ERROR_SYMBOL_MISMATCH', 'HSA_FENCE_SCOPE_AGENT', - 'HSA_FENCE_SCOPE_NONE', 'HSA_FENCE_SCOPE_SYSTEM', - 'HSA_FLUSH_MODE_FTZ', 'HSA_FLUSH_MODE_NON_FTZ', 'HSA_FP_TYPE_16', - 'HSA_FP_TYPE_32', 'HSA_FP_TYPE_64', 'HSA_IOMMU_SUPPORT_NONE', - 'HSA_IOMMU_SUPPORT_V2', - 'HSA_ISA_INFO_BASE_PROFILE_DEFAULT_FLOAT_ROUNDING_MODES', - 'HSA_ISA_INFO_CALL_CONVENTION_COUNT', - 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONTS_PER_COMPUTE_UNIT', - 'HSA_ISA_INFO_CALL_CONVENTION_INFO_WAVEFRONT_SIZE', - 'HSA_ISA_INFO_DEFAULT_FLOAT_ROUNDING_MODES', - 'HSA_ISA_INFO_FAST_F16_OPERATION', - 'HSA_ISA_INFO_FBARRIER_MAX_SIZE', 'HSA_ISA_INFO_GRID_MAX_DIM', - 'HSA_ISA_INFO_GRID_MAX_SIZE', 'HSA_ISA_INFO_MACHINE_MODELS', - 'HSA_ISA_INFO_NAME', 'HSA_ISA_INFO_NAME_LENGTH', - 'HSA_ISA_INFO_PROFILES', 'HSA_ISA_INFO_WORKGROUP_MAX_DIM', - 'HSA_ISA_INFO_WORKGROUP_MAX_SIZE', - 'HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS', - 'HSA_KERNEL_DISPATCH_PACKET_SETUP_WIDTH_DIMENSIONS', - 'HSA_MACHINE_MODEL_LARGE', 'HSA_MACHINE_MODEL_SMALL', - 'HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_BARRIER', - 'HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_TYPE', - 'HSA_PACKET_HEADER_WIDTH_ACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_BARRIER', - 'HSA_PACKET_HEADER_WIDTH_RELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_SCACQUIRE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_SCRELEASE_FENCE_SCOPE', - 'HSA_PACKET_HEADER_WIDTH_TYPE', 'HSA_PACKET_TYPE_AGENT_DISPATCH', - 'HSA_PACKET_TYPE_BARRIER_AND', 'HSA_PACKET_TYPE_BARRIER_OR', - 'HSA_PACKET_TYPE_INVALID', 'HSA_PACKET_TYPE_KERNEL_DISPATCH', - 'HSA_PACKET_TYPE_VENDOR_SPECIFIC', 'HSA_PROFILE_BASE', - 'HSA_PROFILE_FULL', 'HSA_QUEUE_FEATURE_AGENT_DISPATCH', - 'HSA_QUEUE_FEATURE_KERNEL_DISPATCH', 'HSA_QUEUE_TYPE_COOPERATIVE', - 'HSA_QUEUE_TYPE_MULTI', 'HSA_QUEUE_TYPE_SINGLE', - 'HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED', - 'HSA_REGION_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED', - 'HSA_REGION_GLOBAL_FLAG_FINE_GRAINED', - 'HSA_REGION_GLOBAL_FLAG_KERNARG', - 'HSA_REGION_INFO_ALLOC_MAX_PRIVATE_WORKGROUP_SIZE', - 'HSA_REGION_INFO_ALLOC_MAX_SIZE', 'HSA_REGION_INFO_GLOBAL_FLAGS', - 'HSA_REGION_INFO_RUNTIME_ALLOC_ALIGNMENT', - 'HSA_REGION_INFO_RUNTIME_ALLOC_ALLOWED', - 'HSA_REGION_INFO_RUNTIME_ALLOC_GRANULE', - 'HSA_REGION_INFO_SEGMENT', 'HSA_REGION_INFO_SIZE', - 'HSA_REGION_SEGMENT_GLOBAL', 'HSA_REGION_SEGMENT_GROUP', - 'HSA_REGION_SEGMENT_KERNARG', 'HSA_REGION_SEGMENT_PRIVATE', - 'HSA_REGION_SEGMENT_READONLY', 'HSA_ROUND_METHOD_DOUBLE', - 'HSA_ROUND_METHOD_SINGLE', 'HSA_SIGNAL_CONDITION_EQ', - 'HSA_SIGNAL_CONDITION_GTE', 'HSA_SIGNAL_CONDITION_LT', - 'HSA_SIGNAL_CONDITION_NE', 'HSA_STATUS_CU_MASK_REDUCED', - 'HSA_STATUS_ERROR', 'HSA_STATUS_ERROR_EXCEPTION', - 'HSA_STATUS_ERROR_FATAL', 'HSA_STATUS_ERROR_FROZEN_EXECUTABLE', - 'HSA_STATUS_ERROR_ILLEGAL_INSTRUCTION', - 'HSA_STATUS_ERROR_INCOMPATIBLE_ARGUMENTS', - 'HSA_STATUS_ERROR_INVALID_AGENT', - 'HSA_STATUS_ERROR_INVALID_ALLOCATION', - 'HSA_STATUS_ERROR_INVALID_ARGUMENT', - 'HSA_STATUS_ERROR_INVALID_CACHE', - 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT', - 'HSA_STATUS_ERROR_INVALID_CODE_OBJECT_READER', - 'HSA_STATUS_ERROR_INVALID_CODE_SYMBOL', - 'HSA_STATUS_ERROR_INVALID_EXECUTABLE', - 'HSA_STATUS_ERROR_INVALID_EXECUTABLE_SYMBOL', - 'HSA_STATUS_ERROR_INVALID_FILE', 'HSA_STATUS_ERROR_INVALID_INDEX', - 'HSA_STATUS_ERROR_INVALID_ISA', - 'HSA_STATUS_ERROR_INVALID_ISA_NAME', - 'HSA_STATUS_ERROR_INVALID_MEMORY_POOL', - 'HSA_STATUS_ERROR_INVALID_PACKET_FORMAT', - 'HSA_STATUS_ERROR_INVALID_QUEUE', - 'HSA_STATUS_ERROR_INVALID_QUEUE_CREATION', - 'HSA_STATUS_ERROR_INVALID_REGION', - 'HSA_STATUS_ERROR_INVALID_RUNTIME_STATE', - 'HSA_STATUS_ERROR_INVALID_SIGNAL', - 'HSA_STATUS_ERROR_INVALID_SIGNAL_GROUP', - 'HSA_STATUS_ERROR_INVALID_SYMBOL_NAME', - 'HSA_STATUS_ERROR_INVALID_WAVEFRONT', - 'HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION', - 'HSA_STATUS_ERROR_MEMORY_FAULT', - 'HSA_STATUS_ERROR_NOT_INITIALIZED', - 'HSA_STATUS_ERROR_OUT_OF_REGISTERS', - 'HSA_STATUS_ERROR_OUT_OF_RESOURCES', - 'HSA_STATUS_ERROR_REFCOUNT_OVERFLOW', - 'HSA_STATUS_ERROR_RESOURCE_BUSY', - 'HSA_STATUS_ERROR_RESOURCE_FREE', - 'HSA_STATUS_ERROR_VARIABLE_ALREADY_DEFINED', - 'HSA_STATUS_ERROR_VARIABLE_UNDEFINED', 'HSA_STATUS_INFO_BREAK', - 'HSA_STATUS_SUCCESS', 'HSA_SYMBOL_KIND_INDIRECT_FUNCTION', - 'HSA_SYMBOL_KIND_KERNEL', 'HSA_SYMBOL_KIND_VARIABLE', - 'HSA_SYMBOL_LINKAGE_MODULE', 'HSA_SYMBOL_LINKAGE_PROGRAM', - 'HSA_SYSTEM_INFO_ENDIANNESS', 'HSA_SYSTEM_INFO_EXTENSIONS', - 'HSA_SYSTEM_INFO_MACHINE_MODEL', - 'HSA_SYSTEM_INFO_SIGNAL_MAX_WAIT', 'HSA_SYSTEM_INFO_TIMESTAMP', - 'HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY', - 'HSA_SYSTEM_INFO_VERSION_MAJOR', 'HSA_SYSTEM_INFO_VERSION_MINOR', - 'HSA_VARIABLE_ALLOCATION_AGENT', - 'HSA_VARIABLE_ALLOCATION_PROGRAM', 'HSA_VARIABLE_SEGMENT_GLOBAL', - 'HSA_VARIABLE_SEGMENT_READONLY', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_0', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_1', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_2', - 'HSA_VEN_AMD_AQLPROFILE_ATT_CHANNEL_3', - 'HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCEA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GCR', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1A', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL1C', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2A', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GL2C', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GUS', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCARB', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCHUB', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCMCBVM', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCSEQ', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCXBAR', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MMEA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_RPB', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SDMA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SRBM', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCA', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD', - 'HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_UMC', - 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_PMC', - 'HSA_VEN_AMD_AQLPROFILE_EVENT_TYPE_TRACE', - 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_COUNTERS', - 'HSA_VEN_AMD_AQLPROFILE_INFO_BLOCK_ID', - 'HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_INFO_DISABLE_CMD', - 'HSA_VEN_AMD_AQLPROFILE_INFO_ENABLE_CMD', - 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA', - 'HSA_VEN_AMD_AQLPROFILE_INFO_PMC_DATA_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA', - 'HSA_VEN_AMD_AQLPROFILE_LEGACY_PM4_PACKET_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_ATT_BUFFER_SIZE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_COMPUTE_UNIT_TARGET', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_K_CONCURRENT', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_OCCUPANCY_MODE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_CTRL', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_PERFCOUNTER_NAME', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SAMPLE_RATE', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SE_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_SIMD_SELECTION', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_TOKEN_MASK2', - 'HSA_VEN_AMD_AQLPROFILE_PARAMETER_NAME_VM_ID_MASK', - 'HSA_WAIT_STATE_ACTIVE', 'HSA_WAIT_STATE_BLOCKED', - 'HSA_WAVEFRONT_INFO_SIZE', 'MEMORY_TYPE_NONE', - 'MEMORY_TYPE_PINNED', 'amd_compute_pgm_rsrc_one32_t', - 'amd_compute_pgm_rsrc_one_t', 'amd_compute_pgm_rsrc_two32_t', - 'amd_compute_pgm_rsrc_two_t', 'amd_control_directives_t', - 'amd_element_byte_size_t', 'amd_enabled_control_directive64_t', - 'amd_enabled_control_directive_t', 'amd_exception_kind16_t', - 'amd_exception_kind_t', 'amd_float_denorm_mode_t', - 'amd_float_round_mode_t', 'amd_kernel_code_properties32_t', - 'amd_kernel_code_properties_t', 'amd_kernel_code_t', - 'amd_kernel_code_version32_t', 'amd_kernel_code_version_t', - 'amd_machine_kind16_t', 'amd_machine_kind_t', - 'amd_machine_version16_t', 'amd_powertwo8_t', 'amd_powertwo_t', - 'amd_queue_capabilities32_t', 'amd_queue_capabilities_t', - 'amd_queue_properties32_t', 'amd_queue_properties_t', - 'amd_queue_t', 'amd_runtime_loader_debug_info_t', - 'amd_signal_kind64_t', 'amd_signal_kind_t', 'amd_signal_t', - 'amd_system_vgpr_workitem_id_t', 'c__EA_hsa_access_permission_t', - 'c__EA_hsa_agent_feature_t', 'c__EA_hsa_agent_info_t', - 'c__EA_hsa_amd_agent_memory_pool_info_t', - 'c__EA_hsa_amd_copy_direction_t', - 'c__EA_hsa_amd_hw_exception_reset_cause_t', - 'c__EA_hsa_amd_hw_exception_reset_type_t', - 'c__EA_hsa_amd_iommu_version_t', 'c__EA_hsa_amd_link_info_type_t', - 'c__EA_hsa_amd_memory_fault_reason_t', - 'c__EA_hsa_amd_memory_pool_access_t', - 'c__EA_hsa_amd_memory_pool_info_t', 'c__EA_hsa_amd_memory_type_t', - 'c__EA_hsa_amd_packet_type_t', 'c__EA_hsa_amd_pointer_type_t', - 'c__EA_hsa_amd_segment_t', 'c__EA_hsa_amd_signal_attribute_t', - 'c__EA_hsa_cache_info_t', 'c__EA_hsa_code_object_info_t', - 'c__EA_hsa_code_object_type_t', 'c__EA_hsa_code_symbol_info_t', - 'c__EA_hsa_default_float_rounding_mode_t', - 'c__EA_hsa_device_type_t', 'c__EA_hsa_endianness_t', - 'c__EA_hsa_exception_policy_t', 'c__EA_hsa_executable_info_t', - 'c__EA_hsa_executable_state_t', - 'c__EA_hsa_executable_symbol_info_t', - 'c__EA_hsa_ext_finalizer_call_convention_t', - 'c__EA_hsa_ext_image_capability_t', - 'c__EA_hsa_ext_image_channel_order_t', - 'c__EA_hsa_ext_image_channel_type_t', - 'c__EA_hsa_ext_image_data_layout_t', - 'c__EA_hsa_ext_image_geometry_t', 'c__EA_hsa_ext_program_info_t', - 'c__EA_hsa_ext_sampler_addressing_mode_t', - 'c__EA_hsa_ext_sampler_coordinate_mode_t', - 'c__EA_hsa_ext_sampler_filter_mode_t', 'c__EA_hsa_extension_t', - 'c__EA_hsa_fence_scope_t', 'c__EA_hsa_flush_mode_t', - 'c__EA_hsa_fp_type_t', 'c__EA_hsa_isa_info_t', - 'c__EA_hsa_kernel_dispatch_packet_setup_t', - 'c__EA_hsa_kernel_dispatch_packet_setup_width_t', - 'c__EA_hsa_machine_model_t', 'c__EA_hsa_packet_header_t', - 'c__EA_hsa_packet_header_width_t', 'c__EA_hsa_packet_type_t', - 'c__EA_hsa_profile_t', 'c__EA_hsa_queue_feature_t', - 'c__EA_hsa_queue_info_attribute_t', 'c__EA_hsa_queue_type_t', - 'c__EA_hsa_region_global_flag_t', 'c__EA_hsa_region_info_t', - 'c__EA_hsa_region_segment_t', 'c__EA_hsa_round_method_t', - 'c__EA_hsa_signal_condition_t', 'c__EA_hsa_status_t', - 'c__EA_hsa_symbol_kind_t', 'c__EA_hsa_symbol_linkage_t', - 'c__EA_hsa_system_info_t', 'c__EA_hsa_variable_allocation_t', - 'c__EA_hsa_variable_segment_t', - 'c__EA_hsa_ven_amd_aqlprofile_att_marker_channel_t', - 'c__EA_hsa_ven_amd_aqlprofile_block_name_t', - 'c__EA_hsa_ven_amd_aqlprofile_event_type_t', - 'c__EA_hsa_ven_amd_aqlprofile_info_type_t', - 'c__EA_hsa_ven_amd_aqlprofile_parameter_name_t', - 'c__EA_hsa_wait_state_t', 'c__EA_hsa_wavefront_info_t', - 'c__Ea_HSA_EXT_AGENT_INFO_IMAGE_1D_MAX_ELEMENTS', - 'c__Ea_HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED', - 'c__Ea_HSA_EXT_STATUS_ERROR_INVALID_PROGRAM', - 'c__Ea_HSA_STATUS_ERROR_INVALID_MEMORY_POOL', 'hsaDeviceToDevice', - 'hsaDeviceToHost', 'hsaHostToDevice', 'hsaHostToHost', - 'hsa_access_permission_t', 'hsa_access_permission_t__enumvalues', - 'hsa_agent_dispatch_packet_t', 'hsa_agent_extension_supported', - 'hsa_agent_feature_t', 'hsa_agent_feature_t__enumvalues', - 'hsa_agent_get_exception_policies', 'hsa_agent_get_info', - 'hsa_agent_info_t', 'hsa_agent_info_t__enumvalues', - 'hsa_agent_iterate_caches', 'hsa_agent_iterate_isas', - 'hsa_agent_iterate_regions', - 'hsa_agent_major_extension_supported', 'hsa_agent_t', - 'hsa_amd_agent_info_s', 'hsa_amd_agent_info_t', - 'hsa_amd_agent_info_t__enumvalues', - 'hsa_amd_agent_iterate_memory_pools', - 'hsa_amd_agent_memory_pool_get_info', - 'hsa_amd_agent_memory_pool_info_t', - 'hsa_amd_agent_memory_pool_info_t__enumvalues', - 'hsa_amd_agent_memory_properties_s', - 'hsa_amd_agent_memory_properties_t', - 'hsa_amd_agent_memory_properties_t__enumvalues', - 'hsa_amd_agent_set_async_scratch_limit', - 'hsa_amd_agents_allow_access', 'hsa_amd_async_function', - 'hsa_amd_barrier_value_packet_t', 'hsa_amd_coherency_get_type', - 'hsa_amd_coherency_set_type', 'hsa_amd_coherency_type_s', - 'hsa_amd_coherency_type_t', - 'hsa_amd_coherency_type_t__enumvalues', - 'hsa_amd_copy_direction_t', - 'hsa_amd_copy_direction_t__enumvalues', - 'hsa_amd_deallocation_callback_t', - 'hsa_amd_deregister_deallocation_callback', 'hsa_amd_event_t', - 'hsa_amd_event_type_s', 'hsa_amd_event_type_t', - 'hsa_amd_event_type_t__enumvalues', - 'hsa_amd_gpu_hw_exception_info_t', - 'hsa_amd_gpu_memory_fault_info_t', 'hsa_amd_hdp_flush_t', - 'hsa_amd_hw_exception_reset_cause_t', - 'hsa_amd_hw_exception_reset_cause_t__enumvalues', - 'hsa_amd_hw_exception_reset_type_t', - 'hsa_amd_hw_exception_reset_type_t__enumvalues', - 'hsa_amd_image_create', 'hsa_amd_image_descriptor_t', - 'hsa_amd_image_get_info_max_dim', 'hsa_amd_interop_map_buffer', - 'hsa_amd_interop_unmap_buffer', 'hsa_amd_iommu_version_t', - 'hsa_amd_iommu_version_t__enumvalues', - 'hsa_amd_ipc_memory_attach', 'hsa_amd_ipc_memory_create', - 'hsa_amd_ipc_memory_detach', 'hsa_amd_ipc_memory_t', - 'hsa_amd_ipc_signal_attach', 'hsa_amd_ipc_signal_create', - 'hsa_amd_ipc_signal_t', 'hsa_amd_link_info_type_t', - 'hsa_amd_link_info_type_t__enumvalues', - 'hsa_amd_memory_access_desc_t', 'hsa_amd_memory_async_copy', - 'hsa_amd_memory_async_copy_on_engine', - 'hsa_amd_memory_async_copy_rect', - 'hsa_amd_memory_copy_engine_status', - 'hsa_amd_memory_fault_reason_t', - 'hsa_amd_memory_fault_reason_t__enumvalues', - 'hsa_amd_memory_fill', 'hsa_amd_memory_lock', - 'hsa_amd_memory_lock_to_pool', 'hsa_amd_memory_migrate', - 'hsa_amd_memory_pool_access_t', - 'hsa_amd_memory_pool_access_t__enumvalues', - 'hsa_amd_memory_pool_allocate', 'hsa_amd_memory_pool_can_migrate', - 'hsa_amd_memory_pool_flag_s', 'hsa_amd_memory_pool_flag_t', - 'hsa_amd_memory_pool_flag_t__enumvalues', - 'hsa_amd_memory_pool_free', 'hsa_amd_memory_pool_get_info', - 'hsa_amd_memory_pool_global_flag_s', - 'hsa_amd_memory_pool_global_flag_t', - 'hsa_amd_memory_pool_global_flag_t__enumvalues', - 'hsa_amd_memory_pool_info_t', - 'hsa_amd_memory_pool_info_t__enumvalues', - 'hsa_amd_memory_pool_link_info_t', - 'hsa_amd_memory_pool_location_s', - 'hsa_amd_memory_pool_location_t', - 'hsa_amd_memory_pool_location_t__enumvalues', - 'hsa_amd_memory_pool_t', 'hsa_amd_memory_type_t', - 'hsa_amd_memory_type_t__enumvalues', 'hsa_amd_memory_unlock', - 'hsa_amd_packet_type8_t', 'hsa_amd_packet_type_t', - 'hsa_amd_packet_type_t__enumvalues', 'hsa_amd_pointer_info', - 'hsa_amd_pointer_info_set_userdata', 'hsa_amd_pointer_info_t', - 'hsa_amd_pointer_type_t', 'hsa_amd_pointer_type_t__enumvalues', - 'hsa_amd_portable_close_dmabuf', 'hsa_amd_portable_export_dmabuf', - 'hsa_amd_profiling_async_copy_enable', - 'hsa_amd_profiling_async_copy_time_t', - 'hsa_amd_profiling_convert_tick_to_system_domain', - 'hsa_amd_profiling_dispatch_time_t', - 'hsa_amd_profiling_get_async_copy_time', - 'hsa_amd_profiling_get_dispatch_time', - 'hsa_amd_profiling_set_profiler_enabled', - 'hsa_amd_queue_cu_get_mask', 'hsa_amd_queue_cu_set_mask', - 'hsa_amd_queue_get_info', 'hsa_amd_queue_priority_s', - 'hsa_amd_queue_priority_t', - 'hsa_amd_queue_priority_t__enumvalues', - 'hsa_amd_queue_set_priority', 'hsa_amd_region_info_s', - 'hsa_amd_region_info_t', 'hsa_amd_region_info_t__enumvalues', - 'hsa_amd_register_deallocation_callback', - 'hsa_amd_register_system_event_handler', 'hsa_amd_sdma_engine_id', - 'hsa_amd_sdma_engine_id_t', - 'hsa_amd_sdma_engine_id_t__enumvalues', 'hsa_amd_segment_t', - 'hsa_amd_segment_t__enumvalues', 'hsa_amd_signal_async_handler', - 'hsa_amd_signal_attribute_t', - 'hsa_amd_signal_attribute_t__enumvalues', 'hsa_amd_signal_create', - 'hsa_amd_signal_handler', 'hsa_amd_signal_value_pointer', - 'hsa_amd_signal_wait_any', 'hsa_amd_spm_acquire', - 'hsa_amd_spm_release', 'hsa_amd_spm_set_dest_buffer', - 'hsa_amd_svm_attribute_pair_t', 'hsa_amd_svm_attribute_s', - 'hsa_amd_svm_attribute_t', 'hsa_amd_svm_attribute_t__enumvalues', - 'hsa_amd_svm_attributes_get', 'hsa_amd_svm_attributes_set', - 'hsa_amd_svm_model_s', 'hsa_amd_svm_model_t', - 'hsa_amd_svm_model_t__enumvalues', 'hsa_amd_svm_prefetch_async', - 'hsa_amd_system_event_callback_t', - 'hsa_amd_vendor_packet_header_t', 'hsa_amd_vmem_address_free', - 'hsa_amd_vmem_address_reserve', - 'hsa_amd_vmem_address_reserve_align', - 'hsa_amd_vmem_alloc_handle_t', - 'hsa_amd_vmem_export_shareable_handle', 'hsa_amd_vmem_get_access', - 'hsa_amd_vmem_get_alloc_properties_from_handle', - 'hsa_amd_vmem_handle_create', 'hsa_amd_vmem_handle_release', - 'hsa_amd_vmem_import_shareable_handle', 'hsa_amd_vmem_map', - 'hsa_amd_vmem_retain_alloc_handle', 'hsa_amd_vmem_set_access', - 'hsa_amd_vmem_unmap', 'hsa_barrier_and_packet_t', - 'hsa_barrier_or_packet_t', 'hsa_cache_get_info', - 'hsa_cache_info_t', 'hsa_cache_info_t__enumvalues', 'hsa_cache_t', - 'hsa_callback_data_t', 'hsa_code_object_deserialize', - 'hsa_code_object_destroy', 'hsa_code_object_get_info', - 'hsa_code_object_get_symbol', - 'hsa_code_object_get_symbol_from_name', 'hsa_code_object_info_t', - 'hsa_code_object_info_t__enumvalues', - 'hsa_code_object_iterate_symbols', - 'hsa_code_object_reader_create_from_file', - 'hsa_code_object_reader_create_from_memory', - 'hsa_code_object_reader_destroy', 'hsa_code_object_reader_t', - 'hsa_code_object_serialize', 'hsa_code_object_t', - 'hsa_code_object_type_t', 'hsa_code_object_type_t__enumvalues', - 'hsa_code_symbol_get_info', 'hsa_code_symbol_info_t', - 'hsa_code_symbol_info_t__enumvalues', 'hsa_code_symbol_t', - 'hsa_default_float_rounding_mode_t', - 'hsa_default_float_rounding_mode_t__enumvalues', - 'hsa_device_type_t', 'hsa_device_type_t__enumvalues', - 'hsa_dim3_t', 'hsa_endianness_t', 'hsa_endianness_t__enumvalues', - 'hsa_exception_policy_t', 'hsa_exception_policy_t__enumvalues', - 'hsa_executable_agent_global_variable_define', - 'hsa_executable_create', 'hsa_executable_create_alt', - 'hsa_executable_destroy', 'hsa_executable_freeze', - 'hsa_executable_get_info', 'hsa_executable_get_symbol', - 'hsa_executable_get_symbol_by_name', - 'hsa_executable_global_variable_define', 'hsa_executable_info_t', - 'hsa_executable_info_t__enumvalues', - 'hsa_executable_iterate_agent_symbols', - 'hsa_executable_iterate_program_symbols', - 'hsa_executable_iterate_symbols', - 'hsa_executable_load_agent_code_object', - 'hsa_executable_load_code_object', - 'hsa_executable_load_program_code_object', - 'hsa_executable_readonly_variable_define', - 'hsa_executable_state_t', 'hsa_executable_state_t__enumvalues', - 'hsa_executable_symbol_get_info', 'hsa_executable_symbol_info_t', - 'hsa_executable_symbol_info_t__enumvalues', - 'hsa_executable_symbol_t', 'hsa_executable_t', - 'hsa_executable_validate', 'hsa_executable_validate_alt', - 'hsa_ext_amd_aql_pm4_packet_t', 'hsa_ext_control_directives_t', - 'hsa_ext_finalizer_1_00_pfn_t', - 'hsa_ext_finalizer_call_convention_t', - 'hsa_ext_finalizer_call_convention_t__enumvalues', - 'hsa_ext_image_capability_t', - 'hsa_ext_image_capability_t__enumvalues', - 'hsa_ext_image_channel_order32_t', - 'hsa_ext_image_channel_order_t', - 'hsa_ext_image_channel_order_t__enumvalues', - 'hsa_ext_image_channel_type32_t', 'hsa_ext_image_channel_type_t', - 'hsa_ext_image_channel_type_t__enumvalues', 'hsa_ext_image_clear', - 'hsa_ext_image_copy', 'hsa_ext_image_create', - 'hsa_ext_image_create_with_layout', 'hsa_ext_image_data_get_info', - 'hsa_ext_image_data_get_info_with_layout', - 'hsa_ext_image_data_info_t', 'hsa_ext_image_data_layout_t', - 'hsa_ext_image_data_layout_t__enumvalues', - 'hsa_ext_image_descriptor_t', 'hsa_ext_image_destroy', - 'hsa_ext_image_export', 'hsa_ext_image_format_t', - 'hsa_ext_image_geometry_t', - 'hsa_ext_image_geometry_t__enumvalues', - 'hsa_ext_image_get_capability', - 'hsa_ext_image_get_capability_with_layout', - 'hsa_ext_image_import', 'hsa_ext_image_region_t', - 'hsa_ext_image_t', 'hsa_ext_images_1_00_pfn_t', - 'hsa_ext_images_1_pfn_t', 'hsa_ext_module_t', - 'hsa_ext_program_add_module', 'hsa_ext_program_create', - 'hsa_ext_program_destroy', 'hsa_ext_program_finalize', - 'hsa_ext_program_get_info', 'hsa_ext_program_info_t', - 'hsa_ext_program_info_t__enumvalues', - 'hsa_ext_program_iterate_modules', 'hsa_ext_program_t', - 'hsa_ext_sampler_addressing_mode32_t', - 'hsa_ext_sampler_addressing_mode_t', - 'hsa_ext_sampler_addressing_mode_t__enumvalues', - 'hsa_ext_sampler_coordinate_mode32_t', - 'hsa_ext_sampler_coordinate_mode_t', - 'hsa_ext_sampler_coordinate_mode_t__enumvalues', - 'hsa_ext_sampler_create', 'hsa_ext_sampler_descriptor_t', - 'hsa_ext_sampler_destroy', 'hsa_ext_sampler_filter_mode32_t', - 'hsa_ext_sampler_filter_mode_t', - 'hsa_ext_sampler_filter_mode_t__enumvalues', 'hsa_ext_sampler_t', - 'hsa_extension_get_name', 'hsa_extension_t', - 'hsa_extension_t__enumvalues', 'hsa_fence_scope_t', - 'hsa_fence_scope_t__enumvalues', 'hsa_file_t', 'hsa_flag_isset64', - 'hsa_flush_mode_t', 'hsa_flush_mode_t__enumvalues', - 'hsa_fp_type_t', 'hsa_fp_type_t__enumvalues', 'hsa_init', - 'hsa_isa_compatible', 'hsa_isa_from_name', - 'hsa_isa_get_exception_policies', 'hsa_isa_get_info', - 'hsa_isa_get_info_alt', 'hsa_isa_get_round_method', - 'hsa_isa_info_t', 'hsa_isa_info_t__enumvalues', - 'hsa_isa_iterate_wavefronts', 'hsa_isa_t', 'hsa_iterate_agents', - 'hsa_kernel_dispatch_packet_setup_t', - 'hsa_kernel_dispatch_packet_setup_t__enumvalues', - 'hsa_kernel_dispatch_packet_setup_width_t', - 'hsa_kernel_dispatch_packet_setup_width_t__enumvalues', - 'hsa_kernel_dispatch_packet_t', 'hsa_loaded_code_object_t', - 'hsa_machine_model_t', 'hsa_machine_model_t__enumvalues', - 'hsa_memory_allocate', 'hsa_memory_assign_agent', - 'hsa_memory_copy', 'hsa_memory_deregister', 'hsa_memory_free', - 'hsa_memory_register', 'hsa_packet_header_t', - 'hsa_packet_header_t__enumvalues', 'hsa_packet_header_width_t', - 'hsa_packet_header_width_t__enumvalues', 'hsa_packet_type_t', - 'hsa_packet_type_t__enumvalues', 'hsa_pitched_ptr_t', - 'hsa_profile_t', 'hsa_profile_t__enumvalues', - 'hsa_queue_add_write_index_acq_rel', - 'hsa_queue_add_write_index_acquire', - 'hsa_queue_add_write_index_relaxed', - 'hsa_queue_add_write_index_release', - 'hsa_queue_add_write_index_scacq_screl', - 'hsa_queue_add_write_index_scacquire', - 'hsa_queue_add_write_index_screlease', - 'hsa_queue_cas_write_index_acq_rel', - 'hsa_queue_cas_write_index_acquire', - 'hsa_queue_cas_write_index_relaxed', - 'hsa_queue_cas_write_index_release', - 'hsa_queue_cas_write_index_scacq_screl', - 'hsa_queue_cas_write_index_scacquire', - 'hsa_queue_cas_write_index_screlease', 'hsa_queue_create', - 'hsa_queue_destroy', 'hsa_queue_feature_t', - 'hsa_queue_feature_t__enumvalues', 'hsa_queue_inactivate', - 'hsa_queue_info_attribute_t', - 'hsa_queue_info_attribute_t__enumvalues', - 'hsa_queue_load_read_index_acquire', - 'hsa_queue_load_read_index_relaxed', - 'hsa_queue_load_read_index_scacquire', - 'hsa_queue_load_write_index_acquire', - 'hsa_queue_load_write_index_relaxed', - 'hsa_queue_load_write_index_scacquire', - 'hsa_queue_store_read_index_relaxed', - 'hsa_queue_store_read_index_release', - 'hsa_queue_store_read_index_screlease', - 'hsa_queue_store_write_index_relaxed', - 'hsa_queue_store_write_index_release', - 'hsa_queue_store_write_index_screlease', 'hsa_queue_t', - 'hsa_queue_type32_t', 'hsa_queue_type_t', - 'hsa_queue_type_t__enumvalues', 'hsa_region_get_info', - 'hsa_region_global_flag_t', - 'hsa_region_global_flag_t__enumvalues', 'hsa_region_info_t', - 'hsa_region_info_t__enumvalues', 'hsa_region_segment_t', - 'hsa_region_segment_t__enumvalues', 'hsa_region_t', - 'hsa_round_method_t', 'hsa_round_method_t__enumvalues', - 'hsa_shut_down', 'hsa_signal_add_acq_rel', - 'hsa_signal_add_acquire', 'hsa_signal_add_relaxed', - 'hsa_signal_add_release', 'hsa_signal_add_scacq_screl', - 'hsa_signal_add_scacquire', 'hsa_signal_add_screlease', - 'hsa_signal_and_acq_rel', 'hsa_signal_and_acquire', - 'hsa_signal_and_relaxed', 'hsa_signal_and_release', - 'hsa_signal_and_scacq_screl', 'hsa_signal_and_scacquire', - 'hsa_signal_and_screlease', 'hsa_signal_cas_acq_rel', - 'hsa_signal_cas_acquire', 'hsa_signal_cas_relaxed', - 'hsa_signal_cas_release', 'hsa_signal_cas_scacq_screl', - 'hsa_signal_cas_scacquire', 'hsa_signal_cas_screlease', - 'hsa_signal_condition32_t', 'hsa_signal_condition_t', - 'hsa_signal_condition_t__enumvalues', 'hsa_signal_create', - 'hsa_signal_destroy', 'hsa_signal_exchange_acq_rel', - 'hsa_signal_exchange_acquire', 'hsa_signal_exchange_relaxed', - 'hsa_signal_exchange_release', 'hsa_signal_exchange_scacq_screl', - 'hsa_signal_exchange_scacquire', 'hsa_signal_exchange_screlease', - 'hsa_signal_group_create', 'hsa_signal_group_destroy', - 'hsa_signal_group_t', 'hsa_signal_group_wait_any_relaxed', - 'hsa_signal_group_wait_any_scacquire', 'hsa_signal_load_acquire', - 'hsa_signal_load_relaxed', 'hsa_signal_load_scacquire', - 'hsa_signal_or_acq_rel', 'hsa_signal_or_acquire', - 'hsa_signal_or_relaxed', 'hsa_signal_or_release', - 'hsa_signal_or_scacq_screl', 'hsa_signal_or_scacquire', - 'hsa_signal_or_screlease', 'hsa_signal_silent_store_relaxed', - 'hsa_signal_silent_store_screlease', 'hsa_signal_store_relaxed', - 'hsa_signal_store_release', 'hsa_signal_store_screlease', - 'hsa_signal_subtract_acq_rel', 'hsa_signal_subtract_acquire', - 'hsa_signal_subtract_relaxed', 'hsa_signal_subtract_release', - 'hsa_signal_subtract_scacq_screl', - 'hsa_signal_subtract_scacquire', 'hsa_signal_subtract_screlease', - 'hsa_signal_t', 'hsa_signal_value_t', 'hsa_signal_wait_acquire', - 'hsa_signal_wait_relaxed', 'hsa_signal_wait_scacquire', - 'hsa_signal_xor_acq_rel', 'hsa_signal_xor_acquire', - 'hsa_signal_xor_relaxed', 'hsa_signal_xor_release', - 'hsa_signal_xor_scacq_screl', 'hsa_signal_xor_scacquire', - 'hsa_signal_xor_screlease', 'hsa_soft_queue_create', - 'hsa_status_string', 'hsa_status_t', 'hsa_status_t__enumvalues', - 'hsa_symbol_kind_t', 'hsa_symbol_kind_t__enumvalues', - 'hsa_symbol_linkage_t', 'hsa_symbol_linkage_t__enumvalues', - 'hsa_system_extension_supported', - 'hsa_system_get_extension_table', 'hsa_system_get_info', - 'hsa_system_get_major_extension_table', 'hsa_system_info_t', - 'hsa_system_info_t__enumvalues', - 'hsa_system_major_extension_supported', - 'hsa_variable_allocation_t', - 'hsa_variable_allocation_t__enumvalues', 'hsa_variable_segment_t', - 'hsa_variable_segment_t__enumvalues', - 'hsa_ven_amd_aqlprofile_1_00_pfn_t', - 'hsa_ven_amd_aqlprofile_att_marker', - 'hsa_ven_amd_aqlprofile_att_marker_channel_t', - 'hsa_ven_amd_aqlprofile_att_marker_channel_t__enumvalues', - 'hsa_ven_amd_aqlprofile_block_name_t', - 'hsa_ven_amd_aqlprofile_block_name_t__enumvalues', - 'hsa_ven_amd_aqlprofile_coordinate_callback_t', - 'hsa_ven_amd_aqlprofile_data_callback_t', - 'hsa_ven_amd_aqlprofile_descriptor_t', - 'hsa_ven_amd_aqlprofile_error_string', - 'hsa_ven_amd_aqlprofile_event_t', - 'hsa_ven_amd_aqlprofile_event_type_t', - 'hsa_ven_amd_aqlprofile_event_type_t__enumvalues', - 'hsa_ven_amd_aqlprofile_eventname_callback_t', - 'hsa_ven_amd_aqlprofile_get_info', - 'hsa_ven_amd_aqlprofile_id_query_t', - 'hsa_ven_amd_aqlprofile_info_data_t', - 'hsa_ven_amd_aqlprofile_info_type_t', - 'hsa_ven_amd_aqlprofile_info_type_t__enumvalues', - 'hsa_ven_amd_aqlprofile_iterate_data', - 'hsa_ven_amd_aqlprofile_iterate_event_coord', - 'hsa_ven_amd_aqlprofile_iterate_event_ids', - 'hsa_ven_amd_aqlprofile_legacy_get_pm4', - 'hsa_ven_amd_aqlprofile_parameter_name_t', - 'hsa_ven_amd_aqlprofile_parameter_name_t__enumvalues', - 'hsa_ven_amd_aqlprofile_parameter_t', - 'hsa_ven_amd_aqlprofile_pfn_t', - 'hsa_ven_amd_aqlprofile_profile_t', 'hsa_ven_amd_aqlprofile_read', - 'hsa_ven_amd_aqlprofile_start', 'hsa_ven_amd_aqlprofile_stop', - 'hsa_ven_amd_aqlprofile_validate_event', - 'hsa_ven_amd_aqlprofile_version_major', - 'hsa_ven_amd_aqlprofile_version_minor', 'hsa_wait_state_t', - 'hsa_wait_state_t__enumvalues', 'hsa_wavefront_get_info', - 'hsa_wavefront_info_t', 'hsa_wavefront_info_t__enumvalues', - 'hsa_wavefront_t', 'int32_t', 'kAqlProfileLib', 'size_t', - 'struct_BrigModuleHeader', 'struct_amd_control_directives_s', - 'struct_amd_kernel_code_s', 'struct_amd_queue_s', - 'struct_amd_runtime_loader_debug_info_s', 'struct_amd_signal_s', - 'struct_c__SA_hsa_ext_amd_aql_pm4_packet_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_descriptor_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_event_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_id_query_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0_pmc_data', - 'struct_c__SA_hsa_ven_amd_aqlprofile_parameter_t', - 'struct_c__SA_hsa_ven_amd_aqlprofile_profile_t', - 'struct_hsa_agent_dispatch_packet_s', 'struct_hsa_agent_s', - 'struct_hsa_amd_barrier_value_packet_s', 'struct_hsa_amd_event_s', - 'struct_hsa_amd_gpu_hw_exception_info_s', - 'struct_hsa_amd_gpu_memory_fault_info_s', - 'struct_hsa_amd_hdp_flush_s', 'struct_hsa_amd_image_descriptor_s', - 'struct_hsa_amd_ipc_memory_s', - 'struct_hsa_amd_memory_access_desc_s', - 'struct_hsa_amd_memory_pool_link_info_s', - 'struct_hsa_amd_memory_pool_s', 'struct_hsa_amd_packet_header_s', - 'struct_hsa_amd_pointer_info_s', - 'struct_hsa_amd_profiling_async_copy_time_s', - 'struct_hsa_amd_profiling_dispatch_time_s', - 'struct_hsa_amd_svm_attribute_pair_s', - 'struct_hsa_amd_vmem_alloc_handle_s', - 'struct_hsa_barrier_and_packet_s', - 'struct_hsa_barrier_or_packet_s', 'struct_hsa_cache_s', - 'struct_hsa_callback_data_s', 'struct_hsa_code_object_reader_s', - 'struct_hsa_code_object_s', 'struct_hsa_code_symbol_s', - 'struct_hsa_dim3_s', 'struct_hsa_executable_s', - 'struct_hsa_executable_symbol_s', - 'struct_hsa_ext_control_directives_s', - 'struct_hsa_ext_finalizer_1_00_pfn_s', - 'struct_hsa_ext_image_data_info_s', - 'struct_hsa_ext_image_descriptor_s', - 'struct_hsa_ext_image_format_s', 'struct_hsa_ext_image_region_s', - 'struct_hsa_ext_image_s', 'struct_hsa_ext_images_1_00_pfn_s', - 'struct_hsa_ext_images_1_pfn_s', 'struct_hsa_ext_program_s', - 'struct_hsa_ext_sampler_descriptor_s', 'struct_hsa_ext_sampler_s', - 'struct_hsa_isa_s', 'struct_hsa_kernel_dispatch_packet_s', - 'struct_hsa_loaded_code_object_s', 'struct_hsa_pitched_ptr_s', - 'struct_hsa_queue_s', 'struct_hsa_region_s', - 'struct_hsa_signal_group_s', 'struct_hsa_signal_s', - 'struct_hsa_ven_amd_aqlprofile_1_00_pfn_s', - 'struct_hsa_wavefront_s', 'uint16_t', 'uint32_t', 'uint64_t', - 'union_amd_signal_s_0', 'union_amd_signal_s_1', - 'union_c__SA_hsa_ven_amd_aqlprofile_info_data_t_0', - 'union_hsa_amd_event_s_0'] +HSA_VERSION_1_0 = 1 +HSA_AMD_INTERFACE_VERSION_MAJOR = 1 +HSA_AMD_INTERFACE_VERSION_MINOR = 6 +AMD_SIGNAL_ALIGN_BYTES = 64 +AMD_QUEUE_ALIGN_BYTES = 64 +AMD_CONTROL_DIRECTIVES_ALIGN_BYTES = 64 +AMD_ISA_ALIGN_BYTES = 256 +AMD_KERNEL_CODE_ALIGN_BYTES = 64 +HSA_AQLPROFILE_VERSION_MAJOR = 2 +HSA_AQLPROFILE_VERSION_MINOR = 0 +hsa_ven_amd_aqlprofile_VERSION_MAJOR = 1 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/ib.py b/tinygrad/runtime/autogen/ib.py index d3c5266b16..0c0a8fa13b 100644 --- a/tinygrad/runtime/autogen/ib.py +++ b/tinygrad/runtime/autogen/ib.py @@ -1,7173 +1,3499 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['libibverbs'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['libibverbs'] = ctypes.CDLL(ctypes.util.find_library('ibverbs'), use_errno=True) # ctypes.CDLL('libibverbs') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -INFINIBAND_VERBS_H = True # macro -VERBS_API_H = True # macro -# def RDMA_UAPI_PTR(_type, _name): # macro -# return {_type_name;__aligned_u64_name##_data_u64;} -IB_USER_IOCTL_VERBS_H = True # macro -IB_USER_VERBS_H = True # macro -IB_USER_VERBS_ABI_VERSION = 6 # macro -IB_USER_VERBS_CMD_THRESHOLD = 50 # macro -IB_USER_VERBS_CMD_COMMAND_MASK = 0xff # macro -IB_USER_VERBS_CMD_FLAG_EXTENDED = 0x80000000 # macro -IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE = 0x0d # macro -IB_DEVICE_NAME_MAX = 64 # macro -IB_UVERBS_ACCESS_OPTIONAL_FIRST = (1<<20) # macro -IB_UVERBS_ACCESS_OPTIONAL_LAST = (1<<29) # macro -# ibv_flow_action_esp_keymat_aes_gcm = ib_uverbs_flow_action_esp_keymat_aes_gcm # macro -# ibv_flow_action_esp_replay_bmp = ib_uverbs_flow_action_esp_replay_bmp # macro -# ibv_flow_action_esp_encap = ib_uverbs_flow_action_esp_encap # macro -# ibv_flow_action_esp = ib_uverbs_flow_action_esp # macro -IBV_ACCESS_OPTIONAL_FIRST = (1<<20) # macro -__attribute_const = True # macro -# def vext_field_avail(type, fld, sz): # macro -# return (offsetof(type,fld)<(sz)) -# __VERBS_ABI_IS_EXTENDED = ((void*)UINTPTR_MAX) # macro -IBV_DEVICE_RAW_SCATTER_FCS = (1<<34) # macro -IBV_DEVICE_PCI_WRITE_END_PADDING = (1<<36) # macro -# IBV_ALLOCATOR_USE_DEFAULT = ((void*)-1) # macro -ETHERNET_LL_SIZE = 6 # macro -IB_ROCE_UDP_ENCAP_VALID_PORT_MIN = (0xC000) # macro -IB_ROCE_UDP_ENCAP_VALID_PORT_MAX = (0xFFFF) # macro -IB_GRH_FLOWLABEL_MASK = (0x000FFFFF) # macro - -# values for enumeration 'ib_uverbs_write_cmds' -ib_uverbs_write_cmds__enumvalues = { - 0: 'IB_USER_VERBS_CMD_GET_CONTEXT', - 1: 'IB_USER_VERBS_CMD_QUERY_DEVICE', - 2: 'IB_USER_VERBS_CMD_QUERY_PORT', - 3: 'IB_USER_VERBS_CMD_ALLOC_PD', - 4: 'IB_USER_VERBS_CMD_DEALLOC_PD', - 5: 'IB_USER_VERBS_CMD_CREATE_AH', - 6: 'IB_USER_VERBS_CMD_MODIFY_AH', - 7: 'IB_USER_VERBS_CMD_QUERY_AH', - 8: 'IB_USER_VERBS_CMD_DESTROY_AH', - 9: 'IB_USER_VERBS_CMD_REG_MR', - 10: 'IB_USER_VERBS_CMD_REG_SMR', - 11: 'IB_USER_VERBS_CMD_REREG_MR', - 12: 'IB_USER_VERBS_CMD_QUERY_MR', - 13: 'IB_USER_VERBS_CMD_DEREG_MR', - 14: 'IB_USER_VERBS_CMD_ALLOC_MW', - 15: 'IB_USER_VERBS_CMD_BIND_MW', - 16: 'IB_USER_VERBS_CMD_DEALLOC_MW', - 17: 'IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL', - 18: 'IB_USER_VERBS_CMD_CREATE_CQ', - 19: 'IB_USER_VERBS_CMD_RESIZE_CQ', - 20: 'IB_USER_VERBS_CMD_DESTROY_CQ', - 21: 'IB_USER_VERBS_CMD_POLL_CQ', - 22: 'IB_USER_VERBS_CMD_PEEK_CQ', - 23: 'IB_USER_VERBS_CMD_REQ_NOTIFY_CQ', - 24: 'IB_USER_VERBS_CMD_CREATE_QP', - 25: 'IB_USER_VERBS_CMD_QUERY_QP', - 26: 'IB_USER_VERBS_CMD_MODIFY_QP', - 27: 'IB_USER_VERBS_CMD_DESTROY_QP', - 28: 'IB_USER_VERBS_CMD_POST_SEND', - 29: 'IB_USER_VERBS_CMD_POST_RECV', - 30: 'IB_USER_VERBS_CMD_ATTACH_MCAST', - 31: 'IB_USER_VERBS_CMD_DETACH_MCAST', - 32: 'IB_USER_VERBS_CMD_CREATE_SRQ', - 33: 'IB_USER_VERBS_CMD_MODIFY_SRQ', - 34: 'IB_USER_VERBS_CMD_QUERY_SRQ', - 35: 'IB_USER_VERBS_CMD_DESTROY_SRQ', - 36: 'IB_USER_VERBS_CMD_POST_SRQ_RECV', - 37: 'IB_USER_VERBS_CMD_OPEN_XRCD', - 38: 'IB_USER_VERBS_CMD_CLOSE_XRCD', - 39: 'IB_USER_VERBS_CMD_CREATE_XSRQ', - 40: 'IB_USER_VERBS_CMD_OPEN_QP', -} -IB_USER_VERBS_CMD_GET_CONTEXT = 0 -IB_USER_VERBS_CMD_QUERY_DEVICE = 1 -IB_USER_VERBS_CMD_QUERY_PORT = 2 -IB_USER_VERBS_CMD_ALLOC_PD = 3 -IB_USER_VERBS_CMD_DEALLOC_PD = 4 -IB_USER_VERBS_CMD_CREATE_AH = 5 -IB_USER_VERBS_CMD_MODIFY_AH = 6 -IB_USER_VERBS_CMD_QUERY_AH = 7 -IB_USER_VERBS_CMD_DESTROY_AH = 8 -IB_USER_VERBS_CMD_REG_MR = 9 -IB_USER_VERBS_CMD_REG_SMR = 10 -IB_USER_VERBS_CMD_REREG_MR = 11 -IB_USER_VERBS_CMD_QUERY_MR = 12 -IB_USER_VERBS_CMD_DEREG_MR = 13 -IB_USER_VERBS_CMD_ALLOC_MW = 14 -IB_USER_VERBS_CMD_BIND_MW = 15 -IB_USER_VERBS_CMD_DEALLOC_MW = 16 -IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL = 17 -IB_USER_VERBS_CMD_CREATE_CQ = 18 -IB_USER_VERBS_CMD_RESIZE_CQ = 19 -IB_USER_VERBS_CMD_DESTROY_CQ = 20 -IB_USER_VERBS_CMD_POLL_CQ = 21 -IB_USER_VERBS_CMD_PEEK_CQ = 22 -IB_USER_VERBS_CMD_REQ_NOTIFY_CQ = 23 -IB_USER_VERBS_CMD_CREATE_QP = 24 -IB_USER_VERBS_CMD_QUERY_QP = 25 -IB_USER_VERBS_CMD_MODIFY_QP = 26 -IB_USER_VERBS_CMD_DESTROY_QP = 27 -IB_USER_VERBS_CMD_POST_SEND = 28 -IB_USER_VERBS_CMD_POST_RECV = 29 -IB_USER_VERBS_CMD_ATTACH_MCAST = 30 -IB_USER_VERBS_CMD_DETACH_MCAST = 31 -IB_USER_VERBS_CMD_CREATE_SRQ = 32 -IB_USER_VERBS_CMD_MODIFY_SRQ = 33 -IB_USER_VERBS_CMD_QUERY_SRQ = 34 -IB_USER_VERBS_CMD_DESTROY_SRQ = 35 -IB_USER_VERBS_CMD_POST_SRQ_RECV = 36 -IB_USER_VERBS_CMD_OPEN_XRCD = 37 -IB_USER_VERBS_CMD_CLOSE_XRCD = 38 -IB_USER_VERBS_CMD_CREATE_XSRQ = 39 -IB_USER_VERBS_CMD_OPEN_QP = 40 -ib_uverbs_write_cmds = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE' -c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE__enumvalues = { - 1: 'IB_USER_VERBS_EX_CMD_QUERY_DEVICE', - 18: 'IB_USER_VERBS_EX_CMD_CREATE_CQ', - 24: 'IB_USER_VERBS_EX_CMD_CREATE_QP', - 26: 'IB_USER_VERBS_EX_CMD_MODIFY_QP', - 50: 'IB_USER_VERBS_EX_CMD_CREATE_FLOW', - 51: 'IB_USER_VERBS_EX_CMD_DESTROY_FLOW', - 52: 'IB_USER_VERBS_EX_CMD_CREATE_WQ', - 53: 'IB_USER_VERBS_EX_CMD_MODIFY_WQ', - 54: 'IB_USER_VERBS_EX_CMD_DESTROY_WQ', - 55: 'IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL', - 56: 'IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL', - 57: 'IB_USER_VERBS_EX_CMD_MODIFY_CQ', -} -IB_USER_VERBS_EX_CMD_QUERY_DEVICE = 1 -IB_USER_VERBS_EX_CMD_CREATE_CQ = 18 -IB_USER_VERBS_EX_CMD_CREATE_QP = 24 -IB_USER_VERBS_EX_CMD_MODIFY_QP = 26 -IB_USER_VERBS_EX_CMD_CREATE_FLOW = 50 -IB_USER_VERBS_EX_CMD_DESTROY_FLOW = 51 -IB_USER_VERBS_EX_CMD_CREATE_WQ = 52 -IB_USER_VERBS_EX_CMD_MODIFY_WQ = 53 -IB_USER_VERBS_EX_CMD_DESTROY_WQ = 54 -IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL = 55 -IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL = 56 -IB_USER_VERBS_EX_CMD_MODIFY_CQ = 57 -c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE = ctypes.c_uint32 # enum - -# values for enumeration 'ib_placement_type' -ib_placement_type__enumvalues = { - 1: 'IB_FLUSH_GLOBAL', - 2: 'IB_FLUSH_PERSISTENT', -} -IB_FLUSH_GLOBAL = 1 -IB_FLUSH_PERSISTENT = 2 -ib_placement_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_selectivity_level' -ib_selectivity_level__enumvalues = { - 0: 'IB_FLUSH_RANGE', - 1: 'IB_FLUSH_MR', -} -IB_FLUSH_RANGE = 0 -IB_FLUSH_MR = 1 -ib_selectivity_level = ctypes.c_uint32 # enum -class struct_ib_uverbs_async_event_desc(Structure): - pass - -struct_ib_uverbs_async_event_desc._pack_ = 1 # source:False -struct_ib_uverbs_async_event_desc._fields_ = [ - ('element', ctypes.c_uint64), - ('event_type', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_comp_event_desc(Structure): - pass - -struct_ib_uverbs_comp_event_desc._pack_ = 1 # source:False -struct_ib_uverbs_comp_event_desc._fields_ = [ - ('cq_handle', ctypes.c_uint64), -] - -class struct_ib_uverbs_cq_moderation_caps(Structure): - pass - -struct_ib_uverbs_cq_moderation_caps._pack_ = 1 # source:False -struct_ib_uverbs_cq_moderation_caps._fields_ = [ - ('max_cq_moderation_count', ctypes.c_uint16), - ('max_cq_moderation_period', ctypes.c_uint16), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_cmd_hdr(Structure): - pass - -struct_ib_uverbs_cmd_hdr._pack_ = 1 # source:False -struct_ib_uverbs_cmd_hdr._fields_ = [ - ('command', ctypes.c_uint32), - ('in_words', ctypes.c_uint16), - ('out_words', ctypes.c_uint16), -] - -class struct_ib_uverbs_ex_cmd_hdr(Structure): - pass - -struct_ib_uverbs_ex_cmd_hdr._pack_ = 1 # source:False -struct_ib_uverbs_ex_cmd_hdr._fields_ = [ - ('response', ctypes.c_uint64), - ('provider_in_words', ctypes.c_uint16), - ('provider_out_words', ctypes.c_uint16), - ('cmd_hdr_reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_get_context(Structure): - pass - -struct_ib_uverbs_get_context._pack_ = 1 # source:False -struct_ib_uverbs_get_context._fields_ = [ - ('response', ctypes.c_uint64), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_get_context_resp(Structure): - pass - -struct_ib_uverbs_get_context_resp._pack_ = 1 # source:False -struct_ib_uverbs_get_context_resp._fields_ = [ - ('async_fd', ctypes.c_uint32), - ('num_comp_vectors', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_device(Structure): - pass - -struct_ib_uverbs_query_device._pack_ = 1 # source:False -struct_ib_uverbs_query_device._fields_ = [ - ('response', ctypes.c_uint64), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_device_resp(Structure): - pass - -struct_ib_uverbs_query_device_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_device_resp._fields_ = [ - ('fw_ver', ctypes.c_uint64), - ('node_guid', ctypes.c_uint64), - ('sys_image_guid', ctypes.c_uint64), - ('max_mr_size', ctypes.c_uint64), - ('page_size_cap', ctypes.c_uint64), - ('vendor_id', ctypes.c_uint32), - ('vendor_part_id', ctypes.c_uint32), - ('hw_ver', ctypes.c_uint32), - ('max_qp', ctypes.c_uint32), - ('max_qp_wr', ctypes.c_uint32), - ('device_cap_flags', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('max_sge_rd', ctypes.c_uint32), - ('max_cq', ctypes.c_uint32), - ('max_cqe', ctypes.c_uint32), - ('max_mr', ctypes.c_uint32), - ('max_pd', ctypes.c_uint32), - ('max_qp_rd_atom', ctypes.c_uint32), - ('max_ee_rd_atom', ctypes.c_uint32), - ('max_res_rd_atom', ctypes.c_uint32), - ('max_qp_init_rd_atom', ctypes.c_uint32), - ('max_ee_init_rd_atom', ctypes.c_uint32), - ('atomic_cap', ctypes.c_uint32), - ('max_ee', ctypes.c_uint32), - ('max_rdd', ctypes.c_uint32), - ('max_mw', ctypes.c_uint32), - ('max_raw_ipv6_qp', ctypes.c_uint32), - ('max_raw_ethy_qp', ctypes.c_uint32), - ('max_mcast_grp', ctypes.c_uint32), - ('max_mcast_qp_attach', ctypes.c_uint32), - ('max_total_mcast_qp_attach', ctypes.c_uint32), - ('max_ah', ctypes.c_uint32), - ('max_fmr', ctypes.c_uint32), - ('max_map_per_fmr', ctypes.c_uint32), - ('max_srq', ctypes.c_uint32), - ('max_srq_wr', ctypes.c_uint32), - ('max_srq_sge', ctypes.c_uint32), - ('max_pkeys', ctypes.c_uint16), - ('local_ca_ack_delay', ctypes.c_ubyte), - ('phys_port_cnt', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 4), -] - -class struct_ib_uverbs_ex_query_device(Structure): - pass - -struct_ib_uverbs_ex_query_device._pack_ = 1 # source:False -struct_ib_uverbs_ex_query_device._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_odp_caps(Structure): - pass - -class struct_ib_uverbs_odp_caps_per_transport_caps(Structure): - pass - -struct_ib_uverbs_odp_caps_per_transport_caps._pack_ = 1 # source:False -struct_ib_uverbs_odp_caps_per_transport_caps._fields_ = [ - ('rc_odp_caps', ctypes.c_uint32), - ('uc_odp_caps', ctypes.c_uint32), - ('ud_odp_caps', ctypes.c_uint32), -] - -struct_ib_uverbs_odp_caps._pack_ = 1 # source:False -struct_ib_uverbs_odp_caps._fields_ = [ - ('general_caps', ctypes.c_uint64), - ('per_transport_caps', struct_ib_uverbs_odp_caps_per_transport_caps), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_rss_caps(Structure): - pass - -struct_ib_uverbs_rss_caps._pack_ = 1 # source:False -struct_ib_uverbs_rss_caps._fields_ = [ - ('supported_qpts', ctypes.c_uint32), - ('max_rwq_indirection_tables', ctypes.c_uint32), - ('max_rwq_indirection_table_size', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_tm_caps(Structure): - pass - -struct_ib_uverbs_tm_caps._pack_ = 1 # source:False -struct_ib_uverbs_tm_caps._fields_ = [ - ('max_rndv_hdr_size', ctypes.c_uint32), - ('max_num_tags', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('max_ops', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_query_device_resp(Structure): - pass - -struct_ib_uverbs_ex_query_device_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_query_device_resp._fields_ = [ - ('base', struct_ib_uverbs_query_device_resp), - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('odp_caps', struct_ib_uverbs_odp_caps), - ('timestamp_mask', ctypes.c_uint64), - ('hca_core_clock', ctypes.c_uint64), - ('device_cap_flags_ex', ctypes.c_uint64), - ('rss_caps', struct_ib_uverbs_rss_caps), - ('max_wq_type_rq', ctypes.c_uint32), - ('raw_packet_caps', ctypes.c_uint32), - ('tm_caps', struct_ib_uverbs_tm_caps), - ('cq_moderation_caps', struct_ib_uverbs_cq_moderation_caps), - ('max_dm_size', ctypes.c_uint64), - ('xrc_odp_caps', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_query_port(Structure): - pass - -struct_ib_uverbs_query_port._pack_ = 1 # source:False -struct_ib_uverbs_query_port._fields_ = [ - ('response', ctypes.c_uint64), - ('port_num', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 7), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_port_resp(Structure): - pass - -struct_ib_uverbs_query_port_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_port_resp._fields_ = [ - ('port_cap_flags', ctypes.c_uint32), - ('max_msg_sz', ctypes.c_uint32), - ('bad_pkey_cntr', ctypes.c_uint32), - ('qkey_viol_cntr', ctypes.c_uint32), - ('gid_tbl_len', ctypes.c_uint32), - ('pkey_tbl_len', ctypes.c_uint16), - ('lid', ctypes.c_uint16), - ('sm_lid', ctypes.c_uint16), - ('state', ctypes.c_ubyte), - ('max_mtu', ctypes.c_ubyte), - ('active_mtu', ctypes.c_ubyte), - ('lmc', ctypes.c_ubyte), - ('max_vl_num', ctypes.c_ubyte), - ('sm_sl', ctypes.c_ubyte), - ('subnet_timeout', ctypes.c_ubyte), - ('init_type_reply', ctypes.c_ubyte), - ('active_width', ctypes.c_ubyte), - ('active_speed', ctypes.c_ubyte), - ('phys_state', ctypes.c_ubyte), - ('link_layer', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_alloc_pd(Structure): - pass - -struct_ib_uverbs_alloc_pd._pack_ = 1 # source:False -struct_ib_uverbs_alloc_pd._fields_ = [ - ('response', ctypes.c_uint64), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_alloc_pd_resp(Structure): - pass - -struct_ib_uverbs_alloc_pd_resp._pack_ = 1 # source:False -struct_ib_uverbs_alloc_pd_resp._fields_ = [ - ('pd_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_dealloc_pd(Structure): - pass - -struct_ib_uverbs_dealloc_pd._pack_ = 1 # source:False -struct_ib_uverbs_dealloc_pd._fields_ = [ - ('pd_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_open_xrcd(Structure): - pass - -struct_ib_uverbs_open_xrcd._pack_ = 1 # source:False -struct_ib_uverbs_open_xrcd._fields_ = [ - ('response', ctypes.c_uint64), - ('fd', ctypes.c_uint32), - ('oflags', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_open_xrcd_resp(Structure): - pass - -struct_ib_uverbs_open_xrcd_resp._pack_ = 1 # source:False -struct_ib_uverbs_open_xrcd_resp._fields_ = [ - ('xrcd_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_close_xrcd(Structure): - pass - -struct_ib_uverbs_close_xrcd._pack_ = 1 # source:False -struct_ib_uverbs_close_xrcd._fields_ = [ - ('xrcd_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_reg_mr(Structure): - pass - -struct_ib_uverbs_reg_mr._pack_ = 1 # source:False -struct_ib_uverbs_reg_mr._fields_ = [ - ('response', ctypes.c_uint64), - ('start', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('hca_va', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('access_flags', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_reg_mr_resp(Structure): - pass - -struct_ib_uverbs_reg_mr_resp._pack_ = 1 # source:False -struct_ib_uverbs_reg_mr_resp._fields_ = [ - ('mr_handle', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_rereg_mr(Structure): - pass - -struct_ib_uverbs_rereg_mr._pack_ = 1 # source:False -struct_ib_uverbs_rereg_mr._fields_ = [ - ('response', ctypes.c_uint64), - ('mr_handle', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('start', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('hca_va', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('access_flags', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_rereg_mr_resp(Structure): - pass - -struct_ib_uverbs_rereg_mr_resp._pack_ = 1 # source:False -struct_ib_uverbs_rereg_mr_resp._fields_ = [ - ('lkey', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_dereg_mr(Structure): - pass - -struct_ib_uverbs_dereg_mr._pack_ = 1 # source:False -struct_ib_uverbs_dereg_mr._fields_ = [ - ('mr_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_alloc_mw(Structure): - pass - -struct_ib_uverbs_alloc_mw._pack_ = 1 # source:False -struct_ib_uverbs_alloc_mw._fields_ = [ - ('response', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('mw_type', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 3), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_alloc_mw_resp(Structure): - pass - -struct_ib_uverbs_alloc_mw_resp._pack_ = 1 # source:False -struct_ib_uverbs_alloc_mw_resp._fields_ = [ - ('mw_handle', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_dealloc_mw(Structure): - pass - -struct_ib_uverbs_dealloc_mw._pack_ = 1 # source:False -struct_ib_uverbs_dealloc_mw._fields_ = [ - ('mw_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_comp_channel(Structure): - pass - -struct_ib_uverbs_create_comp_channel._pack_ = 1 # source:False -struct_ib_uverbs_create_comp_channel._fields_ = [ - ('response', ctypes.c_uint64), -] - -class struct_ib_uverbs_create_comp_channel_resp(Structure): - pass - -struct_ib_uverbs_create_comp_channel_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_comp_channel_resp._fields_ = [ - ('fd', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_cq(Structure): - pass - -struct_ib_uverbs_create_cq._pack_ = 1 # source:False -struct_ib_uverbs_create_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('cqe', ctypes.c_uint32), - ('comp_vector', ctypes.c_uint32), - ('comp_channel', ctypes.c_int32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - - -# values for enumeration 'ib_uverbs_ex_create_cq_flags' -ib_uverbs_ex_create_cq_flags__enumvalues = { - 1: 'IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION', - 2: 'IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN', -} -IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 -IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = 2 -ib_uverbs_ex_create_cq_flags = ctypes.c_uint32 # enum -class struct_ib_uverbs_ex_create_cq(Structure): - pass - -struct_ib_uverbs_ex_create_cq._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_cq._fields_ = [ - ('user_handle', ctypes.c_uint64), - ('cqe', ctypes.c_uint32), - ('comp_vector', ctypes.c_uint32), - ('comp_channel', ctypes.c_int32), - ('comp_mask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_cq_resp(Structure): - pass - -struct_ib_uverbs_create_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_cq_resp._fields_ = [ - ('cq_handle', ctypes.c_uint32), - ('cqe', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_ex_create_cq_resp(Structure): - pass - -struct_ib_uverbs_ex_create_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_cq_resp._fields_ = [ - ('base', struct_ib_uverbs_create_cq_resp), - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), -] - -class struct_ib_uverbs_resize_cq(Structure): - pass - -struct_ib_uverbs_resize_cq._pack_ = 1 # source:False -struct_ib_uverbs_resize_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('cq_handle', ctypes.c_uint32), - ('cqe', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_resize_cq_resp(Structure): - pass - -struct_ib_uverbs_resize_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_resize_cq_resp._fields_ = [ - ('cqe', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_poll_cq(Structure): - pass - -struct_ib_uverbs_poll_cq._pack_ = 1 # source:False -struct_ib_uverbs_poll_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('cq_handle', ctypes.c_uint32), - ('ne', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_wc_opcode' -ib_uverbs_wc_opcode__enumvalues = { - 0: 'IB_UVERBS_WC_SEND', - 1: 'IB_UVERBS_WC_RDMA_WRITE', - 2: 'IB_UVERBS_WC_RDMA_READ', - 3: 'IB_UVERBS_WC_COMP_SWAP', - 4: 'IB_UVERBS_WC_FETCH_ADD', - 5: 'IB_UVERBS_WC_BIND_MW', - 6: 'IB_UVERBS_WC_LOCAL_INV', - 7: 'IB_UVERBS_WC_TSO', - 8: 'IB_UVERBS_WC_FLUSH', - 9: 'IB_UVERBS_WC_ATOMIC_WRITE', -} -IB_UVERBS_WC_SEND = 0 -IB_UVERBS_WC_RDMA_WRITE = 1 -IB_UVERBS_WC_RDMA_READ = 2 -IB_UVERBS_WC_COMP_SWAP = 3 -IB_UVERBS_WC_FETCH_ADD = 4 -IB_UVERBS_WC_BIND_MW = 5 -IB_UVERBS_WC_LOCAL_INV = 6 -IB_UVERBS_WC_TSO = 7 -IB_UVERBS_WC_FLUSH = 8 -IB_UVERBS_WC_ATOMIC_WRITE = 9 -ib_uverbs_wc_opcode = ctypes.c_uint32 # enum -class struct_ib_uverbs_wc(Structure): - pass - -class union_ib_uverbs_wc_ex(Union): - pass - -union_ib_uverbs_wc_ex._pack_ = 1 # source:False -union_ib_uverbs_wc_ex._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidate_rkey', ctypes.c_uint32), -] - -struct_ib_uverbs_wc._pack_ = 1 # source:False -struct_ib_uverbs_wc._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('opcode', ctypes.c_uint32), - ('vendor_err', ctypes.c_uint32), - ('byte_len', ctypes.c_uint32), - ('ex', union_ib_uverbs_wc_ex), - ('qp_num', ctypes.c_uint32), - ('src_qp', ctypes.c_uint32), - ('wc_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('slid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('dlid_path_bits', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_poll_cq_resp(Structure): - pass - -struct_ib_uverbs_poll_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_poll_cq_resp._fields_ = [ - ('count', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('wc', struct_ib_uverbs_wc * 0), -] - -class struct_ib_uverbs_req_notify_cq(Structure): - pass - -struct_ib_uverbs_req_notify_cq._pack_ = 1 # source:False -struct_ib_uverbs_req_notify_cq._fields_ = [ - ('cq_handle', ctypes.c_uint32), - ('solicited_only', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_cq(Structure): - pass - -struct_ib_uverbs_destroy_cq._pack_ = 1 # source:False -struct_ib_uverbs_destroy_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('cq_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_cq_resp(Structure): - pass - -struct_ib_uverbs_destroy_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_cq_resp._fields_ = [ - ('comp_events_reported', ctypes.c_uint32), - ('async_events_reported', ctypes.c_uint32), -] - -class struct_ib_uverbs_global_route(Structure): - pass - -struct_ib_uverbs_global_route._pack_ = 1 # source:False -struct_ib_uverbs_global_route._fields_ = [ - ('dgid', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('sgid_index', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_ah_attr(Structure): - pass - -struct_ib_uverbs_ah_attr._pack_ = 1 # source:False -struct_ib_uverbs_ah_attr._fields_ = [ - ('grh', struct_ib_uverbs_global_route), - ('dlid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('src_path_bits', ctypes.c_ubyte), - ('static_rate', ctypes.c_ubyte), - ('is_global', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_qp_attr(Structure): - pass - -struct_ib_uverbs_qp_attr._pack_ = 1 # source:False -struct_ib_uverbs_qp_attr._fields_ = [ - ('qp_attr_mask', ctypes.c_uint32), - ('qp_state', ctypes.c_uint32), - ('cur_qp_state', ctypes.c_uint32), - ('path_mtu', ctypes.c_uint32), - ('path_mig_state', ctypes.c_uint32), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('ah_attr', struct_ib_uverbs_ah_attr), - ('alt_ah_attr', struct_ib_uverbs_ah_attr), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('en_sqd_async_notify', ctypes.c_ubyte), - ('sq_draining', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 5), -] - -class struct_ib_uverbs_create_qp(Structure): - pass - -struct_ib_uverbs_create_qp._pack_ = 1 # source:False -struct_ib_uverbs_create_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('send_cq_handle', ctypes.c_uint32), - ('recv_cq_handle', ctypes.c_uint32), - ('srq_handle', ctypes.c_uint32), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('sq_sig_all', ctypes.c_ubyte), - ('qp_type', ctypes.c_ubyte), - ('is_srq', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), - ('driver_data', ctypes.c_uint64 * 0), -] - - -# values for enumeration 'ib_uverbs_create_qp_mask' -ib_uverbs_create_qp_mask__enumvalues = { - 1: 'IB_UVERBS_CREATE_QP_MASK_IND_TABLE', -} -IB_UVERBS_CREATE_QP_MASK_IND_TABLE = 1 -ib_uverbs_create_qp_mask = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK' -c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK__enumvalues = { - 1: 'IB_UVERBS_CREATE_QP_SUP_COMP_MASK', -} -IB_UVERBS_CREATE_QP_SUP_COMP_MASK = 1 -c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK = ctypes.c_uint32 # enum -class struct_ib_uverbs_ex_create_qp(Structure): - pass - -struct_ib_uverbs_ex_create_qp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_qp._fields_ = [ - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('send_cq_handle', ctypes.c_uint32), - ('recv_cq_handle', ctypes.c_uint32), - ('srq_handle', ctypes.c_uint32), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('sq_sig_all', ctypes.c_ubyte), - ('qp_type', ctypes.c_ubyte), - ('is_srq', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), - ('comp_mask', ctypes.c_uint32), - ('create_flags', ctypes.c_uint32), - ('rwq_ind_tbl_handle', ctypes.c_uint32), - ('source_qpn', ctypes.c_uint32), -] - -class struct_ib_uverbs_open_qp(Structure): - pass - -struct_ib_uverbs_open_qp._pack_ = 1 # source:False -struct_ib_uverbs_open_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('qpn', ctypes.c_uint32), - ('qp_type', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 7), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_qp_resp(Structure): - pass - -struct_ib_uverbs_create_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_qp_resp._fields_ = [ - ('qp_handle', ctypes.c_uint32), - ('qpn', ctypes.c_uint32), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_ex_create_qp_resp(Structure): - pass - -struct_ib_uverbs_ex_create_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_qp_resp._fields_ = [ - ('base', struct_ib_uverbs_create_qp_resp), - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), -] - -class struct_ib_uverbs_qp_dest(Structure): - pass - -struct_ib_uverbs_qp_dest._pack_ = 1 # source:False -struct_ib_uverbs_qp_dest._fields_ = [ - ('dgid', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('dlid', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('sgid_index', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('sl', ctypes.c_ubyte), - ('src_path_bits', ctypes.c_ubyte), - ('static_rate', ctypes.c_ubyte), - ('is_global', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), -] - -class struct_ib_uverbs_query_qp(Structure): - pass - -struct_ib_uverbs_query_qp._pack_ = 1 # source:False -struct_ib_uverbs_query_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_qp_resp(Structure): - pass - -struct_ib_uverbs_query_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_qp_resp._fields_ = [ - ('dest', struct_ib_uverbs_qp_dest), - ('alt_dest', struct_ib_uverbs_qp_dest), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('qp_state', ctypes.c_ubyte), - ('cur_qp_state', ctypes.c_ubyte), - ('path_mtu', ctypes.c_ubyte), - ('path_mig_state', ctypes.c_ubyte), - ('sq_draining', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('sq_sig_all', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 5), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_modify_qp(Structure): - pass - -struct_ib_uverbs_modify_qp._pack_ = 1 # source:False -struct_ib_uverbs_modify_qp._fields_ = [ - ('dest', struct_ib_uverbs_qp_dest), - ('alt_dest', struct_ib_uverbs_qp_dest), - ('qp_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('qp_state', ctypes.c_ubyte), - ('cur_qp_state', ctypes.c_ubyte), - ('path_mtu', ctypes.c_ubyte), - ('path_mig_state', ctypes.c_ubyte), - ('en_sqd_async_notify', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 2), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_ex_modify_qp(Structure): - pass - -struct_ib_uverbs_ex_modify_qp._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_qp._fields_ = [ - ('base', struct_ib_uverbs_modify_qp), - ('rate_limit', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_modify_qp_resp(Structure): - pass - -struct_ib_uverbs_ex_modify_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_qp_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_qp(Structure): - pass - -struct_ib_uverbs_destroy_qp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_qp_resp(Structure): - pass - -struct_ib_uverbs_destroy_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_qp_resp._fields_ = [ - ('events_reported', ctypes.c_uint32), -] - -class struct_ib_uverbs_sge(Structure): - pass - -struct_ib_uverbs_sge._pack_ = 1 # source:False -struct_ib_uverbs_sge._fields_ = [ - ('addr', ctypes.c_uint64), - ('length', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_wr_opcode' -ib_uverbs_wr_opcode__enumvalues = { - 0: 'IB_UVERBS_WR_RDMA_WRITE', - 1: 'IB_UVERBS_WR_RDMA_WRITE_WITH_IMM', - 2: 'IB_UVERBS_WR_SEND', - 3: 'IB_UVERBS_WR_SEND_WITH_IMM', - 4: 'IB_UVERBS_WR_RDMA_READ', - 5: 'IB_UVERBS_WR_ATOMIC_CMP_AND_SWP', - 6: 'IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD', - 7: 'IB_UVERBS_WR_LOCAL_INV', - 8: 'IB_UVERBS_WR_BIND_MW', - 9: 'IB_UVERBS_WR_SEND_WITH_INV', - 10: 'IB_UVERBS_WR_TSO', - 11: 'IB_UVERBS_WR_RDMA_READ_WITH_INV', - 12: 'IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP', - 13: 'IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD', - 14: 'IB_UVERBS_WR_FLUSH', - 15: 'IB_UVERBS_WR_ATOMIC_WRITE', -} -IB_UVERBS_WR_RDMA_WRITE = 0 -IB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1 -IB_UVERBS_WR_SEND = 2 -IB_UVERBS_WR_SEND_WITH_IMM = 3 -IB_UVERBS_WR_RDMA_READ = 4 -IB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5 -IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6 -IB_UVERBS_WR_LOCAL_INV = 7 -IB_UVERBS_WR_BIND_MW = 8 -IB_UVERBS_WR_SEND_WITH_INV = 9 -IB_UVERBS_WR_TSO = 10 -IB_UVERBS_WR_RDMA_READ_WITH_INV = 11 -IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12 -IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13 -IB_UVERBS_WR_FLUSH = 14 -IB_UVERBS_WR_ATOMIC_WRITE = 15 -ib_uverbs_wr_opcode = ctypes.c_uint32 # enum -class struct_ib_uverbs_send_wr(Structure): - pass - -class union_ib_uverbs_send_wr_ex(Union): - pass - -union_ib_uverbs_send_wr_ex._pack_ = 1 # source:False -union_ib_uverbs_send_wr_ex._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidate_rkey', ctypes.c_uint32), -] - -class union_ib_uverbs_send_wr_wr(Union): - pass - -class struct_ib_uverbs_send_wr_1_rdma(Structure): - pass - -struct_ib_uverbs_send_wr_1_rdma._pack_ = 1 # source:False -struct_ib_uverbs_send_wr_1_rdma._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_send_wr_1_atomic(Structure): - pass - -struct_ib_uverbs_send_wr_1_atomic._pack_ = 1 # source:False -struct_ib_uverbs_send_wr_1_atomic._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('compare_add', ctypes.c_uint64), - ('swap', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_send_wr_1_ud(Structure): - pass - -struct_ib_uverbs_send_wr_1_ud._pack_ = 1 # source:False -struct_ib_uverbs_send_wr_1_ud._fields_ = [ - ('ah', ctypes.c_uint32), - ('remote_qpn', ctypes.c_uint32), - ('remote_qkey', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -union_ib_uverbs_send_wr_wr._pack_ = 1 # source:False -union_ib_uverbs_send_wr_wr._fields_ = [ - ('rdma', struct_ib_uverbs_send_wr_1_rdma), - ('atomic', struct_ib_uverbs_send_wr_1_atomic), - ('ud', struct_ib_uverbs_send_wr_1_ud), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_ib_uverbs_send_wr._pack_ = 1 # source:False -struct_ib_uverbs_send_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('num_sge', ctypes.c_uint32), - ('opcode', ctypes.c_uint32), - ('send_flags', ctypes.c_uint32), - ('ex', union_ib_uverbs_send_wr_ex), - ('wr', union_ib_uverbs_send_wr_wr), -] - -class struct_ib_uverbs_post_send(Structure): - pass - -struct_ib_uverbs_post_send._pack_ = 1 # source:False -struct_ib_uverbs_post_send._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('wr_count', ctypes.c_uint32), - ('sge_count', ctypes.c_uint32), - ('wqe_size', ctypes.c_uint32), - ('send_wr', struct_ib_uverbs_send_wr * 0), -] - -class struct_ib_uverbs_post_send_resp(Structure): - pass - -struct_ib_uverbs_post_send_resp._pack_ = 1 # source:False -struct_ib_uverbs_post_send_resp._fields_ = [ - ('bad_wr', ctypes.c_uint32), -] - -class struct_ib_uverbs_recv_wr(Structure): - pass - -struct_ib_uverbs_recv_wr._pack_ = 1 # source:False -struct_ib_uverbs_recv_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('num_sge', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_post_recv(Structure): - pass - -struct_ib_uverbs_post_recv._pack_ = 1 # source:False -struct_ib_uverbs_post_recv._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('wr_count', ctypes.c_uint32), - ('sge_count', ctypes.c_uint32), - ('wqe_size', ctypes.c_uint32), - ('recv_wr', struct_ib_uverbs_recv_wr * 0), -] - -class struct_ib_uverbs_post_recv_resp(Structure): - pass - -struct_ib_uverbs_post_recv_resp._pack_ = 1 # source:False -struct_ib_uverbs_post_recv_resp._fields_ = [ - ('bad_wr', ctypes.c_uint32), -] - -class struct_ib_uverbs_post_srq_recv(Structure): - pass - -struct_ib_uverbs_post_srq_recv._pack_ = 1 # source:False -struct_ib_uverbs_post_srq_recv._fields_ = [ - ('response', ctypes.c_uint64), - ('srq_handle', ctypes.c_uint32), - ('wr_count', ctypes.c_uint32), - ('sge_count', ctypes.c_uint32), - ('wqe_size', ctypes.c_uint32), - ('recv', struct_ib_uverbs_recv_wr * 0), -] - -class struct_ib_uverbs_post_srq_recv_resp(Structure): - pass - -struct_ib_uverbs_post_srq_recv_resp._pack_ = 1 # source:False -struct_ib_uverbs_post_srq_recv_resp._fields_ = [ - ('bad_wr', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_ah(Structure): - pass - -struct_ib_uverbs_create_ah._pack_ = 1 # source:False -struct_ib_uverbs_create_ah._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('attr', struct_ib_uverbs_ah_attr), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_ah_resp(Structure): - pass - -struct_ib_uverbs_create_ah_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_ah_resp._fields_ = [ - ('ah_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_destroy_ah(Structure): - pass - -struct_ib_uverbs_destroy_ah._pack_ = 1 # source:False -struct_ib_uverbs_destroy_ah._fields_ = [ - ('ah_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_attach_mcast(Structure): - pass - -struct_ib_uverbs_attach_mcast._pack_ = 1 # source:False -struct_ib_uverbs_attach_mcast._fields_ = [ - ('gid', ctypes.c_ubyte * 16), - ('qp_handle', ctypes.c_uint32), - ('mlid', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_detach_mcast(Structure): - pass - -struct_ib_uverbs_detach_mcast._pack_ = 1 # source:False -struct_ib_uverbs_detach_mcast._fields_ = [ - ('gid', ctypes.c_ubyte * 16), - ('qp_handle', ctypes.c_uint32), - ('mlid', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_flow_spec_hdr(Structure): - pass - -struct_ib_uverbs_flow_spec_hdr._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_hdr._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('flow_spec_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_flow_eth_filter(Structure): - pass - -struct_ib_uverbs_flow_eth_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_eth_filter._fields_ = [ - ('dst_mac', ctypes.c_ubyte * 6), - ('src_mac', ctypes.c_ubyte * 6), - ('ether_type', ctypes.c_uint16), - ('vlan_tag', ctypes.c_uint16), -] - -class struct_ib_uverbs_flow_spec_eth(Structure): - pass - -class union_ib_uverbs_flow_spec_eth_0(Union): - pass - -class struct_ib_uverbs_flow_spec_eth_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_eth_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_eth_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_eth_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_eth_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_eth_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_eth_0_0), -] - -struct_ib_uverbs_flow_spec_eth._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_eth._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_eth._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_eth_0), - ('val', struct_ib_uverbs_flow_eth_filter), - ('mask', struct_ib_uverbs_flow_eth_filter), -] - -class struct_ib_uverbs_flow_ipv4_filter(Structure): - pass - -struct_ib_uverbs_flow_ipv4_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_ipv4_filter._fields_ = [ - ('src_ip', ctypes.c_uint32), - ('dst_ip', ctypes.c_uint32), - ('proto', ctypes.c_ubyte), - ('tos', ctypes.c_ubyte), - ('ttl', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -class struct_ib_uverbs_flow_spec_ipv4(Structure): - pass - -class union_ib_uverbs_flow_spec_ipv4_0(Union): - pass - -class struct_ib_uverbs_flow_spec_ipv4_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_ipv4_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv4_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_ipv4_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_ipv4_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_ipv4_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_ipv4_0_0), -] - -struct_ib_uverbs_flow_spec_ipv4._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv4._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_ipv4._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_ipv4_0), - ('val', struct_ib_uverbs_flow_ipv4_filter), - ('mask', struct_ib_uverbs_flow_ipv4_filter), -] - -class struct_ib_uverbs_flow_tcp_udp_filter(Structure): - pass - -struct_ib_uverbs_flow_tcp_udp_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_tcp_udp_filter._fields_ = [ - ('dst_port', ctypes.c_uint16), - ('src_port', ctypes.c_uint16), -] - -class struct_ib_uverbs_flow_spec_tcp_udp(Structure): - pass - -class union_ib_uverbs_flow_spec_tcp_udp_0(Union): - pass - -class struct_ib_uverbs_flow_spec_tcp_udp_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_tcp_udp_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tcp_udp_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_tcp_udp_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_tcp_udp_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_tcp_udp_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_tcp_udp_0_0), -] - -struct_ib_uverbs_flow_spec_tcp_udp._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tcp_udp._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_tcp_udp._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_tcp_udp_0), - ('val', struct_ib_uverbs_flow_tcp_udp_filter), - ('mask', struct_ib_uverbs_flow_tcp_udp_filter), -] - -class struct_ib_uverbs_flow_ipv6_filter(Structure): - pass - -struct_ib_uverbs_flow_ipv6_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_ipv6_filter._fields_ = [ - ('src_ip', ctypes.c_ubyte * 16), - ('dst_ip', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('next_hdr', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_flow_spec_ipv6(Structure): - pass - -class union_ib_uverbs_flow_spec_ipv6_0(Union): - pass - -class struct_ib_uverbs_flow_spec_ipv6_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_ipv6_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv6_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_ipv6_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_ipv6_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_ipv6_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_ipv6_0_0), -] - -struct_ib_uverbs_flow_spec_ipv6._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv6._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_ipv6._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_ipv6_0), - ('val', struct_ib_uverbs_flow_ipv6_filter), - ('mask', struct_ib_uverbs_flow_ipv6_filter), -] - -class struct_ib_uverbs_flow_spec_action_tag(Structure): - pass - -class union_ib_uverbs_flow_spec_action_tag_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_tag_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_tag_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_tag_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_tag_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_tag_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_tag_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_tag_0_0), -] - -struct_ib_uverbs_flow_spec_action_tag._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_tag._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_tag._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_tag_0), - ('tag_id', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_action_drop(Structure): - pass - -class union_ib_uverbs_flow_spec_action_drop_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_drop_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_drop_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_drop_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_drop_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_drop_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_drop_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_drop_0_0), -] - -struct_ib_uverbs_flow_spec_action_drop._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_drop._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_drop._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_drop_0), -] - -class struct_ib_uverbs_flow_spec_action_handle(Structure): - pass - -class union_ib_uverbs_flow_spec_action_handle_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_handle_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_handle_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_handle_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_handle_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_handle_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_handle_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_handle_0_0), -] - -struct_ib_uverbs_flow_spec_action_handle._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_handle._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_handle._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_handle_0), - ('handle', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_action_count(Structure): - pass - -class union_ib_uverbs_flow_spec_action_count_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_count_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_count_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_count_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_count_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_count_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_count_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_count_0_0), -] - -struct_ib_uverbs_flow_spec_action_count._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_count._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_count._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_count_0), - ('handle', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_tunnel_filter(Structure): - pass - -struct_ib_uverbs_flow_tunnel_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_tunnel_filter._fields_ = [ - ('tunnel_id', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_tunnel(Structure): - pass - -class union_ib_uverbs_flow_spec_tunnel_0(Union): - pass - -class struct_ib_uverbs_flow_spec_tunnel_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_tunnel_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tunnel_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_tunnel_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_tunnel_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_tunnel_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_tunnel_0_0), -] - -struct_ib_uverbs_flow_spec_tunnel._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tunnel._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_tunnel._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_tunnel_0), - ('val', struct_ib_uverbs_flow_tunnel_filter), - ('mask', struct_ib_uverbs_flow_tunnel_filter), -] - -class struct_ib_uverbs_flow_spec_esp_filter(Structure): - pass - -struct_ib_uverbs_flow_spec_esp_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_esp_filter._fields_ = [ - ('spi', ctypes.c_uint32), - ('seq', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_esp(Structure): - pass - -class union_ib_uverbs_flow_spec_esp_0(Union): - pass - -class struct_ib_uverbs_flow_spec_esp_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_esp_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_esp_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_esp_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_esp_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_esp_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_esp_0_0), -] - -struct_ib_uverbs_flow_spec_esp._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_esp._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_esp._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_esp_0), - ('val', struct_ib_uverbs_flow_spec_esp_filter), - ('mask', struct_ib_uverbs_flow_spec_esp_filter), -] - -class struct_ib_uverbs_flow_gre_filter(Structure): - pass - -struct_ib_uverbs_flow_gre_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_gre_filter._fields_ = [ - ('c_ks_res0_ver', ctypes.c_uint16), - ('protocol', ctypes.c_uint16), - ('key', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_gre(Structure): - pass - -class union_ib_uverbs_flow_spec_gre_0(Union): - pass - -class struct_ib_uverbs_flow_spec_gre_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_gre_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_gre_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_gre_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_gre_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_gre_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_gre_0_0), -] - -struct_ib_uverbs_flow_spec_gre._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_gre._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_gre._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_gre_0), - ('val', struct_ib_uverbs_flow_gre_filter), - ('mask', struct_ib_uverbs_flow_gre_filter), -] - -class struct_ib_uverbs_flow_mpls_filter(Structure): - pass - -struct_ib_uverbs_flow_mpls_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_mpls_filter._fields_ = [ - ('label', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_mpls(Structure): - pass - -class union_ib_uverbs_flow_spec_mpls_0(Union): - pass - -class struct_ib_uverbs_flow_spec_mpls_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_mpls_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_mpls_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_mpls_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_mpls_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_mpls_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_mpls_0_0), -] - -struct_ib_uverbs_flow_spec_mpls._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_mpls._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_mpls._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_mpls_0), - ('val', struct_ib_uverbs_flow_mpls_filter), - ('mask', struct_ib_uverbs_flow_mpls_filter), -] - -class struct_ib_uverbs_flow_attr(Structure): - pass - -struct_ib_uverbs_flow_attr._pack_ = 1 # source:False -struct_ib_uverbs_flow_attr._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('priority', ctypes.c_uint16), - ('num_of_specs', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 2), - ('port', ctypes.c_ubyte), - ('flags', ctypes.c_uint32), - ('flow_specs', struct_ib_uverbs_flow_spec_hdr * 0), -] - -class struct_ib_uverbs_create_flow(Structure): - pass - -struct_ib_uverbs_create_flow._pack_ = 1 # source:False -struct_ib_uverbs_create_flow._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('qp_handle', ctypes.c_uint32), - ('flow_attr', struct_ib_uverbs_flow_attr), -] - -class struct_ib_uverbs_create_flow_resp(Structure): - pass - -struct_ib_uverbs_create_flow_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_flow_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('flow_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_flow(Structure): - pass - -struct_ib_uverbs_destroy_flow._pack_ = 1 # source:False -struct_ib_uverbs_destroy_flow._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('flow_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_srq(Structure): - pass - -struct_ib_uverbs_create_srq._pack_ = 1 # source:False -struct_ib_uverbs_create_srq._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_xsrq(Structure): - pass - -struct_ib_uverbs_create_xsrq._pack_ = 1 # source:False -struct_ib_uverbs_create_xsrq._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('srq_type', ctypes.c_uint32), - ('pd_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('max_num_tags', ctypes.c_uint32), - ('xrcd_handle', ctypes.c_uint32), - ('cq_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_srq_resp(Structure): - pass - -struct_ib_uverbs_create_srq_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_srq_resp._fields_ = [ - ('srq_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srqn', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_modify_srq(Structure): - pass - -struct_ib_uverbs_modify_srq._pack_ = 1 # source:False -struct_ib_uverbs_modify_srq._fields_ = [ - ('srq_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_srq(Structure): - pass - -struct_ib_uverbs_query_srq._pack_ = 1 # source:False -struct_ib_uverbs_query_srq._fields_ = [ - ('response', ctypes.c_uint64), - ('srq_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_srq_resp(Structure): - pass - -struct_ib_uverbs_query_srq_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_srq_resp._fields_ = [ - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_srq(Structure): - pass - -struct_ib_uverbs_destroy_srq._pack_ = 1 # source:False -struct_ib_uverbs_destroy_srq._fields_ = [ - ('response', ctypes.c_uint64), - ('srq_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_srq_resp(Structure): - pass - -struct_ib_uverbs_destroy_srq_resp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_srq_resp._fields_ = [ - ('events_reported', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_create_wq(Structure): - pass - -struct_ib_uverbs_ex_create_wq._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_wq._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('wq_type', ctypes.c_uint32), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('cq_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('create_flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_create_wq_resp(Structure): - pass - -struct_ib_uverbs_ex_create_wq_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_wq_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('wq_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('wqn', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_destroy_wq(Structure): - pass - -struct_ib_uverbs_ex_destroy_wq._pack_ = 1 # source:False -struct_ib_uverbs_ex_destroy_wq._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('wq_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_destroy_wq_resp(Structure): - pass - -struct_ib_uverbs_ex_destroy_wq_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_destroy_wq_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('events_reported', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_modify_wq(Structure): - pass - -struct_ib_uverbs_ex_modify_wq._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_wq._fields_ = [ - ('attr_mask', ctypes.c_uint32), - ('wq_handle', ctypes.c_uint32), - ('wq_state', ctypes.c_uint32), - ('curr_wq_state', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('flags_mask', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_create_rwq_ind_table(Structure): - pass - -struct_ib_uverbs_ex_create_rwq_ind_table._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_rwq_ind_table._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('log_ind_tbl_size', ctypes.c_uint32), - ('wq_handles', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_ex_create_rwq_ind_table_resp(Structure): - pass - -struct_ib_uverbs_ex_create_rwq_ind_table_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_rwq_ind_table_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('ind_tbl_handle', ctypes.c_uint32), - ('ind_tbl_num', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_destroy_rwq_ind_table(Structure): - pass - -struct_ib_uverbs_ex_destroy_rwq_ind_table._pack_ = 1 # source:False -struct_ib_uverbs_ex_destroy_rwq_ind_table._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('ind_tbl_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_cq_moderation(Structure): - pass - -struct_ib_uverbs_cq_moderation._pack_ = 1 # source:False -struct_ib_uverbs_cq_moderation._fields_ = [ - ('cq_count', ctypes.c_uint16), - ('cq_period', ctypes.c_uint16), -] - -class struct_ib_uverbs_ex_modify_cq(Structure): - pass - -struct_ib_uverbs_ex_modify_cq._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_cq._fields_ = [ - ('cq_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('attr', struct_ib_uverbs_cq_moderation), - ('reserved', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_device_cap_flags' -ib_uverbs_device_cap_flags__enumvalues = { - 1: 'IB_UVERBS_DEVICE_RESIZE_MAX_WR', - 2: 'IB_UVERBS_DEVICE_BAD_PKEY_CNTR', - 4: 'IB_UVERBS_DEVICE_BAD_QKEY_CNTR', - 8: 'IB_UVERBS_DEVICE_RAW_MULTI', - 16: 'IB_UVERBS_DEVICE_AUTO_PATH_MIG', - 32: 'IB_UVERBS_DEVICE_CHANGE_PHY_PORT', - 64: 'IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE', - 128: 'IB_UVERBS_DEVICE_CURR_QP_STATE_MOD', - 256: 'IB_UVERBS_DEVICE_SHUTDOWN_PORT', - 1024: 'IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT', - 2048: 'IB_UVERBS_DEVICE_SYS_IMAGE_GUID', - 4096: 'IB_UVERBS_DEVICE_RC_RNR_NAK_GEN', - 8192: 'IB_UVERBS_DEVICE_SRQ_RESIZE', - 16384: 'IB_UVERBS_DEVICE_N_NOTIFY_CQ', - 131072: 'IB_UVERBS_DEVICE_MEM_WINDOW', - 262144: 'IB_UVERBS_DEVICE_UD_IP_CSUM', - 1048576: 'IB_UVERBS_DEVICE_XRC', - 2097152: 'IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS', - 8388608: 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A', - 16777216: 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B', - 33554432: 'IB_UVERBS_DEVICE_RC_IP_CSUM', - 67108864: 'IB_UVERBS_DEVICE_RAW_IP_CSUM', - 536870912: 'IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING', - 17179869184: 'IB_UVERBS_DEVICE_RAW_SCATTER_FCS', - 68719476736: 'IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING', - 274877906944: 'IB_UVERBS_DEVICE_FLUSH_GLOBAL', - 549755813888: 'IB_UVERBS_DEVICE_FLUSH_PERSISTENT', - 1099511627776: 'IB_UVERBS_DEVICE_ATOMIC_WRITE', -} -IB_UVERBS_DEVICE_RESIZE_MAX_WR = 1 -IB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2 -IB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4 -IB_UVERBS_DEVICE_RAW_MULTI = 8 -IB_UVERBS_DEVICE_AUTO_PATH_MIG = 16 -IB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32 -IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64 -IB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128 -IB_UVERBS_DEVICE_SHUTDOWN_PORT = 256 -IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024 -IB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048 -IB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096 -IB_UVERBS_DEVICE_SRQ_RESIZE = 8192 -IB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384 -IB_UVERBS_DEVICE_MEM_WINDOW = 131072 -IB_UVERBS_DEVICE_UD_IP_CSUM = 262144 -IB_UVERBS_DEVICE_XRC = 1048576 -IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152 -IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608 -IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216 -IB_UVERBS_DEVICE_RC_IP_CSUM = 33554432 -IB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864 -IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912 -IB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184 -IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736 -IB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944 -IB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888 -IB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776 -ib_uverbs_device_cap_flags = ctypes.c_uint64 # enum - -# values for enumeration 'ib_uverbs_raw_packet_caps' -ib_uverbs_raw_packet_caps__enumvalues = { - 1: 'IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING', - 2: 'IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS', - 4: 'IB_UVERBS_RAW_PACKET_CAP_IP_CSUM', - 8: 'IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP', -} -IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1 -IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2 -IB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4 -IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8 -ib_uverbs_raw_packet_caps = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_core_support' -ib_uverbs_core_support__enumvalues = { - 1: 'IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS', -} -IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS = 1 -ib_uverbs_core_support = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_access_flags' -ib_uverbs_access_flags__enumvalues = { - 1: 'IB_UVERBS_ACCESS_LOCAL_WRITE', - 2: 'IB_UVERBS_ACCESS_REMOTE_WRITE', - 4: 'IB_UVERBS_ACCESS_REMOTE_READ', - 8: 'IB_UVERBS_ACCESS_REMOTE_ATOMIC', - 16: 'IB_UVERBS_ACCESS_MW_BIND', - 32: 'IB_UVERBS_ACCESS_ZERO_BASED', - 64: 'IB_UVERBS_ACCESS_ON_DEMAND', - 128: 'IB_UVERBS_ACCESS_HUGETLB', - 256: 'IB_UVERBS_ACCESS_FLUSH_GLOBAL', - 512: 'IB_UVERBS_ACCESS_FLUSH_PERSISTENT', - 1048576: 'IB_UVERBS_ACCESS_RELAXED_ORDERING', - 1072693248: 'IB_UVERBS_ACCESS_OPTIONAL_RANGE', -} -IB_UVERBS_ACCESS_LOCAL_WRITE = 1 -IB_UVERBS_ACCESS_REMOTE_WRITE = 2 -IB_UVERBS_ACCESS_REMOTE_READ = 4 -IB_UVERBS_ACCESS_REMOTE_ATOMIC = 8 -IB_UVERBS_ACCESS_MW_BIND = 16 -IB_UVERBS_ACCESS_ZERO_BASED = 32 -IB_UVERBS_ACCESS_ON_DEMAND = 64 -IB_UVERBS_ACCESS_HUGETLB = 128 -IB_UVERBS_ACCESS_FLUSH_GLOBAL = 256 -IB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512 -IB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576 -IB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248 -ib_uverbs_access_flags = ctypes.c_uint32 # enum -IBV_ACCESS_OPTIONAL_RANGE = IB_UVERBS_ACCESS_OPTIONAL_RANGE # macro - -# values for enumeration 'ib_uverbs_srq_type' -ib_uverbs_srq_type__enumvalues = { - 0: 'IB_UVERBS_SRQT_BASIC', - 1: 'IB_UVERBS_SRQT_XRC', - 2: 'IB_UVERBS_SRQT_TM', -} -IB_UVERBS_SRQT_BASIC = 0 -IB_UVERBS_SRQT_XRC = 1 -IB_UVERBS_SRQT_TM = 2 -ib_uverbs_srq_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_wq_type' -ib_uverbs_wq_type__enumvalues = { - 0: 'IB_UVERBS_WQT_RQ', -} -IB_UVERBS_WQT_RQ = 0 -ib_uverbs_wq_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_wq_flags' -ib_uverbs_wq_flags__enumvalues = { - 1: 'IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING', - 2: 'IB_UVERBS_WQ_FLAGS_SCATTER_FCS', - 4: 'IB_UVERBS_WQ_FLAGS_DELAY_DROP', - 8: 'IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING', -} -IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1 -IB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2 -IB_UVERBS_WQ_FLAGS_DELAY_DROP = 4 -IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8 -ib_uverbs_wq_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_qp_type' -ib_uverbs_qp_type__enumvalues = { - 2: 'IB_UVERBS_QPT_RC', - 3: 'IB_UVERBS_QPT_UC', - 4: 'IB_UVERBS_QPT_UD', - 8: 'IB_UVERBS_QPT_RAW_PACKET', - 9: 'IB_UVERBS_QPT_XRC_INI', - 10: 'IB_UVERBS_QPT_XRC_TGT', - 255: 'IB_UVERBS_QPT_DRIVER', -} -IB_UVERBS_QPT_RC = 2 -IB_UVERBS_QPT_UC = 3 -IB_UVERBS_QPT_UD = 4 -IB_UVERBS_QPT_RAW_PACKET = 8 -IB_UVERBS_QPT_XRC_INI = 9 -IB_UVERBS_QPT_XRC_TGT = 10 -IB_UVERBS_QPT_DRIVER = 255 -ib_uverbs_qp_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_qp_create_flags' -ib_uverbs_qp_create_flags__enumvalues = { - 2: 'IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK', - 256: 'IB_UVERBS_QP_CREATE_SCATTER_FCS', - 512: 'IB_UVERBS_QP_CREATE_CVLAN_STRIPPING', - 2048: 'IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING', - 4096: 'IB_UVERBS_QP_CREATE_SQ_SIG_ALL', -} -IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2 -IB_UVERBS_QP_CREATE_SCATTER_FCS = 256 -IB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512 -IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048 -IB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096 -ib_uverbs_qp_create_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_query_port_cap_flags' -ib_uverbs_query_port_cap_flags__enumvalues = { - 2: 'IB_UVERBS_PCF_SM', - 4: 'IB_UVERBS_PCF_NOTICE_SUP', - 8: 'IB_UVERBS_PCF_TRAP_SUP', - 16: 'IB_UVERBS_PCF_OPT_IPD_SUP', - 32: 'IB_UVERBS_PCF_AUTO_MIGR_SUP', - 64: 'IB_UVERBS_PCF_SL_MAP_SUP', - 128: 'IB_UVERBS_PCF_MKEY_NVRAM', - 256: 'IB_UVERBS_PCF_PKEY_NVRAM', - 512: 'IB_UVERBS_PCF_LED_INFO_SUP', - 1024: 'IB_UVERBS_PCF_SM_DISABLED', - 2048: 'IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP', - 4096: 'IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP', - 16384: 'IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP', - 65536: 'IB_UVERBS_PCF_CM_SUP', - 131072: 'IB_UVERBS_PCF_SNMP_TUNNEL_SUP', - 262144: 'IB_UVERBS_PCF_REINIT_SUP', - 524288: 'IB_UVERBS_PCF_DEVICE_MGMT_SUP', - 1048576: 'IB_UVERBS_PCF_VENDOR_CLASS_SUP', - 2097152: 'IB_UVERBS_PCF_DR_NOTICE_SUP', - 4194304: 'IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP', - 8388608: 'IB_UVERBS_PCF_BOOT_MGMT_SUP', - 16777216: 'IB_UVERBS_PCF_LINK_LATENCY_SUP', - 33554432: 'IB_UVERBS_PCF_CLIENT_REG_SUP', - 134217728: 'IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP', - 268435456: 'IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP', - 536870912: 'IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP', - 1073741824: 'IB_UVERBS_PCF_MCAST_FDB_TOP_SUP', - 2147483648: 'IB_UVERBS_PCF_HIERARCHY_INFO_SUP', - 67108864: 'IB_UVERBS_PCF_IP_BASED_GIDS', -} -IB_UVERBS_PCF_SM = 2 -IB_UVERBS_PCF_NOTICE_SUP = 4 -IB_UVERBS_PCF_TRAP_SUP = 8 -IB_UVERBS_PCF_OPT_IPD_SUP = 16 -IB_UVERBS_PCF_AUTO_MIGR_SUP = 32 -IB_UVERBS_PCF_SL_MAP_SUP = 64 -IB_UVERBS_PCF_MKEY_NVRAM = 128 -IB_UVERBS_PCF_PKEY_NVRAM = 256 -IB_UVERBS_PCF_LED_INFO_SUP = 512 -IB_UVERBS_PCF_SM_DISABLED = 1024 -IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP = 2048 -IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP = 4096 -IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP = 16384 -IB_UVERBS_PCF_CM_SUP = 65536 -IB_UVERBS_PCF_SNMP_TUNNEL_SUP = 131072 -IB_UVERBS_PCF_REINIT_SUP = 262144 -IB_UVERBS_PCF_DEVICE_MGMT_SUP = 524288 -IB_UVERBS_PCF_VENDOR_CLASS_SUP = 1048576 -IB_UVERBS_PCF_DR_NOTICE_SUP = 2097152 -IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP = 4194304 -IB_UVERBS_PCF_BOOT_MGMT_SUP = 8388608 -IB_UVERBS_PCF_LINK_LATENCY_SUP = 16777216 -IB_UVERBS_PCF_CLIENT_REG_SUP = 33554432 -IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP = 134217728 -IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP = 268435456 -IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP = 536870912 -IB_UVERBS_PCF_MCAST_FDB_TOP_SUP = 1073741824 -IB_UVERBS_PCF_HIERARCHY_INFO_SUP = 2147483648 -IB_UVERBS_PCF_IP_BASED_GIDS = 67108864 -ib_uverbs_query_port_cap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_query_port_flags' -ib_uverbs_query_port_flags__enumvalues = { - 1: 'IB_UVERBS_QPF_GRH_REQUIRED', -} -IB_UVERBS_QPF_GRH_REQUIRED = 1 -ib_uverbs_query_port_flags = ctypes.c_uint32 # enum -IBV_QPF_GRH_REQUIRED = IB_UVERBS_QPF_GRH_REQUIRED # macro - -# values for enumeration 'ib_uverbs_flow_action_esp_keymat' -ib_uverbs_flow_action_esp_keymat__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM', -} -IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM = 0 -ib_uverbs_flow_action_esp_keymat = ctypes.c_uint32 # enum -ibv_flow_action_esp_keymat = ib_uverbs_flow_action_esp_keymat # macro -IBV_FLOW_ACTION_ESP_KEYMAT_AES_GCM = IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM # macro - -# values for enumeration 'ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo' -ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ', -} -IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ = 0 -ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo = ctypes.c_uint32 # enum -ibv_flow_action_esp_keymat_aes_gcm_iv_algo = ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo # macro -IBV_FLOW_ACTION_IV_ALGO_SEQ = IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ # macro -class struct_ib_uverbs_flow_action_esp_keymat_aes_gcm(Structure): - pass - -struct_ib_uverbs_flow_action_esp_keymat_aes_gcm._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp_keymat_aes_gcm._fields_ = [ - ('iv', ctypes.c_uint64), - ('iv_algo', ctypes.c_uint32), - ('salt', ctypes.c_uint32), - ('icv_len', ctypes.c_uint32), - ('key_len', ctypes.c_uint32), - ('aes_key', ctypes.c_uint32 * 8), -] - - -# values for enumeration 'ib_uverbs_flow_action_esp_replay' -ib_uverbs_flow_action_esp_replay__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE', - 1: 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP', -} -IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE = 0 -IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP = 1 -ib_uverbs_flow_action_esp_replay = ctypes.c_uint32 # enum -ibv_flow_action_esp_replay = ib_uverbs_flow_action_esp_replay # macro -IBV_FLOW_ACTION_ESP_REPLAY_NONE = IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE # macro -IBV_FLOW_ACTION_ESP_REPLAY_BMP = IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP # macro -class struct_ib_uverbs_flow_action_esp_replay_bmp(Structure): - pass - -struct_ib_uverbs_flow_action_esp_replay_bmp._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp_replay_bmp._fields_ = [ - ('size', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_flow_action_esp_flags' -ib_uverbs_flow_action_esp_flags__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', - 1: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', - 0: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL', - 2: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT', - 0: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT', - 4: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT', - 8: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', -} -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = 0 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = 1 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL = 0 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT = 2 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT = 0 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT = 4 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = 8 -ib_uverbs_flow_action_esp_flags = ctypes.c_uint32 # enum -ibv_flow_action_esp_flags = ib_uverbs_flow_action_esp_flags # macro -IBV_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO # macro -IBV_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD # macro -IBV_FLOW_ACTION_ESP_FLAGS_TUNNEL = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL # macro -IBV_FLOW_ACTION_ESP_FLAGS_TRANSPORT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT # macro -IBV_FLOW_ACTION_ESP_FLAGS_DECRYPT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT # macro -IBV_FLOW_ACTION_ESP_FLAGS_ENCRYPT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT # macro -IBV_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW # macro -class struct_ib_uverbs_flow_action_esp_encap(Structure): - pass - -class union_ib_uverbs_flow_action_esp_encap_0(Union): - pass - -union_ib_uverbs_flow_action_esp_encap_0._pack_ = 1 # source:False -union_ib_uverbs_flow_action_esp_encap_0._fields_ = [ - ('val_ptr', ctypes.POINTER(None)), - ('val_ptr_data_u64', ctypes.c_uint64), -] - -class union_ib_uverbs_flow_action_esp_encap_1(Union): - pass - -union_ib_uverbs_flow_action_esp_encap_1._pack_ = 1 # source:False -union_ib_uverbs_flow_action_esp_encap_1._fields_ = [ - ('next_ptr', ctypes.POINTER(struct_ib_uverbs_flow_action_esp_encap)), - ('next_ptr_data_u64', ctypes.c_uint64), -] - -struct_ib_uverbs_flow_action_esp_encap._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp_encap._anonymous_ = ('_0', '_1',) -struct_ib_uverbs_flow_action_esp_encap._fields_ = [ - ('_0', union_ib_uverbs_flow_action_esp_encap_0), - ('_1', union_ib_uverbs_flow_action_esp_encap_1), - ('len', ctypes.c_uint16), - ('type', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ib_uverbs_flow_action_esp(Structure): - pass - -struct_ib_uverbs_flow_action_esp._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp._fields_ = [ - ('spi', ctypes.c_uint32), - ('seq', ctypes.c_uint32), - ('tfc_pad', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hard_limit_pkts', ctypes.c_uint64), -] - - -# values for enumeration 'ib_uverbs_read_counters_flags' -ib_uverbs_read_counters_flags__enumvalues = { - 1: 'IB_UVERBS_READ_COUNTERS_PREFER_CACHED', -} -IB_UVERBS_READ_COUNTERS_PREFER_CACHED = 1 -ib_uverbs_read_counters_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_advise_mr_advice' -ib_uverbs_advise_mr_advice__enumvalues = { - 0: 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH', - 1: 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE', - 2: 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', -} -IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0 -IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1 -IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2 -ib_uverbs_advise_mr_advice = ctypes.c_uint32 # enum -ibv_advise_mr_advice = ib_uverbs_advise_mr_advice # macro -IBV_ADVISE_MR_ADVICE_PREFETCH = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH # macro -IBV_ADVISE_MR_ADVICE_PREFETCH_WRITE = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE # macro -IBV_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT # macro - -# values for enumeration 'ib_uverbs_advise_mr_flag' -ib_uverbs_advise_mr_flag__enumvalues = { - 1: 'IB_UVERBS_ADVISE_MR_FLAG_FLUSH', -} -IB_UVERBS_ADVISE_MR_FLAG_FLUSH = 1 -ib_uverbs_advise_mr_flag = ctypes.c_uint32 # enum -IBV_ADVISE_MR_FLAG_FLUSH = IB_UVERBS_ADVISE_MR_FLAG_FLUSH # macro -class struct_ib_uverbs_query_port_resp_ex(Structure): - pass - -struct_ib_uverbs_query_port_resp_ex._pack_ = 1 # source:False -struct_ib_uverbs_query_port_resp_ex._fields_ = [ - ('legacy_resp', struct_ib_uverbs_query_port_resp), - ('port_cap_flags2', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('active_speed_ex', ctypes.c_uint32), -] - -class struct_ib_uverbs_qp_cap(Structure): - pass - -struct_ib_uverbs_qp_cap._pack_ = 1 # source:False -struct_ib_uverbs_qp_cap._fields_ = [ - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), -] - - -# values for enumeration 'rdma_driver_id' -rdma_driver_id__enumvalues = { - 0: 'RDMA_DRIVER_UNKNOWN', - 1: 'RDMA_DRIVER_MLX5', - 2: 'RDMA_DRIVER_MLX4', - 3: 'RDMA_DRIVER_CXGB3', - 4: 'RDMA_DRIVER_CXGB4', - 5: 'RDMA_DRIVER_MTHCA', - 6: 'RDMA_DRIVER_BNXT_RE', - 7: 'RDMA_DRIVER_OCRDMA', - 8: 'RDMA_DRIVER_NES', - 9: 'RDMA_DRIVER_I40IW', - 9: 'RDMA_DRIVER_IRDMA', - 10: 'RDMA_DRIVER_VMW_PVRDMA', - 11: 'RDMA_DRIVER_QEDR', - 12: 'RDMA_DRIVER_HNS', - 13: 'RDMA_DRIVER_USNIC', - 14: 'RDMA_DRIVER_RXE', - 15: 'RDMA_DRIVER_HFI1', - 16: 'RDMA_DRIVER_QIB', - 17: 'RDMA_DRIVER_EFA', - 18: 'RDMA_DRIVER_SIW', - 19: 'RDMA_DRIVER_ERDMA', - 20: 'RDMA_DRIVER_MANA', -} -RDMA_DRIVER_UNKNOWN = 0 -RDMA_DRIVER_MLX5 = 1 -RDMA_DRIVER_MLX4 = 2 -RDMA_DRIVER_CXGB3 = 3 -RDMA_DRIVER_CXGB4 = 4 -RDMA_DRIVER_MTHCA = 5 -RDMA_DRIVER_BNXT_RE = 6 -RDMA_DRIVER_OCRDMA = 7 -RDMA_DRIVER_NES = 8 -RDMA_DRIVER_I40IW = 9 -RDMA_DRIVER_IRDMA = 9 -RDMA_DRIVER_VMW_PVRDMA = 10 -RDMA_DRIVER_QEDR = 11 -RDMA_DRIVER_HNS = 12 -RDMA_DRIVER_USNIC = 13 -RDMA_DRIVER_RXE = 14 -RDMA_DRIVER_HFI1 = 15 -RDMA_DRIVER_QIB = 16 -RDMA_DRIVER_EFA = 17 -RDMA_DRIVER_SIW = 18 -RDMA_DRIVER_ERDMA = 19 -RDMA_DRIVER_MANA = 20 -rdma_driver_id = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_gid_type' -ib_uverbs_gid_type__enumvalues = { - 0: 'IB_UVERBS_GID_TYPE_IB', - 1: 'IB_UVERBS_GID_TYPE_ROCE_V1', - 2: 'IB_UVERBS_GID_TYPE_ROCE_V2', -} -IB_UVERBS_GID_TYPE_IB = 0 -IB_UVERBS_GID_TYPE_ROCE_V1 = 1 -IB_UVERBS_GID_TYPE_ROCE_V2 = 2 -ib_uverbs_gid_type = ctypes.c_uint32 # enum -class struct_ib_uverbs_gid_entry(Structure): - pass - -struct_ib_uverbs_gid_entry._pack_ = 1 # source:False -struct_ib_uverbs_gid_entry._fields_ = [ - ('gid', ctypes.c_uint64 * 2), - ('gid_index', ctypes.c_uint32), - ('port_num', ctypes.c_uint32), - ('gid_type', ctypes.c_uint32), - ('netdev_ifindex', ctypes.c_uint32), -] - -class union_ibv_gid(Union): - pass - -class struct_ibv_gid_global(Structure): - pass - -struct_ibv_gid_global._pack_ = 1 # source:False -struct_ibv_gid_global._fields_ = [ - ('subnet_prefix', ctypes.c_uint64), - ('interface_id', ctypes.c_uint64), -] - -union_ibv_gid._pack_ = 1 # source:False -union_ibv_gid._fields_ = [ - ('raw', ctypes.c_ubyte * 16), - ('global', struct_ibv_gid_global), -] - - -# values for enumeration 'ibv_gid_type' -ibv_gid_type__enumvalues = { - 0: 'IBV_GID_TYPE_IB', - 1: 'IBV_GID_TYPE_ROCE_V1', - 2: 'IBV_GID_TYPE_ROCE_V2', -} -IBV_GID_TYPE_IB = 0 -IBV_GID_TYPE_ROCE_V1 = 1 -IBV_GID_TYPE_ROCE_V2 = 2 -ibv_gid_type = ctypes.c_uint32 # enum -class struct_ibv_gid_entry(Structure): - pass - -struct_ibv_gid_entry._pack_ = 1 # source:False -struct_ibv_gid_entry._fields_ = [ - ('gid', union_ibv_gid), - ('gid_index', ctypes.c_uint32), - ('port_num', ctypes.c_uint32), - ('gid_type', ctypes.c_uint32), - ('ndev_ifindex', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_node_type' -ibv_node_type__enumvalues = { - -1: 'IBV_NODE_UNKNOWN', - 1: 'IBV_NODE_CA', - 2: 'IBV_NODE_SWITCH', - 3: 'IBV_NODE_ROUTER', - 4: 'IBV_NODE_RNIC', - 5: 'IBV_NODE_USNIC', - 6: 'IBV_NODE_USNIC_UDP', - 7: 'IBV_NODE_UNSPECIFIED', -} -IBV_NODE_UNKNOWN = -1 -IBV_NODE_CA = 1 -IBV_NODE_SWITCH = 2 -IBV_NODE_ROUTER = 3 -IBV_NODE_RNIC = 4 -IBV_NODE_USNIC = 5 -IBV_NODE_USNIC_UDP = 6 -IBV_NODE_UNSPECIFIED = 7 -ibv_node_type = ctypes.c_int32 # enum - -# values for enumeration 'ibv_transport_type' -ibv_transport_type__enumvalues = { - -1: 'IBV_TRANSPORT_UNKNOWN', - 0: 'IBV_TRANSPORT_IB', - 1: 'IBV_TRANSPORT_IWARP', - 2: 'IBV_TRANSPORT_USNIC', - 3: 'IBV_TRANSPORT_USNIC_UDP', - 4: 'IBV_TRANSPORT_UNSPECIFIED', -} -IBV_TRANSPORT_UNKNOWN = -1 -IBV_TRANSPORT_IB = 0 -IBV_TRANSPORT_IWARP = 1 -IBV_TRANSPORT_USNIC = 2 -IBV_TRANSPORT_USNIC_UDP = 3 -IBV_TRANSPORT_UNSPECIFIED = 4 -ibv_transport_type = ctypes.c_int32 # enum - -# values for enumeration 'ibv_device_cap_flags' -ibv_device_cap_flags__enumvalues = { - 1: 'IBV_DEVICE_RESIZE_MAX_WR', - 2: 'IBV_DEVICE_BAD_PKEY_CNTR', - 4: 'IBV_DEVICE_BAD_QKEY_CNTR', - 8: 'IBV_DEVICE_RAW_MULTI', - 16: 'IBV_DEVICE_AUTO_PATH_MIG', - 32: 'IBV_DEVICE_CHANGE_PHY_PORT', - 64: 'IBV_DEVICE_UD_AV_PORT_ENFORCE', - 128: 'IBV_DEVICE_CURR_QP_STATE_MOD', - 256: 'IBV_DEVICE_SHUTDOWN_PORT', - 512: 'IBV_DEVICE_INIT_TYPE', - 1024: 'IBV_DEVICE_PORT_ACTIVE_EVENT', - 2048: 'IBV_DEVICE_SYS_IMAGE_GUID', - 4096: 'IBV_DEVICE_RC_RNR_NAK_GEN', - 8192: 'IBV_DEVICE_SRQ_RESIZE', - 16384: 'IBV_DEVICE_N_NOTIFY_CQ', - 131072: 'IBV_DEVICE_MEM_WINDOW', - 262144: 'IBV_DEVICE_UD_IP_CSUM', - 1048576: 'IBV_DEVICE_XRC', - 2097152: 'IBV_DEVICE_MEM_MGT_EXTENSIONS', - 8388608: 'IBV_DEVICE_MEM_WINDOW_TYPE_2A', - 16777216: 'IBV_DEVICE_MEM_WINDOW_TYPE_2B', - 33554432: 'IBV_DEVICE_RC_IP_CSUM', - 67108864: 'IBV_DEVICE_RAW_IP_CSUM', - 536870912: 'IBV_DEVICE_MANAGED_FLOW_STEERING', -} -IBV_DEVICE_RESIZE_MAX_WR = 1 -IBV_DEVICE_BAD_PKEY_CNTR = 2 -IBV_DEVICE_BAD_QKEY_CNTR = 4 -IBV_DEVICE_RAW_MULTI = 8 -IBV_DEVICE_AUTO_PATH_MIG = 16 -IBV_DEVICE_CHANGE_PHY_PORT = 32 -IBV_DEVICE_UD_AV_PORT_ENFORCE = 64 -IBV_DEVICE_CURR_QP_STATE_MOD = 128 -IBV_DEVICE_SHUTDOWN_PORT = 256 -IBV_DEVICE_INIT_TYPE = 512 -IBV_DEVICE_PORT_ACTIVE_EVENT = 1024 -IBV_DEVICE_SYS_IMAGE_GUID = 2048 -IBV_DEVICE_RC_RNR_NAK_GEN = 4096 -IBV_DEVICE_SRQ_RESIZE = 8192 -IBV_DEVICE_N_NOTIFY_CQ = 16384 -IBV_DEVICE_MEM_WINDOW = 131072 -IBV_DEVICE_UD_IP_CSUM = 262144 -IBV_DEVICE_XRC = 1048576 -IBV_DEVICE_MEM_MGT_EXTENSIONS = 2097152 -IBV_DEVICE_MEM_WINDOW_TYPE_2A = 8388608 -IBV_DEVICE_MEM_WINDOW_TYPE_2B = 16777216 -IBV_DEVICE_RC_IP_CSUM = 33554432 -IBV_DEVICE_RAW_IP_CSUM = 67108864 -IBV_DEVICE_MANAGED_FLOW_STEERING = 536870912 -ibv_device_cap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_fork_status' -ibv_fork_status__enumvalues = { - 0: 'IBV_FORK_DISABLED', - 1: 'IBV_FORK_ENABLED', - 2: 'IBV_FORK_UNNEEDED', -} -IBV_FORK_DISABLED = 0 -IBV_FORK_ENABLED = 1 -IBV_FORK_UNNEEDED = 2 -ibv_fork_status = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_atomic_cap' -ibv_atomic_cap__enumvalues = { - 0: 'IBV_ATOMIC_NONE', - 1: 'IBV_ATOMIC_HCA', - 2: 'IBV_ATOMIC_GLOB', -} -IBV_ATOMIC_NONE = 0 -IBV_ATOMIC_HCA = 1 -IBV_ATOMIC_GLOB = 2 -ibv_atomic_cap = ctypes.c_uint32 # enum -class struct_ibv_alloc_dm_attr(Structure): - pass - -struct_ibv_alloc_dm_attr._pack_ = 1 # source:False -struct_ibv_alloc_dm_attr._fields_ = [ - ('length', ctypes.c_uint64), - ('log_align_req', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_dm_mask' -ibv_dm_mask__enumvalues = { - 1: 'IBV_DM_MASK_HANDLE', -} -IBV_DM_MASK_HANDLE = 1 -ibv_dm_mask = ctypes.c_uint32 # enum -class struct_ibv_dm(Structure): - pass - -class struct_ibv_context(Structure): - pass - -struct_ibv_dm._pack_ = 1 # source:False -struct_ibv_dm._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('memcpy_to_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_dm), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64)), - ('memcpy_from_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(struct_ibv_dm), ctypes.c_uint64, ctypes.c_uint64)), - ('comp_mask', ctypes.c_uint32), - ('handle', ctypes.c_uint32), -] - -class struct_ibv_device(Structure): - pass - -class struct_ibv_context_ops(Structure): - pass - -class struct_ibv_device_attr(Structure): - pass - -class struct__compat_ibv_port_attr(Structure): - pass - -class struct_ibv_mw(Structure): - pass - -class struct_ibv_pd(Structure): - pass - - -# values for enumeration 'ibv_mw_type' -ibv_mw_type__enumvalues = { - 1: 'IBV_MW_TYPE_1', - 2: 'IBV_MW_TYPE_2', -} -IBV_MW_TYPE_1 = 1 -IBV_MW_TYPE_2 = 2 -ibv_mw_type = ctypes.c_uint32 # enum -class struct_ibv_qp(Structure): - pass - -class struct_ibv_mw_bind(Structure): - pass - -class struct_ibv_cq(Structure): - pass - -class struct_ibv_wc(Structure): - pass - -class struct_ibv_srq(Structure): - pass - -class struct_ibv_recv_wr(Structure): - pass - -class struct_ibv_send_wr(Structure): - pass - -struct_ibv_context_ops._pack_ = 1 # source:False -struct_ibv_context_ops._fields_ = [ - ('_compat_query_device', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device_attr))), - ('_compat_query_port', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.c_ubyte, ctypes.POINTER(struct__compat_ibv_port_attr))), - ('_compat_alloc_pd', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_dealloc_pd', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_reg_mr', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_rereg_mr', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_dereg_mr', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('alloc_mw', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_pd), ibv_mw_type)), - ('bind_mw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_mw_bind))), - ('dealloc_mw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_mw))), - ('_compat_create_cq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('poll_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.c_int32, ctypes.POINTER(struct_ibv_wc))), - ('req_notify_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.c_int32)), - ('_compat_cq_event', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_resize_cq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_cq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_create_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_modify_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_query_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('post_srq_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), - ('_compat_create_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_query_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_modify_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('post_send', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_send_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_send_wr)))), - ('post_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), - ('_compat_create_ah', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_ah', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_attach_mcast', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_detach_mcast', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_async_event', ctypes.CFUNCTYPE(ctypes.POINTER(None))), -] - -class union_c__UA_pthread_mutex_t(Union): - pass - -class struct___pthread_mutex_s(Structure): - pass - -class struct___pthread_internal_list(Structure): - pass - -struct___pthread_internal_list._pack_ = 1 # source:False -struct___pthread_internal_list._fields_ = [ - ('__prev', ctypes.POINTER(struct___pthread_internal_list)), - ('__next', ctypes.POINTER(struct___pthread_internal_list)), -] - -struct___pthread_mutex_s._pack_ = 1 # source:False -struct___pthread_mutex_s._fields_ = [ - ('__lock', ctypes.c_int32), - ('__count', ctypes.c_uint32), - ('__owner', ctypes.c_int32), - ('__nusers', ctypes.c_uint32), - ('__kind', ctypes.c_int32), - ('__spins', ctypes.c_int16), - ('__elision', ctypes.c_int16), - ('__list', struct___pthread_internal_list), -] - -union_c__UA_pthread_mutex_t._pack_ = 1 # source:False -union_c__UA_pthread_mutex_t._fields_ = [ - ('__data', struct___pthread_mutex_s), - ('__size', ctypes.c_char * 40), - ('__align', ctypes.c_int64), - ('PADDING_0', ctypes.c_ubyte * 32), -] - -struct_ibv_context._pack_ = 1 # source:False -struct_ibv_context._fields_ = [ - ('device', ctypes.POINTER(struct_ibv_device)), - ('ops', struct_ibv_context_ops), - ('cmd_fd', ctypes.c_int32), - ('async_fd', ctypes.c_int32), - ('num_comp_vectors', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('mutex', union_c__UA_pthread_mutex_t), - ('abi_compat', ctypes.POINTER(None)), -] - -class struct__ibv_device_ops(Structure): - pass - -struct__ibv_device_ops._pack_ = 1 # source:False -struct__ibv_device_ops._fields_ = [ - ('_dummy1', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device), ctypes.c_int32)), - ('_dummy2', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_context))), -] - -struct_ibv_device._pack_ = 1 # source:False -struct_ibv_device._fields_ = [ - ('_ops', struct__ibv_device_ops), - ('node_type', ibv_node_type), - ('transport_type', ibv_transport_type), - ('name', ctypes.c_char * 64), - ('dev_name', ctypes.c_char * 64), - ('dev_path', ctypes.c_char * 256), - ('ibdev_path', ctypes.c_char * 256), -] - -struct_ibv_device_attr._pack_ = 1 # source:False -struct_ibv_device_attr._fields_ = [ - ('fw_ver', ctypes.c_char * 64), - ('node_guid', ctypes.c_uint64), - ('sys_image_guid', ctypes.c_uint64), - ('max_mr_size', ctypes.c_uint64), - ('page_size_cap', ctypes.c_uint64), - ('vendor_id', ctypes.c_uint32), - ('vendor_part_id', ctypes.c_uint32), - ('hw_ver', ctypes.c_uint32), - ('max_qp', ctypes.c_int32), - ('max_qp_wr', ctypes.c_int32), - ('device_cap_flags', ctypes.c_uint32), - ('max_sge', ctypes.c_int32), - ('max_sge_rd', ctypes.c_int32), - ('max_cq', ctypes.c_int32), - ('max_cqe', ctypes.c_int32), - ('max_mr', ctypes.c_int32), - ('max_pd', ctypes.c_int32), - ('max_qp_rd_atom', ctypes.c_int32), - ('max_ee_rd_atom', ctypes.c_int32), - ('max_res_rd_atom', ctypes.c_int32), - ('max_qp_init_rd_atom', ctypes.c_int32), - ('max_ee_init_rd_atom', ctypes.c_int32), - ('atomic_cap', ibv_atomic_cap), - ('max_ee', ctypes.c_int32), - ('max_rdd', ctypes.c_int32), - ('max_mw', ctypes.c_int32), - ('max_raw_ipv6_qp', ctypes.c_int32), - ('max_raw_ethy_qp', ctypes.c_int32), - ('max_mcast_grp', ctypes.c_int32), - ('max_mcast_qp_attach', ctypes.c_int32), - ('max_total_mcast_qp_attach', ctypes.c_int32), - ('max_ah', ctypes.c_int32), - ('max_fmr', ctypes.c_int32), - ('max_map_per_fmr', ctypes.c_int32), - ('max_srq', ctypes.c_int32), - ('max_srq_wr', ctypes.c_int32), - ('max_srq_sge', ctypes.c_int32), - ('max_pkeys', ctypes.c_uint16), - ('local_ca_ack_delay', ctypes.c_ubyte), - ('phys_port_cnt', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_mw._pack_ = 1 # source:False -struct_ibv_mw._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('rkey', ctypes.c_uint32), - ('handle', ctypes.c_uint32), - ('type', ibv_mw_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_pd._pack_ = 1 # source:False -struct_ibv_pd._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_qp_state' -ibv_qp_state__enumvalues = { - 0: 'IBV_QPS_RESET', - 1: 'IBV_QPS_INIT', - 2: 'IBV_QPS_RTR', - 3: 'IBV_QPS_RTS', - 4: 'IBV_QPS_SQD', - 5: 'IBV_QPS_SQE', - 6: 'IBV_QPS_ERR', - 7: 'IBV_QPS_UNKNOWN', -} -IBV_QPS_RESET = 0 -IBV_QPS_INIT = 1 -IBV_QPS_RTR = 2 -IBV_QPS_RTS = 3 -IBV_QPS_SQD = 4 -IBV_QPS_SQE = 5 -IBV_QPS_ERR = 6 -IBV_QPS_UNKNOWN = 7 -ibv_qp_state = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_qp_type' -ibv_qp_type__enumvalues = { - 2: 'IBV_QPT_RC', - 3: 'IBV_QPT_UC', - 4: 'IBV_QPT_UD', - 8: 'IBV_QPT_RAW_PACKET', - 9: 'IBV_QPT_XRC_SEND', - 10: 'IBV_QPT_XRC_RECV', - 255: 'IBV_QPT_DRIVER', -} -IBV_QPT_RC = 2 -IBV_QPT_UC = 3 -IBV_QPT_UD = 4 -IBV_QPT_RAW_PACKET = 8 -IBV_QPT_XRC_SEND = 9 -IBV_QPT_XRC_RECV = 10 -IBV_QPT_DRIVER = 255 -ibv_qp_type = ctypes.c_uint32 # enum -class union_c__UA_pthread_cond_t(Union): - pass - -class struct___pthread_cond_s(Structure): - pass - -class union_c__UA___atomic_wide_counter(Union): - pass - -class struct_c__UA___atomic_wide_counter___value32(Structure): - pass - -struct_c__UA___atomic_wide_counter___value32._pack_ = 1 # source:False -struct_c__UA___atomic_wide_counter___value32._fields_ = [ - ('__low', ctypes.c_uint32), - ('__high', ctypes.c_uint32), -] - -union_c__UA___atomic_wide_counter._pack_ = 1 # source:False -union_c__UA___atomic_wide_counter._fields_ = [ - ('__value64', ctypes.c_uint64), - ('__value32', struct_c__UA___atomic_wide_counter___value32), -] - -struct___pthread_cond_s._pack_ = 1 # source:False -struct___pthread_cond_s._fields_ = [ - ('__wseq', union_c__UA___atomic_wide_counter), - ('__g1_start', union_c__UA___atomic_wide_counter), - ('__g_refs', ctypes.c_uint32 * 2), - ('__g_size', ctypes.c_uint32 * 2), - ('__g1_orig_size', ctypes.c_uint32), - ('__wrefs', ctypes.c_uint32), - ('__g_signals', ctypes.c_uint32 * 2), -] - -union_c__UA_pthread_cond_t._pack_ = 1 # source:False -union_c__UA_pthread_cond_t._fields_ = [ - ('__data', struct___pthread_cond_s), - ('__size', ctypes.c_char * 48), - ('__align', ctypes.c_int64), - ('PADDING_0', ctypes.c_ubyte * 40), -] - -struct_ibv_qp._pack_ = 1 # source:False -struct_ibv_qp._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('qp_context', ctypes.POINTER(None)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('send_cq', ctypes.POINTER(struct_ibv_cq)), - ('recv_cq', ctypes.POINTER(struct_ibv_cq)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('handle', ctypes.c_uint32), - ('qp_num', ctypes.c_uint32), - ('state', ibv_qp_state), - ('qp_type', ibv_qp_type), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('events_completed', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_comp_channel(Structure): - pass - -struct_ibv_cq._pack_ = 1 # source:False -struct_ibv_cq._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('channel', ctypes.POINTER(struct_ibv_comp_channel)), - ('cq_context', ctypes.POINTER(None)), - ('handle', ctypes.c_uint32), - ('cqe', ctypes.c_int32), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('comp_events_completed', ctypes.c_uint32), - ('async_events_completed', ctypes.c_uint32), -] - -struct_ibv_comp_channel._pack_ = 1 # source:False -struct_ibv_comp_channel._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('fd', ctypes.c_int32), - ('refcnt', ctypes.c_int32), -] - -struct_ibv_srq._pack_ = 1 # source:False -struct_ibv_srq._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('srq_context', ctypes.POINTER(None)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('events_completed', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_ibv_mw_bind_info(Structure): - pass - -class struct_ibv_mr(Structure): - pass - -struct_ibv_mw_bind_info._pack_ = 1 # source:False -struct_ibv_mw_bind_info._fields_ = [ - ('mr', ctypes.POINTER(struct_ibv_mr)), - ('addr', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('mw_access_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_mw_bind._pack_ = 1 # source:False -struct_ibv_mw_bind._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('send_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bind_info', struct_ibv_mw_bind_info), -] - -struct_ibv_mr._pack_ = 1 # source:False -struct_ibv_mr._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('addr', ctypes.POINTER(None)), - ('length', ctypes.c_uint64), - ('handle', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_wc_status' -ibv_wc_status__enumvalues = { - 0: 'IBV_WC_SUCCESS', - 1: 'IBV_WC_LOC_LEN_ERR', - 2: 'IBV_WC_LOC_QP_OP_ERR', - 3: 'IBV_WC_LOC_EEC_OP_ERR', - 4: 'IBV_WC_LOC_PROT_ERR', - 5: 'IBV_WC_WR_FLUSH_ERR', - 6: 'IBV_WC_MW_BIND_ERR', - 7: 'IBV_WC_BAD_RESP_ERR', - 8: 'IBV_WC_LOC_ACCESS_ERR', - 9: 'IBV_WC_REM_INV_REQ_ERR', - 10: 'IBV_WC_REM_ACCESS_ERR', - 11: 'IBV_WC_REM_OP_ERR', - 12: 'IBV_WC_RETRY_EXC_ERR', - 13: 'IBV_WC_RNR_RETRY_EXC_ERR', - 14: 'IBV_WC_LOC_RDD_VIOL_ERR', - 15: 'IBV_WC_REM_INV_RD_REQ_ERR', - 16: 'IBV_WC_REM_ABORT_ERR', - 17: 'IBV_WC_INV_EECN_ERR', - 18: 'IBV_WC_INV_EEC_STATE_ERR', - 19: 'IBV_WC_FATAL_ERR', - 20: 'IBV_WC_RESP_TIMEOUT_ERR', - 21: 'IBV_WC_GENERAL_ERR', - 22: 'IBV_WC_TM_ERR', - 23: 'IBV_WC_TM_RNDV_INCOMPLETE', -} -IBV_WC_SUCCESS = 0 -IBV_WC_LOC_LEN_ERR = 1 -IBV_WC_LOC_QP_OP_ERR = 2 -IBV_WC_LOC_EEC_OP_ERR = 3 -IBV_WC_LOC_PROT_ERR = 4 -IBV_WC_WR_FLUSH_ERR = 5 -IBV_WC_MW_BIND_ERR = 6 -IBV_WC_BAD_RESP_ERR = 7 -IBV_WC_LOC_ACCESS_ERR = 8 -IBV_WC_REM_INV_REQ_ERR = 9 -IBV_WC_REM_ACCESS_ERR = 10 -IBV_WC_REM_OP_ERR = 11 -IBV_WC_RETRY_EXC_ERR = 12 -IBV_WC_RNR_RETRY_EXC_ERR = 13 -IBV_WC_LOC_RDD_VIOL_ERR = 14 -IBV_WC_REM_INV_RD_REQ_ERR = 15 -IBV_WC_REM_ABORT_ERR = 16 -IBV_WC_INV_EECN_ERR = 17 -IBV_WC_INV_EEC_STATE_ERR = 18 -IBV_WC_FATAL_ERR = 19 -IBV_WC_RESP_TIMEOUT_ERR = 20 -IBV_WC_GENERAL_ERR = 21 -IBV_WC_TM_ERR = 22 -IBV_WC_TM_RNDV_INCOMPLETE = 23 -ibv_wc_status = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wc_opcode' -ibv_wc_opcode__enumvalues = { - 0: 'IBV_WC_SEND', - 1: 'IBV_WC_RDMA_WRITE', - 2: 'IBV_WC_RDMA_READ', - 3: 'IBV_WC_COMP_SWAP', - 4: 'IBV_WC_FETCH_ADD', - 5: 'IBV_WC_BIND_MW', - 6: 'IBV_WC_LOCAL_INV', - 7: 'IBV_WC_TSO', - 8: 'IBV_WC_FLUSH', - 9: 'IBV_WC_ATOMIC_WRITE', - 128: 'IBV_WC_RECV', - 129: 'IBV_WC_RECV_RDMA_WITH_IMM', - 130: 'IBV_WC_TM_ADD', - 131: 'IBV_WC_TM_DEL', - 132: 'IBV_WC_TM_SYNC', - 133: 'IBV_WC_TM_RECV', - 134: 'IBV_WC_TM_NO_TAG', - 135: 'IBV_WC_DRIVER1', - 136: 'IBV_WC_DRIVER2', - 137: 'IBV_WC_DRIVER3', -} -IBV_WC_SEND = 0 -IBV_WC_RDMA_WRITE = 1 -IBV_WC_RDMA_READ = 2 -IBV_WC_COMP_SWAP = 3 -IBV_WC_FETCH_ADD = 4 -IBV_WC_BIND_MW = 5 -IBV_WC_LOCAL_INV = 6 -IBV_WC_TSO = 7 -IBV_WC_FLUSH = 8 -IBV_WC_ATOMIC_WRITE = 9 -IBV_WC_RECV = 128 -IBV_WC_RECV_RDMA_WITH_IMM = 129 -IBV_WC_TM_ADD = 130 -IBV_WC_TM_DEL = 131 -IBV_WC_TM_SYNC = 132 -IBV_WC_TM_RECV = 133 -IBV_WC_TM_NO_TAG = 134 -IBV_WC_DRIVER1 = 135 -IBV_WC_DRIVER2 = 136 -IBV_WC_DRIVER3 = 137 -ibv_wc_opcode = ctypes.c_uint32 # enum -class union_ibv_wc_0(Union): - pass - -union_ibv_wc_0._pack_ = 1 # source:False -union_ibv_wc_0._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidated_rkey', ctypes.c_uint32), -] - -struct_ibv_wc._pack_ = 1 # source:False -struct_ibv_wc._anonymous_ = ('_0',) -struct_ibv_wc._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('status', ibv_wc_status), - ('opcode', ibv_wc_opcode), - ('vendor_err', ctypes.c_uint32), - ('byte_len', ctypes.c_uint32), - ('_0', union_ibv_wc_0), - ('qp_num', ctypes.c_uint32), - ('src_qp', ctypes.c_uint32), - ('wc_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('slid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('dlid_path_bits', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_sge(Structure): - pass - -struct_ibv_recv_wr._pack_ = 1 # source:False -struct_ibv_recv_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('next', ctypes.POINTER(struct_ibv_recv_wr)), - ('sg_list', ctypes.POINTER(struct_ibv_sge)), - ('num_sge', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_sge._pack_ = 1 # source:False -struct_ibv_sge._fields_ = [ - ('addr', ctypes.c_uint64), - ('length', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_wr_opcode' -ibv_wr_opcode__enumvalues = { - 0: 'IBV_WR_RDMA_WRITE', - 1: 'IBV_WR_RDMA_WRITE_WITH_IMM', - 2: 'IBV_WR_SEND', - 3: 'IBV_WR_SEND_WITH_IMM', - 4: 'IBV_WR_RDMA_READ', - 5: 'IBV_WR_ATOMIC_CMP_AND_SWP', - 6: 'IBV_WR_ATOMIC_FETCH_AND_ADD', - 7: 'IBV_WR_LOCAL_INV', - 8: 'IBV_WR_BIND_MW', - 9: 'IBV_WR_SEND_WITH_INV', - 10: 'IBV_WR_TSO', - 11: 'IBV_WR_DRIVER1', - 14: 'IBV_WR_FLUSH', - 15: 'IBV_WR_ATOMIC_WRITE', -} -IBV_WR_RDMA_WRITE = 0 -IBV_WR_RDMA_WRITE_WITH_IMM = 1 -IBV_WR_SEND = 2 -IBV_WR_SEND_WITH_IMM = 3 -IBV_WR_RDMA_READ = 4 -IBV_WR_ATOMIC_CMP_AND_SWP = 5 -IBV_WR_ATOMIC_FETCH_AND_ADD = 6 -IBV_WR_LOCAL_INV = 7 -IBV_WR_BIND_MW = 8 -IBV_WR_SEND_WITH_INV = 9 -IBV_WR_TSO = 10 -IBV_WR_DRIVER1 = 11 -IBV_WR_FLUSH = 14 -IBV_WR_ATOMIC_WRITE = 15 -ibv_wr_opcode = ctypes.c_uint32 # enum -class union_ibv_send_wr_0(Union): - pass - -union_ibv_send_wr_0._pack_ = 1 # source:False -union_ibv_send_wr_0._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidate_rkey', ctypes.c_uint32), -] - -class union_ibv_send_wr_wr(Union): - pass - -class struct_ibv_send_wr_1_rdma(Structure): - pass - -struct_ibv_send_wr_1_rdma._pack_ = 1 # source:False -struct_ibv_send_wr_1_rdma._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_send_wr_1_atomic(Structure): - pass - -struct_ibv_send_wr_1_atomic._pack_ = 1 # source:False -struct_ibv_send_wr_1_atomic._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('compare_add', ctypes.c_uint64), - ('swap', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_send_wr_1_ud(Structure): - pass - -class struct_ibv_ah(Structure): - pass - -struct_ibv_send_wr_1_ud._pack_ = 1 # source:False -struct_ibv_send_wr_1_ud._fields_ = [ - ('ah', ctypes.POINTER(struct_ibv_ah)), - ('remote_qpn', ctypes.c_uint32), - ('remote_qkey', ctypes.c_uint32), -] - -union_ibv_send_wr_wr._pack_ = 1 # source:False -union_ibv_send_wr_wr._fields_ = [ - ('rdma', struct_ibv_send_wr_1_rdma), - ('atomic', struct_ibv_send_wr_1_atomic), - ('ud', struct_ibv_send_wr_1_ud), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -class union_ibv_send_wr_qp_type(Union): - pass - -class struct_ibv_send_wr_2_xrc(Structure): - pass - -struct_ibv_send_wr_2_xrc._pack_ = 1 # source:False -struct_ibv_send_wr_2_xrc._fields_ = [ - ('remote_srqn', ctypes.c_uint32), -] - -union_ibv_send_wr_qp_type._pack_ = 1 # source:False -union_ibv_send_wr_qp_type._fields_ = [ - ('xrc', struct_ibv_send_wr_2_xrc), -] - -class union_ibv_send_wr_3(Union): - pass - -class struct_ibv_send_wr_3_bind_mw(Structure): - pass - -struct_ibv_send_wr_3_bind_mw._pack_ = 1 # source:False -struct_ibv_send_wr_3_bind_mw._fields_ = [ - ('mw', ctypes.POINTER(struct_ibv_mw)), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bind_info', struct_ibv_mw_bind_info), -] - -class struct_ibv_send_wr_3_tso(Structure): - pass - -struct_ibv_send_wr_3_tso._pack_ = 1 # source:False -struct_ibv_send_wr_3_tso._fields_ = [ - ('hdr', ctypes.POINTER(None)), - ('hdr_sz', ctypes.c_uint16), - ('mss', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -union_ibv_send_wr_3._pack_ = 1 # source:False -union_ibv_send_wr_3._fields_ = [ - ('bind_mw', struct_ibv_send_wr_3_bind_mw), - ('tso', struct_ibv_send_wr_3_tso), - ('PADDING_0', ctypes.c_ubyte * 32), -] - -struct_ibv_send_wr._pack_ = 1 # source:False -struct_ibv_send_wr._anonymous_ = ('_0', '_1',) -struct_ibv_send_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('next', ctypes.POINTER(struct_ibv_send_wr)), - ('sg_list', ctypes.POINTER(struct_ibv_sge)), - ('num_sge', ctypes.c_int32), - ('opcode', ibv_wr_opcode), - ('send_flags', ctypes.c_uint32), - ('_0', union_ibv_send_wr_0), - ('wr', union_ibv_send_wr_wr), - ('qp_type', union_ibv_send_wr_qp_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_1', union_ibv_send_wr_3), -] - -struct_ibv_ah._pack_ = 1 # source:False -struct_ibv_ah._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_query_device_ex_input(Structure): - pass - -struct_ibv_query_device_ex_input._pack_ = 1 # source:False -struct_ibv_query_device_ex_input._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_odp_transport_cap_bits' -ibv_odp_transport_cap_bits__enumvalues = { - 1: 'IBV_ODP_SUPPORT_SEND', - 2: 'IBV_ODP_SUPPORT_RECV', - 4: 'IBV_ODP_SUPPORT_WRITE', - 8: 'IBV_ODP_SUPPORT_READ', - 16: 'IBV_ODP_SUPPORT_ATOMIC', - 32: 'IBV_ODP_SUPPORT_SRQ_RECV', -} -IBV_ODP_SUPPORT_SEND = 1 -IBV_ODP_SUPPORT_RECV = 2 -IBV_ODP_SUPPORT_WRITE = 4 -IBV_ODP_SUPPORT_READ = 8 -IBV_ODP_SUPPORT_ATOMIC = 16 -IBV_ODP_SUPPORT_SRQ_RECV = 32 -ibv_odp_transport_cap_bits = ctypes.c_uint32 # enum -class struct_ibv_odp_caps(Structure): - pass - -class struct_ibv_odp_caps_per_transport_caps(Structure): - pass - -struct_ibv_odp_caps_per_transport_caps._pack_ = 1 # source:False -struct_ibv_odp_caps_per_transport_caps._fields_ = [ - ('rc_odp_caps', ctypes.c_uint32), - ('uc_odp_caps', ctypes.c_uint32), - ('ud_odp_caps', ctypes.c_uint32), -] - -struct_ibv_odp_caps._pack_ = 1 # source:False -struct_ibv_odp_caps._fields_ = [ - ('general_caps', ctypes.c_uint64), - ('per_transport_caps', struct_ibv_odp_caps_per_transport_caps), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_odp_general_caps' -ibv_odp_general_caps__enumvalues = { - 1: 'IBV_ODP_SUPPORT', - 2: 'IBV_ODP_SUPPORT_IMPLICIT', -} -IBV_ODP_SUPPORT = 1 -IBV_ODP_SUPPORT_IMPLICIT = 2 -ibv_odp_general_caps = ctypes.c_uint32 # enum -class struct_ibv_tso_caps(Structure): - pass - -struct_ibv_tso_caps._pack_ = 1 # source:False -struct_ibv_tso_caps._fields_ = [ - ('max_tso', ctypes.c_uint32), - ('supported_qpts', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_rx_hash_function_flags' -ibv_rx_hash_function_flags__enumvalues = { - 1: 'IBV_RX_HASH_FUNC_TOEPLITZ', -} -IBV_RX_HASH_FUNC_TOEPLITZ = 1 -ibv_rx_hash_function_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_rx_hash_fields' -ibv_rx_hash_fields__enumvalues = { - 1: 'IBV_RX_HASH_SRC_IPV4', - 2: 'IBV_RX_HASH_DST_IPV4', - 4: 'IBV_RX_HASH_SRC_IPV6', - 8: 'IBV_RX_HASH_DST_IPV6', - 16: 'IBV_RX_HASH_SRC_PORT_TCP', - 32: 'IBV_RX_HASH_DST_PORT_TCP', - 64: 'IBV_RX_HASH_SRC_PORT_UDP', - 128: 'IBV_RX_HASH_DST_PORT_UDP', - 256: 'IBV_RX_HASH_IPSEC_SPI', - 2147483648: 'IBV_RX_HASH_INNER', -} -IBV_RX_HASH_SRC_IPV4 = 1 -IBV_RX_HASH_DST_IPV4 = 2 -IBV_RX_HASH_SRC_IPV6 = 4 -IBV_RX_HASH_DST_IPV6 = 8 -IBV_RX_HASH_SRC_PORT_TCP = 16 -IBV_RX_HASH_DST_PORT_TCP = 32 -IBV_RX_HASH_SRC_PORT_UDP = 64 -IBV_RX_HASH_DST_PORT_UDP = 128 -IBV_RX_HASH_IPSEC_SPI = 256 -IBV_RX_HASH_INNER = 2147483648 -ibv_rx_hash_fields = ctypes.c_uint32 # enum -class struct_ibv_rss_caps(Structure): - pass - -struct_ibv_rss_caps._pack_ = 1 # source:False -struct_ibv_rss_caps._fields_ = [ - ('supported_qpts', ctypes.c_uint32), - ('max_rwq_indirection_tables', ctypes.c_uint32), - ('max_rwq_indirection_table_size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('rx_hash_fields_mask', ctypes.c_uint64), - ('rx_hash_function', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -class struct_ibv_packet_pacing_caps(Structure): - pass - -struct_ibv_packet_pacing_caps._pack_ = 1 # source:False -struct_ibv_packet_pacing_caps._fields_ = [ - ('qp_rate_limit_min', ctypes.c_uint32), - ('qp_rate_limit_max', ctypes.c_uint32), - ('supported_qpts', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_raw_packet_caps' -ibv_raw_packet_caps__enumvalues = { - 1: 'IBV_RAW_PACKET_CAP_CVLAN_STRIPPING', - 2: 'IBV_RAW_PACKET_CAP_SCATTER_FCS', - 4: 'IBV_RAW_PACKET_CAP_IP_CSUM', - 8: 'IBV_RAW_PACKET_CAP_DELAY_DROP', -} -IBV_RAW_PACKET_CAP_CVLAN_STRIPPING = 1 -IBV_RAW_PACKET_CAP_SCATTER_FCS = 2 -IBV_RAW_PACKET_CAP_IP_CSUM = 4 -IBV_RAW_PACKET_CAP_DELAY_DROP = 8 -ibv_raw_packet_caps = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_tm_cap_flags' -ibv_tm_cap_flags__enumvalues = { - 1: 'IBV_TM_CAP_RC', -} -IBV_TM_CAP_RC = 1 -ibv_tm_cap_flags = ctypes.c_uint32 # enum -class struct_ibv_tm_caps(Structure): - pass - -struct_ibv_tm_caps._pack_ = 1 # source:False -struct_ibv_tm_caps._fields_ = [ - ('max_rndv_hdr_size', ctypes.c_uint32), - ('max_num_tags', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('max_ops', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), -] - -class struct_ibv_cq_moderation_caps(Structure): - pass - -struct_ibv_cq_moderation_caps._pack_ = 1 # source:False -struct_ibv_cq_moderation_caps._fields_ = [ - ('max_cq_count', ctypes.c_uint16), - ('max_cq_period', ctypes.c_uint16), -] - - -# values for enumeration 'ibv_pci_atomic_op_size' -ibv_pci_atomic_op_size__enumvalues = { - 1: 'IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP', - 2: 'IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP', - 4: 'IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP', -} -IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP = 1 -IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP = 2 -IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP = 4 -ibv_pci_atomic_op_size = ctypes.c_uint32 # enum -class struct_ibv_pci_atomic_caps(Structure): - pass - -struct_ibv_pci_atomic_caps._pack_ = 1 # source:False -struct_ibv_pci_atomic_caps._fields_ = [ - ('fetch_add', ctypes.c_uint16), - ('swap', ctypes.c_uint16), - ('compare_swap', ctypes.c_uint16), -] - -class struct_ibv_device_attr_ex(Structure): - pass - -struct_ibv_device_attr_ex._pack_ = 1 # source:False -struct_ibv_device_attr_ex._fields_ = [ - ('orig_attr', struct_ibv_device_attr), - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('odp_caps', struct_ibv_odp_caps), - ('completion_timestamp_mask', ctypes.c_uint64), - ('hca_core_clock', ctypes.c_uint64), - ('device_cap_flags_ex', ctypes.c_uint64), - ('tso_caps', struct_ibv_tso_caps), - ('rss_caps', struct_ibv_rss_caps), - ('max_wq_type_rq', ctypes.c_uint32), - ('packet_pacing_caps', struct_ibv_packet_pacing_caps), - ('raw_packet_caps', ctypes.c_uint32), - ('tm_caps', struct_ibv_tm_caps), - ('cq_mod_caps', struct_ibv_cq_moderation_caps), - ('PADDING_1', ctypes.c_ubyte * 4), - ('max_dm_size', ctypes.c_uint64), - ('pci_atomic_caps', struct_ibv_pci_atomic_caps), - ('PADDING_2', ctypes.c_ubyte * 2), - ('xrc_odp_caps', ctypes.c_uint32), - ('phys_port_cnt_ex', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_mtu' -ibv_mtu__enumvalues = { - 1: 'IBV_MTU_256', - 2: 'IBV_MTU_512', - 3: 'IBV_MTU_1024', - 4: 'IBV_MTU_2048', - 5: 'IBV_MTU_4096', -} -IBV_MTU_256 = 1 -IBV_MTU_512 = 2 -IBV_MTU_1024 = 3 -IBV_MTU_2048 = 4 -IBV_MTU_4096 = 5 -ibv_mtu = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_port_state' -ibv_port_state__enumvalues = { - 0: 'IBV_PORT_NOP', - 1: 'IBV_PORT_DOWN', - 2: 'IBV_PORT_INIT', - 3: 'IBV_PORT_ARMED', - 4: 'IBV_PORT_ACTIVE', - 5: 'IBV_PORT_ACTIVE_DEFER', -} -IBV_PORT_NOP = 0 -IBV_PORT_DOWN = 1 -IBV_PORT_INIT = 2 -IBV_PORT_ARMED = 3 -IBV_PORT_ACTIVE = 4 -IBV_PORT_ACTIVE_DEFER = 5 -ibv_port_state = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IBV_LINK_LAYER_UNSPECIFIED' -c__Ea_IBV_LINK_LAYER_UNSPECIFIED__enumvalues = { - 0: 'IBV_LINK_LAYER_UNSPECIFIED', - 1: 'IBV_LINK_LAYER_INFINIBAND', - 2: 'IBV_LINK_LAYER_ETHERNET', -} -IBV_LINK_LAYER_UNSPECIFIED = 0 -IBV_LINK_LAYER_INFINIBAND = 1 -IBV_LINK_LAYER_ETHERNET = 2 -c__Ea_IBV_LINK_LAYER_UNSPECIFIED = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_port_cap_flags' -ibv_port_cap_flags__enumvalues = { - 2: 'IBV_PORT_SM', - 4: 'IBV_PORT_NOTICE_SUP', - 8: 'IBV_PORT_TRAP_SUP', - 16: 'IBV_PORT_OPT_IPD_SUP', - 32: 'IBV_PORT_AUTO_MIGR_SUP', - 64: 'IBV_PORT_SL_MAP_SUP', - 128: 'IBV_PORT_MKEY_NVRAM', - 256: 'IBV_PORT_PKEY_NVRAM', - 512: 'IBV_PORT_LED_INFO_SUP', - 2048: 'IBV_PORT_SYS_IMAGE_GUID_SUP', - 4096: 'IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP', - 16384: 'IBV_PORT_EXTENDED_SPEEDS_SUP', - 32768: 'IBV_PORT_CAP_MASK2_SUP', - 65536: 'IBV_PORT_CM_SUP', - 131072: 'IBV_PORT_SNMP_TUNNEL_SUP', - 262144: 'IBV_PORT_REINIT_SUP', - 524288: 'IBV_PORT_DEVICE_MGMT_SUP', - 1048576: 'IBV_PORT_VENDOR_CLASS_SUP', - 2097152: 'IBV_PORT_DR_NOTICE_SUP', - 4194304: 'IBV_PORT_CAP_MASK_NOTICE_SUP', - 8388608: 'IBV_PORT_BOOT_MGMT_SUP', - 16777216: 'IBV_PORT_LINK_LATENCY_SUP', - 33554432: 'IBV_PORT_CLIENT_REG_SUP', - 67108864: 'IBV_PORT_IP_BASED_GIDS', -} -IBV_PORT_SM = 2 -IBV_PORT_NOTICE_SUP = 4 -IBV_PORT_TRAP_SUP = 8 -IBV_PORT_OPT_IPD_SUP = 16 -IBV_PORT_AUTO_MIGR_SUP = 32 -IBV_PORT_SL_MAP_SUP = 64 -IBV_PORT_MKEY_NVRAM = 128 -IBV_PORT_PKEY_NVRAM = 256 -IBV_PORT_LED_INFO_SUP = 512 -IBV_PORT_SYS_IMAGE_GUID_SUP = 2048 -IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 4096 -IBV_PORT_EXTENDED_SPEEDS_SUP = 16384 -IBV_PORT_CAP_MASK2_SUP = 32768 -IBV_PORT_CM_SUP = 65536 -IBV_PORT_SNMP_TUNNEL_SUP = 131072 -IBV_PORT_REINIT_SUP = 262144 -IBV_PORT_DEVICE_MGMT_SUP = 524288 -IBV_PORT_VENDOR_CLASS_SUP = 1048576 -IBV_PORT_DR_NOTICE_SUP = 2097152 -IBV_PORT_CAP_MASK_NOTICE_SUP = 4194304 -IBV_PORT_BOOT_MGMT_SUP = 8388608 -IBV_PORT_LINK_LATENCY_SUP = 16777216 -IBV_PORT_CLIENT_REG_SUP = 33554432 -IBV_PORT_IP_BASED_GIDS = 67108864 -ibv_port_cap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_port_cap_flags2' -ibv_port_cap_flags2__enumvalues = { - 1: 'IBV_PORT_SET_NODE_DESC_SUP', - 2: 'IBV_PORT_INFO_EXT_SUP', - 4: 'IBV_PORT_VIRT_SUP', - 8: 'IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP', - 16: 'IBV_PORT_LINK_WIDTH_2X_SUP', - 32: 'IBV_PORT_LINK_SPEED_HDR_SUP', - 1024: 'IBV_PORT_LINK_SPEED_NDR_SUP', - 4096: 'IBV_PORT_LINK_SPEED_XDR_SUP', -} -IBV_PORT_SET_NODE_DESC_SUP = 1 -IBV_PORT_INFO_EXT_SUP = 2 -IBV_PORT_VIRT_SUP = 4 -IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP = 8 -IBV_PORT_LINK_WIDTH_2X_SUP = 16 -IBV_PORT_LINK_SPEED_HDR_SUP = 32 -IBV_PORT_LINK_SPEED_NDR_SUP = 1024 -IBV_PORT_LINK_SPEED_XDR_SUP = 4096 -ibv_port_cap_flags2 = ctypes.c_uint32 # enum -class struct_ibv_port_attr(Structure): - pass - -struct_ibv_port_attr._pack_ = 1 # source:False -struct_ibv_port_attr._fields_ = [ - ('state', ibv_port_state), - ('max_mtu', ibv_mtu), - ('active_mtu', ibv_mtu), - ('gid_tbl_len', ctypes.c_int32), - ('port_cap_flags', ctypes.c_uint32), - ('max_msg_sz', ctypes.c_uint32), - ('bad_pkey_cntr', ctypes.c_uint32), - ('qkey_viol_cntr', ctypes.c_uint32), - ('pkey_tbl_len', ctypes.c_uint16), - ('lid', ctypes.c_uint16), - ('sm_lid', ctypes.c_uint16), - ('lmc', ctypes.c_ubyte), - ('max_vl_num', ctypes.c_ubyte), - ('sm_sl', ctypes.c_ubyte), - ('subnet_timeout', ctypes.c_ubyte), - ('init_type_reply', ctypes.c_ubyte), - ('active_width', ctypes.c_ubyte), - ('active_speed', ctypes.c_ubyte), - ('phys_state', ctypes.c_ubyte), - ('link_layer', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('port_cap_flags2', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('active_speed_ex', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_event_type' -ibv_event_type__enumvalues = { - 0: 'IBV_EVENT_CQ_ERR', - 1: 'IBV_EVENT_QP_FATAL', - 2: 'IBV_EVENT_QP_REQ_ERR', - 3: 'IBV_EVENT_QP_ACCESS_ERR', - 4: 'IBV_EVENT_COMM_EST', - 5: 'IBV_EVENT_SQ_DRAINED', - 6: 'IBV_EVENT_PATH_MIG', - 7: 'IBV_EVENT_PATH_MIG_ERR', - 8: 'IBV_EVENT_DEVICE_FATAL', - 9: 'IBV_EVENT_PORT_ACTIVE', - 10: 'IBV_EVENT_PORT_ERR', - 11: 'IBV_EVENT_LID_CHANGE', - 12: 'IBV_EVENT_PKEY_CHANGE', - 13: 'IBV_EVENT_SM_CHANGE', - 14: 'IBV_EVENT_SRQ_ERR', - 15: 'IBV_EVENT_SRQ_LIMIT_REACHED', - 16: 'IBV_EVENT_QP_LAST_WQE_REACHED', - 17: 'IBV_EVENT_CLIENT_REREGISTER', - 18: 'IBV_EVENT_GID_CHANGE', - 19: 'IBV_EVENT_WQ_FATAL', -} -IBV_EVENT_CQ_ERR = 0 -IBV_EVENT_QP_FATAL = 1 -IBV_EVENT_QP_REQ_ERR = 2 -IBV_EVENT_QP_ACCESS_ERR = 3 -IBV_EVENT_COMM_EST = 4 -IBV_EVENT_SQ_DRAINED = 5 -IBV_EVENT_PATH_MIG = 6 -IBV_EVENT_PATH_MIG_ERR = 7 -IBV_EVENT_DEVICE_FATAL = 8 -IBV_EVENT_PORT_ACTIVE = 9 -IBV_EVENT_PORT_ERR = 10 -IBV_EVENT_LID_CHANGE = 11 -IBV_EVENT_PKEY_CHANGE = 12 -IBV_EVENT_SM_CHANGE = 13 -IBV_EVENT_SRQ_ERR = 14 -IBV_EVENT_SRQ_LIMIT_REACHED = 15 -IBV_EVENT_QP_LAST_WQE_REACHED = 16 -IBV_EVENT_CLIENT_REREGISTER = 17 -IBV_EVENT_GID_CHANGE = 18 -IBV_EVENT_WQ_FATAL = 19 -ibv_event_type = ctypes.c_uint32 # enum -class struct_ibv_async_event(Structure): - pass - -class union_ibv_async_event_element(Union): - pass - -class struct_ibv_wq(Structure): - pass - -union_ibv_async_event_element._pack_ = 1 # source:False -union_ibv_async_event_element._fields_ = [ - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('qp', ctypes.POINTER(struct_ibv_qp)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('wq', ctypes.POINTER(struct_ibv_wq)), - ('port_num', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_async_event._pack_ = 1 # source:False -struct_ibv_async_event._fields_ = [ - ('element', union_ibv_async_event_element), - ('event_type', ibv_event_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_wq_state' -ibv_wq_state__enumvalues = { - 0: 'IBV_WQS_RESET', - 1: 'IBV_WQS_RDY', - 2: 'IBV_WQS_ERR', - 3: 'IBV_WQS_UNKNOWN', -} -IBV_WQS_RESET = 0 -IBV_WQS_RDY = 1 -IBV_WQS_ERR = 2 -IBV_WQS_UNKNOWN = 3 -ibv_wq_state = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wq_type' -ibv_wq_type__enumvalues = { - 0: 'IBV_WQT_RQ', -} -IBV_WQT_RQ = 0 -ibv_wq_type = ctypes.c_uint32 # enum -struct_ibv_wq._pack_ = 1 # source:False -struct_ibv_wq._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('wq_context', ctypes.POINTER(None)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('wq_num', ctypes.c_uint32), - ('handle', ctypes.c_uint32), - ('state', ibv_wq_state), - ('wq_type', ibv_wq_type), - ('post_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('events_completed', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - -try: - ibv_wc_status_str = _libraries['libibverbs'].ibv_wc_status_str - ibv_wc_status_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_wc_status_str.argtypes = [ibv_wc_status] -except AttributeError: - pass - -# values for enumeration 'c__Ea_IBV_WC_IP_CSUM_OK_SHIFT' -c__Ea_IBV_WC_IP_CSUM_OK_SHIFT__enumvalues = { - 2: 'IBV_WC_IP_CSUM_OK_SHIFT', -} -IBV_WC_IP_CSUM_OK_SHIFT = 2 -c__Ea_IBV_WC_IP_CSUM_OK_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_create_cq_wc_flags' -ibv_create_cq_wc_flags__enumvalues = { - 1: 'IBV_WC_EX_WITH_BYTE_LEN', - 2: 'IBV_WC_EX_WITH_IMM', - 4: 'IBV_WC_EX_WITH_QP_NUM', - 8: 'IBV_WC_EX_WITH_SRC_QP', - 16: 'IBV_WC_EX_WITH_SLID', - 32: 'IBV_WC_EX_WITH_SL', - 64: 'IBV_WC_EX_WITH_DLID_PATH_BITS', - 128: 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP', - 256: 'IBV_WC_EX_WITH_CVLAN', - 512: 'IBV_WC_EX_WITH_FLOW_TAG', - 1024: 'IBV_WC_EX_WITH_TM_INFO', - 2048: 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK', -} -IBV_WC_EX_WITH_BYTE_LEN = 1 -IBV_WC_EX_WITH_IMM = 2 -IBV_WC_EX_WITH_QP_NUM = 4 -IBV_WC_EX_WITH_SRC_QP = 8 -IBV_WC_EX_WITH_SLID = 16 -IBV_WC_EX_WITH_SL = 32 -IBV_WC_EX_WITH_DLID_PATH_BITS = 64 -IBV_WC_EX_WITH_COMPLETION_TIMESTAMP = 128 -IBV_WC_EX_WITH_CVLAN = 256 -IBV_WC_EX_WITH_FLOW_TAG = 512 -IBV_WC_EX_WITH_TM_INFO = 1024 -IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK = 2048 -ibv_create_cq_wc_flags = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IBV_WC_STANDARD_FLAGS' -c__Ea_IBV_WC_STANDARD_FLAGS__enumvalues = { - 127: 'IBV_WC_STANDARD_FLAGS', -} -IBV_WC_STANDARD_FLAGS = 127 -c__Ea_IBV_WC_STANDARD_FLAGS = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS' -c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS__enumvalues = { - 4095: 'IBV_CREATE_CQ_SUP_WC_FLAGS', -} -IBV_CREATE_CQ_SUP_WC_FLAGS = 4095 -c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wc_flags' -ibv_wc_flags__enumvalues = { - 1: 'IBV_WC_GRH', - 2: 'IBV_WC_WITH_IMM', - 4: 'IBV_WC_IP_CSUM_OK', - 8: 'IBV_WC_WITH_INV', - 16: 'IBV_WC_TM_SYNC_REQ', - 32: 'IBV_WC_TM_MATCH', - 64: 'IBV_WC_TM_DATA_VALID', -} -IBV_WC_GRH = 1 -IBV_WC_WITH_IMM = 2 -IBV_WC_IP_CSUM_OK = 4 -IBV_WC_WITH_INV = 8 -IBV_WC_TM_SYNC_REQ = 16 -IBV_WC_TM_MATCH = 32 -IBV_WC_TM_DATA_VALID = 64 -ibv_wc_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_access_flags' -ibv_access_flags__enumvalues = { - 1: 'IBV_ACCESS_LOCAL_WRITE', - 2: 'IBV_ACCESS_REMOTE_WRITE', - 4: 'IBV_ACCESS_REMOTE_READ', - 8: 'IBV_ACCESS_REMOTE_ATOMIC', - 16: 'IBV_ACCESS_MW_BIND', - 32: 'IBV_ACCESS_ZERO_BASED', - 64: 'IBV_ACCESS_ON_DEMAND', - 128: 'IBV_ACCESS_HUGETLB', - 256: 'IBV_ACCESS_FLUSH_GLOBAL', - 512: 'IBV_ACCESS_FLUSH_PERSISTENT', - 1048576: 'IBV_ACCESS_RELAXED_ORDERING', -} -IBV_ACCESS_LOCAL_WRITE = 1 -IBV_ACCESS_REMOTE_WRITE = 2 -IBV_ACCESS_REMOTE_READ = 4 -IBV_ACCESS_REMOTE_ATOMIC = 8 -IBV_ACCESS_MW_BIND = 16 -IBV_ACCESS_ZERO_BASED = 32 -IBV_ACCESS_ON_DEMAND = 64 -IBV_ACCESS_HUGETLB = 128 -IBV_ACCESS_FLUSH_GLOBAL = 256 -IBV_ACCESS_FLUSH_PERSISTENT = 512 -IBV_ACCESS_RELAXED_ORDERING = 1048576 -ibv_access_flags = ctypes.c_uint32 # enum -class struct_ibv_td_init_attr(Structure): - pass - -struct_ibv_td_init_attr._pack_ = 1 # source:False -struct_ibv_td_init_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - -class struct_ibv_td(Structure): - pass - -struct_ibv_td._pack_ = 1 # source:False -struct_ibv_td._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - - -# values for enumeration 'ibv_xrcd_init_attr_mask' -ibv_xrcd_init_attr_mask__enumvalues = { - 1: 'IBV_XRCD_INIT_ATTR_FD', - 2: 'IBV_XRCD_INIT_ATTR_OFLAGS', - 4: 'IBV_XRCD_INIT_ATTR_RESERVED', -} -IBV_XRCD_INIT_ATTR_FD = 1 -IBV_XRCD_INIT_ATTR_OFLAGS = 2 -IBV_XRCD_INIT_ATTR_RESERVED = 4 -ibv_xrcd_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_xrcd_init_attr(Structure): - pass - -struct_ibv_xrcd_init_attr._pack_ = 1 # source:False -struct_ibv_xrcd_init_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('fd', ctypes.c_int32), - ('oflags', ctypes.c_int32), -] - -class struct_ibv_xrcd(Structure): - pass - -struct_ibv_xrcd._pack_ = 1 # source:False -struct_ibv_xrcd._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - - -# values for enumeration 'ibv_rereg_mr_flags' -ibv_rereg_mr_flags__enumvalues = { - 1: 'IBV_REREG_MR_CHANGE_TRANSLATION', - 2: 'IBV_REREG_MR_CHANGE_PD', - 4: 'IBV_REREG_MR_CHANGE_ACCESS', - 7: 'IBV_REREG_MR_FLAGS_SUPPORTED', -} -IBV_REREG_MR_CHANGE_TRANSLATION = 1 -IBV_REREG_MR_CHANGE_PD = 2 -IBV_REREG_MR_CHANGE_ACCESS = 4 -IBV_REREG_MR_FLAGS_SUPPORTED = 7 -ibv_rereg_mr_flags = ctypes.c_uint32 # enum -class struct_ibv_global_route(Structure): - pass - -struct_ibv_global_route._pack_ = 1 # source:False -struct_ibv_global_route._fields_ = [ - ('dgid', union_ibv_gid), - ('flow_label', ctypes.c_uint32), - ('sgid_index', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -class struct_ibv_grh(Structure): - pass - -struct_ibv_grh._pack_ = 1 # source:False -struct_ibv_grh._fields_ = [ - ('version_tclass_flow', ctypes.c_uint32), - ('paylen', ctypes.c_uint16), - ('next_hdr', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('sgid', union_ibv_gid), - ('dgid', union_ibv_gid), -] - - -# values for enumeration 'ibv_rate' -ibv_rate__enumvalues = { - 0: 'IBV_RATE_MAX', - 2: 'IBV_RATE_2_5_GBPS', - 5: 'IBV_RATE_5_GBPS', - 3: 'IBV_RATE_10_GBPS', - 6: 'IBV_RATE_20_GBPS', - 4: 'IBV_RATE_30_GBPS', - 7: 'IBV_RATE_40_GBPS', - 8: 'IBV_RATE_60_GBPS', - 9: 'IBV_RATE_80_GBPS', - 10: 'IBV_RATE_120_GBPS', - 11: 'IBV_RATE_14_GBPS', - 12: 'IBV_RATE_56_GBPS', - 13: 'IBV_RATE_112_GBPS', - 14: 'IBV_RATE_168_GBPS', - 15: 'IBV_RATE_25_GBPS', - 16: 'IBV_RATE_100_GBPS', - 17: 'IBV_RATE_200_GBPS', - 18: 'IBV_RATE_300_GBPS', - 19: 'IBV_RATE_28_GBPS', - 20: 'IBV_RATE_50_GBPS', - 21: 'IBV_RATE_400_GBPS', - 22: 'IBV_RATE_600_GBPS', - 23: 'IBV_RATE_800_GBPS', - 24: 'IBV_RATE_1200_GBPS', -} -IBV_RATE_MAX = 0 -IBV_RATE_2_5_GBPS = 2 -IBV_RATE_5_GBPS = 5 -IBV_RATE_10_GBPS = 3 -IBV_RATE_20_GBPS = 6 -IBV_RATE_30_GBPS = 4 -IBV_RATE_40_GBPS = 7 -IBV_RATE_60_GBPS = 8 -IBV_RATE_80_GBPS = 9 -IBV_RATE_120_GBPS = 10 -IBV_RATE_14_GBPS = 11 -IBV_RATE_56_GBPS = 12 -IBV_RATE_112_GBPS = 13 -IBV_RATE_168_GBPS = 14 -IBV_RATE_25_GBPS = 15 -IBV_RATE_100_GBPS = 16 -IBV_RATE_200_GBPS = 17 -IBV_RATE_300_GBPS = 18 -IBV_RATE_28_GBPS = 19 -IBV_RATE_50_GBPS = 20 -IBV_RATE_400_GBPS = 21 -IBV_RATE_600_GBPS = 22 -IBV_RATE_800_GBPS = 23 -IBV_RATE_1200_GBPS = 24 -ibv_rate = ctypes.c_uint32 # enum -try: - ibv_rate_to_mult = _libraries['libibverbs'].ibv_rate_to_mult - ibv_rate_to_mult.restype = ctypes.c_int32 - ibv_rate_to_mult.argtypes = [ibv_rate] -except AttributeError: - pass -try: - mult_to_ibv_rate = _libraries['libibverbs'].mult_to_ibv_rate - mult_to_ibv_rate.restype = ibv_rate - mult_to_ibv_rate.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - ibv_rate_to_mbps = _libraries['libibverbs'].ibv_rate_to_mbps - ibv_rate_to_mbps.restype = ctypes.c_int32 - ibv_rate_to_mbps.argtypes = [ibv_rate] -except AttributeError: - pass -try: - mbps_to_ibv_rate = _libraries['libibverbs'].mbps_to_ibv_rate - mbps_to_ibv_rate.restype = ibv_rate - mbps_to_ibv_rate.argtypes = [ctypes.c_int32] -except AttributeError: - pass -class struct_ibv_ah_attr(Structure): - pass - -struct_ibv_ah_attr._pack_ = 1 # source:False -struct_ibv_ah_attr._fields_ = [ - ('grh', struct_ibv_global_route), - ('dlid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('src_path_bits', ctypes.c_ubyte), - ('static_rate', ctypes.c_ubyte), - ('is_global', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - - -# values for enumeration 'ibv_srq_attr_mask' -ibv_srq_attr_mask__enumvalues = { - 1: 'IBV_SRQ_MAX_WR', - 2: 'IBV_SRQ_LIMIT', -} -IBV_SRQ_MAX_WR = 1 -IBV_SRQ_LIMIT = 2 -ibv_srq_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_srq_attr(Structure): - pass - -struct_ibv_srq_attr._pack_ = 1 # source:False -struct_ibv_srq_attr._fields_ = [ - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), -] - -class struct_ibv_srq_init_attr(Structure): - pass - -struct_ibv_srq_init_attr._pack_ = 1 # source:False -struct_ibv_srq_init_attr._fields_ = [ - ('srq_context', ctypes.POINTER(None)), - ('attr', struct_ibv_srq_attr), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_srq_type' -ibv_srq_type__enumvalues = { - 0: 'IBV_SRQT_BASIC', - 1: 'IBV_SRQT_XRC', - 2: 'IBV_SRQT_TM', -} -IBV_SRQT_BASIC = 0 -IBV_SRQT_XRC = 1 -IBV_SRQT_TM = 2 -ibv_srq_type = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_srq_init_attr_mask' -ibv_srq_init_attr_mask__enumvalues = { - 1: 'IBV_SRQ_INIT_ATTR_TYPE', - 2: 'IBV_SRQ_INIT_ATTR_PD', - 4: 'IBV_SRQ_INIT_ATTR_XRCD', - 8: 'IBV_SRQ_INIT_ATTR_CQ', - 16: 'IBV_SRQ_INIT_ATTR_TM', - 32: 'IBV_SRQ_INIT_ATTR_RESERVED', -} -IBV_SRQ_INIT_ATTR_TYPE = 1 -IBV_SRQ_INIT_ATTR_PD = 2 -IBV_SRQ_INIT_ATTR_XRCD = 4 -IBV_SRQ_INIT_ATTR_CQ = 8 -IBV_SRQ_INIT_ATTR_TM = 16 -IBV_SRQ_INIT_ATTR_RESERVED = 32 -ibv_srq_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_tm_cap(Structure): - pass - -struct_ibv_tm_cap._pack_ = 1 # source:False -struct_ibv_tm_cap._fields_ = [ - ('max_num_tags', ctypes.c_uint32), - ('max_ops', ctypes.c_uint32), -] - -class struct_ibv_srq_init_attr_ex(Structure): - pass - -struct_ibv_srq_init_attr_ex._pack_ = 1 # source:False -struct_ibv_srq_init_attr_ex._fields_ = [ - ('srq_context', ctypes.POINTER(None)), - ('attr', struct_ibv_srq_attr), - ('comp_mask', ctypes.c_uint32), - ('srq_type', ibv_srq_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('tm_cap', struct_ibv_tm_cap), -] - - -# values for enumeration 'ibv_wq_init_attr_mask' -ibv_wq_init_attr_mask__enumvalues = { - 1: 'IBV_WQ_INIT_ATTR_FLAGS', - 2: 'IBV_WQ_INIT_ATTR_RESERVED', -} -IBV_WQ_INIT_ATTR_FLAGS = 1 -IBV_WQ_INIT_ATTR_RESERVED = 2 -ibv_wq_init_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wq_flags' -ibv_wq_flags__enumvalues = { - 1: 'IBV_WQ_FLAGS_CVLAN_STRIPPING', - 2: 'IBV_WQ_FLAGS_SCATTER_FCS', - 4: 'IBV_WQ_FLAGS_DELAY_DROP', - 8: 'IBV_WQ_FLAGS_PCI_WRITE_END_PADDING', - 16: 'IBV_WQ_FLAGS_RESERVED', -} -IBV_WQ_FLAGS_CVLAN_STRIPPING = 1 -IBV_WQ_FLAGS_SCATTER_FCS = 2 -IBV_WQ_FLAGS_DELAY_DROP = 4 -IBV_WQ_FLAGS_PCI_WRITE_END_PADDING = 8 -IBV_WQ_FLAGS_RESERVED = 16 -ibv_wq_flags = ctypes.c_uint32 # enum -class struct_ibv_wq_init_attr(Structure): - pass - -struct_ibv_wq_init_attr._pack_ = 1 # source:False -struct_ibv_wq_init_attr._fields_ = [ - ('wq_context', ctypes.POINTER(None)), - ('wq_type', ibv_wq_type), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('comp_mask', ctypes.c_uint32), - ('create_flags', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_wq_attr_mask' -ibv_wq_attr_mask__enumvalues = { - 1: 'IBV_WQ_ATTR_STATE', - 2: 'IBV_WQ_ATTR_CURR_STATE', - 4: 'IBV_WQ_ATTR_FLAGS', - 8: 'IBV_WQ_ATTR_RESERVED', -} -IBV_WQ_ATTR_STATE = 1 -IBV_WQ_ATTR_CURR_STATE = 2 -IBV_WQ_ATTR_FLAGS = 4 -IBV_WQ_ATTR_RESERVED = 8 -ibv_wq_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_wq_attr(Structure): - pass - -struct_ibv_wq_attr._pack_ = 1 # source:False -struct_ibv_wq_attr._fields_ = [ - ('attr_mask', ctypes.c_uint32), - ('wq_state', ibv_wq_state), - ('curr_wq_state', ibv_wq_state), - ('flags', ctypes.c_uint32), - ('flags_mask', ctypes.c_uint32), -] - -class struct_ibv_rwq_ind_table(Structure): - pass - -struct_ibv_rwq_ind_table._pack_ = 1 # source:False -struct_ibv_rwq_ind_table._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('ind_tbl_handle', ctypes.c_int32), - ('ind_tbl_num', ctypes.c_int32), - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_ind_table_init_attr_mask' -ibv_ind_table_init_attr_mask__enumvalues = { - 1: 'IBV_CREATE_IND_TABLE_RESERVED', -} -IBV_CREATE_IND_TABLE_RESERVED = 1 -ibv_ind_table_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_rwq_ind_table_init_attr(Structure): - pass - -struct_ibv_rwq_ind_table_init_attr._pack_ = 1 # source:False -struct_ibv_rwq_ind_table_init_attr._fields_ = [ - ('log_ind_tbl_size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ind_tbl', ctypes.POINTER(ctypes.POINTER(struct_ibv_wq))), - ('comp_mask', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_ibv_qp_cap(Structure): - pass - -struct_ibv_qp_cap._pack_ = 1 # source:False -struct_ibv_qp_cap._fields_ = [ - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), -] - -class struct_ibv_qp_init_attr(Structure): - pass - -struct_ibv_qp_init_attr._pack_ = 1 # source:False -struct_ibv_qp_init_attr._fields_ = [ - ('qp_context', ctypes.POINTER(None)), - ('send_cq', ctypes.POINTER(struct_ibv_cq)), - ('recv_cq', ctypes.POINTER(struct_ibv_cq)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('cap', struct_ibv_qp_cap), - ('qp_type', ibv_qp_type), - ('sq_sig_all', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_qp_init_attr_mask' -ibv_qp_init_attr_mask__enumvalues = { - 1: 'IBV_QP_INIT_ATTR_PD', - 2: 'IBV_QP_INIT_ATTR_XRCD', - 4: 'IBV_QP_INIT_ATTR_CREATE_FLAGS', - 8: 'IBV_QP_INIT_ATTR_MAX_TSO_HEADER', - 16: 'IBV_QP_INIT_ATTR_IND_TABLE', - 32: 'IBV_QP_INIT_ATTR_RX_HASH', - 64: 'IBV_QP_INIT_ATTR_SEND_OPS_FLAGS', -} -IBV_QP_INIT_ATTR_PD = 1 -IBV_QP_INIT_ATTR_XRCD = 2 -IBV_QP_INIT_ATTR_CREATE_FLAGS = 4 -IBV_QP_INIT_ATTR_MAX_TSO_HEADER = 8 -IBV_QP_INIT_ATTR_IND_TABLE = 16 -IBV_QP_INIT_ATTR_RX_HASH = 32 -IBV_QP_INIT_ATTR_SEND_OPS_FLAGS = 64 -ibv_qp_init_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_qp_create_flags' -ibv_qp_create_flags__enumvalues = { - 2: 'IBV_QP_CREATE_BLOCK_SELF_MCAST_LB', - 256: 'IBV_QP_CREATE_SCATTER_FCS', - 512: 'IBV_QP_CREATE_CVLAN_STRIPPING', - 1024: 'IBV_QP_CREATE_SOURCE_QPN', - 2048: 'IBV_QP_CREATE_PCI_WRITE_END_PADDING', -} -IBV_QP_CREATE_BLOCK_SELF_MCAST_LB = 2 -IBV_QP_CREATE_SCATTER_FCS = 256 -IBV_QP_CREATE_CVLAN_STRIPPING = 512 -IBV_QP_CREATE_SOURCE_QPN = 1024 -IBV_QP_CREATE_PCI_WRITE_END_PADDING = 2048 -ibv_qp_create_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_qp_create_send_ops_flags' -ibv_qp_create_send_ops_flags__enumvalues = { - 1: 'IBV_QP_EX_WITH_RDMA_WRITE', - 2: 'IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM', - 4: 'IBV_QP_EX_WITH_SEND', - 8: 'IBV_QP_EX_WITH_SEND_WITH_IMM', - 16: 'IBV_QP_EX_WITH_RDMA_READ', - 32: 'IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP', - 64: 'IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD', - 128: 'IBV_QP_EX_WITH_LOCAL_INV', - 256: 'IBV_QP_EX_WITH_BIND_MW', - 512: 'IBV_QP_EX_WITH_SEND_WITH_INV', - 1024: 'IBV_QP_EX_WITH_TSO', - 2048: 'IBV_QP_EX_WITH_FLUSH', - 4096: 'IBV_QP_EX_WITH_ATOMIC_WRITE', -} -IBV_QP_EX_WITH_RDMA_WRITE = 1 -IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM = 2 -IBV_QP_EX_WITH_SEND = 4 -IBV_QP_EX_WITH_SEND_WITH_IMM = 8 -IBV_QP_EX_WITH_RDMA_READ = 16 -IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP = 32 -IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD = 64 -IBV_QP_EX_WITH_LOCAL_INV = 128 -IBV_QP_EX_WITH_BIND_MW = 256 -IBV_QP_EX_WITH_SEND_WITH_INV = 512 -IBV_QP_EX_WITH_TSO = 1024 -IBV_QP_EX_WITH_FLUSH = 2048 -IBV_QP_EX_WITH_ATOMIC_WRITE = 4096 -ibv_qp_create_send_ops_flags = ctypes.c_uint32 # enum -class struct_ibv_rx_hash_conf(Structure): - pass - -struct_ibv_rx_hash_conf._pack_ = 1 # source:False -struct_ibv_rx_hash_conf._fields_ = [ - ('rx_hash_function', ctypes.c_ubyte), - ('rx_hash_key_len', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('rx_hash_key', ctypes.POINTER(ctypes.c_ubyte)), - ('rx_hash_fields_mask', ctypes.c_uint64), -] - -class struct_ibv_qp_init_attr_ex(Structure): - pass - -struct_ibv_qp_init_attr_ex._pack_ = 1 # source:False -struct_ibv_qp_init_attr_ex._fields_ = [ - ('qp_context', ctypes.POINTER(None)), - ('send_cq', ctypes.POINTER(struct_ibv_cq)), - ('recv_cq', ctypes.POINTER(struct_ibv_cq)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('cap', struct_ibv_qp_cap), - ('qp_type', ibv_qp_type), - ('sq_sig_all', ctypes.c_int32), - ('comp_mask', ctypes.c_uint32), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), - ('create_flags', ctypes.c_uint32), - ('max_tso_header', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('rwq_ind_tbl', ctypes.POINTER(struct_ibv_rwq_ind_table)), - ('rx_hash_conf', struct_ibv_rx_hash_conf), - ('source_qpn', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('send_ops_flags', ctypes.c_uint64), -] - - -# values for enumeration 'ibv_qp_open_attr_mask' -ibv_qp_open_attr_mask__enumvalues = { - 1: 'IBV_QP_OPEN_ATTR_NUM', - 2: 'IBV_QP_OPEN_ATTR_XRCD', - 4: 'IBV_QP_OPEN_ATTR_CONTEXT', - 8: 'IBV_QP_OPEN_ATTR_TYPE', - 16: 'IBV_QP_OPEN_ATTR_RESERVED', -} -IBV_QP_OPEN_ATTR_NUM = 1 -IBV_QP_OPEN_ATTR_XRCD = 2 -IBV_QP_OPEN_ATTR_CONTEXT = 4 -IBV_QP_OPEN_ATTR_TYPE = 8 -IBV_QP_OPEN_ATTR_RESERVED = 16 -ibv_qp_open_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_qp_open_attr(Structure): - pass - -struct_ibv_qp_open_attr._pack_ = 1 # source:False -struct_ibv_qp_open_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('qp_num', ctypes.c_uint32), - ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), - ('qp_context', ctypes.POINTER(None)), - ('qp_type', ibv_qp_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_qp_attr_mask' -ibv_qp_attr_mask__enumvalues = { - 1: 'IBV_QP_STATE', - 2: 'IBV_QP_CUR_STATE', - 4: 'IBV_QP_EN_SQD_ASYNC_NOTIFY', - 8: 'IBV_QP_ACCESS_FLAGS', - 16: 'IBV_QP_PKEY_INDEX', - 32: 'IBV_QP_PORT', - 64: 'IBV_QP_QKEY', - 128: 'IBV_QP_AV', - 256: 'IBV_QP_PATH_MTU', - 512: 'IBV_QP_TIMEOUT', - 1024: 'IBV_QP_RETRY_CNT', - 2048: 'IBV_QP_RNR_RETRY', - 4096: 'IBV_QP_RQ_PSN', - 8192: 'IBV_QP_MAX_QP_RD_ATOMIC', - 16384: 'IBV_QP_ALT_PATH', - 32768: 'IBV_QP_MIN_RNR_TIMER', - 65536: 'IBV_QP_SQ_PSN', - 131072: 'IBV_QP_MAX_DEST_RD_ATOMIC', - 262144: 'IBV_QP_PATH_MIG_STATE', - 524288: 'IBV_QP_CAP', - 1048576: 'IBV_QP_DEST_QPN', - 33554432: 'IBV_QP_RATE_LIMIT', -} -IBV_QP_STATE = 1 -IBV_QP_CUR_STATE = 2 -IBV_QP_EN_SQD_ASYNC_NOTIFY = 4 -IBV_QP_ACCESS_FLAGS = 8 -IBV_QP_PKEY_INDEX = 16 -IBV_QP_PORT = 32 -IBV_QP_QKEY = 64 -IBV_QP_AV = 128 -IBV_QP_PATH_MTU = 256 -IBV_QP_TIMEOUT = 512 -IBV_QP_RETRY_CNT = 1024 -IBV_QP_RNR_RETRY = 2048 -IBV_QP_RQ_PSN = 4096 -IBV_QP_MAX_QP_RD_ATOMIC = 8192 -IBV_QP_ALT_PATH = 16384 -IBV_QP_MIN_RNR_TIMER = 32768 -IBV_QP_SQ_PSN = 65536 -IBV_QP_MAX_DEST_RD_ATOMIC = 131072 -IBV_QP_PATH_MIG_STATE = 262144 -IBV_QP_CAP = 524288 -IBV_QP_DEST_QPN = 1048576 -IBV_QP_RATE_LIMIT = 33554432 -ibv_qp_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_query_qp_data_in_order_flags' -ibv_query_qp_data_in_order_flags__enumvalues = { - 1: 'IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS', -} -IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS = 1 -ibv_query_qp_data_in_order_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_query_qp_data_in_order_caps' -ibv_query_qp_data_in_order_caps__enumvalues = { - 1: 'IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG', - 2: 'IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES', -} -IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG = 1 -IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES = 2 -ibv_query_qp_data_in_order_caps = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_mig_state' -ibv_mig_state__enumvalues = { - 0: 'IBV_MIG_MIGRATED', - 1: 'IBV_MIG_REARM', - 2: 'IBV_MIG_ARMED', -} -IBV_MIG_MIGRATED = 0 -IBV_MIG_REARM = 1 -IBV_MIG_ARMED = 2 -ibv_mig_state = ctypes.c_uint32 # enum -class struct_ibv_qp_attr(Structure): - pass - -struct_ibv_qp_attr._pack_ = 1 # source:False -struct_ibv_qp_attr._fields_ = [ - ('qp_state', ibv_qp_state), - ('cur_qp_state', ibv_qp_state), - ('path_mtu', ibv_mtu), - ('path_mig_state', ibv_mig_state), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('cap', struct_ibv_qp_cap), - ('ah_attr', struct_ibv_ah_attr), - ('alt_ah_attr', struct_ibv_ah_attr), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('en_sqd_async_notify', ctypes.c_ubyte), - ('sq_draining', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('rate_limit', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_ibv_qp_rate_limit_attr(Structure): - pass - -struct_ibv_qp_rate_limit_attr._pack_ = 1 # source:False -struct_ibv_qp_rate_limit_attr._fields_ = [ - ('rate_limit', ctypes.c_uint32), - ('max_burst_sz', ctypes.c_uint32), - ('typical_pkt_sz', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('comp_mask', ctypes.c_uint32), -] - -try: - ibv_wr_opcode_str = _libraries['libibverbs'].ibv_wr_opcode_str - ibv_wr_opcode_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_wr_opcode_str.argtypes = [ibv_wr_opcode] -except AttributeError: - pass - -# values for enumeration 'ibv_send_flags' -ibv_send_flags__enumvalues = { - 1: 'IBV_SEND_FENCE', - 2: 'IBV_SEND_SIGNALED', - 4: 'IBV_SEND_SOLICITED', - 8: 'IBV_SEND_INLINE', - 16: 'IBV_SEND_IP_CSUM', -} -IBV_SEND_FENCE = 1 -IBV_SEND_SIGNALED = 2 -IBV_SEND_SOLICITED = 4 -IBV_SEND_INLINE = 8 -IBV_SEND_IP_CSUM = 16 -ibv_send_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_placement_type' -ibv_placement_type__enumvalues = { - 1: 'IBV_FLUSH_GLOBAL', - 2: 'IBV_FLUSH_PERSISTENT', -} -IBV_FLUSH_GLOBAL = 1 -IBV_FLUSH_PERSISTENT = 2 -ibv_placement_type = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_selectivity_level' -ibv_selectivity_level__enumvalues = { - 0: 'IBV_FLUSH_RANGE', - 1: 'IBV_FLUSH_MR', -} -IBV_FLUSH_RANGE = 0 -IBV_FLUSH_MR = 1 -ibv_selectivity_level = ctypes.c_uint32 # enum -class struct_ibv_data_buf(Structure): - pass - -struct_ibv_data_buf._pack_ = 1 # source:False -struct_ibv_data_buf._fields_ = [ - ('addr', ctypes.POINTER(None)), - ('length', ctypes.c_uint64), -] - - -# values for enumeration 'ibv_ops_wr_opcode' -ibv_ops_wr_opcode__enumvalues = { - 0: 'IBV_WR_TAG_ADD', - 1: 'IBV_WR_TAG_DEL', - 2: 'IBV_WR_TAG_SYNC', -} -IBV_WR_TAG_ADD = 0 -IBV_WR_TAG_DEL = 1 -IBV_WR_TAG_SYNC = 2 -ibv_ops_wr_opcode = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_ops_flags' -ibv_ops_flags__enumvalues = { - 1: 'IBV_OPS_SIGNALED', - 2: 'IBV_OPS_TM_SYNC', -} -IBV_OPS_SIGNALED = 1 -IBV_OPS_TM_SYNC = 2 -ibv_ops_flags = ctypes.c_uint32 # enum -class struct_ibv_ops_wr(Structure): - pass - -class struct_ibv_ops_wr_tm(Structure): - pass - -class struct_ibv_ops_wr_0_add(Structure): - pass - -struct_ibv_ops_wr_0_add._pack_ = 1 # source:False -struct_ibv_ops_wr_0_add._fields_ = [ - ('recv_wr_id', ctypes.c_uint64), - ('sg_list', ctypes.POINTER(struct_ibv_sge)), - ('num_sge', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('tag', ctypes.c_uint64), - ('mask', ctypes.c_uint64), -] - -struct_ibv_ops_wr_tm._pack_ = 1 # source:False -struct_ibv_ops_wr_tm._fields_ = [ - ('unexpected_cnt', ctypes.c_uint32), - ('handle', ctypes.c_uint32), - ('add', struct_ibv_ops_wr_0_add), -] - -struct_ibv_ops_wr._pack_ = 1 # source:False -struct_ibv_ops_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('next', ctypes.POINTER(struct_ibv_ops_wr)), - ('opcode', ibv_ops_wr_opcode), - ('flags', ctypes.c_int32), - ('tm', struct_ibv_ops_wr_tm), -] - -class struct_ibv_qp_ex(Structure): - pass - -struct_ibv_qp_ex._pack_ = 1 # source:False -struct_ibv_qp_ex._fields_ = [ - ('qp_base', struct_ibv_qp), - ('comp_mask', ctypes.c_uint64), - ('wr_id', ctypes.c_uint64), - ('wr_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('wr_atomic_cmp_swp', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64)), - ('wr_atomic_fetch_add', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint64)), - ('wr_bind_mw', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_mw), ctypes.c_uint32, ctypes.POINTER(struct_ibv_mw_bind_info))), - ('wr_local_inv', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_rdma_read', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64)), - ('wr_rdma_write', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64)), - ('wr_rdma_write_imm', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint32)), - ('wr_send', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_send_imm', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_send_inv', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_send_tso', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), ctypes.c_uint16, ctypes.c_uint16)), - ('wr_set_ud_addr', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_ah), ctypes.c_uint32, ctypes.c_uint32)), - ('wr_set_xrc_srqn', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_set_inline_data', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), ctypes.c_uint64)), - ('wr_set_inline_data_list', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint64, ctypes.POINTER(struct_ibv_data_buf))), - ('wr_set_sge', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint32)), - ('wr_set_sge_list', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint64, ctypes.POINTER(struct_ibv_sge))), - ('wr_start', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_complete', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_abort', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_atomic_write', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.POINTER(None))), - ('wr_flush', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_ubyte, ctypes.c_ubyte)), -] - -try: - ibv_qp_to_qp_ex = _libraries['libibverbs'].ibv_qp_to_qp_ex - ibv_qp_to_qp_ex.restype = ctypes.POINTER(struct_ibv_qp_ex) - ibv_qp_to_qp_ex.argtypes = [ctypes.POINTER(struct_ibv_qp)] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -uint64_t = ctypes.c_uint64 -try: - ibv_wr_atomic_cmp_swp = _libraries['libibverbs'].ibv_wr_atomic_cmp_swp - ibv_wr_atomic_cmp_swp.restype = None - ibv_wr_atomic_cmp_swp.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - ibv_wr_atomic_fetch_add = _libraries['libibverbs'].ibv_wr_atomic_fetch_add - ibv_wr_atomic_fetch_add.restype = None - ibv_wr_atomic_fetch_add.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - ibv_wr_bind_mw = _libraries['libibverbs'].ibv_wr_bind_mw - ibv_wr_bind_mw.restype = None - ibv_wr_bind_mw.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_mw), uint32_t, ctypes.POINTER(struct_ibv_mw_bind_info)] -except AttributeError: - pass -try: - ibv_wr_local_inv = _libraries['libibverbs'].ibv_wr_local_inv - ibv_wr_local_inv.restype = None - ibv_wr_local_inv.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t] -except AttributeError: - pass -try: - ibv_wr_rdma_read = _libraries['libibverbs'].ibv_wr_rdma_read - ibv_wr_rdma_read.restype = None - ibv_wr_rdma_read.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t] -except AttributeError: - pass -try: - ibv_wr_rdma_write = _libraries['libibverbs'].ibv_wr_rdma_write - ibv_wr_rdma_write.restype = None - ibv_wr_rdma_write.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t] -except AttributeError: - pass -size_t = ctypes.c_uint64 -uint8_t = ctypes.c_uint8 -try: - ibv_wr_flush = _libraries['libibverbs'].ibv_wr_flush - ibv_wr_flush.restype = None - ibv_wr_flush.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, size_t, uint8_t, uint8_t] -except AttributeError: - pass -__be32 = ctypes.c_uint32 -try: - ibv_wr_rdma_write_imm = _libraries['libibverbs'].ibv_wr_rdma_write_imm - ibv_wr_rdma_write_imm.restype = None - ibv_wr_rdma_write_imm.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, __be32] -except AttributeError: - pass -try: - ibv_wr_send = _libraries['libibverbs'].ibv_wr_send - ibv_wr_send.restype = None - ibv_wr_send.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_send_imm = _libraries['libibverbs'].ibv_wr_send_imm - ibv_wr_send_imm.restype = None - ibv_wr_send_imm.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), __be32] -except AttributeError: - pass -try: - ibv_wr_send_inv = _libraries['libibverbs'].ibv_wr_send_inv - ibv_wr_send_inv.restype = None - ibv_wr_send_inv.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t] -except AttributeError: - pass -uint16_t = ctypes.c_uint16 -try: - ibv_wr_send_tso = _libraries['libibverbs'].ibv_wr_send_tso - ibv_wr_send_tso.restype = None - ibv_wr_send_tso.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), uint16_t, uint16_t] -except AttributeError: - pass -try: - ibv_wr_set_ud_addr = _libraries['libibverbs'].ibv_wr_set_ud_addr - ibv_wr_set_ud_addr.restype = None - ibv_wr_set_ud_addr.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_ah), uint32_t, uint32_t] -except AttributeError: - pass -try: - ibv_wr_set_xrc_srqn = _libraries['libibverbs'].ibv_wr_set_xrc_srqn - ibv_wr_set_xrc_srqn.restype = None - ibv_wr_set_xrc_srqn.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t] -except AttributeError: - pass -try: - ibv_wr_set_inline_data = _libraries['libibverbs'].ibv_wr_set_inline_data - ibv_wr_set_inline_data.restype = None - ibv_wr_set_inline_data.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - ibv_wr_set_inline_data_list = _libraries['libibverbs'].ibv_wr_set_inline_data_list - ibv_wr_set_inline_data_list.restype = None - ibv_wr_set_inline_data_list.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), size_t, ctypes.POINTER(struct_ibv_data_buf)] -except AttributeError: - pass -try: - ibv_wr_set_sge = _libraries['libibverbs'].ibv_wr_set_sge - ibv_wr_set_sge.restype = None - ibv_wr_set_sge.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint32_t] -except AttributeError: - pass -try: - ibv_wr_set_sge_list = _libraries['libibverbs'].ibv_wr_set_sge_list - ibv_wr_set_sge_list.restype = None - ibv_wr_set_sge_list.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), size_t, ctypes.POINTER(struct_ibv_sge)] -except AttributeError: - pass -try: - ibv_wr_start = _libraries['libibverbs'].ibv_wr_start - ibv_wr_start.restype = None - ibv_wr_start.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_complete = _libraries['libibverbs'].ibv_wr_complete - ibv_wr_complete.restype = ctypes.c_int32 - ibv_wr_complete.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_abort = _libraries['libibverbs'].ibv_wr_abort - ibv_wr_abort.restype = None - ibv_wr_abort.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_atomic_write = _libraries['libibverbs'].ibv_wr_atomic_write - ibv_wr_atomic_write.restype = None - ibv_wr_atomic_write.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, ctypes.POINTER(None)] -except AttributeError: - pass -class struct_ibv_ece(Structure): - pass - -struct_ibv_ece._pack_ = 1 # source:False -struct_ibv_ece._fields_ = [ - ('vendor_id', ctypes.c_uint32), - ('options', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - -class struct_ibv_poll_cq_attr(Structure): - pass - -struct_ibv_poll_cq_attr._pack_ = 1 # source:False -struct_ibv_poll_cq_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - -class struct_ibv_wc_tm_info(Structure): - pass - -struct_ibv_wc_tm_info._pack_ = 1 # source:False -struct_ibv_wc_tm_info._fields_ = [ - ('tag', ctypes.c_uint64), - ('priv', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_cq_ex(Structure): - pass - -struct_ibv_cq_ex._pack_ = 1 # source:False -struct_ibv_cq_ex._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('channel', ctypes.POINTER(struct_ibv_comp_channel)), - ('cq_context', ctypes.POINTER(None)), - ('handle', ctypes.c_uint32), - ('cqe', ctypes.c_int32), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('comp_events_completed', ctypes.c_uint32), - ('async_events_completed', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), - ('status', ibv_wc_status), - ('wr_id', ctypes.c_uint64), - ('start_poll', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_poll_cq_attr))), - ('next_poll', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq_ex))), - ('end_poll', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_opcode', ctypes.CFUNCTYPE(ibv_wc_opcode, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_vendor_err', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_byte_len', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_imm_data', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_qp_num', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_src_qp', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_wc_flags', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_slid', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_sl', ctypes.CFUNCTYPE(ctypes.c_ubyte, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_dlid_path_bits', ctypes.CFUNCTYPE(ctypes.c_ubyte, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_completion_ts', ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_cvlan', ctypes.CFUNCTYPE(ctypes.c_uint16, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_flow_tag', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_tm_info', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_wc_tm_info))), - ('read_completion_wallclock_ns', ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_ibv_cq_ex))), -] - -try: - ibv_cq_ex_to_cq = _libraries['libibverbs'].ibv_cq_ex_to_cq - ibv_cq_ex_to_cq.restype = ctypes.POINTER(struct_ibv_cq) - ibv_cq_ex_to_cq.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass - -# values for enumeration 'ibv_cq_attr_mask' -ibv_cq_attr_mask__enumvalues = { - 1: 'IBV_CQ_ATTR_MODERATE', - 2: 'IBV_CQ_ATTR_RESERVED', -} -IBV_CQ_ATTR_MODERATE = 1 -IBV_CQ_ATTR_RESERVED = 2 -ibv_cq_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_moderate_cq(Structure): - pass - -struct_ibv_moderate_cq._pack_ = 1 # source:False -struct_ibv_moderate_cq._fields_ = [ - ('cq_count', ctypes.c_uint16), - ('cq_period', ctypes.c_uint16), -] - -class struct_ibv_modify_cq_attr(Structure): - pass - -struct_ibv_modify_cq_attr._pack_ = 1 # source:False -struct_ibv_modify_cq_attr._fields_ = [ - ('attr_mask', ctypes.c_uint32), - ('moderate', struct_ibv_moderate_cq), -] - -try: - ibv_start_poll = _libraries['libibverbs'].ibv_start_poll - ibv_start_poll.restype = ctypes.c_int32 - ibv_start_poll.argtypes = [ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_poll_cq_attr)] -except AttributeError: - pass -try: - ibv_next_poll = _libraries['libibverbs'].ibv_next_poll - ibv_next_poll.restype = ctypes.c_int32 - ibv_next_poll.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_end_poll = _libraries['libibverbs'].ibv_end_poll - ibv_end_poll.restype = None - ibv_end_poll.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_opcode = _libraries['libibverbs'].ibv_wc_read_opcode - ibv_wc_read_opcode.restype = ibv_wc_opcode - ibv_wc_read_opcode.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_vendor_err = _libraries['libibverbs'].ibv_wc_read_vendor_err - ibv_wc_read_vendor_err.restype = uint32_t - ibv_wc_read_vendor_err.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_byte_len = _libraries['libibverbs'].ibv_wc_read_byte_len - ibv_wc_read_byte_len.restype = uint32_t - ibv_wc_read_byte_len.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_imm_data = _libraries['libibverbs'].ibv_wc_read_imm_data - ibv_wc_read_imm_data.restype = __be32 - ibv_wc_read_imm_data.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_invalidated_rkey = _libraries['libibverbs'].ibv_wc_read_invalidated_rkey - ibv_wc_read_invalidated_rkey.restype = uint32_t - ibv_wc_read_invalidated_rkey.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_qp_num = _libraries['libibverbs'].ibv_wc_read_qp_num - ibv_wc_read_qp_num.restype = uint32_t - ibv_wc_read_qp_num.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_src_qp = _libraries['libibverbs'].ibv_wc_read_src_qp - ibv_wc_read_src_qp.restype = uint32_t - ibv_wc_read_src_qp.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_wc_flags = _libraries['libibverbs'].ibv_wc_read_wc_flags - ibv_wc_read_wc_flags.restype = ctypes.c_uint32 - ibv_wc_read_wc_flags.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_slid = _libraries['libibverbs'].ibv_wc_read_slid - ibv_wc_read_slid.restype = uint32_t - ibv_wc_read_slid.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_sl = _libraries['libibverbs'].ibv_wc_read_sl - ibv_wc_read_sl.restype = uint8_t - ibv_wc_read_sl.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_dlid_path_bits = _libraries['libibverbs'].ibv_wc_read_dlid_path_bits - ibv_wc_read_dlid_path_bits.restype = uint8_t - ibv_wc_read_dlid_path_bits.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_completion_ts = _libraries['libibverbs'].ibv_wc_read_completion_ts - ibv_wc_read_completion_ts.restype = uint64_t - ibv_wc_read_completion_ts.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_completion_wallclock_ns = _libraries['libibverbs'].ibv_wc_read_completion_wallclock_ns - ibv_wc_read_completion_wallclock_ns.restype = uint64_t - ibv_wc_read_completion_wallclock_ns.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_cvlan = _libraries['libibverbs'].ibv_wc_read_cvlan - ibv_wc_read_cvlan.restype = uint16_t - ibv_wc_read_cvlan.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_flow_tag = _libraries['libibverbs'].ibv_wc_read_flow_tag - ibv_wc_read_flow_tag.restype = uint32_t - ibv_wc_read_flow_tag.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_tm_info = _libraries['libibverbs'].ibv_wc_read_tm_info - ibv_wc_read_tm_info.restype = None - ibv_wc_read_tm_info.argtypes = [ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_wc_tm_info)] -except AttributeError: - pass -try: - ibv_post_wq_recv = _libraries['libibverbs'].ibv_post_wq_recv - ibv_post_wq_recv.restype = ctypes.c_int32 - ibv_post_wq_recv.argtypes = [ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr))] -except AttributeError: - pass - -# values for enumeration 'ibv_flow_flags' -ibv_flow_flags__enumvalues = { - 2: 'IBV_FLOW_ATTR_FLAGS_DONT_TRAP', - 4: 'IBV_FLOW_ATTR_FLAGS_EGRESS', -} -IBV_FLOW_ATTR_FLAGS_DONT_TRAP = 2 -IBV_FLOW_ATTR_FLAGS_EGRESS = 4 -ibv_flow_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_flow_attr_type' -ibv_flow_attr_type__enumvalues = { - 0: 'IBV_FLOW_ATTR_NORMAL', - 1: 'IBV_FLOW_ATTR_ALL_DEFAULT', - 2: 'IBV_FLOW_ATTR_MC_DEFAULT', - 3: 'IBV_FLOW_ATTR_SNIFFER', -} -IBV_FLOW_ATTR_NORMAL = 0 -IBV_FLOW_ATTR_ALL_DEFAULT = 1 -IBV_FLOW_ATTR_MC_DEFAULT = 2 -IBV_FLOW_ATTR_SNIFFER = 3 -ibv_flow_attr_type = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_flow_spec_type' -ibv_flow_spec_type__enumvalues = { - 32: 'IBV_FLOW_SPEC_ETH', - 48: 'IBV_FLOW_SPEC_IPV4', - 49: 'IBV_FLOW_SPEC_IPV6', - 50: 'IBV_FLOW_SPEC_IPV4_EXT', - 52: 'IBV_FLOW_SPEC_ESP', - 64: 'IBV_FLOW_SPEC_TCP', - 65: 'IBV_FLOW_SPEC_UDP', - 80: 'IBV_FLOW_SPEC_VXLAN_TUNNEL', - 81: 'IBV_FLOW_SPEC_GRE', - 96: 'IBV_FLOW_SPEC_MPLS', - 256: 'IBV_FLOW_SPEC_INNER', - 4096: 'IBV_FLOW_SPEC_ACTION_TAG', - 4097: 'IBV_FLOW_SPEC_ACTION_DROP', - 4098: 'IBV_FLOW_SPEC_ACTION_HANDLE', - 4099: 'IBV_FLOW_SPEC_ACTION_COUNT', -} -IBV_FLOW_SPEC_ETH = 32 -IBV_FLOW_SPEC_IPV4 = 48 -IBV_FLOW_SPEC_IPV6 = 49 -IBV_FLOW_SPEC_IPV4_EXT = 50 -IBV_FLOW_SPEC_ESP = 52 -IBV_FLOW_SPEC_TCP = 64 -IBV_FLOW_SPEC_UDP = 65 -IBV_FLOW_SPEC_VXLAN_TUNNEL = 80 -IBV_FLOW_SPEC_GRE = 81 -IBV_FLOW_SPEC_MPLS = 96 -IBV_FLOW_SPEC_INNER = 256 -IBV_FLOW_SPEC_ACTION_TAG = 4096 -IBV_FLOW_SPEC_ACTION_DROP = 4097 -IBV_FLOW_SPEC_ACTION_HANDLE = 4098 -IBV_FLOW_SPEC_ACTION_COUNT = 4099 -ibv_flow_spec_type = ctypes.c_uint32 # enum -class struct_ibv_flow_eth_filter(Structure): - pass - -struct_ibv_flow_eth_filter._pack_ = 1 # source:False -struct_ibv_flow_eth_filter._fields_ = [ - ('dst_mac', ctypes.c_ubyte * 6), - ('src_mac', ctypes.c_ubyte * 6), - ('ether_type', ctypes.c_uint16), - ('vlan_tag', ctypes.c_uint16), -] - -class struct_ibv_flow_spec_eth(Structure): - pass - -struct_ibv_flow_spec_eth._pack_ = 1 # source:False -struct_ibv_flow_spec_eth._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('val', struct_ibv_flow_eth_filter), - ('mask', struct_ibv_flow_eth_filter), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_flow_ipv4_filter(Structure): - pass - -struct_ibv_flow_ipv4_filter._pack_ = 1 # source:False -struct_ibv_flow_ipv4_filter._fields_ = [ - ('src_ip', ctypes.c_uint32), - ('dst_ip', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_ipv4(Structure): - pass - -struct_ibv_flow_spec_ipv4._pack_ = 1 # source:False -struct_ibv_flow_spec_ipv4._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_ipv4_filter), - ('mask', struct_ibv_flow_ipv4_filter), -] - -class struct_ibv_flow_ipv4_ext_filter(Structure): - pass - -struct_ibv_flow_ipv4_ext_filter._pack_ = 1 # source:False -struct_ibv_flow_ipv4_ext_filter._fields_ = [ - ('src_ip', ctypes.c_uint32), - ('dst_ip', ctypes.c_uint32), - ('proto', ctypes.c_ubyte), - ('tos', ctypes.c_ubyte), - ('ttl', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -class struct_ibv_flow_spec_ipv4_ext(Structure): - pass - -struct_ibv_flow_spec_ipv4_ext._pack_ = 1 # source:False -struct_ibv_flow_spec_ipv4_ext._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_ipv4_ext_filter), - ('mask', struct_ibv_flow_ipv4_ext_filter), -] - -class struct_ibv_flow_ipv6_filter(Structure): - pass - -struct_ibv_flow_ipv6_filter._pack_ = 1 # source:False -struct_ibv_flow_ipv6_filter._fields_ = [ - ('src_ip', ctypes.c_ubyte * 16), - ('dst_ip', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('next_hdr', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -class struct_ibv_flow_spec_ipv6(Structure): - pass - -struct_ibv_flow_spec_ipv6._pack_ = 1 # source:False -struct_ibv_flow_spec_ipv6._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_ipv6_filter), - ('mask', struct_ibv_flow_ipv6_filter), -] - -class struct_ibv_flow_esp_filter(Structure): - pass - -struct_ibv_flow_esp_filter._pack_ = 1 # source:False -struct_ibv_flow_esp_filter._fields_ = [ - ('spi', ctypes.c_uint32), - ('seq', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_esp(Structure): - pass - -struct_ibv_flow_spec_esp._pack_ = 1 # source:False -struct_ibv_flow_spec_esp._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_esp_filter), - ('mask', struct_ibv_flow_esp_filter), -] - -class struct_ibv_flow_tcp_udp_filter(Structure): - pass - -struct_ibv_flow_tcp_udp_filter._pack_ = 1 # source:False -struct_ibv_flow_tcp_udp_filter._fields_ = [ - ('dst_port', ctypes.c_uint16), - ('src_port', ctypes.c_uint16), -] - -class struct_ibv_flow_spec_tcp_udp(Structure): - pass - -struct_ibv_flow_spec_tcp_udp._pack_ = 1 # source:False -struct_ibv_flow_spec_tcp_udp._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('val', struct_ibv_flow_tcp_udp_filter), - ('mask', struct_ibv_flow_tcp_udp_filter), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_flow_gre_filter(Structure): - pass - -struct_ibv_flow_gre_filter._pack_ = 1 # source:False -struct_ibv_flow_gre_filter._fields_ = [ - ('c_ks_res0_ver', ctypes.c_uint16), - ('protocol', ctypes.c_uint16), - ('key', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_gre(Structure): - pass - -struct_ibv_flow_spec_gre._pack_ = 1 # source:False -struct_ibv_flow_spec_gre._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_gre_filter), - ('mask', struct_ibv_flow_gre_filter), -] - -class struct_ibv_flow_mpls_filter(Structure): - pass - -struct_ibv_flow_mpls_filter._pack_ = 1 # source:False -struct_ibv_flow_mpls_filter._fields_ = [ - ('label', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_mpls(Structure): - pass - -struct_ibv_flow_spec_mpls._pack_ = 1 # source:False -struct_ibv_flow_spec_mpls._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_mpls_filter), - ('mask', struct_ibv_flow_mpls_filter), -] - -class struct_ibv_flow_tunnel_filter(Structure): - pass - -struct_ibv_flow_tunnel_filter._pack_ = 1 # source:False -struct_ibv_flow_tunnel_filter._fields_ = [ - ('tunnel_id', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_tunnel(Structure): - pass - -struct_ibv_flow_spec_tunnel._pack_ = 1 # source:False -struct_ibv_flow_spec_tunnel._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_tunnel_filter), - ('mask', struct_ibv_flow_tunnel_filter), -] - -class struct_ibv_flow_spec_action_tag(Structure): - pass - -struct_ibv_flow_spec_action_tag._pack_ = 1 # source:False -struct_ibv_flow_spec_action_tag._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('tag_id', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_action_drop(Structure): - pass - -struct_ibv_flow_spec_action_drop._pack_ = 1 # source:False -struct_ibv_flow_spec_action_drop._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_flow_spec_action_handle(Structure): - pass - -class struct_ibv_flow_action(Structure): - pass - -struct_ibv_flow_spec_action_handle._pack_ = 1 # source:False -struct_ibv_flow_spec_action_handle._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('action', ctypes.POINTER(struct_ibv_flow_action)), -] - -struct_ibv_flow_action._pack_ = 1 # source:False -struct_ibv_flow_action._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - -class struct_ibv_flow_spec_counter_action(Structure): - pass - -class struct_ibv_counters(Structure): - pass - -struct_ibv_flow_spec_counter_action._pack_ = 1 # source:False -struct_ibv_flow_spec_counter_action._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('counters', ctypes.POINTER(struct_ibv_counters)), -] - -struct_ibv_counters._pack_ = 1 # source:False -struct_ibv_counters._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - -class struct_ibv_flow_spec(Structure): - pass - -class union_ibv_flow_spec_0(Union): - pass - -class struct_ibv_flow_spec_0_hdr(Structure): - pass - -struct_ibv_flow_spec_0_hdr._pack_ = 1 # source:False -struct_ibv_flow_spec_0_hdr._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -union_ibv_flow_spec_0._pack_ = 1 # source:False -union_ibv_flow_spec_0._fields_ = [ - ('hdr', struct_ibv_flow_spec_0_hdr), - ('eth', struct_ibv_flow_spec_eth), - ('ipv4', struct_ibv_flow_spec_ipv4), - ('tcp_udp', struct_ibv_flow_spec_tcp_udp), - ('ipv4_ext', struct_ibv_flow_spec_ipv4_ext), - ('ipv6', struct_ibv_flow_spec_ipv6), - ('esp', struct_ibv_flow_spec_esp), - ('tunnel', struct_ibv_flow_spec_tunnel), - ('gre', struct_ibv_flow_spec_gre), - ('mpls', struct_ibv_flow_spec_mpls), - ('flow_tag', struct_ibv_flow_spec_action_tag), - ('drop', struct_ibv_flow_spec_action_drop), - ('handle', struct_ibv_flow_spec_action_handle), - ('flow_count', struct_ibv_flow_spec_counter_action), - ('PADDING_0', ctypes.c_ubyte * 72), -] - -struct_ibv_flow_spec._pack_ = 1 # source:False -struct_ibv_flow_spec._anonymous_ = ('_0',) -struct_ibv_flow_spec._fields_ = [ - ('_0', union_ibv_flow_spec_0), -] - -class struct_ibv_flow_attr(Structure): - pass - -struct_ibv_flow_attr._pack_ = 1 # source:False -struct_ibv_flow_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('type', ibv_flow_attr_type), - ('size', ctypes.c_uint16), - ('priority', ctypes.c_uint16), - ('num_of_specs', ctypes.c_ubyte), - ('port', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('flags', ctypes.c_uint32), -] - -class struct_ibv_flow(Structure): - pass - -struct_ibv_flow._pack_ = 1 # source:False -struct_ibv_flow._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('context', ctypes.POINTER(struct_ibv_context)), - ('handle', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_flow_action_esp_mask' -ibv_flow_action_esp_mask__enumvalues = { - 1: 'IBV_FLOW_ACTION_ESP_MASK_ESN', -} -IBV_FLOW_ACTION_ESP_MASK_ESN = 1 -ibv_flow_action_esp_mask = ctypes.c_uint32 # enum -class struct_ibv_flow_action_esp_attr(Structure): - pass - -struct_ibv_flow_action_esp_attr._pack_ = 1 # source:False -struct_ibv_flow_action_esp_attr._fields_ = [ - ('esp_attr', ctypes.POINTER(struct_ib_uverbs_flow_action_esp)), - ('keymat_proto', ib_uverbs_flow_action_esp_keymat), - ('keymat_len', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('keymat_ptr', ctypes.POINTER(None)), - ('replay_proto', ib_uverbs_flow_action_esp_replay), - ('replay_len', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('replay_ptr', ctypes.POINTER(None)), - ('esp_encap', ctypes.POINTER(struct_ib_uverbs_flow_action_esp_encap)), - ('comp_mask', ctypes.c_uint32), - ('esn', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_IBV_SYSFS_NAME_MAX' -c__Ea_IBV_SYSFS_NAME_MAX__enumvalues = { - 64: 'IBV_SYSFS_NAME_MAX', - 256: 'IBV_SYSFS_PATH_MAX', -} -IBV_SYSFS_NAME_MAX = 64 -IBV_SYSFS_PATH_MAX = 256 -c__Ea_IBV_SYSFS_NAME_MAX = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_cq_init_attr_mask' -ibv_cq_init_attr_mask__enumvalues = { - 1: 'IBV_CQ_INIT_ATTR_MASK_FLAGS', - 2: 'IBV_CQ_INIT_ATTR_MASK_PD', -} -IBV_CQ_INIT_ATTR_MASK_FLAGS = 1 -IBV_CQ_INIT_ATTR_MASK_PD = 2 -ibv_cq_init_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_create_cq_attr_flags' -ibv_create_cq_attr_flags__enumvalues = { - 1: 'IBV_CREATE_CQ_ATTR_SINGLE_THREADED', - 2: 'IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN', -} -IBV_CREATE_CQ_ATTR_SINGLE_THREADED = 1 -IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN = 2 -ibv_create_cq_attr_flags = ctypes.c_uint32 # enum -class struct_ibv_cq_init_attr_ex(Structure): - pass - -struct_ibv_cq_init_attr_ex._pack_ = 1 # source:False -struct_ibv_cq_init_attr_ex._fields_ = [ - ('cqe', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('cq_context', ctypes.POINTER(None)), - ('channel', ctypes.POINTER(struct_ibv_comp_channel)), - ('comp_vector', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('wc_flags', ctypes.c_uint64), - ('comp_mask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('parent_domain', ctypes.POINTER(struct_ibv_pd)), -] - - -# values for enumeration 'ibv_parent_domain_init_attr_mask' -ibv_parent_domain_init_attr_mask__enumvalues = { - 1: 'IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS', - 2: 'IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT', -} -IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS = 1 -IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT = 2 -ibv_parent_domain_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_parent_domain_init_attr(Structure): - pass - -struct_ibv_parent_domain_init_attr._pack_ = 1 # source:False -struct_ibv_parent_domain_init_attr._fields_ = [ - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('td', ctypes.POINTER(struct_ibv_td)), - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('alloc', ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64)), - ('free', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint64)), - ('pd_context', ctypes.POINTER(None)), -] - -class struct_ibv_counters_init_attr(Structure): - pass - -struct_ibv_counters_init_attr._pack_ = 1 # source:False -struct_ibv_counters_init_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_counter_description' -ibv_counter_description__enumvalues = { - 0: 'IBV_COUNTER_PACKETS', - 1: 'IBV_COUNTER_BYTES', -} -IBV_COUNTER_PACKETS = 0 -IBV_COUNTER_BYTES = 1 -ibv_counter_description = ctypes.c_uint32 # enum -class struct_ibv_counter_attach_attr(Structure): - pass - -struct_ibv_counter_attach_attr._pack_ = 1 # source:False -struct_ibv_counter_attach_attr._fields_ = [ - ('counter_desc', ibv_counter_description), - ('index', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_read_counters_flags' -ibv_read_counters_flags__enumvalues = { - 1: 'IBV_READ_COUNTERS_ATTR_PREFER_CACHED', -} -IBV_READ_COUNTERS_ATTR_PREFER_CACHED = 1 -ibv_read_counters_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_values_mask' -ibv_values_mask__enumvalues = { - 1: 'IBV_VALUES_MASK_RAW_CLOCK', - 2: 'IBV_VALUES_MASK_RESERVED', -} -IBV_VALUES_MASK_RAW_CLOCK = 1 -IBV_VALUES_MASK_RESERVED = 2 -ibv_values_mask = ctypes.c_uint32 # enum -class struct_ibv_values_ex(Structure): - pass - -class struct_timespec(Structure): - pass - -struct_timespec._pack_ = 1 # source:False -struct_timespec._fields_ = [ - ('tv_sec', ctypes.c_int64), - ('tv_nsec', ctypes.c_int64), -] - -struct_ibv_values_ex._pack_ = 1 # source:False -struct_ibv_values_ex._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('raw_clock', struct_timespec), -] - -class struct_verbs_context(Structure): - pass - -class struct_verbs_ex_private(Structure): - pass - -struct_verbs_context._pack_ = 1 # source:False -struct_verbs_context._fields_ = [ - ('query_port', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.c_ubyte, ctypes.POINTER(struct_ibv_port_attr), ctypes.c_uint64)), - ('advise_mr', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_pd), ib_uverbs_advise_mr_advice, ctypes.c_uint32, ctypes.POINTER(struct_ibv_sge), ctypes.c_uint32)), - ('alloc_null_mr', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mr), ctypes.POINTER(struct_ibv_pd))), - ('read_counters', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32, ctypes.c_uint32)), - ('attach_counters_point_flow', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_counter_attach_attr), ctypes.POINTER(struct_ibv_flow))), - ('create_counters', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_counters_init_attr))), - ('destroy_counters', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters))), - ('reg_dm_mr', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mr), ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_dm), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint32)), - ('alloc_dm', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_dm), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_alloc_dm_attr))), - ('free_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_dm))), - ('modify_flow_action_esp', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_flow_action_esp_attr))), - ('destroy_flow_action', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow_action))), - ('create_flow_action_esp', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_flow_action_esp_attr))), - ('modify_qp_rate_limit', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_rate_limit_attr))), - ('alloc_parent_domain', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_parent_domain_init_attr))), - ('dealloc_td', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_td))), - ('alloc_td', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_td), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_td_init_attr))), - ('modify_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.POINTER(struct_ibv_modify_cq_attr))), - ('post_srq_ops', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_ops_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_ops_wr)))), - ('destroy_rwq_ind_table', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_rwq_ind_table))), - ('create_rwq_ind_table', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_rwq_ind_table), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_rwq_ind_table_init_attr))), - ('destroy_wq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq))), - ('modify_wq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_wq_attr))), - ('create_wq', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_wq_init_attr))), - ('query_rt_values', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_values_ex))), - ('create_cq_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_cq_init_attr_ex))), - ('priv', ctypes.POINTER(struct_verbs_ex_private)), - ('query_device_ex', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_query_device_ex_input), ctypes.POINTER(struct_ibv_device_attr_ex), ctypes.c_uint64)), - ('ibv_destroy_flow', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow))), - ('ABI_placeholder2', ctypes.CFUNCTYPE(None)), - ('ibv_create_flow', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_flow), ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_flow_attr))), - ('ABI_placeholder1', ctypes.CFUNCTYPE(None)), - ('open_qp', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_open_attr))), - ('create_qp_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_init_attr_ex))), - ('get_srq_num', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(ctypes.c_uint32))), - ('create_srq_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_srq_init_attr_ex))), - ('open_xrcd', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_xrcd), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_xrcd_init_attr))), - ('close_xrcd', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_xrcd))), - ('_ABI_placeholder3', ctypes.c_uint64), - ('sz', ctypes.c_uint64), - ('context', struct_ibv_context), -] - -try: - verbs_get_ctx = _libraries['libibverbs'].verbs_get_ctx - verbs_get_ctx.restype = ctypes.POINTER(struct_verbs_context) - verbs_get_ctx.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -# def verbs_get_ctx_op(ctx, op): # macro -# return ({struct_verbs_context*__vctx=verbs_get_ctx(ctx);(!__vctx or (__vctx->szop)?NULL:__vctx;}) -try: - ibv_get_device_list = _libraries['libibverbs'].ibv_get_device_list - ibv_get_device_list.restype = ctypes.POINTER(ctypes.POINTER(struct_ibv_device)) - ibv_get_device_list.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - ibv_free_device_list = _libraries['libibverbs'].ibv_free_device_list - ibv_free_device_list.restype = None - ibv_free_device_list.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ibv_device))] -except AttributeError: - pass -try: - ibv_get_device_name = _libraries['libibverbs'].ibv_get_device_name - ibv_get_device_name.restype = ctypes.POINTER(ctypes.c_char) - ibv_get_device_name.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -try: - ibv_get_device_index = _libraries['libibverbs'].ibv_get_device_index - ibv_get_device_index.restype = ctypes.c_int32 - ibv_get_device_index.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +def dll(): + try: return ctypes.CDLL(unwrap(ibverbs), use_errno=True) + except: pass + return None +dll = dll() + +class union_ibv_gid(ctypes.Union): pass +uint8_t = ctypes.c_ubyte +class union_ibv_gid_global(Struct): pass __be64 = ctypes.c_uint64 -try: - ibv_get_device_guid = _libraries['libibverbs'].ibv_get_device_guid - ibv_get_device_guid.restype = __be64 - ibv_get_device_guid.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -try: - ibv_open_device = _libraries['libibverbs'].ibv_open_device - ibv_open_device.restype = ctypes.POINTER(struct_ibv_context) - ibv_open_device.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -try: - ibv_close_device = _libraries['libibverbs'].ibv_close_device - ibv_close_device.restype = ctypes.c_int32 - ibv_close_device.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -try: - ibv_import_device = _libraries['libibverbs'].ibv_import_device - ibv_import_device.restype = ctypes.POINTER(struct_ibv_context) - ibv_import_device.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - ibv_import_pd = _libraries['libibverbs'].ibv_import_pd - ibv_import_pd.restype = ctypes.POINTER(struct_ibv_pd) - ibv_import_pd.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t] -except AttributeError: - pass -try: - ibv_unimport_pd = _libraries['libibverbs'].ibv_unimport_pd - ibv_unimport_pd.restype = None - ibv_unimport_pd.argtypes = [ctypes.POINTER(struct_ibv_pd)] -except AttributeError: - pass -try: - ibv_import_mr = _libraries['libibverbs'].ibv_import_mr - ibv_import_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_import_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), uint32_t] -except AttributeError: - pass -try: - ibv_unimport_mr = _libraries['libibverbs'].ibv_unimport_mr - ibv_unimport_mr.restype = None - ibv_unimport_mr.argtypes = [ctypes.POINTER(struct_ibv_mr)] -except AttributeError: - pass -try: - ibv_import_dm = _libraries['libibverbs'].ibv_import_dm - ibv_import_dm.restype = ctypes.POINTER(struct_ibv_dm) - ibv_import_dm.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t] -except AttributeError: - pass -try: - ibv_unimport_dm = _libraries['libibverbs'].ibv_unimport_dm - ibv_unimport_dm.restype = None - ibv_unimport_dm.argtypes = [ctypes.POINTER(struct_ibv_dm)] -except AttributeError: - pass -try: - ibv_get_async_event = _libraries['libibverbs'].ibv_get_async_event - ibv_get_async_event.restype = ctypes.c_int32 - ibv_get_async_event.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_async_event)] -except AttributeError: - pass -try: - ibv_ack_async_event = _libraries['libibverbs'].ibv_ack_async_event - ibv_ack_async_event.restype = None - ibv_ack_async_event.argtypes = [ctypes.POINTER(struct_ibv_async_event)] -except AttributeError: - pass -try: - ibv_query_device = _libraries['libibverbs'].ibv_query_device - ibv_query_device.restype = ctypes.c_int32 - ibv_query_device.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device_attr)] -except AttributeError: - pass -try: - ___ibv_query_port = _libraries['libibverbs'].___ibv_query_port - ___ibv_query_port.restype = ctypes.c_int32 - ___ibv_query_port.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct_ibv_port_attr)] -except AttributeError: - pass -def ibv_query_port(context, port_num, port_attr): # macro - return ___ibv_query_port(context,port_num,port_attr) -try: - ibv_query_gid = _libraries['libibverbs'].ibv_query_gid - ibv_query_gid.restype = ctypes.c_int32 - ibv_query_gid.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_int32, ctypes.POINTER(union_ibv_gid)] -except AttributeError: - pass -try: - _ibv_query_gid_ex = _libraries['libibverbs']._ibv_query_gid_ex - _ibv_query_gid_ex.restype = ctypes.c_int32 - _ibv_query_gid_ex.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t, uint32_t, ctypes.POINTER(struct_ibv_gid_entry), uint32_t, size_t] -except AttributeError: - pass -try: - ibv_query_gid_ex = _libraries['libibverbs'].ibv_query_gid_ex - ibv_query_gid_ex.restype = ctypes.c_int32 - ibv_query_gid_ex.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t, uint32_t, ctypes.POINTER(struct_ibv_gid_entry), uint32_t] -except AttributeError: - pass -ssize_t = ctypes.c_int64 -try: - _ibv_query_gid_table = _libraries['libibverbs']._ibv_query_gid_table - _ibv_query_gid_table.restype = ssize_t - _ibv_query_gid_table.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_gid_entry), size_t, uint32_t, size_t] -except AttributeError: - pass -try: - ibv_query_gid_table = _libraries['libibverbs'].ibv_query_gid_table - ibv_query_gid_table.restype = ssize_t - ibv_query_gid_table.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_gid_entry), size_t, uint32_t] -except AttributeError: - pass -try: - ibv_query_pkey = _libraries['libibverbs'].ibv_query_pkey - ibv_query_pkey.restype = ctypes.c_int32 - ibv_query_pkey.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -__be16 = ctypes.c_uint16 -try: - ibv_get_pkey_index = _libraries['libibverbs'].ibv_get_pkey_index - ibv_get_pkey_index.restype = ctypes.c_int32 - ibv_get_pkey_index.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, __be16] -except AttributeError: - pass -try: - ibv_alloc_pd = _libraries['libibverbs'].ibv_alloc_pd - ibv_alloc_pd.restype = ctypes.POINTER(struct_ibv_pd) - ibv_alloc_pd.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -try: - ibv_dealloc_pd = _libraries['libibverbs'].ibv_dealloc_pd - ibv_dealloc_pd.restype = ctypes.c_int32 - ibv_dealloc_pd.argtypes = [ctypes.POINTER(struct_ibv_pd)] -except AttributeError: - pass -try: - ibv_create_flow = _libraries['libibverbs'].ibv_create_flow - ibv_create_flow.restype = ctypes.POINTER(struct_ibv_flow) - ibv_create_flow.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_flow_attr)] -except AttributeError: - pass -try: - ibv_destroy_flow = _libraries['libibverbs'].ibv_destroy_flow - ibv_destroy_flow.restype = ctypes.c_int32 - ibv_destroy_flow.argtypes = [ctypes.POINTER(struct_ibv_flow)] -except AttributeError: - pass -try: - ibv_create_flow_action_esp = _libraries['libibverbs'].ibv_create_flow_action_esp - ibv_create_flow_action_esp.restype = ctypes.POINTER(struct_ibv_flow_action) - ibv_create_flow_action_esp.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_flow_action_esp_attr)] -except AttributeError: - pass -try: - ibv_modify_flow_action_esp = _libraries['libibverbs'].ibv_modify_flow_action_esp - ibv_modify_flow_action_esp.restype = ctypes.c_int32 - ibv_modify_flow_action_esp.argtypes = [ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_flow_action_esp_attr)] -except AttributeError: - pass -try: - ibv_destroy_flow_action = _libraries['libibverbs'].ibv_destroy_flow_action - ibv_destroy_flow_action.restype = ctypes.c_int32 - ibv_destroy_flow_action.argtypes = [ctypes.POINTER(struct_ibv_flow_action)] -except AttributeError: - pass -try: - ibv_open_xrcd = _libraries['libibverbs'].ibv_open_xrcd - ibv_open_xrcd.restype = ctypes.POINTER(struct_ibv_xrcd) - ibv_open_xrcd.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_xrcd_init_attr)] -except AttributeError: - pass -try: - ibv_close_xrcd = _libraries['libibverbs'].ibv_close_xrcd - ibv_close_xrcd.restype = ctypes.c_int32 - ibv_close_xrcd.argtypes = [ctypes.POINTER(struct_ibv_xrcd)] -except AttributeError: - pass -try: - ibv_reg_mr_iova2 = _libraries['libibverbs'].ibv_reg_mr_iova2 - ibv_reg_mr_iova2.restype = ctypes.POINTER(struct_ibv_mr) - ibv_reg_mr_iova2.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - __ibv_reg_mr = _libraries['libibverbs'].__ibv_reg_mr - __ibv_reg_mr.restype = ctypes.POINTER(struct_ibv_mr) - __ibv_reg_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -# def ibv_reg_mr(pd, addr, length, access): # macro -# return __ibv_reg_mr(pd,addr,length,access,__builtin_constant_p(((access)&IB_UVERBS_ACCESS_OPTIONAL_RANGE)==0)) -try: - __ibv_reg_mr_iova = _libraries['libibverbs'].__ibv_reg_mr_iova - __ibv_reg_mr_iova.restype = ctypes.POINTER(struct_ibv_mr) - __ibv_reg_mr_iova.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, uint64_t, ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -# def ibv_reg_mr_iova(pd, addr, length, iova, access): # macro -# return __ibv_reg_mr_iova(pd,addr,length,iova,access,__builtin_constant_p(((access)&IB_UVERBS_ACCESS_OPTIONAL_RANGE)==0)) -try: - ibv_reg_dmabuf_mr = _libraries['libibverbs'].ibv_reg_dmabuf_mr - ibv_reg_dmabuf_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_reg_dmabuf_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), uint64_t, size_t, uint64_t, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass +union_ibv_gid_global._fields_ = [ + ('subnet_prefix', ctypes.c_uint64), + ('interface_id', ctypes.c_uint64), +] +union_ibv_gid._fields_ = [ + ('raw', (uint8_t * 16)), + ('global', union_ibv_gid_global), +] +enum_ibv_gid_type = CEnum(ctypes.c_uint32) +IBV_GID_TYPE_IB = enum_ibv_gid_type.define('IBV_GID_TYPE_IB', 0) +IBV_GID_TYPE_ROCE_V1 = enum_ibv_gid_type.define('IBV_GID_TYPE_ROCE_V1', 1) +IBV_GID_TYPE_ROCE_V2 = enum_ibv_gid_type.define('IBV_GID_TYPE_ROCE_V2', 2) -# values for enumeration 'ibv_rereg_mr_err_code' -ibv_rereg_mr_err_code__enumvalues = { - -1: 'IBV_REREG_MR_ERR_INPUT', - -2: 'IBV_REREG_MR_ERR_DONT_FORK_NEW', - -3: 'IBV_REREG_MR_ERR_DO_FORK_OLD', - -4: 'IBV_REREG_MR_ERR_CMD', - -5: 'IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW', -} -IBV_REREG_MR_ERR_INPUT = -1 -IBV_REREG_MR_ERR_DONT_FORK_NEW = -2 -IBV_REREG_MR_ERR_DO_FORK_OLD = -3 -IBV_REREG_MR_ERR_CMD = -4 -IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW = -5 -ibv_rereg_mr_err_code = ctypes.c_int32 # enum -try: - ibv_rereg_mr = _libraries['libibverbs'].ibv_rereg_mr - ibv_rereg_mr.restype = ctypes.c_int32 - ibv_rereg_mr.argtypes = [ctypes.POINTER(struct_ibv_mr), ctypes.c_int32, ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - ibv_dereg_mr = _libraries['libibverbs'].ibv_dereg_mr - ibv_dereg_mr.restype = ctypes.c_int32 - ibv_dereg_mr.argtypes = [ctypes.POINTER(struct_ibv_mr)] -except AttributeError: - pass -try: - ibv_alloc_mw = _libraries['libibverbs'].ibv_alloc_mw - ibv_alloc_mw.restype = ctypes.POINTER(struct_ibv_mw) - ibv_alloc_mw.argtypes = [ctypes.POINTER(struct_ibv_pd), ibv_mw_type] -except AttributeError: - pass -try: - ibv_dealloc_mw = _libraries['libibverbs'].ibv_dealloc_mw - ibv_dealloc_mw.restype = ctypes.c_int32 - ibv_dealloc_mw.argtypes = [ctypes.POINTER(struct_ibv_mw)] -except AttributeError: - pass -try: - ibv_inc_rkey = _libraries['libibverbs'].ibv_inc_rkey - ibv_inc_rkey.restype = uint32_t - ibv_inc_rkey.argtypes = [uint32_t] -except AttributeError: - pass -try: - ibv_bind_mw = _libraries['libibverbs'].ibv_bind_mw - ibv_bind_mw.restype = ctypes.c_int32 - ibv_bind_mw.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_mw_bind)] -except AttributeError: - pass -try: - ibv_create_comp_channel = _libraries['libibverbs'].ibv_create_comp_channel - ibv_create_comp_channel.restype = ctypes.POINTER(struct_ibv_comp_channel) - ibv_create_comp_channel.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -try: - ibv_destroy_comp_channel = _libraries['libibverbs'].ibv_destroy_comp_channel - ibv_destroy_comp_channel.restype = ctypes.c_int32 - ibv_destroy_comp_channel.argtypes = [ctypes.POINTER(struct_ibv_comp_channel)] -except AttributeError: - pass -try: - ibv_advise_mr = _libraries['libibverbs'].ibv_advise_mr - ibv_advise_mr.restype = ctypes.c_int32 - ibv_advise_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), ib_uverbs_advise_mr_advice, uint32_t, ctypes.POINTER(struct_ibv_sge), uint32_t] -except AttributeError: - pass -try: - ibv_alloc_dm = _libraries['libibverbs'].ibv_alloc_dm - ibv_alloc_dm.restype = ctypes.POINTER(struct_ibv_dm) - ibv_alloc_dm.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_alloc_dm_attr)] -except AttributeError: - pass -try: - ibv_free_dm = _libraries['libibverbs'].ibv_free_dm - ibv_free_dm.restype = ctypes.c_int32 - ibv_free_dm.argtypes = [ctypes.POINTER(struct_ibv_dm)] -except AttributeError: - pass -try: - ibv_memcpy_to_dm = _libraries['libibverbs'].ibv_memcpy_to_dm - ibv_memcpy_to_dm.restype = ctypes.c_int32 - ibv_memcpy_to_dm.argtypes = [ctypes.POINTER(struct_ibv_dm), uint64_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - ibv_memcpy_from_dm = _libraries['libibverbs'].ibv_memcpy_from_dm - ibv_memcpy_from_dm.restype = ctypes.c_int32 - ibv_memcpy_from_dm.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_ibv_dm), uint64_t, size_t] -except AttributeError: - pass -try: - ibv_alloc_null_mr = _libraries['libibverbs'].ibv_alloc_null_mr - ibv_alloc_null_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_alloc_null_mr.argtypes = [ctypes.POINTER(struct_ibv_pd)] -except AttributeError: - pass -try: - ibv_reg_dm_mr = _libraries['libibverbs'].ibv_reg_dm_mr - ibv_reg_dm_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_reg_dm_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_dm), uint64_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - ibv_create_cq = _libraries['libibverbs'].ibv_create_cq - ibv_create_cq.restype = ctypes.POINTER(struct_ibv_cq) - ibv_create_cq.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(struct_ibv_comp_channel), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_create_cq_ex = _libraries['libibverbs'].ibv_create_cq_ex - ibv_create_cq_ex.restype = ctypes.POINTER(struct_ibv_cq_ex) - ibv_create_cq_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_cq_init_attr_ex)] -except AttributeError: - pass -try: - ibv_resize_cq = _libraries['libibverbs'].ibv_resize_cq - ibv_resize_cq.restype = ctypes.c_int32 - ibv_resize_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_destroy_cq = _libraries['libibverbs'].ibv_destroy_cq - ibv_destroy_cq.restype = ctypes.c_int32 - ibv_destroy_cq.argtypes = [ctypes.POINTER(struct_ibv_cq)] -except AttributeError: - pass -try: - ibv_get_cq_event = _libraries['libibverbs'].ibv_get_cq_event - ibv_get_cq_event.restype = ctypes.c_int32 - ibv_get_cq_event.argtypes = [ctypes.POINTER(struct_ibv_comp_channel), ctypes.POINTER(ctypes.POINTER(struct_ibv_cq)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - ibv_ack_cq_events = _libraries['libibverbs'].ibv_ack_cq_events - ibv_ack_cq_events.restype = None - ibv_ack_cq_events.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_uint32] -except AttributeError: - pass -try: - ibv_poll_cq = _libraries['libibverbs'].ibv_poll_cq - ibv_poll_cq.restype = ctypes.c_int32 - ibv_poll_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32, ctypes.POINTER(struct_ibv_wc)] -except AttributeError: - pass -try: - ibv_req_notify_cq = _libraries['libibverbs'].ibv_req_notify_cq - ibv_req_notify_cq.restype = ctypes.c_int32 - ibv_req_notify_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_modify_cq = _libraries['libibverbs'].ibv_modify_cq - ibv_modify_cq.restype = ctypes.c_int32 - ibv_modify_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.POINTER(struct_ibv_modify_cq_attr)] -except AttributeError: - pass -try: - ibv_create_srq = _libraries['libibverbs'].ibv_create_srq - ibv_create_srq.restype = ctypes.POINTER(struct_ibv_srq) - ibv_create_srq.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_srq_init_attr)] -except AttributeError: - pass -try: - ibv_create_srq_ex = _libraries['libibverbs'].ibv_create_srq_ex - ibv_create_srq_ex.restype = ctypes.POINTER(struct_ibv_srq) - ibv_create_srq_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_srq_init_attr_ex)] -except AttributeError: - pass -try: - ibv_modify_srq = _libraries['libibverbs'].ibv_modify_srq - ibv_modify_srq.restype = ctypes.c_int32 - ibv_modify_srq.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_srq_attr), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_query_srq = _libraries['libibverbs'].ibv_query_srq - ibv_query_srq.restype = ctypes.c_int32 - ibv_query_srq.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_srq_attr)] -except AttributeError: - pass -try: - ibv_get_srq_num = _libraries['libibverbs'].ibv_get_srq_num - ibv_get_srq_num.restype = ctypes.c_int32 - ibv_get_srq_num.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - ibv_destroy_srq = _libraries['libibverbs'].ibv_destroy_srq - ibv_destroy_srq.restype = ctypes.c_int32 - ibv_destroy_srq.argtypes = [ctypes.POINTER(struct_ibv_srq)] -except AttributeError: - pass -try: - ibv_post_srq_recv = _libraries['libibverbs'].ibv_post_srq_recv - ibv_post_srq_recv.restype = ctypes.c_int32 - ibv_post_srq_recv.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr))] -except AttributeError: - pass -try: - ibv_post_srq_ops = _libraries['libibverbs'].ibv_post_srq_ops - ibv_post_srq_ops.restype = ctypes.c_int32 - ibv_post_srq_ops.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_ops_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_ops_wr))] -except AttributeError: - pass -try: - ibv_create_qp = _libraries['libibverbs'].ibv_create_qp - ibv_create_qp.restype = ctypes.POINTER(struct_ibv_qp) - ibv_create_qp.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_qp_init_attr)] -except AttributeError: - pass -try: - ibv_create_qp_ex = _libraries['libibverbs'].ibv_create_qp_ex - ibv_create_qp_ex.restype = ctypes.POINTER(struct_ibv_qp) - ibv_create_qp_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_init_attr_ex)] -except AttributeError: - pass -try: - ibv_alloc_td = _libraries['libibverbs'].ibv_alloc_td - ibv_alloc_td.restype = ctypes.POINTER(struct_ibv_td) - ibv_alloc_td.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_td_init_attr)] -except AttributeError: - pass -try: - ibv_dealloc_td = _libraries['libibverbs'].ibv_dealloc_td - ibv_dealloc_td.restype = ctypes.c_int32 - ibv_dealloc_td.argtypes = [ctypes.POINTER(struct_ibv_td)] -except AttributeError: - pass -try: - ibv_alloc_parent_domain = _libraries['libibverbs'].ibv_alloc_parent_domain - ibv_alloc_parent_domain.restype = ctypes.POINTER(struct_ibv_pd) - ibv_alloc_parent_domain.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_parent_domain_init_attr)] -except AttributeError: - pass -try: - ibv_query_rt_values_ex = _libraries['libibverbs'].ibv_query_rt_values_ex - ibv_query_rt_values_ex.restype = ctypes.c_int32 - ibv_query_rt_values_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_values_ex)] -except AttributeError: - pass -try: - ibv_query_device_ex = _libraries['libibverbs'].ibv_query_device_ex - ibv_query_device_ex.restype = ctypes.c_int32 - ibv_query_device_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_query_device_ex_input), ctypes.POINTER(struct_ibv_device_attr_ex)] -except AttributeError: - pass -try: - ibv_open_qp = _libraries['libibverbs'].ibv_open_qp - ibv_open_qp.restype = ctypes.POINTER(struct_ibv_qp) - ibv_open_qp.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_open_attr)] -except AttributeError: - pass -try: - ibv_modify_qp = _libraries['libibverbs'].ibv_modify_qp - ibv_modify_qp.restype = ctypes.c_int32 - ibv_modify_qp.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_attr), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_modify_qp_rate_limit = _libraries['libibverbs'].ibv_modify_qp_rate_limit - ibv_modify_qp_rate_limit.restype = ctypes.c_int32 - ibv_modify_qp_rate_limit.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_rate_limit_attr)] -except AttributeError: - pass -try: - ibv_query_qp_data_in_order = _libraries['libibverbs'].ibv_query_qp_data_in_order - ibv_query_qp_data_in_order.restype = ctypes.c_int32 - ibv_query_qp_data_in_order.argtypes = [ctypes.POINTER(struct_ibv_qp), ibv_wr_opcode, uint32_t] -except AttributeError: - pass -try: - ibv_query_qp = _libraries['libibverbs'].ibv_query_qp - ibv_query_qp.restype = ctypes.c_int32 - ibv_query_qp.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_attr), ctypes.c_int32, ctypes.POINTER(struct_ibv_qp_init_attr)] -except AttributeError: - pass -try: - ibv_destroy_qp = _libraries['libibverbs'].ibv_destroy_qp - ibv_destroy_qp.restype = ctypes.c_int32 - ibv_destroy_qp.argtypes = [ctypes.POINTER(struct_ibv_qp)] -except AttributeError: - pass -try: - ibv_create_wq = _libraries['libibverbs'].ibv_create_wq - ibv_create_wq.restype = ctypes.POINTER(struct_ibv_wq) - ibv_create_wq.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_wq_init_attr)] -except AttributeError: - pass -try: - ibv_modify_wq = _libraries['libibverbs'].ibv_modify_wq - ibv_modify_wq.restype = ctypes.c_int32 - ibv_modify_wq.argtypes = [ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_wq_attr)] -except AttributeError: - pass -try: - ibv_destroy_wq = _libraries['libibverbs'].ibv_destroy_wq - ibv_destroy_wq.restype = ctypes.c_int32 - ibv_destroy_wq.argtypes = [ctypes.POINTER(struct_ibv_wq)] -except AttributeError: - pass -try: - ibv_create_rwq_ind_table = _libraries['libibverbs'].ibv_create_rwq_ind_table - ibv_create_rwq_ind_table.restype = ctypes.POINTER(struct_ibv_rwq_ind_table) - ibv_create_rwq_ind_table.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_rwq_ind_table_init_attr)] -except AttributeError: - pass -try: - ibv_destroy_rwq_ind_table = _libraries['libibverbs'].ibv_destroy_rwq_ind_table - ibv_destroy_rwq_ind_table.restype = ctypes.c_int32 - ibv_destroy_rwq_ind_table.argtypes = [ctypes.POINTER(struct_ibv_rwq_ind_table)] -except AttributeError: - pass -try: - ibv_post_send = _libraries['libibverbs'].ibv_post_send - ibv_post_send.restype = ctypes.c_int32 - ibv_post_send.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_send_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_send_wr))] -except AttributeError: - pass -try: - ibv_post_recv = _libraries['libibverbs'].ibv_post_recv - ibv_post_recv.restype = ctypes.c_int32 - ibv_post_recv.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr))] -except AttributeError: - pass -try: - ibv_create_ah = _libraries['libibverbs'].ibv_create_ah - ibv_create_ah.restype = ctypes.POINTER(struct_ibv_ah) - ibv_create_ah.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_ah_attr)] -except AttributeError: - pass -try: - ibv_init_ah_from_wc = _libraries['libibverbs'].ibv_init_ah_from_wc - ibv_init_ah_from_wc.restype = ctypes.c_int32 - ibv_init_ah_from_wc.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct_ibv_wc), ctypes.POINTER(struct_ibv_grh), ctypes.POINTER(struct_ibv_ah_attr)] -except AttributeError: - pass -try: - ibv_create_ah_from_wc = _libraries['libibverbs'].ibv_create_ah_from_wc - ibv_create_ah_from_wc.restype = ctypes.POINTER(struct_ibv_ah) - ibv_create_ah_from_wc.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_wc), ctypes.POINTER(struct_ibv_grh), uint8_t] -except AttributeError: - pass -try: - ibv_destroy_ah = _libraries['libibverbs'].ibv_destroy_ah - ibv_destroy_ah.restype = ctypes.c_int32 - ibv_destroy_ah.argtypes = [ctypes.POINTER(struct_ibv_ah)] -except AttributeError: - pass -try: - ibv_attach_mcast = _libraries['libibverbs'].ibv_attach_mcast - ibv_attach_mcast.restype = ctypes.c_int32 - ibv_attach_mcast.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(union_ibv_gid), uint16_t] -except AttributeError: - pass -try: - ibv_detach_mcast = _libraries['libibverbs'].ibv_detach_mcast - ibv_detach_mcast.restype = ctypes.c_int32 - ibv_detach_mcast.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(union_ibv_gid), uint16_t] -except AttributeError: - pass -try: - ibv_fork_init = _libraries['libibverbs'].ibv_fork_init - ibv_fork_init.restype = ctypes.c_int32 - ibv_fork_init.argtypes = [] -except AttributeError: - pass -try: - ibv_is_fork_initialized = _libraries['libibverbs'].ibv_is_fork_initialized - ibv_is_fork_initialized.restype = ibv_fork_status - ibv_is_fork_initialized.argtypes = [] -except AttributeError: - pass -try: - ibv_node_type_str = _libraries['libibverbs'].ibv_node_type_str - ibv_node_type_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_node_type_str.argtypes = [ibv_node_type] -except AttributeError: - pass -try: - ibv_port_state_str = _libraries['libibverbs'].ibv_port_state_str - ibv_port_state_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_port_state_str.argtypes = [ibv_port_state] -except AttributeError: - pass -try: - ibv_event_type_str = _libraries['libibverbs'].ibv_event_type_str - ibv_event_type_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_event_type_str.argtypes = [ibv_event_type] -except AttributeError: - pass -try: - ibv_resolve_eth_l2_from_gid = _libraries['libibverbs'].ibv_resolve_eth_l2_from_gid - ibv_resolve_eth_l2_from_gid.restype = ctypes.c_int32 - ibv_resolve_eth_l2_from_gid.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_ah_attr), ctypes.c_ubyte * 6, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -try: - ibv_is_qpt_supported = _libraries['libibverbs'].ibv_is_qpt_supported - ibv_is_qpt_supported.restype = ctypes.c_int32 - ibv_is_qpt_supported.argtypes = [uint32_t, ibv_qp_type] -except AttributeError: - pass -try: - ibv_create_counters = _libraries['libibverbs'].ibv_create_counters - ibv_create_counters.restype = ctypes.POINTER(struct_ibv_counters) - ibv_create_counters.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_counters_init_attr)] -except AttributeError: - pass -try: - ibv_destroy_counters = _libraries['libibverbs'].ibv_destroy_counters - ibv_destroy_counters.restype = ctypes.c_int32 - ibv_destroy_counters.argtypes = [ctypes.POINTER(struct_ibv_counters)] -except AttributeError: - pass -try: - ibv_attach_counters_point_flow = _libraries['libibverbs'].ibv_attach_counters_point_flow - ibv_attach_counters_point_flow.restype = ctypes.c_int32 - ibv_attach_counters_point_flow.argtypes = [ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_counter_attach_attr), ctypes.POINTER(struct_ibv_flow)] -except AttributeError: - pass -try: - ibv_read_counters = _libraries['libibverbs'].ibv_read_counters - ibv_read_counters.restype = ctypes.c_int32 - ibv_read_counters.argtypes = [ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(ctypes.c_uint64), uint32_t, uint32_t] -except AttributeError: - pass -try: - ibv_flow_label_to_udp_sport = _libraries['libibverbs'].ibv_flow_label_to_udp_sport - ibv_flow_label_to_udp_sport.restype = uint16_t - ibv_flow_label_to_udp_sport.argtypes = [uint32_t] -except AttributeError: - pass -try: - ibv_set_ece = _libraries['libibverbs'].ibv_set_ece - ibv_set_ece.restype = ctypes.c_int32 - ibv_set_ece.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_ece)] -except AttributeError: - pass -try: - ibv_query_ece = _libraries['libibverbs'].ibv_query_ece - ibv_query_ece.restype = ctypes.c_int32 - ibv_query_ece.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_ece)] -except AttributeError: - pass -__all__ = \ - ['ETHERNET_LL_SIZE', 'IBV_ACCESS_FLUSH_GLOBAL', - 'IBV_ACCESS_FLUSH_PERSISTENT', 'IBV_ACCESS_HUGETLB', - 'IBV_ACCESS_LOCAL_WRITE', 'IBV_ACCESS_MW_BIND', - 'IBV_ACCESS_ON_DEMAND', 'IBV_ACCESS_OPTIONAL_FIRST', - 'IBV_ACCESS_OPTIONAL_RANGE', 'IBV_ACCESS_RELAXED_ORDERING', - 'IBV_ACCESS_REMOTE_ATOMIC', 'IBV_ACCESS_REMOTE_READ', - 'IBV_ACCESS_REMOTE_WRITE', 'IBV_ACCESS_ZERO_BASED', - 'IBV_ADVISE_MR_ADVICE_PREFETCH', - 'IBV_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', - 'IBV_ADVISE_MR_ADVICE_PREFETCH_WRITE', 'IBV_ADVISE_MR_FLAG_FLUSH', - 'IBV_ATOMIC_GLOB', 'IBV_ATOMIC_HCA', 'IBV_ATOMIC_NONE', - 'IBV_COUNTER_BYTES', 'IBV_COUNTER_PACKETS', - 'IBV_CQ_ATTR_MODERATE', 'IBV_CQ_ATTR_RESERVED', - 'IBV_CQ_INIT_ATTR_MASK_FLAGS', 'IBV_CQ_INIT_ATTR_MASK_PD', - 'IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN', - 'IBV_CREATE_CQ_ATTR_SINGLE_THREADED', - 'IBV_CREATE_CQ_SUP_WC_FLAGS', 'IBV_CREATE_IND_TABLE_RESERVED', - 'IBV_DEVICE_AUTO_PATH_MIG', 'IBV_DEVICE_BAD_PKEY_CNTR', - 'IBV_DEVICE_BAD_QKEY_CNTR', 'IBV_DEVICE_CHANGE_PHY_PORT', - 'IBV_DEVICE_CURR_QP_STATE_MOD', 'IBV_DEVICE_INIT_TYPE', - 'IBV_DEVICE_MANAGED_FLOW_STEERING', - 'IBV_DEVICE_MEM_MGT_EXTENSIONS', 'IBV_DEVICE_MEM_WINDOW', - 'IBV_DEVICE_MEM_WINDOW_TYPE_2A', 'IBV_DEVICE_MEM_WINDOW_TYPE_2B', - 'IBV_DEVICE_N_NOTIFY_CQ', 'IBV_DEVICE_PCI_WRITE_END_PADDING', - 'IBV_DEVICE_PORT_ACTIVE_EVENT', 'IBV_DEVICE_RAW_IP_CSUM', - 'IBV_DEVICE_RAW_MULTI', 'IBV_DEVICE_RAW_SCATTER_FCS', - 'IBV_DEVICE_RC_IP_CSUM', 'IBV_DEVICE_RC_RNR_NAK_GEN', - 'IBV_DEVICE_RESIZE_MAX_WR', 'IBV_DEVICE_SHUTDOWN_PORT', - 'IBV_DEVICE_SRQ_RESIZE', 'IBV_DEVICE_SYS_IMAGE_GUID', - 'IBV_DEVICE_UD_AV_PORT_ENFORCE', 'IBV_DEVICE_UD_IP_CSUM', - 'IBV_DEVICE_XRC', 'IBV_DM_MASK_HANDLE', - 'IBV_EVENT_CLIENT_REREGISTER', 'IBV_EVENT_COMM_EST', - 'IBV_EVENT_CQ_ERR', 'IBV_EVENT_DEVICE_FATAL', - 'IBV_EVENT_GID_CHANGE', 'IBV_EVENT_LID_CHANGE', - 'IBV_EVENT_PATH_MIG', 'IBV_EVENT_PATH_MIG_ERR', - 'IBV_EVENT_PKEY_CHANGE', 'IBV_EVENT_PORT_ACTIVE', - 'IBV_EVENT_PORT_ERR', 'IBV_EVENT_QP_ACCESS_ERR', - 'IBV_EVENT_QP_FATAL', 'IBV_EVENT_QP_LAST_WQE_REACHED', - 'IBV_EVENT_QP_REQ_ERR', 'IBV_EVENT_SM_CHANGE', - 'IBV_EVENT_SQ_DRAINED', 'IBV_EVENT_SRQ_ERR', - 'IBV_EVENT_SRQ_LIMIT_REACHED', 'IBV_EVENT_WQ_FATAL', - 'IBV_FLOW_ACTION_ESP_FLAGS_DECRYPT', - 'IBV_FLOW_ACTION_ESP_FLAGS_ENCRYPT', - 'IBV_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', - 'IBV_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', - 'IBV_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', - 'IBV_FLOW_ACTION_ESP_FLAGS_TRANSPORT', - 'IBV_FLOW_ACTION_ESP_FLAGS_TUNNEL', - 'IBV_FLOW_ACTION_ESP_KEYMAT_AES_GCM', - 'IBV_FLOW_ACTION_ESP_MASK_ESN', 'IBV_FLOW_ACTION_ESP_REPLAY_BMP', - 'IBV_FLOW_ACTION_ESP_REPLAY_NONE', 'IBV_FLOW_ACTION_IV_ALGO_SEQ', - 'IBV_FLOW_ATTR_ALL_DEFAULT', 'IBV_FLOW_ATTR_FLAGS_DONT_TRAP', - 'IBV_FLOW_ATTR_FLAGS_EGRESS', 'IBV_FLOW_ATTR_MC_DEFAULT', - 'IBV_FLOW_ATTR_NORMAL', 'IBV_FLOW_ATTR_SNIFFER', - 'IBV_FLOW_SPEC_ACTION_COUNT', 'IBV_FLOW_SPEC_ACTION_DROP', - 'IBV_FLOW_SPEC_ACTION_HANDLE', 'IBV_FLOW_SPEC_ACTION_TAG', - 'IBV_FLOW_SPEC_ESP', 'IBV_FLOW_SPEC_ETH', 'IBV_FLOW_SPEC_GRE', - 'IBV_FLOW_SPEC_INNER', 'IBV_FLOW_SPEC_IPV4', - 'IBV_FLOW_SPEC_IPV4_EXT', 'IBV_FLOW_SPEC_IPV6', - 'IBV_FLOW_SPEC_MPLS', 'IBV_FLOW_SPEC_TCP', 'IBV_FLOW_SPEC_UDP', - 'IBV_FLOW_SPEC_VXLAN_TUNNEL', 'IBV_FLUSH_GLOBAL', 'IBV_FLUSH_MR', - 'IBV_FLUSH_PERSISTENT', 'IBV_FLUSH_RANGE', 'IBV_FORK_DISABLED', - 'IBV_FORK_ENABLED', 'IBV_FORK_UNNEEDED', 'IBV_GID_TYPE_IB', - 'IBV_GID_TYPE_ROCE_V1', 'IBV_GID_TYPE_ROCE_V2', - 'IBV_LINK_LAYER_ETHERNET', 'IBV_LINK_LAYER_INFINIBAND', - 'IBV_LINK_LAYER_UNSPECIFIED', 'IBV_MIG_ARMED', 'IBV_MIG_MIGRATED', - 'IBV_MIG_REARM', 'IBV_MTU_1024', 'IBV_MTU_2048', 'IBV_MTU_256', - 'IBV_MTU_4096', 'IBV_MTU_512', 'IBV_MW_TYPE_1', 'IBV_MW_TYPE_2', - 'IBV_NODE_CA', 'IBV_NODE_RNIC', 'IBV_NODE_ROUTER', - 'IBV_NODE_SWITCH', 'IBV_NODE_UNKNOWN', 'IBV_NODE_UNSPECIFIED', - 'IBV_NODE_USNIC', 'IBV_NODE_USNIC_UDP', 'IBV_ODP_SUPPORT', - 'IBV_ODP_SUPPORT_ATOMIC', 'IBV_ODP_SUPPORT_IMPLICIT', - 'IBV_ODP_SUPPORT_READ', 'IBV_ODP_SUPPORT_RECV', - 'IBV_ODP_SUPPORT_SEND', 'IBV_ODP_SUPPORT_SRQ_RECV', - 'IBV_ODP_SUPPORT_WRITE', 'IBV_OPS_SIGNALED', 'IBV_OPS_TM_SYNC', - 'IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS', - 'IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT', - 'IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP', - 'IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP', - 'IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP', 'IBV_PORT_ACTIVE', - 'IBV_PORT_ACTIVE_DEFER', 'IBV_PORT_ARMED', - 'IBV_PORT_AUTO_MIGR_SUP', 'IBV_PORT_BOOT_MGMT_SUP', - 'IBV_PORT_CAP_MASK2_SUP', 'IBV_PORT_CAP_MASK_NOTICE_SUP', - 'IBV_PORT_CLIENT_REG_SUP', 'IBV_PORT_CM_SUP', - 'IBV_PORT_DEVICE_MGMT_SUP', 'IBV_PORT_DOWN', - 'IBV_PORT_DR_NOTICE_SUP', 'IBV_PORT_EXTENDED_SPEEDS_SUP', - 'IBV_PORT_INFO_EXT_SUP', 'IBV_PORT_INIT', - 'IBV_PORT_IP_BASED_GIDS', 'IBV_PORT_LED_INFO_SUP', - 'IBV_PORT_LINK_LATENCY_SUP', 'IBV_PORT_LINK_SPEED_HDR_SUP', - 'IBV_PORT_LINK_SPEED_NDR_SUP', 'IBV_PORT_LINK_SPEED_XDR_SUP', - 'IBV_PORT_LINK_WIDTH_2X_SUP', 'IBV_PORT_MKEY_NVRAM', - 'IBV_PORT_NOP', 'IBV_PORT_NOTICE_SUP', 'IBV_PORT_OPT_IPD_SUP', - 'IBV_PORT_PKEY_NVRAM', 'IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP', - 'IBV_PORT_REINIT_SUP', 'IBV_PORT_SET_NODE_DESC_SUP', - 'IBV_PORT_SL_MAP_SUP', 'IBV_PORT_SM', 'IBV_PORT_SNMP_TUNNEL_SUP', - 'IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP', - 'IBV_PORT_SYS_IMAGE_GUID_SUP', 'IBV_PORT_TRAP_SUP', - 'IBV_PORT_VENDOR_CLASS_SUP', 'IBV_PORT_VIRT_SUP', - 'IBV_QPF_GRH_REQUIRED', 'IBV_QPS_ERR', 'IBV_QPS_INIT', - 'IBV_QPS_RESET', 'IBV_QPS_RTR', 'IBV_QPS_RTS', 'IBV_QPS_SQD', - 'IBV_QPS_SQE', 'IBV_QPS_UNKNOWN', 'IBV_QPT_DRIVER', - 'IBV_QPT_RAW_PACKET', 'IBV_QPT_RC', 'IBV_QPT_UC', 'IBV_QPT_UD', - 'IBV_QPT_XRC_RECV', 'IBV_QPT_XRC_SEND', 'IBV_QP_ACCESS_FLAGS', - 'IBV_QP_ALT_PATH', 'IBV_QP_AV', 'IBV_QP_CAP', - 'IBV_QP_CREATE_BLOCK_SELF_MCAST_LB', - 'IBV_QP_CREATE_CVLAN_STRIPPING', - 'IBV_QP_CREATE_PCI_WRITE_END_PADDING', - 'IBV_QP_CREATE_SCATTER_FCS', 'IBV_QP_CREATE_SOURCE_QPN', - 'IBV_QP_CUR_STATE', 'IBV_QP_DEST_QPN', - 'IBV_QP_EN_SQD_ASYNC_NOTIFY', 'IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP', - 'IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD', - 'IBV_QP_EX_WITH_ATOMIC_WRITE', 'IBV_QP_EX_WITH_BIND_MW', - 'IBV_QP_EX_WITH_FLUSH', 'IBV_QP_EX_WITH_LOCAL_INV', - 'IBV_QP_EX_WITH_RDMA_READ', 'IBV_QP_EX_WITH_RDMA_WRITE', - 'IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM', 'IBV_QP_EX_WITH_SEND', - 'IBV_QP_EX_WITH_SEND_WITH_IMM', 'IBV_QP_EX_WITH_SEND_WITH_INV', - 'IBV_QP_EX_WITH_TSO', 'IBV_QP_INIT_ATTR_CREATE_FLAGS', - 'IBV_QP_INIT_ATTR_IND_TABLE', 'IBV_QP_INIT_ATTR_MAX_TSO_HEADER', - 'IBV_QP_INIT_ATTR_PD', 'IBV_QP_INIT_ATTR_RX_HASH', - 'IBV_QP_INIT_ATTR_SEND_OPS_FLAGS', 'IBV_QP_INIT_ATTR_XRCD', - 'IBV_QP_MAX_DEST_RD_ATOMIC', 'IBV_QP_MAX_QP_RD_ATOMIC', - 'IBV_QP_MIN_RNR_TIMER', 'IBV_QP_OPEN_ATTR_CONTEXT', - 'IBV_QP_OPEN_ATTR_NUM', 'IBV_QP_OPEN_ATTR_RESERVED', - 'IBV_QP_OPEN_ATTR_TYPE', 'IBV_QP_OPEN_ATTR_XRCD', - 'IBV_QP_PATH_MIG_STATE', 'IBV_QP_PATH_MTU', 'IBV_QP_PKEY_INDEX', - 'IBV_QP_PORT', 'IBV_QP_QKEY', 'IBV_QP_RATE_LIMIT', - 'IBV_QP_RETRY_CNT', 'IBV_QP_RNR_RETRY', 'IBV_QP_RQ_PSN', - 'IBV_QP_SQ_PSN', 'IBV_QP_STATE', 'IBV_QP_TIMEOUT', - 'IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES', - 'IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS', - 'IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG', 'IBV_RATE_100_GBPS', - 'IBV_RATE_10_GBPS', 'IBV_RATE_112_GBPS', 'IBV_RATE_1200_GBPS', - 'IBV_RATE_120_GBPS', 'IBV_RATE_14_GBPS', 'IBV_RATE_168_GBPS', - 'IBV_RATE_200_GBPS', 'IBV_RATE_20_GBPS', 'IBV_RATE_25_GBPS', - 'IBV_RATE_28_GBPS', 'IBV_RATE_2_5_GBPS', 'IBV_RATE_300_GBPS', - 'IBV_RATE_30_GBPS', 'IBV_RATE_400_GBPS', 'IBV_RATE_40_GBPS', - 'IBV_RATE_50_GBPS', 'IBV_RATE_56_GBPS', 'IBV_RATE_5_GBPS', - 'IBV_RATE_600_GBPS', 'IBV_RATE_60_GBPS', 'IBV_RATE_800_GBPS', - 'IBV_RATE_80_GBPS', 'IBV_RATE_MAX', - 'IBV_RAW_PACKET_CAP_CVLAN_STRIPPING', - 'IBV_RAW_PACKET_CAP_DELAY_DROP', 'IBV_RAW_PACKET_CAP_IP_CSUM', - 'IBV_RAW_PACKET_CAP_SCATTER_FCS', - 'IBV_READ_COUNTERS_ATTR_PREFER_CACHED', - 'IBV_REREG_MR_CHANGE_ACCESS', 'IBV_REREG_MR_CHANGE_PD', - 'IBV_REREG_MR_CHANGE_TRANSLATION', 'IBV_REREG_MR_ERR_CMD', - 'IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW', - 'IBV_REREG_MR_ERR_DONT_FORK_NEW', 'IBV_REREG_MR_ERR_DO_FORK_OLD', - 'IBV_REREG_MR_ERR_INPUT', 'IBV_REREG_MR_FLAGS_SUPPORTED', - 'IBV_RX_HASH_DST_IPV4', 'IBV_RX_HASH_DST_IPV6', - 'IBV_RX_HASH_DST_PORT_TCP', 'IBV_RX_HASH_DST_PORT_UDP', - 'IBV_RX_HASH_FUNC_TOEPLITZ', 'IBV_RX_HASH_INNER', - 'IBV_RX_HASH_IPSEC_SPI', 'IBV_RX_HASH_SRC_IPV4', - 'IBV_RX_HASH_SRC_IPV6', 'IBV_RX_HASH_SRC_PORT_TCP', - 'IBV_RX_HASH_SRC_PORT_UDP', 'IBV_SEND_FENCE', 'IBV_SEND_INLINE', - 'IBV_SEND_IP_CSUM', 'IBV_SEND_SIGNALED', 'IBV_SEND_SOLICITED', - 'IBV_SRQT_BASIC', 'IBV_SRQT_TM', 'IBV_SRQT_XRC', - 'IBV_SRQ_INIT_ATTR_CQ', 'IBV_SRQ_INIT_ATTR_PD', - 'IBV_SRQ_INIT_ATTR_RESERVED', 'IBV_SRQ_INIT_ATTR_TM', - 'IBV_SRQ_INIT_ATTR_TYPE', 'IBV_SRQ_INIT_ATTR_XRCD', - 'IBV_SRQ_LIMIT', 'IBV_SRQ_MAX_WR', 'IBV_SYSFS_NAME_MAX', - 'IBV_SYSFS_PATH_MAX', 'IBV_TM_CAP_RC', 'IBV_TRANSPORT_IB', - 'IBV_TRANSPORT_IWARP', 'IBV_TRANSPORT_UNKNOWN', - 'IBV_TRANSPORT_UNSPECIFIED', 'IBV_TRANSPORT_USNIC', - 'IBV_TRANSPORT_USNIC_UDP', 'IBV_VALUES_MASK_RAW_CLOCK', - 'IBV_VALUES_MASK_RESERVED', 'IBV_WC_ATOMIC_WRITE', - 'IBV_WC_BAD_RESP_ERR', 'IBV_WC_BIND_MW', 'IBV_WC_COMP_SWAP', - 'IBV_WC_DRIVER1', 'IBV_WC_DRIVER2', 'IBV_WC_DRIVER3', - 'IBV_WC_EX_WITH_BYTE_LEN', 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP', - 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK', - 'IBV_WC_EX_WITH_CVLAN', 'IBV_WC_EX_WITH_DLID_PATH_BITS', - 'IBV_WC_EX_WITH_FLOW_TAG', 'IBV_WC_EX_WITH_IMM', - 'IBV_WC_EX_WITH_QP_NUM', 'IBV_WC_EX_WITH_SL', - 'IBV_WC_EX_WITH_SLID', 'IBV_WC_EX_WITH_SRC_QP', - 'IBV_WC_EX_WITH_TM_INFO', 'IBV_WC_FATAL_ERR', 'IBV_WC_FETCH_ADD', - 'IBV_WC_FLUSH', 'IBV_WC_GENERAL_ERR', 'IBV_WC_GRH', - 'IBV_WC_INV_EECN_ERR', 'IBV_WC_INV_EEC_STATE_ERR', - 'IBV_WC_IP_CSUM_OK', 'IBV_WC_IP_CSUM_OK_SHIFT', - 'IBV_WC_LOCAL_INV', 'IBV_WC_LOC_ACCESS_ERR', - 'IBV_WC_LOC_EEC_OP_ERR', 'IBV_WC_LOC_LEN_ERR', - 'IBV_WC_LOC_PROT_ERR', 'IBV_WC_LOC_QP_OP_ERR', - 'IBV_WC_LOC_RDD_VIOL_ERR', 'IBV_WC_MW_BIND_ERR', - 'IBV_WC_RDMA_READ', 'IBV_WC_RDMA_WRITE', 'IBV_WC_RECV', - 'IBV_WC_RECV_RDMA_WITH_IMM', 'IBV_WC_REM_ABORT_ERR', - 'IBV_WC_REM_ACCESS_ERR', 'IBV_WC_REM_INV_RD_REQ_ERR', - 'IBV_WC_REM_INV_REQ_ERR', 'IBV_WC_REM_OP_ERR', - 'IBV_WC_RESP_TIMEOUT_ERR', 'IBV_WC_RETRY_EXC_ERR', - 'IBV_WC_RNR_RETRY_EXC_ERR', 'IBV_WC_SEND', - 'IBV_WC_STANDARD_FLAGS', 'IBV_WC_SUCCESS', 'IBV_WC_TM_ADD', - 'IBV_WC_TM_DATA_VALID', 'IBV_WC_TM_DEL', 'IBV_WC_TM_ERR', - 'IBV_WC_TM_MATCH', 'IBV_WC_TM_NO_TAG', 'IBV_WC_TM_RECV', - 'IBV_WC_TM_RNDV_INCOMPLETE', 'IBV_WC_TM_SYNC', - 'IBV_WC_TM_SYNC_REQ', 'IBV_WC_TSO', 'IBV_WC_WITH_IMM', - 'IBV_WC_WITH_INV', 'IBV_WC_WR_FLUSH_ERR', 'IBV_WQS_ERR', - 'IBV_WQS_RDY', 'IBV_WQS_RESET', 'IBV_WQS_UNKNOWN', 'IBV_WQT_RQ', - 'IBV_WQ_ATTR_CURR_STATE', 'IBV_WQ_ATTR_FLAGS', - 'IBV_WQ_ATTR_RESERVED', 'IBV_WQ_ATTR_STATE', - 'IBV_WQ_FLAGS_CVLAN_STRIPPING', 'IBV_WQ_FLAGS_DELAY_DROP', - 'IBV_WQ_FLAGS_PCI_WRITE_END_PADDING', 'IBV_WQ_FLAGS_RESERVED', - 'IBV_WQ_FLAGS_SCATTER_FCS', 'IBV_WQ_INIT_ATTR_FLAGS', - 'IBV_WQ_INIT_ATTR_RESERVED', 'IBV_WR_ATOMIC_CMP_AND_SWP', - 'IBV_WR_ATOMIC_FETCH_AND_ADD', 'IBV_WR_ATOMIC_WRITE', - 'IBV_WR_BIND_MW', 'IBV_WR_DRIVER1', 'IBV_WR_FLUSH', - 'IBV_WR_LOCAL_INV', 'IBV_WR_RDMA_READ', 'IBV_WR_RDMA_WRITE', - 'IBV_WR_RDMA_WRITE_WITH_IMM', 'IBV_WR_SEND', - 'IBV_WR_SEND_WITH_IMM', 'IBV_WR_SEND_WITH_INV', 'IBV_WR_TAG_ADD', - 'IBV_WR_TAG_DEL', 'IBV_WR_TAG_SYNC', 'IBV_WR_TSO', - 'IBV_XRCD_INIT_ATTR_FD', 'IBV_XRCD_INIT_ATTR_OFLAGS', - 'IBV_XRCD_INIT_ATTR_RESERVED', 'IB_DEVICE_NAME_MAX', - 'IB_FLUSH_GLOBAL', 'IB_FLUSH_MR', 'IB_FLUSH_PERSISTENT', - 'IB_FLUSH_RANGE', 'IB_GRH_FLOWLABEL_MASK', - 'IB_ROCE_UDP_ENCAP_VALID_PORT_MAX', - 'IB_ROCE_UDP_ENCAP_VALID_PORT_MIN', 'IB_USER_IOCTL_VERBS_H', - 'IB_USER_VERBS_ABI_VERSION', 'IB_USER_VERBS_CMD_ALLOC_MW', - 'IB_USER_VERBS_CMD_ALLOC_PD', 'IB_USER_VERBS_CMD_ATTACH_MCAST', - 'IB_USER_VERBS_CMD_BIND_MW', 'IB_USER_VERBS_CMD_CLOSE_XRCD', - 'IB_USER_VERBS_CMD_COMMAND_MASK', 'IB_USER_VERBS_CMD_CREATE_AH', - 'IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL', - 'IB_USER_VERBS_CMD_CREATE_CQ', 'IB_USER_VERBS_CMD_CREATE_QP', - 'IB_USER_VERBS_CMD_CREATE_SRQ', 'IB_USER_VERBS_CMD_CREATE_XSRQ', - 'IB_USER_VERBS_CMD_DEALLOC_MW', 'IB_USER_VERBS_CMD_DEALLOC_PD', - 'IB_USER_VERBS_CMD_DEREG_MR', 'IB_USER_VERBS_CMD_DESTROY_AH', - 'IB_USER_VERBS_CMD_DESTROY_CQ', 'IB_USER_VERBS_CMD_DESTROY_QP', - 'IB_USER_VERBS_CMD_DESTROY_SRQ', 'IB_USER_VERBS_CMD_DETACH_MCAST', - 'IB_USER_VERBS_CMD_FLAG_EXTENDED', - 'IB_USER_VERBS_CMD_GET_CONTEXT', 'IB_USER_VERBS_CMD_MODIFY_AH', - 'IB_USER_VERBS_CMD_MODIFY_QP', 'IB_USER_VERBS_CMD_MODIFY_SRQ', - 'IB_USER_VERBS_CMD_OPEN_QP', 'IB_USER_VERBS_CMD_OPEN_XRCD', - 'IB_USER_VERBS_CMD_PEEK_CQ', 'IB_USER_VERBS_CMD_POLL_CQ', - 'IB_USER_VERBS_CMD_POST_RECV', 'IB_USER_VERBS_CMD_POST_SEND', - 'IB_USER_VERBS_CMD_POST_SRQ_RECV', 'IB_USER_VERBS_CMD_QUERY_AH', - 'IB_USER_VERBS_CMD_QUERY_DEVICE', 'IB_USER_VERBS_CMD_QUERY_MR', - 'IB_USER_VERBS_CMD_QUERY_PORT', 'IB_USER_VERBS_CMD_QUERY_QP', - 'IB_USER_VERBS_CMD_QUERY_SRQ', 'IB_USER_VERBS_CMD_REG_MR', - 'IB_USER_VERBS_CMD_REG_SMR', 'IB_USER_VERBS_CMD_REQ_NOTIFY_CQ', - 'IB_USER_VERBS_CMD_REREG_MR', 'IB_USER_VERBS_CMD_RESIZE_CQ', - 'IB_USER_VERBS_CMD_THRESHOLD', 'IB_USER_VERBS_EX_CMD_CREATE_CQ', - 'IB_USER_VERBS_EX_CMD_CREATE_FLOW', - 'IB_USER_VERBS_EX_CMD_CREATE_QP', - 'IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL', - 'IB_USER_VERBS_EX_CMD_CREATE_WQ', - 'IB_USER_VERBS_EX_CMD_DESTROY_FLOW', - 'IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL', - 'IB_USER_VERBS_EX_CMD_DESTROY_WQ', - 'IB_USER_VERBS_EX_CMD_MODIFY_CQ', - 'IB_USER_VERBS_EX_CMD_MODIFY_QP', - 'IB_USER_VERBS_EX_CMD_MODIFY_WQ', - 'IB_USER_VERBS_EX_CMD_QUERY_DEVICE', 'IB_USER_VERBS_H', - 'IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE', - 'IB_UVERBS_ACCESS_FLUSH_GLOBAL', - 'IB_UVERBS_ACCESS_FLUSH_PERSISTENT', 'IB_UVERBS_ACCESS_HUGETLB', - 'IB_UVERBS_ACCESS_LOCAL_WRITE', 'IB_UVERBS_ACCESS_MW_BIND', - 'IB_UVERBS_ACCESS_ON_DEMAND', 'IB_UVERBS_ACCESS_OPTIONAL_FIRST', - 'IB_UVERBS_ACCESS_OPTIONAL_LAST', - 'IB_UVERBS_ACCESS_OPTIONAL_RANGE', - 'IB_UVERBS_ACCESS_RELAXED_ORDERING', - 'IB_UVERBS_ACCESS_REMOTE_ATOMIC', 'IB_UVERBS_ACCESS_REMOTE_READ', - 'IB_UVERBS_ACCESS_REMOTE_WRITE', 'IB_UVERBS_ACCESS_ZERO_BASED', - 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH', - 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', - 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE', - 'IB_UVERBS_ADVISE_MR_FLAG_FLUSH', - 'IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS', - 'IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN', - 'IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION', - 'IB_UVERBS_CREATE_QP_MASK_IND_TABLE', - 'IB_UVERBS_CREATE_QP_SUP_COMP_MASK', - 'IB_UVERBS_DEVICE_ATOMIC_WRITE', 'IB_UVERBS_DEVICE_AUTO_PATH_MIG', - 'IB_UVERBS_DEVICE_BAD_PKEY_CNTR', - 'IB_UVERBS_DEVICE_BAD_QKEY_CNTR', - 'IB_UVERBS_DEVICE_CHANGE_PHY_PORT', - 'IB_UVERBS_DEVICE_CURR_QP_STATE_MOD', - 'IB_UVERBS_DEVICE_FLUSH_GLOBAL', - 'IB_UVERBS_DEVICE_FLUSH_PERSISTENT', - 'IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING', - 'IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS', - 'IB_UVERBS_DEVICE_MEM_WINDOW', - 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A', - 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B', - 'IB_UVERBS_DEVICE_N_NOTIFY_CQ', - 'IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING', - 'IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT', - 'IB_UVERBS_DEVICE_RAW_IP_CSUM', 'IB_UVERBS_DEVICE_RAW_MULTI', - 'IB_UVERBS_DEVICE_RAW_SCATTER_FCS', 'IB_UVERBS_DEVICE_RC_IP_CSUM', - 'IB_UVERBS_DEVICE_RC_RNR_NAK_GEN', - 'IB_UVERBS_DEVICE_RESIZE_MAX_WR', - 'IB_UVERBS_DEVICE_SHUTDOWN_PORT', 'IB_UVERBS_DEVICE_SRQ_RESIZE', - 'IB_UVERBS_DEVICE_SYS_IMAGE_GUID', - 'IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE', - 'IB_UVERBS_DEVICE_UD_IP_CSUM', 'IB_UVERBS_DEVICE_XRC', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL', - 'IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM', - 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP', - 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE', - 'IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ', 'IB_UVERBS_GID_TYPE_IB', - 'IB_UVERBS_GID_TYPE_ROCE_V1', 'IB_UVERBS_GID_TYPE_ROCE_V2', - 'IB_UVERBS_PCF_AUTO_MIGR_SUP', 'IB_UVERBS_PCF_BOOT_MGMT_SUP', - 'IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP', - 'IB_UVERBS_PCF_CLIENT_REG_SUP', 'IB_UVERBS_PCF_CM_SUP', - 'IB_UVERBS_PCF_DEVICE_MGMT_SUP', 'IB_UVERBS_PCF_DR_NOTICE_SUP', - 'IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP', - 'IB_UVERBS_PCF_HIERARCHY_INFO_SUP', 'IB_UVERBS_PCF_IP_BASED_GIDS', - 'IB_UVERBS_PCF_LED_INFO_SUP', 'IB_UVERBS_PCF_LINK_LATENCY_SUP', - 'IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP', - 'IB_UVERBS_PCF_MCAST_FDB_TOP_SUP', - 'IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP', - 'IB_UVERBS_PCF_MKEY_NVRAM', 'IB_UVERBS_PCF_NOTICE_SUP', - 'IB_UVERBS_PCF_OPT_IPD_SUP', 'IB_UVERBS_PCF_PKEY_NVRAM', - 'IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP', - 'IB_UVERBS_PCF_REINIT_SUP', 'IB_UVERBS_PCF_SL_MAP_SUP', - 'IB_UVERBS_PCF_SM', 'IB_UVERBS_PCF_SM_DISABLED', - 'IB_UVERBS_PCF_SNMP_TUNNEL_SUP', - 'IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP', 'IB_UVERBS_PCF_TRAP_SUP', - 'IB_UVERBS_PCF_VENDOR_CLASS_SUP', - 'IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP', - 'IB_UVERBS_QPF_GRH_REQUIRED', 'IB_UVERBS_QPT_DRIVER', - 'IB_UVERBS_QPT_RAW_PACKET', 'IB_UVERBS_QPT_RC', - 'IB_UVERBS_QPT_UC', 'IB_UVERBS_QPT_UD', 'IB_UVERBS_QPT_XRC_INI', - 'IB_UVERBS_QPT_XRC_TGT', - 'IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK', - 'IB_UVERBS_QP_CREATE_CVLAN_STRIPPING', - 'IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING', - 'IB_UVERBS_QP_CREATE_SCATTER_FCS', - 'IB_UVERBS_QP_CREATE_SQ_SIG_ALL', - 'IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING', - 'IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP', - 'IB_UVERBS_RAW_PACKET_CAP_IP_CSUM', - 'IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS', - 'IB_UVERBS_READ_COUNTERS_PREFER_CACHED', 'IB_UVERBS_SRQT_BASIC', - 'IB_UVERBS_SRQT_TM', 'IB_UVERBS_SRQT_XRC', - 'IB_UVERBS_WC_ATOMIC_WRITE', 'IB_UVERBS_WC_BIND_MW', - 'IB_UVERBS_WC_COMP_SWAP', 'IB_UVERBS_WC_FETCH_ADD', - 'IB_UVERBS_WC_FLUSH', 'IB_UVERBS_WC_LOCAL_INV', - 'IB_UVERBS_WC_RDMA_READ', 'IB_UVERBS_WC_RDMA_WRITE', - 'IB_UVERBS_WC_SEND', 'IB_UVERBS_WC_TSO', 'IB_UVERBS_WQT_RQ', - 'IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING', - 'IB_UVERBS_WQ_FLAGS_DELAY_DROP', - 'IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING', - 'IB_UVERBS_WQ_FLAGS_SCATTER_FCS', - 'IB_UVERBS_WR_ATOMIC_CMP_AND_SWP', - 'IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD', 'IB_UVERBS_WR_ATOMIC_WRITE', - 'IB_UVERBS_WR_BIND_MW', 'IB_UVERBS_WR_FLUSH', - 'IB_UVERBS_WR_LOCAL_INV', - 'IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP', - 'IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD', - 'IB_UVERBS_WR_RDMA_READ', 'IB_UVERBS_WR_RDMA_READ_WITH_INV', - 'IB_UVERBS_WR_RDMA_WRITE', 'IB_UVERBS_WR_RDMA_WRITE_WITH_IMM', - 'IB_UVERBS_WR_SEND', 'IB_UVERBS_WR_SEND_WITH_IMM', - 'IB_UVERBS_WR_SEND_WITH_INV', 'IB_UVERBS_WR_TSO', - 'INFINIBAND_VERBS_H', 'RDMA_DRIVER_BNXT_RE', 'RDMA_DRIVER_CXGB3', - 'RDMA_DRIVER_CXGB4', 'RDMA_DRIVER_EFA', 'RDMA_DRIVER_ERDMA', - 'RDMA_DRIVER_HFI1', 'RDMA_DRIVER_HNS', 'RDMA_DRIVER_I40IW', - 'RDMA_DRIVER_IRDMA', 'RDMA_DRIVER_MANA', 'RDMA_DRIVER_MLX4', - 'RDMA_DRIVER_MLX5', 'RDMA_DRIVER_MTHCA', 'RDMA_DRIVER_NES', - 'RDMA_DRIVER_OCRDMA', 'RDMA_DRIVER_QEDR', 'RDMA_DRIVER_QIB', - 'RDMA_DRIVER_RXE', 'RDMA_DRIVER_SIW', 'RDMA_DRIVER_UNKNOWN', - 'RDMA_DRIVER_USNIC', 'RDMA_DRIVER_VMW_PVRDMA', 'VERBS_API_H', - '___ibv_query_port', '__attribute_const', '__be16', '__be32', - '__be64', '__ibv_reg_mr', '__ibv_reg_mr_iova', - '_ibv_query_gid_ex', '_ibv_query_gid_table', - 'c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS', - 'c__Ea_IBV_LINK_LAYER_UNSPECIFIED', 'c__Ea_IBV_SYSFS_NAME_MAX', - 'c__Ea_IBV_WC_IP_CSUM_OK_SHIFT', 'c__Ea_IBV_WC_STANDARD_FLAGS', - 'c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE', - 'c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK', 'ib_placement_type', - 'ib_selectivity_level', 'ib_uverbs_access_flags', - 'ib_uverbs_advise_mr_advice', 'ib_uverbs_advise_mr_flag', - 'ib_uverbs_core_support', 'ib_uverbs_create_qp_mask', - 'ib_uverbs_device_cap_flags', 'ib_uverbs_ex_create_cq_flags', - 'ib_uverbs_flow_action_esp_flags', - 'ib_uverbs_flow_action_esp_keymat', - 'ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo', - 'ib_uverbs_flow_action_esp_replay', 'ib_uverbs_gid_type', - 'ib_uverbs_qp_create_flags', 'ib_uverbs_qp_type', - 'ib_uverbs_query_port_cap_flags', 'ib_uverbs_query_port_flags', - 'ib_uverbs_raw_packet_caps', 'ib_uverbs_read_counters_flags', - 'ib_uverbs_srq_type', 'ib_uverbs_wc_opcode', 'ib_uverbs_wq_flags', - 'ib_uverbs_wq_type', 'ib_uverbs_wr_opcode', - 'ib_uverbs_write_cmds', 'ibv_access_flags', 'ibv_ack_async_event', - 'ibv_ack_cq_events', 'ibv_advise_mr', 'ibv_advise_mr_advice', - 'ibv_alloc_dm', 'ibv_alloc_mw', 'ibv_alloc_null_mr', - 'ibv_alloc_parent_domain', 'ibv_alloc_pd', 'ibv_alloc_td', - 'ibv_atomic_cap', 'ibv_attach_counters_point_flow', - 'ibv_attach_mcast', 'ibv_bind_mw', 'ibv_close_device', - 'ibv_close_xrcd', 'ibv_counter_description', 'ibv_cq_attr_mask', - 'ibv_cq_ex_to_cq', 'ibv_cq_init_attr_mask', 'ibv_create_ah', - 'ibv_create_ah_from_wc', 'ibv_create_comp_channel', - 'ibv_create_counters', 'ibv_create_cq', - 'ibv_create_cq_attr_flags', 'ibv_create_cq_ex', - 'ibv_create_cq_wc_flags', 'ibv_create_flow', - 'ibv_create_flow_action_esp', 'ibv_create_qp', 'ibv_create_qp_ex', - 'ibv_create_rwq_ind_table', 'ibv_create_srq', 'ibv_create_srq_ex', - 'ibv_create_wq', 'ibv_dealloc_mw', 'ibv_dealloc_pd', - 'ibv_dealloc_td', 'ibv_dereg_mr', 'ibv_destroy_ah', - 'ibv_destroy_comp_channel', 'ibv_destroy_counters', - 'ibv_destroy_cq', 'ibv_destroy_flow', 'ibv_destroy_flow_action', - 'ibv_destroy_qp', 'ibv_destroy_rwq_ind_table', 'ibv_destroy_srq', - 'ibv_destroy_wq', 'ibv_detach_mcast', 'ibv_device_cap_flags', - 'ibv_dm_mask', 'ibv_end_poll', 'ibv_event_type', - 'ibv_event_type_str', 'ibv_flow_action_esp_flags', - 'ibv_flow_action_esp_keymat', - 'ibv_flow_action_esp_keymat_aes_gcm_iv_algo', - 'ibv_flow_action_esp_mask', 'ibv_flow_action_esp_replay', - 'ibv_flow_attr_type', 'ibv_flow_flags', - 'ibv_flow_label_to_udp_sport', 'ibv_flow_spec_type', - 'ibv_fork_init', 'ibv_fork_status', 'ibv_free_device_list', - 'ibv_free_dm', 'ibv_get_async_event', 'ibv_get_cq_event', - 'ibv_get_device_guid', 'ibv_get_device_index', - 'ibv_get_device_list', 'ibv_get_device_name', - 'ibv_get_pkey_index', 'ibv_get_srq_num', 'ibv_gid_type', - 'ibv_import_device', 'ibv_import_dm', 'ibv_import_mr', - 'ibv_import_pd', 'ibv_inc_rkey', 'ibv_ind_table_init_attr_mask', - 'ibv_init_ah_from_wc', 'ibv_is_fork_initialized', - 'ibv_is_qpt_supported', 'ibv_memcpy_from_dm', 'ibv_memcpy_to_dm', - 'ibv_mig_state', 'ibv_modify_cq', 'ibv_modify_flow_action_esp', - 'ibv_modify_qp', 'ibv_modify_qp_rate_limit', 'ibv_modify_srq', - 'ibv_modify_wq', 'ibv_mtu', 'ibv_mw_type', 'ibv_next_poll', - 'ibv_node_type', 'ibv_node_type_str', 'ibv_odp_general_caps', - 'ibv_odp_transport_cap_bits', 'ibv_open_device', 'ibv_open_qp', - 'ibv_open_xrcd', 'ibv_ops_flags', 'ibv_ops_wr_opcode', - 'ibv_parent_domain_init_attr_mask', 'ibv_pci_atomic_op_size', - 'ibv_placement_type', 'ibv_poll_cq', 'ibv_port_cap_flags', - 'ibv_port_cap_flags2', 'ibv_port_state', 'ibv_port_state_str', - 'ibv_post_recv', 'ibv_post_send', 'ibv_post_srq_ops', - 'ibv_post_srq_recv', 'ibv_post_wq_recv', 'ibv_qp_attr_mask', - 'ibv_qp_create_flags', 'ibv_qp_create_send_ops_flags', - 'ibv_qp_init_attr_mask', 'ibv_qp_open_attr_mask', 'ibv_qp_state', - 'ibv_qp_to_qp_ex', 'ibv_qp_type', 'ibv_query_device', - 'ibv_query_device_ex', 'ibv_query_ece', 'ibv_query_gid', - 'ibv_query_gid_ex', 'ibv_query_gid_table', 'ibv_query_pkey', - 'ibv_query_qp', 'ibv_query_qp_data_in_order', - 'ibv_query_qp_data_in_order_caps', - 'ibv_query_qp_data_in_order_flags', 'ibv_query_rt_values_ex', - 'ibv_query_srq', 'ibv_rate', 'ibv_rate_to_mbps', - 'ibv_rate_to_mult', 'ibv_raw_packet_caps', 'ibv_read_counters', - 'ibv_read_counters_flags', 'ibv_reg_dm_mr', 'ibv_reg_dmabuf_mr', - 'ibv_reg_mr_iova2', 'ibv_req_notify_cq', 'ibv_rereg_mr', - 'ibv_rereg_mr_err_code', 'ibv_rereg_mr_flags', 'ibv_resize_cq', - 'ibv_resolve_eth_l2_from_gid', 'ibv_rx_hash_fields', - 'ibv_rx_hash_function_flags', 'ibv_selectivity_level', - 'ibv_send_flags', 'ibv_set_ece', 'ibv_srq_attr_mask', - 'ibv_srq_init_attr_mask', 'ibv_srq_type', 'ibv_start_poll', - 'ibv_tm_cap_flags', 'ibv_transport_type', 'ibv_unimport_dm', - 'ibv_unimport_mr', 'ibv_unimport_pd', 'ibv_values_mask', - 'ibv_wc_flags', 'ibv_wc_opcode', 'ibv_wc_read_byte_len', - 'ibv_wc_read_completion_ts', - 'ibv_wc_read_completion_wallclock_ns', 'ibv_wc_read_cvlan', - 'ibv_wc_read_dlid_path_bits', 'ibv_wc_read_flow_tag', - 'ibv_wc_read_imm_data', 'ibv_wc_read_invalidated_rkey', - 'ibv_wc_read_opcode', 'ibv_wc_read_qp_num', 'ibv_wc_read_sl', - 'ibv_wc_read_slid', 'ibv_wc_read_src_qp', 'ibv_wc_read_tm_info', - 'ibv_wc_read_vendor_err', 'ibv_wc_read_wc_flags', 'ibv_wc_status', - 'ibv_wc_status_str', 'ibv_wq_attr_mask', 'ibv_wq_flags', - 'ibv_wq_init_attr_mask', 'ibv_wq_state', 'ibv_wq_type', - 'ibv_wr_abort', 'ibv_wr_atomic_cmp_swp', - 'ibv_wr_atomic_fetch_add', 'ibv_wr_atomic_write', - 'ibv_wr_bind_mw', 'ibv_wr_complete', 'ibv_wr_flush', - 'ibv_wr_local_inv', 'ibv_wr_opcode', 'ibv_wr_opcode_str', - 'ibv_wr_rdma_read', 'ibv_wr_rdma_write', 'ibv_wr_rdma_write_imm', - 'ibv_wr_send', 'ibv_wr_send_imm', 'ibv_wr_send_inv', - 'ibv_wr_send_tso', 'ibv_wr_set_inline_data', - 'ibv_wr_set_inline_data_list', 'ibv_wr_set_sge', - 'ibv_wr_set_sge_list', 'ibv_wr_set_ud_addr', - 'ibv_wr_set_xrc_srqn', 'ibv_wr_start', 'ibv_xrcd_init_attr_mask', - 'mbps_to_ibv_rate', 'mult_to_ibv_rate', 'rdma_driver_id', - 'size_t', 'ssize_t', 'struct___pthread_cond_s', - 'struct___pthread_internal_list', 'struct___pthread_mutex_s', - 'struct__compat_ibv_port_attr', 'struct__ibv_device_ops', - 'struct_c__UA___atomic_wide_counter___value32', - 'struct_ib_uverbs_ah_attr', 'struct_ib_uverbs_alloc_mw', - 'struct_ib_uverbs_alloc_mw_resp', 'struct_ib_uverbs_alloc_pd', - 'struct_ib_uverbs_alloc_pd_resp', - 'struct_ib_uverbs_async_event_desc', - 'struct_ib_uverbs_attach_mcast', 'struct_ib_uverbs_close_xrcd', - 'struct_ib_uverbs_cmd_hdr', 'struct_ib_uverbs_comp_event_desc', - 'struct_ib_uverbs_cq_moderation', - 'struct_ib_uverbs_cq_moderation_caps', - 'struct_ib_uverbs_create_ah', 'struct_ib_uverbs_create_ah_resp', - 'struct_ib_uverbs_create_comp_channel', - 'struct_ib_uverbs_create_comp_channel_resp', - 'struct_ib_uverbs_create_cq', 'struct_ib_uverbs_create_cq_resp', - 'struct_ib_uverbs_create_flow', - 'struct_ib_uverbs_create_flow_resp', 'struct_ib_uverbs_create_qp', - 'struct_ib_uverbs_create_qp_resp', 'struct_ib_uverbs_create_srq', - 'struct_ib_uverbs_create_srq_resp', - 'struct_ib_uverbs_create_xsrq', 'struct_ib_uverbs_dealloc_mw', - 'struct_ib_uverbs_dealloc_pd', 'struct_ib_uverbs_dereg_mr', - 'struct_ib_uverbs_destroy_ah', 'struct_ib_uverbs_destroy_cq', - 'struct_ib_uverbs_destroy_cq_resp', - 'struct_ib_uverbs_destroy_flow', 'struct_ib_uverbs_destroy_qp', - 'struct_ib_uverbs_destroy_qp_resp', - 'struct_ib_uverbs_destroy_srq', - 'struct_ib_uverbs_destroy_srq_resp', - 'struct_ib_uverbs_detach_mcast', 'struct_ib_uverbs_ex_cmd_hdr', - 'struct_ib_uverbs_ex_create_cq', - 'struct_ib_uverbs_ex_create_cq_resp', - 'struct_ib_uverbs_ex_create_qp', - 'struct_ib_uverbs_ex_create_qp_resp', - 'struct_ib_uverbs_ex_create_rwq_ind_table', - 'struct_ib_uverbs_ex_create_rwq_ind_table_resp', - 'struct_ib_uverbs_ex_create_wq', - 'struct_ib_uverbs_ex_create_wq_resp', - 'struct_ib_uverbs_ex_destroy_rwq_ind_table', - 'struct_ib_uverbs_ex_destroy_wq', - 'struct_ib_uverbs_ex_destroy_wq_resp', - 'struct_ib_uverbs_ex_modify_cq', 'struct_ib_uverbs_ex_modify_qp', - 'struct_ib_uverbs_ex_modify_qp_resp', - 'struct_ib_uverbs_ex_modify_wq', - 'struct_ib_uverbs_ex_query_device', - 'struct_ib_uverbs_ex_query_device_resp', - 'struct_ib_uverbs_flow_action_esp', - 'struct_ib_uverbs_flow_action_esp_encap', - 'struct_ib_uverbs_flow_action_esp_keymat_aes_gcm', - 'struct_ib_uverbs_flow_action_esp_replay_bmp', - 'struct_ib_uverbs_flow_attr', 'struct_ib_uverbs_flow_eth_filter', - 'struct_ib_uverbs_flow_gre_filter', - 'struct_ib_uverbs_flow_ipv4_filter', - 'struct_ib_uverbs_flow_ipv6_filter', - 'struct_ib_uverbs_flow_mpls_filter', - 'struct_ib_uverbs_flow_spec_action_count', - 'struct_ib_uverbs_flow_spec_action_count_0_0', - 'struct_ib_uverbs_flow_spec_action_drop', - 'struct_ib_uverbs_flow_spec_action_drop_0_0', - 'struct_ib_uverbs_flow_spec_action_handle', - 'struct_ib_uverbs_flow_spec_action_handle_0_0', - 'struct_ib_uverbs_flow_spec_action_tag', - 'struct_ib_uverbs_flow_spec_action_tag_0_0', - 'struct_ib_uverbs_flow_spec_esp', - 'struct_ib_uverbs_flow_spec_esp_0_0', - 'struct_ib_uverbs_flow_spec_esp_filter', - 'struct_ib_uverbs_flow_spec_eth', - 'struct_ib_uverbs_flow_spec_eth_0_0', - 'struct_ib_uverbs_flow_spec_gre', - 'struct_ib_uverbs_flow_spec_gre_0_0', - 'struct_ib_uverbs_flow_spec_hdr', - 'struct_ib_uverbs_flow_spec_ipv4', - 'struct_ib_uverbs_flow_spec_ipv4_0_0', - 'struct_ib_uverbs_flow_spec_ipv6', - 'struct_ib_uverbs_flow_spec_ipv6_0_0', - 'struct_ib_uverbs_flow_spec_mpls', - 'struct_ib_uverbs_flow_spec_mpls_0_0', - 'struct_ib_uverbs_flow_spec_tcp_udp', - 'struct_ib_uverbs_flow_spec_tcp_udp_0_0', - 'struct_ib_uverbs_flow_spec_tunnel', - 'struct_ib_uverbs_flow_spec_tunnel_0_0', - 'struct_ib_uverbs_flow_tcp_udp_filter', - 'struct_ib_uverbs_flow_tunnel_filter', - 'struct_ib_uverbs_get_context', - 'struct_ib_uverbs_get_context_resp', 'struct_ib_uverbs_gid_entry', - 'struct_ib_uverbs_global_route', 'struct_ib_uverbs_modify_qp', - 'struct_ib_uverbs_modify_srq', 'struct_ib_uverbs_odp_caps', - 'struct_ib_uverbs_odp_caps_per_transport_caps', - 'struct_ib_uverbs_open_qp', 'struct_ib_uverbs_open_xrcd', - 'struct_ib_uverbs_open_xrcd_resp', 'struct_ib_uverbs_poll_cq', - 'struct_ib_uverbs_poll_cq_resp', 'struct_ib_uverbs_post_recv', - 'struct_ib_uverbs_post_recv_resp', 'struct_ib_uverbs_post_send', - 'struct_ib_uverbs_post_send_resp', - 'struct_ib_uverbs_post_srq_recv', - 'struct_ib_uverbs_post_srq_recv_resp', 'struct_ib_uverbs_qp_attr', - 'struct_ib_uverbs_qp_cap', 'struct_ib_uverbs_qp_dest', - 'struct_ib_uverbs_query_device', - 'struct_ib_uverbs_query_device_resp', - 'struct_ib_uverbs_query_port', 'struct_ib_uverbs_query_port_resp', - 'struct_ib_uverbs_query_port_resp_ex', - 'struct_ib_uverbs_query_qp', 'struct_ib_uverbs_query_qp_resp', - 'struct_ib_uverbs_query_srq', 'struct_ib_uverbs_query_srq_resp', - 'struct_ib_uverbs_recv_wr', 'struct_ib_uverbs_reg_mr', - 'struct_ib_uverbs_reg_mr_resp', 'struct_ib_uverbs_req_notify_cq', - 'struct_ib_uverbs_rereg_mr', 'struct_ib_uverbs_rereg_mr_resp', - 'struct_ib_uverbs_resize_cq', 'struct_ib_uverbs_resize_cq_resp', - 'struct_ib_uverbs_rss_caps', 'struct_ib_uverbs_send_wr', - 'struct_ib_uverbs_send_wr_1_atomic', - 'struct_ib_uverbs_send_wr_1_rdma', - 'struct_ib_uverbs_send_wr_1_ud', 'struct_ib_uverbs_sge', - 'struct_ib_uverbs_tm_caps', 'struct_ib_uverbs_wc', - 'struct_ibv_ah', 'struct_ibv_ah_attr', 'struct_ibv_alloc_dm_attr', - 'struct_ibv_async_event', 'struct_ibv_comp_channel', - 'struct_ibv_context', 'struct_ibv_context_ops', - 'struct_ibv_counter_attach_attr', 'struct_ibv_counters', - 'struct_ibv_counters_init_attr', 'struct_ibv_cq', - 'struct_ibv_cq_ex', 'struct_ibv_cq_init_attr_ex', - 'struct_ibv_cq_moderation_caps', 'struct_ibv_data_buf', - 'struct_ibv_device', 'struct_ibv_device_attr', - 'struct_ibv_device_attr_ex', 'struct_ibv_dm', 'struct_ibv_ece', - 'struct_ibv_flow', 'struct_ibv_flow_action', - 'struct_ibv_flow_action_esp_attr', 'struct_ibv_flow_attr', - 'struct_ibv_flow_esp_filter', 'struct_ibv_flow_eth_filter', - 'struct_ibv_flow_gre_filter', 'struct_ibv_flow_ipv4_ext_filter', - 'struct_ibv_flow_ipv4_filter', 'struct_ibv_flow_ipv6_filter', - 'struct_ibv_flow_mpls_filter', 'struct_ibv_flow_spec', - 'struct_ibv_flow_spec_0_hdr', 'struct_ibv_flow_spec_action_drop', - 'struct_ibv_flow_spec_action_handle', - 'struct_ibv_flow_spec_action_tag', - 'struct_ibv_flow_spec_counter_action', 'struct_ibv_flow_spec_esp', - 'struct_ibv_flow_spec_eth', 'struct_ibv_flow_spec_gre', - 'struct_ibv_flow_spec_ipv4', 'struct_ibv_flow_spec_ipv4_ext', - 'struct_ibv_flow_spec_ipv6', 'struct_ibv_flow_spec_mpls', - 'struct_ibv_flow_spec_tcp_udp', 'struct_ibv_flow_spec_tunnel', - 'struct_ibv_flow_tcp_udp_filter', 'struct_ibv_flow_tunnel_filter', - 'struct_ibv_gid_entry', 'struct_ibv_gid_global', - 'struct_ibv_global_route', 'struct_ibv_grh', - 'struct_ibv_moderate_cq', 'struct_ibv_modify_cq_attr', - 'struct_ibv_mr', 'struct_ibv_mw', 'struct_ibv_mw_bind', - 'struct_ibv_mw_bind_info', 'struct_ibv_odp_caps', - 'struct_ibv_odp_caps_per_transport_caps', 'struct_ibv_ops_wr', - 'struct_ibv_ops_wr_0_add', 'struct_ibv_ops_wr_tm', - 'struct_ibv_packet_pacing_caps', - 'struct_ibv_parent_domain_init_attr', - 'struct_ibv_pci_atomic_caps', 'struct_ibv_pd', - 'struct_ibv_poll_cq_attr', 'struct_ibv_port_attr', - 'struct_ibv_qp', 'struct_ibv_qp_attr', 'struct_ibv_qp_cap', - 'struct_ibv_qp_ex', 'struct_ibv_qp_init_attr', - 'struct_ibv_qp_init_attr_ex', 'struct_ibv_qp_open_attr', - 'struct_ibv_qp_rate_limit_attr', - 'struct_ibv_query_device_ex_input', 'struct_ibv_recv_wr', - 'struct_ibv_rss_caps', 'struct_ibv_rwq_ind_table', - 'struct_ibv_rwq_ind_table_init_attr', 'struct_ibv_rx_hash_conf', - 'struct_ibv_send_wr', 'struct_ibv_send_wr_1_atomic', - 'struct_ibv_send_wr_1_rdma', 'struct_ibv_send_wr_1_ud', - 'struct_ibv_send_wr_2_xrc', 'struct_ibv_send_wr_3_bind_mw', - 'struct_ibv_send_wr_3_tso', 'struct_ibv_sge', 'struct_ibv_srq', - 'struct_ibv_srq_attr', 'struct_ibv_srq_init_attr', - 'struct_ibv_srq_init_attr_ex', 'struct_ibv_td', - 'struct_ibv_td_init_attr', 'struct_ibv_tm_cap', - 'struct_ibv_tm_caps', 'struct_ibv_tso_caps', - 'struct_ibv_values_ex', 'struct_ibv_wc', 'struct_ibv_wc_tm_info', - 'struct_ibv_wq', 'struct_ibv_wq_attr', 'struct_ibv_wq_init_attr', - 'struct_ibv_xrcd', 'struct_ibv_xrcd_init_attr', 'struct_timespec', - 'struct_verbs_context', 'struct_verbs_ex_private', 'uint16_t', - 'uint32_t', 'uint64_t', 'uint8_t', - 'union_c__UA___atomic_wide_counter', 'union_c__UA_pthread_cond_t', - 'union_c__UA_pthread_mutex_t', - 'union_ib_uverbs_flow_action_esp_encap_0', - 'union_ib_uverbs_flow_action_esp_encap_1', - 'union_ib_uverbs_flow_spec_action_count_0', - 'union_ib_uverbs_flow_spec_action_drop_0', - 'union_ib_uverbs_flow_spec_action_handle_0', - 'union_ib_uverbs_flow_spec_action_tag_0', - 'union_ib_uverbs_flow_spec_esp_0', - 'union_ib_uverbs_flow_spec_eth_0', - 'union_ib_uverbs_flow_spec_gre_0', - 'union_ib_uverbs_flow_spec_ipv4_0', - 'union_ib_uverbs_flow_spec_ipv6_0', - 'union_ib_uverbs_flow_spec_mpls_0', - 'union_ib_uverbs_flow_spec_tcp_udp_0', - 'union_ib_uverbs_flow_spec_tunnel_0', - 'union_ib_uverbs_send_wr_ex', 'union_ib_uverbs_send_wr_wr', - 'union_ib_uverbs_wc_ex', 'union_ibv_async_event_element', - 'union_ibv_flow_spec_0', 'union_ibv_gid', 'union_ibv_send_wr_0', - 'union_ibv_send_wr_3', 'union_ibv_send_wr_qp_type', - 'union_ibv_send_wr_wr', 'union_ibv_wc_0', 'verbs_get_ctx'] +class struct_ibv_gid_entry(Struct): pass +uint32_t = ctypes.c_uint32 +struct_ibv_gid_entry._fields_ = [ + ('gid', union_ibv_gid), + ('gid_index', uint32_t), + ('port_num', uint32_t), + ('gid_type', uint32_t), + ('ndev_ifindex', uint32_t), +] +enum_ibv_node_type = CEnum(ctypes.c_int32) +IBV_NODE_UNKNOWN = enum_ibv_node_type.define('IBV_NODE_UNKNOWN', -1) +IBV_NODE_CA = enum_ibv_node_type.define('IBV_NODE_CA', 1) +IBV_NODE_SWITCH = enum_ibv_node_type.define('IBV_NODE_SWITCH', 2) +IBV_NODE_ROUTER = enum_ibv_node_type.define('IBV_NODE_ROUTER', 3) +IBV_NODE_RNIC = enum_ibv_node_type.define('IBV_NODE_RNIC', 4) +IBV_NODE_USNIC = enum_ibv_node_type.define('IBV_NODE_USNIC', 5) +IBV_NODE_USNIC_UDP = enum_ibv_node_type.define('IBV_NODE_USNIC_UDP', 6) +IBV_NODE_UNSPECIFIED = enum_ibv_node_type.define('IBV_NODE_UNSPECIFIED', 7) + +enum_ibv_transport_type = CEnum(ctypes.c_int32) +IBV_TRANSPORT_UNKNOWN = enum_ibv_transport_type.define('IBV_TRANSPORT_UNKNOWN', -1) +IBV_TRANSPORT_IB = enum_ibv_transport_type.define('IBV_TRANSPORT_IB', 0) +IBV_TRANSPORT_IWARP = enum_ibv_transport_type.define('IBV_TRANSPORT_IWARP', 1) +IBV_TRANSPORT_USNIC = enum_ibv_transport_type.define('IBV_TRANSPORT_USNIC', 2) +IBV_TRANSPORT_USNIC_UDP = enum_ibv_transport_type.define('IBV_TRANSPORT_USNIC_UDP', 3) +IBV_TRANSPORT_UNSPECIFIED = enum_ibv_transport_type.define('IBV_TRANSPORT_UNSPECIFIED', 4) + +enum_ibv_device_cap_flags = CEnum(ctypes.c_uint32) +IBV_DEVICE_RESIZE_MAX_WR = enum_ibv_device_cap_flags.define('IBV_DEVICE_RESIZE_MAX_WR', 1) +IBV_DEVICE_BAD_PKEY_CNTR = enum_ibv_device_cap_flags.define('IBV_DEVICE_BAD_PKEY_CNTR', 2) +IBV_DEVICE_BAD_QKEY_CNTR = enum_ibv_device_cap_flags.define('IBV_DEVICE_BAD_QKEY_CNTR', 4) +IBV_DEVICE_RAW_MULTI = enum_ibv_device_cap_flags.define('IBV_DEVICE_RAW_MULTI', 8) +IBV_DEVICE_AUTO_PATH_MIG = enum_ibv_device_cap_flags.define('IBV_DEVICE_AUTO_PATH_MIG', 16) +IBV_DEVICE_CHANGE_PHY_PORT = enum_ibv_device_cap_flags.define('IBV_DEVICE_CHANGE_PHY_PORT', 32) +IBV_DEVICE_UD_AV_PORT_ENFORCE = enum_ibv_device_cap_flags.define('IBV_DEVICE_UD_AV_PORT_ENFORCE', 64) +IBV_DEVICE_CURR_QP_STATE_MOD = enum_ibv_device_cap_flags.define('IBV_DEVICE_CURR_QP_STATE_MOD', 128) +IBV_DEVICE_SHUTDOWN_PORT = enum_ibv_device_cap_flags.define('IBV_DEVICE_SHUTDOWN_PORT', 256) +IBV_DEVICE_INIT_TYPE = enum_ibv_device_cap_flags.define('IBV_DEVICE_INIT_TYPE', 512) +IBV_DEVICE_PORT_ACTIVE_EVENT = enum_ibv_device_cap_flags.define('IBV_DEVICE_PORT_ACTIVE_EVENT', 1024) +IBV_DEVICE_SYS_IMAGE_GUID = enum_ibv_device_cap_flags.define('IBV_DEVICE_SYS_IMAGE_GUID', 2048) +IBV_DEVICE_RC_RNR_NAK_GEN = enum_ibv_device_cap_flags.define('IBV_DEVICE_RC_RNR_NAK_GEN', 4096) +IBV_DEVICE_SRQ_RESIZE = enum_ibv_device_cap_flags.define('IBV_DEVICE_SRQ_RESIZE', 8192) +IBV_DEVICE_N_NOTIFY_CQ = enum_ibv_device_cap_flags.define('IBV_DEVICE_N_NOTIFY_CQ', 16384) +IBV_DEVICE_MEM_WINDOW = enum_ibv_device_cap_flags.define('IBV_DEVICE_MEM_WINDOW', 131072) +IBV_DEVICE_UD_IP_CSUM = enum_ibv_device_cap_flags.define('IBV_DEVICE_UD_IP_CSUM', 262144) +IBV_DEVICE_XRC = enum_ibv_device_cap_flags.define('IBV_DEVICE_XRC', 1048576) +IBV_DEVICE_MEM_MGT_EXTENSIONS = enum_ibv_device_cap_flags.define('IBV_DEVICE_MEM_MGT_EXTENSIONS', 2097152) +IBV_DEVICE_MEM_WINDOW_TYPE_2A = enum_ibv_device_cap_flags.define('IBV_DEVICE_MEM_WINDOW_TYPE_2A', 8388608) +IBV_DEVICE_MEM_WINDOW_TYPE_2B = enum_ibv_device_cap_flags.define('IBV_DEVICE_MEM_WINDOW_TYPE_2B', 16777216) +IBV_DEVICE_RC_IP_CSUM = enum_ibv_device_cap_flags.define('IBV_DEVICE_RC_IP_CSUM', 33554432) +IBV_DEVICE_RAW_IP_CSUM = enum_ibv_device_cap_flags.define('IBV_DEVICE_RAW_IP_CSUM', 67108864) +IBV_DEVICE_MANAGED_FLOW_STEERING = enum_ibv_device_cap_flags.define('IBV_DEVICE_MANAGED_FLOW_STEERING', 536870912) + +enum_ibv_fork_status = CEnum(ctypes.c_uint32) +IBV_FORK_DISABLED = enum_ibv_fork_status.define('IBV_FORK_DISABLED', 0) +IBV_FORK_ENABLED = enum_ibv_fork_status.define('IBV_FORK_ENABLED', 1) +IBV_FORK_UNNEEDED = enum_ibv_fork_status.define('IBV_FORK_UNNEEDED', 2) + +enum_ibv_atomic_cap = CEnum(ctypes.c_uint32) +IBV_ATOMIC_NONE = enum_ibv_atomic_cap.define('IBV_ATOMIC_NONE', 0) +IBV_ATOMIC_HCA = enum_ibv_atomic_cap.define('IBV_ATOMIC_HCA', 1) +IBV_ATOMIC_GLOB = enum_ibv_atomic_cap.define('IBV_ATOMIC_GLOB', 2) + +class struct_ibv_alloc_dm_attr(Struct): pass +size_t = ctypes.c_uint64 +struct_ibv_alloc_dm_attr._fields_ = [ + ('length', size_t), + ('log_align_req', uint32_t), + ('comp_mask', uint32_t), +] +enum_ibv_dm_mask = CEnum(ctypes.c_uint32) +IBV_DM_MASK_HANDLE = enum_ibv_dm_mask.define('IBV_DM_MASK_HANDLE', 1) + +class struct_ibv_dm(Struct): pass +class struct_ibv_context(Struct): pass +class struct_ibv_device(Struct): pass +class struct__ibv_device_ops(Struct): pass +struct__ibv_device_ops._fields_ = [ + ('_dummy1', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device), ctypes.c_int32)), + ('_dummy2', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_context))), +] +struct_ibv_device._fields_ = [ + ('_ops', struct__ibv_device_ops), + ('node_type', enum_ibv_node_type), + ('transport_type', enum_ibv_transport_type), + ('name', (ctypes.c_char * 64)), + ('dev_name', (ctypes.c_char * 64)), + ('dev_path', (ctypes.c_char * 256)), + ('ibdev_path', (ctypes.c_char * 256)), +] +class struct_ibv_context_ops(Struct): pass +class struct_ibv_device_attr(Struct): pass +uint64_t = ctypes.c_uint64 +uint16_t = ctypes.c_uint16 +struct_ibv_device_attr._fields_ = [ + ('fw_ver', (ctypes.c_char * 64)), + ('node_guid', ctypes.c_uint64), + ('sys_image_guid', ctypes.c_uint64), + ('max_mr_size', uint64_t), + ('page_size_cap', uint64_t), + ('vendor_id', uint32_t), + ('vendor_part_id', uint32_t), + ('hw_ver', uint32_t), + ('max_qp', ctypes.c_int32), + ('max_qp_wr', ctypes.c_int32), + ('device_cap_flags', ctypes.c_uint32), + ('max_sge', ctypes.c_int32), + ('max_sge_rd', ctypes.c_int32), + ('max_cq', ctypes.c_int32), + ('max_cqe', ctypes.c_int32), + ('max_mr', ctypes.c_int32), + ('max_pd', ctypes.c_int32), + ('max_qp_rd_atom', ctypes.c_int32), + ('max_ee_rd_atom', ctypes.c_int32), + ('max_res_rd_atom', ctypes.c_int32), + ('max_qp_init_rd_atom', ctypes.c_int32), + ('max_ee_init_rd_atom', ctypes.c_int32), + ('atomic_cap', enum_ibv_atomic_cap), + ('max_ee', ctypes.c_int32), + ('max_rdd', ctypes.c_int32), + ('max_mw', ctypes.c_int32), + ('max_raw_ipv6_qp', ctypes.c_int32), + ('max_raw_ethy_qp', ctypes.c_int32), + ('max_mcast_grp', ctypes.c_int32), + ('max_mcast_qp_attach', ctypes.c_int32), + ('max_total_mcast_qp_attach', ctypes.c_int32), + ('max_ah', ctypes.c_int32), + ('max_fmr', ctypes.c_int32), + ('max_map_per_fmr', ctypes.c_int32), + ('max_srq', ctypes.c_int32), + ('max_srq_wr', ctypes.c_int32), + ('max_srq_sge', ctypes.c_int32), + ('max_pkeys', uint16_t), + ('local_ca_ack_delay', uint8_t), + ('phys_port_cnt', uint8_t), +] +class struct__compat_ibv_port_attr(Struct): pass +class struct_ibv_mw(Struct): pass +class struct_ibv_pd(Struct): pass +struct_ibv_pd._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('handle', uint32_t), +] +enum_ibv_mw_type = CEnum(ctypes.c_uint32) +IBV_MW_TYPE_1 = enum_ibv_mw_type.define('IBV_MW_TYPE_1', 1) +IBV_MW_TYPE_2 = enum_ibv_mw_type.define('IBV_MW_TYPE_2', 2) + +struct_ibv_mw._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('rkey', uint32_t), + ('handle', uint32_t), + ('type', enum_ibv_mw_type), +] +class struct_ibv_qp(Struct): pass +class struct_ibv_cq(Struct): pass +class struct_ibv_comp_channel(Struct): pass +struct_ibv_comp_channel._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('fd', ctypes.c_int32), + ('refcnt', ctypes.c_int32), +] +class pthread_mutex_t(ctypes.Union): pass +class struct___pthread_mutex_s(Struct): pass +class struct___pthread_internal_list(Struct): pass +__pthread_list_t = struct___pthread_internal_list +struct___pthread_internal_list._fields_ = [ + ('__prev', ctypes.POINTER(struct___pthread_internal_list)), + ('__next', ctypes.POINTER(struct___pthread_internal_list)), +] +struct___pthread_mutex_s._fields_ = [ + ('__lock', ctypes.c_int32), + ('__count', ctypes.c_uint32), + ('__owner', ctypes.c_int32), + ('__nusers', ctypes.c_uint32), + ('__kind', ctypes.c_int32), + ('__spins', ctypes.c_int16), + ('__elision', ctypes.c_int16), + ('__list', struct___pthread_internal_list), +] +pthread_mutex_t._fields_ = [ + ('__data', struct___pthread_mutex_s), + ('__size', (ctypes.c_char * 40)), + ('__align', ctypes.c_int64), +] +class pthread_cond_t(ctypes.Union): pass +class struct___pthread_cond_s(Struct): pass +class __atomic_wide_counter(ctypes.Union): pass +class __atomic_wide_counter___value32(Struct): pass +__atomic_wide_counter___value32._fields_ = [ + ('__low', ctypes.c_uint32), + ('__high', ctypes.c_uint32), +] +__atomic_wide_counter._fields_ = [ + ('__value64', ctypes.c_uint64), + ('__value32', __atomic_wide_counter___value32), +] +struct___pthread_cond_s._fields_ = [ + ('__wseq', __atomic_wide_counter), + ('__g1_start', __atomic_wide_counter), + ('__g_refs', (ctypes.c_uint32 * 2)), + ('__g_size', (ctypes.c_uint32 * 2)), + ('__g1_orig_size', ctypes.c_uint32), + ('__wrefs', ctypes.c_uint32), + ('__g_signals', (ctypes.c_uint32 * 2)), +] +pthread_cond_t._fields_ = [ + ('__data', struct___pthread_cond_s), + ('__size', (ctypes.c_char * 48)), + ('__align', ctypes.c_int64), +] +struct_ibv_cq._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('channel', ctypes.POINTER(struct_ibv_comp_channel)), + ('cq_context', ctypes.c_void_p), + ('handle', uint32_t), + ('cqe', ctypes.c_int32), + ('mutex', pthread_mutex_t), + ('cond', pthread_cond_t), + ('comp_events_completed', uint32_t), + ('async_events_completed', uint32_t), +] +class struct_ibv_srq(Struct): pass +struct_ibv_srq._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('srq_context', ctypes.c_void_p), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('handle', uint32_t), + ('mutex', pthread_mutex_t), + ('cond', pthread_cond_t), + ('events_completed', uint32_t), +] +enum_ibv_qp_state = CEnum(ctypes.c_uint32) +IBV_QPS_RESET = enum_ibv_qp_state.define('IBV_QPS_RESET', 0) +IBV_QPS_INIT = enum_ibv_qp_state.define('IBV_QPS_INIT', 1) +IBV_QPS_RTR = enum_ibv_qp_state.define('IBV_QPS_RTR', 2) +IBV_QPS_RTS = enum_ibv_qp_state.define('IBV_QPS_RTS', 3) +IBV_QPS_SQD = enum_ibv_qp_state.define('IBV_QPS_SQD', 4) +IBV_QPS_SQE = enum_ibv_qp_state.define('IBV_QPS_SQE', 5) +IBV_QPS_ERR = enum_ibv_qp_state.define('IBV_QPS_ERR', 6) +IBV_QPS_UNKNOWN = enum_ibv_qp_state.define('IBV_QPS_UNKNOWN', 7) + +enum_ibv_qp_type = CEnum(ctypes.c_uint32) +IBV_QPT_RC = enum_ibv_qp_type.define('IBV_QPT_RC', 2) +IBV_QPT_UC = enum_ibv_qp_type.define('IBV_QPT_UC', 3) +IBV_QPT_UD = enum_ibv_qp_type.define('IBV_QPT_UD', 4) +IBV_QPT_RAW_PACKET = enum_ibv_qp_type.define('IBV_QPT_RAW_PACKET', 8) +IBV_QPT_XRC_SEND = enum_ibv_qp_type.define('IBV_QPT_XRC_SEND', 9) +IBV_QPT_XRC_RECV = enum_ibv_qp_type.define('IBV_QPT_XRC_RECV', 10) +IBV_QPT_DRIVER = enum_ibv_qp_type.define('IBV_QPT_DRIVER', 255) + +struct_ibv_qp._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('qp_context', ctypes.c_void_p), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('send_cq', ctypes.POINTER(struct_ibv_cq)), + ('recv_cq', ctypes.POINTER(struct_ibv_cq)), + ('srq', ctypes.POINTER(struct_ibv_srq)), + ('handle', uint32_t), + ('qp_num', uint32_t), + ('state', enum_ibv_qp_state), + ('qp_type', enum_ibv_qp_type), + ('mutex', pthread_mutex_t), + ('cond', pthread_cond_t), + ('events_completed', uint32_t), +] +class struct_ibv_mw_bind(Struct): pass +class struct_ibv_mw_bind_info(Struct): pass +class struct_ibv_mr(Struct): pass +struct_ibv_mr._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('addr', ctypes.c_void_p), + ('length', size_t), + ('handle', uint32_t), + ('lkey', uint32_t), + ('rkey', uint32_t), +] +struct_ibv_mw_bind_info._fields_ = [ + ('mr', ctypes.POINTER(struct_ibv_mr)), + ('addr', uint64_t), + ('length', uint64_t), + ('mw_access_flags', ctypes.c_uint32), +] +struct_ibv_mw_bind._fields_ = [ + ('wr_id', uint64_t), + ('send_flags', ctypes.c_uint32), + ('bind_info', struct_ibv_mw_bind_info), +] +class struct_ibv_wc(Struct): pass +enum_ibv_wc_status = CEnum(ctypes.c_uint32) +IBV_WC_SUCCESS = enum_ibv_wc_status.define('IBV_WC_SUCCESS', 0) +IBV_WC_LOC_LEN_ERR = enum_ibv_wc_status.define('IBV_WC_LOC_LEN_ERR', 1) +IBV_WC_LOC_QP_OP_ERR = enum_ibv_wc_status.define('IBV_WC_LOC_QP_OP_ERR', 2) +IBV_WC_LOC_EEC_OP_ERR = enum_ibv_wc_status.define('IBV_WC_LOC_EEC_OP_ERR', 3) +IBV_WC_LOC_PROT_ERR = enum_ibv_wc_status.define('IBV_WC_LOC_PROT_ERR', 4) +IBV_WC_WR_FLUSH_ERR = enum_ibv_wc_status.define('IBV_WC_WR_FLUSH_ERR', 5) +IBV_WC_MW_BIND_ERR = enum_ibv_wc_status.define('IBV_WC_MW_BIND_ERR', 6) +IBV_WC_BAD_RESP_ERR = enum_ibv_wc_status.define('IBV_WC_BAD_RESP_ERR', 7) +IBV_WC_LOC_ACCESS_ERR = enum_ibv_wc_status.define('IBV_WC_LOC_ACCESS_ERR', 8) +IBV_WC_REM_INV_REQ_ERR = enum_ibv_wc_status.define('IBV_WC_REM_INV_REQ_ERR', 9) +IBV_WC_REM_ACCESS_ERR = enum_ibv_wc_status.define('IBV_WC_REM_ACCESS_ERR', 10) +IBV_WC_REM_OP_ERR = enum_ibv_wc_status.define('IBV_WC_REM_OP_ERR', 11) +IBV_WC_RETRY_EXC_ERR = enum_ibv_wc_status.define('IBV_WC_RETRY_EXC_ERR', 12) +IBV_WC_RNR_RETRY_EXC_ERR = enum_ibv_wc_status.define('IBV_WC_RNR_RETRY_EXC_ERR', 13) +IBV_WC_LOC_RDD_VIOL_ERR = enum_ibv_wc_status.define('IBV_WC_LOC_RDD_VIOL_ERR', 14) +IBV_WC_REM_INV_RD_REQ_ERR = enum_ibv_wc_status.define('IBV_WC_REM_INV_RD_REQ_ERR', 15) +IBV_WC_REM_ABORT_ERR = enum_ibv_wc_status.define('IBV_WC_REM_ABORT_ERR', 16) +IBV_WC_INV_EECN_ERR = enum_ibv_wc_status.define('IBV_WC_INV_EECN_ERR', 17) +IBV_WC_INV_EEC_STATE_ERR = enum_ibv_wc_status.define('IBV_WC_INV_EEC_STATE_ERR', 18) +IBV_WC_FATAL_ERR = enum_ibv_wc_status.define('IBV_WC_FATAL_ERR', 19) +IBV_WC_RESP_TIMEOUT_ERR = enum_ibv_wc_status.define('IBV_WC_RESP_TIMEOUT_ERR', 20) +IBV_WC_GENERAL_ERR = enum_ibv_wc_status.define('IBV_WC_GENERAL_ERR', 21) +IBV_WC_TM_ERR = enum_ibv_wc_status.define('IBV_WC_TM_ERR', 22) +IBV_WC_TM_RNDV_INCOMPLETE = enum_ibv_wc_status.define('IBV_WC_TM_RNDV_INCOMPLETE', 23) + +enum_ibv_wc_opcode = CEnum(ctypes.c_uint32) +IBV_WC_SEND = enum_ibv_wc_opcode.define('IBV_WC_SEND', 0) +IBV_WC_RDMA_WRITE = enum_ibv_wc_opcode.define('IBV_WC_RDMA_WRITE', 1) +IBV_WC_RDMA_READ = enum_ibv_wc_opcode.define('IBV_WC_RDMA_READ', 2) +IBV_WC_COMP_SWAP = enum_ibv_wc_opcode.define('IBV_WC_COMP_SWAP', 3) +IBV_WC_FETCH_ADD = enum_ibv_wc_opcode.define('IBV_WC_FETCH_ADD', 4) +IBV_WC_BIND_MW = enum_ibv_wc_opcode.define('IBV_WC_BIND_MW', 5) +IBV_WC_LOCAL_INV = enum_ibv_wc_opcode.define('IBV_WC_LOCAL_INV', 6) +IBV_WC_TSO = enum_ibv_wc_opcode.define('IBV_WC_TSO', 7) +IBV_WC_FLUSH = enum_ibv_wc_opcode.define('IBV_WC_FLUSH', 8) +IBV_WC_ATOMIC_WRITE = enum_ibv_wc_opcode.define('IBV_WC_ATOMIC_WRITE', 9) +IBV_WC_RECV = enum_ibv_wc_opcode.define('IBV_WC_RECV', 128) +IBV_WC_RECV_RDMA_WITH_IMM = enum_ibv_wc_opcode.define('IBV_WC_RECV_RDMA_WITH_IMM', 129) +IBV_WC_TM_ADD = enum_ibv_wc_opcode.define('IBV_WC_TM_ADD', 130) +IBV_WC_TM_DEL = enum_ibv_wc_opcode.define('IBV_WC_TM_DEL', 131) +IBV_WC_TM_SYNC = enum_ibv_wc_opcode.define('IBV_WC_TM_SYNC', 132) +IBV_WC_TM_RECV = enum_ibv_wc_opcode.define('IBV_WC_TM_RECV', 133) +IBV_WC_TM_NO_TAG = enum_ibv_wc_opcode.define('IBV_WC_TM_NO_TAG', 134) +IBV_WC_DRIVER1 = enum_ibv_wc_opcode.define('IBV_WC_DRIVER1', 135) +IBV_WC_DRIVER2 = enum_ibv_wc_opcode.define('IBV_WC_DRIVER2', 136) +IBV_WC_DRIVER3 = enum_ibv_wc_opcode.define('IBV_WC_DRIVER3', 137) + +class struct_ibv_wc_0(ctypes.Union): pass +__be32 = ctypes.c_uint32 +struct_ibv_wc_0._fields_ = [ + ('imm_data', ctypes.c_uint32), + ('invalidated_rkey', uint32_t), +] +struct_ibv_wc._anonymous_ = ['_0'] +struct_ibv_wc._fields_ = [ + ('wr_id', uint64_t), + ('status', enum_ibv_wc_status), + ('opcode', enum_ibv_wc_opcode), + ('vendor_err', uint32_t), + ('byte_len', uint32_t), + ('_0', struct_ibv_wc_0), + ('qp_num', uint32_t), + ('src_qp', uint32_t), + ('wc_flags', ctypes.c_uint32), + ('pkey_index', uint16_t), + ('slid', uint16_t), + ('sl', uint8_t), + ('dlid_path_bits', uint8_t), +] +class struct_ibv_recv_wr(Struct): pass +class struct_ibv_sge(Struct): pass +struct_ibv_sge._fields_ = [ + ('addr', uint64_t), + ('length', uint32_t), + ('lkey', uint32_t), +] +struct_ibv_recv_wr._fields_ = [ + ('wr_id', uint64_t), + ('next', ctypes.POINTER(struct_ibv_recv_wr)), + ('sg_list', ctypes.POINTER(struct_ibv_sge)), + ('num_sge', ctypes.c_int32), +] +class struct_ibv_send_wr(Struct): pass +enum_ibv_wr_opcode = CEnum(ctypes.c_uint32) +IBV_WR_RDMA_WRITE = enum_ibv_wr_opcode.define('IBV_WR_RDMA_WRITE', 0) +IBV_WR_RDMA_WRITE_WITH_IMM = enum_ibv_wr_opcode.define('IBV_WR_RDMA_WRITE_WITH_IMM', 1) +IBV_WR_SEND = enum_ibv_wr_opcode.define('IBV_WR_SEND', 2) +IBV_WR_SEND_WITH_IMM = enum_ibv_wr_opcode.define('IBV_WR_SEND_WITH_IMM', 3) +IBV_WR_RDMA_READ = enum_ibv_wr_opcode.define('IBV_WR_RDMA_READ', 4) +IBV_WR_ATOMIC_CMP_AND_SWP = enum_ibv_wr_opcode.define('IBV_WR_ATOMIC_CMP_AND_SWP', 5) +IBV_WR_ATOMIC_FETCH_AND_ADD = enum_ibv_wr_opcode.define('IBV_WR_ATOMIC_FETCH_AND_ADD', 6) +IBV_WR_LOCAL_INV = enum_ibv_wr_opcode.define('IBV_WR_LOCAL_INV', 7) +IBV_WR_BIND_MW = enum_ibv_wr_opcode.define('IBV_WR_BIND_MW', 8) +IBV_WR_SEND_WITH_INV = enum_ibv_wr_opcode.define('IBV_WR_SEND_WITH_INV', 9) +IBV_WR_TSO = enum_ibv_wr_opcode.define('IBV_WR_TSO', 10) +IBV_WR_DRIVER1 = enum_ibv_wr_opcode.define('IBV_WR_DRIVER1', 11) +IBV_WR_FLUSH = enum_ibv_wr_opcode.define('IBV_WR_FLUSH', 14) +IBV_WR_ATOMIC_WRITE = enum_ibv_wr_opcode.define('IBV_WR_ATOMIC_WRITE', 15) + +class struct_ibv_send_wr_0(ctypes.Union): pass +struct_ibv_send_wr_0._fields_ = [ + ('imm_data', ctypes.c_uint32), + ('invalidate_rkey', uint32_t), +] +class struct_ibv_send_wr_wr(ctypes.Union): pass +class struct_ibv_send_wr_wr_rdma(Struct): pass +struct_ibv_send_wr_wr_rdma._fields_ = [ + ('remote_addr', uint64_t), + ('rkey', uint32_t), +] +class struct_ibv_send_wr_wr_atomic(Struct): pass +struct_ibv_send_wr_wr_atomic._fields_ = [ + ('remote_addr', uint64_t), + ('compare_add', uint64_t), + ('swap', uint64_t), + ('rkey', uint32_t), +] +class struct_ibv_send_wr_wr_ud(Struct): pass +class struct_ibv_ah(Struct): pass +struct_ibv_ah._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('handle', uint32_t), +] +struct_ibv_send_wr_wr_ud._fields_ = [ + ('ah', ctypes.POINTER(struct_ibv_ah)), + ('remote_qpn', uint32_t), + ('remote_qkey', uint32_t), +] +struct_ibv_send_wr_wr._fields_ = [ + ('rdma', struct_ibv_send_wr_wr_rdma), + ('atomic', struct_ibv_send_wr_wr_atomic), + ('ud', struct_ibv_send_wr_wr_ud), +] +class struct_ibv_send_wr_qp_type(ctypes.Union): pass +class struct_ibv_send_wr_qp_type_xrc(Struct): pass +struct_ibv_send_wr_qp_type_xrc._fields_ = [ + ('remote_srqn', uint32_t), +] +struct_ibv_send_wr_qp_type._fields_ = [ + ('xrc', struct_ibv_send_wr_qp_type_xrc), +] +class struct_ibv_send_wr_1(ctypes.Union): pass +class struct_ibv_send_wr_1_bind_mw(Struct): pass +struct_ibv_send_wr_1_bind_mw._fields_ = [ + ('mw', ctypes.POINTER(struct_ibv_mw)), + ('rkey', uint32_t), + ('bind_info', struct_ibv_mw_bind_info), +] +class struct_ibv_send_wr_1_tso(Struct): pass +struct_ibv_send_wr_1_tso._fields_ = [ + ('hdr', ctypes.c_void_p), + ('hdr_sz', uint16_t), + ('mss', uint16_t), +] +struct_ibv_send_wr_1._fields_ = [ + ('bind_mw', struct_ibv_send_wr_1_bind_mw), + ('tso', struct_ibv_send_wr_1_tso), +] +struct_ibv_send_wr._anonymous_ = ['_0', '_1'] +struct_ibv_send_wr._fields_ = [ + ('wr_id', uint64_t), + ('next', ctypes.POINTER(struct_ibv_send_wr)), + ('sg_list', ctypes.POINTER(struct_ibv_sge)), + ('num_sge', ctypes.c_int32), + ('opcode', enum_ibv_wr_opcode), + ('send_flags', ctypes.c_uint32), + ('_0', struct_ibv_send_wr_0), + ('wr', struct_ibv_send_wr_wr), + ('qp_type', struct_ibv_send_wr_qp_type), + ('_1', struct_ibv_send_wr_1), +] +struct_ibv_context_ops._fields_ = [ + ('_compat_query_device', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device_attr))), + ('_compat_query_port', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct__compat_ibv_port_attr))), + ('_compat_alloc_pd', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_dealloc_pd', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_reg_mr', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_rereg_mr', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_dereg_mr', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('alloc_mw', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_pd), enum_ibv_mw_type)), + ('bind_mw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_mw_bind))), + ('dealloc_mw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_mw))), + ('_compat_create_cq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('poll_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.c_int32, ctypes.POINTER(struct_ibv_wc))), + ('req_notify_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.c_int32)), + ('_compat_cq_event', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_resize_cq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_destroy_cq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_create_srq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_modify_srq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_query_srq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_destroy_srq', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('post_srq_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), + ('_compat_create_qp', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_query_qp', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_modify_qp', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_destroy_qp', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('post_send', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_send_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_send_wr)))), + ('post_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), + ('_compat_create_ah', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_destroy_ah', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_attach_mcast', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_detach_mcast', ctypes.CFUNCTYPE(ctypes.c_void_p, )), + ('_compat_async_event', ctypes.CFUNCTYPE(ctypes.c_void_p, )), +] +struct_ibv_context._fields_ = [ + ('device', ctypes.POINTER(struct_ibv_device)), + ('ops', struct_ibv_context_ops), + ('cmd_fd', ctypes.c_int32), + ('async_fd', ctypes.c_int32), + ('num_comp_vectors', ctypes.c_int32), + ('mutex', pthread_mutex_t), + ('abi_compat', ctypes.c_void_p), +] +struct_ibv_dm._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('memcpy_to_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_dm), uint64_t, ctypes.c_void_p, size_t)), + ('memcpy_from_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_void_p, ctypes.POINTER(struct_ibv_dm), uint64_t, size_t)), + ('comp_mask', uint32_t), + ('handle', uint32_t), +] +class struct_ibv_query_device_ex_input(Struct): pass +struct_ibv_query_device_ex_input._fields_ = [ + ('comp_mask', uint32_t), +] +enum_ibv_odp_transport_cap_bits = CEnum(ctypes.c_uint32) +IBV_ODP_SUPPORT_SEND = enum_ibv_odp_transport_cap_bits.define('IBV_ODP_SUPPORT_SEND', 1) +IBV_ODP_SUPPORT_RECV = enum_ibv_odp_transport_cap_bits.define('IBV_ODP_SUPPORT_RECV', 2) +IBV_ODP_SUPPORT_WRITE = enum_ibv_odp_transport_cap_bits.define('IBV_ODP_SUPPORT_WRITE', 4) +IBV_ODP_SUPPORT_READ = enum_ibv_odp_transport_cap_bits.define('IBV_ODP_SUPPORT_READ', 8) +IBV_ODP_SUPPORT_ATOMIC = enum_ibv_odp_transport_cap_bits.define('IBV_ODP_SUPPORT_ATOMIC', 16) +IBV_ODP_SUPPORT_SRQ_RECV = enum_ibv_odp_transport_cap_bits.define('IBV_ODP_SUPPORT_SRQ_RECV', 32) + +class struct_ibv_odp_caps(Struct): pass +class struct_ibv_odp_caps_per_transport_caps(Struct): pass +struct_ibv_odp_caps_per_transport_caps._fields_ = [ + ('rc_odp_caps', uint32_t), + ('uc_odp_caps', uint32_t), + ('ud_odp_caps', uint32_t), +] +struct_ibv_odp_caps._fields_ = [ + ('general_caps', uint64_t), + ('per_transport_caps', struct_ibv_odp_caps_per_transport_caps), +] +enum_ibv_odp_general_caps = CEnum(ctypes.c_uint32) +IBV_ODP_SUPPORT = enum_ibv_odp_general_caps.define('IBV_ODP_SUPPORT', 1) +IBV_ODP_SUPPORT_IMPLICIT = enum_ibv_odp_general_caps.define('IBV_ODP_SUPPORT_IMPLICIT', 2) + +class struct_ibv_tso_caps(Struct): pass +struct_ibv_tso_caps._fields_ = [ + ('max_tso', uint32_t), + ('supported_qpts', uint32_t), +] +enum_ibv_rx_hash_function_flags = CEnum(ctypes.c_uint32) +IBV_RX_HASH_FUNC_TOEPLITZ = enum_ibv_rx_hash_function_flags.define('IBV_RX_HASH_FUNC_TOEPLITZ', 1) + +enum_ibv_rx_hash_fields = CEnum(ctypes.c_uint32) +IBV_RX_HASH_SRC_IPV4 = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_SRC_IPV4', 1) +IBV_RX_HASH_DST_IPV4 = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_DST_IPV4', 2) +IBV_RX_HASH_SRC_IPV6 = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_SRC_IPV6', 4) +IBV_RX_HASH_DST_IPV6 = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_DST_IPV6', 8) +IBV_RX_HASH_SRC_PORT_TCP = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_SRC_PORT_TCP', 16) +IBV_RX_HASH_DST_PORT_TCP = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_DST_PORT_TCP', 32) +IBV_RX_HASH_SRC_PORT_UDP = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_SRC_PORT_UDP', 64) +IBV_RX_HASH_DST_PORT_UDP = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_DST_PORT_UDP', 128) +IBV_RX_HASH_IPSEC_SPI = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_IPSEC_SPI', 256) +IBV_RX_HASH_INNER = enum_ibv_rx_hash_fields.define('IBV_RX_HASH_INNER', 2147483648) + +class struct_ibv_rss_caps(Struct): pass +struct_ibv_rss_caps._fields_ = [ + ('supported_qpts', uint32_t), + ('max_rwq_indirection_tables', uint32_t), + ('max_rwq_indirection_table_size', uint32_t), + ('rx_hash_fields_mask', uint64_t), + ('rx_hash_function', uint8_t), +] +class struct_ibv_packet_pacing_caps(Struct): pass +struct_ibv_packet_pacing_caps._fields_ = [ + ('qp_rate_limit_min', uint32_t), + ('qp_rate_limit_max', uint32_t), + ('supported_qpts', uint32_t), +] +enum_ibv_raw_packet_caps = CEnum(ctypes.c_uint32) +IBV_RAW_PACKET_CAP_CVLAN_STRIPPING = enum_ibv_raw_packet_caps.define('IBV_RAW_PACKET_CAP_CVLAN_STRIPPING', 1) +IBV_RAW_PACKET_CAP_SCATTER_FCS = enum_ibv_raw_packet_caps.define('IBV_RAW_PACKET_CAP_SCATTER_FCS', 2) +IBV_RAW_PACKET_CAP_IP_CSUM = enum_ibv_raw_packet_caps.define('IBV_RAW_PACKET_CAP_IP_CSUM', 4) +IBV_RAW_PACKET_CAP_DELAY_DROP = enum_ibv_raw_packet_caps.define('IBV_RAW_PACKET_CAP_DELAY_DROP', 8) + +enum_ibv_tm_cap_flags = CEnum(ctypes.c_uint32) +IBV_TM_CAP_RC = enum_ibv_tm_cap_flags.define('IBV_TM_CAP_RC', 1) + +class struct_ibv_tm_caps(Struct): pass +struct_ibv_tm_caps._fields_ = [ + ('max_rndv_hdr_size', uint32_t), + ('max_num_tags', uint32_t), + ('flags', uint32_t), + ('max_ops', uint32_t), + ('max_sge', uint32_t), +] +class struct_ibv_cq_moderation_caps(Struct): pass +struct_ibv_cq_moderation_caps._fields_ = [ + ('max_cq_count', uint16_t), + ('max_cq_period', uint16_t), +] +enum_ibv_pci_atomic_op_size = CEnum(ctypes.c_uint32) +IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP = enum_ibv_pci_atomic_op_size.define('IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP', 1) +IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP = enum_ibv_pci_atomic_op_size.define('IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP', 2) +IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP = enum_ibv_pci_atomic_op_size.define('IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP', 4) + +class struct_ibv_pci_atomic_caps(Struct): pass +struct_ibv_pci_atomic_caps._fields_ = [ + ('fetch_add', uint16_t), + ('swap', uint16_t), + ('compare_swap', uint16_t), +] +class struct_ibv_device_attr_ex(Struct): pass +struct_ibv_device_attr_ex._fields_ = [ + ('orig_attr', struct_ibv_device_attr), + ('comp_mask', uint32_t), + ('odp_caps', struct_ibv_odp_caps), + ('completion_timestamp_mask', uint64_t), + ('hca_core_clock', uint64_t), + ('device_cap_flags_ex', uint64_t), + ('tso_caps', struct_ibv_tso_caps), + ('rss_caps', struct_ibv_rss_caps), + ('max_wq_type_rq', uint32_t), + ('packet_pacing_caps', struct_ibv_packet_pacing_caps), + ('raw_packet_caps', uint32_t), + ('tm_caps', struct_ibv_tm_caps), + ('cq_mod_caps', struct_ibv_cq_moderation_caps), + ('max_dm_size', uint64_t), + ('pci_atomic_caps', struct_ibv_pci_atomic_caps), + ('xrc_odp_caps', uint32_t), + ('phys_port_cnt_ex', uint32_t), +] +enum_ibv_mtu = CEnum(ctypes.c_uint32) +IBV_MTU_256 = enum_ibv_mtu.define('IBV_MTU_256', 1) +IBV_MTU_512 = enum_ibv_mtu.define('IBV_MTU_512', 2) +IBV_MTU_1024 = enum_ibv_mtu.define('IBV_MTU_1024', 3) +IBV_MTU_2048 = enum_ibv_mtu.define('IBV_MTU_2048', 4) +IBV_MTU_4096 = enum_ibv_mtu.define('IBV_MTU_4096', 5) + +enum_ibv_port_state = CEnum(ctypes.c_uint32) +IBV_PORT_NOP = enum_ibv_port_state.define('IBV_PORT_NOP', 0) +IBV_PORT_DOWN = enum_ibv_port_state.define('IBV_PORT_DOWN', 1) +IBV_PORT_INIT = enum_ibv_port_state.define('IBV_PORT_INIT', 2) +IBV_PORT_ARMED = enum_ibv_port_state.define('IBV_PORT_ARMED', 3) +IBV_PORT_ACTIVE = enum_ibv_port_state.define('IBV_PORT_ACTIVE', 4) +IBV_PORT_ACTIVE_DEFER = enum_ibv_port_state.define('IBV_PORT_ACTIVE_DEFER', 5) + +_anonenum0 = CEnum(ctypes.c_uint32) +IBV_LINK_LAYER_UNSPECIFIED = _anonenum0.define('IBV_LINK_LAYER_UNSPECIFIED', 0) +IBV_LINK_LAYER_INFINIBAND = _anonenum0.define('IBV_LINK_LAYER_INFINIBAND', 1) +IBV_LINK_LAYER_ETHERNET = _anonenum0.define('IBV_LINK_LAYER_ETHERNET', 2) + +enum_ibv_port_cap_flags = CEnum(ctypes.c_uint32) +IBV_PORT_SM = enum_ibv_port_cap_flags.define('IBV_PORT_SM', 2) +IBV_PORT_NOTICE_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_NOTICE_SUP', 4) +IBV_PORT_TRAP_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_TRAP_SUP', 8) +IBV_PORT_OPT_IPD_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_OPT_IPD_SUP', 16) +IBV_PORT_AUTO_MIGR_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_AUTO_MIGR_SUP', 32) +IBV_PORT_SL_MAP_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_SL_MAP_SUP', 64) +IBV_PORT_MKEY_NVRAM = enum_ibv_port_cap_flags.define('IBV_PORT_MKEY_NVRAM', 128) +IBV_PORT_PKEY_NVRAM = enum_ibv_port_cap_flags.define('IBV_PORT_PKEY_NVRAM', 256) +IBV_PORT_LED_INFO_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_LED_INFO_SUP', 512) +IBV_PORT_SYS_IMAGE_GUID_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_SYS_IMAGE_GUID_SUP', 2048) +IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP', 4096) +IBV_PORT_EXTENDED_SPEEDS_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_EXTENDED_SPEEDS_SUP', 16384) +IBV_PORT_CAP_MASK2_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_CAP_MASK2_SUP', 32768) +IBV_PORT_CM_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_CM_SUP', 65536) +IBV_PORT_SNMP_TUNNEL_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_SNMP_TUNNEL_SUP', 131072) +IBV_PORT_REINIT_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_REINIT_SUP', 262144) +IBV_PORT_DEVICE_MGMT_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_DEVICE_MGMT_SUP', 524288) +IBV_PORT_VENDOR_CLASS_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_VENDOR_CLASS_SUP', 1048576) +IBV_PORT_DR_NOTICE_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_DR_NOTICE_SUP', 2097152) +IBV_PORT_CAP_MASK_NOTICE_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_CAP_MASK_NOTICE_SUP', 4194304) +IBV_PORT_BOOT_MGMT_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_BOOT_MGMT_SUP', 8388608) +IBV_PORT_LINK_LATENCY_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_LINK_LATENCY_SUP', 16777216) +IBV_PORT_CLIENT_REG_SUP = enum_ibv_port_cap_flags.define('IBV_PORT_CLIENT_REG_SUP', 33554432) +IBV_PORT_IP_BASED_GIDS = enum_ibv_port_cap_flags.define('IBV_PORT_IP_BASED_GIDS', 67108864) + +enum_ibv_port_cap_flags2 = CEnum(ctypes.c_uint32) +IBV_PORT_SET_NODE_DESC_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_SET_NODE_DESC_SUP', 1) +IBV_PORT_INFO_EXT_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_INFO_EXT_SUP', 2) +IBV_PORT_VIRT_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_VIRT_SUP', 4) +IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP', 8) +IBV_PORT_LINK_WIDTH_2X_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_LINK_WIDTH_2X_SUP', 16) +IBV_PORT_LINK_SPEED_HDR_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_LINK_SPEED_HDR_SUP', 32) +IBV_PORT_LINK_SPEED_NDR_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_LINK_SPEED_NDR_SUP', 1024) +IBV_PORT_LINK_SPEED_XDR_SUP = enum_ibv_port_cap_flags2.define('IBV_PORT_LINK_SPEED_XDR_SUP', 4096) + +class struct_ibv_port_attr(Struct): pass +struct_ibv_port_attr._fields_ = [ + ('state', enum_ibv_port_state), + ('max_mtu', enum_ibv_mtu), + ('active_mtu', enum_ibv_mtu), + ('gid_tbl_len', ctypes.c_int32), + ('port_cap_flags', uint32_t), + ('max_msg_sz', uint32_t), + ('bad_pkey_cntr', uint32_t), + ('qkey_viol_cntr', uint32_t), + ('pkey_tbl_len', uint16_t), + ('lid', uint16_t), + ('sm_lid', uint16_t), + ('lmc', uint8_t), + ('max_vl_num', uint8_t), + ('sm_sl', uint8_t), + ('subnet_timeout', uint8_t), + ('init_type_reply', uint8_t), + ('active_width', uint8_t), + ('active_speed', uint8_t), + ('phys_state', uint8_t), + ('link_layer', uint8_t), + ('flags', uint8_t), + ('port_cap_flags2', uint16_t), + ('active_speed_ex', uint32_t), +] +enum_ibv_event_type = CEnum(ctypes.c_uint32) +IBV_EVENT_CQ_ERR = enum_ibv_event_type.define('IBV_EVENT_CQ_ERR', 0) +IBV_EVENT_QP_FATAL = enum_ibv_event_type.define('IBV_EVENT_QP_FATAL', 1) +IBV_EVENT_QP_REQ_ERR = enum_ibv_event_type.define('IBV_EVENT_QP_REQ_ERR', 2) +IBV_EVENT_QP_ACCESS_ERR = enum_ibv_event_type.define('IBV_EVENT_QP_ACCESS_ERR', 3) +IBV_EVENT_COMM_EST = enum_ibv_event_type.define('IBV_EVENT_COMM_EST', 4) +IBV_EVENT_SQ_DRAINED = enum_ibv_event_type.define('IBV_EVENT_SQ_DRAINED', 5) +IBV_EVENT_PATH_MIG = enum_ibv_event_type.define('IBV_EVENT_PATH_MIG', 6) +IBV_EVENT_PATH_MIG_ERR = enum_ibv_event_type.define('IBV_EVENT_PATH_MIG_ERR', 7) +IBV_EVENT_DEVICE_FATAL = enum_ibv_event_type.define('IBV_EVENT_DEVICE_FATAL', 8) +IBV_EVENT_PORT_ACTIVE = enum_ibv_event_type.define('IBV_EVENT_PORT_ACTIVE', 9) +IBV_EVENT_PORT_ERR = enum_ibv_event_type.define('IBV_EVENT_PORT_ERR', 10) +IBV_EVENT_LID_CHANGE = enum_ibv_event_type.define('IBV_EVENT_LID_CHANGE', 11) +IBV_EVENT_PKEY_CHANGE = enum_ibv_event_type.define('IBV_EVENT_PKEY_CHANGE', 12) +IBV_EVENT_SM_CHANGE = enum_ibv_event_type.define('IBV_EVENT_SM_CHANGE', 13) +IBV_EVENT_SRQ_ERR = enum_ibv_event_type.define('IBV_EVENT_SRQ_ERR', 14) +IBV_EVENT_SRQ_LIMIT_REACHED = enum_ibv_event_type.define('IBV_EVENT_SRQ_LIMIT_REACHED', 15) +IBV_EVENT_QP_LAST_WQE_REACHED = enum_ibv_event_type.define('IBV_EVENT_QP_LAST_WQE_REACHED', 16) +IBV_EVENT_CLIENT_REREGISTER = enum_ibv_event_type.define('IBV_EVENT_CLIENT_REREGISTER', 17) +IBV_EVENT_GID_CHANGE = enum_ibv_event_type.define('IBV_EVENT_GID_CHANGE', 18) +IBV_EVENT_WQ_FATAL = enum_ibv_event_type.define('IBV_EVENT_WQ_FATAL', 19) + +class struct_ibv_async_event(Struct): pass +class struct_ibv_async_event_element(ctypes.Union): pass +class struct_ibv_wq(Struct): pass +enum_ibv_wq_state = CEnum(ctypes.c_uint32) +IBV_WQS_RESET = enum_ibv_wq_state.define('IBV_WQS_RESET', 0) +IBV_WQS_RDY = enum_ibv_wq_state.define('IBV_WQS_RDY', 1) +IBV_WQS_ERR = enum_ibv_wq_state.define('IBV_WQS_ERR', 2) +IBV_WQS_UNKNOWN = enum_ibv_wq_state.define('IBV_WQS_UNKNOWN', 3) + +enum_ibv_wq_type = CEnum(ctypes.c_uint32) +IBV_WQT_RQ = enum_ibv_wq_type.define('IBV_WQT_RQ', 0) + +struct_ibv_wq._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('wq_context', ctypes.c_void_p), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('cq', ctypes.POINTER(struct_ibv_cq)), + ('wq_num', uint32_t), + ('handle', uint32_t), + ('state', enum_ibv_wq_state), + ('wq_type', enum_ibv_wq_type), + ('post_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), + ('mutex', pthread_mutex_t), + ('cond', pthread_cond_t), + ('events_completed', uint32_t), + ('comp_mask', uint32_t), +] +struct_ibv_async_event_element._fields_ = [ + ('cq', ctypes.POINTER(struct_ibv_cq)), + ('qp', ctypes.POINTER(struct_ibv_qp)), + ('srq', ctypes.POINTER(struct_ibv_srq)), + ('wq', ctypes.POINTER(struct_ibv_wq)), + ('port_num', ctypes.c_int32), +] +struct_ibv_async_event._fields_ = [ + ('element', struct_ibv_async_event_element), + ('event_type', enum_ibv_event_type), +] +# const char *ibv_wc_status_str(enum ibv_wc_status status) +try: (ibv_wc_status_str:=dll.ibv_wc_status_str).restype, ibv_wc_status_str.argtypes = ctypes.POINTER(ctypes.c_char), [enum_ibv_wc_status] +except AttributeError: pass + +_anonenum1 = CEnum(ctypes.c_uint32) +IBV_WC_IP_CSUM_OK_SHIFT = _anonenum1.define('IBV_WC_IP_CSUM_OK_SHIFT', 2) + +enum_ibv_create_cq_wc_flags = CEnum(ctypes.c_uint32) +IBV_WC_EX_WITH_BYTE_LEN = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_BYTE_LEN', 1) +IBV_WC_EX_WITH_IMM = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_IMM', 2) +IBV_WC_EX_WITH_QP_NUM = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_QP_NUM', 4) +IBV_WC_EX_WITH_SRC_QP = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_SRC_QP', 8) +IBV_WC_EX_WITH_SLID = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_SLID', 16) +IBV_WC_EX_WITH_SL = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_SL', 32) +IBV_WC_EX_WITH_DLID_PATH_BITS = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_DLID_PATH_BITS', 64) +IBV_WC_EX_WITH_COMPLETION_TIMESTAMP = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_COMPLETION_TIMESTAMP', 128) +IBV_WC_EX_WITH_CVLAN = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_CVLAN', 256) +IBV_WC_EX_WITH_FLOW_TAG = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_FLOW_TAG', 512) +IBV_WC_EX_WITH_TM_INFO = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_TM_INFO', 1024) +IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK = enum_ibv_create_cq_wc_flags.define('IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK', 2048) + +_anonenum2 = CEnum(ctypes.c_uint32) +IBV_WC_STANDARD_FLAGS = _anonenum2.define('IBV_WC_STANDARD_FLAGS', 127) + +_anonenum3 = CEnum(ctypes.c_uint32) +IBV_CREATE_CQ_SUP_WC_FLAGS = _anonenum3.define('IBV_CREATE_CQ_SUP_WC_FLAGS', 4095) + +enum_ibv_wc_flags = CEnum(ctypes.c_uint32) +IBV_WC_GRH = enum_ibv_wc_flags.define('IBV_WC_GRH', 1) +IBV_WC_WITH_IMM = enum_ibv_wc_flags.define('IBV_WC_WITH_IMM', 2) +IBV_WC_IP_CSUM_OK = enum_ibv_wc_flags.define('IBV_WC_IP_CSUM_OK', 4) +IBV_WC_WITH_INV = enum_ibv_wc_flags.define('IBV_WC_WITH_INV', 8) +IBV_WC_TM_SYNC_REQ = enum_ibv_wc_flags.define('IBV_WC_TM_SYNC_REQ', 16) +IBV_WC_TM_MATCH = enum_ibv_wc_flags.define('IBV_WC_TM_MATCH', 32) +IBV_WC_TM_DATA_VALID = enum_ibv_wc_flags.define('IBV_WC_TM_DATA_VALID', 64) + +enum_ibv_access_flags = CEnum(ctypes.c_uint32) +IBV_ACCESS_LOCAL_WRITE = enum_ibv_access_flags.define('IBV_ACCESS_LOCAL_WRITE', 1) +IBV_ACCESS_REMOTE_WRITE = enum_ibv_access_flags.define('IBV_ACCESS_REMOTE_WRITE', 2) +IBV_ACCESS_REMOTE_READ = enum_ibv_access_flags.define('IBV_ACCESS_REMOTE_READ', 4) +IBV_ACCESS_REMOTE_ATOMIC = enum_ibv_access_flags.define('IBV_ACCESS_REMOTE_ATOMIC', 8) +IBV_ACCESS_MW_BIND = enum_ibv_access_flags.define('IBV_ACCESS_MW_BIND', 16) +IBV_ACCESS_ZERO_BASED = enum_ibv_access_flags.define('IBV_ACCESS_ZERO_BASED', 32) +IBV_ACCESS_ON_DEMAND = enum_ibv_access_flags.define('IBV_ACCESS_ON_DEMAND', 64) +IBV_ACCESS_HUGETLB = enum_ibv_access_flags.define('IBV_ACCESS_HUGETLB', 128) +IBV_ACCESS_FLUSH_GLOBAL = enum_ibv_access_flags.define('IBV_ACCESS_FLUSH_GLOBAL', 256) +IBV_ACCESS_FLUSH_PERSISTENT = enum_ibv_access_flags.define('IBV_ACCESS_FLUSH_PERSISTENT', 512) +IBV_ACCESS_RELAXED_ORDERING = enum_ibv_access_flags.define('IBV_ACCESS_RELAXED_ORDERING', 1048576) + +class struct_ibv_td_init_attr(Struct): pass +struct_ibv_td_init_attr._fields_ = [ + ('comp_mask', uint32_t), +] +class struct_ibv_td(Struct): pass +struct_ibv_td._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), +] +enum_ibv_xrcd_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_XRCD_INIT_ATTR_FD = enum_ibv_xrcd_init_attr_mask.define('IBV_XRCD_INIT_ATTR_FD', 1) +IBV_XRCD_INIT_ATTR_OFLAGS = enum_ibv_xrcd_init_attr_mask.define('IBV_XRCD_INIT_ATTR_OFLAGS', 2) +IBV_XRCD_INIT_ATTR_RESERVED = enum_ibv_xrcd_init_attr_mask.define('IBV_XRCD_INIT_ATTR_RESERVED', 4) + +class struct_ibv_xrcd_init_attr(Struct): pass +struct_ibv_xrcd_init_attr._fields_ = [ + ('comp_mask', uint32_t), + ('fd', ctypes.c_int32), + ('oflags', ctypes.c_int32), +] +class struct_ibv_xrcd(Struct): pass +struct_ibv_xrcd._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), +] +enum_ibv_rereg_mr_flags = CEnum(ctypes.c_uint32) +IBV_REREG_MR_CHANGE_TRANSLATION = enum_ibv_rereg_mr_flags.define('IBV_REREG_MR_CHANGE_TRANSLATION', 1) +IBV_REREG_MR_CHANGE_PD = enum_ibv_rereg_mr_flags.define('IBV_REREG_MR_CHANGE_PD', 2) +IBV_REREG_MR_CHANGE_ACCESS = enum_ibv_rereg_mr_flags.define('IBV_REREG_MR_CHANGE_ACCESS', 4) +IBV_REREG_MR_FLAGS_SUPPORTED = enum_ibv_rereg_mr_flags.define('IBV_REREG_MR_FLAGS_SUPPORTED', 7) + +class struct_ibv_global_route(Struct): pass +struct_ibv_global_route._fields_ = [ + ('dgid', union_ibv_gid), + ('flow_label', uint32_t), + ('sgid_index', uint8_t), + ('hop_limit', uint8_t), + ('traffic_class', uint8_t), +] +class struct_ibv_grh(Struct): pass +__be16 = ctypes.c_uint16 +struct_ibv_grh._fields_ = [ + ('version_tclass_flow', ctypes.c_uint32), + ('paylen', ctypes.c_uint16), + ('next_hdr', uint8_t), + ('hop_limit', uint8_t), + ('sgid', union_ibv_gid), + ('dgid', union_ibv_gid), +] +enum_ibv_rate = CEnum(ctypes.c_uint32) +IBV_RATE_MAX = enum_ibv_rate.define('IBV_RATE_MAX', 0) +IBV_RATE_2_5_GBPS = enum_ibv_rate.define('IBV_RATE_2_5_GBPS', 2) +IBV_RATE_5_GBPS = enum_ibv_rate.define('IBV_RATE_5_GBPS', 5) +IBV_RATE_10_GBPS = enum_ibv_rate.define('IBV_RATE_10_GBPS', 3) +IBV_RATE_20_GBPS = enum_ibv_rate.define('IBV_RATE_20_GBPS', 6) +IBV_RATE_30_GBPS = enum_ibv_rate.define('IBV_RATE_30_GBPS', 4) +IBV_RATE_40_GBPS = enum_ibv_rate.define('IBV_RATE_40_GBPS', 7) +IBV_RATE_60_GBPS = enum_ibv_rate.define('IBV_RATE_60_GBPS', 8) +IBV_RATE_80_GBPS = enum_ibv_rate.define('IBV_RATE_80_GBPS', 9) +IBV_RATE_120_GBPS = enum_ibv_rate.define('IBV_RATE_120_GBPS', 10) +IBV_RATE_14_GBPS = enum_ibv_rate.define('IBV_RATE_14_GBPS', 11) +IBV_RATE_56_GBPS = enum_ibv_rate.define('IBV_RATE_56_GBPS', 12) +IBV_RATE_112_GBPS = enum_ibv_rate.define('IBV_RATE_112_GBPS', 13) +IBV_RATE_168_GBPS = enum_ibv_rate.define('IBV_RATE_168_GBPS', 14) +IBV_RATE_25_GBPS = enum_ibv_rate.define('IBV_RATE_25_GBPS', 15) +IBV_RATE_100_GBPS = enum_ibv_rate.define('IBV_RATE_100_GBPS', 16) +IBV_RATE_200_GBPS = enum_ibv_rate.define('IBV_RATE_200_GBPS', 17) +IBV_RATE_300_GBPS = enum_ibv_rate.define('IBV_RATE_300_GBPS', 18) +IBV_RATE_28_GBPS = enum_ibv_rate.define('IBV_RATE_28_GBPS', 19) +IBV_RATE_50_GBPS = enum_ibv_rate.define('IBV_RATE_50_GBPS', 20) +IBV_RATE_400_GBPS = enum_ibv_rate.define('IBV_RATE_400_GBPS', 21) +IBV_RATE_600_GBPS = enum_ibv_rate.define('IBV_RATE_600_GBPS', 22) +IBV_RATE_800_GBPS = enum_ibv_rate.define('IBV_RATE_800_GBPS', 23) +IBV_RATE_1200_GBPS = enum_ibv_rate.define('IBV_RATE_1200_GBPS', 24) + +# __attribute__((const)) int ibv_rate_to_mult(enum ibv_rate rate) +try: (ibv_rate_to_mult:=dll.ibv_rate_to_mult).restype, ibv_rate_to_mult.argtypes = ctypes.c_int32, [enum_ibv_rate] +except AttributeError: pass + +# __attribute__((const)) enum ibv_rate mult_to_ibv_rate(int mult) +try: (mult_to_ibv_rate:=dll.mult_to_ibv_rate).restype, mult_to_ibv_rate.argtypes = enum_ibv_rate, [ctypes.c_int32] +except AttributeError: pass + +# __attribute__((const)) int ibv_rate_to_mbps(enum ibv_rate rate) +try: (ibv_rate_to_mbps:=dll.ibv_rate_to_mbps).restype, ibv_rate_to_mbps.argtypes = ctypes.c_int32, [enum_ibv_rate] +except AttributeError: pass + +# __attribute__((const)) enum ibv_rate mbps_to_ibv_rate(int mbps) +try: (mbps_to_ibv_rate:=dll.mbps_to_ibv_rate).restype, mbps_to_ibv_rate.argtypes = enum_ibv_rate, [ctypes.c_int32] +except AttributeError: pass + +class struct_ibv_ah_attr(Struct): pass +struct_ibv_ah_attr._fields_ = [ + ('grh', struct_ibv_global_route), + ('dlid', uint16_t), + ('sl', uint8_t), + ('src_path_bits', uint8_t), + ('static_rate', uint8_t), + ('is_global', uint8_t), + ('port_num', uint8_t), +] +enum_ibv_srq_attr_mask = CEnum(ctypes.c_uint32) +IBV_SRQ_MAX_WR = enum_ibv_srq_attr_mask.define('IBV_SRQ_MAX_WR', 1) +IBV_SRQ_LIMIT = enum_ibv_srq_attr_mask.define('IBV_SRQ_LIMIT', 2) + +class struct_ibv_srq_attr(Struct): pass +struct_ibv_srq_attr._fields_ = [ + ('max_wr', uint32_t), + ('max_sge', uint32_t), + ('srq_limit', uint32_t), +] +class struct_ibv_srq_init_attr(Struct): pass +struct_ibv_srq_init_attr._fields_ = [ + ('srq_context', ctypes.c_void_p), + ('attr', struct_ibv_srq_attr), +] +enum_ibv_srq_type = CEnum(ctypes.c_uint32) +IBV_SRQT_BASIC = enum_ibv_srq_type.define('IBV_SRQT_BASIC', 0) +IBV_SRQT_XRC = enum_ibv_srq_type.define('IBV_SRQT_XRC', 1) +IBV_SRQT_TM = enum_ibv_srq_type.define('IBV_SRQT_TM', 2) + +enum_ibv_srq_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_SRQ_INIT_ATTR_TYPE = enum_ibv_srq_init_attr_mask.define('IBV_SRQ_INIT_ATTR_TYPE', 1) +IBV_SRQ_INIT_ATTR_PD = enum_ibv_srq_init_attr_mask.define('IBV_SRQ_INIT_ATTR_PD', 2) +IBV_SRQ_INIT_ATTR_XRCD = enum_ibv_srq_init_attr_mask.define('IBV_SRQ_INIT_ATTR_XRCD', 4) +IBV_SRQ_INIT_ATTR_CQ = enum_ibv_srq_init_attr_mask.define('IBV_SRQ_INIT_ATTR_CQ', 8) +IBV_SRQ_INIT_ATTR_TM = enum_ibv_srq_init_attr_mask.define('IBV_SRQ_INIT_ATTR_TM', 16) +IBV_SRQ_INIT_ATTR_RESERVED = enum_ibv_srq_init_attr_mask.define('IBV_SRQ_INIT_ATTR_RESERVED', 32) + +class struct_ibv_tm_cap(Struct): pass +struct_ibv_tm_cap._fields_ = [ + ('max_num_tags', uint32_t), + ('max_ops', uint32_t), +] +class struct_ibv_srq_init_attr_ex(Struct): pass +struct_ibv_srq_init_attr_ex._fields_ = [ + ('srq_context', ctypes.c_void_p), + ('attr', struct_ibv_srq_attr), + ('comp_mask', uint32_t), + ('srq_type', enum_ibv_srq_type), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), + ('cq', ctypes.POINTER(struct_ibv_cq)), + ('tm_cap', struct_ibv_tm_cap), +] +enum_ibv_wq_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_WQ_INIT_ATTR_FLAGS = enum_ibv_wq_init_attr_mask.define('IBV_WQ_INIT_ATTR_FLAGS', 1) +IBV_WQ_INIT_ATTR_RESERVED = enum_ibv_wq_init_attr_mask.define('IBV_WQ_INIT_ATTR_RESERVED', 2) + +enum_ibv_wq_flags = CEnum(ctypes.c_uint32) +IBV_WQ_FLAGS_CVLAN_STRIPPING = enum_ibv_wq_flags.define('IBV_WQ_FLAGS_CVLAN_STRIPPING', 1) +IBV_WQ_FLAGS_SCATTER_FCS = enum_ibv_wq_flags.define('IBV_WQ_FLAGS_SCATTER_FCS', 2) +IBV_WQ_FLAGS_DELAY_DROP = enum_ibv_wq_flags.define('IBV_WQ_FLAGS_DELAY_DROP', 4) +IBV_WQ_FLAGS_PCI_WRITE_END_PADDING = enum_ibv_wq_flags.define('IBV_WQ_FLAGS_PCI_WRITE_END_PADDING', 8) +IBV_WQ_FLAGS_RESERVED = enum_ibv_wq_flags.define('IBV_WQ_FLAGS_RESERVED', 16) + +class struct_ibv_wq_init_attr(Struct): pass +struct_ibv_wq_init_attr._fields_ = [ + ('wq_context', ctypes.c_void_p), + ('wq_type', enum_ibv_wq_type), + ('max_wr', uint32_t), + ('max_sge', uint32_t), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('cq', ctypes.POINTER(struct_ibv_cq)), + ('comp_mask', uint32_t), + ('create_flags', uint32_t), +] +enum_ibv_wq_attr_mask = CEnum(ctypes.c_uint32) +IBV_WQ_ATTR_STATE = enum_ibv_wq_attr_mask.define('IBV_WQ_ATTR_STATE', 1) +IBV_WQ_ATTR_CURR_STATE = enum_ibv_wq_attr_mask.define('IBV_WQ_ATTR_CURR_STATE', 2) +IBV_WQ_ATTR_FLAGS = enum_ibv_wq_attr_mask.define('IBV_WQ_ATTR_FLAGS', 4) +IBV_WQ_ATTR_RESERVED = enum_ibv_wq_attr_mask.define('IBV_WQ_ATTR_RESERVED', 8) + +class struct_ibv_wq_attr(Struct): pass +struct_ibv_wq_attr._fields_ = [ + ('attr_mask', uint32_t), + ('wq_state', enum_ibv_wq_state), + ('curr_wq_state', enum_ibv_wq_state), + ('flags', uint32_t), + ('flags_mask', uint32_t), +] +class struct_ibv_rwq_ind_table(Struct): pass +struct_ibv_rwq_ind_table._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('ind_tbl_handle', ctypes.c_int32), + ('ind_tbl_num', ctypes.c_int32), + ('comp_mask', uint32_t), +] +enum_ibv_ind_table_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_CREATE_IND_TABLE_RESERVED = enum_ibv_ind_table_init_attr_mask.define('IBV_CREATE_IND_TABLE_RESERVED', 1) + +class struct_ibv_rwq_ind_table_init_attr(Struct): pass +struct_ibv_rwq_ind_table_init_attr._fields_ = [ + ('log_ind_tbl_size', uint32_t), + ('ind_tbl', ctypes.POINTER(ctypes.POINTER(struct_ibv_wq))), + ('comp_mask', uint32_t), +] +class struct_ibv_qp_cap(Struct): pass +struct_ibv_qp_cap._fields_ = [ + ('max_send_wr', uint32_t), + ('max_recv_wr', uint32_t), + ('max_send_sge', uint32_t), + ('max_recv_sge', uint32_t), + ('max_inline_data', uint32_t), +] +class struct_ibv_qp_init_attr(Struct): pass +struct_ibv_qp_init_attr._fields_ = [ + ('qp_context', ctypes.c_void_p), + ('send_cq', ctypes.POINTER(struct_ibv_cq)), + ('recv_cq', ctypes.POINTER(struct_ibv_cq)), + ('srq', ctypes.POINTER(struct_ibv_srq)), + ('cap', struct_ibv_qp_cap), + ('qp_type', enum_ibv_qp_type), + ('sq_sig_all', ctypes.c_int32), +] +enum_ibv_qp_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_QP_INIT_ATTR_PD = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_PD', 1) +IBV_QP_INIT_ATTR_XRCD = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_XRCD', 2) +IBV_QP_INIT_ATTR_CREATE_FLAGS = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_CREATE_FLAGS', 4) +IBV_QP_INIT_ATTR_MAX_TSO_HEADER = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_MAX_TSO_HEADER', 8) +IBV_QP_INIT_ATTR_IND_TABLE = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_IND_TABLE', 16) +IBV_QP_INIT_ATTR_RX_HASH = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_RX_HASH', 32) +IBV_QP_INIT_ATTR_SEND_OPS_FLAGS = enum_ibv_qp_init_attr_mask.define('IBV_QP_INIT_ATTR_SEND_OPS_FLAGS', 64) + +enum_ibv_qp_create_flags = CEnum(ctypes.c_uint32) +IBV_QP_CREATE_BLOCK_SELF_MCAST_LB = enum_ibv_qp_create_flags.define('IBV_QP_CREATE_BLOCK_SELF_MCAST_LB', 2) +IBV_QP_CREATE_SCATTER_FCS = enum_ibv_qp_create_flags.define('IBV_QP_CREATE_SCATTER_FCS', 256) +IBV_QP_CREATE_CVLAN_STRIPPING = enum_ibv_qp_create_flags.define('IBV_QP_CREATE_CVLAN_STRIPPING', 512) +IBV_QP_CREATE_SOURCE_QPN = enum_ibv_qp_create_flags.define('IBV_QP_CREATE_SOURCE_QPN', 1024) +IBV_QP_CREATE_PCI_WRITE_END_PADDING = enum_ibv_qp_create_flags.define('IBV_QP_CREATE_PCI_WRITE_END_PADDING', 2048) + +enum_ibv_qp_create_send_ops_flags = CEnum(ctypes.c_uint32) +IBV_QP_EX_WITH_RDMA_WRITE = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_RDMA_WRITE', 1) +IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM', 2) +IBV_QP_EX_WITH_SEND = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_SEND', 4) +IBV_QP_EX_WITH_SEND_WITH_IMM = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_SEND_WITH_IMM', 8) +IBV_QP_EX_WITH_RDMA_READ = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_RDMA_READ', 16) +IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP', 32) +IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD', 64) +IBV_QP_EX_WITH_LOCAL_INV = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_LOCAL_INV', 128) +IBV_QP_EX_WITH_BIND_MW = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_BIND_MW', 256) +IBV_QP_EX_WITH_SEND_WITH_INV = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_SEND_WITH_INV', 512) +IBV_QP_EX_WITH_TSO = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_TSO', 1024) +IBV_QP_EX_WITH_FLUSH = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_FLUSH', 2048) +IBV_QP_EX_WITH_ATOMIC_WRITE = enum_ibv_qp_create_send_ops_flags.define('IBV_QP_EX_WITH_ATOMIC_WRITE', 4096) + +class struct_ibv_rx_hash_conf(Struct): pass +struct_ibv_rx_hash_conf._fields_ = [ + ('rx_hash_function', uint8_t), + ('rx_hash_key_len', uint8_t), + ('rx_hash_key', ctypes.POINTER(uint8_t)), + ('rx_hash_fields_mask', uint64_t), +] +class struct_ibv_qp_init_attr_ex(Struct): pass +struct_ibv_qp_init_attr_ex._fields_ = [ + ('qp_context', ctypes.c_void_p), + ('send_cq', ctypes.POINTER(struct_ibv_cq)), + ('recv_cq', ctypes.POINTER(struct_ibv_cq)), + ('srq', ctypes.POINTER(struct_ibv_srq)), + ('cap', struct_ibv_qp_cap), + ('qp_type', enum_ibv_qp_type), + ('sq_sig_all', ctypes.c_int32), + ('comp_mask', uint32_t), + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), + ('create_flags', uint32_t), + ('max_tso_header', uint16_t), + ('rwq_ind_tbl', ctypes.POINTER(struct_ibv_rwq_ind_table)), + ('rx_hash_conf', struct_ibv_rx_hash_conf), + ('source_qpn', uint32_t), + ('send_ops_flags', uint64_t), +] +enum_ibv_qp_open_attr_mask = CEnum(ctypes.c_uint32) +IBV_QP_OPEN_ATTR_NUM = enum_ibv_qp_open_attr_mask.define('IBV_QP_OPEN_ATTR_NUM', 1) +IBV_QP_OPEN_ATTR_XRCD = enum_ibv_qp_open_attr_mask.define('IBV_QP_OPEN_ATTR_XRCD', 2) +IBV_QP_OPEN_ATTR_CONTEXT = enum_ibv_qp_open_attr_mask.define('IBV_QP_OPEN_ATTR_CONTEXT', 4) +IBV_QP_OPEN_ATTR_TYPE = enum_ibv_qp_open_attr_mask.define('IBV_QP_OPEN_ATTR_TYPE', 8) +IBV_QP_OPEN_ATTR_RESERVED = enum_ibv_qp_open_attr_mask.define('IBV_QP_OPEN_ATTR_RESERVED', 16) + +class struct_ibv_qp_open_attr(Struct): pass +struct_ibv_qp_open_attr._fields_ = [ + ('comp_mask', uint32_t), + ('qp_num', uint32_t), + ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), + ('qp_context', ctypes.c_void_p), + ('qp_type', enum_ibv_qp_type), +] +enum_ibv_qp_attr_mask = CEnum(ctypes.c_uint32) +IBV_QP_STATE = enum_ibv_qp_attr_mask.define('IBV_QP_STATE', 1) +IBV_QP_CUR_STATE = enum_ibv_qp_attr_mask.define('IBV_QP_CUR_STATE', 2) +IBV_QP_EN_SQD_ASYNC_NOTIFY = enum_ibv_qp_attr_mask.define('IBV_QP_EN_SQD_ASYNC_NOTIFY', 4) +IBV_QP_ACCESS_FLAGS = enum_ibv_qp_attr_mask.define('IBV_QP_ACCESS_FLAGS', 8) +IBV_QP_PKEY_INDEX = enum_ibv_qp_attr_mask.define('IBV_QP_PKEY_INDEX', 16) +IBV_QP_PORT = enum_ibv_qp_attr_mask.define('IBV_QP_PORT', 32) +IBV_QP_QKEY = enum_ibv_qp_attr_mask.define('IBV_QP_QKEY', 64) +IBV_QP_AV = enum_ibv_qp_attr_mask.define('IBV_QP_AV', 128) +IBV_QP_PATH_MTU = enum_ibv_qp_attr_mask.define('IBV_QP_PATH_MTU', 256) +IBV_QP_TIMEOUT = enum_ibv_qp_attr_mask.define('IBV_QP_TIMEOUT', 512) +IBV_QP_RETRY_CNT = enum_ibv_qp_attr_mask.define('IBV_QP_RETRY_CNT', 1024) +IBV_QP_RNR_RETRY = enum_ibv_qp_attr_mask.define('IBV_QP_RNR_RETRY', 2048) +IBV_QP_RQ_PSN = enum_ibv_qp_attr_mask.define('IBV_QP_RQ_PSN', 4096) +IBV_QP_MAX_QP_RD_ATOMIC = enum_ibv_qp_attr_mask.define('IBV_QP_MAX_QP_RD_ATOMIC', 8192) +IBV_QP_ALT_PATH = enum_ibv_qp_attr_mask.define('IBV_QP_ALT_PATH', 16384) +IBV_QP_MIN_RNR_TIMER = enum_ibv_qp_attr_mask.define('IBV_QP_MIN_RNR_TIMER', 32768) +IBV_QP_SQ_PSN = enum_ibv_qp_attr_mask.define('IBV_QP_SQ_PSN', 65536) +IBV_QP_MAX_DEST_RD_ATOMIC = enum_ibv_qp_attr_mask.define('IBV_QP_MAX_DEST_RD_ATOMIC', 131072) +IBV_QP_PATH_MIG_STATE = enum_ibv_qp_attr_mask.define('IBV_QP_PATH_MIG_STATE', 262144) +IBV_QP_CAP = enum_ibv_qp_attr_mask.define('IBV_QP_CAP', 524288) +IBV_QP_DEST_QPN = enum_ibv_qp_attr_mask.define('IBV_QP_DEST_QPN', 1048576) +IBV_QP_RATE_LIMIT = enum_ibv_qp_attr_mask.define('IBV_QP_RATE_LIMIT', 33554432) + +enum_ibv_query_qp_data_in_order_flags = CEnum(ctypes.c_uint32) +IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS = enum_ibv_query_qp_data_in_order_flags.define('IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS', 1) + +enum_ibv_query_qp_data_in_order_caps = CEnum(ctypes.c_uint32) +IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG = enum_ibv_query_qp_data_in_order_caps.define('IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG', 1) +IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES = enum_ibv_query_qp_data_in_order_caps.define('IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES', 2) + +enum_ibv_mig_state = CEnum(ctypes.c_uint32) +IBV_MIG_MIGRATED = enum_ibv_mig_state.define('IBV_MIG_MIGRATED', 0) +IBV_MIG_REARM = enum_ibv_mig_state.define('IBV_MIG_REARM', 1) +IBV_MIG_ARMED = enum_ibv_mig_state.define('IBV_MIG_ARMED', 2) + +class struct_ibv_qp_attr(Struct): pass +struct_ibv_qp_attr._fields_ = [ + ('qp_state', enum_ibv_qp_state), + ('cur_qp_state', enum_ibv_qp_state), + ('path_mtu', enum_ibv_mtu), + ('path_mig_state', enum_ibv_mig_state), + ('qkey', uint32_t), + ('rq_psn', uint32_t), + ('sq_psn', uint32_t), + ('dest_qp_num', uint32_t), + ('qp_access_flags', ctypes.c_uint32), + ('cap', struct_ibv_qp_cap), + ('ah_attr', struct_ibv_ah_attr), + ('alt_ah_attr', struct_ibv_ah_attr), + ('pkey_index', uint16_t), + ('alt_pkey_index', uint16_t), + ('en_sqd_async_notify', uint8_t), + ('sq_draining', uint8_t), + ('max_rd_atomic', uint8_t), + ('max_dest_rd_atomic', uint8_t), + ('min_rnr_timer', uint8_t), + ('port_num', uint8_t), + ('timeout', uint8_t), + ('retry_cnt', uint8_t), + ('rnr_retry', uint8_t), + ('alt_port_num', uint8_t), + ('alt_timeout', uint8_t), + ('rate_limit', uint32_t), +] +class struct_ibv_qp_rate_limit_attr(Struct): pass +struct_ibv_qp_rate_limit_attr._fields_ = [ + ('rate_limit', uint32_t), + ('max_burst_sz', uint32_t), + ('typical_pkt_sz', uint16_t), + ('comp_mask', uint32_t), +] +# const char *ibv_wr_opcode_str(enum ibv_wr_opcode opcode) +try: (ibv_wr_opcode_str:=dll.ibv_wr_opcode_str).restype, ibv_wr_opcode_str.argtypes = ctypes.POINTER(ctypes.c_char), [enum_ibv_wr_opcode] +except AttributeError: pass + +enum_ibv_send_flags = CEnum(ctypes.c_uint32) +IBV_SEND_FENCE = enum_ibv_send_flags.define('IBV_SEND_FENCE', 1) +IBV_SEND_SIGNALED = enum_ibv_send_flags.define('IBV_SEND_SIGNALED', 2) +IBV_SEND_SOLICITED = enum_ibv_send_flags.define('IBV_SEND_SOLICITED', 4) +IBV_SEND_INLINE = enum_ibv_send_flags.define('IBV_SEND_INLINE', 8) +IBV_SEND_IP_CSUM = enum_ibv_send_flags.define('IBV_SEND_IP_CSUM', 16) + +enum_ibv_placement_type = CEnum(ctypes.c_uint32) +IBV_FLUSH_GLOBAL = enum_ibv_placement_type.define('IBV_FLUSH_GLOBAL', 1) +IBV_FLUSH_PERSISTENT = enum_ibv_placement_type.define('IBV_FLUSH_PERSISTENT', 2) + +enum_ibv_selectivity_level = CEnum(ctypes.c_uint32) +IBV_FLUSH_RANGE = enum_ibv_selectivity_level.define('IBV_FLUSH_RANGE', 0) +IBV_FLUSH_MR = enum_ibv_selectivity_level.define('IBV_FLUSH_MR', 1) + +class struct_ibv_data_buf(Struct): pass +struct_ibv_data_buf._fields_ = [ + ('addr', ctypes.c_void_p), + ('length', size_t), +] +enum_ibv_ops_wr_opcode = CEnum(ctypes.c_uint32) +IBV_WR_TAG_ADD = enum_ibv_ops_wr_opcode.define('IBV_WR_TAG_ADD', 0) +IBV_WR_TAG_DEL = enum_ibv_ops_wr_opcode.define('IBV_WR_TAG_DEL', 1) +IBV_WR_TAG_SYNC = enum_ibv_ops_wr_opcode.define('IBV_WR_TAG_SYNC', 2) + +enum_ibv_ops_flags = CEnum(ctypes.c_uint32) +IBV_OPS_SIGNALED = enum_ibv_ops_flags.define('IBV_OPS_SIGNALED', 1) +IBV_OPS_TM_SYNC = enum_ibv_ops_flags.define('IBV_OPS_TM_SYNC', 2) + +class struct_ibv_ops_wr(Struct): pass +class struct_ibv_ops_wr_tm(Struct): pass +class struct_ibv_ops_wr_tm_add(Struct): pass +struct_ibv_ops_wr_tm_add._fields_ = [ + ('recv_wr_id', uint64_t), + ('sg_list', ctypes.POINTER(struct_ibv_sge)), + ('num_sge', ctypes.c_int32), + ('tag', uint64_t), + ('mask', uint64_t), +] +struct_ibv_ops_wr_tm._fields_ = [ + ('unexpected_cnt', uint32_t), + ('handle', uint32_t), + ('add', struct_ibv_ops_wr_tm_add), +] +struct_ibv_ops_wr._fields_ = [ + ('wr_id', uint64_t), + ('next', ctypes.POINTER(struct_ibv_ops_wr)), + ('opcode', enum_ibv_ops_wr_opcode), + ('flags', ctypes.c_int32), + ('tm', struct_ibv_ops_wr_tm), +] +class struct_ibv_qp_ex(Struct): pass +struct_ibv_qp_ex._fields_ = [ + ('qp_base', struct_ibv_qp), + ('comp_mask', uint64_t), + ('wr_id', uint64_t), + ('wr_flags', ctypes.c_uint32), + ('wr_atomic_cmp_swp', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint64_t, uint64_t)), + ('wr_atomic_fetch_add', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint64_t)), + ('wr_bind_mw', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_mw), uint32_t, ctypes.POINTER(struct_ibv_mw_bind_info))), + ('wr_local_inv', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t)), + ('wr_rdma_read', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t)), + ('wr_rdma_write', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t)), + ('wr_rdma_write_imm', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, ctypes.c_uint32)), + ('wr_send', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), + ('wr_send_imm', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), + ('wr_send_inv', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t)), + ('wr_send_tso', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_void_p, uint16_t, uint16_t)), + ('wr_set_ud_addr', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_ah), uint32_t, uint32_t)), + ('wr_set_xrc_srqn', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t)), + ('wr_set_inline_data', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_void_p, size_t)), + ('wr_set_inline_data_list', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), size_t, ctypes.POINTER(struct_ibv_data_buf))), + ('wr_set_sge', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint32_t)), + ('wr_set_sge_list', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), size_t, ctypes.POINTER(struct_ibv_sge))), + ('wr_start', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), + ('wr_complete', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp_ex))), + ('wr_abort', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), + ('wr_atomic_write', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, ctypes.c_void_p)), + ('wr_flush', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, size_t, uint8_t, uint8_t)), +] +# struct ibv_qp_ex *ibv_qp_to_qp_ex(struct ibv_qp *qp) +try: (ibv_qp_to_qp_ex:=dll.ibv_qp_to_qp_ex).restype, ibv_qp_to_qp_ex.argtypes = ctypes.POINTER(struct_ibv_qp_ex), [ctypes.POINTER(struct_ibv_qp)] +except AttributeError: pass + +class struct_ibv_ece(Struct): pass +struct_ibv_ece._fields_ = [ + ('vendor_id', uint32_t), + ('options', uint32_t), + ('comp_mask', uint32_t), +] +class struct_ibv_poll_cq_attr(Struct): pass +struct_ibv_poll_cq_attr._fields_ = [ + ('comp_mask', uint32_t), +] +class struct_ibv_wc_tm_info(Struct): pass +struct_ibv_wc_tm_info._fields_ = [ + ('tag', uint64_t), + ('priv', uint32_t), +] +class struct_ibv_cq_ex(Struct): pass +struct_ibv_cq_ex._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), + ('channel', ctypes.POINTER(struct_ibv_comp_channel)), + ('cq_context', ctypes.c_void_p), + ('handle', uint32_t), + ('cqe', ctypes.c_int32), + ('mutex', pthread_mutex_t), + ('cond', pthread_cond_t), + ('comp_events_completed', uint32_t), + ('async_events_completed', uint32_t), + ('comp_mask', uint32_t), + ('status', enum_ibv_wc_status), + ('wr_id', uint64_t), + ('start_poll', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_poll_cq_attr))), + ('next_poll', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq_ex))), + ('end_poll', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_opcode', ctypes.CFUNCTYPE(enum_ibv_wc_opcode, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_vendor_err', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_byte_len', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_imm_data', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_qp_num', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_src_qp', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_wc_flags', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_slid', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_sl', ctypes.CFUNCTYPE(uint8_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_dlid_path_bits', ctypes.CFUNCTYPE(uint8_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_completion_ts', ctypes.CFUNCTYPE(uint64_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_cvlan', ctypes.CFUNCTYPE(uint16_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_flow_tag', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(struct_ibv_cq_ex))), + ('read_tm_info', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_wc_tm_info))), + ('read_completion_wallclock_ns', ctypes.CFUNCTYPE(uint64_t, ctypes.POINTER(struct_ibv_cq_ex))), +] +enum_ibv_cq_attr_mask = CEnum(ctypes.c_uint32) +IBV_CQ_ATTR_MODERATE = enum_ibv_cq_attr_mask.define('IBV_CQ_ATTR_MODERATE', 1) +IBV_CQ_ATTR_RESERVED = enum_ibv_cq_attr_mask.define('IBV_CQ_ATTR_RESERVED', 2) + +class struct_ibv_moderate_cq(Struct): pass +struct_ibv_moderate_cq._fields_ = [ + ('cq_count', uint16_t), + ('cq_period', uint16_t), +] +class struct_ibv_modify_cq_attr(Struct): pass +struct_ibv_modify_cq_attr._fields_ = [ + ('attr_mask', uint32_t), + ('moderate', struct_ibv_moderate_cq), +] +enum_ibv_flow_flags = CEnum(ctypes.c_uint32) +IBV_FLOW_ATTR_FLAGS_DONT_TRAP = enum_ibv_flow_flags.define('IBV_FLOW_ATTR_FLAGS_DONT_TRAP', 2) +IBV_FLOW_ATTR_FLAGS_EGRESS = enum_ibv_flow_flags.define('IBV_FLOW_ATTR_FLAGS_EGRESS', 4) + +enum_ibv_flow_attr_type = CEnum(ctypes.c_uint32) +IBV_FLOW_ATTR_NORMAL = enum_ibv_flow_attr_type.define('IBV_FLOW_ATTR_NORMAL', 0) +IBV_FLOW_ATTR_ALL_DEFAULT = enum_ibv_flow_attr_type.define('IBV_FLOW_ATTR_ALL_DEFAULT', 1) +IBV_FLOW_ATTR_MC_DEFAULT = enum_ibv_flow_attr_type.define('IBV_FLOW_ATTR_MC_DEFAULT', 2) +IBV_FLOW_ATTR_SNIFFER = enum_ibv_flow_attr_type.define('IBV_FLOW_ATTR_SNIFFER', 3) + +enum_ibv_flow_spec_type = CEnum(ctypes.c_uint32) +IBV_FLOW_SPEC_ETH = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_ETH', 32) +IBV_FLOW_SPEC_IPV4 = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_IPV4', 48) +IBV_FLOW_SPEC_IPV6 = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_IPV6', 49) +IBV_FLOW_SPEC_IPV4_EXT = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_IPV4_EXT', 50) +IBV_FLOW_SPEC_ESP = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_ESP', 52) +IBV_FLOW_SPEC_TCP = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_TCP', 64) +IBV_FLOW_SPEC_UDP = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_UDP', 65) +IBV_FLOW_SPEC_VXLAN_TUNNEL = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_VXLAN_TUNNEL', 80) +IBV_FLOW_SPEC_GRE = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_GRE', 81) +IBV_FLOW_SPEC_MPLS = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_MPLS', 96) +IBV_FLOW_SPEC_INNER = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_INNER', 256) +IBV_FLOW_SPEC_ACTION_TAG = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_ACTION_TAG', 4096) +IBV_FLOW_SPEC_ACTION_DROP = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_ACTION_DROP', 4097) +IBV_FLOW_SPEC_ACTION_HANDLE = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_ACTION_HANDLE', 4098) +IBV_FLOW_SPEC_ACTION_COUNT = enum_ibv_flow_spec_type.define('IBV_FLOW_SPEC_ACTION_COUNT', 4099) + +class struct_ibv_flow_eth_filter(Struct): pass +struct_ibv_flow_eth_filter._fields_ = [ + ('dst_mac', (uint8_t * 6)), + ('src_mac', (uint8_t * 6)), + ('ether_type', uint16_t), + ('vlan_tag', uint16_t), +] +class struct_ibv_flow_spec_eth(Struct): pass +struct_ibv_flow_spec_eth._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_eth_filter), + ('mask', struct_ibv_flow_eth_filter), +] +class struct_ibv_flow_ipv4_filter(Struct): pass +struct_ibv_flow_ipv4_filter._fields_ = [ + ('src_ip', uint32_t), + ('dst_ip', uint32_t), +] +class struct_ibv_flow_spec_ipv4(Struct): pass +struct_ibv_flow_spec_ipv4._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_ipv4_filter), + ('mask', struct_ibv_flow_ipv4_filter), +] +class struct_ibv_flow_ipv4_ext_filter(Struct): pass +struct_ibv_flow_ipv4_ext_filter._fields_ = [ + ('src_ip', uint32_t), + ('dst_ip', uint32_t), + ('proto', uint8_t), + ('tos', uint8_t), + ('ttl', uint8_t), + ('flags', uint8_t), +] +class struct_ibv_flow_spec_ipv4_ext(Struct): pass +struct_ibv_flow_spec_ipv4_ext._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_ipv4_ext_filter), + ('mask', struct_ibv_flow_ipv4_ext_filter), +] +class struct_ibv_flow_ipv6_filter(Struct): pass +struct_ibv_flow_ipv6_filter._fields_ = [ + ('src_ip', (uint8_t * 16)), + ('dst_ip', (uint8_t * 16)), + ('flow_label', uint32_t), + ('next_hdr', uint8_t), + ('traffic_class', uint8_t), + ('hop_limit', uint8_t), +] +class struct_ibv_flow_spec_ipv6(Struct): pass +struct_ibv_flow_spec_ipv6._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_ipv6_filter), + ('mask', struct_ibv_flow_ipv6_filter), +] +class struct_ibv_flow_esp_filter(Struct): pass +struct_ibv_flow_esp_filter._fields_ = [ + ('spi', uint32_t), + ('seq', uint32_t), +] +class struct_ibv_flow_spec_esp(Struct): pass +struct_ibv_flow_spec_esp._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_esp_filter), + ('mask', struct_ibv_flow_esp_filter), +] +class struct_ibv_flow_tcp_udp_filter(Struct): pass +struct_ibv_flow_tcp_udp_filter._fields_ = [ + ('dst_port', uint16_t), + ('src_port', uint16_t), +] +class struct_ibv_flow_spec_tcp_udp(Struct): pass +struct_ibv_flow_spec_tcp_udp._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_tcp_udp_filter), + ('mask', struct_ibv_flow_tcp_udp_filter), +] +class struct_ibv_flow_gre_filter(Struct): pass +struct_ibv_flow_gre_filter._fields_ = [ + ('c_ks_res0_ver', uint16_t), + ('protocol', uint16_t), + ('key', uint32_t), +] +class struct_ibv_flow_spec_gre(Struct): pass +struct_ibv_flow_spec_gre._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_gre_filter), + ('mask', struct_ibv_flow_gre_filter), +] +class struct_ibv_flow_mpls_filter(Struct): pass +struct_ibv_flow_mpls_filter._fields_ = [ + ('label', uint32_t), +] +class struct_ibv_flow_spec_mpls(Struct): pass +struct_ibv_flow_spec_mpls._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_mpls_filter), + ('mask', struct_ibv_flow_mpls_filter), +] +class struct_ibv_flow_tunnel_filter(Struct): pass +struct_ibv_flow_tunnel_filter._fields_ = [ + ('tunnel_id', uint32_t), +] +class struct_ibv_flow_spec_tunnel(Struct): pass +struct_ibv_flow_spec_tunnel._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('val', struct_ibv_flow_tunnel_filter), + ('mask', struct_ibv_flow_tunnel_filter), +] +class struct_ibv_flow_spec_action_tag(Struct): pass +struct_ibv_flow_spec_action_tag._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('tag_id', uint32_t), +] +class struct_ibv_flow_spec_action_drop(Struct): pass +struct_ibv_flow_spec_action_drop._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), +] +class struct_ibv_flow_spec_action_handle(Struct): pass +class struct_ibv_flow_action(Struct): pass +struct_ibv_flow_action._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), +] +struct_ibv_flow_spec_action_handle._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('action', ctypes.POINTER(struct_ibv_flow_action)), +] +class struct_ibv_flow_spec_counter_action(Struct): pass +class struct_ibv_counters(Struct): pass +struct_ibv_counters._fields_ = [ + ('context', ctypes.POINTER(struct_ibv_context)), +] +struct_ibv_flow_spec_counter_action._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), + ('counters', ctypes.POINTER(struct_ibv_counters)), +] +class struct_ibv_flow_spec(Struct): pass +class struct_ibv_flow_spec_0(ctypes.Union): pass +class struct_ibv_flow_spec_0_hdr(Struct): pass +struct_ibv_flow_spec_0_hdr._fields_ = [ + ('type', enum_ibv_flow_spec_type), + ('size', uint16_t), +] +struct_ibv_flow_spec_0._fields_ = [ + ('hdr', struct_ibv_flow_spec_0_hdr), + ('eth', struct_ibv_flow_spec_eth), + ('ipv4', struct_ibv_flow_spec_ipv4), + ('tcp_udp', struct_ibv_flow_spec_tcp_udp), + ('ipv4_ext', struct_ibv_flow_spec_ipv4_ext), + ('ipv6', struct_ibv_flow_spec_ipv6), + ('esp', struct_ibv_flow_spec_esp), + ('tunnel', struct_ibv_flow_spec_tunnel), + ('gre', struct_ibv_flow_spec_gre), + ('mpls', struct_ibv_flow_spec_mpls), + ('flow_tag', struct_ibv_flow_spec_action_tag), + ('drop', struct_ibv_flow_spec_action_drop), + ('handle', struct_ibv_flow_spec_action_handle), + ('flow_count', struct_ibv_flow_spec_counter_action), +] +struct_ibv_flow_spec._anonymous_ = ['_0'] +struct_ibv_flow_spec._fields_ = [ + ('_0', struct_ibv_flow_spec_0), +] +class struct_ibv_flow_attr(Struct): pass +struct_ibv_flow_attr._fields_ = [ + ('comp_mask', uint32_t), + ('type', enum_ibv_flow_attr_type), + ('size', uint16_t), + ('priority', uint16_t), + ('num_of_specs', uint8_t), + ('port', uint8_t), + ('flags', uint32_t), +] +class struct_ibv_flow(Struct): pass +struct_ibv_flow._fields_ = [ + ('comp_mask', uint32_t), + ('context', ctypes.POINTER(struct_ibv_context)), + ('handle', uint32_t), +] +enum_ibv_flow_action_esp_mask = CEnum(ctypes.c_uint32) +IBV_FLOW_ACTION_ESP_MASK_ESN = enum_ibv_flow_action_esp_mask.define('IBV_FLOW_ACTION_ESP_MASK_ESN', 1) + +class struct_ibv_flow_action_esp_attr(Struct): pass +class struct_ib_uverbs_flow_action_esp(Struct): pass +__u32 = ctypes.c_uint32 +__u64 = ctypes.c_uint64 +struct_ib_uverbs_flow_action_esp._fields_ = [ + ('spi', ctypes.c_uint32), + ('seq', ctypes.c_uint32), + ('tfc_pad', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('hard_limit_pkts', ctypes.c_uint64), +] +enum_ib_uverbs_flow_action_esp_keymat = CEnum(ctypes.c_uint32) +IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM = enum_ib_uverbs_flow_action_esp_keymat.define('IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM', 0) + +enum_ib_uverbs_flow_action_esp_replay = CEnum(ctypes.c_uint32) +IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE = enum_ib_uverbs_flow_action_esp_replay.define('IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE', 0) +IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP = enum_ib_uverbs_flow_action_esp_replay.define('IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP', 1) + +class struct_ib_uverbs_flow_action_esp_encap(Struct): pass +class struct_ib_uverbs_flow_action_esp_encap_0(ctypes.Union): pass +struct_ib_uverbs_flow_action_esp_encap_0._fields_ = [ + ('val_ptr', ctypes.c_void_p), + ('val_ptr_data_u64', ctypes.c_uint64), +] +class struct_ib_uverbs_flow_action_esp_encap_1(ctypes.Union): pass +struct_ib_uverbs_flow_action_esp_encap_1._fields_ = [ + ('next_ptr', ctypes.POINTER(struct_ib_uverbs_flow_action_esp_encap)), + ('next_ptr_data_u64', ctypes.c_uint64), +] +__u16 = ctypes.c_uint16 +struct_ib_uverbs_flow_action_esp_encap._anonymous_ = ['_0', '_1'] +struct_ib_uverbs_flow_action_esp_encap._fields_ = [ + ('_0', struct_ib_uverbs_flow_action_esp_encap_0), + ('_1', struct_ib_uverbs_flow_action_esp_encap_1), + ('len', ctypes.c_uint16), + ('type', ctypes.c_uint16), +] +struct_ibv_flow_action_esp_attr._fields_ = [ + ('esp_attr', ctypes.POINTER(struct_ib_uverbs_flow_action_esp)), + ('keymat_proto', enum_ib_uverbs_flow_action_esp_keymat), + ('keymat_len', uint16_t), + ('keymat_ptr', ctypes.c_void_p), + ('replay_proto', enum_ib_uverbs_flow_action_esp_replay), + ('replay_len', uint16_t), + ('replay_ptr', ctypes.c_void_p), + ('esp_encap', ctypes.POINTER(struct_ib_uverbs_flow_action_esp_encap)), + ('comp_mask', uint32_t), + ('esn', uint32_t), +] +_anonenum4 = CEnum(ctypes.c_uint32) +IBV_SYSFS_NAME_MAX = _anonenum4.define('IBV_SYSFS_NAME_MAX', 64) +IBV_SYSFS_PATH_MAX = _anonenum4.define('IBV_SYSFS_PATH_MAX', 256) + +enum_ibv_cq_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_CQ_INIT_ATTR_MASK_FLAGS = enum_ibv_cq_init_attr_mask.define('IBV_CQ_INIT_ATTR_MASK_FLAGS', 1) +IBV_CQ_INIT_ATTR_MASK_PD = enum_ibv_cq_init_attr_mask.define('IBV_CQ_INIT_ATTR_MASK_PD', 2) + +enum_ibv_create_cq_attr_flags = CEnum(ctypes.c_uint32) +IBV_CREATE_CQ_ATTR_SINGLE_THREADED = enum_ibv_create_cq_attr_flags.define('IBV_CREATE_CQ_ATTR_SINGLE_THREADED', 1) +IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN = enum_ibv_create_cq_attr_flags.define('IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN', 2) + +class struct_ibv_cq_init_attr_ex(Struct): pass +struct_ibv_cq_init_attr_ex._fields_ = [ + ('cqe', uint32_t), + ('cq_context', ctypes.c_void_p), + ('channel', ctypes.POINTER(struct_ibv_comp_channel)), + ('comp_vector', uint32_t), + ('wc_flags', uint64_t), + ('comp_mask', uint32_t), + ('flags', uint32_t), + ('parent_domain', ctypes.POINTER(struct_ibv_pd)), +] +enum_ibv_parent_domain_init_attr_mask = CEnum(ctypes.c_uint32) +IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS = enum_ibv_parent_domain_init_attr_mask.define('IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS', 1) +IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT = enum_ibv_parent_domain_init_attr_mask.define('IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT', 2) + +class struct_ibv_parent_domain_init_attr(Struct): pass +struct_ibv_parent_domain_init_attr._fields_ = [ + ('pd', ctypes.POINTER(struct_ibv_pd)), + ('td', ctypes.POINTER(struct_ibv_td)), + ('comp_mask', uint32_t), + ('alloc', ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.POINTER(struct_ibv_pd), ctypes.c_void_p, size_t, size_t, uint64_t)), + ('free', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_pd), ctypes.c_void_p, ctypes.c_void_p, uint64_t)), + ('pd_context', ctypes.c_void_p), +] +class struct_ibv_counters_init_attr(Struct): pass +struct_ibv_counters_init_attr._fields_ = [ + ('comp_mask', uint32_t), +] +enum_ibv_counter_description = CEnum(ctypes.c_uint32) +IBV_COUNTER_PACKETS = enum_ibv_counter_description.define('IBV_COUNTER_PACKETS', 0) +IBV_COUNTER_BYTES = enum_ibv_counter_description.define('IBV_COUNTER_BYTES', 1) + +class struct_ibv_counter_attach_attr(Struct): pass +struct_ibv_counter_attach_attr._fields_ = [ + ('counter_desc', enum_ibv_counter_description), + ('index', uint32_t), + ('comp_mask', uint32_t), +] +enum_ibv_read_counters_flags = CEnum(ctypes.c_uint32) +IBV_READ_COUNTERS_ATTR_PREFER_CACHED = enum_ibv_read_counters_flags.define('IBV_READ_COUNTERS_ATTR_PREFER_CACHED', 1) + +enum_ibv_values_mask = CEnum(ctypes.c_uint32) +IBV_VALUES_MASK_RAW_CLOCK = enum_ibv_values_mask.define('IBV_VALUES_MASK_RAW_CLOCK', 1) +IBV_VALUES_MASK_RESERVED = enum_ibv_values_mask.define('IBV_VALUES_MASK_RESERVED', 2) + +class struct_ibv_values_ex(Struct): pass +class struct_timespec(Struct): pass +__time_t = ctypes.c_int64 +__syscall_slong_t = ctypes.c_int64 +struct_timespec._fields_ = [ + ('tv_sec', ctypes.c_int64), + ('tv_nsec', ctypes.c_int64), +] +struct_ibv_values_ex._fields_ = [ + ('comp_mask', uint32_t), + ('raw_clock', struct_timespec), +] +class struct_verbs_context(Struct): pass +enum_ib_uverbs_advise_mr_advice = CEnum(ctypes.c_uint32) +IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = enum_ib_uverbs_advise_mr_advice.define('IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH', 0) +IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = enum_ib_uverbs_advise_mr_advice.define('IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE', 1) +IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = enum_ib_uverbs_advise_mr_advice.define('IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', 2) + +class struct_verbs_ex_private(Struct): pass +struct_verbs_context._fields_ = [ + ('query_port', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct_ibv_port_attr), size_t)), + ('advise_mr', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_pd), enum_ib_uverbs_advise_mr_advice, uint32_t, ctypes.POINTER(struct_ibv_sge), uint32_t)), + ('alloc_null_mr', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mr), ctypes.POINTER(struct_ibv_pd))), + ('read_counters', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(uint64_t), uint32_t, uint32_t)), + ('attach_counters_point_flow', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_counter_attach_attr), ctypes.POINTER(struct_ibv_flow))), + ('create_counters', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_counters_init_attr))), + ('destroy_counters', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters))), + ('reg_dm_mr', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mr), ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_dm), uint64_t, size_t, ctypes.c_uint32)), + ('alloc_dm', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_dm), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_alloc_dm_attr))), + ('free_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_dm))), + ('modify_flow_action_esp', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_flow_action_esp_attr))), + ('destroy_flow_action', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow_action))), + ('create_flow_action_esp', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_flow_action_esp_attr))), + ('modify_qp_rate_limit', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_rate_limit_attr))), + ('alloc_parent_domain', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_parent_domain_init_attr))), + ('dealloc_td', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_td))), + ('alloc_td', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_td), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_td_init_attr))), + ('modify_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.POINTER(struct_ibv_modify_cq_attr))), + ('post_srq_ops', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_ops_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_ops_wr)))), + ('destroy_rwq_ind_table', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_rwq_ind_table))), + ('create_rwq_ind_table', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_rwq_ind_table), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_rwq_ind_table_init_attr))), + ('destroy_wq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq))), + ('modify_wq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_wq_attr))), + ('create_wq', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_wq_init_attr))), + ('query_rt_values', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_values_ex))), + ('create_cq_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_cq_init_attr_ex))), + ('priv', ctypes.POINTER(struct_verbs_ex_private)), + ('query_device_ex', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_query_device_ex_input), ctypes.POINTER(struct_ibv_device_attr_ex), size_t)), + ('ibv_destroy_flow', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow))), + ('ABI_placeholder2', ctypes.CFUNCTYPE(None, )), + ('ibv_create_flow', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_flow), ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_flow_attr))), + ('ABI_placeholder1', ctypes.CFUNCTYPE(None, )), + ('open_qp', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_open_attr))), + ('create_qp_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_init_attr_ex))), + ('get_srq_num', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(uint32_t))), + ('create_srq_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_srq_init_attr_ex))), + ('open_xrcd', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_xrcd), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_xrcd_init_attr))), + ('close_xrcd', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_xrcd))), + ('_ABI_placeholder3', uint64_t), + ('sz', size_t), + ('context', struct_ibv_context), +] +# struct ibv_device **ibv_get_device_list(int *num_devices) +try: (ibv_get_device_list:=dll.ibv_get_device_list).restype, ibv_get_device_list.argtypes = ctypes.POINTER(ctypes.POINTER(struct_ibv_device)), [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# void ibv_free_device_list(struct ibv_device **list) +try: (ibv_free_device_list:=dll.ibv_free_device_list).restype, ibv_free_device_list.argtypes = None, [ctypes.POINTER(ctypes.POINTER(struct_ibv_device))] +except AttributeError: pass + +# const char *ibv_get_device_name(struct ibv_device *device) +try: (ibv_get_device_name:=dll.ibv_get_device_name).restype, ibv_get_device_name.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(struct_ibv_device)] +except AttributeError: pass + +# int ibv_get_device_index(struct ibv_device *device) +try: (ibv_get_device_index:=dll.ibv_get_device_index).restype, ibv_get_device_index.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_device)] +except AttributeError: pass + +# __be64 ibv_get_device_guid(struct ibv_device *device) +try: (ibv_get_device_guid:=dll.ibv_get_device_guid).restype, ibv_get_device_guid.argtypes = ctypes.c_uint64, [ctypes.POINTER(struct_ibv_device)] +except AttributeError: pass + +# struct ibv_context *ibv_open_device(struct ibv_device *device) +try: (ibv_open_device:=dll.ibv_open_device).restype, ibv_open_device.argtypes = ctypes.POINTER(struct_ibv_context), [ctypes.POINTER(struct_ibv_device)] +except AttributeError: pass + +# int ibv_close_device(struct ibv_context *context) +try: (ibv_close_device:=dll.ibv_close_device).restype, ibv_close_device.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context)] +except AttributeError: pass + +# struct ibv_context *ibv_import_device(int cmd_fd) +try: (ibv_import_device:=dll.ibv_import_device).restype, ibv_import_device.argtypes = ctypes.POINTER(struct_ibv_context), [ctypes.c_int32] +except AttributeError: pass + +# struct ibv_pd *ibv_import_pd(struct ibv_context *context, uint32_t pd_handle) +try: (ibv_import_pd:=dll.ibv_import_pd).restype, ibv_import_pd.argtypes = ctypes.POINTER(struct_ibv_pd), [ctypes.POINTER(struct_ibv_context), uint32_t] +except AttributeError: pass + +# void ibv_unimport_pd(struct ibv_pd *pd) +try: (ibv_unimport_pd:=dll.ibv_unimport_pd).restype, ibv_unimport_pd.argtypes = None, [ctypes.POINTER(struct_ibv_pd)] +except AttributeError: pass + +# struct ibv_mr *ibv_import_mr(struct ibv_pd *pd, uint32_t mr_handle) +try: (ibv_import_mr:=dll.ibv_import_mr).restype, ibv_import_mr.argtypes = ctypes.POINTER(struct_ibv_mr), [ctypes.POINTER(struct_ibv_pd), uint32_t] +except AttributeError: pass + +# void ibv_unimport_mr(struct ibv_mr *mr) +try: (ibv_unimport_mr:=dll.ibv_unimport_mr).restype, ibv_unimport_mr.argtypes = None, [ctypes.POINTER(struct_ibv_mr)] +except AttributeError: pass + +# struct ibv_dm *ibv_import_dm(struct ibv_context *context, uint32_t dm_handle) +try: (ibv_import_dm:=dll.ibv_import_dm).restype, ibv_import_dm.argtypes = ctypes.POINTER(struct_ibv_dm), [ctypes.POINTER(struct_ibv_context), uint32_t] +except AttributeError: pass + +# void ibv_unimport_dm(struct ibv_dm *dm) +try: (ibv_unimport_dm:=dll.ibv_unimport_dm).restype, ibv_unimport_dm.argtypes = None, [ctypes.POINTER(struct_ibv_dm)] +except AttributeError: pass + +# int ibv_get_async_event(struct ibv_context *context, struct ibv_async_event *event) +try: (ibv_get_async_event:=dll.ibv_get_async_event).restype, ibv_get_async_event.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_async_event)] +except AttributeError: pass + +# void ibv_ack_async_event(struct ibv_async_event *event) +try: (ibv_ack_async_event:=dll.ibv_ack_async_event).restype, ibv_ack_async_event.argtypes = None, [ctypes.POINTER(struct_ibv_async_event)] +except AttributeError: pass + +# int ibv_query_device(struct ibv_context *context, struct ibv_device_attr *device_attr) +try: (ibv_query_device:=dll.ibv_query_device).restype, ibv_query_device.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device_attr)] +except AttributeError: pass + +# int ibv_query_port(struct ibv_context *context, uint8_t port_num, struct _compat_ibv_port_attr *port_attr) +try: (ibv_query_port:=dll.ibv_query_port).restype, ibv_query_port.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct__compat_ibv_port_attr)] +except AttributeError: pass + +# int ibv_query_gid(struct ibv_context *context, uint8_t port_num, int index, union ibv_gid *gid) +try: (ibv_query_gid:=dll.ibv_query_gid).restype, ibv_query_gid.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_int32, ctypes.POINTER(union_ibv_gid)] +except AttributeError: pass + +# int _ibv_query_gid_ex(struct ibv_context *context, uint32_t port_num, uint32_t gid_index, struct ibv_gid_entry *entry, uint32_t flags, size_t entry_size) +try: (_ibv_query_gid_ex:=dll._ibv_query_gid_ex).restype, _ibv_query_gid_ex.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), uint32_t, uint32_t, ctypes.POINTER(struct_ibv_gid_entry), uint32_t, size_t] +except AttributeError: pass + +ssize_t = ctypes.c_int64 +# ssize_t _ibv_query_gid_table(struct ibv_context *context, struct ibv_gid_entry *entries, size_t max_entries, uint32_t flags, size_t entry_size) +try: (_ibv_query_gid_table:=dll._ibv_query_gid_table).restype, _ibv_query_gid_table.argtypes = ssize_t, [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_gid_entry), size_t, uint32_t, size_t] +except AttributeError: pass + +# int ibv_query_pkey(struct ibv_context *context, uint8_t port_num, int index, __be16 *pkey) +try: (ibv_query_pkey:=dll.ibv_query_pkey).restype, ibv_query_pkey.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint16)] +except AttributeError: pass + +# int ibv_get_pkey_index(struct ibv_context *context, uint8_t port_num, __be16 pkey) +try: (ibv_get_pkey_index:=dll.ibv_get_pkey_index).restype, ibv_get_pkey_index.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_uint16] +except AttributeError: pass + +# struct ibv_pd *ibv_alloc_pd(struct ibv_context *context) +try: (ibv_alloc_pd:=dll.ibv_alloc_pd).restype, ibv_alloc_pd.argtypes = ctypes.POINTER(struct_ibv_pd), [ctypes.POINTER(struct_ibv_context)] +except AttributeError: pass + +# int ibv_dealloc_pd(struct ibv_pd *pd) +try: (ibv_dealloc_pd:=dll.ibv_dealloc_pd).restype, ibv_dealloc_pd.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_pd)] +except AttributeError: pass + +# struct ibv_mr *ibv_reg_mr_iova2(struct ibv_pd *pd, void *addr, size_t length, uint64_t iova, unsigned int access) +try: (ibv_reg_mr_iova2:=dll.ibv_reg_mr_iova2).restype, ibv_reg_mr_iova2.argtypes = ctypes.POINTER(struct_ibv_mr), [ctypes.POINTER(struct_ibv_pd), ctypes.c_void_p, size_t, uint64_t, ctypes.c_uint32] +except AttributeError: pass + +# struct ibv_mr *ibv_reg_mr(struct ibv_pd *pd, void *addr, size_t length, int access) +try: (ibv_reg_mr:=dll.ibv_reg_mr).restype, ibv_reg_mr.argtypes = ctypes.POINTER(struct_ibv_mr), [ctypes.POINTER(struct_ibv_pd), ctypes.c_void_p, size_t, ctypes.c_int32] +except AttributeError: pass + +# struct ibv_mr *ibv_reg_mr_iova(struct ibv_pd *pd, void *addr, size_t length, uint64_t iova, int access) +try: (ibv_reg_mr_iova:=dll.ibv_reg_mr_iova).restype, ibv_reg_mr_iova.argtypes = ctypes.POINTER(struct_ibv_mr), [ctypes.POINTER(struct_ibv_pd), ctypes.c_void_p, size_t, uint64_t, ctypes.c_int32] +except AttributeError: pass + +# struct ibv_mr *ibv_reg_dmabuf_mr(struct ibv_pd *pd, uint64_t offset, size_t length, uint64_t iova, int fd, int access) +try: (ibv_reg_dmabuf_mr:=dll.ibv_reg_dmabuf_mr).restype, ibv_reg_dmabuf_mr.argtypes = ctypes.POINTER(struct_ibv_mr), [ctypes.POINTER(struct_ibv_pd), uint64_t, size_t, uint64_t, ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +enum_ibv_rereg_mr_err_code = CEnum(ctypes.c_int32) +IBV_REREG_MR_ERR_INPUT = enum_ibv_rereg_mr_err_code.define('IBV_REREG_MR_ERR_INPUT', -1) +IBV_REREG_MR_ERR_DONT_FORK_NEW = enum_ibv_rereg_mr_err_code.define('IBV_REREG_MR_ERR_DONT_FORK_NEW', -2) +IBV_REREG_MR_ERR_DO_FORK_OLD = enum_ibv_rereg_mr_err_code.define('IBV_REREG_MR_ERR_DO_FORK_OLD', -3) +IBV_REREG_MR_ERR_CMD = enum_ibv_rereg_mr_err_code.define('IBV_REREG_MR_ERR_CMD', -4) +IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW = enum_ibv_rereg_mr_err_code.define('IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW', -5) + +# int ibv_rereg_mr(struct ibv_mr *mr, int flags, struct ibv_pd *pd, void *addr, size_t length, int access) +try: (ibv_rereg_mr:=dll.ibv_rereg_mr).restype, ibv_rereg_mr.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_mr), ctypes.c_int32, ctypes.POINTER(struct_ibv_pd), ctypes.c_void_p, size_t, ctypes.c_int32] +except AttributeError: pass + +# int ibv_dereg_mr(struct ibv_mr *mr) +try: (ibv_dereg_mr:=dll.ibv_dereg_mr).restype, ibv_dereg_mr.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_mr)] +except AttributeError: pass + +# struct ibv_comp_channel *ibv_create_comp_channel(struct ibv_context *context) +try: (ibv_create_comp_channel:=dll.ibv_create_comp_channel).restype, ibv_create_comp_channel.argtypes = ctypes.POINTER(struct_ibv_comp_channel), [ctypes.POINTER(struct_ibv_context)] +except AttributeError: pass + +# int ibv_destroy_comp_channel(struct ibv_comp_channel *channel) +try: (ibv_destroy_comp_channel:=dll.ibv_destroy_comp_channel).restype, ibv_destroy_comp_channel.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_comp_channel)] +except AttributeError: pass + +# struct ibv_cq *ibv_create_cq(struct ibv_context *context, int cqe, void *cq_context, struct ibv_comp_channel *channel, int comp_vector) +try: (ibv_create_cq:=dll.ibv_create_cq).restype, ibv_create_cq.argtypes = ctypes.POINTER(struct_ibv_cq), [ctypes.POINTER(struct_ibv_context), ctypes.c_int32, ctypes.c_void_p, ctypes.POINTER(struct_ibv_comp_channel), ctypes.c_int32] +except AttributeError: pass + +# int ibv_resize_cq(struct ibv_cq *cq, int cqe) +try: (ibv_resize_cq:=dll.ibv_resize_cq).restype, ibv_resize_cq.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32] +except AttributeError: pass + +# int ibv_destroy_cq(struct ibv_cq *cq) +try: (ibv_destroy_cq:=dll.ibv_destroy_cq).restype, ibv_destroy_cq.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_cq)] +except AttributeError: pass + +# int ibv_get_cq_event(struct ibv_comp_channel *channel, struct ibv_cq **cq, void **cq_context) +try: (ibv_get_cq_event:=dll.ibv_get_cq_event).restype, ibv_get_cq_event.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_comp_channel), ctypes.POINTER(ctypes.POINTER(struct_ibv_cq)), ctypes.POINTER(ctypes.c_void_p)] +except AttributeError: pass + +# void ibv_ack_cq_events(struct ibv_cq *cq, unsigned int nevents) +try: (ibv_ack_cq_events:=dll.ibv_ack_cq_events).restype, ibv_ack_cq_events.argtypes = None, [ctypes.POINTER(struct_ibv_cq), ctypes.c_uint32] +except AttributeError: pass + +# struct ibv_srq *ibv_create_srq(struct ibv_pd *pd, struct ibv_srq_init_attr *srq_init_attr) +try: (ibv_create_srq:=dll.ibv_create_srq).restype, ibv_create_srq.argtypes = ctypes.POINTER(struct_ibv_srq), [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_srq_init_attr)] +except AttributeError: pass + +# int ibv_modify_srq(struct ibv_srq *srq, struct ibv_srq_attr *srq_attr, int srq_attr_mask) +try: (ibv_modify_srq:=dll.ibv_modify_srq).restype, ibv_modify_srq.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_srq_attr), ctypes.c_int32] +except AttributeError: pass + +# int ibv_query_srq(struct ibv_srq *srq, struct ibv_srq_attr *srq_attr) +try: (ibv_query_srq:=dll.ibv_query_srq).restype, ibv_query_srq.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_srq_attr)] +except AttributeError: pass + +# int ibv_destroy_srq(struct ibv_srq *srq) +try: (ibv_destroy_srq:=dll.ibv_destroy_srq).restype, ibv_destroy_srq.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_srq)] +except AttributeError: pass + +# struct ibv_qp *ibv_create_qp(struct ibv_pd *pd, struct ibv_qp_init_attr *qp_init_attr) +try: (ibv_create_qp:=dll.ibv_create_qp).restype, ibv_create_qp.argtypes = ctypes.POINTER(struct_ibv_qp), [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_qp_init_attr)] +except AttributeError: pass + +# int ibv_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, int attr_mask) +try: (ibv_modify_qp:=dll.ibv_modify_qp).restype, ibv_modify_qp.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_attr), ctypes.c_int32] +except AttributeError: pass + +# int ibv_query_qp_data_in_order(struct ibv_qp *qp, enum ibv_wr_opcode op, uint32_t flags) +try: (ibv_query_qp_data_in_order:=dll.ibv_query_qp_data_in_order).restype, ibv_query_qp_data_in_order.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), enum_ibv_wr_opcode, uint32_t] +except AttributeError: pass + +# int ibv_query_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, int attr_mask, struct ibv_qp_init_attr *init_attr) +try: (ibv_query_qp:=dll.ibv_query_qp).restype, ibv_query_qp.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_attr), ctypes.c_int32, ctypes.POINTER(struct_ibv_qp_init_attr)] +except AttributeError: pass + +# int ibv_destroy_qp(struct ibv_qp *qp) +try: (ibv_destroy_qp:=dll.ibv_destroy_qp).restype, ibv_destroy_qp.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp)] +except AttributeError: pass + +# struct ibv_ah *ibv_create_ah(struct ibv_pd *pd, struct ibv_ah_attr *attr) +try: (ibv_create_ah:=dll.ibv_create_ah).restype, ibv_create_ah.argtypes = ctypes.POINTER(struct_ibv_ah), [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_ah_attr)] +except AttributeError: pass + +# int ibv_init_ah_from_wc(struct ibv_context *context, uint8_t port_num, struct ibv_wc *wc, struct ibv_grh *grh, struct ibv_ah_attr *ah_attr) +try: (ibv_init_ah_from_wc:=dll.ibv_init_ah_from_wc).restype, ibv_init_ah_from_wc.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct_ibv_wc), ctypes.POINTER(struct_ibv_grh), ctypes.POINTER(struct_ibv_ah_attr)] +except AttributeError: pass + +# struct ibv_ah *ibv_create_ah_from_wc(struct ibv_pd *pd, struct ibv_wc *wc, struct ibv_grh *grh, uint8_t port_num) +try: (ibv_create_ah_from_wc:=dll.ibv_create_ah_from_wc).restype, ibv_create_ah_from_wc.argtypes = ctypes.POINTER(struct_ibv_ah), [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_wc), ctypes.POINTER(struct_ibv_grh), uint8_t] +except AttributeError: pass + +# int ibv_destroy_ah(struct ibv_ah *ah) +try: (ibv_destroy_ah:=dll.ibv_destroy_ah).restype, ibv_destroy_ah.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_ah)] +except AttributeError: pass + +# int ibv_attach_mcast(struct ibv_qp *qp, const union ibv_gid *gid, uint16_t lid) +try: (ibv_attach_mcast:=dll.ibv_attach_mcast).restype, ibv_attach_mcast.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(union_ibv_gid), uint16_t] +except AttributeError: pass + +# int ibv_detach_mcast(struct ibv_qp *qp, const union ibv_gid *gid, uint16_t lid) +try: (ibv_detach_mcast:=dll.ibv_detach_mcast).restype, ibv_detach_mcast.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(union_ibv_gid), uint16_t] +except AttributeError: pass + +# int ibv_fork_init(void) +try: (ibv_fork_init:=dll.ibv_fork_init).restype, ibv_fork_init.argtypes = ctypes.c_int32, [] +except AttributeError: pass + +# enum ibv_fork_status ibv_is_fork_initialized(void) +try: (ibv_is_fork_initialized:=dll.ibv_is_fork_initialized).restype, ibv_is_fork_initialized.argtypes = enum_ibv_fork_status, [] +except AttributeError: pass + +# const char *ibv_node_type_str(enum ibv_node_type node_type) +try: (ibv_node_type_str:=dll.ibv_node_type_str).restype, ibv_node_type_str.argtypes = ctypes.POINTER(ctypes.c_char), [enum_ibv_node_type] +except AttributeError: pass + +# const char *ibv_port_state_str(enum ibv_port_state port_state) +try: (ibv_port_state_str:=dll.ibv_port_state_str).restype, ibv_port_state_str.argtypes = ctypes.POINTER(ctypes.c_char), [enum_ibv_port_state] +except AttributeError: pass + +# const char *ibv_event_type_str(enum ibv_event_type event) +try: (ibv_event_type_str:=dll.ibv_event_type_str).restype, ibv_event_type_str.argtypes = ctypes.POINTER(ctypes.c_char), [enum_ibv_event_type] +except AttributeError: pass + +# int ibv_resolve_eth_l2_from_gid(struct ibv_context *context, struct ibv_ah_attr *attr, uint8_t eth_mac[6], uint16_t *vid) +try: (ibv_resolve_eth_l2_from_gid:=dll.ibv_resolve_eth_l2_from_gid).restype, ibv_resolve_eth_l2_from_gid.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_ah_attr), (uint8_t * 6), ctypes.POINTER(uint16_t)] +except AttributeError: pass + +# int ibv_set_ece(struct ibv_qp *qp, struct ibv_ece *ece) +try: (ibv_set_ece:=dll.ibv_set_ece).restype, ibv_set_ece.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_ece)] +except AttributeError: pass + +# int ibv_query_ece(struct ibv_qp *qp, struct ibv_ece *ece) +try: (ibv_query_ece:=dll.ibv_query_ece).restype, ibv_query_ece.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_ece)] +except AttributeError: pass + +enum_ib_uverbs_core_support = CEnum(ctypes.c_uint32) +IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS = enum_ib_uverbs_core_support.define('IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS', 1) + +enum_ib_uverbs_access_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_ACCESS_LOCAL_WRITE = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_LOCAL_WRITE', 1) +IB_UVERBS_ACCESS_REMOTE_WRITE = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_REMOTE_WRITE', 2) +IB_UVERBS_ACCESS_REMOTE_READ = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_REMOTE_READ', 4) +IB_UVERBS_ACCESS_REMOTE_ATOMIC = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_REMOTE_ATOMIC', 8) +IB_UVERBS_ACCESS_MW_BIND = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_MW_BIND', 16) +IB_UVERBS_ACCESS_ZERO_BASED = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_ZERO_BASED', 32) +IB_UVERBS_ACCESS_ON_DEMAND = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_ON_DEMAND', 64) +IB_UVERBS_ACCESS_HUGETLB = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_HUGETLB', 128) +IB_UVERBS_ACCESS_FLUSH_GLOBAL = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_FLUSH_GLOBAL', 256) +IB_UVERBS_ACCESS_FLUSH_PERSISTENT = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_FLUSH_PERSISTENT', 512) +IB_UVERBS_ACCESS_RELAXED_ORDERING = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_RELAXED_ORDERING', 1048576) +IB_UVERBS_ACCESS_OPTIONAL_RANGE = enum_ib_uverbs_access_flags.define('IB_UVERBS_ACCESS_OPTIONAL_RANGE', 1072693248) + +enum_ib_uverbs_srq_type = CEnum(ctypes.c_uint32) +IB_UVERBS_SRQT_BASIC = enum_ib_uverbs_srq_type.define('IB_UVERBS_SRQT_BASIC', 0) +IB_UVERBS_SRQT_XRC = enum_ib_uverbs_srq_type.define('IB_UVERBS_SRQT_XRC', 1) +IB_UVERBS_SRQT_TM = enum_ib_uverbs_srq_type.define('IB_UVERBS_SRQT_TM', 2) + +enum_ib_uverbs_wq_type = CEnum(ctypes.c_uint32) +IB_UVERBS_WQT_RQ = enum_ib_uverbs_wq_type.define('IB_UVERBS_WQT_RQ', 0) + +enum_ib_uverbs_wq_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = enum_ib_uverbs_wq_flags.define('IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING', 1) +IB_UVERBS_WQ_FLAGS_SCATTER_FCS = enum_ib_uverbs_wq_flags.define('IB_UVERBS_WQ_FLAGS_SCATTER_FCS', 2) +IB_UVERBS_WQ_FLAGS_DELAY_DROP = enum_ib_uverbs_wq_flags.define('IB_UVERBS_WQ_FLAGS_DELAY_DROP', 4) +IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = enum_ib_uverbs_wq_flags.define('IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING', 8) + +enum_ib_uverbs_qp_type = CEnum(ctypes.c_uint32) +IB_UVERBS_QPT_RC = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_RC', 2) +IB_UVERBS_QPT_UC = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_UC', 3) +IB_UVERBS_QPT_UD = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_UD', 4) +IB_UVERBS_QPT_RAW_PACKET = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_RAW_PACKET', 8) +IB_UVERBS_QPT_XRC_INI = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_XRC_INI', 9) +IB_UVERBS_QPT_XRC_TGT = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_XRC_TGT', 10) +IB_UVERBS_QPT_DRIVER = enum_ib_uverbs_qp_type.define('IB_UVERBS_QPT_DRIVER', 255) + +enum_ib_uverbs_qp_create_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = enum_ib_uverbs_qp_create_flags.define('IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK', 2) +IB_UVERBS_QP_CREATE_SCATTER_FCS = enum_ib_uverbs_qp_create_flags.define('IB_UVERBS_QP_CREATE_SCATTER_FCS', 256) +IB_UVERBS_QP_CREATE_CVLAN_STRIPPING = enum_ib_uverbs_qp_create_flags.define('IB_UVERBS_QP_CREATE_CVLAN_STRIPPING', 512) +IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = enum_ib_uverbs_qp_create_flags.define('IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING', 2048) +IB_UVERBS_QP_CREATE_SQ_SIG_ALL = enum_ib_uverbs_qp_create_flags.define('IB_UVERBS_QP_CREATE_SQ_SIG_ALL', 4096) + +enum_ib_uverbs_query_port_cap_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_PCF_SM = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_SM', 2) +IB_UVERBS_PCF_NOTICE_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_NOTICE_SUP', 4) +IB_UVERBS_PCF_TRAP_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_TRAP_SUP', 8) +IB_UVERBS_PCF_OPT_IPD_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_OPT_IPD_SUP', 16) +IB_UVERBS_PCF_AUTO_MIGR_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_AUTO_MIGR_SUP', 32) +IB_UVERBS_PCF_SL_MAP_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_SL_MAP_SUP', 64) +IB_UVERBS_PCF_MKEY_NVRAM = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_MKEY_NVRAM', 128) +IB_UVERBS_PCF_PKEY_NVRAM = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_PKEY_NVRAM', 256) +IB_UVERBS_PCF_LED_INFO_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_LED_INFO_SUP', 512) +IB_UVERBS_PCF_SM_DISABLED = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_SM_DISABLED', 1024) +IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP', 2048) +IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP', 4096) +IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP', 16384) +IB_UVERBS_PCF_CM_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_CM_SUP', 65536) +IB_UVERBS_PCF_SNMP_TUNNEL_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_SNMP_TUNNEL_SUP', 131072) +IB_UVERBS_PCF_REINIT_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_REINIT_SUP', 262144) +IB_UVERBS_PCF_DEVICE_MGMT_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_DEVICE_MGMT_SUP', 524288) +IB_UVERBS_PCF_VENDOR_CLASS_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_VENDOR_CLASS_SUP', 1048576) +IB_UVERBS_PCF_DR_NOTICE_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_DR_NOTICE_SUP', 2097152) +IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP', 4194304) +IB_UVERBS_PCF_BOOT_MGMT_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_BOOT_MGMT_SUP', 8388608) +IB_UVERBS_PCF_LINK_LATENCY_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_LINK_LATENCY_SUP', 16777216) +IB_UVERBS_PCF_CLIENT_REG_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_CLIENT_REG_SUP', 33554432) +IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP', 134217728) +IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP', 268435456) +IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP', 536870912) +IB_UVERBS_PCF_MCAST_FDB_TOP_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_MCAST_FDB_TOP_SUP', 1073741824) +IB_UVERBS_PCF_HIERARCHY_INFO_SUP = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_HIERARCHY_INFO_SUP', 2147483648) +IB_UVERBS_PCF_IP_BASED_GIDS = enum_ib_uverbs_query_port_cap_flags.define('IB_UVERBS_PCF_IP_BASED_GIDS', 67108864) + +enum_ib_uverbs_query_port_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_QPF_GRH_REQUIRED = enum_ib_uverbs_query_port_flags.define('IB_UVERBS_QPF_GRH_REQUIRED', 1) + +enum_ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo = CEnum(ctypes.c_uint32) +IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ = enum_ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo.define('IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ', 0) + +class struct_ib_uverbs_flow_action_esp_keymat_aes_gcm(Struct): pass +struct_ib_uverbs_flow_action_esp_keymat_aes_gcm._fields_ = [ + ('iv', ctypes.c_uint64), + ('iv_algo', ctypes.c_uint32), + ('salt', ctypes.c_uint32), + ('icv_len', ctypes.c_uint32), + ('key_len', ctypes.c_uint32), + ('aes_key', (ctypes.c_uint32 * 8)), +] +class struct_ib_uverbs_flow_action_esp_replay_bmp(Struct): pass +struct_ib_uverbs_flow_action_esp_replay_bmp._fields_ = [ + ('size', ctypes.c_uint32), +] +enum_ib_uverbs_flow_action_esp_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', 0) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', 1) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL', 0) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT', 2) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT', 0) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT', 4) +IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = enum_ib_uverbs_flow_action_esp_flags.define('IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', 8) + +enum_ib_uverbs_read_counters_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_READ_COUNTERS_PREFER_CACHED = enum_ib_uverbs_read_counters_flags.define('IB_UVERBS_READ_COUNTERS_PREFER_CACHED', 1) + +enum_ib_uverbs_advise_mr_flag = CEnum(ctypes.c_uint32) +IB_UVERBS_ADVISE_MR_FLAG_FLUSH = enum_ib_uverbs_advise_mr_flag.define('IB_UVERBS_ADVISE_MR_FLAG_FLUSH', 1) + +class struct_ib_uverbs_query_port_resp_ex(Struct): pass +class struct_ib_uverbs_query_port_resp(Struct): pass +__u8 = ctypes.c_ubyte +struct_ib_uverbs_query_port_resp._fields_ = [ + ('port_cap_flags', ctypes.c_uint32), + ('max_msg_sz', ctypes.c_uint32), + ('bad_pkey_cntr', ctypes.c_uint32), + ('qkey_viol_cntr', ctypes.c_uint32), + ('gid_tbl_len', ctypes.c_uint32), + ('pkey_tbl_len', ctypes.c_uint16), + ('lid', ctypes.c_uint16), + ('sm_lid', ctypes.c_uint16), + ('state', ctypes.c_ubyte), + ('max_mtu', ctypes.c_ubyte), + ('active_mtu', ctypes.c_ubyte), + ('lmc', ctypes.c_ubyte), + ('max_vl_num', ctypes.c_ubyte), + ('sm_sl', ctypes.c_ubyte), + ('subnet_timeout', ctypes.c_ubyte), + ('init_type_reply', ctypes.c_ubyte), + ('active_width', ctypes.c_ubyte), + ('active_speed', ctypes.c_ubyte), + ('phys_state', ctypes.c_ubyte), + ('link_layer', ctypes.c_ubyte), + ('flags', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), +] +struct_ib_uverbs_query_port_resp_ex._fields_ = [ + ('legacy_resp', struct_ib_uverbs_query_port_resp), + ('port_cap_flags2', ctypes.c_uint16), + ('reserved', (ctypes.c_ubyte * 2)), + ('active_speed_ex', ctypes.c_uint32), +] +class struct_ib_uverbs_qp_cap(Struct): pass +struct_ib_uverbs_qp_cap._fields_ = [ + ('max_send_wr', ctypes.c_uint32), + ('max_recv_wr', ctypes.c_uint32), + ('max_send_sge', ctypes.c_uint32), + ('max_recv_sge', ctypes.c_uint32), + ('max_inline_data', ctypes.c_uint32), +] +enum_rdma_driver_id = CEnum(ctypes.c_uint32) +RDMA_DRIVER_UNKNOWN = enum_rdma_driver_id.define('RDMA_DRIVER_UNKNOWN', 0) +RDMA_DRIVER_MLX5 = enum_rdma_driver_id.define('RDMA_DRIVER_MLX5', 1) +RDMA_DRIVER_MLX4 = enum_rdma_driver_id.define('RDMA_DRIVER_MLX4', 2) +RDMA_DRIVER_CXGB3 = enum_rdma_driver_id.define('RDMA_DRIVER_CXGB3', 3) +RDMA_DRIVER_CXGB4 = enum_rdma_driver_id.define('RDMA_DRIVER_CXGB4', 4) +RDMA_DRIVER_MTHCA = enum_rdma_driver_id.define('RDMA_DRIVER_MTHCA', 5) +RDMA_DRIVER_BNXT_RE = enum_rdma_driver_id.define('RDMA_DRIVER_BNXT_RE', 6) +RDMA_DRIVER_OCRDMA = enum_rdma_driver_id.define('RDMA_DRIVER_OCRDMA', 7) +RDMA_DRIVER_NES = enum_rdma_driver_id.define('RDMA_DRIVER_NES', 8) +RDMA_DRIVER_I40IW = enum_rdma_driver_id.define('RDMA_DRIVER_I40IW', 9) +RDMA_DRIVER_IRDMA = enum_rdma_driver_id.define('RDMA_DRIVER_IRDMA', 9) +RDMA_DRIVER_VMW_PVRDMA = enum_rdma_driver_id.define('RDMA_DRIVER_VMW_PVRDMA', 10) +RDMA_DRIVER_QEDR = enum_rdma_driver_id.define('RDMA_DRIVER_QEDR', 11) +RDMA_DRIVER_HNS = enum_rdma_driver_id.define('RDMA_DRIVER_HNS', 12) +RDMA_DRIVER_USNIC = enum_rdma_driver_id.define('RDMA_DRIVER_USNIC', 13) +RDMA_DRIVER_RXE = enum_rdma_driver_id.define('RDMA_DRIVER_RXE', 14) +RDMA_DRIVER_HFI1 = enum_rdma_driver_id.define('RDMA_DRIVER_HFI1', 15) +RDMA_DRIVER_QIB = enum_rdma_driver_id.define('RDMA_DRIVER_QIB', 16) +RDMA_DRIVER_EFA = enum_rdma_driver_id.define('RDMA_DRIVER_EFA', 17) +RDMA_DRIVER_SIW = enum_rdma_driver_id.define('RDMA_DRIVER_SIW', 18) +RDMA_DRIVER_ERDMA = enum_rdma_driver_id.define('RDMA_DRIVER_ERDMA', 19) +RDMA_DRIVER_MANA = enum_rdma_driver_id.define('RDMA_DRIVER_MANA', 20) + +enum_ib_uverbs_gid_type = CEnum(ctypes.c_uint32) +IB_UVERBS_GID_TYPE_IB = enum_ib_uverbs_gid_type.define('IB_UVERBS_GID_TYPE_IB', 0) +IB_UVERBS_GID_TYPE_ROCE_V1 = enum_ib_uverbs_gid_type.define('IB_UVERBS_GID_TYPE_ROCE_V1', 1) +IB_UVERBS_GID_TYPE_ROCE_V2 = enum_ib_uverbs_gid_type.define('IB_UVERBS_GID_TYPE_ROCE_V2', 2) + +class struct_ib_uverbs_gid_entry(Struct): pass +struct_ib_uverbs_gid_entry._fields_ = [ + ('gid', (ctypes.c_uint64 * 2)), + ('gid_index', ctypes.c_uint32), + ('port_num', ctypes.c_uint32), + ('gid_type', ctypes.c_uint32), + ('netdev_ifindex', ctypes.c_uint32), +] +enum_ib_uverbs_write_cmds = CEnum(ctypes.c_uint32) +IB_USER_VERBS_CMD_GET_CONTEXT = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_GET_CONTEXT', 0) +IB_USER_VERBS_CMD_QUERY_DEVICE = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_QUERY_DEVICE', 1) +IB_USER_VERBS_CMD_QUERY_PORT = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_QUERY_PORT', 2) +IB_USER_VERBS_CMD_ALLOC_PD = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_ALLOC_PD', 3) +IB_USER_VERBS_CMD_DEALLOC_PD = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DEALLOC_PD', 4) +IB_USER_VERBS_CMD_CREATE_AH = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CREATE_AH', 5) +IB_USER_VERBS_CMD_MODIFY_AH = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_MODIFY_AH', 6) +IB_USER_VERBS_CMD_QUERY_AH = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_QUERY_AH', 7) +IB_USER_VERBS_CMD_DESTROY_AH = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DESTROY_AH', 8) +IB_USER_VERBS_CMD_REG_MR = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_REG_MR', 9) +IB_USER_VERBS_CMD_REG_SMR = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_REG_SMR', 10) +IB_USER_VERBS_CMD_REREG_MR = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_REREG_MR', 11) +IB_USER_VERBS_CMD_QUERY_MR = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_QUERY_MR', 12) +IB_USER_VERBS_CMD_DEREG_MR = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DEREG_MR', 13) +IB_USER_VERBS_CMD_ALLOC_MW = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_ALLOC_MW', 14) +IB_USER_VERBS_CMD_BIND_MW = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_BIND_MW', 15) +IB_USER_VERBS_CMD_DEALLOC_MW = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DEALLOC_MW', 16) +IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL', 17) +IB_USER_VERBS_CMD_CREATE_CQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CREATE_CQ', 18) +IB_USER_VERBS_CMD_RESIZE_CQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_RESIZE_CQ', 19) +IB_USER_VERBS_CMD_DESTROY_CQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DESTROY_CQ', 20) +IB_USER_VERBS_CMD_POLL_CQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_POLL_CQ', 21) +IB_USER_VERBS_CMD_PEEK_CQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_PEEK_CQ', 22) +IB_USER_VERBS_CMD_REQ_NOTIFY_CQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_REQ_NOTIFY_CQ', 23) +IB_USER_VERBS_CMD_CREATE_QP = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CREATE_QP', 24) +IB_USER_VERBS_CMD_QUERY_QP = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_QUERY_QP', 25) +IB_USER_VERBS_CMD_MODIFY_QP = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_MODIFY_QP', 26) +IB_USER_VERBS_CMD_DESTROY_QP = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DESTROY_QP', 27) +IB_USER_VERBS_CMD_POST_SEND = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_POST_SEND', 28) +IB_USER_VERBS_CMD_POST_RECV = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_POST_RECV', 29) +IB_USER_VERBS_CMD_ATTACH_MCAST = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_ATTACH_MCAST', 30) +IB_USER_VERBS_CMD_DETACH_MCAST = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DETACH_MCAST', 31) +IB_USER_VERBS_CMD_CREATE_SRQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CREATE_SRQ', 32) +IB_USER_VERBS_CMD_MODIFY_SRQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_MODIFY_SRQ', 33) +IB_USER_VERBS_CMD_QUERY_SRQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_QUERY_SRQ', 34) +IB_USER_VERBS_CMD_DESTROY_SRQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_DESTROY_SRQ', 35) +IB_USER_VERBS_CMD_POST_SRQ_RECV = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_POST_SRQ_RECV', 36) +IB_USER_VERBS_CMD_OPEN_XRCD = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_OPEN_XRCD', 37) +IB_USER_VERBS_CMD_CLOSE_XRCD = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CLOSE_XRCD', 38) +IB_USER_VERBS_CMD_CREATE_XSRQ = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_CREATE_XSRQ', 39) +IB_USER_VERBS_CMD_OPEN_QP = enum_ib_uverbs_write_cmds.define('IB_USER_VERBS_CMD_OPEN_QP', 40) + +_anonenum5 = CEnum(ctypes.c_uint32) +IB_USER_VERBS_EX_CMD_QUERY_DEVICE = _anonenum5.define('IB_USER_VERBS_EX_CMD_QUERY_DEVICE', 1) +IB_USER_VERBS_EX_CMD_CREATE_CQ = _anonenum5.define('IB_USER_VERBS_EX_CMD_CREATE_CQ', 18) +IB_USER_VERBS_EX_CMD_CREATE_QP = _anonenum5.define('IB_USER_VERBS_EX_CMD_CREATE_QP', 24) +IB_USER_VERBS_EX_CMD_MODIFY_QP = _anonenum5.define('IB_USER_VERBS_EX_CMD_MODIFY_QP', 26) +IB_USER_VERBS_EX_CMD_CREATE_FLOW = _anonenum5.define('IB_USER_VERBS_EX_CMD_CREATE_FLOW', 50) +IB_USER_VERBS_EX_CMD_DESTROY_FLOW = _anonenum5.define('IB_USER_VERBS_EX_CMD_DESTROY_FLOW', 51) +IB_USER_VERBS_EX_CMD_CREATE_WQ = _anonenum5.define('IB_USER_VERBS_EX_CMD_CREATE_WQ', 52) +IB_USER_VERBS_EX_CMD_MODIFY_WQ = _anonenum5.define('IB_USER_VERBS_EX_CMD_MODIFY_WQ', 53) +IB_USER_VERBS_EX_CMD_DESTROY_WQ = _anonenum5.define('IB_USER_VERBS_EX_CMD_DESTROY_WQ', 54) +IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL = _anonenum5.define('IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL', 55) +IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL = _anonenum5.define('IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL', 56) +IB_USER_VERBS_EX_CMD_MODIFY_CQ = _anonenum5.define('IB_USER_VERBS_EX_CMD_MODIFY_CQ', 57) + +enum_ib_placement_type = CEnum(ctypes.c_uint32) +IB_FLUSH_GLOBAL = enum_ib_placement_type.define('IB_FLUSH_GLOBAL', 1) +IB_FLUSH_PERSISTENT = enum_ib_placement_type.define('IB_FLUSH_PERSISTENT', 2) + +enum_ib_selectivity_level = CEnum(ctypes.c_uint32) +IB_FLUSH_RANGE = enum_ib_selectivity_level.define('IB_FLUSH_RANGE', 0) +IB_FLUSH_MR = enum_ib_selectivity_level.define('IB_FLUSH_MR', 1) + +class struct_ib_uverbs_async_event_desc(Struct): pass +struct_ib_uverbs_async_event_desc._fields_ = [ + ('element', ctypes.c_uint64), + ('event_type', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_comp_event_desc(Struct): pass +struct_ib_uverbs_comp_event_desc._fields_ = [ + ('cq_handle', ctypes.c_uint64), +] +class struct_ib_uverbs_cq_moderation_caps(Struct): pass +struct_ib_uverbs_cq_moderation_caps._fields_ = [ + ('max_cq_moderation_count', ctypes.c_uint16), + ('max_cq_moderation_period', ctypes.c_uint16), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_cmd_hdr(Struct): pass +struct_ib_uverbs_cmd_hdr._fields_ = [ + ('command', ctypes.c_uint32), + ('in_words', ctypes.c_uint16), + ('out_words', ctypes.c_uint16), +] +class struct_ib_uverbs_ex_cmd_hdr(Struct): pass +struct_ib_uverbs_ex_cmd_hdr._fields_ = [ + ('response', ctypes.c_uint64), + ('provider_in_words', ctypes.c_uint16), + ('provider_out_words', ctypes.c_uint16), + ('cmd_hdr_reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_get_context(Struct): pass +struct_ib_uverbs_get_context._fields_ = [ + ('response', ctypes.c_uint64), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_get_context_resp(Struct): pass +struct_ib_uverbs_get_context_resp._fields_ = [ + ('async_fd', ctypes.c_uint32), + ('num_comp_vectors', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_query_device(Struct): pass +struct_ib_uverbs_query_device._fields_ = [ + ('response', ctypes.c_uint64), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_query_device_resp(Struct): pass +struct_ib_uverbs_query_device_resp._fields_ = [ + ('fw_ver', ctypes.c_uint64), + ('node_guid', ctypes.c_uint64), + ('sys_image_guid', ctypes.c_uint64), + ('max_mr_size', ctypes.c_uint64), + ('page_size_cap', ctypes.c_uint64), + ('vendor_id', ctypes.c_uint32), + ('vendor_part_id', ctypes.c_uint32), + ('hw_ver', ctypes.c_uint32), + ('max_qp', ctypes.c_uint32), + ('max_qp_wr', ctypes.c_uint32), + ('device_cap_flags', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('max_sge_rd', ctypes.c_uint32), + ('max_cq', ctypes.c_uint32), + ('max_cqe', ctypes.c_uint32), + ('max_mr', ctypes.c_uint32), + ('max_pd', ctypes.c_uint32), + ('max_qp_rd_atom', ctypes.c_uint32), + ('max_ee_rd_atom', ctypes.c_uint32), + ('max_res_rd_atom', ctypes.c_uint32), + ('max_qp_init_rd_atom', ctypes.c_uint32), + ('max_ee_init_rd_atom', ctypes.c_uint32), + ('atomic_cap', ctypes.c_uint32), + ('max_ee', ctypes.c_uint32), + ('max_rdd', ctypes.c_uint32), + ('max_mw', ctypes.c_uint32), + ('max_raw_ipv6_qp', ctypes.c_uint32), + ('max_raw_ethy_qp', ctypes.c_uint32), + ('max_mcast_grp', ctypes.c_uint32), + ('max_mcast_qp_attach', ctypes.c_uint32), + ('max_total_mcast_qp_attach', ctypes.c_uint32), + ('max_ah', ctypes.c_uint32), + ('max_fmr', ctypes.c_uint32), + ('max_map_per_fmr', ctypes.c_uint32), + ('max_srq', ctypes.c_uint32), + ('max_srq_wr', ctypes.c_uint32), + ('max_srq_sge', ctypes.c_uint32), + ('max_pkeys', ctypes.c_uint16), + ('local_ca_ack_delay', ctypes.c_ubyte), + ('phys_port_cnt', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 4)), +] +class struct_ib_uverbs_ex_query_device(Struct): pass +struct_ib_uverbs_ex_query_device._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_odp_caps(Struct): pass +class struct_ib_uverbs_odp_caps_per_transport_caps(Struct): pass +struct_ib_uverbs_odp_caps_per_transport_caps._fields_ = [ + ('rc_odp_caps', ctypes.c_uint32), + ('uc_odp_caps', ctypes.c_uint32), + ('ud_odp_caps', ctypes.c_uint32), +] +struct_ib_uverbs_odp_caps._fields_ = [ + ('general_caps', ctypes.c_uint64), + ('per_transport_caps', struct_ib_uverbs_odp_caps_per_transport_caps), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_rss_caps(Struct): pass +struct_ib_uverbs_rss_caps._fields_ = [ + ('supported_qpts', ctypes.c_uint32), + ('max_rwq_indirection_tables', ctypes.c_uint32), + ('max_rwq_indirection_table_size', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_tm_caps(Struct): pass +struct_ib_uverbs_tm_caps._fields_ = [ + ('max_rndv_hdr_size', ctypes.c_uint32), + ('max_num_tags', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('max_ops', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_query_device_resp(Struct): pass +struct_ib_uverbs_ex_query_device_resp._fields_ = [ + ('base', struct_ib_uverbs_query_device_resp), + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), + ('odp_caps', struct_ib_uverbs_odp_caps), + ('timestamp_mask', ctypes.c_uint64), + ('hca_core_clock', ctypes.c_uint64), + ('device_cap_flags_ex', ctypes.c_uint64), + ('rss_caps', struct_ib_uverbs_rss_caps), + ('max_wq_type_rq', ctypes.c_uint32), + ('raw_packet_caps', ctypes.c_uint32), + ('tm_caps', struct_ib_uverbs_tm_caps), + ('cq_moderation_caps', struct_ib_uverbs_cq_moderation_caps), + ('max_dm_size', ctypes.c_uint64), + ('xrc_odp_caps', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_query_port(Struct): pass +struct_ib_uverbs_query_port._fields_ = [ + ('response', ctypes.c_uint64), + ('port_num', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 7)), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_alloc_pd(Struct): pass +struct_ib_uverbs_alloc_pd._fields_ = [ + ('response', ctypes.c_uint64), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_alloc_pd_resp(Struct): pass +struct_ib_uverbs_alloc_pd_resp._fields_ = [ + ('pd_handle', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_dealloc_pd(Struct): pass +struct_ib_uverbs_dealloc_pd._fields_ = [ + ('pd_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_open_xrcd(Struct): pass +struct_ib_uverbs_open_xrcd._fields_ = [ + ('response', ctypes.c_uint64), + ('fd', ctypes.c_uint32), + ('oflags', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_open_xrcd_resp(Struct): pass +struct_ib_uverbs_open_xrcd_resp._fields_ = [ + ('xrcd_handle', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_close_xrcd(Struct): pass +struct_ib_uverbs_close_xrcd._fields_ = [ + ('xrcd_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_reg_mr(Struct): pass +struct_ib_uverbs_reg_mr._fields_ = [ + ('response', ctypes.c_uint64), + ('start', ctypes.c_uint64), + ('length', ctypes.c_uint64), + ('hca_va', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('access_flags', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_reg_mr_resp(Struct): pass +struct_ib_uverbs_reg_mr_resp._fields_ = [ + ('mr_handle', ctypes.c_uint32), + ('lkey', ctypes.c_uint32), + ('rkey', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_rereg_mr(Struct): pass +struct_ib_uverbs_rereg_mr._fields_ = [ + ('response', ctypes.c_uint64), + ('mr_handle', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('start', ctypes.c_uint64), + ('length', ctypes.c_uint64), + ('hca_va', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('access_flags', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_rereg_mr_resp(Struct): pass +struct_ib_uverbs_rereg_mr_resp._fields_ = [ + ('lkey', ctypes.c_uint32), + ('rkey', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_dereg_mr(Struct): pass +struct_ib_uverbs_dereg_mr._fields_ = [ + ('mr_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_alloc_mw(Struct): pass +struct_ib_uverbs_alloc_mw._fields_ = [ + ('response', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('mw_type', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 3)), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_alloc_mw_resp(Struct): pass +struct_ib_uverbs_alloc_mw_resp._fields_ = [ + ('mw_handle', ctypes.c_uint32), + ('rkey', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_dealloc_mw(Struct): pass +struct_ib_uverbs_dealloc_mw._fields_ = [ + ('mw_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_create_comp_channel(Struct): pass +struct_ib_uverbs_create_comp_channel._fields_ = [ + ('response', ctypes.c_uint64), +] +class struct_ib_uverbs_create_comp_channel_resp(Struct): pass +struct_ib_uverbs_create_comp_channel_resp._fields_ = [ + ('fd', ctypes.c_uint32), +] +class struct_ib_uverbs_create_cq(Struct): pass +__s32 = ctypes.c_int32 +struct_ib_uverbs_create_cq._fields_ = [ + ('response', ctypes.c_uint64), + ('user_handle', ctypes.c_uint64), + ('cqe', ctypes.c_uint32), + ('comp_vector', ctypes.c_uint32), + ('comp_channel', ctypes.c_int32), + ('reserved', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +enum_ib_uverbs_ex_create_cq_flags = CEnum(ctypes.c_uint32) +IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = enum_ib_uverbs_ex_create_cq_flags.define('IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION', 1) +IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = enum_ib_uverbs_ex_create_cq_flags.define('IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN', 2) + +class struct_ib_uverbs_ex_create_cq(Struct): pass +struct_ib_uverbs_ex_create_cq._fields_ = [ + ('user_handle', ctypes.c_uint64), + ('cqe', ctypes.c_uint32), + ('comp_vector', ctypes.c_uint32), + ('comp_channel', ctypes.c_int32), + ('comp_mask', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_create_cq_resp(Struct): pass +struct_ib_uverbs_create_cq_resp._fields_ = [ + ('cq_handle', ctypes.c_uint32), + ('cqe', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_ex_create_cq_resp(Struct): pass +struct_ib_uverbs_ex_create_cq_resp._fields_ = [ + ('base', struct_ib_uverbs_create_cq_resp), + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), +] +class struct_ib_uverbs_resize_cq(Struct): pass +struct_ib_uverbs_resize_cq._fields_ = [ + ('response', ctypes.c_uint64), + ('cq_handle', ctypes.c_uint32), + ('cqe', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_resize_cq_resp(Struct): pass +struct_ib_uverbs_resize_cq_resp._fields_ = [ + ('cqe', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_poll_cq(Struct): pass +struct_ib_uverbs_poll_cq._fields_ = [ + ('response', ctypes.c_uint64), + ('cq_handle', ctypes.c_uint32), + ('ne', ctypes.c_uint32), +] +enum_ib_uverbs_wc_opcode = CEnum(ctypes.c_uint32) +IB_UVERBS_WC_SEND = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_SEND', 0) +IB_UVERBS_WC_RDMA_WRITE = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_RDMA_WRITE', 1) +IB_UVERBS_WC_RDMA_READ = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_RDMA_READ', 2) +IB_UVERBS_WC_COMP_SWAP = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_COMP_SWAP', 3) +IB_UVERBS_WC_FETCH_ADD = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_FETCH_ADD', 4) +IB_UVERBS_WC_BIND_MW = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_BIND_MW', 5) +IB_UVERBS_WC_LOCAL_INV = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_LOCAL_INV', 6) +IB_UVERBS_WC_TSO = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_TSO', 7) +IB_UVERBS_WC_FLUSH = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_FLUSH', 8) +IB_UVERBS_WC_ATOMIC_WRITE = enum_ib_uverbs_wc_opcode.define('IB_UVERBS_WC_ATOMIC_WRITE', 9) + +class struct_ib_uverbs_wc(Struct): pass +class struct_ib_uverbs_wc_ex(ctypes.Union): pass +struct_ib_uverbs_wc_ex._fields_ = [ + ('imm_data', ctypes.c_uint32), + ('invalidate_rkey', ctypes.c_uint32), +] +struct_ib_uverbs_wc._fields_ = [ + ('wr_id', ctypes.c_uint64), + ('status', ctypes.c_uint32), + ('opcode', ctypes.c_uint32), + ('vendor_err', ctypes.c_uint32), + ('byte_len', ctypes.c_uint32), + ('ex', struct_ib_uverbs_wc_ex), + ('qp_num', ctypes.c_uint32), + ('src_qp', ctypes.c_uint32), + ('wc_flags', ctypes.c_uint32), + ('pkey_index', ctypes.c_uint16), + ('slid', ctypes.c_uint16), + ('sl', ctypes.c_ubyte), + ('dlid_path_bits', ctypes.c_ubyte), + ('port_num', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), +] +class struct_ib_uverbs_poll_cq_resp(Struct): pass +struct_ib_uverbs_poll_cq_resp._fields_ = [ + ('count', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('wc', (struct_ib_uverbs_wc * 0)), +] +class struct_ib_uverbs_req_notify_cq(Struct): pass +struct_ib_uverbs_req_notify_cq._fields_ = [ + ('cq_handle', ctypes.c_uint32), + ('solicited_only', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_cq(Struct): pass +struct_ib_uverbs_destroy_cq._fields_ = [ + ('response', ctypes.c_uint64), + ('cq_handle', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_cq_resp(Struct): pass +struct_ib_uverbs_destroy_cq_resp._fields_ = [ + ('comp_events_reported', ctypes.c_uint32), + ('async_events_reported', ctypes.c_uint32), +] +class struct_ib_uverbs_global_route(Struct): pass +struct_ib_uverbs_global_route._fields_ = [ + ('dgid', (ctypes.c_ubyte * 16)), + ('flow_label', ctypes.c_uint32), + ('sgid_index', ctypes.c_ubyte), + ('hop_limit', ctypes.c_ubyte), + ('traffic_class', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), +] +class struct_ib_uverbs_ah_attr(Struct): pass +struct_ib_uverbs_ah_attr._fields_ = [ + ('grh', struct_ib_uverbs_global_route), + ('dlid', ctypes.c_uint16), + ('sl', ctypes.c_ubyte), + ('src_path_bits', ctypes.c_ubyte), + ('static_rate', ctypes.c_ubyte), + ('is_global', ctypes.c_ubyte), + ('port_num', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), +] +class struct_ib_uverbs_qp_attr(Struct): pass +struct_ib_uverbs_qp_attr._fields_ = [ + ('qp_attr_mask', ctypes.c_uint32), + ('qp_state', ctypes.c_uint32), + ('cur_qp_state', ctypes.c_uint32), + ('path_mtu', ctypes.c_uint32), + ('path_mig_state', ctypes.c_uint32), + ('qkey', ctypes.c_uint32), + ('rq_psn', ctypes.c_uint32), + ('sq_psn', ctypes.c_uint32), + ('dest_qp_num', ctypes.c_uint32), + ('qp_access_flags', ctypes.c_uint32), + ('ah_attr', struct_ib_uverbs_ah_attr), + ('alt_ah_attr', struct_ib_uverbs_ah_attr), + ('max_send_wr', ctypes.c_uint32), + ('max_recv_wr', ctypes.c_uint32), + ('max_send_sge', ctypes.c_uint32), + ('max_recv_sge', ctypes.c_uint32), + ('max_inline_data', ctypes.c_uint32), + ('pkey_index', ctypes.c_uint16), + ('alt_pkey_index', ctypes.c_uint16), + ('en_sqd_async_notify', ctypes.c_ubyte), + ('sq_draining', ctypes.c_ubyte), + ('max_rd_atomic', ctypes.c_ubyte), + ('max_dest_rd_atomic', ctypes.c_ubyte), + ('min_rnr_timer', ctypes.c_ubyte), + ('port_num', ctypes.c_ubyte), + ('timeout', ctypes.c_ubyte), + ('retry_cnt', ctypes.c_ubyte), + ('rnr_retry', ctypes.c_ubyte), + ('alt_port_num', ctypes.c_ubyte), + ('alt_timeout', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 5)), +] +class struct_ib_uverbs_create_qp(Struct): pass +struct_ib_uverbs_create_qp._fields_ = [ + ('response', ctypes.c_uint64), + ('user_handle', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('send_cq_handle', ctypes.c_uint32), + ('recv_cq_handle', ctypes.c_uint32), + ('srq_handle', ctypes.c_uint32), + ('max_send_wr', ctypes.c_uint32), + ('max_recv_wr', ctypes.c_uint32), + ('max_send_sge', ctypes.c_uint32), + ('max_recv_sge', ctypes.c_uint32), + ('max_inline_data', ctypes.c_uint32), + ('sq_sig_all', ctypes.c_ubyte), + ('qp_type', ctypes.c_ubyte), + ('is_srq', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), + ('driver_data', (ctypes.c_uint64 * 0)), +] +enum_ib_uverbs_create_qp_mask = CEnum(ctypes.c_uint32) +IB_UVERBS_CREATE_QP_MASK_IND_TABLE = enum_ib_uverbs_create_qp_mask.define('IB_UVERBS_CREATE_QP_MASK_IND_TABLE', 1) + +_anonenum6 = CEnum(ctypes.c_uint32) +IB_UVERBS_CREATE_QP_SUP_COMP_MASK = _anonenum6.define('IB_UVERBS_CREATE_QP_SUP_COMP_MASK', 1) + +class struct_ib_uverbs_ex_create_qp(Struct): pass +struct_ib_uverbs_ex_create_qp._fields_ = [ + ('user_handle', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('send_cq_handle', ctypes.c_uint32), + ('recv_cq_handle', ctypes.c_uint32), + ('srq_handle', ctypes.c_uint32), + ('max_send_wr', ctypes.c_uint32), + ('max_recv_wr', ctypes.c_uint32), + ('max_send_sge', ctypes.c_uint32), + ('max_recv_sge', ctypes.c_uint32), + ('max_inline_data', ctypes.c_uint32), + ('sq_sig_all', ctypes.c_ubyte), + ('qp_type', ctypes.c_ubyte), + ('is_srq', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), + ('comp_mask', ctypes.c_uint32), + ('create_flags', ctypes.c_uint32), + ('rwq_ind_tbl_handle', ctypes.c_uint32), + ('source_qpn', ctypes.c_uint32), +] +class struct_ib_uverbs_open_qp(Struct): pass +struct_ib_uverbs_open_qp._fields_ = [ + ('response', ctypes.c_uint64), + ('user_handle', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('qpn', ctypes.c_uint32), + ('qp_type', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 7)), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_create_qp_resp(Struct): pass +struct_ib_uverbs_create_qp_resp._fields_ = [ + ('qp_handle', ctypes.c_uint32), + ('qpn', ctypes.c_uint32), + ('max_send_wr', ctypes.c_uint32), + ('max_recv_wr', ctypes.c_uint32), + ('max_send_sge', ctypes.c_uint32), + ('max_recv_sge', ctypes.c_uint32), + ('max_inline_data', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_ex_create_qp_resp(Struct): pass +struct_ib_uverbs_ex_create_qp_resp._fields_ = [ + ('base', struct_ib_uverbs_create_qp_resp), + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), +] +class struct_ib_uverbs_qp_dest(Struct): pass +struct_ib_uverbs_qp_dest._fields_ = [ + ('dgid', (ctypes.c_ubyte * 16)), + ('flow_label', ctypes.c_uint32), + ('dlid', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), + ('sgid_index', ctypes.c_ubyte), + ('hop_limit', ctypes.c_ubyte), + ('traffic_class', ctypes.c_ubyte), + ('sl', ctypes.c_ubyte), + ('src_path_bits', ctypes.c_ubyte), + ('static_rate', ctypes.c_ubyte), + ('is_global', ctypes.c_ubyte), + ('port_num', ctypes.c_ubyte), +] +class struct_ib_uverbs_query_qp(Struct): pass +struct_ib_uverbs_query_qp._fields_ = [ + ('response', ctypes.c_uint64), + ('qp_handle', ctypes.c_uint32), + ('attr_mask', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_query_qp_resp(Struct): pass +struct_ib_uverbs_query_qp_resp._fields_ = [ + ('dest', struct_ib_uverbs_qp_dest), + ('alt_dest', struct_ib_uverbs_qp_dest), + ('max_send_wr', ctypes.c_uint32), + ('max_recv_wr', ctypes.c_uint32), + ('max_send_sge', ctypes.c_uint32), + ('max_recv_sge', ctypes.c_uint32), + ('max_inline_data', ctypes.c_uint32), + ('qkey', ctypes.c_uint32), + ('rq_psn', ctypes.c_uint32), + ('sq_psn', ctypes.c_uint32), + ('dest_qp_num', ctypes.c_uint32), + ('qp_access_flags', ctypes.c_uint32), + ('pkey_index', ctypes.c_uint16), + ('alt_pkey_index', ctypes.c_uint16), + ('qp_state', ctypes.c_ubyte), + ('cur_qp_state', ctypes.c_ubyte), + ('path_mtu', ctypes.c_ubyte), + ('path_mig_state', ctypes.c_ubyte), + ('sq_draining', ctypes.c_ubyte), + ('max_rd_atomic', ctypes.c_ubyte), + ('max_dest_rd_atomic', ctypes.c_ubyte), + ('min_rnr_timer', ctypes.c_ubyte), + ('port_num', ctypes.c_ubyte), + ('timeout', ctypes.c_ubyte), + ('retry_cnt', ctypes.c_ubyte), + ('rnr_retry', ctypes.c_ubyte), + ('alt_port_num', ctypes.c_ubyte), + ('alt_timeout', ctypes.c_ubyte), + ('sq_sig_all', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 5)), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_modify_qp(Struct): pass +struct_ib_uverbs_modify_qp._fields_ = [ + ('dest', struct_ib_uverbs_qp_dest), + ('alt_dest', struct_ib_uverbs_qp_dest), + ('qp_handle', ctypes.c_uint32), + ('attr_mask', ctypes.c_uint32), + ('qkey', ctypes.c_uint32), + ('rq_psn', ctypes.c_uint32), + ('sq_psn', ctypes.c_uint32), + ('dest_qp_num', ctypes.c_uint32), + ('qp_access_flags', ctypes.c_uint32), + ('pkey_index', ctypes.c_uint16), + ('alt_pkey_index', ctypes.c_uint16), + ('qp_state', ctypes.c_ubyte), + ('cur_qp_state', ctypes.c_ubyte), + ('path_mtu', ctypes.c_ubyte), + ('path_mig_state', ctypes.c_ubyte), + ('en_sqd_async_notify', ctypes.c_ubyte), + ('max_rd_atomic', ctypes.c_ubyte), + ('max_dest_rd_atomic', ctypes.c_ubyte), + ('min_rnr_timer', ctypes.c_ubyte), + ('port_num', ctypes.c_ubyte), + ('timeout', ctypes.c_ubyte), + ('retry_cnt', ctypes.c_ubyte), + ('rnr_retry', ctypes.c_ubyte), + ('alt_port_num', ctypes.c_ubyte), + ('alt_timeout', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 2)), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_ex_modify_qp(Struct): pass +struct_ib_uverbs_ex_modify_qp._fields_ = [ + ('base', struct_ib_uverbs_modify_qp), + ('rate_limit', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_modify_qp_resp(Struct): pass +struct_ib_uverbs_ex_modify_qp_resp._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_qp(Struct): pass +struct_ib_uverbs_destroy_qp._fields_ = [ + ('response', ctypes.c_uint64), + ('qp_handle', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_qp_resp(Struct): pass +struct_ib_uverbs_destroy_qp_resp._fields_ = [ + ('events_reported', ctypes.c_uint32), +] +class struct_ib_uverbs_sge(Struct): pass +struct_ib_uverbs_sge._fields_ = [ + ('addr', ctypes.c_uint64), + ('length', ctypes.c_uint32), + ('lkey', ctypes.c_uint32), +] +enum_ib_uverbs_wr_opcode = CEnum(ctypes.c_uint32) +IB_UVERBS_WR_RDMA_WRITE = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_RDMA_WRITE', 0) +IB_UVERBS_WR_RDMA_WRITE_WITH_IMM = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_RDMA_WRITE_WITH_IMM', 1) +IB_UVERBS_WR_SEND = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_SEND', 2) +IB_UVERBS_WR_SEND_WITH_IMM = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_SEND_WITH_IMM', 3) +IB_UVERBS_WR_RDMA_READ = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_RDMA_READ', 4) +IB_UVERBS_WR_ATOMIC_CMP_AND_SWP = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_ATOMIC_CMP_AND_SWP', 5) +IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD', 6) +IB_UVERBS_WR_LOCAL_INV = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_LOCAL_INV', 7) +IB_UVERBS_WR_BIND_MW = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_BIND_MW', 8) +IB_UVERBS_WR_SEND_WITH_INV = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_SEND_WITH_INV', 9) +IB_UVERBS_WR_TSO = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_TSO', 10) +IB_UVERBS_WR_RDMA_READ_WITH_INV = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_RDMA_READ_WITH_INV', 11) +IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP', 12) +IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD', 13) +IB_UVERBS_WR_FLUSH = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_FLUSH', 14) +IB_UVERBS_WR_ATOMIC_WRITE = enum_ib_uverbs_wr_opcode.define('IB_UVERBS_WR_ATOMIC_WRITE', 15) + +class struct_ib_uverbs_send_wr(Struct): pass +class struct_ib_uverbs_send_wr_ex(ctypes.Union): pass +struct_ib_uverbs_send_wr_ex._fields_ = [ + ('imm_data', ctypes.c_uint32), + ('invalidate_rkey', ctypes.c_uint32), +] +class struct_ib_uverbs_send_wr_wr(ctypes.Union): pass +class struct_ib_uverbs_send_wr_wr_rdma(Struct): pass +struct_ib_uverbs_send_wr_wr_rdma._fields_ = [ + ('remote_addr', ctypes.c_uint64), + ('rkey', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_send_wr_wr_atomic(Struct): pass +struct_ib_uverbs_send_wr_wr_atomic._fields_ = [ + ('remote_addr', ctypes.c_uint64), + ('compare_add', ctypes.c_uint64), + ('swap', ctypes.c_uint64), + ('rkey', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_send_wr_wr_ud(Struct): pass +struct_ib_uverbs_send_wr_wr_ud._fields_ = [ + ('ah', ctypes.c_uint32), + ('remote_qpn', ctypes.c_uint32), + ('remote_qkey', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +struct_ib_uverbs_send_wr_wr._fields_ = [ + ('rdma', struct_ib_uverbs_send_wr_wr_rdma), + ('atomic', struct_ib_uverbs_send_wr_wr_atomic), + ('ud', struct_ib_uverbs_send_wr_wr_ud), +] +struct_ib_uverbs_send_wr._fields_ = [ + ('wr_id', ctypes.c_uint64), + ('num_sge', ctypes.c_uint32), + ('opcode', ctypes.c_uint32), + ('send_flags', ctypes.c_uint32), + ('ex', struct_ib_uverbs_send_wr_ex), + ('wr', struct_ib_uverbs_send_wr_wr), +] +class struct_ib_uverbs_post_send(Struct): pass +struct_ib_uverbs_post_send._fields_ = [ + ('response', ctypes.c_uint64), + ('qp_handle', ctypes.c_uint32), + ('wr_count', ctypes.c_uint32), + ('sge_count', ctypes.c_uint32), + ('wqe_size', ctypes.c_uint32), + ('send_wr', (struct_ib_uverbs_send_wr * 0)), +] +class struct_ib_uverbs_post_send_resp(Struct): pass +struct_ib_uverbs_post_send_resp._fields_ = [ + ('bad_wr', ctypes.c_uint32), +] +class struct_ib_uverbs_recv_wr(Struct): pass +struct_ib_uverbs_recv_wr._fields_ = [ + ('wr_id', ctypes.c_uint64), + ('num_sge', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_post_recv(Struct): pass +struct_ib_uverbs_post_recv._fields_ = [ + ('response', ctypes.c_uint64), + ('qp_handle', ctypes.c_uint32), + ('wr_count', ctypes.c_uint32), + ('sge_count', ctypes.c_uint32), + ('wqe_size', ctypes.c_uint32), + ('recv_wr', (struct_ib_uverbs_recv_wr * 0)), +] +class struct_ib_uverbs_post_recv_resp(Struct): pass +struct_ib_uverbs_post_recv_resp._fields_ = [ + ('bad_wr', ctypes.c_uint32), +] +class struct_ib_uverbs_post_srq_recv(Struct): pass +struct_ib_uverbs_post_srq_recv._fields_ = [ + ('response', ctypes.c_uint64), + ('srq_handle', ctypes.c_uint32), + ('wr_count', ctypes.c_uint32), + ('sge_count', ctypes.c_uint32), + ('wqe_size', ctypes.c_uint32), + ('recv', (struct_ib_uverbs_recv_wr * 0)), +] +class struct_ib_uverbs_post_srq_recv_resp(Struct): pass +struct_ib_uverbs_post_srq_recv_resp._fields_ = [ + ('bad_wr', ctypes.c_uint32), +] +class struct_ib_uverbs_create_ah(Struct): pass +struct_ib_uverbs_create_ah._fields_ = [ + ('response', ctypes.c_uint64), + ('user_handle', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('attr', struct_ib_uverbs_ah_attr), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_create_ah_resp(Struct): pass +struct_ib_uverbs_create_ah_resp._fields_ = [ + ('ah_handle', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_destroy_ah(Struct): pass +struct_ib_uverbs_destroy_ah._fields_ = [ + ('ah_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_attach_mcast(Struct): pass +struct_ib_uverbs_attach_mcast._fields_ = [ + ('gid', (ctypes.c_ubyte * 16)), + ('qp_handle', ctypes.c_uint32), + ('mlid', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_detach_mcast(Struct): pass +struct_ib_uverbs_detach_mcast._fields_ = [ + ('gid', (ctypes.c_ubyte * 16)), + ('qp_handle', ctypes.c_uint32), + ('mlid', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_flow_spec_hdr(Struct): pass +struct_ib_uverbs_flow_spec_hdr._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), + ('flow_spec_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_flow_eth_filter(Struct): pass +struct_ib_uverbs_flow_eth_filter._fields_ = [ + ('dst_mac', (ctypes.c_ubyte * 6)), + ('src_mac', (ctypes.c_ubyte * 6)), + ('ether_type', ctypes.c_uint16), + ('vlan_tag', ctypes.c_uint16), +] +class struct_ib_uverbs_flow_spec_eth(Struct): pass +class struct_ib_uverbs_flow_spec_eth_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_eth_0_0(Struct): pass +struct_ib_uverbs_flow_spec_eth_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_eth_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_eth_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_eth_0_0), +] +struct_ib_uverbs_flow_spec_eth._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_eth._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_eth_0), + ('val', struct_ib_uverbs_flow_eth_filter), + ('mask', struct_ib_uverbs_flow_eth_filter), +] +class struct_ib_uverbs_flow_ipv4_filter(Struct): pass +struct_ib_uverbs_flow_ipv4_filter._fields_ = [ + ('src_ip', ctypes.c_uint32), + ('dst_ip', ctypes.c_uint32), + ('proto', ctypes.c_ubyte), + ('tos', ctypes.c_ubyte), + ('ttl', ctypes.c_ubyte), + ('flags', ctypes.c_ubyte), +] +class struct_ib_uverbs_flow_spec_ipv4(Struct): pass +class struct_ib_uverbs_flow_spec_ipv4_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_ipv4_0_0(Struct): pass +struct_ib_uverbs_flow_spec_ipv4_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_ipv4_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_ipv4_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_ipv4_0_0), +] +struct_ib_uverbs_flow_spec_ipv4._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_ipv4._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_ipv4_0), + ('val', struct_ib_uverbs_flow_ipv4_filter), + ('mask', struct_ib_uverbs_flow_ipv4_filter), +] +class struct_ib_uverbs_flow_tcp_udp_filter(Struct): pass +struct_ib_uverbs_flow_tcp_udp_filter._fields_ = [ + ('dst_port', ctypes.c_uint16), + ('src_port', ctypes.c_uint16), +] +class struct_ib_uverbs_flow_spec_tcp_udp(Struct): pass +class struct_ib_uverbs_flow_spec_tcp_udp_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_tcp_udp_0_0(Struct): pass +struct_ib_uverbs_flow_spec_tcp_udp_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_tcp_udp_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_tcp_udp_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_tcp_udp_0_0), +] +struct_ib_uverbs_flow_spec_tcp_udp._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_tcp_udp._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_tcp_udp_0), + ('val', struct_ib_uverbs_flow_tcp_udp_filter), + ('mask', struct_ib_uverbs_flow_tcp_udp_filter), +] +class struct_ib_uverbs_flow_ipv6_filter(Struct): pass +struct_ib_uverbs_flow_ipv6_filter._fields_ = [ + ('src_ip', (ctypes.c_ubyte * 16)), + ('dst_ip', (ctypes.c_ubyte * 16)), + ('flow_label', ctypes.c_uint32), + ('next_hdr', ctypes.c_ubyte), + ('traffic_class', ctypes.c_ubyte), + ('hop_limit', ctypes.c_ubyte), + ('reserved', ctypes.c_ubyte), +] +class struct_ib_uverbs_flow_spec_ipv6(Struct): pass +class struct_ib_uverbs_flow_spec_ipv6_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_ipv6_0_0(Struct): pass +struct_ib_uverbs_flow_spec_ipv6_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_ipv6_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_ipv6_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_ipv6_0_0), +] +struct_ib_uverbs_flow_spec_ipv6._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_ipv6._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_ipv6_0), + ('val', struct_ib_uverbs_flow_ipv6_filter), + ('mask', struct_ib_uverbs_flow_ipv6_filter), +] +class struct_ib_uverbs_flow_spec_action_tag(Struct): pass +class struct_ib_uverbs_flow_spec_action_tag_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_action_tag_0_0(Struct): pass +struct_ib_uverbs_flow_spec_action_tag_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_action_tag_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_tag_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_action_tag_0_0), +] +struct_ib_uverbs_flow_spec_action_tag._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_tag._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_action_tag_0), + ('tag_id', ctypes.c_uint32), + ('reserved1', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_spec_action_drop(Struct): pass +class struct_ib_uverbs_flow_spec_action_drop_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_action_drop_0_0(Struct): pass +struct_ib_uverbs_flow_spec_action_drop_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_action_drop_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_drop_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_action_drop_0_0), +] +struct_ib_uverbs_flow_spec_action_drop._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_drop._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_action_drop_0), +] +class struct_ib_uverbs_flow_spec_action_handle(Struct): pass +class struct_ib_uverbs_flow_spec_action_handle_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_action_handle_0_0(Struct): pass +struct_ib_uverbs_flow_spec_action_handle_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_action_handle_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_handle_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_action_handle_0_0), +] +struct_ib_uverbs_flow_spec_action_handle._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_handle._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_action_handle_0), + ('handle', ctypes.c_uint32), + ('reserved1', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_spec_action_count(Struct): pass +class struct_ib_uverbs_flow_spec_action_count_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_action_count_0_0(Struct): pass +struct_ib_uverbs_flow_spec_action_count_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_action_count_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_count_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_action_count_0_0), +] +struct_ib_uverbs_flow_spec_action_count._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_action_count._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_action_count_0), + ('handle', ctypes.c_uint32), + ('reserved1', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_tunnel_filter(Struct): pass +struct_ib_uverbs_flow_tunnel_filter._fields_ = [ + ('tunnel_id', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_spec_tunnel(Struct): pass +class struct_ib_uverbs_flow_spec_tunnel_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_tunnel_0_0(Struct): pass +struct_ib_uverbs_flow_spec_tunnel_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_tunnel_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_tunnel_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_tunnel_0_0), +] +struct_ib_uverbs_flow_spec_tunnel._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_tunnel._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_tunnel_0), + ('val', struct_ib_uverbs_flow_tunnel_filter), + ('mask', struct_ib_uverbs_flow_tunnel_filter), +] +class struct_ib_uverbs_flow_spec_esp_filter(Struct): pass +struct_ib_uverbs_flow_spec_esp_filter._fields_ = [ + ('spi', ctypes.c_uint32), + ('seq', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_spec_esp(Struct): pass +class struct_ib_uverbs_flow_spec_esp_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_esp_0_0(Struct): pass +struct_ib_uverbs_flow_spec_esp_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_esp_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_esp_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_esp_0_0), +] +struct_ib_uverbs_flow_spec_esp._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_esp._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_esp_0), + ('val', struct_ib_uverbs_flow_spec_esp_filter), + ('mask', struct_ib_uverbs_flow_spec_esp_filter), +] +class struct_ib_uverbs_flow_gre_filter(Struct): pass +struct_ib_uverbs_flow_gre_filter._fields_ = [ + ('c_ks_res0_ver', ctypes.c_uint16), + ('protocol', ctypes.c_uint16), + ('key', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_spec_gre(Struct): pass +class struct_ib_uverbs_flow_spec_gre_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_gre_0_0(Struct): pass +struct_ib_uverbs_flow_spec_gre_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_gre_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_gre_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_gre_0_0), +] +struct_ib_uverbs_flow_spec_gre._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_gre._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_gre_0), + ('val', struct_ib_uverbs_flow_gre_filter), + ('mask', struct_ib_uverbs_flow_gre_filter), +] +class struct_ib_uverbs_flow_mpls_filter(Struct): pass +struct_ib_uverbs_flow_mpls_filter._fields_ = [ + ('label', ctypes.c_uint32), +] +class struct_ib_uverbs_flow_spec_mpls(Struct): pass +class struct_ib_uverbs_flow_spec_mpls_0(ctypes.Union): pass +class struct_ib_uverbs_flow_spec_mpls_0_0(Struct): pass +struct_ib_uverbs_flow_spec_mpls_0_0._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('reserved', ctypes.c_uint16), +] +struct_ib_uverbs_flow_spec_mpls_0._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_mpls_0._fields_ = [ + ('hdr', struct_ib_uverbs_flow_spec_hdr), + ('_0', struct_ib_uverbs_flow_spec_mpls_0_0), +] +struct_ib_uverbs_flow_spec_mpls._anonymous_ = ['_0'] +struct_ib_uverbs_flow_spec_mpls._fields_ = [ + ('_0', struct_ib_uverbs_flow_spec_mpls_0), + ('val', struct_ib_uverbs_flow_mpls_filter), + ('mask', struct_ib_uverbs_flow_mpls_filter), +] +class struct_ib_uverbs_flow_attr(Struct): pass +struct_ib_uverbs_flow_attr._fields_ = [ + ('type', ctypes.c_uint32), + ('size', ctypes.c_uint16), + ('priority', ctypes.c_uint16), + ('num_of_specs', ctypes.c_ubyte), + ('reserved', (ctypes.c_ubyte * 2)), + ('port', ctypes.c_ubyte), + ('flags', ctypes.c_uint32), + ('flow_specs', (struct_ib_uverbs_flow_spec_hdr * 0)), +] +class struct_ib_uverbs_create_flow(Struct): pass +struct_ib_uverbs_create_flow._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('qp_handle', ctypes.c_uint32), + ('flow_attr', struct_ib_uverbs_flow_attr), +] +class struct_ib_uverbs_create_flow_resp(Struct): pass +struct_ib_uverbs_create_flow_resp._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('flow_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_flow(Struct): pass +struct_ib_uverbs_destroy_flow._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('flow_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_create_srq(Struct): pass +struct_ib_uverbs_create_srq._fields_ = [ + ('response', ctypes.c_uint64), + ('user_handle', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('max_wr', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('srq_limit', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_create_xsrq(Struct): pass +struct_ib_uverbs_create_xsrq._fields_ = [ + ('response', ctypes.c_uint64), + ('user_handle', ctypes.c_uint64), + ('srq_type', ctypes.c_uint32), + ('pd_handle', ctypes.c_uint32), + ('max_wr', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('srq_limit', ctypes.c_uint32), + ('max_num_tags', ctypes.c_uint32), + ('xrcd_handle', ctypes.c_uint32), + ('cq_handle', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_create_srq_resp(Struct): pass +struct_ib_uverbs_create_srq_resp._fields_ = [ + ('srq_handle', ctypes.c_uint32), + ('max_wr', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('srqn', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_modify_srq(Struct): pass +struct_ib_uverbs_modify_srq._fields_ = [ + ('srq_handle', ctypes.c_uint32), + ('attr_mask', ctypes.c_uint32), + ('max_wr', ctypes.c_uint32), + ('srq_limit', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_query_srq(Struct): pass +struct_ib_uverbs_query_srq._fields_ = [ + ('response', ctypes.c_uint64), + ('srq_handle', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('driver_data', (ctypes.c_uint64 * 0)), +] +class struct_ib_uverbs_query_srq_resp(Struct): pass +struct_ib_uverbs_query_srq_resp._fields_ = [ + ('max_wr', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('srq_limit', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_srq(Struct): pass +struct_ib_uverbs_destroy_srq._fields_ = [ + ('response', ctypes.c_uint64), + ('srq_handle', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_destroy_srq_resp(Struct): pass +struct_ib_uverbs_destroy_srq_resp._fields_ = [ + ('events_reported', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_create_wq(Struct): pass +struct_ib_uverbs_ex_create_wq._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('wq_type', ctypes.c_uint32), + ('user_handle', ctypes.c_uint64), + ('pd_handle', ctypes.c_uint32), + ('cq_handle', ctypes.c_uint32), + ('max_wr', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('create_flags', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_create_wq_resp(Struct): pass +struct_ib_uverbs_ex_create_wq_resp._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), + ('wq_handle', ctypes.c_uint32), + ('max_wr', ctypes.c_uint32), + ('max_sge', ctypes.c_uint32), + ('wqn', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_destroy_wq(Struct): pass +struct_ib_uverbs_ex_destroy_wq._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('wq_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_destroy_wq_resp(Struct): pass +struct_ib_uverbs_ex_destroy_wq_resp._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), + ('events_reported', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_modify_wq(Struct): pass +struct_ib_uverbs_ex_modify_wq._fields_ = [ + ('attr_mask', ctypes.c_uint32), + ('wq_handle', ctypes.c_uint32), + ('wq_state', ctypes.c_uint32), + ('curr_wq_state', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('flags_mask', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_create_rwq_ind_table(Struct): pass +struct_ib_uverbs_ex_create_rwq_ind_table._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('log_ind_tbl_size', ctypes.c_uint32), + ('wq_handles', (ctypes.c_uint32 * 0)), +] +class struct_ib_uverbs_ex_create_rwq_ind_table_resp(Struct): pass +struct_ib_uverbs_ex_create_rwq_ind_table_resp._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('response_length', ctypes.c_uint32), + ('ind_tbl_handle', ctypes.c_uint32), + ('ind_tbl_num', ctypes.c_uint32), +] +class struct_ib_uverbs_ex_destroy_rwq_ind_table(Struct): pass +struct_ib_uverbs_ex_destroy_rwq_ind_table._fields_ = [ + ('comp_mask', ctypes.c_uint32), + ('ind_tbl_handle', ctypes.c_uint32), +] +class struct_ib_uverbs_cq_moderation(Struct): pass +struct_ib_uverbs_cq_moderation._fields_ = [ + ('cq_count', ctypes.c_uint16), + ('cq_period', ctypes.c_uint16), +] +class struct_ib_uverbs_ex_modify_cq(Struct): pass +struct_ib_uverbs_ex_modify_cq._fields_ = [ + ('cq_handle', ctypes.c_uint32), + ('attr_mask', ctypes.c_uint32), + ('attr', struct_ib_uverbs_cq_moderation), + ('reserved', ctypes.c_uint32), +] +enum_ib_uverbs_device_cap_flags = CEnum(ctypes.c_uint64) +IB_UVERBS_DEVICE_RESIZE_MAX_WR = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_RESIZE_MAX_WR', 1) +IB_UVERBS_DEVICE_BAD_PKEY_CNTR = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_BAD_PKEY_CNTR', 2) +IB_UVERBS_DEVICE_BAD_QKEY_CNTR = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_BAD_QKEY_CNTR', 4) +IB_UVERBS_DEVICE_RAW_MULTI = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_RAW_MULTI', 8) +IB_UVERBS_DEVICE_AUTO_PATH_MIG = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_AUTO_PATH_MIG', 16) +IB_UVERBS_DEVICE_CHANGE_PHY_PORT = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_CHANGE_PHY_PORT', 32) +IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE', 64) +IB_UVERBS_DEVICE_CURR_QP_STATE_MOD = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_CURR_QP_STATE_MOD', 128) +IB_UVERBS_DEVICE_SHUTDOWN_PORT = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_SHUTDOWN_PORT', 256) +IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT', 1024) +IB_UVERBS_DEVICE_SYS_IMAGE_GUID = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_SYS_IMAGE_GUID', 2048) +IB_UVERBS_DEVICE_RC_RNR_NAK_GEN = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_RC_RNR_NAK_GEN', 4096) +IB_UVERBS_DEVICE_SRQ_RESIZE = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_SRQ_RESIZE', 8192) +IB_UVERBS_DEVICE_N_NOTIFY_CQ = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_N_NOTIFY_CQ', 16384) +IB_UVERBS_DEVICE_MEM_WINDOW = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_MEM_WINDOW', 131072) +IB_UVERBS_DEVICE_UD_IP_CSUM = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_UD_IP_CSUM', 262144) +IB_UVERBS_DEVICE_XRC = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_XRC', 1048576) +IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS', 2097152) +IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A', 8388608) +IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B', 16777216) +IB_UVERBS_DEVICE_RC_IP_CSUM = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_RC_IP_CSUM', 33554432) +IB_UVERBS_DEVICE_RAW_IP_CSUM = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_RAW_IP_CSUM', 67108864) +IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING', 536870912) +IB_UVERBS_DEVICE_RAW_SCATTER_FCS = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_RAW_SCATTER_FCS', 17179869184) +IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING', 68719476736) +IB_UVERBS_DEVICE_FLUSH_GLOBAL = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_FLUSH_GLOBAL', 274877906944) +IB_UVERBS_DEVICE_FLUSH_PERSISTENT = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_FLUSH_PERSISTENT', 549755813888) +IB_UVERBS_DEVICE_ATOMIC_WRITE = enum_ib_uverbs_device_cap_flags.define('IB_UVERBS_DEVICE_ATOMIC_WRITE', 1099511627776) + +enum_ib_uverbs_raw_packet_caps = CEnum(ctypes.c_uint32) +IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = enum_ib_uverbs_raw_packet_caps.define('IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING', 1) +IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = enum_ib_uverbs_raw_packet_caps.define('IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS', 2) +IB_UVERBS_RAW_PACKET_CAP_IP_CSUM = enum_ib_uverbs_raw_packet_caps.define('IB_UVERBS_RAW_PACKET_CAP_IP_CSUM', 4) +IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = enum_ib_uverbs_raw_packet_caps.define('IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP', 8) + +vext_field_avail = lambda type,fld,sz: (offsetof(type, fld) < (sz)) +IBV_DEVICE_RAW_SCATTER_FCS = (1 << 34) +IBV_DEVICE_PCI_WRITE_END_PADDING = (1 << 36) +ibv_query_port = lambda context,port_num,port_attr: ___ibv_query_port(context, port_num, port_attr) +ibv_reg_mr = lambda pd,addr,length,access: __ibv_reg_mr(pd, addr, length, access, __builtin_constant_p( ((int)(access) & IBV_ACCESS_OPTIONAL_RANGE) == 0)) +ibv_reg_mr_iova = lambda pd,addr,length,iova,access: __ibv_reg_mr_iova(pd, addr, length, iova, access, __builtin_constant_p( ((access) & IBV_ACCESS_OPTIONAL_RANGE) == 0)) +ETHERNET_LL_SIZE = 6 +IB_ROCE_UDP_ENCAP_VALID_PORT_MIN = (0xC000) +IB_ROCE_UDP_ENCAP_VALID_PORT_MAX = (0xFFFF) +IB_GRH_FLOWLABEL_MASK = (0x000FFFFF) +IBV_FLOW_ACTION_ESP_KEYMAT_AES_GCM = IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM +IBV_FLOW_ACTION_IV_ALGO_SEQ = IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ +IBV_FLOW_ACTION_ESP_REPLAY_NONE = IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE +IBV_FLOW_ACTION_ESP_REPLAY_BMP = IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP +IBV_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO +IBV_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD +IBV_FLOW_ACTION_ESP_FLAGS_TUNNEL = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL +IBV_FLOW_ACTION_ESP_FLAGS_TRANSPORT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT +IBV_FLOW_ACTION_ESP_FLAGS_DECRYPT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT +IBV_FLOW_ACTION_ESP_FLAGS_ENCRYPT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT +IBV_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW +IBV_ADVISE_MR_ADVICE_PREFETCH = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH +IBV_ADVISE_MR_ADVICE_PREFETCH_WRITE = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE +IBV_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT +IBV_ADVISE_MR_FLAG_FLUSH = IB_UVERBS_ADVISE_MR_FLAG_FLUSH +IBV_QPF_GRH_REQUIRED = IB_UVERBS_QPF_GRH_REQUIRED +IBV_ACCESS_OPTIONAL_RANGE = IB_UVERBS_ACCESS_OPTIONAL_RANGE +IB_UVERBS_ACCESS_OPTIONAL_FIRST = (1 << 20) +IB_UVERBS_ACCESS_OPTIONAL_LAST = (1 << 29) +IB_USER_VERBS_ABI_VERSION = 6 +IB_USER_VERBS_CMD_THRESHOLD = 50 +IB_USER_VERBS_CMD_COMMAND_MASK = 0xff +IB_USER_VERBS_CMD_FLAG_EXTENDED = 0x80000000 +IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE = 0x0d +IB_DEVICE_NAME_MAX = 64 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/io_uring.py b/tinygrad/runtime/autogen/io_uring.py index 4a8c10d11d..da9914b69f 100644 --- a/tinygrad/runtime/autogen/io_uring.py +++ b/tinygrad/runtime/autogen/io_uring.py @@ -1,2321 +1,990 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -LIB_URING_H = True # macro -_XOPEN_SOURCE = 500 # macro -_GNU_SOURCE = True # macro -# def uring_unlikely(cond): # macro -# return __builtin_expect(!!(cond),0) -# def uring_likely(cond): # macro -# return __builtin_expect(!!(cond),1) -IOURINGINLINE = True # macro -__NR_io_uring_setup = 425 # macro -__NR_io_uring_enter = 426 # macro -__NR_io_uring_register = 427 # macro -def io_uring_cqe_index(ring, ptr, mask): # macro - return (((ptr)&(mask))<cq.khead;(cqe=(head!=io_uring_smp_load_acquire((ring)->cq.ktail)?&(ring)->cq.cqes[io_uring_cqe_index(ring,head,(ring)->cq.ring_mask)]:NULL));head++) -LIBURING_HAVE_DATA64 = True # macro -def UNUSED(x): # macro - return (void)(x) -# def IO_URING_CHECK_VERSION(major, minor): # macro -# return (major>IO_URING_VERSION_MAJOR or (major==IO_URING_VERSION_MAJOR and minor>=IO_URING_VERSION_MINOR)) -class struct_io_uring_sq(Structure): - pass - -class struct_io_uring_sqe(Structure): - pass - -struct_io_uring_sq._pack_ = 1 # source:False -struct_io_uring_sq._fields_ = [ - ('khead', ctypes.POINTER(ctypes.c_uint32)), - ('ktail', ctypes.POINTER(ctypes.c_uint32)), - ('kring_mask', ctypes.POINTER(ctypes.c_uint32)), - ('kring_entries', ctypes.POINTER(ctypes.c_uint32)), - ('kflags', ctypes.POINTER(ctypes.c_uint32)), - ('kdropped', ctypes.POINTER(ctypes.c_uint32)), - ('array', ctypes.POINTER(ctypes.c_uint32)), - ('sqes', ctypes.POINTER(struct_io_uring_sqe)), - ('sqe_head', ctypes.c_uint32), - ('sqe_tail', ctypes.c_uint32), - ('ring_sz', ctypes.c_uint64), - ('ring_ptr', ctypes.POINTER(None)), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('pad', ctypes.c_uint32 * 2), -] - -class union_io_uring_sqe_0(Union): - pass - -class struct_io_uring_sqe_0_0(Structure): - pass - -struct_io_uring_sqe_0_0._pack_ = 1 # source:False -struct_io_uring_sqe_0_0._fields_ = [ - ('cmd_op', ctypes.c_uint32), - ('__pad1', ctypes.c_uint32), -] - -union_io_uring_sqe_0._pack_ = 1 # source:False -union_io_uring_sqe_0._anonymous_ = ('_0',) -union_io_uring_sqe_0._fields_ = [ - ('off', ctypes.c_uint64), - ('addr2', ctypes.c_uint64), - ('_0', struct_io_uring_sqe_0_0), -] - -class union_io_uring_sqe_1(Union): - pass - -union_io_uring_sqe_1._pack_ = 1 # source:False -union_io_uring_sqe_1._fields_ = [ - ('addr', ctypes.c_uint64), - ('splice_off_in', ctypes.c_uint64), -] - -class union_io_uring_sqe_2(Union): - pass - -union_io_uring_sqe_2._pack_ = 1 # source:False -union_io_uring_sqe_2._fields_ = [ - ('rw_flags', ctypes.c_int32), - ('fsync_flags', ctypes.c_uint32), - ('poll_events', ctypes.c_uint16), - ('poll32_events', ctypes.c_uint32), - ('sync_range_flags', ctypes.c_uint32), - ('msg_flags', ctypes.c_uint32), - ('timeout_flags', ctypes.c_uint32), - ('accept_flags', ctypes.c_uint32), - ('cancel_flags', ctypes.c_uint32), - ('open_flags', ctypes.c_uint32), - ('statx_flags', ctypes.c_uint32), - ('fadvise_advice', ctypes.c_uint32), - ('splice_flags', ctypes.c_uint32), - ('rename_flags', ctypes.c_uint32), - ('unlink_flags', ctypes.c_uint32), - ('hardlink_flags', ctypes.c_uint32), - ('xattr_flags', ctypes.c_uint32), - ('msg_ring_flags', ctypes.c_uint32), - ('uring_cmd_flags', ctypes.c_uint32), -] - -class union_io_uring_sqe_3(Union): - pass - -union_io_uring_sqe_3._pack_ = 1 # source:True -union_io_uring_sqe_3._fields_ = [ - ('buf_index', ctypes.c_uint16), - ('buf_group', ctypes.c_uint16), -] - -class union_io_uring_sqe_4(Union): - pass - -class struct_io_uring_sqe_4_0(Structure): - pass - -struct_io_uring_sqe_4_0._pack_ = 1 # source:False -struct_io_uring_sqe_4_0._fields_ = [ - ('addr_len', ctypes.c_uint16), - ('__pad3', ctypes.c_uint16 * 1), -] - -union_io_uring_sqe_4._pack_ = 1 # source:False -union_io_uring_sqe_4._anonymous_ = ('_0',) -union_io_uring_sqe_4._fields_ = [ - ('splice_fd_in', ctypes.c_int32), - ('file_index', ctypes.c_uint32), - ('_0', struct_io_uring_sqe_4_0), -] - -class union_io_uring_sqe_5(Union): - pass - -class struct_io_uring_sqe_5_0(Structure): - pass - -struct_io_uring_sqe_5_0._pack_ = 1 # source:False -struct_io_uring_sqe_5_0._fields_ = [ - ('addr3', ctypes.c_uint64), - ('__pad2', ctypes.c_uint64 * 1), -] - -union_io_uring_sqe_5._pack_ = 1 # source:False -union_io_uring_sqe_5._anonymous_ = ('_0',) -union_io_uring_sqe_5._fields_ = [ - ('_0', struct_io_uring_sqe_5_0), - ('cmd', ctypes.c_ubyte * 0), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_io_uring_sqe._pack_ = 1 # source:False -struct_io_uring_sqe._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5',) -struct_io_uring_sqe._fields_ = [ - ('opcode', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('ioprio', ctypes.c_uint16), - ('fd', ctypes.c_int32), - ('_0', union_io_uring_sqe_0), - ('_1', union_io_uring_sqe_1), - ('len', ctypes.c_uint32), - ('_2', union_io_uring_sqe_2), - ('user_data', ctypes.c_uint64), - ('_3', union_io_uring_sqe_3), - ('personality', ctypes.c_uint16), - ('_4', union_io_uring_sqe_4), - ('_5', union_io_uring_sqe_5), -] - -class struct_io_uring_cq(Structure): - pass - -class struct_io_uring_cqe(Structure): - pass - -struct_io_uring_cq._pack_ = 1 # source:False -struct_io_uring_cq._fields_ = [ - ('khead', ctypes.POINTER(ctypes.c_uint32)), - ('ktail', ctypes.POINTER(ctypes.c_uint32)), - ('kring_mask', ctypes.POINTER(ctypes.c_uint32)), - ('kring_entries', ctypes.POINTER(ctypes.c_uint32)), - ('kflags', ctypes.POINTER(ctypes.c_uint32)), - ('koverflow', ctypes.POINTER(ctypes.c_uint32)), - ('cqes', ctypes.POINTER(struct_io_uring_cqe)), - ('ring_sz', ctypes.c_uint64), - ('ring_ptr', ctypes.POINTER(None)), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('pad', ctypes.c_uint32 * 2), -] - -struct_io_uring_cqe._pack_ = 1 # source:False -struct_io_uring_cqe._fields_ = [ - ('user_data', ctypes.c_uint64), - ('res', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('big_cqe', ctypes.c_uint64 * 0), -] - -class struct_io_uring(Structure): - pass - -struct_io_uring._pack_ = 1 # source:False -struct_io_uring._fields_ = [ - ('sq', struct_io_uring_sq), - ('cq', struct_io_uring_cq), - ('flags', ctypes.c_uint32), - ('ring_fd', ctypes.c_int32), - ('features', ctypes.c_uint32), - ('enter_ring_fd', ctypes.c_int32), - ('int_flags', ctypes.c_ubyte), - ('pad', ctypes.c_ubyte * 3), - ('pad2', ctypes.c_uint32), -] - -class struct_io_uring_probe(Structure): - pass - -class struct_io_uring_probe_op(Structure): - pass - -struct_io_uring_probe_op._pack_ = 1 # source:False -struct_io_uring_probe_op._fields_ = [ - ('op', ctypes.c_ubyte), - ('resv', ctypes.c_ubyte), - ('flags', ctypes.c_uint16), - ('resv2', ctypes.c_uint32), -] - -struct_io_uring_probe._pack_ = 1 # source:False -struct_io_uring_probe._fields_ = [ - ('last_op', ctypes.c_ubyte), - ('ops_len', ctypes.c_ubyte), - ('resv', ctypes.c_uint16), - ('resv2', ctypes.c_uint32 * 3), - ('ops', struct_io_uring_probe_op * 0), -] - -try: - io_uring_get_probe_ring = _libraries['FIXME_STUB'].io_uring_get_probe_ring - io_uring_get_probe_ring.restype = ctypes.POINTER(struct_io_uring_probe) - io_uring_get_probe_ring.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_get_probe = _libraries['FIXME_STUB'].io_uring_get_probe - io_uring_get_probe.restype = ctypes.POINTER(struct_io_uring_probe) - io_uring_get_probe.argtypes = [] -except AttributeError: - pass -try: - io_uring_free_probe = _libraries['FIXME_STUB'].io_uring_free_probe - io_uring_free_probe.restype = None - io_uring_free_probe.argtypes = [ctypes.POINTER(struct_io_uring_probe)] -except AttributeError: - pass -try: - io_uring_opcode_supported = _libraries['FIXME_STUB'].io_uring_opcode_supported - io_uring_opcode_supported.restype = ctypes.c_int32 - io_uring_opcode_supported.argtypes = [ctypes.POINTER(struct_io_uring_probe), ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_params(Structure): - pass - -class struct_io_sqring_offsets(Structure): - pass - -struct_io_sqring_offsets._pack_ = 1 # source:False -struct_io_sqring_offsets._fields_ = [ - ('head', ctypes.c_uint32), - ('tail', ctypes.c_uint32), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('dropped', ctypes.c_uint32), - ('array', ctypes.c_uint32), - ('resv1', ctypes.c_uint32), - ('user_addr', ctypes.c_uint64), -] - -class struct_io_cqring_offsets(Structure): - pass - -struct_io_cqring_offsets._pack_ = 1 # source:False -struct_io_cqring_offsets._fields_ = [ - ('head', ctypes.c_uint32), - ('tail', ctypes.c_uint32), - ('ring_mask', ctypes.c_uint32), - ('ring_entries', ctypes.c_uint32), - ('overflow', ctypes.c_uint32), - ('cqes', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('resv1', ctypes.c_uint32), - ('user_addr', ctypes.c_uint64), -] - -struct_io_uring_params._pack_ = 1 # source:False -struct_io_uring_params._fields_ = [ - ('sq_entries', ctypes.c_uint32), - ('cq_entries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('sq_thread_cpu', ctypes.c_uint32), - ('sq_thread_idle', ctypes.c_uint32), - ('features', ctypes.c_uint32), - ('wq_fd', ctypes.c_uint32), - ('resv', ctypes.c_uint32 * 3), - ('sq_off', struct_io_sqring_offsets), - ('cq_off', struct_io_cqring_offsets), -] - -size_t = ctypes.c_uint64 -try: - io_uring_queue_init_mem = _libraries['FIXME_STUB'].io_uring_queue_init_mem - io_uring_queue_init_mem.restype = ctypes.c_int32 - io_uring_queue_init_mem.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_params), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - io_uring_queue_init_params = _libraries['FIXME_STUB'].io_uring_queue_init_params - io_uring_queue_init_params.restype = ctypes.c_int32 - io_uring_queue_init_params.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_params)] -except AttributeError: - pass -try: - io_uring_queue_init = _libraries['FIXME_STUB'].io_uring_queue_init - io_uring_queue_init.restype = ctypes.c_int32 - io_uring_queue_init.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_queue_mmap = _libraries['FIXME_STUB'].io_uring_queue_mmap - io_uring_queue_mmap.restype = ctypes.c_int32 - io_uring_queue_mmap.argtypes = [ctypes.c_int32, ctypes.POINTER(struct_io_uring_params), ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_ring_dontfork = _libraries['FIXME_STUB'].io_uring_ring_dontfork - io_uring_ring_dontfork.restype = ctypes.c_int32 - io_uring_ring_dontfork.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_queue_exit = _libraries['FIXME_STUB'].io_uring_queue_exit - io_uring_queue_exit.restype = None - io_uring_queue_exit.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_peek_batch_cqe = _libraries['FIXME_STUB'].io_uring_peek_batch_cqe - io_uring_peek_batch_cqe.restype = ctypes.c_uint32 - io_uring_peek_batch_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32] -except AttributeError: - pass -class struct___kernel_timespec(Structure): - pass - -struct___kernel_timespec._pack_ = 1 # source:False -struct___kernel_timespec._fields_ = [ - ('tv_sec', ctypes.c_int64), - ('tv_nsec', ctypes.c_int64), -] - -class struct_c__SA___sigset_t(Structure): - pass - -struct_c__SA___sigset_t._pack_ = 1 # source:False -struct_c__SA___sigset_t._fields_ = [ - ('__val', ctypes.c_uint64 * 16), -] - -try: - io_uring_wait_cqes = _libraries['FIXME_STUB'].io_uring_wait_cqes - io_uring_wait_cqes.restype = ctypes.c_int32 - io_uring_wait_cqes.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32, ctypes.POINTER(struct___kernel_timespec), ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -try: - io_uring_wait_cqe_timeout = _libraries['FIXME_STUB'].io_uring_wait_cqe_timeout - io_uring_wait_cqe_timeout.restype = ctypes.c_int32 - io_uring_wait_cqe_timeout.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.POINTER(struct___kernel_timespec)] -except AttributeError: - pass -try: - io_uring_submit = _libraries['FIXME_STUB'].io_uring_submit - io_uring_submit.restype = ctypes.c_int32 - io_uring_submit.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_submit_and_wait = _libraries['FIXME_STUB'].io_uring_submit_and_wait - io_uring_submit_and_wait.restype = ctypes.c_int32 - io_uring_submit_and_wait.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_submit_and_wait_timeout = _libraries['FIXME_STUB'].io_uring_submit_and_wait_timeout - io_uring_submit_and_wait_timeout.restype = ctypes.c_int32 - io_uring_submit_and_wait_timeout.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32, ctypes.POINTER(struct___kernel_timespec), ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -class struct_iovec(Structure): - pass - -struct_iovec._pack_ = 1 # source:False -struct_iovec._fields_ = [ - ('iov_base', ctypes.POINTER(None)), - ('iov_len', ctypes.c_uint64), -] - -try: - io_uring_register_buffers = _libraries['FIXME_STUB'].io_uring_register_buffers - io_uring_register_buffers.restype = ctypes.c_int32 - io_uring_register_buffers.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_iovec), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_buffers_tags = _libraries['FIXME_STUB'].io_uring_register_buffers_tags - io_uring_register_buffers_tags.restype = ctypes.c_int32 - io_uring_register_buffers_tags.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_iovec), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_buffers_sparse = _libraries['FIXME_STUB'].io_uring_register_buffers_sparse - io_uring_register_buffers_sparse.restype = ctypes.c_int32 - io_uring_register_buffers_sparse.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_buffers_update_tag = _libraries['FIXME_STUB'].io_uring_register_buffers_update_tag - io_uring_register_buffers_update_tag.restype = ctypes.c_int32 - io_uring_register_buffers_update_tag.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.POINTER(struct_iovec), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_unregister_buffers = _libraries['FIXME_STUB'].io_uring_unregister_buffers - io_uring_unregister_buffers.restype = ctypes.c_int32 - io_uring_unregister_buffers.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_files = _libraries['FIXME_STUB'].io_uring_register_files - io_uring_register_files.restype = ctypes.c_int32 - io_uring_register_files.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_files_tags = _libraries['FIXME_STUB'].io_uring_register_files_tags - io_uring_register_files_tags.restype = ctypes.c_int32 - io_uring_register_files_tags.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_files_sparse = _libraries['FIXME_STUB'].io_uring_register_files_sparse - io_uring_register_files_sparse.restype = ctypes.c_int32 - io_uring_register_files_sparse.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_files_update_tag = _libraries['FIXME_STUB'].io_uring_register_files_update_tag - io_uring_register_files_update_tag.restype = ctypes.c_int32 - io_uring_register_files_update_tag.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_unregister_files = _libraries['FIXME_STUB'].io_uring_unregister_files - io_uring_unregister_files.restype = ctypes.c_int32 - io_uring_unregister_files.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_files_update = _libraries['FIXME_STUB'].io_uring_register_files_update - io_uring_register_files_update.restype = ctypes.c_int32 - io_uring_register_files_update.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_eventfd = _libraries['FIXME_STUB'].io_uring_register_eventfd - io_uring_register_eventfd.restype = ctypes.c_int32 - io_uring_register_eventfd.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_register_eventfd_async = _libraries['FIXME_STUB'].io_uring_register_eventfd_async - io_uring_register_eventfd_async.restype = ctypes.c_int32 - io_uring_register_eventfd_async.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_unregister_eventfd = _libraries['FIXME_STUB'].io_uring_unregister_eventfd - io_uring_unregister_eventfd.restype = ctypes.c_int32 - io_uring_unregister_eventfd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_probe = _libraries['FIXME_STUB'].io_uring_register_probe - io_uring_register_probe.restype = ctypes.c_int32 - io_uring_register_probe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_probe), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_register_personality = _libraries['FIXME_STUB'].io_uring_register_personality - io_uring_register_personality.restype = ctypes.c_int32 - io_uring_register_personality.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_unregister_personality = _libraries['FIXME_STUB'].io_uring_unregister_personality - io_uring_unregister_personality.restype = ctypes.c_int32 - io_uring_unregister_personality.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_restriction(Structure): - pass - -class union_io_uring_restriction_0(Union): - pass - -union_io_uring_restriction_0._pack_ = 1 # source:False -union_io_uring_restriction_0._fields_ = [ - ('register_op', ctypes.c_ubyte), - ('sqe_op', ctypes.c_ubyte), - ('sqe_flags', ctypes.c_ubyte), -] - -struct_io_uring_restriction._pack_ = 1 # source:False -struct_io_uring_restriction._anonymous_ = ('_0',) -struct_io_uring_restriction._fields_ = [ - ('opcode', ctypes.c_uint16), - ('_0', union_io_uring_restriction_0), - ('resv', ctypes.c_ubyte), - ('resv2', ctypes.c_uint32 * 3), -] - -try: - io_uring_register_restrictions = _libraries['FIXME_STUB'].io_uring_register_restrictions - io_uring_register_restrictions.restype = ctypes.c_int32 - io_uring_register_restrictions.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_restriction), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_enable_rings = _libraries['FIXME_STUB'].io_uring_enable_rings - io_uring_enable_rings.restype = ctypes.c_int32 - io_uring_enable_rings.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - __io_uring_sqring_wait = _libraries['FIXME_STUB'].__io_uring_sqring_wait - __io_uring_sqring_wait.restype = ctypes.c_int32 - __io_uring_sqring_wait.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -class struct_c__SA_cpu_set_t(Structure): - pass - -struct_c__SA_cpu_set_t._pack_ = 1 # source:False -struct_c__SA_cpu_set_t._fields_ = [ - ('__bits', ctypes.c_uint64 * 16), -] - -try: - io_uring_register_iowq_aff = _libraries['FIXME_STUB'].io_uring_register_iowq_aff - io_uring_register_iowq_aff.restype = ctypes.c_int32 - io_uring_register_iowq_aff.argtypes = [ctypes.POINTER(struct_io_uring), size_t, ctypes.POINTER(struct_c__SA_cpu_set_t)] -except AttributeError: - pass -try: - io_uring_unregister_iowq_aff = _libraries['FIXME_STUB'].io_uring_unregister_iowq_aff - io_uring_unregister_iowq_aff.restype = ctypes.c_int32 - io_uring_unregister_iowq_aff.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_register_iowq_max_workers = _libraries['FIXME_STUB'].io_uring_register_iowq_max_workers - io_uring_register_iowq_max_workers.restype = ctypes.c_int32 - io_uring_register_iowq_max_workers.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - io_uring_register_ring_fd = _libraries['FIXME_STUB'].io_uring_register_ring_fd - io_uring_register_ring_fd.restype = ctypes.c_int32 - io_uring_register_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_unregister_ring_fd = _libraries['FIXME_STUB'].io_uring_unregister_ring_fd - io_uring_unregister_ring_fd.restype = ctypes.c_int32 - io_uring_unregister_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_close_ring_fd = _libraries['FIXME_STUB'].io_uring_close_ring_fd - io_uring_close_ring_fd.restype = ctypes.c_int32 - io_uring_close_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -class struct_io_uring_buf_reg(Structure): - pass - -struct_io_uring_buf_reg._pack_ = 1 # source:False -struct_io_uring_buf_reg._fields_ = [ - ('ring_addr', ctypes.c_uint64), - ('ring_entries', ctypes.c_uint32), - ('bgid', ctypes.c_uint16), - ('flags', ctypes.c_uint16), - ('resv', ctypes.c_uint64 * 3), -] - -try: - io_uring_register_buf_ring = _libraries['FIXME_STUB'].io_uring_register_buf_ring - io_uring_register_buf_ring.restype = ctypes.c_int32 - io_uring_register_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_reg), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_unregister_buf_ring = _libraries['FIXME_STUB'].io_uring_unregister_buf_ring - io_uring_unregister_buf_ring.restype = ctypes.c_int32 - io_uring_unregister_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_sync_cancel_reg(Structure): - pass - -struct_io_uring_sync_cancel_reg._pack_ = 1 # source:False -struct_io_uring_sync_cancel_reg._fields_ = [ - ('addr', ctypes.c_uint64), - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('timeout', struct___kernel_timespec), - ('pad', ctypes.c_uint64 * 4), -] - -try: - io_uring_register_sync_cancel = _libraries['FIXME_STUB'].io_uring_register_sync_cancel - io_uring_register_sync_cancel.restype = ctypes.c_int32 - io_uring_register_sync_cancel.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_sync_cancel_reg)] -except AttributeError: - pass -try: - io_uring_register_file_alloc_range = _libraries['FIXME_STUB'].io_uring_register_file_alloc_range - io_uring_register_file_alloc_range.restype = ctypes.c_int32 - io_uring_register_file_alloc_range.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_get_events = _libraries['FIXME_STUB'].io_uring_get_events - io_uring_get_events.restype = ctypes.c_int32 - io_uring_get_events.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_submit_and_get_events = _libraries['FIXME_STUB'].io_uring_submit_and_get_events - io_uring_submit_and_get_events.restype = ctypes.c_int32 - io_uring_submit_and_get_events.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_enter = _libraries['FIXME_STUB'].io_uring_enter - io_uring_enter.restype = ctypes.c_int32 - io_uring_enter.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -try: - io_uring_enter2 = _libraries['FIXME_STUB'].io_uring_enter2 - io_uring_enter2.restype = ctypes.c_int32 - io_uring_enter2.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_c__SA___sigset_t), size_t] -except AttributeError: - pass -try: - io_uring_setup = _libraries['FIXME_STUB'].io_uring_setup - io_uring_setup.restype = ctypes.c_int32 - io_uring_setup.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring_params)] -except AttributeError: - pass -try: - io_uring_register = _libraries['FIXME_STUB'].io_uring_register - io_uring_register.restype = ctypes.c_int32 - io_uring_register.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -class struct_io_uring_buf_ring(Structure): - pass - -class union_io_uring_buf_ring_0(Union): - pass - -class struct_io_uring_buf_ring_0_0(Structure): - pass - -struct_io_uring_buf_ring_0_0._pack_ = 1 # source:False -struct_io_uring_buf_ring_0_0._fields_ = [ - ('resv1', ctypes.c_uint64), - ('resv2', ctypes.c_uint32), - ('resv3', ctypes.c_uint16), - ('tail', ctypes.c_uint16), -] - -class struct_io_uring_buf(Structure): - pass - -struct_io_uring_buf._pack_ = 1 # source:False -struct_io_uring_buf._fields_ = [ - ('addr', ctypes.c_uint64), - ('len', ctypes.c_uint32), - ('bid', ctypes.c_uint16), - ('resv', ctypes.c_uint16), -] - -union_io_uring_buf_ring_0._pack_ = 1 # source:False -union_io_uring_buf_ring_0._anonymous_ = ('_0',) -union_io_uring_buf_ring_0._fields_ = [ - ('_0', struct_io_uring_buf_ring_0_0), - ('bufs', struct_io_uring_buf * 0), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_io_uring_buf_ring._pack_ = 1 # source:False -struct_io_uring_buf_ring._anonymous_ = ('_0',) -struct_io_uring_buf_ring._fields_ = [ - ('_0', union_io_uring_buf_ring_0), -] - -try: - io_uring_setup_buf_ring = _libraries['FIXME_STUB'].io_uring_setup_buf_ring - io_uring_setup_buf_ring.restype = ctypes.POINTER(struct_io_uring_buf_ring) - io_uring_setup_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32, ctypes.c_int32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - io_uring_free_buf_ring = _libraries['FIXME_STUB'].io_uring_free_buf_ring - io_uring_free_buf_ring.restype = ctypes.c_int32 - io_uring_free_buf_ring.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - __io_uring_get_cqe = _libraries['FIXME_STUB'].__io_uring_get_cqe - __io_uring_get_cqe.restype = ctypes.c_int32 - __io_uring_get_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(struct_c__SA___sigset_t)] -except AttributeError: - pass -try: - io_uring_cq_advance = _libraries['FIXME_STUB'].io_uring_cq_advance - io_uring_cq_advance.restype = None - io_uring_cq_advance.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_cqe_seen = _libraries['FIXME_STUB'].io_uring_cqe_seen - io_uring_cqe_seen.restype = None - io_uring_cqe_seen.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_cqe)] -except AttributeError: - pass -try: - io_uring_sqe_set_data = _libraries['FIXME_STUB'].io_uring_sqe_set_data - io_uring_sqe_set_data.restype = None - io_uring_sqe_set_data.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None)] -except AttributeError: - pass -try: - io_uring_cqe_get_data = _libraries['FIXME_STUB'].io_uring_cqe_get_data - io_uring_cqe_get_data.restype = ctypes.POINTER(None) - io_uring_cqe_get_data.argtypes = [ctypes.POINTER(struct_io_uring_cqe)] -except AttributeError: - pass -__u64 = ctypes.c_uint64 -# LIBURING_UDATA_TIMEOUT = ((__u64)-1) # macro -try: - io_uring_sqe_set_data64 = _libraries['FIXME_STUB'].io_uring_sqe_set_data64 - io_uring_sqe_set_data64.restype = None - io_uring_sqe_set_data64.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64] -except AttributeError: - pass -try: - io_uring_cqe_get_data64 = _libraries['FIXME_STUB'].io_uring_cqe_get_data64 - io_uring_cqe_get_data64.restype = __u64 - io_uring_cqe_get_data64.argtypes = [ctypes.POINTER(struct_io_uring_cqe)] -except AttributeError: - pass -try: - io_uring_sqe_set_flags = _libraries['FIXME_STUB'].io_uring_sqe_set_flags - io_uring_sqe_set_flags.restype = None - io_uring_sqe_set_flags.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_uint32] -except AttributeError: - pass -try: - __io_uring_set_target_fixed_file = _libraries['FIXME_STUB'].__io_uring_set_target_fixed_file - __io_uring_set_target_fixed_file.restype = None - __io_uring_set_target_fixed_file.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_rw = _libraries['FIXME_STUB'].io_uring_prep_rw - io_uring_prep_rw.restype = None - io_uring_prep_rw.argtypes = [ctypes.c_int32, ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64] -except AttributeError: - pass -int64_t = ctypes.c_int64 -try: - io_uring_prep_splice = _libraries['FIXME_STUB'].io_uring_prep_splice - io_uring_prep_splice.restype = None - io_uring_prep_splice.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, int64_t, ctypes.c_int32, int64_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_tee = _libraries['FIXME_STUB'].io_uring_prep_tee - io_uring_prep_tee.restype = None - io_uring_prep_tee.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_readv = _libraries['FIXME_STUB'].io_uring_prep_readv - io_uring_prep_readv.restype = None - io_uring_prep_readv.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64] -except AttributeError: - pass -try: - io_uring_prep_readv2 = _libraries['FIXME_STUB'].io_uring_prep_readv2 - io_uring_prep_readv2.restype = None - io_uring_prep_readv2.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_read_fixed = _libraries['FIXME_STUB'].io_uring_prep_read_fixed - io_uring_prep_read_fixed.restype = None - io_uring_prep_read_fixed.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_writev = _libraries['FIXME_STUB'].io_uring_prep_writev - io_uring_prep_writev.restype = None - io_uring_prep_writev.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64] -except AttributeError: - pass -try: - io_uring_prep_writev2 = _libraries['FIXME_STUB'].io_uring_prep_writev2 - io_uring_prep_writev2.restype = None - io_uring_prep_writev2.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_iovec), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_write_fixed = _libraries['FIXME_STUB'].io_uring_prep_write_fixed - io_uring_prep_write_fixed.restype = None - io_uring_prep_write_fixed.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -class struct_msghdr(Structure): - pass - -struct_msghdr._pack_ = 1 # source:False -struct_msghdr._fields_ = [ - ('msg_name', ctypes.POINTER(None)), - ('msg_namelen', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('msg_iov', ctypes.POINTER(struct_iovec)), - ('msg_iovlen', ctypes.c_uint64), - ('msg_control', ctypes.POINTER(None)), - ('msg_controllen', ctypes.c_uint64), - ('msg_flags', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -try: - io_uring_prep_recvmsg = _libraries['FIXME_STUB'].io_uring_prep_recvmsg - io_uring_prep_recvmsg.restype = None - io_uring_prep_recvmsg.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_recvmsg_multishot = _libraries['FIXME_STUB'].io_uring_prep_recvmsg_multishot - io_uring_prep_recvmsg_multishot.restype = None - io_uring_prep_recvmsg_multishot.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_sendmsg = _libraries['FIXME_STUB'].io_uring_prep_sendmsg - io_uring_prep_sendmsg.restype = None - io_uring_prep_sendmsg.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - __io_uring_prep_poll_mask = _libraries['FIXME_STUB'].__io_uring_prep_poll_mask - __io_uring_prep_poll_mask.restype = ctypes.c_uint32 - __io_uring_prep_poll_mask.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_poll_add = _libraries['FIXME_STUB'].io_uring_prep_poll_add - io_uring_prep_poll_add.restype = None - io_uring_prep_poll_add.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_poll_multishot = _libraries['FIXME_STUB'].io_uring_prep_poll_multishot - io_uring_prep_poll_multishot.restype = None - io_uring_prep_poll_multishot.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_poll_remove = _libraries['FIXME_STUB'].io_uring_prep_poll_remove - io_uring_prep_poll_remove.restype = None - io_uring_prep_poll_remove.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64] -except AttributeError: - pass -try: - io_uring_prep_poll_update = _libraries['FIXME_STUB'].io_uring_prep_poll_update - io_uring_prep_poll_update.restype = None - io_uring_prep_poll_update.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64, __u64, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_fsync = _libraries['FIXME_STUB'].io_uring_prep_fsync - io_uring_prep_fsync.restype = None - io_uring_prep_fsync.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_nop = _libraries['FIXME_STUB'].io_uring_prep_nop - io_uring_prep_nop.restype = None - io_uring_prep_nop.argtypes = [ctypes.POINTER(struct_io_uring_sqe)] -except AttributeError: - pass -try: - io_uring_prep_timeout = _libraries['FIXME_STUB'].io_uring_prep_timeout - io_uring_prep_timeout.restype = None - io_uring_prep_timeout.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct___kernel_timespec), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_timeout_remove = _libraries['FIXME_STUB'].io_uring_prep_timeout_remove - io_uring_prep_timeout_remove.restype = None - io_uring_prep_timeout_remove.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_timeout_update = _libraries['FIXME_STUB'].io_uring_prep_timeout_update - io_uring_prep_timeout_update.restype = None - io_uring_prep_timeout_update.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct___kernel_timespec), __u64, ctypes.c_uint32] -except AttributeError: - pass -class struct_sockaddr(Structure): - pass - -struct_sockaddr._pack_ = 1 # source:False -struct_sockaddr._fields_ = [ - ('sa_family', ctypes.c_uint16), - ('sa_data', ctypes.c_char * 14), -] - -try: - io_uring_prep_accept = _libraries['FIXME_STUB'].io_uring_prep_accept - io_uring_prep_accept.restype = None - io_uring_prep_accept.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_accept_direct = _libraries['FIXME_STUB'].io_uring_prep_accept_direct - io_uring_prep_accept_direct.restype = None - io_uring_prep_accept_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_multishot_accept = _libraries['FIXME_STUB'].io_uring_prep_multishot_accept - io_uring_prep_multishot_accept.restype = None - io_uring_prep_multishot_accept.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_multishot_accept_direct = _libraries['FIXME_STUB'].io_uring_prep_multishot_accept_direct - io_uring_prep_multishot_accept_direct.restype = None - io_uring_prep_multishot_accept_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), ctypes.POINTER(ctypes.c_uint32), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_cancel64 = _libraries['FIXME_STUB'].io_uring_prep_cancel64 - io_uring_prep_cancel64.restype = None - io_uring_prep_cancel64.argtypes = [ctypes.POINTER(struct_io_uring_sqe), __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_cancel = _libraries['FIXME_STUB'].io_uring_prep_cancel - io_uring_prep_cancel.restype = None - io_uring_prep_cancel.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_cancel_fd = _libraries['FIXME_STUB'].io_uring_prep_cancel_fd - io_uring_prep_cancel_fd.restype = None - io_uring_prep_cancel_fd.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_link_timeout = _libraries['FIXME_STUB'].io_uring_prep_link_timeout - io_uring_prep_link_timeout.restype = None - io_uring_prep_link_timeout.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct___kernel_timespec), ctypes.c_uint32] -except AttributeError: - pass -socklen_t = ctypes.c_uint32 -try: - io_uring_prep_connect = _libraries['FIXME_STUB'].io_uring_prep_connect - io_uring_prep_connect.restype = None - io_uring_prep_connect.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_sockaddr), socklen_t] -except AttributeError: - pass -try: - io_uring_prep_files_update = _libraries['FIXME_STUB'].io_uring_prep_files_update - io_uring_prep_files_update.restype = None - io_uring_prep_files_update.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_fallocate = _libraries['FIXME_STUB'].io_uring_prep_fallocate - io_uring_prep_fallocate.restype = None - io_uring_prep_fallocate.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, __u64, __u64] -except AttributeError: - pass -mode_t = ctypes.c_uint32 -try: - io_uring_prep_openat = _libraries['FIXME_STUB'].io_uring_prep_openat - io_uring_prep_openat.restype = None - io_uring_prep_openat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, mode_t] -except AttributeError: - pass -try: - io_uring_prep_openat_direct = _libraries['FIXME_STUB'].io_uring_prep_openat_direct - io_uring_prep_openat_direct.restype = None - io_uring_prep_openat_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, mode_t, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_close = _libraries['FIXME_STUB'].io_uring_prep_close - io_uring_prep_close.restype = None - io_uring_prep_close.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_close_direct = _libraries['FIXME_STUB'].io_uring_prep_close_direct - io_uring_prep_close_direct.restype = None - io_uring_prep_close_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_read = _libraries['FIXME_STUB'].io_uring_prep_read - io_uring_prep_read.restype = None - io_uring_prep_read.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64] -except AttributeError: - pass -try: - io_uring_prep_write = _libraries['FIXME_STUB'].io_uring_prep_write - io_uring_prep_write.restype = None - io_uring_prep_write.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint32, __u64] -except AttributeError: - pass -class struct_statx(Structure): - pass - -try: - io_uring_prep_statx = _libraries['FIXME_STUB'].io_uring_prep_statx - io_uring_prep_statx.restype = None - io_uring_prep_statx.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_uint32, ctypes.POINTER(struct_statx)] -except AttributeError: - pass -off_t = ctypes.c_int64 -try: - io_uring_prep_fadvise = _libraries['FIXME_STUB'].io_uring_prep_fadvise - io_uring_prep_fadvise.restype = None - io_uring_prep_fadvise.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, __u64, off_t, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_madvise = _libraries['FIXME_STUB'].io_uring_prep_madvise - io_uring_prep_madvise.restype = None - io_uring_prep_madvise.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None), off_t, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_send = _libraries['FIXME_STUB'].io_uring_prep_send - io_uring_prep_send.restype = None - io_uring_prep_send.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class struct_io_uring_sq(Struct): pass +class struct_io_uring_sqe(Struct): pass +__u8 = ctypes.c_ubyte __u16 = ctypes.c_uint16 -try: - io_uring_prep_send_set_addr = _libraries['FIXME_STUB'].io_uring_prep_send_set_addr - io_uring_prep_send_set_addr.restype = None - io_uring_prep_send_set_addr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(struct_sockaddr), __u16] -except AttributeError: - pass -try: - io_uring_prep_sendto = _libraries['FIXME_STUB'].io_uring_prep_sendto - io_uring_prep_sendto.restype = None - io_uring_prep_sendto.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.POINTER(struct_sockaddr), socklen_t] -except AttributeError: - pass -try: - io_uring_prep_send_zc = _libraries['FIXME_STUB'].io_uring_prep_send_zc - io_uring_prep_send_zc.restype = None - io_uring_prep_send_zc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_send_zc_fixed = _libraries['FIXME_STUB'].io_uring_prep_send_zc_fixed - io_uring_prep_send_zc_fixed.restype = None - io_uring_prep_send_zc_fixed.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_sendmsg_zc = _libraries['FIXME_STUB'].io_uring_prep_sendmsg_zc - io_uring_prep_sendmsg_zc.restype = None - io_uring_prep_sendmsg_zc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(struct_msghdr), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_recv = _libraries['FIXME_STUB'].io_uring_prep_recv - io_uring_prep_recv.restype = None - io_uring_prep_recv.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_recv_multishot = _libraries['FIXME_STUB'].io_uring_prep_recv_multishot - io_uring_prep_recv_multishot.restype = None - io_uring_prep_recv_multishot.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -class struct_io_uring_recvmsg_out(Structure): - pass - -struct_io_uring_recvmsg_out._pack_ = 1 # source:False -struct_io_uring_recvmsg_out._fields_ = [ - ('namelen', ctypes.c_uint32), - ('controllen', ctypes.c_uint32), - ('payloadlen', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -try: - io_uring_recvmsg_validate = _libraries['FIXME_STUB'].io_uring_recvmsg_validate - io_uring_recvmsg_validate.restype = ctypes.POINTER(struct_io_uring_recvmsg_out) - io_uring_recvmsg_validate.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_name = _libraries['FIXME_STUB'].io_uring_recvmsg_name - io_uring_recvmsg_name.restype = ctypes.POINTER(None) - io_uring_recvmsg_name.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out)] -except AttributeError: - pass -class struct_cmsghdr(Structure): - pass - -struct_cmsghdr._pack_ = 1 # source:False -struct_cmsghdr._fields_ = [ - ('cmsg_len', ctypes.c_uint64), - ('cmsg_level', ctypes.c_int32), - ('cmsg_type', ctypes.c_int32), - ('__cmsg_data', ctypes.c_ubyte * 0), -] - -try: - io_uring_recvmsg_cmsg_firsthdr = _libraries['FIXME_STUB'].io_uring_recvmsg_cmsg_firsthdr - io_uring_recvmsg_cmsg_firsthdr.restype = ctypes.POINTER(struct_cmsghdr) - io_uring_recvmsg_cmsg_firsthdr.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_cmsg_nexthdr = _libraries['FIXME_STUB'].io_uring_recvmsg_cmsg_nexthdr - io_uring_recvmsg_cmsg_nexthdr.restype = ctypes.POINTER(struct_cmsghdr) - io_uring_recvmsg_cmsg_nexthdr.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.POINTER(struct_msghdr), ctypes.POINTER(struct_cmsghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_payload = _libraries['FIXME_STUB'].io_uring_recvmsg_payload - io_uring_recvmsg_payload.restype = ctypes.POINTER(None) - io_uring_recvmsg_payload.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -try: - io_uring_recvmsg_payload_length = _libraries['FIXME_STUB'].io_uring_recvmsg_payload_length - io_uring_recvmsg_payload_length.restype = ctypes.c_uint32 - io_uring_recvmsg_payload_length.argtypes = [ctypes.POINTER(struct_io_uring_recvmsg_out), ctypes.c_int32, ctypes.POINTER(struct_msghdr)] -except AttributeError: - pass -class struct_open_how(Structure): - pass - -struct_open_how._pack_ = 1 # source:False -struct_open_how._fields_ = [ - ('flags', ctypes.c_uint64), - ('mode', ctypes.c_uint64), - ('resolve', ctypes.c_uint64), -] - -try: - io_uring_prep_openat2 = _libraries['FIXME_STUB'].io_uring_prep_openat2 - io_uring_prep_openat2.restype = None - io_uring_prep_openat2.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_open_how)] -except AttributeError: - pass -try: - io_uring_prep_openat2_direct = _libraries['FIXME_STUB'].io_uring_prep_openat2_direct - io_uring_prep_openat2_direct.restype = None - io_uring_prep_openat2_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_open_how), ctypes.c_uint32] -except AttributeError: - pass -class struct_epoll_event(Structure): - pass - -try: - io_uring_prep_epoll_ctl = _libraries['FIXME_STUB'].io_uring_prep_epoll_ctl - io_uring_prep_epoll_ctl.restype = None - io_uring_prep_epoll_ctl.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(struct_epoll_event)] -except AttributeError: - pass -try: - io_uring_prep_provide_buffers = _libraries['FIXME_STUB'].io_uring_prep_provide_buffers - io_uring_prep_provide_buffers.restype = None - io_uring_prep_provide_buffers.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_remove_buffers = _libraries['FIXME_STUB'].io_uring_prep_remove_buffers - io_uring_prep_remove_buffers.restype = None - io_uring_prep_remove_buffers.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_shutdown = _libraries['FIXME_STUB'].io_uring_prep_shutdown - io_uring_prep_shutdown.restype = None - io_uring_prep_shutdown.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_unlinkat = _libraries['FIXME_STUB'].io_uring_prep_unlinkat - io_uring_prep_unlinkat.restype = None - io_uring_prep_unlinkat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_unlink = _libraries['FIXME_STUB'].io_uring_prep_unlink - io_uring_prep_unlink.restype = None - io_uring_prep_unlink.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_renameat = _libraries['FIXME_STUB'].io_uring_prep_renameat - io_uring_prep_renameat.restype = None - io_uring_prep_renameat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_rename = _libraries['FIXME_STUB'].io_uring_prep_rename - io_uring_prep_rename.restype = None - io_uring_prep_rename.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - io_uring_prep_sync_file_range = _libraries['FIXME_STUB'].io_uring_prep_sync_file_range - io_uring_prep_sync_file_range.restype = None - io_uring_prep_sync_file_range.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32, __u64, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_mkdirat = _libraries['FIXME_STUB'].io_uring_prep_mkdirat - io_uring_prep_mkdirat.restype = None - io_uring_prep_mkdirat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), mode_t] -except AttributeError: - pass -try: - io_uring_prep_mkdir = _libraries['FIXME_STUB'].io_uring_prep_mkdir - io_uring_prep_mkdir.restype = None - io_uring_prep_mkdir.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), mode_t] -except AttributeError: - pass -try: - io_uring_prep_symlinkat = _libraries['FIXME_STUB'].io_uring_prep_symlinkat - io_uring_prep_symlinkat.restype = None - io_uring_prep_symlinkat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - io_uring_prep_symlink = _libraries['FIXME_STUB'].io_uring_prep_symlink - io_uring_prep_symlink.restype = None - io_uring_prep_symlink.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - io_uring_prep_linkat = _libraries['FIXME_STUB'].io_uring_prep_linkat - io_uring_prep_linkat.restype = None - io_uring_prep_linkat.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_link = _libraries['FIXME_STUB'].io_uring_prep_link - io_uring_prep_link.restype = None - io_uring_prep_link.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring_cqe_flags = _libraries['FIXME_STUB'].io_uring_prep_msg_ring_cqe_flags - io_uring_prep_msg_ring_cqe_flags.restype = None - io_uring_prep_msg_ring_cqe_flags.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32, __u64, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring = _libraries['FIXME_STUB'].io_uring_prep_msg_ring - io_uring_prep_msg_ring.restype = None - io_uring_prep_msg_ring.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_uint32, __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring_fd = _libraries['FIXME_STUB'].io_uring_prep_msg_ring_fd - io_uring_prep_msg_ring_fd.restype = None - io_uring_prep_msg_ring_fd.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_msg_ring_fd_alloc = _libraries['FIXME_STUB'].io_uring_prep_msg_ring_fd_alloc - io_uring_prep_msg_ring_fd_alloc.restype = None - io_uring_prep_msg_ring_fd_alloc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, __u64, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_getxattr = _libraries['FIXME_STUB'].io_uring_prep_getxattr - io_uring_prep_getxattr.restype = None - io_uring_prep_getxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_setxattr = _libraries['FIXME_STUB'].io_uring_prep_setxattr - io_uring_prep_setxattr.restype = None - io_uring_prep_setxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_fgetxattr = _libraries['FIXME_STUB'].io_uring_prep_fgetxattr - io_uring_prep_fgetxattr.restype = None - io_uring_prep_fgetxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_fsetxattr = _libraries['FIXME_STUB'].io_uring_prep_fsetxattr - io_uring_prep_fsetxattr.restype = None - io_uring_prep_fsetxattr.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_socket = _libraries['FIXME_STUB'].io_uring_prep_socket - io_uring_prep_socket.restype = None - io_uring_prep_socket.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_socket_direct = _libraries['FIXME_STUB'].io_uring_prep_socket_direct - io_uring_prep_socket_direct.restype = None - io_uring_prep_socket_direct.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_socket_direct_alloc = _libraries['FIXME_STUB'].io_uring_prep_socket_direct_alloc - io_uring_prep_socket_direct_alloc.restype = None - io_uring_prep_socket_direct_alloc.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_prep_cmd_sock = _libraries['FIXME_STUB'].io_uring_prep_cmd_sock - io_uring_prep_cmd_sock.restype = None - io_uring_prep_cmd_sock.argtypes = [ctypes.POINTER(struct_io_uring_sqe), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_sq_ready = _libraries['FIXME_STUB'].io_uring_sq_ready - io_uring_sq_ready.restype = ctypes.c_uint32 - io_uring_sq_ready.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_sq_space_left = _libraries['FIXME_STUB'].io_uring_sq_space_left - io_uring_sq_space_left.restype = ctypes.c_uint32 - io_uring_sq_space_left.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_sqring_wait = _libraries['FIXME_STUB'].io_uring_sqring_wait - io_uring_sqring_wait.restype = ctypes.c_int32 - io_uring_sqring_wait.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_ready = _libraries['FIXME_STUB'].io_uring_cq_ready - io_uring_cq_ready.restype = ctypes.c_uint32 - io_uring_cq_ready.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_has_overflow = _libraries['FIXME_STUB'].io_uring_cq_has_overflow - io_uring_cq_has_overflow.restype = ctypes.c_bool - io_uring_cq_has_overflow.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_eventfd_enabled = _libraries['FIXME_STUB'].io_uring_cq_eventfd_enabled - io_uring_cq_eventfd_enabled.restype = ctypes.c_bool - io_uring_cq_eventfd_enabled.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -try: - io_uring_cq_eventfd_toggle = _libraries['FIXME_STUB'].io_uring_cq_eventfd_toggle - io_uring_cq_eventfd_toggle.restype = ctypes.c_int32 - io_uring_cq_eventfd_toggle.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.c_bool] -except AttributeError: - pass -try: - io_uring_wait_cqe_nr = _libraries['FIXME_STUB'].io_uring_wait_cqe_nr - io_uring_wait_cqe_nr.restype = ctypes.c_int32 - io_uring_wait_cqe_nr.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.c_uint32] -except AttributeError: - pass -try: - __io_uring_peek_cqe = _libraries['FIXME_STUB'].__io_uring_peek_cqe - __io_uring_peek_cqe.restype = ctypes.c_int32 - __io_uring_peek_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - io_uring_peek_cqe = _libraries['FIXME_STUB'].io_uring_peek_cqe - io_uring_peek_cqe.restype = ctypes.c_int32 - io_uring_peek_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe))] -except AttributeError: - pass -try: - io_uring_wait_cqe = _libraries['FIXME_STUB'].io_uring_wait_cqe - io_uring_wait_cqe.restype = ctypes.c_int32 - io_uring_wait_cqe.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(ctypes.POINTER(struct_io_uring_cqe))] -except AttributeError: - pass -try: - _io_uring_get_sqe = _libraries['FIXME_STUB']._io_uring_get_sqe - _io_uring_get_sqe.restype = ctypes.POINTER(struct_io_uring_sqe) - _io_uring_get_sqe.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass +__s32 = ctypes.c_int32 +class struct_io_uring_sqe_0(ctypes.Union): pass +__u64 = ctypes.c_uint64 +class struct_io_uring_sqe_0_0(Struct): pass __u32 = ctypes.c_uint32 -try: - io_uring_buf_ring_mask = _libraries['FIXME_STUB'].io_uring_buf_ring_mask - io_uring_buf_ring_mask.restype = ctypes.c_int32 - io_uring_buf_ring_mask.argtypes = [__u32] -except AttributeError: - pass -try: - io_uring_buf_ring_init = _libraries['FIXME_STUB'].io_uring_buf_ring_init - io_uring_buf_ring_init.restype = None - io_uring_buf_ring_init.argtypes = [ctypes.POINTER(struct_io_uring_buf_ring)] -except AttributeError: - pass -try: - io_uring_buf_ring_add = _libraries['FIXME_STUB'].io_uring_buf_ring_add - io_uring_buf_ring_add.restype = None - io_uring_buf_ring_add.argtypes = [ctypes.POINTER(struct_io_uring_buf_ring), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint16, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_buf_ring_advance = _libraries['FIXME_STUB'].io_uring_buf_ring_advance - io_uring_buf_ring_advance.restype = None - io_uring_buf_ring_advance.argtypes = [ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_int32] -except AttributeError: - pass -try: - __io_uring_buf_ring_cq_advance = _libraries['FIXME_STUB'].__io_uring_buf_ring_cq_advance - __io_uring_buf_ring_cq_advance.restype = None - __io_uring_buf_ring_cq_advance.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_buf_ring_cq_advance = _libraries['FIXME_STUB'].io_uring_buf_ring_cq_advance - io_uring_buf_ring_cq_advance.restype = None - io_uring_buf_ring_cq_advance.argtypes = [ctypes.POINTER(struct_io_uring), ctypes.POINTER(struct_io_uring_buf_ring), ctypes.c_int32] -except AttributeError: - pass -try: - io_uring_get_sqe = _libraries['FIXME_STUB'].io_uring_get_sqe - io_uring_get_sqe.restype = ctypes.POINTER(struct_io_uring_sqe) - io_uring_get_sqe.argtypes = [ctypes.POINTER(struct_io_uring)] -except AttributeError: - pass -ssize_t = ctypes.c_int64 -try: - io_uring_mlock_size = _libraries['FIXME_STUB'].io_uring_mlock_size - io_uring_mlock_size.restype = ssize_t - io_uring_mlock_size.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - io_uring_mlock_size_params = _libraries['FIXME_STUB'].io_uring_mlock_size_params - io_uring_mlock_size_params.restype = ssize_t - io_uring_mlock_size_params.argtypes = [ctypes.c_uint32, ctypes.POINTER(struct_io_uring_params)] -except AttributeError: - pass -try: - io_uring_major_version = _libraries['FIXME_STUB'].io_uring_major_version - io_uring_major_version.restype = ctypes.c_int32 - io_uring_major_version.argtypes = [] -except AttributeError: - pass -try: - io_uring_minor_version = _libraries['FIXME_STUB'].io_uring_minor_version - io_uring_minor_version.restype = ctypes.c_int32 - io_uring_minor_version.argtypes = [] -except AttributeError: - pass -try: - io_uring_check_version = _libraries['FIXME_STUB'].io_uring_check_version - io_uring_check_version.restype = ctypes.c_bool - io_uring_check_version.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -LINUX_IO_URING_H = True # macro -IORING_FILE_INDEX_ALLOC = (~0) # macro -IORING_SETUP_IOPOLL = (1<<0) # macro -IORING_SETUP_SQPOLL = (1<<1) # macro -IORING_SETUP_SQ_AFF = (1<<2) # macro -IORING_SETUP_CQSIZE = (1<<3) # macro -IORING_SETUP_CLAMP = (1<<4) # macro -IORING_SETUP_ATTACH_WQ = (1<<5) # macro -IORING_SETUP_R_DISABLED = (1<<6) # macro -IORING_SETUP_SUBMIT_ALL = (1<<7) # macro -IORING_SETUP_COOP_TASKRUN = (1<<8) # macro -IORING_SETUP_TASKRUN_FLAG = (1<<9) # macro -IORING_SETUP_SQE128 = (1<<10) # macro -IORING_SETUP_CQE32 = (1<<11) # macro -# def io_uring_cqe_shift(ring): # macro -# return (!!((ring)->flags&IORING_SETUP_CQE32)) -IORING_SETUP_SINGLE_ISSUER = (1<<12) # macro -IORING_SETUP_DEFER_TASKRUN = (1<<13) # macro -IORING_SETUP_NO_MMAP = (1<<14) # macro -IORING_SETUP_REGISTERED_FD_ONLY = (1<<15) # macro -IORING_SETUP_NO_SQARRAY = (1<<16) # macro -IORING_URING_CMD_FIXED = (1<<0) # macro -IORING_URING_CMD_MASK = (1<<0) # macro -IORING_FSYNC_DATASYNC = (1<<0) # macro -IORING_TIMEOUT_ABS = (1<<0) # macro -IORING_TIMEOUT_UPDATE = (1<<1) # macro -IORING_TIMEOUT_BOOTTIME = (1<<2) # macro -IORING_TIMEOUT_REALTIME = (1<<3) # macro -IORING_LINK_TIMEOUT_UPDATE = (1<<4) # macro -IORING_TIMEOUT_ETIME_SUCCESS = (1<<5) # macro -IORING_TIMEOUT_MULTISHOT = (1<<6) # macro -IORING_TIMEOUT_CLOCK_MASK = ((1<<2)|(1<<3)) # macro -IORING_TIMEOUT_UPDATE_MASK = ((1<<1)|(1<<4)) # macro -SPLICE_F_FD_IN_FIXED = (1<<31) # macro -IORING_POLL_ADD_MULTI = (1<<0) # macro -IORING_POLL_UPDATE_EVENTS = (1<<1) # macro -IORING_POLL_UPDATE_USER_DATA = (1<<2) # macro -IORING_POLL_ADD_LEVEL = (1<<3) # macro -IORING_ASYNC_CANCEL_ALL = (1<<0) # macro -IORING_ASYNC_CANCEL_FD = (1<<1) # macro -IORING_ASYNC_CANCEL_ANY = (1<<2) # macro -IORING_ASYNC_CANCEL_FD_FIXED = (1<<3) # macro -IORING_ASYNC_CANCEL_USERDATA = (1<<4) # macro -IORING_ASYNC_CANCEL_OP = (1<<5) # macro -IORING_RECVSEND_POLL_FIRST = (1<<0) # macro -IORING_RECV_MULTISHOT = (1<<1) # macro -IORING_RECVSEND_FIXED_BUF = (1<<2) # macro -IORING_SEND_ZC_REPORT_USAGE = (1<<3) # macro -IORING_NOTIF_USAGE_ZC_COPIED = (1<<31) # macro -IORING_ACCEPT_MULTISHOT = (1<<0) # macro -IORING_MSG_RING_CQE_SKIP = (1<<0) # macro -IORING_MSG_RING_FLAGS_PASS = (1<<1) # macro -IORING_FIXED_FD_NO_CLOEXEC = (1<<0) # macro -IORING_CQE_F_BUFFER = (1<<0) # macro -IORING_CQE_F_MORE = (1<<1) # macro -IORING_CQE_F_SOCK_NONEMPTY = (1<<2) # macro -IORING_CQE_F_NOTIF = (1<<3) # macro -IORING_OFF_SQ_RING = 0 # macro -IORING_OFF_CQ_RING = 0x8000000 # macro -IORING_OFF_SQES = 0x10000000 # macro -IORING_OFF_PBUF_RING = 0x80000000 # macro -IORING_OFF_PBUF_SHIFT = 16 # macro -IORING_OFF_MMAP_MASK = 0xf8000000 # macro -IORING_SQ_NEED_WAKEUP = (1<<0) # macro -IORING_SQ_CQ_OVERFLOW = (1<<1) # macro -IORING_SQ_TASKRUN = (1<<2) # macro -IORING_CQ_EVENTFD_DISABLED = (1<<0) # macro -IORING_ENTER_GETEVENTS = (1<<0) # macro -IORING_ENTER_SQ_WAKEUP = (1<<1) # macro -IORING_ENTER_SQ_WAIT = (1<<2) # macro -IORING_ENTER_EXT_ARG = (1<<3) # macro -IORING_ENTER_REGISTERED_RING = (1<<4) # macro -IORING_FEAT_SINGLE_MMAP = (1<<0) # macro -IORING_FEAT_NODROP = (1<<1) # macro -IORING_FEAT_SUBMIT_STABLE = (1<<2) # macro -IORING_FEAT_RW_CUR_POS = (1<<3) # macro -IORING_FEAT_CUR_PERSONALITY = (1<<4) # macro -IORING_FEAT_FAST_POLL = (1<<5) # macro -IORING_FEAT_POLL_32BITS = (1<<6) # macro -IORING_FEAT_SQPOLL_NONFIXED = (1<<7) # macro -IORING_FEAT_EXT_ARG = (1<<8) # macro -IORING_FEAT_NATIVE_WORKERS = (1<<9) # macro -IORING_FEAT_RSRC_TAGS = (1<<10) # macro -IORING_FEAT_CQE_SKIP = (1<<11) # macro -IORING_FEAT_LINKED_FILE = (1<<12) # macro -IORING_FEAT_REG_REG_RING = (1<<13) # macro -IORING_RSRC_REGISTER_SPARSE = (1<<0) # macro -IORING_REGISTER_FILES_SKIP = (-2) # macro -IO_URING_OP_SUPPORTED = (1<<0) # macro +struct_io_uring_sqe_0_0._fields_ = [ + ('cmd_op', ctypes.c_uint32), + ('__pad1', ctypes.c_uint32), +] +struct_io_uring_sqe_0._anonymous_ = ['_0'] +struct_io_uring_sqe_0._fields_ = [ + ('off', ctypes.c_uint64), + ('addr2', ctypes.c_uint64), + ('_0', struct_io_uring_sqe_0_0), +] +class struct_io_uring_sqe_1(ctypes.Union): pass +struct_io_uring_sqe_1._fields_ = [ + ('addr', ctypes.c_uint64), + ('splice_off_in', ctypes.c_uint64), +] +class struct_io_uring_sqe_2(ctypes.Union): pass +__kernel_rwf_t = ctypes.c_int32 +struct_io_uring_sqe_2._fields_ = [ + ('rw_flags', ctypes.c_int32), + ('fsync_flags', ctypes.c_uint32), + ('poll_events', ctypes.c_uint16), + ('poll32_events', ctypes.c_uint32), + ('sync_range_flags', ctypes.c_uint32), + ('msg_flags', ctypes.c_uint32), + ('timeout_flags', ctypes.c_uint32), + ('accept_flags', ctypes.c_uint32), + ('cancel_flags', ctypes.c_uint32), + ('open_flags', ctypes.c_uint32), + ('statx_flags', ctypes.c_uint32), + ('fadvise_advice', ctypes.c_uint32), + ('splice_flags', ctypes.c_uint32), + ('rename_flags', ctypes.c_uint32), + ('unlink_flags', ctypes.c_uint32), + ('hardlink_flags', ctypes.c_uint32), + ('xattr_flags', ctypes.c_uint32), + ('msg_ring_flags', ctypes.c_uint32), + ('uring_cmd_flags', ctypes.c_uint32), +] +class struct_io_uring_sqe_3(ctypes.Union): pass +struct_io_uring_sqe_3._packed_ = True +struct_io_uring_sqe_3._fields_ = [ + ('buf_index', ctypes.c_uint16), + ('buf_group', ctypes.c_uint16), +] +class struct_io_uring_sqe_4(ctypes.Union): pass +class struct_io_uring_sqe_4_0(Struct): pass +struct_io_uring_sqe_4_0._fields_ = [ + ('addr_len', ctypes.c_uint16), + ('__pad3', (ctypes.c_uint16 * 1)), +] +struct_io_uring_sqe_4._anonymous_ = ['_0'] +struct_io_uring_sqe_4._fields_ = [ + ('splice_fd_in', ctypes.c_int32), + ('file_index', ctypes.c_uint32), + ('_0', struct_io_uring_sqe_4_0), +] +class struct_io_uring_sqe_5(ctypes.Union): pass +class struct_io_uring_sqe_5_0(Struct): pass +struct_io_uring_sqe_5_0._fields_ = [ + ('addr3', ctypes.c_uint64), + ('__pad2', (ctypes.c_uint64 * 1)), +] +struct_io_uring_sqe_5._anonymous_ = ['_0'] +struct_io_uring_sqe_5._fields_ = [ + ('_0', struct_io_uring_sqe_5_0), + ('cmd', (ctypes.c_ubyte * 0)), +] +struct_io_uring_sqe._anonymous_ = ['_0', '_1', '_2', '_3', '_4', '_5'] +struct_io_uring_sqe._fields_ = [ + ('opcode', ctypes.c_ubyte), + ('flags', ctypes.c_ubyte), + ('ioprio', ctypes.c_uint16), + ('fd', ctypes.c_int32), + ('_0', struct_io_uring_sqe_0), + ('_1', struct_io_uring_sqe_1), + ('len', ctypes.c_uint32), + ('_2', struct_io_uring_sqe_2), + ('user_data', ctypes.c_uint64), + ('_3', struct_io_uring_sqe_3), + ('personality', ctypes.c_uint16), + ('_4', struct_io_uring_sqe_4), + ('_5', struct_io_uring_sqe_5), +] +size_t = ctypes.c_uint64 +struct_io_uring_sq._fields_ = [ + ('khead', ctypes.POINTER(ctypes.c_uint32)), + ('ktail', ctypes.POINTER(ctypes.c_uint32)), + ('kring_mask', ctypes.POINTER(ctypes.c_uint32)), + ('kring_entries', ctypes.POINTER(ctypes.c_uint32)), + ('kflags', ctypes.POINTER(ctypes.c_uint32)), + ('kdropped', ctypes.POINTER(ctypes.c_uint32)), + ('array', ctypes.POINTER(ctypes.c_uint32)), + ('sqes', ctypes.POINTER(struct_io_uring_sqe)), + ('sqe_head', ctypes.c_uint32), + ('sqe_tail', ctypes.c_uint32), + ('ring_sz', size_t), + ('ring_ptr', ctypes.c_void_p), + ('ring_mask', ctypes.c_uint32), + ('ring_entries', ctypes.c_uint32), + ('pad', (ctypes.c_uint32 * 2)), +] +class struct_io_uring_cq(Struct): pass +class struct_io_uring_cqe(Struct): pass +struct_io_uring_cqe._fields_ = [ + ('user_data', ctypes.c_uint64), + ('res', ctypes.c_int32), + ('flags', ctypes.c_uint32), + ('big_cqe', (ctypes.c_uint64 * 0)), +] +struct_io_uring_cq._fields_ = [ + ('khead', ctypes.POINTER(ctypes.c_uint32)), + ('ktail', ctypes.POINTER(ctypes.c_uint32)), + ('kring_mask', ctypes.POINTER(ctypes.c_uint32)), + ('kring_entries', ctypes.POINTER(ctypes.c_uint32)), + ('kflags', ctypes.POINTER(ctypes.c_uint32)), + ('koverflow', ctypes.POINTER(ctypes.c_uint32)), + ('cqes', ctypes.POINTER(struct_io_uring_cqe)), + ('ring_sz', size_t), + ('ring_ptr', ctypes.c_void_p), + ('ring_mask', ctypes.c_uint32), + ('ring_entries', ctypes.c_uint32), + ('pad', (ctypes.c_uint32 * 2)), +] +class struct_io_uring(Struct): pass +struct_io_uring._fields_ = [ + ('sq', struct_io_uring_sq), + ('cq', struct_io_uring_cq), + ('flags', ctypes.c_uint32), + ('ring_fd', ctypes.c_int32), + ('features', ctypes.c_uint32), + ('enter_ring_fd', ctypes.c_int32), + ('int_flags', ctypes.c_ubyte), + ('pad', (ctypes.c_ubyte * 3)), + ('pad2', ctypes.c_uint32), +] +class struct_statx(Struct): pass +class struct_statx_timestamp(Struct): pass +__s64 = ctypes.c_int64 +struct_statx_timestamp._fields_ = [ + ('tv_sec', ctypes.c_int64), + ('tv_nsec', ctypes.c_uint32), + ('__reserved', ctypes.c_int32), +] +struct_statx._fields_ = [ + ('stx_mask', ctypes.c_uint32), + ('stx_blksize', ctypes.c_uint32), + ('stx_attributes', ctypes.c_uint64), + ('stx_nlink', ctypes.c_uint32), + ('stx_uid', ctypes.c_uint32), + ('stx_gid', ctypes.c_uint32), + ('stx_mode', ctypes.c_uint16), + ('__spare0', (ctypes.c_uint16 * 1)), + ('stx_ino', ctypes.c_uint64), + ('stx_size', ctypes.c_uint64), + ('stx_blocks', ctypes.c_uint64), + ('stx_attributes_mask', ctypes.c_uint64), + ('stx_atime', struct_statx_timestamp), + ('stx_btime', struct_statx_timestamp), + ('stx_ctime', struct_statx_timestamp), + ('stx_mtime', struct_statx_timestamp), + ('stx_rdev_major', ctypes.c_uint32), + ('stx_rdev_minor', ctypes.c_uint32), + ('stx_dev_major', ctypes.c_uint32), + ('stx_dev_minor', ctypes.c_uint32), + ('stx_mnt_id', ctypes.c_uint64), + ('stx_dio_mem_align', ctypes.c_uint32), + ('stx_dio_offset_align', ctypes.c_uint32), + ('__spare3', (ctypes.c_uint64 * 12)), +] +class struct_epoll_event(Struct): pass +class _anonunion0(ctypes.Union): pass +class _anonunion0_0(Struct): pass +_anonunion0_0._fields_ = [ + ('cmd_op', ctypes.c_uint32), + ('__pad1', ctypes.c_uint32), +] +_anonunion0._anonymous_ = ['_0'] +_anonunion0._fields_ = [ + ('off', ctypes.c_uint64), + ('addr2', ctypes.c_uint64), + ('_0', _anonunion0_0), +] +class _anonunion1(ctypes.Union): pass +class _anonunion1_0(Struct): pass +_anonunion1_0._fields_ = [ + ('level', ctypes.c_uint32), + ('optname', ctypes.c_uint32), +] +_anonunion1._anonymous_ = ['_0'] +_anonunion1._fields_ = [ + ('addr', ctypes.c_uint64), + ('splice_off_in', ctypes.c_uint64), + ('_0', _anonunion1_0), +] +class _anonunion2(ctypes.Union): pass +_anonunion2._fields_ = [ + ('rw_flags', ctypes.c_int32), + ('fsync_flags', ctypes.c_uint32), + ('poll_events', ctypes.c_uint16), + ('poll32_events', ctypes.c_uint32), + ('sync_range_flags', ctypes.c_uint32), + ('msg_flags', ctypes.c_uint32), + ('timeout_flags', ctypes.c_uint32), + ('accept_flags', ctypes.c_uint32), + ('cancel_flags', ctypes.c_uint32), + ('open_flags', ctypes.c_uint32), + ('statx_flags', ctypes.c_uint32), + ('fadvise_advice', ctypes.c_uint32), + ('splice_flags', ctypes.c_uint32), + ('rename_flags', ctypes.c_uint32), + ('unlink_flags', ctypes.c_uint32), + ('hardlink_flags', ctypes.c_uint32), + ('xattr_flags', ctypes.c_uint32), + ('msg_ring_flags', ctypes.c_uint32), + ('uring_cmd_flags', ctypes.c_uint32), + ('waitid_flags', ctypes.c_uint32), + ('futex_flags', ctypes.c_uint32), + ('install_fd_flags', ctypes.c_uint32), +] +class _anonunion3(ctypes.Union): pass +_anonunion3._packed_ = True +_anonunion3._fields_ = [ + ('buf_index', ctypes.c_uint16), + ('buf_group', ctypes.c_uint16), +] +class _anonunion4(ctypes.Union): pass +class _anonunion4_0(Struct): pass +_anonunion4_0._fields_ = [ + ('addr_len', ctypes.c_uint16), + ('__pad3', (ctypes.c_uint16 * 1)), +] +_anonunion4._anonymous_ = ['_0'] +_anonunion4._fields_ = [ + ('splice_fd_in', ctypes.c_int32), + ('file_index', ctypes.c_uint32), + ('optlen', ctypes.c_uint32), + ('_0', _anonunion4_0), +] +class _anonunion5(ctypes.Union): pass +class _anonunion5_0(Struct): pass +_anonunion5_0._fields_ = [ + ('addr3', ctypes.c_uint64), + ('__pad2', (ctypes.c_uint64 * 1)), +] +_anonunion5._anonymous_ = ['_0'] +_anonunion5._fields_ = [ + ('_0', _anonunion5_0), + ('optval', ctypes.c_uint64), + ('cmd', (ctypes.c_ubyte * 0)), +] +_anonenum6 = CEnum(ctypes.c_uint32) +IOSQE_FIXED_FILE_BIT = _anonenum6.define('IOSQE_FIXED_FILE_BIT', 0) +IOSQE_IO_DRAIN_BIT = _anonenum6.define('IOSQE_IO_DRAIN_BIT', 1) +IOSQE_IO_LINK_BIT = _anonenum6.define('IOSQE_IO_LINK_BIT', 2) +IOSQE_IO_HARDLINK_BIT = _anonenum6.define('IOSQE_IO_HARDLINK_BIT', 3) +IOSQE_ASYNC_BIT = _anonenum6.define('IOSQE_ASYNC_BIT', 4) +IOSQE_BUFFER_SELECT_BIT = _anonenum6.define('IOSQE_BUFFER_SELECT_BIT', 5) +IOSQE_CQE_SKIP_SUCCESS_BIT = _anonenum6.define('IOSQE_CQE_SKIP_SUCCESS_BIT', 6) -# values for enumeration 'c__Ea_IOSQE_FIXED_FILE_BIT' -c__Ea_IOSQE_FIXED_FILE_BIT__enumvalues = { - 0: 'IOSQE_FIXED_FILE_BIT', - 1: 'IOSQE_IO_DRAIN_BIT', - 2: 'IOSQE_IO_LINK_BIT', - 3: 'IOSQE_IO_HARDLINK_BIT', - 4: 'IOSQE_ASYNC_BIT', - 5: 'IOSQE_BUFFER_SELECT_BIT', - 6: 'IOSQE_CQE_SKIP_SUCCESS_BIT', -} -IOSQE_FIXED_FILE_BIT = 0 -IOSQE_IO_DRAIN_BIT = 1 -IOSQE_IO_LINK_BIT = 2 -IOSQE_IO_HARDLINK_BIT = 3 -IOSQE_ASYNC_BIT = 4 -IOSQE_BUFFER_SELECT_BIT = 5 -IOSQE_CQE_SKIP_SUCCESS_BIT = 6 -c__Ea_IOSQE_FIXED_FILE_BIT = ctypes.c_uint32 # enum -IOSQE_FIXED_FILE = (1< IO_URING_VERSION_MAJOR or (major == IO_URING_VERSION_MAJOR and minor >= IO_URING_VERSION_MINOR)) +IORING_FILE_INDEX_ALLOC = (~0) +IOSQE_FIXED_FILE = (1 << IOSQE_FIXED_FILE_BIT) +IOSQE_IO_DRAIN = (1 << IOSQE_IO_DRAIN_BIT) +IOSQE_IO_LINK = (1 << IOSQE_IO_LINK_BIT) +IOSQE_IO_HARDLINK = (1 << IOSQE_IO_HARDLINK_BIT) +IOSQE_ASYNC = (1 << IOSQE_ASYNC_BIT) +IOSQE_BUFFER_SELECT = (1 << IOSQE_BUFFER_SELECT_BIT) +IOSQE_CQE_SKIP_SUCCESS = (1 << IOSQE_CQE_SKIP_SUCCESS_BIT) +IORING_SETUP_IOPOLL = (1 << 0) +IORING_SETUP_SQPOLL = (1 << 1) +IORING_SETUP_SQ_AFF = (1 << 2) +IORING_SETUP_CQSIZE = (1 << 3) +IORING_SETUP_CLAMP = (1 << 4) +IORING_SETUP_ATTACH_WQ = (1 << 5) +IORING_SETUP_R_DISABLED = (1 << 6) +IORING_SETUP_SUBMIT_ALL = (1 << 7) +IORING_SETUP_COOP_TASKRUN = (1 << 8) +IORING_SETUP_TASKRUN_FLAG = (1 << 9) +IORING_SETUP_SQE128 = (1 << 10) +IORING_SETUP_CQE32 = (1 << 11) +IORING_SETUP_SINGLE_ISSUER = (1 << 12) +IORING_SETUP_DEFER_TASKRUN = (1 << 13) +IORING_SETUP_NO_MMAP = (1 << 14) +IORING_SETUP_REGISTERED_FD_ONLY = (1 << 15) +IORING_SETUP_NO_SQARRAY = (1 << 16) +IORING_URING_CMD_FIXED = (1 << 0) +IORING_URING_CMD_MASK = IORING_URING_CMD_FIXED +IORING_FSYNC_DATASYNC = (1 << 0) +IORING_TIMEOUT_ABS = (1 << 0) +IORING_TIMEOUT_UPDATE = (1 << 1) +IORING_TIMEOUT_BOOTTIME = (1 << 2) +IORING_TIMEOUT_REALTIME = (1 << 3) +IORING_LINK_TIMEOUT_UPDATE = (1 << 4) +IORING_TIMEOUT_ETIME_SUCCESS = (1 << 5) +IORING_TIMEOUT_MULTISHOT = (1 << 6) +IORING_TIMEOUT_CLOCK_MASK = (IORING_TIMEOUT_BOOTTIME | IORING_TIMEOUT_REALTIME) +IORING_TIMEOUT_UPDATE_MASK = (IORING_TIMEOUT_UPDATE | IORING_LINK_TIMEOUT_UPDATE) +SPLICE_F_FD_IN_FIXED = (1 << 31) +IORING_POLL_ADD_MULTI = (1 << 0) +IORING_POLL_UPDATE_EVENTS = (1 << 1) +IORING_POLL_UPDATE_USER_DATA = (1 << 2) +IORING_POLL_ADD_LEVEL = (1 << 3) +IORING_ASYNC_CANCEL_ALL = (1 << 0) +IORING_ASYNC_CANCEL_FD = (1 << 1) +IORING_ASYNC_CANCEL_ANY = (1 << 2) +IORING_ASYNC_CANCEL_FD_FIXED = (1 << 3) +IORING_ASYNC_CANCEL_USERDATA = (1 << 4) +IORING_ASYNC_CANCEL_OP = (1 << 5) +IORING_RECVSEND_POLL_FIRST = (1 << 0) +IORING_RECV_MULTISHOT = (1 << 1) +IORING_RECVSEND_FIXED_BUF = (1 << 2) +IORING_SEND_ZC_REPORT_USAGE = (1 << 3) +IORING_NOTIF_USAGE_ZC_COPIED = (1 << 31) +IORING_ACCEPT_MULTISHOT = (1 << 0) +IORING_MSG_RING_CQE_SKIP = (1 << 0) +IORING_MSG_RING_FLAGS_PASS = (1 << 1) +IORING_FIXED_FD_NO_CLOEXEC = (1 << 0) +IORING_CQE_F_BUFFER = (1 << 0) +IORING_CQE_F_MORE = (1 << 1) +IORING_CQE_F_SOCK_NONEMPTY = (1 << 2) +IORING_CQE_F_NOTIF = (1 << 3) +IORING_OFF_SQ_RING = 0 +IORING_OFF_CQ_RING = 0x8000000 +IORING_OFF_SQES = 0x10000000 +IORING_OFF_PBUF_RING = 0x80000000 +IORING_OFF_PBUF_SHIFT = 16 +IORING_OFF_MMAP_MASK = 0xf8000000 +IORING_SQ_NEED_WAKEUP = (1 << 0) +IORING_SQ_CQ_OVERFLOW = (1 << 1) +IORING_SQ_TASKRUN = (1 << 2) +IORING_CQ_EVENTFD_DISABLED = (1 << 0) +IORING_ENTER_GETEVENTS = (1 << 0) +IORING_ENTER_SQ_WAKEUP = (1 << 1) +IORING_ENTER_SQ_WAIT = (1 << 2) +IORING_ENTER_EXT_ARG = (1 << 3) +IORING_ENTER_REGISTERED_RING = (1 << 4) +IORING_FEAT_SINGLE_MMAP = (1 << 0) +IORING_FEAT_NODROP = (1 << 1) +IORING_FEAT_SUBMIT_STABLE = (1 << 2) +IORING_FEAT_RW_CUR_POS = (1 << 3) +IORING_FEAT_CUR_PERSONALITY = (1 << 4) +IORING_FEAT_FAST_POLL = (1 << 5) +IORING_FEAT_POLL_32BITS = (1 << 6) +IORING_FEAT_SQPOLL_NONFIXED = (1 << 7) +IORING_FEAT_EXT_ARG = (1 << 8) +IORING_FEAT_NATIVE_WORKERS = (1 << 9) +IORING_FEAT_RSRC_TAGS = (1 << 10) +IORING_FEAT_CQE_SKIP = (1 << 11) +IORING_FEAT_LINKED_FILE = (1 << 12) +IORING_FEAT_REG_REG_RING = (1 << 13) +IORING_RSRC_REGISTER_SPARSE = (1 << 0) +IORING_REGISTER_FILES_SKIP = (-2) +IO_URING_OP_SUPPORTED = (1 << 0) +__SC_3264 = lambda _nr,_32,_64: __SYSCALL(_nr, _64) +__SC_COMP = lambda _nr,_sys,_comp: __SYSCALL(_nr, _sys) +__SC_COMP_3264 = lambda _nr,_32,_64,_comp: __SC_3264(_nr, _32, _64) +NR_io_setup = 0 +NR_io_destroy = 1 +NR_io_submit = 2 +NR_io_cancel = 3 +NR_io_getevents = 4 +NR_setxattr = 5 +NR_lsetxattr = 6 +NR_fsetxattr = 7 +NR_getxattr = 8 +NR_lgetxattr = 9 +NR_fgetxattr = 10 +NR_listxattr = 11 +NR_llistxattr = 12 +NR_flistxattr = 13 +NR_removexattr = 14 +NR_lremovexattr = 15 +NR_fremovexattr = 16 +NR_getcwd = 17 +NR_lookup_dcookie = 18 +NR_eventfd2 = 19 +NR_epoll_create1 = 20 +NR_epoll_ctl = 21 +NR_epoll_pwait = 22 +NR_dup = 23 +NR_dup3 = 24 +NR3264_fcntl = 25 +NR_inotify_init1 = 26 +NR_inotify_add_watch = 27 +NR_inotify_rm_watch = 28 +NR_ioctl = 29 +NR_ioprio_set = 30 +NR_ioprio_get = 31 +NR_flock = 32 +NR_mknodat = 33 +NR_mkdirat = 34 +NR_unlinkat = 35 +NR_symlinkat = 36 +NR_linkat = 37 +NR_umount2 = 39 +NR_mount = 40 +NR_pivot_root = 41 +NR_nfsservctl = 42 +NR3264_statfs = 43 +NR3264_fstatfs = 44 +NR3264_truncate = 45 +NR3264_ftruncate = 46 +NR_fallocate = 47 +NR_faccessat = 48 +NR_chdir = 49 +NR_fchdir = 50 +NR_chroot = 51 +NR_fchmod = 52 +NR_fchmodat = 53 +NR_fchownat = 54 +NR_fchown = 55 +NR_openat = 56 +NR_close = 57 +NR_vhangup = 58 +NR_pipe2 = 59 +NR_quotactl = 60 +NR_getdents64 = 61 +NR3264_lseek = 62 +NR_read = 63 +NR_write = 64 +NR_readv = 65 +NR_writev = 66 +NR_pread64 = 67 +NR_pwrite64 = 68 +NR_preadv = 69 +NR_pwritev = 70 +NR3264_sendfile = 71 +NR_pselect6 = 72 +NR_ppoll = 73 +NR_signalfd4 = 74 +NR_vmsplice = 75 +NR_splice = 76 +NR_tee = 77 +NR_readlinkat = 78 +NR_sync = 81 +NR_fsync = 82 +NR_fdatasync = 83 +NR_sync_file_range = 84 +NR_timerfd_create = 85 +NR_timerfd_settime = 86 +NR_timerfd_gettime = 87 +NR_utimensat = 88 +NR_acct = 89 +NR_capget = 90 +NR_capset = 91 +NR_personality = 92 +NR_exit = 93 +NR_exit_group = 94 +NR_waitid = 95 +NR_set_tid_address = 96 +NR_unshare = 97 +NR_futex = 98 +NR_set_robust_list = 99 +NR_get_robust_list = 100 +NR_nanosleep = 101 +NR_getitimer = 102 +NR_setitimer = 103 +NR_kexec_load = 104 +NR_init_module = 105 +NR_delete_module = 106 +NR_timer_create = 107 +NR_timer_gettime = 108 +NR_timer_getoverrun = 109 +NR_timer_settime = 110 +NR_timer_delete = 111 +NR_clock_settime = 112 +NR_clock_gettime = 113 +NR_clock_getres = 114 +NR_clock_nanosleep = 115 +NR_syslog = 116 +NR_ptrace = 117 +NR_sched_setparam = 118 +NR_sched_setscheduler = 119 +NR_sched_getscheduler = 120 +NR_sched_getparam = 121 +NR_sched_setaffinity = 122 +NR_sched_getaffinity = 123 +NR_sched_yield = 124 +NR_sched_get_priority_max = 125 +NR_sched_get_priority_min = 126 +NR_sched_rr_get_interval = 127 +NR_restart_syscall = 128 +NR_kill = 129 +NR_tkill = 130 +NR_tgkill = 131 +NR_sigaltstack = 132 +NR_rt_sigsuspend = 133 +NR_rt_sigaction = 134 +NR_rt_sigprocmask = 135 +NR_rt_sigpending = 136 +NR_rt_sigtimedwait = 137 +NR_rt_sigqueueinfo = 138 +NR_rt_sigreturn = 139 +NR_setpriority = 140 +NR_getpriority = 141 +NR_reboot = 142 +NR_setregid = 143 +NR_setgid = 144 +NR_setreuid = 145 +NR_setuid = 146 +NR_setresuid = 147 +NR_getresuid = 148 +NR_setresgid = 149 +NR_getresgid = 150 +NR_setfsuid = 151 +NR_setfsgid = 152 +NR_times = 153 +NR_setpgid = 154 +NR_getpgid = 155 +NR_getsid = 156 +NR_setsid = 157 +NR_getgroups = 158 +NR_setgroups = 159 +NR_uname = 160 +NR_sethostname = 161 +NR_setdomainname = 162 +NR_getrusage = 165 +NR_umask = 166 +NR_prctl = 167 +NR_getcpu = 168 +NR_gettimeofday = 169 +NR_settimeofday = 170 +NR_adjtimex = 171 +NR_getpid = 172 +NR_getppid = 173 +NR_getuid = 174 +NR_geteuid = 175 +NR_getgid = 176 +NR_getegid = 177 +NR_gettid = 178 +NR_sysinfo = 179 +NR_mq_open = 180 +NR_mq_unlink = 181 +NR_mq_timedsend = 182 +NR_mq_timedreceive = 183 +NR_mq_notify = 184 +NR_mq_getsetattr = 185 +NR_msgget = 186 +NR_msgctl = 187 +NR_msgrcv = 188 +NR_msgsnd = 189 +NR_semget = 190 +NR_semctl = 191 +NR_semtimedop = 192 +NR_semop = 193 +NR_shmget = 194 +NR_shmctl = 195 +NR_shmat = 196 +NR_shmdt = 197 +NR_socket = 198 +NR_socketpair = 199 +NR_bind = 200 +NR_listen = 201 +NR_accept = 202 +NR_connect = 203 +NR_getsockname = 204 +NR_getpeername = 205 +NR_sendto = 206 +NR_recvfrom = 207 +NR_setsockopt = 208 +NR_getsockopt = 209 +NR_shutdown = 210 +NR_sendmsg = 211 +NR_recvmsg = 212 +NR_readahead = 213 +NR_brk = 214 +NR_munmap = 215 +NR_mremap = 216 +NR_add_key = 217 +NR_request_key = 218 +NR_keyctl = 219 +NR_clone = 220 +NR_execve = 221 +NR3264_mmap = 222 +NR3264_fadvise64 = 223 +NR_swapon = 224 +NR_swapoff = 225 +NR_mprotect = 226 +NR_msync = 227 +NR_mlock = 228 +NR_munlock = 229 +NR_mlockall = 230 +NR_munlockall = 231 +NR_mincore = 232 +NR_madvise = 233 +NR_remap_file_pages = 234 +NR_mbind = 235 +NR_get_mempolicy = 236 +NR_set_mempolicy = 237 +NR_migrate_pages = 238 +NR_move_pages = 239 +NR_rt_tgsigqueueinfo = 240 +NR_perf_event_open = 241 +NR_accept4 = 242 +NR_recvmmsg = 243 +NR_arch_specific_syscall = 244 +NR_wait4 = 260 +NR_prlimit64 = 261 +NR_fanotify_init = 262 +NR_fanotify_mark = 263 +NR_name_to_handle_at = 264 +NR_open_by_handle_at = 265 +NR_clock_adjtime = 266 +NR_syncfs = 267 +NR_setns = 268 +NR_sendmmsg = 269 +NR_process_vm_readv = 270 +NR_process_vm_writev = 271 +NR_kcmp = 272 +NR_finit_module = 273 +NR_sched_setattr = 274 +NR_sched_getattr = 275 +NR_renameat2 = 276 +NR_seccomp = 277 +NR_getrandom = 278 +NR_memfd_create = 279 +NR_bpf = 280 +NR_execveat = 281 +NR_userfaultfd = 282 +NR_membarrier = 283 +NR_mlock2 = 284 +NR_copy_file_range = 285 +NR_preadv2 = 286 +NR_pwritev2 = 287 +NR_pkey_mprotect = 288 +NR_pkey_alloc = 289 +NR_pkey_free = 290 +NR_statx = 291 +NR_io_pgetevents = 292 +NR_rseq = 293 +NR_kexec_file_load = 294 +NR_pidfd_send_signal = 424 +NR_io_uring_setup = 425 +NR_io_uring_enter = 426 +NR_io_uring_register = 427 +NR_open_tree = 428 +NR_move_mount = 429 +NR_fsopen = 430 +NR_fsconfig = 431 +NR_fsmount = 432 +NR_fspick = 433 +NR_pidfd_open = 434 +NR_close_range = 436 +NR_openat2 = 437 +NR_pidfd_getfd = 438 +NR_faccessat2 = 439 +NR_process_madvise = 440 +NR_epoll_pwait2 = 441 +NR_mount_setattr = 442 +NR_quotactl_fd = 443 +NR_landlock_create_ruleset = 444 +NR_landlock_add_rule = 445 +NR_landlock_restrict_self = 446 +NR_process_mrelease = 448 +NR_futex_waitv = 449 +NR_set_mempolicy_home_node = 450 +NR_cachestat = 451 +NR_fchmodat2 = 452 +NR_map_shadow_stack = 453 +NR_futex_wake = 454 +NR_futex_wait = 455 +NR_futex_requeue = 456 +NR_statmount = 457 +NR_listmount = 458 +NR_lsm_get_self_attr = 459 +NR_lsm_set_self_attr = 460 +NR_lsm_list_modules = 461 +NR_syscalls = 462 +NR_fcntl = NR3264_fcntl +NR_statfs = NR3264_statfs +NR_fstatfs = NR3264_fstatfs +NR_truncate = NR3264_truncate +NR_ftruncate = NR3264_ftruncate +NR_lseek = NR3264_lseek +NR_sendfile = NR3264_sendfile +NR_mmap = NR3264_mmap +NR_fadvise64 = NR3264_fadvise64 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/kfd.py b/tinygrad/runtime/autogen/kfd.py index 0720e9e579..0dc21a2dd6 100644 --- a/tinygrad/runtime/autogen/kfd.py +++ b/tinygrad/runtime/autogen/kfd.py @@ -1,1550 +1,779 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - - -import functools -from tinygrad.runtime.support.hcq import FileIOInterface - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:FileIOInterface, **kwargs): - ret = __fd.ioctl((__idir<<30) | (ctypes.sizeof(made := __user_struct(**kwargs))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl, 0, ord(base) if isinstance(base, str) else base, nr, None) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -KFD_IOCTL_H_INCLUDED = True # macro -KFD_IOCTL_MAJOR_VERSION = 1 # macro -KFD_IOCTL_MINOR_VERSION = 14 # macro -KFD_IOC_QUEUE_TYPE_COMPUTE = 0x0 # macro -KFD_IOC_QUEUE_TYPE_SDMA = 0x1 # macro -KFD_IOC_QUEUE_TYPE_COMPUTE_AQL = 0x2 # macro -KFD_IOC_QUEUE_TYPE_SDMA_XGMI = 0x3 # macro -KFD_MAX_QUEUE_PERCENTAGE = 100 # macro -KFD_MAX_QUEUE_PRIORITY = 15 # macro -KFD_IOC_CACHE_POLICY_COHERENT = 0 # macro -KFD_IOC_CACHE_POLICY_NONCOHERENT = 1 # macro -NUM_OF_SUPPORTED_GPUS = 7 # macro -MAX_ALLOWED_NUM_POINTS = 100 # macro -MAX_ALLOWED_AW_BUFF_SIZE = 4096 # macro -MAX_ALLOWED_WAC_BUFF_SIZE = 128 # macro -KFD_INVALID_FD = 0xffffffff # macro -KFD_IOC_EVENT_SIGNAL = 0 # macro -KFD_IOC_EVENT_NODECHANGE = 1 # macro -KFD_IOC_EVENT_DEVICESTATECHANGE = 2 # macro -KFD_IOC_EVENT_HW_EXCEPTION = 3 # macro -KFD_IOC_EVENT_SYSTEM_EVENT = 4 # macro -KFD_IOC_EVENT_DEBUG_EVENT = 5 # macro -KFD_IOC_EVENT_PROFILE_EVENT = 6 # macro -KFD_IOC_EVENT_QUEUE_EVENT = 7 # macro -KFD_IOC_EVENT_MEMORY = 8 # macro -KFD_IOC_WAIT_RESULT_COMPLETE = 0 # macro -KFD_IOC_WAIT_RESULT_TIMEOUT = 1 # macro -KFD_IOC_WAIT_RESULT_FAIL = 2 # macro -KFD_SIGNAL_EVENT_LIMIT = 4096 # macro -KFD_HW_EXCEPTION_WHOLE_GPU_RESET = 0 # macro -KFD_HW_EXCEPTION_PER_ENGINE_RESET = 1 # macro -KFD_HW_EXCEPTION_GPU_HANG = 0 # macro -KFD_HW_EXCEPTION_ECC = 1 # macro -KFD_MEM_ERR_NO_RAS = 0 # macro -KFD_MEM_ERR_SRAM_ECC = 1 # macro -KFD_MEM_ERR_POISON_CONSUMED = 2 # macro -KFD_MEM_ERR_GPU_HANG = 3 # macro -KFD_IOC_ALLOC_MEM_FLAGS_VRAM = (1<<0) # macro -KFD_IOC_ALLOC_MEM_FLAGS_GTT = (1<<1) # macro -KFD_IOC_ALLOC_MEM_FLAGS_USERPTR = (1<<2) # macro -KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL = (1<<3) # macro -KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP = (1<<4) # macro -KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE = (1<<31) # macro -KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE = (1<<30) # macro -KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC = (1<<29) # macro -KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE = (1<<28) # macro -KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM = (1<<27) # macro -KFD_IOC_ALLOC_MEM_FLAGS_COHERENT = (1<<26) # macro -KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED = (1<<25) # macro -KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT = (1<<24) # macro -def KFD_SMI_EVENT_MASK_FROM_INDEX(i): # macro - return (1<<((i)-1)) -KFD_SMI_EVENT_MSG_SIZE = 96 # macro -KFD_IOCTL_SVM_FLAG_HOST_ACCESS = 0x00000001 # macro -KFD_IOCTL_SVM_FLAG_COHERENT = 0x00000002 # macro -KFD_IOCTL_SVM_FLAG_HIVE_LOCAL = 0x00000004 # macro -KFD_IOCTL_SVM_FLAG_GPU_RO = 0x00000008 # macro -KFD_IOCTL_SVM_FLAG_GPU_EXEC = 0x00000010 # macro -KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY = 0x00000020 # macro -KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED = 0x00000040 # macro -KFD_IOCTL_SVM_FLAG_EXT_COHERENT = 0x00000080 # macro -def KFD_EC_MASK(ecode): # macro - return (1<<(ecode-1)) -KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK = 1 # macro -KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK = 2 # macro -KFD_DBG_QUEUE_ERROR_BIT = 30 # macro -KFD_DBG_QUEUE_INVALID_BIT = 31 # macro -KFD_DBG_QUEUE_ERROR_MASK = (1<<30) # macro -KFD_DBG_QUEUE_INVALID_MASK = (1<<31) # macro -AMDKFD_IOCTL_BASE = 'K' # macro -def AMDKFD_IO(nr): # macro - return _IO('K',nr) -def AMDKFD_IOR(nr, type): # macro - return _IOR('K',nr,type) -def AMDKFD_IOW(nr, type): # macro - return _IOW('K',nr,type) -def AMDKFD_IOWR(nr, type): # macro - return _IOWR('K',nr,type) -AMDKFD_COMMAND_START = 0x01 # macro -AMDKFD_COMMAND_END = 0x27 # macro -class struct_kfd_ioctl_get_version_args(Structure): - pass - -struct_kfd_ioctl_get_version_args._pack_ = 1 # source:False +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class struct_kfd_ioctl_get_version_args(Struct): pass +__u32 = ctypes.c_uint32 struct_kfd_ioctl_get_version_args._fields_ = [ - ('major_version', ctypes.c_uint32), - ('minor_version', ctypes.c_uint32), + ('major_version', ctypes.c_uint32), + ('minor_version', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_VERSION = AMDKFD_IOR ( 0x01 , struct_kfd_ioctl_get_version_args ) # macro (from list) -class struct_kfd_ioctl_create_queue_args(Structure): - pass - -struct_kfd_ioctl_create_queue_args._pack_ = 1 # source:False +class struct_kfd_ioctl_create_queue_args(Struct): pass +__u64 = ctypes.c_uint64 struct_kfd_ioctl_create_queue_args._fields_ = [ - ('ring_base_address', ctypes.c_uint64), - ('write_pointer_address', ctypes.c_uint64), - ('read_pointer_address', ctypes.c_uint64), - ('doorbell_offset', ctypes.c_uint64), - ('ring_size', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), - ('queue_type', ctypes.c_uint32), - ('queue_percentage', ctypes.c_uint32), - ('queue_priority', ctypes.c_uint32), - ('queue_id', ctypes.c_uint32), - ('eop_buffer_address', ctypes.c_uint64), - ('eop_buffer_size', ctypes.c_uint64), - ('ctx_save_restore_address', ctypes.c_uint64), - ('ctx_save_restore_size', ctypes.c_uint32), - ('ctl_stack_size', ctypes.c_uint32), + ('ring_base_address', ctypes.c_uint64), + ('write_pointer_address', ctypes.c_uint64), + ('read_pointer_address', ctypes.c_uint64), + ('doorbell_offset', ctypes.c_uint64), + ('ring_size', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), + ('queue_type', ctypes.c_uint32), + ('queue_percentage', ctypes.c_uint32), + ('queue_priority', ctypes.c_uint32), + ('queue_id', ctypes.c_uint32), + ('eop_buffer_address', ctypes.c_uint64), + ('eop_buffer_size', ctypes.c_uint64), + ('ctx_save_restore_address', ctypes.c_uint64), + ('ctx_save_restore_size', ctypes.c_uint32), + ('ctl_stack_size', ctypes.c_uint32), ] - -AMDKFD_IOC_CREATE_QUEUE = AMDKFD_IOWR ( 0x02 , struct_kfd_ioctl_create_queue_args ) # macro (from list) -class struct_kfd_ioctl_destroy_queue_args(Structure): - pass - -struct_kfd_ioctl_destroy_queue_args._pack_ = 1 # source:False +class struct_kfd_ioctl_destroy_queue_args(Struct): pass struct_kfd_ioctl_destroy_queue_args._fields_ = [ - ('queue_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('queue_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_DESTROY_QUEUE = AMDKFD_IOWR ( 0x03 , struct_kfd_ioctl_destroy_queue_args ) # macro (from list) -class struct_kfd_ioctl_update_queue_args(Structure): - pass - -struct_kfd_ioctl_update_queue_args._pack_ = 1 # source:False +class struct_kfd_ioctl_update_queue_args(Struct): pass struct_kfd_ioctl_update_queue_args._fields_ = [ - ('ring_base_address', ctypes.c_uint64), - ('queue_id', ctypes.c_uint32), - ('ring_size', ctypes.c_uint32), - ('queue_percentage', ctypes.c_uint32), - ('queue_priority', ctypes.c_uint32), + ('ring_base_address', ctypes.c_uint64), + ('queue_id', ctypes.c_uint32), + ('ring_size', ctypes.c_uint32), + ('queue_percentage', ctypes.c_uint32), + ('queue_priority', ctypes.c_uint32), ] - -AMDKFD_IOC_UPDATE_QUEUE = AMDKFD_IOW ( 0x07 , struct_kfd_ioctl_update_queue_args ) # macro (from list) -class struct_kfd_ioctl_set_cu_mask_args(Structure): - pass - -struct_kfd_ioctl_set_cu_mask_args._pack_ = 1 # source:False +class struct_kfd_ioctl_set_cu_mask_args(Struct): pass struct_kfd_ioctl_set_cu_mask_args._fields_ = [ - ('queue_id', ctypes.c_uint32), - ('num_cu_mask', ctypes.c_uint32), - ('cu_mask_ptr', ctypes.c_uint64), + ('queue_id', ctypes.c_uint32), + ('num_cu_mask', ctypes.c_uint32), + ('cu_mask_ptr', ctypes.c_uint64), ] - -AMDKFD_IOC_SET_CU_MASK = AMDKFD_IOW ( 0x1A , struct_kfd_ioctl_set_cu_mask_args ) # macro (from list) -class struct_kfd_ioctl_get_queue_wave_state_args(Structure): - pass - -struct_kfd_ioctl_get_queue_wave_state_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_queue_wave_state_args(Struct): pass struct_kfd_ioctl_get_queue_wave_state_args._fields_ = [ - ('ctl_stack_address', ctypes.c_uint64), - ('ctl_stack_used_size', ctypes.c_uint32), - ('save_area_used_size', ctypes.c_uint32), - ('queue_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('ctl_stack_address', ctypes.c_uint64), + ('ctl_stack_used_size', ctypes.c_uint32), + ('save_area_used_size', ctypes.c_uint32), + ('queue_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_QUEUE_WAVE_STATE = AMDKFD_IOWR ( 0x1B , struct_kfd_ioctl_get_queue_wave_state_args ) # macro (from list) -class struct_kfd_ioctl_get_available_memory_args(Structure): - pass - -struct_kfd_ioctl_get_available_memory_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_available_memory_args(Struct): pass struct_kfd_ioctl_get_available_memory_args._fields_ = [ - ('available', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('available', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_AVAILABLE_MEMORY = AMDKFD_IOWR ( 0x23 , struct_kfd_ioctl_get_available_memory_args ) # macro (from list) -class struct_kfd_dbg_device_info_entry(Structure): - pass - -struct_kfd_dbg_device_info_entry._pack_ = 1 # source:False +class struct_kfd_dbg_device_info_entry(Struct): pass struct_kfd_dbg_device_info_entry._fields_ = [ - ('exception_status', ctypes.c_uint64), - ('lds_base', ctypes.c_uint64), - ('lds_limit', ctypes.c_uint64), - ('scratch_base', ctypes.c_uint64), - ('scratch_limit', ctypes.c_uint64), - ('gpuvm_base', ctypes.c_uint64), - ('gpuvm_limit', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('location_id', ctypes.c_uint32), - ('vendor_id', ctypes.c_uint32), - ('device_id', ctypes.c_uint32), - ('revision_id', ctypes.c_uint32), - ('subsystem_vendor_id', ctypes.c_uint32), - ('subsystem_device_id', ctypes.c_uint32), - ('fw_version', ctypes.c_uint32), - ('gfx_target_version', ctypes.c_uint32), - ('simd_count', ctypes.c_uint32), - ('max_waves_per_simd', ctypes.c_uint32), - ('array_count', ctypes.c_uint32), - ('simd_arrays_per_engine', ctypes.c_uint32), - ('num_xcc', ctypes.c_uint32), - ('capability', ctypes.c_uint32), - ('debug_prop', ctypes.c_uint32), + ('exception_status', ctypes.c_uint64), + ('lds_base', ctypes.c_uint64), + ('lds_limit', ctypes.c_uint64), + ('scratch_base', ctypes.c_uint64), + ('scratch_limit', ctypes.c_uint64), + ('gpuvm_base', ctypes.c_uint64), + ('gpuvm_limit', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('location_id', ctypes.c_uint32), + ('vendor_id', ctypes.c_uint32), + ('device_id', ctypes.c_uint32), + ('revision_id', ctypes.c_uint32), + ('subsystem_vendor_id', ctypes.c_uint32), + ('subsystem_device_id', ctypes.c_uint32), + ('fw_version', ctypes.c_uint32), + ('gfx_target_version', ctypes.c_uint32), + ('simd_count', ctypes.c_uint32), + ('max_waves_per_simd', ctypes.c_uint32), + ('array_count', ctypes.c_uint32), + ('simd_arrays_per_engine', ctypes.c_uint32), + ('num_xcc', ctypes.c_uint32), + ('capability', ctypes.c_uint32), + ('debug_prop', ctypes.c_uint32), ] - -class struct_kfd_ioctl_set_memory_policy_args(Structure): - pass - -struct_kfd_ioctl_set_memory_policy_args._pack_ = 1 # source:False +class struct_kfd_ioctl_set_memory_policy_args(Struct): pass struct_kfd_ioctl_set_memory_policy_args._fields_ = [ - ('alternate_aperture_base', ctypes.c_uint64), - ('alternate_aperture_size', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('default_policy', ctypes.c_uint32), - ('alternate_policy', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('alternate_aperture_base', ctypes.c_uint64), + ('alternate_aperture_size', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('default_policy', ctypes.c_uint32), + ('alternate_policy', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_SET_MEMORY_POLICY = AMDKFD_IOW ( 0x04 , struct_kfd_ioctl_set_memory_policy_args ) # macro (from list) -class struct_kfd_ioctl_get_clock_counters_args(Structure): - pass - -struct_kfd_ioctl_get_clock_counters_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_clock_counters_args(Struct): pass struct_kfd_ioctl_get_clock_counters_args._fields_ = [ - ('gpu_clock_counter', ctypes.c_uint64), - ('cpu_clock_counter', ctypes.c_uint64), - ('system_clock_counter', ctypes.c_uint64), - ('system_clock_freq', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('gpu_clock_counter', ctypes.c_uint64), + ('cpu_clock_counter', ctypes.c_uint64), + ('system_clock_counter', ctypes.c_uint64), + ('system_clock_freq', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_CLOCK_COUNTERS = AMDKFD_IOWR ( 0x05 , struct_kfd_ioctl_get_clock_counters_args ) # macro (from list) -class struct_kfd_process_device_apertures(Structure): - pass - -struct_kfd_process_device_apertures._pack_ = 1 # source:False +class struct_kfd_process_device_apertures(Struct): pass struct_kfd_process_device_apertures._fields_ = [ - ('lds_base', ctypes.c_uint64), - ('lds_limit', ctypes.c_uint64), - ('scratch_base', ctypes.c_uint64), - ('scratch_limit', ctypes.c_uint64), - ('gpuvm_base', ctypes.c_uint64), - ('gpuvm_limit', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('lds_base', ctypes.c_uint64), + ('lds_limit', ctypes.c_uint64), + ('scratch_base', ctypes.c_uint64), + ('scratch_limit', ctypes.c_uint64), + ('gpuvm_base', ctypes.c_uint64), + ('gpuvm_limit', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -class struct_kfd_ioctl_get_process_apertures_args(Structure): - pass - -struct_kfd_ioctl_get_process_apertures_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_process_apertures_args(Struct): pass struct_kfd_ioctl_get_process_apertures_args._fields_ = [ - ('process_apertures', struct_kfd_process_device_apertures * 7), - ('num_of_nodes', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('process_apertures', (struct_kfd_process_device_apertures * 7)), + ('num_of_nodes', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_PROCESS_APERTURES = AMDKFD_IOR ( 0x06 , struct_kfd_ioctl_get_process_apertures_args ) # macro (from list) -class struct_kfd_ioctl_get_process_apertures_new_args(Structure): - pass - -struct_kfd_ioctl_get_process_apertures_new_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_process_apertures_new_args(Struct): pass struct_kfd_ioctl_get_process_apertures_new_args._fields_ = [ - ('kfd_process_device_apertures_ptr', ctypes.c_uint64), - ('num_of_nodes', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('kfd_process_device_apertures_ptr', ctypes.c_uint64), + ('num_of_nodes', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_PROCESS_APERTURES_NEW = AMDKFD_IOWR ( 0x14 , struct_kfd_ioctl_get_process_apertures_new_args ) # macro (from list) -class struct_kfd_ioctl_dbg_register_args(Structure): - pass - -struct_kfd_ioctl_dbg_register_args._pack_ = 1 # source:False +class struct_kfd_ioctl_dbg_register_args(Struct): pass struct_kfd_ioctl_dbg_register_args._fields_ = [ - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_DBG_REGISTER_DEPRECATED = AMDKFD_IOW ( 0x0D , struct_kfd_ioctl_dbg_register_args ) # macro (from list) -class struct_kfd_ioctl_dbg_unregister_args(Structure): - pass - -struct_kfd_ioctl_dbg_unregister_args._pack_ = 1 # source:False +class struct_kfd_ioctl_dbg_unregister_args(Struct): pass struct_kfd_ioctl_dbg_unregister_args._fields_ = [ - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED = AMDKFD_IOW ( 0x0E , struct_kfd_ioctl_dbg_unregister_args ) # macro (from list) -class struct_kfd_ioctl_dbg_address_watch_args(Structure): - pass - -struct_kfd_ioctl_dbg_address_watch_args._pack_ = 1 # source:False +class struct_kfd_ioctl_dbg_address_watch_args(Struct): pass struct_kfd_ioctl_dbg_address_watch_args._fields_ = [ - ('content_ptr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('buf_size_in_bytes', ctypes.c_uint32), + ('content_ptr', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('buf_size_in_bytes', ctypes.c_uint32), ] - -AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED = AMDKFD_IOW ( 0x0F , struct_kfd_ioctl_dbg_address_watch_args ) # macro (from list) -class struct_kfd_ioctl_dbg_wave_control_args(Structure): - pass - -struct_kfd_ioctl_dbg_wave_control_args._pack_ = 1 # source:False +class struct_kfd_ioctl_dbg_wave_control_args(Struct): pass struct_kfd_ioctl_dbg_wave_control_args._fields_ = [ - ('content_ptr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('buf_size_in_bytes', ctypes.c_uint32), + ('content_ptr', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('buf_size_in_bytes', ctypes.c_uint32), ] - -AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED = AMDKFD_IOW ( 0x10 , struct_kfd_ioctl_dbg_wave_control_args ) # macro (from list) -class struct_kfd_ioctl_create_event_args(Structure): - pass - -struct_kfd_ioctl_create_event_args._pack_ = 1 # source:False +class struct_kfd_ioctl_create_event_args(Struct): pass struct_kfd_ioctl_create_event_args._fields_ = [ - ('event_page_offset', ctypes.c_uint64), - ('event_trigger_data', ctypes.c_uint32), - ('event_type', ctypes.c_uint32), - ('auto_reset', ctypes.c_uint32), - ('node_id', ctypes.c_uint32), - ('event_id', ctypes.c_uint32), - ('event_slot_index', ctypes.c_uint32), + ('event_page_offset', ctypes.c_uint64), + ('event_trigger_data', ctypes.c_uint32), + ('event_type', ctypes.c_uint32), + ('auto_reset', ctypes.c_uint32), + ('node_id', ctypes.c_uint32), + ('event_id', ctypes.c_uint32), + ('event_slot_index', ctypes.c_uint32), ] - -AMDKFD_IOC_CREATE_EVENT = AMDKFD_IOWR ( 0x08 , struct_kfd_ioctl_create_event_args ) # macro (from list) -class struct_kfd_ioctl_destroy_event_args(Structure): - pass - -struct_kfd_ioctl_destroy_event_args._pack_ = 1 # source:False +class struct_kfd_ioctl_destroy_event_args(Struct): pass struct_kfd_ioctl_destroy_event_args._fields_ = [ - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('event_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_DESTROY_EVENT = AMDKFD_IOW ( 0x09 , struct_kfd_ioctl_destroy_event_args ) # macro (from list) -class struct_kfd_ioctl_set_event_args(Structure): - pass - -struct_kfd_ioctl_set_event_args._pack_ = 1 # source:False +class struct_kfd_ioctl_set_event_args(Struct): pass struct_kfd_ioctl_set_event_args._fields_ = [ - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('event_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_SET_EVENT = AMDKFD_IOW ( 0x0A , struct_kfd_ioctl_set_event_args ) # macro (from list) -class struct_kfd_ioctl_reset_event_args(Structure): - pass - -struct_kfd_ioctl_reset_event_args._pack_ = 1 # source:False +class struct_kfd_ioctl_reset_event_args(Struct): pass struct_kfd_ioctl_reset_event_args._fields_ = [ - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('event_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_RESET_EVENT = AMDKFD_IOW ( 0x0B , struct_kfd_ioctl_reset_event_args ) # macro (from list) -class struct_kfd_memory_exception_failure(Structure): - pass - -struct_kfd_memory_exception_failure._pack_ = 1 # source:False +class struct_kfd_memory_exception_failure(Struct): pass struct_kfd_memory_exception_failure._fields_ = [ - ('NotPresent', ctypes.c_uint32), - ('ReadOnly', ctypes.c_uint32), - ('NoExecute', ctypes.c_uint32), - ('imprecise', ctypes.c_uint32), + ('NotPresent', ctypes.c_uint32), + ('ReadOnly', ctypes.c_uint32), + ('NoExecute', ctypes.c_uint32), + ('imprecise', ctypes.c_uint32), ] - -class struct_kfd_hsa_memory_exception_data(Structure): - pass - -struct_kfd_hsa_memory_exception_data._pack_ = 1 # source:False +class struct_kfd_hsa_memory_exception_data(Struct): pass struct_kfd_hsa_memory_exception_data._fields_ = [ - ('failure', struct_kfd_memory_exception_failure), - ('va', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('ErrorType', ctypes.c_uint32), + ('failure', struct_kfd_memory_exception_failure), + ('va', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('ErrorType', ctypes.c_uint32), ] - -class struct_kfd_hsa_hw_exception_data(Structure): - pass - -struct_kfd_hsa_hw_exception_data._pack_ = 1 # source:False +class struct_kfd_hsa_hw_exception_data(Struct): pass struct_kfd_hsa_hw_exception_data._fields_ = [ - ('reset_type', ctypes.c_uint32), - ('reset_cause', ctypes.c_uint32), - ('memory_lost', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), + ('reset_type', ctypes.c_uint32), + ('reset_cause', ctypes.c_uint32), + ('memory_lost', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), ] - -class struct_kfd_hsa_signal_event_data(Structure): - pass - -struct_kfd_hsa_signal_event_data._pack_ = 1 # source:False +class struct_kfd_hsa_signal_event_data(Struct): pass struct_kfd_hsa_signal_event_data._fields_ = [ - ('last_event_age', ctypes.c_uint64), + ('last_event_age', ctypes.c_uint64), ] - -class struct_kfd_event_data(Structure): - pass - -class union_kfd_event_data_0(Union): - pass - -union_kfd_event_data_0._pack_ = 1 # source:False -union_kfd_event_data_0._fields_ = [ - ('memory_exception_data', struct_kfd_hsa_memory_exception_data), - ('hw_exception_data', struct_kfd_hsa_hw_exception_data), - ('signal_event_data', struct_kfd_hsa_signal_event_data), - ('PADDING_0', ctypes.c_ubyte * 24), +class struct_kfd_event_data(Struct): pass +class struct_kfd_event_data_0(ctypes.Union): pass +struct_kfd_event_data_0._fields_ = [ + ('memory_exception_data', struct_kfd_hsa_memory_exception_data), + ('hw_exception_data', struct_kfd_hsa_hw_exception_data), + ('signal_event_data', struct_kfd_hsa_signal_event_data), ] - -struct_kfd_event_data._pack_ = 1 # source:False -struct_kfd_event_data._anonymous_ = ('_0',) +struct_kfd_event_data._anonymous_ = ['_0'] struct_kfd_event_data._fields_ = [ - ('_0', union_kfd_event_data_0), - ('kfd_event_data_ext', ctypes.c_uint64), - ('event_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('_0', struct_kfd_event_data_0), + ('kfd_event_data_ext', ctypes.c_uint64), + ('event_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -class struct_kfd_ioctl_wait_events_args(Structure): - pass - -struct_kfd_ioctl_wait_events_args._pack_ = 1 # source:False +class struct_kfd_ioctl_wait_events_args(Struct): pass struct_kfd_ioctl_wait_events_args._fields_ = [ - ('events_ptr', ctypes.c_uint64), - ('num_events', ctypes.c_uint32), - ('wait_for_all', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), - ('wait_result', ctypes.c_uint32), + ('events_ptr', ctypes.c_uint64), + ('num_events', ctypes.c_uint32), + ('wait_for_all', ctypes.c_uint32), + ('timeout', ctypes.c_uint32), + ('wait_result', ctypes.c_uint32), ] - -AMDKFD_IOC_WAIT_EVENTS = AMDKFD_IOWR ( 0x0C , struct_kfd_ioctl_wait_events_args ) # macro (from list) -class struct_kfd_ioctl_set_scratch_backing_va_args(Structure): - pass - -struct_kfd_ioctl_set_scratch_backing_va_args._pack_ = 1 # source:False +class struct_kfd_ioctl_set_scratch_backing_va_args(Struct): pass struct_kfd_ioctl_set_scratch_backing_va_args._fields_ = [ - ('va_addr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('va_addr', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_SET_SCRATCH_BACKING_VA = AMDKFD_IOWR ( 0x11 , struct_kfd_ioctl_set_scratch_backing_va_args ) # macro (from list) -class struct_kfd_ioctl_get_tile_config_args(Structure): - pass - -struct_kfd_ioctl_get_tile_config_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_tile_config_args(Struct): pass struct_kfd_ioctl_get_tile_config_args._fields_ = [ - ('tile_config_ptr', ctypes.c_uint64), - ('macro_tile_config_ptr', ctypes.c_uint64), - ('num_tile_configs', ctypes.c_uint32), - ('num_macro_tile_configs', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), - ('gb_addr_config', ctypes.c_uint32), - ('num_banks', ctypes.c_uint32), - ('num_ranks', ctypes.c_uint32), + ('tile_config_ptr', ctypes.c_uint64), + ('macro_tile_config_ptr', ctypes.c_uint64), + ('num_tile_configs', ctypes.c_uint32), + ('num_macro_tile_configs', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), + ('gb_addr_config', ctypes.c_uint32), + ('num_banks', ctypes.c_uint32), + ('num_ranks', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_TILE_CONFIG = AMDKFD_IOWR ( 0x12 , struct_kfd_ioctl_get_tile_config_args ) # macro (from list) -class struct_kfd_ioctl_set_trap_handler_args(Structure): - pass - -struct_kfd_ioctl_set_trap_handler_args._pack_ = 1 # source:False +class struct_kfd_ioctl_set_trap_handler_args(Struct): pass struct_kfd_ioctl_set_trap_handler_args._fields_ = [ - ('tba_addr', ctypes.c_uint64), - ('tma_addr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('tba_addr', ctypes.c_uint64), + ('tma_addr', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_SET_TRAP_HANDLER = AMDKFD_IOW ( 0x13 , struct_kfd_ioctl_set_trap_handler_args ) # macro (from list) -class struct_kfd_ioctl_acquire_vm_args(Structure): - pass - -struct_kfd_ioctl_acquire_vm_args._pack_ = 1 # source:False +class struct_kfd_ioctl_acquire_vm_args(Struct): pass struct_kfd_ioctl_acquire_vm_args._fields_ = [ - ('drm_fd', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), + ('drm_fd', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), ] - -AMDKFD_IOC_ACQUIRE_VM = AMDKFD_IOW ( 0x15 , struct_kfd_ioctl_acquire_vm_args ) # macro (from list) -class struct_kfd_ioctl_alloc_memory_of_gpu_args(Structure): - pass - -struct_kfd_ioctl_alloc_memory_of_gpu_args._pack_ = 1 # source:False +class struct_kfd_ioctl_alloc_memory_of_gpu_args(Struct): pass struct_kfd_ioctl_alloc_memory_of_gpu_args._fields_ = [ - ('va_addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('handle', ctypes.c_uint64), - ('mmap_offset', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), + ('va_addr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('handle', ctypes.c_uint64), + ('mmap_offset', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('flags', ctypes.c_uint32), ] - -AMDKFD_IOC_ALLOC_MEMORY_OF_GPU = AMDKFD_IOWR ( 0x16 , struct_kfd_ioctl_alloc_memory_of_gpu_args ) # macro (from list) -class struct_kfd_ioctl_free_memory_of_gpu_args(Structure): - pass - -struct_kfd_ioctl_free_memory_of_gpu_args._pack_ = 1 # source:False +class struct_kfd_ioctl_free_memory_of_gpu_args(Struct): pass struct_kfd_ioctl_free_memory_of_gpu_args._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', ctypes.c_uint64), ] - -AMDKFD_IOC_FREE_MEMORY_OF_GPU = AMDKFD_IOW ( 0x17 , struct_kfd_ioctl_free_memory_of_gpu_args ) # macro (from list) -class struct_kfd_ioctl_map_memory_to_gpu_args(Structure): - pass - -struct_kfd_ioctl_map_memory_to_gpu_args._pack_ = 1 # source:False +class struct_kfd_ioctl_map_memory_to_gpu_args(Struct): pass struct_kfd_ioctl_map_memory_to_gpu_args._fields_ = [ - ('handle', ctypes.c_uint64), - ('device_ids_array_ptr', ctypes.c_uint64), - ('n_devices', ctypes.c_uint32), - ('n_success', ctypes.c_uint32), + ('handle', ctypes.c_uint64), + ('device_ids_array_ptr', ctypes.c_uint64), + ('n_devices', ctypes.c_uint32), + ('n_success', ctypes.c_uint32), ] - -AMDKFD_IOC_MAP_MEMORY_TO_GPU = AMDKFD_IOWR ( 0x18 , struct_kfd_ioctl_map_memory_to_gpu_args ) # macro (from list) -class struct_kfd_ioctl_unmap_memory_from_gpu_args(Structure): - pass - -struct_kfd_ioctl_unmap_memory_from_gpu_args._pack_ = 1 # source:False +class struct_kfd_ioctl_unmap_memory_from_gpu_args(Struct): pass struct_kfd_ioctl_unmap_memory_from_gpu_args._fields_ = [ - ('handle', ctypes.c_uint64), - ('device_ids_array_ptr', ctypes.c_uint64), - ('n_devices', ctypes.c_uint32), - ('n_success', ctypes.c_uint32), + ('handle', ctypes.c_uint64), + ('device_ids_array_ptr', ctypes.c_uint64), + ('n_devices', ctypes.c_uint32), + ('n_success', ctypes.c_uint32), ] - -AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU = AMDKFD_IOWR ( 0x19 , struct_kfd_ioctl_unmap_memory_from_gpu_args ) # macro (from list) -class struct_kfd_ioctl_alloc_queue_gws_args(Structure): - pass - -struct_kfd_ioctl_alloc_queue_gws_args._pack_ = 1 # source:False +class struct_kfd_ioctl_alloc_queue_gws_args(Struct): pass struct_kfd_ioctl_alloc_queue_gws_args._fields_ = [ - ('queue_id', ctypes.c_uint32), - ('num_gws', ctypes.c_uint32), - ('first_gws', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('queue_id', ctypes.c_uint32), + ('num_gws', ctypes.c_uint32), + ('first_gws', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -AMDKFD_IOC_ALLOC_QUEUE_GWS = AMDKFD_IOWR ( 0x1E , struct_kfd_ioctl_alloc_queue_gws_args ) # macro (from list) -class struct_kfd_ioctl_get_dmabuf_info_args(Structure): - pass - -struct_kfd_ioctl_get_dmabuf_info_args._pack_ = 1 # source:False +class struct_kfd_ioctl_get_dmabuf_info_args(Struct): pass struct_kfd_ioctl_get_dmabuf_info_args._fields_ = [ - ('size', ctypes.c_uint64), - ('metadata_ptr', ctypes.c_uint64), - ('metadata_size', ctypes.c_uint32), - ('gpu_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), + ('size', ctypes.c_uint64), + ('metadata_ptr', ctypes.c_uint64), + ('metadata_size', ctypes.c_uint32), + ('gpu_id', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('dmabuf_fd', ctypes.c_uint32), ] - -AMDKFD_IOC_GET_DMABUF_INFO = AMDKFD_IOWR ( 0x1C , struct_kfd_ioctl_get_dmabuf_info_args ) # macro (from list) -class struct_kfd_ioctl_import_dmabuf_args(Structure): - pass - -struct_kfd_ioctl_import_dmabuf_args._pack_ = 1 # source:False +class struct_kfd_ioctl_import_dmabuf_args(Struct): pass struct_kfd_ioctl_import_dmabuf_args._fields_ = [ - ('va_addr', ctypes.c_uint64), - ('handle', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), + ('va_addr', ctypes.c_uint64), + ('handle', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('dmabuf_fd', ctypes.c_uint32), ] - -AMDKFD_IOC_IMPORT_DMABUF = AMDKFD_IOWR ( 0x1D , struct_kfd_ioctl_import_dmabuf_args ) # macro (from list) -class struct_kfd_ioctl_export_dmabuf_args(Structure): - pass - -struct_kfd_ioctl_export_dmabuf_args._pack_ = 1 # source:False +class struct_kfd_ioctl_export_dmabuf_args(Struct): pass struct_kfd_ioctl_export_dmabuf_args._fields_ = [ - ('handle', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), + ('handle', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('dmabuf_fd', ctypes.c_uint32), ] +enum_kfd_smi_event = CEnum(ctypes.c_uint32) +KFD_SMI_EVENT_NONE = enum_kfd_smi_event.define('KFD_SMI_EVENT_NONE', 0) +KFD_SMI_EVENT_VMFAULT = enum_kfd_smi_event.define('KFD_SMI_EVENT_VMFAULT', 1) +KFD_SMI_EVENT_THERMAL_THROTTLE = enum_kfd_smi_event.define('KFD_SMI_EVENT_THERMAL_THROTTLE', 2) +KFD_SMI_EVENT_GPU_PRE_RESET = enum_kfd_smi_event.define('KFD_SMI_EVENT_GPU_PRE_RESET', 3) +KFD_SMI_EVENT_GPU_POST_RESET = enum_kfd_smi_event.define('KFD_SMI_EVENT_GPU_POST_RESET', 4) +KFD_SMI_EVENT_MIGRATE_START = enum_kfd_smi_event.define('KFD_SMI_EVENT_MIGRATE_START', 5) +KFD_SMI_EVENT_MIGRATE_END = enum_kfd_smi_event.define('KFD_SMI_EVENT_MIGRATE_END', 6) +KFD_SMI_EVENT_PAGE_FAULT_START = enum_kfd_smi_event.define('KFD_SMI_EVENT_PAGE_FAULT_START', 7) +KFD_SMI_EVENT_PAGE_FAULT_END = enum_kfd_smi_event.define('KFD_SMI_EVENT_PAGE_FAULT_END', 8) +KFD_SMI_EVENT_QUEUE_EVICTION = enum_kfd_smi_event.define('KFD_SMI_EVENT_QUEUE_EVICTION', 9) +KFD_SMI_EVENT_QUEUE_RESTORE = enum_kfd_smi_event.define('KFD_SMI_EVENT_QUEUE_RESTORE', 10) +KFD_SMI_EVENT_UNMAP_FROM_GPU = enum_kfd_smi_event.define('KFD_SMI_EVENT_UNMAP_FROM_GPU', 11) +KFD_SMI_EVENT_ALL_PROCESS = enum_kfd_smi_event.define('KFD_SMI_EVENT_ALL_PROCESS', 64) -AMDKFD_IOC_EXPORT_DMABUF = AMDKFD_IOWR ( 0x24 , struct_kfd_ioctl_export_dmabuf_args ) # macro (from list) +enum_KFD_MIGRATE_TRIGGERS = CEnum(ctypes.c_uint32) +KFD_MIGRATE_TRIGGER_PREFETCH = enum_KFD_MIGRATE_TRIGGERS.define('KFD_MIGRATE_TRIGGER_PREFETCH', 0) +KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU = enum_KFD_MIGRATE_TRIGGERS.define('KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU', 1) +KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU = enum_KFD_MIGRATE_TRIGGERS.define('KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU', 2) +KFD_MIGRATE_TRIGGER_TTM_EVICTION = enum_KFD_MIGRATE_TRIGGERS.define('KFD_MIGRATE_TRIGGER_TTM_EVICTION', 3) -# values for enumeration 'kfd_smi_event' -kfd_smi_event__enumvalues = { - 0: 'KFD_SMI_EVENT_NONE', - 1: 'KFD_SMI_EVENT_VMFAULT', - 2: 'KFD_SMI_EVENT_THERMAL_THROTTLE', - 3: 'KFD_SMI_EVENT_GPU_PRE_RESET', - 4: 'KFD_SMI_EVENT_GPU_POST_RESET', - 5: 'KFD_SMI_EVENT_MIGRATE_START', - 6: 'KFD_SMI_EVENT_MIGRATE_END', - 7: 'KFD_SMI_EVENT_PAGE_FAULT_START', - 8: 'KFD_SMI_EVENT_PAGE_FAULT_END', - 9: 'KFD_SMI_EVENT_QUEUE_EVICTION', - 10: 'KFD_SMI_EVENT_QUEUE_RESTORE', - 11: 'KFD_SMI_EVENT_UNMAP_FROM_GPU', - 64: 'KFD_SMI_EVENT_ALL_PROCESS', -} -KFD_SMI_EVENT_NONE = 0 -KFD_SMI_EVENT_VMFAULT = 1 -KFD_SMI_EVENT_THERMAL_THROTTLE = 2 -KFD_SMI_EVENT_GPU_PRE_RESET = 3 -KFD_SMI_EVENT_GPU_POST_RESET = 4 -KFD_SMI_EVENT_MIGRATE_START = 5 -KFD_SMI_EVENT_MIGRATE_END = 6 -KFD_SMI_EVENT_PAGE_FAULT_START = 7 -KFD_SMI_EVENT_PAGE_FAULT_END = 8 -KFD_SMI_EVENT_QUEUE_EVICTION = 9 -KFD_SMI_EVENT_QUEUE_RESTORE = 10 -KFD_SMI_EVENT_UNMAP_FROM_GPU = 11 -KFD_SMI_EVENT_ALL_PROCESS = 64 -kfd_smi_event = ctypes.c_uint32 # enum +enum_KFD_QUEUE_EVICTION_TRIGGERS = CEnum(ctypes.c_uint32) +KFD_QUEUE_EVICTION_TRIGGER_SVM = enum_KFD_QUEUE_EVICTION_TRIGGERS.define('KFD_QUEUE_EVICTION_TRIGGER_SVM', 0) +KFD_QUEUE_EVICTION_TRIGGER_USERPTR = enum_KFD_QUEUE_EVICTION_TRIGGERS.define('KFD_QUEUE_EVICTION_TRIGGER_USERPTR', 1) +KFD_QUEUE_EVICTION_TRIGGER_TTM = enum_KFD_QUEUE_EVICTION_TRIGGERS.define('KFD_QUEUE_EVICTION_TRIGGER_TTM', 2) +KFD_QUEUE_EVICTION_TRIGGER_SUSPEND = enum_KFD_QUEUE_EVICTION_TRIGGERS.define('KFD_QUEUE_EVICTION_TRIGGER_SUSPEND', 3) +KFD_QUEUE_EVICTION_CRIU_CHECKPOINT = enum_KFD_QUEUE_EVICTION_TRIGGERS.define('KFD_QUEUE_EVICTION_CRIU_CHECKPOINT', 4) +KFD_QUEUE_EVICTION_CRIU_RESTORE = enum_KFD_QUEUE_EVICTION_TRIGGERS.define('KFD_QUEUE_EVICTION_CRIU_RESTORE', 5) -# values for enumeration 'KFD_MIGRATE_TRIGGERS' -KFD_MIGRATE_TRIGGERS__enumvalues = { - 0: 'KFD_MIGRATE_TRIGGER_PREFETCH', - 1: 'KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU', - 2: 'KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU', - 3: 'KFD_MIGRATE_TRIGGER_TTM_EVICTION', -} -KFD_MIGRATE_TRIGGER_PREFETCH = 0 -KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU = 1 -KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU = 2 -KFD_MIGRATE_TRIGGER_TTM_EVICTION = 3 -KFD_MIGRATE_TRIGGERS = ctypes.c_uint32 # enum +enum_KFD_SVM_UNMAP_TRIGGERS = CEnum(ctypes.c_uint32) +KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY = enum_KFD_SVM_UNMAP_TRIGGERS.define('KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY', 0) +KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE = enum_KFD_SVM_UNMAP_TRIGGERS.define('KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE', 1) +KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU = enum_KFD_SVM_UNMAP_TRIGGERS.define('KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU', 2) -# values for enumeration 'KFD_QUEUE_EVICTION_TRIGGERS' -KFD_QUEUE_EVICTION_TRIGGERS__enumvalues = { - 0: 'KFD_QUEUE_EVICTION_TRIGGER_SVM', - 1: 'KFD_QUEUE_EVICTION_TRIGGER_USERPTR', - 2: 'KFD_QUEUE_EVICTION_TRIGGER_TTM', - 3: 'KFD_QUEUE_EVICTION_TRIGGER_SUSPEND', - 4: 'KFD_QUEUE_EVICTION_CRIU_CHECKPOINT', - 5: 'KFD_QUEUE_EVICTION_CRIU_RESTORE', -} -KFD_QUEUE_EVICTION_TRIGGER_SVM = 0 -KFD_QUEUE_EVICTION_TRIGGER_USERPTR = 1 -KFD_QUEUE_EVICTION_TRIGGER_TTM = 2 -KFD_QUEUE_EVICTION_TRIGGER_SUSPEND = 3 -KFD_QUEUE_EVICTION_CRIU_CHECKPOINT = 4 -KFD_QUEUE_EVICTION_CRIU_RESTORE = 5 -KFD_QUEUE_EVICTION_TRIGGERS = ctypes.c_uint32 # enum - -# values for enumeration 'KFD_SVM_UNMAP_TRIGGERS' -KFD_SVM_UNMAP_TRIGGERS__enumvalues = { - 0: 'KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY', - 1: 'KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE', - 2: 'KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU', -} -KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY = 0 -KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE = 1 -KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU = 2 -KFD_SVM_UNMAP_TRIGGERS = ctypes.c_uint32 # enum -class struct_kfd_ioctl_smi_events_args(Structure): - pass - -struct_kfd_ioctl_smi_events_args._pack_ = 1 # source:False +class struct_kfd_ioctl_smi_events_args(Struct): pass struct_kfd_ioctl_smi_events_args._fields_ = [ - ('gpuid', ctypes.c_uint32), - ('anon_fd', ctypes.c_uint32), + ('gpuid', ctypes.c_uint32), + ('anon_fd', ctypes.c_uint32), ] +enum_kfd_criu_op = CEnum(ctypes.c_uint32) +KFD_CRIU_OP_PROCESS_INFO = enum_kfd_criu_op.define('KFD_CRIU_OP_PROCESS_INFO', 0) +KFD_CRIU_OP_CHECKPOINT = enum_kfd_criu_op.define('KFD_CRIU_OP_CHECKPOINT', 1) +KFD_CRIU_OP_UNPAUSE = enum_kfd_criu_op.define('KFD_CRIU_OP_UNPAUSE', 2) +KFD_CRIU_OP_RESTORE = enum_kfd_criu_op.define('KFD_CRIU_OP_RESTORE', 3) +KFD_CRIU_OP_RESUME = enum_kfd_criu_op.define('KFD_CRIU_OP_RESUME', 4) -AMDKFD_IOC_SMI_EVENTS = AMDKFD_IOWR ( 0x1F , struct_kfd_ioctl_smi_events_args ) # macro (from list) - -# values for enumeration 'kfd_criu_op' -kfd_criu_op__enumvalues = { - 0: 'KFD_CRIU_OP_PROCESS_INFO', - 1: 'KFD_CRIU_OP_CHECKPOINT', - 2: 'KFD_CRIU_OP_UNPAUSE', - 3: 'KFD_CRIU_OP_RESTORE', - 4: 'KFD_CRIU_OP_RESUME', -} -KFD_CRIU_OP_PROCESS_INFO = 0 -KFD_CRIU_OP_CHECKPOINT = 1 -KFD_CRIU_OP_UNPAUSE = 2 -KFD_CRIU_OP_RESTORE = 3 -KFD_CRIU_OP_RESUME = 4 -kfd_criu_op = ctypes.c_uint32 # enum -class struct_kfd_ioctl_criu_args(Structure): - pass - -struct_kfd_ioctl_criu_args._pack_ = 1 # source:False +class struct_kfd_ioctl_criu_args(Struct): pass struct_kfd_ioctl_criu_args._fields_ = [ - ('devices', ctypes.c_uint64), - ('bos', ctypes.c_uint64), - ('priv_data', ctypes.c_uint64), - ('priv_data_size', ctypes.c_uint64), - ('num_devices', ctypes.c_uint32), - ('num_bos', ctypes.c_uint32), - ('num_objects', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('devices', ctypes.c_uint64), + ('bos', ctypes.c_uint64), + ('priv_data', ctypes.c_uint64), + ('priv_data_size', ctypes.c_uint64), + ('num_devices', ctypes.c_uint32), + ('num_bos', ctypes.c_uint32), + ('num_objects', ctypes.c_uint32), + ('pid', ctypes.c_uint32), + ('op', ctypes.c_uint32), ] - -AMDKFD_IOC_CRIU_OP = AMDKFD_IOWR ( 0x22 , struct_kfd_ioctl_criu_args ) # macro (from list) -class struct_kfd_criu_device_bucket(Structure): - pass - -struct_kfd_criu_device_bucket._pack_ = 1 # source:False +class struct_kfd_criu_device_bucket(Struct): pass struct_kfd_criu_device_bucket._fields_ = [ - ('user_gpu_id', ctypes.c_uint32), - ('actual_gpu_id', ctypes.c_uint32), - ('drm_fd', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('user_gpu_id', ctypes.c_uint32), + ('actual_gpu_id', ctypes.c_uint32), + ('drm_fd', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -class struct_kfd_criu_bo_bucket(Structure): - pass - -struct_kfd_criu_bo_bucket._pack_ = 1 # source:False +class struct_kfd_criu_bo_bucket(Struct): pass struct_kfd_criu_bo_bucket._fields_ = [ - ('addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('restored_offset', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('alloc_flags', ctypes.c_uint32), - ('dmabuf_fd', ctypes.c_uint32), - ('pad', ctypes.c_uint32), + ('addr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('offset', ctypes.c_uint64), + ('restored_offset', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('alloc_flags', ctypes.c_uint32), + ('dmabuf_fd', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] +enum_kfd_mmio_remap = CEnum(ctypes.c_uint32) +KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = enum_kfd_mmio_remap.define('KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL', 0) +KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = enum_kfd_mmio_remap.define('KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL', 4) +enum_kfd_ioctl_svm_op = CEnum(ctypes.c_uint32) +KFD_IOCTL_SVM_OP_SET_ATTR = enum_kfd_ioctl_svm_op.define('KFD_IOCTL_SVM_OP_SET_ATTR', 0) +KFD_IOCTL_SVM_OP_GET_ATTR = enum_kfd_ioctl_svm_op.define('KFD_IOCTL_SVM_OP_GET_ATTR', 1) -# values for enumeration 'kfd_mmio_remap' -kfd_mmio_remap__enumvalues = { - 0: 'KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL', - 4: 'KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL', -} -KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0 -KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4 -kfd_mmio_remap = ctypes.c_uint32 # enum +enum_kfd_ioctl_svm_location = CEnum(ctypes.c_uint32) +KFD_IOCTL_SVM_LOCATION_SYSMEM = enum_kfd_ioctl_svm_location.define('KFD_IOCTL_SVM_LOCATION_SYSMEM', 0) +KFD_IOCTL_SVM_LOCATION_UNDEFINED = enum_kfd_ioctl_svm_location.define('KFD_IOCTL_SVM_LOCATION_UNDEFINED', 4294967295) -# values for enumeration 'kfd_ioctl_svm_op' -kfd_ioctl_svm_op__enumvalues = { - 0: 'KFD_IOCTL_SVM_OP_SET_ATTR', - 1: 'KFD_IOCTL_SVM_OP_GET_ATTR', -} -KFD_IOCTL_SVM_OP_SET_ATTR = 0 -KFD_IOCTL_SVM_OP_GET_ATTR = 1 -kfd_ioctl_svm_op = ctypes.c_uint32 # enum +enum_kfd_ioctl_svm_attr_type = CEnum(ctypes.c_uint32) +KFD_IOCTL_SVM_ATTR_PREFERRED_LOC = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_PREFERRED_LOC', 0) +KFD_IOCTL_SVM_ATTR_PREFETCH_LOC = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_PREFETCH_LOC', 1) +KFD_IOCTL_SVM_ATTR_ACCESS = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_ACCESS', 2) +KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE', 3) +KFD_IOCTL_SVM_ATTR_NO_ACCESS = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_NO_ACCESS', 4) +KFD_IOCTL_SVM_ATTR_SET_FLAGS = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_SET_FLAGS', 5) +KFD_IOCTL_SVM_ATTR_CLR_FLAGS = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_CLR_FLAGS', 6) +KFD_IOCTL_SVM_ATTR_GRANULARITY = enum_kfd_ioctl_svm_attr_type.define('KFD_IOCTL_SVM_ATTR_GRANULARITY', 7) -# values for enumeration 'kfd_ioctl_svm_location' -kfd_ioctl_svm_location__enumvalues = { - 0: 'KFD_IOCTL_SVM_LOCATION_SYSMEM', - 4294967295: 'KFD_IOCTL_SVM_LOCATION_UNDEFINED', -} -KFD_IOCTL_SVM_LOCATION_SYSMEM = 0 -KFD_IOCTL_SVM_LOCATION_UNDEFINED = 4294967295 -kfd_ioctl_svm_location = ctypes.c_uint32 # enum - -# values for enumeration 'kfd_ioctl_svm_attr_type' -kfd_ioctl_svm_attr_type__enumvalues = { - 0: 'KFD_IOCTL_SVM_ATTR_PREFERRED_LOC', - 1: 'KFD_IOCTL_SVM_ATTR_PREFETCH_LOC', - 2: 'KFD_IOCTL_SVM_ATTR_ACCESS', - 3: 'KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE', - 4: 'KFD_IOCTL_SVM_ATTR_NO_ACCESS', - 5: 'KFD_IOCTL_SVM_ATTR_SET_FLAGS', - 6: 'KFD_IOCTL_SVM_ATTR_CLR_FLAGS', - 7: 'KFD_IOCTL_SVM_ATTR_GRANULARITY', -} -KFD_IOCTL_SVM_ATTR_PREFERRED_LOC = 0 -KFD_IOCTL_SVM_ATTR_PREFETCH_LOC = 1 -KFD_IOCTL_SVM_ATTR_ACCESS = 2 -KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE = 3 -KFD_IOCTL_SVM_ATTR_NO_ACCESS = 4 -KFD_IOCTL_SVM_ATTR_SET_FLAGS = 5 -KFD_IOCTL_SVM_ATTR_CLR_FLAGS = 6 -KFD_IOCTL_SVM_ATTR_GRANULARITY = 7 -kfd_ioctl_svm_attr_type = ctypes.c_uint32 # enum -class struct_kfd_ioctl_svm_attribute(Structure): - pass - -struct_kfd_ioctl_svm_attribute._pack_ = 1 # source:False +class struct_kfd_ioctl_svm_attribute(Struct): pass struct_kfd_ioctl_svm_attribute._fields_ = [ - ('type', ctypes.c_uint32), - ('value', ctypes.c_uint32), + ('type', ctypes.c_uint32), + ('value', ctypes.c_uint32), ] - -class struct_kfd_ioctl_svm_args(Structure): - pass - -struct_kfd_ioctl_svm_args._pack_ = 1 # source:False +class struct_kfd_ioctl_svm_args(Struct): pass struct_kfd_ioctl_svm_args._fields_ = [ - ('start_addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('op', ctypes.c_uint32), - ('nattr', ctypes.c_uint32), - ('attrs', struct_kfd_ioctl_svm_attribute * 0), + ('start_addr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('op', ctypes.c_uint32), + ('nattr', ctypes.c_uint32), + ('attrs', (struct_kfd_ioctl_svm_attribute * 0)), ] - -AMDKFD_IOC_SVM = AMDKFD_IOWR ( 0x20 , struct_kfd_ioctl_svm_args ) # macro (from list) -class struct_kfd_ioctl_set_xnack_mode_args(Structure): - pass - -struct_kfd_ioctl_set_xnack_mode_args._pack_ = 1 # source:False +class struct_kfd_ioctl_set_xnack_mode_args(Struct): pass +__s32 = ctypes.c_int32 struct_kfd_ioctl_set_xnack_mode_args._fields_ = [ - ('xnack_enabled', ctypes.c_int32), + ('xnack_enabled', ctypes.c_int32), ] +enum_kfd_dbg_trap_override_mode = CEnum(ctypes.c_uint32) +KFD_DBG_TRAP_OVERRIDE_OR = enum_kfd_dbg_trap_override_mode.define('KFD_DBG_TRAP_OVERRIDE_OR', 0) +KFD_DBG_TRAP_OVERRIDE_REPLACE = enum_kfd_dbg_trap_override_mode.define('KFD_DBG_TRAP_OVERRIDE_REPLACE', 1) -AMDKFD_IOC_SET_XNACK_MODE = AMDKFD_IOWR ( 0x21 , struct_kfd_ioctl_set_xnack_mode_args ) # macro (from list) +enum_kfd_dbg_trap_mask = CEnum(ctypes.c_int32) +KFD_DBG_TRAP_MASK_FP_INVALID = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_FP_INVALID', 1) +KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL', 2) +KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO', 4) +KFD_DBG_TRAP_MASK_FP_OVERFLOW = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_FP_OVERFLOW', 8) +KFD_DBG_TRAP_MASK_FP_UNDERFLOW = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_FP_UNDERFLOW', 16) +KFD_DBG_TRAP_MASK_FP_INEXACT = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_FP_INEXACT', 32) +KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO', 64) +KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH', 128) +KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION', 256) +KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START', 1073741824) +KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END = enum_kfd_dbg_trap_mask.define('KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END', -2147483648) -# values for enumeration 'kfd_dbg_trap_override_mode' -kfd_dbg_trap_override_mode__enumvalues = { - 0: 'KFD_DBG_TRAP_OVERRIDE_OR', - 1: 'KFD_DBG_TRAP_OVERRIDE_REPLACE', -} -KFD_DBG_TRAP_OVERRIDE_OR = 0 -KFD_DBG_TRAP_OVERRIDE_REPLACE = 1 -kfd_dbg_trap_override_mode = ctypes.c_uint32 # enum +enum_kfd_dbg_trap_wave_launch_mode = CEnum(ctypes.c_uint32) +KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL = enum_kfd_dbg_trap_wave_launch_mode.define('KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL', 0) +KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT = enum_kfd_dbg_trap_wave_launch_mode.define('KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT', 1) +KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG = enum_kfd_dbg_trap_wave_launch_mode.define('KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG', 3) -# values for enumeration 'kfd_dbg_trap_mask' -kfd_dbg_trap_mask__enumvalues = { - 1: 'KFD_DBG_TRAP_MASK_FP_INVALID', - 2: 'KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL', - 4: 'KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO', - 8: 'KFD_DBG_TRAP_MASK_FP_OVERFLOW', - 16: 'KFD_DBG_TRAP_MASK_FP_UNDERFLOW', - 32: 'KFD_DBG_TRAP_MASK_FP_INEXACT', - 64: 'KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO', - 128: 'KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH', - 256: 'KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION', - 1073741824: 'KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START', - -2147483648: 'KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END', -} -KFD_DBG_TRAP_MASK_FP_INVALID = 1 -KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL = 2 -KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO = 4 -KFD_DBG_TRAP_MASK_FP_OVERFLOW = 8 -KFD_DBG_TRAP_MASK_FP_UNDERFLOW = 16 -KFD_DBG_TRAP_MASK_FP_INEXACT = 32 -KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO = 64 -KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH = 128 -KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION = 256 -KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START = 1073741824 -KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END = -2147483648 -kfd_dbg_trap_mask = ctypes.c_int32 # enum +enum_kfd_dbg_trap_address_watch_mode = CEnum(ctypes.c_uint32) +KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ = enum_kfd_dbg_trap_address_watch_mode.define('KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ', 0) +KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD = enum_kfd_dbg_trap_address_watch_mode.define('KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD', 1) +KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC = enum_kfd_dbg_trap_address_watch_mode.define('KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC', 2) +KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL = enum_kfd_dbg_trap_address_watch_mode.define('KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL', 3) -# values for enumeration 'kfd_dbg_trap_wave_launch_mode' -kfd_dbg_trap_wave_launch_mode__enumvalues = { - 0: 'KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL', - 1: 'KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT', - 3: 'KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG', -} -KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL = 0 -KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT = 1 -KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG = 3 -kfd_dbg_trap_wave_launch_mode = ctypes.c_uint32 # enum +enum_kfd_dbg_trap_flags = CEnum(ctypes.c_uint32) +KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP = enum_kfd_dbg_trap_flags.define('KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP', 1) -# values for enumeration 'kfd_dbg_trap_address_watch_mode' -kfd_dbg_trap_address_watch_mode__enumvalues = { - 0: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ', - 1: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD', - 2: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC', - 3: 'KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL', -} -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ = 0 -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD = 1 -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC = 2 -KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL = 3 -kfd_dbg_trap_address_watch_mode = ctypes.c_uint32 # enum +enum_kfd_dbg_trap_exception_code = CEnum(ctypes.c_uint32) +EC_NONE = enum_kfd_dbg_trap_exception_code.define('EC_NONE', 0) +EC_QUEUE_WAVE_ABORT = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_WAVE_ABORT', 1) +EC_QUEUE_WAVE_TRAP = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_WAVE_TRAP', 2) +EC_QUEUE_WAVE_MATH_ERROR = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_WAVE_MATH_ERROR', 3) +EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION', 4) +EC_QUEUE_WAVE_MEMORY_VIOLATION = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_WAVE_MEMORY_VIOLATION', 5) +EC_QUEUE_WAVE_APERTURE_VIOLATION = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_WAVE_APERTURE_VIOLATION', 6) +EC_QUEUE_PACKET_DISPATCH_DIM_INVALID = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_DISPATCH_DIM_INVALID', 16) +EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID', 17) +EC_QUEUE_PACKET_DISPATCH_CODE_INVALID = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_DISPATCH_CODE_INVALID', 18) +EC_QUEUE_PACKET_RESERVED = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_RESERVED', 19) +EC_QUEUE_PACKET_UNSUPPORTED = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_UNSUPPORTED', 20) +EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID', 21) +EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID', 22) +EC_QUEUE_PACKET_VENDOR_UNSUPPORTED = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PACKET_VENDOR_UNSUPPORTED', 23) +EC_QUEUE_PREEMPTION_ERROR = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_PREEMPTION_ERROR', 30) +EC_QUEUE_NEW = enum_kfd_dbg_trap_exception_code.define('EC_QUEUE_NEW', 31) +EC_DEVICE_QUEUE_DELETE = enum_kfd_dbg_trap_exception_code.define('EC_DEVICE_QUEUE_DELETE', 32) +EC_DEVICE_MEMORY_VIOLATION = enum_kfd_dbg_trap_exception_code.define('EC_DEVICE_MEMORY_VIOLATION', 33) +EC_DEVICE_RAS_ERROR = enum_kfd_dbg_trap_exception_code.define('EC_DEVICE_RAS_ERROR', 34) +EC_DEVICE_FATAL_HALT = enum_kfd_dbg_trap_exception_code.define('EC_DEVICE_FATAL_HALT', 35) +EC_DEVICE_NEW = enum_kfd_dbg_trap_exception_code.define('EC_DEVICE_NEW', 36) +EC_PROCESS_RUNTIME = enum_kfd_dbg_trap_exception_code.define('EC_PROCESS_RUNTIME', 48) +EC_PROCESS_DEVICE_REMOVE = enum_kfd_dbg_trap_exception_code.define('EC_PROCESS_DEVICE_REMOVE', 49) +EC_MAX = enum_kfd_dbg_trap_exception_code.define('EC_MAX', 50) -# values for enumeration 'kfd_dbg_trap_flags' -kfd_dbg_trap_flags__enumvalues = { - 1: 'KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP', -} -KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP = 1 -kfd_dbg_trap_flags = ctypes.c_uint32 # enum +enum_kfd_dbg_runtime_state = CEnum(ctypes.c_uint32) +DEBUG_RUNTIME_STATE_DISABLED = enum_kfd_dbg_runtime_state.define('DEBUG_RUNTIME_STATE_DISABLED', 0) +DEBUG_RUNTIME_STATE_ENABLED = enum_kfd_dbg_runtime_state.define('DEBUG_RUNTIME_STATE_ENABLED', 1) +DEBUG_RUNTIME_STATE_ENABLED_BUSY = enum_kfd_dbg_runtime_state.define('DEBUG_RUNTIME_STATE_ENABLED_BUSY', 2) +DEBUG_RUNTIME_STATE_ENABLED_ERROR = enum_kfd_dbg_runtime_state.define('DEBUG_RUNTIME_STATE_ENABLED_ERROR', 3) -# values for enumeration 'kfd_dbg_trap_exception_code' -kfd_dbg_trap_exception_code__enumvalues = { - 0: 'EC_NONE', - 1: 'EC_QUEUE_WAVE_ABORT', - 2: 'EC_QUEUE_WAVE_TRAP', - 3: 'EC_QUEUE_WAVE_MATH_ERROR', - 4: 'EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION', - 5: 'EC_QUEUE_WAVE_MEMORY_VIOLATION', - 6: 'EC_QUEUE_WAVE_APERTURE_VIOLATION', - 16: 'EC_QUEUE_PACKET_DISPATCH_DIM_INVALID', - 17: 'EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID', - 18: 'EC_QUEUE_PACKET_DISPATCH_CODE_INVALID', - 19: 'EC_QUEUE_PACKET_RESERVED', - 20: 'EC_QUEUE_PACKET_UNSUPPORTED', - 21: 'EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID', - 22: 'EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID', - 23: 'EC_QUEUE_PACKET_VENDOR_UNSUPPORTED', - 30: 'EC_QUEUE_PREEMPTION_ERROR', - 31: 'EC_QUEUE_NEW', - 32: 'EC_DEVICE_QUEUE_DELETE', - 33: 'EC_DEVICE_MEMORY_VIOLATION', - 34: 'EC_DEVICE_RAS_ERROR', - 35: 'EC_DEVICE_FATAL_HALT', - 36: 'EC_DEVICE_NEW', - 48: 'EC_PROCESS_RUNTIME', - 49: 'EC_PROCESS_DEVICE_REMOVE', - 50: 'EC_MAX', -} -EC_NONE = 0 -EC_QUEUE_WAVE_ABORT = 1 -EC_QUEUE_WAVE_TRAP = 2 -EC_QUEUE_WAVE_MATH_ERROR = 3 -EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION = 4 -EC_QUEUE_WAVE_MEMORY_VIOLATION = 5 -EC_QUEUE_WAVE_APERTURE_VIOLATION = 6 -EC_QUEUE_PACKET_DISPATCH_DIM_INVALID = 16 -EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID = 17 -EC_QUEUE_PACKET_DISPATCH_CODE_INVALID = 18 -EC_QUEUE_PACKET_RESERVED = 19 -EC_QUEUE_PACKET_UNSUPPORTED = 20 -EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID = 21 -EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID = 22 -EC_QUEUE_PACKET_VENDOR_UNSUPPORTED = 23 -EC_QUEUE_PREEMPTION_ERROR = 30 -EC_QUEUE_NEW = 31 -EC_DEVICE_QUEUE_DELETE = 32 -EC_DEVICE_MEMORY_VIOLATION = 33 -EC_DEVICE_RAS_ERROR = 34 -EC_DEVICE_FATAL_HALT = 35 -EC_DEVICE_NEW = 36 -EC_PROCESS_RUNTIME = 48 -EC_PROCESS_DEVICE_REMOVE = 49 -EC_MAX = 50 -kfd_dbg_trap_exception_code = ctypes.c_uint32 # enum -KFD_EC_MASK_QUEUE = (KFD_EC_MASK(EC_QUEUE_WAVE_ABORT)|KFD_EC_MASK(EC_QUEUE_WAVE_TRAP)|KFD_EC_MASK(EC_QUEUE_WAVE_MATH_ERROR)|KFD_EC_MASK(EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION)|KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION)|KFD_EC_MASK(EC_QUEUE_WAVE_APERTURE_VIOLATION)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_DIM_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_CODE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_RESERVED)|KFD_EC_MASK(EC_QUEUE_PACKET_UNSUPPORTED)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_VENDOR_UNSUPPORTED)|KFD_EC_MASK(EC_QUEUE_PREEMPTION_ERROR)|KFD_EC_MASK(EC_QUEUE_NEW)) # macro -KFD_EC_MASK_DEVICE = (KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE)|KFD_EC_MASK(EC_DEVICE_RAS_ERROR)|KFD_EC_MASK(EC_DEVICE_FATAL_HALT)|KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION)|KFD_EC_MASK(EC_DEVICE_NEW)) # macro -KFD_EC_MASK_PROCESS = (KFD_EC_MASK(EC_PROCESS_RUNTIME)|KFD_EC_MASK(EC_PROCESS_DEVICE_REMOVE)) # macro -KFD_EC_MASK_PACKET = (KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_DIM_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_GROUP_SEGMENT_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_CODE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_RESERVED)|KFD_EC_MASK(EC_QUEUE_PACKET_UNSUPPORTED)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_WORK_GROUP_SIZE_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_DISPATCH_REGISTER_INVALID)|KFD_EC_MASK(EC_QUEUE_PACKET_VENDOR_UNSUPPORTED)) # macro -def KFD_DBG_EC_IS_VALID(ecode): # macro - return (ecode>EC_NONE and ecode EC_NONE and ecode < EC_MAX) +KFD_DBG_EC_TYPE_IS_QUEUE = lambda ecode: (KFD_DBG_EC_IS_VALID(ecode) and not not (KFD_EC_MASK(ecode) & KFD_EC_MASK_QUEUE)) +KFD_DBG_EC_TYPE_IS_DEVICE = lambda ecode: (KFD_DBG_EC_IS_VALID(ecode) and not not (KFD_EC_MASK(ecode) & KFD_EC_MASK_DEVICE)) +KFD_DBG_EC_TYPE_IS_PROCESS = lambda ecode: (KFD_DBG_EC_IS_VALID(ecode) and not not (KFD_EC_MASK(ecode) & KFD_EC_MASK_PROCESS)) +KFD_DBG_EC_TYPE_IS_PACKET = lambda ecode: (KFD_DBG_EC_IS_VALID(ecode) and not not (KFD_EC_MASK(ecode) & KFD_EC_MASK_PACKET)) +KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK = 1 +KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK = 2 +KFD_DBG_QUEUE_ERROR_BIT = 30 +KFD_DBG_QUEUE_INVALID_BIT = 31 +KFD_DBG_QUEUE_ERROR_MASK = (1 << KFD_DBG_QUEUE_ERROR_BIT) +KFD_DBG_QUEUE_INVALID_MASK = (1 << KFD_DBG_QUEUE_INVALID_BIT) +AMDKFD_IOCTL_BASE = 'K' +AMDKFD_IO = lambda nr: _IO(AMDKFD_IOCTL_BASE, nr) +AMDKFD_IOR = lambda nr,type: _IOR(AMDKFD_IOCTL_BASE, nr, type) +AMDKFD_IOW = lambda nr,type: _IOW(AMDKFD_IOCTL_BASE, nr, type) +AMDKFD_IOWR = lambda nr,type: _IOWR(AMDKFD_IOCTL_BASE, nr, type) +AMDKFD_IOC_GET_VERSION = AMDKFD_IOR(0x01, struct_kfd_ioctl_get_version_args) +AMDKFD_IOC_CREATE_QUEUE = AMDKFD_IOWR(0x02, struct_kfd_ioctl_create_queue_args) +AMDKFD_IOC_DESTROY_QUEUE = AMDKFD_IOWR(0x03, struct_kfd_ioctl_destroy_queue_args) +AMDKFD_IOC_SET_MEMORY_POLICY = AMDKFD_IOW(0x04, struct_kfd_ioctl_set_memory_policy_args) +AMDKFD_IOC_GET_CLOCK_COUNTERS = AMDKFD_IOWR(0x05, struct_kfd_ioctl_get_clock_counters_args) +AMDKFD_IOC_GET_PROCESS_APERTURES = AMDKFD_IOR(0x06, struct_kfd_ioctl_get_process_apertures_args) +AMDKFD_IOC_UPDATE_QUEUE = AMDKFD_IOW(0x07, struct_kfd_ioctl_update_queue_args) +AMDKFD_IOC_CREATE_EVENT = AMDKFD_IOWR(0x08, struct_kfd_ioctl_create_event_args) +AMDKFD_IOC_DESTROY_EVENT = AMDKFD_IOW(0x09, struct_kfd_ioctl_destroy_event_args) +AMDKFD_IOC_SET_EVENT = AMDKFD_IOW(0x0A, struct_kfd_ioctl_set_event_args) +AMDKFD_IOC_RESET_EVENT = AMDKFD_IOW(0x0B, struct_kfd_ioctl_reset_event_args) +AMDKFD_IOC_WAIT_EVENTS = AMDKFD_IOWR(0x0C, struct_kfd_ioctl_wait_events_args) +AMDKFD_IOC_DBG_REGISTER_DEPRECATED = AMDKFD_IOW(0x0D, struct_kfd_ioctl_dbg_register_args) +AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED = AMDKFD_IOW(0x0E, struct_kfd_ioctl_dbg_unregister_args) +AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED = AMDKFD_IOW(0x0F, struct_kfd_ioctl_dbg_address_watch_args) +AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED = AMDKFD_IOW(0x10, struct_kfd_ioctl_dbg_wave_control_args) +AMDKFD_IOC_SET_SCRATCH_BACKING_VA = AMDKFD_IOWR(0x11, struct_kfd_ioctl_set_scratch_backing_va_args) +AMDKFD_IOC_GET_TILE_CONFIG = AMDKFD_IOWR(0x12, struct_kfd_ioctl_get_tile_config_args) +AMDKFD_IOC_SET_TRAP_HANDLER = AMDKFD_IOW(0x13, struct_kfd_ioctl_set_trap_handler_args) +AMDKFD_IOC_GET_PROCESS_APERTURES_NEW = AMDKFD_IOWR(0x14, struct_kfd_ioctl_get_process_apertures_new_args) +AMDKFD_IOC_ACQUIRE_VM = AMDKFD_IOW(0x15, struct_kfd_ioctl_acquire_vm_args) +AMDKFD_IOC_ALLOC_MEMORY_OF_GPU = AMDKFD_IOWR(0x16, struct_kfd_ioctl_alloc_memory_of_gpu_args) +AMDKFD_IOC_FREE_MEMORY_OF_GPU = AMDKFD_IOW(0x17, struct_kfd_ioctl_free_memory_of_gpu_args) +AMDKFD_IOC_MAP_MEMORY_TO_GPU = AMDKFD_IOWR(0x18, struct_kfd_ioctl_map_memory_to_gpu_args) +AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU = AMDKFD_IOWR(0x19, struct_kfd_ioctl_unmap_memory_from_gpu_args) +AMDKFD_IOC_SET_CU_MASK = AMDKFD_IOW(0x1A, struct_kfd_ioctl_set_cu_mask_args) +AMDKFD_IOC_GET_QUEUE_WAVE_STATE = AMDKFD_IOWR(0x1B, struct_kfd_ioctl_get_queue_wave_state_args) +AMDKFD_IOC_GET_DMABUF_INFO = AMDKFD_IOWR(0x1C, struct_kfd_ioctl_get_dmabuf_info_args) +AMDKFD_IOC_IMPORT_DMABUF = AMDKFD_IOWR(0x1D, struct_kfd_ioctl_import_dmabuf_args) +AMDKFD_IOC_ALLOC_QUEUE_GWS = AMDKFD_IOWR(0x1E, struct_kfd_ioctl_alloc_queue_gws_args) +AMDKFD_IOC_SMI_EVENTS = AMDKFD_IOWR(0x1F, struct_kfd_ioctl_smi_events_args) +AMDKFD_IOC_SVM = AMDKFD_IOWR(0x20, struct_kfd_ioctl_svm_args) +AMDKFD_IOC_SET_XNACK_MODE = AMDKFD_IOWR(0x21, struct_kfd_ioctl_set_xnack_mode_args) +AMDKFD_IOC_CRIU_OP = AMDKFD_IOWR(0x22, struct_kfd_ioctl_criu_args) +AMDKFD_IOC_AVAILABLE_MEMORY = AMDKFD_IOWR(0x23, struct_kfd_ioctl_get_available_memory_args) +AMDKFD_IOC_EXPORT_DMABUF = AMDKFD_IOWR(0x24, struct_kfd_ioctl_export_dmabuf_args) +AMDKFD_IOC_RUNTIME_ENABLE = AMDKFD_IOWR(0x25, struct_kfd_ioctl_runtime_enable_args) +AMDKFD_IOC_DBG_TRAP = AMDKFD_IOWR(0x26, struct_kfd_ioctl_dbg_trap_args) +AMDKFD_COMMAND_START = 0x01 +AMDKFD_COMMAND_END = 0x27 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/kgsl.py b/tinygrad/runtime/autogen/kgsl.py index cc6f121c49..da42cda247 100644 --- a/tinygrad/runtime/autogen/kgsl.py +++ b/tinygrad/runtime/autogen/kgsl.py @@ -1,1388 +1,741 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +enum_kgsl_user_mem_type = CEnum(ctypes.c_uint32) +KGSL_USER_MEM_TYPE_PMEM = enum_kgsl_user_mem_type.define('KGSL_USER_MEM_TYPE_PMEM', 0) +KGSL_USER_MEM_TYPE_ASHMEM = enum_kgsl_user_mem_type.define('KGSL_USER_MEM_TYPE_ASHMEM', 1) +KGSL_USER_MEM_TYPE_ADDR = enum_kgsl_user_mem_type.define('KGSL_USER_MEM_TYPE_ADDR', 2) +KGSL_USER_MEM_TYPE_ION = enum_kgsl_user_mem_type.define('KGSL_USER_MEM_TYPE_ION', 3) +KGSL_USER_MEM_TYPE_DMABUF = enum_kgsl_user_mem_type.define('KGSL_USER_MEM_TYPE_DMABUF', 3) +KGSL_USER_MEM_TYPE_MAX = enum_kgsl_user_mem_type.define('KGSL_USER_MEM_TYPE_MAX', 7) +enum_kgsl_ctx_reset_stat = CEnum(ctypes.c_uint32) +KGSL_CTX_STAT_NO_ERROR = enum_kgsl_ctx_reset_stat.define('KGSL_CTX_STAT_NO_ERROR', 0) +KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = enum_kgsl_ctx_reset_stat.define('KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', 1) +KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = enum_kgsl_ctx_reset_stat.define('KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', 2) +KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = enum_kgsl_ctx_reset_stat.define('KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', 3) -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result +enum_kgsl_deviceid = CEnum(ctypes.c_uint32) +KGSL_DEVICE_3D0 = enum_kgsl_deviceid.define('KGSL_DEVICE_3D0', 0) +KGSL_DEVICE_MAX = enum_kgsl_deviceid.define('KGSL_DEVICE_MAX', 1) - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - -import fcntl, functools - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, __payload=None, **kwargs): - ret = __fd.ioctl((__idir<<30) | (ctypes.sizeof(made := (__payload or __user_struct(**kwargs)))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl, 0, ord(base) if isinstance(base, str) else base, nr, None) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - - - -_UAPI_MSM_KGSL_H = True # macro -size_t = True # macro -uint64_t = True # macro -KGSL_VERSION_MAJOR = 3 # macro -KGSL_VERSION_MINOR = 14 # macro -KGSL_CONTEXT_SAVE_GMEM = 0x00000001 # macro -KGSL_CONTEXT_NO_GMEM_ALLOC = 0x00000002 # macro -KGSL_CONTEXT_SUBMIT_IB_LIST = 0x00000004 # macro -KGSL_CONTEXT_CTX_SWITCH = 0x00000008 # macro -KGSL_CONTEXT_PREAMBLE = 0x00000010 # macro -KGSL_CONTEXT_TRASH_STATE = 0x00000020 # macro -KGSL_CONTEXT_PER_CONTEXT_TS = 0x00000040 # macro -KGSL_CONTEXT_USER_GENERATED_TS = 0x00000080 # macro -KGSL_CONTEXT_END_OF_FRAME = 0x00000100 # macro -KGSL_CONTEXT_NO_FAULT_TOLERANCE = 0x00000200 # macro -KGSL_CONTEXT_SYNC = 0x00000400 # macro -KGSL_CONTEXT_PWR_CONSTRAINT = 0x00000800 # macro -KGSL_CONTEXT_PRIORITY_MASK = 0x0000F000 # macro -KGSL_CONTEXT_PRIORITY_SHIFT = 12 # macro -KGSL_CONTEXT_PRIORITY_UNDEF = 0 # macro -KGSL_CONTEXT_IFH_NOP = 0x00010000 # macro -KGSL_CONTEXT_SECURE = 0x00020000 # macro -KGSL_CONTEXT_PREEMPT_STYLE_MASK = 0x0E000000 # macro -KGSL_CONTEXT_PREEMPT_STYLE_SHIFT = 25 # macro -KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT = 0x0 # macro -KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER = 0x1 # macro -KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN = 0x2 # macro -KGSL_CONTEXT_TYPE_MASK = 0x01F00000 # macro -KGSL_CONTEXT_TYPE_SHIFT = 20 # macro -KGSL_CONTEXT_TYPE_ANY = 0 # macro -KGSL_CONTEXT_TYPE_GL = 1 # macro -KGSL_CONTEXT_TYPE_CL = 2 # macro -KGSL_CONTEXT_TYPE_C2D = 3 # macro -KGSL_CONTEXT_TYPE_RS = 4 # macro -KGSL_CONTEXT_TYPE_UNKNOWN = 0x1E # macro -KGSL_CONTEXT_INVALID = 0xffffffff # macro -KGSL_CMDBATCH_MEMLIST = 0x00000001 # macro -KGSL_CMDBATCH_MARKER = 0x00000002 # macro -KGSL_CMDBATCH_SUBMIT_IB_LIST = 0x00000004 # macro -KGSL_CMDBATCH_CTX_SWITCH = 0x00000008 # macro -KGSL_CMDBATCH_PROFILING = 0x00000010 # macro -KGSL_CMDBATCH_PROFILING_KTIME = 0x00000020 # macro -KGSL_CMDBATCH_END_OF_FRAME = 0x00000100 # macro -KGSL_CMDBATCH_SYNC = 0x00000400 # macro -KGSL_CMDBATCH_PWR_CONSTRAINT = 0x00000800 # macro -KGSL_CMDLIST_IB = 0x00000001 # macro -KGSL_CMDLIST_CTXTSWITCH_PREAMBLE = 0x00000002 # macro -KGSL_CMDLIST_IB_PREAMBLE = 0x00000004 # macro -KGSL_OBJLIST_MEMOBJ = 0x00000008 # macro -KGSL_OBJLIST_PROFILE = 0x00000010 # macro -KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP = 0 # macro -KGSL_CMD_SYNCPOINT_TYPE_FENCE = 1 # macro -KGSL_MEMFLAGS_SECURE = 0x00000008 # macro -KGSL_MEMFLAGS_GPUREADONLY = 0x01000000 # macro -KGSL_MEMFLAGS_GPUWRITEONLY = 0x02000000 # macro -KGSL_MEMFLAGS_FORCE_32BIT = 0x100000000 # macro -KGSL_CACHEMODE_MASK = 0x0C000000 # macro -KGSL_CACHEMODE_SHIFT = 26 # macro -KGSL_CACHEMODE_WRITECOMBINE = 0 # macro -KGSL_CACHEMODE_UNCACHED = 1 # macro -KGSL_CACHEMODE_WRITETHROUGH = 2 # macro -KGSL_CACHEMODE_WRITEBACK = 3 # macro -KGSL_MEMFLAGS_USE_CPU_MAP = 0x10000000 # macro -KGSL_MEMTYPE_MASK = 0x0000FF00 # macro -KGSL_MEMTYPE_SHIFT = 8 # macro -KGSL_MEMTYPE_OBJECTANY = 0 # macro -KGSL_MEMTYPE_FRAMEBUFFER = 1 # macro -KGSL_MEMTYPE_RENDERBUFFER = 2 # macro -KGSL_MEMTYPE_ARRAYBUFFER = 3 # macro -KGSL_MEMTYPE_ELEMENTARRAYBUFFER = 4 # macro -KGSL_MEMTYPE_VERTEXARRAYBUFFER = 5 # macro -KGSL_MEMTYPE_TEXTURE = 6 # macro -KGSL_MEMTYPE_SURFACE = 7 # macro -KGSL_MEMTYPE_EGL_SURFACE = 8 # macro -KGSL_MEMTYPE_GL = 9 # macro -KGSL_MEMTYPE_CL = 10 # macro -KGSL_MEMTYPE_CL_BUFFER_MAP = 11 # macro -KGSL_MEMTYPE_CL_BUFFER_NOMAP = 12 # macro -KGSL_MEMTYPE_CL_IMAGE_MAP = 13 # macro -KGSL_MEMTYPE_CL_IMAGE_NOMAP = 14 # macro -KGSL_MEMTYPE_CL_KERNEL_STACK = 15 # macro -KGSL_MEMTYPE_COMMAND = 16 # macro -KGSL_MEMTYPE_2D = 17 # macro -KGSL_MEMTYPE_EGL_IMAGE = 18 # macro -KGSL_MEMTYPE_EGL_SHADOW = 19 # macro -KGSL_MEMTYPE_MULTISAMPLE = 20 # macro -KGSL_MEMTYPE_KERNEL = 255 # macro -KGSL_MEMALIGN_MASK = 0x00FF0000 # macro -KGSL_MEMALIGN_SHIFT = 16 # macro -KGSL_MEMFLAGS_USERMEM_MASK = 0x000000e0 # macro -KGSL_MEMFLAGS_USERMEM_SHIFT = 5 # macro -def KGSL_USERMEM_FLAG(x): # macro - return (((x)+1)<<5) -KGSL_MEMFLAGS_NOT_USERMEM = 0 # macro -KGSL_FLAGS_NORMALMODE = 0x00000000 # macro -KGSL_FLAGS_SAFEMODE = 0x00000001 # macro -KGSL_FLAGS_INITIALIZED0 = 0x00000002 # macro -KGSL_FLAGS_INITIALIZED = 0x00000004 # macro -KGSL_FLAGS_STARTED = 0x00000008 # macro -KGSL_FLAGS_ACTIVE = 0x00000010 # macro -KGSL_FLAGS_RESERVED0 = 0x00000020 # macro -KGSL_FLAGS_RESERVED1 = 0x00000040 # macro -KGSL_FLAGS_RESERVED2 = 0x00000080 # macro -KGSL_FLAGS_SOFT_RESET = 0x00000100 # macro -KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS = 0x00000200 # macro -KGSL_SYNCOBJ_SERVER_TIMEOUT = 2000 # macro -def KGSL_CONVERT_TO_MBPS(val): # macro - return (val*1000*1000) -KGSL_PROP_DEVICE_INFO = 0x1 # macro -KGSL_PROP_DEVICE_SHADOW = 0x2 # macro -KGSL_PROP_DEVICE_POWER = 0x3 # macro -KGSL_PROP_SHMEM = 0x4 # macro -KGSL_PROP_SHMEM_APERTURES = 0x5 # macro -KGSL_PROP_MMU_ENABLE = 0x6 # macro -KGSL_PROP_INTERRUPT_WAITS = 0x7 # macro -KGSL_PROP_VERSION = 0x8 # macro -KGSL_PROP_GPU_RESET_STAT = 0x9 # macro -KGSL_PROP_PWRCTRL = 0xE # macro -KGSL_PROP_PWR_CONSTRAINT = 0x12 # macro -KGSL_PROP_UCHE_GMEM_VADDR = 0x13 # macro -KGSL_PROP_SP_GENERIC_MEM = 0x14 # macro -KGSL_PROP_UCODE_VERSION = 0x15 # macro -KGSL_PROP_GPMU_VERSION = 0x16 # macro -KGSL_PROP_DEVICE_BITNESS = 0x18 # macro -KGSL_PERFCOUNTER_GROUP_CP = 0x0 # macro -KGSL_PERFCOUNTER_GROUP_RBBM = 0x1 # macro -KGSL_PERFCOUNTER_GROUP_PC = 0x2 # macro -KGSL_PERFCOUNTER_GROUP_VFD = 0x3 # macro -KGSL_PERFCOUNTER_GROUP_HLSQ = 0x4 # macro -KGSL_PERFCOUNTER_GROUP_VPC = 0x5 # macro -KGSL_PERFCOUNTER_GROUP_TSE = 0x6 # macro -KGSL_PERFCOUNTER_GROUP_RAS = 0x7 # macro -KGSL_PERFCOUNTER_GROUP_UCHE = 0x8 # macro -KGSL_PERFCOUNTER_GROUP_TP = 0x9 # macro -KGSL_PERFCOUNTER_GROUP_SP = 0xA # macro -KGSL_PERFCOUNTER_GROUP_RB = 0xB # macro -KGSL_PERFCOUNTER_GROUP_PWR = 0xC # macro -KGSL_PERFCOUNTER_GROUP_VBIF = 0xD # macro -KGSL_PERFCOUNTER_GROUP_VBIF_PWR = 0xE # macro -KGSL_PERFCOUNTER_GROUP_MH = 0xF # macro -KGSL_PERFCOUNTER_GROUP_PA_SU = 0x10 # macro -KGSL_PERFCOUNTER_GROUP_SQ = 0x11 # macro -KGSL_PERFCOUNTER_GROUP_SX = 0x12 # macro -KGSL_PERFCOUNTER_GROUP_TCF = 0x13 # macro -KGSL_PERFCOUNTER_GROUP_TCM = 0x14 # macro -KGSL_PERFCOUNTER_GROUP_TCR = 0x15 # macro -KGSL_PERFCOUNTER_GROUP_L2 = 0x16 # macro -KGSL_PERFCOUNTER_GROUP_VSC = 0x17 # macro -KGSL_PERFCOUNTER_GROUP_CCU = 0x18 # macro -KGSL_PERFCOUNTER_GROUP_LRZ = 0x19 # macro -KGSL_PERFCOUNTER_GROUP_CMP = 0x1A # macro -KGSL_PERFCOUNTER_GROUP_ALWAYSON = 0x1B # macro -KGSL_PERFCOUNTER_GROUP_SP_PWR = 0x1C # macro -KGSL_PERFCOUNTER_GROUP_TP_PWR = 0x1D # macro -KGSL_PERFCOUNTER_GROUP_RB_PWR = 0x1E # macro -KGSL_PERFCOUNTER_GROUP_CCU_PWR = 0x1F # macro -KGSL_PERFCOUNTER_GROUP_UCHE_PWR = 0x20 # macro -KGSL_PERFCOUNTER_GROUP_CP_PWR = 0x21 # macro -KGSL_PERFCOUNTER_GROUP_GPMU_PWR = 0x22 # macro -KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR = 0x23 # macro -KGSL_PERFCOUNTER_GROUP_MAX = 0x24 # macro -KGSL_PERFCOUNTER_NOT_USED = 0xFFFFFFFF # macro -KGSL_PERFCOUNTER_BROKEN = 0xFFFFFFFE # macro -KGSL_IOC_TYPE = 0x09 # macro -KGSL_TIMESTAMP_EVENT_GENLOCK = 1 # macro -KGSL_TIMESTAMP_EVENT_FENCE = 2 # macro -KGSL_GPUMEM_CACHE_CLEAN = (1<<0) # macro -KGSL_GPUMEM_CACHE_TO_GPU = (1<<0) # macro -KGSL_GPUMEM_CACHE_INV = (1<<1) # macro -KGSL_GPUMEM_CACHE_FROM_GPU = (1<<1) # macro -KGSL_GPUMEM_CACHE_FLUSH = ((1<<0)|(1<<1)) # macro -KGSL_GPUMEM_CACHE_RANGE = (1<<31) # macro -KGSL_IBDESC_MEMLIST = 0x1 # macro -KGSL_IBDESC_PROFILING_BUFFER = 0x2 # macro -KGSL_CONSTRAINT_NONE = 0 # macro -KGSL_CONSTRAINT_PWRLEVEL = 1 # macro -KGSL_CONSTRAINT_PWR_MIN = 0 # macro -KGSL_CONSTRAINT_PWR_MAX = 1 # macro -KGSL_GPUOBJ_ALLOC_METADATA_MAX = 64 # macro -KGSL_GPUOBJ_FREE_ON_EVENT = 1 # macro -KGSL_GPU_EVENT_TIMESTAMP = 1 # macro -KGSL_GPU_EVENT_FENCE = 2 # macro -KGSL_GPUOBJ_SET_INFO_METADATA = (1<<0) # macro -KGSL_GPUOBJ_SET_INFO_TYPE = (1<<1) # macro - -# values for enumeration 'kgsl_user_mem_type' -kgsl_user_mem_type__enumvalues = { - 0: 'KGSL_USER_MEM_TYPE_PMEM', - 1: 'KGSL_USER_MEM_TYPE_ASHMEM', - 2: 'KGSL_USER_MEM_TYPE_ADDR', - 3: 'KGSL_USER_MEM_TYPE_ION', - 3: 'KGSL_USER_MEM_TYPE_DMABUF', - 7: 'KGSL_USER_MEM_TYPE_MAX', -} -KGSL_USER_MEM_TYPE_PMEM = 0 -KGSL_USER_MEM_TYPE_ASHMEM = 1 -KGSL_USER_MEM_TYPE_ADDR = 2 -KGSL_USER_MEM_TYPE_ION = 3 -KGSL_USER_MEM_TYPE_DMABUF = 3 -KGSL_USER_MEM_TYPE_MAX = 7 -kgsl_user_mem_type = ctypes.c_uint32 # enum -KGSL_MEMFLAGS_USERMEM_PMEM = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_PMEM ) # macro (from list) -KGSL_MEMFLAGS_USERMEM_ASHMEM = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_ASHMEM ) # macro (from list) -KGSL_MEMFLAGS_USERMEM_ADDR = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_ADDR ) # macro (from list) -KGSL_MEMFLAGS_USERMEM_ION = KGSL_USERMEM_FLAG ( KGSL_USER_MEM_TYPE_ION ) # macro (from list) - -# values for enumeration 'kgsl_ctx_reset_stat' -kgsl_ctx_reset_stat__enumvalues = { - 0: 'KGSL_CTX_STAT_NO_ERROR', - 1: 'KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', - 2: 'KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', - 3: 'KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', -} -KGSL_CTX_STAT_NO_ERROR = 0 -KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 1 -KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 2 -KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 3 -kgsl_ctx_reset_stat = ctypes.c_uint32 # enum - -# values for enumeration 'kgsl_deviceid' -kgsl_deviceid__enumvalues = { - 0: 'KGSL_DEVICE_3D0', - 1: 'KGSL_DEVICE_MAX', -} -KGSL_DEVICE_3D0 = 0 -KGSL_DEVICE_MAX = 1 -kgsl_deviceid = ctypes.c_uint32 # enum -class struct_kgsl_devinfo(Structure): - pass - -struct_kgsl_devinfo._pack_ = 1 # source:False +class struct_kgsl_devinfo(Struct): pass struct_kgsl_devinfo._fields_ = [ - ('device_id', ctypes.c_uint32), - ('chip_id', ctypes.c_uint32), - ('mmu_enabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gmem_gpubaseaddr', ctypes.c_uint64), - ('gpu_id', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('gmem_sizebytes', ctypes.c_uint64), + ('device_id', ctypes.c_uint32), + ('chip_id', ctypes.c_uint32), + ('mmu_enabled', ctypes.c_uint32), + ('gmem_gpubaseaddr', ctypes.c_uint64), + ('gpu_id', ctypes.c_uint32), + ('gmem_sizebytes', ctypes.c_uint64), ] - -class struct_kgsl_devmemstore(Structure): - pass - -struct_kgsl_devmemstore._pack_ = 1 # source:False +class struct_kgsl_devmemstore(Struct): pass struct_kgsl_devmemstore._fields_ = [ - ('soptimestamp', ctypes.c_uint32), - ('sbz', ctypes.c_uint32), - ('eoptimestamp', ctypes.c_uint32), - ('sbz2', ctypes.c_uint32), - ('preempted', ctypes.c_uint32), - ('sbz3', ctypes.c_uint32), - ('ref_wait_ts', ctypes.c_uint32), - ('sbz4', ctypes.c_uint32), - ('current_context', ctypes.c_uint32), - ('sbz5', ctypes.c_uint32), + ('soptimestamp', ctypes.c_uint32), + ('sbz', ctypes.c_uint32), + ('eoptimestamp', ctypes.c_uint32), + ('sbz2', ctypes.c_uint32), + ('preempted', ctypes.c_uint32), + ('sbz3', ctypes.c_uint32), + ('ref_wait_ts', ctypes.c_uint32), + ('sbz4', ctypes.c_uint32), + ('current_context', ctypes.c_uint32), + ('sbz5', ctypes.c_uint32), ] +enum_kgsl_timestamp_type = CEnum(ctypes.c_uint32) +KGSL_TIMESTAMP_CONSUMED = enum_kgsl_timestamp_type.define('KGSL_TIMESTAMP_CONSUMED', 1) +KGSL_TIMESTAMP_RETIRED = enum_kgsl_timestamp_type.define('KGSL_TIMESTAMP_RETIRED', 2) +KGSL_TIMESTAMP_QUEUED = enum_kgsl_timestamp_type.define('KGSL_TIMESTAMP_QUEUED', 3) -# def KGSL_MEMSTORE_OFFSET(ctxt_id, field): # macro -# return ((ctxt_id)*ctypes.sizeof(struct_kgsl_devmemstore)+offsetof(struct_kgsl_devmemstore,field)) - -# values for enumeration 'kgsl_timestamp_type' -kgsl_timestamp_type__enumvalues = { - 1: 'KGSL_TIMESTAMP_CONSUMED', - 2: 'KGSL_TIMESTAMP_RETIRED', - 3: 'KGSL_TIMESTAMP_QUEUED', -} -KGSL_TIMESTAMP_CONSUMED = 1 -KGSL_TIMESTAMP_RETIRED = 2 -KGSL_TIMESTAMP_QUEUED = 3 -kgsl_timestamp_type = ctypes.c_uint32 # enum -class struct_kgsl_shadowprop(Structure): - pass - -struct_kgsl_shadowprop._pack_ = 1 # source:False +class struct_kgsl_shadowprop(Struct): pass struct_kgsl_shadowprop._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('gpuaddr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), ] - -class struct_kgsl_version(Structure): - pass - -struct_kgsl_version._pack_ = 1 # source:False +class struct_kgsl_version(Struct): pass struct_kgsl_version._fields_ = [ - ('drv_major', ctypes.c_uint32), - ('drv_minor', ctypes.c_uint32), - ('dev_major', ctypes.c_uint32), - ('dev_minor', ctypes.c_uint32), + ('drv_major', ctypes.c_uint32), + ('drv_minor', ctypes.c_uint32), + ('dev_major', ctypes.c_uint32), + ('dev_minor', ctypes.c_uint32), ] - -class struct_kgsl_sp_generic_mem(Structure): - pass - -struct_kgsl_sp_generic_mem._pack_ = 1 # source:False +class struct_kgsl_sp_generic_mem(Struct): pass struct_kgsl_sp_generic_mem._fields_ = [ - ('local', ctypes.c_uint64), - ('pvt', ctypes.c_uint64), + ('local', ctypes.c_uint64), + ('pvt', ctypes.c_uint64), ] - -class struct_kgsl_ucode_version(Structure): - pass - -struct_kgsl_ucode_version._pack_ = 1 # source:False +class struct_kgsl_ucode_version(Struct): pass struct_kgsl_ucode_version._fields_ = [ - ('pfp', ctypes.c_uint32), - ('pm4', ctypes.c_uint32), + ('pfp', ctypes.c_uint32), + ('pm4', ctypes.c_uint32), ] - -class struct_kgsl_gpmu_version(Structure): - pass - -struct_kgsl_gpmu_version._pack_ = 1 # source:False +class struct_kgsl_gpmu_version(Struct): pass struct_kgsl_gpmu_version._fields_ = [ - ('major', ctypes.c_uint32), - ('minor', ctypes.c_uint32), - ('features', ctypes.c_uint32), + ('major', ctypes.c_uint32), + ('minor', ctypes.c_uint32), + ('features', ctypes.c_uint32), ] - -class struct_kgsl_ibdesc(Structure): - pass - -struct_kgsl_ibdesc._pack_ = 1 # source:False +class struct_kgsl_ibdesc(Struct): pass struct_kgsl_ibdesc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64), - ('sizedwords', ctypes.c_uint64), - ('ctrl', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('gpuaddr', ctypes.c_uint64), + ('__pad', ctypes.c_uint64), + ('sizedwords', ctypes.c_uint64), + ('ctrl', ctypes.c_uint32), ] - -class struct_kgsl_cmdbatch_profiling_buffer(Structure): - pass - -struct_kgsl_cmdbatch_profiling_buffer._pack_ = 1 # source:False +class struct_kgsl_cmdbatch_profiling_buffer(Struct): pass struct_kgsl_cmdbatch_profiling_buffer._fields_ = [ - ('wall_clock_s', ctypes.c_uint64), - ('wall_clock_ns', ctypes.c_uint64), - ('gpu_ticks_queued', ctypes.c_uint64), - ('gpu_ticks_submitted', ctypes.c_uint64), - ('gpu_ticks_retired', ctypes.c_uint64), + ('wall_clock_s', ctypes.c_uint64), + ('wall_clock_ns', ctypes.c_uint64), + ('gpu_ticks_queued', ctypes.c_uint64), + ('gpu_ticks_submitted', ctypes.c_uint64), + ('gpu_ticks_retired', ctypes.c_uint64), ] - -class struct_kgsl_device_getproperty(Structure): - pass - -struct_kgsl_device_getproperty._pack_ = 1 # source:False +class struct_kgsl_device_getproperty(Struct): pass struct_kgsl_device_getproperty._fields_ = [ - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('value', ctypes.POINTER(None)), - ('sizebytes', ctypes.c_uint64), + ('type', ctypes.c_uint32), + ('value', ctypes.c_void_p), + ('sizebytes', ctypes.c_uint64), ] - -IOCTL_KGSL_DEVICE_GETPROPERTY = _IOWR ( 0x09 , 0x2 , struct_kgsl_device_getproperty ) # macro (from list) -IOCTL_KGSL_SETPROPERTY = _IOW ( 0x09 , 0x32 , struct_kgsl_device_getproperty ) # macro (from list) -class struct_kgsl_device_waittimestamp(Structure): - pass - -struct_kgsl_device_waittimestamp._pack_ = 1 # source:False +class struct_kgsl_device_waittimestamp(Struct): pass struct_kgsl_device_waittimestamp._fields_ = [ - ('timestamp', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), + ('timeout', ctypes.c_uint32), ] - -IOCTL_KGSL_DEVICE_WAITTIMESTAMP = _IOW ( 0x09 , 0x6 , struct_kgsl_device_waittimestamp ) # macro (from list) -class struct_kgsl_device_waittimestamp_ctxtid(Structure): - pass - -struct_kgsl_device_waittimestamp_ctxtid._pack_ = 1 # source:False +class struct_kgsl_device_waittimestamp_ctxtid(Struct): pass struct_kgsl_device_waittimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), + ('timeout', ctypes.c_uint32), ] - -IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID = _IOW ( 0x09 , 0x7 , struct_kgsl_device_waittimestamp_ctxtid ) # macro (from list) -class struct_kgsl_ringbuffer_issueibcmds(Structure): - pass - -struct_kgsl_ringbuffer_issueibcmds._pack_ = 1 # source:False +class struct_kgsl_ringbuffer_issueibcmds(Struct): pass struct_kgsl_ringbuffer_issueibcmds._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ibdesc_addr', ctypes.c_uint64), - ('numibs', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('drawctxt_id', ctypes.c_uint32), + ('ibdesc_addr', ctypes.c_uint64), + ('numibs', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), + ('flags', ctypes.c_uint32), ] - -IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS = _IOWR ( 0x09 , 0x10 , struct_kgsl_ringbuffer_issueibcmds ) # macro (from list) -class struct_kgsl_cmdstream_readtimestamp(Structure): - pass - -struct_kgsl_cmdstream_readtimestamp._pack_ = 1 # source:False +class struct_kgsl_cmdstream_readtimestamp(Struct): pass struct_kgsl_cmdstream_readtimestamp._fields_ = [ - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('type', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD = _IOR ( 0x09 , 0x11 , struct_kgsl_cmdstream_readtimestamp ) # macro (from list) -IOCTL_KGSL_CMDSTREAM_READTIMESTAMP = _IOWR ( 0x09 , 0x11 , struct_kgsl_cmdstream_readtimestamp ) # macro (from list) -class struct_kgsl_cmdstream_freememontimestamp(Structure): - pass - -struct_kgsl_cmdstream_freememontimestamp._pack_ = 1 # source:False +class struct_kgsl_cmdstream_freememontimestamp(Struct): pass struct_kgsl_cmdstream_freememontimestamp._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('gpuaddr', ctypes.c_uint64), + ('type', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP = _IOW ( 0x09 , 0x12 , struct_kgsl_cmdstream_freememontimestamp ) # macro (from list) -IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD = _IOR ( 0x09 , 0x12 , struct_kgsl_cmdstream_freememontimestamp ) # macro (from list) -class struct_kgsl_drawctxt_create(Structure): - pass - -struct_kgsl_drawctxt_create._pack_ = 1 # source:False +class struct_kgsl_drawctxt_create(Struct): pass struct_kgsl_drawctxt_create._fields_ = [ - ('flags', ctypes.c_uint32), - ('drawctxt_id', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('drawctxt_id', ctypes.c_uint32), ] - -IOCTL_KGSL_DRAWCTXT_CREATE = _IOWR ( 0x09 , 0x13 , struct_kgsl_drawctxt_create ) # macro (from list) -class struct_kgsl_drawctxt_destroy(Structure): - pass - -struct_kgsl_drawctxt_destroy._pack_ = 1 # source:False +class struct_kgsl_drawctxt_destroy(Struct): pass struct_kgsl_drawctxt_destroy._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), + ('drawctxt_id', ctypes.c_uint32), ] - -IOCTL_KGSL_DRAWCTXT_DESTROY = _IOW ( 0x09 , 0x14 , struct_kgsl_drawctxt_destroy ) # macro (from list) -class struct_kgsl_map_user_mem(Structure): - pass - -struct_kgsl_map_user_mem._pack_ = 1 # source:False +class struct_kgsl_map_user_mem(Struct): pass struct_kgsl_map_user_mem._fields_ = [ - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('hostptr', ctypes.c_uint64), - ('memtype', kgsl_user_mem_type), - ('flags', ctypes.c_uint32), + ('fd', ctypes.c_int32), + ('gpuaddr', ctypes.c_uint64), + ('len', ctypes.c_uint64), + ('offset', ctypes.c_uint64), + ('hostptr', ctypes.c_uint64), + ('memtype', enum_kgsl_user_mem_type), + ('flags', ctypes.c_uint32), ] - -IOCTL_KGSL_MAP_USER_MEM = _IOWR ( 0x09 , 0x15 , struct_kgsl_map_user_mem ) # macro (from list) -class struct_kgsl_cmdstream_readtimestamp_ctxtid(Structure): - pass - -struct_kgsl_cmdstream_readtimestamp_ctxtid._pack_ = 1 # source:False +class struct_kgsl_cmdstream_readtimestamp_ctxtid(Struct): pass struct_kgsl_cmdstream_readtimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('type', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID = _IOWR ( 0x09 , 0x16 , struct_kgsl_cmdstream_readtimestamp_ctxtid ) # macro (from list) -class struct_kgsl_cmdstream_freememontimestamp_ctxtid(Structure): - pass - -struct_kgsl_cmdstream_freememontimestamp_ctxtid._pack_ = 1 # source:False +class struct_kgsl_cmdstream_freememontimestamp_ctxtid(Struct): pass struct_kgsl_cmdstream_freememontimestamp_ctxtid._fields_ = [ - ('context_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('gpuaddr', ctypes.c_uint64), + ('type', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID = _IOW ( 0x09 , 0x17 , struct_kgsl_cmdstream_freememontimestamp_ctxtid ) # macro (from list) -class struct_kgsl_sharedmem_from_pmem(Structure): - pass - -struct_kgsl_sharedmem_from_pmem._pack_ = 1 # source:False +class struct_kgsl_sharedmem_from_pmem(Struct): pass struct_kgsl_sharedmem_from_pmem._fields_ = [ - ('pmem_fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint32), - ('offset', ctypes.c_uint32), + ('pmem_fd', ctypes.c_int32), + ('gpuaddr', ctypes.c_uint64), + ('len', ctypes.c_uint32), + ('offset', ctypes.c_uint32), ] - -IOCTL_KGSL_SHAREDMEM_FROM_PMEM = _IOWR ( 0x09 , 0x20 , struct_kgsl_sharedmem_from_pmem ) # macro (from list) -class struct_kgsl_sharedmem_free(Structure): - pass - -struct_kgsl_sharedmem_free._pack_ = 1 # source:False +class struct_kgsl_sharedmem_free(Struct): pass struct_kgsl_sharedmem_free._fields_ = [ - ('gpuaddr', ctypes.c_uint64), + ('gpuaddr', ctypes.c_uint64), ] - -IOCTL_KGSL_SHAREDMEM_FREE = _IOW ( 0x09 , 0x21 , struct_kgsl_sharedmem_free ) # macro (from list) -IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE = _IOW ( 0x09 , 0x24 , struct_kgsl_sharedmem_free ) # macro (from list) -class struct_kgsl_cff_user_event(Structure): - pass - -struct_kgsl_cff_user_event._pack_ = 1 # source:False +class struct_kgsl_cff_user_event(Struct): pass struct_kgsl_cff_user_event._fields_ = [ - ('cff_opcode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('op1', ctypes.c_uint32), - ('op2', ctypes.c_uint32), - ('op3', ctypes.c_uint32), - ('op4', ctypes.c_uint32), - ('op5', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), + ('cff_opcode', ctypes.c_ubyte), + ('op1', ctypes.c_uint32), + ('op2', ctypes.c_uint32), + ('op3', ctypes.c_uint32), + ('op4', ctypes.c_uint32), + ('op5', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 2)), ] - -IOCTL_KGSL_CFF_USER_EVENT = _IOW ( 0x09 , 0x31 , struct_kgsl_cff_user_event ) # macro (from list) -class struct_kgsl_gmem_desc(Structure): - pass - -struct_kgsl_gmem_desc._pack_ = 1 # source:False +class struct_kgsl_gmem_desc(Struct): pass struct_kgsl_gmem_desc._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), + ('x', ctypes.c_uint32), + ('y', ctypes.c_uint32), + ('width', ctypes.c_uint32), + ('height', ctypes.c_uint32), + ('pitch', ctypes.c_uint32), ] - -class struct_kgsl_buffer_desc(Structure): - pass - -struct_kgsl_buffer_desc._pack_ = 1 # source:False +class struct_kgsl_buffer_desc(Struct): pass struct_kgsl_buffer_desc._fields_ = [ - ('hostptr', ctypes.POINTER(None)), - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_int32), - ('format', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), - ('enabled', ctypes.c_uint32), + ('hostptr', ctypes.c_void_p), + ('gpuaddr', ctypes.c_uint64), + ('size', ctypes.c_int32), + ('format', ctypes.c_uint32), + ('pitch', ctypes.c_uint32), + ('enabled', ctypes.c_uint32), ] - -class struct_kgsl_bind_gmem_shadow(Structure): - pass - -struct_kgsl_bind_gmem_shadow._pack_ = 1 # source:False +class struct_kgsl_bind_gmem_shadow(Struct): pass struct_kgsl_bind_gmem_shadow._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('gmem_desc', struct_kgsl_gmem_desc), - ('shadow_x', ctypes.c_uint32), - ('shadow_y', ctypes.c_uint32), - ('shadow_buffer', struct_kgsl_buffer_desc), - ('buffer_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('drawctxt_id', ctypes.c_uint32), + ('gmem_desc', struct_kgsl_gmem_desc), + ('shadow_x', ctypes.c_uint32), + ('shadow_y', ctypes.c_uint32), + ('shadow_buffer', struct_kgsl_buffer_desc), + ('buffer_id', ctypes.c_uint32), ] - -IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW = _IOW ( 0x09 , 0x22 , struct_kgsl_bind_gmem_shadow ) # macro (from list) -class struct_kgsl_sharedmem_from_vmalloc(Structure): - pass - -struct_kgsl_sharedmem_from_vmalloc._pack_ = 1 # source:False +class struct_kgsl_sharedmem_from_vmalloc(Struct): pass struct_kgsl_sharedmem_from_vmalloc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('hostptr', ctypes.c_uint32), - ('flags', ctypes.c_uint32), + ('gpuaddr', ctypes.c_uint64), + ('hostptr', ctypes.c_uint32), + ('flags', ctypes.c_uint32), ] - -IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC = _IOWR ( 0x09 , 0x23 , struct_kgsl_sharedmem_from_vmalloc ) # macro (from list) -class struct_kgsl_drawctxt_set_bin_base_offset(Structure): - pass - -struct_kgsl_drawctxt_set_bin_base_offset._pack_ = 1 # source:False +class struct_kgsl_drawctxt_set_bin_base_offset(Struct): pass struct_kgsl_drawctxt_set_bin_base_offset._fields_ = [ - ('drawctxt_id', ctypes.c_uint32), - ('offset', ctypes.c_uint32), + ('drawctxt_id', ctypes.c_uint32), + ('offset', ctypes.c_uint32), ] +enum_kgsl_cmdwindow_type = CEnum(ctypes.c_uint32) +KGSL_CMDWINDOW_MIN = enum_kgsl_cmdwindow_type.define('KGSL_CMDWINDOW_MIN', 0) +KGSL_CMDWINDOW_2D = enum_kgsl_cmdwindow_type.define('KGSL_CMDWINDOW_2D', 0) +KGSL_CMDWINDOW_3D = enum_kgsl_cmdwindow_type.define('KGSL_CMDWINDOW_3D', 1) +KGSL_CMDWINDOW_MMU = enum_kgsl_cmdwindow_type.define('KGSL_CMDWINDOW_MMU', 2) +KGSL_CMDWINDOW_ARBITER = enum_kgsl_cmdwindow_type.define('KGSL_CMDWINDOW_ARBITER', 255) +KGSL_CMDWINDOW_MAX = enum_kgsl_cmdwindow_type.define('KGSL_CMDWINDOW_MAX', 255) -IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET = _IOW ( 0x09 , 0x25 , struct_kgsl_drawctxt_set_bin_base_offset ) # macro (from list) - -# values for enumeration 'kgsl_cmdwindow_type' -kgsl_cmdwindow_type__enumvalues = { - 0: 'KGSL_CMDWINDOW_MIN', - 0: 'KGSL_CMDWINDOW_2D', - 1: 'KGSL_CMDWINDOW_3D', - 2: 'KGSL_CMDWINDOW_MMU', - 255: 'KGSL_CMDWINDOW_ARBITER', - 255: 'KGSL_CMDWINDOW_MAX', -} -KGSL_CMDWINDOW_MIN = 0 -KGSL_CMDWINDOW_2D = 0 -KGSL_CMDWINDOW_3D = 1 -KGSL_CMDWINDOW_MMU = 2 -KGSL_CMDWINDOW_ARBITER = 255 -KGSL_CMDWINDOW_MAX = 255 -kgsl_cmdwindow_type = ctypes.c_uint32 # enum -class struct_kgsl_cmdwindow_write(Structure): - pass - -struct_kgsl_cmdwindow_write._pack_ = 1 # source:False +class struct_kgsl_cmdwindow_write(Struct): pass struct_kgsl_cmdwindow_write._fields_ = [ - ('target', kgsl_cmdwindow_type), - ('addr', ctypes.c_uint32), - ('data', ctypes.c_uint32), + ('target', enum_kgsl_cmdwindow_type), + ('addr', ctypes.c_uint32), + ('data', ctypes.c_uint32), ] - -IOCTL_KGSL_CMDWINDOW_WRITE = _IOW ( 0x09 , 0x2e , struct_kgsl_cmdwindow_write ) # macro (from list) -class struct_kgsl_gpumem_alloc(Structure): - pass - -struct_kgsl_gpumem_alloc._pack_ = 1 # source:False +class struct_kgsl_gpumem_alloc(Struct): pass struct_kgsl_gpumem_alloc._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('gpuaddr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUMEM_ALLOC = _IOWR ( 0x09 , 0x2f , struct_kgsl_gpumem_alloc ) # macro (from list) -class struct_kgsl_cff_syncmem(Structure): - pass - -struct_kgsl_cff_syncmem._pack_ = 1 # source:False +class struct_kgsl_cff_syncmem(Struct): pass struct_kgsl_cff_syncmem._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('len', ctypes.c_uint64), - ('__pad', ctypes.c_uint32 * 2), + ('gpuaddr', ctypes.c_uint64), + ('len', ctypes.c_uint64), + ('__pad', (ctypes.c_uint32 * 2)), ] - -IOCTL_KGSL_CFF_SYNCMEM = _IOW ( 0x09 , 0x30 , struct_kgsl_cff_syncmem ) # macro (from list) -class struct_kgsl_timestamp_event(Structure): - pass - -struct_kgsl_timestamp_event._pack_ = 1 # source:False +class struct_kgsl_timestamp_event(Struct): pass struct_kgsl_timestamp_event._fields_ = [ - ('type', ctypes.c_int32), - ('timestamp', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('priv', ctypes.POINTER(None)), - ('len', ctypes.c_uint64), + ('type', ctypes.c_int32), + ('timestamp', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('priv', ctypes.c_void_p), + ('len', ctypes.c_uint64), ] - -IOCTL_KGSL_TIMESTAMP_EVENT_OLD = _IOW ( 0x09 , 0x31 , struct_kgsl_timestamp_event ) # macro (from list) -IOCTL_KGSL_TIMESTAMP_EVENT = _IOWR ( 0x09 , 0x33 , struct_kgsl_timestamp_event ) # macro (from list) -class struct_kgsl_timestamp_event_genlock(Structure): - pass - -struct_kgsl_timestamp_event_genlock._pack_ = 1 # source:False +class struct_kgsl_timestamp_event_genlock(Struct): pass struct_kgsl_timestamp_event_genlock._fields_ = [ - ('handle', ctypes.c_int32), + ('handle', ctypes.c_int32), ] - -class struct_kgsl_timestamp_event_fence(Structure): - pass - -struct_kgsl_timestamp_event_fence._pack_ = 1 # source:False +class struct_kgsl_timestamp_event_fence(Struct): pass struct_kgsl_timestamp_event_fence._fields_ = [ - ('fence_fd', ctypes.c_int32), + ('fence_fd', ctypes.c_int32), ] - -class struct_kgsl_gpumem_alloc_id(Structure): - pass - -struct_kgsl_gpumem_alloc_id._pack_ = 1 # source:False +class struct_kgsl_gpumem_alloc_id(Struct): pass struct_kgsl_gpumem_alloc_id._fields_ = [ - ('id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('gpuaddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64 * 2), + ('id', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('size', ctypes.c_uint64), + ('mmapsize', ctypes.c_uint64), + ('gpuaddr', ctypes.c_uint64), + ('__pad', (ctypes.c_uint64 * 2)), ] - -IOCTL_KGSL_GPUMEM_ALLOC_ID = _IOWR ( 0x09 , 0x34 , struct_kgsl_gpumem_alloc_id ) # macro (from list) -class struct_kgsl_gpumem_free_id(Structure): - pass - -struct_kgsl_gpumem_free_id._pack_ = 1 # source:False +class struct_kgsl_gpumem_free_id(Struct): pass struct_kgsl_gpumem_free_id._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), + ('id', ctypes.c_uint32), + ('__pad', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUMEM_FREE_ID = _IOWR ( 0x09 , 0x35 , struct_kgsl_gpumem_free_id ) # macro (from list) -class struct_kgsl_gpumem_get_info(Structure): - pass - -struct_kgsl_gpumem_get_info._pack_ = 1 # source:False +class struct_kgsl_gpumem_get_info(Struct): pass struct_kgsl_gpumem_get_info._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('useraddr', ctypes.c_uint64), - ('__pad', ctypes.c_uint64 * 4), + ('gpuaddr', ctypes.c_uint64), + ('id', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('size', ctypes.c_uint64), + ('mmapsize', ctypes.c_uint64), + ('useraddr', ctypes.c_uint64), + ('__pad', (ctypes.c_uint64 * 4)), ] - -IOCTL_KGSL_GPUMEM_GET_INFO = _IOWR ( 0x09 , 0x36 , struct_kgsl_gpumem_get_info ) # macro (from list) -class struct_kgsl_gpumem_sync_cache(Structure): - pass - -struct_kgsl_gpumem_sync_cache._pack_ = 1 # source:False +class struct_kgsl_gpumem_sync_cache(Struct): pass struct_kgsl_gpumem_sync_cache._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), + ('gpuaddr', ctypes.c_uint64), + ('id', ctypes.c_uint32), + ('op', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('length', ctypes.c_uint64), ] - -IOCTL_KGSL_GPUMEM_SYNC_CACHE = _IOW ( 0x09 , 0x37 , struct_kgsl_gpumem_sync_cache ) # macro (from list) -class struct_kgsl_perfcounter_get(Structure): - pass - -struct_kgsl_perfcounter_get._pack_ = 1 # source:False +class struct_kgsl_perfcounter_get(Struct): pass struct_kgsl_perfcounter_get._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('offset_hi', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), + ('groupid', ctypes.c_uint32), + ('countable', ctypes.c_uint32), + ('offset', ctypes.c_uint32), + ('offset_hi', ctypes.c_uint32), + ('__pad', ctypes.c_uint32), ] - -IOCTL_KGSL_PERFCOUNTER_GET = _IOWR ( 0x09 , 0x38 , struct_kgsl_perfcounter_get ) # macro (from list) -class struct_kgsl_perfcounter_put(Structure): - pass - -struct_kgsl_perfcounter_put._pack_ = 1 # source:False +class struct_kgsl_perfcounter_put(Struct): pass struct_kgsl_perfcounter_put._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), + ('groupid', ctypes.c_uint32), + ('countable', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 2)), ] - -IOCTL_KGSL_PERFCOUNTER_PUT = _IOW ( 0x09 , 0x39 , struct_kgsl_perfcounter_put ) # macro (from list) -class struct_kgsl_perfcounter_query(Structure): - pass - -struct_kgsl_perfcounter_query._pack_ = 1 # source:False +class struct_kgsl_perfcounter_query(Struct): pass struct_kgsl_perfcounter_query._fields_ = [ - ('groupid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('countables', ctypes.POINTER(ctypes.c_uint32)), - ('count', ctypes.c_uint32), - ('max_counters', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), + ('groupid', ctypes.c_uint32), + ('countables', ctypes.POINTER(ctypes.c_uint32)), + ('count', ctypes.c_uint32), + ('max_counters', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 2)), ] - -IOCTL_KGSL_PERFCOUNTER_QUERY = _IOWR ( 0x09 , 0x3A , struct_kgsl_perfcounter_query ) # macro (from list) -class struct_kgsl_perfcounter_read_group(Structure): - pass - -struct_kgsl_perfcounter_read_group._pack_ = 1 # source:False +class struct_kgsl_perfcounter_read_group(Struct): pass struct_kgsl_perfcounter_read_group._fields_ = [ - ('groupid', ctypes.c_uint32), - ('countable', ctypes.c_uint32), - ('value', ctypes.c_uint64), + ('groupid', ctypes.c_uint32), + ('countable', ctypes.c_uint32), + ('value', ctypes.c_uint64), ] - -class struct_kgsl_perfcounter_read(Structure): - pass - -struct_kgsl_perfcounter_read._pack_ = 1 # source:False +class struct_kgsl_perfcounter_read(Struct): pass struct_kgsl_perfcounter_read._fields_ = [ - ('reads', ctypes.POINTER(struct_kgsl_perfcounter_read_group)), - ('count', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), - ('PADDING_0', ctypes.c_ubyte * 4), + ('reads', ctypes.POINTER(struct_kgsl_perfcounter_read_group)), + ('count', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 2)), ] - -IOCTL_KGSL_PERFCOUNTER_READ = _IOWR ( 0x09 , 0x3B , struct_kgsl_perfcounter_read ) # macro (from list) -class struct_kgsl_gpumem_sync_cache_bulk(Structure): - pass - -struct_kgsl_gpumem_sync_cache_bulk._pack_ = 1 # source:False +class struct_kgsl_gpumem_sync_cache_bulk(Struct): pass struct_kgsl_gpumem_sync_cache_bulk._fields_ = [ - ('id_list', ctypes.POINTER(ctypes.c_uint32)), - ('count', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 2), + ('id_list', ctypes.POINTER(ctypes.c_uint32)), + ('count', ctypes.c_uint32), + ('op', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 2)), ] - -IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK = _IOWR ( 0x09 , 0x3C , struct_kgsl_gpumem_sync_cache_bulk ) # macro (from list) -class struct_kgsl_cmd_syncpoint_timestamp(Structure): - pass - -struct_kgsl_cmd_syncpoint_timestamp._pack_ = 1 # source:False +class struct_kgsl_cmd_syncpoint_timestamp(Struct): pass struct_kgsl_cmd_syncpoint_timestamp._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -class struct_kgsl_cmd_syncpoint_fence(Structure): - pass - -struct_kgsl_cmd_syncpoint_fence._pack_ = 1 # source:False +class struct_kgsl_cmd_syncpoint_fence(Struct): pass struct_kgsl_cmd_syncpoint_fence._fields_ = [ - ('fd', ctypes.c_int32), + ('fd', ctypes.c_int32), ] - -class struct_kgsl_cmd_syncpoint(Structure): - pass - -struct_kgsl_cmd_syncpoint._pack_ = 1 # source:False +class struct_kgsl_cmd_syncpoint(Struct): pass struct_kgsl_cmd_syncpoint._fields_ = [ - ('type', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('priv', ctypes.POINTER(None)), - ('size', ctypes.c_uint64), + ('type', ctypes.c_int32), + ('priv', ctypes.c_void_p), + ('size', ctypes.c_uint64), ] - -class struct_kgsl_submit_commands(Structure): - pass - -struct_kgsl_submit_commands._pack_ = 1 # source:False +class struct_kgsl_submit_commands(Struct): pass struct_kgsl_submit_commands._fields_ = [ - ('context_id', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('cmdlist', ctypes.POINTER(struct_kgsl_ibdesc)), - ('numcmds', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('synclist', ctypes.POINTER(struct_kgsl_cmd_syncpoint)), - ('numsyncs', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 4), + ('context_id', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('cmdlist', ctypes.POINTER(struct_kgsl_ibdesc)), + ('numcmds', ctypes.c_uint32), + ('synclist', ctypes.POINTER(struct_kgsl_cmd_syncpoint)), + ('numsyncs', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 4)), ] - -IOCTL_KGSL_SUBMIT_COMMANDS = _IOWR ( 0x09 , 0x3D , struct_kgsl_submit_commands ) # macro (from list) -class struct_kgsl_device_constraint(Structure): - pass - -struct_kgsl_device_constraint._pack_ = 1 # source:False +class struct_kgsl_device_constraint(Struct): pass struct_kgsl_device_constraint._fields_ = [ - ('type', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('data', ctypes.POINTER(None)), - ('size', ctypes.c_uint64), + ('type', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('data', ctypes.c_void_p), + ('size', ctypes.c_uint64), ] - -class struct_kgsl_device_constraint_pwrlevel(Structure): - pass - -struct_kgsl_device_constraint_pwrlevel._pack_ = 1 # source:False +class struct_kgsl_device_constraint_pwrlevel(Struct): pass struct_kgsl_device_constraint_pwrlevel._fields_ = [ - ('level', ctypes.c_uint32), + ('level', ctypes.c_uint32), ] - -class struct_kgsl_syncsource_create(Structure): - pass - -struct_kgsl_syncsource_create._pack_ = 1 # source:False +class struct_kgsl_syncsource_create(Struct): pass struct_kgsl_syncsource_create._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 3), + ('id', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 3)), ] - -IOCTL_KGSL_SYNCSOURCE_CREATE = _IOWR ( 0x09 , 0x40 , struct_kgsl_syncsource_create ) # macro (from list) -class struct_kgsl_syncsource_destroy(Structure): - pass - -struct_kgsl_syncsource_destroy._pack_ = 1 # source:False +class struct_kgsl_syncsource_destroy(Struct): pass struct_kgsl_syncsource_destroy._fields_ = [ - ('id', ctypes.c_uint32), - ('__pad', ctypes.c_uint32 * 3), + ('id', ctypes.c_uint32), + ('__pad', (ctypes.c_uint32 * 3)), ] - -IOCTL_KGSL_SYNCSOURCE_DESTROY = _IOWR ( 0x09 , 0x41 , struct_kgsl_syncsource_destroy ) # macro (from list) -class struct_kgsl_syncsource_create_fence(Structure): - pass - -struct_kgsl_syncsource_create_fence._pack_ = 1 # source:False +class struct_kgsl_syncsource_create_fence(Struct): pass struct_kgsl_syncsource_create_fence._fields_ = [ - ('id', ctypes.c_uint32), - ('fence_fd', ctypes.c_int32), - ('__pad', ctypes.c_uint32 * 4), + ('id', ctypes.c_uint32), + ('fence_fd', ctypes.c_int32), + ('__pad', (ctypes.c_uint32 * 4)), ] - -IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE = _IOWR ( 0x09 , 0x42 , struct_kgsl_syncsource_create_fence ) # macro (from list) -class struct_kgsl_syncsource_signal_fence(Structure): - pass - -struct_kgsl_syncsource_signal_fence._pack_ = 1 # source:False +class struct_kgsl_syncsource_signal_fence(Struct): pass struct_kgsl_syncsource_signal_fence._fields_ = [ - ('id', ctypes.c_uint32), - ('fence_fd', ctypes.c_int32), - ('__pad', ctypes.c_uint32 * 4), + ('id', ctypes.c_uint32), + ('fence_fd', ctypes.c_int32), + ('__pad', (ctypes.c_uint32 * 4)), ] - -IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE = _IOWR ( 0x09 , 0x43 , struct_kgsl_syncsource_signal_fence ) # macro (from list) -class struct_kgsl_cff_sync_gpuobj(Structure): - pass - -struct_kgsl_cff_sync_gpuobj._pack_ = 1 # source:False +class struct_kgsl_cff_sync_gpuobj(Struct): pass struct_kgsl_cff_sync_gpuobj._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('offset', ctypes.c_uint64), + ('length', ctypes.c_uint64), + ('id', ctypes.c_uint32), ] - -IOCTL_KGSL_CFF_SYNC_GPUOBJ = _IOW ( 0x09 , 0x44 , struct_kgsl_cff_sync_gpuobj ) # macro (from list) -class struct_kgsl_gpuobj_alloc(Structure): - pass - -struct_kgsl_gpuobj_alloc._pack_ = 1 # source:False +class struct_kgsl_gpuobj_alloc(Struct): pass struct_kgsl_gpuobj_alloc._fields_ = [ - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('va_len', ctypes.c_uint64), - ('mmapsize', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('metadata_len', ctypes.c_uint32), - ('metadata', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint64), + ('va_len', ctypes.c_uint64), + ('mmapsize', ctypes.c_uint64), + ('id', ctypes.c_uint32), + ('metadata_len', ctypes.c_uint32), + ('metadata', ctypes.c_uint64), ] - -IOCTL_KGSL_GPUOBJ_ALLOC = _IOWR ( 0x09 , 0x45 , struct_kgsl_gpuobj_alloc ) # macro (from list) -class struct_kgsl_gpuobj_free(Structure): - pass - -struct_kgsl_gpuobj_free._pack_ = 1 # source:False +class struct_kgsl_gpuobj_free(Struct): pass struct_kgsl_gpuobj_free._fields_ = [ - ('flags', ctypes.c_uint64), - ('priv', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('flags', ctypes.c_uint64), + ('priv', ctypes.c_uint64), + ('id', ctypes.c_uint32), + ('type', ctypes.c_uint32), + ('len', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUOBJ_FREE = _IOW ( 0x09 , 0x46 , struct_kgsl_gpuobj_free ) # macro (from list) -class struct_kgsl_gpu_event_timestamp(Structure): - pass - -struct_kgsl_gpu_event_timestamp._pack_ = 1 # source:False +class struct_kgsl_gpu_event_timestamp(Struct): pass struct_kgsl_gpu_event_timestamp._fields_ = [ - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -class struct_kgsl_gpu_event_fence(Structure): - pass - -struct_kgsl_gpu_event_fence._pack_ = 1 # source:False +class struct_kgsl_gpu_event_fence(Struct): pass struct_kgsl_gpu_event_fence._fields_ = [ - ('fd', ctypes.c_int32), + ('fd', ctypes.c_int32), ] - -class struct_kgsl_gpuobj_info(Structure): - pass - -struct_kgsl_gpuobj_info._pack_ = 1 # source:False +class struct_kgsl_gpuobj_info(Struct): pass struct_kgsl_gpuobj_info._fields_ = [ - ('gpuaddr', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('va_len', ctypes.c_uint64), - ('va_addr', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('gpuaddr', ctypes.c_uint64), + ('flags', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('va_len', ctypes.c_uint64), + ('va_addr', ctypes.c_uint64), + ('id', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUOBJ_INFO = _IOWR ( 0x09 , 0x47 , struct_kgsl_gpuobj_info ) # macro (from list) -class struct_kgsl_gpuobj_import(Structure): - pass - -struct_kgsl_gpuobj_import._pack_ = 1 # source:False +class struct_kgsl_gpuobj_import(Struct): pass struct_kgsl_gpuobj_import._fields_ = [ - ('priv', ctypes.c_uint64), - ('priv_len', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('id', ctypes.c_uint32), + ('priv', ctypes.c_uint64), + ('priv_len', ctypes.c_uint64), + ('flags', ctypes.c_uint64), + ('type', ctypes.c_uint32), + ('id', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUOBJ_IMPORT = _IOWR ( 0x09 , 0x48 , struct_kgsl_gpuobj_import ) # macro (from list) -class struct_kgsl_gpuobj_import_dma_buf(Structure): - pass - -struct_kgsl_gpuobj_import_dma_buf._pack_ = 1 # source:False +class struct_kgsl_gpuobj_import_dma_buf(Struct): pass struct_kgsl_gpuobj_import_dma_buf._fields_ = [ - ('fd', ctypes.c_int32), + ('fd', ctypes.c_int32), ] - -class struct_kgsl_gpuobj_import_useraddr(Structure): - pass - -struct_kgsl_gpuobj_import_useraddr._pack_ = 1 # source:False +class struct_kgsl_gpuobj_import_useraddr(Struct): pass struct_kgsl_gpuobj_import_useraddr._fields_ = [ - ('virtaddr', ctypes.c_uint64), + ('virtaddr', ctypes.c_uint64), ] - -class struct_kgsl_gpuobj_sync_obj(Structure): - pass - -struct_kgsl_gpuobj_sync_obj._pack_ = 1 # source:False +class struct_kgsl_gpuobj_sync_obj(Struct): pass struct_kgsl_gpuobj_sync_obj._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('op', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('length', ctypes.c_uint64), + ('id', ctypes.c_uint32), + ('op', ctypes.c_uint32), ] - -class struct_kgsl_gpuobj_sync(Structure): - pass - -struct_kgsl_gpuobj_sync._pack_ = 1 # source:False +class struct_kgsl_gpuobj_sync(Struct): pass struct_kgsl_gpuobj_sync._fields_ = [ - ('objs', ctypes.c_uint64), - ('obj_len', ctypes.c_uint32), - ('count', ctypes.c_uint32), + ('objs', ctypes.c_uint64), + ('obj_len', ctypes.c_uint32), + ('count', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUOBJ_SYNC = _IOW ( 0x09 , 0x49 , struct_kgsl_gpuobj_sync ) # macro (from list) -class struct_kgsl_command_object(Structure): - pass - -struct_kgsl_command_object._pack_ = 1 # source:False +class struct_kgsl_command_object(Struct): pass struct_kgsl_command_object._fields_ = [ - ('offset', ctypes.c_uint64), - ('gpuaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('id', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('gpuaddr', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('flags', ctypes.c_uint32), + ('id', ctypes.c_uint32), ] - -class struct_kgsl_command_syncpoint(Structure): - pass - -struct_kgsl_command_syncpoint._pack_ = 1 # source:False +class struct_kgsl_command_syncpoint(Struct): pass struct_kgsl_command_syncpoint._fields_ = [ - ('priv', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('priv', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('type', ctypes.c_uint32), ] - -class struct_kgsl_gpu_command(Structure): - pass - -struct_kgsl_gpu_command._pack_ = 1 # source:False +class struct_kgsl_gpu_command(Struct): pass struct_kgsl_gpu_command._fields_ = [ - ('flags', ctypes.c_uint64), - ('cmdlist', ctypes.c_uint64), - ('cmdsize', ctypes.c_uint32), - ('numcmds', ctypes.c_uint32), - ('objlist', ctypes.c_uint64), - ('objsize', ctypes.c_uint32), - ('numobjs', ctypes.c_uint32), - ('synclist', ctypes.c_uint64), - ('syncsize', ctypes.c_uint32), - ('numsyncs', ctypes.c_uint32), - ('context_id', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('flags', ctypes.c_uint64), + ('cmdlist', ctypes.c_uint64), + ('cmdsize', ctypes.c_uint32), + ('numcmds', ctypes.c_uint32), + ('objlist', ctypes.c_uint64), + ('objsize', ctypes.c_uint32), + ('numobjs', ctypes.c_uint32), + ('synclist', ctypes.c_uint64), + ('syncsize', ctypes.c_uint32), + ('numsyncs', ctypes.c_uint32), + ('context_id', ctypes.c_uint32), + ('timestamp', ctypes.c_uint32), ] - -IOCTL_KGSL_GPU_COMMAND = _IOWR ( 0x09 , 0x4A , struct_kgsl_gpu_command ) # macro (from list) -class struct_kgsl_preemption_counters_query(Structure): - pass - -struct_kgsl_preemption_counters_query._pack_ = 1 # source:False +class struct_kgsl_preemption_counters_query(Struct): pass struct_kgsl_preemption_counters_query._fields_ = [ - ('counters', ctypes.c_uint64), - ('size_user', ctypes.c_uint32), - ('size_priority_level', ctypes.c_uint32), - ('max_priority_level', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('counters', ctypes.c_uint64), + ('size_user', ctypes.c_uint32), + ('size_priority_level', ctypes.c_uint32), + ('max_priority_level', ctypes.c_uint32), ] - -IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY = _IOWR ( 0x09 , 0x4B , struct_kgsl_preemption_counters_query ) # macro (from list) -class struct_kgsl_gpuobj_set_info(Structure): - pass - -struct_kgsl_gpuobj_set_info._pack_ = 1 # source:False +class struct_kgsl_gpuobj_set_info(Struct): pass struct_kgsl_gpuobj_set_info._fields_ = [ - ('flags', ctypes.c_uint64), - ('metadata', ctypes.c_uint64), - ('id', ctypes.c_uint32), - ('metadata_len', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('flags', ctypes.c_uint64), + ('metadata', ctypes.c_uint64), + ('id', ctypes.c_uint32), + ('metadata_len', ctypes.c_uint32), + ('type', ctypes.c_uint32), ] - -IOCTL_KGSL_GPUOBJ_SET_INFO = _IOW ( 0x09 , 0x4C , struct_kgsl_gpuobj_set_info ) # macro (from list) -__all__ = \ - ['KGSL_CACHEMODE_MASK', 'KGSL_CACHEMODE_SHIFT', - 'KGSL_CACHEMODE_UNCACHED', 'KGSL_CACHEMODE_WRITEBACK', - 'KGSL_CACHEMODE_WRITECOMBINE', 'KGSL_CACHEMODE_WRITETHROUGH', - 'KGSL_CMDBATCH_CTX_SWITCH', 'KGSL_CMDBATCH_END_OF_FRAME', - 'KGSL_CMDBATCH_MARKER', 'KGSL_CMDBATCH_MEMLIST', - 'KGSL_CMDBATCH_PROFILING', 'KGSL_CMDBATCH_PROFILING_KTIME', - 'KGSL_CMDBATCH_PWR_CONSTRAINT', 'KGSL_CMDBATCH_SUBMIT_IB_LIST', - 'KGSL_CMDBATCH_SYNC', 'KGSL_CMDLIST_CTXTSWITCH_PREAMBLE', - 'KGSL_CMDLIST_IB', 'KGSL_CMDLIST_IB_PREAMBLE', - 'KGSL_CMDWINDOW_2D', 'KGSL_CMDWINDOW_3D', - 'KGSL_CMDWINDOW_ARBITER', 'KGSL_CMDWINDOW_MAX', - 'KGSL_CMDWINDOW_MIN', 'KGSL_CMDWINDOW_MMU', - 'KGSL_CMD_SYNCPOINT_TYPE_FENCE', - 'KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP', 'KGSL_CONSTRAINT_NONE', - 'KGSL_CONSTRAINT_PWRLEVEL', 'KGSL_CONSTRAINT_PWR_MAX', - 'KGSL_CONSTRAINT_PWR_MIN', 'KGSL_CONTEXT_CTX_SWITCH', - 'KGSL_CONTEXT_END_OF_FRAME', 'KGSL_CONTEXT_IFH_NOP', - 'KGSL_CONTEXT_INVALID', 'KGSL_CONTEXT_NO_FAULT_TOLERANCE', - 'KGSL_CONTEXT_NO_GMEM_ALLOC', 'KGSL_CONTEXT_PER_CONTEXT_TS', - 'KGSL_CONTEXT_PREAMBLE', 'KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT', - 'KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN', - 'KGSL_CONTEXT_PREEMPT_STYLE_MASK', - 'KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER', - 'KGSL_CONTEXT_PREEMPT_STYLE_SHIFT', 'KGSL_CONTEXT_PRIORITY_MASK', - 'KGSL_CONTEXT_PRIORITY_SHIFT', 'KGSL_CONTEXT_PRIORITY_UNDEF', - 'KGSL_CONTEXT_PWR_CONSTRAINT', 'KGSL_CONTEXT_SAVE_GMEM', - 'KGSL_CONTEXT_SECURE', 'KGSL_CONTEXT_SUBMIT_IB_LIST', - 'KGSL_CONTEXT_SYNC', 'KGSL_CONTEXT_TRASH_STATE', - 'KGSL_CONTEXT_TYPE_ANY', 'KGSL_CONTEXT_TYPE_C2D', - 'KGSL_CONTEXT_TYPE_CL', 'KGSL_CONTEXT_TYPE_GL', - 'KGSL_CONTEXT_TYPE_MASK', 'KGSL_CONTEXT_TYPE_RS', - 'KGSL_CONTEXT_TYPE_SHIFT', 'KGSL_CONTEXT_TYPE_UNKNOWN', - 'KGSL_CONTEXT_USER_GENERATED_TS', - 'KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT', - 'KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT', - 'KGSL_CTX_STAT_NO_ERROR', - 'KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT', 'KGSL_DEVICE_3D0', - 'KGSL_DEVICE_MAX', 'KGSL_FLAGS_ACTIVE', 'KGSL_FLAGS_INITIALIZED', - 'KGSL_FLAGS_INITIALIZED0', 'KGSL_FLAGS_NORMALMODE', - 'KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS', 'KGSL_FLAGS_RESERVED0', - 'KGSL_FLAGS_RESERVED1', 'KGSL_FLAGS_RESERVED2', - 'KGSL_FLAGS_SAFEMODE', 'KGSL_FLAGS_SOFT_RESET', - 'KGSL_FLAGS_STARTED', 'KGSL_GPUMEM_CACHE_CLEAN', - 'KGSL_GPUMEM_CACHE_FLUSH', 'KGSL_GPUMEM_CACHE_FROM_GPU', - 'KGSL_GPUMEM_CACHE_INV', 'KGSL_GPUMEM_CACHE_RANGE', - 'KGSL_GPUMEM_CACHE_TO_GPU', 'KGSL_GPUOBJ_ALLOC_METADATA_MAX', - 'KGSL_GPUOBJ_FREE_ON_EVENT', 'KGSL_GPUOBJ_SET_INFO_METADATA', - 'KGSL_GPUOBJ_SET_INFO_TYPE', 'KGSL_GPU_EVENT_FENCE', - 'KGSL_GPU_EVENT_TIMESTAMP', 'KGSL_IBDESC_MEMLIST', - 'KGSL_IBDESC_PROFILING_BUFFER', 'KGSL_IOC_TYPE', - 'KGSL_MEMALIGN_MASK', 'KGSL_MEMALIGN_SHIFT', - 'KGSL_MEMFLAGS_FORCE_32BIT', 'KGSL_MEMFLAGS_GPUREADONLY', - 'KGSL_MEMFLAGS_GPUWRITEONLY', 'KGSL_MEMFLAGS_NOT_USERMEM', - 'KGSL_MEMFLAGS_SECURE', 'KGSL_MEMFLAGS_USERMEM_MASK', - 'KGSL_MEMFLAGS_USERMEM_SHIFT', 'KGSL_MEMFLAGS_USE_CPU_MAP', - 'KGSL_MEMTYPE_2D', 'KGSL_MEMTYPE_ARRAYBUFFER', 'KGSL_MEMTYPE_CL', - 'KGSL_MEMTYPE_CL_BUFFER_MAP', 'KGSL_MEMTYPE_CL_BUFFER_NOMAP', - 'KGSL_MEMTYPE_CL_IMAGE_MAP', 'KGSL_MEMTYPE_CL_IMAGE_NOMAP', - 'KGSL_MEMTYPE_CL_KERNEL_STACK', 'KGSL_MEMTYPE_COMMAND', - 'KGSL_MEMTYPE_EGL_IMAGE', 'KGSL_MEMTYPE_EGL_SHADOW', - 'KGSL_MEMTYPE_EGL_SURFACE', 'KGSL_MEMTYPE_ELEMENTARRAYBUFFER', - 'KGSL_MEMTYPE_FRAMEBUFFER', 'KGSL_MEMTYPE_GL', - 'KGSL_MEMTYPE_KERNEL', 'KGSL_MEMTYPE_MASK', - 'KGSL_MEMTYPE_MULTISAMPLE', 'KGSL_MEMTYPE_OBJECTANY', - 'KGSL_MEMTYPE_RENDERBUFFER', 'KGSL_MEMTYPE_SHIFT', - 'KGSL_MEMTYPE_SURFACE', 'KGSL_MEMTYPE_TEXTURE', - 'KGSL_MEMTYPE_VERTEXARRAYBUFFER', 'KGSL_OBJLIST_MEMOBJ', - 'KGSL_OBJLIST_PROFILE', 'KGSL_PERFCOUNTER_BROKEN', - 'KGSL_PERFCOUNTER_GROUP_ALWAYSON', - 'KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR', - 'KGSL_PERFCOUNTER_GROUP_CCU', 'KGSL_PERFCOUNTER_GROUP_CCU_PWR', - 'KGSL_PERFCOUNTER_GROUP_CMP', 'KGSL_PERFCOUNTER_GROUP_CP', - 'KGSL_PERFCOUNTER_GROUP_CP_PWR', - 'KGSL_PERFCOUNTER_GROUP_GPMU_PWR', 'KGSL_PERFCOUNTER_GROUP_HLSQ', - 'KGSL_PERFCOUNTER_GROUP_L2', 'KGSL_PERFCOUNTER_GROUP_LRZ', - 'KGSL_PERFCOUNTER_GROUP_MAX', 'KGSL_PERFCOUNTER_GROUP_MH', - 'KGSL_PERFCOUNTER_GROUP_PA_SU', 'KGSL_PERFCOUNTER_GROUP_PC', - 'KGSL_PERFCOUNTER_GROUP_PWR', 'KGSL_PERFCOUNTER_GROUP_RAS', - 'KGSL_PERFCOUNTER_GROUP_RB', 'KGSL_PERFCOUNTER_GROUP_RBBM', - 'KGSL_PERFCOUNTER_GROUP_RB_PWR', 'KGSL_PERFCOUNTER_GROUP_SP', - 'KGSL_PERFCOUNTER_GROUP_SP_PWR', 'KGSL_PERFCOUNTER_GROUP_SQ', - 'KGSL_PERFCOUNTER_GROUP_SX', 'KGSL_PERFCOUNTER_GROUP_TCF', - 'KGSL_PERFCOUNTER_GROUP_TCM', 'KGSL_PERFCOUNTER_GROUP_TCR', - 'KGSL_PERFCOUNTER_GROUP_TP', 'KGSL_PERFCOUNTER_GROUP_TP_PWR', - 'KGSL_PERFCOUNTER_GROUP_TSE', 'KGSL_PERFCOUNTER_GROUP_UCHE', - 'KGSL_PERFCOUNTER_GROUP_UCHE_PWR', 'KGSL_PERFCOUNTER_GROUP_VBIF', - 'KGSL_PERFCOUNTER_GROUP_VBIF_PWR', 'KGSL_PERFCOUNTER_GROUP_VFD', - 'KGSL_PERFCOUNTER_GROUP_VPC', 'KGSL_PERFCOUNTER_GROUP_VSC', - 'KGSL_PERFCOUNTER_NOT_USED', 'KGSL_PROP_DEVICE_BITNESS', - 'KGSL_PROP_DEVICE_INFO', 'KGSL_PROP_DEVICE_POWER', - 'KGSL_PROP_DEVICE_SHADOW', 'KGSL_PROP_GPMU_VERSION', - 'KGSL_PROP_GPU_RESET_STAT', 'KGSL_PROP_INTERRUPT_WAITS', - 'KGSL_PROP_MMU_ENABLE', 'KGSL_PROP_PWRCTRL', - 'KGSL_PROP_PWR_CONSTRAINT', 'KGSL_PROP_SHMEM', - 'KGSL_PROP_SHMEM_APERTURES', 'KGSL_PROP_SP_GENERIC_MEM', - 'KGSL_PROP_UCHE_GMEM_VADDR', 'KGSL_PROP_UCODE_VERSION', - 'KGSL_PROP_VERSION', 'KGSL_SYNCOBJ_SERVER_TIMEOUT', - 'KGSL_TIMESTAMP_CONSUMED', 'KGSL_TIMESTAMP_EVENT_FENCE', - 'KGSL_TIMESTAMP_EVENT_GENLOCK', 'KGSL_TIMESTAMP_QUEUED', - 'KGSL_TIMESTAMP_RETIRED', 'KGSL_USER_MEM_TYPE_ADDR', - 'KGSL_USER_MEM_TYPE_ASHMEM', 'KGSL_USER_MEM_TYPE_DMABUF', - 'KGSL_USER_MEM_TYPE_ION', 'KGSL_USER_MEM_TYPE_MAX', - 'KGSL_USER_MEM_TYPE_PMEM', 'KGSL_VERSION_MAJOR', - 'KGSL_VERSION_MINOR', '_IO', '_IOR', '_IOW', '_IOWR', - '_UAPI_MSM_KGSL_H', 'kgsl_cmdwindow_type', 'kgsl_ctx_reset_stat', - 'kgsl_deviceid', 'kgsl_timestamp_type', 'kgsl_user_mem_type', - 'size_t', 'struct_kgsl_bind_gmem_shadow', - 'struct_kgsl_buffer_desc', 'struct_kgsl_cff_sync_gpuobj', - 'struct_kgsl_cff_syncmem', 'struct_kgsl_cff_user_event', - 'struct_kgsl_cmd_syncpoint', 'struct_kgsl_cmd_syncpoint_fence', - 'struct_kgsl_cmd_syncpoint_timestamp', - 'struct_kgsl_cmdbatch_profiling_buffer', - 'struct_kgsl_cmdstream_freememontimestamp', - 'struct_kgsl_cmdstream_freememontimestamp_ctxtid', - 'struct_kgsl_cmdstream_readtimestamp', - 'struct_kgsl_cmdstream_readtimestamp_ctxtid', - 'struct_kgsl_cmdwindow_write', 'struct_kgsl_command_object', - 'struct_kgsl_command_syncpoint', 'struct_kgsl_device_constraint', - 'struct_kgsl_device_constraint_pwrlevel', - 'struct_kgsl_device_getproperty', - 'struct_kgsl_device_waittimestamp', - 'struct_kgsl_device_waittimestamp_ctxtid', 'struct_kgsl_devinfo', - 'struct_kgsl_devmemstore', 'struct_kgsl_drawctxt_create', - 'struct_kgsl_drawctxt_destroy', - 'struct_kgsl_drawctxt_set_bin_base_offset', - 'struct_kgsl_gmem_desc', 'struct_kgsl_gpmu_version', - 'struct_kgsl_gpu_command', 'struct_kgsl_gpu_event_fence', - 'struct_kgsl_gpu_event_timestamp', 'struct_kgsl_gpumem_alloc', - 'struct_kgsl_gpumem_alloc_id', 'struct_kgsl_gpumem_free_id', - 'struct_kgsl_gpumem_get_info', 'struct_kgsl_gpumem_sync_cache', - 'struct_kgsl_gpumem_sync_cache_bulk', 'struct_kgsl_gpuobj_alloc', - 'struct_kgsl_gpuobj_free', 'struct_kgsl_gpuobj_import', - 'struct_kgsl_gpuobj_import_dma_buf', - 'struct_kgsl_gpuobj_import_useraddr', 'struct_kgsl_gpuobj_info', - 'struct_kgsl_gpuobj_set_info', 'struct_kgsl_gpuobj_sync', - 'struct_kgsl_gpuobj_sync_obj', 'struct_kgsl_ibdesc', - 'struct_kgsl_map_user_mem', 'struct_kgsl_perfcounter_get', - 'struct_kgsl_perfcounter_put', 'struct_kgsl_perfcounter_query', - 'struct_kgsl_perfcounter_read', - 'struct_kgsl_perfcounter_read_group', - 'struct_kgsl_preemption_counters_query', - 'struct_kgsl_ringbuffer_issueibcmds', 'struct_kgsl_shadowprop', - 'struct_kgsl_sharedmem_free', 'struct_kgsl_sharedmem_from_pmem', - 'struct_kgsl_sharedmem_from_vmalloc', - 'struct_kgsl_sp_generic_mem', 'struct_kgsl_submit_commands', - 'struct_kgsl_syncsource_create', - 'struct_kgsl_syncsource_create_fence', - 'struct_kgsl_syncsource_destroy', - 'struct_kgsl_syncsource_signal_fence', - 'struct_kgsl_timestamp_event', - 'struct_kgsl_timestamp_event_fence', - 'struct_kgsl_timestamp_event_genlock', - 'struct_kgsl_ucode_version', 'struct_kgsl_version', 'uint64_t'] -def KGSL_CONTEXT_PRIORITY(val): return (val << KGSL_CONTEXT_PRIORITY_SHIFT) & KGSL_CONTEXT_PRIORITY_MASK -def KGSL_CONTEXT_PREEMPT_STYLE(val): return (val << KGSL_CONTEXT_PREEMPT_STYLE_SHIFT) & KGSL_CONTEXT_PREEMPT_STYLE_MASK -def KGSL_CONTEXT_TYPE(val): return (val << KGSL_CONTEXT_TYPE_SHIFT) & KGSL_CONTEXT_TYPE_MASK -def KGSL_CACHEMODE(val): return (val << KGSL_CACHEMODE_SHIFT) & KGSL_CACHEMODE_MASK -def KGSL_MEMTYPE(val): return (val << KGSL_MEMTYPE_SHIFT) & KGSL_MEMTYPE_MASK -def KGSL_MEMALIGN(val): return (val << KGSL_MEMALIGN_SHIFT) & KGSL_MEMALIGN_MASK -def KGSL_MEMFLAGS_USERMEM(val): return (val << KGSL_MEMFLAGS_USERMEM_SHIFT) & KGSL_MEMFLAGS_USERMEM_MASK +KGSL_VERSION_MAJOR = 3 +KGSL_VERSION_MINOR = 14 +KGSL_CONTEXT_SAVE_GMEM = 0x00000001 +KGSL_CONTEXT_NO_GMEM_ALLOC = 0x00000002 +KGSL_CONTEXT_SUBMIT_IB_LIST = 0x00000004 +KGSL_CONTEXT_CTX_SWITCH = 0x00000008 +KGSL_CONTEXT_PREAMBLE = 0x00000010 +KGSL_CONTEXT_TRASH_STATE = 0x00000020 +KGSL_CONTEXT_PER_CONTEXT_TS = 0x00000040 +KGSL_CONTEXT_USER_GENERATED_TS = 0x00000080 +KGSL_CONTEXT_END_OF_FRAME = 0x00000100 +KGSL_CONTEXT_NO_FAULT_TOLERANCE = 0x00000200 +KGSL_CONTEXT_SYNC = 0x00000400 +KGSL_CONTEXT_PWR_CONSTRAINT = 0x00000800 +KGSL_CONTEXT_PRIORITY_MASK = 0x0000F000 +KGSL_CONTEXT_PRIORITY_SHIFT = 12 +KGSL_CONTEXT_PRIORITY_UNDEF = 0 +KGSL_CONTEXT_IFH_NOP = 0x00010000 +KGSL_CONTEXT_SECURE = 0x00020000 +KGSL_CONTEXT_PREEMPT_STYLE_MASK = 0x0E000000 +KGSL_CONTEXT_PREEMPT_STYLE_SHIFT = 25 +KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT = 0x0 +KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER = 0x1 +KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN = 0x2 +KGSL_CONTEXT_TYPE_MASK = 0x01F00000 +KGSL_CONTEXT_TYPE_SHIFT = 20 +KGSL_CONTEXT_TYPE_ANY = 0 +KGSL_CONTEXT_TYPE_GL = 1 +KGSL_CONTEXT_TYPE_CL = 2 +KGSL_CONTEXT_TYPE_C2D = 3 +KGSL_CONTEXT_TYPE_RS = 4 +KGSL_CONTEXT_TYPE_UNKNOWN = 0x1E +KGSL_CONTEXT_INVALID = 0xffffffff +KGSL_CMDBATCH_MEMLIST = 0x00000001 +KGSL_CMDBATCH_MARKER = 0x00000002 +KGSL_CMDBATCH_SUBMIT_IB_LIST = KGSL_CONTEXT_SUBMIT_IB_LIST +KGSL_CMDBATCH_CTX_SWITCH = KGSL_CONTEXT_CTX_SWITCH +KGSL_CMDBATCH_PROFILING = 0x00000010 +KGSL_CMDBATCH_PROFILING_KTIME = 0x00000020 +KGSL_CMDBATCH_END_OF_FRAME = KGSL_CONTEXT_END_OF_FRAME +KGSL_CMDBATCH_SYNC = KGSL_CONTEXT_SYNC +KGSL_CMDBATCH_PWR_CONSTRAINT = KGSL_CONTEXT_PWR_CONSTRAINT +KGSL_CMDLIST_IB = 0x00000001 +KGSL_CMDLIST_CTXTSWITCH_PREAMBLE = 0x00000002 +KGSL_CMDLIST_IB_PREAMBLE = 0x00000004 +KGSL_OBJLIST_MEMOBJ = 0x00000008 +KGSL_OBJLIST_PROFILE = 0x00000010 +KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP = 0 +KGSL_CMD_SYNCPOINT_TYPE_FENCE = 1 +KGSL_MEMFLAGS_SECURE = 0x00000008 +KGSL_MEMFLAGS_GPUREADONLY = 0x01000000 +KGSL_MEMFLAGS_GPUWRITEONLY = 0x02000000 +KGSL_MEMFLAGS_FORCE_32BIT = 0x100000000 +KGSL_CACHEMODE_MASK = 0x0C000000 +KGSL_CACHEMODE_SHIFT = 26 +KGSL_CACHEMODE_WRITECOMBINE = 0 +KGSL_CACHEMODE_UNCACHED = 1 +KGSL_CACHEMODE_WRITETHROUGH = 2 +KGSL_CACHEMODE_WRITEBACK = 3 +KGSL_MEMFLAGS_USE_CPU_MAP = 0x10000000 +KGSL_MEMTYPE_MASK = 0x0000FF00 +KGSL_MEMTYPE_SHIFT = 8 +KGSL_MEMTYPE_OBJECTANY = 0 +KGSL_MEMTYPE_FRAMEBUFFER = 1 +KGSL_MEMTYPE_RENDERBUFFER = 2 +KGSL_MEMTYPE_ARRAYBUFFER = 3 +KGSL_MEMTYPE_ELEMENTARRAYBUFFER = 4 +KGSL_MEMTYPE_VERTEXARRAYBUFFER = 5 +KGSL_MEMTYPE_TEXTURE = 6 +KGSL_MEMTYPE_SURFACE = 7 +KGSL_MEMTYPE_EGL_SURFACE = 8 +KGSL_MEMTYPE_GL = 9 +KGSL_MEMTYPE_CL = 10 +KGSL_MEMTYPE_CL_BUFFER_MAP = 11 +KGSL_MEMTYPE_CL_BUFFER_NOMAP = 12 +KGSL_MEMTYPE_CL_IMAGE_MAP = 13 +KGSL_MEMTYPE_CL_IMAGE_NOMAP = 14 +KGSL_MEMTYPE_CL_KERNEL_STACK = 15 +KGSL_MEMTYPE_COMMAND = 16 +KGSL_MEMTYPE_2D = 17 +KGSL_MEMTYPE_EGL_IMAGE = 18 +KGSL_MEMTYPE_EGL_SHADOW = 19 +KGSL_MEMTYPE_MULTISAMPLE = 20 +KGSL_MEMTYPE_KERNEL = 255 +KGSL_MEMALIGN_MASK = 0x00FF0000 +KGSL_MEMALIGN_SHIFT = 16 +KGSL_MEMFLAGS_USERMEM_MASK = 0x000000e0 +KGSL_MEMFLAGS_USERMEM_SHIFT = 5 +KGSL_USERMEM_FLAG = lambda x: (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT) +KGSL_MEMFLAGS_NOT_USERMEM = 0 +KGSL_MEMFLAGS_USERMEM_PMEM = KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM) +KGSL_MEMFLAGS_USERMEM_ASHMEM = KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM) +KGSL_MEMFLAGS_USERMEM_ADDR = KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR) +KGSL_MEMFLAGS_USERMEM_ION = KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION) +KGSL_FLAGS_NORMALMODE = 0x00000000 +KGSL_FLAGS_SAFEMODE = 0x00000001 +KGSL_FLAGS_INITIALIZED0 = 0x00000002 +KGSL_FLAGS_INITIALIZED = 0x00000004 +KGSL_FLAGS_STARTED = 0x00000008 +KGSL_FLAGS_ACTIVE = 0x00000010 +KGSL_FLAGS_RESERVED0 = 0x00000020 +KGSL_FLAGS_RESERVED1 = 0x00000040 +KGSL_FLAGS_RESERVED2 = 0x00000080 +KGSL_FLAGS_SOFT_RESET = 0x00000100 +KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS = 0x00000200 +KGSL_SYNCOBJ_SERVER_TIMEOUT = 2000 +KGSL_CONVERT_TO_MBPS = lambda val: (val*1000*1000) +KGSL_MEMSTORE_OFFSET = lambda ctxt_id,field: ((ctxt_id)*sizeof(struct_kgsl_devmemstore) + offsetof(struct_kgsl_devmemstore, field)) +KGSL_PROP_DEVICE_INFO = 0x1 +KGSL_PROP_DEVICE_SHADOW = 0x2 +KGSL_PROP_DEVICE_POWER = 0x3 +KGSL_PROP_SHMEM = 0x4 +KGSL_PROP_SHMEM_APERTURES = 0x5 +KGSL_PROP_MMU_ENABLE = 0x6 +KGSL_PROP_INTERRUPT_WAITS = 0x7 +KGSL_PROP_VERSION = 0x8 +KGSL_PROP_GPU_RESET_STAT = 0x9 +KGSL_PROP_PWRCTRL = 0xE +KGSL_PROP_PWR_CONSTRAINT = 0x12 +KGSL_PROP_UCHE_GMEM_VADDR = 0x13 +KGSL_PROP_SP_GENERIC_MEM = 0x14 +KGSL_PROP_UCODE_VERSION = 0x15 +KGSL_PROP_GPMU_VERSION = 0x16 +KGSL_PROP_DEVICE_BITNESS = 0x18 +KGSL_PERFCOUNTER_GROUP_CP = 0x0 +KGSL_PERFCOUNTER_GROUP_RBBM = 0x1 +KGSL_PERFCOUNTER_GROUP_PC = 0x2 +KGSL_PERFCOUNTER_GROUP_VFD = 0x3 +KGSL_PERFCOUNTER_GROUP_HLSQ = 0x4 +KGSL_PERFCOUNTER_GROUP_VPC = 0x5 +KGSL_PERFCOUNTER_GROUP_TSE = 0x6 +KGSL_PERFCOUNTER_GROUP_RAS = 0x7 +KGSL_PERFCOUNTER_GROUP_UCHE = 0x8 +KGSL_PERFCOUNTER_GROUP_TP = 0x9 +KGSL_PERFCOUNTER_GROUP_SP = 0xA +KGSL_PERFCOUNTER_GROUP_RB = 0xB +KGSL_PERFCOUNTER_GROUP_PWR = 0xC +KGSL_PERFCOUNTER_GROUP_VBIF = 0xD +KGSL_PERFCOUNTER_GROUP_VBIF_PWR = 0xE +KGSL_PERFCOUNTER_GROUP_MH = 0xF +KGSL_PERFCOUNTER_GROUP_PA_SU = 0x10 +KGSL_PERFCOUNTER_GROUP_SQ = 0x11 +KGSL_PERFCOUNTER_GROUP_SX = 0x12 +KGSL_PERFCOUNTER_GROUP_TCF = 0x13 +KGSL_PERFCOUNTER_GROUP_TCM = 0x14 +KGSL_PERFCOUNTER_GROUP_TCR = 0x15 +KGSL_PERFCOUNTER_GROUP_L2 = 0x16 +KGSL_PERFCOUNTER_GROUP_VSC = 0x17 +KGSL_PERFCOUNTER_GROUP_CCU = 0x18 +KGSL_PERFCOUNTER_GROUP_LRZ = 0x19 +KGSL_PERFCOUNTER_GROUP_CMP = 0x1A +KGSL_PERFCOUNTER_GROUP_ALWAYSON = 0x1B +KGSL_PERFCOUNTER_GROUP_SP_PWR = 0x1C +KGSL_PERFCOUNTER_GROUP_TP_PWR = 0x1D +KGSL_PERFCOUNTER_GROUP_RB_PWR = 0x1E +KGSL_PERFCOUNTER_GROUP_CCU_PWR = 0x1F +KGSL_PERFCOUNTER_GROUP_UCHE_PWR = 0x20 +KGSL_PERFCOUNTER_GROUP_CP_PWR = 0x21 +KGSL_PERFCOUNTER_GROUP_GPMU_PWR = 0x22 +KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR = 0x23 +KGSL_PERFCOUNTER_GROUP_MAX = 0x24 +KGSL_PERFCOUNTER_NOT_USED = 0xFFFFFFFF +KGSL_PERFCOUNTER_BROKEN = 0xFFFFFFFE +KGSL_IOC_TYPE = 0x09 +IOCTL_KGSL_DEVICE_GETPROPERTY = _IOWR(KGSL_IOC_TYPE, 0x2, struct_kgsl_device_getproperty) +IOCTL_KGSL_DEVICE_WAITTIMESTAMP = _IOW(KGSL_IOC_TYPE, 0x6, struct_kgsl_device_waittimestamp) +IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID = _IOW(KGSL_IOC_TYPE, 0x7, struct_kgsl_device_waittimestamp_ctxtid) +IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS = _IOWR(KGSL_IOC_TYPE, 0x10, struct_kgsl_ringbuffer_issueibcmds) +IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD = _IOR(KGSL_IOC_TYPE, 0x11, struct_kgsl_cmdstream_readtimestamp) +IOCTL_KGSL_CMDSTREAM_READTIMESTAMP = _IOWR(KGSL_IOC_TYPE, 0x11, struct_kgsl_cmdstream_readtimestamp) +IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP = _IOW(KGSL_IOC_TYPE, 0x12, struct_kgsl_cmdstream_freememontimestamp) +IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD = _IOR(KGSL_IOC_TYPE, 0x12, struct_kgsl_cmdstream_freememontimestamp) +IOCTL_KGSL_DRAWCTXT_CREATE = _IOWR(KGSL_IOC_TYPE, 0x13, struct_kgsl_drawctxt_create) +IOCTL_KGSL_DRAWCTXT_DESTROY = _IOW(KGSL_IOC_TYPE, 0x14, struct_kgsl_drawctxt_destroy) +IOCTL_KGSL_MAP_USER_MEM = _IOWR(KGSL_IOC_TYPE, 0x15, struct_kgsl_map_user_mem) +IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID = _IOWR(KGSL_IOC_TYPE, 0x16, struct_kgsl_cmdstream_readtimestamp_ctxtid) +IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID = _IOW(KGSL_IOC_TYPE, 0x17, struct_kgsl_cmdstream_freememontimestamp_ctxtid) +IOCTL_KGSL_SHAREDMEM_FROM_PMEM = _IOWR(KGSL_IOC_TYPE, 0x20, struct_kgsl_sharedmem_from_pmem) +IOCTL_KGSL_SHAREDMEM_FREE = _IOW(KGSL_IOC_TYPE, 0x21, struct_kgsl_sharedmem_free) +IOCTL_KGSL_CFF_USER_EVENT = _IOW(KGSL_IOC_TYPE, 0x31, struct_kgsl_cff_user_event) +IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW = _IOW(KGSL_IOC_TYPE, 0x22, struct_kgsl_bind_gmem_shadow) +IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC = _IOWR(KGSL_IOC_TYPE, 0x23, struct_kgsl_sharedmem_from_vmalloc) +IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE = _IOW(KGSL_IOC_TYPE, 0x24, struct_kgsl_sharedmem_free) +IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET = _IOW(KGSL_IOC_TYPE, 0x25, struct_kgsl_drawctxt_set_bin_base_offset) +IOCTL_KGSL_CMDWINDOW_WRITE = _IOW(KGSL_IOC_TYPE, 0x2e, struct_kgsl_cmdwindow_write) +IOCTL_KGSL_GPUMEM_ALLOC = _IOWR(KGSL_IOC_TYPE, 0x2f, struct_kgsl_gpumem_alloc) +IOCTL_KGSL_CFF_SYNCMEM = _IOW(KGSL_IOC_TYPE, 0x30, struct_kgsl_cff_syncmem) +IOCTL_KGSL_TIMESTAMP_EVENT_OLD = _IOW(KGSL_IOC_TYPE, 0x31, struct_kgsl_timestamp_event) +KGSL_TIMESTAMP_EVENT_GENLOCK = 1 +KGSL_TIMESTAMP_EVENT_FENCE = 2 +IOCTL_KGSL_SETPROPERTY = _IOW(KGSL_IOC_TYPE, 0x32, struct_kgsl_device_getproperty) +IOCTL_KGSL_TIMESTAMP_EVENT = _IOWR(KGSL_IOC_TYPE, 0x33, struct_kgsl_timestamp_event) +IOCTL_KGSL_GPUMEM_ALLOC_ID = _IOWR(KGSL_IOC_TYPE, 0x34, struct_kgsl_gpumem_alloc_id) +IOCTL_KGSL_GPUMEM_FREE_ID = _IOWR(KGSL_IOC_TYPE, 0x35, struct_kgsl_gpumem_free_id) +IOCTL_KGSL_GPUMEM_GET_INFO = _IOWR(KGSL_IOC_TYPE, 0x36, struct_kgsl_gpumem_get_info) +KGSL_GPUMEM_CACHE_CLEAN = (1 << 0) +KGSL_GPUMEM_CACHE_TO_GPU = KGSL_GPUMEM_CACHE_CLEAN +KGSL_GPUMEM_CACHE_INV = (1 << 1) +KGSL_GPUMEM_CACHE_FROM_GPU = KGSL_GPUMEM_CACHE_INV +KGSL_GPUMEM_CACHE_FLUSH = (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV) +KGSL_GPUMEM_CACHE_RANGE = (1 << 31) +IOCTL_KGSL_GPUMEM_SYNC_CACHE = _IOW(KGSL_IOC_TYPE, 0x37, struct_kgsl_gpumem_sync_cache) +IOCTL_KGSL_PERFCOUNTER_GET = _IOWR(KGSL_IOC_TYPE, 0x38, struct_kgsl_perfcounter_get) +IOCTL_KGSL_PERFCOUNTER_PUT = _IOW(KGSL_IOC_TYPE, 0x39, struct_kgsl_perfcounter_put) +IOCTL_KGSL_PERFCOUNTER_QUERY = _IOWR(KGSL_IOC_TYPE, 0x3A, struct_kgsl_perfcounter_query) +IOCTL_KGSL_PERFCOUNTER_READ = _IOWR(KGSL_IOC_TYPE, 0x3B, struct_kgsl_perfcounter_read) +IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK = _IOWR(KGSL_IOC_TYPE, 0x3C, struct_kgsl_gpumem_sync_cache_bulk) +KGSL_IBDESC_MEMLIST = 0x1 +KGSL_IBDESC_PROFILING_BUFFER = 0x2 +IOCTL_KGSL_SUBMIT_COMMANDS = _IOWR(KGSL_IOC_TYPE, 0x3D, struct_kgsl_submit_commands) +KGSL_CONSTRAINT_NONE = 0 +KGSL_CONSTRAINT_PWRLEVEL = 1 +KGSL_CONSTRAINT_PWR_MIN = 0 +KGSL_CONSTRAINT_PWR_MAX = 1 +IOCTL_KGSL_SYNCSOURCE_CREATE = _IOWR(KGSL_IOC_TYPE, 0x40, struct_kgsl_syncsource_create) +IOCTL_KGSL_SYNCSOURCE_DESTROY = _IOWR(KGSL_IOC_TYPE, 0x41, struct_kgsl_syncsource_destroy) +IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE = _IOWR(KGSL_IOC_TYPE, 0x42, struct_kgsl_syncsource_create_fence) +IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE = _IOWR(KGSL_IOC_TYPE, 0x43, struct_kgsl_syncsource_signal_fence) +IOCTL_KGSL_CFF_SYNC_GPUOBJ = _IOW(KGSL_IOC_TYPE, 0x44, struct_kgsl_cff_sync_gpuobj) +KGSL_GPUOBJ_ALLOC_METADATA_MAX = 64 +IOCTL_KGSL_GPUOBJ_ALLOC = _IOWR(KGSL_IOC_TYPE, 0x45, struct_kgsl_gpuobj_alloc) +KGSL_GPUOBJ_FREE_ON_EVENT = 1 +KGSL_GPU_EVENT_TIMESTAMP = 1 +KGSL_GPU_EVENT_FENCE = 2 +IOCTL_KGSL_GPUOBJ_FREE = _IOW(KGSL_IOC_TYPE, 0x46, struct_kgsl_gpuobj_free) +IOCTL_KGSL_GPUOBJ_INFO = _IOWR(KGSL_IOC_TYPE, 0x47, struct_kgsl_gpuobj_info) +IOCTL_KGSL_GPUOBJ_IMPORT = _IOWR(KGSL_IOC_TYPE, 0x48, struct_kgsl_gpuobj_import) +IOCTL_KGSL_GPUOBJ_SYNC = _IOW(KGSL_IOC_TYPE, 0x49, struct_kgsl_gpuobj_sync) +IOCTL_KGSL_GPU_COMMAND = _IOWR(KGSL_IOC_TYPE, 0x4A, struct_kgsl_gpu_command) +IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY = _IOWR(KGSL_IOC_TYPE, 0x4B, struct_kgsl_preemption_counters_query) +KGSL_GPUOBJ_SET_INFO_METADATA = (1 << 0) +KGSL_GPUOBJ_SET_INFO_TYPE = (1 << 1) +IOCTL_KGSL_GPUOBJ_SET_INFO = _IOW(KGSL_IOC_TYPE, 0x4C, struct_kgsl_gpuobj_set_info) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/libusb.py b/tinygrad/runtime/autogen/libusb.py index 8911049310..6bb6de229e 100644 --- a/tinygrad/runtime/autogen/libusb.py +++ b/tinygrad/runtime/autogen/libusb.py @@ -1,1645 +1,830 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os +import ctypes, os +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(os.getenv('LIBUSB_PATH', find_library('usb-1.0')))) + except: pass + return None +dll = dll() - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['libusb'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['libusb'] = None if (lib_path:=os.getenv('LIBUSB_PATH', ctypes.util.find_library('usb-1.0'))) is None else ctypes.CDLL(lib_path) # ctypes.CDLL('libusb') -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -LIBUSB_H = True # macro -ZERO_SIZED_ARRAY = True # macro -# def LIBUSB_DEPRECATED_FOR(f): # macro -# return ((deprecated)) -# LIBUSB_PACKED = ((packed)) # macro -LIBUSB_CALL = True # macro -LIBUSB_API_VERSION = 0x01000109 # macro -LIBUSBX_API_VERSION = 0x01000109 # macro -LIBUSB_DT_DEVICE_SIZE = 18 # macro -LIBUSB_DT_CONFIG_SIZE = 9 # macro -LIBUSB_DT_INTERFACE_SIZE = 9 # macro -LIBUSB_DT_ENDPOINT_SIZE = 7 # macro -LIBUSB_DT_ENDPOINT_AUDIO_SIZE = 9 # macro -LIBUSB_DT_HUB_NONVAR_SIZE = 7 # macro -LIBUSB_DT_SS_ENDPOINT_COMPANION_SIZE = 6 # macro -LIBUSB_DT_BOS_SIZE = 5 # macro -LIBUSB_DT_DEVICE_CAPABILITY_SIZE = 3 # macro -LIBUSB_BT_USB_2_0_EXTENSION_SIZE = 7 # macro -LIBUSB_BT_SS_USB_DEVICE_CAPABILITY_SIZE = 10 # macro -LIBUSB_BT_CONTAINER_ID_SIZE = 20 # macro -LIBUSB_DT_BOS_MAX_SIZE = (5+7+10+20) # macro -LIBUSB_ENDPOINT_ADDRESS_MASK = 0x0f # macro -LIBUSB_ENDPOINT_DIR_MASK = 0x80 # macro -LIBUSB_TRANSFER_TYPE_MASK = 0x03 # macro -LIBUSB_ISO_SYNC_TYPE_MASK = 0x0c # macro -LIBUSB_ISO_USAGE_TYPE_MASK = 0x30 # macro -LIBUSB_ERROR_COUNT = 14 # macro -LIBUSB_HOTPLUG_NO_FLAGS = 0 # macro -LIBUSB_HOTPLUG_MATCH_ANY = -1 # macro +class _anonunion0(ctypes.Union): pass +uint8_t = ctypes.c_ubyte uint16_t = ctypes.c_uint16 -try: - libusb_cpu_to_le16 = _libraries['libusb'].libusb_cpu_to_le16 - libusb_cpu_to_le16.restype = uint16_t - libusb_cpu_to_le16.argtypes = [uint16_t] -except AttributeError: - pass - # macro +_anonunion0._fields_ = [ + ('b8', (uint8_t * 2)), + ('b16', uint16_t), +] +enum_libusb_class_code = CEnum(ctypes.c_uint32) +LIBUSB_CLASS_PER_INTERFACE = enum_libusb_class_code.define('LIBUSB_CLASS_PER_INTERFACE', 0) +LIBUSB_CLASS_AUDIO = enum_libusb_class_code.define('LIBUSB_CLASS_AUDIO', 1) +LIBUSB_CLASS_COMM = enum_libusb_class_code.define('LIBUSB_CLASS_COMM', 2) +LIBUSB_CLASS_HID = enum_libusb_class_code.define('LIBUSB_CLASS_HID', 3) +LIBUSB_CLASS_PHYSICAL = enum_libusb_class_code.define('LIBUSB_CLASS_PHYSICAL', 5) +LIBUSB_CLASS_IMAGE = enum_libusb_class_code.define('LIBUSB_CLASS_IMAGE', 6) +LIBUSB_CLASS_PTP = enum_libusb_class_code.define('LIBUSB_CLASS_PTP', 6) +LIBUSB_CLASS_PRINTER = enum_libusb_class_code.define('LIBUSB_CLASS_PRINTER', 7) +LIBUSB_CLASS_MASS_STORAGE = enum_libusb_class_code.define('LIBUSB_CLASS_MASS_STORAGE', 8) +LIBUSB_CLASS_HUB = enum_libusb_class_code.define('LIBUSB_CLASS_HUB', 9) +LIBUSB_CLASS_DATA = enum_libusb_class_code.define('LIBUSB_CLASS_DATA', 10) +LIBUSB_CLASS_SMART_CARD = enum_libusb_class_code.define('LIBUSB_CLASS_SMART_CARD', 11) +LIBUSB_CLASS_CONTENT_SECURITY = enum_libusb_class_code.define('LIBUSB_CLASS_CONTENT_SECURITY', 13) +LIBUSB_CLASS_VIDEO = enum_libusb_class_code.define('LIBUSB_CLASS_VIDEO', 14) +LIBUSB_CLASS_PERSONAL_HEALTHCARE = enum_libusb_class_code.define('LIBUSB_CLASS_PERSONAL_HEALTHCARE', 15) +LIBUSB_CLASS_DIAGNOSTIC_DEVICE = enum_libusb_class_code.define('LIBUSB_CLASS_DIAGNOSTIC_DEVICE', 220) +LIBUSB_CLASS_WIRELESS = enum_libusb_class_code.define('LIBUSB_CLASS_WIRELESS', 224) +LIBUSB_CLASS_MISCELLANEOUS = enum_libusb_class_code.define('LIBUSB_CLASS_MISCELLANEOUS', 239) +LIBUSB_CLASS_APPLICATION = enum_libusb_class_code.define('LIBUSB_CLASS_APPLICATION', 254) +LIBUSB_CLASS_VENDOR_SPEC = enum_libusb_class_code.define('LIBUSB_CLASS_VENDOR_SPEC', 255) -# values for enumeration 'libusb_class_code' -libusb_class_code__enumvalues = { - 0: 'LIBUSB_CLASS_PER_INTERFACE', - 1: 'LIBUSB_CLASS_AUDIO', - 2: 'LIBUSB_CLASS_COMM', - 3: 'LIBUSB_CLASS_HID', - 5: 'LIBUSB_CLASS_PHYSICAL', - 6: 'LIBUSB_CLASS_IMAGE', - 6: 'LIBUSB_CLASS_PTP', - 7: 'LIBUSB_CLASS_PRINTER', - 8: 'LIBUSB_CLASS_MASS_STORAGE', - 9: 'LIBUSB_CLASS_HUB', - 10: 'LIBUSB_CLASS_DATA', - 11: 'LIBUSB_CLASS_SMART_CARD', - 13: 'LIBUSB_CLASS_CONTENT_SECURITY', - 14: 'LIBUSB_CLASS_VIDEO', - 15: 'LIBUSB_CLASS_PERSONAL_HEALTHCARE', - 220: 'LIBUSB_CLASS_DIAGNOSTIC_DEVICE', - 224: 'LIBUSB_CLASS_WIRELESS', - 239: 'LIBUSB_CLASS_MISCELLANEOUS', - 254: 'LIBUSB_CLASS_APPLICATION', - 255: 'LIBUSB_CLASS_VENDOR_SPEC', -} -LIBUSB_CLASS_PER_INTERFACE = 0 -LIBUSB_CLASS_AUDIO = 1 -LIBUSB_CLASS_COMM = 2 -LIBUSB_CLASS_HID = 3 -LIBUSB_CLASS_PHYSICAL = 5 -LIBUSB_CLASS_IMAGE = 6 -LIBUSB_CLASS_PTP = 6 -LIBUSB_CLASS_PRINTER = 7 -LIBUSB_CLASS_MASS_STORAGE = 8 -LIBUSB_CLASS_HUB = 9 -LIBUSB_CLASS_DATA = 10 -LIBUSB_CLASS_SMART_CARD = 11 -LIBUSB_CLASS_CONTENT_SECURITY = 13 -LIBUSB_CLASS_VIDEO = 14 -LIBUSB_CLASS_PERSONAL_HEALTHCARE = 15 -LIBUSB_CLASS_DIAGNOSTIC_DEVICE = 220 -LIBUSB_CLASS_WIRELESS = 224 -LIBUSB_CLASS_MISCELLANEOUS = 239 -LIBUSB_CLASS_APPLICATION = 254 -LIBUSB_CLASS_VENDOR_SPEC = 255 -libusb_class_code = ctypes.c_uint32 # enum +enum_libusb_descriptor_type = CEnum(ctypes.c_uint32) +LIBUSB_DT_DEVICE = enum_libusb_descriptor_type.define('LIBUSB_DT_DEVICE', 1) +LIBUSB_DT_CONFIG = enum_libusb_descriptor_type.define('LIBUSB_DT_CONFIG', 2) +LIBUSB_DT_STRING = enum_libusb_descriptor_type.define('LIBUSB_DT_STRING', 3) +LIBUSB_DT_INTERFACE = enum_libusb_descriptor_type.define('LIBUSB_DT_INTERFACE', 4) +LIBUSB_DT_ENDPOINT = enum_libusb_descriptor_type.define('LIBUSB_DT_ENDPOINT', 5) +LIBUSB_DT_INTERFACE_ASSOCIATION = enum_libusb_descriptor_type.define('LIBUSB_DT_INTERFACE_ASSOCIATION', 11) +LIBUSB_DT_BOS = enum_libusb_descriptor_type.define('LIBUSB_DT_BOS', 15) +LIBUSB_DT_DEVICE_CAPABILITY = enum_libusb_descriptor_type.define('LIBUSB_DT_DEVICE_CAPABILITY', 16) +LIBUSB_DT_HID = enum_libusb_descriptor_type.define('LIBUSB_DT_HID', 33) +LIBUSB_DT_REPORT = enum_libusb_descriptor_type.define('LIBUSB_DT_REPORT', 34) +LIBUSB_DT_PHYSICAL = enum_libusb_descriptor_type.define('LIBUSB_DT_PHYSICAL', 35) +LIBUSB_DT_HUB = enum_libusb_descriptor_type.define('LIBUSB_DT_HUB', 41) +LIBUSB_DT_SUPERSPEED_HUB = enum_libusb_descriptor_type.define('LIBUSB_DT_SUPERSPEED_HUB', 42) +LIBUSB_DT_SS_ENDPOINT_COMPANION = enum_libusb_descriptor_type.define('LIBUSB_DT_SS_ENDPOINT_COMPANION', 48) -# values for enumeration 'libusb_descriptor_type' -libusb_descriptor_type__enumvalues = { - 1: 'LIBUSB_DT_DEVICE', - 2: 'LIBUSB_DT_CONFIG', - 3: 'LIBUSB_DT_STRING', - 4: 'LIBUSB_DT_INTERFACE', - 5: 'LIBUSB_DT_ENDPOINT', - 15: 'LIBUSB_DT_BOS', - 16: 'LIBUSB_DT_DEVICE_CAPABILITY', - 33: 'LIBUSB_DT_HID', - 34: 'LIBUSB_DT_REPORT', - 35: 'LIBUSB_DT_PHYSICAL', - 41: 'LIBUSB_DT_HUB', - 42: 'LIBUSB_DT_SUPERSPEED_HUB', - 48: 'LIBUSB_DT_SS_ENDPOINT_COMPANION', -} -LIBUSB_DT_DEVICE = 1 -LIBUSB_DT_CONFIG = 2 -LIBUSB_DT_STRING = 3 -LIBUSB_DT_INTERFACE = 4 -LIBUSB_DT_ENDPOINT = 5 -LIBUSB_DT_BOS = 15 -LIBUSB_DT_DEVICE_CAPABILITY = 16 -LIBUSB_DT_HID = 33 -LIBUSB_DT_REPORT = 34 -LIBUSB_DT_PHYSICAL = 35 -LIBUSB_DT_HUB = 41 -LIBUSB_DT_SUPERSPEED_HUB = 42 -LIBUSB_DT_SS_ENDPOINT_COMPANION = 48 -libusb_descriptor_type = ctypes.c_uint32 # enum +enum_libusb_endpoint_direction = CEnum(ctypes.c_uint32) +LIBUSB_ENDPOINT_OUT = enum_libusb_endpoint_direction.define('LIBUSB_ENDPOINT_OUT', 0) +LIBUSB_ENDPOINT_IN = enum_libusb_endpoint_direction.define('LIBUSB_ENDPOINT_IN', 128) -# values for enumeration 'libusb_endpoint_direction' -libusb_endpoint_direction__enumvalues = { - 0: 'LIBUSB_ENDPOINT_OUT', - 128: 'LIBUSB_ENDPOINT_IN', -} -LIBUSB_ENDPOINT_OUT = 0 -LIBUSB_ENDPOINT_IN = 128 -libusb_endpoint_direction = ctypes.c_uint32 # enum +enum_libusb_endpoint_transfer_type = CEnum(ctypes.c_uint32) +LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL = enum_libusb_endpoint_transfer_type.define('LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL', 0) +LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS = enum_libusb_endpoint_transfer_type.define('LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS', 1) +LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK = enum_libusb_endpoint_transfer_type.define('LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK', 2) +LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT = enum_libusb_endpoint_transfer_type.define('LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT', 3) -# values for enumeration 'libusb_endpoint_transfer_type' -libusb_endpoint_transfer_type__enumvalues = { - 0: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL', - 1: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS', - 2: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK', - 3: 'LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT', -} -LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL = 0 -LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS = 1 -LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK = 2 -LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT = 3 -libusb_endpoint_transfer_type = ctypes.c_uint32 # enum +enum_libusb_standard_request = CEnum(ctypes.c_uint32) +LIBUSB_REQUEST_GET_STATUS = enum_libusb_standard_request.define('LIBUSB_REQUEST_GET_STATUS', 0) +LIBUSB_REQUEST_CLEAR_FEATURE = enum_libusb_standard_request.define('LIBUSB_REQUEST_CLEAR_FEATURE', 1) +LIBUSB_REQUEST_SET_FEATURE = enum_libusb_standard_request.define('LIBUSB_REQUEST_SET_FEATURE', 3) +LIBUSB_REQUEST_SET_ADDRESS = enum_libusb_standard_request.define('LIBUSB_REQUEST_SET_ADDRESS', 5) +LIBUSB_REQUEST_GET_DESCRIPTOR = enum_libusb_standard_request.define('LIBUSB_REQUEST_GET_DESCRIPTOR', 6) +LIBUSB_REQUEST_SET_DESCRIPTOR = enum_libusb_standard_request.define('LIBUSB_REQUEST_SET_DESCRIPTOR', 7) +LIBUSB_REQUEST_GET_CONFIGURATION = enum_libusb_standard_request.define('LIBUSB_REQUEST_GET_CONFIGURATION', 8) +LIBUSB_REQUEST_SET_CONFIGURATION = enum_libusb_standard_request.define('LIBUSB_REQUEST_SET_CONFIGURATION', 9) +LIBUSB_REQUEST_GET_INTERFACE = enum_libusb_standard_request.define('LIBUSB_REQUEST_GET_INTERFACE', 10) +LIBUSB_REQUEST_SET_INTERFACE = enum_libusb_standard_request.define('LIBUSB_REQUEST_SET_INTERFACE', 11) +LIBUSB_REQUEST_SYNCH_FRAME = enum_libusb_standard_request.define('LIBUSB_REQUEST_SYNCH_FRAME', 12) +LIBUSB_REQUEST_SET_SEL = enum_libusb_standard_request.define('LIBUSB_REQUEST_SET_SEL', 48) +LIBUSB_SET_ISOCH_DELAY = enum_libusb_standard_request.define('LIBUSB_SET_ISOCH_DELAY', 49) -# values for enumeration 'libusb_standard_request' -libusb_standard_request__enumvalues = { - 0: 'LIBUSB_REQUEST_GET_STATUS', - 1: 'LIBUSB_REQUEST_CLEAR_FEATURE', - 3: 'LIBUSB_REQUEST_SET_FEATURE', - 5: 'LIBUSB_REQUEST_SET_ADDRESS', - 6: 'LIBUSB_REQUEST_GET_DESCRIPTOR', - 7: 'LIBUSB_REQUEST_SET_DESCRIPTOR', - 8: 'LIBUSB_REQUEST_GET_CONFIGURATION', - 9: 'LIBUSB_REQUEST_SET_CONFIGURATION', - 10: 'LIBUSB_REQUEST_GET_INTERFACE', - 11: 'LIBUSB_REQUEST_SET_INTERFACE', - 12: 'LIBUSB_REQUEST_SYNCH_FRAME', - 48: 'LIBUSB_REQUEST_SET_SEL', - 49: 'LIBUSB_SET_ISOCH_DELAY', -} -LIBUSB_REQUEST_GET_STATUS = 0 -LIBUSB_REQUEST_CLEAR_FEATURE = 1 -LIBUSB_REQUEST_SET_FEATURE = 3 -LIBUSB_REQUEST_SET_ADDRESS = 5 -LIBUSB_REQUEST_GET_DESCRIPTOR = 6 -LIBUSB_REQUEST_SET_DESCRIPTOR = 7 -LIBUSB_REQUEST_GET_CONFIGURATION = 8 -LIBUSB_REQUEST_SET_CONFIGURATION = 9 -LIBUSB_REQUEST_GET_INTERFACE = 10 -LIBUSB_REQUEST_SET_INTERFACE = 11 -LIBUSB_REQUEST_SYNCH_FRAME = 12 -LIBUSB_REQUEST_SET_SEL = 48 -LIBUSB_SET_ISOCH_DELAY = 49 -libusb_standard_request = ctypes.c_uint32 # enum +enum_libusb_request_type = CEnum(ctypes.c_uint32) +LIBUSB_REQUEST_TYPE_STANDARD = enum_libusb_request_type.define('LIBUSB_REQUEST_TYPE_STANDARD', 0) +LIBUSB_REQUEST_TYPE_CLASS = enum_libusb_request_type.define('LIBUSB_REQUEST_TYPE_CLASS', 32) +LIBUSB_REQUEST_TYPE_VENDOR = enum_libusb_request_type.define('LIBUSB_REQUEST_TYPE_VENDOR', 64) +LIBUSB_REQUEST_TYPE_RESERVED = enum_libusb_request_type.define('LIBUSB_REQUEST_TYPE_RESERVED', 96) -# values for enumeration 'libusb_request_type' -libusb_request_type__enumvalues = { - 0: 'LIBUSB_REQUEST_TYPE_STANDARD', - 32: 'LIBUSB_REQUEST_TYPE_CLASS', - 64: 'LIBUSB_REQUEST_TYPE_VENDOR', - 96: 'LIBUSB_REQUEST_TYPE_RESERVED', -} -LIBUSB_REQUEST_TYPE_STANDARD = 0 -LIBUSB_REQUEST_TYPE_CLASS = 32 -LIBUSB_REQUEST_TYPE_VENDOR = 64 -LIBUSB_REQUEST_TYPE_RESERVED = 96 -libusb_request_type = ctypes.c_uint32 # enum +enum_libusb_request_recipient = CEnum(ctypes.c_uint32) +LIBUSB_RECIPIENT_DEVICE = enum_libusb_request_recipient.define('LIBUSB_RECIPIENT_DEVICE', 0) +LIBUSB_RECIPIENT_INTERFACE = enum_libusb_request_recipient.define('LIBUSB_RECIPIENT_INTERFACE', 1) +LIBUSB_RECIPIENT_ENDPOINT = enum_libusb_request_recipient.define('LIBUSB_RECIPIENT_ENDPOINT', 2) +LIBUSB_RECIPIENT_OTHER = enum_libusb_request_recipient.define('LIBUSB_RECIPIENT_OTHER', 3) -# values for enumeration 'libusb_request_recipient' -libusb_request_recipient__enumvalues = { - 0: 'LIBUSB_RECIPIENT_DEVICE', - 1: 'LIBUSB_RECIPIENT_INTERFACE', - 2: 'LIBUSB_RECIPIENT_ENDPOINT', - 3: 'LIBUSB_RECIPIENT_OTHER', -} -LIBUSB_RECIPIENT_DEVICE = 0 -LIBUSB_RECIPIENT_INTERFACE = 1 -LIBUSB_RECIPIENT_ENDPOINT = 2 -LIBUSB_RECIPIENT_OTHER = 3 -libusb_request_recipient = ctypes.c_uint32 # enum +enum_libusb_iso_sync_type = CEnum(ctypes.c_uint32) +LIBUSB_ISO_SYNC_TYPE_NONE = enum_libusb_iso_sync_type.define('LIBUSB_ISO_SYNC_TYPE_NONE', 0) +LIBUSB_ISO_SYNC_TYPE_ASYNC = enum_libusb_iso_sync_type.define('LIBUSB_ISO_SYNC_TYPE_ASYNC', 1) +LIBUSB_ISO_SYNC_TYPE_ADAPTIVE = enum_libusb_iso_sync_type.define('LIBUSB_ISO_SYNC_TYPE_ADAPTIVE', 2) +LIBUSB_ISO_SYNC_TYPE_SYNC = enum_libusb_iso_sync_type.define('LIBUSB_ISO_SYNC_TYPE_SYNC', 3) -# values for enumeration 'libusb_iso_sync_type' -libusb_iso_sync_type__enumvalues = { - 0: 'LIBUSB_ISO_SYNC_TYPE_NONE', - 1: 'LIBUSB_ISO_SYNC_TYPE_ASYNC', - 2: 'LIBUSB_ISO_SYNC_TYPE_ADAPTIVE', - 3: 'LIBUSB_ISO_SYNC_TYPE_SYNC', -} -LIBUSB_ISO_SYNC_TYPE_NONE = 0 -LIBUSB_ISO_SYNC_TYPE_ASYNC = 1 -LIBUSB_ISO_SYNC_TYPE_ADAPTIVE = 2 -LIBUSB_ISO_SYNC_TYPE_SYNC = 3 -libusb_iso_sync_type = ctypes.c_uint32 # enum +enum_libusb_iso_usage_type = CEnum(ctypes.c_uint32) +LIBUSB_ISO_USAGE_TYPE_DATA = enum_libusb_iso_usage_type.define('LIBUSB_ISO_USAGE_TYPE_DATA', 0) +LIBUSB_ISO_USAGE_TYPE_FEEDBACK = enum_libusb_iso_usage_type.define('LIBUSB_ISO_USAGE_TYPE_FEEDBACK', 1) +LIBUSB_ISO_USAGE_TYPE_IMPLICIT = enum_libusb_iso_usage_type.define('LIBUSB_ISO_USAGE_TYPE_IMPLICIT', 2) -# values for enumeration 'libusb_iso_usage_type' -libusb_iso_usage_type__enumvalues = { - 0: 'LIBUSB_ISO_USAGE_TYPE_DATA', - 1: 'LIBUSB_ISO_USAGE_TYPE_FEEDBACK', - 2: 'LIBUSB_ISO_USAGE_TYPE_IMPLICIT', -} -LIBUSB_ISO_USAGE_TYPE_DATA = 0 -LIBUSB_ISO_USAGE_TYPE_FEEDBACK = 1 -LIBUSB_ISO_USAGE_TYPE_IMPLICIT = 2 -libusb_iso_usage_type = ctypes.c_uint32 # enum +enum_libusb_supported_speed = CEnum(ctypes.c_uint32) +LIBUSB_LOW_SPEED_OPERATION = enum_libusb_supported_speed.define('LIBUSB_LOW_SPEED_OPERATION', 1) +LIBUSB_FULL_SPEED_OPERATION = enum_libusb_supported_speed.define('LIBUSB_FULL_SPEED_OPERATION', 2) +LIBUSB_HIGH_SPEED_OPERATION = enum_libusb_supported_speed.define('LIBUSB_HIGH_SPEED_OPERATION', 4) +LIBUSB_SUPER_SPEED_OPERATION = enum_libusb_supported_speed.define('LIBUSB_SUPER_SPEED_OPERATION', 8) -# values for enumeration 'libusb_supported_speed' -libusb_supported_speed__enumvalues = { - 1: 'LIBUSB_LOW_SPEED_OPERATION', - 2: 'LIBUSB_FULL_SPEED_OPERATION', - 4: 'LIBUSB_HIGH_SPEED_OPERATION', - 8: 'LIBUSB_SUPER_SPEED_OPERATION', -} -LIBUSB_LOW_SPEED_OPERATION = 1 -LIBUSB_FULL_SPEED_OPERATION = 2 -LIBUSB_HIGH_SPEED_OPERATION = 4 -LIBUSB_SUPER_SPEED_OPERATION = 8 -libusb_supported_speed = ctypes.c_uint32 # enum +enum_libusb_usb_2_0_extension_attributes = CEnum(ctypes.c_uint32) +LIBUSB_BM_LPM_SUPPORT = enum_libusb_usb_2_0_extension_attributes.define('LIBUSB_BM_LPM_SUPPORT', 2) -# values for enumeration 'libusb_usb_2_0_extension_attributes' -libusb_usb_2_0_extension_attributes__enumvalues = { - 2: 'LIBUSB_BM_LPM_SUPPORT', -} -LIBUSB_BM_LPM_SUPPORT = 2 -libusb_usb_2_0_extension_attributes = ctypes.c_uint32 # enum +enum_libusb_ss_usb_device_capability_attributes = CEnum(ctypes.c_uint32) +LIBUSB_BM_LTM_SUPPORT = enum_libusb_ss_usb_device_capability_attributes.define('LIBUSB_BM_LTM_SUPPORT', 2) -# values for enumeration 'libusb_ss_usb_device_capability_attributes' -libusb_ss_usb_device_capability_attributes__enumvalues = { - 2: 'LIBUSB_BM_LTM_SUPPORT', -} -LIBUSB_BM_LTM_SUPPORT = 2 -libusb_ss_usb_device_capability_attributes = ctypes.c_uint32 # enum +enum_libusb_bos_type = CEnum(ctypes.c_uint32) +LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY = enum_libusb_bos_type.define('LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY', 1) +LIBUSB_BT_USB_2_0_EXTENSION = enum_libusb_bos_type.define('LIBUSB_BT_USB_2_0_EXTENSION', 2) +LIBUSB_BT_SS_USB_DEVICE_CAPABILITY = enum_libusb_bos_type.define('LIBUSB_BT_SS_USB_DEVICE_CAPABILITY', 3) +LIBUSB_BT_CONTAINER_ID = enum_libusb_bos_type.define('LIBUSB_BT_CONTAINER_ID', 4) +LIBUSB_BT_PLATFORM_DESCRIPTOR = enum_libusb_bos_type.define('LIBUSB_BT_PLATFORM_DESCRIPTOR', 5) -# values for enumeration 'libusb_bos_type' -libusb_bos_type__enumvalues = { - 1: 'LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY', - 2: 'LIBUSB_BT_USB_2_0_EXTENSION', - 3: 'LIBUSB_BT_SS_USB_DEVICE_CAPABILITY', - 4: 'LIBUSB_BT_CONTAINER_ID', -} -LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY = 1 -LIBUSB_BT_USB_2_0_EXTENSION = 2 -LIBUSB_BT_SS_USB_DEVICE_CAPABILITY = 3 -LIBUSB_BT_CONTAINER_ID = 4 -libusb_bos_type = ctypes.c_uint32 # enum -class struct_libusb_device_descriptor(Structure): - pass - -struct_libusb_device_descriptor._pack_ = 1 # source:False +class struct_libusb_device_descriptor(Struct): pass struct_libusb_device_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bcdUSB', ctypes.c_uint16), - ('bDeviceClass', ctypes.c_ubyte), - ('bDeviceSubClass', ctypes.c_ubyte), - ('bDeviceProtocol', ctypes.c_ubyte), - ('bMaxPacketSize0', ctypes.c_ubyte), - ('idVendor', ctypes.c_uint16), - ('idProduct', ctypes.c_uint16), - ('bcdDevice', ctypes.c_uint16), - ('iManufacturer', ctypes.c_ubyte), - ('iProduct', ctypes.c_ubyte), - ('iSerialNumber', ctypes.c_ubyte), - ('bNumConfigurations', ctypes.c_ubyte), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bcdUSB', uint16_t), + ('bDeviceClass', uint8_t), + ('bDeviceSubClass', uint8_t), + ('bDeviceProtocol', uint8_t), + ('bMaxPacketSize0', uint8_t), + ('idVendor', uint16_t), + ('idProduct', uint16_t), + ('bcdDevice', uint16_t), + ('iManufacturer', uint8_t), + ('iProduct', uint8_t), + ('iSerialNumber', uint8_t), + ('bNumConfigurations', uint8_t), ] - -class struct_libusb_endpoint_descriptor(Structure): - pass - -struct_libusb_endpoint_descriptor._pack_ = 1 # source:False +class struct_libusb_endpoint_descriptor(Struct): pass struct_libusb_endpoint_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bEndpointAddress', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('wMaxPacketSize', ctypes.c_uint16), - ('bInterval', ctypes.c_ubyte), - ('bRefresh', ctypes.c_ubyte), - ('bSynchAddress', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('extra', ctypes.POINTER(ctypes.c_ubyte)), - ('extra_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bEndpointAddress', uint8_t), + ('bmAttributes', uint8_t), + ('wMaxPacketSize', uint16_t), + ('bInterval', uint8_t), + ('bRefresh', uint8_t), + ('bSynchAddress', uint8_t), + ('extra', ctypes.POINTER(ctypes.c_ubyte)), + ('extra_length', ctypes.c_int32), ] - -class struct_libusb_interface_descriptor(Structure): - pass - -struct_libusb_interface_descriptor._pack_ = 1 # source:False +class struct_libusb_interface_association_descriptor(Struct): pass +struct_libusb_interface_association_descriptor._fields_ = [ + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bFirstInterface', uint8_t), + ('bInterfaceCount', uint8_t), + ('bFunctionClass', uint8_t), + ('bFunctionSubClass', uint8_t), + ('bFunctionProtocol', uint8_t), + ('iFunction', uint8_t), +] +class struct_libusb_interface_association_descriptor_array(Struct): pass +struct_libusb_interface_association_descriptor_array._fields_ = [ + ('iad', ctypes.POINTER(struct_libusb_interface_association_descriptor)), + ('length', ctypes.c_int32), +] +class struct_libusb_interface_descriptor(Struct): pass struct_libusb_interface_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bInterfaceNumber', ctypes.c_ubyte), - ('bAlternateSetting', ctypes.c_ubyte), - ('bNumEndpoints', ctypes.c_ubyte), - ('bInterfaceClass', ctypes.c_ubyte), - ('bInterfaceSubClass', ctypes.c_ubyte), - ('bInterfaceProtocol', ctypes.c_ubyte), - ('iInterface', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('endpoint', ctypes.POINTER(struct_libusb_endpoint_descriptor)), - ('extra', ctypes.POINTER(ctypes.c_ubyte)), - ('extra_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bInterfaceNumber', uint8_t), + ('bAlternateSetting', uint8_t), + ('bNumEndpoints', uint8_t), + ('bInterfaceClass', uint8_t), + ('bInterfaceSubClass', uint8_t), + ('bInterfaceProtocol', uint8_t), + ('iInterface', uint8_t), + ('endpoint', ctypes.POINTER(struct_libusb_endpoint_descriptor)), + ('extra', ctypes.POINTER(ctypes.c_ubyte)), + ('extra_length', ctypes.c_int32), ] - -class struct_libusb_interface(Structure): - pass - -struct_libusb_interface._pack_ = 1 # source:False +class struct_libusb_interface(Struct): pass struct_libusb_interface._fields_ = [ - ('altsetting', ctypes.POINTER(struct_libusb_interface_descriptor)), - ('num_altsetting', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('altsetting', ctypes.POINTER(struct_libusb_interface_descriptor)), + ('num_altsetting', ctypes.c_int32), ] - -class struct_libusb_config_descriptor(Structure): - pass - -struct_libusb_config_descriptor._pack_ = 1 # source:False +class struct_libusb_config_descriptor(Struct): pass struct_libusb_config_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('wTotalLength', ctypes.c_uint16), - ('bNumInterfaces', ctypes.c_ubyte), - ('bConfigurationValue', ctypes.c_ubyte), - ('iConfiguration', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('MaxPower', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('interface', ctypes.POINTER(struct_libusb_interface)), - ('extra', ctypes.POINTER(ctypes.c_ubyte)), - ('extra_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('wTotalLength', uint16_t), + ('bNumInterfaces', uint8_t), + ('bConfigurationValue', uint8_t), + ('iConfiguration', uint8_t), + ('bmAttributes', uint8_t), + ('MaxPower', uint8_t), + ('interface', ctypes.POINTER(struct_libusb_interface)), + ('extra', ctypes.POINTER(ctypes.c_ubyte)), + ('extra_length', ctypes.c_int32), ] - -class struct_libusb_ss_endpoint_companion_descriptor(Structure): - pass - -struct_libusb_ss_endpoint_companion_descriptor._pack_ = 1 # source:False +class struct_libusb_ss_endpoint_companion_descriptor(Struct): pass struct_libusb_ss_endpoint_companion_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bMaxBurst', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('wBytesPerInterval', ctypes.c_uint16), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bMaxBurst', uint8_t), + ('bmAttributes', uint8_t), + ('wBytesPerInterval', uint16_t), ] - -class struct_libusb_bos_dev_capability_descriptor(Structure): - pass - -struct_libusb_bos_dev_capability_descriptor._pack_ = 1 # source:False +class struct_libusb_bos_dev_capability_descriptor(Struct): pass struct_libusb_bos_dev_capability_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('dev_capability_data', ctypes.c_ubyte * 0), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bDevCapabilityType', uint8_t), + ('dev_capability_data', (uint8_t * 0)), ] - -class struct_libusb_bos_descriptor(Structure): - pass - -struct_libusb_bos_descriptor._pack_ = 1 # source:False +class struct_libusb_bos_descriptor(Struct): pass struct_libusb_bos_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('wTotalLength', ctypes.c_uint16), - ('bNumDeviceCaps', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('dev_capability', ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor) * 0), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('wTotalLength', uint16_t), + ('bNumDeviceCaps', uint8_t), + ('dev_capability', (ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor) * 0)), ] - -class struct_libusb_usb_2_0_extension_descriptor(Structure): - pass - -struct_libusb_usb_2_0_extension_descriptor._pack_ = 1 # source:False +class struct_libusb_usb_2_0_extension_descriptor(Struct): pass +uint32_t = ctypes.c_uint32 struct_libusb_usb_2_0_extension_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_uint32), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bDevCapabilityType', uint8_t), + ('bmAttributes', uint32_t), ] - -class struct_libusb_ss_usb_device_capability_descriptor(Structure): - pass - -struct_libusb_ss_usb_device_capability_descriptor._pack_ = 1 # source:False +class struct_libusb_ss_usb_device_capability_descriptor(Struct): pass struct_libusb_ss_usb_device_capability_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('bmAttributes', ctypes.c_ubyte), - ('wSpeedSupported', ctypes.c_uint16), - ('bFunctionalitySupport', ctypes.c_ubyte), - ('bU1DevExitLat', ctypes.c_ubyte), - ('bU2DevExitLat', ctypes.c_uint16), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bDevCapabilityType', uint8_t), + ('bmAttributes', uint8_t), + ('wSpeedSupported', uint16_t), + ('bFunctionalitySupport', uint8_t), + ('bU1DevExitLat', uint8_t), + ('bU2DevExitLat', uint16_t), ] - -class struct_libusb_container_id_descriptor(Structure): - pass - -struct_libusb_container_id_descriptor._pack_ = 1 # source:False +class struct_libusb_container_id_descriptor(Struct): pass struct_libusb_container_id_descriptor._fields_ = [ - ('bLength', ctypes.c_ubyte), - ('bDescriptorType', ctypes.c_ubyte), - ('bDevCapabilityType', ctypes.c_ubyte), - ('bReserved', ctypes.c_ubyte), - ('ContainerID', ctypes.c_ubyte * 16), + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bDevCapabilityType', uint8_t), + ('bReserved', uint8_t), + ('ContainerID', (uint8_t * 16)), ] - -class struct_libusb_control_setup(Structure): - pass - -struct_libusb_control_setup._pack_ = 1 # source:True +class struct_libusb_platform_descriptor(Struct): pass +struct_libusb_platform_descriptor._fields_ = [ + ('bLength', uint8_t), + ('bDescriptorType', uint8_t), + ('bDevCapabilityType', uint8_t), + ('bReserved', uint8_t), + ('PlatformCapabilityUUID', (uint8_t * 16)), + ('CapabilityData', (uint8_t * 0)), +] +class struct_libusb_control_setup(Struct): pass +struct_libusb_control_setup._packed_ = True struct_libusb_control_setup._fields_ = [ - ('bmRequestType', ctypes.c_ubyte), - ('bRequest', ctypes.c_ubyte), - ('wValue', ctypes.c_uint16), - ('wIndex', ctypes.c_uint16), - ('wLength', ctypes.c_uint16), + ('bmRequestType', uint8_t), + ('bRequest', uint8_t), + ('wValue', uint16_t), + ('wIndex', uint16_t), + ('wLength', uint16_t), ] - -# LIBUSB_CONTROL_SETUP_SIZE = (ctypes.sizeof(struct_libusb_control_setup)) # macro -class struct_libusb_context(Structure): - pass - -class struct_libusb_device(Structure): - pass - -class struct_libusb_device_handle(Structure): - pass - -class struct_libusb_version(Structure): - pass - -struct_libusb_version._pack_ = 1 # source:False +class struct_libusb_context(Struct): pass +class struct_libusb_device(Struct): pass +class struct_libusb_device_handle(Struct): pass +class struct_libusb_version(Struct): pass struct_libusb_version._fields_ = [ - ('major', ctypes.c_uint16), - ('minor', ctypes.c_uint16), - ('micro', ctypes.c_uint16), - ('nano', ctypes.c_uint16), - ('rc', ctypes.POINTER(ctypes.c_char)), - ('describe', ctypes.POINTER(ctypes.c_char)), + ('major', uint16_t), + ('minor', uint16_t), + ('micro', uint16_t), + ('nano', uint16_t), + ('rc', ctypes.POINTER(ctypes.c_char)), + ('describe', ctypes.POINTER(ctypes.c_char)), ] - libusb_context = struct_libusb_context libusb_device = struct_libusb_device libusb_device_handle = struct_libusb_device_handle +enum_libusb_speed = CEnum(ctypes.c_uint32) +LIBUSB_SPEED_UNKNOWN = enum_libusb_speed.define('LIBUSB_SPEED_UNKNOWN', 0) +LIBUSB_SPEED_LOW = enum_libusb_speed.define('LIBUSB_SPEED_LOW', 1) +LIBUSB_SPEED_FULL = enum_libusb_speed.define('LIBUSB_SPEED_FULL', 2) +LIBUSB_SPEED_HIGH = enum_libusb_speed.define('LIBUSB_SPEED_HIGH', 3) +LIBUSB_SPEED_SUPER = enum_libusb_speed.define('LIBUSB_SPEED_SUPER', 4) +LIBUSB_SPEED_SUPER_PLUS = enum_libusb_speed.define('LIBUSB_SPEED_SUPER_PLUS', 5) -# values for enumeration 'libusb_speed' -libusb_speed__enumvalues = { - 0: 'LIBUSB_SPEED_UNKNOWN', - 1: 'LIBUSB_SPEED_LOW', - 2: 'LIBUSB_SPEED_FULL', - 3: 'LIBUSB_SPEED_HIGH', - 4: 'LIBUSB_SPEED_SUPER', - 5: 'LIBUSB_SPEED_SUPER_PLUS', -} -LIBUSB_SPEED_UNKNOWN = 0 -LIBUSB_SPEED_LOW = 1 -LIBUSB_SPEED_FULL = 2 -LIBUSB_SPEED_HIGH = 3 -LIBUSB_SPEED_SUPER = 4 -LIBUSB_SPEED_SUPER_PLUS = 5 -libusb_speed = ctypes.c_uint32 # enum +enum_libusb_error = CEnum(ctypes.c_int32) +LIBUSB_SUCCESS = enum_libusb_error.define('LIBUSB_SUCCESS', 0) +LIBUSB_ERROR_IO = enum_libusb_error.define('LIBUSB_ERROR_IO', -1) +LIBUSB_ERROR_INVALID_PARAM = enum_libusb_error.define('LIBUSB_ERROR_INVALID_PARAM', -2) +LIBUSB_ERROR_ACCESS = enum_libusb_error.define('LIBUSB_ERROR_ACCESS', -3) +LIBUSB_ERROR_NO_DEVICE = enum_libusb_error.define('LIBUSB_ERROR_NO_DEVICE', -4) +LIBUSB_ERROR_NOT_FOUND = enum_libusb_error.define('LIBUSB_ERROR_NOT_FOUND', -5) +LIBUSB_ERROR_BUSY = enum_libusb_error.define('LIBUSB_ERROR_BUSY', -6) +LIBUSB_ERROR_TIMEOUT = enum_libusb_error.define('LIBUSB_ERROR_TIMEOUT', -7) +LIBUSB_ERROR_OVERFLOW = enum_libusb_error.define('LIBUSB_ERROR_OVERFLOW', -8) +LIBUSB_ERROR_PIPE = enum_libusb_error.define('LIBUSB_ERROR_PIPE', -9) +LIBUSB_ERROR_INTERRUPTED = enum_libusb_error.define('LIBUSB_ERROR_INTERRUPTED', -10) +LIBUSB_ERROR_NO_MEM = enum_libusb_error.define('LIBUSB_ERROR_NO_MEM', -11) +LIBUSB_ERROR_NOT_SUPPORTED = enum_libusb_error.define('LIBUSB_ERROR_NOT_SUPPORTED', -12) +LIBUSB_ERROR_OTHER = enum_libusb_error.define('LIBUSB_ERROR_OTHER', -99) -# values for enumeration 'libusb_error' -libusb_error__enumvalues = { - 0: 'LIBUSB_SUCCESS', - -1: 'LIBUSB_ERROR_IO', - -2: 'LIBUSB_ERROR_INVALID_PARAM', - -3: 'LIBUSB_ERROR_ACCESS', - -4: 'LIBUSB_ERROR_NO_DEVICE', - -5: 'LIBUSB_ERROR_NOT_FOUND', - -6: 'LIBUSB_ERROR_BUSY', - -7: 'LIBUSB_ERROR_TIMEOUT', - -8: 'LIBUSB_ERROR_OVERFLOW', - -9: 'LIBUSB_ERROR_PIPE', - -10: 'LIBUSB_ERROR_INTERRUPTED', - -11: 'LIBUSB_ERROR_NO_MEM', - -12: 'LIBUSB_ERROR_NOT_SUPPORTED', - -99: 'LIBUSB_ERROR_OTHER', -} -LIBUSB_SUCCESS = 0 -LIBUSB_ERROR_IO = -1 -LIBUSB_ERROR_INVALID_PARAM = -2 -LIBUSB_ERROR_ACCESS = -3 -LIBUSB_ERROR_NO_DEVICE = -4 -LIBUSB_ERROR_NOT_FOUND = -5 -LIBUSB_ERROR_BUSY = -6 -LIBUSB_ERROR_TIMEOUT = -7 -LIBUSB_ERROR_OVERFLOW = -8 -LIBUSB_ERROR_PIPE = -9 -LIBUSB_ERROR_INTERRUPTED = -10 -LIBUSB_ERROR_NO_MEM = -11 -LIBUSB_ERROR_NOT_SUPPORTED = -12 -LIBUSB_ERROR_OTHER = -99 -libusb_error = ctypes.c_int32 # enum +enum_libusb_transfer_type = CEnum(ctypes.c_uint32) +LIBUSB_TRANSFER_TYPE_CONTROL = enum_libusb_transfer_type.define('LIBUSB_TRANSFER_TYPE_CONTROL', 0) +LIBUSB_TRANSFER_TYPE_ISOCHRONOUS = enum_libusb_transfer_type.define('LIBUSB_TRANSFER_TYPE_ISOCHRONOUS', 1) +LIBUSB_TRANSFER_TYPE_BULK = enum_libusb_transfer_type.define('LIBUSB_TRANSFER_TYPE_BULK', 2) +LIBUSB_TRANSFER_TYPE_INTERRUPT = enum_libusb_transfer_type.define('LIBUSB_TRANSFER_TYPE_INTERRUPT', 3) +LIBUSB_TRANSFER_TYPE_BULK_STREAM = enum_libusb_transfer_type.define('LIBUSB_TRANSFER_TYPE_BULK_STREAM', 4) -# values for enumeration 'libusb_transfer_type' -libusb_transfer_type__enumvalues = { - 0: 'LIBUSB_TRANSFER_TYPE_CONTROL', - 1: 'LIBUSB_TRANSFER_TYPE_ISOCHRONOUS', - 2: 'LIBUSB_TRANSFER_TYPE_BULK', - 3: 'LIBUSB_TRANSFER_TYPE_INTERRUPT', - 4: 'LIBUSB_TRANSFER_TYPE_BULK_STREAM', -} -LIBUSB_TRANSFER_TYPE_CONTROL = 0 -LIBUSB_TRANSFER_TYPE_ISOCHRONOUS = 1 -LIBUSB_TRANSFER_TYPE_BULK = 2 -LIBUSB_TRANSFER_TYPE_INTERRUPT = 3 -LIBUSB_TRANSFER_TYPE_BULK_STREAM = 4 -libusb_transfer_type = ctypes.c_uint32 # enum +enum_libusb_transfer_status = CEnum(ctypes.c_uint32) +LIBUSB_TRANSFER_COMPLETED = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_COMPLETED', 0) +LIBUSB_TRANSFER_ERROR = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_ERROR', 1) +LIBUSB_TRANSFER_TIMED_OUT = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_TIMED_OUT', 2) +LIBUSB_TRANSFER_CANCELLED = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_CANCELLED', 3) +LIBUSB_TRANSFER_STALL = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_STALL', 4) +LIBUSB_TRANSFER_NO_DEVICE = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_NO_DEVICE', 5) +LIBUSB_TRANSFER_OVERFLOW = enum_libusb_transfer_status.define('LIBUSB_TRANSFER_OVERFLOW', 6) -# values for enumeration 'libusb_transfer_status' -libusb_transfer_status__enumvalues = { - 0: 'LIBUSB_TRANSFER_COMPLETED', - 1: 'LIBUSB_TRANSFER_ERROR', - 2: 'LIBUSB_TRANSFER_TIMED_OUT', - 3: 'LIBUSB_TRANSFER_CANCELLED', - 4: 'LIBUSB_TRANSFER_STALL', - 5: 'LIBUSB_TRANSFER_NO_DEVICE', - 6: 'LIBUSB_TRANSFER_OVERFLOW', -} -LIBUSB_TRANSFER_COMPLETED = 0 -LIBUSB_TRANSFER_ERROR = 1 -LIBUSB_TRANSFER_TIMED_OUT = 2 -LIBUSB_TRANSFER_CANCELLED = 3 -LIBUSB_TRANSFER_STALL = 4 -LIBUSB_TRANSFER_NO_DEVICE = 5 -LIBUSB_TRANSFER_OVERFLOW = 6 -libusb_transfer_status = ctypes.c_uint32 # enum +enum_libusb_transfer_flags = CEnum(ctypes.c_uint32) +LIBUSB_TRANSFER_SHORT_NOT_OK = enum_libusb_transfer_flags.define('LIBUSB_TRANSFER_SHORT_NOT_OK', 1) +LIBUSB_TRANSFER_FREE_BUFFER = enum_libusb_transfer_flags.define('LIBUSB_TRANSFER_FREE_BUFFER', 2) +LIBUSB_TRANSFER_FREE_TRANSFER = enum_libusb_transfer_flags.define('LIBUSB_TRANSFER_FREE_TRANSFER', 4) +LIBUSB_TRANSFER_ADD_ZERO_PACKET = enum_libusb_transfer_flags.define('LIBUSB_TRANSFER_ADD_ZERO_PACKET', 8) -# values for enumeration 'libusb_transfer_flags' -libusb_transfer_flags__enumvalues = { - 1: 'LIBUSB_TRANSFER_SHORT_NOT_OK', - 2: 'LIBUSB_TRANSFER_FREE_BUFFER', - 4: 'LIBUSB_TRANSFER_FREE_TRANSFER', - 8: 'LIBUSB_TRANSFER_ADD_ZERO_PACKET', -} -LIBUSB_TRANSFER_SHORT_NOT_OK = 1 -LIBUSB_TRANSFER_FREE_BUFFER = 2 -LIBUSB_TRANSFER_FREE_TRANSFER = 4 -LIBUSB_TRANSFER_ADD_ZERO_PACKET = 8 -libusb_transfer_flags = ctypes.c_uint32 # enum -class struct_libusb_iso_packet_descriptor(Structure): - pass - -struct_libusb_iso_packet_descriptor._pack_ = 1 # source:False +class struct_libusb_iso_packet_descriptor(Struct): pass struct_libusb_iso_packet_descriptor._fields_ = [ - ('length', ctypes.c_uint32), - ('actual_length', ctypes.c_uint32), - ('status', libusb_transfer_status), + ('length', ctypes.c_uint32), + ('actual_length', ctypes.c_uint32), + ('status', enum_libusb_transfer_status), ] - -class struct_libusb_transfer(Structure): - pass - +class struct_libusb_transfer(Struct): pass libusb_transfer_cb_fn = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_transfer)) - -# values for enumeration 'libusb_capability' -libusb_capability__enumvalues = { - 0: 'LIBUSB_CAP_HAS_CAPABILITY', - 1: 'LIBUSB_CAP_HAS_HOTPLUG', - 256: 'LIBUSB_CAP_HAS_HID_ACCESS', - 257: 'LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER', -} -LIBUSB_CAP_HAS_CAPABILITY = 0 -LIBUSB_CAP_HAS_HOTPLUG = 1 -LIBUSB_CAP_HAS_HID_ACCESS = 256 -LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER = 257 -libusb_capability = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_log_level' -libusb_log_level__enumvalues = { - 0: 'LIBUSB_LOG_LEVEL_NONE', - 1: 'LIBUSB_LOG_LEVEL_ERROR', - 2: 'LIBUSB_LOG_LEVEL_WARNING', - 3: 'LIBUSB_LOG_LEVEL_INFO', - 4: 'LIBUSB_LOG_LEVEL_DEBUG', -} -LIBUSB_LOG_LEVEL_NONE = 0 -LIBUSB_LOG_LEVEL_ERROR = 1 -LIBUSB_LOG_LEVEL_WARNING = 2 -LIBUSB_LOG_LEVEL_INFO = 3 -LIBUSB_LOG_LEVEL_DEBUG = 4 -libusb_log_level = ctypes.c_uint32 # enum - -# values for enumeration 'libusb_log_cb_mode' -libusb_log_cb_mode__enumvalues = { - 1: 'LIBUSB_LOG_CB_GLOBAL', - 2: 'LIBUSB_LOG_CB_CONTEXT', -} -LIBUSB_LOG_CB_GLOBAL = 1 -LIBUSB_LOG_CB_CONTEXT = 2 -libusb_log_cb_mode = ctypes.c_uint32 # enum -libusb_log_cb = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_context), libusb_log_level, ctypes.POINTER(ctypes.c_char)) -try: - libusb_init = _libraries['libusb'].libusb_init - libusb_init.restype = ctypes.c_int32 - libusb_init.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_libusb_context))] -except AttributeError: - pass -try: - libusb_exit = _libraries['libusb'].libusb_exit - libusb_exit.restype = None - libusb_exit.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_set_debug = _libraries['libusb'].libusb_set_debug - libusb_set_debug.restype = None - libusb_set_debug.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_set_log_cb = _libraries['libusb'].libusb_set_log_cb - libusb_set_log_cb.restype = None - libusb_set_log_cb.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_log_cb, ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_version = _libraries['libusb'].libusb_get_version - libusb_get_version.restype = ctypes.POINTER(struct_libusb_version) - libusb_get_version.argtypes = [] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - libusb_has_capability = _libraries['libusb'].libusb_has_capability - libusb_has_capability.restype = ctypes.c_int32 - libusb_has_capability.argtypes = [uint32_t] -except AttributeError: - pass -try: - libusb_error_name = _libraries['libusb'].libusb_error_name - libusb_error_name.restype = ctypes.POINTER(ctypes.c_char) - libusb_error_name.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - libusb_setlocale = _libraries['libusb'].libusb_setlocale - libusb_setlocale.restype = ctypes.c_int32 - libusb_setlocale.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - libusb_strerror = _libraries['libusb'].libusb_strerror - libusb_strerror.restype = ctypes.POINTER(ctypes.c_char) - libusb_strerror.argtypes = [ctypes.c_int32] -except AttributeError: - pass -ssize_t = ctypes.c_int64 -try: - libusb_get_device_list = _libraries['libusb'].libusb_get_device_list - libusb_get_device_list.restype = ssize_t - libusb_get_device_list.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_libusb_device)))] -except AttributeError: - pass -try: - libusb_free_device_list = _libraries['libusb'].libusb_free_device_list - libusb_free_device_list.restype = None - libusb_free_device_list.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_libusb_device)), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_ref_device = _libraries['libusb'].libusb_ref_device - libusb_ref_device.restype = ctypes.POINTER(struct_libusb_device) - libusb_ref_device.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_unref_device = _libraries['libusb'].libusb_unref_device - libusb_unref_device.restype = None - libusb_unref_device.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_configuration = _libraries['libusb'].libusb_get_configuration - libusb_get_configuration.restype = ctypes.c_int32 - libusb_get_configuration.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_get_device_descriptor = _libraries['libusb'].libusb_get_device_descriptor - libusb_get_device_descriptor.restype = ctypes.c_int32 - libusb_get_device_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(struct_libusb_device_descriptor)] -except AttributeError: - pass -try: - libusb_get_active_config_descriptor = _libraries['libusb'].libusb_get_active_config_descriptor - libusb_get_active_config_descriptor.restype = ctypes.c_int32 - libusb_get_active_config_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] -except AttributeError: - pass -uint8_t = ctypes.c_uint8 -try: - libusb_get_config_descriptor = _libraries['libusb'].libusb_get_config_descriptor - libusb_get_config_descriptor.restype = ctypes.c_int32 - libusb_get_config_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] -except AttributeError: - pass -try: - libusb_get_config_descriptor_by_value = _libraries['libusb'].libusb_get_config_descriptor_by_value - libusb_get_config_descriptor_by_value.restype = ctypes.c_int32 - libusb_get_config_descriptor_by_value.argtypes = [ctypes.POINTER(struct_libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] -except AttributeError: - pass -try: - libusb_free_config_descriptor = _libraries['libusb'].libusb_free_config_descriptor - libusb_free_config_descriptor.restype = None - libusb_free_config_descriptor.argtypes = [ctypes.POINTER(struct_libusb_config_descriptor)] -except AttributeError: - pass -try: - libusb_get_ss_endpoint_companion_descriptor = _libraries['libusb'].libusb_get_ss_endpoint_companion_descriptor - libusb_get_ss_endpoint_companion_descriptor.restype = ctypes.c_int32 - libusb_get_ss_endpoint_companion_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_endpoint_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_ss_endpoint_companion_descriptor))] -except AttributeError: - pass -try: - libusb_free_ss_endpoint_companion_descriptor = _libraries['libusb'].libusb_free_ss_endpoint_companion_descriptor - libusb_free_ss_endpoint_companion_descriptor.restype = None - libusb_free_ss_endpoint_companion_descriptor.argtypes = [ctypes.POINTER(struct_libusb_ss_endpoint_companion_descriptor)] -except AttributeError: - pass -try: - libusb_get_bos_descriptor = _libraries['libusb'].libusb_get_bos_descriptor - libusb_get_bos_descriptor.restype = ctypes.c_int32 - libusb_get_bos_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.POINTER(struct_libusb_bos_descriptor))] -except AttributeError: - pass -try: - libusb_free_bos_descriptor = _libraries['libusb'].libusb_free_bos_descriptor - libusb_free_bos_descriptor.restype = None - libusb_free_bos_descriptor.argtypes = [ctypes.POINTER(struct_libusb_bos_descriptor)] -except AttributeError: - pass -try: - libusb_get_usb_2_0_extension_descriptor = _libraries['libusb'].libusb_get_usb_2_0_extension_descriptor - libusb_get_usb_2_0_extension_descriptor.restype = ctypes.c_int32 - libusb_get_usb_2_0_extension_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_usb_2_0_extension_descriptor))] -except AttributeError: - pass -try: - libusb_free_usb_2_0_extension_descriptor = _libraries['libusb'].libusb_free_usb_2_0_extension_descriptor - libusb_free_usb_2_0_extension_descriptor.restype = None - libusb_free_usb_2_0_extension_descriptor.argtypes = [ctypes.POINTER(struct_libusb_usb_2_0_extension_descriptor)] -except AttributeError: - pass -try: - libusb_get_ss_usb_device_capability_descriptor = _libraries['libusb'].libusb_get_ss_usb_device_capability_descriptor - libusb_get_ss_usb_device_capability_descriptor.restype = ctypes.c_int32 - libusb_get_ss_usb_device_capability_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_ss_usb_device_capability_descriptor))] -except AttributeError: - pass -try: - libusb_free_ss_usb_device_capability_descriptor = _libraries['libusb'].libusb_free_ss_usb_device_capability_descriptor - libusb_free_ss_usb_device_capability_descriptor.restype = None - libusb_free_ss_usb_device_capability_descriptor.argtypes = [ctypes.POINTER(struct_libusb_ss_usb_device_capability_descriptor)] -except AttributeError: - pass -try: - libusb_get_container_id_descriptor = _libraries['libusb'].libusb_get_container_id_descriptor - libusb_get_container_id_descriptor.restype = ctypes.c_int32 - libusb_get_container_id_descriptor.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_container_id_descriptor))] -except AttributeError: - pass -try: - libusb_free_container_id_descriptor = _libraries['libusb'].libusb_free_container_id_descriptor - libusb_free_container_id_descriptor.restype = None - libusb_free_container_id_descriptor.argtypes = [ctypes.POINTER(struct_libusb_container_id_descriptor)] -except AttributeError: - pass -try: - libusb_get_bus_number = _libraries['libusb'].libusb_get_bus_number - libusb_get_bus_number.restype = uint8_t - libusb_get_bus_number.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_port_number = _libraries['libusb'].libusb_get_port_number - libusb_get_port_number.restype = uint8_t - libusb_get_port_number.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_port_numbers = _libraries['libusb'].libusb_get_port_numbers - libusb_get_port_numbers.restype = ctypes.c_int32 - libusb_get_port_numbers.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_port_path = _libraries['libusb'].libusb_get_port_path - libusb_get_port_path.restype = ctypes.c_int32 - libusb_get_port_path.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.c_ubyte), uint8_t] -except AttributeError: - pass -try: - libusb_get_parent = _libraries['libusb'].libusb_get_parent - libusb_get_parent.restype = ctypes.POINTER(struct_libusb_device) - libusb_get_parent.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_device_address = _libraries['libusb'].libusb_get_device_address - libusb_get_device_address.restype = uint8_t - libusb_get_device_address.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_device_speed = _libraries['libusb'].libusb_get_device_speed - libusb_get_device_speed.restype = ctypes.c_int32 - libusb_get_device_speed.argtypes = [ctypes.POINTER(struct_libusb_device)] -except AttributeError: - pass -try: - libusb_get_max_packet_size = _libraries['libusb'].libusb_get_max_packet_size - libusb_get_max_packet_size.restype = ctypes.c_int32 - libusb_get_max_packet_size.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.c_ubyte] -except AttributeError: - pass -try: - libusb_get_max_iso_packet_size = _libraries['libusb'].libusb_get_max_iso_packet_size - libusb_get_max_iso_packet_size.restype = ctypes.c_int32 - libusb_get_max_iso_packet_size.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.c_ubyte] -except AttributeError: - pass -intptr_t = ctypes.c_int64 -try: - libusb_wrap_sys_device = _libraries['libusb'].libusb_wrap_sys_device - libusb_wrap_sys_device.restype = ctypes.c_int32 - libusb_wrap_sys_device.argtypes = [ctypes.POINTER(struct_libusb_context), intptr_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_device_handle))] -except AttributeError: - pass -try: - libusb_open = _libraries['libusb'].libusb_open - libusb_open.restype = ctypes.c_int32 - libusb_open.argtypes = [ctypes.POINTER(struct_libusb_device), ctypes.POINTER(ctypes.POINTER(struct_libusb_device_handle))] -except AttributeError: - pass -try: - libusb_close = _libraries['libusb'].libusb_close - libusb_close.restype = None - libusb_close.argtypes = [ctypes.POINTER(struct_libusb_device_handle)] -except AttributeError: - pass -try: - libusb_get_device = _libraries['libusb'].libusb_get_device - libusb_get_device.restype = ctypes.POINTER(struct_libusb_device) - libusb_get_device.argtypes = [ctypes.POINTER(struct_libusb_device_handle)] -except AttributeError: - pass -try: - libusb_set_configuration = _libraries['libusb'].libusb_set_configuration - libusb_set_configuration.restype = ctypes.c_int32 - libusb_set_configuration.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_claim_interface = _libraries['libusb'].libusb_claim_interface - libusb_claim_interface.restype = ctypes.c_int32 - libusb_claim_interface.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_release_interface = _libraries['libusb'].libusb_release_interface - libusb_release_interface.restype = ctypes.c_int32 - libusb_release_interface.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_open_device_with_vid_pid = _libraries['libusb'].libusb_open_device_with_vid_pid - libusb_open_device_with_vid_pid.restype = ctypes.POINTER(struct_libusb_device_handle) - libusb_open_device_with_vid_pid.argtypes = [ctypes.POINTER(struct_libusb_context), uint16_t, uint16_t] -except AttributeError: - pass -try: - libusb_set_interface_alt_setting = _libraries['libusb'].libusb_set_interface_alt_setting - libusb_set_interface_alt_setting.restype = ctypes.c_int32 - libusb_set_interface_alt_setting.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - libusb_clear_halt = _libraries['libusb'].libusb_clear_halt - libusb_clear_halt.restype = ctypes.c_int32 - libusb_clear_halt.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte] -except AttributeError: - pass -try: - libusb_reset_device = _libraries['libusb'].libusb_reset_device - libusb_reset_device.restype = ctypes.c_int32 - libusb_reset_device.argtypes = [ctypes.POINTER(struct_libusb_device_handle)] -except AttributeError: - pass -try: - libusb_alloc_streams = _libraries['libusb'].libusb_alloc_streams - libusb_alloc_streams.restype = ctypes.c_int32 - libusb_alloc_streams.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint32_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_free_streams = _libraries['libusb'].libusb_free_streams - libusb_free_streams.restype = ctypes.c_int32 - libusb_free_streams.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - libusb_dev_mem_alloc = _libraries['libusb'].libusb_dev_mem_alloc - libusb_dev_mem_alloc.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_dev_mem_alloc.argtypes = [ctypes.POINTER(struct_libusb_device_handle), size_t] -except AttributeError: - pass -try: - libusb_dev_mem_free = _libraries['libusb'].libusb_dev_mem_free - libusb_dev_mem_free.restype = ctypes.c_int32 - libusb_dev_mem_free.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), size_t] -except AttributeError: - pass -try: - libusb_kernel_driver_active = _libraries['libusb'].libusb_kernel_driver_active - libusb_kernel_driver_active.restype = ctypes.c_int32 - libusb_kernel_driver_active.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_detach_kernel_driver = _libraries['libusb'].libusb_detach_kernel_driver - libusb_detach_kernel_driver.restype = ctypes.c_int32 - libusb_detach_kernel_driver.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_attach_kernel_driver = _libraries['libusb'].libusb_attach_kernel_driver - libusb_attach_kernel_driver.restype = ctypes.c_int32 - libusb_attach_kernel_driver.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_set_auto_detach_kernel_driver = _libraries['libusb'].libusb_set_auto_detach_kernel_driver - libusb_set_auto_detach_kernel_driver.restype = ctypes.c_int32 - libusb_set_auto_detach_kernel_driver.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_control_transfer_get_data = _libraries['libusb'].libusb_control_transfer_get_data - libusb_control_transfer_get_data.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_control_transfer_get_data.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_control_transfer_get_setup = _libraries['libusb'].libusb_control_transfer_get_setup - libusb_control_transfer_get_setup.restype = ctypes.POINTER(struct_libusb_control_setup) - libusb_control_transfer_get_setup.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_fill_control_setup = _libraries['libusb'].libusb_fill_control_setup - libusb_fill_control_setup.restype = None - libusb_fill_control_setup.argtypes = [ctypes.POINTER(ctypes.c_ubyte), uint8_t, uint8_t, uint16_t, uint16_t, uint16_t] -except AttributeError: - pass -try: - libusb_alloc_transfer = _libraries['libusb'].libusb_alloc_transfer - libusb_alloc_transfer.restype = ctypes.POINTER(struct_libusb_transfer) - libusb_alloc_transfer.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - libusb_submit_transfer = _libraries['libusb'].libusb_submit_transfer - libusb_submit_transfer.restype = ctypes.c_int32 - libusb_submit_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_cancel_transfer = _libraries['libusb'].libusb_cancel_transfer - libusb_cancel_transfer.restype = ctypes.c_int32 - libusb_cancel_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_free_transfer = _libraries['libusb'].libusb_free_transfer - libusb_free_transfer.restype = None - libusb_free_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_transfer_set_stream_id = _libraries['libusb'].libusb_transfer_set_stream_id - libusb_transfer_set_stream_id.restype = None - libusb_transfer_set_stream_id.argtypes = [ctypes.POINTER(struct_libusb_transfer), uint32_t] -except AttributeError: - pass -try: - libusb_transfer_get_stream_id = _libraries['libusb'].libusb_transfer_get_stream_id - libusb_transfer_get_stream_id.restype = uint32_t - libusb_transfer_get_stream_id.argtypes = [ctypes.POINTER(struct_libusb_transfer)] -except AttributeError: - pass -try: - libusb_fill_control_transfer = _libraries['libusb'].libusb_fill_control_transfer - libusb_fill_control_transfer.restype = None - libusb_fill_control_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_bulk_transfer = _libraries['libusb'].libusb_fill_bulk_transfer - libusb_fill_bulk_transfer.restype = None - libusb_fill_bulk_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_bulk_stream_transfer = _libraries['libusb'].libusb_fill_bulk_stream_transfer - libusb_fill_bulk_stream_transfer.restype = None - libusb_fill_bulk_stream_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, uint32_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_interrupt_transfer = _libraries['libusb'].libusb_fill_interrupt_transfer - libusb_fill_interrupt_transfer.restype = None - libusb_fill_interrupt_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_fill_iso_transfer = _libraries['libusb'].libusb_fill_iso_transfer - libusb_fill_iso_transfer.restype = None - libusb_fill_iso_transfer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.c_int32, libusb_transfer_cb_fn, ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_set_iso_packet_lengths = _libraries['libusb'].libusb_set_iso_packet_lengths - libusb_set_iso_packet_lengths.restype = None - libusb_set_iso_packet_lengths.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_get_iso_packet_buffer = _libraries['libusb'].libusb_get_iso_packet_buffer - libusb_get_iso_packet_buffer.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_get_iso_packet_buffer.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_get_iso_packet_buffer_simple = _libraries['libusb'].libusb_get_iso_packet_buffer_simple - libusb_get_iso_packet_buffer_simple.restype = ctypes.POINTER(ctypes.c_ubyte) - libusb_get_iso_packet_buffer_simple.argtypes = [ctypes.POINTER(struct_libusb_transfer), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_control_transfer = _libraries['libusb'].libusb_control_transfer - libusb_control_transfer.restype = ctypes.c_int32 - libusb_control_transfer.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, uint8_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_ubyte), uint16_t, ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_bulk_transfer = _libraries['libusb'].libusb_bulk_transfer - libusb_bulk_transfer.restype = ctypes.c_int32 - libusb_bulk_transfer.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_interrupt_transfer = _libraries['libusb'].libusb_interrupt_transfer - libusb_interrupt_transfer.restype = ctypes.c_int32 - libusb_interrupt_transfer.argtypes = [ctypes.POINTER(struct_libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass -try: - libusb_get_descriptor = _libraries['libusb'].libusb_get_descriptor - libusb_get_descriptor.restype = ctypes.c_int32 - libusb_get_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, uint8_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_string_descriptor = _libraries['libusb'].libusb_get_string_descriptor - libusb_get_string_descriptor.restype = ctypes.c_int32 - libusb_get_string_descriptor.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, uint16_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_get_string_descriptor_ascii = _libraries['libusb'].libusb_get_string_descriptor_ascii - libusb_get_string_descriptor_ascii.restype = ctypes.c_int32 - libusb_get_string_descriptor_ascii.argtypes = [ctypes.POINTER(struct_libusb_device_handle), uint8_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - libusb_try_lock_events = _libraries['libusb'].libusb_try_lock_events - libusb_try_lock_events.restype = ctypes.c_int32 - libusb_try_lock_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_lock_events = _libraries['libusb'].libusb_lock_events - libusb_lock_events.restype = None - libusb_lock_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_unlock_events = _libraries['libusb'].libusb_unlock_events - libusb_unlock_events.restype = None - libusb_unlock_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_event_handling_ok = _libraries['libusb'].libusb_event_handling_ok - libusb_event_handling_ok.restype = ctypes.c_int32 - libusb_event_handling_ok.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_event_handler_active = _libraries['libusb'].libusb_event_handler_active - libusb_event_handler_active.restype = ctypes.c_int32 - libusb_event_handler_active.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_interrupt_event_handler = _libraries['libusb'].libusb_interrupt_event_handler - libusb_interrupt_event_handler.restype = None - libusb_interrupt_event_handler.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_lock_event_waiters = _libraries['libusb'].libusb_lock_event_waiters - libusb_lock_event_waiters.restype = None - libusb_lock_event_waiters.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_unlock_event_waiters = _libraries['libusb'].libusb_unlock_event_waiters - libusb_unlock_event_waiters.restype = None - libusb_unlock_event_waiters.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -class struct_timeval(Structure): - pass - -struct_timeval._pack_ = 1 # source:False -struct_timeval._fields_ = [ - ('tv_sec', ctypes.c_int64), - ('tv_usec', ctypes.c_int64), -] - -try: - libusb_wait_for_event = _libraries['libusb'].libusb_wait_for_event - libusb_wait_for_event.restype = ctypes.c_int32 - libusb_wait_for_event.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -try: - libusb_handle_events_timeout = _libraries['libusb'].libusb_handle_events_timeout - libusb_handle_events_timeout.restype = ctypes.c_int32 - libusb_handle_events_timeout.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -try: - libusb_handle_events_timeout_completed = _libraries['libusb'].libusb_handle_events_timeout_completed - libusb_handle_events_timeout_completed.restype = ctypes.c_int32 - libusb_handle_events_timeout_completed.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_handle_events = _libraries['libusb'].libusb_handle_events - libusb_handle_events.restype = ctypes.c_int32 - libusb_handle_events.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_handle_events_completed = _libraries['libusb'].libusb_handle_events_completed - libusb_handle_events_completed.restype = ctypes.c_int32 - libusb_handle_events_completed.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_handle_events_locked = _libraries['libusb'].libusb_handle_events_locked - libusb_handle_events_locked.restype = ctypes.c_int32 - libusb_handle_events_locked.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -try: - libusb_pollfds_handle_timeouts = _libraries['libusb'].libusb_pollfds_handle_timeouts - libusb_pollfds_handle_timeouts.restype = ctypes.c_int32 - libusb_pollfds_handle_timeouts.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_get_next_timeout = _libraries['libusb'].libusb_get_next_timeout - libusb_get_next_timeout.restype = ctypes.c_int32 - libusb_get_next_timeout.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_timeval)] -except AttributeError: - pass -class struct_libusb_pollfd(Structure): - pass - -struct_libusb_pollfd._pack_ = 1 # source:False -struct_libusb_pollfd._fields_ = [ - ('fd', ctypes.c_int32), - ('events', ctypes.c_int16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -libusb_pollfd_added_cb = ctypes.CFUNCTYPE(None, ctypes.c_int32, ctypes.c_int16, ctypes.POINTER(None)) -libusb_pollfd_removed_cb = ctypes.CFUNCTYPE(None, ctypes.c_int32, ctypes.POINTER(None)) -try: - libusb_get_pollfds = _libraries['libusb'].libusb_get_pollfds - libusb_get_pollfds.restype = ctypes.POINTER(ctypes.POINTER(struct_libusb_pollfd)) - libusb_get_pollfds.argtypes = [ctypes.POINTER(struct_libusb_context)] -except AttributeError: - pass -try: - libusb_free_pollfds = _libraries['libusb'].libusb_free_pollfds - libusb_free_pollfds.restype = None - libusb_free_pollfds.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_libusb_pollfd))] -except AttributeError: - pass -try: - libusb_set_pollfd_notifiers = _libraries['libusb'].libusb_set_pollfd_notifiers - libusb_set_pollfd_notifiers.restype = None - libusb_set_pollfd_notifiers.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_pollfd_added_cb, libusb_pollfd_removed_cb, ctypes.POINTER(None)] -except AttributeError: - pass -libusb_hotplug_callback_handle = ctypes.c_int32 - -# values for enumeration 'c__EA_libusb_hotplug_event' -c__EA_libusb_hotplug_event__enumvalues = { - 1: 'LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED', - 2: 'LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT', -} -LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED = 1 -LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT = 2 -c__EA_libusb_hotplug_event = ctypes.c_uint32 # enum -libusb_hotplug_event = c__EA_libusb_hotplug_event -libusb_hotplug_event__enumvalues = c__EA_libusb_hotplug_event__enumvalues - -# values for enumeration 'c__EA_libusb_hotplug_flag' -c__EA_libusb_hotplug_flag__enumvalues = { - 1: 'LIBUSB_HOTPLUG_ENUMERATE', -} -LIBUSB_HOTPLUG_ENUMERATE = 1 -c__EA_libusb_hotplug_flag = ctypes.c_uint32 # enum -libusb_hotplug_flag = c__EA_libusb_hotplug_flag -libusb_hotplug_flag__enumvalues = c__EA_libusb_hotplug_flag__enumvalues -libusb_hotplug_callback_fn = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_device), c__EA_libusb_hotplug_event, ctypes.POINTER(None)) -try: - libusb_hotplug_register_callback = _libraries['libusb'].libusb_hotplug_register_callback - libusb_hotplug_register_callback.restype = ctypes.c_int32 - libusb_hotplug_register_callback.argtypes = [ctypes.POINTER(struct_libusb_context), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, libusb_hotplug_callback_fn, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - libusb_hotplug_deregister_callback = _libraries['libusb'].libusb_hotplug_deregister_callback - libusb_hotplug_deregister_callback.restype = None - libusb_hotplug_deregister_callback.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_hotplug_callback_handle] -except AttributeError: - pass -try: - libusb_hotplug_get_user_data = _libraries['libusb'].libusb_hotplug_get_user_data - libusb_hotplug_get_user_data.restype = ctypes.POINTER(None) - libusb_hotplug_get_user_data.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_hotplug_callback_handle] -except AttributeError: - pass - -# values for enumeration 'libusb_option' -libusb_option__enumvalues = { - 0: 'LIBUSB_OPTION_LOG_LEVEL', - 1: 'LIBUSB_OPTION_USE_USBDK', - 2: 'LIBUSB_OPTION_NO_DEVICE_DISCOVERY', - 3: 'LIBUSB_OPTION_MAX', -} -LIBUSB_OPTION_LOG_LEVEL = 0 -LIBUSB_OPTION_USE_USBDK = 1 -LIBUSB_OPTION_NO_DEVICE_DISCOVERY = 2 -LIBUSB_OPTION_MAX = 3 -libusb_option = ctypes.c_uint32 # enum -LIBUSB_OPTION_WEAK_AUTHORITY = LIBUSB_OPTION_NO_DEVICE_DISCOVERY # macro -try: - libusb_set_option = _libraries['libusb'].libusb_set_option - libusb_set_option.restype = ctypes.c_int32 - libusb_set_option.argtypes = [ctypes.POINTER(struct_libusb_context), libusb_option] -except AttributeError: - pass -struct_libusb_transfer._pack_ = 1 # source:False struct_libusb_transfer._fields_ = [ - ('dev_handle', ctypes.POINTER(struct_libusb_device_handle)), - ('flags', ctypes.c_ubyte), - ('endpoint', ctypes.c_ubyte), - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('timeout', ctypes.c_uint32), - ('status', libusb_transfer_status), - ('length', ctypes.c_int32), - ('actual_length', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_transfer))), - ('user_data', ctypes.POINTER(None)), - ('buffer', ctypes.POINTER(ctypes.c_ubyte)), - ('num_iso_packets', ctypes.c_int32), - ('iso_packet_desc', struct_libusb_iso_packet_descriptor * 0), - ('PADDING_2', ctypes.c_ubyte * 4), + ('dev_handle', ctypes.POINTER(libusb_device_handle)), + ('flags', uint8_t), + ('endpoint', ctypes.c_ubyte), + ('type', ctypes.c_ubyte), + ('timeout', ctypes.c_uint32), + ('status', enum_libusb_transfer_status), + ('length', ctypes.c_int32), + ('actual_length', ctypes.c_int32), + ('callback', libusb_transfer_cb_fn), + ('user_data', ctypes.c_void_p), + ('buffer', ctypes.POINTER(ctypes.c_ubyte)), + ('num_iso_packets', ctypes.c_int32), + ('iso_packet_desc', (struct_libusb_iso_packet_descriptor * 0)), ] +enum_libusb_capability = CEnum(ctypes.c_uint32) +LIBUSB_CAP_HAS_CAPABILITY = enum_libusb_capability.define('LIBUSB_CAP_HAS_CAPABILITY', 0) +LIBUSB_CAP_HAS_HOTPLUG = enum_libusb_capability.define('LIBUSB_CAP_HAS_HOTPLUG', 1) +LIBUSB_CAP_HAS_HID_ACCESS = enum_libusb_capability.define('LIBUSB_CAP_HAS_HID_ACCESS', 256) +LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER = enum_libusb_capability.define('LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER', 257) -__all__ = \ - ['LIBUSBX_API_VERSION', 'LIBUSB_API_VERSION', - 'LIBUSB_BM_LPM_SUPPORT', 'LIBUSB_BM_LTM_SUPPORT', - 'LIBUSB_BT_CONTAINER_ID', 'LIBUSB_BT_CONTAINER_ID_SIZE', - 'LIBUSB_BT_SS_USB_DEVICE_CAPABILITY', - 'LIBUSB_BT_SS_USB_DEVICE_CAPABILITY_SIZE', - 'LIBUSB_BT_USB_2_0_EXTENSION', 'LIBUSB_BT_USB_2_0_EXTENSION_SIZE', - 'LIBUSB_BT_WIRELESS_USB_DEVICE_CAPABILITY', 'LIBUSB_CALL', - 'LIBUSB_CAP_HAS_CAPABILITY', 'LIBUSB_CAP_HAS_HID_ACCESS', - 'LIBUSB_CAP_HAS_HOTPLUG', - 'LIBUSB_CAP_SUPPORTS_DETACH_KERNEL_DRIVER', - 'LIBUSB_CLASS_APPLICATION', 'LIBUSB_CLASS_AUDIO', - 'LIBUSB_CLASS_COMM', 'LIBUSB_CLASS_CONTENT_SECURITY', - 'LIBUSB_CLASS_DATA', 'LIBUSB_CLASS_DIAGNOSTIC_DEVICE', - 'LIBUSB_CLASS_HID', 'LIBUSB_CLASS_HUB', 'LIBUSB_CLASS_IMAGE', - 'LIBUSB_CLASS_MASS_STORAGE', 'LIBUSB_CLASS_MISCELLANEOUS', - 'LIBUSB_CLASS_PERSONAL_HEALTHCARE', 'LIBUSB_CLASS_PER_INTERFACE', - 'LIBUSB_CLASS_PHYSICAL', 'LIBUSB_CLASS_PRINTER', - 'LIBUSB_CLASS_PTP', 'LIBUSB_CLASS_SMART_CARD', - 'LIBUSB_CLASS_VENDOR_SPEC', 'LIBUSB_CLASS_VIDEO', - 'LIBUSB_CLASS_WIRELESS', 'LIBUSB_DT_BOS', - 'LIBUSB_DT_BOS_MAX_SIZE', 'LIBUSB_DT_BOS_SIZE', - 'LIBUSB_DT_CONFIG', 'LIBUSB_DT_CONFIG_SIZE', 'LIBUSB_DT_DEVICE', - 'LIBUSB_DT_DEVICE_CAPABILITY', 'LIBUSB_DT_DEVICE_CAPABILITY_SIZE', - 'LIBUSB_DT_DEVICE_SIZE', 'LIBUSB_DT_ENDPOINT', - 'LIBUSB_DT_ENDPOINT_AUDIO_SIZE', 'LIBUSB_DT_ENDPOINT_SIZE', - 'LIBUSB_DT_HID', 'LIBUSB_DT_HUB', 'LIBUSB_DT_HUB_NONVAR_SIZE', - 'LIBUSB_DT_INTERFACE', 'LIBUSB_DT_INTERFACE_SIZE', - 'LIBUSB_DT_PHYSICAL', 'LIBUSB_DT_REPORT', - 'LIBUSB_DT_SS_ENDPOINT_COMPANION', - 'LIBUSB_DT_SS_ENDPOINT_COMPANION_SIZE', 'LIBUSB_DT_STRING', - 'LIBUSB_DT_SUPERSPEED_HUB', 'LIBUSB_ENDPOINT_ADDRESS_MASK', - 'LIBUSB_ENDPOINT_DIR_MASK', 'LIBUSB_ENDPOINT_IN', - 'LIBUSB_ENDPOINT_OUT', 'LIBUSB_ENDPOINT_TRANSFER_TYPE_BULK', - 'LIBUSB_ENDPOINT_TRANSFER_TYPE_CONTROL', - 'LIBUSB_ENDPOINT_TRANSFER_TYPE_INTERRUPT', - 'LIBUSB_ENDPOINT_TRANSFER_TYPE_ISOCHRONOUS', - 'LIBUSB_ERROR_ACCESS', 'LIBUSB_ERROR_BUSY', 'LIBUSB_ERROR_COUNT', - 'LIBUSB_ERROR_INTERRUPTED', 'LIBUSB_ERROR_INVALID_PARAM', - 'LIBUSB_ERROR_IO', 'LIBUSB_ERROR_NOT_FOUND', - 'LIBUSB_ERROR_NOT_SUPPORTED', 'LIBUSB_ERROR_NO_DEVICE', - 'LIBUSB_ERROR_NO_MEM', 'LIBUSB_ERROR_OTHER', - 'LIBUSB_ERROR_OVERFLOW', 'LIBUSB_ERROR_PIPE', - 'LIBUSB_ERROR_TIMEOUT', 'LIBUSB_FULL_SPEED_OPERATION', 'LIBUSB_H', - 'LIBUSB_HIGH_SPEED_OPERATION', 'LIBUSB_HOTPLUG_ENUMERATE', - 'LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED', - 'LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT', 'LIBUSB_HOTPLUG_MATCH_ANY', - 'LIBUSB_HOTPLUG_NO_FLAGS', 'LIBUSB_ISO_SYNC_TYPE_ADAPTIVE', - 'LIBUSB_ISO_SYNC_TYPE_ASYNC', 'LIBUSB_ISO_SYNC_TYPE_MASK', - 'LIBUSB_ISO_SYNC_TYPE_NONE', 'LIBUSB_ISO_SYNC_TYPE_SYNC', - 'LIBUSB_ISO_USAGE_TYPE_DATA', 'LIBUSB_ISO_USAGE_TYPE_FEEDBACK', - 'LIBUSB_ISO_USAGE_TYPE_IMPLICIT', 'LIBUSB_ISO_USAGE_TYPE_MASK', - 'LIBUSB_LOG_CB_CONTEXT', 'LIBUSB_LOG_CB_GLOBAL', - 'LIBUSB_LOG_LEVEL_DEBUG', 'LIBUSB_LOG_LEVEL_ERROR', - 'LIBUSB_LOG_LEVEL_INFO', 'LIBUSB_LOG_LEVEL_NONE', - 'LIBUSB_LOG_LEVEL_WARNING', 'LIBUSB_LOW_SPEED_OPERATION', - 'LIBUSB_OPTION_LOG_LEVEL', 'LIBUSB_OPTION_MAX', - 'LIBUSB_OPTION_NO_DEVICE_DISCOVERY', 'LIBUSB_OPTION_USE_USBDK', - 'LIBUSB_OPTION_WEAK_AUTHORITY', 'LIBUSB_RECIPIENT_DEVICE', - 'LIBUSB_RECIPIENT_ENDPOINT', 'LIBUSB_RECIPIENT_INTERFACE', - 'LIBUSB_RECIPIENT_OTHER', 'LIBUSB_REQUEST_CLEAR_FEATURE', - 'LIBUSB_REQUEST_GET_CONFIGURATION', - 'LIBUSB_REQUEST_GET_DESCRIPTOR', 'LIBUSB_REQUEST_GET_INTERFACE', - 'LIBUSB_REQUEST_GET_STATUS', 'LIBUSB_REQUEST_SET_ADDRESS', - 'LIBUSB_REQUEST_SET_CONFIGURATION', - 'LIBUSB_REQUEST_SET_DESCRIPTOR', 'LIBUSB_REQUEST_SET_FEATURE', - 'LIBUSB_REQUEST_SET_INTERFACE', 'LIBUSB_REQUEST_SET_SEL', - 'LIBUSB_REQUEST_SYNCH_FRAME', 'LIBUSB_REQUEST_TYPE_CLASS', - 'LIBUSB_REQUEST_TYPE_RESERVED', 'LIBUSB_REQUEST_TYPE_STANDARD', - 'LIBUSB_REQUEST_TYPE_VENDOR', 'LIBUSB_SET_ISOCH_DELAY', - 'LIBUSB_SPEED_FULL', 'LIBUSB_SPEED_HIGH', 'LIBUSB_SPEED_LOW', - 'LIBUSB_SPEED_SUPER', 'LIBUSB_SPEED_SUPER_PLUS', - 'LIBUSB_SPEED_UNKNOWN', 'LIBUSB_SUCCESS', - 'LIBUSB_SUPER_SPEED_OPERATION', 'LIBUSB_TRANSFER_ADD_ZERO_PACKET', - 'LIBUSB_TRANSFER_CANCELLED', 'LIBUSB_TRANSFER_COMPLETED', - 'LIBUSB_TRANSFER_ERROR', 'LIBUSB_TRANSFER_FREE_BUFFER', - 'LIBUSB_TRANSFER_FREE_TRANSFER', 'LIBUSB_TRANSFER_NO_DEVICE', - 'LIBUSB_TRANSFER_OVERFLOW', 'LIBUSB_TRANSFER_SHORT_NOT_OK', - 'LIBUSB_TRANSFER_STALL', 'LIBUSB_TRANSFER_TIMED_OUT', - 'LIBUSB_TRANSFER_TYPE_BULK', 'LIBUSB_TRANSFER_TYPE_BULK_STREAM', - 'LIBUSB_TRANSFER_TYPE_CONTROL', 'LIBUSB_TRANSFER_TYPE_INTERRUPT', - 'LIBUSB_TRANSFER_TYPE_ISOCHRONOUS', 'LIBUSB_TRANSFER_TYPE_MASK', - 'ZERO_SIZED_ARRAY', 'c__EA_libusb_hotplug_event', - 'c__EA_libusb_hotplug_flag', 'intptr_t', 'libusb_alloc_streams', - 'libusb_alloc_transfer', 'libusb_attach_kernel_driver', - 'libusb_bos_type', 'libusb_bulk_transfer', - 'libusb_cancel_transfer', 'libusb_capability', - 'libusb_claim_interface', 'libusb_class_code', - 'libusb_clear_halt', 'libusb_close', 'libusb_context', - 'libusb_control_transfer', 'libusb_control_transfer_get_data', - 'libusb_control_transfer_get_setup', 'libusb_cpu_to_le16', - 'libusb_descriptor_type', 'libusb_detach_kernel_driver', - 'libusb_dev_mem_alloc', 'libusb_dev_mem_free', 'libusb_device', - 'libusb_device_handle', 'libusb_endpoint_direction', - 'libusb_endpoint_transfer_type', 'libusb_error', - 'libusb_error_name', 'libusb_event_handler_active', - 'libusb_event_handling_ok', 'libusb_exit', - 'libusb_fill_bulk_stream_transfer', 'libusb_fill_bulk_transfer', - 'libusb_fill_control_setup', 'libusb_fill_control_transfer', - 'libusb_fill_interrupt_transfer', 'libusb_fill_iso_transfer', - 'libusb_free_bos_descriptor', 'libusb_free_config_descriptor', - 'libusb_free_container_id_descriptor', 'libusb_free_device_list', - 'libusb_free_pollfds', - 'libusb_free_ss_endpoint_companion_descriptor', - 'libusb_free_ss_usb_device_capability_descriptor', - 'libusb_free_streams', 'libusb_free_transfer', - 'libusb_free_usb_2_0_extension_descriptor', - 'libusb_get_active_config_descriptor', - 'libusb_get_bos_descriptor', 'libusb_get_bus_number', - 'libusb_get_config_descriptor', - 'libusb_get_config_descriptor_by_value', - 'libusb_get_configuration', 'libusb_get_container_id_descriptor', - 'libusb_get_descriptor', 'libusb_get_device', - 'libusb_get_device_address', 'libusb_get_device_descriptor', - 'libusb_get_device_list', 'libusb_get_device_speed', - 'libusb_get_iso_packet_buffer', - 'libusb_get_iso_packet_buffer_simple', - 'libusb_get_max_iso_packet_size', 'libusb_get_max_packet_size', - 'libusb_get_next_timeout', 'libusb_get_parent', - 'libusb_get_pollfds', 'libusb_get_port_number', - 'libusb_get_port_numbers', 'libusb_get_port_path', - 'libusb_get_ss_endpoint_companion_descriptor', - 'libusb_get_ss_usb_device_capability_descriptor', - 'libusb_get_string_descriptor', - 'libusb_get_string_descriptor_ascii', - 'libusb_get_usb_2_0_extension_descriptor', 'libusb_get_version', - 'libusb_handle_events', 'libusb_handle_events_completed', - 'libusb_handle_events_locked', 'libusb_handle_events_timeout', - 'libusb_handle_events_timeout_completed', 'libusb_has_capability', - 'libusb_hotplug_callback_fn', 'libusb_hotplug_callback_handle', - 'libusb_hotplug_deregister_callback', 'libusb_hotplug_event', - 'libusb_hotplug_event__enumvalues', 'libusb_hotplug_flag', - 'libusb_hotplug_flag__enumvalues', 'libusb_hotplug_get_user_data', - 'libusb_hotplug_register_callback', 'libusb_init', - 'libusb_interrupt_event_handler', 'libusb_interrupt_transfer', - 'libusb_iso_sync_type', 'libusb_iso_usage_type', - 'libusb_kernel_driver_active', 'libusb_le16_to_cpu', - 'libusb_lock_event_waiters', 'libusb_lock_events', - 'libusb_log_cb', 'libusb_log_cb_mode', 'libusb_log_level', - 'libusb_open', 'libusb_open_device_with_vid_pid', 'libusb_option', - 'libusb_pollfd_added_cb', 'libusb_pollfd_removed_cb', - 'libusb_pollfds_handle_timeouts', 'libusb_ref_device', - 'libusb_release_interface', 'libusb_request_recipient', - 'libusb_request_type', 'libusb_reset_device', - 'libusb_set_auto_detach_kernel_driver', - 'libusb_set_configuration', 'libusb_set_debug', - 'libusb_set_interface_alt_setting', - 'libusb_set_iso_packet_lengths', 'libusb_set_log_cb', - 'libusb_set_option', 'libusb_set_pollfd_notifiers', - 'libusb_setlocale', 'libusb_speed', - 'libusb_ss_usb_device_capability_attributes', - 'libusb_standard_request', 'libusb_strerror', - 'libusb_submit_transfer', 'libusb_supported_speed', - 'libusb_transfer_cb_fn', 'libusb_transfer_flags', - 'libusb_transfer_get_stream_id', 'libusb_transfer_set_stream_id', - 'libusb_transfer_status', 'libusb_transfer_type', - 'libusb_try_lock_events', 'libusb_unlock_event_waiters', - 'libusb_unlock_events', 'libusb_unref_device', - 'libusb_usb_2_0_extension_attributes', 'libusb_wait_for_event', - 'libusb_wrap_sys_device', 'size_t', 'ssize_t', - 'struct_libusb_bos_descriptor', - 'struct_libusb_bos_dev_capability_descriptor', - 'struct_libusb_config_descriptor', - 'struct_libusb_container_id_descriptor', 'struct_libusb_context', - 'struct_libusb_control_setup', 'struct_libusb_device', - 'struct_libusb_device_descriptor', 'struct_libusb_device_handle', - 'struct_libusb_endpoint_descriptor', 'struct_libusb_interface', - 'struct_libusb_interface_descriptor', - 'struct_libusb_iso_packet_descriptor', 'struct_libusb_pollfd', - 'struct_libusb_ss_endpoint_companion_descriptor', - 'struct_libusb_ss_usb_device_capability_descriptor', - 'struct_libusb_transfer', - 'struct_libusb_usb_2_0_extension_descriptor', - 'struct_libusb_version', 'struct_timeval', 'uint16_t', 'uint32_t', - 'uint8_t'] +enum_libusb_log_level = CEnum(ctypes.c_uint32) +LIBUSB_LOG_LEVEL_NONE = enum_libusb_log_level.define('LIBUSB_LOG_LEVEL_NONE', 0) +LIBUSB_LOG_LEVEL_ERROR = enum_libusb_log_level.define('LIBUSB_LOG_LEVEL_ERROR', 1) +LIBUSB_LOG_LEVEL_WARNING = enum_libusb_log_level.define('LIBUSB_LOG_LEVEL_WARNING', 2) +LIBUSB_LOG_LEVEL_INFO = enum_libusb_log_level.define('LIBUSB_LOG_LEVEL_INFO', 3) +LIBUSB_LOG_LEVEL_DEBUG = enum_libusb_log_level.define('LIBUSB_LOG_LEVEL_DEBUG', 4) + +enum_libusb_log_cb_mode = CEnum(ctypes.c_uint32) +LIBUSB_LOG_CB_GLOBAL = enum_libusb_log_cb_mode.define('LIBUSB_LOG_CB_GLOBAL', 1) +LIBUSB_LOG_CB_CONTEXT = enum_libusb_log_cb_mode.define('LIBUSB_LOG_CB_CONTEXT', 2) + +enum_libusb_option = CEnum(ctypes.c_uint32) +LIBUSB_OPTION_LOG_LEVEL = enum_libusb_option.define('LIBUSB_OPTION_LOG_LEVEL', 0) +LIBUSB_OPTION_USE_USBDK = enum_libusb_option.define('LIBUSB_OPTION_USE_USBDK', 1) +LIBUSB_OPTION_NO_DEVICE_DISCOVERY = enum_libusb_option.define('LIBUSB_OPTION_NO_DEVICE_DISCOVERY', 2) +LIBUSB_OPTION_LOG_CB = enum_libusb_option.define('LIBUSB_OPTION_LOG_CB', 3) +LIBUSB_OPTION_MAX = enum_libusb_option.define('LIBUSB_OPTION_MAX', 4) + +libusb_log_cb = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_libusb_context), enum_libusb_log_level, ctypes.POINTER(ctypes.c_char)) +class struct_libusb_init_option(Struct): pass +class struct_libusb_init_option_value(ctypes.Union): pass +struct_libusb_init_option_value._fields_ = [ + ('ival', ctypes.c_int32), + ('log_cbval', libusb_log_cb), +] +struct_libusb_init_option._fields_ = [ + ('option', enum_libusb_option), + ('value', struct_libusb_init_option_value), +] +# int libusb_init(libusb_context **ctx) +try: (libusb_init:=dll.libusb_init).restype, libusb_init.argtypes = ctypes.c_int32, [ctypes.POINTER(ctypes.POINTER(libusb_context))] +except AttributeError: pass + +# int libusb_init_context(libusb_context **ctx, const struct libusb_init_option options[], int num_options) +try: (libusb_init_context:=dll.libusb_init_context).restype, libusb_init_context.argtypes = ctypes.c_int32, [ctypes.POINTER(ctypes.POINTER(libusb_context)), (struct_libusb_init_option * 0), ctypes.c_int32] +except AttributeError: pass + +# void libusb_exit(libusb_context *ctx) +try: (libusb_exit:=dll.libusb_exit).restype, libusb_exit.argtypes = None, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_set_debug(libusb_context *ctx, int level) +try: (libusb_set_debug:=dll.libusb_set_debug).restype, libusb_set_debug.argtypes = None, [ctypes.POINTER(libusb_context), ctypes.c_int32] +except AttributeError: pass + +# void libusb_set_log_cb(libusb_context *ctx, libusb_log_cb cb, int mode) +try: (libusb_set_log_cb:=dll.libusb_set_log_cb).restype, libusb_set_log_cb.argtypes = None, [ctypes.POINTER(libusb_context), libusb_log_cb, ctypes.c_int32] +except AttributeError: pass + +# const struct libusb_version *libusb_get_version(void) +try: (libusb_get_version:=dll.libusb_get_version).restype, libusb_get_version.argtypes = ctypes.POINTER(struct_libusb_version), [] +except AttributeError: pass + +# int libusb_has_capability(uint32_t capability) +try: (libusb_has_capability:=dll.libusb_has_capability).restype, libusb_has_capability.argtypes = ctypes.c_int32, [uint32_t] +except AttributeError: pass + +# const char *libusb_error_name(int errcode) +try: (libusb_error_name:=dll.libusb_error_name).restype, libusb_error_name.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_int32] +except AttributeError: pass + +# int libusb_setlocale(const char *locale) +try: (libusb_setlocale:=dll.libusb_setlocale).restype, libusb_setlocale.argtypes = ctypes.c_int32, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const char *libusb_strerror(int errcode) +try: (libusb_strerror:=dll.libusb_strerror).restype, libusb_strerror.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_int32] +except AttributeError: pass + +ssize_t = ctypes.c_int64 +# ssize_t libusb_get_device_list(libusb_context *ctx, libusb_device ***list) +try: (libusb_get_device_list:=dll.libusb_get_device_list).restype, libusb_get_device_list.argtypes = ssize_t, [ctypes.POINTER(libusb_context), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(libusb_device)))] +except AttributeError: pass + +# void libusb_free_device_list(libusb_device **list, int unref_devices) +try: (libusb_free_device_list:=dll.libusb_free_device_list).restype, libusb_free_device_list.argtypes = None, [ctypes.POINTER(ctypes.POINTER(libusb_device)), ctypes.c_int32] +except AttributeError: pass + +# libusb_device *libusb_ref_device(libusb_device *dev) +try: (libusb_ref_device:=dll.libusb_ref_device).restype, libusb_ref_device.argtypes = ctypes.POINTER(libusb_device), [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# void libusb_unref_device(libusb_device *dev) +try: (libusb_unref_device:=dll.libusb_unref_device).restype, libusb_unref_device.argtypes = None, [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# int libusb_get_configuration(libusb_device_handle *dev, int *config) +try: (libusb_get_configuration:=dll.libusb_get_configuration).restype, libusb_get_configuration.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# int libusb_get_device_descriptor(libusb_device *dev, struct libusb_device_descriptor *desc) +try: (libusb_get_device_descriptor:=dll.libusb_get_device_descriptor).restype, libusb_get_device_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.POINTER(struct_libusb_device_descriptor)] +except AttributeError: pass + +# int libusb_get_active_config_descriptor(libusb_device *dev, struct libusb_config_descriptor **config) +try: (libusb_get_active_config_descriptor:=dll.libusb_get_active_config_descriptor).restype, libusb_get_active_config_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] +except AttributeError: pass + +# int libusb_get_config_descriptor(libusb_device *dev, uint8_t config_index, struct libusb_config_descriptor **config) +try: (libusb_get_config_descriptor:=dll.libusb_get_config_descriptor).restype, libusb_get_config_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] +except AttributeError: pass + +# int libusb_get_config_descriptor_by_value(libusb_device *dev, uint8_t bConfigurationValue, struct libusb_config_descriptor **config) +try: (libusb_get_config_descriptor_by_value:=dll.libusb_get_config_descriptor_by_value).restype, libusb_get_config_descriptor_by_value.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_config_descriptor))] +except AttributeError: pass + +# void libusb_free_config_descriptor(struct libusb_config_descriptor *config) +try: (libusb_free_config_descriptor:=dll.libusb_free_config_descriptor).restype, libusb_free_config_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_config_descriptor)] +except AttributeError: pass + +# int libusb_get_ss_endpoint_companion_descriptor(libusb_context *ctx, const struct libusb_endpoint_descriptor *endpoint, struct libusb_ss_endpoint_companion_descriptor **ep_comp) +try: (libusb_get_ss_endpoint_companion_descriptor:=dll.libusb_get_ss_endpoint_companion_descriptor).restype, libusb_get_ss_endpoint_companion_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_libusb_endpoint_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_ss_endpoint_companion_descriptor))] +except AttributeError: pass + +# void libusb_free_ss_endpoint_companion_descriptor(struct libusb_ss_endpoint_companion_descriptor *ep_comp) +try: (libusb_free_ss_endpoint_companion_descriptor:=dll.libusb_free_ss_endpoint_companion_descriptor).restype, libusb_free_ss_endpoint_companion_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_ss_endpoint_companion_descriptor)] +except AttributeError: pass + +# int libusb_get_bos_descriptor(libusb_device_handle *dev_handle, struct libusb_bos_descriptor **bos) +try: (libusb_get_bos_descriptor:=dll.libusb_get_bos_descriptor).restype, libusb_get_bos_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.POINTER(ctypes.POINTER(struct_libusb_bos_descriptor))] +except AttributeError: pass + +# void libusb_free_bos_descriptor(struct libusb_bos_descriptor *bos) +try: (libusb_free_bos_descriptor:=dll.libusb_free_bos_descriptor).restype, libusb_free_bos_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_bos_descriptor)] +except AttributeError: pass + +# int libusb_get_usb_2_0_extension_descriptor(libusb_context *ctx, struct libusb_bos_dev_capability_descriptor *dev_cap, struct libusb_usb_2_0_extension_descriptor **usb_2_0_extension) +try: (libusb_get_usb_2_0_extension_descriptor:=dll.libusb_get_usb_2_0_extension_descriptor).restype, libusb_get_usb_2_0_extension_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_usb_2_0_extension_descriptor))] +except AttributeError: pass + +# void libusb_free_usb_2_0_extension_descriptor(struct libusb_usb_2_0_extension_descriptor *usb_2_0_extension) +try: (libusb_free_usb_2_0_extension_descriptor:=dll.libusb_free_usb_2_0_extension_descriptor).restype, libusb_free_usb_2_0_extension_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_usb_2_0_extension_descriptor)] +except AttributeError: pass + +# int libusb_get_ss_usb_device_capability_descriptor(libusb_context *ctx, struct libusb_bos_dev_capability_descriptor *dev_cap, struct libusb_ss_usb_device_capability_descriptor **ss_usb_device_cap) +try: (libusb_get_ss_usb_device_capability_descriptor:=dll.libusb_get_ss_usb_device_capability_descriptor).restype, libusb_get_ss_usb_device_capability_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_ss_usb_device_capability_descriptor))] +except AttributeError: pass + +# void libusb_free_ss_usb_device_capability_descriptor(struct libusb_ss_usb_device_capability_descriptor *ss_usb_device_cap) +try: (libusb_free_ss_usb_device_capability_descriptor:=dll.libusb_free_ss_usb_device_capability_descriptor).restype, libusb_free_ss_usb_device_capability_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_ss_usb_device_capability_descriptor)] +except AttributeError: pass + +# int libusb_get_container_id_descriptor(libusb_context *ctx, struct libusb_bos_dev_capability_descriptor *dev_cap, struct libusb_container_id_descriptor **container_id) +try: (libusb_get_container_id_descriptor:=dll.libusb_get_container_id_descriptor).restype, libusb_get_container_id_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_container_id_descriptor))] +except AttributeError: pass + +# void libusb_free_container_id_descriptor(struct libusb_container_id_descriptor *container_id) +try: (libusb_free_container_id_descriptor:=dll.libusb_free_container_id_descriptor).restype, libusb_free_container_id_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_container_id_descriptor)] +except AttributeError: pass + +# int libusb_get_platform_descriptor(libusb_context *ctx, struct libusb_bos_dev_capability_descriptor *dev_cap, struct libusb_platform_descriptor **platform_descriptor) +try: (libusb_get_platform_descriptor:=dll.libusb_get_platform_descriptor).restype, libusb_get_platform_descriptor.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_libusb_bos_dev_capability_descriptor), ctypes.POINTER(ctypes.POINTER(struct_libusb_platform_descriptor))] +except AttributeError: pass + +# void libusb_free_platform_descriptor(struct libusb_platform_descriptor *platform_descriptor) +try: (libusb_free_platform_descriptor:=dll.libusb_free_platform_descriptor).restype, libusb_free_platform_descriptor.argtypes = None, [ctypes.POINTER(struct_libusb_platform_descriptor)] +except AttributeError: pass + +# uint8_t libusb_get_bus_number(libusb_device *dev) +try: (libusb_get_bus_number:=dll.libusb_get_bus_number).restype, libusb_get_bus_number.argtypes = uint8_t, [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# uint8_t libusb_get_port_number(libusb_device *dev) +try: (libusb_get_port_number:=dll.libusb_get_port_number).restype, libusb_get_port_number.argtypes = uint8_t, [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# int libusb_get_port_numbers(libusb_device *dev, uint8_t *port_numbers, int port_numbers_len) +try: (libusb_get_port_numbers:=dll.libusb_get_port_numbers).restype, libusb_get_port_numbers.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.POINTER(uint8_t), ctypes.c_int32] +except AttributeError: pass + +# __attribute__((deprecated(""))) int libusb_get_port_path(libusb_context *ctx, libusb_device *dev, uint8_t *path, uint8_t path_length) +try: (libusb_get_port_path:=dll.libusb_get_port_path).restype, libusb_get_port_path.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(libusb_device), ctypes.POINTER(uint8_t), uint8_t] +except AttributeError: pass + +# libusb_device *libusb_get_parent(libusb_device *dev) +try: (libusb_get_parent:=dll.libusb_get_parent).restype, libusb_get_parent.argtypes = ctypes.POINTER(libusb_device), [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# uint8_t libusb_get_device_address(libusb_device *dev) +try: (libusb_get_device_address:=dll.libusb_get_device_address).restype, libusb_get_device_address.argtypes = uint8_t, [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# int libusb_get_device_speed(libusb_device *dev) +try: (libusb_get_device_speed:=dll.libusb_get_device_speed).restype, libusb_get_device_speed.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device)] +except AttributeError: pass + +# int libusb_get_max_packet_size(libusb_device *dev, unsigned char endpoint) +try: (libusb_get_max_packet_size:=dll.libusb_get_max_packet_size).restype, libusb_get_max_packet_size.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.c_ubyte] +except AttributeError: pass + +# int libusb_get_max_iso_packet_size(libusb_device *dev, unsigned char endpoint) +try: (libusb_get_max_iso_packet_size:=dll.libusb_get_max_iso_packet_size).restype, libusb_get_max_iso_packet_size.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.c_ubyte] +except AttributeError: pass + +# int libusb_get_max_alt_packet_size(libusb_device *dev, int interface_number, int alternate_setting, unsigned char endpoint) +try: (libusb_get_max_alt_packet_size:=dll.libusb_get_max_alt_packet_size).restype, libusb_get_max_alt_packet_size.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.c_int32, ctypes.c_int32, ctypes.c_ubyte] +except AttributeError: pass + +# int libusb_get_interface_association_descriptors(libusb_device *dev, uint8_t config_index, struct libusb_interface_association_descriptor_array **iad_array) +try: (libusb_get_interface_association_descriptors:=dll.libusb_get_interface_association_descriptors).restype, libusb_get_interface_association_descriptors.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), uint8_t, ctypes.POINTER(ctypes.POINTER(struct_libusb_interface_association_descriptor_array))] +except AttributeError: pass + +# int libusb_get_active_interface_association_descriptors(libusb_device *dev, struct libusb_interface_association_descriptor_array **iad_array) +try: (libusb_get_active_interface_association_descriptors:=dll.libusb_get_active_interface_association_descriptors).restype, libusb_get_active_interface_association_descriptors.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.POINTER(ctypes.POINTER(struct_libusb_interface_association_descriptor_array))] +except AttributeError: pass + +# void libusb_free_interface_association_descriptors(struct libusb_interface_association_descriptor_array *iad_array) +try: (libusb_free_interface_association_descriptors:=dll.libusb_free_interface_association_descriptors).restype, libusb_free_interface_association_descriptors.argtypes = None, [ctypes.POINTER(struct_libusb_interface_association_descriptor_array)] +except AttributeError: pass + +intptr_t = ctypes.c_int64 +# int libusb_wrap_sys_device(libusb_context *ctx, intptr_t sys_dev, libusb_device_handle **dev_handle) +try: (libusb_wrap_sys_device:=dll.libusb_wrap_sys_device).restype, libusb_wrap_sys_device.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), intptr_t, ctypes.POINTER(ctypes.POINTER(libusb_device_handle))] +except AttributeError: pass + +# int libusb_open(libusb_device *dev, libusb_device_handle **dev_handle) +try: (libusb_open:=dll.libusb_open).restype, libusb_open.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device), ctypes.POINTER(ctypes.POINTER(libusb_device_handle))] +except AttributeError: pass + +# void libusb_close(libusb_device_handle *dev_handle) +try: (libusb_close:=dll.libusb_close).restype, libusb_close.argtypes = None, [ctypes.POINTER(libusb_device_handle)] +except AttributeError: pass + +# libusb_device *libusb_get_device(libusb_device_handle *dev_handle) +try: (libusb_get_device:=dll.libusb_get_device).restype, libusb_get_device.argtypes = ctypes.POINTER(libusb_device), [ctypes.POINTER(libusb_device_handle)] +except AttributeError: pass + +# int libusb_set_configuration(libusb_device_handle *dev_handle, int configuration) +try: (libusb_set_configuration:=dll.libusb_set_configuration).restype, libusb_set_configuration.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# int libusb_claim_interface(libusb_device_handle *dev_handle, int interface_number) +try: (libusb_claim_interface:=dll.libusb_claim_interface).restype, libusb_claim_interface.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# int libusb_release_interface(libusb_device_handle *dev_handle, int interface_number) +try: (libusb_release_interface:=dll.libusb_release_interface).restype, libusb_release_interface.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# libusb_device_handle *libusb_open_device_with_vid_pid(libusb_context *ctx, uint16_t vendor_id, uint16_t product_id) +try: (libusb_open_device_with_vid_pid:=dll.libusb_open_device_with_vid_pid).restype, libusb_open_device_with_vid_pid.argtypes = ctypes.POINTER(libusb_device_handle), [ctypes.POINTER(libusb_context), uint16_t, uint16_t] +except AttributeError: pass + +# int libusb_set_interface_alt_setting(libusb_device_handle *dev_handle, int interface_number, int alternate_setting) +try: (libusb_set_interface_alt_setting:=dll.libusb_set_interface_alt_setting).restype, libusb_set_interface_alt_setting.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# int libusb_clear_halt(libusb_device_handle *dev_handle, unsigned char endpoint) +try: (libusb_clear_halt:=dll.libusb_clear_halt).restype, libusb_clear_halt.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_ubyte] +except AttributeError: pass + +# int libusb_reset_device(libusb_device_handle *dev_handle) +try: (libusb_reset_device:=dll.libusb_reset_device).restype, libusb_reset_device.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle)] +except AttributeError: pass + +# int libusb_alloc_streams(libusb_device_handle *dev_handle, uint32_t num_streams, unsigned char *endpoints, int num_endpoints) +try: (libusb_alloc_streams:=dll.libusb_alloc_streams).restype, libusb_alloc_streams.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), uint32_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] +except AttributeError: pass + +# int libusb_free_streams(libusb_device_handle *dev_handle, unsigned char *endpoints, int num_endpoints) +try: (libusb_free_streams:=dll.libusb_free_streams).restype, libusb_free_streams.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] +except AttributeError: pass + +size_t = ctypes.c_uint64 +# unsigned char *libusb_dev_mem_alloc(libusb_device_handle *dev_handle, size_t length) +try: (libusb_dev_mem_alloc:=dll.libusb_dev_mem_alloc).restype, libusb_dev_mem_alloc.argtypes = ctypes.POINTER(ctypes.c_ubyte), [ctypes.POINTER(libusb_device_handle), size_t] +except AttributeError: pass + +# int libusb_dev_mem_free(libusb_device_handle *dev_handle, unsigned char *buffer, size_t length) +try: (libusb_dev_mem_free:=dll.libusb_dev_mem_free).restype, libusb_dev_mem_free.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.POINTER(ctypes.c_ubyte), size_t] +except AttributeError: pass + +# int libusb_kernel_driver_active(libusb_device_handle *dev_handle, int interface_number) +try: (libusb_kernel_driver_active:=dll.libusb_kernel_driver_active).restype, libusb_kernel_driver_active.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# int libusb_detach_kernel_driver(libusb_device_handle *dev_handle, int interface_number) +try: (libusb_detach_kernel_driver:=dll.libusb_detach_kernel_driver).restype, libusb_detach_kernel_driver.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# int libusb_attach_kernel_driver(libusb_device_handle *dev_handle, int interface_number) +try: (libusb_attach_kernel_driver:=dll.libusb_attach_kernel_driver).restype, libusb_attach_kernel_driver.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# int libusb_set_auto_detach_kernel_driver(libusb_device_handle *dev_handle, int enable) +try: (libusb_set_auto_detach_kernel_driver:=dll.libusb_set_auto_detach_kernel_driver).restype, libusb_set_auto_detach_kernel_driver.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_int32] +except AttributeError: pass + +# struct libusb_transfer *libusb_alloc_transfer(int iso_packets) +try: (libusb_alloc_transfer:=dll.libusb_alloc_transfer).restype, libusb_alloc_transfer.argtypes = ctypes.POINTER(struct_libusb_transfer), [ctypes.c_int32] +except AttributeError: pass + +# int libusb_submit_transfer(struct libusb_transfer *transfer) +try: (libusb_submit_transfer:=dll.libusb_submit_transfer).restype, libusb_submit_transfer.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_libusb_transfer)] +except AttributeError: pass + +# int libusb_cancel_transfer(struct libusb_transfer *transfer) +try: (libusb_cancel_transfer:=dll.libusb_cancel_transfer).restype, libusb_cancel_transfer.argtypes = ctypes.c_int32, [ctypes.POINTER(struct_libusb_transfer)] +except AttributeError: pass + +# void libusb_free_transfer(struct libusb_transfer *transfer) +try: (libusb_free_transfer:=dll.libusb_free_transfer).restype, libusb_free_transfer.argtypes = None, [ctypes.POINTER(struct_libusb_transfer)] +except AttributeError: pass + +# void libusb_transfer_set_stream_id(struct libusb_transfer *transfer, uint32_t stream_id) +try: (libusb_transfer_set_stream_id:=dll.libusb_transfer_set_stream_id).restype, libusb_transfer_set_stream_id.argtypes = None, [ctypes.POINTER(struct_libusb_transfer), uint32_t] +except AttributeError: pass + +# uint32_t libusb_transfer_get_stream_id(struct libusb_transfer *transfer) +try: (libusb_transfer_get_stream_id:=dll.libusb_transfer_get_stream_id).restype, libusb_transfer_get_stream_id.argtypes = uint32_t, [ctypes.POINTER(struct_libusb_transfer)] +except AttributeError: pass + +# int libusb_control_transfer(libusb_device_handle *dev_handle, uint8_t request_type, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, unsigned char *data, uint16_t wLength, unsigned int timeout) +try: (libusb_control_transfer:=dll.libusb_control_transfer).restype, libusb_control_transfer.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), uint8_t, uint8_t, uint16_t, uint16_t, ctypes.POINTER(ctypes.c_ubyte), uint16_t, ctypes.c_uint32] +except AttributeError: pass + +# int libusb_bulk_transfer(libusb_device_handle *dev_handle, unsigned char endpoint, unsigned char *data, int length, int *actual_length, unsigned int timeout) +try: (libusb_bulk_transfer:=dll.libusb_bulk_transfer).restype, libusb_bulk_transfer.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] +except AttributeError: pass + +# int libusb_interrupt_transfer(libusb_device_handle *dev_handle, unsigned char endpoint, unsigned char *data, int length, int *actual_length, unsigned int timeout) +try: (libusb_interrupt_transfer:=dll.libusb_interrupt_transfer).restype, libusb_interrupt_transfer.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), ctypes.c_ubyte, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] +except AttributeError: pass + +# int libusb_get_string_descriptor_ascii(libusb_device_handle *dev_handle, uint8_t desc_index, unsigned char *data, int length) +try: (libusb_get_string_descriptor_ascii:=dll.libusb_get_string_descriptor_ascii).restype, libusb_get_string_descriptor_ascii.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_device_handle), uint8_t, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] +except AttributeError: pass + +# int libusb_try_lock_events(libusb_context *ctx) +try: (libusb_try_lock_events:=dll.libusb_try_lock_events).restype, libusb_try_lock_events.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_lock_events(libusb_context *ctx) +try: (libusb_lock_events:=dll.libusb_lock_events).restype, libusb_lock_events.argtypes = None, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_unlock_events(libusb_context *ctx) +try: (libusb_unlock_events:=dll.libusb_unlock_events).restype, libusb_unlock_events.argtypes = None, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# int libusb_event_handling_ok(libusb_context *ctx) +try: (libusb_event_handling_ok:=dll.libusb_event_handling_ok).restype, libusb_event_handling_ok.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# int libusb_event_handler_active(libusb_context *ctx) +try: (libusb_event_handler_active:=dll.libusb_event_handler_active).restype, libusb_event_handler_active.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_interrupt_event_handler(libusb_context *ctx) +try: (libusb_interrupt_event_handler:=dll.libusb_interrupt_event_handler).restype, libusb_interrupt_event_handler.argtypes = None, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_lock_event_waiters(libusb_context *ctx) +try: (libusb_lock_event_waiters:=dll.libusb_lock_event_waiters).restype, libusb_lock_event_waiters.argtypes = None, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_unlock_event_waiters(libusb_context *ctx) +try: (libusb_unlock_event_waiters:=dll.libusb_unlock_event_waiters).restype, libusb_unlock_event_waiters.argtypes = None, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +class struct_timeval(Struct): pass +__time_t = ctypes.c_int64 +__suseconds_t = ctypes.c_int64 +struct_timeval._fields_ = [ + ('tv_sec', ctypes.c_int64), + ('tv_usec', ctypes.c_int64), +] +# int libusb_wait_for_event(libusb_context *ctx, struct timeval *tv) +try: (libusb_wait_for_event:=dll.libusb_wait_for_event).restype, libusb_wait_for_event.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# int libusb_handle_events_timeout(libusb_context *ctx, struct timeval *tv) +try: (libusb_handle_events_timeout:=dll.libusb_handle_events_timeout).restype, libusb_handle_events_timeout.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# int libusb_handle_events_timeout_completed(libusb_context *ctx, struct timeval *tv, int *completed) +try: (libusb_handle_events_timeout_completed:=dll.libusb_handle_events_timeout_completed).restype, libusb_handle_events_timeout_completed.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_timeval), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# int libusb_handle_events(libusb_context *ctx) +try: (libusb_handle_events:=dll.libusb_handle_events).restype, libusb_handle_events.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# int libusb_handle_events_completed(libusb_context *ctx, int *completed) +try: (libusb_handle_events_completed:=dll.libusb_handle_events_completed).restype, libusb_handle_events_completed.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass + +# int libusb_handle_events_locked(libusb_context *ctx, struct timeval *tv) +try: (libusb_handle_events_locked:=dll.libusb_handle_events_locked).restype, libusb_handle_events_locked.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# int libusb_pollfds_handle_timeouts(libusb_context *ctx) +try: (libusb_pollfds_handle_timeouts:=dll.libusb_pollfds_handle_timeouts).restype, libusb_pollfds_handle_timeouts.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# int libusb_get_next_timeout(libusb_context *ctx, struct timeval *tv) +try: (libusb_get_next_timeout:=dll.libusb_get_next_timeout).restype, libusb_get_next_timeout.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +class struct_libusb_pollfd(Struct): pass +struct_libusb_pollfd._fields_ = [ + ('fd', ctypes.c_int32), + ('events', ctypes.c_int16), +] +libusb_pollfd_added_cb = ctypes.CFUNCTYPE(None, ctypes.c_int32, ctypes.c_int16, ctypes.c_void_p) +libusb_pollfd_removed_cb = ctypes.CFUNCTYPE(None, ctypes.c_int32, ctypes.c_void_p) +# const struct libusb_pollfd **libusb_get_pollfds(libusb_context *ctx) +try: (libusb_get_pollfds:=dll.libusb_get_pollfds).restype, libusb_get_pollfds.argtypes = ctypes.POINTER(ctypes.POINTER(struct_libusb_pollfd)), [ctypes.POINTER(libusb_context)] +except AttributeError: pass + +# void libusb_free_pollfds(const struct libusb_pollfd **pollfds) +try: (libusb_free_pollfds:=dll.libusb_free_pollfds).restype, libusb_free_pollfds.argtypes = None, [ctypes.POINTER(ctypes.POINTER(struct_libusb_pollfd))] +except AttributeError: pass + +# void libusb_set_pollfd_notifiers(libusb_context *ctx, libusb_pollfd_added_cb added_cb, libusb_pollfd_removed_cb removed_cb, void *user_data) +try: (libusb_set_pollfd_notifiers:=dll.libusb_set_pollfd_notifiers).restype, libusb_set_pollfd_notifiers.argtypes = None, [ctypes.POINTER(libusb_context), libusb_pollfd_added_cb, libusb_pollfd_removed_cb, ctypes.c_void_p] +except AttributeError: pass + +libusb_hotplug_callback_handle = ctypes.c_int32 +libusb_hotplug_event = CEnum(ctypes.c_uint32) +LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED = libusb_hotplug_event.define('LIBUSB_HOTPLUG_EVENT_DEVICE_ARRIVED', 1) +LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT = libusb_hotplug_event.define('LIBUSB_HOTPLUG_EVENT_DEVICE_LEFT', 2) + +libusb_hotplug_flag = CEnum(ctypes.c_uint32) +LIBUSB_HOTPLUG_ENUMERATE = libusb_hotplug_flag.define('LIBUSB_HOTPLUG_ENUMERATE', 1) + +libusb_hotplug_callback_fn = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_libusb_context), ctypes.POINTER(struct_libusb_device), libusb_hotplug_event, ctypes.c_void_p) +# int libusb_hotplug_register_callback(libusb_context *ctx, int events, int flags, int vendor_id, int product_id, int dev_class, libusb_hotplug_callback_fn cb_fn, void *user_data, libusb_hotplug_callback_handle *callback_handle) +try: (libusb_hotplug_register_callback:=dll.libusb_hotplug_register_callback).restype, libusb_hotplug_register_callback.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, libusb_hotplug_callback_fn, ctypes.c_void_p, ctypes.POINTER(libusb_hotplug_callback_handle)] +except AttributeError: pass + +# void libusb_hotplug_deregister_callback(libusb_context *ctx, libusb_hotplug_callback_handle callback_handle) +try: (libusb_hotplug_deregister_callback:=dll.libusb_hotplug_deregister_callback).restype, libusb_hotplug_deregister_callback.argtypes = None, [ctypes.POINTER(libusb_context), libusb_hotplug_callback_handle] +except AttributeError: pass + +# void *libusb_hotplug_get_user_data(libusb_context *ctx, libusb_hotplug_callback_handle callback_handle) +try: (libusb_hotplug_get_user_data:=dll.libusb_hotplug_get_user_data).restype, libusb_hotplug_get_user_data.argtypes = ctypes.c_void_p, [ctypes.POINTER(libusb_context), libusb_hotplug_callback_handle] +except AttributeError: pass + +# int libusb_set_option(libusb_context *ctx, enum libusb_option option, ...) +try: (libusb_set_option:=dll.libusb_set_option).restype, libusb_set_option.argtypes = ctypes.c_int32, [ctypes.POINTER(libusb_context), enum_libusb_option] +except AttributeError: pass + +LIBUSB_DEPRECATED_FOR = lambda f: __attribute__ ((deprecated)) +LIBUSB_API_VERSION = 0x0100010A +LIBUSBX_API_VERSION = LIBUSB_API_VERSION +LIBUSB_DT_DEVICE_SIZE = 18 +LIBUSB_DT_CONFIG_SIZE = 9 +LIBUSB_DT_INTERFACE_SIZE = 9 +LIBUSB_DT_ENDPOINT_SIZE = 7 +LIBUSB_DT_ENDPOINT_AUDIO_SIZE = 9 +LIBUSB_DT_HUB_NONVAR_SIZE = 7 +LIBUSB_DT_SS_ENDPOINT_COMPANION_SIZE = 6 +LIBUSB_DT_BOS_SIZE = 5 +LIBUSB_DT_DEVICE_CAPABILITY_SIZE = 3 +LIBUSB_BT_USB_2_0_EXTENSION_SIZE = 7 +LIBUSB_BT_SS_USB_DEVICE_CAPABILITY_SIZE = 10 +LIBUSB_BT_CONTAINER_ID_SIZE = 20 +LIBUSB_BT_PLATFORM_DESCRIPTOR_MIN_SIZE = 20 +LIBUSB_DT_BOS_MAX_SIZE = (LIBUSB_DT_BOS_SIZE + LIBUSB_BT_USB_2_0_EXTENSION_SIZE + LIBUSB_BT_SS_USB_DEVICE_CAPABILITY_SIZE + LIBUSB_BT_CONTAINER_ID_SIZE) +LIBUSB_ENDPOINT_ADDRESS_MASK = 0x0f +LIBUSB_ENDPOINT_DIR_MASK = 0x80 +LIBUSB_TRANSFER_TYPE_MASK = 0x03 +LIBUSB_ISO_SYNC_TYPE_MASK = 0x0c +LIBUSB_ISO_USAGE_TYPE_MASK = 0x30 +LIBUSB_ERROR_COUNT = 14 +LIBUSB_OPTION_WEAK_AUTHORITY = LIBUSB_OPTION_NO_DEVICE_DISCOVERY +LIBUSB_HOTPLUG_NO_FLAGS = 0 +LIBUSB_HOTPLUG_MATCH_ANY = -1 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/llvm.py b/tinygrad/runtime/autogen/llvm.py index 49c0c4c837..4de6219762 100644 --- a/tinygrad/runtime/autogen/llvm.py +++ b/tinygrad/runtime/autogen/llvm.py @@ -1,11381 +1,13834 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-I/usr/lib/llvm-14/include', '-D_GNU_SOURCE', '-D__STDC_CONSTANT_MACROS', '-D__STDC_FORMAT_MACROS', '-D__STDC_LIMIT_MACROS'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, tinygrad.runtime.support.llvm as llvm_support +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from tinygrad.runtime.support.llvm import LLVM_PATH +def dll(): + try: return ctypes.CDLL(unwrap(LLVM_PATH)) + except: pass + return None +dll = dll() +intmax_t = ctypes.c_int64 +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result +class imaxdiv_t(Struct): pass +imaxdiv_t._fields_ = [ + ('quot', ctypes.c_int64), + ('rem', ctypes.c_int64), +] +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass -class Structure(ctypes.Structure, AsDictMixin): +uintmax_t = ctypes.c_uint64 +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields +__gwchar_t = ctypes.c_int32 +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass -class Union(ctypes.Union, AsDictMixin): - pass +class fd_set(Struct): pass +__fd_mask = ctypes.c_int64 +fd_set._fields_ = [ + ('fds_bits', (ctypes.c_int64 * 16)), +] +class struct_timeval(Struct): pass +__time_t = ctypes.c_int64 +__suseconds_t = ctypes.c_int64 +struct_timeval._fields_ = [ + ('tv_sec', ctypes.c_int64), + ('tv_usec', ctypes.c_int64), +] +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass +class struct_timespec(Struct): pass +__syscall_slong_t = ctypes.c_int64 +struct_timespec._fields_ = [ + ('tv_sec', ctypes.c_int64), + ('tv_nsec', ctypes.c_int64), +] +class __sigset_t(Struct): pass +__sigset_t._fields_ = [ + ('__val', (ctypes.c_uint64 * 16)), +] +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass +LLVMVerifierFailureAction = CEnum(ctypes.c_uint32) +LLVMAbortProcessAction = LLVMVerifierFailureAction.define('LLVMAbortProcessAction', 0) +LLVMPrintMessageAction = LLVMVerifierFailureAction.define('LLVMPrintMessageAction', 1) +LLVMReturnStatusAction = LLVMVerifierFailureAction.define('LLVMReturnStatusAction', 2) -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['llvm'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['llvm'] = ctypes.CDLL(llvm_support.LLVM_PATH) # ctypes.CDLL('llvm') -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -LLVM_C_ANALYSIS_H = True # macro -LLVM_C_EXTERNC_H = True # macro -# LLVM_C_STRICT_PROTOTYPES_BEGIN = _Pragma ( "clang diagnostic push" ) _Pragma ( "clang diagnostic error \"-Wstrict-prototypes\"" ) # macro -# LLVM_C_STRICT_PROTOTYPES_END = _Pragma ( "clang diagnostic pop" ) # macro -# LLVM_C_EXTERN_C_BEGIN = _Pragma ( "clang diagnostic push" ) _Pragma ( "clang diagnostic error \"-Wstrict-prototypes\"" ) # macro -# LLVM_C_EXTERN_C_END = _Pragma ( "clang diagnostic pop" ) # macro -LLVM_C_TYPES_H = True # macro -LLVM_C_DATATYPES_H = True # macro LLVMBool = ctypes.c_int32 -class struct_LLVMOpaqueMemoryBuffer(Structure): - pass - -LLVMMemoryBufferRef = ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer) -class struct_LLVMOpaqueContext(Structure): - pass - -LLVMContextRef = ctypes.POINTER(struct_LLVMOpaqueContext) -class struct_LLVMOpaqueModule(Structure): - pass - +class struct_LLVMOpaqueModule(Struct): pass LLVMModuleRef = ctypes.POINTER(struct_LLVMOpaqueModule) -class struct_LLVMOpaqueType(Structure): - pass - -LLVMTypeRef = ctypes.POINTER(struct_LLVMOpaqueType) -class struct_LLVMOpaqueValue(Structure): - pass +# LLVMBool LLVMVerifyModule(LLVMModuleRef M, LLVMVerifierFailureAction Action, char **OutMessage) +try: (LLVMVerifyModule:=dll.LLVMVerifyModule).restype, LLVMVerifyModule.argtypes = LLVMBool, [LLVMModuleRef, LLVMVerifierFailureAction, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass +class struct_LLVMOpaqueValue(Struct): pass LLVMValueRef = ctypes.POINTER(struct_LLVMOpaqueValue) -class struct_LLVMOpaqueBasicBlock(Structure): - pass +# LLVMBool LLVMVerifyFunction(LLVMValueRef Fn, LLVMVerifierFailureAction Action) +try: (LLVMVerifyFunction:=dll.LLVMVerifyFunction).restype, LLVMVerifyFunction.argtypes = LLVMBool, [LLVMValueRef, LLVMVerifierFailureAction] +except AttributeError: pass -LLVMBasicBlockRef = ctypes.POINTER(struct_LLVMOpaqueBasicBlock) -class struct_LLVMOpaqueMetadata(Structure): - pass +# void LLVMViewFunctionCFG(LLVMValueRef Fn) +try: (LLVMViewFunctionCFG:=dll.LLVMViewFunctionCFG).restype, LLVMViewFunctionCFG.argtypes = None, [LLVMValueRef] +except AttributeError: pass -LLVMMetadataRef = ctypes.POINTER(struct_LLVMOpaqueMetadata) -class struct_LLVMOpaqueNamedMDNode(Structure): - pass +# void LLVMViewFunctionCFGOnly(LLVMValueRef Fn) +try: (LLVMViewFunctionCFGOnly:=dll.LLVMViewFunctionCFGOnly).restype, LLVMViewFunctionCFGOnly.argtypes = None, [LLVMValueRef] +except AttributeError: pass -LLVMNamedMDNodeRef = ctypes.POINTER(struct_LLVMOpaqueNamedMDNode) -class struct_LLVMOpaqueValueMetadataEntry(Structure): - pass +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass -LLVMValueMetadataEntry = struct_LLVMOpaqueValueMetadataEntry -class struct_LLVMOpaqueBuilder(Structure): - pass +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass -LLVMBuilderRef = ctypes.POINTER(struct_LLVMOpaqueBuilder) -class struct_LLVMOpaqueDIBuilder(Structure): - pass +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass -LLVMDIBuilderRef = ctypes.POINTER(struct_LLVMOpaqueDIBuilder) -class struct_LLVMOpaqueModuleProvider(Structure): - pass +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass -LLVMModuleProviderRef = ctypes.POINTER(struct_LLVMOpaqueModuleProvider) -class struct_LLVMOpaquePassManager(Structure): - pass +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass -LLVMPassManagerRef = ctypes.POINTER(struct_LLVMOpaquePassManager) -class struct_LLVMOpaquePassRegistry(Structure): - pass +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass -LLVMPassRegistryRef = ctypes.POINTER(struct_LLVMOpaquePassRegistry) -class struct_LLVMOpaqueUse(Structure): - pass +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass -LLVMUseRef = ctypes.POINTER(struct_LLVMOpaqueUse) -class struct_LLVMOpaqueAttributeRef(Structure): - pass +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass -LLVMAttributeRef = ctypes.POINTER(struct_LLVMOpaqueAttributeRef) -class struct_LLVMOpaqueDiagnosticInfo(Structure): - pass +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +class struct_LLVMOpaqueMemoryBuffer(Struct): pass +LLVMMemoryBufferRef = ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer) +# LLVMBool LLVMParseBitcode(LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutModule, char **OutMessage) +try: (LLVMParseBitcode:=dll.LLVMParseBitcode).restype, LLVMParseBitcode.argtypes = LLVMBool, [LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMParseBitcode2(LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutModule) +try: (LLVMParseBitcode2:=dll.LLVMParseBitcode2).restype, LLVMParseBitcode2.argtypes = LLVMBool, [LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef)] +except AttributeError: pass + +class struct_LLVMOpaqueContext(Struct): pass +LLVMContextRef = ctypes.POINTER(struct_LLVMOpaqueContext) +# LLVMBool LLVMParseBitcodeInContext(LLVMContextRef ContextRef, LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutModule, char **OutMessage) +try: (LLVMParseBitcodeInContext:=dll.LLVMParseBitcodeInContext).restype, LLVMParseBitcodeInContext.argtypes = LLVMBool, [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMParseBitcodeInContext2(LLVMContextRef ContextRef, LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutModule) +try: (LLVMParseBitcodeInContext2:=dll.LLVMParseBitcodeInContext2).restype, LLVMParseBitcodeInContext2.argtypes = LLVMBool, [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef)] +except AttributeError: pass + +# LLVMBool LLVMGetBitcodeModuleInContext(LLVMContextRef ContextRef, LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutM, char **OutMessage) +try: (LLVMGetBitcodeModuleInContext:=dll.LLVMGetBitcodeModuleInContext).restype, LLVMGetBitcodeModuleInContext.argtypes = LLVMBool, [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMGetBitcodeModuleInContext2(LLVMContextRef ContextRef, LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutM) +try: (LLVMGetBitcodeModuleInContext2:=dll.LLVMGetBitcodeModuleInContext2).restype, LLVMGetBitcodeModuleInContext2.argtypes = LLVMBool, [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef)] +except AttributeError: pass + +# LLVMBool LLVMGetBitcodeModule(LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutM, char **OutMessage) +try: (LLVMGetBitcodeModule:=dll.LLVMGetBitcodeModule).restype, LLVMGetBitcodeModule.argtypes = LLVMBool, [LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMGetBitcodeModule2(LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutM) +try: (LLVMGetBitcodeModule2:=dll.LLVMGetBitcodeModule2).restype, LLVMGetBitcodeModule2.argtypes = LLVMBool, [LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# int LLVMWriteBitcodeToFile(LLVMModuleRef M, const char *Path) +try: (LLVMWriteBitcodeToFile:=dll.LLVMWriteBitcodeToFile).restype, LLVMWriteBitcodeToFile.argtypes = ctypes.c_int32, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# int LLVMWriteBitcodeToFD(LLVMModuleRef M, int FD, int ShouldClose, int Unbuffered) +try: (LLVMWriteBitcodeToFD:=dll.LLVMWriteBitcodeToFD).restype, LLVMWriteBitcodeToFD.argtypes = ctypes.c_int32, [LLVMModuleRef, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] +except AttributeError: pass + +# int LLVMWriteBitcodeToFileHandle(LLVMModuleRef M, int Handle) +try: (LLVMWriteBitcodeToFileHandle:=dll.LLVMWriteBitcodeToFileHandle).restype, LLVMWriteBitcodeToFileHandle.argtypes = ctypes.c_int32, [LLVMModuleRef, ctypes.c_int32] +except AttributeError: pass + +# LLVMMemoryBufferRef LLVMWriteBitcodeToMemoryBuffer(LLVMModuleRef M) +try: (LLVMWriteBitcodeToMemoryBuffer:=dll.LLVMWriteBitcodeToMemoryBuffer).restype, LLVMWriteBitcodeToMemoryBuffer.argtypes = LLVMMemoryBufferRef, [LLVMModuleRef] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +LLVMComdatSelectionKind = CEnum(ctypes.c_uint32) +LLVMAnyComdatSelectionKind = LLVMComdatSelectionKind.define('LLVMAnyComdatSelectionKind', 0) +LLVMExactMatchComdatSelectionKind = LLVMComdatSelectionKind.define('LLVMExactMatchComdatSelectionKind', 1) +LLVMLargestComdatSelectionKind = LLVMComdatSelectionKind.define('LLVMLargestComdatSelectionKind', 2) +LLVMNoDeduplicateComdatSelectionKind = LLVMComdatSelectionKind.define('LLVMNoDeduplicateComdatSelectionKind', 3) +LLVMSameSizeComdatSelectionKind = LLVMComdatSelectionKind.define('LLVMSameSizeComdatSelectionKind', 4) + +class struct_LLVMComdat(Struct): pass +LLVMComdatRef = ctypes.POINTER(struct_LLVMComdat) +# LLVMComdatRef LLVMGetOrInsertComdat(LLVMModuleRef M, const char *Name) +try: (LLVMGetOrInsertComdat:=dll.LLVMGetOrInsertComdat).restype, LLVMGetOrInsertComdat.argtypes = LLVMComdatRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMComdatRef LLVMGetComdat(LLVMValueRef V) +try: (LLVMGetComdat:=dll.LLVMGetComdat).restype, LLVMGetComdat.argtypes = LLVMComdatRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetComdat(LLVMValueRef V, LLVMComdatRef C) +try: (LLVMSetComdat:=dll.LLVMSetComdat).restype, LLVMSetComdat.argtypes = None, [LLVMValueRef, LLVMComdatRef] +except AttributeError: pass + +# LLVMComdatSelectionKind LLVMGetComdatSelectionKind(LLVMComdatRef C) +try: (LLVMGetComdatSelectionKind:=dll.LLVMGetComdatSelectionKind).restype, LLVMGetComdatSelectionKind.argtypes = LLVMComdatSelectionKind, [LLVMComdatRef] +except AttributeError: pass + +# void LLVMSetComdatSelectionKind(LLVMComdatRef C, LLVMComdatSelectionKind Kind) +try: (LLVMSetComdatSelectionKind:=dll.LLVMSetComdatSelectionKind).restype, LLVMSetComdatSelectionKind.argtypes = None, [LLVMComdatRef, LLVMComdatSelectionKind] +except AttributeError: pass + +LLVMFatalErrorHandler = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char)) +# void LLVMInstallFatalErrorHandler(LLVMFatalErrorHandler Handler) +try: (LLVMInstallFatalErrorHandler:=dll.LLVMInstallFatalErrorHandler).restype, LLVMInstallFatalErrorHandler.argtypes = None, [LLVMFatalErrorHandler] +except AttributeError: pass + +# void LLVMResetFatalErrorHandler(void) +try: (LLVMResetFatalErrorHandler:=dll.LLVMResetFatalErrorHandler).restype, LLVMResetFatalErrorHandler.argtypes = None, [] +except AttributeError: pass + +# void LLVMEnablePrettyStackTrace(void) +try: (LLVMEnablePrettyStackTrace:=dll.LLVMEnablePrettyStackTrace).restype, LLVMEnablePrettyStackTrace.argtypes = None, [] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +LLVMOpcode = CEnum(ctypes.c_uint32) +LLVMRet = LLVMOpcode.define('LLVMRet', 1) +LLVMBr = LLVMOpcode.define('LLVMBr', 2) +LLVMSwitch = LLVMOpcode.define('LLVMSwitch', 3) +LLVMIndirectBr = LLVMOpcode.define('LLVMIndirectBr', 4) +LLVMInvoke = LLVMOpcode.define('LLVMInvoke', 5) +LLVMUnreachable = LLVMOpcode.define('LLVMUnreachable', 7) +LLVMCallBr = LLVMOpcode.define('LLVMCallBr', 67) +LLVMFNeg = LLVMOpcode.define('LLVMFNeg', 66) +LLVMAdd = LLVMOpcode.define('LLVMAdd', 8) +LLVMFAdd = LLVMOpcode.define('LLVMFAdd', 9) +LLVMSub = LLVMOpcode.define('LLVMSub', 10) +LLVMFSub = LLVMOpcode.define('LLVMFSub', 11) +LLVMMul = LLVMOpcode.define('LLVMMul', 12) +LLVMFMul = LLVMOpcode.define('LLVMFMul', 13) +LLVMUDiv = LLVMOpcode.define('LLVMUDiv', 14) +LLVMSDiv = LLVMOpcode.define('LLVMSDiv', 15) +LLVMFDiv = LLVMOpcode.define('LLVMFDiv', 16) +LLVMURem = LLVMOpcode.define('LLVMURem', 17) +LLVMSRem = LLVMOpcode.define('LLVMSRem', 18) +LLVMFRem = LLVMOpcode.define('LLVMFRem', 19) +LLVMShl = LLVMOpcode.define('LLVMShl', 20) +LLVMLShr = LLVMOpcode.define('LLVMLShr', 21) +LLVMAShr = LLVMOpcode.define('LLVMAShr', 22) +LLVMAnd = LLVMOpcode.define('LLVMAnd', 23) +LLVMOr = LLVMOpcode.define('LLVMOr', 24) +LLVMXor = LLVMOpcode.define('LLVMXor', 25) +LLVMAlloca = LLVMOpcode.define('LLVMAlloca', 26) +LLVMLoad = LLVMOpcode.define('LLVMLoad', 27) +LLVMStore = LLVMOpcode.define('LLVMStore', 28) +LLVMGetElementPtr = LLVMOpcode.define('LLVMGetElementPtr', 29) +LLVMTrunc = LLVMOpcode.define('LLVMTrunc', 30) +LLVMZExt = LLVMOpcode.define('LLVMZExt', 31) +LLVMSExt = LLVMOpcode.define('LLVMSExt', 32) +LLVMFPToUI = LLVMOpcode.define('LLVMFPToUI', 33) +LLVMFPToSI = LLVMOpcode.define('LLVMFPToSI', 34) +LLVMUIToFP = LLVMOpcode.define('LLVMUIToFP', 35) +LLVMSIToFP = LLVMOpcode.define('LLVMSIToFP', 36) +LLVMFPTrunc = LLVMOpcode.define('LLVMFPTrunc', 37) +LLVMFPExt = LLVMOpcode.define('LLVMFPExt', 38) +LLVMPtrToInt = LLVMOpcode.define('LLVMPtrToInt', 39) +LLVMIntToPtr = LLVMOpcode.define('LLVMIntToPtr', 40) +LLVMBitCast = LLVMOpcode.define('LLVMBitCast', 41) +LLVMAddrSpaceCast = LLVMOpcode.define('LLVMAddrSpaceCast', 60) +LLVMICmp = LLVMOpcode.define('LLVMICmp', 42) +LLVMFCmp = LLVMOpcode.define('LLVMFCmp', 43) +LLVMPHI = LLVMOpcode.define('LLVMPHI', 44) +LLVMCall = LLVMOpcode.define('LLVMCall', 45) +LLVMSelect = LLVMOpcode.define('LLVMSelect', 46) +LLVMUserOp1 = LLVMOpcode.define('LLVMUserOp1', 47) +LLVMUserOp2 = LLVMOpcode.define('LLVMUserOp2', 48) +LLVMVAArg = LLVMOpcode.define('LLVMVAArg', 49) +LLVMExtractElement = LLVMOpcode.define('LLVMExtractElement', 50) +LLVMInsertElement = LLVMOpcode.define('LLVMInsertElement', 51) +LLVMShuffleVector = LLVMOpcode.define('LLVMShuffleVector', 52) +LLVMExtractValue = LLVMOpcode.define('LLVMExtractValue', 53) +LLVMInsertValue = LLVMOpcode.define('LLVMInsertValue', 54) +LLVMFreeze = LLVMOpcode.define('LLVMFreeze', 68) +LLVMFence = LLVMOpcode.define('LLVMFence', 55) +LLVMAtomicCmpXchg = LLVMOpcode.define('LLVMAtomicCmpXchg', 56) +LLVMAtomicRMW = LLVMOpcode.define('LLVMAtomicRMW', 57) +LLVMResume = LLVMOpcode.define('LLVMResume', 58) +LLVMLandingPad = LLVMOpcode.define('LLVMLandingPad', 59) +LLVMCleanupRet = LLVMOpcode.define('LLVMCleanupRet', 61) +LLVMCatchRet = LLVMOpcode.define('LLVMCatchRet', 62) +LLVMCatchPad = LLVMOpcode.define('LLVMCatchPad', 63) +LLVMCleanupPad = LLVMOpcode.define('LLVMCleanupPad', 64) +LLVMCatchSwitch = LLVMOpcode.define('LLVMCatchSwitch', 65) + +LLVMTypeKind = CEnum(ctypes.c_uint32) +LLVMVoidTypeKind = LLVMTypeKind.define('LLVMVoidTypeKind', 0) +LLVMHalfTypeKind = LLVMTypeKind.define('LLVMHalfTypeKind', 1) +LLVMFloatTypeKind = LLVMTypeKind.define('LLVMFloatTypeKind', 2) +LLVMDoubleTypeKind = LLVMTypeKind.define('LLVMDoubleTypeKind', 3) +LLVMX86_FP80TypeKind = LLVMTypeKind.define('LLVMX86_FP80TypeKind', 4) +LLVMFP128TypeKind = LLVMTypeKind.define('LLVMFP128TypeKind', 5) +LLVMPPC_FP128TypeKind = LLVMTypeKind.define('LLVMPPC_FP128TypeKind', 6) +LLVMLabelTypeKind = LLVMTypeKind.define('LLVMLabelTypeKind', 7) +LLVMIntegerTypeKind = LLVMTypeKind.define('LLVMIntegerTypeKind', 8) +LLVMFunctionTypeKind = LLVMTypeKind.define('LLVMFunctionTypeKind', 9) +LLVMStructTypeKind = LLVMTypeKind.define('LLVMStructTypeKind', 10) +LLVMArrayTypeKind = LLVMTypeKind.define('LLVMArrayTypeKind', 11) +LLVMPointerTypeKind = LLVMTypeKind.define('LLVMPointerTypeKind', 12) +LLVMVectorTypeKind = LLVMTypeKind.define('LLVMVectorTypeKind', 13) +LLVMMetadataTypeKind = LLVMTypeKind.define('LLVMMetadataTypeKind', 14) +LLVMTokenTypeKind = LLVMTypeKind.define('LLVMTokenTypeKind', 16) +LLVMScalableVectorTypeKind = LLVMTypeKind.define('LLVMScalableVectorTypeKind', 17) +LLVMBFloatTypeKind = LLVMTypeKind.define('LLVMBFloatTypeKind', 18) +LLVMX86_AMXTypeKind = LLVMTypeKind.define('LLVMX86_AMXTypeKind', 19) +LLVMTargetExtTypeKind = LLVMTypeKind.define('LLVMTargetExtTypeKind', 20) + +LLVMLinkage = CEnum(ctypes.c_uint32) +LLVMExternalLinkage = LLVMLinkage.define('LLVMExternalLinkage', 0) +LLVMAvailableExternallyLinkage = LLVMLinkage.define('LLVMAvailableExternallyLinkage', 1) +LLVMLinkOnceAnyLinkage = LLVMLinkage.define('LLVMLinkOnceAnyLinkage', 2) +LLVMLinkOnceODRLinkage = LLVMLinkage.define('LLVMLinkOnceODRLinkage', 3) +LLVMLinkOnceODRAutoHideLinkage = LLVMLinkage.define('LLVMLinkOnceODRAutoHideLinkage', 4) +LLVMWeakAnyLinkage = LLVMLinkage.define('LLVMWeakAnyLinkage', 5) +LLVMWeakODRLinkage = LLVMLinkage.define('LLVMWeakODRLinkage', 6) +LLVMAppendingLinkage = LLVMLinkage.define('LLVMAppendingLinkage', 7) +LLVMInternalLinkage = LLVMLinkage.define('LLVMInternalLinkage', 8) +LLVMPrivateLinkage = LLVMLinkage.define('LLVMPrivateLinkage', 9) +LLVMDLLImportLinkage = LLVMLinkage.define('LLVMDLLImportLinkage', 10) +LLVMDLLExportLinkage = LLVMLinkage.define('LLVMDLLExportLinkage', 11) +LLVMExternalWeakLinkage = LLVMLinkage.define('LLVMExternalWeakLinkage', 12) +LLVMGhostLinkage = LLVMLinkage.define('LLVMGhostLinkage', 13) +LLVMCommonLinkage = LLVMLinkage.define('LLVMCommonLinkage', 14) +LLVMLinkerPrivateLinkage = LLVMLinkage.define('LLVMLinkerPrivateLinkage', 15) +LLVMLinkerPrivateWeakLinkage = LLVMLinkage.define('LLVMLinkerPrivateWeakLinkage', 16) + +LLVMVisibility = CEnum(ctypes.c_uint32) +LLVMDefaultVisibility = LLVMVisibility.define('LLVMDefaultVisibility', 0) +LLVMHiddenVisibility = LLVMVisibility.define('LLVMHiddenVisibility', 1) +LLVMProtectedVisibility = LLVMVisibility.define('LLVMProtectedVisibility', 2) + +LLVMUnnamedAddr = CEnum(ctypes.c_uint32) +LLVMNoUnnamedAddr = LLVMUnnamedAddr.define('LLVMNoUnnamedAddr', 0) +LLVMLocalUnnamedAddr = LLVMUnnamedAddr.define('LLVMLocalUnnamedAddr', 1) +LLVMGlobalUnnamedAddr = LLVMUnnamedAddr.define('LLVMGlobalUnnamedAddr', 2) + +LLVMDLLStorageClass = CEnum(ctypes.c_uint32) +LLVMDefaultStorageClass = LLVMDLLStorageClass.define('LLVMDefaultStorageClass', 0) +LLVMDLLImportStorageClass = LLVMDLLStorageClass.define('LLVMDLLImportStorageClass', 1) +LLVMDLLExportStorageClass = LLVMDLLStorageClass.define('LLVMDLLExportStorageClass', 2) + +LLVMCallConv = CEnum(ctypes.c_uint32) +LLVMCCallConv = LLVMCallConv.define('LLVMCCallConv', 0) +LLVMFastCallConv = LLVMCallConv.define('LLVMFastCallConv', 8) +LLVMColdCallConv = LLVMCallConv.define('LLVMColdCallConv', 9) +LLVMGHCCallConv = LLVMCallConv.define('LLVMGHCCallConv', 10) +LLVMHiPECallConv = LLVMCallConv.define('LLVMHiPECallConv', 11) +LLVMAnyRegCallConv = LLVMCallConv.define('LLVMAnyRegCallConv', 13) +LLVMPreserveMostCallConv = LLVMCallConv.define('LLVMPreserveMostCallConv', 14) +LLVMPreserveAllCallConv = LLVMCallConv.define('LLVMPreserveAllCallConv', 15) +LLVMSwiftCallConv = LLVMCallConv.define('LLVMSwiftCallConv', 16) +LLVMCXXFASTTLSCallConv = LLVMCallConv.define('LLVMCXXFASTTLSCallConv', 17) +LLVMX86StdcallCallConv = LLVMCallConv.define('LLVMX86StdcallCallConv', 64) +LLVMX86FastcallCallConv = LLVMCallConv.define('LLVMX86FastcallCallConv', 65) +LLVMARMAPCSCallConv = LLVMCallConv.define('LLVMARMAPCSCallConv', 66) +LLVMARMAAPCSCallConv = LLVMCallConv.define('LLVMARMAAPCSCallConv', 67) +LLVMARMAAPCSVFPCallConv = LLVMCallConv.define('LLVMARMAAPCSVFPCallConv', 68) +LLVMMSP430INTRCallConv = LLVMCallConv.define('LLVMMSP430INTRCallConv', 69) +LLVMX86ThisCallCallConv = LLVMCallConv.define('LLVMX86ThisCallCallConv', 70) +LLVMPTXKernelCallConv = LLVMCallConv.define('LLVMPTXKernelCallConv', 71) +LLVMPTXDeviceCallConv = LLVMCallConv.define('LLVMPTXDeviceCallConv', 72) +LLVMSPIRFUNCCallConv = LLVMCallConv.define('LLVMSPIRFUNCCallConv', 75) +LLVMSPIRKERNELCallConv = LLVMCallConv.define('LLVMSPIRKERNELCallConv', 76) +LLVMIntelOCLBICallConv = LLVMCallConv.define('LLVMIntelOCLBICallConv', 77) +LLVMX8664SysVCallConv = LLVMCallConv.define('LLVMX8664SysVCallConv', 78) +LLVMWin64CallConv = LLVMCallConv.define('LLVMWin64CallConv', 79) +LLVMX86VectorCallCallConv = LLVMCallConv.define('LLVMX86VectorCallCallConv', 80) +LLVMHHVMCallConv = LLVMCallConv.define('LLVMHHVMCallConv', 81) +LLVMHHVMCCallConv = LLVMCallConv.define('LLVMHHVMCCallConv', 82) +LLVMX86INTRCallConv = LLVMCallConv.define('LLVMX86INTRCallConv', 83) +LLVMAVRINTRCallConv = LLVMCallConv.define('LLVMAVRINTRCallConv', 84) +LLVMAVRSIGNALCallConv = LLVMCallConv.define('LLVMAVRSIGNALCallConv', 85) +LLVMAVRBUILTINCallConv = LLVMCallConv.define('LLVMAVRBUILTINCallConv', 86) +LLVMAMDGPUVSCallConv = LLVMCallConv.define('LLVMAMDGPUVSCallConv', 87) +LLVMAMDGPUGSCallConv = LLVMCallConv.define('LLVMAMDGPUGSCallConv', 88) +LLVMAMDGPUPSCallConv = LLVMCallConv.define('LLVMAMDGPUPSCallConv', 89) +LLVMAMDGPUCSCallConv = LLVMCallConv.define('LLVMAMDGPUCSCallConv', 90) +LLVMAMDGPUKERNELCallConv = LLVMCallConv.define('LLVMAMDGPUKERNELCallConv', 91) +LLVMX86RegCallCallConv = LLVMCallConv.define('LLVMX86RegCallCallConv', 92) +LLVMAMDGPUHSCallConv = LLVMCallConv.define('LLVMAMDGPUHSCallConv', 93) +LLVMMSP430BUILTINCallConv = LLVMCallConv.define('LLVMMSP430BUILTINCallConv', 94) +LLVMAMDGPULSCallConv = LLVMCallConv.define('LLVMAMDGPULSCallConv', 95) +LLVMAMDGPUESCallConv = LLVMCallConv.define('LLVMAMDGPUESCallConv', 96) + +LLVMValueKind = CEnum(ctypes.c_uint32) +LLVMArgumentValueKind = LLVMValueKind.define('LLVMArgumentValueKind', 0) +LLVMBasicBlockValueKind = LLVMValueKind.define('LLVMBasicBlockValueKind', 1) +LLVMMemoryUseValueKind = LLVMValueKind.define('LLVMMemoryUseValueKind', 2) +LLVMMemoryDefValueKind = LLVMValueKind.define('LLVMMemoryDefValueKind', 3) +LLVMMemoryPhiValueKind = LLVMValueKind.define('LLVMMemoryPhiValueKind', 4) +LLVMFunctionValueKind = LLVMValueKind.define('LLVMFunctionValueKind', 5) +LLVMGlobalAliasValueKind = LLVMValueKind.define('LLVMGlobalAliasValueKind', 6) +LLVMGlobalIFuncValueKind = LLVMValueKind.define('LLVMGlobalIFuncValueKind', 7) +LLVMGlobalVariableValueKind = LLVMValueKind.define('LLVMGlobalVariableValueKind', 8) +LLVMBlockAddressValueKind = LLVMValueKind.define('LLVMBlockAddressValueKind', 9) +LLVMConstantExprValueKind = LLVMValueKind.define('LLVMConstantExprValueKind', 10) +LLVMConstantArrayValueKind = LLVMValueKind.define('LLVMConstantArrayValueKind', 11) +LLVMConstantStructValueKind = LLVMValueKind.define('LLVMConstantStructValueKind', 12) +LLVMConstantVectorValueKind = LLVMValueKind.define('LLVMConstantVectorValueKind', 13) +LLVMUndefValueValueKind = LLVMValueKind.define('LLVMUndefValueValueKind', 14) +LLVMConstantAggregateZeroValueKind = LLVMValueKind.define('LLVMConstantAggregateZeroValueKind', 15) +LLVMConstantDataArrayValueKind = LLVMValueKind.define('LLVMConstantDataArrayValueKind', 16) +LLVMConstantDataVectorValueKind = LLVMValueKind.define('LLVMConstantDataVectorValueKind', 17) +LLVMConstantIntValueKind = LLVMValueKind.define('LLVMConstantIntValueKind', 18) +LLVMConstantFPValueKind = LLVMValueKind.define('LLVMConstantFPValueKind', 19) +LLVMConstantPointerNullValueKind = LLVMValueKind.define('LLVMConstantPointerNullValueKind', 20) +LLVMConstantTokenNoneValueKind = LLVMValueKind.define('LLVMConstantTokenNoneValueKind', 21) +LLVMMetadataAsValueValueKind = LLVMValueKind.define('LLVMMetadataAsValueValueKind', 22) +LLVMInlineAsmValueKind = LLVMValueKind.define('LLVMInlineAsmValueKind', 23) +LLVMInstructionValueKind = LLVMValueKind.define('LLVMInstructionValueKind', 24) +LLVMPoisonValueValueKind = LLVMValueKind.define('LLVMPoisonValueValueKind', 25) +LLVMConstantTargetNoneValueKind = LLVMValueKind.define('LLVMConstantTargetNoneValueKind', 26) +LLVMConstantPtrAuthValueKind = LLVMValueKind.define('LLVMConstantPtrAuthValueKind', 27) + +LLVMIntPredicate = CEnum(ctypes.c_uint32) +LLVMIntEQ = LLVMIntPredicate.define('LLVMIntEQ', 32) +LLVMIntNE = LLVMIntPredicate.define('LLVMIntNE', 33) +LLVMIntUGT = LLVMIntPredicate.define('LLVMIntUGT', 34) +LLVMIntUGE = LLVMIntPredicate.define('LLVMIntUGE', 35) +LLVMIntULT = LLVMIntPredicate.define('LLVMIntULT', 36) +LLVMIntULE = LLVMIntPredicate.define('LLVMIntULE', 37) +LLVMIntSGT = LLVMIntPredicate.define('LLVMIntSGT', 38) +LLVMIntSGE = LLVMIntPredicate.define('LLVMIntSGE', 39) +LLVMIntSLT = LLVMIntPredicate.define('LLVMIntSLT', 40) +LLVMIntSLE = LLVMIntPredicate.define('LLVMIntSLE', 41) + +LLVMRealPredicate = CEnum(ctypes.c_uint32) +LLVMRealPredicateFalse = LLVMRealPredicate.define('LLVMRealPredicateFalse', 0) +LLVMRealOEQ = LLVMRealPredicate.define('LLVMRealOEQ', 1) +LLVMRealOGT = LLVMRealPredicate.define('LLVMRealOGT', 2) +LLVMRealOGE = LLVMRealPredicate.define('LLVMRealOGE', 3) +LLVMRealOLT = LLVMRealPredicate.define('LLVMRealOLT', 4) +LLVMRealOLE = LLVMRealPredicate.define('LLVMRealOLE', 5) +LLVMRealONE = LLVMRealPredicate.define('LLVMRealONE', 6) +LLVMRealORD = LLVMRealPredicate.define('LLVMRealORD', 7) +LLVMRealUNO = LLVMRealPredicate.define('LLVMRealUNO', 8) +LLVMRealUEQ = LLVMRealPredicate.define('LLVMRealUEQ', 9) +LLVMRealUGT = LLVMRealPredicate.define('LLVMRealUGT', 10) +LLVMRealUGE = LLVMRealPredicate.define('LLVMRealUGE', 11) +LLVMRealULT = LLVMRealPredicate.define('LLVMRealULT', 12) +LLVMRealULE = LLVMRealPredicate.define('LLVMRealULE', 13) +LLVMRealUNE = LLVMRealPredicate.define('LLVMRealUNE', 14) +LLVMRealPredicateTrue = LLVMRealPredicate.define('LLVMRealPredicateTrue', 15) + +LLVMLandingPadClauseTy = CEnum(ctypes.c_uint32) +LLVMLandingPadCatch = LLVMLandingPadClauseTy.define('LLVMLandingPadCatch', 0) +LLVMLandingPadFilter = LLVMLandingPadClauseTy.define('LLVMLandingPadFilter', 1) + +LLVMThreadLocalMode = CEnum(ctypes.c_uint32) +LLVMNotThreadLocal = LLVMThreadLocalMode.define('LLVMNotThreadLocal', 0) +LLVMGeneralDynamicTLSModel = LLVMThreadLocalMode.define('LLVMGeneralDynamicTLSModel', 1) +LLVMLocalDynamicTLSModel = LLVMThreadLocalMode.define('LLVMLocalDynamicTLSModel', 2) +LLVMInitialExecTLSModel = LLVMThreadLocalMode.define('LLVMInitialExecTLSModel', 3) +LLVMLocalExecTLSModel = LLVMThreadLocalMode.define('LLVMLocalExecTLSModel', 4) + +LLVMAtomicOrdering = CEnum(ctypes.c_uint32) +LLVMAtomicOrderingNotAtomic = LLVMAtomicOrdering.define('LLVMAtomicOrderingNotAtomic', 0) +LLVMAtomicOrderingUnordered = LLVMAtomicOrdering.define('LLVMAtomicOrderingUnordered', 1) +LLVMAtomicOrderingMonotonic = LLVMAtomicOrdering.define('LLVMAtomicOrderingMonotonic', 2) +LLVMAtomicOrderingAcquire = LLVMAtomicOrdering.define('LLVMAtomicOrderingAcquire', 4) +LLVMAtomicOrderingRelease = LLVMAtomicOrdering.define('LLVMAtomicOrderingRelease', 5) +LLVMAtomicOrderingAcquireRelease = LLVMAtomicOrdering.define('LLVMAtomicOrderingAcquireRelease', 6) +LLVMAtomicOrderingSequentiallyConsistent = LLVMAtomicOrdering.define('LLVMAtomicOrderingSequentiallyConsistent', 7) + +LLVMAtomicRMWBinOp = CEnum(ctypes.c_uint32) +LLVMAtomicRMWBinOpXchg = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpXchg', 0) +LLVMAtomicRMWBinOpAdd = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpAdd', 1) +LLVMAtomicRMWBinOpSub = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpSub', 2) +LLVMAtomicRMWBinOpAnd = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpAnd', 3) +LLVMAtomicRMWBinOpNand = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpNand', 4) +LLVMAtomicRMWBinOpOr = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpOr', 5) +LLVMAtomicRMWBinOpXor = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpXor', 6) +LLVMAtomicRMWBinOpMax = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpMax', 7) +LLVMAtomicRMWBinOpMin = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpMin', 8) +LLVMAtomicRMWBinOpUMax = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUMax', 9) +LLVMAtomicRMWBinOpUMin = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUMin', 10) +LLVMAtomicRMWBinOpFAdd = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFAdd', 11) +LLVMAtomicRMWBinOpFSub = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFSub', 12) +LLVMAtomicRMWBinOpFMax = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFMax', 13) +LLVMAtomicRMWBinOpFMin = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFMin', 14) +LLVMAtomicRMWBinOpUIncWrap = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUIncWrap', 15) +LLVMAtomicRMWBinOpUDecWrap = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUDecWrap', 16) +LLVMAtomicRMWBinOpUSubCond = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUSubCond', 17) +LLVMAtomicRMWBinOpUSubSat = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUSubSat', 18) + +LLVMDiagnosticSeverity = CEnum(ctypes.c_uint32) +LLVMDSError = LLVMDiagnosticSeverity.define('LLVMDSError', 0) +LLVMDSWarning = LLVMDiagnosticSeverity.define('LLVMDSWarning', 1) +LLVMDSRemark = LLVMDiagnosticSeverity.define('LLVMDSRemark', 2) +LLVMDSNote = LLVMDiagnosticSeverity.define('LLVMDSNote', 3) + +LLVMInlineAsmDialect = CEnum(ctypes.c_uint32) +LLVMInlineAsmDialectATT = LLVMInlineAsmDialect.define('LLVMInlineAsmDialectATT', 0) +LLVMInlineAsmDialectIntel = LLVMInlineAsmDialect.define('LLVMInlineAsmDialectIntel', 1) + +LLVMModuleFlagBehavior = CEnum(ctypes.c_uint32) +LLVMModuleFlagBehaviorError = LLVMModuleFlagBehavior.define('LLVMModuleFlagBehaviorError', 0) +LLVMModuleFlagBehaviorWarning = LLVMModuleFlagBehavior.define('LLVMModuleFlagBehaviorWarning', 1) +LLVMModuleFlagBehaviorRequire = LLVMModuleFlagBehavior.define('LLVMModuleFlagBehaviorRequire', 2) +LLVMModuleFlagBehaviorOverride = LLVMModuleFlagBehavior.define('LLVMModuleFlagBehaviorOverride', 3) +LLVMModuleFlagBehaviorAppend = LLVMModuleFlagBehavior.define('LLVMModuleFlagBehaviorAppend', 4) +LLVMModuleFlagBehaviorAppendUnique = LLVMModuleFlagBehavior.define('LLVMModuleFlagBehaviorAppendUnique', 5) + +_anonenum0 = CEnum(ctypes.c_int32) +LLVMAttributeReturnIndex = _anonenum0.define('LLVMAttributeReturnIndex', 0) +LLVMAttributeFunctionIndex = _anonenum0.define('LLVMAttributeFunctionIndex', -1) + +LLVMAttributeIndex = ctypes.c_uint32 +LLVMTailCallKind = CEnum(ctypes.c_uint32) +LLVMTailCallKindNone = LLVMTailCallKind.define('LLVMTailCallKindNone', 0) +LLVMTailCallKindTail = LLVMTailCallKind.define('LLVMTailCallKindTail', 1) +LLVMTailCallKindMustTail = LLVMTailCallKind.define('LLVMTailCallKindMustTail', 2) +LLVMTailCallKindNoTail = LLVMTailCallKind.define('LLVMTailCallKindNoTail', 3) + +_anonenum1 = CEnum(ctypes.c_uint32) +LLVMFastMathAllowReassoc = _anonenum1.define('LLVMFastMathAllowReassoc', 1) +LLVMFastMathNoNaNs = _anonenum1.define('LLVMFastMathNoNaNs', 2) +LLVMFastMathNoInfs = _anonenum1.define('LLVMFastMathNoInfs', 4) +LLVMFastMathNoSignedZeros = _anonenum1.define('LLVMFastMathNoSignedZeros', 8) +LLVMFastMathAllowReciprocal = _anonenum1.define('LLVMFastMathAllowReciprocal', 16) +LLVMFastMathAllowContract = _anonenum1.define('LLVMFastMathAllowContract', 32) +LLVMFastMathApproxFunc = _anonenum1.define('LLVMFastMathApproxFunc', 64) +LLVMFastMathNone = _anonenum1.define('LLVMFastMathNone', 0) +LLVMFastMathAll = _anonenum1.define('LLVMFastMathAll', 127) + +LLVMFastMathFlags = ctypes.c_uint32 +_anonenum2 = CEnum(ctypes.c_uint32) +LLVMGEPFlagInBounds = _anonenum2.define('LLVMGEPFlagInBounds', 1) +LLVMGEPFlagNUSW = _anonenum2.define('LLVMGEPFlagNUSW', 2) +LLVMGEPFlagNUW = _anonenum2.define('LLVMGEPFlagNUW', 4) + +LLVMGEPNoWrapFlags = ctypes.c_uint32 +# void LLVMShutdown(void) +try: (LLVMShutdown:=dll.LLVMShutdown).restype, LLVMShutdown.argtypes = None, [] +except AttributeError: pass + +# void LLVMGetVersion(unsigned int *Major, unsigned int *Minor, unsigned int *Patch) +try: (LLVMGetVersion:=dll.LLVMGetVersion).restype, LLVMGetVersion.argtypes = None, [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# char *LLVMCreateMessage(const char *Message) +try: (LLVMCreateMessage:=dll.LLVMCreateMessage).restype, LLVMCreateMessage.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeMessage(char *Message) +try: (LLVMDisposeMessage:=dll.LLVMDisposeMessage).restype, LLVMDisposeMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class struct_LLVMOpaqueDiagnosticInfo(Struct): pass +LLVMDiagnosticHandler = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueDiagnosticInfo), ctypes.c_void_p) +LLVMYieldCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueContext), ctypes.c_void_p) +# LLVMContextRef LLVMContextCreate(void) +try: (LLVMContextCreate:=dll.LLVMContextCreate).restype, LLVMContextCreate.argtypes = LLVMContextRef, [] +except AttributeError: pass + +# LLVMContextRef LLVMGetGlobalContext(void) +try: (LLVMGetGlobalContext:=dll.LLVMGetGlobalContext).restype, LLVMGetGlobalContext.argtypes = LLVMContextRef, [] +except AttributeError: pass + +# void LLVMContextSetDiagnosticHandler(LLVMContextRef C, LLVMDiagnosticHandler Handler, void *DiagnosticContext) +try: (LLVMContextSetDiagnosticHandler:=dll.LLVMContextSetDiagnosticHandler).restype, LLVMContextSetDiagnosticHandler.argtypes = None, [LLVMContextRef, LLVMDiagnosticHandler, ctypes.c_void_p] +except AttributeError: pass + +# LLVMDiagnosticHandler LLVMContextGetDiagnosticHandler(LLVMContextRef C) +try: (LLVMContextGetDiagnosticHandler:=dll.LLVMContextGetDiagnosticHandler).restype, LLVMContextGetDiagnosticHandler.argtypes = LLVMDiagnosticHandler, [LLVMContextRef] +except AttributeError: pass + +# void *LLVMContextGetDiagnosticContext(LLVMContextRef C) +try: (LLVMContextGetDiagnosticContext:=dll.LLVMContextGetDiagnosticContext).restype, LLVMContextGetDiagnosticContext.argtypes = ctypes.c_void_p, [LLVMContextRef] +except AttributeError: pass + +# void LLVMContextSetYieldCallback(LLVMContextRef C, LLVMYieldCallback Callback, void *OpaqueHandle) +try: (LLVMContextSetYieldCallback:=dll.LLVMContextSetYieldCallback).restype, LLVMContextSetYieldCallback.argtypes = None, [LLVMContextRef, LLVMYieldCallback, ctypes.c_void_p] +except AttributeError: pass + +# LLVMBool LLVMContextShouldDiscardValueNames(LLVMContextRef C) +try: (LLVMContextShouldDiscardValueNames:=dll.LLVMContextShouldDiscardValueNames).restype, LLVMContextShouldDiscardValueNames.argtypes = LLVMBool, [LLVMContextRef] +except AttributeError: pass + +# void LLVMContextSetDiscardValueNames(LLVMContextRef C, LLVMBool Discard) +try: (LLVMContextSetDiscardValueNames:=dll.LLVMContextSetDiscardValueNames).restype, LLVMContextSetDiscardValueNames.argtypes = None, [LLVMContextRef, LLVMBool] +except AttributeError: pass + +# void LLVMContextDispose(LLVMContextRef C) +try: (LLVMContextDispose:=dll.LLVMContextDispose).restype, LLVMContextDispose.argtypes = None, [LLVMContextRef] +except AttributeError: pass LLVMDiagnosticInfoRef = ctypes.POINTER(struct_LLVMOpaqueDiagnosticInfo) -class struct_LLVMComdat(Structure): - pass +# char *LLVMGetDiagInfoDescription(LLVMDiagnosticInfoRef DI) +try: (LLVMGetDiagInfoDescription:=dll.LLVMGetDiagInfoDescription).restype, LLVMGetDiagInfoDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMDiagnosticInfoRef] +except AttributeError: pass -LLVMComdatRef = ctypes.POINTER(struct_LLVMComdat) -class struct_LLVMOpaqueModuleFlagEntry(Structure): - pass +# LLVMDiagnosticSeverity LLVMGetDiagInfoSeverity(LLVMDiagnosticInfoRef DI) +try: (LLVMGetDiagInfoSeverity:=dll.LLVMGetDiagInfoSeverity).restype, LLVMGetDiagInfoSeverity.argtypes = LLVMDiagnosticSeverity, [LLVMDiagnosticInfoRef] +except AttributeError: pass -LLVMModuleFlagEntry = struct_LLVMOpaqueModuleFlagEntry -class struct_LLVMOpaqueJITEventListener(Structure): - pass +# unsigned int LLVMGetMDKindIDInContext(LLVMContextRef C, const char *Name, unsigned int SLen) +try: (LLVMGetMDKindIDInContext:=dll.LLVMGetMDKindIDInContext).restype, LLVMGetMDKindIDInContext.argtypes = ctypes.c_uint32, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass -LLVMJITEventListenerRef = ctypes.POINTER(struct_LLVMOpaqueJITEventListener) -class struct_LLVMOpaqueBinary(Structure): - pass +# unsigned int LLVMGetMDKindID(const char *Name, unsigned int SLen) +try: (LLVMGetMDKindID:=dll.LLVMGetMDKindID).restype, LLVMGetMDKindID.argtypes = ctypes.c_uint32, [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass -LLVMBinaryRef = ctypes.POINTER(struct_LLVMOpaqueBinary) - -# values for enumeration 'c__EA_LLVMVerifierFailureAction' -c__EA_LLVMVerifierFailureAction__enumvalues = { - 0: 'LLVMAbortProcessAction', - 1: 'LLVMPrintMessageAction', - 2: 'LLVMReturnStatusAction', -} -LLVMAbortProcessAction = 0 -LLVMPrintMessageAction = 1 -LLVMReturnStatusAction = 2 -c__EA_LLVMVerifierFailureAction = ctypes.c_uint32 # enum -LLVMVerifierFailureAction = c__EA_LLVMVerifierFailureAction -LLVMVerifierFailureAction__enumvalues = c__EA_LLVMVerifierFailureAction__enumvalues -try: - LLVMVerifyModule = _libraries['llvm'].LLVMVerifyModule - LLVMVerifyModule.restype = LLVMBool - LLVMVerifyModule.argtypes = [LLVMModuleRef, LLVMVerifierFailureAction, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMVerifyFunction = _libraries['llvm'].LLVMVerifyFunction - LLVMVerifyFunction.restype = LLVMBool - LLVMVerifyFunction.argtypes = [LLVMValueRef, LLVMVerifierFailureAction] -except AttributeError: - pass -try: - LLVMViewFunctionCFG = _libraries['llvm'].LLVMViewFunctionCFG - LLVMViewFunctionCFG.restype = None - LLVMViewFunctionCFG.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMViewFunctionCFGOnly = _libraries['llvm'].LLVMViewFunctionCFGOnly - LLVMViewFunctionCFGOnly.restype = None - LLVMViewFunctionCFGOnly.argtypes = [LLVMValueRef] -except AttributeError: - pass -LLVM_C_BITREADER_H = True # macro -try: - LLVMParseBitcode = _libraries['llvm'].LLVMParseBitcode - LLVMParseBitcode.restype = LLVMBool - LLVMParseBitcode.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMParseBitcode2 = _libraries['llvm'].LLVMParseBitcode2 - LLVMParseBitcode2.restype = LLVMBool - LLVMParseBitcode2.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -try: - LLVMParseBitcodeInContext = _libraries['llvm'].LLVMParseBitcodeInContext - LLVMParseBitcodeInContext.restype = LLVMBool - LLVMParseBitcodeInContext.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMParseBitcodeInContext2 = _libraries['llvm'].LLVMParseBitcodeInContext2 - LLVMParseBitcodeInContext2.restype = LLVMBool - LLVMParseBitcodeInContext2.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -try: - LLVMGetBitcodeModuleInContext = _libraries['llvm'].LLVMGetBitcodeModuleInContext - LLVMGetBitcodeModuleInContext.restype = LLVMBool - LLVMGetBitcodeModuleInContext.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMGetBitcodeModuleInContext2 = _libraries['llvm'].LLVMGetBitcodeModuleInContext2 - LLVMGetBitcodeModuleInContext2.restype = LLVMBool - LLVMGetBitcodeModuleInContext2.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -try: - LLVMGetBitcodeModule = _libraries['llvm'].LLVMGetBitcodeModule - LLVMGetBitcodeModule.restype = LLVMBool - LLVMGetBitcodeModule.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMGetBitcodeModule2 = _libraries['llvm'].LLVMGetBitcodeModule2 - LLVMGetBitcodeModule2.restype = LLVMBool - LLVMGetBitcodeModule2.argtypes = [LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule))] -except AttributeError: - pass -LLVM_C_BITWRITER_H = True # macro -try: - LLVMWriteBitcodeToFile = _libraries['llvm'].LLVMWriteBitcodeToFile - LLVMWriteBitcodeToFile.restype = ctypes.c_int32 - LLVMWriteBitcodeToFile.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMWriteBitcodeToFD = _libraries['llvm'].LLVMWriteBitcodeToFD - LLVMWriteBitcodeToFD.restype = ctypes.c_int32 - LLVMWriteBitcodeToFD.argtypes = [LLVMModuleRef, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - LLVMWriteBitcodeToFileHandle = _libraries['llvm'].LLVMWriteBitcodeToFileHandle - LLVMWriteBitcodeToFileHandle.restype = ctypes.c_int32 - LLVMWriteBitcodeToFileHandle.argtypes = [LLVMModuleRef, ctypes.c_int32] -except AttributeError: - pass -try: - LLVMWriteBitcodeToMemoryBuffer = _libraries['llvm'].LLVMWriteBitcodeToMemoryBuffer - LLVMWriteBitcodeToMemoryBuffer.restype = LLVMMemoryBufferRef - LLVMWriteBitcodeToMemoryBuffer.argtypes = [LLVMModuleRef] -except AttributeError: - pass -LLVM_C_COMDAT_H = True # macro - -# values for enumeration 'c__EA_LLVMComdatSelectionKind' -c__EA_LLVMComdatSelectionKind__enumvalues = { - 0: 'LLVMAnyComdatSelectionKind', - 1: 'LLVMExactMatchComdatSelectionKind', - 2: 'LLVMLargestComdatSelectionKind', - 3: 'LLVMNoDeduplicateComdatSelectionKind', - 4: 'LLVMSameSizeComdatSelectionKind', -} -LLVMAnyComdatSelectionKind = 0 -LLVMExactMatchComdatSelectionKind = 1 -LLVMLargestComdatSelectionKind = 2 -LLVMNoDeduplicateComdatSelectionKind = 3 -LLVMSameSizeComdatSelectionKind = 4 -c__EA_LLVMComdatSelectionKind = ctypes.c_uint32 # enum -LLVMComdatSelectionKind = c__EA_LLVMComdatSelectionKind -LLVMComdatSelectionKind__enumvalues = c__EA_LLVMComdatSelectionKind__enumvalues -try: - LLVMGetOrInsertComdat = _libraries['llvm'].LLVMGetOrInsertComdat - LLVMGetOrInsertComdat.restype = LLVMComdatRef - LLVMGetOrInsertComdat.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetComdat = _libraries['llvm'].LLVMGetComdat - LLVMGetComdat.restype = LLVMComdatRef - LLVMGetComdat.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetComdat = _libraries['llvm'].LLVMSetComdat - LLVMSetComdat.restype = None - LLVMSetComdat.argtypes = [LLVMValueRef, LLVMComdatRef] -except AttributeError: - pass -try: - LLVMGetComdatSelectionKind = _libraries['llvm'].LLVMGetComdatSelectionKind - LLVMGetComdatSelectionKind.restype = LLVMComdatSelectionKind - LLVMGetComdatSelectionKind.argtypes = [LLVMComdatRef] -except AttributeError: - pass -try: - LLVMSetComdatSelectionKind = _libraries['llvm'].LLVMSetComdatSelectionKind - LLVMSetComdatSelectionKind.restype = None - LLVMSetComdatSelectionKind.argtypes = [LLVMComdatRef, LLVMComdatSelectionKind] -except AttributeError: - pass -LLVM_C_CORE_H = True # macro -LLVM_C_DEPRECATED_H = True # macro -# def LLVM_ATTRIBUTE_C_DEPRECATED(decl, message): # macro -# return decl((deprecated(message))) -LLVM_C_ERRORHANDLING_H = True # macro -# def LLVM_FOR_EACH_VALUE_SUBCLASS(macro): # macro -# return macro(Argument)macro(BasicBlock)macro(InlineAsm)macro(User)macro(Constant)macro(BlockAddress)macro(ConstantAggregateZero)macro(ConstantArray)macro(ConstantDataSequential)macro(ConstantDataArray)macro(ConstantDataVector)macro(ConstantExpr)macro(ConstantFP)macro(ConstantInt)macro(ConstantPointerNull)macro(ConstantStruct)macro(ConstantTokenNone)macro(ConstantVector)macro(GlobalValue)macro(GlobalAlias)macro(GlobalObject)macro(Function)macro(GlobalVariable)macro(GlobalIFunc)macro(UndefValue)macro(PoisonValue)macro(Instruction)macro(UnaryOperator)macro(BinaryOperator)macro(CallInst)macro(IntrinsicInst)macro(DbgInfoIntrinsic)macro(DbgVariableIntrinsic)macro(DbgDeclareInst)macro(DbgLabelInst)macro(MemIntrinsic)macro(MemCpyInst)macro(MemMoveInst)macro(MemSetInst)macro(CmpInst)macro(FCmpInst)macro(ICmpInst)macro(ExtractElementInst)macro(GetElementPtrInst)macro(InsertElementInst)macro(InsertValueInst)macro(LandingPadInst)macro(PHINode)macro(SelectInst)macro(ShuffleVectorInst)macro(StoreInst)macro(BranchInst)macro(IndirectBrInst)macro(InvokeInst)macro(ReturnInst)macro(SwitchInst)macro(UnreachableInst)macro(ResumeInst)macro(CleanupReturnInst)macro(CatchReturnInst)macro(CatchSwitchInst)macro(CallBrInst)macro(FuncletPadInst)macro(CatchPadInst)macro(CleanupPadInst)macro(UnaryInstruction)macro(AllocaInst)macro(CastInst)macro(AddrSpaceCastInst)macro(BitCastInst)macro(FPExtInst)macro(FPToSIInst)macro(FPToUIInst)macro(FPTruncInst)macro(IntToPtrInst)macro(PtrToIntInst)macro(SExtInst)macro(SIToFPInst)macro(TruncInst)macro(UIToFPInst)macro(ZExtInst)macro(ExtractValueInst)macro(LoadInst)macro(VAArgInst)macro(FreezeInst)macro(AtomicCmpXchgInst)macro(AtomicRMWInst)macro(FenceInst) -# def LLVM_DECLARE_VALUE_CAST(name): # macro -# return LLVMIsA##name(Val); -LLVMFatalErrorHandler = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char)) -try: - LLVMInstallFatalErrorHandler = _libraries['llvm'].LLVMInstallFatalErrorHandler - LLVMInstallFatalErrorHandler.restype = None - LLVMInstallFatalErrorHandler.argtypes = [LLVMFatalErrorHandler] -except AttributeError: - pass -try: - LLVMResetFatalErrorHandler = _libraries['llvm'].LLVMResetFatalErrorHandler - LLVMResetFatalErrorHandler.restype = None - LLVMResetFatalErrorHandler.argtypes = [] -except AttributeError: - pass -try: - LLVMEnablePrettyStackTrace = _libraries['llvm'].LLVMEnablePrettyStackTrace - LLVMEnablePrettyStackTrace.restype = None - LLVMEnablePrettyStackTrace.argtypes = [] -except AttributeError: - pass - -# values for enumeration 'c__EA_LLVMOpcode' -c__EA_LLVMOpcode__enumvalues = { - 1: 'LLVMRet', - 2: 'LLVMBr', - 3: 'LLVMSwitch', - 4: 'LLVMIndirectBr', - 5: 'LLVMInvoke', - 7: 'LLVMUnreachable', - 67: 'LLVMCallBr', - 66: 'LLVMFNeg', - 8: 'LLVMAdd', - 9: 'LLVMFAdd', - 10: 'LLVMSub', - 11: 'LLVMFSub', - 12: 'LLVMMul', - 13: 'LLVMFMul', - 14: 'LLVMUDiv', - 15: 'LLVMSDiv', - 16: 'LLVMFDiv', - 17: 'LLVMURem', - 18: 'LLVMSRem', - 19: 'LLVMFRem', - 20: 'LLVMShl', - 21: 'LLVMLShr', - 22: 'LLVMAShr', - 23: 'LLVMAnd', - 24: 'LLVMOr', - 25: 'LLVMXor', - 26: 'LLVMAlloca', - 27: 'LLVMLoad', - 28: 'LLVMStore', - 29: 'LLVMGetElementPtr', - 30: 'LLVMTrunc', - 31: 'LLVMZExt', - 32: 'LLVMSExt', - 33: 'LLVMFPToUI', - 34: 'LLVMFPToSI', - 35: 'LLVMUIToFP', - 36: 'LLVMSIToFP', - 37: 'LLVMFPTrunc', - 38: 'LLVMFPExt', - 39: 'LLVMPtrToInt', - 40: 'LLVMIntToPtr', - 41: 'LLVMBitCast', - 60: 'LLVMAddrSpaceCast', - 42: 'LLVMICmp', - 43: 'LLVMFCmp', - 44: 'LLVMPHI', - 45: 'LLVMCall', - 46: 'LLVMSelect', - 47: 'LLVMUserOp1', - 48: 'LLVMUserOp2', - 49: 'LLVMVAArg', - 50: 'LLVMExtractElement', - 51: 'LLVMInsertElement', - 52: 'LLVMShuffleVector', - 53: 'LLVMExtractValue', - 54: 'LLVMInsertValue', - 68: 'LLVMFreeze', - 55: 'LLVMFence', - 56: 'LLVMAtomicCmpXchg', - 57: 'LLVMAtomicRMW', - 58: 'LLVMResume', - 59: 'LLVMLandingPad', - 61: 'LLVMCleanupRet', - 62: 'LLVMCatchRet', - 63: 'LLVMCatchPad', - 64: 'LLVMCleanupPad', - 65: 'LLVMCatchSwitch', -} -LLVMRet = 1 -LLVMBr = 2 -LLVMSwitch = 3 -LLVMIndirectBr = 4 -LLVMInvoke = 5 -LLVMUnreachable = 7 -LLVMCallBr = 67 -LLVMFNeg = 66 -LLVMAdd = 8 -LLVMFAdd = 9 -LLVMSub = 10 -LLVMFSub = 11 -LLVMMul = 12 -LLVMFMul = 13 -LLVMUDiv = 14 -LLVMSDiv = 15 -LLVMFDiv = 16 -LLVMURem = 17 -LLVMSRem = 18 -LLVMFRem = 19 -LLVMShl = 20 -LLVMLShr = 21 -LLVMAShr = 22 -LLVMAnd = 23 -LLVMOr = 24 -LLVMXor = 25 -LLVMAlloca = 26 -LLVMLoad = 27 -LLVMStore = 28 -LLVMGetElementPtr = 29 -LLVMTrunc = 30 -LLVMZExt = 31 -LLVMSExt = 32 -LLVMFPToUI = 33 -LLVMFPToSI = 34 -LLVMUIToFP = 35 -LLVMSIToFP = 36 -LLVMFPTrunc = 37 -LLVMFPExt = 38 -LLVMPtrToInt = 39 -LLVMIntToPtr = 40 -LLVMBitCast = 41 -LLVMAddrSpaceCast = 60 -LLVMICmp = 42 -LLVMFCmp = 43 -LLVMPHI = 44 -LLVMCall = 45 -LLVMSelect = 46 -LLVMUserOp1 = 47 -LLVMUserOp2 = 48 -LLVMVAArg = 49 -LLVMExtractElement = 50 -LLVMInsertElement = 51 -LLVMShuffleVector = 52 -LLVMExtractValue = 53 -LLVMInsertValue = 54 -LLVMFreeze = 68 -LLVMFence = 55 -LLVMAtomicCmpXchg = 56 -LLVMAtomicRMW = 57 -LLVMResume = 58 -LLVMLandingPad = 59 -LLVMCleanupRet = 61 -LLVMCatchRet = 62 -LLVMCatchPad = 63 -LLVMCleanupPad = 64 -LLVMCatchSwitch = 65 -c__EA_LLVMOpcode = ctypes.c_uint32 # enum -LLVMOpcode = c__EA_LLVMOpcode -LLVMOpcode__enumvalues = c__EA_LLVMOpcode__enumvalues - -# values for enumeration 'c__EA_LLVMTypeKind' -c__EA_LLVMTypeKind__enumvalues = { - 0: 'LLVMVoidTypeKind', - 1: 'LLVMHalfTypeKind', - 2: 'LLVMFloatTypeKind', - 3: 'LLVMDoubleTypeKind', - 4: 'LLVMX86_FP80TypeKind', - 5: 'LLVMFP128TypeKind', - 6: 'LLVMPPC_FP128TypeKind', - 7: 'LLVMLabelTypeKind', - 8: 'LLVMIntegerTypeKind', - 9: 'LLVMFunctionTypeKind', - 10: 'LLVMStructTypeKind', - 11: 'LLVMArrayTypeKind', - 12: 'LLVMPointerTypeKind', - 13: 'LLVMVectorTypeKind', - 14: 'LLVMMetadataTypeKind', - 15: 'LLVMX86_MMXTypeKind', - 16: 'LLVMTokenTypeKind', - 17: 'LLVMScalableVectorTypeKind', - 18: 'LLVMBFloatTypeKind', - 19: 'LLVMX86_AMXTypeKind', -} -LLVMVoidTypeKind = 0 -LLVMHalfTypeKind = 1 -LLVMFloatTypeKind = 2 -LLVMDoubleTypeKind = 3 -LLVMX86_FP80TypeKind = 4 -LLVMFP128TypeKind = 5 -LLVMPPC_FP128TypeKind = 6 -LLVMLabelTypeKind = 7 -LLVMIntegerTypeKind = 8 -LLVMFunctionTypeKind = 9 -LLVMStructTypeKind = 10 -LLVMArrayTypeKind = 11 -LLVMPointerTypeKind = 12 -LLVMVectorTypeKind = 13 -LLVMMetadataTypeKind = 14 -LLVMX86_MMXTypeKind = 15 -LLVMTokenTypeKind = 16 -LLVMScalableVectorTypeKind = 17 -LLVMBFloatTypeKind = 18 -LLVMX86_AMXTypeKind = 19 -c__EA_LLVMTypeKind = ctypes.c_uint32 # enum -LLVMTypeKind = c__EA_LLVMTypeKind -LLVMTypeKind__enumvalues = c__EA_LLVMTypeKind__enumvalues - -# values for enumeration 'c__EA_LLVMLinkage' -c__EA_LLVMLinkage__enumvalues = { - 0: 'LLVMExternalLinkage', - 1: 'LLVMAvailableExternallyLinkage', - 2: 'LLVMLinkOnceAnyLinkage', - 3: 'LLVMLinkOnceODRLinkage', - 4: 'LLVMLinkOnceODRAutoHideLinkage', - 5: 'LLVMWeakAnyLinkage', - 6: 'LLVMWeakODRLinkage', - 7: 'LLVMAppendingLinkage', - 8: 'LLVMInternalLinkage', - 9: 'LLVMPrivateLinkage', - 10: 'LLVMDLLImportLinkage', - 11: 'LLVMDLLExportLinkage', - 12: 'LLVMExternalWeakLinkage', - 13: 'LLVMGhostLinkage', - 14: 'LLVMCommonLinkage', - 15: 'LLVMLinkerPrivateLinkage', - 16: 'LLVMLinkerPrivateWeakLinkage', -} -LLVMExternalLinkage = 0 -LLVMAvailableExternallyLinkage = 1 -LLVMLinkOnceAnyLinkage = 2 -LLVMLinkOnceODRLinkage = 3 -LLVMLinkOnceODRAutoHideLinkage = 4 -LLVMWeakAnyLinkage = 5 -LLVMWeakODRLinkage = 6 -LLVMAppendingLinkage = 7 -LLVMInternalLinkage = 8 -LLVMPrivateLinkage = 9 -LLVMDLLImportLinkage = 10 -LLVMDLLExportLinkage = 11 -LLVMExternalWeakLinkage = 12 -LLVMGhostLinkage = 13 -LLVMCommonLinkage = 14 -LLVMLinkerPrivateLinkage = 15 -LLVMLinkerPrivateWeakLinkage = 16 -c__EA_LLVMLinkage = ctypes.c_uint32 # enum -LLVMLinkage = c__EA_LLVMLinkage -LLVMLinkage__enumvalues = c__EA_LLVMLinkage__enumvalues - -# values for enumeration 'c__EA_LLVMVisibility' -c__EA_LLVMVisibility__enumvalues = { - 0: 'LLVMDefaultVisibility', - 1: 'LLVMHiddenVisibility', - 2: 'LLVMProtectedVisibility', -} -LLVMDefaultVisibility = 0 -LLVMHiddenVisibility = 1 -LLVMProtectedVisibility = 2 -c__EA_LLVMVisibility = ctypes.c_uint32 # enum -LLVMVisibility = c__EA_LLVMVisibility -LLVMVisibility__enumvalues = c__EA_LLVMVisibility__enumvalues - -# values for enumeration 'c__EA_LLVMUnnamedAddr' -c__EA_LLVMUnnamedAddr__enumvalues = { - 0: 'LLVMNoUnnamedAddr', - 1: 'LLVMLocalUnnamedAddr', - 2: 'LLVMGlobalUnnamedAddr', -} -LLVMNoUnnamedAddr = 0 -LLVMLocalUnnamedAddr = 1 -LLVMGlobalUnnamedAddr = 2 -c__EA_LLVMUnnamedAddr = ctypes.c_uint32 # enum -LLVMUnnamedAddr = c__EA_LLVMUnnamedAddr -LLVMUnnamedAddr__enumvalues = c__EA_LLVMUnnamedAddr__enumvalues - -# values for enumeration 'c__EA_LLVMDLLStorageClass' -c__EA_LLVMDLLStorageClass__enumvalues = { - 0: 'LLVMDefaultStorageClass', - 1: 'LLVMDLLImportStorageClass', - 2: 'LLVMDLLExportStorageClass', -} -LLVMDefaultStorageClass = 0 -LLVMDLLImportStorageClass = 1 -LLVMDLLExportStorageClass = 2 -c__EA_LLVMDLLStorageClass = ctypes.c_uint32 # enum -LLVMDLLStorageClass = c__EA_LLVMDLLStorageClass -LLVMDLLStorageClass__enumvalues = c__EA_LLVMDLLStorageClass__enumvalues - -# values for enumeration 'c__EA_LLVMCallConv' -c__EA_LLVMCallConv__enumvalues = { - 0: 'LLVMCCallConv', - 8: 'LLVMFastCallConv', - 9: 'LLVMColdCallConv', - 10: 'LLVMGHCCallConv', - 11: 'LLVMHiPECallConv', - 12: 'LLVMWebKitJSCallConv', - 13: 'LLVMAnyRegCallConv', - 14: 'LLVMPreserveMostCallConv', - 15: 'LLVMPreserveAllCallConv', - 16: 'LLVMSwiftCallConv', - 17: 'LLVMCXXFASTTLSCallConv', - 64: 'LLVMX86StdcallCallConv', - 65: 'LLVMX86FastcallCallConv', - 66: 'LLVMARMAPCSCallConv', - 67: 'LLVMARMAAPCSCallConv', - 68: 'LLVMARMAAPCSVFPCallConv', - 69: 'LLVMMSP430INTRCallConv', - 70: 'LLVMX86ThisCallCallConv', - 71: 'LLVMPTXKernelCallConv', - 72: 'LLVMPTXDeviceCallConv', - 75: 'LLVMSPIRFUNCCallConv', - 76: 'LLVMSPIRKERNELCallConv', - 77: 'LLVMIntelOCLBICallConv', - 78: 'LLVMX8664SysVCallConv', - 79: 'LLVMWin64CallConv', - 80: 'LLVMX86VectorCallCallConv', - 81: 'LLVMHHVMCallConv', - 82: 'LLVMHHVMCCallConv', - 83: 'LLVMX86INTRCallConv', - 84: 'LLVMAVRINTRCallConv', - 85: 'LLVMAVRSIGNALCallConv', - 86: 'LLVMAVRBUILTINCallConv', - 87: 'LLVMAMDGPUVSCallConv', - 88: 'LLVMAMDGPUGSCallConv', - 89: 'LLVMAMDGPUPSCallConv', - 90: 'LLVMAMDGPUCSCallConv', - 91: 'LLVMAMDGPUKERNELCallConv', - 92: 'LLVMX86RegCallCallConv', - 93: 'LLVMAMDGPUHSCallConv', - 94: 'LLVMMSP430BUILTINCallConv', - 95: 'LLVMAMDGPULSCallConv', - 96: 'LLVMAMDGPUESCallConv', -} -LLVMCCallConv = 0 -LLVMFastCallConv = 8 -LLVMColdCallConv = 9 -LLVMGHCCallConv = 10 -LLVMHiPECallConv = 11 -LLVMWebKitJSCallConv = 12 -LLVMAnyRegCallConv = 13 -LLVMPreserveMostCallConv = 14 -LLVMPreserveAllCallConv = 15 -LLVMSwiftCallConv = 16 -LLVMCXXFASTTLSCallConv = 17 -LLVMX86StdcallCallConv = 64 -LLVMX86FastcallCallConv = 65 -LLVMARMAPCSCallConv = 66 -LLVMARMAAPCSCallConv = 67 -LLVMARMAAPCSVFPCallConv = 68 -LLVMMSP430INTRCallConv = 69 -LLVMX86ThisCallCallConv = 70 -LLVMPTXKernelCallConv = 71 -LLVMPTXDeviceCallConv = 72 -LLVMSPIRFUNCCallConv = 75 -LLVMSPIRKERNELCallConv = 76 -LLVMIntelOCLBICallConv = 77 -LLVMX8664SysVCallConv = 78 -LLVMWin64CallConv = 79 -LLVMX86VectorCallCallConv = 80 -LLVMHHVMCallConv = 81 -LLVMHHVMCCallConv = 82 -LLVMX86INTRCallConv = 83 -LLVMAVRINTRCallConv = 84 -LLVMAVRSIGNALCallConv = 85 -LLVMAVRBUILTINCallConv = 86 -LLVMAMDGPUVSCallConv = 87 -LLVMAMDGPUGSCallConv = 88 -LLVMAMDGPUPSCallConv = 89 -LLVMAMDGPUCSCallConv = 90 -LLVMAMDGPUKERNELCallConv = 91 -LLVMX86RegCallCallConv = 92 -LLVMAMDGPUHSCallConv = 93 -LLVMMSP430BUILTINCallConv = 94 -LLVMAMDGPULSCallConv = 95 -LLVMAMDGPUESCallConv = 96 -c__EA_LLVMCallConv = ctypes.c_uint32 # enum -LLVMCallConv = c__EA_LLVMCallConv -LLVMCallConv__enumvalues = c__EA_LLVMCallConv__enumvalues - -# values for enumeration 'c__EA_LLVMValueKind' -c__EA_LLVMValueKind__enumvalues = { - 0: 'LLVMArgumentValueKind', - 1: 'LLVMBasicBlockValueKind', - 2: 'LLVMMemoryUseValueKind', - 3: 'LLVMMemoryDefValueKind', - 4: 'LLVMMemoryPhiValueKind', - 5: 'LLVMFunctionValueKind', - 6: 'LLVMGlobalAliasValueKind', - 7: 'LLVMGlobalIFuncValueKind', - 8: 'LLVMGlobalVariableValueKind', - 9: 'LLVMBlockAddressValueKind', - 10: 'LLVMConstantExprValueKind', - 11: 'LLVMConstantArrayValueKind', - 12: 'LLVMConstantStructValueKind', - 13: 'LLVMConstantVectorValueKind', - 14: 'LLVMUndefValueValueKind', - 15: 'LLVMConstantAggregateZeroValueKind', - 16: 'LLVMConstantDataArrayValueKind', - 17: 'LLVMConstantDataVectorValueKind', - 18: 'LLVMConstantIntValueKind', - 19: 'LLVMConstantFPValueKind', - 20: 'LLVMConstantPointerNullValueKind', - 21: 'LLVMConstantTokenNoneValueKind', - 22: 'LLVMMetadataAsValueValueKind', - 23: 'LLVMInlineAsmValueKind', - 24: 'LLVMInstructionValueKind', - 25: 'LLVMPoisonValueValueKind', -} -LLVMArgumentValueKind = 0 -LLVMBasicBlockValueKind = 1 -LLVMMemoryUseValueKind = 2 -LLVMMemoryDefValueKind = 3 -LLVMMemoryPhiValueKind = 4 -LLVMFunctionValueKind = 5 -LLVMGlobalAliasValueKind = 6 -LLVMGlobalIFuncValueKind = 7 -LLVMGlobalVariableValueKind = 8 -LLVMBlockAddressValueKind = 9 -LLVMConstantExprValueKind = 10 -LLVMConstantArrayValueKind = 11 -LLVMConstantStructValueKind = 12 -LLVMConstantVectorValueKind = 13 -LLVMUndefValueValueKind = 14 -LLVMConstantAggregateZeroValueKind = 15 -LLVMConstantDataArrayValueKind = 16 -LLVMConstantDataVectorValueKind = 17 -LLVMConstantIntValueKind = 18 -LLVMConstantFPValueKind = 19 -LLVMConstantPointerNullValueKind = 20 -LLVMConstantTokenNoneValueKind = 21 -LLVMMetadataAsValueValueKind = 22 -LLVMInlineAsmValueKind = 23 -LLVMInstructionValueKind = 24 -LLVMPoisonValueValueKind = 25 -c__EA_LLVMValueKind = ctypes.c_uint32 # enum -LLVMValueKind = c__EA_LLVMValueKind -LLVMValueKind__enumvalues = c__EA_LLVMValueKind__enumvalues - -# values for enumeration 'c__EA_LLVMIntPredicate' -c__EA_LLVMIntPredicate__enumvalues = { - 32: 'LLVMIntEQ', - 33: 'LLVMIntNE', - 34: 'LLVMIntUGT', - 35: 'LLVMIntUGE', - 36: 'LLVMIntULT', - 37: 'LLVMIntULE', - 38: 'LLVMIntSGT', - 39: 'LLVMIntSGE', - 40: 'LLVMIntSLT', - 41: 'LLVMIntSLE', -} -LLVMIntEQ = 32 -LLVMIntNE = 33 -LLVMIntUGT = 34 -LLVMIntUGE = 35 -LLVMIntULT = 36 -LLVMIntULE = 37 -LLVMIntSGT = 38 -LLVMIntSGE = 39 -LLVMIntSLT = 40 -LLVMIntSLE = 41 -c__EA_LLVMIntPredicate = ctypes.c_uint32 # enum -LLVMIntPredicate = c__EA_LLVMIntPredicate -LLVMIntPredicate__enumvalues = c__EA_LLVMIntPredicate__enumvalues - -# values for enumeration 'c__EA_LLVMRealPredicate' -c__EA_LLVMRealPredicate__enumvalues = { - 0: 'LLVMRealPredicateFalse', - 1: 'LLVMRealOEQ', - 2: 'LLVMRealOGT', - 3: 'LLVMRealOGE', - 4: 'LLVMRealOLT', - 5: 'LLVMRealOLE', - 6: 'LLVMRealONE', - 7: 'LLVMRealORD', - 8: 'LLVMRealUNO', - 9: 'LLVMRealUEQ', - 10: 'LLVMRealUGT', - 11: 'LLVMRealUGE', - 12: 'LLVMRealULT', - 13: 'LLVMRealULE', - 14: 'LLVMRealUNE', - 15: 'LLVMRealPredicateTrue', -} -LLVMRealPredicateFalse = 0 -LLVMRealOEQ = 1 -LLVMRealOGT = 2 -LLVMRealOGE = 3 -LLVMRealOLT = 4 -LLVMRealOLE = 5 -LLVMRealONE = 6 -LLVMRealORD = 7 -LLVMRealUNO = 8 -LLVMRealUEQ = 9 -LLVMRealUGT = 10 -LLVMRealUGE = 11 -LLVMRealULT = 12 -LLVMRealULE = 13 -LLVMRealUNE = 14 -LLVMRealPredicateTrue = 15 -c__EA_LLVMRealPredicate = ctypes.c_uint32 # enum -LLVMRealPredicate = c__EA_LLVMRealPredicate -LLVMRealPredicate__enumvalues = c__EA_LLVMRealPredicate__enumvalues - -# values for enumeration 'c__EA_LLVMLandingPadClauseTy' -c__EA_LLVMLandingPadClauseTy__enumvalues = { - 0: 'LLVMLandingPadCatch', - 1: 'LLVMLandingPadFilter', -} -LLVMLandingPadCatch = 0 -LLVMLandingPadFilter = 1 -c__EA_LLVMLandingPadClauseTy = ctypes.c_uint32 # enum -LLVMLandingPadClauseTy = c__EA_LLVMLandingPadClauseTy -LLVMLandingPadClauseTy__enumvalues = c__EA_LLVMLandingPadClauseTy__enumvalues - -# values for enumeration 'c__EA_LLVMThreadLocalMode' -c__EA_LLVMThreadLocalMode__enumvalues = { - 0: 'LLVMNotThreadLocal', - 1: 'LLVMGeneralDynamicTLSModel', - 2: 'LLVMLocalDynamicTLSModel', - 3: 'LLVMInitialExecTLSModel', - 4: 'LLVMLocalExecTLSModel', -} -LLVMNotThreadLocal = 0 -LLVMGeneralDynamicTLSModel = 1 -LLVMLocalDynamicTLSModel = 2 -LLVMInitialExecTLSModel = 3 -LLVMLocalExecTLSModel = 4 -c__EA_LLVMThreadLocalMode = ctypes.c_uint32 # enum -LLVMThreadLocalMode = c__EA_LLVMThreadLocalMode -LLVMThreadLocalMode__enumvalues = c__EA_LLVMThreadLocalMode__enumvalues - -# values for enumeration 'c__EA_LLVMAtomicOrdering' -c__EA_LLVMAtomicOrdering__enumvalues = { - 0: 'LLVMAtomicOrderingNotAtomic', - 1: 'LLVMAtomicOrderingUnordered', - 2: 'LLVMAtomicOrderingMonotonic', - 4: 'LLVMAtomicOrderingAcquire', - 5: 'LLVMAtomicOrderingRelease', - 6: 'LLVMAtomicOrderingAcquireRelease', - 7: 'LLVMAtomicOrderingSequentiallyConsistent', -} -LLVMAtomicOrderingNotAtomic = 0 -LLVMAtomicOrderingUnordered = 1 -LLVMAtomicOrderingMonotonic = 2 -LLVMAtomicOrderingAcquire = 4 -LLVMAtomicOrderingRelease = 5 -LLVMAtomicOrderingAcquireRelease = 6 -LLVMAtomicOrderingSequentiallyConsistent = 7 -c__EA_LLVMAtomicOrdering = ctypes.c_uint32 # enum -LLVMAtomicOrdering = c__EA_LLVMAtomicOrdering -LLVMAtomicOrdering__enumvalues = c__EA_LLVMAtomicOrdering__enumvalues - -# values for enumeration 'c__EA_LLVMAtomicRMWBinOp' -c__EA_LLVMAtomicRMWBinOp__enumvalues = { - 0: 'LLVMAtomicRMWBinOpXchg', - 1: 'LLVMAtomicRMWBinOpAdd', - 2: 'LLVMAtomicRMWBinOpSub', - 3: 'LLVMAtomicRMWBinOpAnd', - 4: 'LLVMAtomicRMWBinOpNand', - 5: 'LLVMAtomicRMWBinOpOr', - 6: 'LLVMAtomicRMWBinOpXor', - 7: 'LLVMAtomicRMWBinOpMax', - 8: 'LLVMAtomicRMWBinOpMin', - 9: 'LLVMAtomicRMWBinOpUMax', - 10: 'LLVMAtomicRMWBinOpUMin', - 11: 'LLVMAtomicRMWBinOpFAdd', - 12: 'LLVMAtomicRMWBinOpFSub', -} -LLVMAtomicRMWBinOpXchg = 0 -LLVMAtomicRMWBinOpAdd = 1 -LLVMAtomicRMWBinOpSub = 2 -LLVMAtomicRMWBinOpAnd = 3 -LLVMAtomicRMWBinOpNand = 4 -LLVMAtomicRMWBinOpOr = 5 -LLVMAtomicRMWBinOpXor = 6 -LLVMAtomicRMWBinOpMax = 7 -LLVMAtomicRMWBinOpMin = 8 -LLVMAtomicRMWBinOpUMax = 9 -LLVMAtomicRMWBinOpUMin = 10 -LLVMAtomicRMWBinOpFAdd = 11 -LLVMAtomicRMWBinOpFSub = 12 -c__EA_LLVMAtomicRMWBinOp = ctypes.c_uint32 # enum -LLVMAtomicRMWBinOp = c__EA_LLVMAtomicRMWBinOp -LLVMAtomicRMWBinOp__enumvalues = c__EA_LLVMAtomicRMWBinOp__enumvalues - -# values for enumeration 'c__EA_LLVMDiagnosticSeverity' -c__EA_LLVMDiagnosticSeverity__enumvalues = { - 0: 'LLVMDSError', - 1: 'LLVMDSWarning', - 2: 'LLVMDSRemark', - 3: 'LLVMDSNote', -} -LLVMDSError = 0 -LLVMDSWarning = 1 -LLVMDSRemark = 2 -LLVMDSNote = 3 -c__EA_LLVMDiagnosticSeverity = ctypes.c_uint32 # enum -LLVMDiagnosticSeverity = c__EA_LLVMDiagnosticSeverity -LLVMDiagnosticSeverity__enumvalues = c__EA_LLVMDiagnosticSeverity__enumvalues - -# values for enumeration 'c__EA_LLVMInlineAsmDialect' -c__EA_LLVMInlineAsmDialect__enumvalues = { - 0: 'LLVMInlineAsmDialectATT', - 1: 'LLVMInlineAsmDialectIntel', -} -LLVMInlineAsmDialectATT = 0 -LLVMInlineAsmDialectIntel = 1 -c__EA_LLVMInlineAsmDialect = ctypes.c_uint32 # enum -LLVMInlineAsmDialect = c__EA_LLVMInlineAsmDialect -LLVMInlineAsmDialect__enumvalues = c__EA_LLVMInlineAsmDialect__enumvalues - -# values for enumeration 'c__EA_LLVMModuleFlagBehavior' -c__EA_LLVMModuleFlagBehavior__enumvalues = { - 0: 'LLVMModuleFlagBehaviorError', - 1: 'LLVMModuleFlagBehaviorWarning', - 2: 'LLVMModuleFlagBehaviorRequire', - 3: 'LLVMModuleFlagBehaviorOverride', - 4: 'LLVMModuleFlagBehaviorAppend', - 5: 'LLVMModuleFlagBehaviorAppendUnique', -} -LLVMModuleFlagBehaviorError = 0 -LLVMModuleFlagBehaviorWarning = 1 -LLVMModuleFlagBehaviorRequire = 2 -LLVMModuleFlagBehaviorOverride = 3 -LLVMModuleFlagBehaviorAppend = 4 -LLVMModuleFlagBehaviorAppendUnique = 5 -c__EA_LLVMModuleFlagBehavior = ctypes.c_uint32 # enum -LLVMModuleFlagBehavior = c__EA_LLVMModuleFlagBehavior -LLVMModuleFlagBehavior__enumvalues = c__EA_LLVMModuleFlagBehavior__enumvalues - -# values for enumeration 'c__Ea_LLVMAttributeReturnIndex' -c__Ea_LLVMAttributeReturnIndex__enumvalues = { - 0: 'LLVMAttributeReturnIndex', - -1: 'LLVMAttributeFunctionIndex', -} -LLVMAttributeReturnIndex = 0 -LLVMAttributeFunctionIndex = -1 -c__Ea_LLVMAttributeReturnIndex = ctypes.c_int32 # enum -LLVMAttributeIndex = ctypes.c_uint32 -try: - LLVMInitializeCore = _libraries['llvm'].LLVMInitializeCore - LLVMInitializeCore.restype = None - LLVMInitializeCore.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMShutdown = _libraries['llvm'].LLVMShutdown - LLVMShutdown.restype = None - LLVMShutdown.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateMessage = _libraries['llvm'].LLVMCreateMessage - LLVMCreateMessage.restype = ctypes.POINTER(ctypes.c_char) - LLVMCreateMessage.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDisposeMessage = _libraries['llvm'].LLVMDisposeMessage - LLVMDisposeMessage.restype = None - LLVMDisposeMessage.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -LLVMDiagnosticHandler = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueDiagnosticInfo), ctypes.POINTER(None)) -LLVMYieldCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueContext), ctypes.POINTER(None)) -try: - LLVMContextCreate = _libraries['llvm'].LLVMContextCreate - LLVMContextCreate.restype = LLVMContextRef - LLVMContextCreate.argtypes = [] -except AttributeError: - pass -try: - LLVMGetGlobalContext = _libraries['llvm'].LLVMGetGlobalContext - LLVMGetGlobalContext.restype = LLVMContextRef - LLVMGetGlobalContext.argtypes = [] -except AttributeError: - pass -try: - LLVMContextSetDiagnosticHandler = _libraries['llvm'].LLVMContextSetDiagnosticHandler - LLVMContextSetDiagnosticHandler.restype = None - LLVMContextSetDiagnosticHandler.argtypes = [LLVMContextRef, LLVMDiagnosticHandler, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMContextGetDiagnosticHandler = _libraries['llvm'].LLVMContextGetDiagnosticHandler - LLVMContextGetDiagnosticHandler.restype = LLVMDiagnosticHandler - LLVMContextGetDiagnosticHandler.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMContextGetDiagnosticContext = _libraries['llvm'].LLVMContextGetDiagnosticContext - LLVMContextGetDiagnosticContext.restype = ctypes.POINTER(None) - LLVMContextGetDiagnosticContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMContextSetYieldCallback = _libraries['llvm'].LLVMContextSetYieldCallback - LLVMContextSetYieldCallback.restype = None - LLVMContextSetYieldCallback.argtypes = [LLVMContextRef, LLVMYieldCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMContextShouldDiscardValueNames = _libraries['llvm'].LLVMContextShouldDiscardValueNames - LLVMContextShouldDiscardValueNames.restype = LLVMBool - LLVMContextShouldDiscardValueNames.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMContextSetDiscardValueNames = _libraries['llvm'].LLVMContextSetDiscardValueNames - LLVMContextSetDiscardValueNames.restype = None - LLVMContextSetDiscardValueNames.argtypes = [LLVMContextRef, LLVMBool] -except AttributeError: - pass -try: - LLVMContextDispose = _libraries['llvm'].LLVMContextDispose - LLVMContextDispose.restype = None - LLVMContextDispose.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMGetDiagInfoDescription = _libraries['llvm'].LLVMGetDiagInfoDescription - LLVMGetDiagInfoDescription.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDiagInfoDescription.argtypes = [LLVMDiagnosticInfoRef] -except AttributeError: - pass -try: - LLVMGetDiagInfoSeverity = _libraries['llvm'].LLVMGetDiagInfoSeverity - LLVMGetDiagInfoSeverity.restype = LLVMDiagnosticSeverity - LLVMGetDiagInfoSeverity.argtypes = [LLVMDiagnosticInfoRef] -except AttributeError: - pass -try: - LLVMGetMDKindIDInContext = _libraries['llvm'].LLVMGetMDKindIDInContext - LLVMGetMDKindIDInContext.restype = ctypes.c_uint32 - LLVMGetMDKindIDInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetMDKindID = _libraries['llvm'].LLVMGetMDKindID - LLVMGetMDKindID.restype = ctypes.c_uint32 - LLVMGetMDKindID.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass size_t = ctypes.c_uint64 -try: - LLVMGetEnumAttributeKindForName = _libraries['llvm'].LLVMGetEnumAttributeKindForName - LLVMGetEnumAttributeKindForName.restype = ctypes.c_uint32 - LLVMGetEnumAttributeKindForName.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetLastEnumAttributeKind = _libraries['llvm'].LLVMGetLastEnumAttributeKind - LLVMGetLastEnumAttributeKind.restype = ctypes.c_uint32 - LLVMGetLastEnumAttributeKind.argtypes = [] -except AttributeError: - pass +# unsigned int LLVMGetSyncScopeID(LLVMContextRef C, const char *Name, size_t SLen) +try: (LLVMGetSyncScopeID:=dll.LLVMGetSyncScopeID).restype, LLVMGetSyncScopeID.argtypes = ctypes.c_uint32, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# unsigned int LLVMGetEnumAttributeKindForName(const char *Name, size_t SLen) +try: (LLVMGetEnumAttributeKindForName:=dll.LLVMGetEnumAttributeKindForName).restype, LLVMGetEnumAttributeKindForName.argtypes = ctypes.c_uint32, [ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# unsigned int LLVMGetLastEnumAttributeKind(void) +try: (LLVMGetLastEnumAttributeKind:=dll.LLVMGetLastEnumAttributeKind).restype, LLVMGetLastEnumAttributeKind.argtypes = ctypes.c_uint32, [] +except AttributeError: pass + +class struct_LLVMOpaqueAttributeRef(Struct): pass +LLVMAttributeRef = ctypes.POINTER(struct_LLVMOpaqueAttributeRef) uint64_t = ctypes.c_uint64 -try: - LLVMCreateEnumAttribute = _libraries['llvm'].LLVMCreateEnumAttribute - LLVMCreateEnumAttribute.restype = LLVMAttributeRef - LLVMCreateEnumAttribute.argtypes = [LLVMContextRef, ctypes.c_uint32, uint64_t] -except AttributeError: - pass -try: - LLVMGetEnumAttributeKind = _libraries['llvm'].LLVMGetEnumAttributeKind - LLVMGetEnumAttributeKind.restype = ctypes.c_uint32 - LLVMGetEnumAttributeKind.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetEnumAttributeValue = _libraries['llvm'].LLVMGetEnumAttributeValue - LLVMGetEnumAttributeValue.restype = uint64_t - LLVMGetEnumAttributeValue.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMCreateTypeAttribute = _libraries['llvm'].LLVMCreateTypeAttribute - LLVMCreateTypeAttribute.restype = LLVMAttributeRef - LLVMCreateTypeAttribute.argtypes = [LLVMContextRef, ctypes.c_uint32, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetTypeAttributeValue = _libraries['llvm'].LLVMGetTypeAttributeValue - LLVMGetTypeAttributeValue.restype = LLVMTypeRef - LLVMGetTypeAttributeValue.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMCreateStringAttribute = _libraries['llvm'].LLVMCreateStringAttribute - LLVMCreateStringAttribute.restype = LLVMAttributeRef - LLVMCreateStringAttribute.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetStringAttributeKind = _libraries['llvm'].LLVMGetStringAttributeKind - LLVMGetStringAttributeKind.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetStringAttributeKind.argtypes = [LLVMAttributeRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetStringAttributeValue = _libraries['llvm'].LLVMGetStringAttributeValue - LLVMGetStringAttributeValue.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetStringAttributeValue.argtypes = [LLVMAttributeRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMIsEnumAttribute = _libraries['llvm'].LLVMIsEnumAttribute - LLVMIsEnumAttribute.restype = LLVMBool - LLVMIsEnumAttribute.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMIsStringAttribute = _libraries['llvm'].LLVMIsStringAttribute - LLVMIsStringAttribute.restype = LLVMBool - LLVMIsStringAttribute.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMIsTypeAttribute = _libraries['llvm'].LLVMIsTypeAttribute - LLVMIsTypeAttribute.restype = LLVMBool - LLVMIsTypeAttribute.argtypes = [LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetTypeByName2 = _libraries['llvm'].LLVMGetTypeByName2 - LLVMGetTypeByName2.restype = LLVMTypeRef - LLVMGetTypeByName2.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMModuleCreateWithName = _libraries['llvm'].LLVMModuleCreateWithName - LLVMModuleCreateWithName.restype = LLVMModuleRef - LLVMModuleCreateWithName.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMModuleCreateWithNameInContext = _libraries['llvm'].LLVMModuleCreateWithNameInContext - LLVMModuleCreateWithNameInContext.restype = LLVMModuleRef - LLVMModuleCreateWithNameInContext.argtypes = [ctypes.POINTER(ctypes.c_char), LLVMContextRef] -except AttributeError: - pass -try: - LLVMCloneModule = _libraries['llvm'].LLVMCloneModule - LLVMCloneModule.restype = LLVMModuleRef - LLVMCloneModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMDisposeModule = _libraries['llvm'].LLVMDisposeModule - LLVMDisposeModule.restype = None - LLVMDisposeModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetModuleIdentifier = _libraries['llvm'].LLVMGetModuleIdentifier - LLVMGetModuleIdentifier.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetModuleIdentifier.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetModuleIdentifier = _libraries['llvm'].LLVMSetModuleIdentifier - LLVMSetModuleIdentifier.restype = None - LLVMSetModuleIdentifier.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetSourceFileName = _libraries['llvm'].LLVMGetSourceFileName - LLVMGetSourceFileName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSourceFileName.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetSourceFileName = _libraries['llvm'].LLVMSetSourceFileName - LLVMSetSourceFileName.restype = None - LLVMSetSourceFileName.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetDataLayoutStr = _libraries['llvm'].LLVMGetDataLayoutStr - LLVMGetDataLayoutStr.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDataLayoutStr.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetDataLayout = _libraries['llvm'].LLVMGetDataLayout - LLVMGetDataLayout.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDataLayout.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMSetDataLayout = _libraries['llvm'].LLVMSetDataLayout - LLVMSetDataLayout.restype = None - LLVMSetDataLayout.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetTarget = _libraries['llvm'].LLVMGetTarget - LLVMGetTarget.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTarget.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMSetTarget = _libraries['llvm'].LLVMSetTarget - LLVMSetTarget.restype = None - LLVMSetTarget.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMCopyModuleFlagsMetadata = _libraries['llvm'].LLVMCopyModuleFlagsMetadata - LLVMCopyModuleFlagsMetadata.restype = ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry) - LLVMCopyModuleFlagsMetadata.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMDisposeModuleFlagsMetadata = _libraries['llvm'].LLVMDisposeModuleFlagsMetadata - LLVMDisposeModuleFlagsMetadata.restype = None - LLVMDisposeModuleFlagsMetadata.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry)] -except AttributeError: - pass -try: - LLVMModuleFlagEntriesGetFlagBehavior = _libraries['llvm'].LLVMModuleFlagEntriesGetFlagBehavior - LLVMModuleFlagEntriesGetFlagBehavior.restype = LLVMModuleFlagBehavior - LLVMModuleFlagEntriesGetFlagBehavior.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMModuleFlagEntriesGetKey = _libraries['llvm'].LLVMModuleFlagEntriesGetKey - LLVMModuleFlagEntriesGetKey.restype = ctypes.POINTER(ctypes.c_char) - LLVMModuleFlagEntriesGetKey.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry), ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMModuleFlagEntriesGetMetadata = _libraries['llvm'].LLVMModuleFlagEntriesGetMetadata - LLVMModuleFlagEntriesGetMetadata.restype = LLVMMetadataRef - LLVMModuleFlagEntriesGetMetadata.argtypes = [ctypes.POINTER(struct_LLVMOpaqueModuleFlagEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetModuleFlag = _libraries['llvm'].LLVMGetModuleFlag - LLVMGetModuleFlag.restype = LLVMMetadataRef - LLVMGetModuleFlag.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMAddModuleFlag = _libraries['llvm'].LLVMAddModuleFlag - LLVMAddModuleFlag.restype = None - LLVMAddModuleFlag.argtypes = [LLVMModuleRef, LLVMModuleFlagBehavior, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDumpModule = _libraries['llvm'].LLVMDumpModule - LLVMDumpModule.restype = None - LLVMDumpModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMPrintModuleToFile = _libraries['llvm'].LLVMPrintModuleToFile - LLVMPrintModuleToFile.restype = LLVMBool - LLVMPrintModuleToFile.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMPrintModuleToString = _libraries['llvm'].LLVMPrintModuleToString - LLVMPrintModuleToString.restype = ctypes.POINTER(ctypes.c_char) - LLVMPrintModuleToString.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetModuleInlineAsm = _libraries['llvm'].LLVMGetModuleInlineAsm - LLVMGetModuleInlineAsm.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetModuleInlineAsm.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetModuleInlineAsm2 = _libraries['llvm'].LLVMSetModuleInlineAsm2 - LLVMSetModuleInlineAsm2.restype = None - LLVMSetModuleInlineAsm2.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMAppendModuleInlineAsm = _libraries['llvm'].LLVMAppendModuleInlineAsm - LLVMAppendModuleInlineAsm.restype = None - LLVMAppendModuleInlineAsm.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetInlineAsm = _libraries['llvm'].LLVMGetInlineAsm - LLVMGetInlineAsm.restype = LLVMValueRef - LLVMGetInlineAsm.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool, LLVMBool, LLVMInlineAsmDialect, LLVMBool] -except AttributeError: - pass -try: - LLVMGetModuleContext = _libraries['llvm'].LLVMGetModuleContext - LLVMGetModuleContext.restype = LLVMContextRef - LLVMGetModuleContext.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetTypeByName = _libraries['llvm'].LLVMGetTypeByName - LLVMGetTypeByName.restype = LLVMTypeRef - LLVMGetTypeByName.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstNamedMetadata = _libraries['llvm'].LLVMGetFirstNamedMetadata - LLVMGetFirstNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetFirstNamedMetadata.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastNamedMetadata = _libraries['llvm'].LLVMGetLastNamedMetadata - LLVMGetLastNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetLastNamedMetadata.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextNamedMetadata = _libraries['llvm'].LLVMGetNextNamedMetadata - LLVMGetNextNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetNextNamedMetadata.argtypes = [LLVMNamedMDNodeRef] -except AttributeError: - pass -try: - LLVMGetPreviousNamedMetadata = _libraries['llvm'].LLVMGetPreviousNamedMetadata - LLVMGetPreviousNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetPreviousNamedMetadata.argtypes = [LLVMNamedMDNodeRef] -except AttributeError: - pass -try: - LLVMGetNamedMetadata = _libraries['llvm'].LLVMGetNamedMetadata - LLVMGetNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetNamedMetadata.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetOrInsertNamedMetadata = _libraries['llvm'].LLVMGetOrInsertNamedMetadata - LLVMGetOrInsertNamedMetadata.restype = LLVMNamedMDNodeRef - LLVMGetOrInsertNamedMetadata.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetNamedMetadataName = _libraries['llvm'].LLVMGetNamedMetadataName - LLVMGetNamedMetadataName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetNamedMetadataName.argtypes = [LLVMNamedMDNodeRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMGetNamedMetadataNumOperands = _libraries['llvm'].LLVMGetNamedMetadataNumOperands - LLVMGetNamedMetadataNumOperands.restype = ctypes.c_uint32 - LLVMGetNamedMetadataNumOperands.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetNamedMetadataOperands = _libraries['llvm'].LLVMGetNamedMetadataOperands - LLVMGetNamedMetadataOperands.restype = None - LLVMGetNamedMetadataOperands.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMAddNamedMetadataOperand = _libraries['llvm'].LLVMAddNamedMetadataOperand - LLVMAddNamedMetadataOperand.restype = None - LLVMAddNamedMetadataOperand.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetDebugLocDirectory = _libraries['llvm'].LLVMGetDebugLocDirectory - LLVMGetDebugLocDirectory.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDebugLocDirectory.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetDebugLocFilename = _libraries['llvm'].LLVMGetDebugLocFilename - LLVMGetDebugLocFilename.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDebugLocFilename.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetDebugLocLine = _libraries['llvm'].LLVMGetDebugLocLine - LLVMGetDebugLocLine.restype = ctypes.c_uint32 - LLVMGetDebugLocLine.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetDebugLocColumn = _libraries['llvm'].LLVMGetDebugLocColumn - LLVMGetDebugLocColumn.restype = ctypes.c_uint32 - LLVMGetDebugLocColumn.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddFunction = _libraries['llvm'].LLVMAddFunction - LLVMAddFunction.restype = LLVMValueRef - LLVMAddFunction.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetNamedFunction = _libraries['llvm'].LLVMGetNamedFunction - LLVMGetNamedFunction.restype = LLVMValueRef - LLVMGetNamedFunction.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstFunction = _libraries['llvm'].LLVMGetFirstFunction - LLVMGetFirstFunction.restype = LLVMValueRef - LLVMGetFirstFunction.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastFunction = _libraries['llvm'].LLVMGetLastFunction - LLVMGetLastFunction.restype = LLVMValueRef - LLVMGetLastFunction.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextFunction = _libraries['llvm'].LLVMGetNextFunction - LLVMGetNextFunction.restype = LLVMValueRef - LLVMGetNextFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousFunction = _libraries['llvm'].LLVMGetPreviousFunction - LLVMGetPreviousFunction.restype = LLVMValueRef - LLVMGetPreviousFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetModuleInlineAsm = _libraries['llvm'].LLVMSetModuleInlineAsm - LLVMSetModuleInlineAsm.restype = None - LLVMSetModuleInlineAsm.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetTypeKind = _libraries['llvm'].LLVMGetTypeKind - LLVMGetTypeKind.restype = LLVMTypeKind - LLVMGetTypeKind.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMTypeIsSized = _libraries['llvm'].LLVMTypeIsSized - LLVMTypeIsSized.restype = LLVMBool - LLVMTypeIsSized.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetTypeContext = _libraries['llvm'].LLVMGetTypeContext - LLVMGetTypeContext.restype = LLVMContextRef - LLVMGetTypeContext.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMDumpType = _libraries['llvm'].LLVMDumpType - LLVMDumpType.restype = None - LLVMDumpType.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPrintTypeToString = _libraries['llvm'].LLVMPrintTypeToString - LLVMPrintTypeToString.restype = ctypes.POINTER(ctypes.c_char) - LLVMPrintTypeToString.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMInt1TypeInContext = _libraries['llvm'].LLVMInt1TypeInContext - LLVMInt1TypeInContext.restype = LLVMTypeRef - LLVMInt1TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt8TypeInContext = _libraries['llvm'].LLVMInt8TypeInContext - LLVMInt8TypeInContext.restype = LLVMTypeRef - LLVMInt8TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt16TypeInContext = _libraries['llvm'].LLVMInt16TypeInContext - LLVMInt16TypeInContext.restype = LLVMTypeRef - LLVMInt16TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt32TypeInContext = _libraries['llvm'].LLVMInt32TypeInContext - LLVMInt32TypeInContext.restype = LLVMTypeRef - LLVMInt32TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt64TypeInContext = _libraries['llvm'].LLVMInt64TypeInContext - LLVMInt64TypeInContext.restype = LLVMTypeRef - LLVMInt64TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMInt128TypeInContext = _libraries['llvm'].LLVMInt128TypeInContext - LLVMInt128TypeInContext.restype = LLVMTypeRef - LLVMInt128TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMIntTypeInContext = _libraries['llvm'].LLVMIntTypeInContext - LLVMIntTypeInContext.restype = LLVMTypeRef - LLVMIntTypeInContext.argtypes = [LLVMContextRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMInt1Type = _libraries['llvm'].LLVMInt1Type - LLVMInt1Type.restype = LLVMTypeRef - LLVMInt1Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt8Type = _libraries['llvm'].LLVMInt8Type - LLVMInt8Type.restype = LLVMTypeRef - LLVMInt8Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt16Type = _libraries['llvm'].LLVMInt16Type - LLVMInt16Type.restype = LLVMTypeRef - LLVMInt16Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt32Type = _libraries['llvm'].LLVMInt32Type - LLVMInt32Type.restype = LLVMTypeRef - LLVMInt32Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt64Type = _libraries['llvm'].LLVMInt64Type - LLVMInt64Type.restype = LLVMTypeRef - LLVMInt64Type.argtypes = [] -except AttributeError: - pass -try: - LLVMInt128Type = _libraries['llvm'].LLVMInt128Type - LLVMInt128Type.restype = LLVMTypeRef - LLVMInt128Type.argtypes = [] -except AttributeError: - pass -try: - LLVMIntType = _libraries['llvm'].LLVMIntType - LLVMIntType.restype = LLVMTypeRef - LLVMIntType.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetIntTypeWidth = _libraries['llvm'].LLVMGetIntTypeWidth - LLVMGetIntTypeWidth.restype = ctypes.c_uint32 - LLVMGetIntTypeWidth.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMHalfTypeInContext = _libraries['llvm'].LLVMHalfTypeInContext - LLVMHalfTypeInContext.restype = LLVMTypeRef - LLVMHalfTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMBFloatTypeInContext = _libraries['llvm'].LLVMBFloatTypeInContext - LLVMBFloatTypeInContext.restype = LLVMTypeRef - LLVMBFloatTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMFloatTypeInContext = _libraries['llvm'].LLVMFloatTypeInContext - LLVMFloatTypeInContext.restype = LLVMTypeRef - LLVMFloatTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMDoubleTypeInContext = _libraries['llvm'].LLVMDoubleTypeInContext - LLVMDoubleTypeInContext.restype = LLVMTypeRef - LLVMDoubleTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMX86FP80TypeInContext = _libraries['llvm'].LLVMX86FP80TypeInContext - LLVMX86FP80TypeInContext.restype = LLVMTypeRef - LLVMX86FP80TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMFP128TypeInContext = _libraries['llvm'].LLVMFP128TypeInContext - LLVMFP128TypeInContext.restype = LLVMTypeRef - LLVMFP128TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMPPCFP128TypeInContext = _libraries['llvm'].LLVMPPCFP128TypeInContext - LLVMPPCFP128TypeInContext.restype = LLVMTypeRef - LLVMPPCFP128TypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMHalfType = _libraries['llvm'].LLVMHalfType - LLVMHalfType.restype = LLVMTypeRef - LLVMHalfType.argtypes = [] -except AttributeError: - pass -try: - LLVMBFloatType = _libraries['llvm'].LLVMBFloatType - LLVMBFloatType.restype = LLVMTypeRef - LLVMBFloatType.argtypes = [] -except AttributeError: - pass -try: - LLVMFloatType = _libraries['llvm'].LLVMFloatType - LLVMFloatType.restype = LLVMTypeRef - LLVMFloatType.argtypes = [] -except AttributeError: - pass -try: - LLVMDoubleType = _libraries['llvm'].LLVMDoubleType - LLVMDoubleType.restype = LLVMTypeRef - LLVMDoubleType.argtypes = [] -except AttributeError: - pass -try: - LLVMX86FP80Type = _libraries['llvm'].LLVMX86FP80Type - LLVMX86FP80Type.restype = LLVMTypeRef - LLVMX86FP80Type.argtypes = [] -except AttributeError: - pass -try: - LLVMFP128Type = _libraries['llvm'].LLVMFP128Type - LLVMFP128Type.restype = LLVMTypeRef - LLVMFP128Type.argtypes = [] -except AttributeError: - pass -try: - LLVMPPCFP128Type = _libraries['llvm'].LLVMPPCFP128Type - LLVMPPCFP128Type.restype = LLVMTypeRef - LLVMPPCFP128Type.argtypes = [] -except AttributeError: - pass -try: - LLVMFunctionType = _libraries['llvm'].LLVMFunctionType - LLVMFunctionType.restype = LLVMTypeRef - LLVMFunctionType.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMIsFunctionVarArg = _libraries['llvm'].LLVMIsFunctionVarArg - LLVMIsFunctionVarArg.restype = LLVMBool - LLVMIsFunctionVarArg.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetReturnType = _libraries['llvm'].LLVMGetReturnType - LLVMGetReturnType.restype = LLVMTypeRef - LLVMGetReturnType.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMCountParamTypes = _libraries['llvm'].LLVMCountParamTypes - LLVMCountParamTypes.restype = ctypes.c_uint32 - LLVMCountParamTypes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetParamTypes = _libraries['llvm'].LLVMGetParamTypes - LLVMGetParamTypes.restype = None - LLVMGetParamTypes.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType))] -except AttributeError: - pass -try: - LLVMStructTypeInContext = _libraries['llvm'].LLVMStructTypeInContext - LLVMStructTypeInContext.restype = LLVMTypeRef - LLVMStructTypeInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMStructType = _libraries['llvm'].LLVMStructType - LLVMStructType.restype = LLVMTypeRef - LLVMStructType.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMStructCreateNamed = _libraries['llvm'].LLVMStructCreateNamed - LLVMStructCreateNamed.restype = LLVMTypeRef - LLVMStructCreateNamed.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetStructName = _libraries['llvm'].LLVMGetStructName - LLVMGetStructName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetStructName.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMStructSetBody = _libraries['llvm'].LLVMStructSetBody - LLVMStructSetBody.restype = None - LLVMStructSetBody.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMCountStructElementTypes = _libraries['llvm'].LLVMCountStructElementTypes - LLVMCountStructElementTypes.restype = ctypes.c_uint32 - LLVMCountStructElementTypes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetStructElementTypes = _libraries['llvm'].LLVMGetStructElementTypes - LLVMGetStructElementTypes.restype = None - LLVMGetStructElementTypes.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType))] -except AttributeError: - pass -try: - LLVMStructGetTypeAtIndex = _libraries['llvm'].LLVMStructGetTypeAtIndex - LLVMStructGetTypeAtIndex.restype = LLVMTypeRef - LLVMStructGetTypeAtIndex.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIsPackedStruct = _libraries['llvm'].LLVMIsPackedStruct - LLVMIsPackedStruct.restype = LLVMBool - LLVMIsPackedStruct.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMIsOpaqueStruct = _libraries['llvm'].LLVMIsOpaqueStruct - LLVMIsOpaqueStruct.restype = LLVMBool - LLVMIsOpaqueStruct.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMIsLiteralStruct = _libraries['llvm'].LLVMIsLiteralStruct - LLVMIsLiteralStruct.restype = LLVMBool - LLVMIsLiteralStruct.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetElementType = _libraries['llvm'].LLVMGetElementType - LLVMGetElementType.restype = LLVMTypeRef - LLVMGetElementType.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetSubtypes = _libraries['llvm'].LLVMGetSubtypes - LLVMGetSubtypes.restype = None - LLVMGetSubtypes.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType))] -except AttributeError: - pass -try: - LLVMGetNumContainedTypes = _libraries['llvm'].LLVMGetNumContainedTypes - LLVMGetNumContainedTypes.restype = ctypes.c_uint32 - LLVMGetNumContainedTypes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMArrayType = _libraries['llvm'].LLVMArrayType - LLVMArrayType.restype = LLVMTypeRef - LLVMArrayType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetArrayLength = _libraries['llvm'].LLVMGetArrayLength - LLVMGetArrayLength.restype = ctypes.c_uint32 - LLVMGetArrayLength.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPointerType = _libraries['llvm'].LLVMPointerType - LLVMPointerType.restype = LLVMTypeRef - LLVMPointerType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetPointerAddressSpace = _libraries['llvm'].LLVMGetPointerAddressSpace - LLVMGetPointerAddressSpace.restype = ctypes.c_uint32 - LLVMGetPointerAddressSpace.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMVectorType = _libraries['llvm'].LLVMVectorType - LLVMVectorType.restype = LLVMTypeRef - LLVMVectorType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMScalableVectorType = _libraries['llvm'].LLVMScalableVectorType - LLVMScalableVectorType.restype = LLVMTypeRef - LLVMScalableVectorType.argtypes = [LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetVectorSize = _libraries['llvm'].LLVMGetVectorSize - LLVMGetVectorSize.restype = ctypes.c_uint32 - LLVMGetVectorSize.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMVoidTypeInContext = _libraries['llvm'].LLVMVoidTypeInContext - LLVMVoidTypeInContext.restype = LLVMTypeRef - LLVMVoidTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMLabelTypeInContext = _libraries['llvm'].LLVMLabelTypeInContext - LLVMLabelTypeInContext.restype = LLVMTypeRef - LLVMLabelTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMX86MMXTypeInContext = _libraries['llvm'].LLVMX86MMXTypeInContext - LLVMX86MMXTypeInContext.restype = LLVMTypeRef - LLVMX86MMXTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMX86AMXTypeInContext = _libraries['llvm'].LLVMX86AMXTypeInContext - LLVMX86AMXTypeInContext.restype = LLVMTypeRef - LLVMX86AMXTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMTokenTypeInContext = _libraries['llvm'].LLVMTokenTypeInContext - LLVMTokenTypeInContext.restype = LLVMTypeRef - LLVMTokenTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMMetadataTypeInContext = _libraries['llvm'].LLVMMetadataTypeInContext - LLVMMetadataTypeInContext.restype = LLVMTypeRef - LLVMMetadataTypeInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMVoidType = _libraries['llvm'].LLVMVoidType - LLVMVoidType.restype = LLVMTypeRef - LLVMVoidType.argtypes = [] -except AttributeError: - pass -try: - LLVMLabelType = _libraries['llvm'].LLVMLabelType - LLVMLabelType.restype = LLVMTypeRef - LLVMLabelType.argtypes = [] -except AttributeError: - pass -try: - LLVMX86MMXType = _libraries['llvm'].LLVMX86MMXType - LLVMX86MMXType.restype = LLVMTypeRef - LLVMX86MMXType.argtypes = [] -except AttributeError: - pass -try: - LLVMX86AMXType = _libraries['llvm'].LLVMX86AMXType - LLVMX86AMXType.restype = LLVMTypeRef - LLVMX86AMXType.argtypes = [] -except AttributeError: - pass -try: - LLVMTypeOf = _libraries['llvm'].LLVMTypeOf - LLVMTypeOf.restype = LLVMTypeRef - LLVMTypeOf.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetValueKind = _libraries['llvm'].LLVMGetValueKind - LLVMGetValueKind.restype = LLVMValueKind - LLVMGetValueKind.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetValueName2 = _libraries['llvm'].LLVMGetValueName2 - LLVMGetValueName2.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetValueName2.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMSetValueName2 = _libraries['llvm'].LLVMSetValueName2 - LLVMSetValueName2.restype = None - LLVMSetValueName2.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDumpValue = _libraries['llvm'].LLVMDumpValue - LLVMDumpValue.restype = None - LLVMDumpValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMPrintValueToString = _libraries['llvm'].LLVMPrintValueToString - LLVMPrintValueToString.restype = ctypes.POINTER(ctypes.c_char) - LLVMPrintValueToString.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMReplaceAllUsesWith = _libraries['llvm'].LLVMReplaceAllUsesWith - LLVMReplaceAllUsesWith.restype = None - LLVMReplaceAllUsesWith.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsConstant = _libraries['llvm'].LLVMIsConstant - LLVMIsConstant.restype = LLVMBool - LLVMIsConstant.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsUndef = _libraries['llvm'].LLVMIsUndef - LLVMIsUndef.restype = LLVMBool - LLVMIsUndef.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsPoison = _libraries['llvm'].LLVMIsPoison - LLVMIsPoison.restype = LLVMBool - LLVMIsPoison.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAArgument = _libraries['llvm'].LLVMIsAArgument - LLVMIsAArgument.restype = LLVMValueRef - LLVMIsAArgument.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABasicBlock = _libraries['llvm'].LLVMIsABasicBlock - LLVMIsABasicBlock.restype = LLVMValueRef - LLVMIsABasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInlineAsm = _libraries['llvm'].LLVMIsAInlineAsm - LLVMIsAInlineAsm.restype = LLVMValueRef - LLVMIsAInlineAsm.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUser = _libraries['llvm'].LLVMIsAUser - LLVMIsAUser.restype = LLVMValueRef - LLVMIsAUser.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstant = _libraries['llvm'].LLVMIsAConstant - LLVMIsAConstant.restype = LLVMValueRef - LLVMIsAConstant.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABlockAddress = _libraries['llvm'].LLVMIsABlockAddress - LLVMIsABlockAddress.restype = LLVMValueRef - LLVMIsABlockAddress.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantAggregateZero = _libraries['llvm'].LLVMIsAConstantAggregateZero - LLVMIsAConstantAggregateZero.restype = LLVMValueRef - LLVMIsAConstantAggregateZero.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantArray = _libraries['llvm'].LLVMIsAConstantArray - LLVMIsAConstantArray.restype = LLVMValueRef - LLVMIsAConstantArray.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantDataSequential = _libraries['llvm'].LLVMIsAConstantDataSequential - LLVMIsAConstantDataSequential.restype = LLVMValueRef - LLVMIsAConstantDataSequential.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantDataArray = _libraries['llvm'].LLVMIsAConstantDataArray - LLVMIsAConstantDataArray.restype = LLVMValueRef - LLVMIsAConstantDataArray.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantDataVector = _libraries['llvm'].LLVMIsAConstantDataVector - LLVMIsAConstantDataVector.restype = LLVMValueRef - LLVMIsAConstantDataVector.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantExpr = _libraries['llvm'].LLVMIsAConstantExpr - LLVMIsAConstantExpr.restype = LLVMValueRef - LLVMIsAConstantExpr.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantFP = _libraries['llvm'].LLVMIsAConstantFP - LLVMIsAConstantFP.restype = LLVMValueRef - LLVMIsAConstantFP.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantInt = _libraries['llvm'].LLVMIsAConstantInt - LLVMIsAConstantInt.restype = LLVMValueRef - LLVMIsAConstantInt.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantPointerNull = _libraries['llvm'].LLVMIsAConstantPointerNull - LLVMIsAConstantPointerNull.restype = LLVMValueRef - LLVMIsAConstantPointerNull.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantStruct = _libraries['llvm'].LLVMIsAConstantStruct - LLVMIsAConstantStruct.restype = LLVMValueRef - LLVMIsAConstantStruct.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantTokenNone = _libraries['llvm'].LLVMIsAConstantTokenNone - LLVMIsAConstantTokenNone.restype = LLVMValueRef - LLVMIsAConstantTokenNone.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAConstantVector = _libraries['llvm'].LLVMIsAConstantVector - LLVMIsAConstantVector.restype = LLVMValueRef - LLVMIsAConstantVector.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalValue = _libraries['llvm'].LLVMIsAGlobalValue - LLVMIsAGlobalValue.restype = LLVMValueRef - LLVMIsAGlobalValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalAlias = _libraries['llvm'].LLVMIsAGlobalAlias - LLVMIsAGlobalAlias.restype = LLVMValueRef - LLVMIsAGlobalAlias.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalObject = _libraries['llvm'].LLVMIsAGlobalObject - LLVMIsAGlobalObject.restype = LLVMValueRef - LLVMIsAGlobalObject.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFunction = _libraries['llvm'].LLVMIsAFunction - LLVMIsAFunction.restype = LLVMValueRef - LLVMIsAFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalVariable = _libraries['llvm'].LLVMIsAGlobalVariable - LLVMIsAGlobalVariable.restype = LLVMValueRef - LLVMIsAGlobalVariable.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGlobalIFunc = _libraries['llvm'].LLVMIsAGlobalIFunc - LLVMIsAGlobalIFunc.restype = LLVMValueRef - LLVMIsAGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUndefValue = _libraries['llvm'].LLVMIsAUndefValue - LLVMIsAUndefValue.restype = LLVMValueRef - LLVMIsAUndefValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAPoisonValue = _libraries['llvm'].LLVMIsAPoisonValue - LLVMIsAPoisonValue.restype = LLVMValueRef - LLVMIsAPoisonValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInstruction = _libraries['llvm'].LLVMIsAInstruction - LLVMIsAInstruction.restype = LLVMValueRef - LLVMIsAInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUnaryOperator = _libraries['llvm'].LLVMIsAUnaryOperator - LLVMIsAUnaryOperator.restype = LLVMValueRef - LLVMIsAUnaryOperator.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABinaryOperator = _libraries['llvm'].LLVMIsABinaryOperator - LLVMIsABinaryOperator.restype = LLVMValueRef - LLVMIsABinaryOperator.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACallInst = _libraries['llvm'].LLVMIsACallInst - LLVMIsACallInst.restype = LLVMValueRef - LLVMIsACallInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAIntrinsicInst = _libraries['llvm'].LLVMIsAIntrinsicInst - LLVMIsAIntrinsicInst.restype = LLVMValueRef - LLVMIsAIntrinsicInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgInfoIntrinsic = _libraries['llvm'].LLVMIsADbgInfoIntrinsic - LLVMIsADbgInfoIntrinsic.restype = LLVMValueRef - LLVMIsADbgInfoIntrinsic.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgVariableIntrinsic = _libraries['llvm'].LLVMIsADbgVariableIntrinsic - LLVMIsADbgVariableIntrinsic.restype = LLVMValueRef - LLVMIsADbgVariableIntrinsic.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgDeclareInst = _libraries['llvm'].LLVMIsADbgDeclareInst - LLVMIsADbgDeclareInst.restype = LLVMValueRef - LLVMIsADbgDeclareInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsADbgLabelInst = _libraries['llvm'].LLVMIsADbgLabelInst - LLVMIsADbgLabelInst.restype = LLVMValueRef - LLVMIsADbgLabelInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemIntrinsic = _libraries['llvm'].LLVMIsAMemIntrinsic - LLVMIsAMemIntrinsic.restype = LLVMValueRef - LLVMIsAMemIntrinsic.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemCpyInst = _libraries['llvm'].LLVMIsAMemCpyInst - LLVMIsAMemCpyInst.restype = LLVMValueRef - LLVMIsAMemCpyInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemMoveInst = _libraries['llvm'].LLVMIsAMemMoveInst - LLVMIsAMemMoveInst.restype = LLVMValueRef - LLVMIsAMemMoveInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMemSetInst = _libraries['llvm'].LLVMIsAMemSetInst - LLVMIsAMemSetInst.restype = LLVMValueRef - LLVMIsAMemSetInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACmpInst = _libraries['llvm'].LLVMIsACmpInst - LLVMIsACmpInst.restype = LLVMValueRef - LLVMIsACmpInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFCmpInst = _libraries['llvm'].LLVMIsAFCmpInst - LLVMIsAFCmpInst.restype = LLVMValueRef - LLVMIsAFCmpInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAICmpInst = _libraries['llvm'].LLVMIsAICmpInst - LLVMIsAICmpInst.restype = LLVMValueRef - LLVMIsAICmpInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAExtractElementInst = _libraries['llvm'].LLVMIsAExtractElementInst - LLVMIsAExtractElementInst.restype = LLVMValueRef - LLVMIsAExtractElementInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAGetElementPtrInst = _libraries['llvm'].LLVMIsAGetElementPtrInst - LLVMIsAGetElementPtrInst.restype = LLVMValueRef - LLVMIsAGetElementPtrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInsertElementInst = _libraries['llvm'].LLVMIsAInsertElementInst - LLVMIsAInsertElementInst.restype = LLVMValueRef - LLVMIsAInsertElementInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInsertValueInst = _libraries['llvm'].LLVMIsAInsertValueInst - LLVMIsAInsertValueInst.restype = LLVMValueRef - LLVMIsAInsertValueInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsALandingPadInst = _libraries['llvm'].LLVMIsALandingPadInst - LLVMIsALandingPadInst.restype = LLVMValueRef - LLVMIsALandingPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAPHINode = _libraries['llvm'].LLVMIsAPHINode - LLVMIsAPHINode.restype = LLVMValueRef - LLVMIsAPHINode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASelectInst = _libraries['llvm'].LLVMIsASelectInst - LLVMIsASelectInst.restype = LLVMValueRef - LLVMIsASelectInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAShuffleVectorInst = _libraries['llvm'].LLVMIsAShuffleVectorInst - LLVMIsAShuffleVectorInst.restype = LLVMValueRef - LLVMIsAShuffleVectorInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAStoreInst = _libraries['llvm'].LLVMIsAStoreInst - LLVMIsAStoreInst.restype = LLVMValueRef - LLVMIsAStoreInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABranchInst = _libraries['llvm'].LLVMIsABranchInst - LLVMIsABranchInst.restype = LLVMValueRef - LLVMIsABranchInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAIndirectBrInst = _libraries['llvm'].LLVMIsAIndirectBrInst - LLVMIsAIndirectBrInst.restype = LLVMValueRef - LLVMIsAIndirectBrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAInvokeInst = _libraries['llvm'].LLVMIsAInvokeInst - LLVMIsAInvokeInst.restype = LLVMValueRef - LLVMIsAInvokeInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAReturnInst = _libraries['llvm'].LLVMIsAReturnInst - LLVMIsAReturnInst.restype = LLVMValueRef - LLVMIsAReturnInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASwitchInst = _libraries['llvm'].LLVMIsASwitchInst - LLVMIsASwitchInst.restype = LLVMValueRef - LLVMIsASwitchInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUnreachableInst = _libraries['llvm'].LLVMIsAUnreachableInst - LLVMIsAUnreachableInst.restype = LLVMValueRef - LLVMIsAUnreachableInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAResumeInst = _libraries['llvm'].LLVMIsAResumeInst - LLVMIsAResumeInst.restype = LLVMValueRef - LLVMIsAResumeInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACleanupReturnInst = _libraries['llvm'].LLVMIsACleanupReturnInst - LLVMIsACleanupReturnInst.restype = LLVMValueRef - LLVMIsACleanupReturnInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACatchReturnInst = _libraries['llvm'].LLVMIsACatchReturnInst - LLVMIsACatchReturnInst.restype = LLVMValueRef - LLVMIsACatchReturnInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACatchSwitchInst = _libraries['llvm'].LLVMIsACatchSwitchInst - LLVMIsACatchSwitchInst.restype = LLVMValueRef - LLVMIsACatchSwitchInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACallBrInst = _libraries['llvm'].LLVMIsACallBrInst - LLVMIsACallBrInst.restype = LLVMValueRef - LLVMIsACallBrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFuncletPadInst = _libraries['llvm'].LLVMIsAFuncletPadInst - LLVMIsAFuncletPadInst.restype = LLVMValueRef - LLVMIsAFuncletPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACatchPadInst = _libraries['llvm'].LLVMIsACatchPadInst - LLVMIsACatchPadInst.restype = LLVMValueRef - LLVMIsACatchPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACleanupPadInst = _libraries['llvm'].LLVMIsACleanupPadInst - LLVMIsACleanupPadInst.restype = LLVMValueRef - LLVMIsACleanupPadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUnaryInstruction = _libraries['llvm'].LLVMIsAUnaryInstruction - LLVMIsAUnaryInstruction.restype = LLVMValueRef - LLVMIsAUnaryInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAllocaInst = _libraries['llvm'].LLVMIsAAllocaInst - LLVMIsAAllocaInst.restype = LLVMValueRef - LLVMIsAAllocaInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsACastInst = _libraries['llvm'].LLVMIsACastInst - LLVMIsACastInst.restype = LLVMValueRef - LLVMIsACastInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAddrSpaceCastInst = _libraries['llvm'].LLVMIsAAddrSpaceCastInst - LLVMIsAAddrSpaceCastInst.restype = LLVMValueRef - LLVMIsAAddrSpaceCastInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsABitCastInst = _libraries['llvm'].LLVMIsABitCastInst - LLVMIsABitCastInst.restype = LLVMValueRef - LLVMIsABitCastInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPExtInst = _libraries['llvm'].LLVMIsAFPExtInst - LLVMIsAFPExtInst.restype = LLVMValueRef - LLVMIsAFPExtInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPToSIInst = _libraries['llvm'].LLVMIsAFPToSIInst - LLVMIsAFPToSIInst.restype = LLVMValueRef - LLVMIsAFPToSIInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPToUIInst = _libraries['llvm'].LLVMIsAFPToUIInst - LLVMIsAFPToUIInst.restype = LLVMValueRef - LLVMIsAFPToUIInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFPTruncInst = _libraries['llvm'].LLVMIsAFPTruncInst - LLVMIsAFPTruncInst.restype = LLVMValueRef - LLVMIsAFPTruncInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAIntToPtrInst = _libraries['llvm'].LLVMIsAIntToPtrInst - LLVMIsAIntToPtrInst.restype = LLVMValueRef - LLVMIsAIntToPtrInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAPtrToIntInst = _libraries['llvm'].LLVMIsAPtrToIntInst - LLVMIsAPtrToIntInst.restype = LLVMValueRef - LLVMIsAPtrToIntInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASExtInst = _libraries['llvm'].LLVMIsASExtInst - LLVMIsASExtInst.restype = LLVMValueRef - LLVMIsASExtInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsASIToFPInst = _libraries['llvm'].LLVMIsASIToFPInst - LLVMIsASIToFPInst.restype = LLVMValueRef - LLVMIsASIToFPInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsATruncInst = _libraries['llvm'].LLVMIsATruncInst - LLVMIsATruncInst.restype = LLVMValueRef - LLVMIsATruncInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAUIToFPInst = _libraries['llvm'].LLVMIsAUIToFPInst - LLVMIsAUIToFPInst.restype = LLVMValueRef - LLVMIsAUIToFPInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAZExtInst = _libraries['llvm'].LLVMIsAZExtInst - LLVMIsAZExtInst.restype = LLVMValueRef - LLVMIsAZExtInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAExtractValueInst = _libraries['llvm'].LLVMIsAExtractValueInst - LLVMIsAExtractValueInst.restype = LLVMValueRef - LLVMIsAExtractValueInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsALoadInst = _libraries['llvm'].LLVMIsALoadInst - LLVMIsALoadInst.restype = LLVMValueRef - LLVMIsALoadInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAVAArgInst = _libraries['llvm'].LLVMIsAVAArgInst - LLVMIsAVAArgInst.restype = LLVMValueRef - LLVMIsAVAArgInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFreezeInst = _libraries['llvm'].LLVMIsAFreezeInst - LLVMIsAFreezeInst.restype = LLVMValueRef - LLVMIsAFreezeInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAtomicCmpXchgInst = _libraries['llvm'].LLVMIsAAtomicCmpXchgInst - LLVMIsAAtomicCmpXchgInst.restype = LLVMValueRef - LLVMIsAAtomicCmpXchgInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAAtomicRMWInst = _libraries['llvm'].LLVMIsAAtomicRMWInst - LLVMIsAAtomicRMWInst.restype = LLVMValueRef - LLVMIsAAtomicRMWInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAFenceInst = _libraries['llvm'].LLVMIsAFenceInst - LLVMIsAFenceInst.restype = LLVMValueRef - LLVMIsAFenceInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMDNode = _libraries['llvm'].LLVMIsAMDNode - LLVMIsAMDNode.restype = LLVMValueRef - LLVMIsAMDNode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsAMDString = _libraries['llvm'].LLVMIsAMDString - LLVMIsAMDString.restype = LLVMValueRef - LLVMIsAMDString.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetValueName = _libraries['llvm'].LLVMGetValueName - LLVMGetValueName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetValueName.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetValueName = _libraries['llvm'].LLVMSetValueName - LLVMSetValueName.restype = None - LLVMSetValueName.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstUse = _libraries['llvm'].LLVMGetFirstUse - LLVMGetFirstUse.restype = LLVMUseRef - LLVMGetFirstUse.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextUse = _libraries['llvm'].LLVMGetNextUse - LLVMGetNextUse.restype = LLVMUseRef - LLVMGetNextUse.argtypes = [LLVMUseRef] -except AttributeError: - pass -try: - LLVMGetUser = _libraries['llvm'].LLVMGetUser - LLVMGetUser.restype = LLVMValueRef - LLVMGetUser.argtypes = [LLVMUseRef] -except AttributeError: - pass -try: - LLVMGetUsedValue = _libraries['llvm'].LLVMGetUsedValue - LLVMGetUsedValue.restype = LLVMValueRef - LLVMGetUsedValue.argtypes = [LLVMUseRef] -except AttributeError: - pass -try: - LLVMGetOperand = _libraries['llvm'].LLVMGetOperand - LLVMGetOperand.restype = LLVMValueRef - LLVMGetOperand.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetOperandUse = _libraries['llvm'].LLVMGetOperandUse - LLVMGetOperandUse.restype = LLVMUseRef - LLVMGetOperandUse.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetOperand = _libraries['llvm'].LLVMSetOperand - LLVMSetOperand.restype = None - LLVMSetOperand.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNumOperands = _libraries['llvm'].LLVMGetNumOperands - LLVMGetNumOperands.restype = ctypes.c_int32 - LLVMGetNumOperands.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNull = _libraries['llvm'].LLVMConstNull - LLVMConstNull.restype = LLVMValueRef - LLVMConstNull.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstAllOnes = _libraries['llvm'].LLVMConstAllOnes - LLVMConstAllOnes.restype = LLVMValueRef - LLVMConstAllOnes.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetUndef = _libraries['llvm'].LLVMGetUndef - LLVMGetUndef.restype = LLVMValueRef - LLVMGetUndef.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMGetPoison = _libraries['llvm'].LLVMGetPoison - LLVMGetPoison.restype = LLVMValueRef - LLVMGetPoison.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMIsNull = _libraries['llvm'].LLVMIsNull - LLVMIsNull.restype = LLVMBool - LLVMIsNull.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstPointerNull = _libraries['llvm'].LLVMConstPointerNull - LLVMConstPointerNull.restype = LLVMValueRef - LLVMConstPointerNull.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstInt = _libraries['llvm'].LLVMConstInt - LLVMConstInt.restype = LLVMValueRef - LLVMConstInt.argtypes = [LLVMTypeRef, ctypes.c_uint64, LLVMBool] -except AttributeError: - pass -try: - LLVMConstIntOfArbitraryPrecision = _libraries['llvm'].LLVMConstIntOfArbitraryPrecision - LLVMConstIntOfArbitraryPrecision.restype = LLVMValueRef - LLVMConstIntOfArbitraryPrecision.argtypes = [LLVMTypeRef, ctypes.c_uint32, ctypes.c_uint64 * 0] -except AttributeError: - pass -uint8_t = ctypes.c_uint8 -try: - LLVMConstIntOfString = _libraries['llvm'].LLVMConstIntOfString - LLVMConstIntOfString.restype = LLVMValueRef - LLVMConstIntOfString.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), uint8_t] -except AttributeError: - pass -try: - LLVMConstIntOfStringAndSize = _libraries['llvm'].LLVMConstIntOfStringAndSize - LLVMConstIntOfStringAndSize.restype = LLVMValueRef - LLVMConstIntOfStringAndSize.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, uint8_t] -except AttributeError: - pass -try: - LLVMConstReal = _libraries['llvm'].LLVMConstReal - LLVMConstReal.restype = LLVMValueRef - LLVMConstReal.argtypes = [LLVMTypeRef, ctypes.c_double] -except AttributeError: - pass -try: - LLVMConstRealOfString = _libraries['llvm'].LLVMConstRealOfString - LLVMConstRealOfString.restype = LLVMValueRef - LLVMConstRealOfString.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMConstRealOfStringAndSize = _libraries['llvm'].LLVMConstRealOfStringAndSize - LLVMConstRealOfStringAndSize.restype = LLVMValueRef - LLVMConstRealOfStringAndSize.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstIntGetZExtValue = _libraries['llvm'].LLVMConstIntGetZExtValue - LLVMConstIntGetZExtValue.restype = ctypes.c_uint64 - LLVMConstIntGetZExtValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstIntGetSExtValue = _libraries['llvm'].LLVMConstIntGetSExtValue - LLVMConstIntGetSExtValue.restype = ctypes.c_int64 - LLVMConstIntGetSExtValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstRealGetDouble = _libraries['llvm'].LLVMConstRealGetDouble - LLVMConstRealGetDouble.restype = ctypes.c_double - LLVMConstRealGetDouble.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - LLVMConstStringInContext = _libraries['llvm'].LLVMConstStringInContext - LLVMConstStringInContext.restype = LLVMValueRef - LLVMConstStringInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMConstString = _libraries['llvm'].LLVMConstString - LLVMConstString.restype = LLVMValueRef - LLVMConstString.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMIsConstantString = _libraries['llvm'].LLVMIsConstantString - LLVMIsConstantString.restype = LLVMBool - LLVMIsConstantString.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetAsString = _libraries['llvm'].LLVMGetAsString - LLVMGetAsString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetAsString.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMConstStructInContext = _libraries['llvm'].LLVMConstStructInContext - LLVMConstStructInContext.restype = LLVMValueRef - LLVMConstStructInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMConstStruct = _libraries['llvm'].LLVMConstStruct - LLVMConstStruct.restype = LLVMValueRef - LLVMConstStruct.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBool] -except AttributeError: - pass -try: - LLVMConstArray = _libraries['llvm'].LLVMConstArray - LLVMConstArray.restype = LLVMValueRef - LLVMConstArray.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstNamedStruct = _libraries['llvm'].LLVMConstNamedStruct - LLVMConstNamedStruct.restype = LLVMValueRef - LLVMConstNamedStruct.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetElementAsConstant = _libraries['llvm'].LLVMGetElementAsConstant - LLVMGetElementAsConstant.restype = LLVMValueRef - LLVMGetElementAsConstant.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstVector = _libraries['llvm'].LLVMConstVector - LLVMConstVector.restype = LLVMValueRef - LLVMConstVector.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetConstOpcode = _libraries['llvm'].LLVMGetConstOpcode - LLVMGetConstOpcode.restype = LLVMOpcode - LLVMGetConstOpcode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAlignOf = _libraries['llvm'].LLVMAlignOf - LLVMAlignOf.restype = LLVMValueRef - LLVMAlignOf.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMSizeOf = _libraries['llvm'].LLVMSizeOf - LLVMSizeOf.restype = LLVMValueRef - LLVMSizeOf.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstNeg = _libraries['llvm'].LLVMConstNeg - LLVMConstNeg.restype = LLVMValueRef - LLVMConstNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWNeg = _libraries['llvm'].LLVMConstNSWNeg - LLVMConstNSWNeg.restype = LLVMValueRef - LLVMConstNSWNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWNeg = _libraries['llvm'].LLVMConstNUWNeg - LLVMConstNUWNeg.restype = LLVMValueRef - LLVMConstNUWNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFNeg = _libraries['llvm'].LLVMConstFNeg - LLVMConstFNeg.restype = LLVMValueRef - LLVMConstFNeg.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNot = _libraries['llvm'].LLVMConstNot - LLVMConstNot.restype = LLVMValueRef - LLVMConstNot.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstAdd = _libraries['llvm'].LLVMConstAdd - LLVMConstAdd.restype = LLVMValueRef - LLVMConstAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWAdd = _libraries['llvm'].LLVMConstNSWAdd - LLVMConstNSWAdd.restype = LLVMValueRef - LLVMConstNSWAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWAdd = _libraries['llvm'].LLVMConstNUWAdd - LLVMConstNUWAdd.restype = LLVMValueRef - LLVMConstNUWAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFAdd = _libraries['llvm'].LLVMConstFAdd - LLVMConstFAdd.restype = LLVMValueRef - LLVMConstFAdd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstSub = _libraries['llvm'].LLVMConstSub - LLVMConstSub.restype = LLVMValueRef - LLVMConstSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWSub = _libraries['llvm'].LLVMConstNSWSub - LLVMConstNSWSub.restype = LLVMValueRef - LLVMConstNSWSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWSub = _libraries['llvm'].LLVMConstNUWSub - LLVMConstNUWSub.restype = LLVMValueRef - LLVMConstNUWSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFSub = _libraries['llvm'].LLVMConstFSub - LLVMConstFSub.restype = LLVMValueRef - LLVMConstFSub.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstMul = _libraries['llvm'].LLVMConstMul - LLVMConstMul.restype = LLVMValueRef - LLVMConstMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNSWMul = _libraries['llvm'].LLVMConstNSWMul - LLVMConstNSWMul.restype = LLVMValueRef - LLVMConstNSWMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstNUWMul = _libraries['llvm'].LLVMConstNUWMul - LLVMConstNUWMul.restype = LLVMValueRef - LLVMConstNUWMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFMul = _libraries['llvm'].LLVMConstFMul - LLVMConstFMul.restype = LLVMValueRef - LLVMConstFMul.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstUDiv = _libraries['llvm'].LLVMConstUDiv - LLVMConstUDiv.restype = LLVMValueRef - LLVMConstUDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExactUDiv = _libraries['llvm'].LLVMConstExactUDiv - LLVMConstExactUDiv.restype = LLVMValueRef - LLVMConstExactUDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstSDiv = _libraries['llvm'].LLVMConstSDiv - LLVMConstSDiv.restype = LLVMValueRef - LLVMConstSDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExactSDiv = _libraries['llvm'].LLVMConstExactSDiv - LLVMConstExactSDiv.restype = LLVMValueRef - LLVMConstExactSDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFDiv = _libraries['llvm'].LLVMConstFDiv - LLVMConstFDiv.restype = LLVMValueRef - LLVMConstFDiv.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstURem = _libraries['llvm'].LLVMConstURem - LLVMConstURem.restype = LLVMValueRef - LLVMConstURem.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstSRem = _libraries['llvm'].LLVMConstSRem - LLVMConstSRem.restype = LLVMValueRef - LLVMConstSRem.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFRem = _libraries['llvm'].LLVMConstFRem - LLVMConstFRem.restype = LLVMValueRef - LLVMConstFRem.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstAnd = _libraries['llvm'].LLVMConstAnd - LLVMConstAnd.restype = LLVMValueRef - LLVMConstAnd.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstOr = _libraries['llvm'].LLVMConstOr - LLVMConstOr.restype = LLVMValueRef - LLVMConstOr.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstXor = _libraries['llvm'].LLVMConstXor - LLVMConstXor.restype = LLVMValueRef - LLVMConstXor.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstICmp = _libraries['llvm'].LLVMConstICmp - LLVMConstICmp.restype = LLVMValueRef - LLVMConstICmp.argtypes = [LLVMIntPredicate, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstFCmp = _libraries['llvm'].LLVMConstFCmp - LLVMConstFCmp.restype = LLVMValueRef - LLVMConstFCmp.argtypes = [LLVMRealPredicate, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstShl = _libraries['llvm'].LLVMConstShl - LLVMConstShl.restype = LLVMValueRef - LLVMConstShl.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstLShr = _libraries['llvm'].LLVMConstLShr - LLVMConstLShr.restype = LLVMValueRef - LLVMConstLShr.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstAShr = _libraries['llvm'].LLVMConstAShr - LLVMConstAShr.restype = LLVMValueRef - LLVMConstAShr.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstGEP = _libraries['llvm'].LLVMConstGEP - LLVMConstGEP.restype = LLVMValueRef - LLVMConstGEP.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstGEP2 = _libraries['llvm'].LLVMConstGEP2 - LLVMConstGEP2.restype = LLVMValueRef - LLVMConstGEP2.argtypes = [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstInBoundsGEP = _libraries['llvm'].LLVMConstInBoundsGEP - LLVMConstInBoundsGEP.restype = LLVMValueRef - LLVMConstInBoundsGEP.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstInBoundsGEP2 = _libraries['llvm'].LLVMConstInBoundsGEP2 - LLVMConstInBoundsGEP2.restype = LLVMValueRef - LLVMConstInBoundsGEP2.argtypes = [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstTrunc = _libraries['llvm'].LLVMConstTrunc - LLVMConstTrunc.restype = LLVMValueRef - LLVMConstTrunc.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSExt = _libraries['llvm'].LLVMConstSExt - LLVMConstSExt.restype = LLVMValueRef - LLVMConstSExt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstZExt = _libraries['llvm'].LLVMConstZExt - LLVMConstZExt.restype = LLVMValueRef - LLVMConstZExt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPTrunc = _libraries['llvm'].LLVMConstFPTrunc - LLVMConstFPTrunc.restype = LLVMValueRef - LLVMConstFPTrunc.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPExt = _libraries['llvm'].LLVMConstFPExt - LLVMConstFPExt.restype = LLVMValueRef - LLVMConstFPExt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstUIToFP = _libraries['llvm'].LLVMConstUIToFP - LLVMConstUIToFP.restype = LLVMValueRef - LLVMConstUIToFP.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSIToFP = _libraries['llvm'].LLVMConstSIToFP - LLVMConstSIToFP.restype = LLVMValueRef - LLVMConstSIToFP.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPToUI = _libraries['llvm'].LLVMConstFPToUI - LLVMConstFPToUI.restype = LLVMValueRef - LLVMConstFPToUI.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstFPToSI = _libraries['llvm'].LLVMConstFPToSI - LLVMConstFPToSI.restype = LLVMValueRef - LLVMConstFPToSI.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstPtrToInt = _libraries['llvm'].LLVMConstPtrToInt - LLVMConstPtrToInt.restype = LLVMValueRef - LLVMConstPtrToInt.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstIntToPtr = _libraries['llvm'].LLVMConstIntToPtr - LLVMConstIntToPtr.restype = LLVMValueRef - LLVMConstIntToPtr.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstBitCast = _libraries['llvm'].LLVMConstBitCast - LLVMConstBitCast.restype = LLVMValueRef - LLVMConstBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstAddrSpaceCast = _libraries['llvm'].LLVMConstAddrSpaceCast - LLVMConstAddrSpaceCast.restype = LLVMValueRef - LLVMConstAddrSpaceCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstZExtOrBitCast = _libraries['llvm'].LLVMConstZExtOrBitCast - LLVMConstZExtOrBitCast.restype = LLVMValueRef - LLVMConstZExtOrBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSExtOrBitCast = _libraries['llvm'].LLVMConstSExtOrBitCast - LLVMConstSExtOrBitCast.restype = LLVMValueRef - LLVMConstSExtOrBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstTruncOrBitCast = _libraries['llvm'].LLVMConstTruncOrBitCast - LLVMConstTruncOrBitCast.restype = LLVMValueRef - LLVMConstTruncOrBitCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstPointerCast = _libraries['llvm'].LLVMConstPointerCast - LLVMConstPointerCast.restype = LLVMValueRef - LLVMConstPointerCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstIntCast = _libraries['llvm'].LLVMConstIntCast - LLVMConstIntCast.restype = LLVMValueRef - LLVMConstIntCast.argtypes = [LLVMValueRef, LLVMTypeRef, LLVMBool] -except AttributeError: - pass -try: - LLVMConstFPCast = _libraries['llvm'].LLVMConstFPCast - LLVMConstFPCast.restype = LLVMValueRef - LLVMConstFPCast.argtypes = [LLVMValueRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMConstSelect = _libraries['llvm'].LLVMConstSelect - LLVMConstSelect.restype = LLVMValueRef - LLVMConstSelect.argtypes = [LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExtractElement = _libraries['llvm'].LLVMConstExtractElement - LLVMConstExtractElement.restype = LLVMValueRef - LLVMConstExtractElement.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstInsertElement = _libraries['llvm'].LLVMConstInsertElement - LLVMConstInsertElement.restype = LLVMValueRef - LLVMConstInsertElement.argtypes = [LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstShuffleVector = _libraries['llvm'].LLVMConstShuffleVector - LLVMConstShuffleVector.restype = LLVMValueRef - LLVMConstShuffleVector.argtypes = [LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMConstExtractValue = _libraries['llvm'].LLVMConstExtractValue - LLVMConstExtractValue.restype = LLVMValueRef - LLVMConstExtractValue.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMConstInsertValue = _libraries['llvm'].LLVMConstInsertValue - LLVMConstInsertValue.restype = LLVMValueRef - LLVMConstInsertValue.argtypes = [LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBlockAddress = _libraries['llvm'].LLVMBlockAddress - LLVMBlockAddress.restype = LLVMValueRef - LLVMBlockAddress.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMConstInlineAsm = _libraries['llvm'].LLVMConstInlineAsm - LLVMConstInlineAsm.restype = LLVMValueRef - LLVMConstInlineAsm.argtypes = [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMBool, LLVMBool] -except AttributeError: - pass -try: - LLVMGetGlobalParent = _libraries['llvm'].LLVMGetGlobalParent - LLVMGetGlobalParent.restype = LLVMModuleRef - LLVMGetGlobalParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsDeclaration = _libraries['llvm'].LLVMIsDeclaration - LLVMIsDeclaration.restype = LLVMBool - LLVMIsDeclaration.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetLinkage = _libraries['llvm'].LLVMGetLinkage - LLVMGetLinkage.restype = LLVMLinkage - LLVMGetLinkage.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetLinkage = _libraries['llvm'].LLVMSetLinkage - LLVMSetLinkage.restype = None - LLVMSetLinkage.argtypes = [LLVMValueRef, LLVMLinkage] -except AttributeError: - pass -try: - LLVMGetSection = _libraries['llvm'].LLVMGetSection - LLVMGetSection.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSection.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetSection = _libraries['llvm'].LLVMSetSection - LLVMSetSection.restype = None - LLVMSetSection.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetVisibility = _libraries['llvm'].LLVMGetVisibility - LLVMGetVisibility.restype = LLVMVisibility - LLVMGetVisibility.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetVisibility = _libraries['llvm'].LLVMSetVisibility - LLVMSetVisibility.restype = None - LLVMSetVisibility.argtypes = [LLVMValueRef, LLVMVisibility] -except AttributeError: - pass -try: - LLVMGetDLLStorageClass = _libraries['llvm'].LLVMGetDLLStorageClass - LLVMGetDLLStorageClass.restype = LLVMDLLStorageClass - LLVMGetDLLStorageClass.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetDLLStorageClass = _libraries['llvm'].LLVMSetDLLStorageClass - LLVMSetDLLStorageClass.restype = None - LLVMSetDLLStorageClass.argtypes = [LLVMValueRef, LLVMDLLStorageClass] -except AttributeError: - pass -try: - LLVMGetUnnamedAddress = _libraries['llvm'].LLVMGetUnnamedAddress - LLVMGetUnnamedAddress.restype = LLVMUnnamedAddr - LLVMGetUnnamedAddress.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetUnnamedAddress = _libraries['llvm'].LLVMSetUnnamedAddress - LLVMSetUnnamedAddress.restype = None - LLVMSetUnnamedAddress.argtypes = [LLVMValueRef, LLVMUnnamedAddr] -except AttributeError: - pass -try: - LLVMGlobalGetValueType = _libraries['llvm'].LLVMGlobalGetValueType - LLVMGlobalGetValueType.restype = LLVMTypeRef - LLVMGlobalGetValueType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMHasUnnamedAddr = _libraries['llvm'].LLVMHasUnnamedAddr - LLVMHasUnnamedAddr.restype = LLVMBool - LLVMHasUnnamedAddr.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetUnnamedAddr = _libraries['llvm'].LLVMSetUnnamedAddr - LLVMSetUnnamedAddr.restype = None - LLVMSetUnnamedAddr.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetAlignment = _libraries['llvm'].LLVMGetAlignment - LLVMGetAlignment.restype = ctypes.c_uint32 - LLVMGetAlignment.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetAlignment = _libraries['llvm'].LLVMSetAlignment - LLVMSetAlignment.restype = None - LLVMSetAlignment.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGlobalSetMetadata = _libraries['llvm'].LLVMGlobalSetMetadata - LLVMGlobalSetMetadata.restype = None - LLVMGlobalSetMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMGlobalEraseMetadata = _libraries['llvm'].LLVMGlobalEraseMetadata - LLVMGlobalEraseMetadata.restype = None - LLVMGlobalEraseMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGlobalClearMetadata = _libraries['llvm'].LLVMGlobalClearMetadata - LLVMGlobalClearMetadata.restype = None - LLVMGlobalClearMetadata.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGlobalCopyAllMetadata = _libraries['llvm'].LLVMGlobalCopyAllMetadata - LLVMGlobalCopyAllMetadata.restype = ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry) - LLVMGlobalCopyAllMetadata.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMDisposeValueMetadataEntries = _libraries['llvm'].LLVMDisposeValueMetadataEntries - LLVMDisposeValueMetadataEntries.restype = None - LLVMDisposeValueMetadataEntries.argtypes = [ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry)] -except AttributeError: - pass -try: - LLVMValueMetadataEntriesGetKind = _libraries['llvm'].LLVMValueMetadataEntriesGetKind - LLVMValueMetadataEntriesGetKind.restype = ctypes.c_uint32 - LLVMValueMetadataEntriesGetKind.argtypes = [ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMValueMetadataEntriesGetMetadata = _libraries['llvm'].LLVMValueMetadataEntriesGetMetadata - LLVMValueMetadataEntriesGetMetadata.restype = LLVMMetadataRef - LLVMValueMetadataEntriesGetMetadata.argtypes = [ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddGlobal = _libraries['llvm'].LLVMAddGlobal - LLVMAddGlobal.restype = LLVMValueRef - LLVMAddGlobal.argtypes = [LLVMModuleRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddGlobalInAddressSpace = _libraries['llvm'].LLVMAddGlobalInAddressSpace - LLVMAddGlobalInAddressSpace.restype = LLVMValueRef - LLVMAddGlobalInAddressSpace.argtypes = [LLVMModuleRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetNamedGlobal = _libraries['llvm'].LLVMGetNamedGlobal - LLVMGetNamedGlobal.restype = LLVMValueRef - LLVMGetNamedGlobal.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFirstGlobal = _libraries['llvm'].LLVMGetFirstGlobal - LLVMGetFirstGlobal.restype = LLVMValueRef - LLVMGetFirstGlobal.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastGlobal = _libraries['llvm'].LLVMGetLastGlobal - LLVMGetLastGlobal.restype = LLVMValueRef - LLVMGetLastGlobal.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextGlobal = _libraries['llvm'].LLVMGetNextGlobal - LLVMGetNextGlobal.restype = LLVMValueRef - LLVMGetNextGlobal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousGlobal = _libraries['llvm'].LLVMGetPreviousGlobal - LLVMGetPreviousGlobal.restype = LLVMValueRef - LLVMGetPreviousGlobal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMDeleteGlobal = _libraries['llvm'].LLVMDeleteGlobal - LLVMDeleteGlobal.restype = None - LLVMDeleteGlobal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetInitializer = _libraries['llvm'].LLVMGetInitializer - LLVMGetInitializer.restype = LLVMValueRef - LLVMGetInitializer.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetInitializer = _libraries['llvm'].LLVMSetInitializer - LLVMSetInitializer.restype = None - LLVMSetInitializer.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsThreadLocal = _libraries['llvm'].LLVMIsThreadLocal - LLVMIsThreadLocal.restype = LLVMBool - LLVMIsThreadLocal.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetThreadLocal = _libraries['llvm'].LLVMSetThreadLocal - LLVMSetThreadLocal.restype = None - LLVMSetThreadLocal.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMIsGlobalConstant = _libraries['llvm'].LLVMIsGlobalConstant - LLVMIsGlobalConstant.restype = LLVMBool - LLVMIsGlobalConstant.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetGlobalConstant = _libraries['llvm'].LLVMSetGlobalConstant - LLVMSetGlobalConstant.restype = None - LLVMSetGlobalConstant.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetThreadLocalMode = _libraries['llvm'].LLVMGetThreadLocalMode - LLVMGetThreadLocalMode.restype = LLVMThreadLocalMode - LLVMGetThreadLocalMode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetThreadLocalMode = _libraries['llvm'].LLVMSetThreadLocalMode - LLVMSetThreadLocalMode.restype = None - LLVMSetThreadLocalMode.argtypes = [LLVMValueRef, LLVMThreadLocalMode] -except AttributeError: - pass -try: - LLVMIsExternallyInitialized = _libraries['llvm'].LLVMIsExternallyInitialized - LLVMIsExternallyInitialized.restype = LLVMBool - LLVMIsExternallyInitialized.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetExternallyInitialized = _libraries['llvm'].LLVMSetExternallyInitialized - LLVMSetExternallyInitialized.restype = None - LLVMSetExternallyInitialized.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMAddAlias = _libraries['llvm'].LLVMAddAlias - LLVMAddAlias.restype = LLVMValueRef - LLVMAddAlias.argtypes = [LLVMModuleRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddAlias2 = _libraries['llvm'].LLVMAddAlias2 - LLVMAddAlias2.restype = LLVMValueRef - LLVMAddAlias2.argtypes = [LLVMModuleRef, LLVMTypeRef, ctypes.c_uint32, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetNamedGlobalAlias = _libraries['llvm'].LLVMGetNamedGlobalAlias - LLVMGetNamedGlobalAlias.restype = LLVMValueRef - LLVMGetNamedGlobalAlias.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetFirstGlobalAlias = _libraries['llvm'].LLVMGetFirstGlobalAlias - LLVMGetFirstGlobalAlias.restype = LLVMValueRef - LLVMGetFirstGlobalAlias.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastGlobalAlias = _libraries['llvm'].LLVMGetLastGlobalAlias - LLVMGetLastGlobalAlias.restype = LLVMValueRef - LLVMGetLastGlobalAlias.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextGlobalAlias = _libraries['llvm'].LLVMGetNextGlobalAlias - LLVMGetNextGlobalAlias.restype = LLVMValueRef - LLVMGetNextGlobalAlias.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousGlobalAlias = _libraries['llvm'].LLVMGetPreviousGlobalAlias - LLVMGetPreviousGlobalAlias.restype = LLVMValueRef - LLVMGetPreviousGlobalAlias.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAliasGetAliasee = _libraries['llvm'].LLVMAliasGetAliasee - LLVMAliasGetAliasee.restype = LLVMValueRef - LLVMAliasGetAliasee.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAliasSetAliasee = _libraries['llvm'].LLVMAliasSetAliasee - LLVMAliasSetAliasee.restype = None - LLVMAliasSetAliasee.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMDeleteFunction = _libraries['llvm'].LLVMDeleteFunction - LLVMDeleteFunction.restype = None - LLVMDeleteFunction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMHasPersonalityFn = _libraries['llvm'].LLVMHasPersonalityFn - LLVMHasPersonalityFn.restype = LLVMBool - LLVMHasPersonalityFn.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPersonalityFn = _libraries['llvm'].LLVMGetPersonalityFn - LLVMGetPersonalityFn.restype = LLVMValueRef - LLVMGetPersonalityFn.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetPersonalityFn = _libraries['llvm'].LLVMSetPersonalityFn - LLVMSetPersonalityFn.restype = None - LLVMSetPersonalityFn.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMLookupIntrinsicID = _libraries['llvm'].LLVMLookupIntrinsicID - LLVMLookupIntrinsicID.restype = ctypes.c_uint32 - LLVMLookupIntrinsicID.argtypes = [ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetIntrinsicID = _libraries['llvm'].LLVMGetIntrinsicID - LLVMGetIntrinsicID.restype = ctypes.c_uint32 - LLVMGetIntrinsicID.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetIntrinsicDeclaration = _libraries['llvm'].LLVMGetIntrinsicDeclaration - LLVMGetIntrinsicDeclaration.restype = LLVMValueRef - LLVMGetIntrinsicDeclaration.argtypes = [LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t] -except AttributeError: - pass -try: - LLVMIntrinsicGetType = _libraries['llvm'].LLVMIntrinsicGetType - LLVMIntrinsicGetType.restype = LLVMTypeRef - LLVMIntrinsicGetType.argtypes = [LLVMContextRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t] -except AttributeError: - pass -try: - LLVMIntrinsicGetName = _libraries['llvm'].LLVMIntrinsicGetName - LLVMIntrinsicGetName.restype = ctypes.POINTER(ctypes.c_char) - LLVMIntrinsicGetName.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMIntrinsicCopyOverloadedName = _libraries['llvm'].LLVMIntrinsicCopyOverloadedName - LLVMIntrinsicCopyOverloadedName.restype = ctypes.POINTER(ctypes.c_char) - LLVMIntrinsicCopyOverloadedName.argtypes = [ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMIntrinsicCopyOverloadedName2 = _libraries['llvm'].LLVMIntrinsicCopyOverloadedName2 - LLVMIntrinsicCopyOverloadedName2.restype = ctypes.POINTER(ctypes.c_char) - LLVMIntrinsicCopyOverloadedName2.argtypes = [LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMIntrinsicIsOverloaded = _libraries['llvm'].LLVMIntrinsicIsOverloaded - LLVMIntrinsicIsOverloaded.restype = LLVMBool - LLVMIntrinsicIsOverloaded.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetFunctionCallConv = _libraries['llvm'].LLVMGetFunctionCallConv - LLVMGetFunctionCallConv.restype = ctypes.c_uint32 - LLVMGetFunctionCallConv.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetFunctionCallConv = _libraries['llvm'].LLVMSetFunctionCallConv - LLVMSetFunctionCallConv.restype = None - LLVMSetFunctionCallConv.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetGC = _libraries['llvm'].LLVMGetGC - LLVMGetGC.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetGC.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetGC = _libraries['llvm'].LLVMSetGC - LLVMSetGC.restype = None - LLVMSetGC.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddAttributeAtIndex = _libraries['llvm'].LLVMAddAttributeAtIndex - LLVMAddAttributeAtIndex.restype = None - LLVMAddAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetAttributeCountAtIndex = _libraries['llvm'].LLVMGetAttributeCountAtIndex - LLVMGetAttributeCountAtIndex.restype = ctypes.c_uint32 - LLVMGetAttributeCountAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex] -except AttributeError: - pass -try: - LLVMGetAttributesAtIndex = _libraries['llvm'].LLVMGetAttributesAtIndex - LLVMGetAttributesAtIndex.restype = None - LLVMGetAttributesAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueAttributeRef))] -except AttributeError: - pass -try: - LLVMGetEnumAttributeAtIndex = _libraries['llvm'].LLVMGetEnumAttributeAtIndex - LLVMGetEnumAttributeAtIndex.restype = LLVMAttributeRef - LLVMGetEnumAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetStringAttributeAtIndex = _libraries['llvm'].LLVMGetStringAttributeAtIndex - LLVMGetStringAttributeAtIndex.restype = LLVMAttributeRef - LLVMGetStringAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveEnumAttributeAtIndex = _libraries['llvm'].LLVMRemoveEnumAttributeAtIndex - LLVMRemoveEnumAttributeAtIndex.restype = None - LLVMRemoveEnumAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveStringAttributeAtIndex = _libraries['llvm'].LLVMRemoveStringAttributeAtIndex - LLVMRemoveStringAttributeAtIndex.restype = None - LLVMRemoveStringAttributeAtIndex.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddTargetDependentFunctionAttr = _libraries['llvm'].LLVMAddTargetDependentFunctionAttr - LLVMAddTargetDependentFunctionAttr.restype = None - LLVMAddTargetDependentFunctionAttr.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMCountParams = _libraries['llvm'].LLVMCountParams - LLVMCountParams.restype = ctypes.c_uint32 - LLVMCountParams.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetParams = _libraries['llvm'].LLVMGetParams - LLVMGetParams.restype = None - LLVMGetParams.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMGetParam = _libraries['llvm'].LLVMGetParam - LLVMGetParam.restype = LLVMValueRef - LLVMGetParam.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetParamParent = _libraries['llvm'].LLVMGetParamParent - LLVMGetParamParent.restype = LLVMValueRef - LLVMGetParamParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetFirstParam = _libraries['llvm'].LLVMGetFirstParam - LLVMGetFirstParam.restype = LLVMValueRef - LLVMGetFirstParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetLastParam = _libraries['llvm'].LLVMGetLastParam - LLVMGetLastParam.restype = LLVMValueRef - LLVMGetLastParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextParam = _libraries['llvm'].LLVMGetNextParam - LLVMGetNextParam.restype = LLVMValueRef - LLVMGetNextParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousParam = _libraries['llvm'].LLVMGetPreviousParam - LLVMGetPreviousParam.restype = LLVMValueRef - LLVMGetPreviousParam.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetParamAlignment = _libraries['llvm'].LLVMSetParamAlignment - LLVMSetParamAlignment.restype = None - LLVMSetParamAlignment.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddGlobalIFunc = _libraries['llvm'].LLVMAddGlobalIFunc - LLVMAddGlobalIFunc.restype = LLVMValueRef - LLVMAddGlobalIFunc.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMTypeRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNamedGlobalIFunc = _libraries['llvm'].LLVMGetNamedGlobalIFunc - LLVMGetNamedGlobalIFunc.restype = LLVMValueRef - LLVMGetNamedGlobalIFunc.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMGetFirstGlobalIFunc = _libraries['llvm'].LLVMGetFirstGlobalIFunc - LLVMGetFirstGlobalIFunc.restype = LLVMValueRef - LLVMGetFirstGlobalIFunc.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetLastGlobalIFunc = _libraries['llvm'].LLVMGetLastGlobalIFunc - LLVMGetLastGlobalIFunc.restype = LLVMValueRef - LLVMGetLastGlobalIFunc.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMGetNextGlobalIFunc = _libraries['llvm'].LLVMGetNextGlobalIFunc - LLVMGetNextGlobalIFunc.restype = LLVMValueRef - LLVMGetNextGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousGlobalIFunc = _libraries['llvm'].LLVMGetPreviousGlobalIFunc - LLVMGetPreviousGlobalIFunc.restype = LLVMValueRef - LLVMGetPreviousGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetGlobalIFuncResolver = _libraries['llvm'].LLVMGetGlobalIFuncResolver - LLVMGetGlobalIFuncResolver.restype = LLVMValueRef - LLVMGetGlobalIFuncResolver.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetGlobalIFuncResolver = _libraries['llvm'].LLVMSetGlobalIFuncResolver - LLVMSetGlobalIFuncResolver.restype = None - LLVMSetGlobalIFuncResolver.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMEraseGlobalIFunc = _libraries['llvm'].LLVMEraseGlobalIFunc - LLVMEraseGlobalIFunc.restype = None - LLVMEraseGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMRemoveGlobalIFunc = _libraries['llvm'].LLVMRemoveGlobalIFunc - LLVMRemoveGlobalIFunc.restype = None - LLVMRemoveGlobalIFunc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMMDStringInContext2 = _libraries['llvm'].LLVMMDStringInContext2 - LLVMMDStringInContext2.restype = LLVMMetadataRef - LLVMMDStringInContext2.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMMDNodeInContext2 = _libraries['llvm'].LLVMMDNodeInContext2 - LLVMMDNodeInContext2.restype = LLVMMetadataRef - LLVMMDNodeInContext2.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMMetadataAsValue = _libraries['llvm'].LLVMMetadataAsValue - LLVMMetadataAsValue.restype = LLVMValueRef - LLVMMetadataAsValue.argtypes = [LLVMContextRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMValueAsMetadata = _libraries['llvm'].LLVMValueAsMetadata - LLVMValueAsMetadata.restype = LLVMMetadataRef - LLVMValueAsMetadata.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetMDString = _libraries['llvm'].LLVMGetMDString - LLVMGetMDString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetMDString.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMGetMDNodeNumOperands = _libraries['llvm'].LLVMGetMDNodeNumOperands - LLVMGetMDNodeNumOperands.restype = ctypes.c_uint32 - LLVMGetMDNodeNumOperands.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetMDNodeOperands = _libraries['llvm'].LLVMGetMDNodeOperands - LLVMGetMDNodeOperands.restype = None - LLVMGetMDNodeOperands.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMMDStringInContext = _libraries['llvm'].LLVMMDStringInContext - LLVMMDStringInContext.restype = LLVMValueRef - LLVMMDStringInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMMDString = _libraries['llvm'].LLVMMDString - LLVMMDString.restype = LLVMValueRef - LLVMMDString.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMMDNodeInContext = _libraries['llvm'].LLVMMDNodeInContext - LLVMMDNodeInContext.restype = LLVMValueRef - LLVMMDNodeInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMMDNode = _libraries['llvm'].LLVMMDNode - LLVMMDNode.restype = LLVMValueRef - LLVMMDNode.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBasicBlockAsValue = _libraries['llvm'].LLVMBasicBlockAsValue - LLVMBasicBlockAsValue.restype = LLVMValueRef - LLVMBasicBlockAsValue.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMValueIsBasicBlock = _libraries['llvm'].LLVMValueIsBasicBlock - LLVMValueIsBasicBlock.restype = LLVMBool - LLVMValueIsBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMValueAsBasicBlock = _libraries['llvm'].LLVMValueAsBasicBlock - LLVMValueAsBasicBlock.restype = LLVMBasicBlockRef - LLVMValueAsBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetBasicBlockName = _libraries['llvm'].LLVMGetBasicBlockName - LLVMGetBasicBlockName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetBasicBlockName.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetBasicBlockParent = _libraries['llvm'].LLVMGetBasicBlockParent - LLVMGetBasicBlockParent.restype = LLVMValueRef - LLVMGetBasicBlockParent.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetBasicBlockTerminator = _libraries['llvm'].LLVMGetBasicBlockTerminator - LLVMGetBasicBlockTerminator.restype = LLVMValueRef - LLVMGetBasicBlockTerminator.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMCountBasicBlocks = _libraries['llvm'].LLVMCountBasicBlocks - LLVMCountBasicBlocks.restype = ctypes.c_uint32 - LLVMCountBasicBlocks.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetBasicBlocks = _libraries['llvm'].LLVMGetBasicBlocks - LLVMGetBasicBlocks.restype = None - LLVMGetBasicBlocks.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueBasicBlock))] -except AttributeError: - pass -try: - LLVMGetFirstBasicBlock = _libraries['llvm'].LLVMGetFirstBasicBlock - LLVMGetFirstBasicBlock.restype = LLVMBasicBlockRef - LLVMGetFirstBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetLastBasicBlock = _libraries['llvm'].LLVMGetLastBasicBlock - LLVMGetLastBasicBlock.restype = LLVMBasicBlockRef - LLVMGetLastBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextBasicBlock = _libraries['llvm'].LLVMGetNextBasicBlock - LLVMGetNextBasicBlock.restype = LLVMBasicBlockRef - LLVMGetNextBasicBlock.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetPreviousBasicBlock = _libraries['llvm'].LLVMGetPreviousBasicBlock - LLVMGetPreviousBasicBlock.restype = LLVMBasicBlockRef - LLVMGetPreviousBasicBlock.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetEntryBasicBlock = _libraries['llvm'].LLVMGetEntryBasicBlock - LLVMGetEntryBasicBlock.restype = LLVMBasicBlockRef - LLVMGetEntryBasicBlock.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInsertExistingBasicBlockAfterInsertBlock = _libraries['llvm'].LLVMInsertExistingBasicBlockAfterInsertBlock - LLVMInsertExistingBasicBlockAfterInsertBlock.restype = None - LLVMInsertExistingBasicBlockAfterInsertBlock.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMAppendExistingBasicBlock = _libraries['llvm'].LLVMAppendExistingBasicBlock - LLVMAppendExistingBasicBlock.restype = None - LLVMAppendExistingBasicBlock.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMCreateBasicBlockInContext = _libraries['llvm'].LLVMCreateBasicBlockInContext - LLVMCreateBasicBlockInContext.restype = LLVMBasicBlockRef - LLVMCreateBasicBlockInContext.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAppendBasicBlockInContext = _libraries['llvm'].LLVMAppendBasicBlockInContext - LLVMAppendBasicBlockInContext.restype = LLVMBasicBlockRef - LLVMAppendBasicBlockInContext.argtypes = [LLVMContextRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAppendBasicBlock = _libraries['llvm'].LLVMAppendBasicBlock - LLVMAppendBasicBlock.restype = LLVMBasicBlockRef - LLVMAppendBasicBlock.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMInsertBasicBlockInContext = _libraries['llvm'].LLVMInsertBasicBlockInContext - LLVMInsertBasicBlockInContext.restype = LLVMBasicBlockRef - LLVMInsertBasicBlockInContext.argtypes = [LLVMContextRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMInsertBasicBlock = _libraries['llvm'].LLVMInsertBasicBlock - LLVMInsertBasicBlock.restype = LLVMBasicBlockRef - LLVMInsertBasicBlock.argtypes = [LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDeleteBasicBlock = _libraries['llvm'].LLVMDeleteBasicBlock - LLVMDeleteBasicBlock.restype = None - LLVMDeleteBasicBlock.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMRemoveBasicBlockFromParent = _libraries['llvm'].LLVMRemoveBasicBlockFromParent - LLVMRemoveBasicBlockFromParent.restype = None - LLVMRemoveBasicBlockFromParent.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMMoveBasicBlockBefore = _libraries['llvm'].LLVMMoveBasicBlockBefore - LLVMMoveBasicBlockBefore.restype = None - LLVMMoveBasicBlockBefore.argtypes = [LLVMBasicBlockRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMMoveBasicBlockAfter = _libraries['llvm'].LLVMMoveBasicBlockAfter - LLVMMoveBasicBlockAfter.restype = None - LLVMMoveBasicBlockAfter.argtypes = [LLVMBasicBlockRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetFirstInstruction = _libraries['llvm'].LLVMGetFirstInstruction - LLVMGetFirstInstruction.restype = LLVMValueRef - LLVMGetFirstInstruction.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetLastInstruction = _libraries['llvm'].LLVMGetLastInstruction - LLVMGetLastInstruction.restype = LLVMValueRef - LLVMGetLastInstruction.argtypes = [LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMHasMetadata = _libraries['llvm'].LLVMHasMetadata - LLVMHasMetadata.restype = ctypes.c_int32 - LLVMHasMetadata.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetMetadata = _libraries['llvm'].LLVMGetMetadata - LLVMGetMetadata.restype = LLVMValueRef - LLVMGetMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetMetadata = _libraries['llvm'].LLVMSetMetadata - LLVMSetMetadata.restype = None - LLVMSetMetadata.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionGetAllMetadataOtherThanDebugLoc = _libraries['llvm'].LLVMInstructionGetAllMetadataOtherThanDebugLoc - LLVMInstructionGetAllMetadataOtherThanDebugLoc.restype = ctypes.POINTER(struct_LLVMOpaqueValueMetadataEntry) - LLVMInstructionGetAllMetadataOtherThanDebugLoc.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMGetInstructionParent = _libraries['llvm'].LLVMGetInstructionParent - LLVMGetInstructionParent.restype = LLVMBasicBlockRef - LLVMGetInstructionParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNextInstruction = _libraries['llvm'].LLVMGetNextInstruction - LLVMGetNextInstruction.restype = LLVMValueRef - LLVMGetNextInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetPreviousInstruction = _libraries['llvm'].LLVMGetPreviousInstruction - LLVMGetPreviousInstruction.restype = LLVMValueRef - LLVMGetPreviousInstruction.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionRemoveFromParent = _libraries['llvm'].LLVMInstructionRemoveFromParent - LLVMInstructionRemoveFromParent.restype = None - LLVMInstructionRemoveFromParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionEraseFromParent = _libraries['llvm'].LLVMInstructionEraseFromParent - LLVMInstructionEraseFromParent.restype = None - LLVMInstructionEraseFromParent.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetInstructionOpcode = _libraries['llvm'].LLVMGetInstructionOpcode - LLVMGetInstructionOpcode.restype = LLVMOpcode - LLVMGetInstructionOpcode.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetICmpPredicate = _libraries['llvm'].LLVMGetICmpPredicate - LLVMGetICmpPredicate.restype = LLVMIntPredicate - LLVMGetICmpPredicate.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetFCmpPredicate = _libraries['llvm'].LLVMGetFCmpPredicate - LLVMGetFCmpPredicate.restype = LLVMRealPredicate - LLVMGetFCmpPredicate.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionClone = _libraries['llvm'].LLVMInstructionClone - LLVMInstructionClone.restype = LLVMValueRef - LLVMInstructionClone.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsATerminatorInst = _libraries['llvm'].LLVMIsATerminatorInst - LLVMIsATerminatorInst.restype = LLVMValueRef - LLVMIsATerminatorInst.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetNumArgOperands = _libraries['llvm'].LLVMGetNumArgOperands - LLVMGetNumArgOperands.restype = ctypes.c_uint32 - LLVMGetNumArgOperands.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetInstructionCallConv = _libraries['llvm'].LLVMSetInstructionCallConv - LLVMSetInstructionCallConv.restype = None - LLVMSetInstructionCallConv.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetInstructionCallConv = _libraries['llvm'].LLVMGetInstructionCallConv - LLVMGetInstructionCallConv.restype = ctypes.c_uint32 - LLVMGetInstructionCallConv.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetInstrParamAlignment = _libraries['llvm'].LLVMSetInstrParamAlignment - LLVMSetInstrParamAlignment.restype = None - LLVMSetInstrParamAlignment.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddCallSiteAttribute = _libraries['llvm'].LLVMAddCallSiteAttribute - LLVMAddCallSiteAttribute.restype = None - LLVMAddCallSiteAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, LLVMAttributeRef] -except AttributeError: - pass -try: - LLVMGetCallSiteAttributeCount = _libraries['llvm'].LLVMGetCallSiteAttributeCount - LLVMGetCallSiteAttributeCount.restype = ctypes.c_uint32 - LLVMGetCallSiteAttributeCount.argtypes = [LLVMValueRef, LLVMAttributeIndex] -except AttributeError: - pass -try: - LLVMGetCallSiteAttributes = _libraries['llvm'].LLVMGetCallSiteAttributes - LLVMGetCallSiteAttributes.restype = None - LLVMGetCallSiteAttributes.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueAttributeRef))] -except AttributeError: - pass -try: - LLVMGetCallSiteEnumAttribute = _libraries['llvm'].LLVMGetCallSiteEnumAttribute - LLVMGetCallSiteEnumAttribute.restype = LLVMAttributeRef - LLVMGetCallSiteEnumAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetCallSiteStringAttribute = _libraries['llvm'].LLVMGetCallSiteStringAttribute - LLVMGetCallSiteStringAttribute.restype = LLVMAttributeRef - LLVMGetCallSiteStringAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveCallSiteEnumAttribute = _libraries['llvm'].LLVMRemoveCallSiteEnumAttribute - LLVMRemoveCallSiteEnumAttribute.restype = None - LLVMRemoveCallSiteEnumAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMRemoveCallSiteStringAttribute = _libraries['llvm'].LLVMRemoveCallSiteStringAttribute - LLVMRemoveCallSiteStringAttribute.restype = None - LLVMRemoveCallSiteStringAttribute.argtypes = [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetCalledFunctionType = _libraries['llvm'].LLVMGetCalledFunctionType - LLVMGetCalledFunctionType.restype = LLVMTypeRef - LLVMGetCalledFunctionType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetCalledValue = _libraries['llvm'].LLVMGetCalledValue - LLVMGetCalledValue.restype = LLVMValueRef - LLVMGetCalledValue.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsTailCall = _libraries['llvm'].LLVMIsTailCall - LLVMIsTailCall.restype = LLVMBool - LLVMIsTailCall.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetTailCall = _libraries['llvm'].LLVMSetTailCall - LLVMSetTailCall.restype = None - LLVMSetTailCall.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetNormalDest = _libraries['llvm'].LLVMGetNormalDest - LLVMGetNormalDest.restype = LLVMBasicBlockRef - LLVMGetNormalDest.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetUnwindDest = _libraries['llvm'].LLVMGetUnwindDest - LLVMGetUnwindDest.restype = LLVMBasicBlockRef - LLVMGetUnwindDest.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetNormalDest = _libraries['llvm'].LLVMSetNormalDest - LLVMSetNormalDest.restype = None - LLVMSetNormalDest.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMSetUnwindDest = _libraries['llvm'].LLVMSetUnwindDest - LLVMSetUnwindDest.restype = None - LLVMSetUnwindDest.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetNumSuccessors = _libraries['llvm'].LLVMGetNumSuccessors - LLVMGetNumSuccessors.restype = ctypes.c_uint32 - LLVMGetNumSuccessors.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetSuccessor = _libraries['llvm'].LLVMGetSuccessor - LLVMGetSuccessor.restype = LLVMBasicBlockRef - LLVMGetSuccessor.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetSuccessor = _libraries['llvm'].LLVMSetSuccessor - LLVMSetSuccessor.restype = None - LLVMSetSuccessor.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMIsConditional = _libraries['llvm'].LLVMIsConditional - LLVMIsConditional.restype = LLVMBool - LLVMIsConditional.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetCondition = _libraries['llvm'].LLVMGetCondition - LLVMGetCondition.restype = LLVMValueRef - LLVMGetCondition.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCondition = _libraries['llvm'].LLVMSetCondition - LLVMSetCondition.restype = None - LLVMSetCondition.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetSwitchDefaultDest = _libraries['llvm'].LLVMGetSwitchDefaultDest - LLVMGetSwitchDefaultDest.restype = LLVMBasicBlockRef - LLVMGetSwitchDefaultDest.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetAllocatedType = _libraries['llvm'].LLVMGetAllocatedType - LLVMGetAllocatedType.restype = LLVMTypeRef - LLVMGetAllocatedType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsInBounds = _libraries['llvm'].LLVMIsInBounds - LLVMIsInBounds.restype = LLVMBool - LLVMIsInBounds.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetIsInBounds = _libraries['llvm'].LLVMSetIsInBounds - LLVMSetIsInBounds.restype = None - LLVMSetIsInBounds.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetGEPSourceElementType = _libraries['llvm'].LLVMGetGEPSourceElementType - LLVMGetGEPSourceElementType.restype = LLVMTypeRef - LLVMGetGEPSourceElementType.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddIncoming = _libraries['llvm'].LLVMAddIncoming - LLVMAddIncoming.restype = None - LLVMAddIncoming.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMCountIncoming = _libraries['llvm'].LLVMCountIncoming - LLVMCountIncoming.restype = ctypes.c_uint32 - LLVMCountIncoming.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetIncomingValue = _libraries['llvm'].LLVMGetIncomingValue - LLVMGetIncomingValue.restype = LLVMValueRef - LLVMGetIncomingValue.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetIncomingBlock = _libraries['llvm'].LLVMGetIncomingBlock - LLVMGetIncomingBlock.restype = LLVMBasicBlockRef - LLVMGetIncomingBlock.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMGetNumIndices = _libraries['llvm'].LLVMGetNumIndices - LLVMGetNumIndices.restype = ctypes.c_uint32 - LLVMGetNumIndices.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetIndices = _libraries['llvm'].LLVMGetIndices - LLVMGetIndices.restype = ctypes.POINTER(ctypes.c_uint32) - LLVMGetIndices.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMCreateBuilderInContext = _libraries['llvm'].LLVMCreateBuilderInContext - LLVMCreateBuilderInContext.restype = LLVMBuilderRef - LLVMCreateBuilderInContext.argtypes = [LLVMContextRef] -except AttributeError: - pass -try: - LLVMCreateBuilder = _libraries['llvm'].LLVMCreateBuilder - LLVMCreateBuilder.restype = LLVMBuilderRef - LLVMCreateBuilder.argtypes = [] -except AttributeError: - pass -try: - LLVMPositionBuilder = _libraries['llvm'].LLVMPositionBuilder - LLVMPositionBuilder.restype = None - LLVMPositionBuilder.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMPositionBuilderBefore = _libraries['llvm'].LLVMPositionBuilderBefore - LLVMPositionBuilderBefore.restype = None - LLVMPositionBuilderBefore.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMPositionBuilderAtEnd = _libraries['llvm'].LLVMPositionBuilderAtEnd - LLVMPositionBuilderAtEnd.restype = None - LLVMPositionBuilderAtEnd.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetInsertBlock = _libraries['llvm'].LLVMGetInsertBlock - LLVMGetInsertBlock.restype = LLVMBasicBlockRef - LLVMGetInsertBlock.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMClearInsertionPosition = _libraries['llvm'].LLVMClearInsertionPosition - LLVMClearInsertionPosition.restype = None - LLVMClearInsertionPosition.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMInsertIntoBuilder = _libraries['llvm'].LLVMInsertIntoBuilder - LLVMInsertIntoBuilder.restype = None - LLVMInsertIntoBuilder.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMInsertIntoBuilderWithName = _libraries['llvm'].LLVMInsertIntoBuilderWithName - LLVMInsertIntoBuilderWithName.restype = None - LLVMInsertIntoBuilderWithName.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDisposeBuilder = _libraries['llvm'].LLVMDisposeBuilder - LLVMDisposeBuilder.restype = None - LLVMDisposeBuilder.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMGetCurrentDebugLocation2 = _libraries['llvm'].LLVMGetCurrentDebugLocation2 - LLVMGetCurrentDebugLocation2.restype = LLVMMetadataRef - LLVMGetCurrentDebugLocation2.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMSetCurrentDebugLocation2 = _libraries['llvm'].LLVMSetCurrentDebugLocation2 - LLVMSetCurrentDebugLocation2.restype = None - LLVMSetCurrentDebugLocation2.argtypes = [LLVMBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMSetInstDebugLocation = _libraries['llvm'].LLVMSetInstDebugLocation - LLVMSetInstDebugLocation.restype = None - LLVMSetInstDebugLocation.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddMetadataToInst = _libraries['llvm'].LLVMAddMetadataToInst - LLVMAddMetadataToInst.restype = None - LLVMAddMetadataToInst.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuilderGetDefaultFPMathTag = _libraries['llvm'].LLVMBuilderGetDefaultFPMathTag - LLVMBuilderGetDefaultFPMathTag.restype = LLVMMetadataRef - LLVMBuilderGetDefaultFPMathTag.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuilderSetDefaultFPMathTag = _libraries['llvm'].LLVMBuilderSetDefaultFPMathTag - LLVMBuilderSetDefaultFPMathTag.restype = None - LLVMBuilderSetDefaultFPMathTag.argtypes = [LLVMBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMSetCurrentDebugLocation = _libraries['llvm'].LLVMSetCurrentDebugLocation - LLVMSetCurrentDebugLocation.restype = None - LLVMSetCurrentDebugLocation.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetCurrentDebugLocation = _libraries['llvm'].LLVMGetCurrentDebugLocation - LLVMGetCurrentDebugLocation.restype = LLVMValueRef - LLVMGetCurrentDebugLocation.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuildRetVoid = _libraries['llvm'].LLVMBuildRetVoid - LLVMBuildRetVoid.restype = LLVMValueRef - LLVMBuildRetVoid.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuildRet = _libraries['llvm'].LLVMBuildRet - LLVMBuildRet.restype = LLVMValueRef - LLVMBuildRet.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildAggregateRet = _libraries['llvm'].LLVMBuildAggregateRet - LLVMBuildAggregateRet.restype = LLVMValueRef - LLVMBuildAggregateRet.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildBr = _libraries['llvm'].LLVMBuildBr - LLVMBuildBr.restype = LLVMValueRef - LLVMBuildBr.argtypes = [LLVMBuilderRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildCondBr = _libraries['llvm'].LLVMBuildCondBr - LLVMBuildCondBr.restype = LLVMValueRef - LLVMBuildCondBr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildSwitch = _libraries['llvm'].LLVMBuildSwitch - LLVMBuildSwitch.restype = LLVMValueRef - LLVMBuildSwitch.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildIndirectBr = _libraries['llvm'].LLVMBuildIndirectBr - LLVMBuildIndirectBr.restype = LLVMValueRef - LLVMBuildIndirectBr.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildInvoke = _libraries['llvm'].LLVMBuildInvoke - LLVMBuildInvoke.restype = LLVMValueRef - LLVMBuildInvoke.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBasicBlockRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInvoke2 = _libraries['llvm'].LLVMBuildInvoke2 - LLVMBuildInvoke2.restype = LLVMValueRef - LLVMBuildInvoke2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, LLVMBasicBlockRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildUnreachable = _libraries['llvm'].LLVMBuildUnreachable - LLVMBuildUnreachable.restype = LLVMValueRef - LLVMBuildUnreachable.argtypes = [LLVMBuilderRef] -except AttributeError: - pass -try: - LLVMBuildResume = _libraries['llvm'].LLVMBuildResume - LLVMBuildResume.restype = LLVMValueRef - LLVMBuildResume.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildLandingPad = _libraries['llvm'].LLVMBuildLandingPad - LLVMBuildLandingPad.restype = LLVMValueRef - LLVMBuildLandingPad.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCleanupRet = _libraries['llvm'].LLVMBuildCleanupRet - LLVMBuildCleanupRet.restype = LLVMValueRef - LLVMBuildCleanupRet.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildCatchRet = _libraries['llvm'].LLVMBuildCatchRet - LLVMBuildCatchRet.restype = LLVMValueRef - LLVMBuildCatchRet.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMBuildCatchPad = _libraries['llvm'].LLVMBuildCatchPad - LLVMBuildCatchPad.restype = LLVMValueRef - LLVMBuildCatchPad.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCleanupPad = _libraries['llvm'].LLVMBuildCleanupPad - LLVMBuildCleanupPad.restype = LLVMValueRef - LLVMBuildCleanupPad.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCatchSwitch = _libraries['llvm'].LLVMBuildCatchSwitch - LLVMBuildCatchSwitch.restype = LLVMValueRef - LLVMBuildCatchSwitch.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddCase = _libraries['llvm'].LLVMAddCase - LLVMAddCase.restype = None - LLVMAddCase.argtypes = [LLVMValueRef, LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMAddDestination = _libraries['llvm'].LLVMAddDestination - LLVMAddDestination.restype = None - LLVMAddDestination.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetNumClauses = _libraries['llvm'].LLVMGetNumClauses - LLVMGetNumClauses.restype = ctypes.c_uint32 - LLVMGetNumClauses.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetClause = _libraries['llvm'].LLVMGetClause - LLVMGetClause.restype = LLVMValueRef - LLVMGetClause.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddClause = _libraries['llvm'].LLVMAddClause - LLVMAddClause.restype = None - LLVMAddClause.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMIsCleanup = _libraries['llvm'].LLVMIsCleanup - LLVMIsCleanup.restype = LLVMBool - LLVMIsCleanup.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCleanup = _libraries['llvm'].LLVMSetCleanup - LLVMSetCleanup.restype = None - LLVMSetCleanup.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMAddHandler = _libraries['llvm'].LLVMAddHandler - LLVMAddHandler.restype = None - LLVMAddHandler.argtypes = [LLVMValueRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMGetNumHandlers = _libraries['llvm'].LLVMGetNumHandlers - LLVMGetNumHandlers.restype = ctypes.c_uint32 - LLVMGetNumHandlers.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetHandlers = _libraries['llvm'].LLVMGetHandlers - LLVMGetHandlers.restype = None - LLVMGetHandlers.argtypes = [LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueBasicBlock))] -except AttributeError: - pass -try: - LLVMGetArgOperand = _libraries['llvm'].LLVMGetArgOperand - LLVMGetArgOperand.restype = LLVMValueRef - LLVMGetArgOperand.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSetArgOperand = _libraries['llvm'].LLVMSetArgOperand - LLVMSetArgOperand.restype = None - LLVMSetArgOperand.argtypes = [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetParentCatchSwitch = _libraries['llvm'].LLVMGetParentCatchSwitch - LLVMGetParentCatchSwitch.restype = LLVMValueRef - LLVMGetParentCatchSwitch.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetParentCatchSwitch = _libraries['llvm'].LLVMSetParentCatchSwitch - LLVMSetParentCatchSwitch.restype = None - LLVMSetParentCatchSwitch.argtypes = [LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildAdd = _libraries['llvm'].LLVMBuildAdd - LLVMBuildAdd.restype = LLVMValueRef - LLVMBuildAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWAdd = _libraries['llvm'].LLVMBuildNSWAdd - LLVMBuildNSWAdd.restype = LLVMValueRef - LLVMBuildNSWAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWAdd = _libraries['llvm'].LLVMBuildNUWAdd - LLVMBuildNUWAdd.restype = LLVMValueRef - LLVMBuildNUWAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFAdd = _libraries['llvm'].LLVMBuildFAdd - LLVMBuildFAdd.restype = LLVMValueRef - LLVMBuildFAdd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSub = _libraries['llvm'].LLVMBuildSub - LLVMBuildSub.restype = LLVMValueRef - LLVMBuildSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWSub = _libraries['llvm'].LLVMBuildNSWSub - LLVMBuildNSWSub.restype = LLVMValueRef - LLVMBuildNSWSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWSub = _libraries['llvm'].LLVMBuildNUWSub - LLVMBuildNUWSub.restype = LLVMValueRef - LLVMBuildNUWSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFSub = _libraries['llvm'].LLVMBuildFSub - LLVMBuildFSub.restype = LLVMValueRef - LLVMBuildFSub.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildMul = _libraries['llvm'].LLVMBuildMul - LLVMBuildMul.restype = LLVMValueRef - LLVMBuildMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWMul = _libraries['llvm'].LLVMBuildNSWMul - LLVMBuildNSWMul.restype = LLVMValueRef - LLVMBuildNSWMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWMul = _libraries['llvm'].LLVMBuildNUWMul - LLVMBuildNUWMul.restype = LLVMValueRef - LLVMBuildNUWMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFMul = _libraries['llvm'].LLVMBuildFMul - LLVMBuildFMul.restype = LLVMValueRef - LLVMBuildFMul.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildUDiv = _libraries['llvm'].LLVMBuildUDiv - LLVMBuildUDiv.restype = LLVMValueRef - LLVMBuildUDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExactUDiv = _libraries['llvm'].LLVMBuildExactUDiv - LLVMBuildExactUDiv.restype = LLVMValueRef - LLVMBuildExactUDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSDiv = _libraries['llvm'].LLVMBuildSDiv - LLVMBuildSDiv.restype = LLVMValueRef - LLVMBuildSDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExactSDiv = _libraries['llvm'].LLVMBuildExactSDiv - LLVMBuildExactSDiv.restype = LLVMValueRef - LLVMBuildExactSDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFDiv = _libraries['llvm'].LLVMBuildFDiv - LLVMBuildFDiv.restype = LLVMValueRef - LLVMBuildFDiv.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildURem = _libraries['llvm'].LLVMBuildURem - LLVMBuildURem.restype = LLVMValueRef - LLVMBuildURem.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSRem = _libraries['llvm'].LLVMBuildSRem - LLVMBuildSRem.restype = LLVMValueRef - LLVMBuildSRem.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFRem = _libraries['llvm'].LLVMBuildFRem - LLVMBuildFRem.restype = LLVMValueRef - LLVMBuildFRem.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildShl = _libraries['llvm'].LLVMBuildShl - LLVMBuildShl.restype = LLVMValueRef - LLVMBuildShl.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildLShr = _libraries['llvm'].LLVMBuildLShr - LLVMBuildLShr.restype = LLVMValueRef - LLVMBuildLShr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAShr = _libraries['llvm'].LLVMBuildAShr - LLVMBuildAShr.restype = LLVMValueRef - LLVMBuildAShr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAnd = _libraries['llvm'].LLVMBuildAnd - LLVMBuildAnd.restype = LLVMValueRef - LLVMBuildAnd.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildOr = _libraries['llvm'].LLVMBuildOr - LLVMBuildOr.restype = LLVMValueRef - LLVMBuildOr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildXor = _libraries['llvm'].LLVMBuildXor - LLVMBuildXor.restype = LLVMValueRef - LLVMBuildXor.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildBinOp = _libraries['llvm'].LLVMBuildBinOp - LLVMBuildBinOp.restype = LLVMValueRef - LLVMBuildBinOp.argtypes = [LLVMBuilderRef, LLVMOpcode, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNeg = _libraries['llvm'].LLVMBuildNeg - LLVMBuildNeg.restype = LLVMValueRef - LLVMBuildNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNSWNeg = _libraries['llvm'].LLVMBuildNSWNeg - LLVMBuildNSWNeg.restype = LLVMValueRef - LLVMBuildNSWNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNUWNeg = _libraries['llvm'].LLVMBuildNUWNeg - LLVMBuildNUWNeg.restype = LLVMValueRef - LLVMBuildNUWNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFNeg = _libraries['llvm'].LLVMBuildFNeg - LLVMBuildFNeg.restype = LLVMValueRef - LLVMBuildFNeg.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildNot = _libraries['llvm'].LLVMBuildNot - LLVMBuildNot.restype = LLVMValueRef - LLVMBuildNot.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildMalloc = _libraries['llvm'].LLVMBuildMalloc - LLVMBuildMalloc.restype = LLVMValueRef - LLVMBuildMalloc.argtypes = [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildArrayMalloc = _libraries['llvm'].LLVMBuildArrayMalloc - LLVMBuildArrayMalloc.restype = LLVMValueRef - LLVMBuildArrayMalloc.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildMemSet = _libraries['llvm'].LLVMBuildMemSet - LLVMBuildMemSet.restype = LLVMValueRef - LLVMBuildMemSet.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMBuildMemCpy = _libraries['llvm'].LLVMBuildMemCpy - LLVMBuildMemCpy.restype = LLVMValueRef - LLVMBuildMemCpy.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildMemMove = _libraries['llvm'].LLVMBuildMemMove - LLVMBuildMemMove.restype = LLVMValueRef - LLVMBuildMemMove.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.c_uint32, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildAlloca = _libraries['llvm'].LLVMBuildAlloca - LLVMBuildAlloca.restype = LLVMValueRef - LLVMBuildAlloca.argtypes = [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildArrayAlloca = _libraries['llvm'].LLVMBuildArrayAlloca - LLVMBuildArrayAlloca.restype = LLVMValueRef - LLVMBuildArrayAlloca.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFree = _libraries['llvm'].LLVMBuildFree - LLVMBuildFree.restype = LLVMValueRef - LLVMBuildFree.argtypes = [LLVMBuilderRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildLoad = _libraries['llvm'].LLVMBuildLoad - LLVMBuildLoad.restype = LLVMValueRef - LLVMBuildLoad.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildLoad2 = _libraries['llvm'].LLVMBuildLoad2 - LLVMBuildLoad2.restype = LLVMValueRef - LLVMBuildLoad2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildStore = _libraries['llvm'].LLVMBuildStore - LLVMBuildStore.restype = LLVMValueRef - LLVMBuildStore.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMBuildGEP = _libraries['llvm'].LLVMBuildGEP - LLVMBuildGEP.restype = LLVMValueRef - LLVMBuildGEP.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInBoundsGEP = _libraries['llvm'].LLVMBuildInBoundsGEP - LLVMBuildInBoundsGEP.restype = LLVMValueRef - LLVMBuildInBoundsGEP.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildStructGEP = _libraries['llvm'].LLVMBuildStructGEP - LLVMBuildStructGEP.restype = LLVMValueRef - LLVMBuildStructGEP.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildGEP2 = _libraries['llvm'].LLVMBuildGEP2 - LLVMBuildGEP2.restype = LLVMValueRef - LLVMBuildGEP2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInBoundsGEP2 = _libraries['llvm'].LLVMBuildInBoundsGEP2 - LLVMBuildInBoundsGEP2.restype = LLVMValueRef - LLVMBuildInBoundsGEP2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildStructGEP2 = _libraries['llvm'].LLVMBuildStructGEP2 - LLVMBuildStructGEP2.restype = LLVMValueRef - LLVMBuildStructGEP2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildGlobalString = _libraries['llvm'].LLVMBuildGlobalString - LLVMBuildGlobalString.restype = LLVMValueRef - LLVMBuildGlobalString.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildGlobalStringPtr = _libraries['llvm'].LLVMBuildGlobalStringPtr - LLVMBuildGlobalStringPtr.restype = LLVMValueRef - LLVMBuildGlobalStringPtr.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetVolatile = _libraries['llvm'].LLVMGetVolatile - LLVMGetVolatile.restype = LLVMBool - LLVMGetVolatile.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetVolatile = _libraries['llvm'].LLVMSetVolatile - LLVMSetVolatile.restype = None - LLVMSetVolatile.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetWeak = _libraries['llvm'].LLVMGetWeak - LLVMGetWeak.restype = LLVMBool - LLVMGetWeak.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetWeak = _libraries['llvm'].LLVMSetWeak - LLVMSetWeak.restype = None - LLVMSetWeak.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetOrdering = _libraries['llvm'].LLVMGetOrdering - LLVMGetOrdering.restype = LLVMAtomicOrdering - LLVMGetOrdering.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetOrdering = _libraries['llvm'].LLVMSetOrdering - LLVMSetOrdering.restype = None - LLVMSetOrdering.argtypes = [LLVMValueRef, LLVMAtomicOrdering] -except AttributeError: - pass -try: - LLVMGetAtomicRMWBinOp = _libraries['llvm'].LLVMGetAtomicRMWBinOp - LLVMGetAtomicRMWBinOp.restype = LLVMAtomicRMWBinOp - LLVMGetAtomicRMWBinOp.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetAtomicRMWBinOp = _libraries['llvm'].LLVMSetAtomicRMWBinOp - LLVMSetAtomicRMWBinOp.restype = None - LLVMSetAtomicRMWBinOp.argtypes = [LLVMValueRef, LLVMAtomicRMWBinOp] -except AttributeError: - pass -try: - LLVMBuildTrunc = _libraries['llvm'].LLVMBuildTrunc - LLVMBuildTrunc.restype = LLVMValueRef - LLVMBuildTrunc.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildZExt = _libraries['llvm'].LLVMBuildZExt - LLVMBuildZExt.restype = LLVMValueRef - LLVMBuildZExt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSExt = _libraries['llvm'].LLVMBuildSExt - LLVMBuildSExt.restype = LLVMValueRef - LLVMBuildSExt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPToUI = _libraries['llvm'].LLVMBuildFPToUI - LLVMBuildFPToUI.restype = LLVMValueRef - LLVMBuildFPToUI.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPToSI = _libraries['llvm'].LLVMBuildFPToSI - LLVMBuildFPToSI.restype = LLVMValueRef - LLVMBuildFPToSI.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildUIToFP = _libraries['llvm'].LLVMBuildUIToFP - LLVMBuildUIToFP.restype = LLVMValueRef - LLVMBuildUIToFP.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSIToFP = _libraries['llvm'].LLVMBuildSIToFP - LLVMBuildSIToFP.restype = LLVMValueRef - LLVMBuildSIToFP.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPTrunc = _libraries['llvm'].LLVMBuildFPTrunc - LLVMBuildFPTrunc.restype = LLVMValueRef - LLVMBuildFPTrunc.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPExt = _libraries['llvm'].LLVMBuildFPExt - LLVMBuildFPExt.restype = LLVMValueRef - LLVMBuildFPExt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPtrToInt = _libraries['llvm'].LLVMBuildPtrToInt - LLVMBuildPtrToInt.restype = LLVMValueRef - LLVMBuildPtrToInt.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIntToPtr = _libraries['llvm'].LLVMBuildIntToPtr - LLVMBuildIntToPtr.restype = LLVMValueRef - LLVMBuildIntToPtr.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildBitCast = _libraries['llvm'].LLVMBuildBitCast - LLVMBuildBitCast.restype = LLVMValueRef - LLVMBuildBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAddrSpaceCast = _libraries['llvm'].LLVMBuildAddrSpaceCast - LLVMBuildAddrSpaceCast.restype = LLVMValueRef - LLVMBuildAddrSpaceCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildZExtOrBitCast = _libraries['llvm'].LLVMBuildZExtOrBitCast - LLVMBuildZExtOrBitCast.restype = LLVMValueRef - LLVMBuildZExtOrBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSExtOrBitCast = _libraries['llvm'].LLVMBuildSExtOrBitCast - LLVMBuildSExtOrBitCast.restype = LLVMValueRef - LLVMBuildSExtOrBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildTruncOrBitCast = _libraries['llvm'].LLVMBuildTruncOrBitCast - LLVMBuildTruncOrBitCast.restype = LLVMValueRef - LLVMBuildTruncOrBitCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCast = _libraries['llvm'].LLVMBuildCast - LLVMBuildCast.restype = LLVMValueRef - LLVMBuildCast.argtypes = [LLVMBuilderRef, LLVMOpcode, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPointerCast = _libraries['llvm'].LLVMBuildPointerCast - LLVMBuildPointerCast.restype = LLVMValueRef - LLVMBuildPointerCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIntCast2 = _libraries['llvm'].LLVMBuildIntCast2 - LLVMBuildIntCast2.restype = LLVMValueRef - LLVMBuildIntCast2.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, LLVMBool, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFPCast = _libraries['llvm'].LLVMBuildFPCast - LLVMBuildFPCast.restype = LLVMValueRef - LLVMBuildFPCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIntCast = _libraries['llvm'].LLVMBuildIntCast - LLVMBuildIntCast.restype = LLVMValueRef - LLVMBuildIntCast.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildICmp = _libraries['llvm'].LLVMBuildICmp - LLVMBuildICmp.restype = LLVMValueRef - LLVMBuildICmp.argtypes = [LLVMBuilderRef, LLVMIntPredicate, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFCmp = _libraries['llvm'].LLVMBuildFCmp - LLVMBuildFCmp.restype = LLVMValueRef - LLVMBuildFCmp.argtypes = [LLVMBuilderRef, LLVMRealPredicate, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPhi = _libraries['llvm'].LLVMBuildPhi - LLVMBuildPhi.restype = LLVMValueRef - LLVMBuildPhi.argtypes = [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCall = _libraries['llvm'].LLVMBuildCall - LLVMBuildCall.restype = LLVMValueRef - LLVMBuildCall.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildCall2 = _libraries['llvm'].LLVMBuildCall2 - LLVMBuildCall2.restype = LLVMValueRef - LLVMBuildCall2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildSelect = _libraries['llvm'].LLVMBuildSelect - LLVMBuildSelect.restype = LLVMValueRef - LLVMBuildSelect.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildVAArg = _libraries['llvm'].LLVMBuildVAArg - LLVMBuildVAArg.restype = LLVMValueRef - LLVMBuildVAArg.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExtractElement = _libraries['llvm'].LLVMBuildExtractElement - LLVMBuildExtractElement.restype = LLVMValueRef - LLVMBuildExtractElement.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInsertElement = _libraries['llvm'].LLVMBuildInsertElement - LLVMBuildInsertElement.restype = LLVMValueRef - LLVMBuildInsertElement.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildShuffleVector = _libraries['llvm'].LLVMBuildShuffleVector - LLVMBuildShuffleVector.restype = LLVMValueRef - LLVMBuildShuffleVector.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildExtractValue = _libraries['llvm'].LLVMBuildExtractValue - LLVMBuildExtractValue.restype = LLVMValueRef - LLVMBuildExtractValue.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildInsertValue = _libraries['llvm'].LLVMBuildInsertValue - LLVMBuildInsertValue.restype = LLVMValueRef - LLVMBuildInsertValue.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFreeze = _libraries['llvm'].LLVMBuildFreeze - LLVMBuildFreeze.restype = LLVMValueRef - LLVMBuildFreeze.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIsNull = _libraries['llvm'].LLVMBuildIsNull - LLVMBuildIsNull.restype = LLVMValueRef - LLVMBuildIsNull.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildIsNotNull = _libraries['llvm'].LLVMBuildIsNotNull - LLVMBuildIsNotNull.restype = LLVMValueRef - LLVMBuildIsNotNull.argtypes = [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPtrDiff = _libraries['llvm'].LLVMBuildPtrDiff - LLVMBuildPtrDiff.restype = LLVMValueRef - LLVMBuildPtrDiff.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildPtrDiff2 = _libraries['llvm'].LLVMBuildPtrDiff2 - LLVMBuildPtrDiff2.restype = LLVMValueRef - LLVMBuildPtrDiff2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildFence = _libraries['llvm'].LLVMBuildFence - LLVMBuildFence.restype = LLVMValueRef - LLVMBuildFence.argtypes = [LLVMBuilderRef, LLVMAtomicOrdering, LLVMBool, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMBuildAtomicRMW = _libraries['llvm'].LLVMBuildAtomicRMW - LLVMBuildAtomicRMW.restype = LLVMValueRef - LLVMBuildAtomicRMW.argtypes = [LLVMBuilderRef, LLVMAtomicRMWBinOp, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMBool] -except AttributeError: - pass -try: - LLVMBuildAtomicCmpXchg = _libraries['llvm'].LLVMBuildAtomicCmpXchg - LLVMBuildAtomicCmpXchg.restype = LLVMValueRef - LLVMBuildAtomicCmpXchg.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMAtomicOrdering, LLVMBool] -except AttributeError: - pass -try: - LLVMGetNumMaskElements = _libraries['llvm'].LLVMGetNumMaskElements - LLVMGetNumMaskElements.restype = ctypes.c_uint32 - LLVMGetNumMaskElements.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetUndefMaskElem = _libraries['llvm'].LLVMGetUndefMaskElem - LLVMGetUndefMaskElem.restype = ctypes.c_int32 - LLVMGetUndefMaskElem.argtypes = [] -except AttributeError: - pass -try: - LLVMGetMaskValue = _libraries['llvm'].LLVMGetMaskValue - LLVMGetMaskValue.restype = ctypes.c_int32 - LLVMGetMaskValue.argtypes = [LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIsAtomicSingleThread = _libraries['llvm'].LLVMIsAtomicSingleThread - LLVMIsAtomicSingleThread.restype = LLVMBool - LLVMIsAtomicSingleThread.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetAtomicSingleThread = _libraries['llvm'].LLVMSetAtomicSingleThread - LLVMSetAtomicSingleThread.restype = None - LLVMSetAtomicSingleThread.argtypes = [LLVMValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGetCmpXchgSuccessOrdering = _libraries['llvm'].LLVMGetCmpXchgSuccessOrdering - LLVMGetCmpXchgSuccessOrdering.restype = LLVMAtomicOrdering - LLVMGetCmpXchgSuccessOrdering.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCmpXchgSuccessOrdering = _libraries['llvm'].LLVMSetCmpXchgSuccessOrdering - LLVMSetCmpXchgSuccessOrdering.restype = None - LLVMSetCmpXchgSuccessOrdering.argtypes = [LLVMValueRef, LLVMAtomicOrdering] -except AttributeError: - pass -try: - LLVMGetCmpXchgFailureOrdering = _libraries['llvm'].LLVMGetCmpXchgFailureOrdering - LLVMGetCmpXchgFailureOrdering.restype = LLVMAtomicOrdering - LLVMGetCmpXchgFailureOrdering.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetCmpXchgFailureOrdering = _libraries['llvm'].LLVMSetCmpXchgFailureOrdering - LLVMSetCmpXchgFailureOrdering.restype = None - LLVMSetCmpXchgFailureOrdering.argtypes = [LLVMValueRef, LLVMAtomicOrdering] -except AttributeError: - pass -try: - LLVMCreateModuleProviderForExistingModule = _libraries['llvm'].LLVMCreateModuleProviderForExistingModule - LLVMCreateModuleProviderForExistingModule.restype = LLVMModuleProviderRef - LLVMCreateModuleProviderForExistingModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMDisposeModuleProvider = _libraries['llvm'].LLVMDisposeModuleProvider - LLVMDisposeModuleProvider.restype = None - LLVMDisposeModuleProvider.argtypes = [LLVMModuleProviderRef] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithContentsOfFile = _libraries['llvm'].LLVMCreateMemoryBufferWithContentsOfFile - LLVMCreateMemoryBufferWithContentsOfFile.restype = LLVMBool - LLVMCreateMemoryBufferWithContentsOfFile.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithSTDIN = _libraries['llvm'].LLVMCreateMemoryBufferWithSTDIN - LLVMCreateMemoryBufferWithSTDIN.restype = LLVMBool - LLVMCreateMemoryBufferWithSTDIN.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithMemoryRange = _libraries['llvm'].LLVMCreateMemoryBufferWithMemoryRange - LLVMCreateMemoryBufferWithMemoryRange.restype = LLVMMemoryBufferRef - LLVMCreateMemoryBufferWithMemoryRange.argtypes = [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), LLVMBool] -except AttributeError: - pass -try: - LLVMCreateMemoryBufferWithMemoryRangeCopy = _libraries['llvm'].LLVMCreateMemoryBufferWithMemoryRangeCopy - LLVMCreateMemoryBufferWithMemoryRangeCopy.restype = LLVMMemoryBufferRef - LLVMCreateMemoryBufferWithMemoryRangeCopy.argtypes = [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetBufferStart = _libraries['llvm'].LLVMGetBufferStart - LLVMGetBufferStart.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetBufferStart.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMGetBufferSize = _libraries['llvm'].LLVMGetBufferSize - LLVMGetBufferSize.restype = size_t - LLVMGetBufferSize.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMDisposeMemoryBuffer = _libraries['llvm'].LLVMDisposeMemoryBuffer - LLVMDisposeMemoryBuffer.restype = None - LLVMDisposeMemoryBuffer.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMGetGlobalPassRegistry = _libraries['llvm'].LLVMGetGlobalPassRegistry - LLVMGetGlobalPassRegistry.restype = LLVMPassRegistryRef - LLVMGetGlobalPassRegistry.argtypes = [] -except AttributeError: - pass -try: - LLVMCreatePassManager = _libraries['llvm'].LLVMCreatePassManager - LLVMCreatePassManager.restype = LLVMPassManagerRef - LLVMCreatePassManager.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateFunctionPassManagerForModule = _libraries['llvm'].LLVMCreateFunctionPassManagerForModule - LLVMCreateFunctionPassManagerForModule.restype = LLVMPassManagerRef - LLVMCreateFunctionPassManagerForModule.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMCreateFunctionPassManager = _libraries['llvm'].LLVMCreateFunctionPassManager - LLVMCreateFunctionPassManager.restype = LLVMPassManagerRef - LLVMCreateFunctionPassManager.argtypes = [LLVMModuleProviderRef] -except AttributeError: - pass -try: - LLVMRunPassManager = _libraries['llvm'].LLVMRunPassManager - LLVMRunPassManager.restype = LLVMBool - LLVMRunPassManager.argtypes = [LLVMPassManagerRef, LLVMModuleRef] -except AttributeError: - pass -try: - LLVMInitializeFunctionPassManager = _libraries['llvm'].LLVMInitializeFunctionPassManager - LLVMInitializeFunctionPassManager.restype = LLVMBool - LLVMInitializeFunctionPassManager.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMRunFunctionPassManager = _libraries['llvm'].LLVMRunFunctionPassManager - LLVMRunFunctionPassManager.restype = LLVMBool - LLVMRunFunctionPassManager.argtypes = [LLVMPassManagerRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMFinalizeFunctionPassManager = _libraries['llvm'].LLVMFinalizeFunctionPassManager - LLVMFinalizeFunctionPassManager.restype = LLVMBool - LLVMFinalizeFunctionPassManager.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMDisposePassManager = _libraries['llvm'].LLVMDisposePassManager - LLVMDisposePassManager.restype = None - LLVMDisposePassManager.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMStartMultithreaded = _libraries['llvm'].LLVMStartMultithreaded - LLVMStartMultithreaded.restype = LLVMBool - LLVMStartMultithreaded.argtypes = [] -except AttributeError: - pass -try: - LLVMStopMultithreaded = _libraries['llvm'].LLVMStopMultithreaded - LLVMStopMultithreaded.restype = None - LLVMStopMultithreaded.argtypes = [] -except AttributeError: - pass -try: - LLVMIsMultithreaded = _libraries['llvm'].LLVMIsMultithreaded - LLVMIsMultithreaded.restype = LLVMBool - LLVMIsMultithreaded.argtypes = [] -except AttributeError: - pass -LLVM_C_DEBUGINFO_H = True # macro +# LLVMAttributeRef LLVMCreateEnumAttribute(LLVMContextRef C, unsigned int KindID, uint64_t Val) +try: (LLVMCreateEnumAttribute:=dll.LLVMCreateEnumAttribute).restype, LLVMCreateEnumAttribute.argtypes = LLVMAttributeRef, [LLVMContextRef, ctypes.c_uint32, uint64_t] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMDIFlags' -c__EA_LLVMDIFlags__enumvalues = { - 0: 'LLVMDIFlagZero', - 1: 'LLVMDIFlagPrivate', - 2: 'LLVMDIFlagProtected', - 3: 'LLVMDIFlagPublic', - 4: 'LLVMDIFlagFwdDecl', - 8: 'LLVMDIFlagAppleBlock', - 16: 'LLVMDIFlagReservedBit4', - 32: 'LLVMDIFlagVirtual', - 64: 'LLVMDIFlagArtificial', - 128: 'LLVMDIFlagExplicit', - 256: 'LLVMDIFlagPrototyped', - 512: 'LLVMDIFlagObjcClassComplete', - 1024: 'LLVMDIFlagObjectPointer', - 2048: 'LLVMDIFlagVector', - 4096: 'LLVMDIFlagStaticMember', - 8192: 'LLVMDIFlagLValueReference', - 16384: 'LLVMDIFlagRValueReference', - 32768: 'LLVMDIFlagReserved', - 65536: 'LLVMDIFlagSingleInheritance', - 131072: 'LLVMDIFlagMultipleInheritance', - 196608: 'LLVMDIFlagVirtualInheritance', - 262144: 'LLVMDIFlagIntroducedVirtual', - 524288: 'LLVMDIFlagBitField', - 1048576: 'LLVMDIFlagNoReturn', - 4194304: 'LLVMDIFlagTypePassByValue', - 8388608: 'LLVMDIFlagTypePassByReference', - 16777216: 'LLVMDIFlagEnumClass', - 16777216: 'LLVMDIFlagFixedEnum', - 33554432: 'LLVMDIFlagThunk', - 67108864: 'LLVMDIFlagNonTrivial', - 134217728: 'LLVMDIFlagBigEndian', - 268435456: 'LLVMDIFlagLittleEndian', - 36: 'LLVMDIFlagIndirectVirtualBase', - 3: 'LLVMDIFlagAccessibility', - 196608: 'LLVMDIFlagPtrToMemberRep', -} -LLVMDIFlagZero = 0 -LLVMDIFlagPrivate = 1 -LLVMDIFlagProtected = 2 -LLVMDIFlagPublic = 3 -LLVMDIFlagFwdDecl = 4 -LLVMDIFlagAppleBlock = 8 -LLVMDIFlagReservedBit4 = 16 -LLVMDIFlagVirtual = 32 -LLVMDIFlagArtificial = 64 -LLVMDIFlagExplicit = 128 -LLVMDIFlagPrototyped = 256 -LLVMDIFlagObjcClassComplete = 512 -LLVMDIFlagObjectPointer = 1024 -LLVMDIFlagVector = 2048 -LLVMDIFlagStaticMember = 4096 -LLVMDIFlagLValueReference = 8192 -LLVMDIFlagRValueReference = 16384 -LLVMDIFlagReserved = 32768 -LLVMDIFlagSingleInheritance = 65536 -LLVMDIFlagMultipleInheritance = 131072 -LLVMDIFlagVirtualInheritance = 196608 -LLVMDIFlagIntroducedVirtual = 262144 -LLVMDIFlagBitField = 524288 -LLVMDIFlagNoReturn = 1048576 -LLVMDIFlagTypePassByValue = 4194304 -LLVMDIFlagTypePassByReference = 8388608 -LLVMDIFlagEnumClass = 16777216 -LLVMDIFlagFixedEnum = 16777216 -LLVMDIFlagThunk = 33554432 -LLVMDIFlagNonTrivial = 67108864 -LLVMDIFlagBigEndian = 134217728 -LLVMDIFlagLittleEndian = 268435456 -LLVMDIFlagIndirectVirtualBase = 36 -LLVMDIFlagAccessibility = 3 -LLVMDIFlagPtrToMemberRep = 196608 -c__EA_LLVMDIFlags = ctypes.c_uint32 # enum -LLVMDIFlags = c__EA_LLVMDIFlags -LLVMDIFlags__enumvalues = c__EA_LLVMDIFlags__enumvalues +# unsigned int LLVMGetEnumAttributeKind(LLVMAttributeRef A) +try: (LLVMGetEnumAttributeKind:=dll.LLVMGetEnumAttributeKind).restype, LLVMGetEnumAttributeKind.argtypes = ctypes.c_uint32, [LLVMAttributeRef] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMDWARFSourceLanguage' -c__EA_LLVMDWARFSourceLanguage__enumvalues = { - 0: 'LLVMDWARFSourceLanguageC89', - 1: 'LLVMDWARFSourceLanguageC', - 2: 'LLVMDWARFSourceLanguageAda83', - 3: 'LLVMDWARFSourceLanguageC_plus_plus', - 4: 'LLVMDWARFSourceLanguageCobol74', - 5: 'LLVMDWARFSourceLanguageCobol85', - 6: 'LLVMDWARFSourceLanguageFortran77', - 7: 'LLVMDWARFSourceLanguageFortran90', - 8: 'LLVMDWARFSourceLanguagePascal83', - 9: 'LLVMDWARFSourceLanguageModula2', - 10: 'LLVMDWARFSourceLanguageJava', - 11: 'LLVMDWARFSourceLanguageC99', - 12: 'LLVMDWARFSourceLanguageAda95', - 13: 'LLVMDWARFSourceLanguageFortran95', - 14: 'LLVMDWARFSourceLanguagePLI', - 15: 'LLVMDWARFSourceLanguageObjC', - 16: 'LLVMDWARFSourceLanguageObjC_plus_plus', - 17: 'LLVMDWARFSourceLanguageUPC', - 18: 'LLVMDWARFSourceLanguageD', - 19: 'LLVMDWARFSourceLanguagePython', - 20: 'LLVMDWARFSourceLanguageOpenCL', - 21: 'LLVMDWARFSourceLanguageGo', - 22: 'LLVMDWARFSourceLanguageModula3', - 23: 'LLVMDWARFSourceLanguageHaskell', - 24: 'LLVMDWARFSourceLanguageC_plus_plus_03', - 25: 'LLVMDWARFSourceLanguageC_plus_plus_11', - 26: 'LLVMDWARFSourceLanguageOCaml', - 27: 'LLVMDWARFSourceLanguageRust', - 28: 'LLVMDWARFSourceLanguageC11', - 29: 'LLVMDWARFSourceLanguageSwift', - 30: 'LLVMDWARFSourceLanguageJulia', - 31: 'LLVMDWARFSourceLanguageDylan', - 32: 'LLVMDWARFSourceLanguageC_plus_plus_14', - 33: 'LLVMDWARFSourceLanguageFortran03', - 34: 'LLVMDWARFSourceLanguageFortran08', - 35: 'LLVMDWARFSourceLanguageRenderScript', - 36: 'LLVMDWARFSourceLanguageBLISS', - 37: 'LLVMDWARFSourceLanguageMips_Assembler', - 38: 'LLVMDWARFSourceLanguageGOOGLE_RenderScript', - 39: 'LLVMDWARFSourceLanguageBORLAND_Delphi', -} -LLVMDWARFSourceLanguageC89 = 0 -LLVMDWARFSourceLanguageC = 1 -LLVMDWARFSourceLanguageAda83 = 2 -LLVMDWARFSourceLanguageC_plus_plus = 3 -LLVMDWARFSourceLanguageCobol74 = 4 -LLVMDWARFSourceLanguageCobol85 = 5 -LLVMDWARFSourceLanguageFortran77 = 6 -LLVMDWARFSourceLanguageFortran90 = 7 -LLVMDWARFSourceLanguagePascal83 = 8 -LLVMDWARFSourceLanguageModula2 = 9 -LLVMDWARFSourceLanguageJava = 10 -LLVMDWARFSourceLanguageC99 = 11 -LLVMDWARFSourceLanguageAda95 = 12 -LLVMDWARFSourceLanguageFortran95 = 13 -LLVMDWARFSourceLanguagePLI = 14 -LLVMDWARFSourceLanguageObjC = 15 -LLVMDWARFSourceLanguageObjC_plus_plus = 16 -LLVMDWARFSourceLanguageUPC = 17 -LLVMDWARFSourceLanguageD = 18 -LLVMDWARFSourceLanguagePython = 19 -LLVMDWARFSourceLanguageOpenCL = 20 -LLVMDWARFSourceLanguageGo = 21 -LLVMDWARFSourceLanguageModula3 = 22 -LLVMDWARFSourceLanguageHaskell = 23 -LLVMDWARFSourceLanguageC_plus_plus_03 = 24 -LLVMDWARFSourceLanguageC_plus_plus_11 = 25 -LLVMDWARFSourceLanguageOCaml = 26 -LLVMDWARFSourceLanguageRust = 27 -LLVMDWARFSourceLanguageC11 = 28 -LLVMDWARFSourceLanguageSwift = 29 -LLVMDWARFSourceLanguageJulia = 30 -LLVMDWARFSourceLanguageDylan = 31 -LLVMDWARFSourceLanguageC_plus_plus_14 = 32 -LLVMDWARFSourceLanguageFortran03 = 33 -LLVMDWARFSourceLanguageFortran08 = 34 -LLVMDWARFSourceLanguageRenderScript = 35 -LLVMDWARFSourceLanguageBLISS = 36 -LLVMDWARFSourceLanguageMips_Assembler = 37 -LLVMDWARFSourceLanguageGOOGLE_RenderScript = 38 -LLVMDWARFSourceLanguageBORLAND_Delphi = 39 -c__EA_LLVMDWARFSourceLanguage = ctypes.c_uint32 # enum -LLVMDWARFSourceLanguage = c__EA_LLVMDWARFSourceLanguage -LLVMDWARFSourceLanguage__enumvalues = c__EA_LLVMDWARFSourceLanguage__enumvalues +# uint64_t LLVMGetEnumAttributeValue(LLVMAttributeRef A) +try: (LLVMGetEnumAttributeValue:=dll.LLVMGetEnumAttributeValue).restype, LLVMGetEnumAttributeValue.argtypes = uint64_t, [LLVMAttributeRef] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMDWARFEmissionKind' -c__EA_LLVMDWARFEmissionKind__enumvalues = { - 0: 'LLVMDWARFEmissionNone', - 1: 'LLVMDWARFEmissionFull', - 2: 'LLVMDWARFEmissionLineTablesOnly', -} -LLVMDWARFEmissionNone = 0 -LLVMDWARFEmissionFull = 1 -LLVMDWARFEmissionLineTablesOnly = 2 -c__EA_LLVMDWARFEmissionKind = ctypes.c_uint32 # enum -LLVMDWARFEmissionKind = c__EA_LLVMDWARFEmissionKind -LLVMDWARFEmissionKind__enumvalues = c__EA_LLVMDWARFEmissionKind__enumvalues +class struct_LLVMOpaqueType(Struct): pass +LLVMTypeRef = ctypes.POINTER(struct_LLVMOpaqueType) +# LLVMAttributeRef LLVMCreateTypeAttribute(LLVMContextRef C, unsigned int KindID, LLVMTypeRef type_ref) +try: (LLVMCreateTypeAttribute:=dll.LLVMCreateTypeAttribute).restype, LLVMCreateTypeAttribute.argtypes = LLVMAttributeRef, [LLVMContextRef, ctypes.c_uint32, LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetTypeAttributeValue(LLVMAttributeRef A) +try: (LLVMGetTypeAttributeValue:=dll.LLVMGetTypeAttributeValue).restype, LLVMGetTypeAttributeValue.argtypes = LLVMTypeRef, [LLVMAttributeRef] +except AttributeError: pass + +# LLVMAttributeRef LLVMCreateConstantRangeAttribute(LLVMContextRef C, unsigned int KindID, unsigned int NumBits, const uint64_t LowerWords[], const uint64_t UpperWords[]) +try: (LLVMCreateConstantRangeAttribute:=dll.LLVMCreateConstantRangeAttribute).restype, LLVMCreateConstantRangeAttribute.argtypes = LLVMAttributeRef, [LLVMContextRef, ctypes.c_uint32, ctypes.c_uint32, (uint64_t * 0), (uint64_t * 0)] +except AttributeError: pass + +# LLVMAttributeRef LLVMCreateStringAttribute(LLVMContextRef C, const char *K, unsigned int KLength, const char *V, unsigned int VLength) +try: (LLVMCreateStringAttribute:=dll.LLVMCreateStringAttribute).restype, LLVMCreateStringAttribute.argtypes = LLVMAttributeRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# const char *LLVMGetStringAttributeKind(LLVMAttributeRef A, unsigned int *Length) +try: (LLVMGetStringAttributeKind:=dll.LLVMGetStringAttributeKind).restype, LLVMGetStringAttributeKind.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMAttributeRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# const char *LLVMGetStringAttributeValue(LLVMAttributeRef A, unsigned int *Length) +try: (LLVMGetStringAttributeValue:=dll.LLVMGetStringAttributeValue).restype, LLVMGetStringAttributeValue.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMAttributeRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# LLVMBool LLVMIsEnumAttribute(LLVMAttributeRef A) +try: (LLVMIsEnumAttribute:=dll.LLVMIsEnumAttribute).restype, LLVMIsEnumAttribute.argtypes = LLVMBool, [LLVMAttributeRef] +except AttributeError: pass + +# LLVMBool LLVMIsStringAttribute(LLVMAttributeRef A) +try: (LLVMIsStringAttribute:=dll.LLVMIsStringAttribute).restype, LLVMIsStringAttribute.argtypes = LLVMBool, [LLVMAttributeRef] +except AttributeError: pass + +# LLVMBool LLVMIsTypeAttribute(LLVMAttributeRef A) +try: (LLVMIsTypeAttribute:=dll.LLVMIsTypeAttribute).restype, LLVMIsTypeAttribute.argtypes = LLVMBool, [LLVMAttributeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetTypeByName2(LLVMContextRef C, const char *Name) +try: (LLVMGetTypeByName2:=dll.LLVMGetTypeByName2).restype, LLVMGetTypeByName2.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMModuleRef LLVMModuleCreateWithName(const char *ModuleID) +try: (LLVMModuleCreateWithName:=dll.LLVMModuleCreateWithName).restype, LLVMModuleCreateWithName.argtypes = LLVMModuleRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMModuleRef LLVMModuleCreateWithNameInContext(const char *ModuleID, LLVMContextRef C) +try: (LLVMModuleCreateWithNameInContext:=dll.LLVMModuleCreateWithNameInContext).restype, LLVMModuleCreateWithNameInContext.argtypes = LLVMModuleRef, [ctypes.POINTER(ctypes.c_char), LLVMContextRef] +except AttributeError: pass + +# LLVMModuleRef LLVMCloneModule(LLVMModuleRef M) +try: (LLVMCloneModule:=dll.LLVMCloneModule).restype, LLVMCloneModule.argtypes = LLVMModuleRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMDisposeModule(LLVMModuleRef M) +try: (LLVMDisposeModule:=dll.LLVMDisposeModule).restype, LLVMDisposeModule.argtypes = None, [LLVMModuleRef] +except AttributeError: pass + +# LLVMBool LLVMIsNewDbgInfoFormat(LLVMModuleRef M) +try: (LLVMIsNewDbgInfoFormat:=dll.LLVMIsNewDbgInfoFormat).restype, LLVMIsNewDbgInfoFormat.argtypes = LLVMBool, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetIsNewDbgInfoFormat(LLVMModuleRef M, LLVMBool UseNewFormat) +try: (LLVMSetIsNewDbgInfoFormat:=dll.LLVMSetIsNewDbgInfoFormat).restype, LLVMSetIsNewDbgInfoFormat.argtypes = None, [LLVMModuleRef, LLVMBool] +except AttributeError: pass + +# const char *LLVMGetModuleIdentifier(LLVMModuleRef M, size_t *Len) +try: (LLVMGetModuleIdentifier:=dll.LLVMGetModuleIdentifier).restype, LLVMGetModuleIdentifier.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMSetModuleIdentifier(LLVMModuleRef M, const char *Ident, size_t Len) +try: (LLVMSetModuleIdentifier:=dll.LLVMSetModuleIdentifier).restype, LLVMSetModuleIdentifier.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# const char *LLVMGetSourceFileName(LLVMModuleRef M, size_t *Len) +try: (LLVMGetSourceFileName:=dll.LLVMGetSourceFileName).restype, LLVMGetSourceFileName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMSetSourceFileName(LLVMModuleRef M, const char *Name, size_t Len) +try: (LLVMSetSourceFileName:=dll.LLVMSetSourceFileName).restype, LLVMSetSourceFileName.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# const char *LLVMGetDataLayoutStr(LLVMModuleRef M) +try: (LLVMGetDataLayoutStr:=dll.LLVMGetDataLayoutStr).restype, LLVMGetDataLayoutStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef] +except AttributeError: pass + +# const char *LLVMGetDataLayout(LLVMModuleRef M) +try: (LLVMGetDataLayout:=dll.LLVMGetDataLayout).restype, LLVMGetDataLayout.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetDataLayout(LLVMModuleRef M, const char *DataLayoutStr) +try: (LLVMSetDataLayout:=dll.LLVMSetDataLayout).restype, LLVMSetDataLayout.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const char *LLVMGetTarget(LLVMModuleRef M) +try: (LLVMGetTarget:=dll.LLVMGetTarget).restype, LLVMGetTarget.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetTarget(LLVMModuleRef M, const char *Triple) +try: (LLVMSetTarget:=dll.LLVMSetTarget).restype, LLVMSetTarget.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class struct_LLVMOpaqueModuleFlagEntry(Struct): pass +LLVMModuleFlagEntry = struct_LLVMOpaqueModuleFlagEntry +# LLVMModuleFlagEntry *LLVMCopyModuleFlagsMetadata(LLVMModuleRef M, size_t *Len) +try: (LLVMCopyModuleFlagsMetadata:=dll.LLVMCopyModuleFlagsMetadata).restype, LLVMCopyModuleFlagsMetadata.argtypes = ctypes.POINTER(LLVMModuleFlagEntry), [LLVMModuleRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMDisposeModuleFlagsMetadata(LLVMModuleFlagEntry *Entries) +try: (LLVMDisposeModuleFlagsMetadata:=dll.LLVMDisposeModuleFlagsMetadata).restype, LLVMDisposeModuleFlagsMetadata.argtypes = None, [ctypes.POINTER(LLVMModuleFlagEntry)] +except AttributeError: pass + +# LLVMModuleFlagBehavior LLVMModuleFlagEntriesGetFlagBehavior(LLVMModuleFlagEntry *Entries, unsigned int Index) +try: (LLVMModuleFlagEntriesGetFlagBehavior:=dll.LLVMModuleFlagEntriesGetFlagBehavior).restype, LLVMModuleFlagEntriesGetFlagBehavior.argtypes = LLVMModuleFlagBehavior, [ctypes.POINTER(LLVMModuleFlagEntry), ctypes.c_uint32] +except AttributeError: pass + +# const char *LLVMModuleFlagEntriesGetKey(LLVMModuleFlagEntry *Entries, unsigned int Index, size_t *Len) +try: (LLVMModuleFlagEntriesGetKey:=dll.LLVMModuleFlagEntriesGetKey).restype, LLVMModuleFlagEntriesGetKey.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(LLVMModuleFlagEntry), ctypes.c_uint32, ctypes.POINTER(size_t)] +except AttributeError: pass + +class struct_LLVMOpaqueMetadata(Struct): pass +LLVMMetadataRef = ctypes.POINTER(struct_LLVMOpaqueMetadata) +# LLVMMetadataRef LLVMModuleFlagEntriesGetMetadata(LLVMModuleFlagEntry *Entries, unsigned int Index) +try: (LLVMModuleFlagEntriesGetMetadata:=dll.LLVMModuleFlagEntriesGetMetadata).restype, LLVMModuleFlagEntriesGetMetadata.argtypes = LLVMMetadataRef, [ctypes.POINTER(LLVMModuleFlagEntry), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMGetModuleFlag(LLVMModuleRef M, const char *Key, size_t KeyLen) +try: (LLVMGetModuleFlag:=dll.LLVMGetModuleFlag).restype, LLVMGetModuleFlag.argtypes = LLVMMetadataRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# void LLVMAddModuleFlag(LLVMModuleRef M, LLVMModuleFlagBehavior Behavior, const char *Key, size_t KeyLen, LLVMMetadataRef Val) +try: (LLVMAddModuleFlag:=dll.LLVMAddModuleFlag).restype, LLVMAddModuleFlag.argtypes = None, [LLVMModuleRef, LLVMModuleFlagBehavior, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef] +except AttributeError: pass + +# void LLVMDumpModule(LLVMModuleRef M) +try: (LLVMDumpModule:=dll.LLVMDumpModule).restype, LLVMDumpModule.argtypes = None, [LLVMModuleRef] +except AttributeError: pass + +# LLVMBool LLVMPrintModuleToFile(LLVMModuleRef M, const char *Filename, char **ErrorMessage) +try: (LLVMPrintModuleToFile:=dll.LLVMPrintModuleToFile).restype, LLVMPrintModuleToFile.argtypes = LLVMBool, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# char *LLVMPrintModuleToString(LLVMModuleRef M) +try: (LLVMPrintModuleToString:=dll.LLVMPrintModuleToString).restype, LLVMPrintModuleToString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef] +except AttributeError: pass + +# const char *LLVMGetModuleInlineAsm(LLVMModuleRef M, size_t *Len) +try: (LLVMGetModuleInlineAsm:=dll.LLVMGetModuleInlineAsm).restype, LLVMGetModuleInlineAsm.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMSetModuleInlineAsm2(LLVMModuleRef M, const char *Asm, size_t Len) +try: (LLVMSetModuleInlineAsm2:=dll.LLVMSetModuleInlineAsm2).restype, LLVMSetModuleInlineAsm2.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# void LLVMAppendModuleInlineAsm(LLVMModuleRef M, const char *Asm, size_t Len) +try: (LLVMAppendModuleInlineAsm:=dll.LLVMAppendModuleInlineAsm).restype, LLVMAppendModuleInlineAsm.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMValueRef LLVMGetInlineAsm(LLVMTypeRef Ty, const char *AsmString, size_t AsmStringSize, const char *Constraints, size_t ConstraintsSize, LLVMBool HasSideEffects, LLVMBool IsAlignStack, LLVMInlineAsmDialect Dialect, LLVMBool CanThrow) +try: (LLVMGetInlineAsm:=dll.LLVMGetInlineAsm).restype, LLVMGetInlineAsm.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool, LLVMBool, LLVMInlineAsmDialect, LLVMBool] +except AttributeError: pass + +# const char *LLVMGetInlineAsmAsmString(LLVMValueRef InlineAsmVal, size_t *Len) +try: (LLVMGetInlineAsmAsmString:=dll.LLVMGetInlineAsmAsmString).restype, LLVMGetInlineAsmAsmString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# const char *LLVMGetInlineAsmConstraintString(LLVMValueRef InlineAsmVal, size_t *Len) +try: (LLVMGetInlineAsmConstraintString:=dll.LLVMGetInlineAsmConstraintString).restype, LLVMGetInlineAsmConstraintString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# LLVMInlineAsmDialect LLVMGetInlineAsmDialect(LLVMValueRef InlineAsmVal) +try: (LLVMGetInlineAsmDialect:=dll.LLVMGetInlineAsmDialect).restype, LLVMGetInlineAsmDialect.argtypes = LLVMInlineAsmDialect, [LLVMValueRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetInlineAsmFunctionType(LLVMValueRef InlineAsmVal) +try: (LLVMGetInlineAsmFunctionType:=dll.LLVMGetInlineAsmFunctionType).restype, LLVMGetInlineAsmFunctionType.argtypes = LLVMTypeRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMGetInlineAsmHasSideEffects(LLVMValueRef InlineAsmVal) +try: (LLVMGetInlineAsmHasSideEffects:=dll.LLVMGetInlineAsmHasSideEffects).restype, LLVMGetInlineAsmHasSideEffects.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMGetInlineAsmNeedsAlignedStack(LLVMValueRef InlineAsmVal) +try: (LLVMGetInlineAsmNeedsAlignedStack:=dll.LLVMGetInlineAsmNeedsAlignedStack).restype, LLVMGetInlineAsmNeedsAlignedStack.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMGetInlineAsmCanUnwind(LLVMValueRef InlineAsmVal) +try: (LLVMGetInlineAsmCanUnwind:=dll.LLVMGetInlineAsmCanUnwind).restype, LLVMGetInlineAsmCanUnwind.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMContextRef LLVMGetModuleContext(LLVMModuleRef M) +try: (LLVMGetModuleContext:=dll.LLVMGetModuleContext).restype, LLVMGetModuleContext.argtypes = LLVMContextRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetTypeByName(LLVMModuleRef M, const char *Name) +try: (LLVMGetTypeByName:=dll.LLVMGetTypeByName).restype, LLVMGetTypeByName.argtypes = LLVMTypeRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class struct_LLVMOpaqueNamedMDNode(Struct): pass +LLVMNamedMDNodeRef = ctypes.POINTER(struct_LLVMOpaqueNamedMDNode) +# LLVMNamedMDNodeRef LLVMGetFirstNamedMetadata(LLVMModuleRef M) +try: (LLVMGetFirstNamedMetadata:=dll.LLVMGetFirstNamedMetadata).restype, LLVMGetFirstNamedMetadata.argtypes = LLVMNamedMDNodeRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMNamedMDNodeRef LLVMGetLastNamedMetadata(LLVMModuleRef M) +try: (LLVMGetLastNamedMetadata:=dll.LLVMGetLastNamedMetadata).restype, LLVMGetLastNamedMetadata.argtypes = LLVMNamedMDNodeRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMNamedMDNodeRef LLVMGetNextNamedMetadata(LLVMNamedMDNodeRef NamedMDNode) +try: (LLVMGetNextNamedMetadata:=dll.LLVMGetNextNamedMetadata).restype, LLVMGetNextNamedMetadata.argtypes = LLVMNamedMDNodeRef, [LLVMNamedMDNodeRef] +except AttributeError: pass + +# LLVMNamedMDNodeRef LLVMGetPreviousNamedMetadata(LLVMNamedMDNodeRef NamedMDNode) +try: (LLVMGetPreviousNamedMetadata:=dll.LLVMGetPreviousNamedMetadata).restype, LLVMGetPreviousNamedMetadata.argtypes = LLVMNamedMDNodeRef, [LLVMNamedMDNodeRef] +except AttributeError: pass + +# LLVMNamedMDNodeRef LLVMGetNamedMetadata(LLVMModuleRef M, const char *Name, size_t NameLen) +try: (LLVMGetNamedMetadata:=dll.LLVMGetNamedMetadata).restype, LLVMGetNamedMetadata.argtypes = LLVMNamedMDNodeRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMNamedMDNodeRef LLVMGetOrInsertNamedMetadata(LLVMModuleRef M, const char *Name, size_t NameLen) +try: (LLVMGetOrInsertNamedMetadata:=dll.LLVMGetOrInsertNamedMetadata).restype, LLVMGetOrInsertNamedMetadata.argtypes = LLVMNamedMDNodeRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# const char *LLVMGetNamedMetadataName(LLVMNamedMDNodeRef NamedMD, size_t *NameLen) +try: (LLVMGetNamedMetadataName:=dll.LLVMGetNamedMetadataName).restype, LLVMGetNamedMetadataName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMNamedMDNodeRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# unsigned int LLVMGetNamedMetadataNumOperands(LLVMModuleRef M, const char *Name) +try: (LLVMGetNamedMetadataNumOperands:=dll.LLVMGetNamedMetadataNumOperands).restype, LLVMGetNamedMetadataNumOperands.argtypes = ctypes.c_uint32, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMGetNamedMetadataOperands(LLVMModuleRef M, const char *Name, LLVMValueRef *Dest) +try: (LLVMGetNamedMetadataOperands:=dll.LLVMGetNamedMetadataOperands).restype, LLVMGetNamedMetadataOperands.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMValueRef)] +except AttributeError: pass + +# void LLVMAddNamedMetadataOperand(LLVMModuleRef M, const char *Name, LLVMValueRef Val) +try: (LLVMAddNamedMetadataOperand:=dll.LLVMAddNamedMetadataOperand).restype, LLVMAddNamedMetadataOperand.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMValueRef] +except AttributeError: pass + +# const char *LLVMGetDebugLocDirectory(LLVMValueRef Val, unsigned int *Length) +try: (LLVMGetDebugLocDirectory:=dll.LLVMGetDebugLocDirectory).restype, LLVMGetDebugLocDirectory.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# const char *LLVMGetDebugLocFilename(LLVMValueRef Val, unsigned int *Length) +try: (LLVMGetDebugLocFilename:=dll.LLVMGetDebugLocFilename).restype, LLVMGetDebugLocFilename.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# unsigned int LLVMGetDebugLocLine(LLVMValueRef Val) +try: (LLVMGetDebugLocLine:=dll.LLVMGetDebugLocLine).restype, LLVMGetDebugLocLine.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMGetDebugLocColumn(LLVMValueRef Val) +try: (LLVMGetDebugLocColumn:=dll.LLVMGetDebugLocColumn).restype, LLVMGetDebugLocColumn.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMAddFunction(LLVMModuleRef M, const char *Name, LLVMTypeRef FunctionTy) +try: (LLVMAddFunction:=dll.LLVMAddFunction).restype, LLVMAddFunction.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNamedFunction(LLVMModuleRef M, const char *Name) +try: (LLVMGetNamedFunction:=dll.LLVMGetNamedFunction).restype, LLVMGetNamedFunction.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMGetNamedFunctionWithLength(LLVMModuleRef M, const char *Name, size_t Length) +try: (LLVMGetNamedFunctionWithLength:=dll.LLVMGetNamedFunctionWithLength).restype, LLVMGetNamedFunctionWithLength.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMValueRef LLVMGetFirstFunction(LLVMModuleRef M) +try: (LLVMGetFirstFunction:=dll.LLVMGetFirstFunction).restype, LLVMGetFirstFunction.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetLastFunction(LLVMModuleRef M) +try: (LLVMGetLastFunction:=dll.LLVMGetLastFunction).restype, LLVMGetLastFunction.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNextFunction(LLVMValueRef Fn) +try: (LLVMGetNextFunction:=dll.LLVMGetNextFunction).restype, LLVMGetNextFunction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPreviousFunction(LLVMValueRef Fn) +try: (LLVMGetPreviousFunction:=dll.LLVMGetPreviousFunction).restype, LLVMGetPreviousFunction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm) +try: (LLVMSetModuleInlineAsm:=dll.LLVMSetModuleInlineAsm).restype, LLVMSetModuleInlineAsm.argtypes = None, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMTypeKind LLVMGetTypeKind(LLVMTypeRef Ty) +try: (LLVMGetTypeKind:=dll.LLVMGetTypeKind).restype, LLVMGetTypeKind.argtypes = LLVMTypeKind, [LLVMTypeRef] +except AttributeError: pass + +# LLVMBool LLVMTypeIsSized(LLVMTypeRef Ty) +try: (LLVMTypeIsSized:=dll.LLVMTypeIsSized).restype, LLVMTypeIsSized.argtypes = LLVMBool, [LLVMTypeRef] +except AttributeError: pass + +# LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty) +try: (LLVMGetTypeContext:=dll.LLVMGetTypeContext).restype, LLVMGetTypeContext.argtypes = LLVMContextRef, [LLVMTypeRef] +except AttributeError: pass + +# void LLVMDumpType(LLVMTypeRef Val) +try: (LLVMDumpType:=dll.LLVMDumpType).restype, LLVMDumpType.argtypes = None, [LLVMTypeRef] +except AttributeError: pass + +# char *LLVMPrintTypeToString(LLVMTypeRef Val) +try: (LLVMPrintTypeToString:=dll.LLVMPrintTypeToString).restype, LLVMPrintTypeToString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMInt1TypeInContext(LLVMContextRef C) +try: (LLVMInt1TypeInContext:=dll.LLVMInt1TypeInContext).restype, LLVMInt1TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMInt8TypeInContext(LLVMContextRef C) +try: (LLVMInt8TypeInContext:=dll.LLVMInt8TypeInContext).restype, LLVMInt8TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMInt16TypeInContext(LLVMContextRef C) +try: (LLVMInt16TypeInContext:=dll.LLVMInt16TypeInContext).restype, LLVMInt16TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMInt32TypeInContext(LLVMContextRef C) +try: (LLVMInt32TypeInContext:=dll.LLVMInt32TypeInContext).restype, LLVMInt32TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMInt64TypeInContext(LLVMContextRef C) +try: (LLVMInt64TypeInContext:=dll.LLVMInt64TypeInContext).restype, LLVMInt64TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMInt128TypeInContext(LLVMContextRef C) +try: (LLVMInt128TypeInContext:=dll.LLVMInt128TypeInContext).restype, LLVMInt128TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntTypeInContext(LLVMContextRef C, unsigned int NumBits) +try: (LLVMIntTypeInContext:=dll.LLVMIntTypeInContext).restype, LLVMIntTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMInt1Type(void) +try: (LLVMInt1Type:=dll.LLVMInt1Type).restype, LLVMInt1Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMInt8Type(void) +try: (LLVMInt8Type:=dll.LLVMInt8Type).restype, LLVMInt8Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMInt16Type(void) +try: (LLVMInt16Type:=dll.LLVMInt16Type).restype, LLVMInt16Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMInt32Type(void) +try: (LLVMInt32Type:=dll.LLVMInt32Type).restype, LLVMInt32Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMInt64Type(void) +try: (LLVMInt64Type:=dll.LLVMInt64Type).restype, LLVMInt64Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMInt128Type(void) +try: (LLVMInt128Type:=dll.LLVMInt128Type).restype, LLVMInt128Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMIntType(unsigned int NumBits) +try: (LLVMIntType:=dll.LLVMIntType).restype, LLVMIntType.argtypes = LLVMTypeRef, [ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetIntTypeWidth(LLVMTypeRef IntegerTy) +try: (LLVMGetIntTypeWidth:=dll.LLVMGetIntTypeWidth).restype, LLVMGetIntTypeWidth.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMHalfTypeInContext(LLVMContextRef C) +try: (LLVMHalfTypeInContext:=dll.LLVMHalfTypeInContext).restype, LLVMHalfTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMBFloatTypeInContext(LLVMContextRef C) +try: (LLVMBFloatTypeInContext:=dll.LLVMBFloatTypeInContext).restype, LLVMBFloatTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMFloatTypeInContext(LLVMContextRef C) +try: (LLVMFloatTypeInContext:=dll.LLVMFloatTypeInContext).restype, LLVMFloatTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMDoubleTypeInContext(LLVMContextRef C) +try: (LLVMDoubleTypeInContext:=dll.LLVMDoubleTypeInContext).restype, LLVMDoubleTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMX86FP80TypeInContext(LLVMContextRef C) +try: (LLVMX86FP80TypeInContext:=dll.LLVMX86FP80TypeInContext).restype, LLVMX86FP80TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMFP128TypeInContext(LLVMContextRef C) +try: (LLVMFP128TypeInContext:=dll.LLVMFP128TypeInContext).restype, LLVMFP128TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMPPCFP128TypeInContext(LLVMContextRef C) +try: (LLVMPPCFP128TypeInContext:=dll.LLVMPPCFP128TypeInContext).restype, LLVMPPCFP128TypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMHalfType(void) +try: (LLVMHalfType:=dll.LLVMHalfType).restype, LLVMHalfType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMBFloatType(void) +try: (LLVMBFloatType:=dll.LLVMBFloatType).restype, LLVMBFloatType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMFloatType(void) +try: (LLVMFloatType:=dll.LLVMFloatType).restype, LLVMFloatType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMDoubleType(void) +try: (LLVMDoubleType:=dll.LLVMDoubleType).restype, LLVMDoubleType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMX86FP80Type(void) +try: (LLVMX86FP80Type:=dll.LLVMX86FP80Type).restype, LLVMX86FP80Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMFP128Type(void) +try: (LLVMFP128Type:=dll.LLVMFP128Type).restype, LLVMFP128Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMPPCFP128Type(void) +try: (LLVMPPCFP128Type:=dll.LLVMPPCFP128Type).restype, LLVMPPCFP128Type.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMFunctionType(LLVMTypeRef ReturnType, LLVMTypeRef *ParamTypes, unsigned int ParamCount, LLVMBool IsVarArg) +try: (LLVMFunctionType:=dll.LLVMFunctionType).restype, LLVMFunctionType.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.POINTER(LLVMTypeRef), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMIsFunctionVarArg(LLVMTypeRef FunctionTy) +try: (LLVMIsFunctionVarArg:=dll.LLVMIsFunctionVarArg).restype, LLVMIsFunctionVarArg.argtypes = LLVMBool, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetReturnType(LLVMTypeRef FunctionTy) +try: (LLVMGetReturnType:=dll.LLVMGetReturnType).restype, LLVMGetReturnType.argtypes = LLVMTypeRef, [LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCountParamTypes(LLVMTypeRef FunctionTy) +try: (LLVMCountParamTypes:=dll.LLVMCountParamTypes).restype, LLVMCountParamTypes.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# void LLVMGetParamTypes(LLVMTypeRef FunctionTy, LLVMTypeRef *Dest) +try: (LLVMGetParamTypes:=dll.LLVMGetParamTypes).restype, LLVMGetParamTypes.argtypes = None, [LLVMTypeRef, ctypes.POINTER(LLVMTypeRef)] +except AttributeError: pass + +# LLVMTypeRef LLVMStructTypeInContext(LLVMContextRef C, LLVMTypeRef *ElementTypes, unsigned int ElementCount, LLVMBool Packed) +try: (LLVMStructTypeInContext:=dll.LLVMStructTypeInContext).restype, LLVMStructTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.POINTER(LLVMTypeRef), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMTypeRef LLVMStructType(LLVMTypeRef *ElementTypes, unsigned int ElementCount, LLVMBool Packed) +try: (LLVMStructType:=dll.LLVMStructType).restype, LLVMStructType.argtypes = LLVMTypeRef, [ctypes.POINTER(LLVMTypeRef), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMTypeRef LLVMStructCreateNamed(LLVMContextRef C, const char *Name) +try: (LLVMStructCreateNamed:=dll.LLVMStructCreateNamed).restype, LLVMStructCreateNamed.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const char *LLVMGetStructName(LLVMTypeRef Ty) +try: (LLVMGetStructName:=dll.LLVMGetStructName).restype, LLVMGetStructName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTypeRef] +except AttributeError: pass + +# void LLVMStructSetBody(LLVMTypeRef StructTy, LLVMTypeRef *ElementTypes, unsigned int ElementCount, LLVMBool Packed) +try: (LLVMStructSetBody:=dll.LLVMStructSetBody).restype, LLVMStructSetBody.argtypes = None, [LLVMTypeRef, ctypes.POINTER(LLVMTypeRef), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# unsigned int LLVMCountStructElementTypes(LLVMTypeRef StructTy) +try: (LLVMCountStructElementTypes:=dll.LLVMCountStructElementTypes).restype, LLVMCountStructElementTypes.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# void LLVMGetStructElementTypes(LLVMTypeRef StructTy, LLVMTypeRef *Dest) +try: (LLVMGetStructElementTypes:=dll.LLVMGetStructElementTypes).restype, LLVMGetStructElementTypes.argtypes = None, [LLVMTypeRef, ctypes.POINTER(LLVMTypeRef)] +except AttributeError: pass + +# LLVMTypeRef LLVMStructGetTypeAtIndex(LLVMTypeRef StructTy, unsigned int i) +try: (LLVMStructGetTypeAtIndex:=dll.LLVMStructGetTypeAtIndex).restype, LLVMStructGetTypeAtIndex.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMBool LLVMIsPackedStruct(LLVMTypeRef StructTy) +try: (LLVMIsPackedStruct:=dll.LLVMIsPackedStruct).restype, LLVMIsPackedStruct.argtypes = LLVMBool, [LLVMTypeRef] +except AttributeError: pass + +# LLVMBool LLVMIsOpaqueStruct(LLVMTypeRef StructTy) +try: (LLVMIsOpaqueStruct:=dll.LLVMIsOpaqueStruct).restype, LLVMIsOpaqueStruct.argtypes = LLVMBool, [LLVMTypeRef] +except AttributeError: pass + +# LLVMBool LLVMIsLiteralStruct(LLVMTypeRef StructTy) +try: (LLVMIsLiteralStruct:=dll.LLVMIsLiteralStruct).restype, LLVMIsLiteralStruct.argtypes = LLVMBool, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetElementType(LLVMTypeRef Ty) +try: (LLVMGetElementType:=dll.LLVMGetElementType).restype, LLVMGetElementType.argtypes = LLVMTypeRef, [LLVMTypeRef] +except AttributeError: pass + +# void LLVMGetSubtypes(LLVMTypeRef Tp, LLVMTypeRef *Arr) +try: (LLVMGetSubtypes:=dll.LLVMGetSubtypes).restype, LLVMGetSubtypes.argtypes = None, [LLVMTypeRef, ctypes.POINTER(LLVMTypeRef)] +except AttributeError: pass + +# unsigned int LLVMGetNumContainedTypes(LLVMTypeRef Tp) +try: (LLVMGetNumContainedTypes:=dll.LLVMGetNumContainedTypes).restype, LLVMGetNumContainedTypes.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMArrayType(LLVMTypeRef ElementType, unsigned int ElementCount) +try: (LLVMArrayType:=dll.LLVMArrayType).restype, LLVMArrayType.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMArrayType2(LLVMTypeRef ElementType, uint64_t ElementCount) +try: (LLVMArrayType2:=dll.LLVMArrayType2).restype, LLVMArrayType2.argtypes = LLVMTypeRef, [LLVMTypeRef, uint64_t] +except AttributeError: pass + +# unsigned int LLVMGetArrayLength(LLVMTypeRef ArrayTy) +try: (LLVMGetArrayLength:=dll.LLVMGetArrayLength).restype, LLVMGetArrayLength.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# uint64_t LLVMGetArrayLength2(LLVMTypeRef ArrayTy) +try: (LLVMGetArrayLength2:=dll.LLVMGetArrayLength2).restype, LLVMGetArrayLength2.argtypes = uint64_t, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMPointerType(LLVMTypeRef ElementType, unsigned int AddressSpace) +try: (LLVMPointerType:=dll.LLVMPointerType).restype, LLVMPointerType.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMBool LLVMPointerTypeIsOpaque(LLVMTypeRef Ty) +try: (LLVMPointerTypeIsOpaque:=dll.LLVMPointerTypeIsOpaque).restype, LLVMPointerTypeIsOpaque.argtypes = LLVMBool, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMPointerTypeInContext(LLVMContextRef C, unsigned int AddressSpace) +try: (LLVMPointerTypeInContext:=dll.LLVMPointerTypeInContext).restype, LLVMPointerTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetPointerAddressSpace(LLVMTypeRef PointerTy) +try: (LLVMGetPointerAddressSpace:=dll.LLVMGetPointerAddressSpace).restype, LLVMGetPointerAddressSpace.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned int ElementCount) +try: (LLVMVectorType:=dll.LLVMVectorType).restype, LLVMVectorType.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMScalableVectorType(LLVMTypeRef ElementType, unsigned int ElementCount) +try: (LLVMScalableVectorType:=dll.LLVMScalableVectorType).restype, LLVMScalableVectorType.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetVectorSize(LLVMTypeRef VectorTy) +try: (LLVMGetVectorSize:=dll.LLVMGetVectorSize).restype, LLVMGetVectorSize.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetConstantPtrAuthPointer(LLVMValueRef PtrAuth) +try: (LLVMGetConstantPtrAuthPointer:=dll.LLVMGetConstantPtrAuthPointer).restype, LLVMGetConstantPtrAuthPointer.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetConstantPtrAuthKey(LLVMValueRef PtrAuth) +try: (LLVMGetConstantPtrAuthKey:=dll.LLVMGetConstantPtrAuthKey).restype, LLVMGetConstantPtrAuthKey.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetConstantPtrAuthDiscriminator(LLVMValueRef PtrAuth) +try: (LLVMGetConstantPtrAuthDiscriminator:=dll.LLVMGetConstantPtrAuthDiscriminator).restype, LLVMGetConstantPtrAuthDiscriminator.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetConstantPtrAuthAddrDiscriminator(LLVMValueRef PtrAuth) +try: (LLVMGetConstantPtrAuthAddrDiscriminator:=dll.LLVMGetConstantPtrAuthAddrDiscriminator).restype, LLVMGetConstantPtrAuthAddrDiscriminator.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMTypeRef LLVMVoidTypeInContext(LLVMContextRef C) +try: (LLVMVoidTypeInContext:=dll.LLVMVoidTypeInContext).restype, LLVMVoidTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMLabelTypeInContext(LLVMContextRef C) +try: (LLVMLabelTypeInContext:=dll.LLVMLabelTypeInContext).restype, LLVMLabelTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMX86AMXTypeInContext(LLVMContextRef C) +try: (LLVMX86AMXTypeInContext:=dll.LLVMX86AMXTypeInContext).restype, LLVMX86AMXTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMTokenTypeInContext(LLVMContextRef C) +try: (LLVMTokenTypeInContext:=dll.LLVMTokenTypeInContext).restype, LLVMTokenTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMMetadataTypeInContext(LLVMContextRef C) +try: (LLVMMetadataTypeInContext:=dll.LLVMMetadataTypeInContext).restype, LLVMMetadataTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMTypeRef LLVMVoidType(void) +try: (LLVMVoidType:=dll.LLVMVoidType).restype, LLVMVoidType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMLabelType(void) +try: (LLVMLabelType:=dll.LLVMLabelType).restype, LLVMLabelType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMX86AMXType(void) +try: (LLVMX86AMXType:=dll.LLVMX86AMXType).restype, LLVMX86AMXType.argtypes = LLVMTypeRef, [] +except AttributeError: pass + +# LLVMTypeRef LLVMTargetExtTypeInContext(LLVMContextRef C, const char *Name, LLVMTypeRef *TypeParams, unsigned int TypeParamCount, unsigned int *IntParams, unsigned int IntParamCount) +try: (LLVMTargetExtTypeInContext:=dll.LLVMTargetExtTypeInContext).restype, LLVMTargetExtTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTypeRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] +except AttributeError: pass + +# const char *LLVMGetTargetExtTypeName(LLVMTypeRef TargetExtTy) +try: (LLVMGetTargetExtTypeName:=dll.LLVMGetTargetExtTypeName).restype, LLVMGetTargetExtTypeName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMGetTargetExtTypeNumTypeParams(LLVMTypeRef TargetExtTy) +try: (LLVMGetTargetExtTypeNumTypeParams:=dll.LLVMGetTargetExtTypeNumTypeParams).restype, LLVMGetTargetExtTypeNumTypeParams.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetTargetExtTypeTypeParam(LLVMTypeRef TargetExtTy, unsigned int Idx) +try: (LLVMGetTargetExtTypeTypeParam:=dll.LLVMGetTargetExtTypeTypeParam).restype, LLVMGetTargetExtTypeTypeParam.argtypes = LLVMTypeRef, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetTargetExtTypeNumIntParams(LLVMTypeRef TargetExtTy) +try: (LLVMGetTargetExtTypeNumIntParams:=dll.LLVMGetTargetExtTypeNumIntParams).restype, LLVMGetTargetExtTypeNumIntParams.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMGetTargetExtTypeIntParam(LLVMTypeRef TargetExtTy, unsigned int Idx) +try: (LLVMGetTargetExtTypeIntParam:=dll.LLVMGetTargetExtTypeIntParam).restype, LLVMGetTargetExtTypeIntParam.argtypes = ctypes.c_uint32, [LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMTypeOf(LLVMValueRef Val) +try: (LLVMTypeOf:=dll.LLVMTypeOf).restype, LLVMTypeOf.argtypes = LLVMTypeRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueKind LLVMGetValueKind(LLVMValueRef Val) +try: (LLVMGetValueKind:=dll.LLVMGetValueKind).restype, LLVMGetValueKind.argtypes = LLVMValueKind, [LLVMValueRef] +except AttributeError: pass + +# const char *LLVMGetValueName2(LLVMValueRef Val, size_t *Length) +try: (LLVMGetValueName2:=dll.LLVMGetValueName2).restype, LLVMGetValueName2.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMSetValueName2(LLVMValueRef Val, const char *Name, size_t NameLen) +try: (LLVMSetValueName2:=dll.LLVMSetValueName2).restype, LLVMSetValueName2.argtypes = None, [LLVMValueRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# void LLVMDumpValue(LLVMValueRef Val) +try: (LLVMDumpValue:=dll.LLVMDumpValue).restype, LLVMDumpValue.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# char *LLVMPrintValueToString(LLVMValueRef Val) +try: (LLVMPrintValueToString:=dll.LLVMPrintValueToString).restype, LLVMPrintValueToString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef] +except AttributeError: pass + +# LLVMContextRef LLVMGetValueContext(LLVMValueRef Val) +try: (LLVMGetValueContext:=dll.LLVMGetValueContext).restype, LLVMGetValueContext.argtypes = LLVMContextRef, [LLVMValueRef] +except AttributeError: pass + +class struct_LLVMOpaqueDbgRecord(Struct): pass +LLVMDbgRecordRef = ctypes.POINTER(struct_LLVMOpaqueDbgRecord) +# char *LLVMPrintDbgRecordToString(LLVMDbgRecordRef Record) +try: (LLVMPrintDbgRecordToString:=dll.LLVMPrintDbgRecordToString).restype, LLVMPrintDbgRecordToString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMDbgRecordRef] +except AttributeError: pass + +# void LLVMReplaceAllUsesWith(LLVMValueRef OldVal, LLVMValueRef NewVal) +try: (LLVMReplaceAllUsesWith:=dll.LLVMReplaceAllUsesWith).restype, LLVMReplaceAllUsesWith.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsConstant(LLVMValueRef Val) +try: (LLVMIsConstant:=dll.LLVMIsConstant).restype, LLVMIsConstant.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsUndef(LLVMValueRef Val) +try: (LLVMIsUndef:=dll.LLVMIsUndef).restype, LLVMIsUndef.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsPoison(LLVMValueRef Val) +try: (LLVMIsPoison:=dll.LLVMIsPoison).restype, LLVMIsPoison.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAArgument(LLVMValueRef Val) +try: (LLVMIsAArgument:=dll.LLVMIsAArgument).restype, LLVMIsAArgument.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsABasicBlock(LLVMValueRef Val) +try: (LLVMIsABasicBlock:=dll.LLVMIsABasicBlock).restype, LLVMIsABasicBlock.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAInlineAsm(LLVMValueRef Val) +try: (LLVMIsAInlineAsm:=dll.LLVMIsAInlineAsm).restype, LLVMIsAInlineAsm.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAUser(LLVMValueRef Val) +try: (LLVMIsAUser:=dll.LLVMIsAUser).restype, LLVMIsAUser.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstant(LLVMValueRef Val) +try: (LLVMIsAConstant:=dll.LLVMIsAConstant).restype, LLVMIsAConstant.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsABlockAddress(LLVMValueRef Val) +try: (LLVMIsABlockAddress:=dll.LLVMIsABlockAddress).restype, LLVMIsABlockAddress.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantAggregateZero(LLVMValueRef Val) +try: (LLVMIsAConstantAggregateZero:=dll.LLVMIsAConstantAggregateZero).restype, LLVMIsAConstantAggregateZero.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantArray(LLVMValueRef Val) +try: (LLVMIsAConstantArray:=dll.LLVMIsAConstantArray).restype, LLVMIsAConstantArray.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantDataSequential(LLVMValueRef Val) +try: (LLVMIsAConstantDataSequential:=dll.LLVMIsAConstantDataSequential).restype, LLVMIsAConstantDataSequential.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantDataArray(LLVMValueRef Val) +try: (LLVMIsAConstantDataArray:=dll.LLVMIsAConstantDataArray).restype, LLVMIsAConstantDataArray.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantDataVector(LLVMValueRef Val) +try: (LLVMIsAConstantDataVector:=dll.LLVMIsAConstantDataVector).restype, LLVMIsAConstantDataVector.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantExpr(LLVMValueRef Val) +try: (LLVMIsAConstantExpr:=dll.LLVMIsAConstantExpr).restype, LLVMIsAConstantExpr.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantFP(LLVMValueRef Val) +try: (LLVMIsAConstantFP:=dll.LLVMIsAConstantFP).restype, LLVMIsAConstantFP.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantInt(LLVMValueRef Val) +try: (LLVMIsAConstantInt:=dll.LLVMIsAConstantInt).restype, LLVMIsAConstantInt.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantPointerNull(LLVMValueRef Val) +try: (LLVMIsAConstantPointerNull:=dll.LLVMIsAConstantPointerNull).restype, LLVMIsAConstantPointerNull.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantStruct(LLVMValueRef Val) +try: (LLVMIsAConstantStruct:=dll.LLVMIsAConstantStruct).restype, LLVMIsAConstantStruct.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantTokenNone(LLVMValueRef Val) +try: (LLVMIsAConstantTokenNone:=dll.LLVMIsAConstantTokenNone).restype, LLVMIsAConstantTokenNone.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantVector(LLVMValueRef Val) +try: (LLVMIsAConstantVector:=dll.LLVMIsAConstantVector).restype, LLVMIsAConstantVector.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAConstantPtrAuth(LLVMValueRef Val) +try: (LLVMIsAConstantPtrAuth:=dll.LLVMIsAConstantPtrAuth).restype, LLVMIsAConstantPtrAuth.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAGlobalValue(LLVMValueRef Val) +try: (LLVMIsAGlobalValue:=dll.LLVMIsAGlobalValue).restype, LLVMIsAGlobalValue.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAGlobalAlias(LLVMValueRef Val) +try: (LLVMIsAGlobalAlias:=dll.LLVMIsAGlobalAlias).restype, LLVMIsAGlobalAlias.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAGlobalObject(LLVMValueRef Val) +try: (LLVMIsAGlobalObject:=dll.LLVMIsAGlobalObject).restype, LLVMIsAGlobalObject.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFunction(LLVMValueRef Val) +try: (LLVMIsAFunction:=dll.LLVMIsAFunction).restype, LLVMIsAFunction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAGlobalVariable(LLVMValueRef Val) +try: (LLVMIsAGlobalVariable:=dll.LLVMIsAGlobalVariable).restype, LLVMIsAGlobalVariable.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAGlobalIFunc(LLVMValueRef Val) +try: (LLVMIsAGlobalIFunc:=dll.LLVMIsAGlobalIFunc).restype, LLVMIsAGlobalIFunc.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAUndefValue(LLVMValueRef Val) +try: (LLVMIsAUndefValue:=dll.LLVMIsAUndefValue).restype, LLVMIsAUndefValue.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAPoisonValue(LLVMValueRef Val) +try: (LLVMIsAPoisonValue:=dll.LLVMIsAPoisonValue).restype, LLVMIsAPoisonValue.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAInstruction(LLVMValueRef Val) +try: (LLVMIsAInstruction:=dll.LLVMIsAInstruction).restype, LLVMIsAInstruction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAUnaryOperator(LLVMValueRef Val) +try: (LLVMIsAUnaryOperator:=dll.LLVMIsAUnaryOperator).restype, LLVMIsAUnaryOperator.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsABinaryOperator(LLVMValueRef Val) +try: (LLVMIsABinaryOperator:=dll.LLVMIsABinaryOperator).restype, LLVMIsABinaryOperator.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACallInst(LLVMValueRef Val) +try: (LLVMIsACallInst:=dll.LLVMIsACallInst).restype, LLVMIsACallInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAIntrinsicInst(LLVMValueRef Val) +try: (LLVMIsAIntrinsicInst:=dll.LLVMIsAIntrinsicInst).restype, LLVMIsAIntrinsicInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsADbgInfoIntrinsic(LLVMValueRef Val) +try: (LLVMIsADbgInfoIntrinsic:=dll.LLVMIsADbgInfoIntrinsic).restype, LLVMIsADbgInfoIntrinsic.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsADbgVariableIntrinsic(LLVMValueRef Val) +try: (LLVMIsADbgVariableIntrinsic:=dll.LLVMIsADbgVariableIntrinsic).restype, LLVMIsADbgVariableIntrinsic.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsADbgDeclareInst(LLVMValueRef Val) +try: (LLVMIsADbgDeclareInst:=dll.LLVMIsADbgDeclareInst).restype, LLVMIsADbgDeclareInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsADbgLabelInst(LLVMValueRef Val) +try: (LLVMIsADbgLabelInst:=dll.LLVMIsADbgLabelInst).restype, LLVMIsADbgLabelInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAMemIntrinsic(LLVMValueRef Val) +try: (LLVMIsAMemIntrinsic:=dll.LLVMIsAMemIntrinsic).restype, LLVMIsAMemIntrinsic.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAMemCpyInst(LLVMValueRef Val) +try: (LLVMIsAMemCpyInst:=dll.LLVMIsAMemCpyInst).restype, LLVMIsAMemCpyInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAMemMoveInst(LLVMValueRef Val) +try: (LLVMIsAMemMoveInst:=dll.LLVMIsAMemMoveInst).restype, LLVMIsAMemMoveInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAMemSetInst(LLVMValueRef Val) +try: (LLVMIsAMemSetInst:=dll.LLVMIsAMemSetInst).restype, LLVMIsAMemSetInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACmpInst(LLVMValueRef Val) +try: (LLVMIsACmpInst:=dll.LLVMIsACmpInst).restype, LLVMIsACmpInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFCmpInst(LLVMValueRef Val) +try: (LLVMIsAFCmpInst:=dll.LLVMIsAFCmpInst).restype, LLVMIsAFCmpInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAICmpInst(LLVMValueRef Val) +try: (LLVMIsAICmpInst:=dll.LLVMIsAICmpInst).restype, LLVMIsAICmpInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAExtractElementInst(LLVMValueRef Val) +try: (LLVMIsAExtractElementInst:=dll.LLVMIsAExtractElementInst).restype, LLVMIsAExtractElementInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAGetElementPtrInst(LLVMValueRef Val) +try: (LLVMIsAGetElementPtrInst:=dll.LLVMIsAGetElementPtrInst).restype, LLVMIsAGetElementPtrInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAInsertElementInst(LLVMValueRef Val) +try: (LLVMIsAInsertElementInst:=dll.LLVMIsAInsertElementInst).restype, LLVMIsAInsertElementInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAInsertValueInst(LLVMValueRef Val) +try: (LLVMIsAInsertValueInst:=dll.LLVMIsAInsertValueInst).restype, LLVMIsAInsertValueInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsALandingPadInst(LLVMValueRef Val) +try: (LLVMIsALandingPadInst:=dll.LLVMIsALandingPadInst).restype, LLVMIsALandingPadInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAPHINode(LLVMValueRef Val) +try: (LLVMIsAPHINode:=dll.LLVMIsAPHINode).restype, LLVMIsAPHINode.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsASelectInst(LLVMValueRef Val) +try: (LLVMIsASelectInst:=dll.LLVMIsASelectInst).restype, LLVMIsASelectInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAShuffleVectorInst(LLVMValueRef Val) +try: (LLVMIsAShuffleVectorInst:=dll.LLVMIsAShuffleVectorInst).restype, LLVMIsAShuffleVectorInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAStoreInst(LLVMValueRef Val) +try: (LLVMIsAStoreInst:=dll.LLVMIsAStoreInst).restype, LLVMIsAStoreInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsABranchInst(LLVMValueRef Val) +try: (LLVMIsABranchInst:=dll.LLVMIsABranchInst).restype, LLVMIsABranchInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAIndirectBrInst(LLVMValueRef Val) +try: (LLVMIsAIndirectBrInst:=dll.LLVMIsAIndirectBrInst).restype, LLVMIsAIndirectBrInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAInvokeInst(LLVMValueRef Val) +try: (LLVMIsAInvokeInst:=dll.LLVMIsAInvokeInst).restype, LLVMIsAInvokeInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAReturnInst(LLVMValueRef Val) +try: (LLVMIsAReturnInst:=dll.LLVMIsAReturnInst).restype, LLVMIsAReturnInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsASwitchInst(LLVMValueRef Val) +try: (LLVMIsASwitchInst:=dll.LLVMIsASwitchInst).restype, LLVMIsASwitchInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAUnreachableInst(LLVMValueRef Val) +try: (LLVMIsAUnreachableInst:=dll.LLVMIsAUnreachableInst).restype, LLVMIsAUnreachableInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAResumeInst(LLVMValueRef Val) +try: (LLVMIsAResumeInst:=dll.LLVMIsAResumeInst).restype, LLVMIsAResumeInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACleanupReturnInst(LLVMValueRef Val) +try: (LLVMIsACleanupReturnInst:=dll.LLVMIsACleanupReturnInst).restype, LLVMIsACleanupReturnInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACatchReturnInst(LLVMValueRef Val) +try: (LLVMIsACatchReturnInst:=dll.LLVMIsACatchReturnInst).restype, LLVMIsACatchReturnInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACatchSwitchInst(LLVMValueRef Val) +try: (LLVMIsACatchSwitchInst:=dll.LLVMIsACatchSwitchInst).restype, LLVMIsACatchSwitchInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACallBrInst(LLVMValueRef Val) +try: (LLVMIsACallBrInst:=dll.LLVMIsACallBrInst).restype, LLVMIsACallBrInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFuncletPadInst(LLVMValueRef Val) +try: (LLVMIsAFuncletPadInst:=dll.LLVMIsAFuncletPadInst).restype, LLVMIsAFuncletPadInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACatchPadInst(LLVMValueRef Val) +try: (LLVMIsACatchPadInst:=dll.LLVMIsACatchPadInst).restype, LLVMIsACatchPadInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACleanupPadInst(LLVMValueRef Val) +try: (LLVMIsACleanupPadInst:=dll.LLVMIsACleanupPadInst).restype, LLVMIsACleanupPadInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAUnaryInstruction(LLVMValueRef Val) +try: (LLVMIsAUnaryInstruction:=dll.LLVMIsAUnaryInstruction).restype, LLVMIsAUnaryInstruction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAAllocaInst(LLVMValueRef Val) +try: (LLVMIsAAllocaInst:=dll.LLVMIsAAllocaInst).restype, LLVMIsAAllocaInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsACastInst(LLVMValueRef Val) +try: (LLVMIsACastInst:=dll.LLVMIsACastInst).restype, LLVMIsACastInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAAddrSpaceCastInst(LLVMValueRef Val) +try: (LLVMIsAAddrSpaceCastInst:=dll.LLVMIsAAddrSpaceCastInst).restype, LLVMIsAAddrSpaceCastInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsABitCastInst(LLVMValueRef Val) +try: (LLVMIsABitCastInst:=dll.LLVMIsABitCastInst).restype, LLVMIsABitCastInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFPExtInst(LLVMValueRef Val) +try: (LLVMIsAFPExtInst:=dll.LLVMIsAFPExtInst).restype, LLVMIsAFPExtInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFPToSIInst(LLVMValueRef Val) +try: (LLVMIsAFPToSIInst:=dll.LLVMIsAFPToSIInst).restype, LLVMIsAFPToSIInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFPToUIInst(LLVMValueRef Val) +try: (LLVMIsAFPToUIInst:=dll.LLVMIsAFPToUIInst).restype, LLVMIsAFPToUIInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFPTruncInst(LLVMValueRef Val) +try: (LLVMIsAFPTruncInst:=dll.LLVMIsAFPTruncInst).restype, LLVMIsAFPTruncInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAIntToPtrInst(LLVMValueRef Val) +try: (LLVMIsAIntToPtrInst:=dll.LLVMIsAIntToPtrInst).restype, LLVMIsAIntToPtrInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAPtrToIntInst(LLVMValueRef Val) +try: (LLVMIsAPtrToIntInst:=dll.LLVMIsAPtrToIntInst).restype, LLVMIsAPtrToIntInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsASExtInst(LLVMValueRef Val) +try: (LLVMIsASExtInst:=dll.LLVMIsASExtInst).restype, LLVMIsASExtInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsASIToFPInst(LLVMValueRef Val) +try: (LLVMIsASIToFPInst:=dll.LLVMIsASIToFPInst).restype, LLVMIsASIToFPInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsATruncInst(LLVMValueRef Val) +try: (LLVMIsATruncInst:=dll.LLVMIsATruncInst).restype, LLVMIsATruncInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAUIToFPInst(LLVMValueRef Val) +try: (LLVMIsAUIToFPInst:=dll.LLVMIsAUIToFPInst).restype, LLVMIsAUIToFPInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAZExtInst(LLVMValueRef Val) +try: (LLVMIsAZExtInst:=dll.LLVMIsAZExtInst).restype, LLVMIsAZExtInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAExtractValueInst(LLVMValueRef Val) +try: (LLVMIsAExtractValueInst:=dll.LLVMIsAExtractValueInst).restype, LLVMIsAExtractValueInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsALoadInst(LLVMValueRef Val) +try: (LLVMIsALoadInst:=dll.LLVMIsALoadInst).restype, LLVMIsALoadInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAVAArgInst(LLVMValueRef Val) +try: (LLVMIsAVAArgInst:=dll.LLVMIsAVAArgInst).restype, LLVMIsAVAArgInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFreezeInst(LLVMValueRef Val) +try: (LLVMIsAFreezeInst:=dll.LLVMIsAFreezeInst).restype, LLVMIsAFreezeInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAAtomicCmpXchgInst(LLVMValueRef Val) +try: (LLVMIsAAtomicCmpXchgInst:=dll.LLVMIsAAtomicCmpXchgInst).restype, LLVMIsAAtomicCmpXchgInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAAtomicRMWInst(LLVMValueRef Val) +try: (LLVMIsAAtomicRMWInst:=dll.LLVMIsAAtomicRMWInst).restype, LLVMIsAAtomicRMWInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAFenceInst(LLVMValueRef Val) +try: (LLVMIsAFenceInst:=dll.LLVMIsAFenceInst).restype, LLVMIsAFenceInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAMDNode(LLVMValueRef Val) +try: (LLVMIsAMDNode:=dll.LLVMIsAMDNode).restype, LLVMIsAMDNode.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAValueAsMetadata(LLVMValueRef Val) +try: (LLVMIsAValueAsMetadata:=dll.LLVMIsAValueAsMetadata).restype, LLVMIsAValueAsMetadata.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsAMDString(LLVMValueRef Val) +try: (LLVMIsAMDString:=dll.LLVMIsAMDString).restype, LLVMIsAMDString.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# const char *LLVMGetValueName(LLVMValueRef Val) +try: (LLVMGetValueName:=dll.LLVMGetValueName).restype, LLVMGetValueName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetValueName(LLVMValueRef Val, const char *Name) +try: (LLVMSetValueName:=dll.LLVMSetValueName).restype, LLVMSetValueName.argtypes = None, [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class struct_LLVMOpaqueUse(Struct): pass +LLVMUseRef = ctypes.POINTER(struct_LLVMOpaqueUse) +# LLVMUseRef LLVMGetFirstUse(LLVMValueRef Val) +try: (LLVMGetFirstUse:=dll.LLVMGetFirstUse).restype, LLVMGetFirstUse.argtypes = LLVMUseRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMUseRef LLVMGetNextUse(LLVMUseRef U) +try: (LLVMGetNextUse:=dll.LLVMGetNextUse).restype, LLVMGetNextUse.argtypes = LLVMUseRef, [LLVMUseRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetUser(LLVMUseRef U) +try: (LLVMGetUser:=dll.LLVMGetUser).restype, LLVMGetUser.argtypes = LLVMValueRef, [LLVMUseRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetUsedValue(LLVMUseRef U) +try: (LLVMGetUsedValue:=dll.LLVMGetUsedValue).restype, LLVMGetUsedValue.argtypes = LLVMValueRef, [LLVMUseRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetOperand(LLVMValueRef Val, unsigned int Index) +try: (LLVMGetOperand:=dll.LLVMGetOperand).restype, LLVMGetOperand.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMUseRef LLVMGetOperandUse(LLVMValueRef Val, unsigned int Index) +try: (LLVMGetOperandUse:=dll.LLVMGetOperandUse).restype, LLVMGetOperandUse.argtypes = LLVMUseRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMSetOperand(LLVMValueRef User, unsigned int Index, LLVMValueRef Val) +try: (LLVMSetOperand:=dll.LLVMSetOperand).restype, LLVMSetOperand.argtypes = None, [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] +except AttributeError: pass + +# int LLVMGetNumOperands(LLVMValueRef Val) +try: (LLVMGetNumOperands:=dll.LLVMGetNumOperands).restype, LLVMGetNumOperands.argtypes = ctypes.c_int32, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNull(LLVMTypeRef Ty) +try: (LLVMConstNull:=dll.LLVMConstNull).restype, LLVMConstNull.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstAllOnes(LLVMTypeRef Ty) +try: (LLVMConstAllOnes:=dll.LLVMConstAllOnes).restype, LLVMConstAllOnes.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetUndef(LLVMTypeRef Ty) +try: (LLVMGetUndef:=dll.LLVMGetUndef).restype, LLVMGetUndef.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPoison(LLVMTypeRef Ty) +try: (LLVMGetPoison:=dll.LLVMGetPoison).restype, LLVMGetPoison.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMBool LLVMIsNull(LLVMValueRef Val) +try: (LLVMIsNull:=dll.LLVMIsNull).restype, LLVMIsNull.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstPointerNull(LLVMTypeRef Ty) +try: (LLVMConstPointerNull:=dll.LLVMConstPointerNull).restype, LLVMConstPointerNull.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstInt(LLVMTypeRef IntTy, unsigned long long N, LLVMBool SignExtend) +try: (LLVMConstInt:=dll.LLVMConstInt).restype, LLVMConstInt.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.c_uint64, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMConstIntOfArbitraryPrecision(LLVMTypeRef IntTy, unsigned int NumWords, const uint64_t Words[]) +try: (LLVMConstIntOfArbitraryPrecision:=dll.LLVMConstIntOfArbitraryPrecision).restype, LLVMConstIntOfArbitraryPrecision.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.c_uint32, (uint64_t * 0)] +except AttributeError: pass + +uint8_t = ctypes.c_ubyte +# LLVMValueRef LLVMConstIntOfString(LLVMTypeRef IntTy, const char *Text, uint8_t Radix) +try: (LLVMConstIntOfString:=dll.LLVMConstIntOfString).restype, LLVMConstIntOfString.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), uint8_t] +except AttributeError: pass + +# LLVMValueRef LLVMConstIntOfStringAndSize(LLVMTypeRef IntTy, const char *Text, unsigned int SLen, uint8_t Radix) +try: (LLVMConstIntOfStringAndSize:=dll.LLVMConstIntOfStringAndSize).restype, LLVMConstIntOfStringAndSize.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, uint8_t] +except AttributeError: pass + +# LLVMValueRef LLVMConstReal(LLVMTypeRef RealTy, double N) +try: (LLVMConstReal:=dll.LLVMConstReal).restype, LLVMConstReal.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.c_double] +except AttributeError: pass + +# LLVMValueRef LLVMConstRealOfString(LLVMTypeRef RealTy, const char *Text) +try: (LLVMConstRealOfString:=dll.LLVMConstRealOfString).restype, LLVMConstRealOfString.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMConstRealOfStringAndSize(LLVMTypeRef RealTy, const char *Text, unsigned int SLen) +try: (LLVMConstRealOfStringAndSize:=dll.LLVMConstRealOfStringAndSize).restype, LLVMConstRealOfStringAndSize.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMConstIntGetZExtValue(LLVMValueRef ConstantVal) +try: (LLVMConstIntGetZExtValue:=dll.LLVMConstIntGetZExtValue).restype, LLVMConstIntGetZExtValue.argtypes = ctypes.c_uint64, [LLVMValueRef] +except AttributeError: pass + +# long long LLVMConstIntGetSExtValue(LLVMValueRef ConstantVal) +try: (LLVMConstIntGetSExtValue:=dll.LLVMConstIntGetSExtValue).restype, LLVMConstIntGetSExtValue.argtypes = ctypes.c_int64, [LLVMValueRef] +except AttributeError: pass + +# double LLVMConstRealGetDouble(LLVMValueRef ConstantVal, LLVMBool *losesInfo) +try: (LLVMConstRealGetDouble:=dll.LLVMConstRealGetDouble).restype, LLVMConstRealGetDouble.argtypes = ctypes.c_double, [LLVMValueRef, ctypes.POINTER(LLVMBool)] +except AttributeError: pass + +# LLVMValueRef LLVMConstStringInContext(LLVMContextRef C, const char *Str, unsigned int Length, LLVMBool DontNullTerminate) +try: (LLVMConstStringInContext:=dll.LLVMConstStringInContext).restype, LLVMConstStringInContext.argtypes = LLVMValueRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMConstStringInContext2(LLVMContextRef C, const char *Str, size_t Length, LLVMBool DontNullTerminate) +try: (LLVMConstStringInContext2:=dll.LLVMConstStringInContext2).restype, LLVMConstStringInContext2.argtypes = LLVMValueRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMConstString(const char *Str, unsigned int Length, LLVMBool DontNullTerminate) +try: (LLVMConstString:=dll.LLVMConstString).restype, LLVMConstString.argtypes = LLVMValueRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMIsConstantString(LLVMValueRef c) +try: (LLVMIsConstantString:=dll.LLVMIsConstantString).restype, LLVMIsConstantString.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# const char *LLVMGetAsString(LLVMValueRef c, size_t *Length) +try: (LLVMGetAsString:=dll.LLVMGetAsString).restype, LLVMGetAsString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# LLVMValueRef LLVMConstStructInContext(LLVMContextRef C, LLVMValueRef *ConstantVals, unsigned int Count, LLVMBool Packed) +try: (LLVMConstStructInContext:=dll.LLVMConstStructInContext).restype, LLVMConstStructInContext.argtypes = LLVMValueRef, [LLVMContextRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMConstStruct(LLVMValueRef *ConstantVals, unsigned int Count, LLVMBool Packed) +try: (LLVMConstStruct:=dll.LLVMConstStruct).restype, LLVMConstStruct.argtypes = LLVMValueRef, [ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMConstArray(LLVMTypeRef ElementTy, LLVMValueRef *ConstantVals, unsigned int Length) +try: (LLVMConstArray:=dll.LLVMConstArray).restype, LLVMConstArray.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMConstArray2(LLVMTypeRef ElementTy, LLVMValueRef *ConstantVals, uint64_t Length) +try: (LLVMConstArray2:=dll.LLVMConstArray2).restype, LLVMConstArray2.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(LLVMValueRef), uint64_t] +except AttributeError: pass + +# LLVMValueRef LLVMConstNamedStruct(LLVMTypeRef StructTy, LLVMValueRef *ConstantVals, unsigned int Count) +try: (LLVMConstNamedStruct:=dll.LLVMConstNamedStruct).restype, LLVMConstNamedStruct.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMGetAggregateElement(LLVMValueRef C, unsigned int Idx) +try: (LLVMGetAggregateElement:=dll.LLVMGetAggregateElement).restype, LLVMGetAggregateElement.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMGetElementAsConstant(LLVMValueRef C, unsigned int idx) __attribute__((deprecated("Use LLVMGetAggregateElement instead"))) +try: (LLVMGetElementAsConstant:=dll.LLVMGetElementAsConstant).restype, LLVMGetElementAsConstant.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMConstVector(LLVMValueRef *ScalarConstantVals, unsigned int Size) +try: (LLVMConstVector:=dll.LLVMConstVector).restype, LLVMConstVector.argtypes = LLVMValueRef, [ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMConstantPtrAuth(LLVMValueRef Ptr, LLVMValueRef Key, LLVMValueRef Disc, LLVMValueRef AddrDisc) +try: (LLVMConstantPtrAuth:=dll.LLVMConstantPtrAuth).restype, LLVMConstantPtrAuth.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMOpcode LLVMGetConstOpcode(LLVMValueRef ConstantVal) +try: (LLVMGetConstOpcode:=dll.LLVMGetConstOpcode).restype, LLVMGetConstOpcode.argtypes = LLVMOpcode, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMAlignOf(LLVMTypeRef Ty) +try: (LLVMAlignOf:=dll.LLVMAlignOf).restype, LLVMAlignOf.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMSizeOf(LLVMTypeRef Ty) +try: (LLVMSizeOf:=dll.LLVMSizeOf).restype, LLVMSizeOf.argtypes = LLVMValueRef, [LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNeg(LLVMValueRef ConstantVal) +try: (LLVMConstNeg:=dll.LLVMConstNeg).restype, LLVMConstNeg.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNSWNeg(LLVMValueRef ConstantVal) +try: (LLVMConstNSWNeg:=dll.LLVMConstNSWNeg).restype, LLVMConstNSWNeg.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNUWNeg(LLVMValueRef ConstantVal) __attribute__((deprecated("Use LLVMConstNull instead."))) +try: (LLVMConstNUWNeg:=dll.LLVMConstNUWNeg).restype, LLVMConstNUWNeg.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNot(LLVMValueRef ConstantVal) +try: (LLVMConstNot:=dll.LLVMConstNot).restype, LLVMConstNot.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstAdd:=dll.LLVMConstAdd).restype, LLVMConstAdd.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNSWAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstNSWAdd:=dll.LLVMConstNSWAdd).restype, LLVMConstNSWAdd.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNUWAdd(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstNUWAdd:=dll.LLVMConstNUWAdd).restype, LLVMConstNUWAdd.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstSub(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstSub:=dll.LLVMConstSub).restype, LLVMConstSub.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNSWSub(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstNSWSub:=dll.LLVMConstNSWSub).restype, LLVMConstNSWSub.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNUWSub(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstNUWSub:=dll.LLVMConstNUWSub).restype, LLVMConstNUWSub.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstMul(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstMul:=dll.LLVMConstMul).restype, LLVMConstMul.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNSWMul(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstNSWMul:=dll.LLVMConstNSWMul).restype, LLVMConstNSWMul.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstNUWMul(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstNUWMul:=dll.LLVMConstNUWMul).restype, LLVMConstNUWMul.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstXor(LLVMValueRef LHSConstant, LLVMValueRef RHSConstant) +try: (LLVMConstXor:=dll.LLVMConstXor).restype, LLVMConstXor.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstGEP2(LLVMTypeRef Ty, LLVMValueRef ConstantVal, LLVMValueRef *ConstantIndices, unsigned int NumIndices) +try: (LLVMConstGEP2:=dll.LLVMConstGEP2).restype, LLVMConstGEP2.argtypes = LLVMValueRef, [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMConstInBoundsGEP2(LLVMTypeRef Ty, LLVMValueRef ConstantVal, LLVMValueRef *ConstantIndices, unsigned int NumIndices) +try: (LLVMConstInBoundsGEP2:=dll.LLVMConstInBoundsGEP2).restype, LLVMConstInBoundsGEP2.argtypes = LLVMValueRef, [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMConstGEPWithNoWrapFlags(LLVMTypeRef Ty, LLVMValueRef ConstantVal, LLVMValueRef *ConstantIndices, unsigned int NumIndices, LLVMGEPNoWrapFlags NoWrapFlags) +try: (LLVMConstGEPWithNoWrapFlags:=dll.LLVMConstGEPWithNoWrapFlags).restype, LLVMConstGEPWithNoWrapFlags.argtypes = LLVMValueRef, [LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, LLVMGEPNoWrapFlags] +except AttributeError: pass + +# LLVMValueRef LLVMConstTrunc(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstTrunc:=dll.LLVMConstTrunc).restype, LLVMConstTrunc.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstPtrToInt(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstPtrToInt:=dll.LLVMConstPtrToInt).restype, LLVMConstPtrToInt.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstIntToPtr(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstIntToPtr:=dll.LLVMConstIntToPtr).restype, LLVMConstIntToPtr.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstBitCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstBitCast:=dll.LLVMConstBitCast).restype, LLVMConstBitCast.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstAddrSpaceCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstAddrSpaceCast:=dll.LLVMConstAddrSpaceCast).restype, LLVMConstAddrSpaceCast.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstTruncOrBitCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstTruncOrBitCast:=dll.LLVMConstTruncOrBitCast).restype, LLVMConstTruncOrBitCast.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstPointerCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType) +try: (LLVMConstPointerCast:=dll.LLVMConstPointerCast).restype, LLVMConstPointerCast.argtypes = LLVMValueRef, [LLVMValueRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstExtractElement(LLVMValueRef VectorConstant, LLVMValueRef IndexConstant) +try: (LLVMConstExtractElement:=dll.LLVMConstExtractElement).restype, LLVMConstExtractElement.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstInsertElement(LLVMValueRef VectorConstant, LLVMValueRef ElementValueConstant, LLVMValueRef IndexConstant) +try: (LLVMConstInsertElement:=dll.LLVMConstInsertElement).restype, LLVMConstInsertElement.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstShuffleVector(LLVMValueRef VectorAConstant, LLVMValueRef VectorBConstant, LLVMValueRef MaskConstant) +try: (LLVMConstShuffleVector:=dll.LLVMConstShuffleVector).restype, LLVMConstShuffleVector.argtypes = LLVMValueRef, [LLVMValueRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +class struct_LLVMOpaqueBasicBlock(Struct): pass +LLVMBasicBlockRef = ctypes.POINTER(struct_LLVMOpaqueBasicBlock) +# LLVMValueRef LLVMBlockAddress(LLVMValueRef F, LLVMBasicBlockRef BB) +try: (LLVMBlockAddress:=dll.LLVMBlockAddress).restype, LLVMBlockAddress.argtypes = LLVMValueRef, [LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetBlockAddressFunction(LLVMValueRef BlockAddr) +try: (LLVMGetBlockAddressFunction:=dll.LLVMGetBlockAddressFunction).restype, LLVMGetBlockAddressFunction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetBlockAddressBasicBlock(LLVMValueRef BlockAddr) +try: (LLVMGetBlockAddressBasicBlock:=dll.LLVMGetBlockAddressBasicBlock).restype, LLVMGetBlockAddressBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMConstInlineAsm(LLVMTypeRef Ty, const char *AsmString, const char *Constraints, LLVMBool HasSideEffects, LLVMBool IsAlignStack) +try: (LLVMConstInlineAsm:=dll.LLVMConstInlineAsm).restype, LLVMConstInlineAsm.argtypes = LLVMValueRef, [LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMBool, LLVMBool] +except AttributeError: pass + +# LLVMModuleRef LLVMGetGlobalParent(LLVMValueRef Global) +try: (LLVMGetGlobalParent:=dll.LLVMGetGlobalParent).restype, LLVMGetGlobalParent.argtypes = LLVMModuleRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsDeclaration(LLVMValueRef Global) +try: (LLVMIsDeclaration:=dll.LLVMIsDeclaration).restype, LLVMIsDeclaration.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMLinkage LLVMGetLinkage(LLVMValueRef Global) +try: (LLVMGetLinkage:=dll.LLVMGetLinkage).restype, LLVMGetLinkage.argtypes = LLVMLinkage, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetLinkage(LLVMValueRef Global, LLVMLinkage Linkage) +try: (LLVMSetLinkage:=dll.LLVMSetLinkage).restype, LLVMSetLinkage.argtypes = None, [LLVMValueRef, LLVMLinkage] +except AttributeError: pass + +# const char *LLVMGetSection(LLVMValueRef Global) +try: (LLVMGetSection:=dll.LLVMGetSection).restype, LLVMGetSection.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetSection(LLVMValueRef Global, const char *Section) +try: (LLVMSetSection:=dll.LLVMSetSection).restype, LLVMSetSection.argtypes = None, [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMVisibility LLVMGetVisibility(LLVMValueRef Global) +try: (LLVMGetVisibility:=dll.LLVMGetVisibility).restype, LLVMGetVisibility.argtypes = LLVMVisibility, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetVisibility(LLVMValueRef Global, LLVMVisibility Viz) +try: (LLVMSetVisibility:=dll.LLVMSetVisibility).restype, LLVMSetVisibility.argtypes = None, [LLVMValueRef, LLVMVisibility] +except AttributeError: pass + +# LLVMDLLStorageClass LLVMGetDLLStorageClass(LLVMValueRef Global) +try: (LLVMGetDLLStorageClass:=dll.LLVMGetDLLStorageClass).restype, LLVMGetDLLStorageClass.argtypes = LLVMDLLStorageClass, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetDLLStorageClass(LLVMValueRef Global, LLVMDLLStorageClass Class) +try: (LLVMSetDLLStorageClass:=dll.LLVMSetDLLStorageClass).restype, LLVMSetDLLStorageClass.argtypes = None, [LLVMValueRef, LLVMDLLStorageClass] +except AttributeError: pass + +# LLVMUnnamedAddr LLVMGetUnnamedAddress(LLVMValueRef Global) +try: (LLVMGetUnnamedAddress:=dll.LLVMGetUnnamedAddress).restype, LLVMGetUnnamedAddress.argtypes = LLVMUnnamedAddr, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetUnnamedAddress(LLVMValueRef Global, LLVMUnnamedAddr UnnamedAddr) +try: (LLVMSetUnnamedAddress:=dll.LLVMSetUnnamedAddress).restype, LLVMSetUnnamedAddress.argtypes = None, [LLVMValueRef, LLVMUnnamedAddr] +except AttributeError: pass + +# LLVMTypeRef LLVMGlobalGetValueType(LLVMValueRef Global) +try: (LLVMGlobalGetValueType:=dll.LLVMGlobalGetValueType).restype, LLVMGlobalGetValueType.argtypes = LLVMTypeRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMHasUnnamedAddr(LLVMValueRef Global) +try: (LLVMHasUnnamedAddr:=dll.LLVMHasUnnamedAddr).restype, LLVMHasUnnamedAddr.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetUnnamedAddr(LLVMValueRef Global, LLVMBool HasUnnamedAddr) +try: (LLVMSetUnnamedAddr:=dll.LLVMSetUnnamedAddr).restype, LLVMSetUnnamedAddr.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# unsigned int LLVMGetAlignment(LLVMValueRef V) +try: (LLVMGetAlignment:=dll.LLVMGetAlignment).restype, LLVMGetAlignment.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetAlignment(LLVMValueRef V, unsigned int Bytes) +try: (LLVMSetAlignment:=dll.LLVMSetAlignment).restype, LLVMSetAlignment.argtypes = None, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMGlobalSetMetadata(LLVMValueRef Global, unsigned int Kind, LLVMMetadataRef MD) +try: (LLVMGlobalSetMetadata:=dll.LLVMGlobalSetMetadata).restype, LLVMGlobalSetMetadata.argtypes = None, [LLVMValueRef, ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass + +# void LLVMGlobalEraseMetadata(LLVMValueRef Global, unsigned int Kind) +try: (LLVMGlobalEraseMetadata:=dll.LLVMGlobalEraseMetadata).restype, LLVMGlobalEraseMetadata.argtypes = None, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMGlobalClearMetadata(LLVMValueRef Global) +try: (LLVMGlobalClearMetadata:=dll.LLVMGlobalClearMetadata).restype, LLVMGlobalClearMetadata.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +class struct_LLVMOpaqueValueMetadataEntry(Struct): pass +LLVMValueMetadataEntry = struct_LLVMOpaqueValueMetadataEntry +# LLVMValueMetadataEntry *LLVMGlobalCopyAllMetadata(LLVMValueRef Value, size_t *NumEntries) +try: (LLVMGlobalCopyAllMetadata:=dll.LLVMGlobalCopyAllMetadata).restype, LLVMGlobalCopyAllMetadata.argtypes = ctypes.POINTER(LLVMValueMetadataEntry), [LLVMValueRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMDisposeValueMetadataEntries(LLVMValueMetadataEntry *Entries) +try: (LLVMDisposeValueMetadataEntries:=dll.LLVMDisposeValueMetadataEntries).restype, LLVMDisposeValueMetadataEntries.argtypes = None, [ctypes.POINTER(LLVMValueMetadataEntry)] +except AttributeError: pass + +# unsigned int LLVMValueMetadataEntriesGetKind(LLVMValueMetadataEntry *Entries, unsigned int Index) +try: (LLVMValueMetadataEntriesGetKind:=dll.LLVMValueMetadataEntriesGetKind).restype, LLVMValueMetadataEntriesGetKind.argtypes = ctypes.c_uint32, [ctypes.POINTER(LLVMValueMetadataEntry), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMValueMetadataEntriesGetMetadata(LLVMValueMetadataEntry *Entries, unsigned int Index) +try: (LLVMValueMetadataEntriesGetMetadata:=dll.LLVMValueMetadataEntriesGetMetadata).restype, LLVMValueMetadataEntriesGetMetadata.argtypes = LLVMMetadataRef, [ctypes.POINTER(LLVMValueMetadataEntry), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMAddGlobal(LLVMModuleRef M, LLVMTypeRef Ty, const char *Name) +try: (LLVMAddGlobal:=dll.LLVMAddGlobal).restype, LLVMAddGlobal.argtypes = LLVMValueRef, [LLVMModuleRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMAddGlobalInAddressSpace(LLVMModuleRef M, LLVMTypeRef Ty, const char *Name, unsigned int AddressSpace) +try: (LLVMAddGlobalInAddressSpace:=dll.LLVMAddGlobalInAddressSpace).restype, LLVMAddGlobalInAddressSpace.argtypes = LLVMValueRef, [LLVMModuleRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMGetNamedGlobal(LLVMModuleRef M, const char *Name) +try: (LLVMGetNamedGlobal:=dll.LLVMGetNamedGlobal).restype, LLVMGetNamedGlobal.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMGetNamedGlobalWithLength(LLVMModuleRef M, const char *Name, size_t Length) +try: (LLVMGetNamedGlobalWithLength:=dll.LLVMGetNamedGlobalWithLength).restype, LLVMGetNamedGlobalWithLength.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMValueRef LLVMGetFirstGlobal(LLVMModuleRef M) +try: (LLVMGetFirstGlobal:=dll.LLVMGetFirstGlobal).restype, LLVMGetFirstGlobal.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetLastGlobal(LLVMModuleRef M) +try: (LLVMGetLastGlobal:=dll.LLVMGetLastGlobal).restype, LLVMGetLastGlobal.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNextGlobal(LLVMValueRef GlobalVar) +try: (LLVMGetNextGlobal:=dll.LLVMGetNextGlobal).restype, LLVMGetNextGlobal.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPreviousGlobal(LLVMValueRef GlobalVar) +try: (LLVMGetPreviousGlobal:=dll.LLVMGetPreviousGlobal).restype, LLVMGetPreviousGlobal.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMDeleteGlobal(LLVMValueRef GlobalVar) +try: (LLVMDeleteGlobal:=dll.LLVMDeleteGlobal).restype, LLVMDeleteGlobal.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetInitializer(LLVMValueRef GlobalVar) +try: (LLVMGetInitializer:=dll.LLVMGetInitializer).restype, LLVMGetInitializer.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetInitializer(LLVMValueRef GlobalVar, LLVMValueRef ConstantVal) +try: (LLVMSetInitializer:=dll.LLVMSetInitializer).restype, LLVMSetInitializer.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsThreadLocal(LLVMValueRef GlobalVar) +try: (LLVMIsThreadLocal:=dll.LLVMIsThreadLocal).restype, LLVMIsThreadLocal.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetThreadLocal(LLVMValueRef GlobalVar, LLVMBool IsThreadLocal) +try: (LLVMSetThreadLocal:=dll.LLVMSetThreadLocal).restype, LLVMSetThreadLocal.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMIsGlobalConstant(LLVMValueRef GlobalVar) +try: (LLVMIsGlobalConstant:=dll.LLVMIsGlobalConstant).restype, LLVMIsGlobalConstant.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetGlobalConstant(LLVMValueRef GlobalVar, LLVMBool IsConstant) +try: (LLVMSetGlobalConstant:=dll.LLVMSetGlobalConstant).restype, LLVMSetGlobalConstant.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMThreadLocalMode LLVMGetThreadLocalMode(LLVMValueRef GlobalVar) +try: (LLVMGetThreadLocalMode:=dll.LLVMGetThreadLocalMode).restype, LLVMGetThreadLocalMode.argtypes = LLVMThreadLocalMode, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetThreadLocalMode(LLVMValueRef GlobalVar, LLVMThreadLocalMode Mode) +try: (LLVMSetThreadLocalMode:=dll.LLVMSetThreadLocalMode).restype, LLVMSetThreadLocalMode.argtypes = None, [LLVMValueRef, LLVMThreadLocalMode] +except AttributeError: pass + +# LLVMBool LLVMIsExternallyInitialized(LLVMValueRef GlobalVar) +try: (LLVMIsExternallyInitialized:=dll.LLVMIsExternallyInitialized).restype, LLVMIsExternallyInitialized.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetExternallyInitialized(LLVMValueRef GlobalVar, LLVMBool IsExtInit) +try: (LLVMSetExternallyInitialized:=dll.LLVMSetExternallyInitialized).restype, LLVMSetExternallyInitialized.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMAddAlias2(LLVMModuleRef M, LLVMTypeRef ValueTy, unsigned int AddrSpace, LLVMValueRef Aliasee, const char *Name) +try: (LLVMAddAlias2:=dll.LLVMAddAlias2).restype, LLVMAddAlias2.argtypes = LLVMValueRef, [LLVMModuleRef, LLVMTypeRef, ctypes.c_uint32, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMGetNamedGlobalAlias(LLVMModuleRef M, const char *Name, size_t NameLen) +try: (LLVMGetNamedGlobalAlias:=dll.LLVMGetNamedGlobalAlias).restype, LLVMGetNamedGlobalAlias.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMValueRef LLVMGetFirstGlobalAlias(LLVMModuleRef M) +try: (LLVMGetFirstGlobalAlias:=dll.LLVMGetFirstGlobalAlias).restype, LLVMGetFirstGlobalAlias.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetLastGlobalAlias(LLVMModuleRef M) +try: (LLVMGetLastGlobalAlias:=dll.LLVMGetLastGlobalAlias).restype, LLVMGetLastGlobalAlias.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNextGlobalAlias(LLVMValueRef GA) +try: (LLVMGetNextGlobalAlias:=dll.LLVMGetNextGlobalAlias).restype, LLVMGetNextGlobalAlias.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPreviousGlobalAlias(LLVMValueRef GA) +try: (LLVMGetPreviousGlobalAlias:=dll.LLVMGetPreviousGlobalAlias).restype, LLVMGetPreviousGlobalAlias.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMAliasGetAliasee(LLVMValueRef Alias) +try: (LLVMAliasGetAliasee:=dll.LLVMAliasGetAliasee).restype, LLVMAliasGetAliasee.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMAliasSetAliasee(LLVMValueRef Alias, LLVMValueRef Aliasee) +try: (LLVMAliasSetAliasee:=dll.LLVMAliasSetAliasee).restype, LLVMAliasSetAliasee.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMDeleteFunction(LLVMValueRef Fn) +try: (LLVMDeleteFunction:=dll.LLVMDeleteFunction).restype, LLVMDeleteFunction.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMHasPersonalityFn(LLVMValueRef Fn) +try: (LLVMHasPersonalityFn:=dll.LLVMHasPersonalityFn).restype, LLVMHasPersonalityFn.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPersonalityFn(LLVMValueRef Fn) +try: (LLVMGetPersonalityFn:=dll.LLVMGetPersonalityFn).restype, LLVMGetPersonalityFn.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetPersonalityFn(LLVMValueRef Fn, LLVMValueRef PersonalityFn) +try: (LLVMSetPersonalityFn:=dll.LLVMSetPersonalityFn).restype, LLVMSetPersonalityFn.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMLookupIntrinsicID(const char *Name, size_t NameLen) +try: (LLVMLookupIntrinsicID:=dll.LLVMLookupIntrinsicID).restype, LLVMLookupIntrinsicID.argtypes = ctypes.c_uint32, [ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# unsigned int LLVMGetIntrinsicID(LLVMValueRef Fn) +try: (LLVMGetIntrinsicID:=dll.LLVMGetIntrinsicID).restype, LLVMGetIntrinsicID.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetIntrinsicDeclaration(LLVMModuleRef Mod, unsigned int ID, LLVMTypeRef *ParamTypes, size_t ParamCount) +try: (LLVMGetIntrinsicDeclaration:=dll.LLVMGetIntrinsicDeclaration).restype, LLVMGetIntrinsicDeclaration.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(LLVMTypeRef), size_t] +except AttributeError: pass + +# LLVMTypeRef LLVMIntrinsicGetType(LLVMContextRef Ctx, unsigned int ID, LLVMTypeRef *ParamTypes, size_t ParamCount) +try: (LLVMIntrinsicGetType:=dll.LLVMIntrinsicGetType).restype, LLVMIntrinsicGetType.argtypes = LLVMTypeRef, [LLVMContextRef, ctypes.c_uint32, ctypes.POINTER(LLVMTypeRef), size_t] +except AttributeError: pass + +# const char *LLVMIntrinsicGetName(unsigned int ID, size_t *NameLength) +try: (LLVMIntrinsicGetName:=dll.LLVMIntrinsicGetName).restype, LLVMIntrinsicGetName.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_uint32, ctypes.POINTER(size_t)] +except AttributeError: pass + +# char *LLVMIntrinsicCopyOverloadedName(unsigned int ID, LLVMTypeRef *ParamTypes, size_t ParamCount, size_t *NameLength) +try: (LLVMIntrinsicCopyOverloadedName:=dll.LLVMIntrinsicCopyOverloadedName).restype, LLVMIntrinsicCopyOverloadedName.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_uint32, ctypes.POINTER(LLVMTypeRef), size_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# char *LLVMIntrinsicCopyOverloadedName2(LLVMModuleRef Mod, unsigned int ID, LLVMTypeRef *ParamTypes, size_t ParamCount, size_t *NameLength) +try: (LLVMIntrinsicCopyOverloadedName2:=dll.LLVMIntrinsicCopyOverloadedName2).restype, LLVMIntrinsicCopyOverloadedName2.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(LLVMTypeRef), size_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# LLVMBool LLVMIntrinsicIsOverloaded(unsigned int ID) +try: (LLVMIntrinsicIsOverloaded:=dll.LLVMIntrinsicIsOverloaded).restype, LLVMIntrinsicIsOverloaded.argtypes = LLVMBool, [ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetFunctionCallConv(LLVMValueRef Fn) +try: (LLVMGetFunctionCallConv:=dll.LLVMGetFunctionCallConv).restype, LLVMGetFunctionCallConv.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetFunctionCallConv(LLVMValueRef Fn, unsigned int CC) +try: (LLVMSetFunctionCallConv:=dll.LLVMSetFunctionCallConv).restype, LLVMSetFunctionCallConv.argtypes = None, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# const char *LLVMGetGC(LLVMValueRef Fn) +try: (LLVMGetGC:=dll.LLVMGetGC).restype, LLVMGetGC.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetGC(LLVMValueRef Fn, const char *Name) +try: (LLVMSetGC:=dll.LLVMSetGC).restype, LLVMSetGC.argtypes = None, [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMGetPrefixData(LLVMValueRef Fn) +try: (LLVMGetPrefixData:=dll.LLVMGetPrefixData).restype, LLVMGetPrefixData.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMHasPrefixData(LLVMValueRef Fn) +try: (LLVMHasPrefixData:=dll.LLVMHasPrefixData).restype, LLVMHasPrefixData.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetPrefixData(LLVMValueRef Fn, LLVMValueRef prefixData) +try: (LLVMSetPrefixData:=dll.LLVMSetPrefixData).restype, LLVMSetPrefixData.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPrologueData(LLVMValueRef Fn) +try: (LLVMGetPrologueData:=dll.LLVMGetPrologueData).restype, LLVMGetPrologueData.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMHasPrologueData(LLVMValueRef Fn) +try: (LLVMHasPrologueData:=dll.LLVMHasPrologueData).restype, LLVMHasPrologueData.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetPrologueData(LLVMValueRef Fn, LLVMValueRef prologueData) +try: (LLVMSetPrologueData:=dll.LLVMSetPrologueData).restype, LLVMSetPrologueData.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMAddAttributeAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx, LLVMAttributeRef A) +try: (LLVMAddAttributeAtIndex:=dll.LLVMAddAttributeAtIndex).restype, LLVMAddAttributeAtIndex.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, LLVMAttributeRef] +except AttributeError: pass + +# unsigned int LLVMGetAttributeCountAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx) +try: (LLVMGetAttributeCountAtIndex:=dll.LLVMGetAttributeCountAtIndex).restype, LLVMGetAttributeCountAtIndex.argtypes = ctypes.c_uint32, [LLVMValueRef, LLVMAttributeIndex] +except AttributeError: pass + +# void LLVMGetAttributesAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx, LLVMAttributeRef *Attrs) +try: (LLVMGetAttributesAtIndex:=dll.LLVMGetAttributesAtIndex).restype, LLVMGetAttributesAtIndex.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(LLVMAttributeRef)] +except AttributeError: pass + +# LLVMAttributeRef LLVMGetEnumAttributeAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx, unsigned int KindID) +try: (LLVMGetEnumAttributeAtIndex:=dll.LLVMGetEnumAttributeAtIndex).restype, LLVMGetEnumAttributeAtIndex.argtypes = LLVMAttributeRef, [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] +except AttributeError: pass + +# LLVMAttributeRef LLVMGetStringAttributeAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx, const char *K, unsigned int KLen) +try: (LLVMGetStringAttributeAtIndex:=dll.LLVMGetStringAttributeAtIndex).restype, LLVMGetStringAttributeAtIndex.argtypes = LLVMAttributeRef, [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# void LLVMRemoveEnumAttributeAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx, unsigned int KindID) +try: (LLVMRemoveEnumAttributeAtIndex:=dll.LLVMRemoveEnumAttributeAtIndex).restype, LLVMRemoveEnumAttributeAtIndex.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMRemoveStringAttributeAtIndex(LLVMValueRef F, LLVMAttributeIndex Idx, const char *K, unsigned int KLen) +try: (LLVMRemoveStringAttributeAtIndex:=dll.LLVMRemoveStringAttributeAtIndex).restype, LLVMRemoveStringAttributeAtIndex.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# void LLVMAddTargetDependentFunctionAttr(LLVMValueRef Fn, const char *A, const char *V) +try: (LLVMAddTargetDependentFunctionAttr:=dll.LLVMAddTargetDependentFunctionAttr).restype, LLVMAddTargetDependentFunctionAttr.argtypes = None, [LLVMValueRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# unsigned int LLVMCountParams(LLVMValueRef Fn) +try: (LLVMCountParams:=dll.LLVMCountParams).restype, LLVMCountParams.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMGetParams(LLVMValueRef Fn, LLVMValueRef *Params) +try: (LLVMGetParams:=dll.LLVMGetParams).restype, LLVMGetParams.argtypes = None, [LLVMValueRef, ctypes.POINTER(LLVMValueRef)] +except AttributeError: pass + +# LLVMValueRef LLVMGetParam(LLVMValueRef Fn, unsigned int Index) +try: (LLVMGetParam:=dll.LLVMGetParam).restype, LLVMGetParam.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMGetParamParent(LLVMValueRef Inst) +try: (LLVMGetParamParent:=dll.LLVMGetParamParent).restype, LLVMGetParamParent.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetFirstParam(LLVMValueRef Fn) +try: (LLVMGetFirstParam:=dll.LLVMGetFirstParam).restype, LLVMGetFirstParam.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetLastParam(LLVMValueRef Fn) +try: (LLVMGetLastParam:=dll.LLVMGetLastParam).restype, LLVMGetLastParam.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNextParam(LLVMValueRef Arg) +try: (LLVMGetNextParam:=dll.LLVMGetNextParam).restype, LLVMGetNextParam.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPreviousParam(LLVMValueRef Arg) +try: (LLVMGetPreviousParam:=dll.LLVMGetPreviousParam).restype, LLVMGetPreviousParam.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetParamAlignment(LLVMValueRef Arg, unsigned int Align) +try: (LLVMSetParamAlignment:=dll.LLVMSetParamAlignment).restype, LLVMSetParamAlignment.argtypes = None, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMAddGlobalIFunc(LLVMModuleRef M, const char *Name, size_t NameLen, LLVMTypeRef Ty, unsigned int AddrSpace, LLVMValueRef Resolver) +try: (LLVMAddGlobalIFunc:=dll.LLVMAddGlobalIFunc).restype, LLVMAddGlobalIFunc.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMTypeRef, ctypes.c_uint32, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNamedGlobalIFunc(LLVMModuleRef M, const char *Name, size_t NameLen) +try: (LLVMGetNamedGlobalIFunc:=dll.LLVMGetNamedGlobalIFunc).restype, LLVMGetNamedGlobalIFunc.argtypes = LLVMValueRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMValueRef LLVMGetFirstGlobalIFunc(LLVMModuleRef M) +try: (LLVMGetFirstGlobalIFunc:=dll.LLVMGetFirstGlobalIFunc).restype, LLVMGetFirstGlobalIFunc.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetLastGlobalIFunc(LLVMModuleRef M) +try: (LLVMGetLastGlobalIFunc:=dll.LLVMGetLastGlobalIFunc).restype, LLVMGetLastGlobalIFunc.argtypes = LLVMValueRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNextGlobalIFunc(LLVMValueRef IFunc) +try: (LLVMGetNextGlobalIFunc:=dll.LLVMGetNextGlobalIFunc).restype, LLVMGetNextGlobalIFunc.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPreviousGlobalIFunc(LLVMValueRef IFunc) +try: (LLVMGetPreviousGlobalIFunc:=dll.LLVMGetPreviousGlobalIFunc).restype, LLVMGetPreviousGlobalIFunc.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetGlobalIFuncResolver(LLVMValueRef IFunc) +try: (LLVMGetGlobalIFuncResolver:=dll.LLVMGetGlobalIFuncResolver).restype, LLVMGetGlobalIFuncResolver.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetGlobalIFuncResolver(LLVMValueRef IFunc, LLVMValueRef Resolver) +try: (LLVMSetGlobalIFuncResolver:=dll.LLVMSetGlobalIFuncResolver).restype, LLVMSetGlobalIFuncResolver.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMEraseGlobalIFunc(LLVMValueRef IFunc) +try: (LLVMEraseGlobalIFunc:=dll.LLVMEraseGlobalIFunc).restype, LLVMEraseGlobalIFunc.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# void LLVMRemoveGlobalIFunc(LLVMValueRef IFunc) +try: (LLVMRemoveGlobalIFunc:=dll.LLVMRemoveGlobalIFunc).restype, LLVMRemoveGlobalIFunc.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMMDStringInContext2(LLVMContextRef C, const char *Str, size_t SLen) +try: (LLVMMDStringInContext2:=dll.LLVMMDStringInContext2).restype, LLVMMDStringInContext2.argtypes = LLVMMetadataRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMMDNodeInContext2(LLVMContextRef C, LLVMMetadataRef *MDs, size_t Count) +try: (LLVMMDNodeInContext2:=dll.LLVMMDNodeInContext2).restype, LLVMMDNodeInContext2.argtypes = LLVMMetadataRef, [LLVMContextRef, ctypes.POINTER(LLVMMetadataRef), size_t] +except AttributeError: pass + +# LLVMValueRef LLVMMetadataAsValue(LLVMContextRef C, LLVMMetadataRef MD) +try: (LLVMMetadataAsValue:=dll.LLVMMetadataAsValue).restype, LLVMMetadataAsValue.argtypes = LLVMValueRef, [LLVMContextRef, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMValueAsMetadata(LLVMValueRef Val) +try: (LLVMValueAsMetadata:=dll.LLVMValueAsMetadata).restype, LLVMValueAsMetadata.argtypes = LLVMMetadataRef, [LLVMValueRef] +except AttributeError: pass + +# const char *LLVMGetMDString(LLVMValueRef V, unsigned int *Length) +try: (LLVMGetMDString:=dll.LLVMGetMDString).restype, LLVMGetMDString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMValueRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# unsigned int LLVMGetMDNodeNumOperands(LLVMValueRef V) +try: (LLVMGetMDNodeNumOperands:=dll.LLVMGetMDNodeNumOperands).restype, LLVMGetMDNodeNumOperands.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMGetMDNodeOperands(LLVMValueRef V, LLVMValueRef *Dest) +try: (LLVMGetMDNodeOperands:=dll.LLVMGetMDNodeOperands).restype, LLVMGetMDNodeOperands.argtypes = None, [LLVMValueRef, ctypes.POINTER(LLVMValueRef)] +except AttributeError: pass + +# void LLVMReplaceMDNodeOperandWith(LLVMValueRef V, unsigned int Index, LLVMMetadataRef Replacement) +try: (LLVMReplaceMDNodeOperandWith:=dll.LLVMReplaceMDNodeOperandWith).restype, LLVMReplaceMDNodeOperandWith.argtypes = None, [LLVMValueRef, ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass + +# LLVMValueRef LLVMMDStringInContext(LLVMContextRef C, const char *Str, unsigned int SLen) +try: (LLVMMDStringInContext:=dll.LLVMMDStringInContext).restype, LLVMMDStringInContext.argtypes = LLVMValueRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMMDString(const char *Str, unsigned int SLen) +try: (LLVMMDString:=dll.LLVMMDString).restype, LLVMMDString.argtypes = LLVMValueRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMMDNodeInContext(LLVMContextRef C, LLVMValueRef *Vals, unsigned int Count) +try: (LLVMMDNodeInContext:=dll.LLVMMDNodeInContext).restype, LLVMMDNodeInContext.argtypes = LLVMValueRef, [LLVMContextRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMMDNode(LLVMValueRef *Vals, unsigned int Count) +try: (LLVMMDNode:=dll.LLVMMDNode).restype, LLVMMDNode.argtypes = LLVMValueRef, [ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +class struct_LLVMOpaqueOperandBundle(Struct): pass +LLVMOperandBundleRef = ctypes.POINTER(struct_LLVMOpaqueOperandBundle) +# LLVMOperandBundleRef LLVMCreateOperandBundle(const char *Tag, size_t TagLen, LLVMValueRef *Args, unsigned int NumArgs) +try: (LLVMCreateOperandBundle:=dll.LLVMCreateOperandBundle).restype, LLVMCreateOperandBundle.argtypes = LLVMOperandBundleRef, [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# void LLVMDisposeOperandBundle(LLVMOperandBundleRef Bundle) +try: (LLVMDisposeOperandBundle:=dll.LLVMDisposeOperandBundle).restype, LLVMDisposeOperandBundle.argtypes = None, [LLVMOperandBundleRef] +except AttributeError: pass + +# const char *LLVMGetOperandBundleTag(LLVMOperandBundleRef Bundle, size_t *Len) +try: (LLVMGetOperandBundleTag:=dll.LLVMGetOperandBundleTag).restype, LLVMGetOperandBundleTag.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOperandBundleRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# unsigned int LLVMGetNumOperandBundleArgs(LLVMOperandBundleRef Bundle) +try: (LLVMGetNumOperandBundleArgs:=dll.LLVMGetNumOperandBundleArgs).restype, LLVMGetNumOperandBundleArgs.argtypes = ctypes.c_uint32, [LLVMOperandBundleRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetOperandBundleArgAtIndex(LLVMOperandBundleRef Bundle, unsigned int Index) +try: (LLVMGetOperandBundleArgAtIndex:=dll.LLVMGetOperandBundleArgAtIndex).restype, LLVMGetOperandBundleArgAtIndex.argtypes = LLVMValueRef, [LLVMOperandBundleRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMBasicBlockAsValue(LLVMBasicBlockRef BB) +try: (LLVMBasicBlockAsValue:=dll.LLVMBasicBlockAsValue).restype, LLVMBasicBlockAsValue.argtypes = LLVMValueRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBool LLVMValueIsBasicBlock(LLVMValueRef Val) +try: (LLVMValueIsBasicBlock:=dll.LLVMValueIsBasicBlock).restype, LLVMValueIsBasicBlock.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMValueAsBasicBlock(LLVMValueRef Val) +try: (LLVMValueAsBasicBlock:=dll.LLVMValueAsBasicBlock).restype, LLVMValueAsBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# const char *LLVMGetBasicBlockName(LLVMBasicBlockRef BB) +try: (LLVMGetBasicBlockName:=dll.LLVMGetBasicBlockName).restype, LLVMGetBasicBlockName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetBasicBlockParent(LLVMBasicBlockRef BB) +try: (LLVMGetBasicBlockParent:=dll.LLVMGetBasicBlockParent).restype, LLVMGetBasicBlockParent.argtypes = LLVMValueRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetBasicBlockTerminator(LLVMBasicBlockRef BB) +try: (LLVMGetBasicBlockTerminator:=dll.LLVMGetBasicBlockTerminator).restype, LLVMGetBasicBlockTerminator.argtypes = LLVMValueRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# unsigned int LLVMCountBasicBlocks(LLVMValueRef Fn) +try: (LLVMCountBasicBlocks:=dll.LLVMCountBasicBlocks).restype, LLVMCountBasicBlocks.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMGetBasicBlocks(LLVMValueRef Fn, LLVMBasicBlockRef *BasicBlocks) +try: (LLVMGetBasicBlocks:=dll.LLVMGetBasicBlocks).restype, LLVMGetBasicBlocks.argtypes = None, [LLVMValueRef, ctypes.POINTER(LLVMBasicBlockRef)] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetFirstBasicBlock(LLVMValueRef Fn) +try: (LLVMGetFirstBasicBlock:=dll.LLVMGetFirstBasicBlock).restype, LLVMGetFirstBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetLastBasicBlock(LLVMValueRef Fn) +try: (LLVMGetLastBasicBlock:=dll.LLVMGetLastBasicBlock).restype, LLVMGetLastBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetNextBasicBlock(LLVMBasicBlockRef BB) +try: (LLVMGetNextBasicBlock:=dll.LLVMGetNextBasicBlock).restype, LLVMGetNextBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetPreviousBasicBlock(LLVMBasicBlockRef BB) +try: (LLVMGetPreviousBasicBlock:=dll.LLVMGetPreviousBasicBlock).restype, LLVMGetPreviousBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetEntryBasicBlock(LLVMValueRef Fn) +try: (LLVMGetEntryBasicBlock:=dll.LLVMGetEntryBasicBlock).restype, LLVMGetEntryBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +class struct_LLVMOpaqueBuilder(Struct): pass +LLVMBuilderRef = ctypes.POINTER(struct_LLVMOpaqueBuilder) +# void LLVMInsertExistingBasicBlockAfterInsertBlock(LLVMBuilderRef Builder, LLVMBasicBlockRef BB) +try: (LLVMInsertExistingBasicBlockAfterInsertBlock:=dll.LLVMInsertExistingBasicBlockAfterInsertBlock).restype, LLVMInsertExistingBasicBlockAfterInsertBlock.argtypes = None, [LLVMBuilderRef, LLVMBasicBlockRef] +except AttributeError: pass + +# void LLVMAppendExistingBasicBlock(LLVMValueRef Fn, LLVMBasicBlockRef BB) +try: (LLVMAppendExistingBasicBlock:=dll.LLVMAppendExistingBasicBlock).restype, LLVMAppendExistingBasicBlock.argtypes = None, [LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMCreateBasicBlockInContext(LLVMContextRef C, const char *Name) +try: (LLVMCreateBasicBlockInContext:=dll.LLVMCreateBasicBlockInContext).restype, LLVMCreateBasicBlockInContext.argtypes = LLVMBasicBlockRef, [LLVMContextRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMAppendBasicBlockInContext(LLVMContextRef C, LLVMValueRef Fn, const char *Name) +try: (LLVMAppendBasicBlockInContext:=dll.LLVMAppendBasicBlockInContext).restype, LLVMAppendBasicBlockInContext.argtypes = LLVMBasicBlockRef, [LLVMContextRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMAppendBasicBlock(LLVMValueRef Fn, const char *Name) +try: (LLVMAppendBasicBlock:=dll.LLVMAppendBasicBlock).restype, LLVMAppendBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMInsertBasicBlockInContext(LLVMContextRef C, LLVMBasicBlockRef BB, const char *Name) +try: (LLVMInsertBasicBlockInContext:=dll.LLVMInsertBasicBlockInContext).restype, LLVMInsertBasicBlockInContext.argtypes = LLVMBasicBlockRef, [LLVMContextRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMInsertBasicBlock(LLVMBasicBlockRef InsertBeforeBB, const char *Name) +try: (LLVMInsertBasicBlock:=dll.LLVMInsertBasicBlock).restype, LLVMInsertBasicBlock.argtypes = LLVMBasicBlockRef, [LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDeleteBasicBlock(LLVMBasicBlockRef BB) +try: (LLVMDeleteBasicBlock:=dll.LLVMDeleteBasicBlock).restype, LLVMDeleteBasicBlock.argtypes = None, [LLVMBasicBlockRef] +except AttributeError: pass + +# void LLVMRemoveBasicBlockFromParent(LLVMBasicBlockRef BB) +try: (LLVMRemoveBasicBlockFromParent:=dll.LLVMRemoveBasicBlockFromParent).restype, LLVMRemoveBasicBlockFromParent.argtypes = None, [LLVMBasicBlockRef] +except AttributeError: pass + +# void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos) +try: (LLVMMoveBasicBlockBefore:=dll.LLVMMoveBasicBlockBefore).restype, LLVMMoveBasicBlockBefore.argtypes = None, [LLVMBasicBlockRef, LLVMBasicBlockRef] +except AttributeError: pass + +# void LLVMMoveBasicBlockAfter(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos) +try: (LLVMMoveBasicBlockAfter:=dll.LLVMMoveBasicBlockAfter).restype, LLVMMoveBasicBlockAfter.argtypes = None, [LLVMBasicBlockRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB) +try: (LLVMGetFirstInstruction:=dll.LLVMGetFirstInstruction).restype, LLVMGetFirstInstruction.argtypes = LLVMValueRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetLastInstruction(LLVMBasicBlockRef BB) +try: (LLVMGetLastInstruction:=dll.LLVMGetLastInstruction).restype, LLVMGetLastInstruction.argtypes = LLVMValueRef, [LLVMBasicBlockRef] +except AttributeError: pass + +# int LLVMHasMetadata(LLVMValueRef Val) +try: (LLVMHasMetadata:=dll.LLVMHasMetadata).restype, LLVMHasMetadata.argtypes = ctypes.c_int32, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetMetadata(LLVMValueRef Val, unsigned int KindID) +try: (LLVMGetMetadata:=dll.LLVMGetMetadata).restype, LLVMGetMetadata.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMSetMetadata(LLVMValueRef Val, unsigned int KindID, LLVMValueRef Node) +try: (LLVMSetMetadata:=dll.LLVMSetMetadata).restype, LLVMSetMetadata.argtypes = None, [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] +except AttributeError: pass + +# LLVMValueMetadataEntry *LLVMInstructionGetAllMetadataOtherThanDebugLoc(LLVMValueRef Instr, size_t *NumEntries) +try: (LLVMInstructionGetAllMetadataOtherThanDebugLoc:=dll.LLVMInstructionGetAllMetadataOtherThanDebugLoc).restype, LLVMInstructionGetAllMetadataOtherThanDebugLoc.argtypes = ctypes.POINTER(LLVMValueMetadataEntry), [LLVMValueRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst) +try: (LLVMGetInstructionParent:=dll.LLVMGetInstructionParent).restype, LLVMGetInstructionParent.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst) +try: (LLVMGetNextInstruction:=dll.LLVMGetNextInstruction).restype, LLVMGetNextInstruction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst) +try: (LLVMGetPreviousInstruction:=dll.LLVMGetPreviousInstruction).restype, LLVMGetPreviousInstruction.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMInstructionRemoveFromParent(LLVMValueRef Inst) +try: (LLVMInstructionRemoveFromParent:=dll.LLVMInstructionRemoveFromParent).restype, LLVMInstructionRemoveFromParent.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# void LLVMInstructionEraseFromParent(LLVMValueRef Inst) +try: (LLVMInstructionEraseFromParent:=dll.LLVMInstructionEraseFromParent).restype, LLVMInstructionEraseFromParent.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# void LLVMDeleteInstruction(LLVMValueRef Inst) +try: (LLVMDeleteInstruction:=dll.LLVMDeleteInstruction).restype, LLVMDeleteInstruction.argtypes = None, [LLVMValueRef] +except AttributeError: pass + +# LLVMOpcode LLVMGetInstructionOpcode(LLVMValueRef Inst) +try: (LLVMGetInstructionOpcode:=dll.LLVMGetInstructionOpcode).restype, LLVMGetInstructionOpcode.argtypes = LLVMOpcode, [LLVMValueRef] +except AttributeError: pass + +# LLVMIntPredicate LLVMGetICmpPredicate(LLVMValueRef Inst) +try: (LLVMGetICmpPredicate:=dll.LLVMGetICmpPredicate).restype, LLVMGetICmpPredicate.argtypes = LLVMIntPredicate, [LLVMValueRef] +except AttributeError: pass + +# LLVMRealPredicate LLVMGetFCmpPredicate(LLVMValueRef Inst) +try: (LLVMGetFCmpPredicate:=dll.LLVMGetFCmpPredicate).restype, LLVMGetFCmpPredicate.argtypes = LLVMRealPredicate, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMInstructionClone(LLVMValueRef Inst) +try: (LLVMInstructionClone:=dll.LLVMInstructionClone).restype, LLVMInstructionClone.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMIsATerminatorInst(LLVMValueRef Inst) +try: (LLVMIsATerminatorInst:=dll.LLVMIsATerminatorInst).restype, LLVMIsATerminatorInst.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMGetFirstDbgRecord(LLVMValueRef Inst) +try: (LLVMGetFirstDbgRecord:=dll.LLVMGetFirstDbgRecord).restype, LLVMGetFirstDbgRecord.argtypes = LLVMDbgRecordRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMGetLastDbgRecord(LLVMValueRef Inst) +try: (LLVMGetLastDbgRecord:=dll.LLVMGetLastDbgRecord).restype, LLVMGetLastDbgRecord.argtypes = LLVMDbgRecordRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMGetNextDbgRecord(LLVMDbgRecordRef DbgRecord) +try: (LLVMGetNextDbgRecord:=dll.LLVMGetNextDbgRecord).restype, LLVMGetNextDbgRecord.argtypes = LLVMDbgRecordRef, [LLVMDbgRecordRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMGetPreviousDbgRecord(LLVMDbgRecordRef DbgRecord) +try: (LLVMGetPreviousDbgRecord:=dll.LLVMGetPreviousDbgRecord).restype, LLVMGetPreviousDbgRecord.argtypes = LLVMDbgRecordRef, [LLVMDbgRecordRef] +except AttributeError: pass + +# unsigned int LLVMGetNumArgOperands(LLVMValueRef Instr) +try: (LLVMGetNumArgOperands:=dll.LLVMGetNumArgOperands).restype, LLVMGetNumArgOperands.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned int CC) +try: (LLVMSetInstructionCallConv:=dll.LLVMSetInstructionCallConv).restype, LLVMSetInstructionCallConv.argtypes = None, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetInstructionCallConv(LLVMValueRef Instr) +try: (LLVMGetInstructionCallConv:=dll.LLVMGetInstructionCallConv).restype, LLVMGetInstructionCallConv.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetInstrParamAlignment(LLVMValueRef Instr, LLVMAttributeIndex Idx, unsigned int Align) +try: (LLVMSetInstrParamAlignment:=dll.LLVMSetInstrParamAlignment).restype, LLVMSetInstrParamAlignment.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMAddCallSiteAttribute(LLVMValueRef C, LLVMAttributeIndex Idx, LLVMAttributeRef A) +try: (LLVMAddCallSiteAttribute:=dll.LLVMAddCallSiteAttribute).restype, LLVMAddCallSiteAttribute.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, LLVMAttributeRef] +except AttributeError: pass + +# unsigned int LLVMGetCallSiteAttributeCount(LLVMValueRef C, LLVMAttributeIndex Idx) +try: (LLVMGetCallSiteAttributeCount:=dll.LLVMGetCallSiteAttributeCount).restype, LLVMGetCallSiteAttributeCount.argtypes = ctypes.c_uint32, [LLVMValueRef, LLVMAttributeIndex] +except AttributeError: pass + +# void LLVMGetCallSiteAttributes(LLVMValueRef C, LLVMAttributeIndex Idx, LLVMAttributeRef *Attrs) +try: (LLVMGetCallSiteAttributes:=dll.LLVMGetCallSiteAttributes).restype, LLVMGetCallSiteAttributes.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(LLVMAttributeRef)] +except AttributeError: pass + +# LLVMAttributeRef LLVMGetCallSiteEnumAttribute(LLVMValueRef C, LLVMAttributeIndex Idx, unsigned int KindID) +try: (LLVMGetCallSiteEnumAttribute:=dll.LLVMGetCallSiteEnumAttribute).restype, LLVMGetCallSiteEnumAttribute.argtypes = LLVMAttributeRef, [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] +except AttributeError: pass + +# LLVMAttributeRef LLVMGetCallSiteStringAttribute(LLVMValueRef C, LLVMAttributeIndex Idx, const char *K, unsigned int KLen) +try: (LLVMGetCallSiteStringAttribute:=dll.LLVMGetCallSiteStringAttribute).restype, LLVMGetCallSiteStringAttribute.argtypes = LLVMAttributeRef, [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# void LLVMRemoveCallSiteEnumAttribute(LLVMValueRef C, LLVMAttributeIndex Idx, unsigned int KindID) +try: (LLVMRemoveCallSiteEnumAttribute:=dll.LLVMRemoveCallSiteEnumAttribute).restype, LLVMRemoveCallSiteEnumAttribute.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMRemoveCallSiteStringAttribute(LLVMValueRef C, LLVMAttributeIndex Idx, const char *K, unsigned int KLen) +try: (LLVMRemoveCallSiteStringAttribute:=dll.LLVMRemoveCallSiteStringAttribute).restype, LLVMRemoveCallSiteStringAttribute.argtypes = None, [LLVMValueRef, LLVMAttributeIndex, ctypes.POINTER(ctypes.c_char), ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMGetCalledFunctionType(LLVMValueRef C) +try: (LLVMGetCalledFunctionType:=dll.LLVMGetCalledFunctionType).restype, LLVMGetCalledFunctionType.argtypes = LLVMTypeRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetCalledValue(LLVMValueRef Instr) +try: (LLVMGetCalledValue:=dll.LLVMGetCalledValue).restype, LLVMGetCalledValue.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMGetNumOperandBundles(LLVMValueRef C) +try: (LLVMGetNumOperandBundles:=dll.LLVMGetNumOperandBundles).restype, LLVMGetNumOperandBundles.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMOperandBundleRef LLVMGetOperandBundleAtIndex(LLVMValueRef C, unsigned int Index) +try: (LLVMGetOperandBundleAtIndex:=dll.LLVMGetOperandBundleAtIndex).restype, LLVMGetOperandBundleAtIndex.argtypes = LLVMOperandBundleRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMBool LLVMIsTailCall(LLVMValueRef CallInst) +try: (LLVMIsTailCall:=dll.LLVMIsTailCall).restype, LLVMIsTailCall.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetTailCall(LLVMValueRef CallInst, LLVMBool IsTailCall) +try: (LLVMSetTailCall:=dll.LLVMSetTailCall).restype, LLVMSetTailCall.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMTailCallKind LLVMGetTailCallKind(LLVMValueRef CallInst) +try: (LLVMGetTailCallKind:=dll.LLVMGetTailCallKind).restype, LLVMGetTailCallKind.argtypes = LLVMTailCallKind, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetTailCallKind(LLVMValueRef CallInst, LLVMTailCallKind kind) +try: (LLVMSetTailCallKind:=dll.LLVMSetTailCallKind).restype, LLVMSetTailCallKind.argtypes = None, [LLVMValueRef, LLVMTailCallKind] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetNormalDest(LLVMValueRef InvokeInst) +try: (LLVMGetNormalDest:=dll.LLVMGetNormalDest).restype, LLVMGetNormalDest.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetUnwindDest(LLVMValueRef InvokeInst) +try: (LLVMGetUnwindDest:=dll.LLVMGetUnwindDest).restype, LLVMGetUnwindDest.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetNormalDest(LLVMValueRef InvokeInst, LLVMBasicBlockRef B) +try: (LLVMSetNormalDest:=dll.LLVMSetNormalDest).restype, LLVMSetNormalDest.argtypes = None, [LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# void LLVMSetUnwindDest(LLVMValueRef InvokeInst, LLVMBasicBlockRef B) +try: (LLVMSetUnwindDest:=dll.LLVMSetUnwindDest).restype, LLVMSetUnwindDest.argtypes = None, [LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetCallBrDefaultDest(LLVMValueRef CallBr) +try: (LLVMGetCallBrDefaultDest:=dll.LLVMGetCallBrDefaultDest).restype, LLVMGetCallBrDefaultDest.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMGetCallBrNumIndirectDests(LLVMValueRef CallBr) +try: (LLVMGetCallBrNumIndirectDests:=dll.LLVMGetCallBrNumIndirectDests).restype, LLVMGetCallBrNumIndirectDests.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetCallBrIndirectDest(LLVMValueRef CallBr, unsigned int Idx) +try: (LLVMGetCallBrIndirectDest:=dll.LLVMGetCallBrIndirectDest).restype, LLVMGetCallBrIndirectDest.argtypes = LLVMBasicBlockRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetNumSuccessors(LLVMValueRef Term) +try: (LLVMGetNumSuccessors:=dll.LLVMGetNumSuccessors).restype, LLVMGetNumSuccessors.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetSuccessor(LLVMValueRef Term, unsigned int i) +try: (LLVMGetSuccessor:=dll.LLVMGetSuccessor).restype, LLVMGetSuccessor.argtypes = LLVMBasicBlockRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMSetSuccessor(LLVMValueRef Term, unsigned int i, LLVMBasicBlockRef block) +try: (LLVMSetSuccessor:=dll.LLVMSetSuccessor).restype, LLVMSetSuccessor.argtypes = None, [LLVMValueRef, ctypes.c_uint32, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBool LLVMIsConditional(LLVMValueRef Branch) +try: (LLVMIsConditional:=dll.LLVMIsConditional).restype, LLVMIsConditional.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetCondition(LLVMValueRef Branch) +try: (LLVMGetCondition:=dll.LLVMGetCondition).restype, LLVMGetCondition.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetCondition(LLVMValueRef Branch, LLVMValueRef Cond) +try: (LLVMSetCondition:=dll.LLVMSetCondition).restype, LLVMSetCondition.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetSwitchDefaultDest(LLVMValueRef SwitchInstr) +try: (LLVMGetSwitchDefaultDest:=dll.LLVMGetSwitchDefaultDest).restype, LLVMGetSwitchDefaultDest.argtypes = LLVMBasicBlockRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMTypeRef LLVMGetAllocatedType(LLVMValueRef Alloca) +try: (LLVMGetAllocatedType:=dll.LLVMGetAllocatedType).restype, LLVMGetAllocatedType.argtypes = LLVMTypeRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsInBounds(LLVMValueRef GEP) +try: (LLVMIsInBounds:=dll.LLVMIsInBounds).restype, LLVMIsInBounds.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetIsInBounds(LLVMValueRef GEP, LLVMBool InBounds) +try: (LLVMSetIsInBounds:=dll.LLVMSetIsInBounds).restype, LLVMSetIsInBounds.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMTypeRef LLVMGetGEPSourceElementType(LLVMValueRef GEP) +try: (LLVMGetGEPSourceElementType:=dll.LLVMGetGEPSourceElementType).restype, LLVMGetGEPSourceElementType.argtypes = LLVMTypeRef, [LLVMValueRef] +except AttributeError: pass + +# LLVMGEPNoWrapFlags LLVMGEPGetNoWrapFlags(LLVMValueRef GEP) +try: (LLVMGEPGetNoWrapFlags:=dll.LLVMGEPGetNoWrapFlags).restype, LLVMGEPGetNoWrapFlags.argtypes = LLVMGEPNoWrapFlags, [LLVMValueRef] +except AttributeError: pass + +# void LLVMGEPSetNoWrapFlags(LLVMValueRef GEP, LLVMGEPNoWrapFlags NoWrapFlags) +try: (LLVMGEPSetNoWrapFlags:=dll.LLVMGEPSetNoWrapFlags).restype, LLVMGEPSetNoWrapFlags.argtypes = None, [LLVMValueRef, LLVMGEPNoWrapFlags] +except AttributeError: pass + +# void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues, LLVMBasicBlockRef *IncomingBlocks, unsigned int Count) +try: (LLVMAddIncoming:=dll.LLVMAddIncoming).restype, LLVMAddIncoming.argtypes = None, [LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.POINTER(LLVMBasicBlockRef), ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMCountIncoming(LLVMValueRef PhiNode) +try: (LLVMCountIncoming:=dll.LLVMCountIncoming).restype, LLVMCountIncoming.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetIncomingValue(LLVMValueRef PhiNode, unsigned int Index) +try: (LLVMGetIncomingValue:=dll.LLVMGetIncomingValue).restype, LLVMGetIncomingValue.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetIncomingBlock(LLVMValueRef PhiNode, unsigned int Index) +try: (LLVMGetIncomingBlock:=dll.LLVMGetIncomingBlock).restype, LLVMGetIncomingBlock.argtypes = LLVMBasicBlockRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetNumIndices(LLVMValueRef Inst) +try: (LLVMGetNumIndices:=dll.LLVMGetNumIndices).restype, LLVMGetNumIndices.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# const unsigned int *LLVMGetIndices(LLVMValueRef Inst) +try: (LLVMGetIndices:=dll.LLVMGetIndices).restype, LLVMGetIndices.argtypes = ctypes.POINTER(ctypes.c_uint32), [LLVMValueRef] +except AttributeError: pass + +# LLVMBuilderRef LLVMCreateBuilderInContext(LLVMContextRef C) +try: (LLVMCreateBuilderInContext:=dll.LLVMCreateBuilderInContext).restype, LLVMCreateBuilderInContext.argtypes = LLVMBuilderRef, [LLVMContextRef] +except AttributeError: pass + +# LLVMBuilderRef LLVMCreateBuilder(void) +try: (LLVMCreateBuilder:=dll.LLVMCreateBuilder).restype, LLVMCreateBuilder.argtypes = LLVMBuilderRef, [] +except AttributeError: pass + +# void LLVMPositionBuilder(LLVMBuilderRef Builder, LLVMBasicBlockRef Block, LLVMValueRef Instr) +try: (LLVMPositionBuilder:=dll.LLVMPositionBuilder).restype, LLVMPositionBuilder.argtypes = None, [LLVMBuilderRef, LLVMBasicBlockRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMPositionBuilderBeforeDbgRecords(LLVMBuilderRef Builder, LLVMBasicBlockRef Block, LLVMValueRef Inst) +try: (LLVMPositionBuilderBeforeDbgRecords:=dll.LLVMPositionBuilderBeforeDbgRecords).restype, LLVMPositionBuilderBeforeDbgRecords.argtypes = None, [LLVMBuilderRef, LLVMBasicBlockRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMPositionBuilderBefore(LLVMBuilderRef Builder, LLVMValueRef Instr) +try: (LLVMPositionBuilderBefore:=dll.LLVMPositionBuilderBefore).restype, LLVMPositionBuilderBefore.argtypes = None, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMPositionBuilderBeforeInstrAndDbgRecords(LLVMBuilderRef Builder, LLVMValueRef Instr) +try: (LLVMPositionBuilderBeforeInstrAndDbgRecords:=dll.LLVMPositionBuilderBeforeInstrAndDbgRecords).restype, LLVMPositionBuilderBeforeInstrAndDbgRecords.argtypes = None, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMPositionBuilderAtEnd(LLVMBuilderRef Builder, LLVMBasicBlockRef Block) +try: (LLVMPositionBuilderAtEnd:=dll.LLVMPositionBuilderAtEnd).restype, LLVMPositionBuilderAtEnd.argtypes = None, [LLVMBuilderRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMBasicBlockRef LLVMGetInsertBlock(LLVMBuilderRef Builder) +try: (LLVMGetInsertBlock:=dll.LLVMGetInsertBlock).restype, LLVMGetInsertBlock.argtypes = LLVMBasicBlockRef, [LLVMBuilderRef] +except AttributeError: pass + +# void LLVMClearInsertionPosition(LLVMBuilderRef Builder) +try: (LLVMClearInsertionPosition:=dll.LLVMClearInsertionPosition).restype, LLVMClearInsertionPosition.argtypes = None, [LLVMBuilderRef] +except AttributeError: pass + +# void LLVMInsertIntoBuilder(LLVMBuilderRef Builder, LLVMValueRef Instr) +try: (LLVMInsertIntoBuilder:=dll.LLVMInsertIntoBuilder).restype, LLVMInsertIntoBuilder.argtypes = None, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMInsertIntoBuilderWithName(LLVMBuilderRef Builder, LLVMValueRef Instr, const char *Name) +try: (LLVMInsertIntoBuilderWithName:=dll.LLVMInsertIntoBuilderWithName).restype, LLVMInsertIntoBuilderWithName.argtypes = None, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeBuilder(LLVMBuilderRef Builder) +try: (LLVMDisposeBuilder:=dll.LLVMDisposeBuilder).restype, LLVMDisposeBuilder.argtypes = None, [LLVMBuilderRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMGetCurrentDebugLocation2(LLVMBuilderRef Builder) +try: (LLVMGetCurrentDebugLocation2:=dll.LLVMGetCurrentDebugLocation2).restype, LLVMGetCurrentDebugLocation2.argtypes = LLVMMetadataRef, [LLVMBuilderRef] +except AttributeError: pass + +# void LLVMSetCurrentDebugLocation2(LLVMBuilderRef Builder, LLVMMetadataRef Loc) +try: (LLVMSetCurrentDebugLocation2:=dll.LLVMSetCurrentDebugLocation2).restype, LLVMSetCurrentDebugLocation2.argtypes = None, [LLVMBuilderRef, LLVMMetadataRef] +except AttributeError: pass + +# void LLVMSetInstDebugLocation(LLVMBuilderRef Builder, LLVMValueRef Inst) +try: (LLVMSetInstDebugLocation:=dll.LLVMSetInstDebugLocation).restype, LLVMSetInstDebugLocation.argtypes = None, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMAddMetadataToInst(LLVMBuilderRef Builder, LLVMValueRef Inst) +try: (LLVMAddMetadataToInst:=dll.LLVMAddMetadataToInst).restype, LLVMAddMetadataToInst.argtypes = None, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMBuilderGetDefaultFPMathTag(LLVMBuilderRef Builder) +try: (LLVMBuilderGetDefaultFPMathTag:=dll.LLVMBuilderGetDefaultFPMathTag).restype, LLVMBuilderGetDefaultFPMathTag.argtypes = LLVMMetadataRef, [LLVMBuilderRef] +except AttributeError: pass + +# void LLVMBuilderSetDefaultFPMathTag(LLVMBuilderRef Builder, LLVMMetadataRef FPMathTag) +try: (LLVMBuilderSetDefaultFPMathTag:=dll.LLVMBuilderSetDefaultFPMathTag).restype, LLVMBuilderSetDefaultFPMathTag.argtypes = None, [LLVMBuilderRef, LLVMMetadataRef] +except AttributeError: pass + +# LLVMContextRef LLVMGetBuilderContext(LLVMBuilderRef Builder) +try: (LLVMGetBuilderContext:=dll.LLVMGetBuilderContext).restype, LLVMGetBuilderContext.argtypes = LLVMContextRef, [LLVMBuilderRef] +except AttributeError: pass + +# void LLVMSetCurrentDebugLocation(LLVMBuilderRef Builder, LLVMValueRef L) +try: (LLVMSetCurrentDebugLocation:=dll.LLVMSetCurrentDebugLocation).restype, LLVMSetCurrentDebugLocation.argtypes = None, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetCurrentDebugLocation(LLVMBuilderRef Builder) +try: (LLVMGetCurrentDebugLocation:=dll.LLVMGetCurrentDebugLocation).restype, LLVMGetCurrentDebugLocation.argtypes = LLVMValueRef, [LLVMBuilderRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildRetVoid(LLVMBuilderRef) +try: (LLVMBuildRetVoid:=dll.LLVMBuildRetVoid).restype, LLVMBuildRetVoid.argtypes = LLVMValueRef, [LLVMBuilderRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildRet(LLVMBuilderRef, LLVMValueRef V) +try: (LLVMBuildRet:=dll.LLVMBuildRet).restype, LLVMBuildRet.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAggregateRet(LLVMBuilderRef, LLVMValueRef *RetVals, unsigned int N) +try: (LLVMBuildAggregateRet:=dll.LLVMBuildAggregateRet).restype, LLVMBuildAggregateRet.argtypes = LLVMValueRef, [LLVMBuilderRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMBuildBr(LLVMBuilderRef, LLVMBasicBlockRef Dest) +try: (LLVMBuildBr:=dll.LLVMBuildBr).restype, LLVMBuildBr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCondBr(LLVMBuilderRef, LLVMValueRef If, LLVMBasicBlockRef Then, LLVMBasicBlockRef Else) +try: (LLVMBuildCondBr:=dll.LLVMBuildCondBr).restype, LLVMBuildCondBr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSwitch(LLVMBuilderRef, LLVMValueRef V, LLVMBasicBlockRef Else, unsigned int NumCases) +try: (LLVMBuildSwitch:=dll.LLVMBuildSwitch).restype, LLVMBuildSwitch.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMBuildIndirectBr(LLVMBuilderRef B, LLVMValueRef Addr, unsigned int NumDests) +try: (LLVMBuildIndirectBr:=dll.LLVMBuildIndirectBr).restype, LLVMBuildIndirectBr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCallBr(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Fn, LLVMBasicBlockRef DefaultDest, LLVMBasicBlockRef *IndirectDests, unsigned int NumIndirectDests, LLVMValueRef *Args, unsigned int NumArgs, LLVMOperandBundleRef *Bundles, unsigned int NumBundles, const char *Name) +try: (LLVMBuildCallBr:=dll.LLVMBuildCallBr).restype, LLVMBuildCallBr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.POINTER(LLVMBasicBlockRef), ctypes.c_uint32, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(LLVMOperandBundleRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildInvoke2(LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef Fn, LLVMValueRef *Args, unsigned int NumArgs, LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch, const char *Name) +try: (LLVMBuildInvoke2:=dll.LLVMBuildInvoke2).restype, LLVMBuildInvoke2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, LLVMBasicBlockRef, LLVMBasicBlockRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildInvokeWithOperandBundles(LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef Fn, LLVMValueRef *Args, unsigned int NumArgs, LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch, LLVMOperandBundleRef *Bundles, unsigned int NumBundles, const char *Name) +try: (LLVMBuildInvokeWithOperandBundles:=dll.LLVMBuildInvokeWithOperandBundles).restype, LLVMBuildInvokeWithOperandBundles.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, LLVMBasicBlockRef, LLVMBasicBlockRef, ctypes.POINTER(LLVMOperandBundleRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef) +try: (LLVMBuildUnreachable:=dll.LLVMBuildUnreachable).restype, LLVMBuildUnreachable.argtypes = LLVMValueRef, [LLVMBuilderRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn) +try: (LLVMBuildResume:=dll.LLVMBuildResume).restype, LLVMBuildResume.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef PersFn, unsigned int NumClauses, const char *Name) +try: (LLVMBuildLandingPad:=dll.LLVMBuildLandingPad).restype, LLVMBuildLandingPad.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCleanupRet(LLVMBuilderRef B, LLVMValueRef CatchPad, LLVMBasicBlockRef BB) +try: (LLVMBuildCleanupRet:=dll.LLVMBuildCleanupRet).restype, LLVMBuildCleanupRet.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCatchRet(LLVMBuilderRef B, LLVMValueRef CatchPad, LLVMBasicBlockRef BB) +try: (LLVMBuildCatchRet:=dll.LLVMBuildCatchRet).restype, LLVMBuildCatchRet.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCatchPad(LLVMBuilderRef B, LLVMValueRef ParentPad, LLVMValueRef *Args, unsigned int NumArgs, const char *Name) +try: (LLVMBuildCatchPad:=dll.LLVMBuildCatchPad).restype, LLVMBuildCatchPad.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCleanupPad(LLVMBuilderRef B, LLVMValueRef ParentPad, LLVMValueRef *Args, unsigned int NumArgs, const char *Name) +try: (LLVMBuildCleanupPad:=dll.LLVMBuildCleanupPad).restype, LLVMBuildCleanupPad.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCatchSwitch(LLVMBuilderRef B, LLVMValueRef ParentPad, LLVMBasicBlockRef UnwindBB, unsigned int NumHandlers, const char *Name) +try: (LLVMBuildCatchSwitch:=dll.LLVMBuildCatchSwitch).restype, LLVMBuildCatchSwitch.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMBasicBlockRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMAddCase(LLVMValueRef Switch, LLVMValueRef OnVal, LLVMBasicBlockRef Dest) +try: (LLVMAddCase:=dll.LLVMAddCase).restype, LLVMAddCase.argtypes = None, [LLVMValueRef, LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# void LLVMAddDestination(LLVMValueRef IndirectBr, LLVMBasicBlockRef Dest) +try: (LLVMAddDestination:=dll.LLVMAddDestination).restype, LLVMAddDestination.argtypes = None, [LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# unsigned int LLVMGetNumClauses(LLVMValueRef LandingPad) +try: (LLVMGetNumClauses:=dll.LLVMGetNumClauses).restype, LLVMGetNumClauses.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetClause(LLVMValueRef LandingPad, unsigned int Idx) +try: (LLVMGetClause:=dll.LLVMGetClause).restype, LLVMGetClause.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMAddClause(LLVMValueRef LandingPad, LLVMValueRef ClauseVal) +try: (LLVMAddClause:=dll.LLVMAddClause).restype, LLVMAddClause.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMIsCleanup(LLVMValueRef LandingPad) +try: (LLVMIsCleanup:=dll.LLVMIsCleanup).restype, LLVMIsCleanup.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetCleanup(LLVMValueRef LandingPad, LLVMBool Val) +try: (LLVMSetCleanup:=dll.LLVMSetCleanup).restype, LLVMSetCleanup.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# void LLVMAddHandler(LLVMValueRef CatchSwitch, LLVMBasicBlockRef Dest) +try: (LLVMAddHandler:=dll.LLVMAddHandler).restype, LLVMAddHandler.argtypes = None, [LLVMValueRef, LLVMBasicBlockRef] +except AttributeError: pass + +# unsigned int LLVMGetNumHandlers(LLVMValueRef CatchSwitch) +try: (LLVMGetNumHandlers:=dll.LLVMGetNumHandlers).restype, LLVMGetNumHandlers.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMGetHandlers(LLVMValueRef CatchSwitch, LLVMBasicBlockRef *Handlers) +try: (LLVMGetHandlers:=dll.LLVMGetHandlers).restype, LLVMGetHandlers.argtypes = None, [LLVMValueRef, ctypes.POINTER(LLVMBasicBlockRef)] +except AttributeError: pass + +# LLVMValueRef LLVMGetArgOperand(LLVMValueRef Funclet, unsigned int i) +try: (LLVMGetArgOperand:=dll.LLVMGetArgOperand).restype, LLVMGetArgOperand.argtypes = LLVMValueRef, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMSetArgOperand(LLVMValueRef Funclet, unsigned int i, LLVMValueRef value) +try: (LLVMSetArgOperand:=dll.LLVMSetArgOperand).restype, LLVMSetArgOperand.argtypes = None, [LLVMValueRef, ctypes.c_uint32, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMGetParentCatchSwitch(LLVMValueRef CatchPad) +try: (LLVMGetParentCatchSwitch:=dll.LLVMGetParentCatchSwitch).restype, LLVMGetParentCatchSwitch.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetParentCatchSwitch(LLVMValueRef CatchPad, LLVMValueRef CatchSwitch) +try: (LLVMSetParentCatchSwitch:=dll.LLVMSetParentCatchSwitch).restype, LLVMSetParentCatchSwitch.argtypes = None, [LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAdd(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildAdd:=dll.LLVMBuildAdd).restype, LLVMBuildAdd.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNSWAdd(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildNSWAdd:=dll.LLVMBuildNSWAdd).restype, LLVMBuildNSWAdd.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNUWAdd(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildNUWAdd:=dll.LLVMBuildNUWAdd).restype, LLVMBuildNUWAdd.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFAdd(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildFAdd:=dll.LLVMBuildFAdd).restype, LLVMBuildFAdd.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSub(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildSub:=dll.LLVMBuildSub).restype, LLVMBuildSub.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNSWSub(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildNSWSub:=dll.LLVMBuildNSWSub).restype, LLVMBuildNSWSub.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNUWSub(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildNUWSub:=dll.LLVMBuildNUWSub).restype, LLVMBuildNUWSub.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFSub(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildFSub:=dll.LLVMBuildFSub).restype, LLVMBuildFSub.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildMul(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildMul:=dll.LLVMBuildMul).restype, LLVMBuildMul.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNSWMul(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildNSWMul:=dll.LLVMBuildNSWMul).restype, LLVMBuildNSWMul.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNUWMul(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildNUWMul:=dll.LLVMBuildNUWMul).restype, LLVMBuildNUWMul.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFMul(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildFMul:=dll.LLVMBuildFMul).restype, LLVMBuildFMul.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildUDiv(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildUDiv:=dll.LLVMBuildUDiv).restype, LLVMBuildUDiv.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildExactUDiv(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildExactUDiv:=dll.LLVMBuildExactUDiv).restype, LLVMBuildExactUDiv.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSDiv(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildSDiv:=dll.LLVMBuildSDiv).restype, LLVMBuildSDiv.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildExactSDiv(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildExactSDiv:=dll.LLVMBuildExactSDiv).restype, LLVMBuildExactSDiv.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFDiv(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildFDiv:=dll.LLVMBuildFDiv).restype, LLVMBuildFDiv.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildURem(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildURem:=dll.LLVMBuildURem).restype, LLVMBuildURem.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSRem(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildSRem:=dll.LLVMBuildSRem).restype, LLVMBuildSRem.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFRem(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildFRem:=dll.LLVMBuildFRem).restype, LLVMBuildFRem.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildShl(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildShl:=dll.LLVMBuildShl).restype, LLVMBuildShl.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildLShr(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildLShr:=dll.LLVMBuildLShr).restype, LLVMBuildLShr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAShr(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildAShr:=dll.LLVMBuildAShr).restype, LLVMBuildAShr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAnd(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildAnd:=dll.LLVMBuildAnd).restype, LLVMBuildAnd.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildOr(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildOr:=dll.LLVMBuildOr).restype, LLVMBuildOr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildXor(LLVMBuilderRef, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildXor:=dll.LLVMBuildXor).restype, LLVMBuildXor.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildBinOp(LLVMBuilderRef B, LLVMOpcode Op, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildBinOp:=dll.LLVMBuildBinOp).restype, LLVMBuildBinOp.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMOpcode, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNeg(LLVMBuilderRef, LLVMValueRef V, const char *Name) +try: (LLVMBuildNeg:=dll.LLVMBuildNeg).restype, LLVMBuildNeg.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNSWNeg(LLVMBuilderRef B, LLVMValueRef V, const char *Name) +try: (LLVMBuildNSWNeg:=dll.LLVMBuildNSWNeg).restype, LLVMBuildNSWNeg.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNUWNeg(LLVMBuilderRef B, LLVMValueRef V, const char *Name) __attribute__((deprecated("Use LLVMBuildNeg + LLVMSetNUW instead."))) +try: (LLVMBuildNUWNeg:=dll.LLVMBuildNUWNeg).restype, LLVMBuildNUWNeg.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFNeg(LLVMBuilderRef, LLVMValueRef V, const char *Name) +try: (LLVMBuildFNeg:=dll.LLVMBuildFNeg).restype, LLVMBuildFNeg.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildNot(LLVMBuilderRef, LLVMValueRef V, const char *Name) +try: (LLVMBuildNot:=dll.LLVMBuildNot).restype, LLVMBuildNot.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetNUW(LLVMValueRef ArithInst) +try: (LLVMGetNUW:=dll.LLVMGetNUW).restype, LLVMGetNUW.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetNUW(LLVMValueRef ArithInst, LLVMBool HasNUW) +try: (LLVMSetNUW:=dll.LLVMSetNUW).restype, LLVMSetNUW.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMGetNSW(LLVMValueRef ArithInst) +try: (LLVMGetNSW:=dll.LLVMGetNSW).restype, LLVMGetNSW.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetNSW(LLVMValueRef ArithInst, LLVMBool HasNSW) +try: (LLVMSetNSW:=dll.LLVMSetNSW).restype, LLVMSetNSW.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMGetExact(LLVMValueRef DivOrShrInst) +try: (LLVMGetExact:=dll.LLVMGetExact).restype, LLVMGetExact.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetExact(LLVMValueRef DivOrShrInst, LLVMBool IsExact) +try: (LLVMSetExact:=dll.LLVMSetExact).restype, LLVMSetExact.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMGetNNeg(LLVMValueRef NonNegInst) +try: (LLVMGetNNeg:=dll.LLVMGetNNeg).restype, LLVMGetNNeg.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetNNeg(LLVMValueRef NonNegInst, LLVMBool IsNonNeg) +try: (LLVMSetNNeg:=dll.LLVMSetNNeg).restype, LLVMSetNNeg.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMFastMathFlags LLVMGetFastMathFlags(LLVMValueRef FPMathInst) +try: (LLVMGetFastMathFlags:=dll.LLVMGetFastMathFlags).restype, LLVMGetFastMathFlags.argtypes = LLVMFastMathFlags, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetFastMathFlags(LLVMValueRef FPMathInst, LLVMFastMathFlags FMF) +try: (LLVMSetFastMathFlags:=dll.LLVMSetFastMathFlags).restype, LLVMSetFastMathFlags.argtypes = None, [LLVMValueRef, LLVMFastMathFlags] +except AttributeError: pass + +# LLVMBool LLVMCanValueUseFastMathFlags(LLVMValueRef Inst) +try: (LLVMCanValueUseFastMathFlags:=dll.LLVMCanValueUseFastMathFlags).restype, LLVMCanValueUseFastMathFlags.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMGetIsDisjoint(LLVMValueRef Inst) +try: (LLVMGetIsDisjoint:=dll.LLVMGetIsDisjoint).restype, LLVMGetIsDisjoint.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetIsDisjoint(LLVMValueRef Inst, LLVMBool IsDisjoint) +try: (LLVMSetIsDisjoint:=dll.LLVMSetIsDisjoint).restype, LLVMSetIsDisjoint.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMBuildMalloc(LLVMBuilderRef, LLVMTypeRef Ty, const char *Name) +try: (LLVMBuildMalloc:=dll.LLVMBuildMalloc).restype, LLVMBuildMalloc.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildArrayMalloc(LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef Val, const char *Name) +try: (LLVMBuildArrayMalloc:=dll.LLVMBuildArrayMalloc).restype, LLVMBuildArrayMalloc.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildMemSet(LLVMBuilderRef B, LLVMValueRef Ptr, LLVMValueRef Val, LLVMValueRef Len, unsigned int Align) +try: (LLVMBuildMemSet:=dll.LLVMBuildMemSet).restype, LLVMBuildMemSet.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMBuildMemCpy(LLVMBuilderRef B, LLVMValueRef Dst, unsigned int DstAlign, LLVMValueRef Src, unsigned int SrcAlign, LLVMValueRef Size) +try: (LLVMBuildMemCpy:=dll.LLVMBuildMemCpy).restype, LLVMBuildMemCpy.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.c_uint32, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildMemMove(LLVMBuilderRef B, LLVMValueRef Dst, unsigned int DstAlign, LLVMValueRef Src, unsigned int SrcAlign, LLVMValueRef Size) +try: (LLVMBuildMemMove:=dll.LLVMBuildMemMove).restype, LLVMBuildMemMove.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.c_uint32, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAlloca(LLVMBuilderRef, LLVMTypeRef Ty, const char *Name) +try: (LLVMBuildAlloca:=dll.LLVMBuildAlloca).restype, LLVMBuildAlloca.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildArrayAlloca(LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef Val, const char *Name) +try: (LLVMBuildArrayAlloca:=dll.LLVMBuildArrayAlloca).restype, LLVMBuildArrayAlloca.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFree(LLVMBuilderRef, LLVMValueRef PointerVal) +try: (LLVMBuildFree:=dll.LLVMBuildFree).restype, LLVMBuildFree.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildLoad2(LLVMBuilderRef, LLVMTypeRef Ty, LLVMValueRef PointerVal, const char *Name) +try: (LLVMBuildLoad2:=dll.LLVMBuildLoad2).restype, LLVMBuildLoad2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildStore(LLVMBuilderRef, LLVMValueRef Val, LLVMValueRef Ptr) +try: (LLVMBuildStore:=dll.LLVMBuildStore).restype, LLVMBuildStore.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef LLVMBuildGEP2(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Pointer, LLVMValueRef *Indices, unsigned int NumIndices, const char *Name) +try: (LLVMBuildGEP2:=dll.LLVMBuildGEP2).restype, LLVMBuildGEP2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildInBoundsGEP2(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Pointer, LLVMValueRef *Indices, unsigned int NumIndices, const char *Name) +try: (LLVMBuildInBoundsGEP2:=dll.LLVMBuildInBoundsGEP2).restype, LLVMBuildInBoundsGEP2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildGEPWithNoWrapFlags(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Pointer, LLVMValueRef *Indices, unsigned int NumIndices, const char *Name, LLVMGEPNoWrapFlags NoWrapFlags) +try: (LLVMBuildGEPWithNoWrapFlags:=dll.LLVMBuildGEPWithNoWrapFlags).restype, LLVMBuildGEPWithNoWrapFlags.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), LLVMGEPNoWrapFlags] +except AttributeError: pass + +# LLVMValueRef LLVMBuildStructGEP2(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Pointer, unsigned int Idx, const char *Name) +try: (LLVMBuildStructGEP2:=dll.LLVMBuildStructGEP2).restype, LLVMBuildStructGEP2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildGlobalString(LLVMBuilderRef B, const char *Str, const char *Name) +try: (LLVMBuildGlobalString:=dll.LLVMBuildGlobalString).restype, LLVMBuildGlobalString.argtypes = LLVMValueRef, [LLVMBuilderRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildGlobalStringPtr(LLVMBuilderRef B, const char *Str, const char *Name) +try: (LLVMBuildGlobalStringPtr:=dll.LLVMBuildGlobalStringPtr).restype, LLVMBuildGlobalStringPtr.argtypes = LLVMValueRef, [LLVMBuilderRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetVolatile(LLVMValueRef MemoryAccessInst) +try: (LLVMGetVolatile:=dll.LLVMGetVolatile).restype, LLVMGetVolatile.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetVolatile(LLVMValueRef MemoryAccessInst, LLVMBool IsVolatile) +try: (LLVMSetVolatile:=dll.LLVMSetVolatile).restype, LLVMSetVolatile.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMGetWeak(LLVMValueRef CmpXchgInst) +try: (LLVMGetWeak:=dll.LLVMGetWeak).restype, LLVMGetWeak.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetWeak(LLVMValueRef CmpXchgInst, LLVMBool IsWeak) +try: (LLVMSetWeak:=dll.LLVMSetWeak).restype, LLVMSetWeak.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMAtomicOrdering LLVMGetOrdering(LLVMValueRef MemoryAccessInst) +try: (LLVMGetOrdering:=dll.LLVMGetOrdering).restype, LLVMGetOrdering.argtypes = LLVMAtomicOrdering, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetOrdering(LLVMValueRef MemoryAccessInst, LLVMAtomicOrdering Ordering) +try: (LLVMSetOrdering:=dll.LLVMSetOrdering).restype, LLVMSetOrdering.argtypes = None, [LLVMValueRef, LLVMAtomicOrdering] +except AttributeError: pass + +# LLVMAtomicRMWBinOp LLVMGetAtomicRMWBinOp(LLVMValueRef AtomicRMWInst) +try: (LLVMGetAtomicRMWBinOp:=dll.LLVMGetAtomicRMWBinOp).restype, LLVMGetAtomicRMWBinOp.argtypes = LLVMAtomicRMWBinOp, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetAtomicRMWBinOp(LLVMValueRef AtomicRMWInst, LLVMAtomicRMWBinOp BinOp) +try: (LLVMSetAtomicRMWBinOp:=dll.LLVMSetAtomicRMWBinOp).restype, LLVMSetAtomicRMWBinOp.argtypes = None, [LLVMValueRef, LLVMAtomicRMWBinOp] +except AttributeError: pass + +# LLVMValueRef LLVMBuildTrunc(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildTrunc:=dll.LLVMBuildTrunc).restype, LLVMBuildTrunc.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildZExt(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildZExt:=dll.LLVMBuildZExt).restype, LLVMBuildZExt.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSExt(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildSExt:=dll.LLVMBuildSExt).restype, LLVMBuildSExt.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFPToUI(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildFPToUI:=dll.LLVMBuildFPToUI).restype, LLVMBuildFPToUI.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFPToSI(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildFPToSI:=dll.LLVMBuildFPToSI).restype, LLVMBuildFPToSI.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildUIToFP(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildUIToFP:=dll.LLVMBuildUIToFP).restype, LLVMBuildUIToFP.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSIToFP(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildSIToFP:=dll.LLVMBuildSIToFP).restype, LLVMBuildSIToFP.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFPTrunc(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildFPTrunc:=dll.LLVMBuildFPTrunc).restype, LLVMBuildFPTrunc.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFPExt(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildFPExt:=dll.LLVMBuildFPExt).restype, LLVMBuildFPExt.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildPtrToInt(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildPtrToInt:=dll.LLVMBuildPtrToInt).restype, LLVMBuildPtrToInt.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildIntToPtr(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildIntToPtr:=dll.LLVMBuildIntToPtr).restype, LLVMBuildIntToPtr.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildBitCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildBitCast:=dll.LLVMBuildBitCast).restype, LLVMBuildBitCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAddrSpaceCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildAddrSpaceCast:=dll.LLVMBuildAddrSpaceCast).restype, LLVMBuildAddrSpaceCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildZExtOrBitCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildZExtOrBitCast:=dll.LLVMBuildZExtOrBitCast).restype, LLVMBuildZExtOrBitCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSExtOrBitCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildSExtOrBitCast:=dll.LLVMBuildSExtOrBitCast).restype, LLVMBuildSExtOrBitCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildTruncOrBitCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildTruncOrBitCast:=dll.LLVMBuildTruncOrBitCast).restype, LLVMBuildTruncOrBitCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCast(LLVMBuilderRef B, LLVMOpcode Op, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildCast:=dll.LLVMBuildCast).restype, LLVMBuildCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMOpcode, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildPointerCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildPointerCast:=dll.LLVMBuildPointerCast).restype, LLVMBuildPointerCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildIntCast2(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, LLVMBool IsSigned, const char *Name) +try: (LLVMBuildIntCast2:=dll.LLVMBuildIntCast2).restype, LLVMBuildIntCast2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, LLVMBool, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFPCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildFPCast:=dll.LLVMBuildFPCast).restype, LLVMBuildFPCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildIntCast(LLVMBuilderRef, LLVMValueRef Val, LLVMTypeRef DestTy, const char *Name) +try: (LLVMBuildIntCast:=dll.LLVMBuildIntCast).restype, LLVMBuildIntCast.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOpcode LLVMGetCastOpcode(LLVMValueRef Src, LLVMBool SrcIsSigned, LLVMTypeRef DestTy, LLVMBool DestIsSigned) +try: (LLVMGetCastOpcode:=dll.LLVMGetCastOpcode).restype, LLVMGetCastOpcode.argtypes = LLVMOpcode, [LLVMValueRef, LLVMBool, LLVMTypeRef, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMBuildICmp(LLVMBuilderRef, LLVMIntPredicate Op, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildICmp:=dll.LLVMBuildICmp).restype, LLVMBuildICmp.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMIntPredicate, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFCmp(LLVMBuilderRef, LLVMRealPredicate Op, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildFCmp:=dll.LLVMBuildFCmp).restype, LLVMBuildFCmp.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMRealPredicate, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildPhi(LLVMBuilderRef, LLVMTypeRef Ty, const char *Name) +try: (LLVMBuildPhi:=dll.LLVMBuildPhi).restype, LLVMBuildPhi.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCall2(LLVMBuilderRef, LLVMTypeRef, LLVMValueRef Fn, LLVMValueRef *Args, unsigned int NumArgs, const char *Name) +try: (LLVMBuildCall2:=dll.LLVMBuildCall2).restype, LLVMBuildCall2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildCallWithOperandBundles(LLVMBuilderRef, LLVMTypeRef, LLVMValueRef Fn, LLVMValueRef *Args, unsigned int NumArgs, LLVMOperandBundleRef *Bundles, unsigned int NumBundles, const char *Name) +try: (LLVMBuildCallWithOperandBundles:=dll.LLVMBuildCallWithOperandBundles).restype, LLVMBuildCallWithOperandBundles.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.c_uint32, ctypes.POINTER(LLVMOperandBundleRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildSelect(LLVMBuilderRef, LLVMValueRef If, LLVMValueRef Then, LLVMValueRef Else, const char *Name) +try: (LLVMBuildSelect:=dll.LLVMBuildSelect).restype, LLVMBuildSelect.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildVAArg(LLVMBuilderRef, LLVMValueRef List, LLVMTypeRef Ty, const char *Name) +try: (LLVMBuildVAArg:=dll.LLVMBuildVAArg).restype, LLVMBuildVAArg.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildExtractElement(LLVMBuilderRef, LLVMValueRef VecVal, LLVMValueRef Index, const char *Name) +try: (LLVMBuildExtractElement:=dll.LLVMBuildExtractElement).restype, LLVMBuildExtractElement.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildInsertElement(LLVMBuilderRef, LLVMValueRef VecVal, LLVMValueRef EltVal, LLVMValueRef Index, const char *Name) +try: (LLVMBuildInsertElement:=dll.LLVMBuildInsertElement).restype, LLVMBuildInsertElement.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef, LLVMValueRef V1, LLVMValueRef V2, LLVMValueRef Mask, const char *Name) +try: (LLVMBuildShuffleVector:=dll.LLVMBuildShuffleVector).restype, LLVMBuildShuffleVector.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildExtractValue(LLVMBuilderRef, LLVMValueRef AggVal, unsigned int Index, const char *Name) +try: (LLVMBuildExtractValue:=dll.LLVMBuildExtractValue).restype, LLVMBuildExtractValue.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildInsertValue(LLVMBuilderRef, LLVMValueRef AggVal, LLVMValueRef EltVal, unsigned int Index, const char *Name) +try: (LLVMBuildInsertValue:=dll.LLVMBuildInsertValue).restype, LLVMBuildInsertValue.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFreeze(LLVMBuilderRef, LLVMValueRef Val, const char *Name) +try: (LLVMBuildFreeze:=dll.LLVMBuildFreeze).restype, LLVMBuildFreeze.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildIsNull(LLVMBuilderRef, LLVMValueRef Val, const char *Name) +try: (LLVMBuildIsNull:=dll.LLVMBuildIsNull).restype, LLVMBuildIsNull.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildIsNotNull(LLVMBuilderRef, LLVMValueRef Val, const char *Name) +try: (LLVMBuildIsNotNull:=dll.LLVMBuildIsNotNull).restype, LLVMBuildIsNotNull.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildPtrDiff2(LLVMBuilderRef, LLVMTypeRef ElemTy, LLVMValueRef LHS, LLVMValueRef RHS, const char *Name) +try: (LLVMBuildPtrDiff2:=dll.LLVMBuildPtrDiff2).restype, LLVMBuildPtrDiff2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFence(LLVMBuilderRef B, LLVMAtomicOrdering ordering, LLVMBool singleThread, const char *Name) +try: (LLVMBuildFence:=dll.LLVMBuildFence).restype, LLVMBuildFence.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMAtomicOrdering, LLVMBool, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildFenceSyncScope(LLVMBuilderRef B, LLVMAtomicOrdering ordering, unsigned int SSID, const char *Name) +try: (LLVMBuildFenceSyncScope:=dll.LLVMBuildFenceSyncScope).restype, LLVMBuildFenceSyncScope.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMAtomicOrdering, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAtomicRMW(LLVMBuilderRef B, LLVMAtomicRMWBinOp op, LLVMValueRef PTR, LLVMValueRef Val, LLVMAtomicOrdering ordering, LLVMBool singleThread) +try: (LLVMBuildAtomicRMW:=dll.LLVMBuildAtomicRMW).restype, LLVMBuildAtomicRMW.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMAtomicRMWBinOp, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAtomicRMWSyncScope(LLVMBuilderRef B, LLVMAtomicRMWBinOp op, LLVMValueRef PTR, LLVMValueRef Val, LLVMAtomicOrdering ordering, unsigned int SSID) +try: (LLVMBuildAtomicRMWSyncScope:=dll.LLVMBuildAtomicRMWSyncScope).restype, LLVMBuildAtomicRMWSyncScope.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMAtomicRMWBinOp, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAtomicCmpXchg(LLVMBuilderRef B, LLVMValueRef Ptr, LLVMValueRef Cmp, LLVMValueRef New, LLVMAtomicOrdering SuccessOrdering, LLVMAtomicOrdering FailureOrdering, LLVMBool SingleThread) +try: (LLVMBuildAtomicCmpXchg:=dll.LLVMBuildAtomicCmpXchg).restype, LLVMBuildAtomicCmpXchg.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMAtomicOrdering, LLVMBool] +except AttributeError: pass + +# LLVMValueRef LLVMBuildAtomicCmpXchgSyncScope(LLVMBuilderRef B, LLVMValueRef Ptr, LLVMValueRef Cmp, LLVMValueRef New, LLVMAtomicOrdering SuccessOrdering, LLVMAtomicOrdering FailureOrdering, unsigned int SSID) +try: (LLVMBuildAtomicCmpXchgSyncScope:=dll.LLVMBuildAtomicCmpXchgSyncScope).restype, LLVMBuildAtomicCmpXchgSyncScope.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, LLVMAtomicOrdering, LLVMAtomicOrdering, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int LLVMGetNumMaskElements(LLVMValueRef ShuffleVectorInst) +try: (LLVMGetNumMaskElements:=dll.LLVMGetNumMaskElements).restype, LLVMGetNumMaskElements.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# int LLVMGetUndefMaskElem(void) +try: (LLVMGetUndefMaskElem:=dll.LLVMGetUndefMaskElem).restype, LLVMGetUndefMaskElem.argtypes = ctypes.c_int32, [] +except AttributeError: pass + +# int LLVMGetMaskValue(LLVMValueRef ShuffleVectorInst, unsigned int Elt) +try: (LLVMGetMaskValue:=dll.LLVMGetMaskValue).restype, LLVMGetMaskValue.argtypes = ctypes.c_int32, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMBool LLVMIsAtomicSingleThread(LLVMValueRef AtomicInst) +try: (LLVMIsAtomicSingleThread:=dll.LLVMIsAtomicSingleThread).restype, LLVMIsAtomicSingleThread.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetAtomicSingleThread(LLVMValueRef AtomicInst, LLVMBool SingleThread) +try: (LLVMSetAtomicSingleThread:=dll.LLVMSetAtomicSingleThread).restype, LLVMSetAtomicSingleThread.argtypes = None, [LLVMValueRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMIsAtomic(LLVMValueRef Inst) +try: (LLVMIsAtomic:=dll.LLVMIsAtomic).restype, LLVMIsAtomic.argtypes = LLVMBool, [LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMGetAtomicSyncScopeID(LLVMValueRef AtomicInst) +try: (LLVMGetAtomicSyncScopeID:=dll.LLVMGetAtomicSyncScopeID).restype, LLVMGetAtomicSyncScopeID.argtypes = ctypes.c_uint32, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetAtomicSyncScopeID(LLVMValueRef AtomicInst, unsigned int SSID) +try: (LLVMSetAtomicSyncScopeID:=dll.LLVMSetAtomicSyncScopeID).restype, LLVMSetAtomicSyncScopeID.argtypes = None, [LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMAtomicOrdering LLVMGetCmpXchgSuccessOrdering(LLVMValueRef CmpXchgInst) +try: (LLVMGetCmpXchgSuccessOrdering:=dll.LLVMGetCmpXchgSuccessOrdering).restype, LLVMGetCmpXchgSuccessOrdering.argtypes = LLVMAtomicOrdering, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetCmpXchgSuccessOrdering(LLVMValueRef CmpXchgInst, LLVMAtomicOrdering Ordering) +try: (LLVMSetCmpXchgSuccessOrdering:=dll.LLVMSetCmpXchgSuccessOrdering).restype, LLVMSetCmpXchgSuccessOrdering.argtypes = None, [LLVMValueRef, LLVMAtomicOrdering] +except AttributeError: pass + +# LLVMAtomicOrdering LLVMGetCmpXchgFailureOrdering(LLVMValueRef CmpXchgInst) +try: (LLVMGetCmpXchgFailureOrdering:=dll.LLVMGetCmpXchgFailureOrdering).restype, LLVMGetCmpXchgFailureOrdering.argtypes = LLVMAtomicOrdering, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetCmpXchgFailureOrdering(LLVMValueRef CmpXchgInst, LLVMAtomicOrdering Ordering) +try: (LLVMSetCmpXchgFailureOrdering:=dll.LLVMSetCmpXchgFailureOrdering).restype, LLVMSetCmpXchgFailureOrdering.argtypes = None, [LLVMValueRef, LLVMAtomicOrdering] +except AttributeError: pass + +class struct_LLVMOpaqueModuleProvider(Struct): pass +LLVMModuleProviderRef = ctypes.POINTER(struct_LLVMOpaqueModuleProvider) +# LLVMModuleProviderRef LLVMCreateModuleProviderForExistingModule(LLVMModuleRef M) +try: (LLVMCreateModuleProviderForExistingModule:=dll.LLVMCreateModuleProviderForExistingModule).restype, LLVMCreateModuleProviderForExistingModule.argtypes = LLVMModuleProviderRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMDisposeModuleProvider(LLVMModuleProviderRef M) +try: (LLVMDisposeModuleProvider:=dll.LLVMDisposeModuleProvider).restype, LLVMDisposeModuleProvider.argtypes = None, [LLVMModuleProviderRef] +except AttributeError: pass + +# LLVMBool LLVMCreateMemoryBufferWithContentsOfFile(const char *Path, LLVMMemoryBufferRef *OutMemBuf, char **OutMessage) +try: (LLVMCreateMemoryBufferWithContentsOfFile:=dll.LLVMCreateMemoryBufferWithContentsOfFile).restype, LLVMCreateMemoryBufferWithContentsOfFile.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMMemoryBufferRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMCreateMemoryBufferWithSTDIN(LLVMMemoryBufferRef *OutMemBuf, char **OutMessage) +try: (LLVMCreateMemoryBufferWithSTDIN:=dll.LLVMCreateMemoryBufferWithSTDIN).restype, LLVMCreateMemoryBufferWithSTDIN.argtypes = LLVMBool, [ctypes.POINTER(LLVMMemoryBufferRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMMemoryBufferRef LLVMCreateMemoryBufferWithMemoryRange(const char *InputData, size_t InputDataLength, const char *BufferName, LLVMBool RequiresNullTerminator) +try: (LLVMCreateMemoryBufferWithMemoryRange:=dll.LLVMCreateMemoryBufferWithMemoryRange).restype, LLVMCreateMemoryBufferWithMemoryRange.argtypes = LLVMMemoryBufferRef, [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), LLVMBool] +except AttributeError: pass + +# LLVMMemoryBufferRef LLVMCreateMemoryBufferWithMemoryRangeCopy(const char *InputData, size_t InputDataLength, const char *BufferName) +try: (LLVMCreateMemoryBufferWithMemoryRangeCopy:=dll.LLVMCreateMemoryBufferWithMemoryRangeCopy).restype, LLVMCreateMemoryBufferWithMemoryRangeCopy.argtypes = LLVMMemoryBufferRef, [ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const char *LLVMGetBufferStart(LLVMMemoryBufferRef MemBuf) +try: (LLVMGetBufferStart:=dll.LLVMGetBufferStart).restype, LLVMGetBufferStart.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMMemoryBufferRef] +except AttributeError: pass + +# size_t LLVMGetBufferSize(LLVMMemoryBufferRef MemBuf) +try: (LLVMGetBufferSize:=dll.LLVMGetBufferSize).restype, LLVMGetBufferSize.argtypes = size_t, [LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMDisposeMemoryBuffer(LLVMMemoryBufferRef MemBuf) +try: (LLVMDisposeMemoryBuffer:=dll.LLVMDisposeMemoryBuffer).restype, LLVMDisposeMemoryBuffer.argtypes = None, [LLVMMemoryBufferRef] +except AttributeError: pass + +class struct_LLVMOpaquePassManager(Struct): pass +LLVMPassManagerRef = ctypes.POINTER(struct_LLVMOpaquePassManager) +# LLVMPassManagerRef LLVMCreatePassManager(void) +try: (LLVMCreatePassManager:=dll.LLVMCreatePassManager).restype, LLVMCreatePassManager.argtypes = LLVMPassManagerRef, [] +except AttributeError: pass + +# LLVMPassManagerRef LLVMCreateFunctionPassManagerForModule(LLVMModuleRef M) +try: (LLVMCreateFunctionPassManagerForModule:=dll.LLVMCreateFunctionPassManagerForModule).restype, LLVMCreateFunctionPassManagerForModule.argtypes = LLVMPassManagerRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMPassManagerRef LLVMCreateFunctionPassManager(LLVMModuleProviderRef MP) +try: (LLVMCreateFunctionPassManager:=dll.LLVMCreateFunctionPassManager).restype, LLVMCreateFunctionPassManager.argtypes = LLVMPassManagerRef, [LLVMModuleProviderRef] +except AttributeError: pass + +# LLVMBool LLVMRunPassManager(LLVMPassManagerRef PM, LLVMModuleRef M) +try: (LLVMRunPassManager:=dll.LLVMRunPassManager).restype, LLVMRunPassManager.argtypes = LLVMBool, [LLVMPassManagerRef, LLVMModuleRef] +except AttributeError: pass + +# LLVMBool LLVMInitializeFunctionPassManager(LLVMPassManagerRef FPM) +try: (LLVMInitializeFunctionPassManager:=dll.LLVMInitializeFunctionPassManager).restype, LLVMInitializeFunctionPassManager.argtypes = LLVMBool, [LLVMPassManagerRef] +except AttributeError: pass + +# LLVMBool LLVMRunFunctionPassManager(LLVMPassManagerRef FPM, LLVMValueRef F) +try: (LLVMRunFunctionPassManager:=dll.LLVMRunFunctionPassManager).restype, LLVMRunFunctionPassManager.argtypes = LLVMBool, [LLVMPassManagerRef, LLVMValueRef] +except AttributeError: pass + +# LLVMBool LLVMFinalizeFunctionPassManager(LLVMPassManagerRef FPM) +try: (LLVMFinalizeFunctionPassManager:=dll.LLVMFinalizeFunctionPassManager).restype, LLVMFinalizeFunctionPassManager.argtypes = LLVMBool, [LLVMPassManagerRef] +except AttributeError: pass + +# void LLVMDisposePassManager(LLVMPassManagerRef PM) +try: (LLVMDisposePassManager:=dll.LLVMDisposePassManager).restype, LLVMDisposePassManager.argtypes = None, [LLVMPassManagerRef] +except AttributeError: pass + +# LLVMBool LLVMStartMultithreaded(void) +try: (LLVMStartMultithreaded:=dll.LLVMStartMultithreaded).restype, LLVMStartMultithreaded.argtypes = LLVMBool, [] +except AttributeError: pass + +# void LLVMStopMultithreaded(void) +try: (LLVMStopMultithreaded:=dll.LLVMStopMultithreaded).restype, LLVMStopMultithreaded.argtypes = None, [] +except AttributeError: pass + +# LLVMBool LLVMIsMultithreaded(void) +try: (LLVMIsMultithreaded:=dll.LLVMIsMultithreaded).restype, LLVMIsMultithreaded.argtypes = LLVMBool, [] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +LLVMDIFlags = CEnum(ctypes.c_uint32) +LLVMDIFlagZero = LLVMDIFlags.define('LLVMDIFlagZero', 0) +LLVMDIFlagPrivate = LLVMDIFlags.define('LLVMDIFlagPrivate', 1) +LLVMDIFlagProtected = LLVMDIFlags.define('LLVMDIFlagProtected', 2) +LLVMDIFlagPublic = LLVMDIFlags.define('LLVMDIFlagPublic', 3) +LLVMDIFlagFwdDecl = LLVMDIFlags.define('LLVMDIFlagFwdDecl', 4) +LLVMDIFlagAppleBlock = LLVMDIFlags.define('LLVMDIFlagAppleBlock', 8) +LLVMDIFlagReservedBit4 = LLVMDIFlags.define('LLVMDIFlagReservedBit4', 16) +LLVMDIFlagVirtual = LLVMDIFlags.define('LLVMDIFlagVirtual', 32) +LLVMDIFlagArtificial = LLVMDIFlags.define('LLVMDIFlagArtificial', 64) +LLVMDIFlagExplicit = LLVMDIFlags.define('LLVMDIFlagExplicit', 128) +LLVMDIFlagPrototyped = LLVMDIFlags.define('LLVMDIFlagPrototyped', 256) +LLVMDIFlagObjcClassComplete = LLVMDIFlags.define('LLVMDIFlagObjcClassComplete', 512) +LLVMDIFlagObjectPointer = LLVMDIFlags.define('LLVMDIFlagObjectPointer', 1024) +LLVMDIFlagVector = LLVMDIFlags.define('LLVMDIFlagVector', 2048) +LLVMDIFlagStaticMember = LLVMDIFlags.define('LLVMDIFlagStaticMember', 4096) +LLVMDIFlagLValueReference = LLVMDIFlags.define('LLVMDIFlagLValueReference', 8192) +LLVMDIFlagRValueReference = LLVMDIFlags.define('LLVMDIFlagRValueReference', 16384) +LLVMDIFlagReserved = LLVMDIFlags.define('LLVMDIFlagReserved', 32768) +LLVMDIFlagSingleInheritance = LLVMDIFlags.define('LLVMDIFlagSingleInheritance', 65536) +LLVMDIFlagMultipleInheritance = LLVMDIFlags.define('LLVMDIFlagMultipleInheritance', 131072) +LLVMDIFlagVirtualInheritance = LLVMDIFlags.define('LLVMDIFlagVirtualInheritance', 196608) +LLVMDIFlagIntroducedVirtual = LLVMDIFlags.define('LLVMDIFlagIntroducedVirtual', 262144) +LLVMDIFlagBitField = LLVMDIFlags.define('LLVMDIFlagBitField', 524288) +LLVMDIFlagNoReturn = LLVMDIFlags.define('LLVMDIFlagNoReturn', 1048576) +LLVMDIFlagTypePassByValue = LLVMDIFlags.define('LLVMDIFlagTypePassByValue', 4194304) +LLVMDIFlagTypePassByReference = LLVMDIFlags.define('LLVMDIFlagTypePassByReference', 8388608) +LLVMDIFlagEnumClass = LLVMDIFlags.define('LLVMDIFlagEnumClass', 16777216) +LLVMDIFlagFixedEnum = LLVMDIFlags.define('LLVMDIFlagFixedEnum', 16777216) +LLVMDIFlagThunk = LLVMDIFlags.define('LLVMDIFlagThunk', 33554432) +LLVMDIFlagNonTrivial = LLVMDIFlags.define('LLVMDIFlagNonTrivial', 67108864) +LLVMDIFlagBigEndian = LLVMDIFlags.define('LLVMDIFlagBigEndian', 134217728) +LLVMDIFlagLittleEndian = LLVMDIFlags.define('LLVMDIFlagLittleEndian', 268435456) +LLVMDIFlagIndirectVirtualBase = LLVMDIFlags.define('LLVMDIFlagIndirectVirtualBase', 36) +LLVMDIFlagAccessibility = LLVMDIFlags.define('LLVMDIFlagAccessibility', 3) +LLVMDIFlagPtrToMemberRep = LLVMDIFlags.define('LLVMDIFlagPtrToMemberRep', 196608) + +LLVMDWARFSourceLanguage = CEnum(ctypes.c_uint32) +LLVMDWARFSourceLanguageC89 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC89', 0) +LLVMDWARFSourceLanguageC = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC', 1) +LLVMDWARFSourceLanguageAda83 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageAda83', 2) +LLVMDWARFSourceLanguageC_plus_plus = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_plus_plus', 3) +LLVMDWARFSourceLanguageCobol74 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageCobol74', 4) +LLVMDWARFSourceLanguageCobol85 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageCobol85', 5) +LLVMDWARFSourceLanguageFortran77 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageFortran77', 6) +LLVMDWARFSourceLanguageFortran90 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageFortran90', 7) +LLVMDWARFSourceLanguagePascal83 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguagePascal83', 8) +LLVMDWARFSourceLanguageModula2 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageModula2', 9) +LLVMDWARFSourceLanguageJava = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageJava', 10) +LLVMDWARFSourceLanguageC99 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC99', 11) +LLVMDWARFSourceLanguageAda95 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageAda95', 12) +LLVMDWARFSourceLanguageFortran95 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageFortran95', 13) +LLVMDWARFSourceLanguagePLI = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguagePLI', 14) +LLVMDWARFSourceLanguageObjC = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageObjC', 15) +LLVMDWARFSourceLanguageObjC_plus_plus = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageObjC_plus_plus', 16) +LLVMDWARFSourceLanguageUPC = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageUPC', 17) +LLVMDWARFSourceLanguageD = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageD', 18) +LLVMDWARFSourceLanguagePython = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguagePython', 19) +LLVMDWARFSourceLanguageOpenCL = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageOpenCL', 20) +LLVMDWARFSourceLanguageGo = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageGo', 21) +LLVMDWARFSourceLanguageModula3 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageModula3', 22) +LLVMDWARFSourceLanguageHaskell = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageHaskell', 23) +LLVMDWARFSourceLanguageC_plus_plus_03 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_plus_plus_03', 24) +LLVMDWARFSourceLanguageC_plus_plus_11 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_plus_plus_11', 25) +LLVMDWARFSourceLanguageOCaml = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageOCaml', 26) +LLVMDWARFSourceLanguageRust = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageRust', 27) +LLVMDWARFSourceLanguageC11 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC11', 28) +LLVMDWARFSourceLanguageSwift = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageSwift', 29) +LLVMDWARFSourceLanguageJulia = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageJulia', 30) +LLVMDWARFSourceLanguageDylan = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageDylan', 31) +LLVMDWARFSourceLanguageC_plus_plus_14 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_plus_plus_14', 32) +LLVMDWARFSourceLanguageFortran03 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageFortran03', 33) +LLVMDWARFSourceLanguageFortran08 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageFortran08', 34) +LLVMDWARFSourceLanguageRenderScript = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageRenderScript', 35) +LLVMDWARFSourceLanguageBLISS = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageBLISS', 36) +LLVMDWARFSourceLanguageKotlin = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageKotlin', 37) +LLVMDWARFSourceLanguageZig = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageZig', 38) +LLVMDWARFSourceLanguageCrystal = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageCrystal', 39) +LLVMDWARFSourceLanguageC_plus_plus_17 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_plus_plus_17', 40) +LLVMDWARFSourceLanguageC_plus_plus_20 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_plus_plus_20', 41) +LLVMDWARFSourceLanguageC17 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC17', 42) +LLVMDWARFSourceLanguageFortran18 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageFortran18', 43) +LLVMDWARFSourceLanguageAda2005 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageAda2005', 44) +LLVMDWARFSourceLanguageAda2012 = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageAda2012', 45) +LLVMDWARFSourceLanguageHIP = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageHIP', 46) +LLVMDWARFSourceLanguageAssembly = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageAssembly', 47) +LLVMDWARFSourceLanguageC_sharp = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageC_sharp', 48) +LLVMDWARFSourceLanguageMojo = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageMojo', 49) +LLVMDWARFSourceLanguageGLSL = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageGLSL', 50) +LLVMDWARFSourceLanguageGLSL_ES = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageGLSL_ES', 51) +LLVMDWARFSourceLanguageHLSL = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageHLSL', 52) +LLVMDWARFSourceLanguageOpenCL_CPP = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageOpenCL_CPP', 53) +LLVMDWARFSourceLanguageCPP_for_OpenCL = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageCPP_for_OpenCL', 54) +LLVMDWARFSourceLanguageSYCL = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageSYCL', 55) +LLVMDWARFSourceLanguageRuby = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageRuby', 56) +LLVMDWARFSourceLanguageMove = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageMove', 57) +LLVMDWARFSourceLanguageHylo = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageHylo', 58) +LLVMDWARFSourceLanguageMetal = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageMetal', 59) +LLVMDWARFSourceLanguageMips_Assembler = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageMips_Assembler', 60) +LLVMDWARFSourceLanguageGOOGLE_RenderScript = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageGOOGLE_RenderScript', 61) +LLVMDWARFSourceLanguageBORLAND_Delphi = LLVMDWARFSourceLanguage.define('LLVMDWARFSourceLanguageBORLAND_Delphi', 62) + +LLVMDWARFEmissionKind = CEnum(ctypes.c_uint32) +LLVMDWARFEmissionNone = LLVMDWARFEmissionKind.define('LLVMDWARFEmissionNone', 0) +LLVMDWARFEmissionFull = LLVMDWARFEmissionKind.define('LLVMDWARFEmissionFull', 1) +LLVMDWARFEmissionLineTablesOnly = LLVMDWARFEmissionKind.define('LLVMDWARFEmissionLineTablesOnly', 2) + +_anonenum3 = CEnum(ctypes.c_uint32) +LLVMMDStringMetadataKind = _anonenum3.define('LLVMMDStringMetadataKind', 0) +LLVMConstantAsMetadataMetadataKind = _anonenum3.define('LLVMConstantAsMetadataMetadataKind', 1) +LLVMLocalAsMetadataMetadataKind = _anonenum3.define('LLVMLocalAsMetadataMetadataKind', 2) +LLVMDistinctMDOperandPlaceholderMetadataKind = _anonenum3.define('LLVMDistinctMDOperandPlaceholderMetadataKind', 3) +LLVMMDTupleMetadataKind = _anonenum3.define('LLVMMDTupleMetadataKind', 4) +LLVMDILocationMetadataKind = _anonenum3.define('LLVMDILocationMetadataKind', 5) +LLVMDIExpressionMetadataKind = _anonenum3.define('LLVMDIExpressionMetadataKind', 6) +LLVMDIGlobalVariableExpressionMetadataKind = _anonenum3.define('LLVMDIGlobalVariableExpressionMetadataKind', 7) +LLVMGenericDINodeMetadataKind = _anonenum3.define('LLVMGenericDINodeMetadataKind', 8) +LLVMDISubrangeMetadataKind = _anonenum3.define('LLVMDISubrangeMetadataKind', 9) +LLVMDIEnumeratorMetadataKind = _anonenum3.define('LLVMDIEnumeratorMetadataKind', 10) +LLVMDIBasicTypeMetadataKind = _anonenum3.define('LLVMDIBasicTypeMetadataKind', 11) +LLVMDIDerivedTypeMetadataKind = _anonenum3.define('LLVMDIDerivedTypeMetadataKind', 12) +LLVMDICompositeTypeMetadataKind = _anonenum3.define('LLVMDICompositeTypeMetadataKind', 13) +LLVMDISubroutineTypeMetadataKind = _anonenum3.define('LLVMDISubroutineTypeMetadataKind', 14) +LLVMDIFileMetadataKind = _anonenum3.define('LLVMDIFileMetadataKind', 15) +LLVMDICompileUnitMetadataKind = _anonenum3.define('LLVMDICompileUnitMetadataKind', 16) +LLVMDISubprogramMetadataKind = _anonenum3.define('LLVMDISubprogramMetadataKind', 17) +LLVMDILexicalBlockMetadataKind = _anonenum3.define('LLVMDILexicalBlockMetadataKind', 18) +LLVMDILexicalBlockFileMetadataKind = _anonenum3.define('LLVMDILexicalBlockFileMetadataKind', 19) +LLVMDINamespaceMetadataKind = _anonenum3.define('LLVMDINamespaceMetadataKind', 20) +LLVMDIModuleMetadataKind = _anonenum3.define('LLVMDIModuleMetadataKind', 21) +LLVMDITemplateTypeParameterMetadataKind = _anonenum3.define('LLVMDITemplateTypeParameterMetadataKind', 22) +LLVMDITemplateValueParameterMetadataKind = _anonenum3.define('LLVMDITemplateValueParameterMetadataKind', 23) +LLVMDIGlobalVariableMetadataKind = _anonenum3.define('LLVMDIGlobalVariableMetadataKind', 24) +LLVMDILocalVariableMetadataKind = _anonenum3.define('LLVMDILocalVariableMetadataKind', 25) +LLVMDILabelMetadataKind = _anonenum3.define('LLVMDILabelMetadataKind', 26) +LLVMDIObjCPropertyMetadataKind = _anonenum3.define('LLVMDIObjCPropertyMetadataKind', 27) +LLVMDIImportedEntityMetadataKind = _anonenum3.define('LLVMDIImportedEntityMetadataKind', 28) +LLVMDIMacroMetadataKind = _anonenum3.define('LLVMDIMacroMetadataKind', 29) +LLVMDIMacroFileMetadataKind = _anonenum3.define('LLVMDIMacroFileMetadataKind', 30) +LLVMDICommonBlockMetadataKind = _anonenum3.define('LLVMDICommonBlockMetadataKind', 31) +LLVMDIStringTypeMetadataKind = _anonenum3.define('LLVMDIStringTypeMetadataKind', 32) +LLVMDIGenericSubrangeMetadataKind = _anonenum3.define('LLVMDIGenericSubrangeMetadataKind', 33) +LLVMDIArgListMetadataKind = _anonenum3.define('LLVMDIArgListMetadataKind', 34) +LLVMDIAssignIDMetadataKind = _anonenum3.define('LLVMDIAssignIDMetadataKind', 35) -# values for enumeration 'c__Ea_LLVMMDStringMetadataKind' -c__Ea_LLVMMDStringMetadataKind__enumvalues = { - 0: 'LLVMMDStringMetadataKind', - 1: 'LLVMConstantAsMetadataMetadataKind', - 2: 'LLVMLocalAsMetadataMetadataKind', - 3: 'LLVMDistinctMDOperandPlaceholderMetadataKind', - 4: 'LLVMMDTupleMetadataKind', - 5: 'LLVMDILocationMetadataKind', - 6: 'LLVMDIExpressionMetadataKind', - 7: 'LLVMDIGlobalVariableExpressionMetadataKind', - 8: 'LLVMGenericDINodeMetadataKind', - 9: 'LLVMDISubrangeMetadataKind', - 10: 'LLVMDIEnumeratorMetadataKind', - 11: 'LLVMDIBasicTypeMetadataKind', - 12: 'LLVMDIDerivedTypeMetadataKind', - 13: 'LLVMDICompositeTypeMetadataKind', - 14: 'LLVMDISubroutineTypeMetadataKind', - 15: 'LLVMDIFileMetadataKind', - 16: 'LLVMDICompileUnitMetadataKind', - 17: 'LLVMDISubprogramMetadataKind', - 18: 'LLVMDILexicalBlockMetadataKind', - 19: 'LLVMDILexicalBlockFileMetadataKind', - 20: 'LLVMDINamespaceMetadataKind', - 21: 'LLVMDIModuleMetadataKind', - 22: 'LLVMDITemplateTypeParameterMetadataKind', - 23: 'LLVMDITemplateValueParameterMetadataKind', - 24: 'LLVMDIGlobalVariableMetadataKind', - 25: 'LLVMDILocalVariableMetadataKind', - 26: 'LLVMDILabelMetadataKind', - 27: 'LLVMDIObjCPropertyMetadataKind', - 28: 'LLVMDIImportedEntityMetadataKind', - 29: 'LLVMDIMacroMetadataKind', - 30: 'LLVMDIMacroFileMetadataKind', - 31: 'LLVMDICommonBlockMetadataKind', - 32: 'LLVMDIStringTypeMetadataKind', - 33: 'LLVMDIGenericSubrangeMetadataKind', - 34: 'LLVMDIArgListMetadataKind', -} -LLVMMDStringMetadataKind = 0 -LLVMConstantAsMetadataMetadataKind = 1 -LLVMLocalAsMetadataMetadataKind = 2 -LLVMDistinctMDOperandPlaceholderMetadataKind = 3 -LLVMMDTupleMetadataKind = 4 -LLVMDILocationMetadataKind = 5 -LLVMDIExpressionMetadataKind = 6 -LLVMDIGlobalVariableExpressionMetadataKind = 7 -LLVMGenericDINodeMetadataKind = 8 -LLVMDISubrangeMetadataKind = 9 -LLVMDIEnumeratorMetadataKind = 10 -LLVMDIBasicTypeMetadataKind = 11 -LLVMDIDerivedTypeMetadataKind = 12 -LLVMDICompositeTypeMetadataKind = 13 -LLVMDISubroutineTypeMetadataKind = 14 -LLVMDIFileMetadataKind = 15 -LLVMDICompileUnitMetadataKind = 16 -LLVMDISubprogramMetadataKind = 17 -LLVMDILexicalBlockMetadataKind = 18 -LLVMDILexicalBlockFileMetadataKind = 19 -LLVMDINamespaceMetadataKind = 20 -LLVMDIModuleMetadataKind = 21 -LLVMDITemplateTypeParameterMetadataKind = 22 -LLVMDITemplateValueParameterMetadataKind = 23 -LLVMDIGlobalVariableMetadataKind = 24 -LLVMDILocalVariableMetadataKind = 25 -LLVMDILabelMetadataKind = 26 -LLVMDIObjCPropertyMetadataKind = 27 -LLVMDIImportedEntityMetadataKind = 28 -LLVMDIMacroMetadataKind = 29 -LLVMDIMacroFileMetadataKind = 30 -LLVMDICommonBlockMetadataKind = 31 -LLVMDIStringTypeMetadataKind = 32 -LLVMDIGenericSubrangeMetadataKind = 33 -LLVMDIArgListMetadataKind = 34 -c__Ea_LLVMMDStringMetadataKind = ctypes.c_uint32 # enum LLVMMetadataKind = ctypes.c_uint32 LLVMDWARFTypeEncoding = ctypes.c_uint32 +LLVMDWARFMacinfoRecordType = CEnum(ctypes.c_uint32) +LLVMDWARFMacinfoRecordTypeDefine = LLVMDWARFMacinfoRecordType.define('LLVMDWARFMacinfoRecordTypeDefine', 1) +LLVMDWARFMacinfoRecordTypeMacro = LLVMDWARFMacinfoRecordType.define('LLVMDWARFMacinfoRecordTypeMacro', 2) +LLVMDWARFMacinfoRecordTypeStartFile = LLVMDWARFMacinfoRecordType.define('LLVMDWARFMacinfoRecordTypeStartFile', 3) +LLVMDWARFMacinfoRecordTypeEndFile = LLVMDWARFMacinfoRecordType.define('LLVMDWARFMacinfoRecordTypeEndFile', 4) +LLVMDWARFMacinfoRecordTypeVendorExt = LLVMDWARFMacinfoRecordType.define('LLVMDWARFMacinfoRecordTypeVendorExt', 255) + +# unsigned int LLVMDebugMetadataVersion(void) +try: (LLVMDebugMetadataVersion:=dll.LLVMDebugMetadataVersion).restype, LLVMDebugMetadataVersion.argtypes = ctypes.c_uint32, [] +except AttributeError: pass + +# unsigned int LLVMGetModuleDebugMetadataVersion(LLVMModuleRef Module) +try: (LLVMGetModuleDebugMetadataVersion:=dll.LLVMGetModuleDebugMetadataVersion).restype, LLVMGetModuleDebugMetadataVersion.argtypes = ctypes.c_uint32, [LLVMModuleRef] +except AttributeError: pass + +# LLVMBool LLVMStripModuleDebugInfo(LLVMModuleRef Module) +try: (LLVMStripModuleDebugInfo:=dll.LLVMStripModuleDebugInfo).restype, LLVMStripModuleDebugInfo.argtypes = LLVMBool, [LLVMModuleRef] +except AttributeError: pass + +class struct_LLVMOpaqueDIBuilder(Struct): pass +LLVMDIBuilderRef = ctypes.POINTER(struct_LLVMOpaqueDIBuilder) +# LLVMDIBuilderRef LLVMCreateDIBuilderDisallowUnresolved(LLVMModuleRef M) +try: (LLVMCreateDIBuilderDisallowUnresolved:=dll.LLVMCreateDIBuilderDisallowUnresolved).restype, LLVMCreateDIBuilderDisallowUnresolved.argtypes = LLVMDIBuilderRef, [LLVMModuleRef] +except AttributeError: pass + +# LLVMDIBuilderRef LLVMCreateDIBuilder(LLVMModuleRef M) +try: (LLVMCreateDIBuilder:=dll.LLVMCreateDIBuilder).restype, LLVMCreateDIBuilder.argtypes = LLVMDIBuilderRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMDisposeDIBuilder(LLVMDIBuilderRef Builder) +try: (LLVMDisposeDIBuilder:=dll.LLVMDisposeDIBuilder).restype, LLVMDisposeDIBuilder.argtypes = None, [LLVMDIBuilderRef] +except AttributeError: pass + +# void LLVMDIBuilderFinalize(LLVMDIBuilderRef Builder) +try: (LLVMDIBuilderFinalize:=dll.LLVMDIBuilderFinalize).restype, LLVMDIBuilderFinalize.argtypes = None, [LLVMDIBuilderRef] +except AttributeError: pass + +# void LLVMDIBuilderFinalizeSubprogram(LLVMDIBuilderRef Builder, LLVMMetadataRef Subprogram) +try: (LLVMDIBuilderFinalizeSubprogram:=dll.LLVMDIBuilderFinalizeSubprogram).restype, LLVMDIBuilderFinalizeSubprogram.argtypes = None, [LLVMDIBuilderRef, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateCompileUnit(LLVMDIBuilderRef Builder, LLVMDWARFSourceLanguage Lang, LLVMMetadataRef FileRef, const char *Producer, size_t ProducerLen, LLVMBool isOptimized, const char *Flags, size_t FlagsLen, unsigned int RuntimeVer, const char *SplitName, size_t SplitNameLen, LLVMDWARFEmissionKind Kind, unsigned int DWOId, LLVMBool SplitDebugInlining, LLVMBool DebugInfoForProfiling, const char *SysRoot, size_t SysRootLen, const char *SDK, size_t SDKLen) +try: (LLVMDIBuilderCreateCompileUnit:=dll.LLVMDIBuilderCreateCompileUnit).restype, LLVMDIBuilderCreateCompileUnit.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMDWARFSourceLanguage, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMDWARFEmissionKind, ctypes.c_uint32, LLVMBool, LLVMBool, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateFile(LLVMDIBuilderRef Builder, const char *Filename, size_t FilenameLen, const char *Directory, size_t DirectoryLen) +try: (LLVMDIBuilderCreateFile:=dll.LLVMDIBuilderCreateFile).restype, LLVMDIBuilderCreateFile.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateModule(LLVMDIBuilderRef Builder, LLVMMetadataRef ParentScope, const char *Name, size_t NameLen, const char *ConfigMacros, size_t ConfigMacrosLen, const char *IncludePath, size_t IncludePathLen, const char *APINotesFile, size_t APINotesFileLen) +try: (LLVMDIBuilderCreateModule:=dll.LLVMDIBuilderCreateModule).restype, LLVMDIBuilderCreateModule.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateNameSpace(LLVMDIBuilderRef Builder, LLVMMetadataRef ParentScope, const char *Name, size_t NameLen, LLVMBool ExportSymbols) +try: (LLVMDIBuilderCreateNameSpace:=dll.LLVMDIBuilderCreateNameSpace).restype, LLVMDIBuilderCreateNameSpace.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateFunction(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, const char *LinkageName, size_t LinkageNameLen, LLVMMetadataRef File, unsigned int LineNo, LLVMMetadataRef Ty, LLVMBool IsLocalToUnit, LLVMBool IsDefinition, unsigned int ScopeLine, LLVMDIFlags Flags, LLVMBool IsOptimized) +try: (LLVMDIBuilderCreateFunction:=dll.LLVMDIBuilderCreateFunction).restype, LLVMDIBuilderCreateFunction.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMBool, ctypes.c_uint32, LLVMDIFlags, LLVMBool] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateLexicalBlock(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, LLVMMetadataRef File, unsigned int Line, unsigned int Column) +try: (LLVMDIBuilderCreateLexicalBlock:=dll.LLVMDIBuilderCreateLexicalBlock).restype, LLVMDIBuilderCreateLexicalBlock.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateLexicalBlockFile(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, LLVMMetadataRef File, unsigned int Discriminator) +try: (LLVMDIBuilderCreateLexicalBlockFile:=dll.LLVMDIBuilderCreateLexicalBlockFile).restype, LLVMDIBuilderCreateLexicalBlockFile.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateImportedModuleFromNamespace(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, LLVMMetadataRef NS, LLVMMetadataRef File, unsigned int Line) +try: (LLVMDIBuilderCreateImportedModuleFromNamespace:=dll.LLVMDIBuilderCreateImportedModuleFromNamespace).restype, LLVMDIBuilderCreateImportedModuleFromNamespace.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateImportedModuleFromAlias(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, LLVMMetadataRef ImportedEntity, LLVMMetadataRef File, unsigned int Line, LLVMMetadataRef *Elements, unsigned int NumElements) +try: (LLVMDIBuilderCreateImportedModuleFromAlias:=dll.LLVMDIBuilderCreateImportedModuleFromAlias).restype, LLVMDIBuilderCreateImportedModuleFromAlias.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateImportedModuleFromModule(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, LLVMMetadataRef M, LLVMMetadataRef File, unsigned int Line, LLVMMetadataRef *Elements, unsigned int NumElements) +try: (LLVMDIBuilderCreateImportedModuleFromModule:=dll.LLVMDIBuilderCreateImportedModuleFromModule).restype, LLVMDIBuilderCreateImportedModuleFromModule.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateImportedDeclaration(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, LLVMMetadataRef Decl, LLVMMetadataRef File, unsigned int Line, const char *Name, size_t NameLen, LLVMMetadataRef *Elements, unsigned int NumElements) +try: (LLVMDIBuilderCreateImportedDeclaration:=dll.LLVMDIBuilderCreateImportedDeclaration).restype, LLVMDIBuilderCreateImportedDeclaration.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateDebugLocation(LLVMContextRef Ctx, unsigned int Line, unsigned int Column, LLVMMetadataRef Scope, LLVMMetadataRef InlinedAt) +try: (LLVMDIBuilderCreateDebugLocation:=dll.LLVMDIBuilderCreateDebugLocation).restype, LLVMDIBuilderCreateDebugLocation.argtypes = LLVMMetadataRef, [LLVMContextRef, ctypes.c_uint32, ctypes.c_uint32, LLVMMetadataRef, LLVMMetadataRef] +except AttributeError: pass + +# unsigned int LLVMDILocationGetLine(LLVMMetadataRef Location) +try: (LLVMDILocationGetLine:=dll.LLVMDILocationGetLine).restype, LLVMDILocationGetLine.argtypes = ctypes.c_uint32, [LLVMMetadataRef] +except AttributeError: pass + +# unsigned int LLVMDILocationGetColumn(LLVMMetadataRef Location) +try: (LLVMDILocationGetColumn:=dll.LLVMDILocationGetColumn).restype, LLVMDILocationGetColumn.argtypes = ctypes.c_uint32, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDILocationGetScope(LLVMMetadataRef Location) +try: (LLVMDILocationGetScope:=dll.LLVMDILocationGetScope).restype, LLVMDILocationGetScope.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDILocationGetInlinedAt(LLVMMetadataRef Location) +try: (LLVMDILocationGetInlinedAt:=dll.LLVMDILocationGetInlinedAt).restype, LLVMDILocationGetInlinedAt.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIScopeGetFile(LLVMMetadataRef Scope) +try: (LLVMDIScopeGetFile:=dll.LLVMDIScopeGetFile).restype, LLVMDIScopeGetFile.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# const char *LLVMDIFileGetDirectory(LLVMMetadataRef File, unsigned int *Len) +try: (LLVMDIFileGetDirectory:=dll.LLVMDIFileGetDirectory).restype, LLVMDIFileGetDirectory.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# const char *LLVMDIFileGetFilename(LLVMMetadataRef File, unsigned int *Len) +try: (LLVMDIFileGetFilename:=dll.LLVMDIFileGetFilename).restype, LLVMDIFileGetFilename.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# const char *LLVMDIFileGetSource(LLVMMetadataRef File, unsigned int *Len) +try: (LLVMDIFileGetSource:=dll.LLVMDIFileGetSource).restype, LLVMDIFileGetSource.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderGetOrCreateTypeArray(LLVMDIBuilderRef Builder, LLVMMetadataRef *Data, size_t NumElements) +try: (LLVMDIBuilderGetOrCreateTypeArray:=dll.LLVMDIBuilderGetOrCreateTypeArray).restype, LLVMDIBuilderGetOrCreateTypeArray.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(LLVMMetadataRef), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateSubroutineType(LLVMDIBuilderRef Builder, LLVMMetadataRef File, LLVMMetadataRef *ParameterTypes, unsigned int NumParameterTypes, LLVMDIFlags Flags) +try: (LLVMDIBuilderCreateSubroutineType:=dll.LLVMDIBuilderCreateSubroutineType).restype, LLVMDIBuilderCreateSubroutineType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32, LLVMDIFlags] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateMacro(LLVMDIBuilderRef Builder, LLVMMetadataRef ParentMacroFile, unsigned int Line, LLVMDWARFMacinfoRecordType RecordType, const char *Name, size_t NameLen, const char *Value, size_t ValueLen) +try: (LLVMDIBuilderCreateMacro:=dll.LLVMDIBuilderCreateMacro).restype, LLVMDIBuilderCreateMacro.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.c_uint32, LLVMDWARFMacinfoRecordType, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateTempMacroFile(LLVMDIBuilderRef Builder, LLVMMetadataRef ParentMacroFile, unsigned int Line, LLVMMetadataRef File) +try: (LLVMDIBuilderCreateTempMacroFile:=dll.LLVMDIBuilderCreateTempMacroFile).restype, LLVMDIBuilderCreateTempMacroFile.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMDWARFMacinfoRecordType' -c__EA_LLVMDWARFMacinfoRecordType__enumvalues = { - 1: 'LLVMDWARFMacinfoRecordTypeDefine', - 2: 'LLVMDWARFMacinfoRecordTypeMacro', - 3: 'LLVMDWARFMacinfoRecordTypeStartFile', - 4: 'LLVMDWARFMacinfoRecordTypeEndFile', - 255: 'LLVMDWARFMacinfoRecordTypeVendorExt', -} -LLVMDWARFMacinfoRecordTypeDefine = 1 -LLVMDWARFMacinfoRecordTypeMacro = 2 -LLVMDWARFMacinfoRecordTypeStartFile = 3 -LLVMDWARFMacinfoRecordTypeEndFile = 4 -LLVMDWARFMacinfoRecordTypeVendorExt = 255 -c__EA_LLVMDWARFMacinfoRecordType = ctypes.c_uint32 # enum -LLVMDWARFMacinfoRecordType = c__EA_LLVMDWARFMacinfoRecordType -LLVMDWARFMacinfoRecordType__enumvalues = c__EA_LLVMDWARFMacinfoRecordType__enumvalues -try: - LLVMDebugMetadataVersion = _libraries['llvm'].LLVMDebugMetadataVersion - LLVMDebugMetadataVersion.restype = ctypes.c_uint32 - LLVMDebugMetadataVersion.argtypes = [] -except AttributeError: - pass -try: - LLVMGetModuleDebugMetadataVersion = _libraries['llvm'].LLVMGetModuleDebugMetadataVersion - LLVMGetModuleDebugMetadataVersion.restype = ctypes.c_uint32 - LLVMGetModuleDebugMetadataVersion.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMStripModuleDebugInfo = _libraries['llvm'].LLVMStripModuleDebugInfo - LLVMStripModuleDebugInfo.restype = LLVMBool - LLVMStripModuleDebugInfo.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMCreateDIBuilderDisallowUnresolved = _libraries['llvm'].LLVMCreateDIBuilderDisallowUnresolved - LLVMCreateDIBuilderDisallowUnresolved.restype = LLVMDIBuilderRef - LLVMCreateDIBuilderDisallowUnresolved.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMCreateDIBuilder = _libraries['llvm'].LLVMCreateDIBuilder - LLVMCreateDIBuilder.restype = LLVMDIBuilderRef - LLVMCreateDIBuilder.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMDisposeDIBuilder = _libraries['llvm'].LLVMDisposeDIBuilder - LLVMDisposeDIBuilder.restype = None - LLVMDisposeDIBuilder.argtypes = [LLVMDIBuilderRef] -except AttributeError: - pass -try: - LLVMDIBuilderFinalize = _libraries['llvm'].LLVMDIBuilderFinalize - LLVMDIBuilderFinalize.restype = None - LLVMDIBuilderFinalize.argtypes = [LLVMDIBuilderRef] -except AttributeError: - pass -try: - LLVMDIBuilderFinalizeSubprogram = _libraries['llvm'].LLVMDIBuilderFinalizeSubprogram - LLVMDIBuilderFinalizeSubprogram.restype = None - LLVMDIBuilderFinalizeSubprogram.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateCompileUnit = _libraries['llvm'].LLVMDIBuilderCreateCompileUnit - LLVMDIBuilderCreateCompileUnit.restype = LLVMMetadataRef - LLVMDIBuilderCreateCompileUnit.argtypes = [LLVMDIBuilderRef, LLVMDWARFSourceLanguage, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMDWARFEmissionKind, ctypes.c_uint32, LLVMBool, LLVMBool, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateFile = _libraries['llvm'].LLVMDIBuilderCreateFile - LLVMDIBuilderCreateFile.restype = LLVMMetadataRef - LLVMDIBuilderCreateFile.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateModule = _libraries['llvm'].LLVMDIBuilderCreateModule - LLVMDIBuilderCreateModule.restype = LLVMMetadataRef - LLVMDIBuilderCreateModule.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateNameSpace = _libraries['llvm'].LLVMDIBuilderCreateNameSpace - LLVMDIBuilderCreateNameSpace.restype = LLVMMetadataRef - LLVMDIBuilderCreateNameSpace.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMBool] -except AttributeError: - pass -try: - LLVMDIBuilderCreateFunction = _libraries['llvm'].LLVMDIBuilderCreateFunction - LLVMDIBuilderCreateFunction.restype = LLVMMetadataRef - LLVMDIBuilderCreateFunction.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMBool, ctypes.c_uint32, LLVMDIFlags, LLVMBool] -except AttributeError: - pass -try: - LLVMDIBuilderCreateLexicalBlock = _libraries['llvm'].LLVMDIBuilderCreateLexicalBlock - LLVMDIBuilderCreateLexicalBlock.restype = LLVMMetadataRef - LLVMDIBuilderCreateLexicalBlock.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateLexicalBlockFile = _libraries['llvm'].LLVMDIBuilderCreateLexicalBlockFile - LLVMDIBuilderCreateLexicalBlockFile.restype = LLVMMetadataRef - LLVMDIBuilderCreateLexicalBlockFile.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedModuleFromNamespace = _libraries['llvm'].LLVMDIBuilderCreateImportedModuleFromNamespace - LLVMDIBuilderCreateImportedModuleFromNamespace.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedModuleFromNamespace.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedModuleFromAlias = _libraries['llvm'].LLVMDIBuilderCreateImportedModuleFromAlias - LLVMDIBuilderCreateImportedModuleFromAlias.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedModuleFromAlias.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedModuleFromModule = _libraries['llvm'].LLVMDIBuilderCreateImportedModuleFromModule - LLVMDIBuilderCreateImportedModuleFromModule.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedModuleFromModule.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateImportedDeclaration = _libraries['llvm'].LLVMDIBuilderCreateImportedDeclaration - LLVMDIBuilderCreateImportedDeclaration.restype = LLVMMetadataRef - LLVMDIBuilderCreateImportedDeclaration.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateDebugLocation = _libraries['llvm'].LLVMDIBuilderCreateDebugLocation - LLVMDIBuilderCreateDebugLocation.restype = LLVMMetadataRef - LLVMDIBuilderCreateDebugLocation.argtypes = [LLVMContextRef, ctypes.c_uint32, ctypes.c_uint32, LLVMMetadataRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetLine = _libraries['llvm'].LLVMDILocationGetLine - LLVMDILocationGetLine.restype = ctypes.c_uint32 - LLVMDILocationGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetColumn = _libraries['llvm'].LLVMDILocationGetColumn - LLVMDILocationGetColumn.restype = ctypes.c_uint32 - LLVMDILocationGetColumn.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetScope = _libraries['llvm'].LLVMDILocationGetScope - LLVMDILocationGetScope.restype = LLVMMetadataRef - LLVMDILocationGetScope.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDILocationGetInlinedAt = _libraries['llvm'].LLVMDILocationGetInlinedAt - LLVMDILocationGetInlinedAt.restype = LLVMMetadataRef - LLVMDILocationGetInlinedAt.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIScopeGetFile = _libraries['llvm'].LLVMDIScopeGetFile - LLVMDIScopeGetFile.restype = LLVMMetadataRef - LLVMDIScopeGetFile.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIFileGetDirectory = _libraries['llvm'].LLVMDIFileGetDirectory - LLVMDIFileGetDirectory.restype = ctypes.POINTER(ctypes.c_char) - LLVMDIFileGetDirectory.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMDIFileGetFilename = _libraries['llvm'].LLVMDIFileGetFilename - LLVMDIFileGetFilename.restype = ctypes.POINTER(ctypes.c_char) - LLVMDIFileGetFilename.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMDIFileGetSource = _libraries['llvm'].LLVMDIFileGetSource - LLVMDIFileGetSource.restype = ctypes.POINTER(ctypes.c_char) - LLVMDIFileGetSource.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - LLVMDIBuilderGetOrCreateTypeArray = _libraries['llvm'].LLVMDIBuilderGetOrCreateTypeArray - LLVMDIBuilderGetOrCreateTypeArray.restype = LLVMMetadataRef - LLVMDIBuilderGetOrCreateTypeArray.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateSubroutineType = _libraries['llvm'].LLVMDIBuilderCreateSubroutineType - LLVMDIBuilderCreateSubroutineType.restype = LLVMMetadataRef - LLVMDIBuilderCreateSubroutineType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreateMacro = _libraries['llvm'].LLVMDIBuilderCreateMacro - LLVMDIBuilderCreateMacro.restype = LLVMMetadataRef - LLVMDIBuilderCreateMacro.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.c_uint32, LLVMDWARFMacinfoRecordType, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateTempMacroFile = _libraries['llvm'].LLVMDIBuilderCreateTempMacroFile - LLVMDIBuilderCreateTempMacroFile.restype = LLVMMetadataRef - LLVMDIBuilderCreateTempMacroFile.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass int64_t = ctypes.c_int64 -try: - LLVMDIBuilderCreateEnumerator = _libraries['llvm'].LLVMDIBuilderCreateEnumerator - LLVMDIBuilderCreateEnumerator.restype = LLVMMetadataRef - LLVMDIBuilderCreateEnumerator.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, int64_t, LLVMBool] -except AttributeError: - pass +# LLVMMetadataRef LLVMDIBuilderCreateEnumerator(LLVMDIBuilderRef Builder, const char *Name, size_t NameLen, int64_t Value, LLVMBool IsUnsigned) +try: (LLVMDIBuilderCreateEnumerator:=dll.LLVMDIBuilderCreateEnumerator).restype, LLVMDIBuilderCreateEnumerator.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, int64_t, LLVMBool] +except AttributeError: pass + uint32_t = ctypes.c_uint32 -try: - LLVMDIBuilderCreateEnumerationType = _libraries['llvm'].LLVMDIBuilderCreateEnumerationType - LLVMDIBuilderCreateEnumerationType.restype = LLVMMetadataRef - LLVMDIBuilderCreateEnumerationType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateUnionType = _libraries['llvm'].LLVMDIBuilderCreateUnionType - LLVMDIBuilderCreateUnionType.restype = LLVMMetadataRef - LLVMDIBuilderCreateUnionType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateArrayType = _libraries['llvm'].LLVMDIBuilderCreateArrayType - LLVMDIBuilderCreateArrayType.restype = LLVMMetadataRef - LLVMDIBuilderCreateArrayType.argtypes = [LLVMDIBuilderRef, uint64_t, uint32_t, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateVectorType = _libraries['llvm'].LLVMDIBuilderCreateVectorType - LLVMDIBuilderCreateVectorType.restype = LLVMMetadataRef - LLVMDIBuilderCreateVectorType.argtypes = [LLVMDIBuilderRef, uint64_t, uint32_t, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMDIBuilderCreateUnspecifiedType = _libraries['llvm'].LLVMDIBuilderCreateUnspecifiedType - LLVMDIBuilderCreateUnspecifiedType.restype = LLVMMetadataRef - LLVMDIBuilderCreateUnspecifiedType.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateBasicType = _libraries['llvm'].LLVMDIBuilderCreateBasicType - LLVMDIBuilderCreateBasicType.restype = LLVMMetadataRef - LLVMDIBuilderCreateBasicType.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, uint64_t, LLVMDWARFTypeEncoding, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreatePointerType = _libraries['llvm'].LLVMDIBuilderCreatePointerType - LLVMDIBuilderCreatePointerType.restype = LLVMMetadataRef - LLVMDIBuilderCreatePointerType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, uint64_t, uint32_t, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateStructType = _libraries['llvm'].LLVMDIBuilderCreateStructType - LLVMDIBuilderCreateStructType.restype = LLVMMetadataRef - LLVMDIBuilderCreateStructType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, ctypes.c_uint32, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateMemberType = _libraries['llvm'].LLVMDIBuilderCreateMemberType - LLVMDIBuilderCreateMemberType.restype = LLVMMetadataRef - LLVMDIBuilderCreateMemberType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateStaticMemberType = _libraries['llvm'].LLVMDIBuilderCreateStaticMemberType - LLVMDIBuilderCreateStaticMemberType.restype = LLVMMetadataRef - LLVMDIBuilderCreateStaticMemberType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMDIFlags, LLVMValueRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateMemberPointerType = _libraries['llvm'].LLVMDIBuilderCreateMemberPointerType - LLVMDIBuilderCreateMemberPointerType.restype = LLVMMetadataRef - LLVMDIBuilderCreateMemberPointerType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, uint64_t, uint32_t, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreateObjCIVar = _libraries['llvm'].LLVMDIBuilderCreateObjCIVar - LLVMDIBuilderCreateObjCIVar.restype = LLVMMetadataRef - LLVMDIBuilderCreateObjCIVar.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateObjCProperty = _libraries['llvm'].LLVMDIBuilderCreateObjCProperty - LLVMDIBuilderCreateObjCProperty.restype = LLVMMetadataRef - LLVMDIBuilderCreateObjCProperty.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateObjectPointerType = _libraries['llvm'].LLVMDIBuilderCreateObjectPointerType - LLVMDIBuilderCreateObjectPointerType.restype = LLVMMetadataRef - LLVMDIBuilderCreateObjectPointerType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateQualifiedType = _libraries['llvm'].LLVMDIBuilderCreateQualifiedType - LLVMDIBuilderCreateQualifiedType.restype = LLVMMetadataRef - LLVMDIBuilderCreateQualifiedType.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateReferenceType = _libraries['llvm'].LLVMDIBuilderCreateReferenceType - LLVMDIBuilderCreateReferenceType.restype = LLVMMetadataRef - LLVMDIBuilderCreateReferenceType.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateNullPtrType = _libraries['llvm'].LLVMDIBuilderCreateNullPtrType - LLVMDIBuilderCreateNullPtrType.restype = LLVMMetadataRef - LLVMDIBuilderCreateNullPtrType.argtypes = [LLVMDIBuilderRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateTypedef = _libraries['llvm'].LLVMDIBuilderCreateTypedef - LLVMDIBuilderCreateTypedef.restype = LLVMMetadataRef - LLVMDIBuilderCreateTypedef.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateInheritance = _libraries['llvm'].LLVMDIBuilderCreateInheritance - LLVMDIBuilderCreateInheritance.restype = LLVMMetadataRef - LLVMDIBuilderCreateInheritance.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, uint64_t, uint32_t, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMDIBuilderCreateForwardDecl = _libraries['llvm'].LLVMDIBuilderCreateForwardDecl - LLVMDIBuilderCreateForwardDecl.restype = LLVMMetadataRef - LLVMDIBuilderCreateForwardDecl.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32, uint64_t, uint32_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateReplaceableCompositeType = _libraries['llvm'].LLVMDIBuilderCreateReplaceableCompositeType - LLVMDIBuilderCreateReplaceableCompositeType.restype = LLVMMetadataRef - LLVMDIBuilderCreateReplaceableCompositeType.argtypes = [LLVMDIBuilderRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateBitFieldMemberType = _libraries['llvm'].LLVMDIBuilderCreateBitFieldMemberType - LLVMDIBuilderCreateBitFieldMemberType.restype = LLVMMetadataRef - LLVMDIBuilderCreateBitFieldMemberType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint64_t, uint64_t, LLVMDIFlags, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateClassType = _libraries['llvm'].LLVMDIBuilderCreateClassType - LLVMDIBuilderCreateClassType.restype = LLVMMetadataRef - LLVMDIBuilderCreateClassType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), ctypes.c_uint32, LLVMMetadataRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateArtificialType = _libraries['llvm'].LLVMDIBuilderCreateArtificialType - LLVMDIBuilderCreateArtificialType.restype = LLVMMetadataRef - LLVMDIBuilderCreateArtificialType.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetName = _libraries['llvm'].LLVMDITypeGetName - LLVMDITypeGetName.restype = ctypes.POINTER(ctypes.c_char) - LLVMDITypeGetName.argtypes = [LLVMMetadataRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMDITypeGetSizeInBits = _libraries['llvm'].LLVMDITypeGetSizeInBits - LLVMDITypeGetSizeInBits.restype = uint64_t - LLVMDITypeGetSizeInBits.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetOffsetInBits = _libraries['llvm'].LLVMDITypeGetOffsetInBits - LLVMDITypeGetOffsetInBits.restype = uint64_t - LLVMDITypeGetOffsetInBits.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetAlignInBits = _libraries['llvm'].LLVMDITypeGetAlignInBits - LLVMDITypeGetAlignInBits.restype = uint32_t - LLVMDITypeGetAlignInBits.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetLine = _libraries['llvm'].LLVMDITypeGetLine - LLVMDITypeGetLine.restype = ctypes.c_uint32 - LLVMDITypeGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDITypeGetFlags = _libraries['llvm'].LLVMDITypeGetFlags - LLVMDITypeGetFlags.restype = LLVMDIFlags - LLVMDITypeGetFlags.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderGetOrCreateSubrange = _libraries['llvm'].LLVMDIBuilderGetOrCreateSubrange - LLVMDIBuilderGetOrCreateSubrange.restype = LLVMMetadataRef - LLVMDIBuilderGetOrCreateSubrange.argtypes = [LLVMDIBuilderRef, int64_t, int64_t] -except AttributeError: - pass -try: - LLVMDIBuilderGetOrCreateArray = _libraries['llvm'].LLVMDIBuilderGetOrCreateArray - LLVMDIBuilderGetOrCreateArray.restype = LLVMMetadataRef - LLVMDIBuilderGetOrCreateArray.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateExpression = _libraries['llvm'].LLVMDIBuilderCreateExpression - LLVMDIBuilderCreateExpression.restype = LLVMMetadataRef - LLVMDIBuilderCreateExpression.argtypes = [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_uint64), size_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateConstantValueExpression = _libraries['llvm'].LLVMDIBuilderCreateConstantValueExpression - LLVMDIBuilderCreateConstantValueExpression.restype = LLVMMetadataRef - LLVMDIBuilderCreateConstantValueExpression.argtypes = [LLVMDIBuilderRef, uint64_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateGlobalVariableExpression = _libraries['llvm'].LLVMDIBuilderCreateGlobalVariableExpression - LLVMDIBuilderCreateGlobalVariableExpression.restype = LLVMMetadataRef - LLVMDIBuilderCreateGlobalVariableExpression.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMMetadataRef, LLVMMetadataRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIGlobalVariableExpressionGetVariable = _libraries['llvm'].LLVMDIGlobalVariableExpressionGetVariable - LLVMDIGlobalVariableExpressionGetVariable.restype = LLVMMetadataRef - LLVMDIGlobalVariableExpressionGetVariable.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIGlobalVariableExpressionGetExpression = _libraries['llvm'].LLVMDIGlobalVariableExpressionGetExpression - LLVMDIGlobalVariableExpressionGetExpression.restype = LLVMMetadataRef - LLVMDIGlobalVariableExpressionGetExpression.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIVariableGetFile = _libraries['llvm'].LLVMDIVariableGetFile - LLVMDIVariableGetFile.restype = LLVMMetadataRef - LLVMDIVariableGetFile.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIVariableGetScope = _libraries['llvm'].LLVMDIVariableGetScope - LLVMDIVariableGetScope.restype = LLVMMetadataRef - LLVMDIVariableGetScope.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIVariableGetLine = _libraries['llvm'].LLVMDIVariableGetLine - LLVMDIVariableGetLine.restype = ctypes.c_uint32 - LLVMDIVariableGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMTemporaryMDNode = _libraries['llvm'].LLVMTemporaryMDNode - LLVMTemporaryMDNode.restype = LLVMMetadataRef - LLVMTemporaryMDNode.argtypes = [LLVMContextRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMetadata)), size_t] -except AttributeError: - pass -try: - LLVMDisposeTemporaryMDNode = _libraries['llvm'].LLVMDisposeTemporaryMDNode - LLVMDisposeTemporaryMDNode.restype = None - LLVMDisposeTemporaryMDNode.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMMetadataReplaceAllUsesWith = _libraries['llvm'].LLVMMetadataReplaceAllUsesWith - LLVMMetadataReplaceAllUsesWith.restype = None - LLVMMetadataReplaceAllUsesWith.argtypes = [LLVMMetadataRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateTempGlobalVariableFwdDecl = _libraries['llvm'].LLVMDIBuilderCreateTempGlobalVariableFwdDecl - LLVMDIBuilderCreateTempGlobalVariableFwdDecl.restype = LLVMMetadataRef - LLVMDIBuilderCreateTempGlobalVariableFwdDecl.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMMetadataRef, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDeclareBefore = _libraries['llvm'].LLVMDIBuilderInsertDeclareBefore - LLVMDIBuilderInsertDeclareBefore.restype = LLVMValueRef - LLVMDIBuilderInsertDeclareBefore.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDeclareAtEnd = _libraries['llvm'].LLVMDIBuilderInsertDeclareAtEnd - LLVMDIBuilderInsertDeclareAtEnd.restype = LLVMValueRef - LLVMDIBuilderInsertDeclareAtEnd.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDbgValueBefore = _libraries['llvm'].LLVMDIBuilderInsertDbgValueBefore - LLVMDIBuilderInsertDbgValueBefore.restype = LLVMValueRef - LLVMDIBuilderInsertDbgValueBefore.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMDIBuilderInsertDbgValueAtEnd = _libraries['llvm'].LLVMDIBuilderInsertDbgValueAtEnd - LLVMDIBuilderInsertDbgValueAtEnd.restype = LLVMValueRef - LLVMDIBuilderInsertDbgValueAtEnd.argtypes = [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] -except AttributeError: - pass -try: - LLVMDIBuilderCreateAutoVariable = _libraries['llvm'].LLVMDIBuilderCreateAutoVariable - LLVMDIBuilderCreateAutoVariable.restype = LLVMMetadataRef - LLVMDIBuilderCreateAutoVariable.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMDIFlags, uint32_t] -except AttributeError: - pass -try: - LLVMDIBuilderCreateParameterVariable = _libraries['llvm'].LLVMDIBuilderCreateParameterVariable - LLVMDIBuilderCreateParameterVariable.restype = LLVMMetadataRef - LLVMDIBuilderCreateParameterVariable.argtypes = [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMDIFlags] -except AttributeError: - pass -try: - LLVMGetSubprogram = _libraries['llvm'].LLVMGetSubprogram - LLVMGetSubprogram.restype = LLVMMetadataRef - LLVMGetSubprogram.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMSetSubprogram = _libraries['llvm'].LLVMSetSubprogram - LLVMSetSubprogram.restype = None - LLVMSetSubprogram.argtypes = [LLVMValueRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMDISubprogramGetLine = _libraries['llvm'].LLVMDISubprogramGetLine - LLVMDISubprogramGetLine.restype = ctypes.c_uint32 - LLVMDISubprogramGetLine.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMInstructionGetDebugLoc = _libraries['llvm'].LLVMInstructionGetDebugLoc - LLVMInstructionGetDebugLoc.restype = LLVMMetadataRef - LLVMInstructionGetDebugLoc.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - LLVMInstructionSetDebugLoc = _libraries['llvm'].LLVMInstructionSetDebugLoc - LLVMInstructionSetDebugLoc.restype = None - LLVMInstructionSetDebugLoc.argtypes = [LLVMValueRef, LLVMMetadataRef] -except AttributeError: - pass -try: - LLVMGetMetadataKind = _libraries['llvm'].LLVMGetMetadataKind - LLVMGetMetadataKind.restype = LLVMMetadataKind - LLVMGetMetadataKind.argtypes = [LLVMMetadataRef] -except AttributeError: - pass -LLVM_C_DISASSEMBLER_H = True # macro -LLVM_C_DISASSEMBLERTYPES_H = True # macro -LLVMDisassembler_VariantKind_None = 0 # macro -LLVMDisassembler_VariantKind_ARM_HI16 = 1 # macro -LLVMDisassembler_VariantKind_ARM_LO16 = 2 # macro -LLVMDisassembler_VariantKind_ARM64_PAGE = 1 # macro -LLVMDisassembler_VariantKind_ARM64_PAGEOFF = 2 # macro -LLVMDisassembler_VariantKind_ARM64_GOTPAGE = 3 # macro -LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF = 4 # macro -LLVMDisassembler_VariantKind_ARM64_TLVP = 5 # macro -LLVMDisassembler_VariantKind_ARM64_TLVOFF = 6 # macro -LLVMDisassembler_ReferenceType_InOut_None = 0 # macro -LLVMDisassembler_ReferenceType_In_Branch = 1 # macro -LLVMDisassembler_ReferenceType_In_PCrel_Load = 2 # macro -LLVMDisassembler_ReferenceType_In_ARM64_ADRP = 0x100000001 # macro -LLVMDisassembler_ReferenceType_In_ARM64_ADDXri = 0x100000002 # macro -LLVMDisassembler_ReferenceType_In_ARM64_LDRXui = 0x100000003 # macro -LLVMDisassembler_ReferenceType_In_ARM64_LDRXl = 0x100000004 # macro -LLVMDisassembler_ReferenceType_In_ARM64_ADR = 0x100000005 # macro -LLVMDisassembler_ReferenceType_Out_SymbolStub = 1 # macro -LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr = 2 # macro -LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr = 3 # macro -LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref = 4 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Message = 5 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref = 6 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref = 7 # macro -LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref = 8 # macro -LLVMDisassembler_ReferenceType_DeMangled_Name = 9 # macro -LLVMDisassembler_Option_UseMarkup = 1 # macro -LLVMDisassembler_Option_PrintImmHex = 2 # macro -LLVMDisassembler_Option_AsmPrinterVariant = 4 # macro -LLVMDisassembler_Option_SetInstrComments = 8 # macro -LLVMDisassembler_Option_PrintLatency = 16 # macro -LLVMDisasmContextRef = ctypes.POINTER(None) -LLVMOpInfoCallback = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_int32, ctypes.POINTER(None)) -class struct_LLVMOpInfoSymbol1(Structure): - pass +# LLVMMetadataRef LLVMDIBuilderCreateEnumerationType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNumber, uint64_t SizeInBits, uint32_t AlignInBits, LLVMMetadataRef *Elements, unsigned int NumElements, LLVMMetadataRef ClassTy) +try: (LLVMDIBuilderCreateEnumerationType:=dll.LLVMDIBuilderCreateEnumerationType).restype, LLVMDIBuilderCreateEnumerationType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass -struct_LLVMOpInfoSymbol1._pack_ = 1 # source:False +# LLVMMetadataRef LLVMDIBuilderCreateUnionType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNumber, uint64_t SizeInBits, uint32_t AlignInBits, LLVMDIFlags Flags, LLVMMetadataRef *Elements, unsigned int NumElements, unsigned int RunTimeLang, const char *UniqueId, size_t UniqueIdLen) +try: (LLVMDIBuilderCreateUnionType:=dll.LLVMDIBuilderCreateUnionType).restype, LLVMDIBuilderCreateUnionType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateArrayType(LLVMDIBuilderRef Builder, uint64_t Size, uint32_t AlignInBits, LLVMMetadataRef Ty, LLVMMetadataRef *Subscripts, unsigned int NumSubscripts) +try: (LLVMDIBuilderCreateArrayType:=dll.LLVMDIBuilderCreateArrayType).restype, LLVMDIBuilderCreateArrayType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, uint64_t, uint32_t, LLVMMetadataRef, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateVectorType(LLVMDIBuilderRef Builder, uint64_t Size, uint32_t AlignInBits, LLVMMetadataRef Ty, LLVMMetadataRef *Subscripts, unsigned int NumSubscripts) +try: (LLVMDIBuilderCreateVectorType:=dll.LLVMDIBuilderCreateVectorType).restype, LLVMDIBuilderCreateVectorType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, uint64_t, uint32_t, LLVMMetadataRef, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateUnspecifiedType(LLVMDIBuilderRef Builder, const char *Name, size_t NameLen) +try: (LLVMDIBuilderCreateUnspecifiedType:=dll.LLVMDIBuilderCreateUnspecifiedType).restype, LLVMDIBuilderCreateUnspecifiedType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateBasicType(LLVMDIBuilderRef Builder, const char *Name, size_t NameLen, uint64_t SizeInBits, LLVMDWARFTypeEncoding Encoding, LLVMDIFlags Flags) +try: (LLVMDIBuilderCreateBasicType:=dll.LLVMDIBuilderCreateBasicType).restype, LLVMDIBuilderCreateBasicType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, uint64_t, LLVMDWARFTypeEncoding, LLVMDIFlags] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreatePointerType(LLVMDIBuilderRef Builder, LLVMMetadataRef PointeeTy, uint64_t SizeInBits, uint32_t AlignInBits, unsigned int AddressSpace, const char *Name, size_t NameLen) +try: (LLVMDIBuilderCreatePointerType:=dll.LLVMDIBuilderCreatePointerType).restype, LLVMDIBuilderCreatePointerType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, uint64_t, uint32_t, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateStructType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNumber, uint64_t SizeInBits, uint32_t AlignInBits, LLVMDIFlags Flags, LLVMMetadataRef DerivedFrom, LLVMMetadataRef *Elements, unsigned int NumElements, unsigned int RunTimeLang, LLVMMetadataRef VTableHolder, const char *UniqueId, size_t UniqueIdLen) +try: (LLVMDIBuilderCreateStructType:=dll.LLVMDIBuilderCreateStructType).restype, LLVMDIBuilderCreateStructType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, LLVMMetadataRef, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32, ctypes.c_uint32, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateMemberType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNo, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, LLVMDIFlags Flags, LLVMMetadataRef Ty) +try: (LLVMDIBuilderCreateMemberType:=dll.LLVMDIBuilderCreateMemberType).restype, LLVMDIBuilderCreateMemberType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateStaticMemberType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNumber, LLVMMetadataRef Type, LLVMDIFlags Flags, LLVMValueRef ConstantVal, uint32_t AlignInBits) +try: (LLVMDIBuilderCreateStaticMemberType:=dll.LLVMDIBuilderCreateStaticMemberType).restype, LLVMDIBuilderCreateStaticMemberType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMDIFlags, LLVMValueRef, uint32_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateMemberPointerType(LLVMDIBuilderRef Builder, LLVMMetadataRef PointeeType, LLVMMetadataRef ClassType, uint64_t SizeInBits, uint32_t AlignInBits, LLVMDIFlags Flags) +try: (LLVMDIBuilderCreateMemberPointerType:=dll.LLVMDIBuilderCreateMemberPointerType).restype, LLVMDIBuilderCreateMemberPointerType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, uint64_t, uint32_t, LLVMDIFlags] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateObjCIVar(LLVMDIBuilderRef Builder, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNo, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, LLVMDIFlags Flags, LLVMMetadataRef Ty, LLVMMetadataRef PropertyNode) +try: (LLVMDIBuilderCreateObjCIVar:=dll.LLVMDIBuilderCreateObjCIVar).restype, LLVMDIBuilderCreateObjCIVar.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateObjCProperty(LLVMDIBuilderRef Builder, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNo, const char *GetterName, size_t GetterNameLen, const char *SetterName, size_t SetterNameLen, unsigned int PropertyAttributes, LLVMMetadataRef Ty) +try: (LLVMDIBuilderCreateObjCProperty:=dll.LLVMDIBuilderCreateObjCProperty).restype, LLVMDIBuilderCreateObjCProperty.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateObjectPointerType(LLVMDIBuilderRef Builder, LLVMMetadataRef Type, LLVMBool Implicit) +try: (LLVMDIBuilderCreateObjectPointerType:=dll.LLVMDIBuilderCreateObjectPointerType).restype, LLVMDIBuilderCreateObjectPointerType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMBool] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateQualifiedType(LLVMDIBuilderRef Builder, unsigned int Tag, LLVMMetadataRef Type) +try: (LLVMDIBuilderCreateQualifiedType:=dll.LLVMDIBuilderCreateQualifiedType).restype, LLVMDIBuilderCreateQualifiedType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateReferenceType(LLVMDIBuilderRef Builder, unsigned int Tag, LLVMMetadataRef Type) +try: (LLVMDIBuilderCreateReferenceType:=dll.LLVMDIBuilderCreateReferenceType).restype, LLVMDIBuilderCreateReferenceType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.c_uint32, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateNullPtrType(LLVMDIBuilderRef Builder) +try: (LLVMDIBuilderCreateNullPtrType:=dll.LLVMDIBuilderCreateNullPtrType).restype, LLVMDIBuilderCreateNullPtrType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateTypedef(LLVMDIBuilderRef Builder, LLVMMetadataRef Type, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNo, LLVMMetadataRef Scope, uint32_t AlignInBits) +try: (LLVMDIBuilderCreateTypedef:=dll.LLVMDIBuilderCreateTypedef).restype, LLVMDIBuilderCreateTypedef.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, uint32_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateInheritance(LLVMDIBuilderRef Builder, LLVMMetadataRef Ty, LLVMMetadataRef BaseTy, uint64_t BaseOffset, uint32_t VBPtrOffset, LLVMDIFlags Flags) +try: (LLVMDIBuilderCreateInheritance:=dll.LLVMDIBuilderCreateInheritance).restype, LLVMDIBuilderCreateInheritance.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, uint64_t, uint32_t, LLVMDIFlags] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateForwardDecl(LLVMDIBuilderRef Builder, unsigned int Tag, const char *Name, size_t NameLen, LLVMMetadataRef Scope, LLVMMetadataRef File, unsigned int Line, unsigned int RuntimeLang, uint64_t SizeInBits, uint32_t AlignInBits, const char *UniqueIdentifier, size_t UniqueIdentifierLen) +try: (LLVMDIBuilderCreateForwardDecl:=dll.LLVMDIBuilderCreateForwardDecl).restype, LLVMDIBuilderCreateForwardDecl.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32, uint64_t, uint32_t, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateReplaceableCompositeType(LLVMDIBuilderRef Builder, unsigned int Tag, const char *Name, size_t NameLen, LLVMMetadataRef Scope, LLVMMetadataRef File, unsigned int Line, unsigned int RuntimeLang, uint64_t SizeInBits, uint32_t AlignInBits, LLVMDIFlags Flags, const char *UniqueIdentifier, size_t UniqueIdentifierLen) +try: (LLVMDIBuilderCreateReplaceableCompositeType:=dll.LLVMDIBuilderCreateReplaceableCompositeType).restype, LLVMDIBuilderCreateReplaceableCompositeType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, LLVMMetadataRef, ctypes.c_uint32, ctypes.c_uint32, uint64_t, uint32_t, LLVMDIFlags, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateBitFieldMemberType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNumber, uint64_t SizeInBits, uint64_t OffsetInBits, uint64_t StorageOffsetInBits, LLVMDIFlags Flags, LLVMMetadataRef Type) +try: (LLVMDIBuilderCreateBitFieldMemberType:=dll.LLVMDIBuilderCreateBitFieldMemberType).restype, LLVMDIBuilderCreateBitFieldMemberType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint64_t, uint64_t, LLVMDIFlags, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateClassType(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNumber, uint64_t SizeInBits, uint32_t AlignInBits, uint64_t OffsetInBits, LLVMDIFlags Flags, LLVMMetadataRef DerivedFrom, LLVMMetadataRef *Elements, unsigned int NumElements, LLVMMetadataRef VTableHolder, LLVMMetadataRef TemplateParamsNode, const char *UniqueIdentifier, size_t UniqueIdentifierLen) +try: (LLVMDIBuilderCreateClassType:=dll.LLVMDIBuilderCreateClassType).restype, LLVMDIBuilderCreateClassType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, uint64_t, uint32_t, uint64_t, LLVMDIFlags, LLVMMetadataRef, ctypes.POINTER(LLVMMetadataRef), ctypes.c_uint32, LLVMMetadataRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateArtificialType(LLVMDIBuilderRef Builder, LLVMMetadataRef Type) +try: (LLVMDIBuilderCreateArtificialType:=dll.LLVMDIBuilderCreateArtificialType).restype, LLVMDIBuilderCreateArtificialType.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef] +except AttributeError: pass + +# const char *LLVMDITypeGetName(LLVMMetadataRef DType, size_t *Length) +try: (LLVMDITypeGetName:=dll.LLVMDITypeGetName).restype, LLVMDITypeGetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMMetadataRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# uint64_t LLVMDITypeGetSizeInBits(LLVMMetadataRef DType) +try: (LLVMDITypeGetSizeInBits:=dll.LLVMDITypeGetSizeInBits).restype, LLVMDITypeGetSizeInBits.argtypes = uint64_t, [LLVMMetadataRef] +except AttributeError: pass + +# uint64_t LLVMDITypeGetOffsetInBits(LLVMMetadataRef DType) +try: (LLVMDITypeGetOffsetInBits:=dll.LLVMDITypeGetOffsetInBits).restype, LLVMDITypeGetOffsetInBits.argtypes = uint64_t, [LLVMMetadataRef] +except AttributeError: pass + +# uint32_t LLVMDITypeGetAlignInBits(LLVMMetadataRef DType) +try: (LLVMDITypeGetAlignInBits:=dll.LLVMDITypeGetAlignInBits).restype, LLVMDITypeGetAlignInBits.argtypes = uint32_t, [LLVMMetadataRef] +except AttributeError: pass + +# unsigned int LLVMDITypeGetLine(LLVMMetadataRef DType) +try: (LLVMDITypeGetLine:=dll.LLVMDITypeGetLine).restype, LLVMDITypeGetLine.argtypes = ctypes.c_uint32, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMDIFlags LLVMDITypeGetFlags(LLVMMetadataRef DType) +try: (LLVMDITypeGetFlags:=dll.LLVMDITypeGetFlags).restype, LLVMDITypeGetFlags.argtypes = LLVMDIFlags, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderGetOrCreateSubrange(LLVMDIBuilderRef Builder, int64_t LowerBound, int64_t Count) +try: (LLVMDIBuilderGetOrCreateSubrange:=dll.LLVMDIBuilderGetOrCreateSubrange).restype, LLVMDIBuilderGetOrCreateSubrange.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, int64_t, int64_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderGetOrCreateArray(LLVMDIBuilderRef Builder, LLVMMetadataRef *Data, size_t NumElements) +try: (LLVMDIBuilderGetOrCreateArray:=dll.LLVMDIBuilderGetOrCreateArray).restype, LLVMDIBuilderGetOrCreateArray.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(LLVMMetadataRef), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateExpression(LLVMDIBuilderRef Builder, uint64_t *Addr, size_t Length) +try: (LLVMDIBuilderCreateExpression:=dll.LLVMDIBuilderCreateExpression).restype, LLVMDIBuilderCreateExpression.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, ctypes.POINTER(uint64_t), size_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateConstantValueExpression(LLVMDIBuilderRef Builder, uint64_t Value) +try: (LLVMDIBuilderCreateConstantValueExpression:=dll.LLVMDIBuilderCreateConstantValueExpression).restype, LLVMDIBuilderCreateConstantValueExpression.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, uint64_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateGlobalVariableExpression(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, const char *Linkage, size_t LinkLen, LLVMMetadataRef File, unsigned int LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit, LLVMMetadataRef Expr, LLVMMetadataRef Decl, uint32_t AlignInBits) +try: (LLVMDIBuilderCreateGlobalVariableExpression:=dll.LLVMDIBuilderCreateGlobalVariableExpression).restype, LLVMDIBuilderCreateGlobalVariableExpression.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMMetadataRef, LLVMMetadataRef, uint32_t] +except AttributeError: pass + +uint16_t = ctypes.c_uint16 +# uint16_t LLVMGetDINodeTag(LLVMMetadataRef MD) +try: (LLVMGetDINodeTag:=dll.LLVMGetDINodeTag).restype, LLVMGetDINodeTag.argtypes = uint16_t, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIGlobalVariableExpressionGetVariable(LLVMMetadataRef GVE) +try: (LLVMDIGlobalVariableExpressionGetVariable:=dll.LLVMDIGlobalVariableExpressionGetVariable).restype, LLVMDIGlobalVariableExpressionGetVariable.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIGlobalVariableExpressionGetExpression(LLVMMetadataRef GVE) +try: (LLVMDIGlobalVariableExpressionGetExpression:=dll.LLVMDIGlobalVariableExpressionGetExpression).restype, LLVMDIGlobalVariableExpressionGetExpression.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIVariableGetFile(LLVMMetadataRef Var) +try: (LLVMDIVariableGetFile:=dll.LLVMDIVariableGetFile).restype, LLVMDIVariableGetFile.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIVariableGetScope(LLVMMetadataRef Var) +try: (LLVMDIVariableGetScope:=dll.LLVMDIVariableGetScope).restype, LLVMDIVariableGetScope.argtypes = LLVMMetadataRef, [LLVMMetadataRef] +except AttributeError: pass + +# unsigned int LLVMDIVariableGetLine(LLVMMetadataRef Var) +try: (LLVMDIVariableGetLine:=dll.LLVMDIVariableGetLine).restype, LLVMDIVariableGetLine.argtypes = ctypes.c_uint32, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMTemporaryMDNode(LLVMContextRef Ctx, LLVMMetadataRef *Data, size_t NumElements) +try: (LLVMTemporaryMDNode:=dll.LLVMTemporaryMDNode).restype, LLVMTemporaryMDNode.argtypes = LLVMMetadataRef, [LLVMContextRef, ctypes.POINTER(LLVMMetadataRef), size_t] +except AttributeError: pass + +# void LLVMDisposeTemporaryMDNode(LLVMMetadataRef TempNode) +try: (LLVMDisposeTemporaryMDNode:=dll.LLVMDisposeTemporaryMDNode).restype, LLVMDisposeTemporaryMDNode.argtypes = None, [LLVMMetadataRef] +except AttributeError: pass + +# void LLVMMetadataReplaceAllUsesWith(LLVMMetadataRef TempTargetMetadata, LLVMMetadataRef Replacement) +try: (LLVMMetadataReplaceAllUsesWith:=dll.LLVMMetadataReplaceAllUsesWith).restype, LLVMMetadataReplaceAllUsesWith.argtypes = None, [LLVMMetadataRef, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateTempGlobalVariableFwdDecl(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, const char *Linkage, size_t LnkLen, LLVMMetadataRef File, unsigned int LineNo, LLVMMetadataRef Ty, LLVMBool LocalToUnit, LLVMMetadataRef Decl, uint32_t AlignInBits) +try: (LLVMDIBuilderCreateTempGlobalVariableFwdDecl:=dll.LLVMDIBuilderCreateTempGlobalVariableFwdDecl).restype, LLVMDIBuilderCreateTempGlobalVariableFwdDecl.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMMetadataRef, uint32_t] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMDIBuilderInsertDeclareRecordBefore(LLVMDIBuilderRef Builder, LLVMValueRef Storage, LLVMMetadataRef VarInfo, LLVMMetadataRef Expr, LLVMMetadataRef DebugLoc, LLVMValueRef Instr) +try: (LLVMDIBuilderInsertDeclareRecordBefore:=dll.LLVMDIBuilderInsertDeclareRecordBefore).restype, LLVMDIBuilderInsertDeclareRecordBefore.argtypes = LLVMDbgRecordRef, [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMDIBuilderInsertDeclareRecordAtEnd(LLVMDIBuilderRef Builder, LLVMValueRef Storage, LLVMMetadataRef VarInfo, LLVMMetadataRef Expr, LLVMMetadataRef DebugLoc, LLVMBasicBlockRef Block) +try: (LLVMDIBuilderInsertDeclareRecordAtEnd:=dll.LLVMDIBuilderInsertDeclareRecordAtEnd).restype, LLVMDIBuilderInsertDeclareRecordAtEnd.argtypes = LLVMDbgRecordRef, [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMDIBuilderInsertDbgValueRecordBefore(LLVMDIBuilderRef Builder, LLVMValueRef Val, LLVMMetadataRef VarInfo, LLVMMetadataRef Expr, LLVMMetadataRef DebugLoc, LLVMValueRef Instr) +try: (LLVMDIBuilderInsertDbgValueRecordBefore:=dll.LLVMDIBuilderInsertDbgValueRecordBefore).restype, LLVMDIBuilderInsertDbgValueRecordBefore.argtypes = LLVMDbgRecordRef, [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMDIBuilderInsertDbgValueRecordAtEnd(LLVMDIBuilderRef Builder, LLVMValueRef Val, LLVMMetadataRef VarInfo, LLVMMetadataRef Expr, LLVMMetadataRef DebugLoc, LLVMBasicBlockRef Block) +try: (LLVMDIBuilderInsertDbgValueRecordAtEnd:=dll.LLVMDIBuilderInsertDbgValueRecordAtEnd).restype, LLVMDIBuilderInsertDbgValueRecordAtEnd.argtypes = LLVMDbgRecordRef, [LLVMDIBuilderRef, LLVMValueRef, LLVMMetadataRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateAutoVariable(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNo, LLVMMetadataRef Ty, LLVMBool AlwaysPreserve, LLVMDIFlags Flags, uint32_t AlignInBits) +try: (LLVMDIBuilderCreateAutoVariable:=dll.LLVMDIBuilderCreateAutoVariable).restype, LLVMDIBuilderCreateAutoVariable.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMDIFlags, uint32_t] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateParameterVariable(LLVMDIBuilderRef Builder, LLVMMetadataRef Scope, const char *Name, size_t NameLen, unsigned int ArgNo, LLVMMetadataRef File, unsigned int LineNo, LLVMMetadataRef Ty, LLVMBool AlwaysPreserve, LLVMDIFlags Flags) +try: (LLVMDIBuilderCreateParameterVariable:=dll.LLVMDIBuilderCreateParameterVariable).restype, LLVMDIBuilderCreateParameterVariable.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.c_uint32, LLVMMetadataRef, ctypes.c_uint32, LLVMMetadataRef, LLVMBool, LLVMDIFlags] +except AttributeError: pass + +# LLVMMetadataRef LLVMGetSubprogram(LLVMValueRef Func) +try: (LLVMGetSubprogram:=dll.LLVMGetSubprogram).restype, LLVMGetSubprogram.argtypes = LLVMMetadataRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMSetSubprogram(LLVMValueRef Func, LLVMMetadataRef SP) +try: (LLVMSetSubprogram:=dll.LLVMSetSubprogram).restype, LLVMSetSubprogram.argtypes = None, [LLVMValueRef, LLVMMetadataRef] +except AttributeError: pass + +# unsigned int LLVMDISubprogramGetLine(LLVMMetadataRef Subprogram) +try: (LLVMDISubprogramGetLine:=dll.LLVMDISubprogramGetLine).restype, LLVMDISubprogramGetLine.argtypes = ctypes.c_uint32, [LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMInstructionGetDebugLoc(LLVMValueRef Inst) +try: (LLVMInstructionGetDebugLoc:=dll.LLVMInstructionGetDebugLoc).restype, LLVMInstructionGetDebugLoc.argtypes = LLVMMetadataRef, [LLVMValueRef] +except AttributeError: pass + +# void LLVMInstructionSetDebugLoc(LLVMValueRef Inst, LLVMMetadataRef Loc) +try: (LLVMInstructionSetDebugLoc:=dll.LLVMInstructionSetDebugLoc).restype, LLVMInstructionSetDebugLoc.argtypes = None, [LLVMValueRef, LLVMMetadataRef] +except AttributeError: pass + +# LLVMMetadataRef LLVMDIBuilderCreateLabel(LLVMDIBuilderRef Builder, LLVMMetadataRef Context, const char *Name, size_t NameLen, LLVMMetadataRef File, unsigned int LineNo, LLVMBool AlwaysPreserve) +try: (LLVMDIBuilderCreateLabel:=dll.LLVMDIBuilderCreateLabel).restype, LLVMDIBuilderCreateLabel.argtypes = LLVMMetadataRef, [LLVMDIBuilderRef, LLVMMetadataRef, ctypes.POINTER(ctypes.c_char), size_t, LLVMMetadataRef, ctypes.c_uint32, LLVMBool] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMDIBuilderInsertLabelBefore(LLVMDIBuilderRef Builder, LLVMMetadataRef LabelInfo, LLVMMetadataRef Location, LLVMValueRef InsertBefore) +try: (LLVMDIBuilderInsertLabelBefore:=dll.LLVMDIBuilderInsertLabelBefore).restype, LLVMDIBuilderInsertLabelBefore.argtypes = LLVMDbgRecordRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMValueRef] +except AttributeError: pass + +# LLVMDbgRecordRef LLVMDIBuilderInsertLabelAtEnd(LLVMDIBuilderRef Builder, LLVMMetadataRef LabelInfo, LLVMMetadataRef Location, LLVMBasicBlockRef InsertAtEnd) +try: (LLVMDIBuilderInsertLabelAtEnd:=dll.LLVMDIBuilderInsertLabelAtEnd).restype, LLVMDIBuilderInsertLabelAtEnd.argtypes = LLVMDbgRecordRef, [LLVMDIBuilderRef, LLVMMetadataRef, LLVMMetadataRef, LLVMBasicBlockRef] +except AttributeError: pass + +# LLVMMetadataKind LLVMGetMetadataKind(LLVMMetadataRef Metadata) +try: (LLVMGetMetadataKind:=dll.LLVMGetMetadataKind).restype, LLVMGetMetadataKind.argtypes = LLVMMetadataKind, [LLVMMetadataRef] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +LLVMDisasmContextRef = ctypes.c_void_p +LLVMOpInfoCallback = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_void_p, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_int32, ctypes.c_void_p) +LLVMSymbolLookupCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))) +# LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp) +try: (LLVMCreateDisasm:=dll.LLVMCreateDisasm).restype, LLVMCreateDisasm.argtypes = LLVMDisasmContextRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] +except AttributeError: pass + +# LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp) +try: (LLVMCreateDisasmCPU:=dll.LLVMCreateDisasmCPU).restype, LLVMCreateDisasmCPU.argtypes = LLVMDisasmContextRef, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] +except AttributeError: pass + +# LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *Triple, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp) +try: (LLVMCreateDisasmCPUFeatures:=dll.LLVMCreateDisasmCPUFeatures).restype, LLVMCreateDisasmCPUFeatures.argtypes = LLVMDisasmContextRef, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] +except AttributeError: pass + +# int LLVMSetDisasmOptions(LLVMDisasmContextRef DC, uint64_t Options) +try: (LLVMSetDisasmOptions:=dll.LLVMSetDisasmOptions).restype, LLVMSetDisasmOptions.argtypes = ctypes.c_int32, [LLVMDisasmContextRef, uint64_t] +except AttributeError: pass + +# void LLVMDisasmDispose(LLVMDisasmContextRef DC) +try: (LLVMDisasmDispose:=dll.LLVMDisasmDispose).restype, LLVMDisasmDispose.argtypes = None, [LLVMDisasmContextRef] +except AttributeError: pass + +# size_t LLVMDisasmInstruction(LLVMDisasmContextRef DC, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize) +try: (LLVMDisasmInstruction:=dll.LLVMDisasmInstruction).restype, LLVMDisasmInstruction.argtypes = size_t, [LLVMDisasmContextRef, ctypes.POINTER(uint8_t), uint64_t, uint64_t, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +class struct_LLVMOpInfoSymbol1(Struct): pass struct_LLVMOpInfoSymbol1._fields_ = [ - ('Present', ctypes.c_uint64), - ('Name', ctypes.POINTER(ctypes.c_char)), - ('Value', ctypes.c_uint64), + ('Present', uint64_t), + ('Name', ctypes.POINTER(ctypes.c_char)), + ('Value', uint64_t), ] - -class struct_LLVMOpInfo1(Structure): - pass - -struct_LLVMOpInfo1._pack_ = 1 # source:False +class struct_LLVMOpInfo1(Struct): pass struct_LLVMOpInfo1._fields_ = [ - ('AddSymbol', struct_LLVMOpInfoSymbol1), - ('SubtractSymbol', struct_LLVMOpInfoSymbol1), - ('Value', ctypes.c_uint64), - ('VariantKind', ctypes.c_uint64), + ('AddSymbol', struct_LLVMOpInfoSymbol1), + ('SubtractSymbol', struct_LLVMOpInfoSymbol1), + ('Value', uint64_t), + ('VariantKind', uint64_t), ] - -LLVMSymbolLookupCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))) -try: - LLVMCreateDisasm = _libraries['llvm'].LLVMCreateDisasm - LLVMCreateDisasm.restype = LLVMDisasmContextRef - LLVMCreateDisasm.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] -except AttributeError: - pass -try: - LLVMCreateDisasmCPU = _libraries['llvm'].LLVMCreateDisasmCPU - LLVMCreateDisasmCPU.restype = LLVMDisasmContextRef - LLVMCreateDisasmCPU.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] -except AttributeError: - pass -try: - LLVMCreateDisasmCPUFeatures = _libraries['llvm'].LLVMCreateDisasmCPUFeatures - LLVMCreateDisasmCPUFeatures.restype = LLVMDisasmContextRef - LLVMCreateDisasmCPUFeatures.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_int32, LLVMOpInfoCallback, LLVMSymbolLookupCallback] -except AttributeError: - pass -try: - LLVMSetDisasmOptions = _libraries['llvm'].LLVMSetDisasmOptions - LLVMSetDisasmOptions.restype = ctypes.c_int32 - LLVMSetDisasmOptions.argtypes = [LLVMDisasmContextRef, uint64_t] -except AttributeError: - pass -try: - LLVMDisasmDispose = _libraries['llvm'].LLVMDisasmDispose - LLVMDisasmDispose.restype = None - LLVMDisasmDispose.argtypes = [LLVMDisasmContextRef] -except AttributeError: - pass -try: - LLVMDisasmInstruction = _libraries['llvm'].LLVMDisasmInstruction - LLVMDisasmInstruction.restype = size_t - LLVMDisasmInstruction.argtypes = [LLVMDisasmContextRef, ctypes.POINTER(ctypes.c_ubyte), uint64_t, uint64_t, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -LLVM_C_ERROR_H = True # macro -LLVMErrorSuccess = 0 # macro -class struct_LLVMOpaqueError(Structure): - pass - +class struct_LLVMOpaqueError(Struct): pass LLVMErrorRef = ctypes.POINTER(struct_LLVMOpaqueError) -LLVMErrorTypeId = ctypes.POINTER(None) -try: - LLVMGetErrorTypeId = _libraries['llvm'].LLVMGetErrorTypeId - LLVMGetErrorTypeId.restype = LLVMErrorTypeId - LLVMGetErrorTypeId.argtypes = [LLVMErrorRef] -except AttributeError: - pass -try: - LLVMConsumeError = _libraries['llvm'].LLVMConsumeError - LLVMConsumeError.restype = None - LLVMConsumeError.argtypes = [LLVMErrorRef] -except AttributeError: - pass -try: - LLVMGetErrorMessage = _libraries['llvm'].LLVMGetErrorMessage - LLVMGetErrorMessage.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetErrorMessage.argtypes = [LLVMErrorRef] -except AttributeError: - pass -try: - LLVMDisposeErrorMessage = _libraries['llvm'].LLVMDisposeErrorMessage - LLVMDisposeErrorMessage.restype = None - LLVMDisposeErrorMessage.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetStringErrorTypeId = _libraries['llvm'].LLVMGetStringErrorTypeId - LLVMGetStringErrorTypeId.restype = LLVMErrorTypeId - LLVMGetStringErrorTypeId.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateStringError = _libraries['llvm'].LLVMCreateStringError - LLVMCreateStringError.restype = LLVMErrorRef - LLVMCreateStringError.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -LLVM_C_EXECUTIONENGINE_H = True # macro -LLVM_C_TARGET_H = True # macro -# def LLVM_TARGET(TargetName): # macro -# return LLVMInitialize##TargetName##TargetMC; -# def LLVM_ASM_PRINTER(TargetName): # macro -# return LLVMInitialize##TargetName##AsmPrinter; -# def LLVM_ASM_PARSER(TargetName): # macro -# return LLVMInitialize##TargetName##AsmParser; -# def LLVM_DISASSEMBLER(TargetName): # macro -# return LLVMInitialize##TargetName##Disassembler; -LLVM_C_TARGETMACHINE_H = True # macro +LLVMErrorTypeId = ctypes.c_void_p +# LLVMErrorTypeId LLVMGetErrorTypeId(LLVMErrorRef Err) +try: (LLVMGetErrorTypeId:=dll.LLVMGetErrorTypeId).restype, LLVMGetErrorTypeId.argtypes = LLVMErrorTypeId, [LLVMErrorRef] +except AttributeError: pass -# values for enumeration 'LLVMByteOrdering' -LLVMByteOrdering__enumvalues = { - 0: 'LLVMBigEndian', - 1: 'LLVMLittleEndian', -} -LLVMBigEndian = 0 -LLVMLittleEndian = 1 -LLVMByteOrdering = ctypes.c_uint32 # enum -class struct_LLVMOpaqueTargetData(Structure): - pass +# void LLVMConsumeError(LLVMErrorRef Err) +try: (LLVMConsumeError:=dll.LLVMConsumeError).restype, LLVMConsumeError.argtypes = None, [LLVMErrorRef] +except AttributeError: pass +# void LLVMCantFail(LLVMErrorRef Err) +try: (LLVMCantFail:=dll.LLVMCantFail).restype, LLVMCantFail.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# char *LLVMGetErrorMessage(LLVMErrorRef Err) +try: (LLVMGetErrorMessage:=dll.LLVMGetErrorMessage).restype, LLVMGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMErrorRef] +except AttributeError: pass + +# void LLVMDisposeErrorMessage(char *ErrMsg) +try: (LLVMDisposeErrorMessage:=dll.LLVMDisposeErrorMessage).restype, LLVMDisposeErrorMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetStringErrorTypeId(void) +try: (LLVMGetStringErrorTypeId:=dll.LLVMGetStringErrorTypeId).restype, LLVMGetStringErrorTypeId.argtypes = LLVMErrorTypeId, [] +except AttributeError: pass + +# LLVMErrorRef LLVMCreateStringError(const char *ErrMsg) +try: (LLVMCreateStringError:=dll.LLVMCreateStringError).restype, LLVMCreateStringError.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMInstallFatalErrorHandler(LLVMFatalErrorHandler Handler) +try: (LLVMInstallFatalErrorHandler:=dll.LLVMInstallFatalErrorHandler).restype, LLVMInstallFatalErrorHandler.argtypes = None, [LLVMFatalErrorHandler] +except AttributeError: pass + +# void LLVMResetFatalErrorHandler(void) +try: (LLVMResetFatalErrorHandler:=dll.LLVMResetFatalErrorHandler).restype, LLVMResetFatalErrorHandler.argtypes = None, [] +except AttributeError: pass + +# void LLVMEnablePrettyStackTrace(void) +try: (LLVMEnablePrettyStackTrace:=dll.LLVMEnablePrettyStackTrace).restype, LLVMEnablePrettyStackTrace.argtypes = None, [] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +class struct_LLVMOpaqueTargetData(Struct): pass LLVMTargetDataRef = ctypes.POINTER(struct_LLVMOpaqueTargetData) -class struct_LLVMOpaqueTargetLibraryInfotData(Structure): - pass +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +class struct_LLVMOpaqueTargetLibraryInfotData(Struct): pass LLVMTargetLibraryInfoRef = ctypes.POINTER(struct_LLVMOpaqueTargetLibraryInfotData) -try: - LLVMInitializeAArch64TargetInfo = _libraries['llvm'].LLVMInitializeAArch64TargetInfo - LLVMInitializeAArch64TargetInfo.restype = None - LLVMInitializeAArch64TargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUTargetInfo = _libraries['llvm'].LLVMInitializeAMDGPUTargetInfo - LLVMInitializeAMDGPUTargetInfo.restype = None - LLVMInitializeAMDGPUTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMTargetInfo = _libraries['llvm'].LLVMInitializeARMTargetInfo - LLVMInitializeARMTargetInfo.restype = None - LLVMInitializeARMTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRTargetInfo = _libraries['llvm'].LLVMInitializeAVRTargetInfo - LLVMInitializeAVRTargetInfo.restype = None - LLVMInitializeAVRTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFTargetInfo = _libraries['llvm'].LLVMInitializeBPFTargetInfo - LLVMInitializeBPFTargetInfo.restype = None - LLVMInitializeBPFTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonTargetInfo = _libraries['llvm'].LLVMInitializeHexagonTargetInfo - LLVMInitializeHexagonTargetInfo.restype = None - LLVMInitializeHexagonTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiTargetInfo = _libraries['llvm'].LLVMInitializeLanaiTargetInfo - LLVMInitializeLanaiTargetInfo.restype = None - LLVMInitializeLanaiTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsTargetInfo = _libraries['llvm'].LLVMInitializeMipsTargetInfo - LLVMInitializeMipsTargetInfo.restype = None - LLVMInitializeMipsTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430TargetInfo = _libraries['llvm'].LLVMInitializeMSP430TargetInfo - LLVMInitializeMSP430TargetInfo.restype = None - LLVMInitializeMSP430TargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXTargetInfo = _libraries['llvm'].LLVMInitializeNVPTXTargetInfo - LLVMInitializeNVPTXTargetInfo.restype = None - LLVMInitializeNVPTXTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCTargetInfo = _libraries['llvm'].LLVMInitializePowerPCTargetInfo - LLVMInitializePowerPCTargetInfo.restype = None - LLVMInitializePowerPCTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVTargetInfo = _libraries['llvm'].LLVMInitializeRISCVTargetInfo - LLVMInitializeRISCVTargetInfo.restype = None - LLVMInitializeRISCVTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcTargetInfo = _libraries['llvm'].LLVMInitializeSparcTargetInfo - LLVMInitializeSparcTargetInfo.restype = None - LLVMInitializeSparcTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZTargetInfo = _libraries['llvm'].LLVMInitializeSystemZTargetInfo - LLVMInitializeSystemZTargetInfo.restype = None - LLVMInitializeSystemZTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVETargetInfo = _libraries['llvm'].LLVMInitializeVETargetInfo - LLVMInitializeVETargetInfo.restype = None - LLVMInitializeVETargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyTargetInfo = _libraries['llvm'].LLVMInitializeWebAssemblyTargetInfo - LLVMInitializeWebAssemblyTargetInfo.restype = None - LLVMInitializeWebAssemblyTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86TargetInfo = _libraries['llvm'].LLVMInitializeX86TargetInfo - LLVMInitializeX86TargetInfo.restype = None - LLVMInitializeX86TargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreTargetInfo = _libraries['llvm'].LLVMInitializeXCoreTargetInfo - LLVMInitializeXCoreTargetInfo.restype = None - LLVMInitializeXCoreTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kTargetInfo = _libraries['llvm'].LLVMInitializeM68kTargetInfo - LLVMInitializeM68kTargetInfo.restype = None - LLVMInitializeM68kTargetInfo.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64Target = _libraries['llvm'].LLVMInitializeAArch64Target - LLVMInitializeAArch64Target.restype = None - LLVMInitializeAArch64Target.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUTarget = _libraries['llvm'].LLVMInitializeAMDGPUTarget - LLVMInitializeAMDGPUTarget.restype = None - LLVMInitializeAMDGPUTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMTarget = _libraries['llvm'].LLVMInitializeARMTarget - LLVMInitializeARMTarget.restype = None - LLVMInitializeARMTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRTarget = _libraries['llvm'].LLVMInitializeAVRTarget - LLVMInitializeAVRTarget.restype = None - LLVMInitializeAVRTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFTarget = _libraries['llvm'].LLVMInitializeBPFTarget - LLVMInitializeBPFTarget.restype = None - LLVMInitializeBPFTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonTarget = _libraries['llvm'].LLVMInitializeHexagonTarget - LLVMInitializeHexagonTarget.restype = None - LLVMInitializeHexagonTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiTarget = _libraries['llvm'].LLVMInitializeLanaiTarget - LLVMInitializeLanaiTarget.restype = None - LLVMInitializeLanaiTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsTarget = _libraries['llvm'].LLVMInitializeMipsTarget - LLVMInitializeMipsTarget.restype = None - LLVMInitializeMipsTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430Target = _libraries['llvm'].LLVMInitializeMSP430Target - LLVMInitializeMSP430Target.restype = None - LLVMInitializeMSP430Target.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXTarget = _libraries['llvm'].LLVMInitializeNVPTXTarget - LLVMInitializeNVPTXTarget.restype = None - LLVMInitializeNVPTXTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCTarget = _libraries['llvm'].LLVMInitializePowerPCTarget - LLVMInitializePowerPCTarget.restype = None - LLVMInitializePowerPCTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVTarget = _libraries['llvm'].LLVMInitializeRISCVTarget - LLVMInitializeRISCVTarget.restype = None - LLVMInitializeRISCVTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcTarget = _libraries['llvm'].LLVMInitializeSparcTarget - LLVMInitializeSparcTarget.restype = None - LLVMInitializeSparcTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZTarget = _libraries['llvm'].LLVMInitializeSystemZTarget - LLVMInitializeSystemZTarget.restype = None - LLVMInitializeSystemZTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVETarget = _libraries['llvm'].LLVMInitializeVETarget - LLVMInitializeVETarget.restype = None - LLVMInitializeVETarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyTarget = _libraries['llvm'].LLVMInitializeWebAssemblyTarget - LLVMInitializeWebAssemblyTarget.restype = None - LLVMInitializeWebAssemblyTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86Target = _libraries['llvm'].LLVMInitializeX86Target - LLVMInitializeX86Target.restype = None - LLVMInitializeX86Target.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreTarget = _libraries['llvm'].LLVMInitializeXCoreTarget - LLVMInitializeXCoreTarget.restype = None - LLVMInitializeXCoreTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kTarget = _libraries['llvm'].LLVMInitializeM68kTarget - LLVMInitializeM68kTarget.restype = None - LLVMInitializeM68kTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64TargetMC = _libraries['llvm'].LLVMInitializeAArch64TargetMC - LLVMInitializeAArch64TargetMC.restype = None - LLVMInitializeAArch64TargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUTargetMC = _libraries['llvm'].LLVMInitializeAMDGPUTargetMC - LLVMInitializeAMDGPUTargetMC.restype = None - LLVMInitializeAMDGPUTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMTargetMC = _libraries['llvm'].LLVMInitializeARMTargetMC - LLVMInitializeARMTargetMC.restype = None - LLVMInitializeARMTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRTargetMC = _libraries['llvm'].LLVMInitializeAVRTargetMC - LLVMInitializeAVRTargetMC.restype = None - LLVMInitializeAVRTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFTargetMC = _libraries['llvm'].LLVMInitializeBPFTargetMC - LLVMInitializeBPFTargetMC.restype = None - LLVMInitializeBPFTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonTargetMC = _libraries['llvm'].LLVMInitializeHexagonTargetMC - LLVMInitializeHexagonTargetMC.restype = None - LLVMInitializeHexagonTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiTargetMC = _libraries['llvm'].LLVMInitializeLanaiTargetMC - LLVMInitializeLanaiTargetMC.restype = None - LLVMInitializeLanaiTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsTargetMC = _libraries['llvm'].LLVMInitializeMipsTargetMC - LLVMInitializeMipsTargetMC.restype = None - LLVMInitializeMipsTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430TargetMC = _libraries['llvm'].LLVMInitializeMSP430TargetMC - LLVMInitializeMSP430TargetMC.restype = None - LLVMInitializeMSP430TargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXTargetMC = _libraries['llvm'].LLVMInitializeNVPTXTargetMC - LLVMInitializeNVPTXTargetMC.restype = None - LLVMInitializeNVPTXTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCTargetMC = _libraries['llvm'].LLVMInitializePowerPCTargetMC - LLVMInitializePowerPCTargetMC.restype = None - LLVMInitializePowerPCTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVTargetMC = _libraries['llvm'].LLVMInitializeRISCVTargetMC - LLVMInitializeRISCVTargetMC.restype = None - LLVMInitializeRISCVTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcTargetMC = _libraries['llvm'].LLVMInitializeSparcTargetMC - LLVMInitializeSparcTargetMC.restype = None - LLVMInitializeSparcTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZTargetMC = _libraries['llvm'].LLVMInitializeSystemZTargetMC - LLVMInitializeSystemZTargetMC.restype = None - LLVMInitializeSystemZTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVETargetMC = _libraries['llvm'].LLVMInitializeVETargetMC - LLVMInitializeVETargetMC.restype = None - LLVMInitializeVETargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyTargetMC = _libraries['llvm'].LLVMInitializeWebAssemblyTargetMC - LLVMInitializeWebAssemblyTargetMC.restype = None - LLVMInitializeWebAssemblyTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86TargetMC = _libraries['llvm'].LLVMInitializeX86TargetMC - LLVMInitializeX86TargetMC.restype = None - LLVMInitializeX86TargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreTargetMC = _libraries['llvm'].LLVMInitializeXCoreTargetMC - LLVMInitializeXCoreTargetMC.restype = None - LLVMInitializeXCoreTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kTargetMC = _libraries['llvm'].LLVMInitializeM68kTargetMC - LLVMInitializeM68kTargetMC.restype = None - LLVMInitializeM68kTargetMC.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64AsmPrinter = _libraries['llvm'].LLVMInitializeAArch64AsmPrinter - LLVMInitializeAArch64AsmPrinter.restype = None - LLVMInitializeAArch64AsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUAsmPrinter = _libraries['llvm'].LLVMInitializeAMDGPUAsmPrinter - LLVMInitializeAMDGPUAsmPrinter.restype = None - LLVMInitializeAMDGPUAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMAsmPrinter = _libraries['llvm'].LLVMInitializeARMAsmPrinter - LLVMInitializeARMAsmPrinter.restype = None - LLVMInitializeARMAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRAsmPrinter = _libraries['llvm'].LLVMInitializeAVRAsmPrinter - LLVMInitializeAVRAsmPrinter.restype = None - LLVMInitializeAVRAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFAsmPrinter = _libraries['llvm'].LLVMInitializeBPFAsmPrinter - LLVMInitializeBPFAsmPrinter.restype = None - LLVMInitializeBPFAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonAsmPrinter = _libraries['llvm'].LLVMInitializeHexagonAsmPrinter - LLVMInitializeHexagonAsmPrinter.restype = None - LLVMInitializeHexagonAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiAsmPrinter = _libraries['llvm'].LLVMInitializeLanaiAsmPrinter - LLVMInitializeLanaiAsmPrinter.restype = None - LLVMInitializeLanaiAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsAsmPrinter = _libraries['llvm'].LLVMInitializeMipsAsmPrinter - LLVMInitializeMipsAsmPrinter.restype = None - LLVMInitializeMipsAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430AsmPrinter = _libraries['llvm'].LLVMInitializeMSP430AsmPrinter - LLVMInitializeMSP430AsmPrinter.restype = None - LLVMInitializeMSP430AsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNVPTXAsmPrinter = _libraries['llvm'].LLVMInitializeNVPTXAsmPrinter - LLVMInitializeNVPTXAsmPrinter.restype = None - LLVMInitializeNVPTXAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCAsmPrinter = _libraries['llvm'].LLVMInitializePowerPCAsmPrinter - LLVMInitializePowerPCAsmPrinter.restype = None - LLVMInitializePowerPCAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVAsmPrinter = _libraries['llvm'].LLVMInitializeRISCVAsmPrinter - LLVMInitializeRISCVAsmPrinter.restype = None - LLVMInitializeRISCVAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcAsmPrinter = _libraries['llvm'].LLVMInitializeSparcAsmPrinter - LLVMInitializeSparcAsmPrinter.restype = None - LLVMInitializeSparcAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZAsmPrinter = _libraries['llvm'].LLVMInitializeSystemZAsmPrinter - LLVMInitializeSystemZAsmPrinter.restype = None - LLVMInitializeSystemZAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVEAsmPrinter = _libraries['llvm'].LLVMInitializeVEAsmPrinter - LLVMInitializeVEAsmPrinter.restype = None - LLVMInitializeVEAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyAsmPrinter = _libraries['llvm'].LLVMInitializeWebAssemblyAsmPrinter - LLVMInitializeWebAssemblyAsmPrinter.restype = None - LLVMInitializeWebAssemblyAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86AsmPrinter = _libraries['llvm'].LLVMInitializeX86AsmPrinter - LLVMInitializeX86AsmPrinter.restype = None - LLVMInitializeX86AsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreAsmPrinter = _libraries['llvm'].LLVMInitializeXCoreAsmPrinter - LLVMInitializeXCoreAsmPrinter.restype = None - LLVMInitializeXCoreAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kAsmPrinter = _libraries['llvm'].LLVMInitializeM68kAsmPrinter - LLVMInitializeM68kAsmPrinter.restype = None - LLVMInitializeM68kAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64AsmParser = _libraries['llvm'].LLVMInitializeAArch64AsmParser - LLVMInitializeAArch64AsmParser.restype = None - LLVMInitializeAArch64AsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUAsmParser = _libraries['llvm'].LLVMInitializeAMDGPUAsmParser - LLVMInitializeAMDGPUAsmParser.restype = None - LLVMInitializeAMDGPUAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMAsmParser = _libraries['llvm'].LLVMInitializeARMAsmParser - LLVMInitializeARMAsmParser.restype = None - LLVMInitializeARMAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRAsmParser = _libraries['llvm'].LLVMInitializeAVRAsmParser - LLVMInitializeAVRAsmParser.restype = None - LLVMInitializeAVRAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFAsmParser = _libraries['llvm'].LLVMInitializeBPFAsmParser - LLVMInitializeBPFAsmParser.restype = None - LLVMInitializeBPFAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonAsmParser = _libraries['llvm'].LLVMInitializeHexagonAsmParser - LLVMInitializeHexagonAsmParser.restype = None - LLVMInitializeHexagonAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiAsmParser = _libraries['llvm'].LLVMInitializeLanaiAsmParser - LLVMInitializeLanaiAsmParser.restype = None - LLVMInitializeLanaiAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsAsmParser = _libraries['llvm'].LLVMInitializeMipsAsmParser - LLVMInitializeMipsAsmParser.restype = None - LLVMInitializeMipsAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430AsmParser = _libraries['llvm'].LLVMInitializeMSP430AsmParser - LLVMInitializeMSP430AsmParser.restype = None - LLVMInitializeMSP430AsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCAsmParser = _libraries['llvm'].LLVMInitializePowerPCAsmParser - LLVMInitializePowerPCAsmParser.restype = None - LLVMInitializePowerPCAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVAsmParser = _libraries['llvm'].LLVMInitializeRISCVAsmParser - LLVMInitializeRISCVAsmParser.restype = None - LLVMInitializeRISCVAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcAsmParser = _libraries['llvm'].LLVMInitializeSparcAsmParser - LLVMInitializeSparcAsmParser.restype = None - LLVMInitializeSparcAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZAsmParser = _libraries['llvm'].LLVMInitializeSystemZAsmParser - LLVMInitializeSystemZAsmParser.restype = None - LLVMInitializeSystemZAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVEAsmParser = _libraries['llvm'].LLVMInitializeVEAsmParser - LLVMInitializeVEAsmParser.restype = None - LLVMInitializeVEAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyAsmParser = _libraries['llvm'].LLVMInitializeWebAssemblyAsmParser - LLVMInitializeWebAssemblyAsmParser.restype = None - LLVMInitializeWebAssemblyAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86AsmParser = _libraries['llvm'].LLVMInitializeX86AsmParser - LLVMInitializeX86AsmParser.restype = None - LLVMInitializeX86AsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kAsmParser = _libraries['llvm'].LLVMInitializeM68kAsmParser - LLVMInitializeM68kAsmParser.restype = None - LLVMInitializeM68kAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAArch64Disassembler = _libraries['llvm'].LLVMInitializeAArch64Disassembler - LLVMInitializeAArch64Disassembler.restype = None - LLVMInitializeAArch64Disassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAMDGPUDisassembler = _libraries['llvm'].LLVMInitializeAMDGPUDisassembler - LLVMInitializeAMDGPUDisassembler.restype = None - LLVMInitializeAMDGPUDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeARMDisassembler = _libraries['llvm'].LLVMInitializeARMDisassembler - LLVMInitializeARMDisassembler.restype = None - LLVMInitializeARMDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAVRDisassembler = _libraries['llvm'].LLVMInitializeAVRDisassembler - LLVMInitializeAVRDisassembler.restype = None - LLVMInitializeAVRDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeBPFDisassembler = _libraries['llvm'].LLVMInitializeBPFDisassembler - LLVMInitializeBPFDisassembler.restype = None - LLVMInitializeBPFDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeHexagonDisassembler = _libraries['llvm'].LLVMInitializeHexagonDisassembler - LLVMInitializeHexagonDisassembler.restype = None - LLVMInitializeHexagonDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeLanaiDisassembler = _libraries['llvm'].LLVMInitializeLanaiDisassembler - LLVMInitializeLanaiDisassembler.restype = None - LLVMInitializeLanaiDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMipsDisassembler = _libraries['llvm'].LLVMInitializeMipsDisassembler - LLVMInitializeMipsDisassembler.restype = None - LLVMInitializeMipsDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeMSP430Disassembler = _libraries['llvm'].LLVMInitializeMSP430Disassembler - LLVMInitializeMSP430Disassembler.restype = None - LLVMInitializeMSP430Disassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializePowerPCDisassembler = _libraries['llvm'].LLVMInitializePowerPCDisassembler - LLVMInitializePowerPCDisassembler.restype = None - LLVMInitializePowerPCDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeRISCVDisassembler = _libraries['llvm'].LLVMInitializeRISCVDisassembler - LLVMInitializeRISCVDisassembler.restype = None - LLVMInitializeRISCVDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSparcDisassembler = _libraries['llvm'].LLVMInitializeSparcDisassembler - LLVMInitializeSparcDisassembler.restype = None - LLVMInitializeSparcDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeSystemZDisassembler = _libraries['llvm'].LLVMInitializeSystemZDisassembler - LLVMInitializeSystemZDisassembler.restype = None - LLVMInitializeSystemZDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeVEDisassembler = _libraries['llvm'].LLVMInitializeVEDisassembler - LLVMInitializeVEDisassembler.restype = None - LLVMInitializeVEDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeWebAssemblyDisassembler = _libraries['llvm'].LLVMInitializeWebAssemblyDisassembler - LLVMInitializeWebAssemblyDisassembler.restype = None - LLVMInitializeWebAssemblyDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeX86Disassembler = _libraries['llvm'].LLVMInitializeX86Disassembler - LLVMInitializeX86Disassembler.restype = None - LLVMInitializeX86Disassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeXCoreDisassembler = _libraries['llvm'].LLVMInitializeXCoreDisassembler - LLVMInitializeXCoreDisassembler.restype = None - LLVMInitializeXCoreDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeM68kDisassembler = _libraries['llvm'].LLVMInitializeM68kDisassembler - LLVMInitializeM68kDisassembler.restype = None - LLVMInitializeM68kDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllTargetInfos = _libraries['llvm'].LLVMInitializeAllTargetInfos - LLVMInitializeAllTargetInfos.restype = None - LLVMInitializeAllTargetInfos.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllTargets = _libraries['llvm'].LLVMInitializeAllTargets - LLVMInitializeAllTargets.restype = None - LLVMInitializeAllTargets.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllTargetMCs = _libraries['llvm'].LLVMInitializeAllTargetMCs - LLVMInitializeAllTargetMCs.restype = None - LLVMInitializeAllTargetMCs.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllAsmPrinters = _libraries['llvm'].LLVMInitializeAllAsmPrinters - LLVMInitializeAllAsmPrinters.restype = None - LLVMInitializeAllAsmPrinters.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllAsmParsers = _libraries['llvm'].LLVMInitializeAllAsmParsers - LLVMInitializeAllAsmParsers.restype = None - LLVMInitializeAllAsmParsers.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeAllDisassemblers = _libraries['llvm'].LLVMInitializeAllDisassemblers - LLVMInitializeAllDisassemblers.restype = None - LLVMInitializeAllDisassemblers.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeTarget = _libraries['llvm'].LLVMInitializeNativeTarget - LLVMInitializeNativeTarget.restype = LLVMBool - LLVMInitializeNativeTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeAsmParser = _libraries['llvm'].LLVMInitializeNativeAsmParser - LLVMInitializeNativeAsmParser.restype = LLVMBool - LLVMInitializeNativeAsmParser.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeAsmPrinter = _libraries['llvm'].LLVMInitializeNativeAsmPrinter - LLVMInitializeNativeAsmPrinter.restype = LLVMBool - LLVMInitializeNativeAsmPrinter.argtypes = [] -except AttributeError: - pass -try: - LLVMInitializeNativeDisassembler = _libraries['llvm'].LLVMInitializeNativeDisassembler - LLVMInitializeNativeDisassembler.restype = LLVMBool - LLVMInitializeNativeDisassembler.argtypes = [] -except AttributeError: - pass -try: - LLVMGetModuleDataLayout = _libraries['llvm'].LLVMGetModuleDataLayout - LLVMGetModuleDataLayout.restype = LLVMTargetDataRef - LLVMGetModuleDataLayout.argtypes = [LLVMModuleRef] -except AttributeError: - pass -try: - LLVMSetModuleDataLayout = _libraries['llvm'].LLVMSetModuleDataLayout - LLVMSetModuleDataLayout.restype = None - LLVMSetModuleDataLayout.argtypes = [LLVMModuleRef, LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMCreateTargetData = _libraries['llvm'].LLVMCreateTargetData - LLVMCreateTargetData.restype = LLVMTargetDataRef - LLVMCreateTargetData.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMDisposeTargetData = _libraries['llvm'].LLVMDisposeTargetData - LLVMDisposeTargetData.restype = None - LLVMDisposeTargetData.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMAddTargetLibraryInfo = _libraries['llvm'].LLVMAddTargetLibraryInfo - LLVMAddTargetLibraryInfo.restype = None - LLVMAddTargetLibraryInfo.argtypes = [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMCopyStringRepOfTargetData = _libraries['llvm'].LLVMCopyStringRepOfTargetData - LLVMCopyStringRepOfTargetData.restype = ctypes.POINTER(ctypes.c_char) - LLVMCopyStringRepOfTargetData.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMByteOrder = _libraries['llvm'].LLVMByteOrder - LLVMByteOrder.restype = LLVMByteOrdering - LLVMByteOrder.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMPointerSize = _libraries['llvm'].LLVMPointerSize - LLVMPointerSize.restype = ctypes.c_uint32 - LLVMPointerSize.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMPointerSizeForAS = _libraries['llvm'].LLVMPointerSizeForAS - LLVMPointerSizeForAS.restype = ctypes.c_uint32 - LLVMPointerSizeForAS.argtypes = [LLVMTargetDataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIntPtrType = _libraries['llvm'].LLVMIntPtrType - LLVMIntPtrType.restype = LLVMTypeRef - LLVMIntPtrType.argtypes = [LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMIntPtrTypeForAS = _libraries['llvm'].LLVMIntPtrTypeForAS - LLVMIntPtrTypeForAS.restype = LLVMTypeRef - LLVMIntPtrTypeForAS.argtypes = [LLVMTargetDataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMIntPtrTypeInContext = _libraries['llvm'].LLVMIntPtrTypeInContext - LLVMIntPtrTypeInContext.restype = LLVMTypeRef - LLVMIntPtrTypeInContext.argtypes = [LLVMContextRef, LLVMTargetDataRef] -except AttributeError: - pass -try: - LLVMIntPtrTypeForASInContext = _libraries['llvm'].LLVMIntPtrTypeForASInContext - LLVMIntPtrTypeForASInContext.restype = LLVMTypeRef - LLVMIntPtrTypeForASInContext.argtypes = [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMSizeOfTypeInBits = _libraries['llvm'].LLVMSizeOfTypeInBits - LLVMSizeOfTypeInBits.restype = ctypes.c_uint64 - LLVMSizeOfTypeInBits.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMStoreSizeOfType = _libraries['llvm'].LLVMStoreSizeOfType - LLVMStoreSizeOfType.restype = ctypes.c_uint64 - LLVMStoreSizeOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMABISizeOfType = _libraries['llvm'].LLVMABISizeOfType - LLVMABISizeOfType.restype = ctypes.c_uint64 - LLVMABISizeOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMABIAlignmentOfType = _libraries['llvm'].LLVMABIAlignmentOfType - LLVMABIAlignmentOfType.restype = ctypes.c_uint32 - LLVMABIAlignmentOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMCallFrameAlignmentOfType = _libraries['llvm'].LLVMCallFrameAlignmentOfType - LLVMCallFrameAlignmentOfType.restype = ctypes.c_uint32 - LLVMCallFrameAlignmentOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPreferredAlignmentOfType = _libraries['llvm'].LLVMPreferredAlignmentOfType - LLVMPreferredAlignmentOfType.restype = ctypes.c_uint32 - LLVMPreferredAlignmentOfType.argtypes = [LLVMTargetDataRef, LLVMTypeRef] -except AttributeError: - pass -try: - LLVMPreferredAlignmentOfGlobal = _libraries['llvm'].LLVMPreferredAlignmentOfGlobal - LLVMPreferredAlignmentOfGlobal.restype = ctypes.c_uint32 - LLVMPreferredAlignmentOfGlobal.argtypes = [LLVMTargetDataRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMElementAtOffset = _libraries['llvm'].LLVMElementAtOffset - LLVMElementAtOffset.restype = ctypes.c_uint32 - LLVMElementAtOffset.argtypes = [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] -except AttributeError: - pass -try: - LLVMOffsetOfElement = _libraries['llvm'].LLVMOffsetOfElement - LLVMOffsetOfElement.restype = ctypes.c_uint64 - LLVMOffsetOfElement.argtypes = [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] -except AttributeError: - pass -class struct_LLVMOpaqueTargetMachine(Structure): - pass +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass -LLVMTargetMachineRef = ctypes.POINTER(struct_LLVMOpaqueTargetMachine) -class struct_LLVMTarget(Structure): - pass +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass +enum_LLVMByteOrdering = CEnum(ctypes.c_uint32) +LLVMBigEndian = enum_LLVMByteOrdering.define('LLVMBigEndian', 0) +LLVMLittleEndian = enum_LLVMByteOrdering.define('LLVMLittleEndian', 1) + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +class struct_LLVMTarget(Struct): pass LLVMTargetRef = ctypes.POINTER(struct_LLVMTarget) +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMCodeGenOptLevel' -c__EA_LLVMCodeGenOptLevel__enumvalues = { - 0: 'LLVMCodeGenLevelNone', - 1: 'LLVMCodeGenLevelLess', - 2: 'LLVMCodeGenLevelDefault', - 3: 'LLVMCodeGenLevelAggressive', -} -LLVMCodeGenLevelNone = 0 -LLVMCodeGenLevelLess = 1 -LLVMCodeGenLevelDefault = 2 -LLVMCodeGenLevelAggressive = 3 -c__EA_LLVMCodeGenOptLevel = ctypes.c_uint32 # enum -LLVMCodeGenOptLevel = c__EA_LLVMCodeGenOptLevel -LLVMCodeGenOptLevel__enumvalues = c__EA_LLVMCodeGenOptLevel__enumvalues +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMRelocMode' -c__EA_LLVMRelocMode__enumvalues = { - 0: 'LLVMRelocDefault', - 1: 'LLVMRelocStatic', - 2: 'LLVMRelocPIC', - 3: 'LLVMRelocDynamicNoPic', - 4: 'LLVMRelocROPI', - 5: 'LLVMRelocRWPI', - 6: 'LLVMRelocROPI_RWPI', -} -LLVMRelocDefault = 0 -LLVMRelocStatic = 1 -LLVMRelocPIC = 2 -LLVMRelocDynamicNoPic = 3 -LLVMRelocROPI = 4 -LLVMRelocRWPI = 5 -LLVMRelocROPI_RWPI = 6 -c__EA_LLVMRelocMode = ctypes.c_uint32 # enum -LLVMRelocMode = c__EA_LLVMRelocMode -LLVMRelocMode__enumvalues = c__EA_LLVMRelocMode__enumvalues +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMCodeModel' -c__EA_LLVMCodeModel__enumvalues = { - 0: 'LLVMCodeModelDefault', - 1: 'LLVMCodeModelJITDefault', - 2: 'LLVMCodeModelTiny', - 3: 'LLVMCodeModelSmall', - 4: 'LLVMCodeModelKernel', - 5: 'LLVMCodeModelMedium', - 6: 'LLVMCodeModelLarge', -} -LLVMCodeModelDefault = 0 -LLVMCodeModelJITDefault = 1 -LLVMCodeModelTiny = 2 -LLVMCodeModelSmall = 3 -LLVMCodeModelKernel = 4 -LLVMCodeModelMedium = 5 -LLVMCodeModelLarge = 6 -c__EA_LLVMCodeModel = ctypes.c_uint32 # enum -LLVMCodeModel = c__EA_LLVMCodeModel -LLVMCodeModel__enumvalues = c__EA_LLVMCodeModel__enumvalues +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMCodeGenFileType' -c__EA_LLVMCodeGenFileType__enumvalues = { - 0: 'LLVMAssemblyFile', - 1: 'LLVMObjectFile', -} -LLVMAssemblyFile = 0 -LLVMObjectFile = 1 -c__EA_LLVMCodeGenFileType = ctypes.c_uint32 # enum -LLVMCodeGenFileType = c__EA_LLVMCodeGenFileType -LLVMCodeGenFileType__enumvalues = c__EA_LLVMCodeGenFileType__enumvalues -try: - LLVMGetFirstTarget = _libraries['llvm'].LLVMGetFirstTarget - LLVMGetFirstTarget.restype = LLVMTargetRef - LLVMGetFirstTarget.argtypes = [] -except AttributeError: - pass -try: - LLVMGetNextTarget = _libraries['llvm'].LLVMGetNextTarget - LLVMGetNextTarget.restype = LLVMTargetRef - LLVMGetNextTarget.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMGetTargetFromName = _libraries['llvm'].LLVMGetTargetFromName - LLVMGetTargetFromName.restype = LLVMTargetRef - LLVMGetTargetFromName.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetTargetFromTriple = _libraries['llvm'].LLVMGetTargetFromTriple - LLVMGetTargetFromTriple.restype = LLVMBool - LLVMGetTargetFromTriple.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMTarget)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMGetTargetName = _libraries['llvm'].LLVMGetTargetName - LLVMGetTargetName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetName.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMGetTargetDescription = _libraries['llvm'].LLVMGetTargetDescription - LLVMGetTargetDescription.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetDescription.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMTargetHasJIT = _libraries['llvm'].LLVMTargetHasJIT - LLVMTargetHasJIT.restype = LLVMBool - LLVMTargetHasJIT.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMTargetHasTargetMachine = _libraries['llvm'].LLVMTargetHasTargetMachine - LLVMTargetHasTargetMachine.restype = LLVMBool - LLVMTargetHasTargetMachine.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMTargetHasAsmBackend = _libraries['llvm'].LLVMTargetHasAsmBackend - LLVMTargetHasAsmBackend.restype = LLVMBool - LLVMTargetHasAsmBackend.argtypes = [LLVMTargetRef] -except AttributeError: - pass -try: - LLVMCreateTargetMachine = _libraries['llvm'].LLVMCreateTargetMachine - LLVMCreateTargetMachine.restype = LLVMTargetMachineRef - LLVMCreateTargetMachine.argtypes = [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] -except AttributeError: - pass -try: - LLVMDisposeTargetMachine = _libraries['llvm'].LLVMDisposeTargetMachine - LLVMDisposeTargetMachine.restype = None - LLVMDisposeTargetMachine.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineTarget = _libraries['llvm'].LLVMGetTargetMachineTarget - LLVMGetTargetMachineTarget.restype = LLVMTargetRef - LLVMGetTargetMachineTarget.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineTriple = _libraries['llvm'].LLVMGetTargetMachineTriple - LLVMGetTargetMachineTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetMachineTriple.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineCPU = _libraries['llvm'].LLVMGetTargetMachineCPU - LLVMGetTargetMachineCPU.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetMachineCPU.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMGetTargetMachineFeatureString = _libraries['llvm'].LLVMGetTargetMachineFeatureString - LLVMGetTargetMachineFeatureString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetTargetMachineFeatureString.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMCreateTargetDataLayout = _libraries['llvm'].LLVMCreateTargetDataLayout - LLVMCreateTargetDataLayout.restype = LLVMTargetDataRef - LLVMCreateTargetDataLayout.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMSetTargetMachineAsmVerbosity = _libraries['llvm'].LLVMSetTargetMachineAsmVerbosity - LLVMSetTargetMachineAsmVerbosity.restype = None - LLVMSetTargetMachineAsmVerbosity.argtypes = [LLVMTargetMachineRef, LLVMBool] -except AttributeError: - pass -try: - LLVMTargetMachineEmitToFile = _libraries['llvm'].LLVMTargetMachineEmitToFile - LLVMTargetMachineEmitToFile.restype = LLVMBool - LLVMTargetMachineEmitToFile.argtypes = [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMTargetMachineEmitToMemoryBuffer = _libraries['llvm'].LLVMTargetMachineEmitToMemoryBuffer - LLVMTargetMachineEmitToMemoryBuffer.restype = LLVMBool - LLVMTargetMachineEmitToMemoryBuffer.argtypes = [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))] -except AttributeError: - pass -try: - LLVMGetDefaultTargetTriple = _libraries['llvm'].LLVMGetDefaultTargetTriple - LLVMGetDefaultTargetTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetDefaultTargetTriple.argtypes = [] -except AttributeError: - pass -try: - LLVMNormalizeTargetTriple = _libraries['llvm'].LLVMNormalizeTargetTriple - LLVMNormalizeTargetTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMNormalizeTargetTriple.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetHostCPUName = _libraries['llvm'].LLVMGetHostCPUName - LLVMGetHostCPUName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetHostCPUName.argtypes = [] -except AttributeError: - pass -try: - LLVMGetHostCPUFeatures = _libraries['llvm'].LLVMGetHostCPUFeatures - LLVMGetHostCPUFeatures.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetHostCPUFeatures.argtypes = [] -except AttributeError: - pass -try: - LLVMAddAnalysisPasses = _libraries['llvm'].LLVMAddAnalysisPasses - LLVMAddAnalysisPasses.restype = None - LLVMAddAnalysisPasses.argtypes = [LLVMTargetMachineRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMLinkInMCJIT = _libraries['llvm'].LLVMLinkInMCJIT - LLVMLinkInMCJIT.restype = None - LLVMLinkInMCJIT.argtypes = [] -except AttributeError: - pass -try: - LLVMLinkInInterpreter = _libraries['llvm'].LLVMLinkInInterpreter - LLVMLinkInInterpreter.restype = None - LLVMLinkInInterpreter.argtypes = [] -except AttributeError: - pass -class struct_LLVMOpaqueGenericValue(Structure): - pass +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +class struct_LLVMOpaqueTargetMachineOptions(Struct): pass +LLVMTargetMachineOptionsRef = ctypes.POINTER(struct_LLVMOpaqueTargetMachineOptions) +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +LLVMCodeGenOptLevel = CEnum(ctypes.c_uint32) +LLVMCodeGenLevelNone = LLVMCodeGenOptLevel.define('LLVMCodeGenLevelNone', 0) +LLVMCodeGenLevelLess = LLVMCodeGenOptLevel.define('LLVMCodeGenLevelLess', 1) +LLVMCodeGenLevelDefault = LLVMCodeGenOptLevel.define('LLVMCodeGenLevelDefault', 2) +LLVMCodeGenLevelAggressive = LLVMCodeGenOptLevel.define('LLVMCodeGenLevelAggressive', 3) + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +LLVMRelocMode = CEnum(ctypes.c_uint32) +LLVMRelocDefault = LLVMRelocMode.define('LLVMRelocDefault', 0) +LLVMRelocStatic = LLVMRelocMode.define('LLVMRelocStatic', 1) +LLVMRelocPIC = LLVMRelocMode.define('LLVMRelocPIC', 2) +LLVMRelocDynamicNoPic = LLVMRelocMode.define('LLVMRelocDynamicNoPic', 3) +LLVMRelocROPI = LLVMRelocMode.define('LLVMRelocROPI', 4) +LLVMRelocRWPI = LLVMRelocMode.define('LLVMRelocRWPI', 5) +LLVMRelocROPI_RWPI = LLVMRelocMode.define('LLVMRelocROPI_RWPI', 6) + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +LLVMCodeModel = CEnum(ctypes.c_uint32) +LLVMCodeModelDefault = LLVMCodeModel.define('LLVMCodeModelDefault', 0) +LLVMCodeModelJITDefault = LLVMCodeModel.define('LLVMCodeModelJITDefault', 1) +LLVMCodeModelTiny = LLVMCodeModel.define('LLVMCodeModelTiny', 2) +LLVMCodeModelSmall = LLVMCodeModel.define('LLVMCodeModelSmall', 3) +LLVMCodeModelKernel = LLVMCodeModel.define('LLVMCodeModelKernel', 4) +LLVMCodeModelMedium = LLVMCodeModel.define('LLVMCodeModelMedium', 5) +LLVMCodeModelLarge = LLVMCodeModel.define('LLVMCodeModelLarge', 6) + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +class struct_LLVMOpaqueTargetMachine(Struct): pass +LLVMTargetMachineRef = ctypes.POINTER(struct_LLVMOpaqueTargetMachine) +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +LLVMGlobalISelAbortMode = CEnum(ctypes.c_uint32) +LLVMGlobalISelAbortEnable = LLVMGlobalISelAbortMode.define('LLVMGlobalISelAbortEnable', 0) +LLVMGlobalISelAbortDisable = LLVMGlobalISelAbortMode.define('LLVMGlobalISelAbortDisable', 1) +LLVMGlobalISelAbortDisableWithDiag = LLVMGlobalISelAbortMode.define('LLVMGlobalISelAbortDisableWithDiag', 2) + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +LLVMCodeGenFileType = CEnum(ctypes.c_uint32) +LLVMAssemblyFile = LLVMCodeGenFileType.define('LLVMAssemblyFile', 0) +LLVMObjectFile = LLVMCodeGenFileType.define('LLVMObjectFile', 1) + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +# void LLVMLinkInMCJIT(void) +try: (LLVMLinkInMCJIT:=dll.LLVMLinkInMCJIT).restype, LLVMLinkInMCJIT.argtypes = None, [] +except AttributeError: pass + +# void LLVMLinkInInterpreter(void) +try: (LLVMLinkInInterpreter:=dll.LLVMLinkInInterpreter).restype, LLVMLinkInInterpreter.argtypes = None, [] +except AttributeError: pass + +class struct_LLVMOpaqueGenericValue(Struct): pass LLVMGenericValueRef = ctypes.POINTER(struct_LLVMOpaqueGenericValue) -class struct_LLVMOpaqueExecutionEngine(Structure): - pass - +class struct_LLVMOpaqueExecutionEngine(Struct): pass LLVMExecutionEngineRef = ctypes.POINTER(struct_LLVMOpaqueExecutionEngine) -class struct_LLVMOpaqueMCJITMemoryManager(Structure): - pass - +class struct_LLVMOpaqueMCJITMemoryManager(Struct): pass LLVMMCJITMemoryManagerRef = ctypes.POINTER(struct_LLVMOpaqueMCJITMemoryManager) -class struct_LLVMMCJITCompilerOptions(Structure): - pass - -struct_LLVMMCJITCompilerOptions._pack_ = 1 # source:False +class struct_LLVMMCJITCompilerOptions(Struct): pass struct_LLVMMCJITCompilerOptions._fields_ = [ - ('OptLevel', ctypes.c_uint32), - ('CodeModel', LLVMCodeModel), - ('NoFramePointerElim', ctypes.c_int32), - ('EnableFastISel', ctypes.c_int32), - ('MCJMM', ctypes.POINTER(struct_LLVMOpaqueMCJITMemoryManager)), + ('OptLevel', ctypes.c_uint32), + ('CodeModel', LLVMCodeModel), + ('NoFramePointerElim', LLVMBool), + ('EnableFastISel', LLVMBool), + ('MCJMM', LLVMMCJITMemoryManagerRef), ] +# LLVMGenericValueRef LLVMCreateGenericValueOfInt(LLVMTypeRef Ty, unsigned long long N, LLVMBool IsSigned) +try: (LLVMCreateGenericValueOfInt:=dll.LLVMCreateGenericValueOfInt).restype, LLVMCreateGenericValueOfInt.argtypes = LLVMGenericValueRef, [LLVMTypeRef, ctypes.c_uint64, LLVMBool] +except AttributeError: pass -try: - LLVMCreateGenericValueOfInt = _libraries['llvm'].LLVMCreateGenericValueOfInt - LLVMCreateGenericValueOfInt.restype = LLVMGenericValueRef - LLVMCreateGenericValueOfInt.argtypes = [LLVMTypeRef, ctypes.c_uint64, LLVMBool] -except AttributeError: - pass -try: - LLVMCreateGenericValueOfPointer = _libraries['llvm'].LLVMCreateGenericValueOfPointer - LLVMCreateGenericValueOfPointer.restype = LLVMGenericValueRef - LLVMCreateGenericValueOfPointer.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMCreateGenericValueOfFloat = _libraries['llvm'].LLVMCreateGenericValueOfFloat - LLVMCreateGenericValueOfFloat.restype = LLVMGenericValueRef - LLVMCreateGenericValueOfFloat.argtypes = [LLVMTypeRef, ctypes.c_double] -except AttributeError: - pass -try: - LLVMGenericValueIntWidth = _libraries['llvm'].LLVMGenericValueIntWidth - LLVMGenericValueIntWidth.restype = ctypes.c_uint32 - LLVMGenericValueIntWidth.argtypes = [LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMGenericValueToInt = _libraries['llvm'].LLVMGenericValueToInt - LLVMGenericValueToInt.restype = ctypes.c_uint64 - LLVMGenericValueToInt.argtypes = [LLVMGenericValueRef, LLVMBool] -except AttributeError: - pass -try: - LLVMGenericValueToPointer = _libraries['llvm'].LLVMGenericValueToPointer - LLVMGenericValueToPointer.restype = ctypes.POINTER(None) - LLVMGenericValueToPointer.argtypes = [LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMGenericValueToFloat = _libraries['llvm'].LLVMGenericValueToFloat - LLVMGenericValueToFloat.restype = ctypes.c_double - LLVMGenericValueToFloat.argtypes = [LLVMTypeRef, LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMDisposeGenericValue = _libraries['llvm'].LLVMDisposeGenericValue - LLVMDisposeGenericValue.restype = None - LLVMDisposeGenericValue.argtypes = [LLVMGenericValueRef] -except AttributeError: - pass -try: - LLVMCreateExecutionEngineForModule = _libraries['llvm'].LLVMCreateExecutionEngineForModule - LLVMCreateExecutionEngineForModule.restype = LLVMBool - LLVMCreateExecutionEngineForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateInterpreterForModule = _libraries['llvm'].LLVMCreateInterpreterForModule - LLVMCreateInterpreterForModule.restype = LLVMBool - LLVMCreateInterpreterForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMCreateJITCompilerForModule = _libraries['llvm'].LLVMCreateJITCompilerForModule - LLVMCreateJITCompilerForModule.restype = LLVMBool - LLVMCreateJITCompilerForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMInitializeMCJITCompilerOptions = _libraries['llvm'].LLVMInitializeMCJITCompilerOptions - LLVMInitializeMCJITCompilerOptions.restype = None - LLVMInitializeMCJITCompilerOptions.argtypes = [ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t] -except AttributeError: - pass -try: - LLVMCreateMCJITCompilerForModule = _libraries['llvm'].LLVMCreateMCJITCompilerForModule - LLVMCreateMCJITCompilerForModule.restype = LLVMBool - LLVMCreateMCJITCompilerForModule.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), LLVMModuleRef, ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMDisposeExecutionEngine = _libraries['llvm'].LLVMDisposeExecutionEngine - LLVMDisposeExecutionEngine.restype = None - LLVMDisposeExecutionEngine.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMRunStaticConstructors = _libraries['llvm'].LLVMRunStaticConstructors - LLVMRunStaticConstructors.restype = None - LLVMRunStaticConstructors.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMRunStaticDestructors = _libraries['llvm'].LLVMRunStaticDestructors - LLVMRunStaticDestructors.restype = None - LLVMRunStaticDestructors.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMRunFunctionAsMain = _libraries['llvm'].LLVMRunFunctionAsMain - LLVMRunFunctionAsMain.restype = ctypes.c_int32 - LLVMRunFunctionAsMain.argtypes = [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMRunFunction = _libraries['llvm'].LLVMRunFunction - LLVMRunFunction.restype = LLVMGenericValueRef - LLVMRunFunction.argtypes = [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueGenericValue))] -except AttributeError: - pass -try: - LLVMFreeMachineCodeForFunction = _libraries['llvm'].LLVMFreeMachineCodeForFunction - LLVMFreeMachineCodeForFunction.restype = None - LLVMFreeMachineCodeForFunction.argtypes = [LLVMExecutionEngineRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMAddModule = _libraries['llvm'].LLVMAddModule - LLVMAddModule.restype = None - LLVMAddModule.argtypes = [LLVMExecutionEngineRef, LLVMModuleRef] -except AttributeError: - pass -try: - LLVMRemoveModule = _libraries['llvm'].LLVMRemoveModule - LLVMRemoveModule.restype = LLVMBool - LLVMRemoveModule.argtypes = [LLVMExecutionEngineRef, LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMFindFunction = _libraries['llvm'].LLVMFindFunction - LLVMFindFunction.restype = LLVMBool - LLVMFindFunction.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))] -except AttributeError: - pass -try: - LLVMRecompileAndRelinkFunction = _libraries['llvm'].LLVMRecompileAndRelinkFunction - LLVMRecompileAndRelinkFunction.restype = ctypes.POINTER(None) - LLVMRecompileAndRelinkFunction.argtypes = [LLVMExecutionEngineRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetExecutionEngineTargetData = _libraries['llvm'].LLVMGetExecutionEngineTargetData - LLVMGetExecutionEngineTargetData.restype = LLVMTargetDataRef - LLVMGetExecutionEngineTargetData.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMGetExecutionEngineTargetMachine = _libraries['llvm'].LLVMGetExecutionEngineTargetMachine - LLVMGetExecutionEngineTargetMachine.restype = LLVMTargetMachineRef - LLVMGetExecutionEngineTargetMachine.argtypes = [LLVMExecutionEngineRef] -except AttributeError: - pass -try: - LLVMAddGlobalMapping = _libraries['llvm'].LLVMAddGlobalMapping - LLVMAddGlobalMapping.restype = None - LLVMAddGlobalMapping.argtypes = [LLVMExecutionEngineRef, LLVMValueRef, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMGetPointerToGlobal = _libraries['llvm'].LLVMGetPointerToGlobal - LLVMGetPointerToGlobal.restype = ctypes.POINTER(None) - LLVMGetPointerToGlobal.argtypes = [LLVMExecutionEngineRef, LLVMValueRef] -except AttributeError: - pass -try: - LLVMGetGlobalValueAddress = _libraries['llvm'].LLVMGetGlobalValueAddress - LLVMGetGlobalValueAddress.restype = uint64_t - LLVMGetGlobalValueAddress.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMGetFunctionAddress = _libraries['llvm'].LLVMGetFunctionAddress - LLVMGetFunctionAddress.restype = uint64_t - LLVMGetFunctionAddress.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMExecutionEngineGetErrMsg = _libraries['llvm'].LLVMExecutionEngineGetErrMsg - LLVMExecutionEngineGetErrMsg.restype = LLVMBool - LLVMExecutionEngineGetErrMsg.argtypes = [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -LLVMMemoryManagerAllocateCodeSectionCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_ubyte), ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)) -LLVMMemoryManagerAllocateDataSectionCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_ubyte), ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32) -LLVMMemoryManagerFinalizeMemoryCallback = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))) -LLVMMemoryManagerDestroyCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -try: - LLVMCreateSimpleMCJITMemoryManager = _libraries['llvm'].LLVMCreateSimpleMCJITMemoryManager - LLVMCreateSimpleMCJITMemoryManager.restype = LLVMMCJITMemoryManagerRef - LLVMCreateSimpleMCJITMemoryManager.argtypes = [ctypes.POINTER(None), LLVMMemoryManagerAllocateCodeSectionCallback, LLVMMemoryManagerAllocateDataSectionCallback, LLVMMemoryManagerFinalizeMemoryCallback, LLVMMemoryManagerDestroyCallback] -except AttributeError: - pass -try: - LLVMDisposeMCJITMemoryManager = _libraries['llvm'].LLVMDisposeMCJITMemoryManager - LLVMDisposeMCJITMemoryManager.restype = None - LLVMDisposeMCJITMemoryManager.argtypes = [LLVMMCJITMemoryManagerRef] -except AttributeError: - pass -try: - LLVMCreateGDBRegistrationListener = _libraries['llvm'].LLVMCreateGDBRegistrationListener - LLVMCreateGDBRegistrationListener.restype = LLVMJITEventListenerRef - LLVMCreateGDBRegistrationListener.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateIntelJITEventListener = _libraries['llvm'].LLVMCreateIntelJITEventListener - LLVMCreateIntelJITEventListener.restype = LLVMJITEventListenerRef - LLVMCreateIntelJITEventListener.argtypes = [] -except AttributeError: - pass -try: - LLVMCreateOProfileJITEventListener = _libraries['llvm'].LLVMCreateOProfileJITEventListener - LLVMCreateOProfileJITEventListener.restype = LLVMJITEventListenerRef - LLVMCreateOProfileJITEventListener.argtypes = [] -except AttributeError: - pass -try: - LLVMCreatePerfJITEventListener = _libraries['llvm'].LLVMCreatePerfJITEventListener - LLVMCreatePerfJITEventListener.restype = LLVMJITEventListenerRef - LLVMCreatePerfJITEventListener.argtypes = [] -except AttributeError: - pass -LLVM_C_IRREADER_H = True # macro -try: - LLVMParseIRInContext = _libraries['llvm'].LLVMParseIRInContext - LLVMParseIRInContext.restype = LLVMBool - LLVMParseIRInContext.argtypes = [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueModule)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -LLVM_C_INITIALIZATION_H = True # macro -try: - LLVMInitializeTransformUtils = _libraries['llvm'].LLVMInitializeTransformUtils - LLVMInitializeTransformUtils.restype = None - LLVMInitializeTransformUtils.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeScalarOpts = _libraries['llvm'].LLVMInitializeScalarOpts - LLVMInitializeScalarOpts.restype = None - LLVMInitializeScalarOpts.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeObjCARCOpts = _libraries['llvm'].LLVMInitializeObjCARCOpts - LLVMInitializeObjCARCOpts.restype = None - LLVMInitializeObjCARCOpts.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeVectorization = _libraries['llvm'].LLVMInitializeVectorization - LLVMInitializeVectorization.restype = None - LLVMInitializeVectorization.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeInstCombine = _libraries['llvm'].LLVMInitializeInstCombine - LLVMInitializeInstCombine.restype = None - LLVMInitializeInstCombine.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeAggressiveInstCombiner = _libraries['llvm'].LLVMInitializeAggressiveInstCombiner - LLVMInitializeAggressiveInstCombiner.restype = None - LLVMInitializeAggressiveInstCombiner.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeIPO = _libraries['llvm'].LLVMInitializeIPO - LLVMInitializeIPO.restype = None - LLVMInitializeIPO.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeInstrumentation = _libraries['llvm'].LLVMInitializeInstrumentation - LLVMInitializeInstrumentation.restype = None - LLVMInitializeInstrumentation.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeAnalysis = _libraries['llvm'].LLVMInitializeAnalysis - LLVMInitializeAnalysis.restype = None - LLVMInitializeAnalysis.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeIPA = _libraries['llvm'].LLVMInitializeIPA - LLVMInitializeIPA.restype = None - LLVMInitializeIPA.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeCodeGen = _libraries['llvm'].LLVMInitializeCodeGen - LLVMInitializeCodeGen.restype = None - LLVMInitializeCodeGen.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -try: - LLVMInitializeTarget = _libraries['llvm'].LLVMInitializeTarget - LLVMInitializeTarget.restype = None - LLVMInitializeTarget.argtypes = [LLVMPassRegistryRef] -except AttributeError: - pass -LLVM_C_LLJIT_H = True # macro -LLVM_C_ORC_H = True # macro -LLVMOrcJITTargetAddress = ctypes.c_uint64 -LLVMOrcExecutorAddress = ctypes.c_uint64 +# LLVMGenericValueRef LLVMCreateGenericValueOfPointer(void *P) +try: (LLVMCreateGenericValueOfPointer:=dll.LLVMCreateGenericValueOfPointer).restype, LLVMCreateGenericValueOfPointer.argtypes = LLVMGenericValueRef, [ctypes.c_void_p] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMJITSymbolGenericFlags' -c__EA_LLVMJITSymbolGenericFlags__enumvalues = { - 1: 'LLVMJITSymbolGenericFlagsExported', - 2: 'LLVMJITSymbolGenericFlagsWeak', - 4: 'LLVMJITSymbolGenericFlagsCallable', - 8: 'LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly', -} -LLVMJITSymbolGenericFlagsExported = 1 -LLVMJITSymbolGenericFlagsWeak = 2 -LLVMJITSymbolGenericFlagsCallable = 4 -LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly = 8 -c__EA_LLVMJITSymbolGenericFlags = ctypes.c_uint32 # enum -LLVMJITSymbolGenericFlags = c__EA_LLVMJITSymbolGenericFlags -LLVMJITSymbolGenericFlags__enumvalues = c__EA_LLVMJITSymbolGenericFlags__enumvalues -LLVMJITSymbolTargetFlags = ctypes.c_ubyte -class struct_c__SA_LLVMJITSymbolFlags(Structure): - pass +# LLVMGenericValueRef LLVMCreateGenericValueOfFloat(LLVMTypeRef Ty, double N) +try: (LLVMCreateGenericValueOfFloat:=dll.LLVMCreateGenericValueOfFloat).restype, LLVMCreateGenericValueOfFloat.argtypes = LLVMGenericValueRef, [LLVMTypeRef, ctypes.c_double] +except AttributeError: pass -struct_c__SA_LLVMJITSymbolFlags._pack_ = 1 # source:False -struct_c__SA_LLVMJITSymbolFlags._fields_ = [ - ('GenericFlags', ctypes.c_ubyte), - ('TargetFlags', ctypes.c_ubyte), -] +# unsigned int LLVMGenericValueIntWidth(LLVMGenericValueRef GenValRef) +try: (LLVMGenericValueIntWidth:=dll.LLVMGenericValueIntWidth).restype, LLVMGenericValueIntWidth.argtypes = ctypes.c_uint32, [LLVMGenericValueRef] +except AttributeError: pass -LLVMJITSymbolFlags = struct_c__SA_LLVMJITSymbolFlags -class struct_c__SA_LLVMJITEvaluatedSymbol(Structure): - pass +# unsigned long long LLVMGenericValueToInt(LLVMGenericValueRef GenVal, LLVMBool IsSigned) +try: (LLVMGenericValueToInt:=dll.LLVMGenericValueToInt).restype, LLVMGenericValueToInt.argtypes = ctypes.c_uint64, [LLVMGenericValueRef, LLVMBool] +except AttributeError: pass -struct_c__SA_LLVMJITEvaluatedSymbol._pack_ = 1 # source:False -struct_c__SA_LLVMJITEvaluatedSymbol._fields_ = [ - ('Address', ctypes.c_uint64), - ('Flags', LLVMJITSymbolFlags), - ('PADDING_0', ctypes.c_ubyte * 6), -] +# void *LLVMGenericValueToPointer(LLVMGenericValueRef GenVal) +try: (LLVMGenericValueToPointer:=dll.LLVMGenericValueToPointer).restype, LLVMGenericValueToPointer.argtypes = ctypes.c_void_p, [LLVMGenericValueRef] +except AttributeError: pass -LLVMJITEvaluatedSymbol = struct_c__SA_LLVMJITEvaluatedSymbol -class struct_LLVMOrcOpaqueExecutionSession(Structure): - pass +# double LLVMGenericValueToFloat(LLVMTypeRef TyRef, LLVMGenericValueRef GenVal) +try: (LLVMGenericValueToFloat:=dll.LLVMGenericValueToFloat).restype, LLVMGenericValueToFloat.argtypes = ctypes.c_double, [LLVMTypeRef, LLVMGenericValueRef] +except AttributeError: pass +# void LLVMDisposeGenericValue(LLVMGenericValueRef GenVal) +try: (LLVMDisposeGenericValue:=dll.LLVMDisposeGenericValue).restype, LLVMDisposeGenericValue.argtypes = None, [LLVMGenericValueRef] +except AttributeError: pass + +# LLVMBool LLVMCreateExecutionEngineForModule(LLVMExecutionEngineRef *OutEE, LLVMModuleRef M, char **OutError) +try: (LLVMCreateExecutionEngineForModule:=dll.LLVMCreateExecutionEngineForModule).restype, LLVMCreateExecutionEngineForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMCreateInterpreterForModule(LLVMExecutionEngineRef *OutInterp, LLVMModuleRef M, char **OutError) +try: (LLVMCreateInterpreterForModule:=dll.LLVMCreateInterpreterForModule).restype, LLVMCreateInterpreterForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMCreateJITCompilerForModule(LLVMExecutionEngineRef *OutJIT, LLVMModuleRef M, unsigned int OptLevel, char **OutError) +try: (LLVMCreateJITCompilerForModule:=dll.LLVMCreateJITCompilerForModule).restype, LLVMCreateJITCompilerForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# void LLVMInitializeMCJITCompilerOptions(struct LLVMMCJITCompilerOptions *Options, size_t SizeOfOptions) +try: (LLVMInitializeMCJITCompilerOptions:=dll.LLVMInitializeMCJITCompilerOptions).restype, LLVMInitializeMCJITCompilerOptions.argtypes = None, [ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t] +except AttributeError: pass + +# LLVMBool LLVMCreateMCJITCompilerForModule(LLVMExecutionEngineRef *OutJIT, LLVMModuleRef M, struct LLVMMCJITCompilerOptions *Options, size_t SizeOfOptions, char **OutError) +try: (LLVMCreateMCJITCompilerForModule:=dll.LLVMCreateMCJITCompilerForModule).restype, LLVMCreateMCJITCompilerForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# void LLVMDisposeExecutionEngine(LLVMExecutionEngineRef EE) +try: (LLVMDisposeExecutionEngine:=dll.LLVMDisposeExecutionEngine).restype, LLVMDisposeExecutionEngine.argtypes = None, [LLVMExecutionEngineRef] +except AttributeError: pass + +# void LLVMRunStaticConstructors(LLVMExecutionEngineRef EE) +try: (LLVMRunStaticConstructors:=dll.LLVMRunStaticConstructors).restype, LLVMRunStaticConstructors.argtypes = None, [LLVMExecutionEngineRef] +except AttributeError: pass + +# void LLVMRunStaticDestructors(LLVMExecutionEngineRef EE) +try: (LLVMRunStaticDestructors:=dll.LLVMRunStaticDestructors).restype, LLVMRunStaticDestructors.argtypes = None, [LLVMExecutionEngineRef] +except AttributeError: pass + +# int LLVMRunFunctionAsMain(LLVMExecutionEngineRef EE, LLVMValueRef F, unsigned int ArgC, const char *const *ArgV, const char *const *EnvP) +try: (LLVMRunFunctionAsMain:=dll.LLVMRunFunctionAsMain).restype, LLVMRunFunctionAsMain.argtypes = ctypes.c_int32, [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMGenericValueRef LLVMRunFunction(LLVMExecutionEngineRef EE, LLVMValueRef F, unsigned int NumArgs, LLVMGenericValueRef *Args) +try: (LLVMRunFunction:=dll.LLVMRunFunction).restype, LLVMRunFunction.argtypes = LLVMGenericValueRef, [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(LLVMGenericValueRef)] +except AttributeError: pass + +# void LLVMFreeMachineCodeForFunction(LLVMExecutionEngineRef EE, LLVMValueRef F) +try: (LLVMFreeMachineCodeForFunction:=dll.LLVMFreeMachineCodeForFunction).restype, LLVMFreeMachineCodeForFunction.argtypes = None, [LLVMExecutionEngineRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMAddModule(LLVMExecutionEngineRef EE, LLVMModuleRef M) +try: (LLVMAddModule:=dll.LLVMAddModule).restype, LLVMAddModule.argtypes = None, [LLVMExecutionEngineRef, LLVMModuleRef] +except AttributeError: pass + +# LLVMBool LLVMRemoveModule(LLVMExecutionEngineRef EE, LLVMModuleRef M, LLVMModuleRef *OutMod, char **OutError) +try: (LLVMRemoveModule:=dll.LLVMRemoveModule).restype, LLVMRemoveModule.argtypes = LLVMBool, [LLVMExecutionEngineRef, LLVMModuleRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMFindFunction(LLVMExecutionEngineRef EE, const char *Name, LLVMValueRef *OutFn) +try: (LLVMFindFunction:=dll.LLVMFindFunction).restype, LLVMFindFunction.argtypes = LLVMBool, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMValueRef)] +except AttributeError: pass + +# void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE, LLVMValueRef Fn) +try: (LLVMRecompileAndRelinkFunction:=dll.LLVMRecompileAndRelinkFunction).restype, LLVMRecompileAndRelinkFunction.argtypes = ctypes.c_void_p, [LLVMExecutionEngineRef, LLVMValueRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef EE) +try: (LLVMGetExecutionEngineTargetData:=dll.LLVMGetExecutionEngineTargetData).restype, LLVMGetExecutionEngineTargetData.argtypes = LLVMTargetDataRef, [LLVMExecutionEngineRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMGetExecutionEngineTargetMachine(LLVMExecutionEngineRef EE) +try: (LLVMGetExecutionEngineTargetMachine:=dll.LLVMGetExecutionEngineTargetMachine).restype, LLVMGetExecutionEngineTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMExecutionEngineRef] +except AttributeError: pass + +# void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global, void *Addr) +try: (LLVMAddGlobalMapping:=dll.LLVMAddGlobalMapping).restype, LLVMAddGlobalMapping.argtypes = None, [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_void_p] +except AttributeError: pass + +# void *LLVMGetPointerToGlobal(LLVMExecutionEngineRef EE, LLVMValueRef Global) +try: (LLVMGetPointerToGlobal:=dll.LLVMGetPointerToGlobal).restype, LLVMGetPointerToGlobal.argtypes = ctypes.c_void_p, [LLVMExecutionEngineRef, LLVMValueRef] +except AttributeError: pass + +# uint64_t LLVMGetGlobalValueAddress(LLVMExecutionEngineRef EE, const char *Name) +try: (LLVMGetGlobalValueAddress:=dll.LLVMGetGlobalValueAddress).restype, LLVMGetGlobalValueAddress.argtypes = uint64_t, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# uint64_t LLVMGetFunctionAddress(LLVMExecutionEngineRef EE, const char *Name) +try: (LLVMGetFunctionAddress:=dll.LLVMGetFunctionAddress).restype, LLVMGetFunctionAddress.argtypes = uint64_t, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMExecutionEngineGetErrMsg(LLVMExecutionEngineRef EE, char **OutError) +try: (LLVMExecutionEngineGetErrMsg:=dll.LLVMExecutionEngineGetErrMsg).restype, LLVMExecutionEngineGetErrMsg.argtypes = LLVMBool, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +LLVMMemoryManagerAllocateCodeSectionCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_ubyte), ctypes.c_void_p, ctypes.c_uint64, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)) +LLVMMemoryManagerAllocateDataSectionCallback = ctypes.CFUNCTYPE(ctypes.POINTER(ctypes.c_ubyte), ctypes.c_void_p, ctypes.c_uint64, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_int32) +LLVMMemoryManagerFinalizeMemoryCallback = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_void_p, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))) +LLVMMemoryManagerDestroyCallback = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +# LLVMMCJITMemoryManagerRef LLVMCreateSimpleMCJITMemoryManager(void *Opaque, LLVMMemoryManagerAllocateCodeSectionCallback AllocateCodeSection, LLVMMemoryManagerAllocateDataSectionCallback AllocateDataSection, LLVMMemoryManagerFinalizeMemoryCallback FinalizeMemory, LLVMMemoryManagerDestroyCallback Destroy) +try: (LLVMCreateSimpleMCJITMemoryManager:=dll.LLVMCreateSimpleMCJITMemoryManager).restype, LLVMCreateSimpleMCJITMemoryManager.argtypes = LLVMMCJITMemoryManagerRef, [ctypes.c_void_p, LLVMMemoryManagerAllocateCodeSectionCallback, LLVMMemoryManagerAllocateDataSectionCallback, LLVMMemoryManagerFinalizeMemoryCallback, LLVMMemoryManagerDestroyCallback] +except AttributeError: pass + +# void LLVMDisposeMCJITMemoryManager(LLVMMCJITMemoryManagerRef MM) +try: (LLVMDisposeMCJITMemoryManager:=dll.LLVMDisposeMCJITMemoryManager).restype, LLVMDisposeMCJITMemoryManager.argtypes = None, [LLVMMCJITMemoryManagerRef] +except AttributeError: pass + +class struct_LLVMOpaqueJITEventListener(Struct): pass +LLVMJITEventListenerRef = ctypes.POINTER(struct_LLVMOpaqueJITEventListener) +# LLVMJITEventListenerRef LLVMCreateGDBRegistrationListener(void) +try: (LLVMCreateGDBRegistrationListener:=dll.LLVMCreateGDBRegistrationListener).restype, LLVMCreateGDBRegistrationListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreateIntelJITEventListener(void) +try: (LLVMCreateIntelJITEventListener:=dll.LLVMCreateIntelJITEventListener).restype, LLVMCreateIntelJITEventListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreateOProfileJITEventListener(void) +try: (LLVMCreateOProfileJITEventListener:=dll.LLVMCreateOProfileJITEventListener).restype, LLVMCreateOProfileJITEventListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreatePerfJITEventListener(void) +try: (LLVMCreatePerfJITEventListener:=dll.LLVMCreatePerfJITEventListener).restype, LLVMCreatePerfJITEventListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# LLVMBool LLVMParseIRInContext(LLVMContextRef ContextRef, LLVMMemoryBufferRef MemBuf, LLVMModuleRef *OutM, char **OutMessage) +try: (LLVMParseIRInContext:=dll.LLVMParseIRInContext).restype, LLVMParseIRInContext.argtypes = LLVMBool, [LLVMContextRef, LLVMMemoryBufferRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetErrorTypeId(LLVMErrorRef Err) +try: (LLVMGetErrorTypeId:=dll.LLVMGetErrorTypeId).restype, LLVMGetErrorTypeId.argtypes = LLVMErrorTypeId, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMConsumeError(LLVMErrorRef Err) +try: (LLVMConsumeError:=dll.LLVMConsumeError).restype, LLVMConsumeError.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMCantFail(LLVMErrorRef Err) +try: (LLVMCantFail:=dll.LLVMCantFail).restype, LLVMCantFail.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# char *LLVMGetErrorMessage(LLVMErrorRef Err) +try: (LLVMGetErrorMessage:=dll.LLVMGetErrorMessage).restype, LLVMGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMErrorRef] +except AttributeError: pass + +# void LLVMDisposeErrorMessage(char *ErrMsg) +try: (LLVMDisposeErrorMessage:=dll.LLVMDisposeErrorMessage).restype, LLVMDisposeErrorMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetStringErrorTypeId(void) +try: (LLVMGetStringErrorTypeId:=dll.LLVMGetStringErrorTypeId).restype, LLVMGetStringErrorTypeId.argtypes = LLVMErrorTypeId, [] +except AttributeError: pass + +# LLVMErrorRef LLVMCreateStringError(const char *ErrMsg) +try: (LLVMCreateStringError:=dll.LLVMCreateStringError).restype, LLVMCreateStringError.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass + +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueExecutionSession(Struct): pass LLVMOrcExecutionSessionRef = ctypes.POINTER(struct_LLVMOrcOpaqueExecutionSession) -LLVMOrcErrorReporterFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOpaqueError)) -class struct_LLVMOrcOpaqueSymbolStringPool(Structure): - pass +LLVMOrcErrorReporterFunction = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.POINTER(struct_LLVMOpaqueError)) +# void LLVMOrcExecutionSessionSetErrorReporter(LLVMOrcExecutionSessionRef ES, LLVMOrcErrorReporterFunction ReportError, void *Ctx) +try: (LLVMOrcExecutionSessionSetErrorReporter:=dll.LLVMOrcExecutionSessionSetErrorReporter).restype, LLVMOrcExecutionSessionSetErrorReporter.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcErrorReporterFunction, ctypes.c_void_p] +except AttributeError: pass +class struct_LLVMOrcOpaqueSymbolStringPool(Struct): pass LLVMOrcSymbolStringPoolRef = ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPool) -class struct_LLVMOrcOpaqueSymbolStringPoolEntry(Structure): - pass +# LLVMOrcSymbolStringPoolRef LLVMOrcExecutionSessionGetSymbolStringPool(LLVMOrcExecutionSessionRef ES) +try: (LLVMOrcExecutionSessionGetSymbolStringPool:=dll.LLVMOrcExecutionSessionGetSymbolStringPool).restype, LLVMOrcExecutionSessionGetSymbolStringPool.argtypes = LLVMOrcSymbolStringPoolRef, [LLVMOrcExecutionSessionRef] +except AttributeError: pass +# void LLVMOrcSymbolStringPoolClearDeadEntries(LLVMOrcSymbolStringPoolRef SSP) +try: (LLVMOrcSymbolStringPoolClearDeadEntries:=dll.LLVMOrcSymbolStringPoolClearDeadEntries).restype, LLVMOrcSymbolStringPoolClearDeadEntries.argtypes = None, [LLVMOrcSymbolStringPoolRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueSymbolStringPoolEntry(Struct): pass LLVMOrcSymbolStringPoolEntryRef = ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry) -class struct_c__SA_LLVMOrcCSymbolFlagsMapPair(Structure): - pass +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcExecutionSessionIntern(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionIntern:=dll.LLVMOrcExecutionSessionIntern).restype, LLVMOrcExecutionSessionIntern.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -struct_c__SA_LLVMOrcCSymbolFlagsMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolFlagsMapPair._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Flags', LLVMJITSymbolFlags), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -LLVMOrcCSymbolFlagsMapPair = struct_c__SA_LLVMOrcCSymbolFlagsMapPair -LLVMOrcCSymbolFlagsMapPairs = ctypes.POINTER(struct_c__SA_LLVMOrcCSymbolFlagsMapPair) -class struct_c__SA_LLVMJITCSymbolMapPair(Structure): - pass - -struct_c__SA_LLVMJITCSymbolMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMJITCSymbolMapPair._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Sym', LLVMJITEvaluatedSymbol), -] - -LLVMJITCSymbolMapPair = struct_c__SA_LLVMJITCSymbolMapPair -LLVMOrcCSymbolMapPairs = ctypes.POINTER(struct_c__SA_LLVMJITCSymbolMapPair) -class struct_c__SA_LLVMOrcCSymbolAliasMapEntry(Structure): - pass - -struct_c__SA_LLVMOrcCSymbolAliasMapEntry._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolAliasMapEntry._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Flags', LLVMJITSymbolFlags), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -LLVMOrcCSymbolAliasMapEntry = struct_c__SA_LLVMOrcCSymbolAliasMapEntry -class struct_c__SA_LLVMOrcCSymbolAliasMapPair(Structure): - pass - -struct_c__SA_LLVMOrcCSymbolAliasMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolAliasMapPair._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('Entry', LLVMOrcCSymbolAliasMapEntry), -] - -LLVMOrcCSymbolAliasMapPair = struct_c__SA_LLVMOrcCSymbolAliasMapPair -LLVMOrcCSymbolAliasMapPairs = ctypes.POINTER(struct_c__SA_LLVMOrcCSymbolAliasMapPair) -class struct_LLVMOrcOpaqueJITDylib(Structure): - pass +LLVMOrcLookupKind = CEnum(ctypes.c_uint32) +LLVMOrcLookupKindStatic = LLVMOrcLookupKind.define('LLVMOrcLookupKindStatic', 0) +LLVMOrcLookupKindDLSym = LLVMOrcLookupKind.define('LLVMOrcLookupKindDLSym', 1) +class LLVMOrcCJITDylibSearchOrderElement(Struct): pass +class struct_LLVMOrcOpaqueJITDylib(Struct): pass LLVMOrcJITDylibRef = ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib) -class struct_c__SA_LLVMOrcCSymbolsList(Structure): - pass +LLVMOrcJITDylibLookupFlags = CEnum(ctypes.c_uint32) +LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly = LLVMOrcJITDylibLookupFlags.define('LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly', 0) +LLVMOrcJITDylibLookupFlagsMatchAllSymbols = LLVMOrcJITDylibLookupFlags.define('LLVMOrcJITDylibLookupFlagsMatchAllSymbols', 1) -struct_c__SA_LLVMOrcCSymbolsList._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCSymbolsList._fields_ = [ - ('Symbols', ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry))), - ('Length', ctypes.c_uint64), +LLVMOrcCJITDylibSearchOrderElement._fields_ = [ + ('JD', LLVMOrcJITDylibRef), + ('JDLookupFlags', LLVMOrcJITDylibLookupFlags), ] +LLVMOrcCJITDylibSearchOrder = ctypes.POINTER(LLVMOrcCJITDylibSearchOrderElement) +class LLVMOrcCLookupSetElement(Struct): pass +LLVMOrcSymbolLookupFlags = CEnum(ctypes.c_uint32) +LLVMOrcSymbolLookupFlagsRequiredSymbol = LLVMOrcSymbolLookupFlags.define('LLVMOrcSymbolLookupFlagsRequiredSymbol', 0) +LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol = LLVMOrcSymbolLookupFlags.define('LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol', 1) -LLVMOrcCSymbolsList = struct_c__SA_LLVMOrcCSymbolsList -class struct_c__SA_LLVMOrcCDependenceMapPair(Structure): - pass - -struct_c__SA_LLVMOrcCDependenceMapPair._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCDependenceMapPair._fields_ = [ - ('JD', ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib)), - ('Names', LLVMOrcCSymbolsList), +LLVMOrcCLookupSetElement._fields_ = [ + ('Name', LLVMOrcSymbolStringPoolEntryRef), + ('LookupFlags', LLVMOrcSymbolLookupFlags), ] - -LLVMOrcCDependenceMapPair = struct_c__SA_LLVMOrcCDependenceMapPair -LLVMOrcCDependenceMapPairs = ctypes.POINTER(struct_c__SA_LLVMOrcCDependenceMapPair) - -# values for enumeration 'c__EA_LLVMOrcLookupKind' -c__EA_LLVMOrcLookupKind__enumvalues = { - 0: 'LLVMOrcLookupKindStatic', - 1: 'LLVMOrcLookupKindDLSym', -} -LLVMOrcLookupKindStatic = 0 -LLVMOrcLookupKindDLSym = 1 -c__EA_LLVMOrcLookupKind = ctypes.c_uint32 # enum -LLVMOrcLookupKind = c__EA_LLVMOrcLookupKind -LLVMOrcLookupKind__enumvalues = c__EA_LLVMOrcLookupKind__enumvalues - -# values for enumeration 'c__EA_LLVMOrcJITDylibLookupFlags' -c__EA_LLVMOrcJITDylibLookupFlags__enumvalues = { - 0: 'LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly', - 1: 'LLVMOrcJITDylibLookupFlagsMatchAllSymbols', -} -LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly = 0 -LLVMOrcJITDylibLookupFlagsMatchAllSymbols = 1 -c__EA_LLVMOrcJITDylibLookupFlags = ctypes.c_uint32 # enum -LLVMOrcJITDylibLookupFlags = c__EA_LLVMOrcJITDylibLookupFlags -LLVMOrcJITDylibLookupFlags__enumvalues = c__EA_LLVMOrcJITDylibLookupFlags__enumvalues - -# values for enumeration 'c__EA_LLVMOrcSymbolLookupFlags' -c__EA_LLVMOrcSymbolLookupFlags__enumvalues = { - 0: 'LLVMOrcSymbolLookupFlagsRequiredSymbol', - 1: 'LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol', -} -LLVMOrcSymbolLookupFlagsRequiredSymbol = 0 -LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol = 1 -c__EA_LLVMOrcSymbolLookupFlags = ctypes.c_uint32 # enum -LLVMOrcSymbolLookupFlags = c__EA_LLVMOrcSymbolLookupFlags -LLVMOrcSymbolLookupFlags__enumvalues = c__EA_LLVMOrcSymbolLookupFlags__enumvalues -class struct_c__SA_LLVMOrcCLookupSetElement(Structure): - pass - -struct_c__SA_LLVMOrcCLookupSetElement._pack_ = 1 # source:False -struct_c__SA_LLVMOrcCLookupSetElement._fields_ = [ - ('Name', ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), - ('LookupFlags', LLVMOrcSymbolLookupFlags), - ('PADDING_0', ctypes.c_ubyte * 4), +LLVMOrcCLookupSet = ctypes.POINTER(LLVMOrcCLookupSetElement) +class LLVMOrcCSymbolMapPair(Struct): pass +class LLVMJITEvaluatedSymbol(Struct): pass +LLVMOrcExecutorAddress = ctypes.c_uint64 +class LLVMJITSymbolFlags(Struct): pass +LLVMJITSymbolFlags._fields_ = [ + ('GenericFlags', uint8_t), + ('TargetFlags', uint8_t), ] +LLVMJITEvaluatedSymbol._fields_ = [ + ('Address', LLVMOrcExecutorAddress), + ('Flags', LLVMJITSymbolFlags), +] +LLVMOrcCSymbolMapPair._fields_ = [ + ('Name', LLVMOrcSymbolStringPoolEntryRef), + ('Sym', LLVMJITEvaluatedSymbol), +] +LLVMOrcExecutionSessionLookupHandleResultFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(LLVMOrcCSymbolMapPair), ctypes.c_uint64, ctypes.c_void_p) +# void LLVMOrcExecutionSessionLookup(LLVMOrcExecutionSessionRef ES, LLVMOrcLookupKind K, LLVMOrcCJITDylibSearchOrder SearchOrder, size_t SearchOrderSize, LLVMOrcCLookupSet Symbols, size_t SymbolsSize, LLVMOrcExecutionSessionLookupHandleResultFunction HandleResult, void *Ctx) +try: (LLVMOrcExecutionSessionLookup:=dll.LLVMOrcExecutionSessionLookup).restype, LLVMOrcExecutionSessionLookup.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcLookupKind, LLVMOrcCJITDylibSearchOrder, size_t, LLVMOrcCLookupSet, size_t, LLVMOrcExecutionSessionLookupHandleResultFunction, ctypes.c_void_p] +except AttributeError: pass -LLVMOrcCLookupSetElement = struct_c__SA_LLVMOrcCLookupSetElement -LLVMOrcCLookupSet = ctypes.POINTER(struct_c__SA_LLVMOrcCLookupSetElement) -class struct_LLVMOrcOpaqueMaterializationUnit(Structure): - pass +# void LLVMOrcRetainSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcRetainSymbolStringPoolEntry:=dll.LLVMOrcRetainSymbolStringPoolEntry).restype, LLVMOrcRetainSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass +# void LLVMOrcReleaseSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcReleaseSymbolStringPoolEntry:=dll.LLVMOrcReleaseSymbolStringPoolEntry).restype, LLVMOrcReleaseSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# const char *LLVMOrcSymbolStringPoolEntryStr(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcSymbolStringPoolEntryStr:=dll.LLVMOrcSymbolStringPoolEntryStr).restype, LLVMOrcSymbolStringPoolEntryStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueResourceTracker(Struct): pass +LLVMOrcResourceTrackerRef = ctypes.POINTER(struct_LLVMOrcOpaqueResourceTracker) +# void LLVMOrcReleaseResourceTracker(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcReleaseResourceTracker:=dll.LLVMOrcReleaseResourceTracker).restype, LLVMOrcReleaseResourceTracker.argtypes = None, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcResourceTrackerTransferTo(LLVMOrcResourceTrackerRef SrcRT, LLVMOrcResourceTrackerRef DstRT) +try: (LLVMOrcResourceTrackerTransferTo:=dll.LLVMOrcResourceTrackerTransferTo).restype, LLVMOrcResourceTrackerTransferTo.argtypes = None, [LLVMOrcResourceTrackerRef, LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcResourceTrackerRemove(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcResourceTrackerRemove:=dll.LLVMOrcResourceTrackerRemove).restype, LLVMOrcResourceTrackerRemove.argtypes = LLVMErrorRef, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueDefinitionGenerator(Struct): pass +LLVMOrcDefinitionGeneratorRef = ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator) +# void LLVMOrcDisposeDefinitionGenerator(LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcDisposeDefinitionGenerator:=dll.LLVMOrcDisposeDefinitionGenerator).restype, LLVMOrcDisposeDefinitionGenerator.argtypes = None, [LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueMaterializationUnit(Struct): pass LLVMOrcMaterializationUnitRef = ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationUnit) -class struct_LLVMOrcOpaqueMaterializationResponsibility(Structure): - pass +# void LLVMOrcDisposeMaterializationUnit(LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcDisposeMaterializationUnit:=dll.LLVMOrcDisposeMaterializationUnit).restype, LLVMOrcDisposeMaterializationUnit.argtypes = None, [LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +class LLVMOrcCSymbolFlagsMapPair(Struct): pass +LLVMOrcCSymbolFlagsMapPair._fields_ = [ + ('Name', LLVMOrcSymbolStringPoolEntryRef), + ('Flags', LLVMJITSymbolFlags), +] +LLVMOrcCSymbolFlagsMapPairs = ctypes.POINTER(LLVMOrcCSymbolFlagsMapPair) +class struct_LLVMOrcOpaqueMaterializationResponsibility(Struct): pass +LLVMOrcMaterializationUnitMaterializeFunction = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility)) +LLVMOrcMaterializationUnitDiscardFunction = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib), ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) +LLVMOrcMaterializationUnitDestroyFunction = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +# LLVMOrcMaterializationUnitRef LLVMOrcCreateCustomMaterializationUnit(const char *Name, void *Ctx, LLVMOrcCSymbolFlagsMapPairs Syms, size_t NumSyms, LLVMOrcSymbolStringPoolEntryRef InitSym, LLVMOrcMaterializationUnitMaterializeFunction Materialize, LLVMOrcMaterializationUnitDiscardFunction Discard, LLVMOrcMaterializationUnitDestroyFunction Destroy) +try: (LLVMOrcCreateCustomMaterializationUnit:=dll.LLVMOrcCreateCustomMaterializationUnit).restype, LLVMOrcCreateCustomMaterializationUnit.argtypes = LLVMOrcMaterializationUnitRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, LLVMOrcCSymbolFlagsMapPairs, size_t, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcMaterializationUnitMaterializeFunction, LLVMOrcMaterializationUnitDiscardFunction, LLVMOrcMaterializationUnitDestroyFunction] +except AttributeError: pass + +LLVMOrcCSymbolMapPairs = ctypes.POINTER(LLVMOrcCSymbolMapPair) +# LLVMOrcMaterializationUnitRef LLVMOrcAbsoluteSymbols(LLVMOrcCSymbolMapPairs Syms, size_t NumPairs) +try: (LLVMOrcAbsoluteSymbols:=dll.LLVMOrcAbsoluteSymbols).restype, LLVMOrcAbsoluteSymbols.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +class struct_LLVMOrcOpaqueLazyCallThroughManager(Struct): pass +LLVMOrcLazyCallThroughManagerRef = ctypes.POINTER(struct_LLVMOrcOpaqueLazyCallThroughManager) +class struct_LLVMOrcOpaqueIndirectStubsManager(Struct): pass +LLVMOrcIndirectStubsManagerRef = ctypes.POINTER(struct_LLVMOrcOpaqueIndirectStubsManager) +class LLVMOrcCSymbolAliasMapPair(Struct): pass +class LLVMOrcCSymbolAliasMapEntry(Struct): pass +LLVMOrcCSymbolAliasMapEntry._fields_ = [ + ('Name', LLVMOrcSymbolStringPoolEntryRef), + ('Flags', LLVMJITSymbolFlags), +] +LLVMOrcCSymbolAliasMapPair._fields_ = [ + ('Name', LLVMOrcSymbolStringPoolEntryRef), + ('Entry', LLVMOrcCSymbolAliasMapEntry), +] +LLVMOrcCSymbolAliasMapPairs = ctypes.POINTER(LLVMOrcCSymbolAliasMapPair) +# LLVMOrcMaterializationUnitRef LLVMOrcLazyReexports(LLVMOrcLazyCallThroughManagerRef LCTM, LLVMOrcIndirectStubsManagerRef ISM, LLVMOrcJITDylibRef SourceRef, LLVMOrcCSymbolAliasMapPairs CallableAliases, size_t NumPairs) +try: (LLVMOrcLazyReexports:=dll.LLVMOrcLazyReexports).restype, LLVMOrcLazyReexports.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcLazyCallThroughManagerRef, LLVMOrcIndirectStubsManagerRef, LLVMOrcJITDylibRef, LLVMOrcCSymbolAliasMapPairs, size_t] +except AttributeError: pass LLVMOrcMaterializationResponsibilityRef = ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility) -LLVMOrcMaterializationUnitMaterializeFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility)) -LLVMOrcMaterializationUnitDiscardFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib), ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) -LLVMOrcMaterializationUnitDestroyFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -class struct_LLVMOrcOpaqueResourceTracker(Structure): - pass +# void LLVMOrcDisposeMaterializationResponsibility(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcDisposeMaterializationResponsibility:=dll.LLVMOrcDisposeMaterializationResponsibility).restype, LLVMOrcDisposeMaterializationResponsibility.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass -LLVMOrcResourceTrackerRef = ctypes.POINTER(struct_LLVMOrcOpaqueResourceTracker) -class struct_LLVMOrcOpaqueDefinitionGenerator(Structure): - pass +# LLVMOrcJITDylibRef LLVMOrcMaterializationResponsibilityGetTargetDylib(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetTargetDylib:=dll.LLVMOrcMaterializationResponsibilityGetTargetDylib).restype, LLVMOrcMaterializationResponsibilityGetTargetDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass -LLVMOrcDefinitionGeneratorRef = ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator) -class struct_LLVMOrcOpaqueLookupState(Structure): - pass +# LLVMOrcExecutionSessionRef LLVMOrcMaterializationResponsibilityGetExecutionSession(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetExecutionSession:=dll.LLVMOrcMaterializationResponsibilityGetExecutionSession).restype, LLVMOrcMaterializationResponsibilityGetExecutionSession.argtypes = LLVMOrcExecutionSessionRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcCSymbolFlagsMapPairs LLVMOrcMaterializationResponsibilityGetSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumPairs) +try: (LLVMOrcMaterializationResponsibilityGetSymbols:=dll.LLVMOrcMaterializationResponsibilityGetSymbols).restype, LLVMOrcMaterializationResponsibilityGetSymbols.argtypes = LLVMOrcCSymbolFlagsMapPairs, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeCSymbolFlagsMap(LLVMOrcCSymbolFlagsMapPairs Pairs) +try: (LLVMOrcDisposeCSymbolFlagsMap:=dll.LLVMOrcDisposeCSymbolFlagsMap).restype, LLVMOrcDisposeCSymbolFlagsMap.argtypes = None, [LLVMOrcCSymbolFlagsMapPairs] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcMaterializationResponsibilityGetInitializerSymbol(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetInitializerSymbol:=dll.LLVMOrcMaterializationResponsibilityGetInitializerSymbol).restype, LLVMOrcMaterializationResponsibilityGetInitializerSymbol.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef *LLVMOrcMaterializationResponsibilityGetRequestedSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumSymbols) +try: (LLVMOrcMaterializationResponsibilityGetRequestedSymbols:=dll.LLVMOrcMaterializationResponsibilityGetRequestedSymbols).restype, LLVMOrcMaterializationResponsibilityGetRequestedSymbols.argtypes = ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeSymbols(LLVMOrcSymbolStringPoolEntryRef *Symbols) +try: (LLVMOrcDisposeSymbols:=dll.LLVMOrcDisposeSymbols).restype, LLVMOrcDisposeSymbols.argtypes = None, [ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyResolved(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolMapPairs Symbols, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityNotifyResolved:=dll.LLVMOrcMaterializationResponsibilityNotifyResolved).restype, LLVMOrcMaterializationResponsibilityNotifyResolved.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +class LLVMOrcCSymbolDependenceGroup(Struct): pass +class LLVMOrcCSymbolsList(Struct): pass +LLVMOrcCSymbolsList._fields_ = [ + ('Symbols', ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef)), + ('Length', size_t), +] +class LLVMOrcCDependenceMapPair(Struct): pass +LLVMOrcCDependenceMapPair._fields_ = [ + ('JD', LLVMOrcJITDylibRef), + ('Names', LLVMOrcCSymbolsList), +] +LLVMOrcCDependenceMapPairs = ctypes.POINTER(LLVMOrcCDependenceMapPair) +LLVMOrcCSymbolDependenceGroup._fields_ = [ + ('Symbols', LLVMOrcCSymbolsList), + ('Dependencies', LLVMOrcCDependenceMapPairs), + ('NumDependencies', size_t), +] +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyEmitted(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolDependenceGroup *SymbolDepGroups, size_t NumSymbolDepGroups) +try: (LLVMOrcMaterializationResponsibilityNotifyEmitted:=dll.LLVMOrcMaterializationResponsibilityNotifyEmitted).restype, LLVMOrcMaterializationResponsibilityNotifyEmitted.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcCSymbolDependenceGroup), size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDefineMaterializing(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolFlagsMapPairs Pairs, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityDefineMaterializing:=dll.LLVMOrcMaterializationResponsibilityDefineMaterializing).restype, LLVMOrcMaterializationResponsibilityDefineMaterializing.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolFlagsMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcMaterializationResponsibilityFailMaterialization(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityFailMaterialization:=dll.LLVMOrcMaterializationResponsibilityFailMaterialization).restype, LLVMOrcMaterializationResponsibilityFailMaterialization.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityReplace(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcMaterializationResponsibilityReplace:=dll.LLVMOrcMaterializationResponsibilityReplace).restype, LLVMOrcMaterializationResponsibilityReplace.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDelegate(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcSymbolStringPoolEntryRef *Symbols, size_t NumSymbols, LLVMOrcMaterializationResponsibilityRef *Result) +try: (LLVMOrcMaterializationResponsibilityDelegate:=dll.LLVMOrcMaterializationResponsibilityDelegate).restype, LLVMOrcMaterializationResponsibilityDelegate.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), size_t, ctypes.POINTER(LLVMOrcMaterializationResponsibilityRef)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionCreateBareJITDylib(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionCreateBareJITDylib:=dll.LLVMOrcExecutionSessionCreateBareJITDylib).restype, LLVMOrcExecutionSessionCreateBareJITDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcExecutionSessionCreateJITDylib(LLVMOrcExecutionSessionRef ES, LLVMOrcJITDylibRef *Result, const char *Name) +try: (LLVMOrcExecutionSessionCreateJITDylib:=dll.LLVMOrcExecutionSessionCreateJITDylib).restype, LLVMOrcExecutionSessionCreateJITDylib.argtypes = LLVMErrorRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(LLVMOrcJITDylibRef), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionGetJITDylibByName(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionGetJITDylibByName:=dll.LLVMOrcExecutionSessionGetJITDylibByName).restype, LLVMOrcExecutionSessionGetJITDylibByName.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibCreateResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibCreateResourceTracker:=dll.LLVMOrcJITDylibCreateResourceTracker).restype, LLVMOrcJITDylibCreateResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibGetDefaultResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibGetDefaultResourceTracker:=dll.LLVMOrcJITDylibGetDefaultResourceTracker).restype, LLVMOrcJITDylibGetDefaultResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibDefine(LLVMOrcJITDylibRef JD, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcJITDylibDefine:=dll.LLVMOrcJITDylibDefine).restype, LLVMOrcJITDylibDefine.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibClear(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibClear:=dll.LLVMOrcJITDylibClear).restype, LLVMOrcJITDylibClear.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# void LLVMOrcJITDylibAddGenerator(LLVMOrcJITDylibRef JD, LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcJITDylibAddGenerator:=dll.LLVMOrcJITDylibAddGenerator).restype, LLVMOrcJITDylibAddGenerator.argtypes = None, [LLVMOrcJITDylibRef, LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueLookupState(Struct): pass +LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator), ctypes.c_void_p, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLookupState)), LLVMOrcLookupKind, ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib), LLVMOrcJITDylibLookupFlags, ctypes.POINTER(LLVMOrcCLookupSetElement), ctypes.c_uint64) +LLVMOrcDisposeCAPIDefinitionGeneratorFunction = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +# LLVMOrcDefinitionGeneratorRef LLVMOrcCreateCustomCAPIDefinitionGenerator(LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction F, void *Ctx, LLVMOrcDisposeCAPIDefinitionGeneratorFunction Dispose) +try: (LLVMOrcCreateCustomCAPIDefinitionGenerator:=dll.LLVMOrcCreateCustomCAPIDefinitionGenerator).restype, LLVMOrcCreateCustomCAPIDefinitionGenerator.argtypes = LLVMOrcDefinitionGeneratorRef, [LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction, ctypes.c_void_p, LLVMOrcDisposeCAPIDefinitionGeneratorFunction] +except AttributeError: pass LLVMOrcLookupStateRef = ctypes.POINTER(struct_LLVMOrcOpaqueLookupState) -LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator), ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLookupState)), c__EA_LLVMOrcLookupKind, ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib), c__EA_LLVMOrcJITDylibLookupFlags, ctypes.POINTER(struct_c__SA_LLVMOrcCLookupSetElement), ctypes.c_uint64) -LLVMOrcSymbolPredicate = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) -class struct_LLVMOrcOpaqueThreadSafeContext(Structure): - pass +# void LLVMOrcLookupStateContinueLookup(LLVMOrcLookupStateRef S, LLVMErrorRef Err) +try: (LLVMOrcLookupStateContinueLookup:=dll.LLVMOrcLookupStateContinueLookup).restype, LLVMOrcLookupStateContinueLookup.argtypes = None, [LLVMOrcLookupStateRef, LLVMErrorRef] +except AttributeError: pass -LLVMOrcThreadSafeContextRef = ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeContext) -class struct_LLVMOrcOpaqueThreadSafeModule(Structure): - pass +LLVMOrcSymbolPredicate = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_void_p, ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess(LLVMOrcDefinitionGeneratorRef *Result, char GlobalPrefx, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass -LLVMOrcThreadSafeModuleRef = ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeModule) -LLVMOrcGenericIRModuleOperationFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOpaqueModule)) -class struct_LLVMOrcOpaqueJITTargetMachineBuilder(Structure): - pass - -LLVMOrcJITTargetMachineBuilderRef = ctypes.POINTER(struct_LLVMOrcOpaqueJITTargetMachineBuilder) -class struct_LLVMOrcOpaqueObjectLayer(Structure): - pass +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, const char *FileName, char GlobalPrefix, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForPath).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.POINTER(ctypes.c_char), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass +class struct_LLVMOrcOpaqueObjectLayer(Struct): pass LLVMOrcObjectLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectLayer) -class struct_LLVMOrcOpaqueObjectLinkingLayer(Structure): - pass +# LLVMErrorRef LLVMOrcCreateStaticLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, LLVMOrcObjectLayerRef ObjLayer, const char *FileName, const char *TargetTriple) +try: (LLVMOrcCreateStaticLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateStaticLibrarySearchGeneratorForPath).restype, LLVMOrcCreateStaticLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), LLVMOrcObjectLayerRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -LLVMOrcObjectLinkingLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectLinkingLayer) -class struct_LLVMOrcOpaqueIRTransformLayer(Structure): - pass +class struct_LLVMOrcOpaqueThreadSafeContext(Struct): pass +LLVMOrcThreadSafeContextRef = ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeContext) +# LLVMOrcThreadSafeContextRef LLVMOrcCreateNewThreadSafeContext(void) +try: (LLVMOrcCreateNewThreadSafeContext:=dll.LLVMOrcCreateNewThreadSafeContext).restype, LLVMOrcCreateNewThreadSafeContext.argtypes = LLVMOrcThreadSafeContextRef, [] +except AttributeError: pass +# LLVMContextRef LLVMOrcThreadSafeContextGetContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcThreadSafeContextGetContext:=dll.LLVMOrcThreadSafeContextGetContext).restype, LLVMOrcThreadSafeContextGetContext.argtypes = LLVMContextRef, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcDisposeThreadSafeContext:=dll.LLVMOrcDisposeThreadSafeContext).restype, LLVMOrcDisposeThreadSafeContext.argtypes = None, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueThreadSafeModule(Struct): pass +LLVMOrcThreadSafeModuleRef = ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeModule) +# LLVMOrcThreadSafeModuleRef LLVMOrcCreateNewThreadSafeModule(LLVMModuleRef M, LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcCreateNewThreadSafeModule:=dll.LLVMOrcCreateNewThreadSafeModule).restype, LLVMOrcCreateNewThreadSafeModule.argtypes = LLVMOrcThreadSafeModuleRef, [LLVMModuleRef, LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeModule(LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcDisposeThreadSafeModule:=dll.LLVMOrcDisposeThreadSafeModule).restype, LLVMOrcDisposeThreadSafeModule.argtypes = None, [LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +LLVMOrcGenericIRModuleOperationFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.c_void_p, ctypes.POINTER(struct_LLVMOpaqueModule)) +# LLVMErrorRef LLVMOrcThreadSafeModuleWithModuleDo(LLVMOrcThreadSafeModuleRef TSM, LLVMOrcGenericIRModuleOperationFunction F, void *Ctx) +try: (LLVMOrcThreadSafeModuleWithModuleDo:=dll.LLVMOrcThreadSafeModuleWithModuleDo).restype, LLVMOrcThreadSafeModuleWithModuleDo.argtypes = LLVMErrorRef, [LLVMOrcThreadSafeModuleRef, LLVMOrcGenericIRModuleOperationFunction, ctypes.c_void_p] +except AttributeError: pass + +class struct_LLVMOrcOpaqueJITTargetMachineBuilder(Struct): pass +LLVMOrcJITTargetMachineBuilderRef = ctypes.POINTER(struct_LLVMOrcOpaqueJITTargetMachineBuilder) +# LLVMErrorRef LLVMOrcJITTargetMachineBuilderDetectHost(LLVMOrcJITTargetMachineBuilderRef *Result) +try: (LLVMOrcJITTargetMachineBuilderDetectHost:=dll.LLVMOrcJITTargetMachineBuilderDetectHost).restype, LLVMOrcJITTargetMachineBuilderDetectHost.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcJITTargetMachineBuilderRef)] +except AttributeError: pass + +# LLVMOrcJITTargetMachineBuilderRef LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine(LLVMTargetMachineRef TM) +try: (LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine:=dll.LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine).restype, LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.argtypes = LLVMOrcJITTargetMachineBuilderRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMOrcDisposeJITTargetMachineBuilder(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcDisposeJITTargetMachineBuilder:=dll.LLVMOrcDisposeJITTargetMachineBuilder).restype, LLVMOrcDisposeJITTargetMachineBuilder.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# char *LLVMOrcJITTargetMachineBuilderGetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcJITTargetMachineBuilderGetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderGetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderGetTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# void LLVMOrcJITTargetMachineBuilderSetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB, const char *TargetTriple) +try: (LLVMOrcJITTargetMachineBuilderSetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderSetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderSetTargetTriple.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFile(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcJITDylibRef JD, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFile:=dll.LLVMOrcObjectLayerAddObjectFile).restype, LLVMOrcObjectLayerAddObjectFile.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFileWithRT(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcResourceTrackerRef RT, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFileWithRT:=dll.LLVMOrcObjectLayerAddObjectFileWithRT).restype, LLVMOrcObjectLayerAddObjectFileWithRT.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcObjectLayerEmit(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcMaterializationResponsibilityRef R, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerEmit:=dll.LLVMOrcObjectLayerEmit).restype, LLVMOrcObjectLayerEmit.argtypes = None, [LLVMOrcObjectLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcDisposeObjectLayer(LLVMOrcObjectLayerRef ObjLayer) +try: (LLVMOrcDisposeObjectLayer:=dll.LLVMOrcDisposeObjectLayer).restype, LLVMOrcDisposeObjectLayer.argtypes = None, [LLVMOrcObjectLayerRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueIRTransformLayer(Struct): pass LLVMOrcIRTransformLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueIRTransformLayer) -LLVMOrcIRTransformLayerTransformFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeModule)), ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility)) -class struct_LLVMOrcOpaqueObjectTransformLayer(Structure): - pass +# void LLVMOrcIRTransformLayerEmit(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcIRTransformLayerEmit:=dll.LLVMOrcIRTransformLayerEmit).restype, LLVMOrcIRTransformLayerEmit.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass +LLVMOrcIRTransformLayerTransformFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.c_void_p, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueThreadSafeModule)), ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility)) +# void LLVMOrcIRTransformLayerSetTransform(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcIRTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcIRTransformLayerSetTransform:=dll.LLVMOrcIRTransformLayerSetTransform).restype, LLVMOrcIRTransformLayerSetTransform.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcIRTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +class struct_LLVMOrcOpaqueObjectTransformLayer(Struct): pass LLVMOrcObjectTransformLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectTransformLayer) -LLVMOrcObjectTransformLayerTransformFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.POINTER(None), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))) -class struct_LLVMOrcOpaqueIndirectStubsManager(Structure): - pass +LLVMOrcObjectTransformLayerTransformFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueError), ctypes.c_void_p, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))) +# void LLVMOrcObjectTransformLayerSetTransform(LLVMOrcObjectTransformLayerRef ObjTransformLayer, LLVMOrcObjectTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcObjectTransformLayerSetTransform:=dll.LLVMOrcObjectTransformLayerSetTransform).restype, LLVMOrcObjectTransformLayerSetTransform.argtypes = None, [LLVMOrcObjectTransformLayerRef, LLVMOrcObjectTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass -LLVMOrcIndirectStubsManagerRef = ctypes.POINTER(struct_LLVMOrcOpaqueIndirectStubsManager) -class struct_LLVMOrcOpaqueLazyCallThroughManager(Structure): - pass +# LLVMOrcIndirectStubsManagerRef LLVMOrcCreateLocalIndirectStubsManager(const char *TargetTriple) +try: (LLVMOrcCreateLocalIndirectStubsManager:=dll.LLVMOrcCreateLocalIndirectStubsManager).restype, LLVMOrcCreateLocalIndirectStubsManager.argtypes = LLVMOrcIndirectStubsManagerRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -LLVMOrcLazyCallThroughManagerRef = ctypes.POINTER(struct_LLVMOrcOpaqueLazyCallThroughManager) -class struct_LLVMOrcOpaqueDumpObjects(Structure): - pass +# void LLVMOrcDisposeIndirectStubsManager(LLVMOrcIndirectStubsManagerRef ISM) +try: (LLVMOrcDisposeIndirectStubsManager:=dll.LLVMOrcDisposeIndirectStubsManager).restype, LLVMOrcDisposeIndirectStubsManager.argtypes = None, [LLVMOrcIndirectStubsManagerRef] +except AttributeError: pass +LLVMOrcJITTargetAddress = ctypes.c_uint64 +# LLVMErrorRef LLVMOrcCreateLocalLazyCallThroughManager(const char *TargetTriple, LLVMOrcExecutionSessionRef ES, LLVMOrcJITTargetAddress ErrorHandlerAddr, LLVMOrcLazyCallThroughManagerRef *LCTM) +try: (LLVMOrcCreateLocalLazyCallThroughManager:=dll.LLVMOrcCreateLocalLazyCallThroughManager).restype, LLVMOrcCreateLocalLazyCallThroughManager.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char), LLVMOrcExecutionSessionRef, LLVMOrcJITTargetAddress, ctypes.POINTER(LLVMOrcLazyCallThroughManagerRef)] +except AttributeError: pass + +# void LLVMOrcDisposeLazyCallThroughManager(LLVMOrcLazyCallThroughManagerRef LCTM) +try: (LLVMOrcDisposeLazyCallThroughManager:=dll.LLVMOrcDisposeLazyCallThroughManager).restype, LLVMOrcDisposeLazyCallThroughManager.argtypes = None, [LLVMOrcLazyCallThroughManagerRef] +except AttributeError: pass + +class struct_LLVMOrcOpaqueDumpObjects(Struct): pass LLVMOrcDumpObjectsRef = ctypes.POINTER(struct_LLVMOrcOpaqueDumpObjects) -try: - LLVMOrcExecutionSessionSetErrorReporter = _libraries['llvm'].LLVMOrcExecutionSessionSetErrorReporter - LLVMOrcExecutionSessionSetErrorReporter.restype = None - LLVMOrcExecutionSessionSetErrorReporter.argtypes = [LLVMOrcExecutionSessionRef, LLVMOrcErrorReporterFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionGetSymbolStringPool = _libraries['llvm'].LLVMOrcExecutionSessionGetSymbolStringPool - LLVMOrcExecutionSessionGetSymbolStringPool.restype = LLVMOrcSymbolStringPoolRef - LLVMOrcExecutionSessionGetSymbolStringPool.argtypes = [LLVMOrcExecutionSessionRef] -except AttributeError: - pass -try: - LLVMOrcSymbolStringPoolClearDeadEntries = _libraries['llvm'].LLVMOrcSymbolStringPoolClearDeadEntries - LLVMOrcSymbolStringPoolClearDeadEntries.restype = None - LLVMOrcSymbolStringPoolClearDeadEntries.argtypes = [LLVMOrcSymbolStringPoolRef] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionIntern = _libraries['llvm'].LLVMOrcExecutionSessionIntern - LLVMOrcExecutionSessionIntern.restype = LLVMOrcSymbolStringPoolEntryRef - LLVMOrcExecutionSessionIntern.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcRetainSymbolStringPoolEntry = _libraries['llvm'].LLVMOrcRetainSymbolStringPoolEntry - LLVMOrcRetainSymbolStringPoolEntry.restype = None - LLVMOrcRetainSymbolStringPoolEntry.argtypes = [LLVMOrcSymbolStringPoolEntryRef] -except AttributeError: - pass -try: - LLVMOrcReleaseSymbolStringPoolEntry = _libraries['llvm'].LLVMOrcReleaseSymbolStringPoolEntry - LLVMOrcReleaseSymbolStringPoolEntry.restype = None - LLVMOrcReleaseSymbolStringPoolEntry.argtypes = [LLVMOrcSymbolStringPoolEntryRef] -except AttributeError: - pass -try: - LLVMOrcSymbolStringPoolEntryStr = _libraries['llvm'].LLVMOrcSymbolStringPoolEntryStr - LLVMOrcSymbolStringPoolEntryStr.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcSymbolStringPoolEntryStr.argtypes = [LLVMOrcSymbolStringPoolEntryRef] -except AttributeError: - pass -try: - LLVMOrcReleaseResourceTracker = _libraries['llvm'].LLVMOrcReleaseResourceTracker - LLVMOrcReleaseResourceTracker.restype = None - LLVMOrcReleaseResourceTracker.argtypes = [LLVMOrcResourceTrackerRef] -except AttributeError: - pass -try: - LLVMOrcResourceTrackerTransferTo = _libraries['llvm'].LLVMOrcResourceTrackerTransferTo - LLVMOrcResourceTrackerTransferTo.restype = None - LLVMOrcResourceTrackerTransferTo.argtypes = [LLVMOrcResourceTrackerRef, LLVMOrcResourceTrackerRef] -except AttributeError: - pass -try: - LLVMOrcResourceTrackerRemove = _libraries['llvm'].LLVMOrcResourceTrackerRemove - LLVMOrcResourceTrackerRemove.restype = LLVMErrorRef - LLVMOrcResourceTrackerRemove.argtypes = [LLVMOrcResourceTrackerRef] -except AttributeError: - pass -try: - LLVMOrcDisposeDefinitionGenerator = _libraries['llvm'].LLVMOrcDisposeDefinitionGenerator - LLVMOrcDisposeDefinitionGenerator.restype = None - LLVMOrcDisposeDefinitionGenerator.argtypes = [LLVMOrcDefinitionGeneratorRef] -except AttributeError: - pass -try: - LLVMOrcDisposeMaterializationUnit = _libraries['llvm'].LLVMOrcDisposeMaterializationUnit - LLVMOrcDisposeMaterializationUnit.restype = None - LLVMOrcDisposeMaterializationUnit.argtypes = [LLVMOrcMaterializationUnitRef] -except AttributeError: - pass -try: - LLVMOrcCreateCustomMaterializationUnit = _libraries['llvm'].LLVMOrcCreateCustomMaterializationUnit - LLVMOrcCreateCustomMaterializationUnit.restype = LLVMOrcMaterializationUnitRef - LLVMOrcCreateCustomMaterializationUnit.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), LLVMOrcCSymbolFlagsMapPairs, size_t, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcMaterializationUnitMaterializeFunction, LLVMOrcMaterializationUnitDiscardFunction, LLVMOrcMaterializationUnitDestroyFunction] -except AttributeError: - pass -try: - LLVMOrcAbsoluteSymbols = _libraries['llvm'].LLVMOrcAbsoluteSymbols - LLVMOrcAbsoluteSymbols.restype = LLVMOrcMaterializationUnitRef - LLVMOrcAbsoluteSymbols.argtypes = [LLVMOrcCSymbolMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcLazyReexports = _libraries['llvm'].LLVMOrcLazyReexports - LLVMOrcLazyReexports.restype = LLVMOrcMaterializationUnitRef - LLVMOrcLazyReexports.argtypes = [LLVMOrcLazyCallThroughManagerRef, LLVMOrcIndirectStubsManagerRef, LLVMOrcJITDylibRef, LLVMOrcCSymbolAliasMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcDisposeMaterializationResponsibility = _libraries['llvm'].LLVMOrcDisposeMaterializationResponsibility - LLVMOrcDisposeMaterializationResponsibility.restype = None - LLVMOrcDisposeMaterializationResponsibility.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetTargetDylib = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetTargetDylib - LLVMOrcMaterializationResponsibilityGetTargetDylib.restype = LLVMOrcJITDylibRef - LLVMOrcMaterializationResponsibilityGetTargetDylib.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetExecutionSession = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetExecutionSession - LLVMOrcMaterializationResponsibilityGetExecutionSession.restype = LLVMOrcExecutionSessionRef - LLVMOrcMaterializationResponsibilityGetExecutionSession.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetSymbols = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetSymbols - LLVMOrcMaterializationResponsibilityGetSymbols.restype = LLVMOrcCSymbolFlagsMapPairs - LLVMOrcMaterializationResponsibilityGetSymbols.argtypes = [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMOrcDisposeCSymbolFlagsMap = _libraries['llvm'].LLVMOrcDisposeCSymbolFlagsMap - LLVMOrcDisposeCSymbolFlagsMap.restype = None - LLVMOrcDisposeCSymbolFlagsMap.argtypes = [LLVMOrcCSymbolFlagsMapPairs] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetInitializerSymbol = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetInitializerSymbol - LLVMOrcMaterializationResponsibilityGetInitializerSymbol.restype = LLVMOrcSymbolStringPoolEntryRef - LLVMOrcMaterializationResponsibilityGetInitializerSymbol.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityGetRequestedSymbols = _libraries['llvm'].LLVMOrcMaterializationResponsibilityGetRequestedSymbols - LLVMOrcMaterializationResponsibilityGetRequestedSymbols.restype = ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)) - LLVMOrcMaterializationResponsibilityGetRequestedSymbols.argtypes = [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - LLVMOrcDisposeSymbols = _libraries['llvm'].LLVMOrcDisposeSymbols - LLVMOrcDisposeSymbols.restype = None - LLVMOrcDisposeSymbols.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry))] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityNotifyResolved = _libraries['llvm'].LLVMOrcMaterializationResponsibilityNotifyResolved - LLVMOrcMaterializationResponsibilityNotifyResolved.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityNotifyResolved.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityNotifyEmitted = _libraries['llvm'].LLVMOrcMaterializationResponsibilityNotifyEmitted - LLVMOrcMaterializationResponsibilityNotifyEmitted.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityNotifyEmitted.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityDefineMaterializing = _libraries['llvm'].LLVMOrcMaterializationResponsibilityDefineMaterializing - LLVMOrcMaterializationResponsibilityDefineMaterializing.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityDefineMaterializing.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolFlagsMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityFailMaterialization = _libraries['llvm'].LLVMOrcMaterializationResponsibilityFailMaterialization - LLVMOrcMaterializationResponsibilityFailMaterialization.restype = None - LLVMOrcMaterializationResponsibilityFailMaterialization.argtypes = [LLVMOrcMaterializationResponsibilityRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityReplace = _libraries['llvm'].LLVMOrcMaterializationResponsibilityReplace - LLVMOrcMaterializationResponsibilityReplace.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityReplace.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcMaterializationUnitRef] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityDelegate = _libraries['llvm'].LLVMOrcMaterializationResponsibilityDelegate - LLVMOrcMaterializationResponsibilityDelegate.restype = LLVMErrorRef - LLVMOrcMaterializationResponsibilityDelegate.argtypes = [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueSymbolStringPoolEntry)), size_t, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueMaterializationResponsibility))] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityAddDependencies = _libraries['llvm'].LLVMOrcMaterializationResponsibilityAddDependencies - LLVMOrcMaterializationResponsibilityAddDependencies.restype = None - LLVMOrcMaterializationResponsibilityAddDependencies.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcCDependenceMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcMaterializationResponsibilityAddDependenciesForAll = _libraries['llvm'].LLVMOrcMaterializationResponsibilityAddDependenciesForAll - LLVMOrcMaterializationResponsibilityAddDependenciesForAll.restype = None - LLVMOrcMaterializationResponsibilityAddDependenciesForAll.argtypes = [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCDependenceMapPairs, size_t] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionCreateBareJITDylib = _libraries['llvm'].LLVMOrcExecutionSessionCreateBareJITDylib - LLVMOrcExecutionSessionCreateBareJITDylib.restype = LLVMOrcJITDylibRef - LLVMOrcExecutionSessionCreateBareJITDylib.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionCreateJITDylib = _libraries['llvm'].LLVMOrcExecutionSessionCreateJITDylib - LLVMOrcExecutionSessionCreateJITDylib.restype = LLVMErrorRef - LLVMOrcExecutionSessionCreateJITDylib.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueJITDylib)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcExecutionSessionGetJITDylibByName = _libraries['llvm'].LLVMOrcExecutionSessionGetJITDylibByName - LLVMOrcExecutionSessionGetJITDylibByName.restype = LLVMOrcJITDylibRef - LLVMOrcExecutionSessionGetJITDylibByName.argtypes = [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcJITDylibCreateResourceTracker = _libraries['llvm'].LLVMOrcJITDylibCreateResourceTracker - LLVMOrcJITDylibCreateResourceTracker.restype = LLVMOrcResourceTrackerRef - LLVMOrcJITDylibCreateResourceTracker.argtypes = [LLVMOrcJITDylibRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibGetDefaultResourceTracker = _libraries['llvm'].LLVMOrcJITDylibGetDefaultResourceTracker - LLVMOrcJITDylibGetDefaultResourceTracker.restype = LLVMOrcResourceTrackerRef - LLVMOrcJITDylibGetDefaultResourceTracker.argtypes = [LLVMOrcJITDylibRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibDefine = _libraries['llvm'].LLVMOrcJITDylibDefine - LLVMOrcJITDylibDefine.restype = LLVMErrorRef - LLVMOrcJITDylibDefine.argtypes = [LLVMOrcJITDylibRef, LLVMOrcMaterializationUnitRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibClear = _libraries['llvm'].LLVMOrcJITDylibClear - LLVMOrcJITDylibClear.restype = LLVMErrorRef - LLVMOrcJITDylibClear.argtypes = [LLVMOrcJITDylibRef] -except AttributeError: - pass -try: - LLVMOrcJITDylibAddGenerator = _libraries['llvm'].LLVMOrcJITDylibAddGenerator - LLVMOrcJITDylibAddGenerator.restype = None - LLVMOrcJITDylibAddGenerator.argtypes = [LLVMOrcJITDylibRef, LLVMOrcDefinitionGeneratorRef] -except AttributeError: - pass -try: - LLVMOrcCreateCustomCAPIDefinitionGenerator = _libraries['llvm'].LLVMOrcCreateCustomCAPIDefinitionGenerator - LLVMOrcCreateCustomCAPIDefinitionGenerator.restype = LLVMOrcDefinitionGeneratorRef - LLVMOrcCreateCustomCAPIDefinitionGenerator.argtypes = [LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess = _libraries['llvm'].LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess - LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.restype = LLVMErrorRef - LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator)), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateDynamicLibrarySearchGeneratorForPath = _libraries['llvm'].LLVMOrcCreateDynamicLibrarySearchGeneratorForPath - LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.restype = LLVMErrorRef - LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator)), ctypes.POINTER(ctypes.c_char), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateStaticLibrarySearchGeneratorForPath = _libraries['llvm'].LLVMOrcCreateStaticLibrarySearchGeneratorForPath - LLVMOrcCreateStaticLibrarySearchGeneratorForPath.restype = LLVMErrorRef - LLVMOrcCreateStaticLibrarySearchGeneratorForPath.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueDefinitionGenerator)), LLVMOrcObjectLayerRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcCreateNewThreadSafeContext = _libraries['llvm'].LLVMOrcCreateNewThreadSafeContext - LLVMOrcCreateNewThreadSafeContext.restype = LLVMOrcThreadSafeContextRef - LLVMOrcCreateNewThreadSafeContext.argtypes = [] -except AttributeError: - pass -try: - LLVMOrcThreadSafeContextGetContext = _libraries['llvm'].LLVMOrcThreadSafeContextGetContext - LLVMOrcThreadSafeContextGetContext.restype = LLVMContextRef - LLVMOrcThreadSafeContextGetContext.argtypes = [LLVMOrcThreadSafeContextRef] -except AttributeError: - pass -try: - LLVMOrcDisposeThreadSafeContext = _libraries['llvm'].LLVMOrcDisposeThreadSafeContext - LLVMOrcDisposeThreadSafeContext.restype = None - LLVMOrcDisposeThreadSafeContext.argtypes = [LLVMOrcThreadSafeContextRef] -except AttributeError: - pass -try: - LLVMOrcCreateNewThreadSafeModule = _libraries['llvm'].LLVMOrcCreateNewThreadSafeModule - LLVMOrcCreateNewThreadSafeModule.restype = LLVMOrcThreadSafeModuleRef - LLVMOrcCreateNewThreadSafeModule.argtypes = [LLVMModuleRef, LLVMOrcThreadSafeContextRef] -except AttributeError: - pass -try: - LLVMOrcDisposeThreadSafeModule = _libraries['llvm'].LLVMOrcDisposeThreadSafeModule - LLVMOrcDisposeThreadSafeModule.restype = None - LLVMOrcDisposeThreadSafeModule.argtypes = [LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcThreadSafeModuleWithModuleDo = _libraries['llvm'].LLVMOrcThreadSafeModuleWithModuleDo - LLVMOrcThreadSafeModuleWithModuleDo.restype = LLVMErrorRef - LLVMOrcThreadSafeModuleWithModuleDo.argtypes = [LLVMOrcThreadSafeModuleRef, LLVMOrcGenericIRModuleOperationFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderDetectHost = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderDetectHost - LLVMOrcJITTargetMachineBuilderDetectHost.restype = LLVMErrorRef - LLVMOrcJITTargetMachineBuilderDetectHost.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueJITTargetMachineBuilder))] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine - LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.restype = LLVMOrcJITTargetMachineBuilderRef - LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.argtypes = [LLVMTargetMachineRef] -except AttributeError: - pass -try: - LLVMOrcDisposeJITTargetMachineBuilder = _libraries['llvm'].LLVMOrcDisposeJITTargetMachineBuilder - LLVMOrcDisposeJITTargetMachineBuilder.restype = None - LLVMOrcDisposeJITTargetMachineBuilder.argtypes = [LLVMOrcJITTargetMachineBuilderRef] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderGetTargetTriple = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderGetTargetTriple - LLVMOrcJITTargetMachineBuilderGetTargetTriple.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcJITTargetMachineBuilderGetTargetTriple.argtypes = [LLVMOrcJITTargetMachineBuilderRef] -except AttributeError: - pass -try: - LLVMOrcJITTargetMachineBuilderSetTargetTriple = _libraries['llvm'].LLVMOrcJITTargetMachineBuilderSetTargetTriple - LLVMOrcJITTargetMachineBuilderSetTargetTriple.restype = None - LLVMOrcJITTargetMachineBuilderSetTargetTriple.argtypes = [LLVMOrcJITTargetMachineBuilderRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcObjectLayerAddObjectFile = _libraries['llvm'].LLVMOrcObjectLayerAddObjectFile - LLVMOrcObjectLayerAddObjectFile.restype = LLVMErrorRef - LLVMOrcObjectLayerAddObjectFile.argtypes = [LLVMOrcObjectLayerRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcObjectLayerAddObjectFileWithRT = _libraries['llvm'].LLVMOrcObjectLayerAddObjectFileWithRT - LLVMOrcObjectLayerAddObjectFileWithRT.restype = LLVMErrorRef - LLVMOrcObjectLayerAddObjectFileWithRT.argtypes = [LLVMOrcObjectLayerRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcObjectLayerEmit = _libraries['llvm'].LLVMOrcObjectLayerEmit - LLVMOrcObjectLayerEmit.restype = None - LLVMOrcObjectLayerEmit.argtypes = [LLVMOrcObjectLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcDisposeObjectLayer = _libraries['llvm'].LLVMOrcDisposeObjectLayer - LLVMOrcDisposeObjectLayer.restype = None - LLVMOrcDisposeObjectLayer.argtypes = [LLVMOrcObjectLayerRef] -except AttributeError: - pass -try: - LLVMOrcIRTransformLayerEmit = _libraries['llvm'].LLVMOrcIRTransformLayerEmit - LLVMOrcIRTransformLayerEmit.restype = None - LLVMOrcIRTransformLayerEmit.argtypes = [LLVMOrcIRTransformLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcIRTransformLayerSetTransform = _libraries['llvm'].LLVMOrcIRTransformLayerSetTransform - LLVMOrcIRTransformLayerSetTransform.restype = None - LLVMOrcIRTransformLayerSetTransform.argtypes = [LLVMOrcIRTransformLayerRef, LLVMOrcIRTransformLayerTransformFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcObjectTransformLayerSetTransform = _libraries['llvm'].LLVMOrcObjectTransformLayerSetTransform - LLVMOrcObjectTransformLayerSetTransform.restype = None - LLVMOrcObjectTransformLayerSetTransform.argtypes = [LLVMOrcObjectTransformLayerRef, LLVMOrcObjectTransformLayerTransformFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateLocalIndirectStubsManager = _libraries['llvm'].LLVMOrcCreateLocalIndirectStubsManager - LLVMOrcCreateLocalIndirectStubsManager.restype = LLVMOrcIndirectStubsManagerRef - LLVMOrcCreateLocalIndirectStubsManager.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcDisposeIndirectStubsManager = _libraries['llvm'].LLVMOrcDisposeIndirectStubsManager - LLVMOrcDisposeIndirectStubsManager.restype = None - LLVMOrcDisposeIndirectStubsManager.argtypes = [LLVMOrcIndirectStubsManagerRef] -except AttributeError: - pass -try: - LLVMOrcCreateLocalLazyCallThroughManager = _libraries['llvm'].LLVMOrcCreateLocalLazyCallThroughManager - LLVMOrcCreateLocalLazyCallThroughManager.restype = LLVMErrorRef - LLVMOrcCreateLocalLazyCallThroughManager.argtypes = [ctypes.POINTER(ctypes.c_char), LLVMOrcExecutionSessionRef, LLVMOrcJITTargetAddress, ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLazyCallThroughManager))] -except AttributeError: - pass -try: - LLVMOrcDisposeLazyCallThroughManager = _libraries['llvm'].LLVMOrcDisposeLazyCallThroughManager - LLVMOrcDisposeLazyCallThroughManager.restype = None - LLVMOrcDisposeLazyCallThroughManager.argtypes = [LLVMOrcLazyCallThroughManagerRef] -except AttributeError: - pass -try: - LLVMOrcCreateDumpObjects = _libraries['llvm'].LLVMOrcCreateDumpObjects - LLVMOrcCreateDumpObjects.restype = LLVMOrcDumpObjectsRef - LLVMOrcCreateDumpObjects.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcDisposeDumpObjects = _libraries['llvm'].LLVMOrcDisposeDumpObjects - LLVMOrcDisposeDumpObjects.restype = None - LLVMOrcDisposeDumpObjects.argtypes = [LLVMOrcDumpObjectsRef] -except AttributeError: - pass -try: - LLVMOrcDumpObjects_CallOperator = _libraries['llvm'].LLVMOrcDumpObjects_CallOperator - LLVMOrcDumpObjects_CallOperator.restype = LLVMErrorRef - LLVMOrcDumpObjects_CallOperator.argtypes = [LLVMOrcDumpObjectsRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueMemoryBuffer))] -except AttributeError: - pass -LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOrcOpaqueObjectLayer), ctypes.POINTER(None), ctypes.POINTER(struct_LLVMOrcOpaqueExecutionSession), ctypes.POINTER(ctypes.c_char)) -class struct_LLVMOrcOpaqueLLJITBuilder(Structure): - pass +# LLVMOrcDumpObjectsRef LLVMOrcCreateDumpObjects(const char *DumpDir, const char *IdentifierOverride) +try: (LLVMOrcCreateDumpObjects:=dll.LLVMOrcCreateDumpObjects).restype, LLVMOrcCreateDumpObjects.argtypes = LLVMOrcDumpObjectsRef, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass +# void LLVMOrcDisposeDumpObjects(LLVMOrcDumpObjectsRef DumpObjects) +try: (LLVMOrcDisposeDumpObjects:=dll.LLVMOrcDisposeDumpObjects).restype, LLVMOrcDisposeDumpObjects.argtypes = None, [LLVMOrcDumpObjectsRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcDumpObjects_CallOperator(LLVMOrcDumpObjectsRef DumpObjects, LLVMMemoryBufferRef *ObjBuffer) +try: (LLVMOrcDumpObjects_CallOperator:=dll.LLVMOrcDumpObjects_CallOperator).restype, LLVMOrcDumpObjects_CallOperator.argtypes = LLVMErrorRef, [LLVMOrcDumpObjectsRef, ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction = ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOrcOpaqueObjectLayer), ctypes.c_void_p, ctypes.POINTER(struct_LLVMOrcOpaqueExecutionSession), ctypes.POINTER(ctypes.c_char)) +class struct_LLVMOrcOpaqueLLJITBuilder(Struct): pass LLVMOrcLLJITBuilderRef = ctypes.POINTER(struct_LLVMOrcOpaqueLLJITBuilder) -class struct_LLVMOrcOpaqueLLJIT(Structure): - pass - +class struct_LLVMOrcOpaqueLLJIT(Struct): pass LLVMOrcLLJITRef = ctypes.POINTER(struct_LLVMOrcOpaqueLLJIT) -try: - LLVMOrcCreateLLJITBuilder = _libraries['llvm'].LLVMOrcCreateLLJITBuilder - LLVMOrcCreateLLJITBuilder.restype = LLVMOrcLLJITBuilderRef - LLVMOrcCreateLLJITBuilder.argtypes = [] -except AttributeError: - pass -try: - LLVMOrcDisposeLLJITBuilder = _libraries['llvm'].LLVMOrcDisposeLLJITBuilder - LLVMOrcDisposeLLJITBuilder.restype = None - LLVMOrcDisposeLLJITBuilder.argtypes = [LLVMOrcLLJITBuilderRef] -except AttributeError: - pass -try: - LLVMOrcLLJITBuilderSetJITTargetMachineBuilder = _libraries['llvm'].LLVMOrcLLJITBuilderSetJITTargetMachineBuilder - LLVMOrcLLJITBuilderSetJITTargetMachineBuilder.restype = None - LLVMOrcLLJITBuilderSetJITTargetMachineBuilder.argtypes = [LLVMOrcLLJITBuilderRef, LLVMOrcJITTargetMachineBuilderRef] -except AttributeError: - pass -try: - LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator = _libraries['llvm'].LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator - LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator.restype = None - LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator.argtypes = [LLVMOrcLLJITBuilderRef, LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction, ctypes.POINTER(None)] -except AttributeError: - pass -try: - LLVMOrcCreateLLJIT = _libraries['llvm'].LLVMOrcCreateLLJIT - LLVMOrcCreateLLJIT.restype = LLVMErrorRef - LLVMOrcCreateLLJIT.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOrcOpaqueLLJIT)), LLVMOrcLLJITBuilderRef] -except AttributeError: - pass -try: - LLVMOrcDisposeLLJIT = _libraries['llvm'].LLVMOrcDisposeLLJIT - LLVMOrcDisposeLLJIT.restype = LLVMErrorRef - LLVMOrcDisposeLLJIT.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetExecutionSession = _libraries['llvm'].LLVMOrcLLJITGetExecutionSession - LLVMOrcLLJITGetExecutionSession.restype = LLVMOrcExecutionSessionRef - LLVMOrcLLJITGetExecutionSession.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetMainJITDylib = _libraries['llvm'].LLVMOrcLLJITGetMainJITDylib - LLVMOrcLLJITGetMainJITDylib.restype = LLVMOrcJITDylibRef - LLVMOrcLLJITGetMainJITDylib.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetTripleString = _libraries['llvm'].LLVMOrcLLJITGetTripleString - LLVMOrcLLJITGetTripleString.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcLLJITGetTripleString.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetGlobalPrefix = _libraries['llvm'].LLVMOrcLLJITGetGlobalPrefix - LLVMOrcLLJITGetGlobalPrefix.restype = ctypes.c_char - LLVMOrcLLJITGetGlobalPrefix.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITMangleAndIntern = _libraries['llvm'].LLVMOrcLLJITMangleAndIntern - LLVMOrcLLJITMangleAndIntern.restype = LLVMOrcSymbolStringPoolEntryRef - LLVMOrcLLJITMangleAndIntern.argtypes = [LLVMOrcLLJITRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcLLJITAddObjectFile = _libraries['llvm'].LLVMOrcLLJITAddObjectFile - LLVMOrcLLJITAddObjectFile.restype = LLVMErrorRef - LLVMOrcLLJITAddObjectFile.argtypes = [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcLLJITAddObjectFileWithRT = _libraries['llvm'].LLVMOrcLLJITAddObjectFileWithRT - LLVMOrcLLJITAddObjectFileWithRT.restype = LLVMErrorRef - LLVMOrcLLJITAddObjectFileWithRT.argtypes = [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMOrcLLJITAddLLVMIRModule = _libraries['llvm'].LLVMOrcLLJITAddLLVMIRModule - LLVMOrcLLJITAddLLVMIRModule.restype = LLVMErrorRef - LLVMOrcLLJITAddLLVMIRModule.argtypes = [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcLLJITAddLLVMIRModuleWithRT = _libraries['llvm'].LLVMOrcLLJITAddLLVMIRModuleWithRT - LLVMOrcLLJITAddLLVMIRModuleWithRT.restype = LLVMErrorRef - LLVMOrcLLJITAddLLVMIRModuleWithRT.argtypes = [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMOrcThreadSafeModuleRef] -except AttributeError: - pass -try: - LLVMOrcLLJITLookup = _libraries['llvm'].LLVMOrcLLJITLookup - LLVMOrcLLJITLookup.restype = LLVMErrorRef - LLVMOrcLLJITLookup.argtypes = [LLVMOrcLLJITRef, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMOrcLLJITGetObjLinkingLayer = _libraries['llvm'].LLVMOrcLLJITGetObjLinkingLayer - LLVMOrcLLJITGetObjLinkingLayer.restype = LLVMOrcObjectLayerRef - LLVMOrcLLJITGetObjLinkingLayer.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetObjTransformLayer = _libraries['llvm'].LLVMOrcLLJITGetObjTransformLayer - LLVMOrcLLJITGetObjTransformLayer.restype = LLVMOrcObjectTransformLayerRef - LLVMOrcLLJITGetObjTransformLayer.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetIRTransformLayer = _libraries['llvm'].LLVMOrcLLJITGetIRTransformLayer - LLVMOrcLLJITGetIRTransformLayer.restype = LLVMOrcIRTransformLayerRef - LLVMOrcLLJITGetIRTransformLayer.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -try: - LLVMOrcLLJITGetDataLayoutStr = _libraries['llvm'].LLVMOrcLLJITGetDataLayoutStr - LLVMOrcLLJITGetDataLayoutStr.restype = ctypes.POINTER(ctypes.c_char) - LLVMOrcLLJITGetDataLayoutStr.argtypes = [LLVMOrcLLJITRef] -except AttributeError: - pass -LLVM_C_LINKER_H = True # macro +# LLVMOrcLLJITBuilderRef LLVMOrcCreateLLJITBuilder(void) +try: (LLVMOrcCreateLLJITBuilder:=dll.LLVMOrcCreateLLJITBuilder).restype, LLVMOrcCreateLLJITBuilder.argtypes = LLVMOrcLLJITBuilderRef, [] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMLinkerMode' -c__EA_LLVMLinkerMode__enumvalues = { - 0: 'LLVMLinkerDestroySource', - 1: 'LLVMLinkerPreserveSource_Removed', -} -LLVMLinkerDestroySource = 0 -LLVMLinkerPreserveSource_Removed = 1 -c__EA_LLVMLinkerMode = ctypes.c_uint32 # enum -LLVMLinkerMode = c__EA_LLVMLinkerMode -LLVMLinkerMode__enumvalues = c__EA_LLVMLinkerMode__enumvalues -try: - LLVMLinkModules2 = _libraries['llvm'].LLVMLinkModules2 - LLVMLinkModules2.restype = LLVMBool - LLVMLinkModules2.argtypes = [LLVMModuleRef, LLVMModuleRef] -except AttributeError: - pass -LLVM_C_OBJECT_H = True # macro -class struct_LLVMOpaqueSectionIterator(Structure): - pass +# void LLVMOrcDisposeLLJITBuilder(LLVMOrcLLJITBuilderRef Builder) +try: (LLVMOrcDisposeLLJITBuilder:=dll.LLVMOrcDisposeLLJITBuilder).restype, LLVMOrcDisposeLLJITBuilder.argtypes = None, [LLVMOrcLLJITBuilderRef] +except AttributeError: pass +# void LLVMOrcLLJITBuilderSetJITTargetMachineBuilder(LLVMOrcLLJITBuilderRef Builder, LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcLLJITBuilderSetJITTargetMachineBuilder:=dll.LLVMOrcLLJITBuilderSetJITTargetMachineBuilder).restype, LLVMOrcLLJITBuilderSetJITTargetMachineBuilder.argtypes = None, [LLVMOrcLLJITBuilderRef, LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# void LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator(LLVMOrcLLJITBuilderRef Builder, LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction F, void *Ctx) +try: (LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator:=dll.LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator).restype, LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator.argtypes = None, [LLVMOrcLLJITBuilderRef, LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateLLJIT(LLVMOrcLLJITRef *Result, LLVMOrcLLJITBuilderRef Builder) +try: (LLVMOrcCreateLLJIT:=dll.LLVMOrcCreateLLJIT).restype, LLVMOrcCreateLLJIT.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcLLJITRef), LLVMOrcLLJITBuilderRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcDisposeLLJIT(LLVMOrcLLJITRef J) +try: (LLVMOrcDisposeLLJIT:=dll.LLVMOrcDisposeLLJIT).restype, LLVMOrcDisposeLLJIT.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcExecutionSessionRef LLVMOrcLLJITGetExecutionSession(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetExecutionSession:=dll.LLVMOrcLLJITGetExecutionSession).restype, LLVMOrcLLJITGetExecutionSession.argtypes = LLVMOrcExecutionSessionRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcLLJITGetMainJITDylib(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetMainJITDylib:=dll.LLVMOrcLLJITGetMainJITDylib).restype, LLVMOrcLLJITGetMainJITDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# const char *LLVMOrcLLJITGetTripleString(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetTripleString:=dll.LLVMOrcLLJITGetTripleString).restype, LLVMOrcLLJITGetTripleString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcLLJITRef] +except AttributeError: pass + +# char LLVMOrcLLJITGetGlobalPrefix(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetGlobalPrefix:=dll.LLVMOrcLLJITGetGlobalPrefix).restype, LLVMOrcLLJITGetGlobalPrefix.argtypes = ctypes.c_char, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcLLJITMangleAndIntern(LLVMOrcLLJITRef J, const char *UnmangledName) +try: (LLVMOrcLLJITMangleAndIntern:=dll.LLVMOrcLLJITMangleAndIntern).restype, LLVMOrcLLJITMangleAndIntern.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcLLJITRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddObjectFile(LLVMOrcLLJITRef J, LLVMOrcJITDylibRef JD, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcLLJITAddObjectFile:=dll.LLVMOrcLLJITAddObjectFile).restype, LLVMOrcLLJITAddObjectFile.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddObjectFileWithRT(LLVMOrcLLJITRef J, LLVMOrcResourceTrackerRef RT, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcLLJITAddObjectFileWithRT:=dll.LLVMOrcLLJITAddObjectFileWithRT).restype, LLVMOrcLLJITAddObjectFileWithRT.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddLLVMIRModule(LLVMOrcLLJITRef J, LLVMOrcJITDylibRef JD, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcLLJITAddLLVMIRModule:=dll.LLVMOrcLLJITAddLLVMIRModule).restype, LLVMOrcLLJITAddLLVMIRModule.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddLLVMIRModuleWithRT(LLVMOrcLLJITRef J, LLVMOrcResourceTrackerRef JD, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcLLJITAddLLVMIRModuleWithRT:=dll.LLVMOrcLLJITAddLLVMIRModuleWithRT).restype, LLVMOrcLLJITAddLLVMIRModuleWithRT.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITLookup(LLVMOrcLLJITRef J, LLVMOrcExecutorAddress *Result, const char *Name) +try: (LLVMOrcLLJITLookup:=dll.LLVMOrcLLJITLookup).restype, LLVMOrcLLJITLookup.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, ctypes.POINTER(LLVMOrcExecutorAddress), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcObjectLayerRef LLVMOrcLLJITGetObjLinkingLayer(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetObjLinkingLayer:=dll.LLVMOrcLLJITGetObjLinkingLayer).restype, LLVMOrcLLJITGetObjLinkingLayer.argtypes = LLVMOrcObjectLayerRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcObjectTransformLayerRef LLVMOrcLLJITGetObjTransformLayer(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetObjTransformLayer:=dll.LLVMOrcLLJITGetObjTransformLayer).restype, LLVMOrcLLJITGetObjTransformLayer.argtypes = LLVMOrcObjectTransformLayerRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcIRTransformLayerRef LLVMOrcLLJITGetIRTransformLayer(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetIRTransformLayer:=dll.LLVMOrcLLJITGetIRTransformLayer).restype, LLVMOrcLLJITGetIRTransformLayer.argtypes = LLVMOrcIRTransformLayerRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# const char *LLVMOrcLLJITGetDataLayoutStr(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetDataLayoutStr:=dll.LLVMOrcLLJITGetDataLayoutStr).restype, LLVMOrcLLJITGetDataLayoutStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetErrorTypeId(LLVMErrorRef Err) +try: (LLVMGetErrorTypeId:=dll.LLVMGetErrorTypeId).restype, LLVMGetErrorTypeId.argtypes = LLVMErrorTypeId, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMConsumeError(LLVMErrorRef Err) +try: (LLVMConsumeError:=dll.LLVMConsumeError).restype, LLVMConsumeError.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMCantFail(LLVMErrorRef Err) +try: (LLVMCantFail:=dll.LLVMCantFail).restype, LLVMCantFail.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# char *LLVMGetErrorMessage(LLVMErrorRef Err) +try: (LLVMGetErrorMessage:=dll.LLVMGetErrorMessage).restype, LLVMGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMErrorRef] +except AttributeError: pass + +# void LLVMDisposeErrorMessage(char *ErrMsg) +try: (LLVMDisposeErrorMessage:=dll.LLVMDisposeErrorMessage).restype, LLVMDisposeErrorMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetStringErrorTypeId(void) +try: (LLVMGetStringErrorTypeId:=dll.LLVMGetStringErrorTypeId).restype, LLVMGetStringErrorTypeId.argtypes = LLVMErrorTypeId, [] +except AttributeError: pass + +# LLVMErrorRef LLVMCreateStringError(const char *ErrMsg) +try: (LLVMCreateStringError:=dll.LLVMCreateStringError).restype, LLVMCreateStringError.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass + +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +# void LLVMOrcExecutionSessionSetErrorReporter(LLVMOrcExecutionSessionRef ES, LLVMOrcErrorReporterFunction ReportError, void *Ctx) +try: (LLVMOrcExecutionSessionSetErrorReporter:=dll.LLVMOrcExecutionSessionSetErrorReporter).restype, LLVMOrcExecutionSessionSetErrorReporter.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcErrorReporterFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolRef LLVMOrcExecutionSessionGetSymbolStringPool(LLVMOrcExecutionSessionRef ES) +try: (LLVMOrcExecutionSessionGetSymbolStringPool:=dll.LLVMOrcExecutionSessionGetSymbolStringPool).restype, LLVMOrcExecutionSessionGetSymbolStringPool.argtypes = LLVMOrcSymbolStringPoolRef, [LLVMOrcExecutionSessionRef] +except AttributeError: pass + +# void LLVMOrcSymbolStringPoolClearDeadEntries(LLVMOrcSymbolStringPoolRef SSP) +try: (LLVMOrcSymbolStringPoolClearDeadEntries:=dll.LLVMOrcSymbolStringPoolClearDeadEntries).restype, LLVMOrcSymbolStringPoolClearDeadEntries.argtypes = None, [LLVMOrcSymbolStringPoolRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcExecutionSessionIntern(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionIntern:=dll.LLVMOrcExecutionSessionIntern).restype, LLVMOrcExecutionSessionIntern.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcExecutionSessionLookup(LLVMOrcExecutionSessionRef ES, LLVMOrcLookupKind K, LLVMOrcCJITDylibSearchOrder SearchOrder, size_t SearchOrderSize, LLVMOrcCLookupSet Symbols, size_t SymbolsSize, LLVMOrcExecutionSessionLookupHandleResultFunction HandleResult, void *Ctx) +try: (LLVMOrcExecutionSessionLookup:=dll.LLVMOrcExecutionSessionLookup).restype, LLVMOrcExecutionSessionLookup.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcLookupKind, LLVMOrcCJITDylibSearchOrder, size_t, LLVMOrcCLookupSet, size_t, LLVMOrcExecutionSessionLookupHandleResultFunction, ctypes.c_void_p] +except AttributeError: pass + +# void LLVMOrcRetainSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcRetainSymbolStringPoolEntry:=dll.LLVMOrcRetainSymbolStringPoolEntry).restype, LLVMOrcRetainSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# void LLVMOrcReleaseSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcReleaseSymbolStringPoolEntry:=dll.LLVMOrcReleaseSymbolStringPoolEntry).restype, LLVMOrcReleaseSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# const char *LLVMOrcSymbolStringPoolEntryStr(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcSymbolStringPoolEntryStr:=dll.LLVMOrcSymbolStringPoolEntryStr).restype, LLVMOrcSymbolStringPoolEntryStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# void LLVMOrcReleaseResourceTracker(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcReleaseResourceTracker:=dll.LLVMOrcReleaseResourceTracker).restype, LLVMOrcReleaseResourceTracker.argtypes = None, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcResourceTrackerTransferTo(LLVMOrcResourceTrackerRef SrcRT, LLVMOrcResourceTrackerRef DstRT) +try: (LLVMOrcResourceTrackerTransferTo:=dll.LLVMOrcResourceTrackerTransferTo).restype, LLVMOrcResourceTrackerTransferTo.argtypes = None, [LLVMOrcResourceTrackerRef, LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcResourceTrackerRemove(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcResourceTrackerRemove:=dll.LLVMOrcResourceTrackerRemove).restype, LLVMOrcResourceTrackerRemove.argtypes = LLVMErrorRef, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcDisposeDefinitionGenerator(LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcDisposeDefinitionGenerator:=dll.LLVMOrcDisposeDefinitionGenerator).restype, LLVMOrcDisposeDefinitionGenerator.argtypes = None, [LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +# void LLVMOrcDisposeMaterializationUnit(LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcDisposeMaterializationUnit:=dll.LLVMOrcDisposeMaterializationUnit).restype, LLVMOrcDisposeMaterializationUnit.argtypes = None, [LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcCreateCustomMaterializationUnit(const char *Name, void *Ctx, LLVMOrcCSymbolFlagsMapPairs Syms, size_t NumSyms, LLVMOrcSymbolStringPoolEntryRef InitSym, LLVMOrcMaterializationUnitMaterializeFunction Materialize, LLVMOrcMaterializationUnitDiscardFunction Discard, LLVMOrcMaterializationUnitDestroyFunction Destroy) +try: (LLVMOrcCreateCustomMaterializationUnit:=dll.LLVMOrcCreateCustomMaterializationUnit).restype, LLVMOrcCreateCustomMaterializationUnit.argtypes = LLVMOrcMaterializationUnitRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, LLVMOrcCSymbolFlagsMapPairs, size_t, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcMaterializationUnitMaterializeFunction, LLVMOrcMaterializationUnitDiscardFunction, LLVMOrcMaterializationUnitDestroyFunction] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcAbsoluteSymbols(LLVMOrcCSymbolMapPairs Syms, size_t NumPairs) +try: (LLVMOrcAbsoluteSymbols:=dll.LLVMOrcAbsoluteSymbols).restype, LLVMOrcAbsoluteSymbols.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcLazyReexports(LLVMOrcLazyCallThroughManagerRef LCTM, LLVMOrcIndirectStubsManagerRef ISM, LLVMOrcJITDylibRef SourceRef, LLVMOrcCSymbolAliasMapPairs CallableAliases, size_t NumPairs) +try: (LLVMOrcLazyReexports:=dll.LLVMOrcLazyReexports).restype, LLVMOrcLazyReexports.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcLazyCallThroughManagerRef, LLVMOrcIndirectStubsManagerRef, LLVMOrcJITDylibRef, LLVMOrcCSymbolAliasMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcDisposeMaterializationResponsibility(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcDisposeMaterializationResponsibility:=dll.LLVMOrcDisposeMaterializationResponsibility).restype, LLVMOrcDisposeMaterializationResponsibility.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcMaterializationResponsibilityGetTargetDylib(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetTargetDylib:=dll.LLVMOrcMaterializationResponsibilityGetTargetDylib).restype, LLVMOrcMaterializationResponsibilityGetTargetDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcExecutionSessionRef LLVMOrcMaterializationResponsibilityGetExecutionSession(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetExecutionSession:=dll.LLVMOrcMaterializationResponsibilityGetExecutionSession).restype, LLVMOrcMaterializationResponsibilityGetExecutionSession.argtypes = LLVMOrcExecutionSessionRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcCSymbolFlagsMapPairs LLVMOrcMaterializationResponsibilityGetSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumPairs) +try: (LLVMOrcMaterializationResponsibilityGetSymbols:=dll.LLVMOrcMaterializationResponsibilityGetSymbols).restype, LLVMOrcMaterializationResponsibilityGetSymbols.argtypes = LLVMOrcCSymbolFlagsMapPairs, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeCSymbolFlagsMap(LLVMOrcCSymbolFlagsMapPairs Pairs) +try: (LLVMOrcDisposeCSymbolFlagsMap:=dll.LLVMOrcDisposeCSymbolFlagsMap).restype, LLVMOrcDisposeCSymbolFlagsMap.argtypes = None, [LLVMOrcCSymbolFlagsMapPairs] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcMaterializationResponsibilityGetInitializerSymbol(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetInitializerSymbol:=dll.LLVMOrcMaterializationResponsibilityGetInitializerSymbol).restype, LLVMOrcMaterializationResponsibilityGetInitializerSymbol.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef *LLVMOrcMaterializationResponsibilityGetRequestedSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumSymbols) +try: (LLVMOrcMaterializationResponsibilityGetRequestedSymbols:=dll.LLVMOrcMaterializationResponsibilityGetRequestedSymbols).restype, LLVMOrcMaterializationResponsibilityGetRequestedSymbols.argtypes = ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeSymbols(LLVMOrcSymbolStringPoolEntryRef *Symbols) +try: (LLVMOrcDisposeSymbols:=dll.LLVMOrcDisposeSymbols).restype, LLVMOrcDisposeSymbols.argtypes = None, [ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyResolved(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolMapPairs Symbols, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityNotifyResolved:=dll.LLVMOrcMaterializationResponsibilityNotifyResolved).restype, LLVMOrcMaterializationResponsibilityNotifyResolved.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyEmitted(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolDependenceGroup *SymbolDepGroups, size_t NumSymbolDepGroups) +try: (LLVMOrcMaterializationResponsibilityNotifyEmitted:=dll.LLVMOrcMaterializationResponsibilityNotifyEmitted).restype, LLVMOrcMaterializationResponsibilityNotifyEmitted.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcCSymbolDependenceGroup), size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDefineMaterializing(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolFlagsMapPairs Pairs, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityDefineMaterializing:=dll.LLVMOrcMaterializationResponsibilityDefineMaterializing).restype, LLVMOrcMaterializationResponsibilityDefineMaterializing.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolFlagsMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcMaterializationResponsibilityFailMaterialization(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityFailMaterialization:=dll.LLVMOrcMaterializationResponsibilityFailMaterialization).restype, LLVMOrcMaterializationResponsibilityFailMaterialization.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityReplace(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcMaterializationResponsibilityReplace:=dll.LLVMOrcMaterializationResponsibilityReplace).restype, LLVMOrcMaterializationResponsibilityReplace.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDelegate(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcSymbolStringPoolEntryRef *Symbols, size_t NumSymbols, LLVMOrcMaterializationResponsibilityRef *Result) +try: (LLVMOrcMaterializationResponsibilityDelegate:=dll.LLVMOrcMaterializationResponsibilityDelegate).restype, LLVMOrcMaterializationResponsibilityDelegate.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), size_t, ctypes.POINTER(LLVMOrcMaterializationResponsibilityRef)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionCreateBareJITDylib(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionCreateBareJITDylib:=dll.LLVMOrcExecutionSessionCreateBareJITDylib).restype, LLVMOrcExecutionSessionCreateBareJITDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcExecutionSessionCreateJITDylib(LLVMOrcExecutionSessionRef ES, LLVMOrcJITDylibRef *Result, const char *Name) +try: (LLVMOrcExecutionSessionCreateJITDylib:=dll.LLVMOrcExecutionSessionCreateJITDylib).restype, LLVMOrcExecutionSessionCreateJITDylib.argtypes = LLVMErrorRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(LLVMOrcJITDylibRef), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionGetJITDylibByName(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionGetJITDylibByName:=dll.LLVMOrcExecutionSessionGetJITDylibByName).restype, LLVMOrcExecutionSessionGetJITDylibByName.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibCreateResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibCreateResourceTracker:=dll.LLVMOrcJITDylibCreateResourceTracker).restype, LLVMOrcJITDylibCreateResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibGetDefaultResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibGetDefaultResourceTracker:=dll.LLVMOrcJITDylibGetDefaultResourceTracker).restype, LLVMOrcJITDylibGetDefaultResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibDefine(LLVMOrcJITDylibRef JD, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcJITDylibDefine:=dll.LLVMOrcJITDylibDefine).restype, LLVMOrcJITDylibDefine.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibClear(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibClear:=dll.LLVMOrcJITDylibClear).restype, LLVMOrcJITDylibClear.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# void LLVMOrcJITDylibAddGenerator(LLVMOrcJITDylibRef JD, LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcJITDylibAddGenerator:=dll.LLVMOrcJITDylibAddGenerator).restype, LLVMOrcJITDylibAddGenerator.argtypes = None, [LLVMOrcJITDylibRef, LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +# LLVMOrcDefinitionGeneratorRef LLVMOrcCreateCustomCAPIDefinitionGenerator(LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction F, void *Ctx, LLVMOrcDisposeCAPIDefinitionGeneratorFunction Dispose) +try: (LLVMOrcCreateCustomCAPIDefinitionGenerator:=dll.LLVMOrcCreateCustomCAPIDefinitionGenerator).restype, LLVMOrcCreateCustomCAPIDefinitionGenerator.argtypes = LLVMOrcDefinitionGeneratorRef, [LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction, ctypes.c_void_p, LLVMOrcDisposeCAPIDefinitionGeneratorFunction] +except AttributeError: pass + +# void LLVMOrcLookupStateContinueLookup(LLVMOrcLookupStateRef S, LLVMErrorRef Err) +try: (LLVMOrcLookupStateContinueLookup:=dll.LLVMOrcLookupStateContinueLookup).restype, LLVMOrcLookupStateContinueLookup.argtypes = None, [LLVMOrcLookupStateRef, LLVMErrorRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess(LLVMOrcDefinitionGeneratorRef *Result, char GlobalPrefx, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, const char *FileName, char GlobalPrefix, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForPath).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.POINTER(ctypes.c_char), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateStaticLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, LLVMOrcObjectLayerRef ObjLayer, const char *FileName, const char *TargetTriple) +try: (LLVMOrcCreateStaticLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateStaticLibrarySearchGeneratorForPath).restype, LLVMOrcCreateStaticLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), LLVMOrcObjectLayerRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcThreadSafeContextRef LLVMOrcCreateNewThreadSafeContext(void) +try: (LLVMOrcCreateNewThreadSafeContext:=dll.LLVMOrcCreateNewThreadSafeContext).restype, LLVMOrcCreateNewThreadSafeContext.argtypes = LLVMOrcThreadSafeContextRef, [] +except AttributeError: pass + +# LLVMContextRef LLVMOrcThreadSafeContextGetContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcThreadSafeContextGetContext:=dll.LLVMOrcThreadSafeContextGetContext).restype, LLVMOrcThreadSafeContextGetContext.argtypes = LLVMContextRef, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcDisposeThreadSafeContext:=dll.LLVMOrcDisposeThreadSafeContext).restype, LLVMOrcDisposeThreadSafeContext.argtypes = None, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# LLVMOrcThreadSafeModuleRef LLVMOrcCreateNewThreadSafeModule(LLVMModuleRef M, LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcCreateNewThreadSafeModule:=dll.LLVMOrcCreateNewThreadSafeModule).restype, LLVMOrcCreateNewThreadSafeModule.argtypes = LLVMOrcThreadSafeModuleRef, [LLVMModuleRef, LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeModule(LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcDisposeThreadSafeModule:=dll.LLVMOrcDisposeThreadSafeModule).restype, LLVMOrcDisposeThreadSafeModule.argtypes = None, [LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcThreadSafeModuleWithModuleDo(LLVMOrcThreadSafeModuleRef TSM, LLVMOrcGenericIRModuleOperationFunction F, void *Ctx) +try: (LLVMOrcThreadSafeModuleWithModuleDo:=dll.LLVMOrcThreadSafeModuleWithModuleDo).restype, LLVMOrcThreadSafeModuleWithModuleDo.argtypes = LLVMErrorRef, [LLVMOrcThreadSafeModuleRef, LLVMOrcGenericIRModuleOperationFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITTargetMachineBuilderDetectHost(LLVMOrcJITTargetMachineBuilderRef *Result) +try: (LLVMOrcJITTargetMachineBuilderDetectHost:=dll.LLVMOrcJITTargetMachineBuilderDetectHost).restype, LLVMOrcJITTargetMachineBuilderDetectHost.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcJITTargetMachineBuilderRef)] +except AttributeError: pass + +# LLVMOrcJITTargetMachineBuilderRef LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine(LLVMTargetMachineRef TM) +try: (LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine:=dll.LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine).restype, LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.argtypes = LLVMOrcJITTargetMachineBuilderRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMOrcDisposeJITTargetMachineBuilder(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcDisposeJITTargetMachineBuilder:=dll.LLVMOrcDisposeJITTargetMachineBuilder).restype, LLVMOrcDisposeJITTargetMachineBuilder.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# char *LLVMOrcJITTargetMachineBuilderGetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcJITTargetMachineBuilderGetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderGetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderGetTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# void LLVMOrcJITTargetMachineBuilderSetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB, const char *TargetTriple) +try: (LLVMOrcJITTargetMachineBuilderSetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderSetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderSetTargetTriple.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFile(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcJITDylibRef JD, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFile:=dll.LLVMOrcObjectLayerAddObjectFile).restype, LLVMOrcObjectLayerAddObjectFile.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFileWithRT(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcResourceTrackerRef RT, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFileWithRT:=dll.LLVMOrcObjectLayerAddObjectFileWithRT).restype, LLVMOrcObjectLayerAddObjectFileWithRT.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcObjectLayerEmit(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcMaterializationResponsibilityRef R, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerEmit:=dll.LLVMOrcObjectLayerEmit).restype, LLVMOrcObjectLayerEmit.argtypes = None, [LLVMOrcObjectLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcDisposeObjectLayer(LLVMOrcObjectLayerRef ObjLayer) +try: (LLVMOrcDisposeObjectLayer:=dll.LLVMOrcDisposeObjectLayer).restype, LLVMOrcDisposeObjectLayer.argtypes = None, [LLVMOrcObjectLayerRef] +except AttributeError: pass + +# void LLVMOrcIRTransformLayerEmit(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcIRTransformLayerEmit:=dll.LLVMOrcIRTransformLayerEmit).restype, LLVMOrcIRTransformLayerEmit.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# void LLVMOrcIRTransformLayerSetTransform(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcIRTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcIRTransformLayerSetTransform:=dll.LLVMOrcIRTransformLayerSetTransform).restype, LLVMOrcIRTransformLayerSetTransform.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcIRTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +# void LLVMOrcObjectTransformLayerSetTransform(LLVMOrcObjectTransformLayerRef ObjTransformLayer, LLVMOrcObjectTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcObjectTransformLayerSetTransform:=dll.LLVMOrcObjectTransformLayerSetTransform).restype, LLVMOrcObjectTransformLayerSetTransform.argtypes = None, [LLVMOrcObjectTransformLayerRef, LLVMOrcObjectTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMOrcIndirectStubsManagerRef LLVMOrcCreateLocalIndirectStubsManager(const char *TargetTriple) +try: (LLVMOrcCreateLocalIndirectStubsManager:=dll.LLVMOrcCreateLocalIndirectStubsManager).restype, LLVMOrcCreateLocalIndirectStubsManager.argtypes = LLVMOrcIndirectStubsManagerRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcDisposeIndirectStubsManager(LLVMOrcIndirectStubsManagerRef ISM) +try: (LLVMOrcDisposeIndirectStubsManager:=dll.LLVMOrcDisposeIndirectStubsManager).restype, LLVMOrcDisposeIndirectStubsManager.argtypes = None, [LLVMOrcIndirectStubsManagerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateLocalLazyCallThroughManager(const char *TargetTriple, LLVMOrcExecutionSessionRef ES, LLVMOrcJITTargetAddress ErrorHandlerAddr, LLVMOrcLazyCallThroughManagerRef *LCTM) +try: (LLVMOrcCreateLocalLazyCallThroughManager:=dll.LLVMOrcCreateLocalLazyCallThroughManager).restype, LLVMOrcCreateLocalLazyCallThroughManager.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char), LLVMOrcExecutionSessionRef, LLVMOrcJITTargetAddress, ctypes.POINTER(LLVMOrcLazyCallThroughManagerRef)] +except AttributeError: pass + +# void LLVMOrcDisposeLazyCallThroughManager(LLVMOrcLazyCallThroughManagerRef LCTM) +try: (LLVMOrcDisposeLazyCallThroughManager:=dll.LLVMOrcDisposeLazyCallThroughManager).restype, LLVMOrcDisposeLazyCallThroughManager.argtypes = None, [LLVMOrcLazyCallThroughManagerRef] +except AttributeError: pass + +# LLVMOrcDumpObjectsRef LLVMOrcCreateDumpObjects(const char *DumpDir, const char *IdentifierOverride) +try: (LLVMOrcCreateDumpObjects:=dll.LLVMOrcCreateDumpObjects).restype, LLVMOrcCreateDumpObjects.argtypes = LLVMOrcDumpObjectsRef, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcDisposeDumpObjects(LLVMOrcDumpObjectsRef DumpObjects) +try: (LLVMOrcDisposeDumpObjects:=dll.LLVMOrcDisposeDumpObjects).restype, LLVMOrcDisposeDumpObjects.argtypes = None, [LLVMOrcDumpObjectsRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcDumpObjects_CallOperator(LLVMOrcDumpObjectsRef DumpObjects, LLVMMemoryBufferRef *ObjBuffer) +try: (LLVMOrcDumpObjects_CallOperator:=dll.LLVMOrcDumpObjects_CallOperator).restype, LLVMOrcDumpObjects_CallOperator.argtypes = LLVMErrorRef, [LLVMOrcDumpObjectsRef, ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# LLVMOrcLLJITBuilderRef LLVMOrcCreateLLJITBuilder(void) +try: (LLVMOrcCreateLLJITBuilder:=dll.LLVMOrcCreateLLJITBuilder).restype, LLVMOrcCreateLLJITBuilder.argtypes = LLVMOrcLLJITBuilderRef, [] +except AttributeError: pass + +# void LLVMOrcDisposeLLJITBuilder(LLVMOrcLLJITBuilderRef Builder) +try: (LLVMOrcDisposeLLJITBuilder:=dll.LLVMOrcDisposeLLJITBuilder).restype, LLVMOrcDisposeLLJITBuilder.argtypes = None, [LLVMOrcLLJITBuilderRef] +except AttributeError: pass + +# void LLVMOrcLLJITBuilderSetJITTargetMachineBuilder(LLVMOrcLLJITBuilderRef Builder, LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcLLJITBuilderSetJITTargetMachineBuilder:=dll.LLVMOrcLLJITBuilderSetJITTargetMachineBuilder).restype, LLVMOrcLLJITBuilderSetJITTargetMachineBuilder.argtypes = None, [LLVMOrcLLJITBuilderRef, LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# void LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator(LLVMOrcLLJITBuilderRef Builder, LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction F, void *Ctx) +try: (LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator:=dll.LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator).restype, LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator.argtypes = None, [LLVMOrcLLJITBuilderRef, LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateLLJIT(LLVMOrcLLJITRef *Result, LLVMOrcLLJITBuilderRef Builder) +try: (LLVMOrcCreateLLJIT:=dll.LLVMOrcCreateLLJIT).restype, LLVMOrcCreateLLJIT.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcLLJITRef), LLVMOrcLLJITBuilderRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcDisposeLLJIT(LLVMOrcLLJITRef J) +try: (LLVMOrcDisposeLLJIT:=dll.LLVMOrcDisposeLLJIT).restype, LLVMOrcDisposeLLJIT.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcExecutionSessionRef LLVMOrcLLJITGetExecutionSession(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetExecutionSession:=dll.LLVMOrcLLJITGetExecutionSession).restype, LLVMOrcLLJITGetExecutionSession.argtypes = LLVMOrcExecutionSessionRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcLLJITGetMainJITDylib(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetMainJITDylib:=dll.LLVMOrcLLJITGetMainJITDylib).restype, LLVMOrcLLJITGetMainJITDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# const char *LLVMOrcLLJITGetTripleString(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetTripleString:=dll.LLVMOrcLLJITGetTripleString).restype, LLVMOrcLLJITGetTripleString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcLLJITRef] +except AttributeError: pass + +# char LLVMOrcLLJITGetGlobalPrefix(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetGlobalPrefix:=dll.LLVMOrcLLJITGetGlobalPrefix).restype, LLVMOrcLLJITGetGlobalPrefix.argtypes = ctypes.c_char, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcLLJITMangleAndIntern(LLVMOrcLLJITRef J, const char *UnmangledName) +try: (LLVMOrcLLJITMangleAndIntern:=dll.LLVMOrcLLJITMangleAndIntern).restype, LLVMOrcLLJITMangleAndIntern.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcLLJITRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddObjectFile(LLVMOrcLLJITRef J, LLVMOrcJITDylibRef JD, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcLLJITAddObjectFile:=dll.LLVMOrcLLJITAddObjectFile).restype, LLVMOrcLLJITAddObjectFile.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddObjectFileWithRT(LLVMOrcLLJITRef J, LLVMOrcResourceTrackerRef RT, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcLLJITAddObjectFileWithRT:=dll.LLVMOrcLLJITAddObjectFileWithRT).restype, LLVMOrcLLJITAddObjectFileWithRT.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddLLVMIRModule(LLVMOrcLLJITRef J, LLVMOrcJITDylibRef JD, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcLLJITAddLLVMIRModule:=dll.LLVMOrcLLJITAddLLVMIRModule).restype, LLVMOrcLLJITAddLLVMIRModule.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcJITDylibRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITAddLLVMIRModuleWithRT(LLVMOrcLLJITRef J, LLVMOrcResourceTrackerRef JD, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcLLJITAddLLVMIRModuleWithRT:=dll.LLVMOrcLLJITAddLLVMIRModuleWithRT).restype, LLVMOrcLLJITAddLLVMIRModuleWithRT.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, LLVMOrcResourceTrackerRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITLookup(LLVMOrcLLJITRef J, LLVMOrcExecutorAddress *Result, const char *Name) +try: (LLVMOrcLLJITLookup:=dll.LLVMOrcLLJITLookup).restype, LLVMOrcLLJITLookup.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef, ctypes.POINTER(LLVMOrcExecutorAddress), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcObjectLayerRef LLVMOrcLLJITGetObjLinkingLayer(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetObjLinkingLayer:=dll.LLVMOrcLLJITGetObjLinkingLayer).restype, LLVMOrcLLJITGetObjLinkingLayer.argtypes = LLVMOrcObjectLayerRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcObjectTransformLayerRef LLVMOrcLLJITGetObjTransformLayer(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetObjTransformLayer:=dll.LLVMOrcLLJITGetObjTransformLayer).restype, LLVMOrcLLJITGetObjTransformLayer.argtypes = LLVMOrcObjectTransformLayerRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMOrcIRTransformLayerRef LLVMOrcLLJITGetIRTransformLayer(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetIRTransformLayer:=dll.LLVMOrcLLJITGetIRTransformLayer).restype, LLVMOrcLLJITGetIRTransformLayer.argtypes = LLVMOrcIRTransformLayerRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# const char *LLVMOrcLLJITGetDataLayoutStr(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITGetDataLayoutStr:=dll.LLVMOrcLLJITGetDataLayoutStr).restype, LLVMOrcLLJITGetDataLayoutStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcLLJITRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcLLJITEnableDebugSupport(LLVMOrcLLJITRef J) +try: (LLVMOrcLLJITEnableDebugSupport:=dll.LLVMOrcLLJITEnableDebugSupport).restype, LLVMOrcLLJITEnableDebugSupport.argtypes = LLVMErrorRef, [LLVMOrcLLJITRef] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +LLVMLinkerMode = CEnum(ctypes.c_uint32) +LLVMLinkerDestroySource = LLVMLinkerMode.define('LLVMLinkerDestroySource', 0) +LLVMLinkerPreserveSource_Removed = LLVMLinkerMode.define('LLVMLinkerPreserveSource_Removed', 1) + +# LLVMBool LLVMLinkModules2(LLVMModuleRef Dest, LLVMModuleRef Src) +try: (LLVMLinkModules2:=dll.LLVMLinkModules2).restype, LLVMLinkModules2.argtypes = LLVMBool, [LLVMModuleRef, LLVMModuleRef] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +class struct_LLVMOpaqueSectionIterator(Struct): pass LLVMSectionIteratorRef = ctypes.POINTER(struct_LLVMOpaqueSectionIterator) -class struct_LLVMOpaqueSymbolIterator(Structure): - pass - +class struct_LLVMOpaqueSymbolIterator(Struct): pass LLVMSymbolIteratorRef = ctypes.POINTER(struct_LLVMOpaqueSymbolIterator) -class struct_LLVMOpaqueRelocationIterator(Structure): - pass - +class struct_LLVMOpaqueRelocationIterator(Struct): pass LLVMRelocationIteratorRef = ctypes.POINTER(struct_LLVMOpaqueRelocationIterator) +LLVMBinaryType = CEnum(ctypes.c_uint32) +LLVMBinaryTypeArchive = LLVMBinaryType.define('LLVMBinaryTypeArchive', 0) +LLVMBinaryTypeMachOUniversalBinary = LLVMBinaryType.define('LLVMBinaryTypeMachOUniversalBinary', 1) +LLVMBinaryTypeCOFFImportFile = LLVMBinaryType.define('LLVMBinaryTypeCOFFImportFile', 2) +LLVMBinaryTypeIR = LLVMBinaryType.define('LLVMBinaryTypeIR', 3) +LLVMBinaryTypeWinRes = LLVMBinaryType.define('LLVMBinaryTypeWinRes', 4) +LLVMBinaryTypeCOFF = LLVMBinaryType.define('LLVMBinaryTypeCOFF', 5) +LLVMBinaryTypeELF32L = LLVMBinaryType.define('LLVMBinaryTypeELF32L', 6) +LLVMBinaryTypeELF32B = LLVMBinaryType.define('LLVMBinaryTypeELF32B', 7) +LLVMBinaryTypeELF64L = LLVMBinaryType.define('LLVMBinaryTypeELF64L', 8) +LLVMBinaryTypeELF64B = LLVMBinaryType.define('LLVMBinaryTypeELF64B', 9) +LLVMBinaryTypeMachO32L = LLVMBinaryType.define('LLVMBinaryTypeMachO32L', 10) +LLVMBinaryTypeMachO32B = LLVMBinaryType.define('LLVMBinaryTypeMachO32B', 11) +LLVMBinaryTypeMachO64L = LLVMBinaryType.define('LLVMBinaryTypeMachO64L', 12) +LLVMBinaryTypeMachO64B = LLVMBinaryType.define('LLVMBinaryTypeMachO64B', 13) +LLVMBinaryTypeWasm = LLVMBinaryType.define('LLVMBinaryTypeWasm', 14) +LLVMBinaryTypeOffload = LLVMBinaryType.define('LLVMBinaryTypeOffload', 15) -# values for enumeration 'c__EA_LLVMBinaryType' -c__EA_LLVMBinaryType__enumvalues = { - 0: 'LLVMBinaryTypeArchive', - 1: 'LLVMBinaryTypeMachOUniversalBinary', - 2: 'LLVMBinaryTypeCOFFImportFile', - 3: 'LLVMBinaryTypeIR', - 4: 'LLVMBinaryTypeWinRes', - 5: 'LLVMBinaryTypeCOFF', - 6: 'LLVMBinaryTypeELF32L', - 7: 'LLVMBinaryTypeELF32B', - 8: 'LLVMBinaryTypeELF64L', - 9: 'LLVMBinaryTypeELF64B', - 10: 'LLVMBinaryTypeMachO32L', - 11: 'LLVMBinaryTypeMachO32B', - 12: 'LLVMBinaryTypeMachO64L', - 13: 'LLVMBinaryTypeMachO64B', - 14: 'LLVMBinaryTypeWasm', -} -LLVMBinaryTypeArchive = 0 -LLVMBinaryTypeMachOUniversalBinary = 1 -LLVMBinaryTypeCOFFImportFile = 2 -LLVMBinaryTypeIR = 3 -LLVMBinaryTypeWinRes = 4 -LLVMBinaryTypeCOFF = 5 -LLVMBinaryTypeELF32L = 6 -LLVMBinaryTypeELF32B = 7 -LLVMBinaryTypeELF64L = 8 -LLVMBinaryTypeELF64B = 9 -LLVMBinaryTypeMachO32L = 10 -LLVMBinaryTypeMachO32B = 11 -LLVMBinaryTypeMachO64L = 12 -LLVMBinaryTypeMachO64B = 13 -LLVMBinaryTypeWasm = 14 -c__EA_LLVMBinaryType = ctypes.c_uint32 # enum -LLVMBinaryType = c__EA_LLVMBinaryType -LLVMBinaryType__enumvalues = c__EA_LLVMBinaryType__enumvalues -try: - LLVMCreateBinary = _libraries['llvm'].LLVMCreateBinary - LLVMCreateBinary.restype = LLVMBinaryRef - LLVMCreateBinary.argtypes = [LLVMMemoryBufferRef, LLVMContextRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMDisposeBinary = _libraries['llvm'].LLVMDisposeBinary - LLVMDisposeBinary.restype = None - LLVMDisposeBinary.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMBinaryCopyMemoryBuffer = _libraries['llvm'].LLVMBinaryCopyMemoryBuffer - LLVMBinaryCopyMemoryBuffer.restype = LLVMMemoryBufferRef - LLVMBinaryCopyMemoryBuffer.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMBinaryGetType = _libraries['llvm'].LLVMBinaryGetType - LLVMBinaryGetType.restype = LLVMBinaryType - LLVMBinaryGetType.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMMachOUniversalBinaryCopyObjectForArch = _libraries['llvm'].LLVMMachOUniversalBinaryCopyObjectForArch - LLVMMachOUniversalBinaryCopyObjectForArch.restype = LLVMBinaryRef - LLVMMachOUniversalBinaryCopyObjectForArch.argtypes = [LLVMBinaryRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - LLVMObjectFileCopySectionIterator = _libraries['llvm'].LLVMObjectFileCopySectionIterator - LLVMObjectFileCopySectionIterator.restype = LLVMSectionIteratorRef - LLVMObjectFileCopySectionIterator.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMObjectFileIsSectionIteratorAtEnd = _libraries['llvm'].LLVMObjectFileIsSectionIteratorAtEnd - LLVMObjectFileIsSectionIteratorAtEnd.restype = LLVMBool - LLVMObjectFileIsSectionIteratorAtEnd.argtypes = [LLVMBinaryRef, LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMObjectFileCopySymbolIterator = _libraries['llvm'].LLVMObjectFileCopySymbolIterator - LLVMObjectFileCopySymbolIterator.restype = LLVMSymbolIteratorRef - LLVMObjectFileCopySymbolIterator.argtypes = [LLVMBinaryRef] -except AttributeError: - pass -try: - LLVMObjectFileIsSymbolIteratorAtEnd = _libraries['llvm'].LLVMObjectFileIsSymbolIteratorAtEnd - LLVMObjectFileIsSymbolIteratorAtEnd.restype = LLVMBool - LLVMObjectFileIsSymbolIteratorAtEnd.argtypes = [LLVMBinaryRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMDisposeSectionIterator = _libraries['llvm'].LLVMDisposeSectionIterator - LLVMDisposeSectionIterator.restype = None - LLVMDisposeSectionIterator.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToNextSection = _libraries['llvm'].LLVMMoveToNextSection - LLVMMoveToNextSection.restype = None - LLVMMoveToNextSection.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToContainingSection = _libraries['llvm'].LLVMMoveToContainingSection - LLVMMoveToContainingSection.restype = None - LLVMMoveToContainingSection.argtypes = [LLVMSectionIteratorRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMDisposeSymbolIterator = _libraries['llvm'].LLVMDisposeSymbolIterator - LLVMDisposeSymbolIterator.restype = None - LLVMDisposeSymbolIterator.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToNextSymbol = _libraries['llvm'].LLVMMoveToNextSymbol - LLVMMoveToNextSymbol.restype = None - LLVMMoveToNextSymbol.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionName = _libraries['llvm'].LLVMGetSectionName - LLVMGetSectionName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSectionName.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionSize = _libraries['llvm'].LLVMGetSectionSize - LLVMGetSectionSize.restype = uint64_t - LLVMGetSectionSize.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionContents = _libraries['llvm'].LLVMGetSectionContents - LLVMGetSectionContents.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSectionContents.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionAddress = _libraries['llvm'].LLVMGetSectionAddress - LLVMGetSectionAddress.restype = uint64_t - LLVMGetSectionAddress.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSectionContainsSymbol = _libraries['llvm'].LLVMGetSectionContainsSymbol - LLVMGetSectionContainsSymbol.restype = LLVMBool - LLVMGetSectionContainsSymbol.argtypes = [LLVMSectionIteratorRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocations = _libraries['llvm'].LLVMGetRelocations - LLVMGetRelocations.restype = LLVMRelocationIteratorRef - LLVMGetRelocations.argtypes = [LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMDisposeRelocationIterator = _libraries['llvm'].LLVMDisposeRelocationIterator - LLVMDisposeRelocationIterator.restype = None - LLVMDisposeRelocationIterator.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMIsRelocationIteratorAtEnd = _libraries['llvm'].LLVMIsRelocationIteratorAtEnd - LLVMIsRelocationIteratorAtEnd.restype = LLVMBool - LLVMIsRelocationIteratorAtEnd.argtypes = [LLVMSectionIteratorRef, LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMMoveToNextRelocation = _libraries['llvm'].LLVMMoveToNextRelocation - LLVMMoveToNextRelocation.restype = None - LLVMMoveToNextRelocation.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbolName = _libraries['llvm'].LLVMGetSymbolName - LLVMGetSymbolName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetSymbolName.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbolAddress = _libraries['llvm'].LLVMGetSymbolAddress - LLVMGetSymbolAddress.restype = uint64_t - LLVMGetSymbolAddress.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbolSize = _libraries['llvm'].LLVMGetSymbolSize - LLVMGetSymbolSize.restype = uint64_t - LLVMGetSymbolSize.argtypes = [LLVMSymbolIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationOffset = _libraries['llvm'].LLVMGetRelocationOffset - LLVMGetRelocationOffset.restype = uint64_t - LLVMGetRelocationOffset.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationSymbol = _libraries['llvm'].LLVMGetRelocationSymbol - LLVMGetRelocationSymbol.restype = LLVMSymbolIteratorRef - LLVMGetRelocationSymbol.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationType = _libraries['llvm'].LLVMGetRelocationType - LLVMGetRelocationType.restype = uint64_t - LLVMGetRelocationType.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationTypeName = _libraries['llvm'].LLVMGetRelocationTypeName - LLVMGetRelocationTypeName.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetRelocationTypeName.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -try: - LLVMGetRelocationValueString = _libraries['llvm'].LLVMGetRelocationValueString - LLVMGetRelocationValueString.restype = ctypes.POINTER(ctypes.c_char) - LLVMGetRelocationValueString.argtypes = [LLVMRelocationIteratorRef] -except AttributeError: - pass -class struct_LLVMOpaqueObjectFile(Structure): - pass +class struct_LLVMOpaqueBinary(Struct): pass +LLVMBinaryRef = ctypes.POINTER(struct_LLVMOpaqueBinary) +# LLVMBinaryRef LLVMCreateBinary(LLVMMemoryBufferRef MemBuf, LLVMContextRef Context, char **ErrorMessage) +try: (LLVMCreateBinary:=dll.LLVMCreateBinary).restype, LLVMCreateBinary.argtypes = LLVMBinaryRef, [LLVMMemoryBufferRef, LLVMContextRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass +# void LLVMDisposeBinary(LLVMBinaryRef BR) +try: (LLVMDisposeBinary:=dll.LLVMDisposeBinary).restype, LLVMDisposeBinary.argtypes = None, [LLVMBinaryRef] +except AttributeError: pass + +# LLVMMemoryBufferRef LLVMBinaryCopyMemoryBuffer(LLVMBinaryRef BR) +try: (LLVMBinaryCopyMemoryBuffer:=dll.LLVMBinaryCopyMemoryBuffer).restype, LLVMBinaryCopyMemoryBuffer.argtypes = LLVMMemoryBufferRef, [LLVMBinaryRef] +except AttributeError: pass + +# LLVMBinaryType LLVMBinaryGetType(LLVMBinaryRef BR) +try: (LLVMBinaryGetType:=dll.LLVMBinaryGetType).restype, LLVMBinaryGetType.argtypes = LLVMBinaryType, [LLVMBinaryRef] +except AttributeError: pass + +# LLVMBinaryRef LLVMMachOUniversalBinaryCopyObjectForArch(LLVMBinaryRef BR, const char *Arch, size_t ArchLen, char **ErrorMessage) +try: (LLVMMachOUniversalBinaryCopyObjectForArch:=dll.LLVMMachOUniversalBinaryCopyObjectForArch).restype, LLVMMachOUniversalBinaryCopyObjectForArch.argtypes = LLVMBinaryRef, [LLVMBinaryRef, ctypes.POINTER(ctypes.c_char), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMSectionIteratorRef LLVMObjectFileCopySectionIterator(LLVMBinaryRef BR) +try: (LLVMObjectFileCopySectionIterator:=dll.LLVMObjectFileCopySectionIterator).restype, LLVMObjectFileCopySectionIterator.argtypes = LLVMSectionIteratorRef, [LLVMBinaryRef] +except AttributeError: pass + +# LLVMBool LLVMObjectFileIsSectionIteratorAtEnd(LLVMBinaryRef BR, LLVMSectionIteratorRef SI) +try: (LLVMObjectFileIsSectionIteratorAtEnd:=dll.LLVMObjectFileIsSectionIteratorAtEnd).restype, LLVMObjectFileIsSectionIteratorAtEnd.argtypes = LLVMBool, [LLVMBinaryRef, LLVMSectionIteratorRef] +except AttributeError: pass + +# LLVMSymbolIteratorRef LLVMObjectFileCopySymbolIterator(LLVMBinaryRef BR) +try: (LLVMObjectFileCopySymbolIterator:=dll.LLVMObjectFileCopySymbolIterator).restype, LLVMObjectFileCopySymbolIterator.argtypes = LLVMSymbolIteratorRef, [LLVMBinaryRef] +except AttributeError: pass + +# LLVMBool LLVMObjectFileIsSymbolIteratorAtEnd(LLVMBinaryRef BR, LLVMSymbolIteratorRef SI) +try: (LLVMObjectFileIsSymbolIteratorAtEnd:=dll.LLVMObjectFileIsSymbolIteratorAtEnd).restype, LLVMObjectFileIsSymbolIteratorAtEnd.argtypes = LLVMBool, [LLVMBinaryRef, LLVMSymbolIteratorRef] +except AttributeError: pass + +# void LLVMDisposeSectionIterator(LLVMSectionIteratorRef SI) +try: (LLVMDisposeSectionIterator:=dll.LLVMDisposeSectionIterator).restype, LLVMDisposeSectionIterator.argtypes = None, [LLVMSectionIteratorRef] +except AttributeError: pass + +# void LLVMMoveToNextSection(LLVMSectionIteratorRef SI) +try: (LLVMMoveToNextSection:=dll.LLVMMoveToNextSection).restype, LLVMMoveToNextSection.argtypes = None, [LLVMSectionIteratorRef] +except AttributeError: pass + +# void LLVMMoveToContainingSection(LLVMSectionIteratorRef Sect, LLVMSymbolIteratorRef Sym) +try: (LLVMMoveToContainingSection:=dll.LLVMMoveToContainingSection).restype, LLVMMoveToContainingSection.argtypes = None, [LLVMSectionIteratorRef, LLVMSymbolIteratorRef] +except AttributeError: pass + +# void LLVMDisposeSymbolIterator(LLVMSymbolIteratorRef SI) +try: (LLVMDisposeSymbolIterator:=dll.LLVMDisposeSymbolIterator).restype, LLVMDisposeSymbolIterator.argtypes = None, [LLVMSymbolIteratorRef] +except AttributeError: pass + +# void LLVMMoveToNextSymbol(LLVMSymbolIteratorRef SI) +try: (LLVMMoveToNextSymbol:=dll.LLVMMoveToNextSymbol).restype, LLVMMoveToNextSymbol.argtypes = None, [LLVMSymbolIteratorRef] +except AttributeError: pass + +# const char *LLVMGetSectionName(LLVMSectionIteratorRef SI) +try: (LLVMGetSectionName:=dll.LLVMGetSectionName).restype, LLVMGetSectionName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMSectionIteratorRef] +except AttributeError: pass + +# uint64_t LLVMGetSectionSize(LLVMSectionIteratorRef SI) +try: (LLVMGetSectionSize:=dll.LLVMGetSectionSize).restype, LLVMGetSectionSize.argtypes = uint64_t, [LLVMSectionIteratorRef] +except AttributeError: pass + +# const char *LLVMGetSectionContents(LLVMSectionIteratorRef SI) +try: (LLVMGetSectionContents:=dll.LLVMGetSectionContents).restype, LLVMGetSectionContents.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMSectionIteratorRef] +except AttributeError: pass + +# uint64_t LLVMGetSectionAddress(LLVMSectionIteratorRef SI) +try: (LLVMGetSectionAddress:=dll.LLVMGetSectionAddress).restype, LLVMGetSectionAddress.argtypes = uint64_t, [LLVMSectionIteratorRef] +except AttributeError: pass + +# LLVMBool LLVMGetSectionContainsSymbol(LLVMSectionIteratorRef SI, LLVMSymbolIteratorRef Sym) +try: (LLVMGetSectionContainsSymbol:=dll.LLVMGetSectionContainsSymbol).restype, LLVMGetSectionContainsSymbol.argtypes = LLVMBool, [LLVMSectionIteratorRef, LLVMSymbolIteratorRef] +except AttributeError: pass + +# LLVMRelocationIteratorRef LLVMGetRelocations(LLVMSectionIteratorRef Section) +try: (LLVMGetRelocations:=dll.LLVMGetRelocations).restype, LLVMGetRelocations.argtypes = LLVMRelocationIteratorRef, [LLVMSectionIteratorRef] +except AttributeError: pass + +# void LLVMDisposeRelocationIterator(LLVMRelocationIteratorRef RI) +try: (LLVMDisposeRelocationIterator:=dll.LLVMDisposeRelocationIterator).restype, LLVMDisposeRelocationIterator.argtypes = None, [LLVMRelocationIteratorRef] +except AttributeError: pass + +# LLVMBool LLVMIsRelocationIteratorAtEnd(LLVMSectionIteratorRef Section, LLVMRelocationIteratorRef RI) +try: (LLVMIsRelocationIteratorAtEnd:=dll.LLVMIsRelocationIteratorAtEnd).restype, LLVMIsRelocationIteratorAtEnd.argtypes = LLVMBool, [LLVMSectionIteratorRef, LLVMRelocationIteratorRef] +except AttributeError: pass + +# void LLVMMoveToNextRelocation(LLVMRelocationIteratorRef RI) +try: (LLVMMoveToNextRelocation:=dll.LLVMMoveToNextRelocation).restype, LLVMMoveToNextRelocation.argtypes = None, [LLVMRelocationIteratorRef] +except AttributeError: pass + +# const char *LLVMGetSymbolName(LLVMSymbolIteratorRef SI) +try: (LLVMGetSymbolName:=dll.LLVMGetSymbolName).restype, LLVMGetSymbolName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMSymbolIteratorRef] +except AttributeError: pass + +# uint64_t LLVMGetSymbolAddress(LLVMSymbolIteratorRef SI) +try: (LLVMGetSymbolAddress:=dll.LLVMGetSymbolAddress).restype, LLVMGetSymbolAddress.argtypes = uint64_t, [LLVMSymbolIteratorRef] +except AttributeError: pass + +# uint64_t LLVMGetSymbolSize(LLVMSymbolIteratorRef SI) +try: (LLVMGetSymbolSize:=dll.LLVMGetSymbolSize).restype, LLVMGetSymbolSize.argtypes = uint64_t, [LLVMSymbolIteratorRef] +except AttributeError: pass + +# uint64_t LLVMGetRelocationOffset(LLVMRelocationIteratorRef RI) +try: (LLVMGetRelocationOffset:=dll.LLVMGetRelocationOffset).restype, LLVMGetRelocationOffset.argtypes = uint64_t, [LLVMRelocationIteratorRef] +except AttributeError: pass + +# LLVMSymbolIteratorRef LLVMGetRelocationSymbol(LLVMRelocationIteratorRef RI) +try: (LLVMGetRelocationSymbol:=dll.LLVMGetRelocationSymbol).restype, LLVMGetRelocationSymbol.argtypes = LLVMSymbolIteratorRef, [LLVMRelocationIteratorRef] +except AttributeError: pass + +# uint64_t LLVMGetRelocationType(LLVMRelocationIteratorRef RI) +try: (LLVMGetRelocationType:=dll.LLVMGetRelocationType).restype, LLVMGetRelocationType.argtypes = uint64_t, [LLVMRelocationIteratorRef] +except AttributeError: pass + +# const char *LLVMGetRelocationTypeName(LLVMRelocationIteratorRef RI) +try: (LLVMGetRelocationTypeName:=dll.LLVMGetRelocationTypeName).restype, LLVMGetRelocationTypeName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMRelocationIteratorRef] +except AttributeError: pass + +# const char *LLVMGetRelocationValueString(LLVMRelocationIteratorRef RI) +try: (LLVMGetRelocationValueString:=dll.LLVMGetRelocationValueString).restype, LLVMGetRelocationValueString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMRelocationIteratorRef] +except AttributeError: pass + +class struct_LLVMOpaqueObjectFile(Struct): pass LLVMObjectFileRef = ctypes.POINTER(struct_LLVMOpaqueObjectFile) -try: - LLVMCreateObjectFile = _libraries['llvm'].LLVMCreateObjectFile - LLVMCreateObjectFile.restype = LLVMObjectFileRef - LLVMCreateObjectFile.argtypes = [LLVMMemoryBufferRef] -except AttributeError: - pass -try: - LLVMDisposeObjectFile = _libraries['llvm'].LLVMDisposeObjectFile - LLVMDisposeObjectFile.restype = None - LLVMDisposeObjectFile.argtypes = [LLVMObjectFileRef] -except AttributeError: - pass -try: - LLVMGetSections = _libraries['llvm'].LLVMGetSections - LLVMGetSections.restype = LLVMSectionIteratorRef - LLVMGetSections.argtypes = [LLVMObjectFileRef] -except AttributeError: - pass -try: - LLVMIsSectionIteratorAtEnd = _libraries['llvm'].LLVMIsSectionIteratorAtEnd - LLVMIsSectionIteratorAtEnd.restype = LLVMBool - LLVMIsSectionIteratorAtEnd.argtypes = [LLVMObjectFileRef, LLVMSectionIteratorRef] -except AttributeError: - pass -try: - LLVMGetSymbols = _libraries['llvm'].LLVMGetSymbols - LLVMGetSymbols.restype = LLVMSymbolIteratorRef - LLVMGetSymbols.argtypes = [LLVMObjectFileRef] -except AttributeError: - pass -try: - LLVMIsSymbolIteratorAtEnd = _libraries['llvm'].LLVMIsSymbolIteratorAtEnd - LLVMIsSymbolIteratorAtEnd.restype = LLVMBool - LLVMIsSymbolIteratorAtEnd.argtypes = [LLVMObjectFileRef, LLVMSymbolIteratorRef] -except AttributeError: - pass -LLVM_C_ORCEE_H = True # macro -try: - LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager = _libraries['llvm'].LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager - LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager.restype = LLVMOrcObjectLayerRef - LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager.argtypes = [LLVMOrcExecutionSessionRef] -except AttributeError: - pass -try: - LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener = _libraries['llvm'].LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener - LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener.restype = None - LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener.argtypes = [LLVMOrcObjectLayerRef, LLVMJITEventListenerRef] -except AttributeError: - pass -LLVM_C_REMARKS_H = True # macro -REMARKS_API_VERSION = 1 # macro +# LLVMObjectFileRef LLVMCreateObjectFile(LLVMMemoryBufferRef MemBuf) +try: (LLVMCreateObjectFile:=dll.LLVMCreateObjectFile).restype, LLVMCreateObjectFile.argtypes = LLVMObjectFileRef, [LLVMMemoryBufferRef] +except AttributeError: pass -# values for enumeration 'LLVMRemarkType' -LLVMRemarkType__enumvalues = { - 0: 'LLVMRemarkTypeUnknown', - 1: 'LLVMRemarkTypePassed', - 2: 'LLVMRemarkTypeMissed', - 3: 'LLVMRemarkTypeAnalysis', - 4: 'LLVMRemarkTypeAnalysisFPCommute', - 5: 'LLVMRemarkTypeAnalysisAliasing', - 6: 'LLVMRemarkTypeFailure', -} -LLVMRemarkTypeUnknown = 0 -LLVMRemarkTypePassed = 1 -LLVMRemarkTypeMissed = 2 -LLVMRemarkTypeAnalysis = 3 -LLVMRemarkTypeAnalysisFPCommute = 4 -LLVMRemarkTypeAnalysisAliasing = 5 -LLVMRemarkTypeFailure = 6 -LLVMRemarkType = ctypes.c_uint32 # enum -class struct_LLVMRemarkOpaqueString(Structure): - pass +# void LLVMDisposeObjectFile(LLVMObjectFileRef ObjectFile) +try: (LLVMDisposeObjectFile:=dll.LLVMDisposeObjectFile).restype, LLVMDisposeObjectFile.argtypes = None, [LLVMObjectFileRef] +except AttributeError: pass +# LLVMSectionIteratorRef LLVMGetSections(LLVMObjectFileRef ObjectFile) +try: (LLVMGetSections:=dll.LLVMGetSections).restype, LLVMGetSections.argtypes = LLVMSectionIteratorRef, [LLVMObjectFileRef] +except AttributeError: pass + +# LLVMBool LLVMIsSectionIteratorAtEnd(LLVMObjectFileRef ObjectFile, LLVMSectionIteratorRef SI) +try: (LLVMIsSectionIteratorAtEnd:=dll.LLVMIsSectionIteratorAtEnd).restype, LLVMIsSectionIteratorAtEnd.argtypes = LLVMBool, [LLVMObjectFileRef, LLVMSectionIteratorRef] +except AttributeError: pass + +# LLVMSymbolIteratorRef LLVMGetSymbols(LLVMObjectFileRef ObjectFile) +try: (LLVMGetSymbols:=dll.LLVMGetSymbols).restype, LLVMGetSymbols.argtypes = LLVMSymbolIteratorRef, [LLVMObjectFileRef] +except AttributeError: pass + +# LLVMBool LLVMIsSymbolIteratorAtEnd(LLVMObjectFileRef ObjectFile, LLVMSymbolIteratorRef SI) +try: (LLVMIsSymbolIteratorAtEnd:=dll.LLVMIsSymbolIteratorAtEnd).restype, LLVMIsSymbolIteratorAtEnd.argtypes = LLVMBool, [LLVMObjectFileRef, LLVMSymbolIteratorRef] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetErrorTypeId(LLVMErrorRef Err) +try: (LLVMGetErrorTypeId:=dll.LLVMGetErrorTypeId).restype, LLVMGetErrorTypeId.argtypes = LLVMErrorTypeId, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMConsumeError(LLVMErrorRef Err) +try: (LLVMConsumeError:=dll.LLVMConsumeError).restype, LLVMConsumeError.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMCantFail(LLVMErrorRef Err) +try: (LLVMCantFail:=dll.LLVMCantFail).restype, LLVMCantFail.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# char *LLVMGetErrorMessage(LLVMErrorRef Err) +try: (LLVMGetErrorMessage:=dll.LLVMGetErrorMessage).restype, LLVMGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMErrorRef] +except AttributeError: pass + +# void LLVMDisposeErrorMessage(char *ErrMsg) +try: (LLVMDisposeErrorMessage:=dll.LLVMDisposeErrorMessage).restype, LLVMDisposeErrorMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetStringErrorTypeId(void) +try: (LLVMGetStringErrorTypeId:=dll.LLVMGetStringErrorTypeId).restype, LLVMGetStringErrorTypeId.argtypes = LLVMErrorTypeId, [] +except AttributeError: pass + +# LLVMErrorRef LLVMCreateStringError(const char *ErrMsg) +try: (LLVMCreateStringError:=dll.LLVMCreateStringError).restype, LLVMCreateStringError.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass + +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +LLVMJITSymbolGenericFlags = CEnum(ctypes.c_uint32) +LLVMJITSymbolGenericFlagsNone = LLVMJITSymbolGenericFlags.define('LLVMJITSymbolGenericFlagsNone', 0) +LLVMJITSymbolGenericFlagsExported = LLVMJITSymbolGenericFlags.define('LLVMJITSymbolGenericFlagsExported', 1) +LLVMJITSymbolGenericFlagsWeak = LLVMJITSymbolGenericFlags.define('LLVMJITSymbolGenericFlagsWeak', 2) +LLVMJITSymbolGenericFlagsCallable = LLVMJITSymbolGenericFlags.define('LLVMJITSymbolGenericFlagsCallable', 4) +LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly = LLVMJITSymbolGenericFlags.define('LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly', 8) + +LLVMJITSymbolTargetFlags = ctypes.c_ubyte +class struct_LLVMOrcOpaqueObjectLinkingLayer(Struct): pass +LLVMOrcObjectLinkingLayerRef = ctypes.POINTER(struct_LLVMOrcOpaqueObjectLinkingLayer) +# void LLVMOrcExecutionSessionSetErrorReporter(LLVMOrcExecutionSessionRef ES, LLVMOrcErrorReporterFunction ReportError, void *Ctx) +try: (LLVMOrcExecutionSessionSetErrorReporter:=dll.LLVMOrcExecutionSessionSetErrorReporter).restype, LLVMOrcExecutionSessionSetErrorReporter.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcErrorReporterFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolRef LLVMOrcExecutionSessionGetSymbolStringPool(LLVMOrcExecutionSessionRef ES) +try: (LLVMOrcExecutionSessionGetSymbolStringPool:=dll.LLVMOrcExecutionSessionGetSymbolStringPool).restype, LLVMOrcExecutionSessionGetSymbolStringPool.argtypes = LLVMOrcSymbolStringPoolRef, [LLVMOrcExecutionSessionRef] +except AttributeError: pass + +# void LLVMOrcSymbolStringPoolClearDeadEntries(LLVMOrcSymbolStringPoolRef SSP) +try: (LLVMOrcSymbolStringPoolClearDeadEntries:=dll.LLVMOrcSymbolStringPoolClearDeadEntries).restype, LLVMOrcSymbolStringPoolClearDeadEntries.argtypes = None, [LLVMOrcSymbolStringPoolRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcExecutionSessionIntern(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionIntern:=dll.LLVMOrcExecutionSessionIntern).restype, LLVMOrcExecutionSessionIntern.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcExecutionSessionLookup(LLVMOrcExecutionSessionRef ES, LLVMOrcLookupKind K, LLVMOrcCJITDylibSearchOrder SearchOrder, size_t SearchOrderSize, LLVMOrcCLookupSet Symbols, size_t SymbolsSize, LLVMOrcExecutionSessionLookupHandleResultFunction HandleResult, void *Ctx) +try: (LLVMOrcExecutionSessionLookup:=dll.LLVMOrcExecutionSessionLookup).restype, LLVMOrcExecutionSessionLookup.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcLookupKind, LLVMOrcCJITDylibSearchOrder, size_t, LLVMOrcCLookupSet, size_t, LLVMOrcExecutionSessionLookupHandleResultFunction, ctypes.c_void_p] +except AttributeError: pass + +# void LLVMOrcRetainSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcRetainSymbolStringPoolEntry:=dll.LLVMOrcRetainSymbolStringPoolEntry).restype, LLVMOrcRetainSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# void LLVMOrcReleaseSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcReleaseSymbolStringPoolEntry:=dll.LLVMOrcReleaseSymbolStringPoolEntry).restype, LLVMOrcReleaseSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# const char *LLVMOrcSymbolStringPoolEntryStr(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcSymbolStringPoolEntryStr:=dll.LLVMOrcSymbolStringPoolEntryStr).restype, LLVMOrcSymbolStringPoolEntryStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# void LLVMOrcReleaseResourceTracker(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcReleaseResourceTracker:=dll.LLVMOrcReleaseResourceTracker).restype, LLVMOrcReleaseResourceTracker.argtypes = None, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcResourceTrackerTransferTo(LLVMOrcResourceTrackerRef SrcRT, LLVMOrcResourceTrackerRef DstRT) +try: (LLVMOrcResourceTrackerTransferTo:=dll.LLVMOrcResourceTrackerTransferTo).restype, LLVMOrcResourceTrackerTransferTo.argtypes = None, [LLVMOrcResourceTrackerRef, LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcResourceTrackerRemove(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcResourceTrackerRemove:=dll.LLVMOrcResourceTrackerRemove).restype, LLVMOrcResourceTrackerRemove.argtypes = LLVMErrorRef, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcDisposeDefinitionGenerator(LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcDisposeDefinitionGenerator:=dll.LLVMOrcDisposeDefinitionGenerator).restype, LLVMOrcDisposeDefinitionGenerator.argtypes = None, [LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +# void LLVMOrcDisposeMaterializationUnit(LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcDisposeMaterializationUnit:=dll.LLVMOrcDisposeMaterializationUnit).restype, LLVMOrcDisposeMaterializationUnit.argtypes = None, [LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcCreateCustomMaterializationUnit(const char *Name, void *Ctx, LLVMOrcCSymbolFlagsMapPairs Syms, size_t NumSyms, LLVMOrcSymbolStringPoolEntryRef InitSym, LLVMOrcMaterializationUnitMaterializeFunction Materialize, LLVMOrcMaterializationUnitDiscardFunction Discard, LLVMOrcMaterializationUnitDestroyFunction Destroy) +try: (LLVMOrcCreateCustomMaterializationUnit:=dll.LLVMOrcCreateCustomMaterializationUnit).restype, LLVMOrcCreateCustomMaterializationUnit.argtypes = LLVMOrcMaterializationUnitRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, LLVMOrcCSymbolFlagsMapPairs, size_t, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcMaterializationUnitMaterializeFunction, LLVMOrcMaterializationUnitDiscardFunction, LLVMOrcMaterializationUnitDestroyFunction] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcAbsoluteSymbols(LLVMOrcCSymbolMapPairs Syms, size_t NumPairs) +try: (LLVMOrcAbsoluteSymbols:=dll.LLVMOrcAbsoluteSymbols).restype, LLVMOrcAbsoluteSymbols.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcLazyReexports(LLVMOrcLazyCallThroughManagerRef LCTM, LLVMOrcIndirectStubsManagerRef ISM, LLVMOrcJITDylibRef SourceRef, LLVMOrcCSymbolAliasMapPairs CallableAliases, size_t NumPairs) +try: (LLVMOrcLazyReexports:=dll.LLVMOrcLazyReexports).restype, LLVMOrcLazyReexports.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcLazyCallThroughManagerRef, LLVMOrcIndirectStubsManagerRef, LLVMOrcJITDylibRef, LLVMOrcCSymbolAliasMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcDisposeMaterializationResponsibility(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcDisposeMaterializationResponsibility:=dll.LLVMOrcDisposeMaterializationResponsibility).restype, LLVMOrcDisposeMaterializationResponsibility.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcMaterializationResponsibilityGetTargetDylib(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetTargetDylib:=dll.LLVMOrcMaterializationResponsibilityGetTargetDylib).restype, LLVMOrcMaterializationResponsibilityGetTargetDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcExecutionSessionRef LLVMOrcMaterializationResponsibilityGetExecutionSession(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetExecutionSession:=dll.LLVMOrcMaterializationResponsibilityGetExecutionSession).restype, LLVMOrcMaterializationResponsibilityGetExecutionSession.argtypes = LLVMOrcExecutionSessionRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcCSymbolFlagsMapPairs LLVMOrcMaterializationResponsibilityGetSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumPairs) +try: (LLVMOrcMaterializationResponsibilityGetSymbols:=dll.LLVMOrcMaterializationResponsibilityGetSymbols).restype, LLVMOrcMaterializationResponsibilityGetSymbols.argtypes = LLVMOrcCSymbolFlagsMapPairs, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeCSymbolFlagsMap(LLVMOrcCSymbolFlagsMapPairs Pairs) +try: (LLVMOrcDisposeCSymbolFlagsMap:=dll.LLVMOrcDisposeCSymbolFlagsMap).restype, LLVMOrcDisposeCSymbolFlagsMap.argtypes = None, [LLVMOrcCSymbolFlagsMapPairs] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcMaterializationResponsibilityGetInitializerSymbol(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetInitializerSymbol:=dll.LLVMOrcMaterializationResponsibilityGetInitializerSymbol).restype, LLVMOrcMaterializationResponsibilityGetInitializerSymbol.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef *LLVMOrcMaterializationResponsibilityGetRequestedSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumSymbols) +try: (LLVMOrcMaterializationResponsibilityGetRequestedSymbols:=dll.LLVMOrcMaterializationResponsibilityGetRequestedSymbols).restype, LLVMOrcMaterializationResponsibilityGetRequestedSymbols.argtypes = ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeSymbols(LLVMOrcSymbolStringPoolEntryRef *Symbols) +try: (LLVMOrcDisposeSymbols:=dll.LLVMOrcDisposeSymbols).restype, LLVMOrcDisposeSymbols.argtypes = None, [ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyResolved(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolMapPairs Symbols, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityNotifyResolved:=dll.LLVMOrcMaterializationResponsibilityNotifyResolved).restype, LLVMOrcMaterializationResponsibilityNotifyResolved.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyEmitted(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolDependenceGroup *SymbolDepGroups, size_t NumSymbolDepGroups) +try: (LLVMOrcMaterializationResponsibilityNotifyEmitted:=dll.LLVMOrcMaterializationResponsibilityNotifyEmitted).restype, LLVMOrcMaterializationResponsibilityNotifyEmitted.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcCSymbolDependenceGroup), size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDefineMaterializing(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolFlagsMapPairs Pairs, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityDefineMaterializing:=dll.LLVMOrcMaterializationResponsibilityDefineMaterializing).restype, LLVMOrcMaterializationResponsibilityDefineMaterializing.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolFlagsMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcMaterializationResponsibilityFailMaterialization(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityFailMaterialization:=dll.LLVMOrcMaterializationResponsibilityFailMaterialization).restype, LLVMOrcMaterializationResponsibilityFailMaterialization.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityReplace(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcMaterializationResponsibilityReplace:=dll.LLVMOrcMaterializationResponsibilityReplace).restype, LLVMOrcMaterializationResponsibilityReplace.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDelegate(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcSymbolStringPoolEntryRef *Symbols, size_t NumSymbols, LLVMOrcMaterializationResponsibilityRef *Result) +try: (LLVMOrcMaterializationResponsibilityDelegate:=dll.LLVMOrcMaterializationResponsibilityDelegate).restype, LLVMOrcMaterializationResponsibilityDelegate.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), size_t, ctypes.POINTER(LLVMOrcMaterializationResponsibilityRef)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionCreateBareJITDylib(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionCreateBareJITDylib:=dll.LLVMOrcExecutionSessionCreateBareJITDylib).restype, LLVMOrcExecutionSessionCreateBareJITDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcExecutionSessionCreateJITDylib(LLVMOrcExecutionSessionRef ES, LLVMOrcJITDylibRef *Result, const char *Name) +try: (LLVMOrcExecutionSessionCreateJITDylib:=dll.LLVMOrcExecutionSessionCreateJITDylib).restype, LLVMOrcExecutionSessionCreateJITDylib.argtypes = LLVMErrorRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(LLVMOrcJITDylibRef), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionGetJITDylibByName(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionGetJITDylibByName:=dll.LLVMOrcExecutionSessionGetJITDylibByName).restype, LLVMOrcExecutionSessionGetJITDylibByName.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibCreateResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibCreateResourceTracker:=dll.LLVMOrcJITDylibCreateResourceTracker).restype, LLVMOrcJITDylibCreateResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibGetDefaultResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibGetDefaultResourceTracker:=dll.LLVMOrcJITDylibGetDefaultResourceTracker).restype, LLVMOrcJITDylibGetDefaultResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibDefine(LLVMOrcJITDylibRef JD, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcJITDylibDefine:=dll.LLVMOrcJITDylibDefine).restype, LLVMOrcJITDylibDefine.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibClear(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibClear:=dll.LLVMOrcJITDylibClear).restype, LLVMOrcJITDylibClear.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# void LLVMOrcJITDylibAddGenerator(LLVMOrcJITDylibRef JD, LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcJITDylibAddGenerator:=dll.LLVMOrcJITDylibAddGenerator).restype, LLVMOrcJITDylibAddGenerator.argtypes = None, [LLVMOrcJITDylibRef, LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +# LLVMOrcDefinitionGeneratorRef LLVMOrcCreateCustomCAPIDefinitionGenerator(LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction F, void *Ctx, LLVMOrcDisposeCAPIDefinitionGeneratorFunction Dispose) +try: (LLVMOrcCreateCustomCAPIDefinitionGenerator:=dll.LLVMOrcCreateCustomCAPIDefinitionGenerator).restype, LLVMOrcCreateCustomCAPIDefinitionGenerator.argtypes = LLVMOrcDefinitionGeneratorRef, [LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction, ctypes.c_void_p, LLVMOrcDisposeCAPIDefinitionGeneratorFunction] +except AttributeError: pass + +# void LLVMOrcLookupStateContinueLookup(LLVMOrcLookupStateRef S, LLVMErrorRef Err) +try: (LLVMOrcLookupStateContinueLookup:=dll.LLVMOrcLookupStateContinueLookup).restype, LLVMOrcLookupStateContinueLookup.argtypes = None, [LLVMOrcLookupStateRef, LLVMErrorRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess(LLVMOrcDefinitionGeneratorRef *Result, char GlobalPrefx, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, const char *FileName, char GlobalPrefix, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForPath).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.POINTER(ctypes.c_char), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateStaticLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, LLVMOrcObjectLayerRef ObjLayer, const char *FileName, const char *TargetTriple) +try: (LLVMOrcCreateStaticLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateStaticLibrarySearchGeneratorForPath).restype, LLVMOrcCreateStaticLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), LLVMOrcObjectLayerRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcThreadSafeContextRef LLVMOrcCreateNewThreadSafeContext(void) +try: (LLVMOrcCreateNewThreadSafeContext:=dll.LLVMOrcCreateNewThreadSafeContext).restype, LLVMOrcCreateNewThreadSafeContext.argtypes = LLVMOrcThreadSafeContextRef, [] +except AttributeError: pass + +# LLVMContextRef LLVMOrcThreadSafeContextGetContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcThreadSafeContextGetContext:=dll.LLVMOrcThreadSafeContextGetContext).restype, LLVMOrcThreadSafeContextGetContext.argtypes = LLVMContextRef, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcDisposeThreadSafeContext:=dll.LLVMOrcDisposeThreadSafeContext).restype, LLVMOrcDisposeThreadSafeContext.argtypes = None, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# LLVMOrcThreadSafeModuleRef LLVMOrcCreateNewThreadSafeModule(LLVMModuleRef M, LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcCreateNewThreadSafeModule:=dll.LLVMOrcCreateNewThreadSafeModule).restype, LLVMOrcCreateNewThreadSafeModule.argtypes = LLVMOrcThreadSafeModuleRef, [LLVMModuleRef, LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeModule(LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcDisposeThreadSafeModule:=dll.LLVMOrcDisposeThreadSafeModule).restype, LLVMOrcDisposeThreadSafeModule.argtypes = None, [LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcThreadSafeModuleWithModuleDo(LLVMOrcThreadSafeModuleRef TSM, LLVMOrcGenericIRModuleOperationFunction F, void *Ctx) +try: (LLVMOrcThreadSafeModuleWithModuleDo:=dll.LLVMOrcThreadSafeModuleWithModuleDo).restype, LLVMOrcThreadSafeModuleWithModuleDo.argtypes = LLVMErrorRef, [LLVMOrcThreadSafeModuleRef, LLVMOrcGenericIRModuleOperationFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITTargetMachineBuilderDetectHost(LLVMOrcJITTargetMachineBuilderRef *Result) +try: (LLVMOrcJITTargetMachineBuilderDetectHost:=dll.LLVMOrcJITTargetMachineBuilderDetectHost).restype, LLVMOrcJITTargetMachineBuilderDetectHost.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcJITTargetMachineBuilderRef)] +except AttributeError: pass + +# LLVMOrcJITTargetMachineBuilderRef LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine(LLVMTargetMachineRef TM) +try: (LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine:=dll.LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine).restype, LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.argtypes = LLVMOrcJITTargetMachineBuilderRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMOrcDisposeJITTargetMachineBuilder(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcDisposeJITTargetMachineBuilder:=dll.LLVMOrcDisposeJITTargetMachineBuilder).restype, LLVMOrcDisposeJITTargetMachineBuilder.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# char *LLVMOrcJITTargetMachineBuilderGetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcJITTargetMachineBuilderGetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderGetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderGetTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# void LLVMOrcJITTargetMachineBuilderSetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB, const char *TargetTriple) +try: (LLVMOrcJITTargetMachineBuilderSetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderSetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderSetTargetTriple.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFile(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcJITDylibRef JD, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFile:=dll.LLVMOrcObjectLayerAddObjectFile).restype, LLVMOrcObjectLayerAddObjectFile.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFileWithRT(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcResourceTrackerRef RT, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFileWithRT:=dll.LLVMOrcObjectLayerAddObjectFileWithRT).restype, LLVMOrcObjectLayerAddObjectFileWithRT.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcObjectLayerEmit(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcMaterializationResponsibilityRef R, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerEmit:=dll.LLVMOrcObjectLayerEmit).restype, LLVMOrcObjectLayerEmit.argtypes = None, [LLVMOrcObjectLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcDisposeObjectLayer(LLVMOrcObjectLayerRef ObjLayer) +try: (LLVMOrcDisposeObjectLayer:=dll.LLVMOrcDisposeObjectLayer).restype, LLVMOrcDisposeObjectLayer.argtypes = None, [LLVMOrcObjectLayerRef] +except AttributeError: pass + +# void LLVMOrcIRTransformLayerEmit(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcIRTransformLayerEmit:=dll.LLVMOrcIRTransformLayerEmit).restype, LLVMOrcIRTransformLayerEmit.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# void LLVMOrcIRTransformLayerSetTransform(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcIRTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcIRTransformLayerSetTransform:=dll.LLVMOrcIRTransformLayerSetTransform).restype, LLVMOrcIRTransformLayerSetTransform.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcIRTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +# void LLVMOrcObjectTransformLayerSetTransform(LLVMOrcObjectTransformLayerRef ObjTransformLayer, LLVMOrcObjectTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcObjectTransformLayerSetTransform:=dll.LLVMOrcObjectTransformLayerSetTransform).restype, LLVMOrcObjectTransformLayerSetTransform.argtypes = None, [LLVMOrcObjectTransformLayerRef, LLVMOrcObjectTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMOrcIndirectStubsManagerRef LLVMOrcCreateLocalIndirectStubsManager(const char *TargetTriple) +try: (LLVMOrcCreateLocalIndirectStubsManager:=dll.LLVMOrcCreateLocalIndirectStubsManager).restype, LLVMOrcCreateLocalIndirectStubsManager.argtypes = LLVMOrcIndirectStubsManagerRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcDisposeIndirectStubsManager(LLVMOrcIndirectStubsManagerRef ISM) +try: (LLVMOrcDisposeIndirectStubsManager:=dll.LLVMOrcDisposeIndirectStubsManager).restype, LLVMOrcDisposeIndirectStubsManager.argtypes = None, [LLVMOrcIndirectStubsManagerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateLocalLazyCallThroughManager(const char *TargetTriple, LLVMOrcExecutionSessionRef ES, LLVMOrcJITTargetAddress ErrorHandlerAddr, LLVMOrcLazyCallThroughManagerRef *LCTM) +try: (LLVMOrcCreateLocalLazyCallThroughManager:=dll.LLVMOrcCreateLocalLazyCallThroughManager).restype, LLVMOrcCreateLocalLazyCallThroughManager.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char), LLVMOrcExecutionSessionRef, LLVMOrcJITTargetAddress, ctypes.POINTER(LLVMOrcLazyCallThroughManagerRef)] +except AttributeError: pass + +# void LLVMOrcDisposeLazyCallThroughManager(LLVMOrcLazyCallThroughManagerRef LCTM) +try: (LLVMOrcDisposeLazyCallThroughManager:=dll.LLVMOrcDisposeLazyCallThroughManager).restype, LLVMOrcDisposeLazyCallThroughManager.argtypes = None, [LLVMOrcLazyCallThroughManagerRef] +except AttributeError: pass + +# LLVMOrcDumpObjectsRef LLVMOrcCreateDumpObjects(const char *DumpDir, const char *IdentifierOverride) +try: (LLVMOrcCreateDumpObjects:=dll.LLVMOrcCreateDumpObjects).restype, LLVMOrcCreateDumpObjects.argtypes = LLVMOrcDumpObjectsRef, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcDisposeDumpObjects(LLVMOrcDumpObjectsRef DumpObjects) +try: (LLVMOrcDisposeDumpObjects:=dll.LLVMOrcDisposeDumpObjects).restype, LLVMOrcDisposeDumpObjects.argtypes = None, [LLVMOrcDumpObjectsRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcDumpObjects_CallOperator(LLVMOrcDumpObjectsRef DumpObjects, LLVMMemoryBufferRef *ObjBuffer) +try: (LLVMOrcDumpObjects_CallOperator:=dll.LLVMOrcDumpObjects_CallOperator).restype, LLVMOrcDumpObjects_CallOperator.argtypes = LLVMErrorRef, [LLVMOrcDumpObjectsRef, ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetErrorTypeId(LLVMErrorRef Err) +try: (LLVMGetErrorTypeId:=dll.LLVMGetErrorTypeId).restype, LLVMGetErrorTypeId.argtypes = LLVMErrorTypeId, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMConsumeError(LLVMErrorRef Err) +try: (LLVMConsumeError:=dll.LLVMConsumeError).restype, LLVMConsumeError.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMCantFail(LLVMErrorRef Err) +try: (LLVMCantFail:=dll.LLVMCantFail).restype, LLVMCantFail.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# char *LLVMGetErrorMessage(LLVMErrorRef Err) +try: (LLVMGetErrorMessage:=dll.LLVMGetErrorMessage).restype, LLVMGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMErrorRef] +except AttributeError: pass + +# void LLVMDisposeErrorMessage(char *ErrMsg) +try: (LLVMDisposeErrorMessage:=dll.LLVMDisposeErrorMessage).restype, LLVMDisposeErrorMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetStringErrorTypeId(void) +try: (LLVMGetStringErrorTypeId:=dll.LLVMGetStringErrorTypeId).restype, LLVMGetStringErrorTypeId.argtypes = LLVMErrorTypeId, [] +except AttributeError: pass + +# LLVMErrorRef LLVMCreateStringError(const char *ErrMsg) +try: (LLVMCreateStringError:=dll.LLVMCreateStringError).restype, LLVMCreateStringError.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass + +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +# void LLVMLinkInMCJIT(void) +try: (LLVMLinkInMCJIT:=dll.LLVMLinkInMCJIT).restype, LLVMLinkInMCJIT.argtypes = None, [] +except AttributeError: pass + +# void LLVMLinkInInterpreter(void) +try: (LLVMLinkInInterpreter:=dll.LLVMLinkInInterpreter).restype, LLVMLinkInInterpreter.argtypes = None, [] +except AttributeError: pass + +# LLVMGenericValueRef LLVMCreateGenericValueOfInt(LLVMTypeRef Ty, unsigned long long N, LLVMBool IsSigned) +try: (LLVMCreateGenericValueOfInt:=dll.LLVMCreateGenericValueOfInt).restype, LLVMCreateGenericValueOfInt.argtypes = LLVMGenericValueRef, [LLVMTypeRef, ctypes.c_uint64, LLVMBool] +except AttributeError: pass + +# LLVMGenericValueRef LLVMCreateGenericValueOfPointer(void *P) +try: (LLVMCreateGenericValueOfPointer:=dll.LLVMCreateGenericValueOfPointer).restype, LLVMCreateGenericValueOfPointer.argtypes = LLVMGenericValueRef, [ctypes.c_void_p] +except AttributeError: pass + +# LLVMGenericValueRef LLVMCreateGenericValueOfFloat(LLVMTypeRef Ty, double N) +try: (LLVMCreateGenericValueOfFloat:=dll.LLVMCreateGenericValueOfFloat).restype, LLVMCreateGenericValueOfFloat.argtypes = LLVMGenericValueRef, [LLVMTypeRef, ctypes.c_double] +except AttributeError: pass + +# unsigned int LLVMGenericValueIntWidth(LLVMGenericValueRef GenValRef) +try: (LLVMGenericValueIntWidth:=dll.LLVMGenericValueIntWidth).restype, LLVMGenericValueIntWidth.argtypes = ctypes.c_uint32, [LLVMGenericValueRef] +except AttributeError: pass + +# unsigned long long LLVMGenericValueToInt(LLVMGenericValueRef GenVal, LLVMBool IsSigned) +try: (LLVMGenericValueToInt:=dll.LLVMGenericValueToInt).restype, LLVMGenericValueToInt.argtypes = ctypes.c_uint64, [LLVMGenericValueRef, LLVMBool] +except AttributeError: pass + +# void *LLVMGenericValueToPointer(LLVMGenericValueRef GenVal) +try: (LLVMGenericValueToPointer:=dll.LLVMGenericValueToPointer).restype, LLVMGenericValueToPointer.argtypes = ctypes.c_void_p, [LLVMGenericValueRef] +except AttributeError: pass + +# double LLVMGenericValueToFloat(LLVMTypeRef TyRef, LLVMGenericValueRef GenVal) +try: (LLVMGenericValueToFloat:=dll.LLVMGenericValueToFloat).restype, LLVMGenericValueToFloat.argtypes = ctypes.c_double, [LLVMTypeRef, LLVMGenericValueRef] +except AttributeError: pass + +# void LLVMDisposeGenericValue(LLVMGenericValueRef GenVal) +try: (LLVMDisposeGenericValue:=dll.LLVMDisposeGenericValue).restype, LLVMDisposeGenericValue.argtypes = None, [LLVMGenericValueRef] +except AttributeError: pass + +# LLVMBool LLVMCreateExecutionEngineForModule(LLVMExecutionEngineRef *OutEE, LLVMModuleRef M, char **OutError) +try: (LLVMCreateExecutionEngineForModule:=dll.LLVMCreateExecutionEngineForModule).restype, LLVMCreateExecutionEngineForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMCreateInterpreterForModule(LLVMExecutionEngineRef *OutInterp, LLVMModuleRef M, char **OutError) +try: (LLVMCreateInterpreterForModule:=dll.LLVMCreateInterpreterForModule).restype, LLVMCreateInterpreterForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMCreateJITCompilerForModule(LLVMExecutionEngineRef *OutJIT, LLVMModuleRef M, unsigned int OptLevel, char **OutError) +try: (LLVMCreateJITCompilerForModule:=dll.LLVMCreateJITCompilerForModule).restype, LLVMCreateJITCompilerForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# void LLVMInitializeMCJITCompilerOptions(struct LLVMMCJITCompilerOptions *Options, size_t SizeOfOptions) +try: (LLVMInitializeMCJITCompilerOptions:=dll.LLVMInitializeMCJITCompilerOptions).restype, LLVMInitializeMCJITCompilerOptions.argtypes = None, [ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t] +except AttributeError: pass + +# LLVMBool LLVMCreateMCJITCompilerForModule(LLVMExecutionEngineRef *OutJIT, LLVMModuleRef M, struct LLVMMCJITCompilerOptions *Options, size_t SizeOfOptions, char **OutError) +try: (LLVMCreateMCJITCompilerForModule:=dll.LLVMCreateMCJITCompilerForModule).restype, LLVMCreateMCJITCompilerForModule.argtypes = LLVMBool, [ctypes.POINTER(LLVMExecutionEngineRef), LLVMModuleRef, ctypes.POINTER(struct_LLVMMCJITCompilerOptions), size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# void LLVMDisposeExecutionEngine(LLVMExecutionEngineRef EE) +try: (LLVMDisposeExecutionEngine:=dll.LLVMDisposeExecutionEngine).restype, LLVMDisposeExecutionEngine.argtypes = None, [LLVMExecutionEngineRef] +except AttributeError: pass + +# void LLVMRunStaticConstructors(LLVMExecutionEngineRef EE) +try: (LLVMRunStaticConstructors:=dll.LLVMRunStaticConstructors).restype, LLVMRunStaticConstructors.argtypes = None, [LLVMExecutionEngineRef] +except AttributeError: pass + +# void LLVMRunStaticDestructors(LLVMExecutionEngineRef EE) +try: (LLVMRunStaticDestructors:=dll.LLVMRunStaticDestructors).restype, LLVMRunStaticDestructors.argtypes = None, [LLVMExecutionEngineRef] +except AttributeError: pass + +# int LLVMRunFunctionAsMain(LLVMExecutionEngineRef EE, LLVMValueRef F, unsigned int ArgC, const char *const *ArgV, const char *const *EnvP) +try: (LLVMRunFunctionAsMain:=dll.LLVMRunFunctionAsMain).restype, LLVMRunFunctionAsMain.argtypes = ctypes.c_int32, [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMGenericValueRef LLVMRunFunction(LLVMExecutionEngineRef EE, LLVMValueRef F, unsigned int NumArgs, LLVMGenericValueRef *Args) +try: (LLVMRunFunction:=dll.LLVMRunFunction).restype, LLVMRunFunction.argtypes = LLVMGenericValueRef, [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(LLVMGenericValueRef)] +except AttributeError: pass + +# void LLVMFreeMachineCodeForFunction(LLVMExecutionEngineRef EE, LLVMValueRef F) +try: (LLVMFreeMachineCodeForFunction:=dll.LLVMFreeMachineCodeForFunction).restype, LLVMFreeMachineCodeForFunction.argtypes = None, [LLVMExecutionEngineRef, LLVMValueRef] +except AttributeError: pass + +# void LLVMAddModule(LLVMExecutionEngineRef EE, LLVMModuleRef M) +try: (LLVMAddModule:=dll.LLVMAddModule).restype, LLVMAddModule.argtypes = None, [LLVMExecutionEngineRef, LLVMModuleRef] +except AttributeError: pass + +# LLVMBool LLVMRemoveModule(LLVMExecutionEngineRef EE, LLVMModuleRef M, LLVMModuleRef *OutMod, char **OutError) +try: (LLVMRemoveModule:=dll.LLVMRemoveModule).restype, LLVMRemoveModule.argtypes = LLVMBool, [LLVMExecutionEngineRef, LLVMModuleRef, ctypes.POINTER(LLVMModuleRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMFindFunction(LLVMExecutionEngineRef EE, const char *Name, LLVMValueRef *OutFn) +try: (LLVMFindFunction:=dll.LLVMFindFunction).restype, LLVMFindFunction.argtypes = LLVMBool, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMValueRef)] +except AttributeError: pass + +# void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE, LLVMValueRef Fn) +try: (LLVMRecompileAndRelinkFunction:=dll.LLVMRecompileAndRelinkFunction).restype, LLVMRecompileAndRelinkFunction.argtypes = ctypes.c_void_p, [LLVMExecutionEngineRef, LLVMValueRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef EE) +try: (LLVMGetExecutionEngineTargetData:=dll.LLVMGetExecutionEngineTargetData).restype, LLVMGetExecutionEngineTargetData.argtypes = LLVMTargetDataRef, [LLVMExecutionEngineRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMGetExecutionEngineTargetMachine(LLVMExecutionEngineRef EE) +try: (LLVMGetExecutionEngineTargetMachine:=dll.LLVMGetExecutionEngineTargetMachine).restype, LLVMGetExecutionEngineTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMExecutionEngineRef] +except AttributeError: pass + +# void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global, void *Addr) +try: (LLVMAddGlobalMapping:=dll.LLVMAddGlobalMapping).restype, LLVMAddGlobalMapping.argtypes = None, [LLVMExecutionEngineRef, LLVMValueRef, ctypes.c_void_p] +except AttributeError: pass + +# void *LLVMGetPointerToGlobal(LLVMExecutionEngineRef EE, LLVMValueRef Global) +try: (LLVMGetPointerToGlobal:=dll.LLVMGetPointerToGlobal).restype, LLVMGetPointerToGlobal.argtypes = ctypes.c_void_p, [LLVMExecutionEngineRef, LLVMValueRef] +except AttributeError: pass + +# uint64_t LLVMGetGlobalValueAddress(LLVMExecutionEngineRef EE, const char *Name) +try: (LLVMGetGlobalValueAddress:=dll.LLVMGetGlobalValueAddress).restype, LLVMGetGlobalValueAddress.argtypes = uint64_t, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# uint64_t LLVMGetFunctionAddress(LLVMExecutionEngineRef EE, const char *Name) +try: (LLVMGetFunctionAddress:=dll.LLVMGetFunctionAddress).restype, LLVMGetFunctionAddress.argtypes = uint64_t, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMExecutionEngineGetErrMsg(LLVMExecutionEngineRef EE, char **OutError) +try: (LLVMExecutionEngineGetErrMsg:=dll.LLVMExecutionEngineGetErrMsg).restype, LLVMExecutionEngineGetErrMsg.argtypes = LLVMBool, [LLVMExecutionEngineRef, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMMCJITMemoryManagerRef LLVMCreateSimpleMCJITMemoryManager(void *Opaque, LLVMMemoryManagerAllocateCodeSectionCallback AllocateCodeSection, LLVMMemoryManagerAllocateDataSectionCallback AllocateDataSection, LLVMMemoryManagerFinalizeMemoryCallback FinalizeMemory, LLVMMemoryManagerDestroyCallback Destroy) +try: (LLVMCreateSimpleMCJITMemoryManager:=dll.LLVMCreateSimpleMCJITMemoryManager).restype, LLVMCreateSimpleMCJITMemoryManager.argtypes = LLVMMCJITMemoryManagerRef, [ctypes.c_void_p, LLVMMemoryManagerAllocateCodeSectionCallback, LLVMMemoryManagerAllocateDataSectionCallback, LLVMMemoryManagerFinalizeMemoryCallback, LLVMMemoryManagerDestroyCallback] +except AttributeError: pass + +# void LLVMDisposeMCJITMemoryManager(LLVMMCJITMemoryManagerRef MM) +try: (LLVMDisposeMCJITMemoryManager:=dll.LLVMDisposeMCJITMemoryManager).restype, LLVMDisposeMCJITMemoryManager.argtypes = None, [LLVMMCJITMemoryManagerRef] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreateGDBRegistrationListener(void) +try: (LLVMCreateGDBRegistrationListener:=dll.LLVMCreateGDBRegistrationListener).restype, LLVMCreateGDBRegistrationListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreateIntelJITEventListener(void) +try: (LLVMCreateIntelJITEventListener:=dll.LLVMCreateIntelJITEventListener).restype, LLVMCreateIntelJITEventListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreateOProfileJITEventListener(void) +try: (LLVMCreateOProfileJITEventListener:=dll.LLVMCreateOProfileJITEventListener).restype, LLVMCreateOProfileJITEventListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# LLVMJITEventListenerRef LLVMCreatePerfJITEventListener(void) +try: (LLVMCreatePerfJITEventListener:=dll.LLVMCreatePerfJITEventListener).restype, LLVMCreatePerfJITEventListener.argtypes = LLVMJITEventListenerRef, [] +except AttributeError: pass + +# void LLVMOrcExecutionSessionSetErrorReporter(LLVMOrcExecutionSessionRef ES, LLVMOrcErrorReporterFunction ReportError, void *Ctx) +try: (LLVMOrcExecutionSessionSetErrorReporter:=dll.LLVMOrcExecutionSessionSetErrorReporter).restype, LLVMOrcExecutionSessionSetErrorReporter.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcErrorReporterFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolRef LLVMOrcExecutionSessionGetSymbolStringPool(LLVMOrcExecutionSessionRef ES) +try: (LLVMOrcExecutionSessionGetSymbolStringPool:=dll.LLVMOrcExecutionSessionGetSymbolStringPool).restype, LLVMOrcExecutionSessionGetSymbolStringPool.argtypes = LLVMOrcSymbolStringPoolRef, [LLVMOrcExecutionSessionRef] +except AttributeError: pass + +# void LLVMOrcSymbolStringPoolClearDeadEntries(LLVMOrcSymbolStringPoolRef SSP) +try: (LLVMOrcSymbolStringPoolClearDeadEntries:=dll.LLVMOrcSymbolStringPoolClearDeadEntries).restype, LLVMOrcSymbolStringPoolClearDeadEntries.argtypes = None, [LLVMOrcSymbolStringPoolRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcExecutionSessionIntern(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionIntern:=dll.LLVMOrcExecutionSessionIntern).restype, LLVMOrcExecutionSessionIntern.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcExecutionSessionLookup(LLVMOrcExecutionSessionRef ES, LLVMOrcLookupKind K, LLVMOrcCJITDylibSearchOrder SearchOrder, size_t SearchOrderSize, LLVMOrcCLookupSet Symbols, size_t SymbolsSize, LLVMOrcExecutionSessionLookupHandleResultFunction HandleResult, void *Ctx) +try: (LLVMOrcExecutionSessionLookup:=dll.LLVMOrcExecutionSessionLookup).restype, LLVMOrcExecutionSessionLookup.argtypes = None, [LLVMOrcExecutionSessionRef, LLVMOrcLookupKind, LLVMOrcCJITDylibSearchOrder, size_t, LLVMOrcCLookupSet, size_t, LLVMOrcExecutionSessionLookupHandleResultFunction, ctypes.c_void_p] +except AttributeError: pass + +# void LLVMOrcRetainSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcRetainSymbolStringPoolEntry:=dll.LLVMOrcRetainSymbolStringPoolEntry).restype, LLVMOrcRetainSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# void LLVMOrcReleaseSymbolStringPoolEntry(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcReleaseSymbolStringPoolEntry:=dll.LLVMOrcReleaseSymbolStringPoolEntry).restype, LLVMOrcReleaseSymbolStringPoolEntry.argtypes = None, [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# const char *LLVMOrcSymbolStringPoolEntryStr(LLVMOrcSymbolStringPoolEntryRef S) +try: (LLVMOrcSymbolStringPoolEntryStr:=dll.LLVMOrcSymbolStringPoolEntryStr).restype, LLVMOrcSymbolStringPoolEntryStr.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcSymbolStringPoolEntryRef] +except AttributeError: pass + +# void LLVMOrcReleaseResourceTracker(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcReleaseResourceTracker:=dll.LLVMOrcReleaseResourceTracker).restype, LLVMOrcReleaseResourceTracker.argtypes = None, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcResourceTrackerTransferTo(LLVMOrcResourceTrackerRef SrcRT, LLVMOrcResourceTrackerRef DstRT) +try: (LLVMOrcResourceTrackerTransferTo:=dll.LLVMOrcResourceTrackerTransferTo).restype, LLVMOrcResourceTrackerTransferTo.argtypes = None, [LLVMOrcResourceTrackerRef, LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcResourceTrackerRemove(LLVMOrcResourceTrackerRef RT) +try: (LLVMOrcResourceTrackerRemove:=dll.LLVMOrcResourceTrackerRemove).restype, LLVMOrcResourceTrackerRemove.argtypes = LLVMErrorRef, [LLVMOrcResourceTrackerRef] +except AttributeError: pass + +# void LLVMOrcDisposeDefinitionGenerator(LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcDisposeDefinitionGenerator:=dll.LLVMOrcDisposeDefinitionGenerator).restype, LLVMOrcDisposeDefinitionGenerator.argtypes = None, [LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +# void LLVMOrcDisposeMaterializationUnit(LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcDisposeMaterializationUnit:=dll.LLVMOrcDisposeMaterializationUnit).restype, LLVMOrcDisposeMaterializationUnit.argtypes = None, [LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcCreateCustomMaterializationUnit(const char *Name, void *Ctx, LLVMOrcCSymbolFlagsMapPairs Syms, size_t NumSyms, LLVMOrcSymbolStringPoolEntryRef InitSym, LLVMOrcMaterializationUnitMaterializeFunction Materialize, LLVMOrcMaterializationUnitDiscardFunction Discard, LLVMOrcMaterializationUnitDestroyFunction Destroy) +try: (LLVMOrcCreateCustomMaterializationUnit:=dll.LLVMOrcCreateCustomMaterializationUnit).restype, LLVMOrcCreateCustomMaterializationUnit.argtypes = LLVMOrcMaterializationUnitRef, [ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, LLVMOrcCSymbolFlagsMapPairs, size_t, LLVMOrcSymbolStringPoolEntryRef, LLVMOrcMaterializationUnitMaterializeFunction, LLVMOrcMaterializationUnitDiscardFunction, LLVMOrcMaterializationUnitDestroyFunction] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcAbsoluteSymbols(LLVMOrcCSymbolMapPairs Syms, size_t NumPairs) +try: (LLVMOrcAbsoluteSymbols:=dll.LLVMOrcAbsoluteSymbols).restype, LLVMOrcAbsoluteSymbols.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +# LLVMOrcMaterializationUnitRef LLVMOrcLazyReexports(LLVMOrcLazyCallThroughManagerRef LCTM, LLVMOrcIndirectStubsManagerRef ISM, LLVMOrcJITDylibRef SourceRef, LLVMOrcCSymbolAliasMapPairs CallableAliases, size_t NumPairs) +try: (LLVMOrcLazyReexports:=dll.LLVMOrcLazyReexports).restype, LLVMOrcLazyReexports.argtypes = LLVMOrcMaterializationUnitRef, [LLVMOrcLazyCallThroughManagerRef, LLVMOrcIndirectStubsManagerRef, LLVMOrcJITDylibRef, LLVMOrcCSymbolAliasMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcDisposeMaterializationResponsibility(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcDisposeMaterializationResponsibility:=dll.LLVMOrcDisposeMaterializationResponsibility).restype, LLVMOrcDisposeMaterializationResponsibility.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcMaterializationResponsibilityGetTargetDylib(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetTargetDylib:=dll.LLVMOrcMaterializationResponsibilityGetTargetDylib).restype, LLVMOrcMaterializationResponsibilityGetTargetDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcExecutionSessionRef LLVMOrcMaterializationResponsibilityGetExecutionSession(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetExecutionSession:=dll.LLVMOrcMaterializationResponsibilityGetExecutionSession).restype, LLVMOrcMaterializationResponsibilityGetExecutionSession.argtypes = LLVMOrcExecutionSessionRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcCSymbolFlagsMapPairs LLVMOrcMaterializationResponsibilityGetSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumPairs) +try: (LLVMOrcMaterializationResponsibilityGetSymbols:=dll.LLVMOrcMaterializationResponsibilityGetSymbols).restype, LLVMOrcMaterializationResponsibilityGetSymbols.argtypes = LLVMOrcCSymbolFlagsMapPairs, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeCSymbolFlagsMap(LLVMOrcCSymbolFlagsMapPairs Pairs) +try: (LLVMOrcDisposeCSymbolFlagsMap:=dll.LLVMOrcDisposeCSymbolFlagsMap).restype, LLVMOrcDisposeCSymbolFlagsMap.argtypes = None, [LLVMOrcCSymbolFlagsMapPairs] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef LLVMOrcMaterializationResponsibilityGetInitializerSymbol(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityGetInitializerSymbol:=dll.LLVMOrcMaterializationResponsibilityGetInitializerSymbol).restype, LLVMOrcMaterializationResponsibilityGetInitializerSymbol.argtypes = LLVMOrcSymbolStringPoolEntryRef, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMOrcSymbolStringPoolEntryRef *LLVMOrcMaterializationResponsibilityGetRequestedSymbols(LLVMOrcMaterializationResponsibilityRef MR, size_t *NumSymbols) +try: (LLVMOrcMaterializationResponsibilityGetRequestedSymbols:=dll.LLVMOrcMaterializationResponsibilityGetRequestedSymbols).restype, LLVMOrcMaterializationResponsibilityGetRequestedSymbols.argtypes = ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(size_t)] +except AttributeError: pass + +# void LLVMOrcDisposeSymbols(LLVMOrcSymbolStringPoolEntryRef *Symbols) +try: (LLVMOrcDisposeSymbols:=dll.LLVMOrcDisposeSymbols).restype, LLVMOrcDisposeSymbols.argtypes = None, [ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyResolved(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolMapPairs Symbols, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityNotifyResolved:=dll.LLVMOrcMaterializationResponsibilityNotifyResolved).restype, LLVMOrcMaterializationResponsibilityNotifyResolved.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolMapPairs, size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityNotifyEmitted(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolDependenceGroup *SymbolDepGroups, size_t NumSymbolDepGroups) +try: (LLVMOrcMaterializationResponsibilityNotifyEmitted:=dll.LLVMOrcMaterializationResponsibilityNotifyEmitted).restype, LLVMOrcMaterializationResponsibilityNotifyEmitted.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcCSymbolDependenceGroup), size_t] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDefineMaterializing(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcCSymbolFlagsMapPairs Pairs, size_t NumPairs) +try: (LLVMOrcMaterializationResponsibilityDefineMaterializing:=dll.LLVMOrcMaterializationResponsibilityDefineMaterializing).restype, LLVMOrcMaterializationResponsibilityDefineMaterializing.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcCSymbolFlagsMapPairs, size_t] +except AttributeError: pass + +# void LLVMOrcMaterializationResponsibilityFailMaterialization(LLVMOrcMaterializationResponsibilityRef MR) +try: (LLVMOrcMaterializationResponsibilityFailMaterialization:=dll.LLVMOrcMaterializationResponsibilityFailMaterialization).restype, LLVMOrcMaterializationResponsibilityFailMaterialization.argtypes = None, [LLVMOrcMaterializationResponsibilityRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityReplace(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcMaterializationResponsibilityReplace:=dll.LLVMOrcMaterializationResponsibilityReplace).restype, LLVMOrcMaterializationResponsibilityReplace.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcMaterializationResponsibilityDelegate(LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcSymbolStringPoolEntryRef *Symbols, size_t NumSymbols, LLVMOrcMaterializationResponsibilityRef *Result) +try: (LLVMOrcMaterializationResponsibilityDelegate:=dll.LLVMOrcMaterializationResponsibilityDelegate).restype, LLVMOrcMaterializationResponsibilityDelegate.argtypes = LLVMErrorRef, [LLVMOrcMaterializationResponsibilityRef, ctypes.POINTER(LLVMOrcSymbolStringPoolEntryRef), size_t, ctypes.POINTER(LLVMOrcMaterializationResponsibilityRef)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionCreateBareJITDylib(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionCreateBareJITDylib:=dll.LLVMOrcExecutionSessionCreateBareJITDylib).restype, LLVMOrcExecutionSessionCreateBareJITDylib.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcExecutionSessionCreateJITDylib(LLVMOrcExecutionSessionRef ES, LLVMOrcJITDylibRef *Result, const char *Name) +try: (LLVMOrcExecutionSessionCreateJITDylib:=dll.LLVMOrcExecutionSessionCreateJITDylib).restype, LLVMOrcExecutionSessionCreateJITDylib.argtypes = LLVMErrorRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(LLVMOrcJITDylibRef), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcJITDylibRef LLVMOrcExecutionSessionGetJITDylibByName(LLVMOrcExecutionSessionRef ES, const char *Name) +try: (LLVMOrcExecutionSessionGetJITDylibByName:=dll.LLVMOrcExecutionSessionGetJITDylibByName).restype, LLVMOrcExecutionSessionGetJITDylibByName.argtypes = LLVMOrcJITDylibRef, [LLVMOrcExecutionSessionRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibCreateResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibCreateResourceTracker:=dll.LLVMOrcJITDylibCreateResourceTracker).restype, LLVMOrcJITDylibCreateResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMOrcResourceTrackerRef LLVMOrcJITDylibGetDefaultResourceTracker(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibGetDefaultResourceTracker:=dll.LLVMOrcJITDylibGetDefaultResourceTracker).restype, LLVMOrcJITDylibGetDefaultResourceTracker.argtypes = LLVMOrcResourceTrackerRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibDefine(LLVMOrcJITDylibRef JD, LLVMOrcMaterializationUnitRef MU) +try: (LLVMOrcJITDylibDefine:=dll.LLVMOrcJITDylibDefine).restype, LLVMOrcJITDylibDefine.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef, LLVMOrcMaterializationUnitRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITDylibClear(LLVMOrcJITDylibRef JD) +try: (LLVMOrcJITDylibClear:=dll.LLVMOrcJITDylibClear).restype, LLVMOrcJITDylibClear.argtypes = LLVMErrorRef, [LLVMOrcJITDylibRef] +except AttributeError: pass + +# void LLVMOrcJITDylibAddGenerator(LLVMOrcJITDylibRef JD, LLVMOrcDefinitionGeneratorRef DG) +try: (LLVMOrcJITDylibAddGenerator:=dll.LLVMOrcJITDylibAddGenerator).restype, LLVMOrcJITDylibAddGenerator.argtypes = None, [LLVMOrcJITDylibRef, LLVMOrcDefinitionGeneratorRef] +except AttributeError: pass + +# LLVMOrcDefinitionGeneratorRef LLVMOrcCreateCustomCAPIDefinitionGenerator(LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction F, void *Ctx, LLVMOrcDisposeCAPIDefinitionGeneratorFunction Dispose) +try: (LLVMOrcCreateCustomCAPIDefinitionGenerator:=dll.LLVMOrcCreateCustomCAPIDefinitionGenerator).restype, LLVMOrcCreateCustomCAPIDefinitionGenerator.argtypes = LLVMOrcDefinitionGeneratorRef, [LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction, ctypes.c_void_p, LLVMOrcDisposeCAPIDefinitionGeneratorFunction] +except AttributeError: pass + +# void LLVMOrcLookupStateContinueLookup(LLVMOrcLookupStateRef S, LLVMErrorRef Err) +try: (LLVMOrcLookupStateContinueLookup:=dll.LLVMOrcLookupStateContinueLookup).restype, LLVMOrcLookupStateContinueLookup.argtypes = None, [LLVMOrcLookupStateRef, LLVMErrorRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess(LLVMOrcDefinitionGeneratorRef *Result, char GlobalPrefx, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateDynamicLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, const char *FileName, char GlobalPrefix, LLVMOrcSymbolPredicate Filter, void *FilterCtx) +try: (LLVMOrcCreateDynamicLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateDynamicLibrarySearchGeneratorForPath).restype, LLVMOrcCreateDynamicLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), ctypes.POINTER(ctypes.c_char), ctypes.c_char, LLVMOrcSymbolPredicate, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateStaticLibrarySearchGeneratorForPath(LLVMOrcDefinitionGeneratorRef *Result, LLVMOrcObjectLayerRef ObjLayer, const char *FileName, const char *TargetTriple) +try: (LLVMOrcCreateStaticLibrarySearchGeneratorForPath:=dll.LLVMOrcCreateStaticLibrarySearchGeneratorForPath).restype, LLVMOrcCreateStaticLibrarySearchGeneratorForPath.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcDefinitionGeneratorRef), LLVMOrcObjectLayerRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMOrcThreadSafeContextRef LLVMOrcCreateNewThreadSafeContext(void) +try: (LLVMOrcCreateNewThreadSafeContext:=dll.LLVMOrcCreateNewThreadSafeContext).restype, LLVMOrcCreateNewThreadSafeContext.argtypes = LLVMOrcThreadSafeContextRef, [] +except AttributeError: pass + +# LLVMContextRef LLVMOrcThreadSafeContextGetContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcThreadSafeContextGetContext:=dll.LLVMOrcThreadSafeContextGetContext).restype, LLVMOrcThreadSafeContextGetContext.argtypes = LLVMContextRef, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeContext(LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcDisposeThreadSafeContext:=dll.LLVMOrcDisposeThreadSafeContext).restype, LLVMOrcDisposeThreadSafeContext.argtypes = None, [LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# LLVMOrcThreadSafeModuleRef LLVMOrcCreateNewThreadSafeModule(LLVMModuleRef M, LLVMOrcThreadSafeContextRef TSCtx) +try: (LLVMOrcCreateNewThreadSafeModule:=dll.LLVMOrcCreateNewThreadSafeModule).restype, LLVMOrcCreateNewThreadSafeModule.argtypes = LLVMOrcThreadSafeModuleRef, [LLVMModuleRef, LLVMOrcThreadSafeContextRef] +except AttributeError: pass + +# void LLVMOrcDisposeThreadSafeModule(LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcDisposeThreadSafeModule:=dll.LLVMOrcDisposeThreadSafeModule).restype, LLVMOrcDisposeThreadSafeModule.argtypes = None, [LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcThreadSafeModuleWithModuleDo(LLVMOrcThreadSafeModuleRef TSM, LLVMOrcGenericIRModuleOperationFunction F, void *Ctx) +try: (LLVMOrcThreadSafeModuleWithModuleDo:=dll.LLVMOrcThreadSafeModuleWithModuleDo).restype, LLVMOrcThreadSafeModuleWithModuleDo.argtypes = LLVMErrorRef, [LLVMOrcThreadSafeModuleRef, LLVMOrcGenericIRModuleOperationFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcJITTargetMachineBuilderDetectHost(LLVMOrcJITTargetMachineBuilderRef *Result) +try: (LLVMOrcJITTargetMachineBuilderDetectHost:=dll.LLVMOrcJITTargetMachineBuilderDetectHost).restype, LLVMOrcJITTargetMachineBuilderDetectHost.argtypes = LLVMErrorRef, [ctypes.POINTER(LLVMOrcJITTargetMachineBuilderRef)] +except AttributeError: pass + +# LLVMOrcJITTargetMachineBuilderRef LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine(LLVMTargetMachineRef TM) +try: (LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine:=dll.LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine).restype, LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine.argtypes = LLVMOrcJITTargetMachineBuilderRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMOrcDisposeJITTargetMachineBuilder(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcDisposeJITTargetMachineBuilder:=dll.LLVMOrcDisposeJITTargetMachineBuilder).restype, LLVMOrcDisposeJITTargetMachineBuilder.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# char *LLVMOrcJITTargetMachineBuilderGetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB) +try: (LLVMOrcJITTargetMachineBuilderGetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderGetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderGetTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMOrcJITTargetMachineBuilderRef] +except AttributeError: pass + +# void LLVMOrcJITTargetMachineBuilderSetTargetTriple(LLVMOrcJITTargetMachineBuilderRef JTMB, const char *TargetTriple) +try: (LLVMOrcJITTargetMachineBuilderSetTargetTriple:=dll.LLVMOrcJITTargetMachineBuilderSetTargetTriple).restype, LLVMOrcJITTargetMachineBuilderSetTargetTriple.argtypes = None, [LLVMOrcJITTargetMachineBuilderRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFile(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcJITDylibRef JD, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFile:=dll.LLVMOrcObjectLayerAddObjectFile).restype, LLVMOrcObjectLayerAddObjectFile.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcJITDylibRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcObjectLayerAddObjectFileWithRT(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcResourceTrackerRef RT, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerAddObjectFileWithRT:=dll.LLVMOrcObjectLayerAddObjectFileWithRT).restype, LLVMOrcObjectLayerAddObjectFileWithRT.argtypes = LLVMErrorRef, [LLVMOrcObjectLayerRef, LLVMOrcResourceTrackerRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcObjectLayerEmit(LLVMOrcObjectLayerRef ObjLayer, LLVMOrcMaterializationResponsibilityRef R, LLVMMemoryBufferRef ObjBuffer) +try: (LLVMOrcObjectLayerEmit:=dll.LLVMOrcObjectLayerEmit).restype, LLVMOrcObjectLayerEmit.argtypes = None, [LLVMOrcObjectLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMMemoryBufferRef] +except AttributeError: pass + +# void LLVMOrcDisposeObjectLayer(LLVMOrcObjectLayerRef ObjLayer) +try: (LLVMOrcDisposeObjectLayer:=dll.LLVMOrcDisposeObjectLayer).restype, LLVMOrcDisposeObjectLayer.argtypes = None, [LLVMOrcObjectLayerRef] +except AttributeError: pass + +# void LLVMOrcIRTransformLayerEmit(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcMaterializationResponsibilityRef MR, LLVMOrcThreadSafeModuleRef TSM) +try: (LLVMOrcIRTransformLayerEmit:=dll.LLVMOrcIRTransformLayerEmit).restype, LLVMOrcIRTransformLayerEmit.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcMaterializationResponsibilityRef, LLVMOrcThreadSafeModuleRef] +except AttributeError: pass + +# void LLVMOrcIRTransformLayerSetTransform(LLVMOrcIRTransformLayerRef IRTransformLayer, LLVMOrcIRTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcIRTransformLayerSetTransform:=dll.LLVMOrcIRTransformLayerSetTransform).restype, LLVMOrcIRTransformLayerSetTransform.argtypes = None, [LLVMOrcIRTransformLayerRef, LLVMOrcIRTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +# void LLVMOrcObjectTransformLayerSetTransform(LLVMOrcObjectTransformLayerRef ObjTransformLayer, LLVMOrcObjectTransformLayerTransformFunction TransformFunction, void *Ctx) +try: (LLVMOrcObjectTransformLayerSetTransform:=dll.LLVMOrcObjectTransformLayerSetTransform).restype, LLVMOrcObjectTransformLayerSetTransform.argtypes = None, [LLVMOrcObjectTransformLayerRef, LLVMOrcObjectTransformLayerTransformFunction, ctypes.c_void_p] +except AttributeError: pass + +# LLVMOrcIndirectStubsManagerRef LLVMOrcCreateLocalIndirectStubsManager(const char *TargetTriple) +try: (LLVMOrcCreateLocalIndirectStubsManager:=dll.LLVMOrcCreateLocalIndirectStubsManager).restype, LLVMOrcCreateLocalIndirectStubsManager.argtypes = LLVMOrcIndirectStubsManagerRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcDisposeIndirectStubsManager(LLVMOrcIndirectStubsManagerRef ISM) +try: (LLVMOrcDisposeIndirectStubsManager:=dll.LLVMOrcDisposeIndirectStubsManager).restype, LLVMOrcDisposeIndirectStubsManager.argtypes = None, [LLVMOrcIndirectStubsManagerRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcCreateLocalLazyCallThroughManager(const char *TargetTriple, LLVMOrcExecutionSessionRef ES, LLVMOrcJITTargetAddress ErrorHandlerAddr, LLVMOrcLazyCallThroughManagerRef *LCTM) +try: (LLVMOrcCreateLocalLazyCallThroughManager:=dll.LLVMOrcCreateLocalLazyCallThroughManager).restype, LLVMOrcCreateLocalLazyCallThroughManager.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char), LLVMOrcExecutionSessionRef, LLVMOrcJITTargetAddress, ctypes.POINTER(LLVMOrcLazyCallThroughManagerRef)] +except AttributeError: pass + +# void LLVMOrcDisposeLazyCallThroughManager(LLVMOrcLazyCallThroughManagerRef LCTM) +try: (LLVMOrcDisposeLazyCallThroughManager:=dll.LLVMOrcDisposeLazyCallThroughManager).restype, LLVMOrcDisposeLazyCallThroughManager.argtypes = None, [LLVMOrcLazyCallThroughManagerRef] +except AttributeError: pass + +# LLVMOrcDumpObjectsRef LLVMOrcCreateDumpObjects(const char *DumpDir, const char *IdentifierOverride) +try: (LLVMOrcCreateDumpObjects:=dll.LLVMOrcCreateDumpObjects).restype, LLVMOrcCreateDumpObjects.argtypes = LLVMOrcDumpObjectsRef, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMOrcDisposeDumpObjects(LLVMOrcDumpObjectsRef DumpObjects) +try: (LLVMOrcDisposeDumpObjects:=dll.LLVMOrcDisposeDumpObjects).restype, LLVMOrcDisposeDumpObjects.argtypes = None, [LLVMOrcDumpObjectsRef] +except AttributeError: pass + +# LLVMErrorRef LLVMOrcDumpObjects_CallOperator(LLVMOrcDumpObjectsRef DumpObjects, LLVMMemoryBufferRef *ObjBuffer) +try: (LLVMOrcDumpObjects_CallOperator:=dll.LLVMOrcDumpObjects_CallOperator).restype, LLVMOrcDumpObjects_CallOperator.argtypes = LLVMErrorRef, [LLVMOrcDumpObjectsRef, ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +LLVMMemoryManagerCreateContextCallback = ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.c_void_p) +LLVMMemoryManagerNotifyTerminatingCallback = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +# LLVMOrcObjectLayerRef LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager(LLVMOrcExecutionSessionRef ES) +try: (LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager:=dll.LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager).restype, LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager.argtypes = LLVMOrcObjectLayerRef, [LLVMOrcExecutionSessionRef] +except AttributeError: pass + +# LLVMOrcObjectLayerRef LLVMOrcCreateRTDyldObjectLinkingLayerWithMCJITMemoryManagerLikeCallbacks(LLVMOrcExecutionSessionRef ES, void *CreateContextCtx, LLVMMemoryManagerCreateContextCallback CreateContext, LLVMMemoryManagerNotifyTerminatingCallback NotifyTerminating, LLVMMemoryManagerAllocateCodeSectionCallback AllocateCodeSection, LLVMMemoryManagerAllocateDataSectionCallback AllocateDataSection, LLVMMemoryManagerFinalizeMemoryCallback FinalizeMemory, LLVMMemoryManagerDestroyCallback Destroy) +try: (LLVMOrcCreateRTDyldObjectLinkingLayerWithMCJITMemoryManagerLikeCallbacks:=dll.LLVMOrcCreateRTDyldObjectLinkingLayerWithMCJITMemoryManagerLikeCallbacks).restype, LLVMOrcCreateRTDyldObjectLinkingLayerWithMCJITMemoryManagerLikeCallbacks.argtypes = LLVMOrcObjectLayerRef, [LLVMOrcExecutionSessionRef, ctypes.c_void_p, LLVMMemoryManagerCreateContextCallback, LLVMMemoryManagerNotifyTerminatingCallback, LLVMMemoryManagerAllocateCodeSectionCallback, LLVMMemoryManagerAllocateDataSectionCallback, LLVMMemoryManagerFinalizeMemoryCallback, LLVMMemoryManagerDestroyCallback] +except AttributeError: pass + +# void LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener(LLVMOrcObjectLayerRef RTDyldObjLinkingLayer, LLVMJITEventListenerRef Listener) +try: (LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener:=dll.LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener).restype, LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener.argtypes = None, [LLVMOrcObjectLayerRef, LLVMJITEventListenerRef] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +enum_LLVMRemarkType = CEnum(ctypes.c_uint32) +LLVMRemarkTypeUnknown = enum_LLVMRemarkType.define('LLVMRemarkTypeUnknown', 0) +LLVMRemarkTypePassed = enum_LLVMRemarkType.define('LLVMRemarkTypePassed', 1) +LLVMRemarkTypeMissed = enum_LLVMRemarkType.define('LLVMRemarkTypeMissed', 2) +LLVMRemarkTypeAnalysis = enum_LLVMRemarkType.define('LLVMRemarkTypeAnalysis', 3) +LLVMRemarkTypeAnalysisFPCommute = enum_LLVMRemarkType.define('LLVMRemarkTypeAnalysisFPCommute', 4) +LLVMRemarkTypeAnalysisAliasing = enum_LLVMRemarkType.define('LLVMRemarkTypeAnalysisAliasing', 5) +LLVMRemarkTypeFailure = enum_LLVMRemarkType.define('LLVMRemarkTypeFailure', 6) + +class struct_LLVMRemarkOpaqueString(Struct): pass LLVMRemarkStringRef = ctypes.POINTER(struct_LLVMRemarkOpaqueString) -try: - LLVMRemarkStringGetData = _libraries['llvm'].LLVMRemarkStringGetData - LLVMRemarkStringGetData.restype = ctypes.POINTER(ctypes.c_char) - LLVMRemarkStringGetData.argtypes = [LLVMRemarkStringRef] -except AttributeError: - pass -try: - LLVMRemarkStringGetLen = _libraries['llvm'].LLVMRemarkStringGetLen - LLVMRemarkStringGetLen.restype = uint32_t - LLVMRemarkStringGetLen.argtypes = [LLVMRemarkStringRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueDebugLoc(Structure): - pass +# extern const char *LLVMRemarkStringGetData(LLVMRemarkStringRef String) +try: (LLVMRemarkStringGetData:=dll.LLVMRemarkStringGetData).restype, LLVMRemarkStringGetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMRemarkStringRef] +except AttributeError: pass +# extern uint32_t LLVMRemarkStringGetLen(LLVMRemarkStringRef String) +try: (LLVMRemarkStringGetLen:=dll.LLVMRemarkStringGetLen).restype, LLVMRemarkStringGetLen.argtypes = uint32_t, [LLVMRemarkStringRef] +except AttributeError: pass + +class struct_LLVMRemarkOpaqueDebugLoc(Struct): pass LLVMRemarkDebugLocRef = ctypes.POINTER(struct_LLVMRemarkOpaqueDebugLoc) -try: - LLVMRemarkDebugLocGetSourceFilePath = _libraries['llvm'].LLVMRemarkDebugLocGetSourceFilePath - LLVMRemarkDebugLocGetSourceFilePath.restype = LLVMRemarkStringRef - LLVMRemarkDebugLocGetSourceFilePath.argtypes = [LLVMRemarkDebugLocRef] -except AttributeError: - pass -try: - LLVMRemarkDebugLocGetSourceLine = _libraries['llvm'].LLVMRemarkDebugLocGetSourceLine - LLVMRemarkDebugLocGetSourceLine.restype = uint32_t - LLVMRemarkDebugLocGetSourceLine.argtypes = [LLVMRemarkDebugLocRef] -except AttributeError: - pass -try: - LLVMRemarkDebugLocGetSourceColumn = _libraries['llvm'].LLVMRemarkDebugLocGetSourceColumn - LLVMRemarkDebugLocGetSourceColumn.restype = uint32_t - LLVMRemarkDebugLocGetSourceColumn.argtypes = [LLVMRemarkDebugLocRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueArg(Structure): - pass +# extern LLVMRemarkStringRef LLVMRemarkDebugLocGetSourceFilePath(LLVMRemarkDebugLocRef DL) +try: (LLVMRemarkDebugLocGetSourceFilePath:=dll.LLVMRemarkDebugLocGetSourceFilePath).restype, LLVMRemarkDebugLocGetSourceFilePath.argtypes = LLVMRemarkStringRef, [LLVMRemarkDebugLocRef] +except AttributeError: pass +# extern uint32_t LLVMRemarkDebugLocGetSourceLine(LLVMRemarkDebugLocRef DL) +try: (LLVMRemarkDebugLocGetSourceLine:=dll.LLVMRemarkDebugLocGetSourceLine).restype, LLVMRemarkDebugLocGetSourceLine.argtypes = uint32_t, [LLVMRemarkDebugLocRef] +except AttributeError: pass + +# extern uint32_t LLVMRemarkDebugLocGetSourceColumn(LLVMRemarkDebugLocRef DL) +try: (LLVMRemarkDebugLocGetSourceColumn:=dll.LLVMRemarkDebugLocGetSourceColumn).restype, LLVMRemarkDebugLocGetSourceColumn.argtypes = uint32_t, [LLVMRemarkDebugLocRef] +except AttributeError: pass + +class struct_LLVMRemarkOpaqueArg(Struct): pass LLVMRemarkArgRef = ctypes.POINTER(struct_LLVMRemarkOpaqueArg) -try: - LLVMRemarkArgGetKey = _libraries['llvm'].LLVMRemarkArgGetKey - LLVMRemarkArgGetKey.restype = LLVMRemarkStringRef - LLVMRemarkArgGetKey.argtypes = [LLVMRemarkArgRef] -except AttributeError: - pass -try: - LLVMRemarkArgGetValue = _libraries['llvm'].LLVMRemarkArgGetValue - LLVMRemarkArgGetValue.restype = LLVMRemarkStringRef - LLVMRemarkArgGetValue.argtypes = [LLVMRemarkArgRef] -except AttributeError: - pass -try: - LLVMRemarkArgGetDebugLoc = _libraries['llvm'].LLVMRemarkArgGetDebugLoc - LLVMRemarkArgGetDebugLoc.restype = LLVMRemarkDebugLocRef - LLVMRemarkArgGetDebugLoc.argtypes = [LLVMRemarkArgRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueEntry(Structure): - pass +# extern LLVMRemarkStringRef LLVMRemarkArgGetKey(LLVMRemarkArgRef Arg) +try: (LLVMRemarkArgGetKey:=dll.LLVMRemarkArgGetKey).restype, LLVMRemarkArgGetKey.argtypes = LLVMRemarkStringRef, [LLVMRemarkArgRef] +except AttributeError: pass +# extern LLVMRemarkStringRef LLVMRemarkArgGetValue(LLVMRemarkArgRef Arg) +try: (LLVMRemarkArgGetValue:=dll.LLVMRemarkArgGetValue).restype, LLVMRemarkArgGetValue.argtypes = LLVMRemarkStringRef, [LLVMRemarkArgRef] +except AttributeError: pass + +# extern LLVMRemarkDebugLocRef LLVMRemarkArgGetDebugLoc(LLVMRemarkArgRef Arg) +try: (LLVMRemarkArgGetDebugLoc:=dll.LLVMRemarkArgGetDebugLoc).restype, LLVMRemarkArgGetDebugLoc.argtypes = LLVMRemarkDebugLocRef, [LLVMRemarkArgRef] +except AttributeError: pass + +class struct_LLVMRemarkOpaqueEntry(Struct): pass LLVMRemarkEntryRef = ctypes.POINTER(struct_LLVMRemarkOpaqueEntry) -try: - LLVMRemarkEntryDispose = _libraries['llvm'].LLVMRemarkEntryDispose - LLVMRemarkEntryDispose.restype = None - LLVMRemarkEntryDispose.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetType = _libraries['llvm'].LLVMRemarkEntryGetType - LLVMRemarkEntryGetType.restype = LLVMRemarkType - LLVMRemarkEntryGetType.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetPassName = _libraries['llvm'].LLVMRemarkEntryGetPassName - LLVMRemarkEntryGetPassName.restype = LLVMRemarkStringRef - LLVMRemarkEntryGetPassName.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetRemarkName = _libraries['llvm'].LLVMRemarkEntryGetRemarkName - LLVMRemarkEntryGetRemarkName.restype = LLVMRemarkStringRef - LLVMRemarkEntryGetRemarkName.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetFunctionName = _libraries['llvm'].LLVMRemarkEntryGetFunctionName - LLVMRemarkEntryGetFunctionName.restype = LLVMRemarkStringRef - LLVMRemarkEntryGetFunctionName.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetDebugLoc = _libraries['llvm'].LLVMRemarkEntryGetDebugLoc - LLVMRemarkEntryGetDebugLoc.restype = LLVMRemarkDebugLocRef - LLVMRemarkEntryGetDebugLoc.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetHotness = _libraries['llvm'].LLVMRemarkEntryGetHotness - LLVMRemarkEntryGetHotness.restype = uint64_t - LLVMRemarkEntryGetHotness.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetNumArgs = _libraries['llvm'].LLVMRemarkEntryGetNumArgs - LLVMRemarkEntryGetNumArgs.restype = uint32_t - LLVMRemarkEntryGetNumArgs.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetFirstArg = _libraries['llvm'].LLVMRemarkEntryGetFirstArg - LLVMRemarkEntryGetFirstArg.restype = LLVMRemarkArgRef - LLVMRemarkEntryGetFirstArg.argtypes = [LLVMRemarkEntryRef] -except AttributeError: - pass -try: - LLVMRemarkEntryGetNextArg = _libraries['llvm'].LLVMRemarkEntryGetNextArg - LLVMRemarkEntryGetNextArg.restype = LLVMRemarkArgRef - LLVMRemarkEntryGetNextArg.argtypes = [LLVMRemarkArgRef, LLVMRemarkEntryRef] -except AttributeError: - pass -class struct_LLVMRemarkOpaqueParser(Structure): - pass +# extern void LLVMRemarkEntryDispose(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryDispose:=dll.LLVMRemarkEntryDispose).restype, LLVMRemarkEntryDispose.argtypes = None, [LLVMRemarkEntryRef] +except AttributeError: pass +# extern enum LLVMRemarkType LLVMRemarkEntryGetType(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetType:=dll.LLVMRemarkEntryGetType).restype, LLVMRemarkEntryGetType.argtypes = enum_LLVMRemarkType, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern LLVMRemarkStringRef LLVMRemarkEntryGetPassName(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetPassName:=dll.LLVMRemarkEntryGetPassName).restype, LLVMRemarkEntryGetPassName.argtypes = LLVMRemarkStringRef, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern LLVMRemarkStringRef LLVMRemarkEntryGetRemarkName(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetRemarkName:=dll.LLVMRemarkEntryGetRemarkName).restype, LLVMRemarkEntryGetRemarkName.argtypes = LLVMRemarkStringRef, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern LLVMRemarkStringRef LLVMRemarkEntryGetFunctionName(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetFunctionName:=dll.LLVMRemarkEntryGetFunctionName).restype, LLVMRemarkEntryGetFunctionName.argtypes = LLVMRemarkStringRef, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern LLVMRemarkDebugLocRef LLVMRemarkEntryGetDebugLoc(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetDebugLoc:=dll.LLVMRemarkEntryGetDebugLoc).restype, LLVMRemarkEntryGetDebugLoc.argtypes = LLVMRemarkDebugLocRef, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern uint64_t LLVMRemarkEntryGetHotness(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetHotness:=dll.LLVMRemarkEntryGetHotness).restype, LLVMRemarkEntryGetHotness.argtypes = uint64_t, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern uint32_t LLVMRemarkEntryGetNumArgs(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetNumArgs:=dll.LLVMRemarkEntryGetNumArgs).restype, LLVMRemarkEntryGetNumArgs.argtypes = uint32_t, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern LLVMRemarkArgRef LLVMRemarkEntryGetFirstArg(LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetFirstArg:=dll.LLVMRemarkEntryGetFirstArg).restype, LLVMRemarkEntryGetFirstArg.argtypes = LLVMRemarkArgRef, [LLVMRemarkEntryRef] +except AttributeError: pass + +# extern LLVMRemarkArgRef LLVMRemarkEntryGetNextArg(LLVMRemarkArgRef It, LLVMRemarkEntryRef Remark) +try: (LLVMRemarkEntryGetNextArg:=dll.LLVMRemarkEntryGetNextArg).restype, LLVMRemarkEntryGetNextArg.argtypes = LLVMRemarkArgRef, [LLVMRemarkArgRef, LLVMRemarkEntryRef] +except AttributeError: pass + +class struct_LLVMRemarkOpaqueParser(Struct): pass LLVMRemarkParserRef = ctypes.POINTER(struct_LLVMRemarkOpaqueParser) -try: - LLVMRemarkParserCreateYAML = _libraries['llvm'].LLVMRemarkParserCreateYAML - LLVMRemarkParserCreateYAML.restype = LLVMRemarkParserRef - LLVMRemarkParserCreateYAML.argtypes = [ctypes.POINTER(None), uint64_t] -except AttributeError: - pass -try: - LLVMRemarkParserCreateBitstream = _libraries['llvm'].LLVMRemarkParserCreateBitstream - LLVMRemarkParserCreateBitstream.restype = LLVMRemarkParserRef - LLVMRemarkParserCreateBitstream.argtypes = [ctypes.POINTER(None), uint64_t] -except AttributeError: - pass -try: - LLVMRemarkParserGetNext = _libraries['llvm'].LLVMRemarkParserGetNext - LLVMRemarkParserGetNext.restype = LLVMRemarkEntryRef - LLVMRemarkParserGetNext.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkParserHasError = _libraries['llvm'].LLVMRemarkParserHasError - LLVMRemarkParserHasError.restype = LLVMBool - LLVMRemarkParserHasError.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkParserGetErrorMessage = _libraries['llvm'].LLVMRemarkParserGetErrorMessage - LLVMRemarkParserGetErrorMessage.restype = ctypes.POINTER(ctypes.c_char) - LLVMRemarkParserGetErrorMessage.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkParserDispose = _libraries['llvm'].LLVMRemarkParserDispose - LLVMRemarkParserDispose.restype = None - LLVMRemarkParserDispose.argtypes = [LLVMRemarkParserRef] -except AttributeError: - pass -try: - LLVMRemarkVersion = _libraries['llvm'].LLVMRemarkVersion - LLVMRemarkVersion.restype = uint32_t - LLVMRemarkVersion.argtypes = [] -except AttributeError: - pass -LLVM_C_SUPPORT_H = True # macro -try: - LLVMLoadLibraryPermanently = _libraries['llvm'].LLVMLoadLibraryPermanently - LLVMLoadLibraryPermanently.restype = LLVMBool - LLVMLoadLibraryPermanently.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMParseCommandLineOptions = _libraries['llvm'].LLVMParseCommandLineOptions - LLVMParseCommandLineOptions.restype = None - LLVMParseCommandLineOptions.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMSearchForAddressOfSymbol = _libraries['llvm'].LLVMSearchForAddressOfSymbol - LLVMSearchForAddressOfSymbol.restype = ctypes.POINTER(None) - LLVMSearchForAddressOfSymbol.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - LLVMAddSymbol = _libraries['llvm'].LLVMAddSymbol - LLVMAddSymbol.restype = None - LLVMAddSymbol.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)] -except AttributeError: - pass -LLVM_C_TRANSFORMS_AGGRESSIVEINSTCOMBINE_H = True # macro -try: - LLVMAddAggressiveInstCombinerPass = _libraries['llvm'].LLVMAddAggressiveInstCombinerPass - LLVMAddAggressiveInstCombinerPass.restype = None - LLVMAddAggressiveInstCombinerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_COROUTINES_H = True # macro -LLVM_C_TRANSFORMS_PASSMANAGERBUILDER_H = True # macro -class struct_LLVMOpaquePassManagerBuilder(Structure): - pass +# extern LLVMRemarkParserRef LLVMRemarkParserCreateYAML(const void *Buf, uint64_t Size) +try: (LLVMRemarkParserCreateYAML:=dll.LLVMRemarkParserCreateYAML).restype, LLVMRemarkParserCreateYAML.argtypes = LLVMRemarkParserRef, [ctypes.c_void_p, uint64_t] +except AttributeError: pass -LLVMPassManagerBuilderRef = ctypes.POINTER(struct_LLVMOpaquePassManagerBuilder) -try: - LLVMPassManagerBuilderCreate = _libraries['llvm'].LLVMPassManagerBuilderCreate - LLVMPassManagerBuilderCreate.restype = LLVMPassManagerBuilderRef - LLVMPassManagerBuilderCreate.argtypes = [] -except AttributeError: - pass -try: - LLVMPassManagerBuilderDispose = _libraries['llvm'].LLVMPassManagerBuilderDispose - LLVMPassManagerBuilderDispose.restype = None - LLVMPassManagerBuilderDispose.argtypes = [LLVMPassManagerBuilderRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetOptLevel = _libraries['llvm'].LLVMPassManagerBuilderSetOptLevel - LLVMPassManagerBuilderSetOptLevel.restype = None - LLVMPassManagerBuilderSetOptLevel.argtypes = [LLVMPassManagerBuilderRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetSizeLevel = _libraries['llvm'].LLVMPassManagerBuilderSetSizeLevel - LLVMPassManagerBuilderSetSizeLevel.restype = None - LLVMPassManagerBuilderSetSizeLevel.argtypes = [LLVMPassManagerBuilderRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetDisableUnitAtATime = _libraries['llvm'].LLVMPassManagerBuilderSetDisableUnitAtATime - LLVMPassManagerBuilderSetDisableUnitAtATime.restype = None - LLVMPassManagerBuilderSetDisableUnitAtATime.argtypes = [LLVMPassManagerBuilderRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetDisableUnrollLoops = _libraries['llvm'].LLVMPassManagerBuilderSetDisableUnrollLoops - LLVMPassManagerBuilderSetDisableUnrollLoops.restype = None - LLVMPassManagerBuilderSetDisableUnrollLoops.argtypes = [LLVMPassManagerBuilderRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassManagerBuilderSetDisableSimplifyLibCalls = _libraries['llvm'].LLVMPassManagerBuilderSetDisableSimplifyLibCalls - LLVMPassManagerBuilderSetDisableSimplifyLibCalls.restype = None - LLVMPassManagerBuilderSetDisableSimplifyLibCalls.argtypes = [LLVMPassManagerBuilderRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassManagerBuilderUseInlinerWithThreshold = _libraries['llvm'].LLVMPassManagerBuilderUseInlinerWithThreshold - LLVMPassManagerBuilderUseInlinerWithThreshold.restype = None - LLVMPassManagerBuilderUseInlinerWithThreshold.argtypes = [LLVMPassManagerBuilderRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassManagerBuilderPopulateFunctionPassManager = _libraries['llvm'].LLVMPassManagerBuilderPopulateFunctionPassManager - LLVMPassManagerBuilderPopulateFunctionPassManager.restype = None - LLVMPassManagerBuilderPopulateFunctionPassManager.argtypes = [LLVMPassManagerBuilderRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderPopulateModulePassManager = _libraries['llvm'].LLVMPassManagerBuilderPopulateModulePassManager - LLVMPassManagerBuilderPopulateModulePassManager.restype = None - LLVMPassManagerBuilderPopulateModulePassManager.argtypes = [LLVMPassManagerBuilderRef, LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderPopulateLTOPassManager = _libraries['llvm'].LLVMPassManagerBuilderPopulateLTOPassManager - LLVMPassManagerBuilderPopulateLTOPassManager.restype = None - LLVMPassManagerBuilderPopulateLTOPassManager.argtypes = [LLVMPassManagerBuilderRef, LLVMPassManagerRef, LLVMBool, LLVMBool] -except AttributeError: - pass -try: - LLVMAddCoroEarlyPass = _libraries['llvm'].LLVMAddCoroEarlyPass - LLVMAddCoroEarlyPass.restype = None - LLVMAddCoroEarlyPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCoroSplitPass = _libraries['llvm'].LLVMAddCoroSplitPass - LLVMAddCoroSplitPass.restype = None - LLVMAddCoroSplitPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCoroElidePass = _libraries['llvm'].LLVMAddCoroElidePass - LLVMAddCoroElidePass.restype = None - LLVMAddCoroElidePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCoroCleanupPass = _libraries['llvm'].LLVMAddCoroCleanupPass - LLVMAddCoroCleanupPass.restype = None - LLVMAddCoroCleanupPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints = _libraries['llvm'].LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints - LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints.restype = None - LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints.argtypes = [LLVMPassManagerBuilderRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_IPO_H = True # macro -try: - LLVMAddArgumentPromotionPass = _libraries['llvm'].LLVMAddArgumentPromotionPass - LLVMAddArgumentPromotionPass.restype = None - LLVMAddArgumentPromotionPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddConstantMergePass = _libraries['llvm'].LLVMAddConstantMergePass - LLVMAddConstantMergePass.restype = None - LLVMAddConstantMergePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddMergeFunctionsPass = _libraries['llvm'].LLVMAddMergeFunctionsPass - LLVMAddMergeFunctionsPass.restype = None - LLVMAddMergeFunctionsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCalledValuePropagationPass = _libraries['llvm'].LLVMAddCalledValuePropagationPass - LLVMAddCalledValuePropagationPass.restype = None - LLVMAddCalledValuePropagationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDeadArgEliminationPass = _libraries['llvm'].LLVMAddDeadArgEliminationPass - LLVMAddDeadArgEliminationPass.restype = None - LLVMAddDeadArgEliminationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddFunctionAttrsPass = _libraries['llvm'].LLVMAddFunctionAttrsPass - LLVMAddFunctionAttrsPass.restype = None - LLVMAddFunctionAttrsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddFunctionInliningPass = _libraries['llvm'].LLVMAddFunctionInliningPass - LLVMAddFunctionInliningPass.restype = None - LLVMAddFunctionInliningPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddAlwaysInlinerPass = _libraries['llvm'].LLVMAddAlwaysInlinerPass - LLVMAddAlwaysInlinerPass.restype = None - LLVMAddAlwaysInlinerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddGlobalDCEPass = _libraries['llvm'].LLVMAddGlobalDCEPass - LLVMAddGlobalDCEPass.restype = None - LLVMAddGlobalDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddGlobalOptimizerPass = _libraries['llvm'].LLVMAddGlobalOptimizerPass - LLVMAddGlobalOptimizerPass.restype = None - LLVMAddGlobalOptimizerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddPruneEHPass = _libraries['llvm'].LLVMAddPruneEHPass - LLVMAddPruneEHPass.restype = None - LLVMAddPruneEHPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddIPSCCPPass = _libraries['llvm'].LLVMAddIPSCCPPass - LLVMAddIPSCCPPass.restype = None - LLVMAddIPSCCPPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddInternalizePass = _libraries['llvm'].LLVMAddInternalizePass - LLVMAddInternalizePass.restype = None - LLVMAddInternalizePass.argtypes = [LLVMPassManagerRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMAddInternalizePassWithMustPreservePredicate = _libraries['llvm'].LLVMAddInternalizePassWithMustPreservePredicate - LLVMAddInternalizePassWithMustPreservePredicate.restype = None - LLVMAddInternalizePassWithMustPreservePredicate.argtypes = [LLVMPassManagerRef, ctypes.POINTER(None), ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(None))] -except AttributeError: - pass -try: - LLVMAddStripDeadPrototypesPass = _libraries['llvm'].LLVMAddStripDeadPrototypesPass - LLVMAddStripDeadPrototypesPass.restype = None - LLVMAddStripDeadPrototypesPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddStripSymbolsPass = _libraries['llvm'].LLVMAddStripSymbolsPass - LLVMAddStripSymbolsPass.restype = None - LLVMAddStripSymbolsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_INSTCOMBINE_H = True # macro -try: - LLVMAddInstructionCombiningPass = _libraries['llvm'].LLVMAddInstructionCombiningPass - LLVMAddInstructionCombiningPass.restype = None - LLVMAddInstructionCombiningPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_PASSBUILDER_H = True # macro -class struct_LLVMOpaquePassBuilderOptions(Structure): - pass +# extern LLVMRemarkParserRef LLVMRemarkParserCreateBitstream(const void *Buf, uint64_t Size) +try: (LLVMRemarkParserCreateBitstream:=dll.LLVMRemarkParserCreateBitstream).restype, LLVMRemarkParserCreateBitstream.argtypes = LLVMRemarkParserRef, [ctypes.c_void_p, uint64_t] +except AttributeError: pass +# extern LLVMRemarkEntryRef LLVMRemarkParserGetNext(LLVMRemarkParserRef Parser) +try: (LLVMRemarkParserGetNext:=dll.LLVMRemarkParserGetNext).restype, LLVMRemarkParserGetNext.argtypes = LLVMRemarkEntryRef, [LLVMRemarkParserRef] +except AttributeError: pass + +# extern LLVMBool LLVMRemarkParserHasError(LLVMRemarkParserRef Parser) +try: (LLVMRemarkParserHasError:=dll.LLVMRemarkParserHasError).restype, LLVMRemarkParserHasError.argtypes = LLVMBool, [LLVMRemarkParserRef] +except AttributeError: pass + +# extern const char *LLVMRemarkParserGetErrorMessage(LLVMRemarkParserRef Parser) +try: (LLVMRemarkParserGetErrorMessage:=dll.LLVMRemarkParserGetErrorMessage).restype, LLVMRemarkParserGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMRemarkParserRef] +except AttributeError: pass + +# extern void LLVMRemarkParserDispose(LLVMRemarkParserRef Parser) +try: (LLVMRemarkParserDispose:=dll.LLVMRemarkParserDispose).restype, LLVMRemarkParserDispose.argtypes = None, [LLVMRemarkParserRef] +except AttributeError: pass + +# extern uint32_t LLVMRemarkVersion(void) +try: (LLVMRemarkVersion:=dll.LLVMRemarkVersion).restype, LLVMRemarkVersion.argtypes = uint32_t, [] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# LLVMBool LLVMLoadLibraryPermanently(const char *Filename) +try: (LLVMLoadLibraryPermanently:=dll.LLVMLoadLibraryPermanently).restype, LLVMLoadLibraryPermanently.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMParseCommandLineOptions(int argc, const char *const *argv, const char *Overview) +try: (LLVMParseCommandLineOptions:=dll.LLVMParseCommandLineOptions).restype, LLVMParseCommandLineOptions.argtypes = None, [ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void *LLVMSearchForAddressOfSymbol(const char *symbolName) +try: (LLVMSearchForAddressOfSymbol:=dll.LLVMSearchForAddressOfSymbol).restype, LLVMSearchForAddressOfSymbol.argtypes = ctypes.c_void_p, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMAddSymbol(const char *symbolName, void *symbolValue) +try: (LLVMAddSymbol:=dll.LLVMAddSymbol).restype, LLVMAddSymbol.argtypes = None, [ctypes.POINTER(ctypes.c_char), ctypes.c_void_p] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass + +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetErrorTypeId(LLVMErrorRef Err) +try: (LLVMGetErrorTypeId:=dll.LLVMGetErrorTypeId).restype, LLVMGetErrorTypeId.argtypes = LLVMErrorTypeId, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMConsumeError(LLVMErrorRef Err) +try: (LLVMConsumeError:=dll.LLVMConsumeError).restype, LLVMConsumeError.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# void LLVMCantFail(LLVMErrorRef Err) +try: (LLVMCantFail:=dll.LLVMCantFail).restype, LLVMCantFail.argtypes = None, [LLVMErrorRef] +except AttributeError: pass + +# char *LLVMGetErrorMessage(LLVMErrorRef Err) +try: (LLVMGetErrorMessage:=dll.LLVMGetErrorMessage).restype, LLVMGetErrorMessage.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMErrorRef] +except AttributeError: pass + +# void LLVMDisposeErrorMessage(char *ErrMsg) +try: (LLVMDisposeErrorMessage:=dll.LLVMDisposeErrorMessage).restype, LLVMDisposeErrorMessage.argtypes = None, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMErrorTypeId LLVMGetStringErrorTypeId(void) +try: (LLVMGetStringErrorTypeId:=dll.LLVMGetStringErrorTypeId).restype, LLVMGetStringErrorTypeId.argtypes = LLVMErrorTypeId, [] +except AttributeError: pass + +# LLVMErrorRef LLVMCreateStringError(const char *ErrMsg) +try: (LLVMCreateStringError:=dll.LLVMCreateStringError).restype, LLVMCreateStringError.argtypes = LLVMErrorRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetInfo(void) +try: (LLVMInitializeAArch64TargetInfo:=dll.LLVMInitializeAArch64TargetInfo).restype, LLVMInitializeAArch64TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetInfo(void) +try: (LLVMInitializeAMDGPUTargetInfo:=dll.LLVMInitializeAMDGPUTargetInfo).restype, LLVMInitializeAMDGPUTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetInfo(void) +try: (LLVMInitializeARMTargetInfo:=dll.LLVMInitializeARMTargetInfo).restype, LLVMInitializeARMTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetInfo(void) +try: (LLVMInitializeAVRTargetInfo:=dll.LLVMInitializeAVRTargetInfo).restype, LLVMInitializeAVRTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetInfo(void) +try: (LLVMInitializeBPFTargetInfo:=dll.LLVMInitializeBPFTargetInfo).restype, LLVMInitializeBPFTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetInfo(void) +try: (LLVMInitializeHexagonTargetInfo:=dll.LLVMInitializeHexagonTargetInfo).restype, LLVMInitializeHexagonTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetInfo(void) +try: (LLVMInitializeLanaiTargetInfo:=dll.LLVMInitializeLanaiTargetInfo).restype, LLVMInitializeLanaiTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetInfo(void) +try: (LLVMInitializeLoongArchTargetInfo:=dll.LLVMInitializeLoongArchTargetInfo).restype, LLVMInitializeLoongArchTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetInfo(void) +try: (LLVMInitializeMipsTargetInfo:=dll.LLVMInitializeMipsTargetInfo).restype, LLVMInitializeMipsTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetInfo(void) +try: (LLVMInitializeMSP430TargetInfo:=dll.LLVMInitializeMSP430TargetInfo).restype, LLVMInitializeMSP430TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetInfo(void) +try: (LLVMInitializeNVPTXTargetInfo:=dll.LLVMInitializeNVPTXTargetInfo).restype, LLVMInitializeNVPTXTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetInfo(void) +try: (LLVMInitializePowerPCTargetInfo:=dll.LLVMInitializePowerPCTargetInfo).restype, LLVMInitializePowerPCTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetInfo(void) +try: (LLVMInitializeRISCVTargetInfo:=dll.LLVMInitializeRISCVTargetInfo).restype, LLVMInitializeRISCVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetInfo(void) +try: (LLVMInitializeSparcTargetInfo:=dll.LLVMInitializeSparcTargetInfo).restype, LLVMInitializeSparcTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetInfo(void) +try: (LLVMInitializeSPIRVTargetInfo:=dll.LLVMInitializeSPIRVTargetInfo).restype, LLVMInitializeSPIRVTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetInfo(void) +try: (LLVMInitializeSystemZTargetInfo:=dll.LLVMInitializeSystemZTargetInfo).restype, LLVMInitializeSystemZTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetInfo(void) +try: (LLVMInitializeVETargetInfo:=dll.LLVMInitializeVETargetInfo).restype, LLVMInitializeVETargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetInfo(void) +try: (LLVMInitializeWebAssemblyTargetInfo:=dll.LLVMInitializeWebAssemblyTargetInfo).restype, LLVMInitializeWebAssemblyTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetInfo(void) +try: (LLVMInitializeX86TargetInfo:=dll.LLVMInitializeX86TargetInfo).restype, LLVMInitializeX86TargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetInfo(void) +try: (LLVMInitializeXCoreTargetInfo:=dll.LLVMInitializeXCoreTargetInfo).restype, LLVMInitializeXCoreTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetInfo(void) +try: (LLVMInitializeM68kTargetInfo:=dll.LLVMInitializeM68kTargetInfo).restype, LLVMInitializeM68kTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetInfo(void) +try: (LLVMInitializeXtensaTargetInfo:=dll.LLVMInitializeXtensaTargetInfo).restype, LLVMInitializeXtensaTargetInfo.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Target(void) +try: (LLVMInitializeAArch64Target:=dll.LLVMInitializeAArch64Target).restype, LLVMInitializeAArch64Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTarget(void) +try: (LLVMInitializeAMDGPUTarget:=dll.LLVMInitializeAMDGPUTarget).restype, LLVMInitializeAMDGPUTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTarget(void) +try: (LLVMInitializeARMTarget:=dll.LLVMInitializeARMTarget).restype, LLVMInitializeARMTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTarget(void) +try: (LLVMInitializeAVRTarget:=dll.LLVMInitializeAVRTarget).restype, LLVMInitializeAVRTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTarget(void) +try: (LLVMInitializeBPFTarget:=dll.LLVMInitializeBPFTarget).restype, LLVMInitializeBPFTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTarget(void) +try: (LLVMInitializeHexagonTarget:=dll.LLVMInitializeHexagonTarget).restype, LLVMInitializeHexagonTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTarget(void) +try: (LLVMInitializeLanaiTarget:=dll.LLVMInitializeLanaiTarget).restype, LLVMInitializeLanaiTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTarget(void) +try: (LLVMInitializeLoongArchTarget:=dll.LLVMInitializeLoongArchTarget).restype, LLVMInitializeLoongArchTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTarget(void) +try: (LLVMInitializeMipsTarget:=dll.LLVMInitializeMipsTarget).restype, LLVMInitializeMipsTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Target(void) +try: (LLVMInitializeMSP430Target:=dll.LLVMInitializeMSP430Target).restype, LLVMInitializeMSP430Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTarget(void) +try: (LLVMInitializeNVPTXTarget:=dll.LLVMInitializeNVPTXTarget).restype, LLVMInitializeNVPTXTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTarget(void) +try: (LLVMInitializePowerPCTarget:=dll.LLVMInitializePowerPCTarget).restype, LLVMInitializePowerPCTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTarget(void) +try: (LLVMInitializeRISCVTarget:=dll.LLVMInitializeRISCVTarget).restype, LLVMInitializeRISCVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTarget(void) +try: (LLVMInitializeSparcTarget:=dll.LLVMInitializeSparcTarget).restype, LLVMInitializeSparcTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTarget(void) +try: (LLVMInitializeSPIRVTarget:=dll.LLVMInitializeSPIRVTarget).restype, LLVMInitializeSPIRVTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTarget(void) +try: (LLVMInitializeSystemZTarget:=dll.LLVMInitializeSystemZTarget).restype, LLVMInitializeSystemZTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETarget(void) +try: (LLVMInitializeVETarget:=dll.LLVMInitializeVETarget).restype, LLVMInitializeVETarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTarget(void) +try: (LLVMInitializeWebAssemblyTarget:=dll.LLVMInitializeWebAssemblyTarget).restype, LLVMInitializeWebAssemblyTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Target(void) +try: (LLVMInitializeX86Target:=dll.LLVMInitializeX86Target).restype, LLVMInitializeX86Target.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTarget(void) +try: (LLVMInitializeXCoreTarget:=dll.LLVMInitializeXCoreTarget).restype, LLVMInitializeXCoreTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTarget(void) +try: (LLVMInitializeM68kTarget:=dll.LLVMInitializeM68kTarget).restype, LLVMInitializeM68kTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTarget(void) +try: (LLVMInitializeXtensaTarget:=dll.LLVMInitializeXtensaTarget).restype, LLVMInitializeXtensaTarget.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64TargetMC(void) +try: (LLVMInitializeAArch64TargetMC:=dll.LLVMInitializeAArch64TargetMC).restype, LLVMInitializeAArch64TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUTargetMC(void) +try: (LLVMInitializeAMDGPUTargetMC:=dll.LLVMInitializeAMDGPUTargetMC).restype, LLVMInitializeAMDGPUTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMTargetMC(void) +try: (LLVMInitializeARMTargetMC:=dll.LLVMInitializeARMTargetMC).restype, LLVMInitializeARMTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRTargetMC(void) +try: (LLVMInitializeAVRTargetMC:=dll.LLVMInitializeAVRTargetMC).restype, LLVMInitializeAVRTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFTargetMC(void) +try: (LLVMInitializeBPFTargetMC:=dll.LLVMInitializeBPFTargetMC).restype, LLVMInitializeBPFTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonTargetMC(void) +try: (LLVMInitializeHexagonTargetMC:=dll.LLVMInitializeHexagonTargetMC).restype, LLVMInitializeHexagonTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiTargetMC(void) +try: (LLVMInitializeLanaiTargetMC:=dll.LLVMInitializeLanaiTargetMC).restype, LLVMInitializeLanaiTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchTargetMC(void) +try: (LLVMInitializeLoongArchTargetMC:=dll.LLVMInitializeLoongArchTargetMC).restype, LLVMInitializeLoongArchTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsTargetMC(void) +try: (LLVMInitializeMipsTargetMC:=dll.LLVMInitializeMipsTargetMC).restype, LLVMInitializeMipsTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430TargetMC(void) +try: (LLVMInitializeMSP430TargetMC:=dll.LLVMInitializeMSP430TargetMC).restype, LLVMInitializeMSP430TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXTargetMC(void) +try: (LLVMInitializeNVPTXTargetMC:=dll.LLVMInitializeNVPTXTargetMC).restype, LLVMInitializeNVPTXTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCTargetMC(void) +try: (LLVMInitializePowerPCTargetMC:=dll.LLVMInitializePowerPCTargetMC).restype, LLVMInitializePowerPCTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVTargetMC(void) +try: (LLVMInitializeRISCVTargetMC:=dll.LLVMInitializeRISCVTargetMC).restype, LLVMInitializeRISCVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcTargetMC(void) +try: (LLVMInitializeSparcTargetMC:=dll.LLVMInitializeSparcTargetMC).restype, LLVMInitializeSparcTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVTargetMC(void) +try: (LLVMInitializeSPIRVTargetMC:=dll.LLVMInitializeSPIRVTargetMC).restype, LLVMInitializeSPIRVTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZTargetMC(void) +try: (LLVMInitializeSystemZTargetMC:=dll.LLVMInitializeSystemZTargetMC).restype, LLVMInitializeSystemZTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVETargetMC(void) +try: (LLVMInitializeVETargetMC:=dll.LLVMInitializeVETargetMC).restype, LLVMInitializeVETargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyTargetMC(void) +try: (LLVMInitializeWebAssemblyTargetMC:=dll.LLVMInitializeWebAssemblyTargetMC).restype, LLVMInitializeWebAssemblyTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86TargetMC(void) +try: (LLVMInitializeX86TargetMC:=dll.LLVMInitializeX86TargetMC).restype, LLVMInitializeX86TargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreTargetMC(void) +try: (LLVMInitializeXCoreTargetMC:=dll.LLVMInitializeXCoreTargetMC).restype, LLVMInitializeXCoreTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kTargetMC(void) +try: (LLVMInitializeM68kTargetMC:=dll.LLVMInitializeM68kTargetMC).restype, LLVMInitializeM68kTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaTargetMC(void) +try: (LLVMInitializeXtensaTargetMC:=dll.LLVMInitializeXtensaTargetMC).restype, LLVMInitializeXtensaTargetMC.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmPrinter(void) +try: (LLVMInitializeAArch64AsmPrinter:=dll.LLVMInitializeAArch64AsmPrinter).restype, LLVMInitializeAArch64AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmPrinter(void) +try: (LLVMInitializeAMDGPUAsmPrinter:=dll.LLVMInitializeAMDGPUAsmPrinter).restype, LLVMInitializeAMDGPUAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmPrinter(void) +try: (LLVMInitializeARMAsmPrinter:=dll.LLVMInitializeARMAsmPrinter).restype, LLVMInitializeARMAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmPrinter(void) +try: (LLVMInitializeAVRAsmPrinter:=dll.LLVMInitializeAVRAsmPrinter).restype, LLVMInitializeAVRAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmPrinter(void) +try: (LLVMInitializeBPFAsmPrinter:=dll.LLVMInitializeBPFAsmPrinter).restype, LLVMInitializeBPFAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmPrinter(void) +try: (LLVMInitializeHexagonAsmPrinter:=dll.LLVMInitializeHexagonAsmPrinter).restype, LLVMInitializeHexagonAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmPrinter(void) +try: (LLVMInitializeLanaiAsmPrinter:=dll.LLVMInitializeLanaiAsmPrinter).restype, LLVMInitializeLanaiAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmPrinter(void) +try: (LLVMInitializeLoongArchAsmPrinter:=dll.LLVMInitializeLoongArchAsmPrinter).restype, LLVMInitializeLoongArchAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmPrinter(void) +try: (LLVMInitializeMipsAsmPrinter:=dll.LLVMInitializeMipsAsmPrinter).restype, LLVMInitializeMipsAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmPrinter(void) +try: (LLVMInitializeMSP430AsmPrinter:=dll.LLVMInitializeMSP430AsmPrinter).restype, LLVMInitializeMSP430AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeNVPTXAsmPrinter(void) +try: (LLVMInitializeNVPTXAsmPrinter:=dll.LLVMInitializeNVPTXAsmPrinter).restype, LLVMInitializeNVPTXAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmPrinter(void) +try: (LLVMInitializePowerPCAsmPrinter:=dll.LLVMInitializePowerPCAsmPrinter).restype, LLVMInitializePowerPCAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmPrinter(void) +try: (LLVMInitializeRISCVAsmPrinter:=dll.LLVMInitializeRISCVAsmPrinter).restype, LLVMInitializeRISCVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmPrinter(void) +try: (LLVMInitializeSparcAsmPrinter:=dll.LLVMInitializeSparcAsmPrinter).restype, LLVMInitializeSparcAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSPIRVAsmPrinter(void) +try: (LLVMInitializeSPIRVAsmPrinter:=dll.LLVMInitializeSPIRVAsmPrinter).restype, LLVMInitializeSPIRVAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmPrinter(void) +try: (LLVMInitializeSystemZAsmPrinter:=dll.LLVMInitializeSystemZAsmPrinter).restype, LLVMInitializeSystemZAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmPrinter(void) +try: (LLVMInitializeVEAsmPrinter:=dll.LLVMInitializeVEAsmPrinter).restype, LLVMInitializeVEAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmPrinter(void) +try: (LLVMInitializeWebAssemblyAsmPrinter:=dll.LLVMInitializeWebAssemblyAsmPrinter).restype, LLVMInitializeWebAssemblyAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmPrinter(void) +try: (LLVMInitializeX86AsmPrinter:=dll.LLVMInitializeX86AsmPrinter).restype, LLVMInitializeX86AsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreAsmPrinter(void) +try: (LLVMInitializeXCoreAsmPrinter:=dll.LLVMInitializeXCoreAsmPrinter).restype, LLVMInitializeXCoreAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmPrinter(void) +try: (LLVMInitializeM68kAsmPrinter:=dll.LLVMInitializeM68kAsmPrinter).restype, LLVMInitializeM68kAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmPrinter(void) +try: (LLVMInitializeXtensaAsmPrinter:=dll.LLVMInitializeXtensaAsmPrinter).restype, LLVMInitializeXtensaAsmPrinter.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64AsmParser(void) +try: (LLVMInitializeAArch64AsmParser:=dll.LLVMInitializeAArch64AsmParser).restype, LLVMInitializeAArch64AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUAsmParser(void) +try: (LLVMInitializeAMDGPUAsmParser:=dll.LLVMInitializeAMDGPUAsmParser).restype, LLVMInitializeAMDGPUAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMAsmParser(void) +try: (LLVMInitializeARMAsmParser:=dll.LLVMInitializeARMAsmParser).restype, LLVMInitializeARMAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRAsmParser(void) +try: (LLVMInitializeAVRAsmParser:=dll.LLVMInitializeAVRAsmParser).restype, LLVMInitializeAVRAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFAsmParser(void) +try: (LLVMInitializeBPFAsmParser:=dll.LLVMInitializeBPFAsmParser).restype, LLVMInitializeBPFAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonAsmParser(void) +try: (LLVMInitializeHexagonAsmParser:=dll.LLVMInitializeHexagonAsmParser).restype, LLVMInitializeHexagonAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiAsmParser(void) +try: (LLVMInitializeLanaiAsmParser:=dll.LLVMInitializeLanaiAsmParser).restype, LLVMInitializeLanaiAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchAsmParser(void) +try: (LLVMInitializeLoongArchAsmParser:=dll.LLVMInitializeLoongArchAsmParser).restype, LLVMInitializeLoongArchAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsAsmParser(void) +try: (LLVMInitializeMipsAsmParser:=dll.LLVMInitializeMipsAsmParser).restype, LLVMInitializeMipsAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430AsmParser(void) +try: (LLVMInitializeMSP430AsmParser:=dll.LLVMInitializeMSP430AsmParser).restype, LLVMInitializeMSP430AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCAsmParser(void) +try: (LLVMInitializePowerPCAsmParser:=dll.LLVMInitializePowerPCAsmParser).restype, LLVMInitializePowerPCAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVAsmParser(void) +try: (LLVMInitializeRISCVAsmParser:=dll.LLVMInitializeRISCVAsmParser).restype, LLVMInitializeRISCVAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcAsmParser(void) +try: (LLVMInitializeSparcAsmParser:=dll.LLVMInitializeSparcAsmParser).restype, LLVMInitializeSparcAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZAsmParser(void) +try: (LLVMInitializeSystemZAsmParser:=dll.LLVMInitializeSystemZAsmParser).restype, LLVMInitializeSystemZAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEAsmParser(void) +try: (LLVMInitializeVEAsmParser:=dll.LLVMInitializeVEAsmParser).restype, LLVMInitializeVEAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyAsmParser(void) +try: (LLVMInitializeWebAssemblyAsmParser:=dll.LLVMInitializeWebAssemblyAsmParser).restype, LLVMInitializeWebAssemblyAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86AsmParser(void) +try: (LLVMInitializeX86AsmParser:=dll.LLVMInitializeX86AsmParser).restype, LLVMInitializeX86AsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kAsmParser(void) +try: (LLVMInitializeM68kAsmParser:=dll.LLVMInitializeM68kAsmParser).restype, LLVMInitializeM68kAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaAsmParser(void) +try: (LLVMInitializeXtensaAsmParser:=dll.LLVMInitializeXtensaAsmParser).restype, LLVMInitializeXtensaAsmParser.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAArch64Disassembler(void) +try: (LLVMInitializeAArch64Disassembler:=dll.LLVMInitializeAArch64Disassembler).restype, LLVMInitializeAArch64Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAMDGPUDisassembler(void) +try: (LLVMInitializeAMDGPUDisassembler:=dll.LLVMInitializeAMDGPUDisassembler).restype, LLVMInitializeAMDGPUDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeARMDisassembler(void) +try: (LLVMInitializeARMDisassembler:=dll.LLVMInitializeARMDisassembler).restype, LLVMInitializeARMDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeAVRDisassembler(void) +try: (LLVMInitializeAVRDisassembler:=dll.LLVMInitializeAVRDisassembler).restype, LLVMInitializeAVRDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeBPFDisassembler(void) +try: (LLVMInitializeBPFDisassembler:=dll.LLVMInitializeBPFDisassembler).restype, LLVMInitializeBPFDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeHexagonDisassembler(void) +try: (LLVMInitializeHexagonDisassembler:=dll.LLVMInitializeHexagonDisassembler).restype, LLVMInitializeHexagonDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLanaiDisassembler(void) +try: (LLVMInitializeLanaiDisassembler:=dll.LLVMInitializeLanaiDisassembler).restype, LLVMInitializeLanaiDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeLoongArchDisassembler(void) +try: (LLVMInitializeLoongArchDisassembler:=dll.LLVMInitializeLoongArchDisassembler).restype, LLVMInitializeLoongArchDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMipsDisassembler(void) +try: (LLVMInitializeMipsDisassembler:=dll.LLVMInitializeMipsDisassembler).restype, LLVMInitializeMipsDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeMSP430Disassembler(void) +try: (LLVMInitializeMSP430Disassembler:=dll.LLVMInitializeMSP430Disassembler).restype, LLVMInitializeMSP430Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializePowerPCDisassembler(void) +try: (LLVMInitializePowerPCDisassembler:=dll.LLVMInitializePowerPCDisassembler).restype, LLVMInitializePowerPCDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeRISCVDisassembler(void) +try: (LLVMInitializeRISCVDisassembler:=dll.LLVMInitializeRISCVDisassembler).restype, LLVMInitializeRISCVDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSparcDisassembler(void) +try: (LLVMInitializeSparcDisassembler:=dll.LLVMInitializeSparcDisassembler).restype, LLVMInitializeSparcDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeSystemZDisassembler(void) +try: (LLVMInitializeSystemZDisassembler:=dll.LLVMInitializeSystemZDisassembler).restype, LLVMInitializeSystemZDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeVEDisassembler(void) +try: (LLVMInitializeVEDisassembler:=dll.LLVMInitializeVEDisassembler).restype, LLVMInitializeVEDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeWebAssemblyDisassembler(void) +try: (LLVMInitializeWebAssemblyDisassembler:=dll.LLVMInitializeWebAssemblyDisassembler).restype, LLVMInitializeWebAssemblyDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeX86Disassembler(void) +try: (LLVMInitializeX86Disassembler:=dll.LLVMInitializeX86Disassembler).restype, LLVMInitializeX86Disassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXCoreDisassembler(void) +try: (LLVMInitializeXCoreDisassembler:=dll.LLVMInitializeXCoreDisassembler).restype, LLVMInitializeXCoreDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeM68kDisassembler(void) +try: (LLVMInitializeM68kDisassembler:=dll.LLVMInitializeM68kDisassembler).restype, LLVMInitializeM68kDisassembler.argtypes = None, [] +except AttributeError: pass + +# void LLVMInitializeXtensaDisassembler(void) +try: (LLVMInitializeXtensaDisassembler:=dll.LLVMInitializeXtensaDisassembler).restype, LLVMInitializeXtensaDisassembler.argtypes = None, [] +except AttributeError: pass + +# LLVMTargetDataRef LLVMGetModuleDataLayout(LLVMModuleRef M) +try: (LLVMGetModuleDataLayout:=dll.LLVMGetModuleDataLayout).restype, LLVMGetModuleDataLayout.argtypes = LLVMTargetDataRef, [LLVMModuleRef] +except AttributeError: pass + +# void LLVMSetModuleDataLayout(LLVMModuleRef M, LLVMTargetDataRef DL) +try: (LLVMSetModuleDataLayout:=dll.LLVMSetModuleDataLayout).restype, LLVMSetModuleDataLayout.argtypes = None, [LLVMModuleRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) +try: (LLVMCreateTargetData:=dll.LLVMCreateTargetData).restype, LLVMCreateTargetData.argtypes = LLVMTargetDataRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMDisposeTargetData(LLVMTargetDataRef TD) +try: (LLVMDisposeTargetData:=dll.LLVMDisposeTargetData).restype, LLVMDisposeTargetData.argtypes = None, [LLVMTargetDataRef] +except AttributeError: pass + +# void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI, LLVMPassManagerRef PM) +try: (LLVMAddTargetLibraryInfo:=dll.LLVMAddTargetLibraryInfo).restype, LLVMAddTargetLibraryInfo.argtypes = None, [LLVMTargetLibraryInfoRef, LLVMPassManagerRef] +except AttributeError: pass + +# char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) +try: (LLVMCopyStringRepOfTargetData:=dll.LLVMCopyStringRepOfTargetData).restype, LLVMCopyStringRepOfTargetData.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetDataRef] +except AttributeError: pass + +# enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD) +try: (LLVMByteOrder:=dll.LLVMByteOrder).restype, LLVMByteOrder.argtypes = enum_LLVMByteOrdering, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSize(LLVMTargetDataRef TD) +try: (LLVMPointerSize:=dll.LLVMPointerSize).restype, LLVMPointerSize.argtypes = ctypes.c_uint32, [LLVMTargetDataRef] +except AttributeError: pass + +# unsigned int LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMPointerSizeForAS:=dll.LLVMPointerSizeForAS).restype, LLVMPointerSizeForAS.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD) +try: (LLVMIntPtrType:=dll.LLVMIntPtrType).restype, LLVMIntPtrType.argtypes = LLVMTypeRef, [LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForAS:=dll.LLVMIntPtrTypeForAS).restype, LLVMIntPtrTypeForAS.argtypes = LLVMTypeRef, [LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) +try: (LLVMIntPtrTypeInContext:=dll.LLVMIntPtrTypeInContext).restype, LLVMIntPtrTypeInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef] +except AttributeError: pass + +# LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRef TD, unsigned int AS) +try: (LLVMIntPtrTypeForASInContext:=dll.LLVMIntPtrTypeForASInContext).restype, LLVMIntPtrTypeForASInContext.argtypes = LLVMTypeRef, [LLVMContextRef, LLVMTargetDataRef, ctypes.c_uint32] +except AttributeError: pass + +# unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMSizeOfTypeInBits:=dll.LLVMSizeOfTypeInBits).restype, LLVMSizeOfTypeInBits.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMStoreSizeOfType:=dll.LLVMStoreSizeOfType).restype, LLVMStoreSizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABISizeOfType:=dll.LLVMABISizeOfType).restype, LLVMABISizeOfType.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMABIAlignmentOfType:=dll.LLVMABIAlignmentOfType).restype, LLVMABIAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMCallFrameAlignmentOfType:=dll.LLVMCallFrameAlignmentOfType).restype, LLVMCallFrameAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) +try: (LLVMPreferredAlignmentOfType:=dll.LLVMPreferredAlignmentOfType).restype, LLVMPreferredAlignmentOfType.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef] +except AttributeError: pass + +# unsigned int LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD, LLVMValueRef GlobalVar) +try: (LLVMPreferredAlignmentOfGlobal:=dll.LLVMPreferredAlignmentOfGlobal).restype, LLVMPreferredAlignmentOfGlobal.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMValueRef] +except AttributeError: pass + +# unsigned int LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned long long Offset) +try: (LLVMElementAtOffset:=dll.LLVMElementAtOffset).restype, LLVMElementAtOffset.argtypes = ctypes.c_uint32, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint64] +except AttributeError: pass + +# unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD, LLVMTypeRef StructTy, unsigned int Element) +try: (LLVMOffsetOfElement:=dll.LLVMOffsetOfElement).restype, LLVMOffsetOfElement.argtypes = ctypes.c_uint64, [LLVMTargetDataRef, LLVMTypeRef, ctypes.c_uint32] +except AttributeError: pass + +# LLVMTargetRef LLVMGetFirstTarget(void) +try: (LLVMGetFirstTarget:=dll.LLVMGetFirstTarget).restype, LLVMGetFirstTarget.argtypes = LLVMTargetRef, [] +except AttributeError: pass + +# LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T) +try: (LLVMGetNextTarget:=dll.LLVMGetNextTarget).restype, LLVMGetNextTarget.argtypes = LLVMTargetRef, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetFromName(const char *Name) +try: (LLVMGetTargetFromName:=dll.LLVMGetTargetFromName).restype, LLVMGetTargetFromName.argtypes = LLVMTargetRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBool LLVMGetTargetFromTriple(const char *Triple, LLVMTargetRef *T, char **ErrorMessage) +try: (LLVMGetTargetFromTriple:=dll.LLVMGetTargetFromTriple).restype, LLVMGetTargetFromTriple.argtypes = LLVMBool, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(LLVMTargetRef), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# const char *LLVMGetTargetName(LLVMTargetRef T) +try: (LLVMGetTargetName:=dll.LLVMGetTargetName).restype, LLVMGetTargetName.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# const char *LLVMGetTargetDescription(LLVMTargetRef T) +try: (LLVMGetTargetDescription:=dll.LLVMGetTargetDescription).restype, LLVMGetTargetDescription.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasJIT(LLVMTargetRef T) +try: (LLVMTargetHasJIT:=dll.LLVMTargetHasJIT).restype, LLVMTargetHasJIT.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T) +try: (LLVMTargetHasTargetMachine:=dll.LLVMTargetHasTargetMachine).restype, LLVMTargetHasTargetMachine.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T) +try: (LLVMTargetHasAsmBackend:=dll.LLVMTargetHasAsmBackend).restype, LLVMTargetHasAsmBackend.argtypes = LLVMBool, [LLVMTargetRef] +except AttributeError: pass + +# LLVMTargetMachineOptionsRef LLVMCreateTargetMachineOptions(void) +try: (LLVMCreateTargetMachineOptions:=dll.LLVMCreateTargetMachineOptions).restype, LLVMCreateTargetMachineOptions.argtypes = LLVMTargetMachineOptionsRef, [] +except AttributeError: pass + +# void LLVMDisposeTargetMachineOptions(LLVMTargetMachineOptionsRef Options) +try: (LLVMDisposeTargetMachineOptions:=dll.LLVMDisposeTargetMachineOptions).restype, LLVMDisposeTargetMachineOptions.argtypes = None, [LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCPU(LLVMTargetMachineOptionsRef Options, const char *CPU) +try: (LLVMTargetMachineOptionsSetCPU:=dll.LLVMTargetMachineOptionsSetCPU).restype, LLVMTargetMachineOptionsSetCPU.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetFeatures(LLVMTargetMachineOptionsRef Options, const char *Features) +try: (LLVMTargetMachineOptionsSetFeatures:=dll.LLVMTargetMachineOptionsSetFeatures).restype, LLVMTargetMachineOptionsSetFeatures.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetABI(LLVMTargetMachineOptionsRef Options, const char *ABI) +try: (LLVMTargetMachineOptionsSetABI:=dll.LLVMTargetMachineOptionsSetABI).restype, LLVMTargetMachineOptionsSetABI.argtypes = None, [LLVMTargetMachineOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeGenOptLevel(LLVMTargetMachineOptionsRef Options, LLVMCodeGenOptLevel Level) +try: (LLVMTargetMachineOptionsSetCodeGenOptLevel:=dll.LLVMTargetMachineOptionsSetCodeGenOptLevel).restype, LLVMTargetMachineOptionsSetCodeGenOptLevel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeGenOptLevel] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetRelocMode(LLVMTargetMachineOptionsRef Options, LLVMRelocMode Reloc) +try: (LLVMTargetMachineOptionsSetRelocMode:=dll.LLVMTargetMachineOptionsSetRelocMode).restype, LLVMTargetMachineOptionsSetRelocMode.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMRelocMode] +except AttributeError: pass + +# void LLVMTargetMachineOptionsSetCodeModel(LLVMTargetMachineOptionsRef Options, LLVMCodeModel CodeModel) +try: (LLVMTargetMachineOptionsSetCodeModel:=dll.LLVMTargetMachineOptionsSetCodeModel).restype, LLVMTargetMachineOptionsSetCodeModel.argtypes = None, [LLVMTargetMachineOptionsRef, LLVMCodeModel] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachineWithOptions(LLVMTargetRef T, const char *Triple, LLVMTargetMachineOptionsRef Options) +try: (LLVMCreateTargetMachineWithOptions:=dll.LLVMCreateTargetMachineWithOptions).restype, LLVMCreateTargetMachineWithOptions.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineOptionsRef] +except AttributeError: pass + +# LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, const char *Triple, const char *CPU, const char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel) +try: (LLVMCreateTargetMachine:=dll.LLVMCreateTargetMachine).restype, LLVMCreateTargetMachine.argtypes = LLVMTargetMachineRef, [LLVMTargetRef, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), LLVMCodeGenOptLevel, LLVMRelocMode, LLVMCodeModel] +except AttributeError: pass + +# void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) +try: (LLVMDisposeTargetMachine:=dll.LLVMDisposeTargetMachine).restype, LLVMDisposeTargetMachine.argtypes = None, [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTarget:=dll.LLVMGetTargetMachineTarget).restype, LLVMGetTargetMachineTarget.argtypes = LLVMTargetRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineTriple(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineTriple:=dll.LLVMGetTargetMachineTriple).restype, LLVMGetTargetMachineTriple.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineCPU:=dll.LLVMGetTargetMachineCPU).restype, LLVMGetTargetMachineCPU.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T) +try: (LLVMGetTargetMachineFeatureString:=dll.LLVMGetTargetMachineFeatureString).restype, LLVMGetTargetMachineFeatureString.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTargetMachineRef] +except AttributeError: pass + +# LLVMTargetDataRef LLVMCreateTargetDataLayout(LLVMTargetMachineRef T) +try: (LLVMCreateTargetDataLayout:=dll.LLVMCreateTargetDataLayout).restype, LLVMCreateTargetDataLayout.argtypes = LLVMTargetDataRef, [LLVMTargetMachineRef] +except AttributeError: pass + +# void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T, LLVMBool VerboseAsm) +try: (LLVMSetTargetMachineAsmVerbosity:=dll.LLVMSetTargetMachineAsmVerbosity).restype, LLVMSetTargetMachineAsmVerbosity.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineFastISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineFastISel:=dll.LLVMSetTargetMachineFastISel).restype, LLVMSetTargetMachineFastISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISel(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineGlobalISel:=dll.LLVMSetTargetMachineGlobalISel).restype, LLVMSetTargetMachineGlobalISel.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# void LLVMSetTargetMachineGlobalISelAbort(LLVMTargetMachineRef T, LLVMGlobalISelAbortMode Mode) +try: (LLVMSetTargetMachineGlobalISelAbort:=dll.LLVMSetTargetMachineGlobalISelAbort).restype, LLVMSetTargetMachineGlobalISelAbort.argtypes = None, [LLVMTargetMachineRef, LLVMGlobalISelAbortMode] +except AttributeError: pass + +# void LLVMSetTargetMachineMachineOutliner(LLVMTargetMachineRef T, LLVMBool Enable) +try: (LLVMSetTargetMachineMachineOutliner:=dll.LLVMSetTargetMachineMachineOutliner).restype, LLVMSetTargetMachineMachineOutliner.argtypes = None, [LLVMTargetMachineRef, LLVMBool] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M, const char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage) +try: (LLVMTargetMachineEmitToFile:=dll.LLVMTargetMachineEmitToFile).restype, LLVMTargetMachineEmitToFile.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMModuleRef M, LLVMCodeGenFileType codegen, char **ErrorMessage, LLVMMemoryBufferRef *OutMemBuf) +try: (LLVMTargetMachineEmitToMemoryBuffer:=dll.LLVMTargetMachineEmitToMemoryBuffer).restype, LLVMTargetMachineEmitToMemoryBuffer.argtypes = LLVMBool, [LLVMTargetMachineRef, LLVMModuleRef, LLVMCodeGenFileType, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(LLVMMemoryBufferRef)] +except AttributeError: pass + +# char *LLVMGetDefaultTargetTriple(void) +try: (LLVMGetDefaultTargetTriple:=dll.LLVMGetDefaultTargetTriple).restype, LLVMGetDefaultTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMNormalizeTargetTriple(const char *triple) +try: (LLVMNormalizeTargetTriple:=dll.LLVMNormalizeTargetTriple).restype, LLVMNormalizeTargetTriple.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *LLVMGetHostCPUName(void) +try: (LLVMGetHostCPUName:=dll.LLVMGetHostCPUName).restype, LLVMGetHostCPUName.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# char *LLVMGetHostCPUFeatures(void) +try: (LLVMGetHostCPUFeatures:=dll.LLVMGetHostCPUFeatures).restype, LLVMGetHostCPUFeatures.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) +try: (LLVMAddAnalysisPasses:=dll.LLVMAddAnalysisPasses).restype, LLVMAddAnalysisPasses.argtypes = None, [LLVMTargetMachineRef, LLVMPassManagerRef] +except AttributeError: pass + +class struct_LLVMOpaquePassBuilderOptions(Struct): pass LLVMPassBuilderOptionsRef = ctypes.POINTER(struct_LLVMOpaquePassBuilderOptions) -try: - LLVMRunPasses = _libraries['llvm'].LLVMRunPasses - LLVMRunPasses.restype = LLVMErrorRef - LLVMRunPasses.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineRef, LLVMPassBuilderOptionsRef] -except AttributeError: - pass -try: - LLVMCreatePassBuilderOptions = _libraries['llvm'].LLVMCreatePassBuilderOptions - LLVMCreatePassBuilderOptions.restype = LLVMPassBuilderOptionsRef - LLVMCreatePassBuilderOptions.argtypes = [] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetVerifyEach = _libraries['llvm'].LLVMPassBuilderOptionsSetVerifyEach - LLVMPassBuilderOptionsSetVerifyEach.restype = None - LLVMPassBuilderOptionsSetVerifyEach.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetDebugLogging = _libraries['llvm'].LLVMPassBuilderOptionsSetDebugLogging - LLVMPassBuilderOptionsSetDebugLogging.restype = None - LLVMPassBuilderOptionsSetDebugLogging.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLoopInterleaving = _libraries['llvm'].LLVMPassBuilderOptionsSetLoopInterleaving - LLVMPassBuilderOptionsSetLoopInterleaving.restype = None - LLVMPassBuilderOptionsSetLoopInterleaving.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLoopVectorization = _libraries['llvm'].LLVMPassBuilderOptionsSetLoopVectorization - LLVMPassBuilderOptionsSetLoopVectorization.restype = None - LLVMPassBuilderOptionsSetLoopVectorization.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetSLPVectorization = _libraries['llvm'].LLVMPassBuilderOptionsSetSLPVectorization - LLVMPassBuilderOptionsSetSLPVectorization.restype = None - LLVMPassBuilderOptionsSetSLPVectorization.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLoopUnrolling = _libraries['llvm'].LLVMPassBuilderOptionsSetLoopUnrolling - LLVMPassBuilderOptionsSetLoopUnrolling.restype = None - LLVMPassBuilderOptionsSetLoopUnrolling.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll = _libraries['llvm'].LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll - LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll.restype = None - LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLicmMssaOptCap = _libraries['llvm'].LLVMPassBuilderOptionsSetLicmMssaOptCap - LLVMPassBuilderOptionsSetLicmMssaOptCap.restype = None - LLVMPassBuilderOptionsSetLicmMssaOptCap.argtypes = [LLVMPassBuilderOptionsRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap = _libraries['llvm'].LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap - LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap.restype = None - LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap.argtypes = [LLVMPassBuilderOptionsRef, ctypes.c_uint32] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetCallGraphProfile = _libraries['llvm'].LLVMPassBuilderOptionsSetCallGraphProfile - LLVMPassBuilderOptionsSetCallGraphProfile.restype = None - LLVMPassBuilderOptionsSetCallGraphProfile.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMPassBuilderOptionsSetMergeFunctions = _libraries['llvm'].LLVMPassBuilderOptionsSetMergeFunctions - LLVMPassBuilderOptionsSetMergeFunctions.restype = None - LLVMPassBuilderOptionsSetMergeFunctions.argtypes = [LLVMPassBuilderOptionsRef, LLVMBool] -except AttributeError: - pass -try: - LLVMDisposePassBuilderOptions = _libraries['llvm'].LLVMDisposePassBuilderOptions - LLVMDisposePassBuilderOptions.restype = None - LLVMDisposePassBuilderOptions.argtypes = [LLVMPassBuilderOptionsRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_SCALAR_H = True # macro -try: - LLVMAddAggressiveDCEPass = _libraries['llvm'].LLVMAddAggressiveDCEPass - LLVMAddAggressiveDCEPass.restype = None - LLVMAddAggressiveDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDCEPass = _libraries['llvm'].LLVMAddDCEPass - LLVMAddDCEPass.restype = None - LLVMAddDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddBitTrackingDCEPass = _libraries['llvm'].LLVMAddBitTrackingDCEPass - LLVMAddBitTrackingDCEPass.restype = None - LLVMAddBitTrackingDCEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddAlignmentFromAssumptionsPass = _libraries['llvm'].LLVMAddAlignmentFromAssumptionsPass - LLVMAddAlignmentFromAssumptionsPass.restype = None - LLVMAddAlignmentFromAssumptionsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCFGSimplificationPass = _libraries['llvm'].LLVMAddCFGSimplificationPass - LLVMAddCFGSimplificationPass.restype = None - LLVMAddCFGSimplificationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDeadStoreEliminationPass = _libraries['llvm'].LLVMAddDeadStoreEliminationPass - LLVMAddDeadStoreEliminationPass.restype = None - LLVMAddDeadStoreEliminationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarizerPass = _libraries['llvm'].LLVMAddScalarizerPass - LLVMAddScalarizerPass.restype = None - LLVMAddScalarizerPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddMergedLoadStoreMotionPass = _libraries['llvm'].LLVMAddMergedLoadStoreMotionPass - LLVMAddMergedLoadStoreMotionPass.restype = None - LLVMAddMergedLoadStoreMotionPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddGVNPass = _libraries['llvm'].LLVMAddGVNPass - LLVMAddGVNPass.restype = None - LLVMAddGVNPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddNewGVNPass = _libraries['llvm'].LLVMAddNewGVNPass - LLVMAddNewGVNPass.restype = None - LLVMAddNewGVNPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddIndVarSimplifyPass = _libraries['llvm'].LLVMAddIndVarSimplifyPass - LLVMAddIndVarSimplifyPass.restype = None - LLVMAddIndVarSimplifyPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddInstructionSimplifyPass = _libraries['llvm'].LLVMAddInstructionSimplifyPass - LLVMAddInstructionSimplifyPass.restype = None - LLVMAddInstructionSimplifyPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddJumpThreadingPass = _libraries['llvm'].LLVMAddJumpThreadingPass - LLVMAddJumpThreadingPass.restype = None - LLVMAddJumpThreadingPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLICMPass = _libraries['llvm'].LLVMAddLICMPass - LLVMAddLICMPass.restype = None - LLVMAddLICMPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopDeletionPass = _libraries['llvm'].LLVMAddLoopDeletionPass - LLVMAddLoopDeletionPass.restype = None - LLVMAddLoopDeletionPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopIdiomPass = _libraries['llvm'].LLVMAddLoopIdiomPass - LLVMAddLoopIdiomPass.restype = None - LLVMAddLoopIdiomPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopRotatePass = _libraries['llvm'].LLVMAddLoopRotatePass - LLVMAddLoopRotatePass.restype = None - LLVMAddLoopRotatePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopRerollPass = _libraries['llvm'].LLVMAddLoopRerollPass - LLVMAddLoopRerollPass.restype = None - LLVMAddLoopRerollPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopUnrollPass = _libraries['llvm'].LLVMAddLoopUnrollPass - LLVMAddLoopUnrollPass.restype = None - LLVMAddLoopUnrollPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopUnrollAndJamPass = _libraries['llvm'].LLVMAddLoopUnrollAndJamPass - LLVMAddLoopUnrollAndJamPass.restype = None - LLVMAddLoopUnrollAndJamPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLoopUnswitchPass = _libraries['llvm'].LLVMAddLoopUnswitchPass - LLVMAddLoopUnswitchPass.restype = None - LLVMAddLoopUnswitchPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLowerAtomicPass = _libraries['llvm'].LLVMAddLowerAtomicPass - LLVMAddLowerAtomicPass.restype = None - LLVMAddLowerAtomicPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddMemCpyOptPass = _libraries['llvm'].LLVMAddMemCpyOptPass - LLVMAddMemCpyOptPass.restype = None - LLVMAddMemCpyOptPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddPartiallyInlineLibCallsPass = _libraries['llvm'].LLVMAddPartiallyInlineLibCallsPass - LLVMAddPartiallyInlineLibCallsPass.restype = None - LLVMAddPartiallyInlineLibCallsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddReassociatePass = _libraries['llvm'].LLVMAddReassociatePass - LLVMAddReassociatePass.restype = None - LLVMAddReassociatePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddSCCPPass = _libraries['llvm'].LLVMAddSCCPPass - LLVMAddSCCPPass.restype = None - LLVMAddSCCPPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarReplAggregatesPass = _libraries['llvm'].LLVMAddScalarReplAggregatesPass - LLVMAddScalarReplAggregatesPass.restype = None - LLVMAddScalarReplAggregatesPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarReplAggregatesPassSSA = _libraries['llvm'].LLVMAddScalarReplAggregatesPassSSA - LLVMAddScalarReplAggregatesPassSSA.restype = None - LLVMAddScalarReplAggregatesPassSSA.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScalarReplAggregatesPassWithThreshold = _libraries['llvm'].LLVMAddScalarReplAggregatesPassWithThreshold - LLVMAddScalarReplAggregatesPassWithThreshold.restype = None - LLVMAddScalarReplAggregatesPassWithThreshold.argtypes = [LLVMPassManagerRef, ctypes.c_int32] -except AttributeError: - pass -try: - LLVMAddSimplifyLibCallsPass = _libraries['llvm'].LLVMAddSimplifyLibCallsPass - LLVMAddSimplifyLibCallsPass.restype = None - LLVMAddSimplifyLibCallsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddTailCallEliminationPass = _libraries['llvm'].LLVMAddTailCallEliminationPass - LLVMAddTailCallEliminationPass.restype = None - LLVMAddTailCallEliminationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddDemoteMemoryToRegisterPass = _libraries['llvm'].LLVMAddDemoteMemoryToRegisterPass - LLVMAddDemoteMemoryToRegisterPass.restype = None - LLVMAddDemoteMemoryToRegisterPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddVerifierPass = _libraries['llvm'].LLVMAddVerifierPass - LLVMAddVerifierPass.restype = None - LLVMAddVerifierPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddCorrelatedValuePropagationPass = _libraries['llvm'].LLVMAddCorrelatedValuePropagationPass - LLVMAddCorrelatedValuePropagationPass.restype = None - LLVMAddCorrelatedValuePropagationPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddEarlyCSEPass = _libraries['llvm'].LLVMAddEarlyCSEPass - LLVMAddEarlyCSEPass.restype = None - LLVMAddEarlyCSEPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddEarlyCSEMemSSAPass = _libraries['llvm'].LLVMAddEarlyCSEMemSSAPass - LLVMAddEarlyCSEMemSSAPass.restype = None - LLVMAddEarlyCSEMemSSAPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLowerExpectIntrinsicPass = _libraries['llvm'].LLVMAddLowerExpectIntrinsicPass - LLVMAddLowerExpectIntrinsicPass.restype = None - LLVMAddLowerExpectIntrinsicPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddLowerConstantIntrinsicsPass = _libraries['llvm'].LLVMAddLowerConstantIntrinsicsPass - LLVMAddLowerConstantIntrinsicsPass.restype = None - LLVMAddLowerConstantIntrinsicsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddTypeBasedAliasAnalysisPass = _libraries['llvm'].LLVMAddTypeBasedAliasAnalysisPass - LLVMAddTypeBasedAliasAnalysisPass.restype = None - LLVMAddTypeBasedAliasAnalysisPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddScopedNoAliasAAPass = _libraries['llvm'].LLVMAddScopedNoAliasAAPass - LLVMAddScopedNoAliasAAPass.restype = None - LLVMAddScopedNoAliasAAPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddBasicAliasAnalysisPass = _libraries['llvm'].LLVMAddBasicAliasAnalysisPass - LLVMAddBasicAliasAnalysisPass.restype = None - LLVMAddBasicAliasAnalysisPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddUnifyFunctionExitNodesPass = _libraries['llvm'].LLVMAddUnifyFunctionExitNodesPass - LLVMAddUnifyFunctionExitNodesPass.restype = None - LLVMAddUnifyFunctionExitNodesPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_UTILS_H = True # macro -try: - LLVMAddLowerSwitchPass = _libraries['llvm'].LLVMAddLowerSwitchPass - LLVMAddLowerSwitchPass.restype = None - LLVMAddLowerSwitchPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddPromoteMemoryToRegisterPass = _libraries['llvm'].LLVMAddPromoteMemoryToRegisterPass - LLVMAddPromoteMemoryToRegisterPass.restype = None - LLVMAddPromoteMemoryToRegisterPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddAddDiscriminatorsPass = _libraries['llvm'].LLVMAddAddDiscriminatorsPass - LLVMAddAddDiscriminatorsPass.restype = None - LLVMAddAddDiscriminatorsPass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_TRANSFORMS_VECTORIZE_H = True # macro -try: - LLVMAddLoopVectorizePass = _libraries['llvm'].LLVMAddLoopVectorizePass - LLVMAddLoopVectorizePass.restype = None - LLVMAddLoopVectorizePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -try: - LLVMAddSLPVectorizePass = _libraries['llvm'].LLVMAddSLPVectorizePass - LLVMAddSLPVectorizePass.restype = None - LLVMAddSLPVectorizePass.argtypes = [LLVMPassManagerRef] -except AttributeError: - pass -LLVM_C_LTO_H = True # macro -LTO_API_VERSION = 29 # macro -lto_bool_t = ctypes.c_bool +# LLVMErrorRef LLVMRunPasses(LLVMModuleRef M, const char *Passes, LLVMTargetMachineRef TM, LLVMPassBuilderOptionsRef Options) +try: (LLVMRunPasses:=dll.LLVMRunPasses).restype, LLVMRunPasses.argtypes = LLVMErrorRef, [LLVMModuleRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineRef, LLVMPassBuilderOptionsRef] +except AttributeError: pass -# values for enumeration 'c__EA_lto_symbol_attributes' -c__EA_lto_symbol_attributes__enumvalues = { - 31: 'LTO_SYMBOL_ALIGNMENT_MASK', - 224: 'LTO_SYMBOL_PERMISSIONS_MASK', - 160: 'LTO_SYMBOL_PERMISSIONS_CODE', - 192: 'LTO_SYMBOL_PERMISSIONS_DATA', - 128: 'LTO_SYMBOL_PERMISSIONS_RODATA', - 1792: 'LTO_SYMBOL_DEFINITION_MASK', - 256: 'LTO_SYMBOL_DEFINITION_REGULAR', - 512: 'LTO_SYMBOL_DEFINITION_TENTATIVE', - 768: 'LTO_SYMBOL_DEFINITION_WEAK', - 1024: 'LTO_SYMBOL_DEFINITION_UNDEFINED', - 1280: 'LTO_SYMBOL_DEFINITION_WEAKUNDEF', - 14336: 'LTO_SYMBOL_SCOPE_MASK', - 2048: 'LTO_SYMBOL_SCOPE_INTERNAL', - 4096: 'LTO_SYMBOL_SCOPE_HIDDEN', - 8192: 'LTO_SYMBOL_SCOPE_PROTECTED', - 6144: 'LTO_SYMBOL_SCOPE_DEFAULT', - 10240: 'LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN', - 16384: 'LTO_SYMBOL_COMDAT', - 32768: 'LTO_SYMBOL_ALIAS', -} -LTO_SYMBOL_ALIGNMENT_MASK = 31 -LTO_SYMBOL_PERMISSIONS_MASK = 224 -LTO_SYMBOL_PERMISSIONS_CODE = 160 -LTO_SYMBOL_PERMISSIONS_DATA = 192 -LTO_SYMBOL_PERMISSIONS_RODATA = 128 -LTO_SYMBOL_DEFINITION_MASK = 1792 -LTO_SYMBOL_DEFINITION_REGULAR = 256 -LTO_SYMBOL_DEFINITION_TENTATIVE = 512 -LTO_SYMBOL_DEFINITION_WEAK = 768 -LTO_SYMBOL_DEFINITION_UNDEFINED = 1024 -LTO_SYMBOL_DEFINITION_WEAKUNDEF = 1280 -LTO_SYMBOL_SCOPE_MASK = 14336 -LTO_SYMBOL_SCOPE_INTERNAL = 2048 -LTO_SYMBOL_SCOPE_HIDDEN = 4096 -LTO_SYMBOL_SCOPE_PROTECTED = 8192 -LTO_SYMBOL_SCOPE_DEFAULT = 6144 -LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN = 10240 -LTO_SYMBOL_COMDAT = 16384 -LTO_SYMBOL_ALIAS = 32768 -c__EA_lto_symbol_attributes = ctypes.c_uint32 # enum -lto_symbol_attributes = c__EA_lto_symbol_attributes -lto_symbol_attributes__enumvalues = c__EA_lto_symbol_attributes__enumvalues +# LLVMErrorRef LLVMRunPassesOnFunction(LLVMValueRef F, const char *Passes, LLVMTargetMachineRef TM, LLVMPassBuilderOptionsRef Options) +try: (LLVMRunPassesOnFunction:=dll.LLVMRunPassesOnFunction).restype, LLVMRunPassesOnFunction.argtypes = LLVMErrorRef, [LLVMValueRef, ctypes.POINTER(ctypes.c_char), LLVMTargetMachineRef, LLVMPassBuilderOptionsRef] +except AttributeError: pass -# values for enumeration 'c__EA_lto_debug_model' -c__EA_lto_debug_model__enumvalues = { - 0: 'LTO_DEBUG_MODEL_NONE', - 1: 'LTO_DEBUG_MODEL_DWARF', -} -LTO_DEBUG_MODEL_NONE = 0 -LTO_DEBUG_MODEL_DWARF = 1 -c__EA_lto_debug_model = ctypes.c_uint32 # enum -lto_debug_model = c__EA_lto_debug_model -lto_debug_model__enumvalues = c__EA_lto_debug_model__enumvalues +# LLVMPassBuilderOptionsRef LLVMCreatePassBuilderOptions(void) +try: (LLVMCreatePassBuilderOptions:=dll.LLVMCreatePassBuilderOptions).restype, LLVMCreatePassBuilderOptions.argtypes = LLVMPassBuilderOptionsRef, [] +except AttributeError: pass -# values for enumeration 'c__EA_lto_codegen_model' -c__EA_lto_codegen_model__enumvalues = { - 0: 'LTO_CODEGEN_PIC_MODEL_STATIC', - 1: 'LTO_CODEGEN_PIC_MODEL_DYNAMIC', - 2: 'LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC', - 3: 'LTO_CODEGEN_PIC_MODEL_DEFAULT', -} -LTO_CODEGEN_PIC_MODEL_STATIC = 0 -LTO_CODEGEN_PIC_MODEL_DYNAMIC = 1 -LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC = 2 -LTO_CODEGEN_PIC_MODEL_DEFAULT = 3 -c__EA_lto_codegen_model = ctypes.c_uint32 # enum -lto_codegen_model = c__EA_lto_codegen_model -lto_codegen_model__enumvalues = c__EA_lto_codegen_model__enumvalues -class struct_LLVMOpaqueLTOModule(Structure): - pass +# void LLVMPassBuilderOptionsSetVerifyEach(LLVMPassBuilderOptionsRef Options, LLVMBool VerifyEach) +try: (LLVMPassBuilderOptionsSetVerifyEach:=dll.LLVMPassBuilderOptionsSetVerifyEach).restype, LLVMPassBuilderOptionsSetVerifyEach.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass -lto_module_t = ctypes.POINTER(struct_LLVMOpaqueLTOModule) -class struct_LLVMOpaqueLTOCodeGenerator(Structure): - pass +# void LLVMPassBuilderOptionsSetDebugLogging(LLVMPassBuilderOptionsRef Options, LLVMBool DebugLogging) +try: (LLVMPassBuilderOptionsSetDebugLogging:=dll.LLVMPassBuilderOptionsSetDebugLogging).restype, LLVMPassBuilderOptionsSetDebugLogging.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass -lto_code_gen_t = ctypes.POINTER(struct_LLVMOpaqueLTOCodeGenerator) -class struct_LLVMOpaqueThinLTOCodeGenerator(Structure): - pass +# void LLVMPassBuilderOptionsSetAAPipeline(LLVMPassBuilderOptionsRef Options, const char *AAPipeline) +try: (LLVMPassBuilderOptionsSetAAPipeline:=dll.LLVMPassBuilderOptionsSetAAPipeline).restype, LLVMPassBuilderOptionsSetAAPipeline.argtypes = None, [LLVMPassBuilderOptionsRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -thinlto_code_gen_t = ctypes.POINTER(struct_LLVMOpaqueThinLTOCodeGenerator) -try: - lto_get_version = _libraries['llvm'].lto_get_version - lto_get_version.restype = ctypes.POINTER(ctypes.c_char) - lto_get_version.argtypes = [] -except AttributeError: - pass -try: - lto_get_error_message = _libraries['llvm'].lto_get_error_message - lto_get_error_message.restype = ctypes.POINTER(ctypes.c_char) - lto_get_error_message.argtypes = [] -except AttributeError: - pass -try: - lto_module_is_object_file = _libraries['llvm'].lto_module_is_object_file - lto_module_is_object_file.restype = lto_bool_t - lto_module_is_object_file.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_is_object_file_for_target = _libraries['llvm'].lto_module_is_object_file_for_target - lto_module_is_object_file_for_target.restype = lto_bool_t - lto_module_is_object_file_for_target.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_has_objc_category = _libraries['llvm'].lto_module_has_objc_category - lto_module_has_objc_category.restype = lto_bool_t - lto_module_has_objc_category.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - lto_module_is_object_file_in_memory = _libraries['llvm'].lto_module_is_object_file_in_memory - lto_module_is_object_file_in_memory.restype = lto_bool_t - lto_module_is_object_file_in_memory.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - lto_module_is_object_file_in_memory_for_target = _libraries['llvm'].lto_module_is_object_file_in_memory_for_target - lto_module_is_object_file_in_memory_for_target.restype = lto_bool_t - lto_module_is_object_file_in_memory_for_target.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create = _libraries['llvm'].lto_module_create - lto_module_create.restype = lto_module_t - lto_module_create.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create_from_memory = _libraries['llvm'].lto_module_create_from_memory - lto_module_create_from_memory.restype = lto_module_t - lto_module_create_from_memory.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - lto_module_create_from_memory_with_path = _libraries['llvm'].lto_module_create_from_memory_with_path - lto_module_create_from_memory_with_path.restype = lto_module_t - lto_module_create_from_memory_with_path.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create_in_local_context = _libraries['llvm'].lto_module_create_in_local_context - lto_module_create_in_local_context.restype = lto_module_t - lto_module_create_in_local_context.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_create_in_codegen_context = _libraries['llvm'].lto_module_create_in_codegen_context - lto_module_create_in_codegen_context.restype = lto_module_t - lto_module_create_in_codegen_context.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char), lto_code_gen_t] -except AttributeError: - pass -try: - lto_module_create_from_fd = _libraries['llvm'].lto_module_create_from_fd - lto_module_create_from_fd.restype = lto_module_t - lto_module_create_from_fd.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -off_t = ctypes.c_int64 -try: - lto_module_create_from_fd_at_offset = _libraries['llvm'].lto_module_create_from_fd_at_offset - lto_module_create_from_fd_at_offset.restype = lto_module_t - lto_module_create_from_fd_at_offset.argtypes = [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t, size_t, off_t] -except AttributeError: - pass -try: - lto_module_dispose = _libraries['llvm'].lto_module_dispose - lto_module_dispose.restype = None - lto_module_dispose.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_get_target_triple = _libraries['llvm'].lto_module_get_target_triple - lto_module_get_target_triple.restype = ctypes.POINTER(ctypes.c_char) - lto_module_get_target_triple.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_set_target_triple = _libraries['llvm'].lto_module_set_target_triple - lto_module_set_target_triple.restype = None - lto_module_set_target_triple.argtypes = [lto_module_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_module_get_num_symbols = _libraries['llvm'].lto_module_get_num_symbols - lto_module_get_num_symbols.restype = ctypes.c_uint32 - lto_module_get_num_symbols.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_get_symbol_name = _libraries['llvm'].lto_module_get_symbol_name - lto_module_get_symbol_name.restype = ctypes.POINTER(ctypes.c_char) - lto_module_get_symbol_name.argtypes = [lto_module_t, ctypes.c_uint32] -except AttributeError: - pass -try: - lto_module_get_symbol_attribute = _libraries['llvm'].lto_module_get_symbol_attribute - lto_module_get_symbol_attribute.restype = lto_symbol_attributes - lto_module_get_symbol_attribute.argtypes = [lto_module_t, ctypes.c_uint32] -except AttributeError: - pass -try: - lto_module_get_linkeropts = _libraries['llvm'].lto_module_get_linkeropts - lto_module_get_linkeropts.restype = ctypes.POINTER(ctypes.c_char) - lto_module_get_linkeropts.argtypes = [lto_module_t] -except AttributeError: - pass -try: - lto_module_get_macho_cputype = _libraries['llvm'].lto_module_get_macho_cputype - lto_module_get_macho_cputype.restype = lto_bool_t - lto_module_get_macho_cputype.argtypes = [lto_module_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - lto_module_has_ctor_dtor = _libraries['llvm'].lto_module_has_ctor_dtor - lto_module_has_ctor_dtor.restype = lto_bool_t - lto_module_has_ctor_dtor.argtypes = [lto_module_t] -except AttributeError: - pass +# void LLVMPassBuilderOptionsSetLoopInterleaving(LLVMPassBuilderOptionsRef Options, LLVMBool LoopInterleaving) +try: (LLVMPassBuilderOptionsSetLoopInterleaving:=dll.LLVMPassBuilderOptionsSetLoopInterleaving).restype, LLVMPassBuilderOptionsSetLoopInterleaving.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass -# values for enumeration 'c__EA_lto_codegen_diagnostic_severity_t' -c__EA_lto_codegen_diagnostic_severity_t__enumvalues = { - 0: 'LTO_DS_ERROR', - 1: 'LTO_DS_WARNING', - 3: 'LTO_DS_REMARK', - 2: 'LTO_DS_NOTE', -} -LTO_DS_ERROR = 0 -LTO_DS_WARNING = 1 -LTO_DS_REMARK = 3 -LTO_DS_NOTE = 2 -c__EA_lto_codegen_diagnostic_severity_t = ctypes.c_uint32 # enum -lto_codegen_diagnostic_severity_t = c__EA_lto_codegen_diagnostic_severity_t -lto_codegen_diagnostic_severity_t__enumvalues = c__EA_lto_codegen_diagnostic_severity_t__enumvalues -lto_diagnostic_handler_t = ctypes.CFUNCTYPE(None, c__EA_lto_codegen_diagnostic_severity_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)) -try: - lto_codegen_set_diagnostic_handler = _libraries['llvm'].lto_codegen_set_diagnostic_handler - lto_codegen_set_diagnostic_handler.restype = None - lto_codegen_set_diagnostic_handler.argtypes = [lto_code_gen_t, lto_diagnostic_handler_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - lto_codegen_create = _libraries['llvm'].lto_codegen_create - lto_codegen_create.restype = lto_code_gen_t - lto_codegen_create.argtypes = [] -except AttributeError: - pass -try: - lto_codegen_create_in_local_context = _libraries['llvm'].lto_codegen_create_in_local_context - lto_codegen_create_in_local_context.restype = lto_code_gen_t - lto_codegen_create_in_local_context.argtypes = [] -except AttributeError: - pass -try: - lto_codegen_dispose = _libraries['llvm'].lto_codegen_dispose - lto_codegen_dispose.restype = None - lto_codegen_dispose.argtypes = [lto_code_gen_t] -except AttributeError: - pass -try: - lto_codegen_add_module = _libraries['llvm'].lto_codegen_add_module - lto_codegen_add_module.restype = lto_bool_t - lto_codegen_add_module.argtypes = [lto_code_gen_t, lto_module_t] -except AttributeError: - pass -try: - lto_codegen_set_module = _libraries['llvm'].lto_codegen_set_module - lto_codegen_set_module.restype = None - lto_codegen_set_module.argtypes = [lto_code_gen_t, lto_module_t] -except AttributeError: - pass -try: - lto_codegen_set_debug_model = _libraries['llvm'].lto_codegen_set_debug_model - lto_codegen_set_debug_model.restype = lto_bool_t - lto_codegen_set_debug_model.argtypes = [lto_code_gen_t, lto_debug_model] -except AttributeError: - pass -try: - lto_codegen_set_pic_model = _libraries['llvm'].lto_codegen_set_pic_model - lto_codegen_set_pic_model.restype = lto_bool_t - lto_codegen_set_pic_model.argtypes = [lto_code_gen_t, lto_codegen_model] -except AttributeError: - pass -try: - lto_codegen_set_cpu = _libraries['llvm'].lto_codegen_set_cpu - lto_codegen_set_cpu.restype = None - lto_codegen_set_cpu.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_set_assembler_path = _libraries['llvm'].lto_codegen_set_assembler_path - lto_codegen_set_assembler_path.restype = None - lto_codegen_set_assembler_path.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_set_assembler_args = _libraries['llvm'].lto_codegen_set_assembler_args - lto_codegen_set_assembler_args.restype = None - lto_codegen_set_assembler_args.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_codegen_add_must_preserve_symbol = _libraries['llvm'].lto_codegen_add_must_preserve_symbol - lto_codegen_add_must_preserve_symbol.restype = None - lto_codegen_add_must_preserve_symbol.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_write_merged_modules = _libraries['llvm'].lto_codegen_write_merged_modules - lto_codegen_write_merged_modules.restype = lto_bool_t - lto_codegen_write_merged_modules.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_compile = _libraries['llvm'].lto_codegen_compile - lto_codegen_compile.restype = ctypes.POINTER(None) - lto_codegen_compile.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - lto_codegen_compile_to_file = _libraries['llvm'].lto_codegen_compile_to_file - lto_codegen_compile_to_file.restype = lto_bool_t - lto_codegen_compile_to_file.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - lto_codegen_optimize = _libraries['llvm'].lto_codegen_optimize - lto_codegen_optimize.restype = lto_bool_t - lto_codegen_optimize.argtypes = [lto_code_gen_t] -except AttributeError: - pass -try: - lto_codegen_compile_optimized = _libraries['llvm'].lto_codegen_compile_optimized - lto_codegen_compile_optimized.restype = ctypes.POINTER(None) - lto_codegen_compile_optimized.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - lto_api_version = _libraries['llvm'].lto_api_version - lto_api_version.restype = ctypes.c_uint32 - lto_api_version.argtypes = [] -except AttributeError: - pass -try: - lto_set_debug_options = _libraries['llvm'].lto_set_debug_options - lto_set_debug_options.restype = None - lto_set_debug_options.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_codegen_debug_options = _libraries['llvm'].lto_codegen_debug_options - lto_codegen_debug_options.restype = None - lto_codegen_debug_options.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_codegen_debug_options_array = _libraries['llvm'].lto_codegen_debug_options_array - lto_codegen_debug_options_array.restype = None - lto_codegen_debug_options_array.argtypes = [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_initialize_disassembler = _libraries['llvm'].lto_initialize_disassembler - lto_initialize_disassembler.restype = None - lto_initialize_disassembler.argtypes = [] -except AttributeError: - pass -try: - lto_codegen_set_should_internalize = _libraries['llvm'].lto_codegen_set_should_internalize - lto_codegen_set_should_internalize.restype = None - lto_codegen_set_should_internalize.argtypes = [lto_code_gen_t, lto_bool_t] -except AttributeError: - pass -try: - lto_codegen_set_should_embed_uselists = _libraries['llvm'].lto_codegen_set_should_embed_uselists - lto_codegen_set_should_embed_uselists.restype = None - lto_codegen_set_should_embed_uselists.argtypes = [lto_code_gen_t, lto_bool_t] -except AttributeError: - pass -class struct_LLVMOpaqueLTOInput(Structure): - pass +# void LLVMPassBuilderOptionsSetLoopVectorization(LLVMPassBuilderOptionsRef Options, LLVMBool LoopVectorization) +try: (LLVMPassBuilderOptionsSetLoopVectorization:=dll.LLVMPassBuilderOptionsSetLoopVectorization).restype, LLVMPassBuilderOptionsSetLoopVectorization.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass -lto_input_t = ctypes.POINTER(struct_LLVMOpaqueLTOInput) -try: - lto_input_create = _libraries['llvm'].lto_input_create - lto_input_create.restype = lto_input_t - lto_input_create.argtypes = [ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lto_input_dispose = _libraries['llvm'].lto_input_dispose - lto_input_dispose.restype = None - lto_input_dispose.argtypes = [lto_input_t] -except AttributeError: - pass -try: - lto_input_get_num_dependent_libraries = _libraries['llvm'].lto_input_get_num_dependent_libraries - lto_input_get_num_dependent_libraries.restype = ctypes.c_uint32 - lto_input_get_num_dependent_libraries.argtypes = [lto_input_t] -except AttributeError: - pass -try: - lto_input_get_dependent_library = _libraries['llvm'].lto_input_get_dependent_library - lto_input_get_dependent_library.restype = ctypes.POINTER(ctypes.c_char) - lto_input_get_dependent_library.argtypes = [lto_input_t, size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - lto_runtime_lib_symbols_list = _libraries['llvm'].lto_runtime_lib_symbols_list - lto_runtime_lib_symbols_list.restype = ctypes.POINTER(ctypes.POINTER(ctypes.c_char)) - lto_runtime_lib_symbols_list.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -class struct_c__SA_LTOObjectBuffer(Structure): - pass +# void LLVMPassBuilderOptionsSetSLPVectorization(LLVMPassBuilderOptionsRef Options, LLVMBool SLPVectorization) +try: (LLVMPassBuilderOptionsSetSLPVectorization:=dll.LLVMPassBuilderOptionsSetSLPVectorization).restype, LLVMPassBuilderOptionsSetSLPVectorization.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass -struct_c__SA_LTOObjectBuffer._pack_ = 1 # source:False -struct_c__SA_LTOObjectBuffer._fields_ = [ - ('Buffer', ctypes.POINTER(ctypes.c_char)), - ('Size', ctypes.c_uint64), +# void LLVMPassBuilderOptionsSetLoopUnrolling(LLVMPassBuilderOptionsRef Options, LLVMBool LoopUnrolling) +try: (LLVMPassBuilderOptionsSetLoopUnrolling:=dll.LLVMPassBuilderOptionsSetLoopUnrolling).restype, LLVMPassBuilderOptionsSetLoopUnrolling.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass + +# void LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll(LLVMPassBuilderOptionsRef Options, LLVMBool ForgetAllSCEVInLoopUnroll) +try: (LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll:=dll.LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll).restype, LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass + +# void LLVMPassBuilderOptionsSetLicmMssaOptCap(LLVMPassBuilderOptionsRef Options, unsigned int LicmMssaOptCap) +try: (LLVMPassBuilderOptionsSetLicmMssaOptCap:=dll.LLVMPassBuilderOptionsSetLicmMssaOptCap).restype, LLVMPassBuilderOptionsSetLicmMssaOptCap.argtypes = None, [LLVMPassBuilderOptionsRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap(LLVMPassBuilderOptionsRef Options, unsigned int LicmMssaNoAccForPromotionCap) +try: (LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap:=dll.LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap).restype, LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap.argtypes = None, [LLVMPassBuilderOptionsRef, ctypes.c_uint32] +except AttributeError: pass + +# void LLVMPassBuilderOptionsSetCallGraphProfile(LLVMPassBuilderOptionsRef Options, LLVMBool CallGraphProfile) +try: (LLVMPassBuilderOptionsSetCallGraphProfile:=dll.LLVMPassBuilderOptionsSetCallGraphProfile).restype, LLVMPassBuilderOptionsSetCallGraphProfile.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass + +# void LLVMPassBuilderOptionsSetMergeFunctions(LLVMPassBuilderOptionsRef Options, LLVMBool MergeFunctions) +try: (LLVMPassBuilderOptionsSetMergeFunctions:=dll.LLVMPassBuilderOptionsSetMergeFunctions).restype, LLVMPassBuilderOptionsSetMergeFunctions.argtypes = None, [LLVMPassBuilderOptionsRef, LLVMBool] +except AttributeError: pass + +# void LLVMPassBuilderOptionsSetInlinerThreshold(LLVMPassBuilderOptionsRef Options, int Threshold) +try: (LLVMPassBuilderOptionsSetInlinerThreshold:=dll.LLVMPassBuilderOptionsSetInlinerThreshold).restype, LLVMPassBuilderOptionsSetInlinerThreshold.argtypes = None, [LLVMPassBuilderOptionsRef, ctypes.c_int32] +except AttributeError: pass + +# void LLVMDisposePassBuilderOptions(LLVMPassBuilderOptionsRef Options) +try: (LLVMDisposePassBuilderOptions:=dll.LLVMDisposePassBuilderOptions).restype, LLVMDisposePassBuilderOptions.argtypes = None, [LLVMPassBuilderOptionsRef] +except AttributeError: pass + +# extern intmax_t imaxabs(intmax_t __n) __attribute__((nothrow)) __attribute__((const)) +try: (imaxabs:=dll.imaxabs).restype, imaxabs.argtypes = intmax_t, [intmax_t] +except AttributeError: pass + +# extern imaxdiv_t imaxdiv(intmax_t __numer, intmax_t __denom) __attribute__((nothrow)) __attribute__((const)) +try: (imaxdiv:=dll.imaxdiv).restype, imaxdiv.argtypes = imaxdiv_t, [intmax_t, intmax_t] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t strtoimax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoimax") __attribute__((nothrow)) +try: (strtoimax:=dll.strtoimax).restype, strtoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t strtoumax(const char *restrict __nptr, char **restrict __endptr, int __base) asm("__isoc23_strtoumax") __attribute__((nothrow)) +try: (strtoumax:=dll.strtoumax).restype, strtoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern intmax_t wcstoimax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoimax") __attribute__((nothrow)) +try: (wcstoimax:=dll.wcstoimax).restype, wcstoimax.argtypes = intmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern uintmax_t wcstoumax(const __gwchar_t *restrict __nptr, __gwchar_t **restrict __endptr, int __base) asm("__isoc23_wcstoumax") __attribute__((nothrow)) +try: (wcstoumax:=dll.wcstoumax).restype, wcstoumax.argtypes = uintmax_t, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.POINTER(ctypes.c_int32)), ctypes.c_int32] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +class llvm_blake3_chunk_state(Struct): pass +llvm_blake3_chunk_state._fields_ = [ + ('cv', (uint32_t * 8)), + ('chunk_counter', uint64_t), + ('buf', (uint8_t * 64)), + ('buf_len', uint8_t), + ('blocks_compressed', uint8_t), + ('flags', uint8_t), ] +class llvm_blake3_hasher(Struct): pass +llvm_blake3_hasher._fields_ = [ + ('key', (uint32_t * 8)), + ('chunk', llvm_blake3_chunk_state), + ('cv_stack_len', uint8_t), + ('cv_stack', (uint8_t * 1760)), +] +# const char *llvm_blake3_version(void) +try: (llvm_blake3_version:=dll.llvm_blake3_version).restype, llvm_blake3_version.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass -LTOObjectBuffer = struct_c__SA_LTOObjectBuffer -try: - thinlto_create_codegen = _libraries['llvm'].thinlto_create_codegen - thinlto_create_codegen.restype = thinlto_code_gen_t - thinlto_create_codegen.argtypes = [] -except AttributeError: - pass -try: - thinlto_codegen_dispose = _libraries['llvm'].thinlto_codegen_dispose - thinlto_codegen_dispose.restype = None - thinlto_codegen_dispose.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_codegen_add_module = _libraries['llvm'].thinlto_codegen_add_module - thinlto_codegen_add_module.restype = None - thinlto_codegen_add_module.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_process = _libraries['llvm'].thinlto_codegen_process - thinlto_codegen_process.restype = None - thinlto_codegen_process.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_module_get_num_objects = _libraries['llvm'].thinlto_module_get_num_objects - thinlto_module_get_num_objects.restype = ctypes.c_uint32 - thinlto_module_get_num_objects.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_module_get_object = _libraries['llvm'].thinlto_module_get_object - thinlto_module_get_object.restype = LTOObjectBuffer - thinlto_module_get_object.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_module_get_num_object_files = _libraries['llvm'].thinlto_module_get_num_object_files - thinlto_module_get_num_object_files.restype = ctypes.c_uint32 - thinlto_module_get_num_object_files.argtypes = [thinlto_code_gen_t] -except AttributeError: - pass -try: - thinlto_module_get_object_file = _libraries['llvm'].thinlto_module_get_object_file - thinlto_module_get_object_file.restype = ctypes.POINTER(ctypes.c_char) - thinlto_module_get_object_file.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_pic_model = _libraries['llvm'].thinlto_codegen_set_pic_model - thinlto_codegen_set_pic_model.restype = lto_bool_t - thinlto_codegen_set_pic_model.argtypes = [thinlto_code_gen_t, lto_codegen_model] -except AttributeError: - pass -try: - thinlto_codegen_set_savetemps_dir = _libraries['llvm'].thinlto_codegen_set_savetemps_dir - thinlto_codegen_set_savetemps_dir.restype = None - thinlto_codegen_set_savetemps_dir.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_set_generated_objects_dir = _libraries['llvm'].thinlto_set_generated_objects_dir - thinlto_set_generated_objects_dir.restype = None - thinlto_set_generated_objects_dir.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_codegen_set_cpu = _libraries['llvm'].thinlto_codegen_set_cpu - thinlto_codegen_set_cpu.restype = None - thinlto_codegen_set_cpu.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_codegen_disable_codegen = _libraries['llvm'].thinlto_codegen_disable_codegen - thinlto_codegen_disable_codegen.restype = None - thinlto_codegen_disable_codegen.argtypes = [thinlto_code_gen_t, lto_bool_t] -except AttributeError: - pass -try: - thinlto_codegen_set_codegen_only = _libraries['llvm'].thinlto_codegen_set_codegen_only - thinlto_codegen_set_codegen_only.restype = None - thinlto_codegen_set_codegen_only.argtypes = [thinlto_code_gen_t, lto_bool_t] -except AttributeError: - pass -try: - thinlto_debug_options = _libraries['llvm'].thinlto_debug_options - thinlto_debug_options.restype = None - thinlto_debug_options.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] -except AttributeError: - pass -try: - lto_module_is_thinlto = _libraries['llvm'].lto_module_is_thinlto - lto_module_is_thinlto.restype = lto_bool_t - lto_module_is_thinlto.argtypes = [lto_module_t] -except AttributeError: - pass -try: - thinlto_codegen_add_must_preserve_symbol = _libraries['llvm'].thinlto_codegen_add_must_preserve_symbol - thinlto_codegen_add_must_preserve_symbol.restype = None - thinlto_codegen_add_must_preserve_symbol.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_add_cross_referenced_symbol = _libraries['llvm'].thinlto_codegen_add_cross_referenced_symbol - thinlto_codegen_add_cross_referenced_symbol.restype = None - thinlto_codegen_add_cross_referenced_symbol.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_dir = _libraries['llvm'].thinlto_codegen_set_cache_dir - thinlto_codegen_set_cache_dir.restype = None - thinlto_codegen_set_cache_dir.argtypes = [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_pruning_interval = _libraries['llvm'].thinlto_codegen_set_cache_pruning_interval - thinlto_codegen_set_cache_pruning_interval.restype = None - thinlto_codegen_set_cache_pruning_interval.argtypes = [thinlto_code_gen_t, ctypes.c_int32] -except AttributeError: - pass -try: - thinlto_codegen_set_final_cache_size_relative_to_available_space = _libraries['llvm'].thinlto_codegen_set_final_cache_size_relative_to_available_space - thinlto_codegen_set_final_cache_size_relative_to_available_space.restype = None - thinlto_codegen_set_final_cache_size_relative_to_available_space.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_entry_expiration = _libraries['llvm'].thinlto_codegen_set_cache_entry_expiration - thinlto_codegen_set_cache_entry_expiration.restype = None - thinlto_codegen_set_cache_entry_expiration.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_size_bytes = _libraries['llvm'].thinlto_codegen_set_cache_size_bytes - thinlto_codegen_set_cache_size_bytes.restype = None - thinlto_codegen_set_cache_size_bytes.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_size_megabytes = _libraries['llvm'].thinlto_codegen_set_cache_size_megabytes - thinlto_codegen_set_cache_size_megabytes.restype = None - thinlto_codegen_set_cache_size_megabytes.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -try: - thinlto_codegen_set_cache_size_files = _libraries['llvm'].thinlto_codegen_set_cache_size_files - thinlto_codegen_set_cache_size_files.restype = None - thinlto_codegen_set_cache_size_files.argtypes = [thinlto_code_gen_t, ctypes.c_uint32] -except AttributeError: - pass -__all__ = \ - ['LLVMABIAlignmentOfType', 'LLVMABISizeOfType', - 'LLVMAMDGPUCSCallConv', 'LLVMAMDGPUESCallConv', - 'LLVMAMDGPUGSCallConv', 'LLVMAMDGPUHSCallConv', - 'LLVMAMDGPUKERNELCallConv', 'LLVMAMDGPULSCallConv', - 'LLVMAMDGPUPSCallConv', 'LLVMAMDGPUVSCallConv', - 'LLVMARMAAPCSCallConv', 'LLVMARMAAPCSVFPCallConv', - 'LLVMARMAPCSCallConv', 'LLVMAShr', 'LLVMAVRBUILTINCallConv', - 'LLVMAVRINTRCallConv', 'LLVMAVRSIGNALCallConv', - 'LLVMAbortProcessAction', 'LLVMAdd', - 'LLVMAddAddDiscriminatorsPass', 'LLVMAddAggressiveDCEPass', - 'LLVMAddAggressiveInstCombinerPass', 'LLVMAddAlias', - 'LLVMAddAlias2', 'LLVMAddAlignmentFromAssumptionsPass', - 'LLVMAddAlwaysInlinerPass', 'LLVMAddAnalysisPasses', - 'LLVMAddArgumentPromotionPass', 'LLVMAddAttributeAtIndex', - 'LLVMAddBasicAliasAnalysisPass', 'LLVMAddBitTrackingDCEPass', - 'LLVMAddCFGSimplificationPass', 'LLVMAddCallSiteAttribute', - 'LLVMAddCalledValuePropagationPass', 'LLVMAddCase', - 'LLVMAddClause', 'LLVMAddConstantMergePass', - 'LLVMAddCoroCleanupPass', 'LLVMAddCoroEarlyPass', - 'LLVMAddCoroElidePass', 'LLVMAddCoroSplitPass', - 'LLVMAddCorrelatedValuePropagationPass', 'LLVMAddDCEPass', - 'LLVMAddDeadArgEliminationPass', - 'LLVMAddDeadStoreEliminationPass', - 'LLVMAddDemoteMemoryToRegisterPass', 'LLVMAddDestination', - 'LLVMAddEarlyCSEMemSSAPass', 'LLVMAddEarlyCSEPass', - 'LLVMAddFunction', 'LLVMAddFunctionAttrsPass', - 'LLVMAddFunctionInliningPass', 'LLVMAddGVNPass', 'LLVMAddGlobal', - 'LLVMAddGlobalDCEPass', 'LLVMAddGlobalIFunc', - 'LLVMAddGlobalInAddressSpace', 'LLVMAddGlobalMapping', - 'LLVMAddGlobalOptimizerPass', 'LLVMAddHandler', - 'LLVMAddIPSCCPPass', 'LLVMAddIncoming', - 'LLVMAddIndVarSimplifyPass', 'LLVMAddInstructionCombiningPass', - 'LLVMAddInstructionSimplifyPass', 'LLVMAddInternalizePass', - 'LLVMAddInternalizePassWithMustPreservePredicate', - 'LLVMAddJumpThreadingPass', 'LLVMAddLICMPass', - 'LLVMAddLoopDeletionPass', 'LLVMAddLoopIdiomPass', - 'LLVMAddLoopRerollPass', 'LLVMAddLoopRotatePass', - 'LLVMAddLoopUnrollAndJamPass', 'LLVMAddLoopUnrollPass', - 'LLVMAddLoopUnswitchPass', 'LLVMAddLoopVectorizePass', - 'LLVMAddLowerAtomicPass', 'LLVMAddLowerConstantIntrinsicsPass', - 'LLVMAddLowerExpectIntrinsicPass', 'LLVMAddLowerSwitchPass', - 'LLVMAddMemCpyOptPass', 'LLVMAddMergeFunctionsPass', - 'LLVMAddMergedLoadStoreMotionPass', 'LLVMAddMetadataToInst', - 'LLVMAddModule', 'LLVMAddModuleFlag', - 'LLVMAddNamedMetadataOperand', 'LLVMAddNewGVNPass', - 'LLVMAddPartiallyInlineLibCallsPass', - 'LLVMAddPromoteMemoryToRegisterPass', 'LLVMAddPruneEHPass', - 'LLVMAddReassociatePass', 'LLVMAddSCCPPass', - 'LLVMAddSLPVectorizePass', 'LLVMAddScalarReplAggregatesPass', - 'LLVMAddScalarReplAggregatesPassSSA', - 'LLVMAddScalarReplAggregatesPassWithThreshold', - 'LLVMAddScalarizerPass', 'LLVMAddScopedNoAliasAAPass', - 'LLVMAddSimplifyLibCallsPass', 'LLVMAddStripDeadPrototypesPass', - 'LLVMAddStripSymbolsPass', 'LLVMAddSymbol', - 'LLVMAddTailCallEliminationPass', - 'LLVMAddTargetDependentFunctionAttr', 'LLVMAddTargetLibraryInfo', - 'LLVMAddTypeBasedAliasAnalysisPass', - 'LLVMAddUnifyFunctionExitNodesPass', 'LLVMAddVerifierPass', - 'LLVMAddrSpaceCast', 'LLVMAliasGetAliasee', 'LLVMAliasSetAliasee', - 'LLVMAlignOf', 'LLVMAlloca', 'LLVMAnd', - 'LLVMAnyComdatSelectionKind', 'LLVMAnyRegCallConv', - 'LLVMAppendBasicBlock', 'LLVMAppendBasicBlockInContext', - 'LLVMAppendExistingBasicBlock', 'LLVMAppendModuleInlineAsm', - 'LLVMAppendingLinkage', 'LLVMArgumentValueKind', 'LLVMArrayType', - 'LLVMArrayTypeKind', 'LLVMAssemblyFile', 'LLVMAtomicCmpXchg', - 'LLVMAtomicOrdering', 'LLVMAtomicOrderingAcquire', - 'LLVMAtomicOrderingAcquireRelease', 'LLVMAtomicOrderingMonotonic', - 'LLVMAtomicOrderingNotAtomic', 'LLVMAtomicOrderingRelease', - 'LLVMAtomicOrderingSequentiallyConsistent', - 'LLVMAtomicOrderingUnordered', 'LLVMAtomicOrdering__enumvalues', - 'LLVMAtomicRMW', 'LLVMAtomicRMWBinOp', 'LLVMAtomicRMWBinOpAdd', - 'LLVMAtomicRMWBinOpAnd', 'LLVMAtomicRMWBinOpFAdd', - 'LLVMAtomicRMWBinOpFSub', 'LLVMAtomicRMWBinOpMax', - 'LLVMAtomicRMWBinOpMin', 'LLVMAtomicRMWBinOpNand', - 'LLVMAtomicRMWBinOpOr', 'LLVMAtomicRMWBinOpSub', - 'LLVMAtomicRMWBinOpUMax', 'LLVMAtomicRMWBinOpUMin', - 'LLVMAtomicRMWBinOpXchg', 'LLVMAtomicRMWBinOpXor', - 'LLVMAtomicRMWBinOp__enumvalues', 'LLVMAttributeFunctionIndex', - 'LLVMAttributeIndex', 'LLVMAttributeRef', - 'LLVMAttributeReturnIndex', 'LLVMAvailableExternallyLinkage', - 'LLVMBFloatType', 'LLVMBFloatTypeInContext', 'LLVMBFloatTypeKind', - 'LLVMBasicBlockAsValue', 'LLVMBasicBlockRef', - 'LLVMBasicBlockValueKind', 'LLVMBigEndian', - 'LLVMBinaryCopyMemoryBuffer', 'LLVMBinaryGetType', - 'LLVMBinaryRef', 'LLVMBinaryType', 'LLVMBinaryTypeArchive', - 'LLVMBinaryTypeCOFF', 'LLVMBinaryTypeCOFFImportFile', - 'LLVMBinaryTypeELF32B', 'LLVMBinaryTypeELF32L', - 'LLVMBinaryTypeELF64B', 'LLVMBinaryTypeELF64L', - 'LLVMBinaryTypeIR', 'LLVMBinaryTypeMachO32B', - 'LLVMBinaryTypeMachO32L', 'LLVMBinaryTypeMachO64B', - 'LLVMBinaryTypeMachO64L', 'LLVMBinaryTypeMachOUniversalBinary', - 'LLVMBinaryTypeWasm', 'LLVMBinaryTypeWinRes', - 'LLVMBinaryType__enumvalues', 'LLVMBitCast', 'LLVMBlockAddress', - 'LLVMBlockAddressValueKind', 'LLVMBool', 'LLVMBr', - 'LLVMBuildAShr', 'LLVMBuildAdd', 'LLVMBuildAddrSpaceCast', - 'LLVMBuildAggregateRet', 'LLVMBuildAlloca', 'LLVMBuildAnd', - 'LLVMBuildArrayAlloca', 'LLVMBuildArrayMalloc', - 'LLVMBuildAtomicCmpXchg', 'LLVMBuildAtomicRMW', 'LLVMBuildBinOp', - 'LLVMBuildBitCast', 'LLVMBuildBr', 'LLVMBuildCall', - 'LLVMBuildCall2', 'LLVMBuildCast', 'LLVMBuildCatchPad', - 'LLVMBuildCatchRet', 'LLVMBuildCatchSwitch', - 'LLVMBuildCleanupPad', 'LLVMBuildCleanupRet', 'LLVMBuildCondBr', - 'LLVMBuildExactSDiv', 'LLVMBuildExactUDiv', - 'LLVMBuildExtractElement', 'LLVMBuildExtractValue', - 'LLVMBuildFAdd', 'LLVMBuildFCmp', 'LLVMBuildFDiv', - 'LLVMBuildFMul', 'LLVMBuildFNeg', 'LLVMBuildFPCast', - 'LLVMBuildFPExt', 'LLVMBuildFPToSI', 'LLVMBuildFPToUI', - 'LLVMBuildFPTrunc', 'LLVMBuildFRem', 'LLVMBuildFSub', - 'LLVMBuildFence', 'LLVMBuildFree', 'LLVMBuildFreeze', - 'LLVMBuildGEP', 'LLVMBuildGEP2', 'LLVMBuildGlobalString', - 'LLVMBuildGlobalStringPtr', 'LLVMBuildICmp', - 'LLVMBuildInBoundsGEP', 'LLVMBuildInBoundsGEP2', - 'LLVMBuildIndirectBr', 'LLVMBuildInsertElement', - 'LLVMBuildInsertValue', 'LLVMBuildIntCast', 'LLVMBuildIntCast2', - 'LLVMBuildIntToPtr', 'LLVMBuildInvoke', 'LLVMBuildInvoke2', - 'LLVMBuildIsNotNull', 'LLVMBuildIsNull', 'LLVMBuildLShr', - 'LLVMBuildLandingPad', 'LLVMBuildLoad', 'LLVMBuildLoad2', - 'LLVMBuildMalloc', 'LLVMBuildMemCpy', 'LLVMBuildMemMove', - 'LLVMBuildMemSet', 'LLVMBuildMul', 'LLVMBuildNSWAdd', - 'LLVMBuildNSWMul', 'LLVMBuildNSWNeg', 'LLVMBuildNSWSub', - 'LLVMBuildNUWAdd', 'LLVMBuildNUWMul', 'LLVMBuildNUWNeg', - 'LLVMBuildNUWSub', 'LLVMBuildNeg', 'LLVMBuildNot', 'LLVMBuildOr', - 'LLVMBuildPhi', 'LLVMBuildPointerCast', 'LLVMBuildPtrDiff', - 'LLVMBuildPtrDiff2', 'LLVMBuildPtrToInt', 'LLVMBuildResume', - 'LLVMBuildRet', 'LLVMBuildRetVoid', 'LLVMBuildSDiv', - 'LLVMBuildSExt', 'LLVMBuildSExtOrBitCast', 'LLVMBuildSIToFP', - 'LLVMBuildSRem', 'LLVMBuildSelect', 'LLVMBuildShl', - 'LLVMBuildShuffleVector', 'LLVMBuildStore', 'LLVMBuildStructGEP', - 'LLVMBuildStructGEP2', 'LLVMBuildSub', 'LLVMBuildSwitch', - 'LLVMBuildTrunc', 'LLVMBuildTruncOrBitCast', 'LLVMBuildUDiv', - 'LLVMBuildUIToFP', 'LLVMBuildURem', 'LLVMBuildUnreachable', - 'LLVMBuildVAArg', 'LLVMBuildXor', 'LLVMBuildZExt', - 'LLVMBuildZExtOrBitCast', 'LLVMBuilderGetDefaultFPMathTag', - 'LLVMBuilderRef', 'LLVMBuilderSetDefaultFPMathTag', - 'LLVMByteOrder', 'LLVMByteOrdering', 'LLVMCCallConv', - 'LLVMCXXFASTTLSCallConv', 'LLVMCall', 'LLVMCallBr', - 'LLVMCallConv', 'LLVMCallConv__enumvalues', - 'LLVMCallFrameAlignmentOfType', 'LLVMCatchPad', 'LLVMCatchRet', - 'LLVMCatchSwitch', 'LLVMCleanupPad', 'LLVMCleanupRet', - 'LLVMClearInsertionPosition', 'LLVMCloneModule', - 'LLVMCodeGenFileType', 'LLVMCodeGenFileType__enumvalues', - 'LLVMCodeGenLevelAggressive', 'LLVMCodeGenLevelDefault', - 'LLVMCodeGenLevelLess', 'LLVMCodeGenLevelNone', - 'LLVMCodeGenOptLevel', 'LLVMCodeGenOptLevel__enumvalues', - 'LLVMCodeModel', 'LLVMCodeModelDefault', - 'LLVMCodeModelJITDefault', 'LLVMCodeModelKernel', - 'LLVMCodeModelLarge', 'LLVMCodeModelMedium', 'LLVMCodeModelSmall', - 'LLVMCodeModelTiny', 'LLVMCodeModel__enumvalues', - 'LLVMColdCallConv', 'LLVMComdatRef', 'LLVMComdatSelectionKind', - 'LLVMComdatSelectionKind__enumvalues', 'LLVMCommonLinkage', - 'LLVMConstAShr', 'LLVMConstAdd', 'LLVMConstAddrSpaceCast', - 'LLVMConstAllOnes', 'LLVMConstAnd', 'LLVMConstArray', - 'LLVMConstBitCast', 'LLVMConstExactSDiv', 'LLVMConstExactUDiv', - 'LLVMConstExtractElement', 'LLVMConstExtractValue', - 'LLVMConstFAdd', 'LLVMConstFCmp', 'LLVMConstFDiv', - 'LLVMConstFMul', 'LLVMConstFNeg', 'LLVMConstFPCast', - 'LLVMConstFPExt', 'LLVMConstFPToSI', 'LLVMConstFPToUI', - 'LLVMConstFPTrunc', 'LLVMConstFRem', 'LLVMConstFSub', - 'LLVMConstGEP', 'LLVMConstGEP2', 'LLVMConstICmp', - 'LLVMConstInBoundsGEP', 'LLVMConstInBoundsGEP2', - 'LLVMConstInlineAsm', 'LLVMConstInsertElement', - 'LLVMConstInsertValue', 'LLVMConstInt', 'LLVMConstIntCast', - 'LLVMConstIntGetSExtValue', 'LLVMConstIntGetZExtValue', - 'LLVMConstIntOfArbitraryPrecision', 'LLVMConstIntOfString', - 'LLVMConstIntOfStringAndSize', 'LLVMConstIntToPtr', - 'LLVMConstLShr', 'LLVMConstMul', 'LLVMConstNSWAdd', - 'LLVMConstNSWMul', 'LLVMConstNSWNeg', 'LLVMConstNSWSub', - 'LLVMConstNUWAdd', 'LLVMConstNUWMul', 'LLVMConstNUWNeg', - 'LLVMConstNUWSub', 'LLVMConstNamedStruct', 'LLVMConstNeg', - 'LLVMConstNot', 'LLVMConstNull', 'LLVMConstOr', - 'LLVMConstPointerCast', 'LLVMConstPointerNull', - 'LLVMConstPtrToInt', 'LLVMConstReal', 'LLVMConstRealGetDouble', - 'LLVMConstRealOfString', 'LLVMConstRealOfStringAndSize', - 'LLVMConstSDiv', 'LLVMConstSExt', 'LLVMConstSExtOrBitCast', - 'LLVMConstSIToFP', 'LLVMConstSRem', 'LLVMConstSelect', - 'LLVMConstShl', 'LLVMConstShuffleVector', 'LLVMConstString', - 'LLVMConstStringInContext', 'LLVMConstStruct', - 'LLVMConstStructInContext', 'LLVMConstSub', 'LLVMConstTrunc', - 'LLVMConstTruncOrBitCast', 'LLVMConstUDiv', 'LLVMConstUIToFP', - 'LLVMConstURem', 'LLVMConstVector', 'LLVMConstXor', - 'LLVMConstZExt', 'LLVMConstZExtOrBitCast', - 'LLVMConstantAggregateZeroValueKind', - 'LLVMConstantArrayValueKind', - 'LLVMConstantAsMetadataMetadataKind', - 'LLVMConstantDataArrayValueKind', - 'LLVMConstantDataVectorValueKind', 'LLVMConstantExprValueKind', - 'LLVMConstantFPValueKind', 'LLVMConstantIntValueKind', - 'LLVMConstantPointerNullValueKind', 'LLVMConstantStructValueKind', - 'LLVMConstantTokenNoneValueKind', 'LLVMConstantVectorValueKind', - 'LLVMConsumeError', 'LLVMContextCreate', 'LLVMContextDispose', - 'LLVMContextGetDiagnosticContext', - 'LLVMContextGetDiagnosticHandler', 'LLVMContextRef', - 'LLVMContextSetDiagnosticHandler', - 'LLVMContextSetDiscardValueNames', 'LLVMContextSetYieldCallback', - 'LLVMContextShouldDiscardValueNames', - 'LLVMCopyModuleFlagsMetadata', 'LLVMCopyStringRepOfTargetData', - 'LLVMCountBasicBlocks', 'LLVMCountIncoming', - 'LLVMCountParamTypes', 'LLVMCountParams', - 'LLVMCountStructElementTypes', 'LLVMCreateBasicBlockInContext', - 'LLVMCreateBinary', 'LLVMCreateBuilder', - 'LLVMCreateBuilderInContext', 'LLVMCreateDIBuilder', - 'LLVMCreateDIBuilderDisallowUnresolved', 'LLVMCreateDisasm', - 'LLVMCreateDisasmCPU', 'LLVMCreateDisasmCPUFeatures', - 'LLVMCreateEnumAttribute', 'LLVMCreateExecutionEngineForModule', - 'LLVMCreateFunctionPassManager', - 'LLVMCreateFunctionPassManagerForModule', - 'LLVMCreateGDBRegistrationListener', - 'LLVMCreateGenericValueOfFloat', 'LLVMCreateGenericValueOfInt', - 'LLVMCreateGenericValueOfPointer', - 'LLVMCreateIntelJITEventListener', - 'LLVMCreateInterpreterForModule', - 'LLVMCreateJITCompilerForModule', - 'LLVMCreateMCJITCompilerForModule', - 'LLVMCreateMemoryBufferWithContentsOfFile', - 'LLVMCreateMemoryBufferWithMemoryRange', - 'LLVMCreateMemoryBufferWithMemoryRangeCopy', - 'LLVMCreateMemoryBufferWithSTDIN', 'LLVMCreateMessage', - 'LLVMCreateModuleProviderForExistingModule', - 'LLVMCreateOProfileJITEventListener', 'LLVMCreateObjectFile', - 'LLVMCreatePassBuilderOptions', 'LLVMCreatePassManager', - 'LLVMCreatePerfJITEventListener', - 'LLVMCreateSimpleMCJITMemoryManager', 'LLVMCreateStringAttribute', - 'LLVMCreateStringError', 'LLVMCreateTargetData', - 'LLVMCreateTargetDataLayout', 'LLVMCreateTargetMachine', - 'LLVMCreateTypeAttribute', 'LLVMDIArgListMetadataKind', - 'LLVMDIBasicTypeMetadataKind', 'LLVMDIBuilderCreateArrayType', - 'LLVMDIBuilderCreateArtificialType', - 'LLVMDIBuilderCreateAutoVariable', 'LLVMDIBuilderCreateBasicType', - 'LLVMDIBuilderCreateBitFieldMemberType', - 'LLVMDIBuilderCreateClassType', 'LLVMDIBuilderCreateCompileUnit', - 'LLVMDIBuilderCreateConstantValueExpression', - 'LLVMDIBuilderCreateDebugLocation', - 'LLVMDIBuilderCreateEnumerationType', - 'LLVMDIBuilderCreateEnumerator', 'LLVMDIBuilderCreateExpression', - 'LLVMDIBuilderCreateFile', 'LLVMDIBuilderCreateForwardDecl', - 'LLVMDIBuilderCreateFunction', - 'LLVMDIBuilderCreateGlobalVariableExpression', - 'LLVMDIBuilderCreateImportedDeclaration', - 'LLVMDIBuilderCreateImportedModuleFromAlias', - 'LLVMDIBuilderCreateImportedModuleFromModule', - 'LLVMDIBuilderCreateImportedModuleFromNamespace', - 'LLVMDIBuilderCreateInheritance', - 'LLVMDIBuilderCreateLexicalBlock', - 'LLVMDIBuilderCreateLexicalBlockFile', 'LLVMDIBuilderCreateMacro', - 'LLVMDIBuilderCreateMemberPointerType', - 'LLVMDIBuilderCreateMemberType', 'LLVMDIBuilderCreateModule', - 'LLVMDIBuilderCreateNameSpace', 'LLVMDIBuilderCreateNullPtrType', - 'LLVMDIBuilderCreateObjCIVar', 'LLVMDIBuilderCreateObjCProperty', - 'LLVMDIBuilderCreateObjectPointerType', - 'LLVMDIBuilderCreateParameterVariable', - 'LLVMDIBuilderCreatePointerType', - 'LLVMDIBuilderCreateQualifiedType', - 'LLVMDIBuilderCreateReferenceType', - 'LLVMDIBuilderCreateReplaceableCompositeType', - 'LLVMDIBuilderCreateStaticMemberType', - 'LLVMDIBuilderCreateStructType', - 'LLVMDIBuilderCreateSubroutineType', - 'LLVMDIBuilderCreateTempGlobalVariableFwdDecl', - 'LLVMDIBuilderCreateTempMacroFile', 'LLVMDIBuilderCreateTypedef', - 'LLVMDIBuilderCreateUnionType', - 'LLVMDIBuilderCreateUnspecifiedType', - 'LLVMDIBuilderCreateVectorType', 'LLVMDIBuilderFinalize', - 'LLVMDIBuilderFinalizeSubprogram', - 'LLVMDIBuilderGetOrCreateArray', - 'LLVMDIBuilderGetOrCreateSubrange', - 'LLVMDIBuilderGetOrCreateTypeArray', - 'LLVMDIBuilderInsertDbgValueAtEnd', - 'LLVMDIBuilderInsertDbgValueBefore', - 'LLVMDIBuilderInsertDeclareAtEnd', - 'LLVMDIBuilderInsertDeclareBefore', 'LLVMDIBuilderRef', - 'LLVMDICommonBlockMetadataKind', 'LLVMDICompileUnitMetadataKind', - 'LLVMDICompositeTypeMetadataKind', - 'LLVMDIDerivedTypeMetadataKind', 'LLVMDIEnumeratorMetadataKind', - 'LLVMDIExpressionMetadataKind', 'LLVMDIFileGetDirectory', - 'LLVMDIFileGetFilename', 'LLVMDIFileGetSource', - 'LLVMDIFileMetadataKind', 'LLVMDIFlagAccessibility', - 'LLVMDIFlagAppleBlock', 'LLVMDIFlagArtificial', - 'LLVMDIFlagBigEndian', 'LLVMDIFlagBitField', - 'LLVMDIFlagEnumClass', 'LLVMDIFlagExplicit', - 'LLVMDIFlagFixedEnum', 'LLVMDIFlagFwdDecl', - 'LLVMDIFlagIndirectVirtualBase', 'LLVMDIFlagIntroducedVirtual', - 'LLVMDIFlagLValueReference', 'LLVMDIFlagLittleEndian', - 'LLVMDIFlagMultipleInheritance', 'LLVMDIFlagNoReturn', - 'LLVMDIFlagNonTrivial', 'LLVMDIFlagObjcClassComplete', - 'LLVMDIFlagObjectPointer', 'LLVMDIFlagPrivate', - 'LLVMDIFlagProtected', 'LLVMDIFlagPrototyped', - 'LLVMDIFlagPtrToMemberRep', 'LLVMDIFlagPublic', - 'LLVMDIFlagRValueReference', 'LLVMDIFlagReserved', - 'LLVMDIFlagReservedBit4', 'LLVMDIFlagSingleInheritance', - 'LLVMDIFlagStaticMember', 'LLVMDIFlagThunk', - 'LLVMDIFlagTypePassByReference', 'LLVMDIFlagTypePassByValue', - 'LLVMDIFlagVector', 'LLVMDIFlagVirtual', - 'LLVMDIFlagVirtualInheritance', 'LLVMDIFlagZero', 'LLVMDIFlags', - 'LLVMDIFlags__enumvalues', 'LLVMDIGenericSubrangeMetadataKind', - 'LLVMDIGlobalVariableExpressionGetExpression', - 'LLVMDIGlobalVariableExpressionGetVariable', - 'LLVMDIGlobalVariableExpressionMetadataKind', - 'LLVMDIGlobalVariableMetadataKind', - 'LLVMDIImportedEntityMetadataKind', 'LLVMDILabelMetadataKind', - 'LLVMDILexicalBlockFileMetadataKind', - 'LLVMDILexicalBlockMetadataKind', - 'LLVMDILocalVariableMetadataKind', 'LLVMDILocationGetColumn', - 'LLVMDILocationGetInlinedAt', 'LLVMDILocationGetLine', - 'LLVMDILocationGetScope', 'LLVMDILocationMetadataKind', - 'LLVMDIMacroFileMetadataKind', 'LLVMDIMacroMetadataKind', - 'LLVMDIModuleMetadataKind', 'LLVMDINamespaceMetadataKind', - 'LLVMDIObjCPropertyMetadataKind', 'LLVMDIScopeGetFile', - 'LLVMDIStringTypeMetadataKind', 'LLVMDISubprogramGetLine', - 'LLVMDISubprogramMetadataKind', 'LLVMDISubrangeMetadataKind', - 'LLVMDISubroutineTypeMetadataKind', - 'LLVMDITemplateTypeParameterMetadataKind', - 'LLVMDITemplateValueParameterMetadataKind', - 'LLVMDITypeGetAlignInBits', 'LLVMDITypeGetFlags', - 'LLVMDITypeGetLine', 'LLVMDITypeGetName', - 'LLVMDITypeGetOffsetInBits', 'LLVMDITypeGetSizeInBits', - 'LLVMDIVariableGetFile', 'LLVMDIVariableGetLine', - 'LLVMDIVariableGetScope', 'LLVMDLLExportLinkage', - 'LLVMDLLExportStorageClass', 'LLVMDLLImportLinkage', - 'LLVMDLLImportStorageClass', 'LLVMDLLStorageClass', - 'LLVMDLLStorageClass__enumvalues', 'LLVMDSError', 'LLVMDSNote', - 'LLVMDSRemark', 'LLVMDSWarning', 'LLVMDWARFEmissionFull', - 'LLVMDWARFEmissionKind', 'LLVMDWARFEmissionKind__enumvalues', - 'LLVMDWARFEmissionLineTablesOnly', 'LLVMDWARFEmissionNone', - 'LLVMDWARFMacinfoRecordType', 'LLVMDWARFMacinfoRecordTypeDefine', - 'LLVMDWARFMacinfoRecordTypeEndFile', - 'LLVMDWARFMacinfoRecordTypeMacro', - 'LLVMDWARFMacinfoRecordTypeStartFile', - 'LLVMDWARFMacinfoRecordTypeVendorExt', - 'LLVMDWARFMacinfoRecordType__enumvalues', - 'LLVMDWARFSourceLanguage', 'LLVMDWARFSourceLanguageAda83', - 'LLVMDWARFSourceLanguageAda95', 'LLVMDWARFSourceLanguageBLISS', - 'LLVMDWARFSourceLanguageBORLAND_Delphi', - 'LLVMDWARFSourceLanguageC', 'LLVMDWARFSourceLanguageC11', - 'LLVMDWARFSourceLanguageC89', 'LLVMDWARFSourceLanguageC99', - 'LLVMDWARFSourceLanguageC_plus_plus', - 'LLVMDWARFSourceLanguageC_plus_plus_03', - 'LLVMDWARFSourceLanguageC_plus_plus_11', - 'LLVMDWARFSourceLanguageC_plus_plus_14', - 'LLVMDWARFSourceLanguageCobol74', - 'LLVMDWARFSourceLanguageCobol85', 'LLVMDWARFSourceLanguageD', - 'LLVMDWARFSourceLanguageDylan', - 'LLVMDWARFSourceLanguageFortran03', - 'LLVMDWARFSourceLanguageFortran08', - 'LLVMDWARFSourceLanguageFortran77', - 'LLVMDWARFSourceLanguageFortran90', - 'LLVMDWARFSourceLanguageFortran95', - 'LLVMDWARFSourceLanguageGOOGLE_RenderScript', - 'LLVMDWARFSourceLanguageGo', 'LLVMDWARFSourceLanguageHaskell', - 'LLVMDWARFSourceLanguageJava', 'LLVMDWARFSourceLanguageJulia', - 'LLVMDWARFSourceLanguageMips_Assembler', - 'LLVMDWARFSourceLanguageModula2', - 'LLVMDWARFSourceLanguageModula3', 'LLVMDWARFSourceLanguageOCaml', - 'LLVMDWARFSourceLanguageObjC', - 'LLVMDWARFSourceLanguageObjC_plus_plus', - 'LLVMDWARFSourceLanguageOpenCL', 'LLVMDWARFSourceLanguagePLI', - 'LLVMDWARFSourceLanguagePascal83', - 'LLVMDWARFSourceLanguagePython', - 'LLVMDWARFSourceLanguageRenderScript', - 'LLVMDWARFSourceLanguageRust', 'LLVMDWARFSourceLanguageSwift', - 'LLVMDWARFSourceLanguageUPC', - 'LLVMDWARFSourceLanguage__enumvalues', 'LLVMDWARFTypeEncoding', - 'LLVMDebugMetadataVersion', 'LLVMDefaultStorageClass', - 'LLVMDefaultVisibility', 'LLVMDeleteBasicBlock', - 'LLVMDeleteFunction', 'LLVMDeleteGlobal', 'LLVMDiagnosticHandler', - 'LLVMDiagnosticInfoRef', 'LLVMDiagnosticSeverity', - 'LLVMDiagnosticSeverity__enumvalues', 'LLVMDisasmContextRef', - 'LLVMDisasmDispose', 'LLVMDisasmInstruction', - 'LLVMDisassembler_Option_AsmPrinterVariant', - 'LLVMDisassembler_Option_PrintImmHex', - 'LLVMDisassembler_Option_PrintLatency', - 'LLVMDisassembler_Option_SetInstrComments', - 'LLVMDisassembler_Option_UseMarkup', - 'LLVMDisassembler_ReferenceType_DeMangled_Name', - 'LLVMDisassembler_ReferenceType_InOut_None', - 'LLVMDisassembler_ReferenceType_In_ARM64_ADDXri', - 'LLVMDisassembler_ReferenceType_In_ARM64_ADR', - 'LLVMDisassembler_ReferenceType_In_ARM64_ADRP', - 'LLVMDisassembler_ReferenceType_In_ARM64_LDRXl', - 'LLVMDisassembler_ReferenceType_In_ARM64_LDRXui', - 'LLVMDisassembler_ReferenceType_In_Branch', - 'LLVMDisassembler_ReferenceType_In_PCrel_Load', - 'LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr', - 'LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr', - 'LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref', - 'LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref', - 'LLVMDisassembler_ReferenceType_Out_Objc_Message', - 'LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref', - 'LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref', - 'LLVMDisassembler_ReferenceType_Out_SymbolStub', - 'LLVMDisassembler_VariantKind_ARM64_GOTPAGE', - 'LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF', - 'LLVMDisassembler_VariantKind_ARM64_PAGE', - 'LLVMDisassembler_VariantKind_ARM64_PAGEOFF', - 'LLVMDisassembler_VariantKind_ARM64_TLVOFF', - 'LLVMDisassembler_VariantKind_ARM64_TLVP', - 'LLVMDisassembler_VariantKind_ARM_HI16', - 'LLVMDisassembler_VariantKind_ARM_LO16', - 'LLVMDisassembler_VariantKind_None', 'LLVMDisposeBinary', - 'LLVMDisposeBuilder', 'LLVMDisposeDIBuilder', - 'LLVMDisposeErrorMessage', 'LLVMDisposeExecutionEngine', - 'LLVMDisposeGenericValue', 'LLVMDisposeMCJITMemoryManager', - 'LLVMDisposeMemoryBuffer', 'LLVMDisposeMessage', - 'LLVMDisposeModule', 'LLVMDisposeModuleFlagsMetadata', - 'LLVMDisposeModuleProvider', 'LLVMDisposeObjectFile', - 'LLVMDisposePassBuilderOptions', 'LLVMDisposePassManager', - 'LLVMDisposeRelocationIterator', 'LLVMDisposeSectionIterator', - 'LLVMDisposeSymbolIterator', 'LLVMDisposeTargetData', - 'LLVMDisposeTargetMachine', 'LLVMDisposeTemporaryMDNode', - 'LLVMDisposeValueMetadataEntries', - 'LLVMDistinctMDOperandPlaceholderMetadataKind', 'LLVMDoubleType', - 'LLVMDoubleTypeInContext', 'LLVMDoubleTypeKind', 'LLVMDumpModule', - 'LLVMDumpType', 'LLVMDumpValue', 'LLVMElementAtOffset', - 'LLVMEnablePrettyStackTrace', 'LLVMEraseGlobalIFunc', - 'LLVMErrorRef', 'LLVMErrorSuccess', 'LLVMErrorTypeId', - 'LLVMExactMatchComdatSelectionKind', - 'LLVMExecutionEngineGetErrMsg', 'LLVMExecutionEngineRef', - 'LLVMExternalLinkage', 'LLVMExternalWeakLinkage', - 'LLVMExtractElement', 'LLVMExtractValue', 'LLVMFAdd', 'LLVMFCmp', - 'LLVMFDiv', 'LLVMFMul', 'LLVMFNeg', 'LLVMFP128Type', - 'LLVMFP128TypeInContext', 'LLVMFP128TypeKind', 'LLVMFPExt', - 'LLVMFPToSI', 'LLVMFPToUI', 'LLVMFPTrunc', 'LLVMFRem', 'LLVMFSub', - 'LLVMFastCallConv', 'LLVMFatalErrorHandler', 'LLVMFence', - 'LLVMFinalizeFunctionPassManager', 'LLVMFindFunction', - 'LLVMFloatType', 'LLVMFloatTypeInContext', 'LLVMFloatTypeKind', - 'LLVMFreeMachineCodeForFunction', 'LLVMFreeze', - 'LLVMFunctionType', 'LLVMFunctionTypeKind', - 'LLVMFunctionValueKind', 'LLVMGHCCallConv', - 'LLVMGeneralDynamicTLSModel', 'LLVMGenericDINodeMetadataKind', - 'LLVMGenericValueIntWidth', 'LLVMGenericValueRef', - 'LLVMGenericValueToFloat', 'LLVMGenericValueToInt', - 'LLVMGenericValueToPointer', 'LLVMGetAlignment', - 'LLVMGetAllocatedType', 'LLVMGetArgOperand', 'LLVMGetArrayLength', - 'LLVMGetAsString', 'LLVMGetAtomicRMWBinOp', - 'LLVMGetAttributeCountAtIndex', 'LLVMGetAttributesAtIndex', - 'LLVMGetBasicBlockName', 'LLVMGetBasicBlockParent', - 'LLVMGetBasicBlockTerminator', 'LLVMGetBasicBlocks', - 'LLVMGetBitcodeModule', 'LLVMGetBitcodeModule2', - 'LLVMGetBitcodeModuleInContext', 'LLVMGetBitcodeModuleInContext2', - 'LLVMGetBufferSize', 'LLVMGetBufferStart', - 'LLVMGetCallSiteAttributeCount', 'LLVMGetCallSiteAttributes', - 'LLVMGetCallSiteEnumAttribute', 'LLVMGetCallSiteStringAttribute', - 'LLVMGetCalledFunctionType', 'LLVMGetCalledValue', - 'LLVMGetClause', 'LLVMGetCmpXchgFailureOrdering', - 'LLVMGetCmpXchgSuccessOrdering', 'LLVMGetComdat', - 'LLVMGetComdatSelectionKind', 'LLVMGetCondition', - 'LLVMGetConstOpcode', 'LLVMGetCurrentDebugLocation', - 'LLVMGetCurrentDebugLocation2', 'LLVMGetDLLStorageClass', - 'LLVMGetDataLayout', 'LLVMGetDataLayoutStr', - 'LLVMGetDebugLocColumn', 'LLVMGetDebugLocDirectory', - 'LLVMGetDebugLocFilename', 'LLVMGetDebugLocLine', - 'LLVMGetDefaultTargetTriple', 'LLVMGetDiagInfoDescription', - 'LLVMGetDiagInfoSeverity', 'LLVMGetElementAsConstant', - 'LLVMGetElementPtr', 'LLVMGetElementType', - 'LLVMGetEntryBasicBlock', 'LLVMGetEnumAttributeAtIndex', - 'LLVMGetEnumAttributeKind', 'LLVMGetEnumAttributeKindForName', - 'LLVMGetEnumAttributeValue', 'LLVMGetErrorMessage', - 'LLVMGetErrorTypeId', 'LLVMGetExecutionEngineTargetData', - 'LLVMGetExecutionEngineTargetMachine', 'LLVMGetFCmpPredicate', - 'LLVMGetFirstBasicBlock', 'LLVMGetFirstFunction', - 'LLVMGetFirstGlobal', 'LLVMGetFirstGlobalAlias', - 'LLVMGetFirstGlobalIFunc', 'LLVMGetFirstInstruction', - 'LLVMGetFirstNamedMetadata', 'LLVMGetFirstParam', - 'LLVMGetFirstTarget', 'LLVMGetFirstUse', 'LLVMGetFunctionAddress', - 'LLVMGetFunctionCallConv', 'LLVMGetGC', - 'LLVMGetGEPSourceElementType', 'LLVMGetGlobalContext', - 'LLVMGetGlobalIFuncResolver', 'LLVMGetGlobalParent', - 'LLVMGetGlobalPassRegistry', 'LLVMGetGlobalValueAddress', - 'LLVMGetHandlers', 'LLVMGetHostCPUFeatures', 'LLVMGetHostCPUName', - 'LLVMGetICmpPredicate', 'LLVMGetIncomingBlock', - 'LLVMGetIncomingValue', 'LLVMGetIndices', 'LLVMGetInitializer', - 'LLVMGetInlineAsm', 'LLVMGetInsertBlock', - 'LLVMGetInstructionCallConv', 'LLVMGetInstructionOpcode', - 'LLVMGetInstructionParent', 'LLVMGetIntTypeWidth', - 'LLVMGetIntrinsicDeclaration', 'LLVMGetIntrinsicID', - 'LLVMGetLastBasicBlock', 'LLVMGetLastEnumAttributeKind', - 'LLVMGetLastFunction', 'LLVMGetLastGlobal', - 'LLVMGetLastGlobalAlias', 'LLVMGetLastGlobalIFunc', - 'LLVMGetLastInstruction', 'LLVMGetLastNamedMetadata', - 'LLVMGetLastParam', 'LLVMGetLinkage', 'LLVMGetMDKindID', - 'LLVMGetMDKindIDInContext', 'LLVMGetMDNodeNumOperands', - 'LLVMGetMDNodeOperands', 'LLVMGetMDString', 'LLVMGetMaskValue', - 'LLVMGetMetadata', 'LLVMGetMetadataKind', 'LLVMGetModuleContext', - 'LLVMGetModuleDataLayout', 'LLVMGetModuleDebugMetadataVersion', - 'LLVMGetModuleFlag', 'LLVMGetModuleIdentifier', - 'LLVMGetModuleInlineAsm', 'LLVMGetNamedFunction', - 'LLVMGetNamedGlobal', 'LLVMGetNamedGlobalAlias', - 'LLVMGetNamedGlobalIFunc', 'LLVMGetNamedMetadata', - 'LLVMGetNamedMetadataName', 'LLVMGetNamedMetadataNumOperands', - 'LLVMGetNamedMetadataOperands', 'LLVMGetNextBasicBlock', - 'LLVMGetNextFunction', 'LLVMGetNextGlobal', - 'LLVMGetNextGlobalAlias', 'LLVMGetNextGlobalIFunc', - 'LLVMGetNextInstruction', 'LLVMGetNextNamedMetadata', - 'LLVMGetNextParam', 'LLVMGetNextTarget', 'LLVMGetNextUse', - 'LLVMGetNormalDest', 'LLVMGetNumArgOperands', 'LLVMGetNumClauses', - 'LLVMGetNumContainedTypes', 'LLVMGetNumHandlers', - 'LLVMGetNumIndices', 'LLVMGetNumMaskElements', - 'LLVMGetNumOperands', 'LLVMGetNumSuccessors', 'LLVMGetOperand', - 'LLVMGetOperandUse', 'LLVMGetOrInsertComdat', - 'LLVMGetOrInsertNamedMetadata', 'LLVMGetOrdering', 'LLVMGetParam', - 'LLVMGetParamParent', 'LLVMGetParamTypes', 'LLVMGetParams', - 'LLVMGetParentCatchSwitch', 'LLVMGetPersonalityFn', - 'LLVMGetPointerAddressSpace', 'LLVMGetPointerToGlobal', - 'LLVMGetPoison', 'LLVMGetPreviousBasicBlock', - 'LLVMGetPreviousFunction', 'LLVMGetPreviousGlobal', - 'LLVMGetPreviousGlobalAlias', 'LLVMGetPreviousGlobalIFunc', - 'LLVMGetPreviousInstruction', 'LLVMGetPreviousNamedMetadata', - 'LLVMGetPreviousParam', 'LLVMGetRelocationOffset', - 'LLVMGetRelocationSymbol', 'LLVMGetRelocationType', - 'LLVMGetRelocationTypeName', 'LLVMGetRelocationValueString', - 'LLVMGetRelocations', 'LLVMGetReturnType', 'LLVMGetSection', - 'LLVMGetSectionAddress', 'LLVMGetSectionContainsSymbol', - 'LLVMGetSectionContents', 'LLVMGetSectionName', - 'LLVMGetSectionSize', 'LLVMGetSections', 'LLVMGetSourceFileName', - 'LLVMGetStringAttributeAtIndex', 'LLVMGetStringAttributeKind', - 'LLVMGetStringAttributeValue', 'LLVMGetStringErrorTypeId', - 'LLVMGetStructElementTypes', 'LLVMGetStructName', - 'LLVMGetSubprogram', 'LLVMGetSubtypes', 'LLVMGetSuccessor', - 'LLVMGetSwitchDefaultDest', 'LLVMGetSymbolAddress', - 'LLVMGetSymbolName', 'LLVMGetSymbolSize', 'LLVMGetSymbols', - 'LLVMGetTarget', 'LLVMGetTargetDescription', - 'LLVMGetTargetFromName', 'LLVMGetTargetFromTriple', - 'LLVMGetTargetMachineCPU', 'LLVMGetTargetMachineFeatureString', - 'LLVMGetTargetMachineTarget', 'LLVMGetTargetMachineTriple', - 'LLVMGetTargetName', 'LLVMGetThreadLocalMode', - 'LLVMGetTypeAttributeValue', 'LLVMGetTypeByName', - 'LLVMGetTypeByName2', 'LLVMGetTypeContext', 'LLVMGetTypeKind', - 'LLVMGetUndef', 'LLVMGetUndefMaskElem', 'LLVMGetUnnamedAddress', - 'LLVMGetUnwindDest', 'LLVMGetUsedValue', 'LLVMGetUser', - 'LLVMGetValueKind', 'LLVMGetValueName', 'LLVMGetValueName2', - 'LLVMGetVectorSize', 'LLVMGetVisibility', 'LLVMGetVolatile', - 'LLVMGetWeak', 'LLVMGhostLinkage', 'LLVMGlobalAliasValueKind', - 'LLVMGlobalClearMetadata', 'LLVMGlobalCopyAllMetadata', - 'LLVMGlobalEraseMetadata', 'LLVMGlobalGetValueType', - 'LLVMGlobalIFuncValueKind', 'LLVMGlobalSetMetadata', - 'LLVMGlobalUnnamedAddr', 'LLVMGlobalVariableValueKind', - 'LLVMHHVMCCallConv', 'LLVMHHVMCallConv', 'LLVMHalfType', - 'LLVMHalfTypeInContext', 'LLVMHalfTypeKind', 'LLVMHasMetadata', - 'LLVMHasPersonalityFn', 'LLVMHasUnnamedAddr', 'LLVMHiPECallConv', - 'LLVMHiddenVisibility', 'LLVMICmp', 'LLVMIndirectBr', - 'LLVMInitialExecTLSModel', 'LLVMInitializeAArch64AsmParser', - 'LLVMInitializeAArch64AsmPrinter', - 'LLVMInitializeAArch64Disassembler', - 'LLVMInitializeAArch64Target', 'LLVMInitializeAArch64TargetInfo', - 'LLVMInitializeAArch64TargetMC', 'LLVMInitializeAMDGPUAsmParser', - 'LLVMInitializeAMDGPUAsmPrinter', - 'LLVMInitializeAMDGPUDisassembler', 'LLVMInitializeAMDGPUTarget', - 'LLVMInitializeAMDGPUTargetInfo', 'LLVMInitializeAMDGPUTargetMC', - 'LLVMInitializeARMAsmParser', 'LLVMInitializeARMAsmPrinter', - 'LLVMInitializeARMDisassembler', 'LLVMInitializeARMTarget', - 'LLVMInitializeARMTargetInfo', 'LLVMInitializeARMTargetMC', - 'LLVMInitializeAVRAsmParser', 'LLVMInitializeAVRAsmPrinter', - 'LLVMInitializeAVRDisassembler', 'LLVMInitializeAVRTarget', - 'LLVMInitializeAVRTargetInfo', 'LLVMInitializeAVRTargetMC', - 'LLVMInitializeAggressiveInstCombiner', - 'LLVMInitializeAllAsmParsers', 'LLVMInitializeAllAsmPrinters', - 'LLVMInitializeAllDisassemblers', 'LLVMInitializeAllTargetInfos', - 'LLVMInitializeAllTargetMCs', 'LLVMInitializeAllTargets', - 'LLVMInitializeAnalysis', 'LLVMInitializeBPFAsmParser', - 'LLVMInitializeBPFAsmPrinter', 'LLVMInitializeBPFDisassembler', - 'LLVMInitializeBPFTarget', 'LLVMInitializeBPFTargetInfo', - 'LLVMInitializeBPFTargetMC', 'LLVMInitializeCodeGen', - 'LLVMInitializeCore', 'LLVMInitializeFunctionPassManager', - 'LLVMInitializeHexagonAsmParser', - 'LLVMInitializeHexagonAsmPrinter', - 'LLVMInitializeHexagonDisassembler', - 'LLVMInitializeHexagonTarget', 'LLVMInitializeHexagonTargetInfo', - 'LLVMInitializeHexagonTargetMC', 'LLVMInitializeIPA', - 'LLVMInitializeIPO', 'LLVMInitializeInstCombine', - 'LLVMInitializeInstrumentation', 'LLVMInitializeLanaiAsmParser', - 'LLVMInitializeLanaiAsmPrinter', - 'LLVMInitializeLanaiDisassembler', 'LLVMInitializeLanaiTarget', - 'LLVMInitializeLanaiTargetInfo', 'LLVMInitializeLanaiTargetMC', - 'LLVMInitializeM68kAsmParser', 'LLVMInitializeM68kAsmPrinter', - 'LLVMInitializeM68kDisassembler', 'LLVMInitializeM68kTarget', - 'LLVMInitializeM68kTargetInfo', 'LLVMInitializeM68kTargetMC', - 'LLVMInitializeMCJITCompilerOptions', - 'LLVMInitializeMSP430AsmParser', 'LLVMInitializeMSP430AsmPrinter', - 'LLVMInitializeMSP430Disassembler', 'LLVMInitializeMSP430Target', - 'LLVMInitializeMSP430TargetInfo', 'LLVMInitializeMSP430TargetMC', - 'LLVMInitializeMipsAsmParser', 'LLVMInitializeMipsAsmPrinter', - 'LLVMInitializeMipsDisassembler', 'LLVMInitializeMipsTarget', - 'LLVMInitializeMipsTargetInfo', 'LLVMInitializeMipsTargetMC', - 'LLVMInitializeNVPTXAsmPrinter', 'LLVMInitializeNVPTXTarget', - 'LLVMInitializeNVPTXTargetInfo', 'LLVMInitializeNVPTXTargetMC', - 'LLVMInitializeNativeAsmParser', 'LLVMInitializeNativeAsmPrinter', - 'LLVMInitializeNativeDisassembler', 'LLVMInitializeNativeTarget', - 'LLVMInitializeObjCARCOpts', 'LLVMInitializePowerPCAsmParser', - 'LLVMInitializePowerPCAsmPrinter', - 'LLVMInitializePowerPCDisassembler', - 'LLVMInitializePowerPCTarget', 'LLVMInitializePowerPCTargetInfo', - 'LLVMInitializePowerPCTargetMC', 'LLVMInitializeRISCVAsmParser', - 'LLVMInitializeRISCVAsmPrinter', - 'LLVMInitializeRISCVDisassembler', 'LLVMInitializeRISCVTarget', - 'LLVMInitializeRISCVTargetInfo', 'LLVMInitializeRISCVTargetMC', - 'LLVMInitializeScalarOpts', 'LLVMInitializeSparcAsmParser', - 'LLVMInitializeSparcAsmPrinter', - 'LLVMInitializeSparcDisassembler', 'LLVMInitializeSparcTarget', - 'LLVMInitializeSparcTargetInfo', 'LLVMInitializeSparcTargetMC', - 'LLVMInitializeSystemZAsmParser', - 'LLVMInitializeSystemZAsmPrinter', - 'LLVMInitializeSystemZDisassembler', - 'LLVMInitializeSystemZTarget', 'LLVMInitializeSystemZTargetInfo', - 'LLVMInitializeSystemZTargetMC', 'LLVMInitializeTarget', - 'LLVMInitializeTransformUtils', 'LLVMInitializeVEAsmParser', - 'LLVMInitializeVEAsmPrinter', 'LLVMInitializeVEDisassembler', - 'LLVMInitializeVETarget', 'LLVMInitializeVETargetInfo', - 'LLVMInitializeVETargetMC', 'LLVMInitializeVectorization', - 'LLVMInitializeWebAssemblyAsmParser', - 'LLVMInitializeWebAssemblyAsmPrinter', - 'LLVMInitializeWebAssemblyDisassembler', - 'LLVMInitializeWebAssemblyTarget', - 'LLVMInitializeWebAssemblyTargetInfo', - 'LLVMInitializeWebAssemblyTargetMC', 'LLVMInitializeX86AsmParser', - 'LLVMInitializeX86AsmPrinter', 'LLVMInitializeX86Disassembler', - 'LLVMInitializeX86Target', 'LLVMInitializeX86TargetInfo', - 'LLVMInitializeX86TargetMC', 'LLVMInitializeXCoreAsmPrinter', - 'LLVMInitializeXCoreDisassembler', 'LLVMInitializeXCoreTarget', - 'LLVMInitializeXCoreTargetInfo', 'LLVMInitializeXCoreTargetMC', - 'LLVMInlineAsmDialect', 'LLVMInlineAsmDialectATT', - 'LLVMInlineAsmDialectIntel', 'LLVMInlineAsmDialect__enumvalues', - 'LLVMInlineAsmValueKind', 'LLVMInsertBasicBlock', - 'LLVMInsertBasicBlockInContext', 'LLVMInsertElement', - 'LLVMInsertExistingBasicBlockAfterInsertBlock', - 'LLVMInsertIntoBuilder', 'LLVMInsertIntoBuilderWithName', - 'LLVMInsertValue', 'LLVMInstallFatalErrorHandler', - 'LLVMInstructionClone', 'LLVMInstructionEraseFromParent', - 'LLVMInstructionGetAllMetadataOtherThanDebugLoc', - 'LLVMInstructionGetDebugLoc', 'LLVMInstructionRemoveFromParent', - 'LLVMInstructionSetDebugLoc', 'LLVMInstructionValueKind', - 'LLVMInt128Type', 'LLVMInt128TypeInContext', 'LLVMInt16Type', - 'LLVMInt16TypeInContext', 'LLVMInt1Type', 'LLVMInt1TypeInContext', - 'LLVMInt32Type', 'LLVMInt32TypeInContext', 'LLVMInt64Type', - 'LLVMInt64TypeInContext', 'LLVMInt8Type', 'LLVMInt8TypeInContext', - 'LLVMIntEQ', 'LLVMIntNE', 'LLVMIntPredicate', - 'LLVMIntPredicate__enumvalues', 'LLVMIntPtrType', - 'LLVMIntPtrTypeForAS', 'LLVMIntPtrTypeForASInContext', - 'LLVMIntPtrTypeInContext', 'LLVMIntSGE', 'LLVMIntSGT', - 'LLVMIntSLE', 'LLVMIntSLT', 'LLVMIntToPtr', 'LLVMIntType', - 'LLVMIntTypeInContext', 'LLVMIntUGE', 'LLVMIntUGT', 'LLVMIntULE', - 'LLVMIntULT', 'LLVMIntegerTypeKind', 'LLVMIntelOCLBICallConv', - 'LLVMInternalLinkage', 'LLVMIntrinsicCopyOverloadedName', - 'LLVMIntrinsicCopyOverloadedName2', 'LLVMIntrinsicGetName', - 'LLVMIntrinsicGetType', 'LLVMIntrinsicIsOverloaded', 'LLVMInvoke', - 'LLVMIsAAddrSpaceCastInst', 'LLVMIsAAllocaInst', - 'LLVMIsAArgument', 'LLVMIsAAtomicCmpXchgInst', - 'LLVMIsAAtomicRMWInst', 'LLVMIsABasicBlock', - 'LLVMIsABinaryOperator', 'LLVMIsABitCastInst', - 'LLVMIsABlockAddress', 'LLVMIsABranchInst', 'LLVMIsACallBrInst', - 'LLVMIsACallInst', 'LLVMIsACastInst', 'LLVMIsACatchPadInst', - 'LLVMIsACatchReturnInst', 'LLVMIsACatchSwitchInst', - 'LLVMIsACleanupPadInst', 'LLVMIsACleanupReturnInst', - 'LLVMIsACmpInst', 'LLVMIsAConstant', - 'LLVMIsAConstantAggregateZero', 'LLVMIsAConstantArray', - 'LLVMIsAConstantDataArray', 'LLVMIsAConstantDataSequential', - 'LLVMIsAConstantDataVector', 'LLVMIsAConstantExpr', - 'LLVMIsAConstantFP', 'LLVMIsAConstantInt', - 'LLVMIsAConstantPointerNull', 'LLVMIsAConstantStruct', - 'LLVMIsAConstantTokenNone', 'LLVMIsAConstantVector', - 'LLVMIsADbgDeclareInst', 'LLVMIsADbgInfoIntrinsic', - 'LLVMIsADbgLabelInst', 'LLVMIsADbgVariableIntrinsic', - 'LLVMIsAExtractElementInst', 'LLVMIsAExtractValueInst', - 'LLVMIsAFCmpInst', 'LLVMIsAFPExtInst', 'LLVMIsAFPToSIInst', - 'LLVMIsAFPToUIInst', 'LLVMIsAFPTruncInst', 'LLVMIsAFenceInst', - 'LLVMIsAFreezeInst', 'LLVMIsAFuncletPadInst', 'LLVMIsAFunction', - 'LLVMIsAGetElementPtrInst', 'LLVMIsAGlobalAlias', - 'LLVMIsAGlobalIFunc', 'LLVMIsAGlobalObject', 'LLVMIsAGlobalValue', - 'LLVMIsAGlobalVariable', 'LLVMIsAICmpInst', - 'LLVMIsAIndirectBrInst', 'LLVMIsAInlineAsm', - 'LLVMIsAInsertElementInst', 'LLVMIsAInsertValueInst', - 'LLVMIsAInstruction', 'LLVMIsAIntToPtrInst', - 'LLVMIsAIntrinsicInst', 'LLVMIsAInvokeInst', - 'LLVMIsALandingPadInst', 'LLVMIsALoadInst', 'LLVMIsAMDNode', - 'LLVMIsAMDString', 'LLVMIsAMemCpyInst', 'LLVMIsAMemIntrinsic', - 'LLVMIsAMemMoveInst', 'LLVMIsAMemSetInst', 'LLVMIsAPHINode', - 'LLVMIsAPoisonValue', 'LLVMIsAPtrToIntInst', 'LLVMIsAResumeInst', - 'LLVMIsAReturnInst', 'LLVMIsASExtInst', 'LLVMIsASIToFPInst', - 'LLVMIsASelectInst', 'LLVMIsAShuffleVectorInst', - 'LLVMIsAStoreInst', 'LLVMIsASwitchInst', 'LLVMIsATerminatorInst', - 'LLVMIsATruncInst', 'LLVMIsAUIToFPInst', - 'LLVMIsAUnaryInstruction', 'LLVMIsAUnaryOperator', - 'LLVMIsAUndefValue', 'LLVMIsAUnreachableInst', 'LLVMIsAUser', - 'LLVMIsAVAArgInst', 'LLVMIsAZExtInst', 'LLVMIsAtomicSingleThread', - 'LLVMIsCleanup', 'LLVMIsConditional', 'LLVMIsConstant', - 'LLVMIsConstantString', 'LLVMIsDeclaration', - 'LLVMIsEnumAttribute', 'LLVMIsExternallyInitialized', - 'LLVMIsFunctionVarArg', 'LLVMIsGlobalConstant', 'LLVMIsInBounds', - 'LLVMIsLiteralStruct', 'LLVMIsMultithreaded', 'LLVMIsNull', - 'LLVMIsOpaqueStruct', 'LLVMIsPackedStruct', 'LLVMIsPoison', - 'LLVMIsRelocationIteratorAtEnd', 'LLVMIsSectionIteratorAtEnd', - 'LLVMIsStringAttribute', 'LLVMIsSymbolIteratorAtEnd', - 'LLVMIsTailCall', 'LLVMIsThreadLocal', 'LLVMIsTypeAttribute', - 'LLVMIsUndef', 'LLVMJITCSymbolMapPair', 'LLVMJITEvaluatedSymbol', - 'LLVMJITEventListenerRef', 'LLVMJITSymbolFlags', - 'LLVMJITSymbolGenericFlags', 'LLVMJITSymbolGenericFlagsCallable', - 'LLVMJITSymbolGenericFlagsExported', - 'LLVMJITSymbolGenericFlagsMaterializationSideEffectsOnly', - 'LLVMJITSymbolGenericFlagsWeak', - 'LLVMJITSymbolGenericFlags__enumvalues', - 'LLVMJITSymbolTargetFlags', 'LLVMLShr', 'LLVMLabelType', - 'LLVMLabelTypeInContext', 'LLVMLabelTypeKind', 'LLVMLandingPad', - 'LLVMLandingPadCatch', 'LLVMLandingPadClauseTy', - 'LLVMLandingPadClauseTy__enumvalues', 'LLVMLandingPadFilter', - 'LLVMLargestComdatSelectionKind', 'LLVMLinkInInterpreter', - 'LLVMLinkInMCJIT', 'LLVMLinkModules2', 'LLVMLinkOnceAnyLinkage', - 'LLVMLinkOnceODRAutoHideLinkage', 'LLVMLinkOnceODRLinkage', - 'LLVMLinkage', 'LLVMLinkage__enumvalues', - 'LLVMLinkerDestroySource', 'LLVMLinkerMode', - 'LLVMLinkerMode__enumvalues', 'LLVMLinkerPreserveSource_Removed', - 'LLVMLinkerPrivateLinkage', 'LLVMLinkerPrivateWeakLinkage', - 'LLVMLittleEndian', 'LLVMLoad', 'LLVMLoadLibraryPermanently', - 'LLVMLocalAsMetadataMetadataKind', 'LLVMLocalDynamicTLSModel', - 'LLVMLocalExecTLSModel', 'LLVMLocalUnnamedAddr', - 'LLVMLookupIntrinsicID', 'LLVMMCJITMemoryManagerRef', - 'LLVMMDNode', 'LLVMMDNodeInContext', 'LLVMMDNodeInContext2', - 'LLVMMDString', 'LLVMMDStringInContext', 'LLVMMDStringInContext2', - 'LLVMMDStringMetadataKind', 'LLVMMDTupleMetadataKind', - 'LLVMMSP430BUILTINCallConv', 'LLVMMSP430INTRCallConv', - 'LLVMMachOUniversalBinaryCopyObjectForArch', - 'LLVMMemoryBufferRef', 'LLVMMemoryDefValueKind', - 'LLVMMemoryManagerAllocateCodeSectionCallback', - 'LLVMMemoryManagerAllocateDataSectionCallback', - 'LLVMMemoryManagerDestroyCallback', - 'LLVMMemoryManagerFinalizeMemoryCallback', - 'LLVMMemoryPhiValueKind', 'LLVMMemoryUseValueKind', - 'LLVMMetadataAsValue', 'LLVMMetadataAsValueValueKind', - 'LLVMMetadataKind', 'LLVMMetadataRef', - 'LLVMMetadataReplaceAllUsesWith', 'LLVMMetadataTypeInContext', - 'LLVMMetadataTypeKind', 'LLVMModuleCreateWithName', - 'LLVMModuleCreateWithNameInContext', 'LLVMModuleFlagBehavior', - 'LLVMModuleFlagBehaviorAppend', - 'LLVMModuleFlagBehaviorAppendUnique', - 'LLVMModuleFlagBehaviorError', 'LLVMModuleFlagBehaviorOverride', - 'LLVMModuleFlagBehaviorRequire', 'LLVMModuleFlagBehaviorWarning', - 'LLVMModuleFlagBehavior__enumvalues', - 'LLVMModuleFlagEntriesGetFlagBehavior', - 'LLVMModuleFlagEntriesGetKey', 'LLVMModuleFlagEntriesGetMetadata', - 'LLVMModuleFlagEntry', 'LLVMModuleProviderRef', 'LLVMModuleRef', - 'LLVMMoveBasicBlockAfter', 'LLVMMoveBasicBlockBefore', - 'LLVMMoveToContainingSection', 'LLVMMoveToNextRelocation', - 'LLVMMoveToNextSection', 'LLVMMoveToNextSymbol', 'LLVMMul', - 'LLVMNamedMDNodeRef', 'LLVMNoDeduplicateComdatSelectionKind', - 'LLVMNoUnnamedAddr', 'LLVMNormalizeTargetTriple', - 'LLVMNotThreadLocal', 'LLVMObjectFile', - 'LLVMObjectFileCopySectionIterator', - 'LLVMObjectFileCopySymbolIterator', - 'LLVMObjectFileIsSectionIteratorAtEnd', - 'LLVMObjectFileIsSymbolIteratorAtEnd', 'LLVMObjectFileRef', - 'LLVMOffsetOfElement', 'LLVMOpInfoCallback', 'LLVMOpcode', - 'LLVMOpcode__enumvalues', 'LLVMOr', 'LLVMOrcAbsoluteSymbols', - 'LLVMOrcCAPIDefinitionGeneratorTryToGenerateFunction', - 'LLVMOrcCDependenceMapPair', 'LLVMOrcCDependenceMapPairs', - 'LLVMOrcCLookupSet', 'LLVMOrcCLookupSetElement', - 'LLVMOrcCSymbolAliasMapEntry', 'LLVMOrcCSymbolAliasMapPair', - 'LLVMOrcCSymbolAliasMapPairs', 'LLVMOrcCSymbolFlagsMapPair', - 'LLVMOrcCSymbolFlagsMapPairs', 'LLVMOrcCSymbolMapPairs', - 'LLVMOrcCSymbolsList', - 'LLVMOrcCreateCustomCAPIDefinitionGenerator', - 'LLVMOrcCreateCustomMaterializationUnit', - 'LLVMOrcCreateDumpObjects', - 'LLVMOrcCreateDynamicLibrarySearchGeneratorForPath', - 'LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess', - 'LLVMOrcCreateLLJIT', 'LLVMOrcCreateLLJITBuilder', - 'LLVMOrcCreateLocalIndirectStubsManager', - 'LLVMOrcCreateLocalLazyCallThroughManager', - 'LLVMOrcCreateNewThreadSafeContext', - 'LLVMOrcCreateNewThreadSafeModule', - 'LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager', - 'LLVMOrcCreateStaticLibrarySearchGeneratorForPath', - 'LLVMOrcDefinitionGeneratorRef', 'LLVMOrcDisposeCSymbolFlagsMap', - 'LLVMOrcDisposeDefinitionGenerator', 'LLVMOrcDisposeDumpObjects', - 'LLVMOrcDisposeIndirectStubsManager', - 'LLVMOrcDisposeJITTargetMachineBuilder', 'LLVMOrcDisposeLLJIT', - 'LLVMOrcDisposeLLJITBuilder', - 'LLVMOrcDisposeLazyCallThroughManager', - 'LLVMOrcDisposeMaterializationResponsibility', - 'LLVMOrcDisposeMaterializationUnit', 'LLVMOrcDisposeObjectLayer', - 'LLVMOrcDisposeSymbols', 'LLVMOrcDisposeThreadSafeContext', - 'LLVMOrcDisposeThreadSafeModule', 'LLVMOrcDumpObjectsRef', - 'LLVMOrcDumpObjects_CallOperator', 'LLVMOrcErrorReporterFunction', - 'LLVMOrcExecutionSessionCreateBareJITDylib', - 'LLVMOrcExecutionSessionCreateJITDylib', - 'LLVMOrcExecutionSessionGetJITDylibByName', - 'LLVMOrcExecutionSessionGetSymbolStringPool', - 'LLVMOrcExecutionSessionIntern', 'LLVMOrcExecutionSessionRef', - 'LLVMOrcExecutionSessionSetErrorReporter', - 'LLVMOrcExecutorAddress', - 'LLVMOrcGenericIRModuleOperationFunction', - 'LLVMOrcIRTransformLayerEmit', 'LLVMOrcIRTransformLayerRef', - 'LLVMOrcIRTransformLayerSetTransform', - 'LLVMOrcIRTransformLayerTransformFunction', - 'LLVMOrcIndirectStubsManagerRef', 'LLVMOrcJITDylibAddGenerator', - 'LLVMOrcJITDylibClear', 'LLVMOrcJITDylibCreateResourceTracker', - 'LLVMOrcJITDylibDefine', - 'LLVMOrcJITDylibGetDefaultResourceTracker', - 'LLVMOrcJITDylibLookupFlags', - 'LLVMOrcJITDylibLookupFlagsMatchAllSymbols', - 'LLVMOrcJITDylibLookupFlagsMatchExportedSymbolsOnly', - 'LLVMOrcJITDylibLookupFlags__enumvalues', 'LLVMOrcJITDylibRef', - 'LLVMOrcJITTargetAddress', - 'LLVMOrcJITTargetMachineBuilderCreateFromTargetMachine', - 'LLVMOrcJITTargetMachineBuilderDetectHost', - 'LLVMOrcJITTargetMachineBuilderGetTargetTriple', - 'LLVMOrcJITTargetMachineBuilderRef', - 'LLVMOrcJITTargetMachineBuilderSetTargetTriple', - 'LLVMOrcLLJITAddLLVMIRModule', - 'LLVMOrcLLJITAddLLVMIRModuleWithRT', 'LLVMOrcLLJITAddObjectFile', - 'LLVMOrcLLJITAddObjectFileWithRT', - 'LLVMOrcLLJITBuilderObjectLinkingLayerCreatorFunction', - 'LLVMOrcLLJITBuilderRef', - 'LLVMOrcLLJITBuilderSetJITTargetMachineBuilder', - 'LLVMOrcLLJITBuilderSetObjectLinkingLayerCreator', - 'LLVMOrcLLJITGetDataLayoutStr', 'LLVMOrcLLJITGetExecutionSession', - 'LLVMOrcLLJITGetGlobalPrefix', 'LLVMOrcLLJITGetIRTransformLayer', - 'LLVMOrcLLJITGetMainJITDylib', 'LLVMOrcLLJITGetObjLinkingLayer', - 'LLVMOrcLLJITGetObjTransformLayer', 'LLVMOrcLLJITGetTripleString', - 'LLVMOrcLLJITLookup', 'LLVMOrcLLJITMangleAndIntern', - 'LLVMOrcLLJITRef', 'LLVMOrcLazyCallThroughManagerRef', - 'LLVMOrcLazyReexports', 'LLVMOrcLookupKind', - 'LLVMOrcLookupKindDLSym', 'LLVMOrcLookupKindStatic', - 'LLVMOrcLookupKind__enumvalues', 'LLVMOrcLookupStateRef', - 'LLVMOrcMaterializationResponsibilityAddDependencies', - 'LLVMOrcMaterializationResponsibilityAddDependenciesForAll', - 'LLVMOrcMaterializationResponsibilityDefineMaterializing', - 'LLVMOrcMaterializationResponsibilityDelegate', - 'LLVMOrcMaterializationResponsibilityFailMaterialization', - 'LLVMOrcMaterializationResponsibilityGetExecutionSession', - 'LLVMOrcMaterializationResponsibilityGetInitializerSymbol', - 'LLVMOrcMaterializationResponsibilityGetRequestedSymbols', - 'LLVMOrcMaterializationResponsibilityGetSymbols', - 'LLVMOrcMaterializationResponsibilityGetTargetDylib', - 'LLVMOrcMaterializationResponsibilityNotifyEmitted', - 'LLVMOrcMaterializationResponsibilityNotifyResolved', - 'LLVMOrcMaterializationResponsibilityRef', - 'LLVMOrcMaterializationResponsibilityReplace', - 'LLVMOrcMaterializationUnitDestroyFunction', - 'LLVMOrcMaterializationUnitDiscardFunction', - 'LLVMOrcMaterializationUnitMaterializeFunction', - 'LLVMOrcMaterializationUnitRef', - 'LLVMOrcObjectLayerAddObjectFile', - 'LLVMOrcObjectLayerAddObjectFileWithRT', 'LLVMOrcObjectLayerEmit', - 'LLVMOrcObjectLayerRef', 'LLVMOrcObjectLinkingLayerRef', - 'LLVMOrcObjectTransformLayerRef', - 'LLVMOrcObjectTransformLayerSetTransform', - 'LLVMOrcObjectTransformLayerTransformFunction', - 'LLVMOrcRTDyldObjectLinkingLayerRegisterJITEventListener', - 'LLVMOrcReleaseResourceTracker', - 'LLVMOrcReleaseSymbolStringPoolEntry', - 'LLVMOrcResourceTrackerRef', 'LLVMOrcResourceTrackerRemove', - 'LLVMOrcResourceTrackerTransferTo', - 'LLVMOrcRetainSymbolStringPoolEntry', 'LLVMOrcSymbolLookupFlags', - 'LLVMOrcSymbolLookupFlagsRequiredSymbol', - 'LLVMOrcSymbolLookupFlagsWeaklyReferencedSymbol', - 'LLVMOrcSymbolLookupFlags__enumvalues', 'LLVMOrcSymbolPredicate', - 'LLVMOrcSymbolStringPoolClearDeadEntries', - 'LLVMOrcSymbolStringPoolEntryRef', - 'LLVMOrcSymbolStringPoolEntryStr', 'LLVMOrcSymbolStringPoolRef', - 'LLVMOrcThreadSafeContextGetContext', - 'LLVMOrcThreadSafeContextRef', 'LLVMOrcThreadSafeModuleRef', - 'LLVMOrcThreadSafeModuleWithModuleDo', 'LLVMPHI', - 'LLVMPPCFP128Type', 'LLVMPPCFP128TypeInContext', - 'LLVMPPC_FP128TypeKind', 'LLVMPTXDeviceCallConv', - 'LLVMPTXKernelCallConv', 'LLVMParseBitcode', 'LLVMParseBitcode2', - 'LLVMParseBitcodeInContext', 'LLVMParseBitcodeInContext2', - 'LLVMParseCommandLineOptions', 'LLVMParseIRInContext', - 'LLVMPassBuilderOptionsRef', - 'LLVMPassBuilderOptionsSetCallGraphProfile', - 'LLVMPassBuilderOptionsSetDebugLogging', - 'LLVMPassBuilderOptionsSetForgetAllSCEVInLoopUnroll', - 'LLVMPassBuilderOptionsSetLicmMssaNoAccForPromotionCap', - 'LLVMPassBuilderOptionsSetLicmMssaOptCap', - 'LLVMPassBuilderOptionsSetLoopInterleaving', - 'LLVMPassBuilderOptionsSetLoopUnrolling', - 'LLVMPassBuilderOptionsSetLoopVectorization', - 'LLVMPassBuilderOptionsSetMergeFunctions', - 'LLVMPassBuilderOptionsSetSLPVectorization', - 'LLVMPassBuilderOptionsSetVerifyEach', - 'LLVMPassManagerBuilderAddCoroutinePassesToExtensionPoints', - 'LLVMPassManagerBuilderCreate', 'LLVMPassManagerBuilderDispose', - 'LLVMPassManagerBuilderPopulateFunctionPassManager', - 'LLVMPassManagerBuilderPopulateLTOPassManager', - 'LLVMPassManagerBuilderPopulateModulePassManager', - 'LLVMPassManagerBuilderRef', - 'LLVMPassManagerBuilderSetDisableSimplifyLibCalls', - 'LLVMPassManagerBuilderSetDisableUnitAtATime', - 'LLVMPassManagerBuilderSetDisableUnrollLoops', - 'LLVMPassManagerBuilderSetOptLevel', - 'LLVMPassManagerBuilderSetSizeLevel', - 'LLVMPassManagerBuilderUseInlinerWithThreshold', - 'LLVMPassManagerRef', 'LLVMPassRegistryRef', 'LLVMPointerSize', - 'LLVMPointerSizeForAS', 'LLVMPointerType', 'LLVMPointerTypeKind', - 'LLVMPoisonValueValueKind', 'LLVMPositionBuilder', - 'LLVMPositionBuilderAtEnd', 'LLVMPositionBuilderBefore', - 'LLVMPreferredAlignmentOfGlobal', 'LLVMPreferredAlignmentOfType', - 'LLVMPreserveAllCallConv', 'LLVMPreserveMostCallConv', - 'LLVMPrintMessageAction', 'LLVMPrintModuleToFile', - 'LLVMPrintModuleToString', 'LLVMPrintTypeToString', - 'LLVMPrintValueToString', 'LLVMPrivateLinkage', - 'LLVMProtectedVisibility', 'LLVMPtrToInt', 'LLVMRealOEQ', - 'LLVMRealOGE', 'LLVMRealOGT', 'LLVMRealOLE', 'LLVMRealOLT', - 'LLVMRealONE', 'LLVMRealORD', 'LLVMRealPredicate', - 'LLVMRealPredicateFalse', 'LLVMRealPredicateTrue', - 'LLVMRealPredicate__enumvalues', 'LLVMRealUEQ', 'LLVMRealUGE', - 'LLVMRealUGT', 'LLVMRealULE', 'LLVMRealULT', 'LLVMRealUNE', - 'LLVMRealUNO', 'LLVMRecompileAndRelinkFunction', - 'LLVMRelocDefault', 'LLVMRelocDynamicNoPic', 'LLVMRelocMode', - 'LLVMRelocMode__enumvalues', 'LLVMRelocPIC', 'LLVMRelocROPI', - 'LLVMRelocROPI_RWPI', 'LLVMRelocRWPI', 'LLVMRelocStatic', - 'LLVMRelocationIteratorRef', 'LLVMRemarkArgGetDebugLoc', - 'LLVMRemarkArgGetKey', 'LLVMRemarkArgGetValue', - 'LLVMRemarkArgRef', 'LLVMRemarkDebugLocGetSourceColumn', - 'LLVMRemarkDebugLocGetSourceFilePath', - 'LLVMRemarkDebugLocGetSourceLine', 'LLVMRemarkDebugLocRef', - 'LLVMRemarkEntryDispose', 'LLVMRemarkEntryGetDebugLoc', - 'LLVMRemarkEntryGetFirstArg', 'LLVMRemarkEntryGetFunctionName', - 'LLVMRemarkEntryGetHotness', 'LLVMRemarkEntryGetNextArg', - 'LLVMRemarkEntryGetNumArgs', 'LLVMRemarkEntryGetPassName', - 'LLVMRemarkEntryGetRemarkName', 'LLVMRemarkEntryGetType', - 'LLVMRemarkEntryRef', 'LLVMRemarkParserCreateBitstream', - 'LLVMRemarkParserCreateYAML', 'LLVMRemarkParserDispose', - 'LLVMRemarkParserGetErrorMessage', 'LLVMRemarkParserGetNext', - 'LLVMRemarkParserHasError', 'LLVMRemarkParserRef', - 'LLVMRemarkStringGetData', 'LLVMRemarkStringGetLen', - 'LLVMRemarkStringRef', 'LLVMRemarkType', 'LLVMRemarkTypeAnalysis', - 'LLVMRemarkTypeAnalysisAliasing', - 'LLVMRemarkTypeAnalysisFPCommute', 'LLVMRemarkTypeFailure', - 'LLVMRemarkTypeMissed', 'LLVMRemarkTypePassed', - 'LLVMRemarkTypeUnknown', 'LLVMRemarkVersion', - 'LLVMRemoveBasicBlockFromParent', - 'LLVMRemoveCallSiteEnumAttribute', - 'LLVMRemoveCallSiteStringAttribute', - 'LLVMRemoveEnumAttributeAtIndex', 'LLVMRemoveGlobalIFunc', - 'LLVMRemoveModule', 'LLVMRemoveStringAttributeAtIndex', - 'LLVMReplaceAllUsesWith', 'LLVMResetFatalErrorHandler', - 'LLVMResume', 'LLVMRet', 'LLVMReturnStatusAction', - 'LLVMRunFunction', 'LLVMRunFunctionAsMain', - 'LLVMRunFunctionPassManager', 'LLVMRunPassManager', - 'LLVMRunPasses', 'LLVMRunStaticConstructors', - 'LLVMRunStaticDestructors', 'LLVMSDiv', 'LLVMSExt', 'LLVMSIToFP', - 'LLVMSPIRFUNCCallConv', 'LLVMSPIRKERNELCallConv', 'LLVMSRem', - 'LLVMSameSizeComdatSelectionKind', 'LLVMScalableVectorType', - 'LLVMScalableVectorTypeKind', 'LLVMSearchForAddressOfSymbol', - 'LLVMSectionIteratorRef', 'LLVMSelect', 'LLVMSetAlignment', - 'LLVMSetArgOperand', 'LLVMSetAtomicRMWBinOp', - 'LLVMSetAtomicSingleThread', 'LLVMSetCleanup', - 'LLVMSetCmpXchgFailureOrdering', 'LLVMSetCmpXchgSuccessOrdering', - 'LLVMSetComdat', 'LLVMSetComdatSelectionKind', 'LLVMSetCondition', - 'LLVMSetCurrentDebugLocation', 'LLVMSetCurrentDebugLocation2', - 'LLVMSetDLLStorageClass', 'LLVMSetDataLayout', - 'LLVMSetDisasmOptions', 'LLVMSetExternallyInitialized', - 'LLVMSetFunctionCallConv', 'LLVMSetGC', 'LLVMSetGlobalConstant', - 'LLVMSetGlobalIFuncResolver', 'LLVMSetInitializer', - 'LLVMSetInstDebugLocation', 'LLVMSetInstrParamAlignment', - 'LLVMSetInstructionCallConv', 'LLVMSetIsInBounds', - 'LLVMSetLinkage', 'LLVMSetMetadata', 'LLVMSetModuleDataLayout', - 'LLVMSetModuleIdentifier', 'LLVMSetModuleInlineAsm', - 'LLVMSetModuleInlineAsm2', 'LLVMSetNormalDest', 'LLVMSetOperand', - 'LLVMSetOrdering', 'LLVMSetParamAlignment', - 'LLVMSetParentCatchSwitch', 'LLVMSetPersonalityFn', - 'LLVMSetSection', 'LLVMSetSourceFileName', 'LLVMSetSubprogram', - 'LLVMSetSuccessor', 'LLVMSetTailCall', 'LLVMSetTarget', - 'LLVMSetTargetMachineAsmVerbosity', 'LLVMSetThreadLocal', - 'LLVMSetThreadLocalMode', 'LLVMSetUnnamedAddr', - 'LLVMSetUnnamedAddress', 'LLVMSetUnwindDest', 'LLVMSetValueName', - 'LLVMSetValueName2', 'LLVMSetVisibility', 'LLVMSetVolatile', - 'LLVMSetWeak', 'LLVMShl', 'LLVMShuffleVector', 'LLVMShutdown', - 'LLVMSizeOf', 'LLVMSizeOfTypeInBits', 'LLVMStartMultithreaded', - 'LLVMStopMultithreaded', 'LLVMStore', 'LLVMStoreSizeOfType', - 'LLVMStripModuleDebugInfo', 'LLVMStructCreateNamed', - 'LLVMStructGetTypeAtIndex', 'LLVMStructSetBody', 'LLVMStructType', - 'LLVMStructTypeInContext', 'LLVMStructTypeKind', 'LLVMSub', - 'LLVMSwiftCallConv', 'LLVMSwitch', 'LLVMSymbolIteratorRef', - 'LLVMSymbolLookupCallback', 'LLVMTargetDataRef', - 'LLVMTargetHasAsmBackend', 'LLVMTargetHasJIT', - 'LLVMTargetHasTargetMachine', 'LLVMTargetLibraryInfoRef', - 'LLVMTargetMachineEmitToFile', - 'LLVMTargetMachineEmitToMemoryBuffer', 'LLVMTargetMachineRef', - 'LLVMTargetRef', 'LLVMTemporaryMDNode', 'LLVMThreadLocalMode', - 'LLVMThreadLocalMode__enumvalues', 'LLVMTokenTypeInContext', - 'LLVMTokenTypeKind', 'LLVMTrunc', 'LLVMTypeIsSized', - 'LLVMTypeKind', 'LLVMTypeKind__enumvalues', 'LLVMTypeOf', - 'LLVMTypeRef', 'LLVMUDiv', 'LLVMUIToFP', 'LLVMURem', - 'LLVMUndefValueValueKind', 'LLVMUnnamedAddr', - 'LLVMUnnamedAddr__enumvalues', 'LLVMUnreachable', 'LLVMUseRef', - 'LLVMUserOp1', 'LLVMUserOp2', 'LLVMVAArg', - 'LLVMValueAsBasicBlock', 'LLVMValueAsMetadata', - 'LLVMValueIsBasicBlock', 'LLVMValueKind', - 'LLVMValueKind__enumvalues', 'LLVMValueMetadataEntriesGetKind', - 'LLVMValueMetadataEntriesGetMetadata', 'LLVMValueMetadataEntry', - 'LLVMValueRef', 'LLVMVectorType', 'LLVMVectorTypeKind', - 'LLVMVerifierFailureAction', - 'LLVMVerifierFailureAction__enumvalues', 'LLVMVerifyFunction', - 'LLVMVerifyModule', 'LLVMViewFunctionCFG', - 'LLVMViewFunctionCFGOnly', 'LLVMVisibility', - 'LLVMVisibility__enumvalues', 'LLVMVoidType', - 'LLVMVoidTypeInContext', 'LLVMVoidTypeKind', 'LLVMWeakAnyLinkage', - 'LLVMWeakODRLinkage', 'LLVMWebKitJSCallConv', 'LLVMWin64CallConv', - 'LLVMWriteBitcodeToFD', 'LLVMWriteBitcodeToFile', - 'LLVMWriteBitcodeToFileHandle', 'LLVMWriteBitcodeToMemoryBuffer', - 'LLVMX8664SysVCallConv', 'LLVMX86AMXType', - 'LLVMX86AMXTypeInContext', 'LLVMX86FP80Type', - 'LLVMX86FP80TypeInContext', 'LLVMX86FastcallCallConv', - 'LLVMX86INTRCallConv', 'LLVMX86MMXType', - 'LLVMX86MMXTypeInContext', 'LLVMX86RegCallCallConv', - 'LLVMX86StdcallCallConv', 'LLVMX86ThisCallCallConv', - 'LLVMX86VectorCallCallConv', 'LLVMX86_AMXTypeKind', - 'LLVMX86_FP80TypeKind', 'LLVMX86_MMXTypeKind', 'LLVMXor', - 'LLVMYieldCallback', 'LLVMZExt', 'LLVM_C_ANALYSIS_H', - 'LLVM_C_BITREADER_H', 'LLVM_C_BITWRITER_H', 'LLVM_C_COMDAT_H', - 'LLVM_C_CORE_H', 'LLVM_C_DATATYPES_H', 'LLVM_C_DEBUGINFO_H', - 'LLVM_C_DEPRECATED_H', 'LLVM_C_DISASSEMBLERTYPES_H', - 'LLVM_C_DISASSEMBLER_H', 'LLVM_C_ERRORHANDLING_H', - 'LLVM_C_ERROR_H', 'LLVM_C_EXECUTIONENGINE_H', 'LLVM_C_EXTERNC_H', - 'LLVM_C_INITIALIZATION_H', 'LLVM_C_IRREADER_H', 'LLVM_C_LINKER_H', - 'LLVM_C_LLJIT_H', 'LLVM_C_LTO_H', 'LLVM_C_OBJECT_H', - 'LLVM_C_ORCEE_H', 'LLVM_C_ORC_H', 'LLVM_C_REMARKS_H', - 'LLVM_C_SUPPORT_H', 'LLVM_C_TARGETMACHINE_H', 'LLVM_C_TARGET_H', - 'LLVM_C_TRANSFORMS_AGGRESSIVEINSTCOMBINE_H', - 'LLVM_C_TRANSFORMS_COROUTINES_H', - 'LLVM_C_TRANSFORMS_INSTCOMBINE_H', 'LLVM_C_TRANSFORMS_IPO_H', - 'LLVM_C_TRANSFORMS_PASSBUILDER_H', - 'LLVM_C_TRANSFORMS_PASSMANAGERBUILDER_H', - 'LLVM_C_TRANSFORMS_SCALAR_H', 'LLVM_C_TRANSFORMS_UTILS_H', - 'LLVM_C_TRANSFORMS_VECTORIZE_H', 'LLVM_C_TYPES_H', - 'LTOObjectBuffer', 'LTO_API_VERSION', - 'LTO_CODEGEN_PIC_MODEL_DEFAULT', 'LTO_CODEGEN_PIC_MODEL_DYNAMIC', - 'LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC', - 'LTO_CODEGEN_PIC_MODEL_STATIC', 'LTO_DEBUG_MODEL_DWARF', - 'LTO_DEBUG_MODEL_NONE', 'LTO_DS_ERROR', 'LTO_DS_NOTE', - 'LTO_DS_REMARK', 'LTO_DS_WARNING', 'LTO_SYMBOL_ALIAS', - 'LTO_SYMBOL_ALIGNMENT_MASK', 'LTO_SYMBOL_COMDAT', - 'LTO_SYMBOL_DEFINITION_MASK', 'LTO_SYMBOL_DEFINITION_REGULAR', - 'LTO_SYMBOL_DEFINITION_TENTATIVE', - 'LTO_SYMBOL_DEFINITION_UNDEFINED', 'LTO_SYMBOL_DEFINITION_WEAK', - 'LTO_SYMBOL_DEFINITION_WEAKUNDEF', 'LTO_SYMBOL_PERMISSIONS_CODE', - 'LTO_SYMBOL_PERMISSIONS_DATA', 'LTO_SYMBOL_PERMISSIONS_MASK', - 'LTO_SYMBOL_PERMISSIONS_RODATA', 'LTO_SYMBOL_SCOPE_DEFAULT', - 'LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN', - 'LTO_SYMBOL_SCOPE_HIDDEN', 'LTO_SYMBOL_SCOPE_INTERNAL', - 'LTO_SYMBOL_SCOPE_MASK', 'LTO_SYMBOL_SCOPE_PROTECTED', - 'REMARKS_API_VERSION', 'c__EA_LLVMAtomicOrdering', - 'c__EA_LLVMAtomicRMWBinOp', 'c__EA_LLVMBinaryType', - 'c__EA_LLVMCallConv', 'c__EA_LLVMCodeGenFileType', - 'c__EA_LLVMCodeGenOptLevel', 'c__EA_LLVMCodeModel', - 'c__EA_LLVMComdatSelectionKind', 'c__EA_LLVMDIFlags', - 'c__EA_LLVMDLLStorageClass', 'c__EA_LLVMDWARFEmissionKind', - 'c__EA_LLVMDWARFMacinfoRecordType', - 'c__EA_LLVMDWARFSourceLanguage', 'c__EA_LLVMDiagnosticSeverity', - 'c__EA_LLVMInlineAsmDialect', 'c__EA_LLVMIntPredicate', - 'c__EA_LLVMJITSymbolGenericFlags', 'c__EA_LLVMLandingPadClauseTy', - 'c__EA_LLVMLinkage', 'c__EA_LLVMLinkerMode', - 'c__EA_LLVMModuleFlagBehavior', 'c__EA_LLVMOpcode', - 'c__EA_LLVMOrcJITDylibLookupFlags', 'c__EA_LLVMOrcLookupKind', - 'c__EA_LLVMOrcSymbolLookupFlags', 'c__EA_LLVMRealPredicate', - 'c__EA_LLVMRelocMode', 'c__EA_LLVMThreadLocalMode', - 'c__EA_LLVMTypeKind', 'c__EA_LLVMUnnamedAddr', - 'c__EA_LLVMValueKind', 'c__EA_LLVMVerifierFailureAction', - 'c__EA_LLVMVisibility', 'c__EA_lto_codegen_diagnostic_severity_t', - 'c__EA_lto_codegen_model', 'c__EA_lto_debug_model', - 'c__EA_lto_symbol_attributes', 'c__Ea_LLVMAttributeReturnIndex', - 'c__Ea_LLVMMDStringMetadataKind', 'int64_t', 'lto_api_version', - 'lto_bool_t', 'lto_code_gen_t', 'lto_codegen_add_module', - 'lto_codegen_add_must_preserve_symbol', 'lto_codegen_compile', - 'lto_codegen_compile_optimized', 'lto_codegen_compile_to_file', - 'lto_codegen_create', 'lto_codegen_create_in_local_context', - 'lto_codegen_debug_options', 'lto_codegen_debug_options_array', - 'lto_codegen_diagnostic_severity_t', - 'lto_codegen_diagnostic_severity_t__enumvalues', - 'lto_codegen_dispose', 'lto_codegen_model', - 'lto_codegen_model__enumvalues', 'lto_codegen_optimize', - 'lto_codegen_set_assembler_args', - 'lto_codegen_set_assembler_path', 'lto_codegen_set_cpu', - 'lto_codegen_set_debug_model', - 'lto_codegen_set_diagnostic_handler', 'lto_codegen_set_module', - 'lto_codegen_set_pic_model', - 'lto_codegen_set_should_embed_uselists', - 'lto_codegen_set_should_internalize', - 'lto_codegen_write_merged_modules', 'lto_debug_model', - 'lto_debug_model__enumvalues', 'lto_diagnostic_handler_t', - 'lto_get_error_message', 'lto_get_version', - 'lto_initialize_disassembler', 'lto_input_create', - 'lto_input_dispose', 'lto_input_get_dependent_library', - 'lto_input_get_num_dependent_libraries', 'lto_input_t', - 'lto_module_create', 'lto_module_create_from_fd', - 'lto_module_create_from_fd_at_offset', - 'lto_module_create_from_memory', - 'lto_module_create_from_memory_with_path', - 'lto_module_create_in_codegen_context', - 'lto_module_create_in_local_context', 'lto_module_dispose', - 'lto_module_get_linkeropts', 'lto_module_get_macho_cputype', - 'lto_module_get_num_symbols', 'lto_module_get_symbol_attribute', - 'lto_module_get_symbol_name', 'lto_module_get_target_triple', - 'lto_module_has_ctor_dtor', 'lto_module_has_objc_category', - 'lto_module_is_object_file', - 'lto_module_is_object_file_for_target', - 'lto_module_is_object_file_in_memory', - 'lto_module_is_object_file_in_memory_for_target', - 'lto_module_is_thinlto', 'lto_module_set_target_triple', - 'lto_module_t', 'lto_runtime_lib_symbols_list', - 'lto_set_debug_options', 'lto_symbol_attributes', - 'lto_symbol_attributes__enumvalues', 'off_t', 'size_t', - 'struct_LLVMComdat', 'struct_LLVMMCJITCompilerOptions', - 'struct_LLVMOpInfo1', 'struct_LLVMOpInfoSymbol1', - 'struct_LLVMOpaqueAttributeRef', 'struct_LLVMOpaqueBasicBlock', - 'struct_LLVMOpaqueBinary', 'struct_LLVMOpaqueBuilder', - 'struct_LLVMOpaqueContext', 'struct_LLVMOpaqueDIBuilder', - 'struct_LLVMOpaqueDiagnosticInfo', 'struct_LLVMOpaqueError', - 'struct_LLVMOpaqueExecutionEngine', - 'struct_LLVMOpaqueGenericValue', - 'struct_LLVMOpaqueJITEventListener', - 'struct_LLVMOpaqueLTOCodeGenerator', 'struct_LLVMOpaqueLTOInput', - 'struct_LLVMOpaqueLTOModule', - 'struct_LLVMOpaqueMCJITMemoryManager', - 'struct_LLVMOpaqueMemoryBuffer', 'struct_LLVMOpaqueMetadata', - 'struct_LLVMOpaqueModule', 'struct_LLVMOpaqueModuleFlagEntry', - 'struct_LLVMOpaqueModuleProvider', 'struct_LLVMOpaqueNamedMDNode', - 'struct_LLVMOpaqueObjectFile', - 'struct_LLVMOpaquePassBuilderOptions', - 'struct_LLVMOpaquePassManager', - 'struct_LLVMOpaquePassManagerBuilder', - 'struct_LLVMOpaquePassRegistry', - 'struct_LLVMOpaqueRelocationIterator', - 'struct_LLVMOpaqueSectionIterator', - 'struct_LLVMOpaqueSymbolIterator', 'struct_LLVMOpaqueTargetData', - 'struct_LLVMOpaqueTargetLibraryInfotData', - 'struct_LLVMOpaqueTargetMachine', - 'struct_LLVMOpaqueThinLTOCodeGenerator', 'struct_LLVMOpaqueType', - 'struct_LLVMOpaqueUse', 'struct_LLVMOpaqueValue', - 'struct_LLVMOpaqueValueMetadataEntry', - 'struct_LLVMOrcOpaqueDefinitionGenerator', - 'struct_LLVMOrcOpaqueDumpObjects', - 'struct_LLVMOrcOpaqueExecutionSession', - 'struct_LLVMOrcOpaqueIRTransformLayer', - 'struct_LLVMOrcOpaqueIndirectStubsManager', - 'struct_LLVMOrcOpaqueJITDylib', - 'struct_LLVMOrcOpaqueJITTargetMachineBuilder', - 'struct_LLVMOrcOpaqueLLJIT', 'struct_LLVMOrcOpaqueLLJITBuilder', - 'struct_LLVMOrcOpaqueLazyCallThroughManager', - 'struct_LLVMOrcOpaqueLookupState', - 'struct_LLVMOrcOpaqueMaterializationResponsibility', - 'struct_LLVMOrcOpaqueMaterializationUnit', - 'struct_LLVMOrcOpaqueObjectLayer', - 'struct_LLVMOrcOpaqueObjectLinkingLayer', - 'struct_LLVMOrcOpaqueObjectTransformLayer', - 'struct_LLVMOrcOpaqueResourceTracker', - 'struct_LLVMOrcOpaqueSymbolStringPool', - 'struct_LLVMOrcOpaqueSymbolStringPoolEntry', - 'struct_LLVMOrcOpaqueThreadSafeContext', - 'struct_LLVMOrcOpaqueThreadSafeModule', - 'struct_LLVMRemarkOpaqueArg', 'struct_LLVMRemarkOpaqueDebugLoc', - 'struct_LLVMRemarkOpaqueEntry', 'struct_LLVMRemarkOpaqueParser', - 'struct_LLVMRemarkOpaqueString', 'struct_LLVMTarget', - 'struct_c__SA_LLVMJITCSymbolMapPair', - 'struct_c__SA_LLVMJITEvaluatedSymbol', - 'struct_c__SA_LLVMJITSymbolFlags', - 'struct_c__SA_LLVMOrcCDependenceMapPair', - 'struct_c__SA_LLVMOrcCLookupSetElement', - 'struct_c__SA_LLVMOrcCSymbolAliasMapEntry', - 'struct_c__SA_LLVMOrcCSymbolAliasMapPair', - 'struct_c__SA_LLVMOrcCSymbolFlagsMapPair', - 'struct_c__SA_LLVMOrcCSymbolsList', - 'struct_c__SA_LTOObjectBuffer', 'thinlto_code_gen_t', - 'thinlto_codegen_add_cross_referenced_symbol', - 'thinlto_codegen_add_module', - 'thinlto_codegen_add_must_preserve_symbol', - 'thinlto_codegen_disable_codegen', 'thinlto_codegen_dispose', - 'thinlto_codegen_process', 'thinlto_codegen_set_cache_dir', - 'thinlto_codegen_set_cache_entry_expiration', - 'thinlto_codegen_set_cache_pruning_interval', - 'thinlto_codegen_set_cache_size_bytes', - 'thinlto_codegen_set_cache_size_files', - 'thinlto_codegen_set_cache_size_megabytes', - 'thinlto_codegen_set_codegen_only', 'thinlto_codegen_set_cpu', - 'thinlto_codegen_set_final_cache_size_relative_to_available_space', - 'thinlto_codegen_set_pic_model', - 'thinlto_codegen_set_savetemps_dir', 'thinlto_create_codegen', - 'thinlto_debug_options', 'thinlto_module_get_num_object_files', - 'thinlto_module_get_num_objects', 'thinlto_module_get_object', - 'thinlto_module_get_object_file', - 'thinlto_set_generated_objects_dir', 'uint32_t', 'uint64_t', - 'uint8_t'] +# void llvm_blake3_hasher_init(llvm_blake3_hasher *self) +try: (llvm_blake3_hasher_init:=dll.llvm_blake3_hasher_init).restype, llvm_blake3_hasher_init.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher)] +except AttributeError: pass + +# void llvm_blake3_hasher_init_keyed(llvm_blake3_hasher *self, const uint8_t key[32]) +try: (llvm_blake3_hasher_init_keyed:=dll.llvm_blake3_hasher_init_keyed).restype, llvm_blake3_hasher_init_keyed.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher), (uint8_t * 32)] +except AttributeError: pass + +# void llvm_blake3_hasher_init_derive_key(llvm_blake3_hasher *self, const char *context) +try: (llvm_blake3_hasher_init_derive_key:=dll.llvm_blake3_hasher_init_derive_key).restype, llvm_blake3_hasher_init_derive_key.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void llvm_blake3_hasher_init_derive_key_raw(llvm_blake3_hasher *self, const void *context, size_t context_len) +try: (llvm_blake3_hasher_init_derive_key_raw:=dll.llvm_blake3_hasher_init_derive_key_raw).restype, llvm_blake3_hasher_init_derive_key_raw.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher), ctypes.c_void_p, size_t] +except AttributeError: pass + +# void llvm_blake3_hasher_update(llvm_blake3_hasher *self, const void *input, size_t input_len) +try: (llvm_blake3_hasher_update:=dll.llvm_blake3_hasher_update).restype, llvm_blake3_hasher_update.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher), ctypes.c_void_p, size_t] +except AttributeError: pass + +# void llvm_blake3_hasher_finalize(const llvm_blake3_hasher *self, uint8_t *out, size_t out_len) +try: (llvm_blake3_hasher_finalize:=dll.llvm_blake3_hasher_finalize).restype, llvm_blake3_hasher_finalize.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher), ctypes.POINTER(uint8_t), size_t] +except AttributeError: pass + +# void llvm_blake3_hasher_finalize_seek(const llvm_blake3_hasher *self, uint64_t seek, uint8_t *out, size_t out_len) +try: (llvm_blake3_hasher_finalize_seek:=dll.llvm_blake3_hasher_finalize_seek).restype, llvm_blake3_hasher_finalize_seek.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher), uint64_t, ctypes.POINTER(uint8_t), size_t] +except AttributeError: pass + +# void llvm_blake3_hasher_reset(llvm_blake3_hasher *self) +try: (llvm_blake3_hasher_reset:=dll.llvm_blake3_hasher_reset).restype, llvm_blake3_hasher_reset.argtypes = None, [ctypes.POINTER(llvm_blake3_hasher)] +except AttributeError: pass + +# extern int select(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, struct timeval *restrict __timeout) +try: (select:=dll.select).restype, select.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timeval)] +except AttributeError: pass + +# extern int pselect(int __nfds, fd_set *restrict __readfds, fd_set *restrict __writefds, fd_set *restrict __exceptfds, const struct timespec *restrict __timeout, const __sigset_t *restrict __sigmask) +try: (pselect:=dll.pselect).restype, pselect.argtypes = ctypes.c_int32, [ctypes.c_int32, ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(fd_set), ctypes.POINTER(struct_timespec), ctypes.POINTER(__sigset_t)] +except AttributeError: pass + +lto_bool_t = ctypes.c_bool +lto_symbol_attributes = CEnum(ctypes.c_uint32) +LTO_SYMBOL_ALIGNMENT_MASK = lto_symbol_attributes.define('LTO_SYMBOL_ALIGNMENT_MASK', 31) +LTO_SYMBOL_PERMISSIONS_MASK = lto_symbol_attributes.define('LTO_SYMBOL_PERMISSIONS_MASK', 224) +LTO_SYMBOL_PERMISSIONS_CODE = lto_symbol_attributes.define('LTO_SYMBOL_PERMISSIONS_CODE', 160) +LTO_SYMBOL_PERMISSIONS_DATA = lto_symbol_attributes.define('LTO_SYMBOL_PERMISSIONS_DATA', 192) +LTO_SYMBOL_PERMISSIONS_RODATA = lto_symbol_attributes.define('LTO_SYMBOL_PERMISSIONS_RODATA', 128) +LTO_SYMBOL_DEFINITION_MASK = lto_symbol_attributes.define('LTO_SYMBOL_DEFINITION_MASK', 1792) +LTO_SYMBOL_DEFINITION_REGULAR = lto_symbol_attributes.define('LTO_SYMBOL_DEFINITION_REGULAR', 256) +LTO_SYMBOL_DEFINITION_TENTATIVE = lto_symbol_attributes.define('LTO_SYMBOL_DEFINITION_TENTATIVE', 512) +LTO_SYMBOL_DEFINITION_WEAK = lto_symbol_attributes.define('LTO_SYMBOL_DEFINITION_WEAK', 768) +LTO_SYMBOL_DEFINITION_UNDEFINED = lto_symbol_attributes.define('LTO_SYMBOL_DEFINITION_UNDEFINED', 1024) +LTO_SYMBOL_DEFINITION_WEAKUNDEF = lto_symbol_attributes.define('LTO_SYMBOL_DEFINITION_WEAKUNDEF', 1280) +LTO_SYMBOL_SCOPE_MASK = lto_symbol_attributes.define('LTO_SYMBOL_SCOPE_MASK', 14336) +LTO_SYMBOL_SCOPE_INTERNAL = lto_symbol_attributes.define('LTO_SYMBOL_SCOPE_INTERNAL', 2048) +LTO_SYMBOL_SCOPE_HIDDEN = lto_symbol_attributes.define('LTO_SYMBOL_SCOPE_HIDDEN', 4096) +LTO_SYMBOL_SCOPE_PROTECTED = lto_symbol_attributes.define('LTO_SYMBOL_SCOPE_PROTECTED', 8192) +LTO_SYMBOL_SCOPE_DEFAULT = lto_symbol_attributes.define('LTO_SYMBOL_SCOPE_DEFAULT', 6144) +LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN = lto_symbol_attributes.define('LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN', 10240) +LTO_SYMBOL_COMDAT = lto_symbol_attributes.define('LTO_SYMBOL_COMDAT', 16384) +LTO_SYMBOL_ALIAS = lto_symbol_attributes.define('LTO_SYMBOL_ALIAS', 32768) + +lto_debug_model = CEnum(ctypes.c_uint32) +LTO_DEBUG_MODEL_NONE = lto_debug_model.define('LTO_DEBUG_MODEL_NONE', 0) +LTO_DEBUG_MODEL_DWARF = lto_debug_model.define('LTO_DEBUG_MODEL_DWARF', 1) + +lto_codegen_model = CEnum(ctypes.c_uint32) +LTO_CODEGEN_PIC_MODEL_STATIC = lto_codegen_model.define('LTO_CODEGEN_PIC_MODEL_STATIC', 0) +LTO_CODEGEN_PIC_MODEL_DYNAMIC = lto_codegen_model.define('LTO_CODEGEN_PIC_MODEL_DYNAMIC', 1) +LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC = lto_codegen_model.define('LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC', 2) +LTO_CODEGEN_PIC_MODEL_DEFAULT = lto_codegen_model.define('LTO_CODEGEN_PIC_MODEL_DEFAULT', 3) + +class struct_LLVMOpaqueLTOModule(Struct): pass +lto_module_t = ctypes.POINTER(struct_LLVMOpaqueLTOModule) +class struct_LLVMOpaqueLTOCodeGenerator(Struct): pass +lto_code_gen_t = ctypes.POINTER(struct_LLVMOpaqueLTOCodeGenerator) +class struct_LLVMOpaqueThinLTOCodeGenerator(Struct): pass +thinlto_code_gen_t = ctypes.POINTER(struct_LLVMOpaqueThinLTOCodeGenerator) +# extern const char *lto_get_version(void) +try: (lto_get_version:=dll.lto_get_version).restype, lto_get_version.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# extern const char *lto_get_error_message(void) +try: (lto_get_error_message:=dll.lto_get_error_message).restype, lto_get_error_message.argtypes = ctypes.POINTER(ctypes.c_char), [] +except AttributeError: pass + +# extern lto_bool_t lto_module_is_object_file(const char *path) +try: (lto_module_is_object_file:=dll.lto_module_is_object_file).restype, lto_module_is_object_file.argtypes = lto_bool_t, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_bool_t lto_module_is_object_file_for_target(const char *path, const char *target_triple_prefix) +try: (lto_module_is_object_file_for_target:=dll.lto_module_is_object_file_for_target).restype, lto_module_is_object_file_for_target.argtypes = lto_bool_t, [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_bool_t lto_module_has_objc_category(const void *mem, size_t length) +try: (lto_module_has_objc_category:=dll.lto_module_has_objc_category).restype, lto_module_has_objc_category.argtypes = lto_bool_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# extern lto_bool_t lto_module_is_object_file_in_memory(const void *mem, size_t length) +try: (lto_module_is_object_file_in_memory:=dll.lto_module_is_object_file_in_memory).restype, lto_module_is_object_file_in_memory.argtypes = lto_bool_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# extern lto_bool_t lto_module_is_object_file_in_memory_for_target(const void *mem, size_t length, const char *target_triple_prefix) +try: (lto_module_is_object_file_in_memory_for_target:=dll.lto_module_is_object_file_in_memory_for_target).restype, lto_module_is_object_file_in_memory_for_target.argtypes = lto_bool_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_module_t lto_module_create(const char *path) +try: (lto_module_create:=dll.lto_module_create).restype, lto_module_create.argtypes = lto_module_t, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_module_t lto_module_create_from_memory(const void *mem, size_t length) +try: (lto_module_create_from_memory:=dll.lto_module_create_from_memory).restype, lto_module_create_from_memory.argtypes = lto_module_t, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# extern lto_module_t lto_module_create_from_memory_with_path(const void *mem, size_t length, const char *path) +try: (lto_module_create_from_memory_with_path:=dll.lto_module_create_from_memory_with_path).restype, lto_module_create_from_memory_with_path.argtypes = lto_module_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_module_t lto_module_create_in_local_context(const void *mem, size_t length, const char *path) +try: (lto_module_create_in_local_context:=dll.lto_module_create_in_local_context).restype, lto_module_create_in_local_context.argtypes = lto_module_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_module_t lto_module_create_in_codegen_context(const void *mem, size_t length, const char *path, lto_code_gen_t cg) +try: (lto_module_create_in_codegen_context:=dll.lto_module_create_in_codegen_context).restype, lto_module_create_in_codegen_context.argtypes = lto_module_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char), lto_code_gen_t] +except AttributeError: pass + +# extern lto_module_t lto_module_create_from_fd(int fd, const char *path, size_t file_size) +try: (lto_module_create_from_fd:=dll.lto_module_create_from_fd).restype, lto_module_create_from_fd.argtypes = lto_module_t, [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +off_t = ctypes.c_int64 +# extern lto_module_t lto_module_create_from_fd_at_offset(int fd, const char *path, size_t file_size, size_t map_size, off_t offset) +try: (lto_module_create_from_fd_at_offset:=dll.lto_module_create_from_fd_at_offset).restype, lto_module_create_from_fd_at_offset.argtypes = lto_module_t, [ctypes.c_int32, ctypes.POINTER(ctypes.c_char), size_t, size_t, off_t] +except AttributeError: pass + +# extern void lto_module_dispose(lto_module_t mod) +try: (lto_module_dispose:=dll.lto_module_dispose).restype, lto_module_dispose.argtypes = None, [lto_module_t] +except AttributeError: pass + +# extern const char *lto_module_get_target_triple(lto_module_t mod) +try: (lto_module_get_target_triple:=dll.lto_module_get_target_triple).restype, lto_module_get_target_triple.argtypes = ctypes.POINTER(ctypes.c_char), [lto_module_t] +except AttributeError: pass + +# extern void lto_module_set_target_triple(lto_module_t mod, const char *triple) +try: (lto_module_set_target_triple:=dll.lto_module_set_target_triple).restype, lto_module_set_target_triple.argtypes = None, [lto_module_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern unsigned int lto_module_get_num_symbols(lto_module_t mod) +try: (lto_module_get_num_symbols:=dll.lto_module_get_num_symbols).restype, lto_module_get_num_symbols.argtypes = ctypes.c_uint32, [lto_module_t] +except AttributeError: pass + +# extern const char *lto_module_get_symbol_name(lto_module_t mod, unsigned int index) +try: (lto_module_get_symbol_name:=dll.lto_module_get_symbol_name).restype, lto_module_get_symbol_name.argtypes = ctypes.POINTER(ctypes.c_char), [lto_module_t, ctypes.c_uint32] +except AttributeError: pass + +# extern lto_symbol_attributes lto_module_get_symbol_attribute(lto_module_t mod, unsigned int index) +try: (lto_module_get_symbol_attribute:=dll.lto_module_get_symbol_attribute).restype, lto_module_get_symbol_attribute.argtypes = lto_symbol_attributes, [lto_module_t, ctypes.c_uint32] +except AttributeError: pass + +# extern const char *lto_module_get_linkeropts(lto_module_t mod) +try: (lto_module_get_linkeropts:=dll.lto_module_get_linkeropts).restype, lto_module_get_linkeropts.argtypes = ctypes.POINTER(ctypes.c_char), [lto_module_t] +except AttributeError: pass + +# extern lto_bool_t lto_module_get_macho_cputype(lto_module_t mod, unsigned int *out_cputype, unsigned int *out_cpusubtype) +try: (lto_module_get_macho_cputype:=dll.lto_module_get_macho_cputype).restype, lto_module_get_macho_cputype.argtypes = lto_bool_t, [lto_module_t, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# extern lto_bool_t lto_module_has_ctor_dtor(lto_module_t mod) +try: (lto_module_has_ctor_dtor:=dll.lto_module_has_ctor_dtor).restype, lto_module_has_ctor_dtor.argtypes = lto_bool_t, [lto_module_t] +except AttributeError: pass + +lto_codegen_diagnostic_severity_t = CEnum(ctypes.c_uint32) +LTO_DS_ERROR = lto_codegen_diagnostic_severity_t.define('LTO_DS_ERROR', 0) +LTO_DS_WARNING = lto_codegen_diagnostic_severity_t.define('LTO_DS_WARNING', 1) +LTO_DS_REMARK = lto_codegen_diagnostic_severity_t.define('LTO_DS_REMARK', 3) +LTO_DS_NOTE = lto_codegen_diagnostic_severity_t.define('LTO_DS_NOTE', 2) + +lto_diagnostic_handler_t = ctypes.CFUNCTYPE(None, lto_codegen_diagnostic_severity_t, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p) +# extern void lto_codegen_set_diagnostic_handler(lto_code_gen_t, lto_diagnostic_handler_t, void *) +try: (lto_codegen_set_diagnostic_handler:=dll.lto_codegen_set_diagnostic_handler).restype, lto_codegen_set_diagnostic_handler.argtypes = None, [lto_code_gen_t, lto_diagnostic_handler_t, ctypes.c_void_p] +except AttributeError: pass + +# extern lto_code_gen_t lto_codegen_create(void) +try: (lto_codegen_create:=dll.lto_codegen_create).restype, lto_codegen_create.argtypes = lto_code_gen_t, [] +except AttributeError: pass + +# extern lto_code_gen_t lto_codegen_create_in_local_context(void) +try: (lto_codegen_create_in_local_context:=dll.lto_codegen_create_in_local_context).restype, lto_codegen_create_in_local_context.argtypes = lto_code_gen_t, [] +except AttributeError: pass + +# extern void lto_codegen_dispose(lto_code_gen_t) +try: (lto_codegen_dispose:=dll.lto_codegen_dispose).restype, lto_codegen_dispose.argtypes = None, [lto_code_gen_t] +except AttributeError: pass + +# extern lto_bool_t lto_codegen_add_module(lto_code_gen_t cg, lto_module_t mod) +try: (lto_codegen_add_module:=dll.lto_codegen_add_module).restype, lto_codegen_add_module.argtypes = lto_bool_t, [lto_code_gen_t, lto_module_t] +except AttributeError: pass + +# extern void lto_codegen_set_module(lto_code_gen_t cg, lto_module_t mod) +try: (lto_codegen_set_module:=dll.lto_codegen_set_module).restype, lto_codegen_set_module.argtypes = None, [lto_code_gen_t, lto_module_t] +except AttributeError: pass + +# extern lto_bool_t lto_codegen_set_debug_model(lto_code_gen_t cg, lto_debug_model) +try: (lto_codegen_set_debug_model:=dll.lto_codegen_set_debug_model).restype, lto_codegen_set_debug_model.argtypes = lto_bool_t, [lto_code_gen_t, lto_debug_model] +except AttributeError: pass + +# extern lto_bool_t lto_codegen_set_pic_model(lto_code_gen_t cg, lto_codegen_model) +try: (lto_codegen_set_pic_model:=dll.lto_codegen_set_pic_model).restype, lto_codegen_set_pic_model.argtypes = lto_bool_t, [lto_code_gen_t, lto_codegen_model] +except AttributeError: pass + +# extern void lto_codegen_set_cpu(lto_code_gen_t cg, const char *cpu) +try: (lto_codegen_set_cpu:=dll.lto_codegen_set_cpu).restype, lto_codegen_set_cpu.argtypes = None, [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void lto_codegen_set_assembler_path(lto_code_gen_t cg, const char *path) +try: (lto_codegen_set_assembler_path:=dll.lto_codegen_set_assembler_path).restype, lto_codegen_set_assembler_path.argtypes = None, [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void lto_codegen_set_assembler_args(lto_code_gen_t cg, const char **args, int nargs) +try: (lto_codegen_set_assembler_args:=dll.lto_codegen_set_assembler_args).restype, lto_codegen_set_assembler_args.argtypes = None, [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern void lto_codegen_add_must_preserve_symbol(lto_code_gen_t cg, const char *symbol) +try: (lto_codegen_add_must_preserve_symbol:=dll.lto_codegen_add_must_preserve_symbol).restype, lto_codegen_add_must_preserve_symbol.argtypes = None, [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern lto_bool_t lto_codegen_write_merged_modules(lto_code_gen_t cg, const char *path) +try: (lto_codegen_write_merged_modules:=dll.lto_codegen_write_merged_modules).restype, lto_codegen_write_merged_modules.argtypes = lto_bool_t, [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern const void *lto_codegen_compile(lto_code_gen_t cg, size_t *length) +try: (lto_codegen_compile:=dll.lto_codegen_compile).restype, lto_codegen_compile.argtypes = ctypes.c_void_p, [lto_code_gen_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern lto_bool_t lto_codegen_compile_to_file(lto_code_gen_t cg, const char **name) +try: (lto_codegen_compile_to_file:=dll.lto_codegen_compile_to_file).restype, lto_codegen_compile_to_file.argtypes = lto_bool_t, [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# extern lto_bool_t lto_codegen_optimize(lto_code_gen_t cg) +try: (lto_codegen_optimize:=dll.lto_codegen_optimize).restype, lto_codegen_optimize.argtypes = lto_bool_t, [lto_code_gen_t] +except AttributeError: pass + +# extern const void *lto_codegen_compile_optimized(lto_code_gen_t cg, size_t *length) +try: (lto_codegen_compile_optimized:=dll.lto_codegen_compile_optimized).restype, lto_codegen_compile_optimized.argtypes = ctypes.c_void_p, [lto_code_gen_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern unsigned int lto_api_version(void) +try: (lto_api_version:=dll.lto_api_version).restype, lto_api_version.argtypes = ctypes.c_uint32, [] +except AttributeError: pass + +# extern void lto_set_debug_options(const char *const *options, int number) +try: (lto_set_debug_options:=dll.lto_set_debug_options).restype, lto_set_debug_options.argtypes = None, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern void lto_codegen_debug_options(lto_code_gen_t cg, const char *) +try: (lto_codegen_debug_options:=dll.lto_codegen_debug_options).restype, lto_codegen_debug_options.argtypes = None, [lto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void lto_codegen_debug_options_array(lto_code_gen_t cg, const char *const *, int number) +try: (lto_codegen_debug_options_array:=dll.lto_codegen_debug_options_array).restype, lto_codegen_debug_options_array.argtypes = None, [lto_code_gen_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern void lto_initialize_disassembler(void) +try: (lto_initialize_disassembler:=dll.lto_initialize_disassembler).restype, lto_initialize_disassembler.argtypes = None, [] +except AttributeError: pass + +# extern void lto_codegen_set_should_internalize(lto_code_gen_t cg, lto_bool_t ShouldInternalize) +try: (lto_codegen_set_should_internalize:=dll.lto_codegen_set_should_internalize).restype, lto_codegen_set_should_internalize.argtypes = None, [lto_code_gen_t, lto_bool_t] +except AttributeError: pass + +# extern void lto_codegen_set_should_embed_uselists(lto_code_gen_t cg, lto_bool_t ShouldEmbedUselists) +try: (lto_codegen_set_should_embed_uselists:=dll.lto_codegen_set_should_embed_uselists).restype, lto_codegen_set_should_embed_uselists.argtypes = None, [lto_code_gen_t, lto_bool_t] +except AttributeError: pass + +class struct_LLVMOpaqueLTOInput(Struct): pass +lto_input_t = ctypes.POINTER(struct_LLVMOpaqueLTOInput) +# extern lto_input_t lto_input_create(const void *buffer, size_t buffer_size, const char *path) +try: (lto_input_create:=dll.lto_input_create).restype, lto_input_create.argtypes = lto_input_t, [ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void lto_input_dispose(lto_input_t input) +try: (lto_input_dispose:=dll.lto_input_dispose).restype, lto_input_dispose.argtypes = None, [lto_input_t] +except AttributeError: pass + +# extern unsigned int lto_input_get_num_dependent_libraries(lto_input_t input) +try: (lto_input_get_num_dependent_libraries:=dll.lto_input_get_num_dependent_libraries).restype, lto_input_get_num_dependent_libraries.argtypes = ctypes.c_uint32, [lto_input_t] +except AttributeError: pass + +# extern const char *lto_input_get_dependent_library(lto_input_t input, size_t index, size_t *size) +try: (lto_input_get_dependent_library:=dll.lto_input_get_dependent_library).restype, lto_input_get_dependent_library.argtypes = ctypes.POINTER(ctypes.c_char), [lto_input_t, size_t, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern const char *const *lto_runtime_lib_symbols_list(size_t *size) +try: (lto_runtime_lib_symbols_list:=dll.lto_runtime_lib_symbols_list).restype, lto_runtime_lib_symbols_list.argtypes = ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), [ctypes.POINTER(size_t)] +except AttributeError: pass + +class LTOObjectBuffer(Struct): pass +LTOObjectBuffer._fields_ = [ + ('Buffer', ctypes.POINTER(ctypes.c_char)), + ('Size', size_t), +] +# extern thinlto_code_gen_t thinlto_create_codegen(void) +try: (thinlto_create_codegen:=dll.thinlto_create_codegen).restype, thinlto_create_codegen.argtypes = thinlto_code_gen_t, [] +except AttributeError: pass + +# extern void thinlto_codegen_dispose(thinlto_code_gen_t cg) +try: (thinlto_codegen_dispose:=dll.thinlto_codegen_dispose).restype, thinlto_codegen_dispose.argtypes = None, [thinlto_code_gen_t] +except AttributeError: pass + +# extern void thinlto_codegen_add_module(thinlto_code_gen_t cg, const char *identifier, const char *data, int length) +try: (thinlto_codegen_add_module:=dll.thinlto_codegen_add_module).restype, thinlto_codegen_add_module.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] +except AttributeError: pass + +# extern void thinlto_codegen_process(thinlto_code_gen_t cg) +try: (thinlto_codegen_process:=dll.thinlto_codegen_process).restype, thinlto_codegen_process.argtypes = None, [thinlto_code_gen_t] +except AttributeError: pass + +# extern unsigned int thinlto_module_get_num_objects(thinlto_code_gen_t cg) +try: (thinlto_module_get_num_objects:=dll.thinlto_module_get_num_objects).restype, thinlto_module_get_num_objects.argtypes = ctypes.c_uint32, [thinlto_code_gen_t] +except AttributeError: pass + +# extern LTOObjectBuffer thinlto_module_get_object(thinlto_code_gen_t cg, unsigned int index) +try: (thinlto_module_get_object:=dll.thinlto_module_get_object).restype, thinlto_module_get_object.argtypes = LTOObjectBuffer, [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +# unsigned int thinlto_module_get_num_object_files(thinlto_code_gen_t cg) +try: (thinlto_module_get_num_object_files:=dll.thinlto_module_get_num_object_files).restype, thinlto_module_get_num_object_files.argtypes = ctypes.c_uint32, [thinlto_code_gen_t] +except AttributeError: pass + +# const char *thinlto_module_get_object_file(thinlto_code_gen_t cg, unsigned int index) +try: (thinlto_module_get_object_file:=dll.thinlto_module_get_object_file).restype, thinlto_module_get_object_file.argtypes = ctypes.POINTER(ctypes.c_char), [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +# extern lto_bool_t thinlto_codegen_set_pic_model(thinlto_code_gen_t cg, lto_codegen_model) +try: (thinlto_codegen_set_pic_model:=dll.thinlto_codegen_set_pic_model).restype, thinlto_codegen_set_pic_model.argtypes = lto_bool_t, [thinlto_code_gen_t, lto_codegen_model] +except AttributeError: pass + +# extern void thinlto_codegen_set_savetemps_dir(thinlto_code_gen_t cg, const char *save_temps_dir) +try: (thinlto_codegen_set_savetemps_dir:=dll.thinlto_codegen_set_savetemps_dir).restype, thinlto_codegen_set_savetemps_dir.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void thinlto_set_generated_objects_dir(thinlto_code_gen_t cg, const char *save_temps_dir) +try: (thinlto_set_generated_objects_dir:=dll.thinlto_set_generated_objects_dir).restype, thinlto_set_generated_objects_dir.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void thinlto_codegen_set_cpu(thinlto_code_gen_t cg, const char *cpu) +try: (thinlto_codegen_set_cpu:=dll.thinlto_codegen_set_cpu).restype, thinlto_codegen_set_cpu.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void thinlto_codegen_disable_codegen(thinlto_code_gen_t cg, lto_bool_t disable) +try: (thinlto_codegen_disable_codegen:=dll.thinlto_codegen_disable_codegen).restype, thinlto_codegen_disable_codegen.argtypes = None, [thinlto_code_gen_t, lto_bool_t] +except AttributeError: pass + +# extern void thinlto_codegen_set_codegen_only(thinlto_code_gen_t cg, lto_bool_t codegen_only) +try: (thinlto_codegen_set_codegen_only:=dll.thinlto_codegen_set_codegen_only).restype, thinlto_codegen_set_codegen_only.argtypes = None, [thinlto_code_gen_t, lto_bool_t] +except AttributeError: pass + +# extern void thinlto_debug_options(const char *const *options, int number) +try: (thinlto_debug_options:=dll.thinlto_debug_options).restype, thinlto_debug_options.argtypes = None, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.c_int32] +except AttributeError: pass + +# extern lto_bool_t lto_module_is_thinlto(lto_module_t mod) +try: (lto_module_is_thinlto:=dll.lto_module_is_thinlto).restype, lto_module_is_thinlto.argtypes = lto_bool_t, [lto_module_t] +except AttributeError: pass + +# extern void thinlto_codegen_add_must_preserve_symbol(thinlto_code_gen_t cg, const char *name, int length) +try: (thinlto_codegen_add_must_preserve_symbol:=dll.thinlto_codegen_add_must_preserve_symbol).restype, thinlto_codegen_add_must_preserve_symbol.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] +except AttributeError: pass + +# extern void thinlto_codegen_add_cross_referenced_symbol(thinlto_code_gen_t cg, const char *name, int length) +try: (thinlto_codegen_add_cross_referenced_symbol:=dll.thinlto_codegen_add_cross_referenced_symbol).restype, thinlto_codegen_add_cross_referenced_symbol.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char), ctypes.c_int32] +except AttributeError: pass + +# extern void thinlto_codegen_set_cache_dir(thinlto_code_gen_t cg, const char *cache_dir) +try: (thinlto_codegen_set_cache_dir:=dll.thinlto_codegen_set_cache_dir).restype, thinlto_codegen_set_cache_dir.argtypes = None, [thinlto_code_gen_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void thinlto_codegen_set_cache_pruning_interval(thinlto_code_gen_t cg, int interval) +try: (thinlto_codegen_set_cache_pruning_interval:=dll.thinlto_codegen_set_cache_pruning_interval).restype, thinlto_codegen_set_cache_pruning_interval.argtypes = None, [thinlto_code_gen_t, ctypes.c_int32] +except AttributeError: pass + +# extern void thinlto_codegen_set_final_cache_size_relative_to_available_space(thinlto_code_gen_t cg, unsigned int percentage) +try: (thinlto_codegen_set_final_cache_size_relative_to_available_space:=dll.thinlto_codegen_set_final_cache_size_relative_to_available_space).restype, thinlto_codegen_set_final_cache_size_relative_to_available_space.argtypes = None, [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +# extern void thinlto_codegen_set_cache_entry_expiration(thinlto_code_gen_t cg, unsigned int expiration) +try: (thinlto_codegen_set_cache_entry_expiration:=dll.thinlto_codegen_set_cache_entry_expiration).restype, thinlto_codegen_set_cache_entry_expiration.argtypes = None, [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +# extern void thinlto_codegen_set_cache_size_bytes(thinlto_code_gen_t cg, unsigned int max_size_bytes) +try: (thinlto_codegen_set_cache_size_bytes:=dll.thinlto_codegen_set_cache_size_bytes).restype, thinlto_codegen_set_cache_size_bytes.argtypes = None, [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +# extern void thinlto_codegen_set_cache_size_megabytes(thinlto_code_gen_t cg, unsigned int max_size_megabytes) +try: (thinlto_codegen_set_cache_size_megabytes:=dll.thinlto_codegen_set_cache_size_megabytes).restype, thinlto_codegen_set_cache_size_megabytes.argtypes = None, [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +# extern void thinlto_codegen_set_cache_size_files(thinlto_code_gen_t cg, unsigned int max_size_files) +try: (thinlto_codegen_set_cache_size_files:=dll.thinlto_codegen_set_cache_size_files).restype, thinlto_codegen_set_cache_size_files.argtypes = None, [thinlto_code_gen_t, ctypes.c_uint32] +except AttributeError: pass + +LLVMDisassembler_Option_UseMarkup = 1 +LLVMDisassembler_Option_PrintImmHex = 2 +LLVMDisassembler_Option_AsmPrinterVariant = 4 +LLVMDisassembler_Option_SetInstrComments = 8 +LLVMDisassembler_Option_PrintLatency = 16 +LLVMDisassembler_Option_Color = 32 +LLVMDisassembler_VariantKind_None = 0 +LLVMDisassembler_VariantKind_ARM_HI16 = 1 +LLVMDisassembler_VariantKind_ARM_LO16 = 2 +LLVMDisassembler_VariantKind_ARM64_PAGE = 1 +LLVMDisassembler_VariantKind_ARM64_PAGEOFF = 2 +LLVMDisassembler_VariantKind_ARM64_GOTPAGE = 3 +LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF = 4 +LLVMDisassembler_VariantKind_ARM64_TLVP = 5 +LLVMDisassembler_VariantKind_ARM64_TLVOFF = 6 +LLVMDisassembler_ReferenceType_InOut_None = 0 +LLVMDisassembler_ReferenceType_In_Branch = 1 +LLVMDisassembler_ReferenceType_In_PCrel_Load = 2 +LLVMDisassembler_ReferenceType_In_ARM64_ADRP = 0x100000001 +LLVMDisassembler_ReferenceType_In_ARM64_ADDXri = 0x100000002 +LLVMDisassembler_ReferenceType_In_ARM64_LDRXui = 0x100000003 +LLVMDisassembler_ReferenceType_In_ARM64_LDRXl = 0x100000004 +LLVMDisassembler_ReferenceType_In_ARM64_ADR = 0x100000005 +LLVMDisassembler_ReferenceType_Out_SymbolStub = 1 +LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr = 2 +LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr = 3 +LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref = 4 +LLVMDisassembler_ReferenceType_Out_Objc_Message = 5 +LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref = 6 +LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref = 7 +LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref = 8 +LLVMDisassembler_ReferenceType_DeMangled_Name = 9 +LLVMErrorSuccess = 0 +REMARKS_API_VERSION = 1 +LLVM_BLAKE3_VERSION_STRING = "1.3.1" +LLVM_BLAKE3_KEY_LEN = 32 +LLVM_BLAKE3_OUT_LEN = 32 +LLVM_BLAKE3_BLOCK_LEN = 64 +LLVM_BLAKE3_CHUNK_LEN = 1024 +LLVM_BLAKE3_MAX_DEPTH = 54 +LTO_API_VERSION = 29 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/mesa.py b/tinygrad/runtime/autogen/mesa.py index b70da41940..71cca30923 100644 --- a/tinygrad/runtime/autogen/mesa.py +++ b/tinygrad/runtime/autogen/mesa.py @@ -1,19881 +1,8657 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-DHAVE_ENDIAN_H', '-DHAVE_STRUCT_TIMESPEC', '-DHAVE_PTHREAD', '-I/tmp/mesa-mesa-25.2.4/src', '-I/tmp/mesa-mesa-25.2.4/include', '-I/tmp/mesa-mesa-25.2.4/gen', '-I/tmp/mesa-mesa-25.2.4/src/compiler/nir', '-I/tmp/mesa-mesa-25.2.4/src/gallium/auxiliary', '-I/tmp/mesa-mesa-25.2.4/src/gallium/include', '-I/usr/lib/llvm-20/include'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os, gzip, base64, subprocess, tinygrad.helpers as helpers -PATHS_TO_TRY = [ - (BASE:=os.getenv('MESA_PATH', f"/usr{'/local/' if helpers.OSX else '/'}lib"))+'/libtinymesa_cpu'+(EXT:='.dylib' if helpers.OSX else '.so'), - f'{BASE}/libtinymesa{EXT}', - '/opt/homebrew/lib/libtinymesa_cpu.dylib', - '/opt/homebrew/lib/libtinymesa.dylib', -] -def _try_dlopen_tinymesa_cpu(): - library = ctypes.util.find_library("tinymesa_cpu") - if library: - try: return ctypes.CDLL(library) - except OSError: pass - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass +import ctypes, os +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +import gzip, base64 +from tinygrad.helpers import OSX +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(find_library('tinymesa_cpu'))) + except: pass + try: return ctypes.CDLL(unwrap((BASE:=os.getenv('MESA_PATH', f"/usr{'/local/' if OSX else '/'}lib"))+'/libtinymesa_cpu'+(EXT:='.dylib' if OSX else '.so'))) + except: pass + try: return ctypes.CDLL(unwrap(f'{BASE}/libtinymesa{EXT}')) + except: pass + try: return ctypes.CDLL(unwrap('/opt/homebrew/lib/libtinymesa_cpu.dylib')) + except: pass + try: return ctypes.CDLL(unwrap('/opt/homebrew/lib/libtinymesa.dylib')) + except: pass return None +dll = dll() - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -_libraries = {} -_libraries['libtinymesa_cpu.so'] = (dll := _try_dlopen_tinymesa_cpu()) -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries['FIXME_STUB'] = FunctionFactoryStub() # (dll := _try_dlopen_tinymesa_cpu()) - - -class struct_blob(Structure): - pass - -struct_blob._pack_ = 1 # source:False -struct_blob._fields_ = [ - ('data', ctypes.POINTER(ctypes.c_ubyte)), - ('allocated', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('fixed_allocation', ctypes.c_bool), - ('out_of_memory', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -class struct_blob_reader(Structure): - pass - -struct_blob_reader._pack_ = 1 # source:False -struct_blob_reader._fields_ = [ - ('data', ctypes.POINTER(ctypes.c_ubyte)), - ('end', ctypes.POINTER(ctypes.c_ubyte)), - ('current', ctypes.POINTER(ctypes.c_ubyte)), - ('overrun', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -try: - blob_init = _libraries['libtinymesa_cpu.so'].blob_init - blob_init.restype = None - blob_init.argtypes = [ctypes.POINTER(struct_blob)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - blob_init_fixed = _libraries['libtinymesa_cpu.so'].blob_init_fixed - blob_init_fixed.restype = None - blob_init_fixed.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - blob_finish = _libraries['FIXME_STUB'].blob_finish - blob_finish.restype = None - blob_finish.argtypes = [ctypes.POINTER(struct_blob)] -except AttributeError: - pass -try: - blob_finish_get_buffer = _libraries['libtinymesa_cpu.so'].blob_finish_get_buffer - blob_finish_get_buffer.restype = None - blob_finish_get_buffer.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - blob_align = _libraries['libtinymesa_cpu.so'].blob_align - blob_align.restype = ctypes.c_bool - blob_align.argtypes = [ctypes.POINTER(struct_blob), size_t] -except AttributeError: - pass -try: - blob_write_bytes = _libraries['libtinymesa_cpu.so'].blob_write_bytes - blob_write_bytes.restype = ctypes.c_bool - blob_write_bytes.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(None), size_t] -except AttributeError: - pass -intptr_t = ctypes.c_int64 -try: - blob_reserve_bytes = _libraries['libtinymesa_cpu.so'].blob_reserve_bytes - blob_reserve_bytes.restype = intptr_t - blob_reserve_bytes.argtypes = [ctypes.POINTER(struct_blob), size_t] -except AttributeError: - pass -try: - blob_reserve_uint32 = _libraries['libtinymesa_cpu.so'].blob_reserve_uint32 - blob_reserve_uint32.restype = intptr_t - blob_reserve_uint32.argtypes = [ctypes.POINTER(struct_blob)] -except AttributeError: - pass -try: - blob_reserve_intptr = _libraries['libtinymesa_cpu.so'].blob_reserve_intptr - blob_reserve_intptr.restype = intptr_t - blob_reserve_intptr.argtypes = [ctypes.POINTER(struct_blob)] -except AttributeError: - pass -try: - blob_overwrite_bytes = _libraries['libtinymesa_cpu.so'].blob_overwrite_bytes - blob_overwrite_bytes.restype = ctypes.c_bool - blob_overwrite_bytes.argtypes = [ctypes.POINTER(struct_blob), size_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -uint8_t = ctypes.c_uint8 -try: - blob_write_uint8 = _libraries['libtinymesa_cpu.so'].blob_write_uint8 - blob_write_uint8.restype = ctypes.c_bool - blob_write_uint8.argtypes = [ctypes.POINTER(struct_blob), uint8_t] -except AttributeError: - pass -try: - blob_overwrite_uint8 = _libraries['libtinymesa_cpu.so'].blob_overwrite_uint8 - blob_overwrite_uint8.restype = ctypes.c_bool - blob_overwrite_uint8.argtypes = [ctypes.POINTER(struct_blob), size_t, uint8_t] -except AttributeError: - pass -uint16_t = ctypes.c_uint16 -try: - blob_write_uint16 = _libraries['libtinymesa_cpu.so'].blob_write_uint16 - blob_write_uint16.restype = ctypes.c_bool - blob_write_uint16.argtypes = [ctypes.POINTER(struct_blob), uint16_t] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - blob_write_uint32 = _libraries['libtinymesa_cpu.so'].blob_write_uint32 - blob_write_uint32.restype = ctypes.c_bool - blob_write_uint32.argtypes = [ctypes.POINTER(struct_blob), uint32_t] -except AttributeError: - pass -try: - blob_overwrite_uint32 = _libraries['libtinymesa_cpu.so'].blob_overwrite_uint32 - blob_overwrite_uint32.restype = ctypes.c_bool - blob_overwrite_uint32.argtypes = [ctypes.POINTER(struct_blob), size_t, uint32_t] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - blob_write_uint64 = _libraries['libtinymesa_cpu.so'].blob_write_uint64 - blob_write_uint64.restype = ctypes.c_bool - blob_write_uint64.argtypes = [ctypes.POINTER(struct_blob), uint64_t] -except AttributeError: - pass -try: - blob_write_intptr = _libraries['libtinymesa_cpu.so'].blob_write_intptr - blob_write_intptr.restype = ctypes.c_bool - blob_write_intptr.argtypes = [ctypes.POINTER(struct_blob), intptr_t] -except AttributeError: - pass -try: - blob_overwrite_intptr = _libraries['libtinymesa_cpu.so'].blob_overwrite_intptr - blob_overwrite_intptr.restype = ctypes.c_bool - blob_overwrite_intptr.argtypes = [ctypes.POINTER(struct_blob), size_t, intptr_t] -except AttributeError: - pass -try: - blob_write_string = _libraries['libtinymesa_cpu.so'].blob_write_string - blob_write_string.restype = ctypes.c_bool - blob_write_string.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - blob_reader_init = _libraries['libtinymesa_cpu.so'].blob_reader_init - blob_reader_init.restype = None - blob_reader_init.argtypes = [ctypes.POINTER(struct_blob_reader), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - blob_reader_align = _libraries['libtinymesa_cpu.so'].blob_reader_align - blob_reader_align.restype = None - blob_reader_align.argtypes = [ctypes.POINTER(struct_blob_reader), size_t] -except AttributeError: - pass -try: - blob_read_bytes = _libraries['libtinymesa_cpu.so'].blob_read_bytes - blob_read_bytes.restype = ctypes.POINTER(None) - blob_read_bytes.argtypes = [ctypes.POINTER(struct_blob_reader), size_t] -except AttributeError: - pass -try: - blob_copy_bytes = _libraries['libtinymesa_cpu.so'].blob_copy_bytes - blob_copy_bytes.restype = None - blob_copy_bytes.argtypes = [ctypes.POINTER(struct_blob_reader), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - blob_skip_bytes = _libraries['libtinymesa_cpu.so'].blob_skip_bytes - blob_skip_bytes.restype = None - blob_skip_bytes.argtypes = [ctypes.POINTER(struct_blob_reader), size_t] -except AttributeError: - pass -try: - blob_read_uint8 = _libraries['libtinymesa_cpu.so'].blob_read_uint8 - blob_read_uint8.restype = uint8_t - blob_read_uint8.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -try: - blob_read_uint16 = _libraries['libtinymesa_cpu.so'].blob_read_uint16 - blob_read_uint16.restype = uint16_t - blob_read_uint16.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -try: - blob_read_uint32 = _libraries['libtinymesa_cpu.so'].blob_read_uint32 - blob_read_uint32.restype = uint32_t - blob_read_uint32.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -try: - blob_read_uint64 = _libraries['libtinymesa_cpu.so'].blob_read_uint64 - blob_read_uint64.restype = uint64_t - blob_read_uint64.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -try: - blob_read_intptr = _libraries['libtinymesa_cpu.so'].blob_read_intptr - blob_read_intptr.restype = intptr_t - blob_read_intptr.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -try: - blob_read_string = _libraries['libtinymesa_cpu.so'].blob_read_string - blob_read_string.restype = ctypes.POINTER(ctypes.c_char) - blob_read_string.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -class struct_glsl_type(Structure): - pass - - -# values for enumeration 'glsl_base_type' -glsl_base_type__enumvalues = { - 0: 'GLSL_TYPE_UINT', - 1: 'GLSL_TYPE_INT', - 2: 'GLSL_TYPE_FLOAT', - 3: 'GLSL_TYPE_FLOAT16', - 4: 'GLSL_TYPE_BFLOAT16', - 5: 'GLSL_TYPE_FLOAT_E4M3FN', - 6: 'GLSL_TYPE_FLOAT_E5M2', - 7: 'GLSL_TYPE_DOUBLE', - 8: 'GLSL_TYPE_UINT8', - 9: 'GLSL_TYPE_INT8', - 10: 'GLSL_TYPE_UINT16', - 11: 'GLSL_TYPE_INT16', - 12: 'GLSL_TYPE_UINT64', - 13: 'GLSL_TYPE_INT64', - 14: 'GLSL_TYPE_BOOL', - 15: 'GLSL_TYPE_COOPERATIVE_MATRIX', - 16: 'GLSL_TYPE_SAMPLER', - 17: 'GLSL_TYPE_TEXTURE', - 18: 'GLSL_TYPE_IMAGE', - 19: 'GLSL_TYPE_ATOMIC_UINT', - 20: 'GLSL_TYPE_STRUCT', - 21: 'GLSL_TYPE_INTERFACE', - 22: 'GLSL_TYPE_ARRAY', - 23: 'GLSL_TYPE_VOID', - 24: 'GLSL_TYPE_SUBROUTINE', - 25: 'GLSL_TYPE_ERROR', -} -GLSL_TYPE_UINT = 0 -GLSL_TYPE_INT = 1 -GLSL_TYPE_FLOAT = 2 -GLSL_TYPE_FLOAT16 = 3 -GLSL_TYPE_BFLOAT16 = 4 -GLSL_TYPE_FLOAT_E4M3FN = 5 -GLSL_TYPE_FLOAT_E5M2 = 6 -GLSL_TYPE_DOUBLE = 7 -GLSL_TYPE_UINT8 = 8 -GLSL_TYPE_INT8 = 9 -GLSL_TYPE_UINT16 = 10 -GLSL_TYPE_INT16 = 11 -GLSL_TYPE_UINT64 = 12 -GLSL_TYPE_INT64 = 13 -GLSL_TYPE_BOOL = 14 -GLSL_TYPE_COOPERATIVE_MATRIX = 15 -GLSL_TYPE_SAMPLER = 16 -GLSL_TYPE_TEXTURE = 17 -GLSL_TYPE_IMAGE = 18 -GLSL_TYPE_ATOMIC_UINT = 19 -GLSL_TYPE_STRUCT = 20 -GLSL_TYPE_INTERFACE = 21 -GLSL_TYPE_ARRAY = 22 -GLSL_TYPE_VOID = 23 -GLSL_TYPE_SUBROUTINE = 24 -GLSL_TYPE_ERROR = 25 -glsl_base_type = ctypes.c_uint32 # enum -class struct_glsl_cmat_description(Structure): - pass - -struct_glsl_cmat_description._pack_ = 1 # source:False -struct_glsl_cmat_description._fields_ = [ - ('element_type', ctypes.c_ubyte, 5), - ('scope', ctypes.c_ubyte, 3), - ('rows', ctypes.c_ubyte, 8), - ('cols', ctypes.c_ubyte), - ('use', ctypes.c_ubyte), -] - -class union_glsl_type_fields(Union): - pass - -class struct_glsl_struct_field(Structure): - pass - -union_glsl_type_fields._pack_ = 1 # source:False -union_glsl_type_fields._fields_ = [ - ('array', ctypes.POINTER(struct_glsl_type)), - ('structure', ctypes.POINTER(struct_glsl_struct_field)), -] - -struct_glsl_type._pack_ = 1 # source:False -struct_glsl_type._fields_ = [ - ('gl_type', ctypes.c_uint32), - ('base_type', glsl_base_type, 8), - ('sampled_type', glsl_base_type, 8), - ('sampler_dimensionality', glsl_base_type, 4), - ('sampler_shadow', glsl_base_type, 1), - ('sampler_array', glsl_base_type, 1), - ('interface_packing', glsl_base_type, 2), - ('interface_row_major', glsl_base_type, 1), - ('PADDING_0', ctypes.c_uint8, 7), - ('cmat_desc', struct_glsl_cmat_description), - ('packed', ctypes.c_uint32, 1), - ('has_builtin_name', ctypes.c_uint32, 1), - ('PADDING_1', ctypes.c_uint8, 6), - ('vector_elements', ctypes.c_uint32, 8), - ('matrix_columns', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), - ('length', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), - ('name_id', ctypes.c_uint64), - ('explicit_stride', ctypes.c_uint32), - ('explicit_alignment', ctypes.c_uint32), - ('fields', union_glsl_type_fields), -] - -glsl_type = struct_glsl_type - -# values for enumeration 'pipe_format' -pipe_format__enumvalues = { - 0: 'PIPE_FORMAT_NONE', - 1: 'PIPE_FORMAT_R64_UINT', - 2: 'PIPE_FORMAT_R64G64_UINT', - 3: 'PIPE_FORMAT_R64G64B64_UINT', - 4: 'PIPE_FORMAT_R64G64B64A64_UINT', - 5: 'PIPE_FORMAT_R64_SINT', - 6: 'PIPE_FORMAT_R64G64_SINT', - 7: 'PIPE_FORMAT_R64G64B64_SINT', - 8: 'PIPE_FORMAT_R64G64B64A64_SINT', - 9: 'PIPE_FORMAT_R64_FLOAT', - 10: 'PIPE_FORMAT_R64G64_FLOAT', - 11: 'PIPE_FORMAT_R64G64B64_FLOAT', - 12: 'PIPE_FORMAT_R64G64B64A64_FLOAT', - 13: 'PIPE_FORMAT_R32_FLOAT', - 14: 'PIPE_FORMAT_R32G32_FLOAT', - 15: 'PIPE_FORMAT_R32G32B32_FLOAT', - 16: 'PIPE_FORMAT_R32G32B32A32_FLOAT', - 17: 'PIPE_FORMAT_R32_UNORM', - 18: 'PIPE_FORMAT_R32G32_UNORM', - 19: 'PIPE_FORMAT_R32G32B32_UNORM', - 20: 'PIPE_FORMAT_R32G32B32A32_UNORM', - 21: 'PIPE_FORMAT_R32_USCALED', - 22: 'PIPE_FORMAT_R32G32_USCALED', - 23: 'PIPE_FORMAT_R32G32B32_USCALED', - 24: 'PIPE_FORMAT_R32G32B32A32_USCALED', - 25: 'PIPE_FORMAT_R32_SNORM', - 26: 'PIPE_FORMAT_R32G32_SNORM', - 27: 'PIPE_FORMAT_R32G32B32_SNORM', - 28: 'PIPE_FORMAT_R32G32B32A32_SNORM', - 29: 'PIPE_FORMAT_R32_SSCALED', - 30: 'PIPE_FORMAT_R32G32_SSCALED', - 31: 'PIPE_FORMAT_R32G32B32_SSCALED', - 32: 'PIPE_FORMAT_R32G32B32A32_SSCALED', - 33: 'PIPE_FORMAT_R16_UNORM', - 34: 'PIPE_FORMAT_R16G16_UNORM', - 35: 'PIPE_FORMAT_R16G16B16_UNORM', - 36: 'PIPE_FORMAT_R16G16B16A16_UNORM', - 37: 'PIPE_FORMAT_R16_USCALED', - 38: 'PIPE_FORMAT_R16G16_USCALED', - 39: 'PIPE_FORMAT_R16G16B16_USCALED', - 40: 'PIPE_FORMAT_R16G16B16A16_USCALED', - 41: 'PIPE_FORMAT_R16_SNORM', - 42: 'PIPE_FORMAT_R16G16_SNORM', - 43: 'PIPE_FORMAT_R16G16B16_SNORM', - 44: 'PIPE_FORMAT_R16G16B16A16_SNORM', - 45: 'PIPE_FORMAT_R16_SSCALED', - 46: 'PIPE_FORMAT_R16G16_SSCALED', - 47: 'PIPE_FORMAT_R16G16B16_SSCALED', - 48: 'PIPE_FORMAT_R16G16B16A16_SSCALED', - 49: 'PIPE_FORMAT_R8_UNORM', - 50: 'PIPE_FORMAT_R8G8_UNORM', - 51: 'PIPE_FORMAT_R8G8B8_UNORM', - 52: 'PIPE_FORMAT_B8G8R8_UNORM', - 53: 'PIPE_FORMAT_R8G8B8A8_UNORM', - 54: 'PIPE_FORMAT_B8G8R8A8_UNORM', - 55: 'PIPE_FORMAT_R8_USCALED', - 56: 'PIPE_FORMAT_R8G8_USCALED', - 57: 'PIPE_FORMAT_R8G8B8_USCALED', - 58: 'PIPE_FORMAT_B8G8R8_USCALED', - 59: 'PIPE_FORMAT_R8G8B8A8_USCALED', - 60: 'PIPE_FORMAT_B8G8R8A8_USCALED', - 61: 'PIPE_FORMAT_A8B8G8R8_USCALED', - 62: 'PIPE_FORMAT_R8_SNORM', - 63: 'PIPE_FORMAT_R8G8_SNORM', - 64: 'PIPE_FORMAT_R8G8B8_SNORM', - 65: 'PIPE_FORMAT_B8G8R8_SNORM', - 66: 'PIPE_FORMAT_R8G8B8A8_SNORM', - 67: 'PIPE_FORMAT_B8G8R8A8_SNORM', - 68: 'PIPE_FORMAT_R8_SSCALED', - 69: 'PIPE_FORMAT_R8G8_SSCALED', - 70: 'PIPE_FORMAT_R8G8B8_SSCALED', - 71: 'PIPE_FORMAT_B8G8R8_SSCALED', - 72: 'PIPE_FORMAT_R8G8B8A8_SSCALED', - 73: 'PIPE_FORMAT_B8G8R8A8_SSCALED', - 74: 'PIPE_FORMAT_A8B8G8R8_SSCALED', - 75: 'PIPE_FORMAT_A8R8G8B8_UNORM', - 76: 'PIPE_FORMAT_R32_FIXED', - 77: 'PIPE_FORMAT_R32G32_FIXED', - 78: 'PIPE_FORMAT_R32G32B32_FIXED', - 79: 'PIPE_FORMAT_R32G32B32A32_FIXED', - 80: 'PIPE_FORMAT_R16_FLOAT', - 81: 'PIPE_FORMAT_R16G16_FLOAT', - 82: 'PIPE_FORMAT_R16G16B16_FLOAT', - 83: 'PIPE_FORMAT_R16G16B16A16_FLOAT', - 84: 'PIPE_FORMAT_R8_UINT', - 85: 'PIPE_FORMAT_R8G8_UINT', - 86: 'PIPE_FORMAT_R8G8B8_UINT', - 87: 'PIPE_FORMAT_B8G8R8_UINT', - 88: 'PIPE_FORMAT_R8G8B8A8_UINT', - 89: 'PIPE_FORMAT_B8G8R8A8_UINT', - 90: 'PIPE_FORMAT_R8_SINT', - 91: 'PIPE_FORMAT_R8G8_SINT', - 92: 'PIPE_FORMAT_R8G8B8_SINT', - 93: 'PIPE_FORMAT_B8G8R8_SINT', - 94: 'PIPE_FORMAT_R8G8B8A8_SINT', - 95: 'PIPE_FORMAT_B8G8R8A8_SINT', - 96: 'PIPE_FORMAT_R16_UINT', - 97: 'PIPE_FORMAT_R16G16_UINT', - 98: 'PIPE_FORMAT_R16G16B16_UINT', - 99: 'PIPE_FORMAT_R16G16B16A16_UINT', - 100: 'PIPE_FORMAT_R16_SINT', - 101: 'PIPE_FORMAT_R16G16_SINT', - 102: 'PIPE_FORMAT_R16G16B16_SINT', - 103: 'PIPE_FORMAT_R16G16B16A16_SINT', - 104: 'PIPE_FORMAT_R32_UINT', - 105: 'PIPE_FORMAT_R32G32_UINT', - 106: 'PIPE_FORMAT_R32G32B32_UINT', - 107: 'PIPE_FORMAT_R32G32B32A32_UINT', - 108: 'PIPE_FORMAT_R32_SINT', - 109: 'PIPE_FORMAT_R32G32_SINT', - 110: 'PIPE_FORMAT_R32G32B32_SINT', - 111: 'PIPE_FORMAT_R32G32B32A32_SINT', - 112: 'PIPE_FORMAT_R10G10B10A2_UNORM', - 113: 'PIPE_FORMAT_R10G10B10A2_SNORM', - 114: 'PIPE_FORMAT_R10G10B10A2_USCALED', - 115: 'PIPE_FORMAT_R10G10B10A2_SSCALED', - 116: 'PIPE_FORMAT_B10G10R10A2_UNORM', - 117: 'PIPE_FORMAT_B10G10R10A2_SNORM', - 118: 'PIPE_FORMAT_B10G10R10A2_USCALED', - 119: 'PIPE_FORMAT_B10G10R10A2_SSCALED', - 120: 'PIPE_FORMAT_R11G11B10_FLOAT', - 121: 'PIPE_FORMAT_R10G10B10A2_UINT', - 122: 'PIPE_FORMAT_R10G10B10A2_SINT', - 123: 'PIPE_FORMAT_B10G10R10A2_UINT', - 124: 'PIPE_FORMAT_B10G10R10A2_SINT', - 125: 'PIPE_FORMAT_B8G8R8X8_UNORM', - 126: 'PIPE_FORMAT_X8B8G8R8_UNORM', - 127: 'PIPE_FORMAT_X8R8G8B8_UNORM', - 128: 'PIPE_FORMAT_B5G5R5A1_UNORM', - 129: 'PIPE_FORMAT_R4G4B4A4_UNORM', - 130: 'PIPE_FORMAT_B4G4R4A4_UNORM', - 131: 'PIPE_FORMAT_R5G6B5_UNORM', - 132: 'PIPE_FORMAT_B5G6R5_UNORM', - 133: 'PIPE_FORMAT_L8_UNORM', - 134: 'PIPE_FORMAT_A8_UNORM', - 135: 'PIPE_FORMAT_I8_UNORM', - 136: 'PIPE_FORMAT_L8A8_UNORM', - 137: 'PIPE_FORMAT_L16_UNORM', - 138: 'PIPE_FORMAT_UYVY', - 139: 'PIPE_FORMAT_VYUY', - 140: 'PIPE_FORMAT_YUYV', - 141: 'PIPE_FORMAT_YVYU', - 142: 'PIPE_FORMAT_Z16_UNORM', - 143: 'PIPE_FORMAT_Z16_UNORM_S8_UINT', - 144: 'PIPE_FORMAT_Z32_UNORM', - 145: 'PIPE_FORMAT_Z32_FLOAT', - 146: 'PIPE_FORMAT_Z24_UNORM_S8_UINT', - 147: 'PIPE_FORMAT_S8_UINT_Z24_UNORM', - 148: 'PIPE_FORMAT_Z24X8_UNORM', - 149: 'PIPE_FORMAT_X8Z24_UNORM', - 150: 'PIPE_FORMAT_S8_UINT', - 151: 'PIPE_FORMAT_L8_SRGB', - 152: 'PIPE_FORMAT_R8_SRGB', - 153: 'PIPE_FORMAT_L8A8_SRGB', - 154: 'PIPE_FORMAT_R8G8_SRGB', - 155: 'PIPE_FORMAT_R8G8B8_SRGB', - 156: 'PIPE_FORMAT_B8G8R8_SRGB', - 157: 'PIPE_FORMAT_A8B8G8R8_SRGB', - 158: 'PIPE_FORMAT_X8B8G8R8_SRGB', - 159: 'PIPE_FORMAT_B8G8R8A8_SRGB', - 160: 'PIPE_FORMAT_B8G8R8X8_SRGB', - 161: 'PIPE_FORMAT_A8R8G8B8_SRGB', - 162: 'PIPE_FORMAT_X8R8G8B8_SRGB', - 163: 'PIPE_FORMAT_R8G8B8A8_SRGB', - 164: 'PIPE_FORMAT_DXT1_RGB', - 165: 'PIPE_FORMAT_DXT1_RGBA', - 166: 'PIPE_FORMAT_DXT3_RGBA', - 167: 'PIPE_FORMAT_DXT5_RGBA', - 168: 'PIPE_FORMAT_DXT1_SRGB', - 169: 'PIPE_FORMAT_DXT1_SRGBA', - 170: 'PIPE_FORMAT_DXT3_SRGBA', - 171: 'PIPE_FORMAT_DXT5_SRGBA', - 172: 'PIPE_FORMAT_RGTC1_UNORM', - 173: 'PIPE_FORMAT_RGTC1_SNORM', - 174: 'PIPE_FORMAT_RGTC2_UNORM', - 175: 'PIPE_FORMAT_RGTC2_SNORM', - 176: 'PIPE_FORMAT_R8G8_B8G8_UNORM', - 177: 'PIPE_FORMAT_G8R8_G8B8_UNORM', - 178: 'PIPE_FORMAT_X6G10_X6B10X6R10_420_UNORM', - 179: 'PIPE_FORMAT_X4G12_X4B12X4R12_420_UNORM', - 180: 'PIPE_FORMAT_X6R10_UNORM', - 181: 'PIPE_FORMAT_X6R10X6G10_UNORM', - 182: 'PIPE_FORMAT_X4R12_UNORM', - 183: 'PIPE_FORMAT_X4R12X4G12_UNORM', - 184: 'PIPE_FORMAT_R8SG8SB8UX8U_NORM', - 185: 'PIPE_FORMAT_R5SG5SB6U_NORM', - 186: 'PIPE_FORMAT_A8B8G8R8_UNORM', - 187: 'PIPE_FORMAT_B5G5R5X1_UNORM', - 188: 'PIPE_FORMAT_R9G9B9E5_FLOAT', - 189: 'PIPE_FORMAT_Z32_FLOAT_S8X24_UINT', - 190: 'PIPE_FORMAT_R1_UNORM', - 191: 'PIPE_FORMAT_R10G10B10X2_USCALED', - 192: 'PIPE_FORMAT_R10G10B10X2_SNORM', - 193: 'PIPE_FORMAT_L4A4_UNORM', - 194: 'PIPE_FORMAT_A2R10G10B10_UNORM', - 195: 'PIPE_FORMAT_A2B10G10R10_UNORM', - 196: 'PIPE_FORMAT_R10SG10SB10SA2U_NORM', - 197: 'PIPE_FORMAT_R8G8Bx_SNORM', - 198: 'PIPE_FORMAT_R8G8B8X8_UNORM', - 199: 'PIPE_FORMAT_B4G4R4X4_UNORM', - 200: 'PIPE_FORMAT_X24S8_UINT', - 201: 'PIPE_FORMAT_S8X24_UINT', - 202: 'PIPE_FORMAT_X32_S8X24_UINT', - 203: 'PIPE_FORMAT_R3G3B2_UNORM', - 204: 'PIPE_FORMAT_B2G3R3_UNORM', - 205: 'PIPE_FORMAT_L16A16_UNORM', - 206: 'PIPE_FORMAT_A16_UNORM', - 207: 'PIPE_FORMAT_I16_UNORM', - 208: 'PIPE_FORMAT_LATC1_UNORM', - 209: 'PIPE_FORMAT_LATC1_SNORM', - 210: 'PIPE_FORMAT_LATC2_UNORM', - 211: 'PIPE_FORMAT_LATC2_SNORM', - 212: 'PIPE_FORMAT_A8_SNORM', - 213: 'PIPE_FORMAT_L8_SNORM', - 214: 'PIPE_FORMAT_L8A8_SNORM', - 215: 'PIPE_FORMAT_I8_SNORM', - 216: 'PIPE_FORMAT_A16_SNORM', - 217: 'PIPE_FORMAT_L16_SNORM', - 218: 'PIPE_FORMAT_L16A16_SNORM', - 219: 'PIPE_FORMAT_I16_SNORM', - 220: 'PIPE_FORMAT_A16_FLOAT', - 221: 'PIPE_FORMAT_L16_FLOAT', - 222: 'PIPE_FORMAT_L16A16_FLOAT', - 223: 'PIPE_FORMAT_I16_FLOAT', - 224: 'PIPE_FORMAT_A32_FLOAT', - 225: 'PIPE_FORMAT_L32_FLOAT', - 226: 'PIPE_FORMAT_L32A32_FLOAT', - 227: 'PIPE_FORMAT_I32_FLOAT', - 228: 'PIPE_FORMAT_YV12', - 229: 'PIPE_FORMAT_YV16', - 230: 'PIPE_FORMAT_IYUV', - 231: 'PIPE_FORMAT_NV12', - 232: 'PIPE_FORMAT_NV21', - 233: 'PIPE_FORMAT_NV16', - 234: 'PIPE_FORMAT_NV15', - 235: 'PIPE_FORMAT_NV20', - 236: 'PIPE_FORMAT_Y8_400_UNORM', - 237: 'PIPE_FORMAT_Y8_U8_V8_422_UNORM', - 238: 'PIPE_FORMAT_Y8_U8_V8_444_UNORM', - 239: 'PIPE_FORMAT_Y8_U8_V8_440_UNORM', - 240: 'PIPE_FORMAT_Y10X6_U10X6_V10X6_420_UNORM', - 241: 'PIPE_FORMAT_Y10X6_U10X6_V10X6_422_UNORM', - 242: 'PIPE_FORMAT_Y10X6_U10X6_V10X6_444_UNORM', - 243: 'PIPE_FORMAT_Y12X4_U12X4_V12X4_420_UNORM', - 244: 'PIPE_FORMAT_Y12X4_U12X4_V12X4_422_UNORM', - 245: 'PIPE_FORMAT_Y12X4_U12X4_V12X4_444_UNORM', - 246: 'PIPE_FORMAT_Y16_U16_V16_420_UNORM', - 247: 'PIPE_FORMAT_Y16_U16_V16_422_UNORM', - 248: 'PIPE_FORMAT_Y16_U16V16_422_UNORM', - 249: 'PIPE_FORMAT_Y16_U16_V16_444_UNORM', - 250: 'PIPE_FORMAT_Y8U8V8_420_UNORM_PACKED', - 251: 'PIPE_FORMAT_Y10U10V10_420_UNORM_PACKED', - 252: 'PIPE_FORMAT_A4R4_UNORM', - 253: 'PIPE_FORMAT_R4A4_UNORM', - 254: 'PIPE_FORMAT_R8A8_UNORM', - 255: 'PIPE_FORMAT_A8R8_UNORM', - 256: 'PIPE_FORMAT_A8_UINT', - 257: 'PIPE_FORMAT_I8_UINT', - 258: 'PIPE_FORMAT_L8_UINT', - 259: 'PIPE_FORMAT_L8A8_UINT', - 260: 'PIPE_FORMAT_A8_SINT', - 261: 'PIPE_FORMAT_I8_SINT', - 262: 'PIPE_FORMAT_L8_SINT', - 263: 'PIPE_FORMAT_L8A8_SINT', - 264: 'PIPE_FORMAT_A16_UINT', - 265: 'PIPE_FORMAT_I16_UINT', - 266: 'PIPE_FORMAT_L16_UINT', - 267: 'PIPE_FORMAT_L16A16_UINT', - 268: 'PIPE_FORMAT_A16_SINT', - 269: 'PIPE_FORMAT_I16_SINT', - 270: 'PIPE_FORMAT_L16_SINT', - 271: 'PIPE_FORMAT_L16A16_SINT', - 272: 'PIPE_FORMAT_A32_UINT', - 273: 'PIPE_FORMAT_I32_UINT', - 274: 'PIPE_FORMAT_L32_UINT', - 275: 'PIPE_FORMAT_L32A32_UINT', - 276: 'PIPE_FORMAT_A32_SINT', - 277: 'PIPE_FORMAT_I32_SINT', - 278: 'PIPE_FORMAT_L32_SINT', - 279: 'PIPE_FORMAT_L32A32_SINT', - 280: 'PIPE_FORMAT_A8R8G8B8_UINT', - 281: 'PIPE_FORMAT_A8B8G8R8_UINT', - 282: 'PIPE_FORMAT_A2R10G10B10_UINT', - 283: 'PIPE_FORMAT_A2B10G10R10_UINT', - 284: 'PIPE_FORMAT_R5G6B5_UINT', - 285: 'PIPE_FORMAT_B5G6R5_UINT', - 286: 'PIPE_FORMAT_R5G5B5A1_UINT', - 287: 'PIPE_FORMAT_B5G5R5A1_UINT', - 288: 'PIPE_FORMAT_A1R5G5B5_UINT', - 289: 'PIPE_FORMAT_A1B5G5R5_UINT', - 290: 'PIPE_FORMAT_R4G4B4A4_UINT', - 291: 'PIPE_FORMAT_B4G4R4A4_UINT', - 292: 'PIPE_FORMAT_A4R4G4B4_UINT', - 293: 'PIPE_FORMAT_A4B4G4R4_UINT', - 294: 'PIPE_FORMAT_R3G3B2_UINT', - 295: 'PIPE_FORMAT_B2G3R3_UINT', - 296: 'PIPE_FORMAT_ETC1_RGB8', - 297: 'PIPE_FORMAT_R8G8_R8B8_UNORM', - 298: 'PIPE_FORMAT_R8B8_R8G8_UNORM', - 299: 'PIPE_FORMAT_G8R8_B8R8_UNORM', - 300: 'PIPE_FORMAT_B8R8_G8R8_UNORM', - 301: 'PIPE_FORMAT_G8B8_G8R8_UNORM', - 302: 'PIPE_FORMAT_B8G8_R8G8_UNORM', - 303: 'PIPE_FORMAT_R8G8B8X8_SNORM', - 304: 'PIPE_FORMAT_R8G8B8X8_SRGB', - 305: 'PIPE_FORMAT_R8G8B8X8_UINT', - 306: 'PIPE_FORMAT_R8G8B8X8_SINT', - 307: 'PIPE_FORMAT_B10G10R10X2_UNORM', - 308: 'PIPE_FORMAT_R16G16B16X16_UNORM', - 309: 'PIPE_FORMAT_R16G16B16X16_SNORM', - 310: 'PIPE_FORMAT_R16G16B16X16_FLOAT', - 311: 'PIPE_FORMAT_R16G16B16X16_UINT', - 312: 'PIPE_FORMAT_R16G16B16X16_SINT', - 313: 'PIPE_FORMAT_R32G32B32X32_FLOAT', - 314: 'PIPE_FORMAT_R32G32B32X32_UINT', - 315: 'PIPE_FORMAT_R32G32B32X32_SINT', - 316: 'PIPE_FORMAT_R8A8_SNORM', - 317: 'PIPE_FORMAT_R16A16_UNORM', - 318: 'PIPE_FORMAT_R16A16_SNORM', - 319: 'PIPE_FORMAT_R16A16_FLOAT', - 320: 'PIPE_FORMAT_R32A32_FLOAT', - 321: 'PIPE_FORMAT_R8A8_UINT', - 322: 'PIPE_FORMAT_R8A8_SINT', - 323: 'PIPE_FORMAT_R16A16_UINT', - 324: 'PIPE_FORMAT_R16A16_SINT', - 325: 'PIPE_FORMAT_R32A32_UINT', - 326: 'PIPE_FORMAT_R32A32_SINT', - 327: 'PIPE_FORMAT_B5G6R5_SRGB', - 328: 'PIPE_FORMAT_BPTC_RGBA_UNORM', - 329: 'PIPE_FORMAT_BPTC_SRGBA', - 330: 'PIPE_FORMAT_BPTC_RGB_FLOAT', - 331: 'PIPE_FORMAT_BPTC_RGB_UFLOAT', - 332: 'PIPE_FORMAT_G8R8_UNORM', - 333: 'PIPE_FORMAT_G8R8_SNORM', - 334: 'PIPE_FORMAT_G16R16_UNORM', - 335: 'PIPE_FORMAT_G16R16_SNORM', - 336: 'PIPE_FORMAT_A8B8G8R8_SNORM', - 337: 'PIPE_FORMAT_X8B8G8R8_SNORM', - 338: 'PIPE_FORMAT_ETC2_RGB8', - 339: 'PIPE_FORMAT_ETC2_SRGB8', - 340: 'PIPE_FORMAT_ETC2_RGB8A1', - 341: 'PIPE_FORMAT_ETC2_SRGB8A1', - 342: 'PIPE_FORMAT_ETC2_RGBA8', - 343: 'PIPE_FORMAT_ETC2_SRGBA8', - 344: 'PIPE_FORMAT_ETC2_R11_UNORM', - 345: 'PIPE_FORMAT_ETC2_R11_SNORM', - 346: 'PIPE_FORMAT_ETC2_RG11_UNORM', - 347: 'PIPE_FORMAT_ETC2_RG11_SNORM', - 348: 'PIPE_FORMAT_ASTC_4x4', - 349: 'PIPE_FORMAT_ASTC_5x4', - 350: 'PIPE_FORMAT_ASTC_5x5', - 351: 'PIPE_FORMAT_ASTC_6x5', - 352: 'PIPE_FORMAT_ASTC_6x6', - 353: 'PIPE_FORMAT_ASTC_8x5', - 354: 'PIPE_FORMAT_ASTC_8x6', - 355: 'PIPE_FORMAT_ASTC_8x8', - 356: 'PIPE_FORMAT_ASTC_10x5', - 357: 'PIPE_FORMAT_ASTC_10x6', - 358: 'PIPE_FORMAT_ASTC_10x8', - 359: 'PIPE_FORMAT_ASTC_10x10', - 360: 'PIPE_FORMAT_ASTC_12x10', - 361: 'PIPE_FORMAT_ASTC_12x12', - 362: 'PIPE_FORMAT_ASTC_4x4_SRGB', - 363: 'PIPE_FORMAT_ASTC_5x4_SRGB', - 364: 'PIPE_FORMAT_ASTC_5x5_SRGB', - 365: 'PIPE_FORMAT_ASTC_6x5_SRGB', - 366: 'PIPE_FORMAT_ASTC_6x6_SRGB', - 367: 'PIPE_FORMAT_ASTC_8x5_SRGB', - 368: 'PIPE_FORMAT_ASTC_8x6_SRGB', - 369: 'PIPE_FORMAT_ASTC_8x8_SRGB', - 370: 'PIPE_FORMAT_ASTC_10x5_SRGB', - 371: 'PIPE_FORMAT_ASTC_10x6_SRGB', - 372: 'PIPE_FORMAT_ASTC_10x8_SRGB', - 373: 'PIPE_FORMAT_ASTC_10x10_SRGB', - 374: 'PIPE_FORMAT_ASTC_12x10_SRGB', - 375: 'PIPE_FORMAT_ASTC_12x12_SRGB', - 376: 'PIPE_FORMAT_ASTC_3x3x3', - 377: 'PIPE_FORMAT_ASTC_4x3x3', - 378: 'PIPE_FORMAT_ASTC_4x4x3', - 379: 'PIPE_FORMAT_ASTC_4x4x4', - 380: 'PIPE_FORMAT_ASTC_5x4x4', - 381: 'PIPE_FORMAT_ASTC_5x5x4', - 382: 'PIPE_FORMAT_ASTC_5x5x5', - 383: 'PIPE_FORMAT_ASTC_6x5x5', - 384: 'PIPE_FORMAT_ASTC_6x6x5', - 385: 'PIPE_FORMAT_ASTC_6x6x6', - 386: 'PIPE_FORMAT_ASTC_3x3x3_SRGB', - 387: 'PIPE_FORMAT_ASTC_4x3x3_SRGB', - 388: 'PIPE_FORMAT_ASTC_4x4x3_SRGB', - 389: 'PIPE_FORMAT_ASTC_4x4x4_SRGB', - 390: 'PIPE_FORMAT_ASTC_5x4x4_SRGB', - 391: 'PIPE_FORMAT_ASTC_5x5x4_SRGB', - 392: 'PIPE_FORMAT_ASTC_5x5x5_SRGB', - 393: 'PIPE_FORMAT_ASTC_6x5x5_SRGB', - 394: 'PIPE_FORMAT_ASTC_6x6x5_SRGB', - 395: 'PIPE_FORMAT_ASTC_6x6x6_SRGB', - 396: 'PIPE_FORMAT_ASTC_4x4_FLOAT', - 397: 'PIPE_FORMAT_ASTC_5x4_FLOAT', - 398: 'PIPE_FORMAT_ASTC_5x5_FLOAT', - 399: 'PIPE_FORMAT_ASTC_6x5_FLOAT', - 400: 'PIPE_FORMAT_ASTC_6x6_FLOAT', - 401: 'PIPE_FORMAT_ASTC_8x5_FLOAT', - 402: 'PIPE_FORMAT_ASTC_8x6_FLOAT', - 403: 'PIPE_FORMAT_ASTC_8x8_FLOAT', - 404: 'PIPE_FORMAT_ASTC_10x5_FLOAT', - 405: 'PIPE_FORMAT_ASTC_10x6_FLOAT', - 406: 'PIPE_FORMAT_ASTC_10x8_FLOAT', - 407: 'PIPE_FORMAT_ASTC_10x10_FLOAT', - 408: 'PIPE_FORMAT_ASTC_12x10_FLOAT', - 409: 'PIPE_FORMAT_ASTC_12x12_FLOAT', - 410: 'PIPE_FORMAT_FXT1_RGB', - 411: 'PIPE_FORMAT_FXT1_RGBA', - 412: 'PIPE_FORMAT_P010', - 413: 'PIPE_FORMAT_P012', - 414: 'PIPE_FORMAT_P016', - 415: 'PIPE_FORMAT_P030', - 416: 'PIPE_FORMAT_Y210', - 417: 'PIPE_FORMAT_Y212', - 418: 'PIPE_FORMAT_Y216', - 419: 'PIPE_FORMAT_Y410', - 420: 'PIPE_FORMAT_Y412', - 421: 'PIPE_FORMAT_Y416', - 422: 'PIPE_FORMAT_R10G10B10X2_UNORM', - 423: 'PIPE_FORMAT_A1R5G5B5_UNORM', - 424: 'PIPE_FORMAT_A1B5G5R5_UNORM', - 425: 'PIPE_FORMAT_X1B5G5R5_UNORM', - 426: 'PIPE_FORMAT_R5G5B5A1_UNORM', - 427: 'PIPE_FORMAT_A4R4G4B4_UNORM', - 428: 'PIPE_FORMAT_A4B4G4R4_UNORM', - 429: 'PIPE_FORMAT_G8R8_SINT', - 430: 'PIPE_FORMAT_A8B8G8R8_SINT', - 431: 'PIPE_FORMAT_X8B8G8R8_SINT', - 432: 'PIPE_FORMAT_ATC_RGB', - 433: 'PIPE_FORMAT_ATC_RGBA_EXPLICIT', - 434: 'PIPE_FORMAT_ATC_RGBA_INTERPOLATED', - 435: 'PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8', - 436: 'PIPE_FORMAT_AYUV', - 437: 'PIPE_FORMAT_XYUV', - 438: 'PIPE_FORMAT_R8G8B8_420_UNORM_PACKED', - 439: 'PIPE_FORMAT_R8_G8B8_420_UNORM', - 440: 'PIPE_FORMAT_R8_B8G8_420_UNORM', - 441: 'PIPE_FORMAT_G8_B8R8_420_UNORM', - 442: 'PIPE_FORMAT_R10G10B10_420_UNORM_PACKED', - 443: 'PIPE_FORMAT_R10_G10B10_420_UNORM', - 444: 'PIPE_FORMAT_R10_G10B10_422_UNORM', - 445: 'PIPE_FORMAT_R8_G8_B8_420_UNORM', - 446: 'PIPE_FORMAT_R8_B8_G8_420_UNORM', - 447: 'PIPE_FORMAT_G8_B8_R8_420_UNORM', - 448: 'PIPE_FORMAT_R8_G8B8_422_UNORM', - 449: 'PIPE_FORMAT_R8_B8G8_422_UNORM', - 450: 'PIPE_FORMAT_G8_B8R8_422_UNORM', - 451: 'PIPE_FORMAT_R8_G8_B8_UNORM', - 452: 'PIPE_FORMAT_Y8_UNORM', - 453: 'PIPE_FORMAT_B8G8R8X8_SNORM', - 454: 'PIPE_FORMAT_B8G8R8X8_UINT', - 455: 'PIPE_FORMAT_B8G8R8X8_SINT', - 456: 'PIPE_FORMAT_A8R8G8B8_SNORM', - 457: 'PIPE_FORMAT_A8R8G8B8_SINT', - 458: 'PIPE_FORMAT_X8R8G8B8_SNORM', - 459: 'PIPE_FORMAT_X8R8G8B8_SINT', - 460: 'PIPE_FORMAT_R5G5B5X1_UNORM', - 461: 'PIPE_FORMAT_X1R5G5B5_UNORM', - 462: 'PIPE_FORMAT_R4G4B4X4_UNORM', - 463: 'PIPE_FORMAT_B10G10R10X2_SNORM', - 464: 'PIPE_FORMAT_R5G6B5_SRGB', - 465: 'PIPE_FORMAT_R10G10B10X2_SINT', - 466: 'PIPE_FORMAT_B10G10R10X2_SINT', - 467: 'PIPE_FORMAT_G16R16_SINT', - 468: 'PIPE_FORMAT_COUNT', -} -PIPE_FORMAT_NONE = 0 -PIPE_FORMAT_R64_UINT = 1 -PIPE_FORMAT_R64G64_UINT = 2 -PIPE_FORMAT_R64G64B64_UINT = 3 -PIPE_FORMAT_R64G64B64A64_UINT = 4 -PIPE_FORMAT_R64_SINT = 5 -PIPE_FORMAT_R64G64_SINT = 6 -PIPE_FORMAT_R64G64B64_SINT = 7 -PIPE_FORMAT_R64G64B64A64_SINT = 8 -PIPE_FORMAT_R64_FLOAT = 9 -PIPE_FORMAT_R64G64_FLOAT = 10 -PIPE_FORMAT_R64G64B64_FLOAT = 11 -PIPE_FORMAT_R64G64B64A64_FLOAT = 12 -PIPE_FORMAT_R32_FLOAT = 13 -PIPE_FORMAT_R32G32_FLOAT = 14 -PIPE_FORMAT_R32G32B32_FLOAT = 15 -PIPE_FORMAT_R32G32B32A32_FLOAT = 16 -PIPE_FORMAT_R32_UNORM = 17 -PIPE_FORMAT_R32G32_UNORM = 18 -PIPE_FORMAT_R32G32B32_UNORM = 19 -PIPE_FORMAT_R32G32B32A32_UNORM = 20 -PIPE_FORMAT_R32_USCALED = 21 -PIPE_FORMAT_R32G32_USCALED = 22 -PIPE_FORMAT_R32G32B32_USCALED = 23 -PIPE_FORMAT_R32G32B32A32_USCALED = 24 -PIPE_FORMAT_R32_SNORM = 25 -PIPE_FORMAT_R32G32_SNORM = 26 -PIPE_FORMAT_R32G32B32_SNORM = 27 -PIPE_FORMAT_R32G32B32A32_SNORM = 28 -PIPE_FORMAT_R32_SSCALED = 29 -PIPE_FORMAT_R32G32_SSCALED = 30 -PIPE_FORMAT_R32G32B32_SSCALED = 31 -PIPE_FORMAT_R32G32B32A32_SSCALED = 32 -PIPE_FORMAT_R16_UNORM = 33 -PIPE_FORMAT_R16G16_UNORM = 34 -PIPE_FORMAT_R16G16B16_UNORM = 35 -PIPE_FORMAT_R16G16B16A16_UNORM = 36 -PIPE_FORMAT_R16_USCALED = 37 -PIPE_FORMAT_R16G16_USCALED = 38 -PIPE_FORMAT_R16G16B16_USCALED = 39 -PIPE_FORMAT_R16G16B16A16_USCALED = 40 -PIPE_FORMAT_R16_SNORM = 41 -PIPE_FORMAT_R16G16_SNORM = 42 -PIPE_FORMAT_R16G16B16_SNORM = 43 -PIPE_FORMAT_R16G16B16A16_SNORM = 44 -PIPE_FORMAT_R16_SSCALED = 45 -PIPE_FORMAT_R16G16_SSCALED = 46 -PIPE_FORMAT_R16G16B16_SSCALED = 47 -PIPE_FORMAT_R16G16B16A16_SSCALED = 48 -PIPE_FORMAT_R8_UNORM = 49 -PIPE_FORMAT_R8G8_UNORM = 50 -PIPE_FORMAT_R8G8B8_UNORM = 51 -PIPE_FORMAT_B8G8R8_UNORM = 52 -PIPE_FORMAT_R8G8B8A8_UNORM = 53 -PIPE_FORMAT_B8G8R8A8_UNORM = 54 -PIPE_FORMAT_R8_USCALED = 55 -PIPE_FORMAT_R8G8_USCALED = 56 -PIPE_FORMAT_R8G8B8_USCALED = 57 -PIPE_FORMAT_B8G8R8_USCALED = 58 -PIPE_FORMAT_R8G8B8A8_USCALED = 59 -PIPE_FORMAT_B8G8R8A8_USCALED = 60 -PIPE_FORMAT_A8B8G8R8_USCALED = 61 -PIPE_FORMAT_R8_SNORM = 62 -PIPE_FORMAT_R8G8_SNORM = 63 -PIPE_FORMAT_R8G8B8_SNORM = 64 -PIPE_FORMAT_B8G8R8_SNORM = 65 -PIPE_FORMAT_R8G8B8A8_SNORM = 66 -PIPE_FORMAT_B8G8R8A8_SNORM = 67 -PIPE_FORMAT_R8_SSCALED = 68 -PIPE_FORMAT_R8G8_SSCALED = 69 -PIPE_FORMAT_R8G8B8_SSCALED = 70 -PIPE_FORMAT_B8G8R8_SSCALED = 71 -PIPE_FORMAT_R8G8B8A8_SSCALED = 72 -PIPE_FORMAT_B8G8R8A8_SSCALED = 73 -PIPE_FORMAT_A8B8G8R8_SSCALED = 74 -PIPE_FORMAT_A8R8G8B8_UNORM = 75 -PIPE_FORMAT_R32_FIXED = 76 -PIPE_FORMAT_R32G32_FIXED = 77 -PIPE_FORMAT_R32G32B32_FIXED = 78 -PIPE_FORMAT_R32G32B32A32_FIXED = 79 -PIPE_FORMAT_R16_FLOAT = 80 -PIPE_FORMAT_R16G16_FLOAT = 81 -PIPE_FORMAT_R16G16B16_FLOAT = 82 -PIPE_FORMAT_R16G16B16A16_FLOAT = 83 -PIPE_FORMAT_R8_UINT = 84 -PIPE_FORMAT_R8G8_UINT = 85 -PIPE_FORMAT_R8G8B8_UINT = 86 -PIPE_FORMAT_B8G8R8_UINT = 87 -PIPE_FORMAT_R8G8B8A8_UINT = 88 -PIPE_FORMAT_B8G8R8A8_UINT = 89 -PIPE_FORMAT_R8_SINT = 90 -PIPE_FORMAT_R8G8_SINT = 91 -PIPE_FORMAT_R8G8B8_SINT = 92 -PIPE_FORMAT_B8G8R8_SINT = 93 -PIPE_FORMAT_R8G8B8A8_SINT = 94 -PIPE_FORMAT_B8G8R8A8_SINT = 95 -PIPE_FORMAT_R16_UINT = 96 -PIPE_FORMAT_R16G16_UINT = 97 -PIPE_FORMAT_R16G16B16_UINT = 98 -PIPE_FORMAT_R16G16B16A16_UINT = 99 -PIPE_FORMAT_R16_SINT = 100 -PIPE_FORMAT_R16G16_SINT = 101 -PIPE_FORMAT_R16G16B16_SINT = 102 -PIPE_FORMAT_R16G16B16A16_SINT = 103 -PIPE_FORMAT_R32_UINT = 104 -PIPE_FORMAT_R32G32_UINT = 105 -PIPE_FORMAT_R32G32B32_UINT = 106 -PIPE_FORMAT_R32G32B32A32_UINT = 107 -PIPE_FORMAT_R32_SINT = 108 -PIPE_FORMAT_R32G32_SINT = 109 -PIPE_FORMAT_R32G32B32_SINT = 110 -PIPE_FORMAT_R32G32B32A32_SINT = 111 -PIPE_FORMAT_R10G10B10A2_UNORM = 112 -PIPE_FORMAT_R10G10B10A2_SNORM = 113 -PIPE_FORMAT_R10G10B10A2_USCALED = 114 -PIPE_FORMAT_R10G10B10A2_SSCALED = 115 -PIPE_FORMAT_B10G10R10A2_UNORM = 116 -PIPE_FORMAT_B10G10R10A2_SNORM = 117 -PIPE_FORMAT_B10G10R10A2_USCALED = 118 -PIPE_FORMAT_B10G10R10A2_SSCALED = 119 -PIPE_FORMAT_R11G11B10_FLOAT = 120 -PIPE_FORMAT_R10G10B10A2_UINT = 121 -PIPE_FORMAT_R10G10B10A2_SINT = 122 -PIPE_FORMAT_B10G10R10A2_UINT = 123 -PIPE_FORMAT_B10G10R10A2_SINT = 124 -PIPE_FORMAT_B8G8R8X8_UNORM = 125 -PIPE_FORMAT_X8B8G8R8_UNORM = 126 -PIPE_FORMAT_X8R8G8B8_UNORM = 127 -PIPE_FORMAT_B5G5R5A1_UNORM = 128 -PIPE_FORMAT_R4G4B4A4_UNORM = 129 -PIPE_FORMAT_B4G4R4A4_UNORM = 130 -PIPE_FORMAT_R5G6B5_UNORM = 131 -PIPE_FORMAT_B5G6R5_UNORM = 132 -PIPE_FORMAT_L8_UNORM = 133 -PIPE_FORMAT_A8_UNORM = 134 -PIPE_FORMAT_I8_UNORM = 135 -PIPE_FORMAT_L8A8_UNORM = 136 -PIPE_FORMAT_L16_UNORM = 137 -PIPE_FORMAT_UYVY = 138 -PIPE_FORMAT_VYUY = 139 -PIPE_FORMAT_YUYV = 140 -PIPE_FORMAT_YVYU = 141 -PIPE_FORMAT_Z16_UNORM = 142 -PIPE_FORMAT_Z16_UNORM_S8_UINT = 143 -PIPE_FORMAT_Z32_UNORM = 144 -PIPE_FORMAT_Z32_FLOAT = 145 -PIPE_FORMAT_Z24_UNORM_S8_UINT = 146 -PIPE_FORMAT_S8_UINT_Z24_UNORM = 147 -PIPE_FORMAT_Z24X8_UNORM = 148 -PIPE_FORMAT_X8Z24_UNORM = 149 -PIPE_FORMAT_S8_UINT = 150 -PIPE_FORMAT_L8_SRGB = 151 -PIPE_FORMAT_R8_SRGB = 152 -PIPE_FORMAT_L8A8_SRGB = 153 -PIPE_FORMAT_R8G8_SRGB = 154 -PIPE_FORMAT_R8G8B8_SRGB = 155 -PIPE_FORMAT_B8G8R8_SRGB = 156 -PIPE_FORMAT_A8B8G8R8_SRGB = 157 -PIPE_FORMAT_X8B8G8R8_SRGB = 158 -PIPE_FORMAT_B8G8R8A8_SRGB = 159 -PIPE_FORMAT_B8G8R8X8_SRGB = 160 -PIPE_FORMAT_A8R8G8B8_SRGB = 161 -PIPE_FORMAT_X8R8G8B8_SRGB = 162 -PIPE_FORMAT_R8G8B8A8_SRGB = 163 -PIPE_FORMAT_DXT1_RGB = 164 -PIPE_FORMAT_DXT1_RGBA = 165 -PIPE_FORMAT_DXT3_RGBA = 166 -PIPE_FORMAT_DXT5_RGBA = 167 -PIPE_FORMAT_DXT1_SRGB = 168 -PIPE_FORMAT_DXT1_SRGBA = 169 -PIPE_FORMAT_DXT3_SRGBA = 170 -PIPE_FORMAT_DXT5_SRGBA = 171 -PIPE_FORMAT_RGTC1_UNORM = 172 -PIPE_FORMAT_RGTC1_SNORM = 173 -PIPE_FORMAT_RGTC2_UNORM = 174 -PIPE_FORMAT_RGTC2_SNORM = 175 -PIPE_FORMAT_R8G8_B8G8_UNORM = 176 -PIPE_FORMAT_G8R8_G8B8_UNORM = 177 -PIPE_FORMAT_X6G10_X6B10X6R10_420_UNORM = 178 -PIPE_FORMAT_X4G12_X4B12X4R12_420_UNORM = 179 -PIPE_FORMAT_X6R10_UNORM = 180 -PIPE_FORMAT_X6R10X6G10_UNORM = 181 -PIPE_FORMAT_X4R12_UNORM = 182 -PIPE_FORMAT_X4R12X4G12_UNORM = 183 -PIPE_FORMAT_R8SG8SB8UX8U_NORM = 184 -PIPE_FORMAT_R5SG5SB6U_NORM = 185 -PIPE_FORMAT_A8B8G8R8_UNORM = 186 -PIPE_FORMAT_B5G5R5X1_UNORM = 187 -PIPE_FORMAT_R9G9B9E5_FLOAT = 188 -PIPE_FORMAT_Z32_FLOAT_S8X24_UINT = 189 -PIPE_FORMAT_R1_UNORM = 190 -PIPE_FORMAT_R10G10B10X2_USCALED = 191 -PIPE_FORMAT_R10G10B10X2_SNORM = 192 -PIPE_FORMAT_L4A4_UNORM = 193 -PIPE_FORMAT_A2R10G10B10_UNORM = 194 -PIPE_FORMAT_A2B10G10R10_UNORM = 195 -PIPE_FORMAT_R10SG10SB10SA2U_NORM = 196 -PIPE_FORMAT_R8G8Bx_SNORM = 197 -PIPE_FORMAT_R8G8B8X8_UNORM = 198 -PIPE_FORMAT_B4G4R4X4_UNORM = 199 -PIPE_FORMAT_X24S8_UINT = 200 -PIPE_FORMAT_S8X24_UINT = 201 -PIPE_FORMAT_X32_S8X24_UINT = 202 -PIPE_FORMAT_R3G3B2_UNORM = 203 -PIPE_FORMAT_B2G3R3_UNORM = 204 -PIPE_FORMAT_L16A16_UNORM = 205 -PIPE_FORMAT_A16_UNORM = 206 -PIPE_FORMAT_I16_UNORM = 207 -PIPE_FORMAT_LATC1_UNORM = 208 -PIPE_FORMAT_LATC1_SNORM = 209 -PIPE_FORMAT_LATC2_UNORM = 210 -PIPE_FORMAT_LATC2_SNORM = 211 -PIPE_FORMAT_A8_SNORM = 212 -PIPE_FORMAT_L8_SNORM = 213 -PIPE_FORMAT_L8A8_SNORM = 214 -PIPE_FORMAT_I8_SNORM = 215 -PIPE_FORMAT_A16_SNORM = 216 -PIPE_FORMAT_L16_SNORM = 217 -PIPE_FORMAT_L16A16_SNORM = 218 -PIPE_FORMAT_I16_SNORM = 219 -PIPE_FORMAT_A16_FLOAT = 220 -PIPE_FORMAT_L16_FLOAT = 221 -PIPE_FORMAT_L16A16_FLOAT = 222 -PIPE_FORMAT_I16_FLOAT = 223 -PIPE_FORMAT_A32_FLOAT = 224 -PIPE_FORMAT_L32_FLOAT = 225 -PIPE_FORMAT_L32A32_FLOAT = 226 -PIPE_FORMAT_I32_FLOAT = 227 -PIPE_FORMAT_YV12 = 228 -PIPE_FORMAT_YV16 = 229 -PIPE_FORMAT_IYUV = 230 -PIPE_FORMAT_NV12 = 231 -PIPE_FORMAT_NV21 = 232 -PIPE_FORMAT_NV16 = 233 -PIPE_FORMAT_NV15 = 234 -PIPE_FORMAT_NV20 = 235 -PIPE_FORMAT_Y8_400_UNORM = 236 -PIPE_FORMAT_Y8_U8_V8_422_UNORM = 237 -PIPE_FORMAT_Y8_U8_V8_444_UNORM = 238 -PIPE_FORMAT_Y8_U8_V8_440_UNORM = 239 -PIPE_FORMAT_Y10X6_U10X6_V10X6_420_UNORM = 240 -PIPE_FORMAT_Y10X6_U10X6_V10X6_422_UNORM = 241 -PIPE_FORMAT_Y10X6_U10X6_V10X6_444_UNORM = 242 -PIPE_FORMAT_Y12X4_U12X4_V12X4_420_UNORM = 243 -PIPE_FORMAT_Y12X4_U12X4_V12X4_422_UNORM = 244 -PIPE_FORMAT_Y12X4_U12X4_V12X4_444_UNORM = 245 -PIPE_FORMAT_Y16_U16_V16_420_UNORM = 246 -PIPE_FORMAT_Y16_U16_V16_422_UNORM = 247 -PIPE_FORMAT_Y16_U16V16_422_UNORM = 248 -PIPE_FORMAT_Y16_U16_V16_444_UNORM = 249 -PIPE_FORMAT_Y8U8V8_420_UNORM_PACKED = 250 -PIPE_FORMAT_Y10U10V10_420_UNORM_PACKED = 251 -PIPE_FORMAT_A4R4_UNORM = 252 -PIPE_FORMAT_R4A4_UNORM = 253 -PIPE_FORMAT_R8A8_UNORM = 254 -PIPE_FORMAT_A8R8_UNORM = 255 -PIPE_FORMAT_A8_UINT = 256 -PIPE_FORMAT_I8_UINT = 257 -PIPE_FORMAT_L8_UINT = 258 -PIPE_FORMAT_L8A8_UINT = 259 -PIPE_FORMAT_A8_SINT = 260 -PIPE_FORMAT_I8_SINT = 261 -PIPE_FORMAT_L8_SINT = 262 -PIPE_FORMAT_L8A8_SINT = 263 -PIPE_FORMAT_A16_UINT = 264 -PIPE_FORMAT_I16_UINT = 265 -PIPE_FORMAT_L16_UINT = 266 -PIPE_FORMAT_L16A16_UINT = 267 -PIPE_FORMAT_A16_SINT = 268 -PIPE_FORMAT_I16_SINT = 269 -PIPE_FORMAT_L16_SINT = 270 -PIPE_FORMAT_L16A16_SINT = 271 -PIPE_FORMAT_A32_UINT = 272 -PIPE_FORMAT_I32_UINT = 273 -PIPE_FORMAT_L32_UINT = 274 -PIPE_FORMAT_L32A32_UINT = 275 -PIPE_FORMAT_A32_SINT = 276 -PIPE_FORMAT_I32_SINT = 277 -PIPE_FORMAT_L32_SINT = 278 -PIPE_FORMAT_L32A32_SINT = 279 -PIPE_FORMAT_A8R8G8B8_UINT = 280 -PIPE_FORMAT_A8B8G8R8_UINT = 281 -PIPE_FORMAT_A2R10G10B10_UINT = 282 -PIPE_FORMAT_A2B10G10R10_UINT = 283 -PIPE_FORMAT_R5G6B5_UINT = 284 -PIPE_FORMAT_B5G6R5_UINT = 285 -PIPE_FORMAT_R5G5B5A1_UINT = 286 -PIPE_FORMAT_B5G5R5A1_UINT = 287 -PIPE_FORMAT_A1R5G5B5_UINT = 288 -PIPE_FORMAT_A1B5G5R5_UINT = 289 -PIPE_FORMAT_R4G4B4A4_UINT = 290 -PIPE_FORMAT_B4G4R4A4_UINT = 291 -PIPE_FORMAT_A4R4G4B4_UINT = 292 -PIPE_FORMAT_A4B4G4R4_UINT = 293 -PIPE_FORMAT_R3G3B2_UINT = 294 -PIPE_FORMAT_B2G3R3_UINT = 295 -PIPE_FORMAT_ETC1_RGB8 = 296 -PIPE_FORMAT_R8G8_R8B8_UNORM = 297 -PIPE_FORMAT_R8B8_R8G8_UNORM = 298 -PIPE_FORMAT_G8R8_B8R8_UNORM = 299 -PIPE_FORMAT_B8R8_G8R8_UNORM = 300 -PIPE_FORMAT_G8B8_G8R8_UNORM = 301 -PIPE_FORMAT_B8G8_R8G8_UNORM = 302 -PIPE_FORMAT_R8G8B8X8_SNORM = 303 -PIPE_FORMAT_R8G8B8X8_SRGB = 304 -PIPE_FORMAT_R8G8B8X8_UINT = 305 -PIPE_FORMAT_R8G8B8X8_SINT = 306 -PIPE_FORMAT_B10G10R10X2_UNORM = 307 -PIPE_FORMAT_R16G16B16X16_UNORM = 308 -PIPE_FORMAT_R16G16B16X16_SNORM = 309 -PIPE_FORMAT_R16G16B16X16_FLOAT = 310 -PIPE_FORMAT_R16G16B16X16_UINT = 311 -PIPE_FORMAT_R16G16B16X16_SINT = 312 -PIPE_FORMAT_R32G32B32X32_FLOAT = 313 -PIPE_FORMAT_R32G32B32X32_UINT = 314 -PIPE_FORMAT_R32G32B32X32_SINT = 315 -PIPE_FORMAT_R8A8_SNORM = 316 -PIPE_FORMAT_R16A16_UNORM = 317 -PIPE_FORMAT_R16A16_SNORM = 318 -PIPE_FORMAT_R16A16_FLOAT = 319 -PIPE_FORMAT_R32A32_FLOAT = 320 -PIPE_FORMAT_R8A8_UINT = 321 -PIPE_FORMAT_R8A8_SINT = 322 -PIPE_FORMAT_R16A16_UINT = 323 -PIPE_FORMAT_R16A16_SINT = 324 -PIPE_FORMAT_R32A32_UINT = 325 -PIPE_FORMAT_R32A32_SINT = 326 -PIPE_FORMAT_B5G6R5_SRGB = 327 -PIPE_FORMAT_BPTC_RGBA_UNORM = 328 -PIPE_FORMAT_BPTC_SRGBA = 329 -PIPE_FORMAT_BPTC_RGB_FLOAT = 330 -PIPE_FORMAT_BPTC_RGB_UFLOAT = 331 -PIPE_FORMAT_G8R8_UNORM = 332 -PIPE_FORMAT_G8R8_SNORM = 333 -PIPE_FORMAT_G16R16_UNORM = 334 -PIPE_FORMAT_G16R16_SNORM = 335 -PIPE_FORMAT_A8B8G8R8_SNORM = 336 -PIPE_FORMAT_X8B8G8R8_SNORM = 337 -PIPE_FORMAT_ETC2_RGB8 = 338 -PIPE_FORMAT_ETC2_SRGB8 = 339 -PIPE_FORMAT_ETC2_RGB8A1 = 340 -PIPE_FORMAT_ETC2_SRGB8A1 = 341 -PIPE_FORMAT_ETC2_RGBA8 = 342 -PIPE_FORMAT_ETC2_SRGBA8 = 343 -PIPE_FORMAT_ETC2_R11_UNORM = 344 -PIPE_FORMAT_ETC2_R11_SNORM = 345 -PIPE_FORMAT_ETC2_RG11_UNORM = 346 -PIPE_FORMAT_ETC2_RG11_SNORM = 347 -PIPE_FORMAT_ASTC_4x4 = 348 -PIPE_FORMAT_ASTC_5x4 = 349 -PIPE_FORMAT_ASTC_5x5 = 350 -PIPE_FORMAT_ASTC_6x5 = 351 -PIPE_FORMAT_ASTC_6x6 = 352 -PIPE_FORMAT_ASTC_8x5 = 353 -PIPE_FORMAT_ASTC_8x6 = 354 -PIPE_FORMAT_ASTC_8x8 = 355 -PIPE_FORMAT_ASTC_10x5 = 356 -PIPE_FORMAT_ASTC_10x6 = 357 -PIPE_FORMAT_ASTC_10x8 = 358 -PIPE_FORMAT_ASTC_10x10 = 359 -PIPE_FORMAT_ASTC_12x10 = 360 -PIPE_FORMAT_ASTC_12x12 = 361 -PIPE_FORMAT_ASTC_4x4_SRGB = 362 -PIPE_FORMAT_ASTC_5x4_SRGB = 363 -PIPE_FORMAT_ASTC_5x5_SRGB = 364 -PIPE_FORMAT_ASTC_6x5_SRGB = 365 -PIPE_FORMAT_ASTC_6x6_SRGB = 366 -PIPE_FORMAT_ASTC_8x5_SRGB = 367 -PIPE_FORMAT_ASTC_8x6_SRGB = 368 -PIPE_FORMAT_ASTC_8x8_SRGB = 369 -PIPE_FORMAT_ASTC_10x5_SRGB = 370 -PIPE_FORMAT_ASTC_10x6_SRGB = 371 -PIPE_FORMAT_ASTC_10x8_SRGB = 372 -PIPE_FORMAT_ASTC_10x10_SRGB = 373 -PIPE_FORMAT_ASTC_12x10_SRGB = 374 -PIPE_FORMAT_ASTC_12x12_SRGB = 375 -PIPE_FORMAT_ASTC_3x3x3 = 376 -PIPE_FORMAT_ASTC_4x3x3 = 377 -PIPE_FORMAT_ASTC_4x4x3 = 378 -PIPE_FORMAT_ASTC_4x4x4 = 379 -PIPE_FORMAT_ASTC_5x4x4 = 380 -PIPE_FORMAT_ASTC_5x5x4 = 381 -PIPE_FORMAT_ASTC_5x5x5 = 382 -PIPE_FORMAT_ASTC_6x5x5 = 383 -PIPE_FORMAT_ASTC_6x6x5 = 384 -PIPE_FORMAT_ASTC_6x6x6 = 385 -PIPE_FORMAT_ASTC_3x3x3_SRGB = 386 -PIPE_FORMAT_ASTC_4x3x3_SRGB = 387 -PIPE_FORMAT_ASTC_4x4x3_SRGB = 388 -PIPE_FORMAT_ASTC_4x4x4_SRGB = 389 -PIPE_FORMAT_ASTC_5x4x4_SRGB = 390 -PIPE_FORMAT_ASTC_5x5x4_SRGB = 391 -PIPE_FORMAT_ASTC_5x5x5_SRGB = 392 -PIPE_FORMAT_ASTC_6x5x5_SRGB = 393 -PIPE_FORMAT_ASTC_6x6x5_SRGB = 394 -PIPE_FORMAT_ASTC_6x6x6_SRGB = 395 -PIPE_FORMAT_ASTC_4x4_FLOAT = 396 -PIPE_FORMAT_ASTC_5x4_FLOAT = 397 -PIPE_FORMAT_ASTC_5x5_FLOAT = 398 -PIPE_FORMAT_ASTC_6x5_FLOAT = 399 -PIPE_FORMAT_ASTC_6x6_FLOAT = 400 -PIPE_FORMAT_ASTC_8x5_FLOAT = 401 -PIPE_FORMAT_ASTC_8x6_FLOAT = 402 -PIPE_FORMAT_ASTC_8x8_FLOAT = 403 -PIPE_FORMAT_ASTC_10x5_FLOAT = 404 -PIPE_FORMAT_ASTC_10x6_FLOAT = 405 -PIPE_FORMAT_ASTC_10x8_FLOAT = 406 -PIPE_FORMAT_ASTC_10x10_FLOAT = 407 -PIPE_FORMAT_ASTC_12x10_FLOAT = 408 -PIPE_FORMAT_ASTC_12x12_FLOAT = 409 -PIPE_FORMAT_FXT1_RGB = 410 -PIPE_FORMAT_FXT1_RGBA = 411 -PIPE_FORMAT_P010 = 412 -PIPE_FORMAT_P012 = 413 -PIPE_FORMAT_P016 = 414 -PIPE_FORMAT_P030 = 415 -PIPE_FORMAT_Y210 = 416 -PIPE_FORMAT_Y212 = 417 -PIPE_FORMAT_Y216 = 418 -PIPE_FORMAT_Y410 = 419 -PIPE_FORMAT_Y412 = 420 -PIPE_FORMAT_Y416 = 421 -PIPE_FORMAT_R10G10B10X2_UNORM = 422 -PIPE_FORMAT_A1R5G5B5_UNORM = 423 -PIPE_FORMAT_A1B5G5R5_UNORM = 424 -PIPE_FORMAT_X1B5G5R5_UNORM = 425 -PIPE_FORMAT_R5G5B5A1_UNORM = 426 -PIPE_FORMAT_A4R4G4B4_UNORM = 427 -PIPE_FORMAT_A4B4G4R4_UNORM = 428 -PIPE_FORMAT_G8R8_SINT = 429 -PIPE_FORMAT_A8B8G8R8_SINT = 430 -PIPE_FORMAT_X8B8G8R8_SINT = 431 -PIPE_FORMAT_ATC_RGB = 432 -PIPE_FORMAT_ATC_RGBA_EXPLICIT = 433 -PIPE_FORMAT_ATC_RGBA_INTERPOLATED = 434 -PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 435 -PIPE_FORMAT_AYUV = 436 -PIPE_FORMAT_XYUV = 437 -PIPE_FORMAT_R8G8B8_420_UNORM_PACKED = 438 -PIPE_FORMAT_R8_G8B8_420_UNORM = 439 -PIPE_FORMAT_R8_B8G8_420_UNORM = 440 -PIPE_FORMAT_G8_B8R8_420_UNORM = 441 -PIPE_FORMAT_R10G10B10_420_UNORM_PACKED = 442 -PIPE_FORMAT_R10_G10B10_420_UNORM = 443 -PIPE_FORMAT_R10_G10B10_422_UNORM = 444 -PIPE_FORMAT_R8_G8_B8_420_UNORM = 445 -PIPE_FORMAT_R8_B8_G8_420_UNORM = 446 -PIPE_FORMAT_G8_B8_R8_420_UNORM = 447 -PIPE_FORMAT_R8_G8B8_422_UNORM = 448 -PIPE_FORMAT_R8_B8G8_422_UNORM = 449 -PIPE_FORMAT_G8_B8R8_422_UNORM = 450 -PIPE_FORMAT_R8_G8_B8_UNORM = 451 -PIPE_FORMAT_Y8_UNORM = 452 -PIPE_FORMAT_B8G8R8X8_SNORM = 453 -PIPE_FORMAT_B8G8R8X8_UINT = 454 -PIPE_FORMAT_B8G8R8X8_SINT = 455 -PIPE_FORMAT_A8R8G8B8_SNORM = 456 -PIPE_FORMAT_A8R8G8B8_SINT = 457 -PIPE_FORMAT_X8R8G8B8_SNORM = 458 -PIPE_FORMAT_X8R8G8B8_SINT = 459 -PIPE_FORMAT_R5G5B5X1_UNORM = 460 -PIPE_FORMAT_X1R5G5B5_UNORM = 461 -PIPE_FORMAT_R4G4B4X4_UNORM = 462 -PIPE_FORMAT_B10G10R10X2_SNORM = 463 -PIPE_FORMAT_R5G6B5_SRGB = 464 -PIPE_FORMAT_R10G10B10X2_SINT = 465 -PIPE_FORMAT_B10G10R10X2_SINT = 466 -PIPE_FORMAT_G16R16_SINT = 467 -PIPE_FORMAT_COUNT = 468 -pipe_format = ctypes.c_uint32 # enum -class union_glsl_struct_field_0(Union): - pass - -class struct_glsl_struct_field_0_0(Structure): - pass - -struct_glsl_struct_field_0_0._pack_ = 1 # source:False -struct_glsl_struct_field_0_0._fields_ = [ - ('interpolation', ctypes.c_uint32, 3), - ('centroid', ctypes.c_uint32, 1), - ('sample', ctypes.c_uint32, 1), - ('matrix_layout', ctypes.c_uint32, 2), - ('patch', ctypes.c_uint32, 1), - ('precision', ctypes.c_uint32, 2), - ('memory_read_only', ctypes.c_uint32, 1), - ('memory_write_only', ctypes.c_uint32, 1), - ('memory_coherent', ctypes.c_uint32, 1), - ('memory_volatile', ctypes.c_uint32, 1), - ('memory_restrict', ctypes.c_uint32, 1), - ('explicit_xfb_buffer', ctypes.c_uint32, 1), - ('implicit_sized_array', ctypes.c_uint32, 1), - ('PADDING_0', ctypes.c_uint16, 15), -] - -union_glsl_struct_field_0._pack_ = 1 # source:False -union_glsl_struct_field_0._anonymous_ = ('_0',) -union_glsl_struct_field_0._fields_ = [ - ('_0', struct_glsl_struct_field_0_0), - ('flags', ctypes.c_uint32), -] - -struct_glsl_struct_field._pack_ = 1 # source:False -struct_glsl_struct_field._anonymous_ = ('_0',) -struct_glsl_struct_field._fields_ = [ - ('type', ctypes.POINTER(struct_glsl_type)), - ('name', ctypes.POINTER(ctypes.c_char)), - ('location', ctypes.c_int32), - ('component', ctypes.c_int32), - ('offset', ctypes.c_int32), - ('xfb_buffer', ctypes.c_int32), - ('xfb_stride', ctypes.c_int32), - ('image_format', pipe_format), - ('_0', union_glsl_struct_field_0), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -glsl_struct_field = struct_glsl_struct_field -try: - glsl_type_singleton_init_or_ref = _libraries['libtinymesa_cpu.so'].glsl_type_singleton_init_or_ref - glsl_type_singleton_init_or_ref.restype = None - glsl_type_singleton_init_or_ref.argtypes = [] -except AttributeError: - pass -try: - glsl_type_singleton_decref = _libraries['libtinymesa_cpu.so'].glsl_type_singleton_decref - glsl_type_singleton_decref.restype = None - glsl_type_singleton_decref.argtypes = [] -except AttributeError: - pass -try: - encode_type_to_blob = _libraries['libtinymesa_cpu.so'].encode_type_to_blob - encode_type_to_blob.restype = None - encode_type_to_blob.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - decode_type_from_blob = _libraries['libtinymesa_cpu.so'].decode_type_from_blob - decode_type_from_blob.restype = ctypes.POINTER(struct_glsl_type) - decode_type_from_blob.argtypes = [ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -glsl_type_size_align_func = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)) -try: - glsl_base_type_bit_size = _libraries['FIXME_STUB'].glsl_base_type_bit_size - glsl_base_type_bit_size.restype = ctypes.c_uint32 - glsl_base_type_bit_size.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_base_type_is_16bit = _libraries['FIXME_STUB'].glsl_base_type_is_16bit - glsl_base_type_is_16bit.restype = ctypes.c_bool - glsl_base_type_is_16bit.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_base_type_is_64bit = _libraries['FIXME_STUB'].glsl_base_type_is_64bit - glsl_base_type_is_64bit.restype = ctypes.c_bool - glsl_base_type_is_64bit.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_base_type_is_integer = _libraries['FIXME_STUB'].glsl_base_type_is_integer - glsl_base_type_is_integer.restype = ctypes.c_bool - glsl_base_type_is_integer.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_base_type_is_float = _libraries['FIXME_STUB'].glsl_base_type_is_float - glsl_base_type_is_float.restype = ctypes.c_bool - glsl_base_type_is_float.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_base_type_get_bit_size = _libraries['FIXME_STUB'].glsl_base_type_get_bit_size - glsl_base_type_get_bit_size.restype = ctypes.c_uint32 - glsl_base_type_get_bit_size.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_unsigned_base_type_of = _libraries['FIXME_STUB'].glsl_unsigned_base_type_of - glsl_unsigned_base_type_of.restype = glsl_base_type - glsl_unsigned_base_type_of.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_signed_base_type_of = _libraries['FIXME_STUB'].glsl_signed_base_type_of - glsl_signed_base_type_of.restype = glsl_base_type - glsl_signed_base_type_of.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_apply_signedness_to_base_type = _libraries['libtinymesa_cpu.so'].glsl_apply_signedness_to_base_type - glsl_apply_signedness_to_base_type.restype = glsl_base_type - glsl_apply_signedness_to_base_type.argtypes = [glsl_base_type, ctypes.c_bool] -except AttributeError: - pass - -# values for enumeration 'glsl_sampler_dim' -glsl_sampler_dim__enumvalues = { - 0: 'GLSL_SAMPLER_DIM_1D', - 1: 'GLSL_SAMPLER_DIM_2D', - 2: 'GLSL_SAMPLER_DIM_3D', - 3: 'GLSL_SAMPLER_DIM_CUBE', - 4: 'GLSL_SAMPLER_DIM_RECT', - 5: 'GLSL_SAMPLER_DIM_BUF', - 6: 'GLSL_SAMPLER_DIM_EXTERNAL', - 7: 'GLSL_SAMPLER_DIM_MS', - 8: 'GLSL_SAMPLER_DIM_SUBPASS', - 9: 'GLSL_SAMPLER_DIM_SUBPASS_MS', -} -GLSL_SAMPLER_DIM_1D = 0 -GLSL_SAMPLER_DIM_2D = 1 -GLSL_SAMPLER_DIM_3D = 2 -GLSL_SAMPLER_DIM_CUBE = 3 -GLSL_SAMPLER_DIM_RECT = 4 -GLSL_SAMPLER_DIM_BUF = 5 -GLSL_SAMPLER_DIM_EXTERNAL = 6 -GLSL_SAMPLER_DIM_MS = 7 -GLSL_SAMPLER_DIM_SUBPASS = 8 -GLSL_SAMPLER_DIM_SUBPASS_MS = 9 -glsl_sampler_dim = ctypes.c_uint32 # enum -try: - glsl_get_sampler_dim_coordinate_components = _libraries['libtinymesa_cpu.so'].glsl_get_sampler_dim_coordinate_components - glsl_get_sampler_dim_coordinate_components.restype = ctypes.c_int32 - glsl_get_sampler_dim_coordinate_components.argtypes = [glsl_sampler_dim] -except AttributeError: - pass - -# values for enumeration 'glsl_matrix_layout' -glsl_matrix_layout__enumvalues = { - 0: 'GLSL_MATRIX_LAYOUT_INHERITED', - 1: 'GLSL_MATRIX_LAYOUT_COLUMN_MAJOR', - 2: 'GLSL_MATRIX_LAYOUT_ROW_MAJOR', -} -GLSL_MATRIX_LAYOUT_INHERITED = 0 -GLSL_MATRIX_LAYOUT_COLUMN_MAJOR = 1 -GLSL_MATRIX_LAYOUT_ROW_MAJOR = 2 -glsl_matrix_layout = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_GLSL_PRECISION_NONE' -c__Ea_GLSL_PRECISION_NONE__enumvalues = { - 0: 'GLSL_PRECISION_NONE', - 1: 'GLSL_PRECISION_HIGH', - 2: 'GLSL_PRECISION_MEDIUM', - 3: 'GLSL_PRECISION_LOW', -} -GLSL_PRECISION_NONE = 0 -GLSL_PRECISION_HIGH = 1 -GLSL_PRECISION_MEDIUM = 2 -GLSL_PRECISION_LOW = 3 -c__Ea_GLSL_PRECISION_NONE = ctypes.c_uint32 # enum - -# values for enumeration 'glsl_cmat_use' -glsl_cmat_use__enumvalues = { - 0: 'GLSL_CMAT_USE_NONE', - 1: 'GLSL_CMAT_USE_A', - 2: 'GLSL_CMAT_USE_B', - 3: 'GLSL_CMAT_USE_ACCUMULATOR', -} -GLSL_CMAT_USE_NONE = 0 -GLSL_CMAT_USE_A = 1 -GLSL_CMAT_USE_B = 2 -GLSL_CMAT_USE_ACCUMULATOR = 3 -glsl_cmat_use = ctypes.c_uint32 # enum -try: - glsl_get_type_name = _libraries['libtinymesa_cpu.so'].glsl_get_type_name - glsl_get_type_name.restype = ctypes.POINTER(ctypes.c_char) - glsl_get_type_name.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_base_type = _libraries['FIXME_STUB'].glsl_get_base_type - glsl_get_base_type.restype = glsl_base_type - glsl_get_base_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_bit_size = _libraries['FIXME_STUB'].glsl_get_bit_size - glsl_get_bit_size.restype = ctypes.c_uint32 - glsl_get_bit_size.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_boolean = _libraries['FIXME_STUB'].glsl_type_is_boolean - glsl_type_is_boolean.restype = ctypes.c_bool - glsl_type_is_boolean.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_sampler = _libraries['FIXME_STUB'].glsl_type_is_sampler - glsl_type_is_sampler.restype = ctypes.c_bool - glsl_type_is_sampler.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_texture = _libraries['FIXME_STUB'].glsl_type_is_texture - glsl_type_is_texture.restype = ctypes.c_bool - glsl_type_is_texture.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_image = _libraries['FIXME_STUB'].glsl_type_is_image - glsl_type_is_image.restype = ctypes.c_bool - glsl_type_is_image.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_atomic_uint = _libraries['FIXME_STUB'].glsl_type_is_atomic_uint - glsl_type_is_atomic_uint.restype = ctypes.c_bool - glsl_type_is_atomic_uint.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_struct = _libraries['FIXME_STUB'].glsl_type_is_struct - glsl_type_is_struct.restype = ctypes.c_bool - glsl_type_is_struct.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_interface = _libraries['FIXME_STUB'].glsl_type_is_interface - glsl_type_is_interface.restype = ctypes.c_bool - glsl_type_is_interface.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_array = _libraries['FIXME_STUB'].glsl_type_is_array - glsl_type_is_array.restype = ctypes.c_bool - glsl_type_is_array.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_cmat = _libraries['FIXME_STUB'].glsl_type_is_cmat - glsl_type_is_cmat.restype = ctypes.c_bool - glsl_type_is_cmat.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_void = _libraries['FIXME_STUB'].glsl_type_is_void - glsl_type_is_void.restype = ctypes.c_bool - glsl_type_is_void.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_subroutine = _libraries['FIXME_STUB'].glsl_type_is_subroutine - glsl_type_is_subroutine.restype = ctypes.c_bool - glsl_type_is_subroutine.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_error = _libraries['FIXME_STUB'].glsl_type_is_error - glsl_type_is_error.restype = ctypes.c_bool - glsl_type_is_error.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_double = _libraries['FIXME_STUB'].glsl_type_is_double - glsl_type_is_double.restype = ctypes.c_bool - glsl_type_is_double.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_float = _libraries['FIXME_STUB'].glsl_type_is_float - glsl_type_is_float.restype = ctypes.c_bool - glsl_type_is_float.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_numeric = _libraries['FIXME_STUB'].glsl_type_is_numeric - glsl_type_is_numeric.restype = ctypes.c_bool - glsl_type_is_numeric.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer = _libraries['FIXME_STUB'].glsl_type_is_integer - glsl_type_is_integer.restype = ctypes.c_bool - glsl_type_is_integer.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_struct_or_ifc = _libraries['FIXME_STUB'].glsl_type_is_struct_or_ifc - glsl_type_is_struct_or_ifc.restype = ctypes.c_bool - glsl_type_is_struct_or_ifc.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_packed = _libraries['FIXME_STUB'].glsl_type_is_packed - glsl_type_is_packed.restype = ctypes.c_bool - glsl_type_is_packed.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_16bit = _libraries['FIXME_STUB'].glsl_type_is_16bit - glsl_type_is_16bit.restype = ctypes.c_bool - glsl_type_is_16bit.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_32bit = _libraries['FIXME_STUB'].glsl_type_is_32bit - glsl_type_is_32bit.restype = ctypes.c_bool - glsl_type_is_32bit.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_64bit = _libraries['FIXME_STUB'].glsl_type_is_64bit - glsl_type_is_64bit.restype = ctypes.c_bool - glsl_type_is_64bit.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer_16 = _libraries['FIXME_STUB'].glsl_type_is_integer_16 - glsl_type_is_integer_16.restype = ctypes.c_bool - glsl_type_is_integer_16.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer_32 = _libraries['FIXME_STUB'].glsl_type_is_integer_32 - glsl_type_is_integer_32.restype = ctypes.c_bool - glsl_type_is_integer_32.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer_64 = _libraries['FIXME_STUB'].glsl_type_is_integer_64 - glsl_type_is_integer_64.restype = ctypes.c_bool - glsl_type_is_integer_64.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer_32_64 = _libraries['FIXME_STUB'].glsl_type_is_integer_32_64 - glsl_type_is_integer_32_64.restype = ctypes.c_bool - glsl_type_is_integer_32_64.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer_16_32 = _libraries['FIXME_STUB'].glsl_type_is_integer_16_32 - glsl_type_is_integer_16_32.restype = ctypes.c_bool - glsl_type_is_integer_16_32.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_integer_16_32_64 = _libraries['FIXME_STUB'].glsl_type_is_integer_16_32_64 - glsl_type_is_integer_16_32_64.restype = ctypes.c_bool - glsl_type_is_integer_16_32_64.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_float_16 = _libraries['FIXME_STUB'].glsl_type_is_float_16 - glsl_type_is_float_16.restype = ctypes.c_bool - glsl_type_is_float_16.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_float_16_32 = _libraries['FIXME_STUB'].glsl_type_is_float_16_32 - glsl_type_is_float_16_32.restype = ctypes.c_bool - glsl_type_is_float_16_32.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_float_16_32_64 = _libraries['FIXME_STUB'].glsl_type_is_float_16_32_64 - glsl_type_is_float_16_32_64.restype = ctypes.c_bool - glsl_type_is_float_16_32_64.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_bfloat_16 = _libraries['FIXME_STUB'].glsl_type_is_bfloat_16 - glsl_type_is_bfloat_16.restype = ctypes.c_bool - glsl_type_is_bfloat_16.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_e4m3fn = _libraries['FIXME_STUB'].glsl_type_is_e4m3fn - glsl_type_is_e4m3fn.restype = ctypes.c_bool - glsl_type_is_e4m3fn.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_e5m2 = _libraries['FIXME_STUB'].glsl_type_is_e5m2 - glsl_type_is_e5m2.restype = ctypes.c_bool - glsl_type_is_e5m2.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_int_16_32_64 = _libraries['FIXME_STUB'].glsl_type_is_int_16_32_64 - glsl_type_is_int_16_32_64.restype = ctypes.c_bool - glsl_type_is_int_16_32_64.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_uint_16_32_64 = _libraries['FIXME_STUB'].glsl_type_is_uint_16_32_64 - glsl_type_is_uint_16_32_64.restype = ctypes.c_bool - glsl_type_is_uint_16_32_64.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_int_16_32 = _libraries['FIXME_STUB'].glsl_type_is_int_16_32 - glsl_type_is_int_16_32.restype = ctypes.c_bool - glsl_type_is_int_16_32.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_uint_16_32 = _libraries['FIXME_STUB'].glsl_type_is_uint_16_32 - glsl_type_is_uint_16_32.restype = ctypes.c_bool - glsl_type_is_uint_16_32.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_unsized_array = _libraries['FIXME_STUB'].glsl_type_is_unsized_array - glsl_type_is_unsized_array.restype = ctypes.c_bool - glsl_type_is_unsized_array.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_array_of_arrays = _libraries['FIXME_STUB'].glsl_type_is_array_of_arrays - glsl_type_is_array_of_arrays.restype = ctypes.c_bool - glsl_type_is_array_of_arrays.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_bare_sampler = _libraries['FIXME_STUB'].glsl_type_is_bare_sampler - glsl_type_is_bare_sampler.restype = ctypes.c_bool - glsl_type_is_bare_sampler.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_vector = _libraries['libtinymesa_cpu.so'].glsl_type_is_vector - glsl_type_is_vector.restype = ctypes.c_bool - glsl_type_is_vector.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_scalar = _libraries['libtinymesa_cpu.so'].glsl_type_is_scalar - glsl_type_is_scalar.restype = ctypes.c_bool - glsl_type_is_scalar.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_vector_or_scalar = _libraries['libtinymesa_cpu.so'].glsl_type_is_vector_or_scalar - glsl_type_is_vector_or_scalar.restype = ctypes.c_bool - glsl_type_is_vector_or_scalar.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_matrix = _libraries['libtinymesa_cpu.so'].glsl_type_is_matrix - glsl_type_is_matrix.restype = ctypes.c_bool - glsl_type_is_matrix.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_array_or_matrix = _libraries['libtinymesa_cpu.so'].glsl_type_is_array_or_matrix - glsl_type_is_array_or_matrix.restype = ctypes.c_bool - glsl_type_is_array_or_matrix.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_dual_slot = _libraries['libtinymesa_cpu.so'].glsl_type_is_dual_slot - glsl_type_is_dual_slot.restype = ctypes.c_bool - glsl_type_is_dual_slot.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_is_leaf = _libraries['libtinymesa_cpu.so'].glsl_type_is_leaf - glsl_type_is_leaf.restype = ctypes.c_bool - glsl_type_is_leaf.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_matrix_type_is_row_major = _libraries['FIXME_STUB'].glsl_matrix_type_is_row_major - glsl_matrix_type_is_row_major.restype = ctypes.c_bool - glsl_matrix_type_is_row_major.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_sampler_type_is_shadow = _libraries['FIXME_STUB'].glsl_sampler_type_is_shadow - glsl_sampler_type_is_shadow.restype = ctypes.c_bool - glsl_sampler_type_is_shadow.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_sampler_type_is_array = _libraries['FIXME_STUB'].glsl_sampler_type_is_array - glsl_sampler_type_is_array.restype = ctypes.c_bool - glsl_sampler_type_is_array.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_struct_type_is_packed = _libraries['FIXME_STUB'].glsl_struct_type_is_packed - glsl_struct_type_is_packed.restype = ctypes.c_bool - glsl_struct_type_is_packed.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_bare_type = _libraries['libtinymesa_cpu.so'].glsl_get_bare_type - glsl_get_bare_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_bare_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_scalar_type = _libraries['libtinymesa_cpu.so'].glsl_get_scalar_type - glsl_get_scalar_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_scalar_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_base_glsl_type = _libraries['libtinymesa_cpu.so'].glsl_get_base_glsl_type - glsl_get_base_glsl_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_base_glsl_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_length = _libraries['libtinymesa_cpu.so'].glsl_get_length - glsl_get_length.restype = ctypes.c_uint32 - glsl_get_length.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_vector_elements = _libraries['FIXME_STUB'].glsl_get_vector_elements - glsl_get_vector_elements.restype = ctypes.c_uint32 - glsl_get_vector_elements.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_components = _libraries['FIXME_STUB'].glsl_get_components - glsl_get_components.restype = ctypes.c_uint32 - glsl_get_components.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_matrix_columns = _libraries['FIXME_STUB'].glsl_get_matrix_columns - glsl_get_matrix_columns.restype = ctypes.c_uint32 - glsl_get_matrix_columns.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_wrap_in_arrays = _libraries['libtinymesa_cpu.so'].glsl_type_wrap_in_arrays - glsl_type_wrap_in_arrays.restype = ctypes.POINTER(struct_glsl_type) - glsl_type_wrap_in_arrays.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_array_size = _libraries['FIXME_STUB'].glsl_array_size - glsl_array_size.restype = ctypes.c_int32 - glsl_array_size.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_aoa_size = _libraries['libtinymesa_cpu.so'].glsl_get_aoa_size - glsl_get_aoa_size.restype = ctypes.c_uint32 - glsl_get_aoa_size.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_array_element = _libraries['libtinymesa_cpu.so'].glsl_get_array_element - glsl_get_array_element.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_array_element.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_without_array = _libraries['libtinymesa_cpu.so'].glsl_without_array - glsl_without_array.restype = ctypes.POINTER(struct_glsl_type) - glsl_without_array.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_without_array_or_matrix = _libraries['libtinymesa_cpu.so'].glsl_without_array_or_matrix - glsl_without_array_or_matrix.restype = ctypes.POINTER(struct_glsl_type) - glsl_without_array_or_matrix.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_cmat_element = _libraries['libtinymesa_cpu.so'].glsl_get_cmat_element - glsl_get_cmat_element.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_cmat_element.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_cmat_description = _libraries['libtinymesa_cpu.so'].glsl_get_cmat_description - glsl_get_cmat_description.restype = ctypes.POINTER(struct_glsl_cmat_description) - glsl_get_cmat_description.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_atomic_size = _libraries['libtinymesa_cpu.so'].glsl_atomic_size - glsl_atomic_size.restype = ctypes.c_uint32 - glsl_atomic_size.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_contains_32bit = _libraries['libtinymesa_cpu.so'].glsl_type_contains_32bit - glsl_type_contains_32bit.restype = ctypes.c_bool - glsl_type_contains_32bit.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_contains_64bit = _libraries['libtinymesa_cpu.so'].glsl_type_contains_64bit - glsl_type_contains_64bit.restype = ctypes.c_bool - glsl_type_contains_64bit.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_contains_image = _libraries['libtinymesa_cpu.so'].glsl_type_contains_image - glsl_type_contains_image.restype = ctypes.c_bool - glsl_type_contains_image.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_atomic = _libraries['libtinymesa_cpu.so'].glsl_contains_atomic - glsl_contains_atomic.restype = ctypes.c_bool - glsl_contains_atomic.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_double = _libraries['libtinymesa_cpu.so'].glsl_contains_double - glsl_contains_double.restype = ctypes.c_bool - glsl_contains_double.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_integer = _libraries['libtinymesa_cpu.so'].glsl_contains_integer - glsl_contains_integer.restype = ctypes.c_bool - glsl_contains_integer.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_opaque = _libraries['libtinymesa_cpu.so'].glsl_contains_opaque - glsl_contains_opaque.restype = ctypes.c_bool - glsl_contains_opaque.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_sampler = _libraries['libtinymesa_cpu.so'].glsl_contains_sampler - glsl_contains_sampler.restype = ctypes.c_bool - glsl_contains_sampler.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_array = _libraries['libtinymesa_cpu.so'].glsl_contains_array - glsl_contains_array.restype = ctypes.c_bool - glsl_contains_array.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_contains_subroutine = _libraries['libtinymesa_cpu.so'].glsl_contains_subroutine - glsl_contains_subroutine.restype = ctypes.c_bool - glsl_contains_subroutine.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_sampler_dim = _libraries['FIXME_STUB'].glsl_get_sampler_dim - glsl_get_sampler_dim.restype = glsl_sampler_dim - glsl_get_sampler_dim.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_sampler_result_type = _libraries['FIXME_STUB'].glsl_get_sampler_result_type - glsl_get_sampler_result_type.restype = glsl_base_type - glsl_get_sampler_result_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_sampler_coordinate_components = _libraries['libtinymesa_cpu.so'].glsl_get_sampler_coordinate_components - glsl_get_sampler_coordinate_components.restype = ctypes.c_int32 - glsl_get_sampler_coordinate_components.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_compare_no_precision = _libraries['libtinymesa_cpu.so'].glsl_type_compare_no_precision - glsl_type_compare_no_precision.restype = ctypes.c_bool - glsl_type_compare_no_precision.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_record_compare = _libraries['libtinymesa_cpu.so'].glsl_record_compare - glsl_record_compare.restype = ctypes.c_bool - glsl_record_compare.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(struct_glsl_type), ctypes.c_bool, ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_struct_field = _libraries['libtinymesa_cpu.so'].glsl_get_struct_field - glsl_get_struct_field.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_struct_field.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_get_struct_field_data = _libraries['libtinymesa_cpu.so'].glsl_get_struct_field_data - glsl_get_struct_field_data.restype = ctypes.POINTER(struct_glsl_struct_field) - glsl_get_struct_field_data.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_get_struct_location_offset = _libraries['libtinymesa_cpu.so'].glsl_get_struct_location_offset - glsl_get_struct_location_offset.restype = ctypes.c_uint32 - glsl_get_struct_location_offset.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_get_field_index = _libraries['libtinymesa_cpu.so'].glsl_get_field_index - glsl_get_field_index.restype = ctypes.c_int32 - glsl_get_field_index.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - glsl_get_field_type = _libraries['libtinymesa_cpu.so'].glsl_get_field_type - glsl_get_field_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_field_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - glsl_get_struct_field_offset = _libraries['FIXME_STUB'].glsl_get_struct_field_offset - glsl_get_struct_field_offset.restype = ctypes.c_int32 - glsl_get_struct_field_offset.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_get_struct_elem_name = _libraries['FIXME_STUB'].glsl_get_struct_elem_name - glsl_get_struct_elem_name.restype = ctypes.POINTER(ctypes.c_char) - glsl_get_struct_elem_name.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_void_type = _libraries['FIXME_STUB'].glsl_void_type - glsl_void_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_void_type.argtypes = [] -except AttributeError: - pass -try: - glsl_float_type = _libraries['FIXME_STUB'].glsl_float_type - glsl_float_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_float_type.argtypes = [] -except AttributeError: - pass -try: - glsl_float16_t_type = _libraries['FIXME_STUB'].glsl_float16_t_type - glsl_float16_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_float16_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_double_type = _libraries['FIXME_STUB'].glsl_double_type - glsl_double_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_double_type.argtypes = [] -except AttributeError: - pass -try: - glsl_vec2_type = _libraries['FIXME_STUB'].glsl_vec2_type - glsl_vec2_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_vec2_type.argtypes = [] -except AttributeError: - pass -try: - glsl_dvec2_type = _libraries['FIXME_STUB'].glsl_dvec2_type - glsl_dvec2_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_dvec2_type.argtypes = [] -except AttributeError: - pass -try: - glsl_uvec2_type = _libraries['FIXME_STUB'].glsl_uvec2_type - glsl_uvec2_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uvec2_type.argtypes = [] -except AttributeError: - pass -try: - glsl_ivec2_type = _libraries['FIXME_STUB'].glsl_ivec2_type - glsl_ivec2_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_ivec2_type.argtypes = [] -except AttributeError: - pass -try: - glsl_bvec2_type = _libraries['FIXME_STUB'].glsl_bvec2_type - glsl_bvec2_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bvec2_type.argtypes = [] -except AttributeError: - pass -try: - glsl_vec4_type = _libraries['FIXME_STUB'].glsl_vec4_type - glsl_vec4_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_vec4_type.argtypes = [] -except AttributeError: - pass -try: - glsl_dvec4_type = _libraries['FIXME_STUB'].glsl_dvec4_type - glsl_dvec4_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_dvec4_type.argtypes = [] -except AttributeError: - pass -try: - glsl_uvec4_type = _libraries['FIXME_STUB'].glsl_uvec4_type - glsl_uvec4_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uvec4_type.argtypes = [] -except AttributeError: - pass -try: - glsl_ivec4_type = _libraries['FIXME_STUB'].glsl_ivec4_type - glsl_ivec4_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_ivec4_type.argtypes = [] -except AttributeError: - pass -try: - glsl_bvec4_type = _libraries['FIXME_STUB'].glsl_bvec4_type - glsl_bvec4_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bvec4_type.argtypes = [] -except AttributeError: - pass -try: - glsl_int_type = _libraries['FIXME_STUB'].glsl_int_type - glsl_int_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_int_type.argtypes = [] -except AttributeError: - pass -try: - glsl_uint_type = _libraries['FIXME_STUB'].glsl_uint_type - glsl_uint_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uint_type.argtypes = [] -except AttributeError: - pass -try: - glsl_int64_t_type = _libraries['FIXME_STUB'].glsl_int64_t_type - glsl_int64_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_int64_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_uint64_t_type = _libraries['FIXME_STUB'].glsl_uint64_t_type - glsl_uint64_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uint64_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_int16_t_type = _libraries['FIXME_STUB'].glsl_int16_t_type - glsl_int16_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_int16_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_uint16_t_type = _libraries['FIXME_STUB'].glsl_uint16_t_type - glsl_uint16_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uint16_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_int8_t_type = _libraries['FIXME_STUB'].glsl_int8_t_type - glsl_int8_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_int8_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_uint8_t_type = _libraries['FIXME_STUB'].glsl_uint8_t_type - glsl_uint8_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uint8_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_bool_type = _libraries['FIXME_STUB'].glsl_bool_type - glsl_bool_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bool_type.argtypes = [] -except AttributeError: - pass -try: - glsl_atomic_uint_type = _libraries['FIXME_STUB'].glsl_atomic_uint_type - glsl_atomic_uint_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_atomic_uint_type.argtypes = [] -except AttributeError: - pass -try: - glsl_bfloat16_t_type = _libraries['FIXME_STUB'].glsl_bfloat16_t_type - glsl_bfloat16_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bfloat16_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_e4m3fn_t_type = _libraries['FIXME_STUB'].glsl_e4m3fn_t_type - glsl_e4m3fn_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_e4m3fn_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_e5m2_t_type = _libraries['FIXME_STUB'].glsl_e5m2_t_type - glsl_e5m2_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_e5m2_t_type.argtypes = [] -except AttributeError: - pass -try: - glsl_floatN_t_type = _libraries['FIXME_STUB'].glsl_floatN_t_type - glsl_floatN_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_floatN_t_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_bfloatN_t_type = _libraries['FIXME_STUB'].glsl_bfloatN_t_type - glsl_bfloatN_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bfloatN_t_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_intN_t_type = _libraries['FIXME_STUB'].glsl_intN_t_type - glsl_intN_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_intN_t_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_uintN_t_type = _libraries['FIXME_STUB'].glsl_uintN_t_type - glsl_uintN_t_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uintN_t_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_vec_type = _libraries['libtinymesa_cpu.so'].glsl_vec_type - glsl_vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_f16vec_type = _libraries['libtinymesa_cpu.so'].glsl_f16vec_type - glsl_f16vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_f16vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_bf16vec_type = _libraries['libtinymesa_cpu.so'].glsl_bf16vec_type - glsl_bf16vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bf16vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_e4m3fnvec_type = _libraries['libtinymesa_cpu.so'].glsl_e4m3fnvec_type - glsl_e4m3fnvec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_e4m3fnvec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_e5m2vec_type = _libraries['libtinymesa_cpu.so'].glsl_e5m2vec_type - glsl_e5m2vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_e5m2vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_dvec_type = _libraries['libtinymesa_cpu.so'].glsl_dvec_type - glsl_dvec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_dvec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_ivec_type = _libraries['libtinymesa_cpu.so'].glsl_ivec_type - glsl_ivec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_ivec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_uvec_type = _libraries['libtinymesa_cpu.so'].glsl_uvec_type - glsl_uvec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uvec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_bvec_type = _libraries['libtinymesa_cpu.so'].glsl_bvec_type - glsl_bvec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bvec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_i64vec_type = _libraries['libtinymesa_cpu.so'].glsl_i64vec_type - glsl_i64vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_i64vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_u64vec_type = _libraries['libtinymesa_cpu.so'].glsl_u64vec_type - glsl_u64vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_u64vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_i16vec_type = _libraries['libtinymesa_cpu.so'].glsl_i16vec_type - glsl_i16vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_i16vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_u16vec_type = _libraries['libtinymesa_cpu.so'].glsl_u16vec_type - glsl_u16vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_u16vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_i8vec_type = _libraries['libtinymesa_cpu.so'].glsl_i8vec_type - glsl_i8vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_i8vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_u8vec_type = _libraries['libtinymesa_cpu.so'].glsl_u8vec_type - glsl_u8vec_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_u8vec_type.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_simple_explicit_type = _libraries['libtinymesa_cpu.so'].glsl_simple_explicit_type - glsl_simple_explicit_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_simple_explicit_type.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_simple_type = _libraries['FIXME_STUB'].glsl_simple_type - glsl_simple_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_simple_type.argtypes = [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_sampler_type = _libraries['libtinymesa_cpu.so'].glsl_sampler_type - glsl_sampler_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_sampler_type.argtypes = [glsl_sampler_dim, ctypes.c_bool, ctypes.c_bool, glsl_base_type] -except AttributeError: - pass -try: - glsl_bare_sampler_type = _libraries['libtinymesa_cpu.so'].glsl_bare_sampler_type - glsl_bare_sampler_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bare_sampler_type.argtypes = [] -except AttributeError: - pass -try: - glsl_bare_shadow_sampler_type = _libraries['libtinymesa_cpu.so'].glsl_bare_shadow_sampler_type - glsl_bare_shadow_sampler_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_bare_shadow_sampler_type.argtypes = [] -except AttributeError: - pass -try: - glsl_texture_type = _libraries['libtinymesa_cpu.so'].glsl_texture_type - glsl_texture_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_texture_type.argtypes = [glsl_sampler_dim, ctypes.c_bool, glsl_base_type] -except AttributeError: - pass -try: - glsl_image_type = _libraries['libtinymesa_cpu.so'].glsl_image_type - glsl_image_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_image_type.argtypes = [glsl_sampler_dim, ctypes.c_bool, glsl_base_type] -except AttributeError: - pass -try: - glsl_array_type = _libraries['libtinymesa_cpu.so'].glsl_array_type - glsl_array_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_array_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_cmat_type = _libraries['libtinymesa_cpu.so'].glsl_cmat_type - glsl_cmat_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_cmat_type.argtypes = [ctypes.POINTER(struct_glsl_cmat_description)] -except AttributeError: - pass -try: - glsl_struct_type_with_explicit_alignment = _libraries['libtinymesa_cpu.so'].glsl_struct_type_with_explicit_alignment - glsl_struct_type_with_explicit_alignment.restype = ctypes.POINTER(struct_glsl_type) - glsl_struct_type_with_explicit_alignment.argtypes = [ctypes.POINTER(struct_glsl_struct_field), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_bool, ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_struct_type = _libraries['FIXME_STUB'].glsl_struct_type - glsl_struct_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_struct_type.argtypes = [ctypes.POINTER(struct_glsl_struct_field), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_bool] -except AttributeError: - pass - -# values for enumeration 'glsl_interface_packing' -glsl_interface_packing__enumvalues = { - 0: 'GLSL_INTERFACE_PACKING_STD140', - 1: 'GLSL_INTERFACE_PACKING_SHARED', - 2: 'GLSL_INTERFACE_PACKING_PACKED', - 3: 'GLSL_INTERFACE_PACKING_STD430', -} -GLSL_INTERFACE_PACKING_STD140 = 0 -GLSL_INTERFACE_PACKING_SHARED = 1 -GLSL_INTERFACE_PACKING_PACKED = 2 -GLSL_INTERFACE_PACKING_STD430 = 3 -glsl_interface_packing = ctypes.c_uint32 # enum -try: - glsl_interface_type = _libraries['libtinymesa_cpu.so'].glsl_interface_type - glsl_interface_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_interface_type.argtypes = [ctypes.POINTER(struct_glsl_struct_field), ctypes.c_uint32, glsl_interface_packing, ctypes.c_bool, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - glsl_subroutine_type = _libraries['libtinymesa_cpu.so'].glsl_subroutine_type - glsl_subroutine_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_subroutine_type.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - glsl_get_row_type = _libraries['libtinymesa_cpu.so'].glsl_get_row_type - glsl_get_row_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_row_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_column_type = _libraries['libtinymesa_cpu.so'].glsl_get_column_type - glsl_get_column_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_column_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_explicit_type_for_size_align = _libraries['libtinymesa_cpu.so'].glsl_get_explicit_type_for_size_align - glsl_get_explicit_type_for_size_align.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_explicit_type_for_size_align.argtypes = [ctypes.POINTER(struct_glsl_type), glsl_type_size_align_func, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - glsl_type_replace_vec3_with_vec4 = _libraries['libtinymesa_cpu.so'].glsl_type_replace_vec3_with_vec4 - glsl_type_replace_vec3_with_vec4.restype = ctypes.POINTER(struct_glsl_type) - glsl_type_replace_vec3_with_vec4.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_float16_type = _libraries['libtinymesa_cpu.so'].glsl_float16_type - glsl_float16_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_float16_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_int16_type = _libraries['libtinymesa_cpu.so'].glsl_int16_type - glsl_int16_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_int16_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_uint16_type = _libraries['libtinymesa_cpu.so'].glsl_uint16_type - glsl_uint16_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_uint16_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_to_16bit = _libraries['libtinymesa_cpu.so'].glsl_type_to_16bit - glsl_type_to_16bit.restype = ctypes.POINTER(struct_glsl_type) - glsl_type_to_16bit.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_scalar_type = _libraries['FIXME_STUB'].glsl_scalar_type - glsl_scalar_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_scalar_type.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - glsl_vector_type = _libraries['FIXME_STUB'].glsl_vector_type - glsl_vector_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_vector_type.argtypes = [glsl_base_type, ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_matrix_type = _libraries['FIXME_STUB'].glsl_matrix_type - glsl_matrix_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_matrix_type.argtypes = [glsl_base_type, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_explicit_matrix_type = _libraries['FIXME_STUB'].glsl_explicit_matrix_type - glsl_explicit_matrix_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_explicit_matrix_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32, ctypes.c_bool] -except AttributeError: - pass -try: - glsl_transposed_type = _libraries['FIXME_STUB'].glsl_transposed_type - glsl_transposed_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_transposed_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_texture_type_to_sampler = _libraries['FIXME_STUB'].glsl_texture_type_to_sampler - glsl_texture_type_to_sampler.restype = ctypes.POINTER(struct_glsl_type) - glsl_texture_type_to_sampler.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_sampler_type_to_texture = _libraries['FIXME_STUB'].glsl_sampler_type_to_texture - glsl_sampler_type_to_texture.restype = ctypes.POINTER(struct_glsl_type) - glsl_sampler_type_to_texture.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_replace_vector_type = _libraries['libtinymesa_cpu.so'].glsl_replace_vector_type - glsl_replace_vector_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_replace_vector_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_channel_type = _libraries['libtinymesa_cpu.so'].glsl_channel_type - glsl_channel_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_channel_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_mul_type = _libraries['libtinymesa_cpu.so'].glsl_get_mul_type - glsl_get_mul_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_mul_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_get_sampler_count = _libraries['libtinymesa_cpu.so'].glsl_type_get_sampler_count - glsl_type_get_sampler_count.restype = ctypes.c_uint32 - glsl_type_get_sampler_count.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_get_texture_count = _libraries['libtinymesa_cpu.so'].glsl_type_get_texture_count - glsl_type_get_texture_count.restype = ctypes.c_uint32 - glsl_type_get_texture_count.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_get_image_count = _libraries['libtinymesa_cpu.so'].glsl_type_get_image_count - glsl_type_get_image_count.restype = ctypes.c_uint32 - glsl_type_get_image_count.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_count_vec4_slots = _libraries['libtinymesa_cpu.so'].glsl_count_vec4_slots - glsl_count_vec4_slots.restype = ctypes.c_uint32 - glsl_count_vec4_slots.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - glsl_count_dword_slots = _libraries['libtinymesa_cpu.so'].glsl_count_dword_slots - glsl_count_dword_slots.restype = ctypes.c_uint32 - glsl_count_dword_slots.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_component_slots = _libraries['libtinymesa_cpu.so'].glsl_get_component_slots - glsl_get_component_slots.restype = ctypes.c_uint32 - glsl_get_component_slots.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_component_slots_aligned = _libraries['libtinymesa_cpu.so'].glsl_get_component_slots_aligned - glsl_get_component_slots_aligned.restype = ctypes.c_uint32 - glsl_get_component_slots_aligned.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - glsl_varying_count = _libraries['libtinymesa_cpu.so'].glsl_varying_count - glsl_varying_count.restype = ctypes.c_uint32 - glsl_varying_count.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_type_uniform_locations = _libraries['libtinymesa_cpu.so'].glsl_type_uniform_locations - glsl_type_uniform_locations.restype = ctypes.c_uint32 - glsl_type_uniform_locations.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_count_attribute_slots = _libraries['FIXME_STUB'].glsl_count_attribute_slots - glsl_count_attribute_slots.restype = ctypes.c_uint32 - glsl_count_attribute_slots.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_cl_size = _libraries['libtinymesa_cpu.so'].glsl_get_cl_size - glsl_get_cl_size.restype = ctypes.c_uint32 - glsl_get_cl_size.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_cl_alignment = _libraries['libtinymesa_cpu.so'].glsl_get_cl_alignment - glsl_get_cl_alignment.restype = ctypes.c_uint32 - glsl_get_cl_alignment.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_cl_type_size_align = _libraries['libtinymesa_cpu.so'].glsl_get_cl_type_size_align - glsl_get_cl_type_size_align.restype = None - glsl_get_cl_type_size_align.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - glsl_get_internal_ifc_packing = _libraries['libtinymesa_cpu.so'].glsl_get_internal_ifc_packing - glsl_get_internal_ifc_packing.restype = glsl_interface_packing - glsl_get_internal_ifc_packing.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_ifc_packing = _libraries['FIXME_STUB'].glsl_get_ifc_packing - glsl_get_ifc_packing.restype = glsl_interface_packing - glsl_get_ifc_packing.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_std140_base_alignment = _libraries['libtinymesa_cpu.so'].glsl_get_std140_base_alignment - glsl_get_std140_base_alignment.restype = ctypes.c_uint32 - glsl_get_std140_base_alignment.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_std140_size = _libraries['libtinymesa_cpu.so'].glsl_get_std140_size - glsl_get_std140_size.restype = ctypes.c_uint32 - glsl_get_std140_size.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_std430_array_stride = _libraries['libtinymesa_cpu.so'].glsl_get_std430_array_stride - glsl_get_std430_array_stride.restype = ctypes.c_uint32 - glsl_get_std430_array_stride.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_std430_base_alignment = _libraries['libtinymesa_cpu.so'].glsl_get_std430_base_alignment - glsl_get_std430_base_alignment.restype = ctypes.c_uint32 - glsl_get_std430_base_alignment.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_std430_size = _libraries['libtinymesa_cpu.so'].glsl_get_std430_size - glsl_get_std430_size.restype = ctypes.c_uint32 - glsl_get_std430_size.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_explicit_size = _libraries['libtinymesa_cpu.so'].glsl_get_explicit_size - glsl_get_explicit_size.restype = ctypes.c_uint32 - glsl_get_explicit_size.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_explicit_stride = _libraries['FIXME_STUB'].glsl_get_explicit_stride - glsl_get_explicit_stride.restype = ctypes.c_uint32 - glsl_get_explicit_stride.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_explicit_alignment = _libraries['FIXME_STUB'].glsl_get_explicit_alignment - glsl_get_explicit_alignment.restype = ctypes.c_uint32 - glsl_get_explicit_alignment.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - glsl_get_explicit_std140_type = _libraries['libtinymesa_cpu.so'].glsl_get_explicit_std140_type - glsl_get_explicit_std140_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_explicit_std140_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_explicit_std430_type = _libraries['libtinymesa_cpu.so'].glsl_get_explicit_std430_type - glsl_get_explicit_std430_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_explicit_std430_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_get_explicit_interface_type = _libraries['FIXME_STUB'].glsl_get_explicit_interface_type - glsl_get_explicit_interface_type.restype = ctypes.POINTER(struct_glsl_type) - glsl_get_explicit_interface_type.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.c_bool] -except AttributeError: - pass -try: - glsl_size_align_handle_array_and_structs = _libraries['libtinymesa_cpu.so'].glsl_size_align_handle_array_and_structs - glsl_size_align_handle_array_and_structs.restype = None - glsl_size_align_handle_array_and_structs.argtypes = [ctypes.POINTER(struct_glsl_type), glsl_type_size_align_func, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - glsl_get_natural_size_align_bytes = _libraries['libtinymesa_cpu.so'].glsl_get_natural_size_align_bytes - glsl_get_natural_size_align_bytes.restype = None - glsl_get_natural_size_align_bytes.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - glsl_get_word_size_align_bytes = _libraries['libtinymesa_cpu.so'].glsl_get_word_size_align_bytes - glsl_get_word_size_align_bytes.restype = None - glsl_get_word_size_align_bytes.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - glsl_get_vec4_size_align_bytes = _libraries['libtinymesa_cpu.so'].glsl_get_vec4_size_align_bytes - glsl_get_vec4_size_align_bytes.restype = None - glsl_get_vec4_size_align_bytes.argtypes = [ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - ralloc_context = _libraries['libtinymesa_cpu.so'].ralloc_context - ralloc_context.restype = ctypes.POINTER(None) - ralloc_context.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - ralloc_size = _libraries['libtinymesa_cpu.so'].ralloc_size - ralloc_size.restype = ctypes.POINTER(None) - ralloc_size.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - rzalloc_size = _libraries['libtinymesa_cpu.so'].rzalloc_size - rzalloc_size.restype = ctypes.POINTER(None) - rzalloc_size.argtypes = [ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - reralloc_size = _libraries['libtinymesa_cpu.so'].reralloc_size - reralloc_size.restype = ctypes.POINTER(None) - reralloc_size.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - rerzalloc_size = _libraries['libtinymesa_cpu.so'].rerzalloc_size - rerzalloc_size.restype = ctypes.POINTER(None) - rerzalloc_size.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t] -except AttributeError: - pass -try: - ralloc_array_size = _libraries['libtinymesa_cpu.so'].ralloc_array_size - ralloc_array_size.restype = ctypes.POINTER(None) - ralloc_array_size.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - rzalloc_array_size = _libraries['libtinymesa_cpu.so'].rzalloc_array_size - rzalloc_array_size.restype = ctypes.POINTER(None) - rzalloc_array_size.argtypes = [ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - reralloc_array_size = _libraries['libtinymesa_cpu.so'].reralloc_array_size - reralloc_array_size.restype = ctypes.POINTER(None) - reralloc_array_size.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - rerzalloc_array_size = _libraries['libtinymesa_cpu.so'].rerzalloc_array_size - rerzalloc_array_size.restype = ctypes.POINTER(None) - rerzalloc_array_size.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - ralloc_free = _libraries['libtinymesa_cpu.so'].ralloc_free - ralloc_free.restype = None - ralloc_free.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - ralloc_steal = _libraries['libtinymesa_cpu.so'].ralloc_steal - ralloc_steal.restype = None - ralloc_steal.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None)] -except AttributeError: - pass -try: - ralloc_adopt = _libraries['libtinymesa_cpu.so'].ralloc_adopt - ralloc_adopt.restype = None - ralloc_adopt.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None)] -except AttributeError: - pass -try: - ralloc_parent = _libraries['libtinymesa_cpu.so'].ralloc_parent - ralloc_parent.restype = ctypes.POINTER(None) - ralloc_parent.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - ralloc_set_destructor = _libraries['libtinymesa_cpu.so'].ralloc_set_destructor - ralloc_set_destructor.restype = None - ralloc_set_destructor.argtypes = [ctypes.POINTER(None), ctypes.CFUNCTYPE(None, ctypes.POINTER(None))] -except AttributeError: - pass -try: - ralloc_memdup = _libraries['libtinymesa_cpu.so'].ralloc_memdup - ralloc_memdup.restype = ctypes.POINTER(None) - ralloc_memdup.argtypes = [ctypes.POINTER(None), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - ralloc_strdup = _libraries['libtinymesa_cpu.so'].ralloc_strdup - ralloc_strdup.restype = ctypes.POINTER(ctypes.c_char) - ralloc_strdup.argtypes = [ctypes.POINTER(None), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - ralloc_strndup = _libraries['libtinymesa_cpu.so'].ralloc_strndup - ralloc_strndup.restype = ctypes.POINTER(ctypes.c_char) - ralloc_strndup.argtypes = [ctypes.POINTER(None), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - ralloc_strcat = _libraries['libtinymesa_cpu.so'].ralloc_strcat - ralloc_strcat.restype = ctypes.c_bool - ralloc_strcat.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - ralloc_strncat = _libraries['libtinymesa_cpu.so'].ralloc_strncat - ralloc_strncat.restype = ctypes.c_bool - ralloc_strncat.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), size_t] -except AttributeError: - pass -try: - ralloc_str_append = _libraries['libtinymesa_cpu.so'].ralloc_str_append - ralloc_str_append.restype = ctypes.c_bool - ralloc_str_append.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), size_t, size_t] -except AttributeError: - pass -try: - ralloc_asprintf = _libraries['libtinymesa_cpu.so'].ralloc_asprintf - ralloc_asprintf.restype = ctypes.POINTER(ctypes.c_char) - ralloc_asprintf.argtypes = [ctypes.POINTER(None), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct___va_list_tag(Structure): - pass - -struct___va_list_tag._pack_ = 1 # source:False -struct___va_list_tag._fields_ = [ - ('gp_offset', ctypes.c_uint32), - ('fp_offset', ctypes.c_uint32), - ('overflow_arg_area', ctypes.POINTER(None)), - ('reg_save_area', ctypes.POINTER(None)), -] - -va_list = struct___va_list_tag * 1 -try: - ralloc_vasprintf = _libraries['libtinymesa_cpu.so'].ralloc_vasprintf - ralloc_vasprintf.restype = ctypes.POINTER(ctypes.c_char) - ralloc_vasprintf.argtypes = [ctypes.POINTER(None), ctypes.POINTER(ctypes.c_char), va_list] -except AttributeError: - pass -try: - ralloc_asprintf_rewrite_tail = _libraries['libtinymesa_cpu.so'].ralloc_asprintf_rewrite_tail - ralloc_asprintf_rewrite_tail.restype = ctypes.c_bool - ralloc_asprintf_rewrite_tail.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - ralloc_vasprintf_rewrite_tail = _libraries['libtinymesa_cpu.so'].ralloc_vasprintf_rewrite_tail - ralloc_vasprintf_rewrite_tail.restype = ctypes.c_bool - ralloc_vasprintf_rewrite_tail.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), va_list] -except AttributeError: - pass -try: - ralloc_asprintf_append = _libraries['libtinymesa_cpu.so'].ralloc_asprintf_append - ralloc_asprintf_append.restype = ctypes.c_bool - ralloc_asprintf_append.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - ralloc_vasprintf_append = _libraries['libtinymesa_cpu.so'].ralloc_vasprintf_append - ralloc_vasprintf_append.restype = ctypes.c_bool - ralloc_vasprintf_append.argtypes = [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), va_list] -except AttributeError: - pass -try: - ralloc_total_size = _libraries['libtinymesa_cpu.so'].ralloc_total_size - ralloc_total_size.restype = size_t - ralloc_total_size.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -class struct_gc_ctx(Structure): - pass - -gc_ctx = struct_gc_ctx -try: - gc_context = _libraries['libtinymesa_cpu.so'].gc_context - gc_context.restype = ctypes.POINTER(struct_gc_ctx) - gc_context.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - gc_alloc_size = _libraries['libtinymesa_cpu.so'].gc_alloc_size - gc_alloc_size.restype = ctypes.POINTER(None) - gc_alloc_size.argtypes = [ctypes.POINTER(struct_gc_ctx), size_t, size_t] -except AttributeError: - pass -try: - gc_zalloc_size = _libraries['libtinymesa_cpu.so'].gc_zalloc_size - gc_zalloc_size.restype = ctypes.POINTER(None) - gc_zalloc_size.argtypes = [ctypes.POINTER(struct_gc_ctx), size_t, size_t] -except AttributeError: - pass -try: - gc_free = _libraries['libtinymesa_cpu.so'].gc_free - gc_free.restype = None - gc_free.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - gc_get_context = _libraries['libtinymesa_cpu.so'].gc_get_context - gc_get_context.restype = ctypes.POINTER(struct_gc_ctx) - gc_get_context.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - gc_sweep_start = _libraries['libtinymesa_cpu.so'].gc_sweep_start - gc_sweep_start.restype = None - gc_sweep_start.argtypes = [ctypes.POINTER(struct_gc_ctx)] -except AttributeError: - pass -try: - gc_mark_live = _libraries['libtinymesa_cpu.so'].gc_mark_live - gc_mark_live.restype = None - gc_mark_live.argtypes = [ctypes.POINTER(struct_gc_ctx), ctypes.POINTER(None)] -except AttributeError: - pass -try: - gc_sweep_end = _libraries['libtinymesa_cpu.so'].gc_sweep_end - gc_sweep_end.restype = None - gc_sweep_end.argtypes = [ctypes.POINTER(struct_gc_ctx)] -except AttributeError: - pass -class struct_linear_ctx(Structure): - pass - -linear_ctx = struct_linear_ctx -try: - linear_alloc_child = _libraries['libtinymesa_cpu.so'].linear_alloc_child - linear_alloc_child.restype = ctypes.POINTER(None) - linear_alloc_child.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.c_uint32] -except AttributeError: - pass -class struct_c__SA_linear_opts(Structure): - pass - -struct_c__SA_linear_opts._pack_ = 1 # source:False -struct_c__SA_linear_opts._fields_ = [ - ('min_buffer_size', ctypes.c_uint32), -] - -linear_opts = struct_c__SA_linear_opts -try: - linear_context = _libraries['libtinymesa_cpu.so'].linear_context - linear_context.restype = ctypes.POINTER(struct_linear_ctx) - linear_context.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - linear_context_with_opts = _libraries['libtinymesa_cpu.so'].linear_context_with_opts - linear_context_with_opts.restype = ctypes.POINTER(struct_linear_ctx) - linear_context_with_opts.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_c__SA_linear_opts)] -except AttributeError: - pass -try: - linear_zalloc_child = _libraries['libtinymesa_cpu.so'].linear_zalloc_child - linear_zalloc_child.restype = ctypes.POINTER(None) - linear_zalloc_child.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.c_uint32] -except AttributeError: - pass -try: - linear_free_context = _libraries['libtinymesa_cpu.so'].linear_free_context - linear_free_context.restype = None - linear_free_context.argtypes = [ctypes.POINTER(struct_linear_ctx)] -except AttributeError: - pass -try: - ralloc_steal_linear_context = _libraries['libtinymesa_cpu.so'].ralloc_steal_linear_context - ralloc_steal_linear_context.restype = None - ralloc_steal_linear_context.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_linear_ctx)] -except AttributeError: - pass -try: - ralloc_parent_of_linear_context = _libraries['libtinymesa_cpu.so'].ralloc_parent_of_linear_context - ralloc_parent_of_linear_context.restype = ctypes.POINTER(None) - ralloc_parent_of_linear_context.argtypes = [ctypes.POINTER(struct_linear_ctx)] -except AttributeError: - pass -try: - linear_alloc_child_array = _libraries['libtinymesa_cpu.so'].linear_alloc_child_array - linear_alloc_child_array.restype = ctypes.POINTER(None) - linear_alloc_child_array.argtypes = [ctypes.POINTER(struct_linear_ctx), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - linear_zalloc_child_array = _libraries['libtinymesa_cpu.so'].linear_zalloc_child_array - linear_zalloc_child_array.restype = ctypes.POINTER(None) - linear_zalloc_child_array.argtypes = [ctypes.POINTER(struct_linear_ctx), size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - linear_strdup = _libraries['libtinymesa_cpu.so'].linear_strdup - linear_strdup.restype = ctypes.POINTER(ctypes.c_char) - linear_strdup.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - linear_asprintf = _libraries['libtinymesa_cpu.so'].linear_asprintf - linear_asprintf.restype = ctypes.POINTER(ctypes.c_char) - linear_asprintf.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - linear_vasprintf = _libraries['libtinymesa_cpu.so'].linear_vasprintf - linear_vasprintf.restype = ctypes.POINTER(ctypes.c_char) - linear_vasprintf.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.c_char), va_list] -except AttributeError: - pass -try: - linear_asprintf_append = _libraries['libtinymesa_cpu.so'].linear_asprintf_append - linear_asprintf_append.restype = ctypes.c_bool - linear_asprintf_append.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - linear_vasprintf_append = _libraries['libtinymesa_cpu.so'].linear_vasprintf_append - linear_vasprintf_append.restype = ctypes.c_bool - linear_vasprintf_append.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), va_list] -except AttributeError: - pass -try: - linear_asprintf_rewrite_tail = _libraries['libtinymesa_cpu.so'].linear_asprintf_rewrite_tail - linear_asprintf_rewrite_tail.restype = ctypes.c_bool - linear_asprintf_rewrite_tail.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - linear_vasprintf_rewrite_tail = _libraries['libtinymesa_cpu.so'].linear_vasprintf_rewrite_tail - linear_vasprintf_rewrite_tail.restype = ctypes.c_bool - linear_vasprintf_rewrite_tail.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), va_list] -except AttributeError: - pass -try: - linear_strcat = _libraries['libtinymesa_cpu.so'].linear_strcat - linear_strcat.restype = ctypes.c_bool - linear_strcat.argtypes = [ctypes.POINTER(struct_linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass - -# values for enumeration 'c__Ea_RALLOC_PRINT_INFO_SUMMARY_ONLY' -c__Ea_RALLOC_PRINT_INFO_SUMMARY_ONLY__enumvalues = { - 1: 'RALLOC_PRINT_INFO_SUMMARY_ONLY', -} -RALLOC_PRINT_INFO_SUMMARY_ONLY = 1 -c__Ea_RALLOC_PRINT_INFO_SUMMARY_ONLY = ctypes.c_uint32 # enum -class struct__IO_FILE(Structure): - pass - -class struct__IO_marker(Structure): - pass - -class struct__IO_codecvt(Structure): - pass - -class struct__IO_wide_data(Structure): - pass - -struct__IO_FILE._pack_ = 1 # source:False -struct__IO_FILE._fields_ = [ - ('_flags', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_IO_read_ptr', ctypes.POINTER(ctypes.c_char)), - ('_IO_read_end', ctypes.POINTER(ctypes.c_char)), - ('_IO_read_base', ctypes.POINTER(ctypes.c_char)), - ('_IO_write_base', ctypes.POINTER(ctypes.c_char)), - ('_IO_write_ptr', ctypes.POINTER(ctypes.c_char)), - ('_IO_write_end', ctypes.POINTER(ctypes.c_char)), - ('_IO_buf_base', ctypes.POINTER(ctypes.c_char)), - ('_IO_buf_end', ctypes.POINTER(ctypes.c_char)), - ('_IO_save_base', ctypes.POINTER(ctypes.c_char)), - ('_IO_backup_base', ctypes.POINTER(ctypes.c_char)), - ('_IO_save_end', ctypes.POINTER(ctypes.c_char)), - ('_markers', ctypes.POINTER(struct__IO_marker)), - ('_chain', ctypes.POINTER(struct__IO_FILE)), - ('_fileno', ctypes.c_int32), - ('_flags2', ctypes.c_int32), - ('_old_offset', ctypes.c_int64), - ('_cur_column', ctypes.c_uint16), - ('_vtable_offset', ctypes.c_byte), - ('_shortbuf', ctypes.c_char * 1), - ('PADDING_1', ctypes.c_ubyte * 4), - ('_lock', ctypes.POINTER(None)), - ('_offset', ctypes.c_int64), - ('_codecvt', ctypes.POINTER(struct__IO_codecvt)), - ('_wide_data', ctypes.POINTER(struct__IO_wide_data)), - ('_freeres_list', ctypes.POINTER(struct__IO_FILE)), - ('_freeres_buf', ctypes.POINTER(None)), - ('__pad5', ctypes.c_uint64), - ('_mode', ctypes.c_int32), - ('_unused2', ctypes.c_char * 20), -] - -try: - ralloc_print_info = _libraries['libtinymesa_cpu.so'].ralloc_print_info - ralloc_print_info.restype = None - ralloc_print_info.argtypes = [ctypes.POINTER(struct__IO_FILE), ctypes.POINTER(None), ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_lower_int64_options' -c__EA_nir_lower_int64_options__enumvalues = { - 1: 'nir_lower_imul64', - 2: 'nir_lower_isign64', - 4: 'nir_lower_divmod64', - 8: 'nir_lower_imul_high64', - 16: 'nir_lower_bcsel64', - 32: 'nir_lower_icmp64', - 64: 'nir_lower_iadd64', - 128: 'nir_lower_iabs64', - 256: 'nir_lower_ineg64', - 512: 'nir_lower_logic64', - 1024: 'nir_lower_minmax64', - 2048: 'nir_lower_shift64', - 4096: 'nir_lower_imul_2x32_64', - 8192: 'nir_lower_extract64', - 16384: 'nir_lower_ufind_msb64', - 32768: 'nir_lower_bit_count64', - 65536: 'nir_lower_subgroup_shuffle64', - 131072: 'nir_lower_scan_reduce_bitwise64', - 262144: 'nir_lower_scan_reduce_iadd64', - 524288: 'nir_lower_vote_ieq64', - 1048576: 'nir_lower_usub_sat64', - 2097152: 'nir_lower_iadd_sat64', - 4194304: 'nir_lower_find_lsb64', - 8388608: 'nir_lower_conv64', - 16777216: 'nir_lower_uadd_sat64', - 33554432: 'nir_lower_iadd3_64', - 67108864: 'nir_lower_bitfield_reverse64', - 134217728: 'nir_lower_bitfield_extract64', -} -nir_lower_imul64 = 1 -nir_lower_isign64 = 2 -nir_lower_divmod64 = 4 -nir_lower_imul_high64 = 8 -nir_lower_bcsel64 = 16 -nir_lower_icmp64 = 32 -nir_lower_iadd64 = 64 -nir_lower_iabs64 = 128 -nir_lower_ineg64 = 256 -nir_lower_logic64 = 512 -nir_lower_minmax64 = 1024 -nir_lower_shift64 = 2048 -nir_lower_imul_2x32_64 = 4096 -nir_lower_extract64 = 8192 -nir_lower_ufind_msb64 = 16384 -nir_lower_bit_count64 = 32768 -nir_lower_subgroup_shuffle64 = 65536 -nir_lower_scan_reduce_bitwise64 = 131072 -nir_lower_scan_reduce_iadd64 = 262144 -nir_lower_vote_ieq64 = 524288 -nir_lower_usub_sat64 = 1048576 -nir_lower_iadd_sat64 = 2097152 -nir_lower_find_lsb64 = 4194304 -nir_lower_conv64 = 8388608 -nir_lower_uadd_sat64 = 16777216 -nir_lower_iadd3_64 = 33554432 -nir_lower_bitfield_reverse64 = 67108864 -nir_lower_bitfield_extract64 = 134217728 -c__EA_nir_lower_int64_options = ctypes.c_uint32 # enum -nir_lower_int64_options = c__EA_nir_lower_int64_options -nir_lower_int64_options__enumvalues = c__EA_nir_lower_int64_options__enumvalues - -# values for enumeration 'c__EA_nir_lower_doubles_options' -c__EA_nir_lower_doubles_options__enumvalues = { - 1: 'nir_lower_drcp', - 2: 'nir_lower_dsqrt', - 4: 'nir_lower_drsq', - 8: 'nir_lower_dtrunc', - 16: 'nir_lower_dfloor', - 32: 'nir_lower_dceil', - 64: 'nir_lower_dfract', - 128: 'nir_lower_dround_even', - 256: 'nir_lower_dmod', - 512: 'nir_lower_dsub', - 1024: 'nir_lower_ddiv', - 2048: 'nir_lower_dsign', - 4096: 'nir_lower_dminmax', - 8192: 'nir_lower_dsat', - 16384: 'nir_lower_fp64_full_software', -} -nir_lower_drcp = 1 -nir_lower_dsqrt = 2 -nir_lower_drsq = 4 -nir_lower_dtrunc = 8 -nir_lower_dfloor = 16 -nir_lower_dceil = 32 -nir_lower_dfract = 64 -nir_lower_dround_even = 128 -nir_lower_dmod = 256 -nir_lower_dsub = 512 -nir_lower_ddiv = 1024 -nir_lower_dsign = 2048 -nir_lower_dminmax = 4096 -nir_lower_dsat = 8192 -nir_lower_fp64_full_software = 16384 -c__EA_nir_lower_doubles_options = ctypes.c_uint32 # enum -nir_lower_doubles_options = c__EA_nir_lower_doubles_options -nir_lower_doubles_options__enumvalues = c__EA_nir_lower_doubles_options__enumvalues - -# values for enumeration 'c__EA_nir_divergence_options' -c__EA_nir_divergence_options__enumvalues = { - 1: 'nir_divergence_single_prim_per_subgroup', - 2: 'nir_divergence_single_patch_per_tcs_subgroup', - 4: 'nir_divergence_single_patch_per_tes_subgroup', - 8: 'nir_divergence_view_index_uniform', - 16: 'nir_divergence_single_frag_shading_rate_per_subgroup', - 32: 'nir_divergence_multiple_workgroup_per_compute_subgroup', - 64: 'nir_divergence_shader_record_ptr_uniform', - 128: 'nir_divergence_uniform_load_tears', - 256: 'nir_divergence_ignore_undef_if_phi_srcs', -} -nir_divergence_single_prim_per_subgroup = 1 -nir_divergence_single_patch_per_tcs_subgroup = 2 -nir_divergence_single_patch_per_tes_subgroup = 4 -nir_divergence_view_index_uniform = 8 -nir_divergence_single_frag_shading_rate_per_subgroup = 16 -nir_divergence_multiple_workgroup_per_compute_subgroup = 32 -nir_divergence_shader_record_ptr_uniform = 64 -nir_divergence_uniform_load_tears = 128 -nir_divergence_ignore_undef_if_phi_srcs = 256 -c__EA_nir_divergence_options = ctypes.c_uint32 # enum -nir_divergence_options = c__EA_nir_divergence_options -nir_divergence_options__enumvalues = c__EA_nir_divergence_options__enumvalues -class struct_nir_instr(Structure): - pass - -class struct_nir_block(Structure): - pass - -class struct_exec_node(Structure): - pass - -struct_exec_node._pack_ = 1 # source:False -struct_exec_node._fields_ = [ - ('next', ctypes.POINTER(struct_exec_node)), - ('prev', ctypes.POINTER(struct_exec_node)), -] - -struct_nir_instr._pack_ = 1 # source:False -struct_nir_instr._fields_ = [ - ('node', struct_exec_node), - ('block', ctypes.POINTER(struct_nir_block)), - ('type', ctypes.c_ubyte), - ('pass_flags', ctypes.c_ubyte), - ('has_debug_info', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), - ('index', ctypes.c_uint32), -] - -class struct_set(Structure): - pass - -class struct_nir_cf_node(Structure): - pass - - -# values for enumeration 'c__EA_nir_cf_node_type' -c__EA_nir_cf_node_type__enumvalues = { - 0: 'nir_cf_node_block', - 1: 'nir_cf_node_if', - 2: 'nir_cf_node_loop', - 3: 'nir_cf_node_function', -} -nir_cf_node_block = 0 -nir_cf_node_if = 1 -nir_cf_node_loop = 2 -nir_cf_node_function = 3 -c__EA_nir_cf_node_type = ctypes.c_uint32 # enum -struct_nir_cf_node._pack_ = 1 # source:False -struct_nir_cf_node._fields_ = [ - ('node', struct_exec_node), - ('type', c__EA_nir_cf_node_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('parent', ctypes.POINTER(struct_nir_cf_node)), -] - -class struct_exec_list(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('head_sentinel', struct_exec_node), - ('tail_sentinel', struct_exec_node), - ] - -struct_nir_block._pack_ = 1 # source:False -struct_nir_block._fields_ = [ - ('cf_node', struct_nir_cf_node), - ('instr_list', struct_exec_list), - ('index', ctypes.c_uint32), - ('divergent', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('successors', ctypes.POINTER(struct_nir_block) * 2), - ('predecessors', ctypes.POINTER(struct_set)), - ('imm_dom', ctypes.POINTER(struct_nir_block)), - ('num_dom_children', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('dom_children', ctypes.POINTER(ctypes.POINTER(struct_nir_block))), - ('dom_frontier', ctypes.POINTER(struct_set)), - ('dom_pre_index', ctypes.c_uint32), - ('dom_post_index', ctypes.c_uint32), - ('start_ip', ctypes.c_uint32), - ('end_ip', ctypes.c_uint32), - ('live_in', ctypes.POINTER(ctypes.c_uint32)), - ('live_out', ctypes.POINTER(ctypes.c_uint32)), -] - -class struct_set_entry(Structure): - pass - -struct_set._pack_ = 1 # source:False -struct_set._fields_ = [ - ('mem_ctx', ctypes.POINTER(None)), - ('table', ctypes.POINTER(struct_set_entry)), - ('key_hash_function', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(None))), - ('key_equals_function', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(None), ctypes.POINTER(None))), - ('size', ctypes.c_uint32), - ('rehash', ctypes.c_uint32), - ('size_magic', ctypes.c_uint64), - ('rehash_magic', ctypes.c_uint64), - ('max_entries', ctypes.c_uint32), - ('size_index', ctypes.c_uint32), - ('entries', ctypes.c_uint32), - ('deleted_entries', ctypes.c_uint32), -] - -struct_set_entry._pack_ = 1 # source:False -struct_set_entry._fields_ = [ - ('hash', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('key', ctypes.POINTER(None)), -] - -nir_instr_filter_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)) - -# values for enumeration 'c__EA_nir_io_options' -c__EA_nir_io_options__enumvalues = { - 1: 'nir_io_has_flexible_input_interpolation_except_flat', - 2: 'nir_io_dont_use_pos_for_non_fs_varyings', - 4: 'nir_io_16bit_input_output_support', - 8: 'nir_io_mediump_is_32bit', - 16: 'nir_io_prefer_scalar_fs_inputs', - 32: 'nir_io_mix_convergent_flat_with_interpolated', - 64: 'nir_io_vectorizer_ignores_types', - 128: 'nir_io_always_interpolate_convergent_fs_inputs', - 256: 'nir_io_compaction_rotates_color_channels', - 512: 'nir_io_compaction_groups_tes_inputs_into_pos_and_var_groups', - 1024: 'nir_io_radv_intrinsic_component_workaround', - 65536: 'nir_io_has_intrinsics', - 131072: 'nir_io_separate_clip_cull_distance_arrays', -} -nir_io_has_flexible_input_interpolation_except_flat = 1 -nir_io_dont_use_pos_for_non_fs_varyings = 2 -nir_io_16bit_input_output_support = 4 -nir_io_mediump_is_32bit = 8 -nir_io_prefer_scalar_fs_inputs = 16 -nir_io_mix_convergent_flat_with_interpolated = 32 -nir_io_vectorizer_ignores_types = 64 -nir_io_always_interpolate_convergent_fs_inputs = 128 -nir_io_compaction_rotates_color_channels = 256 -nir_io_compaction_groups_tes_inputs_into_pos_and_var_groups = 512 -nir_io_radv_intrinsic_component_workaround = 1024 -nir_io_has_intrinsics = 65536 -nir_io_separate_clip_cull_distance_arrays = 131072 -c__EA_nir_io_options = ctypes.c_uint32 # enum -nir_io_options = c__EA_nir_io_options -nir_io_options__enumvalues = c__EA_nir_io_options__enumvalues - -# values for enumeration 'c__EA_nir_lower_packing_op' -c__EA_nir_lower_packing_op__enumvalues = { - 0: 'nir_lower_packing_op_pack_64_2x32', - 1: 'nir_lower_packing_op_unpack_64_2x32', - 2: 'nir_lower_packing_op_pack_64_4x16', - 3: 'nir_lower_packing_op_unpack_64_4x16', - 4: 'nir_lower_packing_op_pack_32_2x16', - 5: 'nir_lower_packing_op_unpack_32_2x16', - 6: 'nir_lower_packing_op_pack_32_4x8', - 7: 'nir_lower_packing_op_unpack_32_4x8', - 8: 'nir_lower_packing_num_ops', -} -nir_lower_packing_op_pack_64_2x32 = 0 -nir_lower_packing_op_unpack_64_2x32 = 1 -nir_lower_packing_op_pack_64_4x16 = 2 -nir_lower_packing_op_unpack_64_4x16 = 3 -nir_lower_packing_op_pack_32_2x16 = 4 -nir_lower_packing_op_unpack_32_2x16 = 5 -nir_lower_packing_op_pack_32_4x8 = 6 -nir_lower_packing_op_unpack_32_4x8 = 7 -nir_lower_packing_num_ops = 8 -c__EA_nir_lower_packing_op = ctypes.c_uint32 # enum -nir_lower_packing_op = c__EA_nir_lower_packing_op -nir_lower_packing_op__enumvalues = c__EA_nir_lower_packing_op__enumvalues -class struct_nir_shader_compiler_options(Structure): - pass - - -# values for enumeration 'c__EA_nir_variable_mode' -c__EA_nir_variable_mode__enumvalues = { - 1: 'nir_var_system_value', - 2: 'nir_var_uniform', - 4: 'nir_var_shader_in', - 8: 'nir_var_shader_out', - 16: 'nir_var_image', - 32: 'nir_var_shader_call_data', - 64: 'nir_var_ray_hit_attrib', - 128: 'nir_var_mem_ubo', - 256: 'nir_var_mem_push_const', - 512: 'nir_var_mem_ssbo', - 1024: 'nir_var_mem_constant', - 2048: 'nir_var_mem_task_payload', - 4096: 'nir_var_mem_node_payload', - 8192: 'nir_var_mem_node_payload_in', - 16384: 'nir_var_function_in', - 32768: 'nir_var_function_out', - 65536: 'nir_var_function_inout', - 131072: 'nir_var_shader_temp', - 262144: 'nir_var_function_temp', - 524288: 'nir_var_mem_shared', - 1048576: 'nir_var_mem_global', - 1966080: 'nir_var_mem_generic', - 1159: 'nir_var_read_only_modes', - 1969033: 'nir_var_vec_indexable_modes', - 21: 'nir_num_variable_modes', - 2097151: 'nir_var_all', -} -nir_var_system_value = 1 -nir_var_uniform = 2 -nir_var_shader_in = 4 -nir_var_shader_out = 8 -nir_var_image = 16 -nir_var_shader_call_data = 32 -nir_var_ray_hit_attrib = 64 -nir_var_mem_ubo = 128 -nir_var_mem_push_const = 256 -nir_var_mem_ssbo = 512 -nir_var_mem_constant = 1024 -nir_var_mem_task_payload = 2048 -nir_var_mem_node_payload = 4096 -nir_var_mem_node_payload_in = 8192 -nir_var_function_in = 16384 -nir_var_function_out = 32768 -nir_var_function_inout = 65536 -nir_var_shader_temp = 131072 -nir_var_function_temp = 262144 -nir_var_mem_shared = 524288 -nir_var_mem_global = 1048576 -nir_var_mem_generic = 1966080 -nir_var_read_only_modes = 1159 -nir_var_vec_indexable_modes = 1969033 -nir_num_variable_modes = 21 -nir_var_all = 2097151 -c__EA_nir_variable_mode = ctypes.c_uint32 # enum -class struct_nir_shader(Structure): - pass - -struct_nir_shader_compiler_options._pack_ = 1 # source:False -struct_nir_shader_compiler_options._fields_ = [ - ('lower_fdiv', ctypes.c_bool), - ('lower_ffma16', ctypes.c_bool), - ('lower_ffma32', ctypes.c_bool), - ('lower_ffma64', ctypes.c_bool), - ('fuse_ffma16', ctypes.c_bool), - ('fuse_ffma32', ctypes.c_bool), - ('fuse_ffma64', ctypes.c_bool), - ('lower_flrp16', ctypes.c_bool), - ('lower_flrp32', ctypes.c_bool), - ('lower_flrp64', ctypes.c_bool), - ('lower_fpow', ctypes.c_bool), - ('lower_fsat', ctypes.c_bool), - ('lower_fsqrt', ctypes.c_bool), - ('lower_sincos', ctypes.c_bool), - ('lower_fmod', ctypes.c_bool), - ('lower_bitfield_extract8', ctypes.c_bool), - ('lower_bitfield_extract16', ctypes.c_bool), - ('lower_bitfield_extract', ctypes.c_bool), - ('lower_bitfield_insert', ctypes.c_bool), - ('lower_bitfield_reverse', ctypes.c_bool), - ('lower_bit_count', ctypes.c_bool), - ('lower_ifind_msb', ctypes.c_bool), - ('lower_ufind_msb', ctypes.c_bool), - ('lower_find_lsb', ctypes.c_bool), - ('lower_uadd_carry', ctypes.c_bool), - ('lower_usub_borrow', ctypes.c_bool), - ('lower_mul_high', ctypes.c_bool), - ('lower_mul_high16', ctypes.c_bool), - ('lower_fneg', ctypes.c_bool), - ('lower_ineg', ctypes.c_bool), - ('lower_fisnormal', ctypes.c_bool), - ('lower_scmp', ctypes.c_bool), - ('lower_vector_cmp', ctypes.c_bool), - ('lower_bitops', ctypes.c_bool), - ('lower_isign', ctypes.c_bool), - ('lower_fsign', ctypes.c_bool), - ('lower_iabs', ctypes.c_bool), - ('lower_umax', ctypes.c_bool), - ('lower_umin', ctypes.c_bool), - ('lower_fminmax_signed_zero', ctypes.c_bool), - ('lower_fdph', ctypes.c_bool), - ('fdot_replicates', ctypes.c_bool), - ('lower_ffloor', ctypes.c_bool), - ('lower_ffract', ctypes.c_bool), - ('lower_fceil', ctypes.c_bool), - ('lower_ftrunc', ctypes.c_bool), - ('lower_fround_even', ctypes.c_bool), - ('lower_ldexp', ctypes.c_bool), - ('lower_pack_half_2x16', ctypes.c_bool), - ('lower_pack_unorm_2x16', ctypes.c_bool), - ('lower_pack_snorm_2x16', ctypes.c_bool), - ('lower_pack_unorm_4x8', ctypes.c_bool), - ('lower_pack_snorm_4x8', ctypes.c_bool), - ('lower_pack_64_2x32', ctypes.c_bool), - ('lower_pack_64_4x16', ctypes.c_bool), - ('lower_pack_32_2x16', ctypes.c_bool), - ('lower_pack_64_2x32_split', ctypes.c_bool), - ('lower_pack_32_2x16_split', ctypes.c_bool), - ('lower_unpack_half_2x16', ctypes.c_bool), - ('lower_unpack_unorm_2x16', ctypes.c_bool), - ('lower_unpack_snorm_2x16', ctypes.c_bool), - ('lower_unpack_unorm_4x8', ctypes.c_bool), - ('lower_unpack_snorm_4x8', ctypes.c_bool), - ('lower_unpack_64_2x32_split', ctypes.c_bool), - ('lower_unpack_32_2x16_split', ctypes.c_bool), - ('lower_pack_split', ctypes.c_bool), - ('lower_extract_byte', ctypes.c_bool), - ('lower_extract_word', ctypes.c_bool), - ('lower_insert_byte', ctypes.c_bool), - ('lower_insert_word', ctypes.c_bool), - ('vertex_id_zero_based', ctypes.c_bool), - ('lower_base_vertex', ctypes.c_bool), - ('instance_id_includes_base_index', ctypes.c_bool), - ('lower_helper_invocation', ctypes.c_bool), - ('optimize_sample_mask_in', ctypes.c_bool), - ('optimize_load_front_face_fsign', ctypes.c_bool), - ('optimize_quad_vote_to_reduce', ctypes.c_bool), - ('lower_cs_local_index_to_id', ctypes.c_bool), - ('lower_cs_local_id_to_index', ctypes.c_bool), - ('has_cs_global_id', ctypes.c_bool), - ('lower_device_index_to_zero', ctypes.c_bool), - ('lower_wpos_pntc', ctypes.c_bool), - ('lower_hadd', ctypes.c_bool), - ('lower_hadd64', ctypes.c_bool), - ('lower_uadd_sat', ctypes.c_bool), - ('lower_usub_sat', ctypes.c_bool), - ('lower_iadd_sat', ctypes.c_bool), - ('lower_mul_32x16', ctypes.c_bool), - ('lower_bfloat16_conversions', ctypes.c_bool), - ('vectorize_tess_levels', ctypes.c_bool), - ('lower_to_scalar', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 5), - ('lower_to_scalar_filter', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('vectorize_vec2_16bit', ctypes.c_bool), - ('unify_interfaces', ctypes.c_bool), - ('lower_interpolate_at', ctypes.c_bool), - ('lower_mul_2x32_64', ctypes.c_bool), - ('has_rotate8', ctypes.c_bool), - ('has_rotate16', ctypes.c_bool), - ('has_rotate32', ctypes.c_bool), - ('has_shfr32', ctypes.c_bool), - ('has_iadd3', ctypes.c_bool), - ('has_amul', ctypes.c_bool), - ('has_imul24', ctypes.c_bool), - ('has_umul24', ctypes.c_bool), - ('has_mul24_relaxed', ctypes.c_bool), - ('has_imad32', ctypes.c_bool), - ('has_umad24', ctypes.c_bool), - ('has_fused_comp_and_csel', ctypes.c_bool), - ('has_icsel_eqz64', ctypes.c_bool), - ('has_icsel_eqz32', ctypes.c_bool), - ('has_icsel_eqz16', ctypes.c_bool), - ('has_fneo_fcmpu', ctypes.c_bool), - ('has_ford_funord', ctypes.c_bool), - ('has_fsub', ctypes.c_bool), - ('has_isub', ctypes.c_bool), - ('has_pack_32_4x8', ctypes.c_bool), - ('has_texture_scaling', ctypes.c_bool), - ('has_sdot_4x8', ctypes.c_bool), - ('has_udot_4x8', ctypes.c_bool), - ('has_sudot_4x8', ctypes.c_bool), - ('has_sdot_4x8_sat', ctypes.c_bool), - ('has_udot_4x8_sat', ctypes.c_bool), - ('has_sudot_4x8_sat', ctypes.c_bool), - ('has_dot_2x16', ctypes.c_bool), - ('has_bfdot2_bfadd', ctypes.c_bool), - ('has_fmulz', ctypes.c_bool), - ('has_fmulz_no_denorms', ctypes.c_bool), - ('has_find_msb_rev', ctypes.c_bool), - ('has_pack_half_2x16_rtz', ctypes.c_bool), - ('has_bit_test', ctypes.c_bool), - ('has_bfe', ctypes.c_bool), - ('has_bfm', ctypes.c_bool), - ('has_bfi', ctypes.c_bool), - ('has_bitfield_select', ctypes.c_bool), - ('has_uclz', ctypes.c_bool), - ('has_msad', ctypes.c_bool), - ('has_f2e4m3fn_satfn', ctypes.c_bool), - ('has_load_global_bounded', ctypes.c_bool), - ('intel_vec4', ctypes.c_bool), - ('avoid_ternary_with_two_constants', ctypes.c_bool), - ('support_8bit_alu', ctypes.c_bool), - ('support_16bit_alu', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 2), - ('max_unroll_iterations', ctypes.c_uint32), - ('max_unroll_iterations_aggressive', ctypes.c_uint32), - ('max_unroll_iterations_fp64', ctypes.c_uint32), - ('lower_uniforms_to_ubo', ctypes.c_bool), - ('force_indirect_unrolling_sampler', ctypes.c_bool), - ('no_integers', ctypes.c_bool), - ('PADDING_2', ctypes.c_ubyte), - ('force_indirect_unrolling', c__EA_nir_variable_mode), - ('driver_functions', ctypes.c_bool), - ('late_lower_int64', ctypes.c_bool), - ('PADDING_3', ctypes.c_ubyte * 2), - ('lower_int64_options', nir_lower_int64_options), - ('lower_doubles_options', nir_lower_doubles_options), - ('divergence_analysis_options', nir_divergence_options), - ('support_indirect_inputs', ctypes.c_ubyte), - ('support_indirect_outputs', ctypes.c_ubyte), - ('lower_image_offset_to_range_base', ctypes.c_bool), - ('lower_atomic_offset_to_range_base', ctypes.c_bool), - ('preserve_mediump', ctypes.c_bool), - ('lower_fquantize2f16', ctypes.c_bool), - ('force_f2f16_rtz', ctypes.c_bool), - ('lower_layer_fs_input_to_sysval', ctypes.c_bool), - ('compact_arrays', ctypes.c_bool), - ('discard_is_demote', ctypes.c_bool), - ('has_ddx_intrinsics', ctypes.c_bool), - ('scalarize_ddx', ctypes.c_bool), - ('per_view_unique_driver_locations', ctypes.c_bool), - ('compact_view_index', ctypes.c_bool), - ('PADDING_4', ctypes.c_ubyte * 2), - ('io_options', nir_io_options), - ('skip_lower_packing_ops', ctypes.c_uint32), - ('lower_mediump_io', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_nir_shader))), - ('varying_expression_max_cost', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader))), - ('varying_estimate_instr_cost', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_instr))), - ('max_varying_expression_cost', ctypes.c_uint32), - ('PADDING_5', ctypes.c_ubyte * 4), -] - -class struct_nir_xfb_info(Structure): - pass - -class struct_u_printf_info(Structure): - pass - -class struct_shader_info(Structure): - pass - - -# values for enumeration 'pipe_shader_type' -pipe_shader_type__enumvalues = { - -1: 'MESA_SHADER_NONE', - 0: 'MESA_SHADER_VERTEX', - 0: 'PIPE_SHADER_VERTEX', - 1: 'MESA_SHADER_TESS_CTRL', - 1: 'PIPE_SHADER_TESS_CTRL', - 2: 'MESA_SHADER_TESS_EVAL', - 2: 'PIPE_SHADER_TESS_EVAL', - 3: 'MESA_SHADER_GEOMETRY', - 3: 'PIPE_SHADER_GEOMETRY', - 4: 'MESA_SHADER_FRAGMENT', - 4: 'PIPE_SHADER_FRAGMENT', - 5: 'MESA_SHADER_COMPUTE', - 5: 'PIPE_SHADER_COMPUTE', - 6: 'PIPE_SHADER_TYPES', - 6: 'MESA_SHADER_TASK', - 6: 'PIPE_SHADER_TASK', - 7: 'MESA_SHADER_MESH', - 7: 'PIPE_SHADER_MESH', - 8: 'PIPE_SHADER_MESH_TYPES', - 8: 'MESA_SHADER_RAYGEN', - 9: 'MESA_SHADER_ANY_HIT', - 10: 'MESA_SHADER_CLOSEST_HIT', - 11: 'MESA_SHADER_MISS', - 12: 'MESA_SHADER_INTERSECTION', - 13: 'MESA_SHADER_CALLABLE', - 14: 'MESA_SHADER_KERNEL', -} -MESA_SHADER_NONE = -1 -MESA_SHADER_VERTEX = 0 -PIPE_SHADER_VERTEX = 0 -MESA_SHADER_TESS_CTRL = 1 -PIPE_SHADER_TESS_CTRL = 1 -MESA_SHADER_TESS_EVAL = 2 -PIPE_SHADER_TESS_EVAL = 2 -MESA_SHADER_GEOMETRY = 3 -PIPE_SHADER_GEOMETRY = 3 -MESA_SHADER_FRAGMENT = 4 -PIPE_SHADER_FRAGMENT = 4 -MESA_SHADER_COMPUTE = 5 -PIPE_SHADER_COMPUTE = 5 -PIPE_SHADER_TYPES = 6 -MESA_SHADER_TASK = 6 -PIPE_SHADER_TASK = 6 -MESA_SHADER_MESH = 7 -PIPE_SHADER_MESH = 7 -PIPE_SHADER_MESH_TYPES = 8 -MESA_SHADER_RAYGEN = 8 -MESA_SHADER_ANY_HIT = 9 -MESA_SHADER_CLOSEST_HIT = 10 -MESA_SHADER_MISS = 11 -MESA_SHADER_INTERSECTION = 12 -MESA_SHADER_CALLABLE = 13 -MESA_SHADER_KERNEL = 14 -pipe_shader_type = ctypes.c_int32 # enum - -# values for enumeration 'gl_subgroup_size' -gl_subgroup_size__enumvalues = { - 0: 'SUBGROUP_SIZE_VARYING', - 1: 'SUBGROUP_SIZE_UNIFORM', - 2: 'SUBGROUP_SIZE_API_CONSTANT', - 3: 'SUBGROUP_SIZE_FULL_SUBGROUPS', - 4: 'SUBGROUP_SIZE_REQUIRE_4', - 8: 'SUBGROUP_SIZE_REQUIRE_8', - 16: 'SUBGROUP_SIZE_REQUIRE_16', - 32: 'SUBGROUP_SIZE_REQUIRE_32', - 64: 'SUBGROUP_SIZE_REQUIRE_64', - 128: 'SUBGROUP_SIZE_REQUIRE_128', -} -SUBGROUP_SIZE_VARYING = 0 -SUBGROUP_SIZE_UNIFORM = 1 -SUBGROUP_SIZE_API_CONSTANT = 2 -SUBGROUP_SIZE_FULL_SUBGROUPS = 3 -SUBGROUP_SIZE_REQUIRE_4 = 4 -SUBGROUP_SIZE_REQUIRE_8 = 8 -SUBGROUP_SIZE_REQUIRE_16 = 16 -SUBGROUP_SIZE_REQUIRE_32 = 32 -SUBGROUP_SIZE_REQUIRE_64 = 64 -SUBGROUP_SIZE_REQUIRE_128 = 128 -gl_subgroup_size = ctypes.c_uint32 # enum - -# values for enumeration 'gl_derivative_group' -gl_derivative_group__enumvalues = { - 0: 'DERIVATIVE_GROUP_NONE', - 1: 'DERIVATIVE_GROUP_QUADS', - 2: 'DERIVATIVE_GROUP_LINEAR', -} -DERIVATIVE_GROUP_NONE = 0 -DERIVATIVE_GROUP_QUADS = 1 -DERIVATIVE_GROUP_LINEAR = 2 -gl_derivative_group = ctypes.c_uint32 # enum -class union_shader_info_0(Union): - pass - -class struct_shader_info_0_vs(Structure): - pass - -struct_shader_info_0_vs._pack_ = 1 # source:False -struct_shader_info_0_vs._fields_ = [ - ('double_inputs', ctypes.c_uint64), - ('blit_sgprs_amd', ctypes.c_ubyte, 4), - ('tes_agx', ctypes.c_ubyte, 1), - ('window_space_position', ctypes.c_ubyte, 1), - ('needs_edge_flag', ctypes.c_ubyte, 1), - ('PADDING_0', ctypes.c_uint64, 57), -] - -class struct_shader_info_0_gs(Structure): - pass - - -# values for enumeration 'mesa_prim' -mesa_prim__enumvalues = { - 0: 'MESA_PRIM_POINTS', - 1: 'MESA_PRIM_LINES', - 2: 'MESA_PRIM_LINE_LOOP', - 3: 'MESA_PRIM_LINE_STRIP', - 4: 'MESA_PRIM_TRIANGLES', - 5: 'MESA_PRIM_TRIANGLE_STRIP', - 6: 'MESA_PRIM_TRIANGLE_FAN', - 7: 'MESA_PRIM_QUADS', - 8: 'MESA_PRIM_QUAD_STRIP', - 9: 'MESA_PRIM_POLYGON', - 10: 'MESA_PRIM_LINES_ADJACENCY', - 11: 'MESA_PRIM_LINE_STRIP_ADJACENCY', - 12: 'MESA_PRIM_TRIANGLES_ADJACENCY', - 13: 'MESA_PRIM_TRIANGLE_STRIP_ADJACENCY', - 14: 'MESA_PRIM_PATCHES', - 14: 'MESA_PRIM_MAX', - 15: 'MESA_PRIM_COUNT', - 28: 'MESA_PRIM_UNKNOWN', -} -MESA_PRIM_POINTS = 0 -MESA_PRIM_LINES = 1 -MESA_PRIM_LINE_LOOP = 2 -MESA_PRIM_LINE_STRIP = 3 -MESA_PRIM_TRIANGLES = 4 -MESA_PRIM_TRIANGLE_STRIP = 5 -MESA_PRIM_TRIANGLE_FAN = 6 -MESA_PRIM_QUADS = 7 -MESA_PRIM_QUAD_STRIP = 8 -MESA_PRIM_POLYGON = 9 -MESA_PRIM_LINES_ADJACENCY = 10 -MESA_PRIM_LINE_STRIP_ADJACENCY = 11 -MESA_PRIM_TRIANGLES_ADJACENCY = 12 -MESA_PRIM_TRIANGLE_STRIP_ADJACENCY = 13 -MESA_PRIM_PATCHES = 14 -MESA_PRIM_MAX = 14 -MESA_PRIM_COUNT = 15 -MESA_PRIM_UNKNOWN = 28 -mesa_prim = ctypes.c_uint32 # enum -struct_shader_info_0_gs._pack_ = 1 # source:False -struct_shader_info_0_gs._fields_ = [ - ('output_primitive', mesa_prim), - ('input_primitive', mesa_prim), - ('vertices_out', ctypes.c_uint16), - ('invocations', ctypes.c_ubyte), - ('vertices_in', ctypes.c_ubyte, 3), - ('uses_end_primitive', ctypes.c_ubyte, 1), - ('active_stream_mask', ctypes.c_ubyte, 4), -] - -class struct_shader_info_0_fs(Structure): - pass - - -# values for enumeration 'c_uint64' -c_uint64__enumvalues = { - 0: 'FRAG_DEPTH_LAYOUT_NONE', - 1: 'FRAG_DEPTH_LAYOUT_ANY', - 2: 'FRAG_DEPTH_LAYOUT_GREATER', - 3: 'FRAG_DEPTH_LAYOUT_LESS', - 4: 'FRAG_DEPTH_LAYOUT_UNCHANGED', -} -FRAG_DEPTH_LAYOUT_NONE = 0 -FRAG_DEPTH_LAYOUT_ANY = 1 -FRAG_DEPTH_LAYOUT_GREATER = 2 -FRAG_DEPTH_LAYOUT_LESS = 3 -FRAG_DEPTH_LAYOUT_UNCHANGED = 4 -c_uint64 = ctypes.c_uint32 # enum - -# values for enumeration 'c_bool' -c_bool__enumvalues = { - 0: 'FRAG_STENCIL_LAYOUT_NONE', - 1: 'FRAG_STENCIL_LAYOUT_ANY', - 2: 'FRAG_STENCIL_LAYOUT_GREATER', - 3: 'FRAG_STENCIL_LAYOUT_LESS', - 4: 'FRAG_STENCIL_LAYOUT_UNCHANGED', -} -FRAG_STENCIL_LAYOUT_NONE = 0 -FRAG_STENCIL_LAYOUT_ANY = 1 -FRAG_STENCIL_LAYOUT_GREATER = 2 -FRAG_STENCIL_LAYOUT_LESS = 3 -FRAG_STENCIL_LAYOUT_UNCHANGED = 4 -c_bool = ctypes.c_uint32 # enum -struct_shader_info_0_fs._pack_ = 1 # source:False -struct_shader_info_0_fs._fields_ = [ - ('uses_discard', ctypes.c_uint64, 1), - ('uses_fbfetch_output', ctypes.c_uint64, 1), - ('fbfetch_coherent', ctypes.c_uint64, 1), - ('color_is_dual_source', ctypes.c_uint64, 1), - ('require_full_quads', ctypes.c_uint64, 1), - ('quad_derivatives', ctypes.c_uint64, 1), - ('needs_coarse_quad_helper_invocations', ctypes.c_uint64, 1), - ('needs_full_quad_helper_invocations', ctypes.c_uint64, 1), - ('uses_sample_qualifier', ctypes.c_uint64, 1), - ('uses_sample_shading', ctypes.c_uint64, 1), - ('early_fragment_tests', ctypes.c_uint64, 1), - ('inner_coverage', ctypes.c_uint64, 1), - ('post_depth_coverage', ctypes.c_uint64, 1), - ('pixel_center_integer', ctypes.c_uint64, 1), - ('origin_upper_left', ctypes.c_uint64, 1), - ('pixel_interlock_ordered', ctypes.c_uint64, 1), - ('pixel_interlock_unordered', ctypes.c_uint64, 1), - ('sample_interlock_ordered', ctypes.c_uint64, 1), - ('sample_interlock_unordered', ctypes.c_uint64, 1), - ('untyped_color_outputs', ctypes.c_uint64, 1), - ('depth_layout', c_uint64, 3), - ('color0_interp', ctypes.c_uint64, 3), - ('color0_sample', ctypes.c_uint64, 1), - ('color0_centroid', ctypes.c_uint64, 1), - ('color1_interp', ctypes.c_uint64, 3), - ('color1_sample', ctypes.c_uint64, 1), - ('color1_centroid', ctypes.c_uint64, 1), - ('PADDING_0', ctypes.c_uint32, 31), - ('advanced_blend_modes', ctypes.c_uint32), - ('early_and_late_fragment_tests', ctypes.c_bool, 1), - ('stencil_front_layout', c_bool, 3), - ('stencil_back_layout', c_bool, 3), - ('PADDING_1', ctypes.c_uint32, 25), -] - -class struct_shader_info_0_cs(Structure): - pass - -struct_shader_info_0_cs._pack_ = 1 # source:False -struct_shader_info_0_cs._fields_ = [ - ('workgroup_size_hint', ctypes.c_uint16 * 3), - ('user_data_components_amd', ctypes.c_ubyte, 4), - ('has_variable_shared_mem', ctypes.c_ubyte, 1), - ('has_cooperative_matrix', ctypes.c_ubyte, 1), - ('PADDING_0', ctypes.c_uint8, 2), - ('image_block_size_per_thread_agx', ctypes.c_ubyte, 8), - ('ptr_size', ctypes.c_uint32), - ('shader_index', ctypes.c_uint32), - ('node_payloads_size', ctypes.c_uint32), - ('workgroup_count', ctypes.c_uint32 * 3), -] - -class struct_shader_info_0_tess(Structure): - pass - - -# values for enumeration 'tess_primitive_mode' -tess_primitive_mode__enumvalues = { - 0: 'TESS_PRIMITIVE_UNSPECIFIED', - 1: 'TESS_PRIMITIVE_TRIANGLES', - 2: 'TESS_PRIMITIVE_QUADS', - 3: 'TESS_PRIMITIVE_ISOLINES', -} -TESS_PRIMITIVE_UNSPECIFIED = 0 -TESS_PRIMITIVE_TRIANGLES = 1 -TESS_PRIMITIVE_QUADS = 2 -TESS_PRIMITIVE_ISOLINES = 3 -tess_primitive_mode = ctypes.c_uint32 # enum -struct_shader_info_0_tess._pack_ = 1 # source:False -struct_shader_info_0_tess._fields_ = [ - ('_primitive_mode', tess_primitive_mode), - ('tcs_vertices_out', ctypes.c_ubyte), - ('spacing', ctypes.c_uint32, 2), - ('ccw', ctypes.c_uint32, 1), - ('point_mode', ctypes.c_uint32, 1), - ('PADDING_0', ctypes.c_uint32, 20), - ('tcs_same_invocation_inputs_read', ctypes.c_uint64), - ('tcs_cross_invocation_inputs_read', ctypes.c_uint64), - ('tcs_cross_invocation_outputs_read', ctypes.c_uint64), - ('tcs_cross_invocation_outputs_written', ctypes.c_uint64), - ('tcs_outputs_read_by_tes', ctypes.c_uint64), - ('tcs_patch_outputs_read_by_tes', ctypes.c_uint32), - ('tcs_outputs_read_by_tes_16bit', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), -] - -class struct_shader_info_0_mesh(Structure): - pass - -struct_shader_info_0_mesh._pack_ = 1 # source:False -struct_shader_info_0_mesh._fields_ = [ - ('ms_cross_invocation_output_access', ctypes.c_uint64), - ('ts_mesh_dispatch_dimensions', ctypes.c_uint32 * 3), - ('max_vertices_out', ctypes.c_uint16), - ('max_primitives_out', ctypes.c_uint16), - ('primitive_type', mesa_prim), - ('nv', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -union_shader_info_0._pack_ = 1 # source:False -union_shader_info_0._fields_ = [ - ('vs', struct_shader_info_0_vs), - ('gs', struct_shader_info_0_gs), - ('fs', struct_shader_info_0_fs), - ('cs', struct_shader_info_0_cs), - ('tess', struct_shader_info_0_tess), - ('mesh', struct_shader_info_0_mesh), - ('PADDING_0', ctypes.c_ubyte * 24), -] - -struct_shader_info._pack_ = 1 # source:False -struct_shader_info._anonymous_ = ('_0',) -struct_shader_info._fields_ = [ - ('name', ctypes.POINTER(ctypes.c_char)), - ('label', ctypes.POINTER(ctypes.c_char)), - ('internal', ctypes.c_bool), - ('source_blake3', ctypes.c_ubyte * 32), - ('stage', ctypes.c_ubyte), - ('prev_stage', ctypes.c_ubyte), - ('next_stage', ctypes.c_ubyte), - ('prev_stage_has_xfb', ctypes.c_ubyte), - ('num_textures', ctypes.c_ubyte), - ('num_ubos', ctypes.c_ubyte), - ('num_abos', ctypes.c_ubyte), - ('num_ssbos', ctypes.c_ubyte), - ('num_images', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('inputs_read', ctypes.c_uint64), - ('dual_slot_inputs', ctypes.c_uint64), - ('outputs_written', ctypes.c_uint64), - ('outputs_read', ctypes.c_uint64), - ('system_values_read', ctypes.c_uint32 * 4), - ('per_primitive_inputs', ctypes.c_uint64), - ('per_primitive_outputs', ctypes.c_uint64), - ('per_view_outputs', ctypes.c_uint64), - ('view_mask', ctypes.c_uint32), - ('inputs_read_16bit', ctypes.c_uint16), - ('outputs_written_16bit', ctypes.c_uint16), - ('outputs_read_16bit', ctypes.c_uint16), - ('inputs_read_indirectly_16bit', ctypes.c_uint16), - ('outputs_read_indirectly_16bit', ctypes.c_uint16), - ('outputs_written_indirectly_16bit', ctypes.c_uint16), - ('patch_inputs_read', ctypes.c_uint32), - ('patch_outputs_written', ctypes.c_uint32), - ('patch_outputs_read', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('inputs_read_indirectly', ctypes.c_uint64), - ('outputs_read_indirectly', ctypes.c_uint64), - ('outputs_written_indirectly', ctypes.c_uint64), - ('patch_inputs_read_indirectly', ctypes.c_uint32), - ('patch_outputs_read_indirectly', ctypes.c_uint32), - ('patch_outputs_written_indirectly', ctypes.c_uint32), - ('textures_used', ctypes.c_uint32 * 4), - ('textures_used_by_txf', ctypes.c_uint32 * 4), - ('samplers_used', ctypes.c_uint32 * 1), - ('images_used', ctypes.c_uint32 * 2), - ('image_buffers', ctypes.c_uint32 * 2), - ('msaa_images', ctypes.c_uint32 * 2), - ('float_controls_execution_mode', ctypes.c_uint32), - ('shared_size', ctypes.c_uint32), - ('task_payload_size', ctypes.c_uint32), - ('ray_queries', ctypes.c_uint32), - ('workgroup_size', ctypes.c_uint16 * 3), - ('PADDING_2', ctypes.c_ubyte * 2), - ('subgroup_size', gl_subgroup_size), - ('num_subgroups', ctypes.c_ubyte), - ('uses_wide_subgroup_intrinsics', ctypes.c_bool), - ('xfb_stride', ctypes.c_ubyte * 4), - ('inlinable_uniform_dw_offsets', ctypes.c_uint16 * 4), - ('num_inlinable_uniforms', ctypes.c_ubyte, 4), - ('clip_distance_array_size', ctypes.c_ubyte, 4), - ('cull_distance_array_size', ctypes.c_ubyte, 4), - ('uses_texture_gather', ctypes.c_ubyte, 1), - ('uses_resource_info_query', ctypes.c_ubyte, 1), - ('PADDING_3', ctypes.c_uint8, 2), - ('bit_sizes_float', ctypes.c_ubyte, 8), - ('bit_sizes_int', ctypes.c_ubyte), - ('first_ubo_is_default_ubo', ctypes.c_bool, 1), - ('separate_shader', ctypes.c_bool, 1), - ('has_transform_feedback_varyings', ctypes.c_bool, 1), - ('flrp_lowered', ctypes.c_bool, 1), - ('io_lowered', ctypes.c_bool, 1), - ('var_copies_lowered', ctypes.c_bool, 1), - ('writes_memory', ctypes.c_bool, 1), - ('layer_viewport_relative', ctypes.c_bool, 1), - ('uses_control_barrier', ctypes.c_bool, 1), - ('uses_memory_barrier', ctypes.c_bool, 1), - ('uses_bindless', ctypes.c_bool, 1), - ('shared_memory_explicit_layout', ctypes.c_bool, 1), - ('zero_initialize_shared_memory', ctypes.c_bool, 1), - ('workgroup_size_variable', ctypes.c_bool, 1), - ('uses_printf', ctypes.c_bool, 1), - ('maximally_reconverges', ctypes.c_bool, 1), - ('use_aco_amd', ctypes.c_bool, 1), - ('use_lowered_image_to_global', ctypes.c_bool, 1), - ('PADDING_4', ctypes.c_uint8, 6), - ('use_legacy_math_rules', ctypes.c_bool, 8), - ('derivative_group', gl_derivative_group, 2), - ('PADDING_5', ctypes.c_uint64, 46), - ('_0', union_shader_info_0), -] - -struct_nir_shader._pack_ = 1 # source:False -struct_nir_shader._fields_ = [ - ('gctx', ctypes.POINTER(struct_gc_ctx)), - ('variables', struct_exec_list), - ('options', ctypes.POINTER(struct_nir_shader_compiler_options)), - ('info', struct_shader_info), - ('functions', struct_exec_list), - ('num_inputs', ctypes.c_uint32), - ('num_uniforms', ctypes.c_uint32), - ('num_outputs', ctypes.c_uint32), - ('global_mem_size', ctypes.c_uint32), - ('scratch_size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('constant_data', ctypes.POINTER(None)), - ('constant_data_size', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('xfb_info', ctypes.POINTER(struct_nir_xfb_info)), - ('printf_info_count', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('printf_info', ctypes.POINTER(struct_u_printf_info)), - ('has_debug_info', ctypes.c_bool), - ('PADDING_3', ctypes.c_ubyte * 7), -] - -nir_shader_compiler_options = struct_nir_shader_compiler_options +class struct_u_printf_info(Struct): pass u_printf_info = struct_u_printf_info -nir_debug = 0 # Variable ctypes.c_uint32 -nir_debug_print_shader = [] # Variable ctypes.c_bool * 15 +uint32_t = ctypes.c_uint32 +try: nir_debug = uint32_t.in_dll(dll, 'nir_debug') +except (ValueError,AttributeError): pass +try: nir_debug_print_shader = (ctypes.c_bool * 15).in_dll(dll, 'nir_debug_print_shader') +except (ValueError,AttributeError): pass nir_component_mask_t = ctypes.c_uint16 -try: - nir_round_up_components = _libraries['FIXME_STUB'].nir_round_up_components - nir_round_up_components.restype = ctypes.c_uint32 - nir_round_up_components.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - nir_round_down_components = _libraries['FIXME_STUB'].nir_round_down_components - nir_round_down_components.restype = ctypes.c_uint32 - nir_round_down_components.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - nir_component_mask = _libraries['FIXME_STUB'].nir_component_mask - nir_component_mask.restype = nir_component_mask_t - nir_component_mask.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - nir_process_debug_variable = _libraries['libtinymesa_cpu.so'].nir_process_debug_variable - nir_process_debug_variable.restype = None - nir_process_debug_variable.argtypes = [] -except AttributeError: - pass -try: - nir_component_mask_can_reinterpret = _libraries['libtinymesa_cpu.so'].nir_component_mask_can_reinterpret - nir_component_mask_can_reinterpret.restype = ctypes.c_bool - nir_component_mask_can_reinterpret.argtypes = [nir_component_mask_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_component_mask_reinterpret = _libraries['libtinymesa_cpu.so'].nir_component_mask_reinterpret - nir_component_mask_reinterpret.restype = nir_component_mask_t - nir_component_mask_reinterpret.argtypes = [nir_component_mask_t, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -class struct_nir_state_slot(Structure): - pass +# void nir_process_debug_variable(void) +try: (nir_process_debug_variable:=dll.nir_process_debug_variable).restype, nir_process_debug_variable.argtypes = None, [] +except AttributeError: pass -struct_nir_state_slot._pack_ = 1 # source:False +# bool nir_component_mask_can_reinterpret(nir_component_mask_t mask, unsigned int old_bit_size, unsigned int new_bit_size) +try: (nir_component_mask_can_reinterpret:=dll.nir_component_mask_can_reinterpret).restype, nir_component_mask_can_reinterpret.argtypes = ctypes.c_bool, [nir_component_mask_t, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# nir_component_mask_t nir_component_mask_reinterpret(nir_component_mask_t mask, unsigned int old_bit_size, unsigned int new_bit_size) +try: (nir_component_mask_reinterpret:=dll.nir_component_mask_reinterpret).restype, nir_component_mask_reinterpret.argtypes = nir_component_mask_t, [nir_component_mask_t, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +class struct_nir_state_slot(Struct): pass +gl_state_index16 = ctypes.c_int16 struct_nir_state_slot._fields_ = [ - ('tokens', ctypes.c_int16 * 4), + ('tokens', (gl_state_index16 * 4)), ] - nir_state_slot = struct_nir_state_slot +nir_rounding_mode = CEnum(ctypes.c_uint32) +nir_rounding_mode_undef = nir_rounding_mode.define('nir_rounding_mode_undef', 0) +nir_rounding_mode_rtne = nir_rounding_mode.define('nir_rounding_mode_rtne', 1) +nir_rounding_mode_ru = nir_rounding_mode.define('nir_rounding_mode_ru', 2) +nir_rounding_mode_rd = nir_rounding_mode.define('nir_rounding_mode_rd', 3) +nir_rounding_mode_rtz = nir_rounding_mode.define('nir_rounding_mode_rtz', 4) -# values for enumeration 'c__EA_nir_rounding_mode' -c__EA_nir_rounding_mode__enumvalues = { - 0: 'nir_rounding_mode_undef', - 1: 'nir_rounding_mode_rtne', - 2: 'nir_rounding_mode_ru', - 3: 'nir_rounding_mode_rd', - 4: 'nir_rounding_mode_rtz', -} -nir_rounding_mode_undef = 0 -nir_rounding_mode_rtne = 1 -nir_rounding_mode_ru = 2 -nir_rounding_mode_rd = 3 -nir_rounding_mode_rtz = 4 -c__EA_nir_rounding_mode = ctypes.c_uint32 # enum -nir_rounding_mode = c__EA_nir_rounding_mode -nir_rounding_mode__enumvalues = c__EA_nir_rounding_mode__enumvalues +nir_ray_query_value = CEnum(ctypes.c_uint32) +nir_ray_query_value_intersection_type = nir_ray_query_value.define('nir_ray_query_value_intersection_type', 0) +nir_ray_query_value_intersection_t = nir_ray_query_value.define('nir_ray_query_value_intersection_t', 1) +nir_ray_query_value_intersection_instance_custom_index = nir_ray_query_value.define('nir_ray_query_value_intersection_instance_custom_index', 2) +nir_ray_query_value_intersection_instance_id = nir_ray_query_value.define('nir_ray_query_value_intersection_instance_id', 3) +nir_ray_query_value_intersection_instance_sbt_index = nir_ray_query_value.define('nir_ray_query_value_intersection_instance_sbt_index', 4) +nir_ray_query_value_intersection_geometry_index = nir_ray_query_value.define('nir_ray_query_value_intersection_geometry_index', 5) +nir_ray_query_value_intersection_primitive_index = nir_ray_query_value.define('nir_ray_query_value_intersection_primitive_index', 6) +nir_ray_query_value_intersection_barycentrics = nir_ray_query_value.define('nir_ray_query_value_intersection_barycentrics', 7) +nir_ray_query_value_intersection_front_face = nir_ray_query_value.define('nir_ray_query_value_intersection_front_face', 8) +nir_ray_query_value_intersection_object_ray_direction = nir_ray_query_value.define('nir_ray_query_value_intersection_object_ray_direction', 9) +nir_ray_query_value_intersection_object_ray_origin = nir_ray_query_value.define('nir_ray_query_value_intersection_object_ray_origin', 10) +nir_ray_query_value_intersection_object_to_world = nir_ray_query_value.define('nir_ray_query_value_intersection_object_to_world', 11) +nir_ray_query_value_intersection_world_to_object = nir_ray_query_value.define('nir_ray_query_value_intersection_world_to_object', 12) +nir_ray_query_value_intersection_candidate_aabb_opaque = nir_ray_query_value.define('nir_ray_query_value_intersection_candidate_aabb_opaque', 13) +nir_ray_query_value_tmin = nir_ray_query_value.define('nir_ray_query_value_tmin', 14) +nir_ray_query_value_flags = nir_ray_query_value.define('nir_ray_query_value_flags', 15) +nir_ray_query_value_world_ray_direction = nir_ray_query_value.define('nir_ray_query_value_world_ray_direction', 16) +nir_ray_query_value_world_ray_origin = nir_ray_query_value.define('nir_ray_query_value_world_ray_origin', 17) +nir_ray_query_value_intersection_triangle_vertex_positions = nir_ray_query_value.define('nir_ray_query_value_intersection_triangle_vertex_positions', 18) -# values for enumeration 'c__EA_nir_ray_query_value' -c__EA_nir_ray_query_value__enumvalues = { - 0: 'nir_ray_query_value_intersection_type', - 1: 'nir_ray_query_value_intersection_t', - 2: 'nir_ray_query_value_intersection_instance_custom_index', - 3: 'nir_ray_query_value_intersection_instance_id', - 4: 'nir_ray_query_value_intersection_instance_sbt_index', - 5: 'nir_ray_query_value_intersection_geometry_index', - 6: 'nir_ray_query_value_intersection_primitive_index', - 7: 'nir_ray_query_value_intersection_barycentrics', - 8: 'nir_ray_query_value_intersection_front_face', - 9: 'nir_ray_query_value_intersection_object_ray_direction', - 10: 'nir_ray_query_value_intersection_object_ray_origin', - 11: 'nir_ray_query_value_intersection_object_to_world', - 12: 'nir_ray_query_value_intersection_world_to_object', - 13: 'nir_ray_query_value_intersection_candidate_aabb_opaque', - 14: 'nir_ray_query_value_tmin', - 15: 'nir_ray_query_value_flags', - 16: 'nir_ray_query_value_world_ray_direction', - 17: 'nir_ray_query_value_world_ray_origin', - 18: 'nir_ray_query_value_intersection_triangle_vertex_positions', -} -nir_ray_query_value_intersection_type = 0 -nir_ray_query_value_intersection_t = 1 -nir_ray_query_value_intersection_instance_custom_index = 2 -nir_ray_query_value_intersection_instance_id = 3 -nir_ray_query_value_intersection_instance_sbt_index = 4 -nir_ray_query_value_intersection_geometry_index = 5 -nir_ray_query_value_intersection_primitive_index = 6 -nir_ray_query_value_intersection_barycentrics = 7 -nir_ray_query_value_intersection_front_face = 8 -nir_ray_query_value_intersection_object_ray_direction = 9 -nir_ray_query_value_intersection_object_ray_origin = 10 -nir_ray_query_value_intersection_object_to_world = 11 -nir_ray_query_value_intersection_world_to_object = 12 -nir_ray_query_value_intersection_candidate_aabb_opaque = 13 -nir_ray_query_value_tmin = 14 -nir_ray_query_value_flags = 15 -nir_ray_query_value_world_ray_direction = 16 -nir_ray_query_value_world_ray_origin = 17 -nir_ray_query_value_intersection_triangle_vertex_positions = 18 -c__EA_nir_ray_query_value = ctypes.c_uint32 # enum -nir_ray_query_value = c__EA_nir_ray_query_value -nir_ray_query_value__enumvalues = c__EA_nir_ray_query_value__enumvalues +nir_resource_data_intel = CEnum(ctypes.c_uint32) +nir_resource_intel_bindless = nir_resource_data_intel.define('nir_resource_intel_bindless', 1) +nir_resource_intel_pushable = nir_resource_data_intel.define('nir_resource_intel_pushable', 2) +nir_resource_intel_sampler = nir_resource_data_intel.define('nir_resource_intel_sampler', 4) +nir_resource_intel_non_uniform = nir_resource_data_intel.define('nir_resource_intel_non_uniform', 8) +nir_resource_intel_sampler_embedded = nir_resource_data_intel.define('nir_resource_intel_sampler_embedded', 16) -# values for enumeration 'c__EA_nir_resource_data_intel' -c__EA_nir_resource_data_intel__enumvalues = { - 1: 'nir_resource_intel_bindless', - 2: 'nir_resource_intel_pushable', - 4: 'nir_resource_intel_sampler', - 8: 'nir_resource_intel_non_uniform', - 16: 'nir_resource_intel_sampler_embedded', -} -nir_resource_intel_bindless = 1 -nir_resource_intel_pushable = 2 -nir_resource_intel_sampler = 4 -nir_resource_intel_non_uniform = 8 -nir_resource_intel_sampler_embedded = 16 -c__EA_nir_resource_data_intel = ctypes.c_uint32 # enum -nir_resource_data_intel = c__EA_nir_resource_data_intel -nir_resource_data_intel__enumvalues = c__EA_nir_resource_data_intel__enumvalues +nir_preamble_class = CEnum(ctypes.c_uint32) +nir_preamble_class_general = nir_preamble_class.define('nir_preamble_class_general', 0) +nir_preamble_class_image = nir_preamble_class.define('nir_preamble_class_image', 1) +nir_preamble_num_classes = nir_preamble_class.define('nir_preamble_num_classes', 2) -# values for enumeration 'c__EA_nir_preamble_class' -c__EA_nir_preamble_class__enumvalues = { - 0: 'nir_preamble_class_general', - 1: 'nir_preamble_class_image', - 2: 'nir_preamble_num_classes', -} -nir_preamble_class_general = 0 -nir_preamble_class_image = 1 -nir_preamble_num_classes = 2 -c__EA_nir_preamble_class = ctypes.c_uint32 # enum -nir_preamble_class = c__EA_nir_preamble_class -nir_preamble_class__enumvalues = c__EA_nir_preamble_class__enumvalues +nir_cmat_signed = CEnum(ctypes.c_uint32) +NIR_CMAT_A_SIGNED = nir_cmat_signed.define('NIR_CMAT_A_SIGNED', 1) +NIR_CMAT_B_SIGNED = nir_cmat_signed.define('NIR_CMAT_B_SIGNED', 2) +NIR_CMAT_C_SIGNED = nir_cmat_signed.define('NIR_CMAT_C_SIGNED', 4) +NIR_CMAT_RESULT_SIGNED = nir_cmat_signed.define('NIR_CMAT_RESULT_SIGNED', 8) -# values for enumeration 'c__EA_nir_cmat_signed' -c__EA_nir_cmat_signed__enumvalues = { - 1: 'NIR_CMAT_A_SIGNED', - 2: 'NIR_CMAT_B_SIGNED', - 4: 'NIR_CMAT_C_SIGNED', - 8: 'NIR_CMAT_RESULT_SIGNED', -} -NIR_CMAT_A_SIGNED = 1 -NIR_CMAT_B_SIGNED = 2 -NIR_CMAT_C_SIGNED = 4 -NIR_CMAT_RESULT_SIGNED = 8 -c__EA_nir_cmat_signed = ctypes.c_uint32 # enum -nir_cmat_signed = c__EA_nir_cmat_signed -nir_cmat_signed__enumvalues = c__EA_nir_cmat_signed__enumvalues -class union_c__UA_nir_const_value(Union): - pass - -union_c__UA_nir_const_value._pack_ = 1 # source:False -union_c__UA_nir_const_value._fields_ = [ - ('b', ctypes.c_bool), - ('f32', ctypes.c_float), - ('f64', ctypes.c_double), - ('i8', ctypes.c_byte), - ('u8', ctypes.c_ubyte), - ('i16', ctypes.c_int16), - ('u16', ctypes.c_uint16), - ('i32', ctypes.c_int32), - ('u32', ctypes.c_uint32), - ('i64', ctypes.c_int64), - ('u64', ctypes.c_uint64), -] - -nir_const_value = union_c__UA_nir_const_value -try: - nir_const_value_for_raw_uint = _libraries['FIXME_STUB'].nir_const_value_for_raw_uint - nir_const_value_for_raw_uint.restype = nir_const_value - nir_const_value_for_raw_uint.argtypes = [uint64_t, ctypes.c_uint32] -except AttributeError: - pass +class nir_const_value(ctypes.Union): pass +int8_t = ctypes.c_char +uint8_t = ctypes.c_ubyte +int16_t = ctypes.c_int16 +uint16_t = ctypes.c_uint16 +int32_t = ctypes.c_int32 int64_t = ctypes.c_int64 -try: - nir_const_value_for_int = _libraries['FIXME_STUB'].nir_const_value_for_int - nir_const_value_for_int.restype = nir_const_value - nir_const_value_for_int.argtypes = [int64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_for_uint = _libraries['FIXME_STUB'].nir_const_value_for_uint - nir_const_value_for_uint.restype = nir_const_value - nir_const_value_for_uint.argtypes = [uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_for_bool = _libraries['FIXME_STUB'].nir_const_value_for_bool - nir_const_value_for_bool.restype = nir_const_value - nir_const_value_for_bool.argtypes = [ctypes.c_bool, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_for_float = _libraries['libtinymesa_cpu.so'].nir_const_value_for_float - nir_const_value_for_float.restype = nir_const_value - nir_const_value_for_float.argtypes = [ctypes.c_double, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_as_int = _libraries['FIXME_STUB'].nir_const_value_as_int - nir_const_value_as_int.restype = int64_t - nir_const_value_as_int.argtypes = [nir_const_value, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_as_uint = _libraries['FIXME_STUB'].nir_const_value_as_uint - nir_const_value_as_uint.restype = uint64_t - nir_const_value_as_uint.argtypes = [nir_const_value, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_as_bool = _libraries['FIXME_STUB'].nir_const_value_as_bool - nir_const_value_as_bool.restype = ctypes.c_bool - nir_const_value_as_bool.argtypes = [nir_const_value, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_const_value_as_float = _libraries['libtinymesa_cpu.so'].nir_const_value_as_float - nir_const_value_as_float.restype = ctypes.c_double - nir_const_value_as_float.argtypes = [nir_const_value, ctypes.c_uint32] -except AttributeError: - pass -class struct_nir_constant(Structure): - pass - -struct_nir_constant._pack_ = 1 # source:False -struct_nir_constant._fields_ = [ - ('values', union_c__UA_nir_const_value * 16), - ('is_null_constant', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('num_elements', ctypes.c_uint32), - ('elements', ctypes.POINTER(ctypes.POINTER(struct_nir_constant))), +uint64_t = ctypes.c_uint64 +nir_const_value._fields_ = [ + ('b', ctypes.c_bool), + ('f32', ctypes.c_float), + ('f64', ctypes.c_double), + ('i8', int8_t), + ('u8', uint8_t), + ('i16', int16_t), + ('u16', uint16_t), + ('i32', int32_t), + ('u32', uint32_t), + ('i64', int64_t), + ('u64', uint64_t), ] +# nir_const_value nir_const_value_for_float(double b, unsigned int bit_size) +try: (nir_const_value_for_float:=dll.nir_const_value_for_float).restype, nir_const_value_for_float.argtypes = nir_const_value, [ctypes.c_double, ctypes.c_uint32] +except AttributeError: pass +# double nir_const_value_as_float(nir_const_value value, unsigned int bit_size) +try: (nir_const_value_as_float:=dll.nir_const_value_as_float).restype, nir_const_value_as_float.argtypes = ctypes.c_double, [nir_const_value, ctypes.c_uint32] +except AttributeError: pass + +class struct_nir_constant(Struct): pass nir_constant = struct_nir_constant +struct_nir_constant._fields_ = [ + ('values', (nir_const_value * 16)), + ('is_null_constant', ctypes.c_bool), + ('num_elements', ctypes.c_uint32), + ('elements', ctypes.POINTER(ctypes.POINTER(nir_constant))), +] +nir_depth_layout = CEnum(ctypes.c_uint32) +nir_depth_layout_none = nir_depth_layout.define('nir_depth_layout_none', 0) +nir_depth_layout_any = nir_depth_layout.define('nir_depth_layout_any', 1) +nir_depth_layout_greater = nir_depth_layout.define('nir_depth_layout_greater', 2) +nir_depth_layout_less = nir_depth_layout.define('nir_depth_layout_less', 3) +nir_depth_layout_unchanged = nir_depth_layout.define('nir_depth_layout_unchanged', 4) -# values for enumeration 'c__EA_nir_depth_layout' -c__EA_nir_depth_layout__enumvalues = { - 0: 'nir_depth_layout_none', - 1: 'nir_depth_layout_any', - 2: 'nir_depth_layout_greater', - 3: 'nir_depth_layout_less', - 4: 'nir_depth_layout_unchanged', -} -nir_depth_layout_none = 0 -nir_depth_layout_any = 1 -nir_depth_layout_greater = 2 -nir_depth_layout_less = 3 -nir_depth_layout_unchanged = 4 -c__EA_nir_depth_layout = ctypes.c_uint32 # enum -nir_depth_layout = c__EA_nir_depth_layout -nir_depth_layout__enumvalues = c__EA_nir_depth_layout__enumvalues +nir_var_declaration_type = CEnum(ctypes.c_uint32) +nir_var_declared_normally = nir_var_declaration_type.define('nir_var_declared_normally', 0) +nir_var_declared_implicitly = nir_var_declaration_type.define('nir_var_declared_implicitly', 1) +nir_var_hidden = nir_var_declaration_type.define('nir_var_hidden', 2) -# values for enumeration 'c__EA_nir_var_declaration_type' -c__EA_nir_var_declaration_type__enumvalues = { - 0: 'nir_var_declared_normally', - 1: 'nir_var_declared_implicitly', - 2: 'nir_var_hidden', -} -nir_var_declared_normally = 0 -nir_var_declared_implicitly = 1 -nir_var_hidden = 2 -c__EA_nir_var_declaration_type = ctypes.c_uint32 # enum -nir_var_declaration_type = c__EA_nir_var_declaration_type -nir_var_declaration_type__enumvalues = c__EA_nir_var_declaration_type__enumvalues -class struct_nir_variable_data(Structure): - pass +class struct_nir_variable_data(Struct): pass +class struct_nir_variable_data_0(ctypes.Union): pass +class struct_nir_variable_data_0_image(Struct): pass +enum_pipe_format = CEnum(ctypes.c_uint32) +PIPE_FORMAT_NONE = enum_pipe_format.define('PIPE_FORMAT_NONE', 0) +PIPE_FORMAT_R64_UINT = enum_pipe_format.define('PIPE_FORMAT_R64_UINT', 1) +PIPE_FORMAT_R64G64_UINT = enum_pipe_format.define('PIPE_FORMAT_R64G64_UINT', 2) +PIPE_FORMAT_R64G64B64_UINT = enum_pipe_format.define('PIPE_FORMAT_R64G64B64_UINT', 3) +PIPE_FORMAT_R64G64B64A64_UINT = enum_pipe_format.define('PIPE_FORMAT_R64G64B64A64_UINT', 4) +PIPE_FORMAT_R64_SINT = enum_pipe_format.define('PIPE_FORMAT_R64_SINT', 5) +PIPE_FORMAT_R64G64_SINT = enum_pipe_format.define('PIPE_FORMAT_R64G64_SINT', 6) +PIPE_FORMAT_R64G64B64_SINT = enum_pipe_format.define('PIPE_FORMAT_R64G64B64_SINT', 7) +PIPE_FORMAT_R64G64B64A64_SINT = enum_pipe_format.define('PIPE_FORMAT_R64G64B64A64_SINT', 8) +PIPE_FORMAT_R64_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R64_FLOAT', 9) +PIPE_FORMAT_R64G64_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R64G64_FLOAT', 10) +PIPE_FORMAT_R64G64B64_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R64G64B64_FLOAT', 11) +PIPE_FORMAT_R64G64B64A64_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R64G64B64A64_FLOAT', 12) +PIPE_FORMAT_R32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R32_FLOAT', 13) +PIPE_FORMAT_R32G32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R32G32_FLOAT', 14) +PIPE_FORMAT_R32G32B32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_FLOAT', 15) +PIPE_FORMAT_R32G32B32A32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_FLOAT', 16) +PIPE_FORMAT_R32_UNORM = enum_pipe_format.define('PIPE_FORMAT_R32_UNORM', 17) +PIPE_FORMAT_R32G32_UNORM = enum_pipe_format.define('PIPE_FORMAT_R32G32_UNORM', 18) +PIPE_FORMAT_R32G32B32_UNORM = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_UNORM', 19) +PIPE_FORMAT_R32G32B32A32_UNORM = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_UNORM', 20) +PIPE_FORMAT_R32_USCALED = enum_pipe_format.define('PIPE_FORMAT_R32_USCALED', 21) +PIPE_FORMAT_R32G32_USCALED = enum_pipe_format.define('PIPE_FORMAT_R32G32_USCALED', 22) +PIPE_FORMAT_R32G32B32_USCALED = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_USCALED', 23) +PIPE_FORMAT_R32G32B32A32_USCALED = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_USCALED', 24) +PIPE_FORMAT_R32_SNORM = enum_pipe_format.define('PIPE_FORMAT_R32_SNORM', 25) +PIPE_FORMAT_R32G32_SNORM = enum_pipe_format.define('PIPE_FORMAT_R32G32_SNORM', 26) +PIPE_FORMAT_R32G32B32_SNORM = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_SNORM', 27) +PIPE_FORMAT_R32G32B32A32_SNORM = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_SNORM', 28) +PIPE_FORMAT_R32_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R32_SSCALED', 29) +PIPE_FORMAT_R32G32_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R32G32_SSCALED', 30) +PIPE_FORMAT_R32G32B32_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_SSCALED', 31) +PIPE_FORMAT_R32G32B32A32_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_SSCALED', 32) +PIPE_FORMAT_R16_UNORM = enum_pipe_format.define('PIPE_FORMAT_R16_UNORM', 33) +PIPE_FORMAT_R16G16_UNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16_UNORM', 34) +PIPE_FORMAT_R16G16B16_UNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_UNORM', 35) +PIPE_FORMAT_R16G16B16A16_UNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_UNORM', 36) +PIPE_FORMAT_R16_USCALED = enum_pipe_format.define('PIPE_FORMAT_R16_USCALED', 37) +PIPE_FORMAT_R16G16_USCALED = enum_pipe_format.define('PIPE_FORMAT_R16G16_USCALED', 38) +PIPE_FORMAT_R16G16B16_USCALED = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_USCALED', 39) +PIPE_FORMAT_R16G16B16A16_USCALED = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_USCALED', 40) +PIPE_FORMAT_R16_SNORM = enum_pipe_format.define('PIPE_FORMAT_R16_SNORM', 41) +PIPE_FORMAT_R16G16_SNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16_SNORM', 42) +PIPE_FORMAT_R16G16B16_SNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_SNORM', 43) +PIPE_FORMAT_R16G16B16A16_SNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_SNORM', 44) +PIPE_FORMAT_R16_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R16_SSCALED', 45) +PIPE_FORMAT_R16G16_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R16G16_SSCALED', 46) +PIPE_FORMAT_R16G16B16_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_SSCALED', 47) +PIPE_FORMAT_R16G16B16A16_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_SSCALED', 48) +PIPE_FORMAT_R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_UNORM', 49) +PIPE_FORMAT_R8G8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8_UNORM', 50) +PIPE_FORMAT_R8G8B8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_UNORM', 51) +PIPE_FORMAT_B8G8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_UNORM', 52) +PIPE_FORMAT_R8G8B8A8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_UNORM', 53) +PIPE_FORMAT_B8G8R8A8_UNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_UNORM', 54) +PIPE_FORMAT_R8_USCALED = enum_pipe_format.define('PIPE_FORMAT_R8_USCALED', 55) +PIPE_FORMAT_R8G8_USCALED = enum_pipe_format.define('PIPE_FORMAT_R8G8_USCALED', 56) +PIPE_FORMAT_R8G8B8_USCALED = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_USCALED', 57) +PIPE_FORMAT_B8G8R8_USCALED = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_USCALED', 58) +PIPE_FORMAT_R8G8B8A8_USCALED = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_USCALED', 59) +PIPE_FORMAT_B8G8R8A8_USCALED = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_USCALED', 60) +PIPE_FORMAT_A8B8G8R8_USCALED = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_USCALED', 61) +PIPE_FORMAT_R8_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8_SNORM', 62) +PIPE_FORMAT_R8G8_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8_SNORM', 63) +PIPE_FORMAT_R8G8B8_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_SNORM', 64) +PIPE_FORMAT_B8G8R8_SNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_SNORM', 65) +PIPE_FORMAT_R8G8B8A8_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_SNORM', 66) +PIPE_FORMAT_B8G8R8A8_SNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_SNORM', 67) +PIPE_FORMAT_R8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R8_SSCALED', 68) +PIPE_FORMAT_R8G8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R8G8_SSCALED', 69) +PIPE_FORMAT_R8G8B8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_SSCALED', 70) +PIPE_FORMAT_B8G8R8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_SSCALED', 71) +PIPE_FORMAT_R8G8B8A8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_SSCALED', 72) +PIPE_FORMAT_B8G8R8A8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_SSCALED', 73) +PIPE_FORMAT_A8B8G8R8_SSCALED = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_SSCALED', 74) +PIPE_FORMAT_A8R8G8B8_UNORM = enum_pipe_format.define('PIPE_FORMAT_A8R8G8B8_UNORM', 75) +PIPE_FORMAT_R32_FIXED = enum_pipe_format.define('PIPE_FORMAT_R32_FIXED', 76) +PIPE_FORMAT_R32G32_FIXED = enum_pipe_format.define('PIPE_FORMAT_R32G32_FIXED', 77) +PIPE_FORMAT_R32G32B32_FIXED = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_FIXED', 78) +PIPE_FORMAT_R32G32B32A32_FIXED = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_FIXED', 79) +PIPE_FORMAT_R16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R16_FLOAT', 80) +PIPE_FORMAT_R16G16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R16G16_FLOAT', 81) +PIPE_FORMAT_R16G16B16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_FLOAT', 82) +PIPE_FORMAT_R16G16B16A16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_FLOAT', 83) +PIPE_FORMAT_R8_UINT = enum_pipe_format.define('PIPE_FORMAT_R8_UINT', 84) +PIPE_FORMAT_R8G8_UINT = enum_pipe_format.define('PIPE_FORMAT_R8G8_UINT', 85) +PIPE_FORMAT_R8G8B8_UINT = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_UINT', 86) +PIPE_FORMAT_B8G8R8_UINT = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_UINT', 87) +PIPE_FORMAT_R8G8B8A8_UINT = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_UINT', 88) +PIPE_FORMAT_B8G8R8A8_UINT = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_UINT', 89) +PIPE_FORMAT_R8_SINT = enum_pipe_format.define('PIPE_FORMAT_R8_SINT', 90) +PIPE_FORMAT_R8G8_SINT = enum_pipe_format.define('PIPE_FORMAT_R8G8_SINT', 91) +PIPE_FORMAT_R8G8B8_SINT = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_SINT', 92) +PIPE_FORMAT_B8G8R8_SINT = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_SINT', 93) +PIPE_FORMAT_R8G8B8A8_SINT = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_SINT', 94) +PIPE_FORMAT_B8G8R8A8_SINT = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_SINT', 95) +PIPE_FORMAT_R16_UINT = enum_pipe_format.define('PIPE_FORMAT_R16_UINT', 96) +PIPE_FORMAT_R16G16_UINT = enum_pipe_format.define('PIPE_FORMAT_R16G16_UINT', 97) +PIPE_FORMAT_R16G16B16_UINT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_UINT', 98) +PIPE_FORMAT_R16G16B16A16_UINT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_UINT', 99) +PIPE_FORMAT_R16_SINT = enum_pipe_format.define('PIPE_FORMAT_R16_SINT', 100) +PIPE_FORMAT_R16G16_SINT = enum_pipe_format.define('PIPE_FORMAT_R16G16_SINT', 101) +PIPE_FORMAT_R16G16B16_SINT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16_SINT', 102) +PIPE_FORMAT_R16G16B16A16_SINT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16A16_SINT', 103) +PIPE_FORMAT_R32_UINT = enum_pipe_format.define('PIPE_FORMAT_R32_UINT', 104) +PIPE_FORMAT_R32G32_UINT = enum_pipe_format.define('PIPE_FORMAT_R32G32_UINT', 105) +PIPE_FORMAT_R32G32B32_UINT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_UINT', 106) +PIPE_FORMAT_R32G32B32A32_UINT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_UINT', 107) +PIPE_FORMAT_R32_SINT = enum_pipe_format.define('PIPE_FORMAT_R32_SINT', 108) +PIPE_FORMAT_R32G32_SINT = enum_pipe_format.define('PIPE_FORMAT_R32G32_SINT', 109) +PIPE_FORMAT_R32G32B32_SINT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32_SINT', 110) +PIPE_FORMAT_R32G32B32A32_SINT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32A32_SINT', 111) +PIPE_FORMAT_R10G10B10A2_UNORM = enum_pipe_format.define('PIPE_FORMAT_R10G10B10A2_UNORM', 112) +PIPE_FORMAT_R10G10B10A2_SNORM = enum_pipe_format.define('PIPE_FORMAT_R10G10B10A2_SNORM', 113) +PIPE_FORMAT_R10G10B10A2_USCALED = enum_pipe_format.define('PIPE_FORMAT_R10G10B10A2_USCALED', 114) +PIPE_FORMAT_R10G10B10A2_SSCALED = enum_pipe_format.define('PIPE_FORMAT_R10G10B10A2_SSCALED', 115) +PIPE_FORMAT_B10G10R10A2_UNORM = enum_pipe_format.define('PIPE_FORMAT_B10G10R10A2_UNORM', 116) +PIPE_FORMAT_B10G10R10A2_SNORM = enum_pipe_format.define('PIPE_FORMAT_B10G10R10A2_SNORM', 117) +PIPE_FORMAT_B10G10R10A2_USCALED = enum_pipe_format.define('PIPE_FORMAT_B10G10R10A2_USCALED', 118) +PIPE_FORMAT_B10G10R10A2_SSCALED = enum_pipe_format.define('PIPE_FORMAT_B10G10R10A2_SSCALED', 119) +PIPE_FORMAT_R11G11B10_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R11G11B10_FLOAT', 120) +PIPE_FORMAT_R10G10B10A2_UINT = enum_pipe_format.define('PIPE_FORMAT_R10G10B10A2_UINT', 121) +PIPE_FORMAT_R10G10B10A2_SINT = enum_pipe_format.define('PIPE_FORMAT_R10G10B10A2_SINT', 122) +PIPE_FORMAT_B10G10R10A2_UINT = enum_pipe_format.define('PIPE_FORMAT_B10G10R10A2_UINT', 123) +PIPE_FORMAT_B10G10R10A2_SINT = enum_pipe_format.define('PIPE_FORMAT_B10G10R10A2_SINT', 124) +PIPE_FORMAT_B8G8R8X8_UNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8R8X8_UNORM', 125) +PIPE_FORMAT_X8B8G8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_X8B8G8R8_UNORM', 126) +PIPE_FORMAT_X8R8G8B8_UNORM = enum_pipe_format.define('PIPE_FORMAT_X8R8G8B8_UNORM', 127) +PIPE_FORMAT_B5G5R5A1_UNORM = enum_pipe_format.define('PIPE_FORMAT_B5G5R5A1_UNORM', 128) +PIPE_FORMAT_R4G4B4A4_UNORM = enum_pipe_format.define('PIPE_FORMAT_R4G4B4A4_UNORM', 129) +PIPE_FORMAT_B4G4R4A4_UNORM = enum_pipe_format.define('PIPE_FORMAT_B4G4R4A4_UNORM', 130) +PIPE_FORMAT_R5G6B5_UNORM = enum_pipe_format.define('PIPE_FORMAT_R5G6B5_UNORM', 131) +PIPE_FORMAT_B5G6R5_UNORM = enum_pipe_format.define('PIPE_FORMAT_B5G6R5_UNORM', 132) +PIPE_FORMAT_L8_UNORM = enum_pipe_format.define('PIPE_FORMAT_L8_UNORM', 133) +PIPE_FORMAT_A8_UNORM = enum_pipe_format.define('PIPE_FORMAT_A8_UNORM', 134) +PIPE_FORMAT_I8_UNORM = enum_pipe_format.define('PIPE_FORMAT_I8_UNORM', 135) +PIPE_FORMAT_L8A8_UNORM = enum_pipe_format.define('PIPE_FORMAT_L8A8_UNORM', 136) +PIPE_FORMAT_L16_UNORM = enum_pipe_format.define('PIPE_FORMAT_L16_UNORM', 137) +PIPE_FORMAT_UYVY = enum_pipe_format.define('PIPE_FORMAT_UYVY', 138) +PIPE_FORMAT_VYUY = enum_pipe_format.define('PIPE_FORMAT_VYUY', 139) +PIPE_FORMAT_YUYV = enum_pipe_format.define('PIPE_FORMAT_YUYV', 140) +PIPE_FORMAT_YVYU = enum_pipe_format.define('PIPE_FORMAT_YVYU', 141) +PIPE_FORMAT_Z16_UNORM = enum_pipe_format.define('PIPE_FORMAT_Z16_UNORM', 142) +PIPE_FORMAT_Z16_UNORM_S8_UINT = enum_pipe_format.define('PIPE_FORMAT_Z16_UNORM_S8_UINT', 143) +PIPE_FORMAT_Z32_UNORM = enum_pipe_format.define('PIPE_FORMAT_Z32_UNORM', 144) +PIPE_FORMAT_Z32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_Z32_FLOAT', 145) +PIPE_FORMAT_Z24_UNORM_S8_UINT = enum_pipe_format.define('PIPE_FORMAT_Z24_UNORM_S8_UINT', 146) +PIPE_FORMAT_S8_UINT_Z24_UNORM = enum_pipe_format.define('PIPE_FORMAT_S8_UINT_Z24_UNORM', 147) +PIPE_FORMAT_Z24X8_UNORM = enum_pipe_format.define('PIPE_FORMAT_Z24X8_UNORM', 148) +PIPE_FORMAT_X8Z24_UNORM = enum_pipe_format.define('PIPE_FORMAT_X8Z24_UNORM', 149) +PIPE_FORMAT_S8_UINT = enum_pipe_format.define('PIPE_FORMAT_S8_UINT', 150) +PIPE_FORMAT_L8_SRGB = enum_pipe_format.define('PIPE_FORMAT_L8_SRGB', 151) +PIPE_FORMAT_R8_SRGB = enum_pipe_format.define('PIPE_FORMAT_R8_SRGB', 152) +PIPE_FORMAT_L8A8_SRGB = enum_pipe_format.define('PIPE_FORMAT_L8A8_SRGB', 153) +PIPE_FORMAT_R8G8_SRGB = enum_pipe_format.define('PIPE_FORMAT_R8G8_SRGB', 154) +PIPE_FORMAT_R8G8B8_SRGB = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_SRGB', 155) +PIPE_FORMAT_B8G8R8_SRGB = enum_pipe_format.define('PIPE_FORMAT_B8G8R8_SRGB', 156) +PIPE_FORMAT_A8B8G8R8_SRGB = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_SRGB', 157) +PIPE_FORMAT_X8B8G8R8_SRGB = enum_pipe_format.define('PIPE_FORMAT_X8B8G8R8_SRGB', 158) +PIPE_FORMAT_B8G8R8A8_SRGB = enum_pipe_format.define('PIPE_FORMAT_B8G8R8A8_SRGB', 159) +PIPE_FORMAT_B8G8R8X8_SRGB = enum_pipe_format.define('PIPE_FORMAT_B8G8R8X8_SRGB', 160) +PIPE_FORMAT_A8R8G8B8_SRGB = enum_pipe_format.define('PIPE_FORMAT_A8R8G8B8_SRGB', 161) +PIPE_FORMAT_X8R8G8B8_SRGB = enum_pipe_format.define('PIPE_FORMAT_X8R8G8B8_SRGB', 162) +PIPE_FORMAT_R8G8B8A8_SRGB = enum_pipe_format.define('PIPE_FORMAT_R8G8B8A8_SRGB', 163) +PIPE_FORMAT_DXT1_RGB = enum_pipe_format.define('PIPE_FORMAT_DXT1_RGB', 164) +PIPE_FORMAT_DXT1_RGBA = enum_pipe_format.define('PIPE_FORMAT_DXT1_RGBA', 165) +PIPE_FORMAT_DXT3_RGBA = enum_pipe_format.define('PIPE_FORMAT_DXT3_RGBA', 166) +PIPE_FORMAT_DXT5_RGBA = enum_pipe_format.define('PIPE_FORMAT_DXT5_RGBA', 167) +PIPE_FORMAT_DXT1_SRGB = enum_pipe_format.define('PIPE_FORMAT_DXT1_SRGB', 168) +PIPE_FORMAT_DXT1_SRGBA = enum_pipe_format.define('PIPE_FORMAT_DXT1_SRGBA', 169) +PIPE_FORMAT_DXT3_SRGBA = enum_pipe_format.define('PIPE_FORMAT_DXT3_SRGBA', 170) +PIPE_FORMAT_DXT5_SRGBA = enum_pipe_format.define('PIPE_FORMAT_DXT5_SRGBA', 171) +PIPE_FORMAT_RGTC1_UNORM = enum_pipe_format.define('PIPE_FORMAT_RGTC1_UNORM', 172) +PIPE_FORMAT_RGTC1_SNORM = enum_pipe_format.define('PIPE_FORMAT_RGTC1_SNORM', 173) +PIPE_FORMAT_RGTC2_UNORM = enum_pipe_format.define('PIPE_FORMAT_RGTC2_UNORM', 174) +PIPE_FORMAT_RGTC2_SNORM = enum_pipe_format.define('PIPE_FORMAT_RGTC2_SNORM', 175) +PIPE_FORMAT_R8G8_B8G8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8_B8G8_UNORM', 176) +PIPE_FORMAT_G8R8_G8B8_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8R8_G8B8_UNORM', 177) +PIPE_FORMAT_X6G10_X6B10X6R10_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_X6G10_X6B10X6R10_420_UNORM', 178) +PIPE_FORMAT_X4G12_X4B12X4R12_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_X4G12_X4B12X4R12_420_UNORM', 179) +PIPE_FORMAT_X6R10_UNORM = enum_pipe_format.define('PIPE_FORMAT_X6R10_UNORM', 180) +PIPE_FORMAT_X6R10X6G10_UNORM = enum_pipe_format.define('PIPE_FORMAT_X6R10X6G10_UNORM', 181) +PIPE_FORMAT_X4R12_UNORM = enum_pipe_format.define('PIPE_FORMAT_X4R12_UNORM', 182) +PIPE_FORMAT_X4R12X4G12_UNORM = enum_pipe_format.define('PIPE_FORMAT_X4R12X4G12_UNORM', 183) +PIPE_FORMAT_R8SG8SB8UX8U_NORM = enum_pipe_format.define('PIPE_FORMAT_R8SG8SB8UX8U_NORM', 184) +PIPE_FORMAT_R5SG5SB6U_NORM = enum_pipe_format.define('PIPE_FORMAT_R5SG5SB6U_NORM', 185) +PIPE_FORMAT_A8B8G8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_UNORM', 186) +PIPE_FORMAT_B5G5R5X1_UNORM = enum_pipe_format.define('PIPE_FORMAT_B5G5R5X1_UNORM', 187) +PIPE_FORMAT_R9G9B9E5_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R9G9B9E5_FLOAT', 188) +PIPE_FORMAT_Z32_FLOAT_S8X24_UINT = enum_pipe_format.define('PIPE_FORMAT_Z32_FLOAT_S8X24_UINT', 189) +PIPE_FORMAT_R1_UNORM = enum_pipe_format.define('PIPE_FORMAT_R1_UNORM', 190) +PIPE_FORMAT_R10G10B10X2_USCALED = enum_pipe_format.define('PIPE_FORMAT_R10G10B10X2_USCALED', 191) +PIPE_FORMAT_R10G10B10X2_SNORM = enum_pipe_format.define('PIPE_FORMAT_R10G10B10X2_SNORM', 192) +PIPE_FORMAT_L4A4_UNORM = enum_pipe_format.define('PIPE_FORMAT_L4A4_UNORM', 193) +PIPE_FORMAT_A2R10G10B10_UNORM = enum_pipe_format.define('PIPE_FORMAT_A2R10G10B10_UNORM', 194) +PIPE_FORMAT_A2B10G10R10_UNORM = enum_pipe_format.define('PIPE_FORMAT_A2B10G10R10_UNORM', 195) +PIPE_FORMAT_R10SG10SB10SA2U_NORM = enum_pipe_format.define('PIPE_FORMAT_R10SG10SB10SA2U_NORM', 196) +PIPE_FORMAT_R8G8Bx_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8Bx_SNORM', 197) +PIPE_FORMAT_R8G8B8X8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8B8X8_UNORM', 198) +PIPE_FORMAT_B4G4R4X4_UNORM = enum_pipe_format.define('PIPE_FORMAT_B4G4R4X4_UNORM', 199) +PIPE_FORMAT_X24S8_UINT = enum_pipe_format.define('PIPE_FORMAT_X24S8_UINT', 200) +PIPE_FORMAT_S8X24_UINT = enum_pipe_format.define('PIPE_FORMAT_S8X24_UINT', 201) +PIPE_FORMAT_X32_S8X24_UINT = enum_pipe_format.define('PIPE_FORMAT_X32_S8X24_UINT', 202) +PIPE_FORMAT_R3G3B2_UNORM = enum_pipe_format.define('PIPE_FORMAT_R3G3B2_UNORM', 203) +PIPE_FORMAT_B2G3R3_UNORM = enum_pipe_format.define('PIPE_FORMAT_B2G3R3_UNORM', 204) +PIPE_FORMAT_L16A16_UNORM = enum_pipe_format.define('PIPE_FORMAT_L16A16_UNORM', 205) +PIPE_FORMAT_A16_UNORM = enum_pipe_format.define('PIPE_FORMAT_A16_UNORM', 206) +PIPE_FORMAT_I16_UNORM = enum_pipe_format.define('PIPE_FORMAT_I16_UNORM', 207) +PIPE_FORMAT_LATC1_UNORM = enum_pipe_format.define('PIPE_FORMAT_LATC1_UNORM', 208) +PIPE_FORMAT_LATC1_SNORM = enum_pipe_format.define('PIPE_FORMAT_LATC1_SNORM', 209) +PIPE_FORMAT_LATC2_UNORM = enum_pipe_format.define('PIPE_FORMAT_LATC2_UNORM', 210) +PIPE_FORMAT_LATC2_SNORM = enum_pipe_format.define('PIPE_FORMAT_LATC2_SNORM', 211) +PIPE_FORMAT_A8_SNORM = enum_pipe_format.define('PIPE_FORMAT_A8_SNORM', 212) +PIPE_FORMAT_L8_SNORM = enum_pipe_format.define('PIPE_FORMAT_L8_SNORM', 213) +PIPE_FORMAT_L8A8_SNORM = enum_pipe_format.define('PIPE_FORMAT_L8A8_SNORM', 214) +PIPE_FORMAT_I8_SNORM = enum_pipe_format.define('PIPE_FORMAT_I8_SNORM', 215) +PIPE_FORMAT_A16_SNORM = enum_pipe_format.define('PIPE_FORMAT_A16_SNORM', 216) +PIPE_FORMAT_L16_SNORM = enum_pipe_format.define('PIPE_FORMAT_L16_SNORM', 217) +PIPE_FORMAT_L16A16_SNORM = enum_pipe_format.define('PIPE_FORMAT_L16A16_SNORM', 218) +PIPE_FORMAT_I16_SNORM = enum_pipe_format.define('PIPE_FORMAT_I16_SNORM', 219) +PIPE_FORMAT_A16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_A16_FLOAT', 220) +PIPE_FORMAT_L16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_L16_FLOAT', 221) +PIPE_FORMAT_L16A16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_L16A16_FLOAT', 222) +PIPE_FORMAT_I16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_I16_FLOAT', 223) +PIPE_FORMAT_A32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_A32_FLOAT', 224) +PIPE_FORMAT_L32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_L32_FLOAT', 225) +PIPE_FORMAT_L32A32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_L32A32_FLOAT', 226) +PIPE_FORMAT_I32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_I32_FLOAT', 227) +PIPE_FORMAT_YV12 = enum_pipe_format.define('PIPE_FORMAT_YV12', 228) +PIPE_FORMAT_YV16 = enum_pipe_format.define('PIPE_FORMAT_YV16', 229) +PIPE_FORMAT_IYUV = enum_pipe_format.define('PIPE_FORMAT_IYUV', 230) +PIPE_FORMAT_NV12 = enum_pipe_format.define('PIPE_FORMAT_NV12', 231) +PIPE_FORMAT_NV21 = enum_pipe_format.define('PIPE_FORMAT_NV21', 232) +PIPE_FORMAT_NV16 = enum_pipe_format.define('PIPE_FORMAT_NV16', 233) +PIPE_FORMAT_NV15 = enum_pipe_format.define('PIPE_FORMAT_NV15', 234) +PIPE_FORMAT_NV20 = enum_pipe_format.define('PIPE_FORMAT_NV20', 235) +PIPE_FORMAT_Y8_400_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y8_400_UNORM', 236) +PIPE_FORMAT_Y8_U8_V8_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y8_U8_V8_422_UNORM', 237) +PIPE_FORMAT_Y8_U8_V8_444_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y8_U8_V8_444_UNORM', 238) +PIPE_FORMAT_Y8_U8_V8_440_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y8_U8_V8_440_UNORM', 239) +PIPE_FORMAT_Y10X6_U10X6_V10X6_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y10X6_U10X6_V10X6_420_UNORM', 240) +PIPE_FORMAT_Y10X6_U10X6_V10X6_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y10X6_U10X6_V10X6_422_UNORM', 241) +PIPE_FORMAT_Y10X6_U10X6_V10X6_444_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y10X6_U10X6_V10X6_444_UNORM', 242) +PIPE_FORMAT_Y12X4_U12X4_V12X4_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y12X4_U12X4_V12X4_420_UNORM', 243) +PIPE_FORMAT_Y12X4_U12X4_V12X4_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y12X4_U12X4_V12X4_422_UNORM', 244) +PIPE_FORMAT_Y12X4_U12X4_V12X4_444_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y12X4_U12X4_V12X4_444_UNORM', 245) +PIPE_FORMAT_Y16_U16_V16_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y16_U16_V16_420_UNORM', 246) +PIPE_FORMAT_Y16_U16_V16_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y16_U16_V16_422_UNORM', 247) +PIPE_FORMAT_Y16_U16V16_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y16_U16V16_422_UNORM', 248) +PIPE_FORMAT_Y16_U16_V16_444_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y16_U16_V16_444_UNORM', 249) +PIPE_FORMAT_Y8U8V8_420_UNORM_PACKED = enum_pipe_format.define('PIPE_FORMAT_Y8U8V8_420_UNORM_PACKED', 250) +PIPE_FORMAT_Y10U10V10_420_UNORM_PACKED = enum_pipe_format.define('PIPE_FORMAT_Y10U10V10_420_UNORM_PACKED', 251) +PIPE_FORMAT_A4R4_UNORM = enum_pipe_format.define('PIPE_FORMAT_A4R4_UNORM', 252) +PIPE_FORMAT_R4A4_UNORM = enum_pipe_format.define('PIPE_FORMAT_R4A4_UNORM', 253) +PIPE_FORMAT_R8A8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8A8_UNORM', 254) +PIPE_FORMAT_A8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_A8R8_UNORM', 255) +PIPE_FORMAT_A8_UINT = enum_pipe_format.define('PIPE_FORMAT_A8_UINT', 256) +PIPE_FORMAT_I8_UINT = enum_pipe_format.define('PIPE_FORMAT_I8_UINT', 257) +PIPE_FORMAT_L8_UINT = enum_pipe_format.define('PIPE_FORMAT_L8_UINT', 258) +PIPE_FORMAT_L8A8_UINT = enum_pipe_format.define('PIPE_FORMAT_L8A8_UINT', 259) +PIPE_FORMAT_A8_SINT = enum_pipe_format.define('PIPE_FORMAT_A8_SINT', 260) +PIPE_FORMAT_I8_SINT = enum_pipe_format.define('PIPE_FORMAT_I8_SINT', 261) +PIPE_FORMAT_L8_SINT = enum_pipe_format.define('PIPE_FORMAT_L8_SINT', 262) +PIPE_FORMAT_L8A8_SINT = enum_pipe_format.define('PIPE_FORMAT_L8A8_SINT', 263) +PIPE_FORMAT_A16_UINT = enum_pipe_format.define('PIPE_FORMAT_A16_UINT', 264) +PIPE_FORMAT_I16_UINT = enum_pipe_format.define('PIPE_FORMAT_I16_UINT', 265) +PIPE_FORMAT_L16_UINT = enum_pipe_format.define('PIPE_FORMAT_L16_UINT', 266) +PIPE_FORMAT_L16A16_UINT = enum_pipe_format.define('PIPE_FORMAT_L16A16_UINT', 267) +PIPE_FORMAT_A16_SINT = enum_pipe_format.define('PIPE_FORMAT_A16_SINT', 268) +PIPE_FORMAT_I16_SINT = enum_pipe_format.define('PIPE_FORMAT_I16_SINT', 269) +PIPE_FORMAT_L16_SINT = enum_pipe_format.define('PIPE_FORMAT_L16_SINT', 270) +PIPE_FORMAT_L16A16_SINT = enum_pipe_format.define('PIPE_FORMAT_L16A16_SINT', 271) +PIPE_FORMAT_A32_UINT = enum_pipe_format.define('PIPE_FORMAT_A32_UINT', 272) +PIPE_FORMAT_I32_UINT = enum_pipe_format.define('PIPE_FORMAT_I32_UINT', 273) +PIPE_FORMAT_L32_UINT = enum_pipe_format.define('PIPE_FORMAT_L32_UINT', 274) +PIPE_FORMAT_L32A32_UINT = enum_pipe_format.define('PIPE_FORMAT_L32A32_UINT', 275) +PIPE_FORMAT_A32_SINT = enum_pipe_format.define('PIPE_FORMAT_A32_SINT', 276) +PIPE_FORMAT_I32_SINT = enum_pipe_format.define('PIPE_FORMAT_I32_SINT', 277) +PIPE_FORMAT_L32_SINT = enum_pipe_format.define('PIPE_FORMAT_L32_SINT', 278) +PIPE_FORMAT_L32A32_SINT = enum_pipe_format.define('PIPE_FORMAT_L32A32_SINT', 279) +PIPE_FORMAT_A8R8G8B8_UINT = enum_pipe_format.define('PIPE_FORMAT_A8R8G8B8_UINT', 280) +PIPE_FORMAT_A8B8G8R8_UINT = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_UINT', 281) +PIPE_FORMAT_A2R10G10B10_UINT = enum_pipe_format.define('PIPE_FORMAT_A2R10G10B10_UINT', 282) +PIPE_FORMAT_A2B10G10R10_UINT = enum_pipe_format.define('PIPE_FORMAT_A2B10G10R10_UINT', 283) +PIPE_FORMAT_R5G6B5_UINT = enum_pipe_format.define('PIPE_FORMAT_R5G6B5_UINT', 284) +PIPE_FORMAT_B5G6R5_UINT = enum_pipe_format.define('PIPE_FORMAT_B5G6R5_UINT', 285) +PIPE_FORMAT_R5G5B5A1_UINT = enum_pipe_format.define('PIPE_FORMAT_R5G5B5A1_UINT', 286) +PIPE_FORMAT_B5G5R5A1_UINT = enum_pipe_format.define('PIPE_FORMAT_B5G5R5A1_UINT', 287) +PIPE_FORMAT_A1R5G5B5_UINT = enum_pipe_format.define('PIPE_FORMAT_A1R5G5B5_UINT', 288) +PIPE_FORMAT_A1B5G5R5_UINT = enum_pipe_format.define('PIPE_FORMAT_A1B5G5R5_UINT', 289) +PIPE_FORMAT_R4G4B4A4_UINT = enum_pipe_format.define('PIPE_FORMAT_R4G4B4A4_UINT', 290) +PIPE_FORMAT_B4G4R4A4_UINT = enum_pipe_format.define('PIPE_FORMAT_B4G4R4A4_UINT', 291) +PIPE_FORMAT_A4R4G4B4_UINT = enum_pipe_format.define('PIPE_FORMAT_A4R4G4B4_UINT', 292) +PIPE_FORMAT_A4B4G4R4_UINT = enum_pipe_format.define('PIPE_FORMAT_A4B4G4R4_UINT', 293) +PIPE_FORMAT_R3G3B2_UINT = enum_pipe_format.define('PIPE_FORMAT_R3G3B2_UINT', 294) +PIPE_FORMAT_B2G3R3_UINT = enum_pipe_format.define('PIPE_FORMAT_B2G3R3_UINT', 295) +PIPE_FORMAT_ETC1_RGB8 = enum_pipe_format.define('PIPE_FORMAT_ETC1_RGB8', 296) +PIPE_FORMAT_R8G8_R8B8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8_R8B8_UNORM', 297) +PIPE_FORMAT_R8B8_R8G8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8B8_R8G8_UNORM', 298) +PIPE_FORMAT_G8R8_B8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8R8_B8R8_UNORM', 299) +PIPE_FORMAT_B8R8_G8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_B8R8_G8R8_UNORM', 300) +PIPE_FORMAT_G8B8_G8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8B8_G8R8_UNORM', 301) +PIPE_FORMAT_B8G8_R8G8_UNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8_R8G8_UNORM', 302) +PIPE_FORMAT_R8G8B8X8_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8G8B8X8_SNORM', 303) +PIPE_FORMAT_R8G8B8X8_SRGB = enum_pipe_format.define('PIPE_FORMAT_R8G8B8X8_SRGB', 304) +PIPE_FORMAT_R8G8B8X8_UINT = enum_pipe_format.define('PIPE_FORMAT_R8G8B8X8_UINT', 305) +PIPE_FORMAT_R8G8B8X8_SINT = enum_pipe_format.define('PIPE_FORMAT_R8G8B8X8_SINT', 306) +PIPE_FORMAT_B10G10R10X2_UNORM = enum_pipe_format.define('PIPE_FORMAT_B10G10R10X2_UNORM', 307) +PIPE_FORMAT_R16G16B16X16_UNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16B16X16_UNORM', 308) +PIPE_FORMAT_R16G16B16X16_SNORM = enum_pipe_format.define('PIPE_FORMAT_R16G16B16X16_SNORM', 309) +PIPE_FORMAT_R16G16B16X16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16X16_FLOAT', 310) +PIPE_FORMAT_R16G16B16X16_UINT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16X16_UINT', 311) +PIPE_FORMAT_R16G16B16X16_SINT = enum_pipe_format.define('PIPE_FORMAT_R16G16B16X16_SINT', 312) +PIPE_FORMAT_R32G32B32X32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32X32_FLOAT', 313) +PIPE_FORMAT_R32G32B32X32_UINT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32X32_UINT', 314) +PIPE_FORMAT_R32G32B32X32_SINT = enum_pipe_format.define('PIPE_FORMAT_R32G32B32X32_SINT', 315) +PIPE_FORMAT_R8A8_SNORM = enum_pipe_format.define('PIPE_FORMAT_R8A8_SNORM', 316) +PIPE_FORMAT_R16A16_UNORM = enum_pipe_format.define('PIPE_FORMAT_R16A16_UNORM', 317) +PIPE_FORMAT_R16A16_SNORM = enum_pipe_format.define('PIPE_FORMAT_R16A16_SNORM', 318) +PIPE_FORMAT_R16A16_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R16A16_FLOAT', 319) +PIPE_FORMAT_R32A32_FLOAT = enum_pipe_format.define('PIPE_FORMAT_R32A32_FLOAT', 320) +PIPE_FORMAT_R8A8_UINT = enum_pipe_format.define('PIPE_FORMAT_R8A8_UINT', 321) +PIPE_FORMAT_R8A8_SINT = enum_pipe_format.define('PIPE_FORMAT_R8A8_SINT', 322) +PIPE_FORMAT_R16A16_UINT = enum_pipe_format.define('PIPE_FORMAT_R16A16_UINT', 323) +PIPE_FORMAT_R16A16_SINT = enum_pipe_format.define('PIPE_FORMAT_R16A16_SINT', 324) +PIPE_FORMAT_R32A32_UINT = enum_pipe_format.define('PIPE_FORMAT_R32A32_UINT', 325) +PIPE_FORMAT_R32A32_SINT = enum_pipe_format.define('PIPE_FORMAT_R32A32_SINT', 326) +PIPE_FORMAT_B5G6R5_SRGB = enum_pipe_format.define('PIPE_FORMAT_B5G6R5_SRGB', 327) +PIPE_FORMAT_BPTC_RGBA_UNORM = enum_pipe_format.define('PIPE_FORMAT_BPTC_RGBA_UNORM', 328) +PIPE_FORMAT_BPTC_SRGBA = enum_pipe_format.define('PIPE_FORMAT_BPTC_SRGBA', 329) +PIPE_FORMAT_BPTC_RGB_FLOAT = enum_pipe_format.define('PIPE_FORMAT_BPTC_RGB_FLOAT', 330) +PIPE_FORMAT_BPTC_RGB_UFLOAT = enum_pipe_format.define('PIPE_FORMAT_BPTC_RGB_UFLOAT', 331) +PIPE_FORMAT_G8R8_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8R8_UNORM', 332) +PIPE_FORMAT_G8R8_SNORM = enum_pipe_format.define('PIPE_FORMAT_G8R8_SNORM', 333) +PIPE_FORMAT_G16R16_UNORM = enum_pipe_format.define('PIPE_FORMAT_G16R16_UNORM', 334) +PIPE_FORMAT_G16R16_SNORM = enum_pipe_format.define('PIPE_FORMAT_G16R16_SNORM', 335) +PIPE_FORMAT_A8B8G8R8_SNORM = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_SNORM', 336) +PIPE_FORMAT_X8B8G8R8_SNORM = enum_pipe_format.define('PIPE_FORMAT_X8B8G8R8_SNORM', 337) +PIPE_FORMAT_ETC2_RGB8 = enum_pipe_format.define('PIPE_FORMAT_ETC2_RGB8', 338) +PIPE_FORMAT_ETC2_SRGB8 = enum_pipe_format.define('PIPE_FORMAT_ETC2_SRGB8', 339) +PIPE_FORMAT_ETC2_RGB8A1 = enum_pipe_format.define('PIPE_FORMAT_ETC2_RGB8A1', 340) +PIPE_FORMAT_ETC2_SRGB8A1 = enum_pipe_format.define('PIPE_FORMAT_ETC2_SRGB8A1', 341) +PIPE_FORMAT_ETC2_RGBA8 = enum_pipe_format.define('PIPE_FORMAT_ETC2_RGBA8', 342) +PIPE_FORMAT_ETC2_SRGBA8 = enum_pipe_format.define('PIPE_FORMAT_ETC2_SRGBA8', 343) +PIPE_FORMAT_ETC2_R11_UNORM = enum_pipe_format.define('PIPE_FORMAT_ETC2_R11_UNORM', 344) +PIPE_FORMAT_ETC2_R11_SNORM = enum_pipe_format.define('PIPE_FORMAT_ETC2_R11_SNORM', 345) +PIPE_FORMAT_ETC2_RG11_UNORM = enum_pipe_format.define('PIPE_FORMAT_ETC2_RG11_UNORM', 346) +PIPE_FORMAT_ETC2_RG11_SNORM = enum_pipe_format.define('PIPE_FORMAT_ETC2_RG11_SNORM', 347) +PIPE_FORMAT_ASTC_4x4 = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4', 348) +PIPE_FORMAT_ASTC_5x4 = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x4', 349) +PIPE_FORMAT_ASTC_5x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5', 350) +PIPE_FORMAT_ASTC_6x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x5', 351) +PIPE_FORMAT_ASTC_6x6 = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6', 352) +PIPE_FORMAT_ASTC_8x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x5', 353) +PIPE_FORMAT_ASTC_8x6 = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x6', 354) +PIPE_FORMAT_ASTC_8x8 = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x8', 355) +PIPE_FORMAT_ASTC_10x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x5', 356) +PIPE_FORMAT_ASTC_10x6 = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x6', 357) +PIPE_FORMAT_ASTC_10x8 = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x8', 358) +PIPE_FORMAT_ASTC_10x10 = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x10', 359) +PIPE_FORMAT_ASTC_12x10 = enum_pipe_format.define('PIPE_FORMAT_ASTC_12x10', 360) +PIPE_FORMAT_ASTC_12x12 = enum_pipe_format.define('PIPE_FORMAT_ASTC_12x12', 361) +PIPE_FORMAT_ASTC_4x4_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4_SRGB', 362) +PIPE_FORMAT_ASTC_5x4_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x4_SRGB', 363) +PIPE_FORMAT_ASTC_5x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5_SRGB', 364) +PIPE_FORMAT_ASTC_6x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x5_SRGB', 365) +PIPE_FORMAT_ASTC_6x6_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6_SRGB', 366) +PIPE_FORMAT_ASTC_8x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x5_SRGB', 367) +PIPE_FORMAT_ASTC_8x6_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x6_SRGB', 368) +PIPE_FORMAT_ASTC_8x8_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x8_SRGB', 369) +PIPE_FORMAT_ASTC_10x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x5_SRGB', 370) +PIPE_FORMAT_ASTC_10x6_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x6_SRGB', 371) +PIPE_FORMAT_ASTC_10x8_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x8_SRGB', 372) +PIPE_FORMAT_ASTC_10x10_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x10_SRGB', 373) +PIPE_FORMAT_ASTC_12x10_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_12x10_SRGB', 374) +PIPE_FORMAT_ASTC_12x12_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_12x12_SRGB', 375) +PIPE_FORMAT_ASTC_3x3x3 = enum_pipe_format.define('PIPE_FORMAT_ASTC_3x3x3', 376) +PIPE_FORMAT_ASTC_4x3x3 = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x3x3', 377) +PIPE_FORMAT_ASTC_4x4x3 = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4x3', 378) +PIPE_FORMAT_ASTC_4x4x4 = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4x4', 379) +PIPE_FORMAT_ASTC_5x4x4 = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x4x4', 380) +PIPE_FORMAT_ASTC_5x5x4 = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5x4', 381) +PIPE_FORMAT_ASTC_5x5x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5x5', 382) +PIPE_FORMAT_ASTC_6x5x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x5x5', 383) +PIPE_FORMAT_ASTC_6x6x5 = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6x5', 384) +PIPE_FORMAT_ASTC_6x6x6 = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6x6', 385) +PIPE_FORMAT_ASTC_3x3x3_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_3x3x3_SRGB', 386) +PIPE_FORMAT_ASTC_4x3x3_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x3x3_SRGB', 387) +PIPE_FORMAT_ASTC_4x4x3_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4x3_SRGB', 388) +PIPE_FORMAT_ASTC_4x4x4_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4x4_SRGB', 389) +PIPE_FORMAT_ASTC_5x4x4_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x4x4_SRGB', 390) +PIPE_FORMAT_ASTC_5x5x4_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5x4_SRGB', 391) +PIPE_FORMAT_ASTC_5x5x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5x5_SRGB', 392) +PIPE_FORMAT_ASTC_6x5x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x5x5_SRGB', 393) +PIPE_FORMAT_ASTC_6x6x5_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6x5_SRGB', 394) +PIPE_FORMAT_ASTC_6x6x6_SRGB = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6x6_SRGB', 395) +PIPE_FORMAT_ASTC_4x4_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_4x4_FLOAT', 396) +PIPE_FORMAT_ASTC_5x4_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x4_FLOAT', 397) +PIPE_FORMAT_ASTC_5x5_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_5x5_FLOAT', 398) +PIPE_FORMAT_ASTC_6x5_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x5_FLOAT', 399) +PIPE_FORMAT_ASTC_6x6_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_6x6_FLOAT', 400) +PIPE_FORMAT_ASTC_8x5_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x5_FLOAT', 401) +PIPE_FORMAT_ASTC_8x6_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x6_FLOAT', 402) +PIPE_FORMAT_ASTC_8x8_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_8x8_FLOAT', 403) +PIPE_FORMAT_ASTC_10x5_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x5_FLOAT', 404) +PIPE_FORMAT_ASTC_10x6_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x6_FLOAT', 405) +PIPE_FORMAT_ASTC_10x8_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x8_FLOAT', 406) +PIPE_FORMAT_ASTC_10x10_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_10x10_FLOAT', 407) +PIPE_FORMAT_ASTC_12x10_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_12x10_FLOAT', 408) +PIPE_FORMAT_ASTC_12x12_FLOAT = enum_pipe_format.define('PIPE_FORMAT_ASTC_12x12_FLOAT', 409) +PIPE_FORMAT_FXT1_RGB = enum_pipe_format.define('PIPE_FORMAT_FXT1_RGB', 410) +PIPE_FORMAT_FXT1_RGBA = enum_pipe_format.define('PIPE_FORMAT_FXT1_RGBA', 411) +PIPE_FORMAT_P010 = enum_pipe_format.define('PIPE_FORMAT_P010', 412) +PIPE_FORMAT_P012 = enum_pipe_format.define('PIPE_FORMAT_P012', 413) +PIPE_FORMAT_P016 = enum_pipe_format.define('PIPE_FORMAT_P016', 414) +PIPE_FORMAT_P030 = enum_pipe_format.define('PIPE_FORMAT_P030', 415) +PIPE_FORMAT_Y210 = enum_pipe_format.define('PIPE_FORMAT_Y210', 416) +PIPE_FORMAT_Y212 = enum_pipe_format.define('PIPE_FORMAT_Y212', 417) +PIPE_FORMAT_Y216 = enum_pipe_format.define('PIPE_FORMAT_Y216', 418) +PIPE_FORMAT_Y410 = enum_pipe_format.define('PIPE_FORMAT_Y410', 419) +PIPE_FORMAT_Y412 = enum_pipe_format.define('PIPE_FORMAT_Y412', 420) +PIPE_FORMAT_Y416 = enum_pipe_format.define('PIPE_FORMAT_Y416', 421) +PIPE_FORMAT_R10G10B10X2_UNORM = enum_pipe_format.define('PIPE_FORMAT_R10G10B10X2_UNORM', 422) +PIPE_FORMAT_A1R5G5B5_UNORM = enum_pipe_format.define('PIPE_FORMAT_A1R5G5B5_UNORM', 423) +PIPE_FORMAT_A1B5G5R5_UNORM = enum_pipe_format.define('PIPE_FORMAT_A1B5G5R5_UNORM', 424) +PIPE_FORMAT_X1B5G5R5_UNORM = enum_pipe_format.define('PIPE_FORMAT_X1B5G5R5_UNORM', 425) +PIPE_FORMAT_R5G5B5A1_UNORM = enum_pipe_format.define('PIPE_FORMAT_R5G5B5A1_UNORM', 426) +PIPE_FORMAT_A4R4G4B4_UNORM = enum_pipe_format.define('PIPE_FORMAT_A4R4G4B4_UNORM', 427) +PIPE_FORMAT_A4B4G4R4_UNORM = enum_pipe_format.define('PIPE_FORMAT_A4B4G4R4_UNORM', 428) +PIPE_FORMAT_G8R8_SINT = enum_pipe_format.define('PIPE_FORMAT_G8R8_SINT', 429) +PIPE_FORMAT_A8B8G8R8_SINT = enum_pipe_format.define('PIPE_FORMAT_A8B8G8R8_SINT', 430) +PIPE_FORMAT_X8B8G8R8_SINT = enum_pipe_format.define('PIPE_FORMAT_X8B8G8R8_SINT', 431) +PIPE_FORMAT_ATC_RGB = enum_pipe_format.define('PIPE_FORMAT_ATC_RGB', 432) +PIPE_FORMAT_ATC_RGBA_EXPLICIT = enum_pipe_format.define('PIPE_FORMAT_ATC_RGBA_EXPLICIT', 433) +PIPE_FORMAT_ATC_RGBA_INTERPOLATED = enum_pipe_format.define('PIPE_FORMAT_ATC_RGBA_INTERPOLATED', 434) +PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = enum_pipe_format.define('PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 435) +PIPE_FORMAT_AYUV = enum_pipe_format.define('PIPE_FORMAT_AYUV', 436) +PIPE_FORMAT_XYUV = enum_pipe_format.define('PIPE_FORMAT_XYUV', 437) +PIPE_FORMAT_R8G8B8_420_UNORM_PACKED = enum_pipe_format.define('PIPE_FORMAT_R8G8B8_420_UNORM_PACKED', 438) +PIPE_FORMAT_R8_G8B8_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_G8B8_420_UNORM', 439) +PIPE_FORMAT_R8_B8G8_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_B8G8_420_UNORM', 440) +PIPE_FORMAT_G8_B8R8_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8_B8R8_420_UNORM', 441) +PIPE_FORMAT_R10G10B10_420_UNORM_PACKED = enum_pipe_format.define('PIPE_FORMAT_R10G10B10_420_UNORM_PACKED', 442) +PIPE_FORMAT_R10_G10B10_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_R10_G10B10_420_UNORM', 443) +PIPE_FORMAT_R10_G10B10_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_R10_G10B10_422_UNORM', 444) +PIPE_FORMAT_R8_G8_B8_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_G8_B8_420_UNORM', 445) +PIPE_FORMAT_R8_B8_G8_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_B8_G8_420_UNORM', 446) +PIPE_FORMAT_G8_B8_R8_420_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8_B8_R8_420_UNORM', 447) +PIPE_FORMAT_R8_G8B8_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_G8B8_422_UNORM', 448) +PIPE_FORMAT_R8_B8G8_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_B8G8_422_UNORM', 449) +PIPE_FORMAT_G8_B8R8_422_UNORM = enum_pipe_format.define('PIPE_FORMAT_G8_B8R8_422_UNORM', 450) +PIPE_FORMAT_R8_G8_B8_UNORM = enum_pipe_format.define('PIPE_FORMAT_R8_G8_B8_UNORM', 451) +PIPE_FORMAT_Y8_UNORM = enum_pipe_format.define('PIPE_FORMAT_Y8_UNORM', 452) +PIPE_FORMAT_B8G8R8X8_SNORM = enum_pipe_format.define('PIPE_FORMAT_B8G8R8X8_SNORM', 453) +PIPE_FORMAT_B8G8R8X8_UINT = enum_pipe_format.define('PIPE_FORMAT_B8G8R8X8_UINT', 454) +PIPE_FORMAT_B8G8R8X8_SINT = enum_pipe_format.define('PIPE_FORMAT_B8G8R8X8_SINT', 455) +PIPE_FORMAT_A8R8G8B8_SNORM = enum_pipe_format.define('PIPE_FORMAT_A8R8G8B8_SNORM', 456) +PIPE_FORMAT_A8R8G8B8_SINT = enum_pipe_format.define('PIPE_FORMAT_A8R8G8B8_SINT', 457) +PIPE_FORMAT_X8R8G8B8_SNORM = enum_pipe_format.define('PIPE_FORMAT_X8R8G8B8_SNORM', 458) +PIPE_FORMAT_X8R8G8B8_SINT = enum_pipe_format.define('PIPE_FORMAT_X8R8G8B8_SINT', 459) +PIPE_FORMAT_R5G5B5X1_UNORM = enum_pipe_format.define('PIPE_FORMAT_R5G5B5X1_UNORM', 460) +PIPE_FORMAT_X1R5G5B5_UNORM = enum_pipe_format.define('PIPE_FORMAT_X1R5G5B5_UNORM', 461) +PIPE_FORMAT_R4G4B4X4_UNORM = enum_pipe_format.define('PIPE_FORMAT_R4G4B4X4_UNORM', 462) +PIPE_FORMAT_B10G10R10X2_SNORM = enum_pipe_format.define('PIPE_FORMAT_B10G10R10X2_SNORM', 463) +PIPE_FORMAT_R5G6B5_SRGB = enum_pipe_format.define('PIPE_FORMAT_R5G6B5_SRGB', 464) +PIPE_FORMAT_R10G10B10X2_SINT = enum_pipe_format.define('PIPE_FORMAT_R10G10B10X2_SINT', 465) +PIPE_FORMAT_B10G10R10X2_SINT = enum_pipe_format.define('PIPE_FORMAT_B10G10R10X2_SINT', 466) +PIPE_FORMAT_G16R16_SINT = enum_pipe_format.define('PIPE_FORMAT_G16R16_SINT', 467) +PIPE_FORMAT_COUNT = enum_pipe_format.define('PIPE_FORMAT_COUNT', 468) -class union_nir_variable_data_0(Union): - pass - -class struct_nir_variable_data_0_image(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('format', pipe_format), - ] - -class struct_nir_variable_data_0_sampler(Structure): - pass - -struct_nir_variable_data_0_sampler._pack_ = 1 # source:False +struct_nir_variable_data_0_image._fields_ = [ + ('format', enum_pipe_format), +] +class struct_nir_variable_data_0_sampler(Struct): pass struct_nir_variable_data_0_sampler._fields_ = [ - ('is_inline_sampler', ctypes.c_uint32, 1), - ('addressing_mode', ctypes.c_uint32, 3), - ('normalized_coordinates', ctypes.c_uint32, 1), - ('filter_mode', ctypes.c_uint32, 1), - ('PADDING_0', ctypes.c_uint32, 26), + ('is_inline_sampler', ctypes.c_uint32,1), + ('addressing_mode', ctypes.c_uint32,3), + ('normalized_coordinates', ctypes.c_uint32,1), + ('filter_mode', ctypes.c_uint32,1), ] - -class struct_nir_variable_data_0_xfb(Structure): - pass - -struct_nir_variable_data_0_xfb._pack_ = 1 # source:False +class struct_nir_variable_data_0_xfb(Struct): pass struct_nir_variable_data_0_xfb._fields_ = [ - ('buffer', ctypes.c_uint16, 2), - ('PADDING_0', ctypes.c_uint16, 14), - ('stride', ctypes.c_uint16), + ('buffer', uint16_t,2), + ('stride', uint16_t), ] - -union_nir_variable_data_0._pack_ = 1 # source:False -union_nir_variable_data_0._fields_ = [ - ('image', struct_nir_variable_data_0_image), - ('sampler', struct_nir_variable_data_0_sampler), - ('xfb', struct_nir_variable_data_0_xfb), +struct_nir_variable_data_0._fields_ = [ + ('image', struct_nir_variable_data_0_image), + ('sampler', struct_nir_variable_data_0_sampler), + ('xfb', struct_nir_variable_data_0_xfb), ] - -struct_nir_variable_data._pack_ = 1 # source:False -struct_nir_variable_data._anonymous_ = ('_0',) +struct_nir_variable_data._anonymous_ = ['_0'] struct_nir_variable_data._fields_ = [ - ('mode', ctypes.c_uint64, 21), - ('read_only', ctypes.c_uint64, 1), - ('centroid', ctypes.c_uint64, 1), - ('sample', ctypes.c_uint64, 1), - ('patch', ctypes.c_uint64, 1), - ('invariant', ctypes.c_uint64, 1), - ('explicit_invariant', ctypes.c_uint64, 1), - ('ray_query', ctypes.c_uint64, 1), - ('precision', ctypes.c_uint64, 2), - ('assigned', ctypes.c_uint64, 1), - ('cannot_coalesce', ctypes.c_uint64, 1), - ('always_active_io', ctypes.c_uint64, 1), - ('interpolation', ctypes.c_uint64, 3), - ('location_frac', ctypes.c_uint64, 2), - ('compact', ctypes.c_uint64, 1), - ('fb_fetch_output', ctypes.c_uint64, 1), - ('bindless', ctypes.c_uint64, 1), - ('explicit_binding', ctypes.c_uint64, 1), - ('explicit_location', ctypes.c_uint64, 1), - ('implicit_sized_array', ctypes.c_uint64, 1), - ('PADDING_0', ctypes.c_uint32, 20), - ('max_array_access', ctypes.c_int32), - ('has_initializer', ctypes.c_uint64, 1), - ('is_implicit_initializer', ctypes.c_uint64, 1), - ('is_xfb', ctypes.c_uint64, 1), - ('is_xfb_only', ctypes.c_uint64, 1), - ('explicit_xfb_buffer', ctypes.c_uint64, 1), - ('explicit_xfb_stride', ctypes.c_uint64, 1), - ('explicit_offset', ctypes.c_uint64, 1), - ('matrix_layout', ctypes.c_uint64, 2), - ('from_named_ifc_block', ctypes.c_uint64, 1), - ('from_ssbo_unsized_array', ctypes.c_uint64, 1), - ('must_be_shader_input', ctypes.c_uint64, 1), - ('used', ctypes.c_uint64, 1), - ('how_declared', ctypes.c_uint64, 2), - ('per_view', ctypes.c_uint64, 1), - ('per_primitive', ctypes.c_uint64, 1), - ('per_vertex', ctypes.c_uint64, 1), - ('aliased_shared_memory', ctypes.c_uint64, 1), - ('depth_layout', ctypes.c_uint64, 3), - ('stream', ctypes.c_uint64, 9), - ('PADDING_1', ctypes.c_uint8, 1), - ('access', ctypes.c_uint64, 9), - ('descriptor_set', ctypes.c_uint64, 5), - ('PADDING_2', ctypes.c_uint32, 18), - ('index', ctypes.c_uint32), - ('binding', ctypes.c_uint32), - ('location', ctypes.c_int32), - ('alignment', ctypes.c_uint32), - ('driver_location', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('_0', union_nir_variable_data_0), - ('node_name', ctypes.POINTER(ctypes.c_char)), + ('mode', ctypes.c_uint32,21), + ('read_only', ctypes.c_uint32,1), + ('centroid', ctypes.c_uint32,1), + ('sample', ctypes.c_uint32,1), + ('patch', ctypes.c_uint32,1), + ('invariant', ctypes.c_uint32,1), + ('explicit_invariant', ctypes.c_uint32,1), + ('ray_query', ctypes.c_uint32,1), + ('precision', ctypes.c_uint32,2), + ('assigned', ctypes.c_uint32,1), + ('cannot_coalesce', ctypes.c_uint32,1), + ('always_active_io', ctypes.c_uint32,1), + ('interpolation', ctypes.c_uint32,3), + ('location_frac', ctypes.c_uint32,2), + ('compact', ctypes.c_uint32,1), + ('fb_fetch_output', ctypes.c_uint32,1), + ('bindless', ctypes.c_uint32,1), + ('explicit_binding', ctypes.c_uint32,1), + ('explicit_location', ctypes.c_uint32,1), + ('implicit_sized_array', ctypes.c_uint32,1), + ('max_array_access', ctypes.c_int32), + ('has_initializer', ctypes.c_uint32,1), + ('is_implicit_initializer', ctypes.c_uint32,1), + ('is_xfb', ctypes.c_uint32,1), + ('is_xfb_only', ctypes.c_uint32,1), + ('explicit_xfb_buffer', ctypes.c_uint32,1), + ('explicit_xfb_stride', ctypes.c_uint32,1), + ('explicit_offset', ctypes.c_uint32,1), + ('matrix_layout', ctypes.c_uint32,2), + ('from_named_ifc_block', ctypes.c_uint32,1), + ('from_ssbo_unsized_array', ctypes.c_uint32,1), + ('must_be_shader_input', ctypes.c_uint32,1), + ('used', ctypes.c_uint32,1), + ('how_declared', ctypes.c_uint32,2), + ('per_view', ctypes.c_uint32,1), + ('per_primitive', ctypes.c_uint32,1), + ('per_vertex', ctypes.c_uint32,1), + ('aliased_shared_memory', ctypes.c_uint32,1), + ('depth_layout', ctypes.c_uint32,3), + ('stream', ctypes.c_uint32,9), + ('access', ctypes.c_uint32,9), + ('descriptor_set', ctypes.c_uint32,5), + ('index', ctypes.c_uint32), + ('binding', ctypes.c_uint32), + ('location', ctypes.c_int32), + ('alignment', ctypes.c_uint32), + ('driver_location', ctypes.c_uint32), + ('offset', ctypes.c_uint32), + ('_0', struct_nir_variable_data_0), + ('node_name', ctypes.POINTER(ctypes.c_char)), ] - nir_variable_data = struct_nir_variable_data -class struct_nir_variable(Structure): - pass - -struct_nir_variable._pack_ = 1 # source:False -struct_nir_variable._fields_ = [ - ('node', struct_exec_node), - ('type', ctypes.POINTER(struct_glsl_type)), - ('name', ctypes.POINTER(ctypes.c_char)), - ('data', struct_nir_variable_data), - ('index', ctypes.c_uint32), - ('num_members', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('max_ifc_array_access', ctypes.POINTER(ctypes.c_int32)), - ('num_state_slots', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 6), - ('state_slots', ctypes.POINTER(struct_nir_state_slot)), - ('constant_initializer', ctypes.POINTER(struct_nir_constant)), - ('pointer_initializer', ctypes.POINTER(struct_nir_variable)), - ('interface_type', ctypes.POINTER(struct_glsl_type)), - ('members', ctypes.POINTER(struct_nir_variable_data)), +class struct_nir_variable(Struct): pass +class struct_exec_node(Struct): pass +struct_exec_node._fields_ = [ + ('next', ctypes.POINTER(struct_exec_node)), + ('prev', ctypes.POINTER(struct_exec_node)), ] +class struct_glsl_type(Struct): pass +enum_glsl_base_type = CEnum(ctypes.c_uint32) +GLSL_TYPE_UINT = enum_glsl_base_type.define('GLSL_TYPE_UINT', 0) +GLSL_TYPE_INT = enum_glsl_base_type.define('GLSL_TYPE_INT', 1) +GLSL_TYPE_FLOAT = enum_glsl_base_type.define('GLSL_TYPE_FLOAT', 2) +GLSL_TYPE_FLOAT16 = enum_glsl_base_type.define('GLSL_TYPE_FLOAT16', 3) +GLSL_TYPE_BFLOAT16 = enum_glsl_base_type.define('GLSL_TYPE_BFLOAT16', 4) +GLSL_TYPE_FLOAT_E4M3FN = enum_glsl_base_type.define('GLSL_TYPE_FLOAT_E4M3FN', 5) +GLSL_TYPE_FLOAT_E5M2 = enum_glsl_base_type.define('GLSL_TYPE_FLOAT_E5M2', 6) +GLSL_TYPE_DOUBLE = enum_glsl_base_type.define('GLSL_TYPE_DOUBLE', 7) +GLSL_TYPE_UINT8 = enum_glsl_base_type.define('GLSL_TYPE_UINT8', 8) +GLSL_TYPE_INT8 = enum_glsl_base_type.define('GLSL_TYPE_INT8', 9) +GLSL_TYPE_UINT16 = enum_glsl_base_type.define('GLSL_TYPE_UINT16', 10) +GLSL_TYPE_INT16 = enum_glsl_base_type.define('GLSL_TYPE_INT16', 11) +GLSL_TYPE_UINT64 = enum_glsl_base_type.define('GLSL_TYPE_UINT64', 12) +GLSL_TYPE_INT64 = enum_glsl_base_type.define('GLSL_TYPE_INT64', 13) +GLSL_TYPE_BOOL = enum_glsl_base_type.define('GLSL_TYPE_BOOL', 14) +GLSL_TYPE_COOPERATIVE_MATRIX = enum_glsl_base_type.define('GLSL_TYPE_COOPERATIVE_MATRIX', 15) +GLSL_TYPE_SAMPLER = enum_glsl_base_type.define('GLSL_TYPE_SAMPLER', 16) +GLSL_TYPE_TEXTURE = enum_glsl_base_type.define('GLSL_TYPE_TEXTURE', 17) +GLSL_TYPE_IMAGE = enum_glsl_base_type.define('GLSL_TYPE_IMAGE', 18) +GLSL_TYPE_ATOMIC_UINT = enum_glsl_base_type.define('GLSL_TYPE_ATOMIC_UINT', 19) +GLSL_TYPE_STRUCT = enum_glsl_base_type.define('GLSL_TYPE_STRUCT', 20) +GLSL_TYPE_INTERFACE = enum_glsl_base_type.define('GLSL_TYPE_INTERFACE', 21) +GLSL_TYPE_ARRAY = enum_glsl_base_type.define('GLSL_TYPE_ARRAY', 22) +GLSL_TYPE_VOID = enum_glsl_base_type.define('GLSL_TYPE_VOID', 23) +GLSL_TYPE_SUBROUTINE = enum_glsl_base_type.define('GLSL_TYPE_SUBROUTINE', 24) +GLSL_TYPE_ERROR = enum_glsl_base_type.define('GLSL_TYPE_ERROR', 25) +class struct_glsl_cmat_description(Struct): pass +struct_glsl_cmat_description._fields_ = [ + ('element_type', uint8_t,5), + ('scope', uint8_t,3), + ('rows', uint8_t), + ('cols', uint8_t), + ('use', uint8_t), +] +uintptr_t = ctypes.c_uint64 +class struct_glsl_type_fields(ctypes.Union): pass +glsl_type = struct_glsl_type +class struct_glsl_struct_field(Struct): pass +glsl_struct_field = struct_glsl_struct_field +class struct_glsl_struct_field_0(ctypes.Union): pass +class struct_glsl_struct_field_0_0(Struct): pass +struct_glsl_struct_field_0_0._fields_ = [ + ('interpolation', ctypes.c_uint32,3), + ('centroid', ctypes.c_uint32,1), + ('sample', ctypes.c_uint32,1), + ('matrix_layout', ctypes.c_uint32,2), + ('patch', ctypes.c_uint32,1), + ('precision', ctypes.c_uint32,2), + ('memory_read_only', ctypes.c_uint32,1), + ('memory_write_only', ctypes.c_uint32,1), + ('memory_coherent', ctypes.c_uint32,1), + ('memory_volatile', ctypes.c_uint32,1), + ('memory_restrict', ctypes.c_uint32,1), + ('explicit_xfb_buffer', ctypes.c_uint32,1), + ('implicit_sized_array', ctypes.c_uint32,1), +] +struct_glsl_struct_field_0._anonymous_ = ['_0'] +struct_glsl_struct_field_0._fields_ = [ + ('_0', struct_glsl_struct_field_0_0), + ('flags', ctypes.c_uint32), +] +struct_glsl_struct_field._anonymous_ = ['_0'] +struct_glsl_struct_field._fields_ = [ + ('type', ctypes.POINTER(glsl_type)), + ('name', ctypes.POINTER(ctypes.c_char)), + ('location', ctypes.c_int32), + ('component', ctypes.c_int32), + ('offset', ctypes.c_int32), + ('xfb_buffer', ctypes.c_int32), + ('xfb_stride', ctypes.c_int32), + ('image_format', enum_pipe_format), + ('_0', struct_glsl_struct_field_0), +] +struct_glsl_type_fields._fields_ = [ + ('array', ctypes.POINTER(glsl_type)), + ('structure', ctypes.POINTER(glsl_struct_field)), +] +struct_glsl_type._fields_ = [ + ('gl_type', uint32_t), + ('base_type', enum_glsl_base_type,8), + ('sampled_type', enum_glsl_base_type,8), + ('sampler_dimensionality', ctypes.c_uint32,4), + ('sampler_shadow', ctypes.c_uint32,1), + ('sampler_array', ctypes.c_uint32,1), + ('interface_packing', ctypes.c_uint32,2), + ('interface_row_major', ctypes.c_uint32,1), + ('cmat_desc', struct_glsl_cmat_description), + ('packed', ctypes.c_uint32,1), + ('has_builtin_name', ctypes.c_uint32,1), + ('vector_elements', uint8_t), + ('matrix_columns', uint8_t), + ('length', ctypes.c_uint32), + ('name_id', uintptr_t), + ('explicit_stride', ctypes.c_uint32), + ('explicit_alignment', ctypes.c_uint32), + ('fields', struct_glsl_type_fields), +] nir_variable = struct_nir_variable -try: - _nir_shader_variable_has_mode = _libraries['FIXME_STUB']._nir_shader_variable_has_mode - _nir_shader_variable_has_mode.restype = ctypes.c_bool - _nir_shader_variable_has_mode.argtypes = [ctypes.POINTER(struct_nir_variable), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_variable_is_global = _libraries['FIXME_STUB'].nir_variable_is_global - nir_variable_is_global.restype = ctypes.c_bool - nir_variable_is_global.argtypes = [ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_instr_type' -c__EA_nir_instr_type__enumvalues = { - 0: 'nir_instr_type_alu', - 1: 'nir_instr_type_deref', - 2: 'nir_instr_type_call', - 3: 'nir_instr_type_tex', - 4: 'nir_instr_type_intrinsic', - 5: 'nir_instr_type_load_const', - 6: 'nir_instr_type_jump', - 7: 'nir_instr_type_undef', - 8: 'nir_instr_type_phi', - 9: 'nir_instr_type_parallel_copy', -} -nir_instr_type_alu = 0 -nir_instr_type_deref = 1 -nir_instr_type_call = 2 -nir_instr_type_tex = 3 -nir_instr_type_intrinsic = 4 -nir_instr_type_load_const = 5 -nir_instr_type_jump = 6 -nir_instr_type_undef = 7 -nir_instr_type_phi = 8 -nir_instr_type_parallel_copy = 9 -c__EA_nir_instr_type = ctypes.c_uint32 # enum -nir_instr_type = c__EA_nir_instr_type -nir_instr_type__enumvalues = c__EA_nir_instr_type__enumvalues -nir_instr = struct_nir_instr -try: - nir_instr_next = _libraries['FIXME_STUB'].nir_instr_next - nir_instr_next.restype = ctypes.POINTER(struct_nir_instr) - nir_instr_next.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_prev = _libraries['FIXME_STUB'].nir_instr_prev - nir_instr_prev.restype = ctypes.POINTER(struct_nir_instr) - nir_instr_prev.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_is_first = _libraries['FIXME_STUB'].nir_instr_is_first - nir_instr_is_first.restype = ctypes.c_bool - nir_instr_is_first.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_is_last = _libraries['FIXME_STUB'].nir_instr_is_last - nir_instr_is_last.restype = ctypes.c_bool - nir_instr_is_last.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -class struct_nir_def(Structure): - pass - -class struct_list_head(Structure): - pass - -struct_list_head._pack_ = 1 # source:False -struct_list_head._fields_ = [ - ('prev', ctypes.POINTER(struct_list_head)), - ('next', ctypes.POINTER(struct_list_head)), +struct_nir_variable._fields_ = [ + ('node', struct_exec_node), + ('type', ctypes.POINTER(struct_glsl_type)), + ('name', ctypes.POINTER(ctypes.c_char)), + ('data', struct_nir_variable_data), + ('index', ctypes.c_uint32), + ('num_members', uint16_t), + ('max_ifc_array_access', ctypes.POINTER(ctypes.c_int32)), + ('num_state_slots', uint16_t), + ('state_slots', ctypes.POINTER(nir_state_slot)), + ('constant_initializer', ctypes.POINTER(nir_constant)), + ('pointer_initializer', ctypes.POINTER(nir_variable)), + ('interface_type', ctypes.POINTER(struct_glsl_type)), + ('members', ctypes.POINTER(nir_variable_data)), ] - -struct_nir_def._pack_ = 1 # source:False -struct_nir_def._fields_ = [ - ('parent_instr', ctypes.POINTER(struct_nir_instr)), - ('uses', struct_list_head), - ('index', ctypes.c_uint32), - ('num_components', ctypes.c_ubyte), - ('bit_size', ctypes.c_ubyte), - ('divergent', ctypes.c_bool), - ('loop_invariant', ctypes.c_bool), -] - -nir_def = struct_nir_def -class struct_nir_src(Structure): - pass - -struct_nir_src._pack_ = 1 # source:False -struct_nir_src._fields_ = [ - ('_parent', ctypes.c_uint64), - ('use_link', struct_list_head), - ('ssa', ctypes.POINTER(struct_nir_def)), -] - -nir_src = struct_nir_src -try: - nir_src_is_if = _libraries['FIXME_STUB'].nir_src_is_if - nir_src_is_if.restype = ctypes.c_bool - nir_src_is_if.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_src_parent_instr = _libraries['FIXME_STUB'].nir_src_parent_instr - nir_src_parent_instr.restype = ctypes.POINTER(struct_nir_instr) - nir_src_parent_instr.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -class struct_nir_if(Structure): - pass - - -# values for enumeration 'c__EA_nir_selection_control' -c__EA_nir_selection_control__enumvalues = { - 0: 'nir_selection_control_none', - 1: 'nir_selection_control_flatten', - 2: 'nir_selection_control_dont_flatten', - 3: 'nir_selection_control_divergent_always_taken', -} -nir_selection_control_none = 0 -nir_selection_control_flatten = 1 -nir_selection_control_dont_flatten = 2 -nir_selection_control_divergent_always_taken = 3 -c__EA_nir_selection_control = ctypes.c_uint32 # enum -struct_nir_if._pack_ = 1 # source:False -struct_nir_if._fields_ = [ - ('cf_node', struct_nir_cf_node), - ('condition', nir_src), - ('control', c__EA_nir_selection_control), - ('PADDING_0', ctypes.c_ubyte * 4), - ('then_list', struct_exec_list), - ('else_list', struct_exec_list), -] - -try: - nir_src_parent_if = _libraries['FIXME_STUB'].nir_src_parent_if - nir_src_parent_if.restype = ctypes.POINTER(struct_nir_if) - nir_src_parent_if.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - _nir_src_set_parent = _libraries['FIXME_STUB']._nir_src_set_parent - _nir_src_set_parent.restype = None - _nir_src_set_parent.argtypes = [ctypes.POINTER(struct_nir_src), ctypes.POINTER(None), ctypes.c_bool] -except AttributeError: - pass -try: - nir_src_set_parent_instr = _libraries['FIXME_STUB'].nir_src_set_parent_instr - nir_src_set_parent_instr.restype = None - nir_src_set_parent_instr.argtypes = [ctypes.POINTER(struct_nir_src), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_src_set_parent_if = _libraries['FIXME_STUB'].nir_src_set_parent_if - nir_src_set_parent_if.restype = None - nir_src_set_parent_if.argtypes = [ctypes.POINTER(struct_nir_src), ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_src_init = _libraries['FIXME_STUB'].nir_src_init - nir_src_init.restype = nir_src - nir_src_init.argtypes = [] -except AttributeError: - pass -try: - nir_def_used_by_if = _libraries['FIXME_STUB'].nir_def_used_by_if - nir_def_used_by_if.restype = ctypes.c_bool - nir_def_used_by_if.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_only_used_by_if = _libraries['FIXME_STUB'].nir_def_only_used_by_if - nir_def_only_used_by_if.restype = ctypes.c_bool - nir_def_only_used_by_if.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_src_for_ssa = _libraries['FIXME_STUB'].nir_src_for_ssa - nir_src_for_ssa.restype = nir_src - nir_src_for_ssa.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_src_bit_size = _libraries['FIXME_STUB'].nir_src_bit_size - nir_src_bit_size.restype = ctypes.c_uint32 - nir_src_bit_size.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_num_components = _libraries['FIXME_STUB'].nir_src_num_components - nir_src_num_components.restype = ctypes.c_uint32 - nir_src_num_components.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_is_const = _libraries['FIXME_STUB'].nir_src_is_const - nir_src_is_const.restype = ctypes.c_bool - nir_src_is_const.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_is_undef = _libraries['FIXME_STUB'].nir_src_is_undef - nir_src_is_undef.restype = ctypes.c_bool - nir_src_is_undef.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_is_divergent = _libraries['libtinymesa_cpu.so'].nir_src_is_divergent - nir_src_is_divergent.restype = ctypes.c_bool - nir_src_is_divergent.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_is_same_comp_swizzle = _libraries['FIXME_STUB'].nir_is_same_comp_swizzle - nir_is_same_comp_swizzle.restype = ctypes.c_bool - nir_is_same_comp_swizzle.argtypes = [ctypes.POINTER(ctypes.c_ubyte), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_sequential_comp_swizzle = _libraries['FIXME_STUB'].nir_is_sequential_comp_swizzle - nir_is_sequential_comp_swizzle.restype = ctypes.c_bool - nir_is_sequential_comp_swizzle.argtypes = [ctypes.POINTER(ctypes.c_ubyte), ctypes.c_uint32] -except AttributeError: - pass -class struct_nir_alu_src(Structure): - pass - -struct_nir_alu_src._pack_ = 1 # source:False -struct_nir_alu_src._fields_ = [ - ('src', nir_src), - ('swizzle', ctypes.c_ubyte * 16), -] - -nir_alu_src = struct_nir_alu_src - -# values for enumeration 'c__EA_nir_alu_type' -c__EA_nir_alu_type__enumvalues = { - 0: 'nir_type_invalid', - 2: 'nir_type_int', - 4: 'nir_type_uint', - 6: 'nir_type_bool', - 128: 'nir_type_float', - 7: 'nir_type_bool1', - 14: 'nir_type_bool8', - 22: 'nir_type_bool16', - 38: 'nir_type_bool32', - 3: 'nir_type_int1', - 10: 'nir_type_int8', - 18: 'nir_type_int16', - 34: 'nir_type_int32', - 66: 'nir_type_int64', - 5: 'nir_type_uint1', - 12: 'nir_type_uint8', - 20: 'nir_type_uint16', - 36: 'nir_type_uint32', - 68: 'nir_type_uint64', - 144: 'nir_type_float16', - 160: 'nir_type_float32', - 192: 'nir_type_float64', -} -nir_type_invalid = 0 -nir_type_int = 2 -nir_type_uint = 4 -nir_type_bool = 6 -nir_type_float = 128 -nir_type_bool1 = 7 -nir_type_bool8 = 14 -nir_type_bool16 = 22 -nir_type_bool32 = 38 -nir_type_int1 = 3 -nir_type_int8 = 10 -nir_type_int16 = 18 -nir_type_int32 = 34 -nir_type_int64 = 66 -nir_type_uint1 = 5 -nir_type_uint8 = 12 -nir_type_uint16 = 20 -nir_type_uint32 = 36 -nir_type_uint64 = 68 -nir_type_float16 = 144 -nir_type_float32 = 160 -nir_type_float64 = 192 -c__EA_nir_alu_type = ctypes.c_uint32 # enum -nir_alu_type = c__EA_nir_alu_type -nir_alu_type__enumvalues = c__EA_nir_alu_type__enumvalues -try: - nir_get_nir_type_for_glsl_base_type = _libraries['libtinymesa_cpu.so'].nir_get_nir_type_for_glsl_base_type - nir_get_nir_type_for_glsl_base_type.restype = nir_alu_type - nir_get_nir_type_for_glsl_base_type.argtypes = [glsl_base_type] -except AttributeError: - pass -try: - nir_get_nir_type_for_glsl_type = _libraries['FIXME_STUB'].nir_get_nir_type_for_glsl_type - nir_get_nir_type_for_glsl_type.restype = nir_alu_type - nir_get_nir_type_for_glsl_type.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - nir_get_glsl_base_type_for_nir_type = _libraries['libtinymesa_cpu.so'].nir_get_glsl_base_type_for_nir_type - nir_get_glsl_base_type_for_nir_type.restype = glsl_base_type - nir_get_glsl_base_type_for_nir_type.argtypes = [nir_alu_type] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_op' -c__EA_nir_op__enumvalues = { - 0: 'nir_op_alignbyte_amd', - 1: 'nir_op_amul', - 2: 'nir_op_andg_ir3', - 3: 'nir_op_b16all_fequal16', - 4: 'nir_op_b16all_fequal2', - 5: 'nir_op_b16all_fequal3', - 6: 'nir_op_b16all_fequal4', - 7: 'nir_op_b16all_fequal5', - 8: 'nir_op_b16all_fequal8', - 9: 'nir_op_b16all_iequal16', - 10: 'nir_op_b16all_iequal2', - 11: 'nir_op_b16all_iequal3', - 12: 'nir_op_b16all_iequal4', - 13: 'nir_op_b16all_iequal5', - 14: 'nir_op_b16all_iequal8', - 15: 'nir_op_b16any_fnequal16', - 16: 'nir_op_b16any_fnequal2', - 17: 'nir_op_b16any_fnequal3', - 18: 'nir_op_b16any_fnequal4', - 19: 'nir_op_b16any_fnequal5', - 20: 'nir_op_b16any_fnequal8', - 21: 'nir_op_b16any_inequal16', - 22: 'nir_op_b16any_inequal2', - 23: 'nir_op_b16any_inequal3', - 24: 'nir_op_b16any_inequal4', - 25: 'nir_op_b16any_inequal5', - 26: 'nir_op_b16any_inequal8', - 27: 'nir_op_b16csel', - 28: 'nir_op_b2b1', - 29: 'nir_op_b2b16', - 30: 'nir_op_b2b32', - 31: 'nir_op_b2b8', - 32: 'nir_op_b2f16', - 33: 'nir_op_b2f32', - 34: 'nir_op_b2f64', - 35: 'nir_op_b2i1', - 36: 'nir_op_b2i16', - 37: 'nir_op_b2i32', - 38: 'nir_op_b2i64', - 39: 'nir_op_b2i8', - 40: 'nir_op_b32all_fequal16', - 41: 'nir_op_b32all_fequal2', - 42: 'nir_op_b32all_fequal3', - 43: 'nir_op_b32all_fequal4', - 44: 'nir_op_b32all_fequal5', - 45: 'nir_op_b32all_fequal8', - 46: 'nir_op_b32all_iequal16', - 47: 'nir_op_b32all_iequal2', - 48: 'nir_op_b32all_iequal3', - 49: 'nir_op_b32all_iequal4', - 50: 'nir_op_b32all_iequal5', - 51: 'nir_op_b32all_iequal8', - 52: 'nir_op_b32any_fnequal16', - 53: 'nir_op_b32any_fnequal2', - 54: 'nir_op_b32any_fnequal3', - 55: 'nir_op_b32any_fnequal4', - 56: 'nir_op_b32any_fnequal5', - 57: 'nir_op_b32any_fnequal8', - 58: 'nir_op_b32any_inequal16', - 59: 'nir_op_b32any_inequal2', - 60: 'nir_op_b32any_inequal3', - 61: 'nir_op_b32any_inequal4', - 62: 'nir_op_b32any_inequal5', - 63: 'nir_op_b32any_inequal8', - 64: 'nir_op_b32csel', - 65: 'nir_op_b32fcsel_mdg', - 66: 'nir_op_b8all_fequal16', - 67: 'nir_op_b8all_fequal2', - 68: 'nir_op_b8all_fequal3', - 69: 'nir_op_b8all_fequal4', - 70: 'nir_op_b8all_fequal5', - 71: 'nir_op_b8all_fequal8', - 72: 'nir_op_b8all_iequal16', - 73: 'nir_op_b8all_iequal2', - 74: 'nir_op_b8all_iequal3', - 75: 'nir_op_b8all_iequal4', - 76: 'nir_op_b8all_iequal5', - 77: 'nir_op_b8all_iequal8', - 78: 'nir_op_b8any_fnequal16', - 79: 'nir_op_b8any_fnequal2', - 80: 'nir_op_b8any_fnequal3', - 81: 'nir_op_b8any_fnequal4', - 82: 'nir_op_b8any_fnequal5', - 83: 'nir_op_b8any_fnequal8', - 84: 'nir_op_b8any_inequal16', - 85: 'nir_op_b8any_inequal2', - 86: 'nir_op_b8any_inequal3', - 87: 'nir_op_b8any_inequal4', - 88: 'nir_op_b8any_inequal5', - 89: 'nir_op_b8any_inequal8', - 90: 'nir_op_b8csel', - 91: 'nir_op_ball_fequal16', - 92: 'nir_op_ball_fequal2', - 93: 'nir_op_ball_fequal3', - 94: 'nir_op_ball_fequal4', - 95: 'nir_op_ball_fequal5', - 96: 'nir_op_ball_fequal8', - 97: 'nir_op_ball_iequal16', - 98: 'nir_op_ball_iequal2', - 99: 'nir_op_ball_iequal3', - 100: 'nir_op_ball_iequal4', - 101: 'nir_op_ball_iequal5', - 102: 'nir_op_ball_iequal8', - 103: 'nir_op_bany_fnequal16', - 104: 'nir_op_bany_fnequal2', - 105: 'nir_op_bany_fnequal3', - 106: 'nir_op_bany_fnequal4', - 107: 'nir_op_bany_fnequal5', - 108: 'nir_op_bany_fnequal8', - 109: 'nir_op_bany_inequal16', - 110: 'nir_op_bany_inequal2', - 111: 'nir_op_bany_inequal3', - 112: 'nir_op_bany_inequal4', - 113: 'nir_op_bany_inequal5', - 114: 'nir_op_bany_inequal8', - 115: 'nir_op_bcsel', - 116: 'nir_op_bf2f', - 117: 'nir_op_bfdot16', - 118: 'nir_op_bfdot2', - 119: 'nir_op_bfdot2_bfadd', - 120: 'nir_op_bfdot3', - 121: 'nir_op_bfdot4', - 122: 'nir_op_bfdot5', - 123: 'nir_op_bfdot8', - 124: 'nir_op_bffma', - 125: 'nir_op_bfi', - 126: 'nir_op_bfm', - 127: 'nir_op_bfmul', - 128: 'nir_op_bit_count', - 129: 'nir_op_bitfield_insert', - 130: 'nir_op_bitfield_reverse', - 131: 'nir_op_bitfield_select', - 132: 'nir_op_bitnz', - 133: 'nir_op_bitnz16', - 134: 'nir_op_bitnz32', - 135: 'nir_op_bitnz8', - 136: 'nir_op_bitz', - 137: 'nir_op_bitz16', - 138: 'nir_op_bitz32', - 139: 'nir_op_bitz8', - 140: 'nir_op_bounds_agx', - 141: 'nir_op_byte_perm_amd', - 142: 'nir_op_cube_amd', - 143: 'nir_op_e4m3fn2f', - 144: 'nir_op_e5m22f', - 145: 'nir_op_extr_agx', - 146: 'nir_op_extract_i16', - 147: 'nir_op_extract_i8', - 148: 'nir_op_extract_u16', - 149: 'nir_op_extract_u8', - 150: 'nir_op_f2bf', - 151: 'nir_op_f2e4m3fn', - 152: 'nir_op_f2e4m3fn_sat', - 153: 'nir_op_f2e4m3fn_satfn', - 154: 'nir_op_f2e5m2', - 155: 'nir_op_f2e5m2_sat', - 156: 'nir_op_f2f16', - 157: 'nir_op_f2f16_rtne', - 158: 'nir_op_f2f16_rtz', - 159: 'nir_op_f2f32', - 160: 'nir_op_f2f64', - 161: 'nir_op_f2fmp', - 162: 'nir_op_f2i1', - 163: 'nir_op_f2i16', - 164: 'nir_op_f2i32', - 165: 'nir_op_f2i64', - 166: 'nir_op_f2i8', - 167: 'nir_op_f2imp', - 168: 'nir_op_f2snorm_16_v3d', - 169: 'nir_op_f2u1', - 170: 'nir_op_f2u16', - 171: 'nir_op_f2u32', - 172: 'nir_op_f2u64', - 173: 'nir_op_f2u8', - 174: 'nir_op_f2ump', - 175: 'nir_op_f2unorm_16_v3d', - 176: 'nir_op_fabs', - 177: 'nir_op_fadd', - 178: 'nir_op_fall_equal16', - 179: 'nir_op_fall_equal2', - 180: 'nir_op_fall_equal3', - 181: 'nir_op_fall_equal4', - 182: 'nir_op_fall_equal5', - 183: 'nir_op_fall_equal8', - 184: 'nir_op_fany_nequal16', - 185: 'nir_op_fany_nequal2', - 186: 'nir_op_fany_nequal3', - 187: 'nir_op_fany_nequal4', - 188: 'nir_op_fany_nequal5', - 189: 'nir_op_fany_nequal8', - 190: 'nir_op_fceil', - 191: 'nir_op_fclamp_pos', - 192: 'nir_op_fcos', - 193: 'nir_op_fcos_amd', - 194: 'nir_op_fcos_mdg', - 195: 'nir_op_fcsel', - 196: 'nir_op_fcsel_ge', - 197: 'nir_op_fcsel_gt', - 198: 'nir_op_fdiv', - 199: 'nir_op_fdot16', - 200: 'nir_op_fdot16_replicated', - 201: 'nir_op_fdot2', - 202: 'nir_op_fdot2_replicated', - 203: 'nir_op_fdot3', - 204: 'nir_op_fdot3_replicated', - 205: 'nir_op_fdot4', - 206: 'nir_op_fdot4_replicated', - 207: 'nir_op_fdot5', - 208: 'nir_op_fdot5_replicated', - 209: 'nir_op_fdot8', - 210: 'nir_op_fdot8_replicated', - 211: 'nir_op_fdph', - 212: 'nir_op_fdph_replicated', - 213: 'nir_op_feq', - 214: 'nir_op_feq16', - 215: 'nir_op_feq32', - 216: 'nir_op_feq8', - 217: 'nir_op_fequ', - 218: 'nir_op_fequ16', - 219: 'nir_op_fequ32', - 220: 'nir_op_fequ8', - 221: 'nir_op_fexp2', - 222: 'nir_op_ffloor', - 223: 'nir_op_ffma', - 224: 'nir_op_ffmaz', - 225: 'nir_op_ffract', - 226: 'nir_op_fge', - 227: 'nir_op_fge16', - 228: 'nir_op_fge32', - 229: 'nir_op_fge8', - 230: 'nir_op_fgeu', - 231: 'nir_op_fgeu16', - 232: 'nir_op_fgeu32', - 233: 'nir_op_fgeu8', - 234: 'nir_op_find_lsb', - 235: 'nir_op_fisfinite', - 236: 'nir_op_fisfinite32', - 237: 'nir_op_fisnormal', - 238: 'nir_op_flog2', - 239: 'nir_op_flrp', - 240: 'nir_op_flt', - 241: 'nir_op_flt16', - 242: 'nir_op_flt32', - 243: 'nir_op_flt8', - 244: 'nir_op_fltu', - 245: 'nir_op_fltu16', - 246: 'nir_op_fltu32', - 247: 'nir_op_fltu8', - 248: 'nir_op_fmax', - 249: 'nir_op_fmax_agx', - 250: 'nir_op_fmin', - 251: 'nir_op_fmin_agx', - 252: 'nir_op_fmod', - 253: 'nir_op_fmul', - 254: 'nir_op_fmulz', - 255: 'nir_op_fneg', - 256: 'nir_op_fneo', - 257: 'nir_op_fneo16', - 258: 'nir_op_fneo32', - 259: 'nir_op_fneo8', - 260: 'nir_op_fneu', - 261: 'nir_op_fneu16', - 262: 'nir_op_fneu32', - 263: 'nir_op_fneu8', - 264: 'nir_op_ford', - 265: 'nir_op_ford16', - 266: 'nir_op_ford32', - 267: 'nir_op_ford8', - 268: 'nir_op_fpow', - 269: 'nir_op_fquantize2f16', - 270: 'nir_op_frcp', - 271: 'nir_op_frem', - 272: 'nir_op_frexp_exp', - 273: 'nir_op_frexp_sig', - 274: 'nir_op_fround_even', - 275: 'nir_op_frsq', - 276: 'nir_op_fsat', - 277: 'nir_op_fsat_signed', - 278: 'nir_op_fsign', - 279: 'nir_op_fsin', - 280: 'nir_op_fsin_agx', - 281: 'nir_op_fsin_amd', - 282: 'nir_op_fsin_mdg', - 283: 'nir_op_fsqrt', - 284: 'nir_op_fsub', - 285: 'nir_op_fsum2', - 286: 'nir_op_fsum3', - 287: 'nir_op_fsum4', - 288: 'nir_op_ftrunc', - 289: 'nir_op_funord', - 290: 'nir_op_funord16', - 291: 'nir_op_funord32', - 292: 'nir_op_funord8', - 293: 'nir_op_i2f16', - 294: 'nir_op_i2f32', - 295: 'nir_op_i2f64', - 296: 'nir_op_i2fmp', - 297: 'nir_op_i2i1', - 298: 'nir_op_i2i16', - 299: 'nir_op_i2i32', - 300: 'nir_op_i2i64', - 301: 'nir_op_i2i8', - 302: 'nir_op_i2imp', - 303: 'nir_op_i32csel_ge', - 304: 'nir_op_i32csel_gt', - 305: 'nir_op_iabs', - 306: 'nir_op_iadd', - 307: 'nir_op_iadd3', - 308: 'nir_op_iadd_sat', - 309: 'nir_op_iand', - 310: 'nir_op_ibfe', - 311: 'nir_op_ibitfield_extract', - 312: 'nir_op_icsel_eqz', - 313: 'nir_op_idiv', - 314: 'nir_op_ieq', - 315: 'nir_op_ieq16', - 316: 'nir_op_ieq32', - 317: 'nir_op_ieq8', - 318: 'nir_op_ifind_msb', - 319: 'nir_op_ifind_msb_rev', - 320: 'nir_op_ige', - 321: 'nir_op_ige16', - 322: 'nir_op_ige32', - 323: 'nir_op_ige8', - 324: 'nir_op_ihadd', - 325: 'nir_op_ilea_agx', - 326: 'nir_op_ilt', - 327: 'nir_op_ilt16', - 328: 'nir_op_ilt32', - 329: 'nir_op_ilt8', - 330: 'nir_op_imad', - 331: 'nir_op_imad24_ir3', - 332: 'nir_op_imadsh_mix16', - 333: 'nir_op_imadshl_agx', - 334: 'nir_op_imax', - 335: 'nir_op_imin', - 336: 'nir_op_imod', - 337: 'nir_op_imsubshl_agx', - 338: 'nir_op_imul', - 339: 'nir_op_imul24', - 340: 'nir_op_imul24_relaxed', - 341: 'nir_op_imul_2x32_64', - 342: 'nir_op_imul_32x16', - 343: 'nir_op_imul_high', - 344: 'nir_op_ine', - 345: 'nir_op_ine16', - 346: 'nir_op_ine32', - 347: 'nir_op_ine8', - 348: 'nir_op_ineg', - 349: 'nir_op_inot', - 350: 'nir_op_insert_u16', - 351: 'nir_op_insert_u8', - 352: 'nir_op_interleave_agx', - 353: 'nir_op_ior', - 354: 'nir_op_irem', - 355: 'nir_op_irhadd', - 356: 'nir_op_ishl', - 357: 'nir_op_ishr', - 358: 'nir_op_isign', - 359: 'nir_op_isub', - 360: 'nir_op_isub_sat', - 361: 'nir_op_ixor', - 362: 'nir_op_ldexp', - 363: 'nir_op_ldexp16_pan', - 364: 'nir_op_lea_nv', - 365: 'nir_op_mov', - 366: 'nir_op_mqsad_4x8', - 367: 'nir_op_msad_4x8', - 368: 'nir_op_pack_2x16_to_snorm_2x8_v3d', - 369: 'nir_op_pack_2x16_to_unorm_10_2_v3d', - 370: 'nir_op_pack_2x16_to_unorm_2x10_v3d', - 371: 'nir_op_pack_2x16_to_unorm_2x8_v3d', - 372: 'nir_op_pack_2x32_to_2x16_v3d', - 373: 'nir_op_pack_32_2x16', - 374: 'nir_op_pack_32_2x16_split', - 375: 'nir_op_pack_32_4x8', - 376: 'nir_op_pack_32_4x8_split', - 377: 'nir_op_pack_32_to_r11g11b10_v3d', - 378: 'nir_op_pack_4x16_to_4x8_v3d', - 379: 'nir_op_pack_64_2x32', - 380: 'nir_op_pack_64_2x32_split', - 381: 'nir_op_pack_64_4x16', - 382: 'nir_op_pack_double_2x32_dxil', - 383: 'nir_op_pack_half_2x16', - 384: 'nir_op_pack_half_2x16_rtz_split', - 385: 'nir_op_pack_half_2x16_split', - 386: 'nir_op_pack_sint_2x16', - 387: 'nir_op_pack_snorm_2x16', - 388: 'nir_op_pack_snorm_4x8', - 389: 'nir_op_pack_uint_2x16', - 390: 'nir_op_pack_uint_32_to_r10g10b10a2_v3d', - 391: 'nir_op_pack_unorm_2x16', - 392: 'nir_op_pack_unorm_4x8', - 393: 'nir_op_pack_uvec2_to_uint', - 394: 'nir_op_pack_uvec4_to_uint', - 395: 'nir_op_prmt_nv', - 396: 'nir_op_sdot_2x16_iadd', - 397: 'nir_op_sdot_2x16_iadd_sat', - 398: 'nir_op_sdot_4x8_iadd', - 399: 'nir_op_sdot_4x8_iadd_sat', - 400: 'nir_op_seq', - 401: 'nir_op_sge', - 402: 'nir_op_shfr', - 403: 'nir_op_shlg_ir3', - 404: 'nir_op_shlm_ir3', - 405: 'nir_op_shrg_ir3', - 406: 'nir_op_shrm_ir3', - 407: 'nir_op_slt', - 408: 'nir_op_sne', - 409: 'nir_op_sudot_4x8_iadd', - 410: 'nir_op_sudot_4x8_iadd_sat', - 411: 'nir_op_u2f16', - 412: 'nir_op_u2f32', - 413: 'nir_op_u2f64', - 414: 'nir_op_u2fmp', - 415: 'nir_op_u2u1', - 416: 'nir_op_u2u16', - 417: 'nir_op_u2u32', - 418: 'nir_op_u2u64', - 419: 'nir_op_u2u8', - 420: 'nir_op_uabs_isub', - 421: 'nir_op_uabs_usub', - 422: 'nir_op_uadd_carry', - 423: 'nir_op_uadd_sat', - 424: 'nir_op_ubfe', - 425: 'nir_op_ubitfield_extract', - 426: 'nir_op_uclz', - 427: 'nir_op_udiv', - 428: 'nir_op_udiv_aligned_4', - 429: 'nir_op_udot_2x16_uadd', - 430: 'nir_op_udot_2x16_uadd_sat', - 431: 'nir_op_udot_4x8_uadd', - 432: 'nir_op_udot_4x8_uadd_sat', - 433: 'nir_op_ufind_msb', - 434: 'nir_op_ufind_msb_rev', - 435: 'nir_op_uge', - 436: 'nir_op_uge16', - 437: 'nir_op_uge32', - 438: 'nir_op_uge8', - 439: 'nir_op_uhadd', - 440: 'nir_op_ulea_agx', - 441: 'nir_op_ult', - 442: 'nir_op_ult16', - 443: 'nir_op_ult32', - 444: 'nir_op_ult8', - 445: 'nir_op_umad24', - 446: 'nir_op_umad24_relaxed', - 447: 'nir_op_umax', - 448: 'nir_op_umax_4x8_vc4', - 449: 'nir_op_umin', - 450: 'nir_op_umin_4x8_vc4', - 451: 'nir_op_umod', - 452: 'nir_op_umul24', - 453: 'nir_op_umul24_relaxed', - 454: 'nir_op_umul_2x32_64', - 455: 'nir_op_umul_32x16', - 456: 'nir_op_umul_high', - 457: 'nir_op_umul_low', - 458: 'nir_op_umul_unorm_4x8_vc4', - 459: 'nir_op_unpack_32_2x16', - 460: 'nir_op_unpack_32_2x16_split_x', - 461: 'nir_op_unpack_32_2x16_split_y', - 462: 'nir_op_unpack_32_4x8', - 463: 'nir_op_unpack_64_2x32', - 464: 'nir_op_unpack_64_2x32_split_x', - 465: 'nir_op_unpack_64_2x32_split_y', - 466: 'nir_op_unpack_64_4x16', - 467: 'nir_op_unpack_double_2x32_dxil', - 468: 'nir_op_unpack_half_2x16', - 469: 'nir_op_unpack_half_2x16_split_x', - 470: 'nir_op_unpack_half_2x16_split_y', - 471: 'nir_op_unpack_snorm_2x16', - 472: 'nir_op_unpack_snorm_4x8', - 473: 'nir_op_unpack_unorm_2x16', - 474: 'nir_op_unpack_unorm_4x8', - 475: 'nir_op_urhadd', - 476: 'nir_op_urol', - 477: 'nir_op_uror', - 478: 'nir_op_usadd_4x8_vc4', - 479: 'nir_op_ushr', - 480: 'nir_op_ussub_4x8_vc4', - 481: 'nir_op_usub_borrow', - 482: 'nir_op_usub_sat', - 483: 'nir_op_vec16', - 484: 'nir_op_vec2', - 485: 'nir_op_vec3', - 486: 'nir_op_vec4', - 487: 'nir_op_vec5', - 488: 'nir_op_vec8', - 488: 'nir_last_opcode', - 489: 'nir_num_opcodes', -} -nir_op_alignbyte_amd = 0 -nir_op_amul = 1 -nir_op_andg_ir3 = 2 -nir_op_b16all_fequal16 = 3 -nir_op_b16all_fequal2 = 4 -nir_op_b16all_fequal3 = 5 -nir_op_b16all_fequal4 = 6 -nir_op_b16all_fequal5 = 7 -nir_op_b16all_fequal8 = 8 -nir_op_b16all_iequal16 = 9 -nir_op_b16all_iequal2 = 10 -nir_op_b16all_iequal3 = 11 -nir_op_b16all_iequal4 = 12 -nir_op_b16all_iequal5 = 13 -nir_op_b16all_iequal8 = 14 -nir_op_b16any_fnequal16 = 15 -nir_op_b16any_fnequal2 = 16 -nir_op_b16any_fnequal3 = 17 -nir_op_b16any_fnequal4 = 18 -nir_op_b16any_fnequal5 = 19 -nir_op_b16any_fnequal8 = 20 -nir_op_b16any_inequal16 = 21 -nir_op_b16any_inequal2 = 22 -nir_op_b16any_inequal3 = 23 -nir_op_b16any_inequal4 = 24 -nir_op_b16any_inequal5 = 25 -nir_op_b16any_inequal8 = 26 -nir_op_b16csel = 27 -nir_op_b2b1 = 28 -nir_op_b2b16 = 29 -nir_op_b2b32 = 30 -nir_op_b2b8 = 31 -nir_op_b2f16 = 32 -nir_op_b2f32 = 33 -nir_op_b2f64 = 34 -nir_op_b2i1 = 35 -nir_op_b2i16 = 36 -nir_op_b2i32 = 37 -nir_op_b2i64 = 38 -nir_op_b2i8 = 39 -nir_op_b32all_fequal16 = 40 -nir_op_b32all_fequal2 = 41 -nir_op_b32all_fequal3 = 42 -nir_op_b32all_fequal4 = 43 -nir_op_b32all_fequal5 = 44 -nir_op_b32all_fequal8 = 45 -nir_op_b32all_iequal16 = 46 -nir_op_b32all_iequal2 = 47 -nir_op_b32all_iequal3 = 48 -nir_op_b32all_iequal4 = 49 -nir_op_b32all_iequal5 = 50 -nir_op_b32all_iequal8 = 51 -nir_op_b32any_fnequal16 = 52 -nir_op_b32any_fnequal2 = 53 -nir_op_b32any_fnequal3 = 54 -nir_op_b32any_fnequal4 = 55 -nir_op_b32any_fnequal5 = 56 -nir_op_b32any_fnequal8 = 57 -nir_op_b32any_inequal16 = 58 -nir_op_b32any_inequal2 = 59 -nir_op_b32any_inequal3 = 60 -nir_op_b32any_inequal4 = 61 -nir_op_b32any_inequal5 = 62 -nir_op_b32any_inequal8 = 63 -nir_op_b32csel = 64 -nir_op_b32fcsel_mdg = 65 -nir_op_b8all_fequal16 = 66 -nir_op_b8all_fequal2 = 67 -nir_op_b8all_fequal3 = 68 -nir_op_b8all_fequal4 = 69 -nir_op_b8all_fequal5 = 70 -nir_op_b8all_fequal8 = 71 -nir_op_b8all_iequal16 = 72 -nir_op_b8all_iequal2 = 73 -nir_op_b8all_iequal3 = 74 -nir_op_b8all_iequal4 = 75 -nir_op_b8all_iequal5 = 76 -nir_op_b8all_iequal8 = 77 -nir_op_b8any_fnequal16 = 78 -nir_op_b8any_fnequal2 = 79 -nir_op_b8any_fnequal3 = 80 -nir_op_b8any_fnequal4 = 81 -nir_op_b8any_fnequal5 = 82 -nir_op_b8any_fnequal8 = 83 -nir_op_b8any_inequal16 = 84 -nir_op_b8any_inequal2 = 85 -nir_op_b8any_inequal3 = 86 -nir_op_b8any_inequal4 = 87 -nir_op_b8any_inequal5 = 88 -nir_op_b8any_inequal8 = 89 -nir_op_b8csel = 90 -nir_op_ball_fequal16 = 91 -nir_op_ball_fequal2 = 92 -nir_op_ball_fequal3 = 93 -nir_op_ball_fequal4 = 94 -nir_op_ball_fequal5 = 95 -nir_op_ball_fequal8 = 96 -nir_op_ball_iequal16 = 97 -nir_op_ball_iequal2 = 98 -nir_op_ball_iequal3 = 99 -nir_op_ball_iequal4 = 100 -nir_op_ball_iequal5 = 101 -nir_op_ball_iequal8 = 102 -nir_op_bany_fnequal16 = 103 -nir_op_bany_fnequal2 = 104 -nir_op_bany_fnequal3 = 105 -nir_op_bany_fnequal4 = 106 -nir_op_bany_fnequal5 = 107 -nir_op_bany_fnequal8 = 108 -nir_op_bany_inequal16 = 109 -nir_op_bany_inequal2 = 110 -nir_op_bany_inequal3 = 111 -nir_op_bany_inequal4 = 112 -nir_op_bany_inequal5 = 113 -nir_op_bany_inequal8 = 114 -nir_op_bcsel = 115 -nir_op_bf2f = 116 -nir_op_bfdot16 = 117 -nir_op_bfdot2 = 118 -nir_op_bfdot2_bfadd = 119 -nir_op_bfdot3 = 120 -nir_op_bfdot4 = 121 -nir_op_bfdot5 = 122 -nir_op_bfdot8 = 123 -nir_op_bffma = 124 -nir_op_bfi = 125 -nir_op_bfm = 126 -nir_op_bfmul = 127 -nir_op_bit_count = 128 -nir_op_bitfield_insert = 129 -nir_op_bitfield_reverse = 130 -nir_op_bitfield_select = 131 -nir_op_bitnz = 132 -nir_op_bitnz16 = 133 -nir_op_bitnz32 = 134 -nir_op_bitnz8 = 135 -nir_op_bitz = 136 -nir_op_bitz16 = 137 -nir_op_bitz32 = 138 -nir_op_bitz8 = 139 -nir_op_bounds_agx = 140 -nir_op_byte_perm_amd = 141 -nir_op_cube_amd = 142 -nir_op_e4m3fn2f = 143 -nir_op_e5m22f = 144 -nir_op_extr_agx = 145 -nir_op_extract_i16 = 146 -nir_op_extract_i8 = 147 -nir_op_extract_u16 = 148 -nir_op_extract_u8 = 149 -nir_op_f2bf = 150 -nir_op_f2e4m3fn = 151 -nir_op_f2e4m3fn_sat = 152 -nir_op_f2e4m3fn_satfn = 153 -nir_op_f2e5m2 = 154 -nir_op_f2e5m2_sat = 155 -nir_op_f2f16 = 156 -nir_op_f2f16_rtne = 157 -nir_op_f2f16_rtz = 158 -nir_op_f2f32 = 159 -nir_op_f2f64 = 160 -nir_op_f2fmp = 161 -nir_op_f2i1 = 162 -nir_op_f2i16 = 163 -nir_op_f2i32 = 164 -nir_op_f2i64 = 165 -nir_op_f2i8 = 166 -nir_op_f2imp = 167 -nir_op_f2snorm_16_v3d = 168 -nir_op_f2u1 = 169 -nir_op_f2u16 = 170 -nir_op_f2u32 = 171 -nir_op_f2u64 = 172 -nir_op_f2u8 = 173 -nir_op_f2ump = 174 -nir_op_f2unorm_16_v3d = 175 -nir_op_fabs = 176 -nir_op_fadd = 177 -nir_op_fall_equal16 = 178 -nir_op_fall_equal2 = 179 -nir_op_fall_equal3 = 180 -nir_op_fall_equal4 = 181 -nir_op_fall_equal5 = 182 -nir_op_fall_equal8 = 183 -nir_op_fany_nequal16 = 184 -nir_op_fany_nequal2 = 185 -nir_op_fany_nequal3 = 186 -nir_op_fany_nequal4 = 187 -nir_op_fany_nequal5 = 188 -nir_op_fany_nequal8 = 189 -nir_op_fceil = 190 -nir_op_fclamp_pos = 191 -nir_op_fcos = 192 -nir_op_fcos_amd = 193 -nir_op_fcos_mdg = 194 -nir_op_fcsel = 195 -nir_op_fcsel_ge = 196 -nir_op_fcsel_gt = 197 -nir_op_fdiv = 198 -nir_op_fdot16 = 199 -nir_op_fdot16_replicated = 200 -nir_op_fdot2 = 201 -nir_op_fdot2_replicated = 202 -nir_op_fdot3 = 203 -nir_op_fdot3_replicated = 204 -nir_op_fdot4 = 205 -nir_op_fdot4_replicated = 206 -nir_op_fdot5 = 207 -nir_op_fdot5_replicated = 208 -nir_op_fdot8 = 209 -nir_op_fdot8_replicated = 210 -nir_op_fdph = 211 -nir_op_fdph_replicated = 212 -nir_op_feq = 213 -nir_op_feq16 = 214 -nir_op_feq32 = 215 -nir_op_feq8 = 216 -nir_op_fequ = 217 -nir_op_fequ16 = 218 -nir_op_fequ32 = 219 -nir_op_fequ8 = 220 -nir_op_fexp2 = 221 -nir_op_ffloor = 222 -nir_op_ffma = 223 -nir_op_ffmaz = 224 -nir_op_ffract = 225 -nir_op_fge = 226 -nir_op_fge16 = 227 -nir_op_fge32 = 228 -nir_op_fge8 = 229 -nir_op_fgeu = 230 -nir_op_fgeu16 = 231 -nir_op_fgeu32 = 232 -nir_op_fgeu8 = 233 -nir_op_find_lsb = 234 -nir_op_fisfinite = 235 -nir_op_fisfinite32 = 236 -nir_op_fisnormal = 237 -nir_op_flog2 = 238 -nir_op_flrp = 239 -nir_op_flt = 240 -nir_op_flt16 = 241 -nir_op_flt32 = 242 -nir_op_flt8 = 243 -nir_op_fltu = 244 -nir_op_fltu16 = 245 -nir_op_fltu32 = 246 -nir_op_fltu8 = 247 -nir_op_fmax = 248 -nir_op_fmax_agx = 249 -nir_op_fmin = 250 -nir_op_fmin_agx = 251 -nir_op_fmod = 252 -nir_op_fmul = 253 -nir_op_fmulz = 254 -nir_op_fneg = 255 -nir_op_fneo = 256 -nir_op_fneo16 = 257 -nir_op_fneo32 = 258 -nir_op_fneo8 = 259 -nir_op_fneu = 260 -nir_op_fneu16 = 261 -nir_op_fneu32 = 262 -nir_op_fneu8 = 263 -nir_op_ford = 264 -nir_op_ford16 = 265 -nir_op_ford32 = 266 -nir_op_ford8 = 267 -nir_op_fpow = 268 -nir_op_fquantize2f16 = 269 -nir_op_frcp = 270 -nir_op_frem = 271 -nir_op_frexp_exp = 272 -nir_op_frexp_sig = 273 -nir_op_fround_even = 274 -nir_op_frsq = 275 -nir_op_fsat = 276 -nir_op_fsat_signed = 277 -nir_op_fsign = 278 -nir_op_fsin = 279 -nir_op_fsin_agx = 280 -nir_op_fsin_amd = 281 -nir_op_fsin_mdg = 282 -nir_op_fsqrt = 283 -nir_op_fsub = 284 -nir_op_fsum2 = 285 -nir_op_fsum3 = 286 -nir_op_fsum4 = 287 -nir_op_ftrunc = 288 -nir_op_funord = 289 -nir_op_funord16 = 290 -nir_op_funord32 = 291 -nir_op_funord8 = 292 -nir_op_i2f16 = 293 -nir_op_i2f32 = 294 -nir_op_i2f64 = 295 -nir_op_i2fmp = 296 -nir_op_i2i1 = 297 -nir_op_i2i16 = 298 -nir_op_i2i32 = 299 -nir_op_i2i64 = 300 -nir_op_i2i8 = 301 -nir_op_i2imp = 302 -nir_op_i32csel_ge = 303 -nir_op_i32csel_gt = 304 -nir_op_iabs = 305 -nir_op_iadd = 306 -nir_op_iadd3 = 307 -nir_op_iadd_sat = 308 -nir_op_iand = 309 -nir_op_ibfe = 310 -nir_op_ibitfield_extract = 311 -nir_op_icsel_eqz = 312 -nir_op_idiv = 313 -nir_op_ieq = 314 -nir_op_ieq16 = 315 -nir_op_ieq32 = 316 -nir_op_ieq8 = 317 -nir_op_ifind_msb = 318 -nir_op_ifind_msb_rev = 319 -nir_op_ige = 320 -nir_op_ige16 = 321 -nir_op_ige32 = 322 -nir_op_ige8 = 323 -nir_op_ihadd = 324 -nir_op_ilea_agx = 325 -nir_op_ilt = 326 -nir_op_ilt16 = 327 -nir_op_ilt32 = 328 -nir_op_ilt8 = 329 -nir_op_imad = 330 -nir_op_imad24_ir3 = 331 -nir_op_imadsh_mix16 = 332 -nir_op_imadshl_agx = 333 -nir_op_imax = 334 -nir_op_imin = 335 -nir_op_imod = 336 -nir_op_imsubshl_agx = 337 -nir_op_imul = 338 -nir_op_imul24 = 339 -nir_op_imul24_relaxed = 340 -nir_op_imul_2x32_64 = 341 -nir_op_imul_32x16 = 342 -nir_op_imul_high = 343 -nir_op_ine = 344 -nir_op_ine16 = 345 -nir_op_ine32 = 346 -nir_op_ine8 = 347 -nir_op_ineg = 348 -nir_op_inot = 349 -nir_op_insert_u16 = 350 -nir_op_insert_u8 = 351 -nir_op_interleave_agx = 352 -nir_op_ior = 353 -nir_op_irem = 354 -nir_op_irhadd = 355 -nir_op_ishl = 356 -nir_op_ishr = 357 -nir_op_isign = 358 -nir_op_isub = 359 -nir_op_isub_sat = 360 -nir_op_ixor = 361 -nir_op_ldexp = 362 -nir_op_ldexp16_pan = 363 -nir_op_lea_nv = 364 -nir_op_mov = 365 -nir_op_mqsad_4x8 = 366 -nir_op_msad_4x8 = 367 -nir_op_pack_2x16_to_snorm_2x8_v3d = 368 -nir_op_pack_2x16_to_unorm_10_2_v3d = 369 -nir_op_pack_2x16_to_unorm_2x10_v3d = 370 -nir_op_pack_2x16_to_unorm_2x8_v3d = 371 -nir_op_pack_2x32_to_2x16_v3d = 372 -nir_op_pack_32_2x16 = 373 -nir_op_pack_32_2x16_split = 374 -nir_op_pack_32_4x8 = 375 -nir_op_pack_32_4x8_split = 376 -nir_op_pack_32_to_r11g11b10_v3d = 377 -nir_op_pack_4x16_to_4x8_v3d = 378 -nir_op_pack_64_2x32 = 379 -nir_op_pack_64_2x32_split = 380 -nir_op_pack_64_4x16 = 381 -nir_op_pack_double_2x32_dxil = 382 -nir_op_pack_half_2x16 = 383 -nir_op_pack_half_2x16_rtz_split = 384 -nir_op_pack_half_2x16_split = 385 -nir_op_pack_sint_2x16 = 386 -nir_op_pack_snorm_2x16 = 387 -nir_op_pack_snorm_4x8 = 388 -nir_op_pack_uint_2x16 = 389 -nir_op_pack_uint_32_to_r10g10b10a2_v3d = 390 -nir_op_pack_unorm_2x16 = 391 -nir_op_pack_unorm_4x8 = 392 -nir_op_pack_uvec2_to_uint = 393 -nir_op_pack_uvec4_to_uint = 394 -nir_op_prmt_nv = 395 -nir_op_sdot_2x16_iadd = 396 -nir_op_sdot_2x16_iadd_sat = 397 -nir_op_sdot_4x8_iadd = 398 -nir_op_sdot_4x8_iadd_sat = 399 -nir_op_seq = 400 -nir_op_sge = 401 -nir_op_shfr = 402 -nir_op_shlg_ir3 = 403 -nir_op_shlm_ir3 = 404 -nir_op_shrg_ir3 = 405 -nir_op_shrm_ir3 = 406 -nir_op_slt = 407 -nir_op_sne = 408 -nir_op_sudot_4x8_iadd = 409 -nir_op_sudot_4x8_iadd_sat = 410 -nir_op_u2f16 = 411 -nir_op_u2f32 = 412 -nir_op_u2f64 = 413 -nir_op_u2fmp = 414 -nir_op_u2u1 = 415 -nir_op_u2u16 = 416 -nir_op_u2u32 = 417 -nir_op_u2u64 = 418 -nir_op_u2u8 = 419 -nir_op_uabs_isub = 420 -nir_op_uabs_usub = 421 -nir_op_uadd_carry = 422 -nir_op_uadd_sat = 423 -nir_op_ubfe = 424 -nir_op_ubitfield_extract = 425 -nir_op_uclz = 426 -nir_op_udiv = 427 -nir_op_udiv_aligned_4 = 428 -nir_op_udot_2x16_uadd = 429 -nir_op_udot_2x16_uadd_sat = 430 -nir_op_udot_4x8_uadd = 431 -nir_op_udot_4x8_uadd_sat = 432 -nir_op_ufind_msb = 433 -nir_op_ufind_msb_rev = 434 -nir_op_uge = 435 -nir_op_uge16 = 436 -nir_op_uge32 = 437 -nir_op_uge8 = 438 -nir_op_uhadd = 439 -nir_op_ulea_agx = 440 -nir_op_ult = 441 -nir_op_ult16 = 442 -nir_op_ult32 = 443 -nir_op_ult8 = 444 -nir_op_umad24 = 445 -nir_op_umad24_relaxed = 446 -nir_op_umax = 447 -nir_op_umax_4x8_vc4 = 448 -nir_op_umin = 449 -nir_op_umin_4x8_vc4 = 450 -nir_op_umod = 451 -nir_op_umul24 = 452 -nir_op_umul24_relaxed = 453 -nir_op_umul_2x32_64 = 454 -nir_op_umul_32x16 = 455 -nir_op_umul_high = 456 -nir_op_umul_low = 457 -nir_op_umul_unorm_4x8_vc4 = 458 -nir_op_unpack_32_2x16 = 459 -nir_op_unpack_32_2x16_split_x = 460 -nir_op_unpack_32_2x16_split_y = 461 -nir_op_unpack_32_4x8 = 462 -nir_op_unpack_64_2x32 = 463 -nir_op_unpack_64_2x32_split_x = 464 -nir_op_unpack_64_2x32_split_y = 465 -nir_op_unpack_64_4x16 = 466 -nir_op_unpack_double_2x32_dxil = 467 -nir_op_unpack_half_2x16 = 468 -nir_op_unpack_half_2x16_split_x = 469 -nir_op_unpack_half_2x16_split_y = 470 -nir_op_unpack_snorm_2x16 = 471 -nir_op_unpack_snorm_4x8 = 472 -nir_op_unpack_unorm_2x16 = 473 -nir_op_unpack_unorm_4x8 = 474 -nir_op_urhadd = 475 -nir_op_urol = 476 -nir_op_uror = 477 -nir_op_usadd_4x8_vc4 = 478 -nir_op_ushr = 479 -nir_op_ussub_4x8_vc4 = 480 -nir_op_usub_borrow = 481 -nir_op_usub_sat = 482 -nir_op_vec16 = 483 -nir_op_vec2 = 484 -nir_op_vec3 = 485 -nir_op_vec4 = 486 -nir_op_vec5 = 487 -nir_op_vec8 = 488 -nir_last_opcode = 488 -nir_num_opcodes = 489 -c__EA_nir_op = ctypes.c_uint32 # enum -nir_op = c__EA_nir_op -nir_op__enumvalues = c__EA_nir_op__enumvalues -try: - nir_type_conversion_op = _libraries['libtinymesa_cpu.so'].nir_type_conversion_op - nir_type_conversion_op.restype = nir_op - nir_type_conversion_op.argtypes = [nir_alu_type, nir_alu_type, nir_rounding_mode] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_atomic_op' -c__EA_nir_atomic_op__enumvalues = { - 0: 'nir_atomic_op_iadd', - 1: 'nir_atomic_op_imin', - 2: 'nir_atomic_op_umin', - 3: 'nir_atomic_op_imax', - 4: 'nir_atomic_op_umax', - 5: 'nir_atomic_op_iand', - 6: 'nir_atomic_op_ior', - 7: 'nir_atomic_op_ixor', - 8: 'nir_atomic_op_xchg', - 9: 'nir_atomic_op_fadd', - 10: 'nir_atomic_op_fmin', - 11: 'nir_atomic_op_fmax', - 12: 'nir_atomic_op_cmpxchg', - 13: 'nir_atomic_op_fcmpxchg', - 14: 'nir_atomic_op_inc_wrap', - 15: 'nir_atomic_op_dec_wrap', - 16: 'nir_atomic_op_ordered_add_gfx12_amd', -} -nir_atomic_op_iadd = 0 -nir_atomic_op_imin = 1 -nir_atomic_op_umin = 2 -nir_atomic_op_imax = 3 -nir_atomic_op_umax = 4 -nir_atomic_op_iand = 5 -nir_atomic_op_ior = 6 -nir_atomic_op_ixor = 7 -nir_atomic_op_xchg = 8 -nir_atomic_op_fadd = 9 -nir_atomic_op_fmin = 10 -nir_atomic_op_fmax = 11 -nir_atomic_op_cmpxchg = 12 -nir_atomic_op_fcmpxchg = 13 -nir_atomic_op_inc_wrap = 14 -nir_atomic_op_dec_wrap = 15 -nir_atomic_op_ordered_add_gfx12_amd = 16 -c__EA_nir_atomic_op = ctypes.c_uint32 # enum -nir_atomic_op = c__EA_nir_atomic_op -nir_atomic_op__enumvalues = c__EA_nir_atomic_op__enumvalues -try: - nir_atomic_op_type = _libraries['FIXME_STUB'].nir_atomic_op_type - nir_atomic_op_type.restype = nir_alu_type - nir_atomic_op_type.argtypes = [nir_atomic_op] -except AttributeError: - pass -try: - nir_atomic_op_to_alu = _libraries['libtinymesa_cpu.so'].nir_atomic_op_to_alu - nir_atomic_op_to_alu.restype = nir_op - nir_atomic_op_to_alu.argtypes = [nir_atomic_op] -except AttributeError: - pass -try: - nir_op_vec = _libraries['libtinymesa_cpu.so'].nir_op_vec - nir_op_vec.restype = nir_op - nir_op_vec.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - nir_op_is_vec = _libraries['libtinymesa_cpu.so'].nir_op_is_vec - nir_op_is_vec.restype = ctypes.c_bool - nir_op_is_vec.argtypes = [nir_op] -except AttributeError: - pass -try: - nir_op_is_vec_or_mov = _libraries['FIXME_STUB'].nir_op_is_vec_or_mov - nir_op_is_vec_or_mov.restype = ctypes.c_bool - nir_op_is_vec_or_mov.argtypes = [nir_op] -except AttributeError: - pass -try: - nir_is_float_control_signed_zero_preserve = _libraries['FIXME_STUB'].nir_is_float_control_signed_zero_preserve - nir_is_float_control_signed_zero_preserve.restype = ctypes.c_bool - nir_is_float_control_signed_zero_preserve.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_float_control_inf_preserve = _libraries['FIXME_STUB'].nir_is_float_control_inf_preserve - nir_is_float_control_inf_preserve.restype = ctypes.c_bool - nir_is_float_control_inf_preserve.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_float_control_nan_preserve = _libraries['FIXME_STUB'].nir_is_float_control_nan_preserve - nir_is_float_control_nan_preserve.restype = ctypes.c_bool - nir_is_float_control_nan_preserve.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_float_control_signed_zero_inf_nan_preserve = _libraries['FIXME_STUB'].nir_is_float_control_signed_zero_inf_nan_preserve - nir_is_float_control_signed_zero_inf_nan_preserve.restype = ctypes.c_bool - nir_is_float_control_signed_zero_inf_nan_preserve.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_denorm_flush_to_zero = _libraries['FIXME_STUB'].nir_is_denorm_flush_to_zero - nir_is_denorm_flush_to_zero.restype = ctypes.c_bool - nir_is_denorm_flush_to_zero.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_denorm_preserve = _libraries['FIXME_STUB'].nir_is_denorm_preserve - nir_is_denorm_preserve.restype = ctypes.c_bool - nir_is_denorm_preserve.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_rounding_mode_rtne = _libraries['FIXME_STUB'].nir_is_rounding_mode_rtne - nir_is_rounding_mode_rtne.restype = ctypes.c_bool - nir_is_rounding_mode_rtne.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_is_rounding_mode_rtz = _libraries['FIXME_STUB'].nir_is_rounding_mode_rtz - nir_is_rounding_mode_rtz.restype = ctypes.c_bool - nir_is_rounding_mode_rtz.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_has_any_rounding_mode_rtz = _libraries['FIXME_STUB'].nir_has_any_rounding_mode_rtz - nir_has_any_rounding_mode_rtz.restype = ctypes.c_bool - nir_has_any_rounding_mode_rtz.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - nir_has_any_rounding_mode_rtne = _libraries['FIXME_STUB'].nir_has_any_rounding_mode_rtne - nir_has_any_rounding_mode_rtne.restype = ctypes.c_bool - nir_has_any_rounding_mode_rtne.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - nir_get_rounding_mode_from_float_controls = _libraries['FIXME_STUB'].nir_get_rounding_mode_from_float_controls - nir_get_rounding_mode_from_float_controls.restype = nir_rounding_mode - nir_get_rounding_mode_from_float_controls.argtypes = [ctypes.c_uint32, nir_alu_type] -except AttributeError: - pass -try: - nir_has_any_rounding_mode_enabled = _libraries['FIXME_STUB'].nir_has_any_rounding_mode_enabled - nir_has_any_rounding_mode_enabled.restype = ctypes.c_bool - nir_has_any_rounding_mode_enabled.argtypes = [ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_op_algebraic_property' -c__EA_nir_op_algebraic_property__enumvalues = { - 1: 'NIR_OP_IS_2SRC_COMMUTATIVE', - 2: 'NIR_OP_IS_ASSOCIATIVE', - 4: 'NIR_OP_IS_SELECTION', -} -NIR_OP_IS_2SRC_COMMUTATIVE = 1 -NIR_OP_IS_ASSOCIATIVE = 2 -NIR_OP_IS_SELECTION = 4 -c__EA_nir_op_algebraic_property = ctypes.c_uint32 # enum -nir_op_algebraic_property = c__EA_nir_op_algebraic_property -nir_op_algebraic_property__enumvalues = c__EA_nir_op_algebraic_property__enumvalues -class struct_nir_op_info(Structure): - pass - -struct_nir_op_info._pack_ = 1 # source:False -struct_nir_op_info._fields_ = [ - ('name', ctypes.POINTER(ctypes.c_char)), - ('num_inputs', ctypes.c_ubyte), - ('output_size', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('output_type', nir_alu_type), - ('input_sizes', ctypes.c_ubyte * 16), - ('input_types', c__EA_nir_alu_type * 16), - ('algebraic_properties', nir_op_algebraic_property), - ('is_conversion', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -nir_op_info = struct_nir_op_info -try: nir_op_infos = (struct_nir_op_info * 489).in_dll(_libraries['libtinymesa_cpu.so'], 'nir_op_infos') -except (AttributeError, ValueError): pass -try: - nir_op_is_selection = _libraries['FIXME_STUB'].nir_op_is_selection - nir_op_is_selection.restype = ctypes.c_bool - nir_op_is_selection.argtypes = [nir_op] -except AttributeError: - pass -class struct_nir_alu_instr(Structure): - pass - -struct_nir_alu_instr._pack_ = 1 # source:False -struct_nir_alu_instr._fields_ = [ - ('instr', nir_instr), - ('op', nir_op), - ('exact', ctypes.c_bool, 1), - ('no_signed_wrap', ctypes.c_bool, 1), - ('no_unsigned_wrap', ctypes.c_bool, 1), - ('fp_fast_math', ctypes.c_uint32, 9), - ('PADDING_0', ctypes.c_uint32, 20), - ('def', nir_def), - ('src', struct_nir_alu_src * 0), -] - -nir_alu_instr = struct_nir_alu_instr -try: - nir_alu_instr_is_signed_zero_preserve = _libraries['FIXME_STUB'].nir_alu_instr_is_signed_zero_preserve - nir_alu_instr_is_signed_zero_preserve.restype = ctypes.c_bool - nir_alu_instr_is_signed_zero_preserve.argtypes = [ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_alu_instr_is_inf_preserve = _libraries['FIXME_STUB'].nir_alu_instr_is_inf_preserve - nir_alu_instr_is_inf_preserve.restype = ctypes.c_bool - nir_alu_instr_is_inf_preserve.argtypes = [ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_alu_instr_is_nan_preserve = _libraries['FIXME_STUB'].nir_alu_instr_is_nan_preserve - nir_alu_instr_is_nan_preserve.restype = ctypes.c_bool - nir_alu_instr_is_nan_preserve.argtypes = [ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_alu_instr_is_signed_zero_inf_nan_preserve = _libraries['FIXME_STUB'].nir_alu_instr_is_signed_zero_inf_nan_preserve - nir_alu_instr_is_signed_zero_inf_nan_preserve.restype = ctypes.c_bool - nir_alu_instr_is_signed_zero_inf_nan_preserve.argtypes = [ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_alu_src_copy = _libraries['libtinymesa_cpu.so'].nir_alu_src_copy - nir_alu_src_copy.restype = None - nir_alu_src_copy.argtypes = [ctypes.POINTER(struct_nir_alu_src), ctypes.POINTER(struct_nir_alu_src)] -except AttributeError: - pass -try: - nir_alu_instr_src_read_mask = _libraries['libtinymesa_cpu.so'].nir_alu_instr_src_read_mask - nir_alu_instr_src_read_mask.restype = nir_component_mask_t - nir_alu_instr_src_read_mask.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_ssa_alu_instr_src_components = _libraries['libtinymesa_cpu.so'].nir_ssa_alu_instr_src_components - nir_ssa_alu_instr_src_components.restype = ctypes.c_uint32 - nir_ssa_alu_instr_src_components.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_alu_instr_channel_used = _libraries['FIXME_STUB'].nir_alu_instr_channel_used - nir_alu_instr_channel_used.restype = ctypes.c_bool - nir_alu_instr_channel_used.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_alu_instr_is_comparison = _libraries['libtinymesa_cpu.so'].nir_alu_instr_is_comparison - nir_alu_instr_is_comparison.restype = ctypes.c_bool - nir_alu_instr_is_comparison.argtypes = [ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_const_value_negative_equal = _libraries['libtinymesa_cpu.so'].nir_const_value_negative_equal - nir_const_value_negative_equal.restype = ctypes.c_bool - nir_const_value_negative_equal.argtypes = [nir_const_value, nir_const_value, nir_alu_type] -except AttributeError: - pass -try: - nir_alu_srcs_equal = _libraries['libtinymesa_cpu.so'].nir_alu_srcs_equal - nir_alu_srcs_equal.restype = ctypes.c_bool - nir_alu_srcs_equal.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_alu_srcs_negative_equal_typed = _libraries['libtinymesa_cpu.so'].nir_alu_srcs_negative_equal_typed - nir_alu_srcs_negative_equal_typed.restype = ctypes.c_bool - nir_alu_srcs_negative_equal_typed.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32, nir_alu_type] -except AttributeError: - pass -try: - nir_alu_srcs_negative_equal = _libraries['libtinymesa_cpu.so'].nir_alu_srcs_negative_equal - nir_alu_srcs_negative_equal.restype = ctypes.c_bool - nir_alu_srcs_negative_equal.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_alu_src_is_trivial_ssa = _libraries['libtinymesa_cpu.so'].nir_alu_src_is_trivial_ssa - nir_alu_src_is_trivial_ssa.restype = ctypes.c_bool - nir_alu_src_is_trivial_ssa.argtypes = [ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_deref_type' -c__EA_nir_deref_type__enumvalues = { - 0: 'nir_deref_type_var', - 1: 'nir_deref_type_array', - 2: 'nir_deref_type_array_wildcard', - 3: 'nir_deref_type_ptr_as_array', - 4: 'nir_deref_type_struct', - 5: 'nir_deref_type_cast', -} -nir_deref_type_var = 0 -nir_deref_type_array = 1 -nir_deref_type_array_wildcard = 2 -nir_deref_type_ptr_as_array = 3 -nir_deref_type_struct = 4 -nir_deref_type_cast = 5 -c__EA_nir_deref_type = ctypes.c_uint32 # enum -nir_deref_type = c__EA_nir_deref_type -nir_deref_type__enumvalues = c__EA_nir_deref_type__enumvalues -class struct_nir_deref_instr(Structure): - pass - -class union_nir_deref_instr_0(Union): - pass - -union_nir_deref_instr_0._pack_ = 1 # source:False -union_nir_deref_instr_0._fields_ = [ - ('var', ctypes.POINTER(struct_nir_variable)), - ('parent', nir_src), -] - -class union_nir_deref_instr_1(Union): - pass - -class struct_nir_deref_instr_1_arr(Structure): - pass - -struct_nir_deref_instr_1_arr._pack_ = 1 # source:False -struct_nir_deref_instr_1_arr._fields_ = [ - ('index', nir_src), - ('in_bounds', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -class struct_nir_deref_instr_1_strct(Structure): - pass - -struct_nir_deref_instr_1_strct._pack_ = 1 # source:False -struct_nir_deref_instr_1_strct._fields_ = [ - ('index', ctypes.c_uint32), -] - -class struct_nir_deref_instr_1_cast(Structure): - pass - -struct_nir_deref_instr_1_cast._pack_ = 1 # source:False -struct_nir_deref_instr_1_cast._fields_ = [ - ('ptr_stride', ctypes.c_uint32), - ('align_mul', ctypes.c_uint32), - ('align_offset', ctypes.c_uint32), -] - -union_nir_deref_instr_1._pack_ = 1 # source:False -union_nir_deref_instr_1._fields_ = [ - ('arr', struct_nir_deref_instr_1_arr), - ('strct', struct_nir_deref_instr_1_strct), - ('cast', struct_nir_deref_instr_1_cast), - ('PADDING_0', ctypes.c_ubyte * 28), -] - -struct_nir_deref_instr._pack_ = 1 # source:False -struct_nir_deref_instr._anonymous_ = ('_0', '_1',) -struct_nir_deref_instr._fields_ = [ - ('instr', nir_instr), - ('deref_type', nir_deref_type), - ('modes', c__EA_nir_variable_mode), - ('type', ctypes.POINTER(struct_glsl_type)), - ('_0', union_nir_deref_instr_0), - ('_1', union_nir_deref_instr_1), - ('def', nir_def), -] - -nir_deref_instr = struct_nir_deref_instr -try: - nir_deref_cast_is_trivial = _libraries['libtinymesa_cpu.so'].nir_deref_cast_is_trivial - nir_deref_cast_is_trivial.restype = ctypes.c_bool - nir_deref_cast_is_trivial.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -nir_variable_mode = c__EA_nir_variable_mode -nir_variable_mode__enumvalues = c__EA_nir_variable_mode__enumvalues -try: - nir_deref_mode_may_be = _libraries['FIXME_STUB'].nir_deref_mode_may_be - nir_deref_mode_may_be.restype = ctypes.c_bool - nir_deref_mode_may_be.argtypes = [ctypes.POINTER(struct_nir_deref_instr), nir_variable_mode] -except AttributeError: - pass -try: - nir_deref_mode_must_be = _libraries['FIXME_STUB'].nir_deref_mode_must_be - nir_deref_mode_must_be.restype = ctypes.c_bool - nir_deref_mode_must_be.argtypes = [ctypes.POINTER(struct_nir_deref_instr), nir_variable_mode] -except AttributeError: - pass -try: - nir_deref_mode_is = _libraries['FIXME_STUB'].nir_deref_mode_is - nir_deref_mode_is.restype = ctypes.c_bool - nir_deref_mode_is.argtypes = [ctypes.POINTER(struct_nir_deref_instr), nir_variable_mode] -except AttributeError: - pass -try: - nir_deref_mode_is_one_of = _libraries['FIXME_STUB'].nir_deref_mode_is_one_of - nir_deref_mode_is_one_of.restype = ctypes.c_bool - nir_deref_mode_is_one_of.argtypes = [ctypes.POINTER(struct_nir_deref_instr), nir_variable_mode] -except AttributeError: - pass -try: - nir_deref_mode_is_in_set = _libraries['FIXME_STUB'].nir_deref_mode_is_in_set - nir_deref_mode_is_in_set.restype = ctypes.c_bool - nir_deref_mode_is_in_set.argtypes = [ctypes.POINTER(struct_nir_deref_instr), nir_variable_mode] -except AttributeError: - pass -try: - nir_src_as_deref = _libraries['FIXME_STUB'].nir_src_as_deref - nir_src_as_deref.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_src_as_deref.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_deref_instr_parent = _libraries['FIXME_STUB'].nir_deref_instr_parent - nir_deref_instr_parent.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_deref_instr_parent.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_deref_instr_get_variable = _libraries['FIXME_STUB'].nir_deref_instr_get_variable - nir_deref_instr_get_variable.restype = ctypes.POINTER(struct_nir_variable) - nir_deref_instr_get_variable.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_deref_instr_has_indirect = _libraries['libtinymesa_cpu.so'].nir_deref_instr_has_indirect - nir_deref_instr_has_indirect.restype = ctypes.c_bool - nir_deref_instr_has_indirect.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_deref_instr_is_known_out_of_bounds = _libraries['libtinymesa_cpu.so'].nir_deref_instr_is_known_out_of_bounds - nir_deref_instr_is_known_out_of_bounds.restype = ctypes.c_bool - nir_deref_instr_is_known_out_of_bounds.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_deref_instr_has_complex_use_options' -c__EA_nir_deref_instr_has_complex_use_options__enumvalues = { - 1: 'nir_deref_instr_has_complex_use_allow_memcpy_src', - 2: 'nir_deref_instr_has_complex_use_allow_memcpy_dst', - 4: 'nir_deref_instr_has_complex_use_allow_atomics', -} -nir_deref_instr_has_complex_use_allow_memcpy_src = 1 -nir_deref_instr_has_complex_use_allow_memcpy_dst = 2 -nir_deref_instr_has_complex_use_allow_atomics = 4 -c__EA_nir_deref_instr_has_complex_use_options = ctypes.c_uint32 # enum -nir_deref_instr_has_complex_use_options = c__EA_nir_deref_instr_has_complex_use_options -nir_deref_instr_has_complex_use_options__enumvalues = c__EA_nir_deref_instr_has_complex_use_options__enumvalues -try: - nir_deref_instr_has_complex_use = _libraries['libtinymesa_cpu.so'].nir_deref_instr_has_complex_use - nir_deref_instr_has_complex_use.restype = ctypes.c_bool - nir_deref_instr_has_complex_use.argtypes = [ctypes.POINTER(struct_nir_deref_instr), nir_deref_instr_has_complex_use_options] -except AttributeError: - pass -try: - nir_deref_instr_remove_if_unused = _libraries['libtinymesa_cpu.so'].nir_deref_instr_remove_if_unused - nir_deref_instr_remove_if_unused.restype = ctypes.c_bool - nir_deref_instr_remove_if_unused.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_deref_instr_array_stride = _libraries['libtinymesa_cpu.so'].nir_deref_instr_array_stride - nir_deref_instr_array_stride.restype = ctypes.c_uint32 - nir_deref_instr_array_stride.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -class struct_nir_call_instr(Structure): - pass - -class struct_nir_function(Structure): - pass - -struct_nir_call_instr._pack_ = 1 # source:False -struct_nir_call_instr._fields_ = [ - ('instr', nir_instr), - ('callee', ctypes.POINTER(struct_nir_function)), - ('indirect_callee', nir_src), - ('num_params', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', struct_nir_src * 0), -] - -class struct_nir_parameter(Structure): - pass - -class struct_nir_function_impl(Structure): - pass - -struct_nir_function._pack_ = 1 # source:False -struct_nir_function._fields_ = [ - ('node', struct_exec_node), - ('name', ctypes.POINTER(ctypes.c_char)), - ('shader', ctypes.POINTER(struct_nir_shader)), - ('num_params', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', ctypes.POINTER(struct_nir_parameter)), - ('impl', ctypes.POINTER(struct_nir_function_impl)), - ('driver_attributes', ctypes.c_uint32), - ('is_entrypoint', ctypes.c_bool), - ('is_exported', ctypes.c_bool), - ('is_preamble', ctypes.c_bool), - ('should_inline', ctypes.c_bool), - ('dont_inline', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), - ('workgroup_size', ctypes.c_uint32 * 3), - ('is_subroutine', ctypes.c_bool), - ('is_tmp_globals_wrapper', ctypes.c_bool), - ('PADDING_2', ctypes.c_ubyte * 2), - ('num_subroutine_types', ctypes.c_int32), - ('subroutine_types', ctypes.POINTER(ctypes.POINTER(struct_glsl_type))), - ('subroutine_index', ctypes.c_int32), - ('pass_flags', ctypes.c_uint32), -] - -struct_nir_parameter._pack_ = 1 # source:False -struct_nir_parameter._fields_ = [ - ('num_components', ctypes.c_ubyte), - ('bit_size', ctypes.c_ubyte), - ('is_return', ctypes.c_bool), - ('implicit_conversion_prohibited', ctypes.c_bool), - ('is_uniform', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('mode', nir_variable_mode), - ('driver_attributes', ctypes.c_uint32), - ('type', ctypes.POINTER(struct_glsl_type)), - ('name', ctypes.POINTER(ctypes.c_char)), -] - - -# values for enumeration 'c__EA_nir_metadata' -c__EA_nir_metadata__enumvalues = { - 0: 'nir_metadata_none', - 1: 'nir_metadata_block_index', - 2: 'nir_metadata_dominance', - 4: 'nir_metadata_live_defs', - 8: 'nir_metadata_not_properly_reset', - 16: 'nir_metadata_loop_analysis', - 32: 'nir_metadata_instr_index', - 64: 'nir_metadata_divergence', - 3: 'nir_metadata_control_flow', - -9: 'nir_metadata_all', -} -nir_metadata_none = 0 -nir_metadata_block_index = 1 -nir_metadata_dominance = 2 -nir_metadata_live_defs = 4 -nir_metadata_not_properly_reset = 8 -nir_metadata_loop_analysis = 16 -nir_metadata_instr_index = 32 -nir_metadata_divergence = 64 -nir_metadata_control_flow = 3 -nir_metadata_all = -9 -c__EA_nir_metadata = ctypes.c_int32 # enum -struct_nir_function_impl._pack_ = 1 # source:False -struct_nir_function_impl._fields_ = [ - ('cf_node', struct_nir_cf_node), - ('function', ctypes.POINTER(struct_nir_function)), - ('preamble', ctypes.POINTER(struct_nir_function)), - ('body', struct_exec_list), - ('end_block', ctypes.POINTER(struct_nir_block)), - ('locals', struct_exec_list), - ('ssa_alloc', ctypes.c_uint32), - ('num_blocks', ctypes.c_uint32), - ('structured', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('valid_metadata', c__EA_nir_metadata), - ('loop_analysis_indirect_mask', nir_variable_mode), - ('loop_analysis_force_unroll_sampler_indirect', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -nir_call_instr = struct_nir_call_instr - -# values for enumeration 'c__EA_nir_intrinsic_op' -c__EA_nir_intrinsic_op__enumvalues = { - 0: 'nir_intrinsic_accept_ray_intersection', - 1: 'nir_intrinsic_addr_mode_is', - 2: 'nir_intrinsic_al2p_nv', - 3: 'nir_intrinsic_ald_nv', - 4: 'nir_intrinsic_alpha_to_coverage', - 5: 'nir_intrinsic_as_uniform', - 6: 'nir_intrinsic_ast_nv', - 7: 'nir_intrinsic_atomic_add_gen_prim_count_amd', - 8: 'nir_intrinsic_atomic_add_gs_emit_prim_count_amd', - 9: 'nir_intrinsic_atomic_add_shader_invocation_count_amd', - 10: 'nir_intrinsic_atomic_add_xfb_prim_count_amd', - 11: 'nir_intrinsic_atomic_counter_add', - 12: 'nir_intrinsic_atomic_counter_add_deref', - 13: 'nir_intrinsic_atomic_counter_and', - 14: 'nir_intrinsic_atomic_counter_and_deref', - 15: 'nir_intrinsic_atomic_counter_comp_swap', - 16: 'nir_intrinsic_atomic_counter_comp_swap_deref', - 17: 'nir_intrinsic_atomic_counter_exchange', - 18: 'nir_intrinsic_atomic_counter_exchange_deref', - 19: 'nir_intrinsic_atomic_counter_inc', - 20: 'nir_intrinsic_atomic_counter_inc_deref', - 21: 'nir_intrinsic_atomic_counter_max', - 22: 'nir_intrinsic_atomic_counter_max_deref', - 23: 'nir_intrinsic_atomic_counter_min', - 24: 'nir_intrinsic_atomic_counter_min_deref', - 25: 'nir_intrinsic_atomic_counter_or', - 26: 'nir_intrinsic_atomic_counter_or_deref', - 27: 'nir_intrinsic_atomic_counter_post_dec', - 28: 'nir_intrinsic_atomic_counter_post_dec_deref', - 29: 'nir_intrinsic_atomic_counter_pre_dec', - 30: 'nir_intrinsic_atomic_counter_pre_dec_deref', - 31: 'nir_intrinsic_atomic_counter_read', - 32: 'nir_intrinsic_atomic_counter_read_deref', - 33: 'nir_intrinsic_atomic_counter_xor', - 34: 'nir_intrinsic_atomic_counter_xor_deref', - 35: 'nir_intrinsic_ballot', - 36: 'nir_intrinsic_ballot_bit_count_exclusive', - 37: 'nir_intrinsic_ballot_bit_count_inclusive', - 38: 'nir_intrinsic_ballot_bit_count_reduce', - 39: 'nir_intrinsic_ballot_bitfield_extract', - 40: 'nir_intrinsic_ballot_find_lsb', - 41: 'nir_intrinsic_ballot_find_msb', - 42: 'nir_intrinsic_ballot_relaxed', - 43: 'nir_intrinsic_bar_break_nv', - 44: 'nir_intrinsic_bar_set_nv', - 45: 'nir_intrinsic_bar_sync_nv', - 46: 'nir_intrinsic_barrier', - 47: 'nir_intrinsic_begin_invocation_interlock', - 48: 'nir_intrinsic_bindgen_return', - 49: 'nir_intrinsic_bindless_image_agx', - 50: 'nir_intrinsic_bindless_image_atomic', - 51: 'nir_intrinsic_bindless_image_atomic_swap', - 52: 'nir_intrinsic_bindless_image_descriptor_amd', - 53: 'nir_intrinsic_bindless_image_format', - 54: 'nir_intrinsic_bindless_image_fragment_mask_load_amd', - 55: 'nir_intrinsic_bindless_image_levels', - 56: 'nir_intrinsic_bindless_image_load', - 57: 'nir_intrinsic_bindless_image_load_raw_intel', - 58: 'nir_intrinsic_bindless_image_order', - 59: 'nir_intrinsic_bindless_image_samples', - 60: 'nir_intrinsic_bindless_image_samples_identical', - 61: 'nir_intrinsic_bindless_image_size', - 62: 'nir_intrinsic_bindless_image_sparse_load', - 63: 'nir_intrinsic_bindless_image_store', - 64: 'nir_intrinsic_bindless_image_store_block_agx', - 65: 'nir_intrinsic_bindless_image_store_raw_intel', - 66: 'nir_intrinsic_bindless_image_texel_address', - 67: 'nir_intrinsic_bindless_resource_ir3', - 68: 'nir_intrinsic_brcst_active_ir3', - 69: 'nir_intrinsic_btd_retire_intel', - 70: 'nir_intrinsic_btd_spawn_intel', - 71: 'nir_intrinsic_btd_stack_push_intel', - 72: 'nir_intrinsic_bvh64_intersect_ray_amd', - 73: 'nir_intrinsic_bvh8_intersect_ray_amd', - 74: 'nir_intrinsic_bvh_stack_rtn_amd', - 75: 'nir_intrinsic_cmat_binary_op', - 76: 'nir_intrinsic_cmat_bitcast', - 77: 'nir_intrinsic_cmat_construct', - 78: 'nir_intrinsic_cmat_convert', - 79: 'nir_intrinsic_cmat_copy', - 80: 'nir_intrinsic_cmat_extract', - 81: 'nir_intrinsic_cmat_insert', - 82: 'nir_intrinsic_cmat_length', - 83: 'nir_intrinsic_cmat_load', - 84: 'nir_intrinsic_cmat_muladd', - 85: 'nir_intrinsic_cmat_muladd_amd', - 86: 'nir_intrinsic_cmat_muladd_nv', - 87: 'nir_intrinsic_cmat_scalar_op', - 88: 'nir_intrinsic_cmat_store', - 89: 'nir_intrinsic_cmat_transpose', - 90: 'nir_intrinsic_cmat_unary_op', - 91: 'nir_intrinsic_convert_alu_types', - 92: 'nir_intrinsic_convert_cmat_intel', - 93: 'nir_intrinsic_copy_deref', - 94: 'nir_intrinsic_copy_fs_outputs_nv', - 95: 'nir_intrinsic_copy_global_to_uniform_ir3', - 96: 'nir_intrinsic_copy_push_const_to_uniform_ir3', - 97: 'nir_intrinsic_copy_ubo_to_uniform_ir3', - 98: 'nir_intrinsic_ddx', - 99: 'nir_intrinsic_ddx_coarse', - 100: 'nir_intrinsic_ddx_fine', - 101: 'nir_intrinsic_ddy', - 102: 'nir_intrinsic_ddy_coarse', - 103: 'nir_intrinsic_ddy_fine', - 104: 'nir_intrinsic_debug_break', - 105: 'nir_intrinsic_decl_reg', - 106: 'nir_intrinsic_demote', - 107: 'nir_intrinsic_demote_if', - 108: 'nir_intrinsic_demote_samples', - 109: 'nir_intrinsic_deref_atomic', - 110: 'nir_intrinsic_deref_atomic_swap', - 111: 'nir_intrinsic_deref_buffer_array_length', - 112: 'nir_intrinsic_deref_implicit_array_length', - 113: 'nir_intrinsic_deref_mode_is', - 114: 'nir_intrinsic_deref_texture_src', - 115: 'nir_intrinsic_doorbell_agx', - 116: 'nir_intrinsic_dpas_intel', - 117: 'nir_intrinsic_dpp16_shift_amd', - 118: 'nir_intrinsic_elect', - 119: 'nir_intrinsic_elect_any_ir3', - 120: 'nir_intrinsic_emit_primitive_poly', - 121: 'nir_intrinsic_emit_vertex', - 122: 'nir_intrinsic_emit_vertex_nv', - 123: 'nir_intrinsic_emit_vertex_with_counter', - 124: 'nir_intrinsic_end_invocation_interlock', - 125: 'nir_intrinsic_end_primitive', - 126: 'nir_intrinsic_end_primitive_nv', - 127: 'nir_intrinsic_end_primitive_with_counter', - 128: 'nir_intrinsic_enqueue_node_payloads', - 129: 'nir_intrinsic_exclusive_scan', - 130: 'nir_intrinsic_exclusive_scan_clusters_ir3', - 131: 'nir_intrinsic_execute_callable', - 132: 'nir_intrinsic_execute_closest_hit_amd', - 133: 'nir_intrinsic_execute_miss_amd', - 134: 'nir_intrinsic_export_agx', - 135: 'nir_intrinsic_export_amd', - 136: 'nir_intrinsic_export_dual_src_blend_amd', - 137: 'nir_intrinsic_export_row_amd', - 138: 'nir_intrinsic_fence_helper_exit_agx', - 139: 'nir_intrinsic_fence_mem_to_tex_agx', - 140: 'nir_intrinsic_fence_pbe_to_tex_agx', - 141: 'nir_intrinsic_fence_pbe_to_tex_pixel_agx', - 142: 'nir_intrinsic_final_primitive_nv', - 143: 'nir_intrinsic_finalize_incoming_node_payload', - 144: 'nir_intrinsic_first_invocation', - 145: 'nir_intrinsic_fs_out_nv', - 146: 'nir_intrinsic_gds_atomic_add_amd', - 147: 'nir_intrinsic_get_ssbo_size', - 148: 'nir_intrinsic_get_ubo_size', - 149: 'nir_intrinsic_global_atomic', - 150: 'nir_intrinsic_global_atomic_2x32', - 151: 'nir_intrinsic_global_atomic_agx', - 152: 'nir_intrinsic_global_atomic_amd', - 153: 'nir_intrinsic_global_atomic_swap', - 154: 'nir_intrinsic_global_atomic_swap_2x32', - 155: 'nir_intrinsic_global_atomic_swap_agx', - 156: 'nir_intrinsic_global_atomic_swap_amd', - 157: 'nir_intrinsic_ignore_ray_intersection', - 158: 'nir_intrinsic_imadsp_nv', - 159: 'nir_intrinsic_image_atomic', - 160: 'nir_intrinsic_image_atomic_swap', - 161: 'nir_intrinsic_image_deref_atomic', - 162: 'nir_intrinsic_image_deref_atomic_swap', - 163: 'nir_intrinsic_image_deref_descriptor_amd', - 164: 'nir_intrinsic_image_deref_format', - 165: 'nir_intrinsic_image_deref_fragment_mask_load_amd', - 166: 'nir_intrinsic_image_deref_levels', - 167: 'nir_intrinsic_image_deref_load', - 168: 'nir_intrinsic_image_deref_load_info_nv', - 169: 'nir_intrinsic_image_deref_load_param_intel', - 170: 'nir_intrinsic_image_deref_load_raw_intel', - 171: 'nir_intrinsic_image_deref_order', - 172: 'nir_intrinsic_image_deref_samples', - 173: 'nir_intrinsic_image_deref_samples_identical', - 174: 'nir_intrinsic_image_deref_size', - 175: 'nir_intrinsic_image_deref_sparse_load', - 176: 'nir_intrinsic_image_deref_store', - 177: 'nir_intrinsic_image_deref_store_block_agx', - 178: 'nir_intrinsic_image_deref_store_raw_intel', - 179: 'nir_intrinsic_image_deref_texel_address', - 180: 'nir_intrinsic_image_descriptor_amd', - 181: 'nir_intrinsic_image_format', - 182: 'nir_intrinsic_image_fragment_mask_load_amd', - 183: 'nir_intrinsic_image_levels', - 184: 'nir_intrinsic_image_load', - 185: 'nir_intrinsic_image_load_raw_intel', - 186: 'nir_intrinsic_image_order', - 187: 'nir_intrinsic_image_samples', - 188: 'nir_intrinsic_image_samples_identical', - 189: 'nir_intrinsic_image_size', - 190: 'nir_intrinsic_image_sparse_load', - 191: 'nir_intrinsic_image_store', - 192: 'nir_intrinsic_image_store_block_agx', - 193: 'nir_intrinsic_image_store_raw_intel', - 194: 'nir_intrinsic_image_texel_address', - 195: 'nir_intrinsic_inclusive_scan', - 196: 'nir_intrinsic_inclusive_scan_clusters_ir3', - 197: 'nir_intrinsic_initialize_node_payloads', - 198: 'nir_intrinsic_interp_deref_at_centroid', - 199: 'nir_intrinsic_interp_deref_at_offset', - 200: 'nir_intrinsic_interp_deref_at_sample', - 201: 'nir_intrinsic_interp_deref_at_vertex', - 202: 'nir_intrinsic_inverse_ballot', - 203: 'nir_intrinsic_ipa_nv', - 204: 'nir_intrinsic_is_helper_invocation', - 205: 'nir_intrinsic_is_sparse_resident_zink', - 206: 'nir_intrinsic_is_sparse_texels_resident', - 207: 'nir_intrinsic_is_subgroup_invocation_lt_amd', - 208: 'nir_intrinsic_isberd_nv', - 209: 'nir_intrinsic_lane_permute_16_amd', - 210: 'nir_intrinsic_last_invocation', - 211: 'nir_intrinsic_launch_mesh_workgroups', - 212: 'nir_intrinsic_launch_mesh_workgroups_with_payload_deref', - 213: 'nir_intrinsic_ldc_nv', - 214: 'nir_intrinsic_ldcx_nv', - 215: 'nir_intrinsic_ldtram_nv', - 216: 'nir_intrinsic_load_aa_line_width', - 217: 'nir_intrinsic_load_accel_struct_amd', - 218: 'nir_intrinsic_load_active_samples_agx', - 219: 'nir_intrinsic_load_active_subgroup_count_agx', - 220: 'nir_intrinsic_load_active_subgroup_invocation_agx', - 221: 'nir_intrinsic_load_agx', - 222: 'nir_intrinsic_load_alpha_reference_amd', - 223: 'nir_intrinsic_load_api_sample_mask_agx', - 224: 'nir_intrinsic_load_attrib_clamp_agx', - 225: 'nir_intrinsic_load_attribute_pan', - 226: 'nir_intrinsic_load_back_face_agx', - 227: 'nir_intrinsic_load_barycentric_at_offset', - 228: 'nir_intrinsic_load_barycentric_at_offset_nv', - 229: 'nir_intrinsic_load_barycentric_at_sample', - 230: 'nir_intrinsic_load_barycentric_centroid', - 231: 'nir_intrinsic_load_barycentric_coord_at_offset', - 232: 'nir_intrinsic_load_barycentric_coord_at_sample', - 233: 'nir_intrinsic_load_barycentric_coord_centroid', - 234: 'nir_intrinsic_load_barycentric_coord_pixel', - 235: 'nir_intrinsic_load_barycentric_coord_sample', - 236: 'nir_intrinsic_load_barycentric_model', - 237: 'nir_intrinsic_load_barycentric_optimize_amd', - 238: 'nir_intrinsic_load_barycentric_pixel', - 239: 'nir_intrinsic_load_barycentric_sample', - 240: 'nir_intrinsic_load_base_global_invocation_id', - 241: 'nir_intrinsic_load_base_instance', - 242: 'nir_intrinsic_load_base_vertex', - 243: 'nir_intrinsic_load_base_workgroup_id', - 244: 'nir_intrinsic_load_blend_const_color_a_float', - 245: 'nir_intrinsic_load_blend_const_color_aaaa8888_unorm', - 246: 'nir_intrinsic_load_blend_const_color_b_float', - 247: 'nir_intrinsic_load_blend_const_color_g_float', - 248: 'nir_intrinsic_load_blend_const_color_r_float', - 249: 'nir_intrinsic_load_blend_const_color_rgba', - 250: 'nir_intrinsic_load_blend_const_color_rgba8888_unorm', - 251: 'nir_intrinsic_load_btd_global_arg_addr_intel', - 252: 'nir_intrinsic_load_btd_local_arg_addr_intel', - 253: 'nir_intrinsic_load_btd_resume_sbt_addr_intel', - 254: 'nir_intrinsic_load_btd_shader_type_intel', - 255: 'nir_intrinsic_load_btd_stack_id_intel', - 256: 'nir_intrinsic_load_buffer_amd', - 257: 'nir_intrinsic_load_callable_sbt_addr_intel', - 258: 'nir_intrinsic_load_callable_sbt_stride_intel', - 259: 'nir_intrinsic_load_clamp_vertex_color_amd', - 260: 'nir_intrinsic_load_clip_half_line_width_amd', - 261: 'nir_intrinsic_load_clip_z_coeff_agx', - 262: 'nir_intrinsic_load_coalesced_input_count', - 263: 'nir_intrinsic_load_coefficients_agx', - 264: 'nir_intrinsic_load_color0', - 265: 'nir_intrinsic_load_color1', - 266: 'nir_intrinsic_load_const_buf_base_addr_lvp', - 267: 'nir_intrinsic_load_const_ir3', - 268: 'nir_intrinsic_load_constant', - 269: 'nir_intrinsic_load_constant_agx', - 270: 'nir_intrinsic_load_constant_base_ptr', - 271: 'nir_intrinsic_load_converted_output_pan', - 272: 'nir_intrinsic_load_core_id_agx', - 273: 'nir_intrinsic_load_cull_any_enabled_amd', - 274: 'nir_intrinsic_load_cull_back_face_enabled_amd', - 275: 'nir_intrinsic_load_cull_ccw_amd', - 276: 'nir_intrinsic_load_cull_front_face_enabled_amd', - 277: 'nir_intrinsic_load_cull_line_viewport_xy_scale_and_offset_amd', - 278: 'nir_intrinsic_load_cull_mask', - 279: 'nir_intrinsic_load_cull_mask_and_flags_amd', - 280: 'nir_intrinsic_load_cull_small_line_precision_amd', - 281: 'nir_intrinsic_load_cull_small_lines_enabled_amd', - 282: 'nir_intrinsic_load_cull_small_triangle_precision_amd', - 283: 'nir_intrinsic_load_cull_small_triangles_enabled_amd', - 284: 'nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd', - 285: 'nir_intrinsic_load_debug_log_desc_amd', - 286: 'nir_intrinsic_load_depth_never_agx', - 287: 'nir_intrinsic_load_deref', - 288: 'nir_intrinsic_load_deref_block_intel', - 289: 'nir_intrinsic_load_draw_id', - 290: 'nir_intrinsic_load_esgs_vertex_stride_amd', - 291: 'nir_intrinsic_load_exported_agx', - 292: 'nir_intrinsic_load_fb_layers_v3d', - 293: 'nir_intrinsic_load_fbfetch_image_desc_amd', - 294: 'nir_intrinsic_load_fbfetch_image_fmask_desc_amd', - 295: 'nir_intrinsic_load_fep_w_v3d', - 296: 'nir_intrinsic_load_first_vertex', - 297: 'nir_intrinsic_load_fixed_point_size_agx', - 298: 'nir_intrinsic_load_flat_mask', - 299: 'nir_intrinsic_load_force_vrs_rates_amd', - 300: 'nir_intrinsic_load_frag_coord', - 301: 'nir_intrinsic_load_frag_coord_unscaled_ir3', - 302: 'nir_intrinsic_load_frag_coord_w', - 303: 'nir_intrinsic_load_frag_coord_z', - 304: 'nir_intrinsic_load_frag_coord_zw_pan', - 305: 'nir_intrinsic_load_frag_invocation_count', - 306: 'nir_intrinsic_load_frag_offset_ir3', - 307: 'nir_intrinsic_load_frag_shading_rate', - 308: 'nir_intrinsic_load_frag_size', - 309: 'nir_intrinsic_load_frag_size_ir3', - 310: 'nir_intrinsic_load_from_texture_handle_agx', - 311: 'nir_intrinsic_load_front_face', - 312: 'nir_intrinsic_load_front_face_fsign', - 313: 'nir_intrinsic_load_fs_input_interp_deltas', - 314: 'nir_intrinsic_load_fs_msaa_intel', - 315: 'nir_intrinsic_load_fully_covered', - 316: 'nir_intrinsic_load_geometry_param_buffer_poly', - 317: 'nir_intrinsic_load_global', - 318: 'nir_intrinsic_load_global_2x32', - 319: 'nir_intrinsic_load_global_amd', - 320: 'nir_intrinsic_load_global_base_ptr', - 321: 'nir_intrinsic_load_global_block_intel', - 322: 'nir_intrinsic_load_global_bounded', - 323: 'nir_intrinsic_load_global_constant', - 324: 'nir_intrinsic_load_global_constant_bounded', - 325: 'nir_intrinsic_load_global_constant_offset', - 326: 'nir_intrinsic_load_global_constant_uniform_block_intel', - 327: 'nir_intrinsic_load_global_etna', - 328: 'nir_intrinsic_load_global_invocation_id', - 329: 'nir_intrinsic_load_global_invocation_index', - 330: 'nir_intrinsic_load_global_ir3', - 331: 'nir_intrinsic_load_global_size', - 332: 'nir_intrinsic_load_gs_header_ir3', - 333: 'nir_intrinsic_load_gs_vertex_offset_amd', - 334: 'nir_intrinsic_load_gs_wave_id_amd', - 335: 'nir_intrinsic_load_helper_arg_hi_agx', - 336: 'nir_intrinsic_load_helper_arg_lo_agx', - 337: 'nir_intrinsic_load_helper_invocation', - 338: 'nir_intrinsic_load_helper_op_id_agx', - 339: 'nir_intrinsic_load_hit_attrib_amd', - 340: 'nir_intrinsic_load_hs_out_patch_data_offset_amd', - 341: 'nir_intrinsic_load_hs_patch_stride_ir3', - 342: 'nir_intrinsic_load_initial_edgeflags_amd', - 343: 'nir_intrinsic_load_inline_data_intel', - 344: 'nir_intrinsic_load_input', - 345: 'nir_intrinsic_load_input_assembly_buffer_poly', - 346: 'nir_intrinsic_load_input_attachment_conv_pan', - 347: 'nir_intrinsic_load_input_attachment_coord', - 348: 'nir_intrinsic_load_input_attachment_target_pan', - 349: 'nir_intrinsic_load_input_topology_poly', - 350: 'nir_intrinsic_load_input_vertex', - 351: 'nir_intrinsic_load_instance_id', - 352: 'nir_intrinsic_load_interpolated_input', - 353: 'nir_intrinsic_load_intersection_opaque_amd', - 354: 'nir_intrinsic_load_invocation_id', - 355: 'nir_intrinsic_load_is_first_fan_agx', - 356: 'nir_intrinsic_load_is_indexed_draw', - 357: 'nir_intrinsic_load_kernel_input', - 358: 'nir_intrinsic_load_layer_id', - 359: 'nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd', - 360: 'nir_intrinsic_load_leaf_opaque_intel', - 361: 'nir_intrinsic_load_leaf_procedural_intel', - 362: 'nir_intrinsic_load_line_coord', - 363: 'nir_intrinsic_load_line_width', - 364: 'nir_intrinsic_load_local_invocation_id', - 365: 'nir_intrinsic_load_local_invocation_index', - 366: 'nir_intrinsic_load_local_pixel_agx', - 367: 'nir_intrinsic_load_local_shared_r600', - 368: 'nir_intrinsic_load_lshs_vertex_stride_amd', - 369: 'nir_intrinsic_load_max_polygon_intel', - 370: 'nir_intrinsic_load_merged_wave_info_amd', - 371: 'nir_intrinsic_load_mesh_view_count', - 372: 'nir_intrinsic_load_mesh_view_indices', - 373: 'nir_intrinsic_load_multisampled_pan', - 374: 'nir_intrinsic_load_noperspective_varyings_pan', - 375: 'nir_intrinsic_load_num_subgroups', - 376: 'nir_intrinsic_load_num_vertices', - 377: 'nir_intrinsic_load_num_vertices_per_primitive_amd', - 378: 'nir_intrinsic_load_num_workgroups', - 379: 'nir_intrinsic_load_ordered_id_amd', - 380: 'nir_intrinsic_load_output', - 381: 'nir_intrinsic_load_packed_passthrough_primitive_amd', - 382: 'nir_intrinsic_load_param', - 383: 'nir_intrinsic_load_patch_vertices_in', - 384: 'nir_intrinsic_load_per_primitive_input', - 385: 'nir_intrinsic_load_per_primitive_output', - 386: 'nir_intrinsic_load_per_primitive_remap_intel', - 387: 'nir_intrinsic_load_per_vertex_input', - 388: 'nir_intrinsic_load_per_vertex_output', - 389: 'nir_intrinsic_load_per_view_output', - 390: 'nir_intrinsic_load_persp_center_rhw_ir3', - 391: 'nir_intrinsic_load_pipeline_stat_query_enabled_amd', - 392: 'nir_intrinsic_load_pixel_coord', - 393: 'nir_intrinsic_load_point_coord', - 394: 'nir_intrinsic_load_point_coord_maybe_flipped', - 395: 'nir_intrinsic_load_poly_line_smooth_enabled', - 396: 'nir_intrinsic_load_polygon_stipple_agx', - 397: 'nir_intrinsic_load_polygon_stipple_buffer_amd', - 398: 'nir_intrinsic_load_preamble', - 399: 'nir_intrinsic_load_prim_gen_query_enabled_amd', - 400: 'nir_intrinsic_load_prim_xfb_query_enabled_amd', - 401: 'nir_intrinsic_load_primitive_id', - 402: 'nir_intrinsic_load_primitive_location_ir3', - 403: 'nir_intrinsic_load_printf_buffer_address', - 404: 'nir_intrinsic_load_printf_buffer_size', - 405: 'nir_intrinsic_load_provoking_last', - 406: 'nir_intrinsic_load_provoking_vtx_amd', - 407: 'nir_intrinsic_load_provoking_vtx_in_prim_amd', - 408: 'nir_intrinsic_load_push_constant', - 409: 'nir_intrinsic_load_push_constant_zink', - 410: 'nir_intrinsic_load_r600_indirect_per_vertex_input', - 411: 'nir_intrinsic_load_rasterization_primitive_amd', - 412: 'nir_intrinsic_load_rasterization_samples_amd', - 413: 'nir_intrinsic_load_rasterization_stream', - 414: 'nir_intrinsic_load_raw_output_pan', - 415: 'nir_intrinsic_load_raw_vertex_id_pan', - 416: 'nir_intrinsic_load_raw_vertex_offset_pan', - 417: 'nir_intrinsic_load_ray_base_mem_addr_intel', - 418: 'nir_intrinsic_load_ray_flags', - 419: 'nir_intrinsic_load_ray_geometry_index', - 420: 'nir_intrinsic_load_ray_hit_kind', - 421: 'nir_intrinsic_load_ray_hit_sbt_addr_intel', - 422: 'nir_intrinsic_load_ray_hit_sbt_stride_intel', - 423: 'nir_intrinsic_load_ray_hw_stack_size_intel', - 424: 'nir_intrinsic_load_ray_instance_custom_index', - 425: 'nir_intrinsic_load_ray_launch_id', - 426: 'nir_intrinsic_load_ray_launch_size', - 427: 'nir_intrinsic_load_ray_miss_sbt_addr_intel', - 428: 'nir_intrinsic_load_ray_miss_sbt_stride_intel', - 429: 'nir_intrinsic_load_ray_num_dss_rt_stacks_intel', - 430: 'nir_intrinsic_load_ray_object_direction', - 431: 'nir_intrinsic_load_ray_object_origin', - 432: 'nir_intrinsic_load_ray_object_to_world', - 433: 'nir_intrinsic_load_ray_query_global_intel', - 434: 'nir_intrinsic_load_ray_sw_stack_size_intel', - 435: 'nir_intrinsic_load_ray_t_max', - 436: 'nir_intrinsic_load_ray_t_min', - 437: 'nir_intrinsic_load_ray_tracing_stack_base_lvp', - 438: 'nir_intrinsic_load_ray_triangle_vertex_positions', - 439: 'nir_intrinsic_load_ray_world_direction', - 440: 'nir_intrinsic_load_ray_world_origin', - 441: 'nir_intrinsic_load_ray_world_to_object', - 442: 'nir_intrinsic_load_readonly_output_pan', - 443: 'nir_intrinsic_load_reg', - 444: 'nir_intrinsic_load_reg_indirect', - 445: 'nir_intrinsic_load_rel_patch_id_ir3', - 446: 'nir_intrinsic_load_reloc_const_intel', - 447: 'nir_intrinsic_load_resume_shader_address_amd', - 448: 'nir_intrinsic_load_ring_attr_amd', - 449: 'nir_intrinsic_load_ring_attr_offset_amd', - 450: 'nir_intrinsic_load_ring_es2gs_offset_amd', - 451: 'nir_intrinsic_load_ring_esgs_amd', - 452: 'nir_intrinsic_load_ring_gs2vs_offset_amd', - 453: 'nir_intrinsic_load_ring_gsvs_amd', - 454: 'nir_intrinsic_load_ring_mesh_scratch_amd', - 455: 'nir_intrinsic_load_ring_mesh_scratch_offset_amd', - 456: 'nir_intrinsic_load_ring_task_draw_amd', - 457: 'nir_intrinsic_load_ring_task_payload_amd', - 458: 'nir_intrinsic_load_ring_tess_factors_amd', - 459: 'nir_intrinsic_load_ring_tess_factors_offset_amd', - 460: 'nir_intrinsic_load_ring_tess_offchip_amd', - 461: 'nir_intrinsic_load_ring_tess_offchip_offset_amd', - 462: 'nir_intrinsic_load_root_agx', - 463: 'nir_intrinsic_load_rt_arg_scratch_offset_amd', - 464: 'nir_intrinsic_load_rt_conversion_pan', - 465: 'nir_intrinsic_load_sample_id', - 466: 'nir_intrinsic_load_sample_id_no_per_sample', - 467: 'nir_intrinsic_load_sample_mask', - 468: 'nir_intrinsic_load_sample_mask_in', - 469: 'nir_intrinsic_load_sample_pos', - 470: 'nir_intrinsic_load_sample_pos_from_id', - 471: 'nir_intrinsic_load_sample_pos_or_center', - 472: 'nir_intrinsic_load_sample_positions_agx', - 473: 'nir_intrinsic_load_sample_positions_amd', - 474: 'nir_intrinsic_load_sample_positions_pan', - 475: 'nir_intrinsic_load_sampler_handle_agx', - 476: 'nir_intrinsic_load_sampler_lod_parameters', - 477: 'nir_intrinsic_load_samples_log2_agx', - 478: 'nir_intrinsic_load_sbt_base_amd', - 479: 'nir_intrinsic_load_sbt_offset_amd', - 480: 'nir_intrinsic_load_sbt_stride_amd', - 481: 'nir_intrinsic_load_scalar_arg_amd', - 482: 'nir_intrinsic_load_scratch', - 483: 'nir_intrinsic_load_scratch_base_ptr', - 484: 'nir_intrinsic_load_shader_call_data_offset_lvp', - 485: 'nir_intrinsic_load_shader_index', - 486: 'nir_intrinsic_load_shader_output_pan', - 487: 'nir_intrinsic_load_shader_part_tests_zs_agx', - 488: 'nir_intrinsic_load_shader_record_ptr', - 489: 'nir_intrinsic_load_shared', - 490: 'nir_intrinsic_load_shared2_amd', - 491: 'nir_intrinsic_load_shared_base_ptr', - 492: 'nir_intrinsic_load_shared_block_intel', - 493: 'nir_intrinsic_load_shared_ir3', - 494: 'nir_intrinsic_load_shared_lock_nv', - 495: 'nir_intrinsic_load_shared_uniform_block_intel', - 496: 'nir_intrinsic_load_simd_width_intel', - 497: 'nir_intrinsic_load_sm_count_nv', - 498: 'nir_intrinsic_load_sm_id_nv', - 499: 'nir_intrinsic_load_smem_amd', - 500: 'nir_intrinsic_load_ssbo', - 501: 'nir_intrinsic_load_ssbo_address', - 502: 'nir_intrinsic_load_ssbo_block_intel', - 503: 'nir_intrinsic_load_ssbo_intel', - 504: 'nir_intrinsic_load_ssbo_ir3', - 505: 'nir_intrinsic_load_ssbo_uniform_block_intel', - 506: 'nir_intrinsic_load_stack', - 507: 'nir_intrinsic_load_stat_query_address_agx', - 508: 'nir_intrinsic_load_streamout_buffer_amd', - 509: 'nir_intrinsic_load_streamout_config_amd', - 510: 'nir_intrinsic_load_streamout_offset_amd', - 511: 'nir_intrinsic_load_streamout_write_index_amd', - 512: 'nir_intrinsic_load_subgroup_eq_mask', - 513: 'nir_intrinsic_load_subgroup_ge_mask', - 514: 'nir_intrinsic_load_subgroup_gt_mask', - 515: 'nir_intrinsic_load_subgroup_id', - 516: 'nir_intrinsic_load_subgroup_id_shift_ir3', - 517: 'nir_intrinsic_load_subgroup_invocation', - 518: 'nir_intrinsic_load_subgroup_le_mask', - 519: 'nir_intrinsic_load_subgroup_lt_mask', - 520: 'nir_intrinsic_load_subgroup_size', - 521: 'nir_intrinsic_load_sysval_agx', - 522: 'nir_intrinsic_load_sysval_nv', - 523: 'nir_intrinsic_load_task_payload', - 524: 'nir_intrinsic_load_task_ring_entry_amd', - 525: 'nir_intrinsic_load_tcs_header_ir3', - 526: 'nir_intrinsic_load_tcs_in_param_base_r600', - 527: 'nir_intrinsic_load_tcs_mem_attrib_stride', - 528: 'nir_intrinsic_load_tcs_num_patches_amd', - 529: 'nir_intrinsic_load_tcs_out_param_base_r600', - 530: 'nir_intrinsic_load_tcs_primitive_mode_amd', - 531: 'nir_intrinsic_load_tcs_rel_patch_id_r600', - 532: 'nir_intrinsic_load_tcs_tess_factor_base_r600', - 533: 'nir_intrinsic_load_tcs_tess_levels_to_tes_amd', - 534: 'nir_intrinsic_load_tess_coord', - 535: 'nir_intrinsic_load_tess_coord_xy', - 536: 'nir_intrinsic_load_tess_factor_base_ir3', - 537: 'nir_intrinsic_load_tess_level_inner', - 538: 'nir_intrinsic_load_tess_level_inner_default', - 539: 'nir_intrinsic_load_tess_level_outer', - 540: 'nir_intrinsic_load_tess_level_outer_default', - 541: 'nir_intrinsic_load_tess_param_base_ir3', - 542: 'nir_intrinsic_load_tess_param_buffer_poly', - 543: 'nir_intrinsic_load_tess_rel_patch_id_amd', - 544: 'nir_intrinsic_load_tex_sprite_mask_agx', - 545: 'nir_intrinsic_load_texture_handle_agx', - 546: 'nir_intrinsic_load_texture_scale', - 547: 'nir_intrinsic_load_texture_size_etna', - 548: 'nir_intrinsic_load_tlb_color_brcm', - 549: 'nir_intrinsic_load_topology_id_intel', - 550: 'nir_intrinsic_load_typed_buffer_amd', - 551: 'nir_intrinsic_load_uav_ir3', - 552: 'nir_intrinsic_load_ubo', - 553: 'nir_intrinsic_load_ubo_uniform_block_intel', - 554: 'nir_intrinsic_load_ubo_vec4', - 555: 'nir_intrinsic_load_uniform', - 556: 'nir_intrinsic_load_user_clip_plane', - 557: 'nir_intrinsic_load_user_data_amd', - 558: 'nir_intrinsic_load_uvs_index_agx', - 559: 'nir_intrinsic_load_vbo_base_agx', - 560: 'nir_intrinsic_load_vector_arg_amd', - 561: 'nir_intrinsic_load_vertex_id', - 562: 'nir_intrinsic_load_vertex_id_zero_base', - 563: 'nir_intrinsic_load_view_index', - 564: 'nir_intrinsic_load_viewport_offset', - 565: 'nir_intrinsic_load_viewport_scale', - 566: 'nir_intrinsic_load_viewport_x_offset', - 567: 'nir_intrinsic_load_viewport_x_scale', - 568: 'nir_intrinsic_load_viewport_y_offset', - 569: 'nir_intrinsic_load_viewport_y_scale', - 570: 'nir_intrinsic_load_viewport_z_offset', - 571: 'nir_intrinsic_load_viewport_z_scale', - 572: 'nir_intrinsic_load_vs_output_buffer_poly', - 573: 'nir_intrinsic_load_vs_outputs_poly', - 574: 'nir_intrinsic_load_vs_primitive_stride_ir3', - 575: 'nir_intrinsic_load_vs_vertex_stride_ir3', - 576: 'nir_intrinsic_load_vulkan_descriptor', - 577: 'nir_intrinsic_load_warp_id_nv', - 578: 'nir_intrinsic_load_warps_per_sm_nv', - 579: 'nir_intrinsic_load_work_dim', - 580: 'nir_intrinsic_load_workgroup_id', - 581: 'nir_intrinsic_load_workgroup_index', - 582: 'nir_intrinsic_load_workgroup_num_input_primitives_amd', - 583: 'nir_intrinsic_load_workgroup_num_input_vertices_amd', - 584: 'nir_intrinsic_load_workgroup_size', - 585: 'nir_intrinsic_load_xfb_address', - 586: 'nir_intrinsic_load_xfb_index_buffer', - 587: 'nir_intrinsic_load_xfb_size', - 588: 'nir_intrinsic_load_xfb_state_address_gfx12_amd', - 589: 'nir_intrinsic_masked_swizzle_amd', - 590: 'nir_intrinsic_mbcnt_amd', - 591: 'nir_intrinsic_memcpy_deref', - 592: 'nir_intrinsic_nop', - 593: 'nir_intrinsic_nop_amd', - 594: 'nir_intrinsic_optimization_barrier_sgpr_amd', - 595: 'nir_intrinsic_optimization_barrier_vgpr_amd', - 596: 'nir_intrinsic_ordered_add_loop_gfx12_amd', - 597: 'nir_intrinsic_ordered_xfb_counter_add_gfx11_amd', - 598: 'nir_intrinsic_overwrite_tes_arguments_amd', - 599: 'nir_intrinsic_overwrite_vs_arguments_amd', - 600: 'nir_intrinsic_pin_cx_handle_nv', - 601: 'nir_intrinsic_preamble_end_ir3', - 602: 'nir_intrinsic_preamble_start_ir3', - 603: 'nir_intrinsic_prefetch_sam_ir3', - 604: 'nir_intrinsic_prefetch_tex_ir3', - 605: 'nir_intrinsic_prefetch_ubo_ir3', - 606: 'nir_intrinsic_printf', - 607: 'nir_intrinsic_printf_abort', - 608: 'nir_intrinsic_quad_ballot_agx', - 609: 'nir_intrinsic_quad_broadcast', - 610: 'nir_intrinsic_quad_swap_diagonal', - 611: 'nir_intrinsic_quad_swap_horizontal', - 612: 'nir_intrinsic_quad_swap_vertical', - 613: 'nir_intrinsic_quad_swizzle_amd', - 614: 'nir_intrinsic_quad_vote_all', - 615: 'nir_intrinsic_quad_vote_any', - 616: 'nir_intrinsic_r600_indirect_vertex_at_index', - 617: 'nir_intrinsic_ray_intersection_ir3', - 618: 'nir_intrinsic_read_attribute_payload_intel', - 619: 'nir_intrinsic_read_first_invocation', - 620: 'nir_intrinsic_read_getlast_ir3', - 621: 'nir_intrinsic_read_invocation', - 622: 'nir_intrinsic_read_invocation_cond_ir3', - 623: 'nir_intrinsic_reduce', - 624: 'nir_intrinsic_reduce_clusters_ir3', - 625: 'nir_intrinsic_report_ray_intersection', - 626: 'nir_intrinsic_resource_intel', - 627: 'nir_intrinsic_rotate', - 628: 'nir_intrinsic_rq_confirm_intersection', - 629: 'nir_intrinsic_rq_generate_intersection', - 630: 'nir_intrinsic_rq_initialize', - 631: 'nir_intrinsic_rq_load', - 632: 'nir_intrinsic_rq_proceed', - 633: 'nir_intrinsic_rq_terminate', - 634: 'nir_intrinsic_rt_execute_callable', - 635: 'nir_intrinsic_rt_resume', - 636: 'nir_intrinsic_rt_return_amd', - 637: 'nir_intrinsic_rt_trace_ray', - 638: 'nir_intrinsic_sample_mask_agx', - 639: 'nir_intrinsic_select_vertex_poly', - 640: 'nir_intrinsic_sendmsg_amd', - 641: 'nir_intrinsic_set_vertex_and_primitive_count', - 642: 'nir_intrinsic_shader_clock', - 643: 'nir_intrinsic_shared_append_amd', - 644: 'nir_intrinsic_shared_atomic', - 645: 'nir_intrinsic_shared_atomic_swap', - 646: 'nir_intrinsic_shared_consume_amd', - 647: 'nir_intrinsic_shuffle', - 648: 'nir_intrinsic_shuffle_down', - 649: 'nir_intrinsic_shuffle_down_uniform_ir3', - 650: 'nir_intrinsic_shuffle_up', - 651: 'nir_intrinsic_shuffle_up_uniform_ir3', - 652: 'nir_intrinsic_shuffle_xor', - 653: 'nir_intrinsic_shuffle_xor_uniform_ir3', - 654: 'nir_intrinsic_sleep_amd', - 655: 'nir_intrinsic_sparse_residency_code_and', - 656: 'nir_intrinsic_ssa_bar_nv', - 657: 'nir_intrinsic_ssbo_atomic', - 658: 'nir_intrinsic_ssbo_atomic_ir3', - 659: 'nir_intrinsic_ssbo_atomic_swap', - 660: 'nir_intrinsic_ssbo_atomic_swap_ir3', - 661: 'nir_intrinsic_stack_map_agx', - 662: 'nir_intrinsic_stack_unmap_agx', - 663: 'nir_intrinsic_store_agx', - 664: 'nir_intrinsic_store_buffer_amd', - 665: 'nir_intrinsic_store_combined_output_pan', - 666: 'nir_intrinsic_store_const_ir3', - 667: 'nir_intrinsic_store_deref', - 668: 'nir_intrinsic_store_deref_block_intel', - 669: 'nir_intrinsic_store_global', - 670: 'nir_intrinsic_store_global_2x32', - 671: 'nir_intrinsic_store_global_amd', - 672: 'nir_intrinsic_store_global_block_intel', - 673: 'nir_intrinsic_store_global_etna', - 674: 'nir_intrinsic_store_global_ir3', - 675: 'nir_intrinsic_store_hit_attrib_amd', - 676: 'nir_intrinsic_store_local_pixel_agx', - 677: 'nir_intrinsic_store_local_shared_r600', - 678: 'nir_intrinsic_store_output', - 679: 'nir_intrinsic_store_per_primitive_output', - 680: 'nir_intrinsic_store_per_primitive_payload_intel', - 681: 'nir_intrinsic_store_per_vertex_output', - 682: 'nir_intrinsic_store_per_view_output', - 683: 'nir_intrinsic_store_preamble', - 684: 'nir_intrinsic_store_raw_output_pan', - 685: 'nir_intrinsic_store_reg', - 686: 'nir_intrinsic_store_reg_indirect', - 687: 'nir_intrinsic_store_scalar_arg_amd', - 688: 'nir_intrinsic_store_scratch', - 689: 'nir_intrinsic_store_shared', - 690: 'nir_intrinsic_store_shared2_amd', - 691: 'nir_intrinsic_store_shared_block_intel', - 692: 'nir_intrinsic_store_shared_ir3', - 693: 'nir_intrinsic_store_shared_unlock_nv', - 694: 'nir_intrinsic_store_ssbo', - 695: 'nir_intrinsic_store_ssbo_block_intel', - 696: 'nir_intrinsic_store_ssbo_intel', - 697: 'nir_intrinsic_store_ssbo_ir3', - 698: 'nir_intrinsic_store_stack', - 699: 'nir_intrinsic_store_task_payload', - 700: 'nir_intrinsic_store_tf_r600', - 701: 'nir_intrinsic_store_tlb_sample_color_v3d', - 702: 'nir_intrinsic_store_uvs_agx', - 703: 'nir_intrinsic_store_vector_arg_amd', - 704: 'nir_intrinsic_store_zs_agx', - 705: 'nir_intrinsic_strict_wqm_coord_amd', - 706: 'nir_intrinsic_subfm_nv', - 707: 'nir_intrinsic_suclamp_nv', - 708: 'nir_intrinsic_sueau_nv', - 709: 'nir_intrinsic_suldga_nv', - 710: 'nir_intrinsic_sustga_nv', - 711: 'nir_intrinsic_task_payload_atomic', - 712: 'nir_intrinsic_task_payload_atomic_swap', - 713: 'nir_intrinsic_terminate', - 714: 'nir_intrinsic_terminate_if', - 715: 'nir_intrinsic_terminate_ray', - 716: 'nir_intrinsic_trace_ray', - 717: 'nir_intrinsic_trace_ray_intel', - 718: 'nir_intrinsic_unit_test_amd', - 719: 'nir_intrinsic_unit_test_divergent_amd', - 720: 'nir_intrinsic_unit_test_uniform_amd', - 721: 'nir_intrinsic_unpin_cx_handle_nv', - 722: 'nir_intrinsic_use', - 723: 'nir_intrinsic_vild_nv', - 724: 'nir_intrinsic_vote_all', - 725: 'nir_intrinsic_vote_any', - 726: 'nir_intrinsic_vote_feq', - 727: 'nir_intrinsic_vote_ieq', - 728: 'nir_intrinsic_vulkan_resource_index', - 729: 'nir_intrinsic_vulkan_resource_reindex', - 730: 'nir_intrinsic_write_invocation_amd', - 731: 'nir_intrinsic_xfb_counter_sub_gfx11_amd', - 731: 'nir_last_intrinsic', - 732: 'nir_num_intrinsics', -} -nir_intrinsic_accept_ray_intersection = 0 -nir_intrinsic_addr_mode_is = 1 -nir_intrinsic_al2p_nv = 2 -nir_intrinsic_ald_nv = 3 -nir_intrinsic_alpha_to_coverage = 4 -nir_intrinsic_as_uniform = 5 -nir_intrinsic_ast_nv = 6 -nir_intrinsic_atomic_add_gen_prim_count_amd = 7 -nir_intrinsic_atomic_add_gs_emit_prim_count_amd = 8 -nir_intrinsic_atomic_add_shader_invocation_count_amd = 9 -nir_intrinsic_atomic_add_xfb_prim_count_amd = 10 -nir_intrinsic_atomic_counter_add = 11 -nir_intrinsic_atomic_counter_add_deref = 12 -nir_intrinsic_atomic_counter_and = 13 -nir_intrinsic_atomic_counter_and_deref = 14 -nir_intrinsic_atomic_counter_comp_swap = 15 -nir_intrinsic_atomic_counter_comp_swap_deref = 16 -nir_intrinsic_atomic_counter_exchange = 17 -nir_intrinsic_atomic_counter_exchange_deref = 18 -nir_intrinsic_atomic_counter_inc = 19 -nir_intrinsic_atomic_counter_inc_deref = 20 -nir_intrinsic_atomic_counter_max = 21 -nir_intrinsic_atomic_counter_max_deref = 22 -nir_intrinsic_atomic_counter_min = 23 -nir_intrinsic_atomic_counter_min_deref = 24 -nir_intrinsic_atomic_counter_or = 25 -nir_intrinsic_atomic_counter_or_deref = 26 -nir_intrinsic_atomic_counter_post_dec = 27 -nir_intrinsic_atomic_counter_post_dec_deref = 28 -nir_intrinsic_atomic_counter_pre_dec = 29 -nir_intrinsic_atomic_counter_pre_dec_deref = 30 -nir_intrinsic_atomic_counter_read = 31 -nir_intrinsic_atomic_counter_read_deref = 32 -nir_intrinsic_atomic_counter_xor = 33 -nir_intrinsic_atomic_counter_xor_deref = 34 -nir_intrinsic_ballot = 35 -nir_intrinsic_ballot_bit_count_exclusive = 36 -nir_intrinsic_ballot_bit_count_inclusive = 37 -nir_intrinsic_ballot_bit_count_reduce = 38 -nir_intrinsic_ballot_bitfield_extract = 39 -nir_intrinsic_ballot_find_lsb = 40 -nir_intrinsic_ballot_find_msb = 41 -nir_intrinsic_ballot_relaxed = 42 -nir_intrinsic_bar_break_nv = 43 -nir_intrinsic_bar_set_nv = 44 -nir_intrinsic_bar_sync_nv = 45 -nir_intrinsic_barrier = 46 -nir_intrinsic_begin_invocation_interlock = 47 -nir_intrinsic_bindgen_return = 48 -nir_intrinsic_bindless_image_agx = 49 -nir_intrinsic_bindless_image_atomic = 50 -nir_intrinsic_bindless_image_atomic_swap = 51 -nir_intrinsic_bindless_image_descriptor_amd = 52 -nir_intrinsic_bindless_image_format = 53 -nir_intrinsic_bindless_image_fragment_mask_load_amd = 54 -nir_intrinsic_bindless_image_levels = 55 -nir_intrinsic_bindless_image_load = 56 -nir_intrinsic_bindless_image_load_raw_intel = 57 -nir_intrinsic_bindless_image_order = 58 -nir_intrinsic_bindless_image_samples = 59 -nir_intrinsic_bindless_image_samples_identical = 60 -nir_intrinsic_bindless_image_size = 61 -nir_intrinsic_bindless_image_sparse_load = 62 -nir_intrinsic_bindless_image_store = 63 -nir_intrinsic_bindless_image_store_block_agx = 64 -nir_intrinsic_bindless_image_store_raw_intel = 65 -nir_intrinsic_bindless_image_texel_address = 66 -nir_intrinsic_bindless_resource_ir3 = 67 -nir_intrinsic_brcst_active_ir3 = 68 -nir_intrinsic_btd_retire_intel = 69 -nir_intrinsic_btd_spawn_intel = 70 -nir_intrinsic_btd_stack_push_intel = 71 -nir_intrinsic_bvh64_intersect_ray_amd = 72 -nir_intrinsic_bvh8_intersect_ray_amd = 73 -nir_intrinsic_bvh_stack_rtn_amd = 74 -nir_intrinsic_cmat_binary_op = 75 -nir_intrinsic_cmat_bitcast = 76 -nir_intrinsic_cmat_construct = 77 -nir_intrinsic_cmat_convert = 78 -nir_intrinsic_cmat_copy = 79 -nir_intrinsic_cmat_extract = 80 -nir_intrinsic_cmat_insert = 81 -nir_intrinsic_cmat_length = 82 -nir_intrinsic_cmat_load = 83 -nir_intrinsic_cmat_muladd = 84 -nir_intrinsic_cmat_muladd_amd = 85 -nir_intrinsic_cmat_muladd_nv = 86 -nir_intrinsic_cmat_scalar_op = 87 -nir_intrinsic_cmat_store = 88 -nir_intrinsic_cmat_transpose = 89 -nir_intrinsic_cmat_unary_op = 90 -nir_intrinsic_convert_alu_types = 91 -nir_intrinsic_convert_cmat_intel = 92 -nir_intrinsic_copy_deref = 93 -nir_intrinsic_copy_fs_outputs_nv = 94 -nir_intrinsic_copy_global_to_uniform_ir3 = 95 -nir_intrinsic_copy_push_const_to_uniform_ir3 = 96 -nir_intrinsic_copy_ubo_to_uniform_ir3 = 97 -nir_intrinsic_ddx = 98 -nir_intrinsic_ddx_coarse = 99 -nir_intrinsic_ddx_fine = 100 -nir_intrinsic_ddy = 101 -nir_intrinsic_ddy_coarse = 102 -nir_intrinsic_ddy_fine = 103 -nir_intrinsic_debug_break = 104 -nir_intrinsic_decl_reg = 105 -nir_intrinsic_demote = 106 -nir_intrinsic_demote_if = 107 -nir_intrinsic_demote_samples = 108 -nir_intrinsic_deref_atomic = 109 -nir_intrinsic_deref_atomic_swap = 110 -nir_intrinsic_deref_buffer_array_length = 111 -nir_intrinsic_deref_implicit_array_length = 112 -nir_intrinsic_deref_mode_is = 113 -nir_intrinsic_deref_texture_src = 114 -nir_intrinsic_doorbell_agx = 115 -nir_intrinsic_dpas_intel = 116 -nir_intrinsic_dpp16_shift_amd = 117 -nir_intrinsic_elect = 118 -nir_intrinsic_elect_any_ir3 = 119 -nir_intrinsic_emit_primitive_poly = 120 -nir_intrinsic_emit_vertex = 121 -nir_intrinsic_emit_vertex_nv = 122 -nir_intrinsic_emit_vertex_with_counter = 123 -nir_intrinsic_end_invocation_interlock = 124 -nir_intrinsic_end_primitive = 125 -nir_intrinsic_end_primitive_nv = 126 -nir_intrinsic_end_primitive_with_counter = 127 -nir_intrinsic_enqueue_node_payloads = 128 -nir_intrinsic_exclusive_scan = 129 -nir_intrinsic_exclusive_scan_clusters_ir3 = 130 -nir_intrinsic_execute_callable = 131 -nir_intrinsic_execute_closest_hit_amd = 132 -nir_intrinsic_execute_miss_amd = 133 -nir_intrinsic_export_agx = 134 -nir_intrinsic_export_amd = 135 -nir_intrinsic_export_dual_src_blend_amd = 136 -nir_intrinsic_export_row_amd = 137 -nir_intrinsic_fence_helper_exit_agx = 138 -nir_intrinsic_fence_mem_to_tex_agx = 139 -nir_intrinsic_fence_pbe_to_tex_agx = 140 -nir_intrinsic_fence_pbe_to_tex_pixel_agx = 141 -nir_intrinsic_final_primitive_nv = 142 -nir_intrinsic_finalize_incoming_node_payload = 143 -nir_intrinsic_first_invocation = 144 -nir_intrinsic_fs_out_nv = 145 -nir_intrinsic_gds_atomic_add_amd = 146 -nir_intrinsic_get_ssbo_size = 147 -nir_intrinsic_get_ubo_size = 148 -nir_intrinsic_global_atomic = 149 -nir_intrinsic_global_atomic_2x32 = 150 -nir_intrinsic_global_atomic_agx = 151 -nir_intrinsic_global_atomic_amd = 152 -nir_intrinsic_global_atomic_swap = 153 -nir_intrinsic_global_atomic_swap_2x32 = 154 -nir_intrinsic_global_atomic_swap_agx = 155 -nir_intrinsic_global_atomic_swap_amd = 156 -nir_intrinsic_ignore_ray_intersection = 157 -nir_intrinsic_imadsp_nv = 158 -nir_intrinsic_image_atomic = 159 -nir_intrinsic_image_atomic_swap = 160 -nir_intrinsic_image_deref_atomic = 161 -nir_intrinsic_image_deref_atomic_swap = 162 -nir_intrinsic_image_deref_descriptor_amd = 163 -nir_intrinsic_image_deref_format = 164 -nir_intrinsic_image_deref_fragment_mask_load_amd = 165 -nir_intrinsic_image_deref_levels = 166 -nir_intrinsic_image_deref_load = 167 -nir_intrinsic_image_deref_load_info_nv = 168 -nir_intrinsic_image_deref_load_param_intel = 169 -nir_intrinsic_image_deref_load_raw_intel = 170 -nir_intrinsic_image_deref_order = 171 -nir_intrinsic_image_deref_samples = 172 -nir_intrinsic_image_deref_samples_identical = 173 -nir_intrinsic_image_deref_size = 174 -nir_intrinsic_image_deref_sparse_load = 175 -nir_intrinsic_image_deref_store = 176 -nir_intrinsic_image_deref_store_block_agx = 177 -nir_intrinsic_image_deref_store_raw_intel = 178 -nir_intrinsic_image_deref_texel_address = 179 -nir_intrinsic_image_descriptor_amd = 180 -nir_intrinsic_image_format = 181 -nir_intrinsic_image_fragment_mask_load_amd = 182 -nir_intrinsic_image_levels = 183 -nir_intrinsic_image_load = 184 -nir_intrinsic_image_load_raw_intel = 185 -nir_intrinsic_image_order = 186 -nir_intrinsic_image_samples = 187 -nir_intrinsic_image_samples_identical = 188 -nir_intrinsic_image_size = 189 -nir_intrinsic_image_sparse_load = 190 -nir_intrinsic_image_store = 191 -nir_intrinsic_image_store_block_agx = 192 -nir_intrinsic_image_store_raw_intel = 193 -nir_intrinsic_image_texel_address = 194 -nir_intrinsic_inclusive_scan = 195 -nir_intrinsic_inclusive_scan_clusters_ir3 = 196 -nir_intrinsic_initialize_node_payloads = 197 -nir_intrinsic_interp_deref_at_centroid = 198 -nir_intrinsic_interp_deref_at_offset = 199 -nir_intrinsic_interp_deref_at_sample = 200 -nir_intrinsic_interp_deref_at_vertex = 201 -nir_intrinsic_inverse_ballot = 202 -nir_intrinsic_ipa_nv = 203 -nir_intrinsic_is_helper_invocation = 204 -nir_intrinsic_is_sparse_resident_zink = 205 -nir_intrinsic_is_sparse_texels_resident = 206 -nir_intrinsic_is_subgroup_invocation_lt_amd = 207 -nir_intrinsic_isberd_nv = 208 -nir_intrinsic_lane_permute_16_amd = 209 -nir_intrinsic_last_invocation = 210 -nir_intrinsic_launch_mesh_workgroups = 211 -nir_intrinsic_launch_mesh_workgroups_with_payload_deref = 212 -nir_intrinsic_ldc_nv = 213 -nir_intrinsic_ldcx_nv = 214 -nir_intrinsic_ldtram_nv = 215 -nir_intrinsic_load_aa_line_width = 216 -nir_intrinsic_load_accel_struct_amd = 217 -nir_intrinsic_load_active_samples_agx = 218 -nir_intrinsic_load_active_subgroup_count_agx = 219 -nir_intrinsic_load_active_subgroup_invocation_agx = 220 -nir_intrinsic_load_agx = 221 -nir_intrinsic_load_alpha_reference_amd = 222 -nir_intrinsic_load_api_sample_mask_agx = 223 -nir_intrinsic_load_attrib_clamp_agx = 224 -nir_intrinsic_load_attribute_pan = 225 -nir_intrinsic_load_back_face_agx = 226 -nir_intrinsic_load_barycentric_at_offset = 227 -nir_intrinsic_load_barycentric_at_offset_nv = 228 -nir_intrinsic_load_barycentric_at_sample = 229 -nir_intrinsic_load_barycentric_centroid = 230 -nir_intrinsic_load_barycentric_coord_at_offset = 231 -nir_intrinsic_load_barycentric_coord_at_sample = 232 -nir_intrinsic_load_barycentric_coord_centroid = 233 -nir_intrinsic_load_barycentric_coord_pixel = 234 -nir_intrinsic_load_barycentric_coord_sample = 235 -nir_intrinsic_load_barycentric_model = 236 -nir_intrinsic_load_barycentric_optimize_amd = 237 -nir_intrinsic_load_barycentric_pixel = 238 -nir_intrinsic_load_barycentric_sample = 239 -nir_intrinsic_load_base_global_invocation_id = 240 -nir_intrinsic_load_base_instance = 241 -nir_intrinsic_load_base_vertex = 242 -nir_intrinsic_load_base_workgroup_id = 243 -nir_intrinsic_load_blend_const_color_a_float = 244 -nir_intrinsic_load_blend_const_color_aaaa8888_unorm = 245 -nir_intrinsic_load_blend_const_color_b_float = 246 -nir_intrinsic_load_blend_const_color_g_float = 247 -nir_intrinsic_load_blend_const_color_r_float = 248 -nir_intrinsic_load_blend_const_color_rgba = 249 -nir_intrinsic_load_blend_const_color_rgba8888_unorm = 250 -nir_intrinsic_load_btd_global_arg_addr_intel = 251 -nir_intrinsic_load_btd_local_arg_addr_intel = 252 -nir_intrinsic_load_btd_resume_sbt_addr_intel = 253 -nir_intrinsic_load_btd_shader_type_intel = 254 -nir_intrinsic_load_btd_stack_id_intel = 255 -nir_intrinsic_load_buffer_amd = 256 -nir_intrinsic_load_callable_sbt_addr_intel = 257 -nir_intrinsic_load_callable_sbt_stride_intel = 258 -nir_intrinsic_load_clamp_vertex_color_amd = 259 -nir_intrinsic_load_clip_half_line_width_amd = 260 -nir_intrinsic_load_clip_z_coeff_agx = 261 -nir_intrinsic_load_coalesced_input_count = 262 -nir_intrinsic_load_coefficients_agx = 263 -nir_intrinsic_load_color0 = 264 -nir_intrinsic_load_color1 = 265 -nir_intrinsic_load_const_buf_base_addr_lvp = 266 -nir_intrinsic_load_const_ir3 = 267 -nir_intrinsic_load_constant = 268 -nir_intrinsic_load_constant_agx = 269 -nir_intrinsic_load_constant_base_ptr = 270 -nir_intrinsic_load_converted_output_pan = 271 -nir_intrinsic_load_core_id_agx = 272 -nir_intrinsic_load_cull_any_enabled_amd = 273 -nir_intrinsic_load_cull_back_face_enabled_amd = 274 -nir_intrinsic_load_cull_ccw_amd = 275 -nir_intrinsic_load_cull_front_face_enabled_amd = 276 -nir_intrinsic_load_cull_line_viewport_xy_scale_and_offset_amd = 277 -nir_intrinsic_load_cull_mask = 278 -nir_intrinsic_load_cull_mask_and_flags_amd = 279 -nir_intrinsic_load_cull_small_line_precision_amd = 280 -nir_intrinsic_load_cull_small_lines_enabled_amd = 281 -nir_intrinsic_load_cull_small_triangle_precision_amd = 282 -nir_intrinsic_load_cull_small_triangles_enabled_amd = 283 -nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd = 284 -nir_intrinsic_load_debug_log_desc_amd = 285 -nir_intrinsic_load_depth_never_agx = 286 -nir_intrinsic_load_deref = 287 -nir_intrinsic_load_deref_block_intel = 288 -nir_intrinsic_load_draw_id = 289 -nir_intrinsic_load_esgs_vertex_stride_amd = 290 -nir_intrinsic_load_exported_agx = 291 -nir_intrinsic_load_fb_layers_v3d = 292 -nir_intrinsic_load_fbfetch_image_desc_amd = 293 -nir_intrinsic_load_fbfetch_image_fmask_desc_amd = 294 -nir_intrinsic_load_fep_w_v3d = 295 -nir_intrinsic_load_first_vertex = 296 -nir_intrinsic_load_fixed_point_size_agx = 297 -nir_intrinsic_load_flat_mask = 298 -nir_intrinsic_load_force_vrs_rates_amd = 299 -nir_intrinsic_load_frag_coord = 300 -nir_intrinsic_load_frag_coord_unscaled_ir3 = 301 -nir_intrinsic_load_frag_coord_w = 302 -nir_intrinsic_load_frag_coord_z = 303 -nir_intrinsic_load_frag_coord_zw_pan = 304 -nir_intrinsic_load_frag_invocation_count = 305 -nir_intrinsic_load_frag_offset_ir3 = 306 -nir_intrinsic_load_frag_shading_rate = 307 -nir_intrinsic_load_frag_size = 308 -nir_intrinsic_load_frag_size_ir3 = 309 -nir_intrinsic_load_from_texture_handle_agx = 310 -nir_intrinsic_load_front_face = 311 -nir_intrinsic_load_front_face_fsign = 312 -nir_intrinsic_load_fs_input_interp_deltas = 313 -nir_intrinsic_load_fs_msaa_intel = 314 -nir_intrinsic_load_fully_covered = 315 -nir_intrinsic_load_geometry_param_buffer_poly = 316 -nir_intrinsic_load_global = 317 -nir_intrinsic_load_global_2x32 = 318 -nir_intrinsic_load_global_amd = 319 -nir_intrinsic_load_global_base_ptr = 320 -nir_intrinsic_load_global_block_intel = 321 -nir_intrinsic_load_global_bounded = 322 -nir_intrinsic_load_global_constant = 323 -nir_intrinsic_load_global_constant_bounded = 324 -nir_intrinsic_load_global_constant_offset = 325 -nir_intrinsic_load_global_constant_uniform_block_intel = 326 -nir_intrinsic_load_global_etna = 327 -nir_intrinsic_load_global_invocation_id = 328 -nir_intrinsic_load_global_invocation_index = 329 -nir_intrinsic_load_global_ir3 = 330 -nir_intrinsic_load_global_size = 331 -nir_intrinsic_load_gs_header_ir3 = 332 -nir_intrinsic_load_gs_vertex_offset_amd = 333 -nir_intrinsic_load_gs_wave_id_amd = 334 -nir_intrinsic_load_helper_arg_hi_agx = 335 -nir_intrinsic_load_helper_arg_lo_agx = 336 -nir_intrinsic_load_helper_invocation = 337 -nir_intrinsic_load_helper_op_id_agx = 338 -nir_intrinsic_load_hit_attrib_amd = 339 -nir_intrinsic_load_hs_out_patch_data_offset_amd = 340 -nir_intrinsic_load_hs_patch_stride_ir3 = 341 -nir_intrinsic_load_initial_edgeflags_amd = 342 -nir_intrinsic_load_inline_data_intel = 343 -nir_intrinsic_load_input = 344 -nir_intrinsic_load_input_assembly_buffer_poly = 345 -nir_intrinsic_load_input_attachment_conv_pan = 346 -nir_intrinsic_load_input_attachment_coord = 347 -nir_intrinsic_load_input_attachment_target_pan = 348 -nir_intrinsic_load_input_topology_poly = 349 -nir_intrinsic_load_input_vertex = 350 -nir_intrinsic_load_instance_id = 351 -nir_intrinsic_load_interpolated_input = 352 -nir_intrinsic_load_intersection_opaque_amd = 353 -nir_intrinsic_load_invocation_id = 354 -nir_intrinsic_load_is_first_fan_agx = 355 -nir_intrinsic_load_is_indexed_draw = 356 -nir_intrinsic_load_kernel_input = 357 -nir_intrinsic_load_layer_id = 358 -nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd = 359 -nir_intrinsic_load_leaf_opaque_intel = 360 -nir_intrinsic_load_leaf_procedural_intel = 361 -nir_intrinsic_load_line_coord = 362 -nir_intrinsic_load_line_width = 363 -nir_intrinsic_load_local_invocation_id = 364 -nir_intrinsic_load_local_invocation_index = 365 -nir_intrinsic_load_local_pixel_agx = 366 -nir_intrinsic_load_local_shared_r600 = 367 -nir_intrinsic_load_lshs_vertex_stride_amd = 368 -nir_intrinsic_load_max_polygon_intel = 369 -nir_intrinsic_load_merged_wave_info_amd = 370 -nir_intrinsic_load_mesh_view_count = 371 -nir_intrinsic_load_mesh_view_indices = 372 -nir_intrinsic_load_multisampled_pan = 373 -nir_intrinsic_load_noperspective_varyings_pan = 374 -nir_intrinsic_load_num_subgroups = 375 -nir_intrinsic_load_num_vertices = 376 -nir_intrinsic_load_num_vertices_per_primitive_amd = 377 -nir_intrinsic_load_num_workgroups = 378 -nir_intrinsic_load_ordered_id_amd = 379 -nir_intrinsic_load_output = 380 -nir_intrinsic_load_packed_passthrough_primitive_amd = 381 -nir_intrinsic_load_param = 382 -nir_intrinsic_load_patch_vertices_in = 383 -nir_intrinsic_load_per_primitive_input = 384 -nir_intrinsic_load_per_primitive_output = 385 -nir_intrinsic_load_per_primitive_remap_intel = 386 -nir_intrinsic_load_per_vertex_input = 387 -nir_intrinsic_load_per_vertex_output = 388 -nir_intrinsic_load_per_view_output = 389 -nir_intrinsic_load_persp_center_rhw_ir3 = 390 -nir_intrinsic_load_pipeline_stat_query_enabled_amd = 391 -nir_intrinsic_load_pixel_coord = 392 -nir_intrinsic_load_point_coord = 393 -nir_intrinsic_load_point_coord_maybe_flipped = 394 -nir_intrinsic_load_poly_line_smooth_enabled = 395 -nir_intrinsic_load_polygon_stipple_agx = 396 -nir_intrinsic_load_polygon_stipple_buffer_amd = 397 -nir_intrinsic_load_preamble = 398 -nir_intrinsic_load_prim_gen_query_enabled_amd = 399 -nir_intrinsic_load_prim_xfb_query_enabled_amd = 400 -nir_intrinsic_load_primitive_id = 401 -nir_intrinsic_load_primitive_location_ir3 = 402 -nir_intrinsic_load_printf_buffer_address = 403 -nir_intrinsic_load_printf_buffer_size = 404 -nir_intrinsic_load_provoking_last = 405 -nir_intrinsic_load_provoking_vtx_amd = 406 -nir_intrinsic_load_provoking_vtx_in_prim_amd = 407 -nir_intrinsic_load_push_constant = 408 -nir_intrinsic_load_push_constant_zink = 409 -nir_intrinsic_load_r600_indirect_per_vertex_input = 410 -nir_intrinsic_load_rasterization_primitive_amd = 411 -nir_intrinsic_load_rasterization_samples_amd = 412 -nir_intrinsic_load_rasterization_stream = 413 -nir_intrinsic_load_raw_output_pan = 414 -nir_intrinsic_load_raw_vertex_id_pan = 415 -nir_intrinsic_load_raw_vertex_offset_pan = 416 -nir_intrinsic_load_ray_base_mem_addr_intel = 417 -nir_intrinsic_load_ray_flags = 418 -nir_intrinsic_load_ray_geometry_index = 419 -nir_intrinsic_load_ray_hit_kind = 420 -nir_intrinsic_load_ray_hit_sbt_addr_intel = 421 -nir_intrinsic_load_ray_hit_sbt_stride_intel = 422 -nir_intrinsic_load_ray_hw_stack_size_intel = 423 -nir_intrinsic_load_ray_instance_custom_index = 424 -nir_intrinsic_load_ray_launch_id = 425 -nir_intrinsic_load_ray_launch_size = 426 -nir_intrinsic_load_ray_miss_sbt_addr_intel = 427 -nir_intrinsic_load_ray_miss_sbt_stride_intel = 428 -nir_intrinsic_load_ray_num_dss_rt_stacks_intel = 429 -nir_intrinsic_load_ray_object_direction = 430 -nir_intrinsic_load_ray_object_origin = 431 -nir_intrinsic_load_ray_object_to_world = 432 -nir_intrinsic_load_ray_query_global_intel = 433 -nir_intrinsic_load_ray_sw_stack_size_intel = 434 -nir_intrinsic_load_ray_t_max = 435 -nir_intrinsic_load_ray_t_min = 436 -nir_intrinsic_load_ray_tracing_stack_base_lvp = 437 -nir_intrinsic_load_ray_triangle_vertex_positions = 438 -nir_intrinsic_load_ray_world_direction = 439 -nir_intrinsic_load_ray_world_origin = 440 -nir_intrinsic_load_ray_world_to_object = 441 -nir_intrinsic_load_readonly_output_pan = 442 -nir_intrinsic_load_reg = 443 -nir_intrinsic_load_reg_indirect = 444 -nir_intrinsic_load_rel_patch_id_ir3 = 445 -nir_intrinsic_load_reloc_const_intel = 446 -nir_intrinsic_load_resume_shader_address_amd = 447 -nir_intrinsic_load_ring_attr_amd = 448 -nir_intrinsic_load_ring_attr_offset_amd = 449 -nir_intrinsic_load_ring_es2gs_offset_amd = 450 -nir_intrinsic_load_ring_esgs_amd = 451 -nir_intrinsic_load_ring_gs2vs_offset_amd = 452 -nir_intrinsic_load_ring_gsvs_amd = 453 -nir_intrinsic_load_ring_mesh_scratch_amd = 454 -nir_intrinsic_load_ring_mesh_scratch_offset_amd = 455 -nir_intrinsic_load_ring_task_draw_amd = 456 -nir_intrinsic_load_ring_task_payload_amd = 457 -nir_intrinsic_load_ring_tess_factors_amd = 458 -nir_intrinsic_load_ring_tess_factors_offset_amd = 459 -nir_intrinsic_load_ring_tess_offchip_amd = 460 -nir_intrinsic_load_ring_tess_offchip_offset_amd = 461 -nir_intrinsic_load_root_agx = 462 -nir_intrinsic_load_rt_arg_scratch_offset_amd = 463 -nir_intrinsic_load_rt_conversion_pan = 464 -nir_intrinsic_load_sample_id = 465 -nir_intrinsic_load_sample_id_no_per_sample = 466 -nir_intrinsic_load_sample_mask = 467 -nir_intrinsic_load_sample_mask_in = 468 -nir_intrinsic_load_sample_pos = 469 -nir_intrinsic_load_sample_pos_from_id = 470 -nir_intrinsic_load_sample_pos_or_center = 471 -nir_intrinsic_load_sample_positions_agx = 472 -nir_intrinsic_load_sample_positions_amd = 473 -nir_intrinsic_load_sample_positions_pan = 474 -nir_intrinsic_load_sampler_handle_agx = 475 -nir_intrinsic_load_sampler_lod_parameters = 476 -nir_intrinsic_load_samples_log2_agx = 477 -nir_intrinsic_load_sbt_base_amd = 478 -nir_intrinsic_load_sbt_offset_amd = 479 -nir_intrinsic_load_sbt_stride_amd = 480 -nir_intrinsic_load_scalar_arg_amd = 481 -nir_intrinsic_load_scratch = 482 -nir_intrinsic_load_scratch_base_ptr = 483 -nir_intrinsic_load_shader_call_data_offset_lvp = 484 -nir_intrinsic_load_shader_index = 485 -nir_intrinsic_load_shader_output_pan = 486 -nir_intrinsic_load_shader_part_tests_zs_agx = 487 -nir_intrinsic_load_shader_record_ptr = 488 -nir_intrinsic_load_shared = 489 -nir_intrinsic_load_shared2_amd = 490 -nir_intrinsic_load_shared_base_ptr = 491 -nir_intrinsic_load_shared_block_intel = 492 -nir_intrinsic_load_shared_ir3 = 493 -nir_intrinsic_load_shared_lock_nv = 494 -nir_intrinsic_load_shared_uniform_block_intel = 495 -nir_intrinsic_load_simd_width_intel = 496 -nir_intrinsic_load_sm_count_nv = 497 -nir_intrinsic_load_sm_id_nv = 498 -nir_intrinsic_load_smem_amd = 499 -nir_intrinsic_load_ssbo = 500 -nir_intrinsic_load_ssbo_address = 501 -nir_intrinsic_load_ssbo_block_intel = 502 -nir_intrinsic_load_ssbo_intel = 503 -nir_intrinsic_load_ssbo_ir3 = 504 -nir_intrinsic_load_ssbo_uniform_block_intel = 505 -nir_intrinsic_load_stack = 506 -nir_intrinsic_load_stat_query_address_agx = 507 -nir_intrinsic_load_streamout_buffer_amd = 508 -nir_intrinsic_load_streamout_config_amd = 509 -nir_intrinsic_load_streamout_offset_amd = 510 -nir_intrinsic_load_streamout_write_index_amd = 511 -nir_intrinsic_load_subgroup_eq_mask = 512 -nir_intrinsic_load_subgroup_ge_mask = 513 -nir_intrinsic_load_subgroup_gt_mask = 514 -nir_intrinsic_load_subgroup_id = 515 -nir_intrinsic_load_subgroup_id_shift_ir3 = 516 -nir_intrinsic_load_subgroup_invocation = 517 -nir_intrinsic_load_subgroup_le_mask = 518 -nir_intrinsic_load_subgroup_lt_mask = 519 -nir_intrinsic_load_subgroup_size = 520 -nir_intrinsic_load_sysval_agx = 521 -nir_intrinsic_load_sysval_nv = 522 -nir_intrinsic_load_task_payload = 523 -nir_intrinsic_load_task_ring_entry_amd = 524 -nir_intrinsic_load_tcs_header_ir3 = 525 -nir_intrinsic_load_tcs_in_param_base_r600 = 526 -nir_intrinsic_load_tcs_mem_attrib_stride = 527 -nir_intrinsic_load_tcs_num_patches_amd = 528 -nir_intrinsic_load_tcs_out_param_base_r600 = 529 -nir_intrinsic_load_tcs_primitive_mode_amd = 530 -nir_intrinsic_load_tcs_rel_patch_id_r600 = 531 -nir_intrinsic_load_tcs_tess_factor_base_r600 = 532 -nir_intrinsic_load_tcs_tess_levels_to_tes_amd = 533 -nir_intrinsic_load_tess_coord = 534 -nir_intrinsic_load_tess_coord_xy = 535 -nir_intrinsic_load_tess_factor_base_ir3 = 536 -nir_intrinsic_load_tess_level_inner = 537 -nir_intrinsic_load_tess_level_inner_default = 538 -nir_intrinsic_load_tess_level_outer = 539 -nir_intrinsic_load_tess_level_outer_default = 540 -nir_intrinsic_load_tess_param_base_ir3 = 541 -nir_intrinsic_load_tess_param_buffer_poly = 542 -nir_intrinsic_load_tess_rel_patch_id_amd = 543 -nir_intrinsic_load_tex_sprite_mask_agx = 544 -nir_intrinsic_load_texture_handle_agx = 545 -nir_intrinsic_load_texture_scale = 546 -nir_intrinsic_load_texture_size_etna = 547 -nir_intrinsic_load_tlb_color_brcm = 548 -nir_intrinsic_load_topology_id_intel = 549 -nir_intrinsic_load_typed_buffer_amd = 550 -nir_intrinsic_load_uav_ir3 = 551 -nir_intrinsic_load_ubo = 552 -nir_intrinsic_load_ubo_uniform_block_intel = 553 -nir_intrinsic_load_ubo_vec4 = 554 -nir_intrinsic_load_uniform = 555 -nir_intrinsic_load_user_clip_plane = 556 -nir_intrinsic_load_user_data_amd = 557 -nir_intrinsic_load_uvs_index_agx = 558 -nir_intrinsic_load_vbo_base_agx = 559 -nir_intrinsic_load_vector_arg_amd = 560 -nir_intrinsic_load_vertex_id = 561 -nir_intrinsic_load_vertex_id_zero_base = 562 -nir_intrinsic_load_view_index = 563 -nir_intrinsic_load_viewport_offset = 564 -nir_intrinsic_load_viewport_scale = 565 -nir_intrinsic_load_viewport_x_offset = 566 -nir_intrinsic_load_viewport_x_scale = 567 -nir_intrinsic_load_viewport_y_offset = 568 -nir_intrinsic_load_viewport_y_scale = 569 -nir_intrinsic_load_viewport_z_offset = 570 -nir_intrinsic_load_viewport_z_scale = 571 -nir_intrinsic_load_vs_output_buffer_poly = 572 -nir_intrinsic_load_vs_outputs_poly = 573 -nir_intrinsic_load_vs_primitive_stride_ir3 = 574 -nir_intrinsic_load_vs_vertex_stride_ir3 = 575 -nir_intrinsic_load_vulkan_descriptor = 576 -nir_intrinsic_load_warp_id_nv = 577 -nir_intrinsic_load_warps_per_sm_nv = 578 -nir_intrinsic_load_work_dim = 579 -nir_intrinsic_load_workgroup_id = 580 -nir_intrinsic_load_workgroup_index = 581 -nir_intrinsic_load_workgroup_num_input_primitives_amd = 582 -nir_intrinsic_load_workgroup_num_input_vertices_amd = 583 -nir_intrinsic_load_workgroup_size = 584 -nir_intrinsic_load_xfb_address = 585 -nir_intrinsic_load_xfb_index_buffer = 586 -nir_intrinsic_load_xfb_size = 587 -nir_intrinsic_load_xfb_state_address_gfx12_amd = 588 -nir_intrinsic_masked_swizzle_amd = 589 -nir_intrinsic_mbcnt_amd = 590 -nir_intrinsic_memcpy_deref = 591 -nir_intrinsic_nop = 592 -nir_intrinsic_nop_amd = 593 -nir_intrinsic_optimization_barrier_sgpr_amd = 594 -nir_intrinsic_optimization_barrier_vgpr_amd = 595 -nir_intrinsic_ordered_add_loop_gfx12_amd = 596 -nir_intrinsic_ordered_xfb_counter_add_gfx11_amd = 597 -nir_intrinsic_overwrite_tes_arguments_amd = 598 -nir_intrinsic_overwrite_vs_arguments_amd = 599 -nir_intrinsic_pin_cx_handle_nv = 600 -nir_intrinsic_preamble_end_ir3 = 601 -nir_intrinsic_preamble_start_ir3 = 602 -nir_intrinsic_prefetch_sam_ir3 = 603 -nir_intrinsic_prefetch_tex_ir3 = 604 -nir_intrinsic_prefetch_ubo_ir3 = 605 -nir_intrinsic_printf = 606 -nir_intrinsic_printf_abort = 607 -nir_intrinsic_quad_ballot_agx = 608 -nir_intrinsic_quad_broadcast = 609 -nir_intrinsic_quad_swap_diagonal = 610 -nir_intrinsic_quad_swap_horizontal = 611 -nir_intrinsic_quad_swap_vertical = 612 -nir_intrinsic_quad_swizzle_amd = 613 -nir_intrinsic_quad_vote_all = 614 -nir_intrinsic_quad_vote_any = 615 -nir_intrinsic_r600_indirect_vertex_at_index = 616 -nir_intrinsic_ray_intersection_ir3 = 617 -nir_intrinsic_read_attribute_payload_intel = 618 -nir_intrinsic_read_first_invocation = 619 -nir_intrinsic_read_getlast_ir3 = 620 -nir_intrinsic_read_invocation = 621 -nir_intrinsic_read_invocation_cond_ir3 = 622 -nir_intrinsic_reduce = 623 -nir_intrinsic_reduce_clusters_ir3 = 624 -nir_intrinsic_report_ray_intersection = 625 -nir_intrinsic_resource_intel = 626 -nir_intrinsic_rotate = 627 -nir_intrinsic_rq_confirm_intersection = 628 -nir_intrinsic_rq_generate_intersection = 629 -nir_intrinsic_rq_initialize = 630 -nir_intrinsic_rq_load = 631 -nir_intrinsic_rq_proceed = 632 -nir_intrinsic_rq_terminate = 633 -nir_intrinsic_rt_execute_callable = 634 -nir_intrinsic_rt_resume = 635 -nir_intrinsic_rt_return_amd = 636 -nir_intrinsic_rt_trace_ray = 637 -nir_intrinsic_sample_mask_agx = 638 -nir_intrinsic_select_vertex_poly = 639 -nir_intrinsic_sendmsg_amd = 640 -nir_intrinsic_set_vertex_and_primitive_count = 641 -nir_intrinsic_shader_clock = 642 -nir_intrinsic_shared_append_amd = 643 -nir_intrinsic_shared_atomic = 644 -nir_intrinsic_shared_atomic_swap = 645 -nir_intrinsic_shared_consume_amd = 646 -nir_intrinsic_shuffle = 647 -nir_intrinsic_shuffle_down = 648 -nir_intrinsic_shuffle_down_uniform_ir3 = 649 -nir_intrinsic_shuffle_up = 650 -nir_intrinsic_shuffle_up_uniform_ir3 = 651 -nir_intrinsic_shuffle_xor = 652 -nir_intrinsic_shuffle_xor_uniform_ir3 = 653 -nir_intrinsic_sleep_amd = 654 -nir_intrinsic_sparse_residency_code_and = 655 -nir_intrinsic_ssa_bar_nv = 656 -nir_intrinsic_ssbo_atomic = 657 -nir_intrinsic_ssbo_atomic_ir3 = 658 -nir_intrinsic_ssbo_atomic_swap = 659 -nir_intrinsic_ssbo_atomic_swap_ir3 = 660 -nir_intrinsic_stack_map_agx = 661 -nir_intrinsic_stack_unmap_agx = 662 -nir_intrinsic_store_agx = 663 -nir_intrinsic_store_buffer_amd = 664 -nir_intrinsic_store_combined_output_pan = 665 -nir_intrinsic_store_const_ir3 = 666 -nir_intrinsic_store_deref = 667 -nir_intrinsic_store_deref_block_intel = 668 -nir_intrinsic_store_global = 669 -nir_intrinsic_store_global_2x32 = 670 -nir_intrinsic_store_global_amd = 671 -nir_intrinsic_store_global_block_intel = 672 -nir_intrinsic_store_global_etna = 673 -nir_intrinsic_store_global_ir3 = 674 -nir_intrinsic_store_hit_attrib_amd = 675 -nir_intrinsic_store_local_pixel_agx = 676 -nir_intrinsic_store_local_shared_r600 = 677 -nir_intrinsic_store_output = 678 -nir_intrinsic_store_per_primitive_output = 679 -nir_intrinsic_store_per_primitive_payload_intel = 680 -nir_intrinsic_store_per_vertex_output = 681 -nir_intrinsic_store_per_view_output = 682 -nir_intrinsic_store_preamble = 683 -nir_intrinsic_store_raw_output_pan = 684 -nir_intrinsic_store_reg = 685 -nir_intrinsic_store_reg_indirect = 686 -nir_intrinsic_store_scalar_arg_amd = 687 -nir_intrinsic_store_scratch = 688 -nir_intrinsic_store_shared = 689 -nir_intrinsic_store_shared2_amd = 690 -nir_intrinsic_store_shared_block_intel = 691 -nir_intrinsic_store_shared_ir3 = 692 -nir_intrinsic_store_shared_unlock_nv = 693 -nir_intrinsic_store_ssbo = 694 -nir_intrinsic_store_ssbo_block_intel = 695 -nir_intrinsic_store_ssbo_intel = 696 -nir_intrinsic_store_ssbo_ir3 = 697 -nir_intrinsic_store_stack = 698 -nir_intrinsic_store_task_payload = 699 -nir_intrinsic_store_tf_r600 = 700 -nir_intrinsic_store_tlb_sample_color_v3d = 701 -nir_intrinsic_store_uvs_agx = 702 -nir_intrinsic_store_vector_arg_amd = 703 -nir_intrinsic_store_zs_agx = 704 -nir_intrinsic_strict_wqm_coord_amd = 705 -nir_intrinsic_subfm_nv = 706 -nir_intrinsic_suclamp_nv = 707 -nir_intrinsic_sueau_nv = 708 -nir_intrinsic_suldga_nv = 709 -nir_intrinsic_sustga_nv = 710 -nir_intrinsic_task_payload_atomic = 711 -nir_intrinsic_task_payload_atomic_swap = 712 -nir_intrinsic_terminate = 713 -nir_intrinsic_terminate_if = 714 -nir_intrinsic_terminate_ray = 715 -nir_intrinsic_trace_ray = 716 -nir_intrinsic_trace_ray_intel = 717 -nir_intrinsic_unit_test_amd = 718 -nir_intrinsic_unit_test_divergent_amd = 719 -nir_intrinsic_unit_test_uniform_amd = 720 -nir_intrinsic_unpin_cx_handle_nv = 721 -nir_intrinsic_use = 722 -nir_intrinsic_vild_nv = 723 -nir_intrinsic_vote_all = 724 -nir_intrinsic_vote_any = 725 -nir_intrinsic_vote_feq = 726 -nir_intrinsic_vote_ieq = 727 -nir_intrinsic_vulkan_resource_index = 728 -nir_intrinsic_vulkan_resource_reindex = 729 -nir_intrinsic_write_invocation_amd = 730 -nir_intrinsic_xfb_counter_sub_gfx11_amd = 731 -nir_last_intrinsic = 731 -nir_num_intrinsics = 732 -c__EA_nir_intrinsic_op = ctypes.c_uint32 # enum -nir_intrinsic_op = c__EA_nir_intrinsic_op -nir_intrinsic_op__enumvalues = c__EA_nir_intrinsic_op__enumvalues - -# values for enumeration 'c__EA_nir_intrinsic_index_flag' -c__EA_nir_intrinsic_index_flag__enumvalues = { - 0: 'NIR_INTRINSIC_BASE', - 1: 'NIR_INTRINSIC_WRITE_MASK', - 2: 'NIR_INTRINSIC_STREAM_ID', - 3: 'NIR_INTRINSIC_UCP_ID', - 4: 'NIR_INTRINSIC_RANGE_BASE', - 5: 'NIR_INTRINSIC_RANGE', - 6: 'NIR_INTRINSIC_DESC_SET', - 7: 'NIR_INTRINSIC_BINDING', - 8: 'NIR_INTRINSIC_COMPONENT', - 9: 'NIR_INTRINSIC_COLUMN', - 10: 'NIR_INTRINSIC_INTERP_MODE', - 11: 'NIR_INTRINSIC_REDUCTION_OP', - 12: 'NIR_INTRINSIC_CLUSTER_SIZE', - 13: 'NIR_INTRINSIC_PARAM_IDX', - 14: 'NIR_INTRINSIC_IMAGE_DIM', - 15: 'NIR_INTRINSIC_IMAGE_ARRAY', - 16: 'NIR_INTRINSIC_FORMAT', - 17: 'NIR_INTRINSIC_ACCESS', - 18: 'NIR_INTRINSIC_CALL_IDX', - 19: 'NIR_INTRINSIC_STACK_SIZE', - 20: 'NIR_INTRINSIC_ALIGN_MUL', - 21: 'NIR_INTRINSIC_ALIGN_OFFSET', - 22: 'NIR_INTRINSIC_DESC_TYPE', - 23: 'NIR_INTRINSIC_SRC_TYPE', - 24: 'NIR_INTRINSIC_DEST_TYPE', - 25: 'NIR_INTRINSIC_SRC_BASE_TYPE', - 26: 'NIR_INTRINSIC_SRC_BASE_TYPE2', - 27: 'NIR_INTRINSIC_DEST_BASE_TYPE', - 28: 'NIR_INTRINSIC_SWIZZLE_MASK', - 29: 'NIR_INTRINSIC_FETCH_INACTIVE', - 30: 'NIR_INTRINSIC_OFFSET0', - 31: 'NIR_INTRINSIC_OFFSET1', - 32: 'NIR_INTRINSIC_ST64', - 33: 'NIR_INTRINSIC_ARG_UPPER_BOUND_U32_AMD', - 34: 'NIR_INTRINSIC_DST_ACCESS', - 35: 'NIR_INTRINSIC_SRC_ACCESS', - 36: 'NIR_INTRINSIC_DRIVER_LOCATION', - 37: 'NIR_INTRINSIC_MEMORY_SEMANTICS', - 38: 'NIR_INTRINSIC_MEMORY_MODES', - 39: 'NIR_INTRINSIC_MEMORY_SCOPE', - 40: 'NIR_INTRINSIC_EXECUTION_SCOPE', - 41: 'NIR_INTRINSIC_IO_SEMANTICS', - 42: 'NIR_INTRINSIC_IO_XFB', - 43: 'NIR_INTRINSIC_IO_XFB2', - 44: 'NIR_INTRINSIC_RAY_QUERY_VALUE', - 45: 'NIR_INTRINSIC_COMMITTED', - 46: 'NIR_INTRINSIC_ROUNDING_MODE', - 47: 'NIR_INTRINSIC_SATURATE', - 48: 'NIR_INTRINSIC_SYNCHRONOUS', - 49: 'NIR_INTRINSIC_VALUE_ID', - 50: 'NIR_INTRINSIC_SIGN_EXTEND', - 51: 'NIR_INTRINSIC_FLAGS', - 52: 'NIR_INTRINSIC_ATOMIC_OP', - 53: 'NIR_INTRINSIC_RESOURCE_BLOCK_INTEL', - 54: 'NIR_INTRINSIC_RESOURCE_ACCESS_INTEL', - 55: 'NIR_INTRINSIC_NUM_COMPONENTS', - 56: 'NIR_INTRINSIC_NUM_ARRAY_ELEMS', - 57: 'NIR_INTRINSIC_BIT_SIZE', - 58: 'NIR_INTRINSIC_DIVERGENT', - 59: 'NIR_INTRINSIC_LEGACY_FABS', - 60: 'NIR_INTRINSIC_LEGACY_FNEG', - 61: 'NIR_INTRINSIC_LEGACY_FSAT', - 62: 'NIR_INTRINSIC_CMAT_DESC', - 63: 'NIR_INTRINSIC_MATRIX_LAYOUT', - 64: 'NIR_INTRINSIC_CMAT_SIGNED_MASK', - 65: 'NIR_INTRINSIC_ALU_OP', - 66: 'NIR_INTRINSIC_NEG_LO_AMD', - 67: 'NIR_INTRINSIC_NEG_HI_AMD', - 68: 'NIR_INTRINSIC_SYSTOLIC_DEPTH', - 69: 'NIR_INTRINSIC_REPEAT_COUNT', - 70: 'NIR_INTRINSIC_DST_CMAT_DESC', - 71: 'NIR_INTRINSIC_SRC_CMAT_DESC', - 72: 'NIR_INTRINSIC_EXPLICIT_COORD', - 73: 'NIR_INTRINSIC_FMT_IDX', - 74: 'NIR_INTRINSIC_PREAMBLE_CLASS', - 75: 'NIR_INTRINSIC_NUM_INDEX_FLAGS', -} -NIR_INTRINSIC_BASE = 0 -NIR_INTRINSIC_WRITE_MASK = 1 -NIR_INTRINSIC_STREAM_ID = 2 -NIR_INTRINSIC_UCP_ID = 3 -NIR_INTRINSIC_RANGE_BASE = 4 -NIR_INTRINSIC_RANGE = 5 -NIR_INTRINSIC_DESC_SET = 6 -NIR_INTRINSIC_BINDING = 7 -NIR_INTRINSIC_COMPONENT = 8 -NIR_INTRINSIC_COLUMN = 9 -NIR_INTRINSIC_INTERP_MODE = 10 -NIR_INTRINSIC_REDUCTION_OP = 11 -NIR_INTRINSIC_CLUSTER_SIZE = 12 -NIR_INTRINSIC_PARAM_IDX = 13 -NIR_INTRINSIC_IMAGE_DIM = 14 -NIR_INTRINSIC_IMAGE_ARRAY = 15 -NIR_INTRINSIC_FORMAT = 16 -NIR_INTRINSIC_ACCESS = 17 -NIR_INTRINSIC_CALL_IDX = 18 -NIR_INTRINSIC_STACK_SIZE = 19 -NIR_INTRINSIC_ALIGN_MUL = 20 -NIR_INTRINSIC_ALIGN_OFFSET = 21 -NIR_INTRINSIC_DESC_TYPE = 22 -NIR_INTRINSIC_SRC_TYPE = 23 -NIR_INTRINSIC_DEST_TYPE = 24 -NIR_INTRINSIC_SRC_BASE_TYPE = 25 -NIR_INTRINSIC_SRC_BASE_TYPE2 = 26 -NIR_INTRINSIC_DEST_BASE_TYPE = 27 -NIR_INTRINSIC_SWIZZLE_MASK = 28 -NIR_INTRINSIC_FETCH_INACTIVE = 29 -NIR_INTRINSIC_OFFSET0 = 30 -NIR_INTRINSIC_OFFSET1 = 31 -NIR_INTRINSIC_ST64 = 32 -NIR_INTRINSIC_ARG_UPPER_BOUND_U32_AMD = 33 -NIR_INTRINSIC_DST_ACCESS = 34 -NIR_INTRINSIC_SRC_ACCESS = 35 -NIR_INTRINSIC_DRIVER_LOCATION = 36 -NIR_INTRINSIC_MEMORY_SEMANTICS = 37 -NIR_INTRINSIC_MEMORY_MODES = 38 -NIR_INTRINSIC_MEMORY_SCOPE = 39 -NIR_INTRINSIC_EXECUTION_SCOPE = 40 -NIR_INTRINSIC_IO_SEMANTICS = 41 -NIR_INTRINSIC_IO_XFB = 42 -NIR_INTRINSIC_IO_XFB2 = 43 -NIR_INTRINSIC_RAY_QUERY_VALUE = 44 -NIR_INTRINSIC_COMMITTED = 45 -NIR_INTRINSIC_ROUNDING_MODE = 46 -NIR_INTRINSIC_SATURATE = 47 -NIR_INTRINSIC_SYNCHRONOUS = 48 -NIR_INTRINSIC_VALUE_ID = 49 -NIR_INTRINSIC_SIGN_EXTEND = 50 -NIR_INTRINSIC_FLAGS = 51 -NIR_INTRINSIC_ATOMIC_OP = 52 -NIR_INTRINSIC_RESOURCE_BLOCK_INTEL = 53 -NIR_INTRINSIC_RESOURCE_ACCESS_INTEL = 54 -NIR_INTRINSIC_NUM_COMPONENTS = 55 -NIR_INTRINSIC_NUM_ARRAY_ELEMS = 56 -NIR_INTRINSIC_BIT_SIZE = 57 -NIR_INTRINSIC_DIVERGENT = 58 -NIR_INTRINSIC_LEGACY_FABS = 59 -NIR_INTRINSIC_LEGACY_FNEG = 60 -NIR_INTRINSIC_LEGACY_FSAT = 61 -NIR_INTRINSIC_CMAT_DESC = 62 -NIR_INTRINSIC_MATRIX_LAYOUT = 63 -NIR_INTRINSIC_CMAT_SIGNED_MASK = 64 -NIR_INTRINSIC_ALU_OP = 65 -NIR_INTRINSIC_NEG_LO_AMD = 66 -NIR_INTRINSIC_NEG_HI_AMD = 67 -NIR_INTRINSIC_SYSTOLIC_DEPTH = 68 -NIR_INTRINSIC_REPEAT_COUNT = 69 -NIR_INTRINSIC_DST_CMAT_DESC = 70 -NIR_INTRINSIC_SRC_CMAT_DESC = 71 -NIR_INTRINSIC_EXPLICIT_COORD = 72 -NIR_INTRINSIC_FMT_IDX = 73 -NIR_INTRINSIC_PREAMBLE_CLASS = 74 -NIR_INTRINSIC_NUM_INDEX_FLAGS = 75 -c__EA_nir_intrinsic_index_flag = ctypes.c_uint32 # enum -nir_intrinsic_index_flag = c__EA_nir_intrinsic_index_flag -nir_intrinsic_index_flag__enumvalues = c__EA_nir_intrinsic_index_flag__enumvalues -try: nir_intrinsic_index_names = (ctypes.POINTER(ctypes.c_char) * 75).in_dll(_libraries['libtinymesa_cpu.so'], 'nir_intrinsic_index_names') -except (AttributeError, ValueError): pass -class struct_nir_intrinsic_instr(Structure): - pass - -struct_nir_intrinsic_instr._pack_ = 1 # source:False -struct_nir_intrinsic_instr._fields_ = [ - ('instr', nir_instr), - ('intrinsic', nir_intrinsic_op), - ('PADDING_0', ctypes.c_ubyte * 4), - ('def', nir_def), - ('num_components', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('const_index', ctypes.c_int32 * 8), - ('PADDING_2', ctypes.c_ubyte * 4), - ('name', ctypes.POINTER(ctypes.c_char)), - ('src', struct_nir_src * 0), -] - -nir_intrinsic_instr = struct_nir_intrinsic_instr -try: - nir_intrinsic_get_var = _libraries['FIXME_STUB'].nir_intrinsic_get_var - nir_intrinsic_get_var.restype = ctypes.POINTER(struct_nir_variable) - nir_intrinsic_get_var.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_memory_semantics' -c__EA_nir_memory_semantics__enumvalues = { - 1: 'NIR_MEMORY_ACQUIRE', - 2: 'NIR_MEMORY_RELEASE', - 3: 'NIR_MEMORY_ACQ_REL', - 4: 'NIR_MEMORY_MAKE_AVAILABLE', - 8: 'NIR_MEMORY_MAKE_VISIBLE', -} -NIR_MEMORY_ACQUIRE = 1 -NIR_MEMORY_RELEASE = 2 -NIR_MEMORY_ACQ_REL = 3 -NIR_MEMORY_MAKE_AVAILABLE = 4 -NIR_MEMORY_MAKE_VISIBLE = 8 -c__EA_nir_memory_semantics = ctypes.c_uint32 # enum -nir_memory_semantics = c__EA_nir_memory_semantics -nir_memory_semantics__enumvalues = c__EA_nir_memory_semantics__enumvalues - -# values for enumeration 'c__EA_nir_intrinsic_semantic_flag' -c__EA_nir_intrinsic_semantic_flag__enumvalues = { - 1: 'NIR_INTRINSIC_CAN_ELIMINATE', - 2: 'NIR_INTRINSIC_CAN_REORDER', - 4: 'NIR_INTRINSIC_SUBGROUP', - 8: 'NIR_INTRINSIC_QUADGROUP', -} -NIR_INTRINSIC_CAN_ELIMINATE = 1 -NIR_INTRINSIC_CAN_REORDER = 2 -NIR_INTRINSIC_SUBGROUP = 4 -NIR_INTRINSIC_QUADGROUP = 8 -c__EA_nir_intrinsic_semantic_flag = ctypes.c_uint32 # enum -nir_intrinsic_semantic_flag = c__EA_nir_intrinsic_semantic_flag -nir_intrinsic_semantic_flag__enumvalues = c__EA_nir_intrinsic_semantic_flag__enumvalues -class struct_nir_io_semantics(Structure): - pass - -struct_nir_io_semantics._pack_ = 1 # source:False -struct_nir_io_semantics._fields_ = [ - ('location', ctypes.c_uint32, 7), - ('num_slots', ctypes.c_uint32, 6), - ('dual_source_blend_index', ctypes.c_uint32, 1), - ('fb_fetch_output', ctypes.c_uint32, 1), - ('fb_fetch_output_coherent', ctypes.c_uint32, 1), - ('gs_streams', ctypes.c_uint32, 8), - ('medium_precision', ctypes.c_uint32, 1), - ('per_view', ctypes.c_uint32, 1), - ('high_16bits', ctypes.c_uint32, 1), - ('high_dvec2', ctypes.c_uint32, 1), - ('no_varying', ctypes.c_uint32, 1), - ('no_sysval_output', ctypes.c_uint32, 1), - ('interp_explicit_strict', ctypes.c_uint32, 1), - ('_pad', ctypes.c_uint32, 1), -] - -nir_io_semantics = struct_nir_io_semantics -class struct_nir_io_xfb(Structure): - pass - -class struct_nir_io_xfb_0(Structure): - pass - -struct_nir_io_xfb_0._pack_ = 1 # source:False -struct_nir_io_xfb_0._fields_ = [ - ('num_components', ctypes.c_ubyte, 4), - ('buffer', ctypes.c_ubyte, 4), - ('offset', ctypes.c_ubyte, 8), -] - -struct_nir_io_xfb._pack_ = 1 # source:False -struct_nir_io_xfb._fields_ = [ - ('out', struct_nir_io_xfb_0 * 2), -] - -nir_io_xfb = struct_nir_io_xfb -try: - nir_instr_xfb_write_mask = _libraries['libtinymesa_cpu.so'].nir_instr_xfb_write_mask - nir_instr_xfb_write_mask.restype = ctypes.c_uint32 - nir_instr_xfb_write_mask.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -class struct_nir_intrinsic_info(Structure): - pass - -struct_nir_intrinsic_info._pack_ = 1 # source:False -struct_nir_intrinsic_info._fields_ = [ - ('name', ctypes.POINTER(ctypes.c_char)), - ('num_srcs', ctypes.c_ubyte), - ('src_components', ctypes.c_byte * 11), - ('has_dest', ctypes.c_bool), - ('dest_components', ctypes.c_ubyte), - ('dest_bit_sizes', ctypes.c_ubyte), - ('bit_size_src', ctypes.c_byte), - ('num_indices', ctypes.c_ubyte), - ('indices', ctypes.c_ubyte * 8), - ('index_map', ctypes.c_ubyte * 75), - ('flags', nir_intrinsic_semantic_flag), -] - -nir_intrinsic_info = struct_nir_intrinsic_info -try: nir_intrinsic_infos = (struct_nir_intrinsic_info * 732).in_dll(_libraries['libtinymesa_cpu.so'], 'nir_intrinsic_infos') -except (AttributeError, ValueError): pass -try: - nir_intrinsic_src_components = _libraries['libtinymesa_cpu.so'].nir_intrinsic_src_components - nir_intrinsic_src_components.restype = ctypes.c_uint32 - nir_intrinsic_src_components.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_intrinsic_dest_components = _libraries['libtinymesa_cpu.so'].nir_intrinsic_dest_components - nir_intrinsic_dest_components.restype = ctypes.c_uint32 - nir_intrinsic_dest_components.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_intrinsic_instr_src_type = _libraries['libtinymesa_cpu.so'].nir_intrinsic_instr_src_type - nir_intrinsic_instr_src_type.restype = nir_alu_type - nir_intrinsic_instr_src_type.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_intrinsic_instr_dest_type = _libraries['libtinymesa_cpu.so'].nir_intrinsic_instr_dest_type - nir_intrinsic_instr_dest_type.restype = nir_alu_type - nir_intrinsic_instr_dest_type.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_intrinsic_copy_const_indices = _libraries['libtinymesa_cpu.so'].nir_intrinsic_copy_const_indices - nir_intrinsic_copy_const_indices.restype = None - nir_intrinsic_copy_const_indices.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_intrinsic_set_align = _libraries['FIXME_STUB'].nir_intrinsic_set_align - nir_intrinsic_set_align.restype = None - nir_intrinsic_set_align.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_combined_align = _libraries['FIXME_STUB'].nir_combined_align - nir_combined_align.restype = uint32_t - nir_combined_align.argtypes = [uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_intrinsic_align = _libraries['FIXME_STUB'].nir_intrinsic_align - nir_intrinsic_align.restype = ctypes.c_uint32 - nir_intrinsic_align.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_intrinsic_has_align = _libraries['FIXME_STUB'].nir_intrinsic_has_align - nir_intrinsic_has_align.restype = ctypes.c_bool - nir_intrinsic_has_align.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_image_intrinsic_coord_components = _libraries['libtinymesa_cpu.so'].nir_image_intrinsic_coord_components - nir_image_intrinsic_coord_components.restype = ctypes.c_uint32 - nir_image_intrinsic_coord_components.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_rewrite_image_intrinsic = _libraries['libtinymesa_cpu.so'].nir_rewrite_image_intrinsic - nir_rewrite_image_intrinsic.restype = None - nir_rewrite_image_intrinsic.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_def), ctypes.c_bool] -except AttributeError: - pass -try: - nir_intrinsic_can_reorder = _libraries['libtinymesa_cpu.so'].nir_intrinsic_can_reorder - nir_intrinsic_can_reorder.restype = ctypes.c_bool - nir_intrinsic_can_reorder.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_intrinsic_writes_external_memory = _libraries['libtinymesa_cpu.so'].nir_intrinsic_writes_external_memory - nir_intrinsic_writes_external_memory.restype = ctypes.c_bool - nir_intrinsic_writes_external_memory.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_intrinsic_has_semantic = _libraries['FIXME_STUB'].nir_intrinsic_has_semantic - nir_intrinsic_has_semantic.restype = ctypes.c_bool - nir_intrinsic_has_semantic.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), nir_intrinsic_semantic_flag] -except AttributeError: - pass -try: - nir_intrinsic_is_ray_query = _libraries['FIXME_STUB'].nir_intrinsic_is_ray_query - nir_intrinsic_is_ray_query.restype = ctypes.c_bool - nir_intrinsic_is_ray_query.argtypes = [nir_intrinsic_op] -except AttributeError: - pass - -# values for enumeration 'nir_tex_src_type' -nir_tex_src_type__enumvalues = { - 0: 'nir_tex_src_coord', - 1: 'nir_tex_src_projector', - 2: 'nir_tex_src_comparator', - 3: 'nir_tex_src_offset', - 4: 'nir_tex_src_bias', - 5: 'nir_tex_src_lod', - 6: 'nir_tex_src_min_lod', - 7: 'nir_tex_src_lod_bias_min_agx', - 8: 'nir_tex_src_ms_index', - 9: 'nir_tex_src_ms_mcs_intel', - 10: 'nir_tex_src_ddx', - 11: 'nir_tex_src_ddy', - 12: 'nir_tex_src_texture_deref', - 13: 'nir_tex_src_sampler_deref', - 14: 'nir_tex_src_texture_offset', - 15: 'nir_tex_src_sampler_offset', - 16: 'nir_tex_src_texture_handle', - 17: 'nir_tex_src_sampler_handle', - 18: 'nir_tex_src_sampler_deref_intrinsic', - 19: 'nir_tex_src_texture_deref_intrinsic', - 20: 'nir_tex_src_plane', - 21: 'nir_tex_src_backend1', - 22: 'nir_tex_src_backend2', - 23: 'nir_num_tex_src_types', -} -nir_tex_src_coord = 0 -nir_tex_src_projector = 1 -nir_tex_src_comparator = 2 -nir_tex_src_offset = 3 -nir_tex_src_bias = 4 -nir_tex_src_lod = 5 -nir_tex_src_min_lod = 6 -nir_tex_src_lod_bias_min_agx = 7 -nir_tex_src_ms_index = 8 -nir_tex_src_ms_mcs_intel = 9 -nir_tex_src_ddx = 10 -nir_tex_src_ddy = 11 -nir_tex_src_texture_deref = 12 -nir_tex_src_sampler_deref = 13 -nir_tex_src_texture_offset = 14 -nir_tex_src_sampler_offset = 15 -nir_tex_src_texture_handle = 16 -nir_tex_src_sampler_handle = 17 -nir_tex_src_sampler_deref_intrinsic = 18 -nir_tex_src_texture_deref_intrinsic = 19 -nir_tex_src_plane = 20 -nir_tex_src_backend1 = 21 -nir_tex_src_backend2 = 22 -nir_num_tex_src_types = 23 -nir_tex_src_type = ctypes.c_uint32 # enum -class struct_nir_tex_src(Structure): - pass - -struct_nir_tex_src._pack_ = 1 # source:False -struct_nir_tex_src._fields_ = [ - ('src', nir_src), - ('src_type', nir_tex_src_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -nir_tex_src = struct_nir_tex_src - -# values for enumeration 'nir_texop' -nir_texop__enumvalues = { - 0: 'nir_texop_tex', - 1: 'nir_texop_txb', - 2: 'nir_texop_txl', - 3: 'nir_texop_txd', - 4: 'nir_texop_txf', - 5: 'nir_texop_txf_ms', - 6: 'nir_texop_txf_ms_fb', - 7: 'nir_texop_txf_ms_mcs_intel', - 8: 'nir_texop_txs', - 9: 'nir_texop_lod', - 10: 'nir_texop_tg4', - 11: 'nir_texop_query_levels', - 12: 'nir_texop_texture_samples', - 13: 'nir_texop_samples_identical', - 14: 'nir_texop_tex_prefetch', - 15: 'nir_texop_lod_bias', - 16: 'nir_texop_fragment_fetch_amd', - 17: 'nir_texop_fragment_mask_fetch_amd', - 18: 'nir_texop_descriptor_amd', - 19: 'nir_texop_sampler_descriptor_amd', - 20: 'nir_texop_image_min_lod_agx', - 21: 'nir_texop_has_custom_border_color_agx', - 22: 'nir_texop_custom_border_color_agx', - 23: 'nir_texop_hdr_dim_nv', - 24: 'nir_texop_tex_type_nv', -} -nir_texop_tex = 0 -nir_texop_txb = 1 -nir_texop_txl = 2 -nir_texop_txd = 3 -nir_texop_txf = 4 -nir_texop_txf_ms = 5 -nir_texop_txf_ms_fb = 6 -nir_texop_txf_ms_mcs_intel = 7 -nir_texop_txs = 8 -nir_texop_lod = 9 -nir_texop_tg4 = 10 -nir_texop_query_levels = 11 -nir_texop_texture_samples = 12 -nir_texop_samples_identical = 13 -nir_texop_tex_prefetch = 14 -nir_texop_lod_bias = 15 -nir_texop_fragment_fetch_amd = 16 -nir_texop_fragment_mask_fetch_amd = 17 -nir_texop_descriptor_amd = 18 -nir_texop_sampler_descriptor_amd = 19 -nir_texop_image_min_lod_agx = 20 -nir_texop_has_custom_border_color_agx = 21 -nir_texop_custom_border_color_agx = 22 -nir_texop_hdr_dim_nv = 23 -nir_texop_tex_type_nv = 24 -nir_texop = ctypes.c_uint32 # enum -class struct_nir_tex_instr(Structure): - pass - -struct_nir_tex_instr._pack_ = 1 # source:False -struct_nir_tex_instr._fields_ = [ - ('instr', nir_instr), - ('sampler_dim', glsl_sampler_dim), - ('dest_type', nir_alu_type), - ('op', nir_texop), - ('PADDING_0', ctypes.c_ubyte * 4), - ('def', nir_def), - ('src', ctypes.POINTER(struct_nir_tex_src)), - ('num_srcs', ctypes.c_uint32), - ('coord_components', ctypes.c_uint32), - ('is_array', ctypes.c_bool), - ('is_shadow', ctypes.c_bool), - ('is_new_style_shadow', ctypes.c_bool), - ('is_sparse', ctypes.c_bool), - ('component', ctypes.c_uint32, 2), - ('array_is_lowered_cube', ctypes.c_uint32, 1), - ('is_gather_implicit_lod', ctypes.c_uint32, 1), - ('skip_helpers', ctypes.c_uint32, 1), - ('PADDING_1', ctypes.c_uint8, 3), - ('tg4_offsets', ctypes.c_byte * 2 * 4), - ('texture_non_uniform', ctypes.c_bool), - ('sampler_non_uniform', ctypes.c_bool), - ('offset_non_uniform', ctypes.c_bool), - ('texture_index', ctypes.c_uint32), - ('sampler_index', ctypes.c_uint32), - ('backend_flags', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -nir_tex_instr = struct_nir_tex_instr -try: - nir_tex_instr_need_sampler = _libraries['libtinymesa_cpu.so'].nir_tex_instr_need_sampler - nir_tex_instr_need_sampler.restype = ctypes.c_bool - nir_tex_instr_need_sampler.argtypes = [ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -try: - nir_tex_instr_result_size = _libraries['libtinymesa_cpu.so'].nir_tex_instr_result_size - nir_tex_instr_result_size.restype = ctypes.c_uint32 - nir_tex_instr_result_size.argtypes = [ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -try: - nir_tex_instr_dest_size = _libraries['FIXME_STUB'].nir_tex_instr_dest_size - nir_tex_instr_dest_size.restype = ctypes.c_uint32 - nir_tex_instr_dest_size.argtypes = [ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -try: - nir_tex_instr_is_query = _libraries['libtinymesa_cpu.so'].nir_tex_instr_is_query - nir_tex_instr_is_query.restype = ctypes.c_bool - nir_tex_instr_is_query.argtypes = [ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -try: - nir_tex_instr_has_implicit_derivative = _libraries['libtinymesa_cpu.so'].nir_tex_instr_has_implicit_derivative - nir_tex_instr_has_implicit_derivative.restype = ctypes.c_bool - nir_tex_instr_has_implicit_derivative.argtypes = [ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -try: - nir_tex_instr_src_type = _libraries['libtinymesa_cpu.so'].nir_tex_instr_src_type - nir_tex_instr_src_type.restype = nir_alu_type - nir_tex_instr_src_type.argtypes = [ctypes.POINTER(struct_nir_tex_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_tex_instr_src_size = _libraries['libtinymesa_cpu.so'].nir_tex_instr_src_size - nir_tex_instr_src_size.restype = ctypes.c_uint32 - nir_tex_instr_src_size.argtypes = [ctypes.POINTER(struct_nir_tex_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_tex_instr_src_index = _libraries['FIXME_STUB'].nir_tex_instr_src_index - nir_tex_instr_src_index.restype = ctypes.c_int32 - nir_tex_instr_src_index.argtypes = [ctypes.POINTER(struct_nir_tex_instr), nir_tex_src_type] -except AttributeError: - pass -try: - nir_tex_instr_add_src = _libraries['libtinymesa_cpu.so'].nir_tex_instr_add_src - nir_tex_instr_add_src.restype = None - nir_tex_instr_add_src.argtypes = [ctypes.POINTER(struct_nir_tex_instr), nir_tex_src_type, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_tex_instr_remove_src = _libraries['libtinymesa_cpu.so'].nir_tex_instr_remove_src - nir_tex_instr_remove_src.restype = None - nir_tex_instr_remove_src.argtypes = [ctypes.POINTER(struct_nir_tex_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_get_tex_src = _libraries['FIXME_STUB'].nir_get_tex_src - nir_get_tex_src.restype = ctypes.POINTER(struct_nir_def) - nir_get_tex_src.argtypes = [ctypes.POINTER(struct_nir_tex_instr), nir_tex_src_type] -except AttributeError: - pass -try: - nir_get_tex_deref = _libraries['FIXME_STUB'].nir_get_tex_deref - nir_get_tex_deref.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_get_tex_deref.argtypes = [ctypes.POINTER(struct_nir_tex_instr), nir_tex_src_type] -except AttributeError: - pass -try: - nir_steal_tex_src = _libraries['FIXME_STUB'].nir_steal_tex_src - nir_steal_tex_src.restype = ctypes.POINTER(struct_nir_def) - nir_steal_tex_src.argtypes = [ctypes.POINTER(struct_nir_tex_instr), nir_tex_src_type] -except AttributeError: - pass -try: - nir_steal_tex_deref = _libraries['FIXME_STUB'].nir_steal_tex_deref - nir_steal_tex_deref.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_steal_tex_deref.argtypes = [ctypes.POINTER(struct_nir_tex_instr), nir_tex_src_type] -except AttributeError: - pass -try: - nir_tex_instr_has_explicit_tg4_offsets = _libraries['libtinymesa_cpu.so'].nir_tex_instr_has_explicit_tg4_offsets - nir_tex_instr_has_explicit_tg4_offsets.restype = ctypes.c_bool - nir_tex_instr_has_explicit_tg4_offsets.argtypes = [ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -class struct_nir_load_const_instr(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('instr', nir_instr), - ('def', nir_def), - ('value', union_c__UA_nir_const_value * 0), - ] - -nir_load_const_instr = struct_nir_load_const_instr - -# values for enumeration 'c__EA_nir_jump_type' -c__EA_nir_jump_type__enumvalues = { - 0: 'nir_jump_return', - 1: 'nir_jump_halt', - 2: 'nir_jump_break', - 3: 'nir_jump_continue', - 4: 'nir_jump_goto', - 5: 'nir_jump_goto_if', -} -nir_jump_return = 0 -nir_jump_halt = 1 -nir_jump_break = 2 -nir_jump_continue = 3 -nir_jump_goto = 4 -nir_jump_goto_if = 5 -c__EA_nir_jump_type = ctypes.c_uint32 # enum -nir_jump_type = c__EA_nir_jump_type -nir_jump_type__enumvalues = c__EA_nir_jump_type__enumvalues -class struct_nir_jump_instr(Structure): - pass - -struct_nir_jump_instr._pack_ = 1 # source:False -struct_nir_jump_instr._fields_ = [ - ('instr', nir_instr), - ('type', nir_jump_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('condition', nir_src), - ('target', ctypes.POINTER(struct_nir_block)), - ('else_target', ctypes.POINTER(struct_nir_block)), -] - -nir_jump_instr = struct_nir_jump_instr -class struct_nir_undef_instr(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('instr', nir_instr), - ('def', nir_def), - ] - -nir_undef_instr = struct_nir_undef_instr -class struct_nir_phi_src(Structure): - pass - -struct_nir_phi_src._pack_ = 1 # source:False -struct_nir_phi_src._fields_ = [ - ('node', struct_exec_node), - ('pred', ctypes.POINTER(struct_nir_block)), - ('src', nir_src), -] - -nir_phi_src = struct_nir_phi_src -class struct_nir_phi_instr(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('instr', nir_instr), - ('srcs', struct_exec_list), - ('def', nir_def), - ] - -nir_phi_instr = struct_nir_phi_instr -try: - nir_phi_get_src_from_block = _libraries['FIXME_STUB'].nir_phi_get_src_from_block - nir_phi_get_src_from_block.restype = ctypes.POINTER(struct_nir_phi_src) - nir_phi_get_src_from_block.argtypes = [ctypes.POINTER(struct_nir_phi_instr), ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -class struct_nir_parallel_copy_entry(Structure): - pass - -class union_nir_parallel_copy_entry_dest(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('def', nir_def), - ('reg', nir_src), - ] - -struct_nir_parallel_copy_entry._pack_ = 1 # source:False -struct_nir_parallel_copy_entry._fields_ = [ - ('node', struct_exec_node), - ('src_is_reg', ctypes.c_bool), - ('dest_is_reg', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 6), - ('src', nir_src), - ('dest', union_nir_parallel_copy_entry_dest), -] - -nir_parallel_copy_entry = struct_nir_parallel_copy_entry -class struct_nir_parallel_copy_instr(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('instr', nir_instr), - ('entries', struct_exec_list), - ] - -nir_parallel_copy_instr = struct_nir_parallel_copy_instr -class struct_nir_instr_debug_info(Structure): - pass - -struct_nir_instr_debug_info._pack_ = 1 # source:False -struct_nir_instr_debug_info._fields_ = [ - ('filename', ctypes.POINTER(ctypes.c_char)), - ('line', ctypes.c_uint32), - ('column', ctypes.c_uint32), - ('spirv_offset', ctypes.c_uint32), - ('nir_line', ctypes.c_uint32), - ('variable_name', ctypes.POINTER(ctypes.c_char)), - ('instr', nir_instr), -] - -nir_instr_debug_info = struct_nir_instr_debug_info -try: - nir_instr_as_alu = _libraries['FIXME_STUB'].nir_instr_as_alu - nir_instr_as_alu.restype = ctypes.POINTER(struct_nir_alu_instr) - nir_instr_as_alu.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_deref = _libraries['FIXME_STUB'].nir_instr_as_deref - nir_instr_as_deref.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_instr_as_deref.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_call = _libraries['FIXME_STUB'].nir_instr_as_call - nir_instr_as_call.restype = ctypes.POINTER(struct_nir_call_instr) - nir_instr_as_call.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_jump = _libraries['FIXME_STUB'].nir_instr_as_jump - nir_instr_as_jump.restype = ctypes.POINTER(struct_nir_jump_instr) - nir_instr_as_jump.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_tex = _libraries['FIXME_STUB'].nir_instr_as_tex - nir_instr_as_tex.restype = ctypes.POINTER(struct_nir_tex_instr) - nir_instr_as_tex.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_intrinsic = _libraries['FIXME_STUB'].nir_instr_as_intrinsic - nir_instr_as_intrinsic.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_instr_as_intrinsic.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_load_const = _libraries['FIXME_STUB'].nir_instr_as_load_const - nir_instr_as_load_const.restype = ctypes.POINTER(struct_nir_load_const_instr) - nir_instr_as_load_const.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_undef = _libraries['FIXME_STUB'].nir_instr_as_undef - nir_instr_as_undef.restype = ctypes.POINTER(struct_nir_undef_instr) - nir_instr_as_undef.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_phi = _libraries['FIXME_STUB'].nir_instr_as_phi - nir_instr_as_phi.restype = ctypes.POINTER(struct_nir_phi_instr) - nir_instr_as_phi.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_as_parallel_copy = _libraries['FIXME_STUB'].nir_instr_as_parallel_copy - nir_instr_as_parallel_copy.restype = ctypes.POINTER(struct_nir_parallel_copy_instr) - nir_instr_as_parallel_copy.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_src_comp_as_int = _libraries['FIXME_STUB'].nir_src_comp_as_int - nir_src_comp_as_int.restype = int64_t - nir_src_comp_as_int.argtypes = [nir_src, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_src_as_int = _libraries['FIXME_STUB'].nir_src_as_int - nir_src_as_int.restype = int64_t - nir_src_as_int.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_comp_as_uint = _libraries['FIXME_STUB'].nir_src_comp_as_uint - nir_src_comp_as_uint.restype = uint64_t - nir_src_comp_as_uint.argtypes = [nir_src, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_src_as_uint = _libraries['FIXME_STUB'].nir_src_as_uint - nir_src_as_uint.restype = uint64_t - nir_src_as_uint.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_comp_as_bool = _libraries['FIXME_STUB'].nir_src_comp_as_bool - nir_src_comp_as_bool.restype = ctypes.c_bool - nir_src_comp_as_bool.argtypes = [nir_src, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_src_as_bool = _libraries['FIXME_STUB'].nir_src_as_bool - nir_src_as_bool.restype = ctypes.c_bool - nir_src_as_bool.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_comp_as_float = _libraries['FIXME_STUB'].nir_src_comp_as_float - nir_src_comp_as_float.restype = ctypes.c_double - nir_src_comp_as_float.argtypes = [nir_src, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_src_as_float = _libraries['FIXME_STUB'].nir_src_as_float - nir_src_as_float.restype = ctypes.c_double - nir_src_as_float.argtypes = [nir_src] -except AttributeError: - pass -class struct_nir_scalar(Structure): - pass - -struct_nir_scalar._pack_ = 1 # source:False -struct_nir_scalar._fields_ = [ - ('def', ctypes.POINTER(struct_nir_def)), - ('comp', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -nir_scalar = struct_nir_scalar -try: - nir_scalar_is_const = _libraries['FIXME_STUB'].nir_scalar_is_const - nir_scalar_is_const.restype = ctypes.c_bool - nir_scalar_is_const.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_is_undef = _libraries['FIXME_STUB'].nir_scalar_is_undef - nir_scalar_is_undef.restype = ctypes.c_bool - nir_scalar_is_undef.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_as_const_value = _libraries['FIXME_STUB'].nir_scalar_as_const_value - nir_scalar_as_const_value.restype = nir_const_value - nir_scalar_as_const_value.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_as_int = _libraries['FIXME_STUB'].nir_scalar_as_int - nir_scalar_as_int.restype = int64_t - nir_scalar_as_int.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_as_uint = _libraries['FIXME_STUB'].nir_scalar_as_uint - nir_scalar_as_uint.restype = uint64_t - nir_scalar_as_uint.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_as_bool = _libraries['FIXME_STUB'].nir_scalar_as_bool - nir_scalar_as_bool.restype = ctypes.c_bool - nir_scalar_as_bool.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_as_float = _libraries['FIXME_STUB'].nir_scalar_as_float - nir_scalar_as_float.restype = ctypes.c_double - nir_scalar_as_float.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_is_alu = _libraries['FIXME_STUB'].nir_scalar_is_alu - nir_scalar_is_alu.restype = ctypes.c_bool - nir_scalar_is_alu.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_alu_op = _libraries['FIXME_STUB'].nir_scalar_alu_op - nir_scalar_alu_op.restype = nir_op - nir_scalar_alu_op.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_is_intrinsic = _libraries['FIXME_STUB'].nir_scalar_is_intrinsic - nir_scalar_is_intrinsic.restype = ctypes.c_bool - nir_scalar_is_intrinsic.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_intrinsic_op = _libraries['FIXME_STUB'].nir_scalar_intrinsic_op - nir_scalar_intrinsic_op.restype = nir_intrinsic_op - nir_scalar_intrinsic_op.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_scalar_chase_alu_src = _libraries['FIXME_STUB'].nir_scalar_chase_alu_src - nir_scalar_chase_alu_src.restype = nir_scalar - nir_scalar_chase_alu_src.argtypes = [nir_scalar, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_scalar_chase_movs = _libraries['libtinymesa_cpu.so'].nir_scalar_chase_movs - nir_scalar_chase_movs.restype = nir_scalar - nir_scalar_chase_movs.argtypes = [nir_scalar] -except AttributeError: - pass -try: - nir_get_scalar = _libraries['FIXME_STUB'].nir_get_scalar - nir_get_scalar.restype = nir_scalar - nir_get_scalar.argtypes = [ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_scalar_resolved = _libraries['FIXME_STUB'].nir_scalar_resolved - nir_scalar_resolved.restype = nir_scalar - nir_scalar_resolved.argtypes = [ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_scalar_equal = _libraries['FIXME_STUB'].nir_scalar_equal - nir_scalar_equal.restype = ctypes.c_bool - nir_scalar_equal.argtypes = [nir_scalar, nir_scalar] -except AttributeError: - pass -try: - nir_alu_src_as_uint = _libraries['FIXME_STUB'].nir_alu_src_as_uint - nir_alu_src_as_uint.restype = uint64_t - nir_alu_src_as_uint.argtypes = [nir_alu_src] -except AttributeError: - pass -class struct_nir_binding(Structure): - pass - -struct_nir_binding._pack_ = 1 # source:False -struct_nir_binding._fields_ = [ - ('success', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), - ('var', ctypes.POINTER(struct_nir_variable)), - ('desc_set', ctypes.c_uint32), - ('binding', ctypes.c_uint32), - ('num_indices', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('indices', struct_nir_src * 4), - ('read_first_invocation', ctypes.c_bool), - ('PADDING_2', ctypes.c_ubyte * 7), -] - -nir_binding = struct_nir_binding -try: - nir_chase_binding = _libraries['libtinymesa_cpu.so'].nir_chase_binding - nir_chase_binding.restype = nir_binding - nir_chase_binding.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_get_binding_variable = _libraries['libtinymesa_cpu.so'].nir_get_binding_variable - nir_get_binding_variable.restype = ctypes.POINTER(struct_nir_variable) - nir_get_binding_variable.argtypes = [ctypes.POINTER(struct_nir_shader), nir_binding] -except AttributeError: - pass -nir_cf_node_type = c__EA_nir_cf_node_type -nir_cf_node_type__enumvalues = c__EA_nir_cf_node_type__enumvalues -nir_cf_node = struct_nir_cf_node +nir_instr_type = CEnum(ctypes.c_ubyte) +nir_instr_type_alu = nir_instr_type.define('nir_instr_type_alu', 0) +nir_instr_type_deref = nir_instr_type.define('nir_instr_type_deref', 1) +nir_instr_type_call = nir_instr_type.define('nir_instr_type_call', 2) +nir_instr_type_tex = nir_instr_type.define('nir_instr_type_tex', 3) +nir_instr_type_intrinsic = nir_instr_type.define('nir_instr_type_intrinsic', 4) +nir_instr_type_load_const = nir_instr_type.define('nir_instr_type_load_const', 5) +nir_instr_type_jump = nir_instr_type.define('nir_instr_type_jump', 6) +nir_instr_type_undef = nir_instr_type.define('nir_instr_type_undef', 7) +nir_instr_type_phi = nir_instr_type.define('nir_instr_type_phi', 8) +nir_instr_type_parallel_copy = nir_instr_type.define('nir_instr_type_parallel_copy', 9) + +class struct_nir_instr(Struct): pass +class struct_nir_block(Struct): pass nir_block = struct_nir_block -try: - nir_block_is_reachable = _libraries['FIXME_STUB'].nir_block_is_reachable - nir_block_is_reachable.restype = ctypes.c_bool - nir_block_is_reachable.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_first_instr = _libraries['FIXME_STUB'].nir_block_first_instr - nir_block_first_instr.restype = ctypes.POINTER(struct_nir_instr) - nir_block_first_instr.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_last_instr = _libraries['FIXME_STUB'].nir_block_last_instr - nir_block_last_instr.restype = ctypes.POINTER(struct_nir_instr) - nir_block_last_instr.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_ends_in_jump = _libraries['FIXME_STUB'].nir_block_ends_in_jump - nir_block_ends_in_jump.restype = ctypes.c_bool - nir_block_ends_in_jump.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_ends_in_return_or_halt = _libraries['FIXME_STUB'].nir_block_ends_in_return_or_halt - nir_block_ends_in_return_or_halt.restype = ctypes.c_bool - nir_block_ends_in_return_or_halt.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_ends_in_break = _libraries['FIXME_STUB'].nir_block_ends_in_break - nir_block_ends_in_break.restype = ctypes.c_bool - nir_block_ends_in_break.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_contains_work = _libraries['libtinymesa_cpu.so'].nir_block_contains_work - nir_block_contains_work.restype = ctypes.c_bool - nir_block_contains_work.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_first_phi_in_block = _libraries['FIXME_STUB'].nir_first_phi_in_block - nir_first_phi_in_block.restype = ctypes.POINTER(struct_nir_phi_instr) - nir_first_phi_in_block.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_next_phi = _libraries['FIXME_STUB'].nir_next_phi - nir_next_phi.restype = ctypes.POINTER(struct_nir_phi_instr) - nir_next_phi.argtypes = [ctypes.POINTER(struct_nir_phi_instr)] -except AttributeError: - pass -try: - nir_block_last_phi_instr = _libraries['FIXME_STUB'].nir_block_last_phi_instr - nir_block_last_phi_instr.restype = ctypes.POINTER(struct_nir_phi_instr) - nir_block_last_phi_instr.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -nir_selection_control = c__EA_nir_selection_control -nir_selection_control__enumvalues = c__EA_nir_selection_control__enumvalues -nir_if = struct_nir_if -class struct_nir_loop_terminator(Structure): - pass +class struct_nir_cf_node(Struct): pass +nir_cf_node = struct_nir_cf_node +nir_cf_node_type = CEnum(ctypes.c_uint32) +nir_cf_node_block = nir_cf_node_type.define('nir_cf_node_block', 0) +nir_cf_node_if = nir_cf_node_type.define('nir_cf_node_if', 1) +nir_cf_node_loop = nir_cf_node_type.define('nir_cf_node_loop', 2) +nir_cf_node_function = nir_cf_node_type.define('nir_cf_node_function', 3) -struct_nir_loop_terminator._pack_ = 1 # source:False -struct_nir_loop_terminator._fields_ = [ - ('nif', ctypes.POINTER(struct_nir_if)), - ('conditional_instr', ctypes.POINTER(struct_nir_instr)), - ('break_block', ctypes.POINTER(struct_nir_block)), - ('continue_from_block', ctypes.POINTER(struct_nir_block)), - ('continue_from_then', ctypes.c_bool), - ('induction_rhs', ctypes.c_bool), - ('exact_trip_count_unknown', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 5), - ('loop_terminator_link', struct_list_head), +nir_cf_node = struct_nir_cf_node +struct_nir_cf_node._fields_ = [ + ('node', struct_exec_node), + ('type', nir_cf_node_type), + ('parent', ctypes.POINTER(nir_cf_node)), ] - -nir_loop_terminator = struct_nir_loop_terminator -class struct_nir_loop_induction_variable(Structure): - pass - -struct_nir_loop_induction_variable._pack_ = 1 # source:False -struct_nir_loop_induction_variable._fields_ = [ - ('basis', ctypes.POINTER(struct_nir_def)), - ('def', ctypes.POINTER(struct_nir_def)), - ('init_src', ctypes.POINTER(struct_nir_src)), - ('update_src', ctypes.POINTER(struct_nir_alu_src)), +class struct_exec_list(Struct): pass +struct_exec_list._fields_ = [ + ('head_sentinel', struct_exec_node), + ('tail_sentinel', struct_exec_node), ] - -nir_loop_induction_variable = struct_nir_loop_induction_variable -class struct_nir_loop_info(Structure): - pass - -class struct_hash_table(Structure): - pass - -struct_nir_loop_info._pack_ = 1 # source:False -struct_nir_loop_info._fields_ = [ - ('instr_cost', ctypes.c_uint32), - ('has_soft_fp64', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('guessed_trip_count', ctypes.c_uint32), - ('max_trip_count', ctypes.c_uint32), - ('exact_trip_count_known', ctypes.c_bool), - ('force_unroll', ctypes.c_bool), - ('complex_loop', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 5), - ('limiting_terminator', ctypes.POINTER(struct_nir_loop_terminator)), - ('loop_terminator_list', struct_list_head), - ('induction_vars', ctypes.POINTER(struct_hash_table)), +nir_block = struct_nir_block +class struct_set(Struct): pass +class struct_set_entry(Struct): pass +struct_set_entry._fields_ = [ + ('hash', uint32_t), + ('key', ctypes.c_void_p), ] - -class struct_hash_entry(Structure): - pass - -struct_hash_table._pack_ = 1 # source:False -struct_hash_table._fields_ = [ - ('table', ctypes.POINTER(struct_hash_entry)), - ('key_hash_function', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(None))), - ('key_equals_function', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(None), ctypes.POINTER(None))), - ('deleted_key', ctypes.POINTER(None)), - ('size', ctypes.c_uint32), - ('rehash', ctypes.c_uint32), - ('size_magic', ctypes.c_uint64), - ('rehash_magic', ctypes.c_uint64), - ('max_entries', ctypes.c_uint32), - ('size_index', ctypes.c_uint32), - ('entries', ctypes.c_uint32), - ('deleted_entries', ctypes.c_uint32), +struct_set._fields_ = [ + ('mem_ctx', ctypes.c_void_p), + ('table', ctypes.POINTER(struct_set_entry)), + ('key_hash_function', ctypes.CFUNCTYPE(uint32_t, ctypes.c_void_p)), + ('key_equals_function', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_void_p, ctypes.c_void_p)), + ('size', uint32_t), + ('rehash', uint32_t), + ('size_magic', uint64_t), + ('rehash_magic', uint64_t), + ('max_entries', uint32_t), + ('size_index', uint32_t), + ('entries', uint32_t), + ('deleted_entries', uint32_t), ] - -struct_hash_entry._pack_ = 1 # source:False -struct_hash_entry._fields_ = [ - ('hash', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('key', ctypes.POINTER(None)), - ('data', ctypes.POINTER(None)), +struct_nir_block._fields_ = [ + ('cf_node', nir_cf_node), + ('instr_list', struct_exec_list), + ('index', ctypes.c_uint32), + ('divergent', ctypes.c_bool), + ('successors', (ctypes.POINTER(nir_block) * 2)), + ('predecessors', ctypes.POINTER(struct_set)), + ('imm_dom', ctypes.POINTER(nir_block)), + ('num_dom_children', ctypes.c_uint32), + ('dom_children', ctypes.POINTER(ctypes.POINTER(nir_block))), + ('dom_frontier', ctypes.POINTER(struct_set)), + ('dom_pre_index', uint32_t), + ('dom_post_index', uint32_t), + ('start_ip', uint32_t), + ('end_ip', uint32_t), + ('live_in', ctypes.POINTER(ctypes.c_uint32)), + ('live_out', ctypes.POINTER(ctypes.c_uint32)), ] - -nir_loop_info = struct_nir_loop_info - -# values for enumeration 'c__EA_nir_loop_control' -c__EA_nir_loop_control__enumvalues = { - 0: 'nir_loop_control_none', - 1: 'nir_loop_control_unroll', - 2: 'nir_loop_control_dont_unroll', -} -nir_loop_control_none = 0 -nir_loop_control_unroll = 1 -nir_loop_control_dont_unroll = 2 -c__EA_nir_loop_control = ctypes.c_uint32 # enum -nir_loop_control = c__EA_nir_loop_control -nir_loop_control__enumvalues = c__EA_nir_loop_control__enumvalues -class struct_nir_loop(Structure): - pass - -struct_nir_loop._pack_ = 1 # source:False -struct_nir_loop._fields_ = [ - ('cf_node', nir_cf_node), - ('body', struct_exec_list), - ('continue_list', struct_exec_list), - ('info', ctypes.POINTER(struct_nir_loop_info)), - ('control', nir_loop_control), - ('partially_unrolled', ctypes.c_bool), - ('divergent_continue', ctypes.c_bool), - ('divergent_break', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), +struct_nir_instr._fields_ = [ + ('node', struct_exec_node), + ('block', ctypes.POINTER(nir_block)), + ('type', nir_instr_type), + ('pass_flags', uint8_t), + ('has_debug_info', ctypes.c_bool), + ('index', uint32_t), ] +nir_instr = struct_nir_instr +class struct_nir_def(Struct): pass +class struct_list_head(Struct): pass +struct_list_head._fields_ = [ + ('prev', ctypes.POINTER(struct_list_head)), + ('next', ctypes.POINTER(struct_list_head)), +] +struct_nir_def._fields_ = [ + ('parent_instr', ctypes.POINTER(nir_instr)), + ('uses', struct_list_head), + ('index', ctypes.c_uint32), + ('num_components', uint8_t), + ('bit_size', uint8_t), + ('divergent', ctypes.c_bool), + ('loop_invariant', ctypes.c_bool), +] +nir_def = struct_nir_def +class struct_nir_src(Struct): pass +struct_nir_src._fields_ = [ + ('_parent', uintptr_t), + ('use_link', struct_list_head), + ('ssa', ctypes.POINTER(nir_def)), +] +nir_src = struct_nir_src +# bool nir_src_is_divergent(nir_src *src) +try: (nir_src_is_divergent:=dll.nir_src_is_divergent).restype, nir_src_is_divergent.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_src)] +except AttributeError: pass -nir_loop = struct_nir_loop -try: - nir_loop_is_divergent = _libraries['FIXME_STUB'].nir_loop_is_divergent - nir_loop_is_divergent.restype = ctypes.c_bool - nir_loop_is_divergent.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -nir_metadata = c__EA_nir_metadata -nir_metadata__enumvalues = c__EA_nir_metadata__enumvalues -nir_function_impl = struct_nir_function_impl -try: - nir_start_block = _libraries['FIXME_STUB'].nir_start_block - nir_start_block.restype = ctypes.POINTER(struct_nir_block) - nir_start_block.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_impl_last_block = _libraries['FIXME_STUB'].nir_impl_last_block - nir_impl_last_block.restype = ctypes.POINTER(struct_nir_block) - nir_impl_last_block.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_cf_node_next = _libraries['FIXME_STUB'].nir_cf_node_next - nir_cf_node_next.restype = ctypes.POINTER(struct_nir_cf_node) - nir_cf_node_next.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_prev = _libraries['FIXME_STUB'].nir_cf_node_prev - nir_cf_node_prev.restype = ctypes.POINTER(struct_nir_cf_node) - nir_cf_node_prev.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_is_first = _libraries['FIXME_STUB'].nir_cf_node_is_first - nir_cf_node_is_first.restype = ctypes.c_bool - nir_cf_node_is_first.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_is_last = _libraries['FIXME_STUB'].nir_cf_node_is_last - nir_cf_node_is_last.restype = ctypes.c_bool - nir_cf_node_is_last.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_as_block = _libraries['FIXME_STUB'].nir_cf_node_as_block - nir_cf_node_as_block.restype = ctypes.POINTER(struct_nir_block) - nir_cf_node_as_block.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_as_if = _libraries['FIXME_STUB'].nir_cf_node_as_if - nir_cf_node_as_if.restype = ctypes.POINTER(struct_nir_if) - nir_cf_node_as_if.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_as_loop = _libraries['FIXME_STUB'].nir_cf_node_as_loop - nir_cf_node_as_loop.restype = ctypes.POINTER(struct_nir_loop) - nir_cf_node_as_loop.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_as_function = _libraries['FIXME_STUB'].nir_cf_node_as_function - nir_cf_node_as_function.restype = ctypes.POINTER(struct_nir_function_impl) - nir_cf_node_as_function.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_if_first_then_block = _libraries['FIXME_STUB'].nir_if_first_then_block - nir_if_first_then_block.restype = ctypes.POINTER(struct_nir_block) - nir_if_first_then_block.argtypes = [ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_if_last_then_block = _libraries['FIXME_STUB'].nir_if_last_then_block - nir_if_last_then_block.restype = ctypes.POINTER(struct_nir_block) - nir_if_last_then_block.argtypes = [ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_if_first_else_block = _libraries['FIXME_STUB'].nir_if_first_else_block - nir_if_first_else_block.restype = ctypes.POINTER(struct_nir_block) - nir_if_first_else_block.argtypes = [ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_if_last_else_block = _libraries['FIXME_STUB'].nir_if_last_else_block - nir_if_last_else_block.restype = ctypes.POINTER(struct_nir_block) - nir_if_last_else_block.argtypes = [ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_loop_first_block = _libraries['FIXME_STUB'].nir_loop_first_block - nir_loop_first_block.restype = ctypes.POINTER(struct_nir_block) - nir_loop_first_block.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_loop_last_block = _libraries['FIXME_STUB'].nir_loop_last_block - nir_loop_last_block.restype = ctypes.POINTER(struct_nir_block) - nir_loop_last_block.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_loop_has_continue_construct = _libraries['FIXME_STUB'].nir_loop_has_continue_construct - nir_loop_has_continue_construct.restype = ctypes.c_bool - nir_loop_has_continue_construct.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_loop_first_continue_block = _libraries['FIXME_STUB'].nir_loop_first_continue_block - nir_loop_first_continue_block.restype = ctypes.POINTER(struct_nir_block) - nir_loop_first_continue_block.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_loop_last_continue_block = _libraries['FIXME_STUB'].nir_loop_last_continue_block - nir_loop_last_continue_block.restype = ctypes.POINTER(struct_nir_block) - nir_loop_last_continue_block.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_loop_continue_target = _libraries['FIXME_STUB'].nir_loop_continue_target - nir_loop_continue_target.restype = ctypes.POINTER(struct_nir_block) - nir_loop_continue_target.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_cf_list_is_empty_block = _libraries['FIXME_STUB'].nir_cf_list_is_empty_block - nir_cf_list_is_empty_block.restype = ctypes.c_bool - nir_cf_list_is_empty_block.argtypes = [ctypes.POINTER(struct_exec_list)] -except AttributeError: - pass -nir_parameter = struct_nir_parameter +class struct_nir_alu_src(Struct): pass +struct_nir_alu_src._fields_ = [ + ('src', nir_src), + ('swizzle', (uint8_t * 16)), +] +nir_alu_src = struct_nir_alu_src +nir_alu_type = CEnum(ctypes.c_ubyte) +nir_type_invalid = nir_alu_type.define('nir_type_invalid', 0) +nir_type_int = nir_alu_type.define('nir_type_int', 2) +nir_type_uint = nir_alu_type.define('nir_type_uint', 4) +nir_type_bool = nir_alu_type.define('nir_type_bool', 6) +nir_type_float = nir_alu_type.define('nir_type_float', 128) +nir_type_bool1 = nir_alu_type.define('nir_type_bool1', 7) +nir_type_bool8 = nir_alu_type.define('nir_type_bool8', 14) +nir_type_bool16 = nir_alu_type.define('nir_type_bool16', 22) +nir_type_bool32 = nir_alu_type.define('nir_type_bool32', 38) +nir_type_int1 = nir_alu_type.define('nir_type_int1', 3) +nir_type_int8 = nir_alu_type.define('nir_type_int8', 10) +nir_type_int16 = nir_alu_type.define('nir_type_int16', 18) +nir_type_int32 = nir_alu_type.define('nir_type_int32', 34) +nir_type_int64 = nir_alu_type.define('nir_type_int64', 66) +nir_type_uint1 = nir_alu_type.define('nir_type_uint1', 5) +nir_type_uint8 = nir_alu_type.define('nir_type_uint8', 12) +nir_type_uint16 = nir_alu_type.define('nir_type_uint16', 20) +nir_type_uint32 = nir_alu_type.define('nir_type_uint32', 36) +nir_type_uint64 = nir_alu_type.define('nir_type_uint64', 68) +nir_type_float16 = nir_alu_type.define('nir_type_float16', 144) +nir_type_float32 = nir_alu_type.define('nir_type_float32', 160) +nir_type_float64 = nir_alu_type.define('nir_type_float64', 192) + +# nir_alu_type nir_get_nir_type_for_glsl_base_type(enum glsl_base_type base_type) +try: (nir_get_nir_type_for_glsl_base_type:=dll.nir_get_nir_type_for_glsl_base_type).restype, nir_get_nir_type_for_glsl_base_type.argtypes = nir_alu_type, [enum_glsl_base_type] +except AttributeError: pass + +# enum glsl_base_type nir_get_glsl_base_type_for_nir_type(nir_alu_type base_type) +try: (nir_get_glsl_base_type_for_nir_type:=dll.nir_get_glsl_base_type_for_nir_type).restype, nir_get_glsl_base_type_for_nir_type.argtypes = enum_glsl_base_type, [nir_alu_type] +except AttributeError: pass + +nir_op = CEnum(ctypes.c_uint32) +nir_op_alignbyte_amd = nir_op.define('nir_op_alignbyte_amd', 0) +nir_op_amul = nir_op.define('nir_op_amul', 1) +nir_op_andg_ir3 = nir_op.define('nir_op_andg_ir3', 2) +nir_op_b16all_fequal16 = nir_op.define('nir_op_b16all_fequal16', 3) +nir_op_b16all_fequal2 = nir_op.define('nir_op_b16all_fequal2', 4) +nir_op_b16all_fequal3 = nir_op.define('nir_op_b16all_fequal3', 5) +nir_op_b16all_fequal4 = nir_op.define('nir_op_b16all_fequal4', 6) +nir_op_b16all_fequal5 = nir_op.define('nir_op_b16all_fequal5', 7) +nir_op_b16all_fequal8 = nir_op.define('nir_op_b16all_fequal8', 8) +nir_op_b16all_iequal16 = nir_op.define('nir_op_b16all_iequal16', 9) +nir_op_b16all_iequal2 = nir_op.define('nir_op_b16all_iequal2', 10) +nir_op_b16all_iequal3 = nir_op.define('nir_op_b16all_iequal3', 11) +nir_op_b16all_iequal4 = nir_op.define('nir_op_b16all_iequal4', 12) +nir_op_b16all_iequal5 = nir_op.define('nir_op_b16all_iequal5', 13) +nir_op_b16all_iequal8 = nir_op.define('nir_op_b16all_iequal8', 14) +nir_op_b16any_fnequal16 = nir_op.define('nir_op_b16any_fnequal16', 15) +nir_op_b16any_fnequal2 = nir_op.define('nir_op_b16any_fnequal2', 16) +nir_op_b16any_fnequal3 = nir_op.define('nir_op_b16any_fnequal3', 17) +nir_op_b16any_fnequal4 = nir_op.define('nir_op_b16any_fnequal4', 18) +nir_op_b16any_fnequal5 = nir_op.define('nir_op_b16any_fnequal5', 19) +nir_op_b16any_fnequal8 = nir_op.define('nir_op_b16any_fnequal8', 20) +nir_op_b16any_inequal16 = nir_op.define('nir_op_b16any_inequal16', 21) +nir_op_b16any_inequal2 = nir_op.define('nir_op_b16any_inequal2', 22) +nir_op_b16any_inequal3 = nir_op.define('nir_op_b16any_inequal3', 23) +nir_op_b16any_inequal4 = nir_op.define('nir_op_b16any_inequal4', 24) +nir_op_b16any_inequal5 = nir_op.define('nir_op_b16any_inequal5', 25) +nir_op_b16any_inequal8 = nir_op.define('nir_op_b16any_inequal8', 26) +nir_op_b16csel = nir_op.define('nir_op_b16csel', 27) +nir_op_b2b1 = nir_op.define('nir_op_b2b1', 28) +nir_op_b2b16 = nir_op.define('nir_op_b2b16', 29) +nir_op_b2b32 = nir_op.define('nir_op_b2b32', 30) +nir_op_b2b8 = nir_op.define('nir_op_b2b8', 31) +nir_op_b2f16 = nir_op.define('nir_op_b2f16', 32) +nir_op_b2f32 = nir_op.define('nir_op_b2f32', 33) +nir_op_b2f64 = nir_op.define('nir_op_b2f64', 34) +nir_op_b2i1 = nir_op.define('nir_op_b2i1', 35) +nir_op_b2i16 = nir_op.define('nir_op_b2i16', 36) +nir_op_b2i32 = nir_op.define('nir_op_b2i32', 37) +nir_op_b2i64 = nir_op.define('nir_op_b2i64', 38) +nir_op_b2i8 = nir_op.define('nir_op_b2i8', 39) +nir_op_b32all_fequal16 = nir_op.define('nir_op_b32all_fequal16', 40) +nir_op_b32all_fequal2 = nir_op.define('nir_op_b32all_fequal2', 41) +nir_op_b32all_fequal3 = nir_op.define('nir_op_b32all_fequal3', 42) +nir_op_b32all_fequal4 = nir_op.define('nir_op_b32all_fequal4', 43) +nir_op_b32all_fequal5 = nir_op.define('nir_op_b32all_fequal5', 44) +nir_op_b32all_fequal8 = nir_op.define('nir_op_b32all_fequal8', 45) +nir_op_b32all_iequal16 = nir_op.define('nir_op_b32all_iequal16', 46) +nir_op_b32all_iequal2 = nir_op.define('nir_op_b32all_iequal2', 47) +nir_op_b32all_iequal3 = nir_op.define('nir_op_b32all_iequal3', 48) +nir_op_b32all_iequal4 = nir_op.define('nir_op_b32all_iequal4', 49) +nir_op_b32all_iequal5 = nir_op.define('nir_op_b32all_iequal5', 50) +nir_op_b32all_iequal8 = nir_op.define('nir_op_b32all_iequal8', 51) +nir_op_b32any_fnequal16 = nir_op.define('nir_op_b32any_fnequal16', 52) +nir_op_b32any_fnequal2 = nir_op.define('nir_op_b32any_fnequal2', 53) +nir_op_b32any_fnequal3 = nir_op.define('nir_op_b32any_fnequal3', 54) +nir_op_b32any_fnequal4 = nir_op.define('nir_op_b32any_fnequal4', 55) +nir_op_b32any_fnequal5 = nir_op.define('nir_op_b32any_fnequal5', 56) +nir_op_b32any_fnequal8 = nir_op.define('nir_op_b32any_fnequal8', 57) +nir_op_b32any_inequal16 = nir_op.define('nir_op_b32any_inequal16', 58) +nir_op_b32any_inequal2 = nir_op.define('nir_op_b32any_inequal2', 59) +nir_op_b32any_inequal3 = nir_op.define('nir_op_b32any_inequal3', 60) +nir_op_b32any_inequal4 = nir_op.define('nir_op_b32any_inequal4', 61) +nir_op_b32any_inequal5 = nir_op.define('nir_op_b32any_inequal5', 62) +nir_op_b32any_inequal8 = nir_op.define('nir_op_b32any_inequal8', 63) +nir_op_b32csel = nir_op.define('nir_op_b32csel', 64) +nir_op_b32fcsel_mdg = nir_op.define('nir_op_b32fcsel_mdg', 65) +nir_op_b8all_fequal16 = nir_op.define('nir_op_b8all_fequal16', 66) +nir_op_b8all_fequal2 = nir_op.define('nir_op_b8all_fequal2', 67) +nir_op_b8all_fequal3 = nir_op.define('nir_op_b8all_fequal3', 68) +nir_op_b8all_fequal4 = nir_op.define('nir_op_b8all_fequal4', 69) +nir_op_b8all_fequal5 = nir_op.define('nir_op_b8all_fequal5', 70) +nir_op_b8all_fequal8 = nir_op.define('nir_op_b8all_fequal8', 71) +nir_op_b8all_iequal16 = nir_op.define('nir_op_b8all_iequal16', 72) +nir_op_b8all_iequal2 = nir_op.define('nir_op_b8all_iequal2', 73) +nir_op_b8all_iequal3 = nir_op.define('nir_op_b8all_iequal3', 74) +nir_op_b8all_iequal4 = nir_op.define('nir_op_b8all_iequal4', 75) +nir_op_b8all_iequal5 = nir_op.define('nir_op_b8all_iequal5', 76) +nir_op_b8all_iequal8 = nir_op.define('nir_op_b8all_iequal8', 77) +nir_op_b8any_fnequal16 = nir_op.define('nir_op_b8any_fnequal16', 78) +nir_op_b8any_fnequal2 = nir_op.define('nir_op_b8any_fnequal2', 79) +nir_op_b8any_fnequal3 = nir_op.define('nir_op_b8any_fnequal3', 80) +nir_op_b8any_fnequal4 = nir_op.define('nir_op_b8any_fnequal4', 81) +nir_op_b8any_fnequal5 = nir_op.define('nir_op_b8any_fnequal5', 82) +nir_op_b8any_fnequal8 = nir_op.define('nir_op_b8any_fnequal8', 83) +nir_op_b8any_inequal16 = nir_op.define('nir_op_b8any_inequal16', 84) +nir_op_b8any_inequal2 = nir_op.define('nir_op_b8any_inequal2', 85) +nir_op_b8any_inequal3 = nir_op.define('nir_op_b8any_inequal3', 86) +nir_op_b8any_inequal4 = nir_op.define('nir_op_b8any_inequal4', 87) +nir_op_b8any_inequal5 = nir_op.define('nir_op_b8any_inequal5', 88) +nir_op_b8any_inequal8 = nir_op.define('nir_op_b8any_inequal8', 89) +nir_op_b8csel = nir_op.define('nir_op_b8csel', 90) +nir_op_ball_fequal16 = nir_op.define('nir_op_ball_fequal16', 91) +nir_op_ball_fequal2 = nir_op.define('nir_op_ball_fequal2', 92) +nir_op_ball_fequal3 = nir_op.define('nir_op_ball_fequal3', 93) +nir_op_ball_fequal4 = nir_op.define('nir_op_ball_fequal4', 94) +nir_op_ball_fequal5 = nir_op.define('nir_op_ball_fequal5', 95) +nir_op_ball_fequal8 = nir_op.define('nir_op_ball_fequal8', 96) +nir_op_ball_iequal16 = nir_op.define('nir_op_ball_iequal16', 97) +nir_op_ball_iequal2 = nir_op.define('nir_op_ball_iequal2', 98) +nir_op_ball_iequal3 = nir_op.define('nir_op_ball_iequal3', 99) +nir_op_ball_iequal4 = nir_op.define('nir_op_ball_iequal4', 100) +nir_op_ball_iequal5 = nir_op.define('nir_op_ball_iequal5', 101) +nir_op_ball_iequal8 = nir_op.define('nir_op_ball_iequal8', 102) +nir_op_bany_fnequal16 = nir_op.define('nir_op_bany_fnequal16', 103) +nir_op_bany_fnequal2 = nir_op.define('nir_op_bany_fnequal2', 104) +nir_op_bany_fnequal3 = nir_op.define('nir_op_bany_fnequal3', 105) +nir_op_bany_fnequal4 = nir_op.define('nir_op_bany_fnequal4', 106) +nir_op_bany_fnequal5 = nir_op.define('nir_op_bany_fnequal5', 107) +nir_op_bany_fnequal8 = nir_op.define('nir_op_bany_fnequal8', 108) +nir_op_bany_inequal16 = nir_op.define('nir_op_bany_inequal16', 109) +nir_op_bany_inequal2 = nir_op.define('nir_op_bany_inequal2', 110) +nir_op_bany_inequal3 = nir_op.define('nir_op_bany_inequal3', 111) +nir_op_bany_inequal4 = nir_op.define('nir_op_bany_inequal4', 112) +nir_op_bany_inequal5 = nir_op.define('nir_op_bany_inequal5', 113) +nir_op_bany_inequal8 = nir_op.define('nir_op_bany_inequal8', 114) +nir_op_bcsel = nir_op.define('nir_op_bcsel', 115) +nir_op_bf2f = nir_op.define('nir_op_bf2f', 116) +nir_op_bfdot16 = nir_op.define('nir_op_bfdot16', 117) +nir_op_bfdot2 = nir_op.define('nir_op_bfdot2', 118) +nir_op_bfdot2_bfadd = nir_op.define('nir_op_bfdot2_bfadd', 119) +nir_op_bfdot3 = nir_op.define('nir_op_bfdot3', 120) +nir_op_bfdot4 = nir_op.define('nir_op_bfdot4', 121) +nir_op_bfdot5 = nir_op.define('nir_op_bfdot5', 122) +nir_op_bfdot8 = nir_op.define('nir_op_bfdot8', 123) +nir_op_bffma = nir_op.define('nir_op_bffma', 124) +nir_op_bfi = nir_op.define('nir_op_bfi', 125) +nir_op_bfm = nir_op.define('nir_op_bfm', 126) +nir_op_bfmul = nir_op.define('nir_op_bfmul', 127) +nir_op_bit_count = nir_op.define('nir_op_bit_count', 128) +nir_op_bitfield_insert = nir_op.define('nir_op_bitfield_insert', 129) +nir_op_bitfield_reverse = nir_op.define('nir_op_bitfield_reverse', 130) +nir_op_bitfield_select = nir_op.define('nir_op_bitfield_select', 131) +nir_op_bitnz = nir_op.define('nir_op_bitnz', 132) +nir_op_bitnz16 = nir_op.define('nir_op_bitnz16', 133) +nir_op_bitnz32 = nir_op.define('nir_op_bitnz32', 134) +nir_op_bitnz8 = nir_op.define('nir_op_bitnz8', 135) +nir_op_bitz = nir_op.define('nir_op_bitz', 136) +nir_op_bitz16 = nir_op.define('nir_op_bitz16', 137) +nir_op_bitz32 = nir_op.define('nir_op_bitz32', 138) +nir_op_bitz8 = nir_op.define('nir_op_bitz8', 139) +nir_op_bounds_agx = nir_op.define('nir_op_bounds_agx', 140) +nir_op_byte_perm_amd = nir_op.define('nir_op_byte_perm_amd', 141) +nir_op_cube_amd = nir_op.define('nir_op_cube_amd', 142) +nir_op_e4m3fn2f = nir_op.define('nir_op_e4m3fn2f', 143) +nir_op_e5m22f = nir_op.define('nir_op_e5m22f', 144) +nir_op_extr_agx = nir_op.define('nir_op_extr_agx', 145) +nir_op_extract_i16 = nir_op.define('nir_op_extract_i16', 146) +nir_op_extract_i8 = nir_op.define('nir_op_extract_i8', 147) +nir_op_extract_u16 = nir_op.define('nir_op_extract_u16', 148) +nir_op_extract_u8 = nir_op.define('nir_op_extract_u8', 149) +nir_op_f2bf = nir_op.define('nir_op_f2bf', 150) +nir_op_f2e4m3fn = nir_op.define('nir_op_f2e4m3fn', 151) +nir_op_f2e4m3fn_sat = nir_op.define('nir_op_f2e4m3fn_sat', 152) +nir_op_f2e4m3fn_satfn = nir_op.define('nir_op_f2e4m3fn_satfn', 153) +nir_op_f2e5m2 = nir_op.define('nir_op_f2e5m2', 154) +nir_op_f2e5m2_sat = nir_op.define('nir_op_f2e5m2_sat', 155) +nir_op_f2f16 = nir_op.define('nir_op_f2f16', 156) +nir_op_f2f16_rtne = nir_op.define('nir_op_f2f16_rtne', 157) +nir_op_f2f16_rtz = nir_op.define('nir_op_f2f16_rtz', 158) +nir_op_f2f32 = nir_op.define('nir_op_f2f32', 159) +nir_op_f2f64 = nir_op.define('nir_op_f2f64', 160) +nir_op_f2fmp = nir_op.define('nir_op_f2fmp', 161) +nir_op_f2i1 = nir_op.define('nir_op_f2i1', 162) +nir_op_f2i16 = nir_op.define('nir_op_f2i16', 163) +nir_op_f2i32 = nir_op.define('nir_op_f2i32', 164) +nir_op_f2i64 = nir_op.define('nir_op_f2i64', 165) +nir_op_f2i8 = nir_op.define('nir_op_f2i8', 166) +nir_op_f2imp = nir_op.define('nir_op_f2imp', 167) +nir_op_f2snorm_16_v3d = nir_op.define('nir_op_f2snorm_16_v3d', 168) +nir_op_f2u1 = nir_op.define('nir_op_f2u1', 169) +nir_op_f2u16 = nir_op.define('nir_op_f2u16', 170) +nir_op_f2u32 = nir_op.define('nir_op_f2u32', 171) +nir_op_f2u64 = nir_op.define('nir_op_f2u64', 172) +nir_op_f2u8 = nir_op.define('nir_op_f2u8', 173) +nir_op_f2ump = nir_op.define('nir_op_f2ump', 174) +nir_op_f2unorm_16_v3d = nir_op.define('nir_op_f2unorm_16_v3d', 175) +nir_op_fabs = nir_op.define('nir_op_fabs', 176) +nir_op_fadd = nir_op.define('nir_op_fadd', 177) +nir_op_fall_equal16 = nir_op.define('nir_op_fall_equal16', 178) +nir_op_fall_equal2 = nir_op.define('nir_op_fall_equal2', 179) +nir_op_fall_equal3 = nir_op.define('nir_op_fall_equal3', 180) +nir_op_fall_equal4 = nir_op.define('nir_op_fall_equal4', 181) +nir_op_fall_equal5 = nir_op.define('nir_op_fall_equal5', 182) +nir_op_fall_equal8 = nir_op.define('nir_op_fall_equal8', 183) +nir_op_fany_nequal16 = nir_op.define('nir_op_fany_nequal16', 184) +nir_op_fany_nequal2 = nir_op.define('nir_op_fany_nequal2', 185) +nir_op_fany_nequal3 = nir_op.define('nir_op_fany_nequal3', 186) +nir_op_fany_nequal4 = nir_op.define('nir_op_fany_nequal4', 187) +nir_op_fany_nequal5 = nir_op.define('nir_op_fany_nequal5', 188) +nir_op_fany_nequal8 = nir_op.define('nir_op_fany_nequal8', 189) +nir_op_fceil = nir_op.define('nir_op_fceil', 190) +nir_op_fclamp_pos = nir_op.define('nir_op_fclamp_pos', 191) +nir_op_fcos = nir_op.define('nir_op_fcos', 192) +nir_op_fcos_amd = nir_op.define('nir_op_fcos_amd', 193) +nir_op_fcos_mdg = nir_op.define('nir_op_fcos_mdg', 194) +nir_op_fcsel = nir_op.define('nir_op_fcsel', 195) +nir_op_fcsel_ge = nir_op.define('nir_op_fcsel_ge', 196) +nir_op_fcsel_gt = nir_op.define('nir_op_fcsel_gt', 197) +nir_op_fdiv = nir_op.define('nir_op_fdiv', 198) +nir_op_fdot16 = nir_op.define('nir_op_fdot16', 199) +nir_op_fdot16_replicated = nir_op.define('nir_op_fdot16_replicated', 200) +nir_op_fdot2 = nir_op.define('nir_op_fdot2', 201) +nir_op_fdot2_replicated = nir_op.define('nir_op_fdot2_replicated', 202) +nir_op_fdot3 = nir_op.define('nir_op_fdot3', 203) +nir_op_fdot3_replicated = nir_op.define('nir_op_fdot3_replicated', 204) +nir_op_fdot4 = nir_op.define('nir_op_fdot4', 205) +nir_op_fdot4_replicated = nir_op.define('nir_op_fdot4_replicated', 206) +nir_op_fdot5 = nir_op.define('nir_op_fdot5', 207) +nir_op_fdot5_replicated = nir_op.define('nir_op_fdot5_replicated', 208) +nir_op_fdot8 = nir_op.define('nir_op_fdot8', 209) +nir_op_fdot8_replicated = nir_op.define('nir_op_fdot8_replicated', 210) +nir_op_fdph = nir_op.define('nir_op_fdph', 211) +nir_op_fdph_replicated = nir_op.define('nir_op_fdph_replicated', 212) +nir_op_feq = nir_op.define('nir_op_feq', 213) +nir_op_feq16 = nir_op.define('nir_op_feq16', 214) +nir_op_feq32 = nir_op.define('nir_op_feq32', 215) +nir_op_feq8 = nir_op.define('nir_op_feq8', 216) +nir_op_fequ = nir_op.define('nir_op_fequ', 217) +nir_op_fequ16 = nir_op.define('nir_op_fequ16', 218) +nir_op_fequ32 = nir_op.define('nir_op_fequ32', 219) +nir_op_fequ8 = nir_op.define('nir_op_fequ8', 220) +nir_op_fexp2 = nir_op.define('nir_op_fexp2', 221) +nir_op_ffloor = nir_op.define('nir_op_ffloor', 222) +nir_op_ffma = nir_op.define('nir_op_ffma', 223) +nir_op_ffmaz = nir_op.define('nir_op_ffmaz', 224) +nir_op_ffract = nir_op.define('nir_op_ffract', 225) +nir_op_fge = nir_op.define('nir_op_fge', 226) +nir_op_fge16 = nir_op.define('nir_op_fge16', 227) +nir_op_fge32 = nir_op.define('nir_op_fge32', 228) +nir_op_fge8 = nir_op.define('nir_op_fge8', 229) +nir_op_fgeu = nir_op.define('nir_op_fgeu', 230) +nir_op_fgeu16 = nir_op.define('nir_op_fgeu16', 231) +nir_op_fgeu32 = nir_op.define('nir_op_fgeu32', 232) +nir_op_fgeu8 = nir_op.define('nir_op_fgeu8', 233) +nir_op_find_lsb = nir_op.define('nir_op_find_lsb', 234) +nir_op_fisfinite = nir_op.define('nir_op_fisfinite', 235) +nir_op_fisfinite32 = nir_op.define('nir_op_fisfinite32', 236) +nir_op_fisnormal = nir_op.define('nir_op_fisnormal', 237) +nir_op_flog2 = nir_op.define('nir_op_flog2', 238) +nir_op_flrp = nir_op.define('nir_op_flrp', 239) +nir_op_flt = nir_op.define('nir_op_flt', 240) +nir_op_flt16 = nir_op.define('nir_op_flt16', 241) +nir_op_flt32 = nir_op.define('nir_op_flt32', 242) +nir_op_flt8 = nir_op.define('nir_op_flt8', 243) +nir_op_fltu = nir_op.define('nir_op_fltu', 244) +nir_op_fltu16 = nir_op.define('nir_op_fltu16', 245) +nir_op_fltu32 = nir_op.define('nir_op_fltu32', 246) +nir_op_fltu8 = nir_op.define('nir_op_fltu8', 247) +nir_op_fmax = nir_op.define('nir_op_fmax', 248) +nir_op_fmax_agx = nir_op.define('nir_op_fmax_agx', 249) +nir_op_fmin = nir_op.define('nir_op_fmin', 250) +nir_op_fmin_agx = nir_op.define('nir_op_fmin_agx', 251) +nir_op_fmod = nir_op.define('nir_op_fmod', 252) +nir_op_fmul = nir_op.define('nir_op_fmul', 253) +nir_op_fmulz = nir_op.define('nir_op_fmulz', 254) +nir_op_fneg = nir_op.define('nir_op_fneg', 255) +nir_op_fneo = nir_op.define('nir_op_fneo', 256) +nir_op_fneo16 = nir_op.define('nir_op_fneo16', 257) +nir_op_fneo32 = nir_op.define('nir_op_fneo32', 258) +nir_op_fneo8 = nir_op.define('nir_op_fneo8', 259) +nir_op_fneu = nir_op.define('nir_op_fneu', 260) +nir_op_fneu16 = nir_op.define('nir_op_fneu16', 261) +nir_op_fneu32 = nir_op.define('nir_op_fneu32', 262) +nir_op_fneu8 = nir_op.define('nir_op_fneu8', 263) +nir_op_ford = nir_op.define('nir_op_ford', 264) +nir_op_ford16 = nir_op.define('nir_op_ford16', 265) +nir_op_ford32 = nir_op.define('nir_op_ford32', 266) +nir_op_ford8 = nir_op.define('nir_op_ford8', 267) +nir_op_fpow = nir_op.define('nir_op_fpow', 268) +nir_op_fquantize2f16 = nir_op.define('nir_op_fquantize2f16', 269) +nir_op_frcp = nir_op.define('nir_op_frcp', 270) +nir_op_frem = nir_op.define('nir_op_frem', 271) +nir_op_frexp_exp = nir_op.define('nir_op_frexp_exp', 272) +nir_op_frexp_sig = nir_op.define('nir_op_frexp_sig', 273) +nir_op_fround_even = nir_op.define('nir_op_fround_even', 274) +nir_op_frsq = nir_op.define('nir_op_frsq', 275) +nir_op_fsat = nir_op.define('nir_op_fsat', 276) +nir_op_fsat_signed = nir_op.define('nir_op_fsat_signed', 277) +nir_op_fsign = nir_op.define('nir_op_fsign', 278) +nir_op_fsin = nir_op.define('nir_op_fsin', 279) +nir_op_fsin_agx = nir_op.define('nir_op_fsin_agx', 280) +nir_op_fsin_amd = nir_op.define('nir_op_fsin_amd', 281) +nir_op_fsin_mdg = nir_op.define('nir_op_fsin_mdg', 282) +nir_op_fsqrt = nir_op.define('nir_op_fsqrt', 283) +nir_op_fsub = nir_op.define('nir_op_fsub', 284) +nir_op_fsum2 = nir_op.define('nir_op_fsum2', 285) +nir_op_fsum3 = nir_op.define('nir_op_fsum3', 286) +nir_op_fsum4 = nir_op.define('nir_op_fsum4', 287) +nir_op_ftrunc = nir_op.define('nir_op_ftrunc', 288) +nir_op_funord = nir_op.define('nir_op_funord', 289) +nir_op_funord16 = nir_op.define('nir_op_funord16', 290) +nir_op_funord32 = nir_op.define('nir_op_funord32', 291) +nir_op_funord8 = nir_op.define('nir_op_funord8', 292) +nir_op_i2f16 = nir_op.define('nir_op_i2f16', 293) +nir_op_i2f32 = nir_op.define('nir_op_i2f32', 294) +nir_op_i2f64 = nir_op.define('nir_op_i2f64', 295) +nir_op_i2fmp = nir_op.define('nir_op_i2fmp', 296) +nir_op_i2i1 = nir_op.define('nir_op_i2i1', 297) +nir_op_i2i16 = nir_op.define('nir_op_i2i16', 298) +nir_op_i2i32 = nir_op.define('nir_op_i2i32', 299) +nir_op_i2i64 = nir_op.define('nir_op_i2i64', 300) +nir_op_i2i8 = nir_op.define('nir_op_i2i8', 301) +nir_op_i2imp = nir_op.define('nir_op_i2imp', 302) +nir_op_i32csel_ge = nir_op.define('nir_op_i32csel_ge', 303) +nir_op_i32csel_gt = nir_op.define('nir_op_i32csel_gt', 304) +nir_op_iabs = nir_op.define('nir_op_iabs', 305) +nir_op_iadd = nir_op.define('nir_op_iadd', 306) +nir_op_iadd3 = nir_op.define('nir_op_iadd3', 307) +nir_op_iadd_sat = nir_op.define('nir_op_iadd_sat', 308) +nir_op_iand = nir_op.define('nir_op_iand', 309) +nir_op_ibfe = nir_op.define('nir_op_ibfe', 310) +nir_op_ibitfield_extract = nir_op.define('nir_op_ibitfield_extract', 311) +nir_op_icsel_eqz = nir_op.define('nir_op_icsel_eqz', 312) +nir_op_idiv = nir_op.define('nir_op_idiv', 313) +nir_op_ieq = nir_op.define('nir_op_ieq', 314) +nir_op_ieq16 = nir_op.define('nir_op_ieq16', 315) +nir_op_ieq32 = nir_op.define('nir_op_ieq32', 316) +nir_op_ieq8 = nir_op.define('nir_op_ieq8', 317) +nir_op_ifind_msb = nir_op.define('nir_op_ifind_msb', 318) +nir_op_ifind_msb_rev = nir_op.define('nir_op_ifind_msb_rev', 319) +nir_op_ige = nir_op.define('nir_op_ige', 320) +nir_op_ige16 = nir_op.define('nir_op_ige16', 321) +nir_op_ige32 = nir_op.define('nir_op_ige32', 322) +nir_op_ige8 = nir_op.define('nir_op_ige8', 323) +nir_op_ihadd = nir_op.define('nir_op_ihadd', 324) +nir_op_ilea_agx = nir_op.define('nir_op_ilea_agx', 325) +nir_op_ilt = nir_op.define('nir_op_ilt', 326) +nir_op_ilt16 = nir_op.define('nir_op_ilt16', 327) +nir_op_ilt32 = nir_op.define('nir_op_ilt32', 328) +nir_op_ilt8 = nir_op.define('nir_op_ilt8', 329) +nir_op_imad = nir_op.define('nir_op_imad', 330) +nir_op_imad24_ir3 = nir_op.define('nir_op_imad24_ir3', 331) +nir_op_imadsh_mix16 = nir_op.define('nir_op_imadsh_mix16', 332) +nir_op_imadshl_agx = nir_op.define('nir_op_imadshl_agx', 333) +nir_op_imax = nir_op.define('nir_op_imax', 334) +nir_op_imin = nir_op.define('nir_op_imin', 335) +nir_op_imod = nir_op.define('nir_op_imod', 336) +nir_op_imsubshl_agx = nir_op.define('nir_op_imsubshl_agx', 337) +nir_op_imul = nir_op.define('nir_op_imul', 338) +nir_op_imul24 = nir_op.define('nir_op_imul24', 339) +nir_op_imul24_relaxed = nir_op.define('nir_op_imul24_relaxed', 340) +nir_op_imul_2x32_64 = nir_op.define('nir_op_imul_2x32_64', 341) +nir_op_imul_32x16 = nir_op.define('nir_op_imul_32x16', 342) +nir_op_imul_high = nir_op.define('nir_op_imul_high', 343) +nir_op_ine = nir_op.define('nir_op_ine', 344) +nir_op_ine16 = nir_op.define('nir_op_ine16', 345) +nir_op_ine32 = nir_op.define('nir_op_ine32', 346) +nir_op_ine8 = nir_op.define('nir_op_ine8', 347) +nir_op_ineg = nir_op.define('nir_op_ineg', 348) +nir_op_inot = nir_op.define('nir_op_inot', 349) +nir_op_insert_u16 = nir_op.define('nir_op_insert_u16', 350) +nir_op_insert_u8 = nir_op.define('nir_op_insert_u8', 351) +nir_op_interleave_agx = nir_op.define('nir_op_interleave_agx', 352) +nir_op_ior = nir_op.define('nir_op_ior', 353) +nir_op_irem = nir_op.define('nir_op_irem', 354) +nir_op_irhadd = nir_op.define('nir_op_irhadd', 355) +nir_op_ishl = nir_op.define('nir_op_ishl', 356) +nir_op_ishr = nir_op.define('nir_op_ishr', 357) +nir_op_isign = nir_op.define('nir_op_isign', 358) +nir_op_isub = nir_op.define('nir_op_isub', 359) +nir_op_isub_sat = nir_op.define('nir_op_isub_sat', 360) +nir_op_ixor = nir_op.define('nir_op_ixor', 361) +nir_op_ldexp = nir_op.define('nir_op_ldexp', 362) +nir_op_ldexp16_pan = nir_op.define('nir_op_ldexp16_pan', 363) +nir_op_lea_nv = nir_op.define('nir_op_lea_nv', 364) +nir_op_mov = nir_op.define('nir_op_mov', 365) +nir_op_mqsad_4x8 = nir_op.define('nir_op_mqsad_4x8', 366) +nir_op_msad_4x8 = nir_op.define('nir_op_msad_4x8', 367) +nir_op_pack_2x16_to_snorm_2x8_v3d = nir_op.define('nir_op_pack_2x16_to_snorm_2x8_v3d', 368) +nir_op_pack_2x16_to_unorm_10_2_v3d = nir_op.define('nir_op_pack_2x16_to_unorm_10_2_v3d', 369) +nir_op_pack_2x16_to_unorm_2x10_v3d = nir_op.define('nir_op_pack_2x16_to_unorm_2x10_v3d', 370) +nir_op_pack_2x16_to_unorm_2x8_v3d = nir_op.define('nir_op_pack_2x16_to_unorm_2x8_v3d', 371) +nir_op_pack_2x32_to_2x16_v3d = nir_op.define('nir_op_pack_2x32_to_2x16_v3d', 372) +nir_op_pack_32_2x16 = nir_op.define('nir_op_pack_32_2x16', 373) +nir_op_pack_32_2x16_split = nir_op.define('nir_op_pack_32_2x16_split', 374) +nir_op_pack_32_4x8 = nir_op.define('nir_op_pack_32_4x8', 375) +nir_op_pack_32_4x8_split = nir_op.define('nir_op_pack_32_4x8_split', 376) +nir_op_pack_32_to_r11g11b10_v3d = nir_op.define('nir_op_pack_32_to_r11g11b10_v3d', 377) +nir_op_pack_4x16_to_4x8_v3d = nir_op.define('nir_op_pack_4x16_to_4x8_v3d', 378) +nir_op_pack_64_2x32 = nir_op.define('nir_op_pack_64_2x32', 379) +nir_op_pack_64_2x32_split = nir_op.define('nir_op_pack_64_2x32_split', 380) +nir_op_pack_64_4x16 = nir_op.define('nir_op_pack_64_4x16', 381) +nir_op_pack_double_2x32_dxil = nir_op.define('nir_op_pack_double_2x32_dxil', 382) +nir_op_pack_half_2x16 = nir_op.define('nir_op_pack_half_2x16', 383) +nir_op_pack_half_2x16_rtz_split = nir_op.define('nir_op_pack_half_2x16_rtz_split', 384) +nir_op_pack_half_2x16_split = nir_op.define('nir_op_pack_half_2x16_split', 385) +nir_op_pack_sint_2x16 = nir_op.define('nir_op_pack_sint_2x16', 386) +nir_op_pack_snorm_2x16 = nir_op.define('nir_op_pack_snorm_2x16', 387) +nir_op_pack_snorm_4x8 = nir_op.define('nir_op_pack_snorm_4x8', 388) +nir_op_pack_uint_2x16 = nir_op.define('nir_op_pack_uint_2x16', 389) +nir_op_pack_uint_32_to_r10g10b10a2_v3d = nir_op.define('nir_op_pack_uint_32_to_r10g10b10a2_v3d', 390) +nir_op_pack_unorm_2x16 = nir_op.define('nir_op_pack_unorm_2x16', 391) +nir_op_pack_unorm_4x8 = nir_op.define('nir_op_pack_unorm_4x8', 392) +nir_op_pack_uvec2_to_uint = nir_op.define('nir_op_pack_uvec2_to_uint', 393) +nir_op_pack_uvec4_to_uint = nir_op.define('nir_op_pack_uvec4_to_uint', 394) +nir_op_prmt_nv = nir_op.define('nir_op_prmt_nv', 395) +nir_op_sdot_2x16_iadd = nir_op.define('nir_op_sdot_2x16_iadd', 396) +nir_op_sdot_2x16_iadd_sat = nir_op.define('nir_op_sdot_2x16_iadd_sat', 397) +nir_op_sdot_4x8_iadd = nir_op.define('nir_op_sdot_4x8_iadd', 398) +nir_op_sdot_4x8_iadd_sat = nir_op.define('nir_op_sdot_4x8_iadd_sat', 399) +nir_op_seq = nir_op.define('nir_op_seq', 400) +nir_op_sge = nir_op.define('nir_op_sge', 401) +nir_op_shfr = nir_op.define('nir_op_shfr', 402) +nir_op_shlg_ir3 = nir_op.define('nir_op_shlg_ir3', 403) +nir_op_shlm_ir3 = nir_op.define('nir_op_shlm_ir3', 404) +nir_op_shrg_ir3 = nir_op.define('nir_op_shrg_ir3', 405) +nir_op_shrm_ir3 = nir_op.define('nir_op_shrm_ir3', 406) +nir_op_slt = nir_op.define('nir_op_slt', 407) +nir_op_sne = nir_op.define('nir_op_sne', 408) +nir_op_sudot_4x8_iadd = nir_op.define('nir_op_sudot_4x8_iadd', 409) +nir_op_sudot_4x8_iadd_sat = nir_op.define('nir_op_sudot_4x8_iadd_sat', 410) +nir_op_u2f16 = nir_op.define('nir_op_u2f16', 411) +nir_op_u2f32 = nir_op.define('nir_op_u2f32', 412) +nir_op_u2f64 = nir_op.define('nir_op_u2f64', 413) +nir_op_u2fmp = nir_op.define('nir_op_u2fmp', 414) +nir_op_u2u1 = nir_op.define('nir_op_u2u1', 415) +nir_op_u2u16 = nir_op.define('nir_op_u2u16', 416) +nir_op_u2u32 = nir_op.define('nir_op_u2u32', 417) +nir_op_u2u64 = nir_op.define('nir_op_u2u64', 418) +nir_op_u2u8 = nir_op.define('nir_op_u2u8', 419) +nir_op_uabs_isub = nir_op.define('nir_op_uabs_isub', 420) +nir_op_uabs_usub = nir_op.define('nir_op_uabs_usub', 421) +nir_op_uadd_carry = nir_op.define('nir_op_uadd_carry', 422) +nir_op_uadd_sat = nir_op.define('nir_op_uadd_sat', 423) +nir_op_ubfe = nir_op.define('nir_op_ubfe', 424) +nir_op_ubitfield_extract = nir_op.define('nir_op_ubitfield_extract', 425) +nir_op_uclz = nir_op.define('nir_op_uclz', 426) +nir_op_udiv = nir_op.define('nir_op_udiv', 427) +nir_op_udiv_aligned_4 = nir_op.define('nir_op_udiv_aligned_4', 428) +nir_op_udot_2x16_uadd = nir_op.define('nir_op_udot_2x16_uadd', 429) +nir_op_udot_2x16_uadd_sat = nir_op.define('nir_op_udot_2x16_uadd_sat', 430) +nir_op_udot_4x8_uadd = nir_op.define('nir_op_udot_4x8_uadd', 431) +nir_op_udot_4x8_uadd_sat = nir_op.define('nir_op_udot_4x8_uadd_sat', 432) +nir_op_ufind_msb = nir_op.define('nir_op_ufind_msb', 433) +nir_op_ufind_msb_rev = nir_op.define('nir_op_ufind_msb_rev', 434) +nir_op_uge = nir_op.define('nir_op_uge', 435) +nir_op_uge16 = nir_op.define('nir_op_uge16', 436) +nir_op_uge32 = nir_op.define('nir_op_uge32', 437) +nir_op_uge8 = nir_op.define('nir_op_uge8', 438) +nir_op_uhadd = nir_op.define('nir_op_uhadd', 439) +nir_op_ulea_agx = nir_op.define('nir_op_ulea_agx', 440) +nir_op_ult = nir_op.define('nir_op_ult', 441) +nir_op_ult16 = nir_op.define('nir_op_ult16', 442) +nir_op_ult32 = nir_op.define('nir_op_ult32', 443) +nir_op_ult8 = nir_op.define('nir_op_ult8', 444) +nir_op_umad24 = nir_op.define('nir_op_umad24', 445) +nir_op_umad24_relaxed = nir_op.define('nir_op_umad24_relaxed', 446) +nir_op_umax = nir_op.define('nir_op_umax', 447) +nir_op_umax_4x8_vc4 = nir_op.define('nir_op_umax_4x8_vc4', 448) +nir_op_umin = nir_op.define('nir_op_umin', 449) +nir_op_umin_4x8_vc4 = nir_op.define('nir_op_umin_4x8_vc4', 450) +nir_op_umod = nir_op.define('nir_op_umod', 451) +nir_op_umul24 = nir_op.define('nir_op_umul24', 452) +nir_op_umul24_relaxed = nir_op.define('nir_op_umul24_relaxed', 453) +nir_op_umul_2x32_64 = nir_op.define('nir_op_umul_2x32_64', 454) +nir_op_umul_32x16 = nir_op.define('nir_op_umul_32x16', 455) +nir_op_umul_high = nir_op.define('nir_op_umul_high', 456) +nir_op_umul_low = nir_op.define('nir_op_umul_low', 457) +nir_op_umul_unorm_4x8_vc4 = nir_op.define('nir_op_umul_unorm_4x8_vc4', 458) +nir_op_unpack_32_2x16 = nir_op.define('nir_op_unpack_32_2x16', 459) +nir_op_unpack_32_2x16_split_x = nir_op.define('nir_op_unpack_32_2x16_split_x', 460) +nir_op_unpack_32_2x16_split_y = nir_op.define('nir_op_unpack_32_2x16_split_y', 461) +nir_op_unpack_32_4x8 = nir_op.define('nir_op_unpack_32_4x8', 462) +nir_op_unpack_64_2x32 = nir_op.define('nir_op_unpack_64_2x32', 463) +nir_op_unpack_64_2x32_split_x = nir_op.define('nir_op_unpack_64_2x32_split_x', 464) +nir_op_unpack_64_2x32_split_y = nir_op.define('nir_op_unpack_64_2x32_split_y', 465) +nir_op_unpack_64_4x16 = nir_op.define('nir_op_unpack_64_4x16', 466) +nir_op_unpack_double_2x32_dxil = nir_op.define('nir_op_unpack_double_2x32_dxil', 467) +nir_op_unpack_half_2x16 = nir_op.define('nir_op_unpack_half_2x16', 468) +nir_op_unpack_half_2x16_split_x = nir_op.define('nir_op_unpack_half_2x16_split_x', 469) +nir_op_unpack_half_2x16_split_y = nir_op.define('nir_op_unpack_half_2x16_split_y', 470) +nir_op_unpack_snorm_2x16 = nir_op.define('nir_op_unpack_snorm_2x16', 471) +nir_op_unpack_snorm_4x8 = nir_op.define('nir_op_unpack_snorm_4x8', 472) +nir_op_unpack_unorm_2x16 = nir_op.define('nir_op_unpack_unorm_2x16', 473) +nir_op_unpack_unorm_4x8 = nir_op.define('nir_op_unpack_unorm_4x8', 474) +nir_op_urhadd = nir_op.define('nir_op_urhadd', 475) +nir_op_urol = nir_op.define('nir_op_urol', 476) +nir_op_uror = nir_op.define('nir_op_uror', 477) +nir_op_usadd_4x8_vc4 = nir_op.define('nir_op_usadd_4x8_vc4', 478) +nir_op_ushr = nir_op.define('nir_op_ushr', 479) +nir_op_ussub_4x8_vc4 = nir_op.define('nir_op_ussub_4x8_vc4', 480) +nir_op_usub_borrow = nir_op.define('nir_op_usub_borrow', 481) +nir_op_usub_sat = nir_op.define('nir_op_usub_sat', 482) +nir_op_vec16 = nir_op.define('nir_op_vec16', 483) +nir_op_vec2 = nir_op.define('nir_op_vec2', 484) +nir_op_vec3 = nir_op.define('nir_op_vec3', 485) +nir_op_vec4 = nir_op.define('nir_op_vec4', 486) +nir_op_vec5 = nir_op.define('nir_op_vec5', 487) +nir_op_vec8 = nir_op.define('nir_op_vec8', 488) +nir_last_opcode = nir_op.define('nir_last_opcode', 488) +nir_num_opcodes = nir_op.define('nir_num_opcodes', 489) + +# nir_op nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd) +try: (nir_type_conversion_op:=dll.nir_type_conversion_op).restype, nir_type_conversion_op.argtypes = nir_op, [nir_alu_type, nir_alu_type, nir_rounding_mode] +except AttributeError: pass + +nir_atomic_op = CEnum(ctypes.c_uint32) +nir_atomic_op_iadd = nir_atomic_op.define('nir_atomic_op_iadd', 0) +nir_atomic_op_imin = nir_atomic_op.define('nir_atomic_op_imin', 1) +nir_atomic_op_umin = nir_atomic_op.define('nir_atomic_op_umin', 2) +nir_atomic_op_imax = nir_atomic_op.define('nir_atomic_op_imax', 3) +nir_atomic_op_umax = nir_atomic_op.define('nir_atomic_op_umax', 4) +nir_atomic_op_iand = nir_atomic_op.define('nir_atomic_op_iand', 5) +nir_atomic_op_ior = nir_atomic_op.define('nir_atomic_op_ior', 6) +nir_atomic_op_ixor = nir_atomic_op.define('nir_atomic_op_ixor', 7) +nir_atomic_op_xchg = nir_atomic_op.define('nir_atomic_op_xchg', 8) +nir_atomic_op_fadd = nir_atomic_op.define('nir_atomic_op_fadd', 9) +nir_atomic_op_fmin = nir_atomic_op.define('nir_atomic_op_fmin', 10) +nir_atomic_op_fmax = nir_atomic_op.define('nir_atomic_op_fmax', 11) +nir_atomic_op_cmpxchg = nir_atomic_op.define('nir_atomic_op_cmpxchg', 12) +nir_atomic_op_fcmpxchg = nir_atomic_op.define('nir_atomic_op_fcmpxchg', 13) +nir_atomic_op_inc_wrap = nir_atomic_op.define('nir_atomic_op_inc_wrap', 14) +nir_atomic_op_dec_wrap = nir_atomic_op.define('nir_atomic_op_dec_wrap', 15) +nir_atomic_op_ordered_add_gfx12_amd = nir_atomic_op.define('nir_atomic_op_ordered_add_gfx12_amd', 16) + +# nir_op nir_atomic_op_to_alu(nir_atomic_op op) +try: (nir_atomic_op_to_alu:=dll.nir_atomic_op_to_alu).restype, nir_atomic_op_to_alu.argtypes = nir_op, [nir_atomic_op] +except AttributeError: pass + +# nir_op nir_op_vec(unsigned int num_components) +try: (nir_op_vec:=dll.nir_op_vec).restype, nir_op_vec.argtypes = nir_op, [ctypes.c_uint32] +except AttributeError: pass + +# bool nir_op_is_vec(nir_op op) +try: (nir_op_is_vec:=dll.nir_op_is_vec).restype, nir_op_is_vec.argtypes = ctypes.c_bool, [nir_op] +except AttributeError: pass + +nir_op_algebraic_property = CEnum(ctypes.c_uint32) +NIR_OP_IS_2SRC_COMMUTATIVE = nir_op_algebraic_property.define('NIR_OP_IS_2SRC_COMMUTATIVE', 1) +NIR_OP_IS_ASSOCIATIVE = nir_op_algebraic_property.define('NIR_OP_IS_ASSOCIATIVE', 2) +NIR_OP_IS_SELECTION = nir_op_algebraic_property.define('NIR_OP_IS_SELECTION', 4) + +class struct_nir_op_info(Struct): pass +struct_nir_op_info._fields_ = [ + ('name', ctypes.POINTER(ctypes.c_char)), + ('num_inputs', uint8_t), + ('output_size', uint8_t), + ('output_type', nir_alu_type), + ('input_sizes', (uint8_t * 16)), + ('input_types', (nir_alu_type * 16)), + ('algebraic_properties', nir_op_algebraic_property), + ('is_conversion', ctypes.c_bool), +] +nir_op_info = struct_nir_op_info +try: nir_op_infos = (nir_op_info * 489).in_dll(dll, 'nir_op_infos') +except (ValueError,AttributeError): pass +class struct_nir_alu_instr(Struct): pass +struct_nir_alu_instr._fields_ = [ + ('instr', nir_instr), + ('op', nir_op), + ('exact', ctypes.c_bool,1), + ('no_signed_wrap', ctypes.c_bool,1), + ('no_unsigned_wrap', ctypes.c_bool,1), + ('fp_fast_math', uint32_t,9), + ('def', nir_def), + ('src', (nir_alu_src * 0)), +] +nir_alu_instr = struct_nir_alu_instr +# void nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src) +try: (nir_alu_src_copy:=dll.nir_alu_src_copy).restype, nir_alu_src_copy.argtypes = None, [ctypes.POINTER(nir_alu_src), ctypes.POINTER(nir_alu_src)] +except AttributeError: pass + +# nir_component_mask_t nir_alu_instr_src_read_mask(const nir_alu_instr *instr, unsigned int src) +try: (nir_alu_instr_src_read_mask:=dll.nir_alu_instr_src_read_mask).restype, nir_alu_instr_src_read_mask.argtypes = nir_component_mask_t, [ctypes.POINTER(nir_alu_instr), ctypes.c_uint32] +except AttributeError: pass + +# unsigned int nir_ssa_alu_instr_src_components(const nir_alu_instr *instr, unsigned int src) +try: (nir_ssa_alu_instr_src_components:=dll.nir_ssa_alu_instr_src_components).restype, nir_ssa_alu_instr_src_components.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_alu_instr), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_alu_instr_is_comparison(const nir_alu_instr *instr) +try: (nir_alu_instr_is_comparison:=dll.nir_alu_instr_is_comparison).restype, nir_alu_instr_is_comparison.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_alu_instr)] +except AttributeError: pass + +# bool nir_const_value_negative_equal(nir_const_value c1, nir_const_value c2, nir_alu_type full_type) +try: (nir_const_value_negative_equal:=dll.nir_const_value_negative_equal).restype, nir_const_value_negative_equal.argtypes = ctypes.c_bool, [nir_const_value, nir_const_value, nir_alu_type] +except AttributeError: pass + +# bool nir_alu_srcs_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2, unsigned int src1, unsigned int src2) +try: (nir_alu_srcs_equal:=dll.nir_alu_srcs_equal).restype, nir_alu_srcs_equal.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_alu_instr), ctypes.POINTER(nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# bool nir_alu_srcs_negative_equal_typed(const nir_alu_instr *alu1, const nir_alu_instr *alu2, unsigned int src1, unsigned int src2, nir_alu_type base_type) +try: (nir_alu_srcs_negative_equal_typed:=dll.nir_alu_srcs_negative_equal_typed).restype, nir_alu_srcs_negative_equal_typed.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_alu_instr), ctypes.POINTER(nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32, nir_alu_type] +except AttributeError: pass + +# bool nir_alu_srcs_negative_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2, unsigned int src1, unsigned int src2) +try: (nir_alu_srcs_negative_equal:=dll.nir_alu_srcs_negative_equal).restype, nir_alu_srcs_negative_equal.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_alu_instr), ctypes.POINTER(nir_alu_instr), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# bool nir_alu_src_is_trivial_ssa(const nir_alu_instr *alu, unsigned int srcn) +try: (nir_alu_src_is_trivial_ssa:=dll.nir_alu_src_is_trivial_ssa).restype, nir_alu_src_is_trivial_ssa.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_alu_instr), ctypes.c_uint32] +except AttributeError: pass + +nir_deref_type = CEnum(ctypes.c_uint32) +nir_deref_type_var = nir_deref_type.define('nir_deref_type_var', 0) +nir_deref_type_array = nir_deref_type.define('nir_deref_type_array', 1) +nir_deref_type_array_wildcard = nir_deref_type.define('nir_deref_type_array_wildcard', 2) +nir_deref_type_ptr_as_array = nir_deref_type.define('nir_deref_type_ptr_as_array', 3) +nir_deref_type_struct = nir_deref_type.define('nir_deref_type_struct', 4) +nir_deref_type_cast = nir_deref_type.define('nir_deref_type_cast', 5) + +class struct_nir_deref_instr(Struct): pass +nir_variable_mode = CEnum(ctypes.c_uint32) +nir_var_system_value = nir_variable_mode.define('nir_var_system_value', 1) +nir_var_uniform = nir_variable_mode.define('nir_var_uniform', 2) +nir_var_shader_in = nir_variable_mode.define('nir_var_shader_in', 4) +nir_var_shader_out = nir_variable_mode.define('nir_var_shader_out', 8) +nir_var_image = nir_variable_mode.define('nir_var_image', 16) +nir_var_shader_call_data = nir_variable_mode.define('nir_var_shader_call_data', 32) +nir_var_ray_hit_attrib = nir_variable_mode.define('nir_var_ray_hit_attrib', 64) +nir_var_mem_ubo = nir_variable_mode.define('nir_var_mem_ubo', 128) +nir_var_mem_push_const = nir_variable_mode.define('nir_var_mem_push_const', 256) +nir_var_mem_ssbo = nir_variable_mode.define('nir_var_mem_ssbo', 512) +nir_var_mem_constant = nir_variable_mode.define('nir_var_mem_constant', 1024) +nir_var_mem_task_payload = nir_variable_mode.define('nir_var_mem_task_payload', 2048) +nir_var_mem_node_payload = nir_variable_mode.define('nir_var_mem_node_payload', 4096) +nir_var_mem_node_payload_in = nir_variable_mode.define('nir_var_mem_node_payload_in', 8192) +nir_var_function_in = nir_variable_mode.define('nir_var_function_in', 16384) +nir_var_function_out = nir_variable_mode.define('nir_var_function_out', 32768) +nir_var_function_inout = nir_variable_mode.define('nir_var_function_inout', 65536) +nir_var_shader_temp = nir_variable_mode.define('nir_var_shader_temp', 131072) +nir_var_function_temp = nir_variable_mode.define('nir_var_function_temp', 262144) +nir_var_mem_shared = nir_variable_mode.define('nir_var_mem_shared', 524288) +nir_var_mem_global = nir_variable_mode.define('nir_var_mem_global', 1048576) +nir_var_mem_generic = nir_variable_mode.define('nir_var_mem_generic', 1966080) +nir_var_read_only_modes = nir_variable_mode.define('nir_var_read_only_modes', 1159) +nir_var_vec_indexable_modes = nir_variable_mode.define('nir_var_vec_indexable_modes', 1969033) +nir_num_variable_modes = nir_variable_mode.define('nir_num_variable_modes', 21) +nir_var_all = nir_variable_mode.define('nir_var_all', 2097151) + +class struct_nir_deref_instr_0(ctypes.Union): pass +struct_nir_deref_instr_0._fields_ = [ + ('var', ctypes.POINTER(nir_variable)), + ('parent', nir_src), +] +class struct_nir_deref_instr_1(ctypes.Union): pass +class struct_nir_deref_instr_1_arr(Struct): pass +struct_nir_deref_instr_1_arr._fields_ = [ + ('index', nir_src), + ('in_bounds', ctypes.c_bool), +] +class struct_nir_deref_instr_1_strct(Struct): pass +struct_nir_deref_instr_1_strct._fields_ = [ + ('index', ctypes.c_uint32), +] +class struct_nir_deref_instr_1_cast(Struct): pass +struct_nir_deref_instr_1_cast._fields_ = [ + ('ptr_stride', ctypes.c_uint32), + ('align_mul', ctypes.c_uint32), + ('align_offset', ctypes.c_uint32), +] +struct_nir_deref_instr_1._fields_ = [ + ('arr', struct_nir_deref_instr_1_arr), + ('strct', struct_nir_deref_instr_1_strct), + ('cast', struct_nir_deref_instr_1_cast), +] +struct_nir_deref_instr._anonymous_ = ['_0', '_1'] +struct_nir_deref_instr._fields_ = [ + ('instr', nir_instr), + ('deref_type', nir_deref_type), + ('modes', nir_variable_mode), + ('type', ctypes.POINTER(struct_glsl_type)), + ('_0', struct_nir_deref_instr_0), + ('_1', struct_nir_deref_instr_1), + ('def', nir_def), +] +nir_deref_instr = struct_nir_deref_instr +# bool nir_deref_cast_is_trivial(nir_deref_instr *cast) +try: (nir_deref_cast_is_trivial:=dll.nir_deref_cast_is_trivial).restype, nir_deref_cast_is_trivial.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +# bool nir_deref_instr_has_indirect(nir_deref_instr *instr) +try: (nir_deref_instr_has_indirect:=dll.nir_deref_instr_has_indirect).restype, nir_deref_instr_has_indirect.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +# bool nir_deref_instr_is_known_out_of_bounds(nir_deref_instr *instr) +try: (nir_deref_instr_is_known_out_of_bounds:=dll.nir_deref_instr_is_known_out_of_bounds).restype, nir_deref_instr_is_known_out_of_bounds.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +nir_deref_instr_has_complex_use_options = CEnum(ctypes.c_uint32) +nir_deref_instr_has_complex_use_allow_memcpy_src = nir_deref_instr_has_complex_use_options.define('nir_deref_instr_has_complex_use_allow_memcpy_src', 1) +nir_deref_instr_has_complex_use_allow_memcpy_dst = nir_deref_instr_has_complex_use_options.define('nir_deref_instr_has_complex_use_allow_memcpy_dst', 2) +nir_deref_instr_has_complex_use_allow_atomics = nir_deref_instr_has_complex_use_options.define('nir_deref_instr_has_complex_use_allow_atomics', 4) + +# bool nir_deref_instr_has_complex_use(nir_deref_instr *instr, nir_deref_instr_has_complex_use_options opts) +try: (nir_deref_instr_has_complex_use:=dll.nir_deref_instr_has_complex_use).restype, nir_deref_instr_has_complex_use.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr), nir_deref_instr_has_complex_use_options] +except AttributeError: pass + +# bool nir_deref_instr_remove_if_unused(nir_deref_instr *instr) +try: (nir_deref_instr_remove_if_unused:=dll.nir_deref_instr_remove_if_unused).restype, nir_deref_instr_remove_if_unused.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +# unsigned int nir_deref_instr_array_stride(nir_deref_instr *instr) +try: (nir_deref_instr_array_stride:=dll.nir_deref_instr_array_stride).restype, nir_deref_instr_array_stride.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +class struct_nir_call_instr(Struct): pass +class struct_nir_function(Struct): pass nir_function = struct_nir_function -nir_intrin_filter_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None)) -nir_vectorize_cb = ctypes.CFUNCTYPE(ctypes.c_ubyte, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)) +class struct_nir_shader(Struct): pass nir_shader = struct_nir_shader -try: - nir_foreach_function_with_impl_first = _libraries['FIXME_STUB'].nir_foreach_function_with_impl_first - nir_foreach_function_with_impl_first.restype = ctypes.POINTER(struct_nir_function) - nir_foreach_function_with_impl_first.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_foreach_function_with_impl_next = _libraries['FIXME_STUB'].nir_foreach_function_with_impl_next - nir_foreach_function_with_impl_next.restype = ctypes.POINTER(struct_nir_function_impl) - nir_foreach_function_with_impl_next.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nir_function))] -except AttributeError: - pass -try: - nir_shader_get_entrypoint = _libraries['FIXME_STUB'].nir_shader_get_entrypoint - nir_shader_get_entrypoint.restype = ctypes.POINTER(struct_nir_function_impl) - nir_shader_get_entrypoint.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_shader_get_function_for_name = _libraries['FIXME_STUB'].nir_shader_get_function_for_name - nir_shader_get_function_for_name.restype = ctypes.POINTER(struct_nir_function) - nir_shader_get_function_for_name.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_remove_non_entrypoints = _libraries['libtinymesa_cpu.so'].nir_remove_non_entrypoints - nir_remove_non_entrypoints.restype = None - nir_remove_non_entrypoints.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_remove_non_exported = _libraries['libtinymesa_cpu.so'].nir_remove_non_exported - nir_remove_non_exported.restype = None - nir_remove_non_exported.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_remove_entrypoints = _libraries['libtinymesa_cpu.so'].nir_remove_entrypoints - nir_remove_entrypoints.restype = None - nir_remove_entrypoints.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_fixup_is_exported = _libraries['libtinymesa_cpu.so'].nir_fixup_is_exported - nir_fixup_is_exported.restype = None - nir_fixup_is_exported.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -gl_shader_stage = pipe_shader_type -gl_shader_stage__enumvalues = pipe_shader_type__enumvalues -try: - nir_shader_create = _libraries['libtinymesa_cpu.so'].nir_shader_create - nir_shader_create.restype = ctypes.POINTER(struct_nir_shader) - nir_shader_create.argtypes = [ctypes.POINTER(None), gl_shader_stage, ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_shader_info)] -except AttributeError: - pass -try: - nir_shader_add_variable = _libraries['libtinymesa_cpu.so'].nir_shader_add_variable - nir_shader_add_variable.restype = None - nir_shader_add_variable.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_function_impl_add_variable = _libraries['FIXME_STUB'].nir_function_impl_add_variable - nir_function_impl_add_variable.restype = None - nir_function_impl_add_variable.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_variable_create = _libraries['libtinymesa_cpu.so'].nir_variable_create - nir_variable_create.restype = ctypes.POINTER(struct_nir_variable) - nir_variable_create.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_local_variable_create = _libraries['libtinymesa_cpu.so'].nir_local_variable_create - nir_local_variable_create.restype = ctypes.POINTER(struct_nir_variable) - nir_local_variable_create.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_state_variable_create = _libraries['libtinymesa_cpu.so'].nir_state_variable_create - nir_state_variable_create.restype = ctypes.POINTER(struct_nir_variable) - nir_state_variable_create.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char), ctypes.c_int16 * 4] -except AttributeError: - pass -try: - nir_get_variable_with_location = _libraries['libtinymesa_cpu.so'].nir_get_variable_with_location - nir_get_variable_with_location.restype = ctypes.POINTER(struct_nir_variable) - nir_get_variable_with_location.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.c_int32, ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - nir_create_variable_with_location = _libraries['libtinymesa_cpu.so'].nir_create_variable_with_location - nir_create_variable_with_location.restype = ctypes.POINTER(struct_nir_variable) - nir_create_variable_with_location.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.c_int32, ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - nir_find_variable_with_location = _libraries['libtinymesa_cpu.so'].nir_find_variable_with_location - nir_find_variable_with_location.restype = ctypes.POINTER(struct_nir_variable) - nir_find_variable_with_location.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_find_variable_with_driver_location = _libraries['libtinymesa_cpu.so'].nir_find_variable_with_driver_location - nir_find_variable_with_driver_location.restype = ctypes.POINTER(struct_nir_variable) - nir_find_variable_with_driver_location.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_find_state_variable = _libraries['libtinymesa_cpu.so'].nir_find_state_variable - nir_find_state_variable.restype = ctypes.POINTER(struct_nir_variable) - nir_find_state_variable.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_int16 * 4] -except AttributeError: - pass -try: - nir_find_sampler_variable_with_tex_index = _libraries['libtinymesa_cpu.so'].nir_find_sampler_variable_with_tex_index - nir_find_sampler_variable_with_tex_index.restype = ctypes.POINTER(struct_nir_variable) - nir_find_sampler_variable_with_tex_index.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_sort_variables_with_modes = _libraries['libtinymesa_cpu.so'].nir_sort_variables_with_modes - nir_sort_variables_with_modes.restype = None - nir_sort_variables_with_modes.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_variable)), nir_variable_mode] -except AttributeError: - pass -try: - nir_function_create = _libraries['libtinymesa_cpu.so'].nir_function_create - nir_function_create.restype = ctypes.POINTER(struct_nir_function) - nir_function_create.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_function_set_impl = _libraries['FIXME_STUB'].nir_function_set_impl - nir_function_set_impl.restype = None - nir_function_set_impl.argtypes = [ctypes.POINTER(struct_nir_function), ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_function_impl_create = _libraries['libtinymesa_cpu.so'].nir_function_impl_create - nir_function_impl_create.restype = ctypes.POINTER(struct_nir_function_impl) - nir_function_impl_create.argtypes = [ctypes.POINTER(struct_nir_function)] -except AttributeError: - pass -try: - nir_function_impl_create_bare = _libraries['libtinymesa_cpu.so'].nir_function_impl_create_bare - nir_function_impl_create_bare.restype = ctypes.POINTER(struct_nir_function_impl) - nir_function_impl_create_bare.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_block_create = _libraries['libtinymesa_cpu.so'].nir_block_create - nir_block_create.restype = ctypes.POINTER(struct_nir_block) - nir_block_create.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_if_create = _libraries['libtinymesa_cpu.so'].nir_if_create - nir_if_create.restype = ctypes.POINTER(struct_nir_if) - nir_if_create.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_loop_create = _libraries['libtinymesa_cpu.so'].nir_loop_create - nir_loop_create.restype = ctypes.POINTER(struct_nir_loop) - nir_loop_create.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_cf_node_get_function = _libraries['libtinymesa_cpu.so'].nir_cf_node_get_function - nir_cf_node_get_function.restype = ctypes.POINTER(struct_nir_function_impl) - nir_cf_node_get_function.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_metadata_require = _libraries['libtinymesa_cpu.so'].nir_metadata_require - nir_metadata_require.restype = None - nir_metadata_require.argtypes = [ctypes.POINTER(struct_nir_function_impl), nir_metadata] -except AttributeError: - pass -try: - nir_shader_preserve_all_metadata = _libraries['libtinymesa_cpu.so'].nir_shader_preserve_all_metadata - nir_shader_preserve_all_metadata.restype = None - nir_shader_preserve_all_metadata.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_metadata_invalidate = _libraries['libtinymesa_cpu.so'].nir_metadata_invalidate - nir_metadata_invalidate.restype = None - nir_metadata_invalidate.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_progress = _libraries['libtinymesa_cpu.so'].nir_progress - nir_progress.restype = ctypes.c_bool - nir_progress.argtypes = [ctypes.c_bool, ctypes.POINTER(struct_nir_function_impl), nir_metadata] -except AttributeError: - pass -try: - nir_no_progress = _libraries['FIXME_STUB'].nir_no_progress - nir_no_progress.restype = ctypes.c_bool - nir_no_progress.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_alu_instr_create = _libraries['libtinymesa_cpu.so'].nir_alu_instr_create - nir_alu_instr_create.restype = ctypes.POINTER(struct_nir_alu_instr) - nir_alu_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), nir_op] -except AttributeError: - pass -try: - nir_deref_instr_create = _libraries['libtinymesa_cpu.so'].nir_deref_instr_create - nir_deref_instr_create.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_deref_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), nir_deref_type] -except AttributeError: - pass -try: - nir_jump_instr_create = _libraries['libtinymesa_cpu.so'].nir_jump_instr_create - nir_jump_instr_create.restype = ctypes.POINTER(struct_nir_jump_instr) - nir_jump_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), nir_jump_type] -except AttributeError: - pass -try: - nir_load_const_instr_create = _libraries['libtinymesa_cpu.so'].nir_load_const_instr_create - nir_load_const_instr_create.restype = ctypes.POINTER(struct_nir_load_const_instr) - nir_load_const_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_intrinsic_instr_create = _libraries['libtinymesa_cpu.so'].nir_intrinsic_instr_create - nir_intrinsic_instr_create.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_intrinsic_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), nir_intrinsic_op] -except AttributeError: - pass -try: - nir_call_instr_create = _libraries['libtinymesa_cpu.so'].nir_call_instr_create - nir_call_instr_create.restype = ctypes.POINTER(struct_nir_call_instr) - nir_call_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function)] -except AttributeError: - pass -try: - nir_tex_instr_create = _libraries['libtinymesa_cpu.so'].nir_tex_instr_create - nir_tex_instr_create.restype = ctypes.POINTER(struct_nir_tex_instr) - nir_tex_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_phi_instr_create = _libraries['libtinymesa_cpu.so'].nir_phi_instr_create - nir_phi_instr_create.restype = ctypes.POINTER(struct_nir_phi_instr) - nir_phi_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_phi_instr_add_src = _libraries['libtinymesa_cpu.so'].nir_phi_instr_add_src - nir_phi_instr_add_src.restype = ctypes.POINTER(struct_nir_phi_src) - nir_phi_instr_add_src.argtypes = [ctypes.POINTER(struct_nir_phi_instr), ctypes.POINTER(struct_nir_block), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_parallel_copy_instr_create = _libraries['libtinymesa_cpu.so'].nir_parallel_copy_instr_create - nir_parallel_copy_instr_create.restype = ctypes.POINTER(struct_nir_parallel_copy_instr) - nir_parallel_copy_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_undef_instr_create = _libraries['libtinymesa_cpu.so'].nir_undef_instr_create - nir_undef_instr_create.restype = ctypes.POINTER(struct_nir_undef_instr) - nir_undef_instr_create.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_alu_binop_identity = _libraries['libtinymesa_cpu.so'].nir_alu_binop_identity - nir_alu_binop_identity.restype = nir_const_value - nir_alu_binop_identity.argtypes = [nir_op, ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_cursor_option' -c__EA_nir_cursor_option__enumvalues = { - 0: 'nir_cursor_before_block', - 1: 'nir_cursor_after_block', - 2: 'nir_cursor_before_instr', - 3: 'nir_cursor_after_instr', -} -nir_cursor_before_block = 0 -nir_cursor_after_block = 1 -nir_cursor_before_instr = 2 -nir_cursor_after_instr = 3 -c__EA_nir_cursor_option = ctypes.c_uint32 # enum -nir_cursor_option = c__EA_nir_cursor_option -nir_cursor_option__enumvalues = c__EA_nir_cursor_option__enumvalues -class struct_nir_cursor(Structure): - pass - -class union_nir_cursor_0(Union): - pass - -union_nir_cursor_0._pack_ = 1 # source:False -union_nir_cursor_0._fields_ = [ - ('block', ctypes.POINTER(struct_nir_block)), - ('instr', ctypes.POINTER(struct_nir_instr)), +class struct_gc_ctx(Struct): pass +gc_ctx = struct_gc_ctx +class struct_nir_shader_compiler_options(Struct): pass +nir_shader_compiler_options = struct_nir_shader_compiler_options +class const_struct_nir_instr(Struct): pass +const_struct_nir_instr._fields_ = [ + ('node', struct_exec_node), + ('block', ctypes.POINTER(nir_block)), + ('type', nir_instr_type), + ('pass_flags', uint8_t), + ('has_debug_info', ctypes.c_bool), + ('index', uint32_t), ] +nir_instr_filter_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(const_struct_nir_instr), ctypes.c_void_p) +nir_lower_int64_options = CEnum(ctypes.c_uint32) +nir_lower_imul64 = nir_lower_int64_options.define('nir_lower_imul64', 1) +nir_lower_isign64 = nir_lower_int64_options.define('nir_lower_isign64', 2) +nir_lower_divmod64 = nir_lower_int64_options.define('nir_lower_divmod64', 4) +nir_lower_imul_high64 = nir_lower_int64_options.define('nir_lower_imul_high64', 8) +nir_lower_bcsel64 = nir_lower_int64_options.define('nir_lower_bcsel64', 16) +nir_lower_icmp64 = nir_lower_int64_options.define('nir_lower_icmp64', 32) +nir_lower_iadd64 = nir_lower_int64_options.define('nir_lower_iadd64', 64) +nir_lower_iabs64 = nir_lower_int64_options.define('nir_lower_iabs64', 128) +nir_lower_ineg64 = nir_lower_int64_options.define('nir_lower_ineg64', 256) +nir_lower_logic64 = nir_lower_int64_options.define('nir_lower_logic64', 512) +nir_lower_minmax64 = nir_lower_int64_options.define('nir_lower_minmax64', 1024) +nir_lower_shift64 = nir_lower_int64_options.define('nir_lower_shift64', 2048) +nir_lower_imul_2x32_64 = nir_lower_int64_options.define('nir_lower_imul_2x32_64', 4096) +nir_lower_extract64 = nir_lower_int64_options.define('nir_lower_extract64', 8192) +nir_lower_ufind_msb64 = nir_lower_int64_options.define('nir_lower_ufind_msb64', 16384) +nir_lower_bit_count64 = nir_lower_int64_options.define('nir_lower_bit_count64', 32768) +nir_lower_subgroup_shuffle64 = nir_lower_int64_options.define('nir_lower_subgroup_shuffle64', 65536) +nir_lower_scan_reduce_bitwise64 = nir_lower_int64_options.define('nir_lower_scan_reduce_bitwise64', 131072) +nir_lower_scan_reduce_iadd64 = nir_lower_int64_options.define('nir_lower_scan_reduce_iadd64', 262144) +nir_lower_vote_ieq64 = nir_lower_int64_options.define('nir_lower_vote_ieq64', 524288) +nir_lower_usub_sat64 = nir_lower_int64_options.define('nir_lower_usub_sat64', 1048576) +nir_lower_iadd_sat64 = nir_lower_int64_options.define('nir_lower_iadd_sat64', 2097152) +nir_lower_find_lsb64 = nir_lower_int64_options.define('nir_lower_find_lsb64', 4194304) +nir_lower_conv64 = nir_lower_int64_options.define('nir_lower_conv64', 8388608) +nir_lower_uadd_sat64 = nir_lower_int64_options.define('nir_lower_uadd_sat64', 16777216) +nir_lower_iadd3_64 = nir_lower_int64_options.define('nir_lower_iadd3_64', 33554432) +nir_lower_bitfield_reverse64 = nir_lower_int64_options.define('nir_lower_bitfield_reverse64', 67108864) +nir_lower_bitfield_extract64 = nir_lower_int64_options.define('nir_lower_bitfield_extract64', 134217728) -struct_nir_cursor._pack_ = 1 # source:False -struct_nir_cursor._anonymous_ = ('_0',) +nir_lower_doubles_options = CEnum(ctypes.c_uint32) +nir_lower_drcp = nir_lower_doubles_options.define('nir_lower_drcp', 1) +nir_lower_dsqrt = nir_lower_doubles_options.define('nir_lower_dsqrt', 2) +nir_lower_drsq = nir_lower_doubles_options.define('nir_lower_drsq', 4) +nir_lower_dtrunc = nir_lower_doubles_options.define('nir_lower_dtrunc', 8) +nir_lower_dfloor = nir_lower_doubles_options.define('nir_lower_dfloor', 16) +nir_lower_dceil = nir_lower_doubles_options.define('nir_lower_dceil', 32) +nir_lower_dfract = nir_lower_doubles_options.define('nir_lower_dfract', 64) +nir_lower_dround_even = nir_lower_doubles_options.define('nir_lower_dround_even', 128) +nir_lower_dmod = nir_lower_doubles_options.define('nir_lower_dmod', 256) +nir_lower_dsub = nir_lower_doubles_options.define('nir_lower_dsub', 512) +nir_lower_ddiv = nir_lower_doubles_options.define('nir_lower_ddiv', 1024) +nir_lower_dsign = nir_lower_doubles_options.define('nir_lower_dsign', 2048) +nir_lower_dminmax = nir_lower_doubles_options.define('nir_lower_dminmax', 4096) +nir_lower_dsat = nir_lower_doubles_options.define('nir_lower_dsat', 8192) +nir_lower_fp64_full_software = nir_lower_doubles_options.define('nir_lower_fp64_full_software', 16384) + +nir_divergence_options = CEnum(ctypes.c_uint32) +nir_divergence_single_prim_per_subgroup = nir_divergence_options.define('nir_divergence_single_prim_per_subgroup', 1) +nir_divergence_single_patch_per_tcs_subgroup = nir_divergence_options.define('nir_divergence_single_patch_per_tcs_subgroup', 2) +nir_divergence_single_patch_per_tes_subgroup = nir_divergence_options.define('nir_divergence_single_patch_per_tes_subgroup', 4) +nir_divergence_view_index_uniform = nir_divergence_options.define('nir_divergence_view_index_uniform', 8) +nir_divergence_single_frag_shading_rate_per_subgroup = nir_divergence_options.define('nir_divergence_single_frag_shading_rate_per_subgroup', 16) +nir_divergence_multiple_workgroup_per_compute_subgroup = nir_divergence_options.define('nir_divergence_multiple_workgroup_per_compute_subgroup', 32) +nir_divergence_shader_record_ptr_uniform = nir_divergence_options.define('nir_divergence_shader_record_ptr_uniform', 64) +nir_divergence_uniform_load_tears = nir_divergence_options.define('nir_divergence_uniform_load_tears', 128) +nir_divergence_ignore_undef_if_phi_srcs = nir_divergence_options.define('nir_divergence_ignore_undef_if_phi_srcs', 256) + +nir_io_options = CEnum(ctypes.c_uint32) +nir_io_has_flexible_input_interpolation_except_flat = nir_io_options.define('nir_io_has_flexible_input_interpolation_except_flat', 1) +nir_io_dont_use_pos_for_non_fs_varyings = nir_io_options.define('nir_io_dont_use_pos_for_non_fs_varyings', 2) +nir_io_16bit_input_output_support = nir_io_options.define('nir_io_16bit_input_output_support', 4) +nir_io_mediump_is_32bit = nir_io_options.define('nir_io_mediump_is_32bit', 8) +nir_io_prefer_scalar_fs_inputs = nir_io_options.define('nir_io_prefer_scalar_fs_inputs', 16) +nir_io_mix_convergent_flat_with_interpolated = nir_io_options.define('nir_io_mix_convergent_flat_with_interpolated', 32) +nir_io_vectorizer_ignores_types = nir_io_options.define('nir_io_vectorizer_ignores_types', 64) +nir_io_always_interpolate_convergent_fs_inputs = nir_io_options.define('nir_io_always_interpolate_convergent_fs_inputs', 128) +nir_io_compaction_rotates_color_channels = nir_io_options.define('nir_io_compaction_rotates_color_channels', 256) +nir_io_compaction_groups_tes_inputs_into_pos_and_var_groups = nir_io_options.define('nir_io_compaction_groups_tes_inputs_into_pos_and_var_groups', 512) +nir_io_radv_intrinsic_component_workaround = nir_io_options.define('nir_io_radv_intrinsic_component_workaround', 1024) +nir_io_has_intrinsics = nir_io_options.define('nir_io_has_intrinsics', 65536) +nir_io_separate_clip_cull_distance_arrays = nir_io_options.define('nir_io_separate_clip_cull_distance_arrays', 131072) + +struct_nir_shader_compiler_options._fields_ = [ + ('lower_fdiv', ctypes.c_bool), + ('lower_ffma16', ctypes.c_bool), + ('lower_ffma32', ctypes.c_bool), + ('lower_ffma64', ctypes.c_bool), + ('fuse_ffma16', ctypes.c_bool), + ('fuse_ffma32', ctypes.c_bool), + ('fuse_ffma64', ctypes.c_bool), + ('lower_flrp16', ctypes.c_bool), + ('lower_flrp32', ctypes.c_bool), + ('lower_flrp64', ctypes.c_bool), + ('lower_fpow', ctypes.c_bool), + ('lower_fsat', ctypes.c_bool), + ('lower_fsqrt', ctypes.c_bool), + ('lower_sincos', ctypes.c_bool), + ('lower_fmod', ctypes.c_bool), + ('lower_bitfield_extract8', ctypes.c_bool), + ('lower_bitfield_extract16', ctypes.c_bool), + ('lower_bitfield_extract', ctypes.c_bool), + ('lower_bitfield_insert', ctypes.c_bool), + ('lower_bitfield_reverse', ctypes.c_bool), + ('lower_bit_count', ctypes.c_bool), + ('lower_ifind_msb', ctypes.c_bool), + ('lower_ufind_msb', ctypes.c_bool), + ('lower_find_lsb', ctypes.c_bool), + ('lower_uadd_carry', ctypes.c_bool), + ('lower_usub_borrow', ctypes.c_bool), + ('lower_mul_high', ctypes.c_bool), + ('lower_mul_high16', ctypes.c_bool), + ('lower_fneg', ctypes.c_bool), + ('lower_ineg', ctypes.c_bool), + ('lower_fisnormal', ctypes.c_bool), + ('lower_scmp', ctypes.c_bool), + ('lower_vector_cmp', ctypes.c_bool), + ('lower_bitops', ctypes.c_bool), + ('lower_isign', ctypes.c_bool), + ('lower_fsign', ctypes.c_bool), + ('lower_iabs', ctypes.c_bool), + ('lower_umax', ctypes.c_bool), + ('lower_umin', ctypes.c_bool), + ('lower_fminmax_signed_zero', ctypes.c_bool), + ('lower_fdph', ctypes.c_bool), + ('fdot_replicates', ctypes.c_bool), + ('lower_ffloor', ctypes.c_bool), + ('lower_ffract', ctypes.c_bool), + ('lower_fceil', ctypes.c_bool), + ('lower_ftrunc', ctypes.c_bool), + ('lower_fround_even', ctypes.c_bool), + ('lower_ldexp', ctypes.c_bool), + ('lower_pack_half_2x16', ctypes.c_bool), + ('lower_pack_unorm_2x16', ctypes.c_bool), + ('lower_pack_snorm_2x16', ctypes.c_bool), + ('lower_pack_unorm_4x8', ctypes.c_bool), + ('lower_pack_snorm_4x8', ctypes.c_bool), + ('lower_pack_64_2x32', ctypes.c_bool), + ('lower_pack_64_4x16', ctypes.c_bool), + ('lower_pack_32_2x16', ctypes.c_bool), + ('lower_pack_64_2x32_split', ctypes.c_bool), + ('lower_pack_32_2x16_split', ctypes.c_bool), + ('lower_unpack_half_2x16', ctypes.c_bool), + ('lower_unpack_unorm_2x16', ctypes.c_bool), + ('lower_unpack_snorm_2x16', ctypes.c_bool), + ('lower_unpack_unorm_4x8', ctypes.c_bool), + ('lower_unpack_snorm_4x8', ctypes.c_bool), + ('lower_unpack_64_2x32_split', ctypes.c_bool), + ('lower_unpack_32_2x16_split', ctypes.c_bool), + ('lower_pack_split', ctypes.c_bool), + ('lower_extract_byte', ctypes.c_bool), + ('lower_extract_word', ctypes.c_bool), + ('lower_insert_byte', ctypes.c_bool), + ('lower_insert_word', ctypes.c_bool), + ('vertex_id_zero_based', ctypes.c_bool), + ('lower_base_vertex', ctypes.c_bool), + ('instance_id_includes_base_index', ctypes.c_bool), + ('lower_helper_invocation', ctypes.c_bool), + ('optimize_sample_mask_in', ctypes.c_bool), + ('optimize_load_front_face_fsign', ctypes.c_bool), + ('optimize_quad_vote_to_reduce', ctypes.c_bool), + ('lower_cs_local_index_to_id', ctypes.c_bool), + ('lower_cs_local_id_to_index', ctypes.c_bool), + ('has_cs_global_id', ctypes.c_bool), + ('lower_device_index_to_zero', ctypes.c_bool), + ('lower_wpos_pntc', ctypes.c_bool), + ('lower_hadd', ctypes.c_bool), + ('lower_hadd64', ctypes.c_bool), + ('lower_uadd_sat', ctypes.c_bool), + ('lower_usub_sat', ctypes.c_bool), + ('lower_iadd_sat', ctypes.c_bool), + ('lower_mul_32x16', ctypes.c_bool), + ('lower_bfloat16_conversions', ctypes.c_bool), + ('vectorize_tess_levels', ctypes.c_bool), + ('lower_to_scalar', ctypes.c_bool), + ('lower_to_scalar_filter', nir_instr_filter_cb), + ('vectorize_vec2_16bit', ctypes.c_bool), + ('unify_interfaces', ctypes.c_bool), + ('lower_interpolate_at', ctypes.c_bool), + ('lower_mul_2x32_64', ctypes.c_bool), + ('has_rotate8', ctypes.c_bool), + ('has_rotate16', ctypes.c_bool), + ('has_rotate32', ctypes.c_bool), + ('has_shfr32', ctypes.c_bool), + ('has_iadd3', ctypes.c_bool), + ('has_amul', ctypes.c_bool), + ('has_imul24', ctypes.c_bool), + ('has_umul24', ctypes.c_bool), + ('has_mul24_relaxed', ctypes.c_bool), + ('has_imad32', ctypes.c_bool), + ('has_umad24', ctypes.c_bool), + ('has_fused_comp_and_csel', ctypes.c_bool), + ('has_icsel_eqz64', ctypes.c_bool), + ('has_icsel_eqz32', ctypes.c_bool), + ('has_icsel_eqz16', ctypes.c_bool), + ('has_fneo_fcmpu', ctypes.c_bool), + ('has_ford_funord', ctypes.c_bool), + ('has_fsub', ctypes.c_bool), + ('has_isub', ctypes.c_bool), + ('has_pack_32_4x8', ctypes.c_bool), + ('has_texture_scaling', ctypes.c_bool), + ('has_sdot_4x8', ctypes.c_bool), + ('has_udot_4x8', ctypes.c_bool), + ('has_sudot_4x8', ctypes.c_bool), + ('has_sdot_4x8_sat', ctypes.c_bool), + ('has_udot_4x8_sat', ctypes.c_bool), + ('has_sudot_4x8_sat', ctypes.c_bool), + ('has_dot_2x16', ctypes.c_bool), + ('has_bfdot2_bfadd', ctypes.c_bool), + ('has_fmulz', ctypes.c_bool), + ('has_fmulz_no_denorms', ctypes.c_bool), + ('has_find_msb_rev', ctypes.c_bool), + ('has_pack_half_2x16_rtz', ctypes.c_bool), + ('has_bit_test', ctypes.c_bool), + ('has_bfe', ctypes.c_bool), + ('has_bfm', ctypes.c_bool), + ('has_bfi', ctypes.c_bool), + ('has_bitfield_select', ctypes.c_bool), + ('has_uclz', ctypes.c_bool), + ('has_msad', ctypes.c_bool), + ('has_f2e4m3fn_satfn', ctypes.c_bool), + ('has_load_global_bounded', ctypes.c_bool), + ('intel_vec4', ctypes.c_bool), + ('avoid_ternary_with_two_constants', ctypes.c_bool), + ('support_8bit_alu', ctypes.c_bool), + ('support_16bit_alu', ctypes.c_bool), + ('max_unroll_iterations', ctypes.c_uint32), + ('max_unroll_iterations_aggressive', ctypes.c_uint32), + ('max_unroll_iterations_fp64', ctypes.c_uint32), + ('lower_uniforms_to_ubo', ctypes.c_bool), + ('force_indirect_unrolling_sampler', ctypes.c_bool), + ('no_integers', ctypes.c_bool), + ('force_indirect_unrolling', nir_variable_mode), + ('driver_functions', ctypes.c_bool), + ('late_lower_int64', ctypes.c_bool), + ('lower_int64_options', nir_lower_int64_options), + ('lower_doubles_options', nir_lower_doubles_options), + ('divergence_analysis_options', nir_divergence_options), + ('support_indirect_inputs', uint8_t), + ('support_indirect_outputs', uint8_t), + ('lower_image_offset_to_range_base', ctypes.c_bool), + ('lower_atomic_offset_to_range_base', ctypes.c_bool), + ('preserve_mediump', ctypes.c_bool), + ('lower_fquantize2f16', ctypes.c_bool), + ('force_f2f16_rtz', ctypes.c_bool), + ('lower_layer_fs_input_to_sysval', ctypes.c_bool), + ('compact_arrays', ctypes.c_bool), + ('discard_is_demote', ctypes.c_bool), + ('has_ddx_intrinsics', ctypes.c_bool), + ('scalarize_ddx', ctypes.c_bool), + ('per_view_unique_driver_locations', ctypes.c_bool), + ('compact_view_index', ctypes.c_bool), + ('io_options', nir_io_options), + ('skip_lower_packing_ops', ctypes.c_uint32), + ('lower_mediump_io', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_nir_shader))), + ('varying_expression_max_cost', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader))), + ('varying_estimate_instr_cost', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_instr))), + ('max_varying_expression_cost', ctypes.c_uint32), +] +class struct_shader_info(Struct): pass +blake3_hash = (ctypes.c_ubyte * 32) +enum_pipe_shader_type = CEnum(ctypes.c_int32) +MESA_SHADER_NONE = enum_pipe_shader_type.define('MESA_SHADER_NONE', -1) +MESA_SHADER_VERTEX = enum_pipe_shader_type.define('MESA_SHADER_VERTEX', 0) +PIPE_SHADER_VERTEX = enum_pipe_shader_type.define('PIPE_SHADER_VERTEX', 0) +MESA_SHADER_TESS_CTRL = enum_pipe_shader_type.define('MESA_SHADER_TESS_CTRL', 1) +PIPE_SHADER_TESS_CTRL = enum_pipe_shader_type.define('PIPE_SHADER_TESS_CTRL', 1) +MESA_SHADER_TESS_EVAL = enum_pipe_shader_type.define('MESA_SHADER_TESS_EVAL', 2) +PIPE_SHADER_TESS_EVAL = enum_pipe_shader_type.define('PIPE_SHADER_TESS_EVAL', 2) +MESA_SHADER_GEOMETRY = enum_pipe_shader_type.define('MESA_SHADER_GEOMETRY', 3) +PIPE_SHADER_GEOMETRY = enum_pipe_shader_type.define('PIPE_SHADER_GEOMETRY', 3) +MESA_SHADER_FRAGMENT = enum_pipe_shader_type.define('MESA_SHADER_FRAGMENT', 4) +PIPE_SHADER_FRAGMENT = enum_pipe_shader_type.define('PIPE_SHADER_FRAGMENT', 4) +MESA_SHADER_COMPUTE = enum_pipe_shader_type.define('MESA_SHADER_COMPUTE', 5) +PIPE_SHADER_COMPUTE = enum_pipe_shader_type.define('PIPE_SHADER_COMPUTE', 5) +PIPE_SHADER_TYPES = enum_pipe_shader_type.define('PIPE_SHADER_TYPES', 6) +MESA_SHADER_TASK = enum_pipe_shader_type.define('MESA_SHADER_TASK', 6) +PIPE_SHADER_TASK = enum_pipe_shader_type.define('PIPE_SHADER_TASK', 6) +MESA_SHADER_MESH = enum_pipe_shader_type.define('MESA_SHADER_MESH', 7) +PIPE_SHADER_MESH = enum_pipe_shader_type.define('PIPE_SHADER_MESH', 7) +PIPE_SHADER_MESH_TYPES = enum_pipe_shader_type.define('PIPE_SHADER_MESH_TYPES', 8) +MESA_SHADER_RAYGEN = enum_pipe_shader_type.define('MESA_SHADER_RAYGEN', 8) +MESA_SHADER_ANY_HIT = enum_pipe_shader_type.define('MESA_SHADER_ANY_HIT', 9) +MESA_SHADER_CLOSEST_HIT = enum_pipe_shader_type.define('MESA_SHADER_CLOSEST_HIT', 10) +MESA_SHADER_MISS = enum_pipe_shader_type.define('MESA_SHADER_MISS', 11) +MESA_SHADER_INTERSECTION = enum_pipe_shader_type.define('MESA_SHADER_INTERSECTION', 12) +MESA_SHADER_CALLABLE = enum_pipe_shader_type.define('MESA_SHADER_CALLABLE', 13) +MESA_SHADER_KERNEL = enum_pipe_shader_type.define('MESA_SHADER_KERNEL', 14) + +gl_shader_stage = enum_pipe_shader_type +enum_gl_subgroup_size = CEnum(ctypes.c_ubyte) +SUBGROUP_SIZE_VARYING = enum_gl_subgroup_size.define('SUBGROUP_SIZE_VARYING', 0) +SUBGROUP_SIZE_UNIFORM = enum_gl_subgroup_size.define('SUBGROUP_SIZE_UNIFORM', 1) +SUBGROUP_SIZE_API_CONSTANT = enum_gl_subgroup_size.define('SUBGROUP_SIZE_API_CONSTANT', 2) +SUBGROUP_SIZE_FULL_SUBGROUPS = enum_gl_subgroup_size.define('SUBGROUP_SIZE_FULL_SUBGROUPS', 3) +SUBGROUP_SIZE_REQUIRE_4 = enum_gl_subgroup_size.define('SUBGROUP_SIZE_REQUIRE_4', 4) +SUBGROUP_SIZE_REQUIRE_8 = enum_gl_subgroup_size.define('SUBGROUP_SIZE_REQUIRE_8', 8) +SUBGROUP_SIZE_REQUIRE_16 = enum_gl_subgroup_size.define('SUBGROUP_SIZE_REQUIRE_16', 16) +SUBGROUP_SIZE_REQUIRE_32 = enum_gl_subgroup_size.define('SUBGROUP_SIZE_REQUIRE_32', 32) +SUBGROUP_SIZE_REQUIRE_64 = enum_gl_subgroup_size.define('SUBGROUP_SIZE_REQUIRE_64', 64) +SUBGROUP_SIZE_REQUIRE_128 = enum_gl_subgroup_size.define('SUBGROUP_SIZE_REQUIRE_128', 128) + +enum_gl_derivative_group = CEnum(ctypes.c_uint32) +DERIVATIVE_GROUP_NONE = enum_gl_derivative_group.define('DERIVATIVE_GROUP_NONE', 0) +DERIVATIVE_GROUP_QUADS = enum_gl_derivative_group.define('DERIVATIVE_GROUP_QUADS', 1) +DERIVATIVE_GROUP_LINEAR = enum_gl_derivative_group.define('DERIVATIVE_GROUP_LINEAR', 2) + +class struct_shader_info_0(ctypes.Union): pass +class struct_shader_info_0_vs(Struct): pass +struct_shader_info_0_vs._fields_ = [ + ('double_inputs', uint64_t), + ('blit_sgprs_amd', uint8_t,4), + ('tes_agx', ctypes.c_bool,1), + ('window_space_position', ctypes.c_bool,1), + ('needs_edge_flag', ctypes.c_bool,1), +] +class struct_shader_info_0_gs(Struct): pass +enum_mesa_prim = CEnum(ctypes.c_ubyte) +MESA_PRIM_POINTS = enum_mesa_prim.define('MESA_PRIM_POINTS', 0) +MESA_PRIM_LINES = enum_mesa_prim.define('MESA_PRIM_LINES', 1) +MESA_PRIM_LINE_LOOP = enum_mesa_prim.define('MESA_PRIM_LINE_LOOP', 2) +MESA_PRIM_LINE_STRIP = enum_mesa_prim.define('MESA_PRIM_LINE_STRIP', 3) +MESA_PRIM_TRIANGLES = enum_mesa_prim.define('MESA_PRIM_TRIANGLES', 4) +MESA_PRIM_TRIANGLE_STRIP = enum_mesa_prim.define('MESA_PRIM_TRIANGLE_STRIP', 5) +MESA_PRIM_TRIANGLE_FAN = enum_mesa_prim.define('MESA_PRIM_TRIANGLE_FAN', 6) +MESA_PRIM_QUADS = enum_mesa_prim.define('MESA_PRIM_QUADS', 7) +MESA_PRIM_QUAD_STRIP = enum_mesa_prim.define('MESA_PRIM_QUAD_STRIP', 8) +MESA_PRIM_POLYGON = enum_mesa_prim.define('MESA_PRIM_POLYGON', 9) +MESA_PRIM_LINES_ADJACENCY = enum_mesa_prim.define('MESA_PRIM_LINES_ADJACENCY', 10) +MESA_PRIM_LINE_STRIP_ADJACENCY = enum_mesa_prim.define('MESA_PRIM_LINE_STRIP_ADJACENCY', 11) +MESA_PRIM_TRIANGLES_ADJACENCY = enum_mesa_prim.define('MESA_PRIM_TRIANGLES_ADJACENCY', 12) +MESA_PRIM_TRIANGLE_STRIP_ADJACENCY = enum_mesa_prim.define('MESA_PRIM_TRIANGLE_STRIP_ADJACENCY', 13) +MESA_PRIM_PATCHES = enum_mesa_prim.define('MESA_PRIM_PATCHES', 14) +MESA_PRIM_MAX = enum_mesa_prim.define('MESA_PRIM_MAX', 14) +MESA_PRIM_COUNT = enum_mesa_prim.define('MESA_PRIM_COUNT', 15) +MESA_PRIM_UNKNOWN = enum_mesa_prim.define('MESA_PRIM_UNKNOWN', 28) + +struct_shader_info_0_gs._fields_ = [ + ('output_primitive', enum_mesa_prim), + ('input_primitive', enum_mesa_prim), + ('vertices_out', uint16_t), + ('invocations', uint8_t), + ('vertices_in', uint8_t,3), + ('uses_end_primitive', ctypes.c_bool,1), + ('active_stream_mask', uint8_t,4), +] +class struct_shader_info_0_fs(Struct): pass +enum_gl_frag_depth_layout = CEnum(ctypes.c_uint32) +FRAG_DEPTH_LAYOUT_NONE = enum_gl_frag_depth_layout.define('FRAG_DEPTH_LAYOUT_NONE', 0) +FRAG_DEPTH_LAYOUT_ANY = enum_gl_frag_depth_layout.define('FRAG_DEPTH_LAYOUT_ANY', 1) +FRAG_DEPTH_LAYOUT_GREATER = enum_gl_frag_depth_layout.define('FRAG_DEPTH_LAYOUT_GREATER', 2) +FRAG_DEPTH_LAYOUT_LESS = enum_gl_frag_depth_layout.define('FRAG_DEPTH_LAYOUT_LESS', 3) +FRAG_DEPTH_LAYOUT_UNCHANGED = enum_gl_frag_depth_layout.define('FRAG_DEPTH_LAYOUT_UNCHANGED', 4) + +enum_gl_frag_stencil_layout = CEnum(ctypes.c_uint32) +FRAG_STENCIL_LAYOUT_NONE = enum_gl_frag_stencil_layout.define('FRAG_STENCIL_LAYOUT_NONE', 0) +FRAG_STENCIL_LAYOUT_ANY = enum_gl_frag_stencil_layout.define('FRAG_STENCIL_LAYOUT_ANY', 1) +FRAG_STENCIL_LAYOUT_GREATER = enum_gl_frag_stencil_layout.define('FRAG_STENCIL_LAYOUT_GREATER', 2) +FRAG_STENCIL_LAYOUT_LESS = enum_gl_frag_stencil_layout.define('FRAG_STENCIL_LAYOUT_LESS', 3) +FRAG_STENCIL_LAYOUT_UNCHANGED = enum_gl_frag_stencil_layout.define('FRAG_STENCIL_LAYOUT_UNCHANGED', 4) + +struct_shader_info_0_fs._fields_ = [ + ('uses_discard', ctypes.c_bool,1), + ('uses_fbfetch_output', ctypes.c_bool,1), + ('fbfetch_coherent', ctypes.c_bool,1), + ('color_is_dual_source', ctypes.c_bool,1), + ('require_full_quads', ctypes.c_bool,1), + ('quad_derivatives', ctypes.c_bool,1), + ('needs_coarse_quad_helper_invocations', ctypes.c_bool,1), + ('needs_full_quad_helper_invocations', ctypes.c_bool,1), + ('uses_sample_qualifier', ctypes.c_bool,1), + ('uses_sample_shading', ctypes.c_bool,1), + ('early_fragment_tests', ctypes.c_bool,1), + ('inner_coverage', ctypes.c_bool,1), + ('post_depth_coverage', ctypes.c_bool,1), + ('pixel_center_integer', ctypes.c_bool,1), + ('origin_upper_left', ctypes.c_bool,1), + ('pixel_interlock_ordered', ctypes.c_bool,1), + ('pixel_interlock_unordered', ctypes.c_bool,1), + ('sample_interlock_ordered', ctypes.c_bool,1), + ('sample_interlock_unordered', ctypes.c_bool,1), + ('untyped_color_outputs', ctypes.c_bool,1), + ('depth_layout', enum_gl_frag_depth_layout,3), + ('color0_interp', ctypes.c_uint32,3), + ('color0_sample', ctypes.c_bool,1), + ('color0_centroid', ctypes.c_bool,1), + ('color1_interp', ctypes.c_uint32,3), + ('color1_sample', ctypes.c_bool,1), + ('color1_centroid', ctypes.c_bool,1), + ('advanced_blend_modes', ctypes.c_uint32), + ('early_and_late_fragment_tests', ctypes.c_bool,1), + ('stencil_front_layout', enum_gl_frag_stencil_layout,3), + ('stencil_back_layout', enum_gl_frag_stencil_layout,3), +] +class struct_shader_info_0_cs(Struct): pass +struct_shader_info_0_cs._fields_ = [ + ('workgroup_size_hint', (uint16_t * 3)), + ('user_data_components_amd', uint8_t,4), + ('has_variable_shared_mem', ctypes.c_bool,1), + ('has_cooperative_matrix', ctypes.c_bool,1), + ('image_block_size_per_thread_agx', uint8_t), + ('ptr_size', ctypes.c_uint32), + ('shader_index', uint32_t), + ('node_payloads_size', uint32_t), + ('workgroup_count', (uint32_t * 3)), +] +class struct_shader_info_0_tess(Struct): pass +enum_tess_primitive_mode = CEnum(ctypes.c_uint32) +TESS_PRIMITIVE_UNSPECIFIED = enum_tess_primitive_mode.define('TESS_PRIMITIVE_UNSPECIFIED', 0) +TESS_PRIMITIVE_TRIANGLES = enum_tess_primitive_mode.define('TESS_PRIMITIVE_TRIANGLES', 1) +TESS_PRIMITIVE_QUADS = enum_tess_primitive_mode.define('TESS_PRIMITIVE_QUADS', 2) +TESS_PRIMITIVE_ISOLINES = enum_tess_primitive_mode.define('TESS_PRIMITIVE_ISOLINES', 3) + +struct_shader_info_0_tess._fields_ = [ + ('_primitive_mode', enum_tess_primitive_mode), + ('tcs_vertices_out', uint8_t), + ('spacing', ctypes.c_uint32,2), + ('ccw', ctypes.c_bool,1), + ('point_mode', ctypes.c_bool,1), + ('tcs_same_invocation_inputs_read', uint64_t), + ('tcs_cross_invocation_inputs_read', uint64_t), + ('tcs_cross_invocation_outputs_read', uint64_t), + ('tcs_cross_invocation_outputs_written', uint64_t), + ('tcs_outputs_read_by_tes', uint64_t), + ('tcs_patch_outputs_read_by_tes', uint32_t), + ('tcs_outputs_read_by_tes_16bit', uint16_t), +] +class struct_shader_info_0_mesh(Struct): pass +struct_shader_info_0_mesh._fields_ = [ + ('ms_cross_invocation_output_access', uint64_t), + ('ts_mesh_dispatch_dimensions', (uint32_t * 3)), + ('max_vertices_out', uint16_t), + ('max_primitives_out', uint16_t), + ('primitive_type', enum_mesa_prim), + ('nv', ctypes.c_bool), +] +struct_shader_info_0._fields_ = [ + ('vs', struct_shader_info_0_vs), + ('gs', struct_shader_info_0_gs), + ('fs', struct_shader_info_0_fs), + ('cs', struct_shader_info_0_cs), + ('tess', struct_shader_info_0_tess), + ('mesh', struct_shader_info_0_mesh), +] +struct_shader_info._anonymous_ = ['_0'] +struct_shader_info._fields_ = [ + ('name', ctypes.POINTER(ctypes.c_char)), + ('label', ctypes.POINTER(ctypes.c_char)), + ('internal', ctypes.c_bool), + ('source_blake3', blake3_hash), + ('stage', gl_shader_stage,8), + ('prev_stage', gl_shader_stage,8), + ('next_stage', gl_shader_stage,8), + ('prev_stage_has_xfb', ctypes.c_bool), + ('num_textures', uint8_t), + ('num_ubos', uint8_t), + ('num_abos', uint8_t), + ('num_ssbos', uint8_t), + ('num_images', uint8_t), + ('inputs_read', uint64_t), + ('dual_slot_inputs', uint64_t), + ('outputs_written', uint64_t), + ('outputs_read', uint64_t), + ('system_values_read', (ctypes.c_uint32 * 4)), + ('per_primitive_inputs', uint64_t), + ('per_primitive_outputs', uint64_t), + ('per_view_outputs', uint64_t), + ('view_mask', uint32_t), + ('inputs_read_16bit', uint16_t), + ('outputs_written_16bit', uint16_t), + ('outputs_read_16bit', uint16_t), + ('inputs_read_indirectly_16bit', uint16_t), + ('outputs_read_indirectly_16bit', uint16_t), + ('outputs_written_indirectly_16bit', uint16_t), + ('patch_inputs_read', uint32_t), + ('patch_outputs_written', uint32_t), + ('patch_outputs_read', uint32_t), + ('inputs_read_indirectly', uint64_t), + ('outputs_read_indirectly', uint64_t), + ('outputs_written_indirectly', uint64_t), + ('patch_inputs_read_indirectly', uint32_t), + ('patch_outputs_read_indirectly', uint32_t), + ('patch_outputs_written_indirectly', uint32_t), + ('textures_used', (ctypes.c_uint32 * 4)), + ('textures_used_by_txf', (ctypes.c_uint32 * 4)), + ('samplers_used', (ctypes.c_uint32 * 1)), + ('images_used', (ctypes.c_uint32 * 2)), + ('image_buffers', (ctypes.c_uint32 * 2)), + ('msaa_images', (ctypes.c_uint32 * 2)), + ('float_controls_execution_mode', uint32_t), + ('shared_size', ctypes.c_uint32), + ('task_payload_size', ctypes.c_uint32), + ('ray_queries', ctypes.c_uint32), + ('workgroup_size', (uint16_t * 3)), + ('subgroup_size', enum_gl_subgroup_size), + ('num_subgroups', uint8_t), + ('uses_wide_subgroup_intrinsics', ctypes.c_bool), + ('xfb_stride', (uint8_t * 4)), + ('inlinable_uniform_dw_offsets', (uint16_t * 4)), + ('num_inlinable_uniforms', uint8_t,4), + ('clip_distance_array_size', uint8_t,4), + ('cull_distance_array_size', uint8_t,4), + ('uses_texture_gather', ctypes.c_bool,1), + ('uses_resource_info_query', ctypes.c_bool,1), + ('bit_sizes_float', uint8_t), + ('bit_sizes_int', uint8_t), + ('first_ubo_is_default_ubo', ctypes.c_bool,1), + ('separate_shader', ctypes.c_bool,1), + ('has_transform_feedback_varyings', ctypes.c_bool,1), + ('flrp_lowered', ctypes.c_bool,1), + ('io_lowered', ctypes.c_bool,1), + ('var_copies_lowered', ctypes.c_bool,1), + ('writes_memory', ctypes.c_bool,1), + ('layer_viewport_relative', ctypes.c_bool,1), + ('uses_control_barrier', ctypes.c_bool,1), + ('uses_memory_barrier', ctypes.c_bool,1), + ('uses_bindless', ctypes.c_bool,1), + ('shared_memory_explicit_layout', ctypes.c_bool,1), + ('zero_initialize_shared_memory', ctypes.c_bool,1), + ('workgroup_size_variable', ctypes.c_bool,1), + ('uses_printf', ctypes.c_bool,1), + ('maximally_reconverges', ctypes.c_bool,1), + ('use_aco_amd', ctypes.c_bool,1), + ('use_lowered_image_to_global', ctypes.c_bool,1), + ('use_legacy_math_rules', ctypes.c_bool), + ('derivative_group', enum_gl_derivative_group,2), + ('_0', struct_shader_info_0), +] +class struct_nir_xfb_info(Struct): pass +nir_xfb_info = struct_nir_xfb_info +struct_nir_shader._fields_ = [ + ('gctx', ctypes.POINTER(gc_ctx)), + ('variables', struct_exec_list), + ('options', ctypes.POINTER(nir_shader_compiler_options)), + ('info', struct_shader_info), + ('functions', struct_exec_list), + ('num_inputs', ctypes.c_uint32), + ('num_uniforms', ctypes.c_uint32), + ('num_outputs', ctypes.c_uint32), + ('global_mem_size', ctypes.c_uint32), + ('scratch_size', ctypes.c_uint32), + ('constant_data', ctypes.c_void_p), + ('constant_data_size', ctypes.c_uint32), + ('xfb_info', ctypes.POINTER(nir_xfb_info)), + ('printf_info_count', ctypes.c_uint32), + ('printf_info', ctypes.POINTER(u_printf_info)), + ('has_debug_info', ctypes.c_bool), +] +class struct_nir_parameter(Struct): pass +nir_parameter = struct_nir_parameter +struct_nir_parameter._fields_ = [ + ('num_components', uint8_t), + ('bit_size', uint8_t), + ('is_return', ctypes.c_bool), + ('implicit_conversion_prohibited', ctypes.c_bool), + ('is_uniform', ctypes.c_bool), + ('mode', nir_variable_mode), + ('driver_attributes', uint32_t), + ('type', ctypes.POINTER(struct_glsl_type)), + ('name', ctypes.POINTER(ctypes.c_char)), +] +class struct_nir_function_impl(Struct): pass +nir_function_impl = struct_nir_function_impl +nir_function = struct_nir_function +nir_metadata = CEnum(ctypes.c_int32) +nir_metadata_none = nir_metadata.define('nir_metadata_none', 0) +nir_metadata_block_index = nir_metadata.define('nir_metadata_block_index', 1) +nir_metadata_dominance = nir_metadata.define('nir_metadata_dominance', 2) +nir_metadata_live_defs = nir_metadata.define('nir_metadata_live_defs', 4) +nir_metadata_not_properly_reset = nir_metadata.define('nir_metadata_not_properly_reset', 8) +nir_metadata_loop_analysis = nir_metadata.define('nir_metadata_loop_analysis', 16) +nir_metadata_instr_index = nir_metadata.define('nir_metadata_instr_index', 32) +nir_metadata_divergence = nir_metadata.define('nir_metadata_divergence', 64) +nir_metadata_control_flow = nir_metadata.define('nir_metadata_control_flow', 3) +nir_metadata_all = nir_metadata.define('nir_metadata_all', -9) + +struct_nir_function_impl._fields_ = [ + ('cf_node', nir_cf_node), + ('function', ctypes.POINTER(nir_function)), + ('preamble', ctypes.POINTER(nir_function)), + ('body', struct_exec_list), + ('end_block', ctypes.POINTER(nir_block)), + ('locals', struct_exec_list), + ('ssa_alloc', ctypes.c_uint32), + ('num_blocks', ctypes.c_uint32), + ('structured', ctypes.c_bool), + ('valid_metadata', nir_metadata), + ('loop_analysis_indirect_mask', nir_variable_mode), + ('loop_analysis_force_unroll_sampler_indirect', ctypes.c_bool), +] +struct_nir_function._fields_ = [ + ('node', struct_exec_node), + ('name', ctypes.POINTER(ctypes.c_char)), + ('shader', ctypes.POINTER(nir_shader)), + ('num_params', ctypes.c_uint32), + ('params', ctypes.POINTER(nir_parameter)), + ('impl', ctypes.POINTER(nir_function_impl)), + ('driver_attributes', uint32_t), + ('is_entrypoint', ctypes.c_bool), + ('is_exported', ctypes.c_bool), + ('is_preamble', ctypes.c_bool), + ('should_inline', ctypes.c_bool), + ('dont_inline', ctypes.c_bool), + ('workgroup_size', (ctypes.c_uint32 * 3)), + ('is_subroutine', ctypes.c_bool), + ('is_tmp_globals_wrapper', ctypes.c_bool), + ('num_subroutine_types', ctypes.c_int32), + ('subroutine_types', ctypes.POINTER(ctypes.POINTER(struct_glsl_type))), + ('subroutine_index', ctypes.c_int32), + ('pass_flags', uint32_t), +] +struct_nir_call_instr._fields_ = [ + ('instr', nir_instr), + ('callee', ctypes.POINTER(nir_function)), + ('indirect_callee', nir_src), + ('num_params', ctypes.c_uint32), + ('params', (nir_src * 0)), +] +nir_call_instr = struct_nir_call_instr +class struct_nir_intrinsic_instr(Struct): pass +nir_intrinsic_op = CEnum(ctypes.c_uint32) +nir_intrinsic_accept_ray_intersection = nir_intrinsic_op.define('nir_intrinsic_accept_ray_intersection', 0) +nir_intrinsic_addr_mode_is = nir_intrinsic_op.define('nir_intrinsic_addr_mode_is', 1) +nir_intrinsic_al2p_nv = nir_intrinsic_op.define('nir_intrinsic_al2p_nv', 2) +nir_intrinsic_ald_nv = nir_intrinsic_op.define('nir_intrinsic_ald_nv', 3) +nir_intrinsic_alpha_to_coverage = nir_intrinsic_op.define('nir_intrinsic_alpha_to_coverage', 4) +nir_intrinsic_as_uniform = nir_intrinsic_op.define('nir_intrinsic_as_uniform', 5) +nir_intrinsic_ast_nv = nir_intrinsic_op.define('nir_intrinsic_ast_nv', 6) +nir_intrinsic_atomic_add_gen_prim_count_amd = nir_intrinsic_op.define('nir_intrinsic_atomic_add_gen_prim_count_amd', 7) +nir_intrinsic_atomic_add_gs_emit_prim_count_amd = nir_intrinsic_op.define('nir_intrinsic_atomic_add_gs_emit_prim_count_amd', 8) +nir_intrinsic_atomic_add_shader_invocation_count_amd = nir_intrinsic_op.define('nir_intrinsic_atomic_add_shader_invocation_count_amd', 9) +nir_intrinsic_atomic_add_xfb_prim_count_amd = nir_intrinsic_op.define('nir_intrinsic_atomic_add_xfb_prim_count_amd', 10) +nir_intrinsic_atomic_counter_add = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_add', 11) +nir_intrinsic_atomic_counter_add_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_add_deref', 12) +nir_intrinsic_atomic_counter_and = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_and', 13) +nir_intrinsic_atomic_counter_and_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_and_deref', 14) +nir_intrinsic_atomic_counter_comp_swap = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_comp_swap', 15) +nir_intrinsic_atomic_counter_comp_swap_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_comp_swap_deref', 16) +nir_intrinsic_atomic_counter_exchange = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_exchange', 17) +nir_intrinsic_atomic_counter_exchange_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_exchange_deref', 18) +nir_intrinsic_atomic_counter_inc = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_inc', 19) +nir_intrinsic_atomic_counter_inc_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_inc_deref', 20) +nir_intrinsic_atomic_counter_max = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_max', 21) +nir_intrinsic_atomic_counter_max_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_max_deref', 22) +nir_intrinsic_atomic_counter_min = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_min', 23) +nir_intrinsic_atomic_counter_min_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_min_deref', 24) +nir_intrinsic_atomic_counter_or = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_or', 25) +nir_intrinsic_atomic_counter_or_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_or_deref', 26) +nir_intrinsic_atomic_counter_post_dec = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_post_dec', 27) +nir_intrinsic_atomic_counter_post_dec_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_post_dec_deref', 28) +nir_intrinsic_atomic_counter_pre_dec = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_pre_dec', 29) +nir_intrinsic_atomic_counter_pre_dec_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_pre_dec_deref', 30) +nir_intrinsic_atomic_counter_read = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_read', 31) +nir_intrinsic_atomic_counter_read_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_read_deref', 32) +nir_intrinsic_atomic_counter_xor = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_xor', 33) +nir_intrinsic_atomic_counter_xor_deref = nir_intrinsic_op.define('nir_intrinsic_atomic_counter_xor_deref', 34) +nir_intrinsic_ballot = nir_intrinsic_op.define('nir_intrinsic_ballot', 35) +nir_intrinsic_ballot_bit_count_exclusive = nir_intrinsic_op.define('nir_intrinsic_ballot_bit_count_exclusive', 36) +nir_intrinsic_ballot_bit_count_inclusive = nir_intrinsic_op.define('nir_intrinsic_ballot_bit_count_inclusive', 37) +nir_intrinsic_ballot_bit_count_reduce = nir_intrinsic_op.define('nir_intrinsic_ballot_bit_count_reduce', 38) +nir_intrinsic_ballot_bitfield_extract = nir_intrinsic_op.define('nir_intrinsic_ballot_bitfield_extract', 39) +nir_intrinsic_ballot_find_lsb = nir_intrinsic_op.define('nir_intrinsic_ballot_find_lsb', 40) +nir_intrinsic_ballot_find_msb = nir_intrinsic_op.define('nir_intrinsic_ballot_find_msb', 41) +nir_intrinsic_ballot_relaxed = nir_intrinsic_op.define('nir_intrinsic_ballot_relaxed', 42) +nir_intrinsic_bar_break_nv = nir_intrinsic_op.define('nir_intrinsic_bar_break_nv', 43) +nir_intrinsic_bar_set_nv = nir_intrinsic_op.define('nir_intrinsic_bar_set_nv', 44) +nir_intrinsic_bar_sync_nv = nir_intrinsic_op.define('nir_intrinsic_bar_sync_nv', 45) +nir_intrinsic_barrier = nir_intrinsic_op.define('nir_intrinsic_barrier', 46) +nir_intrinsic_begin_invocation_interlock = nir_intrinsic_op.define('nir_intrinsic_begin_invocation_interlock', 47) +nir_intrinsic_bindgen_return = nir_intrinsic_op.define('nir_intrinsic_bindgen_return', 48) +nir_intrinsic_bindless_image_agx = nir_intrinsic_op.define('nir_intrinsic_bindless_image_agx', 49) +nir_intrinsic_bindless_image_atomic = nir_intrinsic_op.define('nir_intrinsic_bindless_image_atomic', 50) +nir_intrinsic_bindless_image_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_bindless_image_atomic_swap', 51) +nir_intrinsic_bindless_image_descriptor_amd = nir_intrinsic_op.define('nir_intrinsic_bindless_image_descriptor_amd', 52) +nir_intrinsic_bindless_image_format = nir_intrinsic_op.define('nir_intrinsic_bindless_image_format', 53) +nir_intrinsic_bindless_image_fragment_mask_load_amd = nir_intrinsic_op.define('nir_intrinsic_bindless_image_fragment_mask_load_amd', 54) +nir_intrinsic_bindless_image_levels = nir_intrinsic_op.define('nir_intrinsic_bindless_image_levels', 55) +nir_intrinsic_bindless_image_load = nir_intrinsic_op.define('nir_intrinsic_bindless_image_load', 56) +nir_intrinsic_bindless_image_load_raw_intel = nir_intrinsic_op.define('nir_intrinsic_bindless_image_load_raw_intel', 57) +nir_intrinsic_bindless_image_order = nir_intrinsic_op.define('nir_intrinsic_bindless_image_order', 58) +nir_intrinsic_bindless_image_samples = nir_intrinsic_op.define('nir_intrinsic_bindless_image_samples', 59) +nir_intrinsic_bindless_image_samples_identical = nir_intrinsic_op.define('nir_intrinsic_bindless_image_samples_identical', 60) +nir_intrinsic_bindless_image_size = nir_intrinsic_op.define('nir_intrinsic_bindless_image_size', 61) +nir_intrinsic_bindless_image_sparse_load = nir_intrinsic_op.define('nir_intrinsic_bindless_image_sparse_load', 62) +nir_intrinsic_bindless_image_store = nir_intrinsic_op.define('nir_intrinsic_bindless_image_store', 63) +nir_intrinsic_bindless_image_store_block_agx = nir_intrinsic_op.define('nir_intrinsic_bindless_image_store_block_agx', 64) +nir_intrinsic_bindless_image_store_raw_intel = nir_intrinsic_op.define('nir_intrinsic_bindless_image_store_raw_intel', 65) +nir_intrinsic_bindless_image_texel_address = nir_intrinsic_op.define('nir_intrinsic_bindless_image_texel_address', 66) +nir_intrinsic_bindless_resource_ir3 = nir_intrinsic_op.define('nir_intrinsic_bindless_resource_ir3', 67) +nir_intrinsic_brcst_active_ir3 = nir_intrinsic_op.define('nir_intrinsic_brcst_active_ir3', 68) +nir_intrinsic_btd_retire_intel = nir_intrinsic_op.define('nir_intrinsic_btd_retire_intel', 69) +nir_intrinsic_btd_spawn_intel = nir_intrinsic_op.define('nir_intrinsic_btd_spawn_intel', 70) +nir_intrinsic_btd_stack_push_intel = nir_intrinsic_op.define('nir_intrinsic_btd_stack_push_intel', 71) +nir_intrinsic_bvh64_intersect_ray_amd = nir_intrinsic_op.define('nir_intrinsic_bvh64_intersect_ray_amd', 72) +nir_intrinsic_bvh8_intersect_ray_amd = nir_intrinsic_op.define('nir_intrinsic_bvh8_intersect_ray_amd', 73) +nir_intrinsic_bvh_stack_rtn_amd = nir_intrinsic_op.define('nir_intrinsic_bvh_stack_rtn_amd', 74) +nir_intrinsic_cmat_binary_op = nir_intrinsic_op.define('nir_intrinsic_cmat_binary_op', 75) +nir_intrinsic_cmat_bitcast = nir_intrinsic_op.define('nir_intrinsic_cmat_bitcast', 76) +nir_intrinsic_cmat_construct = nir_intrinsic_op.define('nir_intrinsic_cmat_construct', 77) +nir_intrinsic_cmat_convert = nir_intrinsic_op.define('nir_intrinsic_cmat_convert', 78) +nir_intrinsic_cmat_copy = nir_intrinsic_op.define('nir_intrinsic_cmat_copy', 79) +nir_intrinsic_cmat_extract = nir_intrinsic_op.define('nir_intrinsic_cmat_extract', 80) +nir_intrinsic_cmat_insert = nir_intrinsic_op.define('nir_intrinsic_cmat_insert', 81) +nir_intrinsic_cmat_length = nir_intrinsic_op.define('nir_intrinsic_cmat_length', 82) +nir_intrinsic_cmat_load = nir_intrinsic_op.define('nir_intrinsic_cmat_load', 83) +nir_intrinsic_cmat_muladd = nir_intrinsic_op.define('nir_intrinsic_cmat_muladd', 84) +nir_intrinsic_cmat_muladd_amd = nir_intrinsic_op.define('nir_intrinsic_cmat_muladd_amd', 85) +nir_intrinsic_cmat_muladd_nv = nir_intrinsic_op.define('nir_intrinsic_cmat_muladd_nv', 86) +nir_intrinsic_cmat_scalar_op = nir_intrinsic_op.define('nir_intrinsic_cmat_scalar_op', 87) +nir_intrinsic_cmat_store = nir_intrinsic_op.define('nir_intrinsic_cmat_store', 88) +nir_intrinsic_cmat_transpose = nir_intrinsic_op.define('nir_intrinsic_cmat_transpose', 89) +nir_intrinsic_cmat_unary_op = nir_intrinsic_op.define('nir_intrinsic_cmat_unary_op', 90) +nir_intrinsic_convert_alu_types = nir_intrinsic_op.define('nir_intrinsic_convert_alu_types', 91) +nir_intrinsic_convert_cmat_intel = nir_intrinsic_op.define('nir_intrinsic_convert_cmat_intel', 92) +nir_intrinsic_copy_deref = nir_intrinsic_op.define('nir_intrinsic_copy_deref', 93) +nir_intrinsic_copy_fs_outputs_nv = nir_intrinsic_op.define('nir_intrinsic_copy_fs_outputs_nv', 94) +nir_intrinsic_copy_global_to_uniform_ir3 = nir_intrinsic_op.define('nir_intrinsic_copy_global_to_uniform_ir3', 95) +nir_intrinsic_copy_push_const_to_uniform_ir3 = nir_intrinsic_op.define('nir_intrinsic_copy_push_const_to_uniform_ir3', 96) +nir_intrinsic_copy_ubo_to_uniform_ir3 = nir_intrinsic_op.define('nir_intrinsic_copy_ubo_to_uniform_ir3', 97) +nir_intrinsic_ddx = nir_intrinsic_op.define('nir_intrinsic_ddx', 98) +nir_intrinsic_ddx_coarse = nir_intrinsic_op.define('nir_intrinsic_ddx_coarse', 99) +nir_intrinsic_ddx_fine = nir_intrinsic_op.define('nir_intrinsic_ddx_fine', 100) +nir_intrinsic_ddy = nir_intrinsic_op.define('nir_intrinsic_ddy', 101) +nir_intrinsic_ddy_coarse = nir_intrinsic_op.define('nir_intrinsic_ddy_coarse', 102) +nir_intrinsic_ddy_fine = nir_intrinsic_op.define('nir_intrinsic_ddy_fine', 103) +nir_intrinsic_debug_break = nir_intrinsic_op.define('nir_intrinsic_debug_break', 104) +nir_intrinsic_decl_reg = nir_intrinsic_op.define('nir_intrinsic_decl_reg', 105) +nir_intrinsic_demote = nir_intrinsic_op.define('nir_intrinsic_demote', 106) +nir_intrinsic_demote_if = nir_intrinsic_op.define('nir_intrinsic_demote_if', 107) +nir_intrinsic_demote_samples = nir_intrinsic_op.define('nir_intrinsic_demote_samples', 108) +nir_intrinsic_deref_atomic = nir_intrinsic_op.define('nir_intrinsic_deref_atomic', 109) +nir_intrinsic_deref_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_deref_atomic_swap', 110) +nir_intrinsic_deref_buffer_array_length = nir_intrinsic_op.define('nir_intrinsic_deref_buffer_array_length', 111) +nir_intrinsic_deref_implicit_array_length = nir_intrinsic_op.define('nir_intrinsic_deref_implicit_array_length', 112) +nir_intrinsic_deref_mode_is = nir_intrinsic_op.define('nir_intrinsic_deref_mode_is', 113) +nir_intrinsic_deref_texture_src = nir_intrinsic_op.define('nir_intrinsic_deref_texture_src', 114) +nir_intrinsic_doorbell_agx = nir_intrinsic_op.define('nir_intrinsic_doorbell_agx', 115) +nir_intrinsic_dpas_intel = nir_intrinsic_op.define('nir_intrinsic_dpas_intel', 116) +nir_intrinsic_dpp16_shift_amd = nir_intrinsic_op.define('nir_intrinsic_dpp16_shift_amd', 117) +nir_intrinsic_elect = nir_intrinsic_op.define('nir_intrinsic_elect', 118) +nir_intrinsic_elect_any_ir3 = nir_intrinsic_op.define('nir_intrinsic_elect_any_ir3', 119) +nir_intrinsic_emit_primitive_poly = nir_intrinsic_op.define('nir_intrinsic_emit_primitive_poly', 120) +nir_intrinsic_emit_vertex = nir_intrinsic_op.define('nir_intrinsic_emit_vertex', 121) +nir_intrinsic_emit_vertex_nv = nir_intrinsic_op.define('nir_intrinsic_emit_vertex_nv', 122) +nir_intrinsic_emit_vertex_with_counter = nir_intrinsic_op.define('nir_intrinsic_emit_vertex_with_counter', 123) +nir_intrinsic_end_invocation_interlock = nir_intrinsic_op.define('nir_intrinsic_end_invocation_interlock', 124) +nir_intrinsic_end_primitive = nir_intrinsic_op.define('nir_intrinsic_end_primitive', 125) +nir_intrinsic_end_primitive_nv = nir_intrinsic_op.define('nir_intrinsic_end_primitive_nv', 126) +nir_intrinsic_end_primitive_with_counter = nir_intrinsic_op.define('nir_intrinsic_end_primitive_with_counter', 127) +nir_intrinsic_enqueue_node_payloads = nir_intrinsic_op.define('nir_intrinsic_enqueue_node_payloads', 128) +nir_intrinsic_exclusive_scan = nir_intrinsic_op.define('nir_intrinsic_exclusive_scan', 129) +nir_intrinsic_exclusive_scan_clusters_ir3 = nir_intrinsic_op.define('nir_intrinsic_exclusive_scan_clusters_ir3', 130) +nir_intrinsic_execute_callable = nir_intrinsic_op.define('nir_intrinsic_execute_callable', 131) +nir_intrinsic_execute_closest_hit_amd = nir_intrinsic_op.define('nir_intrinsic_execute_closest_hit_amd', 132) +nir_intrinsic_execute_miss_amd = nir_intrinsic_op.define('nir_intrinsic_execute_miss_amd', 133) +nir_intrinsic_export_agx = nir_intrinsic_op.define('nir_intrinsic_export_agx', 134) +nir_intrinsic_export_amd = nir_intrinsic_op.define('nir_intrinsic_export_amd', 135) +nir_intrinsic_export_dual_src_blend_amd = nir_intrinsic_op.define('nir_intrinsic_export_dual_src_blend_amd', 136) +nir_intrinsic_export_row_amd = nir_intrinsic_op.define('nir_intrinsic_export_row_amd', 137) +nir_intrinsic_fence_helper_exit_agx = nir_intrinsic_op.define('nir_intrinsic_fence_helper_exit_agx', 138) +nir_intrinsic_fence_mem_to_tex_agx = nir_intrinsic_op.define('nir_intrinsic_fence_mem_to_tex_agx', 139) +nir_intrinsic_fence_pbe_to_tex_agx = nir_intrinsic_op.define('nir_intrinsic_fence_pbe_to_tex_agx', 140) +nir_intrinsic_fence_pbe_to_tex_pixel_agx = nir_intrinsic_op.define('nir_intrinsic_fence_pbe_to_tex_pixel_agx', 141) +nir_intrinsic_final_primitive_nv = nir_intrinsic_op.define('nir_intrinsic_final_primitive_nv', 142) +nir_intrinsic_finalize_incoming_node_payload = nir_intrinsic_op.define('nir_intrinsic_finalize_incoming_node_payload', 143) +nir_intrinsic_first_invocation = nir_intrinsic_op.define('nir_intrinsic_first_invocation', 144) +nir_intrinsic_fs_out_nv = nir_intrinsic_op.define('nir_intrinsic_fs_out_nv', 145) +nir_intrinsic_gds_atomic_add_amd = nir_intrinsic_op.define('nir_intrinsic_gds_atomic_add_amd', 146) +nir_intrinsic_get_ssbo_size = nir_intrinsic_op.define('nir_intrinsic_get_ssbo_size', 147) +nir_intrinsic_get_ubo_size = nir_intrinsic_op.define('nir_intrinsic_get_ubo_size', 148) +nir_intrinsic_global_atomic = nir_intrinsic_op.define('nir_intrinsic_global_atomic', 149) +nir_intrinsic_global_atomic_2x32 = nir_intrinsic_op.define('nir_intrinsic_global_atomic_2x32', 150) +nir_intrinsic_global_atomic_agx = nir_intrinsic_op.define('nir_intrinsic_global_atomic_agx', 151) +nir_intrinsic_global_atomic_amd = nir_intrinsic_op.define('nir_intrinsic_global_atomic_amd', 152) +nir_intrinsic_global_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_global_atomic_swap', 153) +nir_intrinsic_global_atomic_swap_2x32 = nir_intrinsic_op.define('nir_intrinsic_global_atomic_swap_2x32', 154) +nir_intrinsic_global_atomic_swap_agx = nir_intrinsic_op.define('nir_intrinsic_global_atomic_swap_agx', 155) +nir_intrinsic_global_atomic_swap_amd = nir_intrinsic_op.define('nir_intrinsic_global_atomic_swap_amd', 156) +nir_intrinsic_ignore_ray_intersection = nir_intrinsic_op.define('nir_intrinsic_ignore_ray_intersection', 157) +nir_intrinsic_imadsp_nv = nir_intrinsic_op.define('nir_intrinsic_imadsp_nv', 158) +nir_intrinsic_image_atomic = nir_intrinsic_op.define('nir_intrinsic_image_atomic', 159) +nir_intrinsic_image_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_image_atomic_swap', 160) +nir_intrinsic_image_deref_atomic = nir_intrinsic_op.define('nir_intrinsic_image_deref_atomic', 161) +nir_intrinsic_image_deref_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_image_deref_atomic_swap', 162) +nir_intrinsic_image_deref_descriptor_amd = nir_intrinsic_op.define('nir_intrinsic_image_deref_descriptor_amd', 163) +nir_intrinsic_image_deref_format = nir_intrinsic_op.define('nir_intrinsic_image_deref_format', 164) +nir_intrinsic_image_deref_fragment_mask_load_amd = nir_intrinsic_op.define('nir_intrinsic_image_deref_fragment_mask_load_amd', 165) +nir_intrinsic_image_deref_levels = nir_intrinsic_op.define('nir_intrinsic_image_deref_levels', 166) +nir_intrinsic_image_deref_load = nir_intrinsic_op.define('nir_intrinsic_image_deref_load', 167) +nir_intrinsic_image_deref_load_info_nv = nir_intrinsic_op.define('nir_intrinsic_image_deref_load_info_nv', 168) +nir_intrinsic_image_deref_load_param_intel = nir_intrinsic_op.define('nir_intrinsic_image_deref_load_param_intel', 169) +nir_intrinsic_image_deref_load_raw_intel = nir_intrinsic_op.define('nir_intrinsic_image_deref_load_raw_intel', 170) +nir_intrinsic_image_deref_order = nir_intrinsic_op.define('nir_intrinsic_image_deref_order', 171) +nir_intrinsic_image_deref_samples = nir_intrinsic_op.define('nir_intrinsic_image_deref_samples', 172) +nir_intrinsic_image_deref_samples_identical = nir_intrinsic_op.define('nir_intrinsic_image_deref_samples_identical', 173) +nir_intrinsic_image_deref_size = nir_intrinsic_op.define('nir_intrinsic_image_deref_size', 174) +nir_intrinsic_image_deref_sparse_load = nir_intrinsic_op.define('nir_intrinsic_image_deref_sparse_load', 175) +nir_intrinsic_image_deref_store = nir_intrinsic_op.define('nir_intrinsic_image_deref_store', 176) +nir_intrinsic_image_deref_store_block_agx = nir_intrinsic_op.define('nir_intrinsic_image_deref_store_block_agx', 177) +nir_intrinsic_image_deref_store_raw_intel = nir_intrinsic_op.define('nir_intrinsic_image_deref_store_raw_intel', 178) +nir_intrinsic_image_deref_texel_address = nir_intrinsic_op.define('nir_intrinsic_image_deref_texel_address', 179) +nir_intrinsic_image_descriptor_amd = nir_intrinsic_op.define('nir_intrinsic_image_descriptor_amd', 180) +nir_intrinsic_image_format = nir_intrinsic_op.define('nir_intrinsic_image_format', 181) +nir_intrinsic_image_fragment_mask_load_amd = nir_intrinsic_op.define('nir_intrinsic_image_fragment_mask_load_amd', 182) +nir_intrinsic_image_levels = nir_intrinsic_op.define('nir_intrinsic_image_levels', 183) +nir_intrinsic_image_load = nir_intrinsic_op.define('nir_intrinsic_image_load', 184) +nir_intrinsic_image_load_raw_intel = nir_intrinsic_op.define('nir_intrinsic_image_load_raw_intel', 185) +nir_intrinsic_image_order = nir_intrinsic_op.define('nir_intrinsic_image_order', 186) +nir_intrinsic_image_samples = nir_intrinsic_op.define('nir_intrinsic_image_samples', 187) +nir_intrinsic_image_samples_identical = nir_intrinsic_op.define('nir_intrinsic_image_samples_identical', 188) +nir_intrinsic_image_size = nir_intrinsic_op.define('nir_intrinsic_image_size', 189) +nir_intrinsic_image_sparse_load = nir_intrinsic_op.define('nir_intrinsic_image_sparse_load', 190) +nir_intrinsic_image_store = nir_intrinsic_op.define('nir_intrinsic_image_store', 191) +nir_intrinsic_image_store_block_agx = nir_intrinsic_op.define('nir_intrinsic_image_store_block_agx', 192) +nir_intrinsic_image_store_raw_intel = nir_intrinsic_op.define('nir_intrinsic_image_store_raw_intel', 193) +nir_intrinsic_image_texel_address = nir_intrinsic_op.define('nir_intrinsic_image_texel_address', 194) +nir_intrinsic_inclusive_scan = nir_intrinsic_op.define('nir_intrinsic_inclusive_scan', 195) +nir_intrinsic_inclusive_scan_clusters_ir3 = nir_intrinsic_op.define('nir_intrinsic_inclusive_scan_clusters_ir3', 196) +nir_intrinsic_initialize_node_payloads = nir_intrinsic_op.define('nir_intrinsic_initialize_node_payloads', 197) +nir_intrinsic_interp_deref_at_centroid = nir_intrinsic_op.define('nir_intrinsic_interp_deref_at_centroid', 198) +nir_intrinsic_interp_deref_at_offset = nir_intrinsic_op.define('nir_intrinsic_interp_deref_at_offset', 199) +nir_intrinsic_interp_deref_at_sample = nir_intrinsic_op.define('nir_intrinsic_interp_deref_at_sample', 200) +nir_intrinsic_interp_deref_at_vertex = nir_intrinsic_op.define('nir_intrinsic_interp_deref_at_vertex', 201) +nir_intrinsic_inverse_ballot = nir_intrinsic_op.define('nir_intrinsic_inverse_ballot', 202) +nir_intrinsic_ipa_nv = nir_intrinsic_op.define('nir_intrinsic_ipa_nv', 203) +nir_intrinsic_is_helper_invocation = nir_intrinsic_op.define('nir_intrinsic_is_helper_invocation', 204) +nir_intrinsic_is_sparse_resident_zink = nir_intrinsic_op.define('nir_intrinsic_is_sparse_resident_zink', 205) +nir_intrinsic_is_sparse_texels_resident = nir_intrinsic_op.define('nir_intrinsic_is_sparse_texels_resident', 206) +nir_intrinsic_is_subgroup_invocation_lt_amd = nir_intrinsic_op.define('nir_intrinsic_is_subgroup_invocation_lt_amd', 207) +nir_intrinsic_isberd_nv = nir_intrinsic_op.define('nir_intrinsic_isberd_nv', 208) +nir_intrinsic_lane_permute_16_amd = nir_intrinsic_op.define('nir_intrinsic_lane_permute_16_amd', 209) +nir_intrinsic_last_invocation = nir_intrinsic_op.define('nir_intrinsic_last_invocation', 210) +nir_intrinsic_launch_mesh_workgroups = nir_intrinsic_op.define('nir_intrinsic_launch_mesh_workgroups', 211) +nir_intrinsic_launch_mesh_workgroups_with_payload_deref = nir_intrinsic_op.define('nir_intrinsic_launch_mesh_workgroups_with_payload_deref', 212) +nir_intrinsic_ldc_nv = nir_intrinsic_op.define('nir_intrinsic_ldc_nv', 213) +nir_intrinsic_ldcx_nv = nir_intrinsic_op.define('nir_intrinsic_ldcx_nv', 214) +nir_intrinsic_ldtram_nv = nir_intrinsic_op.define('nir_intrinsic_ldtram_nv', 215) +nir_intrinsic_load_aa_line_width = nir_intrinsic_op.define('nir_intrinsic_load_aa_line_width', 216) +nir_intrinsic_load_accel_struct_amd = nir_intrinsic_op.define('nir_intrinsic_load_accel_struct_amd', 217) +nir_intrinsic_load_active_samples_agx = nir_intrinsic_op.define('nir_intrinsic_load_active_samples_agx', 218) +nir_intrinsic_load_active_subgroup_count_agx = nir_intrinsic_op.define('nir_intrinsic_load_active_subgroup_count_agx', 219) +nir_intrinsic_load_active_subgroup_invocation_agx = nir_intrinsic_op.define('nir_intrinsic_load_active_subgroup_invocation_agx', 220) +nir_intrinsic_load_agx = nir_intrinsic_op.define('nir_intrinsic_load_agx', 221) +nir_intrinsic_load_alpha_reference_amd = nir_intrinsic_op.define('nir_intrinsic_load_alpha_reference_amd', 222) +nir_intrinsic_load_api_sample_mask_agx = nir_intrinsic_op.define('nir_intrinsic_load_api_sample_mask_agx', 223) +nir_intrinsic_load_attrib_clamp_agx = nir_intrinsic_op.define('nir_intrinsic_load_attrib_clamp_agx', 224) +nir_intrinsic_load_attribute_pan = nir_intrinsic_op.define('nir_intrinsic_load_attribute_pan', 225) +nir_intrinsic_load_back_face_agx = nir_intrinsic_op.define('nir_intrinsic_load_back_face_agx', 226) +nir_intrinsic_load_barycentric_at_offset = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_at_offset', 227) +nir_intrinsic_load_barycentric_at_offset_nv = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_at_offset_nv', 228) +nir_intrinsic_load_barycentric_at_sample = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_at_sample', 229) +nir_intrinsic_load_barycentric_centroid = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_centroid', 230) +nir_intrinsic_load_barycentric_coord_at_offset = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_coord_at_offset', 231) +nir_intrinsic_load_barycentric_coord_at_sample = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_coord_at_sample', 232) +nir_intrinsic_load_barycentric_coord_centroid = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_coord_centroid', 233) +nir_intrinsic_load_barycentric_coord_pixel = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_coord_pixel', 234) +nir_intrinsic_load_barycentric_coord_sample = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_coord_sample', 235) +nir_intrinsic_load_barycentric_model = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_model', 236) +nir_intrinsic_load_barycentric_optimize_amd = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_optimize_amd', 237) +nir_intrinsic_load_barycentric_pixel = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_pixel', 238) +nir_intrinsic_load_barycentric_sample = nir_intrinsic_op.define('nir_intrinsic_load_barycentric_sample', 239) +nir_intrinsic_load_base_global_invocation_id = nir_intrinsic_op.define('nir_intrinsic_load_base_global_invocation_id', 240) +nir_intrinsic_load_base_instance = nir_intrinsic_op.define('nir_intrinsic_load_base_instance', 241) +nir_intrinsic_load_base_vertex = nir_intrinsic_op.define('nir_intrinsic_load_base_vertex', 242) +nir_intrinsic_load_base_workgroup_id = nir_intrinsic_op.define('nir_intrinsic_load_base_workgroup_id', 243) +nir_intrinsic_load_blend_const_color_a_float = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_a_float', 244) +nir_intrinsic_load_blend_const_color_aaaa8888_unorm = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_aaaa8888_unorm', 245) +nir_intrinsic_load_blend_const_color_b_float = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_b_float', 246) +nir_intrinsic_load_blend_const_color_g_float = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_g_float', 247) +nir_intrinsic_load_blend_const_color_r_float = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_r_float', 248) +nir_intrinsic_load_blend_const_color_rgba = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_rgba', 249) +nir_intrinsic_load_blend_const_color_rgba8888_unorm = nir_intrinsic_op.define('nir_intrinsic_load_blend_const_color_rgba8888_unorm', 250) +nir_intrinsic_load_btd_global_arg_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_btd_global_arg_addr_intel', 251) +nir_intrinsic_load_btd_local_arg_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_btd_local_arg_addr_intel', 252) +nir_intrinsic_load_btd_resume_sbt_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_btd_resume_sbt_addr_intel', 253) +nir_intrinsic_load_btd_shader_type_intel = nir_intrinsic_op.define('nir_intrinsic_load_btd_shader_type_intel', 254) +nir_intrinsic_load_btd_stack_id_intel = nir_intrinsic_op.define('nir_intrinsic_load_btd_stack_id_intel', 255) +nir_intrinsic_load_buffer_amd = nir_intrinsic_op.define('nir_intrinsic_load_buffer_amd', 256) +nir_intrinsic_load_callable_sbt_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_callable_sbt_addr_intel', 257) +nir_intrinsic_load_callable_sbt_stride_intel = nir_intrinsic_op.define('nir_intrinsic_load_callable_sbt_stride_intel', 258) +nir_intrinsic_load_clamp_vertex_color_amd = nir_intrinsic_op.define('nir_intrinsic_load_clamp_vertex_color_amd', 259) +nir_intrinsic_load_clip_half_line_width_amd = nir_intrinsic_op.define('nir_intrinsic_load_clip_half_line_width_amd', 260) +nir_intrinsic_load_clip_z_coeff_agx = nir_intrinsic_op.define('nir_intrinsic_load_clip_z_coeff_agx', 261) +nir_intrinsic_load_coalesced_input_count = nir_intrinsic_op.define('nir_intrinsic_load_coalesced_input_count', 262) +nir_intrinsic_load_coefficients_agx = nir_intrinsic_op.define('nir_intrinsic_load_coefficients_agx', 263) +nir_intrinsic_load_color0 = nir_intrinsic_op.define('nir_intrinsic_load_color0', 264) +nir_intrinsic_load_color1 = nir_intrinsic_op.define('nir_intrinsic_load_color1', 265) +nir_intrinsic_load_const_buf_base_addr_lvp = nir_intrinsic_op.define('nir_intrinsic_load_const_buf_base_addr_lvp', 266) +nir_intrinsic_load_const_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_const_ir3', 267) +nir_intrinsic_load_constant = nir_intrinsic_op.define('nir_intrinsic_load_constant', 268) +nir_intrinsic_load_constant_agx = nir_intrinsic_op.define('nir_intrinsic_load_constant_agx', 269) +nir_intrinsic_load_constant_base_ptr = nir_intrinsic_op.define('nir_intrinsic_load_constant_base_ptr', 270) +nir_intrinsic_load_converted_output_pan = nir_intrinsic_op.define('nir_intrinsic_load_converted_output_pan', 271) +nir_intrinsic_load_core_id_agx = nir_intrinsic_op.define('nir_intrinsic_load_core_id_agx', 272) +nir_intrinsic_load_cull_any_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_any_enabled_amd', 273) +nir_intrinsic_load_cull_back_face_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_back_face_enabled_amd', 274) +nir_intrinsic_load_cull_ccw_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_ccw_amd', 275) +nir_intrinsic_load_cull_front_face_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_front_face_enabled_amd', 276) +nir_intrinsic_load_cull_line_viewport_xy_scale_and_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_line_viewport_xy_scale_and_offset_amd', 277) +nir_intrinsic_load_cull_mask = nir_intrinsic_op.define('nir_intrinsic_load_cull_mask', 278) +nir_intrinsic_load_cull_mask_and_flags_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_mask_and_flags_amd', 279) +nir_intrinsic_load_cull_small_line_precision_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_small_line_precision_amd', 280) +nir_intrinsic_load_cull_small_lines_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_small_lines_enabled_amd', 281) +nir_intrinsic_load_cull_small_triangle_precision_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_small_triangle_precision_amd', 282) +nir_intrinsic_load_cull_small_triangles_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_small_triangles_enabled_amd', 283) +nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd', 284) +nir_intrinsic_load_debug_log_desc_amd = nir_intrinsic_op.define('nir_intrinsic_load_debug_log_desc_amd', 285) +nir_intrinsic_load_depth_never_agx = nir_intrinsic_op.define('nir_intrinsic_load_depth_never_agx', 286) +nir_intrinsic_load_deref = nir_intrinsic_op.define('nir_intrinsic_load_deref', 287) +nir_intrinsic_load_deref_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_deref_block_intel', 288) +nir_intrinsic_load_draw_id = nir_intrinsic_op.define('nir_intrinsic_load_draw_id', 289) +nir_intrinsic_load_esgs_vertex_stride_amd = nir_intrinsic_op.define('nir_intrinsic_load_esgs_vertex_stride_amd', 290) +nir_intrinsic_load_exported_agx = nir_intrinsic_op.define('nir_intrinsic_load_exported_agx', 291) +nir_intrinsic_load_fb_layers_v3d = nir_intrinsic_op.define('nir_intrinsic_load_fb_layers_v3d', 292) +nir_intrinsic_load_fbfetch_image_desc_amd = nir_intrinsic_op.define('nir_intrinsic_load_fbfetch_image_desc_amd', 293) +nir_intrinsic_load_fbfetch_image_fmask_desc_amd = nir_intrinsic_op.define('nir_intrinsic_load_fbfetch_image_fmask_desc_amd', 294) +nir_intrinsic_load_fep_w_v3d = nir_intrinsic_op.define('nir_intrinsic_load_fep_w_v3d', 295) +nir_intrinsic_load_first_vertex = nir_intrinsic_op.define('nir_intrinsic_load_first_vertex', 296) +nir_intrinsic_load_fixed_point_size_agx = nir_intrinsic_op.define('nir_intrinsic_load_fixed_point_size_agx', 297) +nir_intrinsic_load_flat_mask = nir_intrinsic_op.define('nir_intrinsic_load_flat_mask', 298) +nir_intrinsic_load_force_vrs_rates_amd = nir_intrinsic_op.define('nir_intrinsic_load_force_vrs_rates_amd', 299) +nir_intrinsic_load_frag_coord = nir_intrinsic_op.define('nir_intrinsic_load_frag_coord', 300) +nir_intrinsic_load_frag_coord_unscaled_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_frag_coord_unscaled_ir3', 301) +nir_intrinsic_load_frag_coord_w = nir_intrinsic_op.define('nir_intrinsic_load_frag_coord_w', 302) +nir_intrinsic_load_frag_coord_z = nir_intrinsic_op.define('nir_intrinsic_load_frag_coord_z', 303) +nir_intrinsic_load_frag_coord_zw_pan = nir_intrinsic_op.define('nir_intrinsic_load_frag_coord_zw_pan', 304) +nir_intrinsic_load_frag_invocation_count = nir_intrinsic_op.define('nir_intrinsic_load_frag_invocation_count', 305) +nir_intrinsic_load_frag_offset_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_frag_offset_ir3', 306) +nir_intrinsic_load_frag_shading_rate = nir_intrinsic_op.define('nir_intrinsic_load_frag_shading_rate', 307) +nir_intrinsic_load_frag_size = nir_intrinsic_op.define('nir_intrinsic_load_frag_size', 308) +nir_intrinsic_load_frag_size_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_frag_size_ir3', 309) +nir_intrinsic_load_from_texture_handle_agx = nir_intrinsic_op.define('nir_intrinsic_load_from_texture_handle_agx', 310) +nir_intrinsic_load_front_face = nir_intrinsic_op.define('nir_intrinsic_load_front_face', 311) +nir_intrinsic_load_front_face_fsign = nir_intrinsic_op.define('nir_intrinsic_load_front_face_fsign', 312) +nir_intrinsic_load_fs_input_interp_deltas = nir_intrinsic_op.define('nir_intrinsic_load_fs_input_interp_deltas', 313) +nir_intrinsic_load_fs_msaa_intel = nir_intrinsic_op.define('nir_intrinsic_load_fs_msaa_intel', 314) +nir_intrinsic_load_fully_covered = nir_intrinsic_op.define('nir_intrinsic_load_fully_covered', 315) +nir_intrinsic_load_geometry_param_buffer_poly = nir_intrinsic_op.define('nir_intrinsic_load_geometry_param_buffer_poly', 316) +nir_intrinsic_load_global = nir_intrinsic_op.define('nir_intrinsic_load_global', 317) +nir_intrinsic_load_global_2x32 = nir_intrinsic_op.define('nir_intrinsic_load_global_2x32', 318) +nir_intrinsic_load_global_amd = nir_intrinsic_op.define('nir_intrinsic_load_global_amd', 319) +nir_intrinsic_load_global_base_ptr = nir_intrinsic_op.define('nir_intrinsic_load_global_base_ptr', 320) +nir_intrinsic_load_global_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_global_block_intel', 321) +nir_intrinsic_load_global_bounded = nir_intrinsic_op.define('nir_intrinsic_load_global_bounded', 322) +nir_intrinsic_load_global_constant = nir_intrinsic_op.define('nir_intrinsic_load_global_constant', 323) +nir_intrinsic_load_global_constant_bounded = nir_intrinsic_op.define('nir_intrinsic_load_global_constant_bounded', 324) +nir_intrinsic_load_global_constant_offset = nir_intrinsic_op.define('nir_intrinsic_load_global_constant_offset', 325) +nir_intrinsic_load_global_constant_uniform_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_global_constant_uniform_block_intel', 326) +nir_intrinsic_load_global_etna = nir_intrinsic_op.define('nir_intrinsic_load_global_etna', 327) +nir_intrinsic_load_global_invocation_id = nir_intrinsic_op.define('nir_intrinsic_load_global_invocation_id', 328) +nir_intrinsic_load_global_invocation_index = nir_intrinsic_op.define('nir_intrinsic_load_global_invocation_index', 329) +nir_intrinsic_load_global_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_global_ir3', 330) +nir_intrinsic_load_global_size = nir_intrinsic_op.define('nir_intrinsic_load_global_size', 331) +nir_intrinsic_load_gs_header_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_gs_header_ir3', 332) +nir_intrinsic_load_gs_vertex_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_gs_vertex_offset_amd', 333) +nir_intrinsic_load_gs_wave_id_amd = nir_intrinsic_op.define('nir_intrinsic_load_gs_wave_id_amd', 334) +nir_intrinsic_load_helper_arg_hi_agx = nir_intrinsic_op.define('nir_intrinsic_load_helper_arg_hi_agx', 335) +nir_intrinsic_load_helper_arg_lo_agx = nir_intrinsic_op.define('nir_intrinsic_load_helper_arg_lo_agx', 336) +nir_intrinsic_load_helper_invocation = nir_intrinsic_op.define('nir_intrinsic_load_helper_invocation', 337) +nir_intrinsic_load_helper_op_id_agx = nir_intrinsic_op.define('nir_intrinsic_load_helper_op_id_agx', 338) +nir_intrinsic_load_hit_attrib_amd = nir_intrinsic_op.define('nir_intrinsic_load_hit_attrib_amd', 339) +nir_intrinsic_load_hs_out_patch_data_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_hs_out_patch_data_offset_amd', 340) +nir_intrinsic_load_hs_patch_stride_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_hs_patch_stride_ir3', 341) +nir_intrinsic_load_initial_edgeflags_amd = nir_intrinsic_op.define('nir_intrinsic_load_initial_edgeflags_amd', 342) +nir_intrinsic_load_inline_data_intel = nir_intrinsic_op.define('nir_intrinsic_load_inline_data_intel', 343) +nir_intrinsic_load_input = nir_intrinsic_op.define('nir_intrinsic_load_input', 344) +nir_intrinsic_load_input_assembly_buffer_poly = nir_intrinsic_op.define('nir_intrinsic_load_input_assembly_buffer_poly', 345) +nir_intrinsic_load_input_attachment_conv_pan = nir_intrinsic_op.define('nir_intrinsic_load_input_attachment_conv_pan', 346) +nir_intrinsic_load_input_attachment_coord = nir_intrinsic_op.define('nir_intrinsic_load_input_attachment_coord', 347) +nir_intrinsic_load_input_attachment_target_pan = nir_intrinsic_op.define('nir_intrinsic_load_input_attachment_target_pan', 348) +nir_intrinsic_load_input_topology_poly = nir_intrinsic_op.define('nir_intrinsic_load_input_topology_poly', 349) +nir_intrinsic_load_input_vertex = nir_intrinsic_op.define('nir_intrinsic_load_input_vertex', 350) +nir_intrinsic_load_instance_id = nir_intrinsic_op.define('nir_intrinsic_load_instance_id', 351) +nir_intrinsic_load_interpolated_input = nir_intrinsic_op.define('nir_intrinsic_load_interpolated_input', 352) +nir_intrinsic_load_intersection_opaque_amd = nir_intrinsic_op.define('nir_intrinsic_load_intersection_opaque_amd', 353) +nir_intrinsic_load_invocation_id = nir_intrinsic_op.define('nir_intrinsic_load_invocation_id', 354) +nir_intrinsic_load_is_first_fan_agx = nir_intrinsic_op.define('nir_intrinsic_load_is_first_fan_agx', 355) +nir_intrinsic_load_is_indexed_draw = nir_intrinsic_op.define('nir_intrinsic_load_is_indexed_draw', 356) +nir_intrinsic_load_kernel_input = nir_intrinsic_op.define('nir_intrinsic_load_kernel_input', 357) +nir_intrinsic_load_layer_id = nir_intrinsic_op.define('nir_intrinsic_load_layer_id', 358) +nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd = nir_intrinsic_op.define('nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd', 359) +nir_intrinsic_load_leaf_opaque_intel = nir_intrinsic_op.define('nir_intrinsic_load_leaf_opaque_intel', 360) +nir_intrinsic_load_leaf_procedural_intel = nir_intrinsic_op.define('nir_intrinsic_load_leaf_procedural_intel', 361) +nir_intrinsic_load_line_coord = nir_intrinsic_op.define('nir_intrinsic_load_line_coord', 362) +nir_intrinsic_load_line_width = nir_intrinsic_op.define('nir_intrinsic_load_line_width', 363) +nir_intrinsic_load_local_invocation_id = nir_intrinsic_op.define('nir_intrinsic_load_local_invocation_id', 364) +nir_intrinsic_load_local_invocation_index = nir_intrinsic_op.define('nir_intrinsic_load_local_invocation_index', 365) +nir_intrinsic_load_local_pixel_agx = nir_intrinsic_op.define('nir_intrinsic_load_local_pixel_agx', 366) +nir_intrinsic_load_local_shared_r600 = nir_intrinsic_op.define('nir_intrinsic_load_local_shared_r600', 367) +nir_intrinsic_load_lshs_vertex_stride_amd = nir_intrinsic_op.define('nir_intrinsic_load_lshs_vertex_stride_amd', 368) +nir_intrinsic_load_max_polygon_intel = nir_intrinsic_op.define('nir_intrinsic_load_max_polygon_intel', 369) +nir_intrinsic_load_merged_wave_info_amd = nir_intrinsic_op.define('nir_intrinsic_load_merged_wave_info_amd', 370) +nir_intrinsic_load_mesh_view_count = nir_intrinsic_op.define('nir_intrinsic_load_mesh_view_count', 371) +nir_intrinsic_load_mesh_view_indices = nir_intrinsic_op.define('nir_intrinsic_load_mesh_view_indices', 372) +nir_intrinsic_load_multisampled_pan = nir_intrinsic_op.define('nir_intrinsic_load_multisampled_pan', 373) +nir_intrinsic_load_noperspective_varyings_pan = nir_intrinsic_op.define('nir_intrinsic_load_noperspective_varyings_pan', 374) +nir_intrinsic_load_num_subgroups = nir_intrinsic_op.define('nir_intrinsic_load_num_subgroups', 375) +nir_intrinsic_load_num_vertices = nir_intrinsic_op.define('nir_intrinsic_load_num_vertices', 376) +nir_intrinsic_load_num_vertices_per_primitive_amd = nir_intrinsic_op.define('nir_intrinsic_load_num_vertices_per_primitive_amd', 377) +nir_intrinsic_load_num_workgroups = nir_intrinsic_op.define('nir_intrinsic_load_num_workgroups', 378) +nir_intrinsic_load_ordered_id_amd = nir_intrinsic_op.define('nir_intrinsic_load_ordered_id_amd', 379) +nir_intrinsic_load_output = nir_intrinsic_op.define('nir_intrinsic_load_output', 380) +nir_intrinsic_load_packed_passthrough_primitive_amd = nir_intrinsic_op.define('nir_intrinsic_load_packed_passthrough_primitive_amd', 381) +nir_intrinsic_load_param = nir_intrinsic_op.define('nir_intrinsic_load_param', 382) +nir_intrinsic_load_patch_vertices_in = nir_intrinsic_op.define('nir_intrinsic_load_patch_vertices_in', 383) +nir_intrinsic_load_per_primitive_input = nir_intrinsic_op.define('nir_intrinsic_load_per_primitive_input', 384) +nir_intrinsic_load_per_primitive_output = nir_intrinsic_op.define('nir_intrinsic_load_per_primitive_output', 385) +nir_intrinsic_load_per_primitive_remap_intel = nir_intrinsic_op.define('nir_intrinsic_load_per_primitive_remap_intel', 386) +nir_intrinsic_load_per_vertex_input = nir_intrinsic_op.define('nir_intrinsic_load_per_vertex_input', 387) +nir_intrinsic_load_per_vertex_output = nir_intrinsic_op.define('nir_intrinsic_load_per_vertex_output', 388) +nir_intrinsic_load_per_view_output = nir_intrinsic_op.define('nir_intrinsic_load_per_view_output', 389) +nir_intrinsic_load_persp_center_rhw_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_persp_center_rhw_ir3', 390) +nir_intrinsic_load_pipeline_stat_query_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_pipeline_stat_query_enabled_amd', 391) +nir_intrinsic_load_pixel_coord = nir_intrinsic_op.define('nir_intrinsic_load_pixel_coord', 392) +nir_intrinsic_load_point_coord = nir_intrinsic_op.define('nir_intrinsic_load_point_coord', 393) +nir_intrinsic_load_point_coord_maybe_flipped = nir_intrinsic_op.define('nir_intrinsic_load_point_coord_maybe_flipped', 394) +nir_intrinsic_load_poly_line_smooth_enabled = nir_intrinsic_op.define('nir_intrinsic_load_poly_line_smooth_enabled', 395) +nir_intrinsic_load_polygon_stipple_agx = nir_intrinsic_op.define('nir_intrinsic_load_polygon_stipple_agx', 396) +nir_intrinsic_load_polygon_stipple_buffer_amd = nir_intrinsic_op.define('nir_intrinsic_load_polygon_stipple_buffer_amd', 397) +nir_intrinsic_load_preamble = nir_intrinsic_op.define('nir_intrinsic_load_preamble', 398) +nir_intrinsic_load_prim_gen_query_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_prim_gen_query_enabled_amd', 399) +nir_intrinsic_load_prim_xfb_query_enabled_amd = nir_intrinsic_op.define('nir_intrinsic_load_prim_xfb_query_enabled_amd', 400) +nir_intrinsic_load_primitive_id = nir_intrinsic_op.define('nir_intrinsic_load_primitive_id', 401) +nir_intrinsic_load_primitive_location_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_primitive_location_ir3', 402) +nir_intrinsic_load_printf_buffer_address = nir_intrinsic_op.define('nir_intrinsic_load_printf_buffer_address', 403) +nir_intrinsic_load_printf_buffer_size = nir_intrinsic_op.define('nir_intrinsic_load_printf_buffer_size', 404) +nir_intrinsic_load_provoking_last = nir_intrinsic_op.define('nir_intrinsic_load_provoking_last', 405) +nir_intrinsic_load_provoking_vtx_amd = nir_intrinsic_op.define('nir_intrinsic_load_provoking_vtx_amd', 406) +nir_intrinsic_load_provoking_vtx_in_prim_amd = nir_intrinsic_op.define('nir_intrinsic_load_provoking_vtx_in_prim_amd', 407) +nir_intrinsic_load_push_constant = nir_intrinsic_op.define('nir_intrinsic_load_push_constant', 408) +nir_intrinsic_load_push_constant_zink = nir_intrinsic_op.define('nir_intrinsic_load_push_constant_zink', 409) +nir_intrinsic_load_r600_indirect_per_vertex_input = nir_intrinsic_op.define('nir_intrinsic_load_r600_indirect_per_vertex_input', 410) +nir_intrinsic_load_rasterization_primitive_amd = nir_intrinsic_op.define('nir_intrinsic_load_rasterization_primitive_amd', 411) +nir_intrinsic_load_rasterization_samples_amd = nir_intrinsic_op.define('nir_intrinsic_load_rasterization_samples_amd', 412) +nir_intrinsic_load_rasterization_stream = nir_intrinsic_op.define('nir_intrinsic_load_rasterization_stream', 413) +nir_intrinsic_load_raw_output_pan = nir_intrinsic_op.define('nir_intrinsic_load_raw_output_pan', 414) +nir_intrinsic_load_raw_vertex_id_pan = nir_intrinsic_op.define('nir_intrinsic_load_raw_vertex_id_pan', 415) +nir_intrinsic_load_raw_vertex_offset_pan = nir_intrinsic_op.define('nir_intrinsic_load_raw_vertex_offset_pan', 416) +nir_intrinsic_load_ray_base_mem_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_base_mem_addr_intel', 417) +nir_intrinsic_load_ray_flags = nir_intrinsic_op.define('nir_intrinsic_load_ray_flags', 418) +nir_intrinsic_load_ray_geometry_index = nir_intrinsic_op.define('nir_intrinsic_load_ray_geometry_index', 419) +nir_intrinsic_load_ray_hit_kind = nir_intrinsic_op.define('nir_intrinsic_load_ray_hit_kind', 420) +nir_intrinsic_load_ray_hit_sbt_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_hit_sbt_addr_intel', 421) +nir_intrinsic_load_ray_hit_sbt_stride_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_hit_sbt_stride_intel', 422) +nir_intrinsic_load_ray_hw_stack_size_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_hw_stack_size_intel', 423) +nir_intrinsic_load_ray_instance_custom_index = nir_intrinsic_op.define('nir_intrinsic_load_ray_instance_custom_index', 424) +nir_intrinsic_load_ray_launch_id = nir_intrinsic_op.define('nir_intrinsic_load_ray_launch_id', 425) +nir_intrinsic_load_ray_launch_size = nir_intrinsic_op.define('nir_intrinsic_load_ray_launch_size', 426) +nir_intrinsic_load_ray_miss_sbt_addr_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_miss_sbt_addr_intel', 427) +nir_intrinsic_load_ray_miss_sbt_stride_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_miss_sbt_stride_intel', 428) +nir_intrinsic_load_ray_num_dss_rt_stacks_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_num_dss_rt_stacks_intel', 429) +nir_intrinsic_load_ray_object_direction = nir_intrinsic_op.define('nir_intrinsic_load_ray_object_direction', 430) +nir_intrinsic_load_ray_object_origin = nir_intrinsic_op.define('nir_intrinsic_load_ray_object_origin', 431) +nir_intrinsic_load_ray_object_to_world = nir_intrinsic_op.define('nir_intrinsic_load_ray_object_to_world', 432) +nir_intrinsic_load_ray_query_global_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_query_global_intel', 433) +nir_intrinsic_load_ray_sw_stack_size_intel = nir_intrinsic_op.define('nir_intrinsic_load_ray_sw_stack_size_intel', 434) +nir_intrinsic_load_ray_t_max = nir_intrinsic_op.define('nir_intrinsic_load_ray_t_max', 435) +nir_intrinsic_load_ray_t_min = nir_intrinsic_op.define('nir_intrinsic_load_ray_t_min', 436) +nir_intrinsic_load_ray_tracing_stack_base_lvp = nir_intrinsic_op.define('nir_intrinsic_load_ray_tracing_stack_base_lvp', 437) +nir_intrinsic_load_ray_triangle_vertex_positions = nir_intrinsic_op.define('nir_intrinsic_load_ray_triangle_vertex_positions', 438) +nir_intrinsic_load_ray_world_direction = nir_intrinsic_op.define('nir_intrinsic_load_ray_world_direction', 439) +nir_intrinsic_load_ray_world_origin = nir_intrinsic_op.define('nir_intrinsic_load_ray_world_origin', 440) +nir_intrinsic_load_ray_world_to_object = nir_intrinsic_op.define('nir_intrinsic_load_ray_world_to_object', 441) +nir_intrinsic_load_readonly_output_pan = nir_intrinsic_op.define('nir_intrinsic_load_readonly_output_pan', 442) +nir_intrinsic_load_reg = nir_intrinsic_op.define('nir_intrinsic_load_reg', 443) +nir_intrinsic_load_reg_indirect = nir_intrinsic_op.define('nir_intrinsic_load_reg_indirect', 444) +nir_intrinsic_load_rel_patch_id_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_rel_patch_id_ir3', 445) +nir_intrinsic_load_reloc_const_intel = nir_intrinsic_op.define('nir_intrinsic_load_reloc_const_intel', 446) +nir_intrinsic_load_resume_shader_address_amd = nir_intrinsic_op.define('nir_intrinsic_load_resume_shader_address_amd', 447) +nir_intrinsic_load_ring_attr_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_attr_amd', 448) +nir_intrinsic_load_ring_attr_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_attr_offset_amd', 449) +nir_intrinsic_load_ring_es2gs_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_es2gs_offset_amd', 450) +nir_intrinsic_load_ring_esgs_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_esgs_amd', 451) +nir_intrinsic_load_ring_gs2vs_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_gs2vs_offset_amd', 452) +nir_intrinsic_load_ring_gsvs_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_gsvs_amd', 453) +nir_intrinsic_load_ring_mesh_scratch_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_mesh_scratch_amd', 454) +nir_intrinsic_load_ring_mesh_scratch_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_mesh_scratch_offset_amd', 455) +nir_intrinsic_load_ring_task_draw_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_task_draw_amd', 456) +nir_intrinsic_load_ring_task_payload_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_task_payload_amd', 457) +nir_intrinsic_load_ring_tess_factors_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_tess_factors_amd', 458) +nir_intrinsic_load_ring_tess_factors_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_tess_factors_offset_amd', 459) +nir_intrinsic_load_ring_tess_offchip_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_tess_offchip_amd', 460) +nir_intrinsic_load_ring_tess_offchip_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_ring_tess_offchip_offset_amd', 461) +nir_intrinsic_load_root_agx = nir_intrinsic_op.define('nir_intrinsic_load_root_agx', 462) +nir_intrinsic_load_rt_arg_scratch_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_rt_arg_scratch_offset_amd', 463) +nir_intrinsic_load_rt_conversion_pan = nir_intrinsic_op.define('nir_intrinsic_load_rt_conversion_pan', 464) +nir_intrinsic_load_sample_id = nir_intrinsic_op.define('nir_intrinsic_load_sample_id', 465) +nir_intrinsic_load_sample_id_no_per_sample = nir_intrinsic_op.define('nir_intrinsic_load_sample_id_no_per_sample', 466) +nir_intrinsic_load_sample_mask = nir_intrinsic_op.define('nir_intrinsic_load_sample_mask', 467) +nir_intrinsic_load_sample_mask_in = nir_intrinsic_op.define('nir_intrinsic_load_sample_mask_in', 468) +nir_intrinsic_load_sample_pos = nir_intrinsic_op.define('nir_intrinsic_load_sample_pos', 469) +nir_intrinsic_load_sample_pos_from_id = nir_intrinsic_op.define('nir_intrinsic_load_sample_pos_from_id', 470) +nir_intrinsic_load_sample_pos_or_center = nir_intrinsic_op.define('nir_intrinsic_load_sample_pos_or_center', 471) +nir_intrinsic_load_sample_positions_agx = nir_intrinsic_op.define('nir_intrinsic_load_sample_positions_agx', 472) +nir_intrinsic_load_sample_positions_amd = nir_intrinsic_op.define('nir_intrinsic_load_sample_positions_amd', 473) +nir_intrinsic_load_sample_positions_pan = nir_intrinsic_op.define('nir_intrinsic_load_sample_positions_pan', 474) +nir_intrinsic_load_sampler_handle_agx = nir_intrinsic_op.define('nir_intrinsic_load_sampler_handle_agx', 475) +nir_intrinsic_load_sampler_lod_parameters = nir_intrinsic_op.define('nir_intrinsic_load_sampler_lod_parameters', 476) +nir_intrinsic_load_samples_log2_agx = nir_intrinsic_op.define('nir_intrinsic_load_samples_log2_agx', 477) +nir_intrinsic_load_sbt_base_amd = nir_intrinsic_op.define('nir_intrinsic_load_sbt_base_amd', 478) +nir_intrinsic_load_sbt_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_sbt_offset_amd', 479) +nir_intrinsic_load_sbt_stride_amd = nir_intrinsic_op.define('nir_intrinsic_load_sbt_stride_amd', 480) +nir_intrinsic_load_scalar_arg_amd = nir_intrinsic_op.define('nir_intrinsic_load_scalar_arg_amd', 481) +nir_intrinsic_load_scratch = nir_intrinsic_op.define('nir_intrinsic_load_scratch', 482) +nir_intrinsic_load_scratch_base_ptr = nir_intrinsic_op.define('nir_intrinsic_load_scratch_base_ptr', 483) +nir_intrinsic_load_shader_call_data_offset_lvp = nir_intrinsic_op.define('nir_intrinsic_load_shader_call_data_offset_lvp', 484) +nir_intrinsic_load_shader_index = nir_intrinsic_op.define('nir_intrinsic_load_shader_index', 485) +nir_intrinsic_load_shader_output_pan = nir_intrinsic_op.define('nir_intrinsic_load_shader_output_pan', 486) +nir_intrinsic_load_shader_part_tests_zs_agx = nir_intrinsic_op.define('nir_intrinsic_load_shader_part_tests_zs_agx', 487) +nir_intrinsic_load_shader_record_ptr = nir_intrinsic_op.define('nir_intrinsic_load_shader_record_ptr', 488) +nir_intrinsic_load_shared = nir_intrinsic_op.define('nir_intrinsic_load_shared', 489) +nir_intrinsic_load_shared2_amd = nir_intrinsic_op.define('nir_intrinsic_load_shared2_amd', 490) +nir_intrinsic_load_shared_base_ptr = nir_intrinsic_op.define('nir_intrinsic_load_shared_base_ptr', 491) +nir_intrinsic_load_shared_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_shared_block_intel', 492) +nir_intrinsic_load_shared_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_shared_ir3', 493) +nir_intrinsic_load_shared_lock_nv = nir_intrinsic_op.define('nir_intrinsic_load_shared_lock_nv', 494) +nir_intrinsic_load_shared_uniform_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_shared_uniform_block_intel', 495) +nir_intrinsic_load_simd_width_intel = nir_intrinsic_op.define('nir_intrinsic_load_simd_width_intel', 496) +nir_intrinsic_load_sm_count_nv = nir_intrinsic_op.define('nir_intrinsic_load_sm_count_nv', 497) +nir_intrinsic_load_sm_id_nv = nir_intrinsic_op.define('nir_intrinsic_load_sm_id_nv', 498) +nir_intrinsic_load_smem_amd = nir_intrinsic_op.define('nir_intrinsic_load_smem_amd', 499) +nir_intrinsic_load_ssbo = nir_intrinsic_op.define('nir_intrinsic_load_ssbo', 500) +nir_intrinsic_load_ssbo_address = nir_intrinsic_op.define('nir_intrinsic_load_ssbo_address', 501) +nir_intrinsic_load_ssbo_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_ssbo_block_intel', 502) +nir_intrinsic_load_ssbo_intel = nir_intrinsic_op.define('nir_intrinsic_load_ssbo_intel', 503) +nir_intrinsic_load_ssbo_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_ssbo_ir3', 504) +nir_intrinsic_load_ssbo_uniform_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_ssbo_uniform_block_intel', 505) +nir_intrinsic_load_stack = nir_intrinsic_op.define('nir_intrinsic_load_stack', 506) +nir_intrinsic_load_stat_query_address_agx = nir_intrinsic_op.define('nir_intrinsic_load_stat_query_address_agx', 507) +nir_intrinsic_load_streamout_buffer_amd = nir_intrinsic_op.define('nir_intrinsic_load_streamout_buffer_amd', 508) +nir_intrinsic_load_streamout_config_amd = nir_intrinsic_op.define('nir_intrinsic_load_streamout_config_amd', 509) +nir_intrinsic_load_streamout_offset_amd = nir_intrinsic_op.define('nir_intrinsic_load_streamout_offset_amd', 510) +nir_intrinsic_load_streamout_write_index_amd = nir_intrinsic_op.define('nir_intrinsic_load_streamout_write_index_amd', 511) +nir_intrinsic_load_subgroup_eq_mask = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_eq_mask', 512) +nir_intrinsic_load_subgroup_ge_mask = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_ge_mask', 513) +nir_intrinsic_load_subgroup_gt_mask = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_gt_mask', 514) +nir_intrinsic_load_subgroup_id = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_id', 515) +nir_intrinsic_load_subgroup_id_shift_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_id_shift_ir3', 516) +nir_intrinsic_load_subgroup_invocation = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_invocation', 517) +nir_intrinsic_load_subgroup_le_mask = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_le_mask', 518) +nir_intrinsic_load_subgroup_lt_mask = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_lt_mask', 519) +nir_intrinsic_load_subgroup_size = nir_intrinsic_op.define('nir_intrinsic_load_subgroup_size', 520) +nir_intrinsic_load_sysval_agx = nir_intrinsic_op.define('nir_intrinsic_load_sysval_agx', 521) +nir_intrinsic_load_sysval_nv = nir_intrinsic_op.define('nir_intrinsic_load_sysval_nv', 522) +nir_intrinsic_load_task_payload = nir_intrinsic_op.define('nir_intrinsic_load_task_payload', 523) +nir_intrinsic_load_task_ring_entry_amd = nir_intrinsic_op.define('nir_intrinsic_load_task_ring_entry_amd', 524) +nir_intrinsic_load_tcs_header_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_tcs_header_ir3', 525) +nir_intrinsic_load_tcs_in_param_base_r600 = nir_intrinsic_op.define('nir_intrinsic_load_tcs_in_param_base_r600', 526) +nir_intrinsic_load_tcs_mem_attrib_stride = nir_intrinsic_op.define('nir_intrinsic_load_tcs_mem_attrib_stride', 527) +nir_intrinsic_load_tcs_num_patches_amd = nir_intrinsic_op.define('nir_intrinsic_load_tcs_num_patches_amd', 528) +nir_intrinsic_load_tcs_out_param_base_r600 = nir_intrinsic_op.define('nir_intrinsic_load_tcs_out_param_base_r600', 529) +nir_intrinsic_load_tcs_primitive_mode_amd = nir_intrinsic_op.define('nir_intrinsic_load_tcs_primitive_mode_amd', 530) +nir_intrinsic_load_tcs_rel_patch_id_r600 = nir_intrinsic_op.define('nir_intrinsic_load_tcs_rel_patch_id_r600', 531) +nir_intrinsic_load_tcs_tess_factor_base_r600 = nir_intrinsic_op.define('nir_intrinsic_load_tcs_tess_factor_base_r600', 532) +nir_intrinsic_load_tcs_tess_levels_to_tes_amd = nir_intrinsic_op.define('nir_intrinsic_load_tcs_tess_levels_to_tes_amd', 533) +nir_intrinsic_load_tess_coord = nir_intrinsic_op.define('nir_intrinsic_load_tess_coord', 534) +nir_intrinsic_load_tess_coord_xy = nir_intrinsic_op.define('nir_intrinsic_load_tess_coord_xy', 535) +nir_intrinsic_load_tess_factor_base_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_tess_factor_base_ir3', 536) +nir_intrinsic_load_tess_level_inner = nir_intrinsic_op.define('nir_intrinsic_load_tess_level_inner', 537) +nir_intrinsic_load_tess_level_inner_default = nir_intrinsic_op.define('nir_intrinsic_load_tess_level_inner_default', 538) +nir_intrinsic_load_tess_level_outer = nir_intrinsic_op.define('nir_intrinsic_load_tess_level_outer', 539) +nir_intrinsic_load_tess_level_outer_default = nir_intrinsic_op.define('nir_intrinsic_load_tess_level_outer_default', 540) +nir_intrinsic_load_tess_param_base_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_tess_param_base_ir3', 541) +nir_intrinsic_load_tess_param_buffer_poly = nir_intrinsic_op.define('nir_intrinsic_load_tess_param_buffer_poly', 542) +nir_intrinsic_load_tess_rel_patch_id_amd = nir_intrinsic_op.define('nir_intrinsic_load_tess_rel_patch_id_amd', 543) +nir_intrinsic_load_tex_sprite_mask_agx = nir_intrinsic_op.define('nir_intrinsic_load_tex_sprite_mask_agx', 544) +nir_intrinsic_load_texture_handle_agx = nir_intrinsic_op.define('nir_intrinsic_load_texture_handle_agx', 545) +nir_intrinsic_load_texture_scale = nir_intrinsic_op.define('nir_intrinsic_load_texture_scale', 546) +nir_intrinsic_load_texture_size_etna = nir_intrinsic_op.define('nir_intrinsic_load_texture_size_etna', 547) +nir_intrinsic_load_tlb_color_brcm = nir_intrinsic_op.define('nir_intrinsic_load_tlb_color_brcm', 548) +nir_intrinsic_load_topology_id_intel = nir_intrinsic_op.define('nir_intrinsic_load_topology_id_intel', 549) +nir_intrinsic_load_typed_buffer_amd = nir_intrinsic_op.define('nir_intrinsic_load_typed_buffer_amd', 550) +nir_intrinsic_load_uav_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_uav_ir3', 551) +nir_intrinsic_load_ubo = nir_intrinsic_op.define('nir_intrinsic_load_ubo', 552) +nir_intrinsic_load_ubo_uniform_block_intel = nir_intrinsic_op.define('nir_intrinsic_load_ubo_uniform_block_intel', 553) +nir_intrinsic_load_ubo_vec4 = nir_intrinsic_op.define('nir_intrinsic_load_ubo_vec4', 554) +nir_intrinsic_load_uniform = nir_intrinsic_op.define('nir_intrinsic_load_uniform', 555) +nir_intrinsic_load_user_clip_plane = nir_intrinsic_op.define('nir_intrinsic_load_user_clip_plane', 556) +nir_intrinsic_load_user_data_amd = nir_intrinsic_op.define('nir_intrinsic_load_user_data_amd', 557) +nir_intrinsic_load_uvs_index_agx = nir_intrinsic_op.define('nir_intrinsic_load_uvs_index_agx', 558) +nir_intrinsic_load_vbo_base_agx = nir_intrinsic_op.define('nir_intrinsic_load_vbo_base_agx', 559) +nir_intrinsic_load_vector_arg_amd = nir_intrinsic_op.define('nir_intrinsic_load_vector_arg_amd', 560) +nir_intrinsic_load_vertex_id = nir_intrinsic_op.define('nir_intrinsic_load_vertex_id', 561) +nir_intrinsic_load_vertex_id_zero_base = nir_intrinsic_op.define('nir_intrinsic_load_vertex_id_zero_base', 562) +nir_intrinsic_load_view_index = nir_intrinsic_op.define('nir_intrinsic_load_view_index', 563) +nir_intrinsic_load_viewport_offset = nir_intrinsic_op.define('nir_intrinsic_load_viewport_offset', 564) +nir_intrinsic_load_viewport_scale = nir_intrinsic_op.define('nir_intrinsic_load_viewport_scale', 565) +nir_intrinsic_load_viewport_x_offset = nir_intrinsic_op.define('nir_intrinsic_load_viewport_x_offset', 566) +nir_intrinsic_load_viewport_x_scale = nir_intrinsic_op.define('nir_intrinsic_load_viewport_x_scale', 567) +nir_intrinsic_load_viewport_y_offset = nir_intrinsic_op.define('nir_intrinsic_load_viewport_y_offset', 568) +nir_intrinsic_load_viewport_y_scale = nir_intrinsic_op.define('nir_intrinsic_load_viewport_y_scale', 569) +nir_intrinsic_load_viewport_z_offset = nir_intrinsic_op.define('nir_intrinsic_load_viewport_z_offset', 570) +nir_intrinsic_load_viewport_z_scale = nir_intrinsic_op.define('nir_intrinsic_load_viewport_z_scale', 571) +nir_intrinsic_load_vs_output_buffer_poly = nir_intrinsic_op.define('nir_intrinsic_load_vs_output_buffer_poly', 572) +nir_intrinsic_load_vs_outputs_poly = nir_intrinsic_op.define('nir_intrinsic_load_vs_outputs_poly', 573) +nir_intrinsic_load_vs_primitive_stride_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_vs_primitive_stride_ir3', 574) +nir_intrinsic_load_vs_vertex_stride_ir3 = nir_intrinsic_op.define('nir_intrinsic_load_vs_vertex_stride_ir3', 575) +nir_intrinsic_load_vulkan_descriptor = nir_intrinsic_op.define('nir_intrinsic_load_vulkan_descriptor', 576) +nir_intrinsic_load_warp_id_nv = nir_intrinsic_op.define('nir_intrinsic_load_warp_id_nv', 577) +nir_intrinsic_load_warps_per_sm_nv = nir_intrinsic_op.define('nir_intrinsic_load_warps_per_sm_nv', 578) +nir_intrinsic_load_work_dim = nir_intrinsic_op.define('nir_intrinsic_load_work_dim', 579) +nir_intrinsic_load_workgroup_id = nir_intrinsic_op.define('nir_intrinsic_load_workgroup_id', 580) +nir_intrinsic_load_workgroup_index = nir_intrinsic_op.define('nir_intrinsic_load_workgroup_index', 581) +nir_intrinsic_load_workgroup_num_input_primitives_amd = nir_intrinsic_op.define('nir_intrinsic_load_workgroup_num_input_primitives_amd', 582) +nir_intrinsic_load_workgroup_num_input_vertices_amd = nir_intrinsic_op.define('nir_intrinsic_load_workgroup_num_input_vertices_amd', 583) +nir_intrinsic_load_workgroup_size = nir_intrinsic_op.define('nir_intrinsic_load_workgroup_size', 584) +nir_intrinsic_load_xfb_address = nir_intrinsic_op.define('nir_intrinsic_load_xfb_address', 585) +nir_intrinsic_load_xfb_index_buffer = nir_intrinsic_op.define('nir_intrinsic_load_xfb_index_buffer', 586) +nir_intrinsic_load_xfb_size = nir_intrinsic_op.define('nir_intrinsic_load_xfb_size', 587) +nir_intrinsic_load_xfb_state_address_gfx12_amd = nir_intrinsic_op.define('nir_intrinsic_load_xfb_state_address_gfx12_amd', 588) +nir_intrinsic_masked_swizzle_amd = nir_intrinsic_op.define('nir_intrinsic_masked_swizzle_amd', 589) +nir_intrinsic_mbcnt_amd = nir_intrinsic_op.define('nir_intrinsic_mbcnt_amd', 590) +nir_intrinsic_memcpy_deref = nir_intrinsic_op.define('nir_intrinsic_memcpy_deref', 591) +nir_intrinsic_nop = nir_intrinsic_op.define('nir_intrinsic_nop', 592) +nir_intrinsic_nop_amd = nir_intrinsic_op.define('nir_intrinsic_nop_amd', 593) +nir_intrinsic_optimization_barrier_sgpr_amd = nir_intrinsic_op.define('nir_intrinsic_optimization_barrier_sgpr_amd', 594) +nir_intrinsic_optimization_barrier_vgpr_amd = nir_intrinsic_op.define('nir_intrinsic_optimization_barrier_vgpr_amd', 595) +nir_intrinsic_ordered_add_loop_gfx12_amd = nir_intrinsic_op.define('nir_intrinsic_ordered_add_loop_gfx12_amd', 596) +nir_intrinsic_ordered_xfb_counter_add_gfx11_amd = nir_intrinsic_op.define('nir_intrinsic_ordered_xfb_counter_add_gfx11_amd', 597) +nir_intrinsic_overwrite_tes_arguments_amd = nir_intrinsic_op.define('nir_intrinsic_overwrite_tes_arguments_amd', 598) +nir_intrinsic_overwrite_vs_arguments_amd = nir_intrinsic_op.define('nir_intrinsic_overwrite_vs_arguments_amd', 599) +nir_intrinsic_pin_cx_handle_nv = nir_intrinsic_op.define('nir_intrinsic_pin_cx_handle_nv', 600) +nir_intrinsic_preamble_end_ir3 = nir_intrinsic_op.define('nir_intrinsic_preamble_end_ir3', 601) +nir_intrinsic_preamble_start_ir3 = nir_intrinsic_op.define('nir_intrinsic_preamble_start_ir3', 602) +nir_intrinsic_prefetch_sam_ir3 = nir_intrinsic_op.define('nir_intrinsic_prefetch_sam_ir3', 603) +nir_intrinsic_prefetch_tex_ir3 = nir_intrinsic_op.define('nir_intrinsic_prefetch_tex_ir3', 604) +nir_intrinsic_prefetch_ubo_ir3 = nir_intrinsic_op.define('nir_intrinsic_prefetch_ubo_ir3', 605) +nir_intrinsic_printf = nir_intrinsic_op.define('nir_intrinsic_printf', 606) +nir_intrinsic_printf_abort = nir_intrinsic_op.define('nir_intrinsic_printf_abort', 607) +nir_intrinsic_quad_ballot_agx = nir_intrinsic_op.define('nir_intrinsic_quad_ballot_agx', 608) +nir_intrinsic_quad_broadcast = nir_intrinsic_op.define('nir_intrinsic_quad_broadcast', 609) +nir_intrinsic_quad_swap_diagonal = nir_intrinsic_op.define('nir_intrinsic_quad_swap_diagonal', 610) +nir_intrinsic_quad_swap_horizontal = nir_intrinsic_op.define('nir_intrinsic_quad_swap_horizontal', 611) +nir_intrinsic_quad_swap_vertical = nir_intrinsic_op.define('nir_intrinsic_quad_swap_vertical', 612) +nir_intrinsic_quad_swizzle_amd = nir_intrinsic_op.define('nir_intrinsic_quad_swizzle_amd', 613) +nir_intrinsic_quad_vote_all = nir_intrinsic_op.define('nir_intrinsic_quad_vote_all', 614) +nir_intrinsic_quad_vote_any = nir_intrinsic_op.define('nir_intrinsic_quad_vote_any', 615) +nir_intrinsic_r600_indirect_vertex_at_index = nir_intrinsic_op.define('nir_intrinsic_r600_indirect_vertex_at_index', 616) +nir_intrinsic_ray_intersection_ir3 = nir_intrinsic_op.define('nir_intrinsic_ray_intersection_ir3', 617) +nir_intrinsic_read_attribute_payload_intel = nir_intrinsic_op.define('nir_intrinsic_read_attribute_payload_intel', 618) +nir_intrinsic_read_first_invocation = nir_intrinsic_op.define('nir_intrinsic_read_first_invocation', 619) +nir_intrinsic_read_getlast_ir3 = nir_intrinsic_op.define('nir_intrinsic_read_getlast_ir3', 620) +nir_intrinsic_read_invocation = nir_intrinsic_op.define('nir_intrinsic_read_invocation', 621) +nir_intrinsic_read_invocation_cond_ir3 = nir_intrinsic_op.define('nir_intrinsic_read_invocation_cond_ir3', 622) +nir_intrinsic_reduce = nir_intrinsic_op.define('nir_intrinsic_reduce', 623) +nir_intrinsic_reduce_clusters_ir3 = nir_intrinsic_op.define('nir_intrinsic_reduce_clusters_ir3', 624) +nir_intrinsic_report_ray_intersection = nir_intrinsic_op.define('nir_intrinsic_report_ray_intersection', 625) +nir_intrinsic_resource_intel = nir_intrinsic_op.define('nir_intrinsic_resource_intel', 626) +nir_intrinsic_rotate = nir_intrinsic_op.define('nir_intrinsic_rotate', 627) +nir_intrinsic_rq_confirm_intersection = nir_intrinsic_op.define('nir_intrinsic_rq_confirm_intersection', 628) +nir_intrinsic_rq_generate_intersection = nir_intrinsic_op.define('nir_intrinsic_rq_generate_intersection', 629) +nir_intrinsic_rq_initialize = nir_intrinsic_op.define('nir_intrinsic_rq_initialize', 630) +nir_intrinsic_rq_load = nir_intrinsic_op.define('nir_intrinsic_rq_load', 631) +nir_intrinsic_rq_proceed = nir_intrinsic_op.define('nir_intrinsic_rq_proceed', 632) +nir_intrinsic_rq_terminate = nir_intrinsic_op.define('nir_intrinsic_rq_terminate', 633) +nir_intrinsic_rt_execute_callable = nir_intrinsic_op.define('nir_intrinsic_rt_execute_callable', 634) +nir_intrinsic_rt_resume = nir_intrinsic_op.define('nir_intrinsic_rt_resume', 635) +nir_intrinsic_rt_return_amd = nir_intrinsic_op.define('nir_intrinsic_rt_return_amd', 636) +nir_intrinsic_rt_trace_ray = nir_intrinsic_op.define('nir_intrinsic_rt_trace_ray', 637) +nir_intrinsic_sample_mask_agx = nir_intrinsic_op.define('nir_intrinsic_sample_mask_agx', 638) +nir_intrinsic_select_vertex_poly = nir_intrinsic_op.define('nir_intrinsic_select_vertex_poly', 639) +nir_intrinsic_sendmsg_amd = nir_intrinsic_op.define('nir_intrinsic_sendmsg_amd', 640) +nir_intrinsic_set_vertex_and_primitive_count = nir_intrinsic_op.define('nir_intrinsic_set_vertex_and_primitive_count', 641) +nir_intrinsic_shader_clock = nir_intrinsic_op.define('nir_intrinsic_shader_clock', 642) +nir_intrinsic_shared_append_amd = nir_intrinsic_op.define('nir_intrinsic_shared_append_amd', 643) +nir_intrinsic_shared_atomic = nir_intrinsic_op.define('nir_intrinsic_shared_atomic', 644) +nir_intrinsic_shared_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_shared_atomic_swap', 645) +nir_intrinsic_shared_consume_amd = nir_intrinsic_op.define('nir_intrinsic_shared_consume_amd', 646) +nir_intrinsic_shuffle = nir_intrinsic_op.define('nir_intrinsic_shuffle', 647) +nir_intrinsic_shuffle_down = nir_intrinsic_op.define('nir_intrinsic_shuffle_down', 648) +nir_intrinsic_shuffle_down_uniform_ir3 = nir_intrinsic_op.define('nir_intrinsic_shuffle_down_uniform_ir3', 649) +nir_intrinsic_shuffle_up = nir_intrinsic_op.define('nir_intrinsic_shuffle_up', 650) +nir_intrinsic_shuffle_up_uniform_ir3 = nir_intrinsic_op.define('nir_intrinsic_shuffle_up_uniform_ir3', 651) +nir_intrinsic_shuffle_xor = nir_intrinsic_op.define('nir_intrinsic_shuffle_xor', 652) +nir_intrinsic_shuffle_xor_uniform_ir3 = nir_intrinsic_op.define('nir_intrinsic_shuffle_xor_uniform_ir3', 653) +nir_intrinsic_sleep_amd = nir_intrinsic_op.define('nir_intrinsic_sleep_amd', 654) +nir_intrinsic_sparse_residency_code_and = nir_intrinsic_op.define('nir_intrinsic_sparse_residency_code_and', 655) +nir_intrinsic_ssa_bar_nv = nir_intrinsic_op.define('nir_intrinsic_ssa_bar_nv', 656) +nir_intrinsic_ssbo_atomic = nir_intrinsic_op.define('nir_intrinsic_ssbo_atomic', 657) +nir_intrinsic_ssbo_atomic_ir3 = nir_intrinsic_op.define('nir_intrinsic_ssbo_atomic_ir3', 658) +nir_intrinsic_ssbo_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_ssbo_atomic_swap', 659) +nir_intrinsic_ssbo_atomic_swap_ir3 = nir_intrinsic_op.define('nir_intrinsic_ssbo_atomic_swap_ir3', 660) +nir_intrinsic_stack_map_agx = nir_intrinsic_op.define('nir_intrinsic_stack_map_agx', 661) +nir_intrinsic_stack_unmap_agx = nir_intrinsic_op.define('nir_intrinsic_stack_unmap_agx', 662) +nir_intrinsic_store_agx = nir_intrinsic_op.define('nir_intrinsic_store_agx', 663) +nir_intrinsic_store_buffer_amd = nir_intrinsic_op.define('nir_intrinsic_store_buffer_amd', 664) +nir_intrinsic_store_combined_output_pan = nir_intrinsic_op.define('nir_intrinsic_store_combined_output_pan', 665) +nir_intrinsic_store_const_ir3 = nir_intrinsic_op.define('nir_intrinsic_store_const_ir3', 666) +nir_intrinsic_store_deref = nir_intrinsic_op.define('nir_intrinsic_store_deref', 667) +nir_intrinsic_store_deref_block_intel = nir_intrinsic_op.define('nir_intrinsic_store_deref_block_intel', 668) +nir_intrinsic_store_global = nir_intrinsic_op.define('nir_intrinsic_store_global', 669) +nir_intrinsic_store_global_2x32 = nir_intrinsic_op.define('nir_intrinsic_store_global_2x32', 670) +nir_intrinsic_store_global_amd = nir_intrinsic_op.define('nir_intrinsic_store_global_amd', 671) +nir_intrinsic_store_global_block_intel = nir_intrinsic_op.define('nir_intrinsic_store_global_block_intel', 672) +nir_intrinsic_store_global_etna = nir_intrinsic_op.define('nir_intrinsic_store_global_etna', 673) +nir_intrinsic_store_global_ir3 = nir_intrinsic_op.define('nir_intrinsic_store_global_ir3', 674) +nir_intrinsic_store_hit_attrib_amd = nir_intrinsic_op.define('nir_intrinsic_store_hit_attrib_amd', 675) +nir_intrinsic_store_local_pixel_agx = nir_intrinsic_op.define('nir_intrinsic_store_local_pixel_agx', 676) +nir_intrinsic_store_local_shared_r600 = nir_intrinsic_op.define('nir_intrinsic_store_local_shared_r600', 677) +nir_intrinsic_store_output = nir_intrinsic_op.define('nir_intrinsic_store_output', 678) +nir_intrinsic_store_per_primitive_output = nir_intrinsic_op.define('nir_intrinsic_store_per_primitive_output', 679) +nir_intrinsic_store_per_primitive_payload_intel = nir_intrinsic_op.define('nir_intrinsic_store_per_primitive_payload_intel', 680) +nir_intrinsic_store_per_vertex_output = nir_intrinsic_op.define('nir_intrinsic_store_per_vertex_output', 681) +nir_intrinsic_store_per_view_output = nir_intrinsic_op.define('nir_intrinsic_store_per_view_output', 682) +nir_intrinsic_store_preamble = nir_intrinsic_op.define('nir_intrinsic_store_preamble', 683) +nir_intrinsic_store_raw_output_pan = nir_intrinsic_op.define('nir_intrinsic_store_raw_output_pan', 684) +nir_intrinsic_store_reg = nir_intrinsic_op.define('nir_intrinsic_store_reg', 685) +nir_intrinsic_store_reg_indirect = nir_intrinsic_op.define('nir_intrinsic_store_reg_indirect', 686) +nir_intrinsic_store_scalar_arg_amd = nir_intrinsic_op.define('nir_intrinsic_store_scalar_arg_amd', 687) +nir_intrinsic_store_scratch = nir_intrinsic_op.define('nir_intrinsic_store_scratch', 688) +nir_intrinsic_store_shared = nir_intrinsic_op.define('nir_intrinsic_store_shared', 689) +nir_intrinsic_store_shared2_amd = nir_intrinsic_op.define('nir_intrinsic_store_shared2_amd', 690) +nir_intrinsic_store_shared_block_intel = nir_intrinsic_op.define('nir_intrinsic_store_shared_block_intel', 691) +nir_intrinsic_store_shared_ir3 = nir_intrinsic_op.define('nir_intrinsic_store_shared_ir3', 692) +nir_intrinsic_store_shared_unlock_nv = nir_intrinsic_op.define('nir_intrinsic_store_shared_unlock_nv', 693) +nir_intrinsic_store_ssbo = nir_intrinsic_op.define('nir_intrinsic_store_ssbo', 694) +nir_intrinsic_store_ssbo_block_intel = nir_intrinsic_op.define('nir_intrinsic_store_ssbo_block_intel', 695) +nir_intrinsic_store_ssbo_intel = nir_intrinsic_op.define('nir_intrinsic_store_ssbo_intel', 696) +nir_intrinsic_store_ssbo_ir3 = nir_intrinsic_op.define('nir_intrinsic_store_ssbo_ir3', 697) +nir_intrinsic_store_stack = nir_intrinsic_op.define('nir_intrinsic_store_stack', 698) +nir_intrinsic_store_task_payload = nir_intrinsic_op.define('nir_intrinsic_store_task_payload', 699) +nir_intrinsic_store_tf_r600 = nir_intrinsic_op.define('nir_intrinsic_store_tf_r600', 700) +nir_intrinsic_store_tlb_sample_color_v3d = nir_intrinsic_op.define('nir_intrinsic_store_tlb_sample_color_v3d', 701) +nir_intrinsic_store_uvs_agx = nir_intrinsic_op.define('nir_intrinsic_store_uvs_agx', 702) +nir_intrinsic_store_vector_arg_amd = nir_intrinsic_op.define('nir_intrinsic_store_vector_arg_amd', 703) +nir_intrinsic_store_zs_agx = nir_intrinsic_op.define('nir_intrinsic_store_zs_agx', 704) +nir_intrinsic_strict_wqm_coord_amd = nir_intrinsic_op.define('nir_intrinsic_strict_wqm_coord_amd', 705) +nir_intrinsic_subfm_nv = nir_intrinsic_op.define('nir_intrinsic_subfm_nv', 706) +nir_intrinsic_suclamp_nv = nir_intrinsic_op.define('nir_intrinsic_suclamp_nv', 707) +nir_intrinsic_sueau_nv = nir_intrinsic_op.define('nir_intrinsic_sueau_nv', 708) +nir_intrinsic_suldga_nv = nir_intrinsic_op.define('nir_intrinsic_suldga_nv', 709) +nir_intrinsic_sustga_nv = nir_intrinsic_op.define('nir_intrinsic_sustga_nv', 710) +nir_intrinsic_task_payload_atomic = nir_intrinsic_op.define('nir_intrinsic_task_payload_atomic', 711) +nir_intrinsic_task_payload_atomic_swap = nir_intrinsic_op.define('nir_intrinsic_task_payload_atomic_swap', 712) +nir_intrinsic_terminate = nir_intrinsic_op.define('nir_intrinsic_terminate', 713) +nir_intrinsic_terminate_if = nir_intrinsic_op.define('nir_intrinsic_terminate_if', 714) +nir_intrinsic_terminate_ray = nir_intrinsic_op.define('nir_intrinsic_terminate_ray', 715) +nir_intrinsic_trace_ray = nir_intrinsic_op.define('nir_intrinsic_trace_ray', 716) +nir_intrinsic_trace_ray_intel = nir_intrinsic_op.define('nir_intrinsic_trace_ray_intel', 717) +nir_intrinsic_unit_test_amd = nir_intrinsic_op.define('nir_intrinsic_unit_test_amd', 718) +nir_intrinsic_unit_test_divergent_amd = nir_intrinsic_op.define('nir_intrinsic_unit_test_divergent_amd', 719) +nir_intrinsic_unit_test_uniform_amd = nir_intrinsic_op.define('nir_intrinsic_unit_test_uniform_amd', 720) +nir_intrinsic_unpin_cx_handle_nv = nir_intrinsic_op.define('nir_intrinsic_unpin_cx_handle_nv', 721) +nir_intrinsic_use = nir_intrinsic_op.define('nir_intrinsic_use', 722) +nir_intrinsic_vild_nv = nir_intrinsic_op.define('nir_intrinsic_vild_nv', 723) +nir_intrinsic_vote_all = nir_intrinsic_op.define('nir_intrinsic_vote_all', 724) +nir_intrinsic_vote_any = nir_intrinsic_op.define('nir_intrinsic_vote_any', 725) +nir_intrinsic_vote_feq = nir_intrinsic_op.define('nir_intrinsic_vote_feq', 726) +nir_intrinsic_vote_ieq = nir_intrinsic_op.define('nir_intrinsic_vote_ieq', 727) +nir_intrinsic_vulkan_resource_index = nir_intrinsic_op.define('nir_intrinsic_vulkan_resource_index', 728) +nir_intrinsic_vulkan_resource_reindex = nir_intrinsic_op.define('nir_intrinsic_vulkan_resource_reindex', 729) +nir_intrinsic_write_invocation_amd = nir_intrinsic_op.define('nir_intrinsic_write_invocation_amd', 730) +nir_intrinsic_xfb_counter_sub_gfx11_amd = nir_intrinsic_op.define('nir_intrinsic_xfb_counter_sub_gfx11_amd', 731) +nir_last_intrinsic = nir_intrinsic_op.define('nir_last_intrinsic', 731) +nir_num_intrinsics = nir_intrinsic_op.define('nir_num_intrinsics', 732) + +struct_nir_intrinsic_instr._fields_ = [ + ('instr', nir_instr), + ('intrinsic', nir_intrinsic_op), + ('def', nir_def), + ('num_components', uint8_t), + ('const_index', (ctypes.c_int32 * 8)), + ('name', ctypes.POINTER(ctypes.c_char)), + ('src', (nir_src * 0)), +] +nir_intrinsic_instr = struct_nir_intrinsic_instr +nir_memory_semantics = CEnum(ctypes.c_uint32) +NIR_MEMORY_ACQUIRE = nir_memory_semantics.define('NIR_MEMORY_ACQUIRE', 1) +NIR_MEMORY_RELEASE = nir_memory_semantics.define('NIR_MEMORY_RELEASE', 2) +NIR_MEMORY_ACQ_REL = nir_memory_semantics.define('NIR_MEMORY_ACQ_REL', 3) +NIR_MEMORY_MAKE_AVAILABLE = nir_memory_semantics.define('NIR_MEMORY_MAKE_AVAILABLE', 4) +NIR_MEMORY_MAKE_VISIBLE = nir_memory_semantics.define('NIR_MEMORY_MAKE_VISIBLE', 8) + +nir_intrinsic_semantic_flag = CEnum(ctypes.c_uint32) +NIR_INTRINSIC_CAN_ELIMINATE = nir_intrinsic_semantic_flag.define('NIR_INTRINSIC_CAN_ELIMINATE', 1) +NIR_INTRINSIC_CAN_REORDER = nir_intrinsic_semantic_flag.define('NIR_INTRINSIC_CAN_REORDER', 2) +NIR_INTRINSIC_SUBGROUP = nir_intrinsic_semantic_flag.define('NIR_INTRINSIC_SUBGROUP', 4) +NIR_INTRINSIC_QUADGROUP = nir_intrinsic_semantic_flag.define('NIR_INTRINSIC_QUADGROUP', 8) + +class struct_nir_io_semantics(Struct): pass +struct_nir_io_semantics._fields_ = [ + ('location', ctypes.c_uint32,7), + ('num_slots', ctypes.c_uint32,6), + ('dual_source_blend_index', ctypes.c_uint32,1), + ('fb_fetch_output', ctypes.c_uint32,1), + ('fb_fetch_output_coherent', ctypes.c_uint32,1), + ('gs_streams', ctypes.c_uint32,8), + ('medium_precision', ctypes.c_uint32,1), + ('per_view', ctypes.c_uint32,1), + ('high_16bits', ctypes.c_uint32,1), + ('high_dvec2', ctypes.c_uint32,1), + ('no_varying', ctypes.c_uint32,1), + ('no_sysval_output', ctypes.c_uint32,1), + ('interp_explicit_strict', ctypes.c_uint32,1), + ('_pad', ctypes.c_uint32,1), +] +nir_io_semantics = struct_nir_io_semantics +class struct_nir_io_xfb(Struct): pass +class struct_nir_io_xfb_out(Struct): pass +struct_nir_io_xfb_out._fields_ = [ + ('num_components', uint8_t,4), + ('buffer', uint8_t,4), + ('offset', uint8_t), +] +struct_nir_io_xfb._fields_ = [ + ('out', (struct_nir_io_xfb_out * 2)), +] +nir_io_xfb = struct_nir_io_xfb +# unsigned int nir_instr_xfb_write_mask(nir_intrinsic_instr *instr) +try: (nir_instr_xfb_write_mask:=dll.nir_instr_xfb_write_mask).restype, nir_instr_xfb_write_mask.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +class struct_nir_intrinsic_info(Struct): pass +struct_nir_intrinsic_info._fields_ = [ + ('name', ctypes.POINTER(ctypes.c_char)), + ('num_srcs', uint8_t), + ('src_components', (int8_t * 11)), + ('has_dest', ctypes.c_bool), + ('dest_components', uint8_t), + ('dest_bit_sizes', uint8_t), + ('bit_size_src', int8_t), + ('num_indices', uint8_t), + ('indices', (uint8_t * 8)), + ('index_map', (uint8_t * 75)), + ('flags', nir_intrinsic_semantic_flag), +] +nir_intrinsic_info = struct_nir_intrinsic_info +try: nir_intrinsic_infos = (nir_intrinsic_info * 732).in_dll(dll, 'nir_intrinsic_infos') +except (ValueError,AttributeError): pass +# unsigned int nir_intrinsic_src_components(const nir_intrinsic_instr *intr, unsigned int srcn) +try: (nir_intrinsic_src_components:=dll.nir_intrinsic_src_components).restype, nir_intrinsic_src_components.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_intrinsic_instr), ctypes.c_uint32] +except AttributeError: pass + +# unsigned int nir_intrinsic_dest_components(nir_intrinsic_instr *intr) +try: (nir_intrinsic_dest_components:=dll.nir_intrinsic_dest_components).restype, nir_intrinsic_dest_components.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# nir_alu_type nir_intrinsic_instr_src_type(const nir_intrinsic_instr *intrin, unsigned int src) +try: (nir_intrinsic_instr_src_type:=dll.nir_intrinsic_instr_src_type).restype, nir_intrinsic_instr_src_type.argtypes = nir_alu_type, [ctypes.POINTER(nir_intrinsic_instr), ctypes.c_uint32] +except AttributeError: pass + +# nir_alu_type nir_intrinsic_instr_dest_type(const nir_intrinsic_instr *intrin) +try: (nir_intrinsic_instr_dest_type:=dll.nir_intrinsic_instr_dest_type).restype, nir_intrinsic_instr_dest_type.argtypes = nir_alu_type, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# void nir_intrinsic_copy_const_indices(nir_intrinsic_instr *dst, nir_intrinsic_instr *src) +try: (nir_intrinsic_copy_const_indices:=dll.nir_intrinsic_copy_const_indices).restype, nir_intrinsic_copy_const_indices.argtypes = None, [ctypes.POINTER(nir_intrinsic_instr), ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# unsigned int nir_image_intrinsic_coord_components(const nir_intrinsic_instr *instr) +try: (nir_image_intrinsic_coord_components:=dll.nir_image_intrinsic_coord_components).restype, nir_image_intrinsic_coord_components.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# void nir_rewrite_image_intrinsic(nir_intrinsic_instr *instr, nir_def *handle, bool bindless) +try: (nir_rewrite_image_intrinsic:=dll.nir_rewrite_image_intrinsic).restype, nir_rewrite_image_intrinsic.argtypes = None, [ctypes.POINTER(nir_intrinsic_instr), ctypes.POINTER(nir_def), ctypes.c_bool] +except AttributeError: pass + +# bool nir_intrinsic_can_reorder(nir_intrinsic_instr *instr) +try: (nir_intrinsic_can_reorder:=dll.nir_intrinsic_can_reorder).restype, nir_intrinsic_can_reorder.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# bool nir_intrinsic_writes_external_memory(const nir_intrinsic_instr *instr) +try: (nir_intrinsic_writes_external_memory:=dll.nir_intrinsic_writes_external_memory).restype, nir_intrinsic_writes_external_memory.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +enum_nir_tex_src_type = CEnum(ctypes.c_uint32) +nir_tex_src_coord = enum_nir_tex_src_type.define('nir_tex_src_coord', 0) +nir_tex_src_projector = enum_nir_tex_src_type.define('nir_tex_src_projector', 1) +nir_tex_src_comparator = enum_nir_tex_src_type.define('nir_tex_src_comparator', 2) +nir_tex_src_offset = enum_nir_tex_src_type.define('nir_tex_src_offset', 3) +nir_tex_src_bias = enum_nir_tex_src_type.define('nir_tex_src_bias', 4) +nir_tex_src_lod = enum_nir_tex_src_type.define('nir_tex_src_lod', 5) +nir_tex_src_min_lod = enum_nir_tex_src_type.define('nir_tex_src_min_lod', 6) +nir_tex_src_lod_bias_min_agx = enum_nir_tex_src_type.define('nir_tex_src_lod_bias_min_agx', 7) +nir_tex_src_ms_index = enum_nir_tex_src_type.define('nir_tex_src_ms_index', 8) +nir_tex_src_ms_mcs_intel = enum_nir_tex_src_type.define('nir_tex_src_ms_mcs_intel', 9) +nir_tex_src_ddx = enum_nir_tex_src_type.define('nir_tex_src_ddx', 10) +nir_tex_src_ddy = enum_nir_tex_src_type.define('nir_tex_src_ddy', 11) +nir_tex_src_texture_deref = enum_nir_tex_src_type.define('nir_tex_src_texture_deref', 12) +nir_tex_src_sampler_deref = enum_nir_tex_src_type.define('nir_tex_src_sampler_deref', 13) +nir_tex_src_texture_offset = enum_nir_tex_src_type.define('nir_tex_src_texture_offset', 14) +nir_tex_src_sampler_offset = enum_nir_tex_src_type.define('nir_tex_src_sampler_offset', 15) +nir_tex_src_texture_handle = enum_nir_tex_src_type.define('nir_tex_src_texture_handle', 16) +nir_tex_src_sampler_handle = enum_nir_tex_src_type.define('nir_tex_src_sampler_handle', 17) +nir_tex_src_sampler_deref_intrinsic = enum_nir_tex_src_type.define('nir_tex_src_sampler_deref_intrinsic', 18) +nir_tex_src_texture_deref_intrinsic = enum_nir_tex_src_type.define('nir_tex_src_texture_deref_intrinsic', 19) +nir_tex_src_plane = enum_nir_tex_src_type.define('nir_tex_src_plane', 20) +nir_tex_src_backend1 = enum_nir_tex_src_type.define('nir_tex_src_backend1', 21) +nir_tex_src_backend2 = enum_nir_tex_src_type.define('nir_tex_src_backend2', 22) +nir_num_tex_src_types = enum_nir_tex_src_type.define('nir_num_tex_src_types', 23) + +nir_tex_src_type = enum_nir_tex_src_type +class struct_nir_tex_src(Struct): pass +struct_nir_tex_src._fields_ = [ + ('src', nir_src), + ('src_type', nir_tex_src_type), +] +nir_tex_src = struct_nir_tex_src +enum_nir_texop = CEnum(ctypes.c_uint32) +nir_texop_tex = enum_nir_texop.define('nir_texop_tex', 0) +nir_texop_txb = enum_nir_texop.define('nir_texop_txb', 1) +nir_texop_txl = enum_nir_texop.define('nir_texop_txl', 2) +nir_texop_txd = enum_nir_texop.define('nir_texop_txd', 3) +nir_texop_txf = enum_nir_texop.define('nir_texop_txf', 4) +nir_texop_txf_ms = enum_nir_texop.define('nir_texop_txf_ms', 5) +nir_texop_txf_ms_fb = enum_nir_texop.define('nir_texop_txf_ms_fb', 6) +nir_texop_txf_ms_mcs_intel = enum_nir_texop.define('nir_texop_txf_ms_mcs_intel', 7) +nir_texop_txs = enum_nir_texop.define('nir_texop_txs', 8) +nir_texop_lod = enum_nir_texop.define('nir_texop_lod', 9) +nir_texop_tg4 = enum_nir_texop.define('nir_texop_tg4', 10) +nir_texop_query_levels = enum_nir_texop.define('nir_texop_query_levels', 11) +nir_texop_texture_samples = enum_nir_texop.define('nir_texop_texture_samples', 12) +nir_texop_samples_identical = enum_nir_texop.define('nir_texop_samples_identical', 13) +nir_texop_tex_prefetch = enum_nir_texop.define('nir_texop_tex_prefetch', 14) +nir_texop_lod_bias = enum_nir_texop.define('nir_texop_lod_bias', 15) +nir_texop_fragment_fetch_amd = enum_nir_texop.define('nir_texop_fragment_fetch_amd', 16) +nir_texop_fragment_mask_fetch_amd = enum_nir_texop.define('nir_texop_fragment_mask_fetch_amd', 17) +nir_texop_descriptor_amd = enum_nir_texop.define('nir_texop_descriptor_amd', 18) +nir_texop_sampler_descriptor_amd = enum_nir_texop.define('nir_texop_sampler_descriptor_amd', 19) +nir_texop_image_min_lod_agx = enum_nir_texop.define('nir_texop_image_min_lod_agx', 20) +nir_texop_has_custom_border_color_agx = enum_nir_texop.define('nir_texop_has_custom_border_color_agx', 21) +nir_texop_custom_border_color_agx = enum_nir_texop.define('nir_texop_custom_border_color_agx', 22) +nir_texop_hdr_dim_nv = enum_nir_texop.define('nir_texop_hdr_dim_nv', 23) +nir_texop_tex_type_nv = enum_nir_texop.define('nir_texop_tex_type_nv', 24) + +nir_texop = enum_nir_texop +class struct_nir_tex_instr(Struct): pass +enum_glsl_sampler_dim = CEnum(ctypes.c_uint32) +GLSL_SAMPLER_DIM_1D = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_1D', 0) +GLSL_SAMPLER_DIM_2D = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_2D', 1) +GLSL_SAMPLER_DIM_3D = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_3D', 2) +GLSL_SAMPLER_DIM_CUBE = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_CUBE', 3) +GLSL_SAMPLER_DIM_RECT = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_RECT', 4) +GLSL_SAMPLER_DIM_BUF = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_BUF', 5) +GLSL_SAMPLER_DIM_EXTERNAL = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_EXTERNAL', 6) +GLSL_SAMPLER_DIM_MS = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_MS', 7) +GLSL_SAMPLER_DIM_SUBPASS = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_SUBPASS', 8) +GLSL_SAMPLER_DIM_SUBPASS_MS = enum_glsl_sampler_dim.define('GLSL_SAMPLER_DIM_SUBPASS_MS', 9) + +struct_nir_tex_instr._fields_ = [ + ('instr', nir_instr), + ('sampler_dim', enum_glsl_sampler_dim), + ('dest_type', nir_alu_type), + ('op', nir_texop), + ('def', nir_def), + ('src', ctypes.POINTER(nir_tex_src)), + ('num_srcs', ctypes.c_uint32), + ('coord_components', ctypes.c_uint32), + ('is_array', ctypes.c_bool), + ('is_shadow', ctypes.c_bool), + ('is_new_style_shadow', ctypes.c_bool), + ('is_sparse', ctypes.c_bool), + ('component', ctypes.c_uint32,2), + ('array_is_lowered_cube', ctypes.c_uint32,1), + ('is_gather_implicit_lod', ctypes.c_uint32,1), + ('skip_helpers', ctypes.c_uint32,1), + ('tg4_offsets', ((int8_t * 2) * 4)), + ('texture_non_uniform', ctypes.c_bool), + ('sampler_non_uniform', ctypes.c_bool), + ('offset_non_uniform', ctypes.c_bool), + ('texture_index', ctypes.c_uint32), + ('sampler_index', ctypes.c_uint32), + ('backend_flags', uint32_t), +] +nir_tex_instr = struct_nir_tex_instr +# bool nir_tex_instr_need_sampler(const nir_tex_instr *instr) +try: (nir_tex_instr_need_sampler:=dll.nir_tex_instr_need_sampler).restype, nir_tex_instr_need_sampler.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_tex_instr)] +except AttributeError: pass + +# unsigned int nir_tex_instr_result_size(const nir_tex_instr *instr) +try: (nir_tex_instr_result_size:=dll.nir_tex_instr_result_size).restype, nir_tex_instr_result_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_tex_instr)] +except AttributeError: pass + +# bool nir_tex_instr_is_query(const nir_tex_instr *instr) +try: (nir_tex_instr_is_query:=dll.nir_tex_instr_is_query).restype, nir_tex_instr_is_query.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_tex_instr)] +except AttributeError: pass + +# bool nir_tex_instr_has_implicit_derivative(const nir_tex_instr *instr) +try: (nir_tex_instr_has_implicit_derivative:=dll.nir_tex_instr_has_implicit_derivative).restype, nir_tex_instr_has_implicit_derivative.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_tex_instr)] +except AttributeError: pass + +# nir_alu_type nir_tex_instr_src_type(const nir_tex_instr *instr, unsigned int src) +try: (nir_tex_instr_src_type:=dll.nir_tex_instr_src_type).restype, nir_tex_instr_src_type.argtypes = nir_alu_type, [ctypes.POINTER(nir_tex_instr), ctypes.c_uint32] +except AttributeError: pass + +# unsigned int nir_tex_instr_src_size(const nir_tex_instr *instr, unsigned int src) +try: (nir_tex_instr_src_size:=dll.nir_tex_instr_src_size).restype, nir_tex_instr_src_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_tex_instr), ctypes.c_uint32] +except AttributeError: pass + +# void nir_tex_instr_add_src(nir_tex_instr *tex, nir_tex_src_type src_type, nir_def *src) +try: (nir_tex_instr_add_src:=dll.nir_tex_instr_add_src).restype, nir_tex_instr_add_src.argtypes = None, [ctypes.POINTER(nir_tex_instr), nir_tex_src_type, ctypes.POINTER(nir_def)] +except AttributeError: pass + +# void nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned int src_idx) +try: (nir_tex_instr_remove_src:=dll.nir_tex_instr_remove_src).restype, nir_tex_instr_remove_src.argtypes = None, [ctypes.POINTER(nir_tex_instr), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_tex_instr_has_explicit_tg4_offsets(nir_tex_instr *tex) +try: (nir_tex_instr_has_explicit_tg4_offsets:=dll.nir_tex_instr_has_explicit_tg4_offsets).restype, nir_tex_instr_has_explicit_tg4_offsets.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_tex_instr)] +except AttributeError: pass + +class struct_nir_load_const_instr(Struct): pass +struct_nir_load_const_instr._fields_ = [ + ('instr', nir_instr), + ('def', nir_def), + ('value', (nir_const_value * 0)), +] +nir_load_const_instr = struct_nir_load_const_instr +nir_jump_type = CEnum(ctypes.c_uint32) +nir_jump_return = nir_jump_type.define('nir_jump_return', 0) +nir_jump_halt = nir_jump_type.define('nir_jump_halt', 1) +nir_jump_break = nir_jump_type.define('nir_jump_break', 2) +nir_jump_continue = nir_jump_type.define('nir_jump_continue', 3) +nir_jump_goto = nir_jump_type.define('nir_jump_goto', 4) +nir_jump_goto_if = nir_jump_type.define('nir_jump_goto_if', 5) + +class struct_nir_jump_instr(Struct): pass +struct_nir_jump_instr._fields_ = [ + ('instr', nir_instr), + ('type', nir_jump_type), + ('condition', nir_src), + ('target', ctypes.POINTER(nir_block)), + ('else_target', ctypes.POINTER(nir_block)), +] +nir_jump_instr = struct_nir_jump_instr +class struct_nir_undef_instr(Struct): pass +struct_nir_undef_instr._fields_ = [ + ('instr', nir_instr), + ('def', nir_def), +] +nir_undef_instr = struct_nir_undef_instr +class struct_nir_phi_src(Struct): pass +struct_nir_phi_src._fields_ = [ + ('node', struct_exec_node), + ('pred', ctypes.POINTER(nir_block)), + ('src', nir_src), +] +nir_phi_src = struct_nir_phi_src +class struct_nir_phi_instr(Struct): pass +struct_nir_phi_instr._fields_ = [ + ('instr', nir_instr), + ('srcs', struct_exec_list), + ('def', nir_def), +] +nir_phi_instr = struct_nir_phi_instr +class struct_nir_parallel_copy_entry(Struct): pass +class struct_nir_parallel_copy_entry_dest(ctypes.Union): pass +struct_nir_parallel_copy_entry_dest._fields_ = [ + ('def', nir_def), + ('reg', nir_src), +] +struct_nir_parallel_copy_entry._fields_ = [ + ('node', struct_exec_node), + ('src_is_reg', ctypes.c_bool), + ('dest_is_reg', ctypes.c_bool), + ('src', nir_src), + ('dest', struct_nir_parallel_copy_entry_dest), +] +nir_parallel_copy_entry = struct_nir_parallel_copy_entry +class struct_nir_parallel_copy_instr(Struct): pass +struct_nir_parallel_copy_instr._fields_ = [ + ('instr', nir_instr), + ('entries', struct_exec_list), +] +nir_parallel_copy_instr = struct_nir_parallel_copy_instr +class struct_nir_instr_debug_info(Struct): pass +struct_nir_instr_debug_info._fields_ = [ + ('filename', ctypes.POINTER(ctypes.c_char)), + ('line', uint32_t), + ('column', uint32_t), + ('spirv_offset', uint32_t), + ('nir_line', uint32_t), + ('variable_name', ctypes.POINTER(ctypes.c_char)), + ('instr', nir_instr), +] +nir_instr_debug_info = struct_nir_instr_debug_info +class struct_nir_scalar(Struct): pass +struct_nir_scalar._fields_ = [ + ('def', ctypes.POINTER(nir_def)), + ('comp', ctypes.c_uint32), +] +nir_scalar = struct_nir_scalar +# nir_scalar nir_scalar_chase_movs(nir_scalar s) +try: (nir_scalar_chase_movs:=dll.nir_scalar_chase_movs).restype, nir_scalar_chase_movs.argtypes = nir_scalar, [nir_scalar] +except AttributeError: pass + +class struct_nir_binding(Struct): pass +struct_nir_binding._fields_ = [ + ('success', ctypes.c_bool), + ('var', ctypes.POINTER(nir_variable)), + ('desc_set', ctypes.c_uint32), + ('binding', ctypes.c_uint32), + ('num_indices', ctypes.c_uint32), + ('indices', (nir_src * 4)), + ('read_first_invocation', ctypes.c_bool), +] +nir_binding = struct_nir_binding +# nir_binding nir_chase_binding(nir_src rsrc) +try: (nir_chase_binding:=dll.nir_chase_binding).restype, nir_chase_binding.argtypes = nir_binding, [nir_src] +except AttributeError: pass + +# nir_variable *nir_get_binding_variable(nir_shader *shader, nir_binding binding) +try: (nir_get_binding_variable:=dll.nir_get_binding_variable).restype, nir_get_binding_variable.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), nir_binding] +except AttributeError: pass + +# bool nir_block_contains_work(nir_block *block) +try: (nir_block_contains_work:=dll.nir_block_contains_work).restype, nir_block_contains_work.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block)] +except AttributeError: pass + +nir_selection_control = CEnum(ctypes.c_uint32) +nir_selection_control_none = nir_selection_control.define('nir_selection_control_none', 0) +nir_selection_control_flatten = nir_selection_control.define('nir_selection_control_flatten', 1) +nir_selection_control_dont_flatten = nir_selection_control.define('nir_selection_control_dont_flatten', 2) +nir_selection_control_divergent_always_taken = nir_selection_control.define('nir_selection_control_divergent_always_taken', 3) + +class struct_nir_if(Struct): pass +struct_nir_if._fields_ = [ + ('cf_node', nir_cf_node), + ('condition', nir_src), + ('control', nir_selection_control), + ('then_list', struct_exec_list), + ('else_list', struct_exec_list), +] +nir_if = struct_nir_if +class struct_nir_loop_terminator(Struct): pass +struct_nir_loop_terminator._fields_ = [ + ('nif', ctypes.POINTER(nir_if)), + ('conditional_instr', ctypes.POINTER(nir_instr)), + ('break_block', ctypes.POINTER(nir_block)), + ('continue_from_block', ctypes.POINTER(nir_block)), + ('continue_from_then', ctypes.c_bool), + ('induction_rhs', ctypes.c_bool), + ('exact_trip_count_unknown', ctypes.c_bool), + ('loop_terminator_link', struct_list_head), +] +nir_loop_terminator = struct_nir_loop_terminator +class struct_nir_loop_induction_variable(Struct): pass +struct_nir_loop_induction_variable._fields_ = [ + ('basis', ctypes.POINTER(nir_def)), + ('def', ctypes.POINTER(nir_def)), + ('init_src', ctypes.POINTER(nir_src)), + ('update_src', ctypes.POINTER(nir_alu_src)), +] +nir_loop_induction_variable = struct_nir_loop_induction_variable +class struct_nir_loop_info(Struct): pass +class struct_hash_table(Struct): pass +class struct_hash_entry(Struct): pass +struct_hash_entry._fields_ = [ + ('hash', uint32_t), + ('key', ctypes.c_void_p), + ('data', ctypes.c_void_p), +] +struct_hash_table._fields_ = [ + ('table', ctypes.POINTER(struct_hash_entry)), + ('key_hash_function', ctypes.CFUNCTYPE(uint32_t, ctypes.c_void_p)), + ('key_equals_function', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_void_p, ctypes.c_void_p)), + ('deleted_key', ctypes.c_void_p), + ('size', uint32_t), + ('rehash', uint32_t), + ('size_magic', uint64_t), + ('rehash_magic', uint64_t), + ('max_entries', uint32_t), + ('size_index', uint32_t), + ('entries', uint32_t), + ('deleted_entries', uint32_t), +] +struct_nir_loop_info._fields_ = [ + ('instr_cost', ctypes.c_uint32), + ('has_soft_fp64', ctypes.c_bool), + ('guessed_trip_count', ctypes.c_uint32), + ('max_trip_count', ctypes.c_uint32), + ('exact_trip_count_known', ctypes.c_bool), + ('force_unroll', ctypes.c_bool), + ('complex_loop', ctypes.c_bool), + ('limiting_terminator', ctypes.POINTER(nir_loop_terminator)), + ('loop_terminator_list', struct_list_head), + ('induction_vars', ctypes.POINTER(struct_hash_table)), +] +nir_loop_info = struct_nir_loop_info +nir_loop_control = CEnum(ctypes.c_uint32) +nir_loop_control_none = nir_loop_control.define('nir_loop_control_none', 0) +nir_loop_control_unroll = nir_loop_control.define('nir_loop_control_unroll', 1) +nir_loop_control_dont_unroll = nir_loop_control.define('nir_loop_control_dont_unroll', 2) + +class struct_nir_loop(Struct): pass +struct_nir_loop._fields_ = [ + ('cf_node', nir_cf_node), + ('body', struct_exec_list), + ('continue_list', struct_exec_list), + ('info', ctypes.POINTER(nir_loop_info)), + ('control', nir_loop_control), + ('partially_unrolled', ctypes.c_bool), + ('divergent_continue', ctypes.c_bool), + ('divergent_break', ctypes.c_bool), +] +nir_loop = struct_nir_loop +class const_struct_nir_intrinsic_instr(Struct): pass +const_struct_nir_intrinsic_instr._fields_ = [ + ('instr', nir_instr), + ('intrinsic', nir_intrinsic_op), + ('def', nir_def), + ('num_components', uint8_t), + ('const_index', (ctypes.c_int32 * 8)), + ('name', ctypes.POINTER(ctypes.c_char)), + ('src', (nir_src * 0)), +] +nir_intrin_filter_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(const_struct_nir_intrinsic_instr), ctypes.c_void_p) +nir_vectorize_cb = ctypes.CFUNCTYPE(ctypes.c_ubyte, ctypes.POINTER(const_struct_nir_instr), ctypes.c_void_p) +# void nir_remove_non_entrypoints(nir_shader *shader) +try: (nir_remove_non_entrypoints:=dll.nir_remove_non_entrypoints).restype, nir_remove_non_entrypoints.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_remove_non_exported(nir_shader *shader) +try: (nir_remove_non_exported:=dll.nir_remove_non_exported).restype, nir_remove_non_exported.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_remove_entrypoints(nir_shader *shader) +try: (nir_remove_entrypoints:=dll.nir_remove_entrypoints).restype, nir_remove_entrypoints.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_fixup_is_exported(nir_shader *shader) +try: (nir_fixup_is_exported:=dll.nir_fixup_is_exported).restype, nir_fixup_is_exported.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +shader_info = struct_shader_info +# nir_shader *nir_shader_create(void *mem_ctx, gl_shader_stage stage, const nir_shader_compiler_options *options, shader_info *si) +try: (nir_shader_create:=dll.nir_shader_create).restype, nir_shader_create.argtypes = ctypes.POINTER(nir_shader), [ctypes.c_void_p, gl_shader_stage, ctypes.POINTER(nir_shader_compiler_options), ctypes.POINTER(shader_info)] +except AttributeError: pass + +# void nir_shader_add_variable(nir_shader *shader, nir_variable *var) +try: (nir_shader_add_variable:=dll.nir_shader_add_variable).restype, nir_shader_add_variable.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_variable)] +except AttributeError: pass + +# nir_variable *nir_variable_create(nir_shader *shader, nir_variable_mode mode, const struct glsl_type *type, const char *name) +try: (nir_variable_create:=dll.nir_variable_create).restype, nir_variable_create.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nir_variable *nir_local_variable_create(nir_function_impl *impl, const struct glsl_type *type, const char *name) +try: (nir_local_variable_create:=dll.nir_local_variable_create).restype, nir_local_variable_create.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_function_impl), ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nir_variable *nir_state_variable_create(nir_shader *shader, const struct glsl_type *type, const char *name, const gl_state_index16 tokens[4]) +try: (nir_state_variable_create:=dll.nir_state_variable_create).restype, nir_state_variable_create.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_glsl_type), ctypes.POINTER(ctypes.c_char), (gl_state_index16 * 4)] +except AttributeError: pass + +# nir_variable *nir_get_variable_with_location(nir_shader *shader, nir_variable_mode mode, int location, const struct glsl_type *type) +try: (nir_get_variable_with_location:=dll.nir_get_variable_with_location).restype, nir_get_variable_with_location.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.c_int32, ctypes.POINTER(struct_glsl_type)] +except AttributeError: pass + +# nir_variable *nir_create_variable_with_location(nir_shader *shader, nir_variable_mode mode, int location, const struct glsl_type *type) +try: (nir_create_variable_with_location:=dll.nir_create_variable_with_location).restype, nir_create_variable_with_location.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.c_int32, ctypes.POINTER(struct_glsl_type)] +except AttributeError: pass + +# nir_variable *nir_find_variable_with_location(nir_shader *shader, nir_variable_mode mode, unsigned int location) +try: (nir_find_variable_with_location:=dll.nir_find_variable_with_location).restype, nir_find_variable_with_location.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.c_uint32] +except AttributeError: pass + +# nir_variable *nir_find_variable_with_driver_location(nir_shader *shader, nir_variable_mode mode, unsigned int location) +try: (nir_find_variable_with_driver_location:=dll.nir_find_variable_with_driver_location).restype, nir_find_variable_with_driver_location.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.c_uint32] +except AttributeError: pass + +# nir_variable *nir_find_state_variable(nir_shader *s, gl_state_index16 tokens[4]) +try: (nir_find_state_variable:=dll.nir_find_state_variable).restype, nir_find_state_variable.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), (gl_state_index16 * 4)] +except AttributeError: pass + +# nir_variable *nir_find_sampler_variable_with_tex_index(nir_shader *shader, unsigned int texture_index) +try: (nir_find_sampler_variable_with_tex_index:=dll.nir_find_sampler_variable_with_tex_index).restype, nir_find_sampler_variable_with_tex_index.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# void nir_sort_variables_with_modes(nir_shader *shader, int (*compar)(const nir_variable *, const nir_variable *), nir_variable_mode modes) +try: (nir_sort_variables_with_modes:=dll.nir_sort_variables_with_modes).restype, nir_sort_variables_with_modes.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(nir_variable), ctypes.POINTER(nir_variable)), nir_variable_mode] +except AttributeError: pass + +# nir_function *nir_function_create(nir_shader *shader, const char *name) +try: (nir_function_create:=dll.nir_function_create).restype, nir_function_create.argtypes = ctypes.POINTER(nir_function), [ctypes.POINTER(nir_shader), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nir_function_impl *nir_function_impl_create(nir_function *func) +try: (nir_function_impl_create:=dll.nir_function_impl_create).restype, nir_function_impl_create.argtypes = ctypes.POINTER(nir_function_impl), [ctypes.POINTER(nir_function)] +except AttributeError: pass + +# nir_function_impl *nir_function_impl_create_bare(nir_shader *shader) +try: (nir_function_impl_create_bare:=dll.nir_function_impl_create_bare).restype, nir_function_impl_create_bare.argtypes = ctypes.POINTER(nir_function_impl), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_block *nir_block_create(nir_shader *shader) +try: (nir_block_create:=dll.nir_block_create).restype, nir_block_create.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_if *nir_if_create(nir_shader *shader) +try: (nir_if_create:=dll.nir_if_create).restype, nir_if_create.argtypes = ctypes.POINTER(nir_if), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_loop *nir_loop_create(nir_shader *shader) +try: (nir_loop_create:=dll.nir_loop_create).restype, nir_loop_create.argtypes = ctypes.POINTER(nir_loop), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_function_impl *nir_cf_node_get_function(nir_cf_node *node) +try: (nir_cf_node_get_function:=dll.nir_cf_node_get_function).restype, nir_cf_node_get_function.argtypes = ctypes.POINTER(nir_function_impl), [ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# void nir_metadata_require(nir_function_impl *impl, nir_metadata required, ...) +try: (nir_metadata_require:=dll.nir_metadata_require).restype, nir_metadata_require.argtypes = None, [ctypes.POINTER(nir_function_impl), nir_metadata] +except AttributeError: pass + +# void nir_shader_preserve_all_metadata(nir_shader *shader) +try: (nir_shader_preserve_all_metadata:=dll.nir_shader_preserve_all_metadata).restype, nir_shader_preserve_all_metadata.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_metadata_invalidate(nir_shader *shader) +try: (nir_metadata_invalidate:=dll.nir_metadata_invalidate).restype, nir_metadata_invalidate.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_progress(bool progress, nir_function_impl *impl, nir_metadata preserved) +try: (nir_progress:=dll.nir_progress).restype, nir_progress.argtypes = ctypes.c_bool, [ctypes.c_bool, ctypes.POINTER(nir_function_impl), nir_metadata] +except AttributeError: pass + +# nir_alu_instr *nir_alu_instr_create(nir_shader *shader, nir_op op) +try: (nir_alu_instr_create:=dll.nir_alu_instr_create).restype, nir_alu_instr_create.argtypes = ctypes.POINTER(nir_alu_instr), [ctypes.POINTER(nir_shader), nir_op] +except AttributeError: pass + +# nir_deref_instr *nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type) +try: (nir_deref_instr_create:=dll.nir_deref_instr_create).restype, nir_deref_instr_create.argtypes = ctypes.POINTER(nir_deref_instr), [ctypes.POINTER(nir_shader), nir_deref_type] +except AttributeError: pass + +# nir_jump_instr *nir_jump_instr_create(nir_shader *shader, nir_jump_type type) +try: (nir_jump_instr_create:=dll.nir_jump_instr_create).restype, nir_jump_instr_create.argtypes = ctypes.POINTER(nir_jump_instr), [ctypes.POINTER(nir_shader), nir_jump_type] +except AttributeError: pass + +# nir_load_const_instr *nir_load_const_instr_create(nir_shader *shader, unsigned int num_components, unsigned int bit_size) +try: (nir_load_const_instr_create:=dll.nir_load_const_instr_create).restype, nir_load_const_instr_create.argtypes = ctypes.POINTER(nir_load_const_instr), [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# nir_intrinsic_instr *nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op) +try: (nir_intrinsic_instr_create:=dll.nir_intrinsic_instr_create).restype, nir_intrinsic_instr_create.argtypes = ctypes.POINTER(nir_intrinsic_instr), [ctypes.POINTER(nir_shader), nir_intrinsic_op] +except AttributeError: pass + +# nir_call_instr *nir_call_instr_create(nir_shader *shader, nir_function *callee) +try: (nir_call_instr_create:=dll.nir_call_instr_create).restype, nir_call_instr_create.argtypes = ctypes.POINTER(nir_call_instr), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_function)] +except AttributeError: pass + +# nir_tex_instr *nir_tex_instr_create(nir_shader *shader, unsigned int num_srcs) +try: (nir_tex_instr_create:=dll.nir_tex_instr_create).restype, nir_tex_instr_create.argtypes = ctypes.POINTER(nir_tex_instr), [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# nir_phi_instr *nir_phi_instr_create(nir_shader *shader) +try: (nir_phi_instr_create:=dll.nir_phi_instr_create).restype, nir_phi_instr_create.argtypes = ctypes.POINTER(nir_phi_instr), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_phi_src *nir_phi_instr_add_src(nir_phi_instr *instr, nir_block *pred, nir_def *src) +try: (nir_phi_instr_add_src:=dll.nir_phi_instr_add_src).restype, nir_phi_instr_add_src.argtypes = ctypes.POINTER(nir_phi_src), [ctypes.POINTER(nir_phi_instr), ctypes.POINTER(nir_block), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# nir_parallel_copy_instr *nir_parallel_copy_instr_create(nir_shader *shader) +try: (nir_parallel_copy_instr_create:=dll.nir_parallel_copy_instr_create).restype, nir_parallel_copy_instr_create.argtypes = ctypes.POINTER(nir_parallel_copy_instr), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_undef_instr *nir_undef_instr_create(nir_shader *shader, unsigned int num_components, unsigned int bit_size) +try: (nir_undef_instr_create:=dll.nir_undef_instr_create).restype, nir_undef_instr_create.argtypes = ctypes.POINTER(nir_undef_instr), [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# nir_const_value nir_alu_binop_identity(nir_op binop, unsigned int bit_size) +try: (nir_alu_binop_identity:=dll.nir_alu_binop_identity).restype, nir_alu_binop_identity.argtypes = nir_const_value, [nir_op, ctypes.c_uint32] +except AttributeError: pass + +nir_cursor_option = CEnum(ctypes.c_uint32) +nir_cursor_before_block = nir_cursor_option.define('nir_cursor_before_block', 0) +nir_cursor_after_block = nir_cursor_option.define('nir_cursor_after_block', 1) +nir_cursor_before_instr = nir_cursor_option.define('nir_cursor_before_instr', 2) +nir_cursor_after_instr = nir_cursor_option.define('nir_cursor_after_instr', 3) + +class struct_nir_cursor(Struct): pass +class struct_nir_cursor_0(ctypes.Union): pass +struct_nir_cursor_0._fields_ = [ + ('block', ctypes.POINTER(nir_block)), + ('instr', ctypes.POINTER(nir_instr)), +] +struct_nir_cursor._anonymous_ = ['_0'] struct_nir_cursor._fields_ = [ - ('option', nir_cursor_option), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_nir_cursor_0), + ('option', nir_cursor_option), + ('_0', struct_nir_cursor_0), ] - nir_cursor = struct_nir_cursor -try: - nir_cursor_current_block = _libraries['FIXME_STUB'].nir_cursor_current_block - nir_cursor_current_block.restype = ctypes.POINTER(struct_nir_block) - nir_cursor_current_block.argtypes = [nir_cursor] -except AttributeError: - pass -try: - nir_cursors_equal = _libraries['libtinymesa_cpu.so'].nir_cursors_equal - nir_cursors_equal.restype = ctypes.c_bool - nir_cursors_equal.argtypes = [nir_cursor, nir_cursor] -except AttributeError: - pass -try: - nir_before_block = _libraries['FIXME_STUB'].nir_before_block - nir_before_block.restype = nir_cursor - nir_before_block.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_after_block = _libraries['FIXME_STUB'].nir_after_block - nir_after_block.restype = nir_cursor - nir_after_block.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_before_instr = _libraries['FIXME_STUB'].nir_before_instr - nir_before_instr.restype = nir_cursor - nir_before_instr.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_after_instr = _libraries['FIXME_STUB'].nir_after_instr - nir_after_instr.restype = nir_cursor - nir_after_instr.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_before_block_after_phis = _libraries['FIXME_STUB'].nir_before_block_after_phis - nir_before_block_after_phis.restype = nir_cursor - nir_before_block_after_phis.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_after_block_before_jump = _libraries['FIXME_STUB'].nir_after_block_before_jump - nir_after_block_before_jump.restype = nir_cursor - nir_after_block_before_jump.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_before_src = _libraries['FIXME_STUB'].nir_before_src - nir_before_src.restype = nir_cursor - nir_before_src.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_before_cf_node = _libraries['FIXME_STUB'].nir_before_cf_node - nir_before_cf_node.restype = nir_cursor - nir_before_cf_node.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_after_cf_node = _libraries['FIXME_STUB'].nir_after_cf_node - nir_after_cf_node.restype = nir_cursor - nir_after_cf_node.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_after_phis = _libraries['FIXME_STUB'].nir_after_phis - nir_after_phis.restype = nir_cursor - nir_after_phis.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_after_instr_and_phis = _libraries['FIXME_STUB'].nir_after_instr_and_phis - nir_after_instr_and_phis.restype = nir_cursor - nir_after_instr_and_phis.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_after_cf_node_and_phis = _libraries['FIXME_STUB'].nir_after_cf_node_and_phis - nir_after_cf_node_and_phis.restype = nir_cursor - nir_after_cf_node_and_phis.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_before_cf_list = _libraries['FIXME_STUB'].nir_before_cf_list - nir_before_cf_list.restype = nir_cursor - nir_before_cf_list.argtypes = [ctypes.POINTER(struct_exec_list)] -except AttributeError: - pass -try: - nir_after_cf_list = _libraries['FIXME_STUB'].nir_after_cf_list - nir_after_cf_list.restype = nir_cursor - nir_after_cf_list.argtypes = [ctypes.POINTER(struct_exec_list)] -except AttributeError: - pass -try: - nir_before_impl = _libraries['FIXME_STUB'].nir_before_impl - nir_before_impl.restype = nir_cursor - nir_before_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_after_impl = _libraries['FIXME_STUB'].nir_after_impl - nir_after_impl.restype = nir_cursor - nir_after_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_instr_insert = _libraries['libtinymesa_cpu.so'].nir_instr_insert - nir_instr_insert.restype = None - nir_instr_insert.argtypes = [nir_cursor, ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_move = _libraries['libtinymesa_cpu.so'].nir_instr_move - nir_instr_move.restype = ctypes.c_bool - nir_instr_move.argtypes = [nir_cursor, ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_before = _libraries['FIXME_STUB'].nir_instr_insert_before - nir_instr_insert_before.restype = None - nir_instr_insert_before.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_after = _libraries['FIXME_STUB'].nir_instr_insert_after - nir_instr_insert_after.restype = None - nir_instr_insert_after.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_before_block = _libraries['FIXME_STUB'].nir_instr_insert_before_block - nir_instr_insert_before_block.restype = None - nir_instr_insert_before_block.argtypes = [ctypes.POINTER(struct_nir_block), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_after_block = _libraries['FIXME_STUB'].nir_instr_insert_after_block - nir_instr_insert_after_block.restype = None - nir_instr_insert_after_block.argtypes = [ctypes.POINTER(struct_nir_block), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_before_cf = _libraries['FIXME_STUB'].nir_instr_insert_before_cf - nir_instr_insert_before_cf.restype = None - nir_instr_insert_before_cf.argtypes = [ctypes.POINTER(struct_nir_cf_node), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_after_cf = _libraries['FIXME_STUB'].nir_instr_insert_after_cf - nir_instr_insert_after_cf.restype = None - nir_instr_insert_after_cf.argtypes = [ctypes.POINTER(struct_nir_cf_node), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_before_cf_list = _libraries['FIXME_STUB'].nir_instr_insert_before_cf_list - nir_instr_insert_before_cf_list.restype = None - nir_instr_insert_before_cf_list.argtypes = [ctypes.POINTER(struct_exec_list), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_insert_after_cf_list = _libraries['FIXME_STUB'].nir_instr_insert_after_cf_list - nir_instr_insert_after_cf_list.restype = None - nir_instr_insert_after_cf_list.argtypes = [ctypes.POINTER(struct_exec_list), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_remove_v = _libraries['libtinymesa_cpu.so'].nir_instr_remove_v - nir_instr_remove_v.restype = None - nir_instr_remove_v.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_free = _libraries['libtinymesa_cpu.so'].nir_instr_free - nir_instr_free.restype = None - nir_instr_free.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_free_list = _libraries['libtinymesa_cpu.so'].nir_instr_free_list - nir_instr_free_list.restype = None - nir_instr_free_list.argtypes = [ctypes.POINTER(struct_exec_list)] -except AttributeError: - pass -try: - nir_instr_remove = _libraries['FIXME_STUB'].nir_instr_remove - nir_instr_remove.restype = nir_cursor - nir_instr_remove.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_free_and_dce = _libraries['libtinymesa_cpu.so'].nir_instr_free_and_dce - nir_instr_free_and_dce.restype = nir_cursor - nir_instr_free_and_dce.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_def = _libraries['libtinymesa_cpu.so'].nir_instr_def - nir_instr_def.restype = ctypes.POINTER(struct_nir_def) - nir_instr_def.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_get_debug_info = _libraries['FIXME_STUB'].nir_instr_get_debug_info - nir_instr_get_debug_info.restype = ctypes.POINTER(struct_nir_instr_debug_info) - nir_instr_get_debug_info.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_get_gc_pointer = _libraries['FIXME_STUB'].nir_instr_get_gc_pointer - nir_instr_get_gc_pointer.restype = ctypes.POINTER(None) - nir_instr_get_gc_pointer.argtypes = [ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -nir_foreach_def_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_def), ctypes.POINTER(None)) -nir_foreach_src_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_src), ctypes.POINTER(None)) -try: - nir_foreach_src = _libraries['FIXME_STUB'].nir_foreach_src - nir_foreach_src.restype = ctypes.c_bool - nir_foreach_src.argtypes = [ctypes.POINTER(struct_nir_instr), nir_foreach_src_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_foreach_phi_src_leaving_block = _libraries['libtinymesa_cpu.so'].nir_foreach_phi_src_leaving_block - nir_foreach_phi_src_leaving_block.restype = ctypes.c_bool - nir_foreach_phi_src_leaving_block.argtypes = [ctypes.POINTER(struct_nir_block), nir_foreach_src_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_src_as_const_value = _libraries['libtinymesa_cpu.so'].nir_src_as_const_value - nir_src_as_const_value.restype = ctypes.POINTER(union_c__UA_nir_const_value) - nir_src_as_const_value.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_as_alu_instr = _libraries['FIXME_STUB'].nir_src_as_alu_instr - nir_src_as_alu_instr.restype = ctypes.POINTER(struct_nir_alu_instr) - nir_src_as_alu_instr.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_as_intrinsic = _libraries['FIXME_STUB'].nir_src_as_intrinsic - nir_src_as_intrinsic.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_src_as_intrinsic.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_as_string = _libraries['FIXME_STUB'].nir_src_as_string - nir_src_as_string.restype = ctypes.POINTER(ctypes.c_char) - nir_src_as_string.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_src_is_always_uniform = _libraries['libtinymesa_cpu.so'].nir_src_is_always_uniform - nir_src_is_always_uniform.restype = ctypes.c_bool - nir_src_is_always_uniform.argtypes = [nir_src] -except AttributeError: - pass -try: - nir_srcs_equal = _libraries['libtinymesa_cpu.so'].nir_srcs_equal - nir_srcs_equal.restype = ctypes.c_bool - nir_srcs_equal.argtypes = [nir_src, nir_src] -except AttributeError: - pass -try: - nir_instrs_equal = _libraries['libtinymesa_cpu.so'].nir_instrs_equal - nir_instrs_equal.restype = ctypes.c_bool - nir_instrs_equal.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_src_get_block = _libraries['libtinymesa_cpu.so'].nir_src_get_block - nir_src_get_block.restype = ctypes.POINTER(struct_nir_block) - nir_src_get_block.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_src_rewrite = _libraries['FIXME_STUB'].nir_src_rewrite - nir_src_rewrite.restype = None - nir_src_rewrite.argtypes = [ctypes.POINTER(struct_nir_src), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_instr_init_src = _libraries['libtinymesa_cpu.so'].nir_instr_init_src - nir_instr_init_src.restype = None - nir_instr_init_src.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_src), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_instr_clear_src = _libraries['libtinymesa_cpu.so'].nir_instr_clear_src - nir_instr_clear_src.restype = None - nir_instr_clear_src.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_instr_move_src = _libraries['libtinymesa_cpu.so'].nir_instr_move_src - nir_instr_move_src.restype = None - nir_instr_move_src.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_src), ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_instr_is_before = _libraries['libtinymesa_cpu.so'].nir_instr_is_before - nir_instr_is_before.restype = ctypes.c_bool - nir_instr_is_before.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_def_init = _libraries['libtinymesa_cpu.so'].nir_def_init - nir_def_init.restype = None - nir_def_init.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_def_init_for_type = _libraries['FIXME_STUB'].nir_def_init_for_type - nir_def_init_for_type.restype = None - nir_def_init_for_type.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - nir_def_rewrite_uses = _libraries['libtinymesa_cpu.so'].nir_def_rewrite_uses - nir_def_rewrite_uses.restype = None - nir_def_rewrite_uses.argtypes = [ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_rewrite_uses_src = _libraries['libtinymesa_cpu.so'].nir_def_rewrite_uses_src - nir_def_rewrite_uses_src.restype = None - nir_def_rewrite_uses_src.argtypes = [ctypes.POINTER(struct_nir_def), nir_src] -except AttributeError: - pass -try: - nir_def_rewrite_uses_after = _libraries['libtinymesa_cpu.so'].nir_def_rewrite_uses_after - nir_def_rewrite_uses_after.restype = None - nir_def_rewrite_uses_after.argtypes = [ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_def_replace = _libraries['FIXME_STUB'].nir_def_replace - nir_def_replace.restype = None - nir_def_replace.argtypes = [ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_src_components_read = _libraries['libtinymesa_cpu.so'].nir_src_components_read - nir_src_components_read.restype = nir_component_mask_t - nir_src_components_read.argtypes = [ctypes.POINTER(struct_nir_src)] -except AttributeError: - pass -try: - nir_def_components_read = _libraries['libtinymesa_cpu.so'].nir_def_components_read - nir_def_components_read.restype = nir_component_mask_t - nir_def_components_read.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_all_uses_are_fsat = _libraries['libtinymesa_cpu.so'].nir_def_all_uses_are_fsat - nir_def_all_uses_are_fsat.restype = ctypes.c_bool - nir_def_all_uses_are_fsat.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_all_uses_ignore_sign_bit = _libraries['libtinymesa_cpu.so'].nir_def_all_uses_ignore_sign_bit - nir_def_all_uses_ignore_sign_bit.restype = ctypes.c_bool - nir_def_all_uses_ignore_sign_bit.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_first_component_read = _libraries['FIXME_STUB'].nir_def_first_component_read - nir_def_first_component_read.restype = ctypes.c_int32 - nir_def_first_component_read.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_last_component_read = _libraries['FIXME_STUB'].nir_def_last_component_read - nir_def_last_component_read.restype = ctypes.c_int32 - nir_def_last_component_read.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_def_is_unused = _libraries['FIXME_STUB'].nir_def_is_unused - nir_def_is_unused.restype = ctypes.c_bool - nir_def_is_unused.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_sort_unstructured_blocks = _libraries['libtinymesa_cpu.so'].nir_sort_unstructured_blocks - nir_sort_unstructured_blocks.restype = None - nir_sort_unstructured_blocks.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_block_unstructured_next = _libraries['libtinymesa_cpu.so'].nir_block_unstructured_next - nir_block_unstructured_next.restype = ctypes.POINTER(struct_nir_block) - nir_block_unstructured_next.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_unstructured_start_block = _libraries['libtinymesa_cpu.so'].nir_unstructured_start_block - nir_unstructured_start_block.restype = ctypes.POINTER(struct_nir_block) - nir_unstructured_start_block.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_block_cf_tree_next = _libraries['libtinymesa_cpu.so'].nir_block_cf_tree_next - nir_block_cf_tree_next.restype = ctypes.POINTER(struct_nir_block) - nir_block_cf_tree_next.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_cf_tree_prev = _libraries['libtinymesa_cpu.so'].nir_block_cf_tree_prev - nir_block_cf_tree_prev.restype = ctypes.POINTER(struct_nir_block) - nir_block_cf_tree_prev.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_cf_node_cf_tree_first = _libraries['libtinymesa_cpu.so'].nir_cf_node_cf_tree_first - nir_cf_node_cf_tree_first.restype = ctypes.POINTER(struct_nir_block) - nir_cf_node_cf_tree_first.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_cf_tree_last = _libraries['libtinymesa_cpu.so'].nir_cf_node_cf_tree_last - nir_cf_node_cf_tree_last.restype = ctypes.POINTER(struct_nir_block) - nir_cf_node_cf_tree_last.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_cf_tree_next = _libraries['libtinymesa_cpu.so'].nir_cf_node_cf_tree_next - nir_cf_node_cf_tree_next.restype = ctypes.POINTER(struct_nir_block) - nir_cf_node_cf_tree_next.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_cf_node_cf_tree_prev = _libraries['libtinymesa_cpu.so'].nir_cf_node_cf_tree_prev - nir_cf_node_cf_tree_prev.restype = ctypes.POINTER(struct_nir_block) - nir_cf_node_cf_tree_prev.argtypes = [ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_block_get_following_if = _libraries['libtinymesa_cpu.so'].nir_block_get_following_if - nir_block_get_following_if.restype = ctypes.POINTER(struct_nir_if) - nir_block_get_following_if.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_get_following_loop = _libraries['libtinymesa_cpu.so'].nir_block_get_following_loop - nir_block_get_following_loop.restype = ctypes.POINTER(struct_nir_loop) - nir_block_get_following_loop.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_get_predecessors_sorted = _libraries['libtinymesa_cpu.so'].nir_block_get_predecessors_sorted - nir_block_get_predecessors_sorted.restype = ctypes.POINTER(ctypes.POINTER(struct_nir_block)) - nir_block_get_predecessors_sorted.argtypes = [ctypes.POINTER(struct_nir_block), ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_index_ssa_defs = _libraries['libtinymesa_cpu.so'].nir_index_ssa_defs - nir_index_ssa_defs.restype = None - nir_index_ssa_defs.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_index_instrs = _libraries['libtinymesa_cpu.so'].nir_index_instrs - nir_index_instrs.restype = ctypes.c_uint32 - nir_index_instrs.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_index_blocks = _libraries['libtinymesa_cpu.so'].nir_index_blocks - nir_index_blocks.restype = None - nir_index_blocks.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_shader_clear_pass_flags = _libraries['libtinymesa_cpu.so'].nir_shader_clear_pass_flags - nir_shader_clear_pass_flags.restype = None - nir_shader_clear_pass_flags.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_shader_index_vars = _libraries['libtinymesa_cpu.so'].nir_shader_index_vars - nir_shader_index_vars.restype = ctypes.c_uint32 - nir_shader_index_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_function_impl_index_vars = _libraries['libtinymesa_cpu.so'].nir_function_impl_index_vars - nir_function_impl_index_vars.restype = ctypes.c_uint32 - nir_function_impl_index_vars.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_print_shader = _libraries['libtinymesa_cpu.so'].nir_print_shader - nir_print_shader.restype = None - nir_print_shader.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_print_function_body = _libraries['libtinymesa_cpu.so'].nir_print_function_body - nir_print_function_body.restype = None - nir_print_function_body.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_print_shader_annotated = _libraries['libtinymesa_cpu.so'].nir_print_shader_annotated - nir_print_shader_annotated.restype = None - nir_print_shader_annotated.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct__IO_FILE), ctypes.POINTER(struct_hash_table)] -except AttributeError: - pass -try: - nir_print_instr = _libraries['libtinymesa_cpu.so'].nir_print_instr - nir_print_instr.restype = None - nir_print_instr.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_print_deref = _libraries['libtinymesa_cpu.so'].nir_print_deref - nir_print_deref.restype = None - nir_print_deref.argtypes = [ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass +# bool nir_cursors_equal(nir_cursor a, nir_cursor b) +try: (nir_cursors_equal:=dll.nir_cursors_equal).restype, nir_cursors_equal.argtypes = ctypes.c_bool, [nir_cursor, nir_cursor] +except AttributeError: pass -# values for enumeration 'mesa_log_level' -mesa_log_level__enumvalues = { - 0: 'MESA_LOG_ERROR', - 1: 'MESA_LOG_WARN', - 2: 'MESA_LOG_INFO', - 3: 'MESA_LOG_DEBUG', -} -MESA_LOG_ERROR = 0 -MESA_LOG_WARN = 1 -MESA_LOG_INFO = 2 -MESA_LOG_DEBUG = 3 -mesa_log_level = ctypes.c_uint32 # enum -try: - nir_log_shader_annotated_tagged = _libraries['libtinymesa_cpu.so'].nir_log_shader_annotated_tagged - nir_log_shader_annotated_tagged.restype = None - nir_log_shader_annotated_tagged.argtypes = [mesa_log_level, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_hash_table)] -except AttributeError: - pass -try: - nir_shader_as_str = _libraries['libtinymesa_cpu.so'].nir_shader_as_str - nir_shader_as_str.restype = ctypes.POINTER(ctypes.c_char) - nir_shader_as_str.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_as_str_annotated = _libraries['libtinymesa_cpu.so'].nir_shader_as_str_annotated - nir_shader_as_str_annotated.restype = ctypes.POINTER(ctypes.c_char) - nir_shader_as_str_annotated.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_hash_table), ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_instr_as_str = _libraries['libtinymesa_cpu.so'].nir_instr_as_str - nir_instr_as_str.restype = ctypes.POINTER(ctypes.c_char) - nir_instr_as_str.argtypes = [ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_gather_debug_info = _libraries['libtinymesa_cpu.so'].nir_shader_gather_debug_info - nir_shader_gather_debug_info.restype = ctypes.POINTER(ctypes.c_char) - nir_shader_gather_debug_info.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_char), uint32_t] -except AttributeError: - pass -try: - nir_instr_clone = _libraries['libtinymesa_cpu.so'].nir_instr_clone - nir_instr_clone.restype = ctypes.POINTER(struct_nir_instr) - nir_instr_clone.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_clone_deep = _libraries['libtinymesa_cpu.so'].nir_instr_clone_deep - nir_instr_clone_deep.restype = ctypes.POINTER(struct_nir_instr) - nir_instr_clone_deep.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_hash_table)] -except AttributeError: - pass -try: - nir_alu_instr_clone = _libraries['libtinymesa_cpu.so'].nir_alu_instr_clone - nir_alu_instr_clone.restype = ctypes.POINTER(struct_nir_alu_instr) - nir_alu_instr_clone.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_shader_clone = _libraries['libtinymesa_cpu.so'].nir_shader_clone - nir_shader_clone.restype = ctypes.POINTER(struct_nir_shader) - nir_shader_clone.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_function_clone = _libraries['libtinymesa_cpu.so'].nir_function_clone - nir_function_clone.restype = ctypes.POINTER(struct_nir_function) - nir_function_clone.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function)] -except AttributeError: - pass -try: - nir_function_impl_clone = _libraries['libtinymesa_cpu.so'].nir_function_impl_clone - nir_function_impl_clone.restype = ctypes.POINTER(struct_nir_function_impl) - nir_function_impl_clone.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_function_impl_clone_remap_globals = _libraries['libtinymesa_cpu.so'].nir_function_impl_clone_remap_globals - nir_function_impl_clone_remap_globals.restype = ctypes.POINTER(struct_nir_function_impl) - nir_function_impl_clone_remap_globals.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct_hash_table)] -except AttributeError: - pass -try: - nir_constant_clone = _libraries['libtinymesa_cpu.so'].nir_constant_clone - nir_constant_clone.restype = ctypes.POINTER(struct_nir_constant) - nir_constant_clone.argtypes = [ctypes.POINTER(struct_nir_constant), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_variable_clone = _libraries['libtinymesa_cpu.so'].nir_variable_clone - nir_variable_clone.restype = ctypes.POINTER(struct_nir_variable) - nir_variable_clone.argtypes = [ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_shader_replace = _libraries['libtinymesa_cpu.so'].nir_shader_replace - nir_shader_replace.restype = None - nir_shader_replace.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_shader_serialize_deserialize = _libraries['libtinymesa_cpu.so'].nir_shader_serialize_deserialize - nir_shader_serialize_deserialize.restype = None - nir_shader_serialize_deserialize.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_validate_shader = _libraries['libtinymesa_cpu.so'].nir_validate_shader - nir_validate_shader.restype = None - nir_validate_shader.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_validate_ssa_dominance = _libraries['libtinymesa_cpu.so'].nir_validate_ssa_dominance - nir_validate_ssa_dominance.restype = None - nir_validate_ssa_dominance.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_metadata_set_validation_flag = _libraries['libtinymesa_cpu.so'].nir_metadata_set_validation_flag - nir_metadata_set_validation_flag.restype = None - nir_metadata_set_validation_flag.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_metadata_check_validation_flag = _libraries['libtinymesa_cpu.so'].nir_metadata_check_validation_flag - nir_metadata_check_validation_flag.restype = None - nir_metadata_check_validation_flag.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_metadata_require_all = _libraries['libtinymesa_cpu.so'].nir_metadata_require_all - nir_metadata_require_all.restype = None - nir_metadata_require_all.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - should_skip_nir = _libraries['FIXME_STUB'].should_skip_nir - should_skip_nir.restype = ctypes.c_bool - should_skip_nir.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - should_print_nir = _libraries['FIXME_STUB'].should_print_nir - should_print_nir.restype = ctypes.c_bool - should_print_nir.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -nir_instr_writemask_filter_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.c_uint32, ctypes.POINTER(None)) -class struct_nir_builder(Structure): - pass +# void nir_instr_insert(nir_cursor cursor, nir_instr *instr) +try: (nir_instr_insert:=dll.nir_instr_insert).restype, nir_instr_insert.argtypes = None, [nir_cursor, ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# bool nir_instr_move(nir_cursor cursor, nir_instr *instr) +try: (nir_instr_move:=dll.nir_instr_move).restype, nir_instr_move.argtypes = ctypes.c_bool, [nir_cursor, ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# void nir_instr_remove_v(nir_instr *instr) +try: (nir_instr_remove_v:=dll.nir_instr_remove_v).restype, nir_instr_remove_v.argtypes = None, [ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# void nir_instr_free(nir_instr *instr) +try: (nir_instr_free:=dll.nir_instr_free).restype, nir_instr_free.argtypes = None, [ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# void nir_instr_free_list(struct exec_list *list) +try: (nir_instr_free_list:=dll.nir_instr_free_list).restype, nir_instr_free_list.argtypes = None, [ctypes.POINTER(struct_exec_list)] +except AttributeError: pass + +# nir_cursor nir_instr_free_and_dce(nir_instr *instr) +try: (nir_instr_free_and_dce:=dll.nir_instr_free_and_dce).restype, nir_instr_free_and_dce.argtypes = nir_cursor, [ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# nir_def *nir_instr_def(nir_instr *instr) +try: (nir_instr_def:=dll.nir_instr_def).restype, nir_instr_def.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_instr)] +except AttributeError: pass + +nir_foreach_def_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_def), ctypes.c_void_p) +nir_foreach_src_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_src), ctypes.c_void_p) +# bool nir_foreach_phi_src_leaving_block(nir_block *instr, nir_foreach_src_cb cb, void *state) +try: (nir_foreach_phi_src_leaving_block:=dll.nir_foreach_phi_src_leaving_block).restype, nir_foreach_phi_src_leaving_block.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block), nir_foreach_src_cb, ctypes.c_void_p] +except AttributeError: pass + +# nir_const_value *nir_src_as_const_value(nir_src src) +try: (nir_src_as_const_value:=dll.nir_src_as_const_value).restype, nir_src_as_const_value.argtypes = ctypes.POINTER(nir_const_value), [nir_src] +except AttributeError: pass + +# const char *nir_src_as_string(nir_src src) +try: (nir_src_as_string:=dll.nir_src_as_string).restype, nir_src_as_string.argtypes = ctypes.POINTER(ctypes.c_char), [nir_src] +except AttributeError: pass + +# bool nir_src_is_always_uniform(nir_src src) +try: (nir_src_is_always_uniform:=dll.nir_src_is_always_uniform).restype, nir_src_is_always_uniform.argtypes = ctypes.c_bool, [nir_src] +except AttributeError: pass + +# bool nir_srcs_equal(nir_src src1, nir_src src2) +try: (nir_srcs_equal:=dll.nir_srcs_equal).restype, nir_srcs_equal.argtypes = ctypes.c_bool, [nir_src, nir_src] +except AttributeError: pass + +# bool nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2) +try: (nir_instrs_equal:=dll.nir_instrs_equal).restype, nir_instrs_equal.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_instr), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# nir_block *nir_src_get_block(nir_src *src) +try: (nir_src_get_block:=dll.nir_src_get_block).restype, nir_src_get_block.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_src)] +except AttributeError: pass + +# void nir_instr_init_src(nir_instr *instr, nir_src *src, nir_def *def) +try: (nir_instr_init_src:=dll.nir_instr_init_src).restype, nir_instr_init_src.argtypes = None, [ctypes.POINTER(nir_instr), ctypes.POINTER(nir_src), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# void nir_instr_clear_src(nir_instr *instr, nir_src *src) +try: (nir_instr_clear_src:=dll.nir_instr_clear_src).restype, nir_instr_clear_src.argtypes = None, [ctypes.POINTER(nir_instr), ctypes.POINTER(nir_src)] +except AttributeError: pass + +# void nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src) +try: (nir_instr_move_src:=dll.nir_instr_move_src).restype, nir_instr_move_src.argtypes = None, [ctypes.POINTER(nir_instr), ctypes.POINTER(nir_src), ctypes.POINTER(nir_src)] +except AttributeError: pass + +# bool nir_instr_is_before(nir_instr *first, nir_instr *second) +try: (nir_instr_is_before:=dll.nir_instr_is_before).restype, nir_instr_is_before.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_instr), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# void nir_def_init(nir_instr *instr, nir_def *def, unsigned int num_components, unsigned int bit_size) +try: (nir_def_init:=dll.nir_def_init).restype, nir_def_init.argtypes = None, [ctypes.POINTER(nir_instr), ctypes.POINTER(nir_def), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# void nir_def_rewrite_uses(nir_def *def, nir_def *new_ssa) +try: (nir_def_rewrite_uses:=dll.nir_def_rewrite_uses).restype, nir_def_rewrite_uses.argtypes = None, [ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# void nir_def_rewrite_uses_src(nir_def *def, nir_src new_src) +try: (nir_def_rewrite_uses_src:=dll.nir_def_rewrite_uses_src).restype, nir_def_rewrite_uses_src.argtypes = None, [ctypes.POINTER(nir_def), nir_src] +except AttributeError: pass + +# void nir_def_rewrite_uses_after(nir_def *def, nir_def *new_ssa, nir_instr *after_me) +try: (nir_def_rewrite_uses_after:=dll.nir_def_rewrite_uses_after).restype, nir_def_rewrite_uses_after.argtypes = None, [ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# nir_component_mask_t nir_src_components_read(const nir_src *src) +try: (nir_src_components_read:=dll.nir_src_components_read).restype, nir_src_components_read.argtypes = nir_component_mask_t, [ctypes.POINTER(nir_src)] +except AttributeError: pass + +# nir_component_mask_t nir_def_components_read(const nir_def *def) +try: (nir_def_components_read:=dll.nir_def_components_read).restype, nir_def_components_read.argtypes = nir_component_mask_t, [ctypes.POINTER(nir_def)] +except AttributeError: pass + +# bool nir_def_all_uses_are_fsat(const nir_def *def) +try: (nir_def_all_uses_are_fsat:=dll.nir_def_all_uses_are_fsat).restype, nir_def_all_uses_are_fsat.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_def)] +except AttributeError: pass + +# bool nir_def_all_uses_ignore_sign_bit(const nir_def *def) +try: (nir_def_all_uses_ignore_sign_bit:=dll.nir_def_all_uses_ignore_sign_bit).restype, nir_def_all_uses_ignore_sign_bit.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_def)] +except AttributeError: pass + +# void nir_sort_unstructured_blocks(nir_function_impl *impl) +try: (nir_sort_unstructured_blocks:=dll.nir_sort_unstructured_blocks).restype, nir_sort_unstructured_blocks.argtypes = None, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# nir_block *nir_block_unstructured_next(nir_block *block) +try: (nir_block_unstructured_next:=dll.nir_block_unstructured_next).restype, nir_block_unstructured_next.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# nir_block *nir_unstructured_start_block(nir_function_impl *impl) +try: (nir_unstructured_start_block:=dll.nir_unstructured_start_block).restype, nir_unstructured_start_block.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# nir_block *nir_block_cf_tree_next(nir_block *block) +try: (nir_block_cf_tree_next:=dll.nir_block_cf_tree_next).restype, nir_block_cf_tree_next.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# nir_block *nir_block_cf_tree_prev(nir_block *block) +try: (nir_block_cf_tree_prev:=dll.nir_block_cf_tree_prev).restype, nir_block_cf_tree_prev.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node) +try: (nir_cf_node_cf_tree_first:=dll.nir_cf_node_cf_tree_first).restype, nir_cf_node_cf_tree_first.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node) +try: (nir_cf_node_cf_tree_last:=dll.nir_cf_node_cf_tree_last).restype, nir_cf_node_cf_tree_last.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node) +try: (nir_cf_node_cf_tree_next:=dll.nir_cf_node_cf_tree_next).restype, nir_cf_node_cf_tree_next.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# nir_block *nir_cf_node_cf_tree_prev(nir_cf_node *node) +try: (nir_cf_node_cf_tree_prev:=dll.nir_cf_node_cf_tree_prev).restype, nir_cf_node_cf_tree_prev.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# nir_if *nir_block_get_following_if(nir_block *block) +try: (nir_block_get_following_if:=dll.nir_block_get_following_if).restype, nir_block_get_following_if.argtypes = ctypes.POINTER(nir_if), [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# nir_loop *nir_block_get_following_loop(nir_block *block) +try: (nir_block_get_following_loop:=dll.nir_block_get_following_loop).restype, nir_block_get_following_loop.argtypes = ctypes.POINTER(nir_loop), [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# nir_block **nir_block_get_predecessors_sorted(const nir_block *block, void *mem_ctx) +try: (nir_block_get_predecessors_sorted:=dll.nir_block_get_predecessors_sorted).restype, nir_block_get_predecessors_sorted.argtypes = ctypes.POINTER(ctypes.POINTER(nir_block)), [ctypes.POINTER(nir_block), ctypes.c_void_p] +except AttributeError: pass + +# void nir_index_ssa_defs(nir_function_impl *impl) +try: (nir_index_ssa_defs:=dll.nir_index_ssa_defs).restype, nir_index_ssa_defs.argtypes = None, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# unsigned int nir_index_instrs(nir_function_impl *impl) +try: (nir_index_instrs:=dll.nir_index_instrs).restype, nir_index_instrs.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# void nir_index_blocks(nir_function_impl *impl) +try: (nir_index_blocks:=dll.nir_index_blocks).restype, nir_index_blocks.argtypes = None, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# void nir_shader_clear_pass_flags(nir_shader *shader) +try: (nir_shader_clear_pass_flags:=dll.nir_shader_clear_pass_flags).restype, nir_shader_clear_pass_flags.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# unsigned int nir_shader_index_vars(nir_shader *shader, nir_variable_mode modes) +try: (nir_shader_index_vars:=dll.nir_shader_index_vars).restype, nir_shader_index_vars.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# unsigned int nir_function_impl_index_vars(nir_function_impl *impl) +try: (nir_function_impl_index_vars:=dll.nir_function_impl_index_vars).restype, nir_function_impl_index_vars.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +class struct__IO_FILE(Struct): pass +FILE = struct__IO_FILE +class struct__IO_marker(Struct): pass +__off_t = ctypes.c_int64 +_IO_lock_t = None +__off64_t = ctypes.c_int64 +class struct__IO_codecvt(Struct): pass +class struct__IO_wide_data(Struct): pass +size_t = ctypes.c_uint64 +struct__IO_FILE._fields_ = [ + ('_flags', ctypes.c_int32), + ('_IO_read_ptr', ctypes.POINTER(ctypes.c_char)), + ('_IO_read_end', ctypes.POINTER(ctypes.c_char)), + ('_IO_read_base', ctypes.POINTER(ctypes.c_char)), + ('_IO_write_base', ctypes.POINTER(ctypes.c_char)), + ('_IO_write_ptr', ctypes.POINTER(ctypes.c_char)), + ('_IO_write_end', ctypes.POINTER(ctypes.c_char)), + ('_IO_buf_base', ctypes.POINTER(ctypes.c_char)), + ('_IO_buf_end', ctypes.POINTER(ctypes.c_char)), + ('_IO_save_base', ctypes.POINTER(ctypes.c_char)), + ('_IO_backup_base', ctypes.POINTER(ctypes.c_char)), + ('_IO_save_end', ctypes.POINTER(ctypes.c_char)), + ('_markers', ctypes.POINTER(struct__IO_marker)), + ('_chain', ctypes.POINTER(struct__IO_FILE)), + ('_fileno', ctypes.c_int32), + ('_flags2', ctypes.c_int32), + ('_old_offset', ctypes.c_int64), + ('_cur_column', ctypes.c_uint16), + ('_vtable_offset', ctypes.c_char), + ('_shortbuf', (ctypes.c_char * 1)), + ('_lock', ctypes.POINTER(_IO_lock_t)), + ('_offset', ctypes.c_int64), + ('_codecvt', ctypes.POINTER(struct__IO_codecvt)), + ('_wide_data', ctypes.POINTER(struct__IO_wide_data)), + ('_freeres_list', ctypes.POINTER(struct__IO_FILE)), + ('_freeres_buf', ctypes.c_void_p), + ('__pad5', size_t), + ('_mode', ctypes.c_int32), + ('_unused2', (ctypes.c_char * 20)), +] +# void nir_print_shader(nir_shader *shader, FILE *fp) +try: (nir_print_shader:=dll.nir_print_shader).restype, nir_print_shader.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_print_function_body(nir_function_impl *impl, FILE *fp) +try: (nir_print_function_body:=dll.nir_print_function_body).restype, nir_print_function_body.argtypes = None, [ctypes.POINTER(nir_function_impl), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_print_shader_annotated(nir_shader *shader, FILE *fp, struct hash_table *errors) +try: (nir_print_shader_annotated:=dll.nir_print_shader_annotated).restype, nir_print_shader_annotated.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(FILE), ctypes.POINTER(struct_hash_table)] +except AttributeError: pass + +# void nir_print_instr(const nir_instr *instr, FILE *fp) +try: (nir_print_instr:=dll.nir_print_instr).restype, nir_print_instr.argtypes = None, [ctypes.POINTER(nir_instr), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_print_deref(const nir_deref_instr *deref, FILE *fp) +try: (nir_print_deref:=dll.nir_print_deref).restype, nir_print_deref.argtypes = None, [ctypes.POINTER(nir_deref_instr), ctypes.POINTER(FILE)] +except AttributeError: pass + +enum_mesa_log_level = CEnum(ctypes.c_uint32) +MESA_LOG_ERROR = enum_mesa_log_level.define('MESA_LOG_ERROR', 0) +MESA_LOG_WARN = enum_mesa_log_level.define('MESA_LOG_WARN', 1) +MESA_LOG_INFO = enum_mesa_log_level.define('MESA_LOG_INFO', 2) +MESA_LOG_DEBUG = enum_mesa_log_level.define('MESA_LOG_DEBUG', 3) + +# void nir_log_shader_annotated_tagged(enum mesa_log_level level, const char *tag, nir_shader *shader, struct hash_table *annotations) +try: (nir_log_shader_annotated_tagged:=dll.nir_log_shader_annotated_tagged).restype, nir_log_shader_annotated_tagged.argtypes = None, [enum_mesa_log_level, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(nir_shader), ctypes.POINTER(struct_hash_table)] +except AttributeError: pass + +# char *nir_shader_as_str(nir_shader *nir, void *mem_ctx) +try: (nir_shader_as_str:=dll.nir_shader_as_str).restype, nir_shader_as_str.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(nir_shader), ctypes.c_void_p] +except AttributeError: pass + +# char *nir_shader_as_str_annotated(nir_shader *nir, struct hash_table *annotations, void *mem_ctx) +try: (nir_shader_as_str_annotated:=dll.nir_shader_as_str_annotated).restype, nir_shader_as_str_annotated.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_hash_table), ctypes.c_void_p] +except AttributeError: pass + +# char *nir_instr_as_str(const nir_instr *instr, void *mem_ctx) +try: (nir_instr_as_str:=dll.nir_instr_as_str).restype, nir_instr_as_str.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(nir_instr), ctypes.c_void_p] +except AttributeError: pass + +# char *nir_shader_gather_debug_info(nir_shader *shader, const char *filename, uint32_t first_line) +try: (nir_shader_gather_debug_info:=dll.nir_shader_gather_debug_info).restype, nir_shader_gather_debug_info.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(nir_shader), ctypes.POINTER(ctypes.c_char), uint32_t] +except AttributeError: pass + +# nir_instr *nir_instr_clone(nir_shader *s, const nir_instr *orig) +try: (nir_instr_clone:=dll.nir_instr_clone).restype, nir_instr_clone.argtypes = ctypes.POINTER(nir_instr), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# nir_instr *nir_instr_clone_deep(nir_shader *s, const nir_instr *orig, struct hash_table *remap_table) +try: (nir_instr_clone_deep:=dll.nir_instr_clone_deep).restype, nir_instr_clone_deep.argtypes = ctypes.POINTER(nir_instr), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_instr), ctypes.POINTER(struct_hash_table)] +except AttributeError: pass + +# nir_alu_instr *nir_alu_instr_clone(nir_shader *s, const nir_alu_instr *orig) +try: (nir_alu_instr_clone:=dll.nir_alu_instr_clone).restype, nir_alu_instr_clone.argtypes = ctypes.POINTER(nir_alu_instr), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_alu_instr)] +except AttributeError: pass + +# nir_shader *nir_shader_clone(void *mem_ctx, const nir_shader *s) +try: (nir_shader_clone:=dll.nir_shader_clone).restype, nir_shader_clone.argtypes = ctypes.POINTER(nir_shader), [ctypes.c_void_p, ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_function *nir_function_clone(nir_shader *ns, const nir_function *fxn) +try: (nir_function_clone:=dll.nir_function_clone).restype, nir_function_clone.argtypes = ctypes.POINTER(nir_function), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_function)] +except AttributeError: pass + +# nir_function_impl *nir_function_impl_clone(nir_shader *shader, const nir_function_impl *fi) +try: (nir_function_impl_clone:=dll.nir_function_impl_clone).restype, nir_function_impl_clone.argtypes = ctypes.POINTER(nir_function_impl), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# nir_function_impl *nir_function_impl_clone_remap_globals(nir_shader *shader, const nir_function_impl *fi, struct hash_table *remap_table) +try: (nir_function_impl_clone_remap_globals:=dll.nir_function_impl_clone_remap_globals).restype, nir_function_impl_clone_remap_globals.argtypes = ctypes.POINTER(nir_function_impl), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_function_impl), ctypes.POINTER(struct_hash_table)] +except AttributeError: pass + +# nir_constant *nir_constant_clone(const nir_constant *c, nir_variable *var) +try: (nir_constant_clone:=dll.nir_constant_clone).restype, nir_constant_clone.argtypes = ctypes.POINTER(nir_constant), [ctypes.POINTER(nir_constant), ctypes.POINTER(nir_variable)] +except AttributeError: pass + +# nir_variable *nir_variable_clone(const nir_variable *c, nir_shader *shader) +try: (nir_variable_clone:=dll.nir_variable_clone).restype, nir_variable_clone.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_variable), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_shader_replace(nir_shader *dest, nir_shader *src) +try: (nir_shader_replace:=dll.nir_shader_replace).restype, nir_shader_replace.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_shader_serialize_deserialize(nir_shader *s) +try: (nir_shader_serialize_deserialize:=dll.nir_shader_serialize_deserialize).restype, nir_shader_serialize_deserialize.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_validate_shader(nir_shader *shader, const char *when) +try: (nir_validate_shader:=dll.nir_validate_shader).restype, nir_validate_shader.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void nir_validate_ssa_dominance(nir_shader *shader, const char *when) +try: (nir_validate_ssa_dominance:=dll.nir_validate_ssa_dominance).restype, nir_validate_ssa_dominance.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void nir_metadata_set_validation_flag(nir_shader *shader) +try: (nir_metadata_set_validation_flag:=dll.nir_metadata_set_validation_flag).restype, nir_metadata_set_validation_flag.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_metadata_check_validation_flag(nir_shader *shader) +try: (nir_metadata_check_validation_flag:=dll.nir_metadata_check_validation_flag).restype, nir_metadata_check_validation_flag.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_metadata_require_all(nir_shader *shader) +try: (nir_metadata_require_all:=dll.nir_metadata_require_all).restype, nir_metadata_require_all.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_instr_writemask_filter_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(const_struct_nir_instr), ctypes.c_uint32, ctypes.c_void_p) +class struct_nir_builder(Struct): pass +nir_lower_instr_cb = ctypes.CFUNCTYPE(ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_instr), ctypes.c_void_p) +# bool nir_function_impl_lower_instructions(nir_function_impl *impl, nir_instr_filter_cb filter, nir_lower_instr_cb lower, void *cb_data) +try: (nir_function_impl_lower_instructions:=dll.nir_function_impl_lower_instructions).restype, nir_function_impl_lower_instructions.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl), nir_instr_filter_cb, nir_lower_instr_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_shader_lower_instructions(nir_shader *shader, nir_instr_filter_cb filter, nir_lower_instr_cb lower, void *cb_data) +try: (nir_shader_lower_instructions:=dll.nir_shader_lower_instructions).restype, nir_shader_lower_instructions.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_instr_filter_cb, nir_lower_instr_cb, ctypes.c_void_p] +except AttributeError: pass + +# void nir_calc_dominance_impl(nir_function_impl *impl) +try: (nir_calc_dominance_impl:=dll.nir_calc_dominance_impl).restype, nir_calc_dominance_impl.argtypes = None, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# void nir_calc_dominance(nir_shader *shader) +try: (nir_calc_dominance:=dll.nir_calc_dominance).restype, nir_calc_dominance.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_block *nir_dominance_lca(nir_block *b1, nir_block *b2) +try: (nir_dominance_lca:=dll.nir_dominance_lca).restype, nir_dominance_lca.argtypes = ctypes.POINTER(nir_block), [ctypes.POINTER(nir_block), ctypes.POINTER(nir_block)] +except AttributeError: pass + +# bool nir_block_dominates(nir_block *parent, nir_block *child) +try: (nir_block_dominates:=dll.nir_block_dominates).restype, nir_block_dominates.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block), ctypes.POINTER(nir_block)] +except AttributeError: pass + +# bool nir_block_is_unreachable(nir_block *block) +try: (nir_block_is_unreachable:=dll.nir_block_is_unreachable).restype, nir_block_is_unreachable.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# void nir_dump_dom_tree_impl(nir_function_impl *impl, FILE *fp) +try: (nir_dump_dom_tree_impl:=dll.nir_dump_dom_tree_impl).restype, nir_dump_dom_tree_impl.argtypes = None, [ctypes.POINTER(nir_function_impl), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_dump_dom_tree(nir_shader *shader, FILE *fp) +try: (nir_dump_dom_tree:=dll.nir_dump_dom_tree).restype, nir_dump_dom_tree.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_dump_dom_frontier_impl(nir_function_impl *impl, FILE *fp) +try: (nir_dump_dom_frontier_impl:=dll.nir_dump_dom_frontier_impl).restype, nir_dump_dom_frontier_impl.argtypes = None, [ctypes.POINTER(nir_function_impl), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_dump_dom_frontier(nir_shader *shader, FILE *fp) +try: (nir_dump_dom_frontier:=dll.nir_dump_dom_frontier).restype, nir_dump_dom_frontier.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_dump_cfg_impl(nir_function_impl *impl, FILE *fp) +try: (nir_dump_cfg_impl:=dll.nir_dump_cfg_impl).restype, nir_dump_cfg_impl.argtypes = None, [ctypes.POINTER(nir_function_impl), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_dump_cfg(nir_shader *shader, FILE *fp) +try: (nir_dump_cfg:=dll.nir_dump_cfg).restype, nir_dump_cfg.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(FILE)] +except AttributeError: pass + +# void nir_gs_count_vertices_and_primitives(const nir_shader *shader, int *out_vtxcnt, int *out_prmcnt, int *out_decomposed_prmcnt, unsigned int num_streams) +try: (nir_gs_count_vertices_and_primitives:=dll.nir_gs_count_vertices_and_primitives).restype, nir_gs_count_vertices_and_primitives.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] +except AttributeError: pass + +nir_load_grouping = CEnum(ctypes.c_uint32) +nir_group_all = nir_load_grouping.define('nir_group_all', 0) +nir_group_same_resource_only = nir_load_grouping.define('nir_group_same_resource_only', 1) + +# bool nir_group_loads(nir_shader *shader, nir_load_grouping grouping, unsigned int max_distance) +try: (nir_group_loads:=dll.nir_group_loads).restype, nir_group_loads.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_load_grouping, ctypes.c_uint32] +except AttributeError: pass + +# bool nir_shrink_vec_array_vars(nir_shader *shader, nir_variable_mode modes) +try: (nir_shrink_vec_array_vars:=dll.nir_shrink_vec_array_vars).restype, nir_shrink_vec_array_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_split_array_vars(nir_shader *shader, nir_variable_mode modes) +try: (nir_split_array_vars:=dll.nir_split_array_vars).restype, nir_split_array_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_split_var_copies(nir_shader *shader) +try: (nir_split_var_copies:=dll.nir_split_var_copies).restype, nir_split_var_copies.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_split_per_member_structs(nir_shader *shader) +try: (nir_split_per_member_structs:=dll.nir_split_per_member_structs).restype, nir_split_per_member_structs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_split_struct_vars(nir_shader *shader, nir_variable_mode modes) +try: (nir_split_struct_vars:=dll.nir_split_struct_vars).restype, nir_split_struct_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_lower_returns_impl(nir_function_impl *impl) +try: (nir_lower_returns_impl:=dll.nir_lower_returns_impl).restype, nir_lower_returns_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_lower_returns(nir_shader *shader) +try: (nir_lower_returns:=dll.nir_lower_returns).restype, nir_lower_returns.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_builder = struct_nir_builder +# nir_def *nir_inline_function_impl(nir_builder *b, const nir_function_impl *impl, nir_def **params, struct hash_table *shader_var_remap) +try: (nir_inline_function_impl:=dll.nir_inline_function_impl).restype, nir_inline_function_impl.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_function_impl), ctypes.POINTER(ctypes.POINTER(nir_def)), ctypes.POINTER(struct_hash_table)] +except AttributeError: pass + +# bool nir_inline_functions(nir_shader *shader) +try: (nir_inline_functions:=dll.nir_inline_functions).restype, nir_inline_functions.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_cleanup_functions(nir_shader *shader) +try: (nir_cleanup_functions:=dll.nir_cleanup_functions).restype, nir_cleanup_functions.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_link_shader_functions(nir_shader *shader, const nir_shader *link_shader) +try: (nir_link_shader_functions:=dll.nir_link_shader_functions).restype, nir_link_shader_functions.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_calls_to_builtins(nir_shader *s) +try: (nir_lower_calls_to_builtins:=dll.nir_lower_calls_to_builtins).restype, nir_lower_calls_to_builtins.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_find_inlinable_uniforms(nir_shader *shader) +try: (nir_find_inlinable_uniforms:=dll.nir_find_inlinable_uniforms).restype, nir_find_inlinable_uniforms.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_inline_uniforms(nir_shader *shader, unsigned int num_uniforms, const uint32_t *uniform_values, const uint16_t *uniform_dw_offsets) +try: (nir_inline_uniforms:=dll.nir_inline_uniforms).restype, nir_inline_uniforms.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.POINTER(uint32_t), ctypes.POINTER(uint16_t)] +except AttributeError: pass + +# bool nir_collect_src_uniforms(const nir_src *src, int component, uint32_t *uni_offsets, uint8_t *num_offsets, unsigned int max_num_bo, unsigned int max_offset) +try: (nir_collect_src_uniforms:=dll.nir_collect_src_uniforms).restype, nir_collect_src_uniforms.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_src), ctypes.c_int32, ctypes.POINTER(uint32_t), ctypes.POINTER(uint8_t), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# void nir_add_inlinable_uniforms(const nir_src *cond, nir_loop_info *info, uint32_t *uni_offsets, uint8_t *num_offsets, unsigned int max_num_bo, unsigned int max_offset) +try: (nir_add_inlinable_uniforms:=dll.nir_add_inlinable_uniforms).restype, nir_add_inlinable_uniforms.argtypes = None, [ctypes.POINTER(nir_src), ctypes.POINTER(nir_loop_info), ctypes.POINTER(uint32_t), ctypes.POINTER(uint8_t), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# bool nir_propagate_invariant(nir_shader *shader, bool invariant_prim) +try: (nir_propagate_invariant:=dll.nir_propagate_invariant).restype, nir_propagate_invariant.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# void nir_lower_var_copy_instr(nir_intrinsic_instr *copy, nir_shader *shader) +try: (nir_lower_var_copy_instr:=dll.nir_lower_var_copy_instr).restype, nir_lower_var_copy_instr.argtypes = None, [ctypes.POINTER(nir_intrinsic_instr), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_lower_deref_copy_instr(nir_builder *b, nir_intrinsic_instr *copy) +try: (nir_lower_deref_copy_instr:=dll.nir_lower_deref_copy_instr).restype, nir_lower_deref_copy_instr.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# bool nir_lower_var_copies(nir_shader *shader) +try: (nir_lower_var_copies:=dll.nir_lower_var_copies).restype, nir_lower_var_copies.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_memcpy(nir_shader *shader) +try: (nir_opt_memcpy:=dll.nir_opt_memcpy).restype, nir_opt_memcpy.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_memcpy(nir_shader *shader) +try: (nir_lower_memcpy:=dll.nir_lower_memcpy).restype, nir_lower_memcpy.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_fixup_deref_modes(nir_shader *shader) +try: (nir_fixup_deref_modes:=dll.nir_fixup_deref_modes).restype, nir_fixup_deref_modes.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_fixup_deref_types(nir_shader *shader) +try: (nir_fixup_deref_types:=dll.nir_fixup_deref_types).restype, nir_fixup_deref_types.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_global_vars_to_local(nir_shader *shader) +try: (nir_lower_global_vars_to_local:=dll.nir_lower_global_vars_to_local).restype, nir_lower_global_vars_to_local.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_lower_constant_to_temp(nir_shader *shader) +try: (nir_lower_constant_to_temp:=dll.nir_lower_constant_to_temp).restype, nir_lower_constant_to_temp.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_lower_array_deref_of_vec_options = CEnum(ctypes.c_uint32) +nir_lower_direct_array_deref_of_vec_load = nir_lower_array_deref_of_vec_options.define('nir_lower_direct_array_deref_of_vec_load', 1) +nir_lower_indirect_array_deref_of_vec_load = nir_lower_array_deref_of_vec_options.define('nir_lower_indirect_array_deref_of_vec_load', 2) +nir_lower_direct_array_deref_of_vec_store = nir_lower_array_deref_of_vec_options.define('nir_lower_direct_array_deref_of_vec_store', 4) +nir_lower_indirect_array_deref_of_vec_store = nir_lower_array_deref_of_vec_options.define('nir_lower_indirect_array_deref_of_vec_store', 8) + +# bool nir_lower_array_deref_of_vec(nir_shader *shader, nir_variable_mode modes, bool (*filter)(nir_variable *), nir_lower_array_deref_of_vec_options options) +try: (nir_lower_array_deref_of_vec:=dll.nir_lower_array_deref_of_vec).restype, nir_lower_array_deref_of_vec.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(nir_variable)), nir_lower_array_deref_of_vec_options] +except AttributeError: pass + +# bool nir_lower_indirect_derefs(nir_shader *shader, nir_variable_mode modes, uint32_t max_lower_array_len) +try: (nir_lower_indirect_derefs:=dll.nir_lower_indirect_derefs).restype, nir_lower_indirect_derefs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, uint32_t] +except AttributeError: pass + +# bool nir_lower_indirect_var_derefs(nir_shader *shader, const struct set *vars) +try: (nir_lower_indirect_var_derefs:=dll.nir_lower_indirect_var_derefs).restype, nir_lower_indirect_var_derefs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_set)] +except AttributeError: pass + +# bool nir_lower_locals_to_regs(nir_shader *shader, uint8_t bool_bitsize) +try: (nir_lower_locals_to_regs:=dll.nir_lower_locals_to_regs).restype, nir_lower_locals_to_regs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), uint8_t] +except AttributeError: pass + +# bool nir_lower_io_vars_to_temporaries(nir_shader *shader, nir_function_impl *entrypoint, bool outputs, bool inputs) +try: (nir_lower_io_vars_to_temporaries:=dll.nir_lower_io_vars_to_temporaries).restype, nir_lower_io_vars_to_temporaries.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_function_impl), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +class const_struct_glsl_type(Struct): pass +const_struct_glsl_type._fields_ = [ + ('gl_type', uint32_t), + ('base_type', enum_glsl_base_type,8), + ('sampled_type', enum_glsl_base_type,8), + ('sampler_dimensionality', ctypes.c_uint32,4), + ('sampler_shadow', ctypes.c_uint32,1), + ('sampler_array', ctypes.c_uint32,1), + ('interface_packing', ctypes.c_uint32,2), + ('interface_row_major', ctypes.c_uint32,1), + ('cmat_desc', struct_glsl_cmat_description), + ('packed', ctypes.c_uint32,1), + ('has_builtin_name', ctypes.c_uint32,1), + ('vector_elements', uint8_t), + ('matrix_columns', uint8_t), + ('length', ctypes.c_uint32), + ('name_id', uintptr_t), + ('explicit_stride', ctypes.c_uint32), + ('explicit_alignment', ctypes.c_uint32), + ('fields', struct_glsl_type_fields), +] +glsl_type_size_align_func = ctypes.CFUNCTYPE(None, ctypes.POINTER(const_struct_glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)) +# bool nir_lower_vars_to_scratch(nir_shader *shader, nir_variable_mode modes, int size_threshold, glsl_type_size_align_func variable_size_align, glsl_type_size_align_func scratch_layout_size_align) +try: (nir_lower_vars_to_scratch:=dll.nir_lower_vars_to_scratch).restype, nir_lower_vars_to_scratch.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.c_int32, glsl_type_size_align_func, glsl_type_size_align_func] +except AttributeError: pass + +# bool nir_lower_scratch_to_var(nir_shader *nir) +try: (nir_lower_scratch_to_var:=dll.nir_lower_scratch_to_var).restype, nir_lower_scratch_to_var.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_clip_halfz(nir_shader *shader) +try: (nir_lower_clip_halfz:=dll.nir_lower_clip_halfz).restype, nir_lower_clip_halfz.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint) +try: (nir_shader_gather_info:=dll.nir_shader_gather_info).restype, nir_shader_gather_info.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# void nir_gather_types(nir_function_impl *impl, unsigned int *float_types, unsigned int *int_types) +try: (nir_gather_types:=dll.nir_gather_types).restype, nir_gather_types.argtypes = None, [ctypes.POINTER(nir_function_impl), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# bool nir_remove_unused_varyings(nir_shader *producer, nir_shader *consumer) +try: (nir_remove_unused_varyings:=dll.nir_remove_unused_varyings).restype, nir_remove_unused_varyings.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_remove_unused_io_vars(nir_shader *shader, nir_variable_mode mode, uint64_t *used_by_other_stage, uint64_t *used_by_other_stage_patches) +try: (nir_remove_unused_io_vars:=dll.nir_remove_unused_io_vars).restype, nir_remove_unused_io_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.POINTER(uint64_t), ctypes.POINTER(uint64_t)] +except AttributeError: pass + +# void nir_compact_varyings(nir_shader *producer, nir_shader *consumer, bool default_to_smooth_interp) +try: (nir_compact_varyings:=dll.nir_compact_varyings).restype, nir_compact_varyings.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# void nir_link_xfb_varyings(nir_shader *producer, nir_shader *consumer) +try: (nir_link_xfb_varyings:=dll.nir_link_xfb_varyings).restype, nir_link_xfb_varyings.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_link_opt_varyings(nir_shader *producer, nir_shader *consumer) +try: (nir_link_opt_varyings:=dll.nir_link_opt_varyings).restype, nir_link_opt_varyings.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_link_varying_precision(nir_shader *producer, nir_shader *consumer) +try: (nir_link_varying_precision:=dll.nir_link_varying_precision).restype, nir_link_varying_precision.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_variable *nir_clone_uniform_variable(nir_shader *nir, nir_variable *uniform, bool spirv) +try: (nir_clone_uniform_variable:=dll.nir_clone_uniform_variable).restype, nir_clone_uniform_variable.argtypes = ctypes.POINTER(nir_variable), [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_variable), ctypes.c_bool] +except AttributeError: pass + +# nir_deref_instr *nir_clone_deref_instr(nir_builder *b, nir_variable *var, nir_deref_instr *deref) +try: (nir_clone_deref_instr:=dll.nir_clone_deref_instr).restype, nir_clone_deref_instr.argtypes = ctypes.POINTER(nir_deref_instr), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_variable), ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +nir_opt_varyings_progress = CEnum(ctypes.c_uint32) +nir_progress_producer = nir_opt_varyings_progress.define('nir_progress_producer', 1) +nir_progress_consumer = nir_opt_varyings_progress.define('nir_progress_consumer', 2) + +# nir_opt_varyings_progress nir_opt_varyings(nir_shader *producer, nir_shader *consumer, bool spirv, unsigned int max_uniform_components, unsigned int max_ubos_per_stage, bool debug_no_algebraic) +try: (nir_opt_varyings:=dll.nir_opt_varyings).restype, nir_opt_varyings.argtypes = nir_opt_varyings_progress, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader), ctypes.c_bool, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool] +except AttributeError: pass + +gl_varying_slot = CEnum(ctypes.c_uint32) +VARYING_SLOT_POS = gl_varying_slot.define('VARYING_SLOT_POS', 0) +VARYING_SLOT_COL0 = gl_varying_slot.define('VARYING_SLOT_COL0', 1) +VARYING_SLOT_COL1 = gl_varying_slot.define('VARYING_SLOT_COL1', 2) +VARYING_SLOT_FOGC = gl_varying_slot.define('VARYING_SLOT_FOGC', 3) +VARYING_SLOT_TEX0 = gl_varying_slot.define('VARYING_SLOT_TEX0', 4) +VARYING_SLOT_TEX1 = gl_varying_slot.define('VARYING_SLOT_TEX1', 5) +VARYING_SLOT_TEX2 = gl_varying_slot.define('VARYING_SLOT_TEX2', 6) +VARYING_SLOT_TEX3 = gl_varying_slot.define('VARYING_SLOT_TEX3', 7) +VARYING_SLOT_TEX4 = gl_varying_slot.define('VARYING_SLOT_TEX4', 8) +VARYING_SLOT_TEX5 = gl_varying_slot.define('VARYING_SLOT_TEX5', 9) +VARYING_SLOT_TEX6 = gl_varying_slot.define('VARYING_SLOT_TEX6', 10) +VARYING_SLOT_TEX7 = gl_varying_slot.define('VARYING_SLOT_TEX7', 11) +VARYING_SLOT_PSIZ = gl_varying_slot.define('VARYING_SLOT_PSIZ', 12) +VARYING_SLOT_BFC0 = gl_varying_slot.define('VARYING_SLOT_BFC0', 13) +VARYING_SLOT_BFC1 = gl_varying_slot.define('VARYING_SLOT_BFC1', 14) +VARYING_SLOT_EDGE = gl_varying_slot.define('VARYING_SLOT_EDGE', 15) +VARYING_SLOT_CLIP_VERTEX = gl_varying_slot.define('VARYING_SLOT_CLIP_VERTEX', 16) +VARYING_SLOT_CLIP_DIST0 = gl_varying_slot.define('VARYING_SLOT_CLIP_DIST0', 17) +VARYING_SLOT_CLIP_DIST1 = gl_varying_slot.define('VARYING_SLOT_CLIP_DIST1', 18) +VARYING_SLOT_CULL_DIST0 = gl_varying_slot.define('VARYING_SLOT_CULL_DIST0', 19) +VARYING_SLOT_CULL_DIST1 = gl_varying_slot.define('VARYING_SLOT_CULL_DIST1', 20) +VARYING_SLOT_PRIMITIVE_ID = gl_varying_slot.define('VARYING_SLOT_PRIMITIVE_ID', 21) +VARYING_SLOT_LAYER = gl_varying_slot.define('VARYING_SLOT_LAYER', 22) +VARYING_SLOT_VIEWPORT = gl_varying_slot.define('VARYING_SLOT_VIEWPORT', 23) +VARYING_SLOT_FACE = gl_varying_slot.define('VARYING_SLOT_FACE', 24) +VARYING_SLOT_PNTC = gl_varying_slot.define('VARYING_SLOT_PNTC', 25) +VARYING_SLOT_TESS_LEVEL_OUTER = gl_varying_slot.define('VARYING_SLOT_TESS_LEVEL_OUTER', 26) +VARYING_SLOT_TESS_LEVEL_INNER = gl_varying_slot.define('VARYING_SLOT_TESS_LEVEL_INNER', 27) +VARYING_SLOT_BOUNDING_BOX0 = gl_varying_slot.define('VARYING_SLOT_BOUNDING_BOX0', 28) +VARYING_SLOT_BOUNDING_BOX1 = gl_varying_slot.define('VARYING_SLOT_BOUNDING_BOX1', 29) +VARYING_SLOT_VIEW_INDEX = gl_varying_slot.define('VARYING_SLOT_VIEW_INDEX', 30) +VARYING_SLOT_VIEWPORT_MASK = gl_varying_slot.define('VARYING_SLOT_VIEWPORT_MASK', 31) +VARYING_SLOT_PRIMITIVE_SHADING_RATE = gl_varying_slot.define('VARYING_SLOT_PRIMITIVE_SHADING_RATE', 24) +VARYING_SLOT_PRIMITIVE_COUNT = gl_varying_slot.define('VARYING_SLOT_PRIMITIVE_COUNT', 26) +VARYING_SLOT_PRIMITIVE_INDICES = gl_varying_slot.define('VARYING_SLOT_PRIMITIVE_INDICES', 27) +VARYING_SLOT_TASK_COUNT = gl_varying_slot.define('VARYING_SLOT_TASK_COUNT', 28) +VARYING_SLOT_CULL_PRIMITIVE = gl_varying_slot.define('VARYING_SLOT_CULL_PRIMITIVE', 28) +VARYING_SLOT_VAR0 = gl_varying_slot.define('VARYING_SLOT_VAR0', 32) +VARYING_SLOT_VAR1 = gl_varying_slot.define('VARYING_SLOT_VAR1', 33) +VARYING_SLOT_VAR2 = gl_varying_slot.define('VARYING_SLOT_VAR2', 34) +VARYING_SLOT_VAR3 = gl_varying_slot.define('VARYING_SLOT_VAR3', 35) +VARYING_SLOT_VAR4 = gl_varying_slot.define('VARYING_SLOT_VAR4', 36) +VARYING_SLOT_VAR5 = gl_varying_slot.define('VARYING_SLOT_VAR5', 37) +VARYING_SLOT_VAR6 = gl_varying_slot.define('VARYING_SLOT_VAR6', 38) +VARYING_SLOT_VAR7 = gl_varying_slot.define('VARYING_SLOT_VAR7', 39) +VARYING_SLOT_VAR8 = gl_varying_slot.define('VARYING_SLOT_VAR8', 40) +VARYING_SLOT_VAR9 = gl_varying_slot.define('VARYING_SLOT_VAR9', 41) +VARYING_SLOT_VAR10 = gl_varying_slot.define('VARYING_SLOT_VAR10', 42) +VARYING_SLOT_VAR11 = gl_varying_slot.define('VARYING_SLOT_VAR11', 43) +VARYING_SLOT_VAR12 = gl_varying_slot.define('VARYING_SLOT_VAR12', 44) +VARYING_SLOT_VAR13 = gl_varying_slot.define('VARYING_SLOT_VAR13', 45) +VARYING_SLOT_VAR14 = gl_varying_slot.define('VARYING_SLOT_VAR14', 46) +VARYING_SLOT_VAR15 = gl_varying_slot.define('VARYING_SLOT_VAR15', 47) +VARYING_SLOT_VAR16 = gl_varying_slot.define('VARYING_SLOT_VAR16', 48) +VARYING_SLOT_VAR17 = gl_varying_slot.define('VARYING_SLOT_VAR17', 49) +VARYING_SLOT_VAR18 = gl_varying_slot.define('VARYING_SLOT_VAR18', 50) +VARYING_SLOT_VAR19 = gl_varying_slot.define('VARYING_SLOT_VAR19', 51) +VARYING_SLOT_VAR20 = gl_varying_slot.define('VARYING_SLOT_VAR20', 52) +VARYING_SLOT_VAR21 = gl_varying_slot.define('VARYING_SLOT_VAR21', 53) +VARYING_SLOT_VAR22 = gl_varying_slot.define('VARYING_SLOT_VAR22', 54) +VARYING_SLOT_VAR23 = gl_varying_slot.define('VARYING_SLOT_VAR23', 55) +VARYING_SLOT_VAR24 = gl_varying_slot.define('VARYING_SLOT_VAR24', 56) +VARYING_SLOT_VAR25 = gl_varying_slot.define('VARYING_SLOT_VAR25', 57) +VARYING_SLOT_VAR26 = gl_varying_slot.define('VARYING_SLOT_VAR26', 58) +VARYING_SLOT_VAR27 = gl_varying_slot.define('VARYING_SLOT_VAR27', 59) +VARYING_SLOT_VAR28 = gl_varying_slot.define('VARYING_SLOT_VAR28', 60) +VARYING_SLOT_VAR29 = gl_varying_slot.define('VARYING_SLOT_VAR29', 61) +VARYING_SLOT_VAR30 = gl_varying_slot.define('VARYING_SLOT_VAR30', 62) +VARYING_SLOT_VAR31 = gl_varying_slot.define('VARYING_SLOT_VAR31', 63) +VARYING_SLOT_PATCH0 = gl_varying_slot.define('VARYING_SLOT_PATCH0', 64) +VARYING_SLOT_PATCH1 = gl_varying_slot.define('VARYING_SLOT_PATCH1', 65) +VARYING_SLOT_PATCH2 = gl_varying_slot.define('VARYING_SLOT_PATCH2', 66) +VARYING_SLOT_PATCH3 = gl_varying_slot.define('VARYING_SLOT_PATCH3', 67) +VARYING_SLOT_PATCH4 = gl_varying_slot.define('VARYING_SLOT_PATCH4', 68) +VARYING_SLOT_PATCH5 = gl_varying_slot.define('VARYING_SLOT_PATCH5', 69) +VARYING_SLOT_PATCH6 = gl_varying_slot.define('VARYING_SLOT_PATCH6', 70) +VARYING_SLOT_PATCH7 = gl_varying_slot.define('VARYING_SLOT_PATCH7', 71) +VARYING_SLOT_PATCH8 = gl_varying_slot.define('VARYING_SLOT_PATCH8', 72) +VARYING_SLOT_PATCH9 = gl_varying_slot.define('VARYING_SLOT_PATCH9', 73) +VARYING_SLOT_PATCH10 = gl_varying_slot.define('VARYING_SLOT_PATCH10', 74) +VARYING_SLOT_PATCH11 = gl_varying_slot.define('VARYING_SLOT_PATCH11', 75) +VARYING_SLOT_PATCH12 = gl_varying_slot.define('VARYING_SLOT_PATCH12', 76) +VARYING_SLOT_PATCH13 = gl_varying_slot.define('VARYING_SLOT_PATCH13', 77) +VARYING_SLOT_PATCH14 = gl_varying_slot.define('VARYING_SLOT_PATCH14', 78) +VARYING_SLOT_PATCH15 = gl_varying_slot.define('VARYING_SLOT_PATCH15', 79) +VARYING_SLOT_PATCH16 = gl_varying_slot.define('VARYING_SLOT_PATCH16', 80) +VARYING_SLOT_PATCH17 = gl_varying_slot.define('VARYING_SLOT_PATCH17', 81) +VARYING_SLOT_PATCH18 = gl_varying_slot.define('VARYING_SLOT_PATCH18', 82) +VARYING_SLOT_PATCH19 = gl_varying_slot.define('VARYING_SLOT_PATCH19', 83) +VARYING_SLOT_PATCH20 = gl_varying_slot.define('VARYING_SLOT_PATCH20', 84) +VARYING_SLOT_PATCH21 = gl_varying_slot.define('VARYING_SLOT_PATCH21', 85) +VARYING_SLOT_PATCH22 = gl_varying_slot.define('VARYING_SLOT_PATCH22', 86) +VARYING_SLOT_PATCH23 = gl_varying_slot.define('VARYING_SLOT_PATCH23', 87) +VARYING_SLOT_PATCH24 = gl_varying_slot.define('VARYING_SLOT_PATCH24', 88) +VARYING_SLOT_PATCH25 = gl_varying_slot.define('VARYING_SLOT_PATCH25', 89) +VARYING_SLOT_PATCH26 = gl_varying_slot.define('VARYING_SLOT_PATCH26', 90) +VARYING_SLOT_PATCH27 = gl_varying_slot.define('VARYING_SLOT_PATCH27', 91) +VARYING_SLOT_PATCH28 = gl_varying_slot.define('VARYING_SLOT_PATCH28', 92) +VARYING_SLOT_PATCH29 = gl_varying_slot.define('VARYING_SLOT_PATCH29', 93) +VARYING_SLOT_PATCH30 = gl_varying_slot.define('VARYING_SLOT_PATCH30', 94) +VARYING_SLOT_PATCH31 = gl_varying_slot.define('VARYING_SLOT_PATCH31', 95) +VARYING_SLOT_VAR0_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR0_16BIT', 96) +VARYING_SLOT_VAR1_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR1_16BIT', 97) +VARYING_SLOT_VAR2_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR2_16BIT', 98) +VARYING_SLOT_VAR3_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR3_16BIT', 99) +VARYING_SLOT_VAR4_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR4_16BIT', 100) +VARYING_SLOT_VAR5_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR5_16BIT', 101) +VARYING_SLOT_VAR6_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR6_16BIT', 102) +VARYING_SLOT_VAR7_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR7_16BIT', 103) +VARYING_SLOT_VAR8_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR8_16BIT', 104) +VARYING_SLOT_VAR9_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR9_16BIT', 105) +VARYING_SLOT_VAR10_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR10_16BIT', 106) +VARYING_SLOT_VAR11_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR11_16BIT', 107) +VARYING_SLOT_VAR12_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR12_16BIT', 108) +VARYING_SLOT_VAR13_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR13_16BIT', 109) +VARYING_SLOT_VAR14_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR14_16BIT', 110) +VARYING_SLOT_VAR15_16BIT = gl_varying_slot.define('VARYING_SLOT_VAR15_16BIT', 111) +NUM_TOTAL_VARYING_SLOTS = gl_varying_slot.define('NUM_TOTAL_VARYING_SLOTS', 112) + +# bool nir_slot_is_sysval_output(gl_varying_slot slot, gl_shader_stage next_shader) +try: (nir_slot_is_sysval_output:=dll.nir_slot_is_sysval_output).restype, nir_slot_is_sysval_output.argtypes = ctypes.c_bool, [gl_varying_slot, gl_shader_stage] +except AttributeError: pass + +# bool nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader) +try: (nir_slot_is_varying:=dll.nir_slot_is_varying).restype, nir_slot_is_varying.argtypes = ctypes.c_bool, [gl_varying_slot, gl_shader_stage] +except AttributeError: pass + +# bool nir_slot_is_sysval_output_and_varying(gl_varying_slot slot, gl_shader_stage next_shader) +try: (nir_slot_is_sysval_output_and_varying:=dll.nir_slot_is_sysval_output_and_varying).restype, nir_slot_is_sysval_output_and_varying.argtypes = ctypes.c_bool, [gl_varying_slot, gl_shader_stage] +except AttributeError: pass + +# bool nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader) +try: (nir_remove_varying:=dll.nir_remove_varying).restype, nir_remove_varying.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_intrinsic_instr), gl_shader_stage] +except AttributeError: pass + +# bool nir_remove_sysval_output(nir_intrinsic_instr *intr, gl_shader_stage next_shader) +try: (nir_remove_sysval_output:=dll.nir_remove_sysval_output).restype, nir_remove_sysval_output.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_intrinsic_instr), gl_shader_stage] +except AttributeError: pass + +# bool nir_lower_amul(nir_shader *shader, int (*type_size)(const struct glsl_type *, bool)) +try: (nir_lower_amul:=dll.nir_lower_amul).restype, nir_lower_amul.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(const_struct_glsl_type), ctypes.c_bool)] +except AttributeError: pass + +# bool nir_lower_ubo_vec4(nir_shader *shader) +try: (nir_lower_ubo_vec4:=dll.nir_lower_ubo_vec4).restype, nir_lower_ubo_vec4.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_sort_variables_by_location(nir_shader *shader, nir_variable_mode mode) +try: (nir_sort_variables_by_location:=dll.nir_sort_variables_by_location).restype, nir_sort_variables_by_location.argtypes = None, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# void nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode, unsigned int *size, gl_shader_stage stage) +try: (nir_assign_io_var_locations:=dll.nir_assign_io_var_locations).restype, nir_assign_io_var_locations.argtypes = None, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.POINTER(ctypes.c_uint32), gl_shader_stage] +except AttributeError: pass + +# bool nir_opt_clip_cull_const(nir_shader *shader) +try: (nir_opt_clip_cull_const:=dll.nir_opt_clip_cull_const).restype, nir_opt_clip_cull_const.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_lower_io_options = CEnum(ctypes.c_uint32) +nir_lower_io_lower_64bit_to_32 = nir_lower_io_options.define('nir_lower_io_lower_64bit_to_32', 1) +nir_lower_io_lower_64bit_float_to_32 = nir_lower_io_options.define('nir_lower_io_lower_64bit_float_to_32', 2) +nir_lower_io_lower_64bit_to_32_new = nir_lower_io_options.define('nir_lower_io_lower_64bit_to_32_new', 4) +nir_lower_io_use_interpolated_input_intrinsics = nir_lower_io_options.define('nir_lower_io_use_interpolated_input_intrinsics', 8) + +# bool nir_lower_io(nir_shader *shader, nir_variable_mode modes, int (*type_size)(const struct glsl_type *, bool), nir_lower_io_options) +try: (nir_lower_io:=dll.nir_lower_io).restype, nir_lower_io.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(const_struct_glsl_type), ctypes.c_bool), nir_lower_io_options] +except AttributeError: pass + +# bool nir_io_add_const_offset_to_base(nir_shader *nir, nir_variable_mode modes) +try: (nir_io_add_const_offset_to_base:=dll.nir_io_add_const_offset_to_base).restype, nir_io_add_const_offset_to_base.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# void nir_lower_io_passes(nir_shader *nir, bool renumber_vs_inputs) +try: (nir_lower_io_passes:=dll.nir_lower_io_passes).restype, nir_lower_io_passes.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_io_add_intrinsic_xfb_info(nir_shader *nir) +try: (nir_io_add_intrinsic_xfb_info:=dll.nir_io_add_intrinsic_xfb_info).restype, nir_io_add_intrinsic_xfb_info.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_io_indirect_loads(nir_shader *nir, nir_variable_mode modes) +try: (nir_lower_io_indirect_loads:=dll.nir_lower_io_indirect_loads).restype, nir_lower_io_indirect_loads.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_lower_vars_to_explicit_types(nir_shader *shader, nir_variable_mode modes, glsl_type_size_align_func type_info) +try: (nir_lower_vars_to_explicit_types:=dll.nir_lower_vars_to_explicit_types).restype, nir_lower_vars_to_explicit_types.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, glsl_type_size_align_func] +except AttributeError: pass + +# void nir_gather_explicit_io_initializers(nir_shader *shader, void *dst, size_t dst_size, nir_variable_mode mode) +try: (nir_gather_explicit_io_initializers:=dll.nir_gather_explicit_io_initializers).restype, nir_gather_explicit_io_initializers.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.c_void_p, size_t, nir_variable_mode] +except AttributeError: pass + +# bool nir_lower_vec3_to_vec4(nir_shader *shader, nir_variable_mode modes) +try: (nir_lower_vec3_to_vec4:=dll.nir_lower_vec3_to_vec4).restype, nir_lower_vec3_to_vec4.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +nir_address_format = CEnum(ctypes.c_uint32) +nir_address_format_32bit_global = nir_address_format.define('nir_address_format_32bit_global', 0) +nir_address_format_64bit_global = nir_address_format.define('nir_address_format_64bit_global', 1) +nir_address_format_2x32bit_global = nir_address_format.define('nir_address_format_2x32bit_global', 2) +nir_address_format_64bit_global_32bit_offset = nir_address_format.define('nir_address_format_64bit_global_32bit_offset', 3) +nir_address_format_64bit_bounded_global = nir_address_format.define('nir_address_format_64bit_bounded_global', 4) +nir_address_format_32bit_index_offset = nir_address_format.define('nir_address_format_32bit_index_offset', 5) +nir_address_format_32bit_index_offset_pack64 = nir_address_format.define('nir_address_format_32bit_index_offset_pack64', 6) +nir_address_format_vec2_index_32bit_offset = nir_address_format.define('nir_address_format_vec2_index_32bit_offset', 7) +nir_address_format_62bit_generic = nir_address_format.define('nir_address_format_62bit_generic', 8) +nir_address_format_32bit_offset = nir_address_format.define('nir_address_format_32bit_offset', 9) +nir_address_format_32bit_offset_as_64bit = nir_address_format.define('nir_address_format_32bit_offset_as_64bit', 10) +nir_address_format_logical = nir_address_format.define('nir_address_format_logical', 11) + +# unsigned int nir_address_format_bit_size(nir_address_format addr_format) +try: (nir_address_format_bit_size:=dll.nir_address_format_bit_size).restype, nir_address_format_bit_size.argtypes = ctypes.c_uint32, [nir_address_format] +except AttributeError: pass + +# unsigned int nir_address_format_num_components(nir_address_format addr_format) +try: (nir_address_format_num_components:=dll.nir_address_format_num_components).restype, nir_address_format_num_components.argtypes = ctypes.c_uint32, [nir_address_format] +except AttributeError: pass + +# const nir_const_value *nir_address_format_null_value(nir_address_format addr_format) +try: (nir_address_format_null_value:=dll.nir_address_format_null_value).restype, nir_address_format_null_value.argtypes = ctypes.POINTER(nir_const_value), [nir_address_format] +except AttributeError: pass + +# nir_def *nir_build_addr_iadd(nir_builder *b, nir_def *addr, nir_address_format addr_format, nir_variable_mode modes, nir_def *offset) +try: (nir_build_addr_iadd:=dll.nir_build_addr_iadd).restype, nir_build_addr_iadd.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), nir_address_format, nir_variable_mode, ctypes.POINTER(nir_def)] +except AttributeError: pass + +# nir_def *nir_build_addr_iadd_imm(nir_builder *b, nir_def *addr, nir_address_format addr_format, nir_variable_mode modes, int64_t offset) +try: (nir_build_addr_iadd_imm:=dll.nir_build_addr_iadd_imm).restype, nir_build_addr_iadd_imm.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), nir_address_format, nir_variable_mode, int64_t] +except AttributeError: pass + +# nir_def *nir_build_addr_ieq(nir_builder *b, nir_def *addr0, nir_def *addr1, nir_address_format addr_format) +try: (nir_build_addr_ieq:=dll.nir_build_addr_ieq).restype, nir_build_addr_ieq.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), nir_address_format] +except AttributeError: pass + +# nir_def *nir_build_addr_isub(nir_builder *b, nir_def *addr0, nir_def *addr1, nir_address_format addr_format) +try: (nir_build_addr_isub:=dll.nir_build_addr_isub).restype, nir_build_addr_isub.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), nir_address_format] +except AttributeError: pass + +# nir_def *nir_explicit_io_address_from_deref(nir_builder *b, nir_deref_instr *deref, nir_def *base_addr, nir_address_format addr_format) +try: (nir_explicit_io_address_from_deref:=dll.nir_explicit_io_address_from_deref).restype, nir_explicit_io_address_from_deref.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_deref_instr), ctypes.POINTER(nir_def), nir_address_format] +except AttributeError: pass + +# bool nir_get_explicit_deref_align(nir_deref_instr *deref, bool default_to_type_align, uint32_t *align_mul, uint32_t *align_offset) +try: (nir_get_explicit_deref_align:=dll.nir_get_explicit_deref_align).restype, nir_get_explicit_deref_align.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr), ctypes.c_bool, ctypes.POINTER(uint32_t), ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# void nir_lower_explicit_io_instr(nir_builder *b, nir_intrinsic_instr *io_instr, nir_def *addr, nir_address_format addr_format) +try: (nir_lower_explicit_io_instr:=dll.nir_lower_explicit_io_instr).restype, nir_lower_explicit_io_instr.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_intrinsic_instr), ctypes.POINTER(nir_def), nir_address_format] +except AttributeError: pass + +# bool nir_lower_explicit_io(nir_shader *shader, nir_variable_mode modes, nir_address_format) +try: (nir_lower_explicit_io:=dll.nir_lower_explicit_io).restype, nir_lower_explicit_io.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, nir_address_format] +except AttributeError: pass + +nir_mem_access_shift_method = CEnum(ctypes.c_uint32) +nir_mem_access_shift_method_scalar = nir_mem_access_shift_method.define('nir_mem_access_shift_method_scalar', 0) +nir_mem_access_shift_method_shift64 = nir_mem_access_shift_method.define('nir_mem_access_shift_method_shift64', 1) +nir_mem_access_shift_method_bytealign_amd = nir_mem_access_shift_method.define('nir_mem_access_shift_method_bytealign_amd', 2) + +class struct_nir_mem_access_size_align(Struct): pass +struct_nir_mem_access_size_align._fields_ = [ + ('num_components', uint8_t), + ('bit_size', uint8_t), + ('align', uint16_t), + ('shift', nir_mem_access_shift_method), +] +nir_mem_access_size_align = struct_nir_mem_access_size_align +enum_gl_access_qualifier = CEnum(ctypes.c_uint32) +ACCESS_COHERENT = enum_gl_access_qualifier.define('ACCESS_COHERENT', 1) +ACCESS_RESTRICT = enum_gl_access_qualifier.define('ACCESS_RESTRICT', 2) +ACCESS_VOLATILE = enum_gl_access_qualifier.define('ACCESS_VOLATILE', 4) +ACCESS_NON_READABLE = enum_gl_access_qualifier.define('ACCESS_NON_READABLE', 8) +ACCESS_NON_WRITEABLE = enum_gl_access_qualifier.define('ACCESS_NON_WRITEABLE', 16) +ACCESS_NON_UNIFORM = enum_gl_access_qualifier.define('ACCESS_NON_UNIFORM', 32) +ACCESS_CAN_REORDER = enum_gl_access_qualifier.define('ACCESS_CAN_REORDER', 64) +ACCESS_NON_TEMPORAL = enum_gl_access_qualifier.define('ACCESS_NON_TEMPORAL', 128) +ACCESS_INCLUDE_HELPERS = enum_gl_access_qualifier.define('ACCESS_INCLUDE_HELPERS', 256) +ACCESS_IS_SWIZZLED_AMD = enum_gl_access_qualifier.define('ACCESS_IS_SWIZZLED_AMD', 512) +ACCESS_USES_FORMAT_AMD = enum_gl_access_qualifier.define('ACCESS_USES_FORMAT_AMD', 1024) +ACCESS_FMASK_LOWERED_AMD = enum_gl_access_qualifier.define('ACCESS_FMASK_LOWERED_AMD', 2048) +ACCESS_CAN_SPECULATE = enum_gl_access_qualifier.define('ACCESS_CAN_SPECULATE', 4096) +ACCESS_CP_GE_COHERENT_AMD = enum_gl_access_qualifier.define('ACCESS_CP_GE_COHERENT_AMD', 8192) +ACCESS_IN_BOUNDS = enum_gl_access_qualifier.define('ACCESS_IN_BOUNDS', 16384) +ACCESS_KEEP_SCALAR = enum_gl_access_qualifier.define('ACCESS_KEEP_SCALAR', 32768) +ACCESS_SMEM_AMD = enum_gl_access_qualifier.define('ACCESS_SMEM_AMD', 65536) + +nir_lower_mem_access_bit_sizes_cb = ctypes.CFUNCTYPE(struct_nir_mem_access_size_align, nir_intrinsic_op, ctypes.c_ubyte, ctypes.c_ubyte, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, enum_gl_access_qualifier, ctypes.c_void_p) +class struct_nir_lower_mem_access_bit_sizes_options(Struct): pass +struct_nir_lower_mem_access_bit_sizes_options._fields_ = [ + ('callback', nir_lower_mem_access_bit_sizes_cb), + ('modes', nir_variable_mode), + ('may_lower_unaligned_stores_to_atomics', ctypes.c_bool), + ('cb_data', ctypes.c_void_p), +] +nir_lower_mem_access_bit_sizes_options = struct_nir_lower_mem_access_bit_sizes_options +# bool nir_lower_mem_access_bit_sizes(nir_shader *shader, const nir_lower_mem_access_bit_sizes_options *options) +try: (nir_lower_mem_access_bit_sizes:=dll.nir_lower_mem_access_bit_sizes).restype, nir_lower_mem_access_bit_sizes.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_mem_access_bit_sizes_options)] +except AttributeError: pass + +# bool nir_lower_robust_access(nir_shader *s, nir_intrin_filter_cb filter, const void *data) +try: (nir_lower_robust_access:=dll.nir_lower_robust_access).restype, nir_lower_robust_access.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_intrin_filter_cb, ctypes.c_void_p] +except AttributeError: pass + +nir_should_vectorize_mem_func = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int64, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_void_p) +class struct_nir_load_store_vectorize_options(Struct): pass +struct_nir_load_store_vectorize_options._fields_ = [ + ('callback', nir_should_vectorize_mem_func), + ('modes', nir_variable_mode), + ('robust_modes', nir_variable_mode), + ('cb_data', ctypes.c_void_p), + ('has_shared2_amd', ctypes.c_bool), +] +nir_load_store_vectorize_options = struct_nir_load_store_vectorize_options +# bool nir_opt_load_store_vectorize(nir_shader *shader, const nir_load_store_vectorize_options *options) +try: (nir_opt_load_store_vectorize:=dll.nir_opt_load_store_vectorize).restype, nir_opt_load_store_vectorize.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_load_store_vectorize_options)] +except AttributeError: pass + +# bool nir_opt_load_store_update_alignments(nir_shader *shader) +try: (nir_opt_load_store_update_alignments:=dll.nir_opt_load_store_update_alignments).restype, nir_opt_load_store_update_alignments.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_lower_shader_calls_should_remat_func = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.c_void_p) +class struct_nir_lower_shader_calls_options(Struct): pass +struct_nir_lower_shader_calls_options._fields_ = [ + ('address_format', nir_address_format), + ('stack_alignment', ctypes.c_uint32), + ('localized_loads', ctypes.c_bool), + ('vectorizer_callback', nir_should_vectorize_mem_func), + ('vectorizer_data', ctypes.c_void_p), + ('should_remat_callback', nir_lower_shader_calls_should_remat_func), + ('should_remat_data', ctypes.c_void_p), +] +nir_lower_shader_calls_options = struct_nir_lower_shader_calls_options +# bool nir_lower_shader_calls(nir_shader *shader, const nir_lower_shader_calls_options *options, nir_shader ***resume_shaders_out, uint32_t *num_resume_shaders_out, void *mem_ctx) +try: (nir_lower_shader_calls:=dll.nir_lower_shader_calls).restype, nir_lower_shader_calls.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_shader_calls_options), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(nir_shader))), ctypes.POINTER(uint32_t), ctypes.c_void_p] +except AttributeError: pass + +# int nir_get_io_offset_src_number(const nir_intrinsic_instr *instr) +try: (nir_get_io_offset_src_number:=dll.nir_get_io_offset_src_number).restype, nir_get_io_offset_src_number.argtypes = ctypes.c_int32, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# int nir_get_io_index_src_number(const nir_intrinsic_instr *instr) +try: (nir_get_io_index_src_number:=dll.nir_get_io_index_src_number).restype, nir_get_io_index_src_number.argtypes = ctypes.c_int32, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# int nir_get_io_arrayed_index_src_number(const nir_intrinsic_instr *instr) +try: (nir_get_io_arrayed_index_src_number:=dll.nir_get_io_arrayed_index_src_number).restype, nir_get_io_arrayed_index_src_number.argtypes = ctypes.c_int32, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# nir_src *nir_get_io_offset_src(nir_intrinsic_instr *instr) +try: (nir_get_io_offset_src:=dll.nir_get_io_offset_src).restype, nir_get_io_offset_src.argtypes = ctypes.POINTER(nir_src), [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# nir_src *nir_get_io_index_src(nir_intrinsic_instr *instr) +try: (nir_get_io_index_src:=dll.nir_get_io_index_src).restype, nir_get_io_index_src.argtypes = ctypes.POINTER(nir_src), [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# nir_src *nir_get_io_arrayed_index_src(nir_intrinsic_instr *instr) +try: (nir_get_io_arrayed_index_src:=dll.nir_get_io_arrayed_index_src).restype, nir_get_io_arrayed_index_src.argtypes = ctypes.POINTER(nir_src), [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# nir_src *nir_get_shader_call_payload_src(nir_intrinsic_instr *call) +try: (nir_get_shader_call_payload_src:=dll.nir_get_shader_call_payload_src).restype, nir_get_shader_call_payload_src.argtypes = ctypes.POINTER(nir_src), [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# bool nir_is_output_load(nir_intrinsic_instr *intr) +try: (nir_is_output_load:=dll.nir_is_output_load).restype, nir_is_output_load.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# bool nir_is_arrayed_io(const nir_variable *var, gl_shader_stage stage) +try: (nir_is_arrayed_io:=dll.nir_is_arrayed_io).restype, nir_is_arrayed_io.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_variable), gl_shader_stage] +except AttributeError: pass + +# bool nir_lower_reg_intrinsics_to_ssa_impl(nir_function_impl *impl) +try: (nir_lower_reg_intrinsics_to_ssa_impl:=dll.nir_lower_reg_intrinsics_to_ssa_impl).restype, nir_lower_reg_intrinsics_to_ssa_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_lower_reg_intrinsics_to_ssa(nir_shader *shader) +try: (nir_lower_reg_intrinsics_to_ssa:=dll.nir_lower_reg_intrinsics_to_ssa).restype, nir_lower_reg_intrinsics_to_ssa.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_vars_to_ssa(nir_shader *shader) +try: (nir_lower_vars_to_ssa:=dll.nir_lower_vars_to_ssa).restype, nir_lower_vars_to_ssa.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_remove_dead_derefs(nir_shader *shader) +try: (nir_remove_dead_derefs:=dll.nir_remove_dead_derefs).restype, nir_remove_dead_derefs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_remove_dead_derefs_impl(nir_function_impl *impl) +try: (nir_remove_dead_derefs_impl:=dll.nir_remove_dead_derefs_impl).restype, nir_remove_dead_derefs_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +class struct_nir_remove_dead_variables_options(Struct): pass +struct_nir_remove_dead_variables_options._fields_ = [ + ('can_remove_var', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(nir_variable), ctypes.c_void_p)), + ('can_remove_var_data', ctypes.c_void_p), +] +nir_remove_dead_variables_options = struct_nir_remove_dead_variables_options +# bool nir_remove_dead_variables(nir_shader *shader, nir_variable_mode modes, const nir_remove_dead_variables_options *options) +try: (nir_remove_dead_variables:=dll.nir_remove_dead_variables).restype, nir_remove_dead_variables.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.POINTER(nir_remove_dead_variables_options)] +except AttributeError: pass + +# bool nir_lower_variable_initializers(nir_shader *shader, nir_variable_mode modes) +try: (nir_lower_variable_initializers:=dll.nir_lower_variable_initializers).restype, nir_lower_variable_initializers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_zero_initialize_shared_memory(nir_shader *shader, const unsigned int shared_size, const unsigned int chunk_size) +try: (nir_zero_initialize_shared_memory:=dll.nir_zero_initialize_shared_memory).restype, nir_zero_initialize_shared_memory.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# bool nir_clear_shared_memory(nir_shader *shader, const unsigned int shared_size, const unsigned int chunk_size) +try: (nir_clear_shared_memory:=dll.nir_clear_shared_memory).restype, nir_clear_shared_memory.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +nir_opt_move_to_top_options = CEnum(ctypes.c_uint32) +nir_move_to_entry_block_only = nir_opt_move_to_top_options.define('nir_move_to_entry_block_only', 1) +nir_move_to_top_input_loads = nir_opt_move_to_top_options.define('nir_move_to_top_input_loads', 2) +nir_move_to_top_load_smem_amd = nir_opt_move_to_top_options.define('nir_move_to_top_load_smem_amd', 4) + +# bool nir_opt_move_to_top(nir_shader *nir, nir_opt_move_to_top_options options) +try: (nir_opt_move_to_top:=dll.nir_opt_move_to_top).restype, nir_opt_move_to_top.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_opt_move_to_top_options] +except AttributeError: pass + +# bool nir_move_vec_src_uses_to_dest(nir_shader *shader, bool skip_const_srcs) +try: (nir_move_vec_src_uses_to_dest:=dll.nir_move_vec_src_uses_to_dest).restype, nir_move_vec_src_uses_to_dest.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_move_output_stores_to_end(nir_shader *nir) +try: (nir_move_output_stores_to_end:=dll.nir_move_output_stores_to_end).restype, nir_move_output_stores_to_end.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_vec_to_regs(nir_shader *shader, nir_instr_writemask_filter_cb cb, const void *_data) +try: (nir_lower_vec_to_regs:=dll.nir_lower_vec_to_regs).restype, nir_lower_vec_to_regs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_instr_writemask_filter_cb, ctypes.c_void_p] +except AttributeError: pass + +enum_compare_func = CEnum(ctypes.c_uint32) +COMPARE_FUNC_NEVER = enum_compare_func.define('COMPARE_FUNC_NEVER', 0) +COMPARE_FUNC_LESS = enum_compare_func.define('COMPARE_FUNC_LESS', 1) +COMPARE_FUNC_EQUAL = enum_compare_func.define('COMPARE_FUNC_EQUAL', 2) +COMPARE_FUNC_LEQUAL = enum_compare_func.define('COMPARE_FUNC_LEQUAL', 3) +COMPARE_FUNC_GREATER = enum_compare_func.define('COMPARE_FUNC_GREATER', 4) +COMPARE_FUNC_NOTEQUAL = enum_compare_func.define('COMPARE_FUNC_NOTEQUAL', 5) +COMPARE_FUNC_GEQUAL = enum_compare_func.define('COMPARE_FUNC_GEQUAL', 6) +COMPARE_FUNC_ALWAYS = enum_compare_func.define('COMPARE_FUNC_ALWAYS', 7) + +# bool nir_lower_alpha_test(nir_shader *shader, enum compare_func func, bool alpha_to_one, const gl_state_index16 *alpha_ref_state_tokens) +try: (nir_lower_alpha_test:=dll.nir_lower_alpha_test).restype, nir_lower_alpha_test.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), enum_compare_func, ctypes.c_bool, ctypes.POINTER(gl_state_index16)] +except AttributeError: pass + +# bool nir_lower_alpha_to_coverage(nir_shader *shader, uint8_t nr_samples, bool has_intrinsic) +try: (nir_lower_alpha_to_coverage:=dll.nir_lower_alpha_to_coverage).restype, nir_lower_alpha_to_coverage.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), uint8_t, ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_alpha_to_one(nir_shader *shader) +try: (nir_lower_alpha_to_one:=dll.nir_lower_alpha_to_one).restype, nir_lower_alpha_to_one.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_alu(nir_shader *shader) +try: (nir_lower_alu:=dll.nir_lower_alu).restype, nir_lower_alu.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_flrp(nir_shader *shader, unsigned int lowering_mask, bool always_precise) +try: (nir_lower_flrp:=dll.nir_lower_flrp).restype, nir_lower_flrp.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_bool] +except AttributeError: pass + +# bool nir_scale_fdiv(nir_shader *shader) +try: (nir_scale_fdiv:=dll.nir_scale_fdiv).restype, nir_scale_fdiv.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_alu_to_scalar(nir_shader *shader, nir_instr_filter_cb cb, const void *data) +try: (nir_lower_alu_to_scalar:=dll.nir_lower_alu_to_scalar).restype, nir_lower_alu_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_instr_filter_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_alu_width(nir_shader *shader, nir_vectorize_cb cb, const void *data) +try: (nir_lower_alu_width:=dll.nir_lower_alu_width).restype, nir_lower_alu_width.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_vectorize_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_alu_vec8_16_srcs(nir_shader *shader) +try: (nir_lower_alu_vec8_16_srcs:=dll.nir_lower_alu_vec8_16_srcs).restype, nir_lower_alu_vec8_16_srcs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_bool_to_bitsize(nir_shader *shader) +try: (nir_lower_bool_to_bitsize:=dll.nir_lower_bool_to_bitsize).restype, nir_lower_bool_to_bitsize.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_bool_to_float(nir_shader *shader, bool has_fcsel_ne) +try: (nir_lower_bool_to_float:=dll.nir_lower_bool_to_float).restype, nir_lower_bool_to_float.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_bool_to_int32(nir_shader *shader) +try: (nir_lower_bool_to_int32:=dll.nir_lower_bool_to_int32).restype, nir_lower_bool_to_int32.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_simplify_convert_alu_types(nir_shader *shader) +try: (nir_opt_simplify_convert_alu_types:=dll.nir_opt_simplify_convert_alu_types).restype, nir_opt_simplify_convert_alu_types.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_const_arrays_to_uniforms(nir_shader *shader, unsigned int max_uniform_components) +try: (nir_lower_const_arrays_to_uniforms:=dll.nir_lower_const_arrays_to_uniforms).restype, nir_lower_const_arrays_to_uniforms.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_lower_convert_alu_types(nir_shader *shader, bool (*should_lower)(nir_intrinsic_instr *)) +try: (nir_lower_convert_alu_types:=dll.nir_lower_convert_alu_types).restype, nir_lower_convert_alu_types.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(nir_intrinsic_instr))] +except AttributeError: pass + +# bool nir_lower_constant_convert_alu_types(nir_shader *shader) +try: (nir_lower_constant_convert_alu_types:=dll.nir_lower_constant_convert_alu_types).restype, nir_lower_constant_convert_alu_types.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_alu_conversion_to_intrinsic(nir_shader *shader) +try: (nir_lower_alu_conversion_to_intrinsic:=dll.nir_lower_alu_conversion_to_intrinsic).restype, nir_lower_alu_conversion_to_intrinsic.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_int_to_float(nir_shader *shader) +try: (nir_lower_int_to_float:=dll.nir_lower_int_to_float).restype, nir_lower_int_to_float.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_load_const_to_scalar(nir_shader *shader) +try: (nir_lower_load_const_to_scalar:=dll.nir_lower_load_const_to_scalar).restype, nir_lower_load_const_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_read_invocation_to_scalar(nir_shader *shader) +try: (nir_lower_read_invocation_to_scalar:=dll.nir_lower_read_invocation_to_scalar).restype, nir_lower_read_invocation_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_phis_to_scalar(nir_shader *shader, nir_vectorize_cb cb, const void *data) +try: (nir_lower_phis_to_scalar:=dll.nir_lower_phis_to_scalar).restype, nir_lower_phis_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_vectorize_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_all_phis_to_scalar(nir_shader *shader) +try: (nir_lower_all_phis_to_scalar:=dll.nir_lower_all_phis_to_scalar).restype, nir_lower_all_phis_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_lower_io_array_vars_to_elements(nir_shader *producer, nir_shader *consumer) +try: (nir_lower_io_array_vars_to_elements:=dll.nir_lower_io_array_vars_to_elements).restype, nir_lower_io_array_vars_to_elements.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_io_array_vars_to_elements_no_indirects(nir_shader *shader, bool outputs_only) +try: (nir_lower_io_array_vars_to_elements_no_indirects:=dll.nir_lower_io_array_vars_to_elements_no_indirects).restype, nir_lower_io_array_vars_to_elements_no_indirects.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_io_to_scalar(nir_shader *shader, nir_variable_mode mask, nir_instr_filter_cb filter, void *filter_data) +try: (nir_lower_io_to_scalar:=dll.nir_lower_io_to_scalar).restype, nir_lower_io_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, nir_instr_filter_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_io_vars_to_scalar(nir_shader *shader, nir_variable_mode mask) +try: (nir_lower_io_vars_to_scalar:=dll.nir_lower_io_vars_to_scalar).restype, nir_lower_io_vars_to_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_opt_vectorize_io_vars(nir_shader *shader, nir_variable_mode mask) +try: (nir_opt_vectorize_io_vars:=dll.nir_opt_vectorize_io_vars).restype, nir_opt_vectorize_io_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_lower_tess_level_array_vars_to_vec(nir_shader *shader) +try: (nir_lower_tess_level_array_vars_to_vec:=dll.nir_lower_tess_level_array_vars_to_vec).restype, nir_lower_tess_level_array_vars_to_vec.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_shader *nir_create_passthrough_tcs_impl(const nir_shader_compiler_options *options, unsigned int *locations, unsigned int num_locations, uint8_t patch_vertices) +try: (nir_create_passthrough_tcs_impl:=dll.nir_create_passthrough_tcs_impl).restype, nir_create_passthrough_tcs_impl.argtypes = ctypes.POINTER(nir_shader), [ctypes.POINTER(nir_shader_compiler_options), ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32, uint8_t] +except AttributeError: pass + +# nir_shader *nir_create_passthrough_tcs(const nir_shader_compiler_options *options, const nir_shader *vs, uint8_t patch_vertices) +try: (nir_create_passthrough_tcs:=dll.nir_create_passthrough_tcs).restype, nir_create_passthrough_tcs.argtypes = ctypes.POINTER(nir_shader), [ctypes.POINTER(nir_shader_compiler_options), ctypes.POINTER(nir_shader), uint8_t] +except AttributeError: pass + +# nir_shader *nir_create_passthrough_gs(const nir_shader_compiler_options *options, const nir_shader *prev_stage, enum mesa_prim primitive_type, enum mesa_prim output_primitive_type, bool emulate_edgeflags, bool force_line_strip_out, bool passthrough_prim_id) +try: (nir_create_passthrough_gs:=dll.nir_create_passthrough_gs).restype, nir_create_passthrough_gs.argtypes = ctypes.POINTER(nir_shader), [ctypes.POINTER(nir_shader_compiler_options), ctypes.POINTER(nir_shader), enum_mesa_prim, enum_mesa_prim, ctypes.c_bool, ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_fragcolor(nir_shader *shader, unsigned int max_cbufs) +try: (nir_lower_fragcolor:=dll.nir_lower_fragcolor).restype, nir_lower_fragcolor.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_lower_fragcoord_wtrans(nir_shader *shader) +try: (nir_lower_fragcoord_wtrans:=dll.nir_lower_fragcoord_wtrans).restype, nir_lower_fragcoord_wtrans.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_frag_coord_to_pixel_coord(nir_shader *shader) +try: (nir_opt_frag_coord_to_pixel_coord:=dll.nir_opt_frag_coord_to_pixel_coord).restype, nir_opt_frag_coord_to_pixel_coord.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_frag_coord_to_pixel_coord(nir_shader *shader) +try: (nir_lower_frag_coord_to_pixel_coord:=dll.nir_lower_frag_coord_to_pixel_coord).restype, nir_lower_frag_coord_to_pixel_coord.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_viewport_transform(nir_shader *shader) +try: (nir_lower_viewport_transform:=dll.nir_lower_viewport_transform).restype, nir_lower_viewport_transform.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_uniforms_to_ubo(nir_shader *shader, bool dword_packed, bool load_vec4) +try: (nir_lower_uniforms_to_ubo:=dll.nir_lower_uniforms_to_ubo).restype, nir_lower_uniforms_to_ubo.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_is_helper_invocation(nir_shader *shader) +try: (nir_lower_is_helper_invocation:=dll.nir_lower_is_helper_invocation).restype, nir_lower_is_helper_invocation.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_single_sampled(nir_shader *shader) +try: (nir_lower_single_sampled:=dll.nir_lower_single_sampled).restype, nir_lower_single_sampled.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_atomics(nir_shader *shader, nir_instr_filter_cb filter) +try: (nir_lower_atomics:=dll.nir_lower_atomics).restype, nir_lower_atomics.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_instr_filter_cb] +except AttributeError: pass + +class struct_nir_lower_subgroups_options(Struct): pass +struct_nir_lower_subgroups_options._fields_ = [ + ('filter', nir_instr_filter_cb), + ('filter_data', ctypes.c_void_p), + ('subgroup_size', uint8_t), + ('ballot_bit_size', uint8_t), + ('ballot_components', uint8_t), + ('lower_to_scalar', ctypes.c_bool,1), + ('lower_vote_trivial', ctypes.c_bool,1), + ('lower_vote_feq', ctypes.c_bool,1), + ('lower_vote_ieq', ctypes.c_bool,1), + ('lower_vote_bool_eq', ctypes.c_bool,1), + ('lower_first_invocation_to_ballot', ctypes.c_bool,1), + ('lower_read_first_invocation', ctypes.c_bool,1), + ('lower_subgroup_masks', ctypes.c_bool,1), + ('lower_relative_shuffle', ctypes.c_bool,1), + ('lower_shuffle_to_32bit', ctypes.c_bool,1), + ('lower_shuffle_to_swizzle_amd', ctypes.c_bool,1), + ('lower_shuffle', ctypes.c_bool,1), + ('lower_quad', ctypes.c_bool,1), + ('lower_quad_broadcast_dynamic', ctypes.c_bool,1), + ('lower_quad_broadcast_dynamic_to_const', ctypes.c_bool,1), + ('lower_quad_vote', ctypes.c_bool,1), + ('lower_elect', ctypes.c_bool,1), + ('lower_read_invocation_to_cond', ctypes.c_bool,1), + ('lower_rotate_to_shuffle', ctypes.c_bool,1), + ('lower_rotate_clustered_to_shuffle', ctypes.c_bool,1), + ('lower_ballot_bit_count_to_mbcnt_amd', ctypes.c_bool,1), + ('lower_inverse_ballot', ctypes.c_bool,1), + ('lower_reduce', ctypes.c_bool,1), + ('lower_boolean_reduce', ctypes.c_bool,1), + ('lower_boolean_shuffle', ctypes.c_bool,1), +] +nir_lower_subgroups_options = struct_nir_lower_subgroups_options +# bool nir_lower_subgroups(nir_shader *shader, const nir_lower_subgroups_options *options) +try: (nir_lower_subgroups:=dll.nir_lower_subgroups).restype, nir_lower_subgroups.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_subgroups_options)] +except AttributeError: pass + +# bool nir_lower_system_values(nir_shader *shader) +try: (nir_lower_system_values:=dll.nir_lower_system_values).restype, nir_lower_system_values.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_def *nir_build_lowered_load_helper_invocation(nir_builder *b) +try: (nir_build_lowered_load_helper_invocation:=dll.nir_build_lowered_load_helper_invocation).restype, nir_build_lowered_load_helper_invocation.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder)] +except AttributeError: pass + +class struct_nir_lower_compute_system_values_options(Struct): pass +struct_nir_lower_compute_system_values_options._fields_ = [ + ('has_base_global_invocation_id', ctypes.c_bool,1), + ('has_base_workgroup_id', ctypes.c_bool,1), + ('has_global_size', ctypes.c_bool,1), + ('shuffle_local_ids_for_quad_derivatives', ctypes.c_bool,1), + ('lower_local_invocation_index', ctypes.c_bool,1), + ('lower_cs_local_id_to_index', ctypes.c_bool,1), + ('lower_workgroup_id_to_index', ctypes.c_bool,1), + ('global_id_is_32bit', ctypes.c_bool,1), + ('shortcut_1d_workgroup_id', ctypes.c_bool,1), + ('num_workgroups', (uint32_t * 3)), +] +nir_lower_compute_system_values_options = struct_nir_lower_compute_system_values_options +# bool nir_lower_compute_system_values(nir_shader *shader, const nir_lower_compute_system_values_options *options) +try: (nir_lower_compute_system_values:=dll.nir_lower_compute_system_values).restype, nir_lower_compute_system_values.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_compute_system_values_options)] +except AttributeError: pass + +class struct_nir_lower_sysvals_to_varyings_options(Struct): pass +struct_nir_lower_sysvals_to_varyings_options._fields_ = [ + ('frag_coord', ctypes.c_bool,1), + ('front_face', ctypes.c_bool,1), + ('point_coord', ctypes.c_bool,1), +] +nir_lower_sysvals_to_varyings_options = struct_nir_lower_sysvals_to_varyings_options +# bool nir_lower_sysvals_to_varyings(nir_shader *shader, const nir_lower_sysvals_to_varyings_options *options) +try: (nir_lower_sysvals_to_varyings:=dll.nir_lower_sysvals_to_varyings).restype, nir_lower_sysvals_to_varyings.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_sysvals_to_varyings_options)] +except AttributeError: pass + +enum_nir_lower_tex_packing = CEnum(ctypes.c_ubyte) +nir_lower_tex_packing_none = enum_nir_lower_tex_packing.define('nir_lower_tex_packing_none', 0) +nir_lower_tex_packing_16 = enum_nir_lower_tex_packing.define('nir_lower_tex_packing_16', 1) +nir_lower_tex_packing_8 = enum_nir_lower_tex_packing.define('nir_lower_tex_packing_8', 2) + +class struct_nir_lower_tex_options(Struct): pass +struct_nir_lower_tex_options._fields_ = [ + ('lower_txp', ctypes.c_uint32), + ('lower_txp_array', ctypes.c_bool), + ('lower_txf_offset', ctypes.c_bool), + ('lower_rect_offset', ctypes.c_bool), + ('lower_offset_filter', nir_instr_filter_cb), + ('lower_rect', ctypes.c_bool), + ('lower_1d', ctypes.c_bool), + ('lower_1d_shadow', ctypes.c_bool), + ('lower_y_uv_external', ctypes.c_uint32), + ('lower_y_vu_external', ctypes.c_uint32), + ('lower_y_u_v_external', ctypes.c_uint32), + ('lower_yx_xuxv_external', ctypes.c_uint32), + ('lower_yx_xvxu_external', ctypes.c_uint32), + ('lower_xy_uxvx_external', ctypes.c_uint32), + ('lower_xy_vxux_external', ctypes.c_uint32), + ('lower_ayuv_external', ctypes.c_uint32), + ('lower_xyuv_external', ctypes.c_uint32), + ('lower_yuv_external', ctypes.c_uint32), + ('lower_yu_yv_external', ctypes.c_uint32), + ('lower_yv_yu_external', ctypes.c_uint32), + ('lower_y41x_external', ctypes.c_uint32), + ('lower_sx10_external', ctypes.c_uint32), + ('lower_sx12_external', ctypes.c_uint32), + ('bt709_external', ctypes.c_uint32), + ('bt2020_external', ctypes.c_uint32), + ('yuv_full_range_external', ctypes.c_uint32), + ('saturate_s', ctypes.c_uint32), + ('saturate_t', ctypes.c_uint32), + ('saturate_r', ctypes.c_uint32), + ('swizzle_result', ctypes.c_uint32), + ('swizzles', ((uint8_t * 4) * 32)), + ('scale_factors', (ctypes.c_float * 32)), + ('lower_srgb', ctypes.c_uint32), + ('lower_txd_cube_map', ctypes.c_bool), + ('lower_txd_3d', ctypes.c_bool), + ('lower_txd_array', ctypes.c_bool), + ('lower_txd_shadow', ctypes.c_bool), + ('lower_txd', ctypes.c_bool), + ('lower_txd_clamp', ctypes.c_bool), + ('lower_txb_shadow_clamp', ctypes.c_bool), + ('lower_txd_shadow_clamp', ctypes.c_bool), + ('lower_txd_offset_clamp', ctypes.c_bool), + ('lower_txd_clamp_bindless_sampler', ctypes.c_bool), + ('lower_txd_clamp_if_sampler_index_not_lt_16', ctypes.c_bool), + ('lower_txs_lod', ctypes.c_bool), + ('lower_txs_cube_array', ctypes.c_bool), + ('lower_tg4_broadcom_swizzle', ctypes.c_bool), + ('lower_tg4_offsets', ctypes.c_bool), + ('lower_to_fragment_fetch_amd', ctypes.c_bool), + ('lower_tex_packing_cb', ctypes.CFUNCTYPE(enum_nir_lower_tex_packing, ctypes.POINTER(nir_tex_instr), ctypes.c_void_p)), + ('lower_tex_packing_data', ctypes.c_void_p), + ('lower_lod_zero_width', ctypes.c_bool), + ('lower_sampler_lod_bias', ctypes.c_bool), + ('lower_invalid_implicit_lod', ctypes.c_bool), + ('lower_index_to_offset', ctypes.c_bool), + ('callback_data', ctypes.c_void_p), +] +nir_lower_tex_options = struct_nir_lower_tex_options +# bool nir_lower_tex(nir_shader *shader, const nir_lower_tex_options *options) +try: (nir_lower_tex:=dll.nir_lower_tex).restype, nir_lower_tex.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_tex_options)] +except AttributeError: pass + +class struct_nir_lower_tex_shadow_swizzle(Struct): pass +struct_nir_lower_tex_shadow_swizzle._fields_ = [ + ('swizzle_r', ctypes.c_uint32,3), + ('swizzle_g', ctypes.c_uint32,3), + ('swizzle_b', ctypes.c_uint32,3), + ('swizzle_a', ctypes.c_uint32,3), +] +nir_lower_tex_shadow_swizzle = struct_nir_lower_tex_shadow_swizzle +# bool nir_lower_tex_shadow(nir_shader *s, unsigned int n_states, enum compare_func *compare_func, nir_lower_tex_shadow_swizzle *tex_swizzles, bool is_fixed_point_format) +try: (nir_lower_tex_shadow:=dll.nir_lower_tex_shadow).restype, nir_lower_tex_shadow.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.POINTER(enum_compare_func), ctypes.POINTER(nir_lower_tex_shadow_swizzle), ctypes.c_bool] +except AttributeError: pass + +class struct_nir_lower_image_options(Struct): pass +struct_nir_lower_image_options._fields_ = [ + ('lower_cube_size', ctypes.c_bool), + ('lower_to_fragment_mask_load_amd', ctypes.c_bool), + ('lower_image_samples_to_one', ctypes.c_bool), +] +nir_lower_image_options = struct_nir_lower_image_options +# bool nir_lower_image(nir_shader *nir, const nir_lower_image_options *options) +try: (nir_lower_image:=dll.nir_lower_image).restype, nir_lower_image.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_image_options)] +except AttributeError: pass + +# bool nir_lower_image_atomics_to_global(nir_shader *s, nir_intrin_filter_cb filter, const void *data) +try: (nir_lower_image_atomics_to_global:=dll.nir_lower_image_atomics_to_global).restype, nir_lower_image_atomics_to_global.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_intrin_filter_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_readonly_images_to_tex(nir_shader *shader, bool per_variable) +try: (nir_lower_readonly_images_to_tex:=dll.nir_lower_readonly_images_to_tex).restype, nir_lower_readonly_images_to_tex.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +enum_nir_lower_non_uniform_access_type = CEnum(ctypes.c_uint32) +nir_lower_non_uniform_ubo_access = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_ubo_access', 1) +nir_lower_non_uniform_ssbo_access = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_ssbo_access', 2) +nir_lower_non_uniform_texture_access = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_texture_access', 4) +nir_lower_non_uniform_image_access = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_image_access', 8) +nir_lower_non_uniform_get_ssbo_size = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_get_ssbo_size', 16) +nir_lower_non_uniform_texture_offset_access = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_texture_offset_access', 32) +nir_lower_non_uniform_access_type_count = enum_nir_lower_non_uniform_access_type.define('nir_lower_non_uniform_access_type_count', 6) + +class const_struct_nir_tex_instr(Struct): pass +const_struct_nir_tex_instr._fields_ = [ + ('instr', nir_instr), + ('sampler_dim', enum_glsl_sampler_dim), + ('dest_type', nir_alu_type), + ('op', nir_texop), + ('def', nir_def), + ('src', ctypes.POINTER(nir_tex_src)), + ('num_srcs', ctypes.c_uint32), + ('coord_components', ctypes.c_uint32), + ('is_array', ctypes.c_bool), + ('is_shadow', ctypes.c_bool), + ('is_new_style_shadow', ctypes.c_bool), + ('is_sparse', ctypes.c_bool), + ('component', ctypes.c_uint32,2), + ('array_is_lowered_cube', ctypes.c_uint32,1), + ('is_gather_implicit_lod', ctypes.c_uint32,1), + ('skip_helpers', ctypes.c_uint32,1), + ('tg4_offsets', ((int8_t * 2) * 4)), + ('texture_non_uniform', ctypes.c_bool), + ('sampler_non_uniform', ctypes.c_bool), + ('offset_non_uniform', ctypes.c_bool), + ('texture_index', ctypes.c_uint32), + ('sampler_index', ctypes.c_uint32), + ('backend_flags', uint32_t), +] +nir_lower_non_uniform_src_access_callback = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(const_struct_nir_tex_instr), ctypes.c_uint32, ctypes.c_void_p) +class const_struct_nir_src(Struct): pass +const_struct_nir_src._fields_ = [ + ('_parent', uintptr_t), + ('use_link', struct_list_head), + ('ssa', ctypes.POINTER(nir_def)), +] +nir_lower_non_uniform_access_callback = ctypes.CFUNCTYPE(ctypes.c_uint16, ctypes.POINTER(const_struct_nir_src), ctypes.c_void_p) +class struct_nir_lower_non_uniform_access_options(Struct): pass +struct_nir_lower_non_uniform_access_options._fields_ = [ + ('types', enum_nir_lower_non_uniform_access_type), + ('tex_src_callback', nir_lower_non_uniform_src_access_callback), + ('callback', nir_lower_non_uniform_access_callback), + ('callback_data', ctypes.c_void_p), +] +nir_lower_non_uniform_access_options = struct_nir_lower_non_uniform_access_options +# bool nir_has_non_uniform_access(nir_shader *shader, enum nir_lower_non_uniform_access_type types) +try: (nir_has_non_uniform_access:=dll.nir_has_non_uniform_access).restype, nir_has_non_uniform_access.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), enum_nir_lower_non_uniform_access_type] +except AttributeError: pass + +# bool nir_opt_non_uniform_access(nir_shader *shader) +try: (nir_opt_non_uniform_access:=dll.nir_opt_non_uniform_access).restype, nir_opt_non_uniform_access.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_non_uniform_access(nir_shader *shader, const nir_lower_non_uniform_access_options *options) +try: (nir_lower_non_uniform_access:=dll.nir_lower_non_uniform_access).restype, nir_lower_non_uniform_access.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_non_uniform_access_options)] +except AttributeError: pass + +class struct_nir_lower_idiv_options(Struct): pass +struct_nir_lower_idiv_options._fields_ = [ + ('allow_fp16', ctypes.c_bool), +] +nir_lower_idiv_options = struct_nir_lower_idiv_options +# bool nir_lower_idiv(nir_shader *shader, const nir_lower_idiv_options *options) +try: (nir_lower_idiv:=dll.nir_lower_idiv).restype, nir_lower_idiv.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_idiv_options)] +except AttributeError: pass + +class struct_nir_input_attachment_options(Struct): pass +struct_nir_input_attachment_options._fields_ = [ + ('use_ia_coord_intrin', ctypes.c_bool), + ('use_fragcoord_sysval', ctypes.c_bool), + ('use_layer_id_sysval', ctypes.c_bool), + ('use_view_id_for_layer', ctypes.c_bool), + ('unscaled_depth_stencil_ir3', ctypes.c_bool), + ('unscaled_input_attachment_ir3', uint32_t), +] +nir_input_attachment_options = struct_nir_input_attachment_options +# bool nir_lower_input_attachments(nir_shader *shader, const nir_input_attachment_options *options) +try: (nir_lower_input_attachments:=dll.nir_lower_input_attachments).restype, nir_lower_input_attachments.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_input_attachment_options)] +except AttributeError: pass + +# bool nir_lower_clip_vs(nir_shader *shader, unsigned int ucp_enables, bool use_vars, bool use_clipdist_array, const gl_state_index16 clipplane_state_tokens[][4]) +try: (nir_lower_clip_vs:=dll.nir_lower_clip_vs).restype, nir_lower_clip_vs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool, ((gl_state_index16 * 4) * 0)] +except AttributeError: pass + +# bool nir_lower_clip_gs(nir_shader *shader, unsigned int ucp_enables, bool use_clipdist_array, const gl_state_index16 clipplane_state_tokens[][4]) +try: (nir_lower_clip_gs:=dll.nir_lower_clip_gs).restype, nir_lower_clip_gs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_bool, ((gl_state_index16 * 4) * 0)] +except AttributeError: pass + +# bool nir_lower_clip_fs(nir_shader *shader, unsigned int ucp_enables, bool use_clipdist_array, bool use_load_interp) +try: (nir_lower_clip_fs:=dll.nir_lower_clip_fs).restype, nir_lower_clip_fs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_clip_cull_distance_to_vec4s(nir_shader *shader) +try: (nir_lower_clip_cull_distance_to_vec4s:=dll.nir_lower_clip_cull_distance_to_vec4s).restype, nir_lower_clip_cull_distance_to_vec4s.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_clip_cull_distance_array_vars(nir_shader *nir) +try: (nir_lower_clip_cull_distance_array_vars:=dll.nir_lower_clip_cull_distance_array_vars).restype, nir_lower_clip_cull_distance_array_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_clip_disable(nir_shader *shader, unsigned int clip_plane_enable) +try: (nir_lower_clip_disable:=dll.nir_lower_clip_disable).restype, nir_lower_clip_disable.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_lower_point_size_mov(nir_shader *shader, const gl_state_index16 *pointsize_state_tokens) +try: (nir_lower_point_size_mov:=dll.nir_lower_point_size_mov).restype, nir_lower_point_size_mov.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(gl_state_index16)] +except AttributeError: pass + +# bool nir_lower_frexp(nir_shader *nir) +try: (nir_lower_frexp:=dll.nir_lower_frexp).restype, nir_lower_frexp.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_two_sided_color(nir_shader *shader, bool face_sysval) +try: (nir_lower_two_sided_color:=dll.nir_lower_two_sided_color).restype, nir_lower_two_sided_color.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_clamp_color_outputs(nir_shader *shader) +try: (nir_lower_clamp_color_outputs:=dll.nir_lower_clamp_color_outputs).restype, nir_lower_clamp_color_outputs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_flatshade(nir_shader *shader) +try: (nir_lower_flatshade:=dll.nir_lower_flatshade).restype, nir_lower_flatshade.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_passthrough_edgeflags(nir_shader *shader) +try: (nir_lower_passthrough_edgeflags:=dll.nir_lower_passthrough_edgeflags).restype, nir_lower_passthrough_edgeflags.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_patch_vertices(nir_shader *nir, unsigned int static_count, const gl_state_index16 *uniform_state_tokens) +try: (nir_lower_patch_vertices:=dll.nir_lower_patch_vertices).restype, nir_lower_patch_vertices.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.POINTER(gl_state_index16)] +except AttributeError: pass + +class struct_nir_lower_wpos_ytransform_options(Struct): pass +struct_nir_lower_wpos_ytransform_options._fields_ = [ + ('state_tokens', (gl_state_index16 * 4)), + ('fs_coord_origin_upper_left', ctypes.c_bool,1), + ('fs_coord_origin_lower_left', ctypes.c_bool,1), + ('fs_coord_pixel_center_integer', ctypes.c_bool,1), + ('fs_coord_pixel_center_half_integer', ctypes.c_bool,1), +] +nir_lower_wpos_ytransform_options = struct_nir_lower_wpos_ytransform_options +# bool nir_lower_wpos_ytransform(nir_shader *shader, const nir_lower_wpos_ytransform_options *options) +try: (nir_lower_wpos_ytransform:=dll.nir_lower_wpos_ytransform).restype, nir_lower_wpos_ytransform.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_wpos_ytransform_options)] +except AttributeError: pass + +# bool nir_lower_wpos_center(nir_shader *shader) +try: (nir_lower_wpos_center:=dll.nir_lower_wpos_center).restype, nir_lower_wpos_center.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_pntc_ytransform(nir_shader *shader, const gl_state_index16 clipplane_state_tokens[][4]) +try: (nir_lower_pntc_ytransform:=dll.nir_lower_pntc_ytransform).restype, nir_lower_pntc_ytransform.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ((gl_state_index16 * 4) * 0)] +except AttributeError: pass + +# bool nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data) +try: (nir_lower_wrmasks:=dll.nir_lower_wrmasks).restype, nir_lower_wrmasks.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_instr_filter_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_fb_read(nir_shader *shader) +try: (nir_lower_fb_read:=dll.nir_lower_fb_read).restype, nir_lower_fb_read.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_lower_drawpixels_options(Struct): pass +struct_nir_lower_drawpixels_options._fields_ = [ + ('texcoord_state_tokens', (gl_state_index16 * 4)), + ('scale_state_tokens', (gl_state_index16 * 4)), + ('bias_state_tokens', (gl_state_index16 * 4)), + ('drawpix_sampler', ctypes.c_uint32), + ('pixelmap_sampler', ctypes.c_uint32), + ('pixel_maps', ctypes.c_bool,1), + ('scale_and_bias', ctypes.c_bool,1), +] +nir_lower_drawpixels_options = struct_nir_lower_drawpixels_options +# bool nir_lower_drawpixels(nir_shader *shader, const nir_lower_drawpixels_options *options) +try: (nir_lower_drawpixels:=dll.nir_lower_drawpixels).restype, nir_lower_drawpixels.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_drawpixels_options)] +except AttributeError: pass + +class struct_nir_lower_bitmap_options(Struct): pass +struct_nir_lower_bitmap_options._fields_ = [ + ('sampler', ctypes.c_uint32), + ('swizzle_xxxx', ctypes.c_bool), +] +nir_lower_bitmap_options = struct_nir_lower_bitmap_options +# bool nir_lower_bitmap(nir_shader *shader, const nir_lower_bitmap_options *options) +try: (nir_lower_bitmap:=dll.nir_lower_bitmap).restype, nir_lower_bitmap.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_bitmap_options)] +except AttributeError: pass + +# bool nir_lower_atomics_to_ssbo(nir_shader *shader, unsigned int offset_align_state) +try: (nir_lower_atomics_to_ssbo:=dll.nir_lower_atomics_to_ssbo).restype, nir_lower_atomics_to_ssbo.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +nir_lower_gs_intrinsics_flags = CEnum(ctypes.c_uint32) +nir_lower_gs_intrinsics_per_stream = nir_lower_gs_intrinsics_flags.define('nir_lower_gs_intrinsics_per_stream', 1) +nir_lower_gs_intrinsics_count_primitives = nir_lower_gs_intrinsics_flags.define('nir_lower_gs_intrinsics_count_primitives', 2) +nir_lower_gs_intrinsics_count_vertices_per_primitive = nir_lower_gs_intrinsics_flags.define('nir_lower_gs_intrinsics_count_vertices_per_primitive', 4) +nir_lower_gs_intrinsics_overwrite_incomplete = nir_lower_gs_intrinsics_flags.define('nir_lower_gs_intrinsics_overwrite_incomplete', 8) + +# bool nir_lower_gs_intrinsics(nir_shader *shader, nir_lower_gs_intrinsics_flags options) +try: (nir_lower_gs_intrinsics:=dll.nir_lower_gs_intrinsics).restype, nir_lower_gs_intrinsics.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_gs_intrinsics_flags] +except AttributeError: pass + +# bool nir_lower_halt_to_return(nir_shader *nir) +try: (nir_lower_halt_to_return:=dll.nir_lower_halt_to_return).restype, nir_lower_halt_to_return.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_tess_coord_z(nir_shader *shader, bool triangles) +try: (nir_lower_tess_coord_z:=dll.nir_lower_tess_coord_z).restype, nir_lower_tess_coord_z.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +class struct_nir_lower_task_shader_options(Struct): pass +struct_nir_lower_task_shader_options._fields_ = [ + ('payload_to_shared_for_atomics', ctypes.c_bool,1), + ('payload_to_shared_for_small_types', ctypes.c_bool,1), + ('payload_offset_in_bytes', uint32_t), +] +nir_lower_task_shader_options = struct_nir_lower_task_shader_options +# bool nir_lower_task_shader(nir_shader *shader, nir_lower_task_shader_options options) +try: (nir_lower_task_shader:=dll.nir_lower_task_shader).restype, nir_lower_task_shader.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_task_shader_options] +except AttributeError: pass + +nir_lower_bit_size_callback = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(const_struct_nir_instr), ctypes.c_void_p) +# bool nir_lower_bit_size(nir_shader *shader, nir_lower_bit_size_callback callback, void *callback_data) +try: (nir_lower_bit_size:=dll.nir_lower_bit_size).restype, nir_lower_bit_size.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_bit_size_callback, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_lower_64bit_phis(nir_shader *shader) +try: (nir_lower_64bit_phis:=dll.nir_lower_64bit_phis).restype, nir_lower_64bit_phis.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_split_conversions_options(Struct): pass +struct_nir_split_conversions_options._fields_ = [ + ('callback', nir_lower_bit_size_callback), + ('callback_data', ctypes.c_void_p), + ('has_convert_alu_types', ctypes.c_bool), +] +nir_split_conversions_options = struct_nir_split_conversions_options +# bool nir_split_conversions(nir_shader *shader, const nir_split_conversions_options *options) +try: (nir_split_conversions:=dll.nir_split_conversions).restype, nir_split_conversions.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_split_conversions_options)] +except AttributeError: pass + +# bool nir_split_64bit_vec3_and_vec4(nir_shader *shader) +try: (nir_split_64bit_vec3_and_vec4:=dll.nir_split_64bit_vec3_and_vec4).restype, nir_split_64bit_vec3_and_vec4.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_lower_int64_options nir_lower_int64_op_to_options_mask(nir_op opcode) +try: (nir_lower_int64_op_to_options_mask:=dll.nir_lower_int64_op_to_options_mask).restype, nir_lower_int64_op_to_options_mask.argtypes = nir_lower_int64_options, [nir_op] +except AttributeError: pass + +# bool nir_lower_int64(nir_shader *shader) +try: (nir_lower_int64:=dll.nir_lower_int64).restype, nir_lower_int64.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_int64_float_conversions(nir_shader *shader) +try: (nir_lower_int64_float_conversions:=dll.nir_lower_int64_float_conversions).restype, nir_lower_int64_float_conversions.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_lower_doubles_options nir_lower_doubles_op_to_options_mask(nir_op opcode) +try: (nir_lower_doubles_op_to_options_mask:=dll.nir_lower_doubles_op_to_options_mask).restype, nir_lower_doubles_op_to_options_mask.argtypes = nir_lower_doubles_options, [nir_op] +except AttributeError: pass + +# bool nir_lower_doubles(nir_shader *shader, const nir_shader *softfp64, nir_lower_doubles_options options) +try: (nir_lower_doubles:=dll.nir_lower_doubles).restype, nir_lower_doubles.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_shader), nir_lower_doubles_options] +except AttributeError: pass + +# bool nir_lower_pack(nir_shader *shader) +try: (nir_lower_pack:=dll.nir_lower_pack).restype, nir_lower_pack.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# nir_intrinsic_instr *nir_get_io_intrinsic(nir_instr *instr, nir_variable_mode modes, nir_variable_mode *out_mode) +try: (nir_get_io_intrinsic:=dll.nir_get_io_intrinsic).restype, nir_get_io_intrinsic.argtypes = ctypes.POINTER(nir_intrinsic_instr), [ctypes.POINTER(nir_instr), nir_variable_mode, ctypes.POINTER(nir_variable_mode)] +except AttributeError: pass + +# bool nir_recompute_io_bases(nir_shader *nir, nir_variable_mode modes) +try: (nir_recompute_io_bases:=dll.nir_recompute_io_bases).restype, nir_recompute_io_bases.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_lower_mediump_vars(nir_shader *nir, nir_variable_mode modes) +try: (nir_lower_mediump_vars:=dll.nir_lower_mediump_vars).restype, nir_lower_mediump_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_lower_mediump_io(nir_shader *nir, nir_variable_mode modes, uint64_t varying_mask, bool use_16bit_slots) +try: (nir_lower_mediump_io:=dll.nir_lower_mediump_io).restype, nir_lower_mediump_io.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, uint64_t, ctypes.c_bool] +except AttributeError: pass + +# bool nir_clear_mediump_io_flag(nir_shader *nir) +try: (nir_clear_mediump_io_flag:=dll.nir_clear_mediump_io_flag).restype, nir_clear_mediump_io_flag.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_opt_tex_srcs_options(Struct): pass +struct_nir_opt_tex_srcs_options._fields_ = [ + ('sampler_dims', ctypes.c_uint32), + ('src_types', ctypes.c_uint32), +] +nir_opt_tex_srcs_options = struct_nir_opt_tex_srcs_options +class struct_nir_opt_16bit_tex_image_options(Struct): pass +struct_nir_opt_16bit_tex_image_options._fields_ = [ + ('rounding_mode', nir_rounding_mode), + ('opt_tex_dest_types', nir_alu_type), + ('opt_image_dest_types', nir_alu_type), + ('integer_dest_saturates', ctypes.c_bool), + ('opt_image_store_data', ctypes.c_bool), + ('opt_image_srcs', ctypes.c_bool), + ('opt_srcs_options_count', ctypes.c_uint32), + ('opt_srcs_options', ctypes.POINTER(nir_opt_tex_srcs_options)), +] +nir_opt_16bit_tex_image_options = struct_nir_opt_16bit_tex_image_options +# bool nir_opt_16bit_tex_image(nir_shader *nir, nir_opt_16bit_tex_image_options *options) +try: (nir_opt_16bit_tex_image:=dll.nir_opt_16bit_tex_image).restype, nir_opt_16bit_tex_image.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_opt_16bit_tex_image_options)] +except AttributeError: pass + +class struct_nir_tex_src_type_constraint(Struct): pass +struct_nir_tex_src_type_constraint._fields_ = [ + ('legalize_type', ctypes.c_bool), + ('bit_size', uint8_t), + ('match_src', nir_tex_src_type), +] +nir_tex_src_type_constraint = struct_nir_tex_src_type_constraint +nir_tex_src_type_constraints = (struct_nir_tex_src_type_constraint * 23) +# bool nir_legalize_16bit_sampler_srcs(nir_shader *nir, nir_tex_src_type_constraints constraints) +try: (nir_legalize_16bit_sampler_srcs:=dll.nir_legalize_16bit_sampler_srcs).restype, nir_legalize_16bit_sampler_srcs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_tex_src_type_constraints] +except AttributeError: pass + +# bool nir_lower_point_size(nir_shader *shader, float min, float max) +try: (nir_lower_point_size:=dll.nir_lower_point_size).restype, nir_lower_point_size.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_float, ctypes.c_float] +except AttributeError: pass + +# bool nir_lower_default_point_size(nir_shader *nir) +try: (nir_lower_default_point_size:=dll.nir_lower_default_point_size).restype, nir_lower_default_point_size.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_texcoord_replace(nir_shader *s, unsigned int coord_replace, bool point_coord_is_sysval, bool yinvert) +try: (nir_lower_texcoord_replace:=dll.nir_lower_texcoord_replace).restype, nir_lower_texcoord_replace.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_texcoord_replace_late(nir_shader *s, unsigned int coord_replace, bool point_coord_is_sysval) +try: (nir_lower_texcoord_replace_late:=dll.nir_lower_texcoord_replace_late).restype, nir_lower_texcoord_replace_late.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32, ctypes.c_bool] +except AttributeError: pass + +nir_lower_interpolation_options = CEnum(ctypes.c_uint32) +nir_lower_interpolation_at_sample = nir_lower_interpolation_options.define('nir_lower_interpolation_at_sample', 2) +nir_lower_interpolation_at_offset = nir_lower_interpolation_options.define('nir_lower_interpolation_at_offset', 4) +nir_lower_interpolation_centroid = nir_lower_interpolation_options.define('nir_lower_interpolation_centroid', 8) +nir_lower_interpolation_pixel = nir_lower_interpolation_options.define('nir_lower_interpolation_pixel', 16) +nir_lower_interpolation_sample = nir_lower_interpolation_options.define('nir_lower_interpolation_sample', 32) + +# bool nir_lower_interpolation(nir_shader *shader, nir_lower_interpolation_options options) +try: (nir_lower_interpolation:=dll.nir_lower_interpolation).restype, nir_lower_interpolation.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_interpolation_options] +except AttributeError: pass + +nir_lower_discard_if_options = CEnum(ctypes.c_uint32) +nir_lower_demote_if_to_cf = nir_lower_discard_if_options.define('nir_lower_demote_if_to_cf', 1) +nir_lower_terminate_if_to_cf = nir_lower_discard_if_options.define('nir_lower_terminate_if_to_cf', 2) +nir_move_terminate_out_of_loops = nir_lower_discard_if_options.define('nir_move_terminate_out_of_loops', 4) + +# bool nir_lower_discard_if(nir_shader *shader, nir_lower_discard_if_options options) +try: (nir_lower_discard_if:=dll.nir_lower_discard_if).restype, nir_lower_discard_if.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_discard_if_options] +except AttributeError: pass + +# bool nir_lower_terminate_to_demote(nir_shader *nir) +try: (nir_lower_terminate_to_demote:=dll.nir_lower_terminate_to_demote).restype, nir_lower_terminate_to_demote.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_memory_model(nir_shader *shader) +try: (nir_lower_memory_model:=dll.nir_lower_memory_model).restype, nir_lower_memory_model.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_goto_ifs(nir_shader *shader) +try: (nir_lower_goto_ifs:=dll.nir_lower_goto_ifs).restype, nir_lower_goto_ifs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_continue_constructs(nir_shader *shader) +try: (nir_lower_continue_constructs:=dll.nir_lower_continue_constructs).restype, nir_lower_continue_constructs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_lower_multiview_options(Struct): pass +struct_nir_lower_multiview_options._fields_ = [ + ('view_mask', uint32_t), + ('allowed_per_view_outputs', uint64_t), +] +nir_lower_multiview_options = struct_nir_lower_multiview_options +# bool nir_shader_uses_view_index(nir_shader *shader) +try: (nir_shader_uses_view_index:=dll.nir_shader_uses_view_index).restype, nir_shader_uses_view_index.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_can_lower_multiview(nir_shader *shader, nir_lower_multiview_options options) +try: (nir_can_lower_multiview:=dll.nir_can_lower_multiview).restype, nir_can_lower_multiview.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_multiview_options] +except AttributeError: pass + +# bool nir_lower_multiview(nir_shader *shader, nir_lower_multiview_options options) +try: (nir_lower_multiview:=dll.nir_lower_multiview).restype, nir_lower_multiview.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_multiview_options] +except AttributeError: pass + +# bool nir_lower_view_index_to_device_index(nir_shader *shader) +try: (nir_lower_view_index_to_device_index:=dll.nir_lower_view_index_to_device_index).restype, nir_lower_view_index_to_device_index.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_lower_fp16_cast_options = CEnum(ctypes.c_uint32) +nir_lower_fp16_rtz = nir_lower_fp16_cast_options.define('nir_lower_fp16_rtz', 1) +nir_lower_fp16_rtne = nir_lower_fp16_cast_options.define('nir_lower_fp16_rtne', 2) +nir_lower_fp16_ru = nir_lower_fp16_cast_options.define('nir_lower_fp16_ru', 4) +nir_lower_fp16_rd = nir_lower_fp16_cast_options.define('nir_lower_fp16_rd', 8) +nir_lower_fp16_all = nir_lower_fp16_cast_options.define('nir_lower_fp16_all', 15) +nir_lower_fp16_split_fp64 = nir_lower_fp16_cast_options.define('nir_lower_fp16_split_fp64', 16) + +# bool nir_lower_fp16_casts(nir_shader *shader, nir_lower_fp16_cast_options options) +try: (nir_lower_fp16_casts:=dll.nir_lower_fp16_casts).restype, nir_lower_fp16_casts.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_lower_fp16_cast_options] +except AttributeError: pass + +# bool nir_normalize_cubemap_coords(nir_shader *shader) +try: (nir_normalize_cubemap_coords:=dll.nir_normalize_cubemap_coords).restype, nir_normalize_cubemap_coords.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_shader_supports_implicit_lod(nir_shader *shader) +try: (nir_shader_supports_implicit_lod:=dll.nir_shader_supports_implicit_lod).restype, nir_shader_supports_implicit_lod.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_live_defs_impl(nir_function_impl *impl) +try: (nir_live_defs_impl:=dll.nir_live_defs_impl).restype, nir_live_defs_impl.argtypes = None, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# const unsigned int *nir_get_live_defs(nir_cursor cursor, void *mem_ctx) +try: (nir_get_live_defs:=dll.nir_get_live_defs).restype, nir_get_live_defs.argtypes = ctypes.POINTER(ctypes.c_uint32), [nir_cursor, ctypes.c_void_p] +except AttributeError: pass + +# void nir_loop_analyze_impl(nir_function_impl *impl, nir_variable_mode indirect_mask, bool force_unroll_sampler_indirect) +try: (nir_loop_analyze_impl:=dll.nir_loop_analyze_impl).restype, nir_loop_analyze_impl.argtypes = None, [ctypes.POINTER(nir_function_impl), nir_variable_mode, ctypes.c_bool] +except AttributeError: pass + +# bool nir_defs_interfere(nir_def *a, nir_def *b) +try: (nir_defs_interfere:=dll.nir_defs_interfere).restype, nir_defs_interfere.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# bool nir_repair_ssa_impl(nir_function_impl *impl) +try: (nir_repair_ssa_impl:=dll.nir_repair_ssa_impl).restype, nir_repair_ssa_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_repair_ssa(nir_shader *shader) +try: (nir_repair_ssa:=dll.nir_repair_ssa).restype, nir_repair_ssa.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_convert_loop_to_lcssa(nir_loop *loop) +try: (nir_convert_loop_to_lcssa:=dll.nir_convert_loop_to_lcssa).restype, nir_convert_loop_to_lcssa.argtypes = None, [ctypes.POINTER(nir_loop)] +except AttributeError: pass + +# bool nir_convert_to_lcssa(nir_shader *shader, bool skip_invariants, bool skip_bool_invariants) +try: (nir_convert_to_lcssa:=dll.nir_convert_to_lcssa).restype, nir_convert_to_lcssa.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# void nir_divergence_analysis_impl(nir_function_impl *impl, nir_divergence_options options) +try: (nir_divergence_analysis_impl:=dll.nir_divergence_analysis_impl).restype, nir_divergence_analysis_impl.argtypes = None, [ctypes.POINTER(nir_function_impl), nir_divergence_options] +except AttributeError: pass + +# void nir_divergence_analysis(nir_shader *shader) +try: (nir_divergence_analysis:=dll.nir_divergence_analysis).restype, nir_divergence_analysis.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_vertex_divergence_analysis(nir_shader *shader) +try: (nir_vertex_divergence_analysis:=dll.nir_vertex_divergence_analysis).restype, nir_vertex_divergence_analysis.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_has_divergent_loop(nir_shader *shader) +try: (nir_has_divergent_loop:=dll.nir_has_divergent_loop).restype, nir_has_divergent_loop.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# void nir_rewrite_uses_to_load_reg(nir_builder *b, nir_def *old, nir_def *reg) +try: (nir_rewrite_uses_to_load_reg:=dll.nir_rewrite_uses_to_load_reg).restype, nir_rewrite_uses_to_load_reg.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# bool nir_convert_from_ssa(nir_shader *shader, bool phi_webs_only, bool consider_divergence) +try: (nir_convert_from_ssa:=dll.nir_convert_from_ssa).restype, nir_convert_from_ssa.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_phis_to_regs_block(nir_block *block, bool place_writes_in_imm_preds) +try: (nir_lower_phis_to_regs_block:=dll.nir_lower_phis_to_regs_block).restype, nir_lower_phis_to_regs_block.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block), ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_ssa_defs_to_regs_block(nir_block *block) +try: (nir_lower_ssa_defs_to_regs_block:=dll.nir_lower_ssa_defs_to_regs_block).restype, nir_lower_ssa_defs_to_regs_block.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# bool nir_rematerialize_deref_in_use_blocks(nir_deref_instr *instr) +try: (nir_rematerialize_deref_in_use_blocks:=dll.nir_rematerialize_deref_in_use_blocks).restype, nir_rematerialize_deref_in_use_blocks.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_deref_instr)] +except AttributeError: pass + +# bool nir_rematerialize_derefs_in_use_blocks_impl(nir_function_impl *impl) +try: (nir_rematerialize_derefs_in_use_blocks_impl:=dll.nir_rematerialize_derefs_in_use_blocks_impl).restype, nir_rematerialize_derefs_in_use_blocks_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_lower_samplers(nir_shader *shader) +try: (nir_lower_samplers:=dll.nir_lower_samplers).restype, nir_lower_samplers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_cl_images(nir_shader *shader, bool lower_image_derefs, bool lower_sampler_derefs) +try: (nir_lower_cl_images:=dll.nir_lower_cl_images).restype, nir_lower_cl_images.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# bool nir_dedup_inline_samplers(nir_shader *shader) +try: (nir_dedup_inline_samplers:=dll.nir_dedup_inline_samplers).restype, nir_dedup_inline_samplers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_lower_ssbo_options(Struct): pass +struct_nir_lower_ssbo_options._fields_ = [ + ('native_loads', ctypes.c_bool), + ('native_offset', ctypes.c_bool), +] +nir_lower_ssbo_options = struct_nir_lower_ssbo_options +# bool nir_lower_ssbo(nir_shader *shader, const nir_lower_ssbo_options *opts) +try: (nir_lower_ssbo:=dll.nir_lower_ssbo).restype, nir_lower_ssbo.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_ssbo_options)] +except AttributeError: pass + +# bool nir_lower_helper_writes(nir_shader *shader, bool lower_plain_stores) +try: (nir_lower_helper_writes:=dll.nir_lower_helper_writes).restype, nir_lower_helper_writes.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +class struct_nir_lower_printf_options(Struct): pass +struct_nir_lower_printf_options._fields_ = [ + ('max_buffer_size', ctypes.c_uint32), + ('ptr_bit_size', ctypes.c_uint32), + ('hash_format_strings', ctypes.c_bool), +] +nir_lower_printf_options = struct_nir_lower_printf_options +# bool nir_lower_printf(nir_shader *nir, const nir_lower_printf_options *options) +try: (nir_lower_printf:=dll.nir_lower_printf).restype, nir_lower_printf.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_printf_options)] +except AttributeError: pass + +# bool nir_lower_printf_buffer(nir_shader *nir, uint64_t address, uint32_t size) +try: (nir_lower_printf_buffer:=dll.nir_lower_printf_buffer).restype, nir_lower_printf_buffer.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), uint64_t, uint32_t] +except AttributeError: pass + +# bool nir_opt_comparison_pre_impl(nir_function_impl *impl) +try: (nir_opt_comparison_pre_impl:=dll.nir_opt_comparison_pre_impl).restype, nir_opt_comparison_pre_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_opt_comparison_pre(nir_shader *shader) +try: (nir_opt_comparison_pre:=dll.nir_opt_comparison_pre).restype, nir_opt_comparison_pre.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_opt_access_options(Struct): pass +struct_nir_opt_access_options._fields_ = [ + ('is_vulkan', ctypes.c_bool), +] +nir_opt_access_options = struct_nir_opt_access_options +# bool nir_opt_access(nir_shader *shader, const nir_opt_access_options *options) +try: (nir_opt_access:=dll.nir_opt_access).restype, nir_opt_access.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_opt_access_options)] +except AttributeError: pass + +# bool nir_opt_algebraic(nir_shader *shader) +try: (nir_opt_algebraic:=dll.nir_opt_algebraic).restype, nir_opt_algebraic.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_algebraic_before_ffma(nir_shader *shader) +try: (nir_opt_algebraic_before_ffma:=dll.nir_opt_algebraic_before_ffma).restype, nir_opt_algebraic_before_ffma.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_algebraic_before_lower_int64(nir_shader *shader) +try: (nir_opt_algebraic_before_lower_int64:=dll.nir_opt_algebraic_before_lower_int64).restype, nir_opt_algebraic_before_lower_int64.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_algebraic_late(nir_shader *shader) +try: (nir_opt_algebraic_late:=dll.nir_opt_algebraic_late).restype, nir_opt_algebraic_late.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_algebraic_distribute_src_mods(nir_shader *shader) +try: (nir_opt_algebraic_distribute_src_mods:=dll.nir_opt_algebraic_distribute_src_mods).restype, nir_opt_algebraic_distribute_src_mods.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_algebraic_integer_promotion(nir_shader *shader) +try: (nir_opt_algebraic_integer_promotion:=dll.nir_opt_algebraic_integer_promotion).restype, nir_opt_algebraic_integer_promotion.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_reassociate_matrix_mul(nir_shader *shader) +try: (nir_opt_reassociate_matrix_mul:=dll.nir_opt_reassociate_matrix_mul).restype, nir_opt_reassociate_matrix_mul.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_constant_folding(nir_shader *shader) +try: (nir_opt_constant_folding:=dll.nir_opt_constant_folding).restype, nir_opt_constant_folding.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_combine_barrier_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_void_p) +# bool nir_opt_combine_barriers(nir_shader *shader, nir_combine_barrier_cb combine_cb, void *data) +try: (nir_opt_combine_barriers:=dll.nir_opt_combine_barriers).restype, nir_opt_combine_barriers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_combine_barrier_cb, ctypes.c_void_p] +except AttributeError: pass + +mesa_scope = CEnum(ctypes.c_uint32) +SCOPE_NONE = mesa_scope.define('SCOPE_NONE', 0) +SCOPE_INVOCATION = mesa_scope.define('SCOPE_INVOCATION', 1) +SCOPE_SUBGROUP = mesa_scope.define('SCOPE_SUBGROUP', 2) +SCOPE_SHADER_CALL = mesa_scope.define('SCOPE_SHADER_CALL', 3) +SCOPE_WORKGROUP = mesa_scope.define('SCOPE_WORKGROUP', 4) +SCOPE_QUEUE_FAMILY = mesa_scope.define('SCOPE_QUEUE_FAMILY', 5) +SCOPE_DEVICE = mesa_scope.define('SCOPE_DEVICE', 6) + +# bool nir_opt_acquire_release_barriers(nir_shader *shader, mesa_scope max_scope) +try: (nir_opt_acquire_release_barriers:=dll.nir_opt_acquire_release_barriers).restype, nir_opt_acquire_release_barriers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), mesa_scope] +except AttributeError: pass + +# bool nir_opt_barrier_modes(nir_shader *shader) +try: (nir_opt_barrier_modes:=dll.nir_opt_barrier_modes).restype, nir_opt_barrier_modes.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_minimize_call_live_states(nir_shader *shader) +try: (nir_minimize_call_live_states:=dll.nir_minimize_call_live_states).restype, nir_minimize_call_live_states.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_combine_stores(nir_shader *shader, nir_variable_mode modes) +try: (nir_opt_combine_stores:=dll.nir_opt_combine_stores).restype, nir_opt_combine_stores.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode] +except AttributeError: pass + +# bool nir_copy_prop_impl(nir_function_impl *impl) +try: (nir_copy_prop_impl:=dll.nir_copy_prop_impl).restype, nir_copy_prop_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_copy_prop(nir_shader *shader) +try: (nir_copy_prop:=dll.nir_copy_prop).restype, nir_copy_prop.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_copy_prop_vars(nir_shader *shader) +try: (nir_opt_copy_prop_vars:=dll.nir_opt_copy_prop_vars).restype, nir_opt_copy_prop_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_cse(nir_shader *shader) +try: (nir_opt_cse:=dll.nir_opt_cse).restype, nir_opt_cse.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_dce(nir_shader *shader) +try: (nir_opt_dce:=dll.nir_opt_dce).restype, nir_opt_dce.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_dead_cf(nir_shader *shader) +try: (nir_opt_dead_cf:=dll.nir_opt_dead_cf).restype, nir_opt_dead_cf.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_dead_write_vars(nir_shader *shader) +try: (nir_opt_dead_write_vars:=dll.nir_opt_dead_write_vars).restype, nir_opt_dead_write_vars.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_deref_impl(nir_function_impl *impl) +try: (nir_opt_deref_impl:=dll.nir_opt_deref_impl).restype, nir_opt_deref_impl.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_function_impl)] +except AttributeError: pass + +# bool nir_opt_deref(nir_shader *shader) +try: (nir_opt_deref:=dll.nir_opt_deref).restype, nir_opt_deref.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_find_array_copies(nir_shader *shader) +try: (nir_opt_find_array_copies:=dll.nir_opt_find_array_copies).restype, nir_opt_find_array_copies.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_def_is_frag_coord_z(nir_def *def) +try: (nir_def_is_frag_coord_z:=dll.nir_def_is_frag_coord_z).restype, nir_def_is_frag_coord_z.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_def)] +except AttributeError: pass + +# bool nir_opt_fragdepth(nir_shader *shader) +try: (nir_opt_fragdepth:=dll.nir_opt_fragdepth).restype, nir_opt_fragdepth.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_gcm(nir_shader *shader, bool value_number) +try: (nir_opt_gcm:=dll.nir_opt_gcm).restype, nir_opt_gcm.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_opt_generate_bfi(nir_shader *shader) +try: (nir_opt_generate_bfi:=dll.nir_opt_generate_bfi).restype, nir_opt_generate_bfi.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_idiv_const(nir_shader *shader, unsigned int min_bit_size) +try: (nir_opt_idiv_const:=dll.nir_opt_idiv_const).restype, nir_opt_idiv_const.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_opt_mqsad(nir_shader *shader) +try: (nir_opt_mqsad:=dll.nir_opt_mqsad).restype, nir_opt_mqsad.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_opt_if_options = CEnum(ctypes.c_uint32) +nir_opt_if_optimize_phi_true_false = nir_opt_if_options.define('nir_opt_if_optimize_phi_true_false', 1) +nir_opt_if_avoid_64bit_phis = nir_opt_if_options.define('nir_opt_if_avoid_64bit_phis', 2) + +# bool nir_opt_if(nir_shader *shader, nir_opt_if_options options) +try: (nir_opt_if:=dll.nir_opt_if).restype, nir_opt_if.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_opt_if_options] +except AttributeError: pass + +# bool nir_opt_intrinsics(nir_shader *shader) +try: (nir_opt_intrinsics:=dll.nir_opt_intrinsics).restype, nir_opt_intrinsics.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_large_constants(nir_shader *shader, glsl_type_size_align_func size_align, unsigned int threshold) +try: (nir_opt_large_constants:=dll.nir_opt_large_constants).restype, nir_opt_large_constants.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), glsl_type_size_align_func, ctypes.c_uint32] +except AttributeError: pass + +# bool nir_opt_licm(nir_shader *shader) +try: (nir_opt_licm:=dll.nir_opt_licm).restype, nir_opt_licm.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_loop(nir_shader *shader) +try: (nir_opt_loop:=dll.nir_opt_loop).restype, nir_opt_loop.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_loop_unroll(nir_shader *shader) +try: (nir_opt_loop_unroll:=dll.nir_opt_loop_unroll).restype, nir_opt_loop_unroll.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +nir_move_options = CEnum(ctypes.c_uint32) +nir_move_const_undef = nir_move_options.define('nir_move_const_undef', 1) +nir_move_load_ubo = nir_move_options.define('nir_move_load_ubo', 2) +nir_move_load_input = nir_move_options.define('nir_move_load_input', 4) +nir_move_comparisons = nir_move_options.define('nir_move_comparisons', 8) +nir_move_copies = nir_move_options.define('nir_move_copies', 16) +nir_move_load_ssbo = nir_move_options.define('nir_move_load_ssbo', 32) +nir_move_load_uniform = nir_move_options.define('nir_move_load_uniform', 64) +nir_move_alu = nir_move_options.define('nir_move_alu', 128) +nir_dont_move_byte_word_vecs = nir_move_options.define('nir_dont_move_byte_word_vecs', 256) + +# bool nir_can_move_instr(nir_instr *instr, nir_move_options options) +try: (nir_can_move_instr:=dll.nir_can_move_instr).restype, nir_can_move_instr.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_instr), nir_move_options] +except AttributeError: pass + +# bool nir_opt_sink(nir_shader *shader, nir_move_options options) +try: (nir_opt_sink:=dll.nir_opt_sink).restype, nir_opt_sink.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_move_options] +except AttributeError: pass + +# bool nir_opt_move(nir_shader *shader, nir_move_options options) +try: (nir_opt_move:=dll.nir_opt_move).restype, nir_opt_move.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_move_options] +except AttributeError: pass + +class struct_nir_opt_offsets_options(Struct): pass +struct_nir_opt_offsets_options._fields_ = [ + ('uniform_max', uint32_t), + ('ubo_vec4_max', uint32_t), + ('shared_max', uint32_t), + ('shared_atomic_max', uint32_t), + ('buffer_max', uint32_t), + ('max_offset_cb', ctypes.CFUNCTYPE(uint32_t, ctypes.POINTER(nir_intrinsic_instr), ctypes.c_void_p)), + ('max_offset_data', ctypes.c_void_p), + ('allow_offset_wrap', ctypes.c_bool), +] +nir_opt_offsets_options = struct_nir_opt_offsets_options +# bool nir_opt_offsets(nir_shader *shader, const nir_opt_offsets_options *options) +try: (nir_opt_offsets:=dll.nir_opt_offsets).restype, nir_opt_offsets.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_opt_offsets_options)] +except AttributeError: pass + +class struct_nir_opt_peephole_select_options(Struct): pass +struct_nir_opt_peephole_select_options._fields_ = [ + ('limit', ctypes.c_uint32), + ('indirect_load_ok', ctypes.c_bool), + ('expensive_alu_ok', ctypes.c_bool), + ('discard_ok', ctypes.c_bool), +] +nir_opt_peephole_select_options = struct_nir_opt_peephole_select_options +# bool nir_opt_peephole_select(nir_shader *shader, const nir_opt_peephole_select_options *options) +try: (nir_opt_peephole_select:=dll.nir_opt_peephole_select).restype, nir_opt_peephole_select.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_opt_peephole_select_options)] +except AttributeError: pass + +# bool nir_opt_reassociate_bfi(nir_shader *shader) +try: (nir_opt_reassociate_bfi:=dll.nir_opt_reassociate_bfi).restype, nir_opt_reassociate_bfi.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_rematerialize_compares(nir_shader *shader) +try: (nir_opt_rematerialize_compares:=dll.nir_opt_rematerialize_compares).restype, nir_opt_rematerialize_compares.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_remove_phis(nir_shader *shader) +try: (nir_opt_remove_phis:=dll.nir_opt_remove_phis).restype, nir_opt_remove_phis.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_remove_single_src_phis_block(nir_block *block) +try: (nir_remove_single_src_phis_block:=dll.nir_remove_single_src_phis_block).restype, nir_remove_single_src_phis_block.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_block)] +except AttributeError: pass + +# bool nir_opt_phi_precision(nir_shader *shader) +try: (nir_opt_phi_precision:=dll.nir_opt_phi_precision).restype, nir_opt_phi_precision.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_phi_to_bool(nir_shader *shader) +try: (nir_opt_phi_to_bool:=dll.nir_opt_phi_to_bool).restype, nir_opt_phi_to_bool.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_shrink_stores(nir_shader *shader, bool shrink_image_store) +try: (nir_opt_shrink_stores:=dll.nir_opt_shrink_stores).restype, nir_opt_shrink_stores.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_opt_shrink_vectors(nir_shader *shader, bool shrink_start) +try: (nir_opt_shrink_vectors:=dll.nir_opt_shrink_vectors).restype, nir_opt_shrink_vectors.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_opt_undef(nir_shader *shader) +try: (nir_opt_undef:=dll.nir_opt_undef).restype, nir_opt_undef.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_undef_to_zero(nir_shader *shader) +try: (nir_lower_undef_to_zero:=dll.nir_lower_undef_to_zero).restype, nir_lower_undef_to_zero.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_uniform_atomics(nir_shader *shader, bool fs_atomics_predicated) +try: (nir_opt_uniform_atomics:=dll.nir_opt_uniform_atomics).restype, nir_opt_uniform_atomics.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_opt_uniform_subgroup(nir_shader *shader, const nir_lower_subgroups_options *) +try: (nir_opt_uniform_subgroup:=dll.nir_opt_uniform_subgroup).restype, nir_opt_uniform_subgroup.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_lower_subgroups_options)] +except AttributeError: pass + +# bool nir_opt_vectorize(nir_shader *shader, nir_vectorize_cb filter, void *data) +try: (nir_opt_vectorize:=dll.nir_opt_vectorize).restype, nir_opt_vectorize.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_vectorize_cb, ctypes.c_void_p] +except AttributeError: pass + +# bool nir_opt_vectorize_io(nir_shader *shader, nir_variable_mode modes, bool allow_holes) +try: (nir_opt_vectorize_io:=dll.nir_opt_vectorize_io).restype, nir_opt_vectorize_io.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), nir_variable_mode, ctypes.c_bool] +except AttributeError: pass + +# bool nir_opt_move_discards_to_top(nir_shader *shader) +try: (nir_opt_move_discards_to_top:=dll.nir_opt_move_discards_to_top).restype, nir_opt_move_discards_to_top.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_ray_queries(nir_shader *shader) +try: (nir_opt_ray_queries:=dll.nir_opt_ray_queries).restype, nir_opt_ray_queries.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_ray_query_ranges(nir_shader *shader) +try: (nir_opt_ray_query_ranges:=dll.nir_opt_ray_query_ranges).restype, nir_opt_ray_query_ranges.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_opt_tex_skip_helpers(nir_shader *shader, bool no_add_divergence) +try: (nir_opt_tex_skip_helpers:=dll.nir_opt_tex_skip_helpers).restype, nir_opt_tex_skip_helpers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# void nir_sweep(nir_shader *shader) +try: (nir_sweep:=dll.nir_sweep).restype, nir_sweep.argtypes = None, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +gl_system_value = CEnum(ctypes.c_uint32) +SYSTEM_VALUE_SUBGROUP_SIZE = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_SIZE', 0) +SYSTEM_VALUE_SUBGROUP_INVOCATION = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_INVOCATION', 1) +SYSTEM_VALUE_SUBGROUP_EQ_MASK = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_EQ_MASK', 2) +SYSTEM_VALUE_SUBGROUP_GE_MASK = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_GE_MASK', 3) +SYSTEM_VALUE_SUBGROUP_GT_MASK = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_GT_MASK', 4) +SYSTEM_VALUE_SUBGROUP_LE_MASK = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_LE_MASK', 5) +SYSTEM_VALUE_SUBGROUP_LT_MASK = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_LT_MASK', 6) +SYSTEM_VALUE_NUM_SUBGROUPS = gl_system_value.define('SYSTEM_VALUE_NUM_SUBGROUPS', 7) +SYSTEM_VALUE_SUBGROUP_ID = gl_system_value.define('SYSTEM_VALUE_SUBGROUP_ID', 8) +SYSTEM_VALUE_VERTEX_ID = gl_system_value.define('SYSTEM_VALUE_VERTEX_ID', 9) +SYSTEM_VALUE_INSTANCE_ID = gl_system_value.define('SYSTEM_VALUE_INSTANCE_ID', 10) +SYSTEM_VALUE_INSTANCE_INDEX = gl_system_value.define('SYSTEM_VALUE_INSTANCE_INDEX', 11) +SYSTEM_VALUE_VERTEX_ID_ZERO_BASE = gl_system_value.define('SYSTEM_VALUE_VERTEX_ID_ZERO_BASE', 12) +SYSTEM_VALUE_BASE_VERTEX = gl_system_value.define('SYSTEM_VALUE_BASE_VERTEX', 13) +SYSTEM_VALUE_FIRST_VERTEX = gl_system_value.define('SYSTEM_VALUE_FIRST_VERTEX', 14) +SYSTEM_VALUE_IS_INDEXED_DRAW = gl_system_value.define('SYSTEM_VALUE_IS_INDEXED_DRAW', 15) +SYSTEM_VALUE_BASE_INSTANCE = gl_system_value.define('SYSTEM_VALUE_BASE_INSTANCE', 16) +SYSTEM_VALUE_DRAW_ID = gl_system_value.define('SYSTEM_VALUE_DRAW_ID', 17) +SYSTEM_VALUE_INVOCATION_ID = gl_system_value.define('SYSTEM_VALUE_INVOCATION_ID', 18) +SYSTEM_VALUE_FRAG_COORD = gl_system_value.define('SYSTEM_VALUE_FRAG_COORD', 19) +SYSTEM_VALUE_PIXEL_COORD = gl_system_value.define('SYSTEM_VALUE_PIXEL_COORD', 20) +SYSTEM_VALUE_FRAG_COORD_Z = gl_system_value.define('SYSTEM_VALUE_FRAG_COORD_Z', 21) +SYSTEM_VALUE_FRAG_COORD_W = gl_system_value.define('SYSTEM_VALUE_FRAG_COORD_W', 22) +SYSTEM_VALUE_POINT_COORD = gl_system_value.define('SYSTEM_VALUE_POINT_COORD', 23) +SYSTEM_VALUE_LINE_COORD = gl_system_value.define('SYSTEM_VALUE_LINE_COORD', 24) +SYSTEM_VALUE_FRONT_FACE = gl_system_value.define('SYSTEM_VALUE_FRONT_FACE', 25) +SYSTEM_VALUE_FRONT_FACE_FSIGN = gl_system_value.define('SYSTEM_VALUE_FRONT_FACE_FSIGN', 26) +SYSTEM_VALUE_SAMPLE_ID = gl_system_value.define('SYSTEM_VALUE_SAMPLE_ID', 27) +SYSTEM_VALUE_SAMPLE_POS = gl_system_value.define('SYSTEM_VALUE_SAMPLE_POS', 28) +SYSTEM_VALUE_SAMPLE_POS_OR_CENTER = gl_system_value.define('SYSTEM_VALUE_SAMPLE_POS_OR_CENTER', 29) +SYSTEM_VALUE_SAMPLE_MASK_IN = gl_system_value.define('SYSTEM_VALUE_SAMPLE_MASK_IN', 30) +SYSTEM_VALUE_LAYER_ID = gl_system_value.define('SYSTEM_VALUE_LAYER_ID', 31) +SYSTEM_VALUE_HELPER_INVOCATION = gl_system_value.define('SYSTEM_VALUE_HELPER_INVOCATION', 32) +SYSTEM_VALUE_COLOR0 = gl_system_value.define('SYSTEM_VALUE_COLOR0', 33) +SYSTEM_VALUE_COLOR1 = gl_system_value.define('SYSTEM_VALUE_COLOR1', 34) +SYSTEM_VALUE_TESS_COORD = gl_system_value.define('SYSTEM_VALUE_TESS_COORD', 35) +SYSTEM_VALUE_VERTICES_IN = gl_system_value.define('SYSTEM_VALUE_VERTICES_IN', 36) +SYSTEM_VALUE_PRIMITIVE_ID = gl_system_value.define('SYSTEM_VALUE_PRIMITIVE_ID', 37) +SYSTEM_VALUE_TESS_LEVEL_OUTER = gl_system_value.define('SYSTEM_VALUE_TESS_LEVEL_OUTER', 38) +SYSTEM_VALUE_TESS_LEVEL_INNER = gl_system_value.define('SYSTEM_VALUE_TESS_LEVEL_INNER', 39) +SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT = gl_system_value.define('SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT', 40) +SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT = gl_system_value.define('SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT', 41) +SYSTEM_VALUE_LOCAL_INVOCATION_ID = gl_system_value.define('SYSTEM_VALUE_LOCAL_INVOCATION_ID', 42) +SYSTEM_VALUE_LOCAL_INVOCATION_INDEX = gl_system_value.define('SYSTEM_VALUE_LOCAL_INVOCATION_INDEX', 43) +SYSTEM_VALUE_GLOBAL_INVOCATION_ID = gl_system_value.define('SYSTEM_VALUE_GLOBAL_INVOCATION_ID', 44) +SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID = gl_system_value.define('SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID', 45) +SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX = gl_system_value.define('SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX', 46) +SYSTEM_VALUE_WORKGROUP_ID = gl_system_value.define('SYSTEM_VALUE_WORKGROUP_ID', 47) +SYSTEM_VALUE_BASE_WORKGROUP_ID = gl_system_value.define('SYSTEM_VALUE_BASE_WORKGROUP_ID', 48) +SYSTEM_VALUE_WORKGROUP_INDEX = gl_system_value.define('SYSTEM_VALUE_WORKGROUP_INDEX', 49) +SYSTEM_VALUE_NUM_WORKGROUPS = gl_system_value.define('SYSTEM_VALUE_NUM_WORKGROUPS', 50) +SYSTEM_VALUE_WORKGROUP_SIZE = gl_system_value.define('SYSTEM_VALUE_WORKGROUP_SIZE', 51) +SYSTEM_VALUE_GLOBAL_GROUP_SIZE = gl_system_value.define('SYSTEM_VALUE_GLOBAL_GROUP_SIZE', 52) +SYSTEM_VALUE_WORK_DIM = gl_system_value.define('SYSTEM_VALUE_WORK_DIM', 53) +SYSTEM_VALUE_USER_DATA_AMD = gl_system_value.define('SYSTEM_VALUE_USER_DATA_AMD', 54) +SYSTEM_VALUE_DEVICE_INDEX = gl_system_value.define('SYSTEM_VALUE_DEVICE_INDEX', 55) +SYSTEM_VALUE_VIEW_INDEX = gl_system_value.define('SYSTEM_VALUE_VIEW_INDEX', 56) +SYSTEM_VALUE_VERTEX_CNT = gl_system_value.define('SYSTEM_VALUE_VERTEX_CNT', 57) +SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL', 58) +SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE', 59) +SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID', 60) +SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTER_RHW = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTER_RHW', 61) +SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL', 62) +SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID', 63) +SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE', 64) +SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL', 65) +SYSTEM_VALUE_BARYCENTRIC_PERSP_COORD = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_PERSP_COORD', 66) +SYSTEM_VALUE_BARYCENTRIC_LINEAR_COORD = gl_system_value.define('SYSTEM_VALUE_BARYCENTRIC_LINEAR_COORD', 67) +SYSTEM_VALUE_RAY_LAUNCH_ID = gl_system_value.define('SYSTEM_VALUE_RAY_LAUNCH_ID', 68) +SYSTEM_VALUE_RAY_LAUNCH_SIZE = gl_system_value.define('SYSTEM_VALUE_RAY_LAUNCH_SIZE', 69) +SYSTEM_VALUE_RAY_WORLD_ORIGIN = gl_system_value.define('SYSTEM_VALUE_RAY_WORLD_ORIGIN', 70) +SYSTEM_VALUE_RAY_WORLD_DIRECTION = gl_system_value.define('SYSTEM_VALUE_RAY_WORLD_DIRECTION', 71) +SYSTEM_VALUE_RAY_OBJECT_ORIGIN = gl_system_value.define('SYSTEM_VALUE_RAY_OBJECT_ORIGIN', 72) +SYSTEM_VALUE_RAY_OBJECT_DIRECTION = gl_system_value.define('SYSTEM_VALUE_RAY_OBJECT_DIRECTION', 73) +SYSTEM_VALUE_RAY_T_MIN = gl_system_value.define('SYSTEM_VALUE_RAY_T_MIN', 74) +SYSTEM_VALUE_RAY_T_MAX = gl_system_value.define('SYSTEM_VALUE_RAY_T_MAX', 75) +SYSTEM_VALUE_RAY_OBJECT_TO_WORLD = gl_system_value.define('SYSTEM_VALUE_RAY_OBJECT_TO_WORLD', 76) +SYSTEM_VALUE_RAY_WORLD_TO_OBJECT = gl_system_value.define('SYSTEM_VALUE_RAY_WORLD_TO_OBJECT', 77) +SYSTEM_VALUE_RAY_HIT_KIND = gl_system_value.define('SYSTEM_VALUE_RAY_HIT_KIND', 78) +SYSTEM_VALUE_RAY_FLAGS = gl_system_value.define('SYSTEM_VALUE_RAY_FLAGS', 79) +SYSTEM_VALUE_RAY_GEOMETRY_INDEX = gl_system_value.define('SYSTEM_VALUE_RAY_GEOMETRY_INDEX', 80) +SYSTEM_VALUE_RAY_INSTANCE_CUSTOM_INDEX = gl_system_value.define('SYSTEM_VALUE_RAY_INSTANCE_CUSTOM_INDEX', 81) +SYSTEM_VALUE_CULL_MASK = gl_system_value.define('SYSTEM_VALUE_CULL_MASK', 82) +SYSTEM_VALUE_RAY_TRIANGLE_VERTEX_POSITIONS = gl_system_value.define('SYSTEM_VALUE_RAY_TRIANGLE_VERTEX_POSITIONS', 83) +SYSTEM_VALUE_MESH_VIEW_COUNT = gl_system_value.define('SYSTEM_VALUE_MESH_VIEW_COUNT', 84) +SYSTEM_VALUE_MESH_VIEW_INDICES = gl_system_value.define('SYSTEM_VALUE_MESH_VIEW_INDICES', 85) +SYSTEM_VALUE_GS_HEADER_IR3 = gl_system_value.define('SYSTEM_VALUE_GS_HEADER_IR3', 86) +SYSTEM_VALUE_TCS_HEADER_IR3 = gl_system_value.define('SYSTEM_VALUE_TCS_HEADER_IR3', 87) +SYSTEM_VALUE_REL_PATCH_ID_IR3 = gl_system_value.define('SYSTEM_VALUE_REL_PATCH_ID_IR3', 88) +SYSTEM_VALUE_FRAG_SHADING_RATE = gl_system_value.define('SYSTEM_VALUE_FRAG_SHADING_RATE', 89) +SYSTEM_VALUE_FULLY_COVERED = gl_system_value.define('SYSTEM_VALUE_FULLY_COVERED', 90) +SYSTEM_VALUE_FRAG_SIZE = gl_system_value.define('SYSTEM_VALUE_FRAG_SIZE', 91) +SYSTEM_VALUE_FRAG_INVOCATION_COUNT = gl_system_value.define('SYSTEM_VALUE_FRAG_INVOCATION_COUNT', 92) +SYSTEM_VALUE_SHADER_INDEX = gl_system_value.define('SYSTEM_VALUE_SHADER_INDEX', 93) +SYSTEM_VALUE_COALESCED_INPUT_COUNT = gl_system_value.define('SYSTEM_VALUE_COALESCED_INPUT_COUNT', 94) +SYSTEM_VALUE_WARPS_PER_SM_NV = gl_system_value.define('SYSTEM_VALUE_WARPS_PER_SM_NV', 95) +SYSTEM_VALUE_SM_COUNT_NV = gl_system_value.define('SYSTEM_VALUE_SM_COUNT_NV', 96) +SYSTEM_VALUE_WARP_ID_NV = gl_system_value.define('SYSTEM_VALUE_WARP_ID_NV', 97) +SYSTEM_VALUE_SM_ID_NV = gl_system_value.define('SYSTEM_VALUE_SM_ID_NV', 98) +SYSTEM_VALUE_MAX = gl_system_value.define('SYSTEM_VALUE_MAX', 99) + +# nir_intrinsic_op nir_intrinsic_from_system_value(gl_system_value val) +try: (nir_intrinsic_from_system_value:=dll.nir_intrinsic_from_system_value).restype, nir_intrinsic_from_system_value.argtypes = nir_intrinsic_op, [gl_system_value] +except AttributeError: pass + +# gl_system_value nir_system_value_from_intrinsic(nir_intrinsic_op intrin) +try: (nir_system_value_from_intrinsic:=dll.nir_system_value_from_intrinsic).restype, nir_system_value_from_intrinsic.argtypes = gl_system_value, [nir_intrinsic_op] +except AttributeError: pass + +class struct_nir_unsigned_upper_bound_config(Struct): pass +struct_nir_unsigned_upper_bound_config._fields_ = [ + ('min_subgroup_size', ctypes.c_uint32), + ('max_subgroup_size', ctypes.c_uint32), + ('max_workgroup_invocations', ctypes.c_uint32), + ('max_workgroup_count', (ctypes.c_uint32 * 3)), + ('max_workgroup_size', (ctypes.c_uint32 * 3)), + ('vertex_attrib_max', (uint32_t * 32)), +] +nir_unsigned_upper_bound_config = struct_nir_unsigned_upper_bound_config +# uint32_t nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht, nir_scalar scalar, const nir_unsigned_upper_bound_config *config) +try: (nir_unsigned_upper_bound:=dll.nir_unsigned_upper_bound).restype, nir_unsigned_upper_bound.argtypes = uint32_t, [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_hash_table), nir_scalar, ctypes.POINTER(nir_unsigned_upper_bound_config)] +except AttributeError: pass + +# bool nir_addition_might_overflow(nir_shader *shader, struct hash_table *range_ht, nir_scalar ssa, unsigned int const_val, const nir_unsigned_upper_bound_config *config) +try: (nir_addition_might_overflow:=dll.nir_addition_might_overflow).restype, nir_addition_might_overflow.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_hash_table), nir_scalar, ctypes.c_uint32, ctypes.POINTER(nir_unsigned_upper_bound_config)] +except AttributeError: pass + +class struct_nir_opt_preamble_options(Struct): pass +struct_nir_opt_preamble_options._fields_ = [ + ('drawid_uniform', ctypes.c_bool), + ('subgroup_size_uniform', ctypes.c_bool), + ('load_workgroup_size_allowed', ctypes.c_bool), + ('def_size', ctypes.CFUNCTYPE(None, ctypes.POINTER(nir_def), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(nir_preamble_class))), + ('preamble_storage_size', (ctypes.c_uint32 * 2)), + ('instr_cost_cb', ctypes.CFUNCTYPE(ctypes.c_float, ctypes.POINTER(nir_instr), ctypes.c_void_p)), + ('rewrite_cost_cb', ctypes.CFUNCTYPE(ctypes.c_float, ctypes.POINTER(nir_def), ctypes.c_void_p)), + ('avoid_instr_cb', nir_instr_filter_cb), + ('cb_data', ctypes.c_void_p), +] +nir_opt_preamble_options = struct_nir_opt_preamble_options +# bool nir_opt_preamble(nir_shader *shader, const nir_opt_preamble_options *options, unsigned int *size) +try: (nir_opt_preamble:=dll.nir_opt_preamble).restype, nir_opt_preamble.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_opt_preamble_options), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# nir_function_impl *nir_shader_get_preamble(nir_shader *shader) +try: (nir_shader_get_preamble:=dll.nir_shader_get_preamble).restype, nir_shader_get_preamble.argtypes = ctypes.POINTER(nir_function_impl), [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# bool nir_lower_point_smooth(nir_shader *shader, bool set_barycentrics) +try: (nir_lower_point_smooth:=dll.nir_lower_point_smooth).restype, nir_lower_point_smooth.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass + +# bool nir_lower_poly_line_smooth(nir_shader *shader, unsigned int num_smooth_aa_sample) +try: (nir_lower_poly_line_smooth:=dll.nir_lower_poly_line_smooth).restype, nir_lower_poly_line_smooth.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_mod_analysis(nir_scalar val, nir_alu_type val_type, unsigned int div, unsigned int *mod) +try: (nir_mod_analysis:=dll.nir_mod_analysis).restype, nir_mod_analysis.argtypes = ctypes.c_bool, [nir_scalar, nir_alu_type, ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# bool nir_remove_tex_shadow(nir_shader *shader, unsigned int textures_bitmask) +try: (nir_remove_tex_shadow:=dll.nir_remove_tex_shadow).restype, nir_remove_tex_shadow.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.c_uint32] +except AttributeError: pass + +# bool nir_trivialize_registers(nir_shader *s) +try: (nir_trivialize_registers:=dll.nir_trivialize_registers).restype, nir_trivialize_registers.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +# unsigned int nir_static_workgroup_size(const nir_shader *s) +try: (nir_static_workgroup_size:=dll.nir_static_workgroup_size).restype, nir_static_workgroup_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(nir_shader)] +except AttributeError: pass + +class struct_nir_use_dominance_state(Struct): pass +nir_use_dominance_state = struct_nir_use_dominance_state +# nir_use_dominance_state *nir_calc_use_dominance_impl(nir_function_impl *impl, bool post_dominance) +try: (nir_calc_use_dominance_impl:=dll.nir_calc_use_dominance_impl).restype, nir_calc_use_dominance_impl.argtypes = ctypes.POINTER(nir_use_dominance_state), [ctypes.POINTER(nir_function_impl), ctypes.c_bool] +except AttributeError: pass + +# nir_instr *nir_get_immediate_use_dominator(nir_use_dominance_state *state, nir_instr *instr) +try: (nir_get_immediate_use_dominator:=dll.nir_get_immediate_use_dominator).restype, nir_get_immediate_use_dominator.argtypes = ctypes.POINTER(nir_instr), [ctypes.POINTER(nir_use_dominance_state), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# nir_instr *nir_use_dominance_lca(nir_use_dominance_state *state, nir_instr *i1, nir_instr *i2) +try: (nir_use_dominance_lca:=dll.nir_use_dominance_lca).restype, nir_use_dominance_lca.argtypes = ctypes.POINTER(nir_instr), [ctypes.POINTER(nir_use_dominance_state), ctypes.POINTER(nir_instr), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# bool nir_instr_dominates_use(nir_use_dominance_state *state, nir_instr *parent, nir_instr *child) +try: (nir_instr_dominates_use:=dll.nir_instr_dominates_use).restype, nir_instr_dominates_use.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_use_dominance_state), ctypes.POINTER(nir_instr), ctypes.POINTER(nir_instr)] +except AttributeError: pass + +# void nir_print_use_dominators(nir_use_dominance_state *state, nir_instr **instructions, unsigned int num_instructions) +try: (nir_print_use_dominators:=dll.nir_print_use_dominators).restype, nir_print_use_dominators.argtypes = None, [ctypes.POINTER(nir_use_dominance_state), ctypes.POINTER(ctypes.POINTER(nir_instr)), ctypes.c_uint32] +except AttributeError: pass + +class nir_output_deps(Struct): pass +class nir_output_deps_output(Struct): pass +nir_output_deps_output._fields_ = [ + ('instr_list', ctypes.POINTER(ctypes.POINTER(nir_instr))), + ('num_instr', ctypes.c_uint32), +] +nir_output_deps._fields_ = [ + ('output', (nir_output_deps_output * 112)), +] +# void nir_gather_output_dependencies(nir_shader *nir, nir_output_deps *deps) +try: (nir_gather_output_dependencies:=dll.nir_gather_output_dependencies).restype, nir_gather_output_dependencies.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_output_deps)] +except AttributeError: pass + +# void nir_free_output_dependencies(nir_output_deps *deps) +try: (nir_free_output_dependencies:=dll.nir_free_output_dependencies).restype, nir_free_output_dependencies.argtypes = None, [ctypes.POINTER(nir_output_deps)] +except AttributeError: pass + +class nir_input_to_output_deps(Struct): pass +class nir_input_to_output_deps_output(Struct): pass +nir_input_to_output_deps_output._fields_ = [ + ('inputs', (ctypes.c_uint32 * 28)), + ('defined', ctypes.c_bool), + ('uses_ssbo_reads', ctypes.c_bool), + ('uses_image_reads', ctypes.c_bool), +] +nir_input_to_output_deps._fields_ = [ + ('output', (nir_input_to_output_deps_output * 112)), +] +# void nir_gather_input_to_output_dependencies(nir_shader *nir, nir_input_to_output_deps *out_deps) +try: (nir_gather_input_to_output_dependencies:=dll.nir_gather_input_to_output_dependencies).restype, nir_gather_input_to_output_dependencies.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_input_to_output_deps)] +except AttributeError: pass + +# void nir_print_input_to_output_deps(nir_input_to_output_deps *deps, nir_shader *nir, FILE *f) +try: (nir_print_input_to_output_deps:=dll.nir_print_input_to_output_deps).restype, nir_print_input_to_output_deps.argtypes = None, [ctypes.POINTER(nir_input_to_output_deps), ctypes.POINTER(nir_shader), ctypes.POINTER(FILE)] +except AttributeError: pass + +class nir_output_clipper_var_groups(Struct): pass +nir_output_clipper_var_groups._fields_ = [ + ('pos_only', (ctypes.c_uint32 * 28)), + ('var_only', (ctypes.c_uint32 * 28)), + ('both', (ctypes.c_uint32 * 28)), +] +# void nir_gather_output_clipper_var_groups(nir_shader *nir, nir_output_clipper_var_groups *groups) +try: (nir_gather_output_clipper_var_groups:=dll.nir_gather_output_clipper_var_groups).restype, nir_gather_output_clipper_var_groups.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(nir_output_clipper_var_groups)] +except AttributeError: pass struct_nir_builder._fields_ = [ - ('cursor', nir_cursor), - ('exact', ctypes.c_bool), - ('fp_fast_math', ctypes.c_uint32), - ('shader', ctypes.POINTER(struct_nir_shader)), - ('impl', ctypes.POINTER(struct_nir_function_impl)), + ('cursor', nir_cursor), + ('exact', ctypes.c_bool), + ('fp_fast_math', uint32_t), + ('shader', ctypes.POINTER(nir_shader)), + ('impl', ctypes.POINTER(nir_function_impl)), ] +# nir_builder nir_builder_init_simple_shader(gl_shader_stage stage, const nir_shader_compiler_options *options, const char *name, ...) +try: (nir_builder_init_simple_shader:=dll.nir_builder_init_simple_shader).restype, nir_builder_init_simple_shader.argtypes = nir_builder, [gl_shader_stage, ctypes.POINTER(nir_shader_compiler_options), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -nir_lower_instr_cb = ctypes.CFUNCTYPE(ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)) -try: - nir_function_impl_lower_instructions = _libraries['libtinymesa_cpu.so'].nir_function_impl_lower_instructions - nir_function_impl_lower_instructions.restype = ctypes.c_bool - nir_function_impl_lower_instructions.argtypes = [ctypes.POINTER(struct_nir_function_impl), nir_instr_filter_cb, nir_lower_instr_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_lower_instructions = _libraries['libtinymesa_cpu.so'].nir_shader_lower_instructions - nir_shader_lower_instructions.restype = ctypes.c_bool - nir_shader_lower_instructions.argtypes = [ctypes.POINTER(struct_nir_shader), nir_instr_filter_cb, nir_lower_instr_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_calc_dominance_impl = _libraries['libtinymesa_cpu.so'].nir_calc_dominance_impl - nir_calc_dominance_impl.restype = None - nir_calc_dominance_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_calc_dominance = _libraries['libtinymesa_cpu.so'].nir_calc_dominance - nir_calc_dominance.restype = None - nir_calc_dominance.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_dominance_lca = _libraries['libtinymesa_cpu.so'].nir_dominance_lca - nir_dominance_lca.restype = ctypes.POINTER(struct_nir_block) - nir_dominance_lca.argtypes = [ctypes.POINTER(struct_nir_block), ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_dominates = _libraries['libtinymesa_cpu.so'].nir_block_dominates - nir_block_dominates.restype = ctypes.c_bool - nir_block_dominates.argtypes = [ctypes.POINTER(struct_nir_block), ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_block_is_unreachable = _libraries['libtinymesa_cpu.so'].nir_block_is_unreachable - nir_block_is_unreachable.restype = ctypes.c_bool - nir_block_is_unreachable.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_dump_dom_tree_impl = _libraries['libtinymesa_cpu.so'].nir_dump_dom_tree_impl - nir_dump_dom_tree_impl.restype = None - nir_dump_dom_tree_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_dump_dom_tree = _libraries['libtinymesa_cpu.so'].nir_dump_dom_tree - nir_dump_dom_tree.restype = None - nir_dump_dom_tree.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_dump_dom_frontier_impl = _libraries['libtinymesa_cpu.so'].nir_dump_dom_frontier_impl - nir_dump_dom_frontier_impl.restype = None - nir_dump_dom_frontier_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_dump_dom_frontier = _libraries['libtinymesa_cpu.so'].nir_dump_dom_frontier - nir_dump_dom_frontier.restype = None - nir_dump_dom_frontier.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_dump_cfg_impl = _libraries['libtinymesa_cpu.so'].nir_dump_cfg_impl - nir_dump_cfg_impl.restype = None - nir_dump_cfg_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_dump_cfg = _libraries['libtinymesa_cpu.so'].nir_dump_cfg - nir_dump_cfg.restype = None - nir_dump_cfg.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -try: - nir_gs_count_vertices_and_primitives = _libraries['libtinymesa_cpu.so'].nir_gs_count_vertices_and_primitives - nir_gs_count_vertices_and_primitives.restype = None - nir_gs_count_vertices_and_primitives.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32), ctypes.c_uint32] -except AttributeError: - pass +nir_instr_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_instr), ctypes.c_void_p) +nir_intrinsic_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.c_void_p) +nir_alu_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_alu_instr), ctypes.c_void_p) +nir_tex_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_tex_instr), ctypes.c_void_p) +nir_phi_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_phi_instr), ctypes.c_void_p) +# void nir_builder_instr_insert(nir_builder *build, nir_instr *instr) +try: (nir_builder_instr_insert:=dll.nir_builder_instr_insert).restype, nir_builder_instr_insert.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_instr)] +except AttributeError: pass -# values for enumeration 'c__EA_nir_load_grouping' -c__EA_nir_load_grouping__enumvalues = { - 0: 'nir_group_all', - 1: 'nir_group_same_resource_only', -} -nir_group_all = 0 -nir_group_same_resource_only = 1 -c__EA_nir_load_grouping = ctypes.c_uint32 # enum -nir_load_grouping = c__EA_nir_load_grouping -nir_load_grouping__enumvalues = c__EA_nir_load_grouping__enumvalues -try: - nir_group_loads = _libraries['libtinymesa_cpu.so'].nir_group_loads - nir_group_loads.restype = ctypes.c_bool - nir_group_loads.argtypes = [ctypes.POINTER(struct_nir_shader), nir_load_grouping, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_shrink_vec_array_vars = _libraries['libtinymesa_cpu.so'].nir_shrink_vec_array_vars - nir_shrink_vec_array_vars.restype = ctypes.c_bool - nir_shrink_vec_array_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_split_array_vars = _libraries['libtinymesa_cpu.so'].nir_split_array_vars - nir_split_array_vars.restype = ctypes.c_bool - nir_split_array_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_split_var_copies = _libraries['libtinymesa_cpu.so'].nir_split_var_copies - nir_split_var_copies.restype = ctypes.c_bool - nir_split_var_copies.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_split_per_member_structs = _libraries['libtinymesa_cpu.so'].nir_split_per_member_structs - nir_split_per_member_structs.restype = ctypes.c_bool - nir_split_per_member_structs.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_split_struct_vars = _libraries['libtinymesa_cpu.so'].nir_split_struct_vars - nir_split_struct_vars.restype = ctypes.c_bool - nir_split_struct_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_returns_impl = _libraries['libtinymesa_cpu.so'].nir_lower_returns_impl - nir_lower_returns_impl.restype = ctypes.c_bool - nir_lower_returns_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_lower_returns = _libraries['libtinymesa_cpu.so'].nir_lower_returns - nir_lower_returns.restype = ctypes.c_bool - nir_lower_returns.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_inline_function_impl = _libraries['libtinymesa_cpu.so'].nir_inline_function_impl - nir_inline_function_impl.restype = ctypes.POINTER(struct_nir_def) - nir_inline_function_impl.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(ctypes.POINTER(struct_nir_def)), ctypes.POINTER(struct_hash_table)] -except AttributeError: - pass -try: - nir_inline_functions = _libraries['libtinymesa_cpu.so'].nir_inline_functions - nir_inline_functions.restype = ctypes.c_bool - nir_inline_functions.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_cleanup_functions = _libraries['libtinymesa_cpu.so'].nir_cleanup_functions - nir_cleanup_functions.restype = None - nir_cleanup_functions.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_link_shader_functions = _libraries['libtinymesa_cpu.so'].nir_link_shader_functions - nir_link_shader_functions.restype = ctypes.c_bool - nir_link_shader_functions.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_calls_to_builtins = _libraries['libtinymesa_cpu.so'].nir_lower_calls_to_builtins - nir_lower_calls_to_builtins.restype = ctypes.c_bool - nir_lower_calls_to_builtins.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_find_inlinable_uniforms = _libraries['libtinymesa_cpu.so'].nir_find_inlinable_uniforms - nir_find_inlinable_uniforms.restype = None - nir_find_inlinable_uniforms.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_inline_uniforms = _libraries['libtinymesa_cpu.so'].nir_inline_uniforms - nir_inline_uniforms.restype = ctypes.c_bool - nir_inline_uniforms.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -try: - nir_collect_src_uniforms = _libraries['libtinymesa_cpu.so'].nir_collect_src_uniforms - nir_collect_src_uniforms.restype = ctypes.c_bool - nir_collect_src_uniforms.argtypes = [ctypes.POINTER(struct_nir_src), ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_add_inlinable_uniforms = _libraries['libtinymesa_cpu.so'].nir_add_inlinable_uniforms - nir_add_inlinable_uniforms.restype = None - nir_add_inlinable_uniforms.argtypes = [ctypes.POINTER(struct_nir_src), ctypes.POINTER(struct_nir_loop_info), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_ubyte), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_propagate_invariant = _libraries['libtinymesa_cpu.so'].nir_propagate_invariant - nir_propagate_invariant.restype = ctypes.c_bool - nir_propagate_invariant.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_var_copy_instr = _libraries['FIXME_STUB'].nir_lower_var_copy_instr - nir_lower_var_copy_instr.restype = None - nir_lower_var_copy_instr.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_deref_copy_instr = _libraries['libtinymesa_cpu.so'].nir_lower_deref_copy_instr - nir_lower_deref_copy_instr.restype = None - nir_lower_deref_copy_instr.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_lower_var_copies = _libraries['libtinymesa_cpu.so'].nir_lower_var_copies - nir_lower_var_copies.restype = ctypes.c_bool - nir_lower_var_copies.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_memcpy = _libraries['libtinymesa_cpu.so'].nir_opt_memcpy - nir_opt_memcpy.restype = ctypes.c_bool - nir_opt_memcpy.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_memcpy = _libraries['libtinymesa_cpu.so'].nir_lower_memcpy - nir_lower_memcpy.restype = ctypes.c_bool - nir_lower_memcpy.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_fixup_deref_modes = _libraries['libtinymesa_cpu.so'].nir_fixup_deref_modes - nir_fixup_deref_modes.restype = ctypes.c_bool - nir_fixup_deref_modes.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_fixup_deref_types = _libraries['libtinymesa_cpu.so'].nir_fixup_deref_types - nir_fixup_deref_types.restype = ctypes.c_bool - nir_fixup_deref_types.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_global_vars_to_local = _libraries['libtinymesa_cpu.so'].nir_lower_global_vars_to_local - nir_lower_global_vars_to_local.restype = ctypes.c_bool - nir_lower_global_vars_to_local.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_constant_to_temp = _libraries['libtinymesa_cpu.so'].nir_lower_constant_to_temp - nir_lower_constant_to_temp.restype = None - nir_lower_constant_to_temp.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass +# void nir_builder_instr_insert_at_top(nir_builder *build, nir_instr *instr) +try: (nir_builder_instr_insert_at_top:=dll.nir_builder_instr_insert_at_top).restype, nir_builder_instr_insert_at_top.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_instr)] +except AttributeError: pass -# values for enumeration 'c__EA_nir_lower_array_deref_of_vec_options' -c__EA_nir_lower_array_deref_of_vec_options__enumvalues = { - 1: 'nir_lower_direct_array_deref_of_vec_load', - 2: 'nir_lower_indirect_array_deref_of_vec_load', - 4: 'nir_lower_direct_array_deref_of_vec_store', - 8: 'nir_lower_indirect_array_deref_of_vec_store', -} -nir_lower_direct_array_deref_of_vec_load = 1 -nir_lower_indirect_array_deref_of_vec_load = 2 -nir_lower_direct_array_deref_of_vec_store = 4 -nir_lower_indirect_array_deref_of_vec_store = 8 -c__EA_nir_lower_array_deref_of_vec_options = ctypes.c_uint32 # enum -nir_lower_array_deref_of_vec_options = c__EA_nir_lower_array_deref_of_vec_options -nir_lower_array_deref_of_vec_options__enumvalues = c__EA_nir_lower_array_deref_of_vec_options__enumvalues -try: - nir_lower_array_deref_of_vec = _libraries['libtinymesa_cpu.so'].nir_lower_array_deref_of_vec - nir_lower_array_deref_of_vec.restype = ctypes.c_bool - nir_lower_array_deref_of_vec.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_variable)), nir_lower_array_deref_of_vec_options] -except AttributeError: - pass -try: - nir_lower_indirect_derefs = _libraries['libtinymesa_cpu.so'].nir_lower_indirect_derefs - nir_lower_indirect_derefs.restype = ctypes.c_bool - nir_lower_indirect_derefs.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, uint32_t] -except AttributeError: - pass -try: - nir_lower_indirect_var_derefs = _libraries['libtinymesa_cpu.so'].nir_lower_indirect_var_derefs - nir_lower_indirect_var_derefs.restype = ctypes.c_bool - nir_lower_indirect_var_derefs.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_set)] -except AttributeError: - pass -try: - nir_lower_locals_to_regs = _libraries['libtinymesa_cpu.so'].nir_lower_locals_to_regs - nir_lower_locals_to_regs.restype = ctypes.c_bool - nir_lower_locals_to_regs.argtypes = [ctypes.POINTER(struct_nir_shader), uint8_t] -except AttributeError: - pass -try: - nir_lower_io_vars_to_temporaries = _libraries['libtinymesa_cpu.so'].nir_lower_io_vars_to_temporaries - nir_lower_io_vars_to_temporaries.restype = ctypes.c_bool - nir_lower_io_vars_to_temporaries.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function_impl), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_vars_to_scratch = _libraries['libtinymesa_cpu.so'].nir_lower_vars_to_scratch - nir_lower_vars_to_scratch.restype = ctypes.c_bool - nir_lower_vars_to_scratch.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.c_int32, glsl_type_size_align_func, glsl_type_size_align_func] -except AttributeError: - pass -try: - nir_lower_scratch_to_var = _libraries['libtinymesa_cpu.so'].nir_lower_scratch_to_var - nir_lower_scratch_to_var.restype = ctypes.c_bool - nir_lower_scratch_to_var.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_clip_halfz = _libraries['libtinymesa_cpu.so'].nir_lower_clip_halfz - nir_lower_clip_halfz.restype = ctypes.c_bool - nir_lower_clip_halfz.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_shader_gather_info = _libraries['libtinymesa_cpu.so'].nir_shader_gather_info - nir_shader_gather_info.restype = None - nir_shader_gather_info.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_gather_types = _libraries['libtinymesa_cpu.so'].nir_gather_types - nir_gather_types.restype = None - nir_gather_types.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - nir_remove_unused_varyings = _libraries['libtinymesa_cpu.so'].nir_remove_unused_varyings - nir_remove_unused_varyings.restype = ctypes.c_bool - nir_remove_unused_varyings.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_remove_unused_io_vars = _libraries['libtinymesa_cpu.so'].nir_remove_unused_io_vars - nir_remove_unused_io_vars.restype = ctypes.c_bool - nir_remove_unused_io_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nir_compact_varyings = _libraries['libtinymesa_cpu.so'].nir_compact_varyings - nir_compact_varyings.restype = None - nir_compact_varyings.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_link_xfb_varyings = _libraries['libtinymesa_cpu.so'].nir_link_xfb_varyings - nir_link_xfb_varyings.restype = None - nir_link_xfb_varyings.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_link_opt_varyings = _libraries['libtinymesa_cpu.so'].nir_link_opt_varyings - nir_link_opt_varyings.restype = ctypes.c_bool - nir_link_opt_varyings.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_link_varying_precision = _libraries['libtinymesa_cpu.so'].nir_link_varying_precision - nir_link_varying_precision.restype = None - nir_link_varying_precision.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_clone_uniform_variable = _libraries['libtinymesa_cpu.so'].nir_clone_uniform_variable - nir_clone_uniform_variable.restype = ctypes.POINTER(struct_nir_variable) - nir_clone_uniform_variable.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_variable), ctypes.c_bool] -except AttributeError: - pass -try: - nir_clone_deref_instr = _libraries['libtinymesa_cpu.so'].nir_clone_deref_instr - nir_clone_deref_instr.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_clone_deref_instr.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass +# nir_def *nir_build_alu(nir_builder *build, nir_op op, nir_def *src0, nir_def *src1, nir_def *src2, nir_def *src3) +try: (nir_build_alu:=dll.nir_build_alu).restype, nir_build_alu.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass -# values for enumeration 'c__EA_nir_opt_varyings_progress' -c__EA_nir_opt_varyings_progress__enumvalues = { - 1: 'nir_progress_producer', - 2: 'nir_progress_consumer', -} -nir_progress_producer = 1 -nir_progress_consumer = 2 -c__EA_nir_opt_varyings_progress = ctypes.c_uint32 # enum -nir_opt_varyings_progress = c__EA_nir_opt_varyings_progress -nir_opt_varyings_progress__enumvalues = c__EA_nir_opt_varyings_progress__enumvalues -try: - nir_opt_varyings = _libraries['libtinymesa_cpu.so'].nir_opt_varyings - nir_opt_varyings.restype = nir_opt_varyings_progress - nir_opt_varyings.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader), ctypes.c_bool, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool] -except AttributeError: - pass +# nir_def *nir_build_alu1(nir_builder *build, nir_op op, nir_def *src0) +try: (nir_build_alu1:=dll.nir_build_alu1).restype, nir_build_alu1.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(nir_def)] +except AttributeError: pass -# values for enumeration 'c__EA_gl_varying_slot' -c__EA_gl_varying_slot__enumvalues = { - 0: 'VARYING_SLOT_POS', - 1: 'VARYING_SLOT_COL0', - 2: 'VARYING_SLOT_COL1', - 3: 'VARYING_SLOT_FOGC', - 4: 'VARYING_SLOT_TEX0', - 5: 'VARYING_SLOT_TEX1', - 6: 'VARYING_SLOT_TEX2', - 7: 'VARYING_SLOT_TEX3', - 8: 'VARYING_SLOT_TEX4', - 9: 'VARYING_SLOT_TEX5', - 10: 'VARYING_SLOT_TEX6', - 11: 'VARYING_SLOT_TEX7', - 12: 'VARYING_SLOT_PSIZ', - 13: 'VARYING_SLOT_BFC0', - 14: 'VARYING_SLOT_BFC1', - 15: 'VARYING_SLOT_EDGE', - 16: 'VARYING_SLOT_CLIP_VERTEX', - 17: 'VARYING_SLOT_CLIP_DIST0', - 18: 'VARYING_SLOT_CLIP_DIST1', - 19: 'VARYING_SLOT_CULL_DIST0', - 20: 'VARYING_SLOT_CULL_DIST1', - 21: 'VARYING_SLOT_PRIMITIVE_ID', - 22: 'VARYING_SLOT_LAYER', - 23: 'VARYING_SLOT_VIEWPORT', - 24: 'VARYING_SLOT_FACE', - 25: 'VARYING_SLOT_PNTC', - 26: 'VARYING_SLOT_TESS_LEVEL_OUTER', - 27: 'VARYING_SLOT_TESS_LEVEL_INNER', - 28: 'VARYING_SLOT_BOUNDING_BOX0', - 29: 'VARYING_SLOT_BOUNDING_BOX1', - 30: 'VARYING_SLOT_VIEW_INDEX', - 31: 'VARYING_SLOT_VIEWPORT_MASK', - 24: 'VARYING_SLOT_PRIMITIVE_SHADING_RATE', - 26: 'VARYING_SLOT_PRIMITIVE_COUNT', - 27: 'VARYING_SLOT_PRIMITIVE_INDICES', - 28: 'VARYING_SLOT_TASK_COUNT', - 28: 'VARYING_SLOT_CULL_PRIMITIVE', - 32: 'VARYING_SLOT_VAR0', - 33: 'VARYING_SLOT_VAR1', - 34: 'VARYING_SLOT_VAR2', - 35: 'VARYING_SLOT_VAR3', - 36: 'VARYING_SLOT_VAR4', - 37: 'VARYING_SLOT_VAR5', - 38: 'VARYING_SLOT_VAR6', - 39: 'VARYING_SLOT_VAR7', - 40: 'VARYING_SLOT_VAR8', - 41: 'VARYING_SLOT_VAR9', - 42: 'VARYING_SLOT_VAR10', - 43: 'VARYING_SLOT_VAR11', - 44: 'VARYING_SLOT_VAR12', - 45: 'VARYING_SLOT_VAR13', - 46: 'VARYING_SLOT_VAR14', - 47: 'VARYING_SLOT_VAR15', - 48: 'VARYING_SLOT_VAR16', - 49: 'VARYING_SLOT_VAR17', - 50: 'VARYING_SLOT_VAR18', - 51: 'VARYING_SLOT_VAR19', - 52: 'VARYING_SLOT_VAR20', - 53: 'VARYING_SLOT_VAR21', - 54: 'VARYING_SLOT_VAR22', - 55: 'VARYING_SLOT_VAR23', - 56: 'VARYING_SLOT_VAR24', - 57: 'VARYING_SLOT_VAR25', - 58: 'VARYING_SLOT_VAR26', - 59: 'VARYING_SLOT_VAR27', - 60: 'VARYING_SLOT_VAR28', - 61: 'VARYING_SLOT_VAR29', - 62: 'VARYING_SLOT_VAR30', - 63: 'VARYING_SLOT_VAR31', - 64: 'VARYING_SLOT_PATCH0', - 65: 'VARYING_SLOT_PATCH1', - 66: 'VARYING_SLOT_PATCH2', - 67: 'VARYING_SLOT_PATCH3', - 68: 'VARYING_SLOT_PATCH4', - 69: 'VARYING_SLOT_PATCH5', - 70: 'VARYING_SLOT_PATCH6', - 71: 'VARYING_SLOT_PATCH7', - 72: 'VARYING_SLOT_PATCH8', - 73: 'VARYING_SLOT_PATCH9', - 74: 'VARYING_SLOT_PATCH10', - 75: 'VARYING_SLOT_PATCH11', - 76: 'VARYING_SLOT_PATCH12', - 77: 'VARYING_SLOT_PATCH13', - 78: 'VARYING_SLOT_PATCH14', - 79: 'VARYING_SLOT_PATCH15', - 80: 'VARYING_SLOT_PATCH16', - 81: 'VARYING_SLOT_PATCH17', - 82: 'VARYING_SLOT_PATCH18', - 83: 'VARYING_SLOT_PATCH19', - 84: 'VARYING_SLOT_PATCH20', - 85: 'VARYING_SLOT_PATCH21', - 86: 'VARYING_SLOT_PATCH22', - 87: 'VARYING_SLOT_PATCH23', - 88: 'VARYING_SLOT_PATCH24', - 89: 'VARYING_SLOT_PATCH25', - 90: 'VARYING_SLOT_PATCH26', - 91: 'VARYING_SLOT_PATCH27', - 92: 'VARYING_SLOT_PATCH28', - 93: 'VARYING_SLOT_PATCH29', - 94: 'VARYING_SLOT_PATCH30', - 95: 'VARYING_SLOT_PATCH31', - 96: 'VARYING_SLOT_VAR0_16BIT', - 97: 'VARYING_SLOT_VAR1_16BIT', - 98: 'VARYING_SLOT_VAR2_16BIT', - 99: 'VARYING_SLOT_VAR3_16BIT', - 100: 'VARYING_SLOT_VAR4_16BIT', - 101: 'VARYING_SLOT_VAR5_16BIT', - 102: 'VARYING_SLOT_VAR6_16BIT', - 103: 'VARYING_SLOT_VAR7_16BIT', - 104: 'VARYING_SLOT_VAR8_16BIT', - 105: 'VARYING_SLOT_VAR9_16BIT', - 106: 'VARYING_SLOT_VAR10_16BIT', - 107: 'VARYING_SLOT_VAR11_16BIT', - 108: 'VARYING_SLOT_VAR12_16BIT', - 109: 'VARYING_SLOT_VAR13_16BIT', - 110: 'VARYING_SLOT_VAR14_16BIT', - 111: 'VARYING_SLOT_VAR15_16BIT', - 112: 'NUM_TOTAL_VARYING_SLOTS', -} -VARYING_SLOT_POS = 0 -VARYING_SLOT_COL0 = 1 -VARYING_SLOT_COL1 = 2 -VARYING_SLOT_FOGC = 3 -VARYING_SLOT_TEX0 = 4 -VARYING_SLOT_TEX1 = 5 -VARYING_SLOT_TEX2 = 6 -VARYING_SLOT_TEX3 = 7 -VARYING_SLOT_TEX4 = 8 -VARYING_SLOT_TEX5 = 9 -VARYING_SLOT_TEX6 = 10 -VARYING_SLOT_TEX7 = 11 -VARYING_SLOT_PSIZ = 12 -VARYING_SLOT_BFC0 = 13 -VARYING_SLOT_BFC1 = 14 -VARYING_SLOT_EDGE = 15 -VARYING_SLOT_CLIP_VERTEX = 16 -VARYING_SLOT_CLIP_DIST0 = 17 -VARYING_SLOT_CLIP_DIST1 = 18 -VARYING_SLOT_CULL_DIST0 = 19 -VARYING_SLOT_CULL_DIST1 = 20 -VARYING_SLOT_PRIMITIVE_ID = 21 -VARYING_SLOT_LAYER = 22 -VARYING_SLOT_VIEWPORT = 23 -VARYING_SLOT_FACE = 24 -VARYING_SLOT_PNTC = 25 -VARYING_SLOT_TESS_LEVEL_OUTER = 26 -VARYING_SLOT_TESS_LEVEL_INNER = 27 -VARYING_SLOT_BOUNDING_BOX0 = 28 -VARYING_SLOT_BOUNDING_BOX1 = 29 -VARYING_SLOT_VIEW_INDEX = 30 -VARYING_SLOT_VIEWPORT_MASK = 31 -VARYING_SLOT_PRIMITIVE_SHADING_RATE = 24 -VARYING_SLOT_PRIMITIVE_COUNT = 26 -VARYING_SLOT_PRIMITIVE_INDICES = 27 -VARYING_SLOT_TASK_COUNT = 28 -VARYING_SLOT_CULL_PRIMITIVE = 28 -VARYING_SLOT_VAR0 = 32 -VARYING_SLOT_VAR1 = 33 -VARYING_SLOT_VAR2 = 34 -VARYING_SLOT_VAR3 = 35 -VARYING_SLOT_VAR4 = 36 -VARYING_SLOT_VAR5 = 37 -VARYING_SLOT_VAR6 = 38 -VARYING_SLOT_VAR7 = 39 -VARYING_SLOT_VAR8 = 40 -VARYING_SLOT_VAR9 = 41 -VARYING_SLOT_VAR10 = 42 -VARYING_SLOT_VAR11 = 43 -VARYING_SLOT_VAR12 = 44 -VARYING_SLOT_VAR13 = 45 -VARYING_SLOT_VAR14 = 46 -VARYING_SLOT_VAR15 = 47 -VARYING_SLOT_VAR16 = 48 -VARYING_SLOT_VAR17 = 49 -VARYING_SLOT_VAR18 = 50 -VARYING_SLOT_VAR19 = 51 -VARYING_SLOT_VAR20 = 52 -VARYING_SLOT_VAR21 = 53 -VARYING_SLOT_VAR22 = 54 -VARYING_SLOT_VAR23 = 55 -VARYING_SLOT_VAR24 = 56 -VARYING_SLOT_VAR25 = 57 -VARYING_SLOT_VAR26 = 58 -VARYING_SLOT_VAR27 = 59 -VARYING_SLOT_VAR28 = 60 -VARYING_SLOT_VAR29 = 61 -VARYING_SLOT_VAR30 = 62 -VARYING_SLOT_VAR31 = 63 -VARYING_SLOT_PATCH0 = 64 -VARYING_SLOT_PATCH1 = 65 -VARYING_SLOT_PATCH2 = 66 -VARYING_SLOT_PATCH3 = 67 -VARYING_SLOT_PATCH4 = 68 -VARYING_SLOT_PATCH5 = 69 -VARYING_SLOT_PATCH6 = 70 -VARYING_SLOT_PATCH7 = 71 -VARYING_SLOT_PATCH8 = 72 -VARYING_SLOT_PATCH9 = 73 -VARYING_SLOT_PATCH10 = 74 -VARYING_SLOT_PATCH11 = 75 -VARYING_SLOT_PATCH12 = 76 -VARYING_SLOT_PATCH13 = 77 -VARYING_SLOT_PATCH14 = 78 -VARYING_SLOT_PATCH15 = 79 -VARYING_SLOT_PATCH16 = 80 -VARYING_SLOT_PATCH17 = 81 -VARYING_SLOT_PATCH18 = 82 -VARYING_SLOT_PATCH19 = 83 -VARYING_SLOT_PATCH20 = 84 -VARYING_SLOT_PATCH21 = 85 -VARYING_SLOT_PATCH22 = 86 -VARYING_SLOT_PATCH23 = 87 -VARYING_SLOT_PATCH24 = 88 -VARYING_SLOT_PATCH25 = 89 -VARYING_SLOT_PATCH26 = 90 -VARYING_SLOT_PATCH27 = 91 -VARYING_SLOT_PATCH28 = 92 -VARYING_SLOT_PATCH29 = 93 -VARYING_SLOT_PATCH30 = 94 -VARYING_SLOT_PATCH31 = 95 -VARYING_SLOT_VAR0_16BIT = 96 -VARYING_SLOT_VAR1_16BIT = 97 -VARYING_SLOT_VAR2_16BIT = 98 -VARYING_SLOT_VAR3_16BIT = 99 -VARYING_SLOT_VAR4_16BIT = 100 -VARYING_SLOT_VAR5_16BIT = 101 -VARYING_SLOT_VAR6_16BIT = 102 -VARYING_SLOT_VAR7_16BIT = 103 -VARYING_SLOT_VAR8_16BIT = 104 -VARYING_SLOT_VAR9_16BIT = 105 -VARYING_SLOT_VAR10_16BIT = 106 -VARYING_SLOT_VAR11_16BIT = 107 -VARYING_SLOT_VAR12_16BIT = 108 -VARYING_SLOT_VAR13_16BIT = 109 -VARYING_SLOT_VAR14_16BIT = 110 -VARYING_SLOT_VAR15_16BIT = 111 -NUM_TOTAL_VARYING_SLOTS = 112 -c__EA_gl_varying_slot = ctypes.c_uint32 # enum -gl_varying_slot = c__EA_gl_varying_slot -gl_varying_slot__enumvalues = c__EA_gl_varying_slot__enumvalues -try: - nir_slot_is_sysval_output = _libraries['libtinymesa_cpu.so'].nir_slot_is_sysval_output - nir_slot_is_sysval_output.restype = ctypes.c_bool - nir_slot_is_sysval_output.argtypes = [gl_varying_slot, gl_shader_stage] -except AttributeError: - pass -try: - nir_slot_is_varying = _libraries['libtinymesa_cpu.so'].nir_slot_is_varying - nir_slot_is_varying.restype = ctypes.c_bool - nir_slot_is_varying.argtypes = [gl_varying_slot, gl_shader_stage] -except AttributeError: - pass -try: - nir_slot_is_sysval_output_and_varying = _libraries['libtinymesa_cpu.so'].nir_slot_is_sysval_output_and_varying - nir_slot_is_sysval_output_and_varying.restype = ctypes.c_bool - nir_slot_is_sysval_output_and_varying.argtypes = [gl_varying_slot, gl_shader_stage] -except AttributeError: - pass -try: - nir_remove_varying = _libraries['libtinymesa_cpu.so'].nir_remove_varying - nir_remove_varying.restype = ctypes.c_bool - nir_remove_varying.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), gl_shader_stage] -except AttributeError: - pass -try: - nir_remove_sysval_output = _libraries['libtinymesa_cpu.so'].nir_remove_sysval_output - nir_remove_sysval_output.restype = ctypes.c_bool - nir_remove_sysval_output.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), gl_shader_stage] -except AttributeError: - pass -try: - nir_lower_amul = _libraries['libtinymesa_cpu.so'].nir_lower_amul - nir_lower_amul.restype = ctypes.c_bool - nir_lower_amul.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_glsl_type), ctypes.c_bool)] -except AttributeError: - pass -try: - nir_lower_ubo_vec4 = _libraries['libtinymesa_cpu.so'].nir_lower_ubo_vec4 - nir_lower_ubo_vec4.restype = ctypes.c_bool - nir_lower_ubo_vec4.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_sort_variables_by_location = _libraries['libtinymesa_cpu.so'].nir_sort_variables_by_location - nir_sort_variables_by_location.restype = None - nir_sort_variables_by_location.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_assign_io_var_locations = _libraries['libtinymesa_cpu.so'].nir_assign_io_var_locations - nir_assign_io_var_locations.restype = None - nir_assign_io_var_locations.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.POINTER(ctypes.c_uint32), gl_shader_stage] -except AttributeError: - pass -try: - nir_opt_clip_cull_const = _libraries['libtinymesa_cpu.so'].nir_opt_clip_cull_const - nir_opt_clip_cull_const.restype = ctypes.c_bool - nir_opt_clip_cull_const.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass +# nir_def *nir_build_alu2(nir_builder *build, nir_op op, nir_def *src0, nir_def *src1) +try: (nir_build_alu2:=dll.nir_build_alu2).restype, nir_build_alu2.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass -# values for enumeration 'c__EA_nir_lower_io_options' -c__EA_nir_lower_io_options__enumvalues = { - 1: 'nir_lower_io_lower_64bit_to_32', - 2: 'nir_lower_io_lower_64bit_float_to_32', - 4: 'nir_lower_io_lower_64bit_to_32_new', - 8: 'nir_lower_io_use_interpolated_input_intrinsics', -} -nir_lower_io_lower_64bit_to_32 = 1 -nir_lower_io_lower_64bit_float_to_32 = 2 -nir_lower_io_lower_64bit_to_32_new = 4 -nir_lower_io_use_interpolated_input_intrinsics = 8 -c__EA_nir_lower_io_options = ctypes.c_uint32 # enum -nir_lower_io_options = c__EA_nir_lower_io_options -nir_lower_io_options__enumvalues = c__EA_nir_lower_io_options__enumvalues -try: - nir_lower_io = _libraries['libtinymesa_cpu.so'].nir_lower_io - nir_lower_io.restype = ctypes.c_bool - nir_lower_io.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_glsl_type), ctypes.c_bool), nir_lower_io_options] -except AttributeError: - pass -try: - nir_io_add_const_offset_to_base = _libraries['libtinymesa_cpu.so'].nir_io_add_const_offset_to_base - nir_io_add_const_offset_to_base.restype = ctypes.c_bool - nir_io_add_const_offset_to_base.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_io_passes = _libraries['libtinymesa_cpu.so'].nir_lower_io_passes - nir_lower_io_passes.restype = None - nir_lower_io_passes.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_io_add_intrinsic_xfb_info = _libraries['libtinymesa_cpu.so'].nir_io_add_intrinsic_xfb_info - nir_io_add_intrinsic_xfb_info.restype = ctypes.c_bool - nir_io_add_intrinsic_xfb_info.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_io_indirect_loads = _libraries['libtinymesa_cpu.so'].nir_lower_io_indirect_loads - nir_lower_io_indirect_loads.restype = ctypes.c_bool - nir_lower_io_indirect_loads.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_vars_to_explicit_types = _libraries['libtinymesa_cpu.so'].nir_lower_vars_to_explicit_types - nir_lower_vars_to_explicit_types.restype = ctypes.c_bool - nir_lower_vars_to_explicit_types.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, glsl_type_size_align_func] -except AttributeError: - pass -try: - nir_gather_explicit_io_initializers = _libraries['libtinymesa_cpu.so'].nir_gather_explicit_io_initializers - nir_gather_explicit_io_initializers.restype = None - nir_gather_explicit_io_initializers.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(None), size_t, nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_vec3_to_vec4 = _libraries['libtinymesa_cpu.so'].nir_lower_vec3_to_vec4 - nir_lower_vec3_to_vec4.restype = ctypes.c_bool - nir_lower_vec3_to_vec4.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass +# nir_def *nir_build_alu3(nir_builder *build, nir_op op, nir_def *src0, nir_def *src1, nir_def *src2) +try: (nir_build_alu3:=dll.nir_build_alu3).restype, nir_build_alu3.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass -# values for enumeration 'c__EA_nir_address_format' -c__EA_nir_address_format__enumvalues = { - 0: 'nir_address_format_32bit_global', - 1: 'nir_address_format_64bit_global', - 2: 'nir_address_format_2x32bit_global', - 3: 'nir_address_format_64bit_global_32bit_offset', - 4: 'nir_address_format_64bit_bounded_global', - 5: 'nir_address_format_32bit_index_offset', - 6: 'nir_address_format_32bit_index_offset_pack64', - 7: 'nir_address_format_vec2_index_32bit_offset', - 8: 'nir_address_format_62bit_generic', - 9: 'nir_address_format_32bit_offset', - 10: 'nir_address_format_32bit_offset_as_64bit', - 11: 'nir_address_format_logical', -} -nir_address_format_32bit_global = 0 -nir_address_format_64bit_global = 1 -nir_address_format_2x32bit_global = 2 -nir_address_format_64bit_global_32bit_offset = 3 -nir_address_format_64bit_bounded_global = 4 -nir_address_format_32bit_index_offset = 5 -nir_address_format_32bit_index_offset_pack64 = 6 -nir_address_format_vec2_index_32bit_offset = 7 -nir_address_format_62bit_generic = 8 -nir_address_format_32bit_offset = 9 -nir_address_format_32bit_offset_as_64bit = 10 -nir_address_format_logical = 11 -c__EA_nir_address_format = ctypes.c_uint32 # enum -nir_address_format = c__EA_nir_address_format -nir_address_format__enumvalues = c__EA_nir_address_format__enumvalues -try: - nir_address_format_bit_size = _libraries['libtinymesa_cpu.so'].nir_address_format_bit_size - nir_address_format_bit_size.restype = ctypes.c_uint32 - nir_address_format_bit_size.argtypes = [nir_address_format] -except AttributeError: - pass -try: - nir_address_format_num_components = _libraries['libtinymesa_cpu.so'].nir_address_format_num_components - nir_address_format_num_components.restype = ctypes.c_uint32 - nir_address_format_num_components.argtypes = [nir_address_format] -except AttributeError: - pass -try: - nir_address_format_to_glsl_type = _libraries['FIXME_STUB'].nir_address_format_to_glsl_type - nir_address_format_to_glsl_type.restype = ctypes.POINTER(struct_glsl_type) - nir_address_format_to_glsl_type.argtypes = [nir_address_format] -except AttributeError: - pass -try: - nir_address_format_null_value = _libraries['libtinymesa_cpu.so'].nir_address_format_null_value - nir_address_format_null_value.restype = ctypes.POINTER(union_c__UA_nir_const_value) - nir_address_format_null_value.argtypes = [nir_address_format] -except AttributeError: - pass -try: - nir_build_addr_iadd = _libraries['libtinymesa_cpu.so'].nir_build_addr_iadd - nir_build_addr_iadd.restype = ctypes.POINTER(struct_nir_def) - nir_build_addr_iadd.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_address_format, nir_variable_mode, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_addr_iadd_imm = _libraries['libtinymesa_cpu.so'].nir_build_addr_iadd_imm - nir_build_addr_iadd_imm.restype = ctypes.POINTER(struct_nir_def) - nir_build_addr_iadd_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_address_format, nir_variable_mode, int64_t] -except AttributeError: - pass -try: - nir_build_addr_ieq = _libraries['libtinymesa_cpu.so'].nir_build_addr_ieq - nir_build_addr_ieq.restype = ctypes.POINTER(struct_nir_def) - nir_build_addr_ieq.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), nir_address_format] -except AttributeError: - pass -try: - nir_build_addr_isub = _libraries['libtinymesa_cpu.so'].nir_build_addr_isub - nir_build_addr_isub.restype = ctypes.POINTER(struct_nir_def) - nir_build_addr_isub.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), nir_address_format] -except AttributeError: - pass -try: - nir_explicit_io_address_from_deref = _libraries['libtinymesa_cpu.so'].nir_explicit_io_address_from_deref - nir_explicit_io_address_from_deref.restype = ctypes.POINTER(struct_nir_def) - nir_explicit_io_address_from_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), nir_address_format] -except AttributeError: - pass -try: - nir_get_explicit_deref_align = _libraries['libtinymesa_cpu.so'].nir_get_explicit_deref_align - nir_get_explicit_deref_align.restype = ctypes.c_bool - nir_get_explicit_deref_align.argtypes = [ctypes.POINTER(struct_nir_deref_instr), ctypes.c_bool, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - nir_lower_explicit_io_instr = _libraries['libtinymesa_cpu.so'].nir_lower_explicit_io_instr - nir_lower_explicit_io_instr.restype = None - nir_lower_explicit_io_instr.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_def), nir_address_format] -except AttributeError: - pass -try: - nir_lower_explicit_io = _libraries['libtinymesa_cpu.so'].nir_lower_explicit_io - nir_lower_explicit_io.restype = ctypes.c_bool - nir_lower_explicit_io.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, nir_address_format] -except AttributeError: - pass +# nir_def *nir_build_alu4(nir_builder *build, nir_op op, nir_def *src0, nir_def *src1, nir_def *src2, nir_def *src3) +try: (nir_build_alu4:=dll.nir_build_alu4).restype, nir_build_alu4.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass -# values for enumeration 'c__EA_nir_mem_access_shift_method' -c__EA_nir_mem_access_shift_method__enumvalues = { - 0: 'nir_mem_access_shift_method_scalar', - 1: 'nir_mem_access_shift_method_shift64', - 2: 'nir_mem_access_shift_method_bytealign_amd', -} -nir_mem_access_shift_method_scalar = 0 -nir_mem_access_shift_method_shift64 = 1 -nir_mem_access_shift_method_bytealign_amd = 2 -c__EA_nir_mem_access_shift_method = ctypes.c_uint32 # enum -nir_mem_access_shift_method = c__EA_nir_mem_access_shift_method -nir_mem_access_shift_method__enumvalues = c__EA_nir_mem_access_shift_method__enumvalues -class struct_nir_mem_access_size_align(Structure): - pass +# nir_def *nir_build_alu_src_arr(nir_builder *build, nir_op op, nir_def **srcs) +try: (nir_build_alu_src_arr:=dll.nir_build_alu_src_arr).restype, nir_build_alu_src_arr.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(ctypes.POINTER(nir_def))] +except AttributeError: pass -struct_nir_mem_access_size_align._pack_ = 1 # source:False -struct_nir_mem_access_size_align._fields_ = [ - ('num_components', ctypes.c_ubyte), - ('bit_size', ctypes.c_ubyte), - ('align', ctypes.c_uint16), - ('shift', nir_mem_access_shift_method), +# nir_def *nir_build_tex_deref_instr(nir_builder *build, nir_texop op, nir_deref_instr *texture, nir_deref_instr *sampler, unsigned int num_extra_srcs, const nir_tex_src *extra_srcs) +try: (nir_build_tex_deref_instr:=dll.nir_build_tex_deref_instr).restype, nir_build_tex_deref_instr.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_texop, ctypes.POINTER(nir_deref_instr), ctypes.POINTER(nir_deref_instr), ctypes.c_uint32, ctypes.POINTER(nir_tex_src)] +except AttributeError: pass + +# void nir_builder_cf_insert(nir_builder *build, nir_cf_node *cf) +try: (nir_builder_cf_insert:=dll.nir_builder_cf_insert).restype, nir_builder_cf_insert.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# bool nir_builder_is_inside_cf(nir_builder *build, nir_cf_node *cf_node) +try: (nir_builder_is_inside_cf:=dll.nir_builder_is_inside_cf).restype, nir_builder_is_inside_cf.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_cf_node)] +except AttributeError: pass + +# nir_if *nir_push_if(nir_builder *build, nir_def *condition) +try: (nir_push_if:=dll.nir_push_if).restype, nir_push_if.argtypes = ctypes.POINTER(nir_if), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# nir_if *nir_push_else(nir_builder *build, nir_if *nif) +try: (nir_push_else:=dll.nir_push_else).restype, nir_push_else.argtypes = ctypes.POINTER(nir_if), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_if)] +except AttributeError: pass + +# void nir_pop_if(nir_builder *build, nir_if *nif) +try: (nir_pop_if:=dll.nir_pop_if).restype, nir_pop_if.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_if)] +except AttributeError: pass + +# nir_def *nir_if_phi(nir_builder *build, nir_def *then_def, nir_def *else_def) +try: (nir_if_phi:=dll.nir_if_phi).restype, nir_if_phi.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# nir_loop *nir_push_loop(nir_builder *build) +try: (nir_push_loop:=dll.nir_push_loop).restype, nir_push_loop.argtypes = ctypes.POINTER(nir_loop), [ctypes.POINTER(nir_builder)] +except AttributeError: pass + +# nir_loop *nir_push_continue(nir_builder *build, nir_loop *loop) +try: (nir_push_continue:=dll.nir_push_continue).restype, nir_push_continue.argtypes = ctypes.POINTER(nir_loop), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_loop)] +except AttributeError: pass + +# void nir_pop_loop(nir_builder *build, nir_loop *loop) +try: (nir_pop_loop:=dll.nir_pop_loop).restype, nir_pop_loop.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_loop)] +except AttributeError: pass + +# nir_def *nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr) +try: (nir_builder_alu_instr_finish_and_insert:=dll.nir_builder_alu_instr_finish_and_insert).restype, nir_builder_alu_instr_finish_and_insert.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_alu_instr)] +except AttributeError: pass + +# nir_def *nir_build_alu_src_arr(nir_builder *build, nir_op op, nir_def **srcs) +try: (nir_build_alu_src_arr:=dll.nir_build_alu_src_arr).restype, nir_build_alu_src_arr.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_op, ctypes.POINTER(ctypes.POINTER(nir_def))] +except AttributeError: pass + +# nir_def *nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index, unsigned int num_components, unsigned int bit_size) +try: (nir_load_system_value:=dll.nir_load_system_value).restype, nir_load_system_value.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), nir_intrinsic_op, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# nir_def *nir_type_convert(nir_builder *b, nir_def *src, nir_alu_type src_type, nir_alu_type dest_type, nir_rounding_mode rnd) +try: (nir_type_convert:=dll.nir_type_convert).restype, nir_type_convert.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), nir_alu_type, nir_alu_type, nir_rounding_mode] +except AttributeError: pass + +# nir_def *nir_vec_scalars(nir_builder *build, nir_scalar *comp, unsigned int num_components) +try: (nir_vec_scalars:=dll.nir_vec_scalars).restype, nir_vec_scalars.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_scalar), ctypes.c_uint32] +except AttributeError: pass + +# nir_def *nir_ssa_for_alu_src(nir_builder *build, nir_alu_instr *instr, unsigned int srcn) +try: (nir_ssa_for_alu_src:=dll.nir_ssa_for_alu_src).restype, nir_ssa_for_alu_src.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_alu_instr), ctypes.c_uint32] +except AttributeError: pass + +# nir_def *nir_build_string(nir_builder *build, const char *value) +try: (nir_build_string:=dll.nir_build_string).restype, nir_build_string.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nir_def *nir_compare_func(nir_builder *b, enum compare_func func, nir_def *src0, nir_def *src1) +try: (nir_compare_func:=dll.nir_compare_func).restype, nir_compare_func.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), enum_compare_func, ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# nir_def *nir_gen_rect_vertices(nir_builder *b, nir_def *z, nir_def *w) +try: (nir_gen_rect_vertices:=dll.nir_gen_rect_vertices).restype, nir_gen_rect_vertices.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(nir_def), ctypes.POINTER(nir_def)] +except AttributeError: pass + +# void nir_printf_fmt(nir_builder *b, unsigned int ptr_bit_size, const char *fmt, ...) +try: (nir_printf_fmt:=dll.nir_printf_fmt).restype, nir_printf_fmt.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void nir_printf_fmt_at_px(nir_builder *b, unsigned int ptr_bit_size, unsigned int x, unsigned int y, const char *fmt, ...) +try: (nir_printf_fmt_at_px:=dll.nir_printf_fmt_at_px).restype, nir_printf_fmt_at_px.argtypes = None, [ctypes.POINTER(nir_builder), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nir_def *nir_call_serialized(nir_builder *build, const uint32_t *serialized, size_t serialized_size_B, nir_def **args) +try: (nir_call_serialized:=dll.nir_call_serialized).restype, nir_call_serialized.argtypes = ctypes.POINTER(nir_def), [ctypes.POINTER(nir_builder), ctypes.POINTER(uint32_t), size_t, ctypes.POINTER(ctypes.POINTER(nir_def))] +except AttributeError: pass + +nir_lower_packing_op = CEnum(ctypes.c_uint32) +nir_lower_packing_op_pack_64_2x32 = nir_lower_packing_op.define('nir_lower_packing_op_pack_64_2x32', 0) +nir_lower_packing_op_unpack_64_2x32 = nir_lower_packing_op.define('nir_lower_packing_op_unpack_64_2x32', 1) +nir_lower_packing_op_pack_64_4x16 = nir_lower_packing_op.define('nir_lower_packing_op_pack_64_4x16', 2) +nir_lower_packing_op_unpack_64_4x16 = nir_lower_packing_op.define('nir_lower_packing_op_unpack_64_4x16', 3) +nir_lower_packing_op_pack_32_2x16 = nir_lower_packing_op.define('nir_lower_packing_op_pack_32_2x16', 4) +nir_lower_packing_op_unpack_32_2x16 = nir_lower_packing_op.define('nir_lower_packing_op_unpack_32_2x16', 5) +nir_lower_packing_op_pack_32_4x8 = nir_lower_packing_op.define('nir_lower_packing_op_pack_32_4x8', 6) +nir_lower_packing_op_unpack_32_4x8 = nir_lower_packing_op.define('nir_lower_packing_op_unpack_32_4x8', 7) +nir_lower_packing_num_ops = nir_lower_packing_op.define('nir_lower_packing_num_ops', 8) + +class struct_blob(Struct): pass +struct_blob._fields_ = [ + ('data', ctypes.POINTER(uint8_t)), + ('allocated', size_t), + ('size', size_t), + ('fixed_allocation', ctypes.c_bool), + ('out_of_memory', ctypes.c_bool), ] +# void nir_serialize(struct blob *blob, const nir_shader *nir, _Bool strip) +try: (nir_serialize:=dll.nir_serialize).restype, nir_serialize.argtypes = None, [ctypes.POINTER(struct_blob), ctypes.POINTER(nir_shader), ctypes.c_bool] +except AttributeError: pass -nir_mem_access_size_align = struct_nir_mem_access_size_align - -# values for enumeration 'gl_access_qualifier' -gl_access_qualifier__enumvalues = { - 1: 'ACCESS_COHERENT', - 2: 'ACCESS_RESTRICT', - 4: 'ACCESS_VOLATILE', - 8: 'ACCESS_NON_READABLE', - 16: 'ACCESS_NON_WRITEABLE', - 32: 'ACCESS_NON_UNIFORM', - 64: 'ACCESS_CAN_REORDER', - 128: 'ACCESS_NON_TEMPORAL', - 256: 'ACCESS_INCLUDE_HELPERS', - 512: 'ACCESS_IS_SWIZZLED_AMD', - 1024: 'ACCESS_USES_FORMAT_AMD', - 2048: 'ACCESS_FMASK_LOWERED_AMD', - 4096: 'ACCESS_CAN_SPECULATE', - 8192: 'ACCESS_CP_GE_COHERENT_AMD', - 16384: 'ACCESS_IN_BOUNDS', - 32768: 'ACCESS_KEEP_SCALAR', - 65536: 'ACCESS_SMEM_AMD', -} -ACCESS_COHERENT = 1 -ACCESS_RESTRICT = 2 -ACCESS_VOLATILE = 4 -ACCESS_NON_READABLE = 8 -ACCESS_NON_WRITEABLE = 16 -ACCESS_NON_UNIFORM = 32 -ACCESS_CAN_REORDER = 64 -ACCESS_NON_TEMPORAL = 128 -ACCESS_INCLUDE_HELPERS = 256 -ACCESS_IS_SWIZZLED_AMD = 512 -ACCESS_USES_FORMAT_AMD = 1024 -ACCESS_FMASK_LOWERED_AMD = 2048 -ACCESS_CAN_SPECULATE = 4096 -ACCESS_CP_GE_COHERENT_AMD = 8192 -ACCESS_IN_BOUNDS = 16384 -ACCESS_KEEP_SCALAR = 32768 -ACCESS_SMEM_AMD = 65536 -gl_access_qualifier = ctypes.c_uint32 # enum -nir_lower_mem_access_bit_sizes_cb = ctypes.CFUNCTYPE(struct_nir_mem_access_size_align, c__EA_nir_intrinsic_op, ctypes.c_ubyte, ctypes.c_ubyte, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, gl_access_qualifier, ctypes.POINTER(None)) -class struct_nir_lower_mem_access_bit_sizes_options(Structure): - pass - -struct_nir_lower_mem_access_bit_sizes_options._pack_ = 1 # source:False -struct_nir_lower_mem_access_bit_sizes_options._fields_ = [ - ('callback', ctypes.CFUNCTYPE(struct_nir_mem_access_size_align, c__EA_nir_intrinsic_op, ctypes.c_ubyte, ctypes.c_ubyte, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, gl_access_qualifier, ctypes.POINTER(None))), - ('modes', nir_variable_mode), - ('may_lower_unaligned_stores_to_atomics', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('cb_data', ctypes.POINTER(None)), +class struct_blob_reader(Struct): pass +struct_blob_reader._fields_ = [ + ('data', ctypes.POINTER(uint8_t)), + ('end', ctypes.POINTER(uint8_t)), + ('current', ctypes.POINTER(uint8_t)), + ('overrun', ctypes.c_bool), ] - -nir_lower_mem_access_bit_sizes_options = struct_nir_lower_mem_access_bit_sizes_options -try: - nir_lower_mem_access_bit_sizes = _libraries['libtinymesa_cpu.so'].nir_lower_mem_access_bit_sizes - nir_lower_mem_access_bit_sizes.restype = ctypes.c_bool - nir_lower_mem_access_bit_sizes.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_mem_access_bit_sizes_options)] -except AttributeError: - pass -try: - nir_lower_robust_access = _libraries['libtinymesa_cpu.so'].nir_lower_robust_access - nir_lower_robust_access.restype = ctypes.c_bool - nir_lower_robust_access.argtypes = [ctypes.POINTER(struct_nir_shader), nir_intrin_filter_cb, ctypes.POINTER(None)] -except AttributeError: - pass -nir_should_vectorize_mem_func = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int64, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None)) -class struct_nir_load_store_vectorize_options(Structure): - pass - -struct_nir_load_store_vectorize_options._pack_ = 1 # source:False -struct_nir_load_store_vectorize_options._fields_ = [ - ('callback', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int64, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None))), - ('modes', nir_variable_mode), - ('robust_modes', nir_variable_mode), - ('cb_data', ctypes.POINTER(None)), - ('has_shared2_amd', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -nir_load_store_vectorize_options = struct_nir_load_store_vectorize_options -try: - nir_opt_load_store_vectorize = _libraries['libtinymesa_cpu.so'].nir_opt_load_store_vectorize - nir_opt_load_store_vectorize.restype = ctypes.c_bool - nir_opt_load_store_vectorize.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_load_store_vectorize_options)] -except AttributeError: - pass -try: - nir_opt_load_store_update_alignments = _libraries['libtinymesa_cpu.so'].nir_opt_load_store_update_alignments - nir_opt_load_store_update_alignments.restype = ctypes.c_bool - nir_opt_load_store_update_alignments.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -nir_lower_shader_calls_should_remat_func = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)) -class struct_nir_lower_shader_calls_options(Structure): - pass - -struct_nir_lower_shader_calls_options._pack_ = 1 # source:False -struct_nir_lower_shader_calls_options._fields_ = [ - ('address_format', nir_address_format), - ('stack_alignment', ctypes.c_uint32), - ('localized_loads', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), - ('vectorizer_callback', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int64, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None))), - ('vectorizer_data', ctypes.POINTER(None)), - ('should_remat_callback', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('should_remat_data', ctypes.POINTER(None)), -] - -nir_lower_shader_calls_options = struct_nir_lower_shader_calls_options -try: - nir_lower_shader_calls = _libraries['libtinymesa_cpu.so'].nir_lower_shader_calls - nir_lower_shader_calls.restype = ctypes.c_bool - nir_lower_shader_calls.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_shader_calls_options), ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(struct_nir_shader))), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_get_io_offset_src_number = _libraries['libtinymesa_cpu.so'].nir_get_io_offset_src_number - nir_get_io_offset_src_number.restype = ctypes.c_int32 - nir_get_io_offset_src_number.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_get_io_index_src_number = _libraries['libtinymesa_cpu.so'].nir_get_io_index_src_number - nir_get_io_index_src_number.restype = ctypes.c_int32 - nir_get_io_index_src_number.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_get_io_arrayed_index_src_number = _libraries['libtinymesa_cpu.so'].nir_get_io_arrayed_index_src_number - nir_get_io_arrayed_index_src_number.restype = ctypes.c_int32 - nir_get_io_arrayed_index_src_number.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_get_io_offset_src = _libraries['libtinymesa_cpu.so'].nir_get_io_offset_src - nir_get_io_offset_src.restype = ctypes.POINTER(struct_nir_src) - nir_get_io_offset_src.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_get_io_index_src = _libraries['libtinymesa_cpu.so'].nir_get_io_index_src - nir_get_io_index_src.restype = ctypes.POINTER(struct_nir_src) - nir_get_io_index_src.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_get_io_arrayed_index_src = _libraries['libtinymesa_cpu.so'].nir_get_io_arrayed_index_src - nir_get_io_arrayed_index_src.restype = ctypes.POINTER(struct_nir_src) - nir_get_io_arrayed_index_src.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_get_shader_call_payload_src = _libraries['libtinymesa_cpu.so'].nir_get_shader_call_payload_src - nir_get_shader_call_payload_src.restype = ctypes.POINTER(struct_nir_src) - nir_get_shader_call_payload_src.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_is_output_load = _libraries['libtinymesa_cpu.so'].nir_is_output_load - nir_is_output_load.restype = ctypes.c_bool - nir_is_output_load.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_is_arrayed_io = _libraries['libtinymesa_cpu.so'].nir_is_arrayed_io - nir_is_arrayed_io.restype = ctypes.c_bool - nir_is_arrayed_io.argtypes = [ctypes.POINTER(struct_nir_variable), gl_shader_stage] -except AttributeError: - pass -try: - nir_lower_reg_intrinsics_to_ssa_impl = _libraries['libtinymesa_cpu.so'].nir_lower_reg_intrinsics_to_ssa_impl - nir_lower_reg_intrinsics_to_ssa_impl.restype = ctypes.c_bool - nir_lower_reg_intrinsics_to_ssa_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_lower_reg_intrinsics_to_ssa = _libraries['libtinymesa_cpu.so'].nir_lower_reg_intrinsics_to_ssa - nir_lower_reg_intrinsics_to_ssa.restype = ctypes.c_bool - nir_lower_reg_intrinsics_to_ssa.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_vars_to_ssa = _libraries['libtinymesa_cpu.so'].nir_lower_vars_to_ssa - nir_lower_vars_to_ssa.restype = ctypes.c_bool - nir_lower_vars_to_ssa.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_remove_dead_derefs = _libraries['libtinymesa_cpu.so'].nir_remove_dead_derefs - nir_remove_dead_derefs.restype = ctypes.c_bool - nir_remove_dead_derefs.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_remove_dead_derefs_impl = _libraries['libtinymesa_cpu.so'].nir_remove_dead_derefs_impl - nir_remove_dead_derefs_impl.restype = ctypes.c_bool - nir_remove_dead_derefs_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -class struct_nir_remove_dead_variables_options(Structure): - pass - -struct_nir_remove_dead_variables_options._pack_ = 1 # source:False -struct_nir_remove_dead_variables_options._fields_ = [ - ('can_remove_var', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_variable), ctypes.POINTER(None))), - ('can_remove_var_data', ctypes.POINTER(None)), -] - -nir_remove_dead_variables_options = struct_nir_remove_dead_variables_options -try: - nir_remove_dead_variables = _libraries['libtinymesa_cpu.so'].nir_remove_dead_variables - nir_remove_dead_variables.restype = ctypes.c_bool - nir_remove_dead_variables.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.POINTER(struct_nir_remove_dead_variables_options)] -except AttributeError: - pass -try: - nir_lower_variable_initializers = _libraries['libtinymesa_cpu.so'].nir_lower_variable_initializers - nir_lower_variable_initializers.restype = ctypes.c_bool - nir_lower_variable_initializers.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_zero_initialize_shared_memory = _libraries['libtinymesa_cpu.so'].nir_zero_initialize_shared_memory - nir_zero_initialize_shared_memory.restype = ctypes.c_bool - nir_zero_initialize_shared_memory.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_clear_shared_memory = _libraries['libtinymesa_cpu.so'].nir_clear_shared_memory - nir_clear_shared_memory.restype = ctypes.c_bool - nir_clear_shared_memory.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_opt_move_to_top_options' -c__EA_nir_opt_move_to_top_options__enumvalues = { - 1: 'nir_move_to_entry_block_only', - 2: 'nir_move_to_top_input_loads', - 4: 'nir_move_to_top_load_smem_amd', -} -nir_move_to_entry_block_only = 1 -nir_move_to_top_input_loads = 2 -nir_move_to_top_load_smem_amd = 4 -c__EA_nir_opt_move_to_top_options = ctypes.c_uint32 # enum -nir_opt_move_to_top_options = c__EA_nir_opt_move_to_top_options -nir_opt_move_to_top_options__enumvalues = c__EA_nir_opt_move_to_top_options__enumvalues -try: - nir_opt_move_to_top = _libraries['libtinymesa_cpu.so'].nir_opt_move_to_top - nir_opt_move_to_top.restype = ctypes.c_bool - nir_opt_move_to_top.argtypes = [ctypes.POINTER(struct_nir_shader), nir_opt_move_to_top_options] -except AttributeError: - pass -try: - nir_move_vec_src_uses_to_dest = _libraries['libtinymesa_cpu.so'].nir_move_vec_src_uses_to_dest - nir_move_vec_src_uses_to_dest.restype = ctypes.c_bool - nir_move_vec_src_uses_to_dest.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_move_output_stores_to_end = _libraries['libtinymesa_cpu.so'].nir_move_output_stores_to_end - nir_move_output_stores_to_end.restype = ctypes.c_bool - nir_move_output_stores_to_end.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_vec_to_regs = _libraries['libtinymesa_cpu.so'].nir_lower_vec_to_regs - nir_lower_vec_to_regs.restype = ctypes.c_bool - nir_lower_vec_to_regs.argtypes = [ctypes.POINTER(struct_nir_shader), nir_instr_writemask_filter_cb, ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'compare_func' -compare_func__enumvalues = { - 0: 'COMPARE_FUNC_NEVER', - 1: 'COMPARE_FUNC_LESS', - 2: 'COMPARE_FUNC_EQUAL', - 3: 'COMPARE_FUNC_LEQUAL', - 4: 'COMPARE_FUNC_GREATER', - 5: 'COMPARE_FUNC_NOTEQUAL', - 6: 'COMPARE_FUNC_GEQUAL', - 7: 'COMPARE_FUNC_ALWAYS', -} -COMPARE_FUNC_NEVER = 0 -COMPARE_FUNC_LESS = 1 -COMPARE_FUNC_EQUAL = 2 -COMPARE_FUNC_LEQUAL = 3 -COMPARE_FUNC_GREATER = 4 -COMPARE_FUNC_NOTEQUAL = 5 -COMPARE_FUNC_GEQUAL = 6 -COMPARE_FUNC_ALWAYS = 7 -compare_func = ctypes.c_uint32 # enum -try: - nir_lower_alpha_test = _libraries['libtinymesa_cpu.so'].nir_lower_alpha_test - nir_lower_alpha_test.restype = ctypes.c_bool - nir_lower_alpha_test.argtypes = [ctypes.POINTER(struct_nir_shader), compare_func, ctypes.c_bool, ctypes.POINTER(ctypes.c_int16)] -except AttributeError: - pass -try: - nir_lower_alpha_to_coverage = _libraries['libtinymesa_cpu.so'].nir_lower_alpha_to_coverage - nir_lower_alpha_to_coverage.restype = ctypes.c_bool - nir_lower_alpha_to_coverage.argtypes = [ctypes.POINTER(struct_nir_shader), uint8_t, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_alpha_to_one = _libraries['libtinymesa_cpu.so'].nir_lower_alpha_to_one - nir_lower_alpha_to_one.restype = ctypes.c_bool - nir_lower_alpha_to_one.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_alu = _libraries['libtinymesa_cpu.so'].nir_lower_alu - nir_lower_alu.restype = ctypes.c_bool - nir_lower_alu.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_flrp = _libraries['libtinymesa_cpu.so'].nir_lower_flrp - nir_lower_flrp.restype = ctypes.c_bool - nir_lower_flrp.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_bool] -except AttributeError: - pass -try: - nir_scale_fdiv = _libraries['libtinymesa_cpu.so'].nir_scale_fdiv - nir_scale_fdiv.restype = ctypes.c_bool - nir_scale_fdiv.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_alu_to_scalar = _libraries['libtinymesa_cpu.so'].nir_lower_alu_to_scalar - nir_lower_alu_to_scalar.restype = ctypes.c_bool - nir_lower_alu_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader), nir_instr_filter_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_alu_width = _libraries['libtinymesa_cpu.so'].nir_lower_alu_width - nir_lower_alu_width.restype = ctypes.c_bool - nir_lower_alu_width.argtypes = [ctypes.POINTER(struct_nir_shader), nir_vectorize_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_alu_vec8_16_srcs = _libraries['libtinymesa_cpu.so'].nir_lower_alu_vec8_16_srcs - nir_lower_alu_vec8_16_srcs.restype = ctypes.c_bool - nir_lower_alu_vec8_16_srcs.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_bool_to_bitsize = _libraries['libtinymesa_cpu.so'].nir_lower_bool_to_bitsize - nir_lower_bool_to_bitsize.restype = ctypes.c_bool - nir_lower_bool_to_bitsize.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_bool_to_float = _libraries['libtinymesa_cpu.so'].nir_lower_bool_to_float - nir_lower_bool_to_float.restype = ctypes.c_bool - nir_lower_bool_to_float.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_bool_to_int32 = _libraries['libtinymesa_cpu.so'].nir_lower_bool_to_int32 - nir_lower_bool_to_int32.restype = ctypes.c_bool - nir_lower_bool_to_int32.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_simplify_convert_alu_types = _libraries['libtinymesa_cpu.so'].nir_opt_simplify_convert_alu_types - nir_opt_simplify_convert_alu_types.restype = ctypes.c_bool - nir_opt_simplify_convert_alu_types.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_const_arrays_to_uniforms = _libraries['libtinymesa_cpu.so'].nir_lower_const_arrays_to_uniforms - nir_lower_const_arrays_to_uniforms.restype = ctypes.c_bool - nir_lower_const_arrays_to_uniforms.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_lower_convert_alu_types = _libraries['libtinymesa_cpu.so'].nir_lower_convert_alu_types - nir_lower_convert_alu_types.restype = ctypes.c_bool - nir_lower_convert_alu_types.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_intrinsic_instr))] -except AttributeError: - pass -try: - nir_lower_constant_convert_alu_types = _libraries['libtinymesa_cpu.so'].nir_lower_constant_convert_alu_types - nir_lower_constant_convert_alu_types.restype = ctypes.c_bool - nir_lower_constant_convert_alu_types.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_alu_conversion_to_intrinsic = _libraries['libtinymesa_cpu.so'].nir_lower_alu_conversion_to_intrinsic - nir_lower_alu_conversion_to_intrinsic.restype = ctypes.c_bool - nir_lower_alu_conversion_to_intrinsic.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_int_to_float = _libraries['libtinymesa_cpu.so'].nir_lower_int_to_float - nir_lower_int_to_float.restype = ctypes.c_bool - nir_lower_int_to_float.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_load_const_to_scalar = _libraries['libtinymesa_cpu.so'].nir_lower_load_const_to_scalar - nir_lower_load_const_to_scalar.restype = ctypes.c_bool - nir_lower_load_const_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_read_invocation_to_scalar = _libraries['FIXME_STUB'].nir_lower_read_invocation_to_scalar - nir_lower_read_invocation_to_scalar.restype = ctypes.c_bool - nir_lower_read_invocation_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_phis_to_scalar = _libraries['libtinymesa_cpu.so'].nir_lower_phis_to_scalar - nir_lower_phis_to_scalar.restype = ctypes.c_bool - nir_lower_phis_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader), nir_vectorize_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_all_phis_to_scalar = _libraries['libtinymesa_cpu.so'].nir_lower_all_phis_to_scalar - nir_lower_all_phis_to_scalar.restype = ctypes.c_bool - nir_lower_all_phis_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_io_array_vars_to_elements = _libraries['libtinymesa_cpu.so'].nir_lower_io_array_vars_to_elements - nir_lower_io_array_vars_to_elements.restype = None - nir_lower_io_array_vars_to_elements.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_io_array_vars_to_elements_no_indirects = _libraries['libtinymesa_cpu.so'].nir_lower_io_array_vars_to_elements_no_indirects - nir_lower_io_array_vars_to_elements_no_indirects.restype = ctypes.c_bool - nir_lower_io_array_vars_to_elements_no_indirects.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_io_to_scalar = _libraries['libtinymesa_cpu.so'].nir_lower_io_to_scalar - nir_lower_io_to_scalar.restype = ctypes.c_bool - nir_lower_io_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, nir_instr_filter_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_io_vars_to_scalar = _libraries['libtinymesa_cpu.so'].nir_lower_io_vars_to_scalar - nir_lower_io_vars_to_scalar.restype = ctypes.c_bool - nir_lower_io_vars_to_scalar.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_opt_vectorize_io_vars = _libraries['libtinymesa_cpu.so'].nir_opt_vectorize_io_vars - nir_opt_vectorize_io_vars.restype = ctypes.c_bool - nir_opt_vectorize_io_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_tess_level_array_vars_to_vec = _libraries['libtinymesa_cpu.so'].nir_lower_tess_level_array_vars_to_vec - nir_lower_tess_level_array_vars_to_vec.restype = ctypes.c_bool - nir_lower_tess_level_array_vars_to_vec.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_create_passthrough_tcs_impl = _libraries['libtinymesa_cpu.so'].nir_create_passthrough_tcs_impl - nir_create_passthrough_tcs_impl.restype = ctypes.POINTER(struct_nir_shader) - nir_create_passthrough_tcs_impl.argtypes = [ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32, uint8_t] -except AttributeError: - pass -try: - nir_create_passthrough_tcs = _libraries['libtinymesa_cpu.so'].nir_create_passthrough_tcs - nir_create_passthrough_tcs.restype = ctypes.POINTER(struct_nir_shader) - nir_create_passthrough_tcs.argtypes = [ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_nir_shader), uint8_t] -except AttributeError: - pass -try: - nir_create_passthrough_gs = _libraries['libtinymesa_cpu.so'].nir_create_passthrough_gs - nir_create_passthrough_gs.restype = ctypes.POINTER(struct_nir_shader) - nir_create_passthrough_gs.argtypes = [ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_nir_shader), mesa_prim, mesa_prim, ctypes.c_bool, ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_fragcolor = _libraries['libtinymesa_cpu.so'].nir_lower_fragcolor - nir_lower_fragcolor.restype = ctypes.c_bool - nir_lower_fragcolor.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_lower_fragcoord_wtrans = _libraries['libtinymesa_cpu.so'].nir_lower_fragcoord_wtrans - nir_lower_fragcoord_wtrans.restype = ctypes.c_bool - nir_lower_fragcoord_wtrans.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_frag_coord_to_pixel_coord = _libraries['libtinymesa_cpu.so'].nir_opt_frag_coord_to_pixel_coord - nir_opt_frag_coord_to_pixel_coord.restype = ctypes.c_bool - nir_opt_frag_coord_to_pixel_coord.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_frag_coord_to_pixel_coord = _libraries['libtinymesa_cpu.so'].nir_lower_frag_coord_to_pixel_coord - nir_lower_frag_coord_to_pixel_coord.restype = ctypes.c_bool - nir_lower_frag_coord_to_pixel_coord.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_viewport_transform = _libraries['libtinymesa_cpu.so'].nir_lower_viewport_transform - nir_lower_viewport_transform.restype = ctypes.c_bool - nir_lower_viewport_transform.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_uniforms_to_ubo = _libraries['libtinymesa_cpu.so'].nir_lower_uniforms_to_ubo - nir_lower_uniforms_to_ubo.restype = ctypes.c_bool - nir_lower_uniforms_to_ubo.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_is_helper_invocation = _libraries['libtinymesa_cpu.so'].nir_lower_is_helper_invocation - nir_lower_is_helper_invocation.restype = ctypes.c_bool - nir_lower_is_helper_invocation.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_single_sampled = _libraries['libtinymesa_cpu.so'].nir_lower_single_sampled - nir_lower_single_sampled.restype = ctypes.c_bool - nir_lower_single_sampled.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_atomics = _libraries['libtinymesa_cpu.so'].nir_lower_atomics - nir_lower_atomics.restype = ctypes.c_bool - nir_lower_atomics.argtypes = [ctypes.POINTER(struct_nir_shader), nir_instr_filter_cb] -except AttributeError: - pass -class struct_nir_lower_subgroups_options(Structure): - pass - -struct_nir_lower_subgroups_options._pack_ = 1 # source:False -struct_nir_lower_subgroups_options._fields_ = [ - ('filter', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('filter_data', ctypes.POINTER(None)), - ('subgroup_size', ctypes.c_ubyte), - ('ballot_bit_size', ctypes.c_ubyte), - ('ballot_components', ctypes.c_ubyte), - ('lower_to_scalar', ctypes.c_bool, 1), - ('lower_vote_trivial', ctypes.c_bool, 1), - ('lower_vote_feq', ctypes.c_bool, 1), - ('lower_vote_ieq', ctypes.c_bool, 1), - ('lower_vote_bool_eq', ctypes.c_bool, 1), - ('lower_first_invocation_to_ballot', ctypes.c_bool, 1), - ('lower_read_first_invocation', ctypes.c_bool, 1), - ('lower_subgroup_masks', ctypes.c_bool, 1), - ('lower_relative_shuffle', ctypes.c_bool, 1), - ('lower_shuffle_to_32bit', ctypes.c_bool, 1), - ('lower_shuffle_to_swizzle_amd', ctypes.c_bool, 1), - ('lower_shuffle', ctypes.c_bool, 1), - ('lower_quad', ctypes.c_bool, 1), - ('lower_quad_broadcast_dynamic', ctypes.c_bool, 1), - ('lower_quad_broadcast_dynamic_to_const', ctypes.c_bool, 1), - ('lower_quad_vote', ctypes.c_bool, 1), - ('lower_elect', ctypes.c_bool, 1), - ('lower_read_invocation_to_cond', ctypes.c_bool, 1), - ('lower_rotate_to_shuffle', ctypes.c_bool, 1), - ('lower_rotate_clustered_to_shuffle', ctypes.c_bool, 1), - ('lower_ballot_bit_count_to_mbcnt_amd', ctypes.c_bool, 1), - ('lower_inverse_ballot', ctypes.c_bool, 1), - ('lower_reduce', ctypes.c_bool, 1), - ('lower_boolean_reduce', ctypes.c_bool, 1), - ('lower_boolean_shuffle', ctypes.c_bool, 1), - ('PADDING_0', ctypes.c_uint16, 15), -] - -nir_lower_subgroups_options = struct_nir_lower_subgroups_options -try: - nir_lower_subgroups = _libraries['libtinymesa_cpu.so'].nir_lower_subgroups - nir_lower_subgroups.restype = ctypes.c_bool - nir_lower_subgroups.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_subgroups_options)] -except AttributeError: - pass -try: - nir_lower_system_values = _libraries['libtinymesa_cpu.so'].nir_lower_system_values - nir_lower_system_values.restype = ctypes.c_bool - nir_lower_system_values.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_build_lowered_load_helper_invocation = _libraries['libtinymesa_cpu.so'].nir_build_lowered_load_helper_invocation - nir_build_lowered_load_helper_invocation.restype = ctypes.POINTER(struct_nir_def) - nir_build_lowered_load_helper_invocation.argtypes = [ctypes.POINTER(struct_nir_builder)] -except AttributeError: - pass -class struct_nir_lower_compute_system_values_options(Structure): - pass - -struct_nir_lower_compute_system_values_options._pack_ = 1 # source:False -struct_nir_lower_compute_system_values_options._fields_ = [ - ('has_base_global_invocation_id', ctypes.c_bool, 1), - ('has_base_workgroup_id', ctypes.c_bool, 1), - ('has_global_size', ctypes.c_bool, 1), - ('shuffle_local_ids_for_quad_derivatives', ctypes.c_bool, 1), - ('lower_local_invocation_index', ctypes.c_bool, 1), - ('lower_cs_local_id_to_index', ctypes.c_bool, 1), - ('lower_workgroup_id_to_index', ctypes.c_bool, 1), - ('global_id_is_32bit', ctypes.c_bool, 1), - ('shortcut_1d_workgroup_id', ctypes.c_bool, 1), - ('PADDING_0', ctypes.c_uint32, 23), - ('num_workgroups', ctypes.c_uint32 * 3), -] - -nir_lower_compute_system_values_options = struct_nir_lower_compute_system_values_options -try: - nir_lower_compute_system_values = _libraries['libtinymesa_cpu.so'].nir_lower_compute_system_values - nir_lower_compute_system_values.restype = ctypes.c_bool - nir_lower_compute_system_values.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_compute_system_values_options)] -except AttributeError: - pass -class struct_nir_lower_sysvals_to_varyings_options(Structure): - pass - -struct_nir_lower_sysvals_to_varyings_options._pack_ = 1 # source:False -struct_nir_lower_sysvals_to_varyings_options._fields_ = [ - ('frag_coord', ctypes.c_bool, 1), - ('front_face', ctypes.c_bool, 1), - ('point_coord', ctypes.c_bool, 1), - ('PADDING_0', ctypes.c_uint8, 5), -] - -nir_lower_sysvals_to_varyings_options = struct_nir_lower_sysvals_to_varyings_options -try: - nir_lower_sysvals_to_varyings = _libraries['libtinymesa_cpu.so'].nir_lower_sysvals_to_varyings - nir_lower_sysvals_to_varyings.restype = ctypes.c_bool - nir_lower_sysvals_to_varyings.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_sysvals_to_varyings_options)] -except AttributeError: - pass - -# values for enumeration 'nir_lower_tex_packing' -nir_lower_tex_packing__enumvalues = { - 0: 'nir_lower_tex_packing_none', - 1: 'nir_lower_tex_packing_16', - 2: 'nir_lower_tex_packing_8', -} -nir_lower_tex_packing_none = 0 -nir_lower_tex_packing_16 = 1 -nir_lower_tex_packing_8 = 2 -nir_lower_tex_packing = ctypes.c_uint32 # enum -class struct_nir_lower_tex_options(Structure): - pass - -struct_nir_lower_tex_options._pack_ = 1 # source:False -struct_nir_lower_tex_options._fields_ = [ - ('lower_txp', ctypes.c_uint32), - ('lower_txp_array', ctypes.c_bool), - ('lower_txf_offset', ctypes.c_bool), - ('lower_rect_offset', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), - ('lower_offset_filter', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('lower_rect', ctypes.c_bool), - ('lower_1d', ctypes.c_bool), - ('lower_1d_shadow', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte), - ('lower_y_uv_external', ctypes.c_uint32), - ('lower_y_vu_external', ctypes.c_uint32), - ('lower_y_u_v_external', ctypes.c_uint32), - ('lower_yx_xuxv_external', ctypes.c_uint32), - ('lower_yx_xvxu_external', ctypes.c_uint32), - ('lower_xy_uxvx_external', ctypes.c_uint32), - ('lower_xy_vxux_external', ctypes.c_uint32), - ('lower_ayuv_external', ctypes.c_uint32), - ('lower_xyuv_external', ctypes.c_uint32), - ('lower_yuv_external', ctypes.c_uint32), - ('lower_yu_yv_external', ctypes.c_uint32), - ('lower_yv_yu_external', ctypes.c_uint32), - ('lower_y41x_external', ctypes.c_uint32), - ('lower_sx10_external', ctypes.c_uint32), - ('lower_sx12_external', ctypes.c_uint32), - ('bt709_external', ctypes.c_uint32), - ('bt2020_external', ctypes.c_uint32), - ('yuv_full_range_external', ctypes.c_uint32), - ('saturate_s', ctypes.c_uint32), - ('saturate_t', ctypes.c_uint32), - ('saturate_r', ctypes.c_uint32), - ('swizzle_result', ctypes.c_uint32), - ('swizzles', ctypes.c_ubyte * 4 * 32), - ('scale_factors', ctypes.c_float * 32), - ('lower_srgb', ctypes.c_uint32), - ('lower_txd_cube_map', ctypes.c_bool), - ('lower_txd_3d', ctypes.c_bool), - ('lower_txd_array', ctypes.c_bool), - ('lower_txd_shadow', ctypes.c_bool), - ('lower_txd', ctypes.c_bool), - ('lower_txd_clamp', ctypes.c_bool), - ('lower_txb_shadow_clamp', ctypes.c_bool), - ('lower_txd_shadow_clamp', ctypes.c_bool), - ('lower_txd_offset_clamp', ctypes.c_bool), - ('lower_txd_clamp_bindless_sampler', ctypes.c_bool), - ('lower_txd_clamp_if_sampler_index_not_lt_16', ctypes.c_bool), - ('lower_txs_lod', ctypes.c_bool), - ('lower_txs_cube_array', ctypes.c_bool), - ('lower_tg4_broadcom_swizzle', ctypes.c_bool), - ('lower_tg4_offsets', ctypes.c_bool), - ('lower_to_fragment_fetch_amd', ctypes.c_bool), - ('lower_tex_packing_cb', ctypes.CFUNCTYPE(nir_lower_tex_packing, ctypes.POINTER(struct_nir_tex_instr), ctypes.POINTER(None))), - ('lower_tex_packing_data', ctypes.POINTER(None)), - ('lower_lod_zero_width', ctypes.c_bool), - ('lower_sampler_lod_bias', ctypes.c_bool), - ('lower_invalid_implicit_lod', ctypes.c_bool), - ('lower_index_to_offset', ctypes.c_bool), - ('PADDING_2', ctypes.c_ubyte * 4), - ('callback_data', ctypes.POINTER(None)), -] - -nir_lower_tex_options = struct_nir_lower_tex_options -try: - nir_lower_tex = _libraries['libtinymesa_cpu.so'].nir_lower_tex - nir_lower_tex.restype = ctypes.c_bool - nir_lower_tex.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_tex_options)] -except AttributeError: - pass -class struct_nir_lower_tex_shadow_swizzle(Structure): - pass - -struct_nir_lower_tex_shadow_swizzle._pack_ = 1 # source:False -struct_nir_lower_tex_shadow_swizzle._fields_ = [ - ('swizzle_r', ctypes.c_uint32, 3), - ('swizzle_g', ctypes.c_uint32, 3), - ('swizzle_b', ctypes.c_uint32, 3), - ('swizzle_a', ctypes.c_uint32, 3), - ('PADDING_0', ctypes.c_uint32, 20), -] - -nir_lower_tex_shadow_swizzle = struct_nir_lower_tex_shadow_swizzle -try: - nir_lower_tex_shadow = _libraries['libtinymesa_cpu.so'].nir_lower_tex_shadow - nir_lower_tex_shadow.restype = ctypes.c_bool - nir_lower_tex_shadow.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.POINTER(compare_func), ctypes.POINTER(struct_nir_lower_tex_shadow_swizzle), ctypes.c_bool] -except AttributeError: - pass -class struct_nir_lower_image_options(Structure): - pass - -struct_nir_lower_image_options._pack_ = 1 # source:False -struct_nir_lower_image_options._fields_ = [ - ('lower_cube_size', ctypes.c_bool), - ('lower_to_fragment_mask_load_amd', ctypes.c_bool), - ('lower_image_samples_to_one', ctypes.c_bool), -] - -nir_lower_image_options = struct_nir_lower_image_options -try: - nir_lower_image = _libraries['libtinymesa_cpu.so'].nir_lower_image - nir_lower_image.restype = ctypes.c_bool - nir_lower_image.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_image_options)] -except AttributeError: - pass -try: - nir_lower_image_atomics_to_global = _libraries['libtinymesa_cpu.so'].nir_lower_image_atomics_to_global - nir_lower_image_atomics_to_global.restype = ctypes.c_bool - nir_lower_image_atomics_to_global.argtypes = [ctypes.POINTER(struct_nir_shader), nir_intrin_filter_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_readonly_images_to_tex = _libraries['libtinymesa_cpu.so'].nir_lower_readonly_images_to_tex - nir_lower_readonly_images_to_tex.restype = ctypes.c_bool - nir_lower_readonly_images_to_tex.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass - -# values for enumeration 'nir_lower_non_uniform_access_type' -nir_lower_non_uniform_access_type__enumvalues = { - 1: 'nir_lower_non_uniform_ubo_access', - 2: 'nir_lower_non_uniform_ssbo_access', - 4: 'nir_lower_non_uniform_texture_access', - 8: 'nir_lower_non_uniform_image_access', - 16: 'nir_lower_non_uniform_get_ssbo_size', - 32: 'nir_lower_non_uniform_texture_offset_access', - 6: 'nir_lower_non_uniform_access_type_count', -} -nir_lower_non_uniform_ubo_access = 1 -nir_lower_non_uniform_ssbo_access = 2 -nir_lower_non_uniform_texture_access = 4 -nir_lower_non_uniform_image_access = 8 -nir_lower_non_uniform_get_ssbo_size = 16 -nir_lower_non_uniform_texture_offset_access = 32 -nir_lower_non_uniform_access_type_count = 6 -nir_lower_non_uniform_access_type = ctypes.c_uint32 # enum -nir_lower_non_uniform_src_access_callback = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_tex_instr), ctypes.c_uint32, ctypes.POINTER(None)) -nir_lower_non_uniform_access_callback = ctypes.CFUNCTYPE(ctypes.c_uint16, ctypes.POINTER(struct_nir_src), ctypes.POINTER(None)) -class struct_nir_lower_non_uniform_access_options(Structure): - pass - -struct_nir_lower_non_uniform_access_options._pack_ = 1 # source:False -struct_nir_lower_non_uniform_access_options._fields_ = [ - ('types', nir_lower_non_uniform_access_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('tex_src_callback', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_tex_instr), ctypes.c_uint32, ctypes.POINTER(None))), - ('callback', ctypes.CFUNCTYPE(ctypes.c_uint16, ctypes.POINTER(struct_nir_src), ctypes.POINTER(None))), - ('callback_data', ctypes.POINTER(None)), -] - -nir_lower_non_uniform_access_options = struct_nir_lower_non_uniform_access_options -try: - nir_has_non_uniform_access = _libraries['libtinymesa_cpu.so'].nir_has_non_uniform_access - nir_has_non_uniform_access.restype = ctypes.c_bool - nir_has_non_uniform_access.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_non_uniform_access_type] -except AttributeError: - pass -try: - nir_opt_non_uniform_access = _libraries['libtinymesa_cpu.so'].nir_opt_non_uniform_access - nir_opt_non_uniform_access.restype = ctypes.c_bool - nir_opt_non_uniform_access.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_non_uniform_access = _libraries['libtinymesa_cpu.so'].nir_lower_non_uniform_access - nir_lower_non_uniform_access.restype = ctypes.c_bool - nir_lower_non_uniform_access.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_non_uniform_access_options)] -except AttributeError: - pass -class struct_nir_lower_idiv_options(Structure): - pass - -struct_nir_lower_idiv_options._pack_ = 1 # source:False -struct_nir_lower_idiv_options._fields_ = [ - ('allow_fp16', ctypes.c_bool), -] - -nir_lower_idiv_options = struct_nir_lower_idiv_options -try: - nir_lower_idiv = _libraries['libtinymesa_cpu.so'].nir_lower_idiv - nir_lower_idiv.restype = ctypes.c_bool - nir_lower_idiv.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_idiv_options)] -except AttributeError: - pass -class struct_nir_input_attachment_options(Structure): - pass - -struct_nir_input_attachment_options._pack_ = 1 # source:False -struct_nir_input_attachment_options._fields_ = [ - ('use_ia_coord_intrin', ctypes.c_bool), - ('use_fragcoord_sysval', ctypes.c_bool), - ('use_layer_id_sysval', ctypes.c_bool), - ('use_view_id_for_layer', ctypes.c_bool), - ('unscaled_depth_stencil_ir3', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), - ('unscaled_input_attachment_ir3', ctypes.c_uint32), -] - -nir_input_attachment_options = struct_nir_input_attachment_options -try: - nir_lower_input_attachments = _libraries['libtinymesa_cpu.so'].nir_lower_input_attachments - nir_lower_input_attachments.restype = ctypes.c_bool - nir_lower_input_attachments.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_input_attachment_options)] -except AttributeError: - pass -try: - nir_lower_clip_vs = _libraries['libtinymesa_cpu.so'].nir_lower_clip_vs - nir_lower_clip_vs.restype = ctypes.c_bool - nir_lower_clip_vs.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool, ctypes.c_int16 * 4 * 0] -except AttributeError: - pass -try: - nir_lower_clip_gs = _libraries['libtinymesa_cpu.so'].nir_lower_clip_gs - nir_lower_clip_gs.restype = ctypes.c_bool - nir_lower_clip_gs.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_int16 * 4 * 0] -except AttributeError: - pass -try: - nir_lower_clip_fs = _libraries['libtinymesa_cpu.so'].nir_lower_clip_fs - nir_lower_clip_fs.restype = ctypes.c_bool - nir_lower_clip_fs.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_clip_cull_distance_to_vec4s = _libraries['libtinymesa_cpu.so'].nir_lower_clip_cull_distance_to_vec4s - nir_lower_clip_cull_distance_to_vec4s.restype = ctypes.c_bool - nir_lower_clip_cull_distance_to_vec4s.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_clip_cull_distance_array_vars = _libraries['libtinymesa_cpu.so'].nir_lower_clip_cull_distance_array_vars - nir_lower_clip_cull_distance_array_vars.restype = ctypes.c_bool - nir_lower_clip_cull_distance_array_vars.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_clip_disable = _libraries['libtinymesa_cpu.so'].nir_lower_clip_disable - nir_lower_clip_disable.restype = ctypes.c_bool - nir_lower_clip_disable.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_lower_point_size_mov = _libraries['libtinymesa_cpu.so'].nir_lower_point_size_mov - nir_lower_point_size_mov.restype = ctypes.c_bool - nir_lower_point_size_mov.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(ctypes.c_int16)] -except AttributeError: - pass -try: - nir_lower_frexp = _libraries['libtinymesa_cpu.so'].nir_lower_frexp - nir_lower_frexp.restype = ctypes.c_bool - nir_lower_frexp.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_two_sided_color = _libraries['libtinymesa_cpu.so'].nir_lower_two_sided_color - nir_lower_two_sided_color.restype = ctypes.c_bool - nir_lower_two_sided_color.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_clamp_color_outputs = _libraries['libtinymesa_cpu.so'].nir_lower_clamp_color_outputs - nir_lower_clamp_color_outputs.restype = ctypes.c_bool - nir_lower_clamp_color_outputs.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_flatshade = _libraries['libtinymesa_cpu.so'].nir_lower_flatshade - nir_lower_flatshade.restype = ctypes.c_bool - nir_lower_flatshade.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_passthrough_edgeflags = _libraries['libtinymesa_cpu.so'].nir_lower_passthrough_edgeflags - nir_lower_passthrough_edgeflags.restype = ctypes.c_bool - nir_lower_passthrough_edgeflags.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_patch_vertices = _libraries['libtinymesa_cpu.so'].nir_lower_patch_vertices - nir_lower_patch_vertices.restype = ctypes.c_bool - nir_lower_patch_vertices.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.POINTER(ctypes.c_int16)] -except AttributeError: - pass -class struct_nir_lower_wpos_ytransform_options(Structure): - pass - -struct_nir_lower_wpos_ytransform_options._pack_ = 1 # source:False -struct_nir_lower_wpos_ytransform_options._fields_ = [ - ('state_tokens', ctypes.c_int16 * 4), - ('fs_coord_origin_upper_left', ctypes.c_bool, 1), - ('fs_coord_origin_lower_left', ctypes.c_bool, 1), - ('fs_coord_pixel_center_integer', ctypes.c_bool, 1), - ('fs_coord_pixel_center_half_integer', ctypes.c_bool, 1), - ('PADDING_0', ctypes.c_uint16, 12), -] - -nir_lower_wpos_ytransform_options = struct_nir_lower_wpos_ytransform_options -try: - nir_lower_wpos_ytransform = _libraries['libtinymesa_cpu.so'].nir_lower_wpos_ytransform - nir_lower_wpos_ytransform.restype = ctypes.c_bool - nir_lower_wpos_ytransform.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_wpos_ytransform_options)] -except AttributeError: - pass -try: - nir_lower_wpos_center = _libraries['libtinymesa_cpu.so'].nir_lower_wpos_center - nir_lower_wpos_center.restype = ctypes.c_bool - nir_lower_wpos_center.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_pntc_ytransform = _libraries['libtinymesa_cpu.so'].nir_lower_pntc_ytransform - nir_lower_pntc_ytransform.restype = ctypes.c_bool - nir_lower_pntc_ytransform.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_int16 * 4 * 0] -except AttributeError: - pass -try: - nir_lower_wrmasks = _libraries['libtinymesa_cpu.so'].nir_lower_wrmasks - nir_lower_wrmasks.restype = ctypes.c_bool - nir_lower_wrmasks.argtypes = [ctypes.POINTER(struct_nir_shader), nir_instr_filter_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_fb_read = _libraries['libtinymesa_cpu.so'].nir_lower_fb_read - nir_lower_fb_read.restype = ctypes.c_bool - nir_lower_fb_read.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_nir_lower_drawpixels_options(Structure): - pass - -struct_nir_lower_drawpixels_options._pack_ = 1 # source:False -struct_nir_lower_drawpixels_options._fields_ = [ - ('texcoord_state_tokens', ctypes.c_int16 * 4), - ('scale_state_tokens', ctypes.c_int16 * 4), - ('bias_state_tokens', ctypes.c_int16 * 4), - ('drawpix_sampler', ctypes.c_uint32), - ('pixelmap_sampler', ctypes.c_uint32), - ('pixel_maps', ctypes.c_bool, 1), - ('scale_and_bias', ctypes.c_bool, 1), - ('PADDING_0', ctypes.c_uint32, 30), -] - -nir_lower_drawpixels_options = struct_nir_lower_drawpixels_options -try: - nir_lower_drawpixels = _libraries['libtinymesa_cpu.so'].nir_lower_drawpixels - nir_lower_drawpixels.restype = ctypes.c_bool - nir_lower_drawpixels.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_drawpixels_options)] -except AttributeError: - pass -class struct_nir_lower_bitmap_options(Structure): - pass - -struct_nir_lower_bitmap_options._pack_ = 1 # source:False -struct_nir_lower_bitmap_options._fields_ = [ - ('sampler', ctypes.c_uint32), - ('swizzle_xxxx', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -nir_lower_bitmap_options = struct_nir_lower_bitmap_options -try: - nir_lower_bitmap = _libraries['libtinymesa_cpu.so'].nir_lower_bitmap - nir_lower_bitmap.restype = ctypes.c_bool - nir_lower_bitmap.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_bitmap_options)] -except AttributeError: - pass -try: - nir_lower_atomics_to_ssbo = _libraries['libtinymesa_cpu.so'].nir_lower_atomics_to_ssbo - nir_lower_atomics_to_ssbo.restype = ctypes.c_bool - nir_lower_atomics_to_ssbo.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_lower_gs_intrinsics_flags' -c__EA_nir_lower_gs_intrinsics_flags__enumvalues = { - 1: 'nir_lower_gs_intrinsics_per_stream', - 2: 'nir_lower_gs_intrinsics_count_primitives', - 4: 'nir_lower_gs_intrinsics_count_vertices_per_primitive', - 8: 'nir_lower_gs_intrinsics_overwrite_incomplete', -} -nir_lower_gs_intrinsics_per_stream = 1 -nir_lower_gs_intrinsics_count_primitives = 2 -nir_lower_gs_intrinsics_count_vertices_per_primitive = 4 -nir_lower_gs_intrinsics_overwrite_incomplete = 8 -c__EA_nir_lower_gs_intrinsics_flags = ctypes.c_uint32 # enum -nir_lower_gs_intrinsics_flags = c__EA_nir_lower_gs_intrinsics_flags -nir_lower_gs_intrinsics_flags__enumvalues = c__EA_nir_lower_gs_intrinsics_flags__enumvalues -try: - nir_lower_gs_intrinsics = _libraries['libtinymesa_cpu.so'].nir_lower_gs_intrinsics - nir_lower_gs_intrinsics.restype = ctypes.c_bool - nir_lower_gs_intrinsics.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_gs_intrinsics_flags] -except AttributeError: - pass -try: - nir_lower_halt_to_return = _libraries['libtinymesa_cpu.so'].nir_lower_halt_to_return - nir_lower_halt_to_return.restype = ctypes.c_bool - nir_lower_halt_to_return.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_tess_coord_z = _libraries['libtinymesa_cpu.so'].nir_lower_tess_coord_z - nir_lower_tess_coord_z.restype = ctypes.c_bool - nir_lower_tess_coord_z.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -class struct_nir_lower_task_shader_options(Structure): - pass - -struct_nir_lower_task_shader_options._pack_ = 1 # source:False -struct_nir_lower_task_shader_options._fields_ = [ - ('payload_to_shared_for_atomics', ctypes.c_bool, 1), - ('payload_to_shared_for_small_types', ctypes.c_bool, 1), - ('PADDING_0', ctypes.c_uint32, 30), - ('payload_offset_in_bytes', ctypes.c_uint32), -] - -nir_lower_task_shader_options = struct_nir_lower_task_shader_options -try: - nir_lower_task_shader = _libraries['libtinymesa_cpu.so'].nir_lower_task_shader - nir_lower_task_shader.restype = ctypes.c_bool - nir_lower_task_shader.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_task_shader_options] -except AttributeError: - pass -nir_lower_bit_size_callback = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)) -try: - nir_lower_bit_size = _libraries['libtinymesa_cpu.so'].nir_lower_bit_size - nir_lower_bit_size.restype = ctypes.c_bool - nir_lower_bit_size.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_bit_size_callback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_lower_64bit_phis = _libraries['libtinymesa_cpu.so'].nir_lower_64bit_phis - nir_lower_64bit_phis.restype = ctypes.c_bool - nir_lower_64bit_phis.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_nir_split_conversions_options(Structure): - pass - -struct_nir_split_conversions_options._pack_ = 1 # source:False -struct_nir_split_conversions_options._fields_ = [ - ('callback', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('callback_data', ctypes.POINTER(None)), - ('has_convert_alu_types', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -nir_split_conversions_options = struct_nir_split_conversions_options -try: - nir_split_conversions = _libraries['libtinymesa_cpu.so'].nir_split_conversions - nir_split_conversions.restype = ctypes.c_bool - nir_split_conversions.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_split_conversions_options)] -except AttributeError: - pass -try: - nir_split_64bit_vec3_and_vec4 = _libraries['libtinymesa_cpu.so'].nir_split_64bit_vec3_and_vec4 - nir_split_64bit_vec3_and_vec4.restype = ctypes.c_bool - nir_split_64bit_vec3_and_vec4.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_int64_op_to_options_mask = _libraries['libtinymesa_cpu.so'].nir_lower_int64_op_to_options_mask - nir_lower_int64_op_to_options_mask.restype = nir_lower_int64_options - nir_lower_int64_op_to_options_mask.argtypes = [nir_op] -except AttributeError: - pass -try: - nir_lower_int64 = _libraries['libtinymesa_cpu.so'].nir_lower_int64 - nir_lower_int64.restype = ctypes.c_bool - nir_lower_int64.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_int64_float_conversions = _libraries['libtinymesa_cpu.so'].nir_lower_int64_float_conversions - nir_lower_int64_float_conversions.restype = ctypes.c_bool - nir_lower_int64_float_conversions.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_doubles_op_to_options_mask = _libraries['libtinymesa_cpu.so'].nir_lower_doubles_op_to_options_mask - nir_lower_doubles_op_to_options_mask.restype = nir_lower_doubles_options - nir_lower_doubles_op_to_options_mask.argtypes = [nir_op] -except AttributeError: - pass -try: - nir_lower_doubles = _libraries['libtinymesa_cpu.so'].nir_lower_doubles - nir_lower_doubles.restype = ctypes.c_bool - nir_lower_doubles.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_shader), nir_lower_doubles_options] -except AttributeError: - pass -try: - nir_lower_pack = _libraries['libtinymesa_cpu.so'].nir_lower_pack - nir_lower_pack.restype = ctypes.c_bool - nir_lower_pack.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_get_io_intrinsic = _libraries['libtinymesa_cpu.so'].nir_get_io_intrinsic - nir_get_io_intrinsic.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_get_io_intrinsic.argtypes = [ctypes.POINTER(struct_nir_instr), nir_variable_mode, ctypes.POINTER(c__EA_nir_variable_mode)] -except AttributeError: - pass -try: - nir_recompute_io_bases = _libraries['libtinymesa_cpu.so'].nir_recompute_io_bases - nir_recompute_io_bases.restype = ctypes.c_bool - nir_recompute_io_bases.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_mediump_vars = _libraries['libtinymesa_cpu.so'].nir_lower_mediump_vars - nir_lower_mediump_vars.restype = ctypes.c_bool - nir_lower_mediump_vars.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_lower_mediump_io = _libraries['libtinymesa_cpu.so'].nir_lower_mediump_io - nir_lower_mediump_io.restype = ctypes.c_bool - nir_lower_mediump_io.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, uint64_t, ctypes.c_bool] -except AttributeError: - pass -try: - nir_clear_mediump_io_flag = _libraries['libtinymesa_cpu.so'].nir_clear_mediump_io_flag - nir_clear_mediump_io_flag.restype = ctypes.c_bool - nir_clear_mediump_io_flag.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_nir_opt_tex_srcs_options(Structure): - pass - -struct_nir_opt_tex_srcs_options._pack_ = 1 # source:False -struct_nir_opt_tex_srcs_options._fields_ = [ - ('sampler_dims', ctypes.c_uint32), - ('src_types', ctypes.c_uint32), -] - -nir_opt_tex_srcs_options = struct_nir_opt_tex_srcs_options -class struct_nir_opt_16bit_tex_image_options(Structure): - pass - -struct_nir_opt_16bit_tex_image_options._pack_ = 1 # source:False -struct_nir_opt_16bit_tex_image_options._fields_ = [ - ('rounding_mode', nir_rounding_mode), - ('opt_tex_dest_types', nir_alu_type), - ('opt_image_dest_types', nir_alu_type), - ('integer_dest_saturates', ctypes.c_bool), - ('opt_image_store_data', ctypes.c_bool), - ('opt_image_srcs', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), - ('opt_srcs_options_count', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('opt_srcs_options', ctypes.POINTER(struct_nir_opt_tex_srcs_options)), -] - -nir_opt_16bit_tex_image_options = struct_nir_opt_16bit_tex_image_options -try: - nir_opt_16bit_tex_image = _libraries['libtinymesa_cpu.so'].nir_opt_16bit_tex_image - nir_opt_16bit_tex_image.restype = ctypes.c_bool - nir_opt_16bit_tex_image.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_opt_16bit_tex_image_options)] -except AttributeError: - pass -class struct_nir_tex_src_type_constraint(Structure): - pass - -struct_nir_tex_src_type_constraint._pack_ = 1 # source:False -struct_nir_tex_src_type_constraint._fields_ = [ - ('legalize_type', ctypes.c_bool), - ('bit_size', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('match_src', nir_tex_src_type), -] - -nir_tex_src_type_constraint = struct_nir_tex_src_type_constraint -nir_tex_src_type_constraints = struct_nir_tex_src_type_constraint * 23 -try: - nir_legalize_16bit_sampler_srcs = _libraries['libtinymesa_cpu.so'].nir_legalize_16bit_sampler_srcs - nir_legalize_16bit_sampler_srcs.restype = ctypes.c_bool - nir_legalize_16bit_sampler_srcs.argtypes = [ctypes.POINTER(struct_nir_shader), nir_tex_src_type_constraints] -except AttributeError: - pass -try: - nir_lower_point_size = _libraries['libtinymesa_cpu.so'].nir_lower_point_size - nir_lower_point_size.restype = ctypes.c_bool - nir_lower_point_size.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - nir_lower_default_point_size = _libraries['libtinymesa_cpu.so'].nir_lower_default_point_size - nir_lower_default_point_size.restype = ctypes.c_bool - nir_lower_default_point_size.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_texcoord_replace = _libraries['libtinymesa_cpu.so'].nir_lower_texcoord_replace - nir_lower_texcoord_replace.restype = ctypes.c_bool - nir_lower_texcoord_replace.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_texcoord_replace_late = _libraries['libtinymesa_cpu.so'].nir_lower_texcoord_replace_late - nir_lower_texcoord_replace_late.restype = ctypes.c_bool - nir_lower_texcoord_replace_late.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32, ctypes.c_bool] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_lower_interpolation_options' -c__EA_nir_lower_interpolation_options__enumvalues = { - 2: 'nir_lower_interpolation_at_sample', - 4: 'nir_lower_interpolation_at_offset', - 8: 'nir_lower_interpolation_centroid', - 16: 'nir_lower_interpolation_pixel', - 32: 'nir_lower_interpolation_sample', -} -nir_lower_interpolation_at_sample = 2 -nir_lower_interpolation_at_offset = 4 -nir_lower_interpolation_centroid = 8 -nir_lower_interpolation_pixel = 16 -nir_lower_interpolation_sample = 32 -c__EA_nir_lower_interpolation_options = ctypes.c_uint32 # enum -nir_lower_interpolation_options = c__EA_nir_lower_interpolation_options -nir_lower_interpolation_options__enumvalues = c__EA_nir_lower_interpolation_options__enumvalues -try: - nir_lower_interpolation = _libraries['libtinymesa_cpu.so'].nir_lower_interpolation - nir_lower_interpolation.restype = ctypes.c_bool - nir_lower_interpolation.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_interpolation_options] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_lower_discard_if_options' -c__EA_nir_lower_discard_if_options__enumvalues = { - 1: 'nir_lower_demote_if_to_cf', - 2: 'nir_lower_terminate_if_to_cf', - 4: 'nir_move_terminate_out_of_loops', -} -nir_lower_demote_if_to_cf = 1 -nir_lower_terminate_if_to_cf = 2 -nir_move_terminate_out_of_loops = 4 -c__EA_nir_lower_discard_if_options = ctypes.c_uint32 # enum -nir_lower_discard_if_options = c__EA_nir_lower_discard_if_options -nir_lower_discard_if_options__enumvalues = c__EA_nir_lower_discard_if_options__enumvalues -try: - nir_lower_discard_if = _libraries['libtinymesa_cpu.so'].nir_lower_discard_if - nir_lower_discard_if.restype = ctypes.c_bool - nir_lower_discard_if.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_discard_if_options] -except AttributeError: - pass -try: - nir_lower_terminate_to_demote = _libraries['libtinymesa_cpu.so'].nir_lower_terminate_to_demote - nir_lower_terminate_to_demote.restype = ctypes.c_bool - nir_lower_terminate_to_demote.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_memory_model = _libraries['libtinymesa_cpu.so'].nir_lower_memory_model - nir_lower_memory_model.restype = ctypes.c_bool - nir_lower_memory_model.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_goto_ifs = _libraries['libtinymesa_cpu.so'].nir_lower_goto_ifs - nir_lower_goto_ifs.restype = ctypes.c_bool - nir_lower_goto_ifs.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_continue_constructs = _libraries['libtinymesa_cpu.so'].nir_lower_continue_constructs - nir_lower_continue_constructs.restype = ctypes.c_bool - nir_lower_continue_constructs.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_nir_lower_multiview_options(Structure): - pass - -struct_nir_lower_multiview_options._pack_ = 1 # source:False -struct_nir_lower_multiview_options._fields_ = [ - ('view_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('allowed_per_view_outputs', ctypes.c_uint64), -] - -nir_lower_multiview_options = struct_nir_lower_multiview_options -try: - nir_shader_uses_view_index = _libraries['libtinymesa_cpu.so'].nir_shader_uses_view_index - nir_shader_uses_view_index.restype = ctypes.c_bool - nir_shader_uses_view_index.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_can_lower_multiview = _libraries['libtinymesa_cpu.so'].nir_can_lower_multiview - nir_can_lower_multiview.restype = ctypes.c_bool - nir_can_lower_multiview.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_multiview_options] -except AttributeError: - pass -try: - nir_lower_multiview = _libraries['libtinymesa_cpu.so'].nir_lower_multiview - nir_lower_multiview.restype = ctypes.c_bool - nir_lower_multiview.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_multiview_options] -except AttributeError: - pass -try: - nir_lower_view_index_to_device_index = _libraries['libtinymesa_cpu.so'].nir_lower_view_index_to_device_index - nir_lower_view_index_to_device_index.restype = ctypes.c_bool - nir_lower_view_index_to_device_index.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_lower_fp16_cast_options' -c__EA_nir_lower_fp16_cast_options__enumvalues = { - 1: 'nir_lower_fp16_rtz', - 2: 'nir_lower_fp16_rtne', - 4: 'nir_lower_fp16_ru', - 8: 'nir_lower_fp16_rd', - 15: 'nir_lower_fp16_all', - 16: 'nir_lower_fp16_split_fp64', -} -nir_lower_fp16_rtz = 1 -nir_lower_fp16_rtne = 2 -nir_lower_fp16_ru = 4 -nir_lower_fp16_rd = 8 -nir_lower_fp16_all = 15 -nir_lower_fp16_split_fp64 = 16 -c__EA_nir_lower_fp16_cast_options = ctypes.c_uint32 # enum -nir_lower_fp16_cast_options = c__EA_nir_lower_fp16_cast_options -nir_lower_fp16_cast_options__enumvalues = c__EA_nir_lower_fp16_cast_options__enumvalues -try: - nir_lower_fp16_casts = _libraries['libtinymesa_cpu.so'].nir_lower_fp16_casts - nir_lower_fp16_casts.restype = ctypes.c_bool - nir_lower_fp16_casts.argtypes = [ctypes.POINTER(struct_nir_shader), nir_lower_fp16_cast_options] -except AttributeError: - pass -try: - nir_normalize_cubemap_coords = _libraries['libtinymesa_cpu.so'].nir_normalize_cubemap_coords - nir_normalize_cubemap_coords.restype = ctypes.c_bool - nir_normalize_cubemap_coords.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_shader_supports_implicit_lod = _libraries['libtinymesa_cpu.so'].nir_shader_supports_implicit_lod - nir_shader_supports_implicit_lod.restype = ctypes.c_bool - nir_shader_supports_implicit_lod.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_live_defs_impl = _libraries['libtinymesa_cpu.so'].nir_live_defs_impl - nir_live_defs_impl.restype = None - nir_live_defs_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_get_live_defs = _libraries['libtinymesa_cpu.so'].nir_get_live_defs - nir_get_live_defs.restype = ctypes.POINTER(ctypes.c_uint32) - nir_get_live_defs.argtypes = [nir_cursor, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_loop_analyze_impl = _libraries['libtinymesa_cpu.so'].nir_loop_analyze_impl - nir_loop_analyze_impl.restype = None - nir_loop_analyze_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl), nir_variable_mode, ctypes.c_bool] -except AttributeError: - pass -try: - nir_defs_interfere = _libraries['libtinymesa_cpu.so'].nir_defs_interfere - nir_defs_interfere.restype = ctypes.c_bool - nir_defs_interfere.argtypes = [ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_repair_ssa_impl = _libraries['libtinymesa_cpu.so'].nir_repair_ssa_impl - nir_repair_ssa_impl.restype = ctypes.c_bool - nir_repair_ssa_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_repair_ssa = _libraries['libtinymesa_cpu.so'].nir_repair_ssa - nir_repair_ssa.restype = ctypes.c_bool - nir_repair_ssa.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_convert_loop_to_lcssa = _libraries['libtinymesa_cpu.so'].nir_convert_loop_to_lcssa - nir_convert_loop_to_lcssa.restype = None - nir_convert_loop_to_lcssa.argtypes = [ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_convert_to_lcssa = _libraries['libtinymesa_cpu.so'].nir_convert_to_lcssa - nir_convert_to_lcssa.restype = ctypes.c_bool - nir_convert_to_lcssa.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_divergence_analysis_impl = _libraries['libtinymesa_cpu.so'].nir_divergence_analysis_impl - nir_divergence_analysis_impl.restype = None - nir_divergence_analysis_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl), nir_divergence_options] -except AttributeError: - pass -try: - nir_divergence_analysis = _libraries['libtinymesa_cpu.so'].nir_divergence_analysis - nir_divergence_analysis.restype = None - nir_divergence_analysis.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_vertex_divergence_analysis = _libraries['libtinymesa_cpu.so'].nir_vertex_divergence_analysis - nir_vertex_divergence_analysis.restype = None - nir_vertex_divergence_analysis.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_has_divergent_loop = _libraries['libtinymesa_cpu.so'].nir_has_divergent_loop - nir_has_divergent_loop.restype = ctypes.c_bool - nir_has_divergent_loop.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_rewrite_uses_to_load_reg = _libraries['libtinymesa_cpu.so'].nir_rewrite_uses_to_load_reg - nir_rewrite_uses_to_load_reg.restype = None - nir_rewrite_uses_to_load_reg.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_convert_from_ssa = _libraries['libtinymesa_cpu.so'].nir_convert_from_ssa - nir_convert_from_ssa.restype = ctypes.c_bool - nir_convert_from_ssa.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_phis_to_regs_block = _libraries['libtinymesa_cpu.so'].nir_lower_phis_to_regs_block - nir_lower_phis_to_regs_block.restype = ctypes.c_bool - nir_lower_phis_to_regs_block.argtypes = [ctypes.POINTER(struct_nir_block), ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_ssa_defs_to_regs_block = _libraries['libtinymesa_cpu.so'].nir_lower_ssa_defs_to_regs_block - nir_lower_ssa_defs_to_regs_block.restype = ctypes.c_bool - nir_lower_ssa_defs_to_regs_block.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_rematerialize_deref_in_use_blocks = _libraries['libtinymesa_cpu.so'].nir_rematerialize_deref_in_use_blocks - nir_rematerialize_deref_in_use_blocks.restype = ctypes.c_bool - nir_rematerialize_deref_in_use_blocks.argtypes = [ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_rematerialize_derefs_in_use_blocks_impl = _libraries['libtinymesa_cpu.so'].nir_rematerialize_derefs_in_use_blocks_impl - nir_rematerialize_derefs_in_use_blocks_impl.restype = ctypes.c_bool - nir_rematerialize_derefs_in_use_blocks_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_lower_samplers = _libraries['libtinymesa_cpu.so'].nir_lower_samplers - nir_lower_samplers.restype = ctypes.c_bool - nir_lower_samplers.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_cl_images = _libraries['libtinymesa_cpu.so'].nir_lower_cl_images - nir_lower_cl_images.restype = ctypes.c_bool - nir_lower_cl_images.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -try: - nir_dedup_inline_samplers = _libraries['libtinymesa_cpu.so'].nir_dedup_inline_samplers - nir_dedup_inline_samplers.restype = ctypes.c_bool - nir_dedup_inline_samplers.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_nir_lower_ssbo_options(Structure): - pass - -struct_nir_lower_ssbo_options._pack_ = 1 # source:False -struct_nir_lower_ssbo_options._fields_ = [ - ('native_loads', ctypes.c_bool), - ('native_offset', ctypes.c_bool), -] - -nir_lower_ssbo_options = struct_nir_lower_ssbo_options -try: - nir_lower_ssbo = _libraries['libtinymesa_cpu.so'].nir_lower_ssbo - nir_lower_ssbo.restype = ctypes.c_bool - nir_lower_ssbo.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_ssbo_options)] -except AttributeError: - pass -try: - nir_lower_helper_writes = _libraries['libtinymesa_cpu.so'].nir_lower_helper_writes - nir_lower_helper_writes.restype = ctypes.c_bool - nir_lower_helper_writes.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -class struct_nir_lower_printf_options(Structure): - pass - -struct_nir_lower_printf_options._pack_ = 1 # source:False -struct_nir_lower_printf_options._fields_ = [ - ('max_buffer_size', ctypes.c_uint32), - ('ptr_bit_size', ctypes.c_uint32), - ('hash_format_strings', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -nir_lower_printf_options = struct_nir_lower_printf_options -try: - nir_lower_printf = _libraries['libtinymesa_cpu.so'].nir_lower_printf - nir_lower_printf.restype = ctypes.c_bool - nir_lower_printf.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_printf_options)] -except AttributeError: - pass -try: - nir_lower_printf_buffer = _libraries['libtinymesa_cpu.so'].nir_lower_printf_buffer - nir_lower_printf_buffer.restype = ctypes.c_bool - nir_lower_printf_buffer.argtypes = [ctypes.POINTER(struct_nir_shader), uint64_t, uint32_t] -except AttributeError: - pass -try: - nir_opt_comparison_pre_impl = _libraries['libtinymesa_cpu.so'].nir_opt_comparison_pre_impl - nir_opt_comparison_pre_impl.restype = ctypes.c_bool - nir_opt_comparison_pre_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_opt_comparison_pre = _libraries['libtinymesa_cpu.so'].nir_opt_comparison_pre - nir_opt_comparison_pre.restype = ctypes.c_bool - nir_opt_comparison_pre.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_nir_opt_access_options(Structure): - pass - -struct_nir_opt_access_options._pack_ = 1 # source:False -struct_nir_opt_access_options._fields_ = [ - ('is_vulkan', ctypes.c_bool), -] - -nir_opt_access_options = struct_nir_opt_access_options -try: - nir_opt_access = _libraries['libtinymesa_cpu.so'].nir_opt_access - nir_opt_access.restype = ctypes.c_bool - nir_opt_access.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_opt_access_options)] -except AttributeError: - pass -try: - nir_opt_algebraic = _libraries['libtinymesa_cpu.so'].nir_opt_algebraic - nir_opt_algebraic.restype = ctypes.c_bool - nir_opt_algebraic.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_algebraic_before_ffma = _libraries['libtinymesa_cpu.so'].nir_opt_algebraic_before_ffma - nir_opt_algebraic_before_ffma.restype = ctypes.c_bool - nir_opt_algebraic_before_ffma.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_algebraic_before_lower_int64 = _libraries['libtinymesa_cpu.so'].nir_opt_algebraic_before_lower_int64 - nir_opt_algebraic_before_lower_int64.restype = ctypes.c_bool - nir_opt_algebraic_before_lower_int64.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_algebraic_late = _libraries['libtinymesa_cpu.so'].nir_opt_algebraic_late - nir_opt_algebraic_late.restype = ctypes.c_bool - nir_opt_algebraic_late.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_algebraic_distribute_src_mods = _libraries['libtinymesa_cpu.so'].nir_opt_algebraic_distribute_src_mods - nir_opt_algebraic_distribute_src_mods.restype = ctypes.c_bool - nir_opt_algebraic_distribute_src_mods.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_algebraic_integer_promotion = _libraries['libtinymesa_cpu.so'].nir_opt_algebraic_integer_promotion - nir_opt_algebraic_integer_promotion.restype = ctypes.c_bool - nir_opt_algebraic_integer_promotion.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_reassociate_matrix_mul = _libraries['libtinymesa_cpu.so'].nir_opt_reassociate_matrix_mul - nir_opt_reassociate_matrix_mul.restype = ctypes.c_bool - nir_opt_reassociate_matrix_mul.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_constant_folding = _libraries['libtinymesa_cpu.so'].nir_opt_constant_folding - nir_opt_constant_folding.restype = ctypes.c_bool - nir_opt_constant_folding.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -nir_combine_barrier_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None)) -try: - nir_opt_combine_barriers = _libraries['libtinymesa_cpu.so'].nir_opt_combine_barriers - nir_opt_combine_barriers.restype = ctypes.c_bool - nir_opt_combine_barriers.argtypes = [ctypes.POINTER(struct_nir_shader), nir_combine_barrier_cb, ctypes.POINTER(None)] -except AttributeError: - pass - -# values for enumeration 'c__EA_mesa_scope' -c__EA_mesa_scope__enumvalues = { - 0: 'SCOPE_NONE', - 1: 'SCOPE_INVOCATION', - 2: 'SCOPE_SUBGROUP', - 3: 'SCOPE_SHADER_CALL', - 4: 'SCOPE_WORKGROUP', - 5: 'SCOPE_QUEUE_FAMILY', - 6: 'SCOPE_DEVICE', -} -SCOPE_NONE = 0 -SCOPE_INVOCATION = 1 -SCOPE_SUBGROUP = 2 -SCOPE_SHADER_CALL = 3 -SCOPE_WORKGROUP = 4 -SCOPE_QUEUE_FAMILY = 5 -SCOPE_DEVICE = 6 -c__EA_mesa_scope = ctypes.c_uint32 # enum -mesa_scope = c__EA_mesa_scope -mesa_scope__enumvalues = c__EA_mesa_scope__enumvalues -try: - nir_opt_acquire_release_barriers = _libraries['libtinymesa_cpu.so'].nir_opt_acquire_release_barriers - nir_opt_acquire_release_barriers.restype = ctypes.c_bool - nir_opt_acquire_release_barriers.argtypes = [ctypes.POINTER(struct_nir_shader), mesa_scope] -except AttributeError: - pass -try: - nir_opt_barrier_modes = _libraries['libtinymesa_cpu.so'].nir_opt_barrier_modes - nir_opt_barrier_modes.restype = ctypes.c_bool - nir_opt_barrier_modes.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_minimize_call_live_states = _libraries['libtinymesa_cpu.so'].nir_minimize_call_live_states - nir_minimize_call_live_states.restype = ctypes.c_bool - nir_minimize_call_live_states.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_combine_stores = _libraries['libtinymesa_cpu.so'].nir_opt_combine_stores - nir_opt_combine_stores.restype = ctypes.c_bool - nir_opt_combine_stores.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode] -except AttributeError: - pass -try: - nir_copy_prop_impl = _libraries['libtinymesa_cpu.so'].nir_copy_prop_impl - nir_copy_prop_impl.restype = ctypes.c_bool - nir_copy_prop_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_copy_prop = _libraries['libtinymesa_cpu.so'].nir_copy_prop - nir_copy_prop.restype = ctypes.c_bool - nir_copy_prop.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_copy_prop_vars = _libraries['libtinymesa_cpu.so'].nir_opt_copy_prop_vars - nir_opt_copy_prop_vars.restype = ctypes.c_bool - nir_opt_copy_prop_vars.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_cse = _libraries['libtinymesa_cpu.so'].nir_opt_cse - nir_opt_cse.restype = ctypes.c_bool - nir_opt_cse.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_dce = _libraries['libtinymesa_cpu.so'].nir_opt_dce - nir_opt_dce.restype = ctypes.c_bool - nir_opt_dce.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_dead_cf = _libraries['libtinymesa_cpu.so'].nir_opt_dead_cf - nir_opt_dead_cf.restype = ctypes.c_bool - nir_opt_dead_cf.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_dead_write_vars = _libraries['libtinymesa_cpu.so'].nir_opt_dead_write_vars - nir_opt_dead_write_vars.restype = ctypes.c_bool - nir_opt_dead_write_vars.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_deref_impl = _libraries['libtinymesa_cpu.so'].nir_opt_deref_impl - nir_opt_deref_impl.restype = ctypes.c_bool - nir_opt_deref_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_opt_deref = _libraries['libtinymesa_cpu.so'].nir_opt_deref - nir_opt_deref.restype = ctypes.c_bool - nir_opt_deref.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_find_array_copies = _libraries['libtinymesa_cpu.so'].nir_opt_find_array_copies - nir_opt_find_array_copies.restype = ctypes.c_bool - nir_opt_find_array_copies.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_def_is_frag_coord_z = _libraries['libtinymesa_cpu.so'].nir_def_is_frag_coord_z - nir_def_is_frag_coord_z.restype = ctypes.c_bool - nir_def_is_frag_coord_z.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_opt_fragdepth = _libraries['libtinymesa_cpu.so'].nir_opt_fragdepth - nir_opt_fragdepth.restype = ctypes.c_bool - nir_opt_fragdepth.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_gcm = _libraries['libtinymesa_cpu.so'].nir_opt_gcm - nir_opt_gcm.restype = ctypes.c_bool - nir_opt_gcm.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_opt_generate_bfi = _libraries['libtinymesa_cpu.so'].nir_opt_generate_bfi - nir_opt_generate_bfi.restype = ctypes.c_bool - nir_opt_generate_bfi.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_idiv_const = _libraries['libtinymesa_cpu.so'].nir_opt_idiv_const - nir_opt_idiv_const.restype = ctypes.c_bool - nir_opt_idiv_const.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_opt_mqsad = _libraries['libtinymesa_cpu.so'].nir_opt_mqsad - nir_opt_mqsad.restype = ctypes.c_bool - nir_opt_mqsad.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_opt_if_options' -c__EA_nir_opt_if_options__enumvalues = { - 1: 'nir_opt_if_optimize_phi_true_false', - 2: 'nir_opt_if_avoid_64bit_phis', -} -nir_opt_if_optimize_phi_true_false = 1 -nir_opt_if_avoid_64bit_phis = 2 -c__EA_nir_opt_if_options = ctypes.c_uint32 # enum -nir_opt_if_options = c__EA_nir_opt_if_options -nir_opt_if_options__enumvalues = c__EA_nir_opt_if_options__enumvalues -try: - nir_opt_if = _libraries['libtinymesa_cpu.so'].nir_opt_if - nir_opt_if.restype = ctypes.c_bool - nir_opt_if.argtypes = [ctypes.POINTER(struct_nir_shader), nir_opt_if_options] -except AttributeError: - pass -try: - nir_opt_intrinsics = _libraries['libtinymesa_cpu.so'].nir_opt_intrinsics - nir_opt_intrinsics.restype = ctypes.c_bool - nir_opt_intrinsics.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_large_constants = _libraries['libtinymesa_cpu.so'].nir_opt_large_constants - nir_opt_large_constants.restype = ctypes.c_bool - nir_opt_large_constants.argtypes = [ctypes.POINTER(struct_nir_shader), glsl_type_size_align_func, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_opt_licm = _libraries['libtinymesa_cpu.so'].nir_opt_licm - nir_opt_licm.restype = ctypes.c_bool - nir_opt_licm.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_loop = _libraries['libtinymesa_cpu.so'].nir_opt_loop - nir_opt_loop.restype = ctypes.c_bool - nir_opt_loop.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_loop_unroll = _libraries['libtinymesa_cpu.so'].nir_opt_loop_unroll - nir_opt_loop_unroll.restype = ctypes.c_bool - nir_opt_loop_unroll.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass - -# values for enumeration 'c__EA_nir_move_options' -c__EA_nir_move_options__enumvalues = { - 1: 'nir_move_const_undef', - 2: 'nir_move_load_ubo', - 4: 'nir_move_load_input', - 8: 'nir_move_comparisons', - 16: 'nir_move_copies', - 32: 'nir_move_load_ssbo', - 64: 'nir_move_load_uniform', - 128: 'nir_move_alu', - 256: 'nir_dont_move_byte_word_vecs', -} -nir_move_const_undef = 1 -nir_move_load_ubo = 2 -nir_move_load_input = 4 -nir_move_comparisons = 8 -nir_move_copies = 16 -nir_move_load_ssbo = 32 -nir_move_load_uniform = 64 -nir_move_alu = 128 -nir_dont_move_byte_word_vecs = 256 -c__EA_nir_move_options = ctypes.c_uint32 # enum -nir_move_options = c__EA_nir_move_options -nir_move_options__enumvalues = c__EA_nir_move_options__enumvalues -try: - nir_can_move_instr = _libraries['libtinymesa_cpu.so'].nir_can_move_instr - nir_can_move_instr.restype = ctypes.c_bool - nir_can_move_instr.argtypes = [ctypes.POINTER(struct_nir_instr), nir_move_options] -except AttributeError: - pass -try: - nir_opt_sink = _libraries['libtinymesa_cpu.so'].nir_opt_sink - nir_opt_sink.restype = ctypes.c_bool - nir_opt_sink.argtypes = [ctypes.POINTER(struct_nir_shader), nir_move_options] -except AttributeError: - pass -try: - nir_opt_move = _libraries['libtinymesa_cpu.so'].nir_opt_move - nir_opt_move.restype = ctypes.c_bool - nir_opt_move.argtypes = [ctypes.POINTER(struct_nir_shader), nir_move_options] -except AttributeError: - pass -class struct_nir_opt_offsets_options(Structure): - pass - -struct_nir_opt_offsets_options._pack_ = 1 # source:False -struct_nir_opt_offsets_options._fields_ = [ - ('uniform_max', ctypes.c_uint32), - ('ubo_vec4_max', ctypes.c_uint32), - ('shared_max', ctypes.c_uint32), - ('shared_atomic_max', ctypes.c_uint32), - ('buffer_max', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('max_offset_cb', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None))), - ('max_offset_data', ctypes.POINTER(None)), - ('allow_offset_wrap', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -nir_opt_offsets_options = struct_nir_opt_offsets_options -try: - nir_opt_offsets = _libraries['libtinymesa_cpu.so'].nir_opt_offsets - nir_opt_offsets.restype = ctypes.c_bool - nir_opt_offsets.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_opt_offsets_options)] -except AttributeError: - pass -class struct_nir_opt_peephole_select_options(Structure): - pass - -struct_nir_opt_peephole_select_options._pack_ = 1 # source:False -struct_nir_opt_peephole_select_options._fields_ = [ - ('limit', ctypes.c_uint32), - ('indirect_load_ok', ctypes.c_bool), - ('expensive_alu_ok', ctypes.c_bool), - ('discard_ok', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), -] - -nir_opt_peephole_select_options = struct_nir_opt_peephole_select_options -try: - nir_opt_peephole_select = _libraries['libtinymesa_cpu.so'].nir_opt_peephole_select - nir_opt_peephole_select.restype = ctypes.c_bool - nir_opt_peephole_select.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_opt_peephole_select_options)] -except AttributeError: - pass -try: - nir_opt_reassociate_bfi = _libraries['libtinymesa_cpu.so'].nir_opt_reassociate_bfi - nir_opt_reassociate_bfi.restype = ctypes.c_bool - nir_opt_reassociate_bfi.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_rematerialize_compares = _libraries['libtinymesa_cpu.so'].nir_opt_rematerialize_compares - nir_opt_rematerialize_compares.restype = ctypes.c_bool - nir_opt_rematerialize_compares.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_remove_phis = _libraries['libtinymesa_cpu.so'].nir_opt_remove_phis - nir_opt_remove_phis.restype = ctypes.c_bool - nir_opt_remove_phis.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_remove_single_src_phis_block = _libraries['libtinymesa_cpu.so'].nir_remove_single_src_phis_block - nir_remove_single_src_phis_block.restype = ctypes.c_bool - nir_remove_single_src_phis_block.argtypes = [ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_opt_phi_precision = _libraries['libtinymesa_cpu.so'].nir_opt_phi_precision - nir_opt_phi_precision.restype = ctypes.c_bool - nir_opt_phi_precision.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_phi_to_bool = _libraries['libtinymesa_cpu.so'].nir_opt_phi_to_bool - nir_opt_phi_to_bool.restype = ctypes.c_bool - nir_opt_phi_to_bool.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_shrink_stores = _libraries['libtinymesa_cpu.so'].nir_opt_shrink_stores - nir_opt_shrink_stores.restype = ctypes.c_bool - nir_opt_shrink_stores.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_opt_shrink_vectors = _libraries['libtinymesa_cpu.so'].nir_opt_shrink_vectors - nir_opt_shrink_vectors.restype = ctypes.c_bool - nir_opt_shrink_vectors.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_opt_undef = _libraries['libtinymesa_cpu.so'].nir_opt_undef - nir_opt_undef.restype = ctypes.c_bool - nir_opt_undef.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_undef_to_zero = _libraries['libtinymesa_cpu.so'].nir_lower_undef_to_zero - nir_lower_undef_to_zero.restype = ctypes.c_bool - nir_lower_undef_to_zero.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_uniform_atomics = _libraries['libtinymesa_cpu.so'].nir_opt_uniform_atomics - nir_opt_uniform_atomics.restype = ctypes.c_bool - nir_opt_uniform_atomics.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_opt_uniform_subgroup = _libraries['libtinymesa_cpu.so'].nir_opt_uniform_subgroup - nir_opt_uniform_subgroup.restype = ctypes.c_bool - nir_opt_uniform_subgroup.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_lower_subgroups_options)] -except AttributeError: - pass -try: - nir_opt_vectorize = _libraries['libtinymesa_cpu.so'].nir_opt_vectorize - nir_opt_vectorize.restype = ctypes.c_bool - nir_opt_vectorize.argtypes = [ctypes.POINTER(struct_nir_shader), nir_vectorize_cb, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_opt_vectorize_io = _libraries['libtinymesa_cpu.so'].nir_opt_vectorize_io - nir_opt_vectorize_io.restype = ctypes.c_bool - nir_opt_vectorize_io.argtypes = [ctypes.POINTER(struct_nir_shader), nir_variable_mode, ctypes.c_bool] -except AttributeError: - pass -try: - nir_opt_move_discards_to_top = _libraries['libtinymesa_cpu.so'].nir_opt_move_discards_to_top - nir_opt_move_discards_to_top.restype = ctypes.c_bool - nir_opt_move_discards_to_top.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_ray_queries = _libraries['libtinymesa_cpu.so'].nir_opt_ray_queries - nir_opt_ray_queries.restype = ctypes.c_bool - nir_opt_ray_queries.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_ray_query_ranges = _libraries['libtinymesa_cpu.so'].nir_opt_ray_query_ranges - nir_opt_ray_query_ranges.restype = ctypes.c_bool - nir_opt_ray_query_ranges.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_opt_tex_skip_helpers = _libraries['libtinymesa_cpu.so'].nir_opt_tex_skip_helpers - nir_opt_tex_skip_helpers.restype = ctypes.c_bool - nir_opt_tex_skip_helpers.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_sweep = _libraries['libtinymesa_cpu.so'].nir_sweep - nir_sweep.restype = None - nir_sweep.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass - -# values for enumeration 'c__EA_gl_system_value' -c__EA_gl_system_value__enumvalues = { - 0: 'SYSTEM_VALUE_SUBGROUP_SIZE', - 1: 'SYSTEM_VALUE_SUBGROUP_INVOCATION', - 2: 'SYSTEM_VALUE_SUBGROUP_EQ_MASK', - 3: 'SYSTEM_VALUE_SUBGROUP_GE_MASK', - 4: 'SYSTEM_VALUE_SUBGROUP_GT_MASK', - 5: 'SYSTEM_VALUE_SUBGROUP_LE_MASK', - 6: 'SYSTEM_VALUE_SUBGROUP_LT_MASK', - 7: 'SYSTEM_VALUE_NUM_SUBGROUPS', - 8: 'SYSTEM_VALUE_SUBGROUP_ID', - 9: 'SYSTEM_VALUE_VERTEX_ID', - 10: 'SYSTEM_VALUE_INSTANCE_ID', - 11: 'SYSTEM_VALUE_INSTANCE_INDEX', - 12: 'SYSTEM_VALUE_VERTEX_ID_ZERO_BASE', - 13: 'SYSTEM_VALUE_BASE_VERTEX', - 14: 'SYSTEM_VALUE_FIRST_VERTEX', - 15: 'SYSTEM_VALUE_IS_INDEXED_DRAW', - 16: 'SYSTEM_VALUE_BASE_INSTANCE', - 17: 'SYSTEM_VALUE_DRAW_ID', - 18: 'SYSTEM_VALUE_INVOCATION_ID', - 19: 'SYSTEM_VALUE_FRAG_COORD', - 20: 'SYSTEM_VALUE_PIXEL_COORD', - 21: 'SYSTEM_VALUE_FRAG_COORD_Z', - 22: 'SYSTEM_VALUE_FRAG_COORD_W', - 23: 'SYSTEM_VALUE_POINT_COORD', - 24: 'SYSTEM_VALUE_LINE_COORD', - 25: 'SYSTEM_VALUE_FRONT_FACE', - 26: 'SYSTEM_VALUE_FRONT_FACE_FSIGN', - 27: 'SYSTEM_VALUE_SAMPLE_ID', - 28: 'SYSTEM_VALUE_SAMPLE_POS', - 29: 'SYSTEM_VALUE_SAMPLE_POS_OR_CENTER', - 30: 'SYSTEM_VALUE_SAMPLE_MASK_IN', - 31: 'SYSTEM_VALUE_LAYER_ID', - 32: 'SYSTEM_VALUE_HELPER_INVOCATION', - 33: 'SYSTEM_VALUE_COLOR0', - 34: 'SYSTEM_VALUE_COLOR1', - 35: 'SYSTEM_VALUE_TESS_COORD', - 36: 'SYSTEM_VALUE_VERTICES_IN', - 37: 'SYSTEM_VALUE_PRIMITIVE_ID', - 38: 'SYSTEM_VALUE_TESS_LEVEL_OUTER', - 39: 'SYSTEM_VALUE_TESS_LEVEL_INNER', - 40: 'SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT', - 41: 'SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT', - 42: 'SYSTEM_VALUE_LOCAL_INVOCATION_ID', - 43: 'SYSTEM_VALUE_LOCAL_INVOCATION_INDEX', - 44: 'SYSTEM_VALUE_GLOBAL_INVOCATION_ID', - 45: 'SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID', - 46: 'SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX', - 47: 'SYSTEM_VALUE_WORKGROUP_ID', - 48: 'SYSTEM_VALUE_BASE_WORKGROUP_ID', - 49: 'SYSTEM_VALUE_WORKGROUP_INDEX', - 50: 'SYSTEM_VALUE_NUM_WORKGROUPS', - 51: 'SYSTEM_VALUE_WORKGROUP_SIZE', - 52: 'SYSTEM_VALUE_GLOBAL_GROUP_SIZE', - 53: 'SYSTEM_VALUE_WORK_DIM', - 54: 'SYSTEM_VALUE_USER_DATA_AMD', - 55: 'SYSTEM_VALUE_DEVICE_INDEX', - 56: 'SYSTEM_VALUE_VIEW_INDEX', - 57: 'SYSTEM_VALUE_VERTEX_CNT', - 58: 'SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL', - 59: 'SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE', - 60: 'SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID', - 61: 'SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTER_RHW', - 62: 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL', - 63: 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID', - 64: 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE', - 65: 'SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL', - 66: 'SYSTEM_VALUE_BARYCENTRIC_PERSP_COORD', - 67: 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_COORD', - 68: 'SYSTEM_VALUE_RAY_LAUNCH_ID', - 69: 'SYSTEM_VALUE_RAY_LAUNCH_SIZE', - 70: 'SYSTEM_VALUE_RAY_WORLD_ORIGIN', - 71: 'SYSTEM_VALUE_RAY_WORLD_DIRECTION', - 72: 'SYSTEM_VALUE_RAY_OBJECT_ORIGIN', - 73: 'SYSTEM_VALUE_RAY_OBJECT_DIRECTION', - 74: 'SYSTEM_VALUE_RAY_T_MIN', - 75: 'SYSTEM_VALUE_RAY_T_MAX', - 76: 'SYSTEM_VALUE_RAY_OBJECT_TO_WORLD', - 77: 'SYSTEM_VALUE_RAY_WORLD_TO_OBJECT', - 78: 'SYSTEM_VALUE_RAY_HIT_KIND', - 79: 'SYSTEM_VALUE_RAY_FLAGS', - 80: 'SYSTEM_VALUE_RAY_GEOMETRY_INDEX', - 81: 'SYSTEM_VALUE_RAY_INSTANCE_CUSTOM_INDEX', - 82: 'SYSTEM_VALUE_CULL_MASK', - 83: 'SYSTEM_VALUE_RAY_TRIANGLE_VERTEX_POSITIONS', - 84: 'SYSTEM_VALUE_MESH_VIEW_COUNT', - 85: 'SYSTEM_VALUE_MESH_VIEW_INDICES', - 86: 'SYSTEM_VALUE_GS_HEADER_IR3', - 87: 'SYSTEM_VALUE_TCS_HEADER_IR3', - 88: 'SYSTEM_VALUE_REL_PATCH_ID_IR3', - 89: 'SYSTEM_VALUE_FRAG_SHADING_RATE', - 90: 'SYSTEM_VALUE_FULLY_COVERED', - 91: 'SYSTEM_VALUE_FRAG_SIZE', - 92: 'SYSTEM_VALUE_FRAG_INVOCATION_COUNT', - 93: 'SYSTEM_VALUE_SHADER_INDEX', - 94: 'SYSTEM_VALUE_COALESCED_INPUT_COUNT', - 95: 'SYSTEM_VALUE_WARPS_PER_SM_NV', - 96: 'SYSTEM_VALUE_SM_COUNT_NV', - 97: 'SYSTEM_VALUE_WARP_ID_NV', - 98: 'SYSTEM_VALUE_SM_ID_NV', - 99: 'SYSTEM_VALUE_MAX', -} -SYSTEM_VALUE_SUBGROUP_SIZE = 0 -SYSTEM_VALUE_SUBGROUP_INVOCATION = 1 -SYSTEM_VALUE_SUBGROUP_EQ_MASK = 2 -SYSTEM_VALUE_SUBGROUP_GE_MASK = 3 -SYSTEM_VALUE_SUBGROUP_GT_MASK = 4 -SYSTEM_VALUE_SUBGROUP_LE_MASK = 5 -SYSTEM_VALUE_SUBGROUP_LT_MASK = 6 -SYSTEM_VALUE_NUM_SUBGROUPS = 7 -SYSTEM_VALUE_SUBGROUP_ID = 8 -SYSTEM_VALUE_VERTEX_ID = 9 -SYSTEM_VALUE_INSTANCE_ID = 10 -SYSTEM_VALUE_INSTANCE_INDEX = 11 -SYSTEM_VALUE_VERTEX_ID_ZERO_BASE = 12 -SYSTEM_VALUE_BASE_VERTEX = 13 -SYSTEM_VALUE_FIRST_VERTEX = 14 -SYSTEM_VALUE_IS_INDEXED_DRAW = 15 -SYSTEM_VALUE_BASE_INSTANCE = 16 -SYSTEM_VALUE_DRAW_ID = 17 -SYSTEM_VALUE_INVOCATION_ID = 18 -SYSTEM_VALUE_FRAG_COORD = 19 -SYSTEM_VALUE_PIXEL_COORD = 20 -SYSTEM_VALUE_FRAG_COORD_Z = 21 -SYSTEM_VALUE_FRAG_COORD_W = 22 -SYSTEM_VALUE_POINT_COORD = 23 -SYSTEM_VALUE_LINE_COORD = 24 -SYSTEM_VALUE_FRONT_FACE = 25 -SYSTEM_VALUE_FRONT_FACE_FSIGN = 26 -SYSTEM_VALUE_SAMPLE_ID = 27 -SYSTEM_VALUE_SAMPLE_POS = 28 -SYSTEM_VALUE_SAMPLE_POS_OR_CENTER = 29 -SYSTEM_VALUE_SAMPLE_MASK_IN = 30 -SYSTEM_VALUE_LAYER_ID = 31 -SYSTEM_VALUE_HELPER_INVOCATION = 32 -SYSTEM_VALUE_COLOR0 = 33 -SYSTEM_VALUE_COLOR1 = 34 -SYSTEM_VALUE_TESS_COORD = 35 -SYSTEM_VALUE_VERTICES_IN = 36 -SYSTEM_VALUE_PRIMITIVE_ID = 37 -SYSTEM_VALUE_TESS_LEVEL_OUTER = 38 -SYSTEM_VALUE_TESS_LEVEL_INNER = 39 -SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT = 40 -SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT = 41 -SYSTEM_VALUE_LOCAL_INVOCATION_ID = 42 -SYSTEM_VALUE_LOCAL_INVOCATION_INDEX = 43 -SYSTEM_VALUE_GLOBAL_INVOCATION_ID = 44 -SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID = 45 -SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX = 46 -SYSTEM_VALUE_WORKGROUP_ID = 47 -SYSTEM_VALUE_BASE_WORKGROUP_ID = 48 -SYSTEM_VALUE_WORKGROUP_INDEX = 49 -SYSTEM_VALUE_NUM_WORKGROUPS = 50 -SYSTEM_VALUE_WORKGROUP_SIZE = 51 -SYSTEM_VALUE_GLOBAL_GROUP_SIZE = 52 -SYSTEM_VALUE_WORK_DIM = 53 -SYSTEM_VALUE_USER_DATA_AMD = 54 -SYSTEM_VALUE_DEVICE_INDEX = 55 -SYSTEM_VALUE_VIEW_INDEX = 56 -SYSTEM_VALUE_VERTEX_CNT = 57 -SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL = 58 -SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE = 59 -SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID = 60 -SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTER_RHW = 61 -SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL = 62 -SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID = 63 -SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE = 64 -SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL = 65 -SYSTEM_VALUE_BARYCENTRIC_PERSP_COORD = 66 -SYSTEM_VALUE_BARYCENTRIC_LINEAR_COORD = 67 -SYSTEM_VALUE_RAY_LAUNCH_ID = 68 -SYSTEM_VALUE_RAY_LAUNCH_SIZE = 69 -SYSTEM_VALUE_RAY_WORLD_ORIGIN = 70 -SYSTEM_VALUE_RAY_WORLD_DIRECTION = 71 -SYSTEM_VALUE_RAY_OBJECT_ORIGIN = 72 -SYSTEM_VALUE_RAY_OBJECT_DIRECTION = 73 -SYSTEM_VALUE_RAY_T_MIN = 74 -SYSTEM_VALUE_RAY_T_MAX = 75 -SYSTEM_VALUE_RAY_OBJECT_TO_WORLD = 76 -SYSTEM_VALUE_RAY_WORLD_TO_OBJECT = 77 -SYSTEM_VALUE_RAY_HIT_KIND = 78 -SYSTEM_VALUE_RAY_FLAGS = 79 -SYSTEM_VALUE_RAY_GEOMETRY_INDEX = 80 -SYSTEM_VALUE_RAY_INSTANCE_CUSTOM_INDEX = 81 -SYSTEM_VALUE_CULL_MASK = 82 -SYSTEM_VALUE_RAY_TRIANGLE_VERTEX_POSITIONS = 83 -SYSTEM_VALUE_MESH_VIEW_COUNT = 84 -SYSTEM_VALUE_MESH_VIEW_INDICES = 85 -SYSTEM_VALUE_GS_HEADER_IR3 = 86 -SYSTEM_VALUE_TCS_HEADER_IR3 = 87 -SYSTEM_VALUE_REL_PATCH_ID_IR3 = 88 -SYSTEM_VALUE_FRAG_SHADING_RATE = 89 -SYSTEM_VALUE_FULLY_COVERED = 90 -SYSTEM_VALUE_FRAG_SIZE = 91 -SYSTEM_VALUE_FRAG_INVOCATION_COUNT = 92 -SYSTEM_VALUE_SHADER_INDEX = 93 -SYSTEM_VALUE_COALESCED_INPUT_COUNT = 94 -SYSTEM_VALUE_WARPS_PER_SM_NV = 95 -SYSTEM_VALUE_SM_COUNT_NV = 96 -SYSTEM_VALUE_WARP_ID_NV = 97 -SYSTEM_VALUE_SM_ID_NV = 98 -SYSTEM_VALUE_MAX = 99 -c__EA_gl_system_value = ctypes.c_uint32 # enum -gl_system_value = c__EA_gl_system_value -gl_system_value__enumvalues = c__EA_gl_system_value__enumvalues -try: - nir_intrinsic_from_system_value = _libraries['libtinymesa_cpu.so'].nir_intrinsic_from_system_value - nir_intrinsic_from_system_value.restype = nir_intrinsic_op - nir_intrinsic_from_system_value.argtypes = [gl_system_value] -except AttributeError: - pass -try: - nir_system_value_from_intrinsic = _libraries['libtinymesa_cpu.so'].nir_system_value_from_intrinsic - nir_system_value_from_intrinsic.restype = gl_system_value - nir_system_value_from_intrinsic.argtypes = [nir_intrinsic_op] -except AttributeError: - pass -try: - nir_variable_is_in_ubo = _libraries['FIXME_STUB'].nir_variable_is_in_ubo - nir_variable_is_in_ubo.restype = ctypes.c_bool - nir_variable_is_in_ubo.argtypes = [ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_variable_is_in_ssbo = _libraries['FIXME_STUB'].nir_variable_is_in_ssbo - nir_variable_is_in_ssbo.restype = ctypes.c_bool - nir_variable_is_in_ssbo.argtypes = [ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_variable_is_in_block = _libraries['FIXME_STUB'].nir_variable_is_in_block - nir_variable_is_in_block.restype = ctypes.c_bool - nir_variable_is_in_block.argtypes = [ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_variable_count_slots = _libraries['FIXME_STUB'].nir_variable_count_slots - nir_variable_count_slots.restype = ctypes.c_uint32 - nir_variable_count_slots.argtypes = [ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - nir_deref_count_slots = _libraries['FIXME_STUB'].nir_deref_count_slots - nir_deref_count_slots.restype = ctypes.c_uint32 - nir_deref_count_slots.argtypes = [ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -class struct_nir_unsigned_upper_bound_config(Structure): - pass - -struct_nir_unsigned_upper_bound_config._pack_ = 1 # source:False -struct_nir_unsigned_upper_bound_config._fields_ = [ - ('min_subgroup_size', ctypes.c_uint32), - ('max_subgroup_size', ctypes.c_uint32), - ('max_workgroup_invocations', ctypes.c_uint32), - ('max_workgroup_count', ctypes.c_uint32 * 3), - ('max_workgroup_size', ctypes.c_uint32 * 3), - ('vertex_attrib_max', ctypes.c_uint32 * 32), -] - -nir_unsigned_upper_bound_config = struct_nir_unsigned_upper_bound_config -try: - nir_unsigned_upper_bound = _libraries['libtinymesa_cpu.so'].nir_unsigned_upper_bound - nir_unsigned_upper_bound.restype = uint32_t - nir_unsigned_upper_bound.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_hash_table), nir_scalar, ctypes.POINTER(struct_nir_unsigned_upper_bound_config)] -except AttributeError: - pass -try: - nir_addition_might_overflow = _libraries['libtinymesa_cpu.so'].nir_addition_might_overflow - nir_addition_might_overflow.restype = ctypes.c_bool - nir_addition_might_overflow.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_hash_table), nir_scalar, ctypes.c_uint32, ctypes.POINTER(struct_nir_unsigned_upper_bound_config)] -except AttributeError: - pass -class struct_nir_opt_preamble_options(Structure): - pass - -struct_nir_opt_preamble_options._pack_ = 1 # source:False -struct_nir_opt_preamble_options._fields_ = [ - ('drawid_uniform', ctypes.c_bool), - ('subgroup_size_uniform', ctypes.c_bool), - ('load_workgroup_size_allowed', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 5), - ('def_size', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_nir_def), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(c__EA_nir_preamble_class))), - ('preamble_storage_size', ctypes.c_uint32 * 2), - ('instr_cost_cb', ctypes.CFUNCTYPE(ctypes.c_float, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('rewrite_cost_cb', ctypes.CFUNCTYPE(ctypes.c_float, ctypes.POINTER(struct_nir_def), ctypes.POINTER(None))), - ('avoid_instr_cb', ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None))), - ('cb_data', ctypes.POINTER(None)), -] - -nir_opt_preamble_options = struct_nir_opt_preamble_options -try: - nir_opt_preamble = _libraries['libtinymesa_cpu.so'].nir_opt_preamble - nir_opt_preamble.restype = ctypes.c_bool - nir_opt_preamble.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_opt_preamble_options), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - nir_shader_get_preamble = _libraries['libtinymesa_cpu.so'].nir_shader_get_preamble - nir_shader_get_preamble.restype = ctypes.POINTER(struct_nir_function_impl) - nir_shader_get_preamble.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_lower_point_smooth = _libraries['libtinymesa_cpu.so'].nir_lower_point_smooth - nir_lower_point_smooth.restype = ctypes.c_bool - nir_lower_point_smooth.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_lower_poly_line_smooth = _libraries['libtinymesa_cpu.so'].nir_lower_poly_line_smooth - nir_lower_poly_line_smooth.restype = ctypes.c_bool - nir_lower_poly_line_smooth.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_mod_analysis = _libraries['libtinymesa_cpu.so'].nir_mod_analysis - nir_mod_analysis.restype = ctypes.c_bool - nir_mod_analysis.argtypes = [nir_scalar, nir_alu_type, ctypes.c_uint32, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - nir_remove_tex_shadow = _libraries['libtinymesa_cpu.so'].nir_remove_tex_shadow - nir_remove_tex_shadow.restype = ctypes.c_bool - nir_remove_tex_shadow.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_trivialize_registers = _libraries['libtinymesa_cpu.so'].nir_trivialize_registers - nir_trivialize_registers.restype = ctypes.c_bool - nir_trivialize_registers.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_static_workgroup_size = _libraries['libtinymesa_cpu.so'].nir_static_workgroup_size - nir_static_workgroup_size.restype = ctypes.c_uint32 - nir_static_workgroup_size.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_reg_get_decl = _libraries['FIXME_STUB'].nir_reg_get_decl - nir_reg_get_decl.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_reg_get_decl.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_next_decl_reg = _libraries['FIXME_STUB'].nir_next_decl_reg - nir_next_decl_reg.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_next_decl_reg.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_after_reg_decls = _libraries['FIXME_STUB'].nir_after_reg_decls - nir_after_reg_decls.restype = nir_cursor - nir_after_reg_decls.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_is_load_reg = _libraries['FIXME_STUB'].nir_is_load_reg - nir_is_load_reg.restype = ctypes.c_bool - nir_is_load_reg.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_is_store_reg = _libraries['FIXME_STUB'].nir_is_store_reg - nir_is_store_reg.restype = ctypes.c_bool - nir_is_store_reg.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - nir_load_reg_for_def = _libraries['FIXME_STUB'].nir_load_reg_for_def - nir_load_reg_for_def.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_load_reg_for_def.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_store_reg_for_def = _libraries['FIXME_STUB'].nir_store_reg_for_def - nir_store_reg_for_def.restype = ctypes.POINTER(struct_nir_intrinsic_instr) - nir_store_reg_for_def.argtypes = [ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -class struct_nir_use_dominance_state(Structure): - pass - -nir_use_dominance_state = struct_nir_use_dominance_state -try: - nir_calc_use_dominance_impl = _libraries['libtinymesa_cpu.so'].nir_calc_use_dominance_impl - nir_calc_use_dominance_impl.restype = ctypes.POINTER(struct_nir_use_dominance_state) - nir_calc_use_dominance_impl.argtypes = [ctypes.POINTER(struct_nir_function_impl), ctypes.c_bool] -except AttributeError: - pass -try: - nir_get_immediate_use_dominator = _libraries['libtinymesa_cpu.so'].nir_get_immediate_use_dominator - nir_get_immediate_use_dominator.restype = ctypes.POINTER(struct_nir_instr) - nir_get_immediate_use_dominator.argtypes = [ctypes.POINTER(struct_nir_use_dominance_state), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_use_dominance_lca = _libraries['libtinymesa_cpu.so'].nir_use_dominance_lca - nir_use_dominance_lca.restype = ctypes.POINTER(struct_nir_instr) - nir_use_dominance_lca.argtypes = [ctypes.POINTER(struct_nir_use_dominance_state), ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_instr_dominates_use = _libraries['libtinymesa_cpu.so'].nir_instr_dominates_use - nir_instr_dominates_use.restype = ctypes.c_bool - nir_instr_dominates_use.argtypes = [ctypes.POINTER(struct_nir_use_dominance_state), ctypes.POINTER(struct_nir_instr), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_print_use_dominators = _libraries['libtinymesa_cpu.so'].nir_print_use_dominators - nir_print_use_dominators.restype = None - nir_print_use_dominators.argtypes = [ctypes.POINTER(struct_nir_use_dominance_state), ctypes.POINTER(ctypes.POINTER(struct_nir_instr)), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_verts_in_output_prim = _libraries['FIXME_STUB'].nir_verts_in_output_prim - nir_verts_in_output_prim.restype = ctypes.c_uint32 - nir_verts_in_output_prim.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -class struct_c__SA_nir_output_deps(Structure): - pass - -class struct_c__SA_nir_output_deps_0(Structure): - pass - -struct_c__SA_nir_output_deps_0._pack_ = 1 # source:False -struct_c__SA_nir_output_deps_0._fields_ = [ - ('instr_list', ctypes.POINTER(ctypes.POINTER(struct_nir_instr))), - ('num_instr', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_c__SA_nir_output_deps._pack_ = 1 # source:False -struct_c__SA_nir_output_deps._fields_ = [ - ('output', struct_c__SA_nir_output_deps_0 * 112), -] - -nir_output_deps = struct_c__SA_nir_output_deps -try: - nir_gather_output_dependencies = _libraries['libtinymesa_cpu.so'].nir_gather_output_dependencies - nir_gather_output_dependencies.restype = None - nir_gather_output_dependencies.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_c__SA_nir_output_deps)] -except AttributeError: - pass -try: - nir_free_output_dependencies = _libraries['libtinymesa_cpu.so'].nir_free_output_dependencies - nir_free_output_dependencies.restype = None - nir_free_output_dependencies.argtypes = [ctypes.POINTER(struct_c__SA_nir_output_deps)] -except AttributeError: - pass -class struct_c__SA_nir_input_to_output_deps(Structure): - pass - -class struct_c__SA_nir_input_to_output_deps_0(Structure): - pass - -struct_c__SA_nir_input_to_output_deps_0._pack_ = 1 # source:False -struct_c__SA_nir_input_to_output_deps_0._fields_ = [ - ('inputs', ctypes.c_uint32 * 28), - ('defined', ctypes.c_bool), - ('uses_ssbo_reads', ctypes.c_bool), - ('uses_image_reads', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte), -] - -struct_c__SA_nir_input_to_output_deps._pack_ = 1 # source:False -struct_c__SA_nir_input_to_output_deps._fields_ = [ - ('output', struct_c__SA_nir_input_to_output_deps_0 * 112), -] - -nir_input_to_output_deps = struct_c__SA_nir_input_to_output_deps -try: - nir_gather_input_to_output_dependencies = _libraries['libtinymesa_cpu.so'].nir_gather_input_to_output_dependencies - nir_gather_input_to_output_dependencies.restype = None - nir_gather_input_to_output_dependencies.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_c__SA_nir_input_to_output_deps)] -except AttributeError: - pass -try: - nir_print_input_to_output_deps = _libraries['libtinymesa_cpu.so'].nir_print_input_to_output_deps - nir_print_input_to_output_deps.restype = None - nir_print_input_to_output_deps.argtypes = [ctypes.POINTER(struct_c__SA_nir_input_to_output_deps), ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct__IO_FILE)] -except AttributeError: - pass -class struct_c__SA_nir_output_clipper_var_groups(Structure): - pass - -struct_c__SA_nir_output_clipper_var_groups._pack_ = 1 # source:False -struct_c__SA_nir_output_clipper_var_groups._fields_ = [ - ('pos_only', ctypes.c_uint32 * 28), - ('var_only', ctypes.c_uint32 * 28), - ('both', ctypes.c_uint32 * 28), -] - -nir_output_clipper_var_groups = struct_c__SA_nir_output_clipper_var_groups -try: - nir_gather_output_clipper_var_groups = _libraries['libtinymesa_cpu.so'].nir_gather_output_clipper_var_groups - nir_gather_output_clipper_var_groups.restype = None - nir_gather_output_clipper_var_groups.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_c__SA_nir_output_clipper_var_groups)] -except AttributeError: - pass -nir_builder = struct_nir_builder -try: - nir_builder_create = _libraries['FIXME_STUB'].nir_builder_create - nir_builder_create.restype = nir_builder - nir_builder_create.argtypes = [ctypes.POINTER(struct_nir_function_impl)] -except AttributeError: - pass -try: - nir_builder_at = _libraries['FIXME_STUB'].nir_builder_at - nir_builder_at.restype = nir_builder - nir_builder_at.argtypes = [nir_cursor] -except AttributeError: - pass -try: - nir_builder_init_simple_shader = _libraries['libtinymesa_cpu.so'].nir_builder_init_simple_shader - nir_builder_init_simple_shader.restype = nir_builder - nir_builder_init_simple_shader.argtypes = [gl_shader_stage, ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -nir_instr_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_instr), ctypes.POINTER(None)) -nir_intrinsic_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_intrinsic_instr), ctypes.POINTER(None)) -nir_alu_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_alu_instr), ctypes.POINTER(None)) -nir_tex_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_tex_instr), ctypes.POINTER(None)) -nir_phi_pass_cb = ctypes.CFUNCTYPE(ctypes.c_bool, ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_phi_instr), ctypes.POINTER(None)) -try: - nir_function_instructions_pass = _libraries['FIXME_STUB'].nir_function_instructions_pass - nir_function_instructions_pass.restype = ctypes.c_bool - nir_function_instructions_pass.argtypes = [ctypes.POINTER(struct_nir_function_impl), nir_instr_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_instructions_pass = _libraries['FIXME_STUB'].nir_shader_instructions_pass - nir_shader_instructions_pass.restype = ctypes.c_bool - nir_shader_instructions_pass.argtypes = [ctypes.POINTER(struct_nir_shader), nir_instr_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_function_intrinsics_pass = _libraries['FIXME_STUB'].nir_function_intrinsics_pass - nir_function_intrinsics_pass.restype = ctypes.c_bool - nir_function_intrinsics_pass.argtypes = [ctypes.POINTER(struct_nir_function_impl), nir_intrinsic_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_intrinsics_pass = _libraries['FIXME_STUB'].nir_shader_intrinsics_pass - nir_shader_intrinsics_pass.restype = ctypes.c_bool - nir_shader_intrinsics_pass.argtypes = [ctypes.POINTER(struct_nir_shader), nir_intrinsic_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_alu_pass = _libraries['FIXME_STUB'].nir_shader_alu_pass - nir_shader_alu_pass.restype = ctypes.c_bool - nir_shader_alu_pass.argtypes = [ctypes.POINTER(struct_nir_shader), nir_alu_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_tex_pass = _libraries['FIXME_STUB'].nir_shader_tex_pass - nir_shader_tex_pass.restype = ctypes.c_bool - nir_shader_tex_pass.argtypes = [ctypes.POINTER(struct_nir_shader), nir_tex_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_shader_phi_pass = _libraries['FIXME_STUB'].nir_shader_phi_pass - nir_shader_phi_pass.restype = ctypes.c_bool - nir_shader_phi_pass.argtypes = [ctypes.POINTER(struct_nir_shader), nir_phi_pass_cb, nir_metadata, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nir_builder_instr_insert = _libraries['libtinymesa_cpu.so'].nir_builder_instr_insert - nir_builder_instr_insert.restype = None - nir_builder_instr_insert.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_builder_instr_insert_at_top = _libraries['libtinymesa_cpu.so'].nir_builder_instr_insert_at_top - nir_builder_instr_insert_at_top.restype = None - nir_builder_instr_insert_at_top.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_instr)] -except AttributeError: - pass -try: - nir_builder_last_instr = _libraries['FIXME_STUB'].nir_builder_last_instr - nir_builder_last_instr.restype = ctypes.POINTER(struct_nir_instr) - nir_builder_last_instr.argtypes = [ctypes.POINTER(struct_nir_builder)] -except AttributeError: - pass -try: - nir_build_alu = _libraries['libtinymesa_cpu.so'].nir_build_alu - nir_build_alu.restype = ctypes.POINTER(struct_nir_def) - nir_build_alu.argtypes = [ctypes.POINTER(struct_nir_builder), nir_op, ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_alu1 = _libraries['libtinymesa_cpu.so'].nir_build_alu1 - nir_build_alu1.restype = ctypes.POINTER(struct_nir_def) - nir_build_alu1.argtypes = [ctypes.POINTER(struct_nir_builder), nir_op, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_alu2 = _libraries['libtinymesa_cpu.so'].nir_build_alu2 - nir_build_alu2.restype = ctypes.POINTER(struct_nir_def) - nir_build_alu2.argtypes = [ctypes.POINTER(struct_nir_builder), nir_op, ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_alu3 = _libraries['libtinymesa_cpu.so'].nir_build_alu3 - nir_build_alu3.restype = ctypes.POINTER(struct_nir_def) - nir_build_alu3.argtypes = [ctypes.POINTER(struct_nir_builder), nir_op, ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_alu4 = _libraries['libtinymesa_cpu.so'].nir_build_alu4 - nir_build_alu4.restype = ctypes.POINTER(struct_nir_def) - nir_build_alu4.argtypes = [ctypes.POINTER(struct_nir_builder), nir_op, ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_alu_src_arr = _libraries['libtinymesa_cpu.so'].nir_build_alu_src_arr - nir_build_alu_src_arr.restype = ctypes.POINTER(struct_nir_def) - nir_build_alu_src_arr.argtypes = [ctypes.POINTER(struct_nir_builder), nir_op, ctypes.POINTER(ctypes.POINTER(struct_nir_def))] -except AttributeError: - pass -try: - nir_build_tex_deref_instr = _libraries['libtinymesa_cpu.so'].nir_build_tex_deref_instr - nir_build_tex_deref_instr.restype = ctypes.POINTER(struct_nir_def) - nir_build_tex_deref_instr.argtypes = [ctypes.POINTER(struct_nir_builder), nir_texop, ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), ctypes.c_uint32, ctypes.POINTER(struct_nir_tex_src)] -except AttributeError: - pass -try: - nir_builder_cf_insert = _libraries['libtinymesa_cpu.so'].nir_builder_cf_insert - nir_builder_cf_insert.restype = None - nir_builder_cf_insert.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_builder_is_inside_cf = _libraries['libtinymesa_cpu.so'].nir_builder_is_inside_cf - nir_builder_is_inside_cf.restype = ctypes.c_bool - nir_builder_is_inside_cf.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_cf_node)] -except AttributeError: - pass -try: - nir_push_if = _libraries['libtinymesa_cpu.so'].nir_push_if - nir_push_if.restype = ctypes.POINTER(struct_nir_if) - nir_push_if.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_push_else = _libraries['libtinymesa_cpu.so'].nir_push_else - nir_push_else.restype = ctypes.POINTER(struct_nir_if) - nir_push_else.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_pop_if = _libraries['libtinymesa_cpu.so'].nir_pop_if - nir_pop_if.restype = None - nir_pop_if.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_if)] -except AttributeError: - pass -try: - nir_if_phi = _libraries['libtinymesa_cpu.so'].nir_if_phi - nir_if_phi.restype = ctypes.POINTER(struct_nir_def) - nir_if_phi.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_push_loop = _libraries['libtinymesa_cpu.so'].nir_push_loop - nir_push_loop.restype = ctypes.POINTER(struct_nir_loop) - nir_push_loop.argtypes = [ctypes.POINTER(struct_nir_builder)] -except AttributeError: - pass -try: - nir_push_continue = _libraries['libtinymesa_cpu.so'].nir_push_continue - nir_push_continue.restype = ctypes.POINTER(struct_nir_loop) - nir_push_continue.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_pop_loop = _libraries['libtinymesa_cpu.so'].nir_pop_loop - nir_pop_loop.restype = None - nir_pop_loop.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_loop)] -except AttributeError: - pass -try: - nir_undef = _libraries['FIXME_STUB'].nir_undef - nir_undef.restype = ctypes.POINTER(struct_nir_def) - nir_undef.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_build_imm = _libraries['FIXME_STUB'].nir_build_imm - nir_build_imm.restype = ctypes.POINTER(struct_nir_def) - nir_build_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(union_c__UA_nir_const_value)] -except AttributeError: - pass -try: - nir_imm_zero = _libraries['FIXME_STUB'].nir_imm_zero - nir_imm_zero.restype = ctypes.POINTER(struct_nir_def) - nir_imm_zero.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_boolN_t = _libraries['FIXME_STUB'].nir_imm_boolN_t - nir_imm_boolN_t.restype = ctypes.POINTER(struct_nir_def) - nir_imm_boolN_t.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_bool, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_bool = _libraries['FIXME_STUB'].nir_imm_bool - nir_imm_bool.restype = ctypes.POINTER(struct_nir_def) - nir_imm_bool.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_bool] -except AttributeError: - pass -try: - nir_imm_true = _libraries['FIXME_STUB'].nir_imm_true - nir_imm_true.restype = ctypes.POINTER(struct_nir_def) - nir_imm_true.argtypes = [ctypes.POINTER(struct_nir_builder)] -except AttributeError: - pass -try: - nir_imm_false = _libraries['FIXME_STUB'].nir_imm_false - nir_imm_false.restype = ctypes.POINTER(struct_nir_def) - nir_imm_false.argtypes = [ctypes.POINTER(struct_nir_builder)] -except AttributeError: - pass -try: - nir_imm_floatN_t = _libraries['FIXME_STUB'].nir_imm_floatN_t - nir_imm_floatN_t.restype = ctypes.POINTER(struct_nir_def) - nir_imm_floatN_t.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_double, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_float16 = _libraries['FIXME_STUB'].nir_imm_float16 - nir_imm_float16.restype = ctypes.POINTER(struct_nir_def) - nir_imm_float16.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_float] -except AttributeError: - pass -try: - nir_imm_float = _libraries['FIXME_STUB'].nir_imm_float - nir_imm_float.restype = ctypes.POINTER(struct_nir_def) - nir_imm_float.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_float] -except AttributeError: - pass -try: - nir_imm_double = _libraries['FIXME_STUB'].nir_imm_double - nir_imm_double.restype = ctypes.POINTER(struct_nir_def) - nir_imm_double.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_double] -except AttributeError: - pass -try: - nir_imm_vec2 = _libraries['FIXME_STUB'].nir_imm_vec2 - nir_imm_vec2.restype = ctypes.POINTER(struct_nir_def) - nir_imm_vec2.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - nir_imm_vec3 = _libraries['FIXME_STUB'].nir_imm_vec3 - nir_imm_vec3.restype = ctypes.POINTER(struct_nir_def) - nir_imm_vec3.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_float, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - nir_imm_vec4 = _libraries['FIXME_STUB'].nir_imm_vec4 - nir_imm_vec4.restype = ctypes.POINTER(struct_nir_def) - nir_imm_vec4.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - nir_imm_vec4_16 = _libraries['FIXME_STUB'].nir_imm_vec4_16 - nir_imm_vec4_16.restype = ctypes.POINTER(struct_nir_def) - nir_imm_vec4_16.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - nir_imm_intN_t = _libraries['FIXME_STUB'].nir_imm_intN_t - nir_imm_intN_t.restype = ctypes.POINTER(struct_nir_def) - nir_imm_intN_t.argtypes = [ctypes.POINTER(struct_nir_builder), uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_int = _libraries['FIXME_STUB'].nir_imm_int - nir_imm_int.restype = ctypes.POINTER(struct_nir_def) - nir_imm_int.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_int32] -except AttributeError: - pass -try: - nir_imm_int64 = _libraries['FIXME_STUB'].nir_imm_int64 - nir_imm_int64.restype = ctypes.POINTER(struct_nir_def) - nir_imm_int64.argtypes = [ctypes.POINTER(struct_nir_builder), int64_t] -except AttributeError: - pass -try: - nir_imm_ivec2 = _libraries['FIXME_STUB'].nir_imm_ivec2 - nir_imm_ivec2.restype = ctypes.POINTER(struct_nir_def) - nir_imm_ivec2.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - nir_imm_ivec3_intN = _libraries['FIXME_STUB'].nir_imm_ivec3_intN - nir_imm_ivec3_intN.restype = ctypes.POINTER(struct_nir_def) - nir_imm_ivec3_intN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_uvec2_intN = _libraries['FIXME_STUB'].nir_imm_uvec2_intN - nir_imm_uvec2_intN.restype = ctypes.POINTER(struct_nir_def) - nir_imm_uvec2_intN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_uvec3_intN = _libraries['FIXME_STUB'].nir_imm_uvec3_intN - nir_imm_uvec3_intN.restype = ctypes.POINTER(struct_nir_def) - nir_imm_uvec3_intN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_ivec3 = _libraries['FIXME_STUB'].nir_imm_ivec3 - nir_imm_ivec3.restype = ctypes.POINTER(struct_nir_def) - nir_imm_ivec3.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - nir_imm_ivec4_intN = _libraries['FIXME_STUB'].nir_imm_ivec4_intN - nir_imm_ivec4_intN.restype = ctypes.POINTER(struct_nir_def) - nir_imm_ivec4_intN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_imm_ivec4 = _libraries['FIXME_STUB'].nir_imm_ivec4 - nir_imm_ivec4.restype = ctypes.POINTER(struct_nir_def) - nir_imm_ivec4.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - nir_builder_alu_instr_finish_and_insert = _libraries['libtinymesa_cpu.so'].nir_builder_alu_instr_finish_and_insert - nir_builder_alu_instr_finish_and_insert.restype = ctypes.POINTER(struct_nir_def) - nir_builder_alu_instr_finish_and_insert.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_alu_instr)] -except AttributeError: - pass -try: - nir_load_system_value = _libraries['libtinymesa_cpu.so'].nir_load_system_value - nir_load_system_value.restype = ctypes.POINTER(struct_nir_def) - nir_load_system_value.argtypes = [ctypes.POINTER(struct_nir_builder), nir_intrinsic_op, ctypes.c_int32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_type_convert = _libraries['libtinymesa_cpu.so'].nir_type_convert - nir_type_convert.restype = ctypes.POINTER(struct_nir_def) - nir_type_convert.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_alu_type, nir_alu_type, nir_rounding_mode] -except AttributeError: - pass -try: - nir_convert_to_bit_size = _libraries['FIXME_STUB'].nir_convert_to_bit_size - nir_convert_to_bit_size.restype = ctypes.POINTER(struct_nir_def) - nir_convert_to_bit_size.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_alu_type, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_i2iN = _libraries['FIXME_STUB'].nir_i2iN - nir_i2iN.restype = ctypes.POINTER(struct_nir_def) - nir_i2iN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_u2uN = _libraries['FIXME_STUB'].nir_u2uN - nir_u2uN.restype = ctypes.POINTER(struct_nir_def) - nir_u2uN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_b2bN = _libraries['FIXME_STUB'].nir_b2bN - nir_b2bN.restype = ctypes.POINTER(struct_nir_def) - nir_b2bN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_f2fN = _libraries['FIXME_STUB'].nir_f2fN - nir_f2fN.restype = ctypes.POINTER(struct_nir_def) - nir_f2fN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_i2b = _libraries['FIXME_STUB'].nir_i2b - nir_i2b.restype = ctypes.POINTER(struct_nir_def) - nir_i2b.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_b2iN = _libraries['FIXME_STUB'].nir_b2iN - nir_b2iN.restype = ctypes.POINTER(struct_nir_def) - nir_b2iN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t] -except AttributeError: - pass -try: - nir_b2fN = _libraries['FIXME_STUB'].nir_b2fN - nir_b2fN.restype = ctypes.POINTER(struct_nir_def) - nir_b2fN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t] -except AttributeError: - pass -try: - nir_i2fN = _libraries['FIXME_STUB'].nir_i2fN - nir_i2fN.restype = ctypes.POINTER(struct_nir_def) - nir_i2fN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_u2fN = _libraries['FIXME_STUB'].nir_u2fN - nir_u2fN.restype = ctypes.POINTER(struct_nir_def) - nir_u2fN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_f2uN = _libraries['FIXME_STUB'].nir_f2uN - nir_f2uN.restype = ctypes.POINTER(struct_nir_def) - nir_f2uN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_f2iN = _libraries['FIXME_STUB'].nir_f2iN - nir_f2iN.restype = ctypes.POINTER(struct_nir_def) - nir_f2iN.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_vec = _libraries['FIXME_STUB'].nir_vec - nir_vec.restype = ctypes.POINTER(struct_nir_def) - nir_vec.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(ctypes.POINTER(struct_nir_def)), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_vec_scalars = _libraries['libtinymesa_cpu.so'].nir_vec_scalars - nir_vec_scalars.restype = ctypes.POINTER(struct_nir_def) - nir_vec_scalars.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_scalar), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_mov_alu = _libraries['FIXME_STUB'].nir_mov_alu - nir_mov_alu.restype = ctypes.POINTER(struct_nir_def) - nir_mov_alu.argtypes = [ctypes.POINTER(struct_nir_builder), nir_alu_src, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_swizzle = _libraries['FIXME_STUB'].nir_swizzle - nir_swizzle.restype = ctypes.POINTER(struct_nir_def) - nir_swizzle.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(ctypes.c_uint32), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_fdot = _libraries['FIXME_STUB'].nir_fdot - nir_fdot.restype = ctypes.POINTER(struct_nir_def) - nir_fdot.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_bfdot = _libraries['FIXME_STUB'].nir_bfdot - nir_bfdot.restype = ctypes.POINTER(struct_nir_def) - nir_bfdot.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ball_iequal = _libraries['FIXME_STUB'].nir_ball_iequal - nir_ball_iequal.restype = ctypes.POINTER(struct_nir_def) - nir_ball_iequal.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ball = _libraries['FIXME_STUB'].nir_ball - nir_ball.restype = ctypes.POINTER(struct_nir_def) - nir_ball.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_bany_inequal = _libraries['FIXME_STUB'].nir_bany_inequal - nir_bany_inequal.restype = ctypes.POINTER(struct_nir_def) - nir_bany_inequal.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_bany = _libraries['FIXME_STUB'].nir_bany - nir_bany.restype = ctypes.POINTER(struct_nir_def) - nir_bany.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_channel = _libraries['FIXME_STUB'].nir_channel - nir_channel.restype = ctypes.POINTER(struct_nir_def) - nir_channel.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_channel_or_undef = _libraries['FIXME_STUB'].nir_channel_or_undef - nir_channel_or_undef.restype = ctypes.POINTER(struct_nir_def) - nir_channel_or_undef.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_int32] -except AttributeError: - pass -try: - nir_channels = _libraries['FIXME_STUB'].nir_channels - nir_channels.restype = ctypes.POINTER(struct_nir_def) - nir_channels.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_component_mask_t] -except AttributeError: - pass -try: - _nir_select_from_array_helper = _libraries['FIXME_STUB']._nir_select_from_array_helper - _nir_select_from_array_helper.restype = ctypes.POINTER(struct_nir_def) - _nir_select_from_array_helper.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(ctypes.POINTER(struct_nir_def)), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_select_from_ssa_def_array = _libraries['FIXME_STUB'].nir_select_from_ssa_def_array - nir_select_from_ssa_def_array.restype = ctypes.POINTER(struct_nir_def) - nir_select_from_ssa_def_array.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(ctypes.POINTER(struct_nir_def)), ctypes.c_uint32, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_vector_extract = _libraries['FIXME_STUB'].nir_vector_extract - nir_vector_extract.restype = ctypes.POINTER(struct_nir_def) - nir_vector_extract.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_vector_insert_imm = _libraries['FIXME_STUB'].nir_vector_insert_imm - nir_vector_insert_imm.restype = ctypes.POINTER(struct_nir_def) - nir_vector_insert_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_vector_insert = _libraries['FIXME_STUB'].nir_vector_insert - nir_vector_insert.restype = ctypes.POINTER(struct_nir_def) - nir_vector_insert.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_replicate = _libraries['FIXME_STUB'].nir_replicate - nir_replicate.restype = ctypes.POINTER(struct_nir_def) - nir_replicate.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_iadd_imm = _libraries['FIXME_STUB'].nir_iadd_imm - nir_iadd_imm.restype = ctypes.POINTER(struct_nir_def) - nir_iadd_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_iadd_imm_nuw = _libraries['FIXME_STUB'].nir_iadd_imm_nuw - nir_iadd_imm_nuw.restype = ctypes.POINTER(struct_nir_def) - nir_iadd_imm_nuw.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_iadd_nuw = _libraries['FIXME_STUB'].nir_iadd_nuw - nir_iadd_nuw.restype = ctypes.POINTER(struct_nir_def) - nir_iadd_nuw.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_fgt_imm = _libraries['FIXME_STUB'].nir_fgt_imm - nir_fgt_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fgt_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_fle_imm = _libraries['FIXME_STUB'].nir_fle_imm - nir_fle_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fle_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_isub_imm = _libraries['FIXME_STUB'].nir_isub_imm - nir_isub_imm.restype = ctypes.POINTER(struct_nir_def) - nir_isub_imm.argtypes = [ctypes.POINTER(struct_nir_builder), uint64_t, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_imax_imm = _libraries['FIXME_STUB'].nir_imax_imm - nir_imax_imm.restype = ctypes.POINTER(struct_nir_def) - nir_imax_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), int64_t] -except AttributeError: - pass -try: - nir_imin_imm = _libraries['FIXME_STUB'].nir_imin_imm - nir_imin_imm.restype = ctypes.POINTER(struct_nir_def) - nir_imin_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), int64_t] -except AttributeError: - pass -try: - nir_umax_imm = _libraries['FIXME_STUB'].nir_umax_imm - nir_umax_imm.restype = ctypes.POINTER(struct_nir_def) - nir_umax_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_umin_imm = _libraries['FIXME_STUB'].nir_umin_imm - nir_umin_imm.restype = ctypes.POINTER(struct_nir_def) - nir_umin_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - _nir_mul_imm = _libraries['FIXME_STUB']._nir_mul_imm - _nir_mul_imm.restype = ctypes.POINTER(struct_nir_def) - _nir_mul_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t, ctypes.c_bool] -except AttributeError: - pass -try: - nir_imul_imm = _libraries['FIXME_STUB'].nir_imul_imm - nir_imul_imm.restype = ctypes.POINTER(struct_nir_def) - nir_imul_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_amul_imm = _libraries['FIXME_STUB'].nir_amul_imm - nir_amul_imm.restype = ctypes.POINTER(struct_nir_def) - nir_amul_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_fadd_imm = _libraries['FIXME_STUB'].nir_fadd_imm - nir_fadd_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fadd_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_fsub_imm = _libraries['FIXME_STUB'].nir_fsub_imm - nir_fsub_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fsub_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_double, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_fmul_imm = _libraries['FIXME_STUB'].nir_fmul_imm - nir_fmul_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fmul_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_fdiv_imm = _libraries['FIXME_STUB'].nir_fdiv_imm - nir_fdiv_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fdiv_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_fpow_imm = _libraries['FIXME_STUB'].nir_fpow_imm - nir_fpow_imm.restype = ctypes.POINTER(struct_nir_def) - nir_fpow_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_iand_imm = _libraries['FIXME_STUB'].nir_iand_imm - nir_iand_imm.restype = ctypes.POINTER(struct_nir_def) - nir_iand_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_test_mask = _libraries['FIXME_STUB'].nir_test_mask - nir_test_mask.restype = ctypes.POINTER(struct_nir_def) - nir_test_mask.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_ior_imm = _libraries['FIXME_STUB'].nir_ior_imm - nir_ior_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ior_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_ishl_imm = _libraries['FIXME_STUB'].nir_ishl_imm - nir_ishl_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ishl_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t] -except AttributeError: - pass -try: - nir_ishr_imm = _libraries['FIXME_STUB'].nir_ishr_imm - nir_ishr_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ishr_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t] -except AttributeError: - pass -try: - nir_ushr_imm = _libraries['FIXME_STUB'].nir_ushr_imm - nir_ushr_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ushr_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t] -except AttributeError: - pass -try: - nir_imod_imm = _libraries['FIXME_STUB'].nir_imod_imm - nir_imod_imm.restype = ctypes.POINTER(struct_nir_def) - nir_imod_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_udiv_imm = _libraries['FIXME_STUB'].nir_udiv_imm - nir_udiv_imm.restype = ctypes.POINTER(struct_nir_def) - nir_udiv_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_umod_imm = _libraries['FIXME_STUB'].nir_umod_imm - nir_umod_imm.restype = ctypes.POINTER(struct_nir_def) - nir_umod_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_align_imm = _libraries['FIXME_STUB'].nir_align_imm - nir_align_imm.restype = ctypes.POINTER(struct_nir_def) - nir_align_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t] -except AttributeError: - pass -try: - nir_ibfe_imm = _libraries['FIXME_STUB'].nir_ibfe_imm - nir_ibfe_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ibfe_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_ubfe_imm = _libraries['FIXME_STUB'].nir_ubfe_imm - nir_ubfe_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ubfe_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_ubitfield_extract_imm = _libraries['FIXME_STUB'].nir_ubitfield_extract_imm - nir_ubitfield_extract_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ubitfield_extract_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_ibitfield_extract_imm = _libraries['FIXME_STUB'].nir_ibitfield_extract_imm - nir_ibitfield_extract_imm.restype = ctypes.POINTER(struct_nir_def) - nir_ibitfield_extract_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_bitfield_insert_imm = _libraries['FIXME_STUB'].nir_bitfield_insert_imm - nir_bitfield_insert_imm.restype = ctypes.POINTER(struct_nir_def) - nir_bitfield_insert_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_extract_u8_imm = _libraries['FIXME_STUB'].nir_extract_u8_imm - nir_extract_u8_imm.restype = ctypes.POINTER(struct_nir_def) - nir_extract_u8_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_extract_i8_imm = _libraries['FIXME_STUB'].nir_extract_i8_imm - nir_extract_i8_imm.restype = ctypes.POINTER(struct_nir_def) - nir_extract_i8_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_fclamp = _libraries['FIXME_STUB'].nir_fclamp - nir_fclamp.restype = ctypes.POINTER(struct_nir_def) - nir_fclamp.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_iclamp = _libraries['FIXME_STUB'].nir_iclamp - nir_iclamp.restype = ctypes.POINTER(struct_nir_def) - nir_iclamp.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_uclamp = _libraries['FIXME_STUB'].nir_uclamp - nir_uclamp.restype = ctypes.POINTER(struct_nir_def) - nir_uclamp.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ffma_imm12 = _libraries['FIXME_STUB'].nir_ffma_imm12 - nir_ffma_imm12.restype = ctypes.POINTER(struct_nir_def) - nir_ffma_imm12.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double, ctypes.c_double] -except AttributeError: - pass -try: - nir_ffma_imm1 = _libraries['FIXME_STUB'].nir_ffma_imm1 - nir_ffma_imm1.restype = ctypes.POINTER(struct_nir_def) - nir_ffma_imm1.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_double, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ffma_imm2 = _libraries['FIXME_STUB'].nir_ffma_imm2 - nir_ffma_imm2.restype = ctypes.POINTER(struct_nir_def) - nir_ffma_imm2.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.c_double] -except AttributeError: - pass -try: - nir_a_minus_bc = _libraries['FIXME_STUB'].nir_a_minus_bc - nir_a_minus_bc.restype = ctypes.POINTER(struct_nir_def) - nir_a_minus_bc.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_pack_bits = _libraries['FIXME_STUB'].nir_pack_bits - nir_pack_bits.restype = ctypes.POINTER(struct_nir_def) - nir_pack_bits.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_unpack_bits = _libraries['FIXME_STUB'].nir_unpack_bits - nir_unpack_bits.restype = ctypes.POINTER(struct_nir_def) - nir_unpack_bits.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_extract_bits = _libraries['FIXME_STUB'].nir_extract_bits - nir_extract_bits.restype = ctypes.POINTER(struct_nir_def) - nir_extract_bits.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(ctypes.POINTER(struct_nir_def)), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_bitcast_vector = _libraries['FIXME_STUB'].nir_bitcast_vector - nir_bitcast_vector.restype = ctypes.POINTER(struct_nir_def) - nir_bitcast_vector.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_trim_vector = _libraries['FIXME_STUB'].nir_trim_vector - nir_trim_vector.restype = ctypes.POINTER(struct_nir_def) - nir_trim_vector.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_pad_vector = _libraries['FIXME_STUB'].nir_pad_vector - nir_pad_vector.restype = ctypes.POINTER(struct_nir_def) - nir_pad_vector.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_pad_vector_imm_int = _libraries['FIXME_STUB'].nir_pad_vector_imm_int - nir_pad_vector_imm_int.restype = ctypes.POINTER(struct_nir_def) - nir_pad_vector_imm_int.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_pad_vec4 = _libraries['FIXME_STUB'].nir_pad_vec4 - nir_pad_vec4.restype = ctypes.POINTER(struct_nir_def) - nir_pad_vec4.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_resize_vector = _libraries['FIXME_STUB'].nir_resize_vector - nir_resize_vector.restype = ctypes.POINTER(struct_nir_def) - nir_resize_vector.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_shift_channels = _libraries['FIXME_STUB'].nir_shift_channels - nir_shift_channels.restype = ctypes.POINTER(struct_nir_def) - nir_shift_channels.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_int32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_ssa_for_alu_src = _libraries['libtinymesa_cpu.so'].nir_ssa_for_alu_src - nir_ssa_for_alu_src.restype = ctypes.POINTER(struct_nir_def) - nir_ssa_for_alu_src.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_alu_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_get_ptr_bitsize = _libraries['FIXME_STUB'].nir_get_ptr_bitsize - nir_get_ptr_bitsize.restype = ctypes.c_uint32 - nir_get_ptr_bitsize.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - nir_build_deref_var = _libraries['FIXME_STUB'].nir_build_deref_var - nir_build_deref_var.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_var.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_build_deref_array = _libraries['FIXME_STUB'].nir_build_deref_array - nir_build_deref_array.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_array.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_deref_array_imm = _libraries['FIXME_STUB'].nir_build_deref_array_imm - nir_build_deref_array_imm.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_array_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), int64_t] -except AttributeError: - pass -try: - nir_build_deref_ptr_as_array = _libraries['FIXME_STUB'].nir_build_deref_ptr_as_array - nir_build_deref_ptr_as_array.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_ptr_as_array.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_deref_array_wildcard = _libraries['FIXME_STUB'].nir_build_deref_array_wildcard - nir_build_deref_array_wildcard.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_array_wildcard.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_build_deref_struct = _libraries['FIXME_STUB'].nir_build_deref_struct - nir_build_deref_struct.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_struct.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_build_deref_cast_with_alignment = _libraries['FIXME_STUB'].nir_build_deref_cast_with_alignment - nir_build_deref_cast_with_alignment.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_cast_with_alignment.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_variable_mode, ctypes.POINTER(struct_glsl_type), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_build_deref_cast = _libraries['FIXME_STUB'].nir_build_deref_cast - nir_build_deref_cast.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_cast.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_variable_mode, ctypes.POINTER(struct_glsl_type), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_alignment_deref_cast = _libraries['FIXME_STUB'].nir_alignment_deref_cast - nir_alignment_deref_cast.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_alignment_deref_cast.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), uint32_t, uint32_t] -except AttributeError: - pass -try: - nir_build_deref_follower = _libraries['FIXME_STUB'].nir_build_deref_follower - nir_build_deref_follower.restype = ctypes.POINTER(struct_nir_deref_instr) - nir_build_deref_follower.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_load_deref_with_access = _libraries['FIXME_STUB'].nir_load_deref_with_access - nir_load_deref_with_access.restype = ctypes.POINTER(struct_nir_def) - nir_load_deref_with_access.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), gl_access_qualifier] -except AttributeError: - pass -try: - nir_load_deref = _libraries['FIXME_STUB'].nir_load_deref - nir_load_deref.restype = ctypes.POINTER(struct_nir_def) - nir_load_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_store_deref_with_access = _libraries['FIXME_STUB'].nir_store_deref_with_access - nir_store_deref_with_access.restype = None - nir_store_deref_with_access.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, gl_access_qualifier] -except AttributeError: - pass -try: - nir_store_deref = _libraries['FIXME_STUB'].nir_store_deref - nir_store_deref.restype = None - nir_store_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_build_write_masked_store = _libraries['FIXME_STUB'].nir_build_write_masked_store - nir_build_write_masked_store.restype = None - nir_build_write_masked_store.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_build_write_masked_stores = _libraries['FIXME_STUB'].nir_build_write_masked_stores - nir_build_write_masked_stores.restype = None - nir_build_write_masked_stores.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_copy_deref_with_access = _libraries['FIXME_STUB'].nir_copy_deref_with_access - nir_copy_deref_with_access.restype = None - nir_copy_deref_with_access.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), gl_access_qualifier, gl_access_qualifier] -except AttributeError: - pass -try: - nir_copy_deref = _libraries['FIXME_STUB'].nir_copy_deref - nir_copy_deref.restype = None - nir_copy_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr)] -except AttributeError: - pass -try: - nir_memcpy_deref_with_access = _libraries['FIXME_STUB'].nir_memcpy_deref_with_access - nir_memcpy_deref_with_access.restype = None - nir_memcpy_deref_with_access.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), gl_access_qualifier, gl_access_qualifier] -except AttributeError: - pass -try: - nir_memcpy_deref = _libraries['FIXME_STUB'].nir_memcpy_deref - nir_memcpy_deref.restype = None - nir_memcpy_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_load_var = _libraries['FIXME_STUB'].nir_load_var - nir_load_var.restype = ctypes.POINTER(struct_nir_def) - nir_load_var.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_store_var = _libraries['FIXME_STUB'].nir_store_var - nir_store_var.restype = None - nir_store_var.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_copy_var = _libraries['FIXME_STUB'].nir_copy_var - nir_copy_var.restype = None - nir_copy_var.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_variable)] -except AttributeError: - pass -try: - nir_load_array_var = _libraries['FIXME_STUB'].nir_load_array_var - nir_load_array_var.restype = ctypes.POINTER(struct_nir_def) - nir_load_array_var.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_load_array_var_imm = _libraries['FIXME_STUB'].nir_load_array_var_imm - nir_load_array_var_imm.restype = ctypes.POINTER(struct_nir_def) - nir_load_array_var_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), int64_t] -except AttributeError: - pass -try: - nir_store_array_var = _libraries['FIXME_STUB'].nir_store_array_var - nir_store_array_var.restype = None - nir_store_array_var.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_store_array_var_imm = _libraries['FIXME_STUB'].nir_store_array_var_imm - nir_store_array_var_imm.restype = None - nir_store_array_var_imm.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_variable), int64_t, ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_load_global = _libraries['FIXME_STUB'].nir_load_global - nir_load_global.restype = ctypes.POINTER(struct_nir_def) - nir_load_global.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_store_global = _libraries['FIXME_STUB'].nir_store_global - nir_store_global.restype = None - nir_store_global.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, ctypes.POINTER(struct_nir_def), nir_component_mask_t] -except AttributeError: - pass -try: - nir_load_global_constant = _libraries['FIXME_STUB'].nir_load_global_constant - nir_load_global_constant.restype = ctypes.POINTER(struct_nir_def) - nir_load_global_constant.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_load_param = _libraries['FIXME_STUB'].nir_load_param - nir_load_param.restype = ctypes.POINTER(struct_nir_def) - nir_load_param.argtypes = [ctypes.POINTER(struct_nir_builder), uint32_t] -except AttributeError: - pass -try: - nir_decl_reg = _libraries['FIXME_STUB'].nir_decl_reg - nir_decl_reg.restype = ctypes.POINTER(struct_nir_def) - nir_decl_reg.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_load_reg = _libraries['FIXME_STUB'].nir_load_reg - nir_load_reg.restype = ctypes.POINTER(struct_nir_def) - nir_load_reg.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_store_reg = _libraries['FIXME_STUB'].nir_store_reg - nir_store_reg.restype = None - nir_store_reg.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_tex_src_for_ssa = _libraries['FIXME_STUB'].nir_tex_src_for_ssa - nir_tex_src_for_ssa.restype = nir_tex_src - nir_tex_src_for_ssa.argtypes = [nir_tex_src_type, ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_deriv = _libraries['FIXME_STUB'].nir_build_deriv - nir_build_deriv.restype = ctypes.POINTER(struct_nir_def) - nir_build_deriv.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), nir_intrinsic_op] -except AttributeError: - pass -try: - nir_ddx = _libraries['FIXME_STUB'].nir_ddx - nir_ddx.restype = ctypes.POINTER(struct_nir_def) - nir_ddx.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ddx_fine = _libraries['FIXME_STUB'].nir_ddx_fine - nir_ddx_fine.restype = ctypes.POINTER(struct_nir_def) - nir_ddx_fine.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ddx_coarse = _libraries['FIXME_STUB'].nir_ddx_coarse - nir_ddx_coarse.restype = ctypes.POINTER(struct_nir_def) - nir_ddx_coarse.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ddy = _libraries['FIXME_STUB'].nir_ddy - nir_ddy.restype = ctypes.POINTER(struct_nir_def) - nir_ddy.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ddy_fine = _libraries['FIXME_STUB'].nir_ddy_fine - nir_ddy_fine.restype = ctypes.POINTER(struct_nir_def) - nir_ddy_fine.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_ddy_coarse = _libraries['FIXME_STUB'].nir_ddy_coarse - nir_ddy_coarse.restype = ctypes.POINTER(struct_nir_def) - nir_ddy_coarse.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_tex_deref = _libraries['FIXME_STUB'].nir_tex_deref - nir_tex_deref.restype = ctypes.POINTER(struct_nir_def) - nir_tex_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_txl_deref = _libraries['FIXME_STUB'].nir_txl_deref - nir_txl_deref.restype = ctypes.POINTER(struct_nir_def) - nir_txl_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_txl_zero_deref = _libraries['FIXME_STUB'].nir_txl_zero_deref - nir_txl_zero_deref.restype = ctypes.POINTER(struct_nir_def) - nir_txl_zero_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_tex_type_has_lod = _libraries['FIXME_STUB'].nir_tex_type_has_lod - nir_tex_type_has_lod.restype = ctypes.c_bool - nir_tex_type_has_lod.argtypes = [ctypes.POINTER(struct_glsl_type)] -except AttributeError: - pass -try: - nir_txf_deref = _libraries['FIXME_STUB'].nir_txf_deref - nir_txf_deref.restype = ctypes.POINTER(struct_nir_def) - nir_txf_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_txf_ms_deref = _libraries['FIXME_STUB'].nir_txf_ms_deref - nir_txf_ms_deref.restype = ctypes.POINTER(struct_nir_def) - nir_txf_ms_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_txs_deref = _libraries['FIXME_STUB'].nir_txs_deref - nir_txs_deref.restype = ctypes.POINTER(struct_nir_def) - nir_txs_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_samples_identical_deref = _libraries['FIXME_STUB'].nir_samples_identical_deref - nir_samples_identical_deref.restype = ctypes.POINTER(struct_nir_def) - nir_samples_identical_deref.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_deref_instr), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_mask = _libraries['FIXME_STUB'].nir_mask - nir_mask.restype = ctypes.POINTER(struct_nir_def) - nir_mask.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.c_uint32] -except AttributeError: - pass -try: - nir_load_barycentric = _libraries['FIXME_STUB'].nir_load_barycentric - nir_load_barycentric.restype = ctypes.POINTER(struct_nir_def) - nir_load_barycentric.argtypes = [ctypes.POINTER(struct_nir_builder), nir_intrinsic_op, ctypes.c_uint32] -except AttributeError: - pass -try: - nir_jump = _libraries['FIXME_STUB'].nir_jump - nir_jump.restype = None - nir_jump.argtypes = [ctypes.POINTER(struct_nir_builder), nir_jump_type] -except AttributeError: - pass -try: - nir_goto = _libraries['FIXME_STUB'].nir_goto - nir_goto.restype = None - nir_goto.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_goto_if = _libraries['FIXME_STUB'].nir_goto_if - nir_goto_if.restype = None - nir_goto_if.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_block), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_block)] -except AttributeError: - pass -try: - nir_break_if = _libraries['FIXME_STUB'].nir_break_if - nir_break_if.restype = None - nir_break_if.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_call = _libraries['FIXME_STUB'].nir_build_call - nir_build_call.restype = None - nir_build_call.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_function), size_t, ctypes.POINTER(ctypes.POINTER(struct_nir_def))] -except AttributeError: - pass -try: - nir_build_indirect_call = _libraries['FIXME_STUB'].nir_build_indirect_call - nir_build_indirect_call.restype = None - nir_build_indirect_call.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_function), ctypes.POINTER(struct_nir_def), size_t, ctypes.POINTER(ctypes.POINTER(struct_nir_def))] -except AttributeError: - pass -try: - nir_discard = _libraries['FIXME_STUB'].nir_discard - nir_discard.restype = None - nir_discard.argtypes = [ctypes.POINTER(struct_nir_builder)] -except AttributeError: - pass -try: - nir_discard_if = _libraries['FIXME_STUB'].nir_discard_if - nir_discard_if.restype = None - nir_discard_if.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_build_string = _libraries['FIXME_STUB'].nir_build_string - nir_build_string.restype = ctypes.POINTER(struct_nir_def) - nir_build_string.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_compare_func = _libraries['libtinymesa_cpu.so'].nir_compare_func - nir_compare_func.restype = ctypes.POINTER(struct_nir_def) - nir_compare_func.argtypes = [ctypes.POINTER(struct_nir_builder), compare_func, ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_scoped_memory_barrier = _libraries['FIXME_STUB'].nir_scoped_memory_barrier - nir_scoped_memory_barrier.restype = None - nir_scoped_memory_barrier.argtypes = [ctypes.POINTER(struct_nir_builder), mesa_scope, nir_memory_semantics, nir_variable_mode] -except AttributeError: - pass -try: - nir_gen_rect_vertices = _libraries['libtinymesa_cpu.so'].nir_gen_rect_vertices - nir_gen_rect_vertices.restype = ctypes.POINTER(struct_nir_def) - nir_gen_rect_vertices.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(struct_nir_def), ctypes.POINTER(struct_nir_def)] -except AttributeError: - pass -try: - nir_printf_fmt = _libraries['libtinymesa_cpu.so'].nir_printf_fmt - nir_printf_fmt.restype = None - nir_printf_fmt.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_printf_fmt_at_px = _libraries['libtinymesa_cpu.so'].nir_printf_fmt_at_px - nir_printf_fmt_at_px.restype = None - nir_printf_fmt_at_px.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nir_call_serialized = _libraries['libtinymesa_cpu.so'].nir_call_serialized - nir_call_serialized.restype = ctypes.POINTER(struct_nir_def) - nir_call_serialized.argtypes = [ctypes.POINTER(struct_nir_builder), ctypes.POINTER(ctypes.c_uint32), size_t, ctypes.POINTER(ctypes.POINTER(struct_nir_def))] -except AttributeError: - pass -try: - nir_serialize = _libraries['libtinymesa_cpu.so'].nir_serialize - nir_serialize.restype = None - nir_serialize.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(struct_nir_shader), ctypes.c_bool] -except AttributeError: - pass -try: - nir_deserialize = _libraries['libtinymesa_cpu.so'].nir_deserialize - nir_deserialize.restype = ctypes.POINTER(struct_nir_shader) - nir_deserialize.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass -try: - nir_serialize_function = _libraries['libtinymesa_cpu.so'].nir_serialize_function - nir_serialize_function.restype = None - nir_serialize_function.argtypes = [ctypes.POINTER(struct_blob), ctypes.POINTER(struct_nir_function)] -except AttributeError: - pass -try: - nir_deserialize_function = _libraries['libtinymesa_cpu.so'].nir_deserialize_function - nir_deserialize_function.restype = ctypes.POINTER(struct_nir_function) - nir_deserialize_function.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_blob_reader)] -except AttributeError: - pass - -# values for enumeration 'nv_device_type' -nv_device_type__enumvalues = { - 0: 'NV_DEVICE_TYPE_IGP', - 1: 'NV_DEVICE_TYPE_DIS', - 2: 'NV_DEVICE_TYPE_SOC', -} -NV_DEVICE_TYPE_IGP = 0 -NV_DEVICE_TYPE_DIS = 1 -NV_DEVICE_TYPE_SOC = 2 -nv_device_type = ctypes.c_uint32 # enum -class struct_nv_device_info(Structure): - pass - -class struct_nv_device_info_pci(Structure): - pass - -struct_nv_device_info_pci._pack_ = 1 # source:False +# nir_shader *nir_deserialize(void *mem_ctx, const struct nir_shader_compiler_options *options, struct blob_reader *blob) +try: (nir_deserialize:=dll.nir_deserialize).restype, nir_deserialize.argtypes = ctypes.POINTER(nir_shader), [ctypes.c_void_p, ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# void nir_serialize_function(struct blob *blob, const nir_function *fxn) +try: (nir_serialize_function:=dll.nir_serialize_function).restype, nir_serialize_function.argtypes = None, [ctypes.POINTER(struct_blob), ctypes.POINTER(nir_function)] +except AttributeError: pass + +# nir_function *nir_deserialize_function(void *mem_ctx, const struct nir_shader_compiler_options *options, struct blob_reader *blob) +try: (nir_deserialize_function:=dll.nir_deserialize_function).restype, nir_deserialize_function.argtypes = ctypes.POINTER(nir_function), [ctypes.c_void_p, ctypes.POINTER(struct_nir_shader_compiler_options), ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +nir_intrinsic_index_flag = CEnum(ctypes.c_uint32) +NIR_INTRINSIC_BASE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_BASE', 0) +NIR_INTRINSIC_WRITE_MASK = nir_intrinsic_index_flag.define('NIR_INTRINSIC_WRITE_MASK', 1) +NIR_INTRINSIC_STREAM_ID = nir_intrinsic_index_flag.define('NIR_INTRINSIC_STREAM_ID', 2) +NIR_INTRINSIC_UCP_ID = nir_intrinsic_index_flag.define('NIR_INTRINSIC_UCP_ID', 3) +NIR_INTRINSIC_RANGE_BASE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_RANGE_BASE', 4) +NIR_INTRINSIC_RANGE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_RANGE', 5) +NIR_INTRINSIC_DESC_SET = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DESC_SET', 6) +NIR_INTRINSIC_BINDING = nir_intrinsic_index_flag.define('NIR_INTRINSIC_BINDING', 7) +NIR_INTRINSIC_COMPONENT = nir_intrinsic_index_flag.define('NIR_INTRINSIC_COMPONENT', 8) +NIR_INTRINSIC_COLUMN = nir_intrinsic_index_flag.define('NIR_INTRINSIC_COLUMN', 9) +NIR_INTRINSIC_INTERP_MODE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_INTERP_MODE', 10) +NIR_INTRINSIC_REDUCTION_OP = nir_intrinsic_index_flag.define('NIR_INTRINSIC_REDUCTION_OP', 11) +NIR_INTRINSIC_CLUSTER_SIZE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_CLUSTER_SIZE', 12) +NIR_INTRINSIC_PARAM_IDX = nir_intrinsic_index_flag.define('NIR_INTRINSIC_PARAM_IDX', 13) +NIR_INTRINSIC_IMAGE_DIM = nir_intrinsic_index_flag.define('NIR_INTRINSIC_IMAGE_DIM', 14) +NIR_INTRINSIC_IMAGE_ARRAY = nir_intrinsic_index_flag.define('NIR_INTRINSIC_IMAGE_ARRAY', 15) +NIR_INTRINSIC_FORMAT = nir_intrinsic_index_flag.define('NIR_INTRINSIC_FORMAT', 16) +NIR_INTRINSIC_ACCESS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ACCESS', 17) +NIR_INTRINSIC_CALL_IDX = nir_intrinsic_index_flag.define('NIR_INTRINSIC_CALL_IDX', 18) +NIR_INTRINSIC_STACK_SIZE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_STACK_SIZE', 19) +NIR_INTRINSIC_ALIGN_MUL = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ALIGN_MUL', 20) +NIR_INTRINSIC_ALIGN_OFFSET = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ALIGN_OFFSET', 21) +NIR_INTRINSIC_DESC_TYPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DESC_TYPE', 22) +NIR_INTRINSIC_SRC_TYPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SRC_TYPE', 23) +NIR_INTRINSIC_DEST_TYPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DEST_TYPE', 24) +NIR_INTRINSIC_SRC_BASE_TYPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SRC_BASE_TYPE', 25) +NIR_INTRINSIC_SRC_BASE_TYPE2 = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SRC_BASE_TYPE2', 26) +NIR_INTRINSIC_DEST_BASE_TYPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DEST_BASE_TYPE', 27) +NIR_INTRINSIC_SWIZZLE_MASK = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SWIZZLE_MASK', 28) +NIR_INTRINSIC_FETCH_INACTIVE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_FETCH_INACTIVE', 29) +NIR_INTRINSIC_OFFSET0 = nir_intrinsic_index_flag.define('NIR_INTRINSIC_OFFSET0', 30) +NIR_INTRINSIC_OFFSET1 = nir_intrinsic_index_flag.define('NIR_INTRINSIC_OFFSET1', 31) +NIR_INTRINSIC_ST64 = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ST64', 32) +NIR_INTRINSIC_ARG_UPPER_BOUND_U32_AMD = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ARG_UPPER_BOUND_U32_AMD', 33) +NIR_INTRINSIC_DST_ACCESS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DST_ACCESS', 34) +NIR_INTRINSIC_SRC_ACCESS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SRC_ACCESS', 35) +NIR_INTRINSIC_DRIVER_LOCATION = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DRIVER_LOCATION', 36) +NIR_INTRINSIC_MEMORY_SEMANTICS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_MEMORY_SEMANTICS', 37) +NIR_INTRINSIC_MEMORY_MODES = nir_intrinsic_index_flag.define('NIR_INTRINSIC_MEMORY_MODES', 38) +NIR_INTRINSIC_MEMORY_SCOPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_MEMORY_SCOPE', 39) +NIR_INTRINSIC_EXECUTION_SCOPE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_EXECUTION_SCOPE', 40) +NIR_INTRINSIC_IO_SEMANTICS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_IO_SEMANTICS', 41) +NIR_INTRINSIC_IO_XFB = nir_intrinsic_index_flag.define('NIR_INTRINSIC_IO_XFB', 42) +NIR_INTRINSIC_IO_XFB2 = nir_intrinsic_index_flag.define('NIR_INTRINSIC_IO_XFB2', 43) +NIR_INTRINSIC_RAY_QUERY_VALUE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_RAY_QUERY_VALUE', 44) +NIR_INTRINSIC_COMMITTED = nir_intrinsic_index_flag.define('NIR_INTRINSIC_COMMITTED', 45) +NIR_INTRINSIC_ROUNDING_MODE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ROUNDING_MODE', 46) +NIR_INTRINSIC_SATURATE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SATURATE', 47) +NIR_INTRINSIC_SYNCHRONOUS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SYNCHRONOUS', 48) +NIR_INTRINSIC_VALUE_ID = nir_intrinsic_index_flag.define('NIR_INTRINSIC_VALUE_ID', 49) +NIR_INTRINSIC_SIGN_EXTEND = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SIGN_EXTEND', 50) +NIR_INTRINSIC_FLAGS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_FLAGS', 51) +NIR_INTRINSIC_ATOMIC_OP = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ATOMIC_OP', 52) +NIR_INTRINSIC_RESOURCE_BLOCK_INTEL = nir_intrinsic_index_flag.define('NIR_INTRINSIC_RESOURCE_BLOCK_INTEL', 53) +NIR_INTRINSIC_RESOURCE_ACCESS_INTEL = nir_intrinsic_index_flag.define('NIR_INTRINSIC_RESOURCE_ACCESS_INTEL', 54) +NIR_INTRINSIC_NUM_COMPONENTS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_NUM_COMPONENTS', 55) +NIR_INTRINSIC_NUM_ARRAY_ELEMS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_NUM_ARRAY_ELEMS', 56) +NIR_INTRINSIC_BIT_SIZE = nir_intrinsic_index_flag.define('NIR_INTRINSIC_BIT_SIZE', 57) +NIR_INTRINSIC_DIVERGENT = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DIVERGENT', 58) +NIR_INTRINSIC_LEGACY_FABS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_LEGACY_FABS', 59) +NIR_INTRINSIC_LEGACY_FNEG = nir_intrinsic_index_flag.define('NIR_INTRINSIC_LEGACY_FNEG', 60) +NIR_INTRINSIC_LEGACY_FSAT = nir_intrinsic_index_flag.define('NIR_INTRINSIC_LEGACY_FSAT', 61) +NIR_INTRINSIC_CMAT_DESC = nir_intrinsic_index_flag.define('NIR_INTRINSIC_CMAT_DESC', 62) +NIR_INTRINSIC_MATRIX_LAYOUT = nir_intrinsic_index_flag.define('NIR_INTRINSIC_MATRIX_LAYOUT', 63) +NIR_INTRINSIC_CMAT_SIGNED_MASK = nir_intrinsic_index_flag.define('NIR_INTRINSIC_CMAT_SIGNED_MASK', 64) +NIR_INTRINSIC_ALU_OP = nir_intrinsic_index_flag.define('NIR_INTRINSIC_ALU_OP', 65) +NIR_INTRINSIC_NEG_LO_AMD = nir_intrinsic_index_flag.define('NIR_INTRINSIC_NEG_LO_AMD', 66) +NIR_INTRINSIC_NEG_HI_AMD = nir_intrinsic_index_flag.define('NIR_INTRINSIC_NEG_HI_AMD', 67) +NIR_INTRINSIC_SYSTOLIC_DEPTH = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SYSTOLIC_DEPTH', 68) +NIR_INTRINSIC_REPEAT_COUNT = nir_intrinsic_index_flag.define('NIR_INTRINSIC_REPEAT_COUNT', 69) +NIR_INTRINSIC_DST_CMAT_DESC = nir_intrinsic_index_flag.define('NIR_INTRINSIC_DST_CMAT_DESC', 70) +NIR_INTRINSIC_SRC_CMAT_DESC = nir_intrinsic_index_flag.define('NIR_INTRINSIC_SRC_CMAT_DESC', 71) +NIR_INTRINSIC_EXPLICIT_COORD = nir_intrinsic_index_flag.define('NIR_INTRINSIC_EXPLICIT_COORD', 72) +NIR_INTRINSIC_FMT_IDX = nir_intrinsic_index_flag.define('NIR_INTRINSIC_FMT_IDX', 73) +NIR_INTRINSIC_PREAMBLE_CLASS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_PREAMBLE_CLASS', 74) +NIR_INTRINSIC_NUM_INDEX_FLAGS = nir_intrinsic_index_flag.define('NIR_INTRINSIC_NUM_INDEX_FLAGS', 75) + +try: nir_intrinsic_index_names = (ctypes.POINTER(ctypes.c_char) * 75).in_dll(dll, 'nir_intrinsic_index_names') +except (ValueError,AttributeError): pass +enum_nv_device_type = CEnum(ctypes.c_ubyte) +NV_DEVICE_TYPE_IGP = enum_nv_device_type.define('NV_DEVICE_TYPE_IGP', 0) +NV_DEVICE_TYPE_DIS = enum_nv_device_type.define('NV_DEVICE_TYPE_DIS', 1) +NV_DEVICE_TYPE_SOC = enum_nv_device_type.define('NV_DEVICE_TYPE_SOC', 2) + +class struct_nv_device_info(Struct): pass +class struct_nv_device_info_pci(Struct): pass struct_nv_device_info_pci._fields_ = [ - ('domain', ctypes.c_uint16), - ('bus', ctypes.c_ubyte), - ('dev', ctypes.c_ubyte), - ('func', ctypes.c_ubyte), - ('revision_id', ctypes.c_ubyte), + ('domain', uint16_t), + ('bus', uint8_t), + ('dev', uint8_t), + ('func', uint8_t), + ('revision_id', uint8_t), ] - -struct_nv_device_info._pack_ = 1 # source:False struct_nv_device_info._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('device_id', ctypes.c_uint16), - ('chipset', ctypes.c_uint16), - ('device_name', ctypes.c_char * 64), - ('chipset_name', ctypes.c_char * 16), - ('pci', struct_nv_device_info_pci), - ('sm', ctypes.c_ubyte), - ('gpc_count', ctypes.c_ubyte), - ('tpc_count', ctypes.c_uint16), - ('mp_per_tpc', ctypes.c_ubyte), - ('max_warps_per_mp', ctypes.c_ubyte), - ('cls_copy', ctypes.c_uint16), - ('cls_eng2d', ctypes.c_uint16), - ('cls_eng3d', ctypes.c_uint16), - ('cls_m2mf', ctypes.c_uint16), - ('cls_compute', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 4), - ('vram_size_B', ctypes.c_uint64), - ('bar_size_B', ctypes.c_uint64), + ('type', enum_nv_device_type), + ('device_id', uint16_t), + ('chipset', uint16_t), + ('device_name', (ctypes.c_char * 64)), + ('chipset_name', (ctypes.c_char * 16)), + ('pci', struct_nv_device_info_pci), + ('sm', uint8_t), + ('gpc_count', uint8_t), + ('tpc_count', uint16_t), + ('mp_per_tpc', uint8_t), + ('max_warps_per_mp', uint8_t), + ('cls_copy', uint16_t), + ('cls_eng2d', uint16_t), + ('cls_eng3d', uint16_t), + ('cls_m2mf', uint16_t), + ('cls_compute', uint16_t), + ('vram_size_B', uint64_t), + ('bar_size_B', uint64_t), ] +class struct_nak_compiler(Struct): pass +# struct nak_compiler *nak_compiler_create(const struct nv_device_info *dev) +try: (nak_compiler_create:=dll.nak_compiler_create).restype, nak_compiler_create.argtypes = ctypes.POINTER(struct_nak_compiler), [ctypes.POINTER(struct_nv_device_info)] +except AttributeError: pass -try: - nv_device_uuid = _libraries['FIXME_STUB'].nv_device_uuid - nv_device_uuid.restype = None - nv_device_uuid.argtypes = [ctypes.POINTER(struct_nv_device_info), ctypes.POINTER(ctypes.c_ubyte), size_t, ctypes.c_bool] -except AttributeError: - pass -class struct_nak_compiler(Structure): - pass +# void nak_compiler_destroy(struct nak_compiler *nak) +try: (nak_compiler_destroy:=dll.nak_compiler_destroy).restype, nak_compiler_destroy.argtypes = None, [ctypes.POINTER(struct_nak_compiler)] +except AttributeError: pass -try: - nak_compiler_create = _libraries['libtinymesa_cpu.so'].nak_compiler_create - nak_compiler_create.restype = ctypes.POINTER(struct_nak_compiler) - nak_compiler_create.argtypes = [ctypes.POINTER(struct_nv_device_info)] -except AttributeError: - pass -try: - nak_compiler_destroy = _libraries['libtinymesa_cpu.so'].nak_compiler_destroy - nak_compiler_destroy.restype = None - nak_compiler_destroy.argtypes = [ctypes.POINTER(struct_nak_compiler)] -except AttributeError: - pass -try: - nak_debug_flags = _libraries['libtinymesa_cpu.so'].nak_debug_flags - nak_debug_flags.restype = uint64_t - nak_debug_flags.argtypes = [ctypes.POINTER(struct_nak_compiler)] -except AttributeError: - pass -try: - nak_nir_options = _libraries['libtinymesa_cpu.so'].nak_nir_options - nak_nir_options.restype = ctypes.POINTER(struct_nir_shader_compiler_options) - nak_nir_options.argtypes = [ctypes.POINTER(struct_nak_compiler)] -except AttributeError: - pass -try: - nak_preprocess_nir = _libraries['libtinymesa_cpu.so'].nak_preprocess_nir - nak_preprocess_nir.restype = None - nak_preprocess_nir.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nak_compiler)] -except AttributeError: - pass -try: - nak_nir_lower_image_addrs = _libraries['FIXME_STUB'].nak_nir_lower_image_addrs - nak_nir_lower_image_addrs.restype = ctypes.c_bool - nak_nir_lower_image_addrs.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nak_compiler)] -except AttributeError: - pass -class struct_nak_sample_location(Structure): - pass +# uint64_t nak_debug_flags(const struct nak_compiler *nak) +try: (nak_debug_flags:=dll.nak_debug_flags).restype, nak_debug_flags.argtypes = uint64_t, [ctypes.POINTER(struct_nak_compiler)] +except AttributeError: pass -struct_nak_sample_location._pack_ = 1 # source:False +# const struct nir_shader_compiler_options *nak_nir_options(const struct nak_compiler *nak) +try: (nak_nir_options:=dll.nak_nir_options).restype, nak_nir_options.argtypes = ctypes.POINTER(struct_nir_shader_compiler_options), [ctypes.POINTER(struct_nak_compiler)] +except AttributeError: pass + +# void nak_preprocess_nir(nir_shader *nir, const struct nak_compiler *nak) +try: (nak_preprocess_nir:=dll.nak_preprocess_nir).restype, nak_preprocess_nir.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_nak_compiler)] +except AttributeError: pass + +# bool nak_nir_lower_image_addrs(nir_shader *nir, const struct nak_compiler *nak) +try: (nak_nir_lower_image_addrs:=dll.nak_nir_lower_image_addrs).restype, nak_nir_lower_image_addrs.argtypes = ctypes.c_bool, [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_nak_compiler)] +except AttributeError: pass + +class struct_nak_sample_location(Struct): pass struct_nak_sample_location._fields_ = [ - ('x_u4', ctypes.c_ubyte, 4), - ('y_u4', ctypes.c_ubyte, 4), + ('x_u4', uint8_t,4), + ('y_u4', uint8_t,4), ] - -class struct_nak_sample_mask(Structure): - pass - -struct_nak_sample_mask._pack_ = 1 # source:False +class struct_nak_sample_mask(Struct): pass struct_nak_sample_mask._fields_ = [ - ('sample_mask', ctypes.c_uint16), + ('sample_mask', uint16_t), ] - -class struct_nak_fs_key(Structure): - pass - -struct_nak_fs_key._pack_ = 1 # source:False +class struct_nak_fs_key(Struct): pass struct_nak_fs_key._fields_ = [ - ('zs_self_dep', ctypes.c_bool), - ('force_sample_shading', ctypes.c_bool), - ('uses_underestimate', ctypes.c_bool), - ('sample_info_cb', ctypes.c_ubyte), - ('sample_locations_offset', ctypes.c_uint32), - ('sample_masks_offset', ctypes.c_uint32), + ('zs_self_dep', ctypes.c_bool), + ('force_sample_shading', ctypes.c_bool), + ('uses_underestimate', ctypes.c_bool), + ('sample_info_cb', uint8_t), + ('sample_locations_offset', uint32_t), + ('sample_masks_offset', uint32_t), ] +# void nak_postprocess_nir(nir_shader *nir, const struct nak_compiler *nak, nir_variable_mode robust2_modes, const struct nak_fs_key *fs_key) +try: (nak_postprocess_nir:=dll.nak_postprocess_nir).restype, nak_postprocess_nir.argtypes = None, [ctypes.POINTER(nir_shader), ctypes.POINTER(struct_nak_compiler), nir_variable_mode, ctypes.POINTER(struct_nak_fs_key)] +except AttributeError: pass -try: - nak_postprocess_nir = _libraries['libtinymesa_cpu.so'].nak_postprocess_nir - nak_postprocess_nir.restype = None - nak_postprocess_nir.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nak_compiler), nir_variable_mode, ctypes.POINTER(struct_nak_fs_key)] -except AttributeError: - pass +enum_nak_ts_domain = CEnum(ctypes.c_ubyte) +NAK_TS_DOMAIN_ISOLINE = enum_nak_ts_domain.define('NAK_TS_DOMAIN_ISOLINE', 0) +NAK_TS_DOMAIN_TRIANGLE = enum_nak_ts_domain.define('NAK_TS_DOMAIN_TRIANGLE', 1) +NAK_TS_DOMAIN_QUAD = enum_nak_ts_domain.define('NAK_TS_DOMAIN_QUAD', 2) -# values for enumeration 'nak_ts_domain' -nak_ts_domain__enumvalues = { - 0: 'NAK_TS_DOMAIN_ISOLINE', - 1: 'NAK_TS_DOMAIN_TRIANGLE', - 2: 'NAK_TS_DOMAIN_QUAD', -} -NAK_TS_DOMAIN_ISOLINE = 0 -NAK_TS_DOMAIN_TRIANGLE = 1 -NAK_TS_DOMAIN_QUAD = 2 -nak_ts_domain = ctypes.c_uint32 # enum +enum_nak_ts_spacing = CEnum(ctypes.c_ubyte) +NAK_TS_SPACING_INTEGER = enum_nak_ts_spacing.define('NAK_TS_SPACING_INTEGER', 0) +NAK_TS_SPACING_FRACT_ODD = enum_nak_ts_spacing.define('NAK_TS_SPACING_FRACT_ODD', 1) +NAK_TS_SPACING_FRACT_EVEN = enum_nak_ts_spacing.define('NAK_TS_SPACING_FRACT_EVEN', 2) -# values for enumeration 'nak_ts_spacing' -nak_ts_spacing__enumvalues = { - 0: 'NAK_TS_SPACING_INTEGER', - 1: 'NAK_TS_SPACING_FRACT_ODD', - 2: 'NAK_TS_SPACING_FRACT_EVEN', -} -NAK_TS_SPACING_INTEGER = 0 -NAK_TS_SPACING_FRACT_ODD = 1 -NAK_TS_SPACING_FRACT_EVEN = 2 -nak_ts_spacing = ctypes.c_uint32 # enum +enum_nak_ts_prims = CEnum(ctypes.c_ubyte) +NAK_TS_PRIMS_POINTS = enum_nak_ts_prims.define('NAK_TS_PRIMS_POINTS', 0) +NAK_TS_PRIMS_LINES = enum_nak_ts_prims.define('NAK_TS_PRIMS_LINES', 1) +NAK_TS_PRIMS_TRIANGLES_CW = enum_nak_ts_prims.define('NAK_TS_PRIMS_TRIANGLES_CW', 2) +NAK_TS_PRIMS_TRIANGLES_CCW = enum_nak_ts_prims.define('NAK_TS_PRIMS_TRIANGLES_CCW', 3) -# values for enumeration 'nak_ts_prims' -nak_ts_prims__enumvalues = { - 0: 'NAK_TS_PRIMS_POINTS', - 1: 'NAK_TS_PRIMS_LINES', - 2: 'NAK_TS_PRIMS_TRIANGLES_CW', - 3: 'NAK_TS_PRIMS_TRIANGLES_CCW', -} -NAK_TS_PRIMS_POINTS = 0 -NAK_TS_PRIMS_LINES = 1 -NAK_TS_PRIMS_TRIANGLES_CW = 2 -NAK_TS_PRIMS_TRIANGLES_CCW = 3 -nak_ts_prims = ctypes.c_uint32 # enum -class struct_nak_xfb_info(Structure): - pass - -struct_nak_xfb_info._pack_ = 1 # source:False +class struct_nak_xfb_info(Struct): pass struct_nak_xfb_info._fields_ = [ - ('stride', ctypes.c_uint32 * 4), - ('stream', ctypes.c_ubyte * 4), - ('attr_count', ctypes.c_ubyte * 4), - ('attr_index', ctypes.c_ubyte * 128 * 4), + ('stride', (uint32_t * 4)), + ('stream', (uint8_t * 4)), + ('attr_count', (uint8_t * 4)), + ('attr_index', ((uint8_t * 128) * 4)), ] - -class struct_nak_shader_info(Structure): - pass - -class union_nak_shader_info_0(Union): - pass - -class struct_nak_shader_info_0_cs(Structure): - pass - -struct_nak_shader_info_0_cs._pack_ = 1 # source:False +class struct_nak_shader_info(Struct): pass +class struct_nak_shader_info_0(ctypes.Union): pass +class struct_nak_shader_info_0_cs(Struct): pass struct_nak_shader_info_0_cs._fields_ = [ - ('local_size', ctypes.c_uint16 * 3), - ('smem_size', ctypes.c_uint16), - ('_pad', ctypes.c_ubyte * 4), + ('local_size', (uint16_t * 3)), + ('smem_size', uint16_t), + ('_pad', (uint8_t * 4)), ] - -class struct_nak_shader_info_0_fs(Structure): - pass - -struct_nak_shader_info_0_fs._pack_ = 1 # source:False +class struct_nak_shader_info_0_fs(Struct): pass struct_nak_shader_info_0_fs._fields_ = [ - ('writes_depth', ctypes.c_bool), - ('reads_sample_mask', ctypes.c_bool), - ('post_depth_coverage', ctypes.c_bool), - ('uses_sample_shading', ctypes.c_bool), - ('early_fragment_tests', ctypes.c_bool), - ('_pad', ctypes.c_ubyte * 7), + ('writes_depth', ctypes.c_bool), + ('reads_sample_mask', ctypes.c_bool), + ('post_depth_coverage', ctypes.c_bool), + ('uses_sample_shading', ctypes.c_bool), + ('early_fragment_tests', ctypes.c_bool), + ('_pad', (uint8_t * 7)), ] - -class struct_nak_shader_info_0_ts(Structure): - pass - -struct_nak_shader_info_0_ts._pack_ = 1 # source:False +class struct_nak_shader_info_0_ts(Struct): pass struct_nak_shader_info_0_ts._fields_ = [ - ('domain', ctypes.c_ubyte), - ('spacing', ctypes.c_ubyte), - ('prims', ctypes.c_ubyte), - ('_pad', ctypes.c_ubyte * 9), + ('domain', enum_nak_ts_domain), + ('spacing', enum_nak_ts_spacing), + ('prims', enum_nak_ts_prims), + ('_pad', (uint8_t * 9)), ] - -union_nak_shader_info_0._pack_ = 1 # source:False -union_nak_shader_info_0._fields_ = [ - ('cs', struct_nak_shader_info_0_cs), - ('fs', struct_nak_shader_info_0_fs), - ('ts', struct_nak_shader_info_0_ts), - ('_pad', ctypes.c_ubyte * 12), +struct_nak_shader_info_0._fields_ = [ + ('cs', struct_nak_shader_info_0_cs), + ('fs', struct_nak_shader_info_0_fs), + ('ts', struct_nak_shader_info_0_ts), + ('_pad', (uint8_t * 12)), ] - -class struct_nak_shader_info_vtg(Structure): - pass - -struct_nak_shader_info_vtg._pack_ = 1 # source:False +class struct_nak_shader_info_vtg(Struct): pass struct_nak_shader_info_vtg._fields_ = [ - ('writes_layer', ctypes.c_bool), - ('writes_point_size', ctypes.c_bool), - ('writes_vprs_table_index', ctypes.c_bool), - ('clip_enable', ctypes.c_ubyte), - ('cull_enable', ctypes.c_ubyte), - ('_pad', ctypes.c_ubyte * 3), - ('xfb', struct_nak_xfb_info), + ('writes_layer', ctypes.c_bool), + ('writes_point_size', ctypes.c_bool), + ('writes_vprs_table_index', ctypes.c_bool), + ('clip_enable', uint8_t), + ('cull_enable', uint8_t), + ('_pad', (uint8_t * 3)), + ('xfb', struct_nak_xfb_info), ] - -struct_nak_shader_info._pack_ = 1 # source:False -struct_nak_shader_info._anonymous_ = ('_0',) +struct_nak_shader_info._anonymous_ = ['_0'] struct_nak_shader_info._fields_ = [ - ('stage', gl_shader_stage), - ('sm', ctypes.c_ubyte), - ('num_gprs', ctypes.c_ubyte), - ('num_control_barriers', ctypes.c_ubyte), - ('_pad0', ctypes.c_ubyte), - ('max_warps_per_sm', ctypes.c_uint32), - ('num_instrs', ctypes.c_uint32), - ('num_static_cycles', ctypes.c_uint32), - ('num_spills_to_mem', ctypes.c_uint32), - ('num_fills_from_mem', ctypes.c_uint32), - ('num_spills_to_reg', ctypes.c_uint32), - ('num_fills_from_reg', ctypes.c_uint32), - ('slm_size', ctypes.c_uint32), - ('crs_size', ctypes.c_uint32), - ('_0', union_nak_shader_info_0), - ('vtg', struct_nak_shader_info_vtg), - ('hdr', ctypes.c_uint32 * 32), + ('stage', gl_shader_stage), + ('sm', uint8_t), + ('num_gprs', uint8_t), + ('num_control_barriers', uint8_t), + ('_pad0', uint8_t), + ('max_warps_per_sm', uint32_t), + ('num_instrs', uint32_t), + ('num_static_cycles', uint32_t), + ('num_spills_to_mem', uint32_t), + ('num_fills_from_mem', uint32_t), + ('num_spills_to_reg', uint32_t), + ('num_fills_from_reg', uint32_t), + ('slm_size', uint32_t), + ('crs_size', uint32_t), + ('_0', struct_nak_shader_info_0), + ('vtg', struct_nak_shader_info_vtg), + ('hdr', (uint32_t * 32)), ] - -class struct_nak_shader_bin(Structure): - pass - -struct_nak_shader_bin._pack_ = 1 # source:False +class struct_nak_shader_bin(Struct): pass struct_nak_shader_bin._fields_ = [ - ('info', struct_nak_shader_info), - ('code_size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('code', ctypes.POINTER(None)), - ('asm_str', ctypes.POINTER(ctypes.c_char)), + ('info', struct_nak_shader_info), + ('code_size', uint32_t), + ('code', ctypes.c_void_p), + ('asm_str', ctypes.POINTER(ctypes.c_char)), ] +# void nak_shader_bin_destroy(struct nak_shader_bin *bin) +try: (nak_shader_bin_destroy:=dll.nak_shader_bin_destroy).restype, nak_shader_bin_destroy.argtypes = None, [ctypes.POINTER(struct_nak_shader_bin)] +except AttributeError: pass -try: - nak_shader_bin_destroy = _libraries['libtinymesa_cpu.so'].nak_shader_bin_destroy - nak_shader_bin_destroy.restype = None - nak_shader_bin_destroy.argtypes = [ctypes.POINTER(struct_nak_shader_bin)] -except AttributeError: - pass -try: - nak_compile_shader = _libraries['libtinymesa_cpu.so'].nak_compile_shader - nak_compile_shader.restype = ctypes.POINTER(struct_nak_shader_bin) - nak_compile_shader.argtypes = [ctypes.POINTER(struct_nir_shader), ctypes.c_bool, ctypes.POINTER(struct_nak_compiler), nir_variable_mode, ctypes.POINTER(struct_nak_fs_key)] -except AttributeError: - pass -class struct_nak_qmd_cbuf(Structure): - pass +# struct nak_shader_bin *nak_compile_shader(nir_shader *nir, bool dump_asm, const struct nak_compiler *nak, nir_variable_mode robust2_modes, const struct nak_fs_key *fs_key) +try: (nak_compile_shader:=dll.nak_compile_shader).restype, nak_compile_shader.argtypes = ctypes.POINTER(struct_nak_shader_bin), [ctypes.POINTER(nir_shader), ctypes.c_bool, ctypes.POINTER(struct_nak_compiler), nir_variable_mode, ctypes.POINTER(struct_nak_fs_key)] +except AttributeError: pass -struct_nak_qmd_cbuf._pack_ = 1 # source:False +class struct_nak_qmd_cbuf(Struct): pass struct_nak_qmd_cbuf._fields_ = [ - ('index', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('addr', ctypes.c_uint64), + ('index', uint32_t), + ('size', uint32_t), + ('addr', uint64_t), ] - -class struct_nak_qmd_info(Structure): - pass - -struct_nak_qmd_info._pack_ = 1 # source:False +class struct_nak_qmd_info(Struct): pass struct_nak_qmd_info._fields_ = [ - ('addr', ctypes.c_uint64), - ('smem_size', ctypes.c_uint16), - ('smem_max', ctypes.c_uint16), - ('global_size', ctypes.c_uint32 * 3), - ('num_cbufs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('cbufs', struct_nak_qmd_cbuf * 8), + ('addr', uint64_t), + ('smem_size', uint16_t), + ('smem_max', uint16_t), + ('global_size', (uint32_t * 3)), + ('num_cbufs', uint32_t), + ('cbufs', (struct_nak_qmd_cbuf * 8)), ] +# uint32_t nak_qmd_size_B(const struct nv_device_info *dev) +try: (nak_qmd_size_B:=dll.nak_qmd_size_B).restype, nak_qmd_size_B.argtypes = uint32_t, [ctypes.POINTER(struct_nv_device_info)] +except AttributeError: pass -try: - nak_qmd_size_B = _libraries['libtinymesa_cpu.so'].nak_qmd_size_B - nak_qmd_size_B.restype = uint32_t - nak_qmd_size_B.argtypes = [ctypes.POINTER(struct_nv_device_info)] -except AttributeError: - pass -try: - nak_fill_qmd = _libraries['libtinymesa_cpu.so'].nak_fill_qmd - nak_fill_qmd.restype = None - nak_fill_qmd.argtypes = [ctypes.POINTER(struct_nv_device_info), ctypes.POINTER(struct_nak_shader_info), ctypes.POINTER(struct_nak_qmd_info), ctypes.POINTER(None), size_t] -except AttributeError: - pass -class struct_nak_qmd_dispatch_size_layout(Structure): - pass +# void nak_fill_qmd(const struct nv_device_info *dev, const struct nak_shader_info *info, const struct nak_qmd_info *qmd_info, void *qmd_out, size_t qmd_size) +try: (nak_fill_qmd:=dll.nak_fill_qmd).restype, nak_fill_qmd.argtypes = None, [ctypes.POINTER(struct_nv_device_info), ctypes.POINTER(struct_nak_shader_info), ctypes.POINTER(struct_nak_qmd_info), ctypes.c_void_p, size_t] +except AttributeError: pass -struct_nak_qmd_dispatch_size_layout._pack_ = 1 # source:False +class struct_nak_qmd_dispatch_size_layout(Struct): pass struct_nak_qmd_dispatch_size_layout._fields_ = [ - ('x_start', ctypes.c_uint16), - ('x_end', ctypes.c_uint16), - ('y_start', ctypes.c_uint16), - ('y_end', ctypes.c_uint16), - ('z_start', ctypes.c_uint16), - ('z_end', ctypes.c_uint16), + ('x_start', uint16_t), + ('x_end', uint16_t), + ('y_start', uint16_t), + ('y_end', uint16_t), + ('z_start', uint16_t), + ('z_end', uint16_t), ] +# struct nak_qmd_dispatch_size_layout nak_get_qmd_dispatch_size_layout(const struct nv_device_info *dev) +try: (nak_get_qmd_dispatch_size_layout:=dll.nak_get_qmd_dispatch_size_layout).restype, nak_get_qmd_dispatch_size_layout.argtypes = struct_nak_qmd_dispatch_size_layout, [ctypes.POINTER(struct_nv_device_info)] +except AttributeError: pass -try: - nak_get_qmd_dispatch_size_layout = _libraries['libtinymesa_cpu.so'].nak_get_qmd_dispatch_size_layout - nak_get_qmd_dispatch_size_layout.restype = struct_nak_qmd_dispatch_size_layout - nak_get_qmd_dispatch_size_layout.argtypes = [ctypes.POINTER(struct_nv_device_info)] -except AttributeError: - pass -class struct_nak_qmd_cbuf_desc_layout(Structure): - pass - -struct_nak_qmd_cbuf_desc_layout._pack_ = 1 # source:False +class struct_nak_qmd_cbuf_desc_layout(Struct): pass struct_nak_qmd_cbuf_desc_layout._fields_ = [ - ('addr_shift', ctypes.c_uint16), - ('addr_lo_start', ctypes.c_uint16), - ('addr_lo_end', ctypes.c_uint16), - ('addr_hi_start', ctypes.c_uint16), - ('addr_hi_end', ctypes.c_uint16), + ('addr_shift', uint16_t), + ('addr_lo_start', uint16_t), + ('addr_lo_end', uint16_t), + ('addr_hi_start', uint16_t), + ('addr_hi_end', uint16_t), ] +# struct nak_qmd_cbuf_desc_layout nak_get_qmd_cbuf_desc_layout(const struct nv_device_info *dev, uint8_t idx) +try: (nak_get_qmd_cbuf_desc_layout:=dll.nak_get_qmd_cbuf_desc_layout).restype, nak_get_qmd_cbuf_desc_layout.argtypes = struct_nak_qmd_cbuf_desc_layout, [ctypes.POINTER(struct_nv_device_info), uint8_t] +except AttributeError: pass -try: - nak_get_qmd_cbuf_desc_layout = _libraries['libtinymesa_cpu.so'].nak_get_qmd_cbuf_desc_layout - nak_get_qmd_cbuf_desc_layout.restype = struct_nak_qmd_cbuf_desc_layout - nak_get_qmd_cbuf_desc_layout.argtypes = [ctypes.POINTER(struct_nv_device_info), uint8_t] -except AttributeError: - pass -class struct_lp_context_ref(Structure): - pass - -class struct_LLVMOpaqueContext(Structure): - pass - -struct_lp_context_ref._pack_ = 1 # source:False +class struct_lp_context_ref(Struct): pass +class struct_LLVMOpaqueContext(Struct): pass +LLVMContextRef = ctypes.POINTER(struct_LLVMOpaqueContext) struct_lp_context_ref._fields_ = [ - ('ref', ctypes.POINTER(struct_LLVMOpaqueContext)), - ('owned', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), + ('ref', LLVMContextRef), + ('owned', ctypes.c_bool), ] - lp_context_ref = struct_lp_context_ref -try: - lp_context_create = _libraries['FIXME_STUB'].lp_context_create - lp_context_create.restype = None - lp_context_create.argtypes = [ctypes.POINTER(struct_lp_context_ref)] -except AttributeError: - pass -try: - lp_context_destroy = _libraries['FIXME_STUB'].lp_context_destroy - lp_context_destroy.restype = None - lp_context_destroy.argtypes = [ctypes.POINTER(struct_lp_context_ref)] -except AttributeError: - pass -class struct_lp_passmgr(Structure): - pass - -class struct_LLVMOpaqueModule(Structure): - pass - +class struct_lp_passmgr(Struct): pass +class struct_LLVMOpaqueModule(Struct): pass LLVMModuleRef = ctypes.POINTER(struct_LLVMOpaqueModule) -try: - lp_passmgr_create = _libraries['libtinymesa_cpu.so'].lp_passmgr_create - lp_passmgr_create.restype = ctypes.c_bool - lp_passmgr_create.argtypes = [LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(struct_lp_passmgr))] -except AttributeError: - pass -class struct_LLVMOpaqueTargetMachine(Structure): - pass +# _Bool lp_passmgr_create(LLVMModuleRef module, struct lp_passmgr **mgr) +try: (lp_passmgr_create:=dll.lp_passmgr_create).restype, lp_passmgr_create.argtypes = ctypes.c_bool, [LLVMModuleRef, ctypes.POINTER(ctypes.POINTER(struct_lp_passmgr))] +except AttributeError: pass +class struct_LLVMOpaqueTargetMachine(Struct): pass LLVMTargetMachineRef = ctypes.POINTER(struct_LLVMOpaqueTargetMachine) -try: - lp_passmgr_run = _libraries['libtinymesa_cpu.so'].lp_passmgr_run - lp_passmgr_run.restype = None - lp_passmgr_run.argtypes = [ctypes.POINTER(struct_lp_passmgr), LLVMModuleRef, LLVMTargetMachineRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_passmgr_dispose = _libraries['libtinymesa_cpu.so'].lp_passmgr_dispose - lp_passmgr_dispose.restype = None - lp_passmgr_dispose.argtypes = [ctypes.POINTER(struct_lp_passmgr)] -except AttributeError: - pass -class struct_lp_cached_code(Structure): - pass +# void lp_passmgr_run(struct lp_passmgr *mgr, LLVMModuleRef module, LLVMTargetMachineRef tm, const char *module_name) +try: (lp_passmgr_run:=dll.lp_passmgr_run).restype, lp_passmgr_run.argtypes = None, [ctypes.POINTER(struct_lp_passmgr), LLVMModuleRef, LLVMTargetMachineRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -struct_lp_cached_code._pack_ = 1 # source:False +# void lp_passmgr_dispose(struct lp_passmgr *mgr) +try: (lp_passmgr_dispose:=dll.lp_passmgr_dispose).restype, lp_passmgr_dispose.argtypes = None, [ctypes.POINTER(struct_lp_passmgr)] +except AttributeError: pass + +class struct_lp_cached_code(Struct): pass struct_lp_cached_code._fields_ = [ - ('data', ctypes.POINTER(None)), - ('data_size', ctypes.c_uint64), - ('dont_cache', ctypes.c_bool), - ('PADDING_0', ctypes.c_ubyte * 7), - ('jit_obj_cache', ctypes.POINTER(None)), + ('data', ctypes.c_void_p), + ('data_size', size_t), + ('dont_cache', ctypes.c_bool), + ('jit_obj_cache', ctypes.c_void_p), ] - -class struct_lp_generated_code(Structure): - pass - -class struct_LLVMOpaqueTargetLibraryInfotData(Structure): - pass - +class struct_lp_generated_code(Struct): pass +class struct_LLVMOpaqueTargetLibraryInfotData(Struct): pass LLVMTargetLibraryInfoRef = ctypes.POINTER(struct_LLVMOpaqueTargetLibraryInfotData) -try: - gallivm_create_target_library_info = _libraries['libtinymesa_cpu.so'].gallivm_create_target_library_info - gallivm_create_target_library_info.restype = LLVMTargetLibraryInfoRef - gallivm_create_target_library_info.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - gallivm_dispose_target_library_info = _libraries['libtinymesa_cpu.so'].gallivm_dispose_target_library_info - gallivm_dispose_target_library_info.restype = None - gallivm_dispose_target_library_info.argtypes = [LLVMTargetLibraryInfoRef] -except AttributeError: - pass -try: - lp_set_target_options = _libraries['libtinymesa_cpu.so'].lp_set_target_options - lp_set_target_options.restype = None - lp_set_target_options.argtypes = [] -except AttributeError: - pass -try: - lp_bld_init_native_targets = _libraries['libtinymesa_cpu.so'].lp_bld_init_native_targets - lp_bld_init_native_targets.restype = None - lp_bld_init_native_targets.argtypes = [] -except AttributeError: - pass -class struct_LLVMOpaqueExecutionEngine(Structure): - pass +# extern LLVMTargetLibraryInfoRef gallivm_create_target_library_info(const char *triple) +try: (gallivm_create_target_library_info:=dll.gallivm_create_target_library_info).restype, gallivm_create_target_library_info.argtypes = LLVMTargetLibraryInfoRef, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass -class struct_LLVMOpaqueMCJITMemoryManager(Structure): - pass +# extern void gallivm_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info) +try: (gallivm_dispose_target_library_info:=dll.gallivm_dispose_target_library_info).restype, gallivm_dispose_target_library_info.argtypes = None, [LLVMTargetLibraryInfoRef] +except AttributeError: pass +# extern void lp_set_target_options(void) +try: (lp_set_target_options:=dll.lp_set_target_options).restype, lp_set_target_options.argtypes = None, [] +except AttributeError: pass + +# extern void lp_bld_init_native_targets() +try: (lp_bld_init_native_targets:=dll.lp_bld_init_native_targets).restype, lp_bld_init_native_targets.argtypes = None, [] +except AttributeError: pass + +class struct_LLVMOpaqueExecutionEngine(Struct): pass +LLVMExecutionEngineRef = ctypes.POINTER(struct_LLVMOpaqueExecutionEngine) +class struct_LLVMOpaqueMCJITMemoryManager(Struct): pass LLVMMCJITMemoryManagerRef = ctypes.POINTER(struct_LLVMOpaqueMCJITMemoryManager) -try: - lp_build_create_jit_compiler_for_module = _libraries['libtinymesa_cpu.so'].lp_build_create_jit_compiler_for_module - lp_build_create_jit_compiler_for_module.restype = ctypes.c_int32 - lp_build_create_jit_compiler_for_module.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), ctypes.POINTER(ctypes.POINTER(struct_lp_generated_code)), ctypes.POINTER(struct_lp_cached_code), LLVMModuleRef, LLVMMCJITMemoryManagerRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - lp_free_generated_code = _libraries['libtinymesa_cpu.so'].lp_free_generated_code - lp_free_generated_code.restype = None - lp_free_generated_code.argtypes = [ctypes.POINTER(struct_lp_generated_code)] -except AttributeError: - pass -try: - lp_get_default_memory_manager = _libraries['libtinymesa_cpu.so'].lp_get_default_memory_manager - lp_get_default_memory_manager.restype = LLVMMCJITMemoryManagerRef - lp_get_default_memory_manager.argtypes = [] -except AttributeError: - pass -try: - lp_free_memory_manager = _libraries['libtinymesa_cpu.so'].lp_free_memory_manager - lp_free_memory_manager.restype = None - lp_free_memory_manager.argtypes = [LLVMMCJITMemoryManagerRef] -except AttributeError: - pass -class struct_LLVMOpaqueValue(Structure): - pass +# extern int lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, struct lp_generated_code **OutCode, struct lp_cached_code *cache_out, LLVMModuleRef M, LLVMMCJITMemoryManagerRef MM, unsigned int OptLevel, char **OutError) +try: (lp_build_create_jit_compiler_for_module:=dll.lp_build_create_jit_compiler_for_module).restype, lp_build_create_jit_compiler_for_module.argtypes = ctypes.c_int32, [ctypes.POINTER(LLVMExecutionEngineRef), ctypes.POINTER(ctypes.POINTER(struct_lp_generated_code)), ctypes.POINTER(struct_lp_cached_code), LLVMModuleRef, LLVMMCJITMemoryManagerRef, ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass +# extern void lp_free_generated_code(struct lp_generated_code *code) +try: (lp_free_generated_code:=dll.lp_free_generated_code).restype, lp_free_generated_code.argtypes = None, [ctypes.POINTER(struct_lp_generated_code)] +except AttributeError: pass + +# extern LLVMMCJITMemoryManagerRef lp_get_default_memory_manager() +try: (lp_get_default_memory_manager:=dll.lp_get_default_memory_manager).restype, lp_get_default_memory_manager.argtypes = LLVMMCJITMemoryManagerRef, [] +except AttributeError: pass + +# extern void lp_free_memory_manager(LLVMMCJITMemoryManagerRef memorymgr) +try: (lp_free_memory_manager:=dll.lp_free_memory_manager).restype, lp_free_memory_manager.argtypes = None, [LLVMMCJITMemoryManagerRef] +except AttributeError: pass + +class struct_LLVMOpaqueValue(Struct): pass LLVMValueRef = ctypes.POINTER(struct_LLVMOpaqueValue) -try: - lp_get_called_value = _libraries['libtinymesa_cpu.so'].lp_get_called_value - lp_get_called_value.restype = LLVMValueRef - lp_get_called_value.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - lp_is_function = _libraries['libtinymesa_cpu.so'].lp_is_function - lp_is_function.restype = ctypes.c_bool - lp_is_function.argtypes = [LLVMValueRef] -except AttributeError: - pass -try: - lp_free_objcache = _libraries['libtinymesa_cpu.so'].lp_free_objcache - lp_free_objcache.restype = None - lp_free_objcache.argtypes = [ctypes.POINTER(None)] -except AttributeError: - pass -try: - lp_set_module_stack_alignment_override = _libraries['libtinymesa_cpu.so'].lp_set_module_stack_alignment_override - lp_set_module_stack_alignment_override.restype = None - lp_set_module_stack_alignment_override.argtypes = [LLVMModuleRef, ctypes.c_uint32] -except AttributeError: - pass -lp_native_vector_width = 0 # Variable ctypes.c_uint32 -class struct_lp_type(Structure): - pass +# extern LLVMValueRef lp_get_called_value(LLVMValueRef call) +try: (lp_get_called_value:=dll.lp_get_called_value).restype, lp_get_called_value.argtypes = LLVMValueRef, [LLVMValueRef] +except AttributeError: pass -struct_lp_type._pack_ = 1 # source:False +# extern bool lp_is_function(LLVMValueRef v) +try: (lp_is_function:=dll.lp_is_function).restype, lp_is_function.argtypes = ctypes.c_bool, [LLVMValueRef] +except AttributeError: pass + +# void lp_free_objcache(void *objcache) +try: (lp_free_objcache:=dll.lp_free_objcache).restype, lp_free_objcache.argtypes = None, [ctypes.c_void_p] +except AttributeError: pass + +# void lp_set_module_stack_alignment_override(LLVMModuleRef M, unsigned int align) +try: (lp_set_module_stack_alignment_override:=dll.lp_set_module_stack_alignment_override).restype, lp_set_module_stack_alignment_override.argtypes = None, [LLVMModuleRef, ctypes.c_uint32] +except AttributeError: pass + +try: lp_native_vector_width = ctypes.c_uint32.in_dll(dll, 'lp_native_vector_width') +except (ValueError,AttributeError): pass +class struct_lp_type(Struct): pass struct_lp_type._fields_ = [ - ('floating', ctypes.c_uint64, 1), - ('fixed', ctypes.c_uint64, 1), - ('sign', ctypes.c_uint64, 1), - ('norm', ctypes.c_uint64, 1), - ('signed_zero_preserve', ctypes.c_uint64, 1), - ('nan_preserve', ctypes.c_uint64, 1), - ('width', ctypes.c_uint64, 14), - ('PADDING_0', ctypes.c_uint16, 12), - ('length', ctypes.c_uint64, 14), - ('PADDING_1', ctypes.c_uint32, 18), + ('floating', ctypes.c_uint32,1), + ('fixed', ctypes.c_uint32,1), + ('sign', ctypes.c_uint32,1), + ('norm', ctypes.c_uint32,1), + ('signed_zero_preserve', ctypes.c_uint32,1), + ('nan_preserve', ctypes.c_uint32,1), + ('width', ctypes.c_uint32,14), + ('length', ctypes.c_uint32,14), ] - -class struct_lp_build_context(Structure): - pass - -class struct_gallivm_state(Structure): - pass - -class struct_LLVMOpaqueType(Structure): - pass - -struct_lp_build_context._pack_ = 1 # source:False -struct_lp_build_context._fields_ = [ - ('gallivm', ctypes.POINTER(struct_gallivm_state)), - ('type', struct_lp_type), - ('elem_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('vec_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('int_elem_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('int_vec_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('undef', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('zero', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('one', ctypes.POINTER(struct_LLVMOpaqueValue)), -] - -class struct_LLVMOpaqueTargetData(Structure): - pass - -class struct_LLVMOpaqueBuilder(Structure): - pass - -class struct_LLVMOpaqueDIBuilder(Structure): - pass - -class struct_LLVMOpaqueMetadata(Structure): - pass - -class struct_lp_jit_texture(Structure): - pass - -struct_gallivm_state._pack_ = 1 # source:False -struct_gallivm_state._fields_ = [ - ('module_name', ctypes.POINTER(ctypes.c_char)), - ('file_name', ctypes.POINTER(ctypes.c_char)), - ('module', ctypes.POINTER(struct_LLVMOpaqueModule)), - ('target', ctypes.POINTER(struct_LLVMOpaqueTargetData)), - ('engine', ctypes.POINTER(struct_LLVMOpaqueExecutionEngine)), - ('passmgr', ctypes.POINTER(struct_lp_passmgr)), - ('memorymgr', ctypes.POINTER(struct_LLVMOpaqueMCJITMemoryManager)), - ('code', ctypes.POINTER(struct_lp_generated_code)), - ('context', ctypes.POINTER(struct_LLVMOpaqueContext)), - ('builder', ctypes.POINTER(struct_LLVMOpaqueBuilder)), - ('di_builder', ctypes.POINTER(struct_LLVMOpaqueDIBuilder)), - ('cache', ctypes.POINTER(struct_lp_cached_code)), - ('compiled', ctypes.c_uint32), - ('coro_malloc_hook', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('coro_free_hook', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('debug_printf_hook', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('coro_malloc_hook_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('coro_free_hook_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('di_function', ctypes.POINTER(struct_LLVMOpaqueMetadata)), - ('file', ctypes.POINTER(struct_LLVMOpaqueMetadata)), - ('get_time_hook', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('texture_descriptor', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('texture_dynamic_state', ctypes.POINTER(struct_lp_jit_texture)), - ('sampler_descriptor', ctypes.POINTER(struct_LLVMOpaqueValue)), -] - -class struct_util_format_description(Structure): - pass - -class struct_util_format_block(Structure): - pass - -struct_util_format_block._pack_ = 1 # source:False -struct_util_format_block._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depth', ctypes.c_uint32), - ('bits', ctypes.c_uint32), -] - - -# values for enumeration 'util_format_layout' -util_format_layout__enumvalues = { - 0: 'UTIL_FORMAT_LAYOUT_PLAIN', - 1: 'UTIL_FORMAT_LAYOUT_SUBSAMPLED', - 2: 'UTIL_FORMAT_LAYOUT_S3TC', - 3: 'UTIL_FORMAT_LAYOUT_RGTC', - 4: 'UTIL_FORMAT_LAYOUT_ETC', - 5: 'UTIL_FORMAT_LAYOUT_BPTC', - 6: 'UTIL_FORMAT_LAYOUT_ASTC', - 7: 'UTIL_FORMAT_LAYOUT_ATC', - 8: 'UTIL_FORMAT_LAYOUT_PLANAR2', - 9: 'UTIL_FORMAT_LAYOUT_PLANAR3', - 10: 'UTIL_FORMAT_LAYOUT_FXT1', - 11: 'UTIL_FORMAT_LAYOUT_OTHER', -} -UTIL_FORMAT_LAYOUT_PLAIN = 0 -UTIL_FORMAT_LAYOUT_SUBSAMPLED = 1 -UTIL_FORMAT_LAYOUT_S3TC = 2 -UTIL_FORMAT_LAYOUT_RGTC = 3 -UTIL_FORMAT_LAYOUT_ETC = 4 -UTIL_FORMAT_LAYOUT_BPTC = 5 -UTIL_FORMAT_LAYOUT_ASTC = 6 -UTIL_FORMAT_LAYOUT_ATC = 7 -UTIL_FORMAT_LAYOUT_PLANAR2 = 8 -UTIL_FORMAT_LAYOUT_PLANAR3 = 9 -UTIL_FORMAT_LAYOUT_FXT1 = 10 -UTIL_FORMAT_LAYOUT_OTHER = 11 -util_format_layout = ctypes.c_uint32 # enum -class struct_util_format_channel_description(Structure): - pass - -struct_util_format_channel_description._pack_ = 1 # source:False -struct_util_format_channel_description._fields_ = [ - ('type', ctypes.c_uint32, 5), - ('normalized', ctypes.c_uint32, 1), - ('pure_integer', ctypes.c_uint32, 1), - ('size', ctypes.c_uint32, 9), - ('shift', ctypes.c_uint32, 16), -] - - -# values for enumeration 'util_format_colorspace' -util_format_colorspace__enumvalues = { - 0: 'UTIL_FORMAT_COLORSPACE_RGB', - 1: 'UTIL_FORMAT_COLORSPACE_SRGB', - 2: 'UTIL_FORMAT_COLORSPACE_YUV', - 3: 'UTIL_FORMAT_COLORSPACE_ZS', -} -UTIL_FORMAT_COLORSPACE_RGB = 0 -UTIL_FORMAT_COLORSPACE_SRGB = 1 -UTIL_FORMAT_COLORSPACE_YUV = 2 -UTIL_FORMAT_COLORSPACE_ZS = 3 -util_format_colorspace = ctypes.c_uint32 # enum -class union_util_format_description_0(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('srgb_equivalent', pipe_format), - ('linear_equivalent', pipe_format), - ] - -struct_util_format_description._pack_ = 1 # source:False -struct_util_format_description._anonymous_ = ('_0',) -struct_util_format_description._fields_ = [ - ('format', pipe_format), - ('PADDING_0', ctypes.c_ubyte * 4), - ('name', ctypes.POINTER(ctypes.c_char)), - ('short_name', ctypes.POINTER(ctypes.c_char)), - ('block', struct_util_format_block), - ('layout', util_format_layout), - ('nr_channels', ctypes.c_uint32, 3), - ('is_array', ctypes.c_uint32, 1), - ('is_bitmask', ctypes.c_uint32, 1), - ('is_mixed', ctypes.c_uint32, 1), - ('is_unorm', ctypes.c_uint32, 1), - ('is_snorm', ctypes.c_uint32, 1), - ('PADDING_1', ctypes.c_uint32, 24), - ('channel', struct_util_format_channel_description * 4), - ('swizzle', ctypes.c_ubyte * 4), - ('colorspace', util_format_colorspace), - ('_0', union_util_format_description_0), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -try: - lp_type_from_format_desc = _libraries['FIXME_STUB'].lp_type_from_format_desc - lp_type_from_format_desc.restype = None - lp_type_from_format_desc.argtypes = [ctypes.POINTER(struct_lp_type), ctypes.POINTER(struct_util_format_description)] -except AttributeError: - pass -try: - lp_type_from_format = _libraries['FIXME_STUB'].lp_type_from_format - lp_type_from_format.restype = None - lp_type_from_format.argtypes = [ctypes.POINTER(struct_lp_type), pipe_format] -except AttributeError: - pass -try: - lp_type_width = _libraries['FIXME_STUB'].lp_type_width - lp_type_width.restype = ctypes.c_uint32 - lp_type_width.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_type_float = _libraries['FIXME_STUB'].lp_type_float - lp_type_float.restype = struct_lp_type - lp_type_float.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_float_vec = _libraries['FIXME_STUB'].lp_type_float_vec - lp_type_float_vec.restype = struct_lp_type - lp_type_float_vec.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_int = _libraries['FIXME_STUB'].lp_type_int - lp_type_int.restype = struct_lp_type - lp_type_int.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_int_vec = _libraries['FIXME_STUB'].lp_type_int_vec - lp_type_int_vec.restype = struct_lp_type - lp_type_int_vec.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_uint = _libraries['FIXME_STUB'].lp_type_uint - lp_type_uint.restype = struct_lp_type - lp_type_uint.argtypes = [ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_uint_vec = _libraries['FIXME_STUB'].lp_type_uint_vec - lp_type_uint_vec.restype = struct_lp_type - lp_type_uint_vec.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_unorm = _libraries['FIXME_STUB'].lp_type_unorm - lp_type_unorm.restype = struct_lp_type - lp_type_unorm.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_fixed = _libraries['FIXME_STUB'].lp_type_fixed - lp_type_fixed.restype = struct_lp_type - lp_type_fixed.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_type_ufixed = _libraries['FIXME_STUB'].lp_type_ufixed - lp_type_ufixed.restype = struct_lp_type - lp_type_ufixed.argtypes = [ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass +class struct_lp_build_context(Struct): pass +class struct_gallivm_state(Struct): pass +class struct_LLVMOpaqueType(Struct): pass LLVMTypeRef = ctypes.POINTER(struct_LLVMOpaqueType) -try: - lp_build_elem_type = _libraries['libtinymesa_cpu.so'].lp_build_elem_type - lp_build_elem_type.restype = LLVMTypeRef - lp_build_elem_type.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_vec_type = _libraries['libtinymesa_cpu.so'].lp_build_vec_type - lp_build_vec_type.restype = LLVMTypeRef - lp_build_vec_type.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_check_elem_type = _libraries['libtinymesa_cpu.so'].lp_check_elem_type - lp_check_elem_type.restype = ctypes.c_bool - lp_check_elem_type.argtypes = [struct_lp_type, LLVMTypeRef] -except AttributeError: - pass -try: - lp_check_vec_type = _libraries['libtinymesa_cpu.so'].lp_check_vec_type - lp_check_vec_type.restype = ctypes.c_bool - lp_check_vec_type.argtypes = [struct_lp_type, LLVMTypeRef] -except AttributeError: - pass -try: - lp_check_value = _libraries['libtinymesa_cpu.so'].lp_check_value - lp_check_value.restype = ctypes.c_bool - lp_check_value.argtypes = [struct_lp_type, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_int_elem_type = _libraries['libtinymesa_cpu.so'].lp_build_int_elem_type - lp_build_int_elem_type.restype = LLVMTypeRef - lp_build_int_elem_type.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_int_vec_type = _libraries['libtinymesa_cpu.so'].lp_build_int_vec_type - lp_build_int_vec_type.restype = LLVMTypeRef - lp_build_int_vec_type.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_float32_vec4_type = _libraries['FIXME_STUB'].lp_float32_vec4_type - lp_float32_vec4_type.restype = struct_lp_type - lp_float32_vec4_type.argtypes = [] -except AttributeError: - pass -try: - lp_int32_vec4_type = _libraries['FIXME_STUB'].lp_int32_vec4_type - lp_int32_vec4_type.restype = struct_lp_type - lp_int32_vec4_type.argtypes = [] -except AttributeError: - pass -try: - lp_unorm8_vec4_type = _libraries['FIXME_STUB'].lp_unorm8_vec4_type - lp_unorm8_vec4_type.restype = struct_lp_type - lp_unorm8_vec4_type.argtypes = [] -except AttributeError: - pass -try: - lp_elem_type = _libraries['libtinymesa_cpu.so'].lp_elem_type - lp_elem_type.restype = struct_lp_type - lp_elem_type.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_uint_type = _libraries['libtinymesa_cpu.so'].lp_uint_type - lp_uint_type.restype = struct_lp_type - lp_uint_type.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_int_type = _libraries['libtinymesa_cpu.so'].lp_int_type - lp_int_type.restype = struct_lp_type - lp_int_type.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_wider_type = _libraries['libtinymesa_cpu.so'].lp_wider_type - lp_wider_type.restype = struct_lp_type - lp_wider_type.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_sizeof_llvm_type = _libraries['libtinymesa_cpu.so'].lp_sizeof_llvm_type - lp_sizeof_llvm_type.restype = ctypes.c_uint32 - lp_sizeof_llvm_type.argtypes = [LLVMTypeRef] -except AttributeError: - pass - -# values for enumeration 'c__EA_LLVMTypeKind' -c__EA_LLVMTypeKind__enumvalues = { - 0: 'LLVMVoidTypeKind', - 1: 'LLVMHalfTypeKind', - 2: 'LLVMFloatTypeKind', - 3: 'LLVMDoubleTypeKind', - 4: 'LLVMX86_FP80TypeKind', - 5: 'LLVMFP128TypeKind', - 6: 'LLVMPPC_FP128TypeKind', - 7: 'LLVMLabelTypeKind', - 8: 'LLVMIntegerTypeKind', - 9: 'LLVMFunctionTypeKind', - 10: 'LLVMStructTypeKind', - 11: 'LLVMArrayTypeKind', - 12: 'LLVMPointerTypeKind', - 13: 'LLVMVectorTypeKind', - 14: 'LLVMMetadataTypeKind', - 16: 'LLVMTokenTypeKind', - 17: 'LLVMScalableVectorTypeKind', - 18: 'LLVMBFloatTypeKind', - 19: 'LLVMX86_AMXTypeKind', - 20: 'LLVMTargetExtTypeKind', -} -LLVMVoidTypeKind = 0 -LLVMHalfTypeKind = 1 -LLVMFloatTypeKind = 2 -LLVMDoubleTypeKind = 3 -LLVMX86_FP80TypeKind = 4 -LLVMFP128TypeKind = 5 -LLVMPPC_FP128TypeKind = 6 -LLVMLabelTypeKind = 7 -LLVMIntegerTypeKind = 8 -LLVMFunctionTypeKind = 9 -LLVMStructTypeKind = 10 -LLVMArrayTypeKind = 11 -LLVMPointerTypeKind = 12 -LLVMVectorTypeKind = 13 -LLVMMetadataTypeKind = 14 -LLVMTokenTypeKind = 16 -LLVMScalableVectorTypeKind = 17 -LLVMBFloatTypeKind = 18 -LLVMX86_AMXTypeKind = 19 -LLVMTargetExtTypeKind = 20 -c__EA_LLVMTypeKind = ctypes.c_uint32 # enum -LLVMTypeKind = c__EA_LLVMTypeKind -LLVMTypeKind__enumvalues = c__EA_LLVMTypeKind__enumvalues -try: - lp_typekind_name = _libraries['libtinymesa_cpu.so'].lp_typekind_name - lp_typekind_name.restype = ctypes.POINTER(ctypes.c_char) - lp_typekind_name.argtypes = [LLVMTypeKind] -except AttributeError: - pass -try: - lp_dump_llvmtype = _libraries['libtinymesa_cpu.so'].lp_dump_llvmtype - lp_dump_llvmtype.restype = None - lp_dump_llvmtype.argtypes = [LLVMTypeRef] -except AttributeError: - pass -try: - lp_build_context_init = _libraries['libtinymesa_cpu.so'].lp_build_context_init - lp_build_context_init.restype = None - lp_build_context_init.argtypes = [ctypes.POINTER(struct_lp_build_context), ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_count_ir_module = _libraries['libtinymesa_cpu.so'].lp_build_count_ir_module - lp_build_count_ir_module.restype = ctypes.c_uint32 - lp_build_count_ir_module.argtypes = [LLVMModuleRef] -except AttributeError: - pass -class union_lp_jit_texture_0(Union): - pass - -class struct_lp_jit_texture_0_0(Structure): - pass - -struct_lp_jit_texture_0_0._pack_ = 1 # source:False -struct_lp_jit_texture_0_0._fields_ = [ - ('row_stride', ctypes.c_uint32 * 16), - ('img_stride', ctypes.c_uint32 * 16), +struct_lp_build_context._fields_ = [ + ('gallivm', ctypes.POINTER(struct_gallivm_state)), + ('type', struct_lp_type), + ('elem_type', LLVMTypeRef), + ('vec_type', LLVMTypeRef), + ('int_elem_type', LLVMTypeRef), + ('int_vec_type', LLVMTypeRef), + ('undef', LLVMValueRef), + ('zero', LLVMValueRef), + ('one', LLVMValueRef), ] +# LLVMTypeRef lp_build_elem_type(const struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_elem_type:=dll.lp_build_elem_type).restype, lp_build_elem_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass -union_lp_jit_texture_0._pack_ = 1 # source:False -union_lp_jit_texture_0._anonymous_ = ('_0',) -union_lp_jit_texture_0._fields_ = [ - ('_0', struct_lp_jit_texture_0_0), - ('residency', ctypes.POINTER(None)), - ('PADDING_0', ctypes.c_ubyte * 120), -] +# LLVMTypeRef lp_build_vec_type(const struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_vec_type:=dll.lp_build_vec_type).restype, lp_build_vec_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass -struct_lp_jit_texture._pack_ = 1 # source:False -struct_lp_jit_texture._anonymous_ = ('_0',) -struct_lp_jit_texture._fields_ = [ - ('base', ctypes.POINTER(None)), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint16), - ('depth', ctypes.c_uint16), - ('_0', union_lp_jit_texture_0), - ('first_level', ctypes.c_ubyte), - ('last_level', ctypes.c_ubyte), - ('mip_offsets', ctypes.c_uint32 * 16), - ('sampler_index', ctypes.c_uint32), -] +# bool lp_check_elem_type(struct lp_type type, LLVMTypeRef elem_type) +try: (lp_check_elem_type:=dll.lp_check_elem_type).restype, lp_check_elem_type.argtypes = ctypes.c_bool, [struct_lp_type, LLVMTypeRef] +except AttributeError: pass -try: - lp_build_init_native_width = _libraries['libtinymesa_cpu.so'].lp_build_init_native_width - lp_build_init_native_width.restype = ctypes.c_uint32 - lp_build_init_native_width.argtypes = [] -except AttributeError: - pass -try: - lp_build_init = _libraries['libtinymesa_cpu.so'].lp_build_init - lp_build_init.restype = ctypes.c_bool - lp_build_init.argtypes = [] -except AttributeError: - pass -try: - gallivm_create = _libraries['libtinymesa_cpu.so'].gallivm_create - gallivm_create.restype = ctypes.POINTER(struct_gallivm_state) - gallivm_create.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_lp_context_ref), ctypes.POINTER(struct_lp_cached_code)] -except AttributeError: - pass -try: - gallivm_destroy = _libraries['libtinymesa_cpu.so'].gallivm_destroy - gallivm_destroy.restype = None - gallivm_destroy.argtypes = [ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass -try: - gallivm_free_ir = _libraries['libtinymesa_cpu.so'].gallivm_free_ir - gallivm_free_ir.restype = None - gallivm_free_ir.argtypes = [ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass -try: - gallivm_verify_function = _libraries['libtinymesa_cpu.so'].gallivm_verify_function - gallivm_verify_function.restype = None - gallivm_verify_function.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef] -except AttributeError: - pass -try: - gallivm_add_global_mapping = _libraries['libtinymesa_cpu.so'].gallivm_add_global_mapping - gallivm_add_global_mapping.restype = None - gallivm_add_global_mapping.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, ctypes.POINTER(None)] -except AttributeError: - pass -try: - gallivm_compile_module = _libraries['libtinymesa_cpu.so'].gallivm_compile_module - gallivm_compile_module.restype = None - gallivm_compile_module.argtypes = [ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass -func_pointer = ctypes.CFUNCTYPE(None) -try: - gallivm_jit_function = _libraries['libtinymesa_cpu.so'].gallivm_jit_function - gallivm_jit_function.restype = func_pointer - gallivm_jit_function.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - gallivm_stub_func = _libraries['libtinymesa_cpu.so'].gallivm_stub_func - gallivm_stub_func.restype = None - gallivm_stub_func.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef] -except AttributeError: - pass -try: - gallivm_get_perf_flags = _libraries['libtinymesa_cpu.so'].gallivm_get_perf_flags - gallivm_get_perf_flags.restype = ctypes.c_uint32 - gallivm_get_perf_flags.argtypes = [] -except AttributeError: - pass -try: - lp_init_clock_hook = _libraries['libtinymesa_cpu.so'].lp_init_clock_hook - lp_init_clock_hook.restype = None - lp_init_clock_hook.argtypes = [ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass -try: - lp_init_env_options = _libraries['libtinymesa_cpu.so'].lp_init_env_options - lp_init_env_options.restype = None - lp_init_env_options.argtypes = [] -except AttributeError: - pass -try: - lp_bld_ppc_disable_denorms = _libraries['FIXME_STUB'].lp_bld_ppc_disable_denorms - lp_bld_ppc_disable_denorms.restype = None - lp_bld_ppc_disable_denorms.argtypes = [] -except AttributeError: - pass -class struct_lp_build_skip_context(Structure): - pass +# bool lp_check_vec_type(struct lp_type type, LLVMTypeRef vec_type) +try: (lp_check_vec_type:=dll.lp_check_vec_type).restype, lp_check_vec_type.argtypes = ctypes.c_bool, [struct_lp_type, LLVMTypeRef] +except AttributeError: pass -class struct_LLVMOpaqueBasicBlock(Structure): - pass +# bool lp_check_value(struct lp_type type, LLVMValueRef val) +try: (lp_check_value:=dll.lp_check_value).restype, lp_check_value.argtypes = ctypes.c_bool, [struct_lp_type, LLVMValueRef] +except AttributeError: pass -struct_lp_build_skip_context._pack_ = 1 # source:False -struct_lp_build_skip_context._fields_ = [ - ('gallivm', ctypes.POINTER(struct_gallivm_state)), - ('block', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), -] +# LLVMTypeRef lp_build_int_elem_type(const struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_int_elem_type:=dll.lp_build_int_elem_type).restype, lp_build_int_elem_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass -try: - lp_build_flow_skip_begin = _libraries['libtinymesa_cpu.so'].lp_build_flow_skip_begin - lp_build_flow_skip_begin.restype = None - lp_build_flow_skip_begin.argtypes = [ctypes.POINTER(struct_lp_build_skip_context), ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass -try: - lp_build_flow_skip_cond_break = _libraries['libtinymesa_cpu.so'].lp_build_flow_skip_cond_break - lp_build_flow_skip_cond_break.restype = None - lp_build_flow_skip_cond_break.argtypes = [ctypes.POINTER(struct_lp_build_skip_context), LLVMValueRef] -except AttributeError: - pass -try: - lp_build_flow_skip_end = _libraries['libtinymesa_cpu.so'].lp_build_flow_skip_end - lp_build_flow_skip_end.restype = None - lp_build_flow_skip_end.argtypes = [ctypes.POINTER(struct_lp_build_skip_context)] -except AttributeError: - pass -class struct_lp_build_mask_context(Structure): - pass +# LLVMTypeRef lp_build_int_vec_type(const struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_int_vec_type:=dll.lp_build_int_vec_type).restype, lp_build_int_vec_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass -struct_lp_build_mask_context._pack_ = 1 # source:False -struct_lp_build_mask_context._fields_ = [ - ('skip', struct_lp_build_skip_context), - ('reg_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('var_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('var', ctypes.POINTER(struct_LLVMOpaqueValue)), -] +# struct lp_type lp_elem_type(struct lp_type type) +try: (lp_elem_type:=dll.lp_elem_type).restype, lp_elem_type.argtypes = struct_lp_type, [struct_lp_type] +except AttributeError: pass -try: - lp_build_mask_begin = _libraries['libtinymesa_cpu.so'].lp_build_mask_begin - lp_build_mask_begin.restype = None - lp_build_mask_begin.argtypes = [ctypes.POINTER(struct_lp_build_mask_context), ctypes.POINTER(struct_gallivm_state), struct_lp_type, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_mask_value = _libraries['libtinymesa_cpu.so'].lp_build_mask_value - lp_build_mask_value.restype = LLVMValueRef - lp_build_mask_value.argtypes = [ctypes.POINTER(struct_lp_build_mask_context)] -except AttributeError: - pass -try: - lp_build_mask_update = _libraries['libtinymesa_cpu.so'].lp_build_mask_update - lp_build_mask_update.restype = None - lp_build_mask_update.argtypes = [ctypes.POINTER(struct_lp_build_mask_context), LLVMValueRef] -except AttributeError: - pass -try: - lp_build_mask_force = _libraries['libtinymesa_cpu.so'].lp_build_mask_force - lp_build_mask_force.restype = None - lp_build_mask_force.argtypes = [ctypes.POINTER(struct_lp_build_mask_context), LLVMValueRef] -except AttributeError: - pass -try: - lp_build_mask_check = _libraries['libtinymesa_cpu.so'].lp_build_mask_check - lp_build_mask_check.restype = None - lp_build_mask_check.argtypes = [ctypes.POINTER(struct_lp_build_mask_context)] -except AttributeError: - pass -try: - lp_build_mask_end = _libraries['libtinymesa_cpu.so'].lp_build_mask_end - lp_build_mask_end.restype = LLVMValueRef - lp_build_mask_end.argtypes = [ctypes.POINTER(struct_lp_build_mask_context)] -except AttributeError: - pass -class struct_lp_build_loop_state(Structure): - pass +# struct lp_type lp_uint_type(struct lp_type type) +try: (lp_uint_type:=dll.lp_uint_type).restype, lp_uint_type.argtypes = struct_lp_type, [struct_lp_type] +except AttributeError: pass -struct_lp_build_loop_state._pack_ = 1 # source:False -struct_lp_build_loop_state._fields_ = [ - ('block', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('counter_var', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('counter', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('counter_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('gallivm', ctypes.POINTER(struct_gallivm_state)), -] +# struct lp_type lp_int_type(struct lp_type type) +try: (lp_int_type:=dll.lp_int_type).restype, lp_int_type.argtypes = struct_lp_type, [struct_lp_type] +except AttributeError: pass -try: - lp_build_loop_begin = _libraries['libtinymesa_cpu.so'].lp_build_loop_begin - lp_build_loop_begin.restype = None - lp_build_loop_begin.argtypes = [ctypes.POINTER(struct_lp_build_loop_state), ctypes.POINTER(struct_gallivm_state), LLVMValueRef] -except AttributeError: - pass -try: - lp_build_loop_end = _libraries['libtinymesa_cpu.so'].lp_build_loop_end - lp_build_loop_end.restype = None - lp_build_loop_end.argtypes = [ctypes.POINTER(struct_lp_build_loop_state), LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_loop_force_set_counter = _libraries['libtinymesa_cpu.so'].lp_build_loop_force_set_counter - lp_build_loop_force_set_counter.restype = None - lp_build_loop_force_set_counter.argtypes = [ctypes.POINTER(struct_lp_build_loop_state), LLVMValueRef] -except AttributeError: - pass -try: - lp_build_loop_force_reload_counter = _libraries['libtinymesa_cpu.so'].lp_build_loop_force_reload_counter - lp_build_loop_force_reload_counter.restype = None - lp_build_loop_force_reload_counter.argtypes = [ctypes.POINTER(struct_lp_build_loop_state)] -except AttributeError: - pass +# struct lp_type lp_wider_type(struct lp_type type) +try: (lp_wider_type:=dll.lp_wider_type).restype, lp_wider_type.argtypes = struct_lp_type, [struct_lp_type] +except AttributeError: pass -# values for enumeration 'c__EA_LLVMIntPredicate' -c__EA_LLVMIntPredicate__enumvalues = { - 32: 'LLVMIntEQ', - 33: 'LLVMIntNE', - 34: 'LLVMIntUGT', - 35: 'LLVMIntUGE', - 36: 'LLVMIntULT', - 37: 'LLVMIntULE', - 38: 'LLVMIntSGT', - 39: 'LLVMIntSGE', - 40: 'LLVMIntSLT', - 41: 'LLVMIntSLE', -} -LLVMIntEQ = 32 -LLVMIntNE = 33 -LLVMIntUGT = 34 -LLVMIntUGE = 35 -LLVMIntULT = 36 -LLVMIntULE = 37 -LLVMIntSGT = 38 -LLVMIntSGE = 39 -LLVMIntSLT = 40 -LLVMIntSLE = 41 -c__EA_LLVMIntPredicate = ctypes.c_uint32 # enum -LLVMIntPredicate = c__EA_LLVMIntPredicate -LLVMIntPredicate__enumvalues = c__EA_LLVMIntPredicate__enumvalues -try: - lp_build_loop_end_cond = _libraries['libtinymesa_cpu.so'].lp_build_loop_end_cond - lp_build_loop_end_cond.restype = None - lp_build_loop_end_cond.argtypes = [ctypes.POINTER(struct_lp_build_loop_state), LLVMValueRef, LLVMValueRef, LLVMIntPredicate] -except AttributeError: - pass -class struct_lp_build_for_loop_state(Structure): - pass +# unsigned int lp_sizeof_llvm_type(LLVMTypeRef t) +try: (lp_sizeof_llvm_type:=dll.lp_sizeof_llvm_type).restype, lp_sizeof_llvm_type.argtypes = ctypes.c_uint32, [LLVMTypeRef] +except AttributeError: pass -struct_lp_build_for_loop_state._pack_ = 1 # source:False -struct_lp_build_for_loop_state._fields_ = [ - ('begin', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('body', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('exit', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('counter_var', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('counter', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('counter_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('step', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('cond', LLVMIntPredicate), - ('PADDING_0', ctypes.c_ubyte * 4), - ('end', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('gallivm', ctypes.POINTER(struct_gallivm_state)), -] +LLVMTypeKind = CEnum(ctypes.c_uint32) +LLVMVoidTypeKind = LLVMTypeKind.define('LLVMVoidTypeKind', 0) +LLVMHalfTypeKind = LLVMTypeKind.define('LLVMHalfTypeKind', 1) +LLVMFloatTypeKind = LLVMTypeKind.define('LLVMFloatTypeKind', 2) +LLVMDoubleTypeKind = LLVMTypeKind.define('LLVMDoubleTypeKind', 3) +LLVMX86_FP80TypeKind = LLVMTypeKind.define('LLVMX86_FP80TypeKind', 4) +LLVMFP128TypeKind = LLVMTypeKind.define('LLVMFP128TypeKind', 5) +LLVMPPC_FP128TypeKind = LLVMTypeKind.define('LLVMPPC_FP128TypeKind', 6) +LLVMLabelTypeKind = LLVMTypeKind.define('LLVMLabelTypeKind', 7) +LLVMIntegerTypeKind = LLVMTypeKind.define('LLVMIntegerTypeKind', 8) +LLVMFunctionTypeKind = LLVMTypeKind.define('LLVMFunctionTypeKind', 9) +LLVMStructTypeKind = LLVMTypeKind.define('LLVMStructTypeKind', 10) +LLVMArrayTypeKind = LLVMTypeKind.define('LLVMArrayTypeKind', 11) +LLVMPointerTypeKind = LLVMTypeKind.define('LLVMPointerTypeKind', 12) +LLVMVectorTypeKind = LLVMTypeKind.define('LLVMVectorTypeKind', 13) +LLVMMetadataTypeKind = LLVMTypeKind.define('LLVMMetadataTypeKind', 14) +LLVMTokenTypeKind = LLVMTypeKind.define('LLVMTokenTypeKind', 16) +LLVMScalableVectorTypeKind = LLVMTypeKind.define('LLVMScalableVectorTypeKind', 17) +LLVMBFloatTypeKind = LLVMTypeKind.define('LLVMBFloatTypeKind', 18) +LLVMX86_AMXTypeKind = LLVMTypeKind.define('LLVMX86_AMXTypeKind', 19) +LLVMTargetExtTypeKind = LLVMTypeKind.define('LLVMTargetExtTypeKind', 20) -try: - lp_build_for_loop_begin = _libraries['libtinymesa_cpu.so'].lp_build_for_loop_begin - lp_build_for_loop_begin.restype = None - lp_build_for_loop_begin.argtypes = [ctypes.POINTER(struct_lp_build_for_loop_state), ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMIntPredicate, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_for_loop_end = _libraries['libtinymesa_cpu.so'].lp_build_for_loop_end - lp_build_for_loop_end.restype = None - lp_build_for_loop_end.argtypes = [ctypes.POINTER(struct_lp_build_for_loop_state)] -except AttributeError: - pass -class struct_lp_build_if_state(Structure): - pass +# const char *lp_typekind_name(LLVMTypeKind t) +try: (lp_typekind_name:=dll.lp_typekind_name).restype, lp_typekind_name.argtypes = ctypes.POINTER(ctypes.c_char), [LLVMTypeKind] +except AttributeError: pass -struct_lp_build_if_state._pack_ = 1 # source:False -struct_lp_build_if_state._fields_ = [ - ('gallivm', ctypes.POINTER(struct_gallivm_state)), - ('condition', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('entry_block', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('true_block', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('false_block', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), - ('merge_block', ctypes.POINTER(struct_LLVMOpaqueBasicBlock)), -] +# void lp_dump_llvmtype(LLVMTypeRef t) +try: (lp_dump_llvmtype:=dll.lp_dump_llvmtype).restype, lp_dump_llvmtype.argtypes = None, [LLVMTypeRef] +except AttributeError: pass -try: - lp_build_if = _libraries['libtinymesa_cpu.so'].lp_build_if - lp_build_if.restype = None - lp_build_if.argtypes = [ctypes.POINTER(struct_lp_build_if_state), ctypes.POINTER(struct_gallivm_state), LLVMValueRef] -except AttributeError: - pass -try: - lp_build_else = _libraries['libtinymesa_cpu.so'].lp_build_else - lp_build_else.restype = None - lp_build_else.argtypes = [ctypes.POINTER(struct_lp_build_if_state)] -except AttributeError: - pass -try: - lp_build_endif = _libraries['libtinymesa_cpu.so'].lp_build_endif - lp_build_endif.restype = None - lp_build_endif.argtypes = [ctypes.POINTER(struct_lp_build_if_state)] -except AttributeError: - pass -LLVMBasicBlockRef = ctypes.POINTER(struct_LLVMOpaqueBasicBlock) -try: - lp_build_insert_new_block = _libraries['libtinymesa_cpu.so'].lp_build_insert_new_block - lp_build_insert_new_block.restype = LLVMBasicBlockRef - lp_build_insert_new_block.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass +# void lp_build_context_init(struct lp_build_context *bld, struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_context_init:=dll.lp_build_context_init).restype, lp_build_context_init.argtypes = None, [ctypes.POINTER(struct_lp_build_context), ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass + +# unsigned int lp_build_count_ir_module(LLVMModuleRef module) +try: (lp_build_count_ir_module:=dll.lp_build_count_ir_module).restype, lp_build_count_ir_module.argtypes = ctypes.c_uint32, [LLVMModuleRef] +except AttributeError: pass + +class struct_lp_jit_texture(Struct): pass +class struct_LLVMOpaqueTargetData(Struct): pass +LLVMTargetDataRef = ctypes.POINTER(struct_LLVMOpaqueTargetData) +class struct_LLVMOpaqueBuilder(Struct): pass LLVMBuilderRef = ctypes.POINTER(struct_LLVMOpaqueBuilder) -try: - lp_create_builder_at_entry = _libraries['libtinymesa_cpu.so'].lp_create_builder_at_entry - lp_create_builder_at_entry.restype = LLVMBuilderRef - lp_create_builder_at_entry.argtypes = [ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass -try: - lp_build_alloca = _libraries['libtinymesa_cpu.so'].lp_build_alloca - lp_build_alloca.restype = LLVMValueRef - lp_build_alloca.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_build_alloca_undef = _libraries['libtinymesa_cpu.so'].lp_build_alloca_undef - lp_build_alloca_undef.restype = LLVMValueRef - lp_build_alloca_undef.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_build_array_alloca = _libraries['libtinymesa_cpu.so'].lp_build_array_alloca - lp_build_array_alloca.restype = LLVMValueRef - lp_build_array_alloca.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_lp_build_tgsi_params(Structure): - pass - -class struct_lp_bld_tgsi_system_values(Structure): - pass - -class struct_lp_build_sampler_soa(Structure): - pass - -class struct_tgsi_shader_info(Structure): - pass - -class struct_lp_build_gs_iface(Structure): - pass - -class struct_lp_build_tcs_iface(Structure): - pass - -class struct_lp_build_tes_iface(Structure): - pass - -class struct_lp_build_mesh_iface(Structure): - pass - -class struct_lp_build_image_soa(Structure): - pass - -class struct_lp_build_coro_suspend_info(Structure): - pass - -class struct_lp_build_fs_iface(Structure): - pass - -struct_lp_build_tgsi_params._pack_ = 1 # source:False -struct_lp_build_tgsi_params._fields_ = [ - ('type', struct_lp_type), - ('mask', ctypes.POINTER(struct_lp_build_mask_context)), - ('consts_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('const_sizes_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('system_values', ctypes.POINTER(struct_lp_bld_tgsi_system_values)), - ('inputs', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue) * 4)), - ('num_inputs', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('context_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('context_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('resources_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('resources_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('thread_data_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('thread_data_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sampler', ctypes.POINTER(struct_lp_build_sampler_soa)), - ('info', ctypes.POINTER(struct_tgsi_shader_info)), - ('gs_iface', ctypes.POINTER(struct_lp_build_gs_iface)), - ('tcs_iface', ctypes.POINTER(struct_lp_build_tcs_iface)), - ('tes_iface', ctypes.POINTER(struct_lp_build_tes_iface)), - ('mesh_iface', ctypes.POINTER(struct_lp_build_mesh_iface)), - ('ssbo_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('ssbo_sizes_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('image', ctypes.POINTER(struct_lp_build_image_soa)), - ('shared_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('payload_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('coro', ctypes.POINTER(struct_lp_build_coro_suspend_info)), - ('fs_iface', ctypes.POINTER(struct_lp_build_fs_iface)), - ('gs_vertex_streams', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('current_func', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('fns', ctypes.POINTER(struct_hash_table)), - ('scratch_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('call_context_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), +class struct_LLVMOpaqueDIBuilder(Struct): pass +LLVMDIBuilderRef = ctypes.POINTER(struct_LLVMOpaqueDIBuilder) +class struct_LLVMOpaqueMetadata(Struct): pass +LLVMMetadataRef = ctypes.POINTER(struct_LLVMOpaqueMetadata) +struct_gallivm_state._fields_ = [ + ('module_name', ctypes.POINTER(ctypes.c_char)), + ('file_name', ctypes.POINTER(ctypes.c_char)), + ('module', LLVMModuleRef), + ('target', LLVMTargetDataRef), + ('engine', LLVMExecutionEngineRef), + ('passmgr', ctypes.POINTER(struct_lp_passmgr)), + ('memorymgr', LLVMMCJITMemoryManagerRef), + ('code', ctypes.POINTER(struct_lp_generated_code)), + ('context', LLVMContextRef), + ('builder', LLVMBuilderRef), + ('di_builder', LLVMDIBuilderRef), + ('cache', ctypes.POINTER(struct_lp_cached_code)), + ('compiled', ctypes.c_uint32), + ('coro_malloc_hook', LLVMValueRef), + ('coro_free_hook', LLVMValueRef), + ('debug_printf_hook', LLVMValueRef), + ('coro_malloc_hook_type', LLVMTypeRef), + ('coro_free_hook_type', LLVMTypeRef), + ('di_function', LLVMMetadataRef), + ('file', LLVMMetadataRef), + ('get_time_hook', LLVMValueRef), + ('texture_descriptor', LLVMValueRef), + ('texture_dynamic_state', ctypes.POINTER(struct_lp_jit_texture)), + ('sampler_descriptor', LLVMValueRef), ] +# unsigned int lp_build_init_native_width(void) +try: (lp_build_init_native_width:=dll.lp_build_init_native_width).restype, lp_build_init_native_width.argtypes = ctypes.c_uint32, [] +except AttributeError: pass -struct_lp_bld_tgsi_system_values._pack_ = 1 # source:False +# bool lp_build_init(void) +try: (lp_build_init:=dll.lp_build_init).restype, lp_build_init.argtypes = ctypes.c_bool, [] +except AttributeError: pass + +# struct gallivm_state *gallivm_create(const char *name, lp_context_ref *context, struct lp_cached_code *cache) +try: (gallivm_create:=dll.gallivm_create).restype, gallivm_create.argtypes = ctypes.POINTER(struct_gallivm_state), [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(lp_context_ref), ctypes.POINTER(struct_lp_cached_code)] +except AttributeError: pass + +# void gallivm_destroy(struct gallivm_state *gallivm) +try: (gallivm_destroy:=dll.gallivm_destroy).restype, gallivm_destroy.argtypes = None, [ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass + +# void gallivm_free_ir(struct gallivm_state *gallivm) +try: (gallivm_free_ir:=dll.gallivm_free_ir).restype, gallivm_free_ir.argtypes = None, [ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass + +# void gallivm_verify_function(struct gallivm_state *gallivm, LLVMValueRef func) +try: (gallivm_verify_function:=dll.gallivm_verify_function).restype, gallivm_verify_function.argtypes = None, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef] +except AttributeError: pass + +# void gallivm_add_global_mapping(struct gallivm_state *gallivm, LLVMValueRef sym, void *addr) +try: (gallivm_add_global_mapping:=dll.gallivm_add_global_mapping).restype, gallivm_add_global_mapping.argtypes = None, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, ctypes.c_void_p] +except AttributeError: pass + +# void gallivm_compile_module(struct gallivm_state *gallivm) +try: (gallivm_compile_module:=dll.gallivm_compile_module).restype, gallivm_compile_module.argtypes = None, [ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass + +func_pointer = ctypes.CFUNCTYPE(None, ) +# func_pointer gallivm_jit_function(struct gallivm_state *gallivm, LLVMValueRef func, const char *func_name) +try: (gallivm_jit_function:=dll.gallivm_jit_function).restype, gallivm_jit_function.argtypes = func_pointer, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void gallivm_stub_func(struct gallivm_state *gallivm, LLVMValueRef func) +try: (gallivm_stub_func:=dll.gallivm_stub_func).restype, gallivm_stub_func.argtypes = None, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef] +except AttributeError: pass + +# unsigned int gallivm_get_perf_flags(void) +try: (gallivm_get_perf_flags:=dll.gallivm_get_perf_flags).restype, gallivm_get_perf_flags.argtypes = ctypes.c_uint32, [] +except AttributeError: pass + +# void lp_init_clock_hook(struct gallivm_state *gallivm) +try: (lp_init_clock_hook:=dll.lp_init_clock_hook).restype, lp_init_clock_hook.argtypes = None, [ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass + +# void lp_init_env_options(void) +try: (lp_init_env_options:=dll.lp_init_env_options).restype, lp_init_env_options.argtypes = None, [] +except AttributeError: pass + +class struct_lp_build_tgsi_params(Struct): pass +class struct_lp_build_mask_context(Struct): pass +class struct_lp_build_skip_context(Struct): pass +class struct_LLVMOpaqueBasicBlock(Struct): pass +LLVMBasicBlockRef = ctypes.POINTER(struct_LLVMOpaqueBasicBlock) +struct_lp_build_skip_context._fields_ = [ + ('gallivm', ctypes.POINTER(struct_gallivm_state)), + ('block', LLVMBasicBlockRef), +] +struct_lp_build_mask_context._fields_ = [ + ('skip', struct_lp_build_skip_context), + ('reg_type', LLVMTypeRef), + ('var_type', LLVMTypeRef), + ('var', LLVMValueRef), +] +class struct_lp_bld_tgsi_system_values(Struct): pass struct_lp_bld_tgsi_system_values._fields_ = [ - ('instance_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('base_instance', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('vertex_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('vertex_id_nobase', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('prim_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('basevertex', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('firstvertex', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('invocation_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('draw_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('thread_id', ctypes.POINTER(struct_LLVMOpaqueValue) * 3), - ('block_id', ctypes.POINTER(struct_LLVMOpaqueValue) * 3), - ('grid_size', ctypes.POINTER(struct_LLVMOpaqueValue) * 3), - ('front_facing', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('work_dim', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('block_size', ctypes.POINTER(struct_LLVMOpaqueValue) * 3), - ('tess_coord', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('tess_outer', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('tess_inner', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('vertices_in', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sample_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sample_pos_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('sample_pos', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sample_mask_in', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('view_index', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('subgroup_id', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('num_subgroups', ctypes.POINTER(struct_LLVMOpaqueValue)), + ('instance_id', LLVMValueRef), + ('base_instance', LLVMValueRef), + ('vertex_id', LLVMValueRef), + ('vertex_id_nobase', LLVMValueRef), + ('prim_id', LLVMValueRef), + ('basevertex', LLVMValueRef), + ('firstvertex', LLVMValueRef), + ('invocation_id', LLVMValueRef), + ('draw_id', LLVMValueRef), + ('thread_id', (LLVMValueRef * 3)), + ('block_id', (LLVMValueRef * 3)), + ('grid_size', (LLVMValueRef * 3)), + ('front_facing', LLVMValueRef), + ('work_dim', LLVMValueRef), + ('block_size', (LLVMValueRef * 3)), + ('tess_coord', LLVMValueRef), + ('tess_outer', LLVMValueRef), + ('tess_inner', LLVMValueRef), + ('vertices_in', LLVMValueRef), + ('sample_id', LLVMValueRef), + ('sample_pos_type', LLVMTypeRef), + ('sample_pos', LLVMValueRef), + ('sample_mask_in', LLVMValueRef), + ('view_index', LLVMValueRef), + ('subgroup_id', LLVMValueRef), + ('num_subgroups', LLVMValueRef), ] - -class struct_lp_sampler_params(Structure): - pass - -class struct_lp_sampler_size_query_params(Structure): - pass - -struct_lp_build_sampler_soa._pack_ = 1 # source:False -struct_lp_build_sampler_soa._fields_ = [ - ('emit_tex_sample', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_sampler_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_params))), - ('emit_size_query', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_sampler_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_size_query_params))), -] - -class struct_lp_derivatives(Structure): - pass - -struct_lp_sampler_params._pack_ = 1 # source:False -struct_lp_sampler_params._fields_ = [ - ('type', struct_lp_type), - ('texture_index', ctypes.c_uint32), - ('sampler_index', ctypes.c_uint32), - ('texture_index_offset', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sample_key', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resources_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('resources_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('thread_data_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('thread_data_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('coords', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))), - ('offsets', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))), - ('ms_index', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('lod', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('min_lod', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('derivs', ctypes.POINTER(struct_lp_derivatives)), - ('texel', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))), - ('texture_resource', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sampler_resource', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('exec_mask', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('exec_mask_nz', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -struct_lp_derivatives._pack_ = 1 # source:False +class struct_lp_build_sampler_soa(Struct): pass +class struct_lp_sampler_params(Struct): pass +class struct_lp_derivatives(Struct): pass struct_lp_derivatives._fields_ = [ - ('ddx', ctypes.POINTER(struct_LLVMOpaqueValue) * 3), - ('ddy', ctypes.POINTER(struct_LLVMOpaqueValue) * 3), + ('ddx', (LLVMValueRef * 3)), + ('ddy', (LLVMValueRef * 3)), ] +struct_lp_sampler_params._fields_ = [ + ('type', struct_lp_type), + ('texture_index', ctypes.c_uint32), + ('sampler_index', ctypes.c_uint32), + ('texture_index_offset', LLVMValueRef), + ('sample_key', ctypes.c_uint32), + ('resources_type', LLVMTypeRef), + ('resources_ptr', LLVMValueRef), + ('thread_data_type', LLVMTypeRef), + ('thread_data_ptr', LLVMValueRef), + ('coords', ctypes.POINTER(LLVMValueRef)), + ('offsets', ctypes.POINTER(LLVMValueRef)), + ('ms_index', LLVMValueRef), + ('lod', LLVMValueRef), + ('min_lod', LLVMValueRef), + ('derivs', ctypes.POINTER(struct_lp_derivatives)), + ('texel', ctypes.POINTER(LLVMValueRef)), + ('texture_resource', LLVMValueRef), + ('sampler_resource', LLVMValueRef), + ('exec_mask', LLVMValueRef), + ('exec_mask_nz', ctypes.c_bool), +] +class struct_lp_sampler_size_query_params(Struct): pass +enum_lp_sampler_lod_property = CEnum(ctypes.c_uint32) +LP_SAMPLER_LOD_SCALAR = enum_lp_sampler_lod_property.define('LP_SAMPLER_LOD_SCALAR', 0) +LP_SAMPLER_LOD_PER_ELEMENT = enum_lp_sampler_lod_property.define('LP_SAMPLER_LOD_PER_ELEMENT', 1) +LP_SAMPLER_LOD_PER_QUAD = enum_lp_sampler_lod_property.define('LP_SAMPLER_LOD_PER_QUAD', 2) - -# values for enumeration 'lp_sampler_lod_property' -lp_sampler_lod_property__enumvalues = { - 0: 'LP_SAMPLER_LOD_SCALAR', - 1: 'LP_SAMPLER_LOD_PER_ELEMENT', - 2: 'LP_SAMPLER_LOD_PER_QUAD', -} -LP_SAMPLER_LOD_SCALAR = 0 -LP_SAMPLER_LOD_PER_ELEMENT = 1 -LP_SAMPLER_LOD_PER_QUAD = 2 -lp_sampler_lod_property = ctypes.c_uint32 # enum -struct_lp_sampler_size_query_params._pack_ = 1 # source:False struct_lp_sampler_size_query_params._fields_ = [ - ('int_type', struct_lp_type), - ('texture_unit', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('texture_unit_offset', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('target', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('resources_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('resources_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('is_sviewinfo', ctypes.c_bool), - ('samples_only', ctypes.c_bool), - ('ms', ctypes.c_bool), - ('PADDING_2', ctypes.c_ubyte), - ('lod_property', lp_sampler_lod_property), - ('explicit_lod', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('sizes_out', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))), - ('resource', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('exec_mask', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('exec_mask_nz', ctypes.c_bool), - ('PADDING_3', ctypes.c_ubyte * 3), - ('format', pipe_format), + ('int_type', struct_lp_type), + ('texture_unit', ctypes.c_uint32), + ('texture_unit_offset', LLVMValueRef), + ('target', ctypes.c_uint32), + ('resources_type', LLVMTypeRef), + ('resources_ptr', LLVMValueRef), + ('is_sviewinfo', ctypes.c_bool), + ('samples_only', ctypes.c_bool), + ('ms', ctypes.c_bool), + ('lod_property', enum_lp_sampler_lod_property), + ('explicit_lod', LLVMValueRef), + ('sizes_out', ctypes.POINTER(LLVMValueRef)), + ('resource', LLVMValueRef), + ('exec_mask', LLVMValueRef), + ('exec_mask_nz', ctypes.c_bool), + ('format', enum_pipe_format), ] - -struct_tgsi_shader_info._pack_ = 1 # source:False +struct_lp_build_sampler_soa._fields_ = [ + ('emit_tex_sample', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_sampler_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_params))), + ('emit_size_query', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_sampler_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_size_query_params))), +] +class struct_tgsi_shader_info(Struct): pass struct_tgsi_shader_info._fields_ = [ - ('num_inputs', ctypes.c_ubyte), - ('num_outputs', ctypes.c_ubyte), - ('input_semantic_name', ctypes.c_ubyte * 80), - ('input_semantic_index', ctypes.c_ubyte * 80), - ('input_interpolate', ctypes.c_ubyte * 80), - ('input_interpolate_loc', ctypes.c_ubyte * 80), - ('input_usage_mask', ctypes.c_ubyte * 80), - ('output_semantic_name', ctypes.c_ubyte * 80), - ('output_semantic_index', ctypes.c_ubyte * 80), - ('output_usagemask', ctypes.c_ubyte * 80), - ('output_streams', ctypes.c_ubyte * 80), - ('num_system_values', ctypes.c_ubyte), - ('system_value_semantic_name', ctypes.c_ubyte * 80), - ('processor', ctypes.c_ubyte), - ('file_mask', ctypes.c_uint32 * 15), - ('file_count', ctypes.c_uint32 * 15), - ('file_max', ctypes.c_int32 * 15), - ('const_file_max', ctypes.c_int32 * 32), - ('const_buffers_declared', ctypes.c_uint32), - ('samplers_declared', ctypes.c_uint32), - ('sampler_targets', ctypes.c_ubyte * 128), - ('sampler_type', ctypes.c_ubyte * 128), - ('num_stream_output_components', ctypes.c_ubyte * 4), - ('input_array_first', ctypes.c_ubyte * 80), - ('output_array_first', ctypes.c_ubyte * 80), - ('immediate_count', ctypes.c_uint32), - ('num_instructions', ctypes.c_uint32), - ('opcode_count', ctypes.c_uint32 * 252), - ('reads_pervertex_outputs', ctypes.c_bool), - ('reads_perpatch_outputs', ctypes.c_bool), - ('reads_tessfactor_outputs', ctypes.c_bool), - ('reads_z', ctypes.c_bool), - ('writes_z', ctypes.c_bool), - ('writes_stencil', ctypes.c_bool), - ('writes_samplemask', ctypes.c_bool), - ('writes_edgeflag', ctypes.c_bool), - ('uses_kill', ctypes.c_bool), - ('uses_instanceid', ctypes.c_bool), - ('uses_vertexid', ctypes.c_bool), - ('uses_vertexid_nobase', ctypes.c_bool), - ('uses_basevertex', ctypes.c_bool), - ('uses_primid', ctypes.c_bool), - ('uses_frontface', ctypes.c_bool), - ('uses_invocationid', ctypes.c_bool), - ('uses_grid_size', ctypes.c_bool), - ('writes_position', ctypes.c_bool), - ('writes_psize', ctypes.c_bool), - ('writes_clipvertex', ctypes.c_bool), - ('writes_viewport_index', ctypes.c_bool), - ('writes_layer', ctypes.c_bool), - ('writes_memory', ctypes.c_bool), - ('uses_fbfetch', ctypes.c_bool), - ('num_written_culldistance', ctypes.c_uint32), - ('num_written_clipdistance', ctypes.c_uint32), - ('images_declared', ctypes.c_uint32), - ('msaa_images_declared', ctypes.c_uint32), - ('images_buffers', ctypes.c_uint32), - ('shader_buffers_declared', ctypes.c_uint32), - ('shader_buffers_load', ctypes.c_uint32), - ('shader_buffers_store', ctypes.c_uint32), - ('shader_buffers_atomic', ctypes.c_uint32), - ('hw_atomic_declared', ctypes.c_uint32), - ('indirect_files', ctypes.c_uint32), - ('dim_indirect_files', ctypes.c_uint32), - ('properties', ctypes.c_uint32 * 29), + ('num_inputs', uint8_t), + ('num_outputs', uint8_t), + ('input_semantic_name', (uint8_t * 80)), + ('input_semantic_index', (uint8_t * 80)), + ('input_interpolate', (uint8_t * 80)), + ('input_interpolate_loc', (uint8_t * 80)), + ('input_usage_mask', (uint8_t * 80)), + ('output_semantic_name', (uint8_t * 80)), + ('output_semantic_index', (uint8_t * 80)), + ('output_usagemask', (uint8_t * 80)), + ('output_streams', (uint8_t * 80)), + ('num_system_values', uint8_t), + ('system_value_semantic_name', (uint8_t * 80)), + ('processor', uint8_t), + ('file_mask', (uint32_t * 15)), + ('file_count', (ctypes.c_uint32 * 15)), + ('file_max', (ctypes.c_int32 * 15)), + ('const_file_max', (ctypes.c_int32 * 32)), + ('const_buffers_declared', ctypes.c_uint32), + ('samplers_declared', ctypes.c_uint32), + ('sampler_targets', (uint8_t * 128)), + ('sampler_type', (uint8_t * 128)), + ('num_stream_output_components', (uint8_t * 4)), + ('input_array_first', (uint8_t * 80)), + ('output_array_first', (uint8_t * 80)), + ('immediate_count', ctypes.c_uint32), + ('num_instructions', ctypes.c_uint32), + ('opcode_count', (ctypes.c_uint32 * 252)), + ('reads_pervertex_outputs', ctypes.c_bool), + ('reads_perpatch_outputs', ctypes.c_bool), + ('reads_tessfactor_outputs', ctypes.c_bool), + ('reads_z', ctypes.c_bool), + ('writes_z', ctypes.c_bool), + ('writes_stencil', ctypes.c_bool), + ('writes_samplemask', ctypes.c_bool), + ('writes_edgeflag', ctypes.c_bool), + ('uses_kill', ctypes.c_bool), + ('uses_instanceid', ctypes.c_bool), + ('uses_vertexid', ctypes.c_bool), + ('uses_vertexid_nobase', ctypes.c_bool), + ('uses_basevertex', ctypes.c_bool), + ('uses_primid', ctypes.c_bool), + ('uses_frontface', ctypes.c_bool), + ('uses_invocationid', ctypes.c_bool), + ('uses_grid_size', ctypes.c_bool), + ('writes_position', ctypes.c_bool), + ('writes_psize', ctypes.c_bool), + ('writes_clipvertex', ctypes.c_bool), + ('writes_viewport_index', ctypes.c_bool), + ('writes_layer', ctypes.c_bool), + ('writes_memory', ctypes.c_bool), + ('uses_fbfetch', ctypes.c_bool), + ('num_written_culldistance', ctypes.c_uint32), + ('num_written_clipdistance', ctypes.c_uint32), + ('images_declared', ctypes.c_uint32), + ('msaa_images_declared', ctypes.c_uint32), + ('images_buffers', ctypes.c_uint32), + ('shader_buffers_declared', ctypes.c_uint32), + ('shader_buffers_load', ctypes.c_uint32), + ('shader_buffers_store', ctypes.c_uint32), + ('shader_buffers_atomic', ctypes.c_uint32), + ('hw_atomic_declared', ctypes.c_uint32), + ('indirect_files', ctypes.c_uint32), + ('dim_indirect_files', ctypes.c_uint32), + ('properties', (ctypes.c_uint32 * 29)), ] - -struct_lp_build_gs_iface._pack_ = 1 # source:False +class struct_lp_build_gs_iface(Struct): pass struct_lp_build_gs_iface._fields_ = [ - ('fetch_input', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue))), - ('emit_vertex', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue) * 4), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue))), - ('end_primitive', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_uint32)), - ('gs_epilogue', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_uint32)), + ('fetch_input', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, LLVMValueRef)), + ('emit_vertex', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.POINTER((LLVMValueRef * 4)), LLVMValueRef, LLVMValueRef, LLVMValueRef)), + ('end_primitive', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_gs_iface), ctypes.POINTER(struct_lp_build_context), LLVMValueRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32)), + ('gs_epilogue', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_gs_iface), LLVMValueRef, LLVMValueRef, ctypes.c_uint32)), ] - -struct_lp_build_tcs_iface._pack_ = 1 # source:False +class struct_lp_build_tcs_iface(Struct): pass struct_lp_build_tcs_iface._fields_ = [ - ('emit_prologue', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_context))), - ('emit_epilogue', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_context))), - ('emit_barrier', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_context))), - ('emit_store_output', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_tcs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_uint32, ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue))), - ('emit_fetch_input', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_tcs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue))), - ('emit_fetch_output', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_tcs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_uint32)), + ('emit_prologue', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_context))), + ('emit_epilogue', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_context))), + ('emit_barrier', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_context))), + ('emit_store_output', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_tcs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_uint32, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, LLVMValueRef, LLVMValueRef)), + ('emit_fetch_input', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_tcs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef)), + ('emit_fetch_output', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_tcs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, uint32_t)), ] - -struct_lp_build_tes_iface._pack_ = 1 # source:False +class struct_lp_build_tes_iface(Struct): pass struct_lp_build_tes_iface._fields_ = [ - ('fetch_vertex_input', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_tes_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue))), - ('fetch_patch_input', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_tes_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue))), + ('fetch_vertex_input', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_tes_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef)), + ('fetch_patch_input', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_tes_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_bool, LLVMValueRef, LLVMValueRef)), ] - -struct_lp_build_mesh_iface._pack_ = 1 # source:False +class struct_lp_build_mesh_iface(Struct): pass struct_lp_build_mesh_iface._fields_ = [ - ('emit_store_output', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_mesh_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_uint32, ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue))), - ('emit_vertex_and_primitive_count', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_mesh_iface), ctypes.POINTER(struct_lp_build_context), ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_LLVMOpaqueValue))), + ('emit_store_output', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_mesh_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_uint32, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, ctypes.c_bool, LLVMValueRef, LLVMValueRef, LLVMValueRef)), + ('emit_vertex_and_primitive_count', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_mesh_iface), ctypes.POINTER(struct_lp_build_context), LLVMValueRef, LLVMValueRef)), ] +class struct_lp_build_image_soa(Struct): pass +class struct_lp_img_params(Struct): pass +LLVMAtomicRMWBinOp = CEnum(ctypes.c_uint32) +LLVMAtomicRMWBinOpXchg = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpXchg', 0) +LLVMAtomicRMWBinOpAdd = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpAdd', 1) +LLVMAtomicRMWBinOpSub = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpSub', 2) +LLVMAtomicRMWBinOpAnd = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpAnd', 3) +LLVMAtomicRMWBinOpNand = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpNand', 4) +LLVMAtomicRMWBinOpOr = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpOr', 5) +LLVMAtomicRMWBinOpXor = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpXor', 6) +LLVMAtomicRMWBinOpMax = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpMax', 7) +LLVMAtomicRMWBinOpMin = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpMin', 8) +LLVMAtomicRMWBinOpUMax = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUMax', 9) +LLVMAtomicRMWBinOpUMin = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUMin', 10) +LLVMAtomicRMWBinOpFAdd = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFAdd', 11) +LLVMAtomicRMWBinOpFSub = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFSub', 12) +LLVMAtomicRMWBinOpFMax = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFMax', 13) +LLVMAtomicRMWBinOpFMin = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpFMin', 14) +LLVMAtomicRMWBinOpUIncWrap = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUIncWrap', 15) +LLVMAtomicRMWBinOpUDecWrap = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUDecWrap', 16) +LLVMAtomicRMWBinOpUSubCond = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUSubCond', 17) +LLVMAtomicRMWBinOpUSubSat = LLVMAtomicRMWBinOp.define('LLVMAtomicRMWBinOpUSubSat', 18) -class struct_lp_img_params(Structure): - pass - -struct_lp_build_image_soa._pack_ = 1 # source:False -struct_lp_build_image_soa._fields_ = [ - ('emit_op', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_image_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_img_params))), - ('emit_size_query', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_image_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_size_query_params))), -] - - -# values for enumeration 'c__EA_LLVMAtomicRMWBinOp' -c__EA_LLVMAtomicRMWBinOp__enumvalues = { - 0: 'LLVMAtomicRMWBinOpXchg', - 1: 'LLVMAtomicRMWBinOpAdd', - 2: 'LLVMAtomicRMWBinOpSub', - 3: 'LLVMAtomicRMWBinOpAnd', - 4: 'LLVMAtomicRMWBinOpNand', - 5: 'LLVMAtomicRMWBinOpOr', - 6: 'LLVMAtomicRMWBinOpXor', - 7: 'LLVMAtomicRMWBinOpMax', - 8: 'LLVMAtomicRMWBinOpMin', - 9: 'LLVMAtomicRMWBinOpUMax', - 10: 'LLVMAtomicRMWBinOpUMin', - 11: 'LLVMAtomicRMWBinOpFAdd', - 12: 'LLVMAtomicRMWBinOpFSub', - 13: 'LLVMAtomicRMWBinOpFMax', - 14: 'LLVMAtomicRMWBinOpFMin', - 15: 'LLVMAtomicRMWBinOpUIncWrap', - 16: 'LLVMAtomicRMWBinOpUDecWrap', - 17: 'LLVMAtomicRMWBinOpUSubCond', - 18: 'LLVMAtomicRMWBinOpUSubSat', -} -LLVMAtomicRMWBinOpXchg = 0 -LLVMAtomicRMWBinOpAdd = 1 -LLVMAtomicRMWBinOpSub = 2 -LLVMAtomicRMWBinOpAnd = 3 -LLVMAtomicRMWBinOpNand = 4 -LLVMAtomicRMWBinOpOr = 5 -LLVMAtomicRMWBinOpXor = 6 -LLVMAtomicRMWBinOpMax = 7 -LLVMAtomicRMWBinOpMin = 8 -LLVMAtomicRMWBinOpUMax = 9 -LLVMAtomicRMWBinOpUMin = 10 -LLVMAtomicRMWBinOpFAdd = 11 -LLVMAtomicRMWBinOpFSub = 12 -LLVMAtomicRMWBinOpFMax = 13 -LLVMAtomicRMWBinOpFMin = 14 -LLVMAtomicRMWBinOpUIncWrap = 15 -LLVMAtomicRMWBinOpUDecWrap = 16 -LLVMAtomicRMWBinOpUSubCond = 17 -LLVMAtomicRMWBinOpUSubSat = 18 -c__EA_LLVMAtomicRMWBinOp = ctypes.c_uint32 # enum -struct_lp_img_params._pack_ = 1 # source:False struct_lp_img_params._fields_ = [ - ('type', struct_lp_type), - ('image_index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('image_index_offset', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('img_op', ctypes.c_uint32), - ('target', ctypes.c_uint32), - ('packed_op', ctypes.c_uint32), - ('op', c__EA_LLVMAtomicRMWBinOp), - ('exec_mask', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('exec_mask_nz', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 7), - ('resources_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('resources_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('thread_data_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('thread_data_ptr', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('coords', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))), - ('ms_index', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('indata', ctypes.POINTER(struct_LLVMOpaqueValue) * 4), - ('indata2', ctypes.POINTER(struct_LLVMOpaqueValue) * 4), - ('outdata', ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue))), - ('resource', ctypes.POINTER(struct_LLVMOpaqueValue)), - ('format', pipe_format), - ('PADDING_2', ctypes.c_ubyte * 4), + ('type', struct_lp_type), + ('image_index', ctypes.c_uint32), + ('image_index_offset', LLVMValueRef), + ('img_op', ctypes.c_uint32), + ('target', ctypes.c_uint32), + ('packed_op', ctypes.c_uint32), + ('op', LLVMAtomicRMWBinOp), + ('exec_mask', LLVMValueRef), + ('exec_mask_nz', ctypes.c_bool), + ('resources_type', LLVMTypeRef), + ('resources_ptr', LLVMValueRef), + ('thread_data_type', LLVMTypeRef), + ('thread_data_ptr', LLVMValueRef), + ('coords', ctypes.POINTER(LLVMValueRef)), + ('ms_index', LLVMValueRef), + ('indata', (LLVMValueRef * 4)), + ('indata2', (LLVMValueRef * 4)), + ('outdata', ctypes.POINTER(LLVMValueRef)), + ('resource', LLVMValueRef), + ('format', enum_pipe_format), ] - -struct_lp_build_fs_iface._pack_ = 1 # source:False +struct_lp_build_image_soa._fields_ = [ + ('emit_op', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_image_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_img_params))), + ('emit_size_query', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_image_soa), ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_size_query_params))), +] +class struct_lp_build_coro_suspend_info(Struct): pass +class struct_lp_build_fs_iface(Struct): pass struct_lp_build_fs_iface._fields_ = [ - ('interp_fn', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_fs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool, ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)))), - ('fb_fetch', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_fs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)))), + ('interp_fn', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_fs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, ctypes.c_bool, LLVMValueRef, (LLVMValueRef * 2))), + ('fb_fetch', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_lp_build_fs_iface), ctypes.POINTER(struct_lp_build_context), ctypes.c_int32, (LLVMValueRef * 4))), ] +struct_lp_build_tgsi_params._fields_ = [ + ('type', struct_lp_type), + ('mask', ctypes.POINTER(struct_lp_build_mask_context)), + ('consts_ptr', LLVMValueRef), + ('const_sizes_ptr', LLVMValueRef), + ('system_values', ctypes.POINTER(struct_lp_bld_tgsi_system_values)), + ('inputs', ctypes.POINTER((LLVMValueRef * 4))), + ('num_inputs', ctypes.c_int32), + ('context_type', LLVMTypeRef), + ('context_ptr', LLVMValueRef), + ('resources_type', LLVMTypeRef), + ('resources_ptr', LLVMValueRef), + ('thread_data_type', LLVMTypeRef), + ('thread_data_ptr', LLVMValueRef), + ('sampler', ctypes.POINTER(struct_lp_build_sampler_soa)), + ('info', ctypes.POINTER(struct_tgsi_shader_info)), + ('gs_iface', ctypes.POINTER(struct_lp_build_gs_iface)), + ('tcs_iface', ctypes.POINTER(struct_lp_build_tcs_iface)), + ('tes_iface', ctypes.POINTER(struct_lp_build_tes_iface)), + ('mesh_iface', ctypes.POINTER(struct_lp_build_mesh_iface)), + ('ssbo_ptr', LLVMValueRef), + ('ssbo_sizes_ptr', LLVMValueRef), + ('image', ctypes.POINTER(struct_lp_build_image_soa)), + ('shared_ptr', LLVMValueRef), + ('payload_ptr', LLVMValueRef), + ('coro', ctypes.POINTER(struct_lp_build_coro_suspend_info)), + ('fs_iface', ctypes.POINTER(struct_lp_build_fs_iface)), + ('gs_vertex_streams', ctypes.c_uint32), + ('current_func', LLVMValueRef), + ('fns', ctypes.POINTER(struct_hash_table)), + ('scratch_ptr', LLVMValueRef), + ('call_context_ptr', LLVMValueRef), +] +# void lp_build_nir_soa(struct gallivm_state *gallivm, struct nir_shader *shader, const struct lp_build_tgsi_params *params, LLVMValueRef (*outputs)[4]) +try: (lp_build_nir_soa:=dll.lp_build_nir_soa).restype, lp_build_nir_soa.argtypes = None, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_lp_build_tgsi_params), ctypes.POINTER((LLVMValueRef * 4))] +except AttributeError: pass -try: - lp_build_nir_soa = _libraries['libtinymesa_cpu.so'].lp_build_nir_soa - lp_build_nir_soa.restype = None - lp_build_nir_soa.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_lp_build_tgsi_params), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue) * 4)] -except AttributeError: - pass -try: - lp_build_nir_soa_func = _libraries['libtinymesa_cpu.so'].lp_build_nir_soa_func - lp_build_nir_soa_func.restype = None - lp_build_nir_soa_func.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_nir_shader), ctypes.POINTER(struct_nir_function_impl), ctypes.POINTER(struct_lp_build_tgsi_params), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue) * 4)] -except AttributeError: - pass -class struct_lp_build_sampler_aos(Structure): - pass +# void lp_build_nir_soa_func(struct gallivm_state *gallivm, struct nir_shader *shader, nir_function_impl *impl, const struct lp_build_tgsi_params *params, LLVMValueRef (*outputs)[4]) +try: (lp_build_nir_soa_func:=dll.lp_build_nir_soa_func).restype, lp_build_nir_soa_func.argtypes = None, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_nir_shader), ctypes.POINTER(nir_function_impl), ctypes.POINTER(struct_lp_build_tgsi_params), ctypes.POINTER((LLVMValueRef * 4))] +except AttributeError: pass +class struct_lp_build_sampler_aos(Struct): pass +enum_tgsi_texture_type = CEnum(ctypes.c_uint32) +TGSI_TEXTURE_BUFFER = enum_tgsi_texture_type.define('TGSI_TEXTURE_BUFFER', 0) +TGSI_TEXTURE_1D = enum_tgsi_texture_type.define('TGSI_TEXTURE_1D', 1) +TGSI_TEXTURE_2D = enum_tgsi_texture_type.define('TGSI_TEXTURE_2D', 2) +TGSI_TEXTURE_3D = enum_tgsi_texture_type.define('TGSI_TEXTURE_3D', 3) +TGSI_TEXTURE_CUBE = enum_tgsi_texture_type.define('TGSI_TEXTURE_CUBE', 4) +TGSI_TEXTURE_RECT = enum_tgsi_texture_type.define('TGSI_TEXTURE_RECT', 5) +TGSI_TEXTURE_SHADOW1D = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOW1D', 6) +TGSI_TEXTURE_SHADOW2D = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOW2D', 7) +TGSI_TEXTURE_SHADOWRECT = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOWRECT', 8) +TGSI_TEXTURE_1D_ARRAY = enum_tgsi_texture_type.define('TGSI_TEXTURE_1D_ARRAY', 9) +TGSI_TEXTURE_2D_ARRAY = enum_tgsi_texture_type.define('TGSI_TEXTURE_2D_ARRAY', 10) +TGSI_TEXTURE_SHADOW1D_ARRAY = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOW1D_ARRAY', 11) +TGSI_TEXTURE_SHADOW2D_ARRAY = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOW2D_ARRAY', 12) +TGSI_TEXTURE_SHADOWCUBE = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOWCUBE', 13) +TGSI_TEXTURE_2D_MSAA = enum_tgsi_texture_type.define('TGSI_TEXTURE_2D_MSAA', 14) +TGSI_TEXTURE_2D_ARRAY_MSAA = enum_tgsi_texture_type.define('TGSI_TEXTURE_2D_ARRAY_MSAA', 15) +TGSI_TEXTURE_CUBE_ARRAY = enum_tgsi_texture_type.define('TGSI_TEXTURE_CUBE_ARRAY', 16) +TGSI_TEXTURE_SHADOWCUBE_ARRAY = enum_tgsi_texture_type.define('TGSI_TEXTURE_SHADOWCUBE_ARRAY', 17) +TGSI_TEXTURE_UNKNOWN = enum_tgsi_texture_type.define('TGSI_TEXTURE_UNKNOWN', 18) +TGSI_TEXTURE_COUNT = enum_tgsi_texture_type.define('TGSI_TEXTURE_COUNT', 19) -# values for enumeration 'tgsi_texture_type' -tgsi_texture_type__enumvalues = { - 0: 'TGSI_TEXTURE_BUFFER', - 1: 'TGSI_TEXTURE_1D', - 2: 'TGSI_TEXTURE_2D', - 3: 'TGSI_TEXTURE_3D', - 4: 'TGSI_TEXTURE_CUBE', - 5: 'TGSI_TEXTURE_RECT', - 6: 'TGSI_TEXTURE_SHADOW1D', - 7: 'TGSI_TEXTURE_SHADOW2D', - 8: 'TGSI_TEXTURE_SHADOWRECT', - 9: 'TGSI_TEXTURE_1D_ARRAY', - 10: 'TGSI_TEXTURE_2D_ARRAY', - 11: 'TGSI_TEXTURE_SHADOW1D_ARRAY', - 12: 'TGSI_TEXTURE_SHADOW2D_ARRAY', - 13: 'TGSI_TEXTURE_SHADOWCUBE', - 14: 'TGSI_TEXTURE_2D_MSAA', - 15: 'TGSI_TEXTURE_2D_ARRAY_MSAA', - 16: 'TGSI_TEXTURE_CUBE_ARRAY', - 17: 'TGSI_TEXTURE_SHADOWCUBE_ARRAY', - 18: 'TGSI_TEXTURE_UNKNOWN', - 19: 'TGSI_TEXTURE_COUNT', -} -TGSI_TEXTURE_BUFFER = 0 -TGSI_TEXTURE_1D = 1 -TGSI_TEXTURE_2D = 2 -TGSI_TEXTURE_3D = 3 -TGSI_TEXTURE_CUBE = 4 -TGSI_TEXTURE_RECT = 5 -TGSI_TEXTURE_SHADOW1D = 6 -TGSI_TEXTURE_SHADOW2D = 7 -TGSI_TEXTURE_SHADOWRECT = 8 -TGSI_TEXTURE_1D_ARRAY = 9 -TGSI_TEXTURE_2D_ARRAY = 10 -TGSI_TEXTURE_SHADOW1D_ARRAY = 11 -TGSI_TEXTURE_SHADOW2D_ARRAY = 12 -TGSI_TEXTURE_SHADOWCUBE = 13 -TGSI_TEXTURE_2D_MSAA = 14 -TGSI_TEXTURE_2D_ARRAY_MSAA = 15 -TGSI_TEXTURE_CUBE_ARRAY = 16 -TGSI_TEXTURE_SHADOWCUBE_ARRAY = 17 -TGSI_TEXTURE_UNKNOWN = 18 -TGSI_TEXTURE_COUNT = 19 -tgsi_texture_type = ctypes.c_uint32 # enum +enum_lp_build_tex_modifier = CEnum(ctypes.c_uint32) +LP_BLD_TEX_MODIFIER_NONE = enum_lp_build_tex_modifier.define('LP_BLD_TEX_MODIFIER_NONE', 0) +LP_BLD_TEX_MODIFIER_PROJECTED = enum_lp_build_tex_modifier.define('LP_BLD_TEX_MODIFIER_PROJECTED', 1) +LP_BLD_TEX_MODIFIER_LOD_BIAS = enum_lp_build_tex_modifier.define('LP_BLD_TEX_MODIFIER_LOD_BIAS', 2) +LP_BLD_TEX_MODIFIER_EXPLICIT_LOD = enum_lp_build_tex_modifier.define('LP_BLD_TEX_MODIFIER_EXPLICIT_LOD', 3) +LP_BLD_TEX_MODIFIER_EXPLICIT_DERIV = enum_lp_build_tex_modifier.define('LP_BLD_TEX_MODIFIER_EXPLICIT_DERIV', 4) +LP_BLD_TEX_MODIFIER_LOD_ZERO = enum_lp_build_tex_modifier.define('LP_BLD_TEX_MODIFIER_LOD_ZERO', 5) -# values for enumeration 'lp_build_tex_modifier' -lp_build_tex_modifier__enumvalues = { - 0: 'LP_BLD_TEX_MODIFIER_NONE', - 1: 'LP_BLD_TEX_MODIFIER_PROJECTED', - 2: 'LP_BLD_TEX_MODIFIER_LOD_BIAS', - 3: 'LP_BLD_TEX_MODIFIER_EXPLICIT_LOD', - 4: 'LP_BLD_TEX_MODIFIER_EXPLICIT_DERIV', - 5: 'LP_BLD_TEX_MODIFIER_LOD_ZERO', -} -LP_BLD_TEX_MODIFIER_NONE = 0 -LP_BLD_TEX_MODIFIER_PROJECTED = 1 -LP_BLD_TEX_MODIFIER_LOD_BIAS = 2 -LP_BLD_TEX_MODIFIER_EXPLICIT_LOD = 3 -LP_BLD_TEX_MODIFIER_EXPLICIT_DERIV = 4 -LP_BLD_TEX_MODIFIER_LOD_ZERO = 5 -lp_build_tex_modifier = ctypes.c_uint32 # enum -struct_lp_build_sampler_aos._pack_ = 1 # source:False struct_lp_build_sampler_aos._fields_ = [ - ('emit_fetch_texel', ctypes.CFUNCTYPE(ctypes.POINTER(struct_LLVMOpaqueValue), ctypes.POINTER(struct_lp_build_sampler_aos), ctypes.POINTER(struct_lp_build_context), tgsi_texture_type, ctypes.c_uint32, ctypes.POINTER(struct_LLVMOpaqueValue), struct_lp_derivatives, lp_build_tex_modifier)), + ('emit_fetch_texel', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_lp_build_sampler_aos), ctypes.POINTER(struct_lp_build_context), enum_tgsi_texture_type, ctypes.c_uint32, LLVMValueRef, struct_lp_derivatives, enum_lp_build_tex_modifier)), ] +# void lp_build_nir_aos(struct gallivm_state *gallivm, struct nir_shader *shader, struct lp_type type, const unsigned char swizzles[4], LLVMValueRef consts_ptr, const LLVMValueRef *inputs, LLVMValueRef *outputs, const struct lp_build_sampler_aos *sampler) +try: (lp_build_nir_aos:=dll.lp_build_nir_aos).restype, lp_build_nir_aos.argtypes = None, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_nir_shader), struct_lp_type, (ctypes.c_ubyte * 4), LLVMValueRef, ctypes.POINTER(LLVMValueRef), ctypes.POINTER(LLVMValueRef), ctypes.POINTER(struct_lp_build_sampler_aos)] +except AttributeError: pass -try: - lp_build_nir_aos = _libraries['FIXME_STUB'].lp_build_nir_aos - lp_build_nir_aos.restype = None - lp_build_nir_aos.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_nir_shader), struct_lp_type, ctypes.c_ubyte * 4, LLVMValueRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.POINTER(struct_lp_build_sampler_aos)] -except AttributeError: - pass -class struct_lp_build_fn(Structure): - pass - -struct_lp_build_fn._pack_ = 1 # source:False +class struct_lp_build_fn(Struct): pass struct_lp_build_fn._fields_ = [ - ('fn_type', ctypes.POINTER(struct_LLVMOpaqueType)), - ('fn', ctypes.POINTER(struct_LLVMOpaqueValue)), + ('fn_type', LLVMTypeRef), + ('fn', LLVMValueRef), ] +# void lp_build_nir_soa_prepasses(struct nir_shader *nir) +try: (lp_build_nir_soa_prepasses:=dll.lp_build_nir_soa_prepasses).restype, lp_build_nir_soa_prepasses.argtypes = None, [ctypes.POINTER(struct_nir_shader)] +except AttributeError: pass -try: - lp_build_nir_soa_prepasses = _libraries['libtinymesa_cpu.so'].lp_build_nir_soa_prepasses - lp_build_nir_soa_prepasses.restype = None - lp_build_nir_soa_prepasses.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - lp_build_opt_nir = _libraries['libtinymesa_cpu.so'].lp_build_opt_nir - lp_build_opt_nir.restype = None - lp_build_opt_nir.argtypes = [ctypes.POINTER(struct_nir_shader)] -except AttributeError: - pass -try: - lp_nir_array_build_gather_values = _libraries['FIXME_STUB'].lp_nir_array_build_gather_values - lp_nir_array_build_gather_values.restype = LLVMValueRef - lp_nir_array_build_gather_values.argtypes = [LLVMBuilderRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueValue)), ctypes.c_uint32] -except AttributeError: - pass -LLVMAtomicRMWBinOp = c__EA_LLVMAtomicRMWBinOp -LLVMAtomicRMWBinOp__enumvalues = c__EA_LLVMAtomicRMWBinOp__enumvalues -try: - lp_translate_atomic_op = _libraries['libtinymesa_cpu.so'].lp_translate_atomic_op - lp_translate_atomic_op.restype = LLVMAtomicRMWBinOp - lp_translate_atomic_op.argtypes = [nir_atomic_op] -except AttributeError: - pass -try: - lp_build_nir_sample_key = _libraries['libtinymesa_cpu.so'].lp_build_nir_sample_key - lp_build_nir_sample_key.restype = uint32_t - lp_build_nir_sample_key.argtypes = [gl_shader_stage, ctypes.POINTER(struct_nir_tex_instr)] -except AttributeError: - pass -try: - lp_img_op_from_intrinsic = _libraries['libtinymesa_cpu.so'].lp_img_op_from_intrinsic - lp_img_op_from_intrinsic.restype = None - lp_img_op_from_intrinsic.argtypes = [ctypes.POINTER(struct_lp_img_params), ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass -try: - lp_packed_img_op_from_intrinsic = _libraries['libtinymesa_cpu.so'].lp_packed_img_op_from_intrinsic - lp_packed_img_op_from_intrinsic.restype = uint32_t - lp_packed_img_op_from_intrinsic.argtypes = [ctypes.POINTER(struct_nir_intrinsic_instr)] -except AttributeError: - pass +# void lp_build_opt_nir(struct nir_shader *nir) +try: (lp_build_opt_nir:=dll.lp_build_opt_nir).restype, lp_build_opt_nir.argtypes = None, [ctypes.POINTER(struct_nir_shader)] +except AttributeError: pass -# values for enumeration 'lp_nir_call_context_args' -lp_nir_call_context_args__enumvalues = { - 0: 'LP_NIR_CALL_CONTEXT_CONTEXT', - 1: 'LP_NIR_CALL_CONTEXT_RESOURCES', - 2: 'LP_NIR_CALL_CONTEXT_SHARED', - 3: 'LP_NIR_CALL_CONTEXT_SCRATCH', - 4: 'LP_NIR_CALL_CONTEXT_WORK_DIM', - 5: 'LP_NIR_CALL_CONTEXT_THREAD_ID_0', - 6: 'LP_NIR_CALL_CONTEXT_THREAD_ID_1', - 7: 'LP_NIR_CALL_CONTEXT_THREAD_ID_2', - 8: 'LP_NIR_CALL_CONTEXT_BLOCK_ID_0', - 9: 'LP_NIR_CALL_CONTEXT_BLOCK_ID_1', - 10: 'LP_NIR_CALL_CONTEXT_BLOCK_ID_2', - 11: 'LP_NIR_CALL_CONTEXT_GRID_SIZE_0', - 12: 'LP_NIR_CALL_CONTEXT_GRID_SIZE_1', - 13: 'LP_NIR_CALL_CONTEXT_GRID_SIZE_2', - 14: 'LP_NIR_CALL_CONTEXT_BLOCK_SIZE_0', - 15: 'LP_NIR_CALL_CONTEXT_BLOCK_SIZE_1', - 16: 'LP_NIR_CALL_CONTEXT_BLOCK_SIZE_2', - 17: 'LP_NIR_CALL_CONTEXT_MAX_ARGS', -} -LP_NIR_CALL_CONTEXT_CONTEXT = 0 -LP_NIR_CALL_CONTEXT_RESOURCES = 1 -LP_NIR_CALL_CONTEXT_SHARED = 2 -LP_NIR_CALL_CONTEXT_SCRATCH = 3 -LP_NIR_CALL_CONTEXT_WORK_DIM = 4 -LP_NIR_CALL_CONTEXT_THREAD_ID_0 = 5 -LP_NIR_CALL_CONTEXT_THREAD_ID_1 = 6 -LP_NIR_CALL_CONTEXT_THREAD_ID_2 = 7 -LP_NIR_CALL_CONTEXT_BLOCK_ID_0 = 8 -LP_NIR_CALL_CONTEXT_BLOCK_ID_1 = 9 -LP_NIR_CALL_CONTEXT_BLOCK_ID_2 = 10 -LP_NIR_CALL_CONTEXT_GRID_SIZE_0 = 11 -LP_NIR_CALL_CONTEXT_GRID_SIZE_1 = 12 -LP_NIR_CALL_CONTEXT_GRID_SIZE_2 = 13 -LP_NIR_CALL_CONTEXT_BLOCK_SIZE_0 = 14 -LP_NIR_CALL_CONTEXT_BLOCK_SIZE_1 = 15 -LP_NIR_CALL_CONTEXT_BLOCK_SIZE_2 = 16 -LP_NIR_CALL_CONTEXT_MAX_ARGS = 17 -lp_nir_call_context_args = ctypes.c_uint32 # enum -try: - lp_build_cs_func_call_context = _libraries['libtinymesa_cpu.so'].lp_build_cs_func_call_context - lp_build_cs_func_call_context.restype = LLVMTypeRef - lp_build_cs_func_call_context.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.c_int32, LLVMTypeRef, LLVMTypeRef] -except AttributeError: - pass -try: - lp_build_struct_get_ptr2 = _libraries['libtinymesa_cpu.so'].lp_build_struct_get_ptr2 - lp_build_struct_get_ptr2.restype = LLVMValueRef - lp_build_struct_get_ptr2.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_build_struct_get2 = _libraries['libtinymesa_cpu.so'].lp_build_struct_get2 - lp_build_struct_get2.restype = LLVMValueRef - lp_build_struct_get2.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_build_array_get_ptr2 = _libraries['libtinymesa_cpu.so'].lp_build_array_get_ptr2 - lp_build_array_get_ptr2.restype = LLVMValueRef - lp_build_array_get_ptr2.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_array_get2 = _libraries['libtinymesa_cpu.so'].lp_build_array_get2 - lp_build_array_get2.restype = LLVMValueRef - lp_build_array_get2.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_pointer_get2 = _libraries['libtinymesa_cpu.so'].lp_build_pointer_get2 - lp_build_pointer_get2.restype = LLVMValueRef - lp_build_pointer_get2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_pointer_get_unaligned2 = _libraries['libtinymesa_cpu.so'].lp_build_pointer_get_unaligned2 - lp_build_pointer_get_unaligned2.restype = LLVMValueRef - lp_build_pointer_get_unaligned2.argtypes = [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_build_pointer_set = _libraries['libtinymesa_cpu.so'].lp_build_pointer_set - lp_build_pointer_set.restype = None - lp_build_pointer_set.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef] -except AttributeError: - pass -try: - lp_build_pointer_set_unaligned = _libraries['libtinymesa_cpu.so'].lp_build_pointer_set_unaligned - lp_build_pointer_set_unaligned.restype = None - lp_build_pointer_set_unaligned.argtypes = [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -class struct_lp_jit_buffer(Structure): - pass +# LLVMAtomicRMWBinOp lp_translate_atomic_op(nir_atomic_op op) +try: (lp_translate_atomic_op:=dll.lp_translate_atomic_op).restype, lp_translate_atomic_op.argtypes = LLVMAtomicRMWBinOp, [nir_atomic_op] +except AttributeError: pass -class union_lp_jit_buffer_0(Union): - pass +# uint32_t lp_build_nir_sample_key(gl_shader_stage stage, nir_tex_instr *instr) +try: (lp_build_nir_sample_key:=dll.lp_build_nir_sample_key).restype, lp_build_nir_sample_key.argtypes = uint32_t, [gl_shader_stage, ctypes.POINTER(nir_tex_instr)] +except AttributeError: pass -union_lp_jit_buffer_0._pack_ = 1 # source:False -union_lp_jit_buffer_0._fields_ = [ - ('u', ctypes.POINTER(ctypes.c_uint32)), - ('f', ctypes.POINTER(ctypes.c_float)), +# void lp_img_op_from_intrinsic(struct lp_img_params *params, nir_intrinsic_instr *instr) +try: (lp_img_op_from_intrinsic:=dll.lp_img_op_from_intrinsic).restype, lp_img_op_from_intrinsic.argtypes = None, [ctypes.POINTER(struct_lp_img_params), ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +# uint32_t lp_packed_img_op_from_intrinsic(nir_intrinsic_instr *instr) +try: (lp_packed_img_op_from_intrinsic:=dll.lp_packed_img_op_from_intrinsic).restype, lp_packed_img_op_from_intrinsic.argtypes = uint32_t, [ctypes.POINTER(nir_intrinsic_instr)] +except AttributeError: pass + +enum_lp_nir_call_context_args = CEnum(ctypes.c_uint32) +LP_NIR_CALL_CONTEXT_CONTEXT = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_CONTEXT', 0) +LP_NIR_CALL_CONTEXT_RESOURCES = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_RESOURCES', 1) +LP_NIR_CALL_CONTEXT_SHARED = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_SHARED', 2) +LP_NIR_CALL_CONTEXT_SCRATCH = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_SCRATCH', 3) +LP_NIR_CALL_CONTEXT_WORK_DIM = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_WORK_DIM', 4) +LP_NIR_CALL_CONTEXT_THREAD_ID_0 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_THREAD_ID_0', 5) +LP_NIR_CALL_CONTEXT_THREAD_ID_1 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_THREAD_ID_1', 6) +LP_NIR_CALL_CONTEXT_THREAD_ID_2 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_THREAD_ID_2', 7) +LP_NIR_CALL_CONTEXT_BLOCK_ID_0 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_BLOCK_ID_0', 8) +LP_NIR_CALL_CONTEXT_BLOCK_ID_1 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_BLOCK_ID_1', 9) +LP_NIR_CALL_CONTEXT_BLOCK_ID_2 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_BLOCK_ID_2', 10) +LP_NIR_CALL_CONTEXT_GRID_SIZE_0 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_GRID_SIZE_0', 11) +LP_NIR_CALL_CONTEXT_GRID_SIZE_1 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_GRID_SIZE_1', 12) +LP_NIR_CALL_CONTEXT_GRID_SIZE_2 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_GRID_SIZE_2', 13) +LP_NIR_CALL_CONTEXT_BLOCK_SIZE_0 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_BLOCK_SIZE_0', 14) +LP_NIR_CALL_CONTEXT_BLOCK_SIZE_1 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_BLOCK_SIZE_1', 15) +LP_NIR_CALL_CONTEXT_BLOCK_SIZE_2 = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_BLOCK_SIZE_2', 16) +LP_NIR_CALL_CONTEXT_MAX_ARGS = enum_lp_nir_call_context_args.define('LP_NIR_CALL_CONTEXT_MAX_ARGS', 17) + +# LLVMTypeRef lp_build_cs_func_call_context(struct gallivm_state *gallivm, int length, LLVMTypeRef context_type, LLVMTypeRef resources_type) +try: (lp_build_cs_func_call_context:=dll.lp_build_cs_func_call_context).restype, lp_build_cs_func_call_context.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), ctypes.c_int32, LLVMTypeRef, LLVMTypeRef] +except AttributeError: pass + +# LLVMValueRef lp_build_struct_get_ptr2(struct gallivm_state *gallivm, LLVMTypeRef ptr_type, LLVMValueRef ptr, unsigned int member, const char *name) +try: (lp_build_struct_get_ptr2:=dll.lp_build_struct_get_ptr2).restype, lp_build_struct_get_ptr2.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef lp_build_struct_get2(struct gallivm_state *gallivm, LLVMTypeRef ptr_type, LLVMValueRef ptr, unsigned int member, const char *name) +try: (lp_build_struct_get2:=dll.lp_build_struct_get2).restype, lp_build_struct_get2.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef lp_build_array_get_ptr2(struct gallivm_state *gallivm, LLVMTypeRef array_type, LLVMValueRef ptr, LLVMValueRef index) +try: (lp_build_array_get_ptr2:=dll.lp_build_array_get_ptr2).restype, lp_build_array_get_ptr2.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef lp_build_array_get2(struct gallivm_state *gallivm, LLVMTypeRef array_type, LLVMValueRef ptr, LLVMValueRef index) +try: (lp_build_array_get2:=dll.lp_build_array_get2).restype, lp_build_array_get2.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef lp_build_pointer_get2(LLVMBuilderRef builder, LLVMTypeRef ptr_type, LLVMValueRef ptr, LLVMValueRef index) +try: (lp_build_pointer_get2:=dll.lp_build_pointer_get2).restype, lp_build_pointer_get2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef lp_build_pointer_get_unaligned2(LLVMBuilderRef builder, LLVMTypeRef ptr_type, LLVMValueRef ptr, LLVMValueRef index, unsigned int alignment) +try: (lp_build_pointer_get_unaligned2:=dll.lp_build_pointer_get_unaligned2).restype, lp_build_pointer_get_unaligned2.argtypes = LLVMValueRef, [LLVMBuilderRef, LLVMTypeRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +# void lp_build_pointer_set(LLVMBuilderRef builder, LLVMValueRef ptr, LLVMValueRef index, LLVMValueRef value) +try: (lp_build_pointer_set:=dll.lp_build_pointer_set).restype, lp_build_pointer_set.argtypes = None, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# void lp_build_pointer_set_unaligned(LLVMBuilderRef builder, LLVMValueRef ptr, LLVMValueRef index, LLVMValueRef value, unsigned int alignment) +try: (lp_build_pointer_set_unaligned:=dll.lp_build_pointer_set_unaligned).restype, lp_build_pointer_set_unaligned.argtypes = None, [LLVMBuilderRef, LLVMValueRef, LLVMValueRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass + +class struct_lp_sampler_dynamic_state(Struct): pass +struct_lp_sampler_dynamic_state._fields_ = [ + ('width', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('height', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('depth', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('first_level', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('last_level', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('row_stride', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.POINTER(LLVMTypeRef))), + ('img_stride', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.POINTER(LLVMTypeRef))), + ('base_ptr', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('mip_offsets', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef, ctypes.POINTER(LLVMTypeRef))), + ('num_samples', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('sample_stride', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('min_lod', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32)), + ('max_lod', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32)), + ('lod_bias', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32)), + ('border_color', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32)), + ('cache_ptr', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32)), + ('residency', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), + ('base_offset', ctypes.CFUNCTYPE(LLVMValueRef, ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.c_uint32, LLVMValueRef)), ] - -struct_lp_jit_buffer._pack_ = 1 # source:False -struct_lp_jit_buffer._anonymous_ = ('_0',) +class struct_lp_jit_buffer(Struct): pass +class struct_lp_jit_buffer_0(ctypes.Union): pass +struct_lp_jit_buffer_0._fields_ = [ + ('u', ctypes.POINTER(uint32_t)), + ('f', ctypes.POINTER(ctypes.c_float)), +] +struct_lp_jit_buffer._anonymous_ = ['_0'] struct_lp_jit_buffer._fields_ = [ - ('_0', union_lp_jit_buffer_0), - ('num_elements', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('_0', struct_lp_jit_buffer_0), + ('num_elements', uint32_t), ] +_anonenum0 = CEnum(ctypes.c_uint32) +LP_JIT_BUFFER_BASE = _anonenum0.define('LP_JIT_BUFFER_BASE', 0) +LP_JIT_BUFFER_NUM_ELEMENTS = _anonenum0.define('LP_JIT_BUFFER_NUM_ELEMENTS', 1) +LP_JIT_BUFFER_NUM_FIELDS = _anonenum0.define('LP_JIT_BUFFER_NUM_FIELDS', 2) +# LLVMValueRef lp_llvm_descriptor_base(struct gallivm_state *gallivm, LLVMValueRef buffers_ptr, LLVMValueRef index, unsigned int buffers_limit) +try: (lp_llvm_descriptor_base:=dll.lp_llvm_descriptor_base).restype, lp_llvm_descriptor_base.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass -# values for enumeration 'c__Ea_LP_JIT_BUFFER_BASE' -c__Ea_LP_JIT_BUFFER_BASE__enumvalues = { - 0: 'LP_JIT_BUFFER_BASE', - 1: 'LP_JIT_BUFFER_NUM_ELEMENTS', - 2: 'LP_JIT_BUFFER_NUM_FIELDS', -} -LP_JIT_BUFFER_BASE = 0 -LP_JIT_BUFFER_NUM_ELEMENTS = 1 -LP_JIT_BUFFER_NUM_FIELDS = 2 -c__Ea_LP_JIT_BUFFER_BASE = ctypes.c_uint32 # enum -try: - lp_llvm_descriptor_base = _libraries['libtinymesa_cpu.so'].lp_llvm_descriptor_base - lp_llvm_descriptor_base.restype = LLVMValueRef - lp_llvm_descriptor_base.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_llvm_buffer_base = _libraries['libtinymesa_cpu.so'].lp_llvm_buffer_base - lp_llvm_buffer_base.restype = LLVMValueRef - lp_llvm_buffer_base.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_llvm_buffer_num_elements = _libraries['libtinymesa_cpu.so'].lp_llvm_buffer_num_elements - lp_llvm_buffer_num_elements.restype = LLVMValueRef - lp_llvm_buffer_num_elements.argtypes = [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMValueRef, ctypes.c_uint32] -except AttributeError: - pass +# LLVMValueRef lp_llvm_buffer_base(struct gallivm_state *gallivm, LLVMValueRef buffers_ptr, LLVMValueRef buffers_offset, unsigned int buffers_limit) +try: (lp_llvm_buffer_base:=dll.lp_llvm_buffer_base).restype, lp_llvm_buffer_base.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass -# values for enumeration 'c__Ea_LP_JIT_TEXTURE_BASE' -c__Ea_LP_JIT_TEXTURE_BASE__enumvalues = { - 0: 'LP_JIT_TEXTURE_BASE', - 1: 'LP_JIT_TEXTURE_WIDTH', - 2: 'LP_JIT_TEXTURE_HEIGHT', - 3: 'LP_JIT_TEXTURE_DEPTH', - 4: 'LP_JIT_TEXTURE_ROW_STRIDE', - 5: 'LP_JIT_TEXTURE_IMG_STRIDE', - 6: 'LP_JIT_TEXTURE_FIRST_LEVEL', - 7: 'LP_JIT_TEXTURE_LAST_LEVEL', - 8: 'LP_JIT_TEXTURE_MIP_OFFSETS', - 9: 'LP_JIT_SAMPLER_INDEX_DUMMY', - 10: 'LP_JIT_TEXTURE_NUM_FIELDS', -} -LP_JIT_TEXTURE_BASE = 0 -LP_JIT_TEXTURE_WIDTH = 1 -LP_JIT_TEXTURE_HEIGHT = 2 -LP_JIT_TEXTURE_DEPTH = 3 -LP_JIT_TEXTURE_ROW_STRIDE = 4 -LP_JIT_TEXTURE_IMG_STRIDE = 5 -LP_JIT_TEXTURE_FIRST_LEVEL = 6 -LP_JIT_TEXTURE_LAST_LEVEL = 7 -LP_JIT_TEXTURE_MIP_OFFSETS = 8 -LP_JIT_SAMPLER_INDEX_DUMMY = 9 -LP_JIT_TEXTURE_NUM_FIELDS = 10 -c__Ea_LP_JIT_TEXTURE_BASE = ctypes.c_uint32 # enum -class struct_lp_jit_sampler(Structure): - pass +# LLVMValueRef lp_llvm_buffer_num_elements(struct gallivm_state *gallivm, LLVMValueRef buffers_ptr, LLVMValueRef buffers_offset, unsigned int buffers_limit) +try: (lp_llvm_buffer_num_elements:=dll.lp_llvm_buffer_num_elements).restype, lp_llvm_buffer_num_elements.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMValueRef, ctypes.c_uint32] +except AttributeError: pass -struct_lp_jit_sampler._pack_ = 1 # source:False +class struct_lp_jit_texture_0(ctypes.Union): pass +class struct_lp_jit_texture_0_0(Struct): pass +struct_lp_jit_texture_0_0._fields_ = [ + ('row_stride', (uint32_t * 16)), + ('img_stride', (uint32_t * 16)), +] +struct_lp_jit_texture_0._anonymous_ = ['_0'] +struct_lp_jit_texture_0._fields_ = [ + ('_0', struct_lp_jit_texture_0_0), + ('residency', ctypes.c_void_p), +] +struct_lp_jit_texture._anonymous_ = ['_0'] +struct_lp_jit_texture._fields_ = [ + ('base', ctypes.c_void_p), + ('width', uint32_t), + ('height', uint16_t), + ('depth', uint16_t), + ('_0', struct_lp_jit_texture_0), + ('first_level', uint8_t), + ('last_level', uint8_t), + ('mip_offsets', (uint32_t * 16)), + ('sampler_index', uint32_t), +] +_anonenum1 = CEnum(ctypes.c_uint32) +LP_JIT_TEXTURE_BASE = _anonenum1.define('LP_JIT_TEXTURE_BASE', 0) +LP_JIT_TEXTURE_WIDTH = _anonenum1.define('LP_JIT_TEXTURE_WIDTH', 1) +LP_JIT_TEXTURE_HEIGHT = _anonenum1.define('LP_JIT_TEXTURE_HEIGHT', 2) +LP_JIT_TEXTURE_DEPTH = _anonenum1.define('LP_JIT_TEXTURE_DEPTH', 3) +LP_JIT_TEXTURE_ROW_STRIDE = _anonenum1.define('LP_JIT_TEXTURE_ROW_STRIDE', 4) +LP_JIT_TEXTURE_IMG_STRIDE = _anonenum1.define('LP_JIT_TEXTURE_IMG_STRIDE', 5) +LP_JIT_TEXTURE_FIRST_LEVEL = _anonenum1.define('LP_JIT_TEXTURE_FIRST_LEVEL', 6) +LP_JIT_TEXTURE_LAST_LEVEL = _anonenum1.define('LP_JIT_TEXTURE_LAST_LEVEL', 7) +LP_JIT_TEXTURE_MIP_OFFSETS = _anonenum1.define('LP_JIT_TEXTURE_MIP_OFFSETS', 8) +LP_JIT_SAMPLER_INDEX_DUMMY = _anonenum1.define('LP_JIT_SAMPLER_INDEX_DUMMY', 9) +LP_JIT_TEXTURE_NUM_FIELDS = _anonenum1.define('LP_JIT_TEXTURE_NUM_FIELDS', 10) + +class struct_lp_jit_sampler(Struct): pass struct_lp_jit_sampler._fields_ = [ - ('min_lod', ctypes.c_float), - ('max_lod', ctypes.c_float), - ('lod_bias', ctypes.c_float), - ('border_color', ctypes.c_float * 4), + ('min_lod', ctypes.c_float), + ('max_lod', ctypes.c_float), + ('lod_bias', ctypes.c_float), + ('border_color', (ctypes.c_float * 4)), ] +_anonenum2 = CEnum(ctypes.c_uint32) +LP_JIT_SAMPLER_MIN_LOD = _anonenum2.define('LP_JIT_SAMPLER_MIN_LOD', 0) +LP_JIT_SAMPLER_MAX_LOD = _anonenum2.define('LP_JIT_SAMPLER_MAX_LOD', 1) +LP_JIT_SAMPLER_LOD_BIAS = _anonenum2.define('LP_JIT_SAMPLER_LOD_BIAS', 2) +LP_JIT_SAMPLER_BORDER_COLOR = _anonenum2.define('LP_JIT_SAMPLER_BORDER_COLOR', 3) +LP_JIT_SAMPLER_NUM_FIELDS = _anonenum2.define('LP_JIT_SAMPLER_NUM_FIELDS', 4) - -# values for enumeration 'c__Ea_LP_JIT_SAMPLER_MIN_LOD' -c__Ea_LP_JIT_SAMPLER_MIN_LOD__enumvalues = { - 0: 'LP_JIT_SAMPLER_MIN_LOD', - 1: 'LP_JIT_SAMPLER_MAX_LOD', - 2: 'LP_JIT_SAMPLER_LOD_BIAS', - 3: 'LP_JIT_SAMPLER_BORDER_COLOR', - 4: 'LP_JIT_SAMPLER_NUM_FIELDS', -} -LP_JIT_SAMPLER_MIN_LOD = 0 -LP_JIT_SAMPLER_MAX_LOD = 1 -LP_JIT_SAMPLER_LOD_BIAS = 2 -LP_JIT_SAMPLER_BORDER_COLOR = 3 -LP_JIT_SAMPLER_NUM_FIELDS = 4 -c__Ea_LP_JIT_SAMPLER_MIN_LOD = ctypes.c_uint32 # enum -class struct_lp_jit_image(Structure): - pass - -struct_lp_jit_image._pack_ = 1 # source:False +class struct_lp_jit_image(Struct): pass struct_lp_jit_image._fields_ = [ - ('base', ctypes.POINTER(None)), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint16), - ('depth', ctypes.c_uint16), - ('num_samples', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('sample_stride', ctypes.c_uint32), - ('row_stride', ctypes.c_uint32), - ('img_stride', ctypes.c_uint32), - ('residency', ctypes.POINTER(None)), - ('base_offset', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('base', ctypes.c_void_p), + ('width', uint32_t), + ('height', uint16_t), + ('depth', uint16_t), + ('num_samples', uint8_t), + ('sample_stride', uint32_t), + ('row_stride', uint32_t), + ('img_stride', uint32_t), + ('residency', ctypes.c_void_p), + ('base_offset', uint32_t), ] +_anonenum3 = CEnum(ctypes.c_uint32) +LP_JIT_IMAGE_BASE = _anonenum3.define('LP_JIT_IMAGE_BASE', 0) +LP_JIT_IMAGE_WIDTH = _anonenum3.define('LP_JIT_IMAGE_WIDTH', 1) +LP_JIT_IMAGE_HEIGHT = _anonenum3.define('LP_JIT_IMAGE_HEIGHT', 2) +LP_JIT_IMAGE_DEPTH = _anonenum3.define('LP_JIT_IMAGE_DEPTH', 3) +LP_JIT_IMAGE_NUM_SAMPLES = _anonenum3.define('LP_JIT_IMAGE_NUM_SAMPLES', 4) +LP_JIT_IMAGE_SAMPLE_STRIDE = _anonenum3.define('LP_JIT_IMAGE_SAMPLE_STRIDE', 5) +LP_JIT_IMAGE_ROW_STRIDE = _anonenum3.define('LP_JIT_IMAGE_ROW_STRIDE', 6) +LP_JIT_IMAGE_IMG_STRIDE = _anonenum3.define('LP_JIT_IMAGE_IMG_STRIDE', 7) +LP_JIT_IMAGE_RESIDENCY = _anonenum3.define('LP_JIT_IMAGE_RESIDENCY', 8) +LP_JIT_IMAGE_BASE_OFFSET = _anonenum3.define('LP_JIT_IMAGE_BASE_OFFSET', 9) +LP_JIT_IMAGE_NUM_FIELDS = _anonenum3.define('LP_JIT_IMAGE_NUM_FIELDS', 10) +class struct_lp_jit_resources(Struct): pass +struct_lp_jit_resources._fields_ = [ + ('constants', (struct_lp_jit_buffer * 16)), + ('ssbos', (struct_lp_jit_buffer * 32)), + ('textures', (struct_lp_jit_texture * 128)), + ('samplers', (struct_lp_jit_sampler * 32)), + ('images', (struct_lp_jit_image * 64)), +] +_anonenum4 = CEnum(ctypes.c_uint32) +LP_JIT_RES_CONSTANTS = _anonenum4.define('LP_JIT_RES_CONSTANTS', 0) +LP_JIT_RES_SSBOS = _anonenum4.define('LP_JIT_RES_SSBOS', 1) +LP_JIT_RES_TEXTURES = _anonenum4.define('LP_JIT_RES_TEXTURES', 2) +LP_JIT_RES_SAMPLERS = _anonenum4.define('LP_JIT_RES_SAMPLERS', 3) +LP_JIT_RES_IMAGES = _anonenum4.define('LP_JIT_RES_IMAGES', 4) +LP_JIT_RES_COUNT = _anonenum4.define('LP_JIT_RES_COUNT', 5) -# values for enumeration 'c__Ea_LP_JIT_IMAGE_BASE' -c__Ea_LP_JIT_IMAGE_BASE__enumvalues = { - 0: 'LP_JIT_IMAGE_BASE', - 1: 'LP_JIT_IMAGE_WIDTH', - 2: 'LP_JIT_IMAGE_HEIGHT', - 3: 'LP_JIT_IMAGE_DEPTH', - 4: 'LP_JIT_IMAGE_NUM_SAMPLES', - 5: 'LP_JIT_IMAGE_SAMPLE_STRIDE', - 6: 'LP_JIT_IMAGE_ROW_STRIDE', - 7: 'LP_JIT_IMAGE_IMG_STRIDE', - 8: 'LP_JIT_IMAGE_RESIDENCY', - 9: 'LP_JIT_IMAGE_BASE_OFFSET', - 10: 'LP_JIT_IMAGE_NUM_FIELDS', -} -LP_JIT_IMAGE_BASE = 0 -LP_JIT_IMAGE_WIDTH = 1 -LP_JIT_IMAGE_HEIGHT = 2 -LP_JIT_IMAGE_DEPTH = 3 -LP_JIT_IMAGE_NUM_SAMPLES = 4 -LP_JIT_IMAGE_SAMPLE_STRIDE = 5 -LP_JIT_IMAGE_ROW_STRIDE = 6 -LP_JIT_IMAGE_IMG_STRIDE = 7 -LP_JIT_IMAGE_RESIDENCY = 8 -LP_JIT_IMAGE_BASE_OFFSET = 9 -LP_JIT_IMAGE_NUM_FIELDS = 10 -c__Ea_LP_JIT_IMAGE_BASE = ctypes.c_uint32 # enum -class struct_lp_jit_resources(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('constants', struct_lp_jit_buffer * 16), - ('ssbos', struct_lp_jit_buffer * 32), - ('textures', struct_lp_jit_texture * 128), - ('samplers', struct_lp_jit_sampler * 32), - ('images', struct_lp_jit_image * 64), - ] +# LLVMTypeRef lp_build_jit_resources_type(struct gallivm_state *gallivm) +try: (lp_build_jit_resources_type:=dll.lp_build_jit_resources_type).restype, lp_build_jit_resources_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass +_anonenum5 = CEnum(ctypes.c_uint32) +LP_JIT_VERTEX_HEADER_VERTEX_ID = _anonenum5.define('LP_JIT_VERTEX_HEADER_VERTEX_ID', 0) +LP_JIT_VERTEX_HEADER_CLIP_POS = _anonenum5.define('LP_JIT_VERTEX_HEADER_CLIP_POS', 1) +LP_JIT_VERTEX_HEADER_DATA = _anonenum5.define('LP_JIT_VERTEX_HEADER_DATA', 2) -# values for enumeration 'c__Ea_LP_JIT_RES_CONSTANTS' -c__Ea_LP_JIT_RES_CONSTANTS__enumvalues = { - 0: 'LP_JIT_RES_CONSTANTS', - 1: 'LP_JIT_RES_SSBOS', - 2: 'LP_JIT_RES_TEXTURES', - 3: 'LP_JIT_RES_SAMPLERS', - 4: 'LP_JIT_RES_IMAGES', - 5: 'LP_JIT_RES_COUNT', -} -LP_JIT_RES_CONSTANTS = 0 -LP_JIT_RES_SSBOS = 1 -LP_JIT_RES_TEXTURES = 2 -LP_JIT_RES_SAMPLERS = 3 -LP_JIT_RES_IMAGES = 4 -LP_JIT_RES_COUNT = 5 -c__Ea_LP_JIT_RES_CONSTANTS = ctypes.c_uint32 # enum -try: - lp_build_jit_resources_type = _libraries['libtinymesa_cpu.so'].lp_build_jit_resources_type - lp_build_jit_resources_type.restype = LLVMTypeRef - lp_build_jit_resources_type.argtypes = [ctypes.POINTER(struct_gallivm_state)] -except AttributeError: - pass +# LLVMTypeRef lp_build_create_jit_vertex_header_type(struct gallivm_state *gallivm, int data_elems) +try: (lp_build_create_jit_vertex_header_type:=dll.lp_build_create_jit_vertex_header_type).restype, lp_build_create_jit_vertex_header_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), ctypes.c_int32] +except AttributeError: pass -# values for enumeration 'c__Ea_LP_JIT_VERTEX_HEADER_VERTEX_ID' -c__Ea_LP_JIT_VERTEX_HEADER_VERTEX_ID__enumvalues = { - 0: 'LP_JIT_VERTEX_HEADER_VERTEX_ID', - 1: 'LP_JIT_VERTEX_HEADER_CLIP_POS', - 2: 'LP_JIT_VERTEX_HEADER_DATA', -} -LP_JIT_VERTEX_HEADER_VERTEX_ID = 0 -LP_JIT_VERTEX_HEADER_CLIP_POS = 1 -LP_JIT_VERTEX_HEADER_DATA = 2 -c__Ea_LP_JIT_VERTEX_HEADER_VERTEX_ID = ctypes.c_uint32 # enum -try: - lp_build_create_jit_vertex_header_type = _libraries['libtinymesa_cpu.so'].lp_build_create_jit_vertex_header_type - lp_build_create_jit_vertex_header_type.restype = LLVMTypeRef - lp_build_create_jit_vertex_header_type.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.c_int32] -except AttributeError: - pass -class struct_lp_sampler_dynamic_state(Structure): - pass +# void lp_build_jit_fill_sampler_dynamic_state(struct lp_sampler_dynamic_state *state) +try: (lp_build_jit_fill_sampler_dynamic_state:=dll.lp_build_jit_fill_sampler_dynamic_state).restype, lp_build_jit_fill_sampler_dynamic_state.argtypes = None, [ctypes.POINTER(struct_lp_sampler_dynamic_state)] +except AttributeError: pass -try: - lp_build_jit_fill_sampler_dynamic_state = _libraries['libtinymesa_cpu.so'].lp_build_jit_fill_sampler_dynamic_state - lp_build_jit_fill_sampler_dynamic_state.restype = None - lp_build_jit_fill_sampler_dynamic_state.argtypes = [ctypes.POINTER(struct_lp_sampler_dynamic_state)] -except AttributeError: - pass -try: - lp_build_jit_fill_image_dynamic_state = _libraries['libtinymesa_cpu.so'].lp_build_jit_fill_image_dynamic_state - lp_build_jit_fill_image_dynamic_state.restype = None - lp_build_jit_fill_image_dynamic_state.argtypes = [ctypes.POINTER(struct_lp_sampler_dynamic_state)] -except AttributeError: - pass -try: - lp_build_sample_function_type = _libraries['libtinymesa_cpu.so'].lp_build_sample_function_type - lp_build_sample_function_type.restype = LLVMTypeRef - lp_build_sample_function_type.argtypes = [ctypes.POINTER(struct_gallivm_state), uint32_t] -except AttributeError: - pass -try: - lp_build_size_function_type = _libraries['libtinymesa_cpu.so'].lp_build_size_function_type - lp_build_size_function_type.restype = LLVMTypeRef - lp_build_size_function_type.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_size_query_params)] -except AttributeError: - pass -try: - lp_build_image_function_type = _libraries['libtinymesa_cpu.so'].lp_build_image_function_type - lp_build_image_function_type.restype = LLVMTypeRef - lp_build_image_function_type.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_img_params), ctypes.c_bool, ctypes.c_bool] -except AttributeError: - pass -class struct_lp_texture_handle_state(Structure): - pass +# void lp_build_jit_fill_image_dynamic_state(struct lp_sampler_dynamic_state *state) +try: (lp_build_jit_fill_image_dynamic_state:=dll.lp_build_jit_fill_image_dynamic_state).restype, lp_build_jit_fill_image_dynamic_state.argtypes = None, [ctypes.POINTER(struct_lp_sampler_dynamic_state)] +except AttributeError: pass -class struct_lp_static_texture_state(Structure): - pass +# LLVMTypeRef lp_build_sample_function_type(struct gallivm_state *gallivm, uint32_t sample_key) +try: (lp_build_sample_function_type:=dll.lp_build_sample_function_type).restype, lp_build_sample_function_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), uint32_t] +except AttributeError: pass +# LLVMTypeRef lp_build_size_function_type(struct gallivm_state *gallivm, const struct lp_sampler_size_query_params *params) +try: (lp_build_size_function_type:=dll.lp_build_size_function_type).restype, lp_build_size_function_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_sampler_size_query_params)] +except AttributeError: pass + +# LLVMTypeRef lp_build_image_function_type(struct gallivm_state *gallivm, const struct lp_img_params *params, bool ms, bool is64) +try: (lp_build_image_function_type:=dll.lp_build_image_function_type).restype, lp_build_image_function_type.argtypes = LLVMTypeRef, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(struct_lp_img_params), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +class struct_lp_texture_handle_state(Struct): pass +class struct_lp_static_texture_state(Struct): pass +enum_pipe_texture_target = CEnum(ctypes.c_uint32) +PIPE_BUFFER = enum_pipe_texture_target.define('PIPE_BUFFER', 0) +PIPE_TEXTURE_1D = enum_pipe_texture_target.define('PIPE_TEXTURE_1D', 1) +PIPE_TEXTURE_2D = enum_pipe_texture_target.define('PIPE_TEXTURE_2D', 2) +PIPE_TEXTURE_3D = enum_pipe_texture_target.define('PIPE_TEXTURE_3D', 3) +PIPE_TEXTURE_CUBE = enum_pipe_texture_target.define('PIPE_TEXTURE_CUBE', 4) +PIPE_TEXTURE_RECT = enum_pipe_texture_target.define('PIPE_TEXTURE_RECT', 5) +PIPE_TEXTURE_1D_ARRAY = enum_pipe_texture_target.define('PIPE_TEXTURE_1D_ARRAY', 6) +PIPE_TEXTURE_2D_ARRAY = enum_pipe_texture_target.define('PIPE_TEXTURE_2D_ARRAY', 7) +PIPE_TEXTURE_CUBE_ARRAY = enum_pipe_texture_target.define('PIPE_TEXTURE_CUBE_ARRAY', 8) +PIPE_MAX_TEXTURE_TYPES = enum_pipe_texture_target.define('PIPE_MAX_TEXTURE_TYPES', 9) -# values for enumeration 'c_uint32' -c_uint32__enumvalues = { - 0: 'PIPE_BUFFER', - 1: 'PIPE_TEXTURE_1D', - 2: 'PIPE_TEXTURE_2D', - 3: 'PIPE_TEXTURE_3D', - 4: 'PIPE_TEXTURE_CUBE', - 5: 'PIPE_TEXTURE_RECT', - 6: 'PIPE_TEXTURE_1D_ARRAY', - 7: 'PIPE_TEXTURE_2D_ARRAY', - 8: 'PIPE_TEXTURE_CUBE_ARRAY', - 9: 'PIPE_MAX_TEXTURE_TYPES', -} -PIPE_BUFFER = 0 -PIPE_TEXTURE_1D = 1 -PIPE_TEXTURE_2D = 2 -PIPE_TEXTURE_3D = 3 -PIPE_TEXTURE_CUBE = 4 -PIPE_TEXTURE_RECT = 5 -PIPE_TEXTURE_1D_ARRAY = 6 -PIPE_TEXTURE_2D_ARRAY = 7 -PIPE_TEXTURE_CUBE_ARRAY = 8 -PIPE_MAX_TEXTURE_TYPES = 9 -c_uint32 = ctypes.c_uint32 # enum -struct_lp_static_texture_state._pack_ = 1 # source:False struct_lp_static_texture_state._fields_ = [ - ('format', pipe_format), - ('res_format', pipe_format), - ('swizzle_r', ctypes.c_uint32, 3), - ('swizzle_g', ctypes.c_uint32, 3), - ('swizzle_b', ctypes.c_uint32, 3), - ('swizzle_a', ctypes.c_uint32, 3), - ('target', c_uint32, 5), - ('res_target', c_uint32, 5), - ('pot_width', ctypes.c_uint32, 1), - ('pot_height', ctypes.c_uint32, 1), - ('pot_depth', ctypes.c_uint32, 1), - ('level_zero_only', ctypes.c_uint32, 1), - ('tiled', ctypes.c_uint32, 1), - ('tiled_samples', ctypes.c_uint32, 5), + ('format', enum_pipe_format), + ('res_format', enum_pipe_format), + ('swizzle_r', ctypes.c_uint32,3), + ('swizzle_g', ctypes.c_uint32,3), + ('swizzle_b', ctypes.c_uint32,3), + ('swizzle_a', ctypes.c_uint32,3), + ('target', enum_pipe_texture_target,5), + ('res_target', enum_pipe_texture_target,5), + ('pot_width', ctypes.c_uint32,1), + ('pot_height', ctypes.c_uint32,1), + ('pot_depth', ctypes.c_uint32,1), + ('level_zero_only', ctypes.c_uint32,1), + ('tiled', ctypes.c_uint32,1), + ('tiled_samples', ctypes.c_uint32,5), ] - -struct_lp_texture_handle_state._pack_ = 1 # source:False struct_lp_texture_handle_state._fields_ = [ - ('static_state', struct_lp_static_texture_state), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dynamic_state', struct_lp_jit_texture), + ('static_state', struct_lp_static_texture_state), + ('dynamic_state', struct_lp_jit_texture), ] - -class struct_lp_texture_functions(Structure): - pass - -struct_lp_texture_functions._pack_ = 1 # source:False +class struct_lp_texture_functions(Struct): pass struct_lp_texture_functions._fields_ = [ - ('sample_functions', ctypes.POINTER(ctypes.POINTER(ctypes.POINTER(None)))), - ('sampler_count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fetch_functions', ctypes.POINTER(ctypes.POINTER(None))), - ('size_function', ctypes.POINTER(None)), - ('samples_function', ctypes.POINTER(None)), - ('image_functions', ctypes.POINTER(ctypes.POINTER(None))), - ('state', struct_lp_texture_handle_state), - ('sampled', ctypes.c_bool), - ('storage', ctypes.c_bool), - ('PADDING_1', ctypes.c_ubyte * 6), - ('matrix', ctypes.POINTER(None)), + ('sample_functions', ctypes.POINTER(ctypes.POINTER(ctypes.c_void_p))), + ('sampler_count', uint32_t), + ('fetch_functions', ctypes.POINTER(ctypes.c_void_p)), + ('size_function', ctypes.c_void_p), + ('samples_function', ctypes.c_void_p), + ('image_functions', ctypes.POINTER(ctypes.c_void_p)), + ('state', struct_lp_texture_handle_state), + ('sampled', ctypes.c_bool), + ('storage', ctypes.c_bool), + ('matrix', ctypes.c_void_p), ] - -class struct_lp_texture_handle(Structure): - pass - -struct_lp_texture_handle._pack_ = 1 # source:False +class struct_lp_texture_handle(Struct): pass struct_lp_texture_handle._fields_ = [ - ('functions', ctypes.POINTER(None)), - ('sampler_index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('functions', ctypes.c_void_p), + ('sampler_index', uint32_t), ] - -class struct_lp_jit_bindless_texture(Structure): - pass - -struct_lp_jit_bindless_texture._pack_ = 1 # source:False +class struct_lp_jit_bindless_texture(Struct): pass struct_lp_jit_bindless_texture._fields_ = [ - ('base', ctypes.POINTER(None)), - ('residency', ctypes.POINTER(None)), - ('sampler_index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('base', ctypes.c_void_p), + ('residency', ctypes.c_void_p), + ('sampler_index', uint32_t), ] - -class struct_lp_descriptor(Structure): - pass - -class union_lp_descriptor_0(Union): - pass - -class struct_lp_descriptor_0_0(Structure): - pass - -struct_lp_descriptor_0_0._pack_ = 1 # source:False +class struct_lp_descriptor(Struct): pass +class struct_lp_descriptor_0(ctypes.Union): pass +class struct_lp_descriptor_0_0(Struct): pass struct_lp_descriptor_0_0._fields_ = [ - ('texture', struct_lp_jit_bindless_texture), - ('sampler', struct_lp_jit_sampler), - ('PADDING_0', ctypes.c_ubyte * 4), + ('texture', struct_lp_jit_bindless_texture), + ('sampler', struct_lp_jit_sampler), ] - -class struct_lp_descriptor_0_1(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('image', struct_lp_jit_image), - ] - -union_lp_descriptor_0._pack_ = 1 # source:False -union_lp_descriptor_0._anonymous_ = ('_0', '_1',) -union_lp_descriptor_0._fields_ = [ - ('_0', struct_lp_descriptor_0_0), - ('_1', struct_lp_descriptor_0_1), - ('buffer', struct_lp_jit_buffer), - ('accel_struct', ctypes.c_uint64), - ('PADDING_0', ctypes.c_ubyte * 48), +class struct_lp_descriptor_0_1(Struct): pass +struct_lp_descriptor_0_1._fields_ = [ + ('image', struct_lp_jit_image), ] - -struct_lp_descriptor._pack_ = 1 # source:False -struct_lp_descriptor._anonymous_ = ('_0',) +struct_lp_descriptor_0._anonymous_ = ['_0', '_1'] +struct_lp_descriptor_0._fields_ = [ + ('_0', struct_lp_descriptor_0_0), + ('_1', struct_lp_descriptor_0_1), + ('buffer', struct_lp_jit_buffer), + ('accel_struct', uint64_t), +] +struct_lp_descriptor._anonymous_ = ['_0'] struct_lp_descriptor._fields_ = [ - ('_0', union_lp_descriptor_0), - ('functions', ctypes.POINTER(None)), + ('_0', struct_lp_descriptor_0), + ('functions', ctypes.c_void_p), ] +# void lp_build_flow_skip_begin(struct lp_build_skip_context *ctx, struct gallivm_state *gallivm) +try: (lp_build_flow_skip_begin:=dll.lp_build_flow_skip_begin).restype, lp_build_flow_skip_begin.argtypes = None, [ctypes.POINTER(struct_lp_build_skip_context), ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass -try: - lp_mantissa = _libraries['libtinymesa_cpu.so'].lp_mantissa - lp_mantissa.restype = ctypes.c_uint32 - lp_mantissa.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_const_shift = _libraries['libtinymesa_cpu.so'].lp_const_shift - lp_const_shift.restype = ctypes.c_uint32 - lp_const_shift.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_const_offset = _libraries['libtinymesa_cpu.so'].lp_const_offset - lp_const_offset.restype = ctypes.c_uint32 - lp_const_offset.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_const_scale = _libraries['libtinymesa_cpu.so'].lp_const_scale - lp_const_scale.restype = ctypes.c_double - lp_const_scale.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_const_min = _libraries['libtinymesa_cpu.so'].lp_const_min - lp_const_min.restype = ctypes.c_double - lp_const_min.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_const_max = _libraries['libtinymesa_cpu.so'].lp_const_max - lp_const_max.restype = ctypes.c_double - lp_const_max.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_const_eps = _libraries['libtinymesa_cpu.so'].lp_const_eps - lp_const_eps.restype = ctypes.c_double - lp_const_eps.argtypes = [struct_lp_type] -except AttributeError: - pass -try: - lp_build_undef = _libraries['libtinymesa_cpu.so'].lp_build_undef - lp_build_undef.restype = LLVMValueRef - lp_build_undef.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_zero = _libraries['libtinymesa_cpu.so'].lp_build_zero - lp_build_zero.restype = LLVMValueRef - lp_build_zero.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_one = _libraries['libtinymesa_cpu.so'].lp_build_one - lp_build_one.restype = LLVMValueRef - lp_build_one.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_const_elem = _libraries['libtinymesa_cpu.so'].lp_build_const_elem - lp_build_const_elem.restype = LLVMValueRef - lp_build_const_elem.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_double] -except AttributeError: - pass -try: - lp_build_const_vec = _libraries['libtinymesa_cpu.so'].lp_build_const_vec - lp_build_const_vec.restype = LLVMValueRef - lp_build_const_vec.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_double] -except AttributeError: - pass -try: - lp_build_const_int_vec = _libraries['libtinymesa_cpu.so'].lp_build_const_int_vec - lp_build_const_int_vec.restype = LLVMValueRef - lp_build_const_int_vec.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_int64] -except AttributeError: - pass -try: - lp_build_const_channel_vec = _libraries['libtinymesa_cpu.so'].lp_build_const_channel_vec - lp_build_const_channel_vec.restype = LLVMValueRef - lp_build_const_channel_vec.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type] -except AttributeError: - pass -try: - lp_build_const_aos = _libraries['libtinymesa_cpu.so'].lp_build_const_aos - lp_build_const_aos.restype = LLVMValueRef - lp_build_const_aos.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_double, ctypes.c_double, ctypes.c_double, ctypes.c_double, ctypes.POINTER(ctypes.c_ubyte)] -except AttributeError: - pass -try: - lp_build_const_mask_aos = _libraries['libtinymesa_cpu.so'].lp_build_const_mask_aos - lp_build_const_mask_aos.restype = LLVMValueRef - lp_build_const_mask_aos.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_uint32, ctypes.c_uint32] -except AttributeError: - pass -try: - lp_build_const_mask_aos_swizzled = _libraries['libtinymesa_cpu.so'].lp_build_const_mask_aos_swizzled - lp_build_const_mask_aos_swizzled.restype = LLVMValueRef - lp_build_const_mask_aos_swizzled.argtypes = [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_ubyte)] -except AttributeError: - pass -try: - lp_build_const_int32 = _libraries['FIXME_STUB'].lp_build_const_int32 - lp_build_const_int32.restype = LLVMValueRef - lp_build_const_int32.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.c_int32] -except AttributeError: - pass -try: - lp_build_const_int64 = _libraries['FIXME_STUB'].lp_build_const_int64 - lp_build_const_int64.restype = LLVMValueRef - lp_build_const_int64.argtypes = [ctypes.POINTER(struct_gallivm_state), int64_t] -except AttributeError: - pass -try: - lp_build_const_float = _libraries['FIXME_STUB'].lp_build_const_float - lp_build_const_float.restype = LLVMValueRef - lp_build_const_float.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.c_float] -except AttributeError: - pass -try: - lp_build_const_double = _libraries['FIXME_STUB'].lp_build_const_double - lp_build_const_double.restype = LLVMValueRef - lp_build_const_double.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.c_float] -except AttributeError: - pass -try: - lp_build_const_int_pointer = _libraries['FIXME_STUB'].lp_build_const_int_pointer - lp_build_const_int_pointer.restype = LLVMValueRef - lp_build_const_int_pointer.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(None)] -except AttributeError: - pass -try: - lp_build_const_string = _libraries['libtinymesa_cpu.so'].lp_build_const_string - lp_build_const_string.restype = LLVMValueRef - lp_build_const_string.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_build_const_func_pointer = _libraries['libtinymesa_cpu.so'].lp_build_const_func_pointer - lp_build_const_func_pointer.restype = LLVMValueRef - lp_build_const_func_pointer.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(None), LLVMTypeRef, ctypes.POINTER(ctypes.POINTER(struct_LLVMOpaqueType)), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - lp_build_const_func_pointer_from_type = _libraries['libtinymesa_cpu.so'].lp_build_const_func_pointer_from_type - lp_build_const_func_pointer_from_type.restype = LLVMValueRef - lp_build_const_func_pointer_from_type.argtypes = [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(None), LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -__all__ = \ - ['ACCESS_CAN_REORDER', 'ACCESS_CAN_SPECULATE', 'ACCESS_COHERENT', - 'ACCESS_CP_GE_COHERENT_AMD', 'ACCESS_FMASK_LOWERED_AMD', - 'ACCESS_INCLUDE_HELPERS', 'ACCESS_IN_BOUNDS', - 'ACCESS_IS_SWIZZLED_AMD', 'ACCESS_KEEP_SCALAR', - 'ACCESS_NON_READABLE', 'ACCESS_NON_TEMPORAL', - 'ACCESS_NON_UNIFORM', 'ACCESS_NON_WRITEABLE', 'ACCESS_RESTRICT', - 'ACCESS_SMEM_AMD', 'ACCESS_USES_FORMAT_AMD', 'ACCESS_VOLATILE', - 'COMPARE_FUNC_ALWAYS', 'COMPARE_FUNC_EQUAL', - 'COMPARE_FUNC_GEQUAL', 'COMPARE_FUNC_GREATER', - 'COMPARE_FUNC_LEQUAL', 'COMPARE_FUNC_LESS', 'COMPARE_FUNC_NEVER', - 'COMPARE_FUNC_NOTEQUAL', 'DERIVATIVE_GROUP_LINEAR', - 'DERIVATIVE_GROUP_NONE', 'DERIVATIVE_GROUP_QUADS', - 'FRAG_DEPTH_LAYOUT_ANY', 'FRAG_DEPTH_LAYOUT_GREATER', - 'FRAG_DEPTH_LAYOUT_LESS', 'FRAG_DEPTH_LAYOUT_NONE', - 'FRAG_DEPTH_LAYOUT_UNCHANGED', 'FRAG_STENCIL_LAYOUT_ANY', - 'FRAG_STENCIL_LAYOUT_GREATER', 'FRAG_STENCIL_LAYOUT_LESS', - 'FRAG_STENCIL_LAYOUT_NONE', 'FRAG_STENCIL_LAYOUT_UNCHANGED', - 'GLSL_CMAT_USE_A', 'GLSL_CMAT_USE_ACCUMULATOR', 'GLSL_CMAT_USE_B', - 'GLSL_CMAT_USE_NONE', 'GLSL_INTERFACE_PACKING_PACKED', - 'GLSL_INTERFACE_PACKING_SHARED', 'GLSL_INTERFACE_PACKING_STD140', - 'GLSL_INTERFACE_PACKING_STD430', - 'GLSL_MATRIX_LAYOUT_COLUMN_MAJOR', 'GLSL_MATRIX_LAYOUT_INHERITED', - 'GLSL_MATRIX_LAYOUT_ROW_MAJOR', 'GLSL_PRECISION_HIGH', - 'GLSL_PRECISION_LOW', 'GLSL_PRECISION_MEDIUM', - 'GLSL_PRECISION_NONE', 'GLSL_SAMPLER_DIM_1D', - 'GLSL_SAMPLER_DIM_2D', 'GLSL_SAMPLER_DIM_3D', - 'GLSL_SAMPLER_DIM_BUF', 'GLSL_SAMPLER_DIM_CUBE', - 'GLSL_SAMPLER_DIM_EXTERNAL', 'GLSL_SAMPLER_DIM_MS', - 'GLSL_SAMPLER_DIM_RECT', 'GLSL_SAMPLER_DIM_SUBPASS', - 'GLSL_SAMPLER_DIM_SUBPASS_MS', 'GLSL_TYPE_ARRAY', - 'GLSL_TYPE_ATOMIC_UINT', 'GLSL_TYPE_BFLOAT16', 'GLSL_TYPE_BOOL', - 'GLSL_TYPE_COOPERATIVE_MATRIX', 'GLSL_TYPE_DOUBLE', - 'GLSL_TYPE_ERROR', 'GLSL_TYPE_FLOAT', 'GLSL_TYPE_FLOAT16', - 'GLSL_TYPE_FLOAT_E4M3FN', 'GLSL_TYPE_FLOAT_E5M2', - 'GLSL_TYPE_IMAGE', 'GLSL_TYPE_INT', 'GLSL_TYPE_INT16', - 'GLSL_TYPE_INT64', 'GLSL_TYPE_INT8', 'GLSL_TYPE_INTERFACE', - 'GLSL_TYPE_SAMPLER', 'GLSL_TYPE_STRUCT', 'GLSL_TYPE_SUBROUTINE', - 'GLSL_TYPE_TEXTURE', 'GLSL_TYPE_UINT', 'GLSL_TYPE_UINT16', - 'GLSL_TYPE_UINT64', 'GLSL_TYPE_UINT8', 'GLSL_TYPE_VOID', - 'LLVMArrayTypeKind', 'LLVMAtomicRMWBinOp', - 'LLVMAtomicRMWBinOpAdd', 'LLVMAtomicRMWBinOpAnd', - 'LLVMAtomicRMWBinOpFAdd', 'LLVMAtomicRMWBinOpFMax', - 'LLVMAtomicRMWBinOpFMin', 'LLVMAtomicRMWBinOpFSub', - 'LLVMAtomicRMWBinOpMax', 'LLVMAtomicRMWBinOpMin', - 'LLVMAtomicRMWBinOpNand', 'LLVMAtomicRMWBinOpOr', - 'LLVMAtomicRMWBinOpSub', 'LLVMAtomicRMWBinOpUDecWrap', - 'LLVMAtomicRMWBinOpUIncWrap', 'LLVMAtomicRMWBinOpUMax', - 'LLVMAtomicRMWBinOpUMin', 'LLVMAtomicRMWBinOpUSubCond', - 'LLVMAtomicRMWBinOpUSubSat', 'LLVMAtomicRMWBinOpXchg', - 'LLVMAtomicRMWBinOpXor', 'LLVMAtomicRMWBinOp__enumvalues', - 'LLVMBFloatTypeKind', 'LLVMBasicBlockRef', 'LLVMBuilderRef', - 'LLVMDoubleTypeKind', 'LLVMFP128TypeKind', 'LLVMFloatTypeKind', - 'LLVMFunctionTypeKind', 'LLVMHalfTypeKind', 'LLVMIntEQ', - 'LLVMIntNE', 'LLVMIntPredicate', 'LLVMIntPredicate__enumvalues', - 'LLVMIntSGE', 'LLVMIntSGT', 'LLVMIntSLE', 'LLVMIntSLT', - 'LLVMIntUGE', 'LLVMIntUGT', 'LLVMIntULE', 'LLVMIntULT', - 'LLVMIntegerTypeKind', 'LLVMLabelTypeKind', - 'LLVMMCJITMemoryManagerRef', 'LLVMMetadataTypeKind', - 'LLVMModuleRef', 'LLVMPPC_FP128TypeKind', 'LLVMPointerTypeKind', - 'LLVMScalableVectorTypeKind', 'LLVMStructTypeKind', - 'LLVMTargetExtTypeKind', 'LLVMTargetLibraryInfoRef', - 'LLVMTargetMachineRef', 'LLVMTokenTypeKind', 'LLVMTypeKind', - 'LLVMTypeKind__enumvalues', 'LLVMTypeRef', 'LLVMValueRef', - 'LLVMVectorTypeKind', 'LLVMVoidTypeKind', 'LLVMX86_AMXTypeKind', - 'LLVMX86_FP80TypeKind', 'LP_BLD_TEX_MODIFIER_EXPLICIT_DERIV', - 'LP_BLD_TEX_MODIFIER_EXPLICIT_LOD', - 'LP_BLD_TEX_MODIFIER_LOD_BIAS', 'LP_BLD_TEX_MODIFIER_LOD_ZERO', - 'LP_BLD_TEX_MODIFIER_NONE', 'LP_BLD_TEX_MODIFIER_PROJECTED', - 'LP_JIT_BUFFER_BASE', 'LP_JIT_BUFFER_NUM_ELEMENTS', - 'LP_JIT_BUFFER_NUM_FIELDS', 'LP_JIT_IMAGE_BASE', - 'LP_JIT_IMAGE_BASE_OFFSET', 'LP_JIT_IMAGE_DEPTH', - 'LP_JIT_IMAGE_HEIGHT', 'LP_JIT_IMAGE_IMG_STRIDE', - 'LP_JIT_IMAGE_NUM_FIELDS', 'LP_JIT_IMAGE_NUM_SAMPLES', - 'LP_JIT_IMAGE_RESIDENCY', 'LP_JIT_IMAGE_ROW_STRIDE', - 'LP_JIT_IMAGE_SAMPLE_STRIDE', 'LP_JIT_IMAGE_WIDTH', - 'LP_JIT_RES_CONSTANTS', 'LP_JIT_RES_COUNT', 'LP_JIT_RES_IMAGES', - 'LP_JIT_RES_SAMPLERS', 'LP_JIT_RES_SSBOS', 'LP_JIT_RES_TEXTURES', - 'LP_JIT_SAMPLER_BORDER_COLOR', 'LP_JIT_SAMPLER_INDEX_DUMMY', - 'LP_JIT_SAMPLER_LOD_BIAS', 'LP_JIT_SAMPLER_MAX_LOD', - 'LP_JIT_SAMPLER_MIN_LOD', 'LP_JIT_SAMPLER_NUM_FIELDS', - 'LP_JIT_TEXTURE_BASE', 'LP_JIT_TEXTURE_DEPTH', - 'LP_JIT_TEXTURE_FIRST_LEVEL', 'LP_JIT_TEXTURE_HEIGHT', - 'LP_JIT_TEXTURE_IMG_STRIDE', 'LP_JIT_TEXTURE_LAST_LEVEL', - 'LP_JIT_TEXTURE_MIP_OFFSETS', 'LP_JIT_TEXTURE_NUM_FIELDS', - 'LP_JIT_TEXTURE_ROW_STRIDE', 'LP_JIT_TEXTURE_WIDTH', - 'LP_JIT_VERTEX_HEADER_CLIP_POS', 'LP_JIT_VERTEX_HEADER_DATA', - 'LP_JIT_VERTEX_HEADER_VERTEX_ID', - 'LP_NIR_CALL_CONTEXT_BLOCK_ID_0', - 'LP_NIR_CALL_CONTEXT_BLOCK_ID_1', - 'LP_NIR_CALL_CONTEXT_BLOCK_ID_2', - 'LP_NIR_CALL_CONTEXT_BLOCK_SIZE_0', - 'LP_NIR_CALL_CONTEXT_BLOCK_SIZE_1', - 'LP_NIR_CALL_CONTEXT_BLOCK_SIZE_2', 'LP_NIR_CALL_CONTEXT_CONTEXT', - 'LP_NIR_CALL_CONTEXT_GRID_SIZE_0', - 'LP_NIR_CALL_CONTEXT_GRID_SIZE_1', - 'LP_NIR_CALL_CONTEXT_GRID_SIZE_2', 'LP_NIR_CALL_CONTEXT_MAX_ARGS', - 'LP_NIR_CALL_CONTEXT_RESOURCES', 'LP_NIR_CALL_CONTEXT_SCRATCH', - 'LP_NIR_CALL_CONTEXT_SHARED', 'LP_NIR_CALL_CONTEXT_THREAD_ID_0', - 'LP_NIR_CALL_CONTEXT_THREAD_ID_1', - 'LP_NIR_CALL_CONTEXT_THREAD_ID_2', 'LP_NIR_CALL_CONTEXT_WORK_DIM', - 'LP_SAMPLER_LOD_PER_ELEMENT', 'LP_SAMPLER_LOD_PER_QUAD', - 'LP_SAMPLER_LOD_SCALAR', 'MESA_LOG_DEBUG', 'MESA_LOG_ERROR', - 'MESA_LOG_INFO', 'MESA_LOG_WARN', 'MESA_PRIM_COUNT', - 'MESA_PRIM_LINES', 'MESA_PRIM_LINES_ADJACENCY', - 'MESA_PRIM_LINE_LOOP', 'MESA_PRIM_LINE_STRIP', - 'MESA_PRIM_LINE_STRIP_ADJACENCY', 'MESA_PRIM_MAX', - 'MESA_PRIM_PATCHES', 'MESA_PRIM_POINTS', 'MESA_PRIM_POLYGON', - 'MESA_PRIM_QUADS', 'MESA_PRIM_QUAD_STRIP', 'MESA_PRIM_TRIANGLES', - 'MESA_PRIM_TRIANGLES_ADJACENCY', 'MESA_PRIM_TRIANGLE_FAN', - 'MESA_PRIM_TRIANGLE_STRIP', 'MESA_PRIM_TRIANGLE_STRIP_ADJACENCY', - 'MESA_PRIM_UNKNOWN', 'MESA_SHADER_ANY_HIT', - 'MESA_SHADER_CALLABLE', 'MESA_SHADER_CLOSEST_HIT', - 'MESA_SHADER_COMPUTE', 'MESA_SHADER_FRAGMENT', - 'MESA_SHADER_GEOMETRY', 'MESA_SHADER_INTERSECTION', - 'MESA_SHADER_KERNEL', 'MESA_SHADER_MESH', 'MESA_SHADER_MISS', - 'MESA_SHADER_NONE', 'MESA_SHADER_RAYGEN', 'MESA_SHADER_TASK', - 'MESA_SHADER_TESS_CTRL', 'MESA_SHADER_TESS_EVAL', - 'MESA_SHADER_VERTEX', 'NAK_TS_DOMAIN_ISOLINE', - 'NAK_TS_DOMAIN_QUAD', 'NAK_TS_DOMAIN_TRIANGLE', - 'NAK_TS_PRIMS_LINES', 'NAK_TS_PRIMS_POINTS', - 'NAK_TS_PRIMS_TRIANGLES_CCW', 'NAK_TS_PRIMS_TRIANGLES_CW', - 'NAK_TS_SPACING_FRACT_EVEN', 'NAK_TS_SPACING_FRACT_ODD', - 'NAK_TS_SPACING_INTEGER', 'NIR_CMAT_A_SIGNED', - 'NIR_CMAT_B_SIGNED', 'NIR_CMAT_C_SIGNED', - 'NIR_CMAT_RESULT_SIGNED', 'NIR_INTRINSIC_ACCESS', - 'NIR_INTRINSIC_ALIGN_MUL', 'NIR_INTRINSIC_ALIGN_OFFSET', - 'NIR_INTRINSIC_ALU_OP', 'NIR_INTRINSIC_ARG_UPPER_BOUND_U32_AMD', - 'NIR_INTRINSIC_ATOMIC_OP', 'NIR_INTRINSIC_BASE', - 'NIR_INTRINSIC_BINDING', 'NIR_INTRINSIC_BIT_SIZE', - 'NIR_INTRINSIC_CALL_IDX', 'NIR_INTRINSIC_CAN_ELIMINATE', - 'NIR_INTRINSIC_CAN_REORDER', 'NIR_INTRINSIC_CLUSTER_SIZE', - 'NIR_INTRINSIC_CMAT_DESC', 'NIR_INTRINSIC_CMAT_SIGNED_MASK', - 'NIR_INTRINSIC_COLUMN', 'NIR_INTRINSIC_COMMITTED', - 'NIR_INTRINSIC_COMPONENT', 'NIR_INTRINSIC_DESC_SET', - 'NIR_INTRINSIC_DESC_TYPE', 'NIR_INTRINSIC_DEST_BASE_TYPE', - 'NIR_INTRINSIC_DEST_TYPE', 'NIR_INTRINSIC_DIVERGENT', - 'NIR_INTRINSIC_DRIVER_LOCATION', 'NIR_INTRINSIC_DST_ACCESS', - 'NIR_INTRINSIC_DST_CMAT_DESC', 'NIR_INTRINSIC_EXECUTION_SCOPE', - 'NIR_INTRINSIC_EXPLICIT_COORD', 'NIR_INTRINSIC_FETCH_INACTIVE', - 'NIR_INTRINSIC_FLAGS', 'NIR_INTRINSIC_FMT_IDX', - 'NIR_INTRINSIC_FORMAT', 'NIR_INTRINSIC_IMAGE_ARRAY', - 'NIR_INTRINSIC_IMAGE_DIM', 'NIR_INTRINSIC_INTERP_MODE', - 'NIR_INTRINSIC_IO_SEMANTICS', 'NIR_INTRINSIC_IO_XFB', - 'NIR_INTRINSIC_IO_XFB2', 'NIR_INTRINSIC_LEGACY_FABS', - 'NIR_INTRINSIC_LEGACY_FNEG', 'NIR_INTRINSIC_LEGACY_FSAT', - 'NIR_INTRINSIC_MATRIX_LAYOUT', 'NIR_INTRINSIC_MEMORY_MODES', - 'NIR_INTRINSIC_MEMORY_SCOPE', 'NIR_INTRINSIC_MEMORY_SEMANTICS', - 'NIR_INTRINSIC_NEG_HI_AMD', 'NIR_INTRINSIC_NEG_LO_AMD', - 'NIR_INTRINSIC_NUM_ARRAY_ELEMS', 'NIR_INTRINSIC_NUM_COMPONENTS', - 'NIR_INTRINSIC_NUM_INDEX_FLAGS', 'NIR_INTRINSIC_OFFSET0', - 'NIR_INTRINSIC_OFFSET1', 'NIR_INTRINSIC_PARAM_IDX', - 'NIR_INTRINSIC_PREAMBLE_CLASS', 'NIR_INTRINSIC_QUADGROUP', - 'NIR_INTRINSIC_RANGE', 'NIR_INTRINSIC_RANGE_BASE', - 'NIR_INTRINSIC_RAY_QUERY_VALUE', 'NIR_INTRINSIC_REDUCTION_OP', - 'NIR_INTRINSIC_REPEAT_COUNT', - 'NIR_INTRINSIC_RESOURCE_ACCESS_INTEL', - 'NIR_INTRINSIC_RESOURCE_BLOCK_INTEL', - 'NIR_INTRINSIC_ROUNDING_MODE', 'NIR_INTRINSIC_SATURATE', - 'NIR_INTRINSIC_SIGN_EXTEND', 'NIR_INTRINSIC_SRC_ACCESS', - 'NIR_INTRINSIC_SRC_BASE_TYPE', 'NIR_INTRINSIC_SRC_BASE_TYPE2', - 'NIR_INTRINSIC_SRC_CMAT_DESC', 'NIR_INTRINSIC_SRC_TYPE', - 'NIR_INTRINSIC_ST64', 'NIR_INTRINSIC_STACK_SIZE', - 'NIR_INTRINSIC_STREAM_ID', 'NIR_INTRINSIC_SUBGROUP', - 'NIR_INTRINSIC_SWIZZLE_MASK', 'NIR_INTRINSIC_SYNCHRONOUS', - 'NIR_INTRINSIC_SYSTOLIC_DEPTH', 'NIR_INTRINSIC_UCP_ID', - 'NIR_INTRINSIC_VALUE_ID', 'NIR_INTRINSIC_WRITE_MASK', - 'NIR_MEMORY_ACQUIRE', 'NIR_MEMORY_ACQ_REL', - 'NIR_MEMORY_MAKE_AVAILABLE', 'NIR_MEMORY_MAKE_VISIBLE', - 'NIR_MEMORY_RELEASE', 'NIR_OP_IS_2SRC_COMMUTATIVE', - 'NIR_OP_IS_ASSOCIATIVE', 'NIR_OP_IS_SELECTION', - 'NUM_TOTAL_VARYING_SLOTS', 'NV_DEVICE_TYPE_DIS', - 'NV_DEVICE_TYPE_IGP', 'NV_DEVICE_TYPE_SOC', 'PIPE_BUFFER', - 'PIPE_FORMAT_A16_FLOAT', 'PIPE_FORMAT_A16_SINT', - 'PIPE_FORMAT_A16_SNORM', 'PIPE_FORMAT_A16_UINT', - 'PIPE_FORMAT_A16_UNORM', 'PIPE_FORMAT_A1B5G5R5_UINT', - 'PIPE_FORMAT_A1B5G5R5_UNORM', 'PIPE_FORMAT_A1R5G5B5_UINT', - 'PIPE_FORMAT_A1R5G5B5_UNORM', 'PIPE_FORMAT_A2B10G10R10_UINT', - 'PIPE_FORMAT_A2B10G10R10_UNORM', 'PIPE_FORMAT_A2R10G10B10_UINT', - 'PIPE_FORMAT_A2R10G10B10_UNORM', 'PIPE_FORMAT_A32_FLOAT', - 'PIPE_FORMAT_A32_SINT', 'PIPE_FORMAT_A32_UINT', - 'PIPE_FORMAT_A4B4G4R4_UINT', 'PIPE_FORMAT_A4B4G4R4_UNORM', - 'PIPE_FORMAT_A4R4G4B4_UINT', 'PIPE_FORMAT_A4R4G4B4_UNORM', - 'PIPE_FORMAT_A4R4_UNORM', 'PIPE_FORMAT_A8B8G8R8_SINT', - 'PIPE_FORMAT_A8B8G8R8_SNORM', 'PIPE_FORMAT_A8B8G8R8_SRGB', - 'PIPE_FORMAT_A8B8G8R8_SSCALED', 'PIPE_FORMAT_A8B8G8R8_UINT', - 'PIPE_FORMAT_A8B8G8R8_UNORM', 'PIPE_FORMAT_A8B8G8R8_USCALED', - 'PIPE_FORMAT_A8R8G8B8_SINT', 'PIPE_FORMAT_A8R8G8B8_SNORM', - 'PIPE_FORMAT_A8R8G8B8_SRGB', 'PIPE_FORMAT_A8R8G8B8_UINT', - 'PIPE_FORMAT_A8R8G8B8_UNORM', 'PIPE_FORMAT_A8R8_UNORM', - 'PIPE_FORMAT_A8_SINT', 'PIPE_FORMAT_A8_SNORM', - 'PIPE_FORMAT_A8_UINT', 'PIPE_FORMAT_A8_UNORM', - 'PIPE_FORMAT_ASTC_10x10', 'PIPE_FORMAT_ASTC_10x10_FLOAT', - 'PIPE_FORMAT_ASTC_10x10_SRGB', 'PIPE_FORMAT_ASTC_10x5', - 'PIPE_FORMAT_ASTC_10x5_FLOAT', 'PIPE_FORMAT_ASTC_10x5_SRGB', - 'PIPE_FORMAT_ASTC_10x6', 'PIPE_FORMAT_ASTC_10x6_FLOAT', - 'PIPE_FORMAT_ASTC_10x6_SRGB', 'PIPE_FORMAT_ASTC_10x8', - 'PIPE_FORMAT_ASTC_10x8_FLOAT', 'PIPE_FORMAT_ASTC_10x8_SRGB', - 'PIPE_FORMAT_ASTC_12x10', 'PIPE_FORMAT_ASTC_12x10_FLOAT', - 'PIPE_FORMAT_ASTC_12x10_SRGB', 'PIPE_FORMAT_ASTC_12x12', - 'PIPE_FORMAT_ASTC_12x12_FLOAT', 'PIPE_FORMAT_ASTC_12x12_SRGB', - 'PIPE_FORMAT_ASTC_3x3x3', 'PIPE_FORMAT_ASTC_3x3x3_SRGB', - 'PIPE_FORMAT_ASTC_4x3x3', 'PIPE_FORMAT_ASTC_4x3x3_SRGB', - 'PIPE_FORMAT_ASTC_4x4', 'PIPE_FORMAT_ASTC_4x4_FLOAT', - 'PIPE_FORMAT_ASTC_4x4_SRGB', 'PIPE_FORMAT_ASTC_4x4x3', - 'PIPE_FORMAT_ASTC_4x4x3_SRGB', 'PIPE_FORMAT_ASTC_4x4x4', - 'PIPE_FORMAT_ASTC_4x4x4_SRGB', 'PIPE_FORMAT_ASTC_5x4', - 'PIPE_FORMAT_ASTC_5x4_FLOAT', 'PIPE_FORMAT_ASTC_5x4_SRGB', - 'PIPE_FORMAT_ASTC_5x4x4', 'PIPE_FORMAT_ASTC_5x4x4_SRGB', - 'PIPE_FORMAT_ASTC_5x5', 'PIPE_FORMAT_ASTC_5x5_FLOAT', - 'PIPE_FORMAT_ASTC_5x5_SRGB', 'PIPE_FORMAT_ASTC_5x5x4', - 'PIPE_FORMAT_ASTC_5x5x4_SRGB', 'PIPE_FORMAT_ASTC_5x5x5', - 'PIPE_FORMAT_ASTC_5x5x5_SRGB', 'PIPE_FORMAT_ASTC_6x5', - 'PIPE_FORMAT_ASTC_6x5_FLOAT', 'PIPE_FORMAT_ASTC_6x5_SRGB', - 'PIPE_FORMAT_ASTC_6x5x5', 'PIPE_FORMAT_ASTC_6x5x5_SRGB', - 'PIPE_FORMAT_ASTC_6x6', 'PIPE_FORMAT_ASTC_6x6_FLOAT', - 'PIPE_FORMAT_ASTC_6x6_SRGB', 'PIPE_FORMAT_ASTC_6x6x5', - 'PIPE_FORMAT_ASTC_6x6x5_SRGB', 'PIPE_FORMAT_ASTC_6x6x6', - 'PIPE_FORMAT_ASTC_6x6x6_SRGB', 'PIPE_FORMAT_ASTC_8x5', - 'PIPE_FORMAT_ASTC_8x5_FLOAT', 'PIPE_FORMAT_ASTC_8x5_SRGB', - 'PIPE_FORMAT_ASTC_8x6', 'PIPE_FORMAT_ASTC_8x6_FLOAT', - 'PIPE_FORMAT_ASTC_8x6_SRGB', 'PIPE_FORMAT_ASTC_8x8', - 'PIPE_FORMAT_ASTC_8x8_FLOAT', 'PIPE_FORMAT_ASTC_8x8_SRGB', - 'PIPE_FORMAT_ATC_RGB', 'PIPE_FORMAT_ATC_RGBA_EXPLICIT', - 'PIPE_FORMAT_ATC_RGBA_INTERPOLATED', 'PIPE_FORMAT_AYUV', - 'PIPE_FORMAT_B10G10R10A2_SINT', 'PIPE_FORMAT_B10G10R10A2_SNORM', - 'PIPE_FORMAT_B10G10R10A2_SSCALED', 'PIPE_FORMAT_B10G10R10A2_UINT', - 'PIPE_FORMAT_B10G10R10A2_UNORM', - 'PIPE_FORMAT_B10G10R10A2_USCALED', 'PIPE_FORMAT_B10G10R10X2_SINT', - 'PIPE_FORMAT_B10G10R10X2_SNORM', 'PIPE_FORMAT_B10G10R10X2_UNORM', - 'PIPE_FORMAT_B2G3R3_UINT', 'PIPE_FORMAT_B2G3R3_UNORM', - 'PIPE_FORMAT_B4G4R4A4_UINT', 'PIPE_FORMAT_B4G4R4A4_UNORM', - 'PIPE_FORMAT_B4G4R4X4_UNORM', 'PIPE_FORMAT_B5G5R5A1_UINT', - 'PIPE_FORMAT_B5G5R5A1_UNORM', 'PIPE_FORMAT_B5G5R5X1_UNORM', - 'PIPE_FORMAT_B5G6R5_SRGB', 'PIPE_FORMAT_B5G6R5_UINT', - 'PIPE_FORMAT_B5G6R5_UNORM', 'PIPE_FORMAT_B8G8R8A8_SINT', - 'PIPE_FORMAT_B8G8R8A8_SNORM', 'PIPE_FORMAT_B8G8R8A8_SRGB', - 'PIPE_FORMAT_B8G8R8A8_SSCALED', 'PIPE_FORMAT_B8G8R8A8_UINT', - 'PIPE_FORMAT_B8G8R8A8_UNORM', 'PIPE_FORMAT_B8G8R8A8_USCALED', - 'PIPE_FORMAT_B8G8R8X8_SINT', 'PIPE_FORMAT_B8G8R8X8_SNORM', - 'PIPE_FORMAT_B8G8R8X8_SRGB', 'PIPE_FORMAT_B8G8R8X8_UINT', - 'PIPE_FORMAT_B8G8R8X8_UNORM', 'PIPE_FORMAT_B8G8R8_SINT', - 'PIPE_FORMAT_B8G8R8_SNORM', 'PIPE_FORMAT_B8G8R8_SRGB', - 'PIPE_FORMAT_B8G8R8_SSCALED', 'PIPE_FORMAT_B8G8R8_UINT', - 'PIPE_FORMAT_B8G8R8_UNORM', 'PIPE_FORMAT_B8G8R8_USCALED', - 'PIPE_FORMAT_B8G8_R8G8_UNORM', 'PIPE_FORMAT_B8R8_G8R8_UNORM', - 'PIPE_FORMAT_BPTC_RGBA_UNORM', 'PIPE_FORMAT_BPTC_RGB_FLOAT', - 'PIPE_FORMAT_BPTC_RGB_UFLOAT', 'PIPE_FORMAT_BPTC_SRGBA', - 'PIPE_FORMAT_COUNT', 'PIPE_FORMAT_DXT1_RGB', - 'PIPE_FORMAT_DXT1_RGBA', 'PIPE_FORMAT_DXT1_SRGB', - 'PIPE_FORMAT_DXT1_SRGBA', 'PIPE_FORMAT_DXT3_RGBA', - 'PIPE_FORMAT_DXT3_SRGBA', 'PIPE_FORMAT_DXT5_RGBA', - 'PIPE_FORMAT_DXT5_SRGBA', 'PIPE_FORMAT_ETC1_RGB8', - 'PIPE_FORMAT_ETC2_R11_SNORM', 'PIPE_FORMAT_ETC2_R11_UNORM', - 'PIPE_FORMAT_ETC2_RG11_SNORM', 'PIPE_FORMAT_ETC2_RG11_UNORM', - 'PIPE_FORMAT_ETC2_RGB8', 'PIPE_FORMAT_ETC2_RGB8A1', - 'PIPE_FORMAT_ETC2_RGBA8', 'PIPE_FORMAT_ETC2_SRGB8', - 'PIPE_FORMAT_ETC2_SRGB8A1', 'PIPE_FORMAT_ETC2_SRGBA8', - 'PIPE_FORMAT_FXT1_RGB', 'PIPE_FORMAT_FXT1_RGBA', - 'PIPE_FORMAT_G16R16_SINT', 'PIPE_FORMAT_G16R16_SNORM', - 'PIPE_FORMAT_G16R16_UNORM', 'PIPE_FORMAT_G8B8_G8R8_UNORM', - 'PIPE_FORMAT_G8R8_B8R8_UNORM', 'PIPE_FORMAT_G8R8_G8B8_UNORM', - 'PIPE_FORMAT_G8R8_SINT', 'PIPE_FORMAT_G8R8_SNORM', - 'PIPE_FORMAT_G8R8_UNORM', 'PIPE_FORMAT_G8_B8R8_420_UNORM', - 'PIPE_FORMAT_G8_B8R8_422_UNORM', 'PIPE_FORMAT_G8_B8_R8_420_UNORM', - 'PIPE_FORMAT_I16_FLOAT', 'PIPE_FORMAT_I16_SINT', - 'PIPE_FORMAT_I16_SNORM', 'PIPE_FORMAT_I16_UINT', - 'PIPE_FORMAT_I16_UNORM', 'PIPE_FORMAT_I32_FLOAT', - 'PIPE_FORMAT_I32_SINT', 'PIPE_FORMAT_I32_UINT', - 'PIPE_FORMAT_I8_SINT', 'PIPE_FORMAT_I8_SNORM', - 'PIPE_FORMAT_I8_UINT', 'PIPE_FORMAT_I8_UNORM', 'PIPE_FORMAT_IYUV', - 'PIPE_FORMAT_L16A16_FLOAT', 'PIPE_FORMAT_L16A16_SINT', - 'PIPE_FORMAT_L16A16_SNORM', 'PIPE_FORMAT_L16A16_UINT', - 'PIPE_FORMAT_L16A16_UNORM', 'PIPE_FORMAT_L16_FLOAT', - 'PIPE_FORMAT_L16_SINT', 'PIPE_FORMAT_L16_SNORM', - 'PIPE_FORMAT_L16_UINT', 'PIPE_FORMAT_L16_UNORM', - 'PIPE_FORMAT_L32A32_FLOAT', 'PIPE_FORMAT_L32A32_SINT', - 'PIPE_FORMAT_L32A32_UINT', 'PIPE_FORMAT_L32_FLOAT', - 'PIPE_FORMAT_L32_SINT', 'PIPE_FORMAT_L32_UINT', - 'PIPE_FORMAT_L4A4_UNORM', 'PIPE_FORMAT_L8A8_SINT', - 'PIPE_FORMAT_L8A8_SNORM', 'PIPE_FORMAT_L8A8_SRGB', - 'PIPE_FORMAT_L8A8_UINT', 'PIPE_FORMAT_L8A8_UNORM', - 'PIPE_FORMAT_L8_SINT', 'PIPE_FORMAT_L8_SNORM', - 'PIPE_FORMAT_L8_SRGB', 'PIPE_FORMAT_L8_UINT', - 'PIPE_FORMAT_L8_UNORM', 'PIPE_FORMAT_LATC1_SNORM', - 'PIPE_FORMAT_LATC1_UNORM', 'PIPE_FORMAT_LATC2_SNORM', - 'PIPE_FORMAT_LATC2_UNORM', 'PIPE_FORMAT_NONE', 'PIPE_FORMAT_NV12', - 'PIPE_FORMAT_NV15', 'PIPE_FORMAT_NV16', 'PIPE_FORMAT_NV20', - 'PIPE_FORMAT_NV21', 'PIPE_FORMAT_P010', 'PIPE_FORMAT_P012', - 'PIPE_FORMAT_P016', 'PIPE_FORMAT_P030', - 'PIPE_FORMAT_R10G10B10A2_SINT', 'PIPE_FORMAT_R10G10B10A2_SNORM', - 'PIPE_FORMAT_R10G10B10A2_SSCALED', 'PIPE_FORMAT_R10G10B10A2_UINT', - 'PIPE_FORMAT_R10G10B10A2_UNORM', - 'PIPE_FORMAT_R10G10B10A2_USCALED', 'PIPE_FORMAT_R10G10B10X2_SINT', - 'PIPE_FORMAT_R10G10B10X2_SNORM', 'PIPE_FORMAT_R10G10B10X2_UNORM', - 'PIPE_FORMAT_R10G10B10X2_USCALED', - 'PIPE_FORMAT_R10G10B10_420_UNORM_PACKED', - 'PIPE_FORMAT_R10SG10SB10SA2U_NORM', - 'PIPE_FORMAT_R10_G10B10_420_UNORM', - 'PIPE_FORMAT_R10_G10B10_422_UNORM', 'PIPE_FORMAT_R11G11B10_FLOAT', - 'PIPE_FORMAT_R16A16_FLOAT', 'PIPE_FORMAT_R16A16_SINT', - 'PIPE_FORMAT_R16A16_SNORM', 'PIPE_FORMAT_R16A16_UINT', - 'PIPE_FORMAT_R16A16_UNORM', 'PIPE_FORMAT_R16G16B16A16_FLOAT', - 'PIPE_FORMAT_R16G16B16A16_SINT', 'PIPE_FORMAT_R16G16B16A16_SNORM', - 'PIPE_FORMAT_R16G16B16A16_SSCALED', - 'PIPE_FORMAT_R16G16B16A16_UINT', 'PIPE_FORMAT_R16G16B16A16_UNORM', - 'PIPE_FORMAT_R16G16B16A16_USCALED', - 'PIPE_FORMAT_R16G16B16X16_FLOAT', 'PIPE_FORMAT_R16G16B16X16_SINT', - 'PIPE_FORMAT_R16G16B16X16_SNORM', 'PIPE_FORMAT_R16G16B16X16_UINT', - 'PIPE_FORMAT_R16G16B16X16_UNORM', 'PIPE_FORMAT_R16G16B16_FLOAT', - 'PIPE_FORMAT_R16G16B16_SINT', 'PIPE_FORMAT_R16G16B16_SNORM', - 'PIPE_FORMAT_R16G16B16_SSCALED', 'PIPE_FORMAT_R16G16B16_UINT', - 'PIPE_FORMAT_R16G16B16_UNORM', 'PIPE_FORMAT_R16G16B16_USCALED', - 'PIPE_FORMAT_R16G16_FLOAT', 'PIPE_FORMAT_R16G16_SINT', - 'PIPE_FORMAT_R16G16_SNORM', 'PIPE_FORMAT_R16G16_SSCALED', - 'PIPE_FORMAT_R16G16_UINT', 'PIPE_FORMAT_R16G16_UNORM', - 'PIPE_FORMAT_R16G16_USCALED', 'PIPE_FORMAT_R16_FLOAT', - 'PIPE_FORMAT_R16_SINT', 'PIPE_FORMAT_R16_SNORM', - 'PIPE_FORMAT_R16_SSCALED', 'PIPE_FORMAT_R16_UINT', - 'PIPE_FORMAT_R16_UNORM', 'PIPE_FORMAT_R16_USCALED', - 'PIPE_FORMAT_R1_UNORM', 'PIPE_FORMAT_R32A32_FLOAT', - 'PIPE_FORMAT_R32A32_SINT', 'PIPE_FORMAT_R32A32_UINT', - 'PIPE_FORMAT_R32G32B32A32_FIXED', - 'PIPE_FORMAT_R32G32B32A32_FLOAT', 'PIPE_FORMAT_R32G32B32A32_SINT', - 'PIPE_FORMAT_R32G32B32A32_SNORM', - 'PIPE_FORMAT_R32G32B32A32_SSCALED', - 'PIPE_FORMAT_R32G32B32A32_UINT', 'PIPE_FORMAT_R32G32B32A32_UNORM', - 'PIPE_FORMAT_R32G32B32A32_USCALED', - 'PIPE_FORMAT_R32G32B32X32_FLOAT', 'PIPE_FORMAT_R32G32B32X32_SINT', - 'PIPE_FORMAT_R32G32B32X32_UINT', 'PIPE_FORMAT_R32G32B32_FIXED', - 'PIPE_FORMAT_R32G32B32_FLOAT', 'PIPE_FORMAT_R32G32B32_SINT', - 'PIPE_FORMAT_R32G32B32_SNORM', 'PIPE_FORMAT_R32G32B32_SSCALED', - 'PIPE_FORMAT_R32G32B32_UINT', 'PIPE_FORMAT_R32G32B32_UNORM', - 'PIPE_FORMAT_R32G32B32_USCALED', 'PIPE_FORMAT_R32G32_FIXED', - 'PIPE_FORMAT_R32G32_FLOAT', 'PIPE_FORMAT_R32G32_SINT', - 'PIPE_FORMAT_R32G32_SNORM', 'PIPE_FORMAT_R32G32_SSCALED', - 'PIPE_FORMAT_R32G32_UINT', 'PIPE_FORMAT_R32G32_UNORM', - 'PIPE_FORMAT_R32G32_USCALED', 'PIPE_FORMAT_R32_FIXED', - 'PIPE_FORMAT_R32_FLOAT', 'PIPE_FORMAT_R32_SINT', - 'PIPE_FORMAT_R32_SNORM', 'PIPE_FORMAT_R32_SSCALED', - 'PIPE_FORMAT_R32_UINT', 'PIPE_FORMAT_R32_UNORM', - 'PIPE_FORMAT_R32_USCALED', 'PIPE_FORMAT_R3G3B2_UINT', - 'PIPE_FORMAT_R3G3B2_UNORM', 'PIPE_FORMAT_R4A4_UNORM', - 'PIPE_FORMAT_R4G4B4A4_UINT', 'PIPE_FORMAT_R4G4B4A4_UNORM', - 'PIPE_FORMAT_R4G4B4X4_UNORM', 'PIPE_FORMAT_R5G5B5A1_UINT', - 'PIPE_FORMAT_R5G5B5A1_UNORM', 'PIPE_FORMAT_R5G5B5X1_UNORM', - 'PIPE_FORMAT_R5G6B5_SRGB', 'PIPE_FORMAT_R5G6B5_UINT', - 'PIPE_FORMAT_R5G6B5_UNORM', 'PIPE_FORMAT_R5SG5SB6U_NORM', - 'PIPE_FORMAT_R64G64B64A64_FLOAT', 'PIPE_FORMAT_R64G64B64A64_SINT', - 'PIPE_FORMAT_R64G64B64A64_UINT', 'PIPE_FORMAT_R64G64B64_FLOAT', - 'PIPE_FORMAT_R64G64B64_SINT', 'PIPE_FORMAT_R64G64B64_UINT', - 'PIPE_FORMAT_R64G64_FLOAT', 'PIPE_FORMAT_R64G64_SINT', - 'PIPE_FORMAT_R64G64_UINT', 'PIPE_FORMAT_R64_FLOAT', - 'PIPE_FORMAT_R64_SINT', 'PIPE_FORMAT_R64_UINT', - 'PIPE_FORMAT_R8A8_SINT', 'PIPE_FORMAT_R8A8_SNORM', - 'PIPE_FORMAT_R8A8_UINT', 'PIPE_FORMAT_R8A8_UNORM', - 'PIPE_FORMAT_R8B8_R8G8_UNORM', 'PIPE_FORMAT_R8G8B8A8_SINT', - 'PIPE_FORMAT_R8G8B8A8_SNORM', 'PIPE_FORMAT_R8G8B8A8_SRGB', - 'PIPE_FORMAT_R8G8B8A8_SSCALED', 'PIPE_FORMAT_R8G8B8A8_UINT', - 'PIPE_FORMAT_R8G8B8A8_UNORM', 'PIPE_FORMAT_R8G8B8A8_USCALED', - 'PIPE_FORMAT_R8G8B8X8_SINT', 'PIPE_FORMAT_R8G8B8X8_SNORM', - 'PIPE_FORMAT_R8G8B8X8_SRGB', 'PIPE_FORMAT_R8G8B8X8_UINT', - 'PIPE_FORMAT_R8G8B8X8_UNORM', - 'PIPE_FORMAT_R8G8B8_420_UNORM_PACKED', 'PIPE_FORMAT_R8G8B8_SINT', - 'PIPE_FORMAT_R8G8B8_SNORM', 'PIPE_FORMAT_R8G8B8_SRGB', - 'PIPE_FORMAT_R8G8B8_SSCALED', 'PIPE_FORMAT_R8G8B8_UINT', - 'PIPE_FORMAT_R8G8B8_UNORM', 'PIPE_FORMAT_R8G8B8_USCALED', - 'PIPE_FORMAT_R8G8Bx_SNORM', 'PIPE_FORMAT_R8G8_B8G8_UNORM', - 'PIPE_FORMAT_R8G8_R8B8_UNORM', 'PIPE_FORMAT_R8G8_SINT', - 'PIPE_FORMAT_R8G8_SNORM', 'PIPE_FORMAT_R8G8_SRGB', - 'PIPE_FORMAT_R8G8_SSCALED', 'PIPE_FORMAT_R8G8_UINT', - 'PIPE_FORMAT_R8G8_UNORM', 'PIPE_FORMAT_R8G8_USCALED', - 'PIPE_FORMAT_R8SG8SB8UX8U_NORM', 'PIPE_FORMAT_R8_B8G8_420_UNORM', - 'PIPE_FORMAT_R8_B8G8_422_UNORM', 'PIPE_FORMAT_R8_B8_G8_420_UNORM', - 'PIPE_FORMAT_R8_G8B8_420_UNORM', 'PIPE_FORMAT_R8_G8B8_422_UNORM', - 'PIPE_FORMAT_R8_G8_B8_420_UNORM', 'PIPE_FORMAT_R8_G8_B8_UNORM', - 'PIPE_FORMAT_R8_SINT', 'PIPE_FORMAT_R8_SNORM', - 'PIPE_FORMAT_R8_SRGB', 'PIPE_FORMAT_R8_SSCALED', - 'PIPE_FORMAT_R8_UINT', 'PIPE_FORMAT_R8_UNORM', - 'PIPE_FORMAT_R8_USCALED', 'PIPE_FORMAT_R9G9B9E5_FLOAT', - 'PIPE_FORMAT_RGTC1_SNORM', 'PIPE_FORMAT_RGTC1_UNORM', - 'PIPE_FORMAT_RGTC2_SNORM', 'PIPE_FORMAT_RGTC2_UNORM', - 'PIPE_FORMAT_S8X24_UINT', 'PIPE_FORMAT_S8_UINT', - 'PIPE_FORMAT_S8_UINT_Z24_UNORM', 'PIPE_FORMAT_UYVY', - 'PIPE_FORMAT_VYUY', 'PIPE_FORMAT_X1B5G5R5_UNORM', - 'PIPE_FORMAT_X1R5G5B5_UNORM', 'PIPE_FORMAT_X24S8_UINT', - 'PIPE_FORMAT_X32_S8X24_UINT', - 'PIPE_FORMAT_X4G12_X4B12X4R12_420_UNORM', - 'PIPE_FORMAT_X4R12X4G12_UNORM', 'PIPE_FORMAT_X4R12_UNORM', - 'PIPE_FORMAT_X6G10_X6B10X6R10_420_UNORM', - 'PIPE_FORMAT_X6R10X6G10_UNORM', 'PIPE_FORMAT_X6R10_UNORM', - 'PIPE_FORMAT_X8B8G8R8_SINT', 'PIPE_FORMAT_X8B8G8R8_SNORM', - 'PIPE_FORMAT_X8B8G8R8_SRGB', 'PIPE_FORMAT_X8B8G8R8_UNORM', - 'PIPE_FORMAT_X8R8G8B8_SINT', 'PIPE_FORMAT_X8R8G8B8_SNORM', - 'PIPE_FORMAT_X8R8G8B8_SRGB', 'PIPE_FORMAT_X8R8G8B8_UNORM', - 'PIPE_FORMAT_X8Z24_UNORM', 'PIPE_FORMAT_XYUV', - 'PIPE_FORMAT_Y10U10V10_420_UNORM_PACKED', - 'PIPE_FORMAT_Y10X6_U10X6_V10X6_420_UNORM', - 'PIPE_FORMAT_Y10X6_U10X6_V10X6_422_UNORM', - 'PIPE_FORMAT_Y10X6_U10X6_V10X6_444_UNORM', - 'PIPE_FORMAT_Y12X4_U12X4_V12X4_420_UNORM', - 'PIPE_FORMAT_Y12X4_U12X4_V12X4_422_UNORM', - 'PIPE_FORMAT_Y12X4_U12X4_V12X4_444_UNORM', - 'PIPE_FORMAT_Y16_U16V16_422_UNORM', - 'PIPE_FORMAT_Y16_U16_V16_420_UNORM', - 'PIPE_FORMAT_Y16_U16_V16_422_UNORM', - 'PIPE_FORMAT_Y16_U16_V16_444_UNORM', 'PIPE_FORMAT_Y210', - 'PIPE_FORMAT_Y212', 'PIPE_FORMAT_Y216', 'PIPE_FORMAT_Y410', - 'PIPE_FORMAT_Y412', 'PIPE_FORMAT_Y416', - 'PIPE_FORMAT_Y8U8V8_420_UNORM_PACKED', 'PIPE_FORMAT_Y8_400_UNORM', - 'PIPE_FORMAT_Y8_U8_V8_422_UNORM', - 'PIPE_FORMAT_Y8_U8_V8_440_UNORM', - 'PIPE_FORMAT_Y8_U8_V8_444_UNORM', 'PIPE_FORMAT_Y8_UNORM', - 'PIPE_FORMAT_YUYV', 'PIPE_FORMAT_YV12', 'PIPE_FORMAT_YV16', - 'PIPE_FORMAT_YVYU', 'PIPE_FORMAT_Z16_UNORM', - 'PIPE_FORMAT_Z16_UNORM_S8_UINT', 'PIPE_FORMAT_Z24X8_UNORM', - 'PIPE_FORMAT_Z24_UNORM_S8_UINT', - 'PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8', - 'PIPE_FORMAT_Z32_FLOAT', 'PIPE_FORMAT_Z32_FLOAT_S8X24_UINT', - 'PIPE_FORMAT_Z32_UNORM', 'PIPE_MAX_TEXTURE_TYPES', - 'PIPE_SHADER_COMPUTE', 'PIPE_SHADER_FRAGMENT', - 'PIPE_SHADER_GEOMETRY', 'PIPE_SHADER_MESH', - 'PIPE_SHADER_MESH_TYPES', 'PIPE_SHADER_TASK', - 'PIPE_SHADER_TESS_CTRL', 'PIPE_SHADER_TESS_EVAL', - 'PIPE_SHADER_TYPES', 'PIPE_SHADER_VERTEX', 'PIPE_TEXTURE_1D', - 'PIPE_TEXTURE_1D_ARRAY', 'PIPE_TEXTURE_2D', - 'PIPE_TEXTURE_2D_ARRAY', 'PIPE_TEXTURE_3D', 'PIPE_TEXTURE_CUBE', - 'PIPE_TEXTURE_CUBE_ARRAY', 'PIPE_TEXTURE_RECT', - 'RALLOC_PRINT_INFO_SUMMARY_ONLY', 'SCOPE_DEVICE', - 'SCOPE_INVOCATION', 'SCOPE_NONE', 'SCOPE_QUEUE_FAMILY', - 'SCOPE_SHADER_CALL', 'SCOPE_SUBGROUP', 'SCOPE_WORKGROUP', - 'SUBGROUP_SIZE_API_CONSTANT', 'SUBGROUP_SIZE_FULL_SUBGROUPS', - 'SUBGROUP_SIZE_REQUIRE_128', 'SUBGROUP_SIZE_REQUIRE_16', - 'SUBGROUP_SIZE_REQUIRE_32', 'SUBGROUP_SIZE_REQUIRE_4', - 'SUBGROUP_SIZE_REQUIRE_64', 'SUBGROUP_SIZE_REQUIRE_8', - 'SUBGROUP_SIZE_UNIFORM', 'SUBGROUP_SIZE_VARYING', - 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID', - 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_COORD', - 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL', - 'SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE', - 'SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTER_RHW', - 'SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID', - 'SYSTEM_VALUE_BARYCENTRIC_PERSP_COORD', - 'SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL', - 'SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE', - 'SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL', - 'SYSTEM_VALUE_BASE_GLOBAL_INVOCATION_ID', - 'SYSTEM_VALUE_BASE_INSTANCE', 'SYSTEM_VALUE_BASE_VERTEX', - 'SYSTEM_VALUE_BASE_WORKGROUP_ID', - 'SYSTEM_VALUE_COALESCED_INPUT_COUNT', 'SYSTEM_VALUE_COLOR0', - 'SYSTEM_VALUE_COLOR1', 'SYSTEM_VALUE_CULL_MASK', - 'SYSTEM_VALUE_DEVICE_INDEX', 'SYSTEM_VALUE_DRAW_ID', - 'SYSTEM_VALUE_FIRST_VERTEX', 'SYSTEM_VALUE_FRAG_COORD', - 'SYSTEM_VALUE_FRAG_COORD_W', 'SYSTEM_VALUE_FRAG_COORD_Z', - 'SYSTEM_VALUE_FRAG_INVOCATION_COUNT', - 'SYSTEM_VALUE_FRAG_SHADING_RATE', 'SYSTEM_VALUE_FRAG_SIZE', - 'SYSTEM_VALUE_FRONT_FACE', 'SYSTEM_VALUE_FRONT_FACE_FSIGN', - 'SYSTEM_VALUE_FULLY_COVERED', 'SYSTEM_VALUE_GLOBAL_GROUP_SIZE', - 'SYSTEM_VALUE_GLOBAL_INVOCATION_ID', - 'SYSTEM_VALUE_GLOBAL_INVOCATION_INDEX', - 'SYSTEM_VALUE_GS_HEADER_IR3', 'SYSTEM_VALUE_HELPER_INVOCATION', - 'SYSTEM_VALUE_INSTANCE_ID', 'SYSTEM_VALUE_INSTANCE_INDEX', - 'SYSTEM_VALUE_INVOCATION_ID', 'SYSTEM_VALUE_IS_INDEXED_DRAW', - 'SYSTEM_VALUE_LAYER_ID', 'SYSTEM_VALUE_LINE_COORD', - 'SYSTEM_VALUE_LOCAL_INVOCATION_ID', - 'SYSTEM_VALUE_LOCAL_INVOCATION_INDEX', 'SYSTEM_VALUE_MAX', - 'SYSTEM_VALUE_MESH_VIEW_COUNT', 'SYSTEM_VALUE_MESH_VIEW_INDICES', - 'SYSTEM_VALUE_NUM_SUBGROUPS', 'SYSTEM_VALUE_NUM_WORKGROUPS', - 'SYSTEM_VALUE_PIXEL_COORD', 'SYSTEM_VALUE_POINT_COORD', - 'SYSTEM_VALUE_PRIMITIVE_ID', 'SYSTEM_VALUE_RAY_FLAGS', - 'SYSTEM_VALUE_RAY_GEOMETRY_INDEX', 'SYSTEM_VALUE_RAY_HIT_KIND', - 'SYSTEM_VALUE_RAY_INSTANCE_CUSTOM_INDEX', - 'SYSTEM_VALUE_RAY_LAUNCH_ID', 'SYSTEM_VALUE_RAY_LAUNCH_SIZE', - 'SYSTEM_VALUE_RAY_OBJECT_DIRECTION', - 'SYSTEM_VALUE_RAY_OBJECT_ORIGIN', - 'SYSTEM_VALUE_RAY_OBJECT_TO_WORLD', - 'SYSTEM_VALUE_RAY_TRIANGLE_VERTEX_POSITIONS', - 'SYSTEM_VALUE_RAY_T_MAX', 'SYSTEM_VALUE_RAY_T_MIN', - 'SYSTEM_VALUE_RAY_WORLD_DIRECTION', - 'SYSTEM_VALUE_RAY_WORLD_ORIGIN', - 'SYSTEM_VALUE_RAY_WORLD_TO_OBJECT', - 'SYSTEM_VALUE_REL_PATCH_ID_IR3', 'SYSTEM_VALUE_SAMPLE_ID', - 'SYSTEM_VALUE_SAMPLE_MASK_IN', 'SYSTEM_VALUE_SAMPLE_POS', - 'SYSTEM_VALUE_SAMPLE_POS_OR_CENTER', 'SYSTEM_VALUE_SHADER_INDEX', - 'SYSTEM_VALUE_SM_COUNT_NV', 'SYSTEM_VALUE_SM_ID_NV', - 'SYSTEM_VALUE_SUBGROUP_EQ_MASK', 'SYSTEM_VALUE_SUBGROUP_GE_MASK', - 'SYSTEM_VALUE_SUBGROUP_GT_MASK', 'SYSTEM_VALUE_SUBGROUP_ID', - 'SYSTEM_VALUE_SUBGROUP_INVOCATION', - 'SYSTEM_VALUE_SUBGROUP_LE_MASK', 'SYSTEM_VALUE_SUBGROUP_LT_MASK', - 'SYSTEM_VALUE_SUBGROUP_SIZE', 'SYSTEM_VALUE_TCS_HEADER_IR3', - 'SYSTEM_VALUE_TESS_COORD', 'SYSTEM_VALUE_TESS_LEVEL_INNER', - 'SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT', - 'SYSTEM_VALUE_TESS_LEVEL_OUTER', - 'SYSTEM_VALUE_TESS_LEVEL_OUTER_DEFAULT', - 'SYSTEM_VALUE_USER_DATA_AMD', 'SYSTEM_VALUE_VERTEX_CNT', - 'SYSTEM_VALUE_VERTEX_ID', 'SYSTEM_VALUE_VERTEX_ID_ZERO_BASE', - 'SYSTEM_VALUE_VERTICES_IN', 'SYSTEM_VALUE_VIEW_INDEX', - 'SYSTEM_VALUE_WARPS_PER_SM_NV', 'SYSTEM_VALUE_WARP_ID_NV', - 'SYSTEM_VALUE_WORKGROUP_ID', 'SYSTEM_VALUE_WORKGROUP_INDEX', - 'SYSTEM_VALUE_WORKGROUP_SIZE', 'SYSTEM_VALUE_WORK_DIM', - 'TESS_PRIMITIVE_ISOLINES', 'TESS_PRIMITIVE_QUADS', - 'TESS_PRIMITIVE_TRIANGLES', 'TESS_PRIMITIVE_UNSPECIFIED', - 'TGSI_TEXTURE_1D', 'TGSI_TEXTURE_1D_ARRAY', 'TGSI_TEXTURE_2D', - 'TGSI_TEXTURE_2D_ARRAY', 'TGSI_TEXTURE_2D_ARRAY_MSAA', - 'TGSI_TEXTURE_2D_MSAA', 'TGSI_TEXTURE_3D', 'TGSI_TEXTURE_BUFFER', - 'TGSI_TEXTURE_COUNT', 'TGSI_TEXTURE_CUBE', - 'TGSI_TEXTURE_CUBE_ARRAY', 'TGSI_TEXTURE_RECT', - 'TGSI_TEXTURE_SHADOW1D', 'TGSI_TEXTURE_SHADOW1D_ARRAY', - 'TGSI_TEXTURE_SHADOW2D', 'TGSI_TEXTURE_SHADOW2D_ARRAY', - 'TGSI_TEXTURE_SHADOWCUBE', 'TGSI_TEXTURE_SHADOWCUBE_ARRAY', - 'TGSI_TEXTURE_SHADOWRECT', 'TGSI_TEXTURE_UNKNOWN', - 'UTIL_FORMAT_COLORSPACE_RGB', 'UTIL_FORMAT_COLORSPACE_SRGB', - 'UTIL_FORMAT_COLORSPACE_YUV', 'UTIL_FORMAT_COLORSPACE_ZS', - 'UTIL_FORMAT_LAYOUT_ASTC', 'UTIL_FORMAT_LAYOUT_ATC', - 'UTIL_FORMAT_LAYOUT_BPTC', 'UTIL_FORMAT_LAYOUT_ETC', - 'UTIL_FORMAT_LAYOUT_FXT1', 'UTIL_FORMAT_LAYOUT_OTHER', - 'UTIL_FORMAT_LAYOUT_PLAIN', 'UTIL_FORMAT_LAYOUT_PLANAR2', - 'UTIL_FORMAT_LAYOUT_PLANAR3', 'UTIL_FORMAT_LAYOUT_RGTC', - 'UTIL_FORMAT_LAYOUT_S3TC', 'UTIL_FORMAT_LAYOUT_SUBSAMPLED', - 'VARYING_SLOT_BFC0', 'VARYING_SLOT_BFC1', - 'VARYING_SLOT_BOUNDING_BOX0', 'VARYING_SLOT_BOUNDING_BOX1', - 'VARYING_SLOT_CLIP_DIST0', 'VARYING_SLOT_CLIP_DIST1', - 'VARYING_SLOT_CLIP_VERTEX', 'VARYING_SLOT_COL0', - 'VARYING_SLOT_COL1', 'VARYING_SLOT_CULL_DIST0', - 'VARYING_SLOT_CULL_DIST1', 'VARYING_SLOT_CULL_PRIMITIVE', - 'VARYING_SLOT_EDGE', 'VARYING_SLOT_FACE', 'VARYING_SLOT_FOGC', - 'VARYING_SLOT_LAYER', 'VARYING_SLOT_PATCH0', - 'VARYING_SLOT_PATCH1', 'VARYING_SLOT_PATCH10', - 'VARYING_SLOT_PATCH11', 'VARYING_SLOT_PATCH12', - 'VARYING_SLOT_PATCH13', 'VARYING_SLOT_PATCH14', - 'VARYING_SLOT_PATCH15', 'VARYING_SLOT_PATCH16', - 'VARYING_SLOT_PATCH17', 'VARYING_SLOT_PATCH18', - 'VARYING_SLOT_PATCH19', 'VARYING_SLOT_PATCH2', - 'VARYING_SLOT_PATCH20', 'VARYING_SLOT_PATCH21', - 'VARYING_SLOT_PATCH22', 'VARYING_SLOT_PATCH23', - 'VARYING_SLOT_PATCH24', 'VARYING_SLOT_PATCH25', - 'VARYING_SLOT_PATCH26', 'VARYING_SLOT_PATCH27', - 'VARYING_SLOT_PATCH28', 'VARYING_SLOT_PATCH29', - 'VARYING_SLOT_PATCH3', 'VARYING_SLOT_PATCH30', - 'VARYING_SLOT_PATCH31', 'VARYING_SLOT_PATCH4', - 'VARYING_SLOT_PATCH5', 'VARYING_SLOT_PATCH6', - 'VARYING_SLOT_PATCH7', 'VARYING_SLOT_PATCH8', - 'VARYING_SLOT_PATCH9', 'VARYING_SLOT_PNTC', 'VARYING_SLOT_POS', - 'VARYING_SLOT_PRIMITIVE_COUNT', 'VARYING_SLOT_PRIMITIVE_ID', - 'VARYING_SLOT_PRIMITIVE_INDICES', - 'VARYING_SLOT_PRIMITIVE_SHADING_RATE', 'VARYING_SLOT_PSIZ', - 'VARYING_SLOT_TASK_COUNT', 'VARYING_SLOT_TESS_LEVEL_INNER', - 'VARYING_SLOT_TESS_LEVEL_OUTER', 'VARYING_SLOT_TEX0', - 'VARYING_SLOT_TEX1', 'VARYING_SLOT_TEX2', 'VARYING_SLOT_TEX3', - 'VARYING_SLOT_TEX4', 'VARYING_SLOT_TEX5', 'VARYING_SLOT_TEX6', - 'VARYING_SLOT_TEX7', 'VARYING_SLOT_VAR0', - 'VARYING_SLOT_VAR0_16BIT', 'VARYING_SLOT_VAR1', - 'VARYING_SLOT_VAR10', 'VARYING_SLOT_VAR10_16BIT', - 'VARYING_SLOT_VAR11', 'VARYING_SLOT_VAR11_16BIT', - 'VARYING_SLOT_VAR12', 'VARYING_SLOT_VAR12_16BIT', - 'VARYING_SLOT_VAR13', 'VARYING_SLOT_VAR13_16BIT', - 'VARYING_SLOT_VAR14', 'VARYING_SLOT_VAR14_16BIT', - 'VARYING_SLOT_VAR15', 'VARYING_SLOT_VAR15_16BIT', - 'VARYING_SLOT_VAR16', 'VARYING_SLOT_VAR17', 'VARYING_SLOT_VAR18', - 'VARYING_SLOT_VAR19', 'VARYING_SLOT_VAR1_16BIT', - 'VARYING_SLOT_VAR2', 'VARYING_SLOT_VAR20', 'VARYING_SLOT_VAR21', - 'VARYING_SLOT_VAR22', 'VARYING_SLOT_VAR23', 'VARYING_SLOT_VAR24', - 'VARYING_SLOT_VAR25', 'VARYING_SLOT_VAR26', 'VARYING_SLOT_VAR27', - 'VARYING_SLOT_VAR28', 'VARYING_SLOT_VAR29', - 'VARYING_SLOT_VAR2_16BIT', 'VARYING_SLOT_VAR3', - 'VARYING_SLOT_VAR30', 'VARYING_SLOT_VAR31', - 'VARYING_SLOT_VAR3_16BIT', 'VARYING_SLOT_VAR4', - 'VARYING_SLOT_VAR4_16BIT', 'VARYING_SLOT_VAR5', - 'VARYING_SLOT_VAR5_16BIT', 'VARYING_SLOT_VAR6', - 'VARYING_SLOT_VAR6_16BIT', 'VARYING_SLOT_VAR7', - 'VARYING_SLOT_VAR7_16BIT', 'VARYING_SLOT_VAR8', - 'VARYING_SLOT_VAR8_16BIT', 'VARYING_SLOT_VAR9', - 'VARYING_SLOT_VAR9_16BIT', 'VARYING_SLOT_VIEWPORT', - 'VARYING_SLOT_VIEWPORT_MASK', 'VARYING_SLOT_VIEW_INDEX', - '_nir_mul_imm', '_nir_select_from_array_helper', - '_nir_shader_variable_has_mode', '_nir_src_set_parent', - 'blob_align', 'blob_copy_bytes', 'blob_finish', - 'blob_finish_get_buffer', 'blob_init', 'blob_init_fixed', - 'blob_overwrite_bytes', 'blob_overwrite_intptr', - 'blob_overwrite_uint32', 'blob_overwrite_uint8', - 'blob_read_bytes', 'blob_read_intptr', 'blob_read_string', - 'blob_read_uint16', 'blob_read_uint32', 'blob_read_uint64', - 'blob_read_uint8', 'blob_reader_align', 'blob_reader_init', - 'blob_reserve_bytes', 'blob_reserve_intptr', - 'blob_reserve_uint32', 'blob_skip_bytes', 'blob_write_bytes', - 'blob_write_intptr', 'blob_write_string', 'blob_write_uint16', - 'blob_write_uint32', 'blob_write_uint64', 'blob_write_uint8', - 'c__EA_LLVMAtomicRMWBinOp', 'c__EA_LLVMIntPredicate', - 'c__EA_LLVMTypeKind', 'c__EA_gl_system_value', - 'c__EA_gl_varying_slot', 'c__EA_mesa_scope', - 'c__EA_nir_address_format', 'c__EA_nir_alu_type', - 'c__EA_nir_atomic_op', 'c__EA_nir_cf_node_type', - 'c__EA_nir_cmat_signed', 'c__EA_nir_cursor_option', - 'c__EA_nir_depth_layout', - 'c__EA_nir_deref_instr_has_complex_use_options', - 'c__EA_nir_deref_type', 'c__EA_nir_divergence_options', - 'c__EA_nir_instr_type', 'c__EA_nir_intrinsic_index_flag', - 'c__EA_nir_intrinsic_op', 'c__EA_nir_intrinsic_semantic_flag', - 'c__EA_nir_io_options', 'c__EA_nir_jump_type', - 'c__EA_nir_load_grouping', 'c__EA_nir_loop_control', - 'c__EA_nir_lower_array_deref_of_vec_options', - 'c__EA_nir_lower_discard_if_options', - 'c__EA_nir_lower_doubles_options', - 'c__EA_nir_lower_fp16_cast_options', - 'c__EA_nir_lower_gs_intrinsics_flags', - 'c__EA_nir_lower_int64_options', - 'c__EA_nir_lower_interpolation_options', - 'c__EA_nir_lower_io_options', 'c__EA_nir_lower_packing_op', - 'c__EA_nir_mem_access_shift_method', 'c__EA_nir_memory_semantics', - 'c__EA_nir_metadata', 'c__EA_nir_move_options', 'c__EA_nir_op', - 'c__EA_nir_op_algebraic_property', 'c__EA_nir_opt_if_options', - 'c__EA_nir_opt_move_to_top_options', - 'c__EA_nir_opt_varyings_progress', 'c__EA_nir_preamble_class', - 'c__EA_nir_ray_query_value', 'c__EA_nir_resource_data_intel', - 'c__EA_nir_rounding_mode', 'c__EA_nir_selection_control', - 'c__EA_nir_var_declaration_type', 'c__EA_nir_variable_mode', - 'c__Ea_GLSL_PRECISION_NONE', 'c__Ea_LP_JIT_BUFFER_BASE', - 'c__Ea_LP_JIT_IMAGE_BASE', 'c__Ea_LP_JIT_RES_CONSTANTS', - 'c__Ea_LP_JIT_SAMPLER_MIN_LOD', 'c__Ea_LP_JIT_TEXTURE_BASE', - 'c__Ea_LP_JIT_VERTEX_HEADER_VERTEX_ID', - 'c__Ea_RALLOC_PRINT_INFO_SUMMARY_ONLY', 'c_bool', 'c_uint32', - 'c_uint64', 'compare_func', 'decode_type_from_blob', - 'encode_type_to_blob', 'func_pointer', - 'gallivm_add_global_mapping', 'gallivm_compile_module', - 'gallivm_create', 'gallivm_create_target_library_info', - 'gallivm_destroy', 'gallivm_dispose_target_library_info', - 'gallivm_free_ir', 'gallivm_get_perf_flags', - 'gallivm_jit_function', 'gallivm_stub_func', - 'gallivm_verify_function', 'gc_alloc_size', 'gc_context', - 'gc_ctx', 'gc_free', 'gc_get_context', 'gc_mark_live', - 'gc_sweep_end', 'gc_sweep_start', 'gc_zalloc_size', - 'gl_access_qualifier', 'gl_derivative_group', 'gl_shader_stage', - 'gl_shader_stage__enumvalues', 'gl_subgroup_size', - 'gl_system_value', 'gl_system_value__enumvalues', - 'gl_varying_slot', 'gl_varying_slot__enumvalues', - 'glsl_apply_signedness_to_base_type', 'glsl_array_size', - 'glsl_array_type', 'glsl_atomic_size', 'glsl_atomic_uint_type', - 'glsl_bare_sampler_type', 'glsl_bare_shadow_sampler_type', - 'glsl_base_type', 'glsl_base_type_bit_size', - 'glsl_base_type_get_bit_size', 'glsl_base_type_is_16bit', - 'glsl_base_type_is_64bit', 'glsl_base_type_is_float', - 'glsl_base_type_is_integer', 'glsl_bf16vec_type', - 'glsl_bfloat16_t_type', 'glsl_bfloatN_t_type', 'glsl_bool_type', - 'glsl_bvec2_type', 'glsl_bvec4_type', 'glsl_bvec_type', - 'glsl_channel_type', 'glsl_cmat_type', 'glsl_cmat_use', - 'glsl_contains_array', 'glsl_contains_atomic', - 'glsl_contains_double', 'glsl_contains_integer', - 'glsl_contains_opaque', 'glsl_contains_sampler', - 'glsl_contains_subroutine', 'glsl_count_attribute_slots', - 'glsl_count_dword_slots', 'glsl_count_vec4_slots', - 'glsl_double_type', 'glsl_dvec2_type', 'glsl_dvec4_type', - 'glsl_dvec_type', 'glsl_e4m3fn_t_type', 'glsl_e4m3fnvec_type', - 'glsl_e5m2_t_type', 'glsl_e5m2vec_type', - 'glsl_explicit_matrix_type', 'glsl_f16vec_type', - 'glsl_float16_t_type', 'glsl_float16_type', 'glsl_floatN_t_type', - 'glsl_float_type', 'glsl_get_aoa_size', 'glsl_get_array_element', - 'glsl_get_bare_type', 'glsl_get_base_glsl_type', - 'glsl_get_base_type', 'glsl_get_bit_size', - 'glsl_get_cl_alignment', 'glsl_get_cl_size', - 'glsl_get_cl_type_size_align', 'glsl_get_cmat_description', - 'glsl_get_cmat_element', 'glsl_get_column_type', - 'glsl_get_component_slots', 'glsl_get_component_slots_aligned', - 'glsl_get_components', 'glsl_get_explicit_alignment', - 'glsl_get_explicit_interface_type', 'glsl_get_explicit_size', - 'glsl_get_explicit_std140_type', 'glsl_get_explicit_std430_type', - 'glsl_get_explicit_stride', - 'glsl_get_explicit_type_for_size_align', 'glsl_get_field_index', - 'glsl_get_field_type', 'glsl_get_ifc_packing', - 'glsl_get_internal_ifc_packing', 'glsl_get_length', - 'glsl_get_matrix_columns', 'glsl_get_mul_type', - 'glsl_get_natural_size_align_bytes', 'glsl_get_row_type', - 'glsl_get_sampler_coordinate_components', 'glsl_get_sampler_dim', - 'glsl_get_sampler_dim_coordinate_components', - 'glsl_get_sampler_result_type', 'glsl_get_scalar_type', - 'glsl_get_std140_base_alignment', 'glsl_get_std140_size', - 'glsl_get_std430_array_stride', 'glsl_get_std430_base_alignment', - 'glsl_get_std430_size', 'glsl_get_struct_elem_name', - 'glsl_get_struct_field', 'glsl_get_struct_field_data', - 'glsl_get_struct_field_offset', 'glsl_get_struct_location_offset', - 'glsl_get_type_name', 'glsl_get_vec4_size_align_bytes', - 'glsl_get_vector_elements', 'glsl_get_word_size_align_bytes', - 'glsl_i16vec_type', 'glsl_i64vec_type', 'glsl_i8vec_type', - 'glsl_image_type', 'glsl_int16_t_type', 'glsl_int16_type', - 'glsl_int64_t_type', 'glsl_int8_t_type', 'glsl_intN_t_type', - 'glsl_int_type', 'glsl_interface_packing', 'glsl_interface_type', - 'glsl_ivec2_type', 'glsl_ivec4_type', 'glsl_ivec_type', - 'glsl_matrix_layout', 'glsl_matrix_type', - 'glsl_matrix_type_is_row_major', 'glsl_record_compare', - 'glsl_replace_vector_type', 'glsl_sampler_dim', - 'glsl_sampler_type', 'glsl_sampler_type_is_array', - 'glsl_sampler_type_is_shadow', 'glsl_sampler_type_to_texture', - 'glsl_scalar_type', 'glsl_signed_base_type_of', - 'glsl_simple_explicit_type', 'glsl_simple_type', - 'glsl_size_align_handle_array_and_structs', 'glsl_struct_field', - 'glsl_struct_type', 'glsl_struct_type_is_packed', - 'glsl_struct_type_with_explicit_alignment', - 'glsl_subroutine_type', 'glsl_texture_type', - 'glsl_texture_type_to_sampler', 'glsl_transposed_type', - 'glsl_type', 'glsl_type_compare_no_precision', - 'glsl_type_contains_32bit', 'glsl_type_contains_64bit', - 'glsl_type_contains_image', 'glsl_type_get_image_count', - 'glsl_type_get_sampler_count', 'glsl_type_get_texture_count', - 'glsl_type_is_16bit', 'glsl_type_is_32bit', 'glsl_type_is_64bit', - 'glsl_type_is_array', 'glsl_type_is_array_of_arrays', - 'glsl_type_is_array_or_matrix', 'glsl_type_is_atomic_uint', - 'glsl_type_is_bare_sampler', 'glsl_type_is_bfloat_16', - 'glsl_type_is_boolean', 'glsl_type_is_cmat', - 'glsl_type_is_double', 'glsl_type_is_dual_slot', - 'glsl_type_is_e4m3fn', 'glsl_type_is_e5m2', 'glsl_type_is_error', - 'glsl_type_is_float', 'glsl_type_is_float_16', - 'glsl_type_is_float_16_32', 'glsl_type_is_float_16_32_64', - 'glsl_type_is_image', 'glsl_type_is_int_16_32', - 'glsl_type_is_int_16_32_64', 'glsl_type_is_integer', - 'glsl_type_is_integer_16', 'glsl_type_is_integer_16_32', - 'glsl_type_is_integer_16_32_64', 'glsl_type_is_integer_32', - 'glsl_type_is_integer_32_64', 'glsl_type_is_integer_64', - 'glsl_type_is_interface', 'glsl_type_is_leaf', - 'glsl_type_is_matrix', 'glsl_type_is_numeric', - 'glsl_type_is_packed', 'glsl_type_is_sampler', - 'glsl_type_is_scalar', 'glsl_type_is_struct', - 'glsl_type_is_struct_or_ifc', 'glsl_type_is_subroutine', - 'glsl_type_is_texture', 'glsl_type_is_uint_16_32', - 'glsl_type_is_uint_16_32_64', 'glsl_type_is_unsized_array', - 'glsl_type_is_vector', 'glsl_type_is_vector_or_scalar', - 'glsl_type_is_void', 'glsl_type_replace_vec3_with_vec4', - 'glsl_type_singleton_decref', 'glsl_type_singleton_init_or_ref', - 'glsl_type_size_align_func', 'glsl_type_to_16bit', - 'glsl_type_uniform_locations', 'glsl_type_wrap_in_arrays', - 'glsl_u16vec_type', 'glsl_u64vec_type', 'glsl_u8vec_type', - 'glsl_uint16_t_type', 'glsl_uint16_type', 'glsl_uint64_t_type', - 'glsl_uint8_t_type', 'glsl_uintN_t_type', 'glsl_uint_type', - 'glsl_unsigned_base_type_of', 'glsl_uvec2_type', - 'glsl_uvec4_type', 'glsl_uvec_type', 'glsl_varying_count', - 'glsl_vec2_type', 'glsl_vec4_type', 'glsl_vec_type', - 'glsl_vector_type', 'glsl_void_type', 'glsl_without_array', - 'glsl_without_array_or_matrix', 'int64_t', 'intptr_t', - 'linear_alloc_child', 'linear_alloc_child_array', - 'linear_asprintf', 'linear_asprintf_append', - 'linear_asprintf_rewrite_tail', 'linear_context', - 'linear_context_with_opts', 'linear_ctx', 'linear_free_context', - 'linear_opts', 'linear_strcat', 'linear_strdup', - 'linear_vasprintf', 'linear_vasprintf_append', - 'linear_vasprintf_rewrite_tail', 'linear_zalloc_child', - 'linear_zalloc_child_array', 'lp_bld_init_native_targets', - 'lp_bld_ppc_disable_denorms', 'lp_build_alloca', - 'lp_build_alloca_undef', 'lp_build_array_alloca', - 'lp_build_array_get2', 'lp_build_array_get_ptr2', - 'lp_build_const_aos', 'lp_build_const_channel_vec', - 'lp_build_const_double', 'lp_build_const_elem', - 'lp_build_const_float', 'lp_build_const_func_pointer', - 'lp_build_const_func_pointer_from_type', 'lp_build_const_int32', - 'lp_build_const_int64', 'lp_build_const_int_pointer', - 'lp_build_const_int_vec', 'lp_build_const_mask_aos', - 'lp_build_const_mask_aos_swizzled', 'lp_build_const_string', - 'lp_build_const_vec', 'lp_build_context_init', - 'lp_build_count_ir_module', - 'lp_build_create_jit_compiler_for_module', - 'lp_build_create_jit_vertex_header_type', - 'lp_build_cs_func_call_context', 'lp_build_elem_type', - 'lp_build_else', 'lp_build_endif', 'lp_build_flow_skip_begin', - 'lp_build_flow_skip_cond_break', 'lp_build_flow_skip_end', - 'lp_build_for_loop_begin', 'lp_build_for_loop_end', 'lp_build_if', - 'lp_build_image_function_type', 'lp_build_init', - 'lp_build_init_native_width', 'lp_build_insert_new_block', - 'lp_build_int_elem_type', 'lp_build_int_vec_type', - 'lp_build_jit_fill_image_dynamic_state', - 'lp_build_jit_fill_sampler_dynamic_state', - 'lp_build_jit_resources_type', 'lp_build_loop_begin', - 'lp_build_loop_end', 'lp_build_loop_end_cond', - 'lp_build_loop_force_reload_counter', - 'lp_build_loop_force_set_counter', 'lp_build_mask_begin', - 'lp_build_mask_check', 'lp_build_mask_end', 'lp_build_mask_force', - 'lp_build_mask_update', 'lp_build_mask_value', 'lp_build_nir_aos', - 'lp_build_nir_sample_key', 'lp_build_nir_soa', - 'lp_build_nir_soa_func', 'lp_build_nir_soa_prepasses', - 'lp_build_one', 'lp_build_opt_nir', 'lp_build_pointer_get2', - 'lp_build_pointer_get_unaligned2', 'lp_build_pointer_set', - 'lp_build_pointer_set_unaligned', 'lp_build_sample_function_type', - 'lp_build_size_function_type', 'lp_build_struct_get2', - 'lp_build_struct_get_ptr2', 'lp_build_tex_modifier', - 'lp_build_undef', 'lp_build_vec_type', 'lp_build_zero', - 'lp_check_elem_type', 'lp_check_value', 'lp_check_vec_type', - 'lp_const_eps', 'lp_const_max', 'lp_const_min', 'lp_const_offset', - 'lp_const_scale', 'lp_const_shift', 'lp_context_create', - 'lp_context_destroy', 'lp_context_ref', - 'lp_create_builder_at_entry', 'lp_dump_llvmtype', 'lp_elem_type', - 'lp_float32_vec4_type', 'lp_free_generated_code', - 'lp_free_memory_manager', 'lp_free_objcache', - 'lp_get_called_value', 'lp_get_default_memory_manager', - 'lp_img_op_from_intrinsic', 'lp_init_clock_hook', - 'lp_init_env_options', 'lp_int32_vec4_type', 'lp_int_type', - 'lp_is_function', 'lp_llvm_buffer_base', - 'lp_llvm_buffer_num_elements', 'lp_llvm_descriptor_base', - 'lp_mantissa', 'lp_native_vector_width', - 'lp_nir_array_build_gather_values', 'lp_nir_call_context_args', - 'lp_packed_img_op_from_intrinsic', 'lp_passmgr_create', - 'lp_passmgr_dispose', 'lp_passmgr_run', 'lp_sampler_lod_property', - 'lp_set_module_stack_alignment_override', 'lp_set_target_options', - 'lp_sizeof_llvm_type', 'lp_translate_atomic_op', 'lp_type_fixed', - 'lp_type_float', 'lp_type_float_vec', 'lp_type_from_format', - 'lp_type_from_format_desc', 'lp_type_int', 'lp_type_int_vec', - 'lp_type_ufixed', 'lp_type_uint', 'lp_type_uint_vec', - 'lp_type_unorm', 'lp_type_width', 'lp_typekind_name', - 'lp_uint_type', 'lp_unorm8_vec4_type', 'lp_wider_type', - 'mesa_log_level', 'mesa_prim', 'mesa_scope', - 'mesa_scope__enumvalues', 'nak_compile_shader', - 'nak_compiler_create', 'nak_compiler_destroy', 'nak_debug_flags', - 'nak_fill_qmd', 'nak_get_qmd_cbuf_desc_layout', - 'nak_get_qmd_dispatch_size_layout', 'nak_nir_lower_image_addrs', - 'nak_nir_options', 'nak_postprocess_nir', 'nak_preprocess_nir', - 'nak_qmd_size_B', 'nak_shader_bin_destroy', 'nak_ts_domain', - 'nak_ts_prims', 'nak_ts_spacing', 'nir_a_minus_bc', - 'nir_add_inlinable_uniforms', 'nir_addition_might_overflow', - 'nir_address_format', 'nir_address_format_2x32bit_global', - 'nir_address_format_32bit_global', - 'nir_address_format_32bit_index_offset', - 'nir_address_format_32bit_index_offset_pack64', - 'nir_address_format_32bit_offset', - 'nir_address_format_32bit_offset_as_64bit', - 'nir_address_format_62bit_generic', - 'nir_address_format_64bit_bounded_global', - 'nir_address_format_64bit_global', - 'nir_address_format_64bit_global_32bit_offset', - 'nir_address_format__enumvalues', 'nir_address_format_bit_size', - 'nir_address_format_logical', 'nir_address_format_null_value', - 'nir_address_format_num_components', - 'nir_address_format_to_glsl_type', - 'nir_address_format_vec2_index_32bit_offset', 'nir_after_block', - 'nir_after_block_before_jump', 'nir_after_cf_list', - 'nir_after_cf_node', 'nir_after_cf_node_and_phis', - 'nir_after_impl', 'nir_after_instr', 'nir_after_instr_and_phis', - 'nir_after_phis', 'nir_after_reg_decls', 'nir_align_imm', - 'nir_alignment_deref_cast', 'nir_alu_binop_identity', - 'nir_alu_instr', 'nir_alu_instr_channel_used', - 'nir_alu_instr_clone', 'nir_alu_instr_create', - 'nir_alu_instr_is_comparison', 'nir_alu_instr_is_inf_preserve', - 'nir_alu_instr_is_nan_preserve', - 'nir_alu_instr_is_signed_zero_inf_nan_preserve', - 'nir_alu_instr_is_signed_zero_preserve', - 'nir_alu_instr_src_read_mask', 'nir_alu_pass_cb', 'nir_alu_src', - 'nir_alu_src_as_uint', 'nir_alu_src_copy', - 'nir_alu_src_is_trivial_ssa', 'nir_alu_srcs_equal', - 'nir_alu_srcs_negative_equal', - 'nir_alu_srcs_negative_equal_typed', 'nir_alu_type', - 'nir_alu_type__enumvalues', 'nir_amul_imm', - 'nir_assign_io_var_locations', 'nir_atomic_op', - 'nir_atomic_op__enumvalues', 'nir_atomic_op_cmpxchg', - 'nir_atomic_op_dec_wrap', 'nir_atomic_op_fadd', - 'nir_atomic_op_fcmpxchg', 'nir_atomic_op_fmax', - 'nir_atomic_op_fmin', 'nir_atomic_op_iadd', 'nir_atomic_op_iand', - 'nir_atomic_op_imax', 'nir_atomic_op_imin', - 'nir_atomic_op_inc_wrap', 'nir_atomic_op_ior', - 'nir_atomic_op_ixor', 'nir_atomic_op_ordered_add_gfx12_amd', - 'nir_atomic_op_to_alu', 'nir_atomic_op_type', - 'nir_atomic_op_umax', 'nir_atomic_op_umin', 'nir_atomic_op_xchg', - 'nir_b2bN', 'nir_b2fN', 'nir_b2iN', 'nir_ball', 'nir_ball_iequal', - 'nir_bany', 'nir_bany_inequal', 'nir_before_block', - 'nir_before_block_after_phis', 'nir_before_cf_list', - 'nir_before_cf_node', 'nir_before_impl', 'nir_before_instr', - 'nir_before_src', 'nir_bfdot', 'nir_binding', - 'nir_bitcast_vector', 'nir_bitfield_insert_imm', 'nir_block', - 'nir_block_cf_tree_next', 'nir_block_cf_tree_prev', - 'nir_block_contains_work', 'nir_block_create', - 'nir_block_dominates', 'nir_block_ends_in_break', - 'nir_block_ends_in_jump', 'nir_block_ends_in_return_or_halt', - 'nir_block_first_instr', 'nir_block_get_following_if', - 'nir_block_get_following_loop', - 'nir_block_get_predecessors_sorted', 'nir_block_is_reachable', - 'nir_block_is_unreachable', 'nir_block_last_instr', - 'nir_block_last_phi_instr', 'nir_block_unstructured_next', - 'nir_break_if', 'nir_build_addr_iadd', 'nir_build_addr_iadd_imm', - 'nir_build_addr_ieq', 'nir_build_addr_isub', 'nir_build_alu', - 'nir_build_alu1', 'nir_build_alu2', 'nir_build_alu3', - 'nir_build_alu4', 'nir_build_alu_src_arr', 'nir_build_call', - 'nir_build_deref_array', 'nir_build_deref_array_imm', - 'nir_build_deref_array_wildcard', 'nir_build_deref_cast', - 'nir_build_deref_cast_with_alignment', 'nir_build_deref_follower', - 'nir_build_deref_ptr_as_array', 'nir_build_deref_struct', - 'nir_build_deref_var', 'nir_build_deriv', 'nir_build_imm', - 'nir_build_indirect_call', - 'nir_build_lowered_load_helper_invocation', 'nir_build_string', - 'nir_build_tex_deref_instr', 'nir_build_write_masked_store', - 'nir_build_write_masked_stores', 'nir_builder', - 'nir_builder_alu_instr_finish_and_insert', 'nir_builder_at', - 'nir_builder_cf_insert', 'nir_builder_create', - 'nir_builder_init_simple_shader', 'nir_builder_instr_insert', - 'nir_builder_instr_insert_at_top', 'nir_builder_is_inside_cf', - 'nir_builder_last_instr', 'nir_calc_dominance', - 'nir_calc_dominance_impl', 'nir_calc_use_dominance_impl', - 'nir_call_instr', 'nir_call_instr_create', 'nir_call_serialized', - 'nir_can_lower_multiview', 'nir_can_move_instr', - 'nir_cf_list_is_empty_block', 'nir_cf_node', - 'nir_cf_node_as_block', 'nir_cf_node_as_function', - 'nir_cf_node_as_if', 'nir_cf_node_as_loop', 'nir_cf_node_block', - 'nir_cf_node_cf_tree_first', 'nir_cf_node_cf_tree_last', - 'nir_cf_node_cf_tree_next', 'nir_cf_node_cf_tree_prev', - 'nir_cf_node_function', 'nir_cf_node_get_function', - 'nir_cf_node_if', 'nir_cf_node_is_first', 'nir_cf_node_is_last', - 'nir_cf_node_loop', 'nir_cf_node_next', 'nir_cf_node_prev', - 'nir_cf_node_type', 'nir_cf_node_type__enumvalues', 'nir_channel', - 'nir_channel_or_undef', 'nir_channels', 'nir_chase_binding', - 'nir_cleanup_functions', 'nir_clear_mediump_io_flag', - 'nir_clear_shared_memory', 'nir_clone_deref_instr', - 'nir_clone_uniform_variable', 'nir_cmat_signed', - 'nir_cmat_signed__enumvalues', 'nir_collect_src_uniforms', - 'nir_combine_barrier_cb', 'nir_combined_align', - 'nir_compact_varyings', 'nir_compare_func', 'nir_component_mask', - 'nir_component_mask_can_reinterpret', - 'nir_component_mask_reinterpret', 'nir_component_mask_t', - 'nir_const_value', 'nir_const_value_as_bool', - 'nir_const_value_as_float', 'nir_const_value_as_int', - 'nir_const_value_as_uint', 'nir_const_value_for_bool', - 'nir_const_value_for_float', 'nir_const_value_for_int', - 'nir_const_value_for_raw_uint', 'nir_const_value_for_uint', - 'nir_const_value_negative_equal', 'nir_constant', - 'nir_constant_clone', 'nir_convert_from_ssa', - 'nir_convert_loop_to_lcssa', 'nir_convert_to_bit_size', - 'nir_convert_to_lcssa', 'nir_copy_deref', - 'nir_copy_deref_with_access', 'nir_copy_prop', - 'nir_copy_prop_impl', 'nir_copy_var', 'nir_create_passthrough_gs', - 'nir_create_passthrough_tcs', 'nir_create_passthrough_tcs_impl', - 'nir_create_variable_with_location', 'nir_cursor', - 'nir_cursor_after_block', 'nir_cursor_after_instr', - 'nir_cursor_before_block', 'nir_cursor_before_instr', - 'nir_cursor_current_block', 'nir_cursor_option', - 'nir_cursor_option__enumvalues', 'nir_cursors_equal', 'nir_ddx', - 'nir_ddx_coarse', 'nir_ddx_fine', 'nir_ddy', 'nir_ddy_coarse', - 'nir_ddy_fine', 'nir_debug', 'nir_debug_print_shader', - 'nir_decl_reg', 'nir_dedup_inline_samplers', 'nir_def', - 'nir_def_all_uses_are_fsat', 'nir_def_all_uses_ignore_sign_bit', - 'nir_def_components_read', 'nir_def_first_component_read', - 'nir_def_init', 'nir_def_init_for_type', - 'nir_def_is_frag_coord_z', 'nir_def_is_unused', - 'nir_def_last_component_read', 'nir_def_only_used_by_if', - 'nir_def_replace', 'nir_def_rewrite_uses', - 'nir_def_rewrite_uses_after', 'nir_def_rewrite_uses_src', - 'nir_def_used_by_if', 'nir_defs_interfere', 'nir_depth_layout', - 'nir_depth_layout__enumvalues', 'nir_depth_layout_any', - 'nir_depth_layout_greater', 'nir_depth_layout_less', - 'nir_depth_layout_none', 'nir_depth_layout_unchanged', - 'nir_deref_cast_is_trivial', 'nir_deref_count_slots', - 'nir_deref_instr', 'nir_deref_instr_array_stride', - 'nir_deref_instr_create', 'nir_deref_instr_get_variable', - 'nir_deref_instr_has_complex_use', - 'nir_deref_instr_has_complex_use_allow_atomics', - 'nir_deref_instr_has_complex_use_allow_memcpy_dst', - 'nir_deref_instr_has_complex_use_allow_memcpy_src', - 'nir_deref_instr_has_complex_use_options', - 'nir_deref_instr_has_complex_use_options__enumvalues', - 'nir_deref_instr_has_indirect', - 'nir_deref_instr_is_known_out_of_bounds', - 'nir_deref_instr_parent', 'nir_deref_instr_remove_if_unused', - 'nir_deref_mode_is', 'nir_deref_mode_is_in_set', - 'nir_deref_mode_is_one_of', 'nir_deref_mode_may_be', - 'nir_deref_mode_must_be', 'nir_deref_type', - 'nir_deref_type__enumvalues', 'nir_deref_type_array', - 'nir_deref_type_array_wildcard', 'nir_deref_type_cast', - 'nir_deref_type_ptr_as_array', 'nir_deref_type_struct', - 'nir_deref_type_var', 'nir_deserialize', - 'nir_deserialize_function', 'nir_discard', 'nir_discard_if', - 'nir_divergence_analysis', 'nir_divergence_analysis_impl', - 'nir_divergence_ignore_undef_if_phi_srcs', - 'nir_divergence_multiple_workgroup_per_compute_subgroup', - 'nir_divergence_options', 'nir_divergence_options__enumvalues', - 'nir_divergence_shader_record_ptr_uniform', - 'nir_divergence_single_frag_shading_rate_per_subgroup', - 'nir_divergence_single_patch_per_tcs_subgroup', - 'nir_divergence_single_patch_per_tes_subgroup', - 'nir_divergence_single_prim_per_subgroup', - 'nir_divergence_uniform_load_tears', - 'nir_divergence_view_index_uniform', 'nir_dominance_lca', - 'nir_dont_move_byte_word_vecs', 'nir_dump_cfg', - 'nir_dump_cfg_impl', 'nir_dump_dom_frontier', - 'nir_dump_dom_frontier_impl', 'nir_dump_dom_tree', - 'nir_dump_dom_tree_impl', 'nir_explicit_io_address_from_deref', - 'nir_extract_bits', 'nir_extract_i8_imm', 'nir_extract_u8_imm', - 'nir_f2fN', 'nir_f2iN', 'nir_f2uN', 'nir_fadd_imm', 'nir_fclamp', - 'nir_fdiv_imm', 'nir_fdot', 'nir_ffma_imm1', 'nir_ffma_imm12', - 'nir_ffma_imm2', 'nir_fgt_imm', 'nir_find_inlinable_uniforms', - 'nir_find_sampler_variable_with_tex_index', - 'nir_find_state_variable', - 'nir_find_variable_with_driver_location', - 'nir_find_variable_with_location', 'nir_first_phi_in_block', - 'nir_fixup_deref_modes', 'nir_fixup_deref_types', - 'nir_fixup_is_exported', 'nir_fle_imm', 'nir_fmul_imm', - 'nir_foreach_def_cb', 'nir_foreach_function_with_impl_first', - 'nir_foreach_function_with_impl_next', - 'nir_foreach_phi_src_leaving_block', 'nir_foreach_src', - 'nir_foreach_src_cb', 'nir_fpow_imm', - 'nir_free_output_dependencies', 'nir_fsub_imm', 'nir_function', - 'nir_function_clone', 'nir_function_create', 'nir_function_impl', - 'nir_function_impl_add_variable', 'nir_function_impl_clone', - 'nir_function_impl_clone_remap_globals', - 'nir_function_impl_create', 'nir_function_impl_create_bare', - 'nir_function_impl_index_vars', - 'nir_function_impl_lower_instructions', - 'nir_function_instructions_pass', 'nir_function_intrinsics_pass', - 'nir_function_set_impl', 'nir_gather_explicit_io_initializers', - 'nir_gather_input_to_output_dependencies', - 'nir_gather_output_clipper_var_groups', - 'nir_gather_output_dependencies', 'nir_gather_types', - 'nir_gen_rect_vertices', 'nir_get_binding_variable', - 'nir_get_explicit_deref_align', - 'nir_get_glsl_base_type_for_nir_type', - 'nir_get_immediate_use_dominator', 'nir_get_io_arrayed_index_src', - 'nir_get_io_arrayed_index_src_number', 'nir_get_io_index_src', - 'nir_get_io_index_src_number', 'nir_get_io_intrinsic', - 'nir_get_io_offset_src', 'nir_get_io_offset_src_number', - 'nir_get_live_defs', 'nir_get_nir_type_for_glsl_base_type', - 'nir_get_nir_type_for_glsl_type', 'nir_get_ptr_bitsize', - 'nir_get_rounding_mode_from_float_controls', 'nir_get_scalar', - 'nir_get_shader_call_payload_src', 'nir_get_tex_deref', - 'nir_get_tex_src', 'nir_get_variable_with_location', 'nir_goto', - 'nir_goto_if', 'nir_group_all', 'nir_group_loads', - 'nir_group_same_resource_only', - 'nir_gs_count_vertices_and_primitives', - 'nir_has_any_rounding_mode_enabled', - 'nir_has_any_rounding_mode_rtne', 'nir_has_any_rounding_mode_rtz', - 'nir_has_divergent_loop', 'nir_has_non_uniform_access', 'nir_i2b', - 'nir_i2fN', 'nir_i2iN', 'nir_iadd_imm', 'nir_iadd_imm_nuw', - 'nir_iadd_nuw', 'nir_iand_imm', 'nir_ibfe_imm', - 'nir_ibitfield_extract_imm', 'nir_iclamp', 'nir_if', - 'nir_if_create', 'nir_if_first_else_block', - 'nir_if_first_then_block', 'nir_if_last_else_block', - 'nir_if_last_then_block', 'nir_if_phi', - 'nir_image_intrinsic_coord_components', 'nir_imax_imm', - 'nir_imin_imm', 'nir_imm_bool', 'nir_imm_boolN_t', - 'nir_imm_double', 'nir_imm_false', 'nir_imm_float', - 'nir_imm_float16', 'nir_imm_floatN_t', 'nir_imm_int', - 'nir_imm_int64', 'nir_imm_intN_t', 'nir_imm_ivec2', - 'nir_imm_ivec3', 'nir_imm_ivec3_intN', 'nir_imm_ivec4', - 'nir_imm_ivec4_intN', 'nir_imm_true', 'nir_imm_uvec2_intN', - 'nir_imm_uvec3_intN', 'nir_imm_vec2', 'nir_imm_vec3', - 'nir_imm_vec4', 'nir_imm_vec4_16', 'nir_imm_zero', 'nir_imod_imm', - 'nir_impl_last_block', 'nir_imul_imm', 'nir_index_blocks', - 'nir_index_instrs', 'nir_index_ssa_defs', - 'nir_inline_function_impl', 'nir_inline_functions', - 'nir_inline_uniforms', 'nir_input_attachment_options', - 'nir_input_to_output_deps', 'nir_instr', 'nir_instr_as_alu', - 'nir_instr_as_call', 'nir_instr_as_deref', - 'nir_instr_as_intrinsic', 'nir_instr_as_jump', - 'nir_instr_as_load_const', 'nir_instr_as_parallel_copy', - 'nir_instr_as_phi', 'nir_instr_as_str', 'nir_instr_as_tex', - 'nir_instr_as_undef', 'nir_instr_clear_src', 'nir_instr_clone', - 'nir_instr_clone_deep', 'nir_instr_debug_info', 'nir_instr_def', - 'nir_instr_dominates_use', 'nir_instr_filter_cb', - 'nir_instr_free', 'nir_instr_free_and_dce', 'nir_instr_free_list', - 'nir_instr_get_debug_info', 'nir_instr_get_gc_pointer', - 'nir_instr_init_src', 'nir_instr_insert', - 'nir_instr_insert_after', 'nir_instr_insert_after_block', - 'nir_instr_insert_after_cf', 'nir_instr_insert_after_cf_list', - 'nir_instr_insert_before', 'nir_instr_insert_before_block', - 'nir_instr_insert_before_cf', 'nir_instr_insert_before_cf_list', - 'nir_instr_is_before', 'nir_instr_is_first', 'nir_instr_is_last', - 'nir_instr_move', 'nir_instr_move_src', 'nir_instr_next', - 'nir_instr_pass_cb', 'nir_instr_prev', 'nir_instr_remove', - 'nir_instr_remove_v', 'nir_instr_type', - 'nir_instr_type__enumvalues', 'nir_instr_type_alu', - 'nir_instr_type_call', 'nir_instr_type_deref', - 'nir_instr_type_intrinsic', 'nir_instr_type_jump', - 'nir_instr_type_load_const', 'nir_instr_type_parallel_copy', - 'nir_instr_type_phi', 'nir_instr_type_tex', - 'nir_instr_type_undef', 'nir_instr_writemask_filter_cb', - 'nir_instr_xfb_write_mask', 'nir_instrs_equal', - 'nir_intrin_filter_cb', 'nir_intrinsic_accept_ray_intersection', - 'nir_intrinsic_addr_mode_is', 'nir_intrinsic_al2p_nv', - 'nir_intrinsic_ald_nv', 'nir_intrinsic_align', - 'nir_intrinsic_alpha_to_coverage', 'nir_intrinsic_as_uniform', - 'nir_intrinsic_ast_nv', - 'nir_intrinsic_atomic_add_gen_prim_count_amd', - 'nir_intrinsic_atomic_add_gs_emit_prim_count_amd', - 'nir_intrinsic_atomic_add_shader_invocation_count_amd', - 'nir_intrinsic_atomic_add_xfb_prim_count_amd', - 'nir_intrinsic_atomic_counter_add', - 'nir_intrinsic_atomic_counter_add_deref', - 'nir_intrinsic_atomic_counter_and', - 'nir_intrinsic_atomic_counter_and_deref', - 'nir_intrinsic_atomic_counter_comp_swap', - 'nir_intrinsic_atomic_counter_comp_swap_deref', - 'nir_intrinsic_atomic_counter_exchange', - 'nir_intrinsic_atomic_counter_exchange_deref', - 'nir_intrinsic_atomic_counter_inc', - 'nir_intrinsic_atomic_counter_inc_deref', - 'nir_intrinsic_atomic_counter_max', - 'nir_intrinsic_atomic_counter_max_deref', - 'nir_intrinsic_atomic_counter_min', - 'nir_intrinsic_atomic_counter_min_deref', - 'nir_intrinsic_atomic_counter_or', - 'nir_intrinsic_atomic_counter_or_deref', - 'nir_intrinsic_atomic_counter_post_dec', - 'nir_intrinsic_atomic_counter_post_dec_deref', - 'nir_intrinsic_atomic_counter_pre_dec', - 'nir_intrinsic_atomic_counter_pre_dec_deref', - 'nir_intrinsic_atomic_counter_read', - 'nir_intrinsic_atomic_counter_read_deref', - 'nir_intrinsic_atomic_counter_xor', - 'nir_intrinsic_atomic_counter_xor_deref', 'nir_intrinsic_ballot', - 'nir_intrinsic_ballot_bit_count_exclusive', - 'nir_intrinsic_ballot_bit_count_inclusive', - 'nir_intrinsic_ballot_bit_count_reduce', - 'nir_intrinsic_ballot_bitfield_extract', - 'nir_intrinsic_ballot_find_lsb', 'nir_intrinsic_ballot_find_msb', - 'nir_intrinsic_ballot_relaxed', 'nir_intrinsic_bar_break_nv', - 'nir_intrinsic_bar_set_nv', 'nir_intrinsic_bar_sync_nv', - 'nir_intrinsic_barrier', - 'nir_intrinsic_begin_invocation_interlock', - 'nir_intrinsic_bindgen_return', - 'nir_intrinsic_bindless_image_agx', - 'nir_intrinsic_bindless_image_atomic', - 'nir_intrinsic_bindless_image_atomic_swap', - 'nir_intrinsic_bindless_image_descriptor_amd', - 'nir_intrinsic_bindless_image_format', - 'nir_intrinsic_bindless_image_fragment_mask_load_amd', - 'nir_intrinsic_bindless_image_levels', - 'nir_intrinsic_bindless_image_load', - 'nir_intrinsic_bindless_image_load_raw_intel', - 'nir_intrinsic_bindless_image_order', - 'nir_intrinsic_bindless_image_samples', - 'nir_intrinsic_bindless_image_samples_identical', - 'nir_intrinsic_bindless_image_size', - 'nir_intrinsic_bindless_image_sparse_load', - 'nir_intrinsic_bindless_image_store', - 'nir_intrinsic_bindless_image_store_block_agx', - 'nir_intrinsic_bindless_image_store_raw_intel', - 'nir_intrinsic_bindless_image_texel_address', - 'nir_intrinsic_bindless_resource_ir3', - 'nir_intrinsic_brcst_active_ir3', - 'nir_intrinsic_btd_retire_intel', 'nir_intrinsic_btd_spawn_intel', - 'nir_intrinsic_btd_stack_push_intel', - 'nir_intrinsic_bvh64_intersect_ray_amd', - 'nir_intrinsic_bvh8_intersect_ray_amd', - 'nir_intrinsic_bvh_stack_rtn_amd', 'nir_intrinsic_can_reorder', - 'nir_intrinsic_cmat_binary_op', 'nir_intrinsic_cmat_bitcast', - 'nir_intrinsic_cmat_construct', 'nir_intrinsic_cmat_convert', - 'nir_intrinsic_cmat_copy', 'nir_intrinsic_cmat_extract', - 'nir_intrinsic_cmat_insert', 'nir_intrinsic_cmat_length', - 'nir_intrinsic_cmat_load', 'nir_intrinsic_cmat_muladd', - 'nir_intrinsic_cmat_muladd_amd', 'nir_intrinsic_cmat_muladd_nv', - 'nir_intrinsic_cmat_scalar_op', 'nir_intrinsic_cmat_store', - 'nir_intrinsic_cmat_transpose', 'nir_intrinsic_cmat_unary_op', - 'nir_intrinsic_convert_alu_types', - 'nir_intrinsic_convert_cmat_intel', - 'nir_intrinsic_copy_const_indices', 'nir_intrinsic_copy_deref', - 'nir_intrinsic_copy_fs_outputs_nv', - 'nir_intrinsic_copy_global_to_uniform_ir3', - 'nir_intrinsic_copy_push_const_to_uniform_ir3', - 'nir_intrinsic_copy_ubo_to_uniform_ir3', 'nir_intrinsic_ddx', - 'nir_intrinsic_ddx_coarse', 'nir_intrinsic_ddx_fine', - 'nir_intrinsic_ddy', 'nir_intrinsic_ddy_coarse', - 'nir_intrinsic_ddy_fine', 'nir_intrinsic_debug_break', - 'nir_intrinsic_decl_reg', 'nir_intrinsic_demote', - 'nir_intrinsic_demote_if', 'nir_intrinsic_demote_samples', - 'nir_intrinsic_deref_atomic', 'nir_intrinsic_deref_atomic_swap', - 'nir_intrinsic_deref_buffer_array_length', - 'nir_intrinsic_deref_implicit_array_length', - 'nir_intrinsic_deref_mode_is', 'nir_intrinsic_deref_texture_src', - 'nir_intrinsic_dest_components', 'nir_intrinsic_doorbell_agx', - 'nir_intrinsic_dpas_intel', 'nir_intrinsic_dpp16_shift_amd', - 'nir_intrinsic_elect', 'nir_intrinsic_elect_any_ir3', - 'nir_intrinsic_emit_primitive_poly', 'nir_intrinsic_emit_vertex', - 'nir_intrinsic_emit_vertex_nv', - 'nir_intrinsic_emit_vertex_with_counter', - 'nir_intrinsic_end_invocation_interlock', - 'nir_intrinsic_end_primitive', 'nir_intrinsic_end_primitive_nv', - 'nir_intrinsic_end_primitive_with_counter', - 'nir_intrinsic_enqueue_node_payloads', - 'nir_intrinsic_exclusive_scan', - 'nir_intrinsic_exclusive_scan_clusters_ir3', - 'nir_intrinsic_execute_callable', - 'nir_intrinsic_execute_closest_hit_amd', - 'nir_intrinsic_execute_miss_amd', 'nir_intrinsic_export_agx', - 'nir_intrinsic_export_amd', - 'nir_intrinsic_export_dual_src_blend_amd', - 'nir_intrinsic_export_row_amd', - 'nir_intrinsic_fence_helper_exit_agx', - 'nir_intrinsic_fence_mem_to_tex_agx', - 'nir_intrinsic_fence_pbe_to_tex_agx', - 'nir_intrinsic_fence_pbe_to_tex_pixel_agx', - 'nir_intrinsic_final_primitive_nv', - 'nir_intrinsic_finalize_incoming_node_payload', - 'nir_intrinsic_first_invocation', - 'nir_intrinsic_from_system_value', 'nir_intrinsic_fs_out_nv', - 'nir_intrinsic_gds_atomic_add_amd', 'nir_intrinsic_get_ssbo_size', - 'nir_intrinsic_get_ubo_size', 'nir_intrinsic_get_var', - 'nir_intrinsic_global_atomic', 'nir_intrinsic_global_atomic_2x32', - 'nir_intrinsic_global_atomic_agx', - 'nir_intrinsic_global_atomic_amd', - 'nir_intrinsic_global_atomic_swap', - 'nir_intrinsic_global_atomic_swap_2x32', - 'nir_intrinsic_global_atomic_swap_agx', - 'nir_intrinsic_global_atomic_swap_amd', 'nir_intrinsic_has_align', - 'nir_intrinsic_has_semantic', - 'nir_intrinsic_ignore_ray_intersection', - 'nir_intrinsic_imadsp_nv', 'nir_intrinsic_image_atomic', - 'nir_intrinsic_image_atomic_swap', - 'nir_intrinsic_image_deref_atomic', - 'nir_intrinsic_image_deref_atomic_swap', - 'nir_intrinsic_image_deref_descriptor_amd', - 'nir_intrinsic_image_deref_format', - 'nir_intrinsic_image_deref_fragment_mask_load_amd', - 'nir_intrinsic_image_deref_levels', - 'nir_intrinsic_image_deref_load', - 'nir_intrinsic_image_deref_load_info_nv', - 'nir_intrinsic_image_deref_load_param_intel', - 'nir_intrinsic_image_deref_load_raw_intel', - 'nir_intrinsic_image_deref_order', - 'nir_intrinsic_image_deref_samples', - 'nir_intrinsic_image_deref_samples_identical', - 'nir_intrinsic_image_deref_size', - 'nir_intrinsic_image_deref_sparse_load', - 'nir_intrinsic_image_deref_store', - 'nir_intrinsic_image_deref_store_block_agx', - 'nir_intrinsic_image_deref_store_raw_intel', - 'nir_intrinsic_image_deref_texel_address', - 'nir_intrinsic_image_descriptor_amd', - 'nir_intrinsic_image_format', - 'nir_intrinsic_image_fragment_mask_load_amd', - 'nir_intrinsic_image_levels', 'nir_intrinsic_image_load', - 'nir_intrinsic_image_load_raw_intel', 'nir_intrinsic_image_order', - 'nir_intrinsic_image_samples', - 'nir_intrinsic_image_samples_identical', - 'nir_intrinsic_image_size', 'nir_intrinsic_image_sparse_load', - 'nir_intrinsic_image_store', - 'nir_intrinsic_image_store_block_agx', - 'nir_intrinsic_image_store_raw_intel', - 'nir_intrinsic_image_texel_address', - 'nir_intrinsic_inclusive_scan', - 'nir_intrinsic_inclusive_scan_clusters_ir3', - 'nir_intrinsic_index_flag', - 'nir_intrinsic_index_flag__enumvalues', - 'nir_intrinsic_index_names', 'nir_intrinsic_info', - 'nir_intrinsic_infos', 'nir_intrinsic_initialize_node_payloads', - 'nir_intrinsic_instr', 'nir_intrinsic_instr_create', - 'nir_intrinsic_instr_dest_type', 'nir_intrinsic_instr_src_type', - 'nir_intrinsic_interp_deref_at_centroid', - 'nir_intrinsic_interp_deref_at_offset', - 'nir_intrinsic_interp_deref_at_sample', - 'nir_intrinsic_interp_deref_at_vertex', - 'nir_intrinsic_inverse_ballot', 'nir_intrinsic_ipa_nv', - 'nir_intrinsic_is_helper_invocation', - 'nir_intrinsic_is_ray_query', - 'nir_intrinsic_is_sparse_resident_zink', - 'nir_intrinsic_is_sparse_texels_resident', - 'nir_intrinsic_is_subgroup_invocation_lt_amd', - 'nir_intrinsic_isberd_nv', 'nir_intrinsic_lane_permute_16_amd', - 'nir_intrinsic_last_invocation', - 'nir_intrinsic_launch_mesh_workgroups', - 'nir_intrinsic_launch_mesh_workgroups_with_payload_deref', - 'nir_intrinsic_ldc_nv', 'nir_intrinsic_ldcx_nv', - 'nir_intrinsic_ldtram_nv', 'nir_intrinsic_load_aa_line_width', - 'nir_intrinsic_load_accel_struct_amd', - 'nir_intrinsic_load_active_samples_agx', - 'nir_intrinsic_load_active_subgroup_count_agx', - 'nir_intrinsic_load_active_subgroup_invocation_agx', - 'nir_intrinsic_load_agx', - 'nir_intrinsic_load_alpha_reference_amd', - 'nir_intrinsic_load_api_sample_mask_agx', - 'nir_intrinsic_load_attrib_clamp_agx', - 'nir_intrinsic_load_attribute_pan', - 'nir_intrinsic_load_back_face_agx', - 'nir_intrinsic_load_barycentric_at_offset', - 'nir_intrinsic_load_barycentric_at_offset_nv', - 'nir_intrinsic_load_barycentric_at_sample', - 'nir_intrinsic_load_barycentric_centroid', - 'nir_intrinsic_load_barycentric_coord_at_offset', - 'nir_intrinsic_load_barycentric_coord_at_sample', - 'nir_intrinsic_load_barycentric_coord_centroid', - 'nir_intrinsic_load_barycentric_coord_pixel', - 'nir_intrinsic_load_barycentric_coord_sample', - 'nir_intrinsic_load_barycentric_model', - 'nir_intrinsic_load_barycentric_optimize_amd', - 'nir_intrinsic_load_barycentric_pixel', - 'nir_intrinsic_load_barycentric_sample', - 'nir_intrinsic_load_base_global_invocation_id', - 'nir_intrinsic_load_base_instance', - 'nir_intrinsic_load_base_vertex', - 'nir_intrinsic_load_base_workgroup_id', - 'nir_intrinsic_load_blend_const_color_a_float', - 'nir_intrinsic_load_blend_const_color_aaaa8888_unorm', - 'nir_intrinsic_load_blend_const_color_b_float', - 'nir_intrinsic_load_blend_const_color_g_float', - 'nir_intrinsic_load_blend_const_color_r_float', - 'nir_intrinsic_load_blend_const_color_rgba', - 'nir_intrinsic_load_blend_const_color_rgba8888_unorm', - 'nir_intrinsic_load_btd_global_arg_addr_intel', - 'nir_intrinsic_load_btd_local_arg_addr_intel', - 'nir_intrinsic_load_btd_resume_sbt_addr_intel', - 'nir_intrinsic_load_btd_shader_type_intel', - 'nir_intrinsic_load_btd_stack_id_intel', - 'nir_intrinsic_load_buffer_amd', - 'nir_intrinsic_load_callable_sbt_addr_intel', - 'nir_intrinsic_load_callable_sbt_stride_intel', - 'nir_intrinsic_load_clamp_vertex_color_amd', - 'nir_intrinsic_load_clip_half_line_width_amd', - 'nir_intrinsic_load_clip_z_coeff_agx', - 'nir_intrinsic_load_coalesced_input_count', - 'nir_intrinsic_load_coefficients_agx', - 'nir_intrinsic_load_color0', 'nir_intrinsic_load_color1', - 'nir_intrinsic_load_const_buf_base_addr_lvp', - 'nir_intrinsic_load_const_ir3', 'nir_intrinsic_load_constant', - 'nir_intrinsic_load_constant_agx', - 'nir_intrinsic_load_constant_base_ptr', - 'nir_intrinsic_load_converted_output_pan', - 'nir_intrinsic_load_core_id_agx', - 'nir_intrinsic_load_cull_any_enabled_amd', - 'nir_intrinsic_load_cull_back_face_enabled_amd', - 'nir_intrinsic_load_cull_ccw_amd', - 'nir_intrinsic_load_cull_front_face_enabled_amd', - 'nir_intrinsic_load_cull_line_viewport_xy_scale_and_offset_amd', - 'nir_intrinsic_load_cull_mask', - 'nir_intrinsic_load_cull_mask_and_flags_amd', - 'nir_intrinsic_load_cull_small_line_precision_amd', - 'nir_intrinsic_load_cull_small_lines_enabled_amd', - 'nir_intrinsic_load_cull_small_triangle_precision_amd', - 'nir_intrinsic_load_cull_small_triangles_enabled_amd', - 'nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd', - 'nir_intrinsic_load_debug_log_desc_amd', - 'nir_intrinsic_load_depth_never_agx', 'nir_intrinsic_load_deref', - 'nir_intrinsic_load_deref_block_intel', - 'nir_intrinsic_load_draw_id', - 'nir_intrinsic_load_esgs_vertex_stride_amd', - 'nir_intrinsic_load_exported_agx', - 'nir_intrinsic_load_fb_layers_v3d', - 'nir_intrinsic_load_fbfetch_image_desc_amd', - 'nir_intrinsic_load_fbfetch_image_fmask_desc_amd', - 'nir_intrinsic_load_fep_w_v3d', 'nir_intrinsic_load_first_vertex', - 'nir_intrinsic_load_fixed_point_size_agx', - 'nir_intrinsic_load_flat_mask', - 'nir_intrinsic_load_force_vrs_rates_amd', - 'nir_intrinsic_load_frag_coord', - 'nir_intrinsic_load_frag_coord_unscaled_ir3', - 'nir_intrinsic_load_frag_coord_w', - 'nir_intrinsic_load_frag_coord_z', - 'nir_intrinsic_load_frag_coord_zw_pan', - 'nir_intrinsic_load_frag_invocation_count', - 'nir_intrinsic_load_frag_offset_ir3', - 'nir_intrinsic_load_frag_shading_rate', - 'nir_intrinsic_load_frag_size', - 'nir_intrinsic_load_frag_size_ir3', - 'nir_intrinsic_load_from_texture_handle_agx', - 'nir_intrinsic_load_front_face', - 'nir_intrinsic_load_front_face_fsign', - 'nir_intrinsic_load_fs_input_interp_deltas', - 'nir_intrinsic_load_fs_msaa_intel', - 'nir_intrinsic_load_fully_covered', - 'nir_intrinsic_load_geometry_param_buffer_poly', - 'nir_intrinsic_load_global', 'nir_intrinsic_load_global_2x32', - 'nir_intrinsic_load_global_amd', - 'nir_intrinsic_load_global_base_ptr', - 'nir_intrinsic_load_global_block_intel', - 'nir_intrinsic_load_global_bounded', - 'nir_intrinsic_load_global_constant', - 'nir_intrinsic_load_global_constant_bounded', - 'nir_intrinsic_load_global_constant_offset', - 'nir_intrinsic_load_global_constant_uniform_block_intel', - 'nir_intrinsic_load_global_etna', - 'nir_intrinsic_load_global_invocation_id', - 'nir_intrinsic_load_global_invocation_index', - 'nir_intrinsic_load_global_ir3', 'nir_intrinsic_load_global_size', - 'nir_intrinsic_load_gs_header_ir3', - 'nir_intrinsic_load_gs_vertex_offset_amd', - 'nir_intrinsic_load_gs_wave_id_amd', - 'nir_intrinsic_load_helper_arg_hi_agx', - 'nir_intrinsic_load_helper_arg_lo_agx', - 'nir_intrinsic_load_helper_invocation', - 'nir_intrinsic_load_helper_op_id_agx', - 'nir_intrinsic_load_hit_attrib_amd', - 'nir_intrinsic_load_hs_out_patch_data_offset_amd', - 'nir_intrinsic_load_hs_patch_stride_ir3', - 'nir_intrinsic_load_initial_edgeflags_amd', - 'nir_intrinsic_load_inline_data_intel', - 'nir_intrinsic_load_input', - 'nir_intrinsic_load_input_assembly_buffer_poly', - 'nir_intrinsic_load_input_attachment_conv_pan', - 'nir_intrinsic_load_input_attachment_coord', - 'nir_intrinsic_load_input_attachment_target_pan', - 'nir_intrinsic_load_input_topology_poly', - 'nir_intrinsic_load_input_vertex', - 'nir_intrinsic_load_instance_id', - 'nir_intrinsic_load_interpolated_input', - 'nir_intrinsic_load_intersection_opaque_amd', - 'nir_intrinsic_load_invocation_id', - 'nir_intrinsic_load_is_first_fan_agx', - 'nir_intrinsic_load_is_indexed_draw', - 'nir_intrinsic_load_kernel_input', 'nir_intrinsic_load_layer_id', - 'nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd', - 'nir_intrinsic_load_leaf_opaque_intel', - 'nir_intrinsic_load_leaf_procedural_intel', - 'nir_intrinsic_load_line_coord', 'nir_intrinsic_load_line_width', - 'nir_intrinsic_load_local_invocation_id', - 'nir_intrinsic_load_local_invocation_index', - 'nir_intrinsic_load_local_pixel_agx', - 'nir_intrinsic_load_local_shared_r600', - 'nir_intrinsic_load_lshs_vertex_stride_amd', - 'nir_intrinsic_load_max_polygon_intel', - 'nir_intrinsic_load_merged_wave_info_amd', - 'nir_intrinsic_load_mesh_view_count', - 'nir_intrinsic_load_mesh_view_indices', - 'nir_intrinsic_load_multisampled_pan', - 'nir_intrinsic_load_noperspective_varyings_pan', - 'nir_intrinsic_load_num_subgroups', - 'nir_intrinsic_load_num_vertices', - 'nir_intrinsic_load_num_vertices_per_primitive_amd', - 'nir_intrinsic_load_num_workgroups', - 'nir_intrinsic_load_ordered_id_amd', 'nir_intrinsic_load_output', - 'nir_intrinsic_load_packed_passthrough_primitive_amd', - 'nir_intrinsic_load_param', - 'nir_intrinsic_load_patch_vertices_in', - 'nir_intrinsic_load_per_primitive_input', - 'nir_intrinsic_load_per_primitive_output', - 'nir_intrinsic_load_per_primitive_remap_intel', - 'nir_intrinsic_load_per_vertex_input', - 'nir_intrinsic_load_per_vertex_output', - 'nir_intrinsic_load_per_view_output', - 'nir_intrinsic_load_persp_center_rhw_ir3', - 'nir_intrinsic_load_pipeline_stat_query_enabled_amd', - 'nir_intrinsic_load_pixel_coord', - 'nir_intrinsic_load_point_coord', - 'nir_intrinsic_load_point_coord_maybe_flipped', - 'nir_intrinsic_load_poly_line_smooth_enabled', - 'nir_intrinsic_load_polygon_stipple_agx', - 'nir_intrinsic_load_polygon_stipple_buffer_amd', - 'nir_intrinsic_load_preamble', - 'nir_intrinsic_load_prim_gen_query_enabled_amd', - 'nir_intrinsic_load_prim_xfb_query_enabled_amd', - 'nir_intrinsic_load_primitive_id', - 'nir_intrinsic_load_primitive_location_ir3', - 'nir_intrinsic_load_printf_buffer_address', - 'nir_intrinsic_load_printf_buffer_size', - 'nir_intrinsic_load_provoking_last', - 'nir_intrinsic_load_provoking_vtx_amd', - 'nir_intrinsic_load_provoking_vtx_in_prim_amd', - 'nir_intrinsic_load_push_constant', - 'nir_intrinsic_load_push_constant_zink', - 'nir_intrinsic_load_r600_indirect_per_vertex_input', - 'nir_intrinsic_load_rasterization_primitive_amd', - 'nir_intrinsic_load_rasterization_samples_amd', - 'nir_intrinsic_load_rasterization_stream', - 'nir_intrinsic_load_raw_output_pan', - 'nir_intrinsic_load_raw_vertex_id_pan', - 'nir_intrinsic_load_raw_vertex_offset_pan', - 'nir_intrinsic_load_ray_base_mem_addr_intel', - 'nir_intrinsic_load_ray_flags', - 'nir_intrinsic_load_ray_geometry_index', - 'nir_intrinsic_load_ray_hit_kind', - 'nir_intrinsic_load_ray_hit_sbt_addr_intel', - 'nir_intrinsic_load_ray_hit_sbt_stride_intel', - 'nir_intrinsic_load_ray_hw_stack_size_intel', - 'nir_intrinsic_load_ray_instance_custom_index', - 'nir_intrinsic_load_ray_launch_id', - 'nir_intrinsic_load_ray_launch_size', - 'nir_intrinsic_load_ray_miss_sbt_addr_intel', - 'nir_intrinsic_load_ray_miss_sbt_stride_intel', - 'nir_intrinsic_load_ray_num_dss_rt_stacks_intel', - 'nir_intrinsic_load_ray_object_direction', - 'nir_intrinsic_load_ray_object_origin', - 'nir_intrinsic_load_ray_object_to_world', - 'nir_intrinsic_load_ray_query_global_intel', - 'nir_intrinsic_load_ray_sw_stack_size_intel', - 'nir_intrinsic_load_ray_t_max', 'nir_intrinsic_load_ray_t_min', - 'nir_intrinsic_load_ray_tracing_stack_base_lvp', - 'nir_intrinsic_load_ray_triangle_vertex_positions', - 'nir_intrinsic_load_ray_world_direction', - 'nir_intrinsic_load_ray_world_origin', - 'nir_intrinsic_load_ray_world_to_object', - 'nir_intrinsic_load_readonly_output_pan', - 'nir_intrinsic_load_reg', 'nir_intrinsic_load_reg_indirect', - 'nir_intrinsic_load_rel_patch_id_ir3', - 'nir_intrinsic_load_reloc_const_intel', - 'nir_intrinsic_load_resume_shader_address_amd', - 'nir_intrinsic_load_ring_attr_amd', - 'nir_intrinsic_load_ring_attr_offset_amd', - 'nir_intrinsic_load_ring_es2gs_offset_amd', - 'nir_intrinsic_load_ring_esgs_amd', - 'nir_intrinsic_load_ring_gs2vs_offset_amd', - 'nir_intrinsic_load_ring_gsvs_amd', - 'nir_intrinsic_load_ring_mesh_scratch_amd', - 'nir_intrinsic_load_ring_mesh_scratch_offset_amd', - 'nir_intrinsic_load_ring_task_draw_amd', - 'nir_intrinsic_load_ring_task_payload_amd', - 'nir_intrinsic_load_ring_tess_factors_amd', - 'nir_intrinsic_load_ring_tess_factors_offset_amd', - 'nir_intrinsic_load_ring_tess_offchip_amd', - 'nir_intrinsic_load_ring_tess_offchip_offset_amd', - 'nir_intrinsic_load_root_agx', - 'nir_intrinsic_load_rt_arg_scratch_offset_amd', - 'nir_intrinsic_load_rt_conversion_pan', - 'nir_intrinsic_load_sample_id', - 'nir_intrinsic_load_sample_id_no_per_sample', - 'nir_intrinsic_load_sample_mask', - 'nir_intrinsic_load_sample_mask_in', - 'nir_intrinsic_load_sample_pos', - 'nir_intrinsic_load_sample_pos_from_id', - 'nir_intrinsic_load_sample_pos_or_center', - 'nir_intrinsic_load_sample_positions_agx', - 'nir_intrinsic_load_sample_positions_amd', - 'nir_intrinsic_load_sample_positions_pan', - 'nir_intrinsic_load_sampler_handle_agx', - 'nir_intrinsic_load_sampler_lod_parameters', - 'nir_intrinsic_load_samples_log2_agx', - 'nir_intrinsic_load_sbt_base_amd', - 'nir_intrinsic_load_sbt_offset_amd', - 'nir_intrinsic_load_sbt_stride_amd', - 'nir_intrinsic_load_scalar_arg_amd', 'nir_intrinsic_load_scratch', - 'nir_intrinsic_load_scratch_base_ptr', - 'nir_intrinsic_load_shader_call_data_offset_lvp', - 'nir_intrinsic_load_shader_index', - 'nir_intrinsic_load_shader_output_pan', - 'nir_intrinsic_load_shader_part_tests_zs_agx', - 'nir_intrinsic_load_shader_record_ptr', - 'nir_intrinsic_load_shared', 'nir_intrinsic_load_shared2_amd', - 'nir_intrinsic_load_shared_base_ptr', - 'nir_intrinsic_load_shared_block_intel', - 'nir_intrinsic_load_shared_ir3', - 'nir_intrinsic_load_shared_lock_nv', - 'nir_intrinsic_load_shared_uniform_block_intel', - 'nir_intrinsic_load_simd_width_intel', - 'nir_intrinsic_load_sm_count_nv', 'nir_intrinsic_load_sm_id_nv', - 'nir_intrinsic_load_smem_amd', 'nir_intrinsic_load_ssbo', - 'nir_intrinsic_load_ssbo_address', - 'nir_intrinsic_load_ssbo_block_intel', - 'nir_intrinsic_load_ssbo_intel', 'nir_intrinsic_load_ssbo_ir3', - 'nir_intrinsic_load_ssbo_uniform_block_intel', - 'nir_intrinsic_load_stack', - 'nir_intrinsic_load_stat_query_address_agx', - 'nir_intrinsic_load_streamout_buffer_amd', - 'nir_intrinsic_load_streamout_config_amd', - 'nir_intrinsic_load_streamout_offset_amd', - 'nir_intrinsic_load_streamout_write_index_amd', - 'nir_intrinsic_load_subgroup_eq_mask', - 'nir_intrinsic_load_subgroup_ge_mask', - 'nir_intrinsic_load_subgroup_gt_mask', - 'nir_intrinsic_load_subgroup_id', - 'nir_intrinsic_load_subgroup_id_shift_ir3', - 'nir_intrinsic_load_subgroup_invocation', - 'nir_intrinsic_load_subgroup_le_mask', - 'nir_intrinsic_load_subgroup_lt_mask', - 'nir_intrinsic_load_subgroup_size', - 'nir_intrinsic_load_sysval_agx', 'nir_intrinsic_load_sysval_nv', - 'nir_intrinsic_load_task_payload', - 'nir_intrinsic_load_task_ring_entry_amd', - 'nir_intrinsic_load_tcs_header_ir3', - 'nir_intrinsic_load_tcs_in_param_base_r600', - 'nir_intrinsic_load_tcs_mem_attrib_stride', - 'nir_intrinsic_load_tcs_num_patches_amd', - 'nir_intrinsic_load_tcs_out_param_base_r600', - 'nir_intrinsic_load_tcs_primitive_mode_amd', - 'nir_intrinsic_load_tcs_rel_patch_id_r600', - 'nir_intrinsic_load_tcs_tess_factor_base_r600', - 'nir_intrinsic_load_tcs_tess_levels_to_tes_amd', - 'nir_intrinsic_load_tess_coord', - 'nir_intrinsic_load_tess_coord_xy', - 'nir_intrinsic_load_tess_factor_base_ir3', - 'nir_intrinsic_load_tess_level_inner', - 'nir_intrinsic_load_tess_level_inner_default', - 'nir_intrinsic_load_tess_level_outer', - 'nir_intrinsic_load_tess_level_outer_default', - 'nir_intrinsic_load_tess_param_base_ir3', - 'nir_intrinsic_load_tess_param_buffer_poly', - 'nir_intrinsic_load_tess_rel_patch_id_amd', - 'nir_intrinsic_load_tex_sprite_mask_agx', - 'nir_intrinsic_load_texture_handle_agx', - 'nir_intrinsic_load_texture_scale', - 'nir_intrinsic_load_texture_size_etna', - 'nir_intrinsic_load_tlb_color_brcm', - 'nir_intrinsic_load_topology_id_intel', - 'nir_intrinsic_load_typed_buffer_amd', - 'nir_intrinsic_load_uav_ir3', 'nir_intrinsic_load_ubo', - 'nir_intrinsic_load_ubo_uniform_block_intel', - 'nir_intrinsic_load_ubo_vec4', 'nir_intrinsic_load_uniform', - 'nir_intrinsic_load_user_clip_plane', - 'nir_intrinsic_load_user_data_amd', - 'nir_intrinsic_load_uvs_index_agx', - 'nir_intrinsic_load_vbo_base_agx', - 'nir_intrinsic_load_vector_arg_amd', - 'nir_intrinsic_load_vertex_id', - 'nir_intrinsic_load_vertex_id_zero_base', - 'nir_intrinsic_load_view_index', - 'nir_intrinsic_load_viewport_offset', - 'nir_intrinsic_load_viewport_scale', - 'nir_intrinsic_load_viewport_x_offset', - 'nir_intrinsic_load_viewport_x_scale', - 'nir_intrinsic_load_viewport_y_offset', - 'nir_intrinsic_load_viewport_y_scale', - 'nir_intrinsic_load_viewport_z_offset', - 'nir_intrinsic_load_viewport_z_scale', - 'nir_intrinsic_load_vs_output_buffer_poly', - 'nir_intrinsic_load_vs_outputs_poly', - 'nir_intrinsic_load_vs_primitive_stride_ir3', - 'nir_intrinsic_load_vs_vertex_stride_ir3', - 'nir_intrinsic_load_vulkan_descriptor', - 'nir_intrinsic_load_warp_id_nv', - 'nir_intrinsic_load_warps_per_sm_nv', - 'nir_intrinsic_load_work_dim', 'nir_intrinsic_load_workgroup_id', - 'nir_intrinsic_load_workgroup_index', - 'nir_intrinsic_load_workgroup_num_input_primitives_amd', - 'nir_intrinsic_load_workgroup_num_input_vertices_amd', - 'nir_intrinsic_load_workgroup_size', - 'nir_intrinsic_load_xfb_address', - 'nir_intrinsic_load_xfb_index_buffer', - 'nir_intrinsic_load_xfb_size', - 'nir_intrinsic_load_xfb_state_address_gfx12_amd', - 'nir_intrinsic_masked_swizzle_amd', 'nir_intrinsic_mbcnt_amd', - 'nir_intrinsic_memcpy_deref', 'nir_intrinsic_nop', - 'nir_intrinsic_nop_amd', 'nir_intrinsic_op', - 'nir_intrinsic_op__enumvalues', - 'nir_intrinsic_optimization_barrier_sgpr_amd', - 'nir_intrinsic_optimization_barrier_vgpr_amd', - 'nir_intrinsic_ordered_add_loop_gfx12_amd', - 'nir_intrinsic_ordered_xfb_counter_add_gfx11_amd', - 'nir_intrinsic_overwrite_tes_arguments_amd', - 'nir_intrinsic_overwrite_vs_arguments_amd', - 'nir_intrinsic_pass_cb', 'nir_intrinsic_pin_cx_handle_nv', - 'nir_intrinsic_preamble_end_ir3', - 'nir_intrinsic_preamble_start_ir3', - 'nir_intrinsic_prefetch_sam_ir3', - 'nir_intrinsic_prefetch_tex_ir3', - 'nir_intrinsic_prefetch_ubo_ir3', 'nir_intrinsic_printf', - 'nir_intrinsic_printf_abort', 'nir_intrinsic_quad_ballot_agx', - 'nir_intrinsic_quad_broadcast', - 'nir_intrinsic_quad_swap_diagonal', - 'nir_intrinsic_quad_swap_horizontal', - 'nir_intrinsic_quad_swap_vertical', - 'nir_intrinsic_quad_swizzle_amd', 'nir_intrinsic_quad_vote_all', - 'nir_intrinsic_quad_vote_any', - 'nir_intrinsic_r600_indirect_vertex_at_index', - 'nir_intrinsic_ray_intersection_ir3', - 'nir_intrinsic_read_attribute_payload_intel', - 'nir_intrinsic_read_first_invocation', - 'nir_intrinsic_read_getlast_ir3', 'nir_intrinsic_read_invocation', - 'nir_intrinsic_read_invocation_cond_ir3', 'nir_intrinsic_reduce', - 'nir_intrinsic_reduce_clusters_ir3', - 'nir_intrinsic_report_ray_intersection', - 'nir_intrinsic_resource_intel', 'nir_intrinsic_rotate', - 'nir_intrinsic_rq_confirm_intersection', - 'nir_intrinsic_rq_generate_intersection', - 'nir_intrinsic_rq_initialize', 'nir_intrinsic_rq_load', - 'nir_intrinsic_rq_proceed', 'nir_intrinsic_rq_terminate', - 'nir_intrinsic_rt_execute_callable', 'nir_intrinsic_rt_resume', - 'nir_intrinsic_rt_return_amd', 'nir_intrinsic_rt_trace_ray', - 'nir_intrinsic_sample_mask_agx', - 'nir_intrinsic_select_vertex_poly', 'nir_intrinsic_semantic_flag', - 'nir_intrinsic_semantic_flag__enumvalues', - 'nir_intrinsic_sendmsg_amd', 'nir_intrinsic_set_align', - 'nir_intrinsic_set_vertex_and_primitive_count', - 'nir_intrinsic_shader_clock', 'nir_intrinsic_shared_append_amd', - 'nir_intrinsic_shared_atomic', 'nir_intrinsic_shared_atomic_swap', - 'nir_intrinsic_shared_consume_amd', 'nir_intrinsic_shuffle', - 'nir_intrinsic_shuffle_down', - 'nir_intrinsic_shuffle_down_uniform_ir3', - 'nir_intrinsic_shuffle_up', - 'nir_intrinsic_shuffle_up_uniform_ir3', - 'nir_intrinsic_shuffle_xor', - 'nir_intrinsic_shuffle_xor_uniform_ir3', - 'nir_intrinsic_sleep_amd', - 'nir_intrinsic_sparse_residency_code_and', - 'nir_intrinsic_src_components', 'nir_intrinsic_ssa_bar_nv', - 'nir_intrinsic_ssbo_atomic', 'nir_intrinsic_ssbo_atomic_ir3', - 'nir_intrinsic_ssbo_atomic_swap', - 'nir_intrinsic_ssbo_atomic_swap_ir3', - 'nir_intrinsic_stack_map_agx', 'nir_intrinsic_stack_unmap_agx', - 'nir_intrinsic_store_agx', 'nir_intrinsic_store_buffer_amd', - 'nir_intrinsic_store_combined_output_pan', - 'nir_intrinsic_store_const_ir3', 'nir_intrinsic_store_deref', - 'nir_intrinsic_store_deref_block_intel', - 'nir_intrinsic_store_global', 'nir_intrinsic_store_global_2x32', - 'nir_intrinsic_store_global_amd', - 'nir_intrinsic_store_global_block_intel', - 'nir_intrinsic_store_global_etna', - 'nir_intrinsic_store_global_ir3', - 'nir_intrinsic_store_hit_attrib_amd', - 'nir_intrinsic_store_local_pixel_agx', - 'nir_intrinsic_store_local_shared_r600', - 'nir_intrinsic_store_output', - 'nir_intrinsic_store_per_primitive_output', - 'nir_intrinsic_store_per_primitive_payload_intel', - 'nir_intrinsic_store_per_vertex_output', - 'nir_intrinsic_store_per_view_output', - 'nir_intrinsic_store_preamble', - 'nir_intrinsic_store_raw_output_pan', 'nir_intrinsic_store_reg', - 'nir_intrinsic_store_reg_indirect', - 'nir_intrinsic_store_scalar_arg_amd', - 'nir_intrinsic_store_scratch', 'nir_intrinsic_store_shared', - 'nir_intrinsic_store_shared2_amd', - 'nir_intrinsic_store_shared_block_intel', - 'nir_intrinsic_store_shared_ir3', - 'nir_intrinsic_store_shared_unlock_nv', - 'nir_intrinsic_store_ssbo', - 'nir_intrinsic_store_ssbo_block_intel', - 'nir_intrinsic_store_ssbo_intel', 'nir_intrinsic_store_ssbo_ir3', - 'nir_intrinsic_store_stack', 'nir_intrinsic_store_task_payload', - 'nir_intrinsic_store_tf_r600', - 'nir_intrinsic_store_tlb_sample_color_v3d', - 'nir_intrinsic_store_uvs_agx', - 'nir_intrinsic_store_vector_arg_amd', - 'nir_intrinsic_store_zs_agx', - 'nir_intrinsic_strict_wqm_coord_amd', 'nir_intrinsic_subfm_nv', - 'nir_intrinsic_suclamp_nv', 'nir_intrinsic_sueau_nv', - 'nir_intrinsic_suldga_nv', 'nir_intrinsic_sustga_nv', - 'nir_intrinsic_task_payload_atomic', - 'nir_intrinsic_task_payload_atomic_swap', - 'nir_intrinsic_terminate', 'nir_intrinsic_terminate_if', - 'nir_intrinsic_terminate_ray', 'nir_intrinsic_trace_ray', - 'nir_intrinsic_trace_ray_intel', 'nir_intrinsic_unit_test_amd', - 'nir_intrinsic_unit_test_divergent_amd', - 'nir_intrinsic_unit_test_uniform_amd', - 'nir_intrinsic_unpin_cx_handle_nv', 'nir_intrinsic_use', - 'nir_intrinsic_vild_nv', 'nir_intrinsic_vote_all', - 'nir_intrinsic_vote_any', 'nir_intrinsic_vote_feq', - 'nir_intrinsic_vote_ieq', 'nir_intrinsic_vulkan_resource_index', - 'nir_intrinsic_vulkan_resource_reindex', - 'nir_intrinsic_write_invocation_amd', - 'nir_intrinsic_writes_external_memory', - 'nir_intrinsic_xfb_counter_sub_gfx11_amd', - 'nir_io_16bit_input_output_support', - 'nir_io_add_const_offset_to_base', - 'nir_io_add_intrinsic_xfb_info', - 'nir_io_always_interpolate_convergent_fs_inputs', - 'nir_io_compaction_groups_tes_inputs_into_pos_and_var_groups', - 'nir_io_compaction_rotates_color_channels', - 'nir_io_dont_use_pos_for_non_fs_varyings', - 'nir_io_has_flexible_input_interpolation_except_flat', - 'nir_io_has_intrinsics', 'nir_io_mediump_is_32bit', - 'nir_io_mix_convergent_flat_with_interpolated', 'nir_io_options', - 'nir_io_options__enumvalues', 'nir_io_prefer_scalar_fs_inputs', - 'nir_io_radv_intrinsic_component_workaround', 'nir_io_semantics', - 'nir_io_separate_clip_cull_distance_arrays', - 'nir_io_vectorizer_ignores_types', 'nir_io_xfb', 'nir_ior_imm', - 'nir_is_arrayed_io', 'nir_is_denorm_flush_to_zero', - 'nir_is_denorm_preserve', 'nir_is_float_control_inf_preserve', - 'nir_is_float_control_nan_preserve', - 'nir_is_float_control_signed_zero_inf_nan_preserve', - 'nir_is_float_control_signed_zero_preserve', 'nir_is_load_reg', - 'nir_is_output_load', 'nir_is_rounding_mode_rtne', - 'nir_is_rounding_mode_rtz', 'nir_is_same_comp_swizzle', - 'nir_is_sequential_comp_swizzle', 'nir_is_store_reg', - 'nir_ishl_imm', 'nir_ishr_imm', 'nir_isub_imm', 'nir_jump', - 'nir_jump_break', 'nir_jump_continue', 'nir_jump_goto', - 'nir_jump_goto_if', 'nir_jump_halt', 'nir_jump_instr', - 'nir_jump_instr_create', 'nir_jump_return', 'nir_jump_type', - 'nir_jump_type__enumvalues', 'nir_last_intrinsic', - 'nir_last_opcode', 'nir_legalize_16bit_sampler_srcs', - 'nir_link_opt_varyings', 'nir_link_shader_functions', - 'nir_link_varying_precision', 'nir_link_xfb_varyings', - 'nir_live_defs_impl', 'nir_load_array_var', - 'nir_load_array_var_imm', 'nir_load_barycentric', - 'nir_load_const_instr', 'nir_load_const_instr_create', - 'nir_load_deref', 'nir_load_deref_with_access', 'nir_load_global', - 'nir_load_global_constant', 'nir_load_grouping', - 'nir_load_grouping__enumvalues', 'nir_load_param', 'nir_load_reg', - 'nir_load_reg_for_def', 'nir_load_store_vectorize_options', - 'nir_load_system_value', 'nir_load_var', - 'nir_local_variable_create', 'nir_log_shader_annotated_tagged', - 'nir_loop', 'nir_loop_analyze_impl', 'nir_loop_continue_target', - 'nir_loop_control', 'nir_loop_control__enumvalues', - 'nir_loop_control_dont_unroll', 'nir_loop_control_none', - 'nir_loop_control_unroll', 'nir_loop_create', - 'nir_loop_first_block', 'nir_loop_first_continue_block', - 'nir_loop_has_continue_construct', 'nir_loop_induction_variable', - 'nir_loop_info', 'nir_loop_is_divergent', 'nir_loop_last_block', - 'nir_loop_last_continue_block', 'nir_loop_terminator', - 'nir_lower_64bit_phis', 'nir_lower_all_phis_to_scalar', - 'nir_lower_alpha_test', 'nir_lower_alpha_to_coverage', - 'nir_lower_alpha_to_one', 'nir_lower_alu', - 'nir_lower_alu_conversion_to_intrinsic', - 'nir_lower_alu_to_scalar', 'nir_lower_alu_vec8_16_srcs', - 'nir_lower_alu_width', 'nir_lower_amul', - 'nir_lower_array_deref_of_vec', - 'nir_lower_array_deref_of_vec_options', - 'nir_lower_array_deref_of_vec_options__enumvalues', - 'nir_lower_atomics', 'nir_lower_atomics_to_ssbo', - 'nir_lower_bcsel64', 'nir_lower_bit_count64', - 'nir_lower_bit_size', 'nir_lower_bit_size_callback', - 'nir_lower_bitfield_extract64', 'nir_lower_bitfield_reverse64', - 'nir_lower_bitmap', 'nir_lower_bitmap_options', - 'nir_lower_bool_to_bitsize', 'nir_lower_bool_to_float', - 'nir_lower_bool_to_int32', 'nir_lower_calls_to_builtins', - 'nir_lower_cl_images', 'nir_lower_clamp_color_outputs', - 'nir_lower_clip_cull_distance_array_vars', - 'nir_lower_clip_cull_distance_to_vec4s', 'nir_lower_clip_disable', - 'nir_lower_clip_fs', 'nir_lower_clip_gs', 'nir_lower_clip_halfz', - 'nir_lower_clip_vs', 'nir_lower_compute_system_values', - 'nir_lower_compute_system_values_options', - 'nir_lower_const_arrays_to_uniforms', - 'nir_lower_constant_convert_alu_types', - 'nir_lower_constant_to_temp', 'nir_lower_continue_constructs', - 'nir_lower_conv64', 'nir_lower_convert_alu_types', - 'nir_lower_dceil', 'nir_lower_ddiv', - 'nir_lower_default_point_size', 'nir_lower_demote_if_to_cf', - 'nir_lower_deref_copy_instr', 'nir_lower_dfloor', - 'nir_lower_dfract', 'nir_lower_direct_array_deref_of_vec_load', - 'nir_lower_direct_array_deref_of_vec_store', - 'nir_lower_discard_if', 'nir_lower_discard_if_options', - 'nir_lower_discard_if_options__enumvalues', 'nir_lower_divmod64', - 'nir_lower_dminmax', 'nir_lower_dmod', 'nir_lower_doubles', - 'nir_lower_doubles_op_to_options_mask', - 'nir_lower_doubles_options', - 'nir_lower_doubles_options__enumvalues', 'nir_lower_drawpixels', - 'nir_lower_drawpixels_options', 'nir_lower_drcp', - 'nir_lower_dround_even', 'nir_lower_drsq', 'nir_lower_dsat', - 'nir_lower_dsign', 'nir_lower_dsqrt', 'nir_lower_dsub', - 'nir_lower_dtrunc', 'nir_lower_explicit_io', - 'nir_lower_explicit_io_instr', 'nir_lower_extract64', - 'nir_lower_fb_read', 'nir_lower_find_lsb64', - 'nir_lower_flatshade', 'nir_lower_flrp', 'nir_lower_fp16_all', - 'nir_lower_fp16_cast_options', - 'nir_lower_fp16_cast_options__enumvalues', 'nir_lower_fp16_casts', - 'nir_lower_fp16_rd', 'nir_lower_fp16_rtne', 'nir_lower_fp16_rtz', - 'nir_lower_fp16_ru', 'nir_lower_fp16_split_fp64', - 'nir_lower_fp64_full_software', - 'nir_lower_frag_coord_to_pixel_coord', 'nir_lower_fragcolor', - 'nir_lower_fragcoord_wtrans', 'nir_lower_frexp', - 'nir_lower_global_vars_to_local', 'nir_lower_goto_ifs', - 'nir_lower_gs_intrinsics', - 'nir_lower_gs_intrinsics_count_primitives', - 'nir_lower_gs_intrinsics_count_vertices_per_primitive', - 'nir_lower_gs_intrinsics_flags', - 'nir_lower_gs_intrinsics_flags__enumvalues', - 'nir_lower_gs_intrinsics_overwrite_incomplete', - 'nir_lower_gs_intrinsics_per_stream', 'nir_lower_halt_to_return', - 'nir_lower_helper_writes', 'nir_lower_iabs64', - 'nir_lower_iadd3_64', 'nir_lower_iadd64', 'nir_lower_iadd_sat64', - 'nir_lower_icmp64', 'nir_lower_idiv', 'nir_lower_idiv_options', - 'nir_lower_image', 'nir_lower_image_atomics_to_global', - 'nir_lower_image_options', 'nir_lower_imul64', - 'nir_lower_imul_2x32_64', 'nir_lower_imul_high64', - 'nir_lower_indirect_array_deref_of_vec_load', - 'nir_lower_indirect_array_deref_of_vec_store', - 'nir_lower_indirect_derefs', 'nir_lower_indirect_var_derefs', - 'nir_lower_ineg64', 'nir_lower_input_attachments', - 'nir_lower_instr_cb', 'nir_lower_int64', - 'nir_lower_int64_float_conversions', - 'nir_lower_int64_op_to_options_mask', 'nir_lower_int64_options', - 'nir_lower_int64_options__enumvalues', 'nir_lower_int_to_float', - 'nir_lower_interpolation', 'nir_lower_interpolation_at_offset', - 'nir_lower_interpolation_at_sample', - 'nir_lower_interpolation_centroid', - 'nir_lower_interpolation_options', - 'nir_lower_interpolation_options__enumvalues', - 'nir_lower_interpolation_pixel', 'nir_lower_interpolation_sample', - 'nir_lower_io', 'nir_lower_io_array_vars_to_elements', - 'nir_lower_io_array_vars_to_elements_no_indirects', - 'nir_lower_io_indirect_loads', - 'nir_lower_io_lower_64bit_float_to_32', - 'nir_lower_io_lower_64bit_to_32', - 'nir_lower_io_lower_64bit_to_32_new', 'nir_lower_io_options', - 'nir_lower_io_options__enumvalues', 'nir_lower_io_passes', - 'nir_lower_io_to_scalar', - 'nir_lower_io_use_interpolated_input_intrinsics', - 'nir_lower_io_vars_to_scalar', 'nir_lower_io_vars_to_temporaries', - 'nir_lower_is_helper_invocation', 'nir_lower_isign64', - 'nir_lower_load_const_to_scalar', 'nir_lower_locals_to_regs', - 'nir_lower_logic64', 'nir_lower_mediump_io', - 'nir_lower_mediump_vars', 'nir_lower_mem_access_bit_sizes', - 'nir_lower_mem_access_bit_sizes_cb', - 'nir_lower_mem_access_bit_sizes_options', 'nir_lower_memcpy', - 'nir_lower_memory_model', 'nir_lower_minmax64', - 'nir_lower_multiview', 'nir_lower_multiview_options', - 'nir_lower_non_uniform_access', - 'nir_lower_non_uniform_access_callback', - 'nir_lower_non_uniform_access_options', - 'nir_lower_non_uniform_access_type', - 'nir_lower_non_uniform_access_type_count', - 'nir_lower_non_uniform_get_ssbo_size', - 'nir_lower_non_uniform_image_access', - 'nir_lower_non_uniform_src_access_callback', - 'nir_lower_non_uniform_ssbo_access', - 'nir_lower_non_uniform_texture_access', - 'nir_lower_non_uniform_texture_offset_access', - 'nir_lower_non_uniform_ubo_access', 'nir_lower_pack', - 'nir_lower_packing_num_ops', 'nir_lower_packing_op', - 'nir_lower_packing_op__enumvalues', - 'nir_lower_packing_op_pack_32_2x16', - 'nir_lower_packing_op_pack_32_4x8', - 'nir_lower_packing_op_pack_64_2x32', - 'nir_lower_packing_op_pack_64_4x16', - 'nir_lower_packing_op_unpack_32_2x16', - 'nir_lower_packing_op_unpack_32_4x8', - 'nir_lower_packing_op_unpack_64_2x32', - 'nir_lower_packing_op_unpack_64_4x16', - 'nir_lower_passthrough_edgeflags', 'nir_lower_patch_vertices', - 'nir_lower_phis_to_regs_block', 'nir_lower_phis_to_scalar', - 'nir_lower_pntc_ytransform', 'nir_lower_point_size', - 'nir_lower_point_size_mov', 'nir_lower_point_smooth', - 'nir_lower_poly_line_smooth', 'nir_lower_printf', - 'nir_lower_printf_buffer', 'nir_lower_printf_options', - 'nir_lower_read_invocation_to_scalar', - 'nir_lower_readonly_images_to_tex', - 'nir_lower_reg_intrinsics_to_ssa', - 'nir_lower_reg_intrinsics_to_ssa_impl', 'nir_lower_returns', - 'nir_lower_returns_impl', 'nir_lower_robust_access', - 'nir_lower_samplers', 'nir_lower_scan_reduce_bitwise64', - 'nir_lower_scan_reduce_iadd64', 'nir_lower_scratch_to_var', - 'nir_lower_shader_calls', 'nir_lower_shader_calls_options', - 'nir_lower_shader_calls_should_remat_func', 'nir_lower_shift64', - 'nir_lower_single_sampled', 'nir_lower_ssa_defs_to_regs_block', - 'nir_lower_ssbo', 'nir_lower_ssbo_options', - 'nir_lower_subgroup_shuffle64', 'nir_lower_subgroups', - 'nir_lower_subgroups_options', 'nir_lower_system_values', - 'nir_lower_sysvals_to_varyings', - 'nir_lower_sysvals_to_varyings_options', 'nir_lower_task_shader', - 'nir_lower_task_shader_options', 'nir_lower_terminate_if_to_cf', - 'nir_lower_terminate_to_demote', 'nir_lower_tess_coord_z', - 'nir_lower_tess_level_array_vars_to_vec', 'nir_lower_tex', - 'nir_lower_tex_options', 'nir_lower_tex_packing', - 'nir_lower_tex_packing_16', 'nir_lower_tex_packing_8', - 'nir_lower_tex_packing_none', 'nir_lower_tex_shadow', - 'nir_lower_tex_shadow_swizzle', 'nir_lower_texcoord_replace', - 'nir_lower_texcoord_replace_late', 'nir_lower_two_sided_color', - 'nir_lower_uadd_sat64', 'nir_lower_ubo_vec4', - 'nir_lower_ufind_msb64', 'nir_lower_undef_to_zero', - 'nir_lower_uniforms_to_ubo', 'nir_lower_usub_sat64', - 'nir_lower_var_copies', 'nir_lower_var_copy_instr', - 'nir_lower_variable_initializers', - 'nir_lower_vars_to_explicit_types', 'nir_lower_vars_to_scratch', - 'nir_lower_vars_to_ssa', 'nir_lower_vec3_to_vec4', - 'nir_lower_vec_to_regs', 'nir_lower_view_index_to_device_index', - 'nir_lower_viewport_transform', 'nir_lower_vote_ieq64', - 'nir_lower_wpos_center', 'nir_lower_wpos_ytransform', - 'nir_lower_wpos_ytransform_options', 'nir_lower_wrmasks', - 'nir_mask', 'nir_mem_access_shift_method', - 'nir_mem_access_shift_method__enumvalues', - 'nir_mem_access_shift_method_bytealign_amd', - 'nir_mem_access_shift_method_scalar', - 'nir_mem_access_shift_method_shift64', - 'nir_mem_access_size_align', 'nir_memcpy_deref', - 'nir_memcpy_deref_with_access', 'nir_memory_semantics', - 'nir_memory_semantics__enumvalues', 'nir_metadata', - 'nir_metadata__enumvalues', 'nir_metadata_all', - 'nir_metadata_block_index', 'nir_metadata_check_validation_flag', - 'nir_metadata_control_flow', 'nir_metadata_divergence', - 'nir_metadata_dominance', 'nir_metadata_instr_index', - 'nir_metadata_invalidate', 'nir_metadata_live_defs', - 'nir_metadata_loop_analysis', 'nir_metadata_none', - 'nir_metadata_not_properly_reset', 'nir_metadata_require', - 'nir_metadata_require_all', 'nir_metadata_set_validation_flag', - 'nir_minimize_call_live_states', 'nir_mod_analysis', - 'nir_mov_alu', 'nir_move_alu', 'nir_move_comparisons', - 'nir_move_const_undef', 'nir_move_copies', 'nir_move_load_input', - 'nir_move_load_ssbo', 'nir_move_load_ubo', - 'nir_move_load_uniform', 'nir_move_options', - 'nir_move_options__enumvalues', 'nir_move_output_stores_to_end', - 'nir_move_terminate_out_of_loops', 'nir_move_to_entry_block_only', - 'nir_move_to_top_input_loads', 'nir_move_to_top_load_smem_amd', - 'nir_move_vec_src_uses_to_dest', 'nir_next_decl_reg', - 'nir_next_phi', 'nir_no_progress', 'nir_normalize_cubemap_coords', - 'nir_num_intrinsics', 'nir_num_opcodes', 'nir_num_tex_src_types', - 'nir_num_variable_modes', 'nir_op', 'nir_op__enumvalues', - 'nir_op_algebraic_property', - 'nir_op_algebraic_property__enumvalues', 'nir_op_alignbyte_amd', - 'nir_op_amul', 'nir_op_andg_ir3', 'nir_op_b16all_fequal16', - 'nir_op_b16all_fequal2', 'nir_op_b16all_fequal3', - 'nir_op_b16all_fequal4', 'nir_op_b16all_fequal5', - 'nir_op_b16all_fequal8', 'nir_op_b16all_iequal16', - 'nir_op_b16all_iequal2', 'nir_op_b16all_iequal3', - 'nir_op_b16all_iequal4', 'nir_op_b16all_iequal5', - 'nir_op_b16all_iequal8', 'nir_op_b16any_fnequal16', - 'nir_op_b16any_fnequal2', 'nir_op_b16any_fnequal3', - 'nir_op_b16any_fnequal4', 'nir_op_b16any_fnequal5', - 'nir_op_b16any_fnequal8', 'nir_op_b16any_inequal16', - 'nir_op_b16any_inequal2', 'nir_op_b16any_inequal3', - 'nir_op_b16any_inequal4', 'nir_op_b16any_inequal5', - 'nir_op_b16any_inequal8', 'nir_op_b16csel', 'nir_op_b2b1', - 'nir_op_b2b16', 'nir_op_b2b32', 'nir_op_b2b8', 'nir_op_b2f16', - 'nir_op_b2f32', 'nir_op_b2f64', 'nir_op_b2i1', 'nir_op_b2i16', - 'nir_op_b2i32', 'nir_op_b2i64', 'nir_op_b2i8', - 'nir_op_b32all_fequal16', 'nir_op_b32all_fequal2', - 'nir_op_b32all_fequal3', 'nir_op_b32all_fequal4', - 'nir_op_b32all_fequal5', 'nir_op_b32all_fequal8', - 'nir_op_b32all_iequal16', 'nir_op_b32all_iequal2', - 'nir_op_b32all_iequal3', 'nir_op_b32all_iequal4', - 'nir_op_b32all_iequal5', 'nir_op_b32all_iequal8', - 'nir_op_b32any_fnequal16', 'nir_op_b32any_fnequal2', - 'nir_op_b32any_fnequal3', 'nir_op_b32any_fnequal4', - 'nir_op_b32any_fnequal5', 'nir_op_b32any_fnequal8', - 'nir_op_b32any_inequal16', 'nir_op_b32any_inequal2', - 'nir_op_b32any_inequal3', 'nir_op_b32any_inequal4', - 'nir_op_b32any_inequal5', 'nir_op_b32any_inequal8', - 'nir_op_b32csel', 'nir_op_b32fcsel_mdg', 'nir_op_b8all_fequal16', - 'nir_op_b8all_fequal2', 'nir_op_b8all_fequal3', - 'nir_op_b8all_fequal4', 'nir_op_b8all_fequal5', - 'nir_op_b8all_fequal8', 'nir_op_b8all_iequal16', - 'nir_op_b8all_iequal2', 'nir_op_b8all_iequal3', - 'nir_op_b8all_iequal4', 'nir_op_b8all_iequal5', - 'nir_op_b8all_iequal8', 'nir_op_b8any_fnequal16', - 'nir_op_b8any_fnequal2', 'nir_op_b8any_fnequal3', - 'nir_op_b8any_fnequal4', 'nir_op_b8any_fnequal5', - 'nir_op_b8any_fnequal8', 'nir_op_b8any_inequal16', - 'nir_op_b8any_inequal2', 'nir_op_b8any_inequal3', - 'nir_op_b8any_inequal4', 'nir_op_b8any_inequal5', - 'nir_op_b8any_inequal8', 'nir_op_b8csel', 'nir_op_ball_fequal16', - 'nir_op_ball_fequal2', 'nir_op_ball_fequal3', - 'nir_op_ball_fequal4', 'nir_op_ball_fequal5', - 'nir_op_ball_fequal8', 'nir_op_ball_iequal16', - 'nir_op_ball_iequal2', 'nir_op_ball_iequal3', - 'nir_op_ball_iequal4', 'nir_op_ball_iequal5', - 'nir_op_ball_iequal8', 'nir_op_bany_fnequal16', - 'nir_op_bany_fnequal2', 'nir_op_bany_fnequal3', - 'nir_op_bany_fnequal4', 'nir_op_bany_fnequal5', - 'nir_op_bany_fnequal8', 'nir_op_bany_inequal16', - 'nir_op_bany_inequal2', 'nir_op_bany_inequal3', - 'nir_op_bany_inequal4', 'nir_op_bany_inequal5', - 'nir_op_bany_inequal8', 'nir_op_bcsel', 'nir_op_bf2f', - 'nir_op_bfdot16', 'nir_op_bfdot2', 'nir_op_bfdot2_bfadd', - 'nir_op_bfdot3', 'nir_op_bfdot4', 'nir_op_bfdot5', - 'nir_op_bfdot8', 'nir_op_bffma', 'nir_op_bfi', 'nir_op_bfm', - 'nir_op_bfmul', 'nir_op_bit_count', 'nir_op_bitfield_insert', - 'nir_op_bitfield_reverse', 'nir_op_bitfield_select', - 'nir_op_bitnz', 'nir_op_bitnz16', 'nir_op_bitnz32', - 'nir_op_bitnz8', 'nir_op_bitz', 'nir_op_bitz16', 'nir_op_bitz32', - 'nir_op_bitz8', 'nir_op_bounds_agx', 'nir_op_byte_perm_amd', - 'nir_op_cube_amd', 'nir_op_e4m3fn2f', 'nir_op_e5m22f', - 'nir_op_extr_agx', 'nir_op_extract_i16', 'nir_op_extract_i8', - 'nir_op_extract_u16', 'nir_op_extract_u8', 'nir_op_f2bf', - 'nir_op_f2e4m3fn', 'nir_op_f2e4m3fn_sat', 'nir_op_f2e4m3fn_satfn', - 'nir_op_f2e5m2', 'nir_op_f2e5m2_sat', 'nir_op_f2f16', - 'nir_op_f2f16_rtne', 'nir_op_f2f16_rtz', 'nir_op_f2f32', - 'nir_op_f2f64', 'nir_op_f2fmp', 'nir_op_f2i1', 'nir_op_f2i16', - 'nir_op_f2i32', 'nir_op_f2i64', 'nir_op_f2i8', 'nir_op_f2imp', - 'nir_op_f2snorm_16_v3d', 'nir_op_f2u1', 'nir_op_f2u16', - 'nir_op_f2u32', 'nir_op_f2u64', 'nir_op_f2u8', 'nir_op_f2ump', - 'nir_op_f2unorm_16_v3d', 'nir_op_fabs', 'nir_op_fadd', - 'nir_op_fall_equal16', 'nir_op_fall_equal2', 'nir_op_fall_equal3', - 'nir_op_fall_equal4', 'nir_op_fall_equal5', 'nir_op_fall_equal8', - 'nir_op_fany_nequal16', 'nir_op_fany_nequal2', - 'nir_op_fany_nequal3', 'nir_op_fany_nequal4', - 'nir_op_fany_nequal5', 'nir_op_fany_nequal8', 'nir_op_fceil', - 'nir_op_fclamp_pos', 'nir_op_fcos', 'nir_op_fcos_amd', - 'nir_op_fcos_mdg', 'nir_op_fcsel', 'nir_op_fcsel_ge', - 'nir_op_fcsel_gt', 'nir_op_fdiv', 'nir_op_fdot16', - 'nir_op_fdot16_replicated', 'nir_op_fdot2', - 'nir_op_fdot2_replicated', 'nir_op_fdot3', - 'nir_op_fdot3_replicated', 'nir_op_fdot4', - 'nir_op_fdot4_replicated', 'nir_op_fdot5', - 'nir_op_fdot5_replicated', 'nir_op_fdot8', - 'nir_op_fdot8_replicated', 'nir_op_fdph', - 'nir_op_fdph_replicated', 'nir_op_feq', 'nir_op_feq16', - 'nir_op_feq32', 'nir_op_feq8', 'nir_op_fequ', 'nir_op_fequ16', - 'nir_op_fequ32', 'nir_op_fequ8', 'nir_op_fexp2', 'nir_op_ffloor', - 'nir_op_ffma', 'nir_op_ffmaz', 'nir_op_ffract', 'nir_op_fge', - 'nir_op_fge16', 'nir_op_fge32', 'nir_op_fge8', 'nir_op_fgeu', - 'nir_op_fgeu16', 'nir_op_fgeu32', 'nir_op_fgeu8', - 'nir_op_find_lsb', 'nir_op_fisfinite', 'nir_op_fisfinite32', - 'nir_op_fisnormal', 'nir_op_flog2', 'nir_op_flrp', 'nir_op_flt', - 'nir_op_flt16', 'nir_op_flt32', 'nir_op_flt8', 'nir_op_fltu', - 'nir_op_fltu16', 'nir_op_fltu32', 'nir_op_fltu8', 'nir_op_fmax', - 'nir_op_fmax_agx', 'nir_op_fmin', 'nir_op_fmin_agx', - 'nir_op_fmod', 'nir_op_fmul', 'nir_op_fmulz', 'nir_op_fneg', - 'nir_op_fneo', 'nir_op_fneo16', 'nir_op_fneo32', 'nir_op_fneo8', - 'nir_op_fneu', 'nir_op_fneu16', 'nir_op_fneu32', 'nir_op_fneu8', - 'nir_op_ford', 'nir_op_ford16', 'nir_op_ford32', 'nir_op_ford8', - 'nir_op_fpow', 'nir_op_fquantize2f16', 'nir_op_frcp', - 'nir_op_frem', 'nir_op_frexp_exp', 'nir_op_frexp_sig', - 'nir_op_fround_even', 'nir_op_frsq', 'nir_op_fsat', - 'nir_op_fsat_signed', 'nir_op_fsign', 'nir_op_fsin', - 'nir_op_fsin_agx', 'nir_op_fsin_amd', 'nir_op_fsin_mdg', - 'nir_op_fsqrt', 'nir_op_fsub', 'nir_op_fsum2', 'nir_op_fsum3', - 'nir_op_fsum4', 'nir_op_ftrunc', 'nir_op_funord', - 'nir_op_funord16', 'nir_op_funord32', 'nir_op_funord8', - 'nir_op_i2f16', 'nir_op_i2f32', 'nir_op_i2f64', 'nir_op_i2fmp', - 'nir_op_i2i1', 'nir_op_i2i16', 'nir_op_i2i32', 'nir_op_i2i64', - 'nir_op_i2i8', 'nir_op_i2imp', 'nir_op_i32csel_ge', - 'nir_op_i32csel_gt', 'nir_op_iabs', 'nir_op_iadd', 'nir_op_iadd3', - 'nir_op_iadd_sat', 'nir_op_iand', 'nir_op_ibfe', - 'nir_op_ibitfield_extract', 'nir_op_icsel_eqz', 'nir_op_idiv', - 'nir_op_ieq', 'nir_op_ieq16', 'nir_op_ieq32', 'nir_op_ieq8', - 'nir_op_ifind_msb', 'nir_op_ifind_msb_rev', 'nir_op_ige', - 'nir_op_ige16', 'nir_op_ige32', 'nir_op_ige8', 'nir_op_ihadd', - 'nir_op_ilea_agx', 'nir_op_ilt', 'nir_op_ilt16', 'nir_op_ilt32', - 'nir_op_ilt8', 'nir_op_imad', 'nir_op_imad24_ir3', - 'nir_op_imadsh_mix16', 'nir_op_imadshl_agx', 'nir_op_imax', - 'nir_op_imin', 'nir_op_imod', 'nir_op_imsubshl_agx', - 'nir_op_imul', 'nir_op_imul24', 'nir_op_imul24_relaxed', - 'nir_op_imul_2x32_64', 'nir_op_imul_32x16', 'nir_op_imul_high', - 'nir_op_ine', 'nir_op_ine16', 'nir_op_ine32', 'nir_op_ine8', - 'nir_op_ineg', 'nir_op_info', 'nir_op_infos', 'nir_op_inot', - 'nir_op_insert_u16', 'nir_op_insert_u8', 'nir_op_interleave_agx', - 'nir_op_ior', 'nir_op_irem', 'nir_op_irhadd', - 'nir_op_is_selection', 'nir_op_is_vec', 'nir_op_is_vec_or_mov', - 'nir_op_ishl', 'nir_op_ishr', 'nir_op_isign', 'nir_op_isub', - 'nir_op_isub_sat', 'nir_op_ixor', 'nir_op_ldexp', - 'nir_op_ldexp16_pan', 'nir_op_lea_nv', 'nir_op_mov', - 'nir_op_mqsad_4x8', 'nir_op_msad_4x8', - 'nir_op_pack_2x16_to_snorm_2x8_v3d', - 'nir_op_pack_2x16_to_unorm_10_2_v3d', - 'nir_op_pack_2x16_to_unorm_2x10_v3d', - 'nir_op_pack_2x16_to_unorm_2x8_v3d', - 'nir_op_pack_2x32_to_2x16_v3d', 'nir_op_pack_32_2x16', - 'nir_op_pack_32_2x16_split', 'nir_op_pack_32_4x8', - 'nir_op_pack_32_4x8_split', 'nir_op_pack_32_to_r11g11b10_v3d', - 'nir_op_pack_4x16_to_4x8_v3d', 'nir_op_pack_64_2x32', - 'nir_op_pack_64_2x32_split', 'nir_op_pack_64_4x16', - 'nir_op_pack_double_2x32_dxil', 'nir_op_pack_half_2x16', - 'nir_op_pack_half_2x16_rtz_split', 'nir_op_pack_half_2x16_split', - 'nir_op_pack_sint_2x16', 'nir_op_pack_snorm_2x16', - 'nir_op_pack_snorm_4x8', 'nir_op_pack_uint_2x16', - 'nir_op_pack_uint_32_to_r10g10b10a2_v3d', - 'nir_op_pack_unorm_2x16', 'nir_op_pack_unorm_4x8', - 'nir_op_pack_uvec2_to_uint', 'nir_op_pack_uvec4_to_uint', - 'nir_op_prmt_nv', 'nir_op_sdot_2x16_iadd', - 'nir_op_sdot_2x16_iadd_sat', 'nir_op_sdot_4x8_iadd', - 'nir_op_sdot_4x8_iadd_sat', 'nir_op_seq', 'nir_op_sge', - 'nir_op_shfr', 'nir_op_shlg_ir3', 'nir_op_shlm_ir3', - 'nir_op_shrg_ir3', 'nir_op_shrm_ir3', 'nir_op_slt', 'nir_op_sne', - 'nir_op_sudot_4x8_iadd', 'nir_op_sudot_4x8_iadd_sat', - 'nir_op_u2f16', 'nir_op_u2f32', 'nir_op_u2f64', 'nir_op_u2fmp', - 'nir_op_u2u1', 'nir_op_u2u16', 'nir_op_u2u32', 'nir_op_u2u64', - 'nir_op_u2u8', 'nir_op_uabs_isub', 'nir_op_uabs_usub', - 'nir_op_uadd_carry', 'nir_op_uadd_sat', 'nir_op_ubfe', - 'nir_op_ubitfield_extract', 'nir_op_uclz', 'nir_op_udiv', - 'nir_op_udiv_aligned_4', 'nir_op_udot_2x16_uadd', - 'nir_op_udot_2x16_uadd_sat', 'nir_op_udot_4x8_uadd', - 'nir_op_udot_4x8_uadd_sat', 'nir_op_ufind_msb', - 'nir_op_ufind_msb_rev', 'nir_op_uge', 'nir_op_uge16', - 'nir_op_uge32', 'nir_op_uge8', 'nir_op_uhadd', 'nir_op_ulea_agx', - 'nir_op_ult', 'nir_op_ult16', 'nir_op_ult32', 'nir_op_ult8', - 'nir_op_umad24', 'nir_op_umad24_relaxed', 'nir_op_umax', - 'nir_op_umax_4x8_vc4', 'nir_op_umin', 'nir_op_umin_4x8_vc4', - 'nir_op_umod', 'nir_op_umul24', 'nir_op_umul24_relaxed', - 'nir_op_umul_2x32_64', 'nir_op_umul_32x16', 'nir_op_umul_high', - 'nir_op_umul_low', 'nir_op_umul_unorm_4x8_vc4', - 'nir_op_unpack_32_2x16', 'nir_op_unpack_32_2x16_split_x', - 'nir_op_unpack_32_2x16_split_y', 'nir_op_unpack_32_4x8', - 'nir_op_unpack_64_2x32', 'nir_op_unpack_64_2x32_split_x', - 'nir_op_unpack_64_2x32_split_y', 'nir_op_unpack_64_4x16', - 'nir_op_unpack_double_2x32_dxil', 'nir_op_unpack_half_2x16', - 'nir_op_unpack_half_2x16_split_x', - 'nir_op_unpack_half_2x16_split_y', 'nir_op_unpack_snorm_2x16', - 'nir_op_unpack_snorm_4x8', 'nir_op_unpack_unorm_2x16', - 'nir_op_unpack_unorm_4x8', 'nir_op_urhadd', 'nir_op_urol', - 'nir_op_uror', 'nir_op_usadd_4x8_vc4', 'nir_op_ushr', - 'nir_op_ussub_4x8_vc4', 'nir_op_usub_borrow', 'nir_op_usub_sat', - 'nir_op_vec', 'nir_op_vec16', 'nir_op_vec2', 'nir_op_vec3', - 'nir_op_vec4', 'nir_op_vec5', 'nir_op_vec8', - 'nir_opt_16bit_tex_image', 'nir_opt_16bit_tex_image_options', - 'nir_opt_access', 'nir_opt_access_options', - 'nir_opt_acquire_release_barriers', 'nir_opt_algebraic', - 'nir_opt_algebraic_before_ffma', - 'nir_opt_algebraic_before_lower_int64', - 'nir_opt_algebraic_distribute_src_mods', - 'nir_opt_algebraic_integer_promotion', 'nir_opt_algebraic_late', - 'nir_opt_barrier_modes', 'nir_opt_clip_cull_const', - 'nir_opt_combine_barriers', 'nir_opt_combine_stores', - 'nir_opt_comparison_pre', 'nir_opt_comparison_pre_impl', - 'nir_opt_constant_folding', 'nir_opt_copy_prop_vars', - 'nir_opt_cse', 'nir_opt_dce', 'nir_opt_dead_cf', - 'nir_opt_dead_write_vars', 'nir_opt_deref', 'nir_opt_deref_impl', - 'nir_opt_find_array_copies', 'nir_opt_frag_coord_to_pixel_coord', - 'nir_opt_fragdepth', 'nir_opt_gcm', 'nir_opt_generate_bfi', - 'nir_opt_idiv_const', 'nir_opt_if', 'nir_opt_if_avoid_64bit_phis', - 'nir_opt_if_optimize_phi_true_false', 'nir_opt_if_options', - 'nir_opt_if_options__enumvalues', 'nir_opt_intrinsics', - 'nir_opt_large_constants', 'nir_opt_licm', - 'nir_opt_load_store_update_alignments', - 'nir_opt_load_store_vectorize', 'nir_opt_loop', - 'nir_opt_loop_unroll', 'nir_opt_memcpy', 'nir_opt_move', - 'nir_opt_move_discards_to_top', 'nir_opt_move_to_top', - 'nir_opt_move_to_top_options', - 'nir_opt_move_to_top_options__enumvalues', 'nir_opt_mqsad', - 'nir_opt_non_uniform_access', 'nir_opt_offsets', - 'nir_opt_offsets_options', 'nir_opt_peephole_select', - 'nir_opt_peephole_select_options', 'nir_opt_phi_precision', - 'nir_opt_phi_to_bool', 'nir_opt_preamble', - 'nir_opt_preamble_options', 'nir_opt_ray_queries', - 'nir_opt_ray_query_ranges', 'nir_opt_reassociate_bfi', - 'nir_opt_reassociate_matrix_mul', - 'nir_opt_rematerialize_compares', 'nir_opt_remove_phis', - 'nir_opt_shrink_stores', 'nir_opt_shrink_vectors', - 'nir_opt_simplify_convert_alu_types', 'nir_opt_sink', - 'nir_opt_tex_skip_helpers', 'nir_opt_tex_srcs_options', - 'nir_opt_undef', 'nir_opt_uniform_atomics', - 'nir_opt_uniform_subgroup', 'nir_opt_varyings', - 'nir_opt_varyings_progress', - 'nir_opt_varyings_progress__enumvalues', 'nir_opt_vectorize', - 'nir_opt_vectorize_io', 'nir_opt_vectorize_io_vars', - 'nir_output_clipper_var_groups', 'nir_output_deps', - 'nir_pack_bits', 'nir_pad_vec4', 'nir_pad_vector', - 'nir_pad_vector_imm_int', 'nir_parallel_copy_entry', - 'nir_parallel_copy_instr', 'nir_parallel_copy_instr_create', - 'nir_parameter', 'nir_phi_get_src_from_block', 'nir_phi_instr', - 'nir_phi_instr_add_src', 'nir_phi_instr_create', - 'nir_phi_pass_cb', 'nir_phi_src', 'nir_pop_if', 'nir_pop_loop', - 'nir_preamble_class', 'nir_preamble_class__enumvalues', - 'nir_preamble_class_general', 'nir_preamble_class_image', - 'nir_preamble_num_classes', 'nir_print_deref', - 'nir_print_function_body', 'nir_print_input_to_output_deps', - 'nir_print_instr', 'nir_print_shader', - 'nir_print_shader_annotated', 'nir_print_use_dominators', - 'nir_printf_fmt', 'nir_printf_fmt_at_px', - 'nir_process_debug_variable', 'nir_progress', - 'nir_progress_consumer', 'nir_progress_producer', - 'nir_propagate_invariant', 'nir_push_continue', 'nir_push_else', - 'nir_push_if', 'nir_push_loop', 'nir_ray_query_value', - 'nir_ray_query_value__enumvalues', 'nir_ray_query_value_flags', - 'nir_ray_query_value_intersection_barycentrics', - 'nir_ray_query_value_intersection_candidate_aabb_opaque', - 'nir_ray_query_value_intersection_front_face', - 'nir_ray_query_value_intersection_geometry_index', - 'nir_ray_query_value_intersection_instance_custom_index', - 'nir_ray_query_value_intersection_instance_id', - 'nir_ray_query_value_intersection_instance_sbt_index', - 'nir_ray_query_value_intersection_object_ray_direction', - 'nir_ray_query_value_intersection_object_ray_origin', - 'nir_ray_query_value_intersection_object_to_world', - 'nir_ray_query_value_intersection_primitive_index', - 'nir_ray_query_value_intersection_t', - 'nir_ray_query_value_intersection_triangle_vertex_positions', - 'nir_ray_query_value_intersection_type', - 'nir_ray_query_value_intersection_world_to_object', - 'nir_ray_query_value_tmin', - 'nir_ray_query_value_world_ray_direction', - 'nir_ray_query_value_world_ray_origin', 'nir_recompute_io_bases', - 'nir_reg_get_decl', 'nir_rematerialize_deref_in_use_blocks', - 'nir_rematerialize_derefs_in_use_blocks_impl', - 'nir_remove_dead_derefs', 'nir_remove_dead_derefs_impl', - 'nir_remove_dead_variables', 'nir_remove_dead_variables_options', - 'nir_remove_entrypoints', 'nir_remove_non_entrypoints', - 'nir_remove_non_exported', 'nir_remove_single_src_phis_block', - 'nir_remove_sysval_output', 'nir_remove_tex_shadow', - 'nir_remove_unused_io_vars', 'nir_remove_unused_varyings', - 'nir_remove_varying', 'nir_repair_ssa', 'nir_repair_ssa_impl', - 'nir_replicate', 'nir_resize_vector', 'nir_resource_data_intel', - 'nir_resource_data_intel__enumvalues', - 'nir_resource_intel_bindless', 'nir_resource_intel_non_uniform', - 'nir_resource_intel_pushable', 'nir_resource_intel_sampler', - 'nir_resource_intel_sampler_embedded', - 'nir_rewrite_image_intrinsic', 'nir_rewrite_uses_to_load_reg', - 'nir_round_down_components', 'nir_round_up_components', - 'nir_rounding_mode', 'nir_rounding_mode__enumvalues', - 'nir_rounding_mode_rd', 'nir_rounding_mode_rtne', - 'nir_rounding_mode_rtz', 'nir_rounding_mode_ru', - 'nir_rounding_mode_undef', 'nir_samples_identical_deref', - 'nir_scalar', 'nir_scalar_alu_op', 'nir_scalar_as_bool', - 'nir_scalar_as_const_value', 'nir_scalar_as_float', - 'nir_scalar_as_int', 'nir_scalar_as_uint', - 'nir_scalar_chase_alu_src', 'nir_scalar_chase_movs', - 'nir_scalar_equal', 'nir_scalar_intrinsic_op', - 'nir_scalar_is_alu', 'nir_scalar_is_const', - 'nir_scalar_is_intrinsic', 'nir_scalar_is_undef', - 'nir_scalar_resolved', 'nir_scale_fdiv', - 'nir_scoped_memory_barrier', 'nir_select_from_ssa_def_array', - 'nir_selection_control', 'nir_selection_control__enumvalues', - 'nir_selection_control_divergent_always_taken', - 'nir_selection_control_dont_flatten', - 'nir_selection_control_flatten', 'nir_selection_control_none', - 'nir_serialize', 'nir_serialize_function', 'nir_shader', - 'nir_shader_add_variable', 'nir_shader_alu_pass', - 'nir_shader_as_str', 'nir_shader_as_str_annotated', - 'nir_shader_clear_pass_flags', 'nir_shader_clone', - 'nir_shader_compiler_options', 'nir_shader_create', - 'nir_shader_gather_debug_info', 'nir_shader_gather_info', - 'nir_shader_get_entrypoint', 'nir_shader_get_function_for_name', - 'nir_shader_get_preamble', 'nir_shader_index_vars', - 'nir_shader_instructions_pass', 'nir_shader_intrinsics_pass', - 'nir_shader_lower_instructions', 'nir_shader_phi_pass', - 'nir_shader_preserve_all_metadata', 'nir_shader_replace', - 'nir_shader_serialize_deserialize', - 'nir_shader_supports_implicit_lod', 'nir_shader_tex_pass', - 'nir_shader_uses_view_index', 'nir_shift_channels', - 'nir_should_vectorize_mem_func', 'nir_shrink_vec_array_vars', - 'nir_slot_is_sysval_output', - 'nir_slot_is_sysval_output_and_varying', 'nir_slot_is_varying', - 'nir_sort_unstructured_blocks', 'nir_sort_variables_by_location', - 'nir_sort_variables_with_modes', 'nir_split_64bit_vec3_and_vec4', - 'nir_split_array_vars', 'nir_split_conversions', - 'nir_split_conversions_options', 'nir_split_per_member_structs', - 'nir_split_struct_vars', 'nir_split_var_copies', 'nir_src', - 'nir_src_as_alu_instr', 'nir_src_as_bool', - 'nir_src_as_const_value', 'nir_src_as_deref', 'nir_src_as_float', - 'nir_src_as_int', 'nir_src_as_intrinsic', 'nir_src_as_string', - 'nir_src_as_uint', 'nir_src_bit_size', 'nir_src_comp_as_bool', - 'nir_src_comp_as_float', 'nir_src_comp_as_int', - 'nir_src_comp_as_uint', 'nir_src_components_read', - 'nir_src_for_ssa', 'nir_src_get_block', 'nir_src_init', - 'nir_src_is_always_uniform', 'nir_src_is_const', - 'nir_src_is_divergent', 'nir_src_is_if', 'nir_src_is_undef', - 'nir_src_num_components', 'nir_src_parent_if', - 'nir_src_parent_instr', 'nir_src_rewrite', - 'nir_src_set_parent_if', 'nir_src_set_parent_instr', - 'nir_srcs_equal', 'nir_ssa_alu_instr_src_components', - 'nir_ssa_for_alu_src', 'nir_start_block', 'nir_state_slot', - 'nir_state_variable_create', 'nir_static_workgroup_size', - 'nir_steal_tex_deref', 'nir_steal_tex_src', 'nir_store_array_var', - 'nir_store_array_var_imm', 'nir_store_deref', - 'nir_store_deref_with_access', 'nir_store_global', - 'nir_store_reg', 'nir_store_reg_for_def', 'nir_store_var', - 'nir_sweep', 'nir_swizzle', 'nir_system_value_from_intrinsic', - 'nir_test_mask', 'nir_tex_deref', 'nir_tex_instr', - 'nir_tex_instr_add_src', 'nir_tex_instr_create', - 'nir_tex_instr_dest_size', - 'nir_tex_instr_has_explicit_tg4_offsets', - 'nir_tex_instr_has_implicit_derivative', 'nir_tex_instr_is_query', - 'nir_tex_instr_need_sampler', 'nir_tex_instr_remove_src', - 'nir_tex_instr_result_size', 'nir_tex_instr_src_index', - 'nir_tex_instr_src_size', 'nir_tex_instr_src_type', - 'nir_tex_pass_cb', 'nir_tex_src', 'nir_tex_src_backend1', - 'nir_tex_src_backend2', 'nir_tex_src_bias', - 'nir_tex_src_comparator', 'nir_tex_src_coord', 'nir_tex_src_ddx', - 'nir_tex_src_ddy', 'nir_tex_src_for_ssa', 'nir_tex_src_lod', - 'nir_tex_src_lod_bias_min_agx', 'nir_tex_src_min_lod', - 'nir_tex_src_ms_index', 'nir_tex_src_ms_mcs_intel', - 'nir_tex_src_offset', 'nir_tex_src_plane', - 'nir_tex_src_projector', 'nir_tex_src_sampler_deref', - 'nir_tex_src_sampler_deref_intrinsic', - 'nir_tex_src_sampler_handle', 'nir_tex_src_sampler_offset', - 'nir_tex_src_texture_deref', - 'nir_tex_src_texture_deref_intrinsic', - 'nir_tex_src_texture_handle', 'nir_tex_src_texture_offset', - 'nir_tex_src_type', 'nir_tex_src_type_constraint', - 'nir_tex_src_type_constraints', 'nir_tex_type_has_lod', - 'nir_texop', 'nir_texop_custom_border_color_agx', - 'nir_texop_descriptor_amd', 'nir_texop_fragment_fetch_amd', - 'nir_texop_fragment_mask_fetch_amd', - 'nir_texop_has_custom_border_color_agx', 'nir_texop_hdr_dim_nv', - 'nir_texop_image_min_lod_agx', 'nir_texop_lod', - 'nir_texop_lod_bias', 'nir_texop_query_levels', - 'nir_texop_sampler_descriptor_amd', 'nir_texop_samples_identical', - 'nir_texop_tex', 'nir_texop_tex_prefetch', - 'nir_texop_tex_type_nv', 'nir_texop_texture_samples', - 'nir_texop_tg4', 'nir_texop_txb', 'nir_texop_txd', - 'nir_texop_txf', 'nir_texop_txf_ms', 'nir_texop_txf_ms_fb', - 'nir_texop_txf_ms_mcs_intel', 'nir_texop_txl', 'nir_texop_txs', - 'nir_trim_vector', 'nir_trivialize_registers', 'nir_txf_deref', - 'nir_txf_ms_deref', 'nir_txl_deref', 'nir_txl_zero_deref', - 'nir_txs_deref', 'nir_type_bool', 'nir_type_bool1', - 'nir_type_bool16', 'nir_type_bool32', 'nir_type_bool8', - 'nir_type_conversion_op', 'nir_type_convert', 'nir_type_float', - 'nir_type_float16', 'nir_type_float32', 'nir_type_float64', - 'nir_type_int', 'nir_type_int1', 'nir_type_int16', - 'nir_type_int32', 'nir_type_int64', 'nir_type_int8', - 'nir_type_invalid', 'nir_type_uint', 'nir_type_uint1', - 'nir_type_uint16', 'nir_type_uint32', 'nir_type_uint64', - 'nir_type_uint8', 'nir_u2fN', 'nir_u2uN', 'nir_ubfe_imm', - 'nir_ubitfield_extract_imm', 'nir_uclamp', 'nir_udiv_imm', - 'nir_umax_imm', 'nir_umin_imm', 'nir_umod_imm', 'nir_undef', - 'nir_undef_instr', 'nir_undef_instr_create', 'nir_unpack_bits', - 'nir_unsigned_upper_bound', 'nir_unsigned_upper_bound_config', - 'nir_unstructured_start_block', 'nir_use_dominance_lca', - 'nir_use_dominance_state', 'nir_ushr_imm', 'nir_validate_shader', - 'nir_validate_ssa_dominance', 'nir_var_all', - 'nir_var_declaration_type', - 'nir_var_declaration_type__enumvalues', - 'nir_var_declared_implicitly', 'nir_var_declared_normally', - 'nir_var_function_in', 'nir_var_function_inout', - 'nir_var_function_out', 'nir_var_function_temp', 'nir_var_hidden', - 'nir_var_image', 'nir_var_mem_constant', 'nir_var_mem_generic', - 'nir_var_mem_global', 'nir_var_mem_node_payload', - 'nir_var_mem_node_payload_in', 'nir_var_mem_push_const', - 'nir_var_mem_shared', 'nir_var_mem_ssbo', - 'nir_var_mem_task_payload', 'nir_var_mem_ubo', - 'nir_var_ray_hit_attrib', 'nir_var_read_only_modes', - 'nir_var_shader_call_data', 'nir_var_shader_in', - 'nir_var_shader_out', 'nir_var_shader_temp', - 'nir_var_system_value', 'nir_var_uniform', - 'nir_var_vec_indexable_modes', 'nir_variable', - 'nir_variable_clone', 'nir_variable_count_slots', - 'nir_variable_create', 'nir_variable_data', - 'nir_variable_is_global', 'nir_variable_is_in_block', - 'nir_variable_is_in_ssbo', 'nir_variable_is_in_ubo', - 'nir_variable_mode', 'nir_variable_mode__enumvalues', 'nir_vec', - 'nir_vec_scalars', 'nir_vector_extract', 'nir_vector_insert', - 'nir_vector_insert_imm', 'nir_vectorize_cb', - 'nir_vertex_divergence_analysis', 'nir_verts_in_output_prim', - 'nir_zero_initialize_shared_memory', 'nv_device_type', - 'nv_device_uuid', 'pipe_format', 'pipe_shader_type', - 'ralloc_adopt', 'ralloc_array_size', 'ralloc_asprintf', - 'ralloc_asprintf_append', 'ralloc_asprintf_rewrite_tail', - 'ralloc_context', 'ralloc_free', 'ralloc_memdup', 'ralloc_parent', - 'ralloc_parent_of_linear_context', 'ralloc_print_info', - 'ralloc_set_destructor', 'ralloc_size', 'ralloc_steal', - 'ralloc_steal_linear_context', 'ralloc_str_append', - 'ralloc_strcat', 'ralloc_strdup', 'ralloc_strncat', - 'ralloc_strndup', 'ralloc_total_size', 'ralloc_vasprintf', - 'ralloc_vasprintf_append', 'ralloc_vasprintf_rewrite_tail', - 'reralloc_array_size', 'reralloc_size', 'rerzalloc_array_size', - 'rerzalloc_size', 'rzalloc_array_size', 'rzalloc_size', - 'should_print_nir', 'should_skip_nir', 'size_t', - 'struct_LLVMOpaqueBasicBlock', 'struct_LLVMOpaqueBuilder', - 'struct_LLVMOpaqueContext', 'struct_LLVMOpaqueDIBuilder', - 'struct_LLVMOpaqueExecutionEngine', - 'struct_LLVMOpaqueMCJITMemoryManager', - 'struct_LLVMOpaqueMetadata', 'struct_LLVMOpaqueModule', - 'struct_LLVMOpaqueTargetData', - 'struct_LLVMOpaqueTargetLibraryInfotData', - 'struct_LLVMOpaqueTargetMachine', 'struct_LLVMOpaqueType', - 'struct_LLVMOpaqueValue', 'struct__IO_FILE', 'struct__IO_codecvt', - 'struct__IO_marker', 'struct__IO_wide_data', - 'struct___va_list_tag', 'struct_blob', 'struct_blob_reader', - 'struct_c__SA_linear_opts', - 'struct_c__SA_nir_input_to_output_deps', - 'struct_c__SA_nir_input_to_output_deps_0', - 'struct_c__SA_nir_output_clipper_var_groups', - 'struct_c__SA_nir_output_deps', 'struct_c__SA_nir_output_deps_0', - 'struct_exec_list', 'struct_exec_node', 'struct_gallivm_state', - 'struct_gc_ctx', 'struct_glsl_cmat_description', - 'struct_glsl_struct_field', 'struct_glsl_struct_field_0_0', - 'struct_glsl_type', 'struct_hash_entry', 'struct_hash_table', - 'struct_linear_ctx', 'struct_list_head', - 'struct_lp_bld_tgsi_system_values', 'struct_lp_build_context', - 'struct_lp_build_coro_suspend_info', 'struct_lp_build_fn', - 'struct_lp_build_for_loop_state', 'struct_lp_build_fs_iface', - 'struct_lp_build_gs_iface', 'struct_lp_build_if_state', - 'struct_lp_build_image_soa', 'struct_lp_build_loop_state', - 'struct_lp_build_mask_context', 'struct_lp_build_mesh_iface', - 'struct_lp_build_sampler_aos', 'struct_lp_build_sampler_soa', - 'struct_lp_build_skip_context', 'struct_lp_build_tcs_iface', - 'struct_lp_build_tes_iface', 'struct_lp_build_tgsi_params', - 'struct_lp_cached_code', 'struct_lp_context_ref', - 'struct_lp_derivatives', 'struct_lp_descriptor', - 'struct_lp_descriptor_0_0', 'struct_lp_descriptor_0_1', - 'struct_lp_generated_code', 'struct_lp_img_params', - 'struct_lp_jit_bindless_texture', 'struct_lp_jit_buffer', - 'struct_lp_jit_image', 'struct_lp_jit_resources', - 'struct_lp_jit_sampler', 'struct_lp_jit_texture', - 'struct_lp_jit_texture_0_0', 'struct_lp_passmgr', - 'struct_lp_sampler_dynamic_state', 'struct_lp_sampler_params', - 'struct_lp_sampler_size_query_params', - 'struct_lp_static_texture_state', 'struct_lp_texture_functions', - 'struct_lp_texture_handle', 'struct_lp_texture_handle_state', - 'struct_lp_type', 'struct_nak_compiler', 'struct_nak_fs_key', - 'struct_nak_qmd_cbuf', 'struct_nak_qmd_cbuf_desc_layout', - 'struct_nak_qmd_dispatch_size_layout', 'struct_nak_qmd_info', - 'struct_nak_sample_location', 'struct_nak_sample_mask', - 'struct_nak_shader_bin', 'struct_nak_shader_info', - 'struct_nak_shader_info_0_cs', 'struct_nak_shader_info_0_fs', - 'struct_nak_shader_info_0_ts', 'struct_nak_shader_info_vtg', - 'struct_nak_xfb_info', 'struct_nir_alu_instr', - 'struct_nir_alu_src', 'struct_nir_binding', 'struct_nir_block', - 'struct_nir_builder', 'struct_nir_call_instr', - 'struct_nir_cf_node', 'struct_nir_constant', 'struct_nir_cursor', - 'struct_nir_def', 'struct_nir_deref_instr', - 'struct_nir_deref_instr_1_arr', 'struct_nir_deref_instr_1_cast', - 'struct_nir_deref_instr_1_strct', 'struct_nir_function', - 'struct_nir_function_impl', 'struct_nir_if', - 'struct_nir_input_attachment_options', 'struct_nir_instr', - 'struct_nir_instr_debug_info', 'struct_nir_intrinsic_info', - 'struct_nir_intrinsic_instr', 'struct_nir_io_semantics', - 'struct_nir_io_xfb', 'struct_nir_io_xfb_0', - 'struct_nir_jump_instr', 'struct_nir_load_const_instr', - 'struct_nir_load_store_vectorize_options', 'struct_nir_loop', - 'struct_nir_loop_induction_variable', 'struct_nir_loop_info', - 'struct_nir_loop_terminator', 'struct_nir_lower_bitmap_options', - 'struct_nir_lower_compute_system_values_options', - 'struct_nir_lower_drawpixels_options', - 'struct_nir_lower_idiv_options', 'struct_nir_lower_image_options', - 'struct_nir_lower_mem_access_bit_sizes_options', - 'struct_nir_lower_multiview_options', - 'struct_nir_lower_non_uniform_access_options', - 'struct_nir_lower_printf_options', - 'struct_nir_lower_shader_calls_options', - 'struct_nir_lower_ssbo_options', - 'struct_nir_lower_subgroups_options', - 'struct_nir_lower_sysvals_to_varyings_options', - 'struct_nir_lower_task_shader_options', - 'struct_nir_lower_tex_options', - 'struct_nir_lower_tex_shadow_swizzle', - 'struct_nir_lower_wpos_ytransform_options', - 'struct_nir_mem_access_size_align', 'struct_nir_op_info', - 'struct_nir_opt_16bit_tex_image_options', - 'struct_nir_opt_access_options', 'struct_nir_opt_offsets_options', - 'struct_nir_opt_peephole_select_options', - 'struct_nir_opt_preamble_options', - 'struct_nir_opt_tex_srcs_options', - 'struct_nir_parallel_copy_entry', - 'struct_nir_parallel_copy_instr', 'struct_nir_parameter', - 'struct_nir_phi_instr', 'struct_nir_phi_src', - 'struct_nir_remove_dead_variables_options', 'struct_nir_scalar', - 'struct_nir_shader', 'struct_nir_shader_compiler_options', - 'struct_nir_split_conversions_options', 'struct_nir_src', - 'struct_nir_state_slot', 'struct_nir_tex_instr', - 'struct_nir_tex_src', 'struct_nir_tex_src_type_constraint', - 'struct_nir_undef_instr', - 'struct_nir_unsigned_upper_bound_config', - 'struct_nir_use_dominance_state', 'struct_nir_variable', - 'struct_nir_variable_data', 'struct_nir_variable_data_0_image', - 'struct_nir_variable_data_0_sampler', - 'struct_nir_variable_data_0_xfb', 'struct_nir_xfb_info', - 'struct_nv_device_info', 'struct_nv_device_info_pci', - 'struct_set', 'struct_set_entry', 'struct_shader_info', - 'struct_shader_info_0_cs', 'struct_shader_info_0_fs', - 'struct_shader_info_0_gs', 'struct_shader_info_0_mesh', - 'struct_shader_info_0_tess', 'struct_shader_info_0_vs', - 'struct_tgsi_shader_info', 'struct_u_printf_info', - 'struct_util_format_block', - 'struct_util_format_channel_description', - 'struct_util_format_description', 'tess_primitive_mode', - 'tgsi_texture_type', 'u_printf_info', 'uint16_t', 'uint32_t', - 'uint64_t', 'uint8_t', 'union_c__UA_nir_const_value', - 'union_glsl_struct_field_0', 'union_glsl_type_fields', - 'union_lp_descriptor_0', 'union_lp_jit_buffer_0', - 'union_lp_jit_texture_0', 'union_nak_shader_info_0', - 'union_nir_cursor_0', 'union_nir_deref_instr_0', - 'union_nir_deref_instr_1', 'union_nir_parallel_copy_entry_dest', - 'union_nir_variable_data_0', 'union_shader_info_0', - 'union_util_format_description_0', 'util_format_colorspace', - 'util_format_layout', 'va_list'] -lvp_nir_options = gzip.decompress(base64.b64decode('H4sIAAAAAAAAA2NgZGRkYGAAkYxgCsQFsxigwgwQBoxmhCqFq2WEKwIrAEGIkQxoAEMALwCqVsCiGUwLMHA0QPn29nBJkswHANb8YpH4AAAA')) -def __getattr__(nm): raise AttributeError('LLVMpipe requires tinymesa_cpu' if 'tinymesa_cpu' not in dll._name else f'attribute {nm} not found') if dll else FileNotFoundError(f'libtinymesa not found (MESA_PATH={BASE}). See https://github.com/sirhcm/tinymesa (tinymesa-32dc66c, mesa-25.2.4)') +# void lp_build_flow_skip_cond_break(struct lp_build_skip_context *ctx, LLVMValueRef cond) +try: (lp_build_flow_skip_cond_break:=dll.lp_build_flow_skip_cond_break).restype, lp_build_flow_skip_cond_break.argtypes = None, [ctypes.POINTER(struct_lp_build_skip_context), LLVMValueRef] +except AttributeError: pass + +# void lp_build_flow_skip_end(struct lp_build_skip_context *ctx) +try: (lp_build_flow_skip_end:=dll.lp_build_flow_skip_end).restype, lp_build_flow_skip_end.argtypes = None, [ctypes.POINTER(struct_lp_build_skip_context)] +except AttributeError: pass + +# void lp_build_mask_begin(struct lp_build_mask_context *mask, struct gallivm_state *gallivm, struct lp_type type, LLVMValueRef value) +try: (lp_build_mask_begin:=dll.lp_build_mask_begin).restype, lp_build_mask_begin.argtypes = None, [ctypes.POINTER(struct_lp_build_mask_context), ctypes.POINTER(struct_gallivm_state), struct_lp_type, LLVMValueRef] +except AttributeError: pass + +# LLVMValueRef lp_build_mask_value(struct lp_build_mask_context *mask) +try: (lp_build_mask_value:=dll.lp_build_mask_value).restype, lp_build_mask_value.argtypes = LLVMValueRef, [ctypes.POINTER(struct_lp_build_mask_context)] +except AttributeError: pass + +# void lp_build_mask_update(struct lp_build_mask_context *mask, LLVMValueRef value) +try: (lp_build_mask_update:=dll.lp_build_mask_update).restype, lp_build_mask_update.argtypes = None, [ctypes.POINTER(struct_lp_build_mask_context), LLVMValueRef] +except AttributeError: pass + +# void lp_build_mask_force(struct lp_build_mask_context *mask, LLVMValueRef value) +try: (lp_build_mask_force:=dll.lp_build_mask_force).restype, lp_build_mask_force.argtypes = None, [ctypes.POINTER(struct_lp_build_mask_context), LLVMValueRef] +except AttributeError: pass + +# void lp_build_mask_check(struct lp_build_mask_context *mask) +try: (lp_build_mask_check:=dll.lp_build_mask_check).restype, lp_build_mask_check.argtypes = None, [ctypes.POINTER(struct_lp_build_mask_context)] +except AttributeError: pass + +# LLVMValueRef lp_build_mask_end(struct lp_build_mask_context *mask) +try: (lp_build_mask_end:=dll.lp_build_mask_end).restype, lp_build_mask_end.argtypes = LLVMValueRef, [ctypes.POINTER(struct_lp_build_mask_context)] +except AttributeError: pass + +class struct_lp_build_loop_state(Struct): pass +struct_lp_build_loop_state._fields_ = [ + ('block', LLVMBasicBlockRef), + ('counter_var', LLVMValueRef), + ('counter', LLVMValueRef), + ('counter_type', LLVMTypeRef), + ('gallivm', ctypes.POINTER(struct_gallivm_state)), +] +# void lp_build_loop_begin(struct lp_build_loop_state *state, struct gallivm_state *gallivm, LLVMValueRef start) +try: (lp_build_loop_begin:=dll.lp_build_loop_begin).restype, lp_build_loop_begin.argtypes = None, [ctypes.POINTER(struct_lp_build_loop_state), ctypes.POINTER(struct_gallivm_state), LLVMValueRef] +except AttributeError: pass + +# void lp_build_loop_end(struct lp_build_loop_state *state, LLVMValueRef end, LLVMValueRef step) +try: (lp_build_loop_end:=dll.lp_build_loop_end).restype, lp_build_loop_end.argtypes = None, [ctypes.POINTER(struct_lp_build_loop_state), LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# void lp_build_loop_force_set_counter(struct lp_build_loop_state *state, LLVMValueRef end) +try: (lp_build_loop_force_set_counter:=dll.lp_build_loop_force_set_counter).restype, lp_build_loop_force_set_counter.argtypes = None, [ctypes.POINTER(struct_lp_build_loop_state), LLVMValueRef] +except AttributeError: pass + +# void lp_build_loop_force_reload_counter(struct lp_build_loop_state *state) +try: (lp_build_loop_force_reload_counter:=dll.lp_build_loop_force_reload_counter).restype, lp_build_loop_force_reload_counter.argtypes = None, [ctypes.POINTER(struct_lp_build_loop_state)] +except AttributeError: pass + +LLVMIntPredicate = CEnum(ctypes.c_uint32) +LLVMIntEQ = LLVMIntPredicate.define('LLVMIntEQ', 32) +LLVMIntNE = LLVMIntPredicate.define('LLVMIntNE', 33) +LLVMIntUGT = LLVMIntPredicate.define('LLVMIntUGT', 34) +LLVMIntUGE = LLVMIntPredicate.define('LLVMIntUGE', 35) +LLVMIntULT = LLVMIntPredicate.define('LLVMIntULT', 36) +LLVMIntULE = LLVMIntPredicate.define('LLVMIntULE', 37) +LLVMIntSGT = LLVMIntPredicate.define('LLVMIntSGT', 38) +LLVMIntSGE = LLVMIntPredicate.define('LLVMIntSGE', 39) +LLVMIntSLT = LLVMIntPredicate.define('LLVMIntSLT', 40) +LLVMIntSLE = LLVMIntPredicate.define('LLVMIntSLE', 41) + +# void lp_build_loop_end_cond(struct lp_build_loop_state *state, LLVMValueRef end, LLVMValueRef step, LLVMIntPredicate cond) +try: (lp_build_loop_end_cond:=dll.lp_build_loop_end_cond).restype, lp_build_loop_end_cond.argtypes = None, [ctypes.POINTER(struct_lp_build_loop_state), LLVMValueRef, LLVMValueRef, LLVMIntPredicate] +except AttributeError: pass + +class struct_lp_build_for_loop_state(Struct): pass +struct_lp_build_for_loop_state._fields_ = [ + ('begin', LLVMBasicBlockRef), + ('body', LLVMBasicBlockRef), + ('exit', LLVMBasicBlockRef), + ('counter_var', LLVMValueRef), + ('counter', LLVMValueRef), + ('counter_type', LLVMTypeRef), + ('step', LLVMValueRef), + ('cond', LLVMIntPredicate), + ('end', LLVMValueRef), + ('gallivm', ctypes.POINTER(struct_gallivm_state)), +] +# void lp_build_for_loop_begin(struct lp_build_for_loop_state *state, struct gallivm_state *gallivm, LLVMValueRef start, LLVMIntPredicate llvm_cond, LLVMValueRef end, LLVMValueRef step) +try: (lp_build_for_loop_begin:=dll.lp_build_for_loop_begin).restype, lp_build_for_loop_begin.argtypes = None, [ctypes.POINTER(struct_lp_build_for_loop_state), ctypes.POINTER(struct_gallivm_state), LLVMValueRef, LLVMIntPredicate, LLVMValueRef, LLVMValueRef] +except AttributeError: pass + +# void lp_build_for_loop_end(struct lp_build_for_loop_state *state) +try: (lp_build_for_loop_end:=dll.lp_build_for_loop_end).restype, lp_build_for_loop_end.argtypes = None, [ctypes.POINTER(struct_lp_build_for_loop_state)] +except AttributeError: pass + +class struct_lp_build_if_state(Struct): pass +struct_lp_build_if_state._fields_ = [ + ('gallivm', ctypes.POINTER(struct_gallivm_state)), + ('condition', LLVMValueRef), + ('entry_block', LLVMBasicBlockRef), + ('true_block', LLVMBasicBlockRef), + ('false_block', LLVMBasicBlockRef), + ('merge_block', LLVMBasicBlockRef), +] +# void lp_build_if(struct lp_build_if_state *ctx, struct gallivm_state *gallivm, LLVMValueRef condition) +try: (lp_build_if:=dll.lp_build_if).restype, lp_build_if.argtypes = None, [ctypes.POINTER(struct_lp_build_if_state), ctypes.POINTER(struct_gallivm_state), LLVMValueRef] +except AttributeError: pass + +# void lp_build_else(struct lp_build_if_state *ctx) +try: (lp_build_else:=dll.lp_build_else).restype, lp_build_else.argtypes = None, [ctypes.POINTER(struct_lp_build_if_state)] +except AttributeError: pass + +# void lp_build_endif(struct lp_build_if_state *ctx) +try: (lp_build_endif:=dll.lp_build_endif).restype, lp_build_endif.argtypes = None, [ctypes.POINTER(struct_lp_build_if_state)] +except AttributeError: pass + +# LLVMBasicBlockRef lp_build_insert_new_block(struct gallivm_state *gallivm, const char *name) +try: (lp_build_insert_new_block:=dll.lp_build_insert_new_block).restype, lp_build_insert_new_block.argtypes = LLVMBasicBlockRef, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMBuilderRef lp_create_builder_at_entry(struct gallivm_state *gallivm) +try: (lp_create_builder_at_entry:=dll.lp_create_builder_at_entry).restype, lp_create_builder_at_entry.argtypes = LLVMBuilderRef, [ctypes.POINTER(struct_gallivm_state)] +except AttributeError: pass + +# LLVMValueRef lp_build_alloca(struct gallivm_state *gallivm, LLVMTypeRef type, const char *name) +try: (lp_build_alloca:=dll.lp_build_alloca).restype, lp_build_alloca.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef lp_build_alloca_undef(struct gallivm_state *gallivm, LLVMTypeRef type, const char *name) +try: (lp_build_alloca_undef:=dll.lp_build_alloca_undef).restype, lp_build_alloca_undef.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef lp_build_array_alloca(struct gallivm_state *gallivm, LLVMTypeRef type, LLVMValueRef count, const char *name) +try: (lp_build_array_alloca:=dll.lp_build_array_alloca).restype, lp_build_array_alloca.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), LLVMTypeRef, LLVMValueRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# unsigned int lp_mantissa(struct lp_type type) +try: (lp_mantissa:=dll.lp_mantissa).restype, lp_mantissa.argtypes = ctypes.c_uint32, [struct_lp_type] +except AttributeError: pass + +# unsigned int lp_const_shift(struct lp_type type) +try: (lp_const_shift:=dll.lp_const_shift).restype, lp_const_shift.argtypes = ctypes.c_uint32, [struct_lp_type] +except AttributeError: pass + +# unsigned int lp_const_offset(struct lp_type type) +try: (lp_const_offset:=dll.lp_const_offset).restype, lp_const_offset.argtypes = ctypes.c_uint32, [struct_lp_type] +except AttributeError: pass + +# double lp_const_scale(struct lp_type type) +try: (lp_const_scale:=dll.lp_const_scale).restype, lp_const_scale.argtypes = ctypes.c_double, [struct_lp_type] +except AttributeError: pass + +# double lp_const_min(struct lp_type type) +try: (lp_const_min:=dll.lp_const_min).restype, lp_const_min.argtypes = ctypes.c_double, [struct_lp_type] +except AttributeError: pass + +# double lp_const_max(struct lp_type type) +try: (lp_const_max:=dll.lp_const_max).restype, lp_const_max.argtypes = ctypes.c_double, [struct_lp_type] +except AttributeError: pass + +# double lp_const_eps(struct lp_type type) +try: (lp_const_eps:=dll.lp_const_eps).restype, lp_const_eps.argtypes = ctypes.c_double, [struct_lp_type] +except AttributeError: pass + +# LLVMValueRef lp_build_undef(struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_undef:=dll.lp_build_undef).restype, lp_build_undef.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass + +# LLVMValueRef lp_build_zero(struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_zero:=dll.lp_build_zero).restype, lp_build_zero.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass + +# LLVMValueRef lp_build_one(struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_one:=dll.lp_build_one).restype, lp_build_one.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass + +# LLVMValueRef lp_build_const_elem(struct gallivm_state *gallivm, struct lp_type type, double val) +try: (lp_build_const_elem:=dll.lp_build_const_elem).restype, lp_build_const_elem.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_double] +except AttributeError: pass + +# LLVMValueRef lp_build_const_vec(struct gallivm_state *gallivm, struct lp_type type, double val) +try: (lp_build_const_vec:=dll.lp_build_const_vec).restype, lp_build_const_vec.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_double] +except AttributeError: pass + +# LLVMValueRef lp_build_const_int_vec(struct gallivm_state *gallivm, struct lp_type type, long long val) +try: (lp_build_const_int_vec:=dll.lp_build_const_int_vec).restype, lp_build_const_int_vec.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_int64] +except AttributeError: pass + +# LLVMValueRef lp_build_const_channel_vec(struct gallivm_state *gallivm, struct lp_type type) +try: (lp_build_const_channel_vec:=dll.lp_build_const_channel_vec).restype, lp_build_const_channel_vec.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type] +except AttributeError: pass + +# LLVMValueRef lp_build_const_aos(struct gallivm_state *gallivm, struct lp_type type, double r, double g, double b, double a, const unsigned char *swizzle) +try: (lp_build_const_aos:=dll.lp_build_const_aos).restype, lp_build_const_aos.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_double, ctypes.c_double, ctypes.c_double, ctypes.c_double, ctypes.POINTER(ctypes.c_ubyte)] +except AttributeError: pass + +# LLVMValueRef lp_build_const_mask_aos(struct gallivm_state *gallivm, struct lp_type type, unsigned int mask, unsigned int channels) +try: (lp_build_const_mask_aos:=dll.lp_build_const_mask_aos).restype, lp_build_const_mask_aos.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# LLVMValueRef lp_build_const_mask_aos_swizzled(struct gallivm_state *gallivm, struct lp_type type, unsigned int mask, unsigned int channels, const unsigned char *swizzle) +try: (lp_build_const_mask_aos_swizzled:=dll.lp_build_const_mask_aos_swizzled).restype, lp_build_const_mask_aos_swizzled.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), struct_lp_type, ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(ctypes.c_ubyte)] +except AttributeError: pass + +# LLVMValueRef lp_build_const_string(struct gallivm_state *gallivm, const char *str) +try: (lp_build_const_string:=dll.lp_build_const_string).restype, lp_build_const_string.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef lp_build_const_func_pointer(struct gallivm_state *gallivm, const void *ptr, LLVMTypeRef ret_type, LLVMTypeRef *arg_types, unsigned int num_args, const char *name) +try: (lp_build_const_func_pointer:=dll.lp_build_const_func_pointer).restype, lp_build_const_func_pointer.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), ctypes.c_void_p, LLVMTypeRef, ctypes.POINTER(LLVMTypeRef), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# LLVMValueRef lp_build_const_func_pointer_from_type(struct gallivm_state *gallivm, const void *ptr, LLVMTypeRef function_type, const char *name) +try: (lp_build_const_func_pointer_from_type:=dll.lp_build_const_func_pointer_from_type).restype, lp_build_const_func_pointer_from_type.argtypes = LLVMValueRef, [ctypes.POINTER(struct_gallivm_state), ctypes.c_void_p, LLVMTypeRef, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern void glsl_type_singleton_init_or_ref(void) +try: (glsl_type_singleton_init_or_ref:=dll.glsl_type_singleton_init_or_ref).restype, glsl_type_singleton_init_or_ref.argtypes = None, [] +except AttributeError: pass + +# extern void glsl_type_singleton_decref(void) +try: (glsl_type_singleton_decref:=dll.glsl_type_singleton_decref).restype, glsl_type_singleton_decref.argtypes = None, [] +except AttributeError: pass + +# void encode_type_to_blob(struct blob *blob, const glsl_type *type) +try: (encode_type_to_blob:=dll.encode_type_to_blob).restype, encode_type_to_blob.argtypes = None, [ctypes.POINTER(struct_blob), ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *decode_type_from_blob(struct blob_reader *blob) +try: (decode_type_from_blob:=dll.decode_type_from_blob).restype, decode_type_from_blob.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# enum glsl_base_type glsl_apply_signedness_to_base_type(enum glsl_base_type type, bool signedness) +try: (glsl_apply_signedness_to_base_type:=dll.glsl_apply_signedness_to_base_type).restype, glsl_apply_signedness_to_base_type.argtypes = enum_glsl_base_type, [enum_glsl_base_type, ctypes.c_bool] +except AttributeError: pass + +# int glsl_get_sampler_dim_coordinate_components(enum glsl_sampler_dim dim) +try: (glsl_get_sampler_dim_coordinate_components:=dll.glsl_get_sampler_dim_coordinate_components).restype, glsl_get_sampler_dim_coordinate_components.argtypes = ctypes.c_int32, [enum_glsl_sampler_dim] +except AttributeError: pass + +enum_glsl_matrix_layout = CEnum(ctypes.c_uint32) +GLSL_MATRIX_LAYOUT_INHERITED = enum_glsl_matrix_layout.define('GLSL_MATRIX_LAYOUT_INHERITED', 0) +GLSL_MATRIX_LAYOUT_COLUMN_MAJOR = enum_glsl_matrix_layout.define('GLSL_MATRIX_LAYOUT_COLUMN_MAJOR', 1) +GLSL_MATRIX_LAYOUT_ROW_MAJOR = enum_glsl_matrix_layout.define('GLSL_MATRIX_LAYOUT_ROW_MAJOR', 2) + +_anonenum6 = CEnum(ctypes.c_uint32) +GLSL_PRECISION_NONE = _anonenum6.define('GLSL_PRECISION_NONE', 0) +GLSL_PRECISION_HIGH = _anonenum6.define('GLSL_PRECISION_HIGH', 1) +GLSL_PRECISION_MEDIUM = _anonenum6.define('GLSL_PRECISION_MEDIUM', 2) +GLSL_PRECISION_LOW = _anonenum6.define('GLSL_PRECISION_LOW', 3) + +enum_glsl_cmat_use = CEnum(ctypes.c_uint32) +GLSL_CMAT_USE_NONE = enum_glsl_cmat_use.define('GLSL_CMAT_USE_NONE', 0) +GLSL_CMAT_USE_A = enum_glsl_cmat_use.define('GLSL_CMAT_USE_A', 1) +GLSL_CMAT_USE_B = enum_glsl_cmat_use.define('GLSL_CMAT_USE_B', 2) +GLSL_CMAT_USE_ACCUMULATOR = enum_glsl_cmat_use.define('GLSL_CMAT_USE_ACCUMULATOR', 3) + +# const char *glsl_get_type_name(const glsl_type *type) +try: (glsl_get_type_name:=dll.glsl_get_type_name).restype, glsl_get_type_name.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_vector(const glsl_type *t) +try: (glsl_type_is_vector:=dll.glsl_type_is_vector).restype, glsl_type_is_vector.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_scalar(const glsl_type *t) +try: (glsl_type_is_scalar:=dll.glsl_type_is_scalar).restype, glsl_type_is_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_vector_or_scalar(const glsl_type *t) +try: (glsl_type_is_vector_or_scalar:=dll.glsl_type_is_vector_or_scalar).restype, glsl_type_is_vector_or_scalar.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_matrix(const glsl_type *t) +try: (glsl_type_is_matrix:=dll.glsl_type_is_matrix).restype, glsl_type_is_matrix.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_array_or_matrix(const glsl_type *t) +try: (glsl_type_is_array_or_matrix:=dll.glsl_type_is_array_or_matrix).restype, glsl_type_is_array_or_matrix.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_dual_slot(const glsl_type *t) +try: (glsl_type_is_dual_slot:=dll.glsl_type_is_dual_slot).restype, glsl_type_is_dual_slot.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_is_leaf(const glsl_type *type) +try: (glsl_type_is_leaf:=dll.glsl_type_is_leaf).restype, glsl_type_is_leaf.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_bare_type(const glsl_type *t) +try: (glsl_get_bare_type:=dll.glsl_get_bare_type).restype, glsl_get_bare_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_scalar_type(const glsl_type *t) +try: (glsl_get_scalar_type:=dll.glsl_get_scalar_type).restype, glsl_get_scalar_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_base_glsl_type(const glsl_type *t) +try: (glsl_get_base_glsl_type:=dll.glsl_get_base_glsl_type).restype, glsl_get_base_glsl_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_get_length(const glsl_type *t) +try: (glsl_get_length:=dll.glsl_get_length).restype, glsl_get_length.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_type_wrap_in_arrays(const glsl_type *t, const glsl_type *arrays) +try: (glsl_type_wrap_in_arrays:=dll.glsl_type_wrap_in_arrays).restype, glsl_type_wrap_in_arrays.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_get_aoa_size(const glsl_type *t) +try: (glsl_get_aoa_size:=dll.glsl_get_aoa_size).restype, glsl_get_aoa_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_array_element(const glsl_type *t) +try: (glsl_get_array_element:=dll.glsl_get_array_element).restype, glsl_get_array_element.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_without_array(const glsl_type *t) +try: (glsl_without_array:=dll.glsl_without_array).restype, glsl_without_array.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_without_array_or_matrix(const glsl_type *t) +try: (glsl_without_array_or_matrix:=dll.glsl_without_array_or_matrix).restype, glsl_without_array_or_matrix.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_type_wrap_in_arrays(const glsl_type *t, const glsl_type *arrays) +try: (glsl_type_wrap_in_arrays:=dll.glsl_type_wrap_in_arrays).restype, glsl_type_wrap_in_arrays.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_cmat_element(const glsl_type *t) +try: (glsl_get_cmat_element:=dll.glsl_get_cmat_element).restype, glsl_get_cmat_element.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const struct glsl_cmat_description *glsl_get_cmat_description(const glsl_type *t) +try: (glsl_get_cmat_description:=dll.glsl_get_cmat_description).restype, glsl_get_cmat_description.argtypes = ctypes.POINTER(struct_glsl_cmat_description), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_atomic_size(const glsl_type *type) +try: (glsl_atomic_size:=dll.glsl_atomic_size).restype, glsl_atomic_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_contains_32bit(const glsl_type *t) +try: (glsl_type_contains_32bit:=dll.glsl_type_contains_32bit).restype, glsl_type_contains_32bit.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_contains_64bit(const glsl_type *t) +try: (glsl_type_contains_64bit:=dll.glsl_type_contains_64bit).restype, glsl_type_contains_64bit.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_contains_image(const glsl_type *t) +try: (glsl_type_contains_image:=dll.glsl_type_contains_image).restype, glsl_type_contains_image.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_atomic(const glsl_type *t) +try: (glsl_contains_atomic:=dll.glsl_contains_atomic).restype, glsl_contains_atomic.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_double(const glsl_type *t) +try: (glsl_contains_double:=dll.glsl_contains_double).restype, glsl_contains_double.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_integer(const glsl_type *t) +try: (glsl_contains_integer:=dll.glsl_contains_integer).restype, glsl_contains_integer.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_opaque(const glsl_type *t) +try: (glsl_contains_opaque:=dll.glsl_contains_opaque).restype, glsl_contains_opaque.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_sampler(const glsl_type *t) +try: (glsl_contains_sampler:=dll.glsl_contains_sampler).restype, glsl_contains_sampler.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_array(const glsl_type *t) +try: (glsl_contains_array:=dll.glsl_contains_array).restype, glsl_contains_array.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_contains_subroutine(const glsl_type *t) +try: (glsl_contains_subroutine:=dll.glsl_contains_subroutine).restype, glsl_contains_subroutine.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# int glsl_get_sampler_coordinate_components(const glsl_type *t) +try: (glsl_get_sampler_coordinate_components:=dll.glsl_get_sampler_coordinate_components).restype, glsl_get_sampler_coordinate_components.argtypes = ctypes.c_int32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_type_compare_no_precision(const glsl_type *a, const glsl_type *b) +try: (glsl_type_compare_no_precision:=dll.glsl_type_compare_no_precision).restype, glsl_type_compare_no_precision.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type), ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# bool glsl_record_compare(const glsl_type *a, const glsl_type *b, bool match_name, bool match_locations, bool match_precision) +try: (glsl_record_compare:=dll.glsl_record_compare).restype, glsl_record_compare.argtypes = ctypes.c_bool, [ctypes.POINTER(glsl_type), ctypes.POINTER(glsl_type), ctypes.c_bool, ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# const glsl_type *glsl_get_struct_field(const glsl_type *t, unsigned int index) +try: (glsl_get_struct_field:=dll.glsl_get_struct_field).restype, glsl_get_struct_field.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.c_uint32] +except AttributeError: pass + +# const glsl_struct_field *glsl_get_struct_field_data(const glsl_type *t, unsigned int index) +try: (glsl_get_struct_field_data:=dll.glsl_get_struct_field_data).restype, glsl_get_struct_field_data.argtypes = ctypes.POINTER(glsl_struct_field), [ctypes.POINTER(glsl_type), ctypes.c_uint32] +except AttributeError: pass + +# unsigned int glsl_get_struct_location_offset(const glsl_type *t, unsigned int length) +try: (glsl_get_struct_location_offset:=dll.glsl_get_struct_location_offset).restype, glsl_get_struct_location_offset.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_uint32] +except AttributeError: pass + +# int glsl_get_field_index(const glsl_type *t, const char *name) +try: (glsl_get_field_index:=dll.glsl_get_field_index).restype, glsl_get_field_index.argtypes = ctypes.c_int32, [ctypes.POINTER(glsl_type), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const glsl_type *glsl_get_field_type(const glsl_type *t, const char *name) +try: (glsl_get_field_type:=dll.glsl_get_field_type).restype, glsl_get_field_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const glsl_type *glsl_vec_type(unsigned int components) +try: (glsl_vec_type:=dll.glsl_vec_type).restype, glsl_vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_f16vec_type(unsigned int components) +try: (glsl_f16vec_type:=dll.glsl_f16vec_type).restype, glsl_f16vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_bf16vec_type(unsigned int components) +try: (glsl_bf16vec_type:=dll.glsl_bf16vec_type).restype, glsl_bf16vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_e4m3fnvec_type(unsigned int components) +try: (glsl_e4m3fnvec_type:=dll.glsl_e4m3fnvec_type).restype, glsl_e4m3fnvec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_e5m2vec_type(unsigned int components) +try: (glsl_e5m2vec_type:=dll.glsl_e5m2vec_type).restype, glsl_e5m2vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_dvec_type(unsigned int components) +try: (glsl_dvec_type:=dll.glsl_dvec_type).restype, glsl_dvec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_ivec_type(unsigned int components) +try: (glsl_ivec_type:=dll.glsl_ivec_type).restype, glsl_ivec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_uvec_type(unsigned int components) +try: (glsl_uvec_type:=dll.glsl_uvec_type).restype, glsl_uvec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_bvec_type(unsigned int components) +try: (glsl_bvec_type:=dll.glsl_bvec_type).restype, glsl_bvec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_i64vec_type(unsigned int components) +try: (glsl_i64vec_type:=dll.glsl_i64vec_type).restype, glsl_i64vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_u64vec_type(unsigned int components) +try: (glsl_u64vec_type:=dll.glsl_u64vec_type).restype, glsl_u64vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_i16vec_type(unsigned int components) +try: (glsl_i16vec_type:=dll.glsl_i16vec_type).restype, glsl_i16vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_u16vec_type(unsigned int components) +try: (glsl_u16vec_type:=dll.glsl_u16vec_type).restype, glsl_u16vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_i8vec_type(unsigned int components) +try: (glsl_i8vec_type:=dll.glsl_i8vec_type).restype, glsl_i8vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_u8vec_type(unsigned int components) +try: (glsl_u8vec_type:=dll.glsl_u8vec_type).restype, glsl_u8vec_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_simple_explicit_type(unsigned int base_type, unsigned int rows, unsigned int columns, unsigned int explicit_stride, bool row_major, unsigned int explicit_alignment) +try: (glsl_simple_explicit_type:=dll.glsl_simple_explicit_type).restype, glsl_simple_explicit_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_bool, ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_sampler_type(enum glsl_sampler_dim dim, bool shadow, bool array, enum glsl_base_type type) +try: (glsl_sampler_type:=dll.glsl_sampler_type).restype, glsl_sampler_type.argtypes = ctypes.POINTER(glsl_type), [enum_glsl_sampler_dim, ctypes.c_bool, ctypes.c_bool, enum_glsl_base_type] +except AttributeError: pass + +# const glsl_type *glsl_bare_sampler_type(void) +try: (glsl_bare_sampler_type:=dll.glsl_bare_sampler_type).restype, glsl_bare_sampler_type.argtypes = ctypes.POINTER(glsl_type), [] +except AttributeError: pass + +# const glsl_type *glsl_bare_shadow_sampler_type(void) +try: (glsl_bare_shadow_sampler_type:=dll.glsl_bare_shadow_sampler_type).restype, glsl_bare_shadow_sampler_type.argtypes = ctypes.POINTER(glsl_type), [] +except AttributeError: pass + +# const glsl_type *glsl_texture_type(enum glsl_sampler_dim dim, bool array, enum glsl_base_type type) +try: (glsl_texture_type:=dll.glsl_texture_type).restype, glsl_texture_type.argtypes = ctypes.POINTER(glsl_type), [enum_glsl_sampler_dim, ctypes.c_bool, enum_glsl_base_type] +except AttributeError: pass + +# const glsl_type *glsl_image_type(enum glsl_sampler_dim dim, bool array, enum glsl_base_type type) +try: (glsl_image_type:=dll.glsl_image_type).restype, glsl_image_type.argtypes = ctypes.POINTER(glsl_type), [enum_glsl_sampler_dim, ctypes.c_bool, enum_glsl_base_type] +except AttributeError: pass + +# const glsl_type *glsl_array_type(const glsl_type *element, unsigned int array_size, unsigned int explicit_stride) +try: (glsl_array_type:=dll.glsl_array_type).restype, glsl_array_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_cmat_type(const struct glsl_cmat_description *desc) +try: (glsl_cmat_type:=dll.glsl_cmat_type).restype, glsl_cmat_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(struct_glsl_cmat_description)] +except AttributeError: pass + +# const glsl_type *glsl_struct_type_with_explicit_alignment(const glsl_struct_field *fields, unsigned int num_fields, const char *name, bool packed, unsigned int explicit_alignment) +try: (glsl_struct_type_with_explicit_alignment:=dll.glsl_struct_type_with_explicit_alignment).restype, glsl_struct_type_with_explicit_alignment.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_struct_field), ctypes.c_uint32, ctypes.POINTER(ctypes.c_char), ctypes.c_bool, ctypes.c_uint32] +except AttributeError: pass + +enum_glsl_interface_packing = CEnum(ctypes.c_uint32) +GLSL_INTERFACE_PACKING_STD140 = enum_glsl_interface_packing.define('GLSL_INTERFACE_PACKING_STD140', 0) +GLSL_INTERFACE_PACKING_SHARED = enum_glsl_interface_packing.define('GLSL_INTERFACE_PACKING_SHARED', 1) +GLSL_INTERFACE_PACKING_PACKED = enum_glsl_interface_packing.define('GLSL_INTERFACE_PACKING_PACKED', 2) +GLSL_INTERFACE_PACKING_STD430 = enum_glsl_interface_packing.define('GLSL_INTERFACE_PACKING_STD430', 3) + +# const glsl_type *glsl_interface_type(const glsl_struct_field *fields, unsigned int num_fields, enum glsl_interface_packing packing, bool row_major, const char *block_name) +try: (glsl_interface_type:=dll.glsl_interface_type).restype, glsl_interface_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_struct_field), ctypes.c_uint32, enum_glsl_interface_packing, ctypes.c_bool, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const glsl_type *glsl_subroutine_type(const char *subroutine_name) +try: (glsl_subroutine_type:=dll.glsl_subroutine_type).restype, glsl_subroutine_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# const glsl_type *glsl_get_row_type(const glsl_type *t) +try: (glsl_get_row_type:=dll.glsl_get_row_type).restype, glsl_get_row_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_column_type(const glsl_type *t) +try: (glsl_get_column_type:=dll.glsl_get_column_type).restype, glsl_get_column_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_explicit_type_for_size_align(const glsl_type *type, glsl_type_size_align_func type_info, unsigned int *size, unsigned int *alignment) +try: (glsl_get_explicit_type_for_size_align:=dll.glsl_get_explicit_type_for_size_align).restype, glsl_get_explicit_type_for_size_align.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), glsl_type_size_align_func, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# const glsl_type *glsl_type_replace_vec3_with_vec4(const glsl_type *type) +try: (glsl_type_replace_vec3_with_vec4:=dll.glsl_type_replace_vec3_with_vec4).restype, glsl_type_replace_vec3_with_vec4.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_float16_type(const glsl_type *t) +try: (glsl_float16_type:=dll.glsl_float16_type).restype, glsl_float16_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_int16_type(const glsl_type *t) +try: (glsl_int16_type:=dll.glsl_int16_type).restype, glsl_int16_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_uint16_type(const glsl_type *t) +try: (glsl_uint16_type:=dll.glsl_uint16_type).restype, glsl_uint16_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_type_to_16bit(const glsl_type *old_type) +try: (glsl_type_to_16bit:=dll.glsl_type_to_16bit).restype, glsl_type_to_16bit.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_replace_vector_type(const glsl_type *t, unsigned int components) +try: (glsl_replace_vector_type:=dll.glsl_replace_vector_type).restype, glsl_replace_vector_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.c_uint32] +except AttributeError: pass + +# const glsl_type *glsl_channel_type(const glsl_type *t) +try: (glsl_channel_type:=dll.glsl_channel_type).restype, glsl_channel_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# const glsl_type *glsl_get_mul_type(const glsl_type *type_a, const glsl_type *type_b) +try: (glsl_get_mul_type:=dll.glsl_get_mul_type).restype, glsl_get_mul_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_type_get_sampler_count(const glsl_type *t) +try: (glsl_type_get_sampler_count:=dll.glsl_type_get_sampler_count).restype, glsl_type_get_sampler_count.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_type_get_texture_count(const glsl_type *t) +try: (glsl_type_get_texture_count:=dll.glsl_type_get_texture_count).restype, glsl_type_get_texture_count.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_type_get_image_count(const glsl_type *t) +try: (glsl_type_get_image_count:=dll.glsl_type_get_image_count).restype, glsl_type_get_image_count.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_count_vec4_slots(const glsl_type *t, bool is_gl_vertex_input, bool is_bindless) +try: (glsl_count_vec4_slots:=dll.glsl_count_vec4_slots).restype, glsl_count_vec4_slots.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool, ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_count_dword_slots(const glsl_type *t, bool is_bindless) +try: (glsl_count_dword_slots:=dll.glsl_count_dword_slots).restype, glsl_count_dword_slots.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_component_slots(const glsl_type *t) +try: (glsl_get_component_slots:=dll.glsl_get_component_slots).restype, glsl_get_component_slots.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_get_component_slots_aligned(const glsl_type *t, unsigned int offset) +try: (glsl_get_component_slots_aligned:=dll.glsl_get_component_slots_aligned).restype, glsl_get_component_slots_aligned.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_uint32] +except AttributeError: pass + +# unsigned int glsl_varying_count(const glsl_type *t) +try: (glsl_varying_count:=dll.glsl_varying_count).restype, glsl_varying_count.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_type_uniform_locations(const glsl_type *t) +try: (glsl_type_uniform_locations:=dll.glsl_type_uniform_locations).restype, glsl_type_uniform_locations.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_get_cl_size(const glsl_type *t) +try: (glsl_get_cl_size:=dll.glsl_get_cl_size).restype, glsl_get_cl_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# unsigned int glsl_get_cl_alignment(const glsl_type *t) +try: (glsl_get_cl_alignment:=dll.glsl_get_cl_alignment).restype, glsl_get_cl_alignment.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type)] +except AttributeError: pass + +# void glsl_get_cl_type_size_align(const glsl_type *t, unsigned int *size, unsigned int *align) +try: (glsl_get_cl_type_size_align:=dll.glsl_get_cl_type_size_align).restype, glsl_get_cl_type_size_align.argtypes = None, [ctypes.POINTER(glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# enum glsl_interface_packing glsl_get_internal_ifc_packing(const glsl_type *t, bool std430_supported) +try: (glsl_get_internal_ifc_packing:=dll.glsl_get_internal_ifc_packing).restype, glsl_get_internal_ifc_packing.argtypes = enum_glsl_interface_packing, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_std140_base_alignment(const glsl_type *t, bool row_major) +try: (glsl_get_std140_base_alignment:=dll.glsl_get_std140_base_alignment).restype, glsl_get_std140_base_alignment.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_std140_size(const glsl_type *t, bool row_major) +try: (glsl_get_std140_size:=dll.glsl_get_std140_size).restype, glsl_get_std140_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_std430_array_stride(const glsl_type *t, bool row_major) +try: (glsl_get_std430_array_stride:=dll.glsl_get_std430_array_stride).restype, glsl_get_std430_array_stride.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_std430_base_alignment(const glsl_type *t, bool row_major) +try: (glsl_get_std430_base_alignment:=dll.glsl_get_std430_base_alignment).restype, glsl_get_std430_base_alignment.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_std430_size(const glsl_type *t, bool row_major) +try: (glsl_get_std430_size:=dll.glsl_get_std430_size).restype, glsl_get_std430_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# unsigned int glsl_get_explicit_size(const glsl_type *t, bool align_to_stride) +try: (glsl_get_explicit_size:=dll.glsl_get_explicit_size).restype, glsl_get_explicit_size.argtypes = ctypes.c_uint32, [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# const glsl_type *glsl_get_explicit_std140_type(const glsl_type *t, bool row_major) +try: (glsl_get_explicit_std140_type:=dll.glsl_get_explicit_std140_type).restype, glsl_get_explicit_std140_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# const glsl_type *glsl_get_explicit_std430_type(const glsl_type *t, bool row_major) +try: (glsl_get_explicit_std430_type:=dll.glsl_get_explicit_std430_type).restype, glsl_get_explicit_std430_type.argtypes = ctypes.POINTER(glsl_type), [ctypes.POINTER(glsl_type), ctypes.c_bool] +except AttributeError: pass + +# void glsl_size_align_handle_array_and_structs(const glsl_type *type, glsl_type_size_align_func size_align, unsigned int *size, unsigned int *align) +try: (glsl_size_align_handle_array_and_structs:=dll.glsl_size_align_handle_array_and_structs).restype, glsl_size_align_handle_array_and_structs.argtypes = None, [ctypes.POINTER(glsl_type), glsl_type_size_align_func, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# void glsl_get_natural_size_align_bytes(const glsl_type *t, unsigned int *size, unsigned int *align) +try: (glsl_get_natural_size_align_bytes:=dll.glsl_get_natural_size_align_bytes).restype, glsl_get_natural_size_align_bytes.argtypes = None, [ctypes.POINTER(glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# void glsl_get_word_size_align_bytes(const glsl_type *type, unsigned int *size, unsigned int *align) +try: (glsl_get_word_size_align_bytes:=dll.glsl_get_word_size_align_bytes).restype, glsl_get_word_size_align_bytes.argtypes = None, [ctypes.POINTER(glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# void glsl_get_vec4_size_align_bytes(const glsl_type *type, unsigned int *size, unsigned int *align) +try: (glsl_get_vec4_size_align_bytes:=dll.glsl_get_vec4_size_align_bytes).restype, glsl_get_vec4_size_align_bytes.argtypes = None, [ctypes.POINTER(glsl_type), ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + +# void blob_init(struct blob *blob) +try: (blob_init:=dll.blob_init).restype, blob_init.argtypes = None, [ctypes.POINTER(struct_blob)] +except AttributeError: pass + +# void blob_init_fixed(struct blob *blob, void *data, size_t size) +try: (blob_init_fixed:=dll.blob_init_fixed).restype, blob_init_fixed.argtypes = None, [ctypes.POINTER(struct_blob), ctypes.c_void_p, size_t] +except AttributeError: pass + +# void blob_finish_get_buffer(struct blob *blob, void **buffer, size_t *size) +try: (blob_finish_get_buffer:=dll.blob_finish_get_buffer).restype, blob_finish_get_buffer.argtypes = None, [ctypes.POINTER(struct_blob), ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t)] +except AttributeError: pass + +# _Bool blob_align(struct blob *blob, size_t alignment) +try: (blob_align:=dll.blob_align).restype, blob_align.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), size_t] +except AttributeError: pass + +# _Bool blob_write_bytes(struct blob *blob, const void *bytes, size_t to_write) +try: (blob_write_bytes:=dll.blob_write_bytes).restype, blob_write_bytes.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), ctypes.c_void_p, size_t] +except AttributeError: pass + +intptr_t = ctypes.c_int64 +# intptr_t blob_reserve_bytes(struct blob *blob, size_t to_write) +try: (blob_reserve_bytes:=dll.blob_reserve_bytes).restype, blob_reserve_bytes.argtypes = intptr_t, [ctypes.POINTER(struct_blob), size_t] +except AttributeError: pass + +# intptr_t blob_reserve_uint32(struct blob *blob) +try: (blob_reserve_uint32:=dll.blob_reserve_uint32).restype, blob_reserve_uint32.argtypes = intptr_t, [ctypes.POINTER(struct_blob)] +except AttributeError: pass + +# intptr_t blob_reserve_intptr(struct blob *blob) +try: (blob_reserve_intptr:=dll.blob_reserve_intptr).restype, blob_reserve_intptr.argtypes = intptr_t, [ctypes.POINTER(struct_blob)] +except AttributeError: pass + +# _Bool blob_overwrite_bytes(struct blob *blob, size_t offset, const void *bytes, size_t to_write) +try: (blob_overwrite_bytes:=dll.blob_overwrite_bytes).restype, blob_overwrite_bytes.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), size_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# _Bool blob_write_uint8(struct blob *blob, uint8_t value) +try: (blob_write_uint8:=dll.blob_write_uint8).restype, blob_write_uint8.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), uint8_t] +except AttributeError: pass + +# _Bool blob_overwrite_uint8(struct blob *blob, size_t offset, uint8_t value) +try: (blob_overwrite_uint8:=dll.blob_overwrite_uint8).restype, blob_overwrite_uint8.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), size_t, uint8_t] +except AttributeError: pass + +# _Bool blob_write_uint16(struct blob *blob, uint16_t value) +try: (blob_write_uint16:=dll.blob_write_uint16).restype, blob_write_uint16.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), uint16_t] +except AttributeError: pass + +# _Bool blob_write_uint32(struct blob *blob, uint32_t value) +try: (blob_write_uint32:=dll.blob_write_uint32).restype, blob_write_uint32.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), uint32_t] +except AttributeError: pass + +# _Bool blob_overwrite_uint32(struct blob *blob, size_t offset, uint32_t value) +try: (blob_overwrite_uint32:=dll.blob_overwrite_uint32).restype, blob_overwrite_uint32.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), size_t, uint32_t] +except AttributeError: pass + +# _Bool blob_write_uint64(struct blob *blob, uint64_t value) +try: (blob_write_uint64:=dll.blob_write_uint64).restype, blob_write_uint64.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), uint64_t] +except AttributeError: pass + +# _Bool blob_write_intptr(struct blob *blob, intptr_t value) +try: (blob_write_intptr:=dll.blob_write_intptr).restype, blob_write_intptr.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), intptr_t] +except AttributeError: pass + +# _Bool blob_overwrite_intptr(struct blob *blob, size_t offset, intptr_t value) +try: (blob_overwrite_intptr:=dll.blob_overwrite_intptr).restype, blob_overwrite_intptr.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), size_t, intptr_t] +except AttributeError: pass + +# _Bool blob_write_string(struct blob *blob, const char *str) +try: (blob_write_string:=dll.blob_write_string).restype, blob_write_string.argtypes = ctypes.c_bool, [ctypes.POINTER(struct_blob), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# void blob_reader_init(struct blob_reader *blob, const void *data, size_t size) +try: (blob_reader_init:=dll.blob_reader_init).restype, blob_reader_init.argtypes = None, [ctypes.POINTER(struct_blob_reader), ctypes.c_void_p, size_t] +except AttributeError: pass + +# void blob_reader_align(struct blob_reader *blob, size_t alignment) +try: (blob_reader_align:=dll.blob_reader_align).restype, blob_reader_align.argtypes = None, [ctypes.POINTER(struct_blob_reader), size_t] +except AttributeError: pass + +# const void *blob_read_bytes(struct blob_reader *blob, size_t size) +try: (blob_read_bytes:=dll.blob_read_bytes).restype, blob_read_bytes.argtypes = ctypes.c_void_p, [ctypes.POINTER(struct_blob_reader), size_t] +except AttributeError: pass + +# void blob_copy_bytes(struct blob_reader *blob, void *dest, size_t size) +try: (blob_copy_bytes:=dll.blob_copy_bytes).restype, blob_copy_bytes.argtypes = None, [ctypes.POINTER(struct_blob_reader), ctypes.c_void_p, size_t] +except AttributeError: pass + +# void blob_skip_bytes(struct blob_reader *blob, size_t size) +try: (blob_skip_bytes:=dll.blob_skip_bytes).restype, blob_skip_bytes.argtypes = None, [ctypes.POINTER(struct_blob_reader), size_t] +except AttributeError: pass + +# uint8_t blob_read_uint8(struct blob_reader *blob) +try: (blob_read_uint8:=dll.blob_read_uint8).restype, blob_read_uint8.argtypes = uint8_t, [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# uint16_t blob_read_uint16(struct blob_reader *blob) +try: (blob_read_uint16:=dll.blob_read_uint16).restype, blob_read_uint16.argtypes = uint16_t, [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# uint32_t blob_read_uint32(struct blob_reader *blob) +try: (blob_read_uint32:=dll.blob_read_uint32).restype, blob_read_uint32.argtypes = uint32_t, [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# uint64_t blob_read_uint64(struct blob_reader *blob) +try: (blob_read_uint64:=dll.blob_read_uint64).restype, blob_read_uint64.argtypes = uint64_t, [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# intptr_t blob_read_intptr(struct blob_reader *blob) +try: (blob_read_intptr:=dll.blob_read_intptr).restype, blob_read_intptr.argtypes = intptr_t, [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# char *blob_read_string(struct blob_reader *blob) +try: (blob_read_string:=dll.blob_read_string).restype, blob_read_string.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(struct_blob_reader)] +except AttributeError: pass + +# void *ralloc_context(const void *ctx) +try: (ralloc_context:=dll.ralloc_context).restype, ralloc_context.argtypes = ctypes.c_void_p, [ctypes.c_void_p] +except AttributeError: pass + +# void *ralloc_size(const void *ctx, size_t size) +try: (ralloc_size:=dll.ralloc_size).restype, ralloc_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# void *rzalloc_size(const void *ctx, size_t size) +try: (rzalloc_size:=dll.rzalloc_size).restype, rzalloc_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, size_t] +except AttributeError: pass + +# void *reralloc_size(const void *ctx, void *ptr, size_t size) +try: (reralloc_size:=dll.reralloc_size).restype, reralloc_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, ctypes.c_void_p, size_t] +except AttributeError: pass + +# void *rerzalloc_size(const void *ctx, void *ptr, size_t old_size, size_t new_size) +try: (rerzalloc_size:=dll.rerzalloc_size).restype, rerzalloc_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, ctypes.c_void_p, size_t, size_t] +except AttributeError: pass + +# void *ralloc_array_size(const void *ctx, size_t size, unsigned int count) +try: (ralloc_array_size:=dll.ralloc_array_size).restype, ralloc_array_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# void *rzalloc_array_size(const void *ctx, size_t size, unsigned int count) +try: (rzalloc_array_size:=dll.rzalloc_array_size).restype, rzalloc_array_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# void *reralloc_array_size(const void *ctx, void *ptr, size_t size, unsigned int count) +try: (reralloc_array_size:=dll.reralloc_array_size).restype, reralloc_array_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, ctypes.c_void_p, size_t, ctypes.c_uint32] +except AttributeError: pass + +# void *rerzalloc_array_size(const void *ctx, void *ptr, size_t size, unsigned int old_count, unsigned int new_count) +try: (rerzalloc_array_size:=dll.rerzalloc_array_size).restype, rerzalloc_array_size.argtypes = ctypes.c_void_p, [ctypes.c_void_p, ctypes.c_void_p, size_t, ctypes.c_uint32, ctypes.c_uint32] +except AttributeError: pass + +# void ralloc_free(void *ptr) +try: (ralloc_free:=dll.ralloc_free).restype, ralloc_free.argtypes = None, [ctypes.c_void_p] +except AttributeError: pass + +# void ralloc_steal(const void *new_ctx, void *ptr) +try: (ralloc_steal:=dll.ralloc_steal).restype, ralloc_steal.argtypes = None, [ctypes.c_void_p, ctypes.c_void_p] +except AttributeError: pass + +# void ralloc_adopt(const void *new_ctx, void *old_ctx) +try: (ralloc_adopt:=dll.ralloc_adopt).restype, ralloc_adopt.argtypes = None, [ctypes.c_void_p, ctypes.c_void_p] +except AttributeError: pass + +# void *ralloc_parent(const void *ptr) +try: (ralloc_parent:=dll.ralloc_parent).restype, ralloc_parent.argtypes = ctypes.c_void_p, [ctypes.c_void_p] +except AttributeError: pass + +# void ralloc_set_destructor(const void *ptr, void (*destructor)(void *)) +try: (ralloc_set_destructor:=dll.ralloc_set_destructor).restype, ralloc_set_destructor.argtypes = None, [ctypes.c_void_p, ctypes.CFUNCTYPE(None, ctypes.c_void_p)] +except AttributeError: pass + +# void *ralloc_memdup(const void *ctx, const void *mem, size_t n) +try: (ralloc_memdup:=dll.ralloc_memdup).restype, ralloc_memdup.argtypes = ctypes.c_void_p, [ctypes.c_void_p, ctypes.c_void_p, size_t] +except AttributeError: pass + +# char *ralloc_strdup(const void *ctx, const char *str) +try: (ralloc_strdup:=dll.ralloc_strdup).restype, ralloc_strdup.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_void_p, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *ralloc_strndup(const void *ctx, const char *str, size_t n) +try: (ralloc_strndup:=dll.ralloc_strndup).restype, ralloc_strndup.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_void_p, ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# _Bool ralloc_strcat(char **dest, const char *str) +try: (ralloc_strcat:=dll.ralloc_strcat).restype, ralloc_strcat.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# _Bool ralloc_strncat(char **dest, const char *str, size_t n) +try: (ralloc_strncat:=dll.ralloc_strncat).restype, ralloc_strncat.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), size_t] +except AttributeError: pass + +# _Bool ralloc_str_append(char **dest, const char *str, size_t existing_length, size_t str_size) +try: (ralloc_str_append:=dll.ralloc_str_append).restype, ralloc_str_append.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), size_t, size_t] +except AttributeError: pass + +# char *ralloc_asprintf(const void *ctx, const char *fmt, ...) +try: (ralloc_asprintf:=dll.ralloc_asprintf).restype, ralloc_asprintf.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_void_p, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +class struct___va_list_tag(Struct): pass +struct___va_list_tag._fields_ = [ + ('gp_offset', ctypes.c_uint32), + ('fp_offset', ctypes.c_uint32), + ('overflow_arg_area', ctypes.c_void_p), + ('reg_save_area', ctypes.c_void_p), +] +va_list = (struct___va_list_tag * 1) +# char *ralloc_vasprintf(const void *ctx, const char *fmt, va_list args) +try: (ralloc_vasprintf:=dll.ralloc_vasprintf).restype, ralloc_vasprintf.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.c_void_p, ctypes.POINTER(ctypes.c_char), va_list] +except AttributeError: pass + +# _Bool ralloc_asprintf_rewrite_tail(char **str, size_t *start, const char *fmt, ...) +try: (ralloc_asprintf_rewrite_tail:=dll.ralloc_asprintf_rewrite_tail).restype, ralloc_asprintf_rewrite_tail.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# _Bool ralloc_vasprintf_rewrite_tail(char **str, size_t *start, const char *fmt, va_list args) +try: (ralloc_vasprintf_rewrite_tail:=dll.ralloc_vasprintf_rewrite_tail).restype, ralloc_vasprintf_rewrite_tail.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char), va_list] +except AttributeError: pass + +# _Bool ralloc_asprintf_append(char **str, const char *fmt, ...) +try: (ralloc_asprintf_append:=dll.ralloc_asprintf_append).restype, ralloc_asprintf_append.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# _Bool ralloc_vasprintf_append(char **str, const char *fmt, va_list args) +try: (ralloc_vasprintf_append:=dll.ralloc_vasprintf_append).restype, ralloc_vasprintf_append.argtypes = ctypes.c_bool, [ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), va_list] +except AttributeError: pass + +# size_t ralloc_total_size(const void *ptr) +try: (ralloc_total_size:=dll.ralloc_total_size).restype, ralloc_total_size.argtypes = size_t, [ctypes.c_void_p] +except AttributeError: pass + +# gc_ctx *gc_context(const void *parent) +try: (gc_context:=dll.gc_context).restype, gc_context.argtypes = ctypes.POINTER(gc_ctx), [ctypes.c_void_p] +except AttributeError: pass + +# void *gc_alloc_size(gc_ctx *ctx, size_t size, size_t alignment) +try: (gc_alloc_size:=dll.gc_alloc_size).restype, gc_alloc_size.argtypes = ctypes.c_void_p, [ctypes.POINTER(gc_ctx), size_t, size_t] +except AttributeError: pass + +# void *gc_zalloc_size(gc_ctx *ctx, size_t size, size_t alignment) +try: (gc_zalloc_size:=dll.gc_zalloc_size).restype, gc_zalloc_size.argtypes = ctypes.c_void_p, [ctypes.POINTER(gc_ctx), size_t, size_t] +except AttributeError: pass + +# void gc_free(void *ptr) +try: (gc_free:=dll.gc_free).restype, gc_free.argtypes = None, [ctypes.c_void_p] +except AttributeError: pass + +# gc_ctx *gc_get_context(void *ptr) +try: (gc_get_context:=dll.gc_get_context).restype, gc_get_context.argtypes = ctypes.POINTER(gc_ctx), [ctypes.c_void_p] +except AttributeError: pass + +# void gc_sweep_start(gc_ctx *ctx) +try: (gc_sweep_start:=dll.gc_sweep_start).restype, gc_sweep_start.argtypes = None, [ctypes.POINTER(gc_ctx)] +except AttributeError: pass + +# void gc_mark_live(gc_ctx *ctx, const void *mem) +try: (gc_mark_live:=dll.gc_mark_live).restype, gc_mark_live.argtypes = None, [ctypes.POINTER(gc_ctx), ctypes.c_void_p] +except AttributeError: pass + +# void gc_sweep_end(gc_ctx *ctx) +try: (gc_sweep_end:=dll.gc_sweep_end).restype, gc_sweep_end.argtypes = None, [ctypes.POINTER(gc_ctx)] +except AttributeError: pass + +class struct_linear_ctx(Struct): pass +linear_ctx = struct_linear_ctx +# void *linear_alloc_child(linear_ctx *ctx, unsigned int size) +try: (linear_alloc_child:=dll.linear_alloc_child).restype, linear_alloc_child.argtypes = ctypes.c_void_p, [ctypes.POINTER(linear_ctx), ctypes.c_uint32] +except AttributeError: pass + +class linear_opts(Struct): pass +linear_opts._fields_ = [ + ('min_buffer_size', ctypes.c_uint32), +] +# linear_ctx *linear_context(void *ralloc_ctx) +try: (linear_context:=dll.linear_context).restype, linear_context.argtypes = ctypes.POINTER(linear_ctx), [ctypes.c_void_p] +except AttributeError: pass + +# linear_ctx *linear_context_with_opts(void *ralloc_ctx, const linear_opts *opts) +try: (linear_context_with_opts:=dll.linear_context_with_opts).restype, linear_context_with_opts.argtypes = ctypes.POINTER(linear_ctx), [ctypes.c_void_p, ctypes.POINTER(linear_opts)] +except AttributeError: pass + +# void *linear_zalloc_child(linear_ctx *ctx, unsigned int size) +try: (linear_zalloc_child:=dll.linear_zalloc_child).restype, linear_zalloc_child.argtypes = ctypes.c_void_p, [ctypes.POINTER(linear_ctx), ctypes.c_uint32] +except AttributeError: pass + +# void linear_free_context(linear_ctx *ctx) +try: (linear_free_context:=dll.linear_free_context).restype, linear_free_context.argtypes = None, [ctypes.POINTER(linear_ctx)] +except AttributeError: pass + +# void ralloc_steal_linear_context(void *new_ralloc_ctx, linear_ctx *ctx) +try: (ralloc_steal_linear_context:=dll.ralloc_steal_linear_context).restype, ralloc_steal_linear_context.argtypes = None, [ctypes.c_void_p, ctypes.POINTER(linear_ctx)] +except AttributeError: pass + +# void *ralloc_parent_of_linear_context(linear_ctx *ctx) +try: (ralloc_parent_of_linear_context:=dll.ralloc_parent_of_linear_context).restype, ralloc_parent_of_linear_context.argtypes = ctypes.c_void_p, [ctypes.POINTER(linear_ctx)] +except AttributeError: pass + +# void *linear_alloc_child_array(linear_ctx *ctx, size_t size, unsigned int count) +try: (linear_alloc_child_array:=dll.linear_alloc_child_array).restype, linear_alloc_child_array.argtypes = ctypes.c_void_p, [ctypes.POINTER(linear_ctx), size_t, ctypes.c_uint32] +except AttributeError: pass + +# void *linear_zalloc_child_array(linear_ctx *ctx, size_t size, unsigned int count) +try: (linear_zalloc_child_array:=dll.linear_zalloc_child_array).restype, linear_zalloc_child_array.argtypes = ctypes.c_void_p, [ctypes.POINTER(linear_ctx), size_t, ctypes.c_uint32] +except AttributeError: pass + +# char *linear_strdup(linear_ctx *ctx, const char *str) +try: (linear_strdup:=dll.linear_strdup).restype, linear_strdup.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *linear_asprintf(linear_ctx *ctx, const char *fmt, ...) +try: (linear_asprintf:=dll.linear_asprintf).restype, linear_asprintf.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# char *linear_vasprintf(linear_ctx *ctx, const char *fmt, va_list args) +try: (linear_vasprintf:=dll.linear_vasprintf).restype, linear_vasprintf.argtypes = ctypes.POINTER(ctypes.c_char), [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.c_char), va_list] +except AttributeError: pass + +# _Bool linear_asprintf_append(linear_ctx *ctx, char **str, const char *fmt, ...) +try: (linear_asprintf_append:=dll.linear_asprintf_append).restype, linear_asprintf_append.argtypes = ctypes.c_bool, [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# _Bool linear_vasprintf_append(linear_ctx *ctx, char **str, const char *fmt, va_list args) +try: (linear_vasprintf_append:=dll.linear_vasprintf_append).restype, linear_vasprintf_append.argtypes = ctypes.c_bool, [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char), va_list] +except AttributeError: pass + +# _Bool linear_asprintf_rewrite_tail(linear_ctx *ctx, char **str, size_t *start, const char *fmt, ...) +try: (linear_asprintf_rewrite_tail:=dll.linear_asprintf_rewrite_tail).restype, linear_asprintf_rewrite_tail.argtypes = ctypes.c_bool, [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# _Bool linear_vasprintf_rewrite_tail(linear_ctx *ctx, char **str, size_t *start, const char *fmt, va_list args) +try: (linear_vasprintf_rewrite_tail:=dll.linear_vasprintf_rewrite_tail).restype, linear_vasprintf_rewrite_tail.argtypes = ctypes.c_bool, [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(size_t), ctypes.POINTER(ctypes.c_char), va_list] +except AttributeError: pass + +# _Bool linear_strcat(linear_ctx *ctx, char **dest, const char *str) +try: (linear_strcat:=dll.linear_strcat).restype, linear_strcat.argtypes = ctypes.c_bool, [ctypes.POINTER(linear_ctx), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +_anonenum7 = CEnum(ctypes.c_uint32) +RALLOC_PRINT_INFO_SUMMARY_ONLY = _anonenum7.define('RALLOC_PRINT_INFO_SUMMARY_ONLY', 1) + +# void ralloc_print_info(FILE *f, const void *p, unsigned int flags) +try: (ralloc_print_info:=dll.ralloc_print_info).restype, ralloc_print_info.argtypes = None, [ctypes.POINTER(FILE), ctypes.c_void_p, ctypes.c_uint32] +except AttributeError: pass + +NIR_DEBUG_CLONE = (1 << 0) +NIR_DEBUG_SERIALIZE = (1 << 1) +NIR_DEBUG_NOVALIDATE = (1 << 2) +NIR_DEBUG_EXTENDED_VALIDATION = (1 << 3) +NIR_DEBUG_TGSI = (1 << 4) +NIR_DEBUG_PRINT_VS = (1 << 5) +NIR_DEBUG_PRINT_TCS = (1 << 6) +NIR_DEBUG_PRINT_TES = (1 << 7) +NIR_DEBUG_PRINT_GS = (1 << 8) +NIR_DEBUG_PRINT_FS = (1 << 9) +NIR_DEBUG_PRINT_CS = (1 << 10) +NIR_DEBUG_PRINT_TS = (1 << 11) +NIR_DEBUG_PRINT_MS = (1 << 12) +NIR_DEBUG_PRINT_RGS = (1 << 13) +NIR_DEBUG_PRINT_AHS = (1 << 14) +NIR_DEBUG_PRINT_CHS = (1 << 15) +NIR_DEBUG_PRINT_MHS = (1 << 16) +NIR_DEBUG_PRINT_IS = (1 << 17) +NIR_DEBUG_PRINT_CBS = (1 << 18) +NIR_DEBUG_PRINT_KS = (1 << 19) +NIR_DEBUG_PRINT_NO_INLINE_CONSTS = (1 << 20) +NIR_DEBUG_PRINT_INTERNAL = (1 << 21) +NIR_DEBUG_PRINT_PASS_FLAGS = (1 << 22) +NIR_DEBUG_INVALIDATE_METADATA = (1 << 23) +NIR_DEBUG_PRINT_STRUCT_DECLS = (1 << 24) +NIR_DEBUG_PRINT = (NIR_DEBUG_PRINT_VS | NIR_DEBUG_PRINT_TCS | NIR_DEBUG_PRINT_TES | NIR_DEBUG_PRINT_GS | NIR_DEBUG_PRINT_FS | NIR_DEBUG_PRINT_CS | NIR_DEBUG_PRINT_TS | NIR_DEBUG_PRINT_MS | NIR_DEBUG_PRINT_RGS | NIR_DEBUG_PRINT_AHS | NIR_DEBUG_PRINT_CHS | NIR_DEBUG_PRINT_MHS | NIR_DEBUG_PRINT_IS | NIR_DEBUG_PRINT_CBS | NIR_DEBUG_PRINT_KS) +NIR_FALSE = 0 +NIR_TRUE = (~0) +NIR_MAX_VEC_COMPONENTS = 16 +NIR_MAX_MATRIX_COLUMNS = 4 +NIR_STREAM_PACKED = (1 << 8) +NIR_VARIABLE_NO_INDEX = ~0 +nir_foreach_variable_in_list = lambda var,var_list: foreach_list_typed(nir_variable, var, node, var_list) +nir_foreach_variable_in_list_safe = lambda var,var_list: foreach_list_typed_safe(nir_variable, var, node, var_list) +nir_foreach_shader_in_variable = lambda var,shader: nir_foreach_variable_with_modes(var, shader, nir_var_shader_in) +nir_foreach_shader_in_variable_safe = lambda var,shader: nir_foreach_variable_with_modes_safe(var, shader, nir_var_shader_in) +nir_foreach_shader_out_variable = lambda var,shader: nir_foreach_variable_with_modes(var, shader, nir_var_shader_out) +nir_foreach_shader_out_variable_safe = lambda var,shader: nir_foreach_variable_with_modes_safe(var, shader, nir_var_shader_out) +nir_foreach_uniform_variable = lambda var,shader: nir_foreach_variable_with_modes(var, shader, nir_var_uniform) +nir_foreach_uniform_variable_safe = lambda var,shader: nir_foreach_variable_with_modes_safe(var, shader, nir_var_uniform) +nir_foreach_image_variable = lambda var,shader: nir_foreach_variable_with_modes(var, shader, nir_var_image) +nir_foreach_image_variable_safe = lambda var,shader: nir_foreach_variable_with_modes_safe(var, shader, nir_var_image) +NIR_SRC_PARENT_IS_IF = (0x1) +NIR_ALU_MAX_INPUTS = NIR_MAX_VEC_COMPONENTS +NIR_INTRINSIC_MAX_CONST_INDEX = 8 +NIR_ALIGN_MUL_MAX = 0x40000000 +NIR_INTRINSIC_MAX_INPUTS = 11 +nir_log_shadere = lambda s: nir_log_shader_annotated_tagged(MESA_LOG_ERROR, (MESA_LOG_TAG), (s), NULL) +nir_log_shaderw = lambda s: nir_log_shader_annotated_tagged(MESA_LOG_WARN, (MESA_LOG_TAG), (s), NULL) +nir_log_shaderi = lambda s: nir_log_shader_annotated_tagged(MESA_LOG_INFO, (MESA_LOG_TAG), (s), NULL) +nir_log_shader_annotated = lambda s,annotations: nir_log_shader_annotated_tagged(MESA_LOG_ERROR, (MESA_LOG_TAG), (s), annotations) +NIR_STRINGIZE = lambda x: NIR_STRINGIZE_INNER(x) +NVIDIA_VENDOR_ID = 0x10de +NAK_SUBGROUP_SIZE = 32 +NAK_QMD_ALIGN_B = 256 +NAK_MAX_QMD_SIZE_B = 384 +NAK_MAX_QMD_DWORDS = (NAK_MAX_QMD_SIZE_B / 4) +LP_MAX_VECTOR_WIDTH = 512 +LP_MIN_VECTOR_ALIGN = 64 +LP_MAX_VECTOR_LENGTH = (LP_MAX_VECTOR_WIDTH/8) +LP_RESV_FUNC_ARGS = 2 +LP_JIT_TEXTURE_SAMPLE_STRIDE = 15 +lp_jit_resources_constants = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_RES_CONSTANTS, "constants") +lp_jit_resources_ssbos = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_RES_SSBOS, "ssbos") +lp_jit_resources_textures = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_RES_TEXTURES, "textures") +lp_jit_resources_samplers = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_RES_SAMPLERS, "samplers") +lp_jit_resources_images = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_RES_IMAGES, "images") +lp_jit_vertex_header_id = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_VERTEX_HEADER_VERTEX_ID, "id") +lp_jit_vertex_header_clip_pos = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_VERTEX_HEADER_CLIP_POS, "clip_pos") +lp_jit_vertex_header_data = lambda _gallivm,_type,_ptr: lp_build_struct__get_ptr2(_gallivm, _type, _ptr, LP_JIT_VERTEX_HEADER_DATA, "data") +LP_MAX_TEX_FUNC_ARGS = 32 +gc_alloc = lambda ctx,type,count: gc_alloc_size(ctx, sizeof(type) * (count), alignof(type)) +gc_zalloc = lambda ctx,type,count: gc_zalloc_size(ctx, sizeof(type) * (count), alignof(type)) +gc_alloc_zla = lambda ctx,type,type2,count: gc_alloc_size(ctx, sizeof(type) + sizeof(type2) * (count), MAX2(alignof(type), alignof(type2))) +gc_zalloc_zla = lambda ctx,type,type2,count: gc_zalloc_size(ctx, sizeof(type) + sizeof(type2) * (count), MAX2(alignof(type), alignof(type2))) +DECLARE_RALLOC_CXX_OPERATORS = lambda type: DECLARE_RALLOC_CXX_OPERATORS_TEMPLATE(type, ralloc_size) +DECLARE_RZALLOC_CXX_OPERATORS = lambda type: DECLARE_RALLOC_CXX_OPERATORS_TEMPLATE(type, rzalloc_size) +DECLARE_LINEAR_ALLOC_CXX_OPERATORS = lambda type: DECLARE_LINEAR_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_alloc_child) +DECLARE_LINEAR_ZALLOC_CXX_OPERATORS = lambda type: DECLARE_LINEAR_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_zalloc_child) +lvp_nir_options = gzip.decompress(base64.b64decode("H4sIAAAAAAAAA2NgZGRkYGAAkYxgCsQFsxigwgwQBoxmhCqFq2WEKwIrAEGIkQxoAEMALwCqVsCiGUwLMHA0QPn29nBJkswHANb8YpH4AAAA")) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/nv.py b/tinygrad/runtime/autogen/nv.py new file mode 100644 index 0000000000..9d88c3eaf1 --- /dev/null +++ b/tinygrad/runtime/autogen/nv.py @@ -0,0 +1,4837 @@ +# mypy: ignore-errors +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class MCTP_HEADER(Struct): pass +NvU32 = ctypes.c_uint32 +NvU8 = ctypes.c_ubyte +NvU16 = ctypes.c_uint16 +MCTP_HEADER._packed_ = True +MCTP_HEADER._fields_ = [ + ('constBlob', NvU32), + ('msgType', NvU8), + ('vendorId', NvU16), +] +class NVDM_PAYLOAD_COT(Struct): pass +NvU64 = ctypes.c_uint64 +NVDM_PAYLOAD_COT._packed_ = True +NVDM_PAYLOAD_COT._fields_ = [ + ('version', NvU16), + ('size', NvU16), + ('gspFmcSysmemOffset', NvU64), + ('frtsSysmemOffset', NvU64), + ('frtsSysmemSize', NvU32), + ('frtsVidmemOffset', NvU64), + ('frtsVidmemSize', NvU32), + ('hash384', (NvU32 * 12)), + ('publicKey', (NvU32 * 96)), + ('signature', (NvU32 * 96)), + ('gspBootArgsSysmemOffset', NvU64), +] +class MESSAGE_QUEUE_INIT_ARGUMENTS(Struct): pass +NvLength = ctypes.c_uint64 +MESSAGE_QUEUE_INIT_ARGUMENTS._fields_ = [ + ('sharedMemPhysAddr', NvU64), + ('pageTableEntryCount', NvU32), + ('cmdQueueOffset', NvLength), + ('statQueueOffset', NvLength), +] +class GSP_SR_INIT_ARGUMENTS(Struct): pass +NvBool = ctypes.c_ubyte +GSP_SR_INIT_ARGUMENTS._fields_ = [ + ('oldLevel', NvU32), + ('flags', NvU32), + ('bInPMTransition', NvBool), +] +class GSP_ARGUMENTS_CACHED(Struct): pass +class GSP_ARGUMENTS_CACHED_profilerArgs(Struct): pass +GSP_ARGUMENTS_CACHED_profilerArgs._fields_ = [ + ('pa', NvU64), + ('size', NvU64), +] +GSP_ARGUMENTS_CACHED._fields_ = [ + ('messageQueueInitArguments', MESSAGE_QUEUE_INIT_ARGUMENTS), + ('srInitArguments', GSP_SR_INIT_ARGUMENTS), + ('gpuInstance', NvU32), + ('bDmemStack', NvBool), + ('profilerArgs', GSP_ARGUMENTS_CACHED_profilerArgs), +] +GSP_DMA_TARGET = CEnum(ctypes.c_uint32) +GSP_DMA_TARGET_LOCAL_FB = GSP_DMA_TARGET.define('GSP_DMA_TARGET_LOCAL_FB', 0) +GSP_DMA_TARGET_COHERENT_SYSTEM = GSP_DMA_TARGET.define('GSP_DMA_TARGET_COHERENT_SYSTEM', 1) +GSP_DMA_TARGET_NONCOHERENT_SYSTEM = GSP_DMA_TARGET.define('GSP_DMA_TARGET_NONCOHERENT_SYSTEM', 2) +GSP_DMA_TARGET_COUNT = GSP_DMA_TARGET.define('GSP_DMA_TARGET_COUNT', 3) + +class struct_GSP_FMC_INIT_PARAMS(Struct): pass +struct_GSP_FMC_INIT_PARAMS._fields_ = [ + ('regkeys', NvU32), +] +GSP_FMC_INIT_PARAMS = struct_GSP_FMC_INIT_PARAMS +class struct_GSP_ACR_BOOT_GSP_RM_PARAMS(Struct): pass +struct_GSP_ACR_BOOT_GSP_RM_PARAMS._fields_ = [ + ('target', GSP_DMA_TARGET), + ('gspRmDescSize', NvU32), + ('gspRmDescOffset', NvU64), + ('wprCarveoutOffset', NvU64), + ('wprCarveoutSize', NvU32), + ('bIsGspRmBoot', NvBool), +] +GSP_ACR_BOOT_GSP_RM_PARAMS = struct_GSP_ACR_BOOT_GSP_RM_PARAMS +class struct_GSP_RM_PARAMS(Struct): pass +struct_GSP_RM_PARAMS._fields_ = [ + ('target', GSP_DMA_TARGET), + ('bootArgsOffset', NvU64), +] +GSP_RM_PARAMS = struct_GSP_RM_PARAMS +class struct_GSP_SPDM_PARAMS(Struct): pass +struct_GSP_SPDM_PARAMS._fields_ = [ + ('target', GSP_DMA_TARGET), + ('payloadBufferOffset', NvU64), + ('payloadBufferSize', NvU32), +] +GSP_SPDM_PARAMS = struct_GSP_SPDM_PARAMS +class struct_GSP_FMC_BOOT_PARAMS(Struct): pass +struct_GSP_FMC_BOOT_PARAMS._fields_ = [ + ('initParams', GSP_FMC_INIT_PARAMS), + ('bootGspRmParams', GSP_ACR_BOOT_GSP_RM_PARAMS), + ('gspRmParams', GSP_RM_PARAMS), + ('gspSpdmParams', GSP_SPDM_PARAMS), +] +GSP_FMC_BOOT_PARAMS = struct_GSP_FMC_BOOT_PARAMS +class GspFwWprMeta(Struct): pass +class GspFwWprMeta_0(ctypes.Union): pass +class GspFwWprMeta_0_0(Struct): pass +GspFwWprMeta_0_0._fields_ = [ + ('sysmemAddrOfSignature', NvU64), + ('sizeOfSignature', NvU64), +] +class GspFwWprMeta_0_1(Struct): pass +GspFwWprMeta_0_1._fields_ = [ + ('gspFwHeapFreeListWprOffset', NvU32), + ('unused0', NvU32), + ('unused1', NvU64), +] +GspFwWprMeta_0._anonymous_ = ['_0', '_1'] +GspFwWprMeta_0._fields_ = [ + ('_0', GspFwWprMeta_0_0), + ('_1', GspFwWprMeta_0_1), +] +class GspFwWprMeta_1(ctypes.Union): pass +class GspFwWprMeta_1_0(Struct): pass +GspFwWprMeta_1_0._fields_ = [ + ('partitionRpcAddr', NvU64), + ('partitionRpcRequestOffset', NvU16), + ('partitionRpcReplyOffset', NvU16), + ('elfCodeOffset', NvU32), + ('elfDataOffset', NvU32), + ('elfCodeSize', NvU32), + ('elfDataSize', NvU32), + ('lsUcodeVersion', NvU32), +] +class GspFwWprMeta_1_1(Struct): pass +GspFwWprMeta_1_1._fields_ = [ + ('partitionRpcPadding', (NvU32 * 4)), + ('sysmemAddrOfCrashReportQueue', NvU64), + ('sizeOfCrashReportQueue', NvU32), + ('lsUcodeVersionPadding', (NvU32 * 1)), +] +GspFwWprMeta_1._anonymous_ = ['_0', '_1'] +GspFwWprMeta_1._fields_ = [ + ('_0', GspFwWprMeta_1_0), + ('_1', GspFwWprMeta_1_1), +] +GspFwWprMeta._anonymous_ = ['_0', '_1'] +GspFwWprMeta._fields_ = [ + ('magic', NvU64), + ('revision', NvU64), + ('sysmemAddrOfRadix3Elf', NvU64), + ('sizeOfRadix3Elf', NvU64), + ('sysmemAddrOfBootloader', NvU64), + ('sizeOfBootloader', NvU64), + ('bootloaderCodeOffset', NvU64), + ('bootloaderDataOffset', NvU64), + ('bootloaderManifestOffset', NvU64), + ('_0', GspFwWprMeta_0), + ('gspFwRsvdStart', NvU64), + ('nonWprHeapOffset', NvU64), + ('nonWprHeapSize', NvU64), + ('gspFwWprStart', NvU64), + ('gspFwHeapOffset', NvU64), + ('gspFwHeapSize', NvU64), + ('gspFwOffset', NvU64), + ('bootBinOffset', NvU64), + ('frtsOffset', NvU64), + ('frtsSize', NvU64), + ('gspFwWprEnd', NvU64), + ('fbSize', NvU64), + ('vgaWorkspaceOffset', NvU64), + ('vgaWorkspaceSize', NvU64), + ('bootCount', NvU64), + ('_1', GspFwWprMeta_1), + ('gspFwHeapVfPartitionCount', NvU8), + ('flags', NvU8), + ('padding', (NvU8 * 2)), + ('pmuReservedSize', NvU32), + ('verified', NvU64), +] +class GspFwHeapFreeRegion(Struct): pass +GspFwHeapFreeRegion._fields_ = [ + ('offs', NvU32), + ('length', NvU32), +] +class GspFwHeapFreeList(Struct): pass +GspFwHeapFreeList._fields_ = [ + ('magic', NvU64), + ('nregions', NvU32), + ('regions', (GspFwHeapFreeRegion * 128)), +] +class GspFwSRMeta(Struct): pass +GspFwSRMeta._fields_ = [ + ('magic', NvU64), + ('revision', NvU64), + ('sysmemAddrOfSuspendResumeData', NvU64), + ('sizeOfSuspendResumeData', NvU64), + ('internal', (NvU32 * 32)), + ('flags', NvU32), + ('subrevision', NvU32), + ('padding', (NvU32 * 22)), +] +class RM_RISCV_UCODE_DESC(Struct): pass +RM_RISCV_UCODE_DESC._fields_ = [ + ('version', NvU32), + ('bootloaderOffset', NvU32), + ('bootloaderSize', NvU32), + ('bootloaderParamOffset', NvU32), + ('bootloaderParamSize', NvU32), + ('riscvElfOffset', NvU32), + ('riscvElfSize', NvU32), + ('appVersion', NvU32), + ('manifestOffset', NvU32), + ('manifestSize', NvU32), + ('monitorDataOffset', NvU32), + ('monitorDataSize', NvU32), + ('monitorCodeOffset', NvU32), + ('monitorCodeSize', NvU32), + ('bIsMonitorEnabled', NvU32), + ('swbromCodeOffset', NvU32), + ('swbromCodeSize', NvU32), + ('swbromDataOffset', NvU32), + ('swbromDataSize', NvU32), + ('fbReservedSize', NvU32), + ('bSignedAsCode', NvU32), +] +RPC_GR_BUFFER_TYPE = CEnum(ctypes.c_uint32) +RPC_GR_BUFFER_TYPE_GRAPHICS = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS', 0) +RPC_GR_BUFFER_TYPE_GRAPHICS_ZCULL = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_ZCULL', 1) +RPC_GR_BUFFER_TYPE_GRAPHICS_GRAPHICS_PM = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_GRAPHICS_PM', 2) +RPC_GR_BUFFER_TYPE_COMPUTE_PREEMPT = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_COMPUTE_PREEMPT', 3) +RPC_GR_BUFFER_TYPE_GRAPHICS_PATCH = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_PATCH', 4) +RPC_GR_BUFFER_TYPE_GRAPHICS_BUNDLE_CB = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_BUNDLE_CB', 5) +RPC_GR_BUFFER_TYPE_GRAPHICS_PAGEPOOL_GLOBAL = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_PAGEPOOL_GLOBAL', 6) +RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB', 7) +RPC_GR_BUFFER_TYPE_GRAPHICS_RTV_CB_GLOBAL = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_RTV_CB_GLOBAL', 8) +RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_POOL = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_POOL', 9) +RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_CTRL_BLK = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_CTRL_BLK', 10) +RPC_GR_BUFFER_TYPE_GRAPHICS_FECS_EVENT = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_FECS_EVENT', 11) +RPC_GR_BUFFER_TYPE_GRAPHICS_PRIV_ACCESS_MAP = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_PRIV_ACCESS_MAP', 12) +RPC_GR_BUFFER_TYPE_GRAPHICS_MAX = RPC_GR_BUFFER_TYPE.define('RPC_GR_BUFFER_TYPE_GRAPHICS_MAX', 13) + +FECS_ERROR_EVENT_TYPE = CEnum(ctypes.c_uint32) +FECS_ERROR_EVENT_TYPE_NONE = FECS_ERROR_EVENT_TYPE.define('FECS_ERROR_EVENT_TYPE_NONE', 0) +FECS_ERROR_EVENT_TYPE_BUFFER_RESET_REQUIRED = FECS_ERROR_EVENT_TYPE.define('FECS_ERROR_EVENT_TYPE_BUFFER_RESET_REQUIRED', 1) +FECS_ERROR_EVENT_TYPE_BUFFER_FULL = FECS_ERROR_EVENT_TYPE.define('FECS_ERROR_EVENT_TYPE_BUFFER_FULL', 2) +FECS_ERROR_EVENT_TYPE_MAX = FECS_ERROR_EVENT_TYPE.define('FECS_ERROR_EVENT_TYPE_MAX', 3) + +NV_RPC_UPDATE_PDE_BAR_TYPE = CEnum(ctypes.c_uint32) +NV_RPC_UPDATE_PDE_BAR_1 = NV_RPC_UPDATE_PDE_BAR_TYPE.define('NV_RPC_UPDATE_PDE_BAR_1', 0) +NV_RPC_UPDATE_PDE_BAR_2 = NV_RPC_UPDATE_PDE_BAR_TYPE.define('NV_RPC_UPDATE_PDE_BAR_2', 1) +NV_RPC_UPDATE_PDE_BAR_INVALID = NV_RPC_UPDATE_PDE_BAR_TYPE.define('NV_RPC_UPDATE_PDE_BAR_INVALID', 2) + +class struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS(Struct): pass +struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS._fields_ = [ + ('headIndex', NvU32), + ('maxHResolution', NvU32), + ('maxVResolution', NvU32), +] +VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS = struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS +class struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS(Struct): pass +struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS._fields_ = [ + ('numHeads', NvU32), + ('maxNumHeads', NvU32), +] +VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS = struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS +GPU_RECOVERY_EVENT_TYPE = CEnum(ctypes.c_uint32) +GPU_RECOVERY_EVENT_TYPE_REFRESH = GPU_RECOVERY_EVENT_TYPE.define('GPU_RECOVERY_EVENT_TYPE_REFRESH', 0) +GPU_RECOVERY_EVENT_TYPE_GPU_DRAIN_P2P = GPU_RECOVERY_EVENT_TYPE.define('GPU_RECOVERY_EVENT_TYPE_GPU_DRAIN_P2P', 1) +GPU_RECOVERY_EVENT_TYPE_SYS_REBOOT = GPU_RECOVERY_EVENT_TYPE.define('GPU_RECOVERY_EVENT_TYPE_SYS_REBOOT', 2) + +rpc_fns = CEnum(ctypes.c_uint32) +NV_VGPU_MSG_FUNCTION_NOP = rpc_fns.define('NV_VGPU_MSG_FUNCTION_NOP', 0) +NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO', 1) +NV_VGPU_MSG_FUNCTION_ALLOC_ROOT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_ROOT', 2) +NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE', 3) +NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY', 4) +NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA', 5) +NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA', 6) +NV_VGPU_MSG_FUNCTION_MAP_MEMORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_MAP_MEMORY', 7) +NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA', 8) +NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT', 9) +NV_VGPU_MSG_FUNCTION_FREE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_FREE', 10) +NV_VGPU_MSG_FUNCTION_LOG = rpc_fns.define('NV_VGPU_MSG_FUNCTION_LOG', 11) +NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM', 12) +NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY', 13) +NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA', 14) +NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA', 15) +NV_VGPU_MSG_FUNCTION_GET_EDID = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_EDID', 16) +NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL', 17) +NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT', 18) +NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE', 19) +NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY', 20) +NV_VGPU_MSG_FUNCTION_DUP_OBJECT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DUP_OBJECT', 21) +NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS', 22) +NV_VGPU_MSG_FUNCTION_ALLOC_EVENT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_EVENT', 23) +NV_VGPU_MSG_FUNCTION_SEND_EVENT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SEND_EVENT', 24) +NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL', 25) +NV_VGPU_MSG_FUNCTION_DMA_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DMA_CONTROL', 26) +NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM', 27) +NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE', 28) +NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA', 29) +NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT', 30) +NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT', 31) +NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE', 32) +NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL', 33) +NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API = rpc_fns.define('NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API', 34) +NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ', 35) +NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE', 36) +NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA', 37) +NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT', 38) +NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO', 39) +NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE', 40) +NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO', 41) +NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO', 42) +NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY', 43) +NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY', 44) +NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES', 45) +NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE', 46) +NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER', 47) +NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE', 48) +NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA', 49) +NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS', 50) +NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO', 51) +NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM', 52) +NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2', 53) +NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY', 54) +NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO', 55) +NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES', 56) +NV_VGPU_MSG_FUNCTION_RESERVED_57 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RESERVED_57', 57) +NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT', 58) +NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE', 59) +NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION', 60) +NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES', 61) +NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY', 62) +NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32', 63) +NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT', 64) +NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO', 65) +NV_VGPU_MSG_FUNCTION_RMFS_INIT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RMFS_INIT', 66) +NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE', 67) +NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP', 68) +NV_VGPU_MSG_FUNCTION_RMFS_TEST = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RMFS_TEST', 69) +NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE', 70) +NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD', 71) +NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO', 72) +NV_VGPU_MSG_FUNCTION_SET_REGISTRY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_REGISTRY', 73) +NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU', 74) +NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION', 75) +NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL', 76) +NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2', 77) +NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT', 78) +NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY', 79) +NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO', 80) +NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER', 81) +NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER', 82) +NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER', 83) +NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER', 84) +NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE', 85) +NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO', 86) +NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO', 87) +NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL', 88) +NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL', 89) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT', 90) +NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO', 91) +NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST', 92) +NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL', 93) +NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE', 94) +NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR', 95) +NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR', 96) +NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE', 97) +NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE', 98) +NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT', 99) +NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS', 100) +NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL', 101) +NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL', 102) +NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC', 103) +NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2', 104) +NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT', 105) +NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY', 106) +NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS', 107) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES', 108) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES', 109) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK', 110) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX', 111) +NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND', 112) +NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE', 113) +NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND', 114) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX', 115) +NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES', 116) +NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT', 117) +NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES', 118) +NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS', 119) +NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE', 120) +NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK', 121) +NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY', 122) +NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK', 123) +NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS', 124) +NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS', 125) +NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX', 126) +NV_VGPU_MSG_FUNCTION_RESERVED_0 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RESERVED_0', 127) +NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC', 128) +NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY', 129) +NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS', 130) +NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES', 131) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT', 132) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT', 133) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS', 134) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG', 135) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE', 136) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE', 137) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG', 138) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE', 139) +NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM', 140) +NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT', 141) +NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2', 142) +NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES', 143) +NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO', 144) +NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES', 145) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX', 146) +NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO', 147) +NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO', 148) +NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL', 149) +NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE', 150) +NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS', 151) +NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL', 152) +NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM', 153) +NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ', 154) +NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB', 155) +NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO', 156) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP', 157) +NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE', 158) +NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE', 159) +NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE', 160) +NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY', 161) +NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP', 162) +NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP', 163) +NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM', 164) +NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES', 165) +NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION', 166) +NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL', 167) +NV_VGPU_MSG_FUNCTION_DCE_RM_INIT = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DCE_RM_INIT', 168) +NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER', 169) +NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET', 170) +NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND', 171) +NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2', 172) +NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM', 173) +NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE', 174) +NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS', 175) +NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE', 176) +NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO', 177) +NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS', 178) +NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE', 179) +NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS', 180) +NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA', 181) +NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA', 182) +NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED', 183) +NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE', 184) +NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE', 185) +NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN', 186) +NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX', 187) +NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION = rpc_fns.define('NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION', 188) +NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK', 189) +NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER', 190) +NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS', 191) +NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING', 192) +NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING', 193) +NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK', 194) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS', 195) +NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS', 196) +NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS', 197) +NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS', 198) +NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER', 199) +NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB = rpc_fns.define('NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB', 200) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS', 201) +NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK = rpc_fns.define('NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK', 202) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG', 203) +NV_VGPU_MSG_FUNCTION_RM_API_CONTROL = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RM_API_CONTROL', 204) +NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE', 205) +NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA', 206) +NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA', 207) +NV_VGPU_MSG_FUNCTION_RESERVED_208 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_RESERVED_208', 208) +NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2 = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2', 209) +NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS', 210) +NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA', 211) +NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO = rpc_fns.define('NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO', 212) +NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE', 213) +NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR', 214) +NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS', 215) +NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS', 216) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG', 217) +NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG', 218) +NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES', 219) +NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES', 220) +NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF', 221) +NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF = rpc_fns.define('NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF', 222) +NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS = rpc_fns.define('NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS', 223) + +rpc_events = CEnum(ctypes.c_uint32) +NV_VGPU_MSG_EVENT_FIRST_EVENT = rpc_events.define('NV_VGPU_MSG_EVENT_FIRST_EVENT', 4096) +NV_VGPU_MSG_EVENT_GSP_INIT_DONE = rpc_events.define('NV_VGPU_MSG_EVENT_GSP_INIT_DONE', 4097) +NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER = rpc_events.define('NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER', 4098) +NV_VGPU_MSG_EVENT_POST_EVENT = rpc_events.define('NV_VGPU_MSG_EVENT_POST_EVENT', 4099) +NV_VGPU_MSG_EVENT_RC_TRIGGERED = rpc_events.define('NV_VGPU_MSG_EVENT_RC_TRIGGERED', 4100) +NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED = rpc_events.define('NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED', 4101) +NV_VGPU_MSG_EVENT_OS_ERROR_LOG = rpc_events.define('NV_VGPU_MSG_EVENT_OS_ERROR_LOG', 4102) +NV_VGPU_MSG_EVENT_RG_LINE_INTR = rpc_events.define('NV_VGPU_MSG_EVENT_RG_LINE_INTR', 4103) +NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES = rpc_events.define('NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES', 4104) +NV_VGPU_MSG_EVENT_SIM_READ = rpc_events.define('NV_VGPU_MSG_EVENT_SIM_READ', 4105) +NV_VGPU_MSG_EVENT_SIM_WRITE = rpc_events.define('NV_VGPU_MSG_EVENT_SIM_WRITE', 4106) +NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK = rpc_events.define('NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK', 4107) +NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT = rpc_events.define('NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT', 4108) +NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED = rpc_events.define('NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED', 4109) +NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK = rpc_events.define('NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK', 4110) +NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE = rpc_events.define('NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE', 4111) +NV_VGPU_MSG_EVENT_VGPU_CONFIG = rpc_events.define('NV_VGPU_MSG_EVENT_VGPU_CONFIG', 4112) +NV_VGPU_MSG_EVENT_DISPLAY_MODESET = rpc_events.define('NV_VGPU_MSG_EVENT_DISPLAY_MODESET', 4113) +NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE = rpc_events.define('NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE', 4114) +NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256 = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256', 4115) +NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512 = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512', 4116) +NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024 = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024', 4117) +NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048 = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048', 4118) +NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096 = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096', 4119) +NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE = rpc_events.define('NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE', 4120) +NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED', 4121) +NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK = rpc_events.define('NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK', 4122) +NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP', 4123) +NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE = rpc_events.define('NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE', 4124) +NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE = rpc_events.define('NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE', 4125) +NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE = rpc_events.define('NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE', 4126) +NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY = rpc_events.define('NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY', 4127) +NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD = rpc_events.define('NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD', 4128) +NV_VGPU_MSG_EVENT_FECS_ERROR = rpc_events.define('NV_VGPU_MSG_EVENT_FECS_ERROR', 4129) +NV_VGPU_MSG_EVENT_RECOVERY_ACTION = rpc_events.define('NV_VGPU_MSG_EVENT_RECOVERY_ACTION', 4130) +NV_VGPU_MSG_EVENT_NUM_EVENTS = rpc_events.define('NV_VGPU_MSG_EVENT_NUM_EVENTS', 4131) + +LibosAddress = ctypes.c_uint64 +LibosMemoryRegionKind = CEnum(ctypes.c_uint32) +LIBOS_MEMORY_REGION_NONE = LibosMemoryRegionKind.define('LIBOS_MEMORY_REGION_NONE', 0) +LIBOS_MEMORY_REGION_CONTIGUOUS = LibosMemoryRegionKind.define('LIBOS_MEMORY_REGION_CONTIGUOUS', 1) +LIBOS_MEMORY_REGION_RADIX3 = LibosMemoryRegionKind.define('LIBOS_MEMORY_REGION_RADIX3', 2) + +LibosMemoryRegionLoc = CEnum(ctypes.c_uint32) +LIBOS_MEMORY_REGION_LOC_NONE = LibosMemoryRegionLoc.define('LIBOS_MEMORY_REGION_LOC_NONE', 0) +LIBOS_MEMORY_REGION_LOC_SYSMEM = LibosMemoryRegionLoc.define('LIBOS_MEMORY_REGION_LOC_SYSMEM', 1) +LIBOS_MEMORY_REGION_LOC_FB = LibosMemoryRegionLoc.define('LIBOS_MEMORY_REGION_LOC_FB', 2) + +class LibosMemoryRegionInitArgument(Struct): pass +LibosMemoryRegionInitArgument._fields_ = [ + ('id8', LibosAddress), + ('pa', LibosAddress), + ('size', LibosAddress), + ('kind', NvU8), + ('loc', NvU8), +] +class msgqTxHeader(Struct): pass +msgqTxHeader._fields_ = [ + ('version', NvU32), + ('size', NvU32), + ('msgSize', NvU32), + ('msgCount', NvU32), + ('writePtr', NvU32), + ('flags', NvU32), + ('rxHdrOff', NvU32), + ('entryOff', NvU32), +] +class msgqRxHeader(Struct): pass +msgqRxHeader._fields_ = [ + ('readPtr', NvU32), +] +class msgqMetadata(Struct): pass +msgqFcnNotifyRemote = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_int32, ctypes.c_void_p) +msgqFcnBackendRw = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_void_p, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_void_p) +msgqFcnCacheOp = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_uint32) +msgqFcnBarrier = ctypes.CFUNCTYPE(None, ) +msgqMetadata._fields_ = [ + ('pOurTxHdr', ctypes.POINTER(msgqTxHeader)), + ('pTheirTxHdr', ctypes.POINTER(msgqTxHeader)), + ('pOurRxHdr', ctypes.POINTER(msgqRxHeader)), + ('pTheirRxHdr', ctypes.POINTER(msgqRxHeader)), + ('pOurEntries', ctypes.POINTER(NvU8)), + ('pTheirEntries', ctypes.POINTER(NvU8)), + ('pReadIncoming', ctypes.POINTER(NvU32)), + ('pWriteIncoming', ctypes.POINTER(NvU32)), + ('pReadOutgoing', ctypes.POINTER(NvU32)), + ('pWriteOutgoing', ctypes.POINTER(NvU32)), + ('tx', msgqTxHeader), + ('txReadPtr', NvU32), + ('txFree', NvU32), + ('txLinked', NvBool), + ('rx', msgqTxHeader), + ('rxReadPtr', NvU32), + ('rxAvail', NvU32), + ('rxLinked', NvBool), + ('rxSwapped', NvBool), + ('fcnNotify', msgqFcnNotifyRemote), + ('fcnNotifyArg', ctypes.c_void_p), + ('fcnBackendRw', msgqFcnBackendRw), + ('fcnBackendRwArg', ctypes.c_void_p), + ('fcnInvalidate', msgqFcnCacheOp), + ('fcnFlush', msgqFcnCacheOp), + ('fcnZero', msgqFcnCacheOp), + ('fcnBarrier', msgqFcnBarrier), +] +class struct_rpc_set_guest_system_info_v03_00(Struct): pass +struct_rpc_set_guest_system_info_v03_00._fields_ = [ + ('vgxVersionMajorNum', NvU32), + ('vgxVersionMinorNum', NvU32), + ('guestDriverVersionBufferLength', NvU32), + ('guestVersionBufferLength', NvU32), + ('guestTitleBufferLength', NvU32), + ('guestClNum', NvU32), + ('guestDriverVersion', (ctypes.c_char * 256)), + ('guestVersion', (ctypes.c_char * 256)), + ('guestTitle', (ctypes.c_char * 256)), +] +rpc_set_guest_system_info_v03_00 = struct_rpc_set_guest_system_info_v03_00 +rpc_set_guest_system_info_v = struct_rpc_set_guest_system_info_v03_00 +class struct_rpc_set_guest_system_info_ext_v15_02(Struct): pass +struct_rpc_set_guest_system_info_ext_v15_02._fields_ = [ + ('guestDriverBranch', (ctypes.c_char * 256)), + ('domain', NvU32), + ('bus', NvU16), + ('device', NvU16), +] +rpc_set_guest_system_info_ext_v15_02 = struct_rpc_set_guest_system_info_ext_v15_02 +class struct_rpc_set_guest_system_info_ext_v25_1B(Struct): pass +struct_rpc_set_guest_system_info_ext_v25_1B._fields_ = [ + ('guestDriverBranch', (ctypes.c_char * 256)), + ('domain', NvU32), + ('bus', NvU16), + ('device', NvU16), + ('gridBuildCsp', NvU32), +] +rpc_set_guest_system_info_ext_v25_1B = struct_rpc_set_guest_system_info_ext_v25_1B +rpc_set_guest_system_info_ext_v = struct_rpc_set_guest_system_info_ext_v25_1B +class struct_rpc_alloc_root_v07_00(Struct): pass +NvHandle = ctypes.c_uint32 +struct_rpc_alloc_root_v07_00._fields_ = [ + ('hClient', NvHandle), + ('processID', NvU32), + ('processName', (ctypes.c_char * 100)), +] +rpc_alloc_root_v07_00 = struct_rpc_alloc_root_v07_00 +rpc_alloc_root_v = struct_rpc_alloc_root_v07_00 +class struct_rpc_alloc_memory_v13_01(Struct): pass +class struct_pte_desc(Struct): pass +class struct_pte_desc_pte_pde(ctypes.Union): pass +struct_pte_desc_pte_pde._fields_ = [ + ('pte', NvU64), + ('pde', NvU64), +] +struct_pte_desc._fields_ = [ + ('idr', NvU32,2), + ('reserved1', NvU32,14), + ('length', NvU32,16), + ('pte_pde', (struct_pte_desc_pte_pde * 0)), +] +struct_rpc_alloc_memory_v13_01._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hMemory', NvHandle), + ('hClass', NvU32), + ('flags', NvU32), + ('pteAdjust', NvU32), + ('format', NvU32), + ('length', NvU64), + ('pageCount', NvU32), + ('pteDesc', struct_pte_desc), +] +rpc_alloc_memory_v13_01 = struct_rpc_alloc_memory_v13_01 +rpc_alloc_memory_v = struct_rpc_alloc_memory_v13_01 +class struct_rpc_alloc_channel_dma_v1F_04(Struct): pass +class struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04(Struct): pass +NV_CHANNEL_ALLOC_PARAMS_v1F_04 = struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04 +class struct_NV_MEMORY_DESC_PARAMS_v18_01(Struct): pass +NV_MEMORY_DESC_PARAMS_v18_01 = struct_NV_MEMORY_DESC_PARAMS_v18_01 +struct_NV_MEMORY_DESC_PARAMS_v18_01._fields_ = [ + ('base', NvU64), + ('size', NvU64), + ('addressSpace', NvU32), + ('cacheAttrib', NvU32), +] +struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04._fields_ = [ + ('hObjectError', NvHandle), + ('hObjectBuffer', NvHandle), + ('gpFifoOffset', NvU64), + ('gpFifoEntries', NvU32), + ('flags', NvU32), + ('hContextShare', NvHandle), + ('hVASpace', NvHandle), + ('hUserdMemory', (NvHandle * 1)), + ('userdOffset', (NvU64 * 1)), + ('engineType', NvU32), + ('hObjectEccError', NvHandle), + ('instanceMem', NV_MEMORY_DESC_PARAMS_v18_01), + ('ramfcMem', NV_MEMORY_DESC_PARAMS_v18_01), + ('userdMem', NV_MEMORY_DESC_PARAMS_v18_01), + ('mthdbufMem', NV_MEMORY_DESC_PARAMS_v18_01), + ('hPhysChannelGroup', NvHandle), + ('subDeviceId', NvHandle), + ('internalFlags', NvU32), + ('errorNotifierMem', NV_MEMORY_DESC_PARAMS_v18_01), + ('eccErrorNotifierMem', NV_MEMORY_DESC_PARAMS_v18_01), +] +struct_rpc_alloc_channel_dma_v1F_04._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hChannel', NvHandle), + ('hClass', NvU32), + ('flags', NvU32), + ('params', NV_CHANNEL_ALLOC_PARAMS_v1F_04), + ('chid', NvU32), +] +rpc_alloc_channel_dma_v1F_04 = struct_rpc_alloc_channel_dma_v1F_04 +rpc_alloc_channel_dma_v = struct_rpc_alloc_channel_dma_v1F_04 +class struct_rpc_alloc_object_v25_08(Struct): pass +class union_alloc_object_params_v25_08(ctypes.Union): pass +alloc_object_params_v25_08 = union_alloc_object_params_v25_08 +class struct_alloc_object_NV50_TESLA_v03_00(Struct): pass +alloc_object_NV50_TESLA_v03_00 = struct_alloc_object_NV50_TESLA_v03_00 +struct_alloc_object_NV50_TESLA_v03_00._fields_ = [ + ('version', NvU32), + ('flags', NvU32), + ('size', NvU32), + ('caps', NvU32), +] +class struct_alloc_object_GT212_DMA_COPY_v03_00(Struct): pass +alloc_object_GT212_DMA_COPY_v03_00 = struct_alloc_object_GT212_DMA_COPY_v03_00 +struct_alloc_object_GT212_DMA_COPY_v03_00._fields_ = [ + ('version', NvU32), + ('engineInstance', NvU32), +] +class struct_alloc_object_GF100_DISP_SW_v03_00(Struct): pass +alloc_object_GF100_DISP_SW_v03_00 = struct_alloc_object_GF100_DISP_SW_v03_00 +struct_alloc_object_GF100_DISP_SW_v03_00._fields_ = [ + ('_reserved1', NvU32), + ('_reserved2', NvU64), + ('logicalHeadId', NvU32), + ('displayMask', NvU32), + ('caps', NvU32), +] +class struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08(Struct): pass +alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 = struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 +struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08._fields_ = [ + ('hObjectError', NvU32), + ('hVASpace', NvU32), + ('engineType', NvU32), +] +class struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00(Struct): pass +alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 = struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 +struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00._fields_ = [ + ('hVASpace', NvU32), + ('flags', NvU32), + ('subctxId', NvU32), +] +class struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00(Struct): pass +alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 = struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 +struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), +] +class struct_alloc_object_FERMI_VASPACE_A_v03_00(Struct): pass +alloc_object_FERMI_VASPACE_A_v03_00 = struct_alloc_object_FERMI_VASPACE_A_v03_00 +struct_alloc_object_FERMI_VASPACE_A_v03_00._fields_ = [ + ('index', NvU32), + ('flags', NvU32), + ('vaSize', NvU64), + ('bigPageSize', NvU32), + ('vaBase', NvU64), +] +class struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00(Struct): pass +alloc_object_NVB0B0_VIDEO_DECODER_v03_00 = struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00 +struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), +] +class struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00(Struct): pass +alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 = struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 +struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00._fields_ = [ + ('hDebuggerClient', NvHandle), + ('hAppClient', NvHandle), + ('hClass3dObject', NvHandle), +] +class struct_alloc_object_NVENC_SW_SESSION_v06_01(Struct): pass +alloc_object_NVENC_SW_SESSION_v06_01 = struct_alloc_object_NVENC_SW_SESSION_v06_01 +struct_alloc_object_NVENC_SW_SESSION_v06_01._fields_ = [ + ('codecType', NvU32), + ('hResolution', NvU32), + ('vResolution', NvU32), +] +class struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02(Struct): pass +alloc_object_NVC4B0_VIDEO_DECODER_v12_02 = struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02 +struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), +] +class struct_alloc_object_NVFBC_SW_SESSION_v12_04(Struct): pass +alloc_object_NVFBC_SW_SESSION_v12_04 = struct_alloc_object_NVFBC_SW_SESSION_v12_04 +struct_alloc_object_NVFBC_SW_SESSION_v12_04._fields_ = [ + ('displayOrdinal', NvU32), + ('sessionType', NvU32), + ('sessionFlags', NvU32), + ('hMaxResolution', NvU32), + ('vMaxResolution', NvU32), +] +class struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02(Struct): pass +alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 = struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 +struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), +] +class struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02(Struct): pass +alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 = struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 +struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02._fields_ = [ + ('hSubDevice', NvHandle), + ('hPeerSubDevice', NvHandle), + ('subDevicePeerIdMask', NvU32), + ('peerSubDevicePeerIdMask', NvU32), + ('mailboxBar1Addr', NvU64), + ('mailboxTotalSize', NvU32), + ('flags', NvU32), +] +class struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00(Struct): pass +alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 = struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 +struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00._fields_ = [ + ('swizzId', NvU32), +] +class struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03(Struct): pass +alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 = struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 +struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03._fields_ = [ + ('offset', NvU64), + ('limit', NvU64), + ('hVASpace', NvHandle), +] +class struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06(Struct): pass +alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 = struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 +struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06._fields_ = [ + ('execPartitionId', NvU32), +] +class struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15(Struct): pass +alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 = struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 +struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15._fields_ = [ + ('flags', NvU32), + ('p2pToken', NvU64), +] +class struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01(Struct): pass +alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 = struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 +struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01._fields_ = [ + ('numHeads', NvU32), + ('numSors', NvU32), + ('numDsis', NvU32), +] +class struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03(Struct): pass +alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03 = struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03 +struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03._fields_ = [ + ('hSubDevice', NvHandle), +] +class struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03(Struct): pass +alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 = struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 +struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03._fields_ = [ + ('hClientTarget', NvHandle), + ('hContextTarget', NvHandle), +] +class struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17(Struct): pass +NV_GR_ALLOCATION_PARAMETERS_v1A_17 = struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17 +struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17._fields_ = [ + ('version', NvU32), + ('flags', NvU32), + ('size', NvU32), + ('caps', NvU32), +] +class struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B(Struct): pass +alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B = struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B +struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), +] +class struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C(Struct): pass +alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C = struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C +class struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C(Struct): pass +NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C = struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C +struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C._fields_ = [ + ('offset', NvU64), + ('hVidMem', NvHandle), + ('flags', NvU32), +] +struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C._fields_ = [ + ('alignment', NvU64), + ('allocSize', NvU64), + ('pageSize', NvU32), + ('allocFlags', NvU32), + ('map', NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C), +] +class struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00(Struct): pass +alloc_object_NVC9FA_VIDEO_OFA_v1F_00 = struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00 +struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), +] +class struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08(Struct): pass +alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 = struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 +struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08._fields_ = [ + ('reserved', NvU32), +] +union_alloc_object_params_v25_08._fields_ = [ + ('param_NV50_TESLA', alloc_object_NV50_TESLA_v03_00), + ('param_GT212_DMA_COPY', alloc_object_GT212_DMA_COPY_v03_00), + ('param_GF100_DISP_SW', alloc_object_GF100_DISP_SW_v03_00), + ('param_KEPLER_CHANNEL_GROUP_A', alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), + ('param_FERMI_CONTEXT_SHARE_A', alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), + ('param_NVD0B7_VIDEO_ENCODER', alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), + ('param_FERMI_VASPACE_A', alloc_object_FERMI_VASPACE_A_v03_00), + ('param_NVB0B0_VIDEO_DECODER', alloc_object_NVB0B0_VIDEO_DECODER_v03_00), + ('param_NV83DE_ALLOC_PARAMETERS', alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), + ('param_NVENC_SW_SESSION', alloc_object_NVENC_SW_SESSION_v06_01), + ('param_NVC4B0_VIDEO_DECODER', alloc_object_NVC4B0_VIDEO_DECODER_v12_02), + ('param_NVFBC_SW_SESSION', alloc_object_NVFBC_SW_SESSION_v12_04), + ('param_NV_NVJPG_ALLOCATION_PARAMETERS', alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), + ('param_NV503B_ALLOC_PARAMETERS', alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), + ('param_NVC637_ALLOCATION_PARAMETERS', alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), + ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), + ('param_NVC638_ALLOCATION_PARAMETERS', alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), + ('param_NV503C_ALLOC_PARAMETERS', alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), + ('param_NVC670_ALLOCATION_PARAMETERS', alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), + ('param_NVB1CC_ALLOC_PARAMETERS', alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), + ('param_NVB2CC_ALLOC_PARAMETERS', alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), + ('param_NV_GR_ALLOCATION_PARAMETERS', NV_GR_ALLOCATION_PARAMETERS_v1A_17), + ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), + ('param_NV00F8_ALLOCATION_PARAMETERS', alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), + ('param_NVC9FA_VIDEO_OFA', alloc_object_NVC9FA_VIDEO_OFA_v1F_00), + ('param_NV2081_ALLOC_PARAMETERS', alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), +] +struct_rpc_alloc_object_v25_08._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClass', NvU32), + ('param_len', NvU32), + ('params', alloc_object_params_v25_08), +] +rpc_alloc_object_v25_08 = struct_rpc_alloc_object_v25_08 +class struct_rpc_alloc_object_v26_00(Struct): pass +class union_alloc_object_params_v26_00(ctypes.Union): pass +alloc_object_params_v26_00 = union_alloc_object_params_v26_00 +union_alloc_object_params_v26_00._fields_ = [ + ('param_NV50_TESLA', alloc_object_NV50_TESLA_v03_00), + ('param_GT212_DMA_COPY', alloc_object_GT212_DMA_COPY_v03_00), + ('param_GF100_DISP_SW', alloc_object_GF100_DISP_SW_v03_00), + ('param_KEPLER_CHANNEL_GROUP_A', alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), + ('param_FERMI_CONTEXT_SHARE_A', alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), + ('param_NVD0B7_VIDEO_ENCODER', alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), + ('param_FERMI_VASPACE_A', alloc_object_FERMI_VASPACE_A_v03_00), + ('param_NVB0B0_VIDEO_DECODER', alloc_object_NVB0B0_VIDEO_DECODER_v03_00), + ('param_NV83DE_ALLOC_PARAMETERS', alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), + ('param_NVENC_SW_SESSION', alloc_object_NVENC_SW_SESSION_v06_01), + ('param_NVC4B0_VIDEO_DECODER', alloc_object_NVC4B0_VIDEO_DECODER_v12_02), + ('param_NVFBC_SW_SESSION', alloc_object_NVFBC_SW_SESSION_v12_04), + ('param_NV_NVJPG_ALLOCATION_PARAMETERS', alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), + ('param_NV503B_ALLOC_PARAMETERS', alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), + ('param_NVC637_ALLOCATION_PARAMETERS', alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), + ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), + ('param_NVC638_ALLOCATION_PARAMETERS', alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), + ('param_NV503C_ALLOC_PARAMETERS', alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), + ('param_NVC670_ALLOCATION_PARAMETERS', alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), + ('param_NVB1CC_ALLOC_PARAMETERS', alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), + ('param_NVB2CC_ALLOC_PARAMETERS', alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), + ('param_NV_GR_ALLOCATION_PARAMETERS', NV_GR_ALLOCATION_PARAMETERS_v1A_17), + ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), + ('param_NV00F8_ALLOCATION_PARAMETERS', alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), + ('param_NVC9FA_VIDEO_OFA', alloc_object_NVC9FA_VIDEO_OFA_v1F_00), + ('param_NV2081_ALLOC_PARAMETERS', alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), + ('param_padding', (NvU8 * 56)), +] +struct_rpc_alloc_object_v26_00._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClass', NvU32), + ('param_len', NvU32), + ('params', alloc_object_params_v26_00), +] +rpc_alloc_object_v26_00 = struct_rpc_alloc_object_v26_00 +class struct_rpc_alloc_object_v27_00(Struct): pass +class union_alloc_object_params_v27_00(ctypes.Union): pass +alloc_object_params_v27_00 = union_alloc_object_params_v27_00 +union_alloc_object_params_v27_00._fields_ = [ + ('param_NV50_TESLA', alloc_object_NV50_TESLA_v03_00), + ('param_GT212_DMA_COPY', alloc_object_GT212_DMA_COPY_v03_00), + ('param_GF100_DISP_SW', alloc_object_GF100_DISP_SW_v03_00), + ('param_KEPLER_CHANNEL_GROUP_A', alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), + ('param_FERMI_CONTEXT_SHARE_A', alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), + ('param_NVD0B7_VIDEO_ENCODER', alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), + ('param_FERMI_VASPACE_A', alloc_object_FERMI_VASPACE_A_v03_00), + ('param_NVB0B0_VIDEO_DECODER', alloc_object_NVB0B0_VIDEO_DECODER_v03_00), + ('param_NV83DE_ALLOC_PARAMETERS', alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), + ('param_NVENC_SW_SESSION', alloc_object_NVENC_SW_SESSION_v06_01), + ('param_NVC4B0_VIDEO_DECODER', alloc_object_NVC4B0_VIDEO_DECODER_v12_02), + ('param_NVFBC_SW_SESSION', alloc_object_NVFBC_SW_SESSION_v12_04), + ('param_NV_NVJPG_ALLOCATION_PARAMETERS', alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), + ('param_NV503B_ALLOC_PARAMETERS', alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), + ('param_NVC637_ALLOCATION_PARAMETERS', alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), + ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), + ('param_NVC638_ALLOCATION_PARAMETERS', alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), + ('param_NV503C_ALLOC_PARAMETERS', alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), + ('param_NVC670_ALLOCATION_PARAMETERS', alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), + ('param_NVB1CC_ALLOC_PARAMETERS', alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), + ('param_NVB2CC_ALLOC_PARAMETERS', alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), + ('param_NV_GR_ALLOCATION_PARAMETERS', NV_GR_ALLOCATION_PARAMETERS_v1A_17), + ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), + ('param_NV00F8_ALLOCATION_PARAMETERS', alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), + ('param_NVC9FA_VIDEO_OFA', alloc_object_NVC9FA_VIDEO_OFA_v1F_00), + ('param_NV2081_ALLOC_PARAMETERS', alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), + ('param_padding', (NvU8 * 56)), +] +struct_rpc_alloc_object_v27_00._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClass', NvU32), + ('param_len', NvU32), + ('params', alloc_object_params_v27_00), +] +rpc_alloc_object_v27_00 = struct_rpc_alloc_object_v27_00 +class struct_rpc_alloc_object_v29_06(Struct): pass +class union_alloc_object_params_v29_06(ctypes.Union): pass +alloc_object_params_v29_06 = union_alloc_object_params_v29_06 +class struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06(Struct): pass +alloc_object_NVC9FA_VIDEO_OFA_v29_06 = struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06 +struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), +] +union_alloc_object_params_v29_06._fields_ = [ + ('param_NV50_TESLA', alloc_object_NV50_TESLA_v03_00), + ('param_GT212_DMA_COPY', alloc_object_GT212_DMA_COPY_v03_00), + ('param_GF100_DISP_SW', alloc_object_GF100_DISP_SW_v03_00), + ('param_KEPLER_CHANNEL_GROUP_A', alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), + ('param_FERMI_CONTEXT_SHARE_A', alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), + ('param_NVD0B7_VIDEO_ENCODER', alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), + ('param_FERMI_VASPACE_A', alloc_object_FERMI_VASPACE_A_v03_00), + ('param_NVB0B0_VIDEO_DECODER', alloc_object_NVB0B0_VIDEO_DECODER_v03_00), + ('param_NV83DE_ALLOC_PARAMETERS', alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), + ('param_NVENC_SW_SESSION', alloc_object_NVENC_SW_SESSION_v06_01), + ('param_NVC4B0_VIDEO_DECODER', alloc_object_NVC4B0_VIDEO_DECODER_v12_02), + ('param_NVFBC_SW_SESSION', alloc_object_NVFBC_SW_SESSION_v12_04), + ('param_NV_NVJPG_ALLOCATION_PARAMETERS', alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), + ('param_NV503B_ALLOC_PARAMETERS', alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), + ('param_NVC637_ALLOCATION_PARAMETERS', alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), + ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), + ('param_NVC638_ALLOCATION_PARAMETERS', alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), + ('param_NV503C_ALLOC_PARAMETERS', alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), + ('param_NVC670_ALLOCATION_PARAMETERS', alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), + ('param_NVB1CC_ALLOC_PARAMETERS', alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), + ('param_NVB2CC_ALLOC_PARAMETERS', alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), + ('param_NV_GR_ALLOCATION_PARAMETERS', NV_GR_ALLOCATION_PARAMETERS_v1A_17), + ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), + ('param_NV00F8_ALLOCATION_PARAMETERS', alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), + ('param_NVC9FA_VIDEO_OFA', alloc_object_NVC9FA_VIDEO_OFA_v29_06), + ('param_NV2081_ALLOC_PARAMETERS', alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), + ('param_padding', (NvU8 * 56)), +] +struct_rpc_alloc_object_v29_06._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClass', NvU32), + ('param_len', NvU32), + ('params', alloc_object_params_v29_06), +] +rpc_alloc_object_v29_06 = struct_rpc_alloc_object_v29_06 +rpc_alloc_object_v = struct_rpc_alloc_object_v29_06 +class struct_rpc_free_v03_00(Struct): pass +class struct_NVOS00_PARAMETERS_v03_00(Struct): pass +NVOS00_PARAMETERS_v03_00 = struct_NVOS00_PARAMETERS_v03_00 +NvV32 = ctypes.c_uint32 +struct_NVOS00_PARAMETERS_v03_00._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectOld', NvHandle), + ('status', NvV32), +] +struct_rpc_free_v03_00._fields_ = [ + ('params', NVOS00_PARAMETERS_v03_00), +] +rpc_free_v03_00 = struct_rpc_free_v03_00 +rpc_free_v = struct_rpc_free_v03_00 +class struct_rpc_log_v03_00(Struct): pass +struct_rpc_log_v03_00._fields_ = [ + ('level', NvU32), + ('log_len', NvU32), + ('log_msg', (ctypes.c_char * 0)), +] +rpc_log_v03_00 = struct_rpc_log_v03_00 +rpc_log_v = struct_rpc_log_v03_00 +class struct_rpc_map_memory_dma_v03_00(Struct): pass +class struct_NVOS46_PARAMETERS_v03_00(Struct): pass +NVOS46_PARAMETERS_v03_00 = struct_NVOS46_PARAMETERS_v03_00 +struct_NVOS46_PARAMETERS_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hDma', NvHandle), + ('hMemory', NvHandle), + ('offset', NvU64), + ('length', NvU64), + ('flags', NvV32), + ('dmaOffset', NvU64), + ('status', NvV32), +] +struct_rpc_map_memory_dma_v03_00._fields_ = [ + ('params', NVOS46_PARAMETERS_v03_00), +] +rpc_map_memory_dma_v03_00 = struct_rpc_map_memory_dma_v03_00 +rpc_map_memory_dma_v = struct_rpc_map_memory_dma_v03_00 +class struct_rpc_unmap_memory_dma_v03_00(Struct): pass +class struct_NVOS47_PARAMETERS_v03_00(Struct): pass +NVOS47_PARAMETERS_v03_00 = struct_NVOS47_PARAMETERS_v03_00 +struct_NVOS47_PARAMETERS_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hDma', NvHandle), + ('hMemory', NvHandle), + ('flags', NvV32), + ('dmaOffset', NvU64), + ('status', NvV32), +] +struct_rpc_unmap_memory_dma_v03_00._fields_ = [ + ('params', NVOS47_PARAMETERS_v03_00), +] +rpc_unmap_memory_dma_v03_00 = struct_rpc_unmap_memory_dma_v03_00 +rpc_unmap_memory_dma_v = struct_rpc_unmap_memory_dma_v03_00 +class struct_rpc_alloc_subdevice_v08_01(Struct): pass +class struct_NVOS21_PARAMETERS_v03_00(Struct): pass +NVOS21_PARAMETERS_v03_00 = struct_NVOS21_PARAMETERS_v03_00 +NvP64 = ctypes.c_void_p +struct_NVOS21_PARAMETERS_v03_00._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('pAllocParms', NvP64), + ('status', NvV32), +] +struct_rpc_alloc_subdevice_v08_01._fields_ = [ + ('subDeviceInst', NvU32), + ('params', NVOS21_PARAMETERS_v03_00), +] +rpc_alloc_subdevice_v08_01 = struct_rpc_alloc_subdevice_v08_01 +rpc_alloc_subdevice_v = struct_rpc_alloc_subdevice_v08_01 +class struct_rpc_dup_object_v03_00(Struct): pass +class struct_NVOS55_PARAMETERS_v03_00(Struct): pass +NVOS55_PARAMETERS_v03_00 = struct_NVOS55_PARAMETERS_v03_00 +struct_NVOS55_PARAMETERS_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClientSrc', NvHandle), + ('hObjectSrc', NvHandle), + ('flags', NvU32), + ('status', NvU32), +] +struct_rpc_dup_object_v03_00._fields_ = [ + ('params', NVOS55_PARAMETERS_v03_00), +] +rpc_dup_object_v03_00 = struct_rpc_dup_object_v03_00 +rpc_dup_object_v = struct_rpc_dup_object_v03_00 +class struct_rpc_idle_channels_v03_00(Struct): pass +class struct_idle_channel_list_v03_00(Struct): pass +idle_channel_list_v03_00 = struct_idle_channel_list_v03_00 +struct_idle_channel_list_v03_00._fields_ = [ + ('phClient', NvU32), + ('phDevice', NvU32), + ('phChannel', NvU32), +] +struct_rpc_idle_channels_v03_00._fields_ = [ + ('flags', NvU32), + ('timeout', NvU32), + ('nchannels', NvU32), + ('channel_list', (idle_channel_list_v03_00 * 0)), +] +rpc_idle_channels_v03_00 = struct_rpc_idle_channels_v03_00 +rpc_idle_channels_v = struct_rpc_idle_channels_v03_00 +class struct_rpc_alloc_event_v03_00(Struct): pass +struct_rpc_alloc_event_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hParentClient', NvHandle), + ('hChannel', NvHandle), + ('hObject', NvHandle), + ('hEvent', NvHandle), + ('hClass', NvU32), + ('notifyIndex', NvU32), +] +rpc_alloc_event_v03_00 = struct_rpc_alloc_event_v03_00 +rpc_alloc_event_v = struct_rpc_alloc_event_v03_00 +class struct_rpc_rm_api_control_v25_0D(Struct): pass +class struct_NVOS54_PARAMETERS_v03_00(Struct): pass +NVOS54_PARAMETERS_v03_00 = struct_NVOS54_PARAMETERS_v03_00 +NvRmctrlCmd = ctypes.c_uint32 +struct_NVOS54_PARAMETERS_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvRmctrlCmd), + ('params', NvP64), + ('paramsSize', NvU32), + ('status', NvV32), +] +struct_rpc_rm_api_control_v25_0D._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_0D = struct_rpc_rm_api_control_v25_0D +class struct_rpc_rm_api_control_v25_0F(Struct): pass +struct_rpc_rm_api_control_v25_0F._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_0F = struct_rpc_rm_api_control_v25_0F +class struct_rpc_rm_api_control_v25_10(Struct): pass +struct_rpc_rm_api_control_v25_10._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_10 = struct_rpc_rm_api_control_v25_10 +class struct_rpc_rm_api_control_v25_14(Struct): pass +struct_rpc_rm_api_control_v25_14._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_14 = struct_rpc_rm_api_control_v25_14 +class struct_rpc_rm_api_control_v25_15(Struct): pass +struct_rpc_rm_api_control_v25_15._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_15 = struct_rpc_rm_api_control_v25_15 +class struct_rpc_rm_api_control_v25_16(Struct): pass +struct_rpc_rm_api_control_v25_16._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_16 = struct_rpc_rm_api_control_v25_16 +class struct_rpc_rm_api_control_v25_17(Struct): pass +struct_rpc_rm_api_control_v25_17._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_17 = struct_rpc_rm_api_control_v25_17 +class struct_rpc_rm_api_control_v25_18(Struct): pass +struct_rpc_rm_api_control_v25_18._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_18 = struct_rpc_rm_api_control_v25_18 +class struct_rpc_rm_api_control_v25_19(Struct): pass +struct_rpc_rm_api_control_v25_19._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_19 = struct_rpc_rm_api_control_v25_19 +class struct_rpc_rm_api_control_v25_1A(Struct): pass +struct_rpc_rm_api_control_v25_1A._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v25_1A = struct_rpc_rm_api_control_v25_1A +class struct_rpc_rm_api_control_v27_03(Struct): pass +struct_rpc_rm_api_control_v27_03._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v27_03 = struct_rpc_rm_api_control_v27_03 +class struct_rpc_rm_api_control_v29_04(Struct): pass +struct_rpc_rm_api_control_v29_04._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v29_04 = struct_rpc_rm_api_control_v29_04 +class struct_rpc_rm_api_control_v29_09(Struct): pass +struct_rpc_rm_api_control_v29_09._fields_ = [ + ('params', NVOS54_PARAMETERS_v03_00), + ('rm_api_params', NvP64), +] +rpc_rm_api_control_v29_09 = struct_rpc_rm_api_control_v29_09 +rpc_rm_api_control_v = struct_rpc_rm_api_control_v29_09 +class struct_rpc_alloc_share_device_v03_00(Struct): pass +class struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00(Struct): pass +NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 = struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 +struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00._fields_ = [ + ('szName', NvP64), + ('hClientShare', NvHandle), + ('hTargetClient', NvHandle), + ('hTargetDevice', NvHandle), + ('flags', NvV32), + ('vaSpaceSize', NvU64), + ('vaMode', NvV32), + ('vaBase', NvU64), +] +struct_rpc_alloc_share_device_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hClass', NvU32), + ('params', NV_DEVICE_ALLOCATION_PARAMETERS_v03_00), +] +rpc_alloc_share_device_v03_00 = struct_rpc_alloc_share_device_v03_00 +rpc_alloc_share_device_v = struct_rpc_alloc_share_device_v03_00 +class struct_rpc_get_engine_utilization_v1F_0E(Struct): pass +class union_vgpuGetEngineUtilization_data_v1F_0E(ctypes.Union): pass +vgpuGetEngineUtilization_data_v1F_0E = union_vgpuGetEngineUtilization_data_v1F_0E +class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00(Struct): pass +NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 = struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 +enum_NV2080_CTRL_CMD_PERF_VID_ENG = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', 1) +NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', 2) +NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', 3) +NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', 4) + +NV2080_CTRL_CMD_PERF_VID_ENG = enum_NV2080_CTRL_CMD_PERF_VID_ENG +struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00._fields_ = [ + ('engineType', NV2080_CTRL_CMD_PERF_VID_ENG), + ('clkPercentBusy', NvU32), + ('samplingPeriodUs', NvU32), +] +class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C(Struct): pass +NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C +struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C._fields_ = [ + ('gpuId', NvU32), + ('vmPid', NvU32), + ('state', NvU32), +] +class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C(Struct): pass +NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C +struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C._fields_ = [ + ('gpuId', NvU32), + ('vmPid', NvU32), + ('newState', NvU32), +] +class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C(Struct): pass +NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C +struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C._fields_ = [ + ('gpuId', NvU32), + ('vmPid', NvU32), + ('passIndex', NvU32), + ('pidCount', NvU32), + ('pidTable', (NvU32 * 1000)), +] +class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C(Struct): pass +NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C +struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C._fields_ = [ + ('gpuId', NvU32), + ('pid', NvU32), + ('subPid', NvU32), + ('gpuUtil', NvU32), + ('fbUtil', NvU32), + ('maxFbUsage', NvU64), + ('startTime', NvU64), + ('endTime', NvU64), +] +class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C(Struct): pass +NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C +struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C._fields_ = [ + ('gpuId', NvU32), + ('vmPid', NvU32), +] +class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E(Struct): pass +NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E = struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E +class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00(Struct): pass +NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 = struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 +struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00._fields_ = [ + ('util', NvU32), + ('procId', NvU32), + ('subProcessID', NvU32), +] +struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E._fields_ = [ + ('timeStamp', NvU64), + ('fb', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), + ('gr', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), + ('nvenc', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), + ('nvdec', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), +] +union_vgpuGetEngineUtilization_data_v1F_0E._fields_ = [ + ('vidPerfmonSample', NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00), + ('getAccountingState', NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C), + ('setAccountingState', NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C), + ('getAccountingPidList', NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C), + ('procAccountingInfo', NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C), + ('clearAccountingInfo', NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C), + ('gpumonPerfmonsampleV2', (NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E * 72)), +] +struct_rpc_get_engine_utilization_v1F_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvU32), + ('params', vgpuGetEngineUtilization_data_v1F_0E), +] +rpc_get_engine_utilization_v1F_0E = struct_rpc_get_engine_utilization_v1F_0E +rpc_get_engine_utilization_v = struct_rpc_get_engine_utilization_v1F_0E +class struct_rpc_perf_get_level_info_v03_00(Struct): pass +struct_rpc_perf_get_level_info_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('level', NvU32), + ('flags', NvU32), + ('perfGetClkInfoListSize', NvU32), + ('param_size', NvU32), + ('params', (NvU32 * 0)), +] +rpc_perf_get_level_info_v03_00 = struct_rpc_perf_get_level_info_v03_00 +rpc_perf_get_level_info_v = struct_rpc_perf_get_level_info_v03_00 +class struct_rpc_set_surface_properties_v07_07(Struct): pass +class struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07(Struct): pass +NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 = struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 +struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07._fields_ = [ + ('headIndex', NvU32), + ('isPrimary', NvU32), + ('offset', NvU32), + ('surfaceType', NvU32), + ('surfaceBlockHeight', NvU32), + ('surfacePitch', NvU32), + ('surfaceFormat', NvU32), + ('surfaceWidth', NvU32), + ('surfaceHeight', NvU32), + ('rectX', NvU32), + ('rectY', NvU32), + ('rectWidth', NvU32), + ('rectHeight', NvU32), + ('surfaceSize', NvU32), + ('surfaceKind', NvU32), + ('hHwResDevice', NvU32), + ('hHwResHandle', NvU32), + ('effectiveFbPageSize', NvU32), +] +struct_rpc_set_surface_properties_v07_07._fields_ = [ + ('hClient', NvHandle), + ('params', NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07), +] +rpc_set_surface_properties_v07_07 = struct_rpc_set_surface_properties_v07_07 +rpc_set_surface_properties_v = struct_rpc_set_surface_properties_v07_07 +class struct_rpc_cleanup_surface_v03_00(Struct): pass +class struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00(Struct): pass +NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 = struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 +struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00._fields_ = [ + ('headIndex', NvU32), + ('blankingEnabled', NvU32), +] +struct_rpc_cleanup_surface_v03_00._fields_ = [ + ('params', NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00), +] +rpc_cleanup_surface_v03_00 = struct_rpc_cleanup_surface_v03_00 +rpc_cleanup_surface_v = struct_rpc_cleanup_surface_v03_00 +class struct_rpc_unloading_guest_driver_v1F_07(Struct): pass +struct_rpc_unloading_guest_driver_v1F_07._fields_ = [ + ('bInPMTransition', NvBool), + ('bGc6Entering', NvBool), + ('newLevel', NvU32), +] +rpc_unloading_guest_driver_v1F_07 = struct_rpc_unloading_guest_driver_v1F_07 +rpc_unloading_guest_driver_v = struct_rpc_unloading_guest_driver_v1F_07 +class struct_rpc_gpu_exec_reg_ops_v12_01(Struct): pass +class struct_gpu_exec_reg_ops_v12_01(Struct): pass +gpu_exec_reg_ops_v12_01 = struct_gpu_exec_reg_ops_v12_01 +class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01(Struct): pass +NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 +class struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01(Struct): pass +NV2080_CTRL_GR_ROUTE_INFO_v12_01 = struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01 +struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01._fields_ = [ + ('flags', NvU32), + ('route', NvU64), +] +struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01._fields_ = [ + ('hClientTarget', NvHandle), + ('hChannelTarget', NvHandle), + ('reserved00', (NvU32 * 3)), + ('regOpCount', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), + ('regOps', NvP64), +] +class struct_NV2080_CTRL_GPU_REG_OP_v03_00(Struct): pass +NV2080_CTRL_GPU_REG_OP_v03_00 = struct_NV2080_CTRL_GPU_REG_OP_v03_00 +struct_NV2080_CTRL_GPU_REG_OP_v03_00._fields_ = [ + ('regOp', NvU8), + ('regType', NvU8), + ('regStatus', NvU8), + ('regQuad', NvU8), + ('regGroupMask', NvU32), + ('regSubGroupMask', NvU32), + ('regOffset', NvU32), + ('regValueHi', NvU32), + ('regValueLo', NvU32), + ('regAndNMaskHi', NvU32), + ('regAndNMaskLo', NvU32), +] +struct_gpu_exec_reg_ops_v12_01._fields_ = [ + ('reg_op_params', NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01), + ('operations', (NV2080_CTRL_GPU_REG_OP_v03_00 * 0)), +] +struct_rpc_gpu_exec_reg_ops_v12_01._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', gpu_exec_reg_ops_v12_01), +] +rpc_gpu_exec_reg_ops_v12_01 = struct_rpc_gpu_exec_reg_ops_v12_01 +rpc_gpu_exec_reg_ops_v = struct_rpc_gpu_exec_reg_ops_v12_01 +class struct_rpc_get_static_data_v25_0E(Struct): pass +struct_rpc_get_static_data_v25_0E._fields_ = [ + ('offset', NvU32), + ('size', NvU32), + ('payload', (NvU8 * 0)), +] +rpc_get_static_data_v25_0E = struct_rpc_get_static_data_v25_0E +class struct_rpc_get_static_data_v27_01(Struct): pass +struct_rpc_get_static_data_v27_01._fields_ = [ + ('offset', NvU32), + ('size', NvU32), + ('payload', (NvU8 * 0)), +] +rpc_get_static_data_v27_01 = struct_rpc_get_static_data_v27_01 +rpc_get_static_data_v = struct_rpc_get_static_data_v27_01 +class struct_rpc_get_consolidated_gr_static_info_v1B_04(Struct): pass +struct_rpc_get_consolidated_gr_static_info_v1B_04._fields_ = [ + ('offset', NvU32), + ('size', NvU32), + ('payload', (NvU8 * 0)), +] +rpc_get_consolidated_gr_static_info_v1B_04 = struct_rpc_get_consolidated_gr_static_info_v1B_04 +rpc_get_consolidated_gr_static_info_v = struct_rpc_get_consolidated_gr_static_info_v1B_04 +class struct_rpc_set_page_directory_v1E_05(Struct): pass +class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05(Struct): pass +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 +struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05._fields_ = [ + ('physAddress', NvU64), + ('numEntries', NvU32), + ('flags', NvU32), + ('hVASpace', NvHandle), + ('chId', NvU32), + ('subDeviceId', NvU32), + ('pasid', NvU32), +] +struct_rpc_set_page_directory_v1E_05._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('pasid', NvU32), + ('params', NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05), +] +rpc_set_page_directory_v1E_05 = struct_rpc_set_page_directory_v1E_05 +rpc_set_page_directory_v = struct_rpc_set_page_directory_v1E_05 +class struct_rpc_unset_page_directory_v1E_05(Struct): pass +class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05(Struct): pass +NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 +struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05._fields_ = [ + ('hVASpace', NvHandle), + ('subDeviceId', NvU32), +] +struct_rpc_unset_page_directory_v1E_05._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('params', NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05), +] +rpc_unset_page_directory_v1E_05 = struct_rpc_unset_page_directory_v1E_05 +rpc_unset_page_directory_v = struct_rpc_unset_page_directory_v1E_05 +class struct_rpc_get_gsp_static_info_v14_00(Struct): pass +struct_rpc_get_gsp_static_info_v14_00._fields_ = [ + ('data', NvU32), +] +rpc_get_gsp_static_info_v14_00 = struct_rpc_get_gsp_static_info_v14_00 +rpc_get_gsp_static_info_v = struct_rpc_get_gsp_static_info_v14_00 +class struct_rpc_update_bar_pde_v15_00(Struct): pass +class struct_UpdateBarPde_v15_00(Struct): pass +UpdateBarPde_v15_00 = struct_UpdateBarPde_v15_00 +struct_UpdateBarPde_v15_00._fields_ = [ + ('barType', NV_RPC_UPDATE_PDE_BAR_TYPE), + ('entryValue', NvU64), + ('entryLevelShift', NvU64), +] +struct_rpc_update_bar_pde_v15_00._fields_ = [ + ('info', UpdateBarPde_v15_00), +] +rpc_update_bar_pde_v15_00 = struct_rpc_update_bar_pde_v15_00 +rpc_update_bar_pde_v = struct_rpc_update_bar_pde_v15_00 +class struct_rpc_get_encoder_capacity_v07_00(Struct): pass +struct_rpc_get_encoder_capacity_v07_00._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('encoderCapacity', NvU32), +] +rpc_get_encoder_capacity_v07_00 = struct_rpc_get_encoder_capacity_v07_00 +rpc_get_encoder_capacity_v = struct_rpc_get_encoder_capacity_v07_00 +class struct_rpc_vgpu_pf_reg_read32_v15_00(Struct): pass +struct_rpc_vgpu_pf_reg_read32_v15_00._fields_ = [ + ('address', NvU64), + ('value', NvU32), + ('grEngId', NvU32), +] +rpc_vgpu_pf_reg_read32_v15_00 = struct_rpc_vgpu_pf_reg_read32_v15_00 +rpc_vgpu_pf_reg_read32_v = struct_rpc_vgpu_pf_reg_read32_v15_00 +class struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08(Struct): pass +class struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02(Struct): pass +NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02 = struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02 +struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02._fields_ = [ + ('fbUsed', NvU64), +] +struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08._fields_ = [ + ('setFbUsage', NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02), +] +rpc_ctrl_set_vgpu_fb_usage_v1A_08 = struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08 +rpc_ctrl_set_vgpu_fb_usage_v = struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08 +class struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09(Struct): pass +class struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(Struct): pass +NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 = struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 +struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01._fields_ = [ + ('hResolution', NvU32), + ('vResolution', NvU32), + ('averageEncodeLatency', NvU32), + ('averageEncodeFps', NvU32), + ('timestampBufferSize', NvU32), + ('timestampBuffer', NvP64), +] +struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('nvencSessionUpdate', NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01), +] +rpc_ctrl_nvenc_sw_session_update_info_v1A_09 = struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 +rpc_ctrl_nvenc_sw_session_update_info_v = struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 +class struct_rpc_ctrl_reset_channel_v1A_09(Struct): pass +class struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(Struct): pass +NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 = struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 +struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01._fields_ = [ + ('engineID', NvU32), + ('subdeviceInstance', NvU32), + ('resetReason', NvU32), +] +struct_rpc_ctrl_reset_channel_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('resetChannel', NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01), +] +rpc_ctrl_reset_channel_v1A_09 = struct_rpc_ctrl_reset_channel_v1A_09 +rpc_ctrl_reset_channel_v = struct_rpc_ctrl_reset_channel_v1A_09 +class struct_rpc_ctrl_reset_isolated_channel_v1A_09(Struct): pass +class struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(Struct): pass +NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 = struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 +struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00._fields_ = [ + ('exceptType', NvU32), + ('engineID', NvU32), +] +struct_rpc_ctrl_reset_isolated_channel_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('resetIsolatedChannel', NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00), +] +rpc_ctrl_reset_isolated_channel_v1A_09 = struct_rpc_ctrl_reset_isolated_channel_v1A_09 +rpc_ctrl_reset_isolated_channel_v = struct_rpc_ctrl_reset_isolated_channel_v1A_09 +class struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09(Struct): pass +class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(Struct): pass +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 = struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 +struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09._fields_ = [ + ('faultType', NvU32), +] +struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('handleVfPriFault', NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09), +] +rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 = struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 +rpc_ctrl_gpu_handle_vf_pri_fault_v = struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 +class struct_rpc_ctrl_perf_boost_v1A_09(Struct): pass +class struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(Struct): pass +NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 = struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 +struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00._fields_ = [ + ('flags', NvU32), + ('duration', NvU32), +] +struct_rpc_ctrl_perf_boost_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('perfBoost', NV2080_CTRL_PERF_BOOST_PARAMS_v03_00), +] +rpc_ctrl_perf_boost_v1A_09 = struct_rpc_ctrl_perf_boost_v1A_09 +rpc_ctrl_perf_boost_v = struct_rpc_ctrl_perf_boost_v1A_09 +class struct_rpc_ctrl_get_zbc_clear_table_v1A_09(Struct): pass +class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(Struct): pass +NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 = struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 +class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00(Struct): pass +NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 = struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 +struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00._fields_ = [ + ('colorFB', (NvU32 * 4)), + ('colorDS', (NvU32 * 4)), + ('depth', NvU32), + ('stencil', NvU32), +] +struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00._fields_ = [ + ('value', NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00), + ('indexSize', NvU32), + ('indexUsed', NvU32), + ('format', NvU32), + ('valType', NvU32), +] +struct_rpc_ctrl_get_zbc_clear_table_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('getZbcClearTable', NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00), +] +rpc_ctrl_get_zbc_clear_table_v1A_09 = struct_rpc_ctrl_get_zbc_clear_table_v1A_09 +rpc_ctrl_get_zbc_clear_table_v = struct_rpc_ctrl_get_zbc_clear_table_v1A_09 +class struct_rpc_ctrl_set_zbc_color_clear_v1A_09(Struct): pass +class struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(Struct): pass +NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 = struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 +struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00._fields_ = [ + ('colorFB', (NvU32 * 4)), + ('colorDS', (NvU32 * 4)), + ('format', NvU32), +] +struct_rpc_ctrl_set_zbc_color_clear_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('setZbcColorClr', NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00), +] +rpc_ctrl_set_zbc_color_clear_v1A_09 = struct_rpc_ctrl_set_zbc_color_clear_v1A_09 +rpc_ctrl_set_zbc_color_clear_v = struct_rpc_ctrl_set_zbc_color_clear_v1A_09 +class struct_rpc_ctrl_set_zbc_depth_clear_v1A_09(Struct): pass +class struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(Struct): pass +NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 = struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 +struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00._fields_ = [ + ('depth', NvU32), + ('format', NvU32), +] +struct_rpc_ctrl_set_zbc_depth_clear_v1A_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('setZbcDepthClr', NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00), +] +rpc_ctrl_set_zbc_depth_clear_v1A_09 = struct_rpc_ctrl_set_zbc_depth_clear_v1A_09 +rpc_ctrl_set_zbc_depth_clear_v = struct_rpc_ctrl_set_zbc_depth_clear_v1A_09 +class struct_rpc_ctrl_set_zbc_stencil_clear_v27_06(Struct): pass +class struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06(Struct): pass +NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06 = struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06 +struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06._fields_ = [ + ('stencil', NvU32), + ('format', NvU32), + ('bSkipL2Table', NvBool), +] +struct_rpc_ctrl_set_zbc_stencil_clear_v27_06._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('setZbcStencilClr', NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06), +] +rpc_ctrl_set_zbc_stencil_clear_v27_06 = struct_rpc_ctrl_set_zbc_stencil_clear_v27_06 +rpc_ctrl_set_zbc_stencil_clear_v = struct_rpc_ctrl_set_zbc_stencil_clear_v27_06 +class struct_rpc_ctrl_gpfifo_schedule_v1A_0A(Struct): pass +class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(Struct): pass +NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 +struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00._fields_ = [ + ('bEnable', NvBool), +] +struct_rpc_ctrl_gpfifo_schedule_v1A_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvU32), + ('gpfifoSchedule', NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00), +] +rpc_ctrl_gpfifo_schedule_v1A_0A = struct_rpc_ctrl_gpfifo_schedule_v1A_0A +rpc_ctrl_gpfifo_schedule_v = struct_rpc_ctrl_gpfifo_schedule_v1A_0A +class struct_rpc_ctrl_set_timeslice_v1A_0A(Struct): pass +class struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(Struct): pass +NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 = struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 +struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00._fields_ = [ + ('timesliceUs', NvU64), +] +struct_rpc_ctrl_set_timeslice_v1A_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('setTimeSlice', NVA06C_CTRL_TIMESLICE_PARAMS_v06_00), +] +rpc_ctrl_set_timeslice_v1A_0A = struct_rpc_ctrl_set_timeslice_v1A_0A +rpc_ctrl_set_timeslice_v = struct_rpc_ctrl_set_timeslice_v1A_0A +class struct_rpc_ctrl_fifo_disable_channels_v1A_0A(Struct): pass +class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(Struct): pass +NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 +struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00._fields_ = [ + ('bDisable', NvBool), + ('numChannels', NvU32), + ('bOnlyDisableScheduling', NvBool), + ('bRewindGpPut', NvBool), + ('pRunlistPreemptEvent', NvP64), + ('hClientList', (NvHandle * 64)), + ('hChannelList', (NvHandle * 64)), +] +struct_rpc_ctrl_fifo_disable_channels_v1A_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('fifoDisableChannels', NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00), +] +rpc_ctrl_fifo_disable_channels_v1A_0A = struct_rpc_ctrl_fifo_disable_channels_v1A_0A +rpc_ctrl_fifo_disable_channels_v = struct_rpc_ctrl_fifo_disable_channels_v1A_0A +class struct_rpc_ctrl_preempt_v1A_0A(Struct): pass +class struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(Struct): pass +NVA06C_CTRL_PREEMPT_PARAMS_v09_0A = struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A +struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A._fields_ = [ + ('bWait', NvBool), + ('bManualTimeout', NvBool), + ('timeoutUs', NvU32), +] +struct_rpc_ctrl_preempt_v1A_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmdPreempt', NVA06C_CTRL_PREEMPT_PARAMS_v09_0A), +] +rpc_ctrl_preempt_v1A_0A = struct_rpc_ctrl_preempt_v1A_0A +rpc_ctrl_preempt_v = struct_rpc_ctrl_preempt_v1A_0A +class struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A(Struct): pass +class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(Struct): pass +NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 +struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02._fields_ = [ + ('tsgInterleaveLevel', NvU32), +] +struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('interleaveLevelTSG', NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02), +] +rpc_ctrl_set_tsg_interleave_level_v1A_0A = struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A +rpc_ctrl_set_tsg_interleave_level_v = struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A +class struct_rpc_ctrl_set_channel_interleave_level_v1A_0A(Struct): pass +class struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(Struct): pass +NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 = struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 +struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02._fields_ = [ + ('channelInterleaveLevel', NvU32), +] +struct_rpc_ctrl_set_channel_interleave_level_v1A_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('interleaveLevelChannel', NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02), +] +rpc_ctrl_set_channel_interleave_level_v1A_0A = struct_rpc_ctrl_set_channel_interleave_level_v1A_0A +rpc_ctrl_set_channel_interleave_level_v = struct_rpc_ctrl_set_channel_interleave_level_v1A_0A +class struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E(Struct): pass +class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(Struct): pass +NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 +struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01._fields_ = [ + ('flags', NvU32), + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtrs', (NvU64 * 8)), + ('gfxpPreemptMode', NvU32), + ('cilpPreemptMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), +] +struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01), +] +rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E = struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E +class struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07(Struct): pass +class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07(Struct): pass +NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07 = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07 +struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07._fields_ = [ + ('flags', NvU32), + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtrs', (NvU64 * 9)), + ('gfxpPreemptMode', NvU32), + ('cilpPreemptMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), +] +struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07), +] +rpc_ctrl_gr_ctxsw_preemption_bind_v28_07 = struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07 +rpc_ctrl_gr_ctxsw_preemption_bind_v = struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07 +class struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E(Struct): pass +class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(Struct): pass +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 +struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01._fields_ = [ + ('flags', NvU32), + ('hChannel', NvHandle), + ('gfxpPreemptMode', NvU32), + ('cilpPreemptMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), +] +struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01), +] +rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E = struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E +rpc_ctrl_gr_set_ctxsw_preemption_mode_v = struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E +class struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E(Struct): pass +class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(Struct): pass +NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 +struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtr', NvU64), + ('zcullMode', NvU32), +] +struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00), +] +rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E = struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E +rpc_ctrl_gr_ctxsw_zcull_bind_v = struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E +class struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E(Struct): pass +class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(Struct): pass +NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 = struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 +struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00._fields_ = [ + ('engineType', NvU32), + ('hClient', NvHandle), + ('ChID', NvU32), + ('hChanClient', NvHandle), + ('hObject', NvHandle), + ('hVirtMemory', NvHandle), + ('physAddress', NvU64), + ('physAttr', NvU32), + ('hDmaHandle', NvHandle), + ('index', NvU32), + ('size', NvU64), +] +struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00), +] +rpc_ctrl_gpu_initialize_ctx_v1A_0E = struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E +rpc_ctrl_gpu_initialize_ctx_v = struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E +class struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04(Struct): pass +class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(Struct): pass +NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 +class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04(Struct): pass +NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04._fields_ = [ + ('physAddress', NvU64), + ('size', NvU64), + ('aperture', NvU32), + ('pageShift', NvU8), +] +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('pageSize', NvU64), + ('virtAddrLo', NvU64), + ('virtAddrHi', NvU64), + ('numLevelsToCopy', NvU32), + ('levels', (NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 * 6)), +] +struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04), +] +rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 = struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 +rpc_ctrl_vaspace_copy_server_reserved_pdes_v = struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 +class struct_rpc_ctrl_mc_service_interrupts_v1A_0E(Struct): pass +class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(Struct): pass +NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 = struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 +struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01._fields_ = [ + ('engines', NvU32), +] +struct_rpc_ctrl_mc_service_interrupts_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01), +] +rpc_ctrl_mc_service_interrupts_v1A_0E = struct_rpc_ctrl_mc_service_interrupts_v1A_0E +rpc_ctrl_mc_service_interrupts_v = struct_rpc_ctrl_mc_service_interrupts_v1A_0E +class struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D(Struct): pass +struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D._fields_ = [ + ('iter', NvU8), + ('gpuIds', (NvU32 * 32)), + ('gpuCount', NvU32), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), + ('busPeerIds', (NvU32 * 512)), +] +rpc_ctrl_get_p2p_caps_v2_v1F_0D = struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D +rpc_ctrl_get_p2p_caps_v2_v = struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D +class struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02(Struct): pass +class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(Struct): pass +NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 = struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 +class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02(Struct): pass +NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 = struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 +struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02._fields_ = [ + ('gpuId', NvU32), + ('gpuUuid', (NvU8 * 16)), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), + ('busPeerId', NvU32), +] +struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02._fields_ = [ + ('bAllCaps', NvBool), + ('bUseUuid', NvBool), + ('peerGpuCount', NvU32), + ('peerGpuCaps', (NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 * 32)), +] +struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02._fields_ = [ + ('ctrlParams', NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02), +] +rpc_ctrl_subdevice_get_p2p_caps_v21_02 = struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +rpc_ctrl_subdevice_get_p2p_caps_v = struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +class struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03(Struct): pass +class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03(Struct): pass +NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03 = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03 +struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03._fields_ = [ + ('allocatedSize', NvU64), + ('peakAllocatedSize', NvU64), + ('managedSize', NvU64), + ('allocationCount', NvU32), + ('peakAllocationCount', NvU32), +] +struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03), +] +rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03 = struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03 +class struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06(Struct): pass +class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06(Struct): pass +NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06 = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06 +struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06._fields_ = [ + ('allocatedSize', NvU64), + ('peakAllocatedSize', NvU64), + ('managedSize', NvU64), + ('allocationCount', NvU32), + ('peakAllocationCount', NvU32), + ('largestFreeChunkSize', NvU64), +] +struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06), +] +rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06 = struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06 +rpc_ctrl_subdevice_get_vgpu_heap_stats_v = struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06 +class struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C(Struct): pass +class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(Struct): pass +NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 = struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 +struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00._fields_ = [ + ('hTargetChannel', NvHandle), + ('numSMsToClear', NvU32), +] +struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00), +] +rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C = struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C +rpc_ctrl_dbg_clear_all_sm_error_states_v = struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C +class struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06(Struct): pass +class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(Struct): pass +NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 = struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 +class struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06(Struct): pass +NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 = struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 +struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06._fields_ = [ + ('hwwGlobalEsr', NvU32), + ('hwwWarpEsr', NvU32), + ('hwwWarpEsrPc', NvU32), + ('hwwGlobalEsrReportMask', NvU32), + ('hwwWarpEsrReportMask', NvU32), + ('hwwEsrAddr', NvU64), + ('hwwWarpEsrPc64', NvU64), + ('hwwCgaEsr', NvU32), + ('hwwCgaEsrReportMask', NvU32), +] +class struct_NV83DE_MMU_FAULT_INFO_v16_03(Struct): pass +NV83DE_MMU_FAULT_INFO_v16_03 = struct_NV83DE_MMU_FAULT_INFO_v16_03 +struct_NV83DE_MMU_FAULT_INFO_v16_03._fields_ = [ + ('valid', NvBool), + ('faultInfo', NvU32), +] +struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06._fields_ = [ + ('hTargetChannel', NvHandle), + ('numSMsToRead', NvU32), + ('smErrorStateArray', (NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 * 80)), + ('mmuFaultInfo', NvU32), + ('mmuFault', NV83DE_MMU_FAULT_INFO_v16_03), + ('startingSM', NvU32), +] +struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06), +] +rpc_ctrl_dbg_read_all_sm_error_states_v21_06 = struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 +rpc_ctrl_dbg_read_all_sm_error_states_v = struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 +class struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C(Struct): pass +class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(Struct): pass +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 = struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 +struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00._fields_ = [ + ('exceptionMask', NvU32), +] +struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00), +] +rpc_ctrl_dbg_set_exception_mask_v1A_0C = struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C +rpc_ctrl_dbg_set_exception_mask_v = struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C +class struct_rpc_ctrl_gpu_promote_ctx_v1A_20(Struct): pass +class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(Struct): pass +NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 = struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 +class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20(Struct): pass +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 = struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 +struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20._fields_ = [ + ('gpuPhysAddr', NvU64), + ('gpuVirtAddr', NvU64), + ('size', NvU64), + ('physAttr', NvU32), + ('bufferId', NvU16), + ('bInitialize', NvU8), + ('bNonmapped', NvU8), +] +struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20._fields_ = [ + ('engineType', NvU32), + ('hClient', NvHandle), + ('ChID', NvU32), + ('hChanClient', NvHandle), + ('hObject', NvHandle), + ('hVirtMemory', NvHandle), + ('virtAddress', NvU64), + ('size', NvU64), + ('entryCount', NvU32), + ('promoteEntry', (NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 * 16)), +] +struct_rpc_ctrl_gpu_promote_ctx_v1A_20._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('promoteCtx', NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20), +] +rpc_ctrl_gpu_promote_ctx_v1A_20 = struct_rpc_ctrl_gpu_promote_ctx_v1A_20 +rpc_ctrl_gpu_promote_ctx_v = struct_rpc_ctrl_gpu_promote_ctx_v1A_20 +class struct_rpc_ctrl_dbg_suspend_context_v1A_10(Struct): pass +class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(Struct): pass +NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 +struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06._fields_ = [ + ('waitForEvent', NvU32), + ('hResidentChannel', NvHandle), +] +struct_rpc_ctrl_dbg_suspend_context_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06), +] +rpc_ctrl_dbg_suspend_context_v1A_10 = struct_rpc_ctrl_dbg_suspend_context_v1A_10 +rpc_ctrl_dbg_suspend_context_v = struct_rpc_ctrl_dbg_suspend_context_v1A_10 +class struct_rpc_ctrl_dbg_resume_context_v1A_10(Struct): pass +struct_rpc_ctrl_dbg_resume_context_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), +] +rpc_ctrl_dbg_resume_context_v1A_10 = struct_rpc_ctrl_dbg_resume_context_v1A_10 +rpc_ctrl_dbg_resume_context_v = struct_rpc_ctrl_dbg_resume_context_v1A_10 +class struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10(Struct): pass +class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(Struct): pass +NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 = struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 +struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06._fields_ = [ + ('bNonTransactional', NvBool), + ('regOpCount', NvU32), + ('regOps', (NV2080_CTRL_GPU_REG_OP_v03_00 * 100)), +] +struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06), +] +rpc_ctrl_dbg_exec_reg_ops_v1A_10 = struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10 +rpc_ctrl_dbg_exec_reg_ops_v = struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10 +class struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10(Struct): pass +class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(Struct): pass +NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 +struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06._fields_ = [ + ('action', NvU32), +] +struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06), +] +rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 = struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 +rpc_ctrl_dbg_set_mode_mmu_debug_v = struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 +class struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07(Struct): pass +class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(Struct): pass +NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 +struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07._fields_ = [ + ('action', NvU32), +] +struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07), +] +rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07 = struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07 +rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v = struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07 +class struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06(Struct): pass +class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(Struct): pass +NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 = struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 +struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06._fields_ = [ + ('hTargetChannel', NvHandle), + ('smID', NvU32), + ('smErrorState', NV83DE_SM_ERROR_STATE_REGISTERS_v21_06), +] +struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06), +] +rpc_ctrl_dbg_read_single_sm_error_state_v21_06 = struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 +rpc_ctrl_dbg_read_single_sm_error_state_v = struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 +class struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10(Struct): pass +class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(Struct): pass +NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 = struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 +struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06._fields_ = [ + ('hTargetChannel', NvHandle), + ('smID', NvU32), +] +struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06), +] +rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 = struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 +rpc_ctrl_dbg_clear_single_sm_error_state_v = struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 +class struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10(Struct): pass +class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(Struct): pass +NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 = struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 +struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06._fields_ = [ + ('action', NvU32), +] +struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06), +] +rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 = struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 +rpc_ctrl_dbg_set_mode_errbar_debug_v = struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 +class struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10(Struct): pass +class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(Struct): pass +NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 = struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 +struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06._fields_ = [ + ('stopTriggerType', NvU32), +] +struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06), +] +rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 = struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 +rpc_ctrl_dbg_set_next_stop_trigger_type_v = struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 +class struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E(Struct): pass +class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(Struct): pass +NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 +struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00._fields_ = [ + ('hVASpace', NvHandle), +] +struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00), +] +rpc_ctrl_dma_set_default_vaspace_v1A_0E = struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E +rpc_ctrl_dma_set_default_vaspace_v = struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E +class struct_rpc_ctrl_get_ce_pce_mask_v1A_0E(Struct): pass +class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(Struct): pass +NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 +struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07._fields_ = [ + ('ceEngineType', NvU32), + ('pceMask', NvU32), +] +struct_rpc_ctrl_get_ce_pce_mask_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07), +] +rpc_ctrl_get_ce_pce_mask_v1A_0E = struct_rpc_ctrl_get_ce_pce_mask_v1A_0E +rpc_ctrl_get_ce_pce_mask_v = struct_rpc_ctrl_get_ce_pce_mask_v1A_0E +class struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E(Struct): pass +class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(Struct): pass +NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 = struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 +class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07(Struct): pass +NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 = struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 +struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07._fields_ = [ + ('colorFB', (NvU32 * 4)), + ('colorDS', (NvU32 * 4)), + ('depth', NvU32), + ('stencil', NvU32), +] +enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE = CEnum(ctypes.c_uint32) +NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID = enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE.define('NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID', 0) +NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR = enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE.define('NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR', 1) +NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH = enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE.define('NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH', 2) +NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL = enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE.define('NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL', 3) +NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT = enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE.define('NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT', 4) + +NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE = enum_NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE +struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07._fields_ = [ + ('value', NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07), + ('format', NvU32), + ('index', NvU32), + ('bIndexValid', NvBool), + ('tableType', NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE), +] +struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07), +] +rpc_ctrl_get_zbc_clear_table_entry_v1A_0E = struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E +rpc_ctrl_get_zbc_clear_table_entry_v = struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E +class struct_rpc_ctrl_get_nvlink_status_v23_04(Struct): pass +class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(Struct): pass +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 +class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D(Struct): pass +NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D +class struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02(Struct): pass +NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 = struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 +struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02._fields_ = [ + ('deviceIdFlags', NvU32), + ('domain', NvU32), + ('bus', NvU16), + ('device', NvU16), + ('function', NvU16), + ('pciDeviceId', NvU32), + ('deviceType', NvU64), + ('deviceUUID', (NvU8 * 16)), +] +struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D._fields_ = [ + ('capsTbl', NvU32), + ('phyType', NvU8), + ('subLinkWidth', NvU8), + ('linkState', NvU32), + ('rxSublinkStatus', NvU8), + ('txSublinkStatus', NvU8), + ('nvlinkVersion', NvU8), + ('nciVersion', NvU8), + ('phyVersion', NvU8), + ('nvlinkLinkClockKHz', NvU32), + ('nvlinkLineRateMbps', NvU32), + ('connected', NvBool), + ('remoteDeviceLinkNumber', NvU8), + ('localDeviceLinkNumber', NvU8), + ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02), + ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02), +] +struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04._fields_ = [ + ('enabledLinkMask', NvU32), + ('linkInfo', (NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D * 24)), +] +struct_rpc_ctrl_get_nvlink_status_v23_04._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04), +] +rpc_ctrl_get_nvlink_status_v23_04 = struct_rpc_ctrl_get_nvlink_status_v23_04 +class struct_rpc_ctrl_get_nvlink_status_v28_09(Struct): pass +class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09(Struct): pass +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09 = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09 +class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09(Struct): pass +NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09 = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09 +class struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09(Struct): pass +NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09 = struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09 +struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09._fields_ = [ + ('deviceIdFlags', NvU32), + ('domain', NvU32), + ('bus', NvU16), + ('device', NvU16), + ('function', NvU16), + ('pciDeviceId', NvU32), + ('deviceType', NvU64), + ('deviceUUID', (NvU8 * 16)), + ('fabricRecoveryStatusMask', NvU32), +] +struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09._fields_ = [ + ('capsTbl', NvU32), + ('phyType', NvU8), + ('subLinkWidth', NvU8), + ('linkState', NvU32), + ('rxSublinkStatus', NvU8), + ('txSublinkStatus', NvU8), + ('nvlinkVersion', NvU8), + ('nciVersion', NvU8), + ('phyVersion', NvU8), + ('nvlinkLinkClockKHz', NvU32), + ('nvlinkLineRateMbps', NvU32), + ('connected', NvBool), + ('remoteDeviceLinkNumber', NvU8), + ('localDeviceLinkNumber', NvU8), + ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09), + ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09), +] +struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09._fields_ = [ + ('enabledLinkMask', NvU32), + ('linkInfo', (NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09 * 24)), +] +struct_rpc_ctrl_get_nvlink_status_v28_09._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09), +] +rpc_ctrl_get_nvlink_status_v28_09 = struct_rpc_ctrl_get_nvlink_status_v28_09 +rpc_ctrl_get_nvlink_status_v = struct_rpc_ctrl_get_nvlink_status_v28_09 +class struct_rpc_ctrl_get_p2p_caps_v1F_0D(Struct): pass +class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(Struct): pass +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D +struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D._fields_ = [ + ('gpuIds', (NvU32 * 32)), + ('gpuCount', NvU32), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), +] +struct_rpc_ctrl_get_p2p_caps_v1F_0D._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D), +] +rpc_ctrl_get_p2p_caps_v1F_0D = struct_rpc_ctrl_get_p2p_caps_v1F_0D +rpc_ctrl_get_p2p_caps_v = struct_rpc_ctrl_get_p2p_caps_v1F_0D +class struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E(Struct): pass +class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(Struct): pass +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A +class struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A(Struct): pass +NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A = struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A +struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A._fields_ = [ + ('array', (NvU32 * 8)), +] +struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A._fields_ = [ + ('grpACount', NvU32), + ('grpBCount', NvU32), + ('gpuIdGrpA', (NvU32 * 8)), + ('gpuIdGrpB', (NvU32 * 8)), + ('p2pCaps', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8)), + ('a2bOptimalReadCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8)), + ('a2bOptimalWriteCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8)), + ('b2aOptimalReadCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8)), + ('b2aOptimalWriteCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8)), +] +struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A), +] +rpc_ctrl_get_p2p_caps_matrix_v1A_0E = struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E +rpc_ctrl_get_p2p_caps_matrix_v = struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E +class struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F(Struct): pass +class struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(Struct): pass +NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F = struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F +struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F._fields_ = [ + ('ctxsw', NvBool), +] +struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F), +] +rpc_ctrl_reserve_pm_area_smpc_v1A_0F = struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F +rpc_ctrl_reserve_pm_area_smpc_v = struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F +class struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F(Struct): pass +class struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(Struct): pass +NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F = struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F +struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F._fields_ = [ + ('ctxsw', NvBool), +] +struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F), +] +rpc_ctrl_reserve_hwpm_legacy_v1A_0F = struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F +rpc_ctrl_reserve_hwpm_legacy_v = struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F +class struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F(Struct): pass +class struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(Struct): pass +NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F = struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F +enum_NVB0CC_REGOPS_MODE = CEnum(ctypes.c_uint32) +NVB0CC_REGOPS_MODE_ALL_OR_NONE = enum_NVB0CC_REGOPS_MODE.define('NVB0CC_REGOPS_MODE_ALL_OR_NONE', 0) +NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = enum_NVB0CC_REGOPS_MODE.define('NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR', 1) + +NVB0CC_REGOPS_MODE = enum_NVB0CC_REGOPS_MODE +struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F._fields_ = [ + ('regOpCount', NvU32), + ('mode', NVB0CC_REGOPS_MODE), + ('bPassed', NvBool), + ('bDirect', NvBool), + ('regOps', (NV2080_CTRL_GPU_REG_OP_v03_00 * 124)), +] +struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F), +] +rpc_ctrl_b0cc_exec_reg_ops_v1A_0F = struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F +rpc_ctrl_b0cc_exec_reg_ops_v = struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F +class struct_rpc_ctrl_bind_pm_resources_v1A_0F(Struct): pass +struct_rpc_ctrl_bind_pm_resources_v1A_0F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), +] +rpc_ctrl_bind_pm_resources_v1A_0F = struct_rpc_ctrl_bind_pm_resources_v1A_0F +rpc_ctrl_bind_pm_resources_v = struct_rpc_ctrl_bind_pm_resources_v1A_0F +class struct_rpc_ctrl_alloc_pma_stream_v1A_14(Struct): pass +class struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(Struct): pass +NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 = struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 +struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14._fields_ = [ + ('hMemPmaBuffer', NvHandle), + ('pmaBufferOffset', NvU64), + ('pmaBufferSize', NvU64), + ('hMemPmaBytesAvailable', NvHandle), + ('pmaBytesAvailableOffset', NvU64), + ('ctxsw', NvBool), + ('pmaChannelIdx', NvU32), + ('pmaBufferVA', NvU64), +] +struct_rpc_ctrl_alloc_pma_stream_v1A_14._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14), +] +rpc_ctrl_alloc_pma_stream_v1A_14 = struct_rpc_ctrl_alloc_pma_stream_v1A_14 +rpc_ctrl_alloc_pma_stream_v = struct_rpc_ctrl_alloc_pma_stream_v1A_14 +class struct_rpc_ctrl_pma_stream_update_get_put_v1A_14(Struct): pass +class struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(Struct): pass +NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 = struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 +struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14._fields_ = [ + ('bytesConsumed', NvU64), + ('bUpdateAvailableBytes', NvBool), + ('bWait', NvBool), + ('bytesAvailable', NvU64), + ('bReturnPut', NvBool), + ('putPtr', NvU64), + ('pmaChannelIdx', NvU32), +] +struct_rpc_ctrl_pma_stream_update_get_put_v1A_14._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14), +] +rpc_ctrl_pma_stream_update_get_put_v1A_14 = struct_rpc_ctrl_pma_stream_update_get_put_v1A_14 +rpc_ctrl_pma_stream_update_get_put_v = struct_rpc_ctrl_pma_stream_update_get_put_v1A_14 +class struct_rpc_ctrl_fb_get_info_v2_v25_0A(Struct): pass +class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(Struct): pass +NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A +class struct_NV2080_CTRL_FB_INFO_v1A_15(Struct): pass +NV2080_CTRL_FB_INFO_v1A_15 = struct_NV2080_CTRL_FB_INFO_v1A_15 +struct_NV2080_CTRL_FB_INFO_v1A_15._fields_ = [ + ('index', NvU32), + ('data', NvU32), +] +struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A._fields_ = [ + ('fbInfoListSize', NvU32), + ('fbInfoList', (NV2080_CTRL_FB_INFO_v1A_15 * 55)), +] +struct_rpc_ctrl_fb_get_info_v2_v25_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A), +] +rpc_ctrl_fb_get_info_v2_v25_0A = struct_rpc_ctrl_fb_get_info_v2_v25_0A +class struct_rpc_ctrl_fb_get_info_v2_v27_00(Struct): pass +class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00(Struct): pass +NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00 = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00 +struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00._fields_ = [ + ('fbInfoListSize', NvU32), + ('fbInfoList', (NV2080_CTRL_FB_INFO_v1A_15 * 57)), +] +struct_rpc_ctrl_fb_get_info_v2_v27_00._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00), +] +rpc_ctrl_fb_get_info_v2_v27_00 = struct_rpc_ctrl_fb_get_info_v2_v27_00 +rpc_ctrl_fb_get_info_v2_v = struct_rpc_ctrl_fb_get_info_v2_v27_00 +class struct_rpc_ctrl_fifo_set_channel_properties_v1A_16(Struct): pass +class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(Struct): pass +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 +struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00._fields_ = [ + ('hChannel', NvHandle), + ('property', NvU32), + ('value', NvU64), +] +struct_rpc_ctrl_fifo_set_channel_properties_v1A_16._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00), +] +rpc_ctrl_fifo_set_channel_properties_v1A_16 = struct_rpc_ctrl_fifo_set_channel_properties_v1A_16 +rpc_ctrl_fifo_set_channel_properties_v = struct_rpc_ctrl_fifo_set_channel_properties_v1A_16 +class struct_rpc_ctrl_gpu_evict_ctx_v1A_1C(Struct): pass +class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00(Struct): pass +NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 = struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 +struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00._fields_ = [ + ('engineType', NvU32), + ('hClient', NvHandle), + ('ChID', NvU32), + ('hChanClient', NvHandle), + ('hObject', NvHandle), +] +struct_rpc_ctrl_gpu_evict_ctx_v1A_1C._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00), +] +rpc_ctrl_gpu_evict_ctx_v1A_1C = struct_rpc_ctrl_gpu_evict_ctx_v1A_1C +rpc_ctrl_gpu_evict_ctx_v = struct_rpc_ctrl_gpu_evict_ctx_v1A_1C +class struct_rpc_ctrl_fb_get_fs_info_v24_00(Struct): pass +class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(Struct): pass +NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 +class struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D +class union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(ctypes.Union): pass +NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D = union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D +class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D._fields_ = [ + ('data', (NvU8 * 24)), +] +class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D._fields_ = [ + ('swizzId', NvU32), + ('fbpEnMask', NvU64), +] +class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('ltcEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('ltsEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('fbpaEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('ropEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('ltcEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('ltsEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('fbpaEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('ropEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('fbpaSubpEnMask', NvU64), +] +class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('fbpaSubpEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D +struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D._fields_ = [ + ('fbpIndex', NvU32), + ('fbpLogicalIndex', NvU32), +] +union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D._fields_ = [ + ('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D), + ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D), + ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D), + ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D), + ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D), + ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D), + ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D), + ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D), + ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D), + ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D), + ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D), + ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D), + ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D), +] +struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D._fields_ = [ + ('queryType', NvU16), + ('reserved', (NvU8 * 2)), + ('status', NvU32), + ('queryParams', NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D), +] +struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00._fields_ = [ + ('numQueries', NvU16), + ('reserved', (NvU8 * 6)), + ('queries', (NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D * 120)), +] +struct_rpc_ctrl_fb_get_fs_info_v24_00._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00), +] +rpc_ctrl_fb_get_fs_info_v24_00 = struct_rpc_ctrl_fb_get_fs_info_v24_00 +class struct_rpc_ctrl_fb_get_fs_info_v26_04(Struct): pass +class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04(Struct): pass +NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04 = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04 +class struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04(Struct): pass +NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 = struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 +class union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04(ctypes.Union): pass +NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04 = union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04 +class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04(Struct): pass +NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04 = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04 +struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04._fields_ = [ + ('sysIdx', NvU32), + ('sysl2LtcEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04(Struct): pass +NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04 = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04 +struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04._fields_ = [ + ('fbpIndex', NvU32), + ('pacEnMask', NvU32), +] +class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04(Struct): pass +NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04 = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04 +struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04._fields_ = [ + ('fbpIndex', NvU32), + ('logicalLtcEnMask', NvU64), +] +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04(Struct): pass +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04 = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04 +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('logicalLtcEnMask', NvU64), +] +union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04._fields_ = [ + ('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D), + ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D), + ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D), + ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D), + ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D), + ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D), + ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D), + ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D), + ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D), + ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D), + ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D), + ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D), + ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D), + ('sysl2Ltc', NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04), + ('pac', NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04), + ('logicalLtc', NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04), + ('dmLogicalLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04), +] +struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04._fields_ = [ + ('queryType', NvU16), + ('reserved', (NvU8 * 2)), + ('status', NvU32), + ('queryParams', NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04), +] +struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04._fields_ = [ + ('numQueries', NvU16), + ('reserved', (NvU8 * 6)), + ('queries', (NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 * 120)), +] +struct_rpc_ctrl_fb_get_fs_info_v26_04._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04), +] +rpc_ctrl_fb_get_fs_info_v26_04 = struct_rpc_ctrl_fb_get_fs_info_v26_04 +rpc_ctrl_fb_get_fs_info_v = struct_rpc_ctrl_fb_get_fs_info_v26_04 +class struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D(Struct): pass +class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D +class union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(ctypes.Union): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D = union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D._fields_ = [ + ('gpcCount', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D._fields_ = [ + ('gpcId', NvU32), + ('chipletGpcMap', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D._fields_ = [ + ('gpcId', NvU32), + ('tpcMask', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D._fields_ = [ + ('gpcId', NvU32), + ('ppcMask', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D._fields_ = [ + ('swizzId', NvU32), + ('gpcId', NvU32), + ('chipletGpcMap', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D._fields_ = [ + ('chipletSyspipeMask', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D._fields_ = [ + ('swizzId', NvU16), + ('physSyspipeIdCount', NvU16), + ('physSyspipeId', (NvU8 * 8)), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D._fields_ = [ + ('swizzId', NvU32), + ('grIdx', NvU32), + ('gpcEnMask', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D._fields_ = [ + ('syspipeId', NvU32), +] +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D(Struct): pass +NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D._fields_ = [ + ('gpcId', NvU32), + ('ropMask', NvU32), +] +union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D._fields_ = [ + ('gpcCountData', NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D), + ('chipletGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D), + ('tpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D), + ('ppcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D), + ('partitionGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D), + ('syspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D), + ('partitionChipletSyspipeData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D), + ('dmGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D), + ('partitionSyspipeIdData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D), + ('ropMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D), +] +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D._fields_ = [ + ('queryType', NvU16), + ('reserved', (NvU8 * 2)), + ('status', NvU32), + ('queryData', NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D), +] +struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D._fields_ = [ + ('numQueries', NvU16), + ('reserved', (NvU8 * 6)), + ('queries', (NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D * 96)), +] +struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D), +] +rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D = struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D +rpc_ctrl_grmgr_get_gr_fs_info_v = struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D +class struct_rpc_ctrl_stop_channel_v1A_1E(Struct): pass +class struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E(Struct): pass +NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E = struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E +struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E._fields_ = [ + ('bImmediate', NvBool), +] +struct_rpc_ctrl_stop_channel_v1A_1E._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E), +] +rpc_ctrl_stop_channel_v1A_1E = struct_rpc_ctrl_stop_channel_v1A_1E +rpc_ctrl_stop_channel_v = struct_rpc_ctrl_stop_channel_v1A_1E +class struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F(Struct): pass +class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(Struct): pass +NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F +struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F._fields_ = [ + ('hChannel', NvHandle), + ('samplingMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), +] +struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F), +] +rpc_ctrl_gr_pc_sampling_mode_v1A_1F = struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F +rpc_ctrl_gr_pc_sampling_mode_v = struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F +class struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F(Struct): pass +class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(Struct): pass +NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F = struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F +class struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F(Struct): pass +PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F = struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F +struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F._fields_ = [ + ('clientActiveMask', NvU32), + ('bRegkeyLimitRatedTdp', NvU8), +] +enum_NV2080_CTRL_PERF_RATED_TDP_ACTION = CEnum(ctypes.c_uint32) +NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', 0) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', 1) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', 2) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', 3) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', 4) + +NV2080_CTRL_PERF_RATED_TDP_ACTION = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION +struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F._fields_ = [ + ('rm', PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F), + ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION), + ('inputs', (NV2080_CTRL_PERF_RATED_TDP_ACTION * 5)), +] +struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F), +] +rpc_ctrl_perf_rated_tdp_get_status_v1A_1F = struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F +rpc_ctrl_perf_rated_tdp_get_status_v = struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F +class struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F(Struct): pass +class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(Struct): pass +NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F +enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT = CEnum(ctypes.c_uint32) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', 0) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', 1) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', 2) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', 3) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', 4) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', 5) + +NV2080_CTRL_PERF_RATED_TDP_CLIENT = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT +struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F._fields_ = [ + ('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT), + ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION), +] +struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F), +] +rpc_ctrl_perf_rated_tdp_set_control_v1A_1F = struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F +rpc_ctrl_perf_rated_tdp_set_control_v = struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F +class struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F(Struct): pass +class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(Struct): pass +NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F = struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F +struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F._fields_ = [ + ('bSetMaxFreq', NvBool), +] +struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F), +] +rpc_ctrl_timer_set_gr_tick_freq_v1A_1F = struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F +rpc_ctrl_timer_set_gr_tick_freq_v = struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F +class struct_rpc_ctrl_free_pma_stream_v1A_1F(Struct): pass +class struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(Struct): pass +NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F = struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F +struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F._fields_ = [ + ('pmaChannelIdx', NvU32), +] +struct_rpc_ctrl_free_pma_stream_v1A_1F._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F), +] +rpc_ctrl_free_pma_stream_v1A_1F = struct_rpc_ctrl_free_pma_stream_v1A_1F +rpc_ctrl_free_pma_stream_v = struct_rpc_ctrl_free_pma_stream_v1A_1F +class struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23(Struct): pass +class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23(Struct): pass +NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 +struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23._fields_ = [ + ('base', NvU64), + ('size', NvU64), + ('addressSpace', NvU32), + ('cacheAttrib', NvU32), +] +struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23), +] +rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 = struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 +rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v = struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 +class struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02(Struct): pass +class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(Struct): pass +NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 +struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02._fields_ = [ + ('smID', NvU32), + ('bSingleStep', NvBool), +] +struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02), +] +rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 = struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 +rpc_ctrl_dbg_set_single_sm_single_step_v = struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 +class struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04(Struct): pass +class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(Struct): pass +NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 +enum_NV0080_CTRL_GR_TPC_PARTITION_MODE = CEnum(ctypes.c_uint32) +NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', 0) +NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', 1) +NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', 2) + +NV0080_CTRL_GR_TPC_PARTITION_MODE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE +struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04._fields_ = [ + ('hChannelGroup', NvHandle), + ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE), + ('bEnableAllTpcs', NvBool), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), +] +struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04), +] +rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 = struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 +rpc_ctrl_gr_get_tpc_partition_mode_v = struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 +class struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04(Struct): pass +struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04), +] +rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 = struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 +rpc_ctrl_gr_set_tpc_partition_mode_v = struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 +class struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07(Struct): pass +class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07(Struct): pass +NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 +class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07(Struct): pass +NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 +struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07._fields_ = [ + ('base', NvU64), + ('size', NvU64), + ('alignment', NvU64), + ('addressSpace', NvU32), + ('cpuCacheAttrib', NvU32), +] +struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07._fields_ = [ + ('methodBufferMemdesc', (NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 * 2)), + ('bar2Addr', (NvU64 * 2)), + ('numValidEntries', NvU32), +] +struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07), +] +rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 = struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 +rpc_ctrl_internal_promote_fault_method_buffers_v = struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 +class struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05(Struct): pass +class struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05(Struct): pass +NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 = struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 +struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05._fields_ = [ + ('bZbcSurfacesExist', NvBool), +] +struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05), +] +rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 = struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 +rpc_ctrl_internal_memsys_set_zbc_referenced_v = struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 +class struct_rpc_ctrl_fabric_memory_describe_v1E_0C(Struct): pass +class struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C(Struct): pass +NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C = struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C +struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C._fields_ = [ + ('offset', NvU64), + ('totalPfns', NvU64), + ('pfnArray', (NvU32 * 512)), + ('numPfns', NvU32), +] +struct_rpc_ctrl_fabric_memory_describe_v1E_0C._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C), +] +rpc_ctrl_fabric_memory_describe_v1E_0C = struct_rpc_ctrl_fabric_memory_describe_v1E_0C +rpc_ctrl_fabric_memory_describe_v = struct_rpc_ctrl_fabric_memory_describe_v1E_0C +class struct_rpc_ctrl_fabric_mem_stats_v1E_0C(Struct): pass +class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C(Struct): pass +NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C +struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C._fields_ = [ + ('totalSize', NvU64), + ('freeSize', NvU64), +] +struct_rpc_ctrl_fabric_mem_stats_v1E_0C._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C), +] +rpc_ctrl_fabric_mem_stats_v1E_0C = struct_rpc_ctrl_fabric_mem_stats_v1E_0C +rpc_ctrl_fabric_mem_stats_v = struct_rpc_ctrl_fabric_mem_stats_v1E_0C +class struct_rpc_ctrl_bus_set_p2p_mapping_v21_03(Struct): pass +class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(Struct): pass +NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 +struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03._fields_ = [ + ('connectionType', NvU32), + ('peerId', NvU32), + ('bSpaAccessOnly', NvU32), + ('bUseUuid', NvBool), + ('remoteGpuId', NvU32), + ('remoteGpuUuid', (NvU8 * 16)), +] +struct_rpc_ctrl_bus_set_p2p_mapping_v21_03._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03), +] +rpc_ctrl_bus_set_p2p_mapping_v21_03 = struct_rpc_ctrl_bus_set_p2p_mapping_v21_03 +class struct_rpc_ctrl_bus_set_p2p_mapping_v29_08(Struct): pass +class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08(Struct): pass +NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08 = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08 +struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08._fields_ = [ + ('connectionType', NvU32), + ('peerId', NvU32), + ('bEgmPeer', NvBool), + ('bSpaAccessOnly', NvU32), + ('bUseUuid', NvBool), + ('remoteGpuId', NvU32), + ('remoteGpuUuid', (NvU8 * 16)), +] +struct_rpc_ctrl_bus_set_p2p_mapping_v29_08._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08), +] +rpc_ctrl_bus_set_p2p_mapping_v29_08 = struct_rpc_ctrl_bus_set_p2p_mapping_v29_08 +rpc_ctrl_bus_set_p2p_mapping_v = struct_rpc_ctrl_bus_set_p2p_mapping_v29_08 +class struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03(Struct): pass +class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(Struct): pass +NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 +struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03._fields_ = [ + ('connectionType', NvU32), + ('peerId', NvU32), + ('bUseUuid', NvBool), + ('remoteGpuId', NvU32), + ('remoteGpuUuid', (NvU8 * 16)), +] +struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03), +] +rpc_ctrl_bus_unset_p2p_mapping_v21_03 = struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +rpc_ctrl_bus_unset_p2p_mapping_v = struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +class struct_rpc_ctrl_gpu_get_info_v2_v25_11(Struct): pass +class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(Struct): pass +NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 +class struct_NV2080_CTRL_GPU_INFO_v25_11(Struct): pass +NV2080_CTRL_GPU_INFO_v25_11 = struct_NV2080_CTRL_GPU_INFO_v25_11 +struct_NV2080_CTRL_GPU_INFO_v25_11._fields_ = [ + ('index', NvU32), + ('data', NvU32), +] +struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11._fields_ = [ + ('gpuInfoListSize', NvU32), + ('gpuInfoList', (NV2080_CTRL_GPU_INFO_v25_11 * 65)), +] +struct_rpc_ctrl_gpu_get_info_v2_v25_11._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11), +] +rpc_ctrl_gpu_get_info_v2_v25_11 = struct_rpc_ctrl_gpu_get_info_v2_v25_11 +rpc_ctrl_gpu_get_info_v2_v = struct_rpc_ctrl_gpu_get_info_v2_v25_11 +class struct_rpc_update_gpm_guest_buffer_info_v27_01(Struct): pass +struct_rpc_update_gpm_guest_buffer_info_v27_01._fields_ = [ + ('gpfn', NvU64), + ('swizzId', NvU32), + ('computeId', NvU32), + ('bufSize', NvU32), + ('bMap', NvBool), +] +rpc_update_gpm_guest_buffer_info_v27_01 = struct_rpc_update_gpm_guest_buffer_info_v27_01 +rpc_update_gpm_guest_buffer_info_v = struct_rpc_update_gpm_guest_buffer_info_v27_01 +class struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08(Struct): pass +class struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(Struct): pass +NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 = struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 +struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08._fields_ = [ + ('pmaChannelIdx', NvU32), + ('bMembytesPollingRequired', NvBool), +] +struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08), +] +rpc_ctrl_internal_quiesce_pma_channel_v1C_08 = struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 +rpc_ctrl_internal_quiesce_pma_channel_v = struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 +class struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C(Struct): pass +class struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(Struct): pass +NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C = struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C +struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C._fields_ = [ + ('pmaChannelIdx', NvU32), + ('pmaBufferVA', NvU64), + ('pmaBufferSize', NvU64), + ('membytesVA', NvU64), + ('hwpmIBPA', NvU64), + ('hwpmIBAperture', NvU8), +] +struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C), +] +rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C = struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C +rpc_ctrl_internal_sriov_promote_pma_stream_v = struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C +class struct_rpc_ctrl_exec_partitions_create_v24_05(Struct): pass +class struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05(Struct): pass +NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 = struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 +class struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05(Struct): pass +NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 = struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 +struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05._fields_ = [ + ('gpcCount', NvU32), + ('gfxGpcCount', NvU32), + ('veidCount', NvU32), + ('ceCount', NvU32), + ('nvEncCount', NvU32), + ('nvDecCount', NvU32), + ('nvJpgCount', NvU32), + ('ofaCount', NvU32), + ('sharedEngFlag', NvU32), + ('smCount', NvU32), + ('spanStart', NvU32), + ('computeSize', NvU32), +] +struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05._fields_ = [ + ('bQuery', NvBool), + ('execPartCount', NvU32), + ('execPartInfo', (NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 * 8)), + ('execPartId', (NvU32 * 8)), +] +struct_rpc_ctrl_exec_partitions_create_v24_05._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('status', NvU32), + ('execPartitionsCreate', NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05), +] +rpc_ctrl_exec_partitions_create_v24_05 = struct_rpc_ctrl_exec_partitions_create_v24_05 +rpc_ctrl_exec_partitions_create_v = struct_rpc_ctrl_exec_partitions_create_v24_05 +class struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05(Struct): pass +class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04(Struct): pass +NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 +struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04._fields_ = [ + ('imbPhysAddr', NvU64), + ('addrSpace', NvU32), + ('flaAction', NvU32), +] +struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04), +] +rpc_ctrl_fla_setup_instance_mem_block_v21_05 = struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05 +rpc_ctrl_fla_setup_instance_mem_block_v = struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05 +class struct_rpc_ctrl_get_total_hs_credits_v21_08(Struct): pass +class struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(Struct): pass +NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 = struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 +struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08._fields_ = [ + ('numCredits', NvU32), +] +struct_rpc_ctrl_get_total_hs_credits_v21_08._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08), +] +rpc_ctrl_get_total_hs_credits_v21_08 = struct_rpc_ctrl_get_total_hs_credits_v21_08 +rpc_ctrl_get_total_hs_credits_v = struct_rpc_ctrl_get_total_hs_credits_v21_08 +class struct_rpc_ctrl_get_hs_credits_v21_08(Struct): pass +class struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(Struct): pass +NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 = struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 +class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08(Struct): pass +NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 +struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08._fields_ = [ + ('status', NvU8), + ('entryIndex', NvU8), +] +class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08(Struct): pass +NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 = struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 +struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08._fields_ = [ + ('chipletType', NvU8), + ('chipletIndex', NvU8), + ('numCredits', NvU16), +] +struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08._fields_ = [ + ('pmaChannelIdx', NvU8), + ('numEntries', NvU8), + ('statusInfo', NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08), + ('creditInfo', (NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 * 63)), +] +struct_rpc_ctrl_get_hs_credits_v21_08._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08), +] +rpc_ctrl_get_hs_credits_v21_08 = struct_rpc_ctrl_get_hs_credits_v21_08 +rpc_ctrl_get_hs_credits_v = struct_rpc_ctrl_get_hs_credits_v21_08 +class struct_rpc_ctrl_reserve_hes_v29_07(Struct): pass +class struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07(Struct): pass +NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07 = struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07 +class struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07(Struct): pass +NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07 = struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07 +class struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07(Struct): pass +NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07 = struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07 +struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07._fields_ = [ + ('ctxsw', NvBool), +] +struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07._fields_ = [ + ('cwd', NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07), +] +struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07._fields_ = [ + ('type', NvU32), + ('reserveParams', NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07), +] +struct_rpc_ctrl_reserve_hes_v29_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07), +] +rpc_ctrl_reserve_hes_v29_07 = struct_rpc_ctrl_reserve_hes_v29_07 +rpc_ctrl_reserve_hes_v = struct_rpc_ctrl_reserve_hes_v29_07 +class struct_rpc_ctrl_release_hes_v29_07(Struct): pass +class struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07(Struct): pass +NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07 = struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07 +struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07._fields_ = [ + ('type', NvU32), +] +struct_rpc_ctrl_release_hes_v29_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07), +] +rpc_ctrl_release_hes_v29_07 = struct_rpc_ctrl_release_hes_v29_07 +rpc_ctrl_release_hes_v = struct_rpc_ctrl_release_hes_v29_07 +class struct_rpc_ctrl_reserve_ccu_prof_v29_07(Struct): pass +class struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07(Struct): pass +NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07 = struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07 +struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07._fields_ = [ + ('ctxsw', NvBool), +] +struct_rpc_ctrl_reserve_ccu_prof_v29_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07), +] +rpc_ctrl_reserve_ccu_prof_v29_07 = struct_rpc_ctrl_reserve_ccu_prof_v29_07 +rpc_ctrl_reserve_ccu_prof_v = struct_rpc_ctrl_reserve_ccu_prof_v29_07 +class struct_rpc_ctrl_release_ccu_prof_v29_07(Struct): pass +struct_rpc_ctrl_release_ccu_prof_v29_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), +] +rpc_ctrl_release_ccu_prof_v29_07 = struct_rpc_ctrl_release_ccu_prof_v29_07 +rpc_ctrl_release_ccu_prof_v = struct_rpc_ctrl_release_ccu_prof_v29_07 +class struct_rpc_ctrl_set_hs_credits_v21_08(Struct): pass +class struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(Struct): pass +NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 = struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 +struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08._fields_ = [ + ('pmaChannelIdx', NvU8), + ('numEntries', NvU8), + ('statusInfo', NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08), + ('creditInfo', (NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 * 63)), +] +struct_rpc_ctrl_set_hs_credits_v21_08._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08), +] +rpc_ctrl_set_hs_credits_v21_08 = struct_rpc_ctrl_set_hs_credits_v21_08 +rpc_ctrl_set_hs_credits_v = struct_rpc_ctrl_set_hs_credits_v21_08 +class struct_rpc_ctrl_pm_area_pc_sampler_v21_0B(Struct): pass +struct_rpc_ctrl_pm_area_pc_sampler_v21_0B._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvU32), +] +rpc_ctrl_pm_area_pc_sampler_v21_0B = struct_rpc_ctrl_pm_area_pc_sampler_v21_0B +rpc_ctrl_pm_area_pc_sampler_v = struct_rpc_ctrl_pm_area_pc_sampler_v21_0B +class struct_rpc_ctrl_exec_partitions_delete_v1F_0A(Struct): pass +class struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05(Struct): pass +NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 = struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 +struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05._fields_ = [ + ('execPartCount', NvU32), + ('execPartId', (NvU32 * 8)), +] +struct_rpc_ctrl_exec_partitions_delete_v1F_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('execPartitionsDelete', NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05), +] +rpc_ctrl_exec_partitions_delete_v1F_0A = struct_rpc_ctrl_exec_partitions_delete_v1F_0A +rpc_ctrl_exec_partitions_delete_v = struct_rpc_ctrl_exec_partitions_delete_v1F_0A +class struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A(Struct): pass +class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00(Struct): pass +NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 +struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00._fields_ = [ + ('workSubmitToken', NvU32), +] +struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('workSubmitToken', NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00), +] +rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A = struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A +rpc_ctrl_gpfifo_get_work_submit_token_v = struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A +class struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A(Struct): pass +class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04(Struct): pass +NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 +struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04._fields_ = [ + ('index', NvU32), +] +struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('setWorkSubmitTokenIndex', NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04), +] +rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A = struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A +rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v = struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A +class struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D(Struct): pass +class struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B(Struct): pass +NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B = struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B +struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B._fields_ = [ + ('eccMask', NvU32), + ('nvlinkMask', NvU32), +] +struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('vfErrContIntrMask', NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B), +] +rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D = struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D +rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v = struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D +class struct_rpc_save_hibernation_data_v1E_0E(Struct): pass +struct_rpc_save_hibernation_data_v1E_0E._fields_ = [ + ('remainedBytes', NvU32), + ('payload', (NvU8 * 0)), +] +rpc_save_hibernation_data_v1E_0E = struct_rpc_save_hibernation_data_v1E_0E +rpc_save_hibernation_data_v = struct_rpc_save_hibernation_data_v1E_0E +class struct_rpc_restore_hibernation_data_v1E_0E(Struct): pass +struct_rpc_restore_hibernation_data_v1E_0E._fields_ = [ + ('remainedBytes', NvU32), + ('payload', (NvU8 * 0)), +] +rpc_restore_hibernation_data_v1E_0E = struct_rpc_restore_hibernation_data_v1E_0E +rpc_restore_hibernation_data_v = struct_rpc_restore_hibernation_data_v1E_0E +class struct_rpc_ctrl_get_mmu_debug_mode_v1E_06(Struct): pass +class struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(Struct): pass +NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 = struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 +struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06._fields_ = [ + ('bMode', NvBool), +] +struct_rpc_ctrl_get_mmu_debug_mode_v1E_06._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06), +] +rpc_ctrl_get_mmu_debug_mode_v1E_06 = struct_rpc_ctrl_get_mmu_debug_mode_v1E_06 +rpc_ctrl_get_mmu_debug_mode_v = struct_rpc_ctrl_get_mmu_debug_mode_v1E_06 +class struct_rpc_disable_channels_v1E_0B(Struct): pass +struct_rpc_disable_channels_v1E_0B._fields_ = [ + ('bDisable', NvU32), +] +rpc_disable_channels_v1E_0B = struct_rpc_disable_channels_v1E_0B +rpc_disable_channels_v = struct_rpc_disable_channels_v1E_0B +class struct_rpc_ctrl_gpu_migratable_ops_v21_07(Struct): pass +class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(Struct): pass +NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 +struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07._fields_ = [ + ('hClientTarget', NvHandle), + ('hChannelTarget', NvHandle), + ('bNonTransactional', NvU32), + ('regOpCount', NvU32), + ('smIds', (NvU32 * 50)), + ('regOps', (NV2080_CTRL_GPU_REG_OP_v03_00 * 50)), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO_v12_01), +] +struct_rpc_ctrl_gpu_migratable_ops_v21_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07), +] +rpc_ctrl_gpu_migratable_ops_v21_07 = struct_rpc_ctrl_gpu_migratable_ops_v21_07 +rpc_ctrl_gpu_migratable_ops_v = struct_rpc_ctrl_gpu_migratable_ops_v21_07 +class struct_rpc_invalidate_tlb_v23_03(Struct): pass +struct_rpc_invalidate_tlb_v23_03._fields_ = [ + ('pdbAddress', NvU64), + ('regVal', NvU32), +] +rpc_invalidate_tlb_v23_03 = struct_rpc_invalidate_tlb_v23_03 +rpc_invalidate_tlb_v = struct_rpc_invalidate_tlb_v23_03 +class struct_rpc_get_brand_caps_v25_12(Struct): pass +struct_rpc_get_brand_caps_v25_12._fields_ = [ + ('brands', NvU32), +] +rpc_get_brand_caps_v25_12 = struct_rpc_get_brand_caps_v25_12 +rpc_get_brand_caps_v = struct_rpc_get_brand_caps_v25_12 +class struct_rpc_gsp_set_system_info_v17_00(Struct): pass +struct_rpc_gsp_set_system_info_v17_00._fields_ = [ + ('data', NvU32), +] +rpc_gsp_set_system_info_v17_00 = struct_rpc_gsp_set_system_info_v17_00 +rpc_gsp_set_system_info_v = struct_rpc_gsp_set_system_info_v17_00 +class struct_rpc_gsp_rm_alloc_v03_00(Struct): pass +struct_rpc_gsp_rm_alloc_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClass', NvU32), + ('status', NvU32), + ('paramsSize', NvU32), + ('flags', NvU32), + ('reserved', (NvU8 * 4)), + ('params', (NvU8 * 0)), +] +rpc_gsp_rm_alloc_v03_00 = struct_rpc_gsp_rm_alloc_v03_00 +rpc_gsp_rm_alloc_v = struct_rpc_gsp_rm_alloc_v03_00 +class struct_rpc_gsp_rm_control_v03_00(Struct): pass +struct_rpc_gsp_rm_control_v03_00._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvU32), + ('status', NvU32), + ('paramsSize', NvU32), + ('flags', NvU32), + ('params', (NvU8 * 0)), +] +rpc_gsp_rm_control_v03_00 = struct_rpc_gsp_rm_control_v03_00 +rpc_gsp_rm_control_v = struct_rpc_gsp_rm_control_v03_00 +class struct_rpc_dump_protobuf_component_v18_12(Struct): pass +struct_rpc_dump_protobuf_component_v18_12._fields_ = [ + ('component', NvU16), + ('nvDumpType', NvU8), + ('countOnly', NvBool), + ('bugCheckCode', NvU32), + ('internalCode', NvU32), + ('bufferSize', NvU32), + ('blob', (NvU8 * 0)), +] +rpc_dump_protobuf_component_v18_12 = struct_rpc_dump_protobuf_component_v18_12 +rpc_dump_protobuf_component_v = struct_rpc_dump_protobuf_component_v18_12 +class struct_rpc_run_cpu_sequencer_v17_00(Struct): pass +struct_rpc_run_cpu_sequencer_v17_00._fields_ = [ + ('bufferSizeDWord', NvU32), + ('cmdIndex', NvU32), + ('regSaveArea', (NvU32 * 8)), + ('commandBuffer', (NvU32 * 0)), +] +rpc_run_cpu_sequencer_v17_00 = struct_rpc_run_cpu_sequencer_v17_00 +rpc_run_cpu_sequencer_v = struct_rpc_run_cpu_sequencer_v17_00 +class struct_rpc_post_event_v17_00(Struct): pass +struct_rpc_post_event_v17_00._fields_ = [ + ('hClient', NvHandle), + ('hEvent', NvHandle), + ('notifyIndex', NvU32), + ('data', NvU32), + ('info16', NvU16), + ('status', NvU32), + ('eventDataSize', NvU32), + ('bNotifyList', NvBool), + ('eventData', (NvU8 * 0)), +] +rpc_post_event_v17_00 = struct_rpc_post_event_v17_00 +rpc_post_event_v = struct_rpc_post_event_v17_00 +class struct_rpc_rc_triggered_v17_02(Struct): pass +struct_rpc_rc_triggered_v17_02._fields_ = [ + ('nv2080EngineType', NvU32), + ('chid', NvU32), + ('gfid', NvU32), + ('exceptLevel', NvU32), + ('exceptType', NvU32), + ('scope', NvU32), + ('partitionAttributionId', NvU16), + ('mmuFaultAddrLo', NvU32), + ('mmuFaultAddrHi', NvU32), + ('mmuFaultType', NvU32), + ('bCallbackNeeded', NvBool), + ('rcJournalBufferSize', NvU32), + ('rcJournalBuffer', (NvU8 * 0)), +] +rpc_rc_triggered_v17_02 = struct_rpc_rc_triggered_v17_02 +rpc_rc_triggered_v = struct_rpc_rc_triggered_v17_02 +class struct_rpc_os_error_log_v17_00(Struct): pass +struct_rpc_os_error_log_v17_00._fields_ = [ + ('exceptType', NvU32), + ('runlistId', NvU32), + ('chid', NvU32), + ('errString', (ctypes.c_char * 256)), +] +rpc_os_error_log_v17_00 = struct_rpc_os_error_log_v17_00 +rpc_os_error_log_v = struct_rpc_os_error_log_v17_00 +class struct_rpc_rg_line_intr_v17_00(Struct): pass +struct_rpc_rg_line_intr_v17_00._fields_ = [ + ('head', NvU32), + ('rgIntr', NvU32), +] +rpc_rg_line_intr_v17_00 = struct_rpc_rg_line_intr_v17_00 +rpc_rg_line_intr_v = struct_rpc_rg_line_intr_v17_00 +class struct_rpc_display_modeset_v01_00(Struct): pass +struct_rpc_display_modeset_v01_00._fields_ = [ + ('bModesetStart', NvBool), + ('minRequiredIsoBandwidthKBPS', NvU32), + ('minRequiredFloorBandwidthKBPS', NvU32), +] +rpc_display_modeset_v01_00 = struct_rpc_display_modeset_v01_00 +rpc_display_modeset_v = struct_rpc_display_modeset_v01_00 +class struct_rpc_gpuacct_perfmon_util_samples_v1F_0E(Struct): pass +class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E(Struct): pass +NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E = struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E +struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E._fields_ = [ + ('type', NvU8), + ('bufSize', NvU32), + ('count', NvU32), + ('tracker', NvU32), + ('samples', (NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E * 72)), +] +struct_rpc_gpuacct_perfmon_util_samples_v1F_0E._fields_ = [ + ('params', NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E), +] +rpc_gpuacct_perfmon_util_samples_v1F_0E = struct_rpc_gpuacct_perfmon_util_samples_v1F_0E +rpc_gpuacct_perfmon_util_samples_v = struct_rpc_gpuacct_perfmon_util_samples_v1F_0E +class struct_rpc_vgpu_gsp_plugin_triggered_v17_00(Struct): pass +struct_rpc_vgpu_gsp_plugin_triggered_v17_00._fields_ = [ + ('gfid', NvU32), + ('notifyIndex', NvU32), +] +rpc_vgpu_gsp_plugin_triggered_v17_00 = struct_rpc_vgpu_gsp_plugin_triggered_v17_00 +rpc_vgpu_gsp_plugin_triggered_v = struct_rpc_vgpu_gsp_plugin_triggered_v17_00 +class struct_rpc_vgpu_config_event_v17_00(Struct): pass +struct_rpc_vgpu_config_event_v17_00._fields_ = [ + ('notifyIndex', NvU32), +] +rpc_vgpu_config_event_v17_00 = struct_rpc_vgpu_config_event_v17_00 +rpc_vgpu_config_event_v = struct_rpc_vgpu_config_event_v17_00 +class struct_rpc_dce_rm_init_v01_00(Struct): pass +struct_rpc_dce_rm_init_v01_00._fields_ = [ + ('bInit', NvBool), + ('hInternalClient', NvU32), +] +rpc_dce_rm_init_v01_00 = struct_rpc_dce_rm_init_v01_00 +rpc_dce_rm_init_v = struct_rpc_dce_rm_init_v01_00 +class struct_rpc_sim_read_v1E_01(Struct): pass +struct_rpc_sim_read_v1E_01._fields_ = [ + ('path', (ctypes.c_char * 256)), + ('index', NvU32), + ('count', NvU32), +] +rpc_sim_read_v1E_01 = struct_rpc_sim_read_v1E_01 +rpc_sim_read_v = struct_rpc_sim_read_v1E_01 +class struct_rpc_sim_write_v1E_01(Struct): pass +struct_rpc_sim_write_v1E_01._fields_ = [ + ('path', (ctypes.c_char * 256)), + ('index', NvU32), + ('count', NvU32), + ('data', NvU32), +] +rpc_sim_write_v1E_01 = struct_rpc_sim_write_v1E_01 +rpc_sim_write_v = struct_rpc_sim_write_v1E_01 +class struct_rpc_ucode_libos_print_v1E_08(Struct): pass +struct_rpc_ucode_libos_print_v1E_08._fields_ = [ + ('ucodeEngDesc', NvU32), + ('libosPrintBufSize', NvU32), + ('libosPrintBuf', (NvU8 * 0)), +] +rpc_ucode_libos_print_v1E_08 = struct_rpc_ucode_libos_print_v1E_08 +rpc_ucode_libos_print_v = struct_rpc_ucode_libos_print_v1E_08 +class struct_rpc_init_done_v17_00(Struct): pass +struct_rpc_init_done_v17_00._fields_ = [ + ('not_used', NvU32), +] +rpc_init_done_v17_00 = struct_rpc_init_done_v17_00 +rpc_init_done_v = struct_rpc_init_done_v17_00 +class struct_rpc_semaphore_schedule_callback_v17_00(Struct): pass +struct_rpc_semaphore_schedule_callback_v17_00._fields_ = [ + ('GPUVA', NvU64), + ('hVASpace', NvU32), + ('ReleaseValue', NvU32), + ('Flags', NvU32), + ('completionStatus', NvU32), + ('hClient', NvHandle), + ('hEvent', NvHandle), +] +rpc_semaphore_schedule_callback_v17_00 = struct_rpc_semaphore_schedule_callback_v17_00 +rpc_semaphore_schedule_callback_v = struct_rpc_semaphore_schedule_callback_v17_00 +class struct_rpc_timed_semaphore_release_v01_00(Struct): pass +struct_rpc_timed_semaphore_release_v01_00._fields_ = [ + ('semaphoreVA', NvU64), + ('notifierVA', NvU64), + ('hVASpace', NvU32), + ('releaseValue', NvU32), + ('completionStatus', NvU32), + ('hClient', NvHandle), + ('hDevice', NvHandle), +] +rpc_timed_semaphore_release_v01_00 = struct_rpc_timed_semaphore_release_v01_00 +rpc_timed_semaphore_release_v = struct_rpc_timed_semaphore_release_v01_00 +class struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00(Struct): pass +class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00(Struct): pass +NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 +struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00._fields_ = [ + ('flags', NvU32), + ('bBridgeless', NvBool), + ('currLimits', (NvU32 * 2)), +] +struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00._fields_ = [ + ('params', NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00), +] +rpc_perf_gpu_boost_sync_limits_callback_v17_00 = struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00 +rpc_perf_gpu_boost_sync_limits_callback_v = struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00 +class struct_rpc_perf_bridgeless_info_update_v17_00(Struct): pass +struct_rpc_perf_bridgeless_info_update_v17_00._fields_ = [ + ('bBridgeless', NvU64), +] +rpc_perf_bridgeless_info_update_v17_00 = struct_rpc_perf_bridgeless_info_update_v17_00 +rpc_perf_bridgeless_info_update_v = struct_rpc_perf_bridgeless_info_update_v17_00 +class struct_rpc_nvlink_fault_up_v17_00(Struct): pass +struct_rpc_nvlink_fault_up_v17_00._fields_ = [ + ('linkId', NvU32), +] +rpc_nvlink_fault_up_v17_00 = struct_rpc_nvlink_fault_up_v17_00 +rpc_nvlink_fault_up_v = struct_rpc_nvlink_fault_up_v17_00 +class struct_rpc_nvlink_inband_received_data_256_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00._fields_ = [ + ('dataSize', NvU32), + ('data', (NvU8 * 256)), +] +struct_rpc_nvlink_inband_received_data_256_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00), +] +rpc_nvlink_inband_received_data_256_v17_00 = struct_rpc_nvlink_inband_received_data_256_v17_00 +rpc_nvlink_inband_received_data_256_v = struct_rpc_nvlink_inband_received_data_256_v17_00 +class struct_rpc_nvlink_inband_received_data_512_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00._fields_ = [ + ('dataSize', NvU32), + ('data', (NvU8 * 512)), +] +struct_rpc_nvlink_inband_received_data_512_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00), +] +rpc_nvlink_inband_received_data_512_v17_00 = struct_rpc_nvlink_inband_received_data_512_v17_00 +rpc_nvlink_inband_received_data_512_v = struct_rpc_nvlink_inband_received_data_512_v17_00 +class struct_rpc_nvlink_inband_received_data_1024_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00._fields_ = [ + ('dataSize', NvU32), + ('data', (NvU8 * 1024)), +] +struct_rpc_nvlink_inband_received_data_1024_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00), +] +rpc_nvlink_inband_received_data_1024_v17_00 = struct_rpc_nvlink_inband_received_data_1024_v17_00 +rpc_nvlink_inband_received_data_1024_v = struct_rpc_nvlink_inband_received_data_1024_v17_00 +class struct_rpc_nvlink_inband_received_data_2048_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00._fields_ = [ + ('dataSize', NvU32), + ('data', (NvU8 * 2048)), +] +struct_rpc_nvlink_inband_received_data_2048_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00), +] +rpc_nvlink_inband_received_data_2048_v17_00 = struct_rpc_nvlink_inband_received_data_2048_v17_00 +rpc_nvlink_inband_received_data_2048_v = struct_rpc_nvlink_inband_received_data_2048_v17_00 +class struct_rpc_nvlink_inband_received_data_4096_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00._fields_ = [ + ('dataSize', NvU32), + ('data', (NvU8 * 4096)), +] +struct_rpc_nvlink_inband_received_data_4096_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00), +] +rpc_nvlink_inband_received_data_4096_v17_00 = struct_rpc_nvlink_inband_received_data_4096_v17_00 +rpc_nvlink_inband_received_data_4096_v = struct_rpc_nvlink_inband_received_data_4096_v17_00 +class struct_rpc_nvlink_is_gpu_degraded_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00._fields_ = [ + ('linkId', NvU32), + ('bIsGpuDegraded', NvBool), +] +struct_rpc_nvlink_is_gpu_degraded_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00), +] +rpc_nvlink_is_gpu_degraded_v17_00 = struct_rpc_nvlink_is_gpu_degraded_v17_00 +rpc_nvlink_is_gpu_degraded_v = struct_rpc_nvlink_is_gpu_degraded_v17_00 +class struct_rpc_nvlink_fatal_error_recovery_v17_00(Struct): pass +class struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00(Struct): pass +NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00 = struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00 +struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00._fields_ = [ + ('bRecoverable', NvBool), + ('bLazy', NvBool), +] +struct_rpc_nvlink_fatal_error_recovery_v17_00._fields_ = [ + ('params', NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00), +] +rpc_nvlink_fatal_error_recovery_v17_00 = struct_rpc_nvlink_fatal_error_recovery_v17_00 +rpc_nvlink_fatal_error_recovery_v = struct_rpc_nvlink_fatal_error_recovery_v17_00 +class struct_rpc_update_gsp_trace_v01_00(Struct): pass +struct_rpc_update_gsp_trace_v01_00._fields_ = [ + ('records', NvU32), + ('data', NvU32), +] +rpc_update_gsp_trace_v01_00 = struct_rpc_update_gsp_trace_v01_00 +rpc_update_gsp_trace_v = struct_rpc_update_gsp_trace_v01_00 +class struct_rpc_gsp_post_nocat_record_v01_00(Struct): pass +struct_rpc_gsp_post_nocat_record_v01_00._fields_ = [ + ('data', NvU32), +] +rpc_gsp_post_nocat_record_v01_00 = struct_rpc_gsp_post_nocat_record_v01_00 +rpc_gsp_post_nocat_record_v = struct_rpc_gsp_post_nocat_record_v01_00 +class struct_rpc_extdev_intr_service_v17_00(Struct): pass +struct_rpc_extdev_intr_service_v17_00._fields_ = [ + ('lossRegStatus', NvU8), + ('gainRegStatus', NvU8), + ('miscRegStatus', NvU8), + ('rmStatus', NvBool), +] +rpc_extdev_intr_service_v17_00 = struct_rpc_extdev_intr_service_v17_00 +rpc_extdev_intr_service_v = struct_rpc_extdev_intr_service_v17_00 +class struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04(Struct): pass +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04(Struct): pass +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04(Struct): pass +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 +class union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(ctypes.Union): pass +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 = union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04(Struct): pass +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 +struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04._fields_ = [ + ('sensorId', NvU32), + ('limit', NvU32), +] +union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04._fields_ = [ + ('smbpbi', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04), +] +struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04._fields_ = [ + ('type', NvU8), + ('data', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04), +] +struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04._fields_ = [ + ('flags', NvU8), + ('syncData', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04), +] +struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04._fields_ = [ + ('params', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04), +] +rpc_pfm_req_hndlr_state_sync_callback_v21_04 = struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +rpc_pfm_req_hndlr_state_sync_callback_v = struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +class struct_rpc_vgpu_gsp_mig_ci_config_v21_03(Struct): pass +struct_rpc_vgpu_gsp_mig_ci_config_v21_03._fields_ = [ + ('execPartCount', NvU32), + ('execPartId', (NvU32 * 8)), + ('gfid', NvU32), + ('bDelete', NvBool), +] +rpc_vgpu_gsp_mig_ci_config_v21_03 = struct_rpc_vgpu_gsp_mig_ci_config_v21_03 +rpc_vgpu_gsp_mig_ci_config_v = struct_rpc_vgpu_gsp_mig_ci_config_v21_03 +class struct_rpc_gsp_lockdown_notice_v17_00(Struct): pass +struct_rpc_gsp_lockdown_notice_v17_00._fields_ = [ + ('bLockdownEngaging', NvBool), +] +rpc_gsp_lockdown_notice_v17_00 = struct_rpc_gsp_lockdown_notice_v17_00 +rpc_gsp_lockdown_notice_v = struct_rpc_gsp_lockdown_notice_v17_00 +class struct_rpc_ctrl_gpu_query_ecc_status_v24_06(Struct): pass +class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06(Struct): pass +NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06 = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06 +class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01(Struct): pass +NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 = struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 +class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01(Struct): pass +NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 = struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 +struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01._fields_ = [ + ('count', NvU64), +] +struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01._fields_ = [ + ('enabled', NvBool), + ('scrubComplete', NvBool), + ('supported', NvBool), + ('dbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), + ('dbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), + ('sbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), + ('sbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), +] +struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06._fields_ = [ + ('units', (NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 * 25)), + ('bFatalPoisonError', NvBool), + ('flags', NvU32), +] +struct_rpc_ctrl_gpu_query_ecc_status_v24_06._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06), +] +rpc_ctrl_gpu_query_ecc_status_v24_06 = struct_rpc_ctrl_gpu_query_ecc_status_v24_06 +class struct_rpc_ctrl_gpu_query_ecc_status_v26_02(Struct): pass +class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02(Struct): pass +NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02 = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02 +struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02._fields_ = [ + ('units', (NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 * 30)), + ('bFatalPoisonError', NvBool), + ('flags', NvU32), +] +struct_rpc_ctrl_gpu_query_ecc_status_v26_02._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('params', NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02), +] +rpc_ctrl_gpu_query_ecc_status_v26_02 = struct_rpc_ctrl_gpu_query_ecc_status_v26_02 +rpc_ctrl_gpu_query_ecc_status_v = struct_rpc_ctrl_gpu_query_ecc_status_v26_02 +class struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04(Struct): pass +class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(Struct): pass +NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 +struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04._fields_ = [ + ('value', NvU32), +] +struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04), +] +rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 = struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 +rpc_ctrl_dbg_get_mode_mmu_debug_v = struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 +class struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07(Struct): pass +class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(Struct): pass +NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 +struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07._fields_ = [ + ('value', NvU32), +] +struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07), +] +rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07 = struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07 +rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v = struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07 +class struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09(Struct): pass +struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09._fields_ = [ + ('bwMode', NvU8), +] +rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 = struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 +rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v = struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 +class struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C(Struct): pass +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C(Struct): pass +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C +struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C._fields_ = [ + ('dataSize', NvU32), + ('data', (NvU8 * 512)), +] +struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C._fields_ = [ + ('message_type', NvU16), + ('more', NvBool), + ('payload', NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C), +] +rpc_ctrl_nvlink_get_inband_received_data_v25_0C = struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C +rpc_ctrl_nvlink_get_inband_received_data_v = struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C +class struct_rpc_fecs_error_v26_02(Struct): pass +struct_rpc_fecs_error_v26_02._fields_ = [ + ('grIdx', NvU32), + ('error_type', NvU8), +] +rpc_fecs_error_v26_02 = struct_rpc_fecs_error_v26_02 +rpc_fecs_error_v = struct_rpc_fecs_error_v26_02 +class struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05(Struct): pass +struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05._fields_ = [ + ('buffer', (NvU8 * 1024)), + ('dataSize', NvU32), +] +rpc_ctrl_cmd_nvlink_inband_send_data_v26_05 = struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05 +rpc_ctrl_cmd_nvlink_inband_send_data_v = struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05 +class struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00(Struct): pass +struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00._fields_ = [ + ('bufferSize', NvU32), + ('tracepointMask', NvU32), + ('bufferWatermark', NvU32), + ('bufferAddr', NvU64), + ('flag', NvU8), +] +rpc_ctrl_cmd_internal_control_gsp_trace_v28_00 = struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00 +rpc_ctrl_cmd_internal_control_gsp_trace_v = struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00 +class struct_rpc_recovery_action_v28_01(Struct): pass +struct_rpc_recovery_action_v28_01._fields_ = [ + ('type', NvU32), + ('value', NvBool), +] +rpc_recovery_action_v28_01 = struct_rpc_recovery_action_v28_01 +rpc_recovery_action_v = struct_rpc_recovery_action_v28_01 +class struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02(Struct): pass +class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02(Struct): pass +NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02 = struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02 +class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02(Struct): pass +NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02 = struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02 +struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02._fields_ = [ + ('allocations', NvU32), + ('peakAllocations', NvU32), + ('objectSize', NvU64), +] +struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02._fields_ = [ + ('poolStats', (NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02 * 64)), + ('totalHeapSize', NvU64), + ('poolCount', NvU8), +] +struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('ctrlParams', NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02), +] +rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 = struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 +rpc_ctrl_subdevice_get_libos_heap_stats_v = struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 +class struct_GSP_MSG_QUEUE_ELEMENT(Struct): pass +struct_GSP_MSG_QUEUE_ELEMENT._fields_ = [ + ('authTagBuffer', (NvU8 * 16)), + ('aadBuffer', (NvU8 * 16)), + ('checkSum', NvU32), + ('seqNum', NvU32), + ('elemCount', NvU32), + ('padding', NvU32), +] +GSP_MSG_QUEUE_ELEMENT = struct_GSP_MSG_QUEUE_ELEMENT +class union_rpc_message_rpc_union_field_v03_00(ctypes.Union): pass +union_rpc_message_rpc_union_field_v03_00._fields_ = [ + ('spare', NvU32), + ('cpuRmGfid', NvU32), +] +rpc_message_rpc_union_field_v03_00 = union_rpc_message_rpc_union_field_v03_00 +rpc_message_rpc_union_field_v = union_rpc_message_rpc_union_field_v03_00 +class struct_rpc_message_header_v03_00(Struct): pass +struct_rpc_message_header_v03_00._fields_ = [ + ('header_version', NvU32), + ('signature', NvU32), + ('length', NvU32), + ('function', NvU32), + ('rpc_result', NvU32), + ('rpc_result_private', NvU32), + ('sequence', NvU32), + ('u', rpc_message_rpc_union_field_v), +] +rpc_message_header_v03_00 = struct_rpc_message_header_v03_00 +rpc_message_header_v = struct_rpc_message_header_v03_00 +class struct_PACKED_REGISTRY_ENTRY(Struct): pass +struct_PACKED_REGISTRY_ENTRY._fields_ = [ + ('nameOffset', NvU32), + ('type', NvU8), + ('data', NvU32), + ('length', NvU32), +] +PACKED_REGISTRY_ENTRY = struct_PACKED_REGISTRY_ENTRY +class struct_PACKED_REGISTRY_TABLE(Struct): pass +struct_PACKED_REGISTRY_TABLE._fields_ = [ + ('size', NvU32), + ('numEntries', NvU32), +] +PACKED_REGISTRY_TABLE = struct_PACKED_REGISTRY_TABLE +DISPMUXSTATE = CEnum(ctypes.c_uint32) +dispMuxState_None = DISPMUXSTATE.define('dispMuxState_None', 0) +dispMuxState_IntegratedGPU = DISPMUXSTATE.define('dispMuxState_IntegratedGPU', 1) +dispMuxState_DiscreteGPU = DISPMUXSTATE.define('dispMuxState_DiscreteGPU', 2) + +class ACPI_DSM_CACHE(Struct): pass +ACPI_DSM_CACHE._fields_ = [ + ('suppFuncStatus', NvU32), + ('suppFuncs', (NvU8 * 8)), + ('suppFuncsLen', NvU32), + ('bArg3isInteger', NvBool), + ('callbackStatus', NvU32), + ('callback', NvU32), +] +class ACPI_DATA(Struct): pass +enum__ACPI_DSM_FUNCTION = CEnum(ctypes.c_uint32) +ACPI_DSM_FUNCTION_NBSI = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_NBSI', 0) +ACPI_DSM_FUNCTION_NVHG = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_NVHG', 1) +ACPI_DSM_FUNCTION_MXM = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_MXM', 2) +ACPI_DSM_FUNCTION_NBCI = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_NBCI', 3) +ACPI_DSM_FUNCTION_NVOP = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_NVOP', 4) +ACPI_DSM_FUNCTION_PCFG = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_PCFG', 5) +ACPI_DSM_FUNCTION_GPS_2X = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_GPS_2X', 6) +ACPI_DSM_FUNCTION_JT = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_JT', 7) +ACPI_DSM_FUNCTION_PEX = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_PEX', 8) +ACPI_DSM_FUNCTION_NVPCF_2X = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_NVPCF_2X', 9) +ACPI_DSM_FUNCTION_GPS = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_GPS', 10) +ACPI_DSM_FUNCTION_NVPCF = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_NVPCF', 11) +ACPI_DSM_FUNCTION_COUNT = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_COUNT', 12) +ACPI_DSM_FUNCTION_CURRENT = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_CURRENT', 13) +ACPI_DSM_FUNCTION_INVALID = enum__ACPI_DSM_FUNCTION.define('ACPI_DSM_FUNCTION_INVALID', 255) + +ACPI_DSM_FUNCTION = enum__ACPI_DSM_FUNCTION +ACPI_DATA._fields_ = [ + ('dsm', (ACPI_DSM_CACHE * 12)), + ('dispStatusHotplugFunc', ACPI_DSM_FUNCTION), + ('dispStatusConfigFunc', ACPI_DSM_FUNCTION), + ('perfPostPowerStateFunc', ACPI_DSM_FUNCTION), + ('stereo3dStateActiveFunc', ACPI_DSM_FUNCTION), + ('dsmPlatCapsCache', (NvU32 * 12)), + ('MDTLFeatureSupport', NvU32), + ('dsmCurrentFunc', (ACPI_DSM_FUNCTION * 8)), + ('dsmCurrentSubFunc', (NvU32 * 8)), + ('dsmCurrentFuncSupport', NvU32), +] +class struct_DOD_METHOD_DATA(Struct): pass +NV_STATUS = ctypes.c_uint32 +struct_DOD_METHOD_DATA._fields_ = [ + ('status', NV_STATUS), + ('acpiIdListLen', NvU32), + ('acpiIdList', (NvU32 * 16)), +] +DOD_METHOD_DATA = struct_DOD_METHOD_DATA +class struct_JT_METHOD_DATA(Struct): pass +struct_JT_METHOD_DATA._fields_ = [ + ('status', NV_STATUS), + ('jtCaps', NvU32), + ('jtRevId', NvU16), + ('bSBIOSCaps', NvBool), +] +JT_METHOD_DATA = struct_JT_METHOD_DATA +class struct_MUX_METHOD_DATA_ELEMENT(Struct): pass +struct_MUX_METHOD_DATA_ELEMENT._fields_ = [ + ('acpiId', NvU32), + ('mode', NvU32), + ('status', NV_STATUS), +] +MUX_METHOD_DATA_ELEMENT = struct_MUX_METHOD_DATA_ELEMENT +class struct_MUX_METHOD_DATA(Struct): pass +struct_MUX_METHOD_DATA._fields_ = [ + ('tableLen', NvU32), + ('acpiIdMuxModeTable', (MUX_METHOD_DATA_ELEMENT * 16)), + ('acpiIdMuxPartTable', (MUX_METHOD_DATA_ELEMENT * 16)), + ('acpiIdMuxStateTable', (MUX_METHOD_DATA_ELEMENT * 16)), +] +MUX_METHOD_DATA = struct_MUX_METHOD_DATA +class struct_CAPS_METHOD_DATA(Struct): pass +struct_CAPS_METHOD_DATA._fields_ = [ + ('status', NV_STATUS), + ('optimusCaps', NvU32), +] +CAPS_METHOD_DATA = struct_CAPS_METHOD_DATA +class struct_ACPI_METHOD_DATA(Struct): pass +struct_ACPI_METHOD_DATA._fields_ = [ + ('bValid', NvBool), + ('dodMethodData', DOD_METHOD_DATA), + ('jtMethodData', JT_METHOD_DATA), + ('muxMethodData', MUX_METHOD_DATA), + ('capsMethodData', CAPS_METHOD_DATA), +] +ACPI_METHOD_DATA = struct_ACPI_METHOD_DATA +RM_ENGINE_TYPE = CEnum(ctypes.c_uint32) +RM_ENGINE_TYPE_NULL = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NULL', 0) +RM_ENGINE_TYPE_GR0 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR0', 1) +RM_ENGINE_TYPE_GR1 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR1', 2) +RM_ENGINE_TYPE_GR2 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR2', 3) +RM_ENGINE_TYPE_GR3 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR3', 4) +RM_ENGINE_TYPE_GR4 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR4', 5) +RM_ENGINE_TYPE_GR5 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR5', 6) +RM_ENGINE_TYPE_GR6 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR6', 7) +RM_ENGINE_TYPE_GR7 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_GR7', 8) +RM_ENGINE_TYPE_COPY0 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY0', 9) +RM_ENGINE_TYPE_COPY1 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY1', 10) +RM_ENGINE_TYPE_COPY2 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY2', 11) +RM_ENGINE_TYPE_COPY3 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY3', 12) +RM_ENGINE_TYPE_COPY4 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY4', 13) +RM_ENGINE_TYPE_COPY5 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY5', 14) +RM_ENGINE_TYPE_COPY6 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY6', 15) +RM_ENGINE_TYPE_COPY7 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY7', 16) +RM_ENGINE_TYPE_COPY8 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY8', 17) +RM_ENGINE_TYPE_COPY9 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY9', 18) +RM_ENGINE_TYPE_COPY10 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY10', 19) +RM_ENGINE_TYPE_COPY11 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY11', 20) +RM_ENGINE_TYPE_COPY12 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY12', 21) +RM_ENGINE_TYPE_COPY13 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY13', 22) +RM_ENGINE_TYPE_COPY14 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY14', 23) +RM_ENGINE_TYPE_COPY15 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY15', 24) +RM_ENGINE_TYPE_COPY16 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY16', 25) +RM_ENGINE_TYPE_COPY17 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY17', 26) +RM_ENGINE_TYPE_COPY18 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY18', 27) +RM_ENGINE_TYPE_COPY19 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_COPY19', 28) +RM_ENGINE_TYPE_NVDEC0 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC0', 29) +RM_ENGINE_TYPE_NVDEC1 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC1', 30) +RM_ENGINE_TYPE_NVDEC2 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC2', 31) +RM_ENGINE_TYPE_NVDEC3 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC3', 32) +RM_ENGINE_TYPE_NVDEC4 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC4', 33) +RM_ENGINE_TYPE_NVDEC5 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC5', 34) +RM_ENGINE_TYPE_NVDEC6 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC6', 35) +RM_ENGINE_TYPE_NVDEC7 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVDEC7', 36) +RM_ENGINE_TYPE_NVENC0 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVENC0', 37) +RM_ENGINE_TYPE_NVENC1 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVENC1', 38) +RM_ENGINE_TYPE_NVENC2 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVENC2', 39) +RM_ENGINE_TYPE_NVENC3 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVENC3', 40) +RM_ENGINE_TYPE_VP = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_VP', 41) +RM_ENGINE_TYPE_ME = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_ME', 42) +RM_ENGINE_TYPE_PPP = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_PPP', 43) +RM_ENGINE_TYPE_MPEG = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_MPEG', 44) +RM_ENGINE_TYPE_SW = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_SW', 45) +RM_ENGINE_TYPE_TSEC = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_TSEC', 46) +RM_ENGINE_TYPE_VIC = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_VIC', 47) +RM_ENGINE_TYPE_MP = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_MP', 48) +RM_ENGINE_TYPE_SEC2 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_SEC2', 49) +RM_ENGINE_TYPE_HOST = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_HOST', 50) +RM_ENGINE_TYPE_DPU = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_DPU', 51) +RM_ENGINE_TYPE_PMU = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_PMU', 52) +RM_ENGINE_TYPE_FBFLCN = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_FBFLCN', 53) +RM_ENGINE_TYPE_NVJPEG0 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG0', 54) +RM_ENGINE_TYPE_NVJPEG1 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG1', 55) +RM_ENGINE_TYPE_NVJPEG2 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG2', 56) +RM_ENGINE_TYPE_NVJPEG3 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG3', 57) +RM_ENGINE_TYPE_NVJPEG4 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG4', 58) +RM_ENGINE_TYPE_NVJPEG5 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG5', 59) +RM_ENGINE_TYPE_NVJPEG6 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG6', 60) +RM_ENGINE_TYPE_NVJPEG7 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_NVJPEG7', 61) +RM_ENGINE_TYPE_OFA0 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_OFA0', 62) +RM_ENGINE_TYPE_OFA1 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_OFA1', 63) +RM_ENGINE_TYPE_RESERVED40 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED40', 64) +RM_ENGINE_TYPE_RESERVED41 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED41', 65) +RM_ENGINE_TYPE_RESERVED42 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED42', 66) +RM_ENGINE_TYPE_RESERVED43 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED43', 67) +RM_ENGINE_TYPE_RESERVED44 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED44', 68) +RM_ENGINE_TYPE_RESERVED45 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED45', 69) +RM_ENGINE_TYPE_RESERVED46 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED46', 70) +RM_ENGINE_TYPE_RESERVED47 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED47', 71) +RM_ENGINE_TYPE_RESERVED48 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED48', 72) +RM_ENGINE_TYPE_RESERVED49 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED49', 73) +RM_ENGINE_TYPE_RESERVED4a = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED4a', 74) +RM_ENGINE_TYPE_RESERVED4b = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED4b', 75) +RM_ENGINE_TYPE_RESERVED4c = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED4c', 76) +RM_ENGINE_TYPE_RESERVED4d = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED4d', 77) +RM_ENGINE_TYPE_RESERVED4e = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED4e', 78) +RM_ENGINE_TYPE_RESERVED4f = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED4f', 79) +RM_ENGINE_TYPE_RESERVED50 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED50', 80) +RM_ENGINE_TYPE_RESERVED51 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED51', 81) +RM_ENGINE_TYPE_RESERVED52 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED52', 82) +RM_ENGINE_TYPE_RESERVED53 = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_RESERVED53', 83) +RM_ENGINE_TYPE_LAST = RM_ENGINE_TYPE.define('RM_ENGINE_TYPE_LAST', 84) + +class BUSINFO(Struct): pass +BUSINFO._fields_ = [ + ('deviceID', NvU16), + ('vendorID', NvU16), + ('subdeviceID', NvU16), + ('subvendorID', NvU16), + ('revisionID', NvU8), +] +class struct_GSP_VF_INFO(Struct): pass +struct_GSP_VF_INFO._fields_ = [ + ('totalVFs', NvU32), + ('firstVFOffset', NvU32), + ('FirstVFBar0Address', NvU64), + ('FirstVFBar1Address', NvU64), + ('FirstVFBar2Address', NvU64), + ('b64bitBar0', NvBool), + ('b64bitBar1', NvBool), + ('b64bitBar2', NvBool), +] +GSP_VF_INFO = struct_GSP_VF_INFO +class GSP_PCIE_CONFIG_REG(Struct): pass +GSP_PCIE_CONFIG_REG._fields_ = [ + ('linkCap', NvU32), +] +class EcidManufacturingInfo(Struct): pass +EcidManufacturingInfo._fields_ = [ + ('ecidLow', NvU32), + ('ecidHigh', NvU32), + ('ecidExtended', NvU32), +] +class FW_WPR_LAYOUT_OFFSET(Struct): pass +FW_WPR_LAYOUT_OFFSET._fields_ = [ + ('nonWprHeapOffset', NvU64), + ('frtsOffset', NvU64), +] +class struct_GspStaticConfigInfo_t(Struct): pass +class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(Struct): pass +NV2080_CTRL_GPU_GET_GID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS +struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._fields_ = [ + ('index', NvU32), + ('flags', NvU32), + ('length', NvU32), + ('data', (NvU8 * 256)), +] +class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(Struct): pass +NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS +struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._fields_ = [ + ('BoardID', NvU32), + ('chipSKU', (ctypes.c_char * 9)), + ('chipSKUMod', (ctypes.c_char * 5)), + ('skuConfigVersion', NvU32), + ('project', (ctypes.c_char * 5)), + ('projectSKU', (ctypes.c_char * 5)), + ('CDP', (ctypes.c_char * 6)), + ('projectSKUMod', (ctypes.c_char * 2)), + ('businessCycle', NvU32), +] +class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(Struct): pass +NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS +class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(Struct): pass +NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO +NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = (ctypes.c_ubyte * 17) +struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._fields_ = [ + ('base', NvU64), + ('limit', NvU64), + ('reserved', NvU64), + ('performance', NvU32), + ('supportCompressed', NvBool), + ('supportISO', NvBool), + ('bProtected', NvBool), + ('blackList', NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG), +] +struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._fields_ = [ + ('numFBRegions', NvU32), + ('fbRegion', (NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO * 16)), +] +class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(Struct): pass +NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS +struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._fields_ = [ + ('totalVFs', NvU32), + ('firstVfOffset', NvU32), + ('vfFeatureMask', NvU32), + ('FirstVFBar0Address', NvU64), + ('FirstVFBar1Address', NvU64), + ('FirstVFBar2Address', NvU64), + ('bar0Size', NvU64), + ('bar1Size', NvU64), + ('bar2Size', NvU64), + ('b64bitBar0', NvBool), + ('b64bitBar1', NvBool), + ('b64bitBar2', NvBool), + ('bSriovEnabled', NvBool), + ('bSriovHeavyEnabled', NvBool), + ('bEmulateVFBar0TlbInvalidationRegister', NvBool), + ('bClientRmAllocatedCtxBuffer', NvBool), + ('bNonPowerOf2ChannelCountSupported', NvBool), + ('bVfResizableBAR1Supported', NvBool), +] +struct_GspStaticConfigInfo_t._fields_ = [ + ('grCapsBits', (NvU8 * 23)), + ('gidInfo', NV2080_CTRL_GPU_GET_GID_INFO_PARAMS), + ('SKUInfo', NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), + ('fbRegionInfoParams', NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS), + ('sriovCaps', NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS), + ('sriovMaxGfid', NvU32), + ('engineCaps', (NvU32 * 3)), + ('poisonFuseEnabled', NvBool), + ('fb_length', NvU64), + ('fbio_mask', NvU64), + ('fb_bus_width', NvU32), + ('fb_ram_type', NvU32), + ('fbp_mask', NvU64), + ('l2_cache_size', NvU32), + ('gpuNameString', (NvU8 * 64)), + ('gpuShortNameString', (NvU8 * 64)), + ('gpuNameString_Unicode', (NvU16 * 64)), + ('bGpuInternalSku', NvBool), + ('bIsQuadroGeneric', NvBool), + ('bIsQuadroAd', NvBool), + ('bIsNvidiaNvs', NvBool), + ('bIsVgx', NvBool), + ('bGeforceSmb', NvBool), + ('bIsTitan', NvBool), + ('bIsTesla', NvBool), + ('bIsMobile', NvBool), + ('bIsGc6Rtd3Allowed', NvBool), + ('bIsGc8Rtd3Allowed', NvBool), + ('bIsGcOffRtd3Allowed', NvBool), + ('bIsGcoffLegacyAllowed', NvBool), + ('bIsMigSupported', NvBool), + ('RTD3GC6TotalBoardPower', NvU16), + ('RTD3GC6PerstDelay', NvU16), + ('bar1PdeBase', NvU64), + ('bar2PdeBase', NvU64), + ('bVbiosValid', NvBool), + ('vbiosSubVendor', NvU32), + ('vbiosSubDevice', NvU32), + ('bPageRetirementSupported', NvBool), + ('bSplitVasBetweenServerClientRm', NvBool), + ('bClRootportNeedsNosnoopWAR', NvBool), + ('displaylessMaxHeads', VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS), + ('displaylessMaxResolution', VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS), + ('displaylessMaxPixels', NvU64), + ('hInternalClient', NvHandle), + ('hInternalDevice', NvHandle), + ('hInternalSubdevice', NvHandle), + ('bSelfHostedMode', NvBool), + ('bAtsSupported', NvBool), + ('bIsGpuUefi', NvBool), + ('bIsEfiInit', NvBool), + ('ecidInfo', (EcidManufacturingInfo * 2)), + ('fwWprLayoutOffset', FW_WPR_LAYOUT_OFFSET), +] +GspStaticConfigInfo = struct_GspStaticConfigInfo_t +class struct_GspSystemInfo(Struct): pass +struct_GspSystemInfo._fields_ = [ + ('gpuPhysAddr', NvU64), + ('gpuPhysFbAddr', NvU64), + ('gpuPhysInstAddr', NvU64), + ('gpuPhysIoAddr', NvU64), + ('nvDomainBusDeviceFunc', NvU64), + ('simAccessBufPhysAddr', NvU64), + ('notifyOpSharedSurfacePhysAddr', NvU64), + ('pcieAtomicsOpMask', NvU64), + ('consoleMemSize', NvU64), + ('maxUserVa', NvU64), + ('pciConfigMirrorBase', NvU32), + ('pciConfigMirrorSize', NvU32), + ('PCIDeviceID', NvU32), + ('PCISubDeviceID', NvU32), + ('PCIRevisionID', NvU32), + ('pcieAtomicsCplDeviceCapMask', NvU32), + ('oorArch', NvU8), + ('clPdbProperties', NvU64), + ('Chipset', NvU32), + ('bGpuBehindBridge', NvBool), + ('bFlrSupported', NvBool), + ('b64bBar0Supported', NvBool), + ('bMnocAvailable', NvBool), + ('chipsetL1ssEnable', NvU32), + ('bUpstreamL0sUnsupported', NvBool), + ('bUpstreamL1Unsupported', NvBool), + ('bUpstreamL1PorSupported', NvBool), + ('bUpstreamL1PorMobileOnly', NvBool), + ('bSystemHasMux', NvBool), + ('upstreamAddressValid', NvU8), + ('FHBBusInfo', BUSINFO), + ('chipsetIDInfo', BUSINFO), + ('acpiMethodData', ACPI_METHOD_DATA), + ('hypervisorType', NvU32), + ('bIsPassthru', NvBool), + ('sysTimerOffsetNs', NvU64), + ('gspVFInfo', GSP_VF_INFO), + ('bIsPrimary', NvBool), + ('isGridBuild', NvBool), + ('pcieConfigReg', GSP_PCIE_CONFIG_REG), + ('gridBuildCsp', NvU32), + ('bPreserveVideoMemoryAllocations', NvBool), + ('bTdrEventSupported', NvBool), + ('bFeatureStretchVblankCapable', NvBool), + ('bEnableDynamicGranularityPageArrays', NvBool), + ('bClockBoostSupported', NvBool), + ('bRouteDispIntrsToCPU', NvBool), + ('hostPageSize', NvU64), +] +GspSystemInfo = struct_GspSystemInfo +class FALCON_APPLICATION_INTERFACE_HEADER_V1(Struct): pass +FALCON_APPLICATION_INTERFACE_HEADER_V1._packed_ = True +FALCON_APPLICATION_INTERFACE_HEADER_V1._fields_ = [ + ('version', NvU8), + ('headerSize', NvU8), + ('entrySize', NvU8), + ('entryCount', NvU8), +] +class FALCON_APPLICATION_INTERFACE_ENTRY_V1(Struct): pass +FALCON_APPLICATION_INTERFACE_ENTRY_V1._packed_ = True +FALCON_APPLICATION_INTERFACE_ENTRY_V1._fields_ = [ + ('id', NvU32), + ('dmemOffset', NvU32), +] +class FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3(Struct): pass +FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3._packed_ = True +FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3._fields_ = [ + ('signature', NvU32), + ('version', NvU16), + ('size', NvU16), + ('cmd_in_buffer_offset', NvU32), + ('cmd_in_buffer_size', NvU32), + ('cmd_out_buffer_offset', NvU32), + ('cmd_out_buffer_size', NvU32), + ('nvf_img_data_buffer_offset', NvU32), + ('nvf_img_data_buffer_size', NvU32), + ('printfBufferHdr', NvU32), + ('ucode_build_time_stamp', NvU32), + ('ucode_signature', NvU32), + ('init_cmd', NvU32), + ('ucode_feature', NvU32), + ('ucode_cmd_mask0', NvU32), + ('ucode_cmd_mask1', NvU32), + ('multiTgtTbl', NvU32), +] +class struct_BIT_HEADER_V1_00(Struct): pass +struct_BIT_HEADER_V1_00._packed_ = True +struct_BIT_HEADER_V1_00._fields_ = [ + ('Id', ctypes.c_uint16), + ('Signature', ctypes.c_uint32), + ('BCD_Version', ctypes.c_uint16), + ('HeaderSize', ctypes.c_ubyte), + ('TokenSize', ctypes.c_ubyte), + ('TokenEntries', ctypes.c_ubyte), + ('HeaderChksum', ctypes.c_ubyte), +] +BIT_HEADER_V1_00 = struct_BIT_HEADER_V1_00 +class struct_BIT_TOKEN_V1_00(Struct): pass +struct_BIT_TOKEN_V1_00._packed_ = True +struct_BIT_TOKEN_V1_00._fields_ = [ + ('TokenId', ctypes.c_ubyte), + ('DataVersion', ctypes.c_ubyte), + ('DataSize', ctypes.c_uint16), + ('DataPtr', ctypes.c_uint32), +] +BIT_TOKEN_V1_00 = struct_BIT_TOKEN_V1_00 +class BIT_DATA_BIOSDATA_BINVER(Struct): pass +BIT_DATA_BIOSDATA_BINVER._packed_ = True +BIT_DATA_BIOSDATA_BINVER._fields_ = [ + ('Version', ctypes.c_uint32), + ('OemVersion', ctypes.c_ubyte), +] +class BIT_DATA_FALCON_DATA_V2(Struct): pass +BIT_DATA_FALCON_DATA_V2._packed_ = True +BIT_DATA_FALCON_DATA_V2._fields_ = [ + ('FalconUcodeTablePtr', ctypes.c_uint32), +] +class FALCON_UCODE_TABLE_HDR_V1(Struct): pass +FALCON_UCODE_TABLE_HDR_V1._packed_ = True +FALCON_UCODE_TABLE_HDR_V1._fields_ = [ + ('Version', ctypes.c_ubyte), + ('HeaderSize', ctypes.c_ubyte), + ('EntrySize', ctypes.c_ubyte), + ('EntryCount', ctypes.c_ubyte), + ('DescVersion', ctypes.c_ubyte), + ('DescSize', ctypes.c_ubyte), +] +class FALCON_UCODE_TABLE_ENTRY_V1(Struct): pass +FALCON_UCODE_TABLE_ENTRY_V1._packed_ = True +FALCON_UCODE_TABLE_ENTRY_V1._fields_ = [ + ('ApplicationID', ctypes.c_ubyte), + ('TargetID', ctypes.c_ubyte), + ('DescPtr', ctypes.c_uint32), +] +class FALCON_UCODE_DESC_HEADER(Struct): pass +FALCON_UCODE_DESC_HEADER._packed_ = True +FALCON_UCODE_DESC_HEADER._fields_ = [ + ('vDesc', ctypes.c_uint32), +] +class FALCON_UCODE_DESC_V3(Struct): pass +FALCON_UCODE_DESC_V3._fields_ = [ + ('Hdr', FALCON_UCODE_DESC_HEADER), + ('StoredSize', ctypes.c_uint32), + ('PKCDataOffset', ctypes.c_uint32), + ('InterfaceOffset', ctypes.c_uint32), + ('IMEMPhysBase', ctypes.c_uint32), + ('IMEMLoadSize', ctypes.c_uint32), + ('IMEMVirtBase', ctypes.c_uint32), + ('DMEMPhysBase', ctypes.c_uint32), + ('DMEMLoadSize', ctypes.c_uint32), + ('EngineIdMask', ctypes.c_uint16), + ('UcodeId', ctypes.c_ubyte), + ('SignatureCount', ctypes.c_ubyte), + ('SignatureVersions', ctypes.c_uint16), + ('Reserved', ctypes.c_uint16), +] +class FWSECLIC_READ_VBIOS_DESC(Struct): pass +FWSECLIC_READ_VBIOS_DESC._packed_ = True +FWSECLIC_READ_VBIOS_DESC._fields_ = [ + ('version', NvU32), + ('size', NvU32), + ('gfwImageOffset', NvU64), + ('gfwImageSize', NvU32), + ('flags', NvU32), +] +class FWSECLIC_FRTS_REGION_DESC(Struct): pass +FWSECLIC_FRTS_REGION_DESC._packed_ = True +FWSECLIC_FRTS_REGION_DESC._fields_ = [ + ('version', NvU32), + ('size', NvU32), + ('frtsRegionOffset4K', NvU32), + ('frtsRegionSize', NvU32), + ('frtsRegionMediaType', NvU32), +] +class FWSECLIC_FRTS_CMD(Struct): pass +FWSECLIC_FRTS_CMD._packed_ = True +FWSECLIC_FRTS_CMD._fields_ = [ + ('readVbiosDesc', FWSECLIC_READ_VBIOS_DESC), + ('frtsRegionDesc', FWSECLIC_FRTS_REGION_DESC), +] +class struct__PCI_EXP_ROM_STANDARD(Struct): pass +struct__PCI_EXP_ROM_STANDARD._packed_ = True +struct__PCI_EXP_ROM_STANDARD._fields_ = [ + ('sig', NvU16), + ('reserved', (NvU8 * 22)), + ('pciDataStrucPtr', NvU16), + ('sizeOfBlock', NvU32), +] +PCI_EXP_ROM_STANDARD = struct__PCI_EXP_ROM_STANDARD +PPCI_EXP_ROM_STANDARD = ctypes.POINTER(struct__PCI_EXP_ROM_STANDARD) +class struct__PCI_EXP_ROM_NBSI(Struct): pass +struct__PCI_EXP_ROM_NBSI._packed_ = True +struct__PCI_EXP_ROM_NBSI._fields_ = [ + ('sig', NvU16), + ('reserved', (NvU8 * 20)), + ('nbsiDataOffset', NvU16), + ('pciDataStrucPtr', NvU16), + ('sizeOfBlock', NvU32), +] +PCI_EXP_ROM_NBSI = struct__PCI_EXP_ROM_NBSI +PPCI_EXP_ROM_NBSI = ctypes.POINTER(struct__PCI_EXP_ROM_NBSI) +class union__PCI_EXP_ROM(ctypes.Union): pass +union__PCI_EXP_ROM._fields_ = [ + ('standard', PCI_EXP_ROM_STANDARD), + ('nbsi', PCI_EXP_ROM_NBSI), +] +PCI_EXP_ROM = union__PCI_EXP_ROM +PPCI_EXP_ROM = ctypes.POINTER(union__PCI_EXP_ROM) +class struct__PCI_DATA_STRUCT(Struct): pass +struct__PCI_DATA_STRUCT._packed_ = True +struct__PCI_DATA_STRUCT._fields_ = [ + ('sig', NvU32), + ('vendorID', NvU16), + ('deviceID', NvU16), + ('deviceListPtr', NvU16), + ('pciDataStructLen', NvU16), + ('pciDataStructRev', NvU8), + ('classCode', (NvU8 * 3)), + ('imageLen', NvU16), + ('vendorRomRev', NvU16), + ('codeType', NvU8), + ('lastImage', NvU8), + ('maxRunTimeImageLen', NvU16), +] +PCI_DATA_STRUCT = struct__PCI_DATA_STRUCT +PPCI_DATA_STRUCT = ctypes.POINTER(struct__PCI_DATA_STRUCT) +class struct__NV_PCI_DATA_EXT_STRUCT(Struct): pass +struct__NV_PCI_DATA_EXT_STRUCT._packed_ = True +struct__NV_PCI_DATA_EXT_STRUCT._fields_ = [ + ('signature', NvU32), + ('nvPciDataExtRev', NvU16), + ('nvPciDataExtLen', NvU16), + ('subimageLen', NvU16), + ('privLastImage', NvU8), + ('flags', NvU8), +] +NV_PCI_DATA_EXT_STRUCT = struct__NV_PCI_DATA_EXT_STRUCT +PNV_PCI_DATA_EXT_STRUCT = ctypes.POINTER(struct__NV_PCI_DATA_EXT_STRUCT) +GSP_FW_WPR_META_VERIFIED = 0xa0a0a0a0a0a0a0a0 +GSP_FW_WPR_META_REVISION = 1 +GSP_FW_WPR_META_MAGIC = 0xdc3aae21371a60b3 +GSP_FW_WPR_HEAP_FREE_REGION_COUNT = 128 +GSP_FW_HEAP_FREE_LIST_MAGIC = 0x4845415046524545 +GSP_FW_SR_META_MAGIC = 0x8a3bb9e6c6c39d93 +GSP_FW_SR_META_REVISION = 2 +GSP_FW_SR_META_INTERNAL_SIZE = 128 +NVDM_TYPE_HULK = 0x11 +NVDM_TYPE_FIRMWARE_UPDATE = 0x12 +NVDM_TYPE_PRC = 0x13 +NVDM_TYPE_COT = 0x14 +NVDM_TYPE_FSP_RESPONSE = 0x15 +NVDM_TYPE_CAPS_QUERY = 0x16 +NVDM_TYPE_INFOROM = 0x17 +NVDM_TYPE_SMBPBI = 0x18 +NVDM_TYPE_ROMREAD = 0x1A +NVDM_TYPE_UEFI_RM = 0x1C +NVDM_TYPE_UEFI_XTL_DEBUG_INTR = 0x1D +NVDM_TYPE_TNVL = 0x1F +NVDM_TYPE_CLOCK_BOOST = 0x20 +NVDM_TYPE_FSP_GSP_COMM = 0x21 +MAX_GPC_COUNT = 32 +VGPU_MAX_REGOPS_PER_RPC = 100 +VGPU_RESERVED_HANDLE_BASE = 0xCAF3F000 +VGPU_RESERVED_HANDLE_RANGE = 0x1000 +VGPU_CALC_PARAM_OFFSET = lambda prev_offset,prev_params: (prev_offset + NV_ALIGN_UP(sizeof(prev_params), sizeof(NvU32))) +NV_VGPU_MSG_HEADER_VERSION_MAJOR_TOT = 0x00000003 +NV_VGPU_MSG_HEADER_VERSION_MINOR_TOT = 0x00000000 +NV_VGPU_MSG_SIGNATURE_VALID = 0x43505256 +NV_VGPU_MSG_RESULT_VMIOP_INVAL = 0xFF000001 +NV_VGPU_MSG_RESULT_VMIOP_RESOURCE = 0xFF000002 +NV_VGPU_MSG_RESULT_VMIOP_RANGE = 0xFF000003 +NV_VGPU_MSG_RESULT_VMIOP_READ_ONLY = 0xFF000004 +NV_VGPU_MSG_RESULT_VMIOP_NOT_FOUND = 0xFF000005 +NV_VGPU_MSG_RESULT_VMIOP_NO_ADDRESS_SPACE = 0xFF000006 +NV_VGPU_MSG_RESULT_VMIOP_TIMEOUT = 0xFF000007 +NV_VGPU_MSG_RESULT_VMIOP_NOT_ALLOWED_IN_CALLBACK = 0xFF000008 +NV_VGPU_MSG_RESULT_VMIOP_ECC_MISMATCH = 0xFF000009 +NV_VGPU_MSG_RESULT_VMIOP_NOT_SUPPORTED = 0xFF00000a +NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION = 0xFF100001 +NV_VGPU_MSG_RESULT_RPC_INVALID_MESSAGE_FORMAT = 0xFF100002 +NV_VGPU_MSG_RESULT_RPC_HANDLE_NOT_FOUND = 0xFF100003 +NV_VGPU_MSG_RESULT_RPC_HANDLE_EXISTS = 0xFF100004 +NV_VGPU_MSG_RESULT_RPC_UNKNOWN_RM_ERROR = 0xFF100005 +NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR = 0xFF100006 +NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE = 0xFF100007 +NV_VGPU_MSG_RESULT_RPC_CUDA_PROFILING_DISABLED = 0xFF100008 +NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED = 0xFF100009 +NV_VGPU_MSG_RESULT_RPC_PENDING = 0xFFFFFFFF +NV_VGPU_MSG_UNION_INIT = 0x00000000 +NV_VGPU_PTEDESC_INIT = 0x00000000 +NV_VGPU_PTEDESC__PROD = 0x00000000 +NV_VGPU_PTEDESC_IDR_NONE = 0x00000000 +NV_VGPU_PTEDESC_IDR_SINGLE = 0x00000001 +NV_VGPU_PTEDESC_IDR_DOUBLE = 0x00000002 +NV_VGPU_PTEDESC_IDR_TRIPLE = 0x00000003 +NV_VGPU_PTE_PAGE_SIZE = 0x1000 +NV_VGPU_PTE_SIZE = 4 +NV_VGPU_PTE_INDEX_SHIFT = 10 +NV_VGPU_PTE_INDEX_MASK = 0x3FF +NV_VGPU_PTE_64_PAGE_SIZE = 0x1000 +NV_VGPU_PTE_64_SIZE = 8 +NV_VGPU_PTE_64_INDEX_SHIFT = 9 +NV_VGPU_PTE_64_INDEX_MASK = 0x1FF +NV_VGPU_LOG_LEVEL_FATAL = 0x00000000 +NV_VGPU_LOG_LEVEL_ERROR = 0x00000001 +NV_VGPU_LOG_LEVEL_NOTICE = 0x00000002 +NV_VGPU_LOG_LEVEL_STATUS = 0x00000003 +NV_VGPU_LOG_LEVEL_DEBUG = 0x00000004 +VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC = 512 +GR_MAX_RPC_CTX_BUFFER_COUNT = 32 +VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 = 80 +LIBOS_MEMORY_REGION_INIT_ARGUMENTS_MAX = 4096 +LIBOS_MEMORY_REGION_RADIX_PAGE_SIZE = 4096 +LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2 = 12 +MSGQ_VERSION = 0 +MAX_DSM_SUPPORTED_FUNCS_RTN_LEN = 8 +NV_ACPI_GENERIC_FUNC_COUNT = 8 +REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN = 0 +REGISTRY_TABLE_ENTRY_TYPE_DWORD = 1 +REGISTRY_TABLE_ENTRY_TYPE_BINARY = 2 +REGISTRY_TABLE_ENTRY_TYPE_STRING = 3 +MAX_GROUP_COUNT = 2 +RM_ENGINE_TYPE_GRAPHICS = RM_ENGINE_TYPE_GR0 +RM_ENGINE_TYPE_BSP = RM_ENGINE_TYPE_NVDEC0 +RM_ENGINE_TYPE_MSENC = RM_ENGINE_TYPE_NVENC0 +RM_ENGINE_TYPE_CIPHER = RM_ENGINE_TYPE_TSEC +RM_ENGINE_TYPE_NVJPG = RM_ENGINE_TYPE_NVJPEG0 +RM_ENGINE_TYPE_COPY_SIZE = 20 +RM_ENGINE_TYPE_NVENC_SIZE = 4 +RM_ENGINE_TYPE_NVJPEG_SIZE = 8 +RM_ENGINE_TYPE_NVDEC_SIZE = 8 +RM_ENGINE_TYPE_OFA_SIZE = 2 +RM_ENGINE_TYPE_GR_SIZE = 8 +NVGPU_ENGINE_CAPS_MASK_BITS = 32 +NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX = ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1) +NVGPU_GET_ENGINE_CAPS_MASK = lambda caps,id: (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] & NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS)) +FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER = (0x4) +FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS = (0x15) +FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB = (0x19) +BIT_HEADER_ID = 0xB8FF +BIT_HEADER_SIGNATURE = 0x00544942 +BIT_HEADER_SIZE_OFFSET = 8 +BIT_HEADER_V1_00_FMT = "1w1d1w4b" +BIT_TOKEN_V1_00_SIZE_6 = 6 +BIT_TOKEN_V1_00_SIZE_8 = 8 +BIT_TOKEN_V1_00_FMT_SIZE_6 = "2b2w" +BIT_TOKEN_V1_00_FMT_SIZE_8 = "2b1w1d" +BIT_TOKEN_BIOSDATA = 0x42 +BIT_DATA_BIOSDATA_VERSION_1 = 0x1 +BIT_DATA_BIOSDATA_VERSION_2 = 0x2 +BIT_DATA_BIOSDATA_BINVER_FMT = "1d1b" +BIT_DATA_BIOSDATA_BINVER_SIZE_5 = 5 +BIT_TOKEN_FALCON_DATA = 0x70 +BIT_DATA_FALCON_DATA_V2_4_FMT = "1d" +BIT_DATA_FALCON_DATA_V2_SIZE_4 = 4 +FALCON_UCODE_TABLE_HDR_V1_VERSION = 1 +FALCON_UCODE_TABLE_HDR_V1_SIZE_6 = 6 +FALCON_UCODE_TABLE_HDR_V1_6_FMT = "6b" +FALCON_UCODE_TABLE_ENTRY_V1_VERSION = 1 +FALCON_UCODE_TABLE_ENTRY_V1_SIZE_6 = 6 +FALCON_UCODE_TABLE_ENTRY_V1_6_FMT = "2b1d" +FALCON_UCODE_ENTRY_APPID_FIRMWARE_SEC_LIC = 0x05 +FALCON_UCODE_ENTRY_APPID_FWSEC_DBG = 0x45 +FALCON_UCODE_ENTRY_APPID_FWSEC_PROD = 0x85 +NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_UNAVAILABLE = 0x00 +NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_AVAILABLE = 0x01 +NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V1 = 0x01 +NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V2 = 0x02 +NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V3 = 0x03 +NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V4 = 0x04 +FALCON_UCODE_DESC_HEADER_FORMAT = "1d" +FALCON_UCODE_DESC_V3_SIZE_44 = 44 +FALCON_UCODE_DESC_V3_44_FMT = "9d1w2b2w" +BCRT30_RSA3K_SIG_SIZE = 384 +FWSECLIC_READ_VBIOS_STRUCT_FLAGS = (2) +FWSECLIC_FRTS_REGION_MEDIA_FB = (2) +FWSECLIC_FRTS_REGION_SIZE_1MB_IN_4K = (0x100) +NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE = 0x00 +NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT = 0xE0 +PCI_EXP_ROM_SIGNATURE = 0xaa55 +PCI_EXP_ROM_SIGNATURE_NV = 0x4e56 +PCI_EXP_ROM_SIGNATURE_NV2 = 0xbb77 +IS_VALID_PCI_ROM_SIG = lambda sig: ((sig == PCI_EXP_ROM_SIGNATURE) or (sig == PCI_EXP_ROM_SIGNATURE_NV) or (sig == PCI_EXP_ROM_SIGNATURE_NV2)) +OFFSETOF_PCI_EXP_ROM_SIG = 0x0 +OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET = 0x16 +OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR = 0x18 +PCI_DATA_STRUCT_SIGNATURE = 0x52494350 +PCI_DATA_STRUCT_SIGNATURE_NV = 0x5344504E +PCI_DATA_STRUCT_SIGNATURE_NV2 = 0x53494752 +IS_VALID_PCI_DATA_SIG = lambda sig: ((sig == PCI_DATA_STRUCT_SIGNATURE) or (sig == PCI_DATA_STRUCT_SIGNATURE_NV) or (sig == PCI_DATA_STRUCT_SIGNATURE_NV2)) +PCI_ROM_IMAGE_BLOCK_SIZE = 512 +OFFSETOF_PCI_DATA_STRUCT_SIG = 0x0 +OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID = 0x4 +OFFSETOF_PCI_DATA_STRUCT_LEN = 0xa +OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE = 0xd +OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE = 0x14 +OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN = 0x10 +OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE = 0x15 +NV_PCI_DATA_EXT_SIG = 0x4544504E +NV_PCI_DATA_EXT_REV_10 = 0x100 +NV_PCI_DATA_EXT_REV_11 = 0x101 +OFFSETOF_PCI_DATA_EXT_STRUCT_SIG = 0x0 +OFFSETOF_PCI_DATA_EXT_STRUCT_LEN = 0x6 +OFFSETOF_PCI_DATA_EXT_STRUCT_REV = 0x4 +OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN = 0x8 +OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE = 0xa +OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS = 0xb +PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED = 0x04 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/nv/nv.py b/tinygrad/runtime/autogen/nv/nv.py deleted file mode 100644 index 0516ebd5ba..0000000000 --- a/tinygrad/runtime/autogen/nv/nv.py +++ /dev/null @@ -1,8740 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-DRPC_MESSAGE_STRUCTURES', '-DRPC_STRUCTURES', '-include', '/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc/nvtypes.h', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/generated', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/interface/', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/inc/kernel', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/inc/libraries', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/arch/nvalloc/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/kernel-open/nvidia-uvm', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/kernel-open/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/arch/nvalloc/unix/include', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc/ctrl'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -KERN_FSP_COT_PAYLOAD_H = True # macro -class struct_c__SA_MCTP_HEADER(Structure): - pass - -struct_c__SA_MCTP_HEADER._pack_ = 1 # source:False -struct_c__SA_MCTP_HEADER._fields_ = [ - ('constBlob', ctypes.c_uint32), - ('msgType', ctypes.c_ubyte), - ('vendorId', ctypes.c_uint16), -] - -MCTP_HEADER = struct_c__SA_MCTP_HEADER -class struct_c__SA_NVDM_PAYLOAD_COT(Structure): - pass - -struct_c__SA_NVDM_PAYLOAD_COT._pack_ = 1 # source:False -struct_c__SA_NVDM_PAYLOAD_COT._fields_ = [ - ('version', ctypes.c_uint16), - ('size', ctypes.c_uint16), - ('gspFmcSysmemOffset', ctypes.c_uint64), - ('frtsSysmemOffset', ctypes.c_uint64), - ('frtsSysmemSize', ctypes.c_uint32), - ('frtsVidmemOffset', ctypes.c_uint64), - ('frtsVidmemSize', ctypes.c_uint32), - ('hash384', ctypes.c_uint32 * 12), - ('publicKey', ctypes.c_uint32 * 96), - ('signature', ctypes.c_uint32 * 96), - ('gspBootArgsSysmemOffset', ctypes.c_uint64), -] - -NVDM_PAYLOAD_COT = struct_c__SA_NVDM_PAYLOAD_COT -GSPIFPUB_H = True # macro - -# values for enumeration 'c__EA_GSP_DMA_TARGET' -c__EA_GSP_DMA_TARGET__enumvalues = { - 0: 'GSP_DMA_TARGET_LOCAL_FB', - 1: 'GSP_DMA_TARGET_COHERENT_SYSTEM', - 2: 'GSP_DMA_TARGET_NONCOHERENT_SYSTEM', - 3: 'GSP_DMA_TARGET_COUNT', -} -GSP_DMA_TARGET_LOCAL_FB = 0 -GSP_DMA_TARGET_COHERENT_SYSTEM = 1 -GSP_DMA_TARGET_NONCOHERENT_SYSTEM = 2 -GSP_DMA_TARGET_COUNT = 3 -c__EA_GSP_DMA_TARGET = ctypes.c_uint32 # enum -GSP_DMA_TARGET = c__EA_GSP_DMA_TARGET -GSP_DMA_TARGET__enumvalues = c__EA_GSP_DMA_TARGET__enumvalues -class struct_GSP_FMC_INIT_PARAMS(Structure): - pass - -struct_GSP_FMC_INIT_PARAMS._pack_ = 1 # source:False -struct_GSP_FMC_INIT_PARAMS._fields_ = [ - ('regkeys', ctypes.c_uint32), -] - -GSP_FMC_INIT_PARAMS = struct_GSP_FMC_INIT_PARAMS -class struct_GSP_ACR_BOOT_GSP_RM_PARAMS(Structure): - pass - -struct_GSP_ACR_BOOT_GSP_RM_PARAMS._pack_ = 1 # source:False -struct_GSP_ACR_BOOT_GSP_RM_PARAMS._fields_ = [ - ('target', GSP_DMA_TARGET), - ('gspRmDescSize', ctypes.c_uint32), - ('gspRmDescOffset', ctypes.c_uint64), - ('wprCarveoutOffset', ctypes.c_uint64), - ('wprCarveoutSize', ctypes.c_uint32), - ('bIsGspRmBoot', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -GSP_ACR_BOOT_GSP_RM_PARAMS = struct_GSP_ACR_BOOT_GSP_RM_PARAMS -class struct_GSP_RM_PARAMS(Structure): - pass - -struct_GSP_RM_PARAMS._pack_ = 1 # source:False -struct_GSP_RM_PARAMS._fields_ = [ - ('target', GSP_DMA_TARGET), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bootArgsOffset', ctypes.c_uint64), -] - -GSP_RM_PARAMS = struct_GSP_RM_PARAMS -class struct_GSP_SPDM_PARAMS(Structure): - pass - -struct_GSP_SPDM_PARAMS._pack_ = 1 # source:False -struct_GSP_SPDM_PARAMS._fields_ = [ - ('target', GSP_DMA_TARGET), - ('PADDING_0', ctypes.c_ubyte * 4), - ('payloadBufferOffset', ctypes.c_uint64), - ('payloadBufferSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -GSP_SPDM_PARAMS = struct_GSP_SPDM_PARAMS -class struct_GSP_FMC_BOOT_PARAMS(Structure): - pass - -struct_GSP_FMC_BOOT_PARAMS._pack_ = 1 # source:False -struct_GSP_FMC_BOOT_PARAMS._fields_ = [ - ('initParams', GSP_FMC_INIT_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bootGspRmParams', GSP_ACR_BOOT_GSP_RM_PARAMS), - ('gspRmParams', GSP_RM_PARAMS), - ('gspSpdmParams', GSP_SPDM_PARAMS), -] - -GSP_FMC_BOOT_PARAMS = struct_GSP_FMC_BOOT_PARAMS -GSP_FW_WPR_META_H_ = True # macro -GSP_FW_WPR_META_VERIFIED = 0xa0a0a0a0a0a0a0a0 # macro -GSP_FW_WPR_META_REVISION = 1 # macro -GSP_FW_WPR_META_MAGIC = 0xdc3aae21371a60b3 # macro -GSP_FW_WPR_HEAP_FREE_REGION_COUNT = 128 # macro -GSP_FW_HEAP_FREE_LIST_MAGIC = 0x4845415046524545 # macro -# GSP_FW_FLAGS = 8 : 0 # macro -# GSP_FW_FLAGS_CLOCK_BOOST = NVBIT ( 0 ) # macro -# GSP_FW_FLAGS_RECOVERY_MARGIN_PRESENT = NVBIT ( 1 ) # macro -# GSP_FW_FLAGS_PPCIE_ENABLED = NVBIT ( 2 ) # macro -class struct_c__SA_GspFwWprMeta(Structure): - pass - -class union_c__SA_GspFwWprMeta_0(Union): - pass - -class struct_c__SA_GspFwWprMeta_0_0(Structure): - pass - -struct_c__SA_GspFwWprMeta_0_0._pack_ = 1 # source:False -struct_c__SA_GspFwWprMeta_0_0._fields_ = [ - ('sysmemAddrOfSignature', ctypes.c_uint64), - ('sizeOfSignature', ctypes.c_uint64), -] - -class struct_c__SA_GspFwWprMeta_0_1(Structure): - pass - -struct_c__SA_GspFwWprMeta_0_1._pack_ = 1 # source:False -struct_c__SA_GspFwWprMeta_0_1._fields_ = [ - ('gspFwHeapFreeListWprOffset', ctypes.c_uint32), - ('unused0', ctypes.c_uint32), - ('unused1', ctypes.c_uint64), -] - -union_c__SA_GspFwWprMeta_0._pack_ = 1 # source:False -union_c__SA_GspFwWprMeta_0._anonymous_ = ('_0', '_1',) -union_c__SA_GspFwWprMeta_0._fields_ = [ - ('_0', struct_c__SA_GspFwWprMeta_0_0), - ('_1', struct_c__SA_GspFwWprMeta_0_1), -] - -class union_c__SA_GspFwWprMeta_1(Union): - pass - -class struct_c__SA_GspFwWprMeta_1_0(Structure): - pass - -struct_c__SA_GspFwWprMeta_1_0._pack_ = 1 # source:False -struct_c__SA_GspFwWprMeta_1_0._fields_ = [ - ('partitionRpcAddr', ctypes.c_uint64), - ('partitionRpcRequestOffset', ctypes.c_uint16), - ('partitionRpcReplyOffset', ctypes.c_uint16), - ('elfCodeOffset', ctypes.c_uint32), - ('elfDataOffset', ctypes.c_uint32), - ('elfCodeSize', ctypes.c_uint32), - ('elfDataSize', ctypes.c_uint32), - ('lsUcodeVersion', ctypes.c_uint32), -] - -class struct_c__SA_GspFwWprMeta_1_1(Structure): - pass - -struct_c__SA_GspFwWprMeta_1_1._pack_ = 1 # source:False -struct_c__SA_GspFwWprMeta_1_1._fields_ = [ - ('partitionRpcPadding', ctypes.c_uint32 * 4), - ('sysmemAddrOfCrashReportQueue', ctypes.c_uint64), - ('sizeOfCrashReportQueue', ctypes.c_uint32), - ('lsUcodeVersionPadding', ctypes.c_uint32 * 1), -] - -union_c__SA_GspFwWprMeta_1._pack_ = 1 # source:False -union_c__SA_GspFwWprMeta_1._anonymous_ = ('_0', '_1',) -union_c__SA_GspFwWprMeta_1._fields_ = [ - ('_0', struct_c__SA_GspFwWprMeta_1_0), - ('_1', struct_c__SA_GspFwWprMeta_1_1), -] - -struct_c__SA_GspFwWprMeta._pack_ = 1 # source:False -struct_c__SA_GspFwWprMeta._anonymous_ = ('_0', '_1',) -struct_c__SA_GspFwWprMeta._fields_ = [ - ('magic', ctypes.c_uint64), - ('revision', ctypes.c_uint64), - ('sysmemAddrOfRadix3Elf', ctypes.c_uint64), - ('sizeOfRadix3Elf', ctypes.c_uint64), - ('sysmemAddrOfBootloader', ctypes.c_uint64), - ('sizeOfBootloader', ctypes.c_uint64), - ('bootloaderCodeOffset', ctypes.c_uint64), - ('bootloaderDataOffset', ctypes.c_uint64), - ('bootloaderManifestOffset', ctypes.c_uint64), - ('_0', union_c__SA_GspFwWprMeta_0), - ('gspFwRsvdStart', ctypes.c_uint64), - ('nonWprHeapOffset', ctypes.c_uint64), - ('nonWprHeapSize', ctypes.c_uint64), - ('gspFwWprStart', ctypes.c_uint64), - ('gspFwHeapOffset', ctypes.c_uint64), - ('gspFwHeapSize', ctypes.c_uint64), - ('gspFwOffset', ctypes.c_uint64), - ('bootBinOffset', ctypes.c_uint64), - ('frtsOffset', ctypes.c_uint64), - ('frtsSize', ctypes.c_uint64), - ('gspFwWprEnd', ctypes.c_uint64), - ('fbSize', ctypes.c_uint64), - ('vgaWorkspaceOffset', ctypes.c_uint64), - ('vgaWorkspaceSize', ctypes.c_uint64), - ('bootCount', ctypes.c_uint64), - ('_1', union_c__SA_GspFwWprMeta_1), - ('gspFwHeapVfPartitionCount', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('padding', ctypes.c_ubyte * 2), - ('pmuReservedSize', ctypes.c_uint32), - ('verified', ctypes.c_uint64), -] - -GspFwWprMeta = struct_c__SA_GspFwWprMeta -class struct_c__SA_GspFwHeapFreeRegion(Structure): - pass - -struct_c__SA_GspFwHeapFreeRegion._pack_ = 1 # source:False -struct_c__SA_GspFwHeapFreeRegion._fields_ = [ - ('offs', ctypes.c_uint32), - ('length', ctypes.c_uint32), -] - -GspFwHeapFreeRegion = struct_c__SA_GspFwHeapFreeRegion -class struct_c__SA_GspFwHeapFreeList(Structure): - pass - -struct_c__SA_GspFwHeapFreeList._pack_ = 1 # source:False -struct_c__SA_GspFwHeapFreeList._fields_ = [ - ('magic', ctypes.c_uint64), - ('nregions', ctypes.c_uint32), - ('regions', struct_c__SA_GspFwHeapFreeRegion * 128), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -GspFwHeapFreeList = struct_c__SA_GspFwHeapFreeList -GSP_FW_SR_META_H_ = True # macro -GSP_FW_SR_META_MAGIC = 0x8a3bb9e6c6c39d93 # macro -GSP_FW_SR_META_REVISION = 2 # macro -GSP_FW_SR_META_INTERNAL_SIZE = 128 # macro -class struct_c__SA_GspFwSRMeta(Structure): - pass - -struct_c__SA_GspFwSRMeta._pack_ = 1 # source:False -struct_c__SA_GspFwSRMeta._fields_ = [ - ('magic', ctypes.c_uint64), - ('revision', ctypes.c_uint64), - ('sysmemAddrOfSuspendResumeData', ctypes.c_uint64), - ('sizeOfSuspendResumeData', ctypes.c_uint64), - ('internal', ctypes.c_uint32 * 32), - ('flags', ctypes.c_uint32), - ('subrevision', ctypes.c_uint32), - ('padding', ctypes.c_uint32 * 22), -] - -GspFwSRMeta = struct_c__SA_GspFwSRMeta -GSP_INIT_ARGS_H = True # macro -class struct_c__SA_MESSAGE_QUEUE_INIT_ARGUMENTS(Structure): - pass - -struct_c__SA_MESSAGE_QUEUE_INIT_ARGUMENTS._pack_ = 1 # source:False -struct_c__SA_MESSAGE_QUEUE_INIT_ARGUMENTS._fields_ = [ - ('sharedMemPhysAddr', ctypes.c_uint64), - ('pageTableEntryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('cmdQueueOffset', ctypes.c_uint64), - ('statQueueOffset', ctypes.c_uint64), -] - -MESSAGE_QUEUE_INIT_ARGUMENTS = struct_c__SA_MESSAGE_QUEUE_INIT_ARGUMENTS -class struct_c__SA_GSP_SR_INIT_ARGUMENTS(Structure): - pass - -struct_c__SA_GSP_SR_INIT_ARGUMENTS._pack_ = 1 # source:False -struct_c__SA_GSP_SR_INIT_ARGUMENTS._fields_ = [ - ('oldLevel', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('bInPMTransition', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -GSP_SR_INIT_ARGUMENTS = struct_c__SA_GSP_SR_INIT_ARGUMENTS -class struct_c__SA_GSP_ARGUMENTS_CACHED(Structure): - pass - -class struct_c__SA_GSP_ARGUMENTS_CACHED_profilerArgs(Structure): - pass - -struct_c__SA_GSP_ARGUMENTS_CACHED_profilerArgs._pack_ = 1 # source:False -struct_c__SA_GSP_ARGUMENTS_CACHED_profilerArgs._fields_ = [ - ('pa', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -struct_c__SA_GSP_ARGUMENTS_CACHED._pack_ = 1 # source:False -struct_c__SA_GSP_ARGUMENTS_CACHED._fields_ = [ - ('messageQueueInitArguments', MESSAGE_QUEUE_INIT_ARGUMENTS), - ('srInitArguments', GSP_SR_INIT_ARGUMENTS), - ('gpuInstance', ctypes.c_uint32), - ('bDmemStack', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('profilerArgs', struct_c__SA_GSP_ARGUMENTS_CACHED_profilerArgs), -] - -GSP_ARGUMENTS_CACHED = struct_c__SA_GSP_ARGUMENTS_CACHED -LIBOS_INIT_H_ = True # macro -LIBOS_MEMORY_REGION_INIT_ARGUMENTS_MAX = 4096 # macro -LIBOS_MEMORY_REGION_RADIX_PAGE_SIZE = 4096 # macro -LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2 = 12 # macro -LibosAddress = ctypes.c_uint64 - -# values for enumeration 'c__EA_LibosMemoryRegionKind' -c__EA_LibosMemoryRegionKind__enumvalues = { - 0: 'LIBOS_MEMORY_REGION_NONE', - 1: 'LIBOS_MEMORY_REGION_CONTIGUOUS', - 2: 'LIBOS_MEMORY_REGION_RADIX3', -} -LIBOS_MEMORY_REGION_NONE = 0 -LIBOS_MEMORY_REGION_CONTIGUOUS = 1 -LIBOS_MEMORY_REGION_RADIX3 = 2 -c__EA_LibosMemoryRegionKind = ctypes.c_uint32 # enum -LibosMemoryRegionKind = c__EA_LibosMemoryRegionKind -LibosMemoryRegionKind__enumvalues = c__EA_LibosMemoryRegionKind__enumvalues - -# values for enumeration 'c__EA_LibosMemoryRegionLoc' -c__EA_LibosMemoryRegionLoc__enumvalues = { - 0: 'LIBOS_MEMORY_REGION_LOC_NONE', - 1: 'LIBOS_MEMORY_REGION_LOC_SYSMEM', - 2: 'LIBOS_MEMORY_REGION_LOC_FB', -} -LIBOS_MEMORY_REGION_LOC_NONE = 0 -LIBOS_MEMORY_REGION_LOC_SYSMEM = 1 -LIBOS_MEMORY_REGION_LOC_FB = 2 -c__EA_LibosMemoryRegionLoc = ctypes.c_uint32 # enum -LibosMemoryRegionLoc = c__EA_LibosMemoryRegionLoc -LibosMemoryRegionLoc__enumvalues = c__EA_LibosMemoryRegionLoc__enumvalues -class struct_c__SA_LibosMemoryRegionInitArgument(Structure): - pass - -struct_c__SA_LibosMemoryRegionInitArgument._pack_ = 1 # source:False -struct_c__SA_LibosMemoryRegionInitArgument._fields_ = [ - ('id8', ctypes.c_uint64), - ('pa', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('kind', ctypes.c_ubyte), - ('loc', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -LibosMemoryRegionInitArgument = struct_c__SA_LibosMemoryRegionInitArgument -RM_RISCV_UCODE_H = True # macro -class struct_c__SA_RM_RISCV_UCODE_DESC(Structure): - pass - -struct_c__SA_RM_RISCV_UCODE_DESC._pack_ = 1 # source:False -struct_c__SA_RM_RISCV_UCODE_DESC._fields_ = [ - ('version', ctypes.c_uint32), - ('bootloaderOffset', ctypes.c_uint32), - ('bootloaderSize', ctypes.c_uint32), - ('bootloaderParamOffset', ctypes.c_uint32), - ('bootloaderParamSize', ctypes.c_uint32), - ('riscvElfOffset', ctypes.c_uint32), - ('riscvElfSize', ctypes.c_uint32), - ('appVersion', ctypes.c_uint32), - ('manifestOffset', ctypes.c_uint32), - ('manifestSize', ctypes.c_uint32), - ('monitorDataOffset', ctypes.c_uint32), - ('monitorDataSize', ctypes.c_uint32), - ('monitorCodeOffset', ctypes.c_uint32), - ('monitorCodeSize', ctypes.c_uint32), - ('bIsMonitorEnabled', ctypes.c_uint32), - ('swbromCodeOffset', ctypes.c_uint32), - ('swbromCodeSize', ctypes.c_uint32), - ('swbromDataOffset', ctypes.c_uint32), - ('swbromDataSize', ctypes.c_uint32), - ('fbReservedSize', ctypes.c_uint32), - ('bSignedAsCode', ctypes.c_uint32), -] - -RM_RISCV_UCODE_DESC = struct_c__SA_RM_RISCV_UCODE_DESC -MSGQ_PRIV_H = True # macro -MSGQ_VERSION = 0 # macro -class struct_c__SA_msgqTxHeader(Structure): - pass - -struct_c__SA_msgqTxHeader._pack_ = 1 # source:False -struct_c__SA_msgqTxHeader._fields_ = [ - ('version', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('msgSize', ctypes.c_uint32), - ('msgCount', ctypes.c_uint32), - ('writePtr', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('rxHdrOff', ctypes.c_uint32), - ('entryOff', ctypes.c_uint32), -] - -msgqTxHeader = struct_c__SA_msgqTxHeader -class struct_c__SA_msgqRxHeader(Structure): - pass - -struct_c__SA_msgqRxHeader._pack_ = 1 # source:False -struct_c__SA_msgqRxHeader._fields_ = [ - ('readPtr', ctypes.c_uint32), -] - -msgqRxHeader = struct_c__SA_msgqRxHeader -class struct_c__SA_msgqMetadata(Structure): - pass - -struct_c__SA_msgqMetadata._pack_ = 1 # source:False -struct_c__SA_msgqMetadata._fields_ = [ - ('pOurTxHdr', ctypes.POINTER(struct_c__SA_msgqTxHeader)), - ('pTheirTxHdr', ctypes.POINTER(struct_c__SA_msgqTxHeader)), - ('pOurRxHdr', ctypes.POINTER(struct_c__SA_msgqRxHeader)), - ('pTheirRxHdr', ctypes.POINTER(struct_c__SA_msgqRxHeader)), - ('pOurEntries', ctypes.POINTER(ctypes.c_ubyte)), - ('pTheirEntries', ctypes.POINTER(ctypes.c_ubyte)), - ('pReadIncoming', ctypes.POINTER(ctypes.c_uint32)), - ('pWriteIncoming', ctypes.POINTER(ctypes.c_uint32)), - ('pReadOutgoing', ctypes.POINTER(ctypes.c_uint32)), - ('pWriteOutgoing', ctypes.POINTER(ctypes.c_uint32)), - ('tx', msgqTxHeader), - ('txReadPtr', ctypes.c_uint32), - ('txFree', ctypes.c_uint32), - ('txLinked', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rx', msgqTxHeader), - ('rxReadPtr', ctypes.c_uint32), - ('rxAvail', ctypes.c_uint32), - ('rxLinked', ctypes.c_ubyte), - ('rxSwapped', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('fcnNotify', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None))), - ('fcnNotifyArg', ctypes.POINTER(None)), - ('fcnBackendRw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.POINTER(None))), - ('fcnBackendRwArg', ctypes.POINTER(None)), - ('fcnInvalidate', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint32)), - ('fcnFlush', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint32)), - ('fcnZero', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint32)), - ('fcnBarrier', ctypes.CFUNCTYPE(None)), -] - -msgqMetadata = struct_c__SA_msgqMetadata -__vgpu_rpc_nv_headers_h__ = True # macro -MAX_GPC_COUNT = 32 # macro -VGPU_MAX_REGOPS_PER_RPC = 100 # macro -VGPU_RESERVED_HANDLE_BASE = 0xCAF3F000 # macro -VGPU_RESERVED_HANDLE_RANGE = 0x1000 # macro -# def VGPU_CALC_PARAM_OFFSET(prev_offset, prev_params): # macro -# return (prev_offset+NV_ALIGN_UP(ctypes.sizeof(prev_params),ctypes.sizeof(NvU32))) -# NV_VGPU_MSG_HEADER_VERSION_MAJOR = 31 : 24 # macro -# NV_VGPU_MSG_HEADER_VERSION_MINOR = 23 : 16 # macro -NV_VGPU_MSG_HEADER_VERSION_MAJOR_TOT = 0x00000003 # macro -NV_VGPU_MSG_HEADER_VERSION_MINOR_TOT = 0x00000000 # macro -NV_VGPU_MSG_SIGNATURE_VALID = 0x43505256 # macro -_RPC_GLOBAL_ENUMS_H_ = True # macro -# def X(UNIT, RPC, VAL): # macro -# return NV_VGPU_MSG_FUNCTION_##RPC=VAL, -DEFINING_X_IN_RPC_GLOBAL_ENUMS_H = True # macro -# def E(RPC, VAL): # macro -# return NV_VGPU_MSG_EVENT_##RPC=VAL, -DEFINING_E_IN_RPC_GLOBAL_ENUMS_H = True # macro -# NV_VGPU_MSG_RESULT__RM = NV_ERR_GENERIC : 0x00000000 # macro -# NV_VGPU_MSG_RESULT_SUCCESS = NV_OK # macro -# NV_VGPU_MSG_RESULT_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT # macro -# NV_VGPU_MSG_RESULT_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE # macro -# NV_VGPU_MSG_RESULT_GENERIC = NV_ERR_GENERIC # macro -# NV_VGPU_MSG_RESULT_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER # macro -# NV_VGPU_MSG_RESULT_IN_USE = NV_ERR_IN_USE # macro -# NV_VGPU_MSG_RESULT_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES # macro -# NV_VGPU_MSG_RESULT_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE # macro -# NV_VGPU_MSG_RESULT_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT # macro -# NV_VGPU_MSG_RESULT_INVALID_BASE = NV_ERR_INVALID_BASE # macro -# NV_VGPU_MSG_RESULT_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL # macro -# NV_VGPU_MSG_RESULT_INVALID_CLASS = NV_ERR_INVALID_CLASS # macro -# NV_VGPU_MSG_RESULT_INVALID_CLIENT = NV_ERR_INVALID_CLIENT # macro -# NV_VGPU_MSG_RESULT_INVALID_COMMAND = NV_ERR_INVALID_COMMAND # macro -# NV_VGPU_MSG_RESULT_INVALID_DATA = NV_ERR_INVALID_DATA # macro -# NV_VGPU_MSG_RESULT_INVALID_DEVICE = NV_ERR_INVALID_DEVICE # macro -# NV_VGPU_MSG_RESULT_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER # macro -# NV_VGPU_MSG_RESULT_INVALID_EVENT = NV_ERR_INVALID_EVENT # macro -# NV_VGPU_MSG_RESULT_INVALID_FLAGS = NV_ERR_INVALID_FLAGS # macro -# NV_VGPU_MSG_RESULT_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION # macro -# NV_VGPU_MSG_RESULT_INVALID_HEAP = NV_ERR_INVALID_HEAP # macro -# NV_VGPU_MSG_RESULT_INVALID_INDEX = NV_ERR_INVALID_INDEX # macro -# NV_VGPU_MSG_RESULT_INVALID_LIMIT = NV_ERR_INVALID_LIMIT # macro -# NV_VGPU_MSG_RESULT_INVALID_METHOD = NV_ERR_INVALID_METHOD # macro -# NV_VGPU_MSG_RESULT_INVALID_OBJECT_BUFFER = NV_ERR_INVALID_OBJECT_BUFFER # macro -# NV_VGPU_MSG_RESULT_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT # macro -# NV_VGPU_MSG_RESULT_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE # macro -# NV_VGPU_MSG_RESULT_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW # macro -# NV_VGPU_MSG_RESULT_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD # macro -# NV_VGPU_MSG_RESULT_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT # macro -# NV_VGPU_MSG_RESULT_INVALID_OFFSET = NV_ERR_INVALID_OFFSET # macro -# NV_VGPU_MSG_RESULT_INVALID_OWNER = NV_ERR_INVALID_OWNER # macro -# NV_VGPU_MSG_RESULT_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT # macro -# NV_VGPU_MSG_RESULT_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER # macro -# NV_VGPU_MSG_RESULT_INVALID_POINTER = NV_ERR_INVALID_POINTER # macro -# NV_VGPU_MSG_RESULT_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY # macro -# NV_VGPU_MSG_RESULT_INVALID_STATE = NV_ERR_INVALID_STATE # macro -# NV_VGPU_MSG_RESULT_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH # macro -# NV_VGPU_MSG_RESULT_INVALID_XLATE = NV_ERR_INVALID_XLATE # macro -# NV_VGPU_MSG_RESULT_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING # macro -# NV_VGPU_MSG_RESULT_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES # macro -# NV_VGPU_MSG_RESULT_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED # macro -# NV_VGPU_MSG_RESULT_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM # macro -# NV_VGPU_MSG_RESULT_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT # macro -# NV_VGPU_MSG_RESULT_TIMEOUT = NV_ERR_TIMEOUT # macro -# NV_VGPU_MSG_RESULT_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES # macro -# NV_VGPU_MSG_RESULT_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED # macro -# NV_VGPU_MSG_RESULT_GUEST_HOST_DRIVER_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH # macro -# NV_VGPU_MSG_RESULT__VMIOP = 0xFF00000a : 0xFF000000 # macro -NV_VGPU_MSG_RESULT_VMIOP_INVAL = 0xFF000001 # macro -NV_VGPU_MSG_RESULT_VMIOP_RESOURCE = 0xFF000002 # macro -NV_VGPU_MSG_RESULT_VMIOP_RANGE = 0xFF000003 # macro -NV_VGPU_MSG_RESULT_VMIOP_READ_ONLY = 0xFF000004 # macro -NV_VGPU_MSG_RESULT_VMIOP_NOT_FOUND = 0xFF000005 # macro -NV_VGPU_MSG_RESULT_VMIOP_NO_ADDRESS_SPACE = 0xFF000006 # macro -NV_VGPU_MSG_RESULT_VMIOP_TIMEOUT = 0xFF000007 # macro -NV_VGPU_MSG_RESULT_VMIOP_NOT_ALLOWED_IN_CALLBACK = 0xFF000008 # macro -NV_VGPU_MSG_RESULT_VMIOP_ECC_MISMATCH = 0xFF000009 # macro -NV_VGPU_MSG_RESULT_VMIOP_NOT_SUPPORTED = 0xFF00000a # macro -# NV_VGPU_MSG_RESULT__RPC = 0xFF100009 : 0xFF100000 # macro -NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION = 0xFF100001 # macro -NV_VGPU_MSG_RESULT_RPC_INVALID_MESSAGE_FORMAT = 0xFF100002 # macro -NV_VGPU_MSG_RESULT_RPC_HANDLE_NOT_FOUND = 0xFF100003 # macro -NV_VGPU_MSG_RESULT_RPC_HANDLE_EXISTS = 0xFF100004 # macro -NV_VGPU_MSG_RESULT_RPC_UNKNOWN_RM_ERROR = 0xFF100005 # macro -NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR = 0xFF100006 # macro -NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE = 0xFF100007 # macro -NV_VGPU_MSG_RESULT_RPC_CUDA_PROFILING_DISABLED = 0xFF100008 # macro -NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED = 0xFF100009 # macro -NV_VGPU_MSG_RESULT_RPC_PENDING = 0xFFFFFFFF # macro -NV_VGPU_MSG_UNION_INIT = 0x00000000 # macro -NV_VGPU_PTEDESC_INIT = 0x00000000 # macro -NV_VGPU_PTEDESC__PROD = 0x00000000 # macro -NV_VGPU_PTEDESC_IDR_NONE = 0x00000000 # macro -NV_VGPU_PTEDESC_IDR_SINGLE = 0x00000001 # macro -NV_VGPU_PTEDESC_IDR_DOUBLE = 0x00000002 # macro -NV_VGPU_PTEDESC_IDR_TRIPLE = 0x00000003 # macro -NV_VGPU_PTE_PAGE_SIZE = 0x1000 # macro -NV_VGPU_PTE_SIZE = 4 # macro -NV_VGPU_PTE_INDEX_SHIFT = 10 # macro -NV_VGPU_PTE_INDEX_MASK = 0x3FF # macro -NV_VGPU_PTE_64_PAGE_SIZE = 0x1000 # macro -NV_VGPU_PTE_64_SIZE = 8 # macro -NV_VGPU_PTE_64_INDEX_SHIFT = 9 # macro -NV_VGPU_PTE_64_INDEX_MASK = 0x1FF # macro -NV_VGPU_LOG_LEVEL_FATAL = 0x00000000 # macro -NV_VGPU_LOG_LEVEL_ERROR = 0x00000001 # macro -NV_VGPU_LOG_LEVEL_NOTICE = 0x00000002 # macro -NV_VGPU_LOG_LEVEL_STATUS = 0x00000003 # macro -NV_VGPU_LOG_LEVEL_DEBUG = 0x00000004 # macro -VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC = 512 # macro -GR_MAX_RPC_CTX_BUFFER_COUNT = 32 # macro -VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 = 80 # macro - -# values for enumeration 'c__Ea_NV_VGPU_MSG_FUNCTION_NOP' -c__Ea_NV_VGPU_MSG_FUNCTION_NOP__enumvalues = { - 0: 'NV_VGPU_MSG_FUNCTION_NOP', - 1: 'NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO', - 2: 'NV_VGPU_MSG_FUNCTION_ALLOC_ROOT', - 3: 'NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE', - 4: 'NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY', - 5: 'NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA', - 6: 'NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA', - 7: 'NV_VGPU_MSG_FUNCTION_MAP_MEMORY', - 8: 'NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA', - 9: 'NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT', - 10: 'NV_VGPU_MSG_FUNCTION_FREE', - 11: 'NV_VGPU_MSG_FUNCTION_LOG', - 12: 'NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM', - 13: 'NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY', - 14: 'NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA', - 15: 'NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA', - 16: 'NV_VGPU_MSG_FUNCTION_GET_EDID', - 17: 'NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL', - 18: 'NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT', - 19: 'NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE', - 20: 'NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY', - 21: 'NV_VGPU_MSG_FUNCTION_DUP_OBJECT', - 22: 'NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS', - 23: 'NV_VGPU_MSG_FUNCTION_ALLOC_EVENT', - 24: 'NV_VGPU_MSG_FUNCTION_SEND_EVENT', - 25: 'NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL', - 26: 'NV_VGPU_MSG_FUNCTION_DMA_CONTROL', - 27: 'NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM', - 28: 'NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE', - 29: 'NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA', - 30: 'NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT', - 31: 'NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT', - 32: 'NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE', - 33: 'NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL', - 34: 'NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API', - 35: 'NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ', - 36: 'NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE', - 37: 'NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA', - 38: 'NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT', - 39: 'NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO', - 40: 'NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE', - 41: 'NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO', - 42: 'NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO', - 43: 'NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY', - 44: 'NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY', - 45: 'NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES', - 46: 'NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE', - 47: 'NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER', - 48: 'NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE', - 49: 'NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA', - 50: 'NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS', - 51: 'NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO', - 52: 'NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM', - 53: 'NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2', - 54: 'NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY', - 55: 'NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO', - 56: 'NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES', - 57: 'NV_VGPU_MSG_FUNCTION_RESERVED_57', - 58: 'NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT', - 59: 'NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE', - 60: 'NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION', - 61: 'NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES', - 62: 'NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY', - 63: 'NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32', - 64: 'NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT', - 65: 'NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO', - 66: 'NV_VGPU_MSG_FUNCTION_RMFS_INIT', - 67: 'NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE', - 68: 'NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP', - 69: 'NV_VGPU_MSG_FUNCTION_RMFS_TEST', - 70: 'NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE', - 71: 'NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD', - 72: 'NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO', - 73: 'NV_VGPU_MSG_FUNCTION_SET_REGISTRY', - 74: 'NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU', - 75: 'NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION', - 76: 'NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL', - 77: 'NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2', - 78: 'NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT', - 79: 'NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY', - 80: 'NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO', - 81: 'NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER', - 82: 'NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER', - 83: 'NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 84: 'NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 85: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE', - 86: 'NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO', - 87: 'NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO', - 88: 'NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL', - 89: 'NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL', - 90: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT', - 91: 'NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO', - 92: 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST', - 93: 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL', - 94: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE', - 95: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR', - 96: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR', - 97: 'NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE', - 98: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE', - 99: 'NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT', - 100: 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS', - 101: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL', - 102: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL', - 103: 'NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC', - 104: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2', - 105: 'NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT', - 106: 'NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY', - 107: 'NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS', - 108: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES', - 109: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES', - 110: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK', - 111: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX', - 112: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND', - 113: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE', - 114: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND', - 115: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX', - 116: 'NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES', - 117: 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT', - 118: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES', - 119: 'NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS', - 120: 'NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE', - 121: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK', - 122: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY', - 123: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK', - 124: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS', - 125: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS', - 126: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX', - 127: 'NV_VGPU_MSG_FUNCTION_RESERVED_0', - 128: 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC', - 129: 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY', - 130: 'NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS', - 131: 'NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES', - 132: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT', - 133: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT', - 134: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS', - 135: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG', - 136: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE', - 137: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE', - 138: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG', - 139: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE', - 140: 'NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM', - 141: 'NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT', - 142: 'NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2', - 143: 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES', - 144: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO', - 145: 'NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES', - 146: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX', - 147: 'NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO', - 148: 'NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO', - 149: 'NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL', - 150: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE', - 151: 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS', - 152: 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL', - 153: 'NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM', - 154: 'NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ', - 155: 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB', - 156: 'NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO', - 157: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP', - 158: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE', - 159: 'NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE', - 160: 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE', - 161: 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY', - 162: 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP', - 163: 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP', - 164: 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM', - 165: 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES', - 166: 'NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION', - 167: 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL', - 168: 'NV_VGPU_MSG_FUNCTION_DCE_RM_INIT', - 169: 'NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER', - 170: 'NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET', - 171: 'NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND', - 172: 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2', - 173: 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM', - 174: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE', - 175: 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS', - 176: 'NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE', - 177: 'NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO', - 178: 'NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS', - 179: 'NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE', - 180: 'NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS', - 181: 'NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA', - 182: 'NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA', - 183: 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED', - 184: 'NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE', - 185: 'NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE', - 186: 'NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN', - 187: 'NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX', - 188: 'NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION', - 189: 'NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK', - 190: 'NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER', - 191: 'NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS', - 192: 'NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING', - 193: 'NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING', - 194: 'NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK', - 195: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS', - 196: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS', - 197: 'NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS', - 198: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS', - 199: 'NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER', - 200: 'NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB', - 201: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS', - 202: 'NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK', - 203: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG', - 204: 'NV_VGPU_MSG_FUNCTION_RM_API_CONTROL', - 205: 'NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE', - 206: 'NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA', - 207: 'NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA', - 208: 'NV_VGPU_MSG_FUNCTION_RESERVED_208', - 209: 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2', - 210: 'NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS', - 211: 'NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA', - 212: 'NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO', - 213: 'NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE', - 214: 'NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR', - 215: 'NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS', - 216: 'NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS', - 217: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG', - 218: 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG', - 219: 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES', - 220: 'NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES', - 221: 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF', - 222: 'NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF', - 223: 'NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS', -} -NV_VGPU_MSG_FUNCTION_NOP = 0 -NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO = 1 -NV_VGPU_MSG_FUNCTION_ALLOC_ROOT = 2 -NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE = 3 -NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY = 4 -NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA = 5 -NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA = 6 -NV_VGPU_MSG_FUNCTION_MAP_MEMORY = 7 -NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA = 8 -NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT = 9 -NV_VGPU_MSG_FUNCTION_FREE = 10 -NV_VGPU_MSG_FUNCTION_LOG = 11 -NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM = 12 -NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY = 13 -NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA = 14 -NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA = 15 -NV_VGPU_MSG_FUNCTION_GET_EDID = 16 -NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL = 17 -NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT = 18 -NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE = 19 -NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY = 20 -NV_VGPU_MSG_FUNCTION_DUP_OBJECT = 21 -NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS = 22 -NV_VGPU_MSG_FUNCTION_ALLOC_EVENT = 23 -NV_VGPU_MSG_FUNCTION_SEND_EVENT = 24 -NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL = 25 -NV_VGPU_MSG_FUNCTION_DMA_CONTROL = 26 -NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM = 27 -NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE = 28 -NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA = 29 -NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT = 30 -NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT = 31 -NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE = 32 -NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL = 33 -NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API = 34 -NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ = 35 -NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE = 36 -NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA = 37 -NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT = 38 -NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO = 39 -NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE = 40 -NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO = 41 -NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO = 42 -NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY = 43 -NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY = 44 -NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES = 45 -NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE = 46 -NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER = 47 -NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE = 48 -NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA = 49 -NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS = 50 -NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO = 51 -NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM = 52 -NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2 = 53 -NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY = 54 -NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO = 55 -NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES = 56 -NV_VGPU_MSG_FUNCTION_RESERVED_57 = 57 -NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT = 58 -NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE = 59 -NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION = 60 -NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES = 61 -NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY = 62 -NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32 = 63 -NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT = 64 -NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO = 65 -NV_VGPU_MSG_FUNCTION_RMFS_INIT = 66 -NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE = 67 -NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP = 68 -NV_VGPU_MSG_FUNCTION_RMFS_TEST = 69 -NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE = 70 -NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD = 71 -NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO = 72 -NV_VGPU_MSG_FUNCTION_SET_REGISTRY = 73 -NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU = 74 -NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION = 75 -NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL = 76 -NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2 = 77 -NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT = 78 -NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY = 79 -NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO = 80 -NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER = 81 -NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER = 82 -NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = 83 -NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = 84 -NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE = 85 -NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO = 86 -NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO = 87 -NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL = 88 -NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL = 89 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT = 90 -NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO = 91 -NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST = 92 -NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL = 93 -NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE = 94 -NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR = 95 -NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR = 96 -NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE = 97 -NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE = 98 -NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT = 99 -NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS = 100 -NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL = 101 -NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL = 102 -NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC = 103 -NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2 = 104 -NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT = 105 -NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY = 106 -NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS = 107 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES = 108 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES = 109 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK = 110 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX = 111 -NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND = 112 -NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE = 113 -NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND = 114 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX = 115 -NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES = 116 -NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT = 117 -NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES = 118 -NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS = 119 -NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE = 120 -NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK = 121 -NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY = 122 -NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK = 123 -NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS = 124 -NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS = 125 -NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX = 126 -NV_VGPU_MSG_FUNCTION_RESERVED_0 = 127 -NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC = 128 -NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY = 129 -NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS = 130 -NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES = 131 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT = 132 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT = 133 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS = 134 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG = 135 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE = 136 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE = 137 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG = 138 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE = 139 -NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM = 140 -NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT = 141 -NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2 = 142 -NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES = 143 -NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO = 144 -NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES = 145 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX = 146 -NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO = 147 -NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO = 148 -NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL = 149 -NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE = 150 -NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS = 151 -NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL = 152 -NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM = 153 -NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ = 154 -NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = 155 -NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO = 156 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP = 157 -NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE = 158 -NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE = 159 -NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE = 160 -NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY = 161 -NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP = 162 -NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP = 163 -NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM = 164 -NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES = 165 -NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION = 166 -NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL = 167 -NV_VGPU_MSG_FUNCTION_DCE_RM_INIT = 168 -NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER = 169 -NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET = 170 -NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND = 171 -NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2 = 172 -NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM = 173 -NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE = 174 -NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = 175 -NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE = 176 -NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO = 177 -NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS = 178 -NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE = 179 -NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS = 180 -NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA = 181 -NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA = 182 -NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = 183 -NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE = 184 -NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE = 185 -NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN = 186 -NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = 187 -NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION = 188 -NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK = 189 -NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER = 190 -NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS = 191 -NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING = 192 -NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING = 193 -NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK = 194 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS = 195 -NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS = 196 -NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS = 197 -NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS = 198 -NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER = 199 -NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB = 200 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS = 201 -NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK = 202 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG = 203 -NV_VGPU_MSG_FUNCTION_RM_API_CONTROL = 204 -NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = 205 -NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA = 206 -NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA = 207 -NV_VGPU_MSG_FUNCTION_RESERVED_208 = 208 -NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2 = 209 -NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS = 210 -NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA = 211 -NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO = 212 -NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = 213 -NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR = 214 -NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS = 215 -NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS = 216 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG = 217 -NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG = 218 -NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES = 219 -NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES = 220 -NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF = 221 -NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF = 222 -NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS = 223 -c__Ea_NV_VGPU_MSG_FUNCTION_NOP = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_NV_VGPU_MSG_EVENT_FIRST_EVENT' -c__Ea_NV_VGPU_MSG_EVENT_FIRST_EVENT__enumvalues = { - 4096: 'NV_VGPU_MSG_EVENT_FIRST_EVENT', - 4097: 'NV_VGPU_MSG_EVENT_GSP_INIT_DONE', - 4098: 'NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER', - 4099: 'NV_VGPU_MSG_EVENT_POST_EVENT', - 4100: 'NV_VGPU_MSG_EVENT_RC_TRIGGERED', - 4101: 'NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED', - 4102: 'NV_VGPU_MSG_EVENT_OS_ERROR_LOG', - 4103: 'NV_VGPU_MSG_EVENT_RG_LINE_INTR', - 4104: 'NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES', - 4105: 'NV_VGPU_MSG_EVENT_SIM_READ', - 4106: 'NV_VGPU_MSG_EVENT_SIM_WRITE', - 4107: 'NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK', - 4108: 'NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT', - 4109: 'NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED', - 4110: 'NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK', - 4111: 'NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE', - 4112: 'NV_VGPU_MSG_EVENT_VGPU_CONFIG', - 4113: 'NV_VGPU_MSG_EVENT_DISPLAY_MODESET', - 4114: 'NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE', - 4115: 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256', - 4116: 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512', - 4117: 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024', - 4118: 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048', - 4119: 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096', - 4120: 'NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE', - 4121: 'NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED', - 4122: 'NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK', - 4123: 'NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP', - 4124: 'NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE', - 4125: 'NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE', - 4126: 'NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE', - 4127: 'NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY', - 4128: 'NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD', - 4129: 'NV_VGPU_MSG_EVENT_FECS_ERROR', - 4130: 'NV_VGPU_MSG_EVENT_RECOVERY_ACTION', - 4131: 'NV_VGPU_MSG_EVENT_NUM_EVENTS', -} -NV_VGPU_MSG_EVENT_FIRST_EVENT = 4096 -NV_VGPU_MSG_EVENT_GSP_INIT_DONE = 4097 -NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER = 4098 -NV_VGPU_MSG_EVENT_POST_EVENT = 4099 -NV_VGPU_MSG_EVENT_RC_TRIGGERED = 4100 -NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED = 4101 -NV_VGPU_MSG_EVENT_OS_ERROR_LOG = 4102 -NV_VGPU_MSG_EVENT_RG_LINE_INTR = 4103 -NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES = 4104 -NV_VGPU_MSG_EVENT_SIM_READ = 4105 -NV_VGPU_MSG_EVENT_SIM_WRITE = 4106 -NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK = 4107 -NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT = 4108 -NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED = 4109 -NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK = 4110 -NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE = 4111 -NV_VGPU_MSG_EVENT_VGPU_CONFIG = 4112 -NV_VGPU_MSG_EVENT_DISPLAY_MODESET = 4113 -NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE = 4114 -NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256 = 4115 -NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512 = 4116 -NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024 = 4117 -NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048 = 4118 -NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096 = 4119 -NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE = 4120 -NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED = 4121 -NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK = 4122 -NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP = 4123 -NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE = 4124 -NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE = 4125 -NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE = 4126 -NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY = 4127 -NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD = 4128 -NV_VGPU_MSG_EVENT_FECS_ERROR = 4129 -NV_VGPU_MSG_EVENT_RECOVERY_ACTION = 4130 -NV_VGPU_MSG_EVENT_NUM_EVENTS = 4131 -c__Ea_NV_VGPU_MSG_EVENT_FIRST_EVENT = ctypes.c_uint32 # enum - -# values for enumeration 'c__EA_RPC_GR_BUFFER_TYPE' -c__EA_RPC_GR_BUFFER_TYPE__enumvalues = { - 0: 'RPC_GR_BUFFER_TYPE_GRAPHICS', - 1: 'RPC_GR_BUFFER_TYPE_GRAPHICS_ZCULL', - 2: 'RPC_GR_BUFFER_TYPE_GRAPHICS_GRAPHICS_PM', - 3: 'RPC_GR_BUFFER_TYPE_COMPUTE_PREEMPT', - 4: 'RPC_GR_BUFFER_TYPE_GRAPHICS_PATCH', - 5: 'RPC_GR_BUFFER_TYPE_GRAPHICS_BUNDLE_CB', - 6: 'RPC_GR_BUFFER_TYPE_GRAPHICS_PAGEPOOL_GLOBAL', - 7: 'RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB', - 8: 'RPC_GR_BUFFER_TYPE_GRAPHICS_RTV_CB_GLOBAL', - 9: 'RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_POOL', - 10: 'RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_CTRL_BLK', - 11: 'RPC_GR_BUFFER_TYPE_GRAPHICS_FECS_EVENT', - 12: 'RPC_GR_BUFFER_TYPE_GRAPHICS_PRIV_ACCESS_MAP', - 13: 'RPC_GR_BUFFER_TYPE_GRAPHICS_MAX', -} -RPC_GR_BUFFER_TYPE_GRAPHICS = 0 -RPC_GR_BUFFER_TYPE_GRAPHICS_ZCULL = 1 -RPC_GR_BUFFER_TYPE_GRAPHICS_GRAPHICS_PM = 2 -RPC_GR_BUFFER_TYPE_COMPUTE_PREEMPT = 3 -RPC_GR_BUFFER_TYPE_GRAPHICS_PATCH = 4 -RPC_GR_BUFFER_TYPE_GRAPHICS_BUNDLE_CB = 5 -RPC_GR_BUFFER_TYPE_GRAPHICS_PAGEPOOL_GLOBAL = 6 -RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB = 7 -RPC_GR_BUFFER_TYPE_GRAPHICS_RTV_CB_GLOBAL = 8 -RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_POOL = 9 -RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_CTRL_BLK = 10 -RPC_GR_BUFFER_TYPE_GRAPHICS_FECS_EVENT = 11 -RPC_GR_BUFFER_TYPE_GRAPHICS_PRIV_ACCESS_MAP = 12 -RPC_GR_BUFFER_TYPE_GRAPHICS_MAX = 13 -c__EA_RPC_GR_BUFFER_TYPE = ctypes.c_uint32 # enum -RPC_GR_BUFFER_TYPE = c__EA_RPC_GR_BUFFER_TYPE -RPC_GR_BUFFER_TYPE__enumvalues = c__EA_RPC_GR_BUFFER_TYPE__enumvalues - -# values for enumeration 'c__EA_FECS_ERROR_EVENT_TYPE' -c__EA_FECS_ERROR_EVENT_TYPE__enumvalues = { - 0: 'FECS_ERROR_EVENT_TYPE_NONE', - 1: 'FECS_ERROR_EVENT_TYPE_BUFFER_RESET_REQUIRED', - 2: 'FECS_ERROR_EVENT_TYPE_BUFFER_FULL', - 3: 'FECS_ERROR_EVENT_TYPE_MAX', -} -FECS_ERROR_EVENT_TYPE_NONE = 0 -FECS_ERROR_EVENT_TYPE_BUFFER_RESET_REQUIRED = 1 -FECS_ERROR_EVENT_TYPE_BUFFER_FULL = 2 -FECS_ERROR_EVENT_TYPE_MAX = 3 -c__EA_FECS_ERROR_EVENT_TYPE = ctypes.c_uint32 # enum -FECS_ERROR_EVENT_TYPE = c__EA_FECS_ERROR_EVENT_TYPE -FECS_ERROR_EVENT_TYPE__enumvalues = c__EA_FECS_ERROR_EVENT_TYPE__enumvalues - -# values for enumeration 'c__EA_NV_RPC_UPDATE_PDE_BAR_TYPE' -c__EA_NV_RPC_UPDATE_PDE_BAR_TYPE__enumvalues = { - 0: 'NV_RPC_UPDATE_PDE_BAR_1', - 1: 'NV_RPC_UPDATE_PDE_BAR_2', - 2: 'NV_RPC_UPDATE_PDE_BAR_INVALID', -} -NV_RPC_UPDATE_PDE_BAR_1 = 0 -NV_RPC_UPDATE_PDE_BAR_2 = 1 -NV_RPC_UPDATE_PDE_BAR_INVALID = 2 -c__EA_NV_RPC_UPDATE_PDE_BAR_TYPE = ctypes.c_uint32 # enum -NV_RPC_UPDATE_PDE_BAR_TYPE = c__EA_NV_RPC_UPDATE_PDE_BAR_TYPE -NV_RPC_UPDATE_PDE_BAR_TYPE__enumvalues = c__EA_NV_RPC_UPDATE_PDE_BAR_TYPE__enumvalues -class struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS(Structure): - pass - -struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS._pack_ = 1 # source:False -struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS._fields_ = [ - ('headIndex', ctypes.c_uint32), - ('maxHResolution', ctypes.c_uint32), - ('maxVResolution', ctypes.c_uint32), -] - -VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS = struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS -class struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS(Structure): - pass - -struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS._pack_ = 1 # source:False -struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS._fields_ = [ - ('numHeads', ctypes.c_uint32), - ('maxNumHeads', ctypes.c_uint32), -] - -VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS = struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS - -# values for enumeration 'c__EA_GPU_RECOVERY_EVENT_TYPE' -c__EA_GPU_RECOVERY_EVENT_TYPE__enumvalues = { - 0: 'GPU_RECOVERY_EVENT_TYPE_REFRESH', - 1: 'GPU_RECOVERY_EVENT_TYPE_GPU_DRAIN_P2P', - 2: 'GPU_RECOVERY_EVENT_TYPE_SYS_REBOOT', -} -GPU_RECOVERY_EVENT_TYPE_REFRESH = 0 -GPU_RECOVERY_EVENT_TYPE_GPU_DRAIN_P2P = 1 -GPU_RECOVERY_EVENT_TYPE_SYS_REBOOT = 2 -c__EA_GPU_RECOVERY_EVENT_TYPE = ctypes.c_uint32 # enum -GPU_RECOVERY_EVENT_TYPE = c__EA_GPU_RECOVERY_EVENT_TYPE -GPU_RECOVERY_EVENT_TYPE__enumvalues = c__EA_GPU_RECOVERY_EVENT_TYPE__enumvalues -SDK_STRUCTURES = True # macro -class struct_rpc_set_guest_system_info_v03_00(Structure): - pass - -struct_rpc_set_guest_system_info_v03_00._pack_ = 1 # source:False -struct_rpc_set_guest_system_info_v03_00._fields_ = [ - ('vgxVersionMajorNum', ctypes.c_uint32), - ('vgxVersionMinorNum', ctypes.c_uint32), - ('guestDriverVersionBufferLength', ctypes.c_uint32), - ('guestVersionBufferLength', ctypes.c_uint32), - ('guestTitleBufferLength', ctypes.c_uint32), - ('guestClNum', ctypes.c_uint32), - ('guestDriverVersion', ctypes.c_char * 256), - ('guestVersion', ctypes.c_char * 256), - ('guestTitle', ctypes.c_char * 256), -] - -rpc_set_guest_system_info_v03_00 = struct_rpc_set_guest_system_info_v03_00 -rpc_set_guest_system_info_v = struct_rpc_set_guest_system_info_v03_00 -class struct_rpc_set_guest_system_info_ext_v15_02(Structure): - pass - -struct_rpc_set_guest_system_info_ext_v15_02._pack_ = 1 # source:False -struct_rpc_set_guest_system_info_ext_v15_02._fields_ = [ - ('guestDriverBranch', ctypes.c_char * 256), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), -] - -rpc_set_guest_system_info_ext_v15_02 = struct_rpc_set_guest_system_info_ext_v15_02 -class struct_rpc_set_guest_system_info_ext_v25_1B(Structure): - pass - -struct_rpc_set_guest_system_info_ext_v25_1B._pack_ = 1 # source:False -struct_rpc_set_guest_system_info_ext_v25_1B._fields_ = [ - ('guestDriverBranch', ctypes.c_char * 256), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('gridBuildCsp', ctypes.c_uint32), -] - -rpc_set_guest_system_info_ext_v25_1B = struct_rpc_set_guest_system_info_ext_v25_1B -rpc_set_guest_system_info_ext_v = struct_rpc_set_guest_system_info_ext_v25_1B -class struct_rpc_alloc_root_v07_00(Structure): - pass - -struct_rpc_alloc_root_v07_00._pack_ = 1 # source:False -struct_rpc_alloc_root_v07_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('processID', ctypes.c_uint32), - ('processName', ctypes.c_char * 100), -] - -rpc_alloc_root_v07_00 = struct_rpc_alloc_root_v07_00 -rpc_alloc_root_v = struct_rpc_alloc_root_v07_00 -class struct_rpc_alloc_memory_v13_01(Structure): - pass - -class struct_pte_desc(Structure): - pass - -class union_pte_desc_0(Union): - pass - -union_pte_desc_0._pack_ = 1 # source:False -union_pte_desc_0._fields_ = [ - ('pte', ctypes.c_uint64), - ('pde', ctypes.c_uint64), -] - -struct_pte_desc._pack_ = 1 # source:False -struct_pte_desc._fields_ = [ - ('idr', ctypes.c_uint32, 2), - ('reserved1', ctypes.c_uint32, 14), - ('length', ctypes.c_uint32, 16), - ('PADDING_0', ctypes.c_uint32, 32), - ('pte_pde', union_pte_desc_0 * 0), -] - -struct_rpc_alloc_memory_v13_01._pack_ = 1 # source:False -struct_rpc_alloc_memory_v13_01._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('pteAdjust', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('length', ctypes.c_uint64), - ('pageCount', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pteDesc', struct_pte_desc), -] - -rpc_alloc_memory_v13_01 = struct_rpc_alloc_memory_v13_01 -rpc_alloc_memory_v = struct_rpc_alloc_memory_v13_01 -class struct_rpc_alloc_channel_dma_v1F_04(Structure): - pass - -class struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04(Structure): - pass - -class struct_NV_MEMORY_DESC_PARAMS_v18_01(Structure): - pass - -struct_NV_MEMORY_DESC_PARAMS_v18_01._pack_ = 1 # source:False -struct_NV_MEMORY_DESC_PARAMS_v18_01._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cacheAttrib', ctypes.c_uint32), -] - -struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04._pack_ = 1 # source:False -struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04._fields_ = [ - ('hObjectError', ctypes.c_uint32), - ('hObjectBuffer', ctypes.c_uint32), - ('gpFifoOffset', ctypes.c_uint64), - ('gpFifoEntries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hContextShare', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('hUserdMemory', ctypes.c_uint32 * 1), - ('PADDING_0', ctypes.c_ubyte * 4), - ('userdOffset', ctypes.c_uint64 * 1), - ('engineType', ctypes.c_uint32), - ('hObjectEccError', ctypes.c_uint32), - ('instanceMem', struct_NV_MEMORY_DESC_PARAMS_v18_01), - ('ramfcMem', struct_NV_MEMORY_DESC_PARAMS_v18_01), - ('userdMem', struct_NV_MEMORY_DESC_PARAMS_v18_01), - ('mthdbufMem', struct_NV_MEMORY_DESC_PARAMS_v18_01), - ('hPhysChannelGroup', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('internalFlags', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('errorNotifierMem', struct_NV_MEMORY_DESC_PARAMS_v18_01), - ('eccErrorNotifierMem', struct_NV_MEMORY_DESC_PARAMS_v18_01), -] - -struct_rpc_alloc_channel_dma_v1F_04._pack_ = 1 # source:False -struct_rpc_alloc_channel_dma_v1F_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04), - ('chid', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -rpc_alloc_channel_dma_v1F_04 = struct_rpc_alloc_channel_dma_v1F_04 -rpc_alloc_channel_dma_v = struct_rpc_alloc_channel_dma_v1F_04 -class struct_rpc_alloc_object_v25_08(Structure): - pass - -class union_alloc_object_params_v25_08(Union): - pass - -class struct_alloc_object_NV50_TESLA_v03_00(Structure): - pass - -struct_alloc_object_NV50_TESLA_v03_00._pack_ = 1 # source:False -struct_alloc_object_NV50_TESLA_v03_00._fields_ = [ - ('version', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), -] - -class struct_alloc_object_GT212_DMA_COPY_v03_00(Structure): - pass - -struct_alloc_object_GT212_DMA_COPY_v03_00._pack_ = 1 # source:False -struct_alloc_object_GT212_DMA_COPY_v03_00._fields_ = [ - ('version', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -class struct_alloc_object_GF100_DISP_SW_v03_00(Structure): - pass - -struct_alloc_object_GF100_DISP_SW_v03_00._pack_ = 1 # source:False -struct_alloc_object_GF100_DISP_SW_v03_00._fields_ = [ - ('_reserved1', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_reserved2', ctypes.c_uint64), - ('logicalHeadId', ctypes.c_uint32), - ('displayMask', ctypes.c_uint32), - ('caps', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08(Structure): - pass - -struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08._pack_ = 1 # source:False -struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08._fields_ = [ - ('hObjectError', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('engineType', ctypes.c_uint32), -] - -class struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00(Structure): - pass - -struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00._pack_ = 1 # source:False -struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('subctxId', ctypes.c_uint32), -] - -class struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00(Structure): - pass - -struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00._pack_ = 1 # source:False -struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -class struct_alloc_object_FERMI_VASPACE_A_v03_00(Structure): - pass - -struct_alloc_object_FERMI_VASPACE_A_v03_00._pack_ = 1 # source:False -struct_alloc_object_FERMI_VASPACE_A_v03_00._fields_ = [ - ('index', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaSize', ctypes.c_uint64), - ('bigPageSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vaBase', ctypes.c_uint64), -] - -class struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00(Structure): - pass - -struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00._pack_ = 1 # source:False -struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), -] - -class struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00(Structure): - pass - -struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00._fields_ = [ - ('hDebuggerClient', ctypes.c_uint32), - ('hAppClient', ctypes.c_uint32), - ('hClass3dObject', ctypes.c_uint32), -] - -class struct_alloc_object_NVENC_SW_SESSION_v06_01(Structure): - pass - -struct_alloc_object_NVENC_SW_SESSION_v06_01._pack_ = 1 # source:False -struct_alloc_object_NVENC_SW_SESSION_v06_01._fields_ = [ - ('codecType', ctypes.c_uint32), - ('hResolution', ctypes.c_uint32), - ('vResolution', ctypes.c_uint32), -] - -class struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02(Structure): - pass - -struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02._pack_ = 1 # source:False -struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -class struct_alloc_object_NVFBC_SW_SESSION_v12_04(Structure): - pass - -struct_alloc_object_NVFBC_SW_SESSION_v12_04._pack_ = 1 # source:False -struct_alloc_object_NVFBC_SW_SESSION_v12_04._fields_ = [ - ('displayOrdinal', ctypes.c_uint32), - ('sessionType', ctypes.c_uint32), - ('sessionFlags', ctypes.c_uint32), - ('hMaxResolution', ctypes.c_uint32), - ('vMaxResolution', ctypes.c_uint32), -] - -class struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02(Structure): - pass - -struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02._pack_ = 1 # source:False -struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -class struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02(Structure): - pass - -struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02._pack_ = 1 # source:False -struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('hPeerSubDevice', ctypes.c_uint32), - ('subDevicePeerIdMask', ctypes.c_uint32), - ('peerSubDevicePeerIdMask', ctypes.c_uint32), - ('mailboxBar1Addr', ctypes.c_uint64), - ('mailboxTotalSize', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -class struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00(Structure): - pass - -struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00._pack_ = 1 # source:False -struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00._fields_ = [ - ('swizzId', ctypes.c_uint32), -] - -class struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03(Structure): - pass - -struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03._pack_ = 1 # source:False -struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03._fields_ = [ - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06(Structure): - pass - -struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06._pack_ = 1 # source:False -struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06._fields_ = [ - ('execPartitionId', ctypes.c_uint32), -] - -class struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15(Structure): - pass - -struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15._pack_ = 1 # source:False -struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('p2pToken', ctypes.c_uint64), -] - -class struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01(Structure): - pass - -struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01._pack_ = 1 # source:False -struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01._fields_ = [ - ('numHeads', ctypes.c_uint32), - ('numSors', ctypes.c_uint32), - ('numDsis', ctypes.c_uint32), -] - -class struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03(Structure): - pass - -struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03._pack_ = 1 # source:False -struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03._fields_ = [ - ('hSubDevice', ctypes.c_uint32), -] - -class struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03(Structure): - pass - -struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03._pack_ = 1 # source:False -struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hContextTarget', ctypes.c_uint32), -] - -class struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17(Structure): - pass - -struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17._pack_ = 1 # source:False -struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17._fields_ = [ - ('version', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), -] - -class struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B(Structure): - pass - -struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B._pack_ = 1 # source:False -struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), -] - -class struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C(Structure): - pass - -class struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C(Structure): - pass - -struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C._pack_ = 1 # source:False -struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C._fields_ = [ - ('offset', ctypes.c_uint64), - ('hVidMem', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C._pack_ = 1 # source:False -struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C._fields_ = [ - ('alignment', ctypes.c_uint64), - ('allocSize', ctypes.c_uint64), - ('pageSize', ctypes.c_uint32), - ('allocFlags', ctypes.c_uint32), - ('map', struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C), -] - -class struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00(Structure): - pass - -struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00._pack_ = 1 # source:False -struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), -] - -class struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08(Structure): - pass - -struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08._pack_ = 1 # source:False -struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08._fields_ = [ - ('reserved', ctypes.c_uint32), -] - -union_alloc_object_params_v25_08._pack_ = 1 # source:False -union_alloc_object_params_v25_08._fields_ = [ - ('param_NV50_TESLA', struct_alloc_object_NV50_TESLA_v03_00), - ('param_GT212_DMA_COPY', struct_alloc_object_GT212_DMA_COPY_v03_00), - ('param_GF100_DISP_SW', struct_alloc_object_GF100_DISP_SW_v03_00), - ('param_KEPLER_CHANNEL_GROUP_A', struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), - ('param_FERMI_CONTEXT_SHARE_A', struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), - ('param_NVD0B7_VIDEO_ENCODER', struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), - ('param_FERMI_VASPACE_A', struct_alloc_object_FERMI_VASPACE_A_v03_00), - ('param_NVB0B0_VIDEO_DECODER', struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00), - ('param_NV83DE_ALLOC_PARAMETERS', struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), - ('param_NVENC_SW_SESSION', struct_alloc_object_NVENC_SW_SESSION_v06_01), - ('param_NVC4B0_VIDEO_DECODER', struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02), - ('param_NVFBC_SW_SESSION', struct_alloc_object_NVFBC_SW_SESSION_v12_04), - ('param_NV_NVJPG_ALLOCATION_PARAMETERS', struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), - ('param_NV503B_ALLOC_PARAMETERS', struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), - ('param_NVC637_ALLOCATION_PARAMETERS', struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), - ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), - ('param_NVC638_ALLOCATION_PARAMETERS', struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), - ('param_NV503C_ALLOC_PARAMETERS', struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), - ('param_NVC670_ALLOCATION_PARAMETERS', struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), - ('param_NVB1CC_ALLOC_PARAMETERS', struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), - ('param_NVB2CC_ALLOC_PARAMETERS', struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), - ('param_NV_GR_ALLOCATION_PARAMETERS', struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17), - ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), - ('param_NV00F8_ALLOCATION_PARAMETERS', struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), - ('param_NVC9FA_VIDEO_OFA', struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00), - ('param_NV2081_ALLOC_PARAMETERS', struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), - ('PADDING_0', ctypes.c_ubyte * 36), -] - -struct_rpc_alloc_object_v25_08._pack_ = 1 # source:False -struct_rpc_alloc_object_v25_08._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('param_len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', union_alloc_object_params_v25_08), -] - -rpc_alloc_object_v25_08 = struct_rpc_alloc_object_v25_08 -class struct_rpc_alloc_object_v26_00(Structure): - pass - -class union_alloc_object_params_v26_00(Union): - pass - -union_alloc_object_params_v26_00._pack_ = 1 # source:False -union_alloc_object_params_v26_00._fields_ = [ - ('param_NV50_TESLA', struct_alloc_object_NV50_TESLA_v03_00), - ('param_GT212_DMA_COPY', struct_alloc_object_GT212_DMA_COPY_v03_00), - ('param_GF100_DISP_SW', struct_alloc_object_GF100_DISP_SW_v03_00), - ('param_KEPLER_CHANNEL_GROUP_A', struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), - ('param_FERMI_CONTEXT_SHARE_A', struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), - ('param_NVD0B7_VIDEO_ENCODER', struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), - ('param_FERMI_VASPACE_A', struct_alloc_object_FERMI_VASPACE_A_v03_00), - ('param_NVB0B0_VIDEO_DECODER', struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00), - ('param_NV83DE_ALLOC_PARAMETERS', struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), - ('param_NVENC_SW_SESSION', struct_alloc_object_NVENC_SW_SESSION_v06_01), - ('param_NVC4B0_VIDEO_DECODER', struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02), - ('param_NVFBC_SW_SESSION', struct_alloc_object_NVFBC_SW_SESSION_v12_04), - ('param_NV_NVJPG_ALLOCATION_PARAMETERS', struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), - ('param_NV503B_ALLOC_PARAMETERS', struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), - ('param_NVC637_ALLOCATION_PARAMETERS', struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), - ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), - ('param_NVC638_ALLOCATION_PARAMETERS', struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), - ('param_NV503C_ALLOC_PARAMETERS', struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), - ('param_NVC670_ALLOCATION_PARAMETERS', struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), - ('param_NVB1CC_ALLOC_PARAMETERS', struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), - ('param_NVB2CC_ALLOC_PARAMETERS', struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), - ('param_NV_GR_ALLOCATION_PARAMETERS', struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17), - ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), - ('param_NV00F8_ALLOCATION_PARAMETERS', struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), - ('param_NVC9FA_VIDEO_OFA', struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00), - ('param_NV2081_ALLOC_PARAMETERS', struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), - ('param_padding', ctypes.c_ubyte * 56), -] - -struct_rpc_alloc_object_v26_00._pack_ = 1 # source:False -struct_rpc_alloc_object_v26_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('param_len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', union_alloc_object_params_v26_00), -] - -rpc_alloc_object_v26_00 = struct_rpc_alloc_object_v26_00 -class struct_rpc_alloc_object_v27_00(Structure): - pass - -class union_alloc_object_params_v27_00(Union): - pass - -union_alloc_object_params_v27_00._pack_ = 1 # source:False -union_alloc_object_params_v27_00._fields_ = [ - ('param_NV50_TESLA', struct_alloc_object_NV50_TESLA_v03_00), - ('param_GT212_DMA_COPY', struct_alloc_object_GT212_DMA_COPY_v03_00), - ('param_GF100_DISP_SW', struct_alloc_object_GF100_DISP_SW_v03_00), - ('param_KEPLER_CHANNEL_GROUP_A', struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), - ('param_FERMI_CONTEXT_SHARE_A', struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), - ('param_NVD0B7_VIDEO_ENCODER', struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), - ('param_FERMI_VASPACE_A', struct_alloc_object_FERMI_VASPACE_A_v03_00), - ('param_NVB0B0_VIDEO_DECODER', struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00), - ('param_NV83DE_ALLOC_PARAMETERS', struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), - ('param_NVENC_SW_SESSION', struct_alloc_object_NVENC_SW_SESSION_v06_01), - ('param_NVC4B0_VIDEO_DECODER', struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02), - ('param_NVFBC_SW_SESSION', struct_alloc_object_NVFBC_SW_SESSION_v12_04), - ('param_NV_NVJPG_ALLOCATION_PARAMETERS', struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), - ('param_NV503B_ALLOC_PARAMETERS', struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), - ('param_NVC637_ALLOCATION_PARAMETERS', struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), - ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), - ('param_NVC638_ALLOCATION_PARAMETERS', struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), - ('param_NV503C_ALLOC_PARAMETERS', struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), - ('param_NVC670_ALLOCATION_PARAMETERS', struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), - ('param_NVB1CC_ALLOC_PARAMETERS', struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), - ('param_NVB2CC_ALLOC_PARAMETERS', struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), - ('param_NV_GR_ALLOCATION_PARAMETERS', struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17), - ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), - ('param_NV00F8_ALLOCATION_PARAMETERS', struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), - ('param_NVC9FA_VIDEO_OFA', struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00), - ('param_NV2081_ALLOC_PARAMETERS', struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), - ('param_padding', ctypes.c_ubyte * 56), -] - -struct_rpc_alloc_object_v27_00._pack_ = 1 # source:False -struct_rpc_alloc_object_v27_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('param_len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', union_alloc_object_params_v27_00), -] - -rpc_alloc_object_v27_00 = struct_rpc_alloc_object_v27_00 -class struct_rpc_alloc_object_v29_06(Structure): - pass - -class union_alloc_object_params_v29_06(Union): - pass - -class struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06(Structure): - pass - -struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06._pack_ = 1 # source:False -struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), -] - -union_alloc_object_params_v29_06._pack_ = 1 # source:False -union_alloc_object_params_v29_06._fields_ = [ - ('param_NV50_TESLA', struct_alloc_object_NV50_TESLA_v03_00), - ('param_GT212_DMA_COPY', struct_alloc_object_GT212_DMA_COPY_v03_00), - ('param_GF100_DISP_SW', struct_alloc_object_GF100_DISP_SW_v03_00), - ('param_KEPLER_CHANNEL_GROUP_A', struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08), - ('param_FERMI_CONTEXT_SHARE_A', struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00), - ('param_NVD0B7_VIDEO_ENCODER', struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00), - ('param_FERMI_VASPACE_A', struct_alloc_object_FERMI_VASPACE_A_v03_00), - ('param_NVB0B0_VIDEO_DECODER', struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00), - ('param_NV83DE_ALLOC_PARAMETERS', struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00), - ('param_NVENC_SW_SESSION', struct_alloc_object_NVENC_SW_SESSION_v06_01), - ('param_NVC4B0_VIDEO_DECODER', struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02), - ('param_NVFBC_SW_SESSION', struct_alloc_object_NVFBC_SW_SESSION_v12_04), - ('param_NV_NVJPG_ALLOCATION_PARAMETERS', struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02), - ('param_NV503B_ALLOC_PARAMETERS', struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02), - ('param_NVC637_ALLOCATION_PARAMETERS', struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00), - ('param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS', struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03), - ('param_NVC638_ALLOCATION_PARAMETERS', struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06), - ('param_NV503C_ALLOC_PARAMETERS', struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15), - ('param_NVC670_ALLOCATION_PARAMETERS', struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01), - ('param_NVB1CC_ALLOC_PARAMETERS', struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03), - ('param_NVB2CC_ALLOC_PARAMETERS', struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03), - ('param_NV_GR_ALLOCATION_PARAMETERS', struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17), - ('param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS', struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B), - ('param_NV00F8_ALLOCATION_PARAMETERS', struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C), - ('param_NVC9FA_VIDEO_OFA', struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06), - ('param_NV2081_ALLOC_PARAMETERS', struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08), - ('param_padding', ctypes.c_ubyte * 56), -] - -struct_rpc_alloc_object_v29_06._pack_ = 1 # source:False -struct_rpc_alloc_object_v29_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('param_len', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', union_alloc_object_params_v29_06), -] - -rpc_alloc_object_v29_06 = struct_rpc_alloc_object_v29_06 -rpc_alloc_object_v = struct_rpc_alloc_object_v29_06 -class struct_rpc_free_v03_00(Structure): - pass - -class struct_NVOS00_PARAMETERS_v03_00(Structure): - pass - -struct_NVOS00_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NVOS00_PARAMETERS_v03_00._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectOld', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -struct_rpc_free_v03_00._pack_ = 1 # source:False -struct_rpc_free_v03_00._fields_ = [ - ('params', struct_NVOS00_PARAMETERS_v03_00), -] - -rpc_free_v03_00 = struct_rpc_free_v03_00 -rpc_free_v = struct_rpc_free_v03_00 -class struct_rpc_log_v03_00(Structure): - pass - -struct_rpc_log_v03_00._pack_ = 1 # source:False -struct_rpc_log_v03_00._fields_ = [ - ('level', ctypes.c_uint32), - ('log_len', ctypes.c_uint32), - ('log_msg', ctypes.c_char * 0), -] - -rpc_log_v03_00 = struct_rpc_log_v03_00 -rpc_log_v = struct_rpc_log_v03_00 -class struct_rpc_map_memory_dma_v03_00(Structure): - pass - -class struct_NVOS46_PARAMETERS_v03_00(Structure): - pass - -struct_NVOS46_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NVOS46_PARAMETERS_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hDma', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dmaOffset', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -struct_rpc_map_memory_dma_v03_00._pack_ = 1 # source:False -struct_rpc_map_memory_dma_v03_00._fields_ = [ - ('params', struct_NVOS46_PARAMETERS_v03_00), -] - -rpc_map_memory_dma_v03_00 = struct_rpc_map_memory_dma_v03_00 -rpc_map_memory_dma_v = struct_rpc_map_memory_dma_v03_00 -class struct_rpc_unmap_memory_dma_v03_00(Structure): - pass - -class struct_NVOS47_PARAMETERS_v03_00(Structure): - pass - -struct_NVOS47_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NVOS47_PARAMETERS_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hDma', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dmaOffset', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -struct_rpc_unmap_memory_dma_v03_00._pack_ = 1 # source:False -struct_rpc_unmap_memory_dma_v03_00._fields_ = [ - ('params', struct_NVOS47_PARAMETERS_v03_00), -] - -rpc_unmap_memory_dma_v03_00 = struct_rpc_unmap_memory_dma_v03_00 -rpc_unmap_memory_dma_v = struct_rpc_unmap_memory_dma_v03_00 -class struct_rpc_alloc_subdevice_v08_01(Structure): - pass - -class struct_NVOS21_PARAMETERS_v03_00(Structure): - pass - -struct_NVOS21_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NVOS21_PARAMETERS_v03_00._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('pAllocParms', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_rpc_alloc_subdevice_v08_01._pack_ = 1 # source:False -struct_rpc_alloc_subdevice_v08_01._fields_ = [ - ('subDeviceInst', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', struct_NVOS21_PARAMETERS_v03_00), -] - -rpc_alloc_subdevice_v08_01 = struct_rpc_alloc_subdevice_v08_01 -rpc_alloc_subdevice_v = struct_rpc_alloc_subdevice_v08_01 -class struct_rpc_dup_object_v03_00(Structure): - pass - -class struct_NVOS55_PARAMETERS_v03_00(Structure): - pass - -struct_NVOS55_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NVOS55_PARAMETERS_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClientSrc', ctypes.c_uint32), - ('hObjectSrc', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -struct_rpc_dup_object_v03_00._pack_ = 1 # source:False -struct_rpc_dup_object_v03_00._fields_ = [ - ('params', struct_NVOS55_PARAMETERS_v03_00), -] - -rpc_dup_object_v03_00 = struct_rpc_dup_object_v03_00 -rpc_dup_object_v = struct_rpc_dup_object_v03_00 -class struct_rpc_idle_channels_v03_00(Structure): - pass - -class struct_idle_channel_list_v03_00(Structure): - pass - -struct_idle_channel_list_v03_00._pack_ = 1 # source:False -struct_idle_channel_list_v03_00._fields_ = [ - ('phClient', ctypes.c_uint32), - ('phDevice', ctypes.c_uint32), - ('phChannel', ctypes.c_uint32), -] - -struct_rpc_idle_channels_v03_00._pack_ = 1 # source:False -struct_rpc_idle_channels_v03_00._fields_ = [ - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), - ('nchannels', ctypes.c_uint32), - ('channel_list', struct_idle_channel_list_v03_00 * 0), -] - -rpc_idle_channels_v03_00 = struct_rpc_idle_channels_v03_00 -rpc_idle_channels_v = struct_rpc_idle_channels_v03_00 -class struct_rpc_alloc_event_v03_00(Structure): - pass - -struct_rpc_alloc_event_v03_00._pack_ = 1 # source:False -struct_rpc_alloc_event_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParentClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hEvent', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('notifyIndex', ctypes.c_uint32), -] - -rpc_alloc_event_v03_00 = struct_rpc_alloc_event_v03_00 -rpc_alloc_event_v = struct_rpc_alloc_event_v03_00 -class struct_rpc_rm_api_control_v25_0D(Structure): - pass - -class struct_NVOS54_PARAMETERS_v03_00(Structure): - pass - -struct_NVOS54_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NVOS54_PARAMETERS_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -struct_rpc_rm_api_control_v25_0D._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_0D._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_0D = struct_rpc_rm_api_control_v25_0D -class struct_rpc_rm_api_control_v25_0F(Structure): - pass - -struct_rpc_rm_api_control_v25_0F._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_0F._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_0F = struct_rpc_rm_api_control_v25_0F -class struct_rpc_rm_api_control_v25_10(Structure): - pass - -struct_rpc_rm_api_control_v25_10._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_10._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_10 = struct_rpc_rm_api_control_v25_10 -class struct_rpc_rm_api_control_v25_14(Structure): - pass - -struct_rpc_rm_api_control_v25_14._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_14._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_14 = struct_rpc_rm_api_control_v25_14 -class struct_rpc_rm_api_control_v25_15(Structure): - pass - -struct_rpc_rm_api_control_v25_15._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_15._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_15 = struct_rpc_rm_api_control_v25_15 -class struct_rpc_rm_api_control_v25_16(Structure): - pass - -struct_rpc_rm_api_control_v25_16._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_16._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_16 = struct_rpc_rm_api_control_v25_16 -class struct_rpc_rm_api_control_v25_17(Structure): - pass - -struct_rpc_rm_api_control_v25_17._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_17._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_17 = struct_rpc_rm_api_control_v25_17 -class struct_rpc_rm_api_control_v25_18(Structure): - pass - -struct_rpc_rm_api_control_v25_18._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_18._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_18 = struct_rpc_rm_api_control_v25_18 -class struct_rpc_rm_api_control_v25_19(Structure): - pass - -struct_rpc_rm_api_control_v25_19._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_19._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_19 = struct_rpc_rm_api_control_v25_19 -class struct_rpc_rm_api_control_v25_1A(Structure): - pass - -struct_rpc_rm_api_control_v25_1A._pack_ = 1 # source:False -struct_rpc_rm_api_control_v25_1A._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v25_1A = struct_rpc_rm_api_control_v25_1A -class struct_rpc_rm_api_control_v27_03(Structure): - pass - -struct_rpc_rm_api_control_v27_03._pack_ = 1 # source:False -struct_rpc_rm_api_control_v27_03._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v27_03 = struct_rpc_rm_api_control_v27_03 -class struct_rpc_rm_api_control_v29_04(Structure): - pass - -struct_rpc_rm_api_control_v29_04._pack_ = 1 # source:False -struct_rpc_rm_api_control_v29_04._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v29_04 = struct_rpc_rm_api_control_v29_04 -class struct_rpc_rm_api_control_v29_09(Structure): - pass - -struct_rpc_rm_api_control_v29_09._pack_ = 1 # source:False -struct_rpc_rm_api_control_v29_09._fields_ = [ - ('params', struct_NVOS54_PARAMETERS_v03_00), - ('rm_api_params', ctypes.POINTER(None)), -] - -rpc_rm_api_control_v29_09 = struct_rpc_rm_api_control_v29_09 -rpc_rm_api_control_v = struct_rpc_rm_api_control_v29_09 -class struct_rpc_alloc_share_device_v03_00(Structure): - pass - -class struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00(Structure): - pass - -struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00._pack_ = 1 # source:False -struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00._fields_ = [ - ('szName', ctypes.POINTER(None)), - ('hClientShare', ctypes.c_uint32), - ('hTargetClient', ctypes.c_uint32), - ('hTargetDevice', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaSpaceSize', ctypes.c_uint64), - ('vaMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vaBase', ctypes.c_uint64), -] - -struct_rpc_alloc_share_device_v03_00._pack_ = 1 # source:False -struct_rpc_alloc_share_device_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00), -] - -rpc_alloc_share_device_v03_00 = struct_rpc_alloc_share_device_v03_00 -rpc_alloc_share_device_v = struct_rpc_alloc_share_device_v03_00 -class struct_rpc_get_engine_utilization_v1F_0E(Structure): - pass - -class union_vgpuGetEngineUtilization_data_v1F_0E(Union): - pass - -class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00(Structure): - pass - - -# values for enumeration 'NV2080_CTRL_CMD_PERF_VID_ENG' -NV2080_CTRL_CMD_PERF_VID_ENG__enumvalues = { - 1: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', - 2: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', - 3: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', - 4: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', -} -NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1 -NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2 -NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3 -NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4 -NV2080_CTRL_CMD_PERF_VID_ENG = ctypes.c_uint32 # enum -struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00._fields_ = [ - ('engineType', NV2080_CTRL_CMD_PERF_VID_ENG), - ('clkPercentBusy', ctypes.c_uint32), - ('samplingPeriodUs', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('vmPid', ctypes.c_uint32), - ('state', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('vmPid', ctypes.c_uint32), - ('newState', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('vmPid', ctypes.c_uint32), - ('passIndex', ctypes.c_uint32), - ('pidCount', ctypes.c_uint32), - ('pidTable', ctypes.c_uint32 * 1000), -] - -class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('subPid', ctypes.c_uint32), - ('gpuUtil', ctypes.c_uint32), - ('fbUtil', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('maxFbUsage', ctypes.c_uint64), - ('startTime', ctypes.c_uint64), - ('endTime', ctypes.c_uint64), -] - -class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('vmPid', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E(Structure): - pass - -class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00(Structure): - pass - -struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00._fields_ = [ - ('util', ctypes.c_uint32), - ('procId', ctypes.c_uint32), - ('subProcessID', ctypes.c_uint32), -] - -struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E._fields_ = [ - ('timeStamp', ctypes.c_uint64), - ('fb', struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), - ('gr', struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), - ('nvenc', struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), - ('nvdec', struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00), -] - -union_vgpuGetEngineUtilization_data_v1F_0E._pack_ = 1 # source:False -union_vgpuGetEngineUtilization_data_v1F_0E._fields_ = [ - ('vidPerfmonSample', struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00), - ('getAccountingState', struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C), - ('setAccountingState', struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C), - ('getAccountingPidList', struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C), - ('procAccountingInfo', struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C), - ('clearAccountingInfo', struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C), - ('gpumonPerfmonsampleV2', struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E * 72), -] - -struct_rpc_get_engine_utilization_v1F_0E._pack_ = 1 # source:False -struct_rpc_get_engine_utilization_v1F_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', union_vgpuGetEngineUtilization_data_v1F_0E), -] - -rpc_get_engine_utilization_v1F_0E = struct_rpc_get_engine_utilization_v1F_0E -rpc_get_engine_utilization_v = struct_rpc_get_engine_utilization_v1F_0E -class struct_rpc_perf_get_level_info_v03_00(Structure): - pass - -struct_rpc_perf_get_level_info_v03_00._pack_ = 1 # source:False -struct_rpc_perf_get_level_info_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('perfGetClkInfoListSize', ctypes.c_uint32), - ('param_size', ctypes.c_uint32), - ('params', ctypes.c_uint32 * 0), -] - -rpc_perf_get_level_info_v03_00 = struct_rpc_perf_get_level_info_v03_00 -rpc_perf_get_level_info_v = struct_rpc_perf_get_level_info_v03_00 -class struct_rpc_set_surface_properties_v07_07(Structure): - pass - -class struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07(Structure): - pass - -struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07._pack_ = 1 # source:False -struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07._fields_ = [ - ('headIndex', ctypes.c_uint32), - ('isPrimary', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('surfaceType', ctypes.c_uint32), - ('surfaceBlockHeight', ctypes.c_uint32), - ('surfacePitch', ctypes.c_uint32), - ('surfaceFormat', ctypes.c_uint32), - ('surfaceWidth', ctypes.c_uint32), - ('surfaceHeight', ctypes.c_uint32), - ('rectX', ctypes.c_uint32), - ('rectY', ctypes.c_uint32), - ('rectWidth', ctypes.c_uint32), - ('rectHeight', ctypes.c_uint32), - ('surfaceSize', ctypes.c_uint32), - ('surfaceKind', ctypes.c_uint32), - ('hHwResDevice', ctypes.c_uint32), - ('hHwResHandle', ctypes.c_uint32), - ('effectiveFbPageSize', ctypes.c_uint32), -] - -struct_rpc_set_surface_properties_v07_07._pack_ = 1 # source:False -struct_rpc_set_surface_properties_v07_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('params', struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07), -] - -rpc_set_surface_properties_v07_07 = struct_rpc_set_surface_properties_v07_07 -rpc_set_surface_properties_v = struct_rpc_set_surface_properties_v07_07 -class struct_rpc_cleanup_surface_v03_00(Structure): - pass - -class struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00(Structure): - pass - -struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00._pack_ = 1 # source:False -struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00._fields_ = [ - ('headIndex', ctypes.c_uint32), - ('blankingEnabled', ctypes.c_uint32), -] - -struct_rpc_cleanup_surface_v03_00._pack_ = 1 # source:False -struct_rpc_cleanup_surface_v03_00._fields_ = [ - ('params', struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00), -] - -rpc_cleanup_surface_v03_00 = struct_rpc_cleanup_surface_v03_00 -rpc_cleanup_surface_v = struct_rpc_cleanup_surface_v03_00 -class struct_rpc_unloading_guest_driver_v1F_07(Structure): - pass - -struct_rpc_unloading_guest_driver_v1F_07._pack_ = 1 # source:False -struct_rpc_unloading_guest_driver_v1F_07._fields_ = [ - ('bInPMTransition', ctypes.c_ubyte), - ('bGc6Entering', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('newLevel', ctypes.c_uint32), -] - -rpc_unloading_guest_driver_v1F_07 = struct_rpc_unloading_guest_driver_v1F_07 -rpc_unloading_guest_driver_v = struct_rpc_unloading_guest_driver_v1F_07 -class struct_rpc_gpu_exec_reg_ops_v12_01(Structure): - pass - -class struct_gpu_exec_reg_ops_v12_01(Structure): - pass - -class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01(Structure): - pass - -class struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01(Structure): - pass - -struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('route', ctypes.c_uint64), -] - -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('reserved00', ctypes.c_uint32 * 3), - ('regOpCount', ctypes.c_uint32), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), - ('regOps', ctypes.POINTER(None)), -] - -class struct_NV2080_CTRL_GPU_REG_OP_v03_00(Structure): - pass - -struct_NV2080_CTRL_GPU_REG_OP_v03_00._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_REG_OP_v03_00._fields_ = [ - ('regOp', ctypes.c_ubyte), - ('regType', ctypes.c_ubyte), - ('regStatus', ctypes.c_ubyte), - ('regQuad', ctypes.c_ubyte), - ('regGroupMask', ctypes.c_uint32), - ('regSubGroupMask', ctypes.c_uint32), - ('regOffset', ctypes.c_uint32), - ('regValueHi', ctypes.c_uint32), - ('regValueLo', ctypes.c_uint32), - ('regAndNMaskHi', ctypes.c_uint32), - ('regAndNMaskLo', ctypes.c_uint32), -] - -struct_gpu_exec_reg_ops_v12_01._pack_ = 1 # source:False -struct_gpu_exec_reg_ops_v12_01._fields_ = [ - ('reg_op_params', struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01), - ('operations', struct_NV2080_CTRL_GPU_REG_OP_v03_00 * 0), -] - -struct_rpc_gpu_exec_reg_ops_v12_01._pack_ = 1 # source:False -struct_rpc_gpu_exec_reg_ops_v12_01._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_gpu_exec_reg_ops_v12_01), -] - -rpc_gpu_exec_reg_ops_v12_01 = struct_rpc_gpu_exec_reg_ops_v12_01 -rpc_gpu_exec_reg_ops_v = struct_rpc_gpu_exec_reg_ops_v12_01 -class struct_rpc_get_static_data_v25_0E(Structure): - pass - -struct_rpc_get_static_data_v25_0E._pack_ = 1 # source:False -struct_rpc_get_static_data_v25_0E._fields_ = [ - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('payload', ctypes.c_ubyte * 0), -] - -rpc_get_static_data_v25_0E = struct_rpc_get_static_data_v25_0E -class struct_rpc_get_static_data_v27_01(Structure): - pass - -struct_rpc_get_static_data_v27_01._pack_ = 1 # source:False -struct_rpc_get_static_data_v27_01._fields_ = [ - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('payload', ctypes.c_ubyte * 0), -] - -rpc_get_static_data_v27_01 = struct_rpc_get_static_data_v27_01 -rpc_get_static_data_v = struct_rpc_get_static_data_v27_01 -class struct_rpc_get_consolidated_gr_static_info_v1B_04(Structure): - pass - -struct_rpc_get_consolidated_gr_static_info_v1B_04._pack_ = 1 # source:False -struct_rpc_get_consolidated_gr_static_info_v1B_04._fields_ = [ - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('payload', ctypes.c_ubyte * 0), -] - -rpc_get_consolidated_gr_static_info_v1B_04 = struct_rpc_get_consolidated_gr_static_info_v1B_04 -rpc_get_consolidated_gr_static_info_v = struct_rpc_get_consolidated_gr_static_info_v1B_04 -class struct_rpc_set_page_directory_v1E_05(Structure): - pass - -class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('chId', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pasid', ctypes.c_uint32), -] - -struct_rpc_set_page_directory_v1E_05._pack_ = 1 # source:False -struct_rpc_set_page_directory_v1E_05._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('pasid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('params', struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05), -] - -rpc_set_page_directory_v1E_05 = struct_rpc_set_page_directory_v1E_05 -rpc_set_page_directory_v = struct_rpc_set_page_directory_v1E_05 -class struct_rpc_unset_page_directory_v1E_05(Structure): - pass - -class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05(Structure): - pass - -struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), -] - -struct_rpc_unset_page_directory_v1E_05._pack_ = 1 # source:False -struct_rpc_unset_page_directory_v1E_05._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('params', struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05), -] - -rpc_unset_page_directory_v1E_05 = struct_rpc_unset_page_directory_v1E_05 -rpc_unset_page_directory_v = struct_rpc_unset_page_directory_v1E_05 -class struct_rpc_get_gsp_static_info_v14_00(Structure): - pass - -struct_rpc_get_gsp_static_info_v14_00._pack_ = 1 # source:False -struct_rpc_get_gsp_static_info_v14_00._fields_ = [ - ('data', ctypes.c_uint32), -] - -rpc_get_gsp_static_info_v14_00 = struct_rpc_get_gsp_static_info_v14_00 -rpc_get_gsp_static_info_v = struct_rpc_get_gsp_static_info_v14_00 -class struct_rpc_update_bar_pde_v15_00(Structure): - pass - -class struct_UpdateBarPde_v15_00(Structure): - pass - -struct_UpdateBarPde_v15_00._pack_ = 1 # source:False -struct_UpdateBarPde_v15_00._fields_ = [ - ('barType', NV_RPC_UPDATE_PDE_BAR_TYPE), - ('PADDING_0', ctypes.c_ubyte * 4), - ('entryValue', ctypes.c_uint64), - ('entryLevelShift', ctypes.c_uint64), -] - -struct_rpc_update_bar_pde_v15_00._pack_ = 1 # source:False -struct_rpc_update_bar_pde_v15_00._fields_ = [ - ('info', struct_UpdateBarPde_v15_00), -] - -rpc_update_bar_pde_v15_00 = struct_rpc_update_bar_pde_v15_00 -rpc_update_bar_pde_v = struct_rpc_update_bar_pde_v15_00 -class struct_rpc_get_encoder_capacity_v07_00(Structure): - pass - -struct_rpc_get_encoder_capacity_v07_00._pack_ = 1 # source:False -struct_rpc_get_encoder_capacity_v07_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('encoderCapacity', ctypes.c_uint32), -] - -rpc_get_encoder_capacity_v07_00 = struct_rpc_get_encoder_capacity_v07_00 -rpc_get_encoder_capacity_v = struct_rpc_get_encoder_capacity_v07_00 -class struct_rpc_vgpu_pf_reg_read32_v15_00(Structure): - pass - -struct_rpc_vgpu_pf_reg_read32_v15_00._pack_ = 1 # source:False -struct_rpc_vgpu_pf_reg_read32_v15_00._fields_ = [ - ('address', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('grEngId', ctypes.c_uint32), -] - -rpc_vgpu_pf_reg_read32_v15_00 = struct_rpc_vgpu_pf_reg_read32_v15_00 -rpc_vgpu_pf_reg_read32_v = struct_rpc_vgpu_pf_reg_read32_v15_00 -class struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08(Structure): - pass - -class struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02(Structure): - pass - -struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02._pack_ = 1 # source:False -struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02._fields_ = [ - ('fbUsed', ctypes.c_uint64), -] - -struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08._pack_ = 1 # source:False -struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08._fields_ = [ - ('setFbUsage', struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02), -] - -rpc_ctrl_set_vgpu_fb_usage_v1A_08 = struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08 -rpc_ctrl_set_vgpu_fb_usage_v = struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08 -class struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09(Structure): - pass - -class struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(Structure): - pass - -struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01._pack_ = 1 # source:False -struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01._fields_ = [ - ('hResolution', ctypes.c_uint32), - ('vResolution', ctypes.c_uint32), - ('averageEncodeLatency', ctypes.c_uint32), - ('averageEncodeFps', ctypes.c_uint32), - ('timestampBufferSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timestampBuffer', ctypes.POINTER(None)), -] - -struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('nvencSessionUpdate', struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01), -] - -rpc_ctrl_nvenc_sw_session_update_info_v1A_09 = struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 -rpc_ctrl_nvenc_sw_session_update_info_v = struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 -class struct_rpc_ctrl_reset_channel_v1A_09(Structure): - pass - -class struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(Structure): - pass - -struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01._pack_ = 1 # source:False -struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01._fields_ = [ - ('engineID', ctypes.c_uint32), - ('subdeviceInstance', ctypes.c_uint32), - ('resetReason', ctypes.c_uint32), -] - -struct_rpc_ctrl_reset_channel_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_reset_channel_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('resetChannel', struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01), -] - -rpc_ctrl_reset_channel_v1A_09 = struct_rpc_ctrl_reset_channel_v1A_09 -rpc_ctrl_reset_channel_v = struct_rpc_ctrl_reset_channel_v1A_09 -class struct_rpc_ctrl_reset_isolated_channel_v1A_09(Structure): - pass - -class struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(Structure): - pass - -struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00._fields_ = [ - ('exceptType', ctypes.c_uint32), - ('engineID', ctypes.c_uint32), -] - -struct_rpc_ctrl_reset_isolated_channel_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_reset_isolated_channel_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('resetIsolatedChannel', struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00), -] - -rpc_ctrl_reset_isolated_channel_v1A_09 = struct_rpc_ctrl_reset_isolated_channel_v1A_09 -rpc_ctrl_reset_isolated_channel_v = struct_rpc_ctrl_reset_isolated_channel_v1A_09 -class struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09(Structure): - pass - -class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09._fields_ = [ - ('faultType', ctypes.c_uint32), -] - -struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('handleVfPriFault', struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09), -] - -rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 = struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 -rpc_ctrl_gpu_handle_vf_pri_fault_v = struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 -class struct_rpc_ctrl_perf_boost_v1A_09(Structure): - pass - -class struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(Structure): - pass - -struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00._fields_ = [ - ('flags', ctypes.c_uint32), - ('duration', ctypes.c_uint32), -] - -struct_rpc_ctrl_perf_boost_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_perf_boost_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('perfBoost', struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00), -] - -rpc_ctrl_perf_boost_v1A_09 = struct_rpc_ctrl_perf_boost_v1A_09 -rpc_ctrl_perf_boost_v = struct_rpc_ctrl_perf_boost_v1A_09 -class struct_rpc_ctrl_get_zbc_clear_table_v1A_09(Structure): - pass - -class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(Structure): - pass - -class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00(Structure): - pass - -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00._pack_ = 1 # source:False -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00._fields_ = [ - ('colorFB', ctypes.c_uint32 * 4), - ('colorDS', ctypes.c_uint32 * 4), - ('depth', ctypes.c_uint32), - ('stencil', ctypes.c_uint32), -] - -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00._pack_ = 1 # source:False -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00._fields_ = [ - ('value', struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00), - ('indexSize', ctypes.c_uint32), - ('indexUsed', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('valType', ctypes.c_uint32), -] - -struct_rpc_ctrl_get_zbc_clear_table_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_get_zbc_clear_table_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('getZbcClearTable', struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00), -] - -rpc_ctrl_get_zbc_clear_table_v1A_09 = struct_rpc_ctrl_get_zbc_clear_table_v1A_09 -rpc_ctrl_get_zbc_clear_table_v = struct_rpc_ctrl_get_zbc_clear_table_v1A_09 -class struct_rpc_ctrl_set_zbc_color_clear_v1A_09(Structure): - pass - -class struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(Structure): - pass - -struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00._fields_ = [ - ('colorFB', ctypes.c_uint32 * 4), - ('colorDS', ctypes.c_uint32 * 4), - ('format', ctypes.c_uint32), -] - -struct_rpc_ctrl_set_zbc_color_clear_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_set_zbc_color_clear_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('setZbcColorClr', struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00), -] - -rpc_ctrl_set_zbc_color_clear_v1A_09 = struct_rpc_ctrl_set_zbc_color_clear_v1A_09 -rpc_ctrl_set_zbc_color_clear_v = struct_rpc_ctrl_set_zbc_color_clear_v1A_09 -class struct_rpc_ctrl_set_zbc_depth_clear_v1A_09(Structure): - pass - -class struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(Structure): - pass - -struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00._fields_ = [ - ('depth', ctypes.c_uint32), - ('format', ctypes.c_uint32), -] - -struct_rpc_ctrl_set_zbc_depth_clear_v1A_09._pack_ = 1 # source:False -struct_rpc_ctrl_set_zbc_depth_clear_v1A_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('setZbcDepthClr', struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00), -] - -rpc_ctrl_set_zbc_depth_clear_v1A_09 = struct_rpc_ctrl_set_zbc_depth_clear_v1A_09 -rpc_ctrl_set_zbc_depth_clear_v = struct_rpc_ctrl_set_zbc_depth_clear_v1A_09 -class struct_rpc_ctrl_set_zbc_stencil_clear_v27_06(Structure): - pass - -class struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06(Structure): - pass - -struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06._pack_ = 1 # source:False -struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06._fields_ = [ - ('stencil', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('bSkipL2Table', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_rpc_ctrl_set_zbc_stencil_clear_v27_06._pack_ = 1 # source:False -struct_rpc_ctrl_set_zbc_stencil_clear_v27_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('setZbcStencilClr', struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06), -] - -rpc_ctrl_set_zbc_stencil_clear_v27_06 = struct_rpc_ctrl_set_zbc_stencil_clear_v27_06 -rpc_ctrl_set_zbc_stencil_clear_v = struct_rpc_ctrl_set_zbc_stencil_clear_v27_06 -class struct_rpc_ctrl_gpfifo_schedule_v1A_0A(Structure): - pass - -class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(Structure): - pass - -struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00._pack_ = 1 # source:False -struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -struct_rpc_ctrl_gpfifo_schedule_v1A_0A._pack_ = 1 # source:False -struct_rpc_ctrl_gpfifo_schedule_v1A_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('gpfifoSchedule', struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_gpfifo_schedule_v1A_0A = struct_rpc_ctrl_gpfifo_schedule_v1A_0A -rpc_ctrl_gpfifo_schedule_v = struct_rpc_ctrl_gpfifo_schedule_v1A_0A -class struct_rpc_ctrl_set_timeslice_v1A_0A(Structure): - pass - -class struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(Structure): - pass - -struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00._pack_ = 1 # source:False -struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00._fields_ = [ - ('timesliceUs', ctypes.c_uint64), -] - -struct_rpc_ctrl_set_timeslice_v1A_0A._pack_ = 1 # source:False -struct_rpc_ctrl_set_timeslice_v1A_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('setTimeSlice', struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00), -] - -rpc_ctrl_set_timeslice_v1A_0A = struct_rpc_ctrl_set_timeslice_v1A_0A -rpc_ctrl_set_timeslice_v = struct_rpc_ctrl_set_timeslice_v1A_0A -class struct_rpc_ctrl_fifo_disable_channels_v1A_0A(Structure): - pass - -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00._fields_ = [ - ('bDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numChannels', ctypes.c_uint32), - ('bOnlyDisableScheduling', ctypes.c_ubyte), - ('bRewindGpPut', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 6), - ('pRunlistPreemptEvent', ctypes.POINTER(None)), - ('hClientList', ctypes.c_uint32 * 64), - ('hChannelList', ctypes.c_uint32 * 64), -] - -struct_rpc_ctrl_fifo_disable_channels_v1A_0A._pack_ = 1 # source:False -struct_rpc_ctrl_fifo_disable_channels_v1A_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('fifoDisableChannels', struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00), -] - -rpc_ctrl_fifo_disable_channels_v1A_0A = struct_rpc_ctrl_fifo_disable_channels_v1A_0A -rpc_ctrl_fifo_disable_channels_v = struct_rpc_ctrl_fifo_disable_channels_v1A_0A -class struct_rpc_ctrl_preempt_v1A_0A(Structure): - pass - -class struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(Structure): - pass - -struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A._pack_ = 1 # source:False -struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A._fields_ = [ - ('bWait', ctypes.c_ubyte), - ('bManualTimeout', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('timeoutUs', ctypes.c_uint32), -] - -struct_rpc_ctrl_preempt_v1A_0A._pack_ = 1 # source:False -struct_rpc_ctrl_preempt_v1A_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmdPreempt', struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A), -] - -rpc_ctrl_preempt_v1A_0A = struct_rpc_ctrl_preempt_v1A_0A -rpc_ctrl_preempt_v = struct_rpc_ctrl_preempt_v1A_0A -class struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A(Structure): - pass - -class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(Structure): - pass - -struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02._pack_ = 1 # source:False -struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02._fields_ = [ - ('tsgInterleaveLevel', ctypes.c_uint32), -] - -struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A._pack_ = 1 # source:False -struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('interleaveLevelTSG', struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02), -] - -rpc_ctrl_set_tsg_interleave_level_v1A_0A = struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A -rpc_ctrl_set_tsg_interleave_level_v = struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A -class struct_rpc_ctrl_set_channel_interleave_level_v1A_0A(Structure): - pass - -class struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(Structure): - pass - -struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02._pack_ = 1 # source:False -struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02._fields_ = [ - ('channelInterleaveLevel', ctypes.c_uint32), -] - -struct_rpc_ctrl_set_channel_interleave_level_v1A_0A._pack_ = 1 # source:False -struct_rpc_ctrl_set_channel_interleave_level_v1A_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('interleaveLevelChannel', struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02), -] - -rpc_ctrl_set_channel_interleave_level_v1A_0A = struct_rpc_ctrl_set_channel_interleave_level_v1A_0A -rpc_ctrl_set_channel_interleave_level_v = struct_rpc_ctrl_set_channel_interleave_level_v1A_0A -class struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E(Structure): - pass - -class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01._fields_ = [ - ('flags', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vMemPtrs', ctypes.c_uint64 * 8), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), -] - -struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01), -] - -rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E = struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E -class struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07(Structure): - pass - -class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07._fields_ = [ - ('flags', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vMemPtrs', ctypes.c_uint64 * 9), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), -] - -struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07._pack_ = 1 # source:False -struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07), -] - -rpc_ctrl_gr_ctxsw_preemption_bind_v28_07 = struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07 -rpc_ctrl_gr_ctxsw_preemption_bind_v = struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07 -class struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E(Structure): - pass - -class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(Structure): - pass - -struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01._fields_ = [ - ('flags', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), -] - -struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01), -] - -rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E = struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E -rpc_ctrl_gr_set_ctxsw_preemption_mode_v = struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E -class struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E(Structure): - pass - -class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), - ('zcullMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00), -] - -rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E = struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E -rpc_ctrl_gr_ctxsw_zcull_bind_v = struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E -class struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E(Structure): - pass - -class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(Structure): - pass - -struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hVirtMemory', ctypes.c_uint32), - ('physAddress', ctypes.c_uint64), - ('physAttr', ctypes.c_uint32), - ('hDmaHandle', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), -] - -struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00), -] - -rpc_ctrl_gpu_initialize_ctx_v1A_0E = struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E -rpc_ctrl_gpu_initialize_ctx_v = struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E -class struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04(Structure): - pass - -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(Structure): - pass - -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('pageShift', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), - ('numLevelsToCopy', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('levels', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 * 6), -] - -struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04._pack_ = 1 # source:False -struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04), -] - -rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 = struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 -rpc_ctrl_vaspace_copy_server_reserved_pdes_v = struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 -class struct_rpc_ctrl_mc_service_interrupts_v1A_0E(Structure): - pass - -class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(Structure): - pass - -struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01._pack_ = 1 # source:False -struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01._fields_ = [ - ('engines', ctypes.c_uint32), -] - -struct_rpc_ctrl_mc_service_interrupts_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_mc_service_interrupts_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01), -] - -rpc_ctrl_mc_service_interrupts_v1A_0E = struct_rpc_ctrl_mc_service_interrupts_v1A_0E -rpc_ctrl_mc_service_interrupts_v = struct_rpc_ctrl_mc_service_interrupts_v1A_0E -class struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D(Structure): - pass - -struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D._pack_ = 1 # source:False -struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D._fields_ = [ - ('iter', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gpuIds', ctypes.c_uint32 * 32), - ('gpuCount', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_1', ctypes.c_ubyte * 3), - ('busPeerIds', ctypes.c_uint32 * 512), -] - -rpc_ctrl_get_p2p_caps_v2_v1F_0D = struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D -rpc_ctrl_get_p2p_caps_v2_v = struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D -class struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02(Structure): - pass - -class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(Structure): - pass - -class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02(Structure): - pass - -struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuUuid', ctypes.c_ubyte * 16), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerId', ctypes.c_uint32), -] - -struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02._pack_ = 1 # source:False -struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02._fields_ = [ - ('bAllCaps', ctypes.c_ubyte), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('peerGpuCount', ctypes.c_uint32), - ('peerGpuCaps', struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 * 32), -] - -struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02._pack_ = 1 # source:False -struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02._fields_ = [ - ('ctrlParams', struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02), -] - -rpc_ctrl_subdevice_get_p2p_caps_v21_02 = struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02 -rpc_ctrl_subdevice_get_p2p_caps_v = struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02 -class struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03(Structure): - pass - -class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03(Structure): - pass - -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03._fields_ = [ - ('allocatedSize', ctypes.c_uint64), - ('peakAllocatedSize', ctypes.c_uint64), - ('managedSize', ctypes.c_uint64), - ('allocationCount', ctypes.c_uint32), - ('peakAllocationCount', ctypes.c_uint32), -] - -struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03._pack_ = 1 # source:False -struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03), -] - -rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03 = struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03 -class struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06(Structure): - pass - -class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06(Structure): - pass - -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06._fields_ = [ - ('allocatedSize', ctypes.c_uint64), - ('peakAllocatedSize', ctypes.c_uint64), - ('managedSize', ctypes.c_uint64), - ('allocationCount', ctypes.c_uint32), - ('peakAllocationCount', ctypes.c_uint32), - ('largestFreeChunkSize', ctypes.c_uint64), -] - -struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06._pack_ = 1 # source:False -struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06), -] - -rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06 = struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06 -rpc_ctrl_subdevice_get_vgpu_heap_stats_v = struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06 -class struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('numSMsToClear', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00), -] - -rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C = struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C -rpc_ctrl_dbg_clear_all_sm_error_states_v = struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C -class struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(Structure): - pass - -class struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06(Structure): - pass - -struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06._pack_ = 1 # source:False -struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06._fields_ = [ - ('hwwGlobalEsr', ctypes.c_uint32), - ('hwwWarpEsr', ctypes.c_uint32), - ('hwwWarpEsrPc', ctypes.c_uint32), - ('hwwGlobalEsrReportMask', ctypes.c_uint32), - ('hwwWarpEsrReportMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hwwEsrAddr', ctypes.c_uint64), - ('hwwWarpEsrPc64', ctypes.c_uint64), - ('hwwCgaEsr', ctypes.c_uint32), - ('hwwCgaEsrReportMask', ctypes.c_uint32), -] - -class struct_NV83DE_MMU_FAULT_INFO_v16_03(Structure): - pass - -struct_NV83DE_MMU_FAULT_INFO_v16_03._pack_ = 1 # source:False -struct_NV83DE_MMU_FAULT_INFO_v16_03._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('faultInfo', ctypes.c_uint32), -] - -struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('numSMsToRead', ctypes.c_uint32), - ('smErrorStateArray', struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 * 80), - ('mmuFaultInfo', ctypes.c_uint32), - ('mmuFault', struct_NV83DE_MMU_FAULT_INFO_v16_03), - ('startingSM', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06), -] - -rpc_ctrl_dbg_read_all_sm_error_states_v21_06 = struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 -rpc_ctrl_dbg_read_all_sm_error_states_v = struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 -class struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00._fields_ = [ - ('exceptionMask', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00), -] - -rpc_ctrl_dbg_set_exception_mask_v1A_0C = struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C -rpc_ctrl_dbg_set_exception_mask_v = struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C -class struct_rpc_ctrl_gpu_promote_ctx_v1A_20(Structure): - pass - -class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(Structure): - pass - -class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20(Structure): - pass - -struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20._fields_ = [ - ('gpuPhysAddr', ctypes.c_uint64), - ('gpuVirtAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('physAttr', ctypes.c_uint32), - ('bufferId', ctypes.c_uint16), - ('bInitialize', ctypes.c_ubyte), - ('bNonmapped', ctypes.c_ubyte), -] - -struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hVirtMemory', ctypes.c_uint32), - ('virtAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('entryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('promoteEntry', struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 * 16), -] - -struct_rpc_ctrl_gpu_promote_ctx_v1A_20._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_promote_ctx_v1A_20._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('promoteCtx', struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20), -] - -rpc_ctrl_gpu_promote_ctx_v1A_20 = struct_rpc_ctrl_gpu_promote_ctx_v1A_20 -rpc_ctrl_gpu_promote_ctx_v = struct_rpc_ctrl_gpu_promote_ctx_v1A_20 -class struct_rpc_ctrl_dbg_suspend_context_v1A_10(Structure): - pass - -class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(Structure): - pass - -struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06._fields_ = [ - ('waitForEvent', ctypes.c_uint32), - ('hResidentChannel', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_suspend_context_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_suspend_context_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06), -] - -rpc_ctrl_dbg_suspend_context_v1A_10 = struct_rpc_ctrl_dbg_suspend_context_v1A_10 -rpc_ctrl_dbg_suspend_context_v = struct_rpc_ctrl_dbg_suspend_context_v1A_10 -class struct_rpc_ctrl_dbg_resume_context_v1A_10(Structure): - pass - -struct_rpc_ctrl_dbg_resume_context_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_resume_context_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -rpc_ctrl_dbg_resume_context_v1A_10 = struct_rpc_ctrl_dbg_resume_context_v1A_10 -rpc_ctrl_dbg_resume_context_v = struct_rpc_ctrl_dbg_resume_context_v1A_10 -class struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06._fields_ = [ - ('bNonTransactional', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('regOpCount', ctypes.c_uint32), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP_v03_00 * 100), -] - -struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06), -] - -rpc_ctrl_dbg_exec_reg_ops_v1A_10 = struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10 -rpc_ctrl_dbg_exec_reg_ops_v = struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10 -class struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06._fields_ = [ - ('action', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06), -] - -rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 = struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 -rpc_ctrl_dbg_set_mode_mmu_debug_v = struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 -class struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07._fields_ = [ - ('action', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07), -] - -rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07 = struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07 -rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v = struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07 -class struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('smID', ctypes.c_uint32), - ('smErrorState', struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06), -] - -struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06), -] - -rpc_ctrl_dbg_read_single_sm_error_state_v21_06 = struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 -rpc_ctrl_dbg_read_single_sm_error_state_v = struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 -class struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('smID', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06), -] - -rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 = struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 -rpc_ctrl_dbg_clear_single_sm_error_state_v = struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 -class struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06._fields_ = [ - ('action', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06), -] - -rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 = struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 -rpc_ctrl_dbg_set_mode_errbar_debug_v = struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 -class struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06._fields_ = [ - ('stopTriggerType', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06), -] - -rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 = struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 -rpc_ctrl_dbg_set_next_stop_trigger_type_v = struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 -class struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E(Structure): - pass - -class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00._fields_ = [ - ('hVASpace', ctypes.c_uint32), -] - -struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00), -] - -rpc_ctrl_dma_set_default_vaspace_v1A_0E = struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E -rpc_ctrl_dma_set_default_vaspace_v = struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E -class struct_rpc_ctrl_get_ce_pce_mask_v1A_0E(Structure): - pass - -class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('pceMask', ctypes.c_uint32), -] - -struct_rpc_ctrl_get_ce_pce_mask_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_get_ce_pce_mask_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07), -] - -rpc_ctrl_get_ce_pce_mask_v1A_0E = struct_rpc_ctrl_get_ce_pce_mask_v1A_0E -rpc_ctrl_get_ce_pce_mask_v = struct_rpc_ctrl_get_ce_pce_mask_v1A_0E -class struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E(Structure): - pass - -class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(Structure): - pass - -class struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07(Structure): - pass - -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07._pack_ = 1 # source:False -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07._fields_ = [ - ('colorFB', ctypes.c_uint32 * 4), - ('colorDS', ctypes.c_uint32 * 4), - ('depth', ctypes.c_uint32), - ('stencil', ctypes.c_uint32), -] - - -# values for enumeration 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE' -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE__enumvalues = { - 0: 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID', - 1: 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR', - 2: 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH', - 3: 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL', - 4: 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT', -} -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID = 0 -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR = 1 -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH = 2 -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL = 3 -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT = 4 -NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE = ctypes.c_uint32 # enum -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07._pack_ = 1 # source:False -struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07._fields_ = [ - ('value', struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07), - ('format', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('bIndexValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('tableType', NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE), -] - -struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07), -] - -rpc_ctrl_get_zbc_clear_table_entry_v1A_0E = struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E -rpc_ctrl_get_zbc_clear_table_entry_v = struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E -class struct_rpc_ctrl_get_nvlink_status_v23_04(Structure): - pass - -class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02(Structure): - pass - -struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02._fields_ = [ - ('deviceIdFlags', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('function', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('pciDeviceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('deviceType', ctypes.c_uint64), - ('deviceUUID', ctypes.c_ubyte * 16), -] - -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D._fields_ = [ - ('capsTbl', ctypes.c_uint32), - ('phyType', ctypes.c_ubyte), - ('subLinkWidth', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('linkState', ctypes.c_uint32), - ('rxSublinkStatus', ctypes.c_ubyte), - ('txSublinkStatus', ctypes.c_ubyte), - ('nvlinkVersion', ctypes.c_ubyte), - ('nciVersion', ctypes.c_ubyte), - ('phyVersion', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('nvlinkLinkClockKHz', ctypes.c_uint32), - ('nvlinkLineRateMbps', ctypes.c_uint32), - ('connected', ctypes.c_ubyte), - ('remoteDeviceLinkNumber', ctypes.c_ubyte), - ('localDeviceLinkNumber', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), - ('remoteDeviceInfo', struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02), - ('localDeviceInfo', struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02), -] - -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04._fields_ = [ - ('enabledLinkMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('linkInfo', struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D * 24), -] - -struct_rpc_ctrl_get_nvlink_status_v23_04._pack_ = 1 # source:False -struct_rpc_ctrl_get_nvlink_status_v23_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04), -] - -rpc_ctrl_get_nvlink_status_v23_04 = struct_rpc_ctrl_get_nvlink_status_v23_04 -class struct_rpc_ctrl_get_nvlink_status_v28_09(Structure): - pass - -class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09(Structure): - pass - -struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09._fields_ = [ - ('deviceIdFlags', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('function', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('pciDeviceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('deviceType', ctypes.c_uint64), - ('deviceUUID', ctypes.c_ubyte * 16), - ('fabricRecoveryStatusMask', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09._fields_ = [ - ('capsTbl', ctypes.c_uint32), - ('phyType', ctypes.c_ubyte), - ('subLinkWidth', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('linkState', ctypes.c_uint32), - ('rxSublinkStatus', ctypes.c_ubyte), - ('txSublinkStatus', ctypes.c_ubyte), - ('nvlinkVersion', ctypes.c_ubyte), - ('nciVersion', ctypes.c_ubyte), - ('phyVersion', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('nvlinkLinkClockKHz', ctypes.c_uint32), - ('nvlinkLineRateMbps', ctypes.c_uint32), - ('connected', ctypes.c_ubyte), - ('remoteDeviceLinkNumber', ctypes.c_ubyte), - ('localDeviceLinkNumber', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), - ('remoteDeviceInfo', struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09), - ('localDeviceInfo', struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09), -] - -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09._fields_ = [ - ('enabledLinkMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('linkInfo', struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09 * 24), -] - -struct_rpc_ctrl_get_nvlink_status_v28_09._pack_ = 1 # source:False -struct_rpc_ctrl_get_nvlink_status_v28_09._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09), -] - -rpc_ctrl_get_nvlink_status_v28_09 = struct_rpc_ctrl_get_nvlink_status_v28_09 -rpc_ctrl_get_nvlink_status_v = struct_rpc_ctrl_get_nvlink_status_v28_09 -class struct_rpc_ctrl_get_p2p_caps_v1F_0D(Structure): - pass - -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('gpuCount', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_rpc_ctrl_get_p2p_caps_v1F_0D._pack_ = 1 # source:False -struct_rpc_ctrl_get_p2p_caps_v1F_0D._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D), -] - -rpc_ctrl_get_p2p_caps_v1F_0D = struct_rpc_ctrl_get_p2p_caps_v1F_0D -rpc_ctrl_get_p2p_caps_v = struct_rpc_ctrl_get_p2p_caps_v1F_0D -class struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E(Structure): - pass - -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(Structure): - pass - -class struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A(Structure): - pass - -struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A._pack_ = 1 # source:False -struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A._fields_ = [ - ('array', ctypes.c_uint32 * 8), -] - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A._fields_ = [ - ('grpACount', ctypes.c_uint32), - ('grpBCount', ctypes.c_uint32), - ('gpuIdGrpA', ctypes.c_uint32 * 8), - ('gpuIdGrpB', ctypes.c_uint32 * 8), - ('p2pCaps', struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8), - ('a2bOptimalReadCes', struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8), - ('a2bOptimalWriteCes', struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8), - ('b2aOptimalReadCes', struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8), - ('b2aOptimalWriteCes', struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A * 8), -] - -struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E._pack_ = 1 # source:False -struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A), -] - -rpc_ctrl_get_p2p_caps_matrix_v1A_0E = struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E -rpc_ctrl_get_p2p_caps_matrix_v = struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E -class struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F(Structure): - pass - -class struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(Structure): - pass - -struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F._pack_ = 1 # source:False -struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F._fields_ = [ - ('ctxsw', ctypes.c_ubyte), -] - -struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F._pack_ = 1 # source:False -struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_reserve_pm_area_smpc_v1A_0F = struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F -rpc_ctrl_reserve_pm_area_smpc_v = struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F -class struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F(Structure): - pass - -class struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(Structure): - pass - -struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F._pack_ = 1 # source:False -struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F._fields_ = [ - ('ctxsw', ctypes.c_ubyte), -] - -struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F._pack_ = 1 # source:False -struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_reserve_hwpm_legacy_v1A_0F = struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F -rpc_ctrl_reserve_hwpm_legacy_v = struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F -class struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F(Structure): - pass - -class struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(Structure): - pass - - -# values for enumeration 'NVB0CC_REGOPS_MODE' -NVB0CC_REGOPS_MODE__enumvalues = { - 0: 'NVB0CC_REGOPS_MODE_ALL_OR_NONE', - 1: 'NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR', -} -NVB0CC_REGOPS_MODE_ALL_OR_NONE = 0 -NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR = 1 -NVB0CC_REGOPS_MODE = ctypes.c_uint32 # enum -struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F._pack_ = 1 # source:False -struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F._fields_ = [ - ('regOpCount', ctypes.c_uint32), - ('mode', NVB0CC_REGOPS_MODE), - ('bPassed', ctypes.c_ubyte), - ('bDirect', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP_v03_00 * 124), -] - -struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F._pack_ = 1 # source:False -struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F), -] - -rpc_ctrl_b0cc_exec_reg_ops_v1A_0F = struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F -rpc_ctrl_b0cc_exec_reg_ops_v = struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F -class struct_rpc_ctrl_bind_pm_resources_v1A_0F(Structure): - pass - -struct_rpc_ctrl_bind_pm_resources_v1A_0F._pack_ = 1 # source:False -struct_rpc_ctrl_bind_pm_resources_v1A_0F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -rpc_ctrl_bind_pm_resources_v1A_0F = struct_rpc_ctrl_bind_pm_resources_v1A_0F -rpc_ctrl_bind_pm_resources_v = struct_rpc_ctrl_bind_pm_resources_v1A_0F -class struct_rpc_ctrl_alloc_pma_stream_v1A_14(Structure): - pass - -class struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(Structure): - pass - -struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14._pack_ = 1 # source:False -struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14._fields_ = [ - ('hMemPmaBuffer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pmaBufferOffset', ctypes.c_uint64), - ('pmaBufferSize', ctypes.c_uint64), - ('hMemPmaBytesAvailable', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pmaBytesAvailableOffset', ctypes.c_uint64), - ('ctxsw', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), - ('pmaChannelIdx', ctypes.c_uint32), - ('pmaBufferVA', ctypes.c_uint64), -] - -struct_rpc_ctrl_alloc_pma_stream_v1A_14._pack_ = 1 # source:False -struct_rpc_ctrl_alloc_pma_stream_v1A_14._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14), -] - -rpc_ctrl_alloc_pma_stream_v1A_14 = struct_rpc_ctrl_alloc_pma_stream_v1A_14 -rpc_ctrl_alloc_pma_stream_v = struct_rpc_ctrl_alloc_pma_stream_v1A_14 -class struct_rpc_ctrl_pma_stream_update_get_put_v1A_14(Structure): - pass - -class struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(Structure): - pass - -struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14._pack_ = 1 # source:False -struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14._fields_ = [ - ('bytesConsumed', ctypes.c_uint64), - ('bUpdateAvailableBytes', ctypes.c_ubyte), - ('bWait', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('bytesAvailable', ctypes.c_uint64), - ('bReturnPut', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), - ('putPtr', ctypes.c_uint64), - ('pmaChannelIdx', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), -] - -struct_rpc_ctrl_pma_stream_update_get_put_v1A_14._pack_ = 1 # source:False -struct_rpc_ctrl_pma_stream_update_get_put_v1A_14._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14), -] - -rpc_ctrl_pma_stream_update_get_put_v1A_14 = struct_rpc_ctrl_pma_stream_update_get_put_v1A_14 -rpc_ctrl_pma_stream_update_get_put_v = struct_rpc_ctrl_pma_stream_update_get_put_v1A_14 -class struct_rpc_ctrl_fb_get_info_v2_v25_0A(Structure): - pass - -class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(Structure): - pass - -class struct_NV2080_CTRL_FB_INFO_v1A_15(Structure): - pass - -struct_NV2080_CTRL_FB_INFO_v1A_15._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_INFO_v1A_15._fields_ = [ - ('index', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A._fields_ = [ - ('fbInfoListSize', ctypes.c_uint32), - ('fbInfoList', struct_NV2080_CTRL_FB_INFO_v1A_15 * 55), -] - -struct_rpc_ctrl_fb_get_info_v2_v25_0A._pack_ = 1 # source:False -struct_rpc_ctrl_fb_get_info_v2_v25_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A), -] - -rpc_ctrl_fb_get_info_v2_v25_0A = struct_rpc_ctrl_fb_get_info_v2_v25_0A -class struct_rpc_ctrl_fb_get_info_v2_v27_00(Structure): - pass - -class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00(Structure): - pass - -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00._fields_ = [ - ('fbInfoListSize', ctypes.c_uint32), - ('fbInfoList', struct_NV2080_CTRL_FB_INFO_v1A_15 * 57), -] - -struct_rpc_ctrl_fb_get_info_v2_v27_00._pack_ = 1 # source:False -struct_rpc_ctrl_fb_get_info_v2_v27_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00), -] - -rpc_ctrl_fb_get_info_v2_v27_00 = struct_rpc_ctrl_fb_get_info_v2_v27_00 -rpc_ctrl_fb_get_info_v2_v = struct_rpc_ctrl_fb_get_info_v2_v27_00 -class struct_rpc_ctrl_fifo_set_channel_properties_v1A_16(Structure): - pass - -class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(Structure): - pass - -struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('property', ctypes.c_uint32), - ('value', ctypes.c_uint64), -] - -struct_rpc_ctrl_fifo_set_channel_properties_v1A_16._pack_ = 1 # source:False -struct_rpc_ctrl_fifo_set_channel_properties_v1A_16._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00), -] - -rpc_ctrl_fifo_set_channel_properties_v1A_16 = struct_rpc_ctrl_fifo_set_channel_properties_v1A_16 -rpc_ctrl_fifo_set_channel_properties_v = struct_rpc_ctrl_fifo_set_channel_properties_v1A_16 -class struct_rpc_ctrl_gpu_evict_ctx_v1A_1C(Structure): - pass - -class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00(Structure): - pass - -struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -struct_rpc_ctrl_gpu_evict_ctx_v1A_1C._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_evict_ctx_v1A_1C._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00), -] - -rpc_ctrl_gpu_evict_ctx_v1A_1C = struct_rpc_ctrl_gpu_evict_ctx_v1A_1C -rpc_ctrl_gpu_evict_ctx_v = struct_rpc_ctrl_gpu_evict_ctx_v1A_1C -class struct_rpc_ctrl_fb_get_fs_info_v24_00(Structure): - pass - -class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(Structure): - pass - -class struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D(Structure): - pass - -class union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(Union): - pass - -class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D._fields_ = [ - ('data', ctypes.c_ubyte * 24), -] - -class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbpEnMask', ctypes.c_uint64), -] - -class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ltcEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ltsEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpaEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ropEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ltcEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ltsEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('fbpaEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ropEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('fbpaSubpEnMask', ctypes.c_uint64), -] - -class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpaSubpEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpLogicalIndex', ctypes.c_uint32), -] - -union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D._pack_ = 1 # source:False -union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D._fields_ = [ - ('inv', struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D), - ('fbp', struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D), - ('ltc', struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D), - ('lts', struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D), - ('fbpa', struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D), - ('rop', struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D), - ('dmLtc', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D), - ('dmLts', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D), - ('dmFbpa', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D), - ('dmRop', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D), - ('dmFbpaSubp', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D), - ('fbpaSubp', struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D), - ('fbpLogicalMap', struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryParams', union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D), -] - -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D * 120), -] - -struct_rpc_ctrl_fb_get_fs_info_v24_00._pack_ = 1 # source:False -struct_rpc_ctrl_fb_get_fs_info_v24_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00), -] - -rpc_ctrl_fb_get_fs_info_v24_00 = struct_rpc_ctrl_fb_get_fs_info_v24_00 -class struct_rpc_ctrl_fb_get_fs_info_v26_04(Structure): - pass - -class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04(Structure): - pass - -class struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04(Structure): - pass - -class union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04(Union): - pass - -class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04(Structure): - pass - -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04._pack_ = 1 # source:False -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04._fields_ = [ - ('sysIdx', ctypes.c_uint32), - ('sysl2LtcEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('pacEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('logicalLtcEnMask', ctypes.c_uint64), -] - -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('logicalLtcEnMask', ctypes.c_uint64), -] - -union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04._pack_ = 1 # source:False -union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04._fields_ = [ - ('inv', struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D), - ('fbp', struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D), - ('ltc', struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D), - ('lts', struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D), - ('fbpa', struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D), - ('rop', struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D), - ('dmLtc', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D), - ('dmLts', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D), - ('dmFbpa', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D), - ('dmRop', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D), - ('dmFbpaSubp', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D), - ('fbpaSubp', struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D), - ('fbpLogicalMap', struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D), - ('sysl2Ltc', struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04), - ('pac', struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04), - ('logicalLtc', struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04), - ('dmLogicalLtc', struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryParams', union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04), -] - -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04 * 120), -] - -struct_rpc_ctrl_fb_get_fs_info_v26_04._pack_ = 1 # source:False -struct_rpc_ctrl_fb_get_fs_info_v26_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04), -] - -rpc_ctrl_fb_get_fs_info_v26_04 = struct_rpc_ctrl_fb_get_fs_info_v26_04 -rpc_ctrl_fb_get_fs_info_v = struct_rpc_ctrl_fb_get_fs_info_v26_04 -class struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D(Structure): - pass - -class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(Structure): - pass - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D(Structure): - pass - -class union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(Union): - pass - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D._fields_ = [ - ('gpcCount', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('chipletGpcMap', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('ppcMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('gpcId', ctypes.c_uint32), - ('chipletGpcMap', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D._fields_ = [ - ('chipletSyspipeMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D._fields_ = [ - ('swizzId', ctypes.c_uint16), - ('physSyspipeIdCount', ctypes.c_uint16), - ('physSyspipeId', ctypes.c_ubyte * 8), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('grIdx', ctypes.c_uint32), - ('gpcEnMask', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D._fields_ = [ - ('syspipeId', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('ropMask', ctypes.c_uint32), -] - -union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D._pack_ = 1 # source:False -union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D._fields_ = [ - ('gpcCountData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D), - ('chipletGpcMapData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D), - ('tpcMaskData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D), - ('ppcMaskData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D), - ('partitionGpcMapData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D), - ('syspipeMaskData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D), - ('partitionChipletSyspipeData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D), - ('dmGpcMaskData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D), - ('partitionSyspipeIdData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D), - ('ropMaskData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryData', union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D), -] - -struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D._pack_ = 1 # source:False -struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D * 96), -] - -struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D._pack_ = 1 # source:False -struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D), -] - -rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D = struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D -rpc_ctrl_grmgr_get_gr_fs_info_v = struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D -class struct_rpc_ctrl_stop_channel_v1A_1E(Structure): - pass - -class struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E(Structure): - pass - -struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E._pack_ = 1 # source:False -struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E._fields_ = [ - ('bImmediate', ctypes.c_ubyte), -] - -struct_rpc_ctrl_stop_channel_v1A_1E._pack_ = 1 # source:False -struct_rpc_ctrl_stop_channel_v1A_1E._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_stop_channel_v1A_1E = struct_rpc_ctrl_stop_channel_v1A_1E -rpc_ctrl_stop_channel_v = struct_rpc_ctrl_stop_channel_v1A_1E -class struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F(Structure): - pass - -class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(Structure): - pass - -struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('samplingMode', ctypes.c_uint32), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), -] - -struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F._pack_ = 1 # source:False -struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F), -] - -rpc_ctrl_gr_pc_sampling_mode_v1A_1F = struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F -rpc_ctrl_gr_pc_sampling_mode_v = struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F -class struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F(Structure): - pass - -class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(Structure): - pass - -class struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F(Structure): - pass - -struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F._pack_ = 1 # source:False -struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F._fields_ = [ - ('clientActiveMask', ctypes.c_uint32), - ('bRegkeyLimitRatedTdp', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - - -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_ACTION' -NV2080_CTRL_PERF_RATED_TDP_ACTION__enumvalues = { - 0: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', - 1: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', - 2: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', - 3: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', - 4: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', -} -NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4 -NV2080_CTRL_PERF_RATED_TDP_ACTION = ctypes.c_uint32 # enum -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F._fields_ = [ - ('rm', struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F), - ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('inputs', NV2080_CTRL_PERF_RATED_TDP_ACTION * 5), -] - -struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F._pack_ = 1 # source:False -struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F), -] - -rpc_ctrl_perf_rated_tdp_get_status_v1A_1F = struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F -rpc_ctrl_perf_rated_tdp_get_status_v = struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F -class struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F(Structure): - pass - -class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(Structure): - pass - - -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_CLIENT' -NV2080_CTRL_PERF_RATED_TDP_CLIENT__enumvalues = { - 0: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', - 1: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', - 2: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', - 3: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', - 4: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', - 5: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', -} -NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5 -NV2080_CTRL_PERF_RATED_TDP_CLIENT = ctypes.c_uint32 # enum -struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F._fields_ = [ - ('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT), - ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION), -] - -struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F._pack_ = 1 # source:False -struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F), -] - -rpc_ctrl_perf_rated_tdp_set_control_v1A_1F = struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F -rpc_ctrl_perf_rated_tdp_set_control_v = struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F -class struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F(Structure): - pass - -class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(Structure): - pass - -struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F._fields_ = [ - ('bSetMaxFreq', ctypes.c_ubyte), -] - -struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F._pack_ = 1 # source:False -struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_timer_set_gr_tick_freq_v1A_1F = struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F -rpc_ctrl_timer_set_gr_tick_freq_v = struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F -class struct_rpc_ctrl_free_pma_stream_v1A_1F(Structure): - pass - -class struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(Structure): - pass - -struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F._pack_ = 1 # source:False -struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F._fields_ = [ - ('pmaChannelIdx', ctypes.c_uint32), -] - -struct_rpc_ctrl_free_pma_stream_v1A_1F._pack_ = 1 # source:False -struct_rpc_ctrl_free_pma_stream_v1A_1F._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F), -] - -rpc_ctrl_free_pma_stream_v1A_1F = struct_rpc_ctrl_free_pma_stream_v1A_1F -rpc_ctrl_free_pma_stream_v = struct_rpc_ctrl_free_pma_stream_v1A_1F -class struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23(Structure): - pass - -class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23(Structure): - pass - -struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cacheAttrib', ctypes.c_uint32), -] - -struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23._pack_ = 1 # source:False -struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23), -] - -rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 = struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 -rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v = struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 -class struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02._fields_ = [ - ('smID', ctypes.c_uint32), - ('bSingleStep', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02), -] - -rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 = struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 -rpc_ctrl_dbg_set_single_sm_single_step_v = struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 -class struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04(Structure): - pass - -class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(Structure): - pass - - -# values for enumeration 'NV0080_CTRL_GR_TPC_PARTITION_MODE' -NV0080_CTRL_GR_TPC_PARTITION_MODE__enumvalues = { - 0: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', - 1: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', - 2: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', -} -NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0 -NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1 -NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2 -NV0080_CTRL_GR_TPC_PARTITION_MODE = ctypes.c_uint32 # enum -struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04._pack_ = 1 # source:False -struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04._fields_ = [ - ('hChannelGroup', ctypes.c_uint32), - ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE), - ('bEnableAllTpcs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), -] - -struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04._pack_ = 1 # source:False -struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04), -] - -rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 = struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 -rpc_ctrl_gr_get_tpc_partition_mode_v = struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 -class struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04(Structure): - pass - -struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04._pack_ = 1 # source:False -struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04), -] - -rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 = struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 -rpc_ctrl_gr_set_tpc_partition_mode_v = struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 -class struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07(Structure): - pass - -class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07(Structure): - pass - -class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cpuCacheAttrib', ctypes.c_uint32), -] - -struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07._pack_ = 1 # source:False -struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07._fields_ = [ - ('methodBufferMemdesc', struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 * 2), - ('bar2Addr', ctypes.c_uint64 * 2), - ('numValidEntries', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07._pack_ = 1 # source:False -struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07), -] - -rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 = struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 -rpc_ctrl_internal_promote_fault_method_buffers_v = struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 -class struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05(Structure): - pass - -class struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05._fields_ = [ - ('bZbcSurfacesExist', ctypes.c_ubyte), -] - -struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05._pack_ = 1 # source:False -struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 = struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 -rpc_ctrl_internal_memsys_set_zbc_referenced_v = struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 -class struct_rpc_ctrl_fabric_memory_describe_v1E_0C(Structure): - pass - -class struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C(Structure): - pass - -struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C._pack_ = 1 # source:False -struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C._fields_ = [ - ('offset', ctypes.c_uint64), - ('totalPfns', ctypes.c_uint64), - ('pfnArray', ctypes.c_uint32 * 512), - ('numPfns', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_rpc_ctrl_fabric_memory_describe_v1E_0C._pack_ = 1 # source:False -struct_rpc_ctrl_fabric_memory_describe_v1E_0C._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C), -] - -rpc_ctrl_fabric_memory_describe_v1E_0C = struct_rpc_ctrl_fabric_memory_describe_v1E_0C -rpc_ctrl_fabric_memory_describe_v = struct_rpc_ctrl_fabric_memory_describe_v1E_0C -class struct_rpc_ctrl_fabric_mem_stats_v1E_0C(Structure): - pass - -class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C(Structure): - pass - -struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C._fields_ = [ - ('totalSize', ctypes.c_uint64), - ('freeSize', ctypes.c_uint64), -] - -struct_rpc_ctrl_fabric_mem_stats_v1E_0C._pack_ = 1 # source:False -struct_rpc_ctrl_fabric_mem_stats_v1E_0C._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C), -] - -rpc_ctrl_fabric_mem_stats_v1E_0C = struct_rpc_ctrl_fabric_mem_stats_v1E_0C -rpc_ctrl_fabric_mem_stats_v = struct_rpc_ctrl_fabric_mem_stats_v1E_0C -class struct_rpc_ctrl_bus_set_p2p_mapping_v21_03(Structure): - pass - -class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bSpaAccessOnly', ctypes.c_uint32), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -struct_rpc_ctrl_bus_set_p2p_mapping_v21_03._pack_ = 1 # source:False -struct_rpc_ctrl_bus_set_p2p_mapping_v21_03._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03), -] - -rpc_ctrl_bus_set_p2p_mapping_v21_03 = struct_rpc_ctrl_bus_set_p2p_mapping_v21_03 -class struct_rpc_ctrl_bus_set_p2p_mapping_v29_08(Structure): - pass - -class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bEgmPeer', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bSpaAccessOnly', ctypes.c_uint32), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -struct_rpc_ctrl_bus_set_p2p_mapping_v29_08._pack_ = 1 # source:False -struct_rpc_ctrl_bus_set_p2p_mapping_v29_08._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08), -] - -rpc_ctrl_bus_set_p2p_mapping_v29_08 = struct_rpc_ctrl_bus_set_p2p_mapping_v29_08 -rpc_ctrl_bus_set_p2p_mapping_v = struct_rpc_ctrl_bus_set_p2p_mapping_v29_08 -class struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03(Structure): - pass - -class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(Structure): - pass - -struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03._pack_ = 1 # source:False -struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03), -] - -rpc_ctrl_bus_unset_p2p_mapping_v21_03 = struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03 -rpc_ctrl_bus_unset_p2p_mapping_v = struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03 -class struct_rpc_ctrl_gpu_get_info_v2_v25_11(Structure): - pass - -class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(Structure): - pass - -class struct_NV2080_CTRL_GPU_INFO_v25_11(Structure): - pass - -struct_NV2080_CTRL_GPU_INFO_v25_11._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_INFO_v25_11._fields_ = [ - ('index', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11._fields_ = [ - ('gpuInfoListSize', ctypes.c_uint32), - ('gpuInfoList', struct_NV2080_CTRL_GPU_INFO_v25_11 * 65), -] - -struct_rpc_ctrl_gpu_get_info_v2_v25_11._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_get_info_v2_v25_11._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11), -] - -rpc_ctrl_gpu_get_info_v2_v25_11 = struct_rpc_ctrl_gpu_get_info_v2_v25_11 -rpc_ctrl_gpu_get_info_v2_v = struct_rpc_ctrl_gpu_get_info_v2_v25_11 -class struct_rpc_update_gpm_guest_buffer_info_v27_01(Structure): - pass - -struct_rpc_update_gpm_guest_buffer_info_v27_01._pack_ = 1 # source:False -struct_rpc_update_gpm_guest_buffer_info_v27_01._fields_ = [ - ('gpfn', ctypes.c_uint64), - ('swizzId', ctypes.c_uint32), - ('computeId', ctypes.c_uint32), - ('bufSize', ctypes.c_uint32), - ('bMap', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_update_gpm_guest_buffer_info_v27_01 = struct_rpc_update_gpm_guest_buffer_info_v27_01 -rpc_update_gpm_guest_buffer_info_v = struct_rpc_update_gpm_guest_buffer_info_v27_01 -class struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08(Structure): - pass - -class struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(Structure): - pass - -struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08._pack_ = 1 # source:False -struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08._fields_ = [ - ('pmaChannelIdx', ctypes.c_uint32), - ('bMembytesPollingRequired', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08._pack_ = 1 # source:False -struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08), -] - -rpc_ctrl_internal_quiesce_pma_channel_v1C_08 = struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 -rpc_ctrl_internal_quiesce_pma_channel_v = struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 -class struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C(Structure): - pass - -class struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(Structure): - pass - -struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C._pack_ = 1 # source:False -struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C._fields_ = [ - ('pmaChannelIdx', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pmaBufferVA', ctypes.c_uint64), - ('pmaBufferSize', ctypes.c_uint64), - ('membytesVA', ctypes.c_uint64), - ('hwpmIBPA', ctypes.c_uint64), - ('hwpmIBAperture', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C._pack_ = 1 # source:False -struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C), -] - -rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C = struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C -rpc_ctrl_internal_sriov_promote_pma_stream_v = struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C -class struct_rpc_ctrl_exec_partitions_create_v24_05(Structure): - pass - -class struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05(Structure): - pass - -class struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05(Structure): - pass - -struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05._pack_ = 1 # source:False -struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05._fields_ = [ - ('gpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('ofaCount', ctypes.c_uint32), - ('sharedEngFlag', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('spanStart', ctypes.c_uint32), - ('computeSize', ctypes.c_uint32), -] - -struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05._pack_ = 1 # source:False -struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05._fields_ = [ - ('bQuery', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('execPartCount', ctypes.c_uint32), - ('execPartInfo', struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 * 8), - ('execPartId', ctypes.c_uint32 * 8), -] - -struct_rpc_ctrl_exec_partitions_create_v24_05._pack_ = 1 # source:False -struct_rpc_ctrl_exec_partitions_create_v24_05._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('execPartitionsCreate', struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05), -] - -rpc_ctrl_exec_partitions_create_v24_05 = struct_rpc_ctrl_exec_partitions_create_v24_05 -rpc_ctrl_exec_partitions_create_v = struct_rpc_ctrl_exec_partitions_create_v24_05 -class struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05(Structure): - pass - -class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04(Structure): - pass - -struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04._fields_ = [ - ('imbPhysAddr', ctypes.c_uint64), - ('addrSpace', ctypes.c_uint32), - ('flaAction', ctypes.c_uint32), -] - -struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05._pack_ = 1 # source:False -struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04), -] - -rpc_ctrl_fla_setup_instance_mem_block_v21_05 = struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05 -rpc_ctrl_fla_setup_instance_mem_block_v = struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05 -class struct_rpc_ctrl_get_total_hs_credits_v21_08(Structure): - pass - -class struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(Structure): - pass - -struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08._pack_ = 1 # source:False -struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08._fields_ = [ - ('numCredits', ctypes.c_uint32), -] - -struct_rpc_ctrl_get_total_hs_credits_v21_08._pack_ = 1 # source:False -struct_rpc_ctrl_get_total_hs_credits_v21_08._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08), -] - -rpc_ctrl_get_total_hs_credits_v21_08 = struct_rpc_ctrl_get_total_hs_credits_v21_08 -rpc_ctrl_get_total_hs_credits_v = struct_rpc_ctrl_get_total_hs_credits_v21_08 -class struct_rpc_ctrl_get_hs_credits_v21_08(Structure): - pass - -class struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(Structure): - pass - -class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08(Structure): - pass - -struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08._pack_ = 1 # source:False -struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08._fields_ = [ - ('status', ctypes.c_ubyte), - ('entryIndex', ctypes.c_ubyte), -] - -class struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08(Structure): - pass - -struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08._pack_ = 1 # source:False -struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08._fields_ = [ - ('chipletType', ctypes.c_ubyte), - ('chipletIndex', ctypes.c_ubyte), - ('numCredits', ctypes.c_uint16), -] - -struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08._pack_ = 1 # source:False -struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08._fields_ = [ - ('pmaChannelIdx', ctypes.c_ubyte), - ('numEntries', ctypes.c_ubyte), - ('statusInfo', struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08), - ('creditInfo', struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 * 63), -] - -struct_rpc_ctrl_get_hs_credits_v21_08._pack_ = 1 # source:False -struct_rpc_ctrl_get_hs_credits_v21_08._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08), -] - -rpc_ctrl_get_hs_credits_v21_08 = struct_rpc_ctrl_get_hs_credits_v21_08 -rpc_ctrl_get_hs_credits_v = struct_rpc_ctrl_get_hs_credits_v21_08 -class struct_rpc_ctrl_reserve_hes_v29_07(Structure): - pass - -class struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07(Structure): - pass - -class struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07(Structure): - pass - -class struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07(Structure): - pass - -struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07._pack_ = 1 # source:False -struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07._fields_ = [ - ('ctxsw', ctypes.c_ubyte), -] - -struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07._pack_ = 1 # source:False -struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07._fields_ = [ - ('cwd', struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07), -] - -struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07._pack_ = 1 # source:False -struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07._fields_ = [ - ('type', ctypes.c_uint32), - ('reserveParams', struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_rpc_ctrl_reserve_hes_v29_07._pack_ = 1 # source:False -struct_rpc_ctrl_reserve_hes_v29_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07), -] - -rpc_ctrl_reserve_hes_v29_07 = struct_rpc_ctrl_reserve_hes_v29_07 -rpc_ctrl_reserve_hes_v = struct_rpc_ctrl_reserve_hes_v29_07 -class struct_rpc_ctrl_release_hes_v29_07(Structure): - pass - -class struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07(Structure): - pass - -struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07._pack_ = 1 # source:False -struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07._fields_ = [ - ('type', ctypes.c_uint32), -] - -struct_rpc_ctrl_release_hes_v29_07._pack_ = 1 # source:False -struct_rpc_ctrl_release_hes_v29_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07), -] - -rpc_ctrl_release_hes_v29_07 = struct_rpc_ctrl_release_hes_v29_07 -rpc_ctrl_release_hes_v = struct_rpc_ctrl_release_hes_v29_07 -class struct_rpc_ctrl_reserve_ccu_prof_v29_07(Structure): - pass - -class struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07(Structure): - pass - -struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07._pack_ = 1 # source:False -struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07._fields_ = [ - ('ctxsw', ctypes.c_ubyte), -] - -struct_rpc_ctrl_reserve_ccu_prof_v29_07._pack_ = 1 # source:False -struct_rpc_ctrl_reserve_ccu_prof_v29_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_reserve_ccu_prof_v29_07 = struct_rpc_ctrl_reserve_ccu_prof_v29_07 -rpc_ctrl_reserve_ccu_prof_v = struct_rpc_ctrl_reserve_ccu_prof_v29_07 -class struct_rpc_ctrl_release_ccu_prof_v29_07(Structure): - pass - -struct_rpc_ctrl_release_ccu_prof_v29_07._pack_ = 1 # source:False -struct_rpc_ctrl_release_ccu_prof_v29_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), -] - -rpc_ctrl_release_ccu_prof_v29_07 = struct_rpc_ctrl_release_ccu_prof_v29_07 -rpc_ctrl_release_ccu_prof_v = struct_rpc_ctrl_release_ccu_prof_v29_07 -class struct_rpc_ctrl_set_hs_credits_v21_08(Structure): - pass - -class struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(Structure): - pass - -struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08._pack_ = 1 # source:False -struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08._fields_ = [ - ('pmaChannelIdx', ctypes.c_ubyte), - ('numEntries', ctypes.c_ubyte), - ('statusInfo', struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08), - ('creditInfo', struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 * 63), -] - -struct_rpc_ctrl_set_hs_credits_v21_08._pack_ = 1 # source:False -struct_rpc_ctrl_set_hs_credits_v21_08._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08), -] - -rpc_ctrl_set_hs_credits_v21_08 = struct_rpc_ctrl_set_hs_credits_v21_08 -rpc_ctrl_set_hs_credits_v = struct_rpc_ctrl_set_hs_credits_v21_08 -class struct_rpc_ctrl_pm_area_pc_sampler_v21_0B(Structure): - pass - -struct_rpc_ctrl_pm_area_pc_sampler_v21_0B._pack_ = 1 # source:False -struct_rpc_ctrl_pm_area_pc_sampler_v21_0B._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), -] - -rpc_ctrl_pm_area_pc_sampler_v21_0B = struct_rpc_ctrl_pm_area_pc_sampler_v21_0B -rpc_ctrl_pm_area_pc_sampler_v = struct_rpc_ctrl_pm_area_pc_sampler_v21_0B -class struct_rpc_ctrl_exec_partitions_delete_v1F_0A(Structure): - pass - -class struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05(Structure): - pass - -struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05._pack_ = 1 # source:False -struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05._fields_ = [ - ('execPartCount', ctypes.c_uint32), - ('execPartId', ctypes.c_uint32 * 8), -] - -struct_rpc_ctrl_exec_partitions_delete_v1F_0A._pack_ = 1 # source:False -struct_rpc_ctrl_exec_partitions_delete_v1F_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('execPartitionsDelete', struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05), -] - -rpc_ctrl_exec_partitions_delete_v1F_0A = struct_rpc_ctrl_exec_partitions_delete_v1F_0A -rpc_ctrl_exec_partitions_delete_v = struct_rpc_ctrl_exec_partitions_delete_v1F_0A -class struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A(Structure): - pass - -class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00(Structure): - pass - -struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00._pack_ = 1 # source:False -struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00._fields_ = [ - ('workSubmitToken', ctypes.c_uint32), -] - -struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A._pack_ = 1 # source:False -struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('workSubmitToken', struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00), -] - -rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A = struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A -rpc_ctrl_gpfifo_get_work_submit_token_v = struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A -class struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A(Structure): - pass - -class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04(Structure): - pass - -struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04._pack_ = 1 # source:False -struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04._fields_ = [ - ('index', ctypes.c_uint32), -] - -struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A._pack_ = 1 # source:False -struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('setWorkSubmitTokenIndex', struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04), -] - -rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A = struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A -rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v = struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A -class struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D(Structure): - pass - -class struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B(Structure): - pass - -struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B._pack_ = 1 # source:False -struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B._fields_ = [ - ('eccMask', ctypes.c_uint32), - ('nvlinkMask', ctypes.c_uint32), -] - -struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D._pack_ = 1 # source:False -struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('vfErrContIntrMask', struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B), -] - -rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D = struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D -rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v = struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D -class struct_rpc_save_hibernation_data_v1E_0E(Structure): - pass - -struct_rpc_save_hibernation_data_v1E_0E._pack_ = 1 # source:False -struct_rpc_save_hibernation_data_v1E_0E._fields_ = [ - ('remainedBytes', ctypes.c_uint32), - ('payload', ctypes.c_ubyte * 0), -] - -rpc_save_hibernation_data_v1E_0E = struct_rpc_save_hibernation_data_v1E_0E -rpc_save_hibernation_data_v = struct_rpc_save_hibernation_data_v1E_0E -class struct_rpc_restore_hibernation_data_v1E_0E(Structure): - pass - -struct_rpc_restore_hibernation_data_v1E_0E._pack_ = 1 # source:False -struct_rpc_restore_hibernation_data_v1E_0E._fields_ = [ - ('remainedBytes', ctypes.c_uint32), - ('payload', ctypes.c_ubyte * 0), -] - -rpc_restore_hibernation_data_v1E_0E = struct_rpc_restore_hibernation_data_v1E_0E -rpc_restore_hibernation_data_v = struct_rpc_restore_hibernation_data_v1E_0E -class struct_rpc_ctrl_get_mmu_debug_mode_v1E_06(Structure): - pass - -class struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(Structure): - pass - -struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06._pack_ = 1 # source:False -struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06._fields_ = [ - ('bMode', ctypes.c_ubyte), -] - -struct_rpc_ctrl_get_mmu_debug_mode_v1E_06._pack_ = 1 # source:False -struct_rpc_ctrl_get_mmu_debug_mode_v1E_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_ctrl_get_mmu_debug_mode_v1E_06 = struct_rpc_ctrl_get_mmu_debug_mode_v1E_06 -rpc_ctrl_get_mmu_debug_mode_v = struct_rpc_ctrl_get_mmu_debug_mode_v1E_06 -class struct_rpc_disable_channels_v1E_0B(Structure): - pass - -struct_rpc_disable_channels_v1E_0B._pack_ = 1 # source:False -struct_rpc_disable_channels_v1E_0B._fields_ = [ - ('bDisable', ctypes.c_uint32), -] - -rpc_disable_channels_v1E_0B = struct_rpc_disable_channels_v1E_0B -rpc_disable_channels_v = struct_rpc_disable_channels_v1E_0B -class struct_rpc_ctrl_gpu_migratable_ops_v21_07(Structure): - pass - -class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(Structure): - pass - -struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('regOpCount', ctypes.c_uint32), - ('smIds', ctypes.c_uint32 * 50), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP_v03_00 * 50), - ('grRouteInfo', struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01), -] - -struct_rpc_ctrl_gpu_migratable_ops_v21_07._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_migratable_ops_v21_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07), -] - -rpc_ctrl_gpu_migratable_ops_v21_07 = struct_rpc_ctrl_gpu_migratable_ops_v21_07 -rpc_ctrl_gpu_migratable_ops_v = struct_rpc_ctrl_gpu_migratable_ops_v21_07 -class struct_rpc_invalidate_tlb_v23_03(Structure): - pass - -struct_rpc_invalidate_tlb_v23_03._pack_ = 1 # source:False -struct_rpc_invalidate_tlb_v23_03._fields_ = [ - ('pdbAddress', ctypes.c_uint64), - ('regVal', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -rpc_invalidate_tlb_v23_03 = struct_rpc_invalidate_tlb_v23_03 -rpc_invalidate_tlb_v = struct_rpc_invalidate_tlb_v23_03 -class struct_rpc_get_brand_caps_v25_12(Structure): - pass - -struct_rpc_get_brand_caps_v25_12._pack_ = 1 # source:False -struct_rpc_get_brand_caps_v25_12._fields_ = [ - ('brands', ctypes.c_uint32), -] - -rpc_get_brand_caps_v25_12 = struct_rpc_get_brand_caps_v25_12 -rpc_get_brand_caps_v = struct_rpc_get_brand_caps_v25_12 -class struct_rpc_gsp_set_system_info_v17_00(Structure): - pass - -struct_rpc_gsp_set_system_info_v17_00._pack_ = 1 # source:False -struct_rpc_gsp_set_system_info_v17_00._fields_ = [ - ('data', ctypes.c_uint32), -] - -rpc_gsp_set_system_info_v17_00 = struct_rpc_gsp_set_system_info_v17_00 -rpc_gsp_set_system_info_v = struct_rpc_gsp_set_system_info_v17_00 -class struct_rpc_gsp_rm_alloc_v03_00(Structure): - pass - -struct_rpc_gsp_rm_alloc_v03_00._pack_ = 1 # source:False -struct_rpc_gsp_rm_alloc_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('paramsSize', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_ubyte * 4), - ('params', ctypes.c_ubyte * 0), -] - -rpc_gsp_rm_alloc_v03_00 = struct_rpc_gsp_rm_alloc_v03_00 -rpc_gsp_rm_alloc_v = struct_rpc_gsp_rm_alloc_v03_00 -class struct_rpc_gsp_rm_control_v03_00(Structure): - pass - -struct_rpc_gsp_rm_control_v03_00._pack_ = 1 # source:False -struct_rpc_gsp_rm_control_v03_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('paramsSize', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('params', ctypes.c_ubyte * 0), -] - -rpc_gsp_rm_control_v03_00 = struct_rpc_gsp_rm_control_v03_00 -rpc_gsp_rm_control_v = struct_rpc_gsp_rm_control_v03_00 -class struct_rpc_dump_protobuf_component_v18_12(Structure): - pass - -struct_rpc_dump_protobuf_component_v18_12._pack_ = 1 # source:False -struct_rpc_dump_protobuf_component_v18_12._fields_ = [ - ('component', ctypes.c_uint16), - ('nvDumpType', ctypes.c_ubyte), - ('countOnly', ctypes.c_ubyte), - ('bugCheckCode', ctypes.c_uint32), - ('internalCode', ctypes.c_uint32), - ('bufferSize', ctypes.c_uint32), - ('blob', ctypes.c_ubyte * 0), -] - -rpc_dump_protobuf_component_v18_12 = struct_rpc_dump_protobuf_component_v18_12 -rpc_dump_protobuf_component_v = struct_rpc_dump_protobuf_component_v18_12 -class struct_rpc_run_cpu_sequencer_v17_00(Structure): - pass - -struct_rpc_run_cpu_sequencer_v17_00._pack_ = 1 # source:False -struct_rpc_run_cpu_sequencer_v17_00._fields_ = [ - ('bufferSizeDWord', ctypes.c_uint32), - ('cmdIndex', ctypes.c_uint32), - ('regSaveArea', ctypes.c_uint32 * 8), - ('commandBuffer', ctypes.c_uint32 * 0), -] - -rpc_run_cpu_sequencer_v17_00 = struct_rpc_run_cpu_sequencer_v17_00 -rpc_run_cpu_sequencer_v = struct_rpc_run_cpu_sequencer_v17_00 -class struct_rpc_post_event_v17_00(Structure): - pass - -struct_rpc_post_event_v17_00._pack_ = 1 # source:False -struct_rpc_post_event_v17_00._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hEvent', ctypes.c_uint32), - ('notifyIndex', ctypes.c_uint32), - ('data', ctypes.c_uint32), - ('info16', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('eventDataSize', ctypes.c_uint32), - ('bNotifyList', ctypes.c_ubyte), - ('eventData', ctypes.c_ubyte * 0), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -rpc_post_event_v17_00 = struct_rpc_post_event_v17_00 -rpc_post_event_v = struct_rpc_post_event_v17_00 -class struct_rpc_rc_triggered_v17_02(Structure): - pass - -struct_rpc_rc_triggered_v17_02._pack_ = 1 # source:False -struct_rpc_rc_triggered_v17_02._fields_ = [ - ('nv2080EngineType', ctypes.c_uint32), - ('chid', ctypes.c_uint32), - ('gfid', ctypes.c_uint32), - ('exceptLevel', ctypes.c_uint32), - ('exceptType', ctypes.c_uint32), - ('scope', ctypes.c_uint32), - ('partitionAttributionId', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('mmuFaultAddrLo', ctypes.c_uint32), - ('mmuFaultAddrHi', ctypes.c_uint32), - ('mmuFaultType', ctypes.c_uint32), - ('bCallbackNeeded', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('rcJournalBufferSize', ctypes.c_uint32), - ('rcJournalBuffer', ctypes.c_ubyte * 0), -] - -rpc_rc_triggered_v17_02 = struct_rpc_rc_triggered_v17_02 -rpc_rc_triggered_v = struct_rpc_rc_triggered_v17_02 -class struct_rpc_os_error_log_v17_00(Structure): - pass - -struct_rpc_os_error_log_v17_00._pack_ = 1 # source:False -struct_rpc_os_error_log_v17_00._fields_ = [ - ('exceptType', ctypes.c_uint32), - ('runlistId', ctypes.c_uint32), - ('chid', ctypes.c_uint32), - ('errString', ctypes.c_char * 256), -] - -rpc_os_error_log_v17_00 = struct_rpc_os_error_log_v17_00 -rpc_os_error_log_v = struct_rpc_os_error_log_v17_00 -class struct_rpc_rg_line_intr_v17_00(Structure): - pass - -struct_rpc_rg_line_intr_v17_00._pack_ = 1 # source:False -struct_rpc_rg_line_intr_v17_00._fields_ = [ - ('head', ctypes.c_uint32), - ('rgIntr', ctypes.c_uint32), -] - -rpc_rg_line_intr_v17_00 = struct_rpc_rg_line_intr_v17_00 -rpc_rg_line_intr_v = struct_rpc_rg_line_intr_v17_00 -class struct_rpc_display_modeset_v01_00(Structure): - pass - -struct_rpc_display_modeset_v01_00._pack_ = 1 # source:False -struct_rpc_display_modeset_v01_00._fields_ = [ - ('bModesetStart', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('minRequiredIsoBandwidthKBPS', ctypes.c_uint32), - ('minRequiredFloorBandwidthKBPS', ctypes.c_uint32), -] - -rpc_display_modeset_v01_00 = struct_rpc_display_modeset_v01_00 -rpc_display_modeset_v = struct_rpc_display_modeset_v01_00 -class struct_rpc_gpuacct_perfmon_util_samples_v1F_0E(Structure): - pass - -class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bufSize', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('tracker', ctypes.c_uint32), - ('samples', struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E * 72), -] - -struct_rpc_gpuacct_perfmon_util_samples_v1F_0E._pack_ = 1 # source:False -struct_rpc_gpuacct_perfmon_util_samples_v1F_0E._fields_ = [ - ('params', struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E), -] - -rpc_gpuacct_perfmon_util_samples_v1F_0E = struct_rpc_gpuacct_perfmon_util_samples_v1F_0E -rpc_gpuacct_perfmon_util_samples_v = struct_rpc_gpuacct_perfmon_util_samples_v1F_0E -class struct_rpc_vgpu_gsp_plugin_triggered_v17_00(Structure): - pass - -struct_rpc_vgpu_gsp_plugin_triggered_v17_00._pack_ = 1 # source:False -struct_rpc_vgpu_gsp_plugin_triggered_v17_00._fields_ = [ - ('gfid', ctypes.c_uint32), - ('notifyIndex', ctypes.c_uint32), -] - -rpc_vgpu_gsp_plugin_triggered_v17_00 = struct_rpc_vgpu_gsp_plugin_triggered_v17_00 -rpc_vgpu_gsp_plugin_triggered_v = struct_rpc_vgpu_gsp_plugin_triggered_v17_00 -class struct_rpc_vgpu_config_event_v17_00(Structure): - pass - -struct_rpc_vgpu_config_event_v17_00._pack_ = 1 # source:False -struct_rpc_vgpu_config_event_v17_00._fields_ = [ - ('notifyIndex', ctypes.c_uint32), -] - -rpc_vgpu_config_event_v17_00 = struct_rpc_vgpu_config_event_v17_00 -rpc_vgpu_config_event_v = struct_rpc_vgpu_config_event_v17_00 -class struct_rpc_dce_rm_init_v01_00(Structure): - pass - -struct_rpc_dce_rm_init_v01_00._pack_ = 1 # source:False -struct_rpc_dce_rm_init_v01_00._fields_ = [ - ('bInit', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('hInternalClient', ctypes.c_uint32), -] - -rpc_dce_rm_init_v01_00 = struct_rpc_dce_rm_init_v01_00 -rpc_dce_rm_init_v = struct_rpc_dce_rm_init_v01_00 -class struct_rpc_sim_read_v1E_01(Structure): - pass - -struct_rpc_sim_read_v1E_01._pack_ = 1 # source:False -struct_rpc_sim_read_v1E_01._fields_ = [ - ('path', ctypes.c_char * 256), - ('index', ctypes.c_uint32), - ('count', ctypes.c_uint32), -] - -rpc_sim_read_v1E_01 = struct_rpc_sim_read_v1E_01 -rpc_sim_read_v = struct_rpc_sim_read_v1E_01 -class struct_rpc_sim_write_v1E_01(Structure): - pass - -struct_rpc_sim_write_v1E_01._pack_ = 1 # source:False -struct_rpc_sim_write_v1E_01._fields_ = [ - ('path', ctypes.c_char * 256), - ('index', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -rpc_sim_write_v1E_01 = struct_rpc_sim_write_v1E_01 -rpc_sim_write_v = struct_rpc_sim_write_v1E_01 -class struct_rpc_ucode_libos_print_v1E_08(Structure): - pass - -struct_rpc_ucode_libos_print_v1E_08._pack_ = 1 # source:False -struct_rpc_ucode_libos_print_v1E_08._fields_ = [ - ('ucodeEngDesc', ctypes.c_uint32), - ('libosPrintBufSize', ctypes.c_uint32), - ('libosPrintBuf', ctypes.c_ubyte * 0), -] - -rpc_ucode_libos_print_v1E_08 = struct_rpc_ucode_libos_print_v1E_08 -rpc_ucode_libos_print_v = struct_rpc_ucode_libos_print_v1E_08 -class struct_rpc_init_done_v17_00(Structure): - pass - -struct_rpc_init_done_v17_00._pack_ = 1 # source:False -struct_rpc_init_done_v17_00._fields_ = [ - ('not_used', ctypes.c_uint32), -] - -rpc_init_done_v17_00 = struct_rpc_init_done_v17_00 -rpc_init_done_v = struct_rpc_init_done_v17_00 -class struct_rpc_semaphore_schedule_callback_v17_00(Structure): - pass - -struct_rpc_semaphore_schedule_callback_v17_00._pack_ = 1 # source:False -struct_rpc_semaphore_schedule_callback_v17_00._fields_ = [ - ('GPUVA', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('ReleaseValue', ctypes.c_uint32), - ('Flags', ctypes.c_uint32), - ('completionStatus', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('hEvent', ctypes.c_uint32), -] - -rpc_semaphore_schedule_callback_v17_00 = struct_rpc_semaphore_schedule_callback_v17_00 -rpc_semaphore_schedule_callback_v = struct_rpc_semaphore_schedule_callback_v17_00 -class struct_rpc_timed_semaphore_release_v01_00(Structure): - pass - -struct_rpc_timed_semaphore_release_v01_00._pack_ = 1 # source:False -struct_rpc_timed_semaphore_release_v01_00._fields_ = [ - ('semaphoreVA', ctypes.c_uint64), - ('notifierVA', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('releaseValue', ctypes.c_uint32), - ('completionStatus', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -rpc_timed_semaphore_release_v01_00 = struct_rpc_timed_semaphore_release_v01_00 -rpc_timed_semaphore_release_v = struct_rpc_timed_semaphore_release_v01_00 -class struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00(Structure): - pass - -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00._fields_ = [ - ('flags', ctypes.c_uint32), - ('bBridgeless', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('currLimits', ctypes.c_uint32 * 2), -] - -struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00._pack_ = 1 # source:False -struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00), -] - -rpc_perf_gpu_boost_sync_limits_callback_v17_00 = struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00 -rpc_perf_gpu_boost_sync_limits_callback_v = struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00 -class struct_rpc_perf_bridgeless_info_update_v17_00(Structure): - pass - -struct_rpc_perf_bridgeless_info_update_v17_00._pack_ = 1 # source:False -struct_rpc_perf_bridgeless_info_update_v17_00._fields_ = [ - ('bBridgeless', ctypes.c_uint64), -] - -rpc_perf_bridgeless_info_update_v17_00 = struct_rpc_perf_bridgeless_info_update_v17_00 -rpc_perf_bridgeless_info_update_v = struct_rpc_perf_bridgeless_info_update_v17_00 -class struct_rpc_nvlink_fault_up_v17_00(Structure): - pass - -struct_rpc_nvlink_fault_up_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_fault_up_v17_00._fields_ = [ - ('linkId', ctypes.c_uint32), -] - -rpc_nvlink_fault_up_v17_00 = struct_rpc_nvlink_fault_up_v17_00 -rpc_nvlink_fault_up_v = struct_rpc_nvlink_fault_up_v17_00 -class struct_rpc_nvlink_inband_received_data_256_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00._fields_ = [ - ('dataSize', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 256), -] - -struct_rpc_nvlink_inband_received_data_256_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_inband_received_data_256_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00), -] - -rpc_nvlink_inband_received_data_256_v17_00 = struct_rpc_nvlink_inband_received_data_256_v17_00 -rpc_nvlink_inband_received_data_256_v = struct_rpc_nvlink_inband_received_data_256_v17_00 -class struct_rpc_nvlink_inband_received_data_512_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00._fields_ = [ - ('dataSize', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 512), -] - -struct_rpc_nvlink_inband_received_data_512_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_inband_received_data_512_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00), -] - -rpc_nvlink_inband_received_data_512_v17_00 = struct_rpc_nvlink_inband_received_data_512_v17_00 -rpc_nvlink_inband_received_data_512_v = struct_rpc_nvlink_inband_received_data_512_v17_00 -class struct_rpc_nvlink_inband_received_data_1024_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00._fields_ = [ - ('dataSize', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 1024), -] - -struct_rpc_nvlink_inband_received_data_1024_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_inband_received_data_1024_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00), -] - -rpc_nvlink_inband_received_data_1024_v17_00 = struct_rpc_nvlink_inband_received_data_1024_v17_00 -rpc_nvlink_inband_received_data_1024_v = struct_rpc_nvlink_inband_received_data_1024_v17_00 -class struct_rpc_nvlink_inband_received_data_2048_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00._fields_ = [ - ('dataSize', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 2048), -] - -struct_rpc_nvlink_inband_received_data_2048_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_inband_received_data_2048_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00), -] - -rpc_nvlink_inband_received_data_2048_v17_00 = struct_rpc_nvlink_inband_received_data_2048_v17_00 -rpc_nvlink_inband_received_data_2048_v = struct_rpc_nvlink_inband_received_data_2048_v17_00 -class struct_rpc_nvlink_inband_received_data_4096_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00._fields_ = [ - ('dataSize', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 4096), -] - -struct_rpc_nvlink_inband_received_data_4096_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_inband_received_data_4096_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00), -] - -rpc_nvlink_inband_received_data_4096_v17_00 = struct_rpc_nvlink_inband_received_data_4096_v17_00 -rpc_nvlink_inband_received_data_4096_v = struct_rpc_nvlink_inband_received_data_4096_v17_00 -class struct_rpc_nvlink_is_gpu_degraded_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00._fields_ = [ - ('linkId', ctypes.c_uint32), - ('bIsGpuDegraded', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_rpc_nvlink_is_gpu_degraded_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_is_gpu_degraded_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00), -] - -rpc_nvlink_is_gpu_degraded_v17_00 = struct_rpc_nvlink_is_gpu_degraded_v17_00 -rpc_nvlink_is_gpu_degraded_v = struct_rpc_nvlink_is_gpu_degraded_v17_00 -class struct_rpc_nvlink_fatal_error_recovery_v17_00(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00(Structure): - pass - -struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00._fields_ = [ - ('bRecoverable', ctypes.c_ubyte), - ('bLazy', ctypes.c_ubyte), -] - -struct_rpc_nvlink_fatal_error_recovery_v17_00._pack_ = 1 # source:False -struct_rpc_nvlink_fatal_error_recovery_v17_00._fields_ = [ - ('params', struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00), -] - -rpc_nvlink_fatal_error_recovery_v17_00 = struct_rpc_nvlink_fatal_error_recovery_v17_00 -rpc_nvlink_fatal_error_recovery_v = struct_rpc_nvlink_fatal_error_recovery_v17_00 -class struct_rpc_update_gsp_trace_v01_00(Structure): - pass - -struct_rpc_update_gsp_trace_v01_00._pack_ = 1 # source:False -struct_rpc_update_gsp_trace_v01_00._fields_ = [ - ('records', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - -rpc_update_gsp_trace_v01_00 = struct_rpc_update_gsp_trace_v01_00 -rpc_update_gsp_trace_v = struct_rpc_update_gsp_trace_v01_00 -class struct_rpc_gsp_post_nocat_record_v01_00(Structure): - pass - -struct_rpc_gsp_post_nocat_record_v01_00._pack_ = 1 # source:False -struct_rpc_gsp_post_nocat_record_v01_00._fields_ = [ - ('data', ctypes.c_uint32), -] - -rpc_gsp_post_nocat_record_v01_00 = struct_rpc_gsp_post_nocat_record_v01_00 -rpc_gsp_post_nocat_record_v = struct_rpc_gsp_post_nocat_record_v01_00 -class struct_rpc_extdev_intr_service_v17_00(Structure): - pass - -struct_rpc_extdev_intr_service_v17_00._pack_ = 1 # source:False -struct_rpc_extdev_intr_service_v17_00._fields_ = [ - ('lossRegStatus', ctypes.c_ubyte), - ('gainRegStatus', ctypes.c_ubyte), - ('miscRegStatus', ctypes.c_ubyte), - ('rmStatus', ctypes.c_ubyte), -] - -rpc_extdev_intr_service_v17_00 = struct_rpc_extdev_intr_service_v17_00 -rpc_extdev_intr_service_v = struct_rpc_extdev_intr_service_v17_00 -class struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04(Structure): - pass - -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04(Structure): - pass - -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(Union): - pass - -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04._fields_ = [ - ('sensorId', ctypes.c_uint32), - ('limit', ctypes.c_uint32), -] - -union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04._pack_ = 1 # source:False -union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04._fields_ = [ - ('smbpbi', struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04), -] - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('data', union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04), -] - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04._fields_ = [ - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('syncData', struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04), -] - -struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04._pack_ = 1 # source:False -struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04._fields_ = [ - ('params', struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04), -] - -rpc_pfm_req_hndlr_state_sync_callback_v21_04 = struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04 -rpc_pfm_req_hndlr_state_sync_callback_v = struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04 -class struct_rpc_vgpu_gsp_mig_ci_config_v21_03(Structure): - pass - -struct_rpc_vgpu_gsp_mig_ci_config_v21_03._pack_ = 1 # source:False -struct_rpc_vgpu_gsp_mig_ci_config_v21_03._fields_ = [ - ('execPartCount', ctypes.c_uint32), - ('execPartId', ctypes.c_uint32 * 8), - ('gfid', ctypes.c_uint32), - ('bDelete', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_vgpu_gsp_mig_ci_config_v21_03 = struct_rpc_vgpu_gsp_mig_ci_config_v21_03 -rpc_vgpu_gsp_mig_ci_config_v = struct_rpc_vgpu_gsp_mig_ci_config_v21_03 -class struct_rpc_gsp_lockdown_notice_v17_00(Structure): - pass - -struct_rpc_gsp_lockdown_notice_v17_00._pack_ = 1 # source:False -struct_rpc_gsp_lockdown_notice_v17_00._fields_ = [ - ('bLockdownEngaging', ctypes.c_ubyte), -] - -rpc_gsp_lockdown_notice_v17_00 = struct_rpc_gsp_lockdown_notice_v17_00 -rpc_gsp_lockdown_notice_v = struct_rpc_gsp_lockdown_notice_v17_00 -class struct_rpc_ctrl_gpu_query_ecc_status_v24_06(Structure): - pass - -class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06(Structure): - pass - -class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01(Structure): - pass - -class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01._fields_ = [ - ('count', ctypes.c_uint64), -] - -struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01._fields_ = [ - ('enabled', ctypes.c_ubyte), - ('scrubComplete', ctypes.c_ubyte), - ('supported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 5), - ('dbe', struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), - ('dbeNonResettable', struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), - ('sbe', struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), - ('sbeNonResettable', struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01), -] - -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06._fields_ = [ - ('units', struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 * 25), - ('bFatalPoisonError', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('flags', ctypes.c_uint32), -] - -struct_rpc_ctrl_gpu_query_ecc_status_v24_06._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_query_ecc_status_v24_06._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06), -] - -rpc_ctrl_gpu_query_ecc_status_v24_06 = struct_rpc_ctrl_gpu_query_ecc_status_v24_06 -class struct_rpc_ctrl_gpu_query_ecc_status_v26_02(Structure): - pass - -class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02._fields_ = [ - ('units', struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 * 30), - ('bFatalPoisonError', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('flags', ctypes.c_uint32), -] - -struct_rpc_ctrl_gpu_query_ecc_status_v26_02._pack_ = 1 # source:False -struct_rpc_ctrl_gpu_query_ecc_status_v26_02._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02), -] - -rpc_ctrl_gpu_query_ecc_status_v26_02 = struct_rpc_ctrl_gpu_query_ecc_status_v26_02 -rpc_ctrl_gpu_query_ecc_status_v = struct_rpc_ctrl_gpu_query_ecc_status_v26_02 -class struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04._fields_ = [ - ('value', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04), -] - -rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 = struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 -rpc_ctrl_dbg_get_mode_mmu_debug_v = struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 -class struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07(Structure): - pass - -class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07._pack_ = 1 # source:False -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07._fields_ = [ - ('value', ctypes.c_uint32), -] - -struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07._pack_ = 1 # source:False -struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07), -] - -rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07 = struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07 -rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v = struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07 -class struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09(Structure): - pass - -struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09._pack_ = 1 # source:False -struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09._fields_ = [ - ('bwMode', ctypes.c_ubyte), -] - -rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 = struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 -rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v = struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 -class struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C(Structure): - pass - -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C._pack_ = 1 # source:False -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C._fields_ = [ - ('dataSize', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 512), -] - -struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C._pack_ = 1 # source:False -struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C._fields_ = [ - ('message_type', ctypes.c_uint16), - ('more', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('payload', struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C), -] - -rpc_ctrl_nvlink_get_inband_received_data_v25_0C = struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C -rpc_ctrl_nvlink_get_inband_received_data_v = struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C -class struct_rpc_fecs_error_v26_02(Structure): - pass - -struct_rpc_fecs_error_v26_02._pack_ = 1 # source:False -struct_rpc_fecs_error_v26_02._fields_ = [ - ('grIdx', ctypes.c_uint32), - ('error_type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_fecs_error_v26_02 = struct_rpc_fecs_error_v26_02 -rpc_fecs_error_v = struct_rpc_fecs_error_v26_02 -class struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05(Structure): - pass - -struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05._pack_ = 1 # source:False -struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05._fields_ = [ - ('buffer', ctypes.c_ubyte * 1024), - ('dataSize', ctypes.c_uint32), -] - -rpc_ctrl_cmd_nvlink_inband_send_data_v26_05 = struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05 -rpc_ctrl_cmd_nvlink_inband_send_data_v = struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05 -class struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00(Structure): - pass - -struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00._pack_ = 1 # source:False -struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00._fields_ = [ - ('bufferSize', ctypes.c_uint32), - ('tracepointMask', ctypes.c_uint32), - ('bufferWatermark', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bufferAddr', ctypes.c_uint64), - ('flag', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -rpc_ctrl_cmd_internal_control_gsp_trace_v28_00 = struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00 -rpc_ctrl_cmd_internal_control_gsp_trace_v = struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00 -class struct_rpc_recovery_action_v28_01(Structure): - pass - -struct_rpc_recovery_action_v28_01._pack_ = 1 # source:False -struct_rpc_recovery_action_v28_01._fields_ = [ - ('type', ctypes.c_uint32), - ('value', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -rpc_recovery_action_v28_01 = struct_rpc_recovery_action_v28_01 -rpc_recovery_action_v = struct_rpc_recovery_action_v28_01 -class struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02(Structure): - pass - -class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02(Structure): - pass - -class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02(Structure): - pass - -struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02._pack_ = 1 # source:False -struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02._fields_ = [ - ('allocations', ctypes.c_uint32), - ('peakAllocations', ctypes.c_uint32), - ('objectSize', ctypes.c_uint64), -] - -struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02._fields_ = [ - ('poolStats', struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02 * 64), - ('totalHeapSize', ctypes.c_uint64), - ('poolCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02._pack_ = 1 # source:False -struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('ctrlParams', struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02), -] - -rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 = struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 -rpc_ctrl_subdevice_get_libos_heap_stats_v = struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 -FSP_NVDM_FORMAT_H = True # macro -NVDM_TYPE_HULK = 0x11 # macro -NVDM_TYPE_FIRMWARE_UPDATE = 0x12 # macro -NVDM_TYPE_PRC = 0x13 # macro -NVDM_TYPE_COT = 0x14 # macro -NVDM_TYPE_FSP_RESPONSE = 0x15 # macro -NVDM_TYPE_CAPS_QUERY = 0x16 # macro -NVDM_TYPE_INFOROM = 0x17 # macro -NVDM_TYPE_SMBPBI = 0x18 # macro -NVDM_TYPE_ROMREAD = 0x1A # macro -NVDM_TYPE_UEFI_RM = 0x1C # macro -NVDM_TYPE_UEFI_XTL_DEBUG_INTR = 0x1D # macro -NVDM_TYPE_TNVL = 0x1F # macro -NVDM_TYPE_CLOCK_BOOST = 0x20 # macro -NVDM_TYPE_FSP_GSP_COMM = 0x21 # macro -class struct_GSP_MSG_QUEUE_ELEMENT(Structure): - pass - -struct_GSP_MSG_QUEUE_ELEMENT._pack_ = 1 # source:False -struct_GSP_MSG_QUEUE_ELEMENT._fields_ = [ - ('authTagBuffer', ctypes.c_ubyte * 16), - ('aadBuffer', ctypes.c_ubyte * 16), - ('checkSum', ctypes.c_uint32), - ('seqNum', ctypes.c_uint32), - ('elemCount', ctypes.c_uint32), - ('padding', ctypes.c_uint32), -] - -GSP_MSG_QUEUE_ELEMENT = struct_GSP_MSG_QUEUE_ELEMENT -class union_rpc_message_rpc_union_field_v03_00(Union): - pass - -union_rpc_message_rpc_union_field_v03_00._pack_ = 1 # source:False -union_rpc_message_rpc_union_field_v03_00._fields_ = [ - ('spare', ctypes.c_uint32), - ('cpuRmGfid', ctypes.c_uint32), -] - -rpc_message_rpc_union_field_v03_00 = union_rpc_message_rpc_union_field_v03_00 -rpc_message_rpc_union_field_v = union_rpc_message_rpc_union_field_v03_00 -class struct_rpc_message_header_v03_00(Structure): - pass - -struct_rpc_message_header_v03_00._pack_ = 1 # source:False -struct_rpc_message_header_v03_00._fields_ = [ - ('header_version', ctypes.c_uint32), - ('signature', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('function', ctypes.c_uint32), - ('rpc_result', ctypes.c_uint32), - ('rpc_result_private', ctypes.c_uint32), - ('sequence', ctypes.c_uint32), - ('u', rpc_message_rpc_union_field_v), -] - -rpc_message_header_v03_00 = struct_rpc_message_header_v03_00 -rpc_message_header_v = struct_rpc_message_header_v03_00 -GSP_STATIC_CONFIG_H = True # macro -MAX_DSM_SUPPORTED_FUNCS_RTN_LEN = 8 # macro -NV_ACPI_GENERIC_FUNC_COUNT = 8 # macro -REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN = 0 # macro -REGISTRY_TABLE_ENTRY_TYPE_DWORD = 1 # macro -REGISTRY_TABLE_ENTRY_TYPE_BINARY = 2 # macro -REGISTRY_TABLE_ENTRY_TYPE_STRING = 3 # macro -MAX_GROUP_COUNT = 2 # macro -RM_ENGINE_TYPE_COPY_SIZE = 20 # macro -RM_ENGINE_TYPE_NVENC_SIZE = 4 # macro -RM_ENGINE_TYPE_NVJPEG_SIZE = 8 # macro -RM_ENGINE_TYPE_NVDEC_SIZE = 8 # macro -RM_ENGINE_TYPE_OFA_SIZE = 2 # macro -RM_ENGINE_TYPE_GR_SIZE = 8 # macro -NVGPU_ENGINE_CAPS_MASK_BITS = 32 # macro -# def NVGPU_GET_ENGINE_CAPS_MASK(caps, id): # macro -# return (caps[(id)/32]&NVBIT((id)%32)) -# def NVGPU_SET_ENGINE_CAPS_MASK(caps, id): # macro -# return (caps[(id)/32]|=NVBIT((id)%32)) -class struct_PACKED_REGISTRY_ENTRY(Structure): - pass - -struct_PACKED_REGISTRY_ENTRY._pack_ = 1 # source:False -struct_PACKED_REGISTRY_ENTRY._fields_ = [ - ('nameOffset', ctypes.c_uint32), - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('data', ctypes.c_uint32), - ('length', ctypes.c_uint32), -] - -PACKED_REGISTRY_ENTRY = struct_PACKED_REGISTRY_ENTRY -class struct_PACKED_REGISTRY_TABLE(Structure): - pass - -struct_PACKED_REGISTRY_TABLE._pack_ = 1 # source:False -struct_PACKED_REGISTRY_TABLE._fields_ = [ - ('size', ctypes.c_uint32), - ('numEntries', ctypes.c_uint32), -] - -PACKED_REGISTRY_TABLE = struct_PACKED_REGISTRY_TABLE - -# values for enumeration 'c__EA_DISPMUXSTATE' -c__EA_DISPMUXSTATE__enumvalues = { - 0: 'dispMuxState_None', - 1: 'dispMuxState_IntegratedGPU', - 2: 'dispMuxState_DiscreteGPU', -} -dispMuxState_None = 0 -dispMuxState_IntegratedGPU = 1 -dispMuxState_DiscreteGPU = 2 -c__EA_DISPMUXSTATE = ctypes.c_uint32 # enum -DISPMUXSTATE = c__EA_DISPMUXSTATE -DISPMUXSTATE__enumvalues = c__EA_DISPMUXSTATE__enumvalues -class struct_c__SA_ACPI_DSM_CACHE(Structure): - pass - -struct_c__SA_ACPI_DSM_CACHE._pack_ = 1 # source:False -struct_c__SA_ACPI_DSM_CACHE._fields_ = [ - ('suppFuncStatus', ctypes.c_uint32), - ('suppFuncs', ctypes.c_ubyte * 8), - ('suppFuncsLen', ctypes.c_uint32), - ('bArg3isInteger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('callbackStatus', ctypes.c_uint32), - ('callback', ctypes.c_uint32), -] - -ACPI_DSM_CACHE = struct_c__SA_ACPI_DSM_CACHE -class struct_c__SA_ACPI_DATA(Structure): - pass - - -# values for enumeration '_ACPI_DSM_FUNCTION' -_ACPI_DSM_FUNCTION__enumvalues = { - 0: 'ACPI_DSM_FUNCTION_NBSI', - 1: 'ACPI_DSM_FUNCTION_NVHG', - 2: 'ACPI_DSM_FUNCTION_MXM', - 3: 'ACPI_DSM_FUNCTION_NBCI', - 4: 'ACPI_DSM_FUNCTION_NVOP', - 5: 'ACPI_DSM_FUNCTION_PCFG', - 6: 'ACPI_DSM_FUNCTION_GPS_2X', - 7: 'ACPI_DSM_FUNCTION_JT', - 8: 'ACPI_DSM_FUNCTION_PEX', - 9: 'ACPI_DSM_FUNCTION_NVPCF_2X', - 10: 'ACPI_DSM_FUNCTION_GPS', - 11: 'ACPI_DSM_FUNCTION_NVPCF', - 12: 'ACPI_DSM_FUNCTION_COUNT', - 13: 'ACPI_DSM_FUNCTION_CURRENT', - 255: 'ACPI_DSM_FUNCTION_INVALID', -} -ACPI_DSM_FUNCTION_NBSI = 0 -ACPI_DSM_FUNCTION_NVHG = 1 -ACPI_DSM_FUNCTION_MXM = 2 -ACPI_DSM_FUNCTION_NBCI = 3 -ACPI_DSM_FUNCTION_NVOP = 4 -ACPI_DSM_FUNCTION_PCFG = 5 -ACPI_DSM_FUNCTION_GPS_2X = 6 -ACPI_DSM_FUNCTION_JT = 7 -ACPI_DSM_FUNCTION_PEX = 8 -ACPI_DSM_FUNCTION_NVPCF_2X = 9 -ACPI_DSM_FUNCTION_GPS = 10 -ACPI_DSM_FUNCTION_NVPCF = 11 -ACPI_DSM_FUNCTION_COUNT = 12 -ACPI_DSM_FUNCTION_CURRENT = 13 -ACPI_DSM_FUNCTION_INVALID = 255 -_ACPI_DSM_FUNCTION = ctypes.c_uint32 # enum -struct_c__SA_ACPI_DATA._pack_ = 1 # source:False -struct_c__SA_ACPI_DATA._fields_ = [ - ('dsm', struct_c__SA_ACPI_DSM_CACHE * 12), - ('dispStatusHotplugFunc', _ACPI_DSM_FUNCTION), - ('dispStatusConfigFunc', _ACPI_DSM_FUNCTION), - ('perfPostPowerStateFunc', _ACPI_DSM_FUNCTION), - ('stereo3dStateActiveFunc', _ACPI_DSM_FUNCTION), - ('dsmPlatCapsCache', ctypes.c_uint32 * 12), - ('MDTLFeatureSupport', ctypes.c_uint32), - ('dsmCurrentFunc', _ACPI_DSM_FUNCTION * 8), - ('dsmCurrentSubFunc', ctypes.c_uint32 * 8), - ('dsmCurrentFuncSupport', ctypes.c_uint32), -] - -ACPI_DATA = struct_c__SA_ACPI_DATA -class struct_DOD_METHOD_DATA(Structure): - pass - -struct_DOD_METHOD_DATA._pack_ = 1 # source:False -struct_DOD_METHOD_DATA._fields_ = [ - ('status', ctypes.c_uint32), - ('acpiIdListLen', ctypes.c_uint32), - ('acpiIdList', ctypes.c_uint32 * 16), -] - -DOD_METHOD_DATA = struct_DOD_METHOD_DATA -class struct_JT_METHOD_DATA(Structure): - pass - -struct_JT_METHOD_DATA._pack_ = 1 # source:False -struct_JT_METHOD_DATA._fields_ = [ - ('status', ctypes.c_uint32), - ('jtCaps', ctypes.c_uint32), - ('jtRevId', ctypes.c_uint16), - ('bSBIOSCaps', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -JT_METHOD_DATA = struct_JT_METHOD_DATA -class struct_MUX_METHOD_DATA_ELEMENT(Structure): - pass - -struct_MUX_METHOD_DATA_ELEMENT._pack_ = 1 # source:False -struct_MUX_METHOD_DATA_ELEMENT._fields_ = [ - ('acpiId', ctypes.c_uint32), - ('mode', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -MUX_METHOD_DATA_ELEMENT = struct_MUX_METHOD_DATA_ELEMENT -class struct_MUX_METHOD_DATA(Structure): - pass - -struct_MUX_METHOD_DATA._pack_ = 1 # source:False -struct_MUX_METHOD_DATA._fields_ = [ - ('tableLen', ctypes.c_uint32), - ('acpiIdMuxModeTable', struct_MUX_METHOD_DATA_ELEMENT * 16), - ('acpiIdMuxPartTable', struct_MUX_METHOD_DATA_ELEMENT * 16), - ('acpiIdMuxStateTable', struct_MUX_METHOD_DATA_ELEMENT * 16), -] - -MUX_METHOD_DATA = struct_MUX_METHOD_DATA -class struct_CAPS_METHOD_DATA(Structure): - pass - -struct_CAPS_METHOD_DATA._pack_ = 1 # source:False -struct_CAPS_METHOD_DATA._fields_ = [ - ('status', ctypes.c_uint32), - ('optimusCaps', ctypes.c_uint32), -] - -CAPS_METHOD_DATA = struct_CAPS_METHOD_DATA -class struct_ACPI_METHOD_DATA(Structure): - pass - -struct_ACPI_METHOD_DATA._pack_ = 1 # source:False -struct_ACPI_METHOD_DATA._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('dodMethodData', DOD_METHOD_DATA), - ('jtMethodData', JT_METHOD_DATA), - ('muxMethodData', MUX_METHOD_DATA), - ('capsMethodData', CAPS_METHOD_DATA), -] - -ACPI_METHOD_DATA = struct_ACPI_METHOD_DATA - -# values for enumeration 'c__EA_RM_ENGINE_TYPE' -c__EA_RM_ENGINE_TYPE__enumvalues = { - 0: 'RM_ENGINE_TYPE_NULL', - 1: 'RM_ENGINE_TYPE_GR0', - 2: 'RM_ENGINE_TYPE_GR1', - 3: 'RM_ENGINE_TYPE_GR2', - 4: 'RM_ENGINE_TYPE_GR3', - 5: 'RM_ENGINE_TYPE_GR4', - 6: 'RM_ENGINE_TYPE_GR5', - 7: 'RM_ENGINE_TYPE_GR6', - 8: 'RM_ENGINE_TYPE_GR7', - 9: 'RM_ENGINE_TYPE_COPY0', - 10: 'RM_ENGINE_TYPE_COPY1', - 11: 'RM_ENGINE_TYPE_COPY2', - 12: 'RM_ENGINE_TYPE_COPY3', - 13: 'RM_ENGINE_TYPE_COPY4', - 14: 'RM_ENGINE_TYPE_COPY5', - 15: 'RM_ENGINE_TYPE_COPY6', - 16: 'RM_ENGINE_TYPE_COPY7', - 17: 'RM_ENGINE_TYPE_COPY8', - 18: 'RM_ENGINE_TYPE_COPY9', - 19: 'RM_ENGINE_TYPE_COPY10', - 20: 'RM_ENGINE_TYPE_COPY11', - 21: 'RM_ENGINE_TYPE_COPY12', - 22: 'RM_ENGINE_TYPE_COPY13', - 23: 'RM_ENGINE_TYPE_COPY14', - 24: 'RM_ENGINE_TYPE_COPY15', - 25: 'RM_ENGINE_TYPE_COPY16', - 26: 'RM_ENGINE_TYPE_COPY17', - 27: 'RM_ENGINE_TYPE_COPY18', - 28: 'RM_ENGINE_TYPE_COPY19', - 29: 'RM_ENGINE_TYPE_NVDEC0', - 30: 'RM_ENGINE_TYPE_NVDEC1', - 31: 'RM_ENGINE_TYPE_NVDEC2', - 32: 'RM_ENGINE_TYPE_NVDEC3', - 33: 'RM_ENGINE_TYPE_NVDEC4', - 34: 'RM_ENGINE_TYPE_NVDEC5', - 35: 'RM_ENGINE_TYPE_NVDEC6', - 36: 'RM_ENGINE_TYPE_NVDEC7', - 37: 'RM_ENGINE_TYPE_NVENC0', - 38: 'RM_ENGINE_TYPE_NVENC1', - 39: 'RM_ENGINE_TYPE_NVENC2', - 40: 'RM_ENGINE_TYPE_NVENC3', - 41: 'RM_ENGINE_TYPE_VP', - 42: 'RM_ENGINE_TYPE_ME', - 43: 'RM_ENGINE_TYPE_PPP', - 44: 'RM_ENGINE_TYPE_MPEG', - 45: 'RM_ENGINE_TYPE_SW', - 46: 'RM_ENGINE_TYPE_TSEC', - 47: 'RM_ENGINE_TYPE_VIC', - 48: 'RM_ENGINE_TYPE_MP', - 49: 'RM_ENGINE_TYPE_SEC2', - 50: 'RM_ENGINE_TYPE_HOST', - 51: 'RM_ENGINE_TYPE_DPU', - 52: 'RM_ENGINE_TYPE_PMU', - 53: 'RM_ENGINE_TYPE_FBFLCN', - 54: 'RM_ENGINE_TYPE_NVJPEG0', - 55: 'RM_ENGINE_TYPE_NVJPEG1', - 56: 'RM_ENGINE_TYPE_NVJPEG2', - 57: 'RM_ENGINE_TYPE_NVJPEG3', - 58: 'RM_ENGINE_TYPE_NVJPEG4', - 59: 'RM_ENGINE_TYPE_NVJPEG5', - 60: 'RM_ENGINE_TYPE_NVJPEG6', - 61: 'RM_ENGINE_TYPE_NVJPEG7', - 62: 'RM_ENGINE_TYPE_OFA0', - 63: 'RM_ENGINE_TYPE_OFA1', - 64: 'RM_ENGINE_TYPE_RESERVED40', - 65: 'RM_ENGINE_TYPE_RESERVED41', - 66: 'RM_ENGINE_TYPE_RESERVED42', - 67: 'RM_ENGINE_TYPE_RESERVED43', - 68: 'RM_ENGINE_TYPE_RESERVED44', - 69: 'RM_ENGINE_TYPE_RESERVED45', - 70: 'RM_ENGINE_TYPE_RESERVED46', - 71: 'RM_ENGINE_TYPE_RESERVED47', - 72: 'RM_ENGINE_TYPE_RESERVED48', - 73: 'RM_ENGINE_TYPE_RESERVED49', - 74: 'RM_ENGINE_TYPE_RESERVED4a', - 75: 'RM_ENGINE_TYPE_RESERVED4b', - 76: 'RM_ENGINE_TYPE_RESERVED4c', - 77: 'RM_ENGINE_TYPE_RESERVED4d', - 78: 'RM_ENGINE_TYPE_RESERVED4e', - 79: 'RM_ENGINE_TYPE_RESERVED4f', - 80: 'RM_ENGINE_TYPE_RESERVED50', - 81: 'RM_ENGINE_TYPE_RESERVED51', - 82: 'RM_ENGINE_TYPE_RESERVED52', - 83: 'RM_ENGINE_TYPE_RESERVED53', - 84: 'RM_ENGINE_TYPE_LAST', -} -RM_ENGINE_TYPE_NULL = 0 -RM_ENGINE_TYPE_GR0 = 1 -RM_ENGINE_TYPE_GR1 = 2 -RM_ENGINE_TYPE_GR2 = 3 -RM_ENGINE_TYPE_GR3 = 4 -RM_ENGINE_TYPE_GR4 = 5 -RM_ENGINE_TYPE_GR5 = 6 -RM_ENGINE_TYPE_GR6 = 7 -RM_ENGINE_TYPE_GR7 = 8 -RM_ENGINE_TYPE_COPY0 = 9 -RM_ENGINE_TYPE_COPY1 = 10 -RM_ENGINE_TYPE_COPY2 = 11 -RM_ENGINE_TYPE_COPY3 = 12 -RM_ENGINE_TYPE_COPY4 = 13 -RM_ENGINE_TYPE_COPY5 = 14 -RM_ENGINE_TYPE_COPY6 = 15 -RM_ENGINE_TYPE_COPY7 = 16 -RM_ENGINE_TYPE_COPY8 = 17 -RM_ENGINE_TYPE_COPY9 = 18 -RM_ENGINE_TYPE_COPY10 = 19 -RM_ENGINE_TYPE_COPY11 = 20 -RM_ENGINE_TYPE_COPY12 = 21 -RM_ENGINE_TYPE_COPY13 = 22 -RM_ENGINE_TYPE_COPY14 = 23 -RM_ENGINE_TYPE_COPY15 = 24 -RM_ENGINE_TYPE_COPY16 = 25 -RM_ENGINE_TYPE_COPY17 = 26 -RM_ENGINE_TYPE_COPY18 = 27 -RM_ENGINE_TYPE_COPY19 = 28 -RM_ENGINE_TYPE_NVDEC0 = 29 -RM_ENGINE_TYPE_NVDEC1 = 30 -RM_ENGINE_TYPE_NVDEC2 = 31 -RM_ENGINE_TYPE_NVDEC3 = 32 -RM_ENGINE_TYPE_NVDEC4 = 33 -RM_ENGINE_TYPE_NVDEC5 = 34 -RM_ENGINE_TYPE_NVDEC6 = 35 -RM_ENGINE_TYPE_NVDEC7 = 36 -RM_ENGINE_TYPE_NVENC0 = 37 -RM_ENGINE_TYPE_NVENC1 = 38 -RM_ENGINE_TYPE_NVENC2 = 39 -RM_ENGINE_TYPE_NVENC3 = 40 -RM_ENGINE_TYPE_VP = 41 -RM_ENGINE_TYPE_ME = 42 -RM_ENGINE_TYPE_PPP = 43 -RM_ENGINE_TYPE_MPEG = 44 -RM_ENGINE_TYPE_SW = 45 -RM_ENGINE_TYPE_TSEC = 46 -RM_ENGINE_TYPE_VIC = 47 -RM_ENGINE_TYPE_MP = 48 -RM_ENGINE_TYPE_SEC2 = 49 -RM_ENGINE_TYPE_HOST = 50 -RM_ENGINE_TYPE_DPU = 51 -RM_ENGINE_TYPE_PMU = 52 -RM_ENGINE_TYPE_FBFLCN = 53 -RM_ENGINE_TYPE_NVJPEG0 = 54 -RM_ENGINE_TYPE_NVJPEG1 = 55 -RM_ENGINE_TYPE_NVJPEG2 = 56 -RM_ENGINE_TYPE_NVJPEG3 = 57 -RM_ENGINE_TYPE_NVJPEG4 = 58 -RM_ENGINE_TYPE_NVJPEG5 = 59 -RM_ENGINE_TYPE_NVJPEG6 = 60 -RM_ENGINE_TYPE_NVJPEG7 = 61 -RM_ENGINE_TYPE_OFA0 = 62 -RM_ENGINE_TYPE_OFA1 = 63 -RM_ENGINE_TYPE_RESERVED40 = 64 -RM_ENGINE_TYPE_RESERVED41 = 65 -RM_ENGINE_TYPE_RESERVED42 = 66 -RM_ENGINE_TYPE_RESERVED43 = 67 -RM_ENGINE_TYPE_RESERVED44 = 68 -RM_ENGINE_TYPE_RESERVED45 = 69 -RM_ENGINE_TYPE_RESERVED46 = 70 -RM_ENGINE_TYPE_RESERVED47 = 71 -RM_ENGINE_TYPE_RESERVED48 = 72 -RM_ENGINE_TYPE_RESERVED49 = 73 -RM_ENGINE_TYPE_RESERVED4a = 74 -RM_ENGINE_TYPE_RESERVED4b = 75 -RM_ENGINE_TYPE_RESERVED4c = 76 -RM_ENGINE_TYPE_RESERVED4d = 77 -RM_ENGINE_TYPE_RESERVED4e = 78 -RM_ENGINE_TYPE_RESERVED4f = 79 -RM_ENGINE_TYPE_RESERVED50 = 80 -RM_ENGINE_TYPE_RESERVED51 = 81 -RM_ENGINE_TYPE_RESERVED52 = 82 -RM_ENGINE_TYPE_RESERVED53 = 83 -RM_ENGINE_TYPE_LAST = 84 -c__EA_RM_ENGINE_TYPE = ctypes.c_uint32 # enum -RM_ENGINE_TYPE_GRAPHICS = RM_ENGINE_TYPE_GR0 # macro -RM_ENGINE_TYPE_BSP = RM_ENGINE_TYPE_NVDEC0 # macro -RM_ENGINE_TYPE_MSENC = RM_ENGINE_TYPE_NVENC0 # macro -RM_ENGINE_TYPE_CIPHER = RM_ENGINE_TYPE_TSEC # macro -RM_ENGINE_TYPE_NVJPG = RM_ENGINE_TYPE_NVJPEG0 # macro -NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX = ((RM_ENGINE_TYPE_LAST-1)/32+1) # macro -RM_ENGINE_TYPE = c__EA_RM_ENGINE_TYPE -RM_ENGINE_TYPE__enumvalues = c__EA_RM_ENGINE_TYPE__enumvalues -class struct_c__SA_BUSINFO(Structure): - pass - -struct_c__SA_BUSINFO._pack_ = 1 # source:False -struct_c__SA_BUSINFO._fields_ = [ - ('deviceID', ctypes.c_uint16), - ('vendorID', ctypes.c_uint16), - ('subdeviceID', ctypes.c_uint16), - ('subvendorID', ctypes.c_uint16), - ('revisionID', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -BUSINFO = struct_c__SA_BUSINFO -class struct_GSP_VF_INFO(Structure): - pass - -struct_GSP_VF_INFO._pack_ = 1 # source:False -struct_GSP_VF_INFO._fields_ = [ - ('totalVFs', ctypes.c_uint32), - ('firstVFOffset', ctypes.c_uint32), - ('FirstVFBar0Address', ctypes.c_uint64), - ('FirstVFBar1Address', ctypes.c_uint64), - ('FirstVFBar2Address', ctypes.c_uint64), - ('b64bitBar0', ctypes.c_ubyte), - ('b64bitBar1', ctypes.c_ubyte), - ('b64bitBar2', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 5), -] - -GSP_VF_INFO = struct_GSP_VF_INFO -class struct_c__SA_GSP_PCIE_CONFIG_REG(Structure): - pass - -struct_c__SA_GSP_PCIE_CONFIG_REG._pack_ = 1 # source:False -struct_c__SA_GSP_PCIE_CONFIG_REG._fields_ = [ - ('linkCap', ctypes.c_uint32), -] - -GSP_PCIE_CONFIG_REG = struct_c__SA_GSP_PCIE_CONFIG_REG -class struct_c__SA_EcidManufacturingInfo(Structure): - pass - -struct_c__SA_EcidManufacturingInfo._pack_ = 1 # source:False -struct_c__SA_EcidManufacturingInfo._fields_ = [ - ('ecidLow', ctypes.c_uint32), - ('ecidHigh', ctypes.c_uint32), - ('ecidExtended', ctypes.c_uint32), -] - -EcidManufacturingInfo = struct_c__SA_EcidManufacturingInfo -class struct_c__SA_FW_WPR_LAYOUT_OFFSET(Structure): - pass - -struct_c__SA_FW_WPR_LAYOUT_OFFSET._pack_ = 1 # source:False -struct_c__SA_FW_WPR_LAYOUT_OFFSET._fields_ = [ - ('nonWprHeapOffset', ctypes.c_uint64), - ('frtsOffset', ctypes.c_uint64), -] - -FW_WPR_LAYOUT_OFFSET = struct_c__SA_FW_WPR_LAYOUT_OFFSET -class struct_GspStaticConfigInfo_t(Structure): - pass - -class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._fields_ = [ - ('index', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 256), -] - -class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._fields_ = [ - ('BoardID', ctypes.c_uint32), - ('chipSKU', ctypes.c_char * 9), - ('chipSKUMod', ctypes.c_char * 5), - ('PADDING_0', ctypes.c_ubyte * 2), - ('skuConfigVersion', ctypes.c_uint32), - ('project', ctypes.c_char * 5), - ('projectSKU', ctypes.c_char * 5), - ('CDP', ctypes.c_char * 6), - ('projectSKUMod', ctypes.c_char * 2), - ('PADDING_1', ctypes.c_ubyte * 2), - ('businessCycle', ctypes.c_uint32), -] - -class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._fields_ = [ - ('base', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('reserved', ctypes.c_uint64), - ('performance', ctypes.c_uint32), - ('supportCompressed', ctypes.c_ubyte), - ('supportISO', ctypes.c_ubyte), - ('bProtected', ctypes.c_ubyte), - ('blackList', ctypes.c_ubyte * 17), -] - -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._fields_ = [ - ('numFBRegions', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbRegion', struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO * 16), -] - -class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._fields_ = [ - ('totalVFs', ctypes.c_uint32), - ('firstVfOffset', ctypes.c_uint32), - ('vfFeatureMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('FirstVFBar0Address', ctypes.c_uint64), - ('FirstVFBar1Address', ctypes.c_uint64), - ('FirstVFBar2Address', ctypes.c_uint64), - ('bar0Size', ctypes.c_uint64), - ('bar1Size', ctypes.c_uint64), - ('bar2Size', ctypes.c_uint64), - ('b64bitBar0', ctypes.c_ubyte), - ('b64bitBar1', ctypes.c_ubyte), - ('b64bitBar2', ctypes.c_ubyte), - ('bSriovEnabled', ctypes.c_ubyte), - ('bSriovHeavyEnabled', ctypes.c_ubyte), - ('bEmulateVFBar0TlbInvalidationRegister', ctypes.c_ubyte), - ('bClientRmAllocatedCtxBuffer', ctypes.c_ubyte), - ('bNonPowerOf2ChannelCountSupported', ctypes.c_ubyte), - ('bVfResizableBAR1Supported', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -struct_GspStaticConfigInfo_t._pack_ = 1 # source:False -struct_GspStaticConfigInfo_t._fields_ = [ - ('grCapsBits', ctypes.c_ubyte * 23), - ('PADDING_0', ctypes.c_ubyte), - ('gidInfo', struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS), - ('SKUInfo', struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), - ('PADDING_1', ctypes.c_ubyte * 4), - ('fbRegionInfoParams', struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS), - ('sriovCaps', struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS), - ('sriovMaxGfid', ctypes.c_uint32), - ('engineCaps', ctypes.c_uint32 * 3), - ('poisonFuseEnabled', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), - ('fb_length', ctypes.c_uint64), - ('fbio_mask', ctypes.c_uint64), - ('fb_bus_width', ctypes.c_uint32), - ('fb_ram_type', ctypes.c_uint32), - ('fbp_mask', ctypes.c_uint64), - ('l2_cache_size', ctypes.c_uint32), - ('gpuNameString', ctypes.c_ubyte * 64), - ('gpuShortNameString', ctypes.c_ubyte * 64), - ('gpuNameString_Unicode', ctypes.c_uint16 * 64), - ('bGpuInternalSku', ctypes.c_ubyte), - ('bIsQuadroGeneric', ctypes.c_ubyte), - ('bIsQuadroAd', ctypes.c_ubyte), - ('bIsNvidiaNvs', ctypes.c_ubyte), - ('bIsVgx', ctypes.c_ubyte), - ('bGeforceSmb', ctypes.c_ubyte), - ('bIsTitan', ctypes.c_ubyte), - ('bIsTesla', ctypes.c_ubyte), - ('bIsMobile', ctypes.c_ubyte), - ('bIsGc6Rtd3Allowed', ctypes.c_ubyte), - ('bIsGc8Rtd3Allowed', ctypes.c_ubyte), - ('bIsGcOffRtd3Allowed', ctypes.c_ubyte), - ('bIsGcoffLegacyAllowed', ctypes.c_ubyte), - ('bIsMigSupported', ctypes.c_ubyte), - ('RTD3GC6TotalBoardPower', ctypes.c_uint16), - ('RTD3GC6PerstDelay', ctypes.c_uint16), - ('PADDING_3', ctypes.c_ubyte * 2), - ('bar1PdeBase', ctypes.c_uint64), - ('bar2PdeBase', ctypes.c_uint64), - ('bVbiosValid', ctypes.c_ubyte), - ('PADDING_4', ctypes.c_ubyte * 3), - ('vbiosSubVendor', ctypes.c_uint32), - ('vbiosSubDevice', ctypes.c_uint32), - ('bPageRetirementSupported', ctypes.c_ubyte), - ('bSplitVasBetweenServerClientRm', ctypes.c_ubyte), - ('bClRootportNeedsNosnoopWAR', ctypes.c_ubyte), - ('PADDING_5', ctypes.c_ubyte), - ('displaylessMaxHeads', VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS), - ('displaylessMaxResolution', VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS), - ('PADDING_6', ctypes.c_ubyte * 4), - ('displaylessMaxPixels', ctypes.c_uint64), - ('hInternalClient', ctypes.c_uint32), - ('hInternalDevice', ctypes.c_uint32), - ('hInternalSubdevice', ctypes.c_uint32), - ('bSelfHostedMode', ctypes.c_ubyte), - ('bAtsSupported', ctypes.c_ubyte), - ('bIsGpuUefi', ctypes.c_ubyte), - ('bIsEfiInit', ctypes.c_ubyte), - ('ecidInfo', struct_c__SA_EcidManufacturingInfo * 2), - ('fwWprLayoutOffset', FW_WPR_LAYOUT_OFFSET), -] - -GspStaticConfigInfo = struct_GspStaticConfigInfo_t -class struct_GspSystemInfo(Structure): - pass - -struct_GspSystemInfo._pack_ = 1 # source:False -struct_GspSystemInfo._fields_ = [ - ('gpuPhysAddr', ctypes.c_uint64), - ('gpuPhysFbAddr', ctypes.c_uint64), - ('gpuPhysInstAddr', ctypes.c_uint64), - ('gpuPhysIoAddr', ctypes.c_uint64), - ('nvDomainBusDeviceFunc', ctypes.c_uint64), - ('simAccessBufPhysAddr', ctypes.c_uint64), - ('notifyOpSharedSurfacePhysAddr', ctypes.c_uint64), - ('pcieAtomicsOpMask', ctypes.c_uint64), - ('consoleMemSize', ctypes.c_uint64), - ('maxUserVa', ctypes.c_uint64), - ('pciConfigMirrorBase', ctypes.c_uint32), - ('pciConfigMirrorSize', ctypes.c_uint32), - ('PCIDeviceID', ctypes.c_uint32), - ('PCISubDeviceID', ctypes.c_uint32), - ('PCIRevisionID', ctypes.c_uint32), - ('pcieAtomicsCplDeviceCapMask', ctypes.c_uint32), - ('oorArch', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('clPdbProperties', ctypes.c_uint64), - ('Chipset', ctypes.c_uint32), - ('bGpuBehindBridge', ctypes.c_ubyte), - ('bFlrSupported', ctypes.c_ubyte), - ('b64bBar0Supported', ctypes.c_ubyte), - ('bMnocAvailable', ctypes.c_ubyte), - ('chipsetL1ssEnable', ctypes.c_uint32), - ('bUpstreamL0sUnsupported', ctypes.c_ubyte), - ('bUpstreamL1Unsupported', ctypes.c_ubyte), - ('bUpstreamL1PorSupported', ctypes.c_ubyte), - ('bUpstreamL1PorMobileOnly', ctypes.c_ubyte), - ('bSystemHasMux', ctypes.c_ubyte), - ('upstreamAddressValid', ctypes.c_ubyte), - ('FHBBusInfo', BUSINFO), - ('chipsetIDInfo', BUSINFO), - ('PADDING_1', ctypes.c_ubyte * 2), - ('acpiMethodData', ACPI_METHOD_DATA), - ('hypervisorType', ctypes.c_uint32), - ('bIsPassthru', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), - ('sysTimerOffsetNs', ctypes.c_uint64), - ('gspVFInfo', GSP_VF_INFO), - ('bIsPrimary', ctypes.c_ubyte), - ('isGridBuild', ctypes.c_ubyte), - ('PADDING_3', ctypes.c_ubyte * 2), - ('pcieConfigReg', GSP_PCIE_CONFIG_REG), - ('gridBuildCsp', ctypes.c_uint32), - ('bPreserveVideoMemoryAllocations', ctypes.c_ubyte), - ('bTdrEventSupported', ctypes.c_ubyte), - ('bFeatureStretchVblankCapable', ctypes.c_ubyte), - ('bEnableDynamicGranularityPageArrays', ctypes.c_ubyte), - ('bClockBoostSupported', ctypes.c_ubyte), - ('bRouteDispIntrsToCPU', ctypes.c_ubyte), - ('PADDING_4', ctypes.c_ubyte * 6), - ('hostPageSize', ctypes.c_uint64), -] - -GspSystemInfo = struct_GspSystemInfo -VBIOS_H = True # macro -FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER = (0x4) # macro -FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS = (0x15) # macro -FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB = (0x19) # macro -BIT_HEADER_ID = 0xB8FF # macro -BIT_HEADER_SIGNATURE = 0x00544942 # macro -BIT_HEADER_SIZE_OFFSET = 8 # macro -BIT_HEADER_V1_00_FMT = "1w1d1w4b" # macro -BIT_TOKEN_V1_00_SIZE_6 = 6 # macro -BIT_TOKEN_V1_00_SIZE_8 = 8 # macro -BIT_TOKEN_V1_00_FMT_SIZE_6 = "2b2w" # macro -BIT_TOKEN_V1_00_FMT_SIZE_8 = "2b1w1d" # macro -BIT_TOKEN_BIOSDATA = 0x42 # macro -BIT_DATA_BIOSDATA_VERSION_1 = 0x1 # macro -BIT_DATA_BIOSDATA_VERSION_2 = 0x2 # macro -BIT_DATA_BIOSDATA_BINVER_FMT = "1d1b" # macro -BIT_DATA_BIOSDATA_BINVER_SIZE_5 = 5 # macro -BIT_TOKEN_FALCON_DATA = 0x70 # macro -BIT_DATA_FALCON_DATA_V2_4_FMT = "1d" # macro -BIT_DATA_FALCON_DATA_V2_SIZE_4 = 4 # macro -FALCON_UCODE_TABLE_HDR_V1_VERSION = 1 # macro -FALCON_UCODE_TABLE_HDR_V1_SIZE_6 = 6 # macro -FALCON_UCODE_TABLE_HDR_V1_6_FMT = "6b" # macro -FALCON_UCODE_TABLE_ENTRY_V1_VERSION = 1 # macro -FALCON_UCODE_TABLE_ENTRY_V1_SIZE_6 = 6 # macro -FALCON_UCODE_TABLE_ENTRY_V1_6_FMT = "2b1d" # macro -FALCON_UCODE_ENTRY_APPID_FIRMWARE_SEC_LIC = 0x05 # macro -FALCON_UCODE_ENTRY_APPID_FWSEC_DBG = 0x45 # macro -FALCON_UCODE_ENTRY_APPID_FWSEC_PROD = 0x85 # macro -# NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION = 0 : 0 # macro -NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_UNAVAILABLE = 0x00 # macro -NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_AVAILABLE = 0x01 # macro -# NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_RESERVED = 1 : 1 # macro -# NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_ENCRYPTED = 2 : 2 # macro -# NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_RESERVED = 7 : 3 # macro -# NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION = 15 : 8 # macro -NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V1 = 0x01 # macro -NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V2 = 0x02 # macro -NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V3 = 0x03 # macro -NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V4 = 0x04 # macro -# NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_SIZE = 31 : 16 # macro -FALCON_UCODE_DESC_HEADER_FORMAT = "1d" # macro -FALCON_UCODE_DESC_V3_SIZE_44 = 44 # macro -FALCON_UCODE_DESC_V3_44_FMT = "9d1w2b2w" # macro -BCRT30_RSA3K_SIG_SIZE = 384 # macro -FWSECLIC_READ_VBIOS_STRUCT_FLAGS = (2) # macro -FWSECLIC_FRTS_REGION_MEDIA_FB = (2) # macro -FWSECLIC_FRTS_REGION_SIZE_1MB_IN_4K = (0x100) # macro -class struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1(Structure): - pass - -struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1._pack_ = 1 # source:True -struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1._fields_ = [ - ('version', ctypes.c_ubyte), - ('headerSize', ctypes.c_ubyte), - ('entrySize', ctypes.c_ubyte), - ('entryCount', ctypes.c_ubyte), -] - -FALCON_APPLICATION_INTERFACE_HEADER_V1 = struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1 -class struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1(Structure): - pass - -struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1._pack_ = 1 # source:True -struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1._fields_ = [ - ('id', ctypes.c_uint32), - ('dmemOffset', ctypes.c_uint32), -] - -FALCON_APPLICATION_INTERFACE_ENTRY_V1 = struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1 -class struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3(Structure): - pass - -struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3._pack_ = 1 # source:True -struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3._fields_ = [ - ('signature', ctypes.c_uint32), - ('version', ctypes.c_uint16), - ('size', ctypes.c_uint16), - ('cmd_in_buffer_offset', ctypes.c_uint32), - ('cmd_in_buffer_size', ctypes.c_uint32), - ('cmd_out_buffer_offset', ctypes.c_uint32), - ('cmd_out_buffer_size', ctypes.c_uint32), - ('nvf_img_data_buffer_offset', ctypes.c_uint32), - ('nvf_img_data_buffer_size', ctypes.c_uint32), - ('printfBufferHdr', ctypes.c_uint32), - ('ucode_build_time_stamp', ctypes.c_uint32), - ('ucode_signature', ctypes.c_uint32), - ('init_cmd', ctypes.c_uint32), - ('ucode_feature', ctypes.c_uint32), - ('ucode_cmd_mask0', ctypes.c_uint32), - ('ucode_cmd_mask1', ctypes.c_uint32), - ('multiTgtTbl', ctypes.c_uint32), -] - -FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3 = struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3 -class struct_BIT_HEADER_V1_00(Structure): - pass - -struct_BIT_HEADER_V1_00._pack_ = 1 # source:True -struct_BIT_HEADER_V1_00._fields_ = [ - ('Id', ctypes.c_uint16), - ('Signature', ctypes.c_uint32), - ('BCD_Version', ctypes.c_uint16), - ('HeaderSize', ctypes.c_ubyte), - ('TokenSize', ctypes.c_ubyte), - ('TokenEntries', ctypes.c_ubyte), - ('HeaderChksum', ctypes.c_ubyte), -] - -BIT_HEADER_V1_00 = struct_BIT_HEADER_V1_00 -class struct_BIT_TOKEN_V1_00(Structure): - pass - -struct_BIT_TOKEN_V1_00._pack_ = 1 # source:True -struct_BIT_TOKEN_V1_00._fields_ = [ - ('TokenId', ctypes.c_ubyte), - ('DataVersion', ctypes.c_ubyte), - ('DataSize', ctypes.c_uint16), - ('DataPtr', ctypes.c_uint32), -] - -BIT_TOKEN_V1_00 = struct_BIT_TOKEN_V1_00 -class struct_c__SA_BIT_DATA_BIOSDATA_BINVER(Structure): - pass - -struct_c__SA_BIT_DATA_BIOSDATA_BINVER._pack_ = 1 # source:True -struct_c__SA_BIT_DATA_BIOSDATA_BINVER._fields_ = [ - ('Version', ctypes.c_uint32), - ('OemVersion', ctypes.c_ubyte), -] - -BIT_DATA_BIOSDATA_BINVER = struct_c__SA_BIT_DATA_BIOSDATA_BINVER -class struct_c__SA_BIT_DATA_FALCON_DATA_V2(Structure): - pass - -struct_c__SA_BIT_DATA_FALCON_DATA_V2._pack_ = 1 # source:True -struct_c__SA_BIT_DATA_FALCON_DATA_V2._fields_ = [ - ('FalconUcodeTablePtr', ctypes.c_uint32), -] - -BIT_DATA_FALCON_DATA_V2 = struct_c__SA_BIT_DATA_FALCON_DATA_V2 -class struct_c__SA_FALCON_UCODE_TABLE_HDR_V1(Structure): - pass - -struct_c__SA_FALCON_UCODE_TABLE_HDR_V1._pack_ = 1 # source:True -struct_c__SA_FALCON_UCODE_TABLE_HDR_V1._fields_ = [ - ('Version', ctypes.c_ubyte), - ('HeaderSize', ctypes.c_ubyte), - ('EntrySize', ctypes.c_ubyte), - ('EntryCount', ctypes.c_ubyte), - ('DescVersion', ctypes.c_ubyte), - ('DescSize', ctypes.c_ubyte), -] - -FALCON_UCODE_TABLE_HDR_V1 = struct_c__SA_FALCON_UCODE_TABLE_HDR_V1 -class struct_c__SA_FALCON_UCODE_TABLE_ENTRY_V1(Structure): - pass - -struct_c__SA_FALCON_UCODE_TABLE_ENTRY_V1._pack_ = 1 # source:True -struct_c__SA_FALCON_UCODE_TABLE_ENTRY_V1._fields_ = [ - ('ApplicationID', ctypes.c_ubyte), - ('TargetID', ctypes.c_ubyte), - ('DescPtr', ctypes.c_uint32), -] - -FALCON_UCODE_TABLE_ENTRY_V1 = struct_c__SA_FALCON_UCODE_TABLE_ENTRY_V1 -class struct_c__SA_FALCON_UCODE_DESC_HEADER(Structure): - pass - -struct_c__SA_FALCON_UCODE_DESC_HEADER._pack_ = 1 # source:True -struct_c__SA_FALCON_UCODE_DESC_HEADER._fields_ = [ - ('vDesc', ctypes.c_uint32), -] - -FALCON_UCODE_DESC_HEADER = struct_c__SA_FALCON_UCODE_DESC_HEADER -class struct_c__SA_FALCON_UCODE_DESC_V3(Structure): - pass - -struct_c__SA_FALCON_UCODE_DESC_V3._pack_ = 1 # source:False -struct_c__SA_FALCON_UCODE_DESC_V3._fields_ = [ - ('Hdr', FALCON_UCODE_DESC_HEADER), - ('StoredSize', ctypes.c_uint32), - ('PKCDataOffset', ctypes.c_uint32), - ('InterfaceOffset', ctypes.c_uint32), - ('IMEMPhysBase', ctypes.c_uint32), - ('IMEMLoadSize', ctypes.c_uint32), - ('IMEMVirtBase', ctypes.c_uint32), - ('DMEMPhysBase', ctypes.c_uint32), - ('DMEMLoadSize', ctypes.c_uint32), - ('EngineIdMask', ctypes.c_uint16), - ('UcodeId', ctypes.c_ubyte), - ('SignatureCount', ctypes.c_ubyte), - ('SignatureVersions', ctypes.c_uint16), - ('Reserved', ctypes.c_uint16), -] - -FALCON_UCODE_DESC_V3 = struct_c__SA_FALCON_UCODE_DESC_V3 -class struct_c__SA_FWSECLIC_READ_VBIOS_DESC(Structure): - pass - -struct_c__SA_FWSECLIC_READ_VBIOS_DESC._pack_ = 1 # source:True -struct_c__SA_FWSECLIC_READ_VBIOS_DESC._fields_ = [ - ('version', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('gfwImageOffset', ctypes.c_uint64), - ('gfwImageSize', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -FWSECLIC_READ_VBIOS_DESC = struct_c__SA_FWSECLIC_READ_VBIOS_DESC -class struct_c__SA_FWSECLIC_FRTS_REGION_DESC(Structure): - pass - -struct_c__SA_FWSECLIC_FRTS_REGION_DESC._pack_ = 1 # source:True -struct_c__SA_FWSECLIC_FRTS_REGION_DESC._fields_ = [ - ('version', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('frtsRegionOffset4K', ctypes.c_uint32), - ('frtsRegionSize', ctypes.c_uint32), - ('frtsRegionMediaType', ctypes.c_uint32), -] - -FWSECLIC_FRTS_REGION_DESC = struct_c__SA_FWSECLIC_FRTS_REGION_DESC -class struct_c__SA_FWSECLIC_FRTS_CMD(Structure): - _pack_ = 1 # source:True - _fields_ = [ - ('readVbiosDesc', FWSECLIC_READ_VBIOS_DESC), - ('frtsRegionDesc', FWSECLIC_FRTS_REGION_DESC), - ] - -FWSECLIC_FRTS_CMD = struct_c__SA_FWSECLIC_FRTS_CMD -PCIEXPTBL_H = True # macro -NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE = 0x00 # macro -NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT = 0xE0 # macro -PCI_EXP_ROM_SIGNATURE = 0xaa55 # macro -PCI_EXP_ROM_SIGNATURE_NV = 0x4e56 # macro -PCI_EXP_ROM_SIGNATURE_NV2 = 0xbb77 # macro -def IS_VALID_PCI_ROM_SIG(sig): # macro - return ((sig==0xaa55) or (sig==0x4e56) or (sig==0xbb77)) -OFFSETOF_PCI_EXP_ROM_SIG = 0x0 # macro -OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET = 0x16 # macro -OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR = 0x18 # macro -PCI_DATA_STRUCT_SIGNATURE = 0x52494350 # macro -PCI_DATA_STRUCT_SIGNATURE_NV = 0x5344504E # macro -PCI_DATA_STRUCT_SIGNATURE_NV2 = 0x53494752 # macro -def IS_VALID_PCI_DATA_SIG(sig): # macro - return ((sig==0x52494350) or (sig==0x5344504E) or (sig==0x53494752)) -# PCI_LAST_IMAGE = NVBIT ( 7 ) # macro -PCI_ROM_IMAGE_BLOCK_SIZE = 512 # macro -OFFSETOF_PCI_DATA_STRUCT_SIG = 0x0 # macro -OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID = 0x4 # macro -OFFSETOF_PCI_DATA_STRUCT_LEN = 0xa # macro -OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE = 0xd # macro -OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE = 0x14 # macro -OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN = 0x10 # macro -OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE = 0x15 # macro -NV_PCI_DATA_EXT_SIG = 0x4544504E # macro -NV_PCI_DATA_EXT_REV_10 = 0x100 # macro -NV_PCI_DATA_EXT_REV_11 = 0x101 # macro -OFFSETOF_PCI_DATA_EXT_STRUCT_SIG = 0x0 # macro -OFFSETOF_PCI_DATA_EXT_STRUCT_LEN = 0x6 # macro -OFFSETOF_PCI_DATA_EXT_STRUCT_REV = 0x4 # macro -OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN = 0x8 # macro -OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE = 0xa # macro -OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS = 0xb # macro -PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED = 0x04 # macro -class struct__PCI_EXP_ROM_STANDARD(Structure): - pass - -struct__PCI_EXP_ROM_STANDARD._pack_ = 1 # source:False -struct__PCI_EXP_ROM_STANDARD._fields_ = [ - ('sig', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 22), - ('pciDataStrucPtr', ctypes.c_uint16), - ('sizeOfBlock', ctypes.c_uint32), -] - -PCI_EXP_ROM_STANDARD = struct__PCI_EXP_ROM_STANDARD -PPCI_EXP_ROM_STANDARD = ctypes.POINTER(struct__PCI_EXP_ROM_STANDARD) -class struct__PCI_EXP_ROM_NBSI(Structure): - pass - -struct__PCI_EXP_ROM_NBSI._pack_ = 1 # source:False -struct__PCI_EXP_ROM_NBSI._fields_ = [ - ('sig', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 20), - ('nbsiDataOffset', ctypes.c_uint16), - ('pciDataStrucPtr', ctypes.c_uint16), - ('sizeOfBlock', ctypes.c_uint32), -] - -PCI_EXP_ROM_NBSI = struct__PCI_EXP_ROM_NBSI -PPCI_EXP_ROM_NBSI = ctypes.POINTER(struct__PCI_EXP_ROM_NBSI) -class union__PCI_EXP_ROM(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('standard', PCI_EXP_ROM_STANDARD), - ('nbsi', PCI_EXP_ROM_NBSI), - ] - -PCI_EXP_ROM = union__PCI_EXP_ROM -PPCI_EXP_ROM = ctypes.POINTER(union__PCI_EXP_ROM) -class struct__PCI_DATA_STRUCT(Structure): - pass - -struct__PCI_DATA_STRUCT._pack_ = 1 # source:False -struct__PCI_DATA_STRUCT._fields_ = [ - ('sig', ctypes.c_uint32), - ('vendorID', ctypes.c_uint16), - ('deviceID', ctypes.c_uint16), - ('deviceListPtr', ctypes.c_uint16), - ('pciDataStructLen', ctypes.c_uint16), - ('pciDataStructRev', ctypes.c_ubyte), - ('classCode', ctypes.c_ubyte * 3), - ('imageLen', ctypes.c_uint16), - ('vendorRomRev', ctypes.c_uint16), - ('codeType', ctypes.c_ubyte), - ('lastImage', ctypes.c_ubyte), - ('maxRunTimeImageLen', ctypes.c_uint16), -] - -PCI_DATA_STRUCT = struct__PCI_DATA_STRUCT -PPCI_DATA_STRUCT = ctypes.POINTER(struct__PCI_DATA_STRUCT) -class struct__NV_PCI_DATA_EXT_STRUCT(Structure): - pass - -struct__NV_PCI_DATA_EXT_STRUCT._pack_ = 1 # source:False -struct__NV_PCI_DATA_EXT_STRUCT._fields_ = [ - ('signature', ctypes.c_uint32), - ('nvPciDataExtRev', ctypes.c_uint16), - ('nvPciDataExtLen', ctypes.c_uint16), - ('subimageLen', ctypes.c_uint16), - ('privLastImage', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -NV_PCI_DATA_EXT_STRUCT = struct__NV_PCI_DATA_EXT_STRUCT -PNV_PCI_DATA_EXT_STRUCT = ctypes.POINTER(struct__NV_PCI_DATA_EXT_STRUCT) -__all__ = \ - ['ACPI_DATA', 'ACPI_DSM_CACHE', 'ACPI_DSM_FUNCTION_COUNT', - 'ACPI_DSM_FUNCTION_CURRENT', 'ACPI_DSM_FUNCTION_GPS', - 'ACPI_DSM_FUNCTION_GPS_2X', 'ACPI_DSM_FUNCTION_INVALID', - 'ACPI_DSM_FUNCTION_JT', 'ACPI_DSM_FUNCTION_MXM', - 'ACPI_DSM_FUNCTION_NBCI', 'ACPI_DSM_FUNCTION_NBSI', - 'ACPI_DSM_FUNCTION_NVHG', 'ACPI_DSM_FUNCTION_NVOP', - 'ACPI_DSM_FUNCTION_NVPCF', 'ACPI_DSM_FUNCTION_NVPCF_2X', - 'ACPI_DSM_FUNCTION_PCFG', 'ACPI_DSM_FUNCTION_PEX', - 'ACPI_METHOD_DATA', 'BCRT30_RSA3K_SIG_SIZE', - 'BIT_DATA_BIOSDATA_BINVER', 'BIT_DATA_BIOSDATA_BINVER_FMT', - 'BIT_DATA_BIOSDATA_BINVER_SIZE_5', 'BIT_DATA_BIOSDATA_VERSION_1', - 'BIT_DATA_BIOSDATA_VERSION_2', 'BIT_DATA_FALCON_DATA_V2', - 'BIT_DATA_FALCON_DATA_V2_4_FMT', 'BIT_DATA_FALCON_DATA_V2_SIZE_4', - 'BIT_HEADER_ID', 'BIT_HEADER_SIGNATURE', 'BIT_HEADER_SIZE_OFFSET', - 'BIT_HEADER_V1_00', 'BIT_HEADER_V1_00_FMT', 'BIT_TOKEN_BIOSDATA', - 'BIT_TOKEN_FALCON_DATA', 'BIT_TOKEN_V1_00', - 'BIT_TOKEN_V1_00_FMT_SIZE_6', 'BIT_TOKEN_V1_00_FMT_SIZE_8', - 'BIT_TOKEN_V1_00_SIZE_6', 'BIT_TOKEN_V1_00_SIZE_8', 'BUSINFO', - 'CAPS_METHOD_DATA', 'DEFINING_E_IN_RPC_GLOBAL_ENUMS_H', - 'DEFINING_X_IN_RPC_GLOBAL_ENUMS_H', 'DISPMUXSTATE', - 'DISPMUXSTATE__enumvalues', 'DOD_METHOD_DATA', - 'EcidManufacturingInfo', - 'FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3', - 'FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS', - 'FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB', - 'FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER', - 'FALCON_APPLICATION_INTERFACE_ENTRY_V1', - 'FALCON_APPLICATION_INTERFACE_HEADER_V1', - 'FALCON_UCODE_DESC_HEADER', 'FALCON_UCODE_DESC_HEADER_FORMAT', - 'FALCON_UCODE_DESC_V3', 'FALCON_UCODE_DESC_V3_44_FMT', - 'FALCON_UCODE_DESC_V3_SIZE_44', - 'FALCON_UCODE_ENTRY_APPID_FIRMWARE_SEC_LIC', - 'FALCON_UCODE_ENTRY_APPID_FWSEC_DBG', - 'FALCON_UCODE_ENTRY_APPID_FWSEC_PROD', - 'FALCON_UCODE_TABLE_ENTRY_V1', - 'FALCON_UCODE_TABLE_ENTRY_V1_6_FMT', - 'FALCON_UCODE_TABLE_ENTRY_V1_SIZE_6', - 'FALCON_UCODE_TABLE_ENTRY_V1_VERSION', - 'FALCON_UCODE_TABLE_HDR_V1', 'FALCON_UCODE_TABLE_HDR_V1_6_FMT', - 'FALCON_UCODE_TABLE_HDR_V1_SIZE_6', - 'FALCON_UCODE_TABLE_HDR_V1_VERSION', 'FECS_ERROR_EVENT_TYPE', - 'FECS_ERROR_EVENT_TYPE_BUFFER_FULL', - 'FECS_ERROR_EVENT_TYPE_BUFFER_RESET_REQUIRED', - 'FECS_ERROR_EVENT_TYPE_MAX', 'FECS_ERROR_EVENT_TYPE_NONE', - 'FECS_ERROR_EVENT_TYPE__enumvalues', 'FSP_NVDM_FORMAT_H', - 'FWSECLIC_FRTS_CMD', 'FWSECLIC_FRTS_REGION_DESC', - 'FWSECLIC_FRTS_REGION_MEDIA_FB', - 'FWSECLIC_FRTS_REGION_SIZE_1MB_IN_4K', 'FWSECLIC_READ_VBIOS_DESC', - 'FWSECLIC_READ_VBIOS_STRUCT_FLAGS', 'FW_WPR_LAYOUT_OFFSET', - 'GPU_RECOVERY_EVENT_TYPE', - 'GPU_RECOVERY_EVENT_TYPE_GPU_DRAIN_P2P', - 'GPU_RECOVERY_EVENT_TYPE_REFRESH', - 'GPU_RECOVERY_EVENT_TYPE_SYS_REBOOT', - 'GPU_RECOVERY_EVENT_TYPE__enumvalues', - 'GR_MAX_RPC_CTX_BUFFER_COUNT', 'GSPIFPUB_H', - 'GSP_ACR_BOOT_GSP_RM_PARAMS', 'GSP_ARGUMENTS_CACHED', - 'GSP_DMA_TARGET', 'GSP_DMA_TARGET_COHERENT_SYSTEM', - 'GSP_DMA_TARGET_COUNT', 'GSP_DMA_TARGET_LOCAL_FB', - 'GSP_DMA_TARGET_NONCOHERENT_SYSTEM', 'GSP_DMA_TARGET__enumvalues', - 'GSP_FMC_BOOT_PARAMS', 'GSP_FMC_INIT_PARAMS', - 'GSP_FW_HEAP_FREE_LIST_MAGIC', 'GSP_FW_SR_META_H_', - 'GSP_FW_SR_META_INTERNAL_SIZE', 'GSP_FW_SR_META_MAGIC', - 'GSP_FW_SR_META_REVISION', 'GSP_FW_WPR_HEAP_FREE_REGION_COUNT', - 'GSP_FW_WPR_META_H_', 'GSP_FW_WPR_META_MAGIC', - 'GSP_FW_WPR_META_REVISION', 'GSP_FW_WPR_META_VERIFIED', - 'GSP_INIT_ARGS_H', 'GSP_MSG_QUEUE_ELEMENT', 'GSP_PCIE_CONFIG_REG', - 'GSP_RM_PARAMS', 'GSP_SPDM_PARAMS', 'GSP_SR_INIT_ARGUMENTS', - 'GSP_STATIC_CONFIG_H', 'GSP_VF_INFO', 'GspFwHeapFreeList', - 'GspFwHeapFreeRegion', 'GspFwSRMeta', 'GspFwWprMeta', - 'GspStaticConfigInfo', 'GspSystemInfo', 'JT_METHOD_DATA', - 'KERN_FSP_COT_PAYLOAD_H', 'LIBOS_INIT_H_', - 'LIBOS_MEMORY_REGION_CONTIGUOUS', - 'LIBOS_MEMORY_REGION_INIT_ARGUMENTS_MAX', - 'LIBOS_MEMORY_REGION_LOC_FB', 'LIBOS_MEMORY_REGION_LOC_NONE', - 'LIBOS_MEMORY_REGION_LOC_SYSMEM', 'LIBOS_MEMORY_REGION_NONE', - 'LIBOS_MEMORY_REGION_RADIX3', - 'LIBOS_MEMORY_REGION_RADIX_PAGE_LOG2', - 'LIBOS_MEMORY_REGION_RADIX_PAGE_SIZE', 'LibosAddress', - 'LibosMemoryRegionInitArgument', 'LibosMemoryRegionKind', - 'LibosMemoryRegionKind__enumvalues', 'LibosMemoryRegionLoc', - 'LibosMemoryRegionLoc__enumvalues', - 'MAX_DSM_SUPPORTED_FUNCS_RTN_LEN', 'MAX_GPC_COUNT', - 'MAX_GROUP_COUNT', 'MCTP_HEADER', 'MESSAGE_QUEUE_INIT_ARGUMENTS', - 'MSGQ_PRIV_H', 'MSGQ_VERSION', 'MUX_METHOD_DATA', - 'MUX_METHOD_DATA_ELEMENT', 'NV0080_CTRL_GR_TPC_PARTITION_MODE', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', - 'NV2080_CTRL_CMD_PERF_VID_ENG', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', - 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE', - 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COLOR', - 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT', - 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_DEPTH', - 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_INVALID', - 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL', 'NVB0CC_REGOPS_MODE', - 'NVB0CC_REGOPS_MODE_ALL_OR_NONE', - 'NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR', 'NVDM_PAYLOAD_COT', - 'NVDM_TYPE_CAPS_QUERY', 'NVDM_TYPE_CLOCK_BOOST', 'NVDM_TYPE_COT', - 'NVDM_TYPE_FIRMWARE_UPDATE', 'NVDM_TYPE_FSP_GSP_COMM', - 'NVDM_TYPE_FSP_RESPONSE', 'NVDM_TYPE_HULK', 'NVDM_TYPE_INFOROM', - 'NVDM_TYPE_PRC', 'NVDM_TYPE_ROMREAD', 'NVDM_TYPE_SMBPBI', - 'NVDM_TYPE_TNVL', 'NVDM_TYPE_UEFI_RM', - 'NVDM_TYPE_UEFI_XTL_DEBUG_INTR', - 'NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX', 'NVGPU_ENGINE_CAPS_MASK_BITS', - 'NV_ACPI_GENERIC_FUNC_COUNT', - 'NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE', - 'NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT', - 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_AVAILABLE', - 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_UNAVAILABLE', - 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V1', - 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V2', - 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V3', - 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V4', - 'NV_PCI_DATA_EXT_REV_10', 'NV_PCI_DATA_EXT_REV_11', - 'NV_PCI_DATA_EXT_SIG', 'NV_PCI_DATA_EXT_STRUCT', - 'NV_RPC_UPDATE_PDE_BAR_1', 'NV_RPC_UPDATE_PDE_BAR_2', - 'NV_RPC_UPDATE_PDE_BAR_INVALID', 'NV_RPC_UPDATE_PDE_BAR_TYPE', - 'NV_RPC_UPDATE_PDE_BAR_TYPE__enumvalues', - 'NV_VGPU_LOG_LEVEL_DEBUG', 'NV_VGPU_LOG_LEVEL_ERROR', - 'NV_VGPU_LOG_LEVEL_FATAL', 'NV_VGPU_LOG_LEVEL_NOTICE', - 'NV_VGPU_LOG_LEVEL_STATUS', 'NV_VGPU_MSG_EVENT_DISPLAY_MODESET', - 'NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE', - 'NV_VGPU_MSG_EVENT_FECS_ERROR', 'NV_VGPU_MSG_EVENT_FIRST_EVENT', - 'NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES', - 'NV_VGPU_MSG_EVENT_GSP_INIT_DONE', - 'NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE', - 'NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD', - 'NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER', - 'NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE', - 'NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED', - 'NV_VGPU_MSG_EVENT_NUM_EVENTS', - 'NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY', - 'NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP', - 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024', - 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048', - 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256', - 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096', - 'NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512', - 'NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED', - 'NV_VGPU_MSG_EVENT_OS_ERROR_LOG', - 'NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE', - 'NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK', - 'NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK', - 'NV_VGPU_MSG_EVENT_POST_EVENT', 'NV_VGPU_MSG_EVENT_RC_TRIGGERED', - 'NV_VGPU_MSG_EVENT_RECOVERY_ACTION', - 'NV_VGPU_MSG_EVENT_RG_LINE_INTR', - 'NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK', - 'NV_VGPU_MSG_EVENT_SIM_READ', 'NV_VGPU_MSG_EVENT_SIM_WRITE', - 'NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE', - 'NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT', - 'NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE', - 'NV_VGPU_MSG_EVENT_VGPU_CONFIG', - 'NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED', - 'NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA', - 'NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA', - 'NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE', - 'NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL', - 'NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT', - 'NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY', - 'NV_VGPU_MSG_FUNCTION_ALLOC_EVENT', - 'NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY', - 'NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT', - 'NV_VGPU_MSG_FUNCTION_ALLOC_ROOT', - 'NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE', - 'NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE', - 'NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM', - 'NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM', - 'NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA', - 'NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA', - 'NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE', - 'NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD', - 'NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT', - 'NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM', - 'NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS', - 'NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES', - 'NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING', - 'NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING', - 'NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT', - 'NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY', - 'NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS', - 'NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE', - 'NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE', - 'NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP', - 'NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT', - 'NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE', - 'NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET', - 'NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE', - 'NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE', - 'NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE', - 'NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS', - 'NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2', - 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT', - 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS', - 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB', - 'NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES', - 'NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK', - 'NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE', - 'NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE', - 'NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX', - 'NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS', - 'NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE', - 'NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE', - 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED', - 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS', - 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL', - 'NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM', - 'NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES', - 'NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK', - 'NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS', - 'NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO', - 'NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA', - 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST', - 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2', - 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS', - 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL', - 'NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL', - 'NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT', - 'NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER', - 'NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT', - 'NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF', - 'NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES', - 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF', - 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES', - 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY', - 'NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC', - 'NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL', - 'NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR', - 'NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR', - 'NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL', - 'NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS', - 'NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS', - 'NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS', - 'NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ', - 'NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES', - 'NV_VGPU_MSG_FUNCTION_DCE_RM_INIT', - 'NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL', - 'NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT', - 'NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS', - 'NV_VGPU_MSG_FUNCTION_DMA_CONTROL', - 'NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM', - 'NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT', - 'NV_VGPU_MSG_FUNCTION_DUP_OBJECT', - 'NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK', - 'NV_VGPU_MSG_FUNCTION_FREE', - 'NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT', - 'NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS', - 'NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO', - 'NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO', - 'NV_VGPU_MSG_FUNCTION_GET_EDID', - 'NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY', - 'NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION', - 'NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO', - 'NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND', - 'NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA', - 'NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO', - 'NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2', - 'NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO', - 'NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 'NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER', - 'NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 'NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER', - 'NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS', - 'NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU', - 'NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC', - 'NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL', - 'NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO', - 'NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS', - 'NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB', 'NV_VGPU_MSG_FUNCTION_LOG', - 'NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE', - 'NV_VGPU_MSG_FUNCTION_MAP_MEMORY', - 'NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA', - 'NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY', - 'NV_VGPU_MSG_FUNCTION_NOP', 'NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS', - 'NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO', - 'NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE', - 'NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO', - 'NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO', - 'NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION', - 'NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER', - 'NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL', - 'NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API', - 'NV_VGPU_MSG_FUNCTION_RESERVED_0', - 'NV_VGPU_MSG_FUNCTION_RESERVED_208', - 'NV_VGPU_MSG_FUNCTION_RESERVED_57', - 'NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT', - 'NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA', - 'NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP', - 'NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE', - 'NV_VGPU_MSG_FUNCTION_RMFS_INIT', - 'NV_VGPU_MSG_FUNCTION_RMFS_TEST', - 'NV_VGPU_MSG_FUNCTION_RM_API_CONTROL', - 'NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA', - 'NV_VGPU_MSG_FUNCTION_SEND_EVENT', - 'NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO', - 'NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT', - 'NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY', - 'NV_VGPU_MSG_FUNCTION_SET_REGISTRY', - 'NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE', - 'NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES', - 'NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER', - 'NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ', - 'NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE', - 'NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA', - 'NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION', - 'NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA', - 'NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE', - 'NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES', - 'NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER', - 'NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY', - 'NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA', - 'NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY', - 'NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY', - 'NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE', - 'NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO', - 'NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES', - 'NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2', - 'NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION', - 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE', - 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY', - 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP', - 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM', - 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES', - 'NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP', - 'NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32', - 'NV_VGPU_MSG_HEADER_VERSION_MAJOR_TOT', - 'NV_VGPU_MSG_HEADER_VERSION_MINOR_TOT', - 'NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED', - 'NV_VGPU_MSG_RESULT_RPC_CUDA_PROFILING_DISABLED', - 'NV_VGPU_MSG_RESULT_RPC_HANDLE_EXISTS', - 'NV_VGPU_MSG_RESULT_RPC_HANDLE_NOT_FOUND', - 'NV_VGPU_MSG_RESULT_RPC_INVALID_MESSAGE_FORMAT', - 'NV_VGPU_MSG_RESULT_RPC_PENDING', - 'NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE', - 'NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION', - 'NV_VGPU_MSG_RESULT_RPC_UNKNOWN_RM_ERROR', - 'NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR', - 'NV_VGPU_MSG_RESULT_VMIOP_ECC_MISMATCH', - 'NV_VGPU_MSG_RESULT_VMIOP_INVAL', - 'NV_VGPU_MSG_RESULT_VMIOP_NOT_ALLOWED_IN_CALLBACK', - 'NV_VGPU_MSG_RESULT_VMIOP_NOT_FOUND', - 'NV_VGPU_MSG_RESULT_VMIOP_NOT_SUPPORTED', - 'NV_VGPU_MSG_RESULT_VMIOP_NO_ADDRESS_SPACE', - 'NV_VGPU_MSG_RESULT_VMIOP_RANGE', - 'NV_VGPU_MSG_RESULT_VMIOP_READ_ONLY', - 'NV_VGPU_MSG_RESULT_VMIOP_RESOURCE', - 'NV_VGPU_MSG_RESULT_VMIOP_TIMEOUT', 'NV_VGPU_MSG_SIGNATURE_VALID', - 'NV_VGPU_MSG_UNION_INIT', 'NV_VGPU_PTEDESC_IDR_DOUBLE', - 'NV_VGPU_PTEDESC_IDR_NONE', 'NV_VGPU_PTEDESC_IDR_SINGLE', - 'NV_VGPU_PTEDESC_IDR_TRIPLE', 'NV_VGPU_PTEDESC_INIT', - 'NV_VGPU_PTEDESC__PROD', 'NV_VGPU_PTE_64_INDEX_MASK', - 'NV_VGPU_PTE_64_INDEX_SHIFT', 'NV_VGPU_PTE_64_PAGE_SIZE', - 'NV_VGPU_PTE_64_SIZE', 'NV_VGPU_PTE_INDEX_MASK', - 'NV_VGPU_PTE_INDEX_SHIFT', 'NV_VGPU_PTE_PAGE_SIZE', - 'NV_VGPU_PTE_SIZE', 'OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS', - 'OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE', - 'OFFSETOF_PCI_DATA_EXT_STRUCT_LEN', - 'OFFSETOF_PCI_DATA_EXT_STRUCT_REV', - 'OFFSETOF_PCI_DATA_EXT_STRUCT_SIG', - 'OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN', - 'OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE', - 'OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE', - 'OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN', - 'OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE', - 'OFFSETOF_PCI_DATA_STRUCT_LEN', 'OFFSETOF_PCI_DATA_STRUCT_SIG', - 'OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID', - 'OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET', - 'OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR', - 'OFFSETOF_PCI_EXP_ROM_SIG', 'PACKED_REGISTRY_ENTRY', - 'PACKED_REGISTRY_TABLE', 'PCIEXPTBL_H', - 'PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED', 'PCI_DATA_STRUCT', - 'PCI_DATA_STRUCT_SIGNATURE', 'PCI_DATA_STRUCT_SIGNATURE_NV', - 'PCI_DATA_STRUCT_SIGNATURE_NV2', 'PCI_EXP_ROM', - 'PCI_EXP_ROM_NBSI', 'PCI_EXP_ROM_SIGNATURE', - 'PCI_EXP_ROM_SIGNATURE_NV', 'PCI_EXP_ROM_SIGNATURE_NV2', - 'PCI_EXP_ROM_STANDARD', 'PCI_ROM_IMAGE_BLOCK_SIZE', - 'PNV_PCI_DATA_EXT_STRUCT', 'PPCI_DATA_STRUCT', 'PPCI_EXP_ROM', - 'PPCI_EXP_ROM_NBSI', 'PPCI_EXP_ROM_STANDARD', - 'REGISTRY_TABLE_ENTRY_TYPE_BINARY', - 'REGISTRY_TABLE_ENTRY_TYPE_DWORD', - 'REGISTRY_TABLE_ENTRY_TYPE_STRING', - 'REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN', 'RM_ENGINE_TYPE', - 'RM_ENGINE_TYPE_BSP', 'RM_ENGINE_TYPE_CIPHER', - 'RM_ENGINE_TYPE_COPY0', 'RM_ENGINE_TYPE_COPY1', - 'RM_ENGINE_TYPE_COPY10', 'RM_ENGINE_TYPE_COPY11', - 'RM_ENGINE_TYPE_COPY12', 'RM_ENGINE_TYPE_COPY13', - 'RM_ENGINE_TYPE_COPY14', 'RM_ENGINE_TYPE_COPY15', - 'RM_ENGINE_TYPE_COPY16', 'RM_ENGINE_TYPE_COPY17', - 'RM_ENGINE_TYPE_COPY18', 'RM_ENGINE_TYPE_COPY19', - 'RM_ENGINE_TYPE_COPY2', 'RM_ENGINE_TYPE_COPY3', - 'RM_ENGINE_TYPE_COPY4', 'RM_ENGINE_TYPE_COPY5', - 'RM_ENGINE_TYPE_COPY6', 'RM_ENGINE_TYPE_COPY7', - 'RM_ENGINE_TYPE_COPY8', 'RM_ENGINE_TYPE_COPY9', - 'RM_ENGINE_TYPE_COPY_SIZE', 'RM_ENGINE_TYPE_DPU', - 'RM_ENGINE_TYPE_FBFLCN', 'RM_ENGINE_TYPE_GR0', - 'RM_ENGINE_TYPE_GR1', 'RM_ENGINE_TYPE_GR2', 'RM_ENGINE_TYPE_GR3', - 'RM_ENGINE_TYPE_GR4', 'RM_ENGINE_TYPE_GR5', 'RM_ENGINE_TYPE_GR6', - 'RM_ENGINE_TYPE_GR7', 'RM_ENGINE_TYPE_GRAPHICS', - 'RM_ENGINE_TYPE_GR_SIZE', 'RM_ENGINE_TYPE_HOST', - 'RM_ENGINE_TYPE_LAST', 'RM_ENGINE_TYPE_ME', 'RM_ENGINE_TYPE_MP', - 'RM_ENGINE_TYPE_MPEG', 'RM_ENGINE_TYPE_MSENC', - 'RM_ENGINE_TYPE_NULL', 'RM_ENGINE_TYPE_NVDEC0', - 'RM_ENGINE_TYPE_NVDEC1', 'RM_ENGINE_TYPE_NVDEC2', - 'RM_ENGINE_TYPE_NVDEC3', 'RM_ENGINE_TYPE_NVDEC4', - 'RM_ENGINE_TYPE_NVDEC5', 'RM_ENGINE_TYPE_NVDEC6', - 'RM_ENGINE_TYPE_NVDEC7', 'RM_ENGINE_TYPE_NVDEC_SIZE', - 'RM_ENGINE_TYPE_NVENC0', 'RM_ENGINE_TYPE_NVENC1', - 'RM_ENGINE_TYPE_NVENC2', 'RM_ENGINE_TYPE_NVENC3', - 'RM_ENGINE_TYPE_NVENC_SIZE', 'RM_ENGINE_TYPE_NVJPEG0', - 'RM_ENGINE_TYPE_NVJPEG1', 'RM_ENGINE_TYPE_NVJPEG2', - 'RM_ENGINE_TYPE_NVJPEG3', 'RM_ENGINE_TYPE_NVJPEG4', - 'RM_ENGINE_TYPE_NVJPEG5', 'RM_ENGINE_TYPE_NVJPEG6', - 'RM_ENGINE_TYPE_NVJPEG7', 'RM_ENGINE_TYPE_NVJPEG_SIZE', - 'RM_ENGINE_TYPE_NVJPG', 'RM_ENGINE_TYPE_OFA0', - 'RM_ENGINE_TYPE_OFA1', 'RM_ENGINE_TYPE_OFA_SIZE', - 'RM_ENGINE_TYPE_PMU', 'RM_ENGINE_TYPE_PPP', - 'RM_ENGINE_TYPE_RESERVED40', 'RM_ENGINE_TYPE_RESERVED41', - 'RM_ENGINE_TYPE_RESERVED42', 'RM_ENGINE_TYPE_RESERVED43', - 'RM_ENGINE_TYPE_RESERVED44', 'RM_ENGINE_TYPE_RESERVED45', - 'RM_ENGINE_TYPE_RESERVED46', 'RM_ENGINE_TYPE_RESERVED47', - 'RM_ENGINE_TYPE_RESERVED48', 'RM_ENGINE_TYPE_RESERVED49', - 'RM_ENGINE_TYPE_RESERVED4a', 'RM_ENGINE_TYPE_RESERVED4b', - 'RM_ENGINE_TYPE_RESERVED4c', 'RM_ENGINE_TYPE_RESERVED4d', - 'RM_ENGINE_TYPE_RESERVED4e', 'RM_ENGINE_TYPE_RESERVED4f', - 'RM_ENGINE_TYPE_RESERVED50', 'RM_ENGINE_TYPE_RESERVED51', - 'RM_ENGINE_TYPE_RESERVED52', 'RM_ENGINE_TYPE_RESERVED53', - 'RM_ENGINE_TYPE_SEC2', 'RM_ENGINE_TYPE_SW', 'RM_ENGINE_TYPE_TSEC', - 'RM_ENGINE_TYPE_VIC', 'RM_ENGINE_TYPE_VP', - 'RM_ENGINE_TYPE__enumvalues', 'RM_RISCV_UCODE_DESC', - 'RM_RISCV_UCODE_H', 'RPC_GR_BUFFER_TYPE', - 'RPC_GR_BUFFER_TYPE_COMPUTE_PREEMPT', - 'RPC_GR_BUFFER_TYPE_GRAPHICS', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_BUNDLE_CB', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_FECS_EVENT', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_CTRL_BLK', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_POOL', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_GRAPHICS_PM', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_MAX', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_PAGEPOOL_GLOBAL', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_PATCH', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_PRIV_ACCESS_MAP', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_RTV_CB_GLOBAL', - 'RPC_GR_BUFFER_TYPE_GRAPHICS_ZCULL', - 'RPC_GR_BUFFER_TYPE__enumvalues', 'SDK_STRUCTURES', 'VBIOS_H', - 'VGPU_MAX_REGOPS_PER_RPC', 'VGPU_RESERVED_HANDLE_BASE', - 'VGPU_RESERVED_HANDLE_RANGE', - 'VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06', - 'VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC', - 'VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS', - 'VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS', '_ACPI_DSM_FUNCTION', - '_RPC_GLOBAL_ENUMS_H_', '__vgpu_rpc_nv_headers_h__', - 'c__EA_DISPMUXSTATE', 'c__EA_FECS_ERROR_EVENT_TYPE', - 'c__EA_GPU_RECOVERY_EVENT_TYPE', 'c__EA_GSP_DMA_TARGET', - 'c__EA_LibosMemoryRegionKind', 'c__EA_LibosMemoryRegionLoc', - 'c__EA_NV_RPC_UPDATE_PDE_BAR_TYPE', 'c__EA_RM_ENGINE_TYPE', - 'c__EA_RPC_GR_BUFFER_TYPE', 'c__Ea_NV_VGPU_MSG_EVENT_FIRST_EVENT', - 'c__Ea_NV_VGPU_MSG_FUNCTION_NOP', 'dispMuxState_DiscreteGPU', - 'dispMuxState_IntegratedGPU', 'dispMuxState_None', 'msgqMetadata', - 'msgqRxHeader', 'msgqTxHeader', 'rpc_alloc_channel_dma_v', - 'rpc_alloc_channel_dma_v1F_04', 'rpc_alloc_event_v', - 'rpc_alloc_event_v03_00', 'rpc_alloc_memory_v', - 'rpc_alloc_memory_v13_01', 'rpc_alloc_object_v', - 'rpc_alloc_object_v25_08', 'rpc_alloc_object_v26_00', - 'rpc_alloc_object_v27_00', 'rpc_alloc_object_v29_06', - 'rpc_alloc_root_v', 'rpc_alloc_root_v07_00', - 'rpc_alloc_share_device_v', 'rpc_alloc_share_device_v03_00', - 'rpc_alloc_subdevice_v', 'rpc_alloc_subdevice_v08_01', - 'rpc_cleanup_surface_v', 'rpc_cleanup_surface_v03_00', - 'rpc_ctrl_alloc_pma_stream_v', 'rpc_ctrl_alloc_pma_stream_v1A_14', - 'rpc_ctrl_b0cc_exec_reg_ops_v', - 'rpc_ctrl_b0cc_exec_reg_ops_v1A_0F', - 'rpc_ctrl_bind_pm_resources_v', - 'rpc_ctrl_bind_pm_resources_v1A_0F', - 'rpc_ctrl_bus_set_p2p_mapping_v', - 'rpc_ctrl_bus_set_p2p_mapping_v21_03', - 'rpc_ctrl_bus_set_p2p_mapping_v29_08', - 'rpc_ctrl_bus_unset_p2p_mapping_v', - 'rpc_ctrl_bus_unset_p2p_mapping_v21_03', - 'rpc_ctrl_cmd_internal_control_gsp_trace_v', - 'rpc_ctrl_cmd_internal_control_gsp_trace_v28_00', - 'rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v', - 'rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09', - 'rpc_ctrl_cmd_nvlink_inband_send_data_v', - 'rpc_ctrl_cmd_nvlink_inband_send_data_v26_05', - 'rpc_ctrl_dbg_clear_all_sm_error_states_v', - 'rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C', - 'rpc_ctrl_dbg_clear_single_sm_error_state_v', - 'rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10', - 'rpc_ctrl_dbg_exec_reg_ops_v', 'rpc_ctrl_dbg_exec_reg_ops_v1A_10', - 'rpc_ctrl_dbg_get_mode_mmu_debug_v', - 'rpc_ctrl_dbg_get_mode_mmu_debug_v25_04', - 'rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v', - 'rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07', - 'rpc_ctrl_dbg_read_all_sm_error_states_v', - 'rpc_ctrl_dbg_read_all_sm_error_states_v21_06', - 'rpc_ctrl_dbg_read_single_sm_error_state_v', - 'rpc_ctrl_dbg_read_single_sm_error_state_v21_06', - 'rpc_ctrl_dbg_resume_context_v', - 'rpc_ctrl_dbg_resume_context_v1A_10', - 'rpc_ctrl_dbg_set_exception_mask_v', - 'rpc_ctrl_dbg_set_exception_mask_v1A_0C', - 'rpc_ctrl_dbg_set_mode_errbar_debug_v', - 'rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10', - 'rpc_ctrl_dbg_set_mode_mmu_debug_v', - 'rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10', - 'rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v', - 'rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07', - 'rpc_ctrl_dbg_set_next_stop_trigger_type_v', - 'rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10', - 'rpc_ctrl_dbg_set_single_sm_single_step_v', - 'rpc_ctrl_dbg_set_single_sm_single_step_v1C_02', - 'rpc_ctrl_dbg_suspend_context_v', - 'rpc_ctrl_dbg_suspend_context_v1A_10', - 'rpc_ctrl_dma_set_default_vaspace_v', - 'rpc_ctrl_dma_set_default_vaspace_v1A_0E', - 'rpc_ctrl_exec_partitions_create_v', - 'rpc_ctrl_exec_partitions_create_v24_05', - 'rpc_ctrl_exec_partitions_delete_v', - 'rpc_ctrl_exec_partitions_delete_v1F_0A', - 'rpc_ctrl_fabric_mem_stats_v', 'rpc_ctrl_fabric_mem_stats_v1E_0C', - 'rpc_ctrl_fabric_memory_describe_v', - 'rpc_ctrl_fabric_memory_describe_v1E_0C', - 'rpc_ctrl_fb_get_fs_info_v', 'rpc_ctrl_fb_get_fs_info_v24_00', - 'rpc_ctrl_fb_get_fs_info_v26_04', 'rpc_ctrl_fb_get_info_v2_v', - 'rpc_ctrl_fb_get_info_v2_v25_0A', - 'rpc_ctrl_fb_get_info_v2_v27_00', - 'rpc_ctrl_fifo_disable_channels_v', - 'rpc_ctrl_fifo_disable_channels_v1A_0A', - 'rpc_ctrl_fifo_set_channel_properties_v', - 'rpc_ctrl_fifo_set_channel_properties_v1A_16', - 'rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v', - 'rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23', - 'rpc_ctrl_fla_setup_instance_mem_block_v', - 'rpc_ctrl_fla_setup_instance_mem_block_v21_05', - 'rpc_ctrl_free_pma_stream_v', 'rpc_ctrl_free_pma_stream_v1A_1F', - 'rpc_ctrl_get_ce_pce_mask_v', 'rpc_ctrl_get_ce_pce_mask_v1A_0E', - 'rpc_ctrl_get_hs_credits_v', 'rpc_ctrl_get_hs_credits_v21_08', - 'rpc_ctrl_get_mmu_debug_mode_v', - 'rpc_ctrl_get_mmu_debug_mode_v1E_06', - 'rpc_ctrl_get_nvlink_status_v', - 'rpc_ctrl_get_nvlink_status_v23_04', - 'rpc_ctrl_get_nvlink_status_v28_09', - 'rpc_ctrl_get_p2p_caps_matrix_v', - 'rpc_ctrl_get_p2p_caps_matrix_v1A_0E', 'rpc_ctrl_get_p2p_caps_v', - 'rpc_ctrl_get_p2p_caps_v1F_0D', 'rpc_ctrl_get_p2p_caps_v2_v', - 'rpc_ctrl_get_p2p_caps_v2_v1F_0D', - 'rpc_ctrl_get_total_hs_credits_v', - 'rpc_ctrl_get_total_hs_credits_v21_08', - 'rpc_ctrl_get_zbc_clear_table_entry_v', - 'rpc_ctrl_get_zbc_clear_table_entry_v1A_0E', - 'rpc_ctrl_get_zbc_clear_table_v', - 'rpc_ctrl_get_zbc_clear_table_v1A_09', - 'rpc_ctrl_gpfifo_get_work_submit_token_v', - 'rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A', - 'rpc_ctrl_gpfifo_schedule_v', 'rpc_ctrl_gpfifo_schedule_v1A_0A', - 'rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v', - 'rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A', - 'rpc_ctrl_gpu_evict_ctx_v', 'rpc_ctrl_gpu_evict_ctx_v1A_1C', - 'rpc_ctrl_gpu_get_info_v2_v', 'rpc_ctrl_gpu_get_info_v2_v25_11', - 'rpc_ctrl_gpu_handle_vf_pri_fault_v', - 'rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09', - 'rpc_ctrl_gpu_initialize_ctx_v', - 'rpc_ctrl_gpu_initialize_ctx_v1A_0E', - 'rpc_ctrl_gpu_migratable_ops_v', - 'rpc_ctrl_gpu_migratable_ops_v21_07', - 'rpc_ctrl_gpu_promote_ctx_v', 'rpc_ctrl_gpu_promote_ctx_v1A_20', - 'rpc_ctrl_gpu_query_ecc_status_v', - 'rpc_ctrl_gpu_query_ecc_status_v24_06', - 'rpc_ctrl_gpu_query_ecc_status_v26_02', - 'rpc_ctrl_gr_ctxsw_preemption_bind_v', - 'rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E', - 'rpc_ctrl_gr_ctxsw_preemption_bind_v28_07', - 'rpc_ctrl_gr_ctxsw_zcull_bind_v', - 'rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E', - 'rpc_ctrl_gr_get_tpc_partition_mode_v', - 'rpc_ctrl_gr_get_tpc_partition_mode_v1C_04', - 'rpc_ctrl_gr_pc_sampling_mode_v', - 'rpc_ctrl_gr_pc_sampling_mode_v1A_1F', - 'rpc_ctrl_gr_set_ctxsw_preemption_mode_v', - 'rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E', - 'rpc_ctrl_gr_set_tpc_partition_mode_v', - 'rpc_ctrl_gr_set_tpc_partition_mode_v1C_04', - 'rpc_ctrl_grmgr_get_gr_fs_info_v', - 'rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D', - 'rpc_ctrl_internal_memsys_set_zbc_referenced_v', - 'rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05', - 'rpc_ctrl_internal_promote_fault_method_buffers_v', - 'rpc_ctrl_internal_promote_fault_method_buffers_v1E_07', - 'rpc_ctrl_internal_quiesce_pma_channel_v', - 'rpc_ctrl_internal_quiesce_pma_channel_v1C_08', - 'rpc_ctrl_internal_sriov_promote_pma_stream_v', - 'rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C', - 'rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v', - 'rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D', - 'rpc_ctrl_mc_service_interrupts_v', - 'rpc_ctrl_mc_service_interrupts_v1A_0E', - 'rpc_ctrl_nvenc_sw_session_update_info_v', - 'rpc_ctrl_nvenc_sw_session_update_info_v1A_09', - 'rpc_ctrl_nvlink_get_inband_received_data_v', - 'rpc_ctrl_nvlink_get_inband_received_data_v25_0C', - 'rpc_ctrl_perf_boost_v', 'rpc_ctrl_perf_boost_v1A_09', - 'rpc_ctrl_perf_rated_tdp_get_status_v', - 'rpc_ctrl_perf_rated_tdp_get_status_v1A_1F', - 'rpc_ctrl_perf_rated_tdp_set_control_v', - 'rpc_ctrl_perf_rated_tdp_set_control_v1A_1F', - 'rpc_ctrl_pm_area_pc_sampler_v', - 'rpc_ctrl_pm_area_pc_sampler_v21_0B', - 'rpc_ctrl_pma_stream_update_get_put_v', - 'rpc_ctrl_pma_stream_update_get_put_v1A_14', 'rpc_ctrl_preempt_v', - 'rpc_ctrl_preempt_v1A_0A', 'rpc_ctrl_release_ccu_prof_v', - 'rpc_ctrl_release_ccu_prof_v29_07', 'rpc_ctrl_release_hes_v', - 'rpc_ctrl_release_hes_v29_07', 'rpc_ctrl_reserve_ccu_prof_v', - 'rpc_ctrl_reserve_ccu_prof_v29_07', 'rpc_ctrl_reserve_hes_v', - 'rpc_ctrl_reserve_hes_v29_07', 'rpc_ctrl_reserve_hwpm_legacy_v', - 'rpc_ctrl_reserve_hwpm_legacy_v1A_0F', - 'rpc_ctrl_reserve_pm_area_smpc_v', - 'rpc_ctrl_reserve_pm_area_smpc_v1A_0F', - 'rpc_ctrl_reset_channel_v', 'rpc_ctrl_reset_channel_v1A_09', - 'rpc_ctrl_reset_isolated_channel_v', - 'rpc_ctrl_reset_isolated_channel_v1A_09', - 'rpc_ctrl_set_channel_interleave_level_v', - 'rpc_ctrl_set_channel_interleave_level_v1A_0A', - 'rpc_ctrl_set_hs_credits_v', 'rpc_ctrl_set_hs_credits_v21_08', - 'rpc_ctrl_set_timeslice_v', 'rpc_ctrl_set_timeslice_v1A_0A', - 'rpc_ctrl_set_tsg_interleave_level_v', - 'rpc_ctrl_set_tsg_interleave_level_v1A_0A', - 'rpc_ctrl_set_vgpu_fb_usage_v', - 'rpc_ctrl_set_vgpu_fb_usage_v1A_08', - 'rpc_ctrl_set_zbc_color_clear_v', - 'rpc_ctrl_set_zbc_color_clear_v1A_09', - 'rpc_ctrl_set_zbc_depth_clear_v', - 'rpc_ctrl_set_zbc_depth_clear_v1A_09', - 'rpc_ctrl_set_zbc_stencil_clear_v', - 'rpc_ctrl_set_zbc_stencil_clear_v27_06', - 'rpc_ctrl_stop_channel_v', 'rpc_ctrl_stop_channel_v1A_1E', - 'rpc_ctrl_subdevice_get_libos_heap_stats_v', - 'rpc_ctrl_subdevice_get_libos_heap_stats_v29_02', - 'rpc_ctrl_subdevice_get_p2p_caps_v', - 'rpc_ctrl_subdevice_get_p2p_caps_v21_02', - 'rpc_ctrl_subdevice_get_vgpu_heap_stats_v', - 'rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03', - 'rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06', - 'rpc_ctrl_timer_set_gr_tick_freq_v', - 'rpc_ctrl_timer_set_gr_tick_freq_v1A_1F', - 'rpc_ctrl_vaspace_copy_server_reserved_pdes_v', - 'rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04', - 'rpc_dce_rm_init_v', 'rpc_dce_rm_init_v01_00', - 'rpc_disable_channels_v', 'rpc_disable_channels_v1E_0B', - 'rpc_display_modeset_v', 'rpc_display_modeset_v01_00', - 'rpc_dump_protobuf_component_v', - 'rpc_dump_protobuf_component_v18_12', 'rpc_dup_object_v', - 'rpc_dup_object_v03_00', 'rpc_extdev_intr_service_v', - 'rpc_extdev_intr_service_v17_00', 'rpc_fecs_error_v', - 'rpc_fecs_error_v26_02', 'rpc_free_v', 'rpc_free_v03_00', - 'rpc_get_brand_caps_v', 'rpc_get_brand_caps_v25_12', - 'rpc_get_consolidated_gr_static_info_v', - 'rpc_get_consolidated_gr_static_info_v1B_04', - 'rpc_get_encoder_capacity_v', 'rpc_get_encoder_capacity_v07_00', - 'rpc_get_engine_utilization_v', - 'rpc_get_engine_utilization_v1F_0E', 'rpc_get_gsp_static_info_v', - 'rpc_get_gsp_static_info_v14_00', 'rpc_get_static_data_v', - 'rpc_get_static_data_v25_0E', 'rpc_get_static_data_v27_01', - 'rpc_gpu_exec_reg_ops_v', 'rpc_gpu_exec_reg_ops_v12_01', - 'rpc_gpuacct_perfmon_util_samples_v', - 'rpc_gpuacct_perfmon_util_samples_v1F_0E', - 'rpc_gsp_lockdown_notice_v', 'rpc_gsp_lockdown_notice_v17_00', - 'rpc_gsp_post_nocat_record_v', 'rpc_gsp_post_nocat_record_v01_00', - 'rpc_gsp_rm_alloc_v', 'rpc_gsp_rm_alloc_v03_00', - 'rpc_gsp_rm_control_v', 'rpc_gsp_rm_control_v03_00', - 'rpc_gsp_set_system_info_v', 'rpc_gsp_set_system_info_v17_00', - 'rpc_idle_channels_v', 'rpc_idle_channels_v03_00', - 'rpc_init_done_v', 'rpc_init_done_v17_00', 'rpc_invalidate_tlb_v', - 'rpc_invalidate_tlb_v23_03', 'rpc_log_v', 'rpc_log_v03_00', - 'rpc_map_memory_dma_v', 'rpc_map_memory_dma_v03_00', - 'rpc_message_header_v', 'rpc_message_header_v03_00', - 'rpc_message_rpc_union_field_v', - 'rpc_message_rpc_union_field_v03_00', - 'rpc_nvlink_fatal_error_recovery_v', - 'rpc_nvlink_fatal_error_recovery_v17_00', 'rpc_nvlink_fault_up_v', - 'rpc_nvlink_fault_up_v17_00', - 'rpc_nvlink_inband_received_data_1024_v', - 'rpc_nvlink_inband_received_data_1024_v17_00', - 'rpc_nvlink_inband_received_data_2048_v', - 'rpc_nvlink_inband_received_data_2048_v17_00', - 'rpc_nvlink_inband_received_data_256_v', - 'rpc_nvlink_inband_received_data_256_v17_00', - 'rpc_nvlink_inband_received_data_4096_v', - 'rpc_nvlink_inband_received_data_4096_v17_00', - 'rpc_nvlink_inband_received_data_512_v', - 'rpc_nvlink_inband_received_data_512_v17_00', - 'rpc_nvlink_is_gpu_degraded_v', - 'rpc_nvlink_is_gpu_degraded_v17_00', 'rpc_os_error_log_v', - 'rpc_os_error_log_v17_00', 'rpc_perf_bridgeless_info_update_v', - 'rpc_perf_bridgeless_info_update_v17_00', - 'rpc_perf_get_level_info_v', 'rpc_perf_get_level_info_v03_00', - 'rpc_perf_gpu_boost_sync_limits_callback_v', - 'rpc_perf_gpu_boost_sync_limits_callback_v17_00', - 'rpc_pfm_req_hndlr_state_sync_callback_v', - 'rpc_pfm_req_hndlr_state_sync_callback_v21_04', - 'rpc_post_event_v', 'rpc_post_event_v17_00', 'rpc_rc_triggered_v', - 'rpc_rc_triggered_v17_02', 'rpc_recovery_action_v', - 'rpc_recovery_action_v28_01', 'rpc_restore_hibernation_data_v', - 'rpc_restore_hibernation_data_v1E_0E', 'rpc_rg_line_intr_v', - 'rpc_rg_line_intr_v17_00', 'rpc_rm_api_control_v', - 'rpc_rm_api_control_v25_0D', 'rpc_rm_api_control_v25_0F', - 'rpc_rm_api_control_v25_10', 'rpc_rm_api_control_v25_14', - 'rpc_rm_api_control_v25_15', 'rpc_rm_api_control_v25_16', - 'rpc_rm_api_control_v25_17', 'rpc_rm_api_control_v25_18', - 'rpc_rm_api_control_v25_19', 'rpc_rm_api_control_v25_1A', - 'rpc_rm_api_control_v27_03', 'rpc_rm_api_control_v29_04', - 'rpc_rm_api_control_v29_09', 'rpc_run_cpu_sequencer_v', - 'rpc_run_cpu_sequencer_v17_00', 'rpc_save_hibernation_data_v', - 'rpc_save_hibernation_data_v1E_0E', - 'rpc_semaphore_schedule_callback_v', - 'rpc_semaphore_schedule_callback_v17_00', - 'rpc_set_guest_system_info_ext_v', - 'rpc_set_guest_system_info_ext_v15_02', - 'rpc_set_guest_system_info_ext_v25_1B', - 'rpc_set_guest_system_info_v', 'rpc_set_guest_system_info_v03_00', - 'rpc_set_page_directory_v', 'rpc_set_page_directory_v1E_05', - 'rpc_set_surface_properties_v', - 'rpc_set_surface_properties_v07_07', 'rpc_sim_read_v', - 'rpc_sim_read_v1E_01', 'rpc_sim_write_v', 'rpc_sim_write_v1E_01', - 'rpc_timed_semaphore_release_v', - 'rpc_timed_semaphore_release_v01_00', 'rpc_ucode_libos_print_v', - 'rpc_ucode_libos_print_v1E_08', 'rpc_unloading_guest_driver_v', - 'rpc_unloading_guest_driver_v1F_07', 'rpc_unmap_memory_dma_v', - 'rpc_unmap_memory_dma_v03_00', 'rpc_unset_page_directory_v', - 'rpc_unset_page_directory_v1E_05', 'rpc_update_bar_pde_v', - 'rpc_update_bar_pde_v15_00', 'rpc_update_gpm_guest_buffer_info_v', - 'rpc_update_gpm_guest_buffer_info_v27_01', - 'rpc_update_gsp_trace_v', 'rpc_update_gsp_trace_v01_00', - 'rpc_vgpu_config_event_v', 'rpc_vgpu_config_event_v17_00', - 'rpc_vgpu_gsp_mig_ci_config_v', - 'rpc_vgpu_gsp_mig_ci_config_v21_03', - 'rpc_vgpu_gsp_plugin_triggered_v', - 'rpc_vgpu_gsp_plugin_triggered_v17_00', - 'rpc_vgpu_pf_reg_read32_v', 'rpc_vgpu_pf_reg_read32_v15_00', - 'struct_ACPI_METHOD_DATA', 'struct_BIT_HEADER_V1_00', - 'struct_BIT_TOKEN_V1_00', 'struct_CAPS_METHOD_DATA', - 'struct_DOD_METHOD_DATA', 'struct_GSP_ACR_BOOT_GSP_RM_PARAMS', - 'struct_GSP_FMC_BOOT_PARAMS', 'struct_GSP_FMC_INIT_PARAMS', - 'struct_GSP_MSG_QUEUE_ELEMENT', 'struct_GSP_RM_PARAMS', - 'struct_GSP_SPDM_PARAMS', 'struct_GSP_VF_INFO', - 'struct_GspStaticConfigInfo_t', 'struct_GspSystemInfo', - 'struct_JT_METHOD_DATA', 'struct_MUX_METHOD_DATA', - 'struct_MUX_METHOD_DATA_ELEMENT', - 'struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C', - 'struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C', - 'struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C', - 'struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C', - 'struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C', - 'struct_NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D', - 'struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00', - 'struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05', - 'struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05', - 'struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00', - 'struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS', - 'struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04', - 'struct_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06', - 'struct_NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C', - 'struct_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C', - 'struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03', - 'struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08', - 'struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03', - 'struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07', - 'struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO', - 'struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09', - 'struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02', - 'struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03', - 'struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06', - 'struct_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09', - 'struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F', - 'struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS_v26_04', - 'struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS_v26_04', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS_v26_04', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D', - 'struct_NV2080_CTRL_FB_FS_INFO_QUERY_v26_04', - 'struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00', - 'struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v26_04', - 'struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A', - 'struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00', - 'struct_NV2080_CTRL_FB_INFO_v1A_15', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00', - 'struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23', - 'struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C', - 'struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04', - 'struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02', - 'struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00', - 'struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01', - 'struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11', - 'struct_NV2080_CTRL_GPU_INFO_v25_11', - 'struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00', - 'struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07', - 'struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02', - 'struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20', - 'struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01', - 'struct_NV2080_CTRL_GPU_REG_OP_v03_00', - 'struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D', - 'struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01', - 'struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v28_07', - 'struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00', - 'struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F', - 'struct_NV2080_CTRL_GR_ROUTE_INFO_v12_01', - 'struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01', - 'struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS_v29_02', - 'struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04', - 'struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01', - 'struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02', - 'struct_NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09', - 'struct_NV2080_CTRL_NVLINK_FATAL_ERROR_RECOVERY_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C', - 'struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00', - 'struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D', - 'struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v28_09', - 'struct_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00', - 'struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E', - 'struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00', - 'struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00', - 'struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E', - 'struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F', - 'struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F', - 'struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS_v26_04', - 'struct_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00', - 'struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06', - 'struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00', - 'struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06', - 'struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07', - 'struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06', - 'struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06', - 'struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07', - 'struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02', - 'struct_NV83DE_MMU_FAULT_INFO_v16_03', - 'struct_NV83DE_SM_ERROR_STATE_REGISTERS_v21_06', - 'struct_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01', - 'struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07', - 'struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07', - 'struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00', - 'struct_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00', - 'struct_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00', - 'struct_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00', - 'struct_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06', - 'struct_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B', - 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04', - 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04', - 'struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02', - 'struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07', - 'struct_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A', - 'struct_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00', - 'struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00', - 'struct_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02', - 'struct_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E', - 'struct_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02', - 'struct_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00', - 'struct_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07', - 'struct_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01', - 'struct_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14', - 'struct_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F', - 'struct_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F', - 'struct_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08', - 'struct_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08', - 'struct_NVB0CC_CTRL_HES_RESERVATION_UNION_v29_07', - 'struct_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08', - 'struct_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C', - 'struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08', - 'struct_NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08', - 'struct_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14', - 'struct_NVB0CC_CTRL_RELEASE_HES_PARAMS_v29_07', - 'struct_NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_v29_07', - 'struct_NVB0CC_CTRL_RESERVE_HES_CWD_PARAMS_v29_07', - 'struct_NVB0CC_CTRL_RESERVE_HES_PARAMS_v29_07', - 'struct_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F', - 'struct_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F', - 'struct_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08', - 'struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00', - 'struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04', - 'struct_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05', - 'struct_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05', - 'struct_NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05', - 'struct_NVOS00_PARAMETERS_v03_00', - 'struct_NVOS21_PARAMETERS_v03_00', - 'struct_NVOS46_PARAMETERS_v03_00', - 'struct_NVOS47_PARAMETERS_v03_00', - 'struct_NVOS54_PARAMETERS_v03_00', - 'struct_NVOS55_PARAMETERS_v03_00', - 'struct_NV_CHANNEL_ALLOC_PARAMS_v1F_04', - 'struct_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00', - 'struct_NV_GR_ALLOCATION_PARAMETERS_v1A_17', - 'struct_NV_MEMORY_DESC_PARAMS_v18_01', - 'struct_PACKED_REGISTRY_ENTRY', 'struct_PACKED_REGISTRY_TABLE', - 'struct_PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F', - 'struct_UpdateBarPde_v15_00', - 'struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS', - 'struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS', - 'struct__NV_PCI_DATA_EXT_STRUCT', 'struct__PCI_DATA_STRUCT', - 'struct__PCI_EXP_ROM_NBSI', 'struct__PCI_EXP_ROM_STANDARD', - 'struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00', - 'struct_alloc_object_FERMI_VASPACE_A_v03_00', - 'struct_alloc_object_GF100_DISP_SW_v03_00', - 'struct_alloc_object_GT212_DMA_COPY_v03_00', - 'struct_alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08', - 'struct_alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C', - 'struct_alloc_object_NV2081_ALLOC_PARAMETERS_v25_08', - 'struct_alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02', - 'struct_alloc_object_NV503C_ALLOC_PARAMETERS_v18_15', - 'struct_alloc_object_NV50_TESLA_v03_00', - 'struct_alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00', - 'struct_alloc_object_NVB0B0_VIDEO_DECODER_v03_00', - 'struct_alloc_object_NVB1CC_ALLOC_PARAMETERS_v1A_03', - 'struct_alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03', - 'struct_alloc_object_NVC4B0_VIDEO_DECODER_v12_02', - 'struct_alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00', - 'struct_alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06', - 'struct_alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01', - 'struct_alloc_object_NVC9FA_VIDEO_OFA_v1F_00', - 'struct_alloc_object_NVC9FA_VIDEO_OFA_v29_06', - 'struct_alloc_object_NVD0B7_VIDEO_ENCODER_v03_00', - 'struct_alloc_object_NVENC_SW_SESSION_v06_01', - 'struct_alloc_object_NVFBC_SW_SESSION_v12_04', - 'struct_alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03', - 'struct_alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02', - 'struct_alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B', - 'struct_c__SA_ACPI_DATA', 'struct_c__SA_ACPI_DSM_CACHE', - 'struct_c__SA_BIT_DATA_BIOSDATA_BINVER', - 'struct_c__SA_BIT_DATA_FALCON_DATA_V2', 'struct_c__SA_BUSINFO', - 'struct_c__SA_EcidManufacturingInfo', - 'struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3', - 'struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1', - 'struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1', - 'struct_c__SA_FALCON_UCODE_DESC_HEADER', - 'struct_c__SA_FALCON_UCODE_DESC_V3', - 'struct_c__SA_FALCON_UCODE_TABLE_ENTRY_V1', - 'struct_c__SA_FALCON_UCODE_TABLE_HDR_V1', - 'struct_c__SA_FWSECLIC_FRTS_CMD', - 'struct_c__SA_FWSECLIC_FRTS_REGION_DESC', - 'struct_c__SA_FWSECLIC_READ_VBIOS_DESC', - 'struct_c__SA_FW_WPR_LAYOUT_OFFSET', - 'struct_c__SA_GSP_ARGUMENTS_CACHED', - 'struct_c__SA_GSP_ARGUMENTS_CACHED_profilerArgs', - 'struct_c__SA_GSP_PCIE_CONFIG_REG', - 'struct_c__SA_GSP_SR_INIT_ARGUMENTS', - 'struct_c__SA_GspFwHeapFreeList', - 'struct_c__SA_GspFwHeapFreeRegion', 'struct_c__SA_GspFwSRMeta', - 'struct_c__SA_GspFwWprMeta', 'struct_c__SA_GspFwWprMeta_0_0', - 'struct_c__SA_GspFwWprMeta_0_1', 'struct_c__SA_GspFwWprMeta_1_0', - 'struct_c__SA_GspFwWprMeta_1_1', - 'struct_c__SA_LibosMemoryRegionInitArgument', - 'struct_c__SA_MCTP_HEADER', - 'struct_c__SA_MESSAGE_QUEUE_INIT_ARGUMENTS', - 'struct_c__SA_NVDM_PAYLOAD_COT', - 'struct_c__SA_RM_RISCV_UCODE_DESC', 'struct_c__SA_msgqMetadata', - 'struct_c__SA_msgqRxHeader', 'struct_c__SA_msgqTxHeader', - 'struct_gpu_exec_reg_ops_v12_01', - 'struct_idle_channel_list_v03_00', 'struct_pte_desc', - 'struct_rpc_alloc_channel_dma_v1F_04', - 'struct_rpc_alloc_event_v03_00', 'struct_rpc_alloc_memory_v13_01', - 'struct_rpc_alloc_object_v25_08', - 'struct_rpc_alloc_object_v26_00', - 'struct_rpc_alloc_object_v27_00', - 'struct_rpc_alloc_object_v29_06', 'struct_rpc_alloc_root_v07_00', - 'struct_rpc_alloc_share_device_v03_00', - 'struct_rpc_alloc_subdevice_v08_01', - 'struct_rpc_cleanup_surface_v03_00', - 'struct_rpc_ctrl_alloc_pma_stream_v1A_14', - 'struct_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F', - 'struct_rpc_ctrl_bind_pm_resources_v1A_0F', - 'struct_rpc_ctrl_bus_set_p2p_mapping_v21_03', - 'struct_rpc_ctrl_bus_set_p2p_mapping_v29_08', - 'struct_rpc_ctrl_bus_unset_p2p_mapping_v21_03', - 'struct_rpc_ctrl_cmd_internal_control_gsp_trace_v28_00', - 'struct_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09', - 'struct_rpc_ctrl_cmd_nvlink_inband_send_data_v26_05', - 'struct_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C', - 'struct_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10', - 'struct_rpc_ctrl_dbg_exec_reg_ops_v1A_10', - 'struct_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04', - 'struct_rpc_ctrl_dbg_get_mode_mmu_gcc_debug_v29_07', - 'struct_rpc_ctrl_dbg_read_all_sm_error_states_v21_06', - 'struct_rpc_ctrl_dbg_read_single_sm_error_state_v21_06', - 'struct_rpc_ctrl_dbg_resume_context_v1A_10', - 'struct_rpc_ctrl_dbg_set_exception_mask_v1A_0C', - 'struct_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10', - 'struct_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10', - 'struct_rpc_ctrl_dbg_set_mode_mmu_gcc_debug_v29_07', - 'struct_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10', - 'struct_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02', - 'struct_rpc_ctrl_dbg_suspend_context_v1A_10', - 'struct_rpc_ctrl_dma_set_default_vaspace_v1A_0E', - 'struct_rpc_ctrl_exec_partitions_create_v24_05', - 'struct_rpc_ctrl_exec_partitions_delete_v1F_0A', - 'struct_rpc_ctrl_fabric_mem_stats_v1E_0C', - 'struct_rpc_ctrl_fabric_memory_describe_v1E_0C', - 'struct_rpc_ctrl_fb_get_fs_info_v24_00', - 'struct_rpc_ctrl_fb_get_fs_info_v26_04', - 'struct_rpc_ctrl_fb_get_info_v2_v25_0A', - 'struct_rpc_ctrl_fb_get_info_v2_v27_00', - 'struct_rpc_ctrl_fifo_disable_channels_v1A_0A', - 'struct_rpc_ctrl_fifo_set_channel_properties_v1A_16', - 'struct_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23', - 'struct_rpc_ctrl_fla_setup_instance_mem_block_v21_05', - 'struct_rpc_ctrl_free_pma_stream_v1A_1F', - 'struct_rpc_ctrl_get_ce_pce_mask_v1A_0E', - 'struct_rpc_ctrl_get_hs_credits_v21_08', - 'struct_rpc_ctrl_get_mmu_debug_mode_v1E_06', - 'struct_rpc_ctrl_get_nvlink_status_v23_04', - 'struct_rpc_ctrl_get_nvlink_status_v28_09', - 'struct_rpc_ctrl_get_p2p_caps_matrix_v1A_0E', - 'struct_rpc_ctrl_get_p2p_caps_v1F_0D', - 'struct_rpc_ctrl_get_p2p_caps_v2_v1F_0D', - 'struct_rpc_ctrl_get_total_hs_credits_v21_08', - 'struct_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E', - 'struct_rpc_ctrl_get_zbc_clear_table_v1A_09', - 'struct_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A', - 'struct_rpc_ctrl_gpfifo_schedule_v1A_0A', - 'struct_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A', - 'struct_rpc_ctrl_gpu_evict_ctx_v1A_1C', - 'struct_rpc_ctrl_gpu_get_info_v2_v25_11', - 'struct_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09', - 'struct_rpc_ctrl_gpu_initialize_ctx_v1A_0E', - 'struct_rpc_ctrl_gpu_migratable_ops_v21_07', - 'struct_rpc_ctrl_gpu_promote_ctx_v1A_20', - 'struct_rpc_ctrl_gpu_query_ecc_status_v24_06', - 'struct_rpc_ctrl_gpu_query_ecc_status_v26_02', - 'struct_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E', - 'struct_rpc_ctrl_gr_ctxsw_preemption_bind_v28_07', - 'struct_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E', - 'struct_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04', - 'struct_rpc_ctrl_gr_pc_sampling_mode_v1A_1F', - 'struct_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E', - 'struct_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04', - 'struct_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D', - 'struct_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05', - 'struct_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07', - 'struct_rpc_ctrl_internal_quiesce_pma_channel_v1C_08', - 'struct_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C', - 'struct_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D', - 'struct_rpc_ctrl_mc_service_interrupts_v1A_0E', - 'struct_rpc_ctrl_nvenc_sw_session_update_info_v1A_09', - 'struct_rpc_ctrl_nvlink_get_inband_received_data_v25_0C', - 'struct_rpc_ctrl_perf_boost_v1A_09', - 'struct_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F', - 'struct_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F', - 'struct_rpc_ctrl_pm_area_pc_sampler_v21_0B', - 'struct_rpc_ctrl_pma_stream_update_get_put_v1A_14', - 'struct_rpc_ctrl_preempt_v1A_0A', - 'struct_rpc_ctrl_release_ccu_prof_v29_07', - 'struct_rpc_ctrl_release_hes_v29_07', - 'struct_rpc_ctrl_reserve_ccu_prof_v29_07', - 'struct_rpc_ctrl_reserve_hes_v29_07', - 'struct_rpc_ctrl_reserve_hwpm_legacy_v1A_0F', - 'struct_rpc_ctrl_reserve_pm_area_smpc_v1A_0F', - 'struct_rpc_ctrl_reset_channel_v1A_09', - 'struct_rpc_ctrl_reset_isolated_channel_v1A_09', - 'struct_rpc_ctrl_set_channel_interleave_level_v1A_0A', - 'struct_rpc_ctrl_set_hs_credits_v21_08', - 'struct_rpc_ctrl_set_timeslice_v1A_0A', - 'struct_rpc_ctrl_set_tsg_interleave_level_v1A_0A', - 'struct_rpc_ctrl_set_vgpu_fb_usage_v1A_08', - 'struct_rpc_ctrl_set_zbc_color_clear_v1A_09', - 'struct_rpc_ctrl_set_zbc_depth_clear_v1A_09', - 'struct_rpc_ctrl_set_zbc_stencil_clear_v27_06', - 'struct_rpc_ctrl_stop_channel_v1A_1E', - 'struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02', - 'struct_rpc_ctrl_subdevice_get_p2p_caps_v21_02', - 'struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_03', - 'struct_rpc_ctrl_subdevice_get_vgpu_heap_stats_v28_06', - 'struct_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F', - 'struct_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04', - 'struct_rpc_dce_rm_init_v01_00', - 'struct_rpc_disable_channels_v1E_0B', - 'struct_rpc_display_modeset_v01_00', - 'struct_rpc_dump_protobuf_component_v18_12', - 'struct_rpc_dup_object_v03_00', - 'struct_rpc_extdev_intr_service_v17_00', - 'struct_rpc_fecs_error_v26_02', 'struct_rpc_free_v03_00', - 'struct_rpc_get_brand_caps_v25_12', - 'struct_rpc_get_consolidated_gr_static_info_v1B_04', - 'struct_rpc_get_encoder_capacity_v07_00', - 'struct_rpc_get_engine_utilization_v1F_0E', - 'struct_rpc_get_gsp_static_info_v14_00', - 'struct_rpc_get_static_data_v25_0E', - 'struct_rpc_get_static_data_v27_01', - 'struct_rpc_gpu_exec_reg_ops_v12_01', - 'struct_rpc_gpuacct_perfmon_util_samples_v1F_0E', - 'struct_rpc_gsp_lockdown_notice_v17_00', - 'struct_rpc_gsp_post_nocat_record_v01_00', - 'struct_rpc_gsp_rm_alloc_v03_00', - 'struct_rpc_gsp_rm_control_v03_00', - 'struct_rpc_gsp_set_system_info_v17_00', - 'struct_rpc_idle_channels_v03_00', 'struct_rpc_init_done_v17_00', - 'struct_rpc_invalidate_tlb_v23_03', 'struct_rpc_log_v03_00', - 'struct_rpc_map_memory_dma_v03_00', - 'struct_rpc_message_header_v03_00', - 'struct_rpc_nvlink_fatal_error_recovery_v17_00', - 'struct_rpc_nvlink_fault_up_v17_00', - 'struct_rpc_nvlink_inband_received_data_1024_v17_00', - 'struct_rpc_nvlink_inband_received_data_2048_v17_00', - 'struct_rpc_nvlink_inband_received_data_256_v17_00', - 'struct_rpc_nvlink_inband_received_data_4096_v17_00', - 'struct_rpc_nvlink_inband_received_data_512_v17_00', - 'struct_rpc_nvlink_is_gpu_degraded_v17_00', - 'struct_rpc_os_error_log_v17_00', - 'struct_rpc_perf_bridgeless_info_update_v17_00', - 'struct_rpc_perf_get_level_info_v03_00', - 'struct_rpc_perf_gpu_boost_sync_limits_callback_v17_00', - 'struct_rpc_pfm_req_hndlr_state_sync_callback_v21_04', - 'struct_rpc_post_event_v17_00', 'struct_rpc_rc_triggered_v17_02', - 'struct_rpc_recovery_action_v28_01', - 'struct_rpc_restore_hibernation_data_v1E_0E', - 'struct_rpc_rg_line_intr_v17_00', - 'struct_rpc_rm_api_control_v25_0D', - 'struct_rpc_rm_api_control_v25_0F', - 'struct_rpc_rm_api_control_v25_10', - 'struct_rpc_rm_api_control_v25_14', - 'struct_rpc_rm_api_control_v25_15', - 'struct_rpc_rm_api_control_v25_16', - 'struct_rpc_rm_api_control_v25_17', - 'struct_rpc_rm_api_control_v25_18', - 'struct_rpc_rm_api_control_v25_19', - 'struct_rpc_rm_api_control_v25_1A', - 'struct_rpc_rm_api_control_v27_03', - 'struct_rpc_rm_api_control_v29_04', - 'struct_rpc_rm_api_control_v29_09', - 'struct_rpc_run_cpu_sequencer_v17_00', - 'struct_rpc_save_hibernation_data_v1E_0E', - 'struct_rpc_semaphore_schedule_callback_v17_00', - 'struct_rpc_set_guest_system_info_ext_v15_02', - 'struct_rpc_set_guest_system_info_ext_v25_1B', - 'struct_rpc_set_guest_system_info_v03_00', - 'struct_rpc_set_page_directory_v1E_05', - 'struct_rpc_set_surface_properties_v07_07', - 'struct_rpc_sim_read_v1E_01', 'struct_rpc_sim_write_v1E_01', - 'struct_rpc_timed_semaphore_release_v01_00', - 'struct_rpc_ucode_libos_print_v1E_08', - 'struct_rpc_unloading_guest_driver_v1F_07', - 'struct_rpc_unmap_memory_dma_v03_00', - 'struct_rpc_unset_page_directory_v1E_05', - 'struct_rpc_update_bar_pde_v15_00', - 'struct_rpc_update_gpm_guest_buffer_info_v27_01', - 'struct_rpc_update_gsp_trace_v01_00', - 'struct_rpc_vgpu_config_event_v17_00', - 'struct_rpc_vgpu_gsp_mig_ci_config_v21_03', - 'struct_rpc_vgpu_gsp_plugin_triggered_v17_00', - 'struct_rpc_vgpu_pf_reg_read32_v15_00', - 'union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D', - 'union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04', - 'union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D', - 'union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04', - 'union__PCI_EXP_ROM', 'union_alloc_object_params_v25_08', - 'union_alloc_object_params_v26_00', - 'union_alloc_object_params_v27_00', - 'union_alloc_object_params_v29_06', 'union_c__SA_GspFwWprMeta_0', - 'union_c__SA_GspFwWprMeta_1', 'union_pte_desc_0', - 'union_rpc_message_rpc_union_field_v03_00', - 'union_vgpuGetEngineUtilization_data_v1F_0E'] diff --git a/tinygrad/runtime/autogen/nv_gpu.py b/tinygrad/runtime/autogen/nv_gpu.py index 4b0fb27caf..83b7a4328d 100644 --- a/tinygrad/runtime/autogen/nv_gpu.py +++ b/tinygrad/runtime/autogen/nv_gpu.py @@ -1,38764 +1,20570 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-include', '/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc/nvtypes.h', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/kernel-open/nvidia-uvm', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/kernel-open/common/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/nvidia/arch/nvalloc/unix/include', '-I/tmp/open-gpu-kernel-modules-81fe4fb417c8ac3b9bdcc1d56827d116743892a5/src/common/sdk/nvidia/inc/ctrl'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -__CLC6C0QMD_H__ = True # macro -NVC6C0_QMDV02_03_OUTER_PUT = (30 , 0) # macro -NVC6C0_QMDV02_03_OUTER_OVERFLOW = (31 , 31) # macro -NVC6C0_QMDV02_03_OUTER_GET = (62 , 32) # macro -NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW = (63 , 63) # macro -NVC6C0_QMDV02_03_INNER_GET = (94 , 64) # macro -NVC6C0_QMDV02_03_INNER_OVERFLOW = (95 , 95) # macro -NVC6C0_QMDV02_03_INNER_PUT = (126 , 96) # macro -NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVC6C0_QMDV02_03_QMD_GROUP_ID = (133 , 128) # macro -NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE = (134 , 134) # macro -NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION = (135 , 135) # macro -NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_IS_QUEUE = (136 , 136) # macro -NVC6C0_QMDV02_03_IS_QUEUE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_IS_QUEUE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137 , 137) # macro -NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 = (138 , 138) # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 = (139 , 139) # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS = (140 , 140) # macro -NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE = (141 , 141) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE = (142 , 142) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE = 0x00000000 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID = 0x00000001 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY = (143 , 143) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_QMD_RESERVED_B = (159 , 144) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_C = (185 , 185) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE = (186 , 186) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187 , 187) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE = (188 , 188) # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE = (189 , 189) # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE = (190 , 190) # macro -NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE = (191 , 191) # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME = (223 , 192) # macro -NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME = (239 , 224) # macro -NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME = (255 , 240) # macro -NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287 , 256) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER = (319 , 288) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER = (327 , 320) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_D = (335 , 328) # macro -NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE = (351 , 336) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID = (357 , 352) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365 , 358) # macro -NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE = (366 , 366) # macro -NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE = (367 , 367) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE = (369 , 368) # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS = (370 , 370) # macro -NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE = (371 , 371) # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT = (378 , 378) # macro -NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVC6C0_QMDV02_03_SAMPLER_INDEX = (382 , 382) # macro -NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVC6C0_QMDV02_03_CTA_RASTER_WIDTH = (415 , 384) # macro -NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT = (431 , 416) # macro -NVC6C0_QMDV02_03_QMD_RESERVED13A = (447 , 432) # macro -NVC6C0_QMDV02_03_CTA_RASTER_DEPTH = (463 , 448) # macro -NVC6C0_QMDV02_03_QMD_RESERVED14A = (479 , 464) # macro -NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER = (511 , 480) # macro -NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD = (529 , 522) # macro -NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 = (534 , 530) # macro -NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE = (561 , 544) # macro -NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568 , 562) # macro -NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575 , 569) # macro -NVC6C0_QMDV02_03_QMD_VERSION = (579 , 576) # macro -NVC6C0_QMDV02_03_QMD_MAJOR_VERSION = (583 , 580) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_H = (591 , 584) # macro -NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 = (607 , 592) # macro -NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 = (623 , 608) # macro -NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 = (639 , 624) # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID(i): # macro - return ((640+(i)*1) , (640+(i)*1)) -NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_REGISTER_COUNT_V = (656 , 648) # macro -NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663 , 657) # macro -NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM = (671 , 664) # macro -NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER = (703 , 672) # macro -NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER = (735 , 704) # macro -NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER = (767 , 736) # macro -NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER = (775 , 768) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_J = (783 , 776) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP = (790 , 788) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_03_QMD_RESERVED_K = (791 , 791) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT = (793 , 792) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE = (794 , 794) # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE = (799 , 799) # macro -NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE0_PAYLOAD = (831 , 800) # macro -NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER = (863 , 832) # macro -NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER = (871 , 864) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_L = (879 , 872) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP = (886 , 884) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_03_QMD_RESERVED_M = (887 , 887) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT = (889 , 888) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE = (890 , 890) # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE = (895 , 895) # macro -NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_03_RELEASE1_PAYLOAD = (927 , 896) # macro -NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE = (951 , 928) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_N = (954 , 952) # macro -NVC6C0_QMDV02_03_BARRIER_COUNT = (959 , 955) # macro -NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983 , 960) # macro -NVC6C0_QMDV02_03_REGISTER_COUNT = (991 , 984) # macro -NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000 , 992) # macro -NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE = (1009 , 1001) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_A = (1015 , 1010) # macro -NVC6C0_QMDV02_03_SASS_VERSION = (1023 , 1016) # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i): # macro - return ((1055+(i)*64) , (1024+(i)*64)) -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i): # macro - return ((1072+(i)*64) , (1056+(i)*64)) -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i): # macro - return ((1073+(i)*64) , (1073+(i)*64)) -NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1074+(i)*64) , (1074+(i)*64)) -NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*64) , (1075+(i)*64)) -NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER = (1567 , 1536) # macro -NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER = (1584 , 1568) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_S = (1599 , 1585) # macro -NVC6C0_QMDV02_03_HW_ONLY_INNER_GET = (1630 , 1600) # macro -NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631 , 1631) # macro -NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT = (1662 , 1632) # macro -NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE = (1663 , 1663) # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693 , 1664) # macro -NVC6C0_QMDV02_03_QMD_RESERVED_Q = (1694 , 1694) # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695 , 1695) # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727 , 1696) # macro -NVC6C0_QMDV02_03_QMD_SPARE_G = (1759 , 1728) # macro -NVC6C0_QMDV02_03_QMD_SPARE_H = (1791 , 1760) # macro -NVC6C0_QMDV02_03_QMD_SPARE_I = (1823 , 1792) # macro -NVC6C0_QMDV02_03_QMD_SPARE_J = (1855 , 1824) # macro -NVC6C0_QMDV02_03_QMD_SPARE_K = (1887 , 1856) # macro -NVC6C0_QMDV02_03_QMD_SPARE_L = (1919 , 1888) # macro -NVC6C0_QMDV02_03_QMD_SPARE_M = (1951 , 1920) # macro -NVC6C0_QMDV02_03_QMD_SPARE_N = (1983 , 1952) # macro -NVC6C0_QMDV02_03_DEBUG_ID_UPPER = (2015 , 1984) # macro -NVC6C0_QMDV02_03_DEBUG_ID_LOWER = (2047 , 2016) # macro -NVC6C0_QMDV02_04_OUTER_PUT = (30 , 0) # macro -NVC6C0_QMDV02_04_OUTER_OVERFLOW = (31 , 31) # macro -NVC6C0_QMDV02_04_OUTER_GET = (62 , 32) # macro -NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW = (63 , 63) # macro -NVC6C0_QMDV02_04_INNER_GET = (94 , 64) # macro -NVC6C0_QMDV02_04_INNER_OVERFLOW = (95 , 95) # macro -NVC6C0_QMDV02_04_INNER_PUT = (126 , 96) # macro -NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVC6C0_QMDV02_04_QMD_GROUP_ID = (133 , 128) # macro -NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE = (134 , 134) # macro -NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION = (135 , 135) # macro -NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_IS_QUEUE = (136 , 136) # macro -NVC6C0_QMDV02_04_IS_QUEUE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_IS_QUEUE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137 , 137) # macro -NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 = (138 , 138) # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 = (139 , 139) # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS = (140 , 140) # macro -NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE = (141 , 141) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION = (144 , 142) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH = (145 , 145) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE = (146 , 146) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION = (149 , 147) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH = (150 , 150) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_DEPENDENCE_COUNTER = (157 , 151) # macro -NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION = (158 , 158) # macro -NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_B = (159 , 159) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST = (185 , 185) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE = (186 , 186) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187 , 187) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE = (188 , 188) # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE = (189 , 189) # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE = (190 , 190) # macro -NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE = (191 , 191) # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME = (223 , 192) # macro -NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME = (239 , 224) # macro -NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME = (255 , 240) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287 , 256) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER = (319 , 288) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER = (327 , 320) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_D = (335 , 328) # macro -NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE = (351 , 336) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID = (357 , 352) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365 , 358) # macro -NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE = (366 , 366) # macro -NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE = (367 , 367) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE = (369 , 368) # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS = (370 , 370) # macro -NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE = (371 , 371) # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT = (378 , 378) # macro -NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVC6C0_QMDV02_04_SAMPLER_INDEX = (382 , 382) # macro -NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE = (383 , 383) # macro -NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_CTA_RASTER_WIDTH = (415 , 384) # macro -NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT = (431 , 416) # macro -NVC6C0_QMDV02_04_QMD_RESERVED13A = (447 , 432) # macro -NVC6C0_QMDV02_04_CTA_RASTER_DEPTH = (463 , 448) # macro -NVC6C0_QMDV02_04_QMD_RESERVED14A = (479 , 464) # macro -NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER = (511 , 480) # macro -NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD = (529 , 522) # macro -NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 = (534 , 530) # macro -NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE = (561 , 544) # macro -NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568 , 562) # macro -NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575 , 569) # macro -NVC6C0_QMDV02_04_QMD_VERSION = (579 , 576) # macro -NVC6C0_QMDV02_04_QMD_MAJOR_VERSION = (583 , 580) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_H = (591 , 584) # macro -NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 = (607 , 592) # macro -NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 = (623 , 608) # macro -NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 = (639 , 624) # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID(i): # macro - return ((640+(i)*1) , (640+(i)*1)) -NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_REGISTER_COUNT_V = (656 , 648) # macro -NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663 , 657) # macro -NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM = (671 , 664) # macro -NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER = (703 , 672) # macro -NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER = (735 , 704) # macro -NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER = (767 , 736) # macro -NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER = (775 , 768) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_J = (783 , 776) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP = (790 , 788) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_K = (791 , 791) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT = (793 , 792) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE = (794 , 794) # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE = (799 , 799) # macro -NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE0_PAYLOAD = (831 , 800) # macro -NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER = (863 , 832) # macro -NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER = (871 , 864) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_L = (879 , 872) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP = (886 , 884) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_M = (887 , 887) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT = (889 , 888) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE = (890 , 890) # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE = (895 , 895) # macro -NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV02_04_RELEASE1_PAYLOAD = (927 , 896) # macro -NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE = (951 , 928) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_N = (954 , 952) # macro -NVC6C0_QMDV02_04_BARRIER_COUNT = (959 , 955) # macro -NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983 , 960) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_G = (991 , 984) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000 , 992) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE = (1009 , 1001) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE = (1011 , 1010) # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVC6C0_QMDV02_04_QMD_RESERVED_A = (1015 , 1012) # macro -NVC6C0_QMDV02_04_SASS_VERSION = (1023 , 1016) # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i): # macro - return ((1055+(i)*64) , (1024+(i)*64)) -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i): # macro - return ((1072+(i)*64) , (1056+(i)*64)) -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i): # macro - return ((1073+(i)*64) , (1073+(i)*64)) -NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1074+(i)*64) , (1074+(i)*64)) -NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -def NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*64) , (1075+(i)*64)) -NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER = (1567 , 1536) # macro -NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER = (1584 , 1568) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_S = (1599 , 1585) # macro -NVC6C0_QMDV02_04_HW_ONLY_INNER_GET = (1630 , 1600) # macro -NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631 , 1631) # macro -NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT = (1662 , 1632) # macro -NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE = (1663 , 1663) # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693 , 1664) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_Q = (1694 , 1694) # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695 , 1695) # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727 , 1696) # macro -NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER = (1734 , 1728) # macro -NVC6C0_QMDV02_04_QMD_RESERVED_I = (1759 , 1735) # macro -NVC6C0_QMDV02_04_QMD_SPARE_H = (1791 , 1760) # macro -NVC6C0_QMDV02_04_QMD_SPARE_I = (1823 , 1792) # macro -NVC6C0_QMDV02_04_QMD_SPARE_J = (1855 , 1824) # macro -NVC6C0_QMDV02_04_QMD_SPARE_K = (1887 , 1856) # macro -NVC6C0_QMDV02_04_QMD_SPARE_L = (1919 , 1888) # macro -NVC6C0_QMDV02_04_QMD_SPARE_M = (1951 , 1920) # macro -NVC6C0_QMDV02_04_QMD_SPARE_N = (1983 , 1952) # macro -NVC6C0_QMDV02_04_DEBUG_ID_UPPER = (2015 , 1984) # macro -NVC6C0_QMDV02_04_DEBUG_ID_LOWER = (2047 , 2016) # macro -NVC6C0_QMDV03_00_OUTER_PUT = (30 , 0) # macro -NVC6C0_QMDV03_00_OUTER_OVERFLOW = (31 , 31) # macro -NVC6C0_QMDV03_00_OUTER_GET = (62 , 32) # macro -NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW = (63 , 63) # macro -NVC6C0_QMDV03_00_INNER_GET = (94 , 64) # macro -NVC6C0_QMDV03_00_INNER_OVERFLOW = (95 , 95) # macro -NVC6C0_QMDV03_00_INNER_PUT = (126 , 96) # macro -NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVC6C0_QMDV03_00_QMD_GROUP_ID = (133 , 128) # macro -NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE = (134 , 134) # macro -NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION = (135 , 135) # macro -NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_IS_QUEUE = (136 , 136) # macro -NVC6C0_QMDV03_00_IS_QUEUE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_IS_QUEUE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137 , 137) # macro -NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED04A = (139 , 138) # macro -NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS = (140 , 140) # macro -NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED04B = (141 , 141) # macro -NVC6C0_QMDV03_00_DEPENDENCE_COUNTER = (157 , 142) # macro -NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION = (158 , 158) # macro -NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED04C = (159 , 159) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST = (185 , 185) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE = (186 , 186) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187 , 187) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE = (188 , 188) # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE = (189 , 189) # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE = (190 , 190) # macro -NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE = (191 , 191) # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME = (223 , 192) # macro -NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME = (239 , 224) # macro -NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME = (255 , 240) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287 , 256) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER = (319 , 288) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER = (327 , 320) # macro -NVC6C0_QMDV03_00_QMD_RESERVED_D = (335 , 328) # macro -NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE = (351 , 336) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID = (357 , 352) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365 , 358) # macro -NVC6C0_QMDV03_00_QMD_RESERVED11A = (366 , 366) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (367 , 367) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE = (369 , 368) # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS = (370 , 370) # macro -NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (371 , 371) # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED11B = (377 , 372) # macro -NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT = (378 , 378) # macro -NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVC6C0_QMDV03_00_QMD_RESERVED11C = (381 , 379) # macro -NVC6C0_QMDV03_00_SAMPLER_INDEX = (382 , 382) # macro -NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE = (383 , 383) # macro -NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_CTA_RASTER_WIDTH = (415 , 384) # macro -NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT = (431 , 416) # macro -NVC6C0_QMDV03_00_CTA_RASTER_DEPTH = (463 , 448) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER = (511 , 480) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE = (512 , 512) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION = (515 , 513) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH = (516 , 516) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE = (517 , 517) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION = (520 , 518) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH = (521 , 521) # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD = (529 , 522) # macro -NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (534 , 530) # macro -NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE = (561 , 544) # macro -NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (567 , 562) # macro -NVC6C0_QMDV03_00_QMD_RESERVED17A = (568 , 568) # macro -NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (574 , 569) # macro -NVC6C0_QMDV03_00_QMD_RESERVED17B = (575 , 575) # macro -NVC6C0_QMDV03_00_QMD_VERSION = (579 , 576) # macro -NVC6C0_QMDV03_00_QMD_MAJOR_VERSION = (583 , 580) # macro -NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 = (607 , 592) # macro -NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 = (623 , 608) # macro -NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 = (639 , 624) # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID(i): # macro - return ((640+(i)*1) , (640+(i)*1)) -NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_REGISTER_COUNT_V = (656 , 648) # macro -NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (662 , 657) # macro -NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE = (663 , 663) # macro -NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM = (671 , 664) # macro -NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER = (703 , 672) # macro -NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER = (735 , 704) # macro -NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE = (759 , 736) # macro -NVC6C0_QMDV03_00_BARRIER_COUNT = (767 , 763) # macro -NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER = (799 , 768) # macro -NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER = (807 , 800) # macro -NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A = (818 , 808) # macro -NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE = (819 , 819) # macro -NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP = (822 , 820) # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV03_00_RELEASE0_ENABLE = (823 , 823) # macro -NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT = (825 , 824) # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE = (826 , 826) # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE = (828 , 827) # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B = (829 , 829) # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE = (831 , 830) # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER = (863 , 832) # macro -NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER = (895 , 864) # macro -NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER = (927 , 896) # macro -NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER = (935 , 928) # macro -NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A = (946 , 936) # macro -NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE = (947 , 947) # macro -NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP = (950 , 948) # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV03_00_RELEASE1_ENABLE = (951 , 951) # macro -NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT = (953 , 952) # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE = (954 , 954) # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE = (956 , 955) # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B = (957 , 957) # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE = (959 , 958) # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER = (991 , 960) # macro -NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER = (1023 , 992) # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i): # macro - return ((1055+(i)*64) , (1024+(i)*64)) -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i): # macro - return ((1072+(i)*64) , (1056+(i)*64)) -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i): # macro - return ((1073+(i)*64) , (1073+(i)*64)) -NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1074+(i)*64) , (1074+(i)*64)) -NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -def NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*64) , (1075+(i)*64)) -NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER = (1567 , 1536) # macro -NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER = (1584 , 1568) # macro -NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE = (1623 , 1600) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1640 , 1632) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE = (1649 , 1641) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE = (1651 , 1650) # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVC6C0_QMDV03_00_SASS_VERSION = (1663 , 1656) # macro -NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER = (1695 , 1664) # macro -NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER = (1703 , 1696) # macro -NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A = (1714 , 1704) # macro -NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE = (1715 , 1715) # macro -NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP = (1718 , 1716) # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR = 0x00000007 # macro -NVC6C0_QMDV03_00_RELEASE2_ENABLE = (1719 , 1719) # macro -NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT = (1721 , 1720) # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE = (1722 , 1722) # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE = (1724 , 1723) # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B = (1725 , 1725) # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE = (1727 , 1726) # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER = (1759 , 1728) # macro -NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER = (1791 , 1760) # macro -NVC6C0_QMDV03_00_QMD_SPARE_I = (1823 , 1792) # macro -NVC6C0_QMDV03_00_HW_ONLY_INNER_GET = (1854 , 1824) # macro -NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1855 , 1855) # macro -NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT = (1886 , 1856) # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1917 , 1888) # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1919 , 1919) # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (1951 , 1920) # macro -NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER = (1958 , 1952) # macro -NVC6C0_QMDV03_00_DEBUG_ID_UPPER = (2015 , 1984) # macro -NVC6C0_QMDV03_00_DEBUG_ID_LOWER = (2047 , 2016) # macro -__CLCEC0QMD_H__ = True # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29 , 0) # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30 , 30) # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31 , 31) # macro -NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (63 , 32) # macro -NVCEC0_QMDV05_00_INNER_GET = (94 , 64) # macro -NVCEC0_QMDV05_00_INNER_OVERFLOW = (95 , 95) # macro -NVCEC0_QMDV05_00_INNER_PUT = (126 , 96) # macro -NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVCEC0_QMDV05_00_DEPENDENCE_COUNTER = (143 , 128) # macro -NVCEC0_QMDV05_00_QMD_GROUP_ID = (149 , 144) # macro -NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150 , 150) # macro -NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_QMD_TYPE = (153 , 151) # macro -NVCEC0_QMDV05_00_QMD_TYPE_QUEUE = 0x00000000 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL = 0x00000001 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA = 0x00000002 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # macro -NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # macro -NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK = (157 , 154) # macro -NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS = (158 , 158) # macro -NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID = (159 , 159) # macro -NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER = (207 , 192) # macro -NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID = (210 , 208) # macro -NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK = (218 , 211) # macro -NVCEC0_QMDV05_00_GRID_WIDTH_RESUME = (255 , 224) # macro -NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME = (271 , 256) # macro -NVCEC0_QMDV05_00_GRID_DEPTH_RESUME = (287 , 272) # macro -def NVCEC0_QMDV05_00_RELEASE_ENABLE(i): # macro - return ((288+(i)*16) , (288+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE(i): # macro - return ((290+(i)*16) , (289+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -def NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE(i): # macro - return ((291+(i)*16) , (291+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE(i): # macro - return ((292+(i)*16) , (292+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP(i): # macro - return ((295+(i)*16) , (293+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # macro -def NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT(i): # macro - return ((297+(i)*16) , (296+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE(i): # macro - return ((299+(i)*16) , (298+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # macro -NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # macro -def NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B(i): # macro - return ((300+(i)*16) , (300+(i)*16)) -NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO(i): # macro - return ((303+(i)*16) , (301+(i)*16)) -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE = (336 , 336) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION = (339 , 337) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH = (340 , 340) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION = (341 , 341) # macro -NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST = (342 , 342) # macro -NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE = (343 , 343) # macro -NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE = (344 , 344) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION = (347 , 345) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH = (348 , 348) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL = (349 , 349) # macro -NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE = (350 , 350) # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE = (351 , 351) # macro -NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CORRELATION_ID = (383 , 352) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER = (415 , 384) # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER = (447 , 416) # macro -NVCEC0_QMDV05_00_SASS_VERSION = (455 , 448) # macro -NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT = (456 , 456) # macro -NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVCEC0_QMDV05_00_SAMPLER_INDEX = (457 , 457) # macro -NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463 , 458) # macro -NVCEC0_QMDV05_00_QMD_MINOR_VERSION = (467 , 464) # macro -NVCEC0_QMDV05_00_QMD_MAJOR_VERSION = (471 , 468) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE = (472 , 472) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473 , 473) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE = (474 , 474) # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE = (475 , 475) # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE = (476 , 476) # macro -NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE = (477 , 477) # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478 , 478) # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479 , 479) # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER = (511 , 480) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER = (536 , 512) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575 , 544) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607 , 576) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615 , 608) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID = (621 , 616) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (622 , 622) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (623 , 623) # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE = (625 , 624) # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626 , 626) # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE = (627 , 627) # macro -NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM = (635 , 628) # macro -NVCEC0_QMDV05_00_SYNC_DOMAIN_ID = (637 , 636) # macro -NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638 , 638) # macro -NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT = (639 , 639) # macro -NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID = (671 , 640) # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID = (703 , 672) # macro -NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM = (721 , 714) # macro -NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM = (729 , 722) # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID = (730 , 730) # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID = (731 , 731) # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE = (732 , 732) # macro -NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733 , 733) # macro -NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734 , 734) # macro -NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735 , 735) # macro -NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP = (743 , 736) # macro -NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP = (751 , 744) # macro -NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER = (759 , 752) # macro -NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER = (767 , 760) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER = (799 , 768) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER = (824 , 800) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863 , 832) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895 , 864) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER = (927 , 896) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER = (952 , 928) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991 , 960) # macro -NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023 , 992) # macro -NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 = (1055 , 1024) # macro -NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 = (1076 , 1056) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE = (1085 , 1077) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE = (1087 , 1086) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 = (1103 , 1088) # macro -NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 = (1119 , 1104) # macro -NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 = (1127 , 1120) # macro -NVCEC0_QMDV05_00_REGISTER_COUNT = (1136 , 1128) # macro -NVCEC0_QMDV05_00_BARRIER_COUNT = (1141 , 1137) # macro -NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE = (1147 , 1142) # macro -NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 = (1162 , 1152) # macro -NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (1168 , 1163) # macro -NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (1174 , 1169) # macro -NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (1180 , 1175) # macro -NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE = (1181 , 1181) # macro -NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = (1199 , 1184) # macro -NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = (1215 , 1200) # macro -NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT = (1223 , 1216) # macro -NVCEC0_QMDV05_00_GRID_WIDTH = (1279 , 1248) # macro -NVCEC0_QMDV05_00_GRID_HEIGHT = (1295 , 1280) # macro -NVCEC0_QMDV05_00_GRID_DEPTH = (1327 , 1312) # macro -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i): # macro - return ((1375+(i)*64) , (1344+(i)*64)) -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i): # macro - return ((1394+(i)*64) , (1376+(i)*64)) -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1407+(i)*64) , (1395+(i)*64)) -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID(i): # macro - return ((1856+(i)*4) , (1856+(i)*4)) -NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH(i): # macro - return ((1858+(i)*4) , (1857+(i)*4)) -NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((1859+(i)*4) , (1859+(i)*4)) -NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1919 , 1888) # macro -NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1936 , 1920) # macro -NVCEC0_QMDV05_00_GPC_CGA_WIDTH = (2053 , 2048) # macro -NVCEC0_QMDV05_00_GPC_CGA_HEIGHT = (2061 , 2056) # macro -NVCEC0_QMDV05_00_GPC_CGA_DEPTH = (2069 , 2064) # macro -NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2075 , 2072) # macro -NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2079 , 2076) # macro -NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE = (2111 , 2111) # macro -NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 # macro -NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 # macro -NVCEC0_QMDV05_00_GPU_CGA_WIDTH = (2127 , 2112) # macro -NVCEC0_QMDV05_00_GPU_CGA_HEIGHT = (2143 , 2128) # macro -NVCEC0_QMDV05_00_GPU_CGA_DEPTH = (2159 , 2144) # macro -NVCEC0_QMDV05_00_DEBUG_ID_LOWER = (2207 , 2176) # macro -NVCEC0_QMDV05_00_DEBUG_ID_UPPER = (2239 , 2208) # macro -def NVCEC0_QMDV05_00_TPC_DISABLE_MASK(i): # macro - return ((2271+(i)*32) , (2240+(i)*32)) -NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2527 , 2496) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2543 , 2528) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2559 , 2544) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2563 , 2560) # macro -NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2567 , 2564) # macro -NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (2596 , 2592) # macro -NVCEC0_QMDV05_00_HW_ONLY_INNER_GET = (2654 , 2624) # macro -NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT = (2686 , 2656) # macro -NVCEC0_QMDV05_00_OUTER_PUT = (3038 , 3008) # macro -NVCEC0_QMDV05_00_OUTER_OVERFLOW = (3039 , 3039) # macro -NVCEC0_QMDV05_00_OUTER_GET = (3070 , 3040) # macro -NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW = (3071 , 3071) # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE(i): # macro - return ((336+(i)*8) , (336+(i)*8)) -NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION(i): # macro - return ((339+(i)*8) , (337+(i)*8)) -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH(i): # macro - return ((340+(i)*8) , (340+(i)*8)) -NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER(i): # macro - return ((415+(i)*32) , (384+(i)*32)) -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29 , 0) # macro -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30 , 30) # macro -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31 , 31) # macro -NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (63 , 32) # macro -NVCEC0_QMDV05_01_INNER_GET = (94 , 64) # macro -NVCEC0_QMDV05_01_INNER_OVERFLOW = (95 , 95) # macro -NVCEC0_QMDV05_01_INNER_PUT = (126 , 96) # macro -NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVCEC0_QMDV05_01_DEPENDENCE_COUNTER = (143 , 128) # macro -NVCEC0_QMDV05_01_QMD_GROUP_ID = (149 , 144) # macro -NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150 , 150) # macro -NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_QMD_TYPE = (153 , 151) # macro -NVCEC0_QMDV05_01_QMD_TYPE_QUEUE = 0x00000000 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL = 0x00000001 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA = 0x00000002 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # macro -NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # macro -NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK = (157 , 154) # macro -NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS = (158 , 158) # macro -NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID = (159 , 159) # macro -NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE = (184 , 160) # macro -NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER = (207 , 192) # macro -NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID = (210 , 208) # macro -NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK = (218 , 211) # macro -NVCEC0_QMDV05_01_GRID_WIDTH_RESUME = (255 , 224) # macro -NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME = (271 , 256) # macro -NVCEC0_QMDV05_01_GRID_DEPTH_RESUME = (287 , 272) # macro -def NVCEC0_QMDV05_01_RELEASE_ENABLE(i): # macro - return ((288+(i)*16) , (288+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE(i): # macro - return ((290+(i)*16) , (289+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -def NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE(i): # macro - return ((291+(i)*16) , (291+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE(i): # macro - return ((292+(i)*16) , (292+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP(i): # macro - return ((295+(i)*16) , (293+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # macro -def NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT(i): # macro - return ((297+(i)*16) , (296+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE(i): # macro - return ((299+(i)*16) , (298+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # macro -NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # macro -def NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B(i): # macro - return ((300+(i)*16) , (300+(i)*16)) -NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO(i): # macro - return ((303+(i)*16) , (301+(i)*16)) -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE = (336 , 336) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION = (339 , 337) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH = (340 , 340) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION = (341 , 341) # macro -NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST = (342 , 342) # macro -NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE = (343 , 343) # macro -NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE = (344 , 344) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION = (347 , 345) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH = (348 , 348) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL = (349 , 349) # macro -NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (350 , 350) # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE = (351 , 351) # macro -NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CORRELATION_ID = (383 , 352) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER = (415 , 384) # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER = (447 , 416) # macro -NVCEC0_QMDV05_01_SASS_VERSION = (455 , 448) # macro -NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT = (456 , 456) # macro -NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVCEC0_QMDV05_01_SAMPLER_INDEX = (457 , 457) # macro -NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463 , 458) # macro -NVCEC0_QMDV05_01_QMD_MINOR_VERSION = (467 , 464) # macro -NVCEC0_QMDV05_01_QMD_MAJOR_VERSION = (471 , 468) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE = (472 , 472) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473 , 473) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE = (474 , 474) # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE = (475 , 475) # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE = (476 , 476) # macro -NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE = (477 , 477) # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478 , 478) # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479 , 479) # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (511 , 480) # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (536 , 512) # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575 , 544) # macro -NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607 , 576) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615 , 608) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID = (621 , 616) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (622 , 622) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (623 , 623) # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE = (625 , 624) # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626 , 626) # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE = (627 , 627) # macro -NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM = (635 , 628) # macro -NVCEC0_QMDV05_01_SYNC_DOMAIN_ID = (637 , 636) # macro -NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638 , 638) # macro -NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT = (639 , 639) # macro -NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID = (671 , 640) # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID = (703 , 672) # macro -NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (721 , 714) # macro -NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM = (729 , 722) # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID = (730 , 730) # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID = (731 , 731) # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE = (732 , 732) # macro -NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733 , 733) # macro -NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734 , 734) # macro -NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735 , 735) # macro -NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 # macro -NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP = (743 , 736) # macro -NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP = (751 , 744) # macro -NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER = (759 , 752) # macro -NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER = (767 , 760) # macro -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4(i): # macro - return ((799+(i)*416) , (768+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4(i): # macro - return ((820+(i)*416) , (800+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE(i): # macro - return ((829+(i)*416) , (821+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE(i): # macro - return ((831+(i)*416) , (830+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0(i): # macro - return ((847+(i)*416) , (832+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1(i): # macro - return ((863+(i)*416) , (848+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2(i): # macro - return ((871+(i)*416) , (864+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT(i): # macro - return ((880+(i)*416) , (872+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT(i): # macro - return ((885+(i)*416) , (881+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID(i): # macro - return ((886+(i)*416) , (886+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH(i): # macro - return ((888+(i)*416) , (887+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE(i): # macro - return ((889+(i)*416) , (889+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE(i): # macro - return ((895+(i)*416) , (890+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7(i): # macro - return ((906+(i)*416) , (896+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE(i): # macro - return ((912+(i)*416) , (907+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE(i): # macro - return ((918+(i)*416) , (913+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE(i): # macro - return ((924+(i)*416) , (919+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE(i): # macro - return ((925+(i)*416) , (925+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4(i): # macro - return ((943+(i)*416) , (928+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4(i): # macro - return ((959+(i)*416) , (944+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6(i): # macro - return ((991+(i)*416) , (960+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6(i): # macro - return ((1010+(i)*416) , (992+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4(i): # macro - return ((1023+(i)*416) , (1011+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6(i): # macro - return ((1055+(i)*416) , (1024+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6(i): # macro - return ((1074+(i)*416) , (1056+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4(i): # macro - return ((1087+(i)*416) , (1075+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID(i): # macro - return ((1088+(i)*416) , (1088+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH(i): # macro - return ((1090+(i)*416) , (1089+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE(i): # macro - return ((1091+(i)*416) , (1091+(i)*416)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT(i): # macro - return ((1099+(i)*416) , (1092+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH(i): # macro - return ((1151+(i)*416) , (1120+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT(i): # macro - return ((1167+(i)*416) , (1152+(i)*416)) -def NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH(i): # macro - return ((1183+(i)*416) , (1168+(i)*416)) -def NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE(i): # macro - return ((336+(i)*8) , (336+(i)*8)) -NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION(i): # macro - return ((339+(i)*8) , (337+(i)*8)) -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -def NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH(i): # macro - return ((340+(i)*8) , (340+(i)*8)) -NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # macro -def NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER(i): # macro - return ((415+(i)*32) , (384+(i)*32)) -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID(i, j): # macro -# return MW((886+(i)*416+(j)*202):(886+(i)*416+(j)*202)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE = 0x00000001 # macro -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH(i, j): # macro -# return MW((888+(i)*416+(j)*202):(887+(i)*416+(j)*202)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST = 0x00000002 # macro -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE(i, j): # macro -# return MW((889+(i)*416+(j)*202):(889+(i)*416+(j)*202)) -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE = 0x00000001 # macro -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6(i, j): # macro -# return MW((991+(i)*416+(j)*64):(960+(i)*416+(j)*64)) -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6(i, j): # macro -# return MW((1010+(i)*416+(j)*64):(992+(i)*416+(j)*64)) -# def NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4(i, j): # macro -# return MW((1023+(i)*416+(j)*64):(1011+(i)*416+(j)*64)) -NVCEC0_QMDV04_01_DEPENDENCE_COUNTER = (15 , 0) # macro -NVCEC0_QMDV04_01_QMD_GROUP_ID = (21 , 16) # macro -NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (22 , 22) # macro -NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_QMD_TYPE = (25 , 23) # macro -NVCEC0_QMDV04_01_QMD_TYPE_QUEUE = 0x00000000 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL = 0x00000001 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA = 0x00000002 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 # macro -NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 # macro -NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID = (28 , 28) # macro -NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID = (29 , 29) # macro -NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS = (30 , 30) # macro -NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID = (31 , 31) # macro -NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE = (56 , 32) # macro -NVCEC0_QMDV04_01_INNER_GET = (94 , 64) # macro -NVCEC0_QMDV04_01_INNER_OVERFLOW = (95 , 95) # macro -NVCEC0_QMDV04_01_INNER_PUT = (126 , 96) # macro -NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW = (127 , 127) # macro -NVCEC0_QMDV04_01_HW_ONLY_INNER_GET = (190 , 160) # macro -NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT = (222 , 192) # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (253 , 224) # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (254 , 254) # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (287 , 256) # macro -NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER = (303 , 288) # macro -NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (304 , 304) # macro -def NVCEC0_QMDV04_01_RELEASE_ENABLE(i): # macro - return ((320+(i)*16) , (320+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE(i): # macro - return ((322+(i)*16) , (321+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 # macro -def NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE(i): # macro - return ((323+(i)*16) , (323+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE(i): # macro - return ((324+(i)*16) , (324+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP(i): # macro - return ((327+(i)*16) , (325+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 # macro -def NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT(i): # macro - return ((329+(i)*16) , (328+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE(i): # macro - return ((331+(i)*16) , (330+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 # macro -NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 # macro -def NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B(i): # macro - return ((332+(i)*16) , (332+(i)*16)) -NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO(i): # macro - return ((335+(i)*16) , (333+(i)*16)) -def NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE(i): # macro - return ((368+(i)*5) , (368+(i)*5)) -NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION(i): # macro - return ((371+(i)*5) , (369+(i)*5)) -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 # macro -def NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH(i): # macro - return ((372+(i)*5) , (372+(i)*5)) -NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION = (378 , 378) # macro -NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST = (379 , 379) # macro -NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE = (380 , 380) # macro -NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL = (381 , 381) # macro -NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (382 , 382) # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CORRELATION_ID = (415 , 384) # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID(i): # macro - return ((416+(i)*4) , (416+(i)*4)) -NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH(i): # macro - return ((418+(i)*4) , (417+(i)*4)) -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE(i): # macro - return ((419+(i)*4) , (419+(i)*4)) -NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER = (479 , 448) # macro -NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER = (511 , 480) # macro -NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE = (535 , 512) # macro -NVCEC0_QMDV04_01_SASS_VERSION = (543 , 536) # macro -NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE = (567 , 544) # macro -NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT = (568 , 568) # macro -NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 # macro -NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 # macro -NVCEC0_QMDV04_01_SAMPLER_INDEX = (569 , 569) # macro -NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 # macro -NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 # macro -NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (575 , 570) # macro -NVCEC0_QMDV04_01_QMD_MINOR_VERSION = (579 , 576) # macro -NVCEC0_QMDV04_01_QMD_MAJOR_VERSION = (583 , 580) # macro -NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE = (601 , 584) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE = (602 , 602) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (603 , 603) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE = (604 , 604) # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE = (605 , 605) # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE = (606 , 606) # macro -NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE = (607 , 607) # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE = (613 , 608) # macro -NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE = (619 , 614) # macro -NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (625 , 620) # macro -NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE = (626 , 626) # macro -NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (671 , 640) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (696 , 672) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (735 , 704) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (767 , 736) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER = (799 , 768) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER = (824 , 800) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863 , 832) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895 , 864) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER = (927 , 896) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER = (952 , 928) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991 , 960) # macro -NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023 , 992) # macro -NVCEC0_QMDV04_01_GRID_WIDTH = (1055 , 1024) # macro -NVCEC0_QMDV04_01_GRID_HEIGHT = (1071 , 1056) # macro -NVCEC0_QMDV04_01_GRID_DEPTH = (1103 , 1088) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (1127 , 1120) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID = (1133 , 1128) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (1134 , 1134) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (1135 , 1135) # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE = (1137 , 1136) # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 # macro -NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 # macro -NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS = (1138 , 1138) # macro -NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE = (1139 , 1139) # macro -NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM = (1147 , 1140) # macro -NVCEC0_QMDV04_01_SYNC_DOMAIN_ID = (1149 , 1148) # macro -NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (1150 , 1150) # macro -NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT = (1151 , 1151) # macro -NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 = (1167 , 1152) # macro -NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 = (1183 , 1168) # macro -NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 = (1191 , 1184) # macro -NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT = (1199 , 1192) # macro -NVCEC0_QMDV04_01_REGISTER_COUNT = (1208 , 1200) # macro -NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE = (1210 , 1210) # macro -NVCEC0_QMDV04_01_BARRIER_COUNT = (1215 , 1211) # macro -NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER = (1247 , 1216) # macro -NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER = (1272 , 1248) # macro -NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP = (1287 , 1280) # macro -NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP = (1295 , 1288) # macro -NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER = (1303 , 1296) # macro -NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER = (1311 , 1304) # macro -NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (1319 , 1312) # macro -NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM = (1327 , 1320) # macro -NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE = (1333 , 1328) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1375 , 1344) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1392 , 1376) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE = (1401 , 1393) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE = (1403 , 1402) # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 # macro -NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (1406 , 1406) # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (1407 , 1407) # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 # macro -NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 # macro -NVCEC0_QMDV04_01_GRID_WIDTH_RESUME = (1439 , 1408) # macro -NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME = (1455 , 1440) # macro -NVCEC0_QMDV04_01_GRID_DEPTH_RESUME = (1471 , 1456) # macro -NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID = (1503 , 1472) # macro -NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID = (1535 , 1504) # macro -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6(i): # macro - return ((1567+(i)*64) , (1536+(i)*64)) -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6(i): # macro - return ((1586+(i)*64) , (1568+(i)*64)) -def NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i): # macro - return ((1599+(i)*64) , (1587+(i)*64)) -NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD = (2135 , 2128) # macro -NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 = (2140 , 2136) # macro -NVCEC0_QMDV04_01_GPC_CGA_WIDTH = (2149 , 2144) # macro -NVCEC0_QMDV04_01_GPC_CGA_HEIGHT = (2157 , 2152) # macro -NVCEC0_QMDV04_01_GPC_CGA_DEPTH = (2165 , 2160) # macro -NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2171 , 2168) # macro -NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2175 , 2172) # macro -NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE = (2207 , 2207) # macro -NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 # macro -NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 # macro -NVCEC0_QMDV04_01_GPU_CGA_WIDTH = (2223 , 2208) # macro -NVCEC0_QMDV04_01_GPU_CGA_HEIGHT = (2239 , 2224) # macro -NVCEC0_QMDV04_01_GPU_CGA_DEPTH = (2255 , 2240) # macro -NVCEC0_QMDV04_01_DEBUG_ID_LOWER = (2399 , 2368) # macro -NVCEC0_QMDV04_01_DEBUG_ID_UPPER = (2431 , 2400) # macro -def NVCEC0_QMDV04_01_TPC_DISABLE_MASK(i): # macro - return ((2463+(i)*32) , (2432+(i)*32)) -NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2591 , 2560) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2607 , 2592) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2623 , 2608) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2627 , 2624) # macro -NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2631 , 2628) # macro -def NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER(i): # macro - return ((2719+(i)*32) , (2688+(i)*32)) -NVCEC0_QMDV04_01_OUTER_PUT = (3038 , 3008) # macro -NVCEC0_QMDV04_01_OUTER_OVERFLOW = (3039 , 3039) # macro -NVCEC0_QMDV04_01_OUTER_GET = (3070 , 3040) # macro -NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW = (3071 , 3071) # macro -NV01_NULL_OBJECT = (0x0) # macro -NV1_NULL_OBJECT = (0x0) # macro -NV01_ROOT = (0x0) # macro -NV0000_ALLOC_PARAMETERS_MESSAGE_ID = (0x0000) # macro -class struct_NV0000_ALLOC_PARAMETERS(Structure): - pass - -struct_NV0000_ALLOC_PARAMETERS._pack_ = 1 # source:False +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class _anonunion0(ctypes.Union): pass +NvUPtr = ctypes.c_uint64 +_anonunion0._fields_ = [ + ('v', NvUPtr), + ('p', ctypes.c_void_p), +] +class _anonunion1(ctypes.Union): pass +_anonunion1._fields_ = [ + ('v', NvUPtr), + ('p', ctypes.c_void_p), +] +class struct_NV0000_ALLOC_PARAMETERS(Struct): pass +NvHandle = ctypes.c_uint32 +NvU32 = ctypes.c_uint32 +NvP64 = ctypes.c_void_p struct_NV0000_ALLOC_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('processID', ctypes.c_uint32), - ('processName', ctypes.c_char * 100), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pOsPidInfo', ctypes.POINTER(None)), + ('hClient', NvHandle), + ('processID', NvU32), + ('processName', (ctypes.c_char * 100)), + ('pOsPidInfo', NvP64), ] - NV0000_ALLOC_PARAMETERS = struct_NV0000_ALLOC_PARAMETERS -NV01_DEVICE_0 = (0x00000080) # macro -# NV0080_MAX_DEVICES = NV_MAX_DEVICES # macro -NV0080_ALLOC_PARAMETERS_MESSAGE_ID = (0x0080) # macro -class struct_NV0080_ALLOC_PARAMETERS(Structure): - pass - -struct_NV0080_ALLOC_PARAMETERS._pack_ = 1 # source:False +class struct_NV0080_ALLOC_PARAMETERS(Struct): pass +NvV32 = ctypes.c_uint32 +NvU64 = ctypes.c_uint64 struct_NV0080_ALLOC_PARAMETERS._fields_ = [ - ('deviceId', ctypes.c_uint32), - ('hClientShare', ctypes.c_uint32), - ('hTargetClient', ctypes.c_uint32), - ('hTargetDevice', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vaSpaceSize', ctypes.c_uint64), - ('vaStartInternal', ctypes.c_uint64), - ('vaLimitInternal', ctypes.c_uint64), - ('vaMode', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('deviceId', NvU32), + ('hClientShare', NvHandle), + ('hTargetClient', NvHandle), + ('hTargetDevice', NvHandle), + ('flags', NvV32), + ('vaSpaceSize', NvU64), + ('vaStartInternal', NvU64), + ('vaLimitInternal', NvU64), + ('vaMode', NvV32), ] - NV0080_ALLOC_PARAMETERS = struct_NV0080_ALLOC_PARAMETERS -_cl2080_notification_h_ = True # macro -NV2080_NOTIFIERS_SW = (0) # macro -NV2080_NOTIFIERS_HOTPLUG = (1) # macro -NV2080_NOTIFIERS_POWER_CONNECTOR = (2) # macro -NV2080_NOTIFIERS_THERMAL_SW = (3) # macro -NV2080_NOTIFIERS_THERMAL_HW = (4) # macro -NV2080_NOTIFIERS_FULL_SCREEN_CHANGE = (5) # macro -NV2080_NOTIFIERS_EVENTBUFFER = (6) # macro -NV2080_NOTIFIERS_DP_IRQ = (7) # macro -NV2080_NOTIFIERS_GR_DEBUG_INTR = (8) # macro -NV2080_NOTIFIERS_PMU_EVENT = (9) # macro -NV2080_NOTIFIERS_PMU_COMMAND = (10) # macro -NV2080_NOTIFIERS_TIMER = (11) # macro -NV2080_NOTIFIERS_GRAPHICS = (12) # macro -NV2080_NOTIFIERS_PPP = (13) # macro -NV2080_NOTIFIERS_VLD = (14) # macro -NV2080_NOTIFIERS_NVDEC0 = (14) # macro -NV2080_NOTIFIERS_NVDEC1 = (15) # macro -NV2080_NOTIFIERS_NVDEC2 = (16) # macro -NV2080_NOTIFIERS_NVDEC3 = (17) # macro -NV2080_NOTIFIERS_NVDEC4 = (18) # macro -NV2080_NOTIFIERS_NVDEC5 = (19) # macro -NV2080_NOTIFIERS_NVDEC6 = (20) # macro -NV2080_NOTIFIERS_NVDEC7 = (21) # macro -NV2080_NOTIFIERS_PDEC = (22) # macro -NV2080_NOTIFIERS_CE0 = (23) # macro -NV2080_NOTIFIERS_CE1 = (24) # macro -NV2080_NOTIFIERS_CE2 = (25) # macro -NV2080_NOTIFIERS_CE3 = (26) # macro -NV2080_NOTIFIERS_CE4 = (27) # macro -NV2080_NOTIFIERS_CE5 = (28) # macro -NV2080_NOTIFIERS_CE6 = (29) # macro -NV2080_NOTIFIERS_CE7 = (30) # macro -NV2080_NOTIFIERS_CE8 = (31) # macro -NV2080_NOTIFIERS_CE9 = (32) # macro -NV2080_NOTIFIERS_PSTATE_CHANGE = (33) # macro -NV2080_NOTIFIERS_HDCP_STATUS_CHANGE = (34) # macro -NV2080_NOTIFIERS_FIFO_EVENT_MTHD = (35) # macro -NV2080_NOTIFIERS_PRIV_RING_HANG = (36) # macro -NV2080_NOTIFIERS_RC_ERROR = (37) # macro -NV2080_NOTIFIERS_MSENC = (38) # macro -NV2080_NOTIFIERS_NVENC0 = (38) # macro -NV2080_NOTIFIERS_NVENC1 = (39) # macro -NV2080_NOTIFIERS_NVENC2 = (40) # macro -NV2080_NOTIFIERS_UNUSED_0 = (41) # macro -NV2080_NOTIFIERS_ACPI_NOTIFY = (42) # macro -NV2080_NOTIFIERS_COOLER_DIAG_ZONE = (43) # macro -NV2080_NOTIFIERS_THERMAL_DIAG_ZONE = (44) # macro -NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST = (45) # macro -NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE = (46) # macro -NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT = (47) # macro -NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT = (48) # macro -NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT = (49) # macro -NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT = (50) # macro -NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT = (51) # macro -NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT = (52) # macro -NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT = (53) # macro -NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT = (54) # macro -NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT = (55) # macro -NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT = (56) # macro -NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT = (57) # macro -NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT = (58) # macro -NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT = (59) # macro -NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT = (60) # macro -NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT = (61) # macro -NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT = (62) # macro -NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT = (63) # macro -NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT = (64) # macro -NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT = (65) # macro -NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT = (66) # macro -NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT = (67) # macro -NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT = (68) # macro -NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT = (69) # macro -NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT = (70) # macro -NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT = (71) # macro -NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT = (72) # macro -NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT = (73) # macro -NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT = (74) # macro -NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT = (75) # macro -NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT = (76) # macro -NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT = (77) # macro -NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT = (78) # macro -NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT = (79) # macro -NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT = (80) # macro -NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT = (81) # macro -NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT = (82) # macro -NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT = (83) # macro -NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT = (84) # macro -NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT = (85) # macro -NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT = (86) # macro -NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT = (87) # macro -NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT = (88) # macro -NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT = (89) # macro -NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT = (90) # macro -NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT = (91) # macro -NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT = (92) # macro -NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT = (93) # macro -NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT = (94) # macro -NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT = (95) # macro -NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT = (96) # macro -NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT = (97) # macro -NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT = (98) # macro -NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT = (99) # macro -NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT = (100) # macro -NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT = (101) # macro -NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT = (102) # macro -NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT = (103) # macro -NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT = (104) # macro -NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT = (105) # macro -NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT = (106) # macro -NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT = (107) # macro -NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT = (108) # macro -NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT = (109) # macro -NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT = (110) # macro -NV2080_NOTIFIERS_ECC_SBE = (111) # macro -NV2080_NOTIFIERS_ECC_DBE = (112) # macro -NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION = (113) # macro -NV2080_NOTIFIERS_GC5_GPU_READY = (114) # macro -NV2080_NOTIFIERS_SEC2 = (115) # macro -NV2080_NOTIFIERS_GC6_REFCOUNT_INC = (116) # macro -NV2080_NOTIFIERS_GC6_REFCOUNT_DEC = (117) # macro -NV2080_NOTIFIERS_POWER_EVENT = (118) # macro -NV2080_NOTIFIERS_CLOCKS_CHANGE = (119) # macro -NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE = (120) # macro -NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT = (121) # macro -NV2080_NOTIFIERS_RESERVED122 = (122) # macro -NV2080_NOTIFIERS_NVLINK_ERROR_FATAL = (123) # macro -NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT = (124) # macro -NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED = (125) # macro -NV2080_NOTIFIERS_NVJPG = (126) # macro -NV2080_NOTIFIERS_NVJPEG0 = (126) # macro -NV2080_NOTIFIERS_NVJPEG1 = (127) # macro -NV2080_NOTIFIERS_NVJPEG2 = (128) # macro -NV2080_NOTIFIERS_NVJPEG3 = (129) # macro -NV2080_NOTIFIERS_NVJPEG4 = (130) # macro -NV2080_NOTIFIERS_NVJPEG5 = (131) # macro -NV2080_NOTIFIERS_NVJPEG6 = (132) # macro -NV2080_NOTIFIERS_NVJPEG7 = (133) # macro -NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE = (134) # macro -NV2080_NOTIFIERS_RUNLIST_ACQUIRE = (135) # macro -NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE = (136) # macro -NV2080_NOTIFIERS_RUNLIST_IDLE = (137) # macro -NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE = (138) # macro -NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE = (139) # macro -NV2080_NOTIFIERS_CTXSW_TIMEOUT = (140) # macro -NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED = (141) # macro -NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT = (142) # macro -NV2080_NOTIFIERS_DSTATE_XUSB_PPC = (143) # macro -NV2080_NOTIFIERS_FECS_CTX_SWITCH = (144) # macro -NV2080_NOTIFIERS_XUSB_PPC_CONNECTED = (145) # macro -NV2080_NOTIFIERS_GR0 = (12) # macro -NV2080_NOTIFIERS_GR1 = (146) # macro -NV2080_NOTIFIERS_GR2 = (147) # macro -NV2080_NOTIFIERS_GR3 = (148) # macro -NV2080_NOTIFIERS_GR4 = (149) # macro -NV2080_NOTIFIERS_GR5 = (150) # macro -NV2080_NOTIFIERS_GR6 = (151) # macro -NV2080_NOTIFIERS_GR7 = (152) # macro -NV2080_NOTIFIERS_OFA = (153) # macro -NV2080_NOTIFIERS_OFA0 = (153) # macro -NV2080_NOTIFIERS_DSTATE_HDA = (154) # macro -NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL = (155) # macro -NV2080_NOTIFIERS_POISON_ERROR_FATAL = (156) # macro -NV2080_NOTIFIERS_UCODE_RESET = (157) # macro -NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE = (158) # macro -NV2080_NOTIFIERS_SMC_CONFIG_UPDATE = (159) # macro -NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED = (160) # macro -NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED = (161) # macro -NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST = (162) # macro -NV2080_NOTIFIERS_SEC_FAULT_ERROR = (163) # macro -NV2080_NOTIFIERS_UNUSED_1 = (164) # macro -NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP = (165) # macro -NV2080_NOTIFIERS_CE10 = (166) # macro -NV2080_NOTIFIERS_CE11 = (167) # macro -NV2080_NOTIFIERS_CE12 = (168) # macro -NV2080_NOTIFIERS_CE13 = (169) # macro -NV2080_NOTIFIERS_CE14 = (170) # macro -NV2080_NOTIFIERS_CE15 = (171) # macro -NV2080_NOTIFIERS_CE16 = (172) # macro -NV2080_NOTIFIERS_CE17 = (173) # macro -NV2080_NOTIFIERS_CE18 = (174) # macro -NV2080_NOTIFIERS_CE19 = (175) # macro -NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN = (176) # macro -NV2080_NOTIFIERS_NVPCF_EVENTS = (177) # macro -NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST = (178) # macro -NV2080_NOTIFIERS_VRR_SET_TIMEOUT = (179) # macro -NV2080_NOTIFIERS_OFA1 = (180) # macro -NV2080_NOTIFIERS_AUX_POWER_EVENT = (181) # macro -NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE = (182) # macro -NV2080_NOTIFIERS_NVENC3 = (183) # macro -NV2080_NOTIFIERS_GSP_PERF_TRACE = (184) # macro -NV2080_NOTIFIERS_INBAND_RESPONSE = (185) # macro -NV2080_NOTIFIERS_RESERVED_186 = (186) # macro -NV2080_NOTIFIERS_ECC_SBE_STORM = (187) # macro -NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT = (188) # macro -NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE = (189) # macro -NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR = (190) # macro -NV2080_NOTIFIERS_GPU_UNAVAILABLE = (191) # macro -NV2080_NOTIFIERS_GPU_RECOVERY_ACTION = (192) # macro -NV2080_NOTIFIERS_POWER_SUSPEND = (193) # macro -NV2080_NOTIFIERS_POWER_RESUME = (194) # macro -NV2080_NOTIFIERS_CTXSW_UCODE_ERROR = (195) # macro -NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD = (196) # macro -NV2080_NOTIFIERS_MAXCOUNT = (197) # macro -# def NV2080_NOTIFIERS_GR(x): # macro -# return ((x==0)?((12)):((146)+(x-1))) -def NV2080_NOTIFIERS_GR_IDX(x): # macro - return ((x)-(12)) -def NV2080_NOTIFIER_TYPE_IS_GR(x): # macro - return (((x)==(12)) or (((x)>=(146)) and ((x)<=(152)))) -# def NV2080_NOTIFIERS_CE(x): # macro -# return (((x)<10)?((23)+(x)):((166)+(x)-10)) -# def NV2080_NOTIFIERS_CE_IDX(x): # macro -# return (((x)<=(32))?((x)-(23)):((x)-(166)+10)) -def NV2080_NOTIFIER_TYPE_IS_CE(x): # macro - return ((((x)>=(23)) and ((x)<=(32))) or (((x)>=(166)) and ((x)<=(175)))) -# def NV2080_NOTIFIERS_NVENC(x): # macro -# return (((x)<3)?((38)+(x)):((183)+(x)-3)) -# def NV2080_NOTIFIERS_NVENC_IDX(x): # macro -# return (((x)<=(40))?((x)-(38)):((x)-(183)+3)) -def NV2080_NOTIFIER_TYPE_IS_NVENC(x): # macro - return ((((x)>=(38)) and ((x)<=(40))) or (((x)==(183)))) -def NV2080_NOTIFIERS_NVDEC(x): # macro - return ((14)+(x)) -def NV2080_NOTIFIERS_NVDEC_IDX(x): # macro - return ((x)-(14)) -def NV2080_NOTIFIER_TYPE_IS_NVDEC(x): # macro - return (((x)>=(14)) and ((x)<=(21))) -def NV2080_NOTIFIERS_NVJPEG(x): # macro - return ((126)+(x)) -def NV2080_NOTIFIERS_NVJPEG_IDX(x): # macro - return ((x)-(126)) -def NV2080_NOTIFIER_TYPE_IS_NVJPEG(x): # macro - return (((x)>=(126)) and ((x)<=(133))) -# def NV2080_NOTIFIERS_OFAn(x): # macro -# return ((x==0)?((153)):((180))) -# def NV2080_NOTIFIERS_OFA_IDX(x): # macro -# return ((x==(153))?((x)-(153)):((x)-(180)+1)) -def NV2080_NOTIFIER_TYPE_IS_OFA(x): # macro - return (((x)==(153)) or ((x)==(180))) -def NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin): # macro - return ((47)+(pin)) -def NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin): # macro - return ((79)+(pin)) -NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS = (0x8000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT = (0x4000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE = (0x2000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE = (0x1000) # macro -NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS = (0x0000) # macro -NV2080_ENGINE_TYPE_NULL = (0x00000000) # macro -NV2080_ENGINE_TYPE_GRAPHICS = (0x00000001) # macro -NV2080_ENGINE_TYPE_GR0 = (0x00000001) # macro -NV2080_ENGINE_TYPE_GR1 = (0x00000002) # macro -NV2080_ENGINE_TYPE_GR2 = (0x00000003) # macro -NV2080_ENGINE_TYPE_GR3 = (0x00000004) # macro -NV2080_ENGINE_TYPE_GR4 = (0x00000005) # macro -NV2080_ENGINE_TYPE_GR5 = (0x00000006) # macro -NV2080_ENGINE_TYPE_GR6 = (0x00000007) # macro -NV2080_ENGINE_TYPE_GR7 = (0x00000008) # macro -NV2080_ENGINE_TYPE_COPY0 = (0x00000009) # macro -NV2080_ENGINE_TYPE_COPY1 = (0x0000000a) # macro -NV2080_ENGINE_TYPE_COPY2 = (0x0000000b) # macro -NV2080_ENGINE_TYPE_COPY3 = (0x0000000c) # macro -NV2080_ENGINE_TYPE_COPY4 = (0x0000000d) # macro -NV2080_ENGINE_TYPE_COPY5 = (0x0000000e) # macro -NV2080_ENGINE_TYPE_COPY6 = (0x0000000f) # macro -NV2080_ENGINE_TYPE_COPY7 = (0x00000010) # macro -NV2080_ENGINE_TYPE_COPY8 = (0x00000011) # macro -NV2080_ENGINE_TYPE_COPY9 = (0x00000012) # macro -NV2080_ENGINE_TYPE_BSP = (0x00000013) # macro -NV2080_ENGINE_TYPE_NVDEC0 = (0x00000013) # macro -NV2080_ENGINE_TYPE_NVDEC1 = (0x00000014) # macro -NV2080_ENGINE_TYPE_NVDEC2 = (0x00000015) # macro -NV2080_ENGINE_TYPE_NVDEC3 = (0x00000016) # macro -NV2080_ENGINE_TYPE_NVDEC4 = (0x00000017) # macro -NV2080_ENGINE_TYPE_NVDEC5 = (0x00000018) # macro -NV2080_ENGINE_TYPE_NVDEC6 = (0x00000019) # macro -NV2080_ENGINE_TYPE_NVDEC7 = (0x0000001a) # macro -NV2080_ENGINE_TYPE_MSENC = (0x0000001b) # macro -NV2080_ENGINE_TYPE_NVENC0 = (0x0000001b) # macro -NV2080_ENGINE_TYPE_NVENC1 = (0x0000001c) # macro -NV2080_ENGINE_TYPE_NVENC2 = (0x0000001d) # macro -NV2080_ENGINE_TYPE_VP = (0x0000001e) # macro -NV2080_ENGINE_TYPE_ME = (0x0000001f) # macro -NV2080_ENGINE_TYPE_PPP = (0x00000020) # macro -NV2080_ENGINE_TYPE_MPEG = (0x00000021) # macro -NV2080_ENGINE_TYPE_SW = (0x00000022) # macro -NV2080_ENGINE_TYPE_CIPHER = (0x00000023) # macro -NV2080_ENGINE_TYPE_TSEC = (0x00000023) # macro -NV2080_ENGINE_TYPE_VIC = (0x00000024) # macro -NV2080_ENGINE_TYPE_MP = (0x00000025) # macro -NV2080_ENGINE_TYPE_SEC2 = (0x00000026) # macro -NV2080_ENGINE_TYPE_HOST = (0x00000027) # macro -NV2080_ENGINE_TYPE_DPU = (0x00000028) # macro -NV2080_ENGINE_TYPE_PMU = (0x00000029) # macro -NV2080_ENGINE_TYPE_FBFLCN = (0x0000002a) # macro -NV2080_ENGINE_TYPE_NVJPG = (0x0000002b) # macro -NV2080_ENGINE_TYPE_NVJPEG0 = (0x0000002b) # macro -NV2080_ENGINE_TYPE_NVJPEG1 = (0x0000002c) # macro -NV2080_ENGINE_TYPE_NVJPEG2 = (0x0000002d) # macro -NV2080_ENGINE_TYPE_NVJPEG3 = (0x0000002e) # macro -NV2080_ENGINE_TYPE_NVJPEG4 = (0x0000002f) # macro -NV2080_ENGINE_TYPE_NVJPEG5 = (0x00000030) # macro -NV2080_ENGINE_TYPE_NVJPEG6 = (0x00000031) # macro -NV2080_ENGINE_TYPE_NVJPEG7 = (0x00000032) # macro -NV2080_ENGINE_TYPE_OFA = (0x00000033) # macro -NV2080_ENGINE_TYPE_OFA0 = (0x00000033) # macro -NV2080_ENGINE_TYPE_COPY10 = (0x00000034) # macro -NV2080_ENGINE_TYPE_COPY11 = (0x00000035) # macro -NV2080_ENGINE_TYPE_COPY12 = (0x00000036) # macro -NV2080_ENGINE_TYPE_COPY13 = (0x00000037) # macro -NV2080_ENGINE_TYPE_COPY14 = (0x00000038) # macro -NV2080_ENGINE_TYPE_COPY15 = (0x00000039) # macro -NV2080_ENGINE_TYPE_COPY16 = (0x0000003a) # macro -NV2080_ENGINE_TYPE_COPY17 = (0x0000003b) # macro -NV2080_ENGINE_TYPE_COPY18 = (0x0000003c) # macro -NV2080_ENGINE_TYPE_COPY19 = (0x0000003d) # macro -NV2080_ENGINE_TYPE_OFA1 = (0x0000003e) # macro -NV2080_ENGINE_TYPE_NVENC3 = (0x0000003f) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 = (0x00000040) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 = (0x00000041) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 = (0x00000042) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 = (0x00000043) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 = (0x00000044) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 = (0x00000045) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 = (0x00000046) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 = (0x00000047) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 = (0x00000048) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 = (0x00000049) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 = (0x0000004a) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 = (0x0000004b) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 = (0x0000004c) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 = (0x0000004d) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 = (0x0000004e) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 = (0x0000004f) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 = (0x00000050) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 = (0x00000051) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 = (0x00000052) # macro -NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 = (0x00000053) # macro -NV2080_ENGINE_TYPE_LAST = (0x00000054) # macro -NV2080_ENGINE_TYPE_ALLENGINES = (0xffffffff) # macro -NV2080_ENGINE_TYPE_COPY_SIZE = 64 # macro -NV2080_ENGINE_TYPE_NVENC_SIZE = 4 # macro -NV2080_ENGINE_TYPE_NVJPEG_SIZE = 8 # macro -NV2080_ENGINE_TYPE_NVDEC_SIZE = 8 # macro -NV2080_ENGINE_TYPE_GR_SIZE = 8 # macro -NV2080_ENGINE_TYPE_OFA_SIZE = 2 # macro -def NV2080_ENGINE_TYPE_COMP_DECOMP_COPY(i): # macro - return ((0x00000040)+(i)) -def NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i): # macro - return (((i)>=(0x00000040)) and ((i)<=(0x00000053))) -def NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX(i): # macro - return ((i)-(0x00000040)) -# def NV2080_ENGINE_TYPE_COPY(i): # macro -# return (((i)<10)?((0x00000009)+(i)):((0x00000034)+(i)-10)) -def NV2080_ENGINE_TYPE_IS_COPY(i): # macro - return ((((i)>=(0x00000009)) and ((i)<=(0x00000012))) or (((i)>=(0x00000034)) and ((i)<=(0x0000003d)))) -# def NV2080_ENGINE_TYPE_COPY_IDX(i): # macro -# return (((i)<=(0x00000012))?((i)-(0x00000009)):((i)-(0x00000034)+10)) -# def NV2080_ENGINE_TYPE_NVENC(i): # macro -# return (((i)<3)?((0x0000001b)+(i)):((0x0000003f)+(i)-3)) -def NV2080_ENGINE_TYPE_IS_NVENC(i): # macro - return ((((i)>=(0x0000001b)) and ((i)<=(0x0000001d))) or (((i)==(0x0000003f)))) -# def NV2080_ENGINE_TYPE_NVENC_IDX(i): # macro -# return (((i)<=(0x0000001d))?((i)-(0x0000001b)):((i)-(0x0000003f)+3)) -def NV2080_ENGINE_TYPE_NVDEC(i): # macro - return ((0x00000013)+(i)) -def NV2080_ENGINE_TYPE_IS_NVDEC(i): # macro - return (((i)>=(0x00000013)) and ((i)=(0x0000002b)) and ((i)=(0x00000001)) and ((i)((0x00000000))) and ((i)<((0x00000054)))) -NV2080_CLIENT_TYPE_TEX = (0x00000001) # macro -NV2080_CLIENT_TYPE_COLOR = (0x00000002) # macro -NV2080_CLIENT_TYPE_DEPTH = (0x00000003) # macro -NV2080_CLIENT_TYPE_DA = (0x00000004) # macro -NV2080_CLIENT_TYPE_FE = (0x00000005) # macro -NV2080_CLIENT_TYPE_SCC = (0x00000006) # macro -NV2080_CLIENT_TYPE_WID = (0x00000007) # macro -NV2080_CLIENT_TYPE_MSVLD = (0x00000008) # macro -NV2080_CLIENT_TYPE_MSPDEC = (0x00000009) # macro -NV2080_CLIENT_TYPE_MSPPP = (0x0000000a) # macro -NV2080_CLIENT_TYPE_VIC = (0x0000000b) # macro -NV2080_CLIENT_TYPE_ALLCLIENTS = (0xffffffff) # macro -NV2080_GC5_EXIT_COMPLETE = (0x00000001) # macro -NV2080_GC5_ENTRY_ABORTED = (0x00000002) # macro -NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION = (0x00000000) # macro -NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION = (0x00000001) # macro -NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT = (0x4000) # macro -# NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX = 7 : 0 # macro -# NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK = 15 : 8 # macro -# NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON = 23 : 16 # macro -NV20_SUBDEVICE_0 = (0x00002080) # macro -# NV2080_MAX_SUBDEVICES = NV_MAX_SUBDEVICES # macro -NV2080_ALLOC_PARAMETERS_MESSAGE_ID = (0x2080) # macro -class struct__cl2080_tag0(Structure): - pass - -struct__cl2080_tag0._pack_ = 1 # source:False -struct__cl2080_tag0._fields_ = [ - ('Reserved00', ctypes.c_uint32 * 1984), -] - -Nv2080Typedef = struct__cl2080_tag0 -Nv20Subdevice0 = struct__cl2080_tag0 -NV2080_TYPEDEF = Nv20Subdevice0 # macro -class struct_Nv2080HdcpStatusChangeNotificationRec(Structure): - pass - -struct_Nv2080HdcpStatusChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080HdcpStatusChangeNotificationRec._fields_ = [ - ('displayId', ctypes.c_uint32), - ('hdcpStatusChangeNotif', ctypes.c_uint32), -] - -Nv2080HdcpStatusChangeNotification = struct_Nv2080HdcpStatusChangeNotificationRec -class struct_Nv2080PStateChangeNotificationRec(Structure): - pass - -class struct_Nv2080PStateChangeNotificationRec_timeStamp(Structure): - pass - -struct_Nv2080PStateChangeNotificationRec_timeStamp._pack_ = 1 # source:False -struct_Nv2080PStateChangeNotificationRec_timeStamp._fields_ = [ - ('nanoseconds', ctypes.c_uint32 * 2), -] - -struct_Nv2080PStateChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080PStateChangeNotificationRec._fields_ = [ - ('timeStamp', struct_Nv2080PStateChangeNotificationRec_timeStamp), - ('NewPstate', ctypes.c_uint32), -] - -Nv2080PStateChangeNotification = struct_Nv2080PStateChangeNotificationRec -class struct_Nv2080ClocksChangeNotificationRec(Structure): - pass - -class struct_Nv2080ClocksChangeNotificationRec_timeStamp(Structure): - pass - -struct_Nv2080ClocksChangeNotificationRec_timeStamp._pack_ = 1 # source:False -struct_Nv2080ClocksChangeNotificationRec_timeStamp._fields_ = [ - ('nanoseconds', ctypes.c_uint32 * 2), -] - -struct_Nv2080ClocksChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080ClocksChangeNotificationRec._fields_ = [ - ('timeStamp', struct_Nv2080ClocksChangeNotificationRec_timeStamp), -] - -Nv2080ClocksChangeNotification = struct_Nv2080ClocksChangeNotificationRec -class struct_Nv2080WorkloadModulationChangeNotificationRec(Structure): - pass - -class struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp(Structure): - pass - -struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp._pack_ = 1 # source:False -struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp._fields_ = [ - ('nanoseconds', ctypes.c_uint32 * 2), -] - -struct_Nv2080WorkloadModulationChangeNotificationRec._pack_ = 1 # source:False -struct_Nv2080WorkloadModulationChangeNotificationRec._fields_ = [ - ('timeStamp', struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp), - ('WorkloadModulationEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -Nv2080WorkloadModulationChangeNotification = struct_Nv2080WorkloadModulationChangeNotificationRec -class struct_c__SA_Nv2080HotplugNotification(Structure): - pass - -struct_c__SA_Nv2080HotplugNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080HotplugNotification._fields_ = [ - ('plugDisplayMask', ctypes.c_uint32), - ('unplugDisplayMask', ctypes.c_uint32), -] - -Nv2080HotplugNotification = struct_c__SA_Nv2080HotplugNotification -class struct_c__SA_Nv2080PowerEventNotification(Structure): - pass - -struct_c__SA_Nv2080PowerEventNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080PowerEventNotification._fields_ = [ - ('bSwitchToAC', ctypes.c_ubyte), - ('bGPUCapabilityChanged', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('displayMaskAffected', ctypes.c_uint32), -] - -Nv2080PowerEventNotification = struct_c__SA_Nv2080PowerEventNotification -class struct_Nv2080DpIrqNotificationRec(Structure): - pass - -struct_Nv2080DpIrqNotificationRec._pack_ = 1 # source:False -struct_Nv2080DpIrqNotificationRec._fields_ = [ - ('displayId', ctypes.c_uint32), -] - -Nv2080DpIrqNotification = struct_Nv2080DpIrqNotificationRec -class struct_Nv2080DstateXusbPpcNotificationRec(Structure): - pass - -struct_Nv2080DstateXusbPpcNotificationRec._pack_ = 1 # source:False -struct_Nv2080DstateXusbPpcNotificationRec._fields_ = [ - ('dstateXusb', ctypes.c_uint32), - ('dstatePpc', ctypes.c_uint32), -] - -Nv2080DstateXusbPpcNotification = struct_Nv2080DstateXusbPpcNotificationRec -class struct_Nv2080XusbPpcConnectStateNotificationRec(Structure): - pass - -struct_Nv2080XusbPpcConnectStateNotificationRec._pack_ = 1 # source:False -struct_Nv2080XusbPpcConnectStateNotificationRec._fields_ = [ - ('bConnected', ctypes.c_ubyte), -] - -Nv2080XusbPpcConnectStateNotification = struct_Nv2080XusbPpcConnectStateNotificationRec -class struct_Nv2080ACPIEvent(Structure): - pass - -struct_Nv2080ACPIEvent._pack_ = 1 # source:False -struct_Nv2080ACPIEvent._fields_ = [ - ('event', ctypes.c_uint32), -] - -Nv2080ACPIEvent = struct_Nv2080ACPIEvent -class struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC(Structure): - pass - -struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC._pack_ = 1 # source:False -struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC._fields_ = [ - ('currentZone', ctypes.c_uint32), -] - -NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC -class struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC(Structure): - pass - -struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC._pack_ = 1 # source:False -struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC._fields_ = [ - ('currentZone', ctypes.c_uint32), -] - -NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC -class struct_Nv2080AudioHdcpRequestRec(Structure): - pass - -struct_Nv2080AudioHdcpRequestRec._pack_ = 1 # source:False -struct_Nv2080AudioHdcpRequestRec._fields_ = [ - ('displayId', ctypes.c_uint32), - ('requestedState', ctypes.c_uint32), -] - -Nv2080AudioHdcpRequest = struct_Nv2080AudioHdcpRequestRec -class struct_Nv2080GC5GpuReadyParams(Structure): - pass - -struct_Nv2080GC5GpuReadyParams._pack_ = 1 # source:False -struct_Nv2080GC5GpuReadyParams._fields_ = [ - ('event', ctypes.c_uint32), - ('sciIntr0', ctypes.c_uint32), - ('sciIntr1', ctypes.c_uint32), -] - -Nv2080GC5GpuReadyParams = struct_Nv2080GC5GpuReadyParams -class struct_c__SA_Nv2080PrivRegAccessFaultNotification(Structure): - pass - -struct_c__SA_Nv2080PrivRegAccessFaultNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080PrivRegAccessFaultNotification._fields_ = [ - ('errAddr', ctypes.c_uint32), -] - -Nv2080PrivRegAccessFaultNotification = struct_c__SA_Nv2080PrivRegAccessFaultNotification -class struct_Nv2080DstateHdaCodecNotificationRec(Structure): - pass - -struct_Nv2080DstateHdaCodecNotificationRec._pack_ = 1 # source:False -struct_Nv2080DstateHdaCodecNotificationRec._fields_ = [ - ('dstateHdaCodec', ctypes.c_uint32), -] - -Nv2080DstateHdaCodecNotification = struct_Nv2080DstateHdaCodecNotificationRec -class struct_Nv2080HdmiFrlRequestNotificationRec(Structure): - pass - -struct_Nv2080HdmiFrlRequestNotificationRec._pack_ = 1 # source:False -struct_Nv2080HdmiFrlRequestNotificationRec._fields_ = [ - ('displayId', ctypes.c_uint32), -] - -Nv2080HdmiFrlRequestNotification = struct_Nv2080HdmiFrlRequestNotificationRec -class struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS(Structure): - pass - -struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS._pack_ = 1 # source:False -struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS._fields_ = [ - ('platformPowerModeIndex', ctypes.c_ubyte), - ('platformPowerModeMask', ctypes.c_ubyte), - ('eventReason', ctypes.c_ubyte), -] - -NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS = struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS -class struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE(Structure): - pass - -struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE._pack_ = 1 # source:False -struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE._fields_ = [ - ('workloadType', ctypes.c_ubyte), -] - -NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE = struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE -class struct_c__SA_Nv2080QosIntrNotification(Structure): - pass - -struct_c__SA_Nv2080QosIntrNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080QosIntrNotification._fields_ = [ - ('engineType', ctypes.c_uint32), -] - -Nv2080QosIntrNotification = struct_c__SA_Nv2080QosIntrNotification -class struct_c__SA_Nv2080EccDbeNotification(Structure): - pass - -struct_c__SA_Nv2080EccDbeNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080EccDbeNotification._fields_ = [ - ('physAddress', ctypes.c_uint64), -] - -Nv2080EccDbeNotification = struct_c__SA_Nv2080EccDbeNotification -class struct_c__SA_Nv2080LpwrDifrPrefetchNotification(Structure): - pass - -struct_c__SA_Nv2080LpwrDifrPrefetchNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080LpwrDifrPrefetchNotification._fields_ = [ - ('l2CacheSize', ctypes.c_uint32), -] - -Nv2080LpwrDifrPrefetchNotification = struct_c__SA_Nv2080LpwrDifrPrefetchNotification -class struct_c__SA_Nv2080NvlinkLnkChangeNotification(Structure): - pass - -struct_c__SA_Nv2080NvlinkLnkChangeNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080NvlinkLnkChangeNotification._fields_ = [ - ('GpuId', ctypes.c_uint32), - ('linkId', ctypes.c_uint32), -] - -Nv2080NvlinkLnkChangeNotification = struct_c__SA_Nv2080NvlinkLnkChangeNotification -class struct_c__SA_Nv2080VrrSetTimeoutNotification(Structure): - pass - -struct_c__SA_Nv2080VrrSetTimeoutNotification._pack_ = 1 # source:False -struct_c__SA_Nv2080VrrSetTimeoutNotification._fields_ = [ - ('head', ctypes.c_uint32), -] - -Nv2080VrrSetTimeoutNotification = struct_c__SA_Nv2080VrrSetTimeoutNotification -class struct_NV2080_ALLOC_PARAMETERS(Structure): - pass - -struct_NV2080_ALLOC_PARAMETERS._pack_ = 1 # source:False +class struct_NV2080_ALLOC_PARAMETERS(Struct): pass struct_NV2080_ALLOC_PARAMETERS._fields_ = [ - ('subDeviceId', ctypes.c_uint32), + ('subDeviceId', NvU32), ] - NV2080_ALLOC_PARAMETERS = struct_NV2080_ALLOC_PARAMETERS -_clc56f_h_ = True # macro -AMPERE_CHANNEL_GPFIFO_A = (0x0000c56f) # macro -# NVC56F_TYPEDEF = AMPERE_CHANNELChannelGPFifoA # macro -NVC56F_NUMBER_OF_SUBCHANNELS = (8) # macro -NVC56F_SET_OBJECT = (0x00000000) # macro -# NVC56F_SET_OBJECT_NVCLASS = 15 : 0 # macro -# NVC56F_SET_OBJECT_ENGINE = 20 : 16 # macro -NVC56F_SET_OBJECT_ENGINE_SW = 0x0000001f # macro -NVC56F_ILLEGAL = (0x00000004) # macro -# NVC56F_ILLEGAL_HANDLE = 31 : 0 # macro -NVC56F_NOP = (0x00000008) # macro -# NVC56F_NOP_HANDLE = 31 : 0 # macro -NVC56F_SEMAPHOREA = (0x00000010) # macro -# NVC56F_SEMAPHOREA_OFFSET_UPPER = 7 : 0 # macro -NVC56F_SEMAPHOREB = (0x00000014) # macro -# NVC56F_SEMAPHOREB_OFFSET_LOWER = 31 : 2 # macro -NVC56F_SEMAPHOREC = (0x00000018) # macro -# NVC56F_SEMAPHOREC_PAYLOAD = 31 : 0 # macro -NVC56F_SEMAPHORED = (0x0000001C) # macro -# NVC56F_SEMAPHORED_OPERATION = 4 : 0 # macro -NVC56F_SEMAPHORED_OPERATION_ACQUIRE = 0x00000001 # macro -NVC56F_SEMAPHORED_OPERATION_RELEASE = 0x00000002 # macro -NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ = 0x00000004 # macro -NVC56F_SEMAPHORED_OPERATION_ACQ_AND = 0x00000008 # macro -NVC56F_SEMAPHORED_OPERATION_REDUCTION = 0x00000010 # macro -# NVC56F_SEMAPHORED_ACQUIRE_SWITCH = 12 : 12 # macro -NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED = 0x00000000 # macro -NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED = 0x00000001 # macro -# NVC56F_SEMAPHORED_RELEASE_WFI = 20 : 20 # macro -NVC56F_SEMAPHORED_RELEASE_WFI_EN = 0x00000000 # macro -NVC56F_SEMAPHORED_RELEASE_WFI_DIS = 0x00000001 # macro -# NVC56F_SEMAPHORED_RELEASE_SIZE = 24 : 24 # macro -NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE = 0x00000000 # macro -NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE = 0x00000001 # macro -# NVC56F_SEMAPHORED_REDUCTION = 30 : 27 # macro -NVC56F_SEMAPHORED_REDUCTION_MIN = 0x00000000 # macro -NVC56F_SEMAPHORED_REDUCTION_MAX = 0x00000001 # macro -NVC56F_SEMAPHORED_REDUCTION_XOR = 0x00000002 # macro -NVC56F_SEMAPHORED_REDUCTION_AND = 0x00000003 # macro -NVC56F_SEMAPHORED_REDUCTION_OR = 0x00000004 # macro -NVC56F_SEMAPHORED_REDUCTION_ADD = 0x00000005 # macro -NVC56F_SEMAPHORED_REDUCTION_INC = 0x00000006 # macro -NVC56F_SEMAPHORED_REDUCTION_DEC = 0x00000007 # macro -# NVC56F_SEMAPHORED_FORMAT = 31 : 31 # macro -NVC56F_SEMAPHORED_FORMAT_SIGNED = 0x00000000 # macro -NVC56F_SEMAPHORED_FORMAT_UNSIGNED = 0x00000001 # macro -NVC56F_NON_STALL_INTERRUPT = (0x00000020) # macro -# NVC56F_NON_STALL_INTERRUPT_HANDLE = 31 : 0 # macro -NVC56F_FB_FLUSH = (0x00000024) # macro -# NVC56F_FB_FLUSH_HANDLE = 31 : 0 # macro -NVC56F_MEM_OP_A = (0x00000028) # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = 5 : 0 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = 5 : 0 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = 10 : 6 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = 7 : 6 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = 6 : 0 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = 11 : 11 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 # macro -NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 # macro -# NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = 31 : 12 # macro -NVC56F_MEM_OP_B = (0x0000002c) # macro -# NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = 31 : 0 # macro -NVC56F_MEM_OP_C = (0x00000030) # macro -# NVC56F_MEM_OP_C_MEMBAR_TYPE = 2 : 0 # macro -NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 # macro -NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB = 0 : 0 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC = 1 : 1 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY = 4 : 2 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = 6 : 5 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = 9 : 7 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = 9 : 7 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = 11 : 10 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 # macro -NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 # macro -# NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = 31 : 12 # macro -# NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = 19 : 0 # macro -NVC56F_MEM_OP_D = (0x00000034) # macro -# NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = 26 : 0 # macro -# NVC56F_MEM_OP_D_OPERATION = 31 : 27 # macro -NVC56F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 # macro -NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 # macro -NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a # macro -NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d # macro -NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e # macro -NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e # macro -NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f # macro -NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 # macro -NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 # macro -NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 # macro -# NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = 1 : 0 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 # macro -# NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = 2 : 2 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 # macro -NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 # macro -# NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = 6 : 3 # macro -NVC56F_SET_REFERENCE = (0x00000050) # macro -# NVC56F_SET_REFERENCE_COUNT = 31 : 0 # macro -NVC56F_SEM_ADDR_LO = (0x0000005c) # macro -# NVC56F_SEM_ADDR_LO_OFFSET = 31 : 2 # macro -NVC56F_SEM_ADDR_HI = (0x00000060) # macro -# NVC56F_SEM_ADDR_HI_OFFSET = 7 : 0 # macro -NVC56F_SEM_PAYLOAD_LO = (0x00000064) # macro -# NVC56F_SEM_PAYLOAD_LO_PAYLOAD = 31 : 0 # macro -NVC56F_SEM_PAYLOAD_HI = (0x00000068) # macro -# NVC56F_SEM_PAYLOAD_HI_PAYLOAD = 31 : 0 # macro -NVC56F_SEM_EXECUTE = (0x0000006c) # macro -# NVC56F_SEM_EXECUTE_OPERATION = 2 : 0 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # macro -NVC56F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ = 0x00000002 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND = 0x00000004 # macro -NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR = 0x00000005 # macro -NVC56F_SEM_EXECUTE_OPERATION_REDUCTION = 0x00000006 # macro -# NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG = 12 : 12 # macro -NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS = 0x00000000 # macro -NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_RELEASE_WFI = 20 : 20 # macro -NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # macro -NVC56F_SEM_EXECUTE_RELEASE_WFI_EN = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_PAYLOAD_SIZE = 24 : 24 # macro -NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # macro -NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP = 25 : 25 # macro -NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000 # macro -NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001 # macro -# NVC56F_SEM_EXECUTE_REDUCTION = 30 : 27 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IMIN = 0x00000000 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IMAX = 0x00000001 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IXOR = 0x00000002 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IAND = 0x00000003 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IOR = 0x00000004 # macro -NVC56F_SEM_EXECUTE_REDUCTION_IADD = 0x00000005 # macro -NVC56F_SEM_EXECUTE_REDUCTION_INC = 0x00000006 # macro -NVC56F_SEM_EXECUTE_REDUCTION_DEC = 0x00000007 # macro -# NVC56F_SEM_EXECUTE_REDUCTION_FORMAT = 31 : 31 # macro -NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000000 # macro -NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000001 # macro -NVC56F_WFI = (0x00000078) # macro -# NVC56F_WFI_SCOPE = 0 : 0 # macro -NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 # macro -NVC56F_WFI_SCOPE_CURRENT_VEID = 0x00000000 # macro -NVC56F_WFI_SCOPE_ALL = 0x00000001 # macro -NVC56F_YIELD = (0x00000080) # macro -# NVC56F_YIELD_OP = 1 : 0 # macro -NVC56F_YIELD_OP_NOP = 0x00000000 # macro -NVC56F_YIELD_OP_TSG = 0x00000003 # macro -NVC56F_CLEAR_FAULTED = (0x00000084) # macro -# NVC56F_CLEAR_FAULTED_HANDLE = 30 : 0 # macro -# NVC56F_CLEAR_FAULTED_TYPE = 31 : 31 # macro -NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED = 0x00000000 # macro -NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED = 0x00000001 # macro -NVC56F_GP_ENTRY__SIZE = 8 # macro -# NVC56F_GP_ENTRY0_FETCH = 0 : 0 # macro -NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # macro -NVC56F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # macro -# NVC56F_GP_ENTRY0_GET = 31 : 2 # macro -# NVC56F_GP_ENTRY0_OPERAND = 31 : 0 # macro -# NVC56F_GP_ENTRY1_GET_HI = 7 : 0 # macro -# NVC56F_GP_ENTRY1_LEVEL = 9 : 9 # macro -NVC56F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # macro -NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # macro -# NVC56F_GP_ENTRY1_LENGTH = 30 : 10 # macro -# NVC56F_GP_ENTRY1_SYNC = 31 : 31 # macro -NVC56F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # macro -NVC56F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # macro -# NVC56F_GP_ENTRY1_OPCODE = 7 : 0 # macro -NVC56F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # macro -NVC56F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # macro -NVC56F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # macro -NVC56F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # macro -# NVC56F_DMA_METHOD_ADDRESS_OLD = 12 : 2 # macro -# NVC56F_DMA_METHOD_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_SUBDEVICE_MASK = 15 : 4 # macro -# NVC56F_DMA_METHOD_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_TERT_OP = 17 : 16 # macro -NVC56F_DMA_TERT_OP_GRP0_INC_METHOD = (0x00000000) # macro -NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK = (0x00000001) # macro -NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK = (0x00000002) # macro -NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK = (0x00000003) # macro -NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD = (0x00000000) # macro -# NVC56F_DMA_METHOD_COUNT_OLD = 28 : 18 # macro -# NVC56F_DMA_METHOD_COUNT = 28 : 16 # macro -# NVC56F_DMA_IMMD_DATA = 28 : 16 # macro -# NVC56F_DMA_SEC_OP = 31 : 29 # macro -NVC56F_DMA_SEC_OP_GRP0_USE_TERT = (0x00000000) # macro -NVC56F_DMA_SEC_OP_INC_METHOD = (0x00000001) # macro -NVC56F_DMA_SEC_OP_GRP2_USE_TERT = (0x00000002) # macro -NVC56F_DMA_SEC_OP_NON_INC_METHOD = (0x00000003) # macro -NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD = (0x00000004) # macro -NVC56F_DMA_SEC_OP_ONE_INC = (0x00000005) # macro -NVC56F_DMA_SEC_OP_RESERVED6 = (0x00000006) # macro -NVC56F_DMA_SEC_OP_END_PB_SEGMENT = (0x00000007) # macro -# NVC56F_DMA_INCR_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_INCR_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_INCR_COUNT = 28 : 16 # macro -# NVC56F_DMA_INCR_OPCODE = 31 : 29 # macro -NVC56F_DMA_INCR_OPCODE_VALUE = (0x00000001) # macro -# NVC56F_DMA_INCR_DATA = 31 : 0 # macro -# NVC56F_DMA_NONINCR_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_NONINCR_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_NONINCR_COUNT = 28 : 16 # macro -# NVC56F_DMA_NONINCR_OPCODE = 31 : 29 # macro -NVC56F_DMA_NONINCR_OPCODE_VALUE = (0x00000003) # macro -# NVC56F_DMA_NONINCR_DATA = 31 : 0 # macro -# NVC56F_DMA_ONEINCR_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_ONEINCR_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_ONEINCR_COUNT = 28 : 16 # macro -# NVC56F_DMA_ONEINCR_OPCODE = 31 : 29 # macro -NVC56F_DMA_ONEINCR_OPCODE_VALUE = (0x00000005) # macro -# NVC56F_DMA_ONEINCR_DATA = 31 : 0 # macro -NVC56F_DMA_NOP = (0x00000000) # macro -# NVC56F_DMA_IMMD_ADDRESS = 11 : 0 # macro -# NVC56F_DMA_IMMD_SUBCHANNEL = 15 : 13 # macro -# NVC56F_DMA_IMMD_OPCODE = 31 : 29 # macro -NVC56F_DMA_IMMD_OPCODE_VALUE = (0x00000004) # macro -# NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE = 15 : 4 # macro -# NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE = 31 : 16 # macro -NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000001) # macro -# NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE = 15 : 4 # macro -# NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE = 31 : 16 # macro -NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000002) # macro -# NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE = 31 : 16 # macro -NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000003) # macro -# NVC56F_DMA_ENDSEG_OPCODE = 31 : 29 # macro -NVC56F_DMA_ENDSEG_OPCODE_VALUE = (0x00000007) # macro -# NVC56F_DMA_ADDRESS = 12 : 2 # macro -# NVC56F_DMA_SUBCH = 15 : 13 # macro -# NVC56F_DMA_OPCODE3 = 17 : 16 # macro -NVC56F_DMA_OPCODE3_NONE = (0x00000000) # macro -# NVC56F_DMA_COUNT = 28 : 18 # macro -# NVC56F_DMA_OPCODE = 31 : 29 # macro -NVC56F_DMA_OPCODE_METHOD = (0x00000000) # macro -NVC56F_DMA_OPCODE_NONINC_METHOD = (0x00000002) # macro -# NVC56F_DMA_DATA = 31 : 0 # macro -class struct_Nvc56fControl_struct(Structure): - pass - -struct_Nvc56fControl_struct._pack_ = 1 # source:False +class struct__cl2080_tag0(Struct): pass +struct__cl2080_tag0._fields_ = [ + ('Reserved00', (NvV32 * 1984)), +] +class volatile_struct__cl2080_tag0(Struct): pass +Nv2080Typedef = volatile_struct__cl2080_tag0 +volatile_struct__cl2080_tag0._fields_ = [ + ('Reserved00', (NvV32 * 1984)), +] +Nv20Subdevice0 = volatile_struct__cl2080_tag0 +class struct_Nv2080HdcpStatusChangeNotificationRec(Struct): pass +struct_Nv2080HdcpStatusChangeNotificationRec._fields_ = [ + ('displayId', NvU32), + ('hdcpStatusChangeNotif', NvU32), +] +Nv2080HdcpStatusChangeNotification = struct_Nv2080HdcpStatusChangeNotificationRec +class struct_Nv2080PStateChangeNotificationRec(Struct): pass +class struct_Nv2080PStateChangeNotificationRec_timeStamp(Struct): pass +struct_Nv2080PStateChangeNotificationRec_timeStamp._fields_ = [ + ('nanoseconds', (NvU32 * 2)), +] +struct_Nv2080PStateChangeNotificationRec._fields_ = [ + ('timeStamp', struct_Nv2080PStateChangeNotificationRec_timeStamp), + ('NewPstate', NvU32), +] +Nv2080PStateChangeNotification = struct_Nv2080PStateChangeNotificationRec +class struct_Nv2080ClocksChangeNotificationRec(Struct): pass +class struct_Nv2080ClocksChangeNotificationRec_timeStamp(Struct): pass +struct_Nv2080ClocksChangeNotificationRec_timeStamp._fields_ = [ + ('nanoseconds', (NvU32 * 2)), +] +struct_Nv2080ClocksChangeNotificationRec._fields_ = [ + ('timeStamp', struct_Nv2080ClocksChangeNotificationRec_timeStamp), +] +Nv2080ClocksChangeNotification = struct_Nv2080ClocksChangeNotificationRec +class struct_Nv2080WorkloadModulationChangeNotificationRec(Struct): pass +class struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp(Struct): pass +struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp._fields_ = [ + ('nanoseconds', (NvU32 * 2)), +] +NvBool = ctypes.c_ubyte +struct_Nv2080WorkloadModulationChangeNotificationRec._fields_ = [ + ('timeStamp', struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp), + ('WorkloadModulationEnabled', NvBool), +] +Nv2080WorkloadModulationChangeNotification = struct_Nv2080WorkloadModulationChangeNotificationRec +class Nv2080HotplugNotification(Struct): pass +Nv2080HotplugNotification._fields_ = [ + ('plugDisplayMask', NvU32), + ('unplugDisplayMask', NvU32), +] +class Nv2080PowerEventNotification(Struct): pass +Nv2080PowerEventNotification._fields_ = [ + ('bSwitchToAC', NvBool), + ('bGPUCapabilityChanged', NvBool), + ('displayMaskAffected', NvU32), +] +class struct_Nv2080DpIrqNotificationRec(Struct): pass +struct_Nv2080DpIrqNotificationRec._fields_ = [ + ('displayId', NvU32), +] +Nv2080DpIrqNotification = struct_Nv2080DpIrqNotificationRec +class struct_Nv2080DstateXusbPpcNotificationRec(Struct): pass +struct_Nv2080DstateXusbPpcNotificationRec._fields_ = [ + ('dstateXusb', NvU32), + ('dstatePpc', NvU32), +] +Nv2080DstateXusbPpcNotification = struct_Nv2080DstateXusbPpcNotificationRec +class struct_Nv2080XusbPpcConnectStateNotificationRec(Struct): pass +struct_Nv2080XusbPpcConnectStateNotificationRec._fields_ = [ + ('bConnected', NvBool), +] +Nv2080XusbPpcConnectStateNotification = struct_Nv2080XusbPpcConnectStateNotificationRec +class struct_Nv2080ACPIEvent(Struct): pass +struct_Nv2080ACPIEvent._fields_ = [ + ('event', NvU32), +] +Nv2080ACPIEvent = struct_Nv2080ACPIEvent +class struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC(Struct): pass +struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC._fields_ = [ + ('currentZone', NvU32), +] +NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC +class struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC(Struct): pass +struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC._fields_ = [ + ('currentZone', NvU32), +] +NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC +class struct_Nv2080AudioHdcpRequestRec(Struct): pass +struct_Nv2080AudioHdcpRequestRec._fields_ = [ + ('displayId', NvU32), + ('requestedState', NvU32), +] +Nv2080AudioHdcpRequest = struct_Nv2080AudioHdcpRequestRec +class struct_Nv2080GC5GpuReadyParams(Struct): pass +struct_Nv2080GC5GpuReadyParams._fields_ = [ + ('event', NvU32), + ('sciIntr0', NvU32), + ('sciIntr1', NvU32), +] +Nv2080GC5GpuReadyParams = struct_Nv2080GC5GpuReadyParams +class Nv2080PrivRegAccessFaultNotification(Struct): pass +Nv2080PrivRegAccessFaultNotification._fields_ = [ + ('errAddr', NvU32), +] +class struct_Nv2080DstateHdaCodecNotificationRec(Struct): pass +struct_Nv2080DstateHdaCodecNotificationRec._fields_ = [ + ('dstateHdaCodec', NvU32), +] +Nv2080DstateHdaCodecNotification = struct_Nv2080DstateHdaCodecNotificationRec +class struct_Nv2080HdmiFrlRequestNotificationRec(Struct): pass +struct_Nv2080HdmiFrlRequestNotificationRec._fields_ = [ + ('displayId', NvU32), +] +Nv2080HdmiFrlRequestNotification = struct_Nv2080HdmiFrlRequestNotificationRec +class struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS(Struct): pass +NvU8 = ctypes.c_ubyte +struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS._fields_ = [ + ('platformPowerModeIndex', NvU8), + ('platformPowerModeMask', NvU8), + ('eventReason', NvU8), +] +NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS = struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS +class struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE(Struct): pass +struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE._fields_ = [ + ('workloadType', NvU8), +] +NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE = struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE +class Nv2080QosIntrNotification(Struct): pass +Nv2080QosIntrNotification._fields_ = [ + ('engineType', NvU32), +] +class Nv2080EccDbeNotification(Struct): pass +Nv2080EccDbeNotification._fields_ = [ + ('physAddress', NvU64), +] +class Nv2080LpwrDifrPrefetchNotification(Struct): pass +Nv2080LpwrDifrPrefetchNotification._fields_ = [ + ('l2CacheSize', NvU32), +] +class Nv2080NvlinkLnkChangeNotification(Struct): pass +Nv2080NvlinkLnkChangeNotification._fields_ = [ + ('GpuId', NvU32), + ('linkId', NvU32), +] +class Nv2080VrrSetTimeoutNotification(Struct): pass +Nv2080VrrSetTimeoutNotification._fields_ = [ + ('head', NvU32), +] +class struct_Nvc56fControl_struct(Struct): pass struct_Nvc56fControl_struct._fields_ = [ - ('Ignored00', ctypes.c_uint32 * 16), - ('Put', ctypes.c_uint32), - ('Get', ctypes.c_uint32), - ('Reference', ctypes.c_uint32), - ('PutHi', ctypes.c_uint32), - ('Ignored01', ctypes.c_uint32 * 2), - ('TopLevelGet', ctypes.c_uint32), - ('TopLevelGetHi', ctypes.c_uint32), - ('GetHi', ctypes.c_uint32), - ('Ignored02', ctypes.c_uint32 * 7), - ('Ignored03', ctypes.c_uint32), - ('Ignored04', ctypes.c_uint32 * 1), - ('GPGet', ctypes.c_uint32), - ('GPPut', ctypes.c_uint32), - ('Ignored05', ctypes.c_uint32 * 92), + ('Ignored00', (NvU32 * 16)), + ('Put', NvU32), + ('Get', NvU32), + ('Reference', NvU32), + ('PutHi', NvU32), + ('Ignored01', (NvU32 * 2)), + ('TopLevelGet', NvU32), + ('TopLevelGetHi', NvU32), + ('GetHi', NvU32), + ('Ignored02', (NvU32 * 7)), + ('Ignored03', NvU32), + ('Ignored04', (NvU32 * 1)), + ('GPGet', NvU32), + ('GPPut', NvU32), + ('Ignored05', (NvU32 * 92)), ] - -Nvc56fControl = struct_Nvc56fControl_struct -AmpereAControlGPFifo = struct_Nvc56fControl_struct -__gh100_clc86f_h__ = True # macro -HOPPER_CHANNEL_GPFIFO_A = (0x0000c86f) # macro -NVC86F_SET_OBJECT = (0x00000000) # macro -NVC86F_SEM_ADDR_LO = (0x0000005c) # macro -# NVC86F_SEM_ADDR_LO_OFFSET = 31 : 2 # macro -NVC86F_SEM_ADDR_HI = (0x00000060) # macro -# NVC86F_SEM_ADDR_HI_OFFSET = 24 : 0 # macro -NVC86F_SEM_PAYLOAD_LO = (0x00000064) # macro -NVC86F_SEM_PAYLOAD_HI = (0x00000068) # macro -NVC86F_SEM_EXECUTE = (0x0000006c) # macro -# NVC86F_SEM_EXECUTE_OPERATION = 2 : 0 # macro -NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # macro -NVC86F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # macro -# NVC86F_SEM_EXECUTE_RELEASE_WFI = 20 : 20 # macro -NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # macro -# NVC86F_SEM_EXECUTE_PAYLOAD_SIZE = 24 : 24 # macro -NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # macro -NVC86F_GP_ENTRY__SIZE = 8 # macro -# NVC86F_GP_ENTRY0_FETCH = 0 : 0 # macro -NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # macro -NVC86F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # macro -# NVC86F_GP_ENTRY0_GET = 31 : 2 # macro -# NVC86F_GP_ENTRY0_OPERAND = 31 : 0 # macro -# NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = 24 : 8 # macro -# NVC86F_GP_ENTRY1_GET_HI = 7 : 0 # macro -# NVC86F_GP_ENTRY1_LEVEL = 9 : 9 # macro -NVC86F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # macro -NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # macro -# NVC86F_GP_ENTRY1_LENGTH = 30 : 10 # macro -# NVC86F_GP_ENTRY1_SYNC = 31 : 31 # macro -NVC86F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # macro -NVC86F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # macro -# NVC86F_GP_ENTRY1_OPCODE = 7 : 0 # macro -NVC86F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # macro -NVC86F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # macro -NVC86F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # macro -NVC86F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # macro -NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 # macro -NVC86F_WFI = (0x00000078) # macro -# NVC86F_WFI_SCOPE = 0 : 0 # macro -NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 # macro -NVC86F_WFI_SCOPE_CURRENT_VEID = 0x00000000 # macro -NVC86F_WFI_SCOPE_ALL = 0x00000001 # macro -NVC86F_MEM_OP_A = (0x00000028) # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID = 5 : 0 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE = 5 : 0 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID = 10 : 6 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE = 7 : 6 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID = 8 : 0 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR = 11 : 11 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 # macro -NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 # macro -# NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO = 31 : 12 # macro -NVC86F_MEM_OP_B = (0x0000002c) # macro -# NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI = 31 : 0 # macro -NVC86F_MEM_OP_C = (0x00000030) # macro -# NVC86F_MEM_OP_C_MEMBAR_TYPE = 2 : 0 # macro -NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 # macro -NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB = 0 : 0 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC = 1 : 1 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY = 4 : 2 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE = 6 : 5 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE = 9 : 7 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL = 9 : 7 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE = 11 : 10 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 # macro -NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 # macro -# NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO = 31 : 12 # macro -# NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG = 19 : 0 # macro -NVC86F_MEM_OP_D = (0x00000034) # macro -# NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI = 26 : 0 # macro -# NVC86F_MEM_OP_D_OPERATION = 31 : 27 # macro -NVC86F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 # macro -NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 # macro -NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a # macro -NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION = 0x0000000b # macro -NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d # macro -NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e # macro -NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e # macro -NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f # macro -NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 # macro -NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 # macro -NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 # macro -# NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE = 1 : 0 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 # macro -# NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE = 2 : 2 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 # macro -NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 # macro -# NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK = 6 : 3 # macro -# NVC86F_MEM_OP_D_MMU_OPERATION_TYPE = 23 : 20 # macro -NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED = 0x00000000 # macro -NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP = 0x00000001 # macro -class struct_Nvc86fControl_struct(Structure): - pass - -struct_Nvc86fControl_struct._pack_ = 1 # source:False +class volatile_struct_Nvc56fControl_struct(Struct): pass +Nvc56fControl = volatile_struct_Nvc56fControl_struct +volatile_struct_Nvc56fControl_struct._fields_ = [ + ('Ignored00', (NvU32 * 16)), + ('Put', NvU32), + ('Get', NvU32), + ('Reference', NvU32), + ('PutHi', NvU32), + ('Ignored01', (NvU32 * 2)), + ('TopLevelGet', NvU32), + ('TopLevelGetHi', NvU32), + ('GetHi', NvU32), + ('Ignored02', (NvU32 * 7)), + ('Ignored03', NvU32), + ('Ignored04', (NvU32 * 1)), + ('GPGet', NvU32), + ('GPPut', NvU32), + ('Ignored05', (NvU32 * 92)), +] +AmpereAControlGPFifo = volatile_struct_Nvc56fControl_struct +class struct_Nvc86fControl_struct(Struct): pass struct_Nvc86fControl_struct._fields_ = [ - ('Ignored00', ctypes.c_uint32 * 16), - ('Put', ctypes.c_uint32), - ('Get', ctypes.c_uint32), - ('Reference', ctypes.c_uint32), - ('PutHi', ctypes.c_uint32), - ('Ignored01', ctypes.c_uint32 * 2), - ('TopLevelGet', ctypes.c_uint32), - ('TopLevelGetHi', ctypes.c_uint32), - ('GetHi', ctypes.c_uint32), - ('Ignored02', ctypes.c_uint32 * 7), - ('Ignored03', ctypes.c_uint32), - ('Ignored04', ctypes.c_uint32 * 1), - ('GPGet', ctypes.c_uint32), - ('GPPut', ctypes.c_uint32), - ('Ignored05', ctypes.c_uint32 * 92), + ('Ignored00', (NvU32 * 16)), + ('Put', NvU32), + ('Get', NvU32), + ('Reference', NvU32), + ('PutHi', NvU32), + ('Ignored01', (NvU32 * 2)), + ('TopLevelGet', NvU32), + ('TopLevelGetHi', NvU32), + ('GetHi', NvU32), + ('Ignored02', (NvU32 * 7)), + ('Ignored03', NvU32), + ('Ignored04', (NvU32 * 1)), + ('GPGet', NvU32), + ('GPPut', NvU32), + ('Ignored05', (NvU32 * 92)), ] - -Nvc86fControl = struct_Nvc86fControl_struct -HopperAControlGPFifo = struct_Nvc86fControl_struct -__gb100_clc96f_h__ = True # macro -BLACKWELL_CHANNEL_GPFIFO_A = (0x0000c96f) # macro -NVC96F_SET_OBJECT = (0x00000000) # macro -NVC96F_SEM_ADDR_LO = (0x0000005c) # macro -# NVC96F_SEM_ADDR_LO_OFFSET = 31 : 2 # macro -NVC96F_SEM_ADDR_HI = (0x00000060) # macro -# NVC96F_SEM_ADDR_HI_OFFSET = 24 : 0 # macro -NVC96F_SEM_PAYLOAD_LO = (0x00000064) # macro -NVC96F_SEM_PAYLOAD_HI = (0x00000068) # macro -NVC96F_SEM_EXECUTE = (0x0000006c) # macro -# NVC96F_SEM_EXECUTE_OPERATION = 2 : 0 # macro -NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 # macro -NVC96F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 # macro -# NVC96F_SEM_EXECUTE_RELEASE_WFI = 20 : 20 # macro -NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 # macro -# NVC96F_SEM_EXECUTE_PAYLOAD_SIZE = 24 : 24 # macro -NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 # macro -NVC96F_GP_ENTRY__SIZE = 8 # macro -# NVC96F_GP_ENTRY0_FETCH = 0 : 0 # macro -NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 # macro -NVC96F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 # macro -# NVC96F_GP_ENTRY0_GET = 31 : 2 # macro -# NVC96F_GP_ENTRY0_OPERAND = 31 : 0 # macro -# NVC96F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND = 24 : 8 # macro -# NVC96F_GP_ENTRY1_GET_HI = 7 : 0 # macro -# NVC96F_GP_ENTRY1_LEVEL = 9 : 9 # macro -NVC96F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 # macro -NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 # macro -# NVC96F_GP_ENTRY1_LENGTH = 30 : 10 # macro -# NVC96F_GP_ENTRY1_SYNC = 31 : 31 # macro -NVC96F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 # macro -NVC96F_GP_ENTRY1_SYNC_WAIT = 0x00000001 # macro -# NVC96F_GP_ENTRY1_OPCODE = 7 : 0 # macro -NVC96F_GP_ENTRY1_OPCODE_NOP = 0x00000000 # macro -NVC96F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 # macro -NVC96F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 # macro -NVC96F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 # macro -NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 # macro -class struct_Nvc96fControl_struct(Structure): - pass - -struct_Nvc96fControl_struct._pack_ = 1 # source:False +class volatile_struct_Nvc86fControl_struct(Struct): pass +Nvc86fControl = volatile_struct_Nvc86fControl_struct +volatile_struct_Nvc86fControl_struct._fields_ = [ + ('Ignored00', (NvU32 * 16)), + ('Put', NvU32), + ('Get', NvU32), + ('Reference', NvU32), + ('PutHi', NvU32), + ('Ignored01', (NvU32 * 2)), + ('TopLevelGet', NvU32), + ('TopLevelGetHi', NvU32), + ('GetHi', NvU32), + ('Ignored02', (NvU32 * 7)), + ('Ignored03', NvU32), + ('Ignored04', (NvU32 * 1)), + ('GPGet', NvU32), + ('GPPut', NvU32), + ('Ignored05', (NvU32 * 92)), +] +HopperAControlGPFifo = volatile_struct_Nvc86fControl_struct +class struct_Nvc96fControl_struct(Struct): pass struct_Nvc96fControl_struct._fields_ = [ - ('Ignored00', ctypes.c_uint32 * 35), - ('GPPut', ctypes.c_uint32), - ('Ignored01', ctypes.c_uint32 * 92), + ('Ignored00', (NvU32 * 35)), + ('GPPut', NvU32), + ('Ignored01', (NvU32 * 92)), ] - -Nvc96fControl = struct_Nvc96fControl_struct -BlackwellAControlGPFifo = struct_Nvc96fControl_struct -_clc761_h_ = True # macro -BLACKWELL_USERMODE_A = (0x0000c761) # macro -GT200_DEBUGGER = (0x000083de) # macro -NV83DE_ALLOC_PARAMETERS_MESSAGE_ID = (0x83de) # macro -class struct_NV83DE_ALLOC_PARAMETERS(Structure): - pass - -struct_NV83DE_ALLOC_PARAMETERS._pack_ = 1 # source:False +class volatile_struct_Nvc96fControl_struct(Struct): pass +Nvc96fControl = volatile_struct_Nvc96fControl_struct +volatile_struct_Nvc96fControl_struct._fields_ = [ + ('Ignored00', (NvU32 * 35)), + ('GPPut', NvU32), + ('Ignored01', (NvU32 * 92)), +] +BlackwellAControlGPFifo = volatile_struct_Nvc96fControl_struct +class struct_NV83DE_ALLOC_PARAMETERS(Struct): pass struct_NV83DE_ALLOC_PARAMETERS._fields_ = [ - ('hDebuggerClient_Obsolete', ctypes.c_uint32), - ('hAppClient', ctypes.c_uint32), - ('hClass3dObject', ctypes.c_uint32), + ('hDebuggerClient_Obsolete', NvHandle), + ('hAppClient', NvHandle), + ('hClass3dObject', NvHandle), ] - NV83DE_ALLOC_PARAMETERS = struct_NV83DE_ALLOC_PARAMETERS -NV1_ROOT = (0x00000000) # macro -NV01_ROOT_NON_PRIV = (0x00000001) # macro -NV1_ROOT_NON_PRIV = (0x00000001) # macro -NV01_ROOT_CLIENT = (0x00000041) # macro -FABRIC_MANAGER_SESSION = (0x0000000f) # macro -NV0020_GPU_MANAGEMENT = (0x00000020) # macro -NV2081_BINAPI = (0x00002081) # macro -NV2082_BINAPI_PRIVILEGED = (0x00002082) # macro -NV20_SUBDEVICE_DIAG = (0x0000208f) # macro -NV01_CONTEXT_DMA = (0x00000002) # macro -NV01_MEMORY_SYSTEM = (0x0000003e) # macro -NV1_MEMORY_SYSTEM = (0x0000003e) # macro -NV01_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) # macro -NV1_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) # macro -NV01_MEMORY_PRIVILEGED = (0x0000003f) # macro -NV1_MEMORY_PRIVILEGED = (0x0000003f) # macro -NV01_MEMORY_LOCAL_USER = (0x00000040) # macro -NV1_MEMORY_LOCAL_USER = (0x00000040) # macro -NV01_MEMORY_USER = (0x00000040) # macro -NV1_MEMORY_USER = (0x00000040) # macro -NV_MEMORY_EXTENDED_USER = (0x00000042) # macro -NV01_MEMORY_VIRTUAL = (0x00000070) # macro -NV01_MEMORY_SYSTEM_DYNAMIC = (0x00000070) # macro -NV1_MEMORY_SYSTEM_DYNAMIC = (0x00000070) # macro -NV_MEMORY_MAPPER = (0x000000fe) # macro -NV01_MEMORY_LOCAL_PHYSICAL = (0x000000c2) # macro -NV01_MEMORY_SYNCPOINT = (0x000000c3) # macro -NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = (0x00000071) # macro -NV01_MEMORY_DEVICELESS = (0x000090ce) # macro -NV01_MEMORY_FRAMEBUFFER_CONSOLE = (0x00000076) # macro -NV01_MEMORY_HW_RESOURCES = (0x000000b1) # macro -NV01_MEMORY_LIST_SYSTEM = (0x00000081) # macro -NV01_MEMORY_LIST_FBMEM = (0x00000082) # macro -NV01_MEMORY_LIST_OBJECT = (0x00000083) # macro -NV_IMEX_SESSION = (0x000000f1) # macro -NV01_MEMORY_FLA = (0x000000f3) # macro -NV_MEMORY_EXPORT = (0x000000e0) # macro -NV_CE_UTILS = (0x00000050) # macro -NV_MEMORY_FABRIC = (0x000000f8) # macro -NV_MEMORY_FABRIC_IMPORT_V2 = (0x000000f9) # macro -NV_MEMORY_FABRIC_IMPORTED_REF = (0x000000fb) # macro -FABRIC_VASPACE_A = (0x000000fc) # macro -NV_MEMORY_MULTICAST_FABRIC = (0x000000fd) # macro -IO_VASPACE_A = (0x000000f2) # macro -NV01_NULL = (0x00000030) # macro -NV1_NULL = (0x00000030) # macro -NV01_EVENT = (0x00000005) # macro -NV1_EVENT = (0x00000005) # macro -NV01_EVENT_KERNEL_CALLBACK = (0x00000078) # macro -NV1_EVENT_KERNEL_CALLBACK = (0x00000078) # macro -NV01_EVENT_OS_EVENT = (0x00000079) # macro -NV1_EVENT_OS_EVENT = (0x00000079) # macro -NV01_EVENT_WIN32_EVENT = (0x00000079) # macro -NV1_EVENT_WIN32_EVENT = (0x00000079) # macro -NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007E) # macro -NV1_EVENT_KERNEL_CALLBACK_EX = (0x0000007e) # macro -NV01_TIMER = (0x00000004) # macro -NV1_TIMER = (0x00000004) # macro -KERNEL_GRAPHICS_CONTEXT = (0x00000090) # macro -LOCK_STRESS_OBJECT = (0x00000100) # macro -NV50_CHANNEL_GPFIFO = (0x0000506f) # macro -GF100_CHANNEL_GPFIFO = (0x0000906f) # macro -KEPLER_CHANNEL_GPFIFO_A = (0x0000a06f) # macro -UVM_CHANNEL_RETAINER = (0x0000c574) # macro -KEPLER_CHANNEL_GPFIFO_B = (0x0000a16f) # macro -MAXWELL_CHANNEL_GPFIFO_A = (0x0000b06f) # macro -PASCAL_CHANNEL_GPFIFO_A = (0x0000c06f) # macro -VOLTA_CHANNEL_GPFIFO_A = (0x0000c36f) # macro -TURING_CHANNEL_GPFIFO_A = (0x0000c46f) # macro -BLACKWELL_CHANNEL_GPFIFO_B = (0x0000ca6f) # macro -NV04_SOFTWARE_TEST = (0x0000007d) # macro -NV4_SOFTWARE_TEST = (0x0000007d) # macro -NV30_GSYNC = (0x000030f1) # macro -VOLTA_USERMODE_A = (0x0000c361) # macro -TURING_USERMODE_A = (0x0000c461) # macro -AMPERE_USERMODE_A = (0x0000c561) # macro -HOPPER_USERMODE_A = (0x0000c661) # macro -NVC371_DISP_SF_USER = (0x0000c371) # macro -NVC372_DISPLAY_SW = (0x0000c372) # macro -NVC573_DISP_CAPABILITIES = (0x0000c573) # macro -NVC673_DISP_CAPABILITIES = (0x0000c673) # macro -NVC773_DISP_CAPABILITIES = (0x0000c773) # macro -NVC973_DISP_CAPABILITIES = (0x0000c973) # macro -NVCA73_DISP_CAPABILITIES = (0x0000ca73) # macro -NV04_DISPLAY_COMMON = (0x00000073) # macro -NV50_DEFERRED_API_CLASS = (0x00005080) # macro -MPS_COMPUTE = (0x0000900e) # macro -NVC570_DISPLAY = (0x0000c570) # macro -NVC57A_CURSOR_IMM_CHANNEL_PIO = (0x0000c57a) # macro -NVC57B_WINDOW_IMM_CHANNEL_DMA = (0x0000c57b) # macro -NVC57D_CORE_CHANNEL_DMA = (0x0000c57d) # macro -NVC57E_WINDOW_CHANNEL_DMA = (0x0000c57e) # macro -NVC670_DISPLAY = (0x0000c670) # macro -NVC671_DISP_SF_USER = (0x0000c671) # macro -NVC67A_CURSOR_IMM_CHANNEL_PIO = (0x0000c67a) # macro -NVC67B_WINDOW_IMM_CHANNEL_DMA = (0x0000c67b) # macro -NVC67D_CORE_CHANNEL_DMA = (0x0000c67d) # macro -NVC67E_WINDOW_CHANNEL_DMA = (0x0000c67e) # macro -NVC77F_ANY_CHANNEL_DMA = (0x0000c77f) # macro -NVC770_DISPLAY = (0x0000c770) # macro -NVC771_DISP_SF_USER = (0x0000c771) # macro -NVC77D_CORE_CHANNEL_DMA = (0x0000c77d) # macro -NVC970_DISPLAY = (0x0000c970) # macro -NVC971_DISP_SF_USER = (0x0000c971) # macro -NVC97A_CURSOR_IMM_CHANNEL_PIO = (0x0000c97a) # macro -NVC97B_WINDOW_IMM_CHANNEL_DMA = (0x0000c97b) # macro -NVC97D_CORE_CHANNEL_DMA = (0x0000c97d) # macro -NVC97E_WINDOW_CHANNEL_DMA = (0x0000c97e) # macro -NVCA70_DISPLAY = (0x0000ca70) # macro -NVCA71_DISP_SF_USER = (0x0000ca71) # macro -NVCA7A_CURSOR_IMM_CHANNEL_PIO = (0x0000ca7a) # macro -NVCA7B_WINDOW_IMM_CHANNEL_DMA = (0x0000ca7b) # macro -NVCA7D_CORE_CHANNEL_DMA = (0x0000ca7d) # macro -NVCA7E_WINDOW_CHANNEL_DMA = (0x0000ca7e) # macro -NV9010_VBLANK_CALLBACK = (0x00009010) # macro -GF100_PROFILER = (0x000090cc) # macro -MAXWELL_PROFILER = (0x0000b0cc) # macro -MAXWELL_PROFILER_CONTEXT = (0x0000b1cc) # macro -MAXWELL_PROFILER_DEVICE = (0x0000b2cc) # macro -GF100_SUBDEVICE_MASTER = (0x000090e6) # macro -GF100_SUBDEVICE_INFOROM = (0x000090e7) # macro -GF100_ZBC_CLEAR = (0x00009096) # macro -GF100_DISP_SW = (0x00009072) # macro -GF100_TIMED_SEMAPHORE_SW = (0x00009074) # macro -G84_PERFBUFFER = (0x0000844c) # macro -NV50_MEMORY_VIRTUAL = (0x000050a0) # macro -NV50_P2P = (0x0000503b) # macro -NV50_THIRD_PARTY_P2P = (0x0000503c) # macro -FERMI_TWOD_A = (0x0000902d) # macro -FERMI_VASPACE_A = (0x000090f1) # macro -HOPPER_SEC2_WORK_LAUNCH_A = (0x0000cba2) # macro -GF100_HDACODEC = (0x000090ec) # macro -NVB8B0_VIDEO_DECODER = (0x0000b8b0) # macro -NVC4B0_VIDEO_DECODER = (0x0000c4b0) # macro -NVC6B0_VIDEO_DECODER = (0x0000c6b0) # macro -NVC7B0_VIDEO_DECODER = (0x0000c7b0) # macro -NVC9B0_VIDEO_DECODER = (0x0000c9b0) # macro -NVCDB0_VIDEO_DECODER = (0x0000cdb0) # macro -NVCFB0_VIDEO_DECODER = (0x0000cfb0) # macro -NVC4B7_VIDEO_ENCODER = (0x0000c4b7) # macro -NVB4B7_VIDEO_ENCODER = (0x0000b4b7) # macro -NVC7B7_VIDEO_ENCODER = (0x0000c7b7) # macro -NVC9B7_VIDEO_ENCODER = (0x0000c9b7) # macro -NVCFB7_VIDEO_ENCODER = (0x0000cfb7) # macro -NVB8D1_VIDEO_NVJPG = (0x0000b8d1) # macro -NVC4D1_VIDEO_NVJPG = (0x0000c4d1) # macro -NVC9D1_VIDEO_NVJPG = (0x0000c9d1) # macro -NVCDD1_VIDEO_NVJPG = (0x0000cdd1) # macro -NVCFD1_VIDEO_NVJPG = (0x0000cfd1) # macro -NVB8FA_VIDEO_OFA = (0x0000b8fa) # macro -NVC6FA_VIDEO_OFA = (0x0000c6fa) # macro -NVC7FA_VIDEO_OFA = (0x0000c7fa) # macro -NVC9FA_VIDEO_OFA = (0x0000c9fa) # macro -NVCDFA_VIDEO_OFA = (0x0000cdfa) # macro -NVCFFA_VIDEO_OFA = (0x0000cffa) # macro -KEPLER_INLINE_TO_MEMORY_B = (0x0000a140) # macro -FERMI_CONTEXT_SHARE_A = (0x00009067) # macro -KEPLER_CHANNEL_GROUP_A = (0x0000a06c) # macro -PASCAL_DMA_COPY_A = (0x0000c0b5) # macro -TURING_DMA_COPY_A = (0x0000c5b5) # macro -AMPERE_DMA_COPY_A = (0x0000C6B5) # macro -AMPERE_DMA_COPY_B = (0x0000c7b5) # macro -HOPPER_DMA_COPY_A = (0x0000c8b5) # macro -BLACKWELL_DMA_COPY_A = (0x0000C9B5) # macro -BLACKWELL_DMA_COPY_B = (0x0000cab5) # macro -MAXWELL_DMA_COPY_A = (0x0000b0b5) # macro -ACCESS_COUNTER_NOTIFY_BUFFER = (0x0000c365) # macro -MMU_FAULT_BUFFER = (0x0000c369) # macro -MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c763) # macro -TURING_A = (0x0000c597) # macro -TURING_COMPUTE_A = (0x0000c5c0) # macro -AMPERE_A = (0x0000c697) # macro -AMPERE_COMPUTE_A = 0xC6C0 # macro -AMPERE_B = (0x0000c797) # macro -AMPERE_COMPUTE_B = (0x0000c7c0) # macro -ADA_A = (0x0000c997) # macro -ADA_COMPUTE_A = (0x0000c9c0) # macro -AMPERE_SMC_PARTITION_REF = (0x0000c637) # macro -AMPERE_SMC_EXEC_PARTITION_REF = (0x0000c638) # macro -AMPERE_SMC_CONFIG_SESSION = (0x0000c639) # macro -NV0092_RG_LINE_CALLBACK = (0x00000092) # macro -AMPERE_SMC_MONITOR_SESSION = (0x0000c640) # macro -HOPPER_A = (0x0000cb97) # macro -HOPPER_COMPUTE_A = (0x0000cbc0) # macro -BLACKWELL_A = (0x0000cd97) # macro -BLACKWELL_COMPUTE_A = 0xCDC0 # macro -BLACKWELL_B = (0x0000ce97) # macro -BLACKWELL_COMPUTE_B = (0x0000cec0) # macro -BLACKWELL_INLINE_TO_MEMORY_A = (0x0000cd40) # macro -NV40_DEBUG_BUFFER = (0x000000db) # macro -RM_USER_SHARED_DATA = (0x000000de) # macro -NV40_I2C = (0x0000402c) # macro -KEPLER_DEVICE_VGPU = (0x0000a080) # macro -NVA081_VGPU_CONFIG = (0x0000a081) # macro -NVA084_KERNEL_HOST_VGPU_DEVICE = (0x0000a084) # macro -NV0060_SYNC_GPU_BOOST = (0x00000060) # macro -GP100_UVM_SW = (0x0000c076) # macro -NVENC_SW_SESSION = (0x0000a0bc) # macro -NV_EVENT_BUFFER = (0x000090cd) # macro -NVFBC_SW_SESSION = (0x0000a0bd) # macro -NV_CONFIDENTIAL_COMPUTE = (0x0000cb33) # macro -NV_COUNTER_COLLECTION_UNIT = (0x0000cbca) # macro -NV_SEMAPHORE_SURFACE = (0x000000da) # macro -_cl_ampere_compute_a_h_ = True # macro -NVC6C0_SET_OBJECT = 0x0000 # macro -# NVC6C0_SET_OBJECT_CLASS_ID = 15 : 0 # macro -# NVC6C0_SET_OBJECT_ENGINE_ID = 20 : 16 # macro -NVC6C0_NO_OPERATION = 0x0100 # macro -# NVC6C0_NO_OPERATION_V = 31 : 0 # macro -NVC6C0_SET_NOTIFY_A = 0x0104 # macro -# NVC6C0_SET_NOTIFY_A_ADDRESS_UPPER = 7 : 0 # macro -NVC6C0_SET_NOTIFY_B = 0x0108 # macro -# NVC6C0_SET_NOTIFY_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_NOTIFY = 0x010c # macro -# NVC6C0_NOTIFY_TYPE = 31 : 0 # macro -NVC6C0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000 # macro -NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001 # macro -NVC6C0_WAIT_FOR_IDLE = 0x0110 # macro -# NVC6C0_WAIT_FOR_IDLE_V = 31 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130 # macro -# NVC6C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134 # macro -# NVC6C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138 # macro -# NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 # macro -NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 # macro -NVC6C0_SEND_GO_IDLE = 0x013c # macro -# NVC6C0_SEND_GO_IDLE_V = 31 : 0 # macro -NVC6C0_PM_TRIGGER = 0x0140 # macro -# NVC6C0_PM_TRIGGER_V = 31 : 0 # macro -NVC6C0_PM_TRIGGER_WFI = 0x0144 # macro -# NVC6C0_PM_TRIGGER_WFI_V = 31 : 0 # macro -NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148 # macro -# NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN_V = 31 : 0 # macro -NVC6C0_FE_ATOMIC_SEQUENCE_END = 0x014c # macro -# NVC6C0_FE_ATOMIC_SEQUENCE_END_V = 31 : 0 # macro -NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150 # macro -# NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER_V = 31 : 0 # macro -NVC6C0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154 # macro -# NVC6C0_SET_INSTRUMENTATION_METHOD_DATA_V = 31 : 0 # macro -NVC6C0_LINE_LENGTH_IN = 0x0180 # macro -# NVC6C0_LINE_LENGTH_IN_VALUE = 31 : 0 # macro -NVC6C0_LINE_COUNT = 0x0184 # macro -# NVC6C0_LINE_COUNT_VALUE = 31 : 0 # macro -NVC6C0_OFFSET_OUT_UPPER = 0x0188 # macro -# NVC6C0_OFFSET_OUT_UPPER_VALUE = 16 : 0 # macro -NVC6C0_OFFSET_OUT = 0x018c # macro -# NVC6C0_OFFSET_OUT_VALUE = 31 : 0 # macro -NVC6C0_PITCH_OUT = 0x0190 # macro -# NVC6C0_PITCH_OUT_VALUE = 31 : 0 # macro -NVC6C0_SET_DST_BLOCK_SIZE = 0x0194 # macro -# NVC6C0_SET_DST_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = 0x00000000 # macro -# NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = 0x00000000 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = 0x00000001 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = 0x00000002 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = 0x00000003 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = 0x00000004 # macro -NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = 0x00000005 # macro -# NVC6C0_SET_DST_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = 0x00000000 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = 0x00000001 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = 0x00000002 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = 0x00000003 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = 0x00000004 # macro -NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = 0x00000005 # macro -NVC6C0_SET_DST_WIDTH = 0x0198 # macro -# NVC6C0_SET_DST_WIDTH_V = 31 : 0 # macro -NVC6C0_SET_DST_HEIGHT = 0x019c # macro -# NVC6C0_SET_DST_HEIGHT_V = 31 : 0 # macro -NVC6C0_SET_DST_DEPTH = 0x01a0 # macro -# NVC6C0_SET_DST_DEPTH_V = 31 : 0 # macro -NVC6C0_SET_DST_LAYER = 0x01a4 # macro -# NVC6C0_SET_DST_LAYER_V = 31 : 0 # macro -NVC6C0_SET_DST_ORIGIN_BYTES_X = 0x01a8 # macro -# NVC6C0_SET_DST_ORIGIN_BYTES_X_V = 20 : 0 # macro -NVC6C0_SET_DST_ORIGIN_SAMPLES_Y = 0x01ac # macro -# NVC6C0_SET_DST_ORIGIN_SAMPLES_Y_V = 16 : 0 # macro -NVC6C0_LAUNCH_DMA = 0x01b0 # macro -# NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT = 0 : 0 # macro -NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_COMPLETION_TYPE = 5 : 4 # macro -NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001 # macro -NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002 # macro -# NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE = 9 : 8 # macro -NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE = 12 : 12 # macro -NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE = 1 : 1 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_REDUCTION_OP = 15 : 13 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007 # macro -# NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT = 3 : 2 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -# NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE = 6 : 6 # macro -NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000 # macro -NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001 # macro -NVC6C0_LOAD_INLINE_DATA = 0x01b4 # macro -# NVC6C0_LOAD_INLINE_DATA_V = 31 : 0 # macro -NVC6C0_SET_I2M_SEMAPHORE_A = 0x01dc # macro -# NVC6C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_I2M_SEMAPHORE_B = 0x01e0 # macro -# NVC6C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_I2M_SEMAPHORE_C = 0x01e4 # macro -# NVC6C0_SET_I2M_SEMAPHORE_C_PAYLOAD = 31 : 0 # macro -NVC6C0_SET_SM_SCG_CONTROL = 0x01e8 # macro -# NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS = 0 : 0 # macro -NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000 # macro -NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001 # macro -NVC6C0_SET_I2M_SPARE_NOOP00 = 0x01f0 # macro -# NVC6C0_SET_I2M_SPARE_NOOP00_V = 31 : 0 # macro -NVC6C0_SET_I2M_SPARE_NOOP01 = 0x01f4 # macro -# NVC6C0_SET_I2M_SPARE_NOOP01_V = 31 : 0 # macro -NVC6C0_SET_I2M_SPARE_NOOP02 = 0x01f8 # macro -# NVC6C0_SET_I2M_SPARE_NOOP02_V = 31 : 0 # macro -NVC6C0_SET_I2M_SPARE_NOOP03 = 0x01fc # macro -# NVC6C0_SET_I2M_SPARE_NOOP03_V = 31 : 0 # macro -NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200 # macro -# NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER = 7 : 0 # macro -NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204 # macro -# NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208 # macro -# NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE = 31 : 0 # macro -NVC6C0_PERFMON_TRANSFER = 0x0210 # macro -# NVC6C0_PERFMON_TRANSFER_V = 31 : 0 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A = 0x0214 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER = 7 : 0 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B = 0x0218 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES = 0x021c # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION = 0 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_DATA = 4 : 4 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT = 12 : 12 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS = 1 : 1 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA = 2 : 2 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001 # macro -NVC6C0_SET_RESERVED_SW_METHOD00 = 0x0220 # macro -# NVC6C0_SET_RESERVED_SW_METHOD00_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD01 = 0x0224 # macro -# NVC6C0_SET_RESERVED_SW_METHOD01_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD02 = 0x0228 # macro -# NVC6C0_SET_RESERVED_SW_METHOD02_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD03 = 0x022c # macro -# NVC6C0_SET_RESERVED_SW_METHOD03_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD04 = 0x0230 # macro -# NVC6C0_SET_RESERVED_SW_METHOD04_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD05 = 0x0234 # macro -# NVC6C0_SET_RESERVED_SW_METHOD05_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD06 = 0x0238 # macro -# NVC6C0_SET_RESERVED_SW_METHOD06_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD07 = 0x023c # macro -# NVC6C0_SET_RESERVED_SW_METHOD07_V = 31 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG = 25 : 4 # macro -NVC6C0_SET_CWD_REF_COUNTER = 0x0248 # macro -# NVC6C0_SET_CWD_REF_COUNTER_SELECT = 5 : 0 # macro -# NVC6C0_SET_CWD_REF_COUNTER_VALUE = 23 : 8 # macro -NVC6C0_SET_RESERVED_SW_METHOD08 = 0x024c # macro -# NVC6C0_SET_RESERVED_SW_METHOD08_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD09 = 0x0250 # macro -# NVC6C0_SET_RESERVED_SW_METHOD09_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD10 = 0x0254 # macro -# NVC6C0_SET_RESERVED_SW_METHOD10_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD11 = 0x0258 # macro -# NVC6C0_SET_RESERVED_SW_METHOD11_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD12 = 0x025c # macro -# NVC6C0_SET_RESERVED_SW_METHOD12_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD13 = 0x0260 # macro -# NVC6C0_SET_RESERVED_SW_METHOD13_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD14 = 0x0264 # macro -# NVC6C0_SET_RESERVED_SW_METHOD14_V = 31 : 0 # macro -NVC6C0_SET_RESERVED_SW_METHOD15 = 0x0268 # macro -# NVC6C0_SET_RESERVED_SW_METHOD15_V = 31 : 0 # macro -NVC6C0_SET_SCG_CONTROL = 0x0270 # macro -# NVC6C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT = 8 : 0 # macro -# NVC6C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT = 20 : 12 # macro -# NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE = 24 : 24 # macro -NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = 0x00000000 # macro -NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = 0x00000001 # macro -NVC6C0_SET_COMPUTE_CLASS_VERSION = 0x0280 # macro -# NVC6C0_SET_COMPUTE_CLASS_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_CHECK_COMPUTE_CLASS_VERSION = 0x0284 # macro -# NVC6C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_SET_QMD_VERSION = 0x0288 # macro -# NVC6C0_SET_QMD_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_SET_QMD_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_CHECK_QMD_VERSION = 0x0290 # macro -# NVC6C0_CHECK_QMD_VERSION_CURRENT = 15 : 0 # macro -# NVC6C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED = 31 : 16 # macro -NVC6C0_INVALIDATE_SKED_CACHES = 0x0298 # macro -# NVC6C0_INVALIDATE_SKED_CACHES_V = 0 : 0 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL = 0x029c # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK = 7 : 0 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE = 8 : 8 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE = 12 : 12 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE = 16 : 16 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE = 20 : 20 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE = 24 : 24 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0 # macro -# NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4 # macro -# NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS = 31 : 0 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL = 0x02a8 # macro -# NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE = 0 : 0 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE = 0x00000000 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE = 0x00000001 # macro -# NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE = 1 : 1 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE = 0x00000000 # macro -NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE = 0x00000001 # macro -NVC6C0_SET_CWD_SLOT_COUNT = 0x02b0 # macro -# NVC6C0_SET_CWD_SLOT_COUNT_V = 7 : 0 # macro -NVC6C0_SEND_PCAS_A = 0x02b4 # macro -# NVC6C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 = 31 : 0 # macro -NVC6C0_SEND_PCAS_B = 0x02b8 # macro -# NVC6C0_SEND_PCAS_B_FROM = 23 : 0 # macro -# NVC6C0_SEND_PCAS_B_DELTA = 31 : 24 # macro -NVC6C0_SEND_SIGNALING_PCAS_B = 0x02bc # macro -# NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE = 0 : 0 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001 # macro -# NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE = 1 : 1 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000 # macro -NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B = 0x02c0 # macro -# NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION = 3 : 0 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009 # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A # macro -NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B # macro -NVC6C0_SET_SKED_CACHE_CONTROL = 0x02cc # macro -# NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID = 0 : 0 # macro -NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000 # macro -NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER = 7 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER = 31 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT = 8 : 0 # macro -NVC6C0_SET_SPA_VERSION = 0x0310 # macro -# NVC6C0_SET_SPA_VERSION_MINOR = 7 : 0 # macro -# NVC6C0_SET_SPA_VERSION_MAJOR = 15 : 8 # macro -NVC6C0_SET_INLINE_QMD_ADDRESS_A = 0x0318 # macro -# NVC6C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER = 31 : 0 # macro -NVC6C0_SET_INLINE_QMD_ADDRESS_B = 0x031c # macro -# NVC6C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER = 31 : 0 # macro -def NVC6C0_LOAD_INLINE_QMD_DATA(i): # macro - return (0x0320+(i)*4) -# NVC6C0_LOAD_INLINE_QMD_DATA_V = 31 : 0 # macro -NVC6C0_SET_FALCON00 = 0x0500 # macro -# NVC6C0_SET_FALCON00_V = 31 : 0 # macro -NVC6C0_SET_FALCON01 = 0x0504 # macro -# NVC6C0_SET_FALCON01_V = 31 : 0 # macro -NVC6C0_SET_FALCON02 = 0x0508 # macro -# NVC6C0_SET_FALCON02_V = 31 : 0 # macro -NVC6C0_SET_FALCON03 = 0x050c # macro -# NVC6C0_SET_FALCON03_V = 31 : 0 # macro -NVC6C0_SET_FALCON04 = 0x0510 # macro -# NVC6C0_SET_FALCON04_V = 31 : 0 # macro -NVC6C0_SET_FALCON05 = 0x0514 # macro -# NVC6C0_SET_FALCON05_V = 31 : 0 # macro -NVC6C0_SET_FALCON06 = 0x0518 # macro -# NVC6C0_SET_FALCON06_V = 31 : 0 # macro -NVC6C0_SET_FALCON07 = 0x051c # macro -# NVC6C0_SET_FALCON07_V = 31 : 0 # macro -NVC6C0_SET_FALCON08 = 0x0520 # macro -# NVC6C0_SET_FALCON08_V = 31 : 0 # macro -NVC6C0_SET_FALCON09 = 0x0524 # macro -# NVC6C0_SET_FALCON09_V = 31 : 0 # macro -NVC6C0_SET_FALCON10 = 0x0528 # macro -# NVC6C0_SET_FALCON10_V = 31 : 0 # macro -NVC6C0_SET_FALCON11 = 0x052c # macro -# NVC6C0_SET_FALCON11_V = 31 : 0 # macro -NVC6C0_SET_FALCON12 = 0x0530 # macro -# NVC6C0_SET_FALCON12_V = 31 : 0 # macro -NVC6C0_SET_FALCON13 = 0x0534 # macro -# NVC6C0_SET_FALCON13_V = 31 : 0 # macro -NVC6C0_SET_FALCON14 = 0x0538 # macro -# NVC6C0_SET_FALCON14_V = 31 : 0 # macro -NVC6C0_SET_FALCON15 = 0x053c # macro -# NVC6C0_SET_FALCON15_V = 31 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_A = 0x0790 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_B = 0x0794 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4 # macro -# NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS = 31 : 0 # macro -NVC6C0_SET_SHADER_CACHE_CONTROL = 0x0d94 # macro -# NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE = 0 : 0 # macro -NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001 # macro -def NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i): # macro - return (0x0da0+(i)*4) -# NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V = 31 : 0 # macro -NVC6C0_SET_SM_TIMEOUT_INTERVAL = 0x0de4 # macro -# NVC6C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT = 5 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG = 25 : 4 # macro -NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8 # macro -# NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL = 0 : 0 # macro -NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000 # macro -NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE = 0x1330 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_TAG = 25 : 4 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG = 25 : 4 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG = 25 : 4 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES = 0 : 0 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000 # macro -NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG = 25 : 4 # macro -NVC6C0_SET_SHADER_EXCEPTIONS = 0x1528 # macro -# NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE = 0 : 0 # macro -NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_A = 0x1550 # macro -# NVC6C0_SET_RENDER_ENABLE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_B = 0x1554 # macro -# NVC6C0_SET_RENDER_ENABLE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_C = 0x1558 # macro -# NVC6C0_SET_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 # macro -NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 # macro -NVC6C0_SET_TEX_SAMPLER_POOL_A = 0x155c # macro -# NVC6C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER = 16 : 0 # macro -NVC6C0_SET_TEX_SAMPLER_POOL_B = 0x1560 # macro -# NVC6C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_TEX_SAMPLER_POOL_C = 0x1564 # macro -# NVC6C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX = 19 : 0 # macro -NVC6C0_SET_TEX_HEADER_POOL_A = 0x1574 # macro -# NVC6C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER = 16 : 0 # macro -NVC6C0_SET_TEX_HEADER_POOL_B = 0x1578 # macro -# NVC6C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_TEX_HEADER_POOL_C = 0x157c # macro -# NVC6C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX = 21 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION = 0 : 0 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA = 4 : 4 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001 # macro -# NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT = 12 : 12 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000 # macro -NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE = 0x1944 # macro -# NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE = 1 : 0 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001 # macro -NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002 # macro -NVC6C0_PIPE_NOP = 0x1a2c # macro -# NVC6C0_PIPE_NOP_V = 31 : 0 # macro -NVC6C0_SET_SPARE00 = 0x1a30 # macro -# NVC6C0_SET_SPARE00_V = 31 : 0 # macro -NVC6C0_SET_SPARE01 = 0x1a34 # macro -# NVC6C0_SET_SPARE01_V = 31 : 0 # macro -NVC6C0_SET_SPARE02 = 0x1a38 # macro -# NVC6C0_SET_SPARE02_V = 31 : 0 # macro -NVC6C0_SET_SPARE03 = 0x1a3c # macro -# NVC6C0_SET_SPARE03_V = 31 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_A = 0x1b00 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER = 7 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_B = 0x1b04 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER = 31 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_C = 0x1b08 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_C_PAYLOAD = 31 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D = 0x1b0c # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION = 1 : 0 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE = 20 : 20 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE = 28 : 28 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE = 2 : 2 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE = 3 : 3 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP = 11 : 9 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT = 18 : 17 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 # macro -# NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP = 19 : 19 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000 # macro -NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001 # macro -NVC6C0_SET_TRAP_HANDLER_A = 0x25f8 # macro -# NVC6C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER = 16 : 0 # macro -NVC6C0_SET_TRAP_HANDLER_B = 0x25fc # macro -# NVC6C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER = 31 : 0 # macro -NVC6C0_SET_BINDLESS_TEXTURE = 0x2608 # macro -# NVC6C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT = 2 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i): # macro - return (0x32f4+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V = 31 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i): # macro - return (0x3314+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V = 31 : 0 # macro -NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334 # macro -# NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = 0 : 0 # macro -NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338 # macro -# NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V = 0 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i): # macro - return (0x333c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V = 31 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i): # macro - return (0x335c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V = 31 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i): # macro - return (0x337c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT = 7 : 0 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i): # macro - return (0x339c+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 = 1 : 0 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 = 4 : 2 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 = 6 : 5 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 = 9 : 7 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 = 11 : 10 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 = 14 : 12 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 = 16 : 15 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 = 19 : 17 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 = 21 : 20 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 = 24 : 22 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 = 26 : 25 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 = 29 : 27 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE = 31 : 30 # macro -def NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i): # macro - return (0x33bc+(i)*4) -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE = 0 : 0 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE = 2 : 1 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED = 3 : 3 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC = 19 : 4 # macro -NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK = 7 : 0 # macro -NVC6C0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0 # macro -# NVC6C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = 7 : 0 # macro -NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4 # macro -# NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK = 7 : 0 # macro -NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8 # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V = 31 : 0 # macro -NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec # macro -# NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V = 31 : 0 # macro -def NVC6C0_SET_MME_SHADOW_SCRATCH(i): # macro - return (0x3400+(i)*4) -# NVC6C0_SET_MME_SHADOW_SCRATCH_V = 31 : 0 # macro -__gb100_clcdc0_h__ = True # macro -_clc6b5_h_ = True # macro -NVC6B5_NOP = (0x00000100) # macro -# NVC6B5_NOP_PARAMETER = 31 : 0 # macro -NVC6B5_PM_TRIGGER = (0x00000140) # macro -# NVC6B5_PM_TRIGGER_V = 31 : 0 # macro -NVC6B5_SET_SEMAPHORE_A = (0x00000240) # macro -# NVC6B5_SET_SEMAPHORE_A_UPPER = 16 : 0 # macro -NVC6B5_SET_SEMAPHORE_B = (0x00000244) # macro -# NVC6B5_SET_SEMAPHORE_B_LOWER = 31 : 0 # macro -NVC6B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) # macro -# NVC6B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = 31 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_A = (0x00000254) # macro -# NVC6B5_SET_RENDER_ENABLE_A_UPPER = 7 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_B = (0x00000258) # macro -# NVC6B5_SET_RENDER_ENABLE_B_LOWER = 31 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_C = (0x0000025C) # macro -# NVC6B5_SET_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) # macro -NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) # macro -NVC6B5_SET_SRC_PHYS_MODE = (0x00000260) # macro -# NVC6B5_SET_SRC_PHYS_MODE_TARGET = 1 : 0 # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC6B5_SET_SRC_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC6B5_SET_SRC_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC6B5_SET_SRC_PHYS_MODE_FLA = 9 : 9 # macro -NVC6B5_SET_DST_PHYS_MODE = (0x00000264) # macro -# NVC6B5_SET_DST_PHYS_MODE_TARGET = 1 : 0 # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC6B5_SET_DST_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC6B5_SET_DST_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC6B5_SET_DST_PHYS_MODE_FLA = 9 : 9 # macro -NVC6B5_LAUNCH_DMA = (0x00000300) # macro -# NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = 1 : 0 # macro -NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) # macro -# NVC6B5_LAUNCH_DMA_FLUSH_ENABLE = 2 : 2 # macro -NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_FLUSH_TYPE = 25 : 25 # macro -NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE = 4 : 3 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) # macro -# NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE = 6 : 5 # macro -NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) # macro -# NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = 7 : 7 # macro -NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = 8 : 8 # macro -NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE = 9 : 9 # macro -NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_REMAP_ENABLE = 10 : 10 # macro -NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE = 11 : 11 # macro -NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SRC_TYPE = 12 : 12 # macro -NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_DST_TYPE = 13 : 13 # macro -NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = 17 : 14 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = 18 : 18 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = 19 : 19 # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_VPRMODE = 23 : 22 # macro -NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_RESERVED_START_OF_COPY = 24 : 24 # macro -# NVC6B5_LAUNCH_DMA_DISABLE_PLC = 26 : 26 # macro -NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) # macro -NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) # macro -# NVC6B5_LAUNCH_DMA_RESERVED_ERR_CODE = 31 : 28 # macro -NVC6B5_OFFSET_IN_UPPER = (0x00000400) # macro -# NVC6B5_OFFSET_IN_UPPER_UPPER = 16 : 0 # macro -NVC6B5_OFFSET_IN_LOWER = (0x00000404) # macro -# NVC6B5_OFFSET_IN_LOWER_VALUE = 31 : 0 # macro -NVC6B5_OFFSET_OUT_UPPER = (0x00000408) # macro -# NVC6B5_OFFSET_OUT_UPPER_UPPER = 16 : 0 # macro -NVC6B5_OFFSET_OUT_LOWER = (0x0000040C) # macro -# NVC6B5_OFFSET_OUT_LOWER_VALUE = 31 : 0 # macro -NVC6B5_PITCH_IN = (0x00000410) # macro -# NVC6B5_PITCH_IN_VALUE = 31 : 0 # macro -NVC6B5_PITCH_OUT = (0x00000414) # macro -# NVC6B5_PITCH_OUT_VALUE = 31 : 0 # macro -NVC6B5_LINE_LENGTH_IN = (0x00000418) # macro -# NVC6B5_LINE_LENGTH_IN_VALUE = 31 : 0 # macro -NVC6B5_LINE_COUNT = (0x0000041C) # macro -# NVC6B5_LINE_COUNT_VALUE = 31 : 0 # macro -NVC6B5_SET_REMAP_CONST_A = (0x00000700) # macro -# NVC6B5_SET_REMAP_CONST_A_V = 31 : 0 # macro -NVC6B5_SET_REMAP_CONST_B = (0x00000704) # macro -# NVC6B5_SET_REMAP_CONST_B_V = 31 : 0 # macro -NVC6B5_SET_REMAP_COMPONENTS = (0x00000708) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_X = 2 : 0 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_Y = 6 : 4 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_Z = 10 : 8 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_DST_W = 14 : 12 # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) # macro -NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) # macro -# NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = 17 : 16 # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) # macro -# NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = 21 : 20 # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) # macro -# NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = 25 : 24 # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) # macro -NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) # macro -NVC6B5_SET_DST_BLOCK_SIZE = (0x0000070C) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC6B5_SET_DST_WIDTH = (0x00000710) # macro -# NVC6B5_SET_DST_WIDTH_V = 31 : 0 # macro -NVC6B5_SET_DST_HEIGHT = (0x00000714) # macro -# NVC6B5_SET_DST_HEIGHT_V = 31 : 0 # macro -NVC6B5_SET_DST_DEPTH = (0x00000718) # macro -# NVC6B5_SET_DST_DEPTH_V = 31 : 0 # macro -NVC6B5_SET_DST_LAYER = (0x0000071C) # macro -# NVC6B5_SET_DST_LAYER_V = 31 : 0 # macro -NVC6B5_SET_DST_ORIGIN = (0x00000720) # macro -# NVC6B5_SET_DST_ORIGIN_X = 15 : 0 # macro -# NVC6B5_SET_DST_ORIGIN_Y = 31 : 16 # macro -NVC6B5_SET_SRC_BLOCK_SIZE = (0x00000728) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC6B5_SET_SRC_WIDTH = (0x0000072C) # macro -# NVC6B5_SET_SRC_WIDTH_V = 31 : 0 # macro -NVC6B5_SET_SRC_HEIGHT = (0x00000730) # macro -# NVC6B5_SET_SRC_HEIGHT_V = 31 : 0 # macro -NVC6B5_SET_SRC_DEPTH = (0x00000734) # macro -# NVC6B5_SET_SRC_DEPTH_V = 31 : 0 # macro -NVC6B5_SET_SRC_LAYER = (0x00000738) # macro -# NVC6B5_SET_SRC_LAYER_V = 31 : 0 # macro -NVC6B5_SET_SRC_ORIGIN = (0x0000073C) # macro -# NVC6B5_SET_SRC_ORIGIN_X = 15 : 0 # macro -# NVC6B5_SET_SRC_ORIGIN_Y = 31 : 16 # macro -NVC6B5_SRC_ORIGIN_X = (0x00000744) # macro -# NVC6B5_SRC_ORIGIN_X_VALUE = 31 : 0 # macro -NVC6B5_SRC_ORIGIN_Y = (0x00000748) # macro -# NVC6B5_SRC_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC6B5_DST_ORIGIN_X = (0x0000074C) # macro -# NVC6B5_DST_ORIGIN_X_VALUE = 31 : 0 # macro -NVC6B5_DST_ORIGIN_Y = (0x00000750) # macro -# NVC6B5_DST_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC6B5_PM_TRIGGER_END = (0x00001114) # macro -# NVC6B5_PM_TRIGGER_END_V = 31 : 0 # macro -_clc9b5_h_ = True # macro -NVC9B5_NOP = (0x00000100) # macro -# NVC9B5_NOP_PARAMETER = 31 : 0 # macro -NVC9B5_PM_TRIGGER = (0x00000140) # macro -# NVC9B5_PM_TRIGGER_V = 31 : 0 # macro -NVC9B5_SET_MONITORED_FENCE_TYPE = (0x0000021C) # macro -# NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE = 0 : 0 # macro -NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE = (0x00000000) # macro -NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT = (0x00000001) # macro -NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER = (0x00000220) # macro -# NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER = (0x00000224) # macro -# NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_SEMAPHORE_A = (0x00000240) # macro -# NVC9B5_SET_SEMAPHORE_A_UPPER = 24 : 0 # macro -NVC9B5_SET_SEMAPHORE_B = (0x00000244) # macro -# NVC9B5_SET_SEMAPHORE_B_LOWER = 31 : 0 # macro -NVC9B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) # macro -# NVC9B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD = 31 : 0 # macro -NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER = (0x0000024C) # macro -# NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD = 31 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_A = (0x00000254) # macro -# NVC9B5_SET_RENDER_ENABLE_A_UPPER = 24 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_B = (0x00000258) # macro -# NVC9B5_SET_RENDER_ENABLE_B_LOWER = 31 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_C = (0x0000025C) # macro -# NVC9B5_SET_RENDER_ENABLE_C_MODE = 2 : 0 # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) # macro -NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) # macro -NVC9B5_SET_SRC_PHYS_MODE = (0x00000260) # macro -# NVC9B5_SET_SRC_PHYS_MODE_TARGET = 1 : 0 # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_SRC_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC9B5_SET_SRC_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC9B5_SET_SRC_PHYS_MODE_FLA = 9 : 9 # macro -NVC9B5_SET_DST_PHYS_MODE = (0x00000264) # macro -# NVC9B5_SET_DST_PHYS_MODE_TARGET = 1 : 0 # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_DST_PHYS_MODE_BASIC_KIND = 5 : 2 # macro -# NVC9B5_SET_DST_PHYS_MODE_PEER_ID = 8 : 6 # macro -# NVC9B5_SET_DST_PHYS_MODE_FLA = 9 : 9 # macro -NVC9B5_LAUNCH_DMA = (0x00000300) # macro -# NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE = 1 : 0 # macro -NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) # macro -# NVC9B5_LAUNCH_DMA_FLUSH_ENABLE = 2 : 2 # macro -NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_FLUSH_TYPE = 25 : 25 # macro -NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE = 4 : 3 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) # macro -# NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE = 6 : 5 # macro -NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) # macro -# NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT = 7 : 7 # macro -NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT = 8 : 8 # macro -NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE = 9 : 9 # macro -NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_REMAP_ENABLE = 10 : 10 # macro -NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE = 11 : 11 # macro -NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SRC_TYPE = 12 : 12 # macro -NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_DST_TYPE = 13 : 13 # macro -NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION = 17 : 14 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA = (0x00000008) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB = (0x00000009) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN = (0x0000000B) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX = (0x0000000C) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC = (0x0000000D) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD = (0x0000000E) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE = (0x0000000F) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN = 18 : 18 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE = 19 : 19 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_COPY_TYPE = 21 : 20 # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE = (0x00000001) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT = (0x00000002) # macro -NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED = (0x00000003) # macro -# NVC9B5_LAUNCH_DMA_VPRMODE = 22 : 22 # macro -NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE = 23 : 23 # macro -NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_RESERVED_START_OF_COPY = 24 : 24 # macro -# NVC9B5_LAUNCH_DMA_DISABLE_PLC = 26 : 26 # macro -NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE = 27 : 27 # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD = (0x00000000) # macro -NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD = (0x00000001) # macro -# NVC9B5_LAUNCH_DMA_RESERVED_ERR_CODE = 31 : 28 # macro -NVC9B5_OFFSET_IN_UPPER = (0x00000400) # macro -# NVC9B5_OFFSET_IN_UPPER_UPPER = 24 : 0 # macro -NVC9B5_OFFSET_IN_LOWER = (0x00000404) # macro -# NVC9B5_OFFSET_IN_LOWER_VALUE = 31 : 0 # macro -NVC9B5_OFFSET_OUT_UPPER = (0x00000408) # macro -# NVC9B5_OFFSET_OUT_UPPER_UPPER = 24 : 0 # macro -NVC9B5_OFFSET_OUT_LOWER = (0x0000040C) # macro -# NVC9B5_OFFSET_OUT_LOWER_VALUE = 31 : 0 # macro -NVC9B5_PITCH_IN = (0x00000410) # macro -# NVC9B5_PITCH_IN_VALUE = 31 : 0 # macro -NVC9B5_PITCH_OUT = (0x00000414) # macro -# NVC9B5_PITCH_OUT_VALUE = 31 : 0 # macro -NVC9B5_LINE_LENGTH_IN = (0x00000418) # macro -# NVC9B5_LINE_LENGTH_IN_VALUE = 31 : 0 # macro -NVC9B5_LINE_COUNT = (0x0000041C) # macro -# NVC9B5_LINE_COUNT_VALUE = 31 : 0 # macro -NVC9B5_SET_SECURE_COPY_MODE = (0x00000500) # macro -# NVC9B5_SET_SECURE_COPY_MODE_MODE = 0 : 0 # macro -NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT = (0x00000000) # macro -NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT = (0x00000001) # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET = 20 : 19 # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_PEER_ID = 23 : 21 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_FLA = 24 : 24 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET = 26 : 25 # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB = (0x00000000) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM = (0x00000001) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM = (0x00000002) # macro -NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM = (0x00000003) # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_PEER_ID = 29 : 27 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_FLA = 30 : 30 # macro -# NVC9B5_SET_SECURE_COPY_MODE_RESERVED_END_OF_COPY = 31 : 31 # macro -NVC9B5_SET_DECRYPT_IV0 = (0x00000504) # macro -# NVC9B5_SET_DECRYPT_IV0_VALUE = 31 : 0 # macro -NVC9B5_SET_DECRYPT_IV1 = (0x00000508) # macro -# NVC9B5_SET_DECRYPT_IV1_VALUE = 31 : 0 # macro -NVC9B5_SET_DECRYPT_IV2 = (0x0000050C) # macro -# NVC9B5_SET_DECRYPT_IV2_VALUE = 31 : 0 # macro -NVC9B5_RESERVED_SET_AESCOUNTER = (0x00000510) # macro -# NVC9B5_RESERVED_SET_AESCOUNTER_VALUE = 31 : 0 # macro -NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER = (0x00000514) # macro -# NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER = (0x00000518) # macro -# NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER = (0x00000530) # macro -# NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER = (0x00000534) # macro -# NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER = (0x00000538) # macro -# NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER = (0x0000053C) # macro -# NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS = (0x00000580) # macro -# NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION = 0 : 0 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS = (0x00000000) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS = (0x00000001) # macro -# NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO = 3 : 1 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY = (0x00000000) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY = (0x00000001) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK = (0x00000002) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM = (0x00000003) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE = (0x00000004) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH = (0x00000005) # macro -# NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM = 29 : 28 # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE = (0x00000000) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32 = (0x00000001) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32 = (0x00000002) # macro -NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC = (0x00000003) # macro -NVC9B5_SET_DECOMPRESS_OUT_LENGTH = (0x00000584) # macro -# NVC9B5_SET_DECOMPRESS_OUT_LENGTH_V = 31 : 0 # macro -NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER = (0x00000588) # macro -# NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER_UPPER = 24 : 0 # macro -NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER = (0x0000058C) # macro -# NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER_LOWER = 31 : 0 # macro -NVC9B5_SET_DECOMPRESS_CHECKSUM = (0x00000590) # macro -# NVC9B5_SET_DECOMPRESS_CHECKSUM_V = 31 : 0 # macro -NVC9B5_SET_MEMORY_SCRUB_PARAMETERS = (0x000006FC) # macro -# NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE = 0 : 0 # macro -NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE = (0x00000000) # macro -NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE = (0x00000001) # macro -NVC9B5_SET_REMAP_CONST_A = (0x00000700) # macro -# NVC9B5_SET_REMAP_CONST_A_V = 31 : 0 # macro -NVC9B5_SET_REMAP_CONST_B = (0x00000704) # macro -# NVC9B5_SET_REMAP_CONST_B_V = 31 : 0 # macro -NVC9B5_SET_REMAP_COMPONENTS = (0x00000708) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_X = 2 : 0 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_Y = 6 : 4 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_Z = 10 : 8 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_DST_W = 14 : 12 # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) # macro -NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) # macro -# NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE = 17 : 16 # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) # macro -# NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS = 21 : 20 # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) # macro -# NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS = 25 : 24 # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) # macro -NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) # macro -NVC9B5_SET_DST_BLOCK_SIZE = (0x0000070C) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC9B5_SET_DST_WIDTH = (0x00000710) # macro -# NVC9B5_SET_DST_WIDTH_V = 31 : 0 # macro -NVC9B5_SET_DST_HEIGHT = (0x00000714) # macro -# NVC9B5_SET_DST_HEIGHT_V = 31 : 0 # macro -NVC9B5_SET_DST_DEPTH = (0x00000718) # macro -# NVC9B5_SET_DST_DEPTH_V = 31 : 0 # macro -NVC9B5_SET_DST_LAYER = (0x0000071C) # macro -# NVC9B5_SET_DST_LAYER_V = 31 : 0 # macro -NVC9B5_SET_DST_ORIGIN = (0x00000720) # macro -# NVC9B5_SET_DST_ORIGIN_X = 15 : 0 # macro -# NVC9B5_SET_DST_ORIGIN_Y = 31 : 16 # macro -NVC9B5_SET_SRC_BLOCK_SIZE = (0x00000728) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH = 3 : 0 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT = 7 : 4 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH = 11 : 8 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) # macro -NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) # macro -# NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT = 15 : 12 # macro -NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) # macro -NVC9B5_SET_SRC_WIDTH = (0x0000072C) # macro -# NVC9B5_SET_SRC_WIDTH_V = 31 : 0 # macro -NVC9B5_SET_SRC_HEIGHT = (0x00000730) # macro -# NVC9B5_SET_SRC_HEIGHT_V = 31 : 0 # macro -NVC9B5_SET_SRC_DEPTH = (0x00000734) # macro -# NVC9B5_SET_SRC_DEPTH_V = 31 : 0 # macro -NVC9B5_SET_SRC_LAYER = (0x00000738) # macro -# NVC9B5_SET_SRC_LAYER_V = 31 : 0 # macro -NVC9B5_SET_SRC_ORIGIN = (0x0000073C) # macro -# NVC9B5_SET_SRC_ORIGIN_X = 15 : 0 # macro -# NVC9B5_SET_SRC_ORIGIN_Y = 31 : 16 # macro -NVC9B5_SRC_ORIGIN_X = (0x00000744) # macro -# NVC9B5_SRC_ORIGIN_X_VALUE = 31 : 0 # macro -NVC9B5_SRC_ORIGIN_Y = (0x00000748) # macro -# NVC9B5_SRC_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC9B5_DST_ORIGIN_X = (0x0000074C) # macro -# NVC9B5_DST_ORIGIN_X_VALUE = 31 : 0 # macro -NVC9B5_DST_ORIGIN_Y = (0x00000750) # macro -# NVC9B5_DST_ORIGIN_Y_VALUE = 31 : 0 # macro -NVC9B5_PM_TRIGGER_END = (0x00001114) # macro -# NVC9B5_PM_TRIGGER_END_V = 31 : 0 # macro -class struct__clc9b5_tag0(Structure): - pass - -struct__clc9b5_tag0._pack_ = 1 # source:False +class struct__clc9b5_tag0(Struct): pass struct__clc9b5_tag0._fields_ = [ - ('Reserved00', ctypes.c_uint32 * 64), - ('Nop', ctypes.c_uint32), - ('Reserved01', ctypes.c_uint32 * 15), - ('PmTrigger', ctypes.c_uint32), - ('Reserved02', ctypes.c_uint32 * 54), - ('SetMonitoredFenceType', ctypes.c_uint32), - ('SetMonitoredFenceSignalAddrBaseUpper', ctypes.c_uint32), - ('SetMonitoredFenceSignalAddrBaseLower', ctypes.c_uint32), - ('Reserved03', ctypes.c_uint32 * 6), - ('SetSemaphoreA', ctypes.c_uint32), - ('SetSemaphoreB', ctypes.c_uint32), - ('SetSemaphorePayload', ctypes.c_uint32), - ('SetSemaphorePayloadUpper', ctypes.c_uint32), - ('Reserved04', ctypes.c_uint32 * 1), - ('SetRenderEnableA', ctypes.c_uint32), - ('SetRenderEnableB', ctypes.c_uint32), - ('SetRenderEnableC', ctypes.c_uint32), - ('SetSrcPhysMode', ctypes.c_uint32), - ('SetDstPhysMode', ctypes.c_uint32), - ('Reserved05', ctypes.c_uint32 * 38), - ('LaunchDma', ctypes.c_uint32), - ('Reserved06', ctypes.c_uint32 * 63), - ('OffsetInUpper', ctypes.c_uint32), - ('OffsetInLower', ctypes.c_uint32), - ('OffsetOutUpper', ctypes.c_uint32), - ('OffsetOutLower', ctypes.c_uint32), - ('PitchIn', ctypes.c_uint32), - ('PitchOut', ctypes.c_uint32), - ('LineLengthIn', ctypes.c_uint32), - ('LineCount', ctypes.c_uint32), - ('Reserved07', ctypes.c_uint32 * 56), - ('SetSecureCopyMode', ctypes.c_uint32), - ('SetDecryptIv0', ctypes.c_uint32), - ('SetDecryptIv1', ctypes.c_uint32), - ('SetDecryptIv2', ctypes.c_uint32), - ('Reserved_SetAESCounter', ctypes.c_uint32), - ('SetDecryptAuthTagCompareAddrUpper', ctypes.c_uint32), - ('SetDecryptAuthTagCompareAddrLower', ctypes.c_uint32), - ('Reserved08', ctypes.c_uint32 * 5), - ('SetEncryptAuthTagAddrUpper', ctypes.c_uint32), - ('SetEncryptAuthTagAddrLower', ctypes.c_uint32), - ('SetEncryptIvAddrUpper', ctypes.c_uint32), - ('SetEncryptIvAddrLower', ctypes.c_uint32), - ('Reserved09', ctypes.c_uint32 * 16), - ('SetCompressionParameters', ctypes.c_uint32), - ('SetDecompressOutLength', ctypes.c_uint32), - ('SetDecompressOutLengthAddrUpper', ctypes.c_uint32), - ('SetDecompressOutLengthAddrLower', ctypes.c_uint32), - ('SetDecompressChecksum', ctypes.c_uint32), - ('Reserved10', ctypes.c_uint32 * 90), - ('SetMemoryScrubParameters', ctypes.c_uint32), - ('SetRemapConstA', ctypes.c_uint32), - ('SetRemapConstB', ctypes.c_uint32), - ('SetRemapComponents', ctypes.c_uint32), - ('SetDstBlockSize', ctypes.c_uint32), - ('SetDstWidth', ctypes.c_uint32), - ('SetDstHeight', ctypes.c_uint32), - ('SetDstDepth', ctypes.c_uint32), - ('SetDstLayer', ctypes.c_uint32), - ('SetDstOrigin', ctypes.c_uint32), - ('Reserved11', ctypes.c_uint32 * 1), - ('SetSrcBlockSize', ctypes.c_uint32), - ('SetSrcWidth', ctypes.c_uint32), - ('SetSrcHeight', ctypes.c_uint32), - ('SetSrcDepth', ctypes.c_uint32), - ('SetSrcLayer', ctypes.c_uint32), - ('SetSrcOrigin', ctypes.c_uint32), - ('Reserved12', ctypes.c_uint32 * 1), - ('SrcOriginX', ctypes.c_uint32), - ('SrcOriginY', ctypes.c_uint32), - ('DstOriginX', ctypes.c_uint32), - ('DstOriginY', ctypes.c_uint32), - ('Reserved13', ctypes.c_uint32 * 624), - ('PmTriggerEnd', ctypes.c_uint32), - ('Reserved14', ctypes.c_uint32 * 954), + ('Reserved00', (NvV32 * 64)), + ('Nop', NvV32), + ('Reserved01', (NvV32 * 15)), + ('PmTrigger', NvV32), + ('Reserved02', (NvV32 * 54)), + ('SetMonitoredFenceType', NvV32), + ('SetMonitoredFenceSignalAddrBaseUpper', NvV32), + ('SetMonitoredFenceSignalAddrBaseLower', NvV32), + ('Reserved03', (NvV32 * 6)), + ('SetSemaphoreA', NvV32), + ('SetSemaphoreB', NvV32), + ('SetSemaphorePayload', NvV32), + ('SetSemaphorePayloadUpper', NvV32), + ('Reserved04', (NvV32 * 1)), + ('SetRenderEnableA', NvV32), + ('SetRenderEnableB', NvV32), + ('SetRenderEnableC', NvV32), + ('SetSrcPhysMode', NvV32), + ('SetDstPhysMode', NvV32), + ('Reserved05', (NvV32 * 38)), + ('LaunchDma', NvV32), + ('Reserved06', (NvV32 * 63)), + ('OffsetInUpper', NvV32), + ('OffsetInLower', NvV32), + ('OffsetOutUpper', NvV32), + ('OffsetOutLower', NvV32), + ('PitchIn', NvV32), + ('PitchOut', NvV32), + ('LineLengthIn', NvV32), + ('LineCount', NvV32), + ('Reserved07', (NvV32 * 56)), + ('SetSecureCopyMode', NvV32), + ('SetDecryptIv0', NvV32), + ('SetDecryptIv1', NvV32), + ('SetDecryptIv2', NvV32), + ('Reserved_SetAESCounter', NvV32), + ('SetDecryptAuthTagCompareAddrUpper', NvV32), + ('SetDecryptAuthTagCompareAddrLower', NvV32), + ('Reserved08', (NvV32 * 5)), + ('SetEncryptAuthTagAddrUpper', NvV32), + ('SetEncryptAuthTagAddrLower', NvV32), + ('SetEncryptIvAddrUpper', NvV32), + ('SetEncryptIvAddrLower', NvV32), + ('Reserved09', (NvV32 * 16)), + ('SetCompressionParameters', NvV32), + ('SetDecompressOutLength', NvV32), + ('SetDecompressOutLengthAddrUpper', NvV32), + ('SetDecompressOutLengthAddrLower', NvV32), + ('SetDecompressChecksum', NvV32), + ('Reserved10', (NvV32 * 90)), + ('SetMemoryScrubParameters', NvV32), + ('SetRemapConstA', NvV32), + ('SetRemapConstB', NvV32), + ('SetRemapComponents', NvV32), + ('SetDstBlockSize', NvV32), + ('SetDstWidth', NvV32), + ('SetDstHeight', NvV32), + ('SetDstDepth', NvV32), + ('SetDstLayer', NvV32), + ('SetDstOrigin', NvV32), + ('Reserved11', (NvV32 * 1)), + ('SetSrcBlockSize', NvV32), + ('SetSrcWidth', NvV32), + ('SetSrcHeight', NvV32), + ('SetSrcDepth', NvV32), + ('SetSrcLayer', NvV32), + ('SetSrcOrigin', NvV32), + ('Reserved12', (NvV32 * 1)), + ('SrcOriginX', NvV32), + ('SrcOriginY', NvV32), + ('DstOriginX', NvV32), + ('DstOriginY', NvV32), + ('Reserved13', (NvV32 * 624)), + ('PmTriggerEnd', NvV32), + ('Reserved14', (NvV32 * 954)), ] - -blackwell_dma_copy_aControlPio = struct__clc9b5_tag0 -_UVM_IOCTL_H = True # macro -def UVM_IOCTL_BASE(i): # macro - return i -UVM_RESERVE_VA = UVM_IOCTL_BASE ( 1 ) # macro -UVM_RELEASE_VA = UVM_IOCTL_BASE ( 2 ) # macro -UVM_REGION_COMMIT = UVM_IOCTL_BASE ( 3 ) # macro -UVM_REGION_DECOMMIT = UVM_IOCTL_BASE ( 4 ) # macro -UVM_REGION_SET_STREAM = UVM_IOCTL_BASE ( 5 ) # macro -UVM_SET_STREAM_RUNNING = UVM_IOCTL_BASE ( 6 ) # macro -UVM_MAX_STREAMS_PER_IOCTL_CALL = 32 # macro -UVM_SET_STREAM_STOPPED = UVM_IOCTL_BASE ( 7 ) # macro -UVM_RUN_TEST = UVM_IOCTL_BASE ( 9 ) # macro -UVM_EVENTS_OFFSET_BASE = (1<<63) # macro -UVM_COUNTERS_OFFSET_BASE = (1<<62) # macro -UVM_ADD_SESSION = UVM_IOCTL_BASE ( 10 ) # macro -UVM_REMOVE_SESSION = UVM_IOCTL_BASE ( 11 ) # macro -UVM_MAX_COUNTERS_PER_IOCTL_CALL = 32 # macro -UVM_ENABLE_COUNTERS = UVM_IOCTL_BASE ( 12 ) # macro -UVM_MAP_COUNTER = UVM_IOCTL_BASE ( 13 ) # macro -UVM_CREATE_EVENT_QUEUE = UVM_IOCTL_BASE ( 14 ) # macro -UVM_REMOVE_EVENT_QUEUE = UVM_IOCTL_BASE ( 15 ) # macro -UVM_MAP_EVENT_QUEUE = UVM_IOCTL_BASE ( 16 ) # macro -UVM_EVENT_CTRL = UVM_IOCTL_BASE ( 17 ) # macro -UVM_REGISTER_MPS_SERVER = UVM_IOCTL_BASE ( 18 ) # macro -UVM_REGISTER_MPS_CLIENT = UVM_IOCTL_BASE ( 19 ) # macro -UVM_GET_GPU_UUID_TABLE = UVM_IOCTL_BASE ( 20 ) # macro -UVM_CREATE_RANGE_GROUP = UVM_IOCTL_BASE ( 23 ) # macro -UVM_DESTROY_RANGE_GROUP = UVM_IOCTL_BASE ( 24 ) # macro -UVM_REGISTER_GPU_VASPACE = UVM_IOCTL_BASE ( 25 ) # macro -UVM_UNREGISTER_GPU_VASPACE = UVM_IOCTL_BASE ( 26 ) # macro -UVM_REGISTER_CHANNEL = UVM_IOCTL_BASE ( 27 ) # macro -UVM_UNREGISTER_CHANNEL = UVM_IOCTL_BASE ( 28 ) # macro -UVM_ENABLE_PEER_ACCESS = UVM_IOCTL_BASE ( 29 ) # macro -UVM_DISABLE_PEER_ACCESS = UVM_IOCTL_BASE ( 30 ) # macro -UVM_SET_RANGE_GROUP = UVM_IOCTL_BASE ( 31 ) # macro -UVM_MAP_EXTERNAL_ALLOCATION = UVM_IOCTL_BASE ( 33 ) # macro -UVM_FREE = UVM_IOCTL_BASE ( 34 ) # macro -UVM_MEM_MAP = UVM_IOCTL_BASE ( 35 ) # macro -UVM_DEBUG_ACCESS_MEMORY = UVM_IOCTL_BASE ( 36 ) # macro -UVM_REGISTER_GPU = UVM_IOCTL_BASE ( 37 ) # macro -UVM_UNREGISTER_GPU = UVM_IOCTL_BASE ( 38 ) # macro -UVM_PAGEABLE_MEM_ACCESS = UVM_IOCTL_BASE ( 39 ) # macro -UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL = 32 # macro -UVM_PREVENT_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE ( 40 ) # macro -UVM_ALLOW_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE ( 41 ) # macro -UVM_SET_PREFERRED_LOCATION = UVM_IOCTL_BASE ( 42 ) # macro -UVM_UNSET_PREFERRED_LOCATION = UVM_IOCTL_BASE ( 43 ) # macro -UVM_ENABLE_READ_DUPLICATION = UVM_IOCTL_BASE ( 44 ) # macro -UVM_DISABLE_READ_DUPLICATION = UVM_IOCTL_BASE ( 45 ) # macro -UVM_SET_ACCESSED_BY = UVM_IOCTL_BASE ( 46 ) # macro -UVM_UNSET_ACCESSED_BY = UVM_IOCTL_BASE ( 47 ) # macro -UVM_MIGRATE_FLAG_ASYNC = 0x00000001 # macro -UVM_MIGRATE_FLAG_SKIP_CPU_MAP = 0x00000002 # macro -UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE = 0x00000004 # macro -UVM_MIGRATE_FLAGS_TEST_ALL = (0x00000002|0x00000004) # macro -UVM_MIGRATE_FLAGS_ALL = (0x00000001|(0x00000002|0x00000004)) # macro -UVM_MIGRATE = UVM_IOCTL_BASE ( 51 ) # macro -UVM_MIGRATE_RANGE_GROUP = UVM_IOCTL_BASE ( 53 ) # macro -UVM_ENABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE ( 54 ) # macro -UVM_DISABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE ( 55 ) # macro -UVM_TOOLS_INIT_EVENT_TRACKER = UVM_IOCTL_BASE ( 56 ) # macro -UVM_TOOLS_SET_NOTIFICATION_THRESHOLD = UVM_IOCTL_BASE ( 57 ) # macro -UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS = UVM_IOCTL_BASE ( 58 ) # macro -UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS = UVM_IOCTL_BASE ( 59 ) # macro -UVM_TOOLS_ENABLE_COUNTERS = UVM_IOCTL_BASE ( 60 ) # macro -UVM_TOOLS_DISABLE_COUNTERS = UVM_IOCTL_BASE ( 61 ) # macro -UVM_TOOLS_READ_PROCESS_MEMORY = UVM_IOCTL_BASE ( 62 ) # macro -UVM_TOOLS_WRITE_PROCESS_MEMORY = UVM_IOCTL_BASE ( 63 ) # macro -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE = UVM_IOCTL_BASE ( 64 ) # macro -UVM_MAP_DYNAMIC_PARALLELISM_REGION = UVM_IOCTL_BASE ( 65 ) # macro -UVM_UNMAP_EXTERNAL = UVM_IOCTL_BASE ( 66 ) # macro -UVM_TOOLS_FLUSH_EVENTS = UVM_IOCTL_BASE ( 67 ) # macro -UVM_ALLOC_SEMAPHORE_POOL = UVM_IOCTL_BASE ( 68 ) # macro -UVM_CLEAN_UP_ZOMBIE_RESOURCES = UVM_IOCTL_BASE ( 69 ) # macro -UVM_PAGEABLE_MEM_ACCESS_ON_GPU = UVM_IOCTL_BASE ( 70 ) # macro -UVM_POPULATE_PAGEABLE = UVM_IOCTL_BASE ( 71 ) # macro -UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED = 0x00000001 # macro -UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK = 0x00000002 # macro -UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL = (0x00000001|0x00000002) # macro -UVM_POPULATE_PAGEABLE_FLAGS_ALL = (0x00000001|0x00000002) # macro -UVM_VALIDATE_VA_RANGE = UVM_IOCTL_BASE ( 72 ) # macro -UVM_CREATE_EXTERNAL_RANGE = UVM_IOCTL_BASE ( 73 ) # macro -UVM_MAP_EXTERNAL_SPARSE = UVM_IOCTL_BASE ( 74 ) # macro -UVM_MM_INITIALIZE = UVM_IOCTL_BASE ( 75 ) # macro -UVM_TOOLS_INIT_EVENT_TRACKER_V2 = UVM_IOCTL_BASE ( 76 ) # macro -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2 = UVM_IOCTL_BASE ( 77 ) # macro -UVM_ALLOC_DEVICE_P2P = UVM_IOCTL_BASE ( 78 ) # macro -UVM_CLEAR_ALL_ACCESS_COUNTERS = UVM_IOCTL_BASE ( 79 ) # macro -UVM_IS_8_SUPPORTED = UVM_IOCTL_BASE ( 2047 ) # macro -class struct_c__SA_UVM_RESERVE_VA_PARAMS(Structure): - pass - -struct_c__SA_UVM_RESERVE_VA_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_RESERVE_VA_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class volatile_struct__clc9b5_tag0(Struct): pass +blackwell_dma_copy_aControlPio = volatile_struct__clc9b5_tag0 +volatile_struct__clc9b5_tag0._fields_ = [ + ('Reserved00', (NvV32 * 64)), + ('Nop', NvV32), + ('Reserved01', (NvV32 * 15)), + ('PmTrigger', NvV32), + ('Reserved02', (NvV32 * 54)), + ('SetMonitoredFenceType', NvV32), + ('SetMonitoredFenceSignalAddrBaseUpper', NvV32), + ('SetMonitoredFenceSignalAddrBaseLower', NvV32), + ('Reserved03', (NvV32 * 6)), + ('SetSemaphoreA', NvV32), + ('SetSemaphoreB', NvV32), + ('SetSemaphorePayload', NvV32), + ('SetSemaphorePayloadUpper', NvV32), + ('Reserved04', (NvV32 * 1)), + ('SetRenderEnableA', NvV32), + ('SetRenderEnableB', NvV32), + ('SetRenderEnableC', NvV32), + ('SetSrcPhysMode', NvV32), + ('SetDstPhysMode', NvV32), + ('Reserved05', (NvV32 * 38)), + ('LaunchDma', NvV32), + ('Reserved06', (NvV32 * 63)), + ('OffsetInUpper', NvV32), + ('OffsetInLower', NvV32), + ('OffsetOutUpper', NvV32), + ('OffsetOutLower', NvV32), + ('PitchIn', NvV32), + ('PitchOut', NvV32), + ('LineLengthIn', NvV32), + ('LineCount', NvV32), + ('Reserved07', (NvV32 * 56)), + ('SetSecureCopyMode', NvV32), + ('SetDecryptIv0', NvV32), + ('SetDecryptIv1', NvV32), + ('SetDecryptIv2', NvV32), + ('Reserved_SetAESCounter', NvV32), + ('SetDecryptAuthTagCompareAddrUpper', NvV32), + ('SetDecryptAuthTagCompareAddrLower', NvV32), + ('Reserved08', (NvV32 * 5)), + ('SetEncryptAuthTagAddrUpper', NvV32), + ('SetEncryptAuthTagAddrLower', NvV32), + ('SetEncryptIvAddrUpper', NvV32), + ('SetEncryptIvAddrLower', NvV32), + ('Reserved09', (NvV32 * 16)), + ('SetCompressionParameters', NvV32), + ('SetDecompressOutLength', NvV32), + ('SetDecompressOutLengthAddrUpper', NvV32), + ('SetDecompressOutLengthAddrLower', NvV32), + ('SetDecompressChecksum', NvV32), + ('Reserved10', (NvV32 * 90)), + ('SetMemoryScrubParameters', NvV32), + ('SetRemapConstA', NvV32), + ('SetRemapConstB', NvV32), + ('SetRemapComponents', NvV32), + ('SetDstBlockSize', NvV32), + ('SetDstWidth', NvV32), + ('SetDstHeight', NvV32), + ('SetDstDepth', NvV32), + ('SetDstLayer', NvV32), + ('SetDstOrigin', NvV32), + ('Reserved11', (NvV32 * 1)), + ('SetSrcBlockSize', NvV32), + ('SetSrcWidth', NvV32), + ('SetSrcHeight', NvV32), + ('SetSrcDepth', NvV32), + ('SetSrcLayer', NvV32), + ('SetSrcOrigin', NvV32), + ('Reserved12', (NvV32 * 1)), + ('SrcOriginX', NvV32), + ('SrcOriginY', NvV32), + ('DstOriginX', NvV32), + ('DstOriginY', NvV32), + ('Reserved13', (NvV32 * 624)), + ('PmTriggerEnd', NvV32), + ('Reserved14', (NvV32 * 954)), ] - -UVM_RESERVE_VA_PARAMS = struct_c__SA_UVM_RESERVE_VA_PARAMS -class struct_c__SA_UVM_RELEASE_VA_PARAMS(Structure): - pass - -struct_c__SA_UVM_RELEASE_VA_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_RELEASE_VA_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class UVM_RESERVE_VA_PARAMS(Struct): pass +NV_STATUS = ctypes.c_uint32 +UVM_RESERVE_VA_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), ] - -UVM_RELEASE_VA_PARAMS = struct_c__SA_UVM_RELEASE_VA_PARAMS -class struct_c__SA_UVM_REGION_COMMIT_PARAMS(Structure): - pass - -class struct_nv_uuid(Structure): - pass - -struct_nv_uuid._pack_ = 1 # source:False +class UVM_RELEASE_VA_PARAMS(Struct): pass +UVM_RELEASE_VA_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_REGION_COMMIT_PARAMS(Struct): pass +UvmStream = ctypes.c_uint64 +class struct_nv_uuid(Struct): pass +NvProcessorUuid = struct_nv_uuid struct_nv_uuid._fields_ = [ - ('uuid', ctypes.c_ubyte * 16), -] - -struct_c__SA_UVM_REGION_COMMIT_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGION_COMMIT_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('streamId', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGION_COMMIT_PARAMS = struct_c__SA_UVM_REGION_COMMIT_PARAMS -class struct_c__SA_UVM_REGION_DECOMMIT_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGION_DECOMMIT_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGION_DECOMMIT_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGION_DECOMMIT_PARAMS = struct_c__SA_UVM_REGION_DECOMMIT_PARAMS -class struct_c__SA_UVM_REGION_SET_STREAM_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGION_SET_STREAM_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGION_SET_STREAM_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('newStreamId', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGION_SET_STREAM_PARAMS = struct_c__SA_UVM_REGION_SET_STREAM_PARAMS -class struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS._fields_ = [ - ('streamId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_STREAM_RUNNING_PARAMS = struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS -class struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS._fields_ = [ - ('streamIdArray', ctypes.c_uint64 * 32), - ('nStreams', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_STREAM_STOPPED_PARAMS = struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS -class struct_c__SA_UVM_RUN_TEST_PARAMS(Structure): - pass - -class struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu(Structure): - pass - -struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu._pack_ = 1 # source:False -struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu._fields_ = [ - ('peerGpuUuid', struct_nv_uuid), - ('peerId', ctypes.c_uint32), -] - -struct_c__SA_UVM_RUN_TEST_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_RUN_TEST_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('test', ctypes.c_uint32), - ('multiGpu', struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu), - ('rmStatus', ctypes.c_uint32), -] - -UVM_RUN_TEST_PARAMS = struct_c__SA_UVM_RUN_TEST_PARAMS -class struct_c__SA_UVM_ADD_SESSION_PARAMS(Structure): - pass - -struct_c__SA_UVM_ADD_SESSION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ADD_SESSION_PARAMS._fields_ = [ - ('pidTarget', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('countersBaseAddress', ctypes.POINTER(None)), - ('sessionIndex', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ADD_SESSION_PARAMS = struct_c__SA_UVM_ADD_SESSION_PARAMS -class struct_c__SA_UVM_REMOVE_SESSION_PARAMS(Structure): - pass - -struct_c__SA_UVM_REMOVE_SESSION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REMOVE_SESSION_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REMOVE_SESSION_PARAMS = struct_c__SA_UVM_REMOVE_SESSION_PARAMS -class struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS(Structure): - pass - -class struct_c__SA_UvmCounterConfig(Structure): - pass - -struct_c__SA_UvmCounterConfig._pack_ = 1 # source:False -struct_c__SA_UvmCounterConfig._fields_ = [ - ('scope', ctypes.c_uint32), - ('name', ctypes.c_uint32), - ('gpuid', struct_nv_uuid), - ('state', ctypes.c_uint32), -] - -struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('config', struct_c__SA_UvmCounterConfig * 32), - ('count', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ENABLE_COUNTERS_PARAMS = struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS -class struct_c__SA_UVM_MAP_COUNTER_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_COUNTER_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_COUNTER_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('scope', ctypes.c_uint32), - ('counterName', ctypes.c_uint32), - ('gpuUuid', struct_nv_uuid), - ('PADDING_0', ctypes.c_ubyte * 4), - ('addr', ctypes.POINTER(None)), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_MAP_COUNTER_PARAMS = struct_c__SA_UVM_MAP_COUNTER_PARAMS -class struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS(Structure): - pass - -struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('queueSize', ctypes.c_uint64), - ('notificationCount', ctypes.c_uint64), - ('timeStampType', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_CREATE_EVENT_QUEUE_PARAMS = struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS -class struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS(Structure): - pass - -struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REMOVE_EVENT_QUEUE_PARAMS = struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS -class struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('userRODataAddr', ctypes.POINTER(None)), - ('userRWDataAddr', ctypes.POINTER(None)), - ('readIndexAddr', ctypes.POINTER(None)), - ('writeIndexAddr', ctypes.POINTER(None)), - ('queueBufferAddr', ctypes.POINTER(None)), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MAP_EVENT_QUEUE_PARAMS = struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS -class struct_c__SA_UVM_EVENT_CTRL_PARAMS(Structure): - pass - -struct_c__SA_UVM_EVENT_CTRL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_EVENT_CTRL_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('eventQueueIndex', ctypes.c_uint32), - ('eventType', ctypes.c_int32), - ('enable', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_EVENT_CTRL_PARAMS = struct_c__SA_UVM_EVENT_CTRL_PARAMS -class struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS._fields_ = [ - ('gpuUuidArray', struct_nv_uuid * 32), - ('numGpus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('serverId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_REGISTER_MPS_SERVER_PARAMS = struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS -class struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS._fields_ = [ - ('serverId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_REGISTER_MPS_CLIENT_PARAMS = struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS -class struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS(Structure): - pass - -struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS._fields_ = [ - ('gpuUuidArray', struct_nv_uuid * 32), - ('validCount', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_GET_GPU_UUID_TABLE_PARAMS = struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS -class struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_CREATE_RANGE_GROUP_PARAMS = struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_DESTROY_RANGE_GROUP_PARAMS = struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hVaSpace', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REGISTER_GPU_VASPACE_PARAMS = struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS -class struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_UNREGISTER_GPU_VASPACE_PARAMS = struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS -class struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_REGISTER_CHANNEL_PARAMS = struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS -class struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_UNREGISTER_CHANNEL_PARAMS = struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS -class struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS._fields_ = [ - ('gpuUuidA', struct_nv_uuid), - ('gpuUuidB', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ENABLE_PEER_ACCESS_PARAMS = struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS -class struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS._fields_ = [ - ('gpuUuidA', struct_nv_uuid), - ('gpuUuidB', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_DISABLE_PEER_ACCESS_PARAMS = struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS -class struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_RANGE_GROUP_PARAMS = struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS(Structure): - pass - -class struct_c__SA_UvmGpuMappingAttributes(Structure): - pass - -struct_c__SA_UvmGpuMappingAttributes._pack_ = 1 # source:False -struct_c__SA_UvmGpuMappingAttributes._fields_ = [ - ('gpuUuid', struct_nv_uuid), - ('gpuMappingType', ctypes.c_uint32), - ('gpuCachingType', ctypes.c_uint32), - ('gpuFormatType', ctypes.c_uint32), - ('gpuElementBits', ctypes.c_uint32), - ('gpuCompressionType', ctypes.c_uint32), -] - -struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('perGpuAttributes', struct_c__SA_UvmGpuMappingAttributes * 256), - ('gpuAttributesCount', ctypes.c_uint64), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_MAP_EXTERNAL_ALLOCATION_PARAMS = struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS -class struct_c__SA_UVM_FREE_PARAMS(Structure): - pass - -struct_c__SA_UVM_FREE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_FREE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_FREE_PARAMS = struct_c__SA_UVM_FREE_PARAMS -class struct_c__SA_UVM_MEM_MAP_PARAMS(Structure): - pass - -struct_c__SA_UVM_MEM_MAP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MEM_MAP_PARAMS._fields_ = [ - ('regionBase', ctypes.POINTER(None)), - ('regionLength', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MEM_MAP_PARAMS = struct_c__SA_UVM_MEM_MAP_PARAMS -class struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS(Structure): - pass - -struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [ - ('sessionIndex', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('baseAddress', ctypes.c_uint64), - ('sizeInBytes', ctypes.c_uint64), - ('accessType', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('buffer', ctypes.c_uint64), - ('isBitmaskSet', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), - ('bitmask', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -UVM_DEBUG_ACCESS_MEMORY_PARAMS = struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS -class struct_c__SA_UVM_REGISTER_GPU_PARAMS(Structure): - pass - -struct_c__SA_UVM_REGISTER_GPU_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_REGISTER_GPU_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('numaEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numaNodeId', ctypes.c_int32), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hSmcPartRef', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_REGISTER_GPU_PARAMS = struct_c__SA_UVM_REGISTER_GPU_PARAMS -class struct_c__SA_UVM_UNREGISTER_GPU_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNREGISTER_GPU_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNREGISTER_GPU_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_UNREGISTER_GPU_PARAMS = struct_c__SA_UVM_UNREGISTER_GPU_PARAMS -class struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS._fields_ = [ - ('pageableMemAccess', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rmStatus', ctypes.c_uint32), -] - -UVM_PAGEABLE_MEM_ACCESS_PARAMS = struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS -class struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS(Structure): - pass - -struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [ - ('rangeGroupIds', ctypes.c_uint64 * 32), - ('numGroupIds', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS = struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS -class struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS(Structure): - pass - -struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [ - ('rangeGroupIds', ctypes.c_uint64 * 32), - ('numGroupIds', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS = struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS -class struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('preferredLocation', struct_nv_uuid), - ('preferredCpuNumaNode', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_SET_PREFERRED_LOCATION_PARAMS = struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS -class struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_UNSET_PREFERRED_LOCATION_PARAMS = struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS -class struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_ENABLE_READ_DUPLICATION_PARAMS = struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS -class struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS(Structure): - pass - -struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_DISABLE_READ_DUPLICATION_PARAMS = struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS -class struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS(Structure): - pass - -struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('accessedByUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_SET_ACCESSED_BY_PARAMS = struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS -class struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS._fields_ = [ - ('requestedBase', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('accessedByUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_UNSET_ACCESSED_BY_PARAMS = struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS -class struct_c__SA_UVM_MIGRATE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MIGRATE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MIGRATE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('destinationUuid', struct_nv_uuid), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('semaphoreAddress', ctypes.c_uint64), - ('semaphorePayload', ctypes.c_uint32), - ('cpuNumaNode', ctypes.c_int32), - ('userSpaceStart', ctypes.c_uint64), - ('userSpaceLength', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -UVM_MIGRATE_PARAMS = struct_c__SA_UVM_MIGRATE_PARAMS -class struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS(Structure): - pass - -struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS._fields_ = [ - ('rangeGroupId', ctypes.c_uint64), - ('destinationUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MIGRATE_RANGE_GROUP_PARAMS = struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS -class struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Structure): - pass - -struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS = struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS -class struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Structure): - pass - -struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), -] - -UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS = struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS -class struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS._fields_ = [ - ('queueBuffer', ctypes.c_uint64), - ('queueBufferSize', ctypes.c_uint64), - ('controlBuffer', ctypes.c_uint64), - ('processor', struct_nv_uuid), - ('allProcessors', ctypes.c_uint32), - ('uvmFd', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS = struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS -class struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS._fields_ = [ - ('notificationThreshold', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS = struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS -class struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS._fields_ = [ - ('eventTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS = struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS -class struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS._fields_ = [ - ('eventTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS = struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS -class struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS._fields_ = [ - ('counterTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_ENABLE_COUNTERS_PARAMS = struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS -class struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS._fields_ = [ - ('counterTypeFlags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_DISABLE_COUNTERS_PARAMS = struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS -class struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS._fields_ = [ - ('buffer', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('targetVa', ctypes.c_uint64), - ('bytesRead', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS = struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS -class struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS._fields_ = [ - ('buffer', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('targetVa', ctypes.c_uint64), - ('bytesWritten', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS = struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS -class struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS._fields_ = [ - ('tablePtr', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS = struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS -class struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS = struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS -class struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS(Structure): - pass - -struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_UNMAP_EXTERNAL_PARAMS = struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS -class struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS(Structure): - pass - -struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS._fields_ = [ - ('rmStatus', ctypes.c_uint32), -] - -UVM_TOOLS_FLUSH_EVENTS_PARAMS = struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS -class struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS(Structure): - pass - -struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('perGpuAttributes', struct_c__SA_UvmGpuMappingAttributes * 256), - ('gpuAttributesCount', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_ALLOC_SEMAPHORE_POOL_PARAMS = struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS -class struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS(Structure): - pass - -struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS._fields_ = [ - ('rmStatus', ctypes.c_uint32), -] - -UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS = struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS -class struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS(Structure): - pass - -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS._fields_ = [ - ('gpu_uuid', struct_nv_uuid), - ('pageableMemAccess', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rmStatus', ctypes.c_uint32), -] - -UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS = struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS -class struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS(Structure): - pass - -struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_POPULATE_PAGEABLE_PARAMS = struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS -class struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS(Structure): - pass - -struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_VALIDATE_VA_RANGE_PARAMS = struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS -class struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS(Structure): - pass - -struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_CREATE_EXTERNAL_RANGE_PARAMS = struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS -class struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_MAP_EXTERNAL_SPARSE_PARAMS = struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS -class struct_c__SA_UVM_MM_INITIALIZE_PARAMS(Structure): - pass - -struct_c__SA_UVM_MM_INITIALIZE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_MM_INITIALIZE_PARAMS._fields_ = [ - ('uvmFd', ctypes.c_int32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_MM_INITIALIZE_PARAMS = struct_c__SA_UVM_MM_INITIALIZE_PARAMS -UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS = struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS -UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS = struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS -class struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS(Structure): - pass - -struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('gpuUuid', struct_nv_uuid), - ('rmCtrlFd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_ALLOC_DEVICE_P2P_PARAMS = struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS -class struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS(Structure): - pass - -struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS._fields_ = [ - ('rmStatus', ctypes.c_uint32), -] - -UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS = struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS -class struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS(Structure): - pass - -struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS._fields_ = [ - ('is8Supported', ctypes.c_uint32), - ('rmStatus', ctypes.c_uint32), -] - -UVM_IS_8_SUPPORTED_PARAMS = struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS -_UVM_LINUX_IOCTL_H = True # macro -UVM_INITIALIZE = 0x30000001 # macro -UVM_DEINITIALIZE = 0x30000002 # macro -class struct_c__SA_UVM_INITIALIZE_PARAMS(Structure): - pass - -struct_c__SA_UVM_INITIALIZE_PARAMS._pack_ = 1 # source:False -struct_c__SA_UVM_INITIALIZE_PARAMS._fields_ = [ - ('flags', ctypes.c_uint64), - ('rmStatus', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -UVM_INITIALIZE_PARAMS = struct_c__SA_UVM_INITIALIZE_PARAMS -__ga100_dev_fault_h__ = True # macro -NV_PFAULT = True # macro -NV_PFAULT_MMU_ENG_ID_GRAPHICS = 64 # macro -NV_PFAULT_MMU_ENG_ID_DISPLAY = 1 # macro -NV_PFAULT_MMU_ENG_ID_GSP = 2 # macro -NV_PFAULT_MMU_ENG_ID_IFB = 9 # macro -NV_PFAULT_MMU_ENG_ID_FLA = 4 # macro -NV_PFAULT_MMU_ENG_ID_BAR1 = 128 # macro -NV_PFAULT_MMU_ENG_ID_BAR2 = 192 # macro -NV_PFAULT_MMU_ENG_ID_SEC = 14 # macro -NV_PFAULT_MMU_ENG_ID_PERF = 8 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC = 25 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC0 = 25 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC1 = 26 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC2 = 27 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC3 = 28 # macro -NV_PFAULT_MMU_ENG_ID_NVDEC4 = 29 # macro -NV_PFAULT_MMU_ENG_ID_NVJPG0 = 30 # macro -NV_PFAULT_MMU_ENG_ID_GRCOPY = 15 # macro -NV_PFAULT_MMU_ENG_ID_CE0 = 15 # macro -NV_PFAULT_MMU_ENG_ID_CE1 = 16 # macro -NV_PFAULT_MMU_ENG_ID_CE2 = 17 # macro -NV_PFAULT_MMU_ENG_ID_CE3 = 18 # macro -NV_PFAULT_MMU_ENG_ID_CE4 = 19 # macro -NV_PFAULT_MMU_ENG_ID_CE5 = 20 # macro -NV_PFAULT_MMU_ENG_ID_CE6 = 21 # macro -NV_PFAULT_MMU_ENG_ID_CE7 = 22 # macro -NV_PFAULT_MMU_ENG_ID_CE8 = 23 # macro -NV_PFAULT_MMU_ENG_ID_CE9 = 24 # macro -NV_PFAULT_MMU_ENG_ID_PWR_PMU = 6 # macro -NV_PFAULT_MMU_ENG_ID_PTP = 3 # macro -NV_PFAULT_MMU_ENG_ID_NVENC0 = 11 # macro -NV_PFAULT_MMU_ENG_ID_NVENC1 = 12 # macro -NV_PFAULT_MMU_ENG_ID_NVENC2 = 13 # macro -NV_PFAULT_MMU_ENG_ID_OFA0 = 10 # macro -NV_PFAULT_MMU_ENG_ID_PHYSICAL = 31 # macro -NV_PFAULT_MMU_ENG_ID_HOST0 = 32 # macro -NV_PFAULT_MMU_ENG_ID_HOST1 = 33 # macro -NV_PFAULT_MMU_ENG_ID_HOST2 = 34 # macro -NV_PFAULT_MMU_ENG_ID_HOST3 = 35 # macro -NV_PFAULT_MMU_ENG_ID_HOST4 = 36 # macro -NV_PFAULT_MMU_ENG_ID_HOST5 = 37 # macro -NV_PFAULT_MMU_ENG_ID_HOST6 = 38 # macro -NV_PFAULT_MMU_ENG_ID_HOST7 = 39 # macro -NV_PFAULT_MMU_ENG_ID_HOST8 = 40 # macro -NV_PFAULT_MMU_ENG_ID_HOST9 = 41 # macro -NV_PFAULT_MMU_ENG_ID_HOST10 = 42 # macro -NV_PFAULT_MMU_ENG_ID_HOST11 = 43 # macro -NV_PFAULT_MMU_ENG_ID_HOST12 = 44 # macro -NV_PFAULT_MMU_ENG_ID_HOST13 = 45 # macro -NV_PFAULT_MMU_ENG_ID_HOST14 = 46 # macro -NV_PFAULT_MMU_ENG_ID_HOST15 = 47 # macro -NV_PFAULT_MMU_ENG_ID_HOST16 = 48 # macro -NV_PFAULT_MMU_ENG_ID_HOST17 = 49 # macro -NV_PFAULT_MMU_ENG_ID_HOST18 = 50 # macro -NV_PFAULT_MMU_ENG_ID_HOST19 = 51 # macro -NV_PFAULT_MMU_ENG_ID_HOST20 = 52 # macro -NV_PFAULT_MMU_ENG_ID_HOST21 = 53 # macro -NV_PFAULT_MMU_ENG_ID_HOST22 = 54 # macro -NV_PFAULT_MMU_ENG_ID_HOST23 = 55 # macro -NV_PFAULT_MMU_ENG_ID_HOST24 = 56 # macro -NV_PFAULT_MMU_ENG_ID_HOST25 = 57 # macro -NV_PFAULT_MMU_ENG_ID_HOST26 = 58 # macro -NV_PFAULT_MMU_ENG_ID_HOST27 = 59 # macro -NV_PFAULT_MMU_ENG_ID_HOST28 = 60 # macro -NV_PFAULT_MMU_ENG_ID_HOST29 = 61 # macro -NV_PFAULT_MMU_ENG_ID_HOST30 = 62 # macro -NV_PFAULT_MMU_ENG_ID_HOST31 = 63 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN0 = 128 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN1 = 129 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN2 = 130 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN3 = 131 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN4 = 132 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN5 = 133 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN6 = 134 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN7 = 135 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN8 = 136 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN9 = 137 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN10 = 138 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN11 = 139 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN12 = 140 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN13 = 141 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN14 = 142 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN15 = 143 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN16 = 144 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN17 = 145 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN18 = 146 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN19 = 147 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN20 = 148 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN21 = 149 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN22 = 150 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN23 = 151 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN24 = 152 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN25 = 153 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN26 = 154 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN27 = 155 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN28 = 156 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN29 = 157 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN30 = 158 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN31 = 159 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN32 = 160 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN33 = 161 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN34 = 162 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN35 = 163 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN36 = 164 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN37 = 165 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN38 = 166 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN39 = 167 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN40 = 168 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN41 = 169 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN42 = 170 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN43 = 171 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN44 = 172 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN45 = 173 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN46 = 174 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN47 = 175 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN48 = 176 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN49 = 177 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN50 = 178 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN51 = 179 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN52 = 180 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN53 = 181 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN54 = 182 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN55 = 183 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN56 = 184 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN57 = 185 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN58 = 186 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN59 = 187 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN60 = 188 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN61 = 189 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN62 = 190 # macro -NV_PFAULT_MMU_ENG_ID_BAR1_FN63 = 191 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN0 = 192 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN1 = 193 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN2 = 194 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN3 = 195 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN4 = 196 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN5 = 197 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN6 = 198 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN7 = 199 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN8 = 200 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN9 = 201 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN10 = 202 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN11 = 203 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN12 = 204 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN13 = 205 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN14 = 206 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN15 = 207 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN16 = 208 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN17 = 209 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN18 = 210 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN19 = 211 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN20 = 212 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN21 = 213 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN22 = 214 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN23 = 215 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN24 = 216 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN25 = 217 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN26 = 218 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN27 = 219 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN28 = 220 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN29 = 221 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN30 = 222 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN31 = 223 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN32 = 224 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN33 = 225 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN34 = 226 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN35 = 227 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN36 = 228 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN37 = 229 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN38 = 230 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN39 = 231 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN40 = 232 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN41 = 233 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN42 = 234 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN43 = 235 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN44 = 236 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN45 = 237 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN46 = 238 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN47 = 239 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN48 = 240 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN49 = 241 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN50 = 242 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN51 = 243 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN52 = 244 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN53 = 245 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN54 = 246 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN55 = 247 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN56 = 248 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN57 = 249 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN58 = 250 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN59 = 251 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN60 = 252 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN61 = 253 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN62 = 254 # macro -NV_PFAULT_MMU_ENG_ID_BAR2_FN63 = 255 # macro -# NV_PFAULT_FAULT_TYPE = 4 : 0 # macro -NV_PFAULT_FAULT_TYPE_PDE = 0x00000000 # macro -NV_PFAULT_FAULT_TYPE_PDE_SIZE = 0x00000001 # macro -NV_PFAULT_FAULT_TYPE_PTE = 0x00000002 # macro -NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION = 0x00000003 # macro -NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK = 0x00000004 # macro -NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION = 0x00000005 # macro -NV_PFAULT_FAULT_TYPE_RO_VIOLATION = 0x00000006 # macro -NV_PFAULT_FAULT_TYPE_WO_VIOLATION = 0x00000007 # macro -NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION = 0x00000008 # macro -NV_PFAULT_FAULT_TYPE_WORK_CREATION = 0x00000009 # macro -NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE = 0x0000000a # macro -NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE = 0x0000000b # macro -NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND = 0x0000000c # macro -NV_PFAULT_FAULT_TYPE_REGION_VIOLATION = 0x0000000d # macro -NV_PFAULT_FAULT_TYPE_POISONED = 0x0000000e # macro -NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION = 0x0000000f # macro -# NV_PFAULT_CLIENT = 14 : 8 # macro -NV_PFAULT_CLIENT_GPC_T1_0 = 0x00000000 # macro -NV_PFAULT_CLIENT_GPC_T1_1 = 0x00000001 # macro -NV_PFAULT_CLIENT_GPC_T1_2 = 0x00000002 # macro -NV_PFAULT_CLIENT_GPC_T1_3 = 0x00000003 # macro -NV_PFAULT_CLIENT_GPC_T1_4 = 0x00000004 # macro -NV_PFAULT_CLIENT_GPC_T1_5 = 0x00000005 # macro -NV_PFAULT_CLIENT_GPC_T1_6 = 0x00000006 # macro -NV_PFAULT_CLIENT_GPC_T1_7 = 0x00000007 # macro -NV_PFAULT_CLIENT_GPC_PE_0 = 0x00000008 # macro -NV_PFAULT_CLIENT_GPC_PE_1 = 0x00000009 # macro -NV_PFAULT_CLIENT_GPC_PE_2 = 0x0000000A # macro -NV_PFAULT_CLIENT_GPC_PE_3 = 0x0000000B # macro -NV_PFAULT_CLIENT_GPC_PE_4 = 0x0000000C # macro -NV_PFAULT_CLIENT_GPC_PE_5 = 0x0000000D # macro -NV_PFAULT_CLIENT_GPC_PE_6 = 0x0000000E # macro -NV_PFAULT_CLIENT_GPC_PE_7 = 0x0000000F # macro -NV_PFAULT_CLIENT_GPC_RAST = 0x00000010 # macro -NV_PFAULT_CLIENT_GPC_GCC = 0x00000011 # macro -NV_PFAULT_CLIENT_GPC_GPCCS = 0x00000012 # macro -NV_PFAULT_CLIENT_GPC_PROP_0 = 0x00000013 # macro -NV_PFAULT_CLIENT_GPC_PROP_1 = 0x00000014 # macro -NV_PFAULT_CLIENT_GPC_PROP_2 = 0x00000015 # macro -NV_PFAULT_CLIENT_GPC_PROP_3 = 0x00000016 # macro -NV_PFAULT_CLIENT_GPC_T1_8 = 0x00000021 # macro -NV_PFAULT_CLIENT_GPC_T1_9 = 0x00000022 # macro -NV_PFAULT_CLIENT_GPC_T1_10 = 0x00000023 # macro -NV_PFAULT_CLIENT_GPC_T1_11 = 0x00000024 # macro -NV_PFAULT_CLIENT_GPC_T1_12 = 0x00000025 # macro -NV_PFAULT_CLIENT_GPC_T1_13 = 0x00000026 # macro -NV_PFAULT_CLIENT_GPC_T1_14 = 0x00000027 # macro -NV_PFAULT_CLIENT_GPC_T1_15 = 0x00000028 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_0 = 0x00000029 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_1 = 0x0000002A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_2 = 0x0000002B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_3 = 0x0000002C # macro -NV_PFAULT_CLIENT_GPC_TPCCS_4 = 0x0000002D # macro -NV_PFAULT_CLIENT_GPC_TPCCS_5 = 0x0000002E # macro -NV_PFAULT_CLIENT_GPC_TPCCS_6 = 0x0000002F # macro -NV_PFAULT_CLIENT_GPC_TPCCS_7 = 0x00000030 # macro -NV_PFAULT_CLIENT_GPC_PE_8 = 0x00000031 # macro -NV_PFAULT_CLIENT_GPC_PE_9 = 0x00000032 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_8 = 0x00000033 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_9 = 0x00000034 # macro -NV_PFAULT_CLIENT_GPC_T1_16 = 0x00000035 # macro -NV_PFAULT_CLIENT_GPC_T1_17 = 0x00000036 # macro -NV_PFAULT_CLIENT_GPC_T1_18 = 0x00000037 # macro -NV_PFAULT_CLIENT_GPC_T1_19 = 0x00000038 # macro -NV_PFAULT_CLIENT_GPC_PE_10 = 0x00000039 # macro -NV_PFAULT_CLIENT_GPC_PE_11 = 0x0000003A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_10 = 0x0000003B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_11 = 0x0000003C # macro -NV_PFAULT_CLIENT_GPC_T1_20 = 0x0000003D # macro -NV_PFAULT_CLIENT_GPC_T1_21 = 0x0000003E # macro -NV_PFAULT_CLIENT_GPC_T1_22 = 0x0000003F # macro -NV_PFAULT_CLIENT_GPC_T1_23 = 0x00000040 # macro -NV_PFAULT_CLIENT_GPC_PE_12 = 0x00000041 # macro -NV_PFAULT_CLIENT_GPC_PE_13 = 0x00000042 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_12 = 0x00000043 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_13 = 0x00000044 # macro -NV_PFAULT_CLIENT_GPC_T1_24 = 0x00000045 # macro -NV_PFAULT_CLIENT_GPC_T1_25 = 0x00000046 # macro -NV_PFAULT_CLIENT_GPC_T1_26 = 0x00000047 # macro -NV_PFAULT_CLIENT_GPC_T1_27 = 0x00000048 # macro -NV_PFAULT_CLIENT_GPC_PE_14 = 0x00000049 # macro -NV_PFAULT_CLIENT_GPC_PE_15 = 0x0000004A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_14 = 0x0000004B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_15 = 0x0000004C # macro -NV_PFAULT_CLIENT_GPC_T1_28 = 0x0000004D # macro -NV_PFAULT_CLIENT_GPC_T1_29 = 0x0000004E # macro -NV_PFAULT_CLIENT_GPC_T1_30 = 0x0000004F # macro -NV_PFAULT_CLIENT_GPC_T1_31 = 0x00000050 # macro -NV_PFAULT_CLIENT_GPC_PE_16 = 0x00000051 # macro -NV_PFAULT_CLIENT_GPC_PE_17 = 0x00000052 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_16 = 0x00000053 # macro -NV_PFAULT_CLIENT_GPC_TPCCS_17 = 0x00000054 # macro -NV_PFAULT_CLIENT_GPC_T1_32 = 0x00000055 # macro -NV_PFAULT_CLIENT_GPC_T1_33 = 0x00000056 # macro -NV_PFAULT_CLIENT_GPC_T1_34 = 0x00000057 # macro -NV_PFAULT_CLIENT_GPC_T1_35 = 0x00000058 # macro -NV_PFAULT_CLIENT_GPC_PE_18 = 0x00000059 # macro -NV_PFAULT_CLIENT_GPC_PE_19 = 0x0000005A # macro -NV_PFAULT_CLIENT_GPC_TPCCS_18 = 0x0000005B # macro -NV_PFAULT_CLIENT_GPC_TPCCS_19 = 0x0000005C # macro -NV_PFAULT_CLIENT_GPC_T1_36 = 0x0000005D # macro -NV_PFAULT_CLIENT_GPC_T1_37 = 0x0000005E # macro -NV_PFAULT_CLIENT_GPC_T1_38 = 0x0000005F # macro -NV_PFAULT_CLIENT_GPC_T1_39 = 0x00000060 # macro -NV_PFAULT_CLIENT_GPC_ROP_0 = 0x00000070 # macro -NV_PFAULT_CLIENT_GPC_ROP_1 = 0x00000071 # macro -NV_PFAULT_CLIENT_GPC_ROP_2 = 0x00000072 # macro -NV_PFAULT_CLIENT_GPC_ROP_3 = 0x00000073 # macro -NV_PFAULT_CLIENT_GPC_GPM = 0x00000017 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 = 0x00000018 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 = 0x00000019 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 = 0x0000001A # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 = 0x0000001B # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 = 0x0000001C # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 = 0x0000001D # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 = 0x0000001E # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 = 0x0000001F # macro -NV_PFAULT_CLIENT_GPC_RGG_UTLB = 0x00000020 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 = 0x00000031 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 = 0x00000032 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 = 0x00000033 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 = 0x00000034 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 = 0x00000035 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 = 0x00000036 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 = 0x00000037 # macro -NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 = 0x00000038 # macro -NV_PFAULT_CLIENT_HUB_VIP = 0x00000000 # macro -NV_PFAULT_CLIENT_HUB_CE0 = 0x00000001 # macro -NV_PFAULT_CLIENT_HUB_CE1 = 0x00000002 # macro -NV_PFAULT_CLIENT_HUB_DNISO = 0x00000003 # macro -NV_PFAULT_CLIENT_HUB_DISPNISO = 0x00000003 # macro -NV_PFAULT_CLIENT_HUB_FE0 = 0x00000004 # macro -NV_PFAULT_CLIENT_HUB_FE = 0x00000004 # macro -NV_PFAULT_CLIENT_HUB_FECS0 = 0x00000005 # macro -NV_PFAULT_CLIENT_HUB_FECS = 0x00000005 # macro -NV_PFAULT_CLIENT_HUB_HOST = 0x00000006 # macro -NV_PFAULT_CLIENT_HUB_HOST_CPU = 0x00000007 # macro -NV_PFAULT_CLIENT_HUB_HOST_CPU_NB = 0x00000008 # macro -NV_PFAULT_CLIENT_HUB_ISO = 0x00000009 # macro -NV_PFAULT_CLIENT_HUB_MMU = 0x0000000A # macro -NV_PFAULT_CLIENT_HUB_NVDEC0 = 0x0000000B # macro -NV_PFAULT_CLIENT_HUB_NVDEC = 0x0000000B # macro -NV_PFAULT_CLIENT_HUB_NVENC1 = 0x0000000D # macro -NV_PFAULT_CLIENT_HUB_NISO = 0x0000000E # macro -NV_PFAULT_CLIENT_HUB_ACTRS = 0x0000000E # macro -NV_PFAULT_CLIENT_HUB_P2P = 0x0000000F # macro -NV_PFAULT_CLIENT_HUB_PD = 0x00000010 # macro -NV_PFAULT_CLIENT_HUB_PERF0 = 0x00000011 # macro -NV_PFAULT_CLIENT_HUB_PERF = 0x00000011 # macro -NV_PFAULT_CLIENT_HUB_PMU = 0x00000012 # macro -NV_PFAULT_CLIENT_HUB_RASTERTWOD = 0x00000013 # macro -NV_PFAULT_CLIENT_HUB_SCC = 0x00000014 # macro -NV_PFAULT_CLIENT_HUB_SCC_NB = 0x00000015 # macro -NV_PFAULT_CLIENT_HUB_SEC = 0x00000016 # macro -NV_PFAULT_CLIENT_HUB_SSYNC = 0x00000017 # macro -NV_PFAULT_CLIENT_HUB_GRCOPY = 0x00000018 # macro -NV_PFAULT_CLIENT_HUB_CE2 = 0x00000018 # macro -NV_PFAULT_CLIENT_HUB_XV = 0x00000019 # macro -NV_PFAULT_CLIENT_HUB_MMU_NB = 0x0000001A # macro -NV_PFAULT_CLIENT_HUB_NVENC0 = 0x0000001B # macro -NV_PFAULT_CLIENT_HUB_NVENC = 0x0000001B # macro -NV_PFAULT_CLIENT_HUB_DFALCON = 0x0000001C # macro -NV_PFAULT_CLIENT_HUB_SKED0 = 0x0000001D # macro -NV_PFAULT_CLIENT_HUB_SKED = 0x0000001D # macro -NV_PFAULT_CLIENT_HUB_AFALCON = 0x0000001E # macro -NV_PFAULT_CLIENT_HUB_DONT_CARE = 0x0000001F # macro -NV_PFAULT_CLIENT_HUB_HSCE0 = 0x00000020 # macro -NV_PFAULT_CLIENT_HUB_HSCE1 = 0x00000021 # macro -NV_PFAULT_CLIENT_HUB_HSCE2 = 0x00000022 # macro -NV_PFAULT_CLIENT_HUB_HSCE3 = 0x00000023 # macro -NV_PFAULT_CLIENT_HUB_HSCE4 = 0x00000024 # macro -NV_PFAULT_CLIENT_HUB_HSCE5 = 0x00000025 # macro -NV_PFAULT_CLIENT_HUB_HSCE6 = 0x00000026 # macro -NV_PFAULT_CLIENT_HUB_HSCE7 = 0x00000027 # macro -NV_PFAULT_CLIENT_HUB_HSCE8 = 0x00000028 # macro -NV_PFAULT_CLIENT_HUB_HSCE9 = 0x00000029 # macro -NV_PFAULT_CLIENT_HUB_HSHUB = 0x0000002A # macro -NV_PFAULT_CLIENT_HUB_PTP_X0 = 0x0000002B # macro -NV_PFAULT_CLIENT_HUB_PTP_X1 = 0x0000002C # macro -NV_PFAULT_CLIENT_HUB_PTP_X2 = 0x0000002D # macro -NV_PFAULT_CLIENT_HUB_PTP_X3 = 0x0000002E # macro -NV_PFAULT_CLIENT_HUB_PTP_X4 = 0x0000002F # macro -NV_PFAULT_CLIENT_HUB_PTP_X5 = 0x00000030 # macro -NV_PFAULT_CLIENT_HUB_PTP_X6 = 0x00000031 # macro -NV_PFAULT_CLIENT_HUB_PTP_X7 = 0x00000032 # macro -NV_PFAULT_CLIENT_HUB_NVENC2 = 0x00000033 # macro -NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 = 0x00000034 # macro -NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 = 0x00000035 # macro -NV_PFAULT_CLIENT_HUB_DWBIF = 0x00000036 # macro -NV_PFAULT_CLIENT_HUB_FBFALCON = 0x00000037 # macro -NV_PFAULT_CLIENT_HUB_CE_SHIM = 0x00000038 # macro -NV_PFAULT_CLIENT_HUB_GSP = 0x00000039 # macro -NV_PFAULT_CLIENT_HUB_NVDEC1 = 0x0000003A # macro -NV_PFAULT_CLIENT_HUB_NVDEC2 = 0x0000003B # macro -NV_PFAULT_CLIENT_HUB_NVJPG0 = 0x0000003C # macro -NV_PFAULT_CLIENT_HUB_NVDEC3 = 0x0000003D # macro -NV_PFAULT_CLIENT_HUB_NVDEC4 = 0x0000003E # macro -NV_PFAULT_CLIENT_HUB_OFA0 = 0x0000003F # macro -NV_PFAULT_CLIENT_HUB_HSCE10 = 0x00000040 # macro -NV_PFAULT_CLIENT_HUB_HSCE11 = 0x00000041 # macro -NV_PFAULT_CLIENT_HUB_HSCE12 = 0x00000042 # macro -NV_PFAULT_CLIENT_HUB_HSCE13 = 0x00000043 # macro -NV_PFAULT_CLIENT_HUB_HSCE14 = 0x00000044 # macro -NV_PFAULT_CLIENT_HUB_HSCE15 = 0x00000045 # macro -NV_PFAULT_CLIENT_HUB_PTP_X8 = 0x00000046 # macro -NV_PFAULT_CLIENT_HUB_PTP_X9 = 0x00000047 # macro -NV_PFAULT_CLIENT_HUB_PTP_X10 = 0x00000048 # macro -NV_PFAULT_CLIENT_HUB_PTP_X11 = 0x00000049 # macro -NV_PFAULT_CLIENT_HUB_PTP_X12 = 0x0000004A # macro -NV_PFAULT_CLIENT_HUB_PTP_X13 = 0x0000004B # macro -NV_PFAULT_CLIENT_HUB_PTP_X14 = 0x0000004C # macro -NV_PFAULT_CLIENT_HUB_PTP_X15 = 0x0000004D # macro -NV_PFAULT_CLIENT_HUB_FE1 = 0x0000004E # macro -NV_PFAULT_CLIENT_HUB_FE2 = 0x0000004F # macro -NV_PFAULT_CLIENT_HUB_FE3 = 0x00000050 # macro -NV_PFAULT_CLIENT_HUB_FE4 = 0x00000051 # macro -NV_PFAULT_CLIENT_HUB_FE5 = 0x00000052 # macro -NV_PFAULT_CLIENT_HUB_FE6 = 0x00000053 # macro -NV_PFAULT_CLIENT_HUB_FE7 = 0x00000054 # macro -NV_PFAULT_CLIENT_HUB_FECS1 = 0x00000055 # macro -NV_PFAULT_CLIENT_HUB_FECS2 = 0x00000056 # macro -NV_PFAULT_CLIENT_HUB_FECS3 = 0x00000057 # macro -NV_PFAULT_CLIENT_HUB_FECS4 = 0x00000058 # macro -NV_PFAULT_CLIENT_HUB_FECS5 = 0x00000059 # macro -NV_PFAULT_CLIENT_HUB_FECS6 = 0x0000005A # macro -NV_PFAULT_CLIENT_HUB_FECS7 = 0x0000005B # macro -NV_PFAULT_CLIENT_HUB_SKED1 = 0x0000005C # macro -NV_PFAULT_CLIENT_HUB_SKED2 = 0x0000005D # macro -NV_PFAULT_CLIENT_HUB_SKED3 = 0x0000005E # macro -NV_PFAULT_CLIENT_HUB_SKED4 = 0x0000005F # macro -NV_PFAULT_CLIENT_HUB_SKED5 = 0x00000060 # macro -NV_PFAULT_CLIENT_HUB_SKED6 = 0x00000061 # macro -NV_PFAULT_CLIENT_HUB_SKED7 = 0x00000062 # macro -NV_PFAULT_CLIENT_HUB_ESC = 0x00000063 # macro -# NV_PFAULT_ACCESS_TYPE = 19 : 16 # macro -NV_PFAULT_ACCESS_TYPE_READ = 0x00000000 # macro -NV_PFAULT_ACCESS_TYPE_WRITE = 0x00000001 # macro -NV_PFAULT_ACCESS_TYPE_ATOMIC = 0x00000002 # macro -NV_PFAULT_ACCESS_TYPE_PREFETCH = 0x00000003 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_READ = 0x00000000 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_WRITE = 0x00000001 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC = 0x00000002 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 0x00000002 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH = 0x00000003 # macro -NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 0x00000004 # macro -NV_PFAULT_ACCESS_TYPE_PHYS_READ = 0x00000008 # macro -NV_PFAULT_ACCESS_TYPE_PHYS_WRITE = 0x00000009 # macro -NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC = 0x0000000a # macro -NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH = 0x0000000b # macro -# NV_PFAULT_MMU_CLIENT_TYPE = 20 : 20 # macro -NV_PFAULT_MMU_CLIENT_TYPE_GPC = 0x00000000 # macro -NV_PFAULT_MMU_CLIENT_TYPE_HUB = 0x00000001 # macro -# NV_PFAULT_GPC_ID = 28 : 24 # macro -# NV_PFAULT_PROTECTED_MODE = 29 : 29 # macro -# NV_PFAULT_REPLAYABLE_FAULT_EN = 30 : 30 # macro -# NV_PFAULT_VALID = 31 : 31 # macro -NV_ESCAPE_H_INCLUDED = True # macro -NV_ESC_RM_ALLOC_MEMORY = 0x27 # macro -NV_ESC_RM_ALLOC_OBJECT = 0x28 # macro -NV_ESC_RM_FREE = 0x29 # macro -NV_ESC_RM_CONTROL = 0x2A # macro -NV_ESC_RM_ALLOC = 0x2B # macro -NV_ESC_RM_CONFIG_GET = 0x32 # macro -NV_ESC_RM_CONFIG_SET = 0x33 # macro -NV_ESC_RM_DUP_OBJECT = 0x34 # macro -NV_ESC_RM_SHARE = 0x35 # macro -NV_ESC_RM_CONFIG_GET_EX = 0x37 # macro -NV_ESC_RM_CONFIG_SET_EX = 0x38 # macro -NV_ESC_RM_I2C_ACCESS = 0x39 # macro -NV_ESC_RM_IDLE_CHANNELS = 0x41 # macro -NV_ESC_RM_VID_HEAP_CONTROL = 0x4A # macro -NV_ESC_RM_ACCESS_REGISTRY = 0x4D # macro -NV_ESC_RM_MAP_MEMORY = 0x4E # macro -NV_ESC_RM_UNMAP_MEMORY = 0x4F # macro -NV_ESC_RM_GET_EVENT_DATA = 0x52 # macro -NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54 # macro -NV_ESC_RM_ADD_VBLANK_CALLBACK = 0x56 # macro -NV_ESC_RM_MAP_MEMORY_DMA = 0x57 # macro -NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58 # macro -NV_ESC_RM_BIND_CONTEXT_DMA = 0x59 # macro -NV_ESC_RM_EXPORT_OBJECT_TO_FD = 0x5C # macro -NV_ESC_RM_IMPORT_OBJECT_FROM_FD = 0x5D # macro -NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5E # macro -NV_ESC_RM_LOCKLESS_DIAGNOSTIC = 0x5F # macro -NV_IOCTL_H = True # macro -NV_RM_API_VERSION_STRING_LENGTH = 64 # macro -NV_RM_API_VERSION_CMD_STRICT = 0 # macro -NV_RM_API_VERSION_CMD_RELAXED = '1' # macro -NV_RM_API_VERSION_CMD_QUERY = '2' # macro -NV_RM_API_VERSION_REPLY_UNRECOGNIZED = 0 # macro -NV_RM_API_VERSION_REPLY_RECOGNIZED = 1 # macro -NV_DMABUF_EXPORT_MAX_HANDLES = 128 # macro -NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = 0 # macro -NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = 1 # macro -class struct_c__SA_nv_pci_info_t(Structure): - pass - -struct_c__SA_nv_pci_info_t._pack_ = 1 # source:False -struct_c__SA_nv_pci_info_t._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('slot', ctypes.c_ubyte), - ('function', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('vendor_id', ctypes.c_uint16), - ('device_id', ctypes.c_uint16), -] - -nv_pci_info_t = struct_c__SA_nv_pci_info_t -class struct_nv_ioctl_xfer(Structure): - pass - -struct_nv_ioctl_xfer._pack_ = 1 # source:False + ('uuid', (NvU8 * 16)), +] +UVM_REGION_COMMIT_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('streamId', UvmStream), + ('gpuUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_REGION_DECOMMIT_PARAMS(Struct): pass +UVM_REGION_DECOMMIT_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_REGION_SET_STREAM_PARAMS(Struct): pass +UVM_REGION_SET_STREAM_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('newStreamId', UvmStream), + ('gpuUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_SET_STREAM_RUNNING_PARAMS(Struct): pass +UVM_SET_STREAM_RUNNING_PARAMS._fields_ = [ + ('streamId', UvmStream), + ('rmStatus', NV_STATUS), +] +class UVM_SET_STREAM_STOPPED_PARAMS(Struct): pass +UVM_SET_STREAM_STOPPED_PARAMS._fields_ = [ + ('streamIdArray', (UvmStream * 32)), + ('nStreams', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_RUN_TEST_PARAMS(Struct): pass +class UVM_RUN_TEST_PARAMS_multiGpu(Struct): pass +UVM_RUN_TEST_PARAMS_multiGpu._fields_ = [ + ('peerGpuUuid', NvProcessorUuid), + ('peerId', NvU32), +] +UVM_RUN_TEST_PARAMS._fields_ = [ + ('gpuUuid', NvProcessorUuid), + ('test', NvU32), + ('multiGpu', UVM_RUN_TEST_PARAMS_multiGpu), + ('rmStatus', NV_STATUS), +] +class UVM_ADD_SESSION_PARAMS(Struct): pass +NvS32 = ctypes.c_int32 +UVM_ADD_SESSION_PARAMS._fields_ = [ + ('pidTarget', NvU32), + ('countersBaseAddress', NvP64), + ('sessionIndex', NvS32), + ('rmStatus', NV_STATUS), +] +class UVM_REMOVE_SESSION_PARAMS(Struct): pass +UVM_REMOVE_SESSION_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('rmStatus', NV_STATUS), +] +class UVM_ENABLE_COUNTERS_PARAMS(Struct): pass +class UvmCounterConfig(Struct): pass +UvmCounterConfig._fields_ = [ + ('scope', NvU32), + ('name', NvU32), + ('gpuid', NvProcessorUuid), + ('state', NvU32), +] +UVM_ENABLE_COUNTERS_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('config', (UvmCounterConfig * 32)), + ('count', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_MAP_COUNTER_PARAMS(Struct): pass +UVM_MAP_COUNTER_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('scope', NvU32), + ('counterName', NvU32), + ('gpuUuid', NvProcessorUuid), + ('addr', NvP64), + ('rmStatus', NV_STATUS), +] +class UVM_CREATE_EVENT_QUEUE_PARAMS(Struct): pass +UVM_CREATE_EVENT_QUEUE_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('eventQueueIndex', NvU32), + ('queueSize', NvU64), + ('notificationCount', NvU64), + ('timeStampType', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_REMOVE_EVENT_QUEUE_PARAMS(Struct): pass +UVM_REMOVE_EVENT_QUEUE_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('eventQueueIndex', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_MAP_EVENT_QUEUE_PARAMS(Struct): pass +UVM_MAP_EVENT_QUEUE_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('eventQueueIndex', NvU32), + ('userRODataAddr', NvP64), + ('userRWDataAddr', NvP64), + ('readIndexAddr', NvP64), + ('writeIndexAddr', NvP64), + ('queueBufferAddr', NvP64), + ('rmStatus', NV_STATUS), +] +class UVM_EVENT_CTRL_PARAMS(Struct): pass +UVM_EVENT_CTRL_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('eventQueueIndex', NvU32), + ('eventType', NvS32), + ('enable', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_REGISTER_MPS_SERVER_PARAMS(Struct): pass +UVM_REGISTER_MPS_SERVER_PARAMS._fields_ = [ + ('gpuUuidArray', (NvProcessorUuid * 32)), + ('numGpus', NvU32), + ('serverId', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_REGISTER_MPS_CLIENT_PARAMS(Struct): pass +UVM_REGISTER_MPS_CLIENT_PARAMS._fields_ = [ + ('serverId', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_GET_GPU_UUID_TABLE_PARAMS(Struct): pass +UVM_GET_GPU_UUID_TABLE_PARAMS._fields_ = [ + ('gpuUuidArray', (NvProcessorUuid * 32)), + ('validCount', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_CREATE_RANGE_GROUP_PARAMS(Struct): pass +UVM_CREATE_RANGE_GROUP_PARAMS._fields_ = [ + ('rangeGroupId', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_DESTROY_RANGE_GROUP_PARAMS(Struct): pass +UVM_DESTROY_RANGE_GROUP_PARAMS._fields_ = [ + ('rangeGroupId', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_REGISTER_GPU_VASPACE_PARAMS(Struct): pass +UVM_REGISTER_GPU_VASPACE_PARAMS._fields_ = [ + ('gpuUuid', NvProcessorUuid), + ('rmCtrlFd', NvS32), + ('hClient', NvHandle), + ('hVaSpace', NvHandle), + ('rmStatus', NV_STATUS), +] +class UVM_UNREGISTER_GPU_VASPACE_PARAMS(Struct): pass +UVM_UNREGISTER_GPU_VASPACE_PARAMS._fields_ = [ + ('gpuUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_REGISTER_CHANNEL_PARAMS(Struct): pass +UVM_REGISTER_CHANNEL_PARAMS._fields_ = [ + ('gpuUuid', NvProcessorUuid), + ('rmCtrlFd', NvS32), + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('base', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_UNREGISTER_CHANNEL_PARAMS(Struct): pass +UVM_UNREGISTER_CHANNEL_PARAMS._fields_ = [ + ('gpuUuid', NvProcessorUuid), + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('rmStatus', NV_STATUS), +] +class UVM_ENABLE_PEER_ACCESS_PARAMS(Struct): pass +UVM_ENABLE_PEER_ACCESS_PARAMS._fields_ = [ + ('gpuUuidA', NvProcessorUuid), + ('gpuUuidB', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_DISABLE_PEER_ACCESS_PARAMS(Struct): pass +UVM_DISABLE_PEER_ACCESS_PARAMS._fields_ = [ + ('gpuUuidA', NvProcessorUuid), + ('gpuUuidB', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_SET_RANGE_GROUP_PARAMS(Struct): pass +UVM_SET_RANGE_GROUP_PARAMS._fields_ = [ + ('rangeGroupId', NvU64), + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_MAP_EXTERNAL_ALLOCATION_PARAMS(Struct): pass +class UvmGpuMappingAttributes(Struct): pass +UvmGpuMappingAttributes._fields_ = [ + ('gpuUuid', NvProcessorUuid), + ('gpuMappingType', NvU32), + ('gpuCachingType', NvU32), + ('gpuFormatType', NvU32), + ('gpuElementBits', NvU32), + ('gpuCompressionType', NvU32), +] +UVM_MAP_EXTERNAL_ALLOCATION_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('offset', NvU64), + ('perGpuAttributes', (UvmGpuMappingAttributes * 256)), + ('gpuAttributesCount', NvU64), + ('rmCtrlFd', NvS32), + ('hClient', NvU32), + ('hMemory', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_FREE_PARAMS(Struct): pass +UVM_FREE_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_MEM_MAP_PARAMS(Struct): pass +UVM_MEM_MAP_PARAMS._fields_ = [ + ('regionBase', NvP64), + ('regionLength', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_DEBUG_ACCESS_MEMORY_PARAMS(Struct): pass +UVM_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [ + ('sessionIndex', NvS32), + ('baseAddress', NvU64), + ('sizeInBytes', NvU64), + ('accessType', NvU32), + ('buffer', NvU64), + ('isBitmaskSet', NvBool), + ('bitmask', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_REGISTER_GPU_PARAMS(Struct): pass +UVM_REGISTER_GPU_PARAMS._fields_ = [ + ('gpu_uuid', NvProcessorUuid), + ('numaEnabled', NvBool), + ('numaNodeId', NvS32), + ('rmCtrlFd', NvS32), + ('hClient', NvHandle), + ('hSmcPartRef', NvHandle), + ('rmStatus', NV_STATUS), +] +class UVM_UNREGISTER_GPU_PARAMS(Struct): pass +UVM_UNREGISTER_GPU_PARAMS._fields_ = [ + ('gpu_uuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_PAGEABLE_MEM_ACCESS_PARAMS(Struct): pass +UVM_PAGEABLE_MEM_ACCESS_PARAMS._fields_ = [ + ('pageableMemAccess', NvBool), + ('rmStatus', NV_STATUS), +] +class UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS(Struct): pass +UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [ + ('rangeGroupIds', (NvU64 * 32)), + ('numGroupIds', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS(Struct): pass +UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [ + ('rangeGroupIds', (NvU64 * 32)), + ('numGroupIds', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_SET_PREFERRED_LOCATION_PARAMS(Struct): pass +UVM_SET_PREFERRED_LOCATION_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('preferredLocation', NvProcessorUuid), + ('preferredCpuNumaNode', NvS32), + ('rmStatus', NV_STATUS), +] +class UVM_UNSET_PREFERRED_LOCATION_PARAMS(Struct): pass +UVM_UNSET_PREFERRED_LOCATION_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_ENABLE_READ_DUPLICATION_PARAMS(Struct): pass +UVM_ENABLE_READ_DUPLICATION_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_DISABLE_READ_DUPLICATION_PARAMS(Struct): pass +UVM_DISABLE_READ_DUPLICATION_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_SET_ACCESSED_BY_PARAMS(Struct): pass +UVM_SET_ACCESSED_BY_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('accessedByUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_UNSET_ACCESSED_BY_PARAMS(Struct): pass +UVM_UNSET_ACCESSED_BY_PARAMS._fields_ = [ + ('requestedBase', NvU64), + ('length', NvU64), + ('accessedByUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_MIGRATE_PARAMS(Struct): pass +UVM_MIGRATE_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('destinationUuid', NvProcessorUuid), + ('flags', NvU32), + ('semaphoreAddress', NvU64), + ('semaphorePayload', NvU32), + ('cpuNumaNode', NvS32), + ('userSpaceStart', NvU64), + ('userSpaceLength', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_MIGRATE_RANGE_GROUP_PARAMS(Struct): pass +UVM_MIGRATE_RANGE_GROUP_PARAMS._fields_ = [ + ('rangeGroupId', NvU64), + ('destinationUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Struct): pass +UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [ + ('gpu_uuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Struct): pass +UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [ + ('gpu_uuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS(Struct): pass +UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS._fields_ = [ + ('queueBuffer', NvU64), + ('queueBufferSize', NvU64), + ('controlBuffer', NvU64), + ('processor', NvProcessorUuid), + ('allProcessors', NvU32), + ('uvmFd', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS(Struct): pass +UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS._fields_ = [ + ('notificationThreshold', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS(Struct): pass +UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS._fields_ = [ + ('eventTypeFlags', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS(Struct): pass +UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS._fields_ = [ + ('eventTypeFlags', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_ENABLE_COUNTERS_PARAMS(Struct): pass +UVM_TOOLS_ENABLE_COUNTERS_PARAMS._fields_ = [ + ('counterTypeFlags', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_DISABLE_COUNTERS_PARAMS(Struct): pass +UVM_TOOLS_DISABLE_COUNTERS_PARAMS._fields_ = [ + ('counterTypeFlags', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS(Struct): pass +UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS._fields_ = [ + ('buffer', NvU64), + ('size', NvU64), + ('targetVa', NvU64), + ('bytesRead', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS(Struct): pass +UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS._fields_ = [ + ('buffer', NvU64), + ('size', NvU64), + ('targetVa', NvU64), + ('bytesWritten', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS(Struct): pass +UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS._fields_ = [ + ('tablePtr', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS(Struct): pass +UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('gpuUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_UNMAP_EXTERNAL_PARAMS(Struct): pass +UVM_UNMAP_EXTERNAL_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('gpuUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_TOOLS_FLUSH_EVENTS_PARAMS(Struct): pass +UVM_TOOLS_FLUSH_EVENTS_PARAMS._fields_ = [ + ('rmStatus', NV_STATUS), +] +class UVM_ALLOC_SEMAPHORE_POOL_PARAMS(Struct): pass +UVM_ALLOC_SEMAPHORE_POOL_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('perGpuAttributes', (UvmGpuMappingAttributes * 256)), + ('gpuAttributesCount', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS(Struct): pass +UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS._fields_ = [ + ('rmStatus', NV_STATUS), +] +class UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS(Struct): pass +UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS._fields_ = [ + ('gpu_uuid', NvProcessorUuid), + ('pageableMemAccess', NvBool), + ('rmStatus', NV_STATUS), +] +class UVM_POPULATE_PAGEABLE_PARAMS(Struct): pass +UVM_POPULATE_PAGEABLE_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('flags', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_VALIDATE_VA_RANGE_PARAMS(Struct): pass +UVM_VALIDATE_VA_RANGE_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_CREATE_EXTERNAL_RANGE_PARAMS(Struct): pass +UVM_CREATE_EXTERNAL_RANGE_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('rmStatus', NV_STATUS), +] +class UVM_MAP_EXTERNAL_SPARSE_PARAMS(Struct): pass +UVM_MAP_EXTERNAL_SPARSE_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('gpuUuid', NvProcessorUuid), + ('rmStatus', NV_STATUS), +] +class UVM_MM_INITIALIZE_PARAMS(Struct): pass +UVM_MM_INITIALIZE_PARAMS._fields_ = [ + ('uvmFd', NvS32), + ('rmStatus', NV_STATUS), +] +UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS = UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS +UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS = UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS +class UVM_ALLOC_DEVICE_P2P_PARAMS(Struct): pass +UVM_ALLOC_DEVICE_P2P_PARAMS._fields_ = [ + ('base', NvU64), + ('length', NvU64), + ('offset', NvU64), + ('gpuUuid', NvProcessorUuid), + ('rmCtrlFd', NvS32), + ('hClient', NvU32), + ('hMemory', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS(Struct): pass +UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS._fields_ = [ + ('rmStatus', NV_STATUS), +] +class UVM_IS_8_SUPPORTED_PARAMS(Struct): pass +UVM_IS_8_SUPPORTED_PARAMS._fields_ = [ + ('is8Supported', NvU32), + ('rmStatus', NV_STATUS), +] +class UVM_INITIALIZE_PARAMS(Struct): pass +UVM_INITIALIZE_PARAMS._fields_ = [ + ('flags', NvU64), + ('rmStatus', NV_STATUS), +] +class nv_pci_info_t(Struct): pass +NvU16 = ctypes.c_uint16 +nv_pci_info_t._fields_ = [ + ('domain', NvU32), + ('bus', NvU8), + ('slot', NvU8), + ('function', NvU8), + ('vendor_id', NvU16), + ('device_id', NvU16), +] +class struct_nv_ioctl_xfer(Struct): pass struct_nv_ioctl_xfer._fields_ = [ - ('cmd', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('ptr', ctypes.POINTER(None)), + ('cmd', NvU32), + ('size', NvU32), + ('ptr', NvP64), ] - nv_ioctl_xfer_t = struct_nv_ioctl_xfer -class struct_nv_ioctl_card_info(Structure): - pass - -struct_nv_ioctl_card_info._pack_ = 1 # source:False +class struct_nv_ioctl_card_info(Struct): pass struct_nv_ioctl_card_info._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pci_info', nv_pci_info_t), - ('gpu_id', ctypes.c_uint32), - ('interrupt_line', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('reg_address', ctypes.c_uint64), - ('reg_size', ctypes.c_uint64), - ('fb_address', ctypes.c_uint64), - ('fb_size', ctypes.c_uint64), - ('minor_number', ctypes.c_uint32), - ('dev_name', ctypes.c_ubyte * 10), - ('PADDING_2', ctypes.c_ubyte * 2), + ('valid', NvBool), + ('pci_info', nv_pci_info_t), + ('gpu_id', NvU32), + ('interrupt_line', NvU16), + ('reg_address', NvU64), + ('reg_size', NvU64), + ('fb_address', NvU64), + ('fb_size', NvU64), + ('minor_number', NvU32), + ('dev_name', (NvU8 * 10)), ] - nv_ioctl_card_info_t = struct_nv_ioctl_card_info -class struct_nv_ioctl_alloc_os_event(Structure): - pass - -struct_nv_ioctl_alloc_os_event._pack_ = 1 # source:False +class struct_nv_ioctl_alloc_os_event(Struct): pass struct_nv_ioctl_alloc_os_event._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('fd', ctypes.c_uint32), - ('Status', ctypes.c_uint32), + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('fd', NvU32), + ('Status', NvU32), ] - nv_ioctl_alloc_os_event_t = struct_nv_ioctl_alloc_os_event -class struct_nv_ioctl_free_os_event(Structure): - pass - -struct_nv_ioctl_free_os_event._pack_ = 1 # source:False +class struct_nv_ioctl_free_os_event(Struct): pass struct_nv_ioctl_free_os_event._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('fd', ctypes.c_uint32), - ('Status', ctypes.c_uint32), + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('fd', NvU32), + ('Status', NvU32), ] - nv_ioctl_free_os_event_t = struct_nv_ioctl_free_os_event -class struct_nv_ioctl_status_code(Structure): - pass - -struct_nv_ioctl_status_code._pack_ = 1 # source:False +class struct_nv_ioctl_status_code(Struct): pass struct_nv_ioctl_status_code._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('slot', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), + ('domain', NvU32), + ('bus', NvU8), + ('slot', NvU8), + ('status', NvU32), ] - nv_ioctl_status_code_t = struct_nv_ioctl_status_code -class struct_nv_ioctl_rm_api_version(Structure): - pass - -struct_nv_ioctl_rm_api_version._pack_ = 1 # source:False +class struct_nv_ioctl_rm_api_version(Struct): pass struct_nv_ioctl_rm_api_version._fields_ = [ - ('cmd', ctypes.c_uint32), - ('reply', ctypes.c_uint32), - ('versionString', ctypes.c_char * 64), + ('cmd', NvU32), + ('reply', NvU32), + ('versionString', (ctypes.c_char * 64)), ] - nv_ioctl_rm_api_version_t = struct_nv_ioctl_rm_api_version -class struct_nv_ioctl_query_device_intr(Structure): - pass - -struct_nv_ioctl_query_device_intr._pack_ = 1 # source:False +class struct_nv_ioctl_query_device_intr(Struct): pass struct_nv_ioctl_query_device_intr._fields_ = [ - ('intrStatus', ctypes.c_uint32), - ('status', ctypes.c_uint32), + ('intrStatus', NvU32), + ('status', NvU32), ] - nv_ioctl_query_device_intr = struct_nv_ioctl_query_device_intr -class struct_nv_ioctl_sys_params(Structure): - pass - -struct_nv_ioctl_sys_params._pack_ = 1 # source:False +class struct_nv_ioctl_sys_params(Struct): pass struct_nv_ioctl_sys_params._fields_ = [ - ('memblock_size', ctypes.c_uint64), + ('memblock_size', NvU64), ] - nv_ioctl_sys_params_t = struct_nv_ioctl_sys_params -class struct_nv_ioctl_register_fd(Structure): - pass - -struct_nv_ioctl_register_fd._pack_ = 1 # source:False +class struct_nv_ioctl_register_fd(Struct): pass struct_nv_ioctl_register_fd._fields_ = [ - ('ctl_fd', ctypes.c_int32), + ('ctl_fd', ctypes.c_int32), ] - nv_ioctl_register_fd_t = struct_nv_ioctl_register_fd -class struct_nv_ioctl_export_to_dma_buf_fd(Structure): - pass - -struct_nv_ioctl_export_to_dma_buf_fd._pack_ = 1 # source:False +class struct_nv_ioctl_export_to_dma_buf_fd(Struct): pass struct_nv_ioctl_export_to_dma_buf_fd._fields_ = [ - ('fd', ctypes.c_int32), - ('hClient', ctypes.c_uint32), - ('totalObjects', ctypes.c_uint32), - ('numObjects', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalSize', ctypes.c_uint64), - ('mappingType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('handles', ctypes.c_uint32 * 128), - ('PADDING_2', ctypes.c_ubyte * 4), - ('offsets', ctypes.c_uint64 * 128), - ('sizes', ctypes.c_uint64 * 128), - ('status', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), + ('fd', ctypes.c_int32), + ('hClient', NvHandle), + ('totalObjects', NvU32), + ('numObjects', NvU32), + ('index', NvU32), + ('totalSize', NvU64), + ('mappingType', NvU8), + ('handles', (NvHandle * 128)), + ('offsets', (NvU64 * 128)), + ('sizes', (NvU64 * 128)), + ('status', NvU32), ] - nv_ioctl_export_to_dma_buf_fd_t = struct_nv_ioctl_export_to_dma_buf_fd -class struct_nv_ioctl_wait_open_complete(Structure): - pass - -struct_nv_ioctl_wait_open_complete._pack_ = 1 # source:False +class struct_nv_ioctl_wait_open_complete(Struct): pass struct_nv_ioctl_wait_open_complete._fields_ = [ - ('rc', ctypes.c_int32), - ('adapterStatus', ctypes.c_uint32), + ('rc', ctypes.c_int32), + ('adapterStatus', NvU32), ] - nv_ioctl_wait_open_complete_t = struct_nv_ioctl_wait_open_complete -NV_IOCTL_NUMBERS_H = True # macro -NV_IOCTL_MAGIC = 'F' # macro -NV_IOCTL_BASE = 200 # macro -NV_ESC_CARD_INFO = (200+0) # macro -NV_ESC_REGISTER_FD = (200+1) # macro -NV_ESC_ALLOC_OS_EVENT = (200+6) # macro -NV_ESC_FREE_OS_EVENT = (200+7) # macro -NV_ESC_STATUS_CODE = (200+9) # macro -NV_ESC_CHECK_VERSION_STR = (200+10) # macro -NV_ESC_IOCTL_XFER_CMD = (200+11) # macro -NV_ESC_ATTACH_GPUS_TO_FD = (200+12) # macro -NV_ESC_QUERY_DEVICE_INTR = (200+13) # macro -NV_ESC_SYS_PARAMS = (200+14) # macro -NV_ESC_EXPORT_TO_DMABUF_FD = (200+17) # macro -NV_ESC_WAIT_OPEN_COMPLETE = (200+18) # macro -NV_IOCTL_NUMA_H = True # macro -# def __aligned(n): # macro -# return ((aligned(n))) -NV_ESC_NUMA_INFO = (200+15) # macro -NV_ESC_SET_NUMA_STATUS = (200+16) # macro -NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 # macro -NV_IOCTL_NUMA_STATUS_DISABLED = 0 # macro -NV_IOCTL_NUMA_STATUS_OFFLINE = 1 # macro -NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS = 2 # macro -NV_IOCTL_NUMA_STATUS_ONLINE = 3 # macro -NV_IOCTL_NUMA_STATUS_ONLINE_FAILED = 4 # macro -NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS = 5 # macro -NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED = 6 # macro -class struct_offline_addresses(Structure): - pass - -struct_offline_addresses._pack_ = 1 # source:False +class struct_offline_addresses(Struct): pass +uint64_t = ctypes.c_uint64 +uint32_t = ctypes.c_uint32 struct_offline_addresses._fields_ = [ - ('addresses', ctypes.c_uint64 * 64), - ('numEntries', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('addresses', (uint64_t * 64)), + ('numEntries', uint32_t), ] - nv_offline_addresses_t = struct_offline_addresses -class struct_nv_ioctl_numa_info(Structure): - pass - -struct_nv_ioctl_numa_info._pack_ = 1 # source:False +class struct_nv_ioctl_numa_info(Struct): pass +int32_t = ctypes.c_int32 +uint8_t = ctypes.c_ubyte struct_nv_ioctl_numa_info._fields_ = [ - ('nid', ctypes.c_int32), - ('status', ctypes.c_int32), - ('memblock_size', ctypes.c_uint64), - ('numa_mem_addr', ctypes.c_uint64), - ('numa_mem_size', ctypes.c_uint64), - ('use_auto_online', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('offline_addresses', nv_offline_addresses_t), + ('nid', int32_t), + ('status', int32_t), + ('memblock_size', uint64_t), + ('numa_mem_addr', uint64_t), + ('numa_mem_size', uint64_t), + ('use_auto_online', uint8_t), + ('offline_addresses', nv_offline_addresses_t), ] - nv_ioctl_numa_info_t = struct_nv_ioctl_numa_info -class struct_nv_ioctl_set_numa_status(Structure): - pass - -struct_nv_ioctl_set_numa_status._pack_ = 1 # source:False +class struct_nv_ioctl_set_numa_status(Struct): pass struct_nv_ioctl_set_numa_status._fields_ = [ - ('status', ctypes.c_int32), + ('status', int32_t), ] - nv_ioctl_set_numa_status_t = struct_nv_ioctl_set_numa_status -_NV_UNIX_NVOS_PARAMS_WRAPPERS_H_ = True # macro -NVOS_INCLUDED = True # macro -# NVOS04_FLAGS_CHANNEL_TYPE = 1 : 0 # macro -NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL = 0x00000001 # macro -NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL = 0x00000002 # macro -# NVOS04_FLAGS_VPR = 2 : 2 # macro -NVOS04_FLAGS_VPR_FALSE = 0x00000000 # macro -NVOS04_FLAGS_VPR_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CC_SECURE = 2 : 2 # macro -NVOS04_FLAGS_CC_SECURE_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CC_SECURE_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING = 3 : 3 # macro -NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE = 4 : 4 # macro -NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT = 0x00000000 # macro -NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE = 0x00000001 # macro -# NVOS04_FLAGS_PRIVILEGED_CHANNEL = 5 : 5 # macro -NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE = 0x00000000 # macro -NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING = 6 : 6 # macro -NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE = 0x00000000 # macro -NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE = 7 : 7 # macro -NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE = 10 : 8 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED = 11 : 11 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE = 20 : 12 # macro -# NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED = 21 : 21 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV = 22 : 22 # macro -NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER = 23 : 23 # macro -NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO = 24 : 24 # macro -NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL = 25 : 25 # macro -NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE = 0x00000000 # macro -NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT = 26 : 26 # macro -NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT = 27 : 27 # macro -NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE = 0x00000000 # macro -NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_GROUP_CHANNEL_THREAD = 29 : 28 # macro -NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT = 0x00000000 # macro -NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE = 0x00000001 # macro -NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO = 0x00000002 # macro -# NVOS04_FLAGS_MAP_CHANNEL = 30 : 30 # macro -NVOS04_FLAGS_MAP_CHANNEL_FALSE = 0x00000000 # macro -NVOS04_FLAGS_MAP_CHANNEL_TRUE = 0x00000001 # macro -# NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC = 31 : 31 # macro -NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE = 0x00000000 # macro -NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE = 0x00000001 # macro -CC_CHAN_ALLOC_IV_SIZE_DWORD = 3 # macro -CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8 # macro -NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID = (0x906f) # macro -FILE_DEVICE_NV = 0x00008000 # macro -NV_IOCTL_FCT_BASE = 0x00000800 # macro -NVOS_MAX_SUBDEVICES = 8 # macro -UNIFIED_NV_STATUS = 1 # macro -# NVOS_STATUS = NV_STATUS # macro -# NVOS_STATUS_SUCCESS = NV_OK # macro -# NVOS_STATUS_ERROR_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT # macro -# NVOS_STATUS_ERROR_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE # macro -# NVOS_STATUS_ERROR_GENERIC = NV_ERR_GENERIC # macro -# NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER # macro -# NVOS_STATUS_ERROR_ILLEGAL_ACTION = NV_ERR_ILLEGAL_ACTION # macro -# NVOS_STATUS_ERROR_IN_USE = NV_ERR_STATE_IN_USE # macro -# NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES # macro -# NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE # macro -# NVOS_STATUS_ERROR_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT # macro -# NVOS_STATUS_ERROR_INVALID_BASE = NV_ERR_INVALID_BASE # macro -# NVOS_STATUS_ERROR_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL # macro -# NVOS_STATUS_ERROR_INVALID_CLASS = NV_ERR_INVALID_CLASS # macro -# NVOS_STATUS_ERROR_INVALID_CLIENT = NV_ERR_INVALID_CLIENT # macro -# NVOS_STATUS_ERROR_INVALID_COMMAND = NV_ERR_INVALID_COMMAND # macro -# NVOS_STATUS_ERROR_INVALID_DATA = NV_ERR_INVALID_DATA # macro -# NVOS_STATUS_ERROR_INVALID_DEVICE = NV_ERR_INVALID_DEVICE # macro -# NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER # macro -# NVOS_STATUS_ERROR_INVALID_EVENT = NV_ERR_INVALID_EVENT # macro -# NVOS_STATUS_ERROR_INVALID_FLAGS = NV_ERR_INVALID_FLAGS # macro -# NVOS_STATUS_ERROR_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION # macro -# NVOS_STATUS_ERROR_INVALID_HEAP = NV_ERR_INVALID_HEAP # macro -# NVOS_STATUS_ERROR_INVALID_INDEX = NV_ERR_INVALID_INDEX # macro -# NVOS_STATUS_ERROR_INVALID_LIMIT = NV_ERR_INVALID_LIMIT # macro -# NVOS_STATUS_ERROR_INVALID_METHOD = NV_ERR_INVALID_METHOD # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER = NV_ERR_BUFFER_TOO_SMALL # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD # macro -# NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT # macro -# NVOS_STATUS_ERROR_INVALID_OFFSET = NV_ERR_INVALID_OFFSET # macro -# NVOS_STATUS_ERROR_INVALID_OWNER = NV_ERR_INVALID_OWNER # macro -# NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT # macro -# NVOS_STATUS_ERROR_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER # macro -# NVOS_STATUS_ERROR_INVALID_POINTER = NV_ERR_INVALID_POINTER # macro -# NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY # macro -# NVOS_STATUS_ERROR_INVALID_STATE = NV_ERR_INVALID_STATE # macro -# NVOS_STATUS_ERROR_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH # macro -# NVOS_STATUS_ERROR_INVALID_XLATE = NV_ERR_INVALID_XLATE # macro -# NVOS_STATUS_ERROR_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING # macro -# NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES # macro -# NVOS_STATUS_ERROR_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED # macro -# NVOS_STATUS_ERROR_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM # macro -# NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH # macro -# NVOS_STATUS_ERROR_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT # macro -# NVOS_STATUS_ERROR_TIMEOUT = NV_ERR_TIMEOUT # macro -# NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES # macro -# NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED # macro -# NVOS_STATUS_ERROR_INVALID_OPERATION = NV_ERR_INVALID_OPERATION # macro -# NVOS_STATUS_ERROR_NOT_COMPATIBLE = NV_ERR_NOT_COMPATIBLE # macro -# NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED = NV_WARN_MORE_PROCESSING_REQUIRED # macro -# NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS = NV_ERR_INSUFFICIENT_PERMISSIONS # macro -# NVOS_STATUS_ERROR_TIMEOUT_RETRY = NV_ERR_TIMEOUT_RETRY # macro -# NVOS_STATUS_ERROR_NOT_READY = NV_ERR_NOT_READY # macro -# NVOS_STATUS_ERROR_GPU_IS_LOST = NV_ERR_GPU_IS_LOST # macro -# NVOS_STATUS_ERROR_IN_FULLCHIP_RESET = NV_ERR_GPU_IN_FULLCHIP_RESET # macro -# NVOS_STATUS_ERROR_INVALID_LOCK_STATE = NV_ERR_INVALID_LOCK_STATE # macro -# NVOS_STATUS_ERROR_INVALID_ADDRESS = NV_ERR_INVALID_ADDRESS # macro -# NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL = NV_ERR_INVALID_IRQ_LEVEL # macro -# NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED = NV_ERR_MEMORY_TRAINING_FAILED # macro -# NVOS_STATUS_ERROR_BUSY_RETRY = NV_ERR_BUSY_RETRY # macro -# NVOS_STATUS_ERROR_INSUFFICIENT_POWER = NV_ERR_INSUFFICIENT_POWER # macro -# NVOS_STATUS_ERROR_OBJECT_NOT_FOUND = NV_ERR_OBJECT_NOT_FOUND # macro -# NVOS_STATUS_ERROR_RESOURCE_LOST = NV_ERR_RESOURCE_LOST # macro -# NVOS_STATUS_ERROR_BUFFER_TOO_SMALL = NV_ERR_BUFFER_TOO_SMALL # macro -# NVOS_STATUS_ERROR_RESET_REQUIRED = NV_ERR_RESET_REQUIRED # macro -# NVOS_STATUS_ERROR_INVALID_REQUEST = NV_ERR_INVALID_REQUEST # macro -# NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION = NV_ERR_PRIV_SEC_VIOLATION # macro -# NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE = NV_ERR_GPU_IN_DEBUG_MODE # macro -# NVOS_STATUS_ERROR_ALREADY_SIGNALLED = NV_ERR_ALREADY_SIGNALLED # macro -NV01_FREE = (0x00000000) # macro -NV01_ROOT_USER = (0x00000041) # macro -NV01_ALLOC_MEMORY = (0x00000002) # macro -# NVOS02_FLAGS_PHYSICALITY = 7 : 4 # macro -NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS = (0x00000000) # macro -NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS = (0x00000001) # macro -# NVOS02_FLAGS_LOCATION = 11 : 8 # macro -NVOS02_FLAGS_LOCATION_PCI = (0x00000000) # macro -NVOS02_FLAGS_LOCATION_VIDMEM = (0x00000002) # macro -# NVOS02_FLAGS_COHERENCY = 15 : 12 # macro -NVOS02_FLAGS_COHERENCY_UNCACHED = (0x00000000) # macro -NVOS02_FLAGS_COHERENCY_CACHED = (0x00000001) # macro -NVOS02_FLAGS_COHERENCY_WRITE_COMBINE = (0x00000002) # macro -NVOS02_FLAGS_COHERENCY_WRITE_THROUGH = (0x00000003) # macro -NVOS02_FLAGS_COHERENCY_WRITE_PROTECT = (0x00000004) # macro -NVOS02_FLAGS_COHERENCY_WRITE_BACK = (0x00000005) # macro -# NVOS02_FLAGS_ALLOC = 17 : 16 # macro -NVOS02_FLAGS_ALLOC_NONE = (0x00000001) # macro -# NVOS02_FLAGS_GPU_CACHEABLE = 18 : 18 # macro -NVOS02_FLAGS_GPU_CACHEABLE_NO = (0x00000000) # macro -NVOS02_FLAGS_GPU_CACHEABLE_YES = (0x00000001) # macro -# NVOS02_FLAGS_KERNEL_MAPPING = 19 : 19 # macro -NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP = (0x00000000) # macro -NVOS02_FLAGS_KERNEL_MAPPING_MAP = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_NISO_DISPLAY = 20 : 20 # macro -NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO = (0x00000000) # macro -NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_USER_READ_ONLY = 21 : 21 # macro -NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO = (0x00000000) # macro -NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY = 22 : 22 # macro -NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO = (0x00000000) # macro -NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES = (0x00000001) # macro -# NVOS02_FLAGS_PEER_MAP_OVERRIDE = 23 : 23 # macro -NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT = (0x00000000) # macro -NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED = (0x00000001) # macro -# NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT = 24 : 24 # macro -NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE = (0x00000001) # macro -# NVOS02_FLAGS_MEMORY_PROTECTION = 26 : 25 # macro -NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT = (0x00000000) # macro -NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED = (0x00000001) # macro -NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED = (0x00000002) # macro -# NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM = 27 : 27 # macro -NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = (0x00000000) # macro -NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = (0x00000001) # macro -# NVOS02_FLAGS_MAPPING = 31 : 30 # macro -NVOS02_FLAGS_MAPPING_DEFAULT = (0x00000000) # macro -NVOS02_FLAGS_MAPPING_NO_MAP = (0x00000001) # macro -NVOS02_FLAGS_MAPPING_NEVER_MAP = (0x00000002) # macro -# NVOS03_FLAGS_ACCESS = 1 : 0 # macro -NVOS03_FLAGS_ACCESS_READ_WRITE = (0x00000000) # macro -NVOS03_FLAGS_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS03_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # macro -# NVOS03_FLAGS_PREALLOCATE = 2 : 2 # macro -NVOS03_FLAGS_PREALLOCATE_DISABLE = (0x00000000) # macro -NVOS03_FLAGS_PREALLOCATE_ENABLE = (0x00000001) # macro -# NVOS03_FLAGS_GPU_MAPPABLE = 15 : 15 # macro -NVOS03_FLAGS_GPU_MAPPABLE_DISABLE = (0x00000000) # macro -NVOS03_FLAGS_GPU_MAPPABLE_ENABLE = (0x00000001) # macro -# NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE = 16 : 16 # macro -NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE = (0x00000000) # macro -NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE = (0x00000001) # macro -# NVOS03_FLAGS_PTE_KIND = 17 : 16 # macro -NVOS03_FLAGS_PTE_KIND_NONE = (0x00000000) # macro -NVOS03_FLAGS_PTE_KIND_BL = (0x00000001) # macro -NVOS03_FLAGS_PTE_KIND_PITCH = (0x00000002) # macro -# NVOS03_FLAGS_TYPE = 23 : 20 # macro -NVOS03_FLAGS_TYPE_NOTIFIER = (0x00000001) # macro -# NVOS03_FLAGS_MAPPING = 20 : 20 # macro -NVOS03_FLAGS_MAPPING_NONE = (0x00000000) # macro -NVOS03_FLAGS_MAPPING_KERNEL = (0x00000001) # macro -# NVOS03_FLAGS_CACHE_SNOOP = 28 : 28 # macro -NVOS03_FLAGS_CACHE_SNOOP_ENABLE = (0x00000000) # macro -NVOS03_FLAGS_CACHE_SNOOP_DISABLE = (0x00000001) # macro -# NVOS03_FLAGS_HASH_TABLE = 29 : 29 # macro -NVOS03_FLAGS_HASH_TABLE_ENABLE = (0x00000000) # macro -NVOS03_FLAGS_HASH_TABLE_DISABLE = (0x00000001) # macro -NV01_ALLOC_OBJECT = (0x00000005) # macro -NV01_EVENT_BROADCAST = (0x80000000) # macro -NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION = (0x40000000) # macro -NV01_EVENT_SUBDEVICE_SPECIFIC = (0x20000000) # macro -NV01_EVENT_WITHOUT_EVENT_DATA = (0x10000000) # macro -NV01_EVENT_NONSTALL_INTR = (0x08000000) # macro -NV01_EVENT_CLIENT_RM = (0x04000000) # macro -NV04_I2C_ACCESS = (0x00000013) # macro -NVOS_I2C_ACCESS_MAX_BUFFER_SIZE = 2048 # macro -NVOS20_COMMAND_unused0001 = 0x0001 # macro -NVOS20_COMMAND_unused0002 = 0x0002 # macro -NVOS20_COMMAND_STRING_PRINT = 0x0003 # macro -NV04_ALLOC = (0x00000015) # macro -NVOS64_FLAGS_NONE = (0x00000000) # macro -NVOS64_FLAGS_FINN_SERIALIZED = (0x00000001) # macro -NVOS65_PARAMETERS_VERSION_MAGIC = 0x77FEF81E # macro -NV04_IDLE_CHANNELS = (0x0000001E) # macro -# NVOS30_FLAGS_BEHAVIOR = 3 : 0 # macro -NVOS30_FLAGS_BEHAVIOR_SPIN = (0x00000000) # macro -NVOS30_FLAGS_BEHAVIOR_SLEEP = (0x00000001) # macro -NVOS30_FLAGS_BEHAVIOR_QUERY = (0x00000002) # macro -NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK = (0x00000003) # macro -# NVOS30_FLAGS_CHANNEL = 7 : 4 # macro -NVOS30_FLAGS_CHANNEL_LIST = (0x00000000) # macro -NVOS30_FLAGS_CHANNEL_SINGLE = (0x00000001) # macro -# NVOS30_FLAGS_IDLE = 30 : 8 # macro -NVOS30_FLAGS_IDLE_PUSH_BUFFER = (0x00000001) # macro -NVOS30_FLAGS_IDLE_CACHE1 = (0x00000002) # macro -NVOS30_FLAGS_IDLE_GRAPHICS = (0x00000004) # macro -NVOS30_FLAGS_IDLE_MPEG = (0x00000008) # macro -NVOS30_FLAGS_IDLE_MOTION_ESTIMATION = (0x00000010) # macro -NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR = (0x00000020) # macro -NVOS30_FLAGS_IDLE_MSPDEC = (0x00000020) # macro -NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR = (0x00000040) # macro -NVOS30_FLAGS_IDLE_MSVLD = (0x00000040) # macro -NVOS30_FLAGS_IDLE_NVDEC0 = (0x00000040) # macro -NVOS30_FLAGS_IDLE_CIPHER_DMA = (0x00000080) # macro -NVOS30_FLAGS_IDLE_SEC = (0x00000080) # macro -NVOS30_FLAGS_IDLE_CALLBACKS = (0x00000100) # macro -NVOS30_FLAGS_IDLE_MSPPP = (0x00000200) # macro -NVOS30_FLAGS_IDLE_CE0 = (0x00000400) # macro -NVOS30_FLAGS_IDLE_CE1 = (0x00000800) # macro -NVOS30_FLAGS_IDLE_CE2 = (0x00001000) # macro -NVOS30_FLAGS_IDLE_CE3 = (0x00002000) # macro -NVOS30_FLAGS_IDLE_CE4 = (0x00004000) # macro -NVOS30_FLAGS_IDLE_CE5 = (0x00008000) # macro -NVOS30_FLAGS_IDLE_VIC = (0x00010000) # macro -NVOS30_FLAGS_IDLE_MSENC = (0x00020000) # macro -NVOS30_FLAGS_IDLE_NVENC0 = (0x00020000) # macro -NVOS30_FLAGS_IDLE_NVENC1 = (0x00040000) # macro -NVOS30_FLAGS_IDLE_NVENC2 = (0x00080000) # macro -NVOS30_FLAGS_IDLE_NVJPG = (0x00100000) # macro -NVOS30_FLAGS_IDLE_NVDEC1 = (0x00200000) # macro -NVOS30_FLAGS_IDLE_NVDEC2 = (0x00400000) # macro -NVOS30_FLAGS_IDLE_ACTIVECHANNELS = (0x00800000) # macro -NVOS30_FLAGS_IDLE_ALL_ENGINES = ((0x00000004)|(0x00000008)|(0x00000010)|(0x00000020)|(0x00000040)|(0x00000080)|(0x00000020)|(0x00000040)|(0x00000080)|(0x00000200)|(0x00000400)|(0x00000800)|(0x00001000)|(0x00002000)|(0x00004000)|(0x00008000)|(0x00020000)|(0x00040000)|(0x00080000)|(0x00010000)|(0x00100000)|(0x00200000)|(0x00400000)) # macro -# NVOS30_FLAGS_WAIT_FOR_ELPG_ON = 31 : 31 # macro -NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO = (0x00000000) # macro -NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES = (0x00000001) # macro -NV04_VID_HEAP_CONTROL = (0x00000020) # macro -NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS = 0 # macro -NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY = 1 # macro -NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY = 2 # macro -NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR = 3 # macro -NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE = 4 # macro -NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR = 5 # macro -NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR = 6 # macro -NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS = 7 # macro -NVOS32_FUNCTION_ALLOC_SIZE = 2 # macro -NVOS32_FUNCTION_FREE = 3 # macro -NVOS32_FUNCTION_INFO = 5 # macro -NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT = 6 # macro -NVOS32_FUNCTION_DUMP = 11 # macro -NVOS32_FUNCTION_ALLOC_SIZE_RANGE = 14 # macro -NVOS32_FUNCTION_REACQUIRE_COMPR = 15 # macro -NVOS32_FUNCTION_RELEASE_COMPR = 16 # macro -NVOS32_FUNCTION_GET_MEM_ALIGNMENT = 18 # macro -NVOS32_FUNCTION_HW_ALLOC = 19 # macro -NVOS32_FUNCTION_HW_FREE = 20 # macro -NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR = 27 # macro -NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU = (0x00000001) # macro -NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP = 0 # macro -NVAL_MAX_BANKS = (4) # macro -# NVAL_MAP_DIRECTION = 0 : 0 # macro -NVAL_MAP_DIRECTION_DOWN = 0x00000000 # macro -NVAL_MAP_DIRECTION_UP = 0x00000001 # macro -NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR = 1 # macro -NVOS32_DELETE_RESOURCES_ALL = 0 # macro -NVOS32_TYPE_IMAGE = 0 # macro -NVOS32_TYPE_DEPTH = 1 # macro -NVOS32_TYPE_TEXTURE = 2 # macro -NVOS32_TYPE_VIDEO = 3 # macro -NVOS32_TYPE_FONT = 4 # macro -NVOS32_TYPE_CURSOR = 5 # macro -NVOS32_TYPE_DMA = 6 # macro -NVOS32_TYPE_INSTANCE = 7 # macro -NVOS32_TYPE_PRIMARY = 8 # macro -NVOS32_TYPE_ZCULL = 9 # macro -NVOS32_TYPE_UNUSED = 10 # macro -NVOS32_TYPE_SHADER_PROGRAM = 11 # macro -NVOS32_TYPE_OWNER_RM = 12 # macro -NVOS32_TYPE_NOTIFIER = 13 # macro -NVOS32_TYPE_RESERVED = 14 # macro -NVOS32_TYPE_PMA = 15 # macro -NVOS32_TYPE_STENCIL = 16 # macro -NVOS32_NUM_MEM_TYPES = 17 # macro -NVOS32_ATTR_NONE = 0x00000000 # macro -# NVOS32_ATTR_DEPTH = 2 : 0 # macro -NVOS32_ATTR_DEPTH_UNKNOWN = 0x00000000 # macro -NVOS32_ATTR_DEPTH_8 = 0x00000001 # macro -NVOS32_ATTR_DEPTH_16 = 0x00000002 # macro -NVOS32_ATTR_DEPTH_24 = 0x00000003 # macro -NVOS32_ATTR_DEPTH_32 = 0x00000004 # macro -NVOS32_ATTR_DEPTH_64 = 0x00000005 # macro -NVOS32_ATTR_DEPTH_128 = 0x00000006 # macro -# NVOS32_ATTR_COMPR_COVG = 3 : 3 # macro -NVOS32_ATTR_COMPR_COVG_DEFAULT = 0x00000000 # macro -NVOS32_ATTR_COMPR_COVG_PROVIDED = 0x00000001 # macro -# NVOS32_ATTR_AA_SAMPLES = 7 : 4 # macro -NVOS32_ATTR_AA_SAMPLES_1 = 0x00000000 # macro -NVOS32_ATTR_AA_SAMPLES_2 = 0x00000001 # macro -NVOS32_ATTR_AA_SAMPLES_4 = 0x00000002 # macro -NVOS32_ATTR_AA_SAMPLES_4_ROTATED = 0x00000003 # macro -NVOS32_ATTR_AA_SAMPLES_6 = 0x00000004 # macro -NVOS32_ATTR_AA_SAMPLES_8 = 0x00000005 # macro -NVOS32_ATTR_AA_SAMPLES_16 = 0x00000006 # macro -NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 = 0x00000007 # macro -NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 = 0x00000008 # macro -NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 = 0x00000009 # macro -NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 = 0x0000000A # macro -# NVOS32_ATTR_ZCULL = 11 : 10 # macro -NVOS32_ATTR_ZCULL_NONE = 0x00000000 # macro -NVOS32_ATTR_ZCULL_REQUIRED = 0x00000001 # macro -NVOS32_ATTR_ZCULL_ANY = 0x00000002 # macro -NVOS32_ATTR_ZCULL_SHARED = 0x00000003 # macro -# NVOS32_ATTR_COMPR = 13 : 12 # macro -NVOS32_ATTR_COMPR_NONE = 0x00000000 # macro -NVOS32_ATTR_COMPR_REQUIRED = 0x00000001 # macro -NVOS32_ATTR_COMPR_ANY = 0x00000002 # macro -NVOS32_ATTR_COMPR_PLC_REQUIRED = 0x00000001 # macro -NVOS32_ATTR_COMPR_PLC_ANY = 0x00000002 # macro -NVOS32_ATTR_COMPR_DISABLE_PLC_ANY = 0x00000003 # macro -# NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP = 14 : 14 # macro -NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO = 0x00000000 # macro -NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES = 0x00000001 # macro -# NVOS32_ATTR_FORMAT = 17 : 16 # macro -NVOS32_ATTR_FORMAT_LOW_FIELD = 16 # macro -NVOS32_ATTR_FORMAT_HIGH_FIELD = 17 # macro -NVOS32_ATTR_FORMAT_PITCH = 0x00000000 # macro -NVOS32_ATTR_FORMAT_SWIZZLED = 0x00000001 # macro -NVOS32_ATTR_FORMAT_BLOCK_LINEAR = 0x00000002 # macro -# NVOS32_ATTR_Z_TYPE = 18 : 18 # macro -NVOS32_ATTR_Z_TYPE_FIXED = 0x00000000 # macro -NVOS32_ATTR_Z_TYPE_FLOAT = 0x00000001 # macro -# NVOS32_ATTR_ZS_PACKING = 21 : 19 # macro -NVOS32_ATTR_ZS_PACKING_S8 = 0x00000000 # macro -NVOS32_ATTR_ZS_PACKING_Z24S8 = 0x00000000 # macro -NVOS32_ATTR_ZS_PACKING_S8Z24 = 0x00000001 # macro -NVOS32_ATTR_ZS_PACKING_Z32 = 0x00000002 # macro -NVOS32_ATTR_ZS_PACKING_Z24X8 = 0x00000003 # macro -NVOS32_ATTR_ZS_PACKING_X8Z24 = 0x00000004 # macro -NVOS32_ATTR_ZS_PACKING_Z32_X24S8 = 0x00000005 # macro -NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 = 0x00000006 # macro -NVOS32_ATTR_ZS_PACKING_Z16 = 0x00000007 # macro -# NVOS32_ATTR_COLOR_PACKING = 21 : 19 # macro -NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 = 0x00000000 # macro -NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 = 0x00000001 # macro -# NVOS32_ATTR_PAGE_SIZE = 24 : 23 # macro -NVOS32_ATTR_PAGE_SIZE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR_PAGE_SIZE_4KB = 0x00000001 # macro -NVOS32_ATTR_PAGE_SIZE_BIG = 0x00000002 # macro -NVOS32_ATTR_PAGE_SIZE_HUGE = 0x00000003 # macro -# NVOS32_ATTR_LOCATION = 26 : 25 # macro -NVOS32_ATTR_LOCATION_VIDMEM = 0x00000000 # macro -NVOS32_ATTR_LOCATION_PCI = 0x00000001 # macro -NVOS32_ATTR_LOCATION_ANY = 0x00000003 # macro -# NVOS32_ATTR_PHYSICALITY = 28 : 27 # macro -NVOS32_ATTR_PHYSICALITY_DEFAULT = 0x00000000 # macro -NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS = 0x00000001 # macro -NVOS32_ATTR_PHYSICALITY_CONTIGUOUS = 0x00000002 # macro -NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS = 0x00000003 # macro -# NVOS32_ATTR_COHERENCY = 31 : 29 # macro -NVOS32_ATTR_COHERENCY_UNCACHED = 0x00000000 # macro -NVOS32_ATTR_COHERENCY_CACHED = 0x00000001 # macro -NVOS32_ATTR_COHERENCY_WRITE_COMBINE = 0x00000002 # macro -NVOS32_ATTR_COHERENCY_WRITE_THROUGH = 0x00000003 # macro -NVOS32_ATTR_COHERENCY_WRITE_PROTECT = 0x00000004 # macro -NVOS32_ATTR_COHERENCY_WRITE_BACK = 0x00000005 # macro -NVOS32_ATTR2_NONE = 0x00000000 # macro -# NVOS32_ATTR2_ZBC = 1 : 0 # macro -NVOS32_ATTR2_ZBC_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_ZBC_PREFER_NO_ZBC = 0x00000001 # macro -NVOS32_ATTR2_ZBC_PREFER_ZBC = 0x00000002 # macro -NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC = 0x00000003 # macro -NVOS32_ATTR2_ZBC_INVALID = 0x00000003 # macro -# NVOS32_ATTR2_GPU_CACHEABLE = 3 : 2 # macro -NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_GPU_CACHEABLE_YES = 0x00000001 # macro -NVOS32_ATTR2_GPU_CACHEABLE_NO = 0x00000002 # macro -NVOS32_ATTR2_GPU_CACHEABLE_INVALID = 0x00000003 # macro -# NVOS32_ATTR2_P2P_GPU_CACHEABLE = 5 : 4 # macro -NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES = 0x00000001 # macro -NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO = 0x00000002 # macro -# NVOS32_ATTR2_32BIT_POINTER = 6 : 6 # macro -NVOS32_ATTR2_32BIT_POINTER_DISABLE = 0x00000000 # macro -NVOS32_ATTR2_32BIT_POINTER_ENABLE = 0x00000001 # macro -# NVOS32_ATTR2_FIXED_NUMA_NODE_ID = 7 : 7 # macro -NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO = 0x00000000 # macro -NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES = 0x00000001 # macro -# NVOS32_ATTR2_SMMU_ON_GPU = 9 : 8 # macro -NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_SMMU_ON_GPU_DISABLE = 0x00000001 # macro -NVOS32_ATTR2_SMMU_ON_GPU_ENABLE = 0x00000002 # macro -# NVOS32_ATTR2_USE_SCANOUT_CARVEOUT = 10 : 10 # macro -NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE = 0x00000000 # macro -NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE = 0x00000001 # macro -# NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN = 11 : 11 # macro -NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF = 0x0 # macro -NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON = 0x1 # macro -NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT = 0x0 # macro -# NVOS32_ATTR2_PRIORITY = 13 : 12 # macro -NVOS32_ATTR2_PRIORITY_DEFAULT = 0x0 # macro -NVOS32_ATTR2_PRIORITY_HIGH = 0x1 # macro -NVOS32_ATTR2_PRIORITY_LOW = 0x2 # macro -# NVOS32_ATTR2_INTERNAL = 14 : 14 # macro -NVOS32_ATTR2_INTERNAL_NO = 0x0 # macro -NVOS32_ATTR2_INTERNAL_YES = 0x1 # macro -# NVOS32_ATTR2_PREFER_2C = 15 : 15 # macro -NVOS32_ATTR2_PREFER_2C_NO = 0x00000000 # macro -NVOS32_ATTR2_PREFER_2C_YES = 0x00000001 # macro -# NVOS32_ATTR2_NISO_DISPLAY = 16 : 16 # macro -NVOS32_ATTR2_NISO_DISPLAY_NO = 0x00000000 # macro -NVOS32_ATTR2_NISO_DISPLAY_YES = 0x00000001 # macro -# NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT = 17 : 17 # macro -NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO = 0x00000000 # macro -NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES = 0x00000001 # macro -# NVOS32_ATTR2_ISO = 18 : 18 # macro -NVOS32_ATTR2_ISO_NO = 0x00000000 # macro -NVOS32_ATTR2_ISO_YES = 0x00000001 # macro -# NVOS32_ATTR2_BLACKLIST = 19 : 19 # macro -NVOS32_ATTR2_BLACKLIST_ON = 0x00000000 # macro -NVOS32_ATTR2_BLACKLIST_OFF = 0x00000001 # macro -# NVOS32_ATTR2_PAGE_OFFLINING = 19 : 19 # macro -NVOS32_ATTR2_PAGE_OFFLINING_ON = 0x00000000 # macro -NVOS32_ATTR2_PAGE_OFFLINING_OFF = 0x00000001 # macro -# NVOS32_ATTR2_PAGE_SIZE_HUGE = 21 : 20 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB = 0x00000001 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB = 0x00000002 # macro -NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB = 0x00000003 # macro -# NVOS32_ATTR2_PROTECTION_USER = 22 : 22 # macro -NVOS32_ATTR2_PROTECTION_USER_READ_WRITE = 0x00000000 # macro -NVOS32_ATTR2_PROTECTION_USER_READ_ONLY = 0x00000001 # macro -# NVOS32_ATTR2_PROTECTION_DEVICE = 23 : 23 # macro -NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE = 0x00000000 # macro -NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY = 0x00000001 # macro -# NVOS32_ATTR2_USE_EGM = 24 : 24 # macro -NVOS32_ATTR2_USE_EGM_FALSE = 0x00000000 # macro -NVOS32_ATTR2_USE_EGM_TRUE = 0x00000001 # macro -# NVOS32_ATTR2_MEMORY_PROTECTION = 26 : 25 # macro -NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT = 0x00000000 # macro -NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED = 0x00000001 # macro -NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED = 0x00000002 # macro -# NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP = 27 : 27 # macro -NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO = 0x00000000 # macro -NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES = 0x00000001 # macro -# NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM = 31 : 31 # macro -NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = 0x00000000 # macro -NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = 0x00000001 # macro -NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT = 0x00000001 # macro -NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP = 0x00000002 # macro -NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN = 0x00000004 # macro -NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE = 0x00000008 # macro -NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE = 0x00000010 # macro -NVOS32_ALLOC_FLAGS_BANK_HINT = 0x00000020 # macro -NVOS32_ALLOC_FLAGS_BANK_FORCE = 0x00000040 # macro -NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT = 0x00000080 # macro -NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE = 0x00000100 # macro -NVOS32_ALLOC_FLAGS_BANK_GROW_UP = 0x00000000 # macro -NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN = 0x00000200 # macro -NVOS32_ALLOC_FLAGS_LAZY = 0x00000400 # macro -NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC = 0x00000800 # macro -NVOS32_ALLOC_FLAGS_NO_SCANOUT = 0x00001000 # macro -NVOS32_ALLOC_FLAGS_PITCH_FORCE = 0x00002000 # macro -NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00004000 # macro -NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED = 0x00008000 # macro -NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM = 0x00010000 # macro -NVOS32_ALLOC_FLAGS_USE_BEGIN_END = 0x00020000 # macro -NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED = 0x00040000 # macro -NVOS32_ALLOC_FLAGS_VIRTUAL = 0x00080000 # macro -NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX = 0x00100000 # macro -NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED = 0x00200000 # macro -NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED = 0x00400000 # macro -NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE = 0x00800000 # macro -NVOS32_ALLOC_FLAGS_PROTECTED = 0x01000000 # macro -NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP = 0x02000000 # macro -NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE = 0x02000000 # macro -NVOS32_ALLOC_FLAGS_SPARSE = 0x04000000 # macro -NVOS32_ALLOC_FLAGS_USER_READ_ONLY = 0x04000000 # macro -NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY = 0x08000000 # macro -NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED = 0x08000000 # macro -NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC = 0x10000000 # macro -NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY = 0x20000000 # macro -NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD = 0x40000000 # macro -NVOS32_ALLOC_FLAGS_WPR1 = 0x40000000 # macro -NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X = 0x80000000 # macro -NVOS32_ALLOC_FLAGS_WPR2 = 0x80000000 # macro -NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC = 0x00000001 # macro -NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB = 0x00000004 # macro -NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE = 0x02000000 # macro -NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY = (0x00080000|0x00000400|0x00400000|0x04000000|0x02000000|0x20000000) # macro -NVOS32_ALLOC_COMPR_COVG_SCALE = 10 # macro -# NVOS32_ALLOC_COMPR_COVG_BITS = 1 : 0 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT = 0x00000000 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_1 = 0x00000001 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_2 = 0x00000002 # macro -NVOS32_ALLOC_COMPR_COVG_BITS_4 = 0x00000003 # macro -# NVOS32_ALLOC_COMPR_COVG_MAX = 11 : 2 # macro -# NVOS32_ALLOC_COMPR_COVG_MIN = 21 : 12 # macro -# NVOS32_ALLOC_COMPR_COVG_START = 31 : 22 # macro -# NVOS32_ALLOC_ZCULL_COVG_FORMAT = 3 : 0 # macro -NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z = 0x00000000 # macro -NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z = 0x00000002 # macro -NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS = 0x00000003 # macro -# NVOS32_ALLOC_ZCULL_COVG_FALLBACK = 4 : 4 # macro -NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW = 0x00000000 # macro -NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW = 0x00000001 # macro -# NVOS32_ALLOC_COMPTAG_OFFSET_START = 19 : 0 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT = 0x00000000 # macro -# NVOS32_ALLOC_COMPTAG_OFFSET_USAGE = 31 : 30 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT = 0x00000000 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF = 0x00000000 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED = 0x00000001 # macro -NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN = 0x00000002 # macro -NVOS32_REALLOC_FLAGS_GROW_ALLOCATION = 0x00000000 # macro -NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION = 0x00000001 # macro -NVOS32_REALLOC_FLAGS_REALLOC_UP = 0x00000000 # macro -NVOS32_REALLOC_FLAGS_REALLOC_DOWN = 0x00000002 # macro -NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 # macro -NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 # macro -NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00000001 # macro -# NVOS32_DUMP_FLAGS_TYPE = 1 : 0 # macro -NVOS32_DUMP_FLAGS_TYPE_FB = 0x00000000 # macro -NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD = 0x00000001 # macro -NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA = 0x00000002 # macro -NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE = 0x00000003 # macro -NVOS32_BLOCK_TYPE_FREE = 0xFFFFFFFF # macro -NVOS32_INVALID_BLOCK_FREE_OFFSET = 0xFFFFFFFF # macro -NVOS32_MEM_TAG_NONE = 0x00000000 # macro -NV04_MAP_MEMORY = (0x00000021) # macro -NV04_MAP_MEMORY_FLAGS_NONE = (0x00000000) # macro -NV04_MAP_MEMORY_FLAGS_USER = (0x00004000) # macro -# NVOS33_FLAGS_ACCESS = 1 : 0 # macro -NVOS33_FLAGS_ACCESS_READ_WRITE = (0x00000000) # macro -NVOS33_FLAGS_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS33_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # macro -# NVOS33_FLAGS_PERSISTENT = 4 : 4 # macro -NVOS33_FLAGS_PERSISTENT_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_PERSISTENT_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_SKIP_SIZE_CHECK = 8 : 8 # macro -NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_MEM_SPACE = 14 : 14 # macro -NVOS33_FLAGS_MEM_SPACE_CLIENT = (0x00000000) # macro -NVOS33_FLAGS_MEM_SPACE_USER = (0x00000001) # macro -# NVOS33_FLAGS_MAPPING = 16 : 15 # macro -NVOS33_FLAGS_MAPPING_DEFAULT = (0x00000000) # macro -NVOS33_FLAGS_MAPPING_DIRECT = (0x00000001) # macro -NVOS33_FLAGS_MAPPING_REFLECTED = (0x00000002) # macro -# NVOS33_FLAGS_FIFO_MAPPING = 17 : 17 # macro -NVOS33_FLAGS_FIFO_MAPPING_DEFAULT = (0x00000000) # macro -NVOS33_FLAGS_FIFO_MAPPING_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_MAP_FIXED = 18 : 18 # macro -NVOS33_FLAGS_MAP_FIXED_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_MAP_FIXED_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_RESERVE_ON_UNMAP = 19 : 19 # macro -NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_OS_DESCRIPTOR = 22 : 22 # macro -NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE = (0x00000000) # macro -NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE = (0x00000001) # macro -# NVOS33_FLAGS_CACHING_TYPE = 25 : 23 # macro -NVOS33_FLAGS_CACHING_TYPE_CACHED = 0 # macro -NVOS33_FLAGS_CACHING_TYPE_UNCACHED = 1 # macro -NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED = 2 # macro -NVOS33_FLAGS_CACHING_TYPE_WRITEBACK = 5 # macro -NVOS33_FLAGS_CACHING_TYPE_DEFAULT = 6 # macro -NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK = 7 # macro -# NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC = 26 : 26 # macro -NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO = (0x00000000) # macro -NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES = (0x00000001) # macro -NV04_UNMAP_MEMORY = (0x00000022) # macro -NV04_ACCESS_REGISTRY = (0x00000026) # macro -NVOS38_ACCESS_TYPE_READ_DWORD = 1 # macro -NVOS38_ACCESS_TYPE_WRITE_DWORD = 2 # macro -NVOS38_ACCESS_TYPE_READ_BINARY = 6 # macro -NVOS38_ACCESS_TYPE_WRITE_BINARY = 7 # macro -NVOS38_MAX_REGISTRY_STRING_LENGTH = 256 # macro -NVOS38_MAX_REGISTRY_BINARY_LENGTH = 256 # macro -NV04_ALLOC_CONTEXT_DMA = (0x00000027) # macro -NV04_GET_EVENT_DATA = (0x00000028) # macro -NVSIM01_BUS_XACT = (0x0000002C) # macro -NV04_MAP_MEMORY_DMA = (0x0000002E) # macro -# NVOS46_FLAGS_ACCESS = 1 : 0 # macro -NVOS46_FLAGS_ACCESS_READ_WRITE = (0x00000000) # macro -NVOS46_FLAGS_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS46_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) # macro -# NVOS46_FLAGS_32BIT_POINTER = 2 : 2 # macro -NVOS46_FLAGS_32BIT_POINTER_DISABLE = (0x00000000) # macro -NVOS46_FLAGS_32BIT_POINTER_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_PAGE_KIND = 3 : 3 # macro -NVOS46_FLAGS_PAGE_KIND_PHYSICAL = (0x00000000) # macro -NVOS46_FLAGS_PAGE_KIND_VIRTUAL = (0x00000001) # macro -# NVOS46_FLAGS_CACHE_SNOOP = 4 : 4 # macro -NVOS46_FLAGS_CACHE_SNOOP_DISABLE = (0x00000000) # macro -NVOS46_FLAGS_CACHE_SNOOP_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_KERNEL_MAPPING = 5 : 5 # macro -NVOS46_FLAGS_KERNEL_MAPPING_NONE = (0x00000000) # macro -NVOS46_FLAGS_KERNEL_MAPPING_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_SHADER_ACCESS = 7 : 6 # macro -NVOS46_FLAGS_SHADER_ACCESS_DEFAULT = (0x00000000) # macro -NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) # macro -NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) # macro -NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000003) # macro -# NVOS46_FLAGS_PAGE_SIZE = 11 : 8 # macro -NVOS46_FLAGS_PAGE_SIZE_DEFAULT = (0x00000000) # macro -NVOS46_FLAGS_PAGE_SIZE_4KB = (0x00000001) # macro -NVOS46_FLAGS_PAGE_SIZE_BIG = (0x00000002) # macro -NVOS46_FLAGS_PAGE_SIZE_BOTH = (0x00000003) # macro -NVOS46_FLAGS_PAGE_SIZE_HUGE = (0x00000004) # macro -NVOS46_FLAGS_PAGE_SIZE_512M = (0x00000005) # macro -# NVOS46_FLAGS_SYSTEM_L3_ALLOC = 13 : 13 # macro -NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT = (0x00000000) # macro -NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT = (0x00000001) # macro -# NVOS46_FLAGS_DMA_OFFSET_GROWS = 14 : 14 # macro -NVOS46_FLAGS_DMA_OFFSET_GROWS_UP = (0x00000000) # macro -NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN = (0x00000001) # macro -# NVOS46_FLAGS_DMA_OFFSET_FIXED = 15 : 15 # macro -NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_DISABLE_ENCRYPTION = 16 : 16 # macro -NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_P2P = 27 : 20 # macro -# NVOS46_FLAGS_P2P_ENABLE = 21 : 20 # macro -NVOS46_FLAGS_P2P_ENABLE_NO = (0x00000000) # macro -NVOS46_FLAGS_P2P_ENABLE_YES = (0x00000001) # macro -NVOS46_FLAGS_P2P_ENABLE_NONE = (0x00000000) # macro -NVOS46_FLAGS_P2P_ENABLE_SLI = (0x00000001) # macro -NVOS46_FLAGS_P2P_ENABLE_NOSLI = (0x00000002) # macro -# NVOS46_FLAGS_P2P_SUBDEVICE_ID = 24 : 22 # macro -# NVOS46_FLAGS_P2P_SUBDEV_ID_SRC = 24 : 22 # macro -# NVOS46_FLAGS_P2P_SUBDEV_ID_TGT = 27 : 25 # macro -# NVOS46_FLAGS_TLB_LOCK = 28 : 28 # macro -NVOS46_FLAGS_TLB_LOCK_DISABLE = (0x00000000) # macro -NVOS46_FLAGS_TLB_LOCK_ENABLE = (0x00000001) # macro -# NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC = 29 : 29 # macro -NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP = 30 : 30 # macro -NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE = (0x00000000) # macro -NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE = (0x00000001) # macro -# NVOS46_FLAGS_DEFER_TLB_INVALIDATION = 31 : 31 # macro -NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) # macro -NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) # macro -NV04_UNMAP_MEMORY_DMA = (0x0000002F) # macro -# NVOS47_FLAGS_DEFER_TLB_INVALIDATION = 0 : 0 # macro -NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) # macro -NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) # macro -NV04_BIND_CONTEXT_DMA = (0x00000031) # macro -NV04_CONTROL = (0x00000036) # macro -NVOS54_FLAGS_NONE = (0x00000000) # macro -NVOS54_FLAGS_IRQL_RAISED = (0x00000001) # macro -NVOS54_FLAGS_LOCK_BYPASS = (0x00000002) # macro -NVOS54_FLAGS_FINN_SERIALIZED = (0x00000004) # macro -NV04_DUP_OBJECT = (0x00000037) # macro -NV04_DUP_HANDLE_FLAGS_NONE = (0x00000000) # macro -NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE = (0x00000001) # macro -NV04_UPDATE_DEVICE_MAPPING_INFO = (0x00000038) # macro -NV04_SHARE = (0x0000003E) # macro -NV_DEVICE_ALLOCATION_SZNAME_MAXLEN = 128 # macro -NV_DEVICE_ALLOCATION_FLAGS_NONE = (0x00000000) # macro -NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY = (0x00000001) # macro -NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (0x00000002) # macro -NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (0x00000004) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE = (0x00000008) # macro -NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE = (0x00000010) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET = (0x00000020) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT = (0x00000100) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k = (0x00000200) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k = (0x00000400) # macro -NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS = (0x00000800) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED = (0x00000040) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED = (0x00001000) # macro -NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE = (0x00002000) # macro -NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT = (0x00004000) # macro -NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET = (0x00008000) # macro -NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES = (0x00000000) # macro -NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE = (0x00000001) # macro -NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES = (0x00000002) # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR = 0x00000000 # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN = 0x00000001 # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS = 0x00000002 # macro -NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 = 3 # macro -# NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE = 14 : 0 # macro -# NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS = 15 : 15 # macro -NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE = 0x1 # macro -NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE = 0x0 # macro -# NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB = 1 : 1 # macro -NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES = 0x00000000 # macro -NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO = 0x00000001 # macro -NV_SWRUNLIST_QOS_INTR_NONE = 0x00000000 # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE = (1 << 0) # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE = (1 << 1) # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE = (1 << 2) # macro -NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE = (1 << 3) # macro -NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE = (0x00000000) # macro -NV_VP_ALLOCATION_FLAGS_STATIC_UCODE = (0x00000001) # macro -NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE = (0x00000002) # macro -NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO = (0x00000000) # macro -NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO = (0x00000001) # macro -NV04_ADD_VBLANK_CALLBACK = (0x0000003D) # macro -NV_VASPACE_ALLOCATION_FLAGS_NONE = (0x00000000) # macro -NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (1 << 0) # macro -NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (1 << 1) # macro -NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT = (1 << 2) # macro -NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED = (1 << 3) # macro -NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS = (1 << 4) # macro -NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED = (1 << 5) # macro -NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING = (1 << 6) # macro -NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT = (1 << 7) # macro -NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS = (1 << 8) # macro -NV_VASPACE_ALLOCATION_FLAGS_IS_FLA = (1 << 9) # macro -NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL = (1 << 10) # macro -NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE = (1 << 11) # macro -NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET = (1 << 12) # macro -NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED = (1 << 13) # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_NEW = 0x00 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_HOST = 0x01 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL = 0x02 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE = 0x03 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_FLA = 0x04 # macro -NV_VASPACE_ALLOCATION_INDEX_GPU_MAX = 0x05 # macro -NV_VASPACE_BIG_PAGE_SIZE_64K = (64*1024) # macro -NV_VASPACE_BIG_PAGE_SIZE_128K = (128*1024) # macro -# NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT = 1 : 0 # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC = (0x00000000) # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC = (0x00000001) # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED = (0x00000002) # macro -NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER = (0x00000003) # macro -# NV_CTXSHARE_ALLOCATION_SUBCTXID_SUBCTXID = 30 : 0 # macro -# NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION = 31 : 31 # macro -NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS = (0x00000001) # macro -NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL = (0x00000000) # macro -NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT = (0x00000002) # macro -NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT = (0x00000003) # macro -class struct_NV_MEMORY_DESC_PARAMS(Structure): - pass - -struct_NV_MEMORY_DESC_PARAMS._pack_ = 1 # source:False +class nv_ioctl_nvos02_parameters_with_fd(Struct): pass +class NVOS02_PARAMETERS(Struct): pass +NVOS02_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('flags', NvV32), + ('pMemory', NvP64), + ('limit', NvU64), + ('status', NvV32), +] +nv_ioctl_nvos02_parameters_with_fd._fields_ = [ + ('params', NVOS02_PARAMETERS), + ('fd', ctypes.c_int32), +] +class nv_ioctl_nvos33_parameters_with_fd(Struct): pass +class NVOS33_PARAMETERS(Struct): pass +NVOS33_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hMemory', NvHandle), + ('offset', NvU64), + ('length', NvU64), + ('pLinearAddress', NvP64), + ('status', NvU32), + ('flags', NvU32), +] +nv_ioctl_nvos33_parameters_with_fd._fields_ = [ + ('params', NVOS33_PARAMETERS), + ('fd', ctypes.c_int32), +] +class struct_NV_MEMORY_DESC_PARAMS(Struct): pass struct_NV_MEMORY_DESC_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cacheAttrib', ctypes.c_uint32), + ('base', NvU64), + ('size', NvU64), + ('addressSpace', NvU32), + ('cacheAttrib', NvU32), ] - NV_MEMORY_DESC_PARAMS = struct_NV_MEMORY_DESC_PARAMS -class struct_NV_CHANNEL_ALLOC_PARAMS(Structure): - pass - -struct_NV_CHANNEL_ALLOC_PARAMS._pack_ = 1 # source:False +class struct_NV_CHANNEL_ALLOC_PARAMS(Struct): pass struct_NV_CHANNEL_ALLOC_PARAMS._fields_ = [ - ('hObjectError', ctypes.c_uint32), - ('hObjectBuffer', ctypes.c_uint32), - ('gpFifoOffset', ctypes.c_uint64), - ('gpFifoEntries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hContextShare', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('hUserdMemory', ctypes.c_uint32 * 8), - ('userdOffset', ctypes.c_uint64 * 8), - ('engineType', ctypes.c_uint32), - ('cid', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('hObjectEccError', ctypes.c_uint32), - ('instanceMem', NV_MEMORY_DESC_PARAMS), - ('userdMem', NV_MEMORY_DESC_PARAMS), - ('ramfcMem', NV_MEMORY_DESC_PARAMS), - ('mthdbufMem', NV_MEMORY_DESC_PARAMS), - ('hPhysChannelGroup', ctypes.c_uint32), - ('internalFlags', ctypes.c_uint32), - ('errorNotifierMem', NV_MEMORY_DESC_PARAMS), - ('eccErrorNotifierMem', NV_MEMORY_DESC_PARAMS), - ('ProcessID', ctypes.c_uint32), - ('SubProcessID', ctypes.c_uint32), - ('encryptIv', ctypes.c_uint32 * 3), - ('decryptIv', ctypes.c_uint32 * 3), - ('hmacNonce', ctypes.c_uint32 * 8), - ('tpcConfigID', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('hObjectError', NvHandle), + ('hObjectBuffer', NvHandle), + ('gpFifoOffset', NvU64), + ('gpFifoEntries', NvU32), + ('flags', NvU32), + ('hContextShare', NvHandle), + ('hVASpace', NvHandle), + ('hUserdMemory', (NvHandle * 8)), + ('userdOffset', (NvU64 * 8)), + ('engineType', NvU32), + ('cid', NvU32), + ('subDeviceId', NvU32), + ('hObjectEccError', NvHandle), + ('instanceMem', NV_MEMORY_DESC_PARAMS), + ('userdMem', NV_MEMORY_DESC_PARAMS), + ('ramfcMem', NV_MEMORY_DESC_PARAMS), + ('mthdbufMem', NV_MEMORY_DESC_PARAMS), + ('hPhysChannelGroup', NvHandle), + ('internalFlags', NvU32), + ('errorNotifierMem', NV_MEMORY_DESC_PARAMS), + ('eccErrorNotifierMem', NV_MEMORY_DESC_PARAMS), + ('ProcessID', NvU32), + ('SubProcessID', NvU32), + ('encryptIv', (NvU32 * 3)), + ('decryptIv', (NvU32 * 3)), + ('hmacNonce', (NvU32 * 8)), + ('tpcConfigID', NvU32), ] - NV_CHANNEL_ALLOC_PARAMS = struct_NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS = struct_NV_CHANNEL_ALLOC_PARAMS -class struct_c__SA_NVOS00_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS00_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS00_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectOld', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS00_PARAMETERS(Struct): pass +NVOS00_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectOld', NvHandle), + ('status', NvV32), ] - -NVOS00_PARAMETERS = struct_c__SA_NVOS00_PARAMETERS -class struct_c__SA_NVOS02_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS02_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS02_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pMemory', ctypes.POINTER(None)), - ('limit', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS05_PARAMETERS(Struct): pass +NVOS05_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('status', NvV32), ] - -NVOS02_PARAMETERS = struct_c__SA_NVOS02_PARAMETERS -class struct_c__SA_NVOS05_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS05_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS05_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('status', ctypes.c_uint32), +Callback1ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.c_void_p) +Callback5ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) +class NVOS10_EVENT_KERNEL_CALLBACK(Struct): pass +NVOS10_EVENT_KERNEL_CALLBACK._fields_ = [ + ('func', Callback1ArgVoidReturn), + ('arg', ctypes.c_void_p), ] - -NVOS05_PARAMETERS = struct_c__SA_NVOS05_PARAMETERS -Callback1ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -Callback5ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -class struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK(Structure): - pass - -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK._pack_ = 1 # source:False -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK._fields_ = [ - ('func', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('arg', ctypes.POINTER(None)), +class NVOS10_EVENT_KERNEL_CALLBACK_EX(Struct): pass +NVOS10_EVENT_KERNEL_CALLBACK_EX._fields_ = [ + ('func', Callback5ArgVoidReturn), + ('arg', ctypes.c_void_p), ] - -NVOS10_EVENT_KERNEL_CALLBACK = struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK -class struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX(Structure): - pass - -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX._pack_ = 1 # source:False -struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX._fields_ = [ - ('func', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32)), - ('arg', ctypes.POINTER(None)), +class NVOS_I2C_ACCESS_PARAMS(Struct): pass +NVOS_I2C_ACCESS_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('paramSize', NvU32), + ('paramStructPtr', NvP64), + ('status', NvV32), ] - -NVOS10_EVENT_KERNEL_CALLBACK_EX = struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX -class struct_c__SA_NVOS_I2C_ACCESS_PARAMS(Structure): - pass - -struct_c__SA_NVOS_I2C_ACCESS_PARAMS._pack_ = 1 # source:False -struct_c__SA_NVOS_I2C_ACCESS_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('paramSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('paramStructPtr', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS21_PARAMETERS(Struct): pass +NVOS21_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('pAllocParms', NvP64), + ('paramsSize', NvU32), + ('status', NvV32), ] - -NVOS_I2C_ACCESS_PARAMS = struct_c__SA_NVOS_I2C_ACCESS_PARAMS -class struct_c__SA_NVOS21_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS21_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS21_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('pAllocParms', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS64_PARAMETERS(Struct): pass +NVOS64_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('pAllocParms', NvP64), + ('pRightsRequested', NvP64), + ('paramsSize', NvU32), + ('flags', NvU32), + ('status', NvV32), ] - -NVOS21_PARAMETERS = struct_c__SA_NVOS21_PARAMETERS -class struct_c__SA_NVOS64_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS64_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS64_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('pAllocParms', ctypes.POINTER(None)), - ('pRightsRequested', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class NVOS62_PARAMETERS(Struct): pass +NVOS62_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('paramSize', NvU32), + ('status', NvV32), ] - -NVOS64_PARAMETERS = struct_c__SA_NVOS64_PARAMETERS -class struct_c__SA_NVOS62_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS62_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS62_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('paramSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS65_PARAMETERS(Struct): pass +NVOS65_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('paramSize', NvU32), + ('versionMagic', NvU32), + ('maskSize', NvU32), + ('status', NvV32), ] - -NVOS62_PARAMETERS = struct_c__SA_NVOS62_PARAMETERS -class struct_c__SA_NVOS65_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS65_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS65_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('paramSize', ctypes.c_uint32), - ('versionMagic', ctypes.c_uint32), - ('maskSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS30_PARAMETERS(Struct): pass +NVOS30_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hChannel', NvHandle), + ('numChannels', NvV32), + ('phClients', NvP64), + ('phDevices', NvP64), + ('phChannels', NvP64), + ('flags', NvV32), + ('timeout', NvV32), + ('status', NvV32), ] - -NVOS65_PARAMETERS = struct_c__SA_NVOS65_PARAMETERS -class struct_c__SA_NVOS30_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS30_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS30_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('phClients', ctypes.POINTER(None)), - ('phDevices', ctypes.POINTER(None)), - ('phChannels', ctypes.POINTER(None)), - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +BindResultFunc = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) +class NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS(Struct): pass +NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS._fields_ = [ + ('sgt', NvP64), + ('gem', NvP64), ] - -NVOS30_PARAMETERS = struct_c__SA_NVOS30_PARAMETERS -BindResultFunc = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) -class struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS._fields_ = [ - ('sgt', ctypes.POINTER(None)), - ('gem', ctypes.POINTER(None)), +class NVOS32_BLOCKINFO(Struct): pass +NVOS32_BLOCKINFO._fields_ = [ + ('startOffset', NvU64), + ('size', NvU64), + ('flags', NvU32), ] - -NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS = struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS -class struct_c__SA_NVOS32_BLOCKINFO(Structure): - pass - -struct_c__SA_NVOS32_BLOCKINFO._pack_ = 1 # source:False -struct_c__SA_NVOS32_BLOCKINFO._fields_ = [ - ('startOffset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class NVOS32_PARAMETERS(Struct): pass +NvS16 = ctypes.c_int16 +class NVOS32_PARAMETERS_data(ctypes.Union): pass +class NVOS32_PARAMETERS_data_AllocSize(Struct): pass +NVOS32_PARAMETERS_data_AllocSize._fields_ = [ + ('owner', NvU32), + ('hMemory', NvHandle), + ('type', NvU32), + ('flags', NvU32), + ('attr', NvU32), + ('format', NvU32), + ('comprCovg', NvU32), + ('zcullCovg', NvU32), + ('partitionStride', NvU32), + ('width', NvU32), + ('height', NvU32), + ('size', NvU64), + ('alignment', NvU64), + ('offset', NvU64), + ('limit', NvU64), + ('address', NvP64), + ('rangeBegin', NvU64), + ('rangeEnd', NvU64), + ('attr2', NvU32), + ('ctagOffset', NvU32), + ('numaNode', NvS32), ] - -NVOS32_BLOCKINFO = struct_c__SA_NVOS32_BLOCKINFO -class struct_c__SA_NVOS32_PARAMETERS(Structure): - pass - -class union_c__SA_NVOS32_PARAMETERS_data(Union): - pass - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocSize(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocSize._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocSize._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('partitionStride', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('rangeBegin', ctypes.c_uint64), - ('rangeEnd', ctypes.c_uint64), - ('attr2', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS32_PARAMETERS_data_AllocTiledPitchHeight(Struct): pass +NVOS32_PARAMETERS_data_AllocTiledPitchHeight._fields_ = [ + ('owner', NvU32), + ('hMemory', NvHandle), + ('type', NvU32), + ('flags', NvU32), + ('height', NvU32), + ('pitch', NvS32), + ('attr', NvU32), + ('width', NvU32), + ('format', NvU32), + ('comprCovg', NvU32), + ('zcullCovg', NvU32), + ('partitionStride', NvU32), + ('size', NvU64), + ('alignment', NvU64), + ('offset', NvU64), + ('limit', NvU64), + ('address', NvP64), + ('rangeBegin', NvU64), + ('rangeEnd', NvU64), + ('attr2', NvU32), + ('ctagOffset', NvU32), + ('numaNode', NvS32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_int32), - ('attr', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('partitionStride', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('rangeBegin', ctypes.c_uint64), - ('rangeEnd', ctypes.c_uint64), - ('attr2', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), +class NVOS32_PARAMETERS_data_Free(Struct): pass +NVOS32_PARAMETERS_data_Free._fields_ = [ + ('owner', NvU32), + ('hMemory', NvHandle), + ('flags', NvU32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_Free(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_Free._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_Free._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), +class NVOS32_PARAMETERS_data_ReleaseCompr(Struct): pass +NVOS32_PARAMETERS_data_ReleaseCompr._fields_ = [ + ('owner', NvU32), + ('flags', NvU32), + ('hMemory', NvHandle), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr._fields_ = [ - ('owner', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), +class NVOS32_PARAMETERS_data_ReacquireCompr(Struct): pass +NVOS32_PARAMETERS_data_ReacquireCompr._fields_ = [ + ('owner', NvU32), + ('flags', NvU32), + ('hMemory', NvHandle), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr._fields_ = [ - ('owner', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), +class NVOS32_PARAMETERS_data_Info(Struct): pass +NVOS32_PARAMETERS_data_Info._fields_ = [ + ('attr', NvU32), + ('offset', NvU64), + ('size', NvU64), + ('base', NvU64), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_Info(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_Info._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_Info._fields_ = [ - ('attr', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('base', ctypes.c_uint64), +class NVOS32_PARAMETERS_data_Dump(Struct): pass +NVOS32_PARAMETERS_data_Dump._fields_ = [ + ('flags', NvU32), + ('pBuffer', NvP64), + ('numBlocks', NvU32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_Dump(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_Dump._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_Dump._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pBuffer', ctypes.POINTER(None)), - ('numBlocks', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS32_PARAMETERS_data_AllocSizeRange(Struct): pass +NVOS32_PARAMETERS_data_AllocSizeRange._fields_ = [ + ('owner', NvU32), + ('hMemory', NvHandle), + ('type', NvU32), + ('flags', NvU32), + ('attr', NvU32), + ('format', NvU32), + ('comprCovg', NvU32), + ('zcullCovg', NvU32), + ('partitionStride', NvU32), + ('size', NvU64), + ('alignment', NvU64), + ('offset', NvU64), + ('limit', NvU64), + ('rangeBegin', NvU64), + ('rangeEnd', NvU64), + ('address', NvP64), + ('attr2', NvU32), + ('ctagOffset', NvU32), + ('numaNode', NvS32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange._fields_ = [ - ('owner', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('partitionStride', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('rangeBegin', ctypes.c_uint64), - ('rangeEnd', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('attr2', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS32_PARAMETERS_data_AllocHintAlignment(Struct): pass +NVOS32_PARAMETERS_data_AllocHintAlignment._fields_ = [ + ('alignType', NvU32), + ('alignAttr', NvU32), + ('alignInputFlags', NvU32), + ('alignSize', NvU64), + ('alignHeight', NvU32), + ('alignWidth', NvU32), + ('alignPitch', NvU32), + ('alignPad', NvU32), + ('alignMask', NvU32), + ('alignOutputFlags', (NvU32 * 4)), + ('alignBank', (NvU32 * 4)), + ('alignKind', NvU32), + ('alignAdjust', NvU32), + ('alignAttr2', NvU32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment._fields_ = [ - ('alignType', ctypes.c_uint32), - ('alignAttr', ctypes.c_uint32), - ('alignInputFlags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('alignSize', ctypes.c_uint64), - ('alignHeight', ctypes.c_uint32), - ('alignWidth', ctypes.c_uint32), - ('alignPitch', ctypes.c_uint32), - ('alignPad', ctypes.c_uint32), - ('alignMask', ctypes.c_uint32), - ('alignOutputFlags', ctypes.c_uint32 * 4), - ('alignBank', ctypes.c_uint32 * 4), - ('alignKind', ctypes.c_uint32), - ('alignAdjust', ctypes.c_uint32), - ('alignAttr2', ctypes.c_uint32), +class NVOS32_PARAMETERS_data_HwAlloc(Struct): pass +class NVOS32_PARAMETERS_data_HwAlloc_comprInfo(Struct): pass +NVOS32_PARAMETERS_data_HwAlloc_comprInfo._fields_ = [ + ('compPageShift', NvU32), + ('compressedKind', NvU32), + ('compTagLineMin', NvU32), + ('compPageIndexLo', NvU32), + ('compPageIndexHi', NvU32), + ('compTagLineMultiplier', NvU32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc(Structure): - pass - -class struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo._fields_ = [ - ('compPageShift', ctypes.c_uint32), - ('compressedKind', ctypes.c_uint32), - ('compTagLineMin', ctypes.c_uint32), - ('compPageIndexLo', ctypes.c_uint32), - ('compPageIndexHi', ctypes.c_uint32), - ('compTagLineMultiplier', ctypes.c_uint32), +NVOS32_PARAMETERS_data_HwAlloc._fields_ = [ + ('allocOwner', NvU32), + ('allochMemory', NvHandle), + ('flags', NvU32), + ('allocType', NvU32), + ('allocAttr', NvU32), + ('allocInputFlags', NvU32), + ('allocSize', NvU64), + ('allocHeight', NvU32), + ('allocWidth', NvU32), + ('allocPitch', NvU32), + ('allocMask', NvU32), + ('allocComprCovg', NvU32), + ('allocZcullCovg', NvU32), + ('bindResultFunc', NvP64), + ('pHandle', NvP64), + ('hResourceHandle', NvHandle), + ('retAttr', NvU32), + ('kind', NvU32), + ('osDeviceHandle', NvU64), + ('allocAttr2', NvU32), + ('retAttr2', NvU32), + ('allocAddr', NvU64), + ('comprInfo', NVOS32_PARAMETERS_data_HwAlloc_comprInfo), + ('uncompressedKind', NvU32), ] - -struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc._fields_ = [ - ('allocOwner', ctypes.c_uint32), - ('allochMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('allocType', ctypes.c_uint32), - ('allocAttr', ctypes.c_uint32), - ('allocInputFlags', ctypes.c_uint32), - ('allocSize', ctypes.c_uint64), - ('allocHeight', ctypes.c_uint32), - ('allocWidth', ctypes.c_uint32), - ('allocPitch', ctypes.c_uint32), - ('allocMask', ctypes.c_uint32), - ('allocComprCovg', ctypes.c_uint32), - ('allocZcullCovg', ctypes.c_uint32), - ('bindResultFunc', ctypes.POINTER(None)), - ('pHandle', ctypes.POINTER(None)), - ('hResourceHandle', ctypes.c_uint32), - ('retAttr', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('osDeviceHandle', ctypes.c_uint64), - ('allocAttr2', ctypes.c_uint32), - ('retAttr2', ctypes.c_uint32), - ('allocAddr', ctypes.c_uint64), - ('comprInfo', struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo), - ('uncompressedKind', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS32_PARAMETERS_data_HwFree(Struct): pass +NVOS32_PARAMETERS_data_HwFree._fields_ = [ + ('hResourceHandle', NvHandle), + ('flags', NvU32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_HwFree(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_HwFree._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_HwFree._fields_ = [ - ('hResourceHandle', ctypes.c_uint32), - ('flags', ctypes.c_uint32), +class NVOS32_PARAMETERS_data_AllocOsDesc(Struct): pass +NVOS32_PARAMETERS_data_AllocOsDesc._fields_ = [ + ('hMemory', NvHandle), + ('type', NvU32), + ('flags', NvU32), + ('attr', NvU32), + ('attr2', NvU32), + ('descriptor', NvP64), + ('limit', NvU64), + ('descriptorType', NvU32), ] - -class struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc(Structure): - pass - -struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('descriptor', ctypes.POINTER(None)), - ('limit', ctypes.c_uint64), - ('descriptorType', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +NVOS32_PARAMETERS_data._fields_ = [ + ('AllocSize', NVOS32_PARAMETERS_data_AllocSize), + ('AllocTiledPitchHeight', NVOS32_PARAMETERS_data_AllocTiledPitchHeight), + ('Free', NVOS32_PARAMETERS_data_Free), + ('ReleaseCompr', NVOS32_PARAMETERS_data_ReleaseCompr), + ('ReacquireCompr', NVOS32_PARAMETERS_data_ReacquireCompr), + ('Info', NVOS32_PARAMETERS_data_Info), + ('Dump', NVOS32_PARAMETERS_data_Dump), + ('AllocSizeRange', NVOS32_PARAMETERS_data_AllocSizeRange), + ('AllocHintAlignment', NVOS32_PARAMETERS_data_AllocHintAlignment), + ('HwAlloc', NVOS32_PARAMETERS_data_HwAlloc), + ('HwFree', NVOS32_PARAMETERS_data_HwFree), + ('AllocOsDesc', NVOS32_PARAMETERS_data_AllocOsDesc), ] - -union_c__SA_NVOS32_PARAMETERS_data._pack_ = 1 # source:False -union_c__SA_NVOS32_PARAMETERS_data._fields_ = [ - ('AllocSize', struct_c__SA_NVOS32_PARAMETERS_0_AllocSize), - ('AllocTiledPitchHeight', struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight), - ('Free', struct_c__SA_NVOS32_PARAMETERS_0_Free), - ('ReleaseCompr', struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr), - ('ReacquireCompr', struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr), - ('Info', struct_c__SA_NVOS32_PARAMETERS_0_Info), - ('Dump', struct_c__SA_NVOS32_PARAMETERS_0_Dump), - ('AllocSizeRange', struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange), - ('AllocHintAlignment', struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment), - ('HwAlloc', struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc), - ('HwFree', struct_c__SA_NVOS32_PARAMETERS_0_HwFree), - ('AllocOsDesc', struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc), - ('PADDING_0', ctypes.c_ubyte * 96), +NVOS32_PARAMETERS._fields_ = [ + ('hRoot', NvHandle), + ('hObjectParent', NvHandle), + ('function', NvU32), + ('hVASpace', NvHandle), + ('ivcHeapNumber', NvS16), + ('status', NvV32), + ('total', NvU64), + ('free', NvU64), + ('data', NVOS32_PARAMETERS_data), ] - -struct_c__SA_NVOS32_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS32_PARAMETERS._fields_ = [ - ('hRoot', ctypes.c_uint32), - ('hObjectParent', ctypes.c_uint32), - ('function', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('ivcHeapNumber', ctypes.c_int16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('total', ctypes.c_uint64), - ('free', ctypes.c_uint64), - ('data', union_c__SA_NVOS32_PARAMETERS_data), +class NVOS32_HEAP_DUMP_BLOCK(Struct): pass +NVOS32_HEAP_DUMP_BLOCK._fields_ = [ + ('owner', NvU32), + ('format', NvU32), + ('begin', NvU64), + ('align', NvU64), + ('end', NvU64), ] - -NVOS32_PARAMETERS = struct_c__SA_NVOS32_PARAMETERS -class struct_c__SA_NVOS32_HEAP_DUMP_BLOCK(Structure): - pass - -struct_c__SA_NVOS32_HEAP_DUMP_BLOCK._pack_ = 1 # source:False -struct_c__SA_NVOS32_HEAP_DUMP_BLOCK._fields_ = [ - ('owner', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('begin', ctypes.c_uint64), - ('align', ctypes.c_uint64), - ('end', ctypes.c_uint64), +class NV_CONTEXT_DMA_ALLOCATION_PARAMS(Struct): pass +NV_CONTEXT_DMA_ALLOCATION_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('flags', NvV32), + ('hMemory', NvHandle), + ('offset', NvU64), + ('limit', NvU64), ] - -NVOS32_HEAP_DUMP_BLOCK = struct_c__SA_NVOS32_HEAP_DUMP_BLOCK -class struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), +class NV_MEMORY_ALLOCATION_PARAMS(Struct): pass +NV_MEMORY_ALLOCATION_PARAMS._fields_ = [ + ('owner', NvU32), + ('type', NvU32), + ('flags', NvU32), + ('width', NvU32), + ('height', NvU32), + ('pitch', NvS32), + ('attr', NvU32), + ('attr2', NvU32), + ('format', NvU32), + ('comprCovg', NvU32), + ('zcullCovg', NvU32), + ('rangeLo', NvU64), + ('rangeHi', NvU64), + ('size', NvU64), + ('alignment', NvU64), + ('offset', NvU64), + ('limit', NvU64), + ('address', NvP64), + ('ctagOffset', NvU32), + ('hVASpace', NvHandle), + ('internalflags', NvU32), + ('tag', NvU32), + ('numaNode', NvS32), ] - -NV_CONTEXT_DMA_ALLOCATION_PARAMS = struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS -class struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS._fields_ = [ - ('owner', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('pitch', ctypes.c_int32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('format', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('rangeLo', ctypes.c_uint64), - ('rangeHi', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('address', ctypes.POINTER(None)), - ('ctagOffset', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('internalflags', ctypes.c_uint32), - ('tag', ctypes.c_uint32), - ('numaNode', ctypes.c_int32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NV_OS_DESC_MEMORY_ALLOCATION_PARAMS(Struct): pass +NV_OS_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [ + ('type', NvU32), + ('flags', NvU32), + ('attr', NvU32), + ('attr2', NvU32), + ('descriptor', NvP64), + ('limit', NvU64), + ('descriptorType', NvU32), + ('tag', NvU32), ] - -NV_MEMORY_ALLOCATION_PARAMS = struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS -class struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [ - ('type', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('descriptor', ctypes.POINTER(None)), - ('limit', ctypes.c_uint64), - ('descriptorType', ctypes.c_uint32), - ('tag', ctypes.c_uint32), +class NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS(Struct): pass +NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [ + ('flags', NvU32), + ('physAddr', NvU64), + ('size', NvU64), + ('tag', NvU32), + ('bGuestAllocated', NvBool), ] - -NV_OS_DESC_MEMORY_ALLOCATION_PARAMS = struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS -class struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('tag', ctypes.c_uint32), - ('bGuestAllocated', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), +class NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS(Struct): pass +NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS._fields_ = [ + ('owner', NvU32), + ('flags', NvU32), + ('type', NvU32), + ('attr', NvU32), + ('attr2', NvU32), + ('height', NvU32), + ('width', NvU32), + ('pitch', NvU32), + ('alignment', NvU32), + ('comprCovg', NvU32), + ('zcullCovg', NvU32), + ('kind', NvU32), + ('bindResultFunc', NvP64), + ('pHandle', NvP64), + ('osDeviceHandle', NvU64), + ('size', NvU64), + ('allocAddr', NvU64), + ('compPageShift', NvU32), + ('compressedKind', NvU32), + ('compTagLineMin', NvU32), + ('compPageIndexLo', NvU32), + ('compPageIndexHi', NvU32), + ('compTagLineMultiplier', NvU32), + ('uncompressedKind', NvU32), + ('tag', NvU32), ] - -NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS = struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS -class struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS._fields_ = [ - ('owner', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('pitch', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), - ('comprCovg', ctypes.c_uint32), - ('zcullCovg', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('bindResultFunc', ctypes.POINTER(None)), - ('pHandle', ctypes.POINTER(None)), - ('osDeviceHandle', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('allocAddr', ctypes.c_uint64), - ('compPageShift', ctypes.c_uint32), - ('compressedKind', ctypes.c_uint32), - ('compTagLineMin', ctypes.c_uint32), - ('compPageIndexLo', ctypes.c_uint32), - ('compPageIndexHi', ctypes.c_uint32), - ('compTagLineMultiplier', ctypes.c_uint32), - ('uncompressedKind', ctypes.c_uint32), - ('tag', ctypes.c_uint32), +class NVOS34_PARAMETERS(Struct): pass +NVOS34_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hMemory', NvHandle), + ('pLinearAddress', NvP64), + ('status', NvU32), + ('flags', NvU32), ] - -NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS = struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS -class struct_c__SA_NVOS33_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS33_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS33_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('pLinearAddress', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('flags', ctypes.c_uint32), +class NVOS38_PARAMETERS(Struct): pass +NVOS38_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('AccessType', NvV32), + ('DevNodeLength', NvV32), + ('pDevNode', NvP64), + ('ParmStrLength', NvV32), + ('pParmStr', NvP64), + ('BinaryDataLength', NvV32), + ('pBinaryData', NvP64), + ('Data', NvV32), + ('Entry', NvV32), + ('status', NvV32), ] - -NVOS33_PARAMETERS = struct_c__SA_NVOS33_PARAMETERS -class struct_c__SA_NVOS34_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS34_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS34_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pLinearAddress', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('flags', ctypes.c_uint32), +class NVOS39_PARAMETERS(Struct): pass +NVOS39_PARAMETERS._fields_ = [ + ('hObjectParent', NvHandle), + ('hSubDevice', NvHandle), + ('hObjectNew', NvHandle), + ('hClass', NvV32), + ('flags', NvV32), + ('selector', NvU32), + ('hMemory', NvHandle), + ('offset', NvU64), + ('limit', NvU64), + ('status', NvV32), ] - -NVOS34_PARAMETERS = struct_c__SA_NVOS34_PARAMETERS -class struct_c__SA_NVOS38_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS38_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS38_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('AccessType', ctypes.c_uint32), - ('DevNodeLength', ctypes.c_uint32), - ('pDevNode', ctypes.POINTER(None)), - ('ParmStrLength', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pParmStr', ctypes.POINTER(None)), - ('BinaryDataLength', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pBinaryData', ctypes.POINTER(None)), - ('Data', ctypes.c_uint32), - ('Entry', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), +class NvUnixEvent(Struct): pass +NvUnixEvent._fields_ = [ + ('hObject', NvHandle), + ('NotifyIndex', NvV32), + ('info32', NvV32), + ('info16', NvU16), ] - -NVOS38_PARAMETERS = struct_c__SA_NVOS38_PARAMETERS -class struct_c__SA_NVOS39_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS39_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS39_PARAMETERS._fields_ = [ - ('hObjectParent', ctypes.c_uint32), - ('hSubDevice', ctypes.c_uint32), - ('hObjectNew', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('selector', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS41_PARAMETERS(Struct): pass +NVOS41_PARAMETERS._fields_ = [ + ('pEvent', NvP64), + ('MoreEvents', NvV32), + ('status', NvV32), ] - -NVOS39_PARAMETERS = struct_c__SA_NVOS39_PARAMETERS -class struct_c__SA_NvUnixEvent(Structure): - pass - -struct_c__SA_NvUnixEvent._pack_ = 1 # source:False -struct_c__SA_NvUnixEvent._fields_ = [ - ('hObject', ctypes.c_uint32), - ('NotifyIndex', ctypes.c_uint32), - ('info32', ctypes.c_uint32), - ('info16', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), +class NVOS2C_PARAMETERS(Struct): pass +NVOS2C_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('offset', NvU32), + ('bar', NvU32), + ('bytes', NvU32), + ('write', NvU32), + ('data', NvU32), + ('status', NvU32), ] - -NvUnixEvent = struct_c__SA_NvUnixEvent -class struct_c__SA_NVOS41_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS41_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS41_PARAMETERS._fields_ = [ - ('pEvent', ctypes.POINTER(None)), - ('MoreEvents', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS46_PARAMETERS(Struct): pass +NVOS46_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hDma', NvHandle), + ('hMemory', NvHandle), + ('offset', NvU64), + ('length', NvU64), + ('flags', NvV32), + ('dmaOffset', NvU64), + ('status', NvV32), ] - -NVOS41_PARAMETERS = struct_c__SA_NVOS41_PARAMETERS -class struct_c__SA_NVOS2C_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS2C_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS2C_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('bar', ctypes.c_uint32), - ('bytes', ctypes.c_uint32), - ('write', ctypes.c_uint32), - ('data', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS47_PARAMETERS(Struct): pass +NVOS47_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hDma', NvHandle), + ('hMemory', NvHandle), + ('flags', NvV32), + ('dmaOffset', NvU64), + ('size', NvU64), + ('status', NvV32), ] - -NVOS2C_PARAMETERS = struct_c__SA_NVOS2C_PARAMETERS -class struct_c__SA_NVOS46_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS46_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS46_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hDma', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dmaOffset', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS49_PARAMETERS(Struct): pass +NVOS49_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('hCtxDma', NvHandle), + ('status', NvV32), ] - -NVOS46_PARAMETERS = struct_c__SA_NVOS46_PARAMETERS -class struct_c__SA_NVOS47_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS47_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS47_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hDma', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('dmaOffset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), +class NVOS54_PARAMETERS(Struct): pass +NVOS54_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvV32), + ('flags', NvU32), + ('params', NvP64), + ('paramsSize', NvU32), + ('status', NvV32), ] - -NVOS47_PARAMETERS = struct_c__SA_NVOS47_PARAMETERS -class struct_c__SA_NVOS49_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS49_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS49_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('hCtxDma', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS63_PARAMETERS(Struct): pass +NVOS63_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('cmd', NvV32), + ('paramsSize', NvU32), + ('status', NvV32), ] - -NVOS49_PARAMETERS = struct_c__SA_NVOS49_PARAMETERS -class struct_c__SA_NVOS54_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS54_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS54_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('params', ctypes.POINTER(None)), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS55_PARAMETERS(Struct): pass +NVOS55_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), + ('hClientSrc', NvHandle), + ('hObjectSrc', NvHandle), + ('flags', NvU32), + ('status', NvU32), ] - -NVOS54_PARAMETERS = struct_c__SA_NVOS54_PARAMETERS -class struct_c__SA_NVOS63_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS63_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS63_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('paramsSize', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS56_PARAMETERS(Struct): pass +NVOS56_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hMemory', NvHandle), + ('pOldCpuAddress', NvP64), + ('pNewCpuAddress', NvP64), + ('status', NvV32), ] - -NVOS63_PARAMETERS = struct_c__SA_NVOS63_PARAMETERS -class struct_c__SA_NVOS55_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS55_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS55_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hClientSrc', ctypes.c_uint32), - ('hObjectSrc', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NVOS55_PARAMETERS = struct_c__SA_NVOS55_PARAMETERS -class struct_c__SA_NVOS56_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS56_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS56_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pOldCpuAddress', ctypes.POINTER(None)), - ('pNewCpuAddress', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NVOS56_PARAMETERS = struct_c__SA_NVOS56_PARAMETERS -class struct_c__SA_NVOS57_PARAMETERS(Structure): - pass - -class struct_RS_SHARE_POLICY(Structure): - pass - -class struct_RS_ACCESS_MASK(Structure): - pass - -struct_RS_ACCESS_MASK._pack_ = 1 # source:False +class NVOS57_PARAMETERS(Struct): pass +class struct_RS_SHARE_POLICY(Struct): pass +RS_SHARE_POLICY = struct_RS_SHARE_POLICY +class struct_RS_ACCESS_MASK(Struct): pass +RS_ACCESS_MASK = struct_RS_ACCESS_MASK +RsAccessLimb = ctypes.c_uint32 struct_RS_ACCESS_MASK._fields_ = [ - ('limbs', ctypes.c_uint32 * 1), + ('limbs', (RsAccessLimb * 1)), ] - -struct_RS_SHARE_POLICY._pack_ = 1 # source:False struct_RS_SHARE_POLICY._fields_ = [ - ('target', ctypes.c_uint32), - ('accessMask', struct_RS_ACCESS_MASK), - ('type', ctypes.c_uint16), - ('action', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), + ('target', NvU32), + ('accessMask', RS_ACCESS_MASK), + ('type', NvU16), + ('action', NvU8), ] - -struct_c__SA_NVOS57_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS57_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('sharePolicy', struct_RS_SHARE_POLICY), - ('status', ctypes.c_uint32), +NVOS57_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hObject', NvHandle), + ('sharePolicy', RS_SHARE_POLICY), + ('status', NvU32), ] - -NVOS57_PARAMETERS = struct_c__SA_NVOS57_PARAMETERS -class struct_c__SA_NVPOWERSTATE_PARAMETERS(Structure): - pass - -struct_c__SA_NVPOWERSTATE_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVPOWERSTATE_PARAMETERS._fields_ = [ - ('deviceReference', ctypes.c_uint32), - ('head', ctypes.c_uint32), - ('state', ctypes.c_uint32), - ('forceMonitorState', ctypes.c_ubyte), - ('bForcePerfBiosLevel', ctypes.c_ubyte), - ('bIsD3HotTransition', ctypes.c_ubyte), - ('bForcePowerStateFail', ctypes.c_ubyte), - ('errorStatus', ctypes.c_uint32), - ('fastBootPowerState', ctypes.c_uint32), - ('bGC8Transition', ctypes.c_ubyte), - ('bGC8InputRailCutOff', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), +class NVPOWERSTATE_PARAMETERS(Struct): pass +NVPOWERSTATE_PARAMETERS._fields_ = [ + ('deviceReference', NvU32), + ('head', NvU32), + ('state', NvU32), + ('forceMonitorState', NvU8), + ('bForcePerfBiosLevel', NvU8), + ('bIsD3HotTransition', NvU8), + ('bForcePowerStateFail', NvU8), + ('errorStatus', NvU32), + ('fastBootPowerState', NvU32), + ('bGC8Transition', NvU8), + ('bGC8InputRailCutOff', NvU8), ] - -NVPOWERSTATE_PARAMETERS = struct_c__SA_NVPOWERSTATE_PARAMETERS -PNVPOWERSTATE_PARAMETERS = ctypes.POINTER(struct_c__SA_NVPOWERSTATE_PARAMETERS) -class struct_c__SA_NV_GR_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_GR_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_GR_ALLOCATION_PARAMETERS._fields_ = [ - ('version', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), +PNVPOWERSTATE_PARAMETERS = ctypes.POINTER(NVPOWERSTATE_PARAMETERS) +class NV_GR_ALLOCATION_PARAMETERS(Struct): pass +NV_GR_ALLOCATION_PARAMETERS._fields_ = [ + ('version', NvU32), + ('flags', NvU32), + ('size', NvU32), + ('caps', NvU32), ] +ChannelPBSize = CEnum(ctypes.c_uint32) +PB_SIZE_4KB = ChannelPBSize.define('PB_SIZE_4KB', 0) +PB_SIZE_8KB = ChannelPBSize.define('PB_SIZE_8KB', 1) +PB_SIZE_16KB = ChannelPBSize.define('PB_SIZE_16KB', 2) +PB_SIZE_32KB = ChannelPBSize.define('PB_SIZE_32KB', 3) +PB_SIZE_64KB = ChannelPBSize.define('PB_SIZE_64KB', 4) -NV_GR_ALLOCATION_PARAMETERS = struct_c__SA_NV_GR_ALLOCATION_PARAMETERS - -# values for enumeration 'c__EA_ChannelPBSize' -c__EA_ChannelPBSize__enumvalues = { - 0: 'PB_SIZE_4KB', - 1: 'PB_SIZE_8KB', - 2: 'PB_SIZE_16KB', - 3: 'PB_SIZE_32KB', - 4: 'PB_SIZE_64KB', -} -PB_SIZE_4KB = 0 -PB_SIZE_8KB = 1 -PB_SIZE_16KB = 2 -PB_SIZE_32KB = 3 -PB_SIZE_64KB = 4 -c__EA_ChannelPBSize = ctypes.c_uint32 # enum -ChannelPBSize = c__EA_ChannelPBSize -ChannelPBSize__enumvalues = c__EA_ChannelPBSize__enumvalues -class struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS._fields_ = [ - ('channelInstance', ctypes.c_uint32), - ('hObjectBuffer', ctypes.c_uint32), - ('hObjectNotify', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('pControl', ctypes.POINTER(None)), - ('flags', ctypes.c_uint32), - ('channelPBSize', ChannelPBSize), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +class NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS(Struct): pass +NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS._fields_ = [ + ('channelInstance', NvV32), + ('hObjectBuffer', NvHandle), + ('hObjectNotify', NvHandle), + ('offset', NvU32), + ('pControl', NvP64), + ('flags', NvU32), + ('channelPBSize', ChannelPBSize), + ('subDeviceId', NvU32), ] - -NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS = struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS -class struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS._fields_ = [ - ('channelInstance', ctypes.c_uint32), - ('hObjectNotify', ctypes.c_uint32), - ('pControl', ctypes.POINTER(None)), +class NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS(Struct): pass +NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS._fields_ = [ + ('channelInstance', NvV32), + ('hObjectNotify', NvHandle), + ('pControl', NvP64), ] - -NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS = struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS -class struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS._fields_ = [ - ('hObjectError', ctypes.c_uint32), - ('hObjectEccError', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('engineType', ctypes.c_uint32), - ('bIsCallingContextVgpuPlugin', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), +class NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(Struct): pass +NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS._fields_ = [ + ('hObjectError', NvHandle), + ('hObjectEccError', NvHandle), + ('hVASpace', NvHandle), + ('engineType', NvU32), + ('bIsCallingContextVgpuPlugin', NvBool), ] - -NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS = struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('maxTSGs', ctypes.c_uint32), - ('qosIntrEnableMask', ctypes.c_uint32), +class NV_SWRUNLIST_ALLOCATION_PARAMS(Struct): pass +NV_SWRUNLIST_ALLOCATION_PARAMS._fields_ = [ + ('engineId', NvU32), + ('maxTSGs', NvU32), + ('qosIntrEnableMask', NvU32), ] - -NV_SWRUNLIST_ALLOCATION_PARAMS = struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS -class struct_c__SA_NV_ME_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_ME_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_ME_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), +class NV_ME_ALLOCATION_PARAMETERS(Struct): pass +NV_ME_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('caps', NvU32), ] - -NV_ME_ALLOCATION_PARAMETERS = struct_c__SA_NV_ME_ALLOCATION_PARAMETERS -class struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), +class NV_BSP_ALLOCATION_PARAMETERS(Struct): pass +NV_BSP_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), ] - -NV_BSP_ALLOCATION_PARAMETERS = struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_VP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_VP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_VP_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('caps', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('altUcode', ctypes.c_uint32), - ('rawUcode', ctypes.POINTER(None)), - ('rawUcodeSize', ctypes.c_uint32), - ('numSubClasses', ctypes.c_uint32), - ('numSubSets', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('subClasses', ctypes.POINTER(None)), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pControl', ctypes.POINTER(None)), - ('hMemoryCmdBuffer', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), +class NV_VP_ALLOCATION_PARAMETERS(Struct): pass +NV_VP_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('caps', NvU32), + ('flags', NvU32), + ('altUcode', NvU32), + ('rawUcode', NvP64), + ('rawUcodeSize', NvU32), + ('numSubClasses', NvU32), + ('numSubSets', NvU32), + ('subClasses', NvP64), + ('prohibitMultipleInstances', NvU32), + ('pControl', NvP64), + ('hMemoryCmdBuffer', NvHandle), + ('offset', NvU64), ] - -NV_VP_ALLOCATION_PARAMETERS = struct_c__SA_NV_VP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), +class NV_PPP_ALLOCATION_PARAMETERS(Struct): pass +NV_PPP_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), ] - -NV_PPP_ALLOCATION_PARAMETERS = struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS -class struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), +class NV_MSENC_ALLOCATION_PARAMETERS(Struct): pass +NV_MSENC_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), ] - -NV_MSENC_ALLOCATION_PARAMETERS = struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS -class struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), +class NV_SEC2_ALLOCATION_PARAMETERS(Struct): pass +NV_SEC2_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), ] - -NV_SEC2_ALLOCATION_PARAMETERS = struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS -class struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), +class NV_NVJPG_ALLOCATION_PARAMETERS(Struct): pass +NV_NVJPG_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), ] - -NV_NVJPG_ALLOCATION_PARAMETERS = struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS -class struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS._fields_ = [ - ('size', ctypes.c_uint32), - ('prohibitMultipleInstances', ctypes.c_uint32), - ('engineInstance', ctypes.c_uint32), +class NV_OFA_ALLOCATION_PARAMETERS(Struct): pass +NV_OFA_ALLOCATION_PARAMETERS._fields_ = [ + ('size', NvU32), + ('prohibitMultipleInstances', NvU32), + ('engineInstance', NvU32), ] - -NV_OFA_ALLOCATION_PARAMETERS = struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS -class struct_c__SA_NVOS61_PARAMETERS(Structure): - pass - -struct_c__SA_NVOS61_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NVOS61_PARAMETERS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hVblank', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pProc', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.POINTER(None))), - ('LogicalHead', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('pParm1', ctypes.POINTER(None)), - ('pParm2', ctypes.POINTER(None)), - ('bAdd', ctypes.c_uint32), - ('status', ctypes.c_uint32), +class NVOS61_PARAMETERS(Struct): pass +OSVBLANKCALLBACKPROC = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_void_p) +NVOS61_PARAMETERS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hVblank', NvHandle), + ('pProc', OSVBLANKCALLBACKPROC), + ('LogicalHead', NvV32), + ('pParm1', ctypes.c_void_p), + ('pParm2', ctypes.c_void_p), + ('bAdd', NvU32), + ('status', NvV32), ] - -NVOS61_PARAMETERS = struct_c__SA_NVOS61_PARAMETERS -class struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS._fields_ = [ - ('index', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaSize', ctypes.c_uint64), - ('vaStartInternal', ctypes.c_uint64), - ('vaLimitInternal', ctypes.c_uint64), - ('bigPageSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vaBase', ctypes.c_uint64), +class NV_VASPACE_ALLOCATION_PARAMETERS(Struct): pass +NV_VASPACE_ALLOCATION_PARAMETERS._fields_ = [ + ('index', NvU32), + ('flags', NvV32), + ('vaSize', NvU64), + ('vaStartInternal', NvU64), + ('vaLimitInternal', NvU64), + ('bigPageSize', NvU32), + ('vaBase', NvU64), ] - -NV_VASPACE_ALLOCATION_PARAMETERS = struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS -class struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS(Structure): - pass - -struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('subctxId', ctypes.c_uint32), +class NV_CTXSHARE_ALLOCATION_PARAMETERS(Struct): pass +NV_CTXSHARE_ALLOCATION_PARAMETERS._fields_ = [ + ('hVASpace', NvHandle), + ('flags', NvU32), + ('subctxId', NvU32), ] - -NV_CTXSHARE_ALLOCATION_PARAMETERS = struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS -class struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS(Structure): - pass - -struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS._pack_ = 1 # source:False -struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('timeoutInMs', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), +class NV_TIMEOUT_CONTROL_PARAMETERS(Struct): pass +NV_TIMEOUT_CONTROL_PARAMETERS._fields_ = [ + ('cmd', NvU32), + ('timeoutInMs', NvU32), + ('deviceInstance', NvU32), ] +NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE = CEnum(ctypes.c_uint32) +NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', 0) +NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', 1) +NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', 2) +NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', 3) -NV_TIMEOUT_CONTROL_PARAMETERS = struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS - -# values for enumeration 'c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE' -c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues = { - 0: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', - 1: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', - 2: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', - 3: 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', -} -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = 0 -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH = 1 -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH = 2 -NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID = 3 -c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE = ctypes.c_uint32 # enum -NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE = c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE -NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues = c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues -class struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS(Structure): - pass - -struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS._fields_ = [ - ('bDirtyTracking', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('granularity', ctypes.c_uint32), - ('accessBitMask', ctypes.c_uint64 * 64), - ('noOfEntries', ctypes.c_uint32), - ('addrSpace', NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE), +class NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS(Struct): pass +NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS._fields_ = [ + ('bDirtyTracking', NvBool), + ('granularity', NvU32), + ('accessBitMask', (NvU64 * 64)), + ('noOfEntries', NvU32), + ('addrSpace', NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE), ] - -NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS = struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS -class struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS(Structure): - pass - -struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS._pack_ = 1 # source:False -struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS._fields_ = [ - ('bBar1Mapping', ctypes.c_ubyte), - ('bPriv', ctypes.c_ubyte), +class NV_HOPPER_USERMODE_A_PARAMS(Struct): pass +NV_HOPPER_USERMODE_A_PARAMS._fields_ = [ + ('bBar1Mapping', NvBool), + ('bPriv', NvBool), ] - -NV_HOPPER_USERMODE_A_PARAMS = struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS -class struct_c__SA_nv_ioctl_nvos02_parameters_with_fd(Structure): - pass - -struct_c__SA_nv_ioctl_nvos02_parameters_with_fd._pack_ = 1 # source:False -struct_c__SA_nv_ioctl_nvos02_parameters_with_fd._fields_ = [ - ('params', NVOS02_PARAMETERS), - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), +class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS(Struct): pass +struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS._fields_ = [ + ('workSubmitToken', NvU32), ] - -nv_ioctl_nvos02_parameters_with_fd = struct_c__SA_nv_ioctl_nvos02_parameters_with_fd -class struct_c__SA_nv_ioctl_nvos33_parameters_with_fd(Structure): - pass - -struct_c__SA_nv_ioctl_nvos33_parameters_with_fd._pack_ = 1 # source:False -struct_c__SA_nv_ioctl_nvos33_parameters_with_fd._fields_ = [ - ('params', NVOS33_PARAMETERS), - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), +NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS +class struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS(Struct): pass +struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS._fields_ = [ + ('bar2Addr', (NvU64 * 2)), ] +NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS = struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS +class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS(Struct): pass +struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS._fields_ = [ + ('index', NvU32), +] +NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS +NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS._fields_ = [ + ('cpuCapability', NvU8), + ('gpusCapability', NvU8), + ('environment', NvU8), + ('ccFeature', NvU8), + ('devToolsMode', NvU8), + ('multiGpuMode', NvU8), +] +NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS._fields_ = [ + ('bAcceptClientRequest', NvBool), +] +NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS._fields_ = [ + ('bAcceptClientRequest', NvBool), +] +NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('protectedMemSizeInKb', NvU64), + ('unprotectedMemSizeInKb', NvU64), +] +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('protectedMemSizeInKb', NvU64), + ('unprotectedMemSizeInKb', NvU64), +] +NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('numSupportedSec2CCSecureChannels', NvU32), + ('numSupportedCeCCSecureChannels', NvU32), +] +NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('certChain', (NvU8 * 4096)), + ('certChainSize', NvU32), + ('attestationCertChain', (NvU8 * 5120)), + ('attestationCertChainSize', NvU32), +] +NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('nonce', (NvU8 * 32)), + ('attestationReport', (NvU8 * 8192)), + ('attestationReportSize', NvU32), + ('isCecAttestationReportPresent', NvBool), + ('cecAttestationReport', (NvU8 * 4096)), + ('cecAttestationReportSize', NvU32), +] +NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('maxSec2Channels', NvU32), + ('maxCeChannels', NvU32), +] +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS +class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS(Struct): pass +struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('keyRotationState', NvU32), +] +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS +class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS(Struct): pass +NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS +struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS._fields_ = [ + ('bEnable', NvBool), + ('bSkipSubmit', NvBool), +] +class struct_NVA06F_CTRL_BIND_PARAMS(Struct): pass +NVA06C_CTRL_BIND_PARAMS = struct_NVA06F_CTRL_BIND_PARAMS +struct_NVA06F_CTRL_BIND_PARAMS._fields_ = [ + ('engineType', NvU32), +] +class struct_NVA06C_CTRL_TIMESLICE_PARAMS(Struct): pass +struct_NVA06C_CTRL_TIMESLICE_PARAMS._fields_ = [ + ('timesliceUs', NvU64), +] +NVA06C_CTRL_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS +NVA06C_CTRL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS +NVA06C_CTRL_GET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS +class struct_NVA06C_CTRL_PREEMPT_PARAMS(Struct): pass +struct_NVA06C_CTRL_PREEMPT_PARAMS._fields_ = [ + ('bWait', NvBool), + ('bManualTimeout', NvBool), + ('timeoutUs', NvU32), +] +NVA06C_CTRL_PREEMPT_PARAMS = struct_NVA06C_CTRL_PREEMPT_PARAMS +class struct_NVA06C_CTRL_GET_INFO_PARAMS(Struct): pass +struct_NVA06C_CTRL_GET_INFO_PARAMS._fields_ = [ + ('tsgID', NvU32), +] +NVA06C_CTRL_GET_INFO_PARAMS = struct_NVA06C_CTRL_GET_INFO_PARAMS +class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS(Struct): pass +struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS._fields_ = [ + ('tsgInterleaveLevel', NvU32), +] +NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS +NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS +NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS +enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE = CEnum(ctypes.c_uint32) +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', 0) +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', 1) +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', 2) -nv_ioctl_nvos33_parameters_with_fd = struct_c__SA_nv_ioctl_nvos33_parameters_with_fd -# def NV0000_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx) -NV0000_CTRL_RESERVED = (0x00) # macro -NV0000_CTRL_SYSTEM = (0x01) # macro -NV0000_CTRL_GPU = (0x02) # macro -NV0000_CTRL_GSYNC = (0x03) # macro -NV0000_CTRL_DIAG = (0x04) # macro -NV0000_CTRL_EVENT = (0x05) # macro -NV0000_CTRL_NVD = (0x06) # macro -NV0000_CTRL_SWINSTR = (0x07) # macro -NV0000_CTRL_PROC = (0x09) # macro -NV0000_CTRL_SYNC_GPU_BOOST = (0x0A) # macro -NV0000_CTRL_GPUACCT = (0x0B) # macro -NV0000_CTRL_VGPU = (0x0C) # macro -NV0000_CTRL_CLIENT = (0x0D) # macro -NV0000_CTRL_OS_WINDOWS = (0x3F) # macro -NV0000_CTRL_OS_MACOS = (0x3E) # macro -NV0000_CTRL_OS_UNIX = (0x3D) # macro -NV0000_CTRL_CMD_NULL = (0x0) # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = (0xd01) # macro -NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID = 0x00000000 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM = 0x00000001 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM = 0x00000002 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM = 0x00000003 # macro -NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC = 0x00000004 # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO = (0xd02) # macro -NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID = 0x00000000 # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT = 0x00000001 # macro -NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID = 0x00000002 # macro -NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS = (0xd03) # macro -NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = (0xd04) # macro -NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE = (0xd05) # macro -NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID = (0x5) # macro -NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT = (0xd06) # macro -NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID = (0x6) # macro -NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES = (0xd07) # macro -NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID = (0x7) # macro -NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL = (0xd08) # macro -NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS._pack_ = 1 # source:False +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE +class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD(Struct): pass +struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD._fields_ = [ + ('size', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE), +] +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD +class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS(Struct): pass +struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS._fields_ = [ + ('l1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD), + ('t1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD), +] +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS +class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS(Struct): pass +class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO(Struct): pass +NV2080_CTRL_INTERNAL_MEMDESC_INFO = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO +struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO._fields_ = [ + ('base', NvU64), + ('size', NvU64), + ('alignment', NvU64), + ('addressSpace', NvU32), + ('cpuCacheAttrib', NvU32), +] +struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS._fields_ = [ + ('methodBufferMemdesc', (NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2)), + ('bar2Addr', (NvU64 * 2)), + ('numValidEntries', NvU32), +] +NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS +class struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS(Struct): pass +struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS._fields_ = [ + ('bRealtime', NvBool), +] +NVA06C_CTRL_MAKE_REALTIME_PARAMS = struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS +NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS +NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS +class struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS(Struct): pass +struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('pFmt', NvP64), +] +NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS +class struct_NV_CTRL_VASPACE_PAGE_LEVEL(Struct): pass +class struct_MMU_FMT_LEVEL(Struct): pass +struct_MMU_FMT_LEVEL._fields_ = [ + ('virtAddrBitLo', NvU8), + ('virtAddrBitHi', NvU8), + ('entrySize', NvU8), + ('bPageTable', NvBool), + ('numSubLevels', NvU8), + ('pageLevelIdTag', NvU32), + ('subLevels', ctypes.POINTER(struct_MMU_FMT_LEVEL)), +] +MMU_FMT_LEVEL = struct_MMU_FMT_LEVEL +struct_NV_CTRL_VASPACE_PAGE_LEVEL._fields_ = [ + ('pFmt', ctypes.POINTER(struct_MMU_FMT_LEVEL)), + ('levelFmt', MMU_FMT_LEVEL), + ('sublevelFmt', (MMU_FMT_LEVEL * 2)), + ('physAddress', NvU64), + ('aperture', NvU32), + ('size', NvU64), + ('entryIndex', NvU32), +] +NV_CTRL_VASPACE_PAGE_LEVEL = struct_NV_CTRL_VASPACE_PAGE_LEVEL +class struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS(Struct): pass +struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('virtAddress', NvU64), + ('pageSize', NvU64), + ('flags', NvU64), + ('numLevels', NvU32), + ('levels', (NV_CTRL_VASPACE_PAGE_LEVEL * 6)), +] +NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS +class struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS(Struct): pass +struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('pageSize', NvU64), + ('virtAddrLo', NvU64), + ('virtAddrHi', NvU64), +] +NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS +class struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS(Struct): pass +struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('pageSize', NvU64), + ('virtAddrLo', NvU64), + ('virtAddrHi', NvU64), +] +NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS +NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS +class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(Struct): pass +class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level(Struct): pass +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level._fields_ = [ + ('physAddress', NvU64), + ('size', NvU64), + ('aperture', NvU32), + ('pageShift', NvU8), +] +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('pageSize', NvU64), + ('virtAddrLo', NvU64), + ('virtAddrHi', NvU64), + ('numLevelsToCopy', NvU32), + ('levels', (struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level * 6)), +] +NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS +class struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS(Struct): pass +struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('requiredVaRange', NvU64), +] +NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS +class struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS(Struct): pass +struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS._fields_ = [ + ('hSubDevice', NvHandle), + ('subDeviceId', NvU32), + ('bytesFree', NvU64), + ('bytesTotal', NvU64), + ('largestFreeOffset', NvU64), + ('largestFreeSize', NvU64), + ('usableBytesFree', NvU64), + ('numFreeBlocks', NvU32), +] +NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS +class struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS(Struct): pass struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('mapFlags', ctypes.c_uint32), - ('addrSpaceType', ctypes.c_uint32), + ('hObject', NvHandle), + ('mapFlags', NvU32), + ('addrSpaceType', NvU32), ] - NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS = struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS -class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS(Structure): - pass - -class union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data(Union): - pass - -union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data._pack_ = 1 # source:False -union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data._fields_ = [ - ('hResult', ctypes.c_uint32), - ('iResult', ctypes.c_uint64), +class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS(Struct): pass +class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data(ctypes.Union): pass +struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data._fields_ = [ + ('hResult', NvHandle), + ('iResult', NvU64), ] - -struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS._pack_ = 1 # source:False struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('data', union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data), + ('hObject', NvHandle), + ('index', NvU32), + ('data', struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data), ] - NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS = struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS -class struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS(Struct): pass struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('maskResult', struct_RS_ACCESS_MASK), + ('hObject', NvHandle), + ('hClient', NvHandle), + ('maskResult', RS_ACCESS_MASK), ] - NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS = struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS -class struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('sharePolicy', struct_RS_SHARE_POLICY), - ] - +class struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS(Struct): pass +struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS._fields_ = [ + ('sharePolicy', RS_SHARE_POLICY), +] NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS = struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS -class struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS(Struct): pass struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS._fields_ = [ - ('hParent', ctypes.c_uint32), - ('classId', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), + ('hParent', NvHandle), + ('classId', NvU32), + ('hObject', NvHandle), ] - NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS = struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS -class struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS(Struct): pass struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS._fields_ = [ - ('hObject', ctypes.c_uint32), - ('sharePolicy', struct_RS_SHARE_POLICY), + ('hObject', NvHandle), + ('sharePolicy', RS_SHARE_POLICY), ] - NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS = struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS -class struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS(Struct): pass struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS._fields_ = [ - ('hObject1', ctypes.c_uint32), - ('hObject2', ctypes.c_uint32), - ('bDuplicates', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('hObject1', NvHandle), + ('hObject2', NvHandle), + ('bDuplicates', NvBool), ] - NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS = struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS -class struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS(Struct): pass struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS._fields_ = [ - ('devDescriptor', ctypes.c_uint64), - ('channel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('devDescriptor', NvU64), + ('channel', NvU32), ] - NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS = struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS -NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE = (0x480) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x80) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED = (0x00000000) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED = (0x00000001) # macro -NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES = (0x20000) # macro -NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE = (0x481) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x81) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE = (0x00000000) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE = (0x00000001) # macro -NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET = (0x00000002) # macro -NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH = (0xc) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA = (0x00000001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED = (0x00000002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND = (0x00000003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA = (0x00000004) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API = (0x00000010) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API = (0x00000011) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS = (0x00000020) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS = (0x00000021) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA = (0x00000100) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL = (0x00001000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET = (0x00002000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET = (0x00002001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX = (0x00002002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX = (0x00002003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP = (0x00003000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM = (0x00003001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM = (0x00003002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA = (0x00003003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA = (0x00003004) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC = (0x00004000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM = (0x00004001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT = (0x00004010) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT = (0x00005000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE = (0x00005001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE = (0x00005002) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG = (0x00005003) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP = (0x00005004) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN = (0x00005005) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL = (0x00005006) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG = (0x00005007) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP = (0x00005008) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY = (0x00005009) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM = (0x0000500A) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT = (0x0000500B) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT = (0x0000500C) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS = (0x00006000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA = (0x00007000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA = (0x00007001) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR = (0x0000F000) # macro -NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC = (0x0000F00F) # macro -NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES = (0x485) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX = (0x40) # macro -NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID = (0x85) # macro -NV0000_CTRL_CMD_DIAG_PROFILE_RPC = (0x488) # macro -NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID = (0x88) # macro -NV0000_CTRL_PROFILE_RPC_CMD_DISABLE = (0x00000000) # macro -NV0000_CTRL_PROFILE_RPC_CMD_ENABLE = (0x00000001) # macro -NV0000_CTRL_PROFILE_RPC_CMD_RESET = (0x00000002) # macro -NV0000_CTRL_CMD_DIAG_DUMP_RPC = (0x489) # macro -NV0000_CTRL_DIAG_RPC_MAX_ENTRIES = (100) # macro -NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID = (0x89) # macro -class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS(Struct): pass struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS._fields_ = [ - ('state', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('missedCount', ctypes.c_uint32), - ('bCircularBuffer', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('state', NvU32), + ('count', NvU32), + ('missedCount', NvU32), + ('bCircularBuffer', NvBool), ] - NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS -class struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS(Struct): pass struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS._fields_ = [ - ('state', ctypes.c_uint32), - ('bCircularBuffer', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('state', NvU32), + ('bCircularBuffer', NvBool), ] - NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS = struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS -class struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY(Structure): - pass - -struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY._pack_ = 1 # source:False +class struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY(Struct): pass struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY._fields_ = [ - ('counter', ctypes.c_uint64), - ('line', ctypes.c_uint32), - ('filename', ctypes.c_ubyte * 12), - ('tag', ctypes.c_uint16), - ('cpuNum', ctypes.c_ubyte), - ('irql', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 4), - ('threadId', ctypes.c_uint64), - ('data0', ctypes.c_uint32), - ('data1', ctypes.c_uint32), - ('data2', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('counter', NvU64), + ('line', NvU32), + ('filename', (NvU8 * 12)), + ('tag', NvU16), + ('cpuNum', NvU8), + ('irql', NvU8), + ('threadId', NvU64), + ('data0', NvU32), + ('data1', NvU32), + ('data2', NvU32), ] - NV0000_CTRL_DIAG_LOCK_METER_ENTRY = struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY -class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS(Struct): pass struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS._fields_ = [ - ('entryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('entries', struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY * 64), + ('entryCount', NvU32), + ('entries', (NV0000_CTRL_DIAG_LOCK_METER_ENTRY * 64)), ] - NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS -class struct_RPC_METER_ENTRY(Structure): - pass - -struct_RPC_METER_ENTRY._pack_ = 1 # source:False +class struct_RPC_METER_ENTRY(Struct): pass struct_RPC_METER_ENTRY._fields_ = [ - ('startTimeInNs', ctypes.c_uint64), - ('endTimeInNs', ctypes.c_uint64), - ('rpcDataTag', ctypes.c_uint64), - ('rpcExtraData', ctypes.c_uint64), + ('startTimeInNs', NvU64), + ('endTimeInNs', NvU64), + ('rpcDataTag', NvU64), + ('rpcExtraData', NvU64), ] - RPC_METER_ENTRY = struct_RPC_METER_ENTRY -class struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS(Struct): pass struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS._fields_ = [ - ('rpcProfileCmd', ctypes.c_uint32), + ('rpcProfileCmd', NvU32), ] - NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS = struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS -class struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS(Struct): pass struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS._fields_ = [ - ('firstEntryOffset', ctypes.c_uint32), - ('outputEntryCount', ctypes.c_uint32), - ('remainingEntryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('elapsedTimeInNs', ctypes.c_uint64), - ('rpcProfilerBuffer', struct_RPC_METER_ENTRY * 100), + ('firstEntryOffset', NvU32), + ('outputEntryCount', NvU32), + ('remainingEntryCount', NvU32), + ('elapsedTimeInNs', NvU64), + ('rpcProfilerBuffer', (RPC_METER_ENTRY * 100)), ] - NV0000_CTRL_DIAG_DUMP_RPC_PARAMS = struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS -NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x501) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) # macro -NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) # macro -NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS = (0x502) # macro -NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Struct): pass struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [ - ('event', ctypes.c_uint32), - ('action', ctypes.c_uint32), + ('event', NvU32), + ('action', NvU32), ] - NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS -class struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS(Struct): pass struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS._fields_ = [ - ('event', ctypes.c_uint32), - ('status', ctypes.c_uint32), + ('event', NvU32), + ('status', NvU32), ] - NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS = struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS -NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = (0x1f0) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID = (0xF0) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_SLI = 0 : 0 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT = 2 : 2 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING = 3 : 3 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED = 4 : 4 # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = (0x101) # macro -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = (0x102) # macro -NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -# NV0000_CTRL_SYSTEM_CPU_FAMILY = 3 : 0 # macro -# NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY = 11 : 4 # macro -# NV0000_CTRL_SYSTEM_CPU_MODEL = 3 : 0 # macro -# NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL = 7 : 4 # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY = 0xF # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY = 0xA # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL = 0x0 # macro -NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL = 0x4 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY = 0x6 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY = 0x0 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL = 0x7 # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL = 0xA # macro -NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL = 0x9 # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN = (0x00000000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P5 = (0x00000001) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P55 = (0x00000002) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P6 = (0x00000003) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P2 = (0x00000004) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC = (0x00000005) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CELA = (0x00000006) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P3 = (0x00000007) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 = (0x00000008) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_P4 = (0x00000009) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 = (0x00000010) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H = (0x00000011) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM = (0x00000012) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM = (0x00000013) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR = (0x00000014) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K5 = (0x00000030) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K6 = (0x00000031) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K62 = (0x00000032) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K63 = (0x00000033) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K7 = (0x00000034) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K8 = (0x00000035) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K10 = (0x00000036) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_K11 = (0x00000037) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN = (0x00000038) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_C6 = (0x00000060) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_C62 = (0x00000061) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_GX = (0x00000070) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_M1 = (0x00000071) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_M2 = (0x00000072) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_MGX = (0x00000073) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE = (0x00000080) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 = (0x00000090) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 = (0x00000091) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 = (0x00000092) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN = (0x00000093) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN = (0xA0000000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 = (0xA0000009) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 = (0xA000000F) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 = (0xA0001000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 = (0xA0002000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC = (0xA00FF000) # macro -NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC = (0xA00FF001) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_MMX = (0x00000001) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE = (0x00000002) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW = (0x00000004) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 = (0x00000008) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE = (0x00000010) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING = (0x00000020) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC = (0x00000040) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO = (0x00000080) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND = (0x00000100) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT = (0x00000200) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT = (0x00000400) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_CMOV = (0x00000800) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH = (0x00001000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 = (0x00002000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 = (0x00004000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 = (0x00008000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE = (0x00010000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 = (0x00020000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 = (0x00040000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_AVX = (0x00080000) # macro -NV0000_CTRL_SYSTEM_CPU_CAP_ERMS = (0x00100000) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO = (0x104) # macro -NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH = (0x0000020) # macro -NV0000_SYSTEM_CHIPSET_INVALID_ID = (0xffff) # macro -NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -# NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE = 0 : 0 # macro -NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO = (0x00000000) # macro -NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES = (0x00000001) # macro -NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT = (0x107) # macro -NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID = (0x7) # macro -NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES = (0x109) # macro -NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID = (0x9) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST = (0x108) # macro -NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE = (32) # macro -NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x8) # macro -NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT = (0x110) # macro -NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID = (0x10) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID = (0x00000003) # macro -NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK = (0x00000004) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI = (0x00000003) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL = (0x00000004) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT = (0x5) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI = (0x00000003) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL = (0x00000004) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT = (0x5) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE = (0x111) # macro -NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID = (0x11) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP = (0x000000) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC = (0x000001) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA = (0x000002) # macro -NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC = (0x000003) # macro -NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL = (0x121) # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE = 512 # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET = (0x00000000) # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET = (0x00000001) # macro -NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID = (0x21) # macro -NV0000_CTRL_SYSTEM_HWBC_INVALID_ID = (0xFFFFFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO = (0x124) # macro -NV0000_CTRL_SYSTEM_MAX_HWBCS = (0x00000080) # macro -NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID = (0x24) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL = (0x122) # macro -NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID = (0x22) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT = (0x0000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC = (0x0001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC = (0x0002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS = (0x0003) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS = (0x0004) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC = (0x0005) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC = (0x0006) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE = (0x0007) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE = (0x0008) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT = (0x0009) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT = (0x000A) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE = (0x000B) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE = (0x000C) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER = (0x0100) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER = (0x0101) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET = (0x0102) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET = (0x0103) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD = (0x0104) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD = (0x0105) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET = (0x0106) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET = (0x0107) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT = (0x0108) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST = (0x0109) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST = (0x010A) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE = (0x010B) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE = (0x010C) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO = (0x010D) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER = (0x0200) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA = (0x0201) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE = (0x0202) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG = (0x0203) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL = (0x0204) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN = (0x0205) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE = (0x0206) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS = (0x0210) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP = (0x0220) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA = (0x0221) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE = (0x0222) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE = (0x0240) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP = (0x0241) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN = (0x0242) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX = (0x0243) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION = (0x0244) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE = (0x0250) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE = (0x0251) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA = (0x0252) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA = (0x0253) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT = (0x0321) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM = (0x0000) # macro -def NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i): # macro - return (0x0100+((i)%0x100)) -def NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i): # macro - return (0x0200+((i)%0x100)) -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID = (0x80000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC = (0x00000008) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC = (0x00000010) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB = (0x00000020) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL = (0x123) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX = (16) # macro -NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x23) # macro -NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = (0x127) # macro -NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32 # macro -NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED = 1024 # macro -NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS = 8 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER = 0xffffffff # macro -NV0000_CTRL_P2P_CAPS_INDEX_READ = 0 # macro -NV0000_CTRL_P2P_CAPS_INDEX_WRITE = 1 # macro -NV0000_CTRL_P2P_CAPS_INDEX_NVLINK = 2 # macro -NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS = 3 # macro -NV0000_CTRL_P2P_CAPS_INDEX_PROP = 4 # macro -NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK = 5 # macro -NV0000_CTRL_P2P_CAPS_INDEX_PCI = 6 # macro -NV0000_CTRL_P2P_CAPS_INDEX_C2C = 7 # macro -NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 = 8 # macro -NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0x27) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED = 0 : 0 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED = 1 : 1 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED = 2 : 2 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED = 3 : 3 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED = 4 : 4 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED = 5 : 5 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED = 6 : 6 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED = 7 : 7 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED = 8 : 8 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED = 9 : 9 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED = 10 : 10 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED = 12 : 12 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE = (0x00000001) # macro -# NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED = 13 : 13 # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE = (0x00000001) # macro -NV0000_P2P_CAPS_STATUS_OK = (0x00) # macro -NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED = (0x01) # macro -NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED = (0x02) # macro -NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED = (0x03) # macro -NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY = (0x04) # macro -NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED = (0x05) # macro -NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = (0x12b) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID = (0x2B) # macro -NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = (0x13a) # macro -NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID = (0x3A) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CTRL = (0x12a) # macro -NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID = (0x2A) # macro -NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) # macro -NV0000_CTRL_GPS_INPUT_SENSOR_INDEX = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_MIN_LIMIT = (0x00000001) # macro -NV0000_CTRL_GPS_RESULT_MAX_LIMIT = (0x00000002) # macro -NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE = (0x00000003) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) # macro -NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) # macro -NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) # macro -NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) # macro -NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) # macro -NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) # macro -NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL = (0x00000001) # macro -NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI = (0x0000001B) # macro -NV0000_CTRL_GPS_INPUT_ACPI_CMD = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN = (0x00000001) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 = (0x00000000) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 = (0x00000001) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ = (0x00000000) # macro -NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) # macro -NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) # macro -NV0000_CTRL_GPS_INPUT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) # macro -NV0000_CTRL_GPS_RESULT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) # macro -NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) # macro -NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) # macro -NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) # macro -NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) # macro -NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) # macro -NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) # macro -NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) # macro -NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PPM = (0x00000048) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK = 1 # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PPM = (0x00000049) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX = (2) # macro -# NV0000_CTRL_GPS_PPM_INDEX = 7 : 0 # macro -NV0000_CTRL_GPS_PPM_INDEX_MAXPERF = (0) # macro -NV0000_CTRL_GPS_PPM_INDEX_BALANCED = (1) # macro -NV0000_CTRL_GPS_PPM_INDEX_QUIET = (2) # macro -NV0000_CTRL_GPS_PPM_INDEX_INVALID = (0xFF) # macro -# NV0000_CTRL_GPS_PPM_MASK = 15 : 8 # macro -NV0000_CTRL_GPS_PPM_MASK_INVALID = (0) # macro -NV0000_CTRL_GPS_CMD_PS_STATUS_OFF = (0) # macro -NV0000_CTRL_GPS_CMD_PS_STATUS_ON = (1) # macro -NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS = (0x129) # macro -GPS_MAX_COUNTERS_PER_BLOCK = 32 # macro -NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID = (0x29) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS = (0x12c) # macro -NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2C) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS = (0x12e) # macro -NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2E) # macro -GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 # macro -NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID = (0x2D) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI = (0x12d) # macro -NV0000_CTRL_SYSTEM_PARAM_TGPU = (0x00000000) # macro -NV0000_CTRL_SYSTEM_PARAM_PDTS = (0x00000001) # macro -NV0000_CTRL_SYSTEM_PARAM_SFAN = (0x00000002) # macro -NV0000_CTRL_SYSTEM_PARAM_SKNT = (0x00000003) # macro -NV0000_CTRL_SYSTEM_PARAM_CPUE = (0x00000004) # macro -NV0000_CTRL_SYSTEM_PARAM_TMP1 = (0x00000005) # macro -NV0000_CTRL_SYSTEM_PARAM_TMP2 = (0x00000006) # macro -NV0000_CTRL_SYSTEM_PARAM_CTGP = (0x00000007) # macro -NV0000_CTRL_SYSTEM_PARAM_PPMD = (0x00000008) # macro -NV0000_CTRL_SYSTEM_PARAM_COUNT = (0x00000009) # macro -NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD = (0x130) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID = (0x30) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS = (0x00000000) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG = (0x00000001) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS = (0x00000002) # macro -NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY = (0x00000003) # macro -NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS = (0x131) # macro -NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID = (0x31) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL = (0x00000001) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ = (0x00000002) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH = (0x00000004) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF = (0x00000010) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG = (0x00000020) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS = (0x00000040) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER = (0x00000080) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP = (0x00000100) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI = (0x00000200) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR = (0x00000400) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK = (0x00000800) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL = (0x00001000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC = (0x00002000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM = (0x00004000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS = (0x00008000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE = (0x00010000) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY = (0x00020000) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA = (0x12f) # macro -NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE = 64 # macro -NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x2F) # macro -NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA = (0x132) # macro -NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x32) # macro -NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE = 256 # macro -NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO = (0x133) # macro -NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID = (0x33) # macro -NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS = (0x134) # macro -NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID = (0x34) # macro -NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED = 0 # macro -NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED = 1 # macro -NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS = (0x135) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID = (0x35) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG = (0x00000001) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG = (0x00000002) # macro -NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = (0x136) # macro -NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID = (0x36) # macro -NV0000_CTRL_VGPU_GET_VGPU_VERSION = (0x137) # macro -NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x37) # macro -NV0000_CTRL_VGPU_SET_VGPU_VERSION = (0x138) # macro -NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x38) # macro -NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID = (0x139) # macro -NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID = (0x39) # macro -NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO = (0x13b) # macro -NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE = 1 # macro -NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE = 32 # macro -NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID = (0x48) # macro -NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID = (0x3B) # macro -CONTROLLER_FILTER_TYPE_EMWA = 0 # macro -CONTROLLER_FILTER_TYPE_MOVING_MAX = 1 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE = 2 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE = 3 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE = 4 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE = 5 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE = 6 # macro -NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED = (0x00000000) # macro -NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) # macro -# NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED = 0 : 0 # macro -NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES = 1 # macro -NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO = 0 # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION = (0x00000200) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED = (0x00000000) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES = (0x00000001) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE = (0x00000008) # macro -NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL = (0x00000009) # macro -NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX = (255) # macro -NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT = (0x13c) # macro -NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID = (0x3C) # macro -NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO = (0x13d) # macro -NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID = (0x3D) # macro -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256 # macro -NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 = (0x13e) # macro -NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID = (0x3E) # macro -NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL = (0x13f) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID = (0x3F) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET = (0x00000000) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET = (0x00000001) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE = (0x00000000) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE = (0x00000001) # macro -NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL = (0x140) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID = (0x40) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT = (0x0000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC = (0x0001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC = (0x0002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS = (0x0003) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS = (0x0004) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC = (0x0005) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC = (0x0006) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE = (0x0007) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE = (0x0008) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT = (0x0009) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT = (0x000A) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE = (0x000B) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE = (0x000C) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER = (0x0100) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER = (0x0101) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET = (0x0102) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET = (0x0103) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD = (0x0104) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD = (0x0105) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET = (0x0106) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET = (0x0107) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT = (0x0108) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST = (0x0109) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST = (0x010A) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE = (0x010B) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE = (0x010C) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO = (0x010D) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER = (0x0200) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA = (0x0201) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE = (0x0202) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG = (0x0203) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL = (0x0204) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN = (0x0205) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE = (0x0206) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS = (0x0210) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP = (0x0220) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA = (0x0221) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE = (0x0222) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE = (0x0240) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP = (0x0241) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN = (0x0242) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX = (0x0243) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION = (0x0244) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE = (0x0250) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE = (0x0251) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA = (0x0252) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA = (0x0253) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT = (0x0321) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID = (0xFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM = (0x0000) # macro -def NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i): # macro - return (0x0100+((i)%0x100)) -def NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i): # macro - return (0x0200+((i)%0x100)) -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID = (0x80000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC = (0x00000008) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC = (0x00000010) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB = (0x00000020) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL = (0x141) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX = (16) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x41) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL = (0x142) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID = (0x42) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT = (0x00000002) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE = (0x00000003) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI = (0x0000001B) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) # macro -NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) # macro -NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM = (0x00000048) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK = 1 # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM = (0x00000049) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX = (0000000000) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX = (2) # macro -# NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX = 7 : 0 # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF = (0) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED = (1) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET = (2) # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID = (0xFF) # macro -# NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK = 15 : 8 # macro -NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID = (0) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF = (0) # macro -NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON = (1) # macro -PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK = 32 # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS = (0x146) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x46) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS = (0x147) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x47) # macro -PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID = (0x43) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI = (0x143) # macro -NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR = (0x00008000) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA = (0x144) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE = 64 # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x44) # macro -NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA = (0x145) # macro -NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x45) # macro -NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = (0x201) # macro -NV0000_CTRL_GPU_MAX_ATTACHED_GPUS = 32 # macro -NV0000_CTRL_GPU_INVALID_ID = (0xffffffff) # macro -NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_GPU_GET_ID_INFO = (0x202) # macro -NV0000_CTRL_GPU_MAX_SZNAME = 128 # macro -NV0000_CTRL_NO_NUMA_NODE = (-1) # macro -NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_SLI_STATUS_OK = (0x00000000) # macro -NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED = (0x00000002) # macro -NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED = (0x00000040) # macro -NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = (0x205) # macro -NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0000_CTRL_GPU_ID_INFO_IN_USE = 0 : 0 # macro -NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE = 1 : 1 # macro -NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_MOBILE = 2 : 2 # macro -NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER = 3 : 3 # macro -NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_SOC = 5 : 5 # macro -NV0000_CTRL_GPU_ID_INFO_SOC_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_SOC_TRUE = (0x00000001) # macro -# NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED = 6 : 6 # macro -NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE = (0x00000000) # macro -NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_GET_INIT_STATUS = (0x203) # macro -NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = (0x204) # macro -NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = (0x214) # macro -# NV0000_CTRL_GPU_MAX_PROBED_GPUS = NV_MAX_DEVICES # macro -NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID = (0x14) # macro -NV0000_CTRL_CMD_GPU_GET_PCI_INFO = (0x21b) # macro -NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1B) # macro -NV0000_CTRL_CMD_GPU_ATTACH_IDS = (0x215) # macro -NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS = (0x0000ffff) # macro -NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID = (0x15) # macro -NV0000_CTRL_CMD_GPU_DETACH_IDS = (0x216) # macro -NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS = (0x0000ffff) # macro -NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID = (0x16) # macro -NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS = (0x219) # macro -NV0000_CTRL_GPU_MAX_VIDEO_LINKS = 8 # macro -NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID = (0x19) # macro -NV0000_CTRL_CMD_GPU_GET_SVM_SIZE = (0x240) # macro -NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID = (0x40) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO = (0x274) # macro -NV0000_GPU_MAX_GID_LENGTH = (0x00000100) # macro -NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID = (0x74) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT = 1 : 0 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY = (0x00000002) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE = 2 : 2 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = (0x275) # macro -NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID = (0x75) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT = 1 : 0 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY = (0x00000002) # macro -# NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE = 2 : 2 # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 = (0x00000000) # macro -NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE = (0x278) # macro -NV0000_CTRL_GPU_DRAIN_STATE_DISABLED = (0x00000000) # macro -NV0000_CTRL_GPU_DRAIN_STATE_ENABLED = (0x00000001) # macro -NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE = (0x00000001) # macro -NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE = (0x00000002) # macro -NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x78) # macro -NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = (0x279) # macro -NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x79) # macro -NV0000_CTRL_CMD_GPU_DISCOVER = (0x27a) # macro -NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = (0x27b) # macro -NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID = (0x7B) # macro -NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE = (0x00000001) # macro -NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT = (0x281) # macro -NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID = (0x81) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA = 0x00000175 # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN = 6 # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT = 5 # macro -NV0000_CTRL_CMD_GPU_LEGACY_CONFIG = (0x282) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID = (0x82) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET = (0x00000001) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX = (0x00000002) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX = (0x00000003) # macro -NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED = (0x00000004) # macro -NV0000_CTRL_CMD_IDLE_CHANNELS = (0x283) # macro -NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x83) # macro -NV0000_CTRL_GPU_IMAGE_TYPE_GSP = (0x00000001) # macro -NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG = (0x00000002) # macro -NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE = (0x00000003) # macro -NV0000_CTRL_CMD_PUSH_UCODE_IMAGE = (0x285) # macro -NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID = (0x85) # macro -# NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LEGACY = 2 : 0 # macro -# NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SETTING_LINK_COUNT = 7 : 3 # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL = (0x00) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF = (0x01) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN = (0x02) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF = (0x03) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER = (0x04) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT = (0x05) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET = (0x00) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE = (0x01) # macro -NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU = (0x02) # macro -NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE = (0x286) # macro -NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x86) # macro -NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE = (0x287) # macro -NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x87) # macro -NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = (0x288) # macro -NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES = 256 # macro -NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x88) # macro -NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = (0x289) # macro -NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID = (0x89) # macro -NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = (0x290) # macro -NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID = (0x90) # macro -class struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS._fields_ = [ + ('gpuIds', (NvU32 * 32)), +] +NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS +class struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('gpuFlags', NvU32), + ('deviceInstance', NvU32), + ('subDeviceInstance', NvU32), + ('szName', NvP64), + ('sliStatus', NvU32), + ('boardId', NvU32), + ('gpuInstance', NvU32), + ('numaId', NvS32), +] +NV0000_CTRL_GPU_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS +class struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('gpuFlags', NvU32), + ('deviceInstance', NvU32), + ('subDeviceInstance', NvU32), + ('sliStatus', NvU32), + ('boardId', NvU32), + ('gpuInstance', NvU32), + ('numaId', NvS32), +] +NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS +class struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('status', NvU32), +] +NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS = struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS +class struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS._fields_ = [ + ('deviceIds', NvU32), +] +NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS +class struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS._fields_ = [ + ('gpuIds', (NvU32 * 32)), + ('excludedGpuIds', (NvU32 * 32)), +] +NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS +class struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('domain', NvU32), + ('bus', NvU16), + ('slot', NvU16), +] +NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS +class struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS._fields_ = [ + ('gpuIds', (NvU32 * 32)), + ('failedId', NvU32), +] +NV0000_CTRL_GPU_ATTACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS +class struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS._fields_ = [ + ('gpuIds', (NvU32 * 32)), +] +NV0000_CTRL_GPU_DETACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS +class struct_NV0000_CTRL_GPU_VIDEO_LINKS(Struct): pass +struct_NV0000_CTRL_GPU_VIDEO_LINKS._fields_ = [ + ('gpuId', NvU32), + ('connectedGpuIds', (NvU32 * 8)), +] +NV0000_CTRL_GPU_VIDEO_LINKS = struct_NV0000_CTRL_GPU_VIDEO_LINKS +class struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS._fields_ = [ + ('links', (NV0000_CTRL_GPU_VIDEO_LINKS * 32)), +] +NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS = struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS +class struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('svmSize', NvU32), +] +NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS = struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS +class struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS._fields_ = [ + ('gpuUuid', (NvU8 * 256)), + ('flags', NvU32), + ('gpuId', NvU32), + ('deviceInstance', NvU32), + ('subdeviceInstance', NvU32), +] +NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS +class struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('flags', NvU32), + ('gpuUuid', (NvU8 * 256)), + ('uuidStrLen', NvU32), +] +NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS +class struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('newState', NvU32), + ('flags', NvU32), +] +NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS +class struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('drainState', NvU32), + ('flags', NvU32), +] +NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS +class struct_NV0000_CTRL_GPU_DISCOVER_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_DISCOVER_PARAMS._fields_ = [ + ('domain', NvU32), + ('bus', NvU8), + ('slot', NvU8), + ('function', NvU8), +] +NV0000_CTRL_GPU_DISCOVER_PARAMS = struct_NV0000_CTRL_GPU_DISCOVER_PARAMS +class struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS._fields_ = [ + ('enableMask', NvU32), +] +NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS = struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS +class struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('mask', NvU32), + ('bSkipHwNvlinkDisable', NvBool), +] +NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS = struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS +class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS(Struct): pass +class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data(ctypes.Union): pass +class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet(Struct): pass +struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet._fields_ = [ + ('newValue', NvU32), + ('oldValue', NvU32), +] +class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx(Struct): pass +struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx._fields_ = [ + ('paramData', (NvU8 * 373)), + ('paramSize', NvU32), +] +class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty(Struct): pass +struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty._fields_ = [ + ('propertyId', NvU32), + ('propertyIn', (NvU32 * 6)), + ('propertyOut', (NvU32 * 5)), +] +struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data._fields_ = [ + ('configSet', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet), + ('configEx', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx), + ('reservedProperty', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty), +] +struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS._fields_ = [ + ('hContext', NvHandle), + ('opType', NvU32), + ('index', NvV32), + ('dataType', NvU32), + ('data', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data), +] +NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS = struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS +class struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS._fields_ = [ + ('hDevice', NvHandle), + ('hChannel', NvHandle), + ('numChannels', NvV32), + ('phClients', NvP64), + ('phDevices', NvP64), + ('phChannels', NvP64), + ('flags', NvV32), + ('timeout', NvV32), +] +NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS = struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS +class struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS._fields_ = [ + ('image', NvU8), + ('totalSize', NvU64), + ('pData', NvP64), +] +NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS = struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS +class struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS._fields_ = [ + ('mode', NvU8), +] +NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS +class struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS._fields_ = [ + ('mode', NvU8), + ('bwModeScope', NvU8), +] +NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS +class struct_NV0000_CTRL_GPU_ACTIVE_DEVICE(Struct): pass +struct_NV0000_CTRL_GPU_ACTIVE_DEVICE._fields_ = [ + ('gpuId', NvU32), + ('gpuInstanceId', NvU32), + ('computeInstanceId', NvU32), +] +NV0000_CTRL_GPU_ACTIVE_DEVICE = struct_NV0000_CTRL_GPU_ACTIVE_DEVICE +class struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS._fields_ = [ + ('numDevices', NvU32), + ('devices', (NV0000_CTRL_GPU_ACTIVE_DEVICE * 256)), +] +NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS +class struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS._fields_ = [ + ('gpuId', NvU32), +] +NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS +class struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS._fields_ = [ + ('gpuId', NvU32), +] +NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS +class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('pid', NvU32), + ('newState', NvU32), +] +NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS +class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('pid', NvU32), + ('state', NvU32), +] +NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS +class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('pid', NvU32), + ('subPid', NvU32), + ('gpuUtil', NvU32), + ('fbUtil', NvU32), + ('maxFbUsage', NvU64), + ('startTime', NvU64), + ('endTime', NvU64), +] +NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS +class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('pid', NvU32), + ('pidTbl', (NvU32 * 4000)), + ('pidCount', NvU32), +] +NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS +class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS(Struct): pass +struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS._fields_ = [ + ('gpuId', NvU32), + ('pid', NvU32), +] +NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS +class struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS(Struct): pass +struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS._fields_ = [ + ('gsyncIds', (NvU32 * 4)), +] +NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS +class struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS._fields_ = [ + ('gsyncId', NvU32), + ('gsyncFlags', NvU32), + ('gsyncInstance', NvU32), +] +NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS +class struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [ + ('component', NvU32), + ('size', NvU32), +] +NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS +class struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [ + ('pBuffer', NvP64), + ('component', NvU32), + ('size', NvU32), +] +NV0000_CTRL_NVD_GET_DUMP_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS +class struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS._fields_ = [ + ('timestamp', NvU64), + ('cpuClkId', NvU8), +] +NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS = struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS +class struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS._fields_ = [ + ('component', NvU32), + ('version', NvU32), + ('runtimeSizes', (NvU8 * 16)), + ('printFlags', NvU32), + ('signature', (NvU32 * 4)), + ('bufferTags', (NvU32 * 3840)), +] +NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS +class struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS._fields_ = [ + ('component', NvU32), + ('buffer', NvU32), + ('tag', NvU32), + ('size', NvU32), + ('flags', NvU32), + ('pos', NvU32), + ('overflow', NvU32), +] +NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS +class struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS._fields_ = [ + ('component', NvU32), + ('buffer', NvU32), + ('blockNum', NvU32), + ('size', NvU32), + ('data', (NvU8 * 4000)), +] +NV0000_CTRL_NVD_GET_NVLOG_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS +class struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY(Struct): pass +struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY._fields_ = [ + ('tag', NvU32), + ('value', NvU32), + ('attribute', NvU32), +] +NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY = struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY +class struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS(Struct): pass +struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS._fields_ = [ + ('reqIdx', NvU16), + ('rptIdx', NvU16), + ('GPUTag', NvU32), + ('rptTime', NvU32), + ('startIdx', NvU16), + ('endIdx', NvU16), + ('rptType', NvU16), + ('flags', NvU32), + ('rptCount', NvU16), + ('owner', NvU32), + ('processId', NvU32), + ('report', (NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY * 200)), +] +NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS = struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS +class struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS(Struct): pass +struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS._fields_ = [ + ('tsBufferSize', NvU32), + ('pTSBuffer', NvP64), +] +NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS = struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS +class struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS(Struct): pass +struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS._fields_ = [ + ('subProcessID', NvU32), + ('subProcessName', (ctypes.c_char * 100)), +] +NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS = struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS +class struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS(Struct): pass +struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS._fields_ = [ + ('bIsSubProcessDisabled', NvBool), +] +NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS = struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS +class struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS(Struct): pass +struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS._fields_ = [ + ('bEnabled', NvBool), +] +NV0000_SYNC_GPU_BOOST_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS +class struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG(Struct): pass +struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG._fields_ = [ + ('gpuCount', NvU32), + ('gpuIds', (NvU32 * 32)), + ('boostGroupId', NvU32), + ('bBridgeless', NvBool), +] +NV0000_SYNC_GPU_BOOST_GROUP_CONFIG = struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG +class struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS(Struct): pass +struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS._fields_ = [ + ('boostConfig', NV0000_SYNC_GPU_BOOST_GROUP_CONFIG), +] +NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS +class struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS(Struct): pass +struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS._fields_ = [ + ('boostGroupId', NvU32), +] +NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS +class struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS(Struct): pass +struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS._fields_ = [ + ('groupCount', NvU32), + ('pBoostGroups', (NV0000_SYNC_GPU_BOOST_GROUP_CONFIG * 16)), +] +NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS +class struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS._fields_ = [ - ('featuresMask', ctypes.c_uint32), + ('featuresMask', NvU32), ] - NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS._fields_ = [ - ('sizeOfStrings', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pDriverVersionBuffer', ctypes.POINTER(None)), - ('pVersionBuffer', ctypes.POINTER(None)), - ('pTitleBuffer', ctypes.POINTER(None)), - ('changelistNumber', ctypes.c_uint32), - ('officialChangelistNumber', ctypes.c_uint32), + ('sizeOfStrings', NvU32), + ('pDriverVersionBuffer', NvP64), + ('pVersionBuffer', NvP64), + ('pTitleBuffer', NvP64), + ('changelistNumber', NvU32), + ('officialChangelistNumber', NvU32), ] - NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS +enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE = CEnum(ctypes.c_uint32) +NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE.define('NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', 0) +NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE.define('NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', 1) -# values for enumeration 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE' -NV0000_CTRL_SYSTEM_SH_SOC_TYPE__enumvalues = { - 0: 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', - 1: 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', -} -NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = 0 -NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = 1 -NV0000_CTRL_SYSTEM_SH_SOC_TYPE = ctypes.c_uint32 # enum -class struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS._pack_ = 1 # source:False +NV0000_CTRL_SYSTEM_SH_SOC_TYPE = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE +class struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS._fields_ = [ - ('type', ctypes.c_uint32), - ('capabilities', ctypes.c_uint32), - ('clock', ctypes.c_uint32), - ('L1DataCacheSize', ctypes.c_uint32), - ('L2DataCacheSize', ctypes.c_uint32), - ('dataCacheLineSize', ctypes.c_uint32), - ('numLogicalCpus', ctypes.c_uint32), - ('numPhysicalCpus', ctypes.c_uint32), - ('name', ctypes.c_ubyte * 52), - ('family', ctypes.c_uint32), - ('model', ctypes.c_uint32), - ('stepping', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('coresOnDie', ctypes.c_uint32), - ('bCCEnabled', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('selfHostedSocType', NV0000_CTRL_SYSTEM_SH_SOC_TYPE), + ('type', NvU32), + ('capabilities', NvU32), + ('clock', NvU32), + ('L1DataCacheSize', NvU32), + ('L2DataCacheSize', NvU32), + ('dataCacheLineSize', NvU32), + ('numLogicalCpus', NvU32), + ('numPhysicalCpus', NvU32), + ('name', (NvU8 * 52)), + ('family', NvU32), + ('model', NvU32), + ('stepping', NvU8), + ('coresOnDie', NvU32), + ('bCCEnabled', NvBool), + ('selfHostedSocType', NV0000_CTRL_SYSTEM_SH_SOC_TYPE), ] - NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS._fields_ = [ - ('vendorId', ctypes.c_uint16), - ('deviceId', ctypes.c_uint16), - ('subSysVendorId', ctypes.c_uint16), - ('subSysDeviceId', ctypes.c_uint16), - ('HBvendorId', ctypes.c_uint16), - ('HBdeviceId', ctypes.c_uint16), - ('HBsubSysVendorId', ctypes.c_uint16), - ('HBsubSysDeviceId', ctypes.c_uint16), - ('sliBondId', ctypes.c_uint32), - ('vendorNameString', ctypes.c_ubyte * 32), - ('subSysVendorNameString', ctypes.c_ubyte * 32), - ('chipsetNameString', ctypes.c_ubyte * 32), - ('sliBondNameString', ctypes.c_ubyte * 32), - ('flags', ctypes.c_uint32), + ('vendorId', NvU16), + ('deviceId', NvU16), + ('subSysVendorId', NvU16), + ('subSysDeviceId', NvU16), + ('HBvendorId', NvU16), + ('HBdeviceId', NvU16), + ('HBsubSysVendorId', NvU16), + ('HBsubSysDeviceId', NvU16), + ('sliBondId', NvU32), + ('vendorNameString', (NvU8 * 32)), + ('subSysVendorNameString', (NvU8 * 32)), + ('chipsetNameString', (NvU8 * 32)), + ('sliBondNameString', (NvU8 * 32)), + ('flags', NvU32), ] - NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS._fields_ = [ - ('bIsPresent', ctypes.c_ubyte), + ('bIsPresent', NvBool), ] - NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS._fields_ = [ - ('waitApiLock', ctypes.c_uint64), - ('holdRoApiLock', ctypes.c_uint64), - ('holdRwApiLock', ctypes.c_uint64), - ('waitGpuLock', ctypes.c_uint64), - ('holdGpuLock', ctypes.c_uint64), + ('waitApiLock', NvU64), + ('holdRoApiLock', NvU64), + ('holdRwApiLock', NvU64), + ('waitGpuLock', NvU64), + ('holdGpuLock', NvU64), ] - NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS._fields_ = [ - ('numClasses', ctypes.c_uint32), - ('classes', ctypes.c_uint32 * 32), + ('numClasses', NvU32), + ('classes', (NvU32 * 32)), ] - NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS -class struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS._fields_ = [ - ('eventType', ctypes.c_uint32), - ('eventData', ctypes.c_uint32), - ('bEventDataForced', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('eventType', NvU32), + ('eventData', NvU32), + ('bEventDataForced', NvBool), ] - NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS = struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS -class struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS(Struct): pass struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS._fields_ = [ - ('systemType', ctypes.c_uint32), + ('systemType', NvU32), ] - NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS -class struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 512), + ('cmd', NvU32), + ('count', NvU32), + ('data', (NvU8 * 512)), ] - NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_HWBC_INFO(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_HWBC_INFO._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_HWBC_INFO(Struct): pass struct_NV0000_CTRL_SYSTEM_HWBC_INFO._fields_ = [ - ('hwbcId', ctypes.c_uint32), - ('firmwareVersion', ctypes.c_uint32), - ('subordinateBus', ctypes.c_uint32), - ('secondaryBus', ctypes.c_uint32), + ('hwbcId', NvU32), + ('firmwareVersion', NvU32), + ('subordinateBus', NvU32), + ('secondaryBus', NvU32), ] - NV0000_CTRL_SYSTEM_HWBC_INFO = struct_NV0000_CTRL_SYSTEM_HWBC_INFO -class struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('hwbcInfo', struct_NV0000_CTRL_SYSTEM_HWBC_INFO * 128), - ] - +class struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS(Struct): pass +struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS._fields_ = [ + ('hwbcInfo', (NV0000_CTRL_SYSTEM_HWBC_INFO * 128)), +] NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), + ('command', NvU16), + ('locale', NvU16), + ('data', NvU32), ] - NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS(Structure): - pass - -class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), +class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS(Struct): pass +class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData(Struct): pass +struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData._fields_ = [ + ('command', NvU16), + ('locale', NvU16), + ('data', NvU32), ] - -struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS._pack_ = 1 # source:False struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS._fields_ = [ - ('cmdCount', ctypes.c_uint32), - ('succeeded', ctypes.c_uint32), - ('cmdData', struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0 * 16), + ('cmdCount', NvU32), + ('succeeded', NvU32), + ('cmdData', (struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData * 16)), ] - NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('gpuCount', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 7), - ('busPeerIds', ctypes.POINTER(None)), - ('busEgmPeerIds', ctypes.POINTER(None)), + ('gpuIds', (NvU32 * 32)), + ('gpuCount', NvU32), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), + ('busPeerIds', NvP64), + ('busEgmPeerIds', NvP64), ] - NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('gpuCount', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerIds', ctypes.c_uint32 * 1024), - ('busEgmPeerIds', ctypes.c_uint32 * 1024), + ('gpuIds', (NvU32 * 32)), + ('gpuCount', NvU32), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), + ('busPeerIds', (NvU32 * 1024)), + ('busEgmPeerIds', (NvU32 * 1024)), ] - NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS -NV0000_CTRL_P2P_CAPS_MATRIX_ROW = ctypes.c_uint32 * 8 -class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS._pack_ = 1 # source:False +NV0000_CTRL_P2P_CAPS_MATRIX_ROW = (ctypes.c_uint32 * 8) +class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS._fields_ = [ - ('grpACount', ctypes.c_uint32), - ('grpBCount', ctypes.c_uint32), - ('gpuIdGrpA', ctypes.c_uint32 * 8), - ('gpuIdGrpB', ctypes.c_uint32 * 8), - ('p2pCaps', ctypes.c_uint32 * 8 * 8), - ('a2bOptimalReadCes', ctypes.c_uint32 * 8 * 8), - ('a2bOptimalWriteCes', ctypes.c_uint32 * 8 * 8), - ('b2aOptimalReadCes', ctypes.c_uint32 * 8 * 8), - ('b2aOptimalWriteCes', ctypes.c_uint32 * 8 * 8), + ('grpACount', NvU32), + ('grpBCount', NvU32), + ('gpuIdGrpA', (NvU32 * 8)), + ('gpuIdGrpB', (NvU32 * 8)), + ('p2pCaps', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)), + ('a2bOptimalReadCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)), + ('a2bOptimalWriteCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)), + ('b2aOptimalReadCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)), + ('b2aOptimalWriteCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)), ] - NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_int32 * 2), - ('result', ctypes.c_int32 * 4), + ('cmd', NvU32), + ('input', (NvS32 * 2)), + ('result', (NvS32 * 4)), ] - NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS._fields_ = [ - ('objHndl', ctypes.c_uint32), - ('blockId', ctypes.c_uint32), - ('nextExpectedSampleTimems', ctypes.c_uint32), - ('countersReq', ctypes.c_uint32), - ('countersReturned', ctypes.c_uint32), - ('counterBlock', ctypes.c_uint32 * 32), + ('objHndl', NvU32), + ('blockId', NvU32), + ('nextExpectedSampleTimems', NvU32), + ('countersReq', NvU32), + ('countersReturned', NvU32), + ('counterBlock', (NvU32 * 32)), ] - NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_uint32), - ('resultSz', ctypes.c_uint32), - ('result', ctypes.c_uint32 * 288), + ('cmd', NvU32), + ('input', NvU32), + ('resultSz', NvU32), + ('result', (NvU32 * 288)), ] - NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS -class struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS._fields_ = [ - ('method', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('inData', ctypes.POINTER(None)), - ('inDataSize', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('outStatus', ctypes.c_uint32), - ('outData', ctypes.POINTER(None)), - ('outDataSize', ctypes.c_uint16), - ('PADDING_2', ctypes.c_ubyte * 6), + ('method', NvU32), + ('inData', NvP64), + ('inDataSize', NvU16), + ('outStatus', NvU32), + ('outData', NvP64), + ('outDataSize', NvU16), ] - NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS = struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS -class struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS._fields_ = [ - ('moduleMask', ctypes.c_uint32), + ('moduleMask', NvU32), ] - NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS = struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE(Struct): pass struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE._fields_ = [ - ('frameTime', ctypes.c_uint16), - ('renderTime', ctypes.c_uint16), - ('targetTime', ctypes.c_uint16), - ('sleepTime', ctypes.c_ubyte), - ('sampleNumber', ctypes.c_ubyte), + ('frameTime', NvU16), + ('renderTime', NvU16), + ('targetTime', NvU16), + ('sleepTime', NvU8), + ('sampleNumber', NvU8), ] - NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE = struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE -class struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS._fields_ = [ - ('samples', struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE * 64), - ('nextSampleNumber', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), + ('samples', (NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE * 64)), + ('nextSampleNumber', NvU8), ] - NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('sampleData', NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE), - ] - +class struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS(Struct): pass +struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS._fields_ = [ + ('sampleData', NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE), +] NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS._fields_ = [ - ('szHostDriverVersionBuffer', ctypes.c_char * 256), - ('szHostVersionBuffer', ctypes.c_char * 256), - ('szHostTitleBuffer', ctypes.c_char * 256), - ('szPluginTitleBuffer', ctypes.c_char * 256), - ('szHostUnameBuffer', ctypes.c_char * 256), - ('iHostChangelistNumber', ctypes.c_uint32), - ('iPluginChangelistNumber', ctypes.c_uint32), + ('szHostDriverVersionBuffer', (ctypes.c_char * 256)), + ('szHostVersionBuffer', (ctypes.c_char * 256)), + ('szHostTitleBuffer', (ctypes.c_char * 256)), + ('szPluginTitleBuffer', (ctypes.c_char * 256)), + ('szHostUnameBuffer', (ctypes.c_char * 256)), + ('iHostChangelistNumber', NvU32), + ('iPluginChangelistNumber', NvU32), ] - NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS._fields_ = [ - ('gpuCount', ctypes.c_ubyte), - ('gpuBus', ctypes.c_ubyte * 32), - ('gpuExternalPowerStatus', ctypes.c_ubyte * 32), + ('gpuCount', NvU8), + ('gpuBus', (NvU8 * 32)), + ('gpuExternalPowerStatus', (NvU8 * 32)), ] - NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS._fields_ = [ - ('privStatusFlags', ctypes.c_ubyte), + ('privStatusFlags', NvU8), ] - NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS +enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS = CEnum(ctypes.c_uint32) +NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', 1) +NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', 2) +NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', 3) +NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', 4) -# values for enumeration 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS' -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS__enumvalues = { - 1: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', - 2: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', - 3: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', - 4: 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', -} -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4 -NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS = ctypes.c_uint32 # enum -class struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fabricStatus', NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS), - ] - +NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS +class struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS(Struct): pass +struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS._fields_ = [ + ('fabricStatus', NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS), +] NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS -class struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS(Struct): pass struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS._fields_ = [ - ('host_min_supported_version', ctypes.c_uint32), - ('host_max_supported_version', ctypes.c_uint32), - ('user_min_supported_version', ctypes.c_uint32), - ('user_max_supported_version', ctypes.c_uint32), + ('host_min_supported_version', NvU32), + ('host_max_supported_version', NvU32), + ('user_min_supported_version', NvU32), + ('user_max_supported_version', NvU32), ] - NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS = struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS -class struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS(Struct): pass struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS._fields_ = [ - ('min_version', ctypes.c_uint32), - ('max_version', ctypes.c_uint32), + ('min_version', NvU32), + ('max_version', NvU32), ] - NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS = struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS._fields_ = [ - ('rm_instance_id', ctypes.c_uint64), + ('rm_instance_id', NvU64), ] - NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS -class struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT(Structure): - pass - -struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT._pack_ = 1 # source:False +class struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT(Struct): pass struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT._fields_ = [ - ('batteryStateOfChargePercent', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('batteryCurrentLimitmA', ctypes.c_uint32), - ('restOfSytemReservedPowermW', ctypes.c_uint32), - ('minCpuTdpmW', ctypes.c_uint32), - ('maxCpuTdpmW', ctypes.c_uint32), - ('shortTimescaleBatteryCurrentLimitmA', ctypes.c_uint32), + ('batteryStateOfChargePercent', NvU8), + ('batteryCurrentLimitmA', NvU32), + ('restOfSytemReservedPowermW', NvU32), + ('minCpuTdpmW', NvU32), + ('maxCpuTdpmW', NvU32), + ('shortTimescaleBatteryCurrentLimitmA', NvU32), ] - NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT = struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT -class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS(Structure): - pass - -class union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam(Union): - pass - -union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam._pack_ = 1 # source:False -union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam._fields_ = [ - ('weight', ctypes.c_ubyte), - ('windowSize', ctypes.c_ubyte), +class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS(Struct): pass +class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam(ctypes.Union): pass +struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam._fields_ = [ + ('weight', NvU8), + ('windowSize', NvU8), ] - -struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS._pack_ = 1 # source:False struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('tpp', ctypes.c_uint32), - ('ratedTgp', ctypes.c_uint32), - ('subFunc', ctypes.c_uint32), - ('ctgpOffsetmW', ctypes.c_int32), - ('targetTppOffsetmW', ctypes.c_int32), - ('maxOutputOffsetmW', ctypes.c_int32), - ('minOutputOffsetmW', ctypes.c_int32), - ('ctgpBattOffsetmW', ctypes.c_int32), - ('targetTppBattOffsetmW', ctypes.c_int32), - ('dcRosReserveOverridemW', ctypes.c_uint32), - ('dcTspLongTimescaleLimitmA', ctypes.c_uint32), - ('dcTspShortTimescaleLimitmA', ctypes.c_uint32), - ('bRequireDcSysPowerLimitsTable', ctypes.c_ubyte), - ('bAllowDcRestOfSystemReserveOverride', ctypes.c_ubyte), - ('bSupportDcTsp', ctypes.c_ubyte), - ('bEnableForAC', ctypes.c_ubyte), - ('bEnableForDC', ctypes.c_ubyte), - ('version', ctypes.c_ubyte), - ('samplingPeriodmS', ctypes.c_uint16), - ('samplingMulti', ctypes.c_uint16), - ('filterType', ctypes.c_ubyte), - ('filterParam', union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam), - ('filterReserved', ctypes.c_uint16), - ('bIsBoostController', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('incRatio', ctypes.c_uint16), - ('decRatio', ctypes.c_uint16), - ('bSupportBatt', ctypes.c_ubyte), - ('cpuType', ctypes.c_ubyte), - ('gpuType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('sysPwrIndex', ctypes.c_uint32), - ('sysPwrGetInfo', struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT * 32), - ('bIsTspSupported', ctypes.c_ubyte), - ('sysPwrLimitsTableVersion', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 2), - ('type', ctypes.c_uint32), - ('cpuTdpmw', ctypes.c_uint32), + ('gpuId', NvU32), + ('tpp', NvU32), + ('ratedTgp', NvU32), + ('subFunc', NvU32), + ('ctgpOffsetmW', NvS32), + ('targetTppOffsetmW', NvS32), + ('maxOutputOffsetmW', NvS32), + ('minOutputOffsetmW', NvS32), + ('ctgpBattOffsetmW', NvS32), + ('targetTppBattOffsetmW', NvS32), + ('dcRosReserveOverridemW', NvU32), + ('dcTspLongTimescaleLimitmA', NvU32), + ('dcTspShortTimescaleLimitmA', NvU32), + ('bRequireDcSysPowerLimitsTable', NvBool), + ('bAllowDcRestOfSystemReserveOverride', NvBool), + ('bSupportDcTsp', NvBool), + ('bEnableForAC', NvBool), + ('bEnableForDC', NvBool), + ('version', NvU8), + ('samplingPeriodmS', NvU16), + ('samplingMulti', NvU16), + ('filterType', NvU8), + ('filterParam', struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam), + ('filterReserved', NvU16), + ('bIsBoostController', NvBool), + ('incRatio', NvU16), + ('decRatio', NvU16), + ('bSupportBatt', NvBool), + ('cpuType', NvU8), + ('gpuType', NvU8), + ('sysPwrIndex', NvU32), + ('sysPwrGetInfo', (NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT * 32)), + ('bIsTspSupported', NvBool), + ('sysPwrLimitsTableVersion', NvU8), + ('type', NvU32), + ('cpuTdpmw', NvU32), ] - NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS -class struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS(Struct): pass struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS._fields_ = [ - ('bExternalFabricMgmt', ctypes.c_ubyte), + ('bExternalFabricMgmt', NvBool), ] - NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS._fields_ = [ - ('clientCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resourceCount', ctypes.c_uint64), + ('clientCount', NvU32), + ('resourceCount', NvU64), ] - NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS -class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS._fields_ = [ - ('driverVersionBuffer', ctypes.c_char * 256), - ('versionBuffer', ctypes.c_char * 256), - ('driverBranch', ctypes.c_char * 256), - ('titleBuffer', ctypes.c_char * 256), - ('changelistNumber', ctypes.c_uint32), - ('officialChangelistNumber', ctypes.c_uint32), + ('driverVersionBuffer', (ctypes.c_char * 256)), + ('versionBuffer', (ctypes.c_char * 256)), + ('driverBranch', (ctypes.c_char * 256)), + ('titleBuffer', (ctypes.c_char * 256)), + ('changelistNumber', NvU32), + ('officialChangelistNumber', NvU32), ] - NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS -class struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('mode', ctypes.c_uint32), + ('cmd', NvU32), + ('mode', NvU32), ] - NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), + ('command', NvU16), + ('locale', NvU16), + ('data', NvU32), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS(Structure): - pass - -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0._pack_ = 1 # source:False -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0._fields_ = [ - ('command', ctypes.c_uint16), - ('locale', ctypes.c_uint16), - ('data', ctypes.c_uint32), +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS(Struct): pass +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData(Struct): pass +struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData._fields_ = [ + ('command', NvU16), + ('locale', NvU16), + ('data', NvU32), ] - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS._pack_ = 1 # source:False struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS._fields_ = [ - ('cmdCount', ctypes.c_uint32), - ('succeeded', ctypes.c_uint32), - ('cmdData', struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0 * 16), + ('cmdCount', NvU32), + ('succeeded', NvU32), + ('cmdData', (struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData * 16)), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_int32 * 2), - ('result', ctypes.c_int32 * 4), + ('cmd', NvU32), + ('input', (NvS32 * 2)), + ('result', (NvS32 * 4)), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS._fields_ = [ - ('objHndl', ctypes.c_uint32), - ('blockId', ctypes.c_uint32), - ('nextExpectedSampleTimems', ctypes.c_uint32), - ('countersReq', ctypes.c_uint32), - ('countersReturned', ctypes.c_uint32), - ('counterBlock', ctypes.c_uint32 * 32), + ('objHndl', NvU32), + ('blockId', NvU32), + ('nextExpectedSampleTimems', NvU32), + ('countersReq', NvU32), + ('countersReturned', NvU32), + ('counterBlock', (NvU32 * 32)), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('input', ctypes.c_uint32), - ('resultSz', ctypes.c_uint32), - ('result', ctypes.c_uint32 * 288), + ('cmd', NvU32), + ('input', NvU32), + ('resultSz', NvU32), + ('result', (NvU32 * 288)), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE(Struct): pass struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE._fields_ = [ - ('frameTime', ctypes.c_uint16), - ('renderTime', ctypes.c_uint16), - ('targetTime', ctypes.c_uint16), - ('sleepTime', ctypes.c_ubyte), - ('sampleNumber', ctypes.c_ubyte), + ('frameTime', NvU16), + ('renderTime', NvU16), + ('targetTime', NvU16), + ('sleepTime', NvU8), + ('sampleNumber', NvU8), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS(Struct): pass struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS._fields_ = [ - ('samples', struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE * 64), - ('nextSampleNumber', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), + ('samples', (NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE * 64)), + ('nextSampleNumber', NvU8), ] - NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('sampleData', NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE), - ] - +class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS(Struct): pass +struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS._fields_ = [ + ('sampleData', NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE), +] NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS -class struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS -class struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuFlags', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), - ('subDeviceInstance', ctypes.c_uint32), - ('szName', ctypes.POINTER(None)), - ('sliStatus', ctypes.c_uint32), - ('boardId', ctypes.c_uint32), - ('gpuInstance', ctypes.c_uint32), - ('numaId', ctypes.c_int32), -] - -NV0000_CTRL_GPU_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS -class struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuFlags', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), - ('subDeviceInstance', ctypes.c_uint32), - ('sliStatus', ctypes.c_uint32), - ('boardId', ctypes.c_uint32), - ('gpuInstance', ctypes.c_uint32), - ('numaId', ctypes.c_int32), -] - -NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS -class struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('status', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS = struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS -class struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS._fields_ = [ - ('deviceIds', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS -class struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('excludedGpuIds', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS -class struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('slot', ctypes.c_uint16), -] - -NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS -class struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), - ('failedId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_ATTACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS -class struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS._fields_ = [ - ('gpuIds', ctypes.c_uint32 * 32), -] - -NV0000_CTRL_GPU_DETACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS -class struct_NV0000_CTRL_GPU_VIDEO_LINKS(Structure): - pass - -struct_NV0000_CTRL_GPU_VIDEO_LINKS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_VIDEO_LINKS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('connectedGpuIds', ctypes.c_uint32 * 8), -] - -NV0000_CTRL_GPU_VIDEO_LINKS = struct_NV0000_CTRL_GPU_VIDEO_LINKS -class struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('links', struct_NV0000_CTRL_GPU_VIDEO_LINKS * 32), - ] - -NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS = struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS -class struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('svmSize', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS = struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS -class struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS._fields_ = [ - ('gpuUuid', ctypes.c_ubyte * 256), - ('flags', ctypes.c_uint32), - ('gpuId', ctypes.c_uint32), - ('deviceInstance', ctypes.c_uint32), - ('subdeviceInstance', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS -class struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('gpuUuid', ctypes.c_ubyte * 256), - ('uuidStrLen', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS -class struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('newState', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS -class struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('drainState', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS -class struct_NV0000_CTRL_GPU_DISCOVER_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_DISCOVER_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_DISCOVER_PARAMS._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('slot', ctypes.c_ubyte), - ('function', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -NV0000_CTRL_GPU_DISCOVER_PARAMS = struct_NV0000_CTRL_GPU_DISCOVER_PARAMS -class struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS._fields_ = [ - ('enableMask', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS = struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS -class struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('bSkipHwNvlinkDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS = struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS(Structure): - pass - -class union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data(Union): - pass - -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet(Structure): - pass - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet._fields_ = [ - ('newValue', ctypes.c_uint32), - ('oldValue', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx(Structure): - pass - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx._fields_ = [ - ('paramData', ctypes.c_ubyte * 373), - ('PADDING_0', ctypes.c_ubyte * 3), - ('paramSize', ctypes.c_uint32), -] - -class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty(Structure): - pass - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty._fields_ = [ - ('propertyId', ctypes.c_uint32), - ('propertyIn', ctypes.c_uint32 * 6), - ('propertyOut', ctypes.c_uint32 * 5), -] - -union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data._pack_ = 1 # source:False -union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data._fields_ = [ - ('configSet', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet), - ('configEx', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx), - ('reservedProperty', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty), - ('PADDING_0', ctypes.c_ubyte * 332), -] - -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS._fields_ = [ - ('hContext', ctypes.c_uint32), - ('opType', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('dataType', ctypes.c_uint32), - ('data', union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data), -] - -NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS = struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS -class struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS._fields_ = [ - ('hDevice', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('phClients', ctypes.POINTER(None)), - ('phDevices', ctypes.POINTER(None)), - ('phChannels', ctypes.POINTER(None)), - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS = struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS -class struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS._fields_ = [ - ('image', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('totalSize', ctypes.c_uint64), - ('pData', ctypes.POINTER(None)), -] - -NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS = struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS -class struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_ubyte), -] - -NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS -class struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_ubyte), - ('bwModeScope', ctypes.c_ubyte), -] - -NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS -class struct_NV0000_CTRL_GPU_ACTIVE_DEVICE(Structure): - pass - -struct_NV0000_CTRL_GPU_ACTIVE_DEVICE._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_ACTIVE_DEVICE._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuInstanceId', ctypes.c_uint32), - ('computeInstanceId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_ACTIVE_DEVICE = struct_NV0000_CTRL_GPU_ACTIVE_DEVICE -class struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS._fields_ = [ - ('numDevices', ctypes.c_uint32), - ('devices', struct_NV0000_CTRL_GPU_ACTIVE_DEVICE * 256), -] - -NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS -class struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS -class struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS -NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE = (0xb01) # macro -NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED = (0x00000000) # macro -NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED = (0x00000001) # macro -NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = (0xb02) # macro -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO = (0xb03) # macro -NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS = (0xb04) # macro -NV0000_GPUACCT_PID_MAX_COUNT = 4000 # macro -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA = (0xb05) # macro -NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID = (0x5) # macro -class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('newState', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS -class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('state', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS -class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('subPid', ctypes.c_uint32), - ('gpuUtil', ctypes.c_uint32), - ('fbUtil', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('maxFbUsage', ctypes.c_uint64), - ('startTime', ctypes.c_uint64), - ('endTime', ctypes.c_uint64), -] - -NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS -class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('pidTbl', ctypes.c_uint32 * 4000), - ('pidCount', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS -class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('pid', ctypes.c_uint32), -] - -NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS -NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = (0x301) # macro -NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_GSYNC_INVALID_ID = (0xffffffff) # macro -NV0000_CTRL_CMD_GSYNC_GET_ID_INFO = (0x302) # macro -NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS._fields_ = [ - ('gsyncIds', ctypes.c_uint32 * 4), -] - -NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS -class struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS._fields_ = [ - ('gsyncId', ctypes.c_uint32), - ('gsyncFlags', ctypes.c_uint32), - ('gsyncInstance', ctypes.c_uint32), -] - -NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS -NV0000_CTRL_NVD_DUMP_COMPONENT_SYS = (0x400) # macro -NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG = (0x800) # macro -NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED = (0xB00) # macro -NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x601) # macro -NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_NVD_MAX_DUMP_SIZE = (1000000) # macro -NV0000_CTRL_CMD_NVD_GET_DUMP = (0x602) # macro -NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT = (0x00000000) # macro -NV0000_NVD_CPU_TIME_CLK_ID_OSTIME = (0x00000001) # macro -NV0000_NVD_CPU_TIME_CLK_ID_TSC = (0x00000002) # macro -NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API = (0x00000003) # macro -NV0000_CTRL_CMD_NVD_GET_TIMESTAMP = (0x603) # macro -NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO = (0x604) # macro -NV0000_CTRL_NVD_MAX_RUNTIME_SIZES = (16) # macro -NV0000_CTRL_NVD_SIGNATURE_SIZE = (4) # macro -NV0000_CTRL_NVD_MAX_BUFFERS = (3840) # macro -NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED = (0) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_INT = (1) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG = (2) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_STRING = (3) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_PTR = (4) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR = (5) # macro -NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT = (6) # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_INFO = 7 : 0 # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE = 23 : 8 # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT = (0x00000004) # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_RUNTIME_LEVEL = 28 : 25 # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP = 30 : 29 # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 = (0x00000001) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 = (0x00000002) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF = (0x00000003) # macro -# NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED = 31 : 31 # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES = (0x00000001) # macro -NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO = (0x605) # macro -NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE = 0 : 0 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED = 0 : 0 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE = 1 : 1 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE = 2 : 2 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED = 3 : 3 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES = (0x00000001) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING = 5 : 4 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE = (0x00000001) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL = (0x00000002) # macro -# NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA = 6 : 6 # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO = (0x00000000) # macro -NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES = (0x00000001) # macro -NV0000_CTRL_CMD_NVD_GET_NVLOG = (0x606) # macro -NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE = (4000) # macro -NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID = (0x6) # macro -NV0000_CTRL_CMD_NVD_GET_RCERR_RPT = (0x607) # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES = 200 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST = 0 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS = 1 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS = 2 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS = 3 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY = 0x00000000 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED = 0x00000001 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG = 0x0000000f # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST = 0x00000001 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST = 0x00000002 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID = 0x00000004 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID = 0x00000008 # macro -def TPC_REG_ATTR(gpcId, tpcId): # macro - return ((gpcId<<8)|(tpcId)) -def ROP_REG_ATTR(gpcId, ropId): # macro - return ((gpcId<<8)|(ropId)) -def SM_REG_ATTR(gpcId, tpcId, smId): # macro - return ((((gpcId)<<16)|((tpcId)<<8))|(smId)) -NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID = 0x00000000 # macro -NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID = 0xFFFFFFFF # macro -NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID = (0x7) # macro -NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS = (0x608) # macro -NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS -class struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [ - ('pBuffer', ctypes.POINTER(None)), - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV0000_CTRL_NVD_GET_DUMP_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS -class struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS._fields_ = [ - ('timestamp', ctypes.c_uint64), - ('cpuClkId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS = struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS -class struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('version', ctypes.c_uint32), - ('runtimeSizes', ctypes.c_ubyte * 16), - ('printFlags', ctypes.c_uint32), - ('signature', ctypes.c_uint32 * 4), - ('bufferTags', ctypes.c_uint32 * 3840), -] - -NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS -class struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('buffer', ctypes.c_uint32), - ('tag', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('pos', ctypes.c_uint32), - ('overflow', ctypes.c_uint32), -] - -NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS -class struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('buffer', ctypes.c_uint32), - ('blockNum', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 4000), -] - -NV0000_CTRL_NVD_GET_NVLOG_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS -class struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY(Structure): - pass - -struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY._fields_ = [ - ('tag', ctypes.c_uint32), - ('value', ctypes.c_uint32), - ('attribute', ctypes.c_uint32), -] - -NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY = struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY -class struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS(Structure): - pass - -struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS._fields_ = [ - ('reqIdx', ctypes.c_uint16), - ('rptIdx', ctypes.c_uint16), - ('GPUTag', ctypes.c_uint32), - ('rptTime', ctypes.c_uint32), - ('startIdx', ctypes.c_uint16), - ('endIdx', ctypes.c_uint16), - ('rptType', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('flags', ctypes.c_uint32), - ('rptCount', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('owner', ctypes.c_uint32), - ('processId', ctypes.c_uint32), - ('report', struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY * 200), -] - -NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS = struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS -class struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS._fields_ = [ - ('tsBufferSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pTSBuffer', ctypes.POINTER(None)), -] - -NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS = struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS -NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_SET_SUB_PROCESS_ID = (0x901) # macro -NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION = (0x902) # macro -class struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS(Structure): - pass - -struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS._fields_ = [ - ('subProcessID', ctypes.c_uint32), - ('subProcessName', ctypes.c_char * 100), -] - -NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS = struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS -class struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS(Structure): - pass - -struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS._fields_ = [ - ('bIsSubProcessDisabled', ctypes.c_ubyte), -] - -NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS = struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS -NV0000_SYNC_GPU_BOOST_MAX_GROUPS = (0x10) # macro -NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID = 0xFFFFFFFF # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO = (0xa01) # macro -NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE = (0xa02) # macro -NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY = (0xa03) # macro -NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = (0xa04) # macro -NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -class struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS._fields_ = [ - ('bEnabled', ctypes.c_ubyte), -] - -NV0000_SYNC_GPU_BOOST_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS -class struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG._fields_ = [ - ('gpuCount', ctypes.c_uint32), - ('gpuIds', ctypes.c_uint32 * 32), - ('boostGroupId', ctypes.c_uint32), - ('bBridgeless', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0000_SYNC_GPU_BOOST_GROUP_CONFIG = struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG -class struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('boostConfig', NV0000_SYNC_GPU_BOOST_GROUP_CONFIG), - ] - -NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS -class struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS._fields_ = [ - ('boostGroupId', ctypes.c_uint32), -] - -NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS -class struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS(Structure): - pass - -struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS._fields_ = [ - ('groupCount', ctypes.c_uint32), - ('pBoostGroups', struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG * 16), -] - -NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS -NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE = (0x3d02) # macro -NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH = (0x00000001) # macro -NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE = (0x00000002) # macro -NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE = (0x00000003) # macro -NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR = (0x3d04) # macro -NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = (0x3d05) # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD = 0 : 0 # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE = (0x00000000) # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE = (0x00000001) # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD = (0x3d06) # macro -NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID = (0x6) # macro -NV0000_CTRL_CMD_OS_GET_GPU_INFO = (0x3d07) # macro -NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO = (0x3d08) # macro -NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE = 64 # macro -NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST = (0x3d09) # macro -NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD = (0x3d0a) # macro -NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE = 64 # macro -NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID = (0xA) # macro -NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD = (0x3d0b) # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS = 512 # macro -NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID = (0xB) # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD = (0x3d0c) # macro -NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS = 128 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE = 0 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM = 1 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM = 2 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC = 3 # macro -NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC = 4 # macro -NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID = (0xC) # macro -class struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS._fields_ = [ - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('cacheOps', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('internalOnly', ctypes.c_uint64), + ('offset', NvU64), + ('length', NvU64), + ('cacheOps', NvU32), + ('hDevice', NvHandle), + ('hObject', NvHandle), + ('internalOnly', NvU64), ] - NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS = struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS -class struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), + ('fd', NvS32), ] - NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS = struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS +enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE = CEnum(ctypes.c_uint32) +NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE.define('NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', 0) +NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE.define('NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', 1) -# values for enumeration 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE' -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE__enumvalues = { - 0: 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', - 1: 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', -} -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0 -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1 -NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE = ctypes.c_uint32 # enum -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT(Structure): - pass - -class union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data(Union): - pass - -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject._pack_ = 1 # source:False -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject._fields_ = [ - ('hDevice', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), +NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE +class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT(Struct): pass +class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data(ctypes.Union): pass +class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject(Struct): pass +struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject._fields_ = [ + ('hDevice', NvHandle), + ('hParent', NvHandle), + ('hObject', NvHandle), ] - -union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data._pack_ = 1 # source:False -union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data._fields_ = [ - ('rmObject', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject), +struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data._fields_ = [ + ('rmObject', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject), ] - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT._pack_ = 1 # source:False struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT._fields_ = [ - ('type', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE), - ('data', union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data), + ('type', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE), + ('data', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data), ] - NV0000_CTRL_OS_UNIX_EXPORT_OBJECT = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS._fields_ = [ - ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT), - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), + ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT), + ('fd', NvS32), + ('flags', NvU32), ] - NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS -class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT), + ('fd', NvS32), + ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT), ] - NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS -class struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS(Struct): pass struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('minorNum', ctypes.c_uint32), + ('gpuId', NvU32), + ('minorNum', NvU32), ] - NV0000_CTRL_OS_GET_GPU_INFO_PARAMS = struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS -class struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('deviceInstance', ctypes.c_uint32), - ('gpuInstanceId', ctypes.c_uint32), - ('maxObjects', ctypes.c_uint16), - ('metadata', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), + ('fd', NvS32), + ('deviceInstance', NvU32), + ('gpuInstanceId', NvU32), + ('maxObjects', NvU16), + ('metadata', (NvU8 * 64)), ] - NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS = struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS -class struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS._fields_ = [ - ('hDevice', ctypes.c_uint32), - ('maxObjects', ctypes.c_uint16), - ('metadata', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), - ('fd', ctypes.c_int32), + ('hDevice', NvHandle), + ('maxObjects', NvU16), + ('metadata', (NvU8 * 64)), + ('fd', NvS32), ] - NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS -class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('hDevice', ctypes.c_uint32), - ('maxObjects', ctypes.c_uint16), - ('metadata', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), - ('objects', ctypes.c_uint32 * 512), - ('numObjects', ctypes.c_uint16), - ('index', ctypes.c_uint16), + ('fd', NvS32), + ('hDevice', NvHandle), + ('maxObjects', NvU16), + ('metadata', (NvU8 * 64)), + ('objects', (NvHandle * 512)), + ('numObjects', NvU16), + ('index', NvU16), ] - NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS -class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS(Structure): - pass - -struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS._pack_ = 1 # source:False +class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS(Struct): pass struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('hParent', ctypes.c_uint32), - ('objects', ctypes.c_uint32 * 128), - ('objectTypes', ctypes.c_ubyte * 128), - ('numObjects', ctypes.c_uint16), - ('index', ctypes.c_uint16), + ('fd', NvS32), + ('hParent', NvHandle), + ('objects', (NvHandle * 128)), + ('objectTypes', (NvU8 * 128)), + ('numObjects', NvU16), + ('index', NvU16), ] - NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS -# def NV2080_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x2080,NV2080_CTRL_##cat,idx) -NV2080_CTRL_RESERVED = (0x00) # macro -NV2080_CTRL_GPU = (0x01) # macro -NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED = (0x81) # macro -NV2080_CTRL_FUSE = (0x02) # macro -NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED = (0x82) # macro -NV2080_CTRL_EVENT = (0x03) # macro -NV2080_CTRL_TIMER = (0x04) # macro -NV2080_CTRL_THERMAL = (0x05) # macro -NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED = (0xc5) # macro -NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED = (0x85) # macro -NV2080_CTRL_I2C = (0x06) # macro -NV2080_CTRL_EXTI2C = (0x07) # macro -NV2080_CTRL_BIOS = (0x08) # macro -NV2080_CTRL_CIPHER = (0x09) # macro -NV2080_CTRL_INTERNAL = (0x0A) # macro -NV2080_CTRL_CLK_LEGACY_PRIVILEGED = (0xd0) # macro -NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED = (0x90) # macro -NV2080_CTRL_CLK = (0x10) # macro -NV2080_CTRL_FIFO = (0x11) # macro -NV2080_CTRL_GR = (0x12) # macro -NV2080_CTRL_FB = (0x13) # macro -NV2080_CTRL_MC = (0x17) # macro -NV2080_CTRL_BUS = (0x18) # macro -NV2080_CTRL_PERF_LEGACY_PRIVILEGED = (0xe0) # macro -NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0xa0) # macro -NV2080_CTRL_PERF = (0x20) # macro -NV2080_CTRL_NVIF = (0x21) # macro -NV2080_CTRL_RC = (0x22) # macro -NV2080_CTRL_GPIO = (0x23) # macro -NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED = (0xa3) # macro -NV2080_CTRL_NVD = (0x24) # macro -NV2080_CTRL_DMA = (0x25) # macro -NV2080_CTRL_PMGR = (0x26) # macro -NV2080_CTRL_PMGR_LEGACY_PRIVILEGED = (0xe6) # macro -NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED = (0xa6) # macro -NV2080_CTRL_POWER = (0x27) # macro -NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED = (0xa7) # macro -NV2080_CTRL_LPWR = (0x28) # macro -NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED = (0xa8) # macro -NV2080_CTRL_LPWR_LEGACY_PRIVILEGED = (0xe8) # macro -NV2080_CTRL_ACR = (0x29) # macro -NV2080_CTRL_CE = (0x2A) # macro -NV2080_CTRL_SPI = (0x2B) # macro -NV2080_CTRL_NVLINK = (0x30) # macro -NV2080_CTRL_FLCN = (0x31) # macro -NV2080_CTRL_VOLT = (0x32) # macro -NV2080_CTRL_VOLT_LEGACY_PRIVILEGED = (0xf2) # macro -NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED = (0xb2) # macro -NV2080_CTRL_FAS = (0x33) # macro -NV2080_CTRL_ECC = (0x34) # macro -NV2080_CTRL_ECC_NON_PRIVILEGED = (0xb4) # macro -NV2080_CTRL_FLA = (0x35) # macro -NV2080_CTRL_GSP = (0x36) # macro -NV2080_CTRL_NNE = (0x37) # macro -NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED = (0xb7) # macro -NV2080_CTRL_GRMGR = (0x38) # macro -NV2080_CTRL_UCODE_FUZZER = (0x39) # macro -NV2080_CTRL_DMABUF = (0x3A) # macro -NV2080_CTRL_BIF = (0x3B) # macro -NV2080_CTRL_OS_WINDOWS = (0x3F) # macro -NV2080_CTRL_OS_MACOS = (0x3E) # macro -NV2080_CTRL_OS_UNIX = (0x3D) # macro -NV2080_CTRL_CMD_NULL = (0x20800000) # macro -# def NV0080_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x0080,NV0080_CTRL_##cat,idx) -NV0080_CTRL_RESERVED = (0x00) # macro -NV0080_CTRL_BIF = (0x01) # macro -NV0080_CTRL_GPU = (0x02) # macro -NV0080_CTRL_CLK = (0x10) # macro -NV0080_CTRL_GR = (0x11) # macro -NV0080_CTRL_CIPHER = (0x12) # macro -NV0080_CTRL_FB = (0x13) # macro -NV0080_CTRL_HOST = (0x14) # macro -NV0080_CTRL_VIDEO = (0x15) # macro -NV0080_CTRL_FIFO = (0x17) # macro -NV0080_CTRL_DMA = (0x18) # macro -NV0080_CTRL_PERF = (0x19) # macro -NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0x99) # macro -NV0080_CTRL_MSENC = (0x1B) # macro -NV0080_CTRL_BSP = (0x1C) # macro -NV0080_CTRL_RC = (0x1D) # macro -NV0080_CTRL_OS_UNIX = (0x1E) # macro -NV0080_CTRL_NVJPG = (0x1F) # macro -NV0080_CTRL_INTERNAL = (0x20) # macro -NV0080_CTRL_NVLINK = (0x21) # macro -NV0080_CTRL_CMD_NULL = (0x800000) # macro -# def NV0080_CTRL_GET_CAP(cat, tbl, c): # macro -# return NV0080_CTRL_##cat##_GET_CAP(tbl,NV0080_CTRL_##cat##_CAPS_##c) -NV0080_CTRL_CMD_GR_GET_CAPS = (0x801102) # macro -NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x2) # macro -# def NV0080_CTRL_GR_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -NV0080_CTRL_GR_CAPS_TBL_SIZE = 23 # macro -NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000) # macro -NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001) # macro -NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002) # macro -NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003) # macro -NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004) # macro -NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005) # macro -NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006) # macro -NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007) # macro -NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008) # macro -NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009) # macro -NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A) # macro -NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B) # macro -NV0080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E) # macro -NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F) # macro -NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010) # macro -NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011) # macro -NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019) # macro -NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C) # macro -NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021) # macro -NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022) # macro -NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029) # macro -NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033) # macro -NV0080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033) # macro -NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038) # macro -NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039) # macro -NV0080_CTRL_GR_INFO_INDEX_MAX = (0x00000039) # macro -NV0080_CTRL_GR_INFO_MAX_SIZE = (0x3a) # macro -NV0080_CTRL_CMD_GR_GET_INFO = (0x801104) # macro -NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x4) # macro -NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE = (0x801107) # macro -NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x801108) # macro -NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x8) # macro -NV0080_CTRL_CMD_GR_GET_CAPS_V2 = (0x801109) # macro -NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x9) # macro -NV0080_CTRL_CMD_GR_GET_INFO_V2 = (0x801110) # macro -NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) # macro -# NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE = 1 : 0 # macro -NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE = 0x0 # macro -NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID = 0x1 # macro -NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL = 0x2 # macro -# NV2080_CTRL_GR_ROUTE_INFO_DATA_CHANNEL_HANDLE = 31 : 0 # macro -# NV2080_CTRL_GR_ROUTE_INFO_DATA_ENGID = 31 : 0 # macro -NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000) # macro -NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001) # macro -NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002) # macro -NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003) # macro -NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004) # macro -NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005) # macro -NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006) # macro -NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007) # macro -NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008) # macro -NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009) # macro -NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A) # macro -NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B) # macro -NV2080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E) # macro -NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F) # macro -NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010) # macro -NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011) # macro -NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019) # macro -NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C) # macro -NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021) # macro -NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022) # macro -NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029) # macro -NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E) # macro -# NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS # macro -# NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS # macro -# NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033) # macro -NV2080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033) # macro -NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038) # macro -NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039) # macro -NV2080_CTRL_GR_INFO_INDEX_MAX = (0x00000039) # macro -NV2080_CTRL_GR_INFO_MAX_SIZE = (0x3a) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_NONE = (0x00000000) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_05 = (0x00000105) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_1 = (0x00000110) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_2 = (0x00000120) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_3 = (0x00000130) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_4 = (0x00000140) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_1_5 = (0x00000150) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_2_0 = (0x00000200) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_2_1 = (0x00000210) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_2_2 = (0x00000220) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_0 = (0x00000300) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_1 = (0x00000310) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_2 = (0x00000320) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_3 = (0x00000330) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_5 = (0x00000350) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_6 = (0x00000360) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_8 = (0x00000380) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_3_9 = (0x00000390) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_4_0 = (0x00000400) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_0 = (0x00000500) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_02 = (0x00000502) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_03 = (0x00000503) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_0 = (0x00000600) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_01 = (0x00000601) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_02 = (0x00000602) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_0 = (0x00000700) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_01 = (0x00000701) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_02 = (0x00000702) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_03 = (0x00000703) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_05 = (0x00000705) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_02 = (0x00000802) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_06 = (0x00000806) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_07 = (0x00000807) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_08 = (0x00000808) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_09 = (0x00000809) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_9_00 = (0x00000900) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_00 = (0x00000A00) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_01 = (0x00000A01) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_04 = (0x00000A04) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_2 = ((0x00000502)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_5_3 = ((0x00000503)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_1 = ((0x00000601)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_6_2 = ((0x00000602)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_1 = ((0x00000701)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_2 = ((0x00000702)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_3 = ((0x00000703)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_7_5 = ((0x00000705)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_2 = ((0x00000802)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_6 = ((0x00000806)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_7 = ((0x00000807)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_8 = ((0x00000808)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_8_9 = ((0x00000809)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_9_0 = ((0x00000900)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_0 = ((0x00000A00)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_1 = ((0x00000A01)) # macro -NV2080_CTRL_GR_INFO_SM_VERSION_10_4 = ((0x00000A04)) # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D = 0 : 0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE = 0x1 # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D = 1 : 1 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE = 0x1 # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE = 2 : 2 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE = 0x1 # macro -# NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M = 3 : 3 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE = 0x0 # macro -NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE = 0x1 # macro -NV2080_CTRL_CMD_GR_GET_INFO = (0x20801201) # macro -NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE = (0x20801205) # macro -NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL = (0x00000000) # macro -NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW = (0x00000001) # macro -NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER = (0x00000002) # macro -NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = (0x20801206) # macro -NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED = True # macro -NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_GR_CTXSW_PM_MODE = (0x20801207) # macro -NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW = (0x00000000) # macro -NV2080_CTRL_CTXSW_PM_MODE_CTXSW = (0x00000001) # macro -NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW = (0x00000002) # macro -NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = (0x20801208) # macro -NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_GR_CTXSW_PM_BIND = (0x20801209) # macro -NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND = (0x2080123a) # macro -NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0x3A) # macro -NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES = 128 # macro -NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP = (0x2080120a) # macro -NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE = (0x2080120e) # macro -NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW = (0x00000000) # macro -NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW = (0x00000001) # macro -NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = (0x2080120f) # macro -NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT = 240 # macro -NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID = (0xF) # macro -NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = (0x20801210) # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID = (0x10) # macro -# NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP = 0 : 0 # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE = (0x00000000) # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET = (0x00000001) # macro -# NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP = 1 : 1 # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE = (0x00000000) # macro -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET = (0x00000001) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI = (0x00000000) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP = (0x00000001) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL = (0x00000002) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI = (0x00000000) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA = (0x00000001) # macro -NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP = (0x00000002) # macro -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND = (0x20801211) # macro -NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE = (0x20801212) # macro -NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_PC_SAMPLING_MODE_DISABLED = (0x00000000) # macro -NV2080_CTRL_PC_SAMPLING_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_CMD_GR_GET_ROP_INFO = (0x20801213) # macro -NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_CMD_GR_GET_CTXSW_STATS = (0x20801215) # macro -NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID = (0x15) # macro -# NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET = 0 : 0 # macro -NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE = (0x00000000) # macro -NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE = (0x00000001) # macro -NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = (0x20801218) # macro -NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT = 64 # macro -NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO = (0x20801219) # macro -NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN = 0 # macro -NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM = 1 # macro -NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM = 2 # macro -NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = (0x2080121b) # macro -NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT = 512 # macro -NV2080_CTRL_GR_DISABLED_SM_VGPC_ID = 0xFF # macro -NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x1B) # macro -NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL = (0x2080121c) # macro -NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID = (0x1C) # macro -NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT = 10 # macro -NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT = 10 # macro -NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA = (0x2080121d) # macro -NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID = (0x1D) # macro -NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE = (0x2080121e) # macro -NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x1E) # macro -NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE = (0x2080121f) # macro -NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID = (0x1F) # macro -NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE = (0x20801220) # macro -NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS = 64 # macro -NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS = (0x20801221) # macro -NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS = (0x20801222) # macro -NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_GR_GET_CAPS_V2 = (0x20801227) # macro -NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_GR_GET_INFO_V2 = (0x20801228) # macro -NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_GR_GET_GPC_MASK = (0x2080122a) # macro -NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID = (0x2A) # macro -NV2080_CTRL_CMD_GR_GET_TPC_MASK = (0x2080122b) # macro -NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x2080122c) # macro -NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES = (0x2080122d) # macro -NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x2D) # macro -NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = (0x20801230) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED = (0x0) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 = (0x1) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 = (0x2) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 = (0x3) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 = (0x4) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 = (0x5) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 = (0x6) # macro -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x30) # macro -NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID = (0x20801231) # macro -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID = (0x31) # macro -NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK = (0x20801232) # macro -NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID = (0x32) # macro -NV2080_CTRL_CMD_GR_GET_PPC_MASK = (0x20801233) # macro -NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID = (0x33) # macro -NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC = (0x20801234) # macro -NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID = (0x34) # macro -NV2080_CTRL_CMD_GR_GET_CTXSW_MODES = (0x20801235) # macro -NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x35) # macro -NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP = (0x20801236) # macro -NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_GR_GET_ZCULL_MASK = (0x20801237) # macro -NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 = (0x20801238) # macro -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO = (0x20801239) # macro -NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK = (0x2080123b) # macro -NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0x3b) # macro -NV_GRID_LICENSE_INFO_MAX_LENGTH = (128) # macro -NV_GRID_LICENSE_FEATURE_VPC_EDITION = "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" # macro -NV_GRID_LICENSE_FEATURE_VAPPS_EDITION = "GRID-Virtual-Apps,3.0" # macro -NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION = "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" # macro -NV_GRID_LICENSE_FEATURE_GAMING_EDITION = "GRID-vGaming,8.0" # macro -NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION = "NVIDIA-vComputeServer,9.0" # macro -NV_GRID_LICENSED_PRODUCT_VWS = "NVIDIA RTX Virtual Workstation" # macro -NV_GRID_LICENSED_PRODUCT_GAMING = "NVIDIA Cloud Gaming" # macro -NV_GRID_LICENSED_PRODUCT_VPC = "NVIDIA Virtual PC" # macro -NV_GRID_LICENSED_PRODUCT_VAPPS = "NVIDIA Virtual Applications" # macro -NV_GRID_LICENSED_PRODUCT_COMPUTE = "NVIDIA Virtual Compute Server" # macro -# NV2080_CTRL_GPU_INFO_INDEX_INDEX = 23 : 0 # macro -NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT = (0x00000004) # macro -NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 = (0x00000012) # macro -NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 = (0x00000013) # macro -NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED = (0x0000001b) # macro -NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS = (0x0000001f) # macro -NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD = (0x00000022) # macro -NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE = (0x00000025) # macro -NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED = (0x00000027) # macro -NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED = (0x00000028) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT = (0x00000029) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE = (0x0000002a) # macro -NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM = (0x0000002b) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION = (0x0000002c) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY = (0x0000002d) # macro -NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM = (0x0000002f) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY = (0x00000030) # macro -NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE = (0x00000031) # macro -NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED = (0x00000033) # macro -NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED = (0x00000034) # macro -NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED = (0x00000035) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY = (0x00000036) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY = (0x00000037) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY = (0x0000003a) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY = (0x0000003b) # macro -NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU = (0x0000003c) # macro -NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY = (0x0000003d) # macro -NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED = (0x0000003f) # macro -NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE = (0x00000041) # macro -# NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID = 30 : 24 # macro -# NV2080_CTRL_GPU_INFO_INDEX_RESERVED = 31 : 31 # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV = (0x00000003) # macro -NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING = (0x00000003) # macro -NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING = (0x00000004) # macro -NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED = (0x00000002) # macro -NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES = (0x00000001) # macro -# NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID = 31 : 1 # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES = (0x00000001) # macro -NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_CMD_GPU_GET_INFO = (0x20800101) # macro -NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_GPU_GET_INFO_V2 = (0x20800102) # macro -NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_GPU_GET_NAME_STRING = (0x20800110) # macro -NV2080_GPU_MAX_NAME_STRING_LENGTH = (0x0000040) # macro -# NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE = 31 : 0 # macro -NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII = (0x00000000) # macro -NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE = (0x00000001) # macro -NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = (0x20800111) # macro -NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_GPU_SET_POWER = (0x20800112) # macro -NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 = (0x00000000) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 = (0x00000001) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 = (0x00000002) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 = (0x00000003) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 = (0x00000004) # macro -NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 = (0x00000007) # macro -NV2080_CTRL_CMD_GPU_GET_SDM = (0x20800118) # macro -NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_CMD_GPU_SET_SDM = (0x20800120) # macro -NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = (0x20800119) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL = (0x00000001) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL = (0x00000002) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL = (0x00000003) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL = (0x00000004) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU = (0x00000005) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER = (0x00000006) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA = (0x00000007) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL = (0x00000008) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL = (0x00000009) # macro -NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_REG_OP_READ_32 = (0x00000000) # macro -NV2080_CTRL_GPU_REG_OP_WRITE_32 = (0x00000001) # macro -NV2080_CTRL_GPU_REG_OP_READ_64 = (0x00000002) # macro -NV2080_CTRL_GPU_REG_OP_WRITE_64 = (0x00000003) # macro -NV2080_CTRL_GPU_REG_OP_READ_08 = (0x00000004) # macro -NV2080_CTRL_GPU_REG_OP_WRITE_08 = (0x00000005) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL = (0x00000000) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX = (0x00000001) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC = (0x00000002) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM = (0x00000004) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP = (0x00000008) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP = (0x00000010) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_FB = (0x00000020) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD = (0x00000040) # macro -NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE = (0x00000080) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS = (0x00) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP = (0x01) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE = (0x02) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET = (0x04) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP = (0x08) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK = (0x10) # macro -NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS = (0x20) # macro -NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = (0x20800122) # macro -NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINES = (0x20800123) # macro -NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = (0x20800170) # macro -NV2080_GPU_MAX_ENGINES_LIST_SIZE = 0x54 # macro -NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID = (0x70) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST = (0x20800124) # macro -NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID = (0x24) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO = (0x20800125) # macro -NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_GPU_QUERY_MODE = (0x20800128) # macro -NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE = (0x00000000) # macro -NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE = (0x00000001) # macro -NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE = (0x00000002) # macro -NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN = 0 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM = 1 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH = 2 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB = 3 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL = 4 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB = 5 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL = 6 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL = 7 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK = 8 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT = 9 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP = 10 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP = 11 # macro -NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP = 12 # macro -NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES = 16 # macro -NV2080_CTRL_CMD_GPU_PROMOTE_CTX = (0x2080012b) # macro -NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_CMD_GPU_EVICT_CTX = (0x2080012c) # macro -NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_CMD_GPU_INITIALIZE_CTX = (0x2080012d) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID = (0x2D) # macro -# NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE = 1 : 0 # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM = (0x00000000) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS = (0x00000001) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS = (0x00000002) # macro -# NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE = 2 : 2 # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES = (0x00000000) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO = (0x00000001) # macro -# NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX = 3 : 3 # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO = (0x00000000) # macro -NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES = (0x00000001) # macro -NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR = (0x2080012e) # macro -NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = (0x2080012f) # macro -NV2080_CTRL_GPU_ECC_UNIT_GSP = (0x0000001D) # macro -NV2080_CTRL_GPU_ECC_UNIT_COUNT = (0x00000024) # macro -# NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE = 0 : 0 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED = (0x00000000) # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW = (0x00000001) # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE = 0 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE = 1 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE = 2 # macro -NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID = (0x2F) # macro -NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES = (0x20800130) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE = (0x00000001) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED = (0x00000002) # macro -NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS = (0x00000003) # macro -NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x30) # macro -NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = (0x20800131) # macro -NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x31) # macro -NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = (0x20800133) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED = (0x00000000) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x33) # macro -NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION = (0x20800134) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE = (0x00000000) # macro -NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE = (0x00000001) # macro -NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x34) # macro -NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS = (0x20800136) # macro -NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE = (0x00000000) # macro -NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE = (0x00000001) # macro -NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE = (0x00000002) # macro -# NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE = 0 : 0 # macro -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE = 0 # macro -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE = 1 # macro -NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO = (0x20800137) # macro -NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO = (0x20800138) # macro -NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO = (0x20800139) # macro -NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = (0x2080013f) # macro -NV2080_GPU_MAX_MARKETING_NAME_LENGTH = (0x00000018) # macro -NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH = (0x00000010) # macro -NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH = (0x00000014) # macro -NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH = (0x00000006) # macro -NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH = (0x00000014) # macro -NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID = (0x3F) # macro -NV2080_CTRL_CMD_GPU_GET_ID = (0x20800142) # macro -NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE = (0x20800143) # macro -NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x43) # macro -NV2080_CTRL_GPU_DEBUG_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_GPU_DEBUG_MODE_DISABLED = (0x00000002) # macro -NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE = (0x20800144) # macro -NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = (0x20800147) # macro -NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS = (0x00000020) # macro -NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_GPU_GET_GID_INFO = (0x2080014a) # macro -NV2080_GPU_MAX_GID_LENGTH = (0x000000100) # macro -NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH = (0x000000010) # macro -NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID = (0x4A) # macro -# NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT = 1 : 0 # macro -NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII = (0x00000000) # macro -NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY = (0x00000002) # macro -# NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE = 2 : 2 # macro -NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 = (0x00000000) # macro -NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = (0x2080014b) # macro -NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN = 3 # macro -NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID = (0x4B) # macro -NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO = (0x2080014c) # macro -NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID = (0x4C) # macro -NV2080_CTRL_CMD_GPU_GET_IP_VERSION = (0x2080014d) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4D) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY = (0x00000001) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC = (0x00000002) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_PMGR = (0x00000003) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU = (0x00000004) # macro -NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON = (0x00000005) # macro -NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS = 0 # macro -NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS = 1 # macro -NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT = (0x20800153) # macro -NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_GPU_GET_ILLUM = (0x20800154) # macro -NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_GPU_SET_ILLUM = (0x20800155) # macro -NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = (0x20800156) # macro -NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN = 16 # macro -NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT = (0x20800157) # macro -NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO = (0x2080015a) # macro -NV2080_CTRL_MAX_PHYSICAL_BRIDGE = (100) # macro -NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x5A) # macro -NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU = (0x2080015b) # macro -NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID = (0x5B) # macro -NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS = (0x2080015f) # macro -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID = (0x5F) # macro -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING = (0x00000000) # macro -NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE = (0x00000001) # macro -NV2080_CTRL_CMD_GPU_GET_VPR_CAPS = (0x20800160) # macro -NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID = (0x60) # macro -NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR = (0x20800167) # macro -NV2080_CTRL_CMD_GPU_GET_PES_INFO = (0x20800168) # macro -NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT = 10 # macro -NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID = (0x68) # macro -NV2080_CTRL_CMD_GPU_GET_OEM_INFO = (0x20800169) # macro -NV2080_GPU_MAX_OEM_INFO_LENGTH = (0x000001F8) # macro -NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID = (0x69) # macro -NV2080_CTRL_CMD_GPU_GET_VPR_INFO = (0x2080016b) # macro -NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID = (0x6B) # macro -NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY = (0x2080016c) # macro -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x6C) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS = (0x2080016d) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x6D) # macro -NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES = 0x200 # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x6E) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO = (0x2080016e) # macro -NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x6F) # macro -NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR = (0x2080016f) # macro -NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID = (0x72) # macro -NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT = (0x20800172) # macro -NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID = (0x73) # macro -NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS = (0x20800173) # macro -NV_GI_UUID_LEN = 16 # macro -PARTITIONID_INVALID = 0xFFFFFFFF # macro -NV2080_CTRL_GPU_PARTITION_ID_INVALID = 0xFFFFFFFF # macro -NV2080_CTRL_GPU_MAX_PARTITIONS = 0x00000008 # macro -NV2080_CTRL_GPU_MAX_PARTITION_IDS = 0x00000009 # macro -NV2080_CTRL_GPU_MAX_SMC_IDS = 0x00000008 # macro -NV2080_CTRL_GPU_MAX_GPC_PER_SMC = 0x0000000c # macro -NV2080_CTRL_GPU_MAX_CE_PER_SMC = 0x00000008 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE = 1 : 0 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL = 0x00000000 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF = 0x00000001 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER = 0x00000002 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH = 0x00000003 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE = 4 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE = 4 : 2 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL = 0x00000000 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF = 0x00000001 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF = 0x00000002 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER = 0x00000003 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER = 0x00000004 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH = 0x00000005 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 = 0x00000006 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 = 0x00000007 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE = 8 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE = 7 : 5 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL = 0x00000001 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF = 0x00000002 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF = 0x00000003 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER = 0x00000004 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH = 0x00000005 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 = 0x00000006 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 = 0x00000007 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE = 0x00000000 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE = 8 # macro -NV2080_CTRL_GPU_PARTITION_MAX_TYPES = 40 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA = 30 : 30 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE = 0 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE = 1 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN = 31 : 31 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE = 0 # macro -NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE = 1 # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_FULL)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_FULL)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_HALF)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_HALF)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_HALF)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_MINI_HALF)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_QUARTER)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_QUARTER)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_QUARTER)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_MINI_QUARTER)) # macro -# NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU = (DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_MEMORY_SIZE,_EIGHTH)|DRF_DEF(2080,_CTRL_GPU_PARTITION_FLAG,_COMPUTE_SIZE,_EIGHTH)) # macro -NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID = (0x74) # macro -NV2080_CTRL_CMD_GPU_SET_PARTITIONS = (0x20800174) # macro -NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID = (0x75) # macro -NV2080_CTRL_CMD_GPU_GET_PARTITIONS = (0x20800175) # macro -NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION = (0x20800176) # macro -NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID = (0x76) # macro -NV2080_CTRL_GPU_FAULT_PACKET_SIZE = 32 # macro -NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT = (0x20800177) # macro -NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID = (0x77) # macro -NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU = (0x20800178) # macro -NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID = (0x78) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE = (0x20800179) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID = (0x79) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR = (0xFFFFFFFB) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR = (0xFFFFFFFB) # macro -NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID = (0x2080017a) # macro -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID = (0x7A) # macro -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL = (0xFFFFFFFF) # macro -NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR = (0xFFFFFFFB) # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS = (0x2080017b) # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x7B) # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 0x00000001 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 0x00000002 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 0x00000004 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 0x00000008 # macro -NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 0x00000010 # macro -NV2080_GPU_NVFBC_MAX_SESSION_COUNT = 256 # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x7C) # macro -NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO = (0x2080017c) # macro -NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID = (0xe6) # macro -NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX = (0x208001e6) # macro -NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE = (0x2080017e) # macro -NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID = (0x7E) # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB = 0x02000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB = 0x04000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB = 0x08000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB = 0x10000000 # macro -NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB = 0x20000000 # macro -NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY = (0x20800181) # macro -NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID = (0x81) # macro -NV2080_CTRL_CMD_GPU_GET_CACHED_INFO = (0x20800182) # macro -NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID = (0x82) # macro -NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE = (0x20800183) # macro -# NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING = 1 : 0 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY = 0 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF = 1 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG = 2 # macro -NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID = (0x85) # macro -NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS = (0x20800185) # macro -NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE = (0x20800188) # macro -NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID = (0x88) # macro -NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID = (0x8A) # macro -NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC = (0x2080018a) # macro -NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID = (0x8B) # macro -NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = (0x2080018b) # macro -NV2080_CTRL_CMD_GPU_GET_PIDS = (0x2080018d) # macro -NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT = 950 # macro -NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID = (0x8D) # macro -NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS = (0x00000000) # macro -NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST = (0x00000001) # macro -NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE = (0x00000000) # macro -NV2080_CTRL_GPU_PID_INFO_INDEX_MAX = (0x00000000) # macro -NV2080_CTRL_CMD_GPU_GET_PID_INFO = (0x2080018e) # macro -NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT = 200 # macro -NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID = (0x8E) # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT = (0x20800192) # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID = 0 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 = 1 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 = 2 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL = 3 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE = 4 # macro -NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID = (0x92) # macro -NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE = 0 # macro -NV2080_CTRL_GPU_COMPUTE_POLICY_MAX = 1 # macro -NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x94) # macro -NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = (0x20800195) # macro -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX = 32 # macro -NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x95) # macro -NV2080_CTRL_CMD_GPU_GET_GFID = (0x20800196) # macro -NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID = (0x96) # macro -NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY = (0x20800197) # macro -NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID = (0x97) # macro -NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST = (0x20800198) # macro -NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID = (0x98) # macro -NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR = (0x20800199) # macro -NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x99) # macro -NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES = (0x2080019b) # macro -NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS = 0xC8 # macro -NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID = (0x9B) # macro -NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING = (0x2080019c) # macro -NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID = (0x9C) # macro -NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS = (0x2080019d) # macro -NV2080_CTRL_REG_OPS_ARRAY_MAX = 100 # macro -NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID = (0x9D) # macro -NV2080_GET_P2P_CAPS_UUID_LEN = 16 # macro -NV2080_CTRL_CMD_GET_P2P_CAPS = (0x208001a0) # macro -NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xA0) # macro -NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xA2) # macro -NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES = (0x208001a2) # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED = 1 # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS = 2 # macro -NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE = 3 # macro -NV2080_GPU_FABRIC_CLUSTER_UUID_LEN = 16 # macro -# NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED = NVBIT64 ( 0 ) # macro -# NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED = NVBIT64 ( 1 ) # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW = 1 : 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2 # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE = 3 : 2 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE = 2 # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY = 5 : 4 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE = 2 # macro -# NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY = 7 : 6 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1 # macro -NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2 # macro -NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xA3) # macro -NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = (0x208001a3) # macro -NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = (0x208001a4) # macro -GPU_PART_NUMBER_FMT = "%04X-%s-%X%X" # macro -NV2080_MAX_CHIP_SKU_LENGTH = 0x00000004 # macro -NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID = (0xA4) # macro -NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP = (0x208001a5) # macro -NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID = (0xA5) # macro -NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS = (0x208001a6) # macro -NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP = (0x208001a7) # macro -NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU = (0x208001a8) # macro -NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX = 50 # macro -NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID = (0xA6) # macro -NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID = (0xA7) # macro -NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID = (0xA8) # macro -NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET = (0x208001a9) # macro -NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET = (0x208001aa) # macro -NV2080_CTRL_CMD_GPU_GET_RESET_STATUS = (0x208001ab) # macro -NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAB) # macro -NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ac) # macro -NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ad) # macro -NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS = (0x208001ae) # macro -NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAE) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID = (0xAF) # macro -NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 = (0x208001af) # macro -NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS = 0x40 # macro -NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO = (0x208001b0) # macro -NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID = (0xB0) # macro -NV2080_CTRL_CMD_GPU_GET_VF_CAPS = (0x208001b1) # macro -NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID = (0xB1) # macro -NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = (0x208001b2) # macro -NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID = (0xB2) # macro -NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID = (0xe4) # macro -NV2080_CTRL_GPU_GET_FIPS_STATUS = (0x208001e4) # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU = 0x2 # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU = 0xC # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC = (0x18) # macro -NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT = (0x1a) # macro -NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID = (0xB3) # macro -NV2080_CTRL_GPU_GET_RAFTS_FS_MASK = (0x208001b3) # macro -NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY = (0x208001e5) # macro -NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID = (0xe5) # macro -NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK = (0x208001e7) # macro -NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0xe7) # macro -# NV0000_BUSDEVICE_DOMAIN = 31 : 16 # macro -# NV0000_BUSDEVICE_BUS = 15 : 8 # macro -# NV0000_BUSDEVICE_DEVICE = 7 : 0 # macro -# def GPU_32_BIT_ID_DECODE_DOMAIN(gpuId): # macro -# return (NvU16)DRF_VAL(0000,_BUSDEVICE,_DOMAIN,gpuId); -# def GPU_32_BIT_ID_DECODE_BUS(gpuId): # macro -# return (NvU8)DRF_VAL(0000,_BUSDEVICE,_BUS,gpuId); -# def GPU_32_BIT_ID_DECODE_DEVICE(gpuId): # macro -# return (NvU8)DRF_VAL(0000,_BUSDEVICE,_DEVICE,gpuId); -NV0000_CTRL_CMD_VGPU_CREATE_DEVICE = (0xc02) # macro -NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID = (0x2) # macro -NV0000_CTRL_CMD_VGPU_GET_INSTANCES = (0xc03) # macro -NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID = (0x3) # macro -NV0000_CTRL_CMD_VGPU_DELETE_DEVICE = (0xc04) # macro -NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID = (0x4) # macro -NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS = (0xc05) # macro -NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID = (0x5) # macro -NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE = (0x206) # macro -NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID = (0x6) # macro -class struct_NV0080_CTRL_GR_ROUTE_INFO(Structure): - pass +class struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS(Struct): pass +struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS._fields_ = [ + ('vgpuName', (NvU8 * 16)), + ('gpuPciId', NvU32), + ('gpuPciBdf', NvU32), + ('vgpuTypeId', NvU32), + ('vgpuId', NvU16), + ('gpuInstanceId', NvU32), + ('placementId', NvU32), +] +NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS +class struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS(Struct): pass +struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS._fields_ = [ + ('gpuPciId', NvU32), + ('gpuPciBdf', NvU32), + ('numVgpuTypes', NvU32), + ('vgpuTypeIds', (NvU32 * 64)), + ('availableInstances', (NvU32 * 64)), +] +NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS = struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS +class struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS(Struct): pass +struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS._fields_ = [ + ('vgpuName', (NvU8 * 16)), + ('vgpuId', NvU16), +] +NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS +class struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS(Struct): pass +struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS._fields_ = [ + ('returnStatus', NvU32), + ('gpuId', NvU32), +] +NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS = struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS +class struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS(Struct): pass +struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS._fields_ = [ + ('vgpuName', (NvU8 * 16)), + ('mode', NvU32), + ('sysfs_val', NvU32), +] +NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS = struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS +class struct_NV0080_CTRL_BIF_RESET_PARAMS(Struct): pass +struct_NV0080_CTRL_BIF_RESET_PARAMS._fields_ = [ + ('flags', NvU32), +] +NV0080_CTRL_BIF_RESET_PARAMS = struct_NV0080_CTRL_BIF_RESET_PARAMS +class struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS(Struct): pass +struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS._fields_ = [ + ('aspmFeatureSupported', NvU32), +] +NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS = struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS +class struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS(Struct): pass +struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS._fields_ = [ + ('bL0sEnable', NvBool), + ('bL1Enable', NvBool), +] +NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS = struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS +class struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS(Struct): pass +struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS._fields_ = [ + ('pciePowerControlMask', NvU32), + ('pciePowerControlIdentifiedKeyOrder', NvU32), + ('pciePowerControlIdentifiedKeyLocation', NvU32), +] +NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS = struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS +class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS._fields_ = [ + ('capsTblSize', NvU32), + ('capsTbl', NvP64), + ('instanceId', NvU32), +] +NV0080_CTRL_BSP_GET_CAPS_PARAMS = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS +class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2(Struct): pass +struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2._fields_ = [ + ('capsTbl', (NvU8 * 8)), + ('instanceId', NvU32), +] +NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 +class struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK(Struct): pass +struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK._fields_ = [ + ('pageSize', NvU64), + ('pteEntrySize', NvU64), + ('comptagLine', NvU32), + ('kind', NvU32), + ('pteFlags', NvU32), +] +NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK +class struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS._fields_ = [ + ('gpuAddr', NvU64), + ('subDeviceId', NvU32), + ('skipVASpaceInit', NvU8), + ('pteBlocks', (NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5)), + ('hVASpace', NvHandle), +] +NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS +class struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS._fields_ = [ + ('gpuAddr', NvU64), + ('subDeviceId', NvU32), + ('pteBlocks', (NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5)), + ('hVASpace', NvHandle), +] +NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS +class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS(Struct): pass +class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource(Struct): pass +struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('hMemory', NvHandle), + ('subDeviceId', NvU32), +] +class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo(Struct): pass +struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo._fields_ = [ + ('fbKind', NvU32), + ('sysKind', NvU32), + ('compTagStartOffset', NvU32), +] +struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS._fields_ = [ + ('pageCount', NvU32), + ('hwResource', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource), + ('comprInfo', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo), + ('offset', NvU64), + ('gpuAddr', NvU64), + ('pageArray', NvP64), + ('pteMem', NvP64), + ('pteMemPfn', NvU32), + ('pageSize', NvU32), + ('startPageIndex', NvU32), + ('flags', NvU32), + ('hSrcVASpace', NvHandle), + ('hTgtVASpace', NvHandle), + ('peerId', NvU32), +] +NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS = struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS +class struct_NV0080_CTRL_DMA_FLUSH_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_FLUSH_PARAMS._fields_ = [ + ('targetUnit', NvU32), +] +NV0080_CTRL_DMA_FLUSH_PARAMS = struct_NV0080_CTRL_DMA_FLUSH_PARAMS +class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT(Struct): pass +struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT._fields_ = [ + ('pageTableSize', NvU32), + ('pageTableCoverage', NvU32), +] +NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT +class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS._fields_ = [ + ('vaBitCount', NvU32), + ('pdeCoverageBitCount', NvU32), + ('num4KPageTableFormats', NvU32), + ('bigPageSize', NvU32), + ('compressionPageSize', NvU32), + ('dualPageTableSupported', NvU32), + ('idealVRAMPageSize', NvU32), + ('pageTableBigFormat', NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT), + ('pageTable4KFormat', (NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT * 16)), + ('hVASpace', NvHandle), + ('vaRangeLo', NvU64), + ('vaSpaceId', NvU32), + ('supportedPageSizeMask', NvU64), +] +NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS +class struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK(Struct): pass +struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK._fields_ = [ + ('ptePhysAddr', NvU64), + ('pteCacheAttrib', NvU32), + ('pteEntrySize', NvU32), + ('pageSize', NvU32), + ('pteAddrSpace', NvU32), + ('pdeVASpaceSize', NvU32), + ('pdeFlags', NvU32), +] +NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK +class struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS._fields_ = [ + ('gpuAddr', NvU64), + ('pdeVirtAddr', NvU64), + ('pdeEntrySize', NvU32), + ('pdeAddrSpace', NvU32), + ('pdeSize', NvU32), + ('subDeviceId', NvU32), + ('pteBlocks', (NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK * 5)), + ('pdbAddr', NvU64), + ('hVASpace', NvHandle), +] +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS +class struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [ + ('hVASpace', NvHandle), + ('flags', NvU32), +] +NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS +class struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS._fields_ = [ + ('capsTblSize', NvU32), + ('capsTbl', (NvU8 * 8)), +] +NV0080_CTRL_DMA_GET_CAPS_PARAMS = struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS +class struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS._fields_ = [ + ('vaSpaceSize', NvU64), + ('hVASpace', NvHandle), +] +NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS = struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS +class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS._fields_ = [ + ('physAddr', NvU64), + ('numEntries', NvU32), + ('aperture', NvU32), +] +NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS +class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS._fields_ = [ + ('pdeIndex', NvU32), + ('flags', NvU32), + ('ptParams', (NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS * 2)), + ('hVASpace', NvHandle), + ('pPdeBuffer', NvP64), + ('subDeviceId', NvU32), +] +NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS +class struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS._fields_ = [ + ('hVASpace', NvHandle), +] +NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS = struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS +class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS._fields_ = [ + ('hVASpace', NvHandle), +] +NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS +class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS._fields_ = [ + ('physAddress', NvU64), + ('numEntries', NvU32), + ('flags', NvU32), + ('hVASpace', NvHandle), + ('chId', NvU32), + ('subDeviceId', NvU32), + ('pasid', NvU32), +] +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS +class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS(Struct): pass +struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS._fields_ = [ + ('hVASpace', NvHandle), + ('subDeviceId', NvU32), +] +NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS +class struct_NV0080_CTRL_FB_GET_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_FB_GET_CAPS_PARAMS._fields_ = [ + ('capsTblSize', NvU32), + ('capsTbl', NvP64), +] +NV0080_CTRL_FB_GET_CAPS_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_PARAMS +class struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS(Struct): pass +struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS._fields_ = [ + ('Size', NvU64), + ('Address', NvU64), + ('AddressSpace', NvU32), + ('MaxCompbitLine', NvU32), + ('comptagsPerCacheLine', NvU32), + ('cacheLineSize', NvU32), + ('cacheLineSizePerSlice', NvU32), + ('cacheLineFetchAlignment', NvU32), + ('backingStoreBase', NvU64), + ('gobsPerComptagPerSlice', NvU32), + ('backingStoreCbcBase', NvU32), + ('comptaglineAllocationPolicy', NvU32), + ('privRegionStartOffset', NvU64), + ('cbcCoveragePerSlice', NvU32), +] +NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS = struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS +class struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS(Struct): pass +struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS._fields_ = [ + ('capsTbl', (NvU8 * 3)), +] +NV0080_CTRL_FB_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS +class struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS(Struct): pass +struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS._fields_ = [ + ('value', NvU32), +] +NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS = struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS +enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY = CEnum(ctypes.c_uint32) +NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', 0) +NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', 1) +NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', 2) +NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', 3) -struct_NV0080_CTRL_GR_ROUTE_INFO._pack_ = 1 # source:False +NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY +class struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS._fields_ = [ + ('capsTblSize', NvU32), + ('capsTbl', NvP64), +] +NV0080_CTRL_FIFO_GET_CAPS_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS +class struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [ + ('engineId', NvU32), + ('alignment', NvU32), + ('size', NvU32), +] +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS +class struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM(Struct): pass +struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM._fields_ = [ + ('hChannel1', NvHandle), + ('hChannel2', NvHandle), +] +NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM +class struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM(Struct): pass +struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM._fields_ = [ + ('hChannel', NvHandle), + ('tsDivisor', NvU32), +] +NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM +class struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS._fields_ = [ + ('hRunlist', NvHandle), + ('engineID', NvU32), +] +NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS +class struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS._fields_ = [ + ('numChannels', NvU32), + ('pChannelHandleList', NvP64), + ('pChannelList', NvP64), +] +NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS = struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS +class struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS._fields_ = [ + ('engineID', NvU32), + ('gpEntries', NvU32), + ('pbEntries', NvU32), +] +NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS = struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS +class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('property', NvU32), + ('value', NvU64), +] +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS +class struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS._fields_ = [ + ('engineID', NvU32), +] +NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS +class struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS._fields_ = [ + ('engineID', NvU32), +] +NV0080_CTRL_FIFO_START_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS +class struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS._fields_ = [ + ('capsTbl', (NvU8 * 2)), +] +NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS +class struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS(Struct): pass +struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS._fields_ = [ + ('numChannels', NvU32), + ('hChannels', (NvHandle * 4096)), + ('flags', NvU32), + ('timeout', NvU32), +] +NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS = struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS +class struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS._fields_ = [ + ('numClasses', NvU32), + ('classList', NvP64), +] +NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS +class struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS._fields_ = [ + ('numSubDevices', NvU32), +] +NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS = struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS +class struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS._fields_ = [ + ('ConnectionCount', NvU32), + ('Order', (NvU32 * 8)), +] +NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS = struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS +class struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS._fields_ = [ + ('subDeviceInstance', NvU32), +] +NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS +class struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS._fields_ = [ + ('subDeviceInstance', NvU32), +] +NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS +class struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS._fields_ = [ + ('enable', NvU32), +] +NV0080_CTRL_GPU_SET_VIDLINK_PARAMS = struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS +class struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [ + ('newState', NvU32), +] +NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS +class struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [ + ('swStatePersistence', NvU32), +] +NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS +class struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS._fields_ = [ + ('virtualizationMode', NvU32), + ('isGridBuild', NvBool), +] +NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS +class struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [ + ('defaultSetting', NvU32), + ('currentSetting', NvU32), + ('pendingSetting', NvU32), +] +NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS +class struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [ + ('setting', NvU32), +] +NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS +class struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS._fields_ = [ + ('isVgx', NvBool), +] +NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS +class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._fields_ = [ + ('totalVFs', NvU32), + ('firstVfOffset', NvU32), + ('vfFeatureMask', NvU32), + ('FirstVFBar0Address', NvU64), + ('FirstVFBar1Address', NvU64), + ('FirstVFBar2Address', NvU64), + ('bar0Size', NvU64), + ('bar1Size', NvU64), + ('bar2Size', NvU64), + ('b64bitBar0', NvBool), + ('b64bitBar1', NvBool), + ('b64bitBar2', NvBool), + ('bSriovEnabled', NvBool), + ('bSriovHeavyEnabled', NvBool), + ('bEmulateVFBar0TlbInvalidationRegister', NvBool), + ('bClientRmAllocatedCtxBuffer', NvBool), + ('bNonPowerOf2ChannelCountSupported', NvBool), + ('bVfResizableBAR1Supported', NvBool), +] +NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS +class struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS._fields_ = [ + ('numClasses', NvU32), + ('classList', (NvU32 * 100)), +] +NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS +class struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM(Struct): pass +struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM._fields_ = [ + ('subDeviceInst', NvU32), + ('hSubDevice', NvHandle), +] +NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM = struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM +class struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS._fields_ = [ + ('brands', NvU32), +] +NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS +class struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS._fields_ = [ + ('vfBar1SizeMB', NvU32), + ('numVfs', NvU32), +] +NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS +class struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ + ('bHeterogeneousMode', NvBool), +] +NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS +class struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS(Struct): pass +struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ + ('bHeterogeneousMode', NvBool), +] +NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS +class struct_NV0080_CTRL_GR_ROUTE_INFO(Struct): pass struct_NV0080_CTRL_GR_ROUTE_INFO._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('route', ctypes.c_uint64), + ('flags', NvU32), + ('route', NvU64), ] - NV0080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO -class struct_NV0080_CTRL_GR_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV0080_CTRL_GR_GET_CAPS_PARAMS(Struct): pass struct_NV0080_CTRL_GR_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), + ('capsTblSize', NvU32), + ('capsTbl', NvP64), ] - NV0080_CTRL_GR_GET_CAPS_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_PARAMS -class struct_NVXXXX_CTRL_XXX_INFO(Structure): - pass - -struct_NVXXXX_CTRL_XXX_INFO._pack_ = 1 # source:False -struct_NVXXXX_CTRL_XXX_INFO._fields_ = [ - ('index', ctypes.c_uint32), - ('data', ctypes.c_uint32), -] - +class struct_NVXXXX_CTRL_XXX_INFO(Struct): pass NV0080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV0080_CTRL_GR_GET_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_INFO_PARAMS._pack_ = 1 # source:False +struct_NVXXXX_CTRL_XXX_INFO._fields_ = [ + ('index', NvU32), + ('data', NvU32), +] +class struct_NV0080_CTRL_GR_GET_INFO_PARAMS(Struct): pass struct_NV0080_CTRL_GR_GET_INFO_PARAMS._fields_ = [ - ('grInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grInfoList', ctypes.POINTER(None)), + ('grInfoListSize', NvU32), + ('grInfoList', NvP64), ] - NV0080_CTRL_GR_GET_INFO_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_PARAMS +enum_NV0080_CTRL_GR_TPC_PARTITION_MODE = CEnum(ctypes.c_uint32) +NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', 0) +NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', 1) +NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', 2) -# values for enumeration 'NV0080_CTRL_GR_TPC_PARTITION_MODE' -NV0080_CTRL_GR_TPC_PARTITION_MODE__enumvalues = { - 0: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', - 1: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', - 2: 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', -} -NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = 0 -NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = 1 -NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = 2 -NV0080_CTRL_GR_TPC_PARTITION_MODE = ctypes.c_uint32 # enum -class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS._pack_ = 1 # source:False +NV0080_CTRL_GR_TPC_PARTITION_MODE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE +class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS(Struct): pass struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS._fields_ = [ - ('hChannelGroup', ctypes.c_uint32), - ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE), - ('bEnableAllTpcs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), + ('hChannelGroup', NvHandle), + ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE), + ('bEnableAllTpcs', NvBool), + ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), ] - NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS -class struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False +class struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS(Struct): pass struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 23), - ('PADDING_0', ctypes.c_ubyte), - ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), - ('bCapsPopulated', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), + ('capsTbl', (NvU8 * 23)), + ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), + ('bCapsPopulated', NvBool), ] - NV0080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS -class struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS._pack_ = 1 # source:False +class struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS(Struct): pass struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS._fields_ = [ - ('grInfoListSize', ctypes.c_uint32), - ('grInfoList', struct_NVXXXX_CTRL_XXX_INFO * 58), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), + ('grInfoListSize', NvU32), + ('grInfoList', (NV0080_CTRL_GR_INFO * 58)), + ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO), ] - NV0080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS -NV2080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO -NV2080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_GR_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_INFO_PARAMS._fields_ = [ - ('grInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grInfoList', ctypes.POINTER(None)), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +class struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS._fields_ = [ + ('capsTblSize', NvU32), + ('capsTbl', NvP64), ] - -NV2080_CTRL_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_INFO_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('hShareClient', ctypes.c_uint32), - ('hShareChannel', ctypes.c_uint32), - ('zcullMode', ctypes.c_uint32), +NV0080_CTRL_HOST_GET_CAPS_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS +class struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS(Struct): pass +struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS._fields_ = [ + ('capsTbl', (NvU8 * 3)), ] - -NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS._fields_ = [ - ('widthAlignPixels', ctypes.c_uint32), - ('heightAlignPixels', ctypes.c_uint32), - ('pixelSquaresByAliquots', ctypes.c_uint32), - ('aliquotTotal', ctypes.c_uint32), - ('zcullRegionByteMultiplier', ctypes.c_uint32), - ('zcullRegionHeaderSize', ctypes.c_uint32), - ('zcullSubregionHeaderSize', ctypes.c_uint32), - ('subregionCount', ctypes.c_uint32), - ('subregionWidthAlignPixels', ctypes.c_uint32), - ('subregionHeightAlignPixels', ctypes.c_uint32), +NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS +class struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS(Struct): pass +struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS._fields_ = [ + ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS), ] - -NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('pmMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS +class struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS(Struct): pass +struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS._fields_ = [ + ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS), ] - -NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), - ('zcullMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS +class struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS(Struct): pass +struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS._fields_ = [ + ('numClients', NvU32), + ('clientHandles', (NvHandle * 200)), ] - -NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), - ('pmMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS = struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS +class struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(Struct): pass +struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS._fields_ = [ + ('capsTblSize', NvU32), + ('capsTbl', NvP64), ] - -NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('vMemPtr', ctypes.c_uint64), +NV0080_CTRL_MSENC_GET_CAPS_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS +class struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(Struct): pass +struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS._fields_ = [ + ('capsTbl', (NvU8 * 4)), + ('instanceId', NvU32), ] - -NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS -class struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS._fields_ = [ - ('mapValueCount', ctypes.c_uint32), - ('mapValues', ctypes.c_ubyte * 128), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS +class struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS(Struct): pass +struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS._fields_ = [ + ('capsTbl', (NvU8 * 9)), + ('instanceId', NvU32), ] - -NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS -class struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('smpcMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS +class struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS(Struct): pass +struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [ + ('bActivate', NvBool), ] - -NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0(Structure): - pass - -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcId', ctypes.c_uint32), +NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS +class struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS(Struct): pass +struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS._fields_ = [ + ('bCudaLimit', NvBool), ] - -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS._fields_ = [ - ('smId', struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0 * 240), - ('smCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS +class struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS(Struct): pass +struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS._fields_ = [ + ('cmd', NvU32), ] - -NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS = struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS -class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS +class struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS(Struct): pass +struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS._fields_ = [ + ('subDeviceInstance', NvU32), + ('width', NvU16), + ('height', NvU16), + ('depth', NvU16), + ('pitch', NvU16), + ('baseAddress', NvU64), + ('size', NvU64), ] - -NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS' -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS__enumvalues = { - 0: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', - 1: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', - 2: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', - 3: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', - 4: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', - 5: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', - 6: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', - 7: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', - 8: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', - 9: 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', -} -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = 8 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 9 -NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vMemPtrs', ctypes.c_uint64 * 9), - ('gfxpPreemptMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS +NV2080_CTRL_BIOS_INFO = struct_NVXXXX_CTRL_XXX_INFO +class struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS._fields_ = [ + ('biosInfoListSize', NvU32), + ('biosInfoList', NvP64), ] - -NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS -class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('samplingMode', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV2080_CTRL_BIOS_GET_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS +class struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS._fields_ = [ + ('biosInfoListSize', NvU32), + ('biosInfoList', (NV2080_CTRL_BIOS_INFO * 15)), ] - -NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS._fields_ = [ - ('ropUnitCount', ctypes.c_uint32), - ('ropOperationsFactor', ctypes.c_uint32), - ('ropOperationsCount', ctypes.c_uint32), +NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS +class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING(Struct): pass +class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value(ctypes.Union): pass +struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value._fields_ = [ + ('ascii', (NvU8 * 256)), + ('unicode', (NvU16 * 256)), + ('hash', NvU16), ] - -NV2080_CTRL_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS -class struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('saveCnt', ctypes.c_uint32), - ('restoreCnt', ctypes.c_uint32), - ('wfiSaveCnt', ctypes.c_uint32), - ('ctaSaveCnt', ctypes.c_uint32), - ('cilpSaveCnt', ctypes.c_uint32), - ('gfxpSaveCnt', ctypes.c_uint32), +struct_NV2080_CTRL_BIOS_NBSI_REG_STRING._fields_ = [ + ('size', NvU32), + ('type', NvU32), + ('value', struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value), ] - -NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS -class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalBufferSize', ctypes.c_uint64), +NV2080_CTRL_BIOS_NBSI_REG_STRING = struct_NV2080_CTRL_BIOS_NBSI_REG_STRING +class struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS._fields_ = [ + ('module', NvU32), + ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING), + ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING), + ('retBuf', NvP64), + ('retSize', NvU32), + ('errorCode', NvU32), ] - -NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS -class struct_NV2080_CTRL_GR_CTX_BUFFER_INFO(Structure): - pass - -struct_NV2080_CTRL_GR_CTX_BUFFER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_CTX_BUFFER_INFO._fields_ = [ - ('alignment', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('bufferHandle', ctypes.POINTER(None)), - ('pageCount', ctypes.c_uint64), - ('physAddr', ctypes.c_uint64), - ('bufferType', ctypes.c_uint32), - ('aperture', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('bIsContigous', ctypes.c_ubyte), - ('bGlobalBuffer', ctypes.c_ubyte), - ('bLocalBuffer', ctypes.c_ubyte), - ('bDeviceDescendant', ctypes.c_ubyte), - ('uuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 4), +NV2080_CTRL_BIOS_GET_NBSI_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS +class struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS._fields_ = [ + ('module', NvU32), + ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING), + ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING), + ('retBuf', (NvU8 * 256)), + ('retSize', NvU32), + ('errorCode', NvU32), ] - -NV2080_CTRL_GR_CTX_BUFFER_INFO = struct_NV2080_CTRL_GR_CTX_BUFFER_INFO -PNV2080_CTRL_GR_CTX_BUFFER_INFO = ctypes.POINTER(struct_NV2080_CTRL_GR_CTX_BUFFER_INFO) -class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [ - ('hUserClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('bufferCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ctxBufferInfo', struct_NV2080_CTRL_GR_CTX_BUFFER_INFO * 64), +NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS +class struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS._fields_ = [ + ('globType', NvU16), + ('globIndex', NvU8), + ('globSource', NvU16), + ('retBufOffset', NvU32), + ('retBuf', NvP64), + ('retSize', NvU32), + ('totalObjSize', NvU32), + ('errorCode', NvU32), ] - -NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS -class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0(Structure): - pass - -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0._fields_ = [ - ('gpcId', ctypes.c_uint16), - ('localTpcId', ctypes.c_uint16), - ('localSmId', ctypes.c_uint16), - ('globalTpcId', ctypes.c_uint16), - ('virtualGpcId', ctypes.c_uint16), - ('migratableTpcId', ctypes.c_uint16), +NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS +class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._fields_ = [ + ('BoardID', NvU32), + ('chipSKU', (ctypes.c_char * 9)), + ('chipSKUMod', (ctypes.c_char * 5)), + ('skuConfigVersion', NvU32), + ('project', (ctypes.c_char * 5)), + ('projectSKU', (ctypes.c_char * 5)), + ('CDP', (ctypes.c_char * 6)), + ('projectSKUMod', (ctypes.c_char * 2)), + ('businessCycle', NvU32), ] - -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS._fields_ = [ - ('globalSmId', struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0 * 512), - ('numSm', ctypes.c_uint16), - ('numTpc', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS +class struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS._fields_ = [ + ('vbiosPostTime', NvU64), ] - -NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS -class struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS._fields_ = [ - ('chID', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS = struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS +class struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS(Struct): pass +struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS._fields_ = [ + ('version', NvU32), + ('flags', NvU32), ] - -NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS = struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS -class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC(Structure): - pass - -struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC._fields_ = [ - ('errorCounter', ctypes.c_uint64), - ('errorTimestamp', ctypes.c_uint64), - ('warningCounter', ctypes.c_uint64), - ('warningTimestamp', ctypes.c_uint64), +NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS = struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS +class struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS._fields_ = [ + ('pciDeviceId', NvU32), + ('pciSubSystemId', NvU32), + ('pciRevisionId', NvU32), + ('pciExtDeviceId', NvU32), ] - -NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC -class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('tpc', struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC * 10), - ] - -NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC -class struct_NV2080_CTRL_GR_VAT_ALARM_DATA(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('gpc', struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC * 10), - ] - -NV2080_CTRL_GR_VAT_ALARM_DATA = struct_NV2080_CTRL_GR_VAT_ALARM_DATA -class struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS._fields_ = [ - ('smVatAlarm', NV2080_CTRL_GR_VAT_ALARM_DATA), - ('maxGpcCount', ctypes.c_uint32), - ('maxTpcPerGpcCount', ctypes.c_uint32), +NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS +NV2080_CTRL_BUS_INFO = struct_NVXXXX_CTRL_XXX_INFO +class struct_NV2080_CTRL_BUS_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_INFO_PARAMS._fields_ = [ + ('busInfoListSize', NvU32), + ('busInfoList', NvP64), ] - -NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS -PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS) -class struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS._fields_ = [ - ('attribBufferSize', ctypes.c_uint32), +NV2080_CTRL_BUS_GET_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_PARAMS +class struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS._fields_ = [ + ('busInfoListSize', NvU32), + ('busInfoList', (NV2080_CTRL_BUS_INFO * 52)), ] - -NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS._fields_ = [ - ('maxSlots', ctypes.c_uint32), - ('slotStride', ctypes.c_uint32), - ('ctrlStructSize', ctypes.c_uint64), - ('ctrlStructAlign', ctypes.c_uint64), - ('poolSize', ctypes.c_uint64), - ('poolAlign', ctypes.c_uint64), +NV2080_CTRL_BUS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS +class struct_NV2080_CTRL_BUS_PCI_BAR_INFO(Struct): pass +struct_NV2080_CTRL_BUS_PCI_BAR_INFO._fields_ = [ + ('flags', NvU32), + ('barSize', NvU32), + ('barSizeBytes', NvU64), + ('barOffset', NvU64), ] - -NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS._fields_ = [ - ('maxSlots', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), +NV2080_CTRL_BUS_PCI_BAR_INFO = struct_NV2080_CTRL_BUS_PCI_BAR_INFO +class struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS._fields_ = [ + ('pciBarCount', NvU32), + ('pciBarInfo', (NV2080_CTRL_BUS_PCI_BAR_INFO * 8)), ] - -NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS._fields_ = [ - ('numSlots', ctypes.c_uint32), - ('slots', ctypes.c_uint32 * 64), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), +NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS +class struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS._fields_ = [ + ('pcieLinkWidth', NvU32), + ('failingReason', NvU32), ] - -NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS -class struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS._fields_ = [ - ('numSlots', ctypes.c_uint32), - ('slots', ctypes.c_uint32 * 64), - ('bRemoveSpecificSlots', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), +NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS +class struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS._fields_ = [ + ('busSpeed', NvU32), ] - -NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS -NV2080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS -NV2080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('gpcMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), +NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS +class struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS._fields_ = [ + ('hMemory', NvHandle), ] - -NV2080_CTRL_GR_GET_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS -class struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), +NV2080_CTRL_BUS_MAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS +class struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS._fields_ = [ + ('hMemory', NvHandle), ] - -NV2080_CTRL_GR_GET_TPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS -NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS -class struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('engineId', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('bInfoPopulated', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), +NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS +class struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS._fields_ = [ + ('hMemory', NvHandle), + ('offset', NvU32), + ('size', NvU32), ] - -NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS -class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('imla0', ctypes.c_ubyte), - ('fmla16', ctypes.c_ubyte), - ('dp', ctypes.c_ubyte), - ('fmla32', ctypes.c_ubyte), - ('ffma', ctypes.c_ubyte), - ('imla1', ctypes.c_ubyte), - ('imla2', ctypes.c_ubyte), - ('imla3', ctypes.c_ubyte), - ('imla4', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), +NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS = struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS +class struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS._fields_ = [ + ('command', NvU8), + ('deviceState', NvU32), ] - -NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS - -# values for enumeration 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD' -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD__enumvalues = { - 0: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', - 1: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', - 2: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', - 3: 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', -} -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = 0 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = 1 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = 2 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = 3 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('recordSize', ctypes.c_uint32), - ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD), - ('eventFilter', ctypes.c_uint32), - ('bAllUsers', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), +NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS = struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS +class struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS._fields_ = [ + ('pexCounterMask', NvU32), + ('pexTotalCorrectableErrors', NvU32), + ('pexCorrectableErrors', NvU16), + ('pexTotalNonFatalErrors', NvU8), + ('pexTotalFatalErrors', NvU8), + ('pexTotalUnsupportedReqs', NvU8), + ('pexCounters', (NvU16 * 31)), ] - -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS -class struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS._fields_ = [ - ('physSyspipeId', ctypes.c_uint32), - ('gpcMask', ctypes.c_uint32), +NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS +class struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS._fields_ = [ + ('pexCounterMask', NvU32), ] - -NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS -class struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('gpcId', ctypes.c_uint32), - ('ppcMask', ctypes.c_uint32), +NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS +class struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS._fields_ = [ + ('pexCounterMask', NvU32), + ('bFreezeRmCounter', NvBool), ] - -NV2080_CTRL_GR_GET_PPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS -class struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('numTpcs', ctypes.c_uint32), +NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS +class struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS._fields_ = [ + ('pexLaneErrorStatus', NvU16), + ('pexLaneCounter', (NvU8 * 16)), ] - -NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS = struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS -class struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('zcullMode', ctypes.c_uint32), - ('pmMode', ctypes.c_uint32), - ('smpcMode', ctypes.c_uint32), - ('cilpPreemptMode', ctypes.c_uint32), - ('gfxpPreemptMode', ctypes.c_uint32), +NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS +class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS._fields_ = [ + ('bPexLtrRegkeyOverride', NvBool), + ('bPexRootPortLtrSupported', NvBool), + ('bPexGpuLtrSupported', NvBool), + ('pexLtrSnoopLatencyValue', NvU16), + ('pexLtrSnoopLatencyScale', NvU8), + ('pexLtrNoSnoopLatencyValue', NvU16), + ('pexLtrNoSnoopLatencyScale', NvU8), ] - -NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS -NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS -class struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('zcullMask', ctypes.c_uint32), +NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS +class struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS._fields_ = [ + ('pexLtrSnoopLatencyValue', NvU16), + ('pexLtrSnoopLatencyScale', NvU8), + ('pexLtrNoSnoopLatencyValue', NvU16), + ('pexLtrNoSnoopLatencyScale', NvU8), ] - -NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS - -# values for enumeration 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE' -NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE__enumvalues = { - 0: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', - 1: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', - 2: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', - 3: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', - 4: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', - 5: 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', -} -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = 0 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = 1 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = 2 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = 3 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = 4 -NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = 5 -NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('recordSize', ctypes.c_uint32), - ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD), - ('eventFilter', ctypes.c_uint32), - ('bAllUsers', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('reasonCode', ctypes.c_uint32), +NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS +class struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS._fields_ = [ + ('pexCounterMask', NvU32), + ('pexCounters', (NvU32 * 7)), ] - -NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS -class struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('physGfxGpcMask', ctypes.c_uint32), - ('numGfxTpc', ctypes.c_uint32), +NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS +class struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS._fields_ = [ + ('pexCounterMask', NvU32), ] - -NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS -class struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [ - ('gpc', ctypes.c_uint32), - ('tpcReconfigMask', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS +class struct_NV2080_CTRL_BUS_GET_BFD_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_BFD_PARAMS._fields_ = [ + ('valid', NvBool), + ('deviceID', NvU16), + ('vendorID', NvU16), + ('domain', NvU32), + ('bus', NvU16), + ('device', NvU16), + ('function', NvU8), ] +NV2080_CTRL_BUS_GET_BFD_PARAMS = struct_NV2080_CTRL_BUS_GET_BFD_PARAMS +class struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR(Struct): pass +struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR._fields_ = [ + ('params', (NV2080_CTRL_BUS_GET_BFD_PARAMS * 32)), +] +NV2080_CTRL_BUS_GET_BFD_PARAMSARR = struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR +class struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS._fields_ = [ + ('aspmDisableFlags', (NvBool * 9)), +] +NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS = struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS +class struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS._fields_ = [ + ('bEnable', NvBool), +] +NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS = struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS +class struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS._fields_ = [ + ('nvlinkPeerIdMask', (NvU32 * 32)), +] +NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS = struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS +class struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS._fields_ = [ + ('eomMode', NvU8), + ('eomNblks', NvU8), + ('eomNerrs', NvU8), +] +NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS +class struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS._fields_ = [ + ('regAddress', NvU32), + ('laneSelectMask', NvU32), + ('regValue', NvU16), +] +NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS +class struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS._fields_ = [ + ('eomMode', NvU8), + ('eomNblks', NvU8), + ('eomNerrs', NvU8), + ('eomBerEyeSel', NvU8), + ('eomPamEyeSel', NvU8), + ('laneMask', NvU32), + ('eomStatus', (NvU16 * 32)), +] +NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS = struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS +class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS._fields_ = [ + ('capType', NvU32), + ('dbdf', NvU32), + ('atomicsCaps', NvU32), +] +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS +class struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO(Struct): pass +struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO._fields_ = [ + ('bSupported', NvBool), + ('attributes', NvU32), +] +NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO = struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO +class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS._fields_ = [ + ('capType', NvU32), + ('dbdf', NvU32), + ('atomicOp', (NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO * 13)), +] +NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS +class struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS._fields_ = [ + ('bIsLinkUp', NvBool), + ('nrLinks', NvU32), + ('maxNrLinks', NvU32), + ('linkMask', NvU32), + ('perLinkBwMBps', NvU32), + ('perLinkLaneWidth', NvU32), + ('remoteType', NvU32), +] +NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS +class struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS._fields_ = [ + ('bDisable', NvBool), +] +NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS = struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS +class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS._fields_ = [ + ('connectionType', NvU32), + ('peerId', NvU32), + ('bEgmPeer', NvBool), + ('bSpaAccessOnly', NvBool), + ('bUseUuid', NvBool), + ('remoteGpuId', NvU32), + ('remoteGpuUuid', (NvU8 * 16)), +] +NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS +class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS(Struct): pass +struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS._fields_ = [ + ('connectionType', NvU32), + ('peerId', NvU32), + ('bUseUuid', NvBool), + ('remoteGpuId', NvU32), + ('remoteGpuUuid', (NvU8 * 16)), +] +NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS +class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS._fields_ = [ + ('atomicsCaps', NvU32), +] +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS +class struct_NV2080_CTRL_CE_GET_CAPS_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_CAPS_PARAMS._fields_ = [ + ('ceEngineType', NvU32), + ('capsTblSize', NvU32), + ('capsTbl', NvP64), +] +NV2080_CTRL_CE_GET_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_PARAMS +class struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS._fields_ = [ + ('ceEngineType', NvU32), + ('capsTbl', (NvU8 * 2)), +] +NV2080_CTRL_CE_GET_CAPS_V2_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS +class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS._fields_ = [ + ('ceEngineType', NvU32), + ('pceMask', NvU32), +] +NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS +class struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS._fields_ = [ + ('ceEngineType', NvU32), + ('pceLceMap', (NvU32 * 32)), + ('grceSharedLceMap', (NvU32 * 4)), +] +NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS = struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS +class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS._fields_ = [ + ('pceLceMap', (NvU32 * 32)), + ('grceConfig', (NvU32 * 4)), + ('exposeCeMask', NvU32), + ('bUpdateNvlinkPceLce', NvBool), +] +NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS +class struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS._fields_ = [ + ('stubbedCeMask', NvU32), +] +NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS = struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS +NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS +class struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS._fields_ = [ + ('size', NvU32), +] +NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS +class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS._fields_ = [ + ('hshubPceMasks', (NvU32 * 32)), + ('fbhubPceMask', NvU32), +] +NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS +class struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS._fields_ = [ + ('capsTbl', ((NvU8 * 2) * 64)), + ('present', NvU64), +] +NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS +NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS +class struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS._fields_ = [ + ('ceEngineType', NvU32), + ('shimInstance', NvU32), + ('shimLocalLceIdx', NvU32), +] +NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS = struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS +class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS._fields_ = [ + ('pceLceMap', (NvU32 * 32)), + ('grceConfig', (NvU32 * 4)), + ('exposeCeMask', NvU32), + ('bUpdateNvlinkPceLce', NvBool), + ('shimInstance', NvU32), +] +NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS +class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS._fields_ = [ + ('connectingHubPceMasks', (NvU32 * 32)), + ('fbhubPceMask', NvU32), + ('shimInstance', NvU32), +] +NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS +enum_NV2080_CTRL_CE_LCE_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_CE_LCE_TYPE_PCIE = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE', 1) +NV2080_CTRL_CE_LCE_TYPE_DECOMP = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_DECOMP', 2) +NV2080_CTRL_CE_LCE_TYPE_SCRUB = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_SCRUB', 3) +NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', 4) +NV2080_CTRL_CE_LCE_TYPE_C2C = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C', 5) +NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', 6) +NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', 7) +NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', 8) +NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', 9) -NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS +NV2080_CTRL_CE_LCE_TYPE = enum_NV2080_CTRL_CE_LCE_TYPE +class struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS._fields_ = [ + ('lceType', NV2080_CTRL_CE_LCE_TYPE), + ('numPces', NvU32), + ('numLces', NvU32), + ('supportedPceMask', NvU32), + ('supportedLceMask', NvU32), + ('pcePerHshub', NvU32), +] +NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS = struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS +class struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS._fields_ = [ + ('decompLceMask', NvU64), + ('shimInstance', NvU32), +] +NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS +class struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS(Struct): pass +struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS._fields_ = [ + ('lceIndex', NvU32), + ('bDecompEnabled', NvBool), +] +NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS = struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS +class struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Struct): pass +struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hDevice', NvHandle), + ('engine', NvU32), + ('hVASpace', NvHandle), +] +NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS +NV2080_CTRL_DMA_INFO = struct_NVXXXX_CTRL_XXX_INFO +class struct_NV2080_CTRL_DMA_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_DMA_GET_INFO_PARAMS._fields_ = [ + ('dmaInfoTblSize', NvU32), + ('dmaInfoTbl', (NV2080_CTRL_DMA_INFO * 256)), +] +NV2080_CTRL_DMA_GET_INFO_PARAMS = struct_NV2080_CTRL_DMA_GET_INFO_PARAMS +class struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO(Struct): pass +struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO._fields_ = [ + ('srcAddr', NvU32), + ('dstAddr', NvU32), + ('relComptagIndex', NvU16), +] +NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO = struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO +class struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO(Struct): pass +struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO._fields_ = [ + ('hMemory', NvHandle), + ('offset', NvU64), + ('size', NvU64), +] +NV2080_CTRL_DMABUF_MEM_HANDLE_INFO = struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO +class struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS(Struct): pass +struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS._fields_ = [ + ('fd', NvS32), + ('totalObjects', NvU32), + ('numObjects', NvU32), + ('index', NvU32), + ('totalSize', NvU64), + ('mappingType', NvU8), + ('handles', (NV2080_CTRL_DMABUF_MEM_HANDLE_INFO * 128)), +] +NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS = struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS +class struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS(Struct): pass +struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS._fields_ = [ + ('sramParityUncorrectedUnique', NvU64), + ('sramSecDedUncorrectedUnique', NvU64), + ('sramCorrectedUnique', NvU64), + ('dramUncorrectedTotal', NvU64), + ('dramCorrectedTotal', NvU64), + ('lastClearedTimestamp', NvU32), + ('sramBucketL2', NvU64), + ('sramBucketSM', NvU64), + ('sramBucketPcie', NvU64), + ('sramBucketFirmware', NvU64), + ('sramBucketOther', NvU64), + ('sramErrorThresholdExceeded', NvBool), +] +NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS = struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS +class struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS(Struct): pass +struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS._fields_ = [ + ('sramCorUni', NvU64), + ('sramUncParityUni', NvU64), + ('sramUncSecDedUni', NvU64), + ('dramCorTot', NvU64), + ('dramUncTot', NvU64), +] +NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS = struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS +class struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [ + ('event', NvU32), + ('action', NvU32), + ('bNotifyState', NvBool), + ('info32', NvU32), + ('info16', NvU16), +] +NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS +enum_NV2080_EVENT_HDACODEC_DSTATE = CEnum(ctypes.c_uint32) +NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', 0) +NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', 1) +NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', 2) +NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', 3) +NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', 4) +NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', 5) + +NV2080_EVENT_HDACODEC_DSTATE = enum_NV2080_EVENT_HDACODEC_DSTATE +class struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS._fields_ = [ + ('hMemory', NvHandle), +] +NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS = struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS +class struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS._fields_ = [ + ('hSemMemory', NvHandle), + ('semOffset', NvU32), +] +NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS +class struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS._fields_ = [ + ('guestMSIAddr', NvU64), + ('guestMSIData', NvU32), + ('hSemMemory', NvHandle), + ('isReset', NvBool), + ('vgpuUuid', (NvU8 * 16)), + ('domainId', NvU64), +] +NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS = struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS +class struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS._fields_ = [ + ('hSemMemory', NvHandle), + ('isSemaMemValidationEnabled', NvBool), +] +NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS +class struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS._fields_ = [ + ('hEvent', NvHandle), +] +NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS = struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS +enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD = CEnum(ctypes.c_uint32) +NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', 0) +NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', 1) +NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', 2) + +NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD +class struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS._fields_ = [ + ('hEventBuffer', NvHandle), + ('recordSize', NvU32), + ('levelOfDetail', NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD), + ('eventFilter', NvU32), + ('bAllUsers', NvBool), +] +NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS +class struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS(Struct): pass +struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS._fields_ = [ + ('hEventBuffer', NvHandle), + ('tracepointMask', NvU64), + ('gspLoggingBufferSize', NvU32), + ('gspLoggingBufferWatermark', NvU32), +] +NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS +NV2080_CTRL_FB_INFO = struct_NVXXXX_CTRL_XXX_INFO +class struct_NV2080_CTRL_FB_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_INFO_PARAMS._fields_ = [ + ('fbInfoListSize', NvU32), + ('fbInfoList', NvP64), +] +NV2080_CTRL_FB_GET_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_PARAMS +class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS._fields_ = [ + ('fbInfoListSize', NvU32), + ('fbInfoList', (NV2080_CTRL_FB_INFO * 57)), +] +NV2080_CTRL_FB_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS +class struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS._fields_ = [ + ('cpuVirtAddress', NvP64), + ('gpuVirtAddress', NvU64), +] +NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS = struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS +class struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS._fields_ = [ + ('flags', NvU32), + ('driveStrengthRiseCount', NvU32), + ('driveStrengthFallCount', NvU32), + ('driveStrengthTermCount', NvU32), + ('slewStrengthRiseCount', NvU32), + ('slewStrengthFallCount', NvU32), +] +NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS = struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS +class struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS._fields_ = [ + ('flags', NvU32), +] +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS = struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS +class struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS._fields_ = [ + ('addressArray', (NvU64 * 500)), + ('addressArraySize', NvU32), + ('addressAlign', NvU32), + ('memBlockSizeBytes', NvU64), + ('flags', NvU32), +] +NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS = struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS +class struct_NV2080_CTRL_FB_IS_KIND_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_IS_KIND_PARAMS._fields_ = [ + ('operation', NvU32), + ('kind', NvU32), + ('result', NvBool), +] +NV2080_CTRL_FB_IS_KIND_PARAMS = struct_NV2080_CTRL_FB_IS_KIND_PARAMS +class struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS._fields_ = [ + ('powerState', NvU32), + ('writeMode', NvU32), + ('bypassMode', NvU32), + ('rcmState', NvU32), +] +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS +NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = (ctypes.c_ubyte * 17) +class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._fields_ = [ + ('base', NvU64), + ('limit', NvU64), + ('reserved', NvU64), + ('performance', NvU32), + ('supportCompressed', NvBool), + ('supportISO', NvBool), + ('bProtected', NvBool), + ('blackList', NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG), +] +NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO +class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._fields_ = [ + ('numFBRegions', NvU32), + ('fbRegion', (NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO * 16)), +] +NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS +class struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO(Struct): pass +struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO._fields_ = [ + ('pageAddressWithEccOn', NvU64), + ('pageAddressWithEccOff', NvU64), + ('rbcAddress', NvU32), + ('source', NvU32), + ('status', NvU32), + ('timestamp', NvU32), +] +NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO +class struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS._fields_ = [ + ('offlined', (NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64)), + ('pageSize', NvU32), + ('validEntries', NvU32), + ('numPagesAdded', NvU32), +] +NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS = struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS +class struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS._fields_ = [ + ('offlined', (NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64)), + ('validEntries', NvU32), + ('bRetirementPending', NvBool), + ('retirementPending', NvU8), +] +NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS +enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', 0) +NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', 1) +NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', 2) + +NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE +enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', 0) +NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', 1) + +NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE +class struct_ACR_REQUEST_PARAMS(Struct): pass +struct_ACR_REQUEST_PARAMS._fields_ = [ + ('clientId', NvU32), + ('reqReadMask', NvU32), + ('reqWriteMask', NvU32), + ('regionSize', NvU32), +] +ACR_REQUEST_PARAMS = struct_ACR_REQUEST_PARAMS +class struct_ACR_REGION_ID_PROP(Struct): pass +struct_ACR_REGION_ID_PROP._fields_ = [ + ('regionId', NvU32), + ('readMask', NvU32), + ('writeMask', NvU32), + ('regionSize', NvU32), + ('clientMask', NvU32), + ('physicalAddress', NvU64), +] +ACR_REGION_ID_PROP = struct_ACR_REGION_ID_PROP +class struct_ACR_STATUS_PARAMS(Struct): pass +struct_ACR_STATUS_PARAMS._fields_ = [ + ('allocStatus', NvU32), + ('regionId', NvU32), + ('physicalAddress', NvU64), +] +ACR_STATUS_PARAMS = struct_ACR_STATUS_PARAMS +class struct_ACR_REGION_HANDLE(Struct): pass +struct_ACR_REGION_HANDLE._fields_ = [ + ('hClient', NvHandle), + ('hParent', NvHandle), + ('hMemory', NvHandle), + ('hClass', NvU32), + ('hDevice', NvHandle), +] +ACR_REGION_HANDLE = struct_ACR_REGION_HANDLE +class struct_ACR_FALCON_LS_STATUS(Struct): pass +struct_ACR_FALCON_LS_STATUS._fields_ = [ + ('falconId', NvU16), + ('bIsInLs', NvBool), +] +ACR_FALCON_LS_STATUS = struct_ACR_FALCON_LS_STATUS +class struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS._fields_ = [ + ('queryType', NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE), + ('errorCode', NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE), + ('acrRegionIdProp', ACR_REGION_ID_PROP), + ('clientReq', ACR_REQUEST_PARAMS), + ('clientReqStatus', ACR_STATUS_PARAMS), + ('handle', ACR_REGION_HANDLE), + ('falconStatus', ACR_FALCON_LS_STATUS), +] +NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS +class struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS._fields_ = [ + ('sourceMask', NvU32), +] +NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS +class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS._fields_ = [ + ('pCompBitCopyObj', NvP64), + ('pSwizzleParams', NvP64), +] +NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS +class struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS._fields_ = [ + ('fbpIndex', NvU8), + ('ltcMask', NvU32), + ('ltcCount', NvU32), + ('ltsMask', NvU32), + ('ltsCount', NvU32), +] +NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS = struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS +class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS._fields_ = [ + ('CBCBaseAddress', NvU32), + ('backingStorePA', NvU64), + ('backingStoreVA', ctypes.POINTER(NvU8)), + ('backingStoreChunkPA', NvU64), + ('backingStoreChunkVA', ctypes.POINTER(NvU8)), + ('backingStoreChunkSize', NvU32), + ('cacheWriteBitMap', ctypes.POINTER(NvU8)), + ('backingStoreChunkOverfetch', NvBool), + ('PageSizeSrc', NvU32), + ('PageSizeDest', NvU32), +] +NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS +class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS._fields_ = [ + ('fcbits', ctypes.POINTER(NvU32)), + ('compbits', ctypes.POINTER(NvU32)), + ('dataPhysicalStart', NvU64), + ('surfaceOffset', NvU64), + ('comptagLine', NvU32), + ('upper64KBCompbitSel', NvBool), +] +NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS +class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS._fields_ = [ + ('fcbits', NvU32), + ('compbits', NvU32), + ('writeFc', NvBool), + ('dataPhysicalStart', NvU64), + ('surfaceOffset', NvU64), + ('comptagLine', NvU32), + ('upper64KBCompbitSel', NvBool), +] +NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS +class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS._fields_ = [ + ('SrcDataPhysicalStart', NvU64), + ('SrcComptagLine', NvU32), + ('page64KB', NvU32), + ('compbitBuffer', ctypes.POINTER(NvU32)), + ('upper64KBCompbitSel', NvBool), +] +NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS +class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS._fields_ = [ + ('DstDataPhysicalStart', NvU64), + ('DstComptagLine', NvU32), + ('page64KB', NvU32), + ('compbitBuffer', ctypes.POINTER(NvU32)), + ('upper64KBCompbitSel', NvBool), +] +NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS +class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS._fields_ = [ + ('bForceBar1', NvBool), +] +NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS +class struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS._fields_ = [ + ('pAmapConfParams', NvP64), + ('pCbcSwizzleParams', NvP64), +] +NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS +enum_CTRL_CMD_FB_CBC_OP = CEnum(ctypes.c_uint32) +CTRL_CMD_FB_CBC_OP_CLEAN = enum_CTRL_CMD_FB_CBC_OP.define('CTRL_CMD_FB_CBC_OP_CLEAN', 0) +CTRL_CMD_FB_CBC_OP_INVALIDATE = enum_CTRL_CMD_FB_CBC_OP.define('CTRL_CMD_FB_CBC_OP_INVALIDATE', 1) + +CTRL_CMD_FB_CBC_OP = enum_CTRL_CMD_FB_CBC_OP +class struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS._fields_ = [ + ('fbCBCOp', CTRL_CMD_FB_CBC_OP), +] +NV2080_CTRL_CMD_FB_CBC_OP_PARAMS = struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS +class struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS._fields_ = [ + ('pCompTags', (NvU32 * 127)), + ('numCompTags', NvU32), +] +NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS = struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS +class struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS._fields_ = [ + ('attr', NvU32), + ('attr2', NvU32), + ('size', NvU32), + ('ctagOffset', NvU32), + ('hwResId', NvU32), + ('retCompTagLineMin', NvU32), + ('retCompTagLineMax', NvU32), +] +NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS = struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS +class struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS._fields_ = [ + ('hwResId', NvU32), +] +NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS = struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS +enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_FB_SET_VPR = enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE.define('NV2080_CTRL_CMD_FB_SET_VPR', 0) + +NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE = enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE +enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE.define('NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', 0) +NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE.define('NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', 1) + +NV2080_CTRL_CMD_FB_VPR_ERROR_CODE = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE +class struct_VPR_REQUEST_PARAMS(Struct): pass +struct_VPR_REQUEST_PARAMS._fields_ = [ + ('startAddr', NvU32), + ('size', NvU32), +] +VPR_REQUEST_PARAMS = struct_VPR_REQUEST_PARAMS +class struct_VPR_STATUS_PARAMS(Struct): pass +struct_VPR_STATUS_PARAMS._fields_ = [ + ('status', NvU32), +] +VPR_STATUS_PARAMS = struct_VPR_STATUS_PARAMS +class struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS._fields_ = [ + ('requestType', NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE), + ('requestParams', VPR_REQUEST_PARAMS), + ('statusParams', VPR_STATUS_PARAMS), +] +NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS +PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS) +class struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS._fields_ = [ + ('offlinedPages', (NvU32 * 64)), + ('pageSize', NvU32), + ('validEntries', NvU32), +] +NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS +class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS._fields_ = [ + ('defaultPageSize', NvU32), + ('comptagsPerCacheLine', NvU32), + ('unpackedComptagLinesPerCacheLine', NvU32), + ('compCacheLineSizePerLTC', NvU32), + ('unpackedCompCacheLineSizePerLTC', NvU32), + ('slicesPerLTC', NvU32), + ('numActiveLTCs', NvU32), + ('familyName', NvU32), + ('chipName', NvU32), + ('bitsPerRAMEntry', NvU32), + ('ramBankWidth', NvU32), + ('bitsPerComptagLine', NvU32), + ('ramEntriesPerCompCacheLine', NvU32), + ('comptagLineSize', NvU32), +] +NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS +class struct_NV2080_CTRL_FB_SET_RRD_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_SET_RRD_PARAMS._fields_ = [ + ('rrd', NvU32), +] +NV2080_CTRL_FB_SET_RRD_PARAMS = struct_NV2080_CTRL_FB_SET_RRD_PARAMS +class struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS._fields_ = [ + ('limit', NvU8), +] +NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS +NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS +NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS +class struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS._fields_ = [ + ('bEnable', NvBool), +] +NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS = struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS +class struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS._fields_ = [ + ('alignType', NvU32), + ('alignAttr', NvU32), + ('alignInputFlags', NvU32), + ('alignHead', NvU32), + ('alignSize', NvU64), + ('alignHeight', NvU32), + ('alignWidth', NvU32), + ('alignPitch', NvU32), + ('alignPad', NvU32), + ('alignMask', NvU32), + ('alignOutputFlags', (NvU32 * 4)), + ('alignBank', (NvU32 * 4)), + ('alignKind', NvU32), + ('alignAdjust', NvU32), + ('alignAttr2', NvU32), +] +NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS = struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS +class struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS._fields_ = [ + ('cbcBaseAddress', NvU32), + ('compCacheLineSize', NvU32), + ('backingStoreStartPA', NvU64), + ('backingStoreAllocPA', NvU64), + ('backingStoreChunkOverfetch', NvU32), +] +NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS +class struct_NV2080_CTRL_FB_REMAP_ENTRY(Struct): pass +struct_NV2080_CTRL_FB_REMAP_ENTRY._fields_ = [ + ('remapRegVal', NvU32), + ('timestamp', NvU32), + ('fbpa', NvU8), + ('sublocation', NvU8), + ('source', NvU8), + ('flags', NvU8), +] +NV2080_CTRL_FB_REMAP_ENTRY = struct_NV2080_CTRL_FB_REMAP_ENTRY +class struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS._fields_ = [ + ('entryCount', NvU32), + ('flags', NvU8), + ('entries', (NV2080_CTRL_FB_REMAP_ENTRY * 512)), +] +NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS = struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS._fields_ = [ + ('data', (NvU8 * 24)), +] +NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS._fields_ = [ + ('swizzId', NvU32), + ('fbpEnMask', NvU64), +] +NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('ltcEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('ltsEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('fbpaEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('fbpaSubpEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('fbpLogicalIndex', NvU32), +] +NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('ropEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('ltcEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('ltsEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('fbpaEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('ropEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('fbpaSubpEnMask', NvU64), +] +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS +class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS._fields_ = [ + ('sysIdx', NvU32), + ('sysl2LtcEnMask', NvU32), +] +NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS +class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS._fields_ = [ + ('sysIdx', NvU32), + ('sysl2LtsEnMask', NvU64), +] +NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('pacEnMask', NvU32), +] +NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('logicalLtcEnMask', NvU64), +] +NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS._fields_ = [ + ('fbpIndex', NvU32), + ('swizzId', NvU32), + ('logicalLtcEnMask', NvU64), +] +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS +class struct_NV2080_CTRL_FB_FS_INFO_QUERY(Struct): pass +class struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams(ctypes.Union): pass +struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams._fields_ = [ + ('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS), + ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS), + ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS), + ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS), + ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS), + ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS), + ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS), + ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS), + ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS), + ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS), + ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS), + ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS), + ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS), + ('sysl2Ltc', NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS), + ('pac', NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS), + ('logicalLtc', NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS), + ('dmLogicalLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS), + ('sysl2Lts', NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS), +] +struct_NV2080_CTRL_FB_FS_INFO_QUERY._fields_ = [ + ('queryType', NvU16), + ('reserved', (NvU8 * 2)), + ('status', NvU32), + ('queryParams', struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams), +] +NV2080_CTRL_FB_FS_INFO_QUERY = struct_NV2080_CTRL_FB_FS_INFO_QUERY +class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS._fields_ = [ + ('numQueries', NvU16), + ('reserved', (NvU8 * 6)), + ('queries', (NV2080_CTRL_FB_FS_INFO_QUERY * 120)), +] +NV2080_CTRL_FB_GET_FS_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS +class struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS._fields_ = [ + ('histogram', (NvU32 * 5)), +] +NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS = struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS +class struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO(Struct): pass +struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO._fields_ = [ + ('pageNumber', NvU64), + ('source', NvU8), +] +NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO +class struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS._fields_ = [ + ('offlined', (NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO * 64)), + ('validEntries', NvU32), + ('baseIndex', NvU32), + ('bMore', NvBool), +] +NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS +class struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO(Struct): pass +struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO._fields_ = [ + ('client', NvU32), + ('flags', NvU32), + ('beginAddr', NvU64), + ('size', NvU64), +] +NV2080_CTRL_CMD_FB_ALLOCATION_INFO = struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO +class struct_NV2080_CTRL_CMD_FB_CLIENT_INFO(Struct): pass +struct_NV2080_CTRL_CMD_FB_CLIENT_INFO._fields_ = [ + ('handle', NvHandle), + ('pid', NvU32), + ('subProcessID', NvU32), + ('subProcessName', (ctypes.c_char * 100)), +] +NV2080_CTRL_CMD_FB_CLIENT_INFO = struct_NV2080_CTRL_CMD_FB_CLIENT_INFO +class struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS._fields_ = [ + ('allocCount', NvU64), + ('pAllocInfo', NvP64), + ('clientCount', NvU64), + ('pClientInfo', NvP64), +] +NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS +class struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS._fields_ = [ + ('bOnline', NvBool), +] +NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS = struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS +class struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS._fields_ = [ + ('numaNodeId', NvS32), + ('numaMemAddr', NvU64), + ('numaMemSize', NvU64), + ('numaOfflineAddressesCount', NvU32), + ('numaOfflineAddresses', (NvU64 * 64)), +] +NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS +class struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS._fields_ = [ + ('maxSubmittedSemaphoreValueOffset', NvU64), + ('monitoredFenceThresholdOffset', NvU64), + ('size', NvU64), + ('caps', NvU32), +] +NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS = struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS +class struct_NV2080_CTRL_CMD_FB_STATS_ENTRY(Struct): pass +struct_NV2080_CTRL_CMD_FB_STATS_ENTRY._fields_ = [ + ('totalSize', NvU64), + ('rsvdSize', NvU64), + ('osSize', NvU64), + ('r1Size', NvU64), + ('r2Size', NvU64), + ('freeSize', NvU64), +] +NV2080_CTRL_CMD_FB_STATS_ENTRY = struct_NV2080_CTRL_CMD_FB_STATS_ENTRY +class struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS(Struct): pass +struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS._fields_ = [ + ('gfid', NvU32), + ('invalidateAll', NvBool), +] +NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS = struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS +class struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO(Struct): pass +struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO._fields_ = [ + ('allocSize', NvU64), + ('numBlocks', NvU32), + ('rsvdSize', NvU64), +] +NV2080_CTRL_CMD_FB_STATS_OWNER_INFO = struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO +class struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS._fields_ = [ + ('version', NvU64), + ('fbSizeInfo', NV2080_CTRL_CMD_FB_STATS_ENTRY), + ('fbBlockInfo', (NV2080_CTRL_CMD_FB_STATS_OWNER_INFO * 200)), +] +NV2080_CTRL_CMD_FB_STATS_GET_PARAMS = struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS +class struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS._fields_ = [ + ('bStaticBar1Enabled', NvBool), + ('staticBar1StartOffset', NvU64), + ('staticBar1Size', NvU64), +] +NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS +class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS._fields_ = [ + ('currentConfiguration', NvU32), +] +NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS +class struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS._fields_ = [ + ('newConfiguration', NvU32), +] +NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS +class struct_NV2080_CTRL_FB_GET_STATUS_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_GET_STATUS_PARAMS._fields_ = [ + ('fbStatus', NvU32), +] +NV2080_CTRL_FB_GET_STATUS_PARAMS = struct_NV2080_CTRL_FB_GET_STATUS_PARAMS +class struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS._fields_ = [ + ('isSupported', NvU32), +] +NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS = struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS +class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS(Struct): pass +struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS._fields_ = [ + ('currentStatus', NvU32), +] +NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS +class struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('base', NvU64), + ('numEntries', NvU32), +] +NV2080_CTRL_CMD_SET_GPFIFO_PARAMS = struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS +class struct_NV2080_CTRL_FIFO_BIND_CHANNEL(Struct): pass +struct_NV2080_CTRL_FIFO_BIND_CHANNEL._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), +] +NV2080_CTRL_FIFO_BIND_CHANNEL = struct_NV2080_CTRL_FIFO_BIND_CHANNEL +class struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS._fields_ = [ + ('bindChannelCount', NvU32), + ('bindChannels', (NV2080_CTRL_FIFO_BIND_CHANNEL * 16)), +] +NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS = struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS +class struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS._fields_ = [ + ('flags', NvU32), +] +NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS = struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS +class struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS._fields_ = [ + ('physChannelCount', NvU32), + ('physChannelCountInUse', NvU32), +] +NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS = struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS +NV2080_CTRL_FIFO_INFO = struct_NVXXXX_CTRL_XXX_INFO +class struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS._fields_ = [ + ('fifoInfoTblSize', NvU32), + ('fifoInfoTbl', (NV2080_CTRL_FIFO_INFO * 256)), + ('engineType', NvU32), +] +NV2080_CTRL_FIFO_GET_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS +class struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS._fields_ = [ + ('hChannel', NvHandle), +] +NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS = struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS +class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS._fields_ = [ + ('bDisable', NvBool), + ('numChannels', NvU32), + ('bOnlyDisableScheduling', NvBool), + ('bRewindGpPut', NvBool), + ('pRunlistPreemptEvent', NvP64), + ('hClientList', (NvHandle * 64)), + ('hChannelList', (NvHandle * 64)), +] +NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS +class struct_NV2080_CTRL_FIFO_MEM_INFO(Struct): pass +struct_NV2080_CTRL_FIFO_MEM_INFO._fields_ = [ + ('aperture', NvU32), + ('base', NvU64), + ('size', NvU64), +] +NV2080_CTRL_FIFO_MEM_INFO = struct_NV2080_CTRL_FIFO_MEM_INFO +class struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO(Struct): pass +struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO._fields_ = [ + ('inst', NV2080_CTRL_FIFO_MEM_INFO), + ('ramfc', NV2080_CTRL_FIFO_MEM_INFO), + ('methodBuf', (NV2080_CTRL_FIFO_MEM_INFO * 2)), + ('methodBufCount', NvU32), +] +NV2080_CTRL_FIFO_CHANNEL_MEM_INFO = struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO +class struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('chMemInfo', NV2080_CTRL_FIFO_CHANNEL_MEM_INFO), +] +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS +class struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS._fields_ = [ + ('aperture', NvU32), + ('attribute', NvU32), +] +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS +class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS(Struct): pass +class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry(Struct): pass +NvS64 = ctypes.c_int64 +struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry._fields_ = [ + ('timestampNs', NvU64), + ('timeRunTotalNs', NvS64), + ('timeRunNs', NvU32), + ('swrlId', NvU32), + ('targetTimeSlice', NvU32), + ('cumulativePreemptionTime', NvU64), + ('counters', (NvU64 * 8)), +] +struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS._fields_ = [ + ('engineId', NvU32), + ('count', NvU32), + ('entry', (struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry * 200)), + ('schedPolicy', NvU32), + ('arrEnabled', NvU32), + ('arrAvgFactor', NvU32), + ('targetTimesliceNs', NvU32), +] +NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS +class struct_NV2080_CTRL_FIFO_DEVICE_ENTRY(Struct): pass +struct_NV2080_CTRL_FIFO_DEVICE_ENTRY._fields_ = [ + ('engineData', (NvU32 * 16)), + ('pbdmaIds', (NvU32 * 2)), + ('pbdmaFaultIds', (NvU32 * 2)), + ('numPbdmas', NvU32), + ('engineName', (ctypes.c_char * 16)), +] +NV2080_CTRL_FIFO_DEVICE_ENTRY = struct_NV2080_CTRL_FIFO_DEVICE_ENTRY +class struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [ + ('baseIndex', NvU32), + ('numEntries', NvU32), + ('bMore', NvBool), + ('entries', (NV2080_CTRL_FIFO_DEVICE_ENTRY * 32)), +] +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS +class struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS._fields_ = [ + ('engineType', NvU32), + ('vChid', NvU32), + ('faultType', NvU32), +] +NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS = struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS +class struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS._fields_ = [ + ('flags', NvU32), + ('schedPolicy', NvU32), +] +NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS = struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS +class struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('hUserdMemory', NvHandle), + ('gpFifoEntries', NvU32), + ('gpFifoOffset', NvU64), + ('userdOffset', NvU64), +] +NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS = struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS +class struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS._fields_ = [ + ('bDisable', NvBool), +] +NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS +class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS._fields_ = [ + ('base', NvU64), + ('size', NvU64), + ('addressSpace', NvU32), + ('cacheAttrib', NvU32), +] +NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS +class struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS._fields_ = [ + ('runlistId', NvU32), + ('bitMask', (NvU32 * 128)), +] +NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS +class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [ + ('numChannels', NvU32), + ('hClientList', (NvHandle * 64)), + ('hChannelList', (NvHandle * 64)), + ('bEnableAfterKeyRotation', NvBool), +] +NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS +class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS._fields_ = [ + ('numChannels', NvU32), + ('hChannelList', (NvHandle * 64)), + ('bEnableAfterKeyRotation', NvBool), +] +NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS +class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS._fields_ = [ + ('engineId', NvU32), + ('schedPolicy', NvU32), + ('arrEnabled', NvU32), + ('targetTimesliceNs', NvU32), + ('arrAvgFactor', NvU32), +] +NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS +class struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS._fields_ = [ + ('engineId', NvU32), + ('schedPolicy', NvU32), + ('enableArr', NvU32), + ('timesliceTargetNs', NvU32), + ('frequencyForARR', NvU32), + ('avgFactorForARR', NvU32), +] +NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS +class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS._fields_ = [ + ('engineId', NvU32), + ('supportedSchedulers', (NvU32 * 3)), + ('bIsArrModeSupported', NvBool), + ('maxTimesliceNs', NvU32), + ('minTimesliceNs', NvU32), + ('maxFrequencyForARR', NvU32), + ('minFrequencyForARR', NvU32), + ('maxAvgFactorForARR', NvU32), + ('minAvgFactorForARR', NvU32), +] +NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS +class struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hChannelOrTsg', NvHandle), + ('tsgId', NvU32), + ('numChannels', NvU32), + ('channelUniqueID', (NvU32 * 128)), + ('vasUniqueID', (NvU32 * 128)), + ('veid', (NvU32 * 128)), +] +NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS +class struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS(Struct): pass +struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS._fields_ = [ + ('hClients', (NvHandle * 128)), + ('hChannels', (NvHandle * 128)), + ('numChannels', NvU32), + ('channelUniqueIDs', (NvU32 * 128)), +] +NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS = struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS +class struct_NV2080_CTRL_FLA_RANGE_PARAMS(Struct): pass +struct_NV2080_CTRL_FLA_RANGE_PARAMS._fields_ = [ + ('base', NvU64), + ('size', NvU64), + ('mode', NvU32), + ('hVASpace', NvHandle), +] +NV2080_CTRL_FLA_RANGE_PARAMS = struct_NV2080_CTRL_FLA_RANGE_PARAMS +enum_NV2080_CTRL_FLA_ADDRSPACE = CEnum(ctypes.c_uint32) +NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = enum_NV2080_CTRL_FLA_ADDRSPACE.define('NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', 0) +NV2080_CTRL_FLA_ADDRSPACE_FBMEM = enum_NV2080_CTRL_FLA_ADDRSPACE.define('NV2080_CTRL_FLA_ADDRSPACE_FBMEM', 1) + +NV2080_CTRL_FLA_ADDRSPACE = enum_NV2080_CTRL_FLA_ADDRSPACE +enum_NV2080_CTRL_FLA_ACTION = CEnum(ctypes.c_uint32) +NV2080_CTRL_FLA_ACTION_BIND = enum_NV2080_CTRL_FLA_ACTION.define('NV2080_CTRL_FLA_ACTION_BIND', 0) +NV2080_CTRL_FLA_ACTION_UNBIND = enum_NV2080_CTRL_FLA_ACTION.define('NV2080_CTRL_FLA_ACTION_UNBIND', 1) + +NV2080_CTRL_FLA_ACTION = enum_NV2080_CTRL_FLA_ACTION +class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS(Struct): pass +struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS._fields_ = [ + ('imbPhysAddr', NvU64), + ('addrSpace', NV2080_CTRL_FLA_ADDRSPACE), + ('flaAction', NV2080_CTRL_FLA_ACTION), +] +NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS +class struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS(Struct): pass +struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS._fields_ = [ + ('base', NvU64), + ('size', NvU64), +] +NV2080_CTRL_FLA_GET_RANGE_PARAMS = struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS +class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS(Struct): pass +struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS._fields_ = [ + ('totalSize', NvU64), + ('freeSize', NvU64), +] +NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS +class struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS(Struct): pass +struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS._fields_ = [ + ('flcnID', NvU32), + ('heapSize', NvU32), + ('heapFree', NvU32), +] +NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS = struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS +class struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS(Struct): pass +struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS._fields_ = [ + ('engine', NvU32), + ('engineArch', NvU32), +] +NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS = struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS +class struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER(Struct): pass +struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER._fields_ = [ + ('mask', (NvU8 * 36)), +] +NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER = struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER +class struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS._fields_ = [ + ('engine', NvU32), + ('pageSize', NvU32), + ('offset', NvUPtr), + ('size', NvU32), + ('queueFeatureId', NvU8), +] +NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS +class struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS(Struct): pass +struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS._fields_ = [ + ('engine', NvU32), + ('eventFilter', NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER), + ('queueId', NvU8), +] +NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS +NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS +NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS +class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [ + ('hUserClient', NvHandle), + ('hChannel', NvHandle), + ('alignment', NvU64), + ('size', NvU64), + ('bufferHandle', NvP64), + ('pageCount', NvU64), + ('physAddr', NvU64), + ('aperture', NvU32), + ('kind', NvU32), + ('pageSize', NvU32), + ('bIsContigous', NvBool), + ('bDeviceDescendant', NvBool), + ('uuid', (NvU8 * 16)), +] +NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS +class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('totalBufferSize', NvU64), +] +NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS +class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS._fields_ = [ + ('gpioPin', NvU32), + ('bInput', NvBool), +] +NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS +class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS._fields_ = [ + ('gpioPin', NvU32), + ('value', NvU32), +] +NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS +class struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS._fields_ = [ + ('gpioPin', NvU32), + ('value', NvU32), +] +NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS +class struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS._fields_ = [ + ('function', NvU32), + ('pin', NvU32), +] +NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS NV2080_CTRL_GPU_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_GPU_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_INFO_PARAMS._fields_ = [ - ('gpuInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('gpuInfoList', ctypes.POINTER(None)), + ('gpuInfoListSize', NvU32), + ('gpuInfoList', NvP64), ] - NV2080_CTRL_GPU_GET_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS._fields_ = [ - ('gpuInfoListSize', ctypes.c_uint32), - ('gpuInfoList', struct_NVXXXX_CTRL_XXX_INFO * 65), + ('gpuInfoListSize', NvU32), + ('gpuInfoList', (NV2080_CTRL_GPU_INFO * 65)), ] - NV2080_CTRL_GPU_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS(Structure): - pass - -class union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString(Union): - pass - -union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString._pack_ = 1 # source:False -union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString._fields_ = [ - ('ascii', ctypes.c_ubyte * 64), - ('unicode', ctypes.c_uint16 * 64), +class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS(Struct): pass +class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString(ctypes.Union): pass +struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString._fields_ = [ + ('ascii', (NvU8 * 64)), + ('unicode', (NvU16 * 64)), ] - -struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS._fields_ = [ - ('gpuNameStringFlags', ctypes.c_uint32), - ('gpuNameString', union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString), + ('gpuNameStringFlags', NvU32), + ('gpuNameString', struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString), ] - NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS = struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS -class struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS._fields_ = [ - ('gpuShortNameString', ctypes.c_ubyte * 64), + ('gpuShortNameString', (NvU8 * 64)), ] - NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS = struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS -class struct_NV2080_CTRL_GPU_SET_POWER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_POWER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_POWER_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_POWER_PARAMS._fields_ = [ - ('target', ctypes.c_uint32), - ('newLevel', ctypes.c_uint32), - ('oldLevel', ctypes.c_uint32), + ('target', NvU32), + ('newLevel', NvU32), + ('oldLevel', NvU32), ] - NV2080_CTRL_GPU_SET_POWER_PARAMS = struct_NV2080_CTRL_GPU_SET_POWER_PARAMS -class struct_NV2080_CTRL_GPU_GET_SDM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_SDM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_SDM_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_SDM_PARAMS._fields_ = [ - ('subdeviceMask', ctypes.c_uint32), + ('subdeviceMask', NvU32), ] - NV2080_CTRL_GPU_GET_SDM_PARAMS = struct_NV2080_CTRL_GPU_GET_SDM_PARAMS -class struct_NV2080_CTRL_GPU_SET_SDM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_SDM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_SDM_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_SDM_PARAMS._fields_ = [ - ('subdeviceMask', ctypes.c_uint32), + ('subdeviceMask', NvU32), ] - NV2080_CTRL_GPU_SET_SDM_PARAMS = struct_NV2080_CTRL_GPU_SET_SDM_PARAMS -class struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS._fields_ = [ - ('type', ctypes.c_uint32), + ('type', NvU32), ] - NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_REG_OP(Structure): - pass - -struct_NV2080_CTRL_GPU_REG_OP._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_REG_OP(Struct): pass struct_NV2080_CTRL_GPU_REG_OP._fields_ = [ - ('regOp', ctypes.c_ubyte), - ('regType', ctypes.c_ubyte), - ('regStatus', ctypes.c_ubyte), - ('regQuad', ctypes.c_ubyte), - ('regGroupMask', ctypes.c_uint32), - ('regSubGroupMask', ctypes.c_uint32), - ('regOffset', ctypes.c_uint32), - ('regValueHi', ctypes.c_uint32), - ('regValueLo', ctypes.c_uint32), - ('regAndNMaskHi', ctypes.c_uint32), - ('regAndNMaskLo', ctypes.c_uint32), + ('regOp', NvU8), + ('regType', NvU8), + ('regStatus', NvU8), + ('regQuad', NvU8), + ('regGroupMask', NvU32), + ('regSubGroupMask', NvU32), + ('regOffset', NvU32), + ('regValueHi', NvU32), + ('regValueLo', NvU32), + ('regAndNMaskHi', NvU32), + ('regAndNMaskLo', NvU32), ] - NV2080_CTRL_GPU_REG_OP = struct_NV2080_CTRL_GPU_REG_OP -class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS(Struct): pass +NV2080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('reserved00', ctypes.c_uint32 * 2), - ('regOpCount', ctypes.c_uint32), - ('regOps', ctypes.POINTER(None)), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('hClientTarget', NvHandle), + ('hChannelTarget', NvHandle), + ('bNonTransactional', NvU32), + ('reserved00', (NvU32 * 2)), + ('regOpCount', NvU32), + ('regOps', NvP64), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), ] - NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('engineList', ctypes.POINTER(None)), + ('engineCount', NvU32), + ('engineList', NvP64), ] - NV2080_CTRL_GPU_GET_ENGINES_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('engineList', ctypes.c_uint32 * 84), + ('engineCount', NvU32), + ('engineList', (NvU32 * 84)), ] - NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('numClasses', ctypes.c_uint32), - ('classList', ctypes.POINTER(None)), + ('engineType', NvU32), + ('numClasses', NvU32), + ('classList', NvP64), ] - NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('mmuFaultId', ctypes.c_uint32), - ('bSubcontextSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('engineType', NvU32), + ('mmuFaultId', NvU32), + ('bSubcontextSupported', NvBool), ] - NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), + ('mode', NvU32), ] - NV2080_CTRL_GPU_QUERY_MODE_PARAMS = struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS -class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(Structure): - pass - -struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(Struct): pass struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY._fields_ = [ - ('gpuPhysAddr', ctypes.c_uint64), - ('gpuVirtAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('physAttr', ctypes.c_uint32), - ('bufferId', ctypes.c_uint16), - ('bInitialize', ctypes.c_ubyte), - ('bNonmapped', ctypes.c_ubyte), + ('gpuPhysAddr', NvU64), + ('gpuVirtAddr', NvU64), + ('size', NvU64), + ('physAttr', NvU32), + ('bufferId', NvU16), + ('bInitialize', NvU8), + ('bNonmapped', NvU8), ] - NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY = struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY -class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hVirtMemory', ctypes.c_uint32), - ('virtAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('entryCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('promoteEntry', struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY * 16), + ('engineType', NvU32), + ('hClient', NvHandle), + ('ChID', NvU32), + ('hChanClient', NvHandle), + ('hObject', NvHandle), + ('hVirtMemory', NvHandle), + ('virtAddress', NvU64), + ('size', NvU64), + ('entryCount', NvU32), + ('promoteEntry', (NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY * 16)), ] - NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS = struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS) -class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), + ('engineType', NvU32), + ('hClient', NvHandle), + ('ChID', NvU32), + ('hChanClient', NvHandle), + ('hObject', NvHandle), ] - NV2080_CTRL_GPU_EVICT_CTX_PARAMS = struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS PNV2080_CTRL_GPU_EVICT_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS) -class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('hClient', ctypes.c_uint32), - ('ChID', ctypes.c_uint32), - ('hChanClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('hVirtMemory', ctypes.c_uint32), - ('physAddress', ctypes.c_uint64), - ('physAttr', ctypes.c_uint32), - ('hDmaHandle', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), + ('engineType', NvU32), + ('hClient', NvHandle), + ('ChID', NvU32), + ('hChanClient', NvHandle), + ('hObject', NvHandle), + ('hVirtMemory', NvHandle), + ('physAddress', NvU64), + ('physAttr', NvU32), + ('hDmaHandle', NvHandle), + ('index', NvU32), + ('size', NvU64), ] - NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS = struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS) -class struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS._fields_ = [ - ('eccIntrStatus', ctypes.c_uint32), + ('eccIntrStatus', NvU32), ] - NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS._fields_ = [ - ('count', ctypes.c_uint64), + ('count', NvU64), ] - NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS = struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS -class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS._fields_ = [ - ('enabled', ctypes.c_ubyte), - ('scrubComplete', ctypes.c_ubyte), - ('supported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 5), - ('dbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), - ('dbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), - ('sbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), - ('sbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), + ('enabled', NvBool), + ('scrubComplete', NvBool), + ('supported', NvBool), + ('dbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), + ('dbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), + ('sbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), + ('sbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS), ] - NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS = struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS -class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS._fields_ = [ - ('units', struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS * 36), - ('bFatalPoisonError', ctypes.c_ubyte), - ('uncorrectableError', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('flags', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('units', (NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS * 36)), + ('bFatalPoisonError', NvBool), + ('uncorrectableError', NvU8), + ('flags', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), ] - NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS._fields_ = [ - ('rules', ctypes.c_uint32), - ('flags', ctypes.c_uint32), + ('rules', NvU32), + ('flags', NvU32), ] - NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS = struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS._fields_ = [ - ('rules', ctypes.c_uint32), + ('rules', NvU32), ] - NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS = struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS._fields_ = [ - ('currentConfiguration', ctypes.c_uint32), - ('defaultConfiguration', ctypes.c_uint32), + ('currentConfiguration', NvU32), + ('defaultConfiguration', NvU32), ] - NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS._fields_ = [ - ('newConfiguration', ctypes.c_uint32), + ('newConfiguration', NvU32), ] - NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS = struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS._fields_ = [ - ('statuses', ctypes.c_uint32), - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('statuses', NvU32), + ('flags', NvU8), ] - NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS = struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS._fields_ = [ - ('gpcMask', ctypes.c_uint32), + ('gpcMask', NvU32), ] - NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), + ('gpcId', NvU32), + ('tpcMask', NvU32), ] - NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('zcullMask', ctypes.c_uint32), + ('gpcId', NvU32), + ('zcullMask', NvU32), ] - NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS._fields_ = [ - ('buildDate', ctypes.c_uint32), - ('marketingName', ctypes.c_ubyte * 24), - ('serialNumber', ctypes.c_ubyte * 16), - ('memoryManufacturer', ctypes.c_ubyte), - ('memoryPartID', ctypes.c_ubyte * 20), - ('memoryDateCode', ctypes.c_ubyte * 6), - ('productPartNumber', ctypes.c_ubyte * 20), - ('boardRevision', ctypes.c_ubyte * 3), - ('boardType', ctypes.c_ubyte), - ('board699PartNumber', ctypes.c_ubyte * 20), - ('board965PartNumber', ctypes.c_ubyte * 20), - ('PADDING_0', ctypes.c_ubyte), + ('buildDate', NvU32), + ('marketingName', (NvU8 * 24)), + ('serialNumber', (NvU8 * 16)), + ('memoryManufacturer', NvU8), + ('memoryPartID', (NvU8 * 20)), + ('memoryDateCode', (NvU8 * 6)), + ('productPartNumber', (NvU8 * 20)), + ('boardRevision', (NvU8 * 3)), + ('boardType', NvU8), + ('board699PartNumber', (NvU8 * 20)), + ('board965PartNumber', (NvU8 * 20)), ] - NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ID_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ID_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), + ('gpuId', NvU32), ] - NV2080_CTRL_GPU_GET_ID_PARAMS = struct_NV2080_CTRL_GPU_GET_ID_PARAMS -class struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), + ('mode', NvU32), ] - NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS -class struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS._fields_ = [ - ('currentMode', ctypes.c_uint32), + ('currentMode', NvU32), ] - NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS = struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('partnershipClassId', ctypes.c_uint32), - ('runqueue', ctypes.c_uint32), - ('numPartners', ctypes.c_uint32), - ('partnerList', ctypes.c_uint32 * 32), + ('engineType', NvU32), + ('partnershipClassId', NvU32), + ('runqueue', NvU32), + ('numPartners', NvU32), + ('partnerList', (NvU32 * 32)), ] - NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS -class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._fields_ = [ - ('index', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 256), + ('index', NvU32), + ('flags', NvU32), + ('length', NvU32), + ('data', (NvU8 * 256)), ] - NV2080_CTRL_GPU_GET_GID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS._fields_ = [ - ('objectType', ctypes.c_char * 3), - ('version', ctypes.c_ubyte), - ('subversion', ctypes.c_ubyte), + ('objectType', (ctypes.c_char * 3)), + ('version', NvU8), + ('subversion', NvU8), ] - NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS._fields_ = [ - ('isOptimusEnabled', ctypes.c_ubyte), + ('isOptimusEnabled', NvBool), ] - NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS = struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS._fields_ = [ - ('targetEngine', ctypes.c_uint32), - ('ipVersion', ctypes.c_uint32), + ('targetEngine', NvU32), + ('ipVersion', NvU32), ] - NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS -class struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS._fields_ = [ - ('attribute', ctypes.c_uint32), - ('bSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('attribute', NvU32), + ('bSupported', NvBool), ] - NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS = struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS -class struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS._fields_ = [ - ('attribute', ctypes.c_uint32), - ('value', ctypes.c_uint32), + ('attribute', NvU32), + ('value', NvU32), ] - NV2080_CTRL_CMD_GPU_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS -class struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS._fields_ = [ - ('version', ctypes.c_ubyte * 16), + ('version', (NvU8 * 16)), ] - NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS._fields_ = [ - ('fwVersion', ctypes.c_uint32), - ('oemVersion', ctypes.c_ubyte), - ('siliconRevision', ctypes.c_ubyte), - ('hwbcResourceType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), + ('fwVersion', NvU32), + ('oemVersion', NvU8), + ('siliconRevision', NvU8), + ('hwbcResourceType', NvU8), ] - NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS._fields_ = [ - ('bridgeCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('hPhysicalBridges', ctypes.c_uint32 * 100), - ('bridgeList', struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS * 100), + ('bridgeCount', NvU8), + ('hPhysicalBridges', (NvHandle * 100)), + ('bridgeList', (NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS * 100)), ] - NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS._fields_ = [ - ('bus', ctypes.c_ubyte), - ('device', ctypes.c_ubyte), - ('func', ctypes.c_ubyte), - ('oemVersion', ctypes.c_ubyte), - ('siliconRevision', ctypes.c_ubyte), - ('hwbcResourceType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('domain', ctypes.c_uint32), - ('fwVersion', ctypes.c_uint32), + ('bus', NvU8), + ('device', NvU8), + ('func', NvU8), + ('oemVersion', NvU8), + ('siliconRevision', NvU8), + ('hwbcResourceType', NvU8), + ('domain', NvU32), + ('fwVersion', NvU32), ] - NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS -class struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS._fields_ = [ - ('bridgeCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('physicalBridgeIds', ctypes.c_uint32 * 100), - ('bridgeList', struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS * 100), + ('bridgeCount', NvU8), + ('physicalBridgeIds', (NvU32 * 100)), + ('bridgeList', (NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS * 100)), ] - NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS = struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS -class struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS._fields_ = [ - ('scrubberStatus', ctypes.c_uint32), - ('remainingTimeMs', ctypes.c_uint32), - ('scrubStartAddr', ctypes.c_uint64), - ('scrubEndAddr', ctypes.c_uint64), + ('scrubberStatus', NvU32), + ('remainingTimeMs', NvU32), + ('scrubStartAddr', NvU64), + ('scrubEndAddr', NvU64), ] - NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS = struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS._fields_ = [ - ('minStartAddr', ctypes.c_uint64), - ('maxEndAddr', ctypes.c_uint64), + ('minStartAddr', NvU64), + ('maxEndAddr', NvU64), ] - NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS = struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS -class struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('numPesInGpc', ctypes.c_uint32), - ('activePesMask', ctypes.c_uint32), - ('maxTpcPerGpcCount', ctypes.c_uint32), - ('tpcToPesMap', ctypes.c_uint32 * 10), + ('gpcId', NvU32), + ('numPesInGpc', NvU32), + ('activePesMask', NvU32), + ('maxTpcPerGpcCount', NvU32), + ('tpcToPesMap', (NvU32 * 10)), ] - NV2080_CTRL_GPU_GET_PES_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS._fields_ = [ - ('oemInfo', ctypes.c_ubyte * 504), + ('oemInfo', (NvU8 * 504)), ] - NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS +enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', 0) +NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', 1) -# values for enumeration 'NV2080_CTRL_VPR_INFO_QUERY_TYPE' -NV2080_CTRL_VPR_INFO_QUERY_TYPE__enumvalues = { - 0: 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', - 1: 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', -} -NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = 0 -NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = 1 -NV2080_CTRL_VPR_INFO_QUERY_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS._pack_ = 1 # source:False +NV2080_CTRL_VPR_INFO_QUERY_TYPE = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE +class struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS._fields_ = [ - ('queryType', NV2080_CTRL_VPR_INFO_QUERY_TYPE), - ('bIsVprEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('vprStartAddressInBytes', ctypes.c_uint64), - ('vprEndAddressInBytes', ctypes.c_uint64), + ('queryType', NV2080_CTRL_VPR_INFO_QUERY_TYPE), + ('bIsVprEnabled', NvBool), + ('vprStartAddressInBytes', NvU64), + ('vprEndAddressInBytes', NvU64), ] - NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS +enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', 0) +NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', 1) +NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', 2) -# values for enumeration 'NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE' -NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE__enumvalues = { - 0: 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', - 1: 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', - 2: 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', -} -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0 -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1 -NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2 -NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS._pack_ = 1 # source:False +NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE +class struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS._fields_ = [ - ('queryType', NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE), - ('encoderCapacity', ctypes.c_uint32), + ('queryType', NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE), + ('encoderCapacity', NvU32), ] - NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS -class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS._fields_ = [ - ('encoderSessionCount', ctypes.c_uint32), - ('averageEncodeFps', ctypes.c_uint32), - ('averageEncodeLatency', ctypes.c_uint32), + ('encoderSessionCount', NvU32), + ('averageEncodeFps', NvU32), + ('averageEncodeLatency', NvU32), ] - NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS -class struct_NV2080_CTRL_NVENC_SW_SESSION_INFO(Structure): - pass - -struct_NV2080_CTRL_NVENC_SW_SESSION_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVENC_SW_SESSION_INFO(Struct): pass struct_NV2080_CTRL_NVENC_SW_SESSION_INFO._fields_ = [ - ('processId', ctypes.c_uint32), - ('subProcessId', ctypes.c_uint32), - ('sessionId', ctypes.c_uint32), - ('codecType', ctypes.c_uint32), - ('hResolution', ctypes.c_uint32), - ('vResolution', ctypes.c_uint32), - ('averageEncodeFps', ctypes.c_uint32), - ('averageEncodeLatency', ctypes.c_uint32), + ('processId', NvU32), + ('subProcessId', NvU32), + ('sessionId', NvU32), + ('codecType', NvU32), + ('hResolution', NvU32), + ('vResolution', NvU32), + ('averageEncodeFps', NvU32), + ('averageEncodeLatency', NvU32), ] - NV2080_CTRL_NVENC_SW_SESSION_INFO = struct_NV2080_CTRL_NVENC_SW_SESSION_INFO -class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS._fields_ = [ - ('sessionInfoTblEntry', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sessionInfoTbl', ctypes.POINTER(None)), + ('sessionInfoTblEntry', NvU32), + ('sessionInfoTbl', NvP64), ] - NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS._fields_ = [ - ('fabricBaseAddr', ctypes.c_uint64), + ('fabricBaseAddr', NvU64), ] - NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS -class struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS._fields_ = [ - ('handle', ctypes.c_uint32), + ('handle', NvU32), ] - NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS = struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS -class struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS._fields_ = [ - ('statusMask', ctypes.c_uint32), - ('xusbData', ctypes.c_uint32), - ('ppcData', ctypes.c_uint32), + ('statusMask', NvU32), + ('xusbData', NvU32), + ('ppcData', NvU32), ] - NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS = struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_PARTITION_SPAN(Structure): - pass - -struct_NV2080_CTRL_GPU_PARTITION_SPAN._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_PARTITION_SPAN(Struct): pass struct_NV2080_CTRL_GPU_PARTITION_SPAN._fields_ = [ - ('lo', ctypes.c_uint64), - ('hi', ctypes.c_uint64), + ('lo', NvU64), + ('hi', NvU64), ] - NV2080_CTRL_GPU_PARTITION_SPAN = struct_NV2080_CTRL_GPU_PARTITION_SPAN -class struct_NV2080_CTRL_EXEC_PARTITION_SPAN(Structure): - pass - -struct_NV2080_CTRL_EXEC_PARTITION_SPAN._pack_ = 1 # source:False +class struct_NV2080_CTRL_EXEC_PARTITION_SPAN(Struct): pass struct_NV2080_CTRL_EXEC_PARTITION_SPAN._fields_ = [ - ('lo', ctypes.c_uint64), - ('hi', ctypes.c_uint64), + ('lo', NvU64), + ('hi', NvU64), ] - NV2080_CTRL_EXEC_PARTITION_SPAN = struct_NV2080_CTRL_EXEC_PARTITION_SPAN -class struct_NV2080_CTRL_GPU_SET_PARTITION_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_PARTITION_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_PARTITION_INFO(Struct): pass struct_NV2080_CTRL_GPU_SET_PARTITION_INFO._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('uuid', ctypes.c_ubyte * 16), - ('partitionFlag', ctypes.c_uint32), - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('placement', NV2080_CTRL_GPU_PARTITION_SPAN), + ('swizzId', NvU32), + ('uuid', (NvU8 * 16)), + ('partitionFlag', NvU32), + ('bValid', NvBool), + ('placement', NV2080_CTRL_GPU_PARTITION_SPAN), ] - NV2080_CTRL_GPU_SET_PARTITION_INFO = struct_NV2080_CTRL_GPU_SET_PARTITION_INFO -class struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS._fields_ = [ - ('partitionCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('partitionInfo', struct_NV2080_CTRL_GPU_SET_PARTITION_INFO * 8), + ('partitionCount', NvU32), + ('partitionInfo', (NV2080_CTRL_GPU_SET_PARTITION_INFO * 8)), ] - NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS -class struct_NV2080_CTRL_GPU_GET_PARTITION_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PARTITION_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PARTITION_INFO(Struct): pass struct_NV2080_CTRL_GPU_GET_PARTITION_INFO._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('partitionFlag', ctypes.c_uint32), - ('grEngCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('nvOfaCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('gpcsPerGr', ctypes.c_uint32 * 8), - ('virtualGpcsPerGr', ctypes.c_uint32 * 8), - ('gfxGpcPerGr', ctypes.c_uint32 * 8), - ('veidsPerGr', ctypes.c_uint32 * 8), - ('PADDING_0', ctypes.c_ubyte * 4), - ('memSize', ctypes.c_uint64), - ('span', NV2080_CTRL_GPU_PARTITION_SPAN), - ('bValid', ctypes.c_ubyte), - ('bPartitionError', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 6), - ('validCTSIdMask', ctypes.c_uint64), - ('validGfxCTSIdMask', ctypes.c_uint64), + ('swizzId', NvU32), + ('partitionFlag', NvU32), + ('grEngCount', NvU32), + ('veidCount', NvU32), + ('smCount', NvU32), + ('ceCount', NvU32), + ('nvEncCount', NvU32), + ('nvDecCount', NvU32), + ('nvJpgCount', NvU32), + ('nvOfaCount', NvU32), + ('gpcCount', NvU32), + ('virtualGpcCount', NvU32), + ('gfxGpcCount', NvU32), + ('gpcsPerGr', (NvU32 * 8)), + ('virtualGpcsPerGr', (NvU32 * 8)), + ('gfxGpcPerGr', (NvU32 * 8)), + ('veidsPerGr', (NvU32 * 8)), + ('memSize', NvU64), + ('span', NV2080_CTRL_GPU_PARTITION_SPAN), + ('bValid', NvBool), + ('bPartitionError', NvBool), + ('validCTSIdMask', NvU64), + ('validGfxCTSIdMask', NvU64), ] - NV2080_CTRL_GPU_GET_PARTITION_INFO = struct_NV2080_CTRL_GPU_GET_PARTITION_INFO -class struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS._fields_ = [ - ('queryPartitionInfo', struct_NV2080_CTRL_GPU_GET_PARTITION_INFO * 8), - ('validPartitionCount', ctypes.c_uint32), - ('bGetAllPartitionInfo', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('queryPartitionInfo', (NV2080_CTRL_GPU_GET_PARTITION_INFO * 8)), + ('validPartitionCount', NvU32), + ('bGetAllPartitionInfo', NvBool), ] - NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS -class struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('gpcCountPerSmcEng', ctypes.c_uint32 * 8), - ('updateSmcEngMask', ctypes.c_uint32), - ('bUseAllGPCs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('swizzId', NvU32), + ('gpcCountPerSmcEng', (NvU32 * 8)), + ('updateSmcEngMask', NvU32), + ('bUseAllGPCs', NvBool), ] - NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS -class struct_NV2080_CTRL_GPU_FAULT_PACKET(Structure): - pass - -struct_NV2080_CTRL_GPU_FAULT_PACKET._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_FAULT_PACKET(Struct): pass struct_NV2080_CTRL_GPU_FAULT_PACKET._fields_ = [ - ('data', ctypes.c_ubyte * 32), + ('data', (NvU8 * 32)), ] - NV2080_CTRL_GPU_FAULT_PACKET = struct_NV2080_CTRL_GPU_FAULT_PACKET -class struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('faultPacket', NV2080_CTRL_GPU_FAULT_PACKET), - ] - +class struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS(Struct): pass +struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS._fields_ = [ + ('faultPacket', NV2080_CTRL_GPU_FAULT_PACKET), +] NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS = struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS._fields_ = [ - ('engineList', ctypes.c_uint32 * 84), - ('runlistPriBase', ctypes.c_uint32 * 84), - ('runlistId', ctypes.c_uint32 * 84), + ('engineList', (NvU32 * 84)), + ('runlistPriBase', (NvU32 * 84)), + ('runlistId', (NvU32 * 84)), ] - NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS -class struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS._fields_ = [ - ('engineList', ctypes.c_uint32 * 84), - ('hwEngineID', ctypes.c_uint32 * 84), + ('engineList', (NvU32 * 84)), + ('hwEngineID', (NvU32 * 84)), ] - NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS = struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS -class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS._fields_ = [ - ('sessionCount', ctypes.c_uint32), - ('averageFPS', ctypes.c_uint32), - ('averageLatency', ctypes.c_uint32), + ('sessionCount', NvU32), + ('averageFPS', NvU32), + ('averageLatency', NvU32), ] - NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS -class struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO(Structure): - pass - -struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO(Struct): pass struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO._fields_ = [ - ('processId', ctypes.c_uint32), - ('subProcessId', ctypes.c_uint32), - ('vgpuInstanceId', ctypes.c_uint32), - ('sessionId', ctypes.c_uint32), - ('sessionType', ctypes.c_uint32), - ('displayOrdinal', ctypes.c_uint32), - ('sessionFlags', ctypes.c_uint32), - ('hMaxResolution', ctypes.c_uint32), - ('vMaxResolution', ctypes.c_uint32), - ('hResolution', ctypes.c_uint32), - ('vResolution', ctypes.c_uint32), - ('averageFPS', ctypes.c_uint32), - ('averageLatency', ctypes.c_uint32), + ('processId', NvU32), + ('subProcessId', NvU32), + ('vgpuInstanceId', NvU32), + ('sessionId', NvU32), + ('sessionType', NvU32), + ('displayOrdinal', NvU32), + ('sessionFlags', NvU32), + ('hMaxResolution', NvU32), + ('vMaxResolution', NvU32), + ('hResolution', NvU32), + ('vResolution', NvU32), + ('averageFPS', NvU32), + ('averageLatency', NvU32), ] - NV2080_CTRL_NVFBC_SW_SESSION_INFO = struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO -class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS._fields_ = [ - ('sessionInfoCount', ctypes.c_uint32), - ('sessionInfoTbl', struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO * 256), + ('sessionInfoCount', NvU32), + ('sessionInfoTbl', (NV2080_CTRL_NVFBC_SW_SESSION_INFO * 256)), ] - NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS._fields_ = [ - ('firstAsyncCEIdx', ctypes.c_uint32), + ('firstAsyncCEIdx', NvU32), ] - NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS = struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS -class struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS._fields_ = [ - ('vmmuSegmentSize', ctypes.c_uint64), + ('vmmuSegmentSize', NvU64), ] - NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS = struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS -class struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('partitionCount', ctypes.c_uint32), - ('availableSpans', struct_NV2080_CTRL_GPU_PARTITION_SPAN * 8), - ('availableSpansCount', ctypes.c_uint32), - ('totalPartitionCount', ctypes.c_uint32), - ('totalSpans', struct_NV2080_CTRL_GPU_PARTITION_SPAN * 8), - ('totalSpansCount', ctypes.c_uint32), - ('bStaticInfo', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('partitionFlag', NvU32), + ('partitionCount', NvU32), + ('availableSpans', (NV2080_CTRL_GPU_PARTITION_SPAN * 8)), + ('availableSpansCount', NvU32), + ('totalPartitionCount', NvU32), + ('totalSpans', (NV2080_CTRL_GPU_PARTITION_SPAN * 8)), + ('totalSpansCount', NvU32), + ('bStaticInfo', NvBool), ] - NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS._fields_ = [ - ('partitioningMode', ctypes.c_uint32), + ('partitioningMode', NvU32), ] - NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS -class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO(Struct): pass struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('grCount', ctypes.c_uint32), - ('gfxGrCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('nvOfaCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('memorySize', ctypes.c_uint64), + ('partitionFlag', NvU32), + ('grCount', NvU32), + ('gfxGrCount', NvU32), + ('gpcCount', NvU32), + ('virtualGpcCount', NvU32), + ('gfxGpcCount', NvU32), + ('veidCount', NvU32), + ('smCount', NvU32), + ('ceCount', NvU32), + ('nvEncCount', NvU32), + ('nvDecCount', NvU32), + ('nvJpgCount', NvU32), + ('nvOfaCount', NvU32), + ('memorySize', NvU64), ] - NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO -class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS._fields_ = [ - ('descCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('partitionDescs', struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO * 40), + ('descCount', NvU32), + ('partitionDescs', (NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO * 40)), ] - NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS -class struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS._fields_ = [ - ('maxSupportedPageSize', ctypes.c_uint64), + ('maxSupportedPageSize', NvU64), ] - NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS = struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS -class struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('gpcId', NvU32), + ('count', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), ] - NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS = struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS -class struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32 * 9), - ('partitionCount', ctypes.c_uint32), + ('swizzId', (NvU32 * 9)), + ('partitionCount', NvU32), ] - NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS = struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS -class struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS._fields_ = [ - ('idType', ctypes.c_uint32), - ('id', ctypes.c_uint32), - ('pidTblCount', ctypes.c_uint32), - ('pidTbl', ctypes.c_uint32 * 950), + ('idType', NvU32), + ('id', NvU32), + ('pidTblCount', NvU32), + ('pidTbl', (NvU32 * 950)), ] - NV2080_CTRL_GPU_GET_PIDS_PARAMS = struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS -class struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO(Structure): - pass - -struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO(Struct): pass struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO._fields_ = [ - ('computeInstanceId', ctypes.c_uint32), - ('gpuInstanceId', ctypes.c_uint32), + ('computeInstanceId', NvU32), + ('gpuInstanceId', NvU32), ] - NV2080_CTRL_SMC_SUBSCRIPTION_INFO = struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO -class struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA(Structure): - pass - -struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA(Struct): pass struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA._fields_ = [ - ('memPrivate', ctypes.c_uint64), - ('memSharedOwned', ctypes.c_uint64), - ('memSharedDuped', ctypes.c_uint64), - ('protectedMemPrivate', ctypes.c_uint64), - ('protectedMemSharedOwned', ctypes.c_uint64), - ('protectedMemSharedDuped', ctypes.c_uint64), + ('memPrivate', NvU64), + ('memSharedOwned', NvU64), + ('memSharedDuped', NvU64), + ('protectedMemPrivate', NvU64), + ('protectedMemSharedOwned', NvU64), + ('protectedMemSharedDuped', NvU64), ] - NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA = struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA -class union_NV2080_CTRL_GPU_PID_INFO_DATA(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('vidMemUsage', NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA), - ] - +class union_NV2080_CTRL_GPU_PID_INFO_DATA(ctypes.Union): pass +union_NV2080_CTRL_GPU_PID_INFO_DATA._fields_ = [ + ('vidMemUsage', NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA), +] NV2080_CTRL_GPU_PID_INFO_DATA = union_NV2080_CTRL_GPU_PID_INFO_DATA -class struct_NV2080_CTRL_GPU_PID_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_PID_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_PID_INFO(Struct): pass struct_NV2080_CTRL_GPU_PID_INFO._fields_ = [ - ('pid', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('result', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('data', NV2080_CTRL_GPU_PID_INFO_DATA), - ('smcSubscription', NV2080_CTRL_SMC_SUBSCRIPTION_INFO), + ('pid', NvU32), + ('index', NvU32), + ('result', NvU32), + ('data', NV2080_CTRL_GPU_PID_INFO_DATA), + ('smcSubscription', NV2080_CTRL_SMC_SUBSCRIPTION_INFO), ] - NV2080_CTRL_GPU_PID_INFO = struct_NV2080_CTRL_GPU_PID_INFO -class struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS._fields_ = [ - ('pidInfoListCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pidInfoList', struct_NV2080_CTRL_GPU_PID_INFO * 200), + ('pidInfoListCount', NvU32), + ('pidInfoList', (NV2080_CTRL_GPU_PID_INFO * 200)), ] - NV2080_CTRL_GPU_GET_PID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS -class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS._fields_ = [ - ('faultType', ctypes.c_uint32), + ('faultType', NvU32), ] - NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS = struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS +enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', 0) +NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', 1) +NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', 2) +NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', 3) +NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', 4) -# values for enumeration 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE' -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE__enumvalues = { - 0: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', - 1: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', - 2: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', - 3: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', - 4: 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', -} -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = 0 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = 1 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = 2 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = 3 -NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = 4 -NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG(Structure): - pass - -class union_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('timeslice', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE), - ] - -struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG._pack_ = 1 # source:False +NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE +class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG(Struct): pass +class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data(ctypes.Union): pass +struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data._fields_ = [ + ('timeslice', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE), +] struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG._fields_ = [ - ('type', ctypes.c_uint32), - ('data', union_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data), + ('type', NvU32), + ('data', struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data), ] - NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG = struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG -class struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('config', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG), - ] - +class struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS(Struct): pass +struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS._fields_ = [ + ('config', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG), +] NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS = struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS -class struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS._fields_ = [ - ('numConfigs', ctypes.c_uint32), - ('configList', struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG * 32), + ('numConfigs', NvU32), + ('configList', (NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG * 32)), ] - NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS -class struct_NV2080_CTRL_GPU_GET_GFID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_GFID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_GFID_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_GFID_PARAMS._fields_ = [ - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_ubyte), - ('device', ctypes.c_ubyte), - ('func', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('gfid', ctypes.c_uint32), - ('gfidMask', ctypes.c_uint32), + ('domain', NvU32), + ('bus', NvU8), + ('device', NvU8), + ('func', NvU8), + ('gfid', NvU32), + ('gfidMask', NvU32), ] - NV2080_CTRL_GPU_GET_GFID_PARAMS = struct_NV2080_CTRL_GPU_GET_GFID_PARAMS -class struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('fabricPartitionId', ctypes.c_uint32), + ('gfid', NvU32), + ('bEnable', NvBool), + ('fabricPartitionId', NvU32), ] - NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS = struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS -class struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS._fields_ = [ - ('addressStart', ctypes.c_uint64), - ('addressLength', ctypes.c_uint64), - ('protection', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('addressStart', NvU64), + ('addressLength', NvU64), + ('protection', NvU32), ] - NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS = struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS -class struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS._fields_ = [ - ('egmGpaFabricBaseAddr', ctypes.c_uint64), + ('egmGpaFabricBaseAddr', NvU64), ] - NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS -class struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('engineList', ctypes.c_uint32 * 200), - ('PADDING_0', ctypes.c_ubyte * 4), - ('engineStateLoadTime', ctypes.c_uint64 * 200), - ('engineIsInit', ctypes.c_ubyte * 200), + ('engineCount', NvU32), + ('engineList', (NvU32 * 200)), + ('engineStateLoadTime', (NvU64 * 200)), + ('engineIsInit', (NvBool * 200)), ] - NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS -class struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS._fields_ = [ - ('engineCount', ctypes.c_uint32), - ('engineID', ctypes.c_uint32 * 200), - ('engineName', ctypes.c_char * 100 * 200), + ('engineCount', NvU32), + ('engineID', (NvU32 * 200)), + ('engineName', ((ctypes.c_char * 100) * 200)), ] - NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS = struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS -class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('reserved00', ctypes.c_uint32 * 2), - ('regOpCount', ctypes.c_uint32), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP * 100), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('hClientTarget', NvHandle), + ('hChannelTarget', NvHandle), + ('bNonTransactional', NvU32), + ('reserved00', (NvU32 * 2)), + ('regOpCount', NvU32), + ('regOps', (NV2080_CTRL_GPU_REG_OP * 100)), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), ] - NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS -class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO(Struct): pass struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuUuid', ctypes.c_ubyte * 16), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerId', ctypes.c_uint32), - ('busEgmPeerId', ctypes.c_uint32), + ('gpuId', NvU32), + ('gpuUuid', (NvU8 * 16)), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), + ('busPeerId', NvU32), + ('busEgmPeerId', NvU32), ] - NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO = struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO -class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS._fields_ = [ - ('bAllCaps', ctypes.c_ubyte), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('peerGpuCount', ctypes.c_uint32), - ('peerGpuCaps', struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO * 32), + ('bAllCaps', NvBool), + ('bUseUuid', NvBool), + ('peerGpuCount', NvU32), + ('peerGpuCaps', (NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO * 32)), ] - NV2080_CTRL_GET_P2P_CAPS_PARAMS = struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_GPU_COMPUTE_PROFILE(Structure): - pass - -struct_NV2080_CTRL_GPU_COMPUTE_PROFILE._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_COMPUTE_PROFILE(Struct): pass struct_NV2080_CTRL_GPU_COMPUTE_PROFILE._fields_ = [ - ('computeSize', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gfxGpcCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), + ('computeSize', NvU8), + ('gfxGpcCount', NvU32), + ('gpcCount', NvU32), + ('veidCount', NvU32), + ('smCount', NvU32), ] - NV2080_CTRL_GPU_COMPUTE_PROFILE = struct_NV2080_CTRL_GPU_COMPUTE_PROFILE -class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('profileCount', ctypes.c_uint32), - ('profiles', struct_NV2080_CTRL_GPU_COMPUTE_PROFILE * 8), + ('partitionFlag', NvU32), + ('profileCount', NvU32), + ('profiles', (NV2080_CTRL_GPU_COMPUTE_PROFILE * 8)), ] - NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS -class struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('state', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('status', ctypes.c_uint32), - ('clusterUuid', ctypes.c_ubyte * 16), - ('fabricPartitionId', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 6), - ('fabricCaps', ctypes.c_uint64), - ('fabricCliqueId', ctypes.c_uint32), - ('fabricHealthMask', ctypes.c_uint32), + ('state', NvU8), + ('status', NV_STATUS), + ('clusterUuid', (NvU8 * 16)), + ('fabricPartitionId', NvU16), + ('fabricCaps', NvU64), + ('fabricCliqueId', NvU32), + ('fabricHealthMask', NvU32), ] - NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS._fields_ = [ - ('pciDevId', ctypes.c_uint32), - ('chipSku', ctypes.c_ubyte * 4), - ('chipMajor', ctypes.c_uint32), - ('chipMinor', ctypes.c_uint32), + ('pciDevId', NvU32), + ('chipSku', (NvU8 * 4)), + ('chipMajor', NvU32), + ('chipMinor', NvU32), ] - NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS = struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS -class struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), + ('swizzId', NvU32), ] - NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS = struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS -class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS._fields_ = [ - ('hClientTarget', ctypes.c_uint32), - ('hChannelTarget', ctypes.c_uint32), - ('bNonTransactional', ctypes.c_uint32), - ('regOpCount', ctypes.c_uint32), - ('smIds', ctypes.c_uint32 * 50), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP * 50), - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('hClientTarget', NvHandle), + ('hChannelTarget', NvHandle), + ('bNonTransactional', NvU32), + ('regOpCount', NvU32), + ('smIds', (NvU32 * 50)), + ('regOps', (NV2080_CTRL_GPU_REG_OP * 50)), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), ] - NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS -class struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS._fields_ = [ - ('bResetRequired', ctypes.c_ubyte), + ('bResetRequired', NvBool), ] - NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS._fields_ = [ - ('bDrainRecommended', ctypes.c_ubyte), + ('bDrainRecommended', NvBool), ] - NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS -class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS._fields_ = [ - ('sessionInfoTblEntry', ctypes.c_uint32), - ('sessionInfoTbl', struct_NV2080_CTRL_NVENC_SW_SESSION_INFO * 512), + ('sessionInfoTblEntry', NvU32), + ('sessionInfoTbl', (NV2080_CTRL_NVENC_SW_SESSION_INFO * 512)), ] - NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS -class struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO(Structure): - pass - -struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO(Struct): pass struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO._fields_ = [ - ('engDesc', ctypes.c_uint32), - ('ctxAttr', ctypes.c_uint32), - ('ctxBufferSize', ctypes.c_uint32), - ('addrSpaceList', ctypes.c_uint32), - ('registerBase', ctypes.c_uint32), + ('engDesc', NvU32), + ('ctxAttr', NvU32), + ('ctxBufferSize', NvU32), + ('addrSpaceList', NvU32), + ('registerBase', NvU32), ] - NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO = struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO -class struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS._fields_ = [ - ('numConstructedFalcons', ctypes.c_uint32), - ('constructedFalconsTable', struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO * 64), + ('numConstructedFalcons', NvU32), + ('constructedFalconsTable', (NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO * 64)), ] - NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS -class struct_NV2080_VF_MSIX_CAPS(Structure): - pass - -struct_NV2080_VF_MSIX_CAPS._pack_ = 1 # source:False +class struct_NV2080_VF_MSIX_CAPS(Struct): pass struct_NV2080_VF_MSIX_CAPS._fields_ = [ - ('msix_header', ctypes.c_uint32), - ('msix_table', ctypes.c_uint32), - ('msix_pba', ctypes.c_uint32), + ('msix_header', NvU32), + ('msix_table', NvU32), + ('msix_pba', NvU32), ] - NV2080_VF_MSIX_CAPS = struct_NV2080_VF_MSIX_CAPS -class struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('vfMsixCap', NV2080_VF_MSIX_CAPS), + ('gfid', NvU32), + ('vfMsixCap', NV2080_VF_MSIX_CAPS), ] - NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS = struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS +enum_NV2080_CTRL_GPU_RECOVERY_ACTION = CEnum(ctypes.c_uint32) +NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', 0) +NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', 1) +NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', 2) +NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', 3) +NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', 4) -# values for enumeration 'NV2080_CTRL_GPU_RECOVERY_ACTION' -NV2080_CTRL_GPU_RECOVERY_ACTION__enumvalues = { - 0: 'NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', - 1: 'NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', - 2: 'NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', - 3: 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', - 4: 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', -} -NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = 0 -NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = 1 -NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = 2 -NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3 -NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = 4 -NV2080_CTRL_GPU_RECOVERY_ACTION = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('action', NV2080_CTRL_GPU_RECOVERY_ACTION), - ] - +NV2080_CTRL_GPU_RECOVERY_ACTION = enum_NV2080_CTRL_GPU_RECOVERY_ACTION +class struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS(Struct): pass +struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS._fields_ = [ + ('action', NV2080_CTRL_GPU_RECOVERY_ACTION), +] NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS = struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS -class struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS._fields_ = [ - ('bFipsEnabled', ctypes.c_ubyte), + ('bFipsEnabled', NvBool), ] - NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS +enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE = CEnum(ctypes.c_uint32) +NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', 0) +NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', 1) +NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', 2) -# values for enumeration 'NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE' -NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE__enumvalues = { - 0: 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', - 1: 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', - 2: 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', -} -NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = 0 -NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = 1 -NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = 2 -NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_RAFTS_FLOORSWEEP_INFO(Structure): - pass - -struct_NV2080_RAFTS_FLOORSWEEP_INFO._pack_ = 1 # source:False +NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE +class struct_NV2080_RAFTS_FLOORSWEEP_INFO(Struct): pass struct_NV2080_RAFTS_FLOORSWEEP_INFO._fields_ = [ - ('unitType', NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE), - ('parentId', ctypes.c_uint32), - ('mask', ctypes.c_uint32), + ('unitType', NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE), + ('parentId', NvU32), + ('mask', NvU32), ] - NV2080_RAFTS_FLOORSWEEP_INFO = struct_NV2080_RAFTS_FLOORSWEEP_INFO -class struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS._fields_ = [ - ('tpcCountMatrix', ctypes.c_ubyte * 12 * 2), - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('floorSweepConfig', struct_NV2080_RAFTS_FLOORSWEEP_INFO * 26), - ('gfxGpcCount', ctypes.c_ubyte), - ('gfxTpcPerGpcCount', ctypes.c_ubyte), - ('maxUgpuTpcDiff', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), + ('tpcCountMatrix', ((NvU8 * 12) * 2)), + ('bValid', NvBool), + ('floorSweepConfig', (NV2080_RAFTS_FLOORSWEEP_INFO * 26)), + ('gfxGpcCount', NvU8), + ('gfxTpcPerGpcCount', NvU8), + ('maxUgpuTpcDiff', NvU8), ] - NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS = struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS -class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('computeSize', ctypes.c_uint32), - ('totalProfileCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalSpans', struct_NV2080_CTRL_EXEC_PARTITION_SPAN * 8), - ('totalSpansCount', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('partitionFlag', NvU32), + ('computeSize', NvU32), + ('totalProfileCount', NvU32), + ('totalSpans', (NV2080_CTRL_EXEC_PARTITION_SPAN * 8)), + ('totalSpansCount', NvU32), ] - NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS -class struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [ - ('gpc', ctypes.c_uint32), - ('tpcReconfigMask', ctypes.c_uint32), + ('gpc', NvU32), + ('tpcReconfigMask', NvU32), ] - NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS -class struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS._fields_ = [ - ('vgpuName', ctypes.c_ubyte * 16), - ('gpuPciId', ctypes.c_uint32), - ('gpuPciBdf', ctypes.c_uint32), - ('vgpuTypeId', ctypes.c_uint32), - ('vgpuId', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('gpuInstanceId', ctypes.c_uint32), - ('placementId', ctypes.c_uint32), -] - -NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS -class struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS._fields_ = [ - ('gpuPciId', ctypes.c_uint32), - ('gpuPciBdf', ctypes.c_uint32), - ('numVgpuTypes', ctypes.c_uint32), - ('vgpuTypeIds', ctypes.c_uint32 * 64), - ('availableInstances', ctypes.c_uint32 * 64), -] - -NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS = struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS -class struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS._fields_ = [ - ('vgpuName', ctypes.c_ubyte * 16), - ('vgpuId', ctypes.c_uint16), -] - -NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS -class struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS(Structure): - pass - -struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS._fields_ = [ - ('returnStatus', ctypes.c_uint32), - ('gpuId', ctypes.c_uint32), -] - -NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS = struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS -class struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS(Structure): - pass - -struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS._pack_ = 1 # source:False -struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS._fields_ = [ - ('vgpuName', ctypes.c_ubyte * 16), - ('mode', ctypes.c_uint32), - ('sysfs_val', ctypes.c_uint32), -] - -NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS = struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS -NV0080_CTRL_CMD_BIF_RESET = (0x800102) # macro -NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID = (0x2) # macro -# NV0080_CTRL_BIF_RESET_FLAGS_TYPE = 4 : 0 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET = 0x1 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR = 0x2 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL = 0x3 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE = 0x4 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE = 0x5 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX = 0x6 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER = 0x7 # macro -NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE = 0x8 # macro -NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE = (0x800104) # macro -NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID = (0x4) # macro -# NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S = 0 : 0 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED = 0x000000001 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED = 0x000000000 # macro -# NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1 = 1 : 1 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED = 0x000000001 # macro -NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED = 0x000000000 # macro -NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE = (0x800105) # macro -NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID = (0x5) # macro -NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK = (0x800106) # macro -NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID = (0x6) # macro -class struct_NV0080_CTRL_BIF_RESET_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BIF_RESET_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BIF_RESET_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV0080_CTRL_BIF_RESET_PARAMS = struct_NV0080_CTRL_BIF_RESET_PARAMS -class struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS._fields_ = [ - ('aspmFeatureSupported', ctypes.c_uint32), -] - -NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS = struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS -class struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS._fields_ = [ - ('bL0sEnable', ctypes.c_ubyte), - ('bL1Enable', ctypes.c_ubyte), -] - -NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS = struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS -class struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS(Structure): - pass - -struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS._fields_ = [ - ('pciePowerControlMask', ctypes.c_uint32), - ('pciePowerControlIdentifiedKeyOrder', ctypes.c_uint32), - ('pciePowerControlIdentifiedKeyLocation', ctypes.c_uint32), -] - -NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS = struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS -NV0080_CTRL_CMD_BSP_GET_CAPS = (0x801c01) # macro -NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_BSP_CAPS_TBL_SIZE = 8 # macro -NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = (0x801c02) # macro -NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), - ('instanceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_BSP_GET_CAPS_PARAMS = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS -class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2(Structure): - pass - -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2._pack_ = 1 # source:False -struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 8), - ('instanceId', ctypes.c_uint32), -] - -NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID = 0 : 0 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED = 2 : 1 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED = (0x00000002) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE = 6 : 3 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS = 10 : 7 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 = (0x00000002) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 = (0x00000004) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED = 12 : 11 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED = (0x00000002) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS = 14 : 13 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED = (0x00000003) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY = 15 : 15 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC = 16 : 16 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING = 17 : 17 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED = 18 : 18 # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_DMA_GET_PTE_INFO = (0x801801) # macro -NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS = 5 # macro -NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_CMD_DMA_SET_PTE_INFO = (0x80180a) # macro -NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS = 5 # macro -NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID = (0xA) # macro -NV0080_CTRL_CMD_DMA_FILL_PTE_MEM = (0x801802) # macro -NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID = (0x2) # macro -NV0080_CTRL_CMD_DMA_FLUSH = (0x801805) # macro -NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID = (0x5) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2 = 0 : 0 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG = 1 : 1 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB = 2 : 2 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE = (0x00000000) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE = (0x00000001) # macro -# NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE = 4 : 3 # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM = (0x00000001) # macro -NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM = (0x00000002) # macro -NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = (0x801806) # macro -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS = (16) # macro -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID = (0x6) # macro -NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO = 0x1 # macro -NV0080_CTRL_CMD_DMA_GET_PDE_INFO = (0x801809) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS = 5 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL = 1 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF = 2 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER = 3 # macro -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH = 4 # macro -NV0080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x80180c) # macro -NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0xC) # macro -# NV0080_CTRL_DMA_INVALIDATE_TLB_ALL = 0 : 0 # macro -NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_DMA_GET_CAPS = (0x80180d) # macro -NV0080_CTRL_DMA_CAPS_TBL_SIZE = 8 # macro -NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID = (0xD) # macro -# def NV0080_CTRL_DMA_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_DMA_CAPS_32BIT_POINTER_ENFORCED = 0 : 0x01 # macro -# NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED = 0 : 0x04 # macro -# NV0080_CTRL_DMA_CAPS_SPARSE_VIRTUAL_SUPPORTED = 0 : 0x08 # macro -# NV0080_CTRL_DMA_CAPS_MULTIPLE_VA_SPACES_SUPPORTED = 0 : 0x10 # macro -NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE = (0x80180e) # macro -NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID = (0xE) # macro -NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX = (0xFFFFFFFFFFFFFFFF) # macro -NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 = (0x80180f) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY = (0x00000001) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL = 0 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG = 1 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE = 2 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID = (0xF) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE = 0 : 0 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE = 1 : 1 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE = 3 : 2 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF = (0x00000001) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER = (0x00000002) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH = (0x00000003) # macro -# NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE = 4 : 4 # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE = (0x00000001) # macro -NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE = (0x801810) # macro -NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID = (0x10) # macro -NV0080_CTRL_DMA_SET_DEFAULT_VASPACE = (0x801812) # macro -NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID = (0x12) # macro -NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY = (0x801813) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x13) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE = 1 : 0 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH = (0x00000001) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH = (0x00000002) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES = 2 : 2 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS = 3 : 3 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY = 4 : 4 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE = (0x00000001) # macro -# NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE = 5 : 5 # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE = (0x00000000) # macro -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY = (0x801814) # macro -NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x14) # macro -class struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK(Structure): - pass - -struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK._fields_ = [ - ('pageSize', ctypes.c_uint64), - ('pteEntrySize', ctypes.c_uint64), - ('comptagLine', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('pteFlags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK -class struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS._fields_ = [ - ('gpuAddr', ctypes.c_uint64), - ('subDeviceId', ctypes.c_uint32), - ('skipVASpaceInit', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pteBlocks', struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5), - ('hVASpace', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS -class struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS._fields_ = [ - ('gpuAddr', ctypes.c_uint64), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pteBlocks', struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5), - ('hVASpace', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS -class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS(Structure): - pass - -class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource(Structure): - pass - -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), -] - -class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo(Structure): - pass - -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo._fields_ = [ - ('fbKind', ctypes.c_uint32), - ('sysKind', ctypes.c_uint32), - ('compTagStartOffset', ctypes.c_uint32), -] - -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS._fields_ = [ - ('pageCount', ctypes.c_uint32), - ('hwResource', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource), - ('comprInfo', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo), - ('offset', ctypes.c_uint64), - ('gpuAddr', ctypes.c_uint64), - ('pageArray', ctypes.POINTER(None)), - ('pteMem', ctypes.POINTER(None)), - ('pteMemPfn', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('startPageIndex', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hSrcVASpace', ctypes.c_uint32), - ('hTgtVASpace', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS = struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS -class struct_NV0080_CTRL_DMA_FLUSH_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_FLUSH_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_FLUSH_PARAMS._fields_ = [ - ('targetUnit', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_FLUSH_PARAMS = struct_NV0080_CTRL_DMA_FLUSH_PARAMS -class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT(Structure): - pass - -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT._fields_ = [ - ('pageTableSize', ctypes.c_uint32), - ('pageTableCoverage', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT -class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS._fields_ = [ - ('vaBitCount', ctypes.c_uint32), - ('pdeCoverageBitCount', ctypes.c_uint32), - ('num4KPageTableFormats', ctypes.c_uint32), - ('bigPageSize', ctypes.c_uint32), - ('compressionPageSize', ctypes.c_uint32), - ('dualPageTableSupported', ctypes.c_uint32), - ('idealVRAMPageSize', ctypes.c_uint32), - ('pageTableBigFormat', NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT), - ('pageTable4KFormat', struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT * 16), - ('hVASpace', ctypes.c_uint32), - ('vaRangeLo', ctypes.c_uint64), - ('vaSpaceId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('supportedPageSizeMask', ctypes.c_uint64), -] - -NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS -class struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK(Structure): - pass - -struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK._fields_ = [ - ('ptePhysAddr', ctypes.c_uint64), - ('pteCacheAttrib', ctypes.c_uint32), - ('pteEntrySize', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('pteAddrSpace', ctypes.c_uint32), - ('pdeVASpaceSize', ctypes.c_uint32), - ('pdeFlags', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK -class struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS._fields_ = [ - ('gpuAddr', ctypes.c_uint64), - ('pdeVirtAddr', ctypes.c_uint64), - ('pdeEntrySize', ctypes.c_uint32), - ('pdeAddrSpace', ctypes.c_uint32), - ('pdeSize', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pteBlocks', struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK * 5), - ('pdbAddr', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS -class struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS -class struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('capsTbl', ctypes.c_ubyte * 8), -] - -NV0080_CTRL_DMA_GET_CAPS_PARAMS = struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS -class struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS._fields_ = [ - ('vaSpaceSize', ctypes.c_uint64), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS = struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS -class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS._fields_ = [ - ('physAddr', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('aperture', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS -class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS._fields_ = [ - ('pdeIndex', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('ptParams', struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS * 2), - ('hVASpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pPdeBuffer', ctypes.POINTER(None)), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS -class struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS = struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS -class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS -class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), - ('chId', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pasid', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS -class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS(Structure): - pass - -struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS._fields_ = [ - ('hVASpace', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), -] - -NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS -NV0080_CTRL_CMD_FB_GET_CAPS = (0x801301) # macro -NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV0080_CTRL_FB_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_FB_CAPS_SUPPORT_RENDER_TO_SYSMEM = 0 : 0x01 # macro -# NV0080_CTRL_FB_CAPS_BLOCKLINEAR = 0 : 0x02 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_SCANOUT_FROM_SYSMEM = 0 : 0x04 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_CACHED_SYSMEM = 0 : 0x08 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_C24_COMPRESSION = 0 : 0x10 # macro -# NV0080_CTRL_FB_CAPS_SUPPORT_SYSMEM_COMPRESSION = 0 : 0x20 # macro -# NV0080_CTRL_FB_CAPS_NISO_CFG0_BUG_534680 = 0 : 0x40 # macro -# NV0080_CTRL_FB_CAPS_ISO_FETCH_ALIGN_BUG_561630 = 0 : 0x80 # macro -# NV0080_CTRL_FB_CAPS_BLOCKLINEAR_GOBS_512 = 1 : 0x01 # macro -# NV0080_CTRL_FB_CAPS_L2_TAG_BUG_632241 = 1 : 0x02 # macro -# NV0080_CTRL_FB_CAPS_SINGLE_FB_UNIT = 1 : 0x04 # macro -# NV0080_CTRL_FB_CAPS_CE_RMW_DISABLE_BUG_897745 = 1 : 0x08 # macro -# NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB = 1 : 0x10 # macro -# NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET = 1 : 0x20 # macro -# NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 = 1 : 0x40 # macro -# NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND = 1 : 0x80 # macro -# NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 = 2 : 0x01 # macro -# NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED = 2 : 0x02 # macro -# NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY = 2 : 0x04 # macro -# NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 = 2 : 0x08 # macro -# NV0080_CTRL_FB_CAPS_PARTIAL_UNMAP = 2 : 0x10 # macro -NV0080_CTRL_FB_CAPS_TBL_SIZE = 3 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO = (0x801306) # macro -NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN = 0 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM = 1 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM = 2 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY = 0 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 = 1 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 = 2 # macro -NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE = 3 # macro -NV0080_CTRL_CMD_FB_GET_CAPS_V2 = (0x801307) # macro -NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY = (0x801308) # macro -NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV0080_CTRL_FB_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_FB_GET_CAPS_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_PARAMS -class struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS._fields_ = [ - ('Size', ctypes.c_uint64), - ('Address', ctypes.c_uint64), - ('AddressSpace', ctypes.c_uint32), - ('MaxCompbitLine', ctypes.c_uint32), - ('comptagsPerCacheLine', ctypes.c_uint32), - ('cacheLineSize', ctypes.c_uint32), - ('cacheLineSizePerSlice', ctypes.c_uint32), - ('cacheLineFetchAlignment', ctypes.c_uint32), - ('backingStoreBase', ctypes.c_uint64), - ('gobsPerComptagPerSlice', ctypes.c_uint32), - ('backingStoreCbcBase', ctypes.c_uint32), - ('comptaglineAllocationPolicy', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('privRegionStartOffset', ctypes.c_uint64), - ('cbcCoveragePerSlice', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS = struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS -class struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 3), -] - -NV0080_CTRL_FB_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS -class struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), -] - -NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS = struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS - -# values for enumeration 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY' -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY__enumvalues = { - 0: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', - 1: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', - 2: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', - 3: 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', -} -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3 -NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY = ctypes.c_uint32 # enum -NV0080_CTRL_CMD_FIFO_GET_CAPS = (0x801701) # macro -NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV0080_CTRL_FIFO_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_FIFO_CAPS_SUPPORT_SCHED_EVENT = 0 : 0x01 # macro -# NV0080_CTRL_FIFO_CAPS_SUPPORT_PCI_PB = 0 : 0x02 # macro -# NV0080_CTRL_FIFO_CAPS_SUPPORT_VID_PB = 0 : 0x04 # macro -# NV0080_CTRL_FIFO_CAPS_USERD_IN_SYSMEM = 0 : 0x40 # macro -# NV0080_CTRL_FIFO_CAPS_NO_PIPELINED_PTE_BLIT = 0 : 0x80 # macro -# NV0080_CTRL_FIFO_CAPS_GPU_MAP_CHANNEL = 1 : 0x01 # macro -# NV0080_CTRL_FIFO_CAPS_BUFFEREDMODE_SCHEDULING = 1 : 0x02 # macro -# NV0080_CTRL_FIFO_CAPS_WFI_BUG_898467 = 1 : 0x08 # macro -# NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921 = 1 : 0x10 # macro -# NV0080_CTRL_FIFO_CAPS_MULTI_VAS_PER_CHANGRP = 1 : 0x20 # macro -# NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING = 1 : 0x40 # macro -NV0080_CTRL_FIFO_CAPS_TBL_SIZE = 2 # macro -NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = (0x801707) # macro -# NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID = 4 : 0 # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS = (0x00000000) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD = (0x00000001) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO = (0x00000002) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG = (0x00000003) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE = (0x00000004) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY = (0x00000005) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION = (0x00000006) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS = (0x00000007) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL = (0x00000008) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM = (0x00000009) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT = (0x0000000a) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT = (0x0000000b) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL = (0x0000000c) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL = (0x0000000d) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB = (0x0000000e) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV = (0x0000000f) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH = (0x00000010) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB = (0x00000011) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL = (0x00000012) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB = (0x00000013) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL = (0x00000014) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL = (0x00000015) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK = (0x00000016) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT = (0x00000017) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP = (0x00000018) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP = (0x00000019) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = (0x0000001a) # macro -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS = (0x801709) # macro -NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS = (8) # macro -NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE = (0x80170b) # macro -NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR = (12) # macro -NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST = (0x80170c) # macro -NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = (0x80170d) # macro -NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID = (0xD) # macro -NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE = (0x80170e) # macro -NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0xE) # macro -NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL = (0xffffffff) # macro -NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES = (0x80170f) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID = (0xF) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS = (0x00000000) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS = (0x00000001) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE = (0x00000002) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE = (0x00000003) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET = (0x00000004) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT = (0x00000005) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP = (0x00000007) # macro -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT = (0x00000008) # macro -NV0080_CTRL_CMD_FIFO_STOP_RUNLIST = (0x801711) # macro -NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID = (0x11) # macro -NV0080_CTRL_CMD_FIFO_START_RUNLIST = (0x801712) # macro -NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID = (0x12) # macro -NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 = (0x801713) # macro -NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x13) # macro -NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS = (0x801714) # macro -NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS = 4096 # macro -NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x14) # macro -class struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_FIFO_GET_CAPS_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS -class struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS -class struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM(Structure): - pass - -struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM._fields_ = [ - ('hChannel1', ctypes.c_uint32), - ('hChannel2', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM -class struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM(Structure): - pass - -struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('tsDivisor', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM -class struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS._fields_ = [ - ('hRunlist', ctypes.c_uint32), - ('engineID', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS -class struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pChannelHandleList', ctypes.POINTER(None)), - ('pChannelList', ctypes.POINTER(None)), -] - -NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS = struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS -class struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS._fields_ = [ - ('engineID', ctypes.c_uint32), - ('gpEntries', ctypes.c_uint32), - ('pbEntries', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS = struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS -class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('property', ctypes.c_uint32), - ('value', ctypes.c_uint64), -] - -NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS -class struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS._fields_ = [ - ('engineID', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS -class struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS._fields_ = [ - ('engineID', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_START_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS -class struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 2), -] - -NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS -class struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('hChannels', ctypes.c_uint32 * 4096), - ('flags', ctypes.c_uint32), - ('timeout', ctypes.c_uint32), -] - -NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS = struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS -NV0080_CTRL_CMD_GPU_GET_CLASSLIST = (0x800201) # macro -NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = (0x800280) # macro -NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID = (0x80) # macro -NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER = (0x800281) # macro -NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID = (0x81) # macro -NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER = (0x800282) # macro -NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x82) # macro -NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER = (0x800283) # macro -NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x83) # macro -NV0080_CTRL_CMD_GPU_SET_VIDLINK = (0x800285) # macro -NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID = (0x85) # macro -NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE = (0x00000000) # macro -NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE = (0x00000001) # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS = 0 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN = 1 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP = 2 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON = 0 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN = 1 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED = 2 # macro -NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP = 3 # macro -NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE = (0x800287) # macro -NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED = (0x00000000) # macro -NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED = (0x00000001) # macro -NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x87) # macro -NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = (0x800288) # macro -NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x88) # macro -NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = (0x800289) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE = (0x00000000) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS = (0x00000001) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX = (0x00000002) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST = (0x00000003) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU = (0x00000003) # macro -NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA = (0x00000004) # macro -NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID = (0x89) # macro -NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028c) # macro -NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8C) # macro -NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028d) # macro -NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8D) # macro -NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT = 0 # macro -NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE = 1 # macro -NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE = 2 # macro -NV0080_CTRL_CMD_GPU_GET_VGX_CAPS = (0x80028e) # macro -NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID = (0x8E) # macro -NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS = (0x800291) # macro -NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID = (0x91) # macro -NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE = 100 # macro -NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = (0x800292) # macro -NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID = (0x92) # macro -NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE = (0x800293) # macro -NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID = (0x93) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO = (1 << 0) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS = (1 << 1) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN = (1 << 2) # macro -NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS = (0x800294) # macro -NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID = (0x94) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M = (1<<6) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M = (1<<7) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M = (1<<8) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M = (1<<9) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G = (1<<10) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G = (1<<11) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G = (1<<12) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G = (1<<13) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G = (1<<14) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G = (1<<15) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G = (1<<16) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G = (1<<17) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G = (1<<18) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN = (1<<6) # macro -NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX = (1<<18) # macro -NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID = 0x0 # macro -NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE = (0x800296) # macro -NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID = (0x96) # macro -NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE = (0x800297) # macro -NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x97) # macro -NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE = (0x800298) # macro -NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x98) # macro -class struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS._fields_ = [ - ('numClasses', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('classList', ctypes.POINTER(None)), -] - -NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS -class struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS._fields_ = [ - ('numSubDevices', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS = struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS -class struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS._fields_ = [ - ('ConnectionCount', ctypes.c_uint32), - ('Order', ctypes.c_uint32 * 8), -] - -NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS = struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS -class struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS._fields_ = [ - ('subDeviceInstance', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS -class struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS._fields_ = [ - ('subDeviceInstance', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS -class struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS._fields_ = [ - ('enable', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_VIDLINK_PARAMS = struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS -class struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [ - ('newState', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS -class struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [ - ('swStatePersistence', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS -class struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS._fields_ = [ - ('virtualizationMode', ctypes.c_uint32), - ('isGridBuild', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS -class struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [ - ('defaultSetting', ctypes.c_uint32), - ('currentSetting', ctypes.c_uint32), - ('pendingSetting', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS -class struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [ - ('setting', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS -class struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS._fields_ = [ - ('isVgx', ctypes.c_ubyte), -] - -NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS -class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._fields_ = [ - ('totalVFs', ctypes.c_uint32), - ('firstVfOffset', ctypes.c_uint32), - ('vfFeatureMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('FirstVFBar0Address', ctypes.c_uint64), - ('FirstVFBar1Address', ctypes.c_uint64), - ('FirstVFBar2Address', ctypes.c_uint64), - ('bar0Size', ctypes.c_uint64), - ('bar1Size', ctypes.c_uint64), - ('bar2Size', ctypes.c_uint64), - ('b64bitBar0', ctypes.c_ubyte), - ('b64bitBar1', ctypes.c_ubyte), - ('b64bitBar2', ctypes.c_ubyte), - ('bSriovEnabled', ctypes.c_ubyte), - ('bSriovHeavyEnabled', ctypes.c_ubyte), - ('bEmulateVFBar0TlbInvalidationRegister', ctypes.c_ubyte), - ('bClientRmAllocatedCtxBuffer', ctypes.c_ubyte), - ('bNonPowerOf2ChannelCountSupported', ctypes.c_ubyte), - ('bVfResizableBAR1Supported', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS -class struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS._fields_ = [ - ('numClasses', ctypes.c_uint32), - ('classList', ctypes.c_uint32 * 100), -] - -NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS -class struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM(Structure): - pass - -struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM._fields_ = [ - ('subDeviceInst', ctypes.c_uint32), - ('hSubDevice', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM = struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM -class struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS._fields_ = [ - ('brands', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS -class struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS._fields_ = [ - ('vfBar1SizeMB', ctypes.c_uint32), - ('numVfs', ctypes.c_uint32), -] - -NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS -class struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ - ('bHeterogeneousMode', ctypes.c_ubyte), -] - -NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS -class struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS(Structure): - pass - -struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ - ('bHeterogeneousMode', ctypes.c_ubyte), -] - -NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS -NV0080_CTRL_CMD_HOST_GET_CAPS = (0x801401) # macro -NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV0080_CTRL_HOST_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 = 2 : 0x20 # macro -# NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD = 2 : 0x40 # macro -NV0080_CTRL_HOST_CAPS_TBL_SIZE = 3 # macro -NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = (0x801402) # macro -NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_HOST_GET_CAPS_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS -class struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 3), -] - -NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS -NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7) # macro -NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID = (0x9) # macro -NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = (0x801909) # macro -NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE = (0x802002) # macro -NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x2) # macro -NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE = (0x802003) # macro -NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x3) # macro -NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL = (0x802009) # macro -NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x802004) # macro -NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL = (0x802007) # macro -NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS = (0x802008) # macro -NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS = 200 # macro -NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0x08) # macro -class struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS(Structure): - pass - -struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [ - ('bActivate', ctypes.c_ubyte), -] - -NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS -class struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS(Structure): - pass - -struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS._fields_ = [ - ('bCudaLimit', ctypes.c_ubyte), -] - -NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS -class struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS), - ] - -NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS -class struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS), - ] - -NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS -class struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS._fields_ = [ - ('numClients', ctypes.c_uint32), - ('clientHandles', ctypes.c_uint32 * 200), -] - -NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS = struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS -NV0080_CTRL_CMD_MSENC_GET_CAPS = (0x801b01) # macro -NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_MSENC_CAPS_TBL_SIZE = 4 # macro -NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 = (0x801b02) # macro -NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(Structure): - pass - -struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS._fields_ = [ - ('capsTblSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('capsTbl', ctypes.POINTER(None)), -] - -NV0080_CTRL_MSENC_GET_CAPS_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS -class struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 4), - ('instanceId', ctypes.c_uint32), -] - -NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS -NV0080_CTRL_NVJPG_CAPS_TBL_SIZE = 9 # macro -NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 = (0x801f02) # macro -NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('instanceId', ctypes.c_uint32), -] - -NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS -NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH = (0x801e01) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID = (0x1) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE = (0x00000001) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE = (0x00000002) # macro -NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED = (0x00000003) # macro -NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO = (0x801e02) # macro -NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS(Structure): - pass - -struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), -] - -NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS -class struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS(Structure): - pass - -struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS._pack_ = 1 # source:False -struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS._fields_ = [ - ('subDeviceInstance', ctypes.c_uint32), - ('width', ctypes.c_uint16), - ('height', ctypes.c_uint16), - ('depth', ctypes.c_uint16), - ('pitch', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), - ('baseAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS -NV2080_CTRL_BIOS_INFO_MAX_SIZE = (0x0000000F) # macro -NV2080_CTRL_BIOS_INFO_INDEX_REVISION = (0x00000000) # macro -NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION = (0x00000001) # macro -NV2080_CTRL_CMD_BIOS_GET_INFO = (0x20800802) # macro -NV2080_CTRL_CMD_BIOS_GET_INFO_V2 = (0x20800810) # macro -NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH = (0x00000100) # macro -NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII = (0x00000000) # macro -NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE = (0x00000001) # macro -NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH = (0x00000002) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_ROOT = (0x00000000) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_RM = (0x00000001) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER = (0x00000002) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO = (0x00000003) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_CPL = (0x00000004) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_D3D = (0x00000005) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_OGL = (0x00000006) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_PMU = (0x00000007) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_MODE = (0x00000008) # macro -NV2080_CTRL_BIOS_NBSI_NUM_MODULES = (0x00000009) # macro -NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN = (0x80000000) # macro -NV2080_CTRL_BIOS_GET_NBSI_SUCCESS = (0x00000000) # macro -NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE = (0x00000001) # macro -NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH = (0xFFFFFFFA) # macro -NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS = (0xFFFFFFFB) # macro -NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE = (0xFFFFFFFC) # macro -NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE = (0xFFFFFFFD) # macro -NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE = (0xFFFFFFFE) # macro -NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND = (0xFFFFFFFF) # macro -NV2080_CTRL_CMD_BIOS_GET_NBSI = (0x20800803) # macro -NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 = (0x2080080e) # macro -NV2080_BIOS_GET_NBSI_MAX_RET_SIZE = (0x100) # macro -NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ = (0x20800806) # macro -NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID = (0x6) # macro -GLOB_TYPE_GET_NBSI_DIR = 0xfffe # macro -GLOB_TYPE_APITEST = 0xffff # macro -GLOB_TYPE_GET_NBSI_ACPI_RAW = 0xfffd # macro -NV2080_CTRL_CMD_BIOS_GET_SKU_INFO = (0x20800808) # macro -NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_BIOS_GET_POST_TIME = (0x20800809) # macro -NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT = (0x2080080b) # macro -NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID = (0xB) # macro -# NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE = 1 : 0 # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO = (0x00000000) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES = (0x00000001) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER = (0x00000002) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN = (0x00000003) # macro -# NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING = 2 : 2 # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE = (0x00000000) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE = (0x00000001) # macro -# NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT = 3 : 3 # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE = (0x00000000) # macro -NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE = (0x00000001) # macro -NV2080_CTRL_BIOS_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS._fields_ = [ - ('biosInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('biosInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_BIOS_GET_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS -class struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS._fields_ = [ - ('biosInfoListSize', ctypes.c_uint32), - ('biosInfoList', struct_NVXXXX_CTRL_XXX_INFO * 15), -] - -NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING(Structure): - pass - -class union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value(Union): - pass - -union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value._pack_ = 1 # source:False -union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value._fields_ = [ - ('ascii', ctypes.c_ubyte * 256), - ('unicode', ctypes.c_uint16 * 256), - ('hash', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 510), -] - -struct_NV2080_CTRL_BIOS_NBSI_REG_STRING._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_NBSI_REG_STRING._fields_ = [ - ('size', ctypes.c_uint32), - ('type', ctypes.c_uint32), - ('value', union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value), -] - -NV2080_CTRL_BIOS_NBSI_REG_STRING = struct_NV2080_CTRL_BIOS_NBSI_REG_STRING -class struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS._fields_ = [ - ('module', ctypes.c_uint32), - ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('PADDING_0', ctypes.c_ubyte * 4), - ('retBuf', ctypes.POINTER(None)), - ('retSize', ctypes.c_uint32), - ('errorCode', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_NBSI_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS -class struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS._fields_ = [ - ('module', ctypes.c_uint32), - ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING), - ('retBuf', ctypes.c_ubyte * 256), - ('retSize', ctypes.c_uint32), - ('errorCode', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS -class struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS._fields_ = [ - ('globType', ctypes.c_uint16), - ('globIndex', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('globSource', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('retBufOffset', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('retBuf', ctypes.POINTER(None)), - ('retSize', ctypes.c_uint32), - ('totalObjSize', ctypes.c_uint32), - ('errorCode', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS -class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._fields_ = [ - ('BoardID', ctypes.c_uint32), - ('chipSKU', ctypes.c_char * 9), - ('chipSKUMod', ctypes.c_char * 5), - ('PADDING_0', ctypes.c_ubyte * 2), - ('skuConfigVersion', ctypes.c_uint32), - ('project', ctypes.c_char * 5), - ('projectSKU', ctypes.c_char * 5), - ('CDP', ctypes.c_char * 6), - ('projectSKUMod', ctypes.c_char * 2), - ('PADDING_1', ctypes.c_ubyte * 2), - ('businessCycle', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS -class struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS._fields_ = [ - ('vbiosPostTime', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS = struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS -class struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS = struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS -NV2080_CTRL_CMD_BUS_GET_PCI_INFO = (0x20801801) # macro -NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_BUS_INFO_INDEX_TYPE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_INDEX_INTLINE = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_INDEX_CAPS = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS = (0x00000005) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS = (0x00000006) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS = (0x00000007) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS = (0x00000009) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS = (0x0000000A) # macro -NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS = (0x0000000B) # macro -NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS = (0x0000000C) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE = (0x0000000D) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS = (0x0000000E) # macro -NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER = (0x0000000F) # macro -NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER = (0x00000010) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS = (0x00000011) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS = (0x00000012) # macro -NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE = (0x00000013) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO = (0x00000014) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER = (0x00000015) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS = (0x00000016) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS = (0x00000017) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS = (0x00000018) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT = (0x00000019) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT = (0x0000001A) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM = (0x0000001B) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS = (0x0000001C) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS = (0x0000001D) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED = (0x0000001E) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS = (0x0000001F) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR = (0x00000020) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR = (0x00000021) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR = (0x00000022) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR = (0x00000023) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS = (0x00000024) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS = (0x00000025) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS = (0x00000026) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS = (0x00000027) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR = (0x00000028) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR = (0x00000029) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR = (0x0000002A) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR = (0x0000002B) # macro -NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER = (0x0000002C) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO = (0x0000002D) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE = (0x0000002E) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO = (0x0000002F) # macro -NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO = (0x00000030) # macro -NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO = (0x00000031) # macro -NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI = (0x00000032) # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE = (0x00000033) # macro -NV2080_CTRL_BUS_INFO_INDEX_MAX = (0x00000033) # macro -NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE = (0x00000034) # macro -NV2080_CTRL_BUS_INFO_TYPE_PCI = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_TYPE_FPCI = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_TYPE_AXI = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED = (0x00000002) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED = 3 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS = (0x00000005) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS = (0x00000006) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH = 9 : 4 # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM = 11 : 10 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 = (0x00000003) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN = 15 : 12 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 = (0x00000005) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL = 19 : 16 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 = (0x00000005) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN = 23 : 20 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 = (0x00000005) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES = 24 : 24 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM = 1 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 = (0x00000003) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED = 19 : 16 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS = (0x00000003) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS = (0x00000005) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS = (0x00000006) # macro -# NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH = 25 : 20 # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 = (0x0000000C) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 = (0x00000010) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 = (0x00000020) # macro -# NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY = (0x00000010) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP = (0x00000004) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR = (0x00000008) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT = (0x00000010) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT = (0x00000020) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL = (0x00000040) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW = (0x00000080) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP = (0x00000100) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR = (0x00000200) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ = (0x00000400) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR = (0x00010000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP = (0x00020000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP = (0x00040000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER = (0x00080000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT = (0x00100000) # macro -NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL = (0x00200000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04 = 4 : 4 # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM = 2 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 = (0x00000002) # macro -NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 = (0x00000003) # macro -# NV2080_CTRL_BUS_INFO_MSI_STATUS = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED = (0x00000001) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED = 4 : 4 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_RESERVED = 7 : 5 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PORT_RESTORE_TIME = 15 : 8 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_SCALE = 17 : 16 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_T_POWER_ON_VALUE = 23 : 19 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED = 0 : 0 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED = 1 : 1 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED = 2 : 2 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED = 3 : 3 # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO = (0x00000000) # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_COMMON_MODE_RESTORE_TIME = 15 : 8 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_VALUE = 25 : 16 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_LTR_L1_2_THRESHOLD_SCALE = 31 : 29 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_SCALE = 1 : 0 # macro -# NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL2_T_POWER_ON_VALUE = 7 : 3 # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE = (0x00000000) # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK = (0x00000001) # macro -NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C = (0x00000002) # macro -NV2080_CTRL_CMD_BUS_GET_INFO = (0x20801802) # macro -NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_BUS_GET_INFO_V2 = (0x20801823) # macro -NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = (0x20801803) # macro -NV2080_CTRL_BUS_MAX_PCI_BARS = (8) # macro -NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH = (0x20801804) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE = (0x00000001) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS = (0x00000002) # macro -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING = (0x00000004) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED = (0x20801805) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS = (0x00000001) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS = (0x00000002) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS = (0x00000003) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS = (0x00000004) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS = (0x00000005) # macro -NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS = (0x00000006) # macro -NV2080_CTRL_CMD_BUS_MAP_BAR2 = (0x20801809) # macro -NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_BUS_UNMAP_BAR2 = (0x2080180a) # macro -NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_BUS_VERIFY_BAR2 = (0x2080180b) # macro -NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE = (0x20801812) # macro -NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE = (0x00000000) # macro -NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE = (0x00000001) # macro -NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE = (0x00000002) # macro -NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = (0x20801813) # macro -NV2080_CTRL_PEX_MAX_COUNTER_TYPES = 31 # macro -NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_BUS_PEX_COUNTER_TYPE = 0x00000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS = 0x00000001 # macro -NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT = 0x00000002 # macro -NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT = 0x00000004 # macro -NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT = 0x00000008 # macro -NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT = 0x00000010 # macro -NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT = 0x00000020 # macro -NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT = 0x00000040 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT = 0x00000080 # macro -NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT = 0x00000100 # macro -NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT = 0x00000200 # macro -NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT = 0x00000400 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS = 0x00000800 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT = 0x00001000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT = 0x00002000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT = 0x00004000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT = 0x00008000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT = 0x00010000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT = 0x00020000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT = 0x00040000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT = 0x00080000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT = 0x00100000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT = 0x00200000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT = 0x00400000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT = 0x00800000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT = 0x01000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT = 0x02000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT = 0x04000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT = 0x08000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT = 0x10000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT = 0x20000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT = 0x40000000 # macro -NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS = (0x20801814) # macro -NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x14) # macro -NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS = (0x20801815) # macro -NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS = (0x20801816) # macro -NV2080_CTRL_PEX_MAX_LANES = 16 # macro -NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID = (0x16) # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE = 0x00000000 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR = 0x00000001 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR = 0x00000002 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR = 0x00000004 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR = 0x00000008 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR = 0x00000010 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW = 0x00000020 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW = 0x00000040 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR = 0x00000080 # macro -NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR = 0x00000100 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY = (0x20801817) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x17) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY = (0x20801818) # macro -NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES = 0x00000001 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES = 0x00000002 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 = 0x00000004 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 = 0x00000008 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S = 0x00000010 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S = 0x00000020 # macro -NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S = 0x00000040 # macro -NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES = 7 # macro -NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = (0x20801819) # macro -NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS = (0x20801820) # macro -NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_BUS_GET_BFD = (0x20801821) # macro -NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE = 0x00000000 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS = 0x00000001 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE = 0x00000002 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED = 0x00000003 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED = 0x00000004 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY = 0x00000005 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED = 0x00000006 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY = 0x00000007 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 = 0x00000008 # macro -NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS = 9 # macro -NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS = (0x20801822) # macro -NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS = (0x20801824) # macro -NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID = (0x24) # macro -NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK = (0x20801825) # macro -NV2080_CTRL_BUS_MAX_NUM_GPUS = 32 # macro -NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS = (0x20801826) # macro -NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID = (0x26) # macro -NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE = (0x20801827) # macro -NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_BUS_GET_EOM_STATUS = (0x20801828) # macro -NV2080_CTRL_BUS_MAX_NUM_LANES = 32 # macro -NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = (0x20801829) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x29) # macro -NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM = 0x0 # macro -NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU = 0x1 # macro -NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P = 0x2 # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 = 0 : 0 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64 = 1 : 1 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32 = 2 : 2 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64 = 3 : 3 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32 = 4 : 4 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64 = 5 : 5 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128 = 6 : 6 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO = (0x00000000) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = (0x2080182a) # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD = 0 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX = 2 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC = 3 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC = 4 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND = 5 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR = 6 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR = 7 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH = 8 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS = 9 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD = 10 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN = 11 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX = 12 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT = 13 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID = (0x2A) # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR = 0 : 0 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR = 1 : 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION = 2 : 2 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32 = 3 : 3 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64 = 4 : 4 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128 = 5 : 5 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED = 6 : 6 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO = 0 # macro -# NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED = 7 : 7 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES = 1 # macro -NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO = 0 # macro -NV2080_CTRL_CMD_BUS_GET_C2C_INFO = (0x2080182b) # macro -NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU = 1 # macro -NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU = 2 # macro -NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS = (0x2080182c) # macro -NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING = (0x2080182e) # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID = 0 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK = 1 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE = 2 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 = 3 # macro -NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C = 4 # macro -NV2080_SET_P2P_MAPPING_UUID_LEN = 16 # macro -NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2E) # macro -NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING = (0x2080182f) # macro -NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2F) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = (0x20801830) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x30) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 = 0 : 0 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 = 1 : 1 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 = 2 : 2 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 = 3 : 3 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 = 4 : 4 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 = 5 : 5 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO = (0x00000000) # macro -# NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 = 6 : 6 # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES = (0x00000001) # macro -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO = (0x00000000) # macro -class struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS._fields_ = [ - ('pciDeviceId', ctypes.c_uint32), - ('pciSubSystemId', ctypes.c_uint32), - ('pciRevisionId', ctypes.c_uint32), - ('pciExtDeviceId', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS -NV2080_CTRL_BUS_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_BUS_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_INFO_PARAMS._fields_ = [ - ('busInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('busInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_BUS_GET_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_PARAMS -class struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS._fields_ = [ - ('busInfoListSize', ctypes.c_uint32), - ('busInfoList', struct_NVXXXX_CTRL_XXX_INFO * 52), -] - -NV2080_CTRL_BUS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_BUS_PCI_BAR_INFO(Structure): - pass - -struct_NV2080_CTRL_BUS_PCI_BAR_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_PCI_BAR_INFO._fields_ = [ - ('flags', ctypes.c_uint32), - ('barSize', ctypes.c_uint32), - ('barSizeBytes', ctypes.c_uint64), - ('barOffset', ctypes.c_uint64), -] - -NV2080_CTRL_BUS_PCI_BAR_INFO = struct_NV2080_CTRL_BUS_PCI_BAR_INFO -class struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS._fields_ = [ - ('pciBarCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pciBarInfo', struct_NV2080_CTRL_BUS_PCI_BAR_INFO * 8), -] - -NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS -class struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS._fields_ = [ - ('pcieLinkWidth', ctypes.c_uint32), - ('failingReason', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS -class struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS._fields_ = [ - ('busSpeed', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS -class struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_MAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS -class struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS -class struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('offset', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS = struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS -class struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS._fields_ = [ - ('command', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('deviceState', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS = struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS -class struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), - ('pexTotalCorrectableErrors', ctypes.c_uint32), - ('pexCorrectableErrors', ctypes.c_uint16), - ('pexTotalNonFatalErrors', ctypes.c_ubyte), - ('pexTotalFatalErrors', ctypes.c_ubyte), - ('pexTotalUnsupportedReqs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('pexCounters', ctypes.c_uint16 * 31), -] - -NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), - ('bFreezeRmCounter', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS._fields_ = [ - ('pexLaneErrorStatus', ctypes.c_uint16), - ('pexLaneCounter', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS._fields_ = [ - ('bPexLtrRegkeyOverride', ctypes.c_ubyte), - ('bPexRootPortLtrSupported', ctypes.c_ubyte), - ('bPexGpuLtrSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('pexLtrSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('pexLtrNoSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrNoSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS -class struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS._fields_ = [ - ('pexLtrSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('pexLtrNoSnoopLatencyValue', ctypes.c_uint16), - ('pexLtrNoSnoopLatencyScale', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS -class struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), - ('pexCounters', ctypes.c_uint32 * 7), -] - -NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS._fields_ = [ - ('pexCounterMask', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS -class struct_NV2080_CTRL_BUS_GET_BFD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_BFD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_BFD_PARAMS._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('deviceID', ctypes.c_uint16), - ('vendorID', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('function', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_BUS_GET_BFD_PARAMS = struct_NV2080_CTRL_BUS_GET_BFD_PARAMS -class struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('params', struct_NV2080_CTRL_BUS_GET_BFD_PARAMS * 32), - ] - -NV2080_CTRL_BUS_GET_BFD_PARAMSARR = struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR -class struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS._fields_ = [ - ('aspmDisableFlags', ctypes.c_ubyte * 9), -] - -NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS = struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS = struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS -class struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS._fields_ = [ - ('nvlinkPeerIdMask', ctypes.c_uint32 * 32), -] - -NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS = struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS -class struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS._fields_ = [ - ('eomMode', ctypes.c_ubyte), - ('eomNblks', ctypes.c_ubyte), - ('eomNerrs', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS._fields_ = [ - ('regAddress', ctypes.c_uint32), - ('laneSelectMask', ctypes.c_uint32), - ('regValue', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS -class struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS._fields_ = [ - ('eomMode', ctypes.c_ubyte), - ('eomNblks', ctypes.c_ubyte), - ('eomNerrs', ctypes.c_ubyte), - ('eomBerEyeSel', ctypes.c_ubyte), - ('eomPamEyeSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('laneMask', ctypes.c_uint32), - ('eomStatus', ctypes.c_uint16 * 32), -] - -NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS = struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS._fields_ = [ - ('capType', ctypes.c_uint32), - ('dbdf', ctypes.c_uint32), - ('atomicsCaps', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS -class struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO(Structure): - pass - -struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO._fields_ = [ - ('bSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('attributes', ctypes.c_uint32), -] - -NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO = struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS._fields_ = [ - ('capType', ctypes.c_uint32), - ('dbdf', ctypes.c_uint32), - ('atomicOp', struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO * 13), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS._fields_ = [ - ('bIsLinkUp', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('nrLinks', ctypes.c_uint32), - ('maxNrLinks', ctypes.c_uint32), - ('linkMask', ctypes.c_uint32), - ('perLinkBwMBps', ctypes.c_uint32), - ('perLinkLaneWidth', ctypes.c_uint32), - ('remoteType', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS -class struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), -] - -NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS = struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS -class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bEgmPeer', ctypes.c_ubyte), - ('bSpaAccessOnly', ctypes.c_ubyte), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS -class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS._fields_ = [ - ('connectionType', ctypes.c_uint32), - ('peerId', ctypes.c_uint32), - ('bUseUuid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('remoteGpuId', ctypes.c_uint32), - ('remoteGpuUuid', ctypes.c_ubyte * 16), -] - -NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS -class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS._fields_ = [ - ('atomicsCaps', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS -NV2080_CTRL_CMD_CE_GET_CAPS = (0x20802a01) # macro -NV2080_CTRL_CE_CAPS_TBL_SIZE = 2 # macro -NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_CE_GET_CAPS_V2 = (0x20802a03) # macro -NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x3) # macro -# def NV2080_CTRL_CE_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV2080_CTRL_CE_CAPS_CE_GRCE = 0 : 0x01 # macro -# NV2080_CTRL_CE_CAPS_CE_SHARED = 0 : 0x02 # macro -# NV2080_CTRL_CE_CAPS_CE_SYSMEM_READ = 0 : 0x04 # macro -# NV2080_CTRL_CE_CAPS_CE_SYSMEM_WRITE = 0 : 0x08 # macro -# NV2080_CTRL_CE_CAPS_CE_NVLINK_P2P = 0 : 0x10 # macro -# NV2080_CTRL_CE_CAPS_CE_SYSMEM = 0 : 0x20 # macro -# NV2080_CTRL_CE_CAPS_CE_P2P = 0 : 0x40 # macro -# NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED = 0 : 0x80 # macro -# NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL = 1 : 0x01 # macro -# NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL = 1 : 0x02 # macro -# NV2080_CTRL_CE_CAPS_CE_CC_SECURE = 1 : 0x04 # macro -# NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED = 1 : 0x08 # macro -NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = (0x20802a02) # macro -NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG = (0x20802a04) # macro -NV2080_CTRL_MAX_PCES = 32 # macro -NV2080_CTRL_MAX_GRCES = 4 # macro -NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS = (0x20802a05) # macro -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE = 0xf # macro -NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB = (0x20802a06) # macro -NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS = (0x20802a07) # macro -NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE = (0x20802a08) # macro -NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK = (0x20802a09) # macro -NV2080_CTRL_CE_MAX_HSHUBS = 32 # macro -NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_CE_GET_ALL_CAPS = (0x20802a0a) # macro -NV2080_CTRL_MAX_CES = 64 # macro -NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID = (0xa) # macro -NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS = (0x20802a0b) # macro -NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0xb) # macro -NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO = (0x20802a0c) # macro -NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID = (0xc) # macro -NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 = (0x20802a0d) # macro -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID = (0xd) # macro -NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 = (0x20802a0e) # macro -NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID = (0xe) # macro -NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE = (0x20802a0f) # macro -NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID = (0xf) # macro -NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK = (0x20802a11) # macro -NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED = (0x20802a12) # macro -NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID = (0x12) # macro -class struct_NV2080_CTRL_CE_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CAPS_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('capsTblSize', ctypes.c_uint32), - ('capsTbl', ctypes.POINTER(None)), -] - -NV2080_CTRL_CE_GET_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_PARAMS -class struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('capsTbl', ctypes.c_ubyte * 2), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_CE_GET_CAPS_V2_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS -class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('pceMask', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS -class struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('pceLceMap', ctypes.c_uint32 * 32), - ('grceSharedLceMap', ctypes.c_uint32 * 4), -] - -NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS = struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS -class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS._fields_ = [ - ('pceLceMap', ctypes.c_uint32 * 32), - ('grceConfig', ctypes.c_uint32 * 4), - ('exposeCeMask', ctypes.c_uint32), - ('bUpdateNvlinkPceLce', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS -class struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS._fields_ = [ - ('stubbedCeMask', ctypes.c_uint32), -] - -NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS = struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS -NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS -class struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS._fields_ = [ - ('size', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS -class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS._fields_ = [ - ('hshubPceMasks', ctypes.c_uint32 * 32), - ('fbhubPceMask', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS -class struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 2 * 64), - ('present', ctypes.c_uint64), -] - -NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS -NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS -class struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS._fields_ = [ - ('ceEngineType', ctypes.c_uint32), - ('shimInstance', ctypes.c_uint32), - ('shimLocalLceIdx', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS = struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS -class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS._fields_ = [ - ('pceLceMap', ctypes.c_uint32 * 32), - ('grceConfig', ctypes.c_uint32 * 4), - ('exposeCeMask', ctypes.c_uint32), - ('bUpdateNvlinkPceLce', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('shimInstance', ctypes.c_uint32), -] - -NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS -class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS._fields_ = [ - ('connectingHubPceMasks', ctypes.c_uint32 * 32), - ('fbhubPceMask', ctypes.c_uint32), - ('shimInstance', ctypes.c_uint32), -] - -NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS - -# values for enumeration 'NV2080_CTRL_CE_LCE_TYPE' -NV2080_CTRL_CE_LCE_TYPE__enumvalues = { - 1: 'NV2080_CTRL_CE_LCE_TYPE_PCIE', - 2: 'NV2080_CTRL_CE_LCE_TYPE_DECOMP', - 3: 'NV2080_CTRL_CE_LCE_TYPE_SCRUB', - 4: 'NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', - 5: 'NV2080_CTRL_CE_LCE_TYPE_C2C', - 6: 'NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', - 7: 'NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', - 8: 'NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', - 9: 'NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', -} -NV2080_CTRL_CE_LCE_TYPE_PCIE = 1 -NV2080_CTRL_CE_LCE_TYPE_DECOMP = 2 -NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3 -NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4 -NV2080_CTRL_CE_LCE_TYPE_C2C = 5 -NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = 6 -NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = 7 -NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = 8 -NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = 9 -NV2080_CTRL_CE_LCE_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS._fields_ = [ - ('lceType', NV2080_CTRL_CE_LCE_TYPE), - ('numPces', ctypes.c_uint32), - ('numLces', ctypes.c_uint32), - ('supportedPceMask', ctypes.c_uint32), - ('supportedLceMask', ctypes.c_uint32), - ('pcePerHshub', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS = struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS -class struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS._fields_ = [ - ('decompLceMask', ctypes.c_uint64), - ('shimInstance', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS -class struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS._fields_ = [ - ('lceIndex', ctypes.c_uint32), - ('bDecompEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS = struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS -NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS = 0x00000001 # macro -NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL = 0x00000002 # macro -# NV2080_GPUMON_PID_INVALID = ((NvU32)(~0)) # macro -class struct_NV2080_CTRL_GPUMON_SAMPLE(Structure): - pass - -struct_NV2080_CTRL_GPUMON_SAMPLE._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPUMON_SAMPLE(Struct): pass struct_NV2080_CTRL_GPUMON_SAMPLE._fields_ = [ - ('timeStamp', ctypes.c_uint64), + ('timeStamp', NvU64), ] - NV2080_CTRL_GPUMON_SAMPLE = struct_NV2080_CTRL_GPUMON_SAMPLE -class struct_NV2080_CTRL_GPUMON_SAMPLES(Structure): - pass - -struct_NV2080_CTRL_GPUMON_SAMPLES._pack_ = 1 # source:False +class struct_NV2080_CTRL_GPUMON_SAMPLES(Struct): pass struct_NV2080_CTRL_GPUMON_SAMPLES._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bufSize', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('tracker', ctypes.c_uint32), - ('pSamples', ctypes.POINTER(None)), + ('type', NvU8), + ('bufSize', NvU32), + ('count', NvU32), + ('tracker', NvU32), + ('pSamples', NvP64), ] - NV2080_CTRL_GPUMON_SAMPLES = struct_NV2080_CTRL_GPUMON_SAMPLES -NV2080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x20802502) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0x2) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS = 0 : 0 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO = 1 : 1 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY = 2 : 2 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE = 3 : 3 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB = 4 : 4 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV = 5 : 5 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG = 6 : 6 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD = 7 : 7 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION = 8 : 8 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON = 9 : 9 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS = 10 : 10 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE = (0x00000001) # macro -# NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR = 11 : 11 # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE = (0x00000000) # macro -NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE = (0x00000001) # macro -NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE = (0x000000000) # macro -NV2080_CTRL_DMA_INFO_INDEX_MAX = (0x000000000) # macro -NV2080_CTRL_CMD_DMA_GET_INFO = (0x20802503) # macro -NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES = (256) # macro -NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -class struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), - ('engine', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), -] - -NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS -NV2080_CTRL_DMA_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_DMA_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_DMA_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_DMA_GET_INFO_PARAMS._fields_ = [ - ('dmaInfoTblSize', ctypes.c_uint32), - ('dmaInfoTbl', struct_NVXXXX_CTRL_XXX_INFO * 256), -] - -NV2080_CTRL_DMA_GET_INFO_PARAMS = struct_NV2080_CTRL_DMA_GET_INFO_PARAMS -class struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO(Structure): - pass - -struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO._fields_ = [ - ('srcAddr', ctypes.c_uint32), - ('dstAddr', ctypes.c_uint32), - ('relComptagIndex', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO = struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO -NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD = (0x20803a01) # macro -NV2080_CTRL_DMABUF_MAX_HANDLES = 128 # macro -NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = (0x00000000) # macro -NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = (0x00000001) # macro -NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID = (0x1) # macro -class struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO(Structure): - pass - -struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_DMABUF_MEM_HANDLE_INFO = struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO -class struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS._fields_ = [ - ('fd', ctypes.c_int32), - ('totalObjects', ctypes.c_uint32), - ('numObjects', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('totalSize', ctypes.c_uint64), - ('mappingType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('handles', struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO * 128), -] - -NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS = struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS -NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS = (0x20803400) # macro -NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID = (0x0) # macro -NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS = (0x20803401) # macro -NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID = (0x1) # macro -class struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS._fields_ = [ - ('sramParityUncorrectedUnique', ctypes.c_uint64), - ('sramSecDedUncorrectedUnique', ctypes.c_uint64), - ('sramCorrectedUnique', ctypes.c_uint64), - ('dramUncorrectedTotal', ctypes.c_uint64), - ('dramCorrectedTotal', ctypes.c_uint64), - ('lastClearedTimestamp', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sramBucketL2', ctypes.c_uint64), - ('sramBucketSM', ctypes.c_uint64), - ('sramBucketPcie', ctypes.c_uint64), - ('sramBucketFirmware', ctypes.c_uint64), - ('sramBucketOther', ctypes.c_uint64), - ('sramErrorThresholdExceeded', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS = struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS -class struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS._fields_ = [ - ('sramCorUni', ctypes.c_uint64), - ('sramUncParityUni', ctypes.c_uint64), - ('sramUncSecDedUni', ctypes.c_uint64), - ('dramCorTot', ctypes.c_uint64), - ('dramUncTot', ctypes.c_uint64), -] - -NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS = struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS -NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x20800301) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) # macro -NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) # macro -NV2080_EVENT_DSTATE_XUSB_D0 = (0x00000000) # macro -NV2080_EVENT_DSTATE_XUSB_D3 = (0x00000003) # macro -NV2080_EVENT_DSTATE_XUSB_INVALID = (0xFFFFFFFF) # macro -NV2080_EVENT_DSTATE_PPC_D0 = (0x00000000) # macro -NV2080_EVENT_DSTATE_PPC_D3 = (0x00000003) # macro -NV2080_EVENT_DSTATE_PPC_INVALID = (0xFFFFFFFF) # macro -NV2080_CTRL_CMD_EVENT_SET_TRIGGER = (0x20800302) # macro -NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES = (0x20800303) # macro -NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED = 0 # macro -NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING = 1 # macro -NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR = 2 # macro -NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY = (0x20800304) # macro -NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI = (0x20800305) # macro -NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION = (0x20800306) # macro -NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO = (0x20800308) # macro -NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF = (0x20800309) # macro -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF = (0x2080030a) # macro -NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xA) # macro -class struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [ - ('event', ctypes.c_uint32), - ('action', ctypes.c_uint32), - ('bNotifyState', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('info32', ctypes.c_uint32), - ('info16', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS - -# values for enumeration 'NV2080_EVENT_HDACODEC_DSTATE' -NV2080_EVENT_HDACODEC_DSTATE__enumvalues = { - 0: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', - 1: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', - 2: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', - 3: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', - 4: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', - 5: 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', -} -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = 0 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = 1 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = 2 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = 3 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = 4 -NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = 5 -NV2080_EVENT_HDACODEC_DSTATE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS = struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS -class struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS._fields_ = [ - ('hSemMemory', ctypes.c_uint32), - ('semOffset', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS -class struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS._fields_ = [ - ('guestMSIAddr', ctypes.c_uint64), - ('guestMSIData', ctypes.c_uint32), - ('hSemMemory', ctypes.c_uint32), - ('isReset', ctypes.c_ubyte), - ('vgpuUuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 7), - ('domainId', ctypes.c_uint64), -] - -NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS = struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS -class struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS._fields_ = [ - ('hSemMemory', ctypes.c_uint32), - ('isSemaMemValidationEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS -class struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS._fields_ = [ - ('hEvent', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS = struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS - -# values for enumeration 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD' -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD__enumvalues = { - 0: 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', - 1: 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', - 2: 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', -} -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = 0 -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = 1 -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = 2 -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('recordSize', ctypes.c_uint32), - ('levelOfDetail', NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD), - ('eventFilter', ctypes.c_uint32), - ('bAllUsers', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS -class struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS._fields_ = [ - ('hEventBuffer', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('tracepointMask', ctypes.c_uint64), - ('gspLoggingBufferSize', ctypes.c_uint32), - ('gspLoggingBufferWatermark', ctypes.c_uint32), -] - -NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS -NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT = (0x00000000) # macro -NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE = (0x00000001) # macro -NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE = (0x00000002) # macro -NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT = (0x00000003) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT = (0x00000004) # macro -NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE = (0x00000005) # macro -NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT = (0x00000006) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE = (0x00000007) # macro -NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE = (0x00000008) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE = (0x00000009) # macro -NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE = (0x0000000A) # macro -NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH = (0x0000000B) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_CFG = (0x0000000C) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE = (0x0000000D) # macro -NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT = (0x0000000E) # macro -NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB = (0x00000010) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB = (0x00000011) # macro -NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB = (0x00000012) # macro -NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB = (0x00000013) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK = (0x00000014) # macro -NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE = (0x00000015) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE = (0x00000016) # macro -NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION = (0x00000017) # macro -NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN = (0x00000018) # macro -NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT = (0x00000019) # macro -NV2080_CTRL_FB_INFO_INDEX_FBP_MASK = (0x0000001A) # macro -NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE = (0x0000001B) # macro -NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID = (0x0000001C) # macro -NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE = (0x0000001D) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_START = (0x0000001E) # macro -NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE = (0x0000001F) # macro -NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE = (0x00000020) # macro -NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T = (0x00000021) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT = (0x00000022) # macro -NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT = (0x00000023) # macro -NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE = (0x00000024) # macro -NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE = (0x00000025) # macro -NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE = (0x00000026) # macro -NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE = (0x00000027) # macro -NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED = (0x00000028) # macro -NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE = (0x00000029) # macro -NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT = (0x0000002A) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_MASK = (0x0000002B) # macro -NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED = (0x0000002C) # macro -NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED = (0x0000002D) # macro -NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED = (0x0000002E) # macro -NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED = (0x0000002F) # macro -NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE = (0x00000030) # macro -NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT = (0x00000031) # macro -NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB = (0x00000032) # macro -NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB = (0x00000033) # macro -NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB = (0x00000034) # macro -NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE = (0x00000035) # macro -NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB = (0x00000036) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 = ((0x00000014)) # macro -NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 = (0x00000037) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 = ((0x0000002B)) # macro -NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 = (0x00000038) # macro -NV2080_CTRL_FB_INFO_MAX_LIST_SIZE = (0x00000039) # macro -NV2080_CTRL_FB_INFO_INDEX_MAX = (0x38) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN = (0x00000000) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM = (0x00000001) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 = (0x00000002) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 = (0x00000003) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 = (0x00000003) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 = (0x00000004) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 = (0x00000005) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 = (0x00000006) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 = (0x00000007) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 = (0x00000007) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 = (0x00000008) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 = (0x00000009) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 = (0x0000000C) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 = (0x0000000D) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 = (0x0000000E) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X = (0x00000010) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 = (0x00000011) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X = (0x00000012) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 = (0x00000013) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 = (0x00000014) # macro -NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 = (0x00000015) # macro -NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED = (0x00000000) # macro -NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED = (0x00000001) # macro -NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED = (0x00000002) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG = (0x00000001) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA = (0x00000002) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA = (0x00000003) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON = (0x00000004) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA = (0x00000005) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX = (0x00000006) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL = (0x00000007) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND = (0x00000008) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT = (0x00000009) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON = (0x0000000F) # macro -NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN = (0xFFFFFFFF) # macro -NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED = (0x00000000) # macro -NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED = (0x00000001) # macro -NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED = (0x00000002) # macro -NV2080_CTRL_CMD_FB_GET_INFO = (0x20801301) # macro -NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_FB_GET_INFO_V2 = (0x20801303) # macro -NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET = (0x20801310) # macro -NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED = (0x2080130c) # macro -NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE = (0x00000000) # macro -NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET = (0x00000001) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL = (0x2080130d) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID = (0xD) # macro -# NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK = 0 : 0 # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO = (0x00000000) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES = (0x00000001) # macro -# NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE = 1 : 1 # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO = (0x00000000) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES = (0x00000001) # macro -# NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH = 2 : 2 # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO = (0x00000000) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES = (0x00000001) # macro -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = (0x2080130e) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES = 500 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID = (0xE) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE = 1 : 0 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY = (0x00000001) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY = (0x00000002) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK = 2 : 2 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES = (0x00000001) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE = 3 : 3 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES = (0x00000001) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE = 4 : 4 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE = (0x00000001) # macro -# NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH = 5 : 5 # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO = (0x00000000) # macro -NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES = (0x00000001) # macro -NV2080_CTRL_CMD_FB_IS_KIND = (0x20801313) # macro -NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED = (0x00000000) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE = (0x00000001) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 = (0x00000002) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 = (0x00000003) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 = (0x00000004) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC = (0x00000005) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 = (0x00000006) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 = (0x00000007) # macro -NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 = (0x00000008) # macro -NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = (0x20801315) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL = (0x00000000) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING = (0x00000001) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED = (0x00000002) # macro -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE = (0x00000003) # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = (0x20801320) # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES = 17 # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES = 16 # macro -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_FB_OFFLINE_PAGES = (0x20801321) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES = (0x00000040) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS = (0xffffffffffffffff) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K = (0x00000000) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K = (0x00000001) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE = (0x00000004) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK = (0x00000000) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT = (0x00000001) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL = (0x00000003) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR = (0x00000004) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE = (0x00000002) # macro -NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE = (0x00000004) # macro -NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = (0x20801322) # macro -# NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE = 0 : 0 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE = 0 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE = 1 # macro -# NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE = 1 : 1 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE = 0 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE = 1 # macro -NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_FB_QUERY_ACR_REGION = (0x20801325) # macro -NV2080_CTRL_CMD_FB_ACR_CLIENT_ID = 2 # macro -NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES = (0x20801326) # macro -NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x26) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO = (0x20801327) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP = (0x20801328) # macro -NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT = (0x20801329) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS = (0x2080132a) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS = (0x2080132b) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB = (0x2080132c) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB = (0x2080132d) # macro -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 = (0x20801335) # macro -NV2080_CTRL_CMD_FB_GET_AMAP_CONF = (0x20801336) # macro -NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_FB_CBC_OP = (0x20801337) # macro -NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION = (0x20801338) # macro -NV2080_MAX_CTAGS_FOR_CBC_EVICTION = 0x7F # macro -NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE = (0x20801339) # macro -NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_FB_FREE_TILE = (0x2080133a) # macro -NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID = (0x3A) # macro -NV2080_CTRL_CMD_FB_SETUP_VPR_REGION = (0x2080133b) # macro -NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID = (0x3B) # macro -NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES = (0x2080133c) # macro -NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x3C) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO = (0x2080133d) # macro -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID = (0x3D) # macro -NV2080_CTRL_CMD_FB_SET_RRD = (0x2080133e) # macro -# NV2080_CTRL_FB_SET_RRD_RESET_VALUE = (~((NvU32)0)) # macro -NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID = (0x3E) # macro -NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE = (0xff) # macro -NV2080_CTRL_CMD_FB_SET_READ_LIMIT = (0x2080133f) # macro -NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE = (0xff) # macro -NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID = (0x3F) # macro -NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT = (0x20801340) # macro -NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE = (0xff) # macro -NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID = (0x40) # macro -NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING = (0x20801341) # macro -NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID = (0x41) # macro -NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT = (0x20801342) # macro -NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS = (4) # macro -NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR = (0x20801343) # macro -NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x43) # macro -# NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING = 0 : 0 # macro -NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE = 0 # macro -NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE = 1 # macro -NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD = (0x00000002) # macro -NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD = (0x00000003) # macro -NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS = (0x00000200) # macro -NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS = (0x20801344) # macro -# NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING = 0 : 0 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE = 0 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE = 1 # macro -# NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE = 1 : 1 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE = 0 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE = 1 # macro -NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE = 24 # macro -NV2080_CTRL_FB_FS_INFO_INVALID_QUERY = 0x0 # macro -NV2080_CTRL_FB_FS_INFO_FBP_MASK = 0x1 # macro -NV2080_CTRL_FB_FS_INFO_LTC_MASK = 0x2 # macro -NV2080_CTRL_FB_FS_INFO_LTS_MASK = 0x3 # macro -NV2080_CTRL_FB_FS_INFO_FBPA_MASK = 0x4 # macro -NV2080_CTRL_FB_FS_INFO_ROP_MASK = 0x5 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK = 0x6 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK = 0x7 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK = 0x8 # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK = 0x9 # macro -NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK = 0xA # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK = 0xB # macro -NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP = 0xC # macro -NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK = 0xD # macro -NV2080_CTRL_FB_FS_INFO_PAC_MASK = 0xE # macro -NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK = 0xF # macro -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK = 0x10 # macro -NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK = 0x11 # macro -NV2080_CTRL_FB_FS_INFO_MAX_QUERIES = 120 # macro -NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID = (0x46) # macro -NV2080_CTRL_CMD_FB_GET_FS_INFO = (0x20801346) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS = (0x0) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW = (0x1) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS = (0x2) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW = (0x3) # macro -NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS = (0x4) # macro -NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM = (0x20801347) # macro -NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES = (0x20801348) # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES = 512 # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES = 64 # macro -NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x48) # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID = (0x00000000) # macro -NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE = (0x00000001) # macro -NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO = (0x20801349) # macro -# NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE = 4 : 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM = 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM = 1 # macro -# NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED = 5 : 5 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE = 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE = 1 # macro -# NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER = 6 : 6 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE = 0 # macro -NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE = 1 # macro -NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID = (0x49) # macro -NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS = (0x20801350) # macro -NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID = (0x50) # macro -NV2080_CTRL_CMD_FB_GET_NUMA_INFO = (0x20801351) # macro -NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 # macro -NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID = (0x51) # macro -NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = (0x20801352) # macro -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED = (0x00000001) # macro -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED = (0x00000002) # macro -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID = (0x52) # macro -NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE = (0x20801353) # macro -NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_FB_STATS_MAX_OWNER = 200 # macro -NV2080_CTRL_CMD_FB_STATS_GET = (0x2080132a) # macro -NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID = (0x2A) # macro -NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO = (0x20801354) # macro -NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = (0x20801355) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED = (0x00000000) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION = (0x20801356) # macro -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE = (0x00000000) # macro -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE = (0x00000001) # macro -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_CMD_FB_GET_STATUS = (0x20801357) # macro -NV2080_CTRL_FB_STATUS_FAILED = (0x00000000) # macro -NV2080_CTRL_FB_STATUS_READY = (0x00000001) # macro -NV2080_CTRL_FB_STATUS_PENDING = (0x00000002) # macro -NV2080_CTRL_FB_STATUS_NOT_APPLICABLE = (0x00000003) # macro -NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID = (0x57) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = (0x20801358) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED = (0x00000000) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID = (0x58) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = (0x20801359) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED = (0x00000000) # macro -NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED = (0x00000001) # macro -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID = (0x59) # macro -NV2080_CTRL_FB_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_FB_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_INFO_PARAMS._fields_ = [ - ('fbInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbInfoList', ctypes.POINTER(None)), -] - -NV2080_CTRL_FB_GET_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS._fields_ = [ - ('fbInfoListSize', ctypes.c_uint32), - ('fbInfoList', struct_NVXXXX_CTRL_XXX_INFO * 57), -] - -NV2080_CTRL_FB_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS -class struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS._fields_ = [ - ('cpuVirtAddress', ctypes.POINTER(None)), - ('gpuVirtAddress', ctypes.c_uint64), -] - -NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS = struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS -class struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('driveStrengthRiseCount', ctypes.c_uint32), - ('driveStrengthFallCount', ctypes.c_uint32), - ('driveStrengthTermCount', ctypes.c_uint32), - ('slewStrengthRiseCount', ctypes.c_uint32), - ('slewStrengthFallCount', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS = struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS -class struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS = struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS -class struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS._fields_ = [ - ('addressArray', ctypes.c_uint64 * 500), - ('addressArraySize', ctypes.c_uint32), - ('addressAlign', ctypes.c_uint32), - ('memBlockSizeBytes', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS = struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS -class struct_NV2080_CTRL_FB_IS_KIND_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_IS_KIND_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_IS_KIND_PARAMS._fields_ = [ - ('operation', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('result', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FB_IS_KIND_PARAMS = struct_NV2080_CTRL_FB_IS_KIND_PARAMS -class struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), - ('writeMode', ctypes.c_uint32), - ('bypassMode', ctypes.c_uint32), - ('rcmState', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS -NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = ctypes.c_ubyte * 17 -class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._fields_ = [ - ('base', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('reserved', ctypes.c_uint64), - ('performance', ctypes.c_uint32), - ('supportCompressed', ctypes.c_ubyte), - ('supportISO', ctypes.c_ubyte), - ('bProtected', ctypes.c_ubyte), - ('blackList', ctypes.c_ubyte * 17), -] - -NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO -class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._fields_ = [ - ('numFBRegions', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbRegion', struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO * 16), -] - -NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS -class struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO(Structure): - pass - -struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO._fields_ = [ - ('pageAddressWithEccOn', ctypes.c_uint64), - ('pageAddressWithEccOff', ctypes.c_uint64), - ('rbcAddress', ctypes.c_uint32), - ('source', ctypes.c_uint32), - ('status', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), -] - -NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO -class struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS._fields_ = [ - ('offlined', struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64), - ('pageSize', ctypes.c_uint32), - ('validEntries', ctypes.c_uint32), - ('numPagesAdded', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS = struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS -class struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS._fields_ = [ - ('offlined', struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64), - ('validEntries', ctypes.c_uint32), - ('bRetirementPending', ctypes.c_ubyte), - ('retirementPending', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE' -NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', - 1: 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', - 2: 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', -} -NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0 -NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = 1 -NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = 2 -NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE' -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', - 1: 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', -} -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = 0 -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = 1 -NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE = ctypes.c_uint32 # enum -class struct_ACR_REQUEST_PARAMS(Structure): - pass - -struct_ACR_REQUEST_PARAMS._pack_ = 1 # source:False -struct_ACR_REQUEST_PARAMS._fields_ = [ - ('clientId', ctypes.c_uint32), - ('reqReadMask', ctypes.c_uint32), - ('reqWriteMask', ctypes.c_uint32), - ('regionSize', ctypes.c_uint32), -] - -ACR_REQUEST_PARAMS = struct_ACR_REQUEST_PARAMS -class struct_ACR_REGION_ID_PROP(Structure): - pass - -struct_ACR_REGION_ID_PROP._pack_ = 1 # source:False -struct_ACR_REGION_ID_PROP._fields_ = [ - ('regionId', ctypes.c_uint32), - ('readMask', ctypes.c_uint32), - ('writeMask', ctypes.c_uint32), - ('regionSize', ctypes.c_uint32), - ('clientMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physicalAddress', ctypes.c_uint64), -] - -ACR_REGION_ID_PROP = struct_ACR_REGION_ID_PROP -class struct_ACR_STATUS_PARAMS(Structure): - pass - -struct_ACR_STATUS_PARAMS._pack_ = 1 # source:False -struct_ACR_STATUS_PARAMS._fields_ = [ - ('allocStatus', ctypes.c_uint32), - ('regionId', ctypes.c_uint32), - ('physicalAddress', ctypes.c_uint64), -] - -ACR_STATUS_PARAMS = struct_ACR_STATUS_PARAMS -class struct_ACR_REGION_HANDLE(Structure): - pass - -struct_ACR_REGION_HANDLE._pack_ = 1 # source:False -struct_ACR_REGION_HANDLE._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hParent', ctypes.c_uint32), - ('hMemory', ctypes.c_uint32), - ('hClass', ctypes.c_uint32), - ('hDevice', ctypes.c_uint32), -] - -ACR_REGION_HANDLE = struct_ACR_REGION_HANDLE -class struct_ACR_FALCON_LS_STATUS(Structure): - pass - -struct_ACR_FALCON_LS_STATUS._pack_ = 1 # source:False -struct_ACR_FALCON_LS_STATUS._fields_ = [ - ('falconId', ctypes.c_uint16), - ('bIsInLs', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -ACR_FALCON_LS_STATUS = struct_ACR_FALCON_LS_STATUS -class struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('queryType', NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE), - ('errorCode', NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE), - ('acrRegionIdProp', ACR_REGION_ID_PROP), - ('clientReq', ACR_REQUEST_PARAMS), - ('clientReqStatus', ACR_STATUS_PARAMS), - ('handle', ACR_REGION_HANDLE), - ('falconStatus', ACR_FALCON_LS_STATUS), - ] - -NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS -class struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS._fields_ = [ - ('sourceMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS._fields_ = [ - ('pCompBitCopyObj', ctypes.POINTER(None)), - ('pSwizzleParams', ctypes.POINTER(None)), -] - -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('ltcMask', ctypes.c_uint32), - ('ltcCount', ctypes.c_uint32), - ('ltsMask', ctypes.c_uint32), - ('ltsCount', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS = struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS._fields_ = [ - ('CBCBaseAddress', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('backingStorePA', ctypes.c_uint64), - ('backingStoreVA', ctypes.POINTER(ctypes.c_ubyte)), - ('backingStoreChunkPA', ctypes.c_uint64), - ('backingStoreChunkVA', ctypes.POINTER(ctypes.c_ubyte)), - ('backingStoreChunkSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('cacheWriteBitMap', ctypes.POINTER(ctypes.c_ubyte)), - ('backingStoreChunkOverfetch', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), - ('PageSizeSrc', ctypes.c_uint32), - ('PageSizeDest', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS._fields_ = [ - ('fcbits', ctypes.POINTER(ctypes.c_uint32)), - ('compbits', ctypes.POINTER(ctypes.c_uint32)), - ('dataPhysicalStart', ctypes.c_uint64), - ('surfaceOffset', ctypes.c_uint64), - ('comptagLine', ctypes.c_uint32), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS._fields_ = [ - ('fcbits', ctypes.c_uint32), - ('compbits', ctypes.c_uint32), - ('writeFc', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('dataPhysicalStart', ctypes.c_uint64), - ('surfaceOffset', ctypes.c_uint64), - ('comptagLine', ctypes.c_uint32), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS._fields_ = [ - ('SrcDataPhysicalStart', ctypes.c_uint64), - ('SrcComptagLine', ctypes.c_uint32), - ('page64KB', ctypes.c_uint32), - ('compbitBuffer', ctypes.POINTER(ctypes.c_uint32)), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS._fields_ = [ - ('DstDataPhysicalStart', ctypes.c_uint64), - ('DstComptagLine', ctypes.c_uint32), - ('page64KB', ctypes.c_uint32), - ('compbitBuffer', ctypes.POINTER(ctypes.c_uint32)), - ('upper64KBCompbitSel', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS -class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS._fields_ = [ - ('bForceBar1', ctypes.c_ubyte), -] - -NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS._fields_ = [ - ('pAmapConfParams', ctypes.POINTER(None)), - ('pCbcSwizzleParams', ctypes.POINTER(None)), -] - -NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS - -# values for enumeration 'CTRL_CMD_FB_CBC_OP' -CTRL_CMD_FB_CBC_OP__enumvalues = { - 0: 'CTRL_CMD_FB_CBC_OP_CLEAN', - 1: 'CTRL_CMD_FB_CBC_OP_INVALIDATE', -} -CTRL_CMD_FB_CBC_OP_CLEAN = 0 -CTRL_CMD_FB_CBC_OP_INVALIDATE = 1 -CTRL_CMD_FB_CBC_OP = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fbCBCOp', CTRL_CMD_FB_CBC_OP), - ] - -NV2080_CTRL_CMD_FB_CBC_OP_PARAMS = struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS -class struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS._fields_ = [ - ('pCompTags', ctypes.c_uint32 * 127), - ('numCompTags', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS = struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS -class struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS._fields_ = [ - ('attr', ctypes.c_uint32), - ('attr2', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('ctagOffset', ctypes.c_uint32), - ('hwResId', ctypes.c_uint32), - ('retCompTagLineMin', ctypes.c_uint32), - ('retCompTagLineMax', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS = struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS -class struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS._fields_ = [ - ('hwResId', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS = struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS - -# values for enumeration 'NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE' -NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_SET_VPR', -} -NV2080_CTRL_CMD_FB_SET_VPR = 0 -NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_CMD_FB_VPR_ERROR_CODE' -NV2080_CTRL_CMD_FB_VPR_ERROR_CODE__enumvalues = { - 0: 'NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', - 1: 'NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', -} -NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = 0 -NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = 1 -NV2080_CTRL_CMD_FB_VPR_ERROR_CODE = ctypes.c_uint32 # enum -class struct_VPR_REQUEST_PARAMS(Structure): - pass - -struct_VPR_REQUEST_PARAMS._pack_ = 1 # source:False -struct_VPR_REQUEST_PARAMS._fields_ = [ - ('startAddr', ctypes.c_uint32), - ('size', ctypes.c_uint32), -] - -VPR_REQUEST_PARAMS = struct_VPR_REQUEST_PARAMS -class struct_VPR_STATUS_PARAMS(Structure): - pass - -struct_VPR_STATUS_PARAMS._pack_ = 1 # source:False -struct_VPR_STATUS_PARAMS._fields_ = [ - ('status', ctypes.c_uint32), -] - -VPR_STATUS_PARAMS = struct_VPR_STATUS_PARAMS -class struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('requestType', NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE), - ('requestParams', VPR_REQUEST_PARAMS), - ('statusParams', VPR_STATUS_PARAMS), - ] - -NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS -PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS) -class struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS._fields_ = [ - ('offlinedPages', ctypes.c_uint32 * 64), - ('pageSize', ctypes.c_uint32), - ('validEntries', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS._fields_ = [ - ('defaultPageSize', ctypes.c_uint32), - ('comptagsPerCacheLine', ctypes.c_uint32), - ('unpackedComptagLinesPerCacheLine', ctypes.c_uint32), - ('compCacheLineSizePerLTC', ctypes.c_uint32), - ('unpackedCompCacheLineSizePerLTC', ctypes.c_uint32), - ('slicesPerLTC', ctypes.c_uint32), - ('numActiveLTCs', ctypes.c_uint32), - ('familyName', ctypes.c_uint32), - ('chipName', ctypes.c_uint32), - ('bitsPerRAMEntry', ctypes.c_uint32), - ('ramBankWidth', ctypes.c_uint32), - ('bitsPerComptagLine', ctypes.c_uint32), - ('ramEntriesPerCompCacheLine', ctypes.c_uint32), - ('comptagLineSize', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS -class struct_NV2080_CTRL_FB_SET_RRD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_SET_RRD_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_SET_RRD_PARAMS._fields_ = [ - ('rrd', ctypes.c_uint32), -] - -NV2080_CTRL_FB_SET_RRD_PARAMS = struct_NV2080_CTRL_FB_SET_RRD_PARAMS -class struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS._fields_ = [ - ('limit', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS -NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS -NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS -class struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS = struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS -class struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS._fields_ = [ - ('alignType', ctypes.c_uint32), - ('alignAttr', ctypes.c_uint32), - ('alignInputFlags', ctypes.c_uint32), - ('alignHead', ctypes.c_uint32), - ('alignSize', ctypes.c_uint64), - ('alignHeight', ctypes.c_uint32), - ('alignWidth', ctypes.c_uint32), - ('alignPitch', ctypes.c_uint32), - ('alignPad', ctypes.c_uint32), - ('alignMask', ctypes.c_uint32), - ('alignOutputFlags', ctypes.c_uint32 * 4), - ('alignBank', ctypes.c_uint32 * 4), - ('alignKind', ctypes.c_uint32), - ('alignAdjust', ctypes.c_uint32), - ('alignAttr2', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS = struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS -class struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS._fields_ = [ - ('cbcBaseAddress', ctypes.c_uint32), - ('compCacheLineSize', ctypes.c_uint32), - ('backingStoreStartPA', ctypes.c_uint64), - ('backingStoreAllocPA', ctypes.c_uint64), - ('backingStoreChunkOverfetch', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS -class struct_NV2080_CTRL_FB_REMAP_ENTRY(Structure): - pass - -struct_NV2080_CTRL_FB_REMAP_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_REMAP_ENTRY._fields_ = [ - ('remapRegVal', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), - ('fbpa', ctypes.c_ubyte), - ('sublocation', ctypes.c_ubyte), - ('source', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_REMAP_ENTRY = struct_NV2080_CTRL_FB_REMAP_ENTRY -class struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS._fields_ = [ - ('entryCount', ctypes.c_uint32), - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('entries', struct_NV2080_CTRL_FB_REMAP_ENTRY * 512), -] - -NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS = struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS._fields_ = [ - ('data', ctypes.c_ubyte * 24), -] - -NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbpEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ltcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ltsEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpaEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpaSubpEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('fbpLogicalIndex', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('ropEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ltcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ltsEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('fbpaEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('ropEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('fbpaSubpEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS -class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS._fields_ = [ - ('sysIdx', ctypes.c_uint32), - ('sysl2LtcEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS -class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS._fields_ = [ - ('sysIdx', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('sysl2LtsEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('pacEnMask', ctypes.c_uint32), -] - -NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('logicalLtcEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS._fields_ = [ - ('fbpIndex', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('logicalLtcEnMask', ctypes.c_uint64), -] - -NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS -class struct_NV2080_CTRL_FB_FS_INFO_QUERY(Structure): - pass - -class union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams(Union): - pass - -union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams._pack_ = 1 # source:False -union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams._fields_ = [ - ('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS), - ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS), - ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS), - ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS), - ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS), - ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS), - ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS), - ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS), - ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS), - ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS), - ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS), - ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS), - ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS), - ('sysl2Ltc', NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS), - ('pac', NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS), - ('logicalLtc', NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS), - ('dmLogicalLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS), - ('sysl2Lts', NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 8), -] - -struct_NV2080_CTRL_FB_FS_INFO_QUERY._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_FS_INFO_QUERY._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryParams', union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams), -] - -NV2080_CTRL_FB_FS_INFO_QUERY = struct_NV2080_CTRL_FB_FS_INFO_QUERY -class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_FB_FS_INFO_QUERY * 120), -] - -NV2080_CTRL_FB_GET_FS_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS._fields_ = [ - ('histogram', ctypes.c_uint32 * 5), -] - -NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS = struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS -class struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO(Structure): - pass - -struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO._fields_ = [ - ('pageNumber', ctypes.c_uint64), - ('source', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO -class struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS._fields_ = [ - ('offlined', struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO * 64), - ('validEntries', ctypes.c_uint32), - ('baseIndex', ctypes.c_uint32), - ('bMore', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), -] - -NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS -class struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO._fields_ = [ - ('client', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('beginAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_FB_ALLOCATION_INFO = struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO -class struct_NV2080_CTRL_CMD_FB_CLIENT_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_CLIENT_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_CLIENT_INFO._fields_ = [ - ('handle', ctypes.c_uint32), - ('pid', ctypes.c_uint32), - ('subProcessID', ctypes.c_uint32), - ('subProcessName', ctypes.c_char * 100), -] - -NV2080_CTRL_CMD_FB_CLIENT_INFO = struct_NV2080_CTRL_CMD_FB_CLIENT_INFO -class struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS._fields_ = [ - ('allocCount', ctypes.c_uint64), - ('pAllocInfo', ctypes.POINTER(None)), - ('clientCount', ctypes.c_uint64), - ('pClientInfo', ctypes.POINTER(None)), -] - -NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS -class struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS._fields_ = [ - ('bOnline', ctypes.c_ubyte), -] - -NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS = struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS -class struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS._fields_ = [ - ('numaNodeId', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('numaMemAddr', ctypes.c_uint64), - ('numaMemSize', ctypes.c_uint64), - ('numaOfflineAddressesCount', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('numaOfflineAddresses', ctypes.c_uint64 * 64), -] - -NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS -class struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS._fields_ = [ - ('maxSubmittedSemaphoreValueOffset', ctypes.c_uint64), - ('monitoredFenceThresholdOffset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('caps', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS = struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS -class struct_NV2080_CTRL_CMD_FB_STATS_ENTRY(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_STATS_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_STATS_ENTRY._fields_ = [ - ('totalSize', ctypes.c_uint64), - ('rsvdSize', ctypes.c_uint64), - ('osSize', ctypes.c_uint64), - ('r1Size', ctypes.c_uint64), - ('r2Size', ctypes.c_uint64), - ('freeSize', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_FB_STATS_ENTRY = struct_NV2080_CTRL_CMD_FB_STATS_ENTRY -class struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('invalidateAll', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS = struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS -class struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO._fields_ = [ - ('allocSize', ctypes.c_uint64), - ('numBlocks', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('rsvdSize', ctypes.c_uint64), -] - -NV2080_CTRL_CMD_FB_STATS_OWNER_INFO = struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO -class struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS._fields_ = [ - ('version', ctypes.c_uint64), - ('fbSizeInfo', NV2080_CTRL_CMD_FB_STATS_ENTRY), - ('fbBlockInfo', struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO * 200), -] - -NV2080_CTRL_CMD_FB_STATS_GET_PARAMS = struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS -class struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS._fields_ = [ - ('bStaticBar1Enabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('staticBar1StartOffset', ctypes.c_uint64), - ('staticBar1Size', ctypes.c_uint64), -] - -NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS -class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS._fields_ = [ - ('currentConfiguration', ctypes.c_uint32), -] - -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS._fields_ = [ - ('newConfiguration', ctypes.c_uint32), -] - -NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS -class struct_NV2080_CTRL_FB_GET_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_GET_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_GET_STATUS_PARAMS._fields_ = [ - ('fbStatus', ctypes.c_uint32), -] - -NV2080_CTRL_FB_GET_STATUS_PARAMS = struct_NV2080_CTRL_FB_GET_STATUS_PARAMS -class struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS._fields_ = [ - ('isSupported', ctypes.c_uint32), -] - -NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS = struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS -class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS._fields_ = [ - ('currentStatus', ctypes.c_uint32), -] - -NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS -NV2080_CTRL_CMD_SET_GPFIFO = (0x20801102) # macro -NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS = (16) # macro -NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_FIFO_BIND_ENGINES = (0x20801103) # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES = (0x20801104) # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID = (0x4) # macro -# NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE = 0 : 0 # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE = (0x00000000) # macro -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE = (0x00000001) # macro -NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT = (0x20801108) # macro -NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL = (0x000000000) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS = (0x000000001) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP = (0x000000002) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP = (0x000000003) # macro -NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET = (0x000000004) # macro -NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE = (0x000000005) # macro -NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE = (0x000000006) # macro -NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED = (0x000000007) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE = (0x000000008) # macro -NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE = (0x000000009) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT = (0x00000000a) # macro -NV2080_CTRL_FIFO_INFO_INDEX_MAX = (0x00000000a) # macro -NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT = (12) # macro -NV2080_CTRL_CMD_FIFO_GET_INFO = (0x20801109) # macro -NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES = (256) # macro -NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL = (0x2080110a) # macro -NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = (0x2080110b) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = (64) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE = (0x00000000) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE = (0x00000001) # macro -NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE = (0x00000000) # macro -NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE = (0x00000001) # macro -NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT = 0x2 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO = (0x2080110c) # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID = 0x00000000 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM = 0x00000001 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH = 0x00000002 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH = 0x00000003 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION = (0x2080110d) # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM = 0x00000000 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM = 0x00000001 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED = 0x00000000 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED = 0X00000001 # macro -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED = 0X00000002 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN = 0 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER = 1 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT = 2 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 3 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE = 4 # macro -NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT = 0 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE = 1 # macro -NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE = 2 # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG = (0x2080110e) # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT = 32 # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS = 8 # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES = 200 # macro -NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE = (0x20801112) # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES = 256 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES = 32 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES = 16 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA = 2 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN = 16 # macro -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT = (0x20801113) # macro -NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE = 0x00000001 # macro -NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA = 0x00000002 # macro -NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY = (0x20801115) # macro -NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT = 0x0 # macro -NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED = 0x1 # macro -NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM = 0x2 # macro -# NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE = 0 : 0 # macro -NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE = (0x00000000) # macro -NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE = (0x00000001) # macro -NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO = (0x20801116) # macro -NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID = (0x16) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS = (0x20801117) # macro -NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID = (0x17) # macro -NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = (0x20801118) # macro -NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS = (0x20801119) # macro -NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS = 4096 # macro -NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID = (0x19) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION = (0x2080111a) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES = (64) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0x1A) # macro -NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 = (0x2080111b) # macro -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID = (0x1B) # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE = (0x20801120) # macro -NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE = (0x20801121) # macro -NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS = (0x20801122) # macro -NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG = 128 # macro -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO = (0x20801123) # macro -NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID = (0x20801124) # macro -NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID = (0x24) # macro -class struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('base', ctypes.c_uint64), - ('numEntries', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_CMD_SET_GPFIFO_PARAMS = struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS -class struct_NV2080_CTRL_FIFO_BIND_CHANNEL(Structure): - pass - -struct_NV2080_CTRL_FIFO_BIND_CHANNEL._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_BIND_CHANNEL._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_BIND_CHANNEL = struct_NV2080_CTRL_FIFO_BIND_CHANNEL -class struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS._fields_ = [ - ('bindChannelCount', ctypes.c_uint32), - ('bindChannels', struct_NV2080_CTRL_FIFO_BIND_CHANNEL * 16), -] - -NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS = struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS -class struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS = struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS -class struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS._fields_ = [ - ('physChannelCount', ctypes.c_uint32), - ('physChannelCountInUse', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS = struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS -NV2080_CTRL_FIFO_INFO = struct_NVXXXX_CTRL_XXX_INFO -class struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS._fields_ = [ - ('fifoInfoTblSize', ctypes.c_uint32), - ('fifoInfoTbl', struct_NVXXXX_CTRL_XXX_INFO * 256), - ('engineType', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_GET_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS -class struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS = struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numChannels', ctypes.c_uint32), - ('bOnlyDisableScheduling', ctypes.c_ubyte), - ('bRewindGpPut', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 6), - ('pRunlistPreemptEvent', ctypes.POINTER(None)), - ('hClientList', ctypes.c_uint32 * 64), - ('hChannelList', ctypes.c_uint32 * 64), -] - -NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS -class struct_NV2080_CTRL_FIFO_MEM_INFO(Structure): - pass - -struct_NV2080_CTRL_FIFO_MEM_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_MEM_INFO._fields_ = [ - ('aperture', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_FIFO_MEM_INFO = struct_NV2080_CTRL_FIFO_MEM_INFO -class struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO(Structure): - pass - -struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO._fields_ = [ - ('inst', NV2080_CTRL_FIFO_MEM_INFO), - ('ramfc', NV2080_CTRL_FIFO_MEM_INFO), - ('methodBuf', struct_NV2080_CTRL_FIFO_MEM_INFO * 2), - ('methodBufCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV2080_CTRL_FIFO_CHANNEL_MEM_INFO = struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO -class struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('chMemInfo', NV2080_CTRL_FIFO_CHANNEL_MEM_INFO), -] - -NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS -class struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS._fields_ = [ - ('aperture', ctypes.c_uint32), - ('attribute', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0._fields_ = [ - ('timestampNs', ctypes.c_uint64), - ('timeRunTotalNs', ctypes.c_int64), - ('timeRunNs', ctypes.c_uint32), - ('swrlId', ctypes.c_uint32), - ('targetTimeSlice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('cumulativePreemptionTime', ctypes.c_uint64), - ('counters', ctypes.c_uint64 * 8), -] - -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('entry', struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0 * 200), - ('schedPolicy', ctypes.c_uint32), - ('arrEnabled', ctypes.c_uint32), - ('arrAvgFactor', ctypes.c_uint32), - ('targetTimesliceNs', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS -class struct_NV2080_CTRL_FIFO_DEVICE_ENTRY(Structure): - pass - -struct_NV2080_CTRL_FIFO_DEVICE_ENTRY._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DEVICE_ENTRY._fields_ = [ - ('engineData', ctypes.c_uint32 * 16), - ('pbdmaIds', ctypes.c_uint32 * 2), - ('pbdmaFaultIds', ctypes.c_uint32 * 2), - ('numPbdmas', ctypes.c_uint32), - ('engineName', ctypes.c_char * 16), -] - -NV2080_CTRL_FIFO_DEVICE_ENTRY = struct_NV2080_CTRL_FIFO_DEVICE_ENTRY -class struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [ - ('baseIndex', ctypes.c_uint32), - ('numEntries', ctypes.c_uint32), - ('bMore', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('entries', struct_NV2080_CTRL_FIFO_DEVICE_ENTRY * 32), -] - -NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS -class struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), - ('vChid', ctypes.c_uint32), - ('faultType', ctypes.c_uint32), -] - -NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS = struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS -class struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('schedPolicy', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS = struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS -class struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('hUserdMemory', ctypes.c_uint32), - ('gpFifoEntries', ctypes.c_uint32), - ('gpFifoOffset', ctypes.c_uint64), - ('userdOffset', ctypes.c_uint64), -] - -NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS = struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), -] - -NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS -class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cacheAttrib', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS -class struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS._fields_ = [ - ('runlistId', ctypes.c_uint32), - ('bitMask', ctypes.c_uint32 * 128), -] - -NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('hClientList', ctypes.c_uint32 * 64), - ('hChannelList', ctypes.c_uint32 * 64), - ('bEnableAfterKeyRotation', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS -class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS._fields_ = [ - ('numChannels', ctypes.c_uint32), - ('hChannelList', ctypes.c_uint32 * 64), - ('bEnableAfterKeyRotation', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('schedPolicy', ctypes.c_uint32), - ('arrEnabled', ctypes.c_uint32), - ('targetTimesliceNs', ctypes.c_uint32), - ('arrAvgFactor', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('schedPolicy', ctypes.c_uint32), - ('enableArr', ctypes.c_uint32), - ('timesliceTargetNs', ctypes.c_uint32), - ('frequencyForARR', ctypes.c_uint32), - ('avgFactorForARR', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS -class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('supportedSchedulers', ctypes.c_uint32 * 3), - ('bIsArrModeSupported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('maxTimesliceNs', ctypes.c_uint32), - ('minTimesliceNs', ctypes.c_uint32), - ('maxFrequencyForARR', ctypes.c_uint32), - ('minFrequencyForARR', ctypes.c_uint32), - ('maxAvgFactorForARR', ctypes.c_uint32), - ('minAvgFactorForARR', ctypes.c_uint32), -] - -NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS -class struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hChannelOrTsg', ctypes.c_uint32), - ('tsgId', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('channelUniqueID', ctypes.c_uint32 * 128), - ('vasUniqueID', ctypes.c_uint32 * 128), - ('veid', ctypes.c_uint32 * 128), -] - -NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS -class struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS._fields_ = [ - ('hClients', ctypes.c_uint32 * 128), - ('hChannels', ctypes.c_uint32 * 128), - ('numChannels', ctypes.c_uint32), - ('channelUniqueIDs', ctypes.c_uint32 * 128), -] - -NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS = struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS -NV2080_CTRL_CMD_FLA_RANGE = (0x20803501) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE = 0x00000000 # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE = (1 << 0) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY = (1 << 1) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE = (1 << 2) # macro -NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY = (1 << 3) # macro -NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK = (0x20803502) # macro -NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_FLA_GET_RANGE = (0x20803503) # macro -NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS = (0x20803504) # macro -NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID = (0x4) # macro -class struct_NV2080_CTRL_FLA_RANGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('mode', ctypes.c_uint32), - ('hVASpace', ctypes.c_uint32), -] - -NV2080_CTRL_FLA_RANGE_PARAMS = struct_NV2080_CTRL_FLA_RANGE_PARAMS - -# values for enumeration 'NV2080_CTRL_FLA_ADDRSPACE' -NV2080_CTRL_FLA_ADDRSPACE__enumvalues = { - 0: 'NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', - 1: 'NV2080_CTRL_FLA_ADDRSPACE_FBMEM', -} -NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = 0 -NV2080_CTRL_FLA_ADDRSPACE_FBMEM = 1 -NV2080_CTRL_FLA_ADDRSPACE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_FLA_ACTION' -NV2080_CTRL_FLA_ACTION__enumvalues = { - 0: 'NV2080_CTRL_FLA_ACTION_BIND', - 1: 'NV2080_CTRL_FLA_ACTION_UNBIND', -} -NV2080_CTRL_FLA_ACTION_BIND = 0 -NV2080_CTRL_FLA_ACTION_UNBIND = 1 -NV2080_CTRL_FLA_ACTION = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS._fields_ = [ - ('imbPhysAddr', ctypes.c_uint64), - ('addrSpace', NV2080_CTRL_FLA_ADDRSPACE), - ('flaAction', NV2080_CTRL_FLA_ACTION), -] - -NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS -class struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -NV2080_CTRL_FLA_GET_RANGE_PARAMS = struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS -class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS._fields_ = [ - ('totalSize', ctypes.c_uint64), - ('freeSize', ctypes.c_uint64), -] - -NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS -FALCON_ID_PMU = ((0x00000029)) # macro -FALCON_ID_DPU = ((0x00000028)) # macro -FALCON_ID_SEC2 = ((0x00000026)) # macro -FALCON_ID_FBFLCN = ((0x0000002a)) # macro -NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE = (0x20803101) # macro -NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE = 0x00 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END = 0x01 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN = 0x02 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END = 0x03 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK = 0x04 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN = 0x05 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END = 0x06 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY = 0x07 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT = 0x08 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 = 0x09 # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END = 0x0A # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN = 0x0B # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END = 0x0C # macro -NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY = 0x0D # macro -NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID = 0xFF # macro -NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH = (0x20803118) # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT = 0x0 # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON = 0x1 # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV = 0x2 # macro -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB = 0x3 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_FLAG = 31 : 31 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_COMM_HEAD = 30 : 30 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_VARIABLE = 29 : 29 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EXTEND = 28 : 28 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT = (27) # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE = (20) # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID = ((27)):((20)) # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT = (28) # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE = (24) # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT = ((28)):((24)) # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_LENGTH = 19 : 8 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOAD = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT = 23 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_HEAD_TIME = 29 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_DATA_PAYLOAD = 30 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON = 10 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD = 0x0 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 = 0x1 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK = 0x2 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK = 0x3 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED = 0x4 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_ODP_MISS_COUNT = 23 : 11 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TIMER_TICK_TIME_SLIP = 23 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_UNIT_ID = 15 : 8 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE = 23 : 16 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID = 15 : 8 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC = 15 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE = 0xF0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID = 23 : 16 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT = 10 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_TASK_ID = 7 : 0 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID = 23 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED = 0x000000 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL = 0x000001 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT = 6 # macro -# NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID = 11 : 0 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID = 0x000 # macro -NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL = 0x001 # macro -NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON = 1 # macro -NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT = 2 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH = 0 : 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED = 1 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH = 1 : 1 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED = 1 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH = 2 : 2 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED = 0 # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED = 1 # macro -# NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_THRESHOLD = 31 : 8 # macro -NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT = (0x20) # macro -NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES = (0x120) # macro -NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES = (0x24) # macro -NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO = (0x20803120) # macro -NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET = (0x20803122) # macro -NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET = (0x20803123) # macro -NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO = (0x20803124) # macro -NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x24) # macro -# NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_UNKNWON = ADDR_UNKNOWN # macro -# NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_SYSMEM = ADDR_SYSMEM # macro -# NV2080_CTRL_FLCN_CTX_BUFFER_INFO_APERTURE_FBMEM = ADDR_FBMEM # macro -NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = (0x20803125) # macro -NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x25) # macro -class struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS._fields_ = [ - ('flcnID', ctypes.c_uint32), - ('heapSize', ctypes.c_uint32), - ('heapFree', ctypes.c_uint32), -] - -NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS = struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS -class struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS._fields_ = [ - ('engine', ctypes.c_uint32), - ('engineArch', ctypes.c_uint32), -] - -NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS = struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS -class struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER(Structure): - pass - -struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER._fields_ = [ - ('mask', ctypes.c_ubyte * 36), -] - -NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER = struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER -class struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS._fields_ = [ - ('engine', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint32), - ('queueFeatureId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS -class struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS._fields_ = [ - ('engine', ctypes.c_uint32), - ('eventFilter', NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER), - ('queueId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS -NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS -NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS -class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [ - ('hUserClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('alignment', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('bufferHandle', ctypes.POINTER(None)), - ('pageCount', ctypes.c_uint64), - ('physAddr', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('kind', ctypes.c_uint32), - ('pageSize', ctypes.c_uint32), - ('bIsContigous', ctypes.c_ubyte), - ('bDeviceDescendant', ctypes.c_ubyte), - ('uuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS -class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('totalBufferSize', ctypes.c_uint64), -] - -NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS -NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION = (0x20802300) # macro -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID = (0x00) # macro -NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT = (0x20802301) # macro -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID = (0x01) # macro -NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT = (0x20802302) # macro -NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID = (0x02) # macro -NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION = (0x20802303) # macro -NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID = (0x03) # macro -class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS._fields_ = [ - ('gpioPin', ctypes.c_uint32), - ('bInput', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS._fields_ = [ - ('gpioPin', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS._fields_ = [ - ('gpioPin', ctypes.c_uint32), - ('value', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS._fields_ = [ - ('function', ctypes.c_uint32), - ('pin', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS -NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO = (0x20803801) # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES = 96 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE = 32 # macro -NV2080_CTRL_GRMGR_MAX_SMC_IDS = 8 # macro -NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID = 0 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT = 1 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP = 2 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK = 3 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK = 4 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP = 5 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK = 6 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS = 7 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK = 8 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID = 9 # macro -NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK = 10 # macro -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS._pack_ = 1 # source:False +NV2080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO +class struct_NV2080_CTRL_GR_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_INFO_PARAMS._fields_ = [ + ('grInfoListSize', NvU32), + ('grInfoList', NvP64), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_INFO_PARAMS +class struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('hShareClient', NvHandle), + ('hShareChannel', NvHandle), + ('zcullMode', NvU32), +] +NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS +class struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS._fields_ = [ + ('widthAlignPixels', NvU32), + ('heightAlignPixels', NvU32), + ('pixelSquaresByAliquots', NvU32), + ('aliquotTotal', NvU32), + ('zcullRegionByteMultiplier', NvU32), + ('zcullRegionHeaderSize', NvU32), + ('zcullSubregionHeaderSize', NvU32), + ('subregionCount', NvU32), + ('subregionWidthAlignPixels', NvU32), + ('subregionHeightAlignPixels', NvU32), +] +NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS +class struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('pmMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS +class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtr', NvU64), + ('zcullMode', NvU32), +] +NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS +class struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtr', NvU64), + ('pmMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS +class struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS._fields_ = [ + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtr', NvU64), +] +NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS +class struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS._fields_ = [ + ('mapValueCount', NvU32), + ('mapValues', (NvU8 * 128)), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS +class struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('smpcMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS +class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS(Struct): pass +class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId(Struct): pass +struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId._fields_ = [ + ('gpcId', NvU32), + ('tpcId', NvU32), +] +struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS._fields_ = [ + ('smId', (struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId * 240)), + ('smCount', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS = struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS +class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS._fields_ = [ + ('flags', NvU32), + ('hChannel', NvHandle), + ('gfxpPreemptMode', NvU32), + ('cilpPreemptMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS +enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', 0) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', 1) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', 2) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', 3) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', 4) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', 5) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', 6) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', 7) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', 8) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', 9) + +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS +class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS._fields_ = [ + ('flags', NvU32), + ('hClient', NvHandle), + ('hChannel', NvHandle), + ('vMemPtrs', (NvU64 * 9)), + ('gfxpPreemptMode', NvU32), + ('cilpPreemptMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS +class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('samplingMode', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS +class struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS._fields_ = [ + ('ropUnitCount', NvU32), + ('ropOperationsFactor', NvU32), + ('ropOperationsCount', NvU32), +] +NV2080_CTRL_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS +class struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('flags', NvU32), + ('saveCnt', NvU32), + ('restoreCnt', NvU32), + ('wfiSaveCnt', NvU32), + ('ctaSaveCnt', NvU32), + ('cilpSaveCnt', NvU32), + ('gfxpSaveCnt', NvU32), +] +NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS +class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('totalBufferSize', NvU64), +] +NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS +class struct_NV2080_CTRL_GR_CTX_BUFFER_INFO(Struct): pass +struct_NV2080_CTRL_GR_CTX_BUFFER_INFO._fields_ = [ + ('alignment', NvU64), + ('size', NvU64), + ('bufferHandle', NvP64), + ('pageCount', NvU64), + ('physAddr', NvU64), + ('bufferType', NvU32), + ('aperture', NvU32), + ('kind', NvU32), + ('pageSize', NvU32), + ('bIsContigous', NvBool), + ('bGlobalBuffer', NvBool), + ('bLocalBuffer', NvBool), + ('bDeviceDescendant', NvBool), + ('uuid', (NvU8 * 16)), +] +NV2080_CTRL_GR_CTX_BUFFER_INFO = struct_NV2080_CTRL_GR_CTX_BUFFER_INFO +PNV2080_CTRL_GR_CTX_BUFFER_INFO = ctypes.POINTER(struct_NV2080_CTRL_GR_CTX_BUFFER_INFO) +class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [ + ('hUserClient', NvHandle), + ('hChannel', NvHandle), + ('bufferCount', NvU32), + ('ctxBufferInfo', (NV2080_CTRL_GR_CTX_BUFFER_INFO * 64)), +] +NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS +class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS(Struct): pass +class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId(Struct): pass +struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId._fields_ = [ + ('gpcId', NvU16), + ('localTpcId', NvU16), + ('localSmId', NvU16), + ('globalTpcId', NvU16), + ('virtualGpcId', NvU16), + ('migratableTpcId', NvU16), +] +struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS._fields_ = [ + ('globalSmId', (struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId * 512)), + ('numSm', NvU16), + ('numTpc', NvU16), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS +class struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS._fields_ = [ + ('chID', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS = struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS +class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC(Struct): pass +struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC._fields_ = [ + ('errorCounter', NvU64), + ('errorTimestamp', NvU64), + ('warningCounter', NvU64), + ('warningTimestamp', NvU64), +] +NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC +class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC(Struct): pass +struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC._fields_ = [ + ('tpc', (NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC * 10)), +] +NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC +class struct_NV2080_CTRL_GR_VAT_ALARM_DATA(Struct): pass +struct_NV2080_CTRL_GR_VAT_ALARM_DATA._fields_ = [ + ('gpc', (NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC * 10)), +] +NV2080_CTRL_GR_VAT_ALARM_DATA = struct_NV2080_CTRL_GR_VAT_ALARM_DATA +class struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS._fields_ = [ + ('smVatAlarm', NV2080_CTRL_GR_VAT_ALARM_DATA), + ('maxGpcCount', NvU32), + ('maxTpcPerGpcCount', NvU32), +] +NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS +PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS) +class struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS._fields_ = [ + ('attribBufferSize', NvU32), +] +NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS +class struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS._fields_ = [ + ('maxSlots', NvU32), + ('slotStride', NvU32), + ('ctrlStructSize', NvU64), + ('ctrlStructAlign', NvU64), + ('poolSize', NvU64), + ('poolAlign', NvU64), +] +NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS +class struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS._fields_ = [ + ('maxSlots', NvU32), + ('hMemory', NvHandle), + ('offset', NvU32), + ('size', NvU32), +] +NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS +class struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS._fields_ = [ + ('numSlots', NvU32), + ('slots', (NvU32 * 64)), + ('hMemory', NvHandle), + ('offset', NvU32), + ('size', NvU32), +] +NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS +class struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS._fields_ = [ + ('numSlots', NvU32), + ('slots', (NvU32 * 64)), + ('bRemoveSpecificSlots', NvBool), + ('hMemory', NvHandle), + ('offset', NvU32), + ('size', NvU32), +] +NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS +NV2080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS +NV2080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS +class struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS._fields_ = [ + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('gpcMask', NvU32), +] +NV2080_CTRL_GR_GET_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS +class struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS._fields_ = [ + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('gpcId', NvU32), + ('tpcMask', NvU32), +] +NV2080_CTRL_GR_GET_TPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS +NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS +class struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [ + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('engineId', NvU32), + ('alignment', NvU32), + ('size', NvU32), + ('bInfoPopulated', NvBool), +] +NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS +class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._fields_ = [ + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('imla0', NvU8), + ('fmla16', NvU8), + ('dp', NvU8), + ('fmla32', NvU8), + ('ffma', NvU8), + ('imla1', NvU8), + ('imla2', NvU8), + ('imla3', NvU8), + ('imla4', NvU8), +] +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS +enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD = CEnum(ctypes.c_uint32) +NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', 0) +NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', 1) +NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', 2) +NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', 3) + +NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD +class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS._fields_ = [ + ('hEventBuffer', NvHandle), + ('recordSize', NvU32), + ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD), + ('eventFilter', NvU32), + ('bAllUsers', NvBool), +] +NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS +class struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS._fields_ = [ + ('physSyspipeId', NvU32), + ('gpcMask', NvU32), +] +NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS +class struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS._fields_ = [ + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('gpcId', NvU32), + ('ppcMask', NvU32), +] +NV2080_CTRL_GR_GET_PPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS +class struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS._fields_ = [ + ('gpcId', NvU32), + ('numTpcs', NvU32), +] +NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS = struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS +class struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS._fields_ = [ + ('hChannel', NvHandle), + ('zcullMode', NvU32), + ('pmMode', NvU32), + ('smpcMode', NvU32), + ('cilpPreemptMode', NvU32), + ('gfxpPreemptMode', NvU32), +] +NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS +NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS +class struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS._fields_ = [ + ('gpcId', NvU32), + ('zcullMask', NvU32), +] +NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS +enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE = CEnum(ctypes.c_uint32) +NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', 0) +NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', 1) +NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', 2) +NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', 3) +NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', 4) +NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', 5) + +NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE +class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS._fields_ = [ + ('hEventBuffer', NvHandle), + ('recordSize', NvU32), + ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD), + ('eventFilter', NvU32), + ('bAllUsers', NvBool), + ('reasonCode', NvU32), +] +NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS +class struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS._fields_ = [ + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('physGfxGpcMask', NvU32), + ('numGfxTpc', NvU32), +] +NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS +class struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS(Struct): pass +struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [ + ('gpc', NvU32), + ('tpcReconfigMask', NvU32), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), +] +NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS._fields_ = [ - ('gpcCount', ctypes.c_uint32), + ('gpcCount', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('chipletGpcMap', ctypes.c_uint32), + ('gpcId', NvU32), + ('chipletGpcMap', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32), + ('gpcId', NvU32), + ('tpcMask', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('ppcMask', ctypes.c_uint32), + ('gpcId', NvU32), + ('ppcMask', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('gpcId', ctypes.c_uint32), - ('chipletGpcMap', ctypes.c_uint32), + ('swizzId', NvU32), + ('gpcId', NvU32), + ('chipletGpcMap', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS._fields_ = [ - ('gpcId', ctypes.c_uint32), - ('ropMask', ctypes.c_uint32), + ('gpcId', NvU32), + ('ropMask', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS._fields_ = [ - ('chipletSyspipeMask', ctypes.c_uint32), + ('chipletSyspipeMask', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint16), - ('physSyspipeIdCount', ctypes.c_uint16), - ('physSyspipeId', ctypes.c_ubyte * 8), + ('swizzId', NvU16), + ('physSyspipeIdCount', NvU16), + ('physSyspipeId', (NvU8 * 8)), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('grIdx', ctypes.c_uint32), - ('gpcEnMask', ctypes.c_uint32), + ('swizzId', NvU32), + ('grIdx', NvU32), + ('gpcEnMask', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS._fields_ = [ - ('syspipeId', ctypes.c_uint32), + ('syspipeId', NvU32), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS -class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS(Structure): - pass - -class union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData(Union): - pass - -union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData._pack_ = 1 # source:False -union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData._fields_ = [ - ('gpcCountData', NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS), - ('chipletGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS), - ('tpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS), - ('ppcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS), - ('partitionGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS), - ('syspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS), - ('partitionChipletSyspipeData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS), - ('dmGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS), - ('partitionSyspipeIdData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS), - ('ropMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 4), +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS(Struct): pass +class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData(ctypes.Union): pass +struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData._fields_ = [ + ('gpcCountData', NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS), + ('chipletGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS), + ('tpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS), + ('ppcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS), + ('partitionGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS), + ('syspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS), + ('partitionChipletSyspipeData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS), + ('dmGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS), + ('partitionSyspipeIdData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS), + ('ropMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS), ] - -struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS._fields_ = [ - ('queryType', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('status', ctypes.c_uint32), - ('queryData', union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData), + ('queryType', NvU16), + ('reserved', (NvU8 * 2)), + ('status', NvU32), + ('queryData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData), ] - NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS -class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS._fields_ = [ - ('numQueries', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 6), - ('queries', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS * 96), + ('numQueries', NvU16), + ('reserved', (NvU8 * 6)), + ('queries', (NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS * 96)), ] - NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS = struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS -NV2080_CTRL_CMD_GSP_GET_FEATURES = (0x20803601) # macro -NV2080_GSP_MAX_BUILD_VERSION_LENGTH = (0x0000040) # macro -NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID = (0x1) # macro -# NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED = 0 : 0 # macro -NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE = (0x00000000) # macro -NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE = (0x00000001) # macro -# NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED = 1 : 1 # macro -NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE = (0x00000000) # macro -NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE = (0x00000001) # macro -NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS = (0x20803602) # macro -NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS = (0x20803603) # macro -NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS = (0x20803604) # macro -NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX = 64 # macro -NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID = (0x4) # macro -class struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS(Struct): pass struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS._fields_ = [ - ('gspFeatures', ctypes.c_uint32), - ('bValid', ctypes.c_ubyte), - ('bDefaultGspRmGpu', ctypes.c_ubyte), - ('firmwareVersion', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 2), + ('gspFeatures', NvU32), + ('bValid', NvBool), + ('bDefaultGspRmGpu', NvBool), + ('firmwareVersion', (NvU8 * 64)), ] - NV2080_CTRL_GSP_GET_FEATURES_PARAMS = struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS -class struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT(Structure): - pass - -struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT._pack_ = 1 # source:False +class struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT(Struct): pass struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT._fields_ = [ - ('allocatedSize', ctypes.c_uint64), - ('usableSize', ctypes.c_uint64), - ('memTrackOverhead', ctypes.c_uint64), - ('allocationCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('allocatedSize', NvU64), + ('usableSize', NvU64), + ('memTrackOverhead', NvU64), + ('allocationCount', NvU32), ] - NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT = struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT -class struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS(Struct): pass struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('managedSize', ctypes.c_uint64), - ('largestFreeChunkSize', ctypes.c_uint64), - ('current', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT), - ('peak', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT), + ('gfid', NvU32), + ('managedSize', NvU64), + ('largestFreeChunkSize', NvU64), + ('current', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT), + ('peak', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT), ] - NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS = struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS -class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS._fields_ = [ - ('allocatedSize', ctypes.c_uint64), - ('peakAllocatedSize', ctypes.c_uint64), - ('managedSize', ctypes.c_uint64), - ('allocationCount', ctypes.c_uint32), - ('peakAllocationCount', ctypes.c_uint32), - ('largestFreeChunkSize', ctypes.c_uint64), + ('allocatedSize', NvU64), + ('peakAllocatedSize', NvU64), + ('managedSize', NvU64), + ('allocationCount', NvU32), + ('peakAllocationCount', NvU32), + ('largestFreeChunkSize', NvU64), ] - NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS -class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS(Structure): - pass - -struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS._pack_ = 1 # source:False +class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS(Struct): pass struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS._fields_ = [ - ('allocations', ctypes.c_uint32), - ('peakAllocations', ctypes.c_uint32), - ('objectSize', ctypes.c_uint64), + ('allocations', NvU32), + ('peakAllocations', NvU32), + ('objectSize', NvU64), ] - NV2080_CTRL_GSP_LIBOS_POOL_STATS = struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS -class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS._fields_ = [ - ('poolStats', struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS * 64), - ('totalHeapSize', ctypes.c_uint64), - ('poolCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('poolStats', (NV2080_CTRL_GSP_LIBOS_POOL_STATS * 64)), + ('totalHeapSize', NvU64), + ('poolCount', NvU8), ] - NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS = struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS -NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK = (0x20804101) # macro -NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE = (0x20804102) # macro -class struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS._fields_ = [ - ('hshubNcisocMask', ctypes.c_uint32), - ('hshubNvlMask', ctypes.c_uint32), + ('hshubNcisocMask', NvU32), + ('hshubNvlMask', NvU32), ] - NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS = struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS -class struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS._fields_ = [ - ('ecMode', ctypes.c_uint32), - ('status', ctypes.c_uint32), + ('ecMode', NvU32), + ('status', NvU32), ] - NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS = struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS -NV2080_CTRL_I2C_VERSION_0 = 0x00 # macro -NV2080_CTRL_I2C_MAX_ENTRIES = 256 # macro -NV2080_CTRL_I2C_MAX_REG_LEN = 8 # macro -NV2080_CTRL_I2C_MAX_ADDR_ENTRIES = 20 # macro -NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC = (0x00000001) # macro -NV2080_CTRL_I2C_FLAGS_PRIVILEGE = (0x00000002) # macro -NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED = (0x00000004) # macro -NV2080_CTRL_I2C_FLAGS_PX3540 = (0x00000010) # macro -NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED = (0x00000008) # macro -NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_I2C_READ_BUFFER = (0x20800601) # macro -NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_I2C_WRITE_BUFFER = (0x20800602) # macro -NV2080_CTRL_CMD_I2C_READ_REG = (0x20800603) # macro -NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_I2C_WRITE_REG = (0x20800604) # macro -NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_I2C_ACCESS = (0x20800610) # macro -NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID = (0x10) # macro -NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_CMD_RELEASE = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_CMD_NULL = 0x5 # macro -NV2080_CTRL_I2C_ACCESS_CMD_RESET = 0x6 # macro -NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT = 0x11 # macro -NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE = 0x12 # macro -NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE = 0x13 # macro -NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER = 0x14 # macro -NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER = 0x15 # macro -NV2080_CTRL_I2C_ACCESS_CMD_START = 0x17 # macro -NV2080_CTRL_I2C_ACCESS_CMD_STOP = 0x18 # macro -NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE = 0x20 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_START = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_STOP = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_ACK = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_RAB = 0x8 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS = 0x10 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE = 0x20 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED = 0x40 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_RESTART = 0x80 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT = 0x100 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT = 0x200 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT = 0x400 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT = 0x800 # macro -NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT = 0x1000 # macro -NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC = 0x0 # macro -NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_PORT_1 = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_PORT_2 = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_PORT_3 = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_PORT_4 = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_PORT_5 = 0x5 # macro -NV2080_CTRL_I2C_ACCESS_PORT_6 = 0x6 # macro -NV2080_CTRL_I2C_ACCESS_PORT_7 = 0x7 # macro -NV2080_CTRL_I2C_ACCESS_PORT_8 = 0x8 # macro -NV2080_CTRL_I2C_ACCESS_PORT_9 = 0x9 # macro -NV2080_CTRL_I2C_ACCESS_PORT_10 = 0x10 # macro -NV2080_CTRL_I2C_ACCESS_NUM_PORTS = 0x10 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS = 0x0 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_ERROR = 0x1 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR = 0x2 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY = 0x3 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND = 0x4 # macro -NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING = 0x5 # macro -NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE = (0x20800620) # macro -NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID = (0x20) # macro -class struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('inputCount', ctypes.c_uint32), - ('inputBuffer', ctypes.c_ubyte * 256), - ('outputCount', ctypes.c_uint32), - ('outputBuffer', ctypes.c_ubyte * 256), + ('version', NvU32), + ('port', NvU32), + ('flags', NvU32), + ('inputCount', NvU32), + ('inputBuffer', (NvU8 * 256)), + ('outputCount', NvU32), + ('outputBuffer', (NvU8 * 256)), ] - NV2080_CTRL_I2C_READ_BUFFER_PARAMS = struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS -class struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('inputCount', ctypes.c_uint32), - ('inputBuffer', ctypes.c_ubyte * 256), - ('encrClientID', ctypes.c_uint32), + ('version', NvU32), + ('port', NvU32), + ('flags', NvU32), + ('inputCount', NvU32), + ('inputBuffer', (NvU8 * 256)), + ('encrClientID', NvU32), ] - NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS = struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS -class struct_NV2080_CTRL_I2C_RW_REG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_RW_REG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_I2C_RW_REG_PARAMS(Struct): pass struct_NV2080_CTRL_I2C_RW_REG_PARAMS._fields_ = [ - ('version', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('addr', ctypes.c_uint32), - ('reg', ctypes.c_ubyte), - ('bufsize', ctypes.c_ubyte), - ('buffer', ctypes.c_ubyte * 255), - ('PADDING_0', ctypes.c_ubyte * 3), + ('version', NvU32), + ('port', NvU32), + ('flags', NvU32), + ('addr', NvU32), + ('reg', NvU8), + ('bufsize', NvU8), + ('buffer', (NvU8 * 255)), ] - NV2080_CTRL_I2C_RW_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS -class struct_NV2080_CTRL_I2C_ACCESS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_ACCESS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_I2C_ACCESS_PARAMS(Struct): pass struct_NV2080_CTRL_I2C_ACCESS_PARAMS._fields_ = [ - ('token', ctypes.c_uint32), - ('cmd', ctypes.c_uint32), - ('port', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('data', ctypes.POINTER(None)), - ('status', ctypes.c_uint32), - ('dataBuffSize', ctypes.c_uint32), - ('speed', ctypes.c_uint32), - ('encrClientID', ctypes.c_uint32), + ('token', NvU32), + ('cmd', NvU32), + ('port', NvU32), + ('flags', NvU32), + ('data', NvP64), + ('status', NvU32), + ('dataBuffSize', NvU32), + ('speed', NvU32), + ('encrClientID', NvU32), ] - NV2080_CTRL_I2C_ACCESS_PARAMS = struct_NV2080_CTRL_I2C_ACCESS_PARAMS -class struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS._fields_ = [ - ('head', ctypes.c_uint32), - ('authType', ctypes.c_uint32), - ('status', ctypes.c_uint32), + ('head', NvU32), + ('authType', NvU32), + ('status', NvU32), ] - NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS = struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS -GMMU_FMT_MAX_LEVELS = 6 # macro -# def NV90F1_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x90F1,NV90F1_CTRL_##cat,idx) -NV90F1_CTRL_RESERVED = (0x00) # macro -NV90F1_CTRL_VASPACE = (0x01) # macro -NV90F1_CTRL_CMD_NULL = (0x90f10000) # macro -NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT = (0x90f10101) # macro -NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID = (0x1) # macro -NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO = (0x90f10102) # macro -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE = 0x0 # macro -# NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 = NVBIT64 ( 0 ) # macro -NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES = (0x90f10103) # macro -NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID = (0x3) # macro -NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES = (0x90f10104) # macro -NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID = (0x4) # macro -NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF = (0x90f10105) # macro -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID = (0x5) # macro -NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES = (0x90f10106) # macro -NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID = (0x6) # macro -NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE = (0x90f10107) # macro -NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID = (0x7) # macro -NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO = (0x90f10108) # macro -NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01) # macro -NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG = (0x20800a1c) # macro -NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER = (0x20800a1d) # macro -NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES = 64 # macro -NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1D) # macro -NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER = (0x20800a1e) # macro -NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1E) # macro -NV2080_CTRL_INTERNAL_GR_MAX_ENGINES = 8 # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x20) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS = (0x20800a1f) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID = (0x1F) # macro -NV2080_CTRL_INTERNAL_GR_MAX_SM = 240 # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER = (0x20800a22) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x22) # macro -NV2080_CTRL_CMD_INTERNAL_MAX_BSPS = 8 # macro -NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS = 8 # macro -NV2080_CTRL_INTERNAL_GR_MAX_GPC = 12 # macro -NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT = 10 # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x27) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS = (0x20800a26) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x26) # macro -NV2080_CTRL_KGR_MAX_BUFFER_PTES = 128 # macro -NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES = (0x20800a28) # macro -NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x2B) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO = (0x20800a2a) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID = (0x2A) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2D) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO = (0x20800a2c) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2C) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2F) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO = (0x20800a2e) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2E) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x31) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS = (0x20800a30) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x30) # macro -NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = 0x1a # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x33) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO = (0x20800a32) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x32) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x35) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER = (0x20800a34) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x34) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO = (0x20800a36) # macro -NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX = 16 # macro -NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID = (0x36) # macro -NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE = (0x20800a37) # macro -NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE = (0x20800a38) # macro -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x37) # macro -NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET = (0x20800a39) # macro -NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET = (0x20800a3a) # macro -NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET = (0x20800a3b) # macro -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID = (0x3A) # macro -NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x3B) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE = (0x20800a3d) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3C) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3D) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3E) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES = (0x20800a3f) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3F) # macro -NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES = 512 # macro -NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE = (0x20800a40) # macro -NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x40) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP = (0x20800a41) # macro -NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE = 4096 # macro -NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES = 4096 # macro -NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID = (0x41) # macro -NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x43) # macro -NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a44) # macro -NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a43) # macro -NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x45) # macro -NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR = (0x20800a46) # macro -NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x46) # macro -NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES = (0x20800a48) # macro -NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x48) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM = (0x20800a49) # macro -NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID = (0x49) # macro -NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS = (0x20800a4a) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION = (0x20800a4b) # macro -NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4B) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE = (0x20800a4c) # macro -NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID = (0x4C) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR = (0x20800a4d) # macro -NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID = (0x4D) # macro -NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES = 60 # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x4F) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM = (0x20800a51) # macro -NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID = (0x51) # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE = 4 # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x52) # macro -NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS = 2 # macro -NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID = 64 # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS = (0x20800a53) # macro -NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO = (0x20800a54) # macro -NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO = (0x20800a55) # macro -NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE = (0x00000000) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM = (0x00000001) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 = (0x00000002) # macro -NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 = (0x00000003) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR = (0x20800a70) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL = (0x20800a71) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID = (0x71) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE = (0x20800a72) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID = (0x72) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX = (0x20800a73) # macro -NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID = (0x73) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING = (0x20800a74) # macro -NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x74) # macro -NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING = (0x20800a75) # macro -NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x75) # macro -NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES = (0x20800a57) # macro -NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES = 128 # macro -NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID = (0x57) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER = (0x20800a58) # macro -NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID = (0x58) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO = (0x20800a59) # macro -NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x59) # macro -NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES = (0x20800a5a) # macro -NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x5A) # macro -NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE = (0x20800a5b) # macro -NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID = (0x5B) # macro -NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE = (0x20800a5c) # macro -NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE = 128 # macro -# NV2080_INTR_INVALID_SUBTREE = NV_U8_MAX # macro -NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID = (0x5C) # macro -NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR = (0x00000000) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK = (0x20800a98) # macro -NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID = (0x98) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET = (0x20800a99) # macro -NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID = (0x99) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES = (0x20800a5d) # macro -NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID = (0x5D) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a60) # macro -NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID = 15 # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x60) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS = (0x20800a61) # macro -NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID = (0x61) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES = (0x20800a63) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x63) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES = (0x20800a65) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x65) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a66) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x66) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a68) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x68) # macro -NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a67) # macro -NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x67) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE = (0x20800a6b) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE = 8 # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID = (0x6B) # macro -NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT = (0x20800a6a) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x20800a7a) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR = (0x20800a7c) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE = (0x20800a81) # macro -NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x81) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X = (0x20800a9a) # macro -NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID = (0x9A) # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE = 0 # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK = 1 # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST = 1 # macro -NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM = (0x2) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL = (0x20800a7e) # macro -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7E) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS = (0x20800a7f) # macro -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID = (0x7F) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO = (0x20800a80) # macro -NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID = (0x80) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER = (0x20800a9b) # macro -NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES = 256 # macro -NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9B) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER = (0x20800a9c) # macro -NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE = (0x00000000) # macro -NV2080_CTRL_FAULT_BUFFER_REPLAYABLE = (0x00000001) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9d) # macro -NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES = 3000 # macro -NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9D) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9e) # macro -NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9E) # macro -NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER = (0x20800a9f) # macro -NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID = (0x9F) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X = (0x20800aa0) # macro -NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID = (0xA0) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X = (0x20800aa1) # macro -NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID = (0xA1) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO = (0x20800aa2) # macro -NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES = 8 # macro -NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 12 # macro -NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0xA2) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE = (0x20800aa3) # macro -NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0xA3) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE = (0x20800aa4) # macro -NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA4) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES = (0x20800aa5) # macro -NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA5) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES = (0x20800aa6) # macro -NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA6) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x20800a69) # macro -NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x69) # macro -NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa7) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa8) # macro -NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE = (0x20800aa9) # macro -NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE = (0x20800aaa) # macro -NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE = 4 # macro -NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA7) # macro -NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA8) # macro -NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA9) # macro -NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xAA) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT = (0x20800a6c) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID = (0x6c) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL = (0x00000001) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST = (0x00000002) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST = (0x00000004) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL = (0x00000008) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN = (0x00000010) # macro -NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL = (0x00000020) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES = (0x20800a6d) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO = (0x20800aac) # macro -NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xac) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG = (0x20800a88) # macro -NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID = (0x88) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS = (0x20800a8a) # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE = 32 # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID = (0x8a) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS = (0x20800a8b) # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID = (0x8b) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID = (0x20800a8c) # macro -NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID = (0x8c) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG = (0x20800a8d) # macro -NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID = (0x8d) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR = (0x20800aad) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID = (0xae) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR = (0x20800aae) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS = (0x20800ab0) # macro -NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID = (0xb0) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT = (0x20800ab1) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE = 32 # macro -NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID = (0xB1) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS = (0x20800a6e) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE = (0x20800a6f) # macro -NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID = (0x6f) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO = (0x20800ab2) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_MAP = (0x20800ab3) # macro -NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX = 1 # macro -NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID = (0xB3) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP = (0x20800ab4) # macro -NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID = (0xB4) # macro -NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS = (0x20800ab5) # macro -NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB5) # macro -NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS = (0x20800ab6) # macro -NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB6) # macro -NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS = (0x20800ab8) # macro -NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB8) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO = (0x20800ab9) # macro -NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID = (0xB9) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE = (0x20800a76) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x76) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE = (0x20800a77) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x77) # macro -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBB) # macro -NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES = (0x20800aba) # macro -NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBA) # macro -NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE = (0x20800abd) # macro -NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID = (0xBD) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT = (0x20800abe) # macro -NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID = (0xBE) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS = (0x20800abf) # macro -NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID = (0xBF) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS = (0x20800ac0) # macro -NV2080_MAX_NUM_HEADS = 4 # macro -NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID = (0xC0) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC = (0x20800ac1) # macro -NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID = (0xC1) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES = (0x20800ac4) # macro -NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID = (0xC4) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID = (0x20800ac9) # macro -NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID = (0xC9) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC = (0x20800aca) # macro -NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID = (0xCA) # macro -NV2080_CTRL_CMD_INTERNAL_FBSR_INIT = (0x20800ac2) # macro -NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID = (0xC2) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING = (0x20800ac3) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID = (0xC3) # macro -NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB = (0x20800ac5) # macro -NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID = (0xC5) # macro -NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD = (0x20800ac6) # macro -NV2080_CTRL_ACPI_DSM_READ_SIZE = (0x1000) # macro -NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID = (0xC6) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC7) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL = (0x20800ac7) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC8) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL = (0x20800ac8) # macro -NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE = (0x20800acb) # macro -NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID = (0xCB) # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR = 0x00 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM = 0x01 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI = 0x02 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD = 0x00 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT = 0x01 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR = 0x02 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET = 0x03 # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC = (0x20800acc) # macro -NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID = (0xCC) # macro -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC = (0x20800acd) # macro -NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID = (0xCD) # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS = 0x00 # macro -NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS = 0x01 # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE = (0x20800ace) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCE) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE = (0x20800acf) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCF) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT = (0x20800ad0) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID = (0xD0) # macro -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT = (0x20800ad1) # macro -NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID = (0xD1) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE = (0x20800ad2) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID = (0xD2) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 = (0x20800ad3) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID = (0xD3) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO = (0x20800ad4) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID = (0xD4) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING = (0x20800ad5) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID = (0xD5) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE = (0x20800ad6) # macro -NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID = (0xD6) # macro -NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE = (0x2080a7d7) # macro -NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID = (0xD7) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT = (0x20800a7b) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS = (0x20800ad8) # macro -NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xD8) # macro -NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS = (0x20800adb) # macro -NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID = (0xDB) # macro -NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS = (0x20800adc) # macro -NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID = (0xDC) # macro -NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE = (0x20800add) # macro -NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL = (0x20800ade) # macro -NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID = (0xDE) # macro -NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA = (0x20800adf) # macro -MAX_EDID_SIZE_FROM_SBIOS = 512 # macro -NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID = (0xDF) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED = (0x20800af0) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET = (0x20800af1) # macro -NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET = (0x20800af2) # macro -NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF4) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO = (0x208001f4) # macro -NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF5) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = (0x208001f5) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE = (0x208001f6) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE = (0x208001f7) # macro -NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF8) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE = (0x208001f8) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE = (0x208001f9) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO = (0x20800af3) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xF3) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS = (0x20800ae1) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE = 3 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL = 0 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER = 1 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER = 2 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT = 3 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT = 6 # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID = (0xE1) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS = (0x20800ae2) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID = (0xE2) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS = (0x20800ae5) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0xE5) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION = (0x20800ae6) # macro -NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0xE6) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE = (0x20800ae7) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID = (0xE7) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY = (0x20800ae8) # macro -NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID = (0xE8) # macro -NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID = (0x20800aef) # macro -NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID = (0xEF) # macro -NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP = (0x20800afa) # macro -CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES = (0x10) # macro -NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID = (0xFA) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG = (0x20800afb) # macro -NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFB) # macro -NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG = (0x20800afc) # macro -NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFC) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO = (0x20800afd) # macro -NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID = (0xFD) # macro -NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID = (0xFE) # macro -NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA = (0x20800afe) # macro -NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID = (0xFF) # macro -NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL = (0x20800aff) # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID = (0xE3) # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST = 0x00 # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST = 0x01 # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP = 0x02 # macro -NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = (0x208001e3) # macro -NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID = (0xAF) # macro -NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES = (0x20800aaf) # macro -NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND = (0x20800ae4) # macro -NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0xE4) # macro -NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID = (0xE9) # macro -NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER = (0x20800ae9) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY = (0x20800aea) # macro -NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID = (0xEA) # macro -NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID = (0xEB) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP = (0x20800aeb) # macro -NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0xEC) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM = (0x20800aec) # macro -NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID = (0xED) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR = (0x20800aed) # macro -NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM = (0x20800a79) # macro -NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID = (0x79) # macro -NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID = (0x14) # macro -NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE = (0x20800a14) # macro -NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID = (0xEE) # macro -NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA = (0x20800aee) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER = (0x20800a21) # macro -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x21) # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF = 0x00 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS = 0x01 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE = 0x02 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT = 0x03 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY = 0x04 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL = 0x05 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT = 0x06 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET = 0x07 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM = 0x08 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM = 0x09 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP = 0x0A # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE = 0x0B # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE = 0x0C # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS = 0x0E # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT = 0x0F # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE = 0x10 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN = 0x11 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP = 0x12 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 = 0x13 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE = 0x14 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE = 0x15 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE = 0x16 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE = 0x17 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT = 0x18 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN = 0x19 # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL = 0x1A # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 = 0x1B # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI = 0x1C # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING = 0x1D # macro -NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID = 0xFF # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS = 0x00 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN = 0x05 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE = 0x06 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF = 0x07 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE = 0x08 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE = 0x09 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY = 0x0A # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ = 0x0B # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN = 0x0C # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS = 0x0D # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS = 0x00 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER = 0x04 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN = 0x05 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE = 0x06 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF = 0x07 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL = 0x08 # macro -NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM = 0x09 # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM = 6 # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE = (0x7) # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE = 0x00 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE = 0x01 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE = 0x02 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE = 0x03 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE = 0x04 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE = 0x05 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE = 0x06 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE = 0x07 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT = 0x08 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT = 0x09 # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN = 0x0A # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN = 0x0B # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE = 0x0C # macro -NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD = 0x0D # macro -NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID = (0x24) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK = (0x20800a24) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID = (0x25) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID = (0x20800a25) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID = (0x29) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED = (0x20800a29) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM = 0x0 # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET = 0x1 # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX = (0x20800a42) # macro -NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x4E) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER = (0x20800a4e) # macro -NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x50) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER = (0x20800a50) # macro -NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID = (0x20800a56) # macro -NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE = (81) # macro -NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM = 0x1 # macro -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER = 0x2 # macro -NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID = (0x5F) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING = (0x20800a5f) # macro -NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID = (0x62) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE = (0x20800a62) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET = (0x00000000) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE = (0x00000001) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE = (0x00000002) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID = (0x64) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY = (0x20800a64) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID = (0x78) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG = (0x20800a78) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID = (0x7D) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK = (0x20800a7d) # macro -NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID = (0x82) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION = (0x20800a82) # macro -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY = (0x20800a83) # macro -NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x84) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI = (0x20800a84) # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE = 64 # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID = (0x85) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET = (0x20800a85) # macro -NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x86) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI = (0x20800a86) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x87) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO = (0x20800a87) # macro -NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW = 6 # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x8E) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO = (0x20800a8e) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID = (0x8F) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED = (0x20800a8f) # macro -NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID = (0x90) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED = (0x20800a90) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT = (0x00000000) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT = (0x00000001) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE = (0x00000002) # macro -NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID = (0x91) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS = (0x20800a91) # macro -NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID = (0x92) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS = (0x20800a92) # macro -NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID = (0x93) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO = (0x20800a93) # macro -NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID = (0x94) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM = (0x20800a94) # macro -NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID = (0x95) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS = (0x20800a95) # macro -NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID = (0x96) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS = (0x20800a96) # macro -NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97) # macro -NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB) # macro -NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab) # macro -class struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pFmt', ctypes.POINTER(None)), -] - -NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS -class struct_NV_CTRL_VASPACE_PAGE_LEVEL(Structure): - pass - -class struct_MMU_FMT_LEVEL(Structure): - pass - -struct_MMU_FMT_LEVEL._pack_ = 1 # source:False -struct_MMU_FMT_LEVEL._fields_ = [ - ('virtAddrBitLo', ctypes.c_ubyte), - ('virtAddrBitHi', ctypes.c_ubyte), - ('entrySize', ctypes.c_ubyte), - ('bPageTable', ctypes.c_ubyte), - ('numSubLevels', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pageLevelIdTag', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('subLevels', ctypes.POINTER(struct_MMU_FMT_LEVEL)), -] - -struct_NV_CTRL_VASPACE_PAGE_LEVEL._pack_ = 1 # source:False -struct_NV_CTRL_VASPACE_PAGE_LEVEL._fields_ = [ - ('pFmt', ctypes.POINTER(struct_MMU_FMT_LEVEL)), - ('levelFmt', struct_MMU_FMT_LEVEL), - ('sublevelFmt', struct_MMU_FMT_LEVEL * 2), - ('physAddress', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), - ('entryIndex', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV_CTRL_VASPACE_PAGE_LEVEL = struct_NV_CTRL_VASPACE_PAGE_LEVEL -class struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('virtAddress', ctypes.c_uint64), - ('pageSize', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('numLevels', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('levels', struct_NV_CTRL_VASPACE_PAGE_LEVEL * 6), -] - -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS -class struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), -] - -NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS -class struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), -] - -NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(Structure): - pass - -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('pageShift', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), - ('numLevelsToCopy', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('levels', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0 * 6), -] - -NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS -class struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('requiredVaRange', ctypes.c_uint64), -] - -NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS -class struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('bytesFree', ctypes.c_uint64), - ('bytesTotal', ctypes.c_uint64), - ('largestFreeOffset', ctypes.c_uint64), - ('largestFreeSize', ctypes.c_uint64), - ('usableBytesFree', ctypes.c_uint64), - ('numFreeBlocks', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS._fields_ = [ - ('feHwSysCap', ctypes.c_uint32), - ('windowPresentMask', ctypes.c_uint32), - ('bFbRemapperEnabled', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numHeads', ctypes.c_uint32), - ('i2cPort', ctypes.c_uint32), - ('internalDispActiveMask', ctypes.c_uint32), - ('embeddedDisplayPortMask', ctypes.c_uint32), - ('bExternalMuxSupported', ctypes.c_ubyte), - ('bInternalMuxSupported', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('numDispChannels', ctypes.c_uint32), + ('feHwSysCap', NvU32), + ('windowPresentMask', NvU32), + ('bFbRemapperEnabled', NvBool), + ('numHeads', NvU32), + ('i2cPort', NvU32), + ('internalDispActiveMask', NvU32), + ('embeddedDisplayPortMask', NvU32), + ('bExternalMuxSupported', NvBool), + ('bInternalMuxSupported', NvBool), + ('numDispChannels', NvU32), ] - NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS._fields_ = [ - ('bOneToOneComptagLineAllocation', ctypes.c_ubyte), - ('bUseOneToFourComptagLineAllocation', ctypes.c_ubyte), - ('bUseRawModeComptaglineAllocation', ctypes.c_ubyte), - ('bDisableCompbitBacking', ctypes.c_ubyte), - ('bDisablePostL2Compression', ctypes.c_ubyte), - ('bEnabledEccFBPA', ctypes.c_ubyte), - ('bL2PreFill', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('l2CacheSize', ctypes.c_uint64), - ('bFbpaPresent', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('comprPageSize', ctypes.c_uint32), - ('comprPageShift', ctypes.c_uint32), - ('ramType', ctypes.c_uint32), - ('ltcCount', ctypes.c_uint32), - ('ltsPerLtcCount', ctypes.c_uint32), + ('bOneToOneComptagLineAllocation', NvBool), + ('bUseOneToFourComptagLineAllocation', NvBool), + ('bUseRawModeComptaglineAllocation', NvBool), + ('bDisableCompbitBacking', NvBool), + ('bDisablePostL2Compression', NvBool), + ('bEnabledEccFBPA', NvBool), + ('bL2PreFill', NvBool), + ('l2CacheSize', NvU64), + ('bFbpaPresent', NvBool), + ('comprPageSize', NvU32), + ('comprPageShift', NvU32), + ('ramType', NvU32), + ('ltcCount', NvU32), + ('ltsPerLtcCount', NvU32), ] - NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS._fields_ = [ - ('accessCounterIndex', ctypes.c_uint32), - ('bufferSize', ctypes.c_uint32), - ('bufferPteArray', ctypes.c_uint64 * 64), + ('accessCounterIndex', NvU32), + ('bufferSize', NvU32), + ('bufferPteArray', (NvU64 * 64)), ] - NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS._fields_ = [ - ('accessCounterIndex', ctypes.c_uint32), + ('accessCounterIndex', NvU32), ] - NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 23), + ('capsTbl', (NvU8 * 23)), ] - NV2080_CTRL_INTERNAL_STATIC_GR_CAPS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineCaps', struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS._fields_ = [ + ('engineCaps', (NV2080_CTRL_INTERNAL_STATIC_GR_CAPS * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER(Structure): - pass - -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0._fields_ = [ - ('gpcId', ctypes.c_uint16), - ('localTpcId', ctypes.c_uint16), - ('localSmId', ctypes.c_uint16), - ('globalTpcId', ctypes.c_uint16), - ('virtualGpcId', ctypes.c_uint16), - ('migratableTpcId', ctypes.c_uint16), +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER(Struct): pass +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId._fields_ = [ + ('gpcId', NvU16), + ('localTpcId', NvU16), + ('localSmId', NvU16), + ('globalTpcId', NvU16), + ('virtualGpcId', NvU16), + ('migratableTpcId', NvU16), ] - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER._pack_ = 1 # source:False struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER._fields_ = [ - ('globalSmId', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0 * 240), - ('numSm', ctypes.c_uint16), - ('numTpc', ctypes.c_uint16), + ('globalSmId', (struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId * 240)), + ('numSm', NvU16), + ('numTpc', NvU16), ] - NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('globalSmOrder', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS._fields_ = [ + ('globalSmOrder', (NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS -class struct_NV2080_CTRL_INTERNAL_BSP_CAPS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BSP_CAPS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BSP_CAPS(Struct): pass struct_NV2080_CTRL_INTERNAL_BSP_CAPS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 8), + ('capsTbl', (NvU8 * 8)), ] - NV2080_CTRL_INTERNAL_BSP_CAPS = struct_NV2080_CTRL_INTERNAL_BSP_CAPS -class struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS._fields_ = [ - ('caps', struct_NV2080_CTRL_INTERNAL_BSP_CAPS * 8), - ('valid', ctypes.c_ubyte * 8), + ('caps', (NV2080_CTRL_INTERNAL_BSP_CAPS * 8)), + ('valid', (NvBool * 8)), ] - NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_MSENC_CAPS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MSENC_CAPS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MSENC_CAPS(Struct): pass struct_NV2080_CTRL_INTERNAL_MSENC_CAPS._fields_ = [ - ('capsTbl', ctypes.c_ubyte * 4), + ('capsTbl', (NvU8 * 4)), ] - NV2080_CTRL_INTERNAL_MSENC_CAPS = struct_NV2080_CTRL_INTERNAL_MSENC_CAPS -class struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS._fields_ = [ - ('caps', struct_NV2080_CTRL_INTERNAL_MSENC_CAPS * 8), - ('valid', ctypes.c_ubyte * 8), + ('caps', (NV2080_CTRL_INTERNAL_MSENC_CAPS * 8)), + ('valid', (NvBool * 8)), ] - NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS._fields_ = [ - ('gpcMask', ctypes.c_uint32), - ('tpcMask', ctypes.c_uint32 * 12), - ('tpcCount', ctypes.c_uint32 * 12), - ('physGpcMask', ctypes.c_uint32), - ('mmuPerGpc', ctypes.c_uint32 * 12), - ('tpcToPesMap', ctypes.c_uint32 * 10), - ('numPesPerGpc', ctypes.c_uint32 * 12), - ('zcullMask', ctypes.c_uint32 * 12), - ('physGfxGpcMask', ctypes.c_uint32), - ('numGfxTpc', ctypes.c_uint32), + ('gpcMask', NvU32), + ('tpcMask', (NvU32 * 12)), + ('tpcCount', (NvU32 * 12)), + ('physGpcMask', NvU32), + ('mmuPerGpc', (NvU32 * 12)), + ('tpcToPesMap', (NvU32 * 10)), + ('numPesPerGpc', (NvU32 * 12)), + ('zcullMask', (NvU32 * 12)), + ('physGfxGpcMask', NvU32), + ('numGfxTpc', NvU32), ] - NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('floorsweepingMasks', struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS._fields_ = [ + ('floorsweepingMasks', (NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS -class struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS(Struct): pass struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS._fields_ = [ - ('hUserClient', ctypes.c_uint32), - ('hChannel', ctypes.c_uint32), - ('bufferType', ctypes.c_uint32), - ('firstPage', ctypes.c_uint32), - ('numPages', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physAddrs', ctypes.c_uint64 * 128), - ('bNoMorePages', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), + ('hUserClient', NvHandle), + ('hChannel', NvHandle), + ('bufferType', NvU32), + ('firstPage', NvU32), + ('numPages', NvU32), + ('physAddrs', (NvU64 * 128)), + ('bNoMorePages', NvBool), ] - NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS = struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO._fields_ = [ - ('base', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('alignment', ctypes.c_uint64), - ('addressSpace', ctypes.c_uint32), - ('cpuCacheAttrib', ctypes.c_uint32), -] - -NV2080_CTRL_INTERNAL_MEMDESC_INFO = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO -class struct_NV2080_CTRL_INTERNAL_GR_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GR_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_GR_INFO._fields_ = [ - ('index', ctypes.c_uint32), - ('data', ctypes.c_uint32), + ('index', NvU32), + ('data', NvU32), ] - NV2080_CTRL_INTERNAL_GR_INFO = struct_NV2080_CTRL_INTERNAL_GR_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('infoList', struct_NV2080_CTRL_INTERNAL_GR_INFO * 58), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO._fields_ = [ + ('infoList', (NV2080_CTRL_INTERNAL_GR_INFO * 58)), +] NV2080_CTRL_INTERNAL_STATIC_GR_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS._fields_ = [ + ('engineInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_INFO * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO._fields_ = [ - ('widthAlignPixels', ctypes.c_uint32), - ('heightAlignPixels', ctypes.c_uint32), - ('pixelSquaresByAliquots', ctypes.c_uint32), - ('aliquotTotal', ctypes.c_uint32), - ('zcullRegionByteMultiplier', ctypes.c_uint32), - ('zcullRegionHeaderSize', ctypes.c_uint32), - ('zcullSubregionHeaderSize', ctypes.c_uint32), - ('subregionCount', ctypes.c_uint32), - ('subregionWidthAlignPixels', ctypes.c_uint32), - ('subregionHeightAlignPixels', ctypes.c_uint32), + ('widthAlignPixels', NvU32), + ('heightAlignPixels', NvU32), + ('pixelSquaresByAliquots', NvU32), + ('aliquotTotal', NvU32), + ('zcullRegionByteMultiplier', NvU32), + ('zcullRegionHeaderSize', NvU32), + ('zcullSubregionHeaderSize', NvU32), + ('subregionCount', NvU32), + ('subregionWidthAlignPixels', NvU32), + ('subregionHeightAlignPixels', NvU32), ] - NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineZcullInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS._fields_ = [ + ('engineZcullInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO._fields_ = [ - ('ropUnitCount', ctypes.c_uint32), - ('ropOperationsFactor', ctypes.c_uint32), - ('ropOperationsCount', ctypes.c_uint32), + ('ropUnitCount', NvU32), + ('ropOperationsFactor', NvU32), + ('ropOperationsCount', NvU32), ] - NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineRopInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS._fields_ = [ + ('engineRopInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS._fields_ = [ - ('mask', ctypes.c_uint32 * 12), + ('mask', (NvU32 * 12)), ] - NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('enginePpcMasks', struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS._fields_ = [ + ('enginePpcMasks', (NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS -class struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO._fields_ = [ - ('size', ctypes.c_uint32), - ('alignment', ctypes.c_uint32), + ('size', NvU32), + ('alignment', NvU32), ] - NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO = struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engine', struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO * 26), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO._fields_ = [ + ('engine', (NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO * 26)), +] NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('engineContextBuffersInfo', struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS._fields_ = [ + ('engineContextBuffersInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER._fields_ = [ - ('imla0', ctypes.c_ubyte), - ('fmla16', ctypes.c_ubyte), - ('dp', ctypes.c_ubyte), - ('fmla32', ctypes.c_ubyte), - ('ffma', ctypes.c_ubyte), - ('imla1', ctypes.c_ubyte), - ('imla2', ctypes.c_ubyte), - ('imla3', ctypes.c_ubyte), - ('imla4', ctypes.c_ubyte), + ('imla0', NvU8), + ('fmla16', NvU8), + ('dp', NvU8), + ('fmla32', NvU8), + ('ffma', NvU8), + ('imla1', NvU8), + ('imla2', NvU8), + ('imla3', NvU8), + ('imla4', NvU8), ] - NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('smIssueRateModifier', struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._fields_ = [ + ('smIssueRateModifier', (NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS._fields_ = [ - ('chipSubRev', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('emulationRev1', ctypes.c_uint32), - ('isCmpSku', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('pciDeviceId', ctypes.c_uint32), - ('pciSubDeviceId', ctypes.c_uint32), - ('pciRevisionId', ctypes.c_uint32), - ('regBases', ctypes.c_uint32 * 16), + ('chipSubRev', NvU8), + ('emulationRev1', NvU32), + ('isCmpSku', NvBool), + ('pciDeviceId', NvU32), + ('pciSubDeviceId', NvU32), + ('pciRevisionId', NvU32), + ('regBases', (NvU32 * 16)), ] - NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('bEnable', NvBool), ] - NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS._fields_ = [ - ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), - ('offset', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO), + ('offset', NvU32), ] - NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE._fields_ = [ - ('fecsRecordSize', ctypes.c_uint32), + ('fecsRecordSize', NvU32), ] - NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fecsRecordSize', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS._fields_ = [ + ('fecsRecordSize', (NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES._fields_ = [ - ('fecsRecordSize', ctypes.c_uint32), - ('timestampHiTagMask', ctypes.c_uint32), - ('timestampHiTagShift', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('timestampVMask', ctypes.c_uint64), - ('numLowerBitsZeroShift', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), + ('fecsRecordSize', NvU32), + ('timestampHiTagMask', NvU32), + ('timestampHiTagShift', NvU8), + ('timestampVMask', NvU64), + ('numLowerBitsZeroShift', NvU8), ] - NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fecsTraceDefines', struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS._fields_ = [ + ('fecsTraceDefines', (NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS -class struct_NV2080_CTRL_INTERNAL_DEVICE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DEVICE_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DEVICE_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_DEVICE_INFO._fields_ = [ - ('faultId', ctypes.c_uint32), - ('instanceId', ctypes.c_uint32), - ('typeEnum', ctypes.c_uint32), - ('resetId', ctypes.c_uint32), - ('devicePriBase', ctypes.c_uint32), - ('isEngine', ctypes.c_uint32), - ('rlEngId', ctypes.c_uint32), - ('runlistPriBase', ctypes.c_uint32), - ('groupId', ctypes.c_uint32), - ('ginTargetId', ctypes.c_uint32), - ('deviceBroadcastPriBase', ctypes.c_uint32), - ('groupLocalInstanceId', ctypes.c_uint32), + ('faultId', NvU32), + ('instanceId', NvU32), + ('typeEnum', NvU32), + ('resetId', NvU32), + ('devicePriBase', NvU32), + ('isEngine', NvU32), + ('rlEngId', NvU32), + ('runlistPriBase', NvU32), + ('groupId', NvU32), + ('ginTargetId', NvU32), + ('deviceBroadcastPriBase', NvU32), + ('groupLocalInstanceId', NvU32), ] - NV2080_CTRL_INTERNAL_DEVICE_INFO = struct_NV2080_CTRL_INTERNAL_DEVICE_INFO -class struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [ - ('numEntries', ctypes.c_uint32), - ('deviceInfoTable', struct_NV2080_CTRL_INTERNAL_DEVICE_INFO * 512), + ('numEntries', NvU32), + ('deviceInfoTable', (NV2080_CTRL_INTERNAL_DEVICE_INFO * 512)), ] - NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS._fields_ = [ - ('userRegisterAccessMapSize', ctypes.c_uint32), - ('compressedSize', ctypes.c_uint32), - ('compressedData', ctypes.c_ubyte * 4096), - ('profilingRangesSize', ctypes.c_uint32), - ('profilingRanges', ctypes.c_ubyte * 4096), + ('userRegisterAccessMapSize', NvU32), + ('compressedSize', NvU32), + ('compressedData', (NvU8 * 4096)), + ('profilingRangesSize', NvU32), + ('profilingRanges', (NvU8 * 4096)), ] - NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS -class struct_NV2080_CTRL_INTERNAL_NV_RANGE(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NV_RANGE._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NV_RANGE(Struct): pass struct_NV2080_CTRL_INTERNAL_NV_RANGE._fields_ = [ - ('lo', ctypes.c_uint64), - ('hi', ctypes.c_uint64), + ('lo', NvU64), + ('hi', NvU64), ] - NV2080_CTRL_INTERNAL_NV_RANGE = struct_NV2080_CTRL_INTERNAL_NV_RANGE -class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('memAddrRange', NV2080_CTRL_INTERNAL_NV_RANGE), + ('swizzId', NvU32), + ('memAddrRange', NV2080_CTRL_INTERNAL_NV_RANGE), ] - NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS._fields_ = [ - ('bTeardown', ctypes.c_ubyte), + ('bTeardown', NvBool), ] - NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES._fields_ = [ - ('bPerSubCtxheaderSupported', ctypes.c_ubyte), + ('bPerSubCtxheaderSupported', NvBool), ] - NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES -class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('pdbTable', struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES * 8), - ] - +class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS._fields_ = [ + ('pdbTable', (NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES * 8)), +] NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS._fields_ = [ - ('instMemPhysAddr', ctypes.c_uint64), - ('instMemSize', ctypes.c_uint64), - ('instMemAddrSpace', ctypes.c_uint32), - ('instMemCpuCacheAttr', ctypes.c_uint32), + ('instMemPhysAddr', NvU64), + ('instMemSize', NvU64), + ('instMemAddrSpace', NvU32), + ('instMemCpuCacheAttr', NvU32), ] - NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS._fields_ = [ - ('ipVersion', ctypes.c_uint32), + ('ipVersion', NvU32), ] - NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS._fields_ = [ - ('smcMode', ctypes.c_uint32), + ('smcMode', NvU32), ] - NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS._fields_ = [ - ('head', ctypes.c_uint32), - ('rgLineNum', ctypes.c_uint32), - ('intrLine', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('head', NvU32), + ('rgLineNum', NvU32), + ('intrLine', NvU32), + ('bEnable', NvBool), ] - NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS -class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO._fields_ = [ - ('partitionFlag', ctypes.c_uint32), - ('grCount', ctypes.c_uint32), - ('gfxGrCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('gfxGpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('ceCount', ctypes.c_uint32), - ('nvEncCount', ctypes.c_uint32), - ('nvDecCount', ctypes.c_uint32), - ('nvJpgCount', ctypes.c_uint32), - ('nvOfaCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('validCTSIdMask', ctypes.c_uint64), - ('validGfxCTSIdMask', ctypes.c_uint64), + ('partitionFlag', NvU32), + ('grCount', NvU32), + ('gfxGrCount', NvU32), + ('gpcCount', NvU32), + ('virtualGpcCount', NvU32), + ('gfxGpcCount', NvU32), + ('veidCount', NvU32), + ('smCount', NvU32), + ('ceCount', NvU32), + ('nvEncCount', NvU32), + ('nvDecCount', NvU32), + ('nvJpgCount', NvU32), + ('nvOfaCount', NvU32), + ('validCTSIdMask', NvU64), + ('validGfxCTSIdMask', NvU64), ] - NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS._fields_ = [ - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('table', struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO * 60), + ('count', NvU32), + ('table', (NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO * 60)), ] - NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS._fields_ = [ - ('partitionableMemSize', ctypes.c_uint64), - ('bottomRsvdSize', ctypes.c_uint64), - ('topRsvdSize', ctypes.c_uint64), - ('partitionableStartAddr', ctypes.c_uint64), - ('partitionableEndAddr', ctypes.c_uint64), + ('partitionableMemSize', NvU64), + ('bottomRsvdSize', NvU64), + ('topRsvdSize', NvU64), + ('partitionableStartAddr', NvU64), + ('partitionableEndAddr', NvU64), ] - NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS._fields_ = [ - ('engineMask', ctypes.c_uint64 * 4), + ('engineMask', (NvU64 * 4)), ] - NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS._fields_ = [ - ('rlBuffers', struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2 * 64), - ('runlistIdMask', ctypes.c_uint64), - ('swizzId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('rlBuffers', ((NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2) * 64)), + ('runlistIdMask', NvU64), + ('swizzId', NvU32), ] - NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS(Structure): - pass - -class struct_TEGRA_IMP_IMPORT_DATA(Structure): - pass - -class struct_DRAM_CLK_INSTANCE(Structure): - pass - -struct_DRAM_CLK_INSTANCE._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS(Struct): pass +class struct_TEGRA_IMP_IMPORT_DATA(Struct): pass +TEGRA_IMP_IMPORT_DATA = struct_TEGRA_IMP_IMPORT_DATA +class struct_DRAM_CLK_INSTANCE(Struct): pass +DRAM_CLK_INSTANCE = struct_DRAM_CLK_INSTANCE struct_DRAM_CLK_INSTANCE._fields_ = [ - ('dram_clk_freq_khz', ctypes.c_uint32), - ('mchub_clk_khz', ctypes.c_uint32), - ('mc_clk_khz', ctypes.c_uint32), - ('max_iso_bw_kbps', ctypes.c_uint32), - ('switch_latency_ns', ctypes.c_uint32), + ('dram_clk_freq_khz', NvU32), + ('mchub_clk_khz', NvU32), + ('mc_clk_khz', NvU32), + ('max_iso_bw_kbps', NvU32), + ('switch_latency_ns', NvU32), ] - -struct_TEGRA_IMP_IMPORT_DATA._pack_ = 1 # source:False struct_TEGRA_IMP_IMPORT_DATA._fields_ = [ - ('max_iso_bw_kbps', ctypes.c_uint32), - ('num_dram_channels', ctypes.c_uint32), - ('num_dram_clk_entries', ctypes.c_uint32), - ('dram_clk_instance', struct_DRAM_CLK_INSTANCE * 24), + ('max_iso_bw_kbps', NvU32), + ('num_dram_channels', NvU32), + ('num_dram_clk_entries', NvU32), + ('dram_clk_instance', (DRAM_CLK_INSTANCE * 24)), ] - -struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS._fields_ = [ - ('tegraImpImportData', struct_TEGRA_IMP_IMPORT_DATA), + ('tegraImpImportData', TEGRA_IMP_IMPORT_DATA), ] - NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS._fields_ = [ - ('pciDeviceId', ctypes.c_uint16), - ('pciSubDeviceId', ctypes.c_uint16), - ('iseGPUBridge', ctypes.c_ubyte), - ('approvedBusType', ctypes.c_ubyte), + ('pciDeviceId', NvU16), + ('pciSubDeviceId', NvU16), + ('iseGPUBridge', NvBool), + ('approvedBusType', NvU8), ] - NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS._fields_ = [ - ('local2Remote', ctypes.c_uint32), - ('remote2Local', ctypes.c_uint32), - ('localP2PDomainRemoteAddr', ctypes.c_uint64), - ('remoteP2PDomainLocalAddr', ctypes.c_uint64), - ('remoteWMBoxLocalAddr', ctypes.c_uint64), - ('p2pWmbTag', ctypes.c_uint64), - ('bNeedWarBug999673', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('local2Remote', NvU32), + ('remote2Local', NvU32), + ('localP2PDomainRemoteAddr', NvU64), + ('remoteP2PDomainLocalAddr', NvU64), + ('remoteWMBoxLocalAddr', NvU64), + ('p2pWmbTag', NvU64), + ('bNeedWarBug999673', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS._fields_ = [ - ('local2Remote', ctypes.c_uint32), - ('remote2Local', ctypes.c_uint32), - ('localP2PDomainRemoteAddr', ctypes.c_uint64), - ('remoteP2PDomainLocalAddr', ctypes.c_uint64), - ('remoteWMBoxAddrU64', ctypes.c_uint64), - ('p2pWmbTag', ctypes.c_uint64), + ('local2Remote', NvU32), + ('remote2Local', NvU32), + ('localP2PDomainRemoteAddr', NvU64), + ('remoteP2PDomainLocalAddr', NvU64), + ('remoteWMBoxAddrU64', NvU64), + ('p2pWmbTag', NvU64), ] - NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS -class struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS._fields_ = [ - ('peerIdx', ctypes.c_uint32), - ('bNeedWarBug999673', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('peerIdx', NvU32), + ('bNeedWarBug999673', NvBool), ] - NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS -class struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), + ('peerId', NvU32), ] - NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS -class struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), + ('peerId', NvU32), ] - NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS -class struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('numEntries', ctypes.c_uint32), - ('gpaEntries', ctypes.c_uint64 * 128), - ('spaEntries', ctypes.c_uint64 * 128), + ('gfid', NvU32), + ('numEntries', NvU32), + ('gpaEntries', (NvU64 * 128)), + ('spaEntries', (NvU64 * 128)), ] - NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS = struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS._fields_ = [ - ('addressSpace', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('physicalAddr', ctypes.c_uint64), - ('limit', ctypes.c_uint64), - ('cacheSnoop', ctypes.c_uint32), - ('hclass', ctypes.c_uint32), - ('channelInstance', ctypes.c_uint32), - ('valid', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('pbTargetAperture', ctypes.c_uint32), - ('channelPBSize', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), + ('addressSpace', NvU32), + ('physicalAddr', NvU64), + ('limit', NvU64), + ('cacheSnoop', NvU32), + ('hclass', NvU32), + ('channelInstance', NvU32), + ('valid', NvBool), + ('pbTargetAperture', NvU32), + ('channelPBSize', NvU32), + ('subDeviceId', NvU32), ] - NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS._fields_ = [ - ('replayableFaultBufferSize', ctypes.c_uint32), - ('replayableShadowFaultBufferMetadataSize', ctypes.c_uint32), - ('nonReplayableFaultBufferSize', ctypes.c_uint32), - ('nonReplayableShadowFaultBufferMetadataSize', ctypes.c_uint32), + ('replayableFaultBufferSize', NvU32), + ('replayableShadowFaultBufferMetadataSize', NvU32), + ('nonReplayableFaultBufferSize', NvU32), + ('nonReplayableShadowFaultBufferMetadataSize', NvU32), ] - NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS -class struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS._fields_ = [ - ('moduleIndex', ctypes.c_uint32), - ('size', ctypes.c_uint32), + ('moduleIndex', NvU32), + ('size', NvU32), ] - NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS +enum_NV2080_INTR_CATEGORY = CEnum(ctypes.c_uint32) +NV2080_INTR_CATEGORY_DEFAULT = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_DEFAULT', 0) +NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', 1) +NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', 2) +NV2080_INTR_CATEGORY_RUNLIST = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_RUNLIST', 3) +NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', 4) +NV2080_INTR_CATEGORY_UVM_OWNED = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_UVM_OWNED', 5) +NV2080_INTR_CATEGORY_UVM_SHARED = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_UVM_SHARED', 6) +NV2080_INTR_CATEGORY_ENUM_COUNT = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ENUM_COUNT', 7) -# values for enumeration 'NV2080_INTR_CATEGORY' -NV2080_INTR_CATEGORY__enumvalues = { - 0: 'NV2080_INTR_CATEGORY_DEFAULT', - 1: 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', - 2: 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', - 3: 'NV2080_INTR_CATEGORY_RUNLIST', - 4: 'NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', - 5: 'NV2080_INTR_CATEGORY_UVM_OWNED', - 6: 'NV2080_INTR_CATEGORY_UVM_SHARED', - 7: 'NV2080_INTR_CATEGORY_ENUM_COUNT', -} -NV2080_INTR_CATEGORY_DEFAULT = 0 -NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1 -NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2 -NV2080_INTR_CATEGORY_RUNLIST = 3 -NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4 -NV2080_INTR_CATEGORY_UVM_OWNED = 5 -NV2080_INTR_CATEGORY_UVM_SHARED = 6 -NV2080_INTR_CATEGORY_ENUM_COUNT = 7 -NV2080_INTR_CATEGORY = ctypes.c_uint32 # enum -class struct_NV2080_INTR_CATEGORY_SUBTREE_MAP(Structure): - pass - -struct_NV2080_INTR_CATEGORY_SUBTREE_MAP._pack_ = 1 # source:False +NV2080_INTR_CATEGORY = enum_NV2080_INTR_CATEGORY +class struct_NV2080_INTR_CATEGORY_SUBTREE_MAP(Struct): pass struct_NV2080_INTR_CATEGORY_SUBTREE_MAP._fields_ = [ - ('subtreeStart', ctypes.c_ubyte), - ('subtreeEnd', ctypes.c_ubyte), + ('subtreeStart', NvU8), + ('subtreeEnd', NvU8), ] - NV2080_INTR_CATEGORY_SUBTREE_MAP = struct_NV2080_INTR_CATEGORY_SUBTREE_MAP -class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY(Struct): pass struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY._fields_ = [ - ('engineIdx', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('pmcIntrMask', ctypes.c_uint32), - ('vectorStall', ctypes.c_uint32), - ('vectorNonStall', ctypes.c_uint32), + ('engineIdx', NvU16), + ('pmcIntrMask', NvU32), + ('vectorStall', NvU32), + ('vectorNonStall', NvU32), ] - NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY -class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS._fields_ = [ - ('tableLen', ctypes.c_uint32), - ('table', struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY * 128), - ('subtreeMap', struct_NV2080_INTR_CATEGORY_SUBTREE_MAP * 7), - ('PADDING_0', ctypes.c_ubyte * 2), + ('tableLen', NvU32), + ('table', (NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY * 128)), + ('subtreeMap', (NV2080_INTR_CATEGORY_SUBTREE_MAP * 7)), ] - NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS._fields_ = [ - ('bReservation', ctypes.c_ubyte), + ('bReservation', NvBool), ] - NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS._fields_ = [ - ('bReservation', ctypes.c_ubyte), - ('bClientHandlesGrGating', ctypes.c_ubyte), - ('bRmHandlesIdleSlow', ctypes.c_ubyte), + ('bReservation', NvBool), + ('bClientHandlesGrGating', NvBool), + ('bRmHandlesIdleSlow', NvBool), ] - NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS._fields_ = [ - ('displayMask', ctypes.c_uint32), - ('numHeads', ctypes.c_uint32), + ('displayMask', NvU32), + ('numHeads', NvU32), ] - NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('fbMemPageRanges', struct_NV2080_CTRL_INTERNAL_NV_RANGE * 15), - ] - -NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS._fields_ = [ - ('runlistId', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), +class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS._fields_ = [ + ('fbMemPageRanges', (NV2080_CTRL_INTERNAL_NV_RANGE * 15)), +] +NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS +class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS._fields_ = [ + ('runlistId', NvU32), + ('numChannels', NvU32), ] - NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS._fields_ = [ - ('memBoundaryCfgA', ctypes.c_uint64), - ('memBoundaryCfgB', ctypes.c_uint64), - ('memBoundaryCfgC', ctypes.c_uint32), - ('memBoundaryCfg', ctypes.c_uint32), - ('memBoundaryCfgValInit', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('memBoundaryCfgA', NvU64), + ('memBoundaryCfgB', NvU64), + ('memBoundaryCfgC', NvU32), + ('memBoundaryCfg', NvU32), + ('memBoundaryCfgValInit', NvU32), ] - NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS._fields_ = [ - ('data', ctypes.c_uint32 * 8), + ('data', (NvU32 * 8)), ] - NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), + ('powerState', NvU32), ] - NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X._fields_ = [ - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('duration', ctypes.c_uint32), + ('flags', NvBool), + ('duration', NvU32), ] - NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [ - ('bActivate', ctypes.c_ubyte), + ('bActivate', NvBool), ] - NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('bBridgeless', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('currLimits', ctypes.c_uint32 * 2), + ('flags', NvU32), + ('bBridgeless', NvBool), + ('currLimits', (NvU32 * 2)), ] - NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS._fields_ = [ - ('hysteresisus', ctypes.c_uint64), - ('bHystersisEnable', ctypes.c_ubyte), - ('bSliGpuBoostSyncEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), + ('hysteresisus', NvU64), + ('bHystersisEnable', NvBool), + ('bSliGpuBoostSyncEnable', NvBool), ] - NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hObject', ctypes.c_uint32), - ('faultBufferSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('faultBufferPteArray', ctypes.c_uint64 * 256), + ('hClient', NvHandle), + ('hObject', NvHandle), + ('faultBufferSize', NvU32), + ('faultBufferPteArray', (NvU64 * 256)), ] - NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._fields_ = [ - ('shadowFaultBufferQueuePhysAddr', ctypes.c_uint64), - ('shadowFaultBufferSize', ctypes.c_uint32), - ('shadowFaultBufferMetadataSize', ctypes.c_uint32), - ('shadowFaultBufferPteArray', ctypes.c_uint64 * 3000), - ('shadowFaultBufferType', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('faultBufferSharedMemoryPhysAddr', ctypes.c_uint64), + ('shadowFaultBufferQueuePhysAddr', NvU64), + ('shadowFaultBufferSize', NvU32), + ('shadowFaultBufferMetadataSize', NvU32), + ('shadowFaultBufferPteArray', (NvU64 * 3000)), + ('shadowFaultBufferType', NvU32), + ('faultBufferSharedMemoryPhysAddr', NvU64), ] - NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._fields_ = [ - ('shadowFaultBufferType', ctypes.c_uint32), + ('shadowFaultBufferType', NvU32), ] - NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS -class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('PdeCopyParams', NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS), - ] - +class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS._fields_ = [ + ('PdeCopyParams', NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS), +] NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X._fields_ = [ - ('flags', ctypes.c_uint32), - ('boostDuration', ctypes.c_uint32), - ('gfId', ctypes.c_uint32), - ('bOverrideInfinite', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('flags', NvU32), + ('boostDuration', NvU32), + ('gfId', NvU32), + ('bOverrideInfinite', NvBool), ] - NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X -class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X._fields_ = [ - ('bIsCudaClient', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gfId', ctypes.c_uint32), + ('bIsCudaClient', NvBool), + ('gfId', NvU32), ] - NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X -class struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO._fields_ = [ - ('skylineVgpcSize', ctypes.c_ubyte * 12), - ('singletonVgpcMask', ctypes.c_uint32), - ('maxInstances', ctypes.c_uint32), - ('computeSizeFlag', ctypes.c_uint32), - ('numNonSingletonVgpcs', ctypes.c_uint32), + ('skylineVgpcSize', (NvU8 * 12)), + ('singletonVgpcMask', NvU32), + ('maxInstances', NvU32), + ('computeSizeFlag', NvU32), + ('numNonSingletonVgpcs', NvU32), ] - NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO = struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO -class struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS._fields_ = [ - ('skylineTable', struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO * 8), - ('validEntries', ctypes.c_uint32), + ('skylineTable', (NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO * 8)), + ('validEntries', NvU32), ] - NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS._fields_ = [ - ('bZbcSurfacesExist', ctypes.c_ubyte), + ('bZbcSurfacesExist', NvBool), ] - NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS -class struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO._fields_ = [ - ('enginesMask', ctypes.c_uint64 * 4), - ('partitionFlags', ctypes.c_uint32), - ('gpcMask', ctypes.c_uint32), - ('virtualGpcCount', ctypes.c_uint32), - ('veidOffset', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('enginesMask', (NvU64 * 4)), + ('partitionFlags', NvU32), + ('gpcMask', NvU32), + ('virtualGpcCount', NvU32), + ('veidOffset', NvU32), + ('veidCount', NvU32), ] - NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO = struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO -class struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS._fields_ = [ - ('swizzId', ctypes.c_uint32), - ('uuid', ctypes.c_ubyte * 16), - ('PADDING_0', ctypes.c_ubyte * 4), - ('info', NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO), + ('swizzId', NvU32), + ('uuid', (NvU8 * 16)), + ('info', NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO), ] - NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), + ('flags', NvU32), ] - NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS._fields_ = [ - ('bPcieGen4Capable', ctypes.c_ubyte), - ('bIsC2CLinkUp', ctypes.c_ubyte), - ('bIsDeviceMultiFunction', ctypes.c_ubyte), - ('bGcxPmuCfgSpaceRestore', ctypes.c_ubyte), + ('bPcieGen4Capable', NvBool), + ('bIsC2CLinkUp', NvBool), + ('bIsDeviceMultiFunction', NvBool), + ('bGcxPmuCfgSpaceRestore', NvBool), ] - NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS._fields_ = [ - ('programPeerMask', ctypes.c_uint32), - ('invalidatePeerMask', ctypes.c_uint32), - ('programPciePeerMask', ctypes.c_uint32), + ('programPeerMask', NvU32), + ('invalidatePeerMask', NvU32), + ('programPciePeerMask', NvU32), ] - NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('hshubIds', ctypes.c_ubyte * 32), + ('linkMask', NvU32), + ('hshubIds', (NvU8 * 32)), ] - NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS._fields_ = [ - ('numHshubs', ctypes.c_uint32), + ('numHshubs', NvU32), ] - NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS._fields_ = [ - ('hshubId', ctypes.c_ubyte), + ('hshubId', NvU8), ] - NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS._fields_ = [ - ('egmPeerId', ctypes.c_uint32), + ('egmPeerId', NvU32), ] - NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS._fields_ = [ - ('bGet', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('addr', ctypes.c_uint64), + ('bGet', NvBool), + ('addr', NvU64), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS._fields_ = [ - ('bCyaMaskL1', ctypes.c_ubyte), - ('bEnableAspmDtL1', ctypes.c_ubyte), + ('bCyaMaskL1', NvBool), + ('bEnableAspmDtL1', NvBool), ] - NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS -class struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS._fields_ = [ - ('maxActiveVGpuVMCount', ctypes.c_ubyte), + ('maxActiveVGpuVMCount', NvU8), ] - NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS._fields_ = [ - ('bRawMode', ctypes.c_ubyte), + ('bRawMode', NvBool), ] - NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS._fields_ = [ - ('ccuSampleSize', ctypes.c_uint32), + ('ccuSampleSize', NvU32), ] - NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO._fields_ = [ - ('phyAddr', ctypes.c_uint64), - ('shrBufSize', ctypes.c_uint32), - ('cntBlkSize', ctypes.c_uint32), + ('phyAddr', NvU64), + ('shrBufSize', NvU32), + ('cntBlkSize', NvU32), ] - NV2080_CTRL_INTERNAL_CCU_MAP_INFO = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO -class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('mapInfo', struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO * 9), - ] - +class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS._fields_ = [ + ('mapInfo', (NV2080_CTRL_INTERNAL_CCU_MAP_INFO * 9)), +] NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS._fields_ = [ - ('bDevShrBuf', ctypes.c_ubyte), - ('bMigShrBuf', ctypes.c_ubyte), + ('bDevShrBuf', NvBool), + ('bMigShrBuf', NvBool), ] - NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('gpuInstance', ctypes.c_uint32), - ('p2pCaps', ctypes.c_uint32), - ('p2pOptimalReadCEs', ctypes.c_uint32), - ('p2pOptimalWriteCEs', ctypes.c_uint32), - ('p2pCapsStatus', ctypes.c_ubyte * 9), - ('PADDING_0', ctypes.c_ubyte * 3), - ('busPeerId', ctypes.c_uint32), - ('busEgmPeerId', ctypes.c_uint32), + ('gpuId', NvU32), + ('gpuInstance', NvU32), + ('p2pCaps', NvU32), + ('p2pOptimalReadCEs', NvU32), + ('p2pOptimalWriteCEs', NvU32), + ('p2pCapsStatus', (NvU8 * 9)), + ('busPeerId', NvU32), + ('busEgmPeerId', NvU32), ] - NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO -class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS._fields_ = [ - ('peerGpuCount', ctypes.c_uint32), - ('peerGpuInfos', struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO * 32), + ('peerGpuCount', NvU32), + ('peerGpuInfos', (NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO * 32)), ] - NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS._fields_ = [ - ('peerGpuIdCount', ctypes.c_uint32), - ('peerGpuIds', ctypes.c_uint32 * 32), + ('peerGpuIdCount', NvU32), + ('peerGpuIds', (NvU32 * 32)), ] - NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS._fields_ = [ - ('bCommonPciSwitchFound', ctypes.c_ubyte), - ('p2pReadCapsStatus', ctypes.c_ubyte), - ('p2pWriteCapsStatus', ctypes.c_ubyte), + ('bCommonPciSwitchFound', NvBool), + ('p2pReadCapsStatus', NvU8), + ('p2pWriteCapsStatus', NvU8), ] - NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS._fields_ = [ - ('enableRo', ctypes.c_ubyte), + ('enableRo', NvBool), ] - NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS._fields_ = [ - ('bSave', ctypes.c_ubyte), - ('bUseVbios', ctypes.c_ubyte), - ('bReturnEarly', ctypes.c_ubyte), + ('bSave', NvBool), + ('bUseVbios', NvBool), + ('bReturnEarly', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS._fields_ = [ - ('bSave', ctypes.c_ubyte), - ('bUseVbios', ctypes.c_ubyte), - ('bVbiosCallSuccessful', ctypes.c_ubyte), + ('bSave', NvBool), + ('bUseVbios', NvBool), + ('bVbiosCallSuccessful', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS -class struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE(Struct): pass struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE._fields_ = [ - ('computeSize', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('gfxGpcCount', ctypes.c_uint32), - ('gpcCount', ctypes.c_uint32), - ('veidCount', ctypes.c_uint32), - ('smCount', ctypes.c_uint32), - ('physicalSlots', ctypes.c_uint32), + ('computeSize', NvU8), + ('gfxGpcCount', NvU32), + ('gpcCount', NvU32), + ('veidCount', NvU32), + ('smCount', NvU32), + ('physicalSlots', NvU32), ] - NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE = struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE -class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS._fields_ = [ - ('profileCount', ctypes.c_uint32), - ('profiles', struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE * 8), + ('profileCount', NvU32), + ('profiles', (NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE * 8)), ] - NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS -class struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS._fields_ = [ - ('bStreamState', ctypes.c_ubyte), + ('bStreamState', NvBool), ] - NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS._fields_ = [ - ('bExtDevFound', ctypes.c_ubyte), + ('bExtDevFound', NvBool), ] - NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS(Structure): - pass - -class struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS(Structure): - pass - -struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS(Struct): pass +class struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS(Struct): pass +NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS = struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS._fields_ = [ - ('gpuId', ctypes.c_uint32), - ('output', ctypes.c_uint32), - ('protocol', ctypes.c_uint32), - ('structure', ctypes.c_uint32), - ('adjust', ctypes.c_uint32), - ('hDeltaStep', ctypes.c_uint32), - ('hDeltaMax', ctypes.c_uint32), - ('vDeltaStep', ctypes.c_uint32), - ('vDeltaMax', ctypes.c_uint32), - ('hSyncEnd', ctypes.c_uint32), - ('hBlankEnd', ctypes.c_uint32), - ('hBlankStart', ctypes.c_uint32), - ('hTotal', ctypes.c_uint32), - ('vSyncEnd', ctypes.c_uint32), - ('vBlankEnd', ctypes.c_uint32), - ('vBlankStart', ctypes.c_uint32), - ('vInterlacedBlankEnd', ctypes.c_uint32), - ('vInterlacedBlankStart', ctypes.c_uint32), - ('vTotal', ctypes.c_uint32), - ('refreshX10K', ctypes.c_uint32), - ('pixelClockHz', ctypes.c_uint64), - ('bOptimized', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('gpuId', NvU32), + ('output', NvU32), + ('protocol', NvU32), + ('structure', NvU32), + ('adjust', NvU32), + ('hDeltaStep', NvU32), + ('hDeltaMax', NvU32), + ('vDeltaStep', NvU32), + ('vDeltaMax', NvU32), + ('hSyncEnd', NvU32), + ('hBlankEnd', NvU32), + ('hBlankStart', NvU32), + ('hTotal', NvU32), + ('vSyncEnd', NvU32), + ('vBlankEnd', NvU32), + ('vBlankStart', NvU32), + ('vInterlacedBlankEnd', NvU32), + ('vInterlacedBlankStart', NvU32), + ('vTotal', NvU32), + ('refreshX10K', NvU32), + ('pixelClockHz', NvU64), + ('bOptimized', NvBool), ] - -struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS._fields_ = [ - ('timingParameters', struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS), + ('timingParameters', NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS), ] - NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS._fields_ = [ - ('displayIds', ctypes.c_uint32 * 4), + ('displayIds', (NvU32 * 4)), ] - NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS._fields_ = [ - ('slave', ctypes.c_uint32 * 4), - ('localSlave', ctypes.c_uint32 * 4), - ('master', ctypes.c_uint32 * 4), - ('regStatus', ctypes.c_uint32), + ('slave', (NvU32 * 4)), + ('localSlave', (NvU32 * 4)), + ('master', (NvU32 * 4)), + ('regStatus', NvU32), ] - NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS._fields_ = [ - ('headIdx', ctypes.c_uint32), - ('vActiveLines', ctypes.c_uint32), + ('headIdx', NvU32), + ('vActiveLines', NvU32), ] - NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS._fields_ = [ - ('displays', ctypes.c_uint32), - ('displayId', ctypes.c_uint32), + ('displays', NvU32), + ('displayId', NvU32), ] - NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS._fields_ = [ - ('bEnableMaster', ctypes.c_ubyte), - ('bRasterSyncGpioSaved', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('bRasterSyncGpioDirection', ctypes.c_uint32), + ('bEnableMaster', NvBool), + ('bRasterSyncGpioSaved', NvBool), + ('bRasterSyncGpioDirection', NvU32), ] - NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS -class struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS._fields_ = [ - ('hClient', ctypes.c_uint32), - ('hSysMem', ctypes.c_uint32), - ('bEnteringGcoffState', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('sysmemAddrOfSuspendResumeData', ctypes.c_uint64), + ('hClient', NvHandle), + ('hSysMem', NvHandle), + ('bEnteringGcoffState', NvBool), + ('sysmemAddrOfSuspendResumeData', NvU64), ] - NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS = struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS._fields_ = [ - ('bDisableActiveChannels', ctypes.c_ubyte), + ('bDisableActiveChannels', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS._fields_ = [ - ('hostReservedFb', ctypes.c_uint64), - ('vgpuTypeId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('hostReservedFb', NvU64), + ('vgpuTypeId', NvU32), ] - NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS -class struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS._fields_ = [ - ('status', ctypes.c_uint32), - ('backLightDataSize', ctypes.c_uint16), - ('backLightData', ctypes.c_ubyte * 4096), - ('PADDING_0', ctypes.c_ubyte * 2), + ('status', NvU32), + ('backLightDataSize', NvU16), + ('backLightData', (NvU8 * 4096)), ] - NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS = struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS._fields_ = [ - ('numActiveLinksPerIoctrl', ctypes.c_uint32), + ('numActiveLinksPerIoctrl', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS._fields_ = [ - ('numLinksPerIoctrl', ctypes.c_uint32), + ('numLinksPerIoctrl', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS -class struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS._fields_ = [ - ('bIsSysCtrlSupported', ctypes.c_ubyte), - ('bIsPlatformLegacy', ctypes.c_ubyte), + ('bIsSysCtrlSupported', NvBool), + ('bIsPlatformLegacy', NvBool), ] - NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS = struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI(Struct): pass struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI._fields_ = [ - ('sensorId', ctypes.c_uint32), - ('limit', ctypes.c_uint32), + ('sensorId', NvU32), + ('limit', NvU32), ] - NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('smbpbi', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI), - ] - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA(Struct): pass +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data(ctypes.Union): pass +struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data._fields_ = [ + ('smbpbi', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI), +] struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('data', union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data), + ('type', NvU8), + ('data', struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data), ] - NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA -class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS._fields_ = [ - ('flags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('syncData', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA), + ('flags', NvU8), + ('syncData', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA), ] - NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS._fields_ = [ - ('flag', ctypes.c_ubyte), - ('bStatus', ctypes.c_ubyte), + ('flag', NvU8), + ('bStatus', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), + ('bEnable', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('clientLimit', ctypes.c_uint32), + ('bEnable', NvBool), + ('clientLimit', NvU32), ] - NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS._fields_ = [ - ('targetTemp', ctypes.c_int32), + ('targetTemp', NvS32), ] - NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), + ('bEnable', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS._fields_ = [ - ('ctgpOffsetmW', ctypes.c_uint32), + ('ctgpOffsetmW', NvU32), ] - NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS._fields_ = [ - ('bVpsPs20Supported', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('vPstateIdxHighest', ctypes.c_uint32), + ('bVpsPs20Supported', NvBool), + ('vPstateIdxHighest', NvU32), ] - NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS._fields_ = [ - ('pStateIdx', ctypes.c_uint32), - ('vPstateIdxMapping', ctypes.c_uint32), + ('pStateIdx', NvU32), + ('vPstateIdxMapping', NvU32), ] - NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS._fields_ = [ - ('vPstateIdx', ctypes.c_uint32), + ('vPstateIdx', NvU32), ] - NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS._fields_ = [ - ('bIsGC6Satisfied', ctypes.c_ubyte), - ('bIsGCOFFSatisfied', ctypes.c_ubyte), + ('bIsGC6Satisfied', NvBool), + ('bIsGCOFFSatisfied', NvBool), ] - NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS = struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [ - ('maxSec2SecureChannels', ctypes.c_uint32), - ('maxCeSecureChannels', ctypes.c_uint32), + ('maxSec2SecureChannels', NvU32), + ('maxCeSecureChannels', NvU32), ] - NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS -class struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS._fields_ = [ - ('bDisable', ctypes.c_ubyte), + ('bDisable', NvBool), ] - NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS._fields_ = [ - ('pinSetIn', ctypes.c_uint32), - ('pinSetOut', ctypes.c_uint32), - ('bMasterScanLock', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('masterScanLockPin', ctypes.c_uint32), - ('bSlaveScanLock', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('slaveScanLockPin', ctypes.c_uint32), + ('pinSetIn', NvU32), + ('pinSetOut', NvU32), + ('bMasterScanLock', NvBool), + ('masterScanLockPin', NvU32), + ('bSlaveScanLock', NvBool), + ('slaveScanLockPin', NvU32), ] - NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS = struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS -class struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS._fields_ = [ - ('pinSet', ctypes.c_uint32), - ('gpioFunction', ctypes.c_uint32), - ('gpioPin', ctypes.c_uint32), - ('gpioDirection', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('pinSet', NvU32), + ('gpioFunction', NvU32), + ('gpioPin', NvU32), + ('gpioDirection', NvBool), ] - NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS = struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS -class struct_NV2080_CTRL_INTERNAL_EDID_DATA(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_EDID_DATA._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_EDID_DATA(Struct): pass struct_NV2080_CTRL_INTERNAL_EDID_DATA._fields_ = [ - ('status', ctypes.c_uint32), - ('acpiId', ctypes.c_uint32), - ('bufferSize', ctypes.c_uint32), - ('edidBuffer', ctypes.c_ubyte * 512), + ('status', NvU32), + ('acpiId', NvU32), + ('bufferSize', NvU32), + ('edidBuffer', (NvU8 * 512)), ] - NV2080_CTRL_INTERNAL_EDID_DATA = struct_NV2080_CTRL_INTERNAL_EDID_DATA -class struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS._fields_ = [ - ('tableLen', ctypes.c_uint32), - ('edidTable', struct_NV2080_CTRL_INTERNAL_EDID_DATA * 16), + ('tableLen', NvU32), + ('edidTable', (NV2080_CTRL_INTERNAL_EDID_DATA * 16)), ] - NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('numProbes', ctypes.c_uint64), + ('numProbes', NvU64), ] - NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('bwMode', ctypes.c_ubyte), - ('bLocalEgmEnabled', ctypes.c_ubyte), + ('bwMode', NvU8), + ('bLocalEgmEnabled', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [ - ('bwMode', ctypes.c_ubyte), + ('bwMode', NvU8), ] - NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS._fields_ = [ - ('bIsBar1Trusted', ctypes.c_ubyte), - ('bIsPcieTrusted', ctypes.c_ubyte), + ('bIsBar1Trusted', NvBool), + ('bIsPcieTrusted', NvBool), ] - NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK(Struct): pass struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK._fields_ = [ - ('ivMask', ctypes.c_uint32 * 3), + ('ivMask', (NvU32 * 3)), ] - NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('ivMaskSet', struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 3), + ('engineId', NvU32), + ('ivMaskSet', (NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 3)), ] - NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS._fields_ = [ - ('engineId', ctypes.c_uint32), - ('ivMaskSet', struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 6), + ('engineId', NvU32), + ('ivMaskSet', (NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 6)), ] - NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS._fields_ = [ - ('globalH2DKey', ctypes.c_uint32), - ('updatedEncryptIVMask', ctypes.c_uint32 * 3), - ('updatedDecryptIVMask', ctypes.c_uint32 * 3), + ('globalH2DKey', NvU32), + ('updatedEncryptIVMask', (NvU32 * 3)), + ('updatedDecryptIVMask', (NvU32 * 3)), ] - NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS -class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [ - ('exceptionType', ctypes.c_uint32), - ('globalH2DKey', ctypes.c_uint32), + ('exceptionType', NvU32), + ('globalH2DKey', NvU32), ] - NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS._fields_ = [ - ('bAcceptClientRequest', ctypes.c_ubyte), + ('bAcceptClientRequest', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS._fields_ = [ - ('attackerAdvantage', ctypes.c_uint64), + ('attackerAdvantage', NvU64), ] - NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS -class struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS._fields_ = [ - ('logicalUprocId', ctypes.c_ubyte), + ('logicalUprocId', NvU8), ] - NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS +enum_NV2080_CTRL_MEMMGR_MEMORY_OP = CEnum(ctypes.c_uint32) +NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = enum_NV2080_CTRL_MEMMGR_MEMORY_OP.define('NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', 0) +NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = enum_NV2080_CTRL_MEMMGR_MEMORY_OP.define('NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', 1) -# values for enumeration 'NV2080_CTRL_MEMMGR_MEMORY_OP' -NV2080_CTRL_MEMMGR_MEMORY_OP__enumvalues = { - 0: 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', - 1: 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', -} -NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0 -NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1 -NV2080_CTRL_MEMMGR_MEMORY_OP = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO._pack_ = 1 # source:False +NV2080_CTRL_MEMMGR_MEMORY_OP = enum_NV2080_CTRL_MEMMGR_MEMORY_OP +class struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO._fields_ = [ - ('baseAddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('cpuCacheAttrib', ctypes.c_uint32), + ('baseAddr', NvU64), + ('size', NvU64), + ('offset', NvU64), + ('aperture', NvU32), + ('cpuCacheAttrib', NvU32), ] - NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO = struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO -class struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS._fields_ = [ - ('src', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO), - ('authTag', ctypes.c_ubyte * 16), - ('dst', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO), - ('transferSize', ctypes.c_uint64), - ('value', ctypes.c_uint32), - ('memop', NV2080_CTRL_MEMMGR_MEMORY_OP), + ('src', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO), + ('authTag', (NvU8 * 16)), + ('dst', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO), + ('transferSize', NvU64), + ('value', NvU32), + ('memop', NV2080_CTRL_MEMMGR_MEMORY_OP), ] - NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS._fields_ = [ - ('addrSysPhys', ctypes.c_uint64), - ('addrWidth', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('maskWidth', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('addrSysPhys', NvU64), + ('addrWidth', NvU32), + ('mask', NvU32), + ('maskWidth', NvU32), ] - NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('addrSysPhys', ctypes.c_uint64), - ('addrWidth', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('maskWidth', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('peerId', NvU32), + ('addrSysPhys', NvU64), + ('addrWidth', NvU32), + ('mask', NvU32), + ('maskWidth', NvU32), ] - NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS._fields_ = [ - ('limitMin', ctypes.c_uint32), - ('limitRated', ctypes.c_uint32), - ('limitMax', ctypes.c_uint32), - ('limitCurr', ctypes.c_uint32), - ('limitBattRated', ctypes.c_uint32), - ('limitBattMax', ctypes.c_uint32), + ('limitMin', NvU32), + ('limitRated', NvU32), + ('limitMax', NvU32), + ('limitCurr', NvU32), + ('limitBattRated', NvU32), + ('limitBattMax', NvU32), ] - NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS._fields_ = [ - ('physAddr', ctypes.c_uint64), + ('physAddr', NvU64), ] - NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS = struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS -class struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS._fields_ = [ - ('polledDataMask', ctypes.c_uint64), - ('pollFrequencyMs', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('polledDataMask', NvU64), + ('pollFrequencyMs', NvU32), ] - NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS = struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS._fields_ = [ - ('tracepointMask', ctypes.c_uint64), - ('bufferAddr', ctypes.c_uint64), - ('bufferSize', ctypes.c_uint32), - ('bufferWatermark', ctypes.c_uint32), - ('flag', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('tracepointMask', NvU64), + ('bufferAddr', NvU64), + ('bufferSize', NvU32), + ('bufferWatermark', NvU32), + ('flag', NvU8), ] - NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS -class struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS._fields_ = [ - ('bMaxwellSec2Enabled', ctypes.c_ubyte), - ('bNv95A1TsecEnabled', ctypes.c_ubyte), - ('bHopperSec2WorkLaunchAEnabled', ctypes.c_ubyte), + ('bMaxwellSec2Enabled', NvBool), + ('bNv95A1TsecEnabled', NvBool), + ('bHopperSec2WorkLaunchAEnabled', NvBool), ] - NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS._fields_ = [ - ('bInPMTransition', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('newPMLevel', ctypes.c_uint32), + ('bInPMTransition', NvBool), + ('newPMLevel', NvU32), ] - NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS._fields_ = [ - ('bSuccessful', ctypes.c_ubyte), + ('bSuccessful', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS._fields_ = [ - ('freeHeapSize', ctypes.c_uint64), + ('freeHeapSize', NvU64), ] - NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS._fields_ = [ - ('attribute', ctypes.c_uint32), - ('value', ctypes.c_uint32), + ('attribute', NvU32), + ('value', NvU32), ] - NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS._fields_ = [ - ('bApplyStereoPinAlwaysHiWar', ctypes.c_ubyte), + ('bApplyStereoPinAlwaysHiWar', NvBool), ] - NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS -class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS._fields_ = [ - ('maxHshubs', ctypes.c_uint32), + ('maxHshubs', NvU32), ] - NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS -class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS._fields_ = [ - ('rasterSyncDecodeMode', ctypes.c_uint32), + ('rasterSyncDecodeMode', NvU32), ] - NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS._fields_ = [ - ('spaValue', ctypes.c_uint64), + ('spaValue', NvU64), ] - NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS._fields_ = [ - ('peerMask', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('peerMask', NvU32), + ('bEnable', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), + ('mode', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS._fields_ = [ - ('seedData', ctypes.c_uint32 * 7), + ('seedData', (NvU32 * 7)), ] - NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS._fields_ = [ - ('remoteDeviceType', ctypes.c_uint32), - ('ipVerDlPl', ctypes.c_uint32), + ('remoteDeviceType', NvU32), + ('ipVerDlPl', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS._fields_ = [ - ('seedData', ctypes.c_uint32 * 7), + ('seedData', (NvU32 * 7)), ] - NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO._fields_ = [ - ('remoteSid', ctypes.c_uint64), - ('remoteDeviceType', ctypes.c_uint32), - ('remoteLinkId', ctypes.c_uint32), - ('localSid', ctypes.c_uint64), + ('remoteSid', NvU64), + ('remoteDeviceType', NvU32), + ('remoteLinkId', NvU32), + ('localSid', NvU64), ] - NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS._fields_ = [ - ('bInitnegotiateConfigGood', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO), + ('bInitnegotiateConfigGood', NvBool), + ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO), ] - NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS._fields_ = [ - ('bPollDone', ctypes.c_ubyte), + ('bPollDone', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams(Union): - pass - -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams._pack_ = 1 # source:False -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams._fields_ = [ - ('linkModeOffParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS), - ('linkModePreHsParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS), - ('linkModeInitPhase1Params', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS), - ('linkModePostInitNegotiateParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS), - ('linkModePostInitOptimizeParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 31), +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS(Struct): pass +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams(ctypes.Union): pass +struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams._fields_ = [ + ('linkModeOffParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS), + ('linkModePreHsParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS), + ('linkModeInitPhase1Params', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS), + ('linkModePostInitNegotiateParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS), + ('linkModePostInitOptimizeParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS), ] - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkMode', ctypes.c_uint32), - ('linkModeParams', union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams), + ('mode', NvU64), + ('bSync', NvBool), + ('linkMode', NvU32), + ('linkModeParams', struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint32), + ('mode', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('mode', NvU64), + ('bSync', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS._fields_ = [ - ('sublinkMode', ctypes.c_uint32), - ('sublinkSubMode', ctypes.c_uint32), + ('sublinkMode', NvU32), + ('sublinkSubMode', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('mode', NvU64), + ('bSync', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS._fields_ = [ - ('mode', ctypes.c_uint64), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), + ('mode', NvU64), + ('bSync', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS._fields_ = [ - ('laneRxdetStatusMask', ctypes.c_uint32), + ('laneRxdetStatusMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS._fields_ = [ - ('bSync', ctypes.c_ubyte), + ('bSync', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS._fields_ = [ - ('ipVerDlPl', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('token', ctypes.c_uint64), + ('ipVerDlPl', NvU32), + ('token', NvU64), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS._fields_ = [ - ('bUnlocked', ctypes.c_ubyte), + ('bUnlocked', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE(Structure): - pass - -class union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams(Union): - pass - -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams._pack_ = 1 # source:False -union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams._fields_ = [ - ('getDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS), - ('setDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS), - ('getTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS), - ('setTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS), - ('getTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS), - ('setTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS), - ('getRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS), - ('setRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS), - ('getRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS), - ('setRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS), - ('writeDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS), - ('readDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS), - ('getUphyLoad', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS), - ('PADDING_0', ctypes.c_ubyte * 47), +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE(Struct): pass +class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams(ctypes.Union): pass +struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams._fields_ = [ + ('getDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS), + ('setDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS), + ('getTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS), + ('setTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS), + ('getTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS), + ('setTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS), + ('getRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS), + ('setRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS), + ('getRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS), + ('setRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS), + ('writeDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS), + ('readDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS), + ('getUphyLoad', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS), ] - -struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE._pack_ = 1 # source:False struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('callbackParams', union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams), + ('type', NvU8), + ('callbackParams', struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams), ] - NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE -class struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callbackType', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE), + ('linkId', NvU32), + ('callbackType', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE), ] - NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO), + ('linkId', NvU32), + ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO), ] - NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS._fields_ = [ - ('bEnableAli', ctypes.c_ubyte), + ('bEnableAli', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS._fields_ = [ - ('updateType', ctypes.c_ubyte), - ('bSysMem', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('peerMask', ctypes.c_uint32), + ('updateType', NvBool), + ('bSysMem', NvBool), + ('peerMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS._fields_ = [ - ('peerId', ctypes.c_uint32), - ('peerLinkMask', ctypes.c_uint32), - ('bEgmPeer', ctypes.c_ubyte), - ('bNvswitchConn', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), + ('peerId', NvU32), + ('peerLinkMask', NvU32), + ('bEgmPeer', NvBool), + ('bNvswitchConn', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS._fields_ = [ - ('peerMask', ctypes.c_uint32), + ('peerMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS._fields_ = [ - ('xid', ctypes.c_uint32), - ('message', ctypes.c_ubyte * 81), - ('PADDING_0', ctypes.c_ubyte * 3), - ('len', ctypes.c_uint32), + ('xid', NvU32), + ('message', (NvU8 * 81)), + ('len', NvU32), ] - NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS = struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS._fields_ = [ - ('mapTypeMask', ctypes.c_uint32), - ('peerMask', ctypes.c_uint32), - ('bL2Entry', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('mapTypeMask', NvU32), + ('peerMask', NvU32), + ('bL2Entry', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS._fields_ = [ - ('bSave', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkMask', ctypes.c_uint32), + ('bSave', NvBool), + ('linkMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('bSysmem', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('peerLinkMask', ctypes.c_uint32), + ('flags', NvU32), + ('bSysmem', NvBool), + ('peerLinkMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS._fields_ = [ - ('bNvlinkSysmemEnabled', ctypes.c_ubyte), + ('bNvlinkSysmemEnabled', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS._fields_ = [ - ('gpuInst', ctypes.c_uint32), - ('peerLinkMask', ctypes.c_uint32), + ('gpuInst', NvU32), + ('peerLinkMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS._fields_ = [ - ('remoteDeviceType', ctypes.c_uint64), - ('remoteChipSid', ctypes.c_uint64), - ('linkId', ctypes.c_uint32), - ('laneRxdetStatusMask', ctypes.c_uint32), - ('remoteLinkNumber', ctypes.c_uint32), - ('remotePciDeviceId', ctypes.c_uint32), - ('remoteDomain', ctypes.c_uint32), - ('remoteBus', ctypes.c_ubyte), - ('remoteDevice', ctypes.c_ubyte), - ('remoteFunction', ctypes.c_ubyte), - ('bConnected', ctypes.c_ubyte), + ('remoteDeviceType', NvU64), + ('remoteChipSid', NvU64), + ('linkId', NvU32), + ('laneRxdetStatusMask', NvU32), + ('remoteLinkNumber', NvU32), + ('remotePciDeviceId', NvU32), + ('remoteDomain', NvU32), + ('remoteBus', NvU8), + ('remoteDevice', NvU8), + ('remoteFunction', NvU8), + ('bConnected', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('initializedLinks', ctypes.c_uint32), + ('linkMask', NvU32), + ('initializedLinks', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkMask', NvU32), + ('bSync', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS._fields_ = [ - ('postRxDetLinkMask', ctypes.c_uint64), - ('laneRxdetStatusMask', ctypes.c_uint32 * 64), + ('postRxDetLinkMask', NvU64), + ('laneRxdetStatusMask', (NvU32 * 64)), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bSync', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkMask', NvU32), + ('bSync', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('linkId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('ioctrlId', ctypes.c_uint32), - ('pllMasterLinkId', ctypes.c_ubyte), - ('pllSlaveLinkId', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('ipVerDlPl', ctypes.c_uint32), + ('bValid', NvBool), + ('linkId', NvU8), + ('ioctrlId', NvU32), + ('pllMasterLinkId', NvU8), + ('pllSlaveLinkId', NvU8), + ('ipVerDlPl', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS._fields_ = [ - ('ioctrlMask', ctypes.c_uint32), - ('ioctrlNumEntries', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('ioctrlSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('discoveredLinks', ctypes.c_uint64), - ('ipVerNvlink', ctypes.c_uint32), - ('linkInfo', struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES * 64), - ('PADDING_2', ctypes.c_ubyte * 4), + ('ioctrlMask', NvU32), + ('ioctrlNumEntries', NvU8), + ('ioctrlSize', NvU32), + ('discoveredLinks', NvU64), + ('ipVerNvlink', NvU32), + ('linkInfo', (NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES * 64)), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES._fields_ = [ - ('ipVerIoctrl', ctypes.c_uint32), - ('ipVerMinion', ctypes.c_uint32), + ('ipVerIoctrl', NvU32), + ('ipVerMinion', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS._fields_ = [ - ('ioctrlIdx', ctypes.c_uint32), - ('PublicId', ctypes.c_uint32), - ('localDiscoveredLinks', ctypes.c_uint32), - ('localGlobalLinkOffset', ctypes.c_uint32), - ('ioctrlDiscoverySize', ctypes.c_uint32), - ('numDevices', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('ipRevisions', NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES), + ('ioctrlIdx', NvU32), + ('PublicId', NvU32), + ('localDiscoveredLinks', NvU32), + ('localGlobalLinkOffset', NvU32), + ('ioctrlDiscoverySize', NvU32), + ('numDevices', NvU8), + ('ipRevisions', NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS._fields_ = [ - ('bPlatformLinerateDefined', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('platformLineRate', ctypes.c_uint32), - ('nvlinkLinkSpeed', ctypes.c_uint32), + ('bPlatformLinerateDefined', NvBool), + ('platformLineRate', NvU32), + ('nvlinkLinkSpeed', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bActiveOnly', ctypes.c_ubyte), - ('bIsLinkActive', ctypes.c_ubyte * 64), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkMask', NvU32), + ('bActiveOnly', NvBool), + ('bIsLinkActive', (NvBool * 64)), ] - NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), + ('linkMask', NvU32), + ('flags', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), + ('linkMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES._fields_ = [ - ('bLinkConnectedToSystem', ctypes.c_ubyte), - ('bLinkConnectedToPeer', ctypes.c_ubyte), - ('bLinkReset', ctypes.c_ubyte), - ('subLinkWidth', ctypes.c_ubyte), - ('linkState', ctypes.c_uint32), - ('txSublinkState', ctypes.c_uint32), - ('rxSublinkState', ctypes.c_uint32), - ('bLaneReversal', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('nvlinkLinkClockKHz', ctypes.c_uint32), - ('nvlinkLineRateMbps', ctypes.c_uint32), - ('nvlinkLinkClockMhz', ctypes.c_uint32), - ('nvlinkLinkDataRateKiBps', ctypes.c_uint32), - ('nvlinkRefClkType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('nvlinkReqLinkClockMhz', ctypes.c_uint32), - ('nvlinkMinL1Threshold', ctypes.c_uint32), - ('nvlinkMaxL1Threshold', ctypes.c_uint32), - ('nvlinkL1ThresholdUnits', ctypes.c_uint32), + ('bLinkConnectedToSystem', NvBool), + ('bLinkConnectedToPeer', NvBool), + ('bLinkReset', NvBool), + ('subLinkWidth', NvU8), + ('linkState', NvU32), + ('txSublinkState', NvU32), + ('rxSublinkState', NvU32), + ('bLaneReversal', NvBool), + ('nvlinkLinkClockKHz', NvU32), + ('nvlinkLineRateMbps', NvU32), + ('nvlinkLinkClockMhz', NvU32), + ('nvlinkLinkDataRateKiBps', NvU32), + ('nvlinkRefClkType', NvU8), + ('nvlinkReqLinkClockMhz', NvU32), + ('nvlinkMinL1Threshold', NvU32), + ('nvlinkMaxL1Threshold', NvU32), + ('nvlinkL1ThresholdUnits', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES -class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('nvlinkRefClkSpeedKHz', ctypes.c_uint32), - ('bSublinkStateInst', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkInfo', struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES * 64), + ('linkMask', NvU64), + ('nvlinkRefClkSpeedKHz', NvU32), + ('bSublinkStateInst', NvBool), + ('linkInfo', (NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES * 64)), ] - NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS._fields_ = [ - ('sysmemLinkMask', ctypes.c_uint32), + ('sysmemLinkMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS._fields_ = [ - ('bLegacyForcedConfig', ctypes.c_ubyte), - ('bOverrideComputePeerMode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('phase', ctypes.c_uint32), - ('linkConnection', ctypes.c_uint32 * 64), + ('bLegacyForcedConfig', NvBool), + ('bOverrideComputePeerMode', NvBool), + ('phase', NvU32), + ('linkConnection', (NvU32 * 64)), ] - NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS._fields_ = [ - ('bLaneShutdownOnUnload', ctypes.c_ubyte), + ('bLaneShutdownOnUnload', NvBool), ] - NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS._fields_ = [ - ('notUsed', ctypes.c_uint32), + ('notUsed', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS -class struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS._fields_ = [ - ('sysmemLinkMask', ctypes.c_uint32), + ('sysmemLinkMask', NvU32), ] - NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS -NV2080_CTRL_CMD_LPWR_DIFR_CTRL = (0x20802801) # macro -NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE = (0x00000001) # macro -NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE = (0x00000002) # macro -NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS = (0x00000003) # macro -NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_LPWR_DIFR_SUPPORTED = (0x00000001) # macro -NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED = (0x00000002) # macro -NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE = (0x20802802) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS = (0x00000001) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED = (0x00000002) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE = (0x00000003) # macro -NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR = (0x00000004) # macro -NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS._fields_ = [ - ('ctrlParamVal', ctypes.c_uint32), + ('ctrlParamVal', NvU32), ] - NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS = struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS -class struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS._fields_ = [ - ('responseVal', ctypes.c_uint32), + ('responseVal', NvU32), ] - NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS = struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS -NV2080_CTRL_CMD_MC_GET_ARCH_INFO = (0x20801701) # macro -NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X = (0xE0000023) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 = (0x00000160) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 = (0x00000170) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 = (0x00000180) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 = (0x00000190) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 = (0x000001A0) # macro -NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 = (0x000001B0) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D = (0x00000005) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 = (0x00000008) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 = (0x00000003) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B = (0x0000000B) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 = (0x00000003) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B = (0x0000000B) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 = (0x00000003) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 = (0x00000004) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 = (0x00000005) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 = (0x00000006) # macro -NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 = (0x00000007) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION = (0x00000000) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P = (0x00000001) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q = (0x00000002) # macro -NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R = (0x00000003) # macro -NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = (0x20801702) # macro -NV2080_CTRL_MC_ENGINE_ID_GRAPHICS = 0x00000001 # macro -NV2080_CTRL_MC_ENGINE_ID_ALL = 0xFFFFFFFF # macro -NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_MC_GET_MANUFACTURER = (0x20801703) # macro -NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP = (0x2080170c) # macro -NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS = (0x2080170d) # macro -NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES = 256 # macro -NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE = (0x2080170e) # macro -NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX = 32 # macro -NV2080_INTR_TYPE_NULL = (0x00000000) # macro -NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT = (0x00000001) # macro -NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR = (0x00000002) # macro -NV2080_INTR_TYPE_INFO_FAULT = (0x00000003) # macro -NV2080_INTR_TYPE_REPLAYABLE_FAULT = (0x00000004) # macro -NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR = (0x00000005) # macro -NV2080_INTR_TYPE_ACCESS_CNTR = (0x00000006) # macro -NV2080_INTR_TYPE_TMR = (0x00000007) # macro -NV2080_INTR_TYPE_CPU_DOORBELL = (0x00000008) # macro -NV2080_INTR_TYPE_GR0_FECS_LOG = (0x00000009) # macro -NV2080_INTR_TYPE_GR1_FECS_LOG = (0x0000000A) # macro -NV2080_INTR_TYPE_GR2_FECS_LOG = (0x0000000B) # macro -NV2080_INTR_TYPE_GR3_FECS_LOG = (0x0000000C) # macro -NV2080_INTR_TYPE_GR4_FECS_LOG = (0x0000000D) # macro -NV2080_INTR_TYPE_GR5_FECS_LOG = (0x0000000E) # macro -NV2080_INTR_TYPE_GR6_FECS_LOG = (0x0000000F) # macro -NV2080_INTR_TYPE_GR7_FECS_LOG = (0x00000010) # macro -NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID = (0xE) # macro -class struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS._fields_ = [ - ('architecture', ctypes.c_uint32), - ('implementation', ctypes.c_uint32), - ('revision', ctypes.c_uint32), - ('subRevision', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('architecture', NvU32), + ('implementation', NvU32), + ('revision', NvU32), + ('subRevision', NvU8), ] - NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS = struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS -class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS(Struct): pass struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS._fields_ = [ - ('engines', ctypes.c_uint32), + ('engines', NvU32), ] - NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS = struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS -class struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS(Struct): pass struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS._fields_ = [ - ('manufacturer', ctypes.c_uint32), + ('manufacturer', NvU32), ] - NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS = struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS -class struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS(Struct): pass struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS._fields_ = [ - ('bOwnedByRm', ctypes.c_ubyte), + ('bOwnedByRm', NvBool), ] - NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS = struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS -class struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY(Structure): - pass - -struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY(Struct): pass struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY._fields_ = [ - ('nv2080EngineType', ctypes.c_uint32), - ('notificationIntrVector', ctypes.c_uint32), + ('nv2080EngineType', NvU32), + ('notificationIntrVector', NvU32), ] - NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY = struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY -class struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(Struct): pass struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS._fields_ = [ - ('numEntries', ctypes.c_uint32), - ('entries', struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY * 256), + ('numEntries', NvU32), + ('entries', (NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY * 256)), ] - NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS = struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS -class struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY(Structure): - pass - -struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY(Struct): pass struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY._fields_ = [ - ('nv2080IntrType', ctypes.c_uint32), - ('pmcIntrMask', ctypes.c_uint32), - ('intrVectorStall', ctypes.c_uint32), - ('intrVectorNonStall', ctypes.c_uint32), + ('nv2080IntrType', NvU32), + ('pmcIntrMask', NvU32), + ('intrVectorStall', NvU32), + ('intrVectorNonStall', NvU32), ] - NV2080_CTRL_MC_STATIC_INTR_ENTRY = struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY -class struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(Struct): pass struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS._fields_ = [ - ('numEntries', ctypes.c_uint32), - ('entries', struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY * 32), + ('numEntries', NvU32), + ('entries', (NV2080_CTRL_MC_STATIC_INTR_ENTRY * 32)), ] - NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS = struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS -NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x20802401) # macro -NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_NVD_GET_DUMP = (0x20802402) # macro -NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL = (0x20802409) # macro -NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER = 1024 # macro -NV2080_NOCAT_JOURNAL_MAX_STR_LEN = 65 # macro -NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS = 10 # macro -NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS = 32 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN = 0 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK = 1 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE = 2 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_TDR = 3 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_RC = 4 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT = 5 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_ANY = 6 # macro -NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT = (0x7) # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX = 0 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX = 1 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX = 2 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX = 3 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX = 4 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX = 5 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX = 6 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX = 7 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX = 8 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX = 9 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX = 10 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX = 11 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX = 12 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX = 13 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX = 14 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX = 15 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX = 16 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX = 17 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX = 18 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX = 19 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX = 20 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX = 21 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX = 22 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX = 23 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX = 24 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX = 25 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX = 26 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX = 27 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX = 28 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX = 29 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX = 30 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX = 31 # macro -NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT = (0x20) # macro -# NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY = 0 : 0 # macro -NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES = 1 # macro -NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO = 0 # macro -# NV2080_CTRL_NOCAT_GET_RESET_COUNTERS = 1 : 1 # macro -NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES = 1 # macro -NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO = 0 # macro -NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA = (0x2080240b) # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY = 0 # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON = 1 # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG = 2 # macro -NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG = 3 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_NONE = 0 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY = 1 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP = 2 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET = 3 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET = 4 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL = 5 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET = 6 # macro -NV2080_CTRL_NOCAT_TDR_TYPE_TEST = 7 # macro -# NV2080_CTRL_NOCAT_TAG_CLEAR = 0 : 0 # macro -NV2080_CTRL_NOCAT_TAG_CLEAR_YES = 1 # macro -NV2080_CTRL_NOCAT_TAG_CLEAR_NO = 0 # macro -NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD = (0x2080240c) # macro -# NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR = 0 : 0 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES = 1 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO = 0 # macro -# NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER = 1 : 1 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES = 1 # macro -NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO = 0 # macro -NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID = (0xC) # macro -class struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Struct): pass struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [ - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), + ('component', NvU32), + ('size', NvU32), ] - NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS -class struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS(Struct): pass struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [ - ('pBuffer', ctypes.POINTER(None)), - ('component', ctypes.c_uint32), - ('size', ctypes.c_uint32), + ('pBuffer', NvP64), + ('component', NvU32), + ('size', NvU32), ] - NV2080_CTRL_NVD_GET_DUMP_PARAMS = struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS -class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS._pack_ = 1 # source:False +class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS(Struct): pass struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS._fields_ = [ - ('userMinOffset', ctypes.c_int32), - ('userMaxOffset', ctypes.c_int32), - ('factoryMinOffset', ctypes.c_uint32), - ('factoryMaxOffset', ctypes.c_uint32), - ('lastActiveClock', ctypes.c_uint32), - ('lastActiveVolt', ctypes.c_uint32), - ('lastActivePoint', ctypes.c_uint32), - ('kappa', ctypes.c_uint32), + ('userMinOffset', NvS32), + ('userMaxOffset', NvS32), + ('factoryMinOffset', NvU32), + ('factoryMaxOffset', NvU32), + ('lastActiveClock', NvU32), + ('lastActiveVolt', NvU32), + ('lastActivePoint', NvU32), + ('kappa', NvU32), ] - NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS -class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG._pack_ = 1 # source:False +class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG(Struct): pass struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG._fields_ = [ - ('pstateVer', ctypes.c_uint32), - ('gpcOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS), - ('mclkOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS), - ('bUserOverclocked', ctypes.c_ubyte), - ('bFactoryOverclocked', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), + ('pstateVer', NvU32), + ('gpcOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS), + ('mclkOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS), + ('bUserOverclocked', NvBool), + ('bFactoryOverclocked', NvBool), ] - NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG -class struct_NV2080_NOCAT_JOURNAL_GPU_STATE(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_GPU_STATE._pack_ = 1 # source:False +class struct_NV2080_NOCAT_JOURNAL_GPU_STATE(Struct): pass struct_NV2080_NOCAT_JOURNAL_GPU_STATE._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('strap', ctypes.c_uint32), - ('deviceId', ctypes.c_uint16), - ('vendorId', ctypes.c_uint16), - ('subsystemVendor', ctypes.c_uint16), - ('subsystemId', ctypes.c_uint16), - ('revision', ctypes.c_uint16), - ('type', ctypes.c_uint16), - ('vbiosVersion', ctypes.c_uint32), - ('bOptimus', ctypes.c_ubyte), - ('bMsHybrid', ctypes.c_ubyte), - ('bFullPower', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('vbiosOemVersion', ctypes.c_uint32), - ('memoryType', ctypes.c_uint16), - ('tag', ctypes.c_ubyte * 65), - ('vbiosProject', ctypes.c_ubyte * 65), - ('bInFullchipReset', ctypes.c_ubyte), - ('bInSecBusReset', ctypes.c_ubyte), - ('bInGc6Reset', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte), - ('overclockCfg', NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG), + ('bValid', NvBool), + ('strap', NvU32), + ('deviceId', NvU16), + ('vendorId', NvU16), + ('subsystemVendor', NvU16), + ('subsystemId', NvU16), + ('revision', NvU16), + ('type', NvU16), + ('vbiosVersion', NvU32), + ('bOptimus', NvBool), + ('bMsHybrid', NvBool), + ('bFullPower', NvBool), + ('vbiosOemVersion', NvU32), + ('memoryType', NvU16), + ('tag', (NvU8 * 65)), + ('vbiosProject', (NvU8 * 65)), + ('bInFullchipReset', NvBool), + ('bInSecBusReset', NvBool), + ('bInGc6Reset', NvBool), + ('overclockCfg', NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG), ] - NV2080_NOCAT_JOURNAL_GPU_STATE = struct_NV2080_NOCAT_JOURNAL_GPU_STATE -class struct_NV2080_NOCAT_JOURNAL_ENTRY(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_ENTRY._pack_ = 1 # source:False +class struct_NV2080_NOCAT_JOURNAL_ENTRY(Struct): pass struct_NV2080_NOCAT_JOURNAL_ENTRY._fields_ = [ - ('recType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bugcheck', ctypes.c_uint32), - ('tdrBucketId', ctypes.c_uint32), - ('source', ctypes.c_ubyte * 65), - ('PADDING_1', ctypes.c_ubyte * 3), - ('subsystem', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), - ('errorCode', ctypes.c_uint64), - ('diagBufferLen', ctypes.c_uint32), - ('diagBuffer', ctypes.c_ubyte * 1024), - ('faultingEngine', ctypes.c_ubyte * 65), - ('PADDING_3', ctypes.c_ubyte * 3), - ('mmuFaultType', ctypes.c_uint32), - ('mmuErrorSrc', ctypes.c_uint32), - ('tdrReason', ctypes.c_ubyte * 65), - ('PADDING_4', ctypes.c_ubyte * 7), + ('recType', NvU8), + ('bugcheck', NvU32), + ('tdrBucketId', NvU32), + ('source', (NvU8 * 65)), + ('subsystem', NvU32), + ('errorCode', NvU64), + ('diagBufferLen', NvU32), + ('diagBuffer', (NvU8 * 1024)), + ('faultingEngine', (NvU8 * 65)), + ('mmuFaultType', NvU32), + ('mmuErrorSrc', NvU32), + ('tdrReason', (NvU8 * 65)), ] - NV2080_NOCAT_JOURNAL_ENTRY = struct_NV2080_NOCAT_JOURNAL_ENTRY -class struct_NV2080_NOCAT_JOURNAL_RECORD(Structure): - pass - -struct_NV2080_NOCAT_JOURNAL_RECORD._pack_ = 1 # source:False +class struct_NV2080_NOCAT_JOURNAL_RECORD(Struct): pass struct_NV2080_NOCAT_JOURNAL_RECORD._fields_ = [ - ('GPUTag', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('loadAddress', ctypes.c_uint64), - ('timeStamp', ctypes.c_uint64), - ('stateMask', ctypes.c_uint64), - ('nocatGpuState', NV2080_NOCAT_JOURNAL_GPU_STATE), - ('nocatJournalEntry', NV2080_NOCAT_JOURNAL_ENTRY), + ('GPUTag', NvU32), + ('loadAddress', NvU64), + ('timeStamp', NvU64), + ('stateMask', NvU64), + ('nocatGpuState', NV2080_NOCAT_JOURNAL_GPU_STATE), + ('nocatJournalEntry', NV2080_NOCAT_JOURNAL_ENTRY), ] - NV2080_NOCAT_JOURNAL_RECORD = struct_NV2080_NOCAT_JOURNAL_RECORD -class struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS(Struct): pass struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('nocatRecordCount', ctypes.c_uint32), - ('nocatOutstandingRecordCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('journalRecords', struct_NV2080_NOCAT_JOURNAL_RECORD * 10), - ('activityCounters', ctypes.c_uint32 * 32), - ('reserved', ctypes.c_ubyte * 65), - ('PADDING_1', ctypes.c_ubyte * 7), + ('flags', NvU32), + ('nocatRecordCount', NvU32), + ('nocatOutstandingRecordCount', NvU32), + ('journalRecords', (NV2080_NOCAT_JOURNAL_RECORD * 10)), + ('activityCounters', (NvU32 * 32)), + ('reserved', (NvU8 * 65)), ] - NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS = struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS -class struct_NV2080CtrlNocatJournalDataTdrReason(Structure): - pass - -struct_NV2080CtrlNocatJournalDataTdrReason._pack_ = 1 # source:False +class struct_NV2080CtrlNocatJournalDataTdrReason(Struct): pass struct_NV2080CtrlNocatJournalDataTdrReason._fields_ = [ - ('flags', ctypes.c_uint32), - ('source', ctypes.c_ubyte * 65), - ('PADDING_0', ctypes.c_ubyte * 3), - ('subsystem', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('errorCode', ctypes.c_uint64), - ('reasonCode', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), + ('flags', NvU32), + ('source', (NvU8 * 65)), + ('subsystem', NvU32), + ('errorCode', NvU64), + ('reasonCode', NvU32), ] - NV2080CtrlNocatJournalDataTdrReason = struct_NV2080CtrlNocatJournalDataTdrReason -class struct_NV2080CtrlNocatJournalSetTag(Structure): - pass - -struct_NV2080CtrlNocatJournalSetTag._pack_ = 1 # source:False +class struct_NV2080CtrlNocatJournalSetTag(Struct): pass struct_NV2080CtrlNocatJournalSetTag._fields_ = [ - ('flags', ctypes.c_uint32), - ('tag', ctypes.c_ubyte * 65), - ('PADDING_0', ctypes.c_ubyte * 3), + ('flags', NvU32), + ('tag', (NvU8 * 65)), ] - NV2080CtrlNocatJournalSetTag = struct_NV2080CtrlNocatJournalSetTag -class struct_NV2080CtrlNocatJournalRclog(Structure): - pass - -struct_NV2080CtrlNocatJournalRclog._pack_ = 1 # source:False +class struct_NV2080CtrlNocatJournalRclog(Struct): pass struct_NV2080CtrlNocatJournalRclog._fields_ = [ - ('flags', ctypes.c_uint32), - ('rclogSize', ctypes.c_uint32), - ('rmGpuId', ctypes.c_uint32), - ('APIType', ctypes.c_uint32), - ('contextType', ctypes.c_uint32), - ('exceptType', ctypes.c_uint32), - ('processImageName', ctypes.c_ubyte * 65), - ('PADDING_0', ctypes.c_ubyte * 3), + ('flags', NvU32), + ('rclogSize', NvU32), + ('rmGpuId', NvU32), + ('APIType', NvU32), + ('contextType', NvU32), + ('exceptType', NvU32), + ('processImageName', (NvU8 * 65)), ] - NV2080CtrlNocatJournalRclog = struct_NV2080CtrlNocatJournalRclog -class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS(Structure): - pass - -class union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData(Union): - pass - -union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData._pack_ = 1 # source:False -union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData._fields_ = [ - ('tdrReason', NV2080CtrlNocatJournalDataTdrReason), - ('tagData', NV2080CtrlNocatJournalSetTag), - ('rclog', NV2080CtrlNocatJournalRclog), - ('PADDING_0', ctypes.c_ubyte * 4), +class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS(Struct): pass +class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData(ctypes.Union): pass +struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData._fields_ = [ + ('tdrReason', NV2080CtrlNocatJournalDataTdrReason), + ('tagData', NV2080CtrlNocatJournalSetTag), + ('rclog', NV2080CtrlNocatJournalRclog), ] - -struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS._fields_ = [ - ('dataType', ctypes.c_uint32), - ('targetRecordType', ctypes.c_uint32), - ('nocatJournalData', union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData), + ('dataType', NvU32), + ('targetRecordType', NvU32), + ('nocatJournalData', struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData), ] - NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS = struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS -class struct_NV2080CtrlNocatJournalInsertRecord(Structure): - pass - -struct_NV2080CtrlNocatJournalInsertRecord._pack_ = 1 # source:False +class struct_NV2080CtrlNocatJournalInsertRecord(Struct): pass struct_NV2080CtrlNocatJournalInsertRecord._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timestamp', ctypes.c_uint64), - ('recType', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), - ('bugcheck', ctypes.c_uint32), - ('source', ctypes.c_char * 65), - ('PADDING_2', ctypes.c_ubyte * 3), - ('subsystem', ctypes.c_uint32), - ('errorCode', ctypes.c_uint64), - ('faultingEngine', ctypes.c_char * 65), - ('PADDING_3', ctypes.c_ubyte * 3), - ('tdrReason', ctypes.c_uint32), - ('diagBufferLen', ctypes.c_uint32), - ('diagBuffer', ctypes.c_ubyte * 1024), - ('PADDING_4', ctypes.c_ubyte * 4), + ('flags', NvU32), + ('timestamp', NvU64), + ('recType', NvU8), + ('bugcheck', NvU32), + ('source', (ctypes.c_char * 65)), + ('subsystem', NvU32), + ('errorCode', NvU64), + ('faultingEngine', (ctypes.c_char * 65)), + ('tdrReason', NvU32), + ('diagBufferLen', NvU32), + ('diagBuffer', (NvU8 * 1024)), ] - NV2080CtrlNocatJournalInsertRecord = struct_NV2080CtrlNocatJournalInsertRecord -class struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('nocatJournalRecord', NV2080CtrlNocatJournalInsertRecord), - ] - +class struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS(Struct): pass +struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS._fields_ = [ + ('nocatJournalRecord', NV2080CtrlNocatJournalInsertRecord), +] NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS = struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID = (0x1) # macro -# def NV2080_CTRL_NVLINK_GET_CAP(tbl, c): # macro -# return (((NvU8)tbl[(1?c)])&(0?c)) -# NV2080_CTRL_NVLINK_CAPS_SUPPORTED = 0 : 0x01 # macro -# NV2080_CTRL_NVLINK_CAPS_P2P_SUPPORTED = 0 : 0x02 # macro -# NV2080_CTRL_NVLINK_CAPS_SYSMEM_ACCESS = 0 : 0x04 # macro -# NV2080_CTRL_NVLINK_CAPS_P2P_ATOMICS = 0 : 0x08 # macro -# NV2080_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS = 0 : 0x10 # macro -# NV2080_CTRL_NVLINK_CAPS_PEX_TUNNELING = 0 : 0x20 # macro -# NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE = 0 : 0x40 # macro -# NV2080_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE = 0 : 0x80 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L0 = 1 : 0x01 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L1 = 1 : 0x02 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L2 = 1 : 0x04 # macro -# NV2080_CTRL_NVLINK_CAPS_POWER_STATE_L3 = 1 : 0x08 # macro -# NV2080_CTRL_NVLINK_CAPS_VALID = 1 : 0x10 # macro -# NV2080_CTRL_NVLINK_CAPS_UNCONTAINED_ERROR_RECOVERY = 1 : 0x20 # macro -NV2080_CTRL_NVLINK_CAPS_TBL_SIZE = 2 # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID = (0x00000000) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID = (0x00000000) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = (0x20803001) # macro -# NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS = 31 : 0 # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI = (0x00000001) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID = (0x00000002) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU = (0x00000001) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU = (0x00000002) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH = (0x00000003) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA = (0x00000004) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE = (0x000000FF) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID = (0xFFFFFFFF) # macro -# NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED = 0 : 0 # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE = (0x00000001) # macro -# NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY = 1 : 1 # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE = (0x00000000) # macro -NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE = (0x00000003) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX = (0x0000000a) # macro -NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID = (0xFFFFFFFF) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT = (0x0000000e) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT = (0x0000000e) # macro -NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_PHY_NVHS = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_PHY_GRS = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_PHY_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 = (0x00000004) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 = (0x00000005) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 = (0x00000006) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 = (0x00000007) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 = (0x00000008) # macro -NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK = (0x00000001) # macro -NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT = (0x00000002) # macro -NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE = (0x00000000) # macro -NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID = (0x000000FF) # macro -NV2080_CTRL_NVLINK_MAX_LINKS = 32 # macro -NV2080_CTRL_NVLINK_MAX_ARR_SIZE = 64 # macro -NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID = (0x00) # macro -NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS = (0x01) # macro -NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX = (0x02) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = (0x20803002) # macro -def NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i): # macro - return (((1<>i) -def NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT(intr, i): # macro - return NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr,i) -NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE = (0x00000001) # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_TL_INTEN_TRUE = (0x00000001) # macro -NV2080_CTRL_NVLINK_TL_INTEN_FALSE = (0x00000000) # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN = 0 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN = 1 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN = 2 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN = 3 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN = 4 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN = 5 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN = 6 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN = 7 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN = 8 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN = 9 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN = 10 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN = 12 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN = 13 # macro -NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX = 14 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR = 0 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR = 1 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR = 2 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR = 3 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR = 4 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR = 5 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR = 6 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR = 7 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR = 8 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR = 9 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR = 10 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR = 12 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR = 13 # macro -NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX = 14 # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS = (0x00000000) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN = (0x00000005) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE = (0x00000006) # macro -NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS = (0x00000000) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN = (0x00000005) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE = (0x00000006) # macro -NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF = (0x00000007) # macro -NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT = (0x0) # macro -NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS = (0x1) # macro -NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS = (0x2) # macro -NV2080_CTRL_NVLINK_MAX_IOCTRLS = 3 # macro -NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO = (0x20803003) # macro -NV2080_CTRL_NVLINK_COUNTER_INVALID = 0x00000000 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_TX0 = 0x00000001 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_TX1 = 0x00000002 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_RX0 = 0x00000004 # macro -NV2080_CTRL_NVLINK_COUNTER_TL_RX1 = 0x00000008 # macro -NV2080_CTRL_NVLINK_LP_COUNTERS_DL = 0x00000010 # macro -def NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L(i): # macro - return (1<<(i+8)) -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE = 4 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 = 0x00000100 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 = 0x00000200 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 = 0x00000400 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 = 0x00000800 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT = 0x00010000 # macro -def NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i): # macro - return (1<<(i+17)) -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE = 8 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 = 0x00020000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 = 0x00040000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 = 0x00080000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 = 0x00100000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 = 0x00200000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 = 0x00400000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 = 0x00800000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 = 0x01000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY = 0x02000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY = 0x04000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY = 0x08000000 # macro -NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED = 0x10000000 # macro -NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES = 32 # macro -NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_NVLINK_GET_COUNTERS = (0x20803004) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS = (0x20803005) # macro -NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 = 0 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 = 1 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 = 2 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 = 3 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE = 4 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 = 4 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 = 5 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 = 6 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 = 7 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE = 8 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 = 8 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 = 9 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 = 10 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 = 11 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 = 12 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 = 13 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 = 14 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 = 15 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY = 16 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY = 17 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY = 18 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED = 19 # macro -NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT = 20 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_DL = 21 # macro -NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER = 21 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS = 22 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES = 23 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS = 24 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES = 25 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER = 26 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER = 27 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER = 28 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS = 29 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS = 30 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS = 31 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR = 32 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR = 33 # macro -NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR = 34 # macro -NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS = 35 # macro -NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS = 36 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME = 37 # macro -NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS = 38 # macro -NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS = 39 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS = 40 # macro -NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS = 41 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 = 42 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 = 43 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL = 44 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 = 45 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 = 46 # macro -NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS = 47 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 = 48 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 = 49 # macro -NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL = 50 # macro -NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS = 51 # macro -NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS = 52 # macro -NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER = 53 # macro -NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS = 54 # macro -NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER = 55 # macro -NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS = 56 # macro -NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS = 57 # macro -NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR = 58 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS = 59 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS = 60 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS = 61 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS = 62 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS = 63 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS = 64 # macro -NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS = 65 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD = 66 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR = 67 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH = 68 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD = 69 # macro -NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR = 70 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 = 71 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 = 72 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 = 73 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 = 74 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 = 75 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 = 76 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 = 77 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 = 78 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 = 79 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 = 80 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 = 81 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 = 82 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 = 83 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 = 84 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 = 85 # macro -NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 = 86 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA = 87 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA = 88 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW = 89 # macro -NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW = 90 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY = 91 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE = 92 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_EXIT = 93 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL = 94 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE = 95 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME = 96 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME = 97 # macro -NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME = 98 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME = 99 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME = 100 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME = 101 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME = 102 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME = 103 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME = 104 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME = 105 # macro -NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME = 106 # macro -NV2080_CTRL_NVLINK_COUNTERS_MAX = 107 # macro -NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS = 2 # macro -NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ = 28 # macro -def NV2080_CTRL_NVLINK_COUNTER_V2_GROUP(i): # macro - return ((i)/64) -# def NV2080_CTRL_NVLINK_COUNTER_V2_COUNTER_MASK(i): # macro -# return ((NvU64)1<<((i)%64)) -NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x50) # macro -NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 = (0x20803050) # macro -NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x51) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 = (0x20803051) # macro -NV2080_CTRL_CMD_NVLINK_INJECT_ERROR = (0x20803006) # macro -NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_NVLINK_UNIT_DL = 0x01 # macro -NV2080_CTRL_NVLINK_UNIT_TL = 0x02 # macro -NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 = 0x03 # macro -NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 = 0x04 # macro -NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 = 0x05 # macro -NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 = 0x06 # macro -NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 = 0x07 # macro -NV2080_CTRL_NVLINK_UNIT_MINION = 0x08 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE = 31 : 28 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER = 0x00000001 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER = 0x00000002 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION = 27 : 12 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA = 11 : 8 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT = 7 : 0 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT = 15 : 0 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP = 16 : 16 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN = 0x00000001 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON = 17 : 17 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN = 0x00000001 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS = 18 : 18 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX = 3 : 0 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR = 4 : 4 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN = 0x00000001 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN = 0 : 0 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN = 0x00000001 # macro -NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x81) # macro -NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT = (0x20803081) # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE = 1 : 0 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST = 0x00000001 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR = 0x00000002 # macro -# NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS = 0 : 0 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT = 0x00000000 # macro -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT = 0x00000001 # macro -NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x82) # macro -NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT = (0x20803082) # macro -NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES = (0x20803007) # macro -NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE = (0x20803008) # macro -NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS = (0x20803009) # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY = 0 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY = 1 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL = 2 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW = 3 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY = 4 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY = 5 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP = 6 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON = 7 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY = 8 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY = 9 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT = 10 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY = 12 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG = 13 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM = 14 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE = 15 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT = 19 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY = 0 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY = 1 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY = 4 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY = 5 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY = 8 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY = 9 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY = 20 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN = 24 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC = 25 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW = 39 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW = 40 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY = 54 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY = 55 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY = 56 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY = 57 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY = 60 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP = 61 # macro -NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN = 62 # macro -NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES = 63 # macro -# def NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID(count, supportedCounts): # macro -# return (!!((supportedCounts)&NVBIT64(count))) -NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES = (0x2080300a) # macro -NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES = 5 # macro -NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE = (0x2080300b) # macro -NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_NVLINK_SETUP_EOM = (0x2080300c) # macro -NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE = (0x2080300d) # macro -NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L0 = (0x00) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L1 = (0x01) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L2 = (0x02) # macro -NV2080_CTRL_NVLINK_POWER_STATE_L3 = (0x03) # macro -NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE = (0x2080300e) # macro -NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR = (0x2080300f) # macro -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID = (0xF) # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES = (0x20803011) # macro -NV2080_CTRL_NVLINK_MAX_LANES = 4 # macro -NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER = (0x20803012) # macro -NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG = (0x20803013) # macro -NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID = (0x14) # macro -NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS = (0x20803014) # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX = 0 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX = 1 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX = 2 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX = 3 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX = 4 # macro -NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID = (0x15) # macro -NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS = (0x20803015) # macro -NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE = (0x20803016) # macro -NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID = (0x16) # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS = 0 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH = 1 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER = 2 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER = 3 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT = 4 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP = 5 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME = 6 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME = 7 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME = 8 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME = 9 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME = 10 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME = 11 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME = 12 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME = 13 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME = 14 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME = 15 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS = 16 # macro -NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID = (0x18) # macro -NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS = (0x20803018) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS = (0x20803052) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT = (0x00000000) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA = (0x00000001) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR = (0x00000002) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW = (0x00000003) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE = (0x00000004) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL = (0x00000005) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL = (0x00000006) # macro -NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID = (0x23) # macro -NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE = (0x20803023) # macro -NV2080_CTRL_NVLINK_MAX_LINK_COUNT = 32 # macro -NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x28) # macro -NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS = (0x20803028) # macro -NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x29) # macro -NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS = (0x20803029) # macro -NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID = (0x38) # macro -NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR = (0x20803038) # macro -NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID = (0x39) # macro -NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO = (0x20803039) # macro -NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS = (0x2080303a) # macro -NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID = (0x3b) # macro -NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS = (0x2080303b) # macro -NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID = (0x3c) # macro -NV2080_CTRL_CMD_NVLINK_EOM_CONTROL = (0x2080303c) # macro -NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE = 5120 # macro -NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID = (0x3d) # macro -NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE = (0x2080303d) # macro -NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT = (0xFFFFFFFF) # macro -NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3e) # macro -NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD = (0x2080303e) # macro -NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3f) # macro -NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD = (0x2080303f) # macro -NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID = (0x40) # macro -NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA = (0x20803040) # macro -NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID = (0x41) # macro -NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED = (0x20803041) # macro -NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID = (0x42) # macro -NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK = (0x20803042) # macro -NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID = (0x43) # macro -NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP = (0x20803043) # macro -NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE = 64 # macro -NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID = (0x44) # macro -NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS = (0x20803044) # macro -NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID = (0x45) # macro -NV2080_CTRL_CMD_NVLINK_CYCLE_LINK = (0x20803045) # macro -NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID = (0x46) # macro -NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG = (0x20803046) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH = 496 # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS = (0x20803047) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID = (0x47) # macro -NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY = (0x20803048) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC = (0x20803053) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID = (0x53) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM = (0x20803054) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID = (0x54) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC = (0x20803055) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID = (0x55) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM = (0x20803056) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID = (0x56) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR = (0x2080305c) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID = (0x5c) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE = (0x2080305e) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID = (0x5e) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE = (0x2080305f) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID = (0x5f) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP = (0x20803061) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID = (0x61) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU = (0x20803062) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID = (0x62) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP = (0x20803064) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID = (0x64) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT = (0x20803065) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID = (0x65) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR = (0x20803066) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID = (0x66) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT = (0x20803068) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID = (0x68) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT = (0x20803069) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID = (0x69) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR = (0x2080306a) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID = (0x6a) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS = (0x2080306b) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID = (0x6b) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR = (0x2080306c) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID = (0x6c) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP = (0x2080306d) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID = (0x6d) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID = (0x2080306e) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID = (0x6e) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT = (0x2080306f) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID = (0x6f) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS = (0x20803070) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID = (0x70) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG = (0x20803071) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID = (0x71) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS = (0x20803072) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID = (0x72) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR = (0x20803073) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID = (0x73) # macro -NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS = (0x20803074) # macro -NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID = (0x74) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD = (0x20803075) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID = (0x75) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP = (0x20803076) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID = (0x76) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF = (0x20803077) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID = (0x77) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL = (0x20803078) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID = (0x78) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM = (0x20803079) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID = (0x79) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE = (0x2080307a) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID = (0x7a) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM = (0x2080307b) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID = (0x7b) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR = (0x2080307c) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID = (0x7c) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR = (0x2080307d) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID = (0x7d) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS = (0x2080307e) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID = (0x7e) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC = (0x2080307f) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID = (0x7f) # macro -NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB = (0x20803080) # macro -NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID = (0x80) # macro -NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = (0x20803083) # macro -NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS = 18 # macro -NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN = (0x20803084) # macro -NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID = (0x84) # macro -NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT = 23 # macro -NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE = (0x20803085) # macro -NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID = (0x85) # macro -NV2080_CTRL_CMD_NVLINK_SET_BW_MODE = (0x20803086) # macro -NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID = (0x86) # macro -NV2080_CTRL_CMD_NVLINK_GET_BW_MODE = (0x20803087) # macro -NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID = (0x87) # macro -NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO = (0x20803088) # macro -NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x88) # macro -NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR = (0x20803089) # macro -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID = (0x89) # macro -NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY = (0x2080308a) # macro -NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE = (0x2080308e) # macro -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8E) # macro -NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE = (0x2080308f) # macro -NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8F) # macro -class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS._fields_ = [ - ('capsTbl', ctypes.c_uint32), - ('lowestNvlinkVersion', ctypes.c_ubyte), - ('highestNvlinkVersion', ctypes.c_ubyte), - ('lowestNciVersion', ctypes.c_ubyte), - ('highestNciVersion', ctypes.c_ubyte), - ('discoveredLinkMask', ctypes.c_uint32), - ('enabledLinkMask', ctypes.c_uint32), - ('discoveredLinks', ctypes.c_uint64), - ('enabledLinks', ctypes.c_uint64), + ('capsTbl', NvU32), + ('lowestNvlinkVersion', NvU8), + ('highestNvlinkVersion', NvU8), + ('lowestNciVersion', NvU8), + ('highestNciVersion', NvU8), + ('discoveredLinkMask', NvU32), + ('enabledLinkMask', NvU32), + ('discoveredLinks', NvU64), + ('enabledLinks', NvU64), ] - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS -class struct_NV2080_CTRL_NVLINK_DEVICE_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_DEVICE_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_DEVICE_INFO(Struct): pass struct_NV2080_CTRL_NVLINK_DEVICE_INFO._fields_ = [ - ('deviceIdFlags', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('bus', ctypes.c_uint16), - ('device', ctypes.c_uint16), - ('function', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('pciDeviceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('deviceType', ctypes.c_uint64), - ('deviceUUID', ctypes.c_ubyte * 16), - ('fabricRecoveryStatusMask', ctypes.c_uint32), - ('PADDING_2', ctypes.c_ubyte * 4), + ('deviceIdFlags', NvU32), + ('domain', NvU32), + ('bus', NvU16), + ('device', NvU16), + ('function', NvU16), + ('pciDeviceId', NvU32), + ('deviceType', NvU64), + ('deviceUUID', (NvU8 * 16)), + ('fabricRecoveryStatusMask', NvU32), ] - NV2080_CTRL_NVLINK_DEVICE_INFO = struct_NV2080_CTRL_NVLINK_DEVICE_INFO -class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO(Struct): pass struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO._fields_ = [ - ('capsTbl', ctypes.c_uint32), - ('phyType', ctypes.c_ubyte), - ('subLinkWidth', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('linkState', ctypes.c_uint32), - ('rxSublinkStatus', ctypes.c_ubyte), - ('txSublinkStatus', ctypes.c_ubyte), - ('bLaneReversal', ctypes.c_ubyte), - ('nvlinkVersion', ctypes.c_ubyte), - ('nciVersion', ctypes.c_ubyte), - ('phyVersion', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), - ('nvlinkLinkClockKHz', ctypes.c_uint32), - ('nvlinkCommonClockSpeedKHz', ctypes.c_uint32), - ('nvlinkRefClkSpeedKHz', ctypes.c_uint32), - ('nvlinkCommonClockSpeedMhz', ctypes.c_uint32), - ('nvlinkLineRateMbps', ctypes.c_uint32), - ('nvlinkLinkClockMhz', ctypes.c_uint32), - ('nvlinkRefClkType', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 3), - ('nvlinkLinkDataRateKiBps', ctypes.c_uint32), - ('nvlinkRefClkSpeedMhz', ctypes.c_uint32), - ('connected', ctypes.c_ubyte), - ('loopProperty', ctypes.c_ubyte), - ('remoteDeviceLinkNumber', ctypes.c_ubyte), - ('localDeviceLinkNumber', ctypes.c_ubyte), - ('PADDING_3', ctypes.c_ubyte * 4), - ('remoteLinkSid', ctypes.c_uint64), - ('localLinkSid', ctypes.c_uint64), - ('laneRxdetStatusMask', ctypes.c_uint32), - ('nvlinkMinL1Threshold', ctypes.c_uint32), - ('nvlinkMaxL1Threshold', ctypes.c_uint32), - ('nvlinkL1ThresholdUnits', ctypes.c_uint32), - ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), - ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), + ('capsTbl', NvU32), + ('phyType', NvU8), + ('subLinkWidth', NvU8), + ('linkState', NvU32), + ('rxSublinkStatus', NvU8), + ('txSublinkStatus', NvU8), + ('bLaneReversal', NvBool), + ('nvlinkVersion', NvU8), + ('nciVersion', NvU8), + ('phyVersion', NvU8), + ('nvlinkLinkClockKHz', NvU32), + ('nvlinkCommonClockSpeedKHz', NvU32), + ('nvlinkRefClkSpeedKHz', NvU32), + ('nvlinkCommonClockSpeedMhz', NvU32), + ('nvlinkLineRateMbps', NvU32), + ('nvlinkLinkClockMhz', NvU32), + ('nvlinkRefClkType', NvU8), + ('nvlinkLinkDataRateKiBps', NvU32), + ('nvlinkRefClkSpeedMhz', NvU32), + ('connected', NvBool), + ('loopProperty', NvU8), + ('remoteDeviceLinkNumber', NvU8), + ('localDeviceLinkNumber', NvU8), + ('remoteLinkSid', NvU64), + ('localLinkSid', NvU64), + ('laneRxdetStatusMask', NvU32), + ('nvlinkMinL1Threshold', NvU32), + ('nvlinkMaxL1Threshold', NvU32), + ('nvlinkL1ThresholdUnits', NvU32), + ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), + ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), ] - NV2080_CTRL_NVLINK_LINK_STATUS_INFO = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO +enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT = CEnum(ctypes.c_uint32) +NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT.define('NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', 0) +NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT.define('NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', 1) -# values for enumeration 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT' -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT__enumvalues = { - 0: 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', - 1: 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', -} -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = 0 -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = 1 -NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS._pack_ = 1 # source:False +NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT +class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS._fields_ = [ - ('enabledLinkMask', ctypes.c_uint32), - ('bSublinkStateInst', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('linkInfo', struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO * 64), + ('enabledLinkMask', NvU32), + ('bSublinkStateInst', NvBool), + ('linkInfo', (NV2080_CTRL_NVLINK_LINK_STATUS_INFO * 64)), ] - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS -class struct_NV2080_CTRL_NVLINK_ERR_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_ERR_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_ERR_INFO(Struct): pass struct_NV2080_CTRL_NVLINK_ERR_INFO._fields_ = [ - ('TLErrlog', ctypes.c_uint32), - ('TLIntrEn', ctypes.c_uint32), - ('TLCTxErrStatus0', ctypes.c_uint32), - ('TLCTxErrStatus1', ctypes.c_uint32), - ('TLCTxSysErrStatus0', ctypes.c_uint32), - ('TLCRxErrStatus0', ctypes.c_uint32), - ('TLCRxErrStatus1', ctypes.c_uint32), - ('TLCRxSysErrStatus0', ctypes.c_uint32), - ('TLCTxErrLogEn0', ctypes.c_uint32), - ('TLCTxErrLogEn1', ctypes.c_uint32), - ('TLCTxSysErrLogEn0', ctypes.c_uint32), - ('TLCRxErrLogEn0', ctypes.c_uint32), - ('TLCRxErrLogEn1', ctypes.c_uint32), - ('TLCRxSysErrLogEn0', ctypes.c_uint32), - ('MIFTxErrStatus0', ctypes.c_uint32), - ('MIFRxErrStatus0', ctypes.c_uint32), - ('NVLIPTLnkErrStatus0', ctypes.c_uint32), - ('NVLIPTLnkErrLogEn0', ctypes.c_uint32), - ('NVLIPTLnkCtrlLinkStateRequest', ctypes.c_uint32), - ('DLSpeedStatusTx', ctypes.c_uint32), - ('DLSpeedStatusRx', ctypes.c_uint32), - ('NVLDLRxSlsmErrCntl', ctypes.c_uint32), - ('NVLDLTopLinkState', ctypes.c_uint32), - ('NVLDLTopIntr', ctypes.c_uint32), - ('DLStatMN00', ctypes.c_uint32), - ('DLStatUC01', ctypes.c_uint32), - ('MinionNvlinkLinkIntr', ctypes.c_uint32), - ('bExcessErrorDL', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('TLErrlog', NvU32), + ('TLIntrEn', NvU32), + ('TLCTxErrStatus0', NvU32), + ('TLCTxErrStatus1', NvU32), + ('TLCTxSysErrStatus0', NvU32), + ('TLCRxErrStatus0', NvU32), + ('TLCRxErrStatus1', NvU32), + ('TLCRxSysErrStatus0', NvU32), + ('TLCTxErrLogEn0', NvU32), + ('TLCTxErrLogEn1', NvU32), + ('TLCTxSysErrLogEn0', NvU32), + ('TLCRxErrLogEn0', NvU32), + ('TLCRxErrLogEn1', NvU32), + ('TLCRxSysErrLogEn0', NvU32), + ('MIFTxErrStatus0', NvU32), + ('MIFRxErrStatus0', NvU32), + ('NVLIPTLnkErrStatus0', NvU32), + ('NVLIPTLnkErrLogEn0', NvU32), + ('NVLIPTLnkCtrlLinkStateRequest', NvU32), + ('DLSpeedStatusTx', NvU32), + ('DLSpeedStatusRx', NvU32), + ('NVLDLRxSlsmErrCntl', NvU32), + ('NVLDLTopLinkState', NvU32), + ('NVLDLTopIntr', NvU32), + ('DLStatMN00', NvU32), + ('DLStatUC01', NvU32), + ('MinionNvlinkLinkIntr', NvU32), + ('bExcessErrorDL', NvBool), ] - NV2080_CTRL_NVLINK_ERR_INFO = struct_NV2080_CTRL_NVLINK_ERR_INFO -class struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO(Struct): pass struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO._fields_ = [ - ('NVLIPTErrStatus0', ctypes.c_uint32), - ('NVLIPTErrLogEn0', ctypes.c_uint32), + ('NVLIPTErrStatus0', NvU32), + ('NVLIPTErrLogEn0', NvU32), ] - NV2080_CTRL_NVLINK_COMMON_ERR_INFO = struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO -class struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('linkErrInfo', struct_NV2080_CTRL_NVLINK_ERR_INFO * 64), - ('ioctrlMask', ctypes.c_uint32), - ('commonErrInfo', struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO * 3), - ('ErrInfoFlags', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkMask', NvU32), + ('linkErrInfo', (NV2080_CTRL_NVLINK_ERR_INFO * 64)), + ('ioctrlMask', NvU32), + ('commonErrInfo', (NV2080_CTRL_NVLINK_COMMON_ERR_INFO * 3)), + ('ErrInfoFlags', NvU8), ] - NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES(Struct): pass struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES._fields_ = [ - ('bTx0TlCounterOverflow', ctypes.c_ubyte), - ('bTx1TlCounterOverflow', ctypes.c_ubyte), - ('bRx0TlCounterOverflow', ctypes.c_ubyte), - ('bRx1TlCounterOverflow', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 4), - ('value', ctypes.c_uint64 * 32), + ('bTx0TlCounterOverflow', NvBool), + ('bTx1TlCounterOverflow', NvBool), + ('bRx0TlCounterOverflow', NvBool), + ('bRx1TlCounterOverflow', NvBool), + ('value', (NvU64 * 32)), ] - NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES -class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('linkMask', ctypes.c_uint64), - ('counters', struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES * 64), + ('counterMask', NvU32), + ('linkMask', NvU64), + ('counters', (NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES * 64)), ] - NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('linkMask', ctypes.c_uint64), + ('counterMask', NvU32), + ('linkMask', NvU64), ] - NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES(Structure): - pass - -struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES(Struct): pass struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES._fields_ = [ - ('overFlow', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('value', ctypes.c_uint64), + ('overFlow', NvBool), + ('value', NvU64), ] - NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES = struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES -class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('counterMask', ctypes.c_uint64 * 2), - ('counter', struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES * 28 * 64), + ('linkMask', NvU64), + ('counterMask', (NvU64 * 2)), + ('counter', ((NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES * 28) * 64)), ] - NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS -class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('counterMask', ctypes.c_uint64 * 2), + ('linkMask', NvU64), + ('counterMask', (NvU64 * 2)), ] - NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS -class struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('bFatalError', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkMask', NvU32), + ('bFatalError', NvBool), ] - NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS +enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', 1) +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', 2) +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', 3) +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', 4) +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', 5) -# values for enumeration 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE' -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE__enumvalues = { - 1: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', - 2: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', - 3: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', - 4: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', - 5: 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', -} -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = 1 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = 2 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = 3 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = 4 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = 5 -NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG(Structure): - pass - -struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG._pack_ = 1 # source:False +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE +class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG(Struct): pass struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG._fields_ = [ - ('errType', NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE), - ('PADDING_0', ctypes.c_ubyte * 4), - ('errSettings', ctypes.c_uint64), + ('errType', NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE), + ('errSettings', NvU64), ] - NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG -class struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('errCfg', struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG * 64), + ('linkMask', NvU64), + ('errCfg', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG * 64)), ] - NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS = struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS -class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO(Struct): pass struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO._fields_ = [ - ('txErrInfo', ctypes.c_uint32), - ('packetErrInfo', ctypes.c_uint32), - ('authErrInfo', ctypes.c_uint32), - ('linkStatus', ctypes.c_uint32), - ('errInjectStatus', ctypes.c_uint32), + ('txErrInfo', NvU32), + ('packetErrInfo', NvU32), + ('authErrInfo', NvU32), + ('linkStatus', NvU32), + ('errInjectStatus', NvU32), ] - NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO -class struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint64), - ('errInfo', struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO * 64), + ('linkMask', NvU64), + ('errInfo', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO * 64)), ] - NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS = struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('numRecoveries', ctypes.c_uint32 * 64), + ('linkMask', NvU32), + ('numRecoveries', (NvU32 * 64)), ] - NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('remoteType', ctypes.c_uint32), + ('linkId', NvU32), + ('remoteType', NvU32), ] - NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('supportedCounts', ctypes.c_uint64), - ('fatalErrorCounts', ctypes.c_ubyte * 63), - ('PADDING_1', ctypes.c_ubyte), + ('linkId', NvU32), + ('supportedCounts', NvU64), + ('fatalErrorCounts', (NvU8 * 63)), ] - NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS -class struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE(Structure): - pass - -struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE(Struct): pass struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE._fields_ = [ - ('errorsPerMinute', ctypes.c_uint32), - ('timestamp', ctypes.c_uint32), + ('errorsPerMinute', NvU32), + ('timestamp', NvU32), ] - NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE = struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE -class struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('numDailyMaxNonfatalErrorRates', ctypes.c_uint32), - ('dailyMaxNonfatalErrorRates', struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5), - ('numMonthlyMaxNonfatalErrorRates', ctypes.c_uint32), - ('monthlyMaxNonfatalErrorRates', struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5), + ('linkId', NvU32), + ('numDailyMaxNonfatalErrorRates', NvU32), + ('dailyMaxNonfatalErrorRates', (NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5)), + ('numMonthlyMaxNonfatalErrorRates', NvU32), + ('monthlyMaxNonfatalErrorRates', (NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5)), ] - NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS._fields_ = [ - ('bEnabled', ctypes.c_ubyte), + ('bEnabled', NvBool), ] - NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS._fields_ = [ - ('linkId', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('params', ctypes.c_uint32), + ('linkId', NvU8), + ('params', NvU32), ] - NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('powerState', ctypes.c_uint32), + ('linkMask', NvU32), + ('powerState', NvU32), ] - NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('powerState', ctypes.c_uint32), + ('linkId', NvU32), + ('powerState', NvU32), ] - NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS +enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE = CEnum(ctypes.c_uint32) +TLC_RX_LNK = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE.define('TLC_RX_LNK', 0) +TLC_TX_SYS = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE.define('TLC_TX_SYS', 1) -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE' -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE__enumvalues = { - 0: 'TLC_RX_LNK', - 1: 'TLC_TX_SYS', -} -TLC_RX_LNK = 0 -TLC_TX_SYS = 1 -NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE = ctypes.c_uint32 # enum +NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE +enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE = CEnum(ctypes.c_uint32) +TX_SYS_TX_RSP_STATUS_HW_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_HW_ERR', 0) +TX_SYS_TX_RSP_STATUS_UR_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_UR_ERR', 1) +TX_SYS_TX_RSP_STATUS_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_PRIV_ERR', 2) -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE' -NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE__enumvalues = { - 0: 'TX_SYS_TX_RSP_STATUS_HW_ERR', - 1: 'TX_SYS_TX_RSP_STATUS_UR_ERR', - 2: 'TX_SYS_TX_RSP_STATUS_PRIV_ERR', -} -TX_SYS_TX_RSP_STATUS_HW_ERR = 0 -TX_SYS_TX_RSP_STATUS_UR_ERR = 1 -TX_SYS_TX_RSP_STATUS_PRIV_ERR = 2 -NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE' -NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE__enumvalues = { - 0: 'RX_LNK_RX_RSP_STATUS_HW_ERR', - 1: 'RX_LNK_RX_RSP_STATUS_UR_ERR', - 2: 'RX_LNK_RX_RSP_STATUS_PRIV_ERR', -} -RX_LNK_RX_RSP_STATUS_HW_ERR = 0 -RX_LNK_RX_RSP_STATUS_UR_ERR = 1 -RX_LNK_RX_RSP_STATUS_PRIV_ERR = 2 -NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE = ctypes.c_uint32 # enum -class union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('txSysErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE), - ('rxLnkErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE), - ] +NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE +enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE = CEnum(ctypes.c_uint32) +RX_LNK_RX_RSP_STATUS_HW_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_HW_ERR', 0) +RX_LNK_RX_RSP_STATUS_UR_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_UR_ERR', 1) +RX_LNK_RX_RSP_STATUS_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_PRIV_ERR', 2) +NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE +class union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE(ctypes.Union): pass +union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE._fields_ = [ + ('txSysErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE), + ('rxLnkErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE), +] NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE = union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE -class struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('device', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE), - ('bBroadcast', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('errorType', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE), + ('linkId', NvU32), + ('device', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE), + ('bBroadcast', NvBool), + ('errorType', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE), ] - NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('numLanes', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('figureOfMeritValues', ctypes.c_uint16 * 4), - ('PADDING_1', ctypes.c_ubyte * 2), + ('linkId', NvU32), + ('numLanes', NvU8), + ('figureOfMeritValues', (NvU16 * 4)), ] - NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS._fields_ = [ - ('peerMask', ctypes.c_uint32), - ('bEnable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('peerMask', NvU32), + ('bEnable', NvBool), ] - NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS -class struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS._fields_ = [ - ('linkId', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('addr', ctypes.c_uint16), - ('phyConfigData', ctypes.c_uint32), + ('linkId', NvU8), + ('lane', NvU8), + ('addr', NvU16), + ('phyConfigData', NvU32), ] - NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS = struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS -class struct_NV2080_CTRL_NVLINK_LANE_ERROR(Structure): - pass - -struct_NV2080_CTRL_NVLINK_LANE_ERROR._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_LANE_ERROR(Struct): pass struct_NV2080_CTRL_NVLINK_LANE_ERROR._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('eccErrorValue', ctypes.c_uint32), - ('overflowed', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 3), + ('bValid', NvBool), + ('eccErrorValue', NvU32), + ('overflowed', NvBool), ] - NV2080_CTRL_NVLINK_LANE_ERROR = struct_NV2080_CTRL_NVLINK_LANE_ERROR -class struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR(Structure): - pass - -struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR(Struct): pass struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR._fields_ = [ - ('errorLane', struct_NV2080_CTRL_NVLINK_LANE_ERROR * 4), - ('eccDecFailed', ctypes.c_uint32), - ('eccDecFailedOverflowed', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('errorLane', (NV2080_CTRL_NVLINK_LANE_ERROR * 4)), + ('eccDecFailed', NvU32), + ('eccDecFailedOverflowed', NvBool), ] - NV2080_CTRL_NVLINK_LINK_ECC_ERROR = struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR -class struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('errorLink', struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR * 64), + ('linkMask', NvU32), + ('errorLink', (NV2080_CTRL_NVLINK_LINK_ECC_ERROR * 64)), ] - NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS -class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES(Struct): pass struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES._fields_ = [ - ('value', ctypes.c_uint64 * 4), + ('value', (NvU64 * 4)), ] - NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES -class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 6), - ('linkMask', ctypes.c_uint64), - ('counters', struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES * 64), + ('counterMask', NvU16), + ('linkMask', NvU64), + ('counters', (NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES * 64)), ] - NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS -class struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS._fields_ = [ - ('bLockPowerMode', ctypes.c_ubyte), + ('bLockPowerMode', NvBool), ] - NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('counterValidMask', ctypes.c_uint32), - ('counterValues', ctypes.c_uint32 * 16), + ('linkId', NvU32), + ('counterValidMask', NvU32), + ('counterValues', (NvU32 * 16)), ] - NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('loopbackMode', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkId', NvU32), + ('loopbackMode', NvU8), ] - NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO(Struct): pass struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO._fields_ = [ - ('bValid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('passCount', ctypes.c_uint16), - ('failCount', ctypes.c_uint16), + ('bValid', NvBool), + ('passCount', NvU16), + ('failCount', NvU16), ] - NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO = struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO -class struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('refreshCount', struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO * 32), + ('linkMask', NvU32), + ('refreshCount', (NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO * 32)), ] - NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), + ('linkMask', NvU32), ] - NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS._fields_ = [ - ('bGet', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 7), - ('addr', ctypes.c_uint64), + ('bGet', NvBool), + ('addr', NvU64), ] - NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS -class struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS._fields_ = [ - ('discoveredLinks', ctypes.c_uint64), - ('connectedLinksMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bridgeSensableLinks', ctypes.c_uint64), - ('bridgedLinks', ctypes.c_uint32), - ('initDisabledLinksMask', ctypes.c_uint32), - ('vbiosDisabledLinkMask', ctypes.c_uint64), - ('initializedLinks', ctypes.c_uint32), - ('bEnableTrainingAtLoad', ctypes.c_ubyte), - ('bEnableSafeModeAtLoad', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), + ('discoveredLinks', NvU64), + ('connectedLinksMask', NvU32), + ('bridgeSensableLinks', NvU64), + ('bridgedLinks', NvU32), + ('initDisabledLinksMask', NvU32), + ('vbiosDisabledLinkMask', NvU64), + ('initializedLinks', NvU32), + ('bEnableTrainingAtLoad', NvBool), + ('bEnableSafeModeAtLoad', NvBool), ] - NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS -class struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS._fields_ = [ - ('initDisabledLinksMask', ctypes.c_uint32), - ('bSkipHwNvlinkDisable', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('initDisabledLinksMask', NvU32), + ('bSkipHwNvlinkDisable', NvBool), ] - NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS = struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS +enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND = CEnum(ctypes.c_uint32) +NVLINK_EOM_CONTROL_START_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_START_EOM', 0) +NVLINK_EOM_CONTROL_END_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_END_EOM', 1) +NVLINK_EOM_CONTROL_CONFIG_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_CONFIG_EOM', 2) +NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE', 3) -# values for enumeration 'NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND' -NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND__enumvalues = { - 0: 'NVLINK_EOM_CONTROL_START_EOM', - 1: 'NVLINK_EOM_CONTROL_END_EOM', - 2: 'NVLINK_EOM_CONTROL_CONFIG_EOM', - 3: 'NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE', -} -NVLINK_EOM_CONTROL_START_EOM = 0 -NVLINK_EOM_CONTROL_END_EOM = 1 -NVLINK_EOM_CONTROL_CONFIG_EOM = 2 -NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3 -NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT(Structure): - pass - -struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT._pack_ = 1 # source:False +NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND +class struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT(Struct): pass struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT._fields_ = [ - ('upper', ctypes.c_ubyte), - ('middle', ctypes.c_ubyte), - ('lower', ctypes.c_ubyte), - ('composite', ctypes.c_ubyte), + ('upper', NvU8), + ('middle', NvU8), + ('lower', NvU8), + ('composite', NvU8), ] - NV2080_CTRL_NVLINK_EOM_MEASUREMENT = struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT -class struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS._fields_ = [ - ('cmd', NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND), - ('linkId', ctypes.c_uint32), - ('params', ctypes.c_uint32), - ('measurements', struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT * 4), + ('cmd', NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND), + ('linkId', NvU32), + ('params', NvU32), + ('measurements', (NV2080_CTRL_NVLINK_EOM_MEASUREMENT * 4)), ] - NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS = struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS -class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS._fields_ = [ - ('data', ctypes.c_ubyte * 5120), - ('dataSize', ctypes.c_uint32), + ('data', (NvU8 * 5120)), + ('dataSize', NvU32), ] - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS._fields_ = [ - ('l1Threshold', ctypes.c_uint32), - ('l1ExitThreshold', ctypes.c_uint32), + ('l1Threshold', NvU32), + ('l1ExitThreshold', NvU32), ] - NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS = struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS._fields_ = [ - ('l1Threshold', ctypes.c_uint32), - ('l1ExitThreshold', ctypes.c_uint32), + ('l1Threshold', NvU32), + ('l1ExitThreshold', NvU32), ] - NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS = struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS -class struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS._fields_ = [ - ('buffer', ctypes.c_ubyte * 5120), - ('dataSize', ctypes.c_uint32), + ('buffer', (NvU8 * 5120)), + ('dataSize', NvU32), ] - NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS = struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS -class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), - ('bIsGpuDegraded', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('linkId', NvU32), + ('bIsGpuDegraded', NvBool), ] - NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS = struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS -class struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS._fields_ = [ - ('bIsEnoughNvLink', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numBridge', ctypes.c_uint32), - ('bridgePresenceMask', ctypes.c_uint32), + ('bIsEnoughNvLink', NvBool), + ('numBridge', NvU32), + ('bridgePresenceMask', NvU32), ] - NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS = struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS -class struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), + ('linkId', NvU32), ] - NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS = struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS -class struct_NV2080_CTRL_NVLINK_PORT_EVENT(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PORT_EVENT._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PORT_EVENT(Struct): pass struct_NV2080_CTRL_NVLINK_PORT_EVENT._fields_ = [ - ('portEventType', ctypes.c_uint32), - ('gpuId', ctypes.c_uint32), - ('linkId', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('time', ctypes.c_uint64), + ('portEventType', NvU32), + ('gpuId', NvU32), + ('linkId', NvU32), + ('time', NvU64), ] - NV2080_CTRL_NVLINK_PORT_EVENT = struct_NV2080_CTRL_NVLINK_PORT_EVENT -class struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS._fields_ = [ - ('portEventIndex', ctypes.c_uint64), - ('nextPortEventIndex', ctypes.c_uint64), - ('portEventCount', ctypes.c_uint32), - ('bOverflow', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('portEvent', struct_NV2080_CTRL_NVLINK_PORT_EVENT * 64), + ('portEventIndex', NvU64), + ('nextPortEventIndex', NvU64), + ('portEventCount', NvU32), + ('bOverflow', NvBool), + ('portEvent', (NV2080_CTRL_NVLINK_PORT_EVENT * 64)), ] - NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS -class struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS._fields_ = [ - ('linkId', ctypes.c_uint32), + ('linkId', NvU32), ] - NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS = struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS -class struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS._fields_ = [ - ('bReducedNvlinkConfig', ctypes.c_ubyte), + ('bReducedNvlinkConfig', NvBool), ] - NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS = struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_DATA(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_DATA._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_DATA(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_DATA._fields_ = [ - ('data', ctypes.c_ubyte * 496), + ('data', (NvU8 * 496)), ] - NV2080_CTRL_NVLINK_PRM_DATA = struct_NV2080_CTRL_NVLINK_PRM_DATA -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('plane_ind', ctypes.c_ubyte), - ('admin_status', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('swid', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('fd', ctypes.c_ubyte), - ('ps_e', ctypes.c_ubyte), - ('ls_e', ctypes.c_ubyte), - ('ee_ps', ctypes.c_ubyte), - ('ee_ls', ctypes.c_ubyte), - ('ee', ctypes.c_ubyte), - ('ase', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('plane_ind', NvU8), + ('admin_status', NvU8), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('swid', NvU8), + ('e', NvU8), + ('fd', NvU8), + ('ps_e', NvU8), + ('ls_e', NvU8), + ('ee_ps', NvU8), + ('ee_ls', NvU8), + ('ee', NvU8), + ('ase', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lane_mask', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('local_tx_precoding_admin', ctypes.c_ubyte), - ('local_rx_precoding_admin', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('lane_mask', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('local_tx_precoding_admin', NvU8), + ('local_rx_precoding_admin', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('test_mode', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('fec_override_admin_10g_40g', ctypes.c_ubyte), - ('fec_override_admin_25g', ctypes.c_ubyte), - ('fec_override_admin_50g', ctypes.c_ubyte), - ('fec_override_admin_100g', ctypes.c_ubyte), - ('fec_override_admin_56g', ctypes.c_ubyte), - ('rs_fec_correction_bypass_admin', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('fec_override_admin_200g_4x', ctypes.c_uint16), - ('fec_override_admin_400g_8x', ctypes.c_uint16), - ('fec_override_admin_50g_1x', ctypes.c_uint16), - ('fec_override_admin_100g_2x', ctypes.c_uint16), - ('fec_override_admin_400g_4x', ctypes.c_uint16), - ('fec_override_admin_800g_8x', ctypes.c_uint16), - ('fec_override_admin_100g_1x', ctypes.c_uint16), - ('fec_override_admin_200g_2x', ctypes.c_uint16), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('test_mode', NvBool), + ('plane_ind', NvU8), + ('port_type', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('fec_override_admin_10g_40g', NvU8), + ('fec_override_admin_25g', NvU8), + ('fec_override_admin_50g', NvU8), + ('fec_override_admin_100g', NvU8), + ('fec_override_admin_56g', NvU8), + ('rs_fec_correction_bypass_admin', NvU8), + ('fec_override_admin_200g_4x', NvU16), + ('fec_override_admin_400g_8x', NvU16), + ('fec_override_admin_50g_1x', NvU16), + ('fec_override_admin_100g_2x', NvU16), + ('fec_override_admin_400g_4x', NvU16), + ('fec_override_admin_800g_8x', NvU16), + ('fec_override_admin_100g_1x', NvU16), + ('fec_override_admin_200g_2x', NvU16), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('l1_req_en', ctypes.c_ubyte), - ('l1_fw_req_en', ctypes.c_ubyte), - ('l1_cap_adv', ctypes.c_ubyte), - ('l1_fw_cap_adv', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('hp_queues_bitmap', ctypes.c_uint32), - ('l1_hw_active_time', ctypes.c_uint16), - ('l1_hw_inactive_time', ctypes.c_uint16), - ('qem', ctypes.c_ubyte * 8), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('l1_req_en', NvBool), + ('l1_fw_req_en', NvBool), + ('l1_cap_adv', NvBool), + ('l1_fw_cap_adv', NvBool), + ('hp_queues_bitmap', NvU32), + ('l1_hw_active_time', NvU16), + ('l1_hw_inactive_time', NvU16), + ('qem', (NvU8 * 8)), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('access_reg_group', ctypes.c_ubyte), - ('feature_group', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('access_reg_group', NvU8), + ('feature_group', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('slot_index', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('slot_index', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('slot_index', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('slot_index', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('slot_index', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('itre', ctypes.c_ubyte), - ('i_e', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('protocol', ctypes.c_ubyte), - ('admin_mtu', ctypes.c_uint16), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('itre', NvBool), + ('i_e', NvU8), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('protocol', NvU8), + ('admin_mtu', NvU16), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('width', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('m_lane_m', ctypes.c_ubyte), - ('rxtx', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('width', NvU8), + ('plane_ind', NvU8), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('m_lane_m', NvBool), + ('rxtx', NvBool), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('trap_id', ctypes.c_uint16), - ('action', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('trap_id', NvU16), + ('action', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('port_type', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('page_select', ctypes.c_ubyte), - ('module_info_ext', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('port_type', NvU8), + ('plane_ind', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('page_select', NvU8), + ('module_info_ext', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('le', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('sw', ctypes.c_ubyte), - ('dm_ig', ctypes.c_ubyte), - ('p', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('modulation', ctypes.c_ubyte), - ('prbs_mode_admin', ctypes.c_ubyte), - ('prbs_fec_admin', ctypes.c_ubyte), - ('lane_rate_admin', ctypes.c_uint16), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('le', NvBool), + ('port_type', NvU8), + ('lane', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('sw', NvBool), + ('dm_ig', NvBool), + ('p', NvBool), + ('e', NvBool), + ('modulation', NvU8), + ('prbs_mode_admin', NvU8), + ('prbs_fec_admin', NvBool), + ('lane_rate_admin', NvU16), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('grp', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('swid', ctypes.c_ubyte), - ('prio_tc', ctypes.c_ubyte), - ('grp_profile', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('counters_cap', ctypes.c_ubyte), - ('lp_gl', ctypes.c_ubyte), - ('clr', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('grp', NvU8), + ('port_type', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('swid', NvU8), + ('prio_tc', NvU8), + ('grp_profile', NvU8), + ('plane_ind', NvU8), + ('counters_cap', NvBool), + ('lp_gl', NvBool), + ('clr', NvBool), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('port_type', ctypes.c_ubyte), - ('phy_test_mode_admin', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('swid', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('phy_status_admin', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('port_type', NvU8), + ('phy_test_mode_admin', NvU8), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('swid', NvU8), + ('plane_ind', NvU8), + ('phy_status_admin', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('hist_type', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('plane_ind', NvU8), + ('port_type', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('hist_type', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('c_db', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lane_speed', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('tx_policy', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('c_db', NvBool), + ('port_type', NvU8), + ('lane_speed', NvU8), + ('lane', NvU8), + ('tx_policy', NvBool), + ('pnat', NvU8), + ('local_port', NvU8), + ('lp_msb', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('le', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('sw', ctypes.c_ubyte), - ('dm_ig', ctypes.c_ubyte), - ('p', ctypes.c_ubyte), - ('s', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('modulation', ctypes.c_ubyte), - ('prbs_mode_admin', ctypes.c_ubyte), - ('lane_rate_oper', ctypes.c_uint16), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('le', NvBool), + ('port_type', NvU8), + ('lane', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), + ('sw', NvBool), + ('dm_ig', NvBool), + ('p', NvBool), + ('s', NvBool), + ('e', NvBool), + ('modulation', NvU8), + ('prbs_mode_admin', NvU8), + ('lane_rate_oper', NvU16), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('proto_mask', ctypes.c_ubyte), - ('transmit_allowed', ctypes.c_ubyte), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('tx_ready_e', ctypes.c_ubyte), - ('ee_tx_ready', ctypes.c_ubyte), - ('an_disable_admin', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('ext_eth_proto_admin', ctypes.c_uint32), - ('eth_proto_admin', ctypes.c_uint32), - ('ib_proto_admin', ctypes.c_uint16), - ('ib_link_width_admin', ctypes.c_uint16), - ('xdr_2x_slow_admin', ctypes.c_ubyte), - ('force_lt_frames_admin', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 2), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('proto_mask', NvU8), + ('transmit_allowed', NvBool), + ('plane_ind', NvU8), + ('port_type', NvU8), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('tx_ready_e', NvU8), + ('ee_tx_ready', NvBool), + ('an_disable_admin', NvBool), + ('ext_eth_proto_admin', NvU32), + ('eth_proto_admin', NvU32), + ('ib_proto_admin', NvU16), + ('ib_link_width_admin', NvU16), + ('xdr_2x_slow_admin', NvBool), + ('force_lt_frames_admin', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('port_type', ctypes.c_ubyte), - ('lane', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('pnat', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('port_type', NvU8), + ('lane', NvU8), + ('lp_msb', NvU8), + ('pnat', NvU8), + ('local_port', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('admin_status', ctypes.c_ubyte), - ('module', ctypes.c_ubyte), - ('slot_index', ctypes.c_ubyte), - ('rst', ctypes.c_ubyte), - ('e', ctypes.c_ubyte), - ('ee', ctypes.c_ubyte), - ('ase', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('admin_status', NvU8), + ('module', NvU8), + ('slot_index', NvU8), + ('rst', NvBool), + ('e', NvU8), + ('ee', NvBool), + ('ase', NvBool), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('plane_ind', ctypes.c_ubyte), - ('port_type', ctypes.c_ubyte), - ('op_mod', ctypes.c_ubyte), - ('apply_im', ctypes.c_ubyte), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('lb_en', ctypes.c_uint16), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('plane_ind', NvU8), + ('port_type', NvU8), + ('op_mod', NvBool), + ('apply_im', NvBool), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('lb_en', NvU16), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS._fields_ = [ - ('counterMask', ctypes.c_uint64 * 2), + ('counterMask', (NvU64 * 2)), ] - NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('segment_type', ctypes.c_uint16), - ('seq_num', ctypes.c_ubyte), - ('vhca_id_valid', ctypes.c_ubyte), - ('inline_dump', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), - ('vhca_id', ctypes.c_uint16), - ('PADDING_2', ctypes.c_ubyte * 2), - ('index1', ctypes.c_uint32), - ('index2', ctypes.c_uint32), - ('num_of_obj2', ctypes.c_uint16), - ('num_of_obj1', ctypes.c_uint16), - ('device_opaque', ctypes.c_uint64), - ('mkey', ctypes.c_uint32), - ('PADDING_3', ctypes.c_ubyte * 4), - ('address', ctypes.c_uint64), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('segment_type', NvU16), + ('seq_num', NvU8), + ('vhca_id_valid', NvBool), + ('inline_dump', NvBool), + ('vhca_id', NvU16), + ('index1', NvU32), + ('index2', NvU32), + ('num_of_obj2', NvU16), + ('num_of_obj1', NvU16), + ('device_opaque', NvU64), + ('mkey', NvU32), + ('address', NvU64), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('trace_owner', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('trace_owner', NvBool), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('trace_mode', ctypes.c_ubyte), - ('log_trace_buffer_size', ctypes.c_ubyte), - ('trace_mkey', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('trace_mode', NvU8), + ('log_trace_buffer_size', NvU8), + ('trace_mkey', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('modify_field_select', ctypes.c_uint16), - ('arm_event', ctypes.c_ubyte), - ('trace_status', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('modify_field_select', NvU16), + ('arm_event', NvBool), + ('trace_status', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('enable_all', ctypes.c_ubyte), - ('log_delay', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('source_id_bitmask', ctypes.c_uint32 * 8), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('enable_all', NvU8), + ('log_delay', NvU8), + ('source_id_bitmask', (NvU32 * 8)), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('log_level', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('log_bit_mask', ctypes.c_uint32), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('log_level', NvU8), + ('log_bit_mask', NvU32), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('warning_inactive_time', ctypes.c_ubyte), - ('warning_active_time', ctypes.c_ubyte), - ('critical_inactive_time', ctypes.c_ubyte), - ('critical_active_time', ctypes.c_ubyte), - ('cc', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('warning_inactive_time', NvU8), + ('warning_active_time', NvU8), + ('critical_inactive_time', NvU8), + ('critical_active_time', NvU8), + ('cc', NvBool), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('lp_msb', NvU8), + ('local_port', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('cnt_64bit', ctypes.c_ubyte), - ('stop_at_ff', ctypes.c_ubyte), - ('counter_rst', ctypes.c_ubyte), - ('counter_en', ctypes.c_ubyte), - ('force_count_mask', ctypes.c_ubyte), - ('cnt_type', ctypes.c_ubyte * 8), - ('cnt_val', ctypes.c_ubyte * 8), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('cnt_64bit', NvU8), + ('stop_at_ff', NvBool), + ('counter_rst', NvBool), + ('counter_en', NvBool), + ('force_count_mask', NvU8), + ('cnt_type', (NvU8 * 8)), + ('cnt_val', (NvU8 * 8)), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS -class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS._fields_ = [ - ('bWrite', ctypes.c_ubyte), - ('prm', NV2080_CTRL_NVLINK_PRM_DATA), - ('PADDING_0', ctypes.c_ubyte), - ('ib_port', ctypes.c_uint16), - ('lp_msb', ctypes.c_ubyte), - ('local_port', ctypes.c_ubyte), - ('split_num', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte), + ('bWrite', NvBool), + ('prm', NV2080_CTRL_NVLINK_PRM_DATA), + ('ib_port', NvU16), + ('lp_msb', NvU8), + ('local_port', NvU8), + ('split_num', NvU8), ] - NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS._fields_ = [ - ('ibGuid', ctypes.c_ubyte * 16), - ('rackGuid', ctypes.c_ubyte * 16), - ('chassisPhysicalSlotNumber', ctypes.c_ubyte), - ('computeSlotIndex', ctypes.c_ubyte), - ('nodeIndex', ctypes.c_ubyte), - ('peerType', ctypes.c_ubyte), - ('moduleId', ctypes.c_ubyte), + ('ibGuid', (NvU8 * 16)), + ('rackGuid', (NvU8 * 16)), + ('chassisPhysicalSlotNumber', NvU8), + ('computeSlotIndex', NvU8), + ('nodeIndex', NvU8), + ('peerType', NvU8), + ('moduleId', NvU8), ] - NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS -class struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD(Structure): - pass - -struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD(Struct): pass struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD._fields_ = [ - ('pllIndex', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('address', ctypes.c_uint16), + ('pllIndex', NvU8), + ('address', NvU16), ] - NV2080_CTRL_NVLINK_UPHY_CLN_CMD = struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD -class struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('uphyCmd', struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD * 18), - ('data', ctypes.c_uint32 * 18), + ('linkMask', NvU32), + ('uphyCmd', (NV2080_CTRL_NVLINK_UPHY_CLN_CMD * 18)), + ('data', (NvU32 * 18)), ] - NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS = struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS._fields_ = [ - ('rbmModesList', ctypes.c_ubyte * 23), - ('rbmTotalModes', ctypes.c_ubyte), + ('rbmModesList', (NvU8 * 23)), + ('rbmTotalModes', NvU8), ] - NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS._fields_ = [ - ('rbmMode', ctypes.c_ubyte), + ('rbmMode', NvU8), ] - NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS._fields_ = [ - ('rbmMode', ctypes.c_ubyte), + ('rbmMode', NvU8), ] - NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), - ] - +class struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS(Struct): pass +struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS._fields_ = [ + ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO), +] NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS +enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY = CEnum(ctypes.c_uint32) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', 0) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', 1) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', 2) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', 3) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', 4) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', 5) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', 6) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', 7) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', 8) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', 9) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', 10) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', 11) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', 12) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', 13) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', 14) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', 15) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', 16) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', 17) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', 18) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', 19) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', 20) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', 21) -# values for enumeration 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY' -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY__enumvalues = { - 0: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', - 1: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', - 2: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', - 3: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', - 4: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', - 5: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', - 6: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', - 7: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', - 8: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', - 9: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', - 10: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', - 11: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', - 12: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', - 13: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', - 14: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', - 15: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', - 16: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', - 17: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', - 18: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', - 19: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', - 20: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', - 21: 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', -} -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = 0 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = 1 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = 2 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = 3 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = 4 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = 5 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = 6 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = 7 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = 8 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = 9 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = 10 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = 11 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = 12 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = 13 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = 14 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = 15 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = 16 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = 17 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21 -NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS._pack_ = 1 # source:False +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY +class struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('severity', NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY), + ('linkMask', NvU32), + ('severity', NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY), ] - NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS +enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE = CEnum(ctypes.c_uint32) +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', 0) +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', 1) +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', 2) +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', 3) +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', 4) -# values for enumeration 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE' -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE__enumvalues = { - 0: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', - 1: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', - 2: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', - 3: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', - 4: 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', -} -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = 0 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = 1 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = 2 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = 3 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = 4 -NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG(Structure): - pass - -struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG._pack_ = 1 # source:False +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE +class struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG(Struct): pass struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG._fields_ = [ - ('mode', NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE), - ('toggleActiveTime', ctypes.c_ubyte), - ('toggleInactiveTime', ctypes.c_ubyte), - ('bTrigger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), + ('mode', NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE), + ('toggleActiveTime', NvU8), + ('toggleInactiveTime', NvU8), + ('bTrigger', NvBool), ] - NV2080_CTRL_NVLINK_L1_FORCE_CONFIG = struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG -class struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('config', NV2080_CTRL_NVLINK_L1_FORCE_CONFIG), + ('linkMask', NvU32), + ('config', NV2080_CTRL_NVLINK_L1_FORCE_CONFIG), ] - NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS = struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS -class struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS(Struct): pass struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS._fields_ = [ - ('linkMask', ctypes.c_uint32), - ('config', struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG * 32), + ('linkMask', NvU32), + ('config', (NV2080_CTRL_NVLINK_L1_FORCE_CONFIG * 32)), ] - NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS -NV_SUBPROC_NAME_MAX_LENGTH = 100 # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_CMD = 1 : 0 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL = (0x00000001) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX = (0x00000002) # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_CUDA = 4 : 4 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES = (0x00000001) # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC = 5 : 5 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES = (0x00000001) # macro -# NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY = 6 : 6 # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT = (0x00000000) # macro -NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH = (0x00000001) # macro -NV2080_CTRL_PERF_BOOST_DURATION_MAX = 3600 # macro -NV2080_CTRL_PERF_BOOST_DURATION_INFINITE = 0xffffffff # macro -NV2080_CTRL_CMD_PERF_BOOST = (0x2080200a) # macro -NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW = (0x20802093) # macro -NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID = (0x93) # macro -NV2080_CTRL_PERF_POWER_SOURCE_AC = (0x00000000) # macro -NV2080_CTRL_PERF_POWER_SOURCE_BATTERY = (0x00000001) # macro -NV2080_CTRL_CMD_PERF_SET_POWERSTATE = (0x2080205b) # macro -NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5B) # macro -NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE = (0x20802092) # macro -NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x92) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P0 = (0x00000000) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P1 = (0x00000001) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P2 = (0x00000002) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P3 = (0x00000003) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_P4 = (0x00000004) # macro -NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT = (0x00000005) # macro -NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID = (0x6D) # macro -NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL = (0x2080206e) # macro -NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID = (0x6E) # macro -NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL = (0x2080206f) # macro -NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID = (0x6F) # macro -NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID = (0x83) # macro -NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL = 72 # macro -NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 = (0x20802096) # macro -NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID = (0x96) # macro -NV2080_CTRL_CMD_PERF_GPU_IS_IDLE = (0x20802089) # macro -NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID = (0x89) # macro -NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE = (0x00000001) # macro -NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE = (0x00000002) # macro -NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY = (0x2080208f) # macro -NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID = (0x8F) # macro -NV2080_CTRL_PERF_CLK_MAX_DOMAINS = 32 # macro -NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO = (0x20802002) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 = (0x2080200b) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID = (0xB) # macro -# NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE = 0 : 0 # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT = (0x00000000) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK = (0x00000001) # macro -# NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE = 2 : 1 # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE = (0x00000000) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP = (0x00000001) # macro -NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF = (0x00000002) # macro -NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE = (0x20802087) # macro -NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x87) # macro -NV2080_CTRL_CMD_PERF_GET_POWERSTATE = (0x2080205a) # macro -NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5A) # macro -NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT = (0x2080205d) # macro -NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID = (0x5D) # macro -NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK = (0x0000ffff) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START = (0x00000001) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP = (0x00000002) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START = (0x00000001) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP = (0x00000002) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START = (0x00000003) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP = (0x00000004) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START = (0x00000005) # macro -NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP = (0x00000006) # macro -NV2080_CTRL_PERF_VIDEOEVENT_OFA_START = (0x00000007) # macro -NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP = (0x00000008) # macro -NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE = (0x00010000) # macro -NV2080_CTRL_PERF_PSTATES_UNDEFINED = (0x00000000) # macro -NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED = (0x00000000) # macro -NV2080_CTRL_PERF_PSTATES_MIN = (0x00000001) # macro -NV2080_CTRL_PERF_PSTATES_P0 = (0x00000001) # macro -NV2080_CTRL_PERF_PSTATES_P1 = (0x00000002) # macro -NV2080_CTRL_PERF_PSTATES_P2 = (0x00000004) # macro -NV2080_CTRL_PERF_PSTATES_P3 = (0x00000008) # macro -NV2080_CTRL_PERF_PSTATES_P4 = (0x00000010) # macro -NV2080_CTRL_PERF_PSTATES_P5 = (0x00000020) # macro -NV2080_CTRL_PERF_PSTATES_P6 = (0x00000040) # macro -NV2080_CTRL_PERF_PSTATES_P7 = (0x00000080) # macro -NV2080_CTRL_PERF_PSTATES_P8 = (0x00000100) # macro -NV2080_CTRL_PERF_PSTATES_P9 = (0x00000200) # macro -NV2080_CTRL_PERF_PSTATES_P10 = (0x00000400) # macro -NV2080_CTRL_PERF_PSTATES_P11 = (0x00000800) # macro -NV2080_CTRL_PERF_PSTATES_P12 = (0x00001000) # macro -NV2080_CTRL_PERF_PSTATES_P13 = (0x00002000) # macro -NV2080_CTRL_PERF_PSTATES_P14 = (0x00004000) # macro -NV2080_CTRL_PERF_PSTATES_P15 = (0x00008000) # macro -NV2080_CTRL_PERF_PSTATES_MAX = (0x00008000) # macro -NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY = (0x10000) # macro -NV2080_CTRL_PERF_PSTATES_ALL = (0xffff) # macro -NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE = (0x20802068) # macro -NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID = (0x68) # macro -class struct_NV2080_CTRL_PERF_BOOST_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_BOOST_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_BOOST_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_BOOST_PARAMS._fields_ = [ - ('flags', ctypes.c_uint32), - ('duration', ctypes.c_uint32), + ('flags', NvU32), + ('duration', NvU32), ] - NV2080_CTRL_PERF_BOOST_PARAMS = struct_NV2080_CTRL_PERF_BOOST_PARAMS -class struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS._fields_ = [ - ('bAcquire', ctypes.c_ubyte), + ('bAcquire', NvBool), ] - NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS = struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS -class struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), + ('powerState', NvU32), ] - NV2080_CTRL_PERF_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS -class struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS), - ] - +class struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS(Struct): pass +struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS._fields_ = [ + ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS), +] NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS -class struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS._fields_ = [ - ('powerState', ctypes.c_uint32), + ('powerState', NvU32), ] - NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS = struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS +enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT = CEnum(ctypes.c_uint32) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', 0) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', 1) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', 2) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', 3) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', 4) +NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', 5) -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_CLIENT' -NV2080_CTRL_PERF_RATED_TDP_CLIENT__enumvalues = { - 0: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', - 1: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', - 2: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', - 3: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', - 4: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', - 5: 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', -} -NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = 0 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = 1 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = 2 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = 3 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = 4 -NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = 5 -NV2080_CTRL_PERF_RATED_TDP_CLIENT = ctypes.c_uint32 # enum +NV2080_CTRL_PERF_RATED_TDP_CLIENT = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT +enum_NV2080_CTRL_PERF_RATED_TDP_ACTION = CEnum(ctypes.c_uint32) +NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', 0) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', 1) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', 2) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', 3) +NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', 4) -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_ACTION' -NV2080_CTRL_PERF_RATED_TDP_ACTION__enumvalues = { - 0: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', - 1: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', - 2: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', - 3: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', - 4: 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', -} -NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = 0 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = 1 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = 2 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = 3 -NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4 -NV2080_CTRL_PERF_RATED_TDP_ACTION = ctypes.c_uint32 # enum - -# values for enumeration 'NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE' -NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE__enumvalues = { - 0: 'NV2080_CTRL_PERF_VPSTATE_RATED_TDP', - 1: 'NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', - 2: 'NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', -} -NV2080_CTRL_PERF_VPSTATE_RATED_TDP = 0 -NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = 1 -NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = 2 -NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('action', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), - ] +NV2080_CTRL_PERF_RATED_TDP_ACTION = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION +enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE = CEnum(ctypes.c_uint32) +NV2080_CTRL_PERF_VPSTATE_RATED_TDP = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_RATED_TDP', 0) +NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', 1) +NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', 2) +NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE +class struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST(Struct): pass +struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST._fields_ = [ + ('action', NV2080_CTRL_PERF_RATED_TDP_ACTION), + ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), +] NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST = struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST -class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm(Structure): - pass - -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS(Struct): pass +class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm(Struct): pass struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm._fields_ = [ - ('clientActiveMask', ctypes.c_uint32), - ('bRegkeyLimitRatedTdp', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('clientActiveMask', NvU32), + ('bRegkeyLimitRatedTdp', NvU8), ] - -struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS._fields_ = [ - ('rm', struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm), - ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('outputVPstate', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), - ('inputs', NV2080_CTRL_PERF_RATED_TDP_ACTION * 5), - ('vPstateTypes', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE * 5), + ('rm', struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm), + ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION), + ('outputVPstate', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), + ('inputs', (NV2080_CTRL_PERF_RATED_TDP_ACTION * 5)), + ('vPstateTypes', (NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE * 5)), ] - NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS -class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT), - ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION), - ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), - ] - +class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS(Struct): pass +struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS._fields_ = [ + ('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT), + ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION), + ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE), +] NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS -class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE(Structure): - pass - -struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE(Struct): pass struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE._fields_ = [ - ('util', ctypes.c_uint32), - ('vgpuScale', ctypes.c_uint32), - ('procId', ctypes.c_uint32), - ('subProcessID', ctypes.c_uint32), - ('subProcessName', ctypes.c_char * 100), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pOsPidInfo', ctypes.c_uint64), + ('util', NvU32), + ('vgpuScale', NvU32), + ('procId', NvU32), + ('subProcessID', NvU32), + ('subProcessName', (ctypes.c_char * 100)), + ('pOsPidInfo', NvU64), ] - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE = struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE -class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('base', NV2080_CTRL_GPUMON_SAMPLE), - ('fb', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('gr', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvenc', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvdec', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvjpg', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ('nvofa', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), - ] - +class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE(Struct): pass +struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE._fields_ = [ + ('base', NV2080_CTRL_GPUMON_SAMPLE), + ('fb', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), + ('gr', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), + ('nvenc', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), + ('nvdec', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), + ('nvjpg', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), + ('nvofa', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE), +] NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE = struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE -NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE = ctypes.sizeof ( NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE ) * 72 # macro (from list) NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM = struct_NV2080_CTRL_GPUMON_SAMPLES -class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS._fields_ = [ - ('type', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('bufSize', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('tracker', ctypes.c_uint32), - ('samples', struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE * 72), + ('type', NvU8), + ('bufSize', NvU32), + ('count', NvU32), + ('tracker', NvU32), + ('samples', (NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE * 72)), ] - NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS = struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS -class struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS._fields_ = [ - ('prevPstate', ctypes.c_uint32), - ('action', ctypes.c_uint32), + ('prevPstate', NvU32), + ('action', NvU32), ] - NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS = struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS -class struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS._fields_ = [ - ('bGpuIsIdle', ctypes.c_ubyte), - ('bRestoreToMax', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('idleTimeUs', ctypes.c_uint64), - ('busyTimeUs', ctypes.c_uint64), + ('bGpuIsIdle', NvBool), + ('bRestoreToMax', NvBool), + ('idleTimeUs', NvU64), + ('busyTimeUs', NvU64), ] - NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS = struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS -class struct_NV2080_CTRL_PERF_GET_CLK_INFO(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_CLK_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GET_CLK_INFO(Struct): pass struct_NV2080_CTRL_PERF_GET_CLK_INFO._fields_ = [ - ('flags', ctypes.c_uint32), - ('domain', ctypes.c_uint32), - ('currentFreq', ctypes.c_uint32), - ('defaultFreq', ctypes.c_uint32), - ('minFreq', ctypes.c_uint32), - ('maxFreq', ctypes.c_uint32), + ('flags', NvU32), + ('domain', NvU32), + ('currentFreq', NvU32), + ('defaultFreq', NvU32), + ('minFreq', NvU32), + ('maxFreq', NvU32), ] - NV2080_CTRL_PERF_GET_CLK_INFO = struct_NV2080_CTRL_PERF_GET_CLK_INFO -class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS._fields_ = [ - ('level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('perfGetClkInfoList', ctypes.POINTER(None)), - ('perfGetClkInfoListSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('level', NvU32), + ('flags', NvU32), + ('perfGetClkInfoList', NvP64), + ('perfGetClkInfoListSize', NvU32), ] - NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS -class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS._fields_ = [ - ('level', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('perfGetClkInfoList', struct_NV2080_CTRL_PERF_GET_CLK_INFO * 32), - ('perfGetClkInfoListSize', ctypes.c_uint32), + ('level', NvU32), + ('flags', NvU32), + ('perfGetClkInfoList', (NV2080_CTRL_PERF_GET_CLK_INFO * 32)), + ('perfGetClkInfoListSize', NvU32), ] - NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS +enum_NV2080_CTRL_CMD_PERF_VID_ENG = CEnum(ctypes.c_uint32) +NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', 1) +NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', 2) +NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', 3) +NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', 4) -# values for enumeration 'NV2080_CTRL_CMD_PERF_VID_ENG' -NV2080_CTRL_CMD_PERF_VID_ENG__enumvalues = { - 1: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', - 2: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', - 3: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', - 4: 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', -} -NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1 -NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2 -NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3 -NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4 -NV2080_CTRL_CMD_PERF_VID_ENG = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS._pack_ = 1 # source:False +NV2080_CTRL_CMD_PERF_VID_ENG = enum_NV2080_CTRL_CMD_PERF_VID_ENG +class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS._fields_ = [ - ('engineType', NV2080_CTRL_CMD_PERF_VID_ENG), - ('clkPercentBusy', ctypes.c_uint32), - ('samplingPeriodUs', ctypes.c_uint32), + ('engineType', NV2080_CTRL_CMD_PERF_VID_ENG), + ('clkPercentBusy', NvU32), + ('samplingPeriodUs', NvU32), ] - NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS = struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS -class struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS), - ] - -NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS -class struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS._pack_ = 1 # source:False -struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS._fields_ = [ - ('videoEvent', ctypes.c_uint32), +class struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS(Struct): pass +struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS._fields_ = [ + ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS), +] +NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS +class struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS(Struct): pass +struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS._fields_ = [ + ('videoEvent', NvU32), ] - NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS = struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS NV2080_CTRL_PERF_PSTATES_ID = ctypes.c_uint32 -class struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS(Struct): pass struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS._fields_ = [ - ('currPstate', ctypes.c_uint32), + ('currPstate', NvU32), ] - NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS -NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED = 0 # macro -NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED = 1 # macro -NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE = 2 # macro -NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO = (0x20802609) # macro -class struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS._fields_ = [ - ('moduleId', ctypes.c_uint32), - ('nvswitchSupport', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('moduleId', NvU32), + ('nvswitchSupport', NvU8), ] - NV2080_CTRL_PMGR_MODULE_INFO_PARAMS = struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS -NV2080_CTRL_CMD_GC6_ENTRY = (0x2080270d) # macro -NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_GC6_EXIT = (0x2080270e) # macro -NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID = (0xE) # macro +enum_NV2080_CTRL_GC6_FLAVOR_ID = CEnum(ctypes.c_uint32) +NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', 0) +NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', 1) +NV2080_CTRL_GC6_FLAVOR_ID_MAX = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_MAX', 4) -# values for enumeration 'NV2080_CTRL_GC6_FLAVOR_ID' -NV2080_CTRL_GC6_FLAVOR_ID__enumvalues = { - 0: 'NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', - 1: 'NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', - 4: 'NV2080_CTRL_GC6_FLAVOR_ID_MAX', -} -NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0 -NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1 -NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4 -NV2080_CTRL_GC6_FLAVOR_ID = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GC6_ENTRY_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params(Structure): - pass - -struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params._pack_ = 1 # source:False +NV2080_CTRL_GC6_FLAVOR_ID = enum_NV2080_CTRL_GC6_FLAVOR_ID +class struct_NV2080_CTRL_GC6_ENTRY_PARAMS(Struct): pass +class struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params(Struct): pass struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params._fields_ = [ - ('bIsRTD3Transition', ctypes.c_ubyte), - ('bIsRTD3CoreRailPowerCut', ctypes.c_ubyte), - ('bSkipPstateSanity', ctypes.c_ubyte), + ('bIsRTD3Transition', NvBool), + ('bIsRTD3CoreRailPowerCut', NvBool), + ('bSkipPstateSanity', NvBool), ] - -struct_NV2080_CTRL_GC6_ENTRY_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_GC6_ENTRY_PARAMS._fields_ = [ - ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), - ('stepMask', ctypes.c_uint32), - ('params', struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params), - ('PADDING_0', ctypes.c_ubyte), + ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), + ('stepMask', NvU32), + ('params', struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params), ] - NV2080_CTRL_GC6_ENTRY_PARAMS = struct_NV2080_CTRL_GC6_ENTRY_PARAMS -class struct_NV2080_CTRL_GC6_EXIT_PARAMS(Structure): - pass - -class struct_NV2080_CTRL_GC6_EXIT_PARAMS_params(Structure): - pass - -struct_NV2080_CTRL_GC6_EXIT_PARAMS_params._pack_ = 1 # source:False +class struct_NV2080_CTRL_GC6_EXIT_PARAMS(Struct): pass +class struct_NV2080_CTRL_GC6_EXIT_PARAMS_params(Struct): pass struct_NV2080_CTRL_GC6_EXIT_PARAMS_params._fields_ = [ - ('bIsGpuSelfWake', ctypes.c_ubyte), - ('bIsRTD3Transition', ctypes.c_ubyte), - ('bIsRTD3HotTransition', ctypes.c_ubyte), + ('bIsGpuSelfWake', NvBool), + ('bIsRTD3Transition', NvBool), + ('bIsRTD3HotTransition', NvBool), ] - -struct_NV2080_CTRL_GC6_EXIT_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_GC6_EXIT_PARAMS._fields_ = [ - ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), - ('params', struct_NV2080_CTRL_GC6_EXIT_PARAMS_params), - ('PADDING_0', ctypes.c_ubyte), + ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), + ('params', struct_NV2080_CTRL_GC6_EXIT_PARAMS_params), ] - NV2080_CTRL_GC6_EXIT_PARAMS = struct_NV2080_CTRL_GC6_EXIT_PARAMS +enum_NV2080_CTRL_GC6_STEP_ID = CEnum(ctypes.c_uint32) +NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', 0) +NV2080_CTRL_GC6_STEP_ID_GPU_OFF = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_GPU_OFF', 1) +NV2080_CTRL_GC6_STEP_ID_MAX = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_MAX', 2) -# values for enumeration 'NV2080_CTRL_GC6_STEP_ID' -NV2080_CTRL_GC6_STEP_ID__enumvalues = { - 0: 'NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', - 1: 'NV2080_CTRL_GC6_STEP_ID_GPU_OFF', - 2: 'NV2080_CTRL_GC6_STEP_ID_MAX', -} -NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0 -NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1 -NV2080_CTRL_GC6_STEP_ID_MAX = 2 -NV2080_CTRL_GC6_STEP_ID = ctypes.c_uint32 # enum -class struct_NV2080_CTRL_GC6_FLAVOR_INFO(Structure): - pass - -struct_NV2080_CTRL_GC6_FLAVOR_INFO._pack_ = 1 # source:False +NV2080_CTRL_GC6_STEP_ID = enum_NV2080_CTRL_GC6_STEP_ID +class struct_NV2080_CTRL_GC6_FLAVOR_INFO(Struct): pass struct_NV2080_CTRL_GC6_FLAVOR_INFO._fields_ = [ - ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), - ('stepMask', ctypes.c_uint32), + ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID), + ('stepMask', NvU32), ] - NV2080_CTRL_GC6_FLAVOR_INFO = struct_NV2080_CTRL_GC6_FLAVOR_INFO -NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM = (0x20802204) # macro -NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CMD_RC_GET_ERROR_COUNT = (0x20802205) # macro -NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE = (0x2000) # macro -NV2080_CTRL_CMD_RC_GET_ERROR = (0x20802206) # macro -NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID = (0x13) # macro -NV2080_CTRL_CMD_RC_GET_ERROR_V2 = (0x20802213) # macro -NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY = (0x20802207) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = (0x20802209) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE = (0x00000000) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED = (0x00000001) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING = (0x00000002) # macro -NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED = (0x00000004) # macro -NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG = (0x2080220a) # macro -NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG = (0x2080220b) # macro -NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = (0x2080220c) # macro -NV2080_CTRL_CMD_SET_RC_RECOVERY = (0x2080220d) # macro -NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_GET_RC_RECOVERY = (0x2080220e) # macro -NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xE) # macro -NV2080_CTRL_CMD_RC_RECOVERY_DISABLED = (0x00000000) # macro -NV2080_CTRL_CMD_RC_RECOVERY_ENABLED = (0x00000001) # macro -NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE = (0x2080220f) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID = (0xF) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN = (0x00000000) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END = (0x00000001) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS = (0x00000000) # macro -NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL = (0x00000001) # macro -NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = (0x20802210) # macro -NV2080_CTRL_CMD_SET_RC_INFO = (0x20802211) # macro -NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID = (0x11) # macro -NV2080_CTRL_CMD_GET_RC_INFO = (0x20802212) # macro -NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID = (0x12) # macro -NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE = (0x00000000) # macro -NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE = (0x00000001) # macro -NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE = (0x00000000) # macro -NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE = (0x00000001) # macro -class struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(Struct): pass struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('virtAddress', ctypes.c_uint64), - ('bufferPtr', ctypes.POINTER(None)), - ('bufferSize', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), + ('hChannel', NvHandle), + ('virtAddress', NvU64), + ('bufferPtr', NvP64), + ('bufferSize', NvU32), ] - NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS = struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS -class struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS(Struct): pass struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS._fields_ = [ - ('errorCount', ctypes.c_uint32), + ('errorCount', NvU32), ] - NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS = struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS -class struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS(Struct): pass struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS._fields_ = [ - ('whichBuffer', ctypes.c_uint32), - ('outputRecordSize', ctypes.c_uint32), - ('recordBuffer', ctypes.c_ubyte * 8192), + ('whichBuffer', NvU32), + ('outputRecordSize', NvU32), + ('recordBuffer', (NvU8 * 8192)), ] - NV2080_CTRL_RC_GET_ERROR_V2_PARAMS = struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS -class struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS._fields_ = [ - ('watchdogStatusFlags', ctypes.c_uint32), + ('watchdogStatusFlags', NvU32), ] - NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS = struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS -class struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS._fields_ = [ - ('rcEnable', ctypes.c_uint32), + ('rcEnable', NvU32), ] - NV2080_CTRL_CMD_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS -class struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS(Struct): pass struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS._fields_ = [ - ('cmd', ctypes.c_uint32), - ('status', ctypes.c_int32), + ('cmd', NvU32), + ('status', NvS32), ] - NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS = struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS -class struct_NV2080_CTRL_CMD_RC_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_RC_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_RC_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_RC_INFO_PARAMS._fields_ = [ - ('rcMode', ctypes.c_uint32), - ('rcBreak', ctypes.c_uint32), + ('rcMode', NvU32), + ('rcBreak', NvU32), ] - NV2080_CTRL_CMD_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS -RM_GSP_SPDM_CMD_ID_CC_INIT = (0x1) # macro -RM_GSP_SPDM_CMD_ID_CC_DEINIT = (0x2) # macro -RM_GSP_SPDM_CMD_ID_CC_CTRL = (0x3) # macro -RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA = (0x4) # macro -RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL = (0x5) # macro -RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST = (0x6) # macro -RM_GSP_SPDM_CMD_ID_INVALID_COMMAND = (0xFF) # macro -SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE = 0x2400 # macro -RSVD7_SIZE = 16 # macro -RSVD8_SIZE = 2 # macro -CE_FIPS_SELF_TEST_DATA_SIZE = 16 # macro -CE_FIPS_SELF_TEST_AUTH_TAG_SIZE = 16 # macro -CE_FIPS_SELF_TEST_IV_SIZE = 12 # macro -RM_GSP_SPDM_MSG_ID_CC_INIT = (0x1) # macro -RM_GSP_SPDM_MSG_ID_CC_DEINIT = (0x2) # macro -RM_GSP_SPDM_MSG_ID_CC_CTRL = (0x3) # macro -RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA = (0x4) # macro -RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL = (0x5) # macro -RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST = (0x6) # macro -RM_GSP_SPDM_MSG_ID_INVALID_COMMAND = (0xFF) # macro -NV2080_CTRL_INTERNAL_SPDM_PARTITION = (0x20800ad9) # macro -NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID = (0xD9) # macro -NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT = (0x20800ada) # macro -NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID = (0xDA) # macro -class struct_RM_GSP_SPDM_CMD_CC_INIT(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_INIT._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_CMD_CC_INIT(Struct): pass struct_RM_GSP_SPDM_CMD_CC_INIT._fields_ = [ - ('cmdType', ctypes.c_ubyte), + ('cmdType', NvU8), ] - RM_GSP_SPDM_CMD_CC_INIT = struct_RM_GSP_SPDM_CMD_CC_INIT PRM_GSP_SPDM_CMD_CC_INIT = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_INIT) -class struct_RM_GSP_SPDM_CMD_CC_DEINIT(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_DEINIT._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_CMD_CC_DEINIT(Struct): pass struct_RM_GSP_SPDM_CMD_CC_DEINIT._fields_ = [ - ('cmdType', ctypes.c_ubyte), + ('cmdType', NvU8), ] - RM_GSP_SPDM_CMD_CC_DEINIT = struct_RM_GSP_SPDM_CMD_CC_DEINIT PRM_GSP_SPDM_CMD_CC_DEINIT = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_DEINIT) -class struct_RM_GSP_SPDM_CMD_CC_CTRL(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_CTRL._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_CMD_CC_CTRL(Struct): pass struct_RM_GSP_SPDM_CMD_CC_CTRL._fields_ = [ - ('cmdType', ctypes.c_ubyte), + ('cmdType', NvU8), ] - RM_GSP_SPDM_CMD_CC_CTRL = struct_RM_GSP_SPDM_CMD_CC_CTRL PRM_GSP_SPDM_CMD_CC_CTRL = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_CTRL) -class struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA(Struct): pass struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('rsvd0', ctypes.c_uint32 * 2), - ('rsvd1', ctypes.c_uint32), - ('rsvd2', ctypes.c_char * 9), - ('rsvd3', ctypes.c_char * 5), - ('rsvd4', ctypes.c_char * 5), - ('rsvd5', ctypes.c_char * 5), - ('rsvd6', ctypes.c_char * 2), - ('rsvd7', ctypes.c_char * 16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('rsvd8', ctypes.c_uint32 * 2), + ('cmdType', NvU8), + ('rsvd0', (NvU32 * 2)), + ('rsvd1', NvU32), + ('rsvd2', (ctypes.c_char * 9)), + ('rsvd3', (ctypes.c_char * 5)), + ('rsvd4', (ctypes.c_char * 5)), + ('rsvd5', (ctypes.c_char * 5)), + ('rsvd6', (ctypes.c_char * 2)), + ('rsvd7', (ctypes.c_char * 16)), + ('rsvd8', (NvU32 * 2)), ] - RM_GSP_SPDM_CMD_CC_INIT_RM_DATA = struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA) -class struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL(Structure): - pass - -struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL(Struct): pass struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('bEnable', ctypes.c_ubyte), + ('cmdType', NvU8), + ('bEnable', NvBool), ] - RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL = struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL) -class struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST(Structure): - pass - -class struct_CC_KMB(Structure): - pass - -class struct_CC_AES_CRYPTOBUNDLE(Structure): - pass - -struct_CC_AES_CRYPTOBUNDLE._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST(Struct): pass +class struct_CC_KMB(Struct): pass +CC_KMB = struct_CC_KMB +class struct_CC_AES_CRYPTOBUNDLE(Struct): pass +CC_AES_CRYPTOBUNDLE = struct_CC_AES_CRYPTOBUNDLE struct_CC_AES_CRYPTOBUNDLE._fields_ = [ - ('iv', ctypes.c_uint32 * 3), - ('key', ctypes.c_uint32 * 8), - ('ivMask', ctypes.c_uint32 * 3), + ('iv', (NvU32 * 3)), + ('key', (NvU32 * 8)), + ('ivMask', (NvU32 * 3)), ] - -class union_CC_KMB_0(Union): - pass - -class struct_CC_HMAC_CRYPTOBUNDLE(Structure): - pass - -struct_CC_HMAC_CRYPTOBUNDLE._pack_ = 1 # source:False +class struct_CC_KMB_0(ctypes.Union): pass +class struct_CC_HMAC_CRYPTOBUNDLE(Struct): pass +CC_HMAC_CRYPTOBUNDLE = struct_CC_HMAC_CRYPTOBUNDLE struct_CC_HMAC_CRYPTOBUNDLE._fields_ = [ - ('nonce', ctypes.c_uint32 * 8), - ('key', ctypes.c_uint32 * 8), + ('nonce', (NvU32 * 8)), + ('key', (NvU32 * 8)), ] - -union_CC_KMB_0._pack_ = 1 # source:False -union_CC_KMB_0._fields_ = [ - ('hmacBundle', struct_CC_HMAC_CRYPTOBUNDLE), - ('decryptBundle', struct_CC_AES_CRYPTOBUNDLE), - ('PADDING_0', ctypes.c_ubyte * 8), +struct_CC_KMB_0._fields_ = [ + ('hmacBundle', CC_HMAC_CRYPTOBUNDLE), + ('decryptBundle', CC_AES_CRYPTOBUNDLE), ] - -struct_CC_KMB._pack_ = 1 # source:False -struct_CC_KMB._anonymous_ = ('_0',) +struct_CC_KMB._anonymous_ = ['_0'] struct_CC_KMB._fields_ = [ - ('encryptBundle', struct_CC_AES_CRYPTOBUNDLE), - ('_0', union_CC_KMB_0), - ('bIsWorkLaunch', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('encryptBundle', CC_AES_CRYPTOBUNDLE), + ('_0', struct_CC_KMB_0), + ('bIsWorkLaunch', NvBool), ] - -struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST._pack_ = 1 # source:False struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('isEnc', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('kmb', struct_CC_KMB), - ('text', ctypes.c_ubyte * 16), - ('authTag', ctypes.c_ubyte * 16), + ('cmdType', NvU8), + ('isEnc', NvU8), + ('kmb', CC_KMB), + ('text', (NvU8 * 16)), + ('authTag', (NvU8 * 16)), ] - RM_GSP_SPDM_CMD_FIPS_SELFTEST = struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST PRM_GSP_SPDM_CMD_FIPS_SELFTEST = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST) -class union_RM_GSP_SPDM_CMD(Union): - pass - -union_RM_GSP_SPDM_CMD._pack_ = 1 # source:False +class union_RM_GSP_SPDM_CMD(ctypes.Union): pass union_RM_GSP_SPDM_CMD._fields_ = [ - ('cmdType', ctypes.c_ubyte), - ('ccInit', RM_GSP_SPDM_CMD_CC_INIT), - ('ccDeinit', RM_GSP_SPDM_CMD_CC_DEINIT), - ('ccCtrl', RM_GSP_SPDM_CMD_CC_CTRL), - ('rmDataInitCmd', RM_GSP_SPDM_CMD_CC_INIT_RM_DATA), - ('ccHeartbeatCtrl', RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL), - ('ccFipsTest', RM_GSP_SPDM_CMD_FIPS_SELFTEST), + ('cmdType', NvU8), + ('ccInit', RM_GSP_SPDM_CMD_CC_INIT), + ('ccDeinit', RM_GSP_SPDM_CMD_CC_DEINIT), + ('ccCtrl', RM_GSP_SPDM_CMD_CC_CTRL), + ('rmDataInitCmd', RM_GSP_SPDM_CMD_CC_INIT_RM_DATA), + ('ccHeartbeatCtrl', RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL), + ('ccFipsTest', RM_GSP_SPDM_CMD_FIPS_SELFTEST), ] - RM_GSP_SPDM_CMD = union_RM_GSP_SPDM_CMD PRM_GSP_SPDM_CMD = ctypes.POINTER(union_RM_GSP_SPDM_CMD) -class struct_RM_GSP_SPDM_MSG(Structure): - pass - -struct_RM_GSP_SPDM_MSG._pack_ = 1 # source:False +class struct_RM_GSP_SPDM_MSG(Struct): pass struct_RM_GSP_SPDM_MSG._fields_ = [ - ('msgType', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('status', ctypes.c_uint32), - ('rsvd1', ctypes.c_uint32), - ('rsvd2', ctypes.c_uint32), - ('rsvd3', ctypes.c_uint32), - ('rsvd4', ctypes.c_uint32), - ('rsvd5', ctypes.c_uint32), + ('msgType', NvU8), + ('status', NvU32), + ('rsvd1', NvU32), + ('rsvd2', NvU32), + ('rsvd3', NvU32), + ('rsvd4', NvU32), + ('rsvd5', NvU32), ] - RM_GSP_SPDM_MSG = struct_RM_GSP_SPDM_MSG PRM_GSP_SPDM_MSG = ctypes.POINTER(struct_RM_GSP_SPDM_MSG) -class struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS._fields_ = [ - ('index', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('cmd', RM_GSP_SPDM_CMD), - ('msg', RM_GSP_SPDM_MSG), + ('index', NvU8), + ('cmd', RM_GSP_SPDM_CMD), + ('msg', RM_GSP_SPDM_MSG), ] - NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS = struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS -class struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS(Struct): pass struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS._fields_ = [ - ('transcript', ctypes.c_ubyte * 9216), - ('transcriptSize', ctypes.c_uint32), + ('transcript', (NvU8 * 9216)), + ('transcriptSize', NvU32), ] - NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS = struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS -NV2080_CTRL_CMD_TIMER_SCHEDULE = (0x20800401) # macro -NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # macro -# NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME = 0 : 0 # macro -NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS = (0x00000000) # macro -NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL = (0x00000001) # macro -NV2080_CTRL_CMD_TIMER_CANCEL = (0x20800402) # macro -NV2080_CTRL_CMD_TIMER_GET_TIME = (0x20800403) # macro -NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET = (0x20800404) # macro -NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = (0x20800406) # macro -NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES = 16 # macro -NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -# NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_SOURCE = 3 : 0 # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME = (0x00000001) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC = (0x00000002) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API = (0x00000003) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS = (0x00000004) # macro -# NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR = 7 : 4 # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU = (0x00000000) # macro -NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP = (0x00000001) # macro -NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = (0x20800407) # macro -NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID = (0x7) # macro -class struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS._fields_ = [ - ('time_nsec', ctypes.c_uint64), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('time_nsec', NvU64), + ('flags', NvU32), ] - NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS = struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS -class struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS(Struct): pass struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS._fields_ = [ - ('time_nsec', ctypes.c_uint64), + ('time_nsec', NvU64), ] - NV2080_CTRL_TIMER_GET_TIME_PARAMS = struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS -class struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS(Struct): pass struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS._fields_ = [ - ('tmr_offset', ctypes.c_uint32), + ('tmr_offset', NvU32), ] - NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS = struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS -class struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE(Structure): - pass - -struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE._pack_ = 1 # source:False +class struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE(Struct): pass struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE._fields_ = [ - ('cpuTime', ctypes.c_uint64), - ('gpuTime', ctypes.c_uint64), + ('cpuTime', NvU64), + ('gpuTime', NvU64), ] - NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE = struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE -class struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS._fields_ = [ - ('cpuClkId', ctypes.c_ubyte), - ('sampleCount', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('samples', struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE * 16), + ('cpuClkId', NvU8), + ('sampleCount', NvU8), + ('samples', (NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE * 16)), ] - NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS = struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS -class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS(Structure): - pass - -struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS(Struct): pass struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS._fields_ = [ - ('bSetMaxFreq', ctypes.c_ubyte), + ('bSetMaxFreq', NvBool), ] - NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS = struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS -NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT = (0x20803d01) # macro -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC = (0x00000001) # macro -NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC = (0x00000002) # macro -NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF = (0x20803d02) # macro -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW = (0x00000001) # macro -NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW = (0x00000002) # macro -NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER = (0x20803d03) # macro -NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS = (0x20803d04) # macro -NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER = (0x20803d05) # macro -NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER = (0x20803d06) # macro -NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS = (0x20803d07) # macro -NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS = (0x20803d08) # macro -NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID = (0x8) # macro -class struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS(Struct): pass struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), + ('action', NvU32), ] - NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS = struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS -class struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS(Struct): pass struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), + ('action', NvU32), ] - NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS = struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS -class struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS(Struct): pass struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS._fields_ = [ - ('bEnter', ctypes.c_ubyte), + ('bEnter', NvBool), ] - NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS = struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS -class struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS(Struct): pass struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS._fields_ = [ - ('hNotifierResource', ctypes.c_uint32), - ('notifyDataSize', ctypes.c_uint32), - ('hNotifyDataMemory', ctypes.c_uint32), - ('perfmonIdCount', ctypes.c_uint32), - ('snapshotBufferSize', ctypes.c_uint32), - ('hSnapshotMemory', ctypes.c_uint32), + ('hNotifierResource', NvHandle), + ('notifyDataSize', NvU32), + ('hNotifyDataMemory', NvHandle), + ('perfmonIdCount', NvU32), + ('snapshotBufferSize', NvU32), + ('hSnapshotMemory', NvHandle), ] - NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS = struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS -class struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS._fields_ = [ - ('bVidmemPersistent', ctypes.c_ubyte), + ('bVidmemPersistent', NvBool), ] - NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS = struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS -class struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS._fields_ = [ - ('bUpdateTGP', ctypes.c_ubyte), + ('bUpdateTGP', NvBool), ] - NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS = struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK = (0x20804001) # macro -NV2080_CTRL_MAX_VMMU_SEGMENTS = 384 # macro -NV2080_GPU_MAX_ENGINES = 0x54 # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x1) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK = (0x20804002) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x2) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE = (0x20804003) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID = (0x3) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU = (0x20804004) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID = (0x4) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO = (0x20804005) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID = (0x5) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE = (0x20804006) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID = (0x6) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY = (0x20804007) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x7) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP = (0x20804008) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID = (0x8) # macro -NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN = 8 # macro -NV2080_CTRL_MAX_GPC_COUNT = 32 # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING = (0x20804009) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID = (0x9) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT = (0x2080400a) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID = (0xA) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG = (0x2080400b) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID = (0xB) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES = (0x2080400c) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID = (0xC) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS = (0x2080400d) # macro -NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID = (0xD) # macro -NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE = (0x2080400e) # macro -NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0xE) # macro -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS._fields_ = [ - ('dbdf', ctypes.c_uint32), - ('gfid', ctypes.c_uint32), - ('vgpuType', ctypes.c_uint32), - ('vmPid', ctypes.c_uint32), - ('swizzId', ctypes.c_uint32), - ('numChannels', ctypes.c_uint32), - ('numPluginChannels', ctypes.c_uint32), - ('chidOffset', ctypes.c_uint32 * 84), - ('bDisableDefaultSmcExecPartRestore', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('numGuestFbSegments', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('guestFbPhysAddrList', ctypes.c_uint64 * 384), - ('guestFbLengthList', ctypes.c_uint64 * 384), - ('pluginHeapMemoryPhysAddr', ctypes.c_uint64), - ('pluginHeapMemoryLength', ctypes.c_uint64), - ('ctrlBuffOffset', ctypes.c_uint64), - ('initTaskLogBuffOffset', ctypes.c_uint64), - ('initTaskLogBuffSize', ctypes.c_uint64), - ('vgpuTaskLogBuffOffset', ctypes.c_uint64), - ('vgpuTaskLogBuffSize', ctypes.c_uint64), - ('kernelLogBuffOffset', ctypes.c_uint64), - ('kernelLogBuffSize', ctypes.c_uint64), - ('migRmHeapMemoryPhysAddr', ctypes.c_uint64), - ('migRmHeapMemoryLength', ctypes.c_uint64), - ('bDeviceProfilingEnabled', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), + ('dbdf', NvU32), + ('gfid', NvU32), + ('vgpuType', NvU32), + ('vmPid', NvU32), + ('swizzId', NvU32), + ('numChannels', NvU32), + ('numPluginChannels', NvU32), + ('chidOffset', (NvU32 * 84)), + ('bDisableDefaultSmcExecPartRestore', NvBool), + ('numGuestFbSegments', NvU32), + ('guestFbPhysAddrList', (NvU64 * 384)), + ('guestFbLengthList', (NvU64 * 384)), + ('pluginHeapMemoryPhysAddr', NvU64), + ('pluginHeapMemoryLength', NvU64), + ('ctrlBuffOffset', NvU64), + ('initTaskLogBuffOffset', NvU64), + ('initTaskLogBuffSize', NvU64), + ('vgpuTaskLogBuffOffset', NvU64), + ('vgpuTaskLogBuffSize', NvU64), + ('kernelLogBuffOffset', NvU64), + ('kernelLogBuffSize', NvU64), + ('migRmHeapMemoryPhysAddr', NvU64), + ('migRmHeapMemoryLength', NvU64), + ('bDeviceProfilingEnabled', NvBool), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), + ('gfid', NvU32), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS(Structure): - pass - -class struct_NVA081_CTRL_VGPU_INFO(Structure): - pass - -struct_NVA081_CTRL_VGPU_INFO._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS(Struct): pass +class struct_NVA081_CTRL_VGPU_INFO(Struct): pass +NVA081_CTRL_VGPU_INFO = struct_NVA081_CTRL_VGPU_INFO struct_NVA081_CTRL_VGPU_INFO._fields_ = [ - ('vgpuType', ctypes.c_uint32), - ('vgpuName', ctypes.c_ubyte * 32), - ('vgpuClass', ctypes.c_ubyte * 32), - ('vgpuSignature', ctypes.c_ubyte * 128), - ('license', ctypes.c_ubyte * 128), - ('maxInstance', ctypes.c_uint32), - ('numHeads', ctypes.c_uint32), - ('maxResolutionX', ctypes.c_uint32), - ('maxResolutionY', ctypes.c_uint32), - ('maxPixels', ctypes.c_uint32), - ('frlConfig', ctypes.c_uint32), - ('cudaEnabled', ctypes.c_uint32), - ('eccSupported', ctypes.c_uint32), - ('gpuInstanceSize', ctypes.c_uint32), - ('multiVgpuSupported', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vdevId', ctypes.c_uint64), - ('pdevId', ctypes.c_uint64), - ('profileSize', ctypes.c_uint64), - ('fbLength', ctypes.c_uint64), - ('gspHeapSize', ctypes.c_uint64), - ('fbReservation', ctypes.c_uint64), - ('mappableVideoSize', ctypes.c_uint64), - ('encoderCapacity', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('bar1Length', ctypes.c_uint64), - ('frlEnable', ctypes.c_uint32), - ('adapterName', ctypes.c_ubyte * 64), - ('adapterName_Unicode', ctypes.c_uint16 * 64), - ('shortGpuNameString', ctypes.c_ubyte * 64), - ('licensedProductName', ctypes.c_ubyte * 128), - ('vgpuExtraParams', ctypes.c_uint32 * 1024), - ('ftraceEnable', ctypes.c_uint32), - ('gpuDirectSupported', ctypes.c_uint32), - ('nvlinkP2PSupported', ctypes.c_uint32), - ('multiVgpuExclusive', ctypes.c_uint32), - ('exclusiveType', ctypes.c_uint32), - ('exclusiveSize', ctypes.c_uint32), - ('gpuInstanceProfileId', ctypes.c_uint32), - ('placementSize', ctypes.c_uint32), - ('homogeneousPlacementCount', ctypes.c_uint32), - ('homogeneousPlacementIds', ctypes.c_uint32 * 32), - ('heterogeneousPlacementCount', ctypes.c_uint32), - ('heterogeneousPlacementIds', ctypes.c_uint32 * 32), - ('PADDING_2', ctypes.c_ubyte * 4), + ('vgpuType', NvU32), + ('vgpuName', (NvU8 * 32)), + ('vgpuClass', (NvU8 * 32)), + ('vgpuSignature', (NvU8 * 128)), + ('license', (NvU8 * 128)), + ('maxInstance', NvU32), + ('numHeads', NvU32), + ('maxResolutionX', NvU32), + ('maxResolutionY', NvU32), + ('maxPixels', NvU32), + ('frlConfig', NvU32), + ('cudaEnabled', NvU32), + ('eccSupported', NvU32), + ('gpuInstanceSize', NvU32), + ('multiVgpuSupported', NvU32), + ('vdevId', NvU64), + ('pdevId', NvU64), + ('profileSize', NvU64), + ('fbLength', NvU64), + ('gspHeapSize', NvU64), + ('fbReservation', NvU64), + ('mappableVideoSize', NvU64), + ('encoderCapacity', NvU32), + ('bar1Length', NvU64), + ('frlEnable', NvU32), + ('adapterName', (NvU8 * 64)), + ('adapterName_Unicode', (NvU16 * 64)), + ('shortGpuNameString', (NvU8 * 64)), + ('licensedProductName', (NvU8 * 128)), + ('vgpuExtraParams', (NvU32 * 1024)), + ('ftraceEnable', NvU32), + ('gpuDirectSupported', NvU32), + ('nvlinkP2PSupported', NvU32), + ('multiVgpuExclusive', NvU32), + ('exclusiveType', NvU32), + ('exclusiveSize', NvU32), + ('gpuInstanceProfileId', NvU32), + ('placementSize', NvU32), + ('homogeneousPlacementCount', NvU32), + ('homogeneousPlacementIds', (NvU32 * 32)), + ('heterogeneousPlacementCount', NvU32), + ('heterogeneousPlacementIds', (NvU32 * 32)), ] - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS._pack_ = 1 # source:False struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS._fields_ = [ - ('discardVgpuTypes', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('vgpuInfoCount', ctypes.c_uint32), - ('vgpuInfo', struct_NVA081_CTRL_VGPU_INFO * 64), + ('discardVgpuTypes', NvBool), + ('vgpuInfoCount', NvU32), + ('vgpuInfo', (NVA081_CTRL_VGPU_INFO * 64)), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS -class struct_NV2080_GUEST_VM_INFO(Structure): - pass +class struct_NV2080_GUEST_VM_INFO(Struct): pass +enum_GUEST_VM_INFO_STATE = CEnum(ctypes.c_uint32) +GUEST_VM_INFO_STATE_UNINITIALIZED = enum_GUEST_VM_INFO_STATE.define('GUEST_VM_INFO_STATE_UNINITIALIZED', 0) +GUEST_VM_INFO_STATE_INITIALIZED = enum_GUEST_VM_INFO_STATE.define('GUEST_VM_INFO_STATE_INITIALIZED', 1) - -# values for enumeration 'GUEST_VM_INFO_STATE' -GUEST_VM_INFO_STATE__enumvalues = { - 0: 'GUEST_VM_INFO_STATE_UNINITIALIZED', - 1: 'GUEST_VM_INFO_STATE_INITIALIZED', -} -GUEST_VM_INFO_STATE_UNINITIALIZED = 0 -GUEST_VM_INFO_STATE_INITIALIZED = 1 -GUEST_VM_INFO_STATE = ctypes.c_uint32 # enum -struct_NV2080_GUEST_VM_INFO._pack_ = 1 # source:False +GUEST_VM_INFO_STATE = enum_GUEST_VM_INFO_STATE struct_NV2080_GUEST_VM_INFO._fields_ = [ - ('vmPid', ctypes.c_uint32), - ('guestOs', ctypes.c_uint32), - ('migrationProhibited', ctypes.c_uint32), - ('guestNegotiatedVgpuVersion', ctypes.c_uint32), - ('frameRateLimit', ctypes.c_uint32), - ('licensed', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('licenseState', ctypes.c_uint32), - ('licenseExpiryTimestamp', ctypes.c_uint32), - ('licenseExpiryStatus', ctypes.c_ubyte), - ('guestDriverVersion', ctypes.c_ubyte * 32), - ('guestDriverBranch', ctypes.c_ubyte * 32), - ('PADDING_1', ctypes.c_ubyte * 3), - ('guestVmInfoState', GUEST_VM_INFO_STATE), + ('vmPid', NvU32), + ('guestOs', NvU32), + ('migrationProhibited', NvU32), + ('guestNegotiatedVgpuVersion', NvU32), + ('frameRateLimit', NvU32), + ('licensed', NvBool), + ('licenseState', NvU32), + ('licenseExpiryTimestamp', NvU32), + ('licenseExpiryStatus', NvU8), + ('guestDriverVersion', (NvU8 * 32)), + ('guestDriverBranch', (NvU8 * 32)), + ('guestVmInfoState', GUEST_VM_INFO_STATE), ] - NV2080_GUEST_VM_INFO = struct_NV2080_GUEST_VM_INFO -class struct_NV2080_HOST_VGPU_DEVICE(Structure): - pass - -struct_NV2080_HOST_VGPU_DEVICE._pack_ = 1 # source:False +class struct_NV2080_HOST_VGPU_DEVICE(Struct): pass struct_NV2080_HOST_VGPU_DEVICE._fields_ = [ - ('gfid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vgpuPciId', ctypes.c_uint64), - ('vgpuDeviceInstanceId', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('fbUsed', ctypes.c_uint64), - ('encoderCapacity', ctypes.c_uint32), - ('eccState', ctypes.c_uint32), - ('bDriverLoaded', ctypes.c_ubyte), - ('PADDING_2', ctypes.c_ubyte * 7), + ('gfid', NvU32), + ('vgpuPciId', NvU64), + ('vgpuDeviceInstanceId', NvU32), + ('fbUsed', NvU64), + ('encoderCapacity', NvU32), + ('eccState', NvU32), + ('bDriverLoaded', NvBool), ] - NV2080_HOST_VGPU_DEVICE = struct_NV2080_HOST_VGPU_DEVICE -class struct_NV2080_VGPU_GUEST(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('guestVmInfo', NV2080_GUEST_VM_INFO), - ('vgpuDevice', NV2080_HOST_VGPU_DEVICE), - ] - +class struct_NV2080_VGPU_GUEST(Struct): pass +struct_NV2080_VGPU_GUEST._fields_ = [ + ('guestVmInfo', NV2080_GUEST_VM_INFO), + ('vgpuDevice', NV2080_HOST_VGPU_DEVICE), +] NV2080_VGPU_GUEST = struct_NV2080_VGPU_GUEST -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS._fields_ = [ - ('numVgpu', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vgpuGuest', struct_NV2080_VGPU_GUEST * 32), + ('numVgpu', NvU32), + ('vgpuGuest', (NV2080_VGPU_GUEST * 32)), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), + ('gfid', NvU32), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS -class struct_NV2080_VGPU_FB_USAGE(Structure): - pass - -struct_NV2080_VGPU_FB_USAGE._pack_ = 1 # source:False +class struct_NV2080_VGPU_FB_USAGE(Struct): pass struct_NV2080_VGPU_FB_USAGE._fields_ = [ - ('gfid', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fbUsed', ctypes.c_uint64), + ('gfid', NvU32), + ('fbUsed', NvU64), ] - NV2080_VGPU_FB_USAGE = struct_NV2080_VGPU_FB_USAGE -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS._fields_ = [ - ('vgpuCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('vgpuFbUsage', struct_NV2080_VGPU_FB_USAGE * 32), + ('vgpuCount', NvU32), + ('vgpuFbUsage', (NV2080_VGPU_FB_USAGE * 32)), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('encoderCapacity', ctypes.c_uint32), + ('gfid', NvU32), + ('encoderCapacity', NvU32), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), + ('gfid', NvU32), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS._fields_ = [ - ('pgpuString', ctypes.c_ubyte * 256), - ('pgpuStringSize', ctypes.c_uint32), + ('pgpuString', (NvU8 * 256)), + ('pgpuStringSize', NvU32), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS._fields_ = [ - ('bIsMigrationSupported', ctypes.c_ubyte), + ('bIsMigrationSupported', NvBool), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS._fields_ = [ - ('bSupportHeterogeneousTimeSlicedVgpuTypes', ctypes.c_ubyte), + ('bSupportHeterogeneousTimeSlicedVgpuTypes', NvBool), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS._fields_ = [ - ('gfid', ctypes.c_uint32), - ('flags', ctypes.c_uint32), + ('gfid', NvU32), + ('flags', NvU32), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS._fields_ = [ - ('bFlrDisabled', ctypes.c_ubyte), + ('bFlrDisabled', NvBool), ] - NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS = struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS -class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Structure): - pass - -struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._pack_ = 1 # source:False +class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Struct): pass struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [ - ('bHeterogeneousMode', ctypes.c_ubyte), + ('bHeterogeneousMode', NvBool), ] - NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS -# def NV83DE_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x83DE,NV83DE_CTRL_##cat,idx) -NV83DE_CTRL_RESERVED = (0x00) # macro -NV83DE_CTRL_GR = (0x01) # macro -NV83DE_CTRL_FIFO = (0x02) # macro -NV83DE_CTRL_DEBUG = (0x03) # macro -NV83DE_CTRL_INTERNAL = (0x04) # macro -NV83DE_CTRL_CMD_NULL = (0x83de0000) # macro -NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE = (0x83de0301) # macro -NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE = (0x83de0302) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG = (0x83de0307) # macro -NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x7) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS = (0x00000003) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG = (0x83de0308) # macro -NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x8) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = (0x83de0309) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID = (0x9) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL = (0x00000001) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP = (0x00000002) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP = (0x00000004) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT = (0x00000008) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP = (0x00000010) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED = (0x00000020) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE = (0x00000000) # macro -NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL = (0x0000FFFF) # macro -NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE = (0x83de030b) # macro -NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xB) # macro -NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = (0x83de030c) # macro -NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL = 100 # macro -NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0xC) # macro -NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE = (0x83de030f) # macro -NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xF) # macro -NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = (0x83de0310) # macro -NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0x10) # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED = 1 # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL = 1 # macro -NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE = (0x83de0313) # macro -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID = (0x13) # macro -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM = (0x00000001) # macro -NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING = (0x83de0314) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID = (0x14) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING = (0x00000001) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_READ_MEMORY = (0x83de0315) # macro -NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID = (0x15) # macro -NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY = (0x83de0316) # macro -NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID = (0x16) # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT = (0x83de0317) # macro -NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID = (0x17) # macro -NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT = (0x83de0318) # macro -NV83DE_CTRL_CMD_DEBUG_GET_HANDLES = (0x83de0319) # macro -NV83DE_CTRL_CMD_READ_SURFACE = (0x83de031a) # macro -NV83DE_CTRL_CMD_WRITE_SURFACE = (0x83de031b) # macro -MAX_ACCESS_OPS = 64 # macro -NV83DE_CTRL_CMD_GET_MAPPINGS = (0x83de031c) # macro -MAX_GET_MAPPINGS_OPS = 64 # macro -NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS = (0x83de031d) # macro -NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS = 100 # macro -NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x1D) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG = (0x83de031f) # macro -NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x1F) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE = (0x00000000) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG = (0x83de0320) # macro -NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x20) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED = (0x00000000) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP = (0x83de0321) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID = (0x21) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER = (0x83de0322) # macro -# NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_BROADCAST = ((NvU32)~0) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID = (0x22) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER = (0x83de0323) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID = (0x23) # macro -NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT = (0x83de0324) # macro -NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID = (0x24) # macro -NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS = (0x83de0325) # macro -NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID = (0x25) # macro -NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY = (0x83de0326) # macro -NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY = (0x83de0327) # macro -MAX_ACCESS_MEMORY_OPS = 150 # macro -NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES = 4 # macro -NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO = (0x83de0328) # macro -NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID = (0x28) # macro -NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC = (0x83de0329) # macro -NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID = (0x29) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG = (0x83de032a) # macro -NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2A) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE = (0x00000002) # macro -NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS = (0x00000003) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG = (0x83de032b) # macro -NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2B) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED = (0x00000001) # macro -NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED = (0x00000002) # macro -class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), + ('action', NvU32), ] - NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), + ('value', NvU32), ] - NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS._fields_ = [ - ('exceptionMask', ctypes.c_uint32), + ('exceptionMask', NvU32), ] - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS -class struct_NV83DE_SM_ERROR_STATE_REGISTERS(Structure): - pass - -struct_NV83DE_SM_ERROR_STATE_REGISTERS._pack_ = 1 # source:False +class struct_NV83DE_SM_ERROR_STATE_REGISTERS(Struct): pass struct_NV83DE_SM_ERROR_STATE_REGISTERS._fields_ = [ - ('hwwGlobalEsr', ctypes.c_uint32), - ('hwwWarpEsr', ctypes.c_uint32), - ('hwwWarpEsrPc', ctypes.c_uint32), - ('hwwGlobalEsrReportMask', ctypes.c_uint32), - ('hwwWarpEsrReportMask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('hwwEsrAddr', ctypes.c_uint64), - ('hwwWarpEsrPc64', ctypes.c_uint64), - ('hwwCgaEsr', ctypes.c_uint32), - ('hwwCgaEsrReportMask', ctypes.c_uint32), + ('hwwGlobalEsr', NvU32), + ('hwwWarpEsr', NvU32), + ('hwwWarpEsrPc', NvU32), + ('hwwGlobalEsrReportMask', NvU32), + ('hwwWarpEsrReportMask', NvU32), + ('hwwEsrAddr', NvU64), + ('hwwWarpEsrPc64', NvU64), + ('hwwCgaEsr', NvU32), + ('hwwCgaEsrReportMask', NvU32), ] - NV83DE_SM_ERROR_STATE_REGISTERS = struct_NV83DE_SM_ERROR_STATE_REGISTERS -class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('smID', ctypes.c_uint32), - ('smErrorState', NV83DE_SM_ERROR_STATE_REGISTERS), + ('hTargetChannel', NvHandle), + ('smID', NvU32), + ('smErrorState', NV83DE_SM_ERROR_STATE_REGISTERS), ] - NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS -class struct_NV83DE_MMU_FAULT_INFO(Structure): - pass - -struct_NV83DE_MMU_FAULT_INFO._pack_ = 1 # source:False +class struct_NV83DE_MMU_FAULT_INFO(Struct): pass struct_NV83DE_MMU_FAULT_INFO._fields_ = [ - ('valid', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('faultInfo', ctypes.c_uint32), + ('valid', NvBool), + ('faultInfo', NvU32), ] - NV83DE_MMU_FAULT_INFO = struct_NV83DE_MMU_FAULT_INFO -class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('numSMsToRead', ctypes.c_uint32), - ('smErrorStateArray', struct_NV83DE_SM_ERROR_STATE_REGISTERS * 100), - ('mmuFaultInfo', ctypes.c_uint32), - ('mmuFault', NV83DE_MMU_FAULT_INFO), - ('startingSM', ctypes.c_uint32), + ('hTargetChannel', NvHandle), + ('numSMsToRead', NvU32), + ('smErrorStateArray', (NV83DE_SM_ERROR_STATE_REGISTERS * 100)), + ('mmuFaultInfo', NvU32), + ('mmuFault', NV83DE_MMU_FAULT_INFO), + ('startingSM', NvU32), ] - NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS -class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('smID', ctypes.c_uint32), + ('hTargetChannel', NvHandle), + ('smID', NvU32), ] - NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS = struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS -class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS._fields_ = [ - ('hTargetChannel', ctypes.c_uint32), - ('numSMsToClear', ctypes.c_uint32), + ('hTargetChannel', NvHandle), + ('numSMsToClear', NvU32), ] - NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS = struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS -class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS(Struct): pass struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS._fields_ = [ - ('waitForEvent', ctypes.c_uint32), - ('hResidentChannel', ctypes.c_uint32), + ('waitForEvent', NvU32), + ('hResidentChannel', NvHandle), ] - NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS._fields_ = [ - ('stopTriggerType', ctypes.c_uint32), + ('stopTriggerType', NvU32), ] - NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS._fields_ = [ - ('singleStepHandling', ctypes.c_uint32), + ('singleStepHandling', NvU32), ] - NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS -class struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('buffer', ctypes.POINTER(None)), + ('hMemory', NvU32), + ('length', NvU32), + ('offset', NvU64), + ('buffer', NvP64), ] - NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS -class struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('buffer', ctypes.POINTER(None)), + ('hMemory', NvU32), + ('length', NvU32), + ('offset', NvU64), + ('buffer', NvP64), ] - NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS._fields_ = [ - ('hChannel', ctypes.c_uint32), - ('hSubdevice', ctypes.c_uint32), + ('hChannel', NvHandle), + ('hSubdevice', NvHandle), ] - NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS -class struct_NV83DE_CTRL_DEBUG_ACCESS_OP(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_OP._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_ACCESS_OP(Struct): pass struct_NV83DE_CTRL_DEBUG_ACCESS_OP._fields_ = [ - ('gpuVA', ctypes.c_uint64), - ('pCpuVA', ctypes.POINTER(None)), - ('size', ctypes.c_uint32), - ('valid', ctypes.c_uint32), + ('gpuVA', NvU64), + ('pCpuVA', NvP64), + ('size', NvU32), + ('valid', NvU32), ] - NV83DE_CTRL_DEBUG_ACCESS_OP = struct_NV83DE_CTRL_DEBUG_ACCESS_OP -class struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS(Struct): pass struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS._fields_ = [ - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('opsBuffer', struct_NV83DE_CTRL_DEBUG_ACCESS_OP * 64), + ('count', NvU32), + ('opsBuffer', (NV83DE_CTRL_DEBUG_ACCESS_OP * 64)), ] - NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS = struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS -class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP._fields_ = [ - ('gpuVA', ctypes.c_uint64), - ('size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('gpuVA', NvU64), + ('size', NvU32), ] - NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP -class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS._fields_ = [ - ('vaLo', ctypes.c_uint64), - ('vaHi', ctypes.c_uint64), - ('count', ctypes.c_uint32), - ('hasMore', ctypes.c_uint32), - ('opsBuffer', struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP * 64), + ('vaLo', NvU64), + ('vaHi', NvU64), + ('count', NvU32), + ('hasMore', NvU32), + ('opsBuffer', (NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP * 64)), ] - NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS -class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS._fields_ = [ - ('bNonTransactional', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('regOpCount', ctypes.c_uint32), - ('regOps', struct_NV2080_CTRL_GPU_REG_OP * 100), + ('bNonTransactional', NvBool), + ('regOpCount', NvU32), + ('regOps', (NV2080_CTRL_GPU_REG_OP * 100)), ] - NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS = struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), + ('action', NvU32), ] - NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), + ('value', NvU32), ] - NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bSingleStep', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('smID', NvU32), + ('bSingleStep', NvBool), ] - NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bStopTrigger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('smID', NvU32), + ('bStopTrigger', NvBool), ] - NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bRunTrigger', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('smID', NvU32), + ('bRunTrigger', NvBool), ] - NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('bSkipIdleWarpDetect', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), + ('smID', NvU32), + ('bSkipIdleWarpDetect', NvBool), ] - NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS -class struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS(Struct): pass struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS._fields_ = [ - ('bInTrapMode', ctypes.c_ubyte), - ('bCrsFlushDone', ctypes.c_ubyte), - ('bRunTriggerInProgress', ctypes.c_ubyte), - ('bComputeContext', ctypes.c_ubyte), - ('bLockedDown', ctypes.c_ubyte), + ('bInTrapMode', NvBool), + ('bCrsFlushDone', NvBool), + ('bRunTriggerInProgress', NvBool), + ('bComputeContext', NvBool), + ('bLockedDown', NvBool), ] - NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS = struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS -class struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS._fields_ = [ - ('smID', ctypes.c_uint32), - ('smDebuggerStatus', NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS), - ('PADDING_0', ctypes.c_ubyte * 3), + ('smID', NvU32), + ('smDebuggerStatus', NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS), ] - NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS -class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY(Struct): pass struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY._fields_ = [ - ('hMemory', ctypes.c_uint32), - ('length', ctypes.c_uint32), - ('memOffset', ctypes.c_uint64), - ('dataOffset', ctypes.c_uint32), - ('status', ctypes.c_uint32), + ('hMemory', NvHandle), + ('length', NvU32), + ('memOffset', NvU64), + ('dataOffset', NvU32), + ('status', NV_STATUS), ] - NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY -class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [ - ('pData', ctypes.POINTER(None)), - ('dataLength', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('entries', struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY * 150), + ('pData', NvP64), + ('dataLength', NvU32), + ('count', NvU32), + ('entries', (NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY * 150)), ] - NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS -class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY(Struct): pass struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY._fields_ = [ - ('faultAddress', ctypes.c_uint64), - ('faultType', ctypes.c_uint32), - ('accessType', ctypes.c_uint32), + ('faultAddress', NvU64), + ('faultType', NvU32), + ('accessType', NvU32), ] - NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY -class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS._fields_ = [ - ('mmuFaultInfoList', struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY * 4), - ('count', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('mmuFaultInfoList', (NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY * 4)), + ('count', NvU32), ] - NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS._fields_ = [ - ('bDropDeferredRc', ctypes.c_ubyte), + ('bDropDeferredRc', NvBool), ] - NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS -class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS._fields_ = [ - ('action', ctypes.c_uint32), + ('action', NvU32), ] - NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS -class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS(Structure): - pass - -struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS._pack_ = 1 # source:False +class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS(Struct): pass struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS._fields_ = [ - ('value', ctypes.c_uint32), + ('value', NvU32), ] - NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS -# def NVC36F_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0xC36F,NVC36F_CTRL_##cat,idx) -NVC36F_CTRL_RESERVED = (0x00) # macro -NVC36F_CTRL_GPFIFO = (0x01) # macro -NVC36F_CTRL_EVENT = (0x02) # macro -NVC36F_CTRL_INTERNAL = (0x03) # macro -NVC36F_CTRL_CMD_NULL = (0xc36f0000) # macro -NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0108) # macro -NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x8) # macro -NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES = 0x2 # macro -NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER = (0xc36f0109) # macro -NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID = (0x9) # macro -NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = (0xc36f010a) # macro -NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID = (0xA) # macro -NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION = (0xc36f0205) # macro -NVC36F_CTRL_CMD_EVENT_SET_TRIGGER = (0xc36f0206) # macro -NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0301) # macro -NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x1) # macro -class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS(Structure): - pass +nv_status_codes = CEnum(ctypes.c_uint32) +NV_OK = nv_status_codes.define('NV_OK', 0) +NV_ERR_GENERIC = nv_status_codes.define('NV_ERR_GENERIC', 65535) +NV_ERR_BROKEN_FB = nv_status_codes.define('NV_ERR_BROKEN_FB', 1) +NV_ERR_BUFFER_TOO_SMALL = nv_status_codes.define('NV_ERR_BUFFER_TOO_SMALL', 2) +NV_ERR_BUSY_RETRY = nv_status_codes.define('NV_ERR_BUSY_RETRY', 3) +NV_ERR_CALLBACK_NOT_SCHEDULED = nv_status_codes.define('NV_ERR_CALLBACK_NOT_SCHEDULED', 4) +NV_ERR_CARD_NOT_PRESENT = nv_status_codes.define('NV_ERR_CARD_NOT_PRESENT', 5) +NV_ERR_CYCLE_DETECTED = nv_status_codes.define('NV_ERR_CYCLE_DETECTED', 6) +NV_ERR_DMA_IN_USE = nv_status_codes.define('NV_ERR_DMA_IN_USE', 7) +NV_ERR_DMA_MEM_NOT_LOCKED = nv_status_codes.define('NV_ERR_DMA_MEM_NOT_LOCKED', 8) +NV_ERR_DMA_MEM_NOT_UNLOCKED = nv_status_codes.define('NV_ERR_DMA_MEM_NOT_UNLOCKED', 9) +NV_ERR_DUAL_LINK_INUSE = nv_status_codes.define('NV_ERR_DUAL_LINK_INUSE', 10) +NV_ERR_ECC_ERROR = nv_status_codes.define('NV_ERR_ECC_ERROR', 11) +NV_ERR_FIFO_BAD_ACCESS = nv_status_codes.define('NV_ERR_FIFO_BAD_ACCESS', 12) +NV_ERR_FREQ_NOT_SUPPORTED = nv_status_codes.define('NV_ERR_FREQ_NOT_SUPPORTED', 13) +NV_ERR_GPU_DMA_NOT_INITIALIZED = nv_status_codes.define('NV_ERR_GPU_DMA_NOT_INITIALIZED', 14) +NV_ERR_GPU_IS_LOST = nv_status_codes.define('NV_ERR_GPU_IS_LOST', 15) +NV_ERR_GPU_IN_FULLCHIP_RESET = nv_status_codes.define('NV_ERR_GPU_IN_FULLCHIP_RESET', 16) +NV_ERR_GPU_NOT_FULL_POWER = nv_status_codes.define('NV_ERR_GPU_NOT_FULL_POWER', 17) +NV_ERR_GPU_UUID_NOT_FOUND = nv_status_codes.define('NV_ERR_GPU_UUID_NOT_FOUND', 18) +NV_ERR_HOT_SWITCH = nv_status_codes.define('NV_ERR_HOT_SWITCH', 19) +NV_ERR_I2C_ERROR = nv_status_codes.define('NV_ERR_I2C_ERROR', 20) +NV_ERR_I2C_SPEED_TOO_HIGH = nv_status_codes.define('NV_ERR_I2C_SPEED_TOO_HIGH', 21) +NV_ERR_ILLEGAL_ACTION = nv_status_codes.define('NV_ERR_ILLEGAL_ACTION', 22) +NV_ERR_IN_USE = nv_status_codes.define('NV_ERR_IN_USE', 23) +NV_ERR_INFLATE_COMPRESSED_DATA_FAILED = nv_status_codes.define('NV_ERR_INFLATE_COMPRESSED_DATA_FAILED', 24) +NV_ERR_INSERT_DUPLICATE_NAME = nv_status_codes.define('NV_ERR_INSERT_DUPLICATE_NAME', 25) +NV_ERR_INSUFFICIENT_RESOURCES = nv_status_codes.define('NV_ERR_INSUFFICIENT_RESOURCES', 26) +NV_ERR_INSUFFICIENT_PERMISSIONS = nv_status_codes.define('NV_ERR_INSUFFICIENT_PERMISSIONS', 27) +NV_ERR_INSUFFICIENT_POWER = nv_status_codes.define('NV_ERR_INSUFFICIENT_POWER', 28) +NV_ERR_INVALID_ACCESS_TYPE = nv_status_codes.define('NV_ERR_INVALID_ACCESS_TYPE', 29) +NV_ERR_INVALID_ADDRESS = nv_status_codes.define('NV_ERR_INVALID_ADDRESS', 30) +NV_ERR_INVALID_ARGUMENT = nv_status_codes.define('NV_ERR_INVALID_ARGUMENT', 31) +NV_ERR_INVALID_BASE = nv_status_codes.define('NV_ERR_INVALID_BASE', 32) +NV_ERR_INVALID_CHANNEL = nv_status_codes.define('NV_ERR_INVALID_CHANNEL', 33) +NV_ERR_INVALID_CLASS = nv_status_codes.define('NV_ERR_INVALID_CLASS', 34) +NV_ERR_INVALID_CLIENT = nv_status_codes.define('NV_ERR_INVALID_CLIENT', 35) +NV_ERR_INVALID_COMMAND = nv_status_codes.define('NV_ERR_INVALID_COMMAND', 36) +NV_ERR_INVALID_DATA = nv_status_codes.define('NV_ERR_INVALID_DATA', 37) +NV_ERR_INVALID_DEVICE = nv_status_codes.define('NV_ERR_INVALID_DEVICE', 38) +NV_ERR_INVALID_DMA_SPECIFIER = nv_status_codes.define('NV_ERR_INVALID_DMA_SPECIFIER', 39) +NV_ERR_INVALID_EVENT = nv_status_codes.define('NV_ERR_INVALID_EVENT', 40) +NV_ERR_INVALID_FLAGS = nv_status_codes.define('NV_ERR_INVALID_FLAGS', 41) +NV_ERR_INVALID_FUNCTION = nv_status_codes.define('NV_ERR_INVALID_FUNCTION', 42) +NV_ERR_INVALID_HEAP = nv_status_codes.define('NV_ERR_INVALID_HEAP', 43) +NV_ERR_INVALID_INDEX = nv_status_codes.define('NV_ERR_INVALID_INDEX', 44) +NV_ERR_INVALID_IRQ_LEVEL = nv_status_codes.define('NV_ERR_INVALID_IRQ_LEVEL', 45) +NV_ERR_INVALID_LIMIT = nv_status_codes.define('NV_ERR_INVALID_LIMIT', 46) +NV_ERR_INVALID_LOCK_STATE = nv_status_codes.define('NV_ERR_INVALID_LOCK_STATE', 47) +NV_ERR_INVALID_METHOD = nv_status_codes.define('NV_ERR_INVALID_METHOD', 48) +NV_ERR_INVALID_OBJECT = nv_status_codes.define('NV_ERR_INVALID_OBJECT', 49) +NV_ERR_INVALID_OBJECT_BUFFER = nv_status_codes.define('NV_ERR_INVALID_OBJECT_BUFFER', 50) +NV_ERR_INVALID_OBJECT_HANDLE = nv_status_codes.define('NV_ERR_INVALID_OBJECT_HANDLE', 51) +NV_ERR_INVALID_OBJECT_NEW = nv_status_codes.define('NV_ERR_INVALID_OBJECT_NEW', 52) +NV_ERR_INVALID_OBJECT_OLD = nv_status_codes.define('NV_ERR_INVALID_OBJECT_OLD', 53) +NV_ERR_INVALID_OBJECT_PARENT = nv_status_codes.define('NV_ERR_INVALID_OBJECT_PARENT', 54) +NV_ERR_INVALID_OFFSET = nv_status_codes.define('NV_ERR_INVALID_OFFSET', 55) +NV_ERR_INVALID_OPERATION = nv_status_codes.define('NV_ERR_INVALID_OPERATION', 56) +NV_ERR_INVALID_OWNER = nv_status_codes.define('NV_ERR_INVALID_OWNER', 57) +NV_ERR_INVALID_PARAM_STRUCT = nv_status_codes.define('NV_ERR_INVALID_PARAM_STRUCT', 58) +NV_ERR_INVALID_PARAMETER = nv_status_codes.define('NV_ERR_INVALID_PARAMETER', 59) +NV_ERR_INVALID_PATH = nv_status_codes.define('NV_ERR_INVALID_PATH', 60) +NV_ERR_INVALID_POINTER = nv_status_codes.define('NV_ERR_INVALID_POINTER', 61) +NV_ERR_INVALID_REGISTRY_KEY = nv_status_codes.define('NV_ERR_INVALID_REGISTRY_KEY', 62) +NV_ERR_INVALID_REQUEST = nv_status_codes.define('NV_ERR_INVALID_REQUEST', 63) +NV_ERR_INVALID_STATE = nv_status_codes.define('NV_ERR_INVALID_STATE', 64) +NV_ERR_INVALID_STRING_LENGTH = nv_status_codes.define('NV_ERR_INVALID_STRING_LENGTH', 65) +NV_ERR_INVALID_READ = nv_status_codes.define('NV_ERR_INVALID_READ', 66) +NV_ERR_INVALID_WRITE = nv_status_codes.define('NV_ERR_INVALID_WRITE', 67) +NV_ERR_INVALID_XLATE = nv_status_codes.define('NV_ERR_INVALID_XLATE', 68) +NV_ERR_IRQ_NOT_FIRING = nv_status_codes.define('NV_ERR_IRQ_NOT_FIRING', 69) +NV_ERR_IRQ_EDGE_TRIGGERED = nv_status_codes.define('NV_ERR_IRQ_EDGE_TRIGGERED', 70) +NV_ERR_MEMORY_TRAINING_FAILED = nv_status_codes.define('NV_ERR_MEMORY_TRAINING_FAILED', 71) +NV_ERR_MISMATCHED_SLAVE = nv_status_codes.define('NV_ERR_MISMATCHED_SLAVE', 72) +NV_ERR_MISMATCHED_TARGET = nv_status_codes.define('NV_ERR_MISMATCHED_TARGET', 73) +NV_ERR_MISSING_TABLE_ENTRY = nv_status_codes.define('NV_ERR_MISSING_TABLE_ENTRY', 74) +NV_ERR_MODULE_LOAD_FAILED = nv_status_codes.define('NV_ERR_MODULE_LOAD_FAILED', 75) +NV_ERR_MORE_DATA_AVAILABLE = nv_status_codes.define('NV_ERR_MORE_DATA_AVAILABLE', 76) +NV_ERR_MORE_PROCESSING_REQUIRED = nv_status_codes.define('NV_ERR_MORE_PROCESSING_REQUIRED', 77) +NV_ERR_MULTIPLE_MEMORY_TYPES = nv_status_codes.define('NV_ERR_MULTIPLE_MEMORY_TYPES', 78) +NV_ERR_NO_FREE_FIFOS = nv_status_codes.define('NV_ERR_NO_FREE_FIFOS', 79) +NV_ERR_NO_INTR_PENDING = nv_status_codes.define('NV_ERR_NO_INTR_PENDING', 80) +NV_ERR_NO_MEMORY = nv_status_codes.define('NV_ERR_NO_MEMORY', 81) +NV_ERR_NO_SUCH_DOMAIN = nv_status_codes.define('NV_ERR_NO_SUCH_DOMAIN', 82) +NV_ERR_NO_VALID_PATH = nv_status_codes.define('NV_ERR_NO_VALID_PATH', 83) +NV_ERR_NOT_COMPATIBLE = nv_status_codes.define('NV_ERR_NOT_COMPATIBLE', 84) +NV_ERR_NOT_READY = nv_status_codes.define('NV_ERR_NOT_READY', 85) +NV_ERR_NOT_SUPPORTED = nv_status_codes.define('NV_ERR_NOT_SUPPORTED', 86) +NV_ERR_OBJECT_NOT_FOUND = nv_status_codes.define('NV_ERR_OBJECT_NOT_FOUND', 87) +NV_ERR_OBJECT_TYPE_MISMATCH = nv_status_codes.define('NV_ERR_OBJECT_TYPE_MISMATCH', 88) +NV_ERR_OPERATING_SYSTEM = nv_status_codes.define('NV_ERR_OPERATING_SYSTEM', 89) +NV_ERR_OTHER_DEVICE_FOUND = nv_status_codes.define('NV_ERR_OTHER_DEVICE_FOUND', 90) +NV_ERR_OUT_OF_RANGE = nv_status_codes.define('NV_ERR_OUT_OF_RANGE', 91) +NV_ERR_OVERLAPPING_UVM_COMMIT = nv_status_codes.define('NV_ERR_OVERLAPPING_UVM_COMMIT', 92) +NV_ERR_PAGE_TABLE_NOT_AVAIL = nv_status_codes.define('NV_ERR_PAGE_TABLE_NOT_AVAIL', 93) +NV_ERR_PID_NOT_FOUND = nv_status_codes.define('NV_ERR_PID_NOT_FOUND', 94) +NV_ERR_PROTECTION_FAULT = nv_status_codes.define('NV_ERR_PROTECTION_FAULT', 95) +NV_ERR_RC_ERROR = nv_status_codes.define('NV_ERR_RC_ERROR', 96) +NV_ERR_REJECTED_VBIOS = nv_status_codes.define('NV_ERR_REJECTED_VBIOS', 97) +NV_ERR_RESET_REQUIRED = nv_status_codes.define('NV_ERR_RESET_REQUIRED', 98) +NV_ERR_STATE_IN_USE = nv_status_codes.define('NV_ERR_STATE_IN_USE', 99) +NV_ERR_SIGNAL_PENDING = nv_status_codes.define('NV_ERR_SIGNAL_PENDING', 100) +NV_ERR_TIMEOUT = nv_status_codes.define('NV_ERR_TIMEOUT', 101) +NV_ERR_TIMEOUT_RETRY = nv_status_codes.define('NV_ERR_TIMEOUT_RETRY', 102) +NV_ERR_TOO_MANY_PRIMARIES = nv_status_codes.define('NV_ERR_TOO_MANY_PRIMARIES', 103) +NV_ERR_UVM_ADDRESS_IN_USE = nv_status_codes.define('NV_ERR_UVM_ADDRESS_IN_USE', 104) +NV_ERR_MAX_SESSION_LIMIT_REACHED = nv_status_codes.define('NV_ERR_MAX_SESSION_LIMIT_REACHED', 105) +NV_ERR_LIB_RM_VERSION_MISMATCH = nv_status_codes.define('NV_ERR_LIB_RM_VERSION_MISMATCH', 106) +NV_ERR_PRIV_SEC_VIOLATION = nv_status_codes.define('NV_ERR_PRIV_SEC_VIOLATION', 107) +NV_ERR_GPU_IN_DEBUG_MODE = nv_status_codes.define('NV_ERR_GPU_IN_DEBUG_MODE', 108) +NV_ERR_FEATURE_NOT_ENABLED = nv_status_codes.define('NV_ERR_FEATURE_NOT_ENABLED', 109) +NV_ERR_RESOURCE_LOST = nv_status_codes.define('NV_ERR_RESOURCE_LOST', 110) +NV_ERR_PMU_NOT_READY = nv_status_codes.define('NV_ERR_PMU_NOT_READY', 111) +NV_ERR_FLCN_ERROR = nv_status_codes.define('NV_ERR_FLCN_ERROR', 112) +NV_ERR_FATAL_ERROR = nv_status_codes.define('NV_ERR_FATAL_ERROR', 113) +NV_ERR_MEMORY_ERROR = nv_status_codes.define('NV_ERR_MEMORY_ERROR', 114) +NV_ERR_INVALID_LICENSE = nv_status_codes.define('NV_ERR_INVALID_LICENSE', 115) +NV_ERR_NVLINK_INIT_ERROR = nv_status_codes.define('NV_ERR_NVLINK_INIT_ERROR', 116) +NV_ERR_NVLINK_MINION_ERROR = nv_status_codes.define('NV_ERR_NVLINK_MINION_ERROR', 117) +NV_ERR_NVLINK_CLOCK_ERROR = nv_status_codes.define('NV_ERR_NVLINK_CLOCK_ERROR', 118) +NV_ERR_NVLINK_TRAINING_ERROR = nv_status_codes.define('NV_ERR_NVLINK_TRAINING_ERROR', 119) +NV_ERR_NVLINK_CONFIGURATION_ERROR = nv_status_codes.define('NV_ERR_NVLINK_CONFIGURATION_ERROR', 120) +NV_ERR_RISCV_ERROR = nv_status_codes.define('NV_ERR_RISCV_ERROR', 121) +NV_ERR_FABRIC_MANAGER_NOT_PRESENT = nv_status_codes.define('NV_ERR_FABRIC_MANAGER_NOT_PRESENT', 122) +NV_ERR_ALREADY_SIGNALLED = nv_status_codes.define('NV_ERR_ALREADY_SIGNALLED', 123) +NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE = nv_status_codes.define('NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE', 124) +NV_ERR_KEY_ROTATION_IN_PROGRESS = nv_status_codes.define('NV_ERR_KEY_ROTATION_IN_PROGRESS', 125) +NV_ERR_TEST_ONLY_CODE_NOT_ENABLED = nv_status_codes.define('NV_ERR_TEST_ONLY_CODE_NOT_ENABLED', 126) +NV_ERR_SECURE_BOOT_FAILED = nv_status_codes.define('NV_ERR_SECURE_BOOT_FAILED', 127) +NV_ERR_INSUFFICIENT_ZBC_ENTRY = nv_status_codes.define('NV_ERR_INSUFFICIENT_ZBC_ENTRY', 128) +NV_ERR_NVLINK_FABRIC_NOT_READY = nv_status_codes.define('NV_ERR_NVLINK_FABRIC_NOT_READY', 129) +NV_ERR_NVLINK_FABRIC_FAILURE = nv_status_codes.define('NV_ERR_NVLINK_FABRIC_FAILURE', 130) +NV_ERR_GPU_MEMORY_ONLINING_FAILURE = nv_status_codes.define('NV_ERR_GPU_MEMORY_ONLINING_FAILURE', 131) +NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE = nv_status_codes.define('NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE', 132) +NV_WARN_HOT_SWITCH = nv_status_codes.define('NV_WARN_HOT_SWITCH', 65537) +NV_WARN_INCORRECT_PERFMON_DATA = nv_status_codes.define('NV_WARN_INCORRECT_PERFMON_DATA', 65538) +NV_WARN_MISMATCHED_SLAVE = nv_status_codes.define('NV_WARN_MISMATCHED_SLAVE', 65539) +NV_WARN_MISMATCHED_TARGET = nv_status_codes.define('NV_WARN_MISMATCHED_TARGET', 65540) +NV_WARN_MORE_PROCESSING_REQUIRED = nv_status_codes.define('NV_WARN_MORE_PROCESSING_REQUIRED', 65541) +NV_WARN_NOTHING_TO_DO = nv_status_codes.define('NV_WARN_NOTHING_TO_DO', 65542) +NV_WARN_NULL_OBJECT = nv_status_codes.define('NV_WARN_NULL_OBJECT', 65543) +NV_WARN_OUT_OF_RANGE = nv_status_codes.define('NV_WARN_OUT_OF_RANGE', 65544) -struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS._pack_ = 1 # source:False -struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS._fields_ = [ - ('workSubmitToken', ctypes.c_uint32), -] - -NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS -class struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS(Structure): - pass - -struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS._pack_ = 1 # source:False -struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS._fields_ = [ - ('bar2Addr', ctypes.c_uint64 * 2), -] - -NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS = struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS -class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS(Structure): - pass - -struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS._pack_ = 1 # source:False -struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS._fields_ = [ - ('index', ctypes.c_uint32), -] - -NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS -NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS -# def NV_CONF_COMPUTE_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0xCB33,NVCB33_CTRL_##cat,idx) -NVCB33_CTRL_RESERVED = (0x00) # macro -NVCB33_CTRL_CONF_COMPUTE = (0x01) # macro -NV_CONF_COMPUTE_CTRL_CMD_NULL = (0xcb330000) # macro -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = (0xcb330101) # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV = 1 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX = 2 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP = 3 # macro -NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM = 4 # macro -NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM = 1 # macro -NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC = 2 # macro -NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM = 1 # macro -NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD = 2 # macro -NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED = 0 # macro -NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED = 1 # macro -NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED = 2 # macro -NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED = 0 # macro -NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED = 1 # macro -NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE = 0 # macro -NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE = 1 # macro -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = (0xcb330104) # macro -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE = (0xcb330105) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE = (0xcb330106) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE = (0xcb330107) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS = (0xcb330108) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0x8) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE = (0xcb330109) # macro -NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE = 0x1000 # macro -NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE = 0x1400 # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID = (0x9) # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT = (0xcb33010a) # macro -NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE = 0x2000 # macro -NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE = 0x1000 # macro -NV_CONF_COMPUTE_NONCE_SIZE = 0x20 # macro -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID = (0xA) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = (0xcb33010b) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE = (0xcb33010c) # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED = 0 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED = 1 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED = 2 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED = 3 # macro -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID = (0xC) # macro -class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS._fields_ = [ - ('cpuCapability', ctypes.c_ubyte), - ('gpusCapability', ctypes.c_ubyte), - ('environment', ctypes.c_ubyte), - ('ccFeature', ctypes.c_ubyte), - ('devToolsMode', ctypes.c_ubyte), - ('multiGpuMode', ctypes.c_ubyte), -] - -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS._fields_ = [ - ('bAcceptClientRequest', ctypes.c_ubyte), -] - -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS._fields_ = [ - ('bAcceptClientRequest', ctypes.c_ubyte), -] - -NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('protectedMemSizeInKb', ctypes.c_uint64), - ('unprotectedMemSizeInKb', ctypes.c_uint64), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('protectedMemSizeInKb', ctypes.c_uint64), - ('unprotectedMemSizeInKb', ctypes.c_uint64), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('numSupportedSec2CCSecureChannels', ctypes.c_uint32), - ('numSupportedCeCCSecureChannels', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('certChain', ctypes.c_ubyte * 4096), - ('certChainSize', ctypes.c_uint32), - ('attestationCertChain', ctypes.c_ubyte * 5120), - ('attestationCertChainSize', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('nonce', ctypes.c_ubyte * 32), - ('attestationReport', ctypes.c_ubyte * 8192), - ('attestationReportSize', ctypes.c_uint32), - ('isCecAttestationReportPresent', ctypes.c_ubyte), - ('cecAttestationReport', ctypes.c_ubyte * 4096), - ('PADDING_0', ctypes.c_ubyte * 3), - ('cecAttestationReportSize', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('maxSec2Channels', ctypes.c_uint32), - ('maxCeChannels', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS -class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS(Structure): - pass - -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS._pack_ = 1 # source:False -struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('keyRotationState', ctypes.c_uint32), -] - -NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS -# def NVA06C_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0xA06C,NVA06C_CTRL_##cat,idx) -NVA06C_CTRL_RESERVED = (0x00) # macro -NVA06C_CTRL_GPFIFO = (0x01) # macro -NVA06C_CTRL_INTERNAL = (0x02) # macro -NVA06C_CTRL_CMD_NULL = (0xa06c0000) # macro -NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06c0101) # macro -NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # macro -NVA06C_CTRL_CMD_BIND = (0xa06c0102) # macro -NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID = (0x2) # macro -NVA06C_CTRL_CMD_SET_TIMESLICE = (0xa06c0103) # macro -NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x3) # macro -NVA06C_CTRL_CMD_GET_TIMESLICE = (0xa06c0104) # macro -NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID = (0x4) # macro -NVA06C_CTRL_CMD_PREEMPT = (0xa06c0105) # macro -NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID = (0x5) # macro -NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US = (1000000) # macro -NVA06C_CTRL_CMD_GET_INFO = (0xa06c0106) # macro -NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID = (0x6) # macro -NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06c0107) # macro -NVA06C_CTRL_INTERLEAVE_LEVEL_LOW = (0x00000000) # macro -NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM = (0x00000001) # macro -NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH = (0x00000002) # macro -NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x7) # macro -NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06c0108) # macro -NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x8) # macro -NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE = (0xa06c0109) # macro -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID = (0x9) # macro -NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = (0xa06c010a) # macro -NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES = (0x2) # macro -NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID = (0xa) # macro -NVA06C_CTRL_CMD_MAKE_REALTIME = (0xa06c0110) # macro -NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID = (0x10) # macro -NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE = (0xa06c0201) # macro -NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) # macro -NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE = (0xa06c0202) # macro -NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x2) # macro -class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS(Structure): - pass - -struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS._pack_ = 1 # source:False -struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS._fields_ = [ - ('bEnable', ctypes.c_ubyte), - ('bSkipSubmit', ctypes.c_ubyte), -] - -NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS -class struct_NVA06F_CTRL_BIND_PARAMS(Structure): - pass - -struct_NVA06F_CTRL_BIND_PARAMS._pack_ = 1 # source:False -struct_NVA06F_CTRL_BIND_PARAMS._fields_ = [ - ('engineType', ctypes.c_uint32), -] - -NVA06C_CTRL_BIND_PARAMS = struct_NVA06F_CTRL_BIND_PARAMS -class struct_NVA06C_CTRL_TIMESLICE_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_TIMESLICE_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_TIMESLICE_PARAMS._fields_ = [ - ('timesliceUs', ctypes.c_uint64), -] - -NVA06C_CTRL_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -NVA06C_CTRL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -NVA06C_CTRL_GET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -class struct_NVA06C_CTRL_PREEMPT_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_PREEMPT_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_PREEMPT_PARAMS._fields_ = [ - ('bWait', ctypes.c_ubyte), - ('bManualTimeout', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('timeoutUs', ctypes.c_uint32), -] - -NVA06C_CTRL_PREEMPT_PARAMS = struct_NVA06C_CTRL_PREEMPT_PARAMS -class struct_NVA06C_CTRL_GET_INFO_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_GET_INFO_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_GET_INFO_PARAMS._fields_ = [ - ('tsgID', ctypes.c_uint32), -] - -NVA06C_CTRL_GET_INFO_PARAMS = struct_NVA06C_CTRL_GET_INFO_PARAMS -class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS._fields_ = [ - ('tsgInterleaveLevel', ctypes.c_uint32), -] - -NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS -NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS -NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS - -# values for enumeration 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE' -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE__enumvalues = { - 0: 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', - 1: 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', - 2: 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', -} -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = 0 -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = 1 -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = 2 -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE = ctypes.c_uint32 # enum -class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('size', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE), - ] - -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD -class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('l1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD), - ('t1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD), - ] - -NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS -class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS._fields_ = [ - ('methodBufferMemdesc', struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2), - ('bar2Addr', ctypes.c_uint64 * 2), - ('numValidEntries', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS -class struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS(Structure): - pass - -struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS._pack_ = 1 # source:False -struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS._fields_ = [ - ('bRealtime', ctypes.c_ubyte), -] - -NVA06C_CTRL_MAKE_REALTIME_PARAMS = struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS -NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS -NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS -__all__ = \ - ['ACCESS_COUNTER_NOTIFY_BUFFER', 'ACR_FALCON_LS_STATUS', - 'ACR_REGION_HANDLE', 'ACR_REGION_ID_PROP', 'ACR_REQUEST_PARAMS', - 'ACR_STATUS_PARAMS', 'ADA_A', 'ADA_COMPUTE_A', 'AMPERE_A', - 'AMPERE_B', 'AMPERE_CHANNEL_GPFIFO_A', 'AMPERE_COMPUTE_A', - 'AMPERE_COMPUTE_B', 'AMPERE_DMA_COPY_A', 'AMPERE_DMA_COPY_B', - 'AMPERE_SMC_CONFIG_SESSION', 'AMPERE_SMC_EXEC_PARTITION_REF', - 'AMPERE_SMC_MONITOR_SESSION', 'AMPERE_SMC_PARTITION_REF', - 'AMPERE_USERMODE_A', 'AmpereAControlGPFifo', 'BLACKWELL_A', - 'BLACKWELL_B', 'BLACKWELL_CHANNEL_GPFIFO_A', - 'BLACKWELL_CHANNEL_GPFIFO_B', 'BLACKWELL_COMPUTE_A', - 'BLACKWELL_COMPUTE_B', 'BLACKWELL_DMA_COPY_A', - 'BLACKWELL_DMA_COPY_B', 'BLACKWELL_INLINE_TO_MEMORY_A', - 'BLACKWELL_USERMODE_A', 'BindResultFunc', - 'BlackwellAControlGPFifo', 'CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES', - 'CC_CHAN_ALLOC_IV_SIZE_DWORD', 'CC_CHAN_ALLOC_NONCE_SIZE_DWORD', - 'CE_FIPS_SELF_TEST_AUTH_TAG_SIZE', 'CE_FIPS_SELF_TEST_DATA_SIZE', - 'CE_FIPS_SELF_TEST_IV_SIZE', 'CONTROLLER_FILTER_TYPE_EMWA', - 'CONTROLLER_FILTER_TYPE_MOVING_MAX', 'CTRL_CMD_FB_CBC_OP', - 'CTRL_CMD_FB_CBC_OP_CLEAN', 'CTRL_CMD_FB_CBC_OP_INVALIDATE', - 'Callback1ArgVoidReturn', 'Callback5ArgVoidReturn', - 'ChannelPBSize', 'ChannelPBSize__enumvalues', - 'FABRIC_MANAGER_SESSION', 'FABRIC_VASPACE_A', 'FALCON_ID_DPU', - 'FALCON_ID_FBFLCN', 'FALCON_ID_PMU', 'FALCON_ID_SEC2', - 'FERMI_CONTEXT_SHARE_A', 'FERMI_TWOD_A', 'FERMI_VASPACE_A', - 'FILE_DEVICE_NV', 'G84_PERFBUFFER', 'GF100_CHANNEL_GPFIFO', - 'GF100_DISP_SW', 'GF100_HDACODEC', 'GF100_PROFILER', - 'GF100_SUBDEVICE_INFOROM', 'GF100_SUBDEVICE_MASTER', - 'GF100_TIMED_SEMAPHORE_SW', 'GF100_ZBC_CLEAR', - 'GLOB_TYPE_APITEST', 'GLOB_TYPE_GET_NBSI_ACPI_RAW', - 'GLOB_TYPE_GET_NBSI_DIR', 'GMMU_FMT_MAX_LEVELS', 'GP100_UVM_SW', - 'GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE', 'GPS_MAX_COUNTERS_PER_BLOCK', - 'GPU_PART_NUMBER_FMT', 'GT200_DEBUGGER', 'GUEST_VM_INFO_STATE', - 'GUEST_VM_INFO_STATE_INITIALIZED', - 'GUEST_VM_INFO_STATE_UNINITIALIZED', 'HOPPER_A', - 'HOPPER_CHANNEL_GPFIFO_A', 'HOPPER_COMPUTE_A', - 'HOPPER_DMA_COPY_A', 'HOPPER_SEC2_WORK_LAUNCH_A', - 'HOPPER_USERMODE_A', 'HopperAControlGPFifo', 'IO_VASPACE_A', - 'KEPLER_CHANNEL_GPFIFO_A', 'KEPLER_CHANNEL_GPFIFO_B', - 'KEPLER_CHANNEL_GROUP_A', 'KEPLER_DEVICE_VGPU', - 'KEPLER_INLINE_TO_MEMORY_B', 'KERNEL_GRAPHICS_CONTEXT', - 'LOCK_STRESS_OBJECT', 'MAXWELL_CHANNEL_GPFIFO_A', - 'MAXWELL_DMA_COPY_A', 'MAXWELL_PROFILER', - 'MAXWELL_PROFILER_CONTEXT', 'MAXWELL_PROFILER_DEVICE', - 'MAX_ACCESS_MEMORY_OPS', 'MAX_ACCESS_OPS', - 'MAX_EDID_SIZE_FROM_SBIOS', 'MAX_GET_MAPPINGS_OPS', - 'MMU_FAULT_BUFFER', 'MMU_VIDMEM_ACCESS_BIT_BUFFER', 'MPS_COMPUTE', - 'NV0000_ALLOC_PARAMETERS', 'NV0000_ALLOC_PARAMETERS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT', - 'NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS', - 'NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS', - 'NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS', - 'NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS', - 'NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS', - 'NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS', - 'NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS', - 'NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM', - 'NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM', - 'NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE', - 'NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS', - 'NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID', - 'NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT', - 'NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES', - 'NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY', - 'NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT', - 'NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL', - 'NV0000_CTRL_CMD_DIAG_DUMP_RPC', - 'NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES', - 'NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE', - 'NV0000_CTRL_CMD_DIAG_PROFILE_RPC', - 'NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE', - 'NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION', - 'NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION', - 'NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS', - 'NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA', - 'NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS', - 'NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE', - 'NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO', - 'NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE', - 'NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID', - 'NV0000_CTRL_CMD_GPU_ATTACH_IDS', - 'NV0000_CTRL_CMD_GPU_DETACH_IDS', - 'NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT', - 'NV0000_CTRL_CMD_GPU_DISCOVER', - 'NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS', - 'NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS', - 'NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS', - 'NV0000_CTRL_CMD_GPU_GET_ID_INFO', - 'NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2', - 'NV0000_CTRL_CMD_GPU_GET_INIT_STATUS', - 'NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE', - 'NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE', - 'NV0000_CTRL_CMD_GPU_GET_PCI_INFO', - 'NV0000_CTRL_CMD_GPU_GET_PROBED_IDS', - 'NV0000_CTRL_CMD_GPU_GET_SVM_SIZE', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1', - 'NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1', - 'NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256', - 'NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS', - 'NV0000_CTRL_CMD_GPU_LEGACY_CONFIG', - 'NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE', - 'NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET', - 'NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE', - 'NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE', - 'NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE', - 'NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID', - 'NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS', - 'NV0000_CTRL_CMD_GSYNC_GET_ID_INFO', - 'NV0000_CTRL_CMD_IDLE_CHANNELS', 'NV0000_CTRL_CMD_NULL', - 'NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS', - 'NV0000_CTRL_CMD_NVD_GET_DUMP', - 'NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE', - 'NV0000_CTRL_CMD_NVD_GET_NVLOG', - 'NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO', - 'NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO', - 'NV0000_CTRL_CMD_NVD_GET_RCERR_RPT', - 'NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS', - 'NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_NVD_GET_TIMESTAMP', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS', - 'NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST', - 'NV0000_CTRL_CMD_OS_GET_GPU_INFO', - 'NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD', - 'NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD', - 'NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD', - 'NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE', - 'NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR', - 'NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM', - 'NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM', - 'NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST', - 'NV0000_CTRL_CMD_PUSH_UCODE_IMAGE', - 'NV0000_CTRL_CMD_SET_SUB_PROCESS_ID', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO', - 'NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO', - 'NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS', - 'NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD', - 'NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION', - 'NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2', - 'NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST', - 'NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS', - 'NV0000_CTRL_CMD_SYSTEM_GET_FEATURES', - 'NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS', - 'NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES', - 'NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS', - 'NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX', - 'NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2', - 'NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE', - 'NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS', - 'NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS', - 'NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID', - 'NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID', - 'NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX', - 'NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT', - 'NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO', - 'NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS', - 'NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE', - 'NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET', - 'NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL', - 'NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS', - 'NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT', - 'NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS', - 'NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_CMD_VGPU_CREATE_DEVICE', - 'NV0000_CTRL_CMD_VGPU_DELETE_DEVICE', - 'NV0000_CTRL_CMD_VGPU_GET_INSTANCES', - 'NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS', 'NV0000_CTRL_DIAG', - 'NV0000_CTRL_DIAG_DUMP_RPC_PARAMS', - 'NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS', - 'NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_LOCK_METER_ENTRY', - 'NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH', - 'NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA', - 'NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP', - 'NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS', - 'NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_RPC_MAX_ENTRIES', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET', - 'NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS', - 'NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_EVENT', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS', - 'NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', - 'NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', - 'NV0000_CTRL_GPS_CMD_PS_STATUS_OFF', - 'NV0000_CTRL_GPS_CMD_PS_STATUS_ON', - 'NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PPM', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PPM', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT', - 'NV0000_CTRL_GPS_INPUT_ACPI_CMD', - 'NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN', - 'NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL', - 'NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_INPUT_SENSOR_INDEX', - 'NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP', - 'NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_GPS_INPUT_TEMP_PERIOD', - 'NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1', - 'NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2', - 'NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE', - 'NV0000_CTRL_GPS_PPM_INDEX_BALANCED', - 'NV0000_CTRL_GPS_PPM_INDEX_INVALID', - 'NV0000_CTRL_GPS_PPM_INDEX_MAXPERF', - 'NV0000_CTRL_GPS_PPM_INDEX_QUIET', - 'NV0000_CTRL_GPS_PPM_MASK_INVALID', - 'NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION', - 'NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE', - 'NV0000_CTRL_GPS_RESULT_MAX_LIMIT', - 'NV0000_CTRL_GPS_RESULT_MIN_LIMIT', - 'NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE', - 'NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP', - 'NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_GPS_RESULT_TEMP_PERIOD', - 'NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT', 'NV0000_CTRL_GPU', - 'NV0000_CTRL_GPUACCT', - 'NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS', - 'NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS', - 'NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS', - 'NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS', - 'NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED', - 'NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED', - 'NV0000_CTRL_GPU_ACTIVE_DEVICE', - 'NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS', - 'NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS', - 'NV0000_CTRL_GPU_ATTACH_IDS_PARAMS', - 'NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS', - 'NV0000_CTRL_GPU_DETACH_IDS_PARAMS', - 'NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS', - 'NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_DISCOVER_PARAMS', - 'NV0000_CTRL_GPU_DRAIN_STATE_DISABLED', - 'NV0000_CTRL_GPU_DRAIN_STATE_ENABLED', - 'NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE', - 'NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE', - 'NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE', - 'NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_ID_INFO_PARAMS', - 'NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS', - 'NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS', - 'NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS', - 'NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS', - 'NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS', - 'NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS', - 'NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS', - 'NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS', - 'NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS', - 'NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS', - 'NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS', - 'NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE', - 'NV0000_CTRL_GPU_ID_INFO_SOC_FALSE', - 'NV0000_CTRL_GPU_ID_INFO_SOC_TRUE', - 'NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE', - 'NV0000_CTRL_GPU_IMAGE_TYPE_GSP', - 'NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG', - 'NV0000_CTRL_GPU_INVALID_ID', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS', - 'NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES', - 'NV0000_CTRL_GPU_MAX_ATTACHED_GPUS', 'NV0000_CTRL_GPU_MAX_SZNAME', - 'NV0000_CTRL_GPU_MAX_VIDEO_LINKS', - 'NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS', - 'NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS', - 'NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS', - 'NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS', - 'NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS', - 'NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GPU_VIDEO_LINKS', - 'NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS', - 'NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GSYNC', 'NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS', - 'NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS', - 'NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_GSYNC_INVALID_ID', 'NV0000_CTRL_NO_NUMA_NODE', - 'NV0000_CTRL_NVD', 'NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG', - 'NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED', - 'NV0000_CTRL_NVD_DUMP_COMPONENT_SYS', - 'NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS', - 'NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_DUMP_PARAMS', - 'NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS', - 'NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS', - 'NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_NVLOG_PARAMS', - 'NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS', - 'NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_NVD_MAX_BUFFERS', 'NV0000_CTRL_NVD_MAX_DUMP_SIZE', - 'NV0000_CTRL_NVD_MAX_RUNTIME_SIZES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP', - 'NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64', - 'NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_INT', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_PTR', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_STRING', - 'NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED', - 'NV0000_CTRL_NVD_SIGNATURE_SIZE', - 'NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE', - 'NV0000_CTRL_OS_GET_GPU_INFO_PARAMS', 'NV0000_CTRL_OS_MACOS', - 'NV0000_CTRL_OS_UNIX', - 'NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE', - 'NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', - 'NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', - 'NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH', - 'NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE', - 'NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE', - 'NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS', - 'NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS', - 'NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS', - 'NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS', - 'NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_OS_WINDOWS', 'NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS', - 'NV0000_CTRL_P2P_CAPS_INDEX_C2C', - 'NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK', - 'NV0000_CTRL_P2P_CAPS_INDEX_NVLINK', - 'NV0000_CTRL_P2P_CAPS_INDEX_PCI', - 'NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1', - 'NV0000_CTRL_P2P_CAPS_INDEX_PROP', - 'NV0000_CTRL_P2P_CAPS_INDEX_READ', - 'NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE', - 'NV0000_CTRL_P2P_CAPS_INDEX_WRITE', - 'NV0000_CTRL_P2P_CAPS_MATRIX_ROW', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES', - 'NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2', - 'NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET', - 'NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID', - 'NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP', - 'NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT', - 'NV0000_CTRL_PROC', 'NV0000_CTRL_PROFILE_RPC_CMD_DISABLE', - 'NV0000_CTRL_PROFILE_RPC_CMD_ENABLE', - 'NV0000_CTRL_PROFILE_RPC_CMD_RESET', 'NV0000_CTRL_RESERVED', - 'NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS', - 'NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED', - 'NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT', - 'NV0000_CTRL_SLI_STATUS_OK', - 'NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED', 'NV0000_CTRL_SWINSTR', - 'NV0000_CTRL_SYNC_GPU_BOOST', 'NV0000_CTRL_SYSTEM', - 'NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO', - 'NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES', - 'NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW', - 'NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT', - 'NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC', - 'NV0000_CTRL_SYSTEM_CPU_CAP_AVX', - 'NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH', - 'NV0000_CTRL_SYSTEM_CPU_CAP_CMOV', - 'NV0000_CTRL_SYSTEM_CPU_CAP_ERMS', - 'NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE', - 'NV0000_CTRL_SYSTEM_CPU_CAP_MMX', - 'NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT', - 'NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888', - 'NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854', - 'NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND', - 'NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE2', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE3', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE41', - 'NV0000_CTRL_SYSTEM_CPU_CAP_SSE42', - 'NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL', - 'NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_C6', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_C62', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CELA', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_GX', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K10', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K11', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K5', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K6', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K62', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K63', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K7', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_K8', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_M1', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_M2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_MGX', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P3', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P4', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P5', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P55', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_P6', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN', - 'NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE', - 'NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS', - 'NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL', - 'NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK', - 'NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS', - 'NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE', - 'NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE', - 'NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE', - 'NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA', - 'NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG', - 'NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG', - 'NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT', - 'NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS', - 'NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE', - 'NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE', - 'NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED', - 'NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED', - 'NV0000_CTRL_SYSTEM_HWBC_INFO', - 'NV0000_CTRL_SYSTEM_HWBC_INVALID_ID', - 'NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS', - 'NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED', - 'NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE', - 'NV0000_CTRL_SYSTEM_MAX_HWBCS', - 'NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS', - 'NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS', - 'NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS', - 'NV0000_CTRL_SYSTEM_PARAM_COUNT', 'NV0000_CTRL_SYSTEM_PARAM_CPUE', - 'NV0000_CTRL_SYSTEM_PARAM_CTGP', 'NV0000_CTRL_SYSTEM_PARAM_PDTS', - 'NV0000_CTRL_SYSTEM_PARAM_PPMD', 'NV0000_CTRL_SYSTEM_PARAM_SFAN', - 'NV0000_CTRL_SYSTEM_PARAM_SKNT', 'NV0000_CTRL_SYSTEM_PARAM_TGPU', - 'NV0000_CTRL_SYSTEM_PARAM_TMP1', 'NV0000_CTRL_SYSTEM_PARAM_TMP2', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS', - 'NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS', - 'NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI', - 'NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM', - 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE', - 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', - 'NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', 'NV0000_CTRL_VGPU', - 'NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS', - 'NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS', - 'NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS', - 'NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_GET_VGPU_VERSION', - 'NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS', - 'NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_SET_VGPU_VERSION', - 'NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS', - 'NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID', - 'NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS', - 'NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID', - 'NV0000_GPUACCT_PID_MAX_COUNT', 'NV0000_GPU_MAX_GID_LENGTH', - 'NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT', - 'NV0000_NVD_CPU_TIME_CLK_ID_OSTIME', - 'NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API', - 'NV0000_NVD_CPU_TIME_CLK_ID_TSC', - 'NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE', - 'NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY', - 'NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED', - 'NV0000_P2P_CAPS_STATUS_OK', 'NV0000_SYNC_GPU_BOOST_GROUP_CONFIG', - 'NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS', - 'NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS', - 'NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS', - 'NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_INFO_PARAMS', - 'NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID', - 'NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID', - 'NV0000_SYNC_GPU_BOOST_MAX_GROUPS', - 'NV0000_SYSTEM_CHIPSET_INVALID_ID', - 'NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH', - 'NV0020_GPU_MANAGEMENT', 'NV0060_SYNC_GPU_BOOST', - 'NV0080_ALLOC_PARAMETERS', 'NV0080_ALLOC_PARAMETERS_MESSAGE_ID', - 'NV0080_CTRL_BIF', 'NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS', - 'NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED', - 'NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR', - 'NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET', - 'NV0080_CTRL_BIF_RESET_PARAMS', - 'NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS', - 'NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BSP', 'NV0080_CTRL_BSP_CAPS_TBL_SIZE', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2', - 'NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID', - 'NV0080_CTRL_CIPHER', 'NV0080_CTRL_CLK', - 'NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE', - 'NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK', - 'NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS', - 'NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_CMD_BIF_RESET', - 'NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE', - 'NV0080_CTRL_CMD_BSP_GET_CAPS', 'NV0080_CTRL_CMD_BSP_GET_CAPS_V2', - 'NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS', - 'NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO', - 'NV0080_CTRL_CMD_DMA_FILL_PTE_MEM', 'NV0080_CTRL_CMD_DMA_FLUSH', - 'NV0080_CTRL_CMD_DMA_GET_CAPS', - 'NV0080_CTRL_CMD_DMA_GET_PDE_INFO', - 'NV0080_CTRL_CMD_DMA_GET_PTE_INFO', - 'NV0080_CTRL_CMD_DMA_INVALIDATE_TLB', - 'NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY', - 'NV0080_CTRL_CMD_DMA_SET_PTE_INFO', - 'NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE', - 'NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY', - 'NV0080_CTRL_CMD_DMA_UPDATE_PDE_2', 'NV0080_CTRL_CMD_FB_GET_CAPS', - 'NV0080_CTRL_CMD_FB_GET_CAPS_V2', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY', - 'NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE', - 'NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY', - 'NV0080_CTRL_CMD_FIFO_GET_CAPS', - 'NV0080_CTRL_CMD_FIFO_GET_CAPS_V2', - 'NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST', - 'NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES', - 'NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE', - 'NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS', - 'NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS', - 'NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST', - 'NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE', - 'NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS', - 'NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES', - 'NV0080_CTRL_CMD_FIFO_START_RUNLIST', - 'NV0080_CTRL_CMD_FIFO_STOP_RUNLIST', - 'NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE', - 'NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS', - 'NV0080_CTRL_CMD_GPU_GET_CLASSLIST', - 'NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2', - 'NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER', - 'NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES', - 'NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE', - 'NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS', - 'NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE', - 'NV0080_CTRL_CMD_GPU_GET_VGX_CAPS', - 'NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER', - 'NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE', - 'NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE', - 'NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE', - 'NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER', - 'NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE', - 'NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE', - 'NV0080_CTRL_CMD_GPU_SET_VIDLINK', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP', - 'NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON', - 'NV0080_CTRL_CMD_GR_GET_CAPS', 'NV0080_CTRL_CMD_GR_GET_CAPS_V2', - 'NV0080_CTRL_CMD_GR_GET_INFO', 'NV0080_CTRL_CMD_GR_GET_INFO_V2', - 'NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_HOST_GET_CAPS', - 'NV0080_CTRL_CMD_HOST_GET_CAPS_V2', - 'NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS', - 'NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS', - 'NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE', - 'NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS', - 'NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE', - 'NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL', - 'NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL', - 'NV0080_CTRL_CMD_MSENC_GET_CAPS', - 'NV0080_CTRL_CMD_MSENC_GET_CAPS_V2', 'NV0080_CTRL_CMD_NULL', - 'NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2', - 'NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO', - 'NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH', - 'NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL', 'NV0080_CTRL_DMA', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS', - 'NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_CAPS_TBL_SIZE', - 'NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE', - 'NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS', - 'NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS', - 'NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_FLUSH_PARAMS', - 'NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM', - 'NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM', - 'NV0080_CTRL_DMA_GET_CAPS_PARAMS', - 'NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS', - 'NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK', - 'NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE', - 'NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE', - 'NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK', - 'NV0080_CTRL_DMA_SET_DEFAULT_VASPACE', - 'NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS', - 'NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS', - 'NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS', - 'NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS', - 'NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX', - 'NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS', - 'NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS', - 'NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL', - 'NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE', 'NV0080_CTRL_FB', - 'NV0080_CTRL_FB_CAPS_TBL_SIZE', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', - 'NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', - 'NV0080_CTRL_FB_GET_CAPS_PARAMS', - 'NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FB_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS', - 'NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS', - 'NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO', 'NV0080_CTRL_FIFO_CAPS_TBL_SIZE', - 'NV0080_CTRL_FIFO_GET_CAPS_PARAMS', - 'NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL', - 'NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS', - 'NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS', - 'NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS', - 'NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS', - 'NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM', - 'NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM', - 'NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS', - 'NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT', - 'NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT', - 'NV0080_CTRL_FIFO_START_RUNLIST_PARAMS', - 'NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS', - 'NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU', 'NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE', - 'NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM', - 'NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS', - 'NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS', - 'NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS', - 'NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS', - 'NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS', - 'NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS', - 'NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS', - 'NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS', - 'NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS', - 'NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS', - 'NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS', - 'NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS', - 'NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE', - 'NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS', - 'NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE', - 'NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE', - 'NV0080_CTRL_GPU_SET_VIDLINK_PARAMS', - 'NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT', - 'NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE', - 'NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE', - 'NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED', - 'NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED', - 'NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX', - 'NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE', - 'NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX', 'NV0080_CTRL_GR', - 'NV0080_CTRL_GR_CAPS_TBL_SIZE', 'NV0080_CTRL_GR_GET_CAPS_PARAMS', - 'NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_INFO_PARAMS', - 'NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_INFO_V2_PARAMS', - 'NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS', - 'NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_INFO', - 'NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT', - 'NV0080_CTRL_GR_INFO_INDEX_DUMMY', - 'NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY', - 'NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES', - 'NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES', - 'NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES', - 'NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC', - 'NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS', - 'NV0080_CTRL_GR_INFO_INDEX_MAX', - 'NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP', - 'NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM', - 'NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894', - 'NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_SM_VERSION', - 'NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT', - 'NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT', - 'NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR', - 'NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED', - 'NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE', - 'NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT', - 'NV0080_CTRL_GR_INFO_MAX_SIZE', - 'NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK', - 'NV0080_CTRL_GR_ROUTE_INFO', - 'NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS', - 'NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS', - 'NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', 'NV0080_CTRL_HOST', - 'NV0080_CTRL_HOST_CAPS_TBL_SIZE', - 'NV0080_CTRL_HOST_GET_CAPS_PARAMS', - 'NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_INTERNAL', - 'NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS', - 'NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_MSENC', 'NV0080_CTRL_MSENC_CAPS_TBL_SIZE', - 'NV0080_CTRL_MSENC_GET_CAPS_PARAMS', - 'NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_NVJPG', 'NV0080_CTRL_NVJPG_CAPS_TBL_SIZE', - 'NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS', - 'NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_NVLINK', 'NV0080_CTRL_OS_UNIX', - 'NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS', - 'NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS', - 'NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_PERF', 'NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS', - 'NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED', - 'NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID', - 'NV0080_CTRL_RC', 'NV0080_CTRL_RESERVED', 'NV0080_CTRL_VIDEO', - 'NV0092_RG_LINE_CALLBACK', 'NV01_ALLOC_MEMORY', - 'NV01_ALLOC_OBJECT', 'NV01_CONTEXT_DMA', 'NV01_DEVICE_0', - 'NV01_EVENT', 'NV01_EVENT_BROADCAST', 'NV01_EVENT_CLIENT_RM', - 'NV01_EVENT_KERNEL_CALLBACK', 'NV01_EVENT_KERNEL_CALLBACK_EX', - 'NV01_EVENT_NONSTALL_INTR', 'NV01_EVENT_OS_EVENT', - 'NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION', - 'NV01_EVENT_SUBDEVICE_SPECIFIC', 'NV01_EVENT_WIN32_EVENT', - 'NV01_EVENT_WITHOUT_EVENT_DATA', 'NV01_FREE', - 'NV01_MEMORY_DEVICELESS', 'NV01_MEMORY_FLA', - 'NV01_MEMORY_FRAMEBUFFER_CONSOLE', 'NV01_MEMORY_HW_RESOURCES', - 'NV01_MEMORY_LIST_FBMEM', 'NV01_MEMORY_LIST_OBJECT', - 'NV01_MEMORY_LIST_SYSTEM', 'NV01_MEMORY_LOCAL_PHYSICAL', - 'NV01_MEMORY_LOCAL_PRIVILEGED', 'NV01_MEMORY_LOCAL_USER', - 'NV01_MEMORY_PRIVILEGED', 'NV01_MEMORY_SYNCPOINT', - 'NV01_MEMORY_SYSTEM', 'NV01_MEMORY_SYSTEM_DYNAMIC', - 'NV01_MEMORY_SYSTEM_OS_DESCRIPTOR', 'NV01_MEMORY_USER', - 'NV01_MEMORY_VIRTUAL', 'NV01_NULL', 'NV01_NULL_OBJECT', - 'NV01_ROOT', 'NV01_ROOT_CLIENT', 'NV01_ROOT_NON_PRIV', - 'NV01_ROOT_USER', 'NV01_TIMER', 'NV04_ACCESS_REGISTRY', - 'NV04_ADD_VBLANK_CALLBACK', 'NV04_ALLOC', - 'NV04_ALLOC_CONTEXT_DMA', 'NV04_BIND_CONTEXT_DMA', 'NV04_CONTROL', - 'NV04_DISPLAY_COMMON', 'NV04_DUP_HANDLE_FLAGS_NONE', - 'NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE', - 'NV04_DUP_OBJECT', 'NV04_GET_EVENT_DATA', 'NV04_I2C_ACCESS', - 'NV04_IDLE_CHANNELS', 'NV04_MAP_MEMORY', 'NV04_MAP_MEMORY_DMA', - 'NV04_MAP_MEMORY_FLAGS_NONE', 'NV04_MAP_MEMORY_FLAGS_USER', - 'NV04_SHARE', 'NV04_SOFTWARE_TEST', 'NV04_UNMAP_MEMORY', - 'NV04_UNMAP_MEMORY_DMA', 'NV04_UPDATE_DEVICE_MAPPING_INFO', - 'NV04_VID_HEAP_CONTROL', 'NV1_EVENT', 'NV1_EVENT_KERNEL_CALLBACK', - 'NV1_EVENT_KERNEL_CALLBACK_EX', 'NV1_EVENT_OS_EVENT', - 'NV1_EVENT_WIN32_EVENT', 'NV1_MEMORY_LOCAL_PRIVILEGED', - 'NV1_MEMORY_LOCAL_USER', 'NV1_MEMORY_PRIVILEGED', - 'NV1_MEMORY_SYSTEM', 'NV1_MEMORY_SYSTEM_DYNAMIC', - 'NV1_MEMORY_USER', 'NV1_NULL', 'NV1_NULL_OBJECT', 'NV1_ROOT', - 'NV1_ROOT_NON_PRIV', 'NV1_TIMER', - 'NV2080CtrlNocatJournalDataTdrReason', - 'NV2080CtrlNocatJournalInsertRecord', - 'NV2080CtrlNocatJournalRclog', 'NV2080CtrlNocatJournalSetTag', - 'NV2080_ALLOC_PARAMETERS', 'NV2080_ALLOC_PARAMETERS_MESSAGE_ID', - 'NV2080_BIOS_GET_NBSI_MAX_RET_SIZE', - 'NV2080_CLIENT_TYPE_ALLCLIENTS', 'NV2080_CLIENT_TYPE_COLOR', - 'NV2080_CLIENT_TYPE_DA', 'NV2080_CLIENT_TYPE_DEPTH', - 'NV2080_CLIENT_TYPE_FE', 'NV2080_CLIENT_TYPE_MSPDEC', - 'NV2080_CLIENT_TYPE_MSPPP', 'NV2080_CLIENT_TYPE_MSVLD', - 'NV2080_CLIENT_TYPE_SCC', 'NV2080_CLIENT_TYPE_TEX', - 'NV2080_CLIENT_TYPE_VIC', 'NV2080_CLIENT_TYPE_WID', - 'NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC', - 'NV2080_CTRL_ACPI_DSM_READ_SIZE', 'NV2080_CTRL_ACR', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS', - 'NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS', - 'NV2080_CTRL_BIF', 'NV2080_CTRL_BIOS', - 'NV2080_CTRL_BIOS_GET_INFO_PARAMS', - 'NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS', - 'NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH', - 'NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE', - 'NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE', - 'NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND', - 'NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE', - 'NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS', - 'NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE', - 'NV2080_CTRL_BIOS_GET_NBSI_PARAMS', - 'NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_NBSI_SUCCESS', - 'NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS', - 'NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS', - 'NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS', - 'NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BIOS_INFO', - 'NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION', - 'NV2080_CTRL_BIOS_INFO_INDEX_REVISION', - 'NV2080_CTRL_BIOS_INFO_MAX_SIZE', - 'NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH', - 'NV2080_CTRL_BIOS_NBSI_MODULE_CPL', - 'NV2080_CTRL_BIOS_NBSI_MODULE_D3D', - 'NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER', - 'NV2080_CTRL_BIOS_NBSI_MODULE_MODE', - 'NV2080_CTRL_BIOS_NBSI_MODULE_OGL', - 'NV2080_CTRL_BIOS_NBSI_MODULE_PMU', - 'NV2080_CTRL_BIOS_NBSI_MODULE_RM', - 'NV2080_CTRL_BIOS_NBSI_MODULE_ROOT', - 'NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN', - 'NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO', - 'NV2080_CTRL_BIOS_NBSI_NUM_MODULES', - 'NV2080_CTRL_BIOS_NBSI_REG_STRING', - 'NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII', - 'NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH', - 'NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE', - 'NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE', - 'NV2080_CTRL_BUS', 'NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS', - 'NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_BFD_PARAMS', - 'NV2080_CTRL_BUS_GET_BFD_PARAMSARR', - 'NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU', - 'NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU', - 'NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS', - 'NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_BUS_GET_INFO_PARAMS', - 'NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS', - 'NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS', - 'NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS', - 'NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS', - 'NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_INFO', - 'NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED', - 'NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE', - 'NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE', - 'NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE', - 'NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER', - 'NV2080_CTRL_BUS_INFO_INDEX_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS', - 'NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER', - 'NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI', - 'NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE', - 'NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE', - 'NV2080_CTRL_BUS_INFO_INDEX_INTLINE', - 'NV2080_CTRL_BUS_INFO_INDEX_MAX', - 'NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS', - 'NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK', - 'NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE', - 'NV2080_CTRL_BUS_INFO_INDEX_TYPE', - 'NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE', - 'NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED', - 'NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE', - 'NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO', - 'NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR', - 'NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST', - 'NV2080_CTRL_BUS_INFO_TYPE_AXI', 'NV2080_CTRL_BUS_INFO_TYPE_FPCI', - 'NV2080_CTRL_BUS_INFO_TYPE_PCI', - 'NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS', - 'NV2080_CTRL_BUS_MAP_BAR2_PARAMS', - 'NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_MAX_NUM_GPUS', 'NV2080_CTRL_BUS_MAX_NUM_LANES', - 'NV2080_CTRL_BUS_MAX_PCI_BARS', - 'NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO', - 'NV2080_CTRL_BUS_PCI_BAR_INFO', - 'NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR', - 'NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE', - 'NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS', - 'NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT', - 'NV2080_CTRL_BUS_PEX_COUNTER_TYPE', - 'NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0', - 'NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S', - 'NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS', - 'NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS', - 'NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS', - 'NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS', - 'NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS', - 'NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS', - 'NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS', - 'NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS', - 'NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID', 'NV2080_CTRL_CE', - 'NV2080_CTRL_CE_CAPS_TBL_SIZE', - 'NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_CAPS_V2_PARAMS', - 'NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS', - 'NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS', - 'NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS', - 'NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS', - 'NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS', - 'NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS', - 'NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_LCE_TYPE', 'NV2080_CTRL_CE_LCE_TYPE_C2C', - 'NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', - 'NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', - 'NV2080_CTRL_CE_LCE_TYPE_DECOMP', - 'NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', - 'NV2080_CTRL_CE_LCE_TYPE_PCIE', 'NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', - 'NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', - 'NV2080_CTRL_CE_LCE_TYPE_SCRUB', 'NV2080_CTRL_CE_MAX_HSHUBS', - 'NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS', - 'NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS', - 'NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS', - 'NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CIPHER', 'NV2080_CTRL_CLK', - 'NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_CLK_LEGACY_PRIVILEGED', - 'NV2080_CTRL_CMD_BIOS_GET_INFO', - 'NV2080_CTRL_CMD_BIOS_GET_INFO_V2', - 'NV2080_CTRL_CMD_BIOS_GET_NBSI', - 'NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ', - 'NV2080_CTRL_CMD_BIOS_GET_NBSI_V2', - 'NV2080_CTRL_CMD_BIOS_GET_POST_TIME', - 'NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS', - 'NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BIOS_GET_SKU_INFO', - 'NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT', - 'NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS', - 'NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS', - 'NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS', - 'NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS', - 'NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS', - 'NV2080_CTRL_CMD_BUS_GET_BFD', 'NV2080_CTRL_CMD_BUS_GET_C2C_INFO', - 'NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_EOM_STATUS', - 'NV2080_CTRL_CMD_BUS_GET_INFO', 'NV2080_CTRL_CMD_BUS_GET_INFO_V2', - 'NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO', - 'NV2080_CTRL_CMD_BUS_GET_PCI_INFO', - 'NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS', - 'NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE', - 'NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS', - 'NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_MAP_BAR2', - 'NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU', - 'NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P', - 'NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM', - 'NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE', - 'NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS', - 'NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS', - 'NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE', - 'NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED', - 'NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS', - 'NV2080_CTRL_CMD_BUS_UNMAP_BAR2', - 'NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING', - 'NV2080_CTRL_CMD_BUS_VERIFY_BAR2', - 'NV2080_CTRL_CMD_CE_GET_ALL_CAPS', - 'NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS', - 'NV2080_CTRL_CMD_CE_GET_CAPS', 'NV2080_CTRL_CMD_CE_GET_CAPS_V2', - 'NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK', - 'NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK', - 'NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE', - 'NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK', - 'NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2', - 'NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO', - 'NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS', - 'NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED', - 'NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG', - 'NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB', - 'NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS', - 'NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2', - 'NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD', - 'NV2080_CTRL_CMD_DMA_GET_INFO', - 'NV2080_CTRL_CMD_DMA_INVALIDATE_TLB', - 'NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS', - 'NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS', - 'NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF', - 'NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI', - 'NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES', - 'NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION', - 'NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY', - 'NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION', - 'NV2080_CTRL_CMD_EVENT_SET_TRIGGER', - 'NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO', - 'NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF', - 'NV2080_CTRL_CMD_FB_ACR_CLIENT_ID', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', - 'NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM', - 'NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM', - 'NV2080_CTRL_CMD_FB_ALLOCATION_INFO', - 'NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE', - 'NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS', - 'NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_CBC_OP', 'NV2080_CTRL_CMD_FB_CBC_OP_PARAMS', - 'NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_CLIENT_INFO', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB', - 'NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS', - 'NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_FREE_TILE', - 'NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS', - 'NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_AMAP_CONF', - 'NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET', - 'NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED', - 'NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE', - 'NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET', - 'NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR', - 'NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO', - 'NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION', - 'NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG', - 'NV2080_CTRL_CMD_FB_GET_FS_INFO', - 'NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO', - 'NV2080_CTRL_CMD_FB_GET_INFO', 'NV2080_CTRL_CMD_FB_GET_INFO_V2', - 'NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP', - 'NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT', - 'NV2080_CTRL_CMD_FB_GET_NUMA_INFO', - 'NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES', - 'NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS', - 'NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM', - 'NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT', - 'NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO', - 'NV2080_CTRL_CMD_FB_GET_STATUS', 'NV2080_CTRL_CMD_FB_IS_KIND', - 'NV2080_CTRL_CMD_FB_OFFLINE_PAGES', - 'NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING', - 'NV2080_CTRL_CMD_FB_QUERY_ACR_REGION', - 'NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS', - 'NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED', - 'NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED', - 'NV2080_CTRL_CMD_FB_SETUP_VPR_REGION', - 'NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS', - 'NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION', - 'NV2080_CTRL_CMD_FB_SET_READ_LIMIT', 'NV2080_CTRL_CMD_FB_SET_RRD', - 'NV2080_CTRL_CMD_FB_SET_VPR', - 'NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT', - 'NV2080_CTRL_CMD_FB_STATS_ENTRY', 'NV2080_CTRL_CMD_FB_STATS_GET', - 'NV2080_CTRL_CMD_FB_STATS_GET_PARAMS', - 'NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FB_STATS_MAX_OWNER', - 'NV2080_CTRL_CMD_FB_STATS_OWNER_INFO', - 'NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS', - 'NV2080_CTRL_CMD_FB_VPR_ERROR_CODE', - 'NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', - 'NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', - 'NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE', - 'NV2080_CTRL_CMD_FIFO_BIND_ENGINES', - 'NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL', - 'NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT', - 'NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS', - 'NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS', - 'NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION', - 'NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2', - 'NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS', - 'NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS', - 'NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE', - 'NV2080_CTRL_CMD_FIFO_GET_INFO', - 'NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS', - 'NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE', - 'NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG', - 'NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID', - 'NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY', - 'NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE', - 'NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE', - 'NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB', - 'NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO', - 'NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS', - 'NV2080_CTRL_CMD_FLA_GET_RANGE', 'NV2080_CTRL_CMD_FLA_RANGE', - 'NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK', - 'NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO', - 'NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE', - 'NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE', - 'NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH', - 'NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET', - 'NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET', - 'NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO', - 'NV2080_CTRL_CMD_GC6_ENTRY', 'NV2080_CTRL_CMD_GC6_EXIT', - 'NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO', - 'NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GET_P2P_CAPS', 'NV2080_CTRL_CMD_GET_RC_INFO', - 'NV2080_CTRL_CMD_GET_RC_RECOVERY', - 'NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', - 'NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', - 'NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION', - 'NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS', - 'NV2080_CTRL_CMD_GPU_EVICT_CTX', - 'NV2080_CTRL_CMD_GPU_EXEC_REG_OPS', - 'NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS', - 'NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU', - 'NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS', - 'NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU', - 'NV2080_CTRL_CMD_GPU_GET_CACHED_INFO', - 'NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS', - 'NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG', - 'NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES', - 'NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY', - 'NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO', - 'NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS', - 'NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY', - 'NV2080_CTRL_CMD_GPU_GET_ENGINES', - 'NV2080_CTRL_CMD_GPU_GET_ENGINES_V2', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST', - 'NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE', - 'NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO', - 'NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO', - 'NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO', - 'NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX', - 'NV2080_CTRL_CMD_GPU_GET_GFID', - 'NV2080_CTRL_CMD_GPU_GET_GID_INFO', - 'NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE', - 'NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID', - 'NV2080_CTRL_CMD_GPU_GET_ID', - 'NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING', - 'NV2080_CTRL_CMD_GPU_GET_ILLUM', 'NV2080_CTRL_CMD_GPU_GET_INFO', - 'NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION', - 'NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION', - 'NV2080_CTRL_CMD_GPU_GET_INFO_V2', - 'NV2080_CTRL_CMD_GPU_GET_IP_VERSION', - 'NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE', - 'NV2080_CTRL_CMD_GPU_GET_NAME_STRING', - 'NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC', - 'NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO', - 'NV2080_CTRL_CMD_GPU_GET_OEM_INFO', - 'NV2080_CTRL_CMD_GPU_GET_PARTITIONS', - 'NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY', - 'NV2080_CTRL_CMD_GPU_GET_PES_INFO', - 'NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT', - 'NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO', - 'NV2080_CTRL_CMD_GPU_GET_PIDS', - 'NV2080_CTRL_CMD_GPU_GET_PID_INFO', - 'NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION', - 'NV2080_CTRL_CMD_GPU_GET_RESET_STATUS', - 'NV2080_CTRL_CMD_GPU_GET_SDM', - 'NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING', - 'NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO', - 'NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK', - 'NV2080_CTRL_CMD_GPU_GET_VF_CAPS', - 'NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE', - 'NV2080_CTRL_CMD_GPU_GET_VPR_CAPS', - 'NV2080_CTRL_CMD_GPU_GET_VPR_INFO', - 'NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL', - 'NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE', - 'NV2080_CTRL_CMD_GPU_ILLUM_PARAMS', - 'NV2080_CTRL_CMD_GPU_INITIALIZE_CTX', - 'NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET', - 'NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET', - 'NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS', - 'NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP', - 'NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU', - 'NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP', - 'NV2080_CTRL_CMD_GPU_PROMOTE_CTX', - 'NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES', - 'NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION', - 'NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR', - 'NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS', - 'NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS', - 'NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS', - 'NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT', - 'NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS', - 'NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT', - 'NV2080_CTRL_CMD_GPU_QUERY_MODE', - 'NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS', - 'NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT', - 'NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS', - 'NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES', - 'NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION', - 'NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR', - 'NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR', - 'NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE', - 'NV2080_CTRL_CMD_GPU_SET_ILLUM', - 'NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE', - 'NV2080_CTRL_CMD_GPU_SET_PARTITIONS', - 'NV2080_CTRL_CMD_GPU_SET_POWER', 'NV2080_CTRL_CMD_GPU_SET_SDM', - 'NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET', - 'NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET', - 'NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY', - 'NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS', - 'NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST', - 'NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT', - 'NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO', - 'NV2080_CTRL_CMD_GR_CTXSW_PM_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_PM_MODE', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', - 'NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', - 'NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE', - 'NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND', - 'NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE', - 'NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID', - 'NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2', - 'NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE', - 'NV2080_CTRL_CMD_GR_GET_CAPS_V2', - 'NV2080_CTRL_CMD_GR_GET_CTXSW_MODES', - 'NV2080_CTRL_CMD_GR_GET_CTXSW_STATS', - 'NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO', - 'NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE', - 'NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL', - 'NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES', - 'NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO', - 'NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER', - 'NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT', - 'NV2080_CTRL_CMD_GR_GET_GPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP', - 'NV2080_CTRL_CMD_GR_GET_INFO', 'NV2080_CTRL_CMD_GR_GET_INFO_V2', - 'NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC', - 'NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_PPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_ROP_INFO', - 'NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER', - 'NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS', - 'NV2080_CTRL_CMD_GR_GET_TPC_MASK', - 'NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK', - 'NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA', - 'NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT', - 'NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT', - 'NV2080_CTRL_CMD_GR_GET_ZCULL_INFO', - 'NV2080_CTRL_CMD_GR_GET_ZCULL_MASK', - 'NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS', - 'NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE', - 'NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE', - 'NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS', - 'NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE', - 'NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE', - 'NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP', - 'NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE', - 'NV2080_CTRL_CMD_GSP_GET_FEATURES', - 'NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS', - 'NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS', - 'NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS', - 'NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS', - 'NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS', - 'NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK', - 'NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS', - 'NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE', - 'NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS', - 'NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_I2C_ACCESS', - 'NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE', - 'NV2080_CTRL_CMD_I2C_READ_BUFFER', 'NV2080_CTRL_CMD_I2C_READ_REG', - 'NV2080_CTRL_CMD_I2C_WRITE_BUFFER', - 'NV2080_CTRL_CMD_I2C_WRITE_REG', - 'NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS', - 'NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS', - 'NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO', - 'NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX', - 'NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR', - 'NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_CCU_MAP', - 'NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE', - 'NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP', - 'NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE', - 'NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO', - 'NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM', - 'NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS', - 'NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL', - 'NV2080_CTRL_CMD_INTERNAL_FBSR_INIT', - 'NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE', - 'NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE', - 'NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES', - 'NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT', - 'NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP', - 'NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM', - 'NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE', - 'NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND', - 'NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES', - 'NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE', - 'NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET', - 'NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE', - 'NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET', - 'NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID', - 'NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD', - 'NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA', - 'NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE', - 'NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR', - 'NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE', - 'NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID', - 'NV2080_CTRL_CMD_INTERNAL_MAX_BSPS', - 'NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS', - 'NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB', - 'NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES', - 'NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK', - 'NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X', - 'NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X', - 'NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X', - 'NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT', - 'NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL', - 'NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT', - 'NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT', - 'NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS', - 'NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA', - 'NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE', - 'NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES', - 'NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS', - 'NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL', - 'NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER', - 'NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES', - 'NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES', - 'NV2080_CTRL_CMD_LPWR_DIFR_CTRL', - 'NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS', - 'NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE', - 'NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS', - 'NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP', - 'NV2080_CTRL_CMD_MC_GET_ARCH_INFO', - 'NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS', - 'NV2080_CTRL_CMD_MC_GET_MANUFACTURER', - 'NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE', - 'NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS', 'NV2080_CTRL_CMD_NULL', - 'NV2080_CTRL_CMD_NVD_GET_DUMP', - 'NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE', - 'NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL', - 'NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD', - 'NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS', - 'NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE', - 'NV2080_CTRL_CMD_NVLINK_CYCLE_LINK', - 'NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK', - 'NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS', - 'NV2080_CTRL_CMD_NVLINK_EOM_CONTROL', - 'NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND', - 'NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY', - 'NV2080_CTRL_CMD_NVLINK_GET_BW_MODE', - 'NV2080_CTRL_CMD_NVLINK_GET_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2', - 'NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES', - 'NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO', - 'NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT', - 'NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD', - 'NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE', - 'NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES', - 'NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO', - 'NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO', - 'NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS', - 'NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE', - 'NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR', - 'NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE', - 'NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA', - 'NV2080_CTRL_CMD_NVLINK_INJECT_ERROR', - 'NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR', - 'NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR', - 'NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED', - 'NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG', - 'NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE', - 'NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP', - 'NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG', - 'NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP', - 'NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS', - 'NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS', - 'NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN', - 'NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG', - 'NV2080_CTRL_CMD_NVLINK_SETUP_EOM', - 'NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS', - 'NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_NVLINK_SET_BW_MODE', - 'NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE', - 'NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT', - 'NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD', - 'NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE', - 'NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER', - 'NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE', - 'NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO', - 'NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF', - 'NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER', - 'NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER', - 'NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT', - 'NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS', - 'NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER', - 'NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS', - 'NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS', - 'NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY', - 'NV2080_CTRL_CMD_PERF_BOOST', - 'NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE', - 'NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2', - 'NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO', - 'NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2', - 'NV2080_CTRL_CMD_PERF_GET_POWERSTATE', - 'NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE', - 'NV2080_CTRL_CMD_PERF_GPU_IS_IDLE', - 'NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT', - 'NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL', - 'NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL', - 'NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW', - 'NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE', - 'NV2080_CTRL_CMD_PERF_SET_POWERSTATE', - 'NV2080_CTRL_CMD_PERF_VID_ENG', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', - 'NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', - 'NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO', - 'NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG', - 'NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG', - 'NV2080_CTRL_CMD_RC_GET_ERROR', - 'NV2080_CTRL_CMD_RC_GET_ERROR_COUNT', - 'NV2080_CTRL_CMD_RC_GET_ERROR_V2', - 'NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO', - 'NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE', - 'NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE', - 'NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE', - 'NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE', - 'NV2080_CTRL_CMD_RC_INFO_PARAMS', - 'NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM', - 'NV2080_CTRL_CMD_RC_RECOVERY_DISABLED', - 'NV2080_CTRL_CMD_RC_RECOVERY_ENABLED', - 'NV2080_CTRL_CMD_RC_RECOVERY_PARAMS', - 'NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS', - 'NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY', - 'NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG', - 'NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE', - 'NV2080_CTRL_CMD_SET_GPFIFO', 'NV2080_CTRL_CMD_SET_GPFIFO_PARAMS', - 'NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS', - 'NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_SET_RC_INFO', 'NV2080_CTRL_CMD_SET_RC_RECOVERY', - 'NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT', - 'NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE', - 'NV2080_CTRL_CMD_TIMER_CANCEL', - 'NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO', - 'NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET', - 'NV2080_CTRL_CMD_TIMER_GET_TIME', - 'NV2080_CTRL_CMD_TIMER_SCHEDULE', - 'NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS', - 'NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ', - 'NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS', - 'NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK', - 'NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER', - 'NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN', - 'NV2080_CTRL_CTXSW_PM_MODE_CTXSW', - 'NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW', - 'NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW', - 'NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW', - 'NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW', - 'NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL', - 'NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW', - 'NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER', 'NV2080_CTRL_DMA', - 'NV2080_CTRL_DMABUF', - 'NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT', - 'NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE', - 'NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS', - 'NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_DMABUF_MAX_HANDLES', - 'NV2080_CTRL_DMABUF_MEM_HANDLE_INFO', - 'NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES', - 'NV2080_CTRL_DMA_GET_INFO_PARAMS', - 'NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_DMA_INFO', 'NV2080_CTRL_DMA_INFO_INDEX_MAX', - 'NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO', - 'NV2080_CTRL_ECC', - 'NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS', - 'NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS', - 'NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_ECC_NON_PRIVILEGED', - 'NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE', 'NV2080_CTRL_EVENT', - 'NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS', - 'NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS', - 'NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS', - 'NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS', - 'NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS', - 'NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS', - 'NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS', - 'NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_EXEC_PARTITION_SPAN', 'NV2080_CTRL_EXTI2C', - 'NV2080_CTRL_FAS', 'NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE', - 'NV2080_CTRL_FAULT_BUFFER_REPLAYABLE', 'NV2080_CTRL_FB', - 'NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS', - 'NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES', - 'NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES', - 'NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS', - 'NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_FS_INFO_FBPA_MASK', - 'NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK', - 'NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP', - 'NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_FBP_MASK', - 'NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_INVALID_QUERY', - 'NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_LTS_MASK', - 'NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_MAX_QUERIES', - 'NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE', - 'NV2080_CTRL_FB_FS_INFO_PAC_MASK', - 'NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK', - 'NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS', - 'NV2080_CTRL_FB_FS_INFO_QUERY', 'NV2080_CTRL_FB_FS_INFO_ROP_MASK', - 'NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS', - 'NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS', - 'NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS', - 'NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS', - 'NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_FS_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK', - 'NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH', - 'NV2080_CTRL_FB_GET_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS', - 'NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS', - 'NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS', - 'NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE', - 'NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS', - 'NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS', - 'NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS', - 'NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS', - 'NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_GET_STATUS_PARAMS', - 'NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW', - 'NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW', - 'NV2080_CTRL_FB_INFO', - 'NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED', - 'NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED', - 'NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED', - 'NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT', - 'NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT', - 'NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH', - 'NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE', - 'NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW', - 'NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_FBP_MASK', - 'NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN', - 'NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED', - 'NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_HEAP_START', - 'NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB', - 'NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE', - 'NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_MASK', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0', - 'NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1', - 'NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_MAX', - 'NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID', - 'NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT', - 'NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT', - 'NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB', - 'NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0', - 'NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1', - 'NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB', - 'NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB', - 'NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_CFG', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE', - 'NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT', - 'NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T', - 'NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE', - 'NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE', - 'NV2080_CTRL_FB_INFO_MAX_LIST_SIZE', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN', - 'NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND', - 'NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED', - 'NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED', - 'NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED', - 'NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED', - 'NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED', - 'NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED', - 'NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM', - 'NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2', - 'NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4', - 'NV2080_CTRL_FB_IS_KIND_PARAMS', - 'NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES', - 'NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO', - 'NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS', - 'NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES', - 'NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K', - 'NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K', - 'NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT', - 'NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL', - 'NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS', - 'NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS', - 'NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS', - 'NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS', - 'NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD', - 'NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD', - 'NV2080_CTRL_FB_REMAP_ENTRY', - 'NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE', - 'NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS', - 'NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS', - 'NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE', - 'NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS', - 'NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE', - 'NV2080_CTRL_FB_SET_RRD_PARAMS', - 'NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS', - 'NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE', - 'NV2080_CTRL_FB_STATUS_FAILED', - 'NV2080_CTRL_FB_STATUS_NOT_APPLICABLE', - 'NV2080_CTRL_FB_STATUS_PENDING', 'NV2080_CTRL_FB_STATUS_READY', - 'NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS', - 'NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO', 'NV2080_CTRL_FIFO_BIND_CHANNEL', - 'NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS', - 'NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS', - 'NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_CHANNEL_MEM_INFO', - 'NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS', - 'NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE', - 'NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA', - 'NV2080_CTRL_FIFO_DEVICE_ENTRY', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE', - 'NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE', - 'NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS', - 'NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS', - 'NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS', - 'NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS', - 'NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS', - 'NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES', - 'NV2080_CTRL_FIFO_GET_INFO_PARAMS', - 'NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT', - 'NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS', - 'NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_INFO', - 'NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET', - 'NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE', - 'NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE', - 'NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE', - 'NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL', - 'NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT', - 'NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP', - 'NV2080_CTRL_FIFO_MEM_INFO', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS', - 'NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE', - 'NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE', - 'NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS', - 'NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED', - 'NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM', - 'NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT', - 'NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS', - 'NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS', - 'NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS', - 'NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA', 'NV2080_CTRL_FLA_ACTION', - 'NV2080_CTRL_FLA_ACTION_BIND', 'NV2080_CTRL_FLA_ACTION_UNBIND', - 'NV2080_CTRL_FLA_ADDRSPACE', 'NV2080_CTRL_FLA_ADDRSPACE_FBMEM', - 'NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', - 'NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS', - 'NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA_GET_RANGE_PARAMS', - 'NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA_RANGE_PARAMS', - 'NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE', - 'NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS', - 'NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN', 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS', - 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS', - 'NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV', - 'NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK', - 'NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0', - 'NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL', - 'NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED', - 'NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT', - 'NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON', - 'NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT', - 'NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES', - 'NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES', - 'NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED', - 'NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED', - 'NV2080_CTRL_FUSE', 'NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_GC6_ENTRY_PARAMS', - 'NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GC6_EXIT_PARAMS', - 'NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GC6_FLAVOR_ID', 'NV2080_CTRL_GC6_FLAVOR_ID_MAX', - 'NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', - 'NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', - 'NV2080_CTRL_GC6_FLAVOR_INFO', 'NV2080_CTRL_GC6_STEP_ID', - 'NV2080_CTRL_GC6_STEP_ID_GPU_OFF', 'NV2080_CTRL_GC6_STEP_ID_MAX', - 'NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', - 'NV2080_CTRL_GET_P2P_CAPS_PARAMS', - 'NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GET_RC_INFO_PARAMS', - 'NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GET_RC_RECOVERY_PARAMS', - 'NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS', - 'NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPIO', 'NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_GPU', 'NV2080_CTRL_GPUMON_SAMPLE', - 'NV2080_CTRL_GPUMON_SAMPLES', - 'NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL', - 'NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS', - 'NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS', - 'NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_MAX', - 'NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE', - 'NV2080_CTRL_GPU_COMPUTE_PROFILE', - 'NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS', - 'NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO', - 'NV2080_CTRL_GPU_DEBUG_MODE_DISABLED', - 'NV2080_CTRL_GPU_DEBUG_MODE_ENABLED', - 'NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO', - 'NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS', - 'NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE', - 'NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED', - 'NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE', - 'NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE', - 'NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE', - 'NV2080_CTRL_GPU_ECC_UNIT_COUNT', 'NV2080_CTRL_GPU_ECC_UNIT_GSP', - 'NV2080_CTRL_GPU_EVICT_CTX_PARAMS', - 'NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS', - 'NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED', - 'NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED', - 'NV2080_CTRL_GPU_FAULT_PACKET', - 'NV2080_CTRL_GPU_FAULT_PACKET_SIZE', - 'NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS', - 'NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS', - 'NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS', - 'NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS', - 'NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS', - 'NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS', - 'NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS', - 'NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINES_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS', - 'NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FIPS_STATUS', - 'NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS', - 'NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS', - 'NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_GFID_PARAMS', - 'NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_GID_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS', - 'NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS', - 'NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS', - 'NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ID_PARAMS', - 'NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_ILLUM_PARAMS', - 'NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS', - 'NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS', - 'NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY', - 'NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON', - 'NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PMGR', - 'NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU', - 'NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS', - 'NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII', - 'NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE', - 'NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS', - 'NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS', - 'NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS', - 'NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS', - 'NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS', - 'NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS', - 'NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PARTITION_INFO', - 'NV2080_CTRL_GPU_GET_PES_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS', - 'NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST', - 'NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT', - 'NV2080_CTRL_GPU_GET_PIDS_PARAMS', - 'NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT', - 'NV2080_CTRL_GPU_GET_PID_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_RAFTS_FS_MASK', - 'NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS', - 'NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS', - 'NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS', - 'NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SDM_PARAMS', - 'NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS', - 'NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL', - 'NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN', - 'NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS', - 'NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS', - 'NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS', - 'NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS', - 'NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS', - 'NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', - 'NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', - 'NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS', - 'NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS', - 'NV2080_CTRL_GPU_INFO', - 'NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN', - 'NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN', - 'NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO', - 'NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING', - 'NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED', - 'NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED', - 'NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU', - 'NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED', - 'NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32', - 'NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32', - 'NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD', - 'NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED', - 'NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT', - 'NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0', - 'NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1', - 'NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE', - 'NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED', - 'NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM', - 'NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED', - 'NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM', - 'NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE', - 'NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO', - 'NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES', - 'NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS', - 'NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV', - 'NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V', - 'NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED', - 'NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED', - 'NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED', - 'NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO', - 'NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES', - 'NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO', - 'NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES', - 'NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO', - 'NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO', - 'NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES', - 'NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_GPU_MAX_CE_PER_SMC', - 'NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS', - 'NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS', - 'NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS', - 'NV2080_CTRL_GPU_MAX_GPC_PER_SMC', - 'NV2080_CTRL_GPU_MAX_PARTITIONS', - 'NV2080_CTRL_GPU_MAX_PARTITION_IDS', - 'NV2080_CTRL_GPU_MAX_SMC_IDS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS', - 'NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS', - 'NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES', - 'NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS', - 'NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07', - 'NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07', - 'NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER', - 'NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE', - 'NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE', - 'NV2080_CTRL_GPU_PARTITION_ID_INVALID', - 'NV2080_CTRL_GPU_PARTITION_MAX_TYPES', - 'NV2080_CTRL_GPU_PARTITION_SPAN', - 'NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS', - 'NV2080_CTRL_GPU_PID_INFO', 'NV2080_CTRL_GPU_PID_INFO_DATA', - 'NV2080_CTRL_GPU_PID_INFO_INDEX_MAX', - 'NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE', - 'NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA', - 'NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL', - 'NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP', - 'NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS', - 'NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS', - 'NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS', - 'NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS', - 'NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE', - 'NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE', - 'NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS', - 'NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE', - 'NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE', - 'NV2080_CTRL_GPU_QUERY_MODE_PARAMS', - 'NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE', - 'NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC', - 'NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU', - 'NV2080_CTRL_GPU_RECOVERY_ACTION', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', - 'NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', 'NV2080_CTRL_GPU_REG_OP', - 'NV2080_CTRL_GPU_REG_OP_READ_08', - 'NV2080_CTRL_GPU_REG_OP_READ_32', - 'NV2080_CTRL_GPU_REG_OP_READ_64', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP', - 'NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE', - 'NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS', - 'NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS', - 'NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP', - 'NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE', - 'NV2080_CTRL_GPU_REG_OP_TYPE_FB', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC', - 'NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP', - 'NV2080_CTRL_GPU_REG_OP_WRITE_08', - 'NV2080_CTRL_GPU_REG_OP_WRITE_32', - 'NV2080_CTRL_GPU_REG_OP_WRITE_64', - 'NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS', - 'NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS', - 'NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS', - 'NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS', - 'NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS', - 'NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS', - 'NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS', - 'NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS', - 'NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_ILLUM_PARAMS', - 'NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY', - 'NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF', - 'NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS', - 'NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_PARTITION_INFO', - 'NV2080_CTRL_GPU_SET_POWER_PARAMS', - 'NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4', - 'NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7', - 'NV2080_CTRL_GPU_SET_SDM_PARAMS', - 'NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS', - 'NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS', - 'NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB', - 'NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB', 'NV2080_CTRL_GR', - 'NV2080_CTRL_GRMGR', 'NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS', - 'NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS', - 'NV2080_CTRL_GRMGR_MAX_SMC_IDS', - 'NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS', - 'NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS', - 'NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS', - 'NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS', - 'NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM', - 'NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN', - 'NV2080_CTRL_GR_DISABLED_SM_VGPC_ID', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', - 'NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', - 'NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', - 'NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CAPS_V2_PARAMS', - 'NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS', - 'NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS', - 'NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS', - 'NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS', - 'NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS', - 'NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_INFO_V2_PARAMS', - 'NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS', - 'NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_PPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ROP_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT', - 'NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS', - 'NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_TPC_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS', - 'NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED', - 'NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS', - 'NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS', - 'NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS', - 'NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_INFO', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE', - 'NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE', - 'NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT', - 'NV2080_CTRL_GR_INFO_INDEX_DUMMY', - 'NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY', - 'NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES', - 'NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES', - 'NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES', - 'NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC', - 'NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS', - 'NV2080_CTRL_GR_INFO_INDEX_MAX', - 'NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP', - 'NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM', - 'NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894', - 'NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_SM_VERSION', - 'NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT', - 'NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT', - 'NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR', - 'NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED', - 'NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE', - 'NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT', - 'NV2080_CTRL_GR_INFO_MAX_SIZE', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_00', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_01', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_04', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_10_4', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_05', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_4', - 'NV2080_CTRL_GR_INFO_SM_VERSION_1_5', - 'NV2080_CTRL_GR_INFO_SM_VERSION_2_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_2_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_2_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_5', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_6', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_8', - 'NV2080_CTRL_GR_INFO_SM_VERSION_3_9', - 'NV2080_CTRL_GR_INFO_SM_VERSION_4_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_03', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_5_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_01', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_6_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_01', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_03', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_05', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_1', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_3', - 'NV2080_CTRL_GR_INFO_SM_VERSION_7_5', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_02', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_06', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_07', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_08', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_09', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_2', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_6', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_7', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_8', - 'NV2080_CTRL_GR_INFO_SM_VERSION_8_9', - 'NV2080_CTRL_GR_INFO_SM_VERSION_9_0', - 'NV2080_CTRL_GR_INFO_SM_VERSION_9_00', - 'NV2080_CTRL_GR_INFO_SM_VERSION_NONE', - 'NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK', - 'NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT', - 'NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS', - 'NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_ROUTE_INFO', - 'NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL', - 'NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID', - 'NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS', - 'NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES', - 'NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS', - 'NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS', - 'NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GR_VAT_ALARM_DATA', - 'NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC', - 'NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC', 'NV2080_CTRL_GSP', - 'NV2080_CTRL_GSP_GET_FEATURES_PARAMS', - 'NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE', - 'NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE', - 'NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE', - 'NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE', - 'NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS', - 'NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX', - 'NV2080_CTRL_GSP_LIBOS_POOL_STATS', - 'NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT', 'NV2080_CTRL_I2C', - 'NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE', - 'NV2080_CTRL_I2C_ACCESS_CMD_NULL', - 'NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER', - 'NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE', - 'NV2080_CTRL_I2C_ACCESS_CMD_RELEASE', - 'NV2080_CTRL_I2C_ACCESS_CMD_RESET', - 'NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE', - 'NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE', - 'NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE', - 'NV2080_CTRL_I2C_ACCESS_CMD_START', - 'NV2080_CTRL_I2C_ACCESS_CMD_STOP', - 'NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT', - 'NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER', - 'NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE', - 'NV2080_CTRL_I2C_ACCESS_FLAG_ACK', - 'NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS', - 'NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED', - 'NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE', - 'NV2080_CTRL_I2C_ACCESS_FLAG_RAB', - 'NV2080_CTRL_I2C_ACCESS_FLAG_RESTART', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT', - 'NV2080_CTRL_I2C_ACCESS_FLAG_START', - 'NV2080_CTRL_I2C_ACCESS_FLAG_STOP', - 'NV2080_CTRL_I2C_ACCESS_NUM_PORTS', - 'NV2080_CTRL_I2C_ACCESS_PARAMS', - 'NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_ACCESS_PORT_1', 'NV2080_CTRL_I2C_ACCESS_PORT_10', - 'NV2080_CTRL_I2C_ACCESS_PORT_2', 'NV2080_CTRL_I2C_ACCESS_PORT_3', - 'NV2080_CTRL_I2C_ACCESS_PORT_4', 'NV2080_CTRL_I2C_ACCESS_PORT_5', - 'NV2080_CTRL_I2C_ACCESS_PORT_6', 'NV2080_CTRL_I2C_ACCESS_PORT_7', - 'NV2080_CTRL_I2C_ACCESS_PORT_8', 'NV2080_CTRL_I2C_ACCESS_PORT_9', - 'NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC', - 'NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY', - 'NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY', - 'NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY', - 'NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY', - 'NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY', - 'NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING', - 'NV2080_CTRL_I2C_ACCESS_STATUS_ERROR', - 'NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND', - 'NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR', - 'NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS', - 'NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS', - 'NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED', - 'NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED', - 'NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC', - 'NV2080_CTRL_I2C_FLAGS_PRIVILEGE', 'NV2080_CTRL_I2C_FLAGS_PX3540', - 'NV2080_CTRL_I2C_MAX_ADDR_ENTRIES', 'NV2080_CTRL_I2C_MAX_ENTRIES', - 'NV2080_CTRL_I2C_MAX_REG_LEN', - 'NV2080_CTRL_I2C_READ_BUFFER_PARAMS', - 'NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_READ_REG_PARAMS', - 'NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_RW_REG_PARAMS', 'NV2080_CTRL_I2C_VERSION_0', - 'NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS', - 'NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_I2C_WRITE_REG_PARAMS', - 'NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL', - 'NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS', - 'NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BSP_CAPS', - 'NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS', - 'NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX', - 'NV2080_CTRL_INTERNAL_CCU_MAP_INFO', - 'NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS', - 'NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS', - 'NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DEVICE_INFO', - 'NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS', - 'NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS', - 'NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS', - 'NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_EDID_DATA', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2', - 'NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3', - 'NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO', - 'NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT', - 'NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS', - 'NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR', - 'NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS', - 'NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS', - 'NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID', - 'NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS', - 'NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS', - 'NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX', - 'NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES', - 'NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES', - 'NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS', - 'NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER', - 'NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS', - 'NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE', - 'NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES', - 'NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES', - 'NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO', - 'NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS', - 'NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES', - 'NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_INFO', - 'NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_MAX_ENGINES', - 'NV2080_CTRL_INTERNAL_GR_MAX_GPC', - 'NV2080_CTRL_INTERNAL_GR_MAX_SM', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS', - 'NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS', - 'NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS', - 'NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY', - 'NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE', - 'NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS', - 'NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS', - 'NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS', - 'NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID', - 'NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT', - 'NV2080_CTRL_INTERNAL_MEMDESC_INFO', - 'NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS', - 'NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE', - 'NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO', - 'NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_MSENC_CAPS', - 'NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE', - 'NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN', - 'NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES', - 'NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES', - 'NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE', - 'NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER', - 'NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS', - 'NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_NV_RANGE', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X', - 'NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS', - 'NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM', - 'NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT', - 'NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO', - 'NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS', - 'NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SPDM_PARTITION', - 'NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS', - 'NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT', - 'NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS', - 'NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_CAPS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER', - 'NV2080_CTRL_INTERNAL_STATIC_GR_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES', - 'NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS', - 'NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER', - 'NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS', - 'NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS', - 'NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO', - 'NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS', - 'NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES', - 'NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS', - 'NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES', - 'NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS', - 'NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_KGR_MAX_BUFFER_PTES', 'NV2080_CTRL_LPWR', - 'NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE', - 'NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE', - 'NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS', - 'NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED', - 'NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS', - 'NV2080_CTRL_LPWR_DIFR_SUPPORTED', - 'NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_LPWR_LEGACY_PRIVILEGED', 'NV2080_CTRL_MAX_CES', - 'NV2080_CTRL_MAX_GPC_COUNT', 'NV2080_CTRL_MAX_GRCES', - 'NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN', - 'NV2080_CTRL_MAX_PCES', 'NV2080_CTRL_MAX_PHYSICAL_BRIDGE', - 'NV2080_CTRL_MAX_VMMU_SEGMENTS', 'NV2080_CTRL_MC', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X', - 'NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116', - 'NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q', - 'NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R', - 'NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS', - 'NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_ENGINE_ID_ALL', - 'NV2080_CTRL_MC_ENGINE_ID_GRAPHICS', - 'NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY', - 'NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS', - 'NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES', - 'NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS', - 'NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS', - 'NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX', - 'NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS', - 'NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS', - 'NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_MC_STATIC_INTR_ENTRY', - 'NV2080_CTRL_MEMMGR_MEMORY_OP', - 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', - 'NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', - 'NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX', 'NV2080_CTRL_NNE', - 'NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO', - 'NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES', - 'NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO', - 'NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO', - 'NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG', - 'NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON', - 'NV2080_CTRL_NOCAT_TAG_CLEAR_NO', - 'NV2080_CTRL_NOCAT_TAG_CLEAR_YES', - 'NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET', - 'NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP', - 'NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET', - 'NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY', - 'NV2080_CTRL_NOCAT_TDR_TYPE_NONE', - 'NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL', - 'NV2080_CTRL_NOCAT_TDR_TYPE_TEST', - 'NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET', 'NV2080_CTRL_NVD', - 'NV2080_CTRL_NVD_GET_DUMP_PARAMS', - 'NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS', - 'NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS', - 'NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVENC_SW_SESSION_INFO', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED', - 'NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED', - 'NV2080_CTRL_NVFBC_SW_SESSION_INFO', 'NV2080_CTRL_NVIF', - 'NV2080_CTRL_NVLINK', 'NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0', - 'NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0', - 'NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_CAPS_TBL_SIZE', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS', - 'NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_COMMON_ERR_INFO', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS', - 'NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_COUNTERS_MAX', - 'NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES', - 'NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1', - 'NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY', - 'NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER', - 'NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY', - 'NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_0', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_1', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_10', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_11', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_12', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_13', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_14', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_15', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_2', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_3', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_4', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_5', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_6', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_7', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_8', - 'NV2080_CTRL_NVLINK_COUNTER_HISTORY_9', - 'NV2080_CTRL_NVLINK_COUNTER_INVALID', - 'NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY', - 'NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE', - 'NV2080_CTRL_NVLINK_COUNTER_L1_EXIT', - 'NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL', - 'NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE', - 'NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_LP_DL', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ', - 'NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS', - 'NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES', - 'NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0', - 'NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR', - 'NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS', - 'NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER', - 'NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR', - 'NV2080_CTRL_NVLINK_COUNTER_TL_RX0', - 'NV2080_CTRL_NVLINK_COUNTER_TL_RX1', - 'NV2080_CTRL_NVLINK_COUNTER_TL_TX0', - 'NV2080_CTRL_NVLINK_COUNTER_TL_TX1', - 'NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA', - 'NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA', - 'NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW', - 'NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS', - 'NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS', - 'NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME', - 'NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS', - 'NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_DEVICE_INFO', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE', - 'NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE', - 'NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS', - 'NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS', - 'NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_EOM_MEASUREMENT', - 'NV2080_CTRL_NVLINK_ERR_INFO', - 'NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS', - 'NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT', - 'NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY', - 'NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY', - 'NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES', - 'NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS', - 'NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS', - 'NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME', - 'NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME', - 'NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS', - 'NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR', - 'NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER', - 'NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE', - 'NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS', - 'NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS', - 'NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS', - 'NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', - 'NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE', - 'NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE', - 'NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE', - 'NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS', - 'NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS', - 'NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_L1_FORCE_CONFIG', - 'NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT', - 'NV2080_CTRL_NVLINK_LANE_ERROR', - 'NV2080_CTRL_NVLINK_LINK_ECC_ERROR', - 'NV2080_CTRL_NVLINK_LINK_STATUS_INFO', - 'NV2080_CTRL_NVLINK_LP_COUNTERS_DL', - 'NV2080_CTRL_NVLINK_MAX_ARR_SIZE', - 'NV2080_CTRL_NVLINK_MAX_IOCTRLS', 'NV2080_CTRL_NVLINK_MAX_LANES', - 'NV2080_CTRL_NVLINK_MAX_LINKS', - 'NV2080_CTRL_NVLINK_MAX_LINK_COUNT', - 'NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE', - 'NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES', - 'NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES', - 'NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO', - 'NV2080_CTRL_NVLINK_PORT_EVENT', - 'NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE', - 'NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS', - 'NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_POWER_STATE_L0', - 'NV2080_CTRL_NVLINK_POWER_STATE_L1', - 'NV2080_CTRL_NVLINK_POWER_STATE_L2', - 'NV2080_CTRL_NVLINK_POWER_STATE_L3', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS', - 'NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_PRM_DATA', - 'NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS', - 'NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX', - 'NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES', - 'NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS', - 'NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS', - 'NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID', - 'NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS', - 'NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX', - 'NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS', - 'NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS', - 'NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL', - 'NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE', - 'NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS', - 'NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS', - 'NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN', - 'NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE', - 'NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE', - 'NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT', - 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', - 'NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP', - 'NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG', - 'NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK', - 'NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT', - 'NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0', - 'NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0', - 'NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_PHY_GRS', - 'NV2080_CTRL_NVLINK_STATUS_PHY_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_PHY_NVHS', - 'NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST', - 'NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING', - 'NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT', - 'NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS', - 'NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR', - 'NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE', - 'NV2080_CTRL_NVLINK_TL_INTEN_FALSE', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN', - 'NV2080_CTRL_NVLINK_TL_INTEN_TRUE', 'NV2080_CTRL_NVLINK_UNIT_DL', - 'NV2080_CTRL_NVLINK_UNIT_MIF_RX_0', - 'NV2080_CTRL_NVLINK_UNIT_MIF_TX_0', - 'NV2080_CTRL_NVLINK_UNIT_MINION', 'NV2080_CTRL_NVLINK_UNIT_TL', - 'NV2080_CTRL_NVLINK_UNIT_TLC_RX_0', - 'NV2080_CTRL_NVLINK_UNIT_TLC_RX_1', - 'NV2080_CTRL_NVLINK_UNIT_TLC_TX_0', - 'NV2080_CTRL_NVLINK_UPHY_CLN_CMD', 'NV2080_CTRL_OS_MACOS', - 'NV2080_CTRL_OS_UNIX', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS', - 'NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS', - 'NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS', - 'NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS', - 'NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS', - 'NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS', - 'NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_OS_WINDOWS', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR', - 'NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR', - 'NV2080_CTRL_PC_SAMPLING_MODE_DISABLED', - 'NV2080_CTRL_PC_SAMPLING_MODE_ENABLED', 'NV2080_CTRL_PERF', - 'NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS', - 'NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P0', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P1', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P2', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P3', - 'NV2080_CTRL_PERF_AUX_POWER_STATE_P4', - 'NV2080_CTRL_PERF_BOOST_DURATION_INFINITE', - 'NV2080_CTRL_PERF_BOOST_DURATION_MAX', - 'NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO', - 'NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH', - 'NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES', - 'NV2080_CTRL_PERF_BOOST_PARAMS', - 'NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_CLK_MAX_DOMAINS', - 'NV2080_CTRL_PERF_GET_CLK_INFO', - 'NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS', - 'NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS', - 'NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS', - 'NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS', - 'NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS', - 'NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE', - 'NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE', - 'NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE', - 'NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_PERF_LEGACY_PRIVILEGED', - 'NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS', - 'NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_POWERSTATE_PARAMS', - 'NV2080_CTRL_PERF_POWER_SOURCE_AC', - 'NV2080_CTRL_PERF_POWER_SOURCE_BATTERY', - 'NV2080_CTRL_PERF_PSTATES_ALL', - 'NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED', - 'NV2080_CTRL_PERF_PSTATES_ID', 'NV2080_CTRL_PERF_PSTATES_MAX', - 'NV2080_CTRL_PERF_PSTATES_MIN', 'NV2080_CTRL_PERF_PSTATES_P0', - 'NV2080_CTRL_PERF_PSTATES_P1', 'NV2080_CTRL_PERF_PSTATES_P10', - 'NV2080_CTRL_PERF_PSTATES_P11', 'NV2080_CTRL_PERF_PSTATES_P12', - 'NV2080_CTRL_PERF_PSTATES_P13', 'NV2080_CTRL_PERF_PSTATES_P14', - 'NV2080_CTRL_PERF_PSTATES_P15', 'NV2080_CTRL_PERF_PSTATES_P2', - 'NV2080_CTRL_PERF_PSTATES_P3', 'NV2080_CTRL_PERF_PSTATES_P4', - 'NV2080_CTRL_PERF_PSTATES_P5', 'NV2080_CTRL_PERF_PSTATES_P6', - 'NV2080_CTRL_PERF_PSTATES_P7', 'NV2080_CTRL_PERF_PSTATES_P8', - 'NV2080_CTRL_PERF_PSTATES_P9', - 'NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY', - 'NV2080_CTRL_PERF_PSTATES_UNDEFINED', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', - 'NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', - 'NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', - 'NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS', - 'NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE', - 'NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS', - 'NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS', - 'NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS', - 'NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK', - 'NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE', - 'NV2080_CTRL_PERF_VIDEOEVENT_OFA_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START', - 'NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP', - 'NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', - 'NV2080_CTRL_PERF_VPSTATE_RATED_TDP', - 'NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', - 'NV2080_CTRL_PEX_MAX_COUNTER_TYPES', 'NV2080_CTRL_PEX_MAX_LANES', - 'NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES', 'NV2080_CTRL_PMGR', - 'NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_PMGR_LEGACY_PRIVILEGED', - 'NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE', - 'NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED', - 'NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED', - 'NV2080_CTRL_PMGR_MODULE_INFO_PARAMS', - 'NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_POWER', 'NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_RC', 'NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE', - 'NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS', - 'NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_RC_GET_ERROR_V2_PARAMS', - 'NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS', - 'NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS', - 'NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_REG_OPS_ARRAY_MAX', 'NV2080_CTRL_RESERVED', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL', - 'NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI', - 'NV2080_CTRL_SET_RC_INFO_PARAMS', - 'NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_SET_RC_RECOVERY_PARAMS', - 'NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_SMC_SUBSCRIPTION_INFO', 'NV2080_CTRL_SPI', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK', - 'NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL', - 'NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS', - 'NV2080_CTRL_THERMAL', - 'NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED', 'NV2080_CTRL_TIMER', - 'NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS', - 'NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS', - 'NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TIMER_GET_TIME_PARAMS', - 'NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES', - 'NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE', - 'NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS', - 'NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL', - 'NV2080_CTRL_UCODE_FUZZER', - 'NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS', - 'NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS', - 'NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID', - 'NV2080_CTRL_VOLT', 'NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED', - 'NV2080_CTRL_VOLT_LEGACY_PRIVILEGED', - 'NV2080_CTRL_VPR_INFO_QUERY_TYPE', - 'NV2080_ENGINE_TYPE_ALLENGINES', 'NV2080_ENGINE_TYPE_BSP', - 'NV2080_ENGINE_TYPE_CIPHER', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8', - 'NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9', - 'NV2080_ENGINE_TYPE_COPY0', 'NV2080_ENGINE_TYPE_COPY1', - 'NV2080_ENGINE_TYPE_COPY10', 'NV2080_ENGINE_TYPE_COPY11', - 'NV2080_ENGINE_TYPE_COPY12', 'NV2080_ENGINE_TYPE_COPY13', - 'NV2080_ENGINE_TYPE_COPY14', 'NV2080_ENGINE_TYPE_COPY15', - 'NV2080_ENGINE_TYPE_COPY16', 'NV2080_ENGINE_TYPE_COPY17', - 'NV2080_ENGINE_TYPE_COPY18', 'NV2080_ENGINE_TYPE_COPY19', - 'NV2080_ENGINE_TYPE_COPY2', 'NV2080_ENGINE_TYPE_COPY3', - 'NV2080_ENGINE_TYPE_COPY4', 'NV2080_ENGINE_TYPE_COPY5', - 'NV2080_ENGINE_TYPE_COPY6', 'NV2080_ENGINE_TYPE_COPY7', - 'NV2080_ENGINE_TYPE_COPY8', 'NV2080_ENGINE_TYPE_COPY9', - 'NV2080_ENGINE_TYPE_COPY_SIZE', 'NV2080_ENGINE_TYPE_DPU', - 'NV2080_ENGINE_TYPE_FBFLCN', 'NV2080_ENGINE_TYPE_GR0', - 'NV2080_ENGINE_TYPE_GR1', 'NV2080_ENGINE_TYPE_GR2', - 'NV2080_ENGINE_TYPE_GR3', 'NV2080_ENGINE_TYPE_GR4', - 'NV2080_ENGINE_TYPE_GR5', 'NV2080_ENGINE_TYPE_GR6', - 'NV2080_ENGINE_TYPE_GR7', 'NV2080_ENGINE_TYPE_GRAPHICS', - 'NV2080_ENGINE_TYPE_GR_SIZE', 'NV2080_ENGINE_TYPE_HOST', - 'NV2080_ENGINE_TYPE_LAST', 'NV2080_ENGINE_TYPE_ME', - 'NV2080_ENGINE_TYPE_MP', 'NV2080_ENGINE_TYPE_MPEG', - 'NV2080_ENGINE_TYPE_MSENC', 'NV2080_ENGINE_TYPE_NULL', - 'NV2080_ENGINE_TYPE_NVDEC0', 'NV2080_ENGINE_TYPE_NVDEC1', - 'NV2080_ENGINE_TYPE_NVDEC2', 'NV2080_ENGINE_TYPE_NVDEC3', - 'NV2080_ENGINE_TYPE_NVDEC4', 'NV2080_ENGINE_TYPE_NVDEC5', - 'NV2080_ENGINE_TYPE_NVDEC6', 'NV2080_ENGINE_TYPE_NVDEC7', - 'NV2080_ENGINE_TYPE_NVDEC_SIZE', 'NV2080_ENGINE_TYPE_NVENC0', - 'NV2080_ENGINE_TYPE_NVENC1', 'NV2080_ENGINE_TYPE_NVENC2', - 'NV2080_ENGINE_TYPE_NVENC3', 'NV2080_ENGINE_TYPE_NVENC_SIZE', - 'NV2080_ENGINE_TYPE_NVJPEG0', 'NV2080_ENGINE_TYPE_NVJPEG1', - 'NV2080_ENGINE_TYPE_NVJPEG2', 'NV2080_ENGINE_TYPE_NVJPEG3', - 'NV2080_ENGINE_TYPE_NVJPEG4', 'NV2080_ENGINE_TYPE_NVJPEG5', - 'NV2080_ENGINE_TYPE_NVJPEG6', 'NV2080_ENGINE_TYPE_NVJPEG7', - 'NV2080_ENGINE_TYPE_NVJPEG_SIZE', 'NV2080_ENGINE_TYPE_NVJPG', - 'NV2080_ENGINE_TYPE_OFA', 'NV2080_ENGINE_TYPE_OFA0', - 'NV2080_ENGINE_TYPE_OFA1', 'NV2080_ENGINE_TYPE_OFA_SIZE', - 'NV2080_ENGINE_TYPE_PMU', 'NV2080_ENGINE_TYPE_PPP', - 'NV2080_ENGINE_TYPE_SEC2', 'NV2080_ENGINE_TYPE_SW', - 'NV2080_ENGINE_TYPE_TSEC', 'NV2080_ENGINE_TYPE_VIC', - 'NV2080_ENGINE_TYPE_VP', 'NV2080_EVENT_DSTATE_PPC_D0', - 'NV2080_EVENT_DSTATE_PPC_D3', 'NV2080_EVENT_DSTATE_PPC_INVALID', - 'NV2080_EVENT_DSTATE_XUSB_D0', 'NV2080_EVENT_DSTATE_XUSB_D3', - 'NV2080_EVENT_DSTATE_XUSB_INVALID', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', - 'NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', - 'NV2080_EVENT_HDACODEC_DSTATE', - 'NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR', - 'NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED', - 'NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING', - 'NV2080_GC5_ENTRY_ABORTED', 'NV2080_GC5_EXIT_COMPLETE', - 'NV2080_GET_P2P_CAPS_UUID_LEN', - 'NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII', - 'NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY', - 'NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1', - 'NV2080_GPU_FABRIC_CLUSTER_UUID_LEN', 'NV2080_GPU_MAX_ENGINES', - 'NV2080_GPU_MAX_ENGINES_LIST_SIZE', 'NV2080_GPU_MAX_GID_LENGTH', - 'NV2080_GPU_MAX_MARKETING_NAME_LENGTH', - 'NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH', - 'NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH', - 'NV2080_GPU_MAX_NAME_STRING_LENGTH', - 'NV2080_GPU_MAX_OEM_INFO_LENGTH', - 'NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH', - 'NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH', - 'NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH', - 'NV2080_GPU_NVFBC_MAX_SESSION_COUNT', - 'NV2080_GSP_MAX_BUILD_VERSION_LENGTH', 'NV2080_GUEST_VM_INFO', - 'NV2080_HOST_VGPU_DEVICE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP', - 'NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP', - 'NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE', - 'NV2080_INTR_CATEGORY', 'NV2080_INTR_CATEGORY_DEFAULT', - 'NV2080_INTR_CATEGORY_ENUM_COUNT', - 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', - 'NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', - 'NV2080_INTR_CATEGORY_RUNLIST', - 'NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', - 'NV2080_INTR_CATEGORY_SUBTREE_MAP', - 'NV2080_INTR_CATEGORY_UVM_OWNED', - 'NV2080_INTR_CATEGORY_UVM_SHARED', 'NV2080_INTR_TYPE_ACCESS_CNTR', - 'NV2080_INTR_TYPE_CPU_DOORBELL', 'NV2080_INTR_TYPE_GR0_FECS_LOG', - 'NV2080_INTR_TYPE_GR1_FECS_LOG', 'NV2080_INTR_TYPE_GR2_FECS_LOG', - 'NV2080_INTR_TYPE_GR3_FECS_LOG', 'NV2080_INTR_TYPE_GR4_FECS_LOG', - 'NV2080_INTR_TYPE_GR5_FECS_LOG', 'NV2080_INTR_TYPE_GR6_FECS_LOG', - 'NV2080_INTR_TYPE_GR7_FECS_LOG', 'NV2080_INTR_TYPE_INFO_FAULT', - 'NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT', - 'NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR', - 'NV2080_INTR_TYPE_NULL', 'NV2080_INTR_TYPE_REPLAYABLE_FAULT', - 'NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR', 'NV2080_INTR_TYPE_TMR', - 'NV2080_MAX_CHIP_SKU_LENGTH', 'NV2080_MAX_CTAGS_FOR_CBC_EVICTION', - 'NV2080_MAX_NUM_HEADS', 'NV2080_NOCAT_JOURNAL_ENTRY', - 'NV2080_NOCAT_JOURNAL_GPU_STATE', - 'NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS', - 'NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER', - 'NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS', - 'NV2080_NOCAT_JOURNAL_MAX_STR_LEN', - 'NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG', - 'NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS', - 'NV2080_NOCAT_JOURNAL_RECORD', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_ANY', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_RC', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_TDR', - 'NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX', - 'NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX', - 'NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT', - 'NV2080_NOTIFIERS_ACPI_NOTIFY', - 'NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST', - 'NV2080_NOTIFIERS_AUX_POWER_EVENT', - 'NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE', 'NV2080_NOTIFIERS_CE0', - 'NV2080_NOTIFIERS_CE1', 'NV2080_NOTIFIERS_CE10', - 'NV2080_NOTIFIERS_CE11', 'NV2080_NOTIFIERS_CE12', - 'NV2080_NOTIFIERS_CE13', 'NV2080_NOTIFIERS_CE14', - 'NV2080_NOTIFIERS_CE15', 'NV2080_NOTIFIERS_CE16', - 'NV2080_NOTIFIERS_CE17', 'NV2080_NOTIFIERS_CE18', - 'NV2080_NOTIFIERS_CE19', 'NV2080_NOTIFIERS_CE2', - 'NV2080_NOTIFIERS_CE3', 'NV2080_NOTIFIERS_CE4', - 'NV2080_NOTIFIERS_CE5', 'NV2080_NOTIFIERS_CE6', - 'NV2080_NOTIFIERS_CE7', 'NV2080_NOTIFIERS_CE8', - 'NV2080_NOTIFIERS_CE9', 'NV2080_NOTIFIERS_CLOCKS_CHANGE', - 'NV2080_NOTIFIERS_COOLER_DIAG_ZONE', - 'NV2080_NOTIFIERS_CTXSW_TIMEOUT', - 'NV2080_NOTIFIERS_CTXSW_UCODE_ERROR', 'NV2080_NOTIFIERS_DP_IRQ', - 'NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT', - 'NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE', - 'NV2080_NOTIFIERS_DSTATE_HDA', 'NV2080_NOTIFIERS_DSTATE_XUSB_PPC', - 'NV2080_NOTIFIERS_ECC_DBE', 'NV2080_NOTIFIERS_ECC_SBE', - 'NV2080_NOTIFIERS_ECC_SBE_STORM', 'NV2080_NOTIFIERS_EVENTBUFFER', - 'NV2080_NOTIFIERS_FECS_CTX_SWITCH', - 'NV2080_NOTIFIERS_FIFO_EVENT_MTHD', - 'NV2080_NOTIFIERS_FULL_SCREEN_CHANGE', - 'NV2080_NOTIFIERS_GC5_GPU_READY', - 'NV2080_NOTIFIERS_GC6_REFCOUNT_DEC', - 'NV2080_NOTIFIERS_GC6_REFCOUNT_INC', - 'NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT', - 'NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT', - 'NV2080_NOTIFIERS_GPU_RECOVERY_ACTION', - 'NV2080_NOTIFIERS_GPU_UNAVAILABLE', 'NV2080_NOTIFIERS_GR0', - 'NV2080_NOTIFIERS_GR1', 'NV2080_NOTIFIERS_GR2', - 'NV2080_NOTIFIERS_GR3', 'NV2080_NOTIFIERS_GR4', - 'NV2080_NOTIFIERS_GR5', 'NV2080_NOTIFIERS_GR6', - 'NV2080_NOTIFIERS_GR7', 'NV2080_NOTIFIERS_GRAPHICS', - 'NV2080_NOTIFIERS_GR_DEBUG_INTR', - 'NV2080_NOTIFIERS_GSP_PERF_TRACE', - 'NV2080_NOTIFIERS_HDCP_STATUS_CHANGE', - 'NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST', - 'NV2080_NOTIFIERS_HOTPLUG', - 'NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE', - 'NV2080_NOTIFIERS_INBAND_RESPONSE', - 'NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED', - 'NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED', - 'NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED', - 'NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST', - 'NV2080_NOTIFIERS_MAXCOUNT', 'NV2080_NOTIFIERS_MSENC', - 'NV2080_NOTIFIERS_NVDEC0', 'NV2080_NOTIFIERS_NVDEC1', - 'NV2080_NOTIFIERS_NVDEC2', 'NV2080_NOTIFIERS_NVDEC3', - 'NV2080_NOTIFIERS_NVDEC4', 'NV2080_NOTIFIERS_NVDEC5', - 'NV2080_NOTIFIERS_NVDEC6', 'NV2080_NOTIFIERS_NVDEC7', - 'NV2080_NOTIFIERS_NVENC0', 'NV2080_NOTIFIERS_NVENC1', - 'NV2080_NOTIFIERS_NVENC2', 'NV2080_NOTIFIERS_NVENC3', - 'NV2080_NOTIFIERS_NVJPEG0', 'NV2080_NOTIFIERS_NVJPEG1', - 'NV2080_NOTIFIERS_NVJPEG2', 'NV2080_NOTIFIERS_NVJPEG3', - 'NV2080_NOTIFIERS_NVJPEG4', 'NV2080_NOTIFIERS_NVJPEG5', - 'NV2080_NOTIFIERS_NVJPEG6', 'NV2080_NOTIFIERS_NVJPEG7', - 'NV2080_NOTIFIERS_NVJPG', 'NV2080_NOTIFIERS_NVLINK_ERROR_FATAL', - 'NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED', - 'NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN', - 'NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP', - 'NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR', - 'NV2080_NOTIFIERS_NVPCF_EVENTS', - 'NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT', - 'NV2080_NOTIFIERS_OFA', 'NV2080_NOTIFIERS_OFA0', - 'NV2080_NOTIFIERS_OFA1', 'NV2080_NOTIFIERS_PDEC', - 'NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT', - 'NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE', - 'NV2080_NOTIFIERS_PMU_COMMAND', 'NV2080_NOTIFIERS_PMU_EVENT', - 'NV2080_NOTIFIERS_POISON_ERROR_FATAL', - 'NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL', - 'NV2080_NOTIFIERS_POWER_CONNECTOR', - 'NV2080_NOTIFIERS_POWER_EVENT', 'NV2080_NOTIFIERS_POWER_RESUME', - 'NV2080_NOTIFIERS_POWER_SUSPEND', 'NV2080_NOTIFIERS_PPP', - 'NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT', - 'NV2080_NOTIFIERS_PRIV_RING_HANG', - 'NV2080_NOTIFIERS_PSTATE_CHANGE', 'NV2080_NOTIFIERS_RC_ERROR', - 'NV2080_NOTIFIERS_RESERVED122', 'NV2080_NOTIFIERS_RESERVED_186', - 'NV2080_NOTIFIERS_RUNLIST_ACQUIRE', - 'NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE', - 'NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE', - 'NV2080_NOTIFIERS_RUNLIST_IDLE', - 'NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE', - 'NV2080_NOTIFIERS_SEC2', 'NV2080_NOTIFIERS_SEC_FAULT_ERROR', - 'NV2080_NOTIFIERS_SMC_CONFIG_UPDATE', - 'NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION', - 'NV2080_NOTIFIERS_SW', 'NV2080_NOTIFIERS_THERMAL_DIAG_ZONE', - 'NV2080_NOTIFIERS_THERMAL_HW', 'NV2080_NOTIFIERS_THERMAL_SW', - 'NV2080_NOTIFIERS_TIMER', 'NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE', - 'NV2080_NOTIFIERS_UCODE_RESET', 'NV2080_NOTIFIERS_UNUSED_0', - 'NV2080_NOTIFIERS_UNUSED_1', - 'NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD', - 'NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE', - 'NV2080_NOTIFIERS_VLD', 'NV2080_NOTIFIERS_VRR_SET_TIMEOUT', - 'NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE', - 'NV2080_NOTIFIERS_XUSB_PPC_CONNECTED', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE', - 'NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN', - 'NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION', - 'NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION', - 'NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS', - 'NV2080_RAFTS_FLOORSWEEP_INFO', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', - 'NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', - 'NV2080_SET_P2P_MAPPING_UUID_LEN', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE', - 'NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS', - 'NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP', - 'NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC', 'NV2080_TYPEDEF', - 'NV2080_VF_MSIX_CAPS', 'NV2080_VGPU_FB_USAGE', - 'NV2080_VGPU_GUEST', 'NV2081_BINAPI', 'NV2082_BINAPI_PRIVILEGED', - 'NV20_SUBDEVICE_0', 'NV20_SUBDEVICE_DIAG', 'NV30_GSYNC', - 'NV40_DEBUG_BUFFER', 'NV40_I2C', 'NV4_SOFTWARE_TEST', - 'NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO', - 'NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES', - 'NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS', - 'NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS', - 'NV50_CHANNEL_GPFIFO', 'NV50_DEFERRED_API_CLASS', - 'NV50_MEMORY_VIRTUAL', 'NV50_P2P', 'NV50_THIRD_PARTY_P2P', - 'NV83DE_ALLOC_PARAMETERS', 'NV83DE_ALLOC_PARAMETERS_MESSAGE_ID', - 'NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES', - 'NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE', - 'NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS', - 'NV83DE_CTRL_CMD_DEBUG_GET_HANDLES', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED', - 'NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS', - 'NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES', - 'NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY', - 'NV83DE_CTRL_CMD_DEBUG_READ_MEMORY', - 'NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO', - 'NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE', - 'NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS', - 'NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS', - 'NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT', - 'NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC', - 'NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE', - 'NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER', - 'NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS', - 'NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY', - 'NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY', - 'NV83DE_CTRL_CMD_GET_MAPPINGS', 'NV83DE_CTRL_CMD_NULL', - 'NV83DE_CTRL_CMD_READ_SURFACE', - 'NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE', - 'NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE', - 'NV83DE_CTRL_CMD_WRITE_SURFACE', 'NV83DE_CTRL_DEBUG', - 'NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY', - 'NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS', - 'NV83DE_CTRL_DEBUG_ACCESS_OP', - 'NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS', - 'NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS', - 'NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS', - 'NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS', - 'NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP', - 'NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS', - 'NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS', - 'NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL', - 'NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS', - 'NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP', - 'NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP', - 'NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING', - 'NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS', - 'NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS', - 'NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID', - 'NV83DE_CTRL_FIFO', 'NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS', - 'NV83DE_CTRL_GR', 'NV83DE_CTRL_INTERNAL', 'NV83DE_CTRL_RESERVED', - 'NV83DE_MMU_FAULT_INFO', 'NV83DE_SM_ERROR_STATE_REGISTERS', - 'NV9010_VBLANK_CALLBACK', 'NV90F1_CTRL_CMD_NULL', - 'NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES', - 'NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT', - 'NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE', - 'NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO', - 'NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF', - 'NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO', - 'NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES', - 'NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES', 'NV90F1_CTRL_RESERVED', - 'NV90F1_CTRL_VASPACE', - 'NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS', - 'NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS', - 'NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS', - 'NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_BIND_PARAMS', 'NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_CMD_BIND', 'NVA06C_CTRL_CMD_GET_INFO', - 'NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL', - 'NVA06C_CTRL_CMD_GET_TIMESLICE', - 'NVA06C_CTRL_CMD_GPFIFO_SCHEDULE', - 'NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE', - 'NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS', - 'NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE', - 'NVA06C_CTRL_CMD_MAKE_REALTIME', 'NVA06C_CTRL_CMD_NULL', - 'NVA06C_CTRL_CMD_PREEMPT', - 'NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US', - 'NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE', - 'NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL', - 'NVA06C_CTRL_CMD_SET_TIMESLICE', 'NVA06C_CTRL_GET_INFO_PARAMS', - 'NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS', - 'NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_GET_TIMESLICE_PARAMS', - 'NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_GPFIFO', 'NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS', - 'NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_LOW', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM', - 'NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS', 'NVA06C_CTRL_INTERNAL', - 'NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS', - 'NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES', - 'NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS', - 'NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS', - 'NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_MAKE_REALTIME_PARAMS', - 'NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_PREEMPT_PARAMS', - 'NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', - 'NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', - 'NVA06C_CTRL_RESERVED', 'NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS', - 'NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_SET_TIMESLICE_PARAMS', - 'NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_TIMESLICE_PARAMS', 'NVA081_VGPU_CONFIG', - 'NVA084_KERNEL_HOST_VGPU_DEVICE', 'NVAL_MAP_DIRECTION_DOWN', - 'NVAL_MAP_DIRECTION_UP', 'NVAL_MAX_BANKS', 'NVB4B7_VIDEO_ENCODER', - 'NVB8B0_VIDEO_DECODER', 'NVB8D1_VIDEO_NVJPG', 'NVB8FA_VIDEO_OFA', - 'NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION', - 'NVC36F_CTRL_CMD_EVENT_SET_TRIGGER', - 'NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES', - 'NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN', - 'NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS', - 'NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX', - 'NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER', - 'NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN', - 'NVC36F_CTRL_CMD_NULL', 'NVC36F_CTRL_EVENT', 'NVC36F_CTRL_GPFIFO', - 'NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS', - 'NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS', - 'NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_INTERNAL', - 'NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS', - 'NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID', - 'NVC36F_CTRL_RESERVED', 'NVC371_DISP_SF_USER', - 'NVC372_DISPLAY_SW', 'NVC4B0_VIDEO_DECODER', - 'NVC4B7_VIDEO_ENCODER', 'NVC4D1_VIDEO_NVJPG', - 'NVC56F_CLEAR_FAULTED', 'NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED', - 'NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED', - 'NVC56F_DMA_ENDSEG_OPCODE_VALUE', 'NVC56F_DMA_IMMD_OPCODE_VALUE', - 'NVC56F_DMA_INCR_OPCODE_VALUE', 'NVC56F_DMA_NONINCR_OPCODE_VALUE', - 'NVC56F_DMA_NOP', 'NVC56F_DMA_ONEINCR_OPCODE_VALUE', - 'NVC56F_DMA_OPCODE3_NONE', 'NVC56F_DMA_OPCODE_METHOD', - 'NVC56F_DMA_OPCODE_NONINC_METHOD', - 'NVC56F_DMA_SEC_OP_END_PB_SEGMENT', - 'NVC56F_DMA_SEC_OP_GRP0_USE_TERT', - 'NVC56F_DMA_SEC_OP_GRP2_USE_TERT', - 'NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD', - 'NVC56F_DMA_SEC_OP_INC_METHOD', - 'NVC56F_DMA_SEC_OP_NON_INC_METHOD', 'NVC56F_DMA_SEC_OP_ONE_INC', - 'NVC56F_DMA_SEC_OP_RESERVED6', - 'NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE', - 'NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE', - 'NVC56F_DMA_TERT_OP_GRP0_INC_METHOD', - 'NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK', - 'NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK', - 'NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK', - 'NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD', - 'NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE', 'NVC56F_FB_FLUSH', - 'NVC56F_GP_ENTRY0_FETCH_CONDITIONAL', - 'NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL', - 'NVC56F_GP_ENTRY1_LEVEL_MAIN', - 'NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE', - 'NVC56F_GP_ENTRY1_OPCODE_GP_CRC', - 'NVC56F_GP_ENTRY1_OPCODE_ILLEGAL', 'NVC56F_GP_ENTRY1_OPCODE_NOP', - 'NVC56F_GP_ENTRY1_OPCODE_PB_CRC', 'NVC56F_GP_ENTRY1_SYNC_PROCEED', - 'NVC56F_GP_ENTRY1_SYNC_WAIT', 'NVC56F_GP_ENTRY__SIZE', - 'NVC56F_ILLEGAL', 'NVC56F_MEM_OP_A', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS', - 'NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN', 'NVC56F_MEM_OP_B', - 'NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES', - 'NVC56F_MEM_OP_C', 'NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR', - 'NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START', - 'NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL', - 'NVC56F_MEM_OP_D', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC', - 'NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED', - 'NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR', - 'NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS', - 'NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY', - 'NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE', - 'NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE', - 'NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS', - 'NVC56F_MEM_OP_D_OPERATION_MEMBAR', - 'NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE', - 'NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED', - 'NVC56F_NON_STALL_INTERRUPT', 'NVC56F_NOP', - 'NVC56F_NUMBER_OF_SUBCHANNELS', 'NVC56F_SEMAPHOREA', - 'NVC56F_SEMAPHOREB', 'NVC56F_SEMAPHOREC', 'NVC56F_SEMAPHORED', - 'NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED', - 'NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED', - 'NVC56F_SEMAPHORED_FORMAT_SIGNED', - 'NVC56F_SEMAPHORED_FORMAT_UNSIGNED', - 'NVC56F_SEMAPHORED_OPERATION_ACQUIRE', - 'NVC56F_SEMAPHORED_OPERATION_ACQ_AND', - 'NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ', - 'NVC56F_SEMAPHORED_OPERATION_REDUCTION', - 'NVC56F_SEMAPHORED_OPERATION_RELEASE', - 'NVC56F_SEMAPHORED_REDUCTION_ADD', - 'NVC56F_SEMAPHORED_REDUCTION_AND', - 'NVC56F_SEMAPHORED_REDUCTION_DEC', - 'NVC56F_SEMAPHORED_REDUCTION_INC', - 'NVC56F_SEMAPHORED_REDUCTION_MAX', - 'NVC56F_SEMAPHORED_REDUCTION_MIN', - 'NVC56F_SEMAPHORED_REDUCTION_OR', - 'NVC56F_SEMAPHORED_REDUCTION_XOR', - 'NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE', - 'NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE', - 'NVC56F_SEMAPHORED_RELEASE_WFI_DIS', - 'NVC56F_SEMAPHORED_RELEASE_WFI_EN', 'NVC56F_SEM_ADDR_HI', - 'NVC56F_SEM_ADDR_LO', 'NVC56F_SEM_EXECUTE', - 'NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS', - 'NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR', - 'NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ', - 'NVC56F_SEM_EXECUTE_OPERATION_REDUCTION', - 'NVC56F_SEM_EXECUTE_OPERATION_RELEASE', - 'NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT', - 'NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT', - 'NVC56F_SEM_EXECUTE_REDUCTION_DEC', - 'NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED', - 'NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED', - 'NVC56F_SEM_EXECUTE_REDUCTION_IADD', - 'NVC56F_SEM_EXECUTE_REDUCTION_IAND', - 'NVC56F_SEM_EXECUTE_REDUCTION_IMAX', - 'NVC56F_SEM_EXECUTE_REDUCTION_IMIN', - 'NVC56F_SEM_EXECUTE_REDUCTION_INC', - 'NVC56F_SEM_EXECUTE_REDUCTION_IOR', - 'NVC56F_SEM_EXECUTE_REDUCTION_IXOR', - 'NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS', - 'NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN', - 'NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS', - 'NVC56F_SEM_EXECUTE_RELEASE_WFI_EN', 'NVC56F_SEM_PAYLOAD_HI', - 'NVC56F_SEM_PAYLOAD_LO', 'NVC56F_SET_OBJECT', - 'NVC56F_SET_OBJECT_ENGINE_SW', 'NVC56F_SET_REFERENCE', - 'NVC56F_WFI', 'NVC56F_WFI_SCOPE_ALL', - 'NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE', - 'NVC56F_WFI_SCOPE_CURRENT_VEID', 'NVC56F_YIELD', - 'NVC56F_YIELD_OP_NOP', 'NVC56F_YIELD_OP_TSG', 'NVC570_DISPLAY', - 'NVC573_DISP_CAPABILITIES', 'NVC57A_CURSOR_IMM_CHANNEL_PIO', - 'NVC57B_WINDOW_IMM_CHANNEL_DMA', 'NVC57D_CORE_CHANNEL_DMA', - 'NVC57E_WINDOW_CHANNEL_DMA', 'NVC670_DISPLAY', - 'NVC671_DISP_SF_USER', 'NVC673_DISP_CAPABILITIES', - 'NVC67A_CURSOR_IMM_CHANNEL_PIO', 'NVC67B_WINDOW_IMM_CHANNEL_DMA', - 'NVC67D_CORE_CHANNEL_DMA', 'NVC67E_WINDOW_CHANNEL_DMA', - 'NVC6B0_VIDEO_DECODER', 'NVC6B5_DST_ORIGIN_X', - 'NVC6B5_DST_ORIGIN_Y', 'NVC6B5_LAUNCH_DMA', - 'NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE', - 'NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED', - 'NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED', - 'NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE', - 'NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE', - 'NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH', - 'NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL', - 'NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL', - 'NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL', - 'NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS', - 'NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING', - 'NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE', - 'NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING', - 'NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE', - 'NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE', - 'NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH', - 'NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL', - 'NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL', - 'NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE', - 'NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID', 'NVC6B5_LINE_COUNT', - 'NVC6B5_LINE_LENGTH_IN', 'NVC6B5_NOP', 'NVC6B5_OFFSET_IN_LOWER', - 'NVC6B5_OFFSET_IN_UPPER', 'NVC6B5_OFFSET_OUT_LOWER', - 'NVC6B5_OFFSET_OUT_UPPER', 'NVC6B5_PITCH_IN', 'NVC6B5_PITCH_OUT', - 'NVC6B5_PM_TRIGGER', 'NVC6B5_PM_TRIGGER_END', - 'NVC6B5_SET_DST_BLOCK_SIZE', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC6B5_SET_DST_DEPTH', - 'NVC6B5_SET_DST_HEIGHT', 'NVC6B5_SET_DST_LAYER', - 'NVC6B5_SET_DST_ORIGIN', 'NVC6B5_SET_DST_PHYS_MODE', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM', 'NVC6B5_SET_DST_WIDTH', - 'NVC6B5_SET_REMAP_COMPONENTS', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE', - 'NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y', - 'NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE', - 'NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO', - 'NVC6B5_SET_REMAP_CONST_A', 'NVC6B5_SET_REMAP_CONST_B', - 'NVC6B5_SET_RENDER_ENABLE_A', 'NVC6B5_SET_RENDER_ENABLE_B', - 'NVC6B5_SET_RENDER_ENABLE_C', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE', 'NVC6B5_SET_SEMAPHORE_A', - 'NVC6B5_SET_SEMAPHORE_B', 'NVC6B5_SET_SEMAPHORE_PAYLOAD', - 'NVC6B5_SET_SRC_BLOCK_SIZE', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC6B5_SET_SRC_DEPTH', - 'NVC6B5_SET_SRC_HEIGHT', 'NVC6B5_SET_SRC_LAYER', - 'NVC6B5_SET_SRC_ORIGIN', 'NVC6B5_SET_SRC_PHYS_MODE', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM', 'NVC6B5_SET_SRC_WIDTH', - 'NVC6B5_SRC_ORIGIN_X', 'NVC6B5_SRC_ORIGIN_Y', - 'NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT', - 'NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE', - 'NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE', - 'NVC6C0_CHECK_COMPUTE_CLASS_VERSION', 'NVC6C0_CHECK_QMD_VERSION', - 'NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER', - 'NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER', - 'NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN', - 'NVC6C0_FE_ATOMIC_SEQUENCE_END', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL', - 'NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE', - 'NVC6C0_INVALIDATE_SHADER_CACHES', - 'NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE', - 'NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE', - 'NVC6C0_INVALIDATE_SKED_CACHES', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL', - 'NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE', - 'NVC6C0_LAUNCH_DMA', - 'NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE', - 'NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY', - 'NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE', - 'NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH', - 'NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT', - 'NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE', - 'NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE', - 'NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE', - 'NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR', - 'NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR', - 'NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS', - 'NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD', - 'NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE', - 'NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE', 'NVC6C0_LINE_COUNT', - 'NVC6C0_LINE_LENGTH_IN', 'NVC6C0_LOAD_INLINE_DATA', - 'NVC6C0_NOTIFY', 'NVC6C0_NOTIFY_TYPE_WRITE_ONLY', - 'NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN', 'NVC6C0_NO_OPERATION', - 'NVC6C0_OFFSET_OUT', 'NVC6C0_OFFSET_OUT_UPPER', - 'NVC6C0_PERFMON_TRANSFER', 'NVC6C0_PIPE_NOP', 'NVC6C0_PITCH_OUT', - 'NVC6C0_PM_TRIGGER', 'NVC6C0_PM_TRIGGER_WFI', - 'NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE', - 'NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE', - 'NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE', - 'NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID', - 'NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE', - 'NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVC6C0_QMDV02_03_IS_QUEUE_FALSE', - 'NVC6C0_QMDV02_03_IS_QUEUE_TRUE', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR', - 'NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR', - 'NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE', - 'NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE', - 'NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY', - 'NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE', - 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'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE', - 'NVC6C0_SEND_SIGNALING_PCAS_B', - 'NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE', - 'NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE', - 'NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE', - 'NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE', - 'NVC6C0_SET_BINDLESS_TEXTURE', 'NVC6C0_SET_COMPUTE_CLASS_VERSION', - 'NVC6C0_SET_CWD_REF_COUNTER', 'NVC6C0_SET_CWD_SLOT_COUNT', - 'NVC6C0_SET_DST_BLOCK_SIZE', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC6C0_SET_DST_DEPTH', - 'NVC6C0_SET_DST_HEIGHT', 'NVC6C0_SET_DST_LAYER', - 'NVC6C0_SET_DST_ORIGIN_BYTES_X', - 'NVC6C0_SET_DST_ORIGIN_SAMPLES_Y', 'NVC6C0_SET_DST_WIDTH', - 'NVC6C0_SET_FALCON00', 'NVC6C0_SET_FALCON01', - 'NVC6C0_SET_FALCON02', 'NVC6C0_SET_FALCON03', - 'NVC6C0_SET_FALCON04', 'NVC6C0_SET_FALCON05', - 'NVC6C0_SET_FALCON06', 'NVC6C0_SET_FALCON07', - 'NVC6C0_SET_FALCON08', 'NVC6C0_SET_FALCON09', - 'NVC6C0_SET_FALCON10', 'NVC6C0_SET_FALCON11', - 'NVC6C0_SET_FALCON12', 'NVC6C0_SET_FALCON13', - 'NVC6C0_SET_FALCON14', 'NVC6C0_SET_FALCON15', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_A', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_B', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE', - 'NVC6C0_SET_I2M_SEMAPHORE_A', 'NVC6C0_SET_I2M_SEMAPHORE_B', - 'NVC6C0_SET_I2M_SEMAPHORE_C', 'NVC6C0_SET_I2M_SPARE_NOOP00', - 'NVC6C0_SET_I2M_SPARE_NOOP01', 'NVC6C0_SET_I2M_SPARE_NOOP02', - 'NVC6C0_SET_I2M_SPARE_NOOP03', 'NVC6C0_SET_INLINE_QMD_ADDRESS_A', - 'NVC6C0_SET_INLINE_QMD_ADDRESS_B', - 'NVC6C0_SET_INSTRUMENTATION_METHOD_DATA', - 'NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER', 'NVC6C0_SET_NOTIFY_A', - 'NVC6C0_SET_NOTIFY_B', 'NVC6C0_SET_OBJECT', - 'NVC6C0_SET_QMD_VERSION', 'NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A', - 'NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE', - 'NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE', - 'NVC6C0_SET_RENDER_ENABLE_A', 'NVC6C0_SET_RENDER_ENABLE_B', - 'NVC6C0_SET_RENDER_ENABLE_C', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER', - 'NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE', - 'NVC6C0_SET_REPORT_SEMAPHORE_A', 'NVC6C0_SET_REPORT_SEMAPHORE_B', - 'NVC6C0_SET_REPORT_SEMAPHORE_C', 'NVC6C0_SET_REPORT_SEMAPHORE_D', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS', - 'NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD', - 'NVC6C0_SET_RESERVED_SW_METHOD00', - 'NVC6C0_SET_RESERVED_SW_METHOD01', - 'NVC6C0_SET_RESERVED_SW_METHOD02', - 'NVC6C0_SET_RESERVED_SW_METHOD03', - 'NVC6C0_SET_RESERVED_SW_METHOD04', - 'NVC6C0_SET_RESERVED_SW_METHOD05', - 'NVC6C0_SET_RESERVED_SW_METHOD06', - 'NVC6C0_SET_RESERVED_SW_METHOD07', - 'NVC6C0_SET_RESERVED_SW_METHOD08', - 'NVC6C0_SET_RESERVED_SW_METHOD09', - 'NVC6C0_SET_RESERVED_SW_METHOD10', - 'NVC6C0_SET_RESERVED_SW_METHOD11', - 'NVC6C0_SET_RESERVED_SW_METHOD12', - 'NVC6C0_SET_RESERVED_SW_METHOD13', - 'NVC6C0_SET_RESERVED_SW_METHOD14', - 'NVC6C0_SET_RESERVED_SW_METHOD15', 'NVC6C0_SET_SCG_CONTROL', - 'NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE', - 'NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE', - 'NVC6C0_SET_SHADER_CACHE_CONTROL', - 'NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE', - 'NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE', - 'NVC6C0_SET_SHADER_EXCEPTIONS', - 'NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE', - 'NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_A', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_B', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A', - 'NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B', - 'NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER', - 'NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER', - 'NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL', - 'NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A', - 'NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B', - 'NVC6C0_SET_SKED_CACHE_CONTROL', - 'NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE', - 'NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE', - 'NVC6C0_SET_SM_SCG_CONTROL', - 'NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE', - 'NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE', - 'NVC6C0_SET_SM_TIMEOUT_INTERVAL', 'NVC6C0_SET_SPARE00', - 'NVC6C0_SET_SPARE01', 'NVC6C0_SET_SPARE02', 'NVC6C0_SET_SPARE03', - 'NVC6C0_SET_SPA_VERSION', 'NVC6C0_SET_TEX_HEADER_POOL_A', - 'NVC6C0_SET_TEX_HEADER_POOL_B', 'NVC6C0_SET_TEX_HEADER_POOL_C', - 'NVC6C0_SET_TEX_SAMPLER_POOL_A', 'NVC6C0_SET_TEX_SAMPLER_POOL_B', - 'NVC6C0_SET_TEX_SAMPLER_POOL_C', 'NVC6C0_SET_TRAP_HANDLER_A', - 'NVC6C0_SET_TRAP_HANDLER_B', - 'NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A', - 'NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B', - 'NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C', - 'NVC6C0_START_SHADER_PERFORMANCE_COUNTER', - 'NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER', 'NVC6C0_WAIT_FOR_IDLE', - 'NVC6FA_VIDEO_OFA', 'NVC770_DISPLAY', 'NVC771_DISP_SF_USER', - 'NVC773_DISP_CAPABILITIES', 'NVC77D_CORE_CHANNEL_DMA', - 'NVC77F_ANY_CHANNEL_DMA', 'NVC7B0_VIDEO_DECODER', - 'NVC7B7_VIDEO_ENCODER', 'NVC7FA_VIDEO_OFA', - 'NVC86F_GP_ENTRY0_FETCH_CONDITIONAL', - 'NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL', - 'NVC86F_GP_ENTRY1_LEVEL_MAIN', - 'NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE', - 'NVC86F_GP_ENTRY1_OPCODE_GP_CRC', - 'NVC86F_GP_ENTRY1_OPCODE_ILLEGAL', 'NVC86F_GP_ENTRY1_OPCODE_NOP', - 'NVC86F_GP_ENTRY1_OPCODE_PB_CRC', - 'NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE', - 'NVC86F_GP_ENTRY1_SYNC_PROCEED', 'NVC86F_GP_ENTRY1_SYNC_WAIT', - 'NVC86F_GP_ENTRY__SIZE', 'NVC86F_MEM_OP_A', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS', - 'NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN', 'NVC86F_MEM_OP_B', - 'NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES', - 'NVC86F_MEM_OP_C', 'NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR', - 'NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START', - 'NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL', - 'NVC86F_MEM_OP_D', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC', - 'NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED', - 'NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED', - 'NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP', - 'NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR', - 'NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS', - 'NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY', - 'NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE', - 'NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE', - 'NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS', - 'NVC86F_MEM_OP_D_OPERATION_MEMBAR', - 'NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION', - 'NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE', - 'NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED', - 'NVC86F_SEM_ADDR_HI', 'NVC86F_SEM_ADDR_LO', 'NVC86F_SEM_EXECUTE', - 'NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE', - 'NVC86F_SEM_EXECUTE_OPERATION_RELEASE', - 'NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT', - 'NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS', 'NVC86F_SEM_PAYLOAD_HI', - 'NVC86F_SEM_PAYLOAD_LO', 'NVC86F_SET_OBJECT', 'NVC86F_WFI', - 'NVC86F_WFI_SCOPE_ALL', 'NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE', - 'NVC86F_WFI_SCOPE_CURRENT_VEID', - 'NVC96F_GP_ENTRY0_FETCH_CONDITIONAL', - 'NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL', - 'NVC96F_GP_ENTRY1_LEVEL_MAIN', - 'NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE', - 'NVC96F_GP_ENTRY1_OPCODE_GP_CRC', - 'NVC96F_GP_ENTRY1_OPCODE_ILLEGAL', 'NVC96F_GP_ENTRY1_OPCODE_NOP', - 'NVC96F_GP_ENTRY1_OPCODE_PB_CRC', - 'NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE', - 'NVC96F_GP_ENTRY1_SYNC_PROCEED', 'NVC96F_GP_ENTRY1_SYNC_WAIT', - 'NVC96F_GP_ENTRY__SIZE', 'NVC96F_SEM_ADDR_HI', - 'NVC96F_SEM_ADDR_LO', 'NVC96F_SEM_EXECUTE', - 'NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE', - 'NVC96F_SEM_EXECUTE_OPERATION_RELEASE', - 'NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT', - 'NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS', 'NVC96F_SEM_PAYLOAD_HI', - 'NVC96F_SEM_PAYLOAD_LO', 'NVC96F_SET_OBJECT', 'NVC970_DISPLAY', - 'NVC971_DISP_SF_USER', 'NVC973_DISP_CAPABILITIES', - 'NVC97A_CURSOR_IMM_CHANNEL_PIO', 'NVC97B_WINDOW_IMM_CHANNEL_DMA', - 'NVC97D_CORE_CHANNEL_DMA', 'NVC97E_WINDOW_CHANNEL_DMA', - 'NVC9B0_VIDEO_DECODER', 'NVC9B5_DST_ORIGIN_X', - 'NVC9B5_DST_ORIGIN_Y', 'NVC9B5_LAUNCH_DMA', - 'NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED', - 'NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE', - 'NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE', - 'NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED', - 'NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED', - 'NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE', - 'NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE', - 'NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH', - 'NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL', - 'NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL', - 'NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL', - 'NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS', - 'NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING', - 'NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE', - 'NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING', - 'NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP', - 'NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP', - 'NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR', - 'NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH', - 'NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL', - 'NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL', - 'NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE', - 'NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID', 'NVC9B5_LINE_COUNT', - 'NVC9B5_LINE_LENGTH_IN', 'NVC9B5_NOP', 'NVC9B5_OFFSET_IN_LOWER', - 'NVC9B5_OFFSET_IN_UPPER', 'NVC9B5_OFFSET_OUT_LOWER', - 'NVC9B5_OFFSET_OUT_UPPER', 'NVC9B5_PITCH_IN', 'NVC9B5_PITCH_OUT', - 'NVC9B5_PM_TRIGGER', 'NVC9B5_PM_TRIGGER_END', - 'NVC9B5_RESERVED_SET_AESCOUNTER', - 'NVC9B5_SET_COMPRESSION_PARAMETERS', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS', - 'NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS', - 'NVC9B5_SET_DECOMPRESS_CHECKSUM', - 'NVC9B5_SET_DECOMPRESS_OUT_LENGTH', - 'NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER', - 'NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER', - 'NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER', - 'NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER', - 'NVC9B5_SET_DECRYPT_IV0', 'NVC9B5_SET_DECRYPT_IV1', - 'NVC9B5_SET_DECRYPT_IV2', 'NVC9B5_SET_DST_BLOCK_SIZE', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC9B5_SET_DST_DEPTH', - 'NVC9B5_SET_DST_HEIGHT', 'NVC9B5_SET_DST_LAYER', - 'NVC9B5_SET_DST_ORIGIN', 'NVC9B5_SET_DST_PHYS_MODE', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM', 'NVC9B5_SET_DST_WIDTH', - 'NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER', - 'NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER', - 'NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER', - 'NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER', - 'NVC9B5_SET_MEMORY_SCRUB_PARAMETERS', - 'NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE', - 'NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE', - 'NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER', - 'NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER', - 'NVC9B5_SET_MONITORED_FENCE_TYPE', - 'NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE', - 'NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT', - 'NVC9B5_SET_REMAP_COMPONENTS', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE', - 'NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y', - 'NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE', - 'NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO', - 'NVC9B5_SET_REMAP_CONST_A', 'NVC9B5_SET_REMAP_CONST_B', - 'NVC9B5_SET_RENDER_ENABLE_A', 'NVC9B5_SET_RENDER_ENABLE_B', - 'NVC9B5_SET_RENDER_ENABLE_C', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL', - 'NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE', - 'NVC9B5_SET_SECURE_COPY_MODE', - 'NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT', - 'NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM', - 'NVC9B5_SET_SEMAPHORE_A', 'NVC9B5_SET_SEMAPHORE_B', - 'NVC9B5_SET_SEMAPHORE_PAYLOAD', - 'NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER', 'NVC9B5_SET_SRC_BLOCK_SIZE', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS', - 'NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB', 'NVC9B5_SET_SRC_DEPTH', - 'NVC9B5_SET_SRC_HEIGHT', 'NVC9B5_SET_SRC_LAYER', - 'NVC9B5_SET_SRC_ORIGIN', 'NVC9B5_SET_SRC_PHYS_MODE', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM', - 'NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM', 'NVC9B5_SET_SRC_WIDTH', - 'NVC9B5_SRC_ORIGIN_X', 'NVC9B5_SRC_ORIGIN_Y', - 'NVC9B7_VIDEO_ENCODER', 'NVC9D1_VIDEO_NVJPG', 'NVC9FA_VIDEO_OFA', - 'NVCA70_DISPLAY', 'NVCA71_DISP_SF_USER', - 'NVCA73_DISP_CAPABILITIES', 'NVCA7A_CURSOR_IMM_CHANNEL_PIO', - 'NVCA7B_WINDOW_IMM_CHANNEL_DMA', 'NVCA7D_CORE_CHANNEL_DMA', - 'NVCA7E_WINDOW_CHANNEL_DMA', 'NVCB33_CTRL_CONF_COMPUTE', - 'NVCB33_CTRL_RESERVED', 'NVCDB0_VIDEO_DECODER', - 'NVCDD1_VIDEO_NVJPG', 'NVCDFA_VIDEO_OFA', - 'NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE', - 'NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE', - 'NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK', - 'NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32', - 'NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING', - 'NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE', - 'NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE', - 'NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE', - 'NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE', - 'NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE', - 'NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE', - 'NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE', - 'NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE', - 'NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE', - 'NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE', - 'NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE', - 'NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE', - 'NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE', - 'NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE', - 'NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE', - 'NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE', - 'NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE', - 'NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA', - 'NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL', - 'NVCEC0_QMDV04_01_QMD_TYPE_QUEUE', - 'NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE', - 'NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE', - 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'NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE', - 'NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA', - 'NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL', - 'NVCEC0_QMDV05_01_QMD_TYPE_QUEUE', - 'NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE', - 'NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR', - 'NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE', - 'NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR', - 'NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR', - 'NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS', - 'NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD', - 'NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE', - 'NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL', - 'NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE', - 'NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE', - 'NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY', - 'NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX', - 'NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE', - 'NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE', - 'NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE', - 'NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE', - 'NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE', - 'NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH', - 'NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST', - 'NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE', - 'NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE', - 'NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE', - 'NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE', - 'NVCFB0_VIDEO_DECODER', 'NVCFB7_VIDEO_ENCODER', - 'NVCFD1_VIDEO_NVJPG', 'NVCFFA_VIDEO_OFA', 'NVENC_SW_SESSION', - 'NVFBC_SW_SESSION', 'NVLINK_EOM_CONTROL_CONFIG_EOM', - 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'NVOS02_FLAGS_MAPPING_NO_MAP', - 'NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT', - 'NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED', - 'NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED', - 'NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT', - 'NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED', - 'NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS', - 'NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS', - 'NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE', - 'NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE', - 'NVOS02_PARAMETERS', 'NVOS03_FLAGS_ACCESS_READ_ONLY', - 'NVOS03_FLAGS_ACCESS_READ_WRITE', - 'NVOS03_FLAGS_ACCESS_WRITE_ONLY', - 'NVOS03_FLAGS_CACHE_SNOOP_DISABLE', - 'NVOS03_FLAGS_CACHE_SNOOP_ENABLE', - 'NVOS03_FLAGS_GPU_MAPPABLE_DISABLE', - 'NVOS03_FLAGS_GPU_MAPPABLE_ENABLE', - 'NVOS03_FLAGS_HASH_TABLE_DISABLE', - 'NVOS03_FLAGS_HASH_TABLE_ENABLE', 'NVOS03_FLAGS_MAPPING_KERNEL', - 'NVOS03_FLAGS_MAPPING_NONE', 'NVOS03_FLAGS_PREALLOCATE_DISABLE', - 'NVOS03_FLAGS_PREALLOCATE_ENABLE', 'NVOS03_FLAGS_PTE_KIND_BL', - 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'NVOS04_FLAGS_VPR_FALSE', 'NVOS04_FLAGS_VPR_TRUE', - 'NVOS05_PARAMETERS', 'NVOS10_EVENT_KERNEL_CALLBACK', - 'NVOS10_EVENT_KERNEL_CALLBACK_EX', 'NVOS20_COMMAND_STRING_PRINT', - 'NVOS20_COMMAND_unused0001', 'NVOS20_COMMAND_unused0002', - 'NVOS21_PARAMETERS', 'NVOS2C_PARAMETERS', - 'NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK', - 'NVOS30_FLAGS_BEHAVIOR_QUERY', 'NVOS30_FLAGS_BEHAVIOR_SLEEP', - 'NVOS30_FLAGS_BEHAVIOR_SPIN', 'NVOS30_FLAGS_CHANNEL_LIST', - 'NVOS30_FLAGS_CHANNEL_SINGLE', 'NVOS30_FLAGS_IDLE_ACTIVECHANNELS', - 'NVOS30_FLAGS_IDLE_ALL_ENGINES', - 'NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR', - 'NVOS30_FLAGS_IDLE_CACHE1', 'NVOS30_FLAGS_IDLE_CALLBACKS', - 'NVOS30_FLAGS_IDLE_CE0', 'NVOS30_FLAGS_IDLE_CE1', - 'NVOS30_FLAGS_IDLE_CE2', 'NVOS30_FLAGS_IDLE_CE3', - 'NVOS30_FLAGS_IDLE_CE4', 'NVOS30_FLAGS_IDLE_CE5', - 'NVOS30_FLAGS_IDLE_CIPHER_DMA', 'NVOS30_FLAGS_IDLE_GRAPHICS', - 'NVOS30_FLAGS_IDLE_MOTION_ESTIMATION', 'NVOS30_FLAGS_IDLE_MPEG', - 'NVOS30_FLAGS_IDLE_MSENC', 'NVOS30_FLAGS_IDLE_MSPDEC', - 'NVOS30_FLAGS_IDLE_MSPPP', 'NVOS30_FLAGS_IDLE_MSVLD', - 'NVOS30_FLAGS_IDLE_NVDEC0', 'NVOS30_FLAGS_IDLE_NVDEC1', - 'NVOS30_FLAGS_IDLE_NVDEC2', 'NVOS30_FLAGS_IDLE_NVENC0', - 'NVOS30_FLAGS_IDLE_NVENC1', 'NVOS30_FLAGS_IDLE_NVENC2', - 'NVOS30_FLAGS_IDLE_NVJPG', 'NVOS30_FLAGS_IDLE_PUSH_BUFFER', - 'NVOS30_FLAGS_IDLE_SEC', 'NVOS30_FLAGS_IDLE_VIC', - 'NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR', - 'NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO', - 'NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES', 'NVOS30_PARAMETERS', - 'NVOS32_ALLOC_COMPR_COVG_BITS_1', - 'NVOS32_ALLOC_COMPR_COVG_BITS_2', - 'NVOS32_ALLOC_COMPR_COVG_BITS_4', - 'NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT', - 'NVOS32_ALLOC_COMPR_COVG_SCALE', - 'NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN', - 'NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF', - 'NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE', - 'NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT', - 'NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED', - 'NVOS32_ALLOC_FLAGS_BANK_FORCE', - 'NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN', - 'NVOS32_ALLOC_FLAGS_BANK_GROW_UP', 'NVOS32_ALLOC_FLAGS_BANK_HINT', - 'NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY', - 'NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED', - 'NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE', - 'NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE', - 'NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE', - 'NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX', - 'NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN', - 'NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP', - 'NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC', - 'NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT', - 'NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP', - 'NVOS32_ALLOC_FLAGS_LAZY', 'NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED', - 'NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE', - 'NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE', - 'NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_ALLOC_FLAGS_NO_SCANOUT', - 'NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM', - 'NVOS32_ALLOC_FLAGS_PITCH_FORCE', - 'NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY', - 'NVOS32_ALLOC_FLAGS_PROTECTED', - 'NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD', - 'NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC', - 'NVOS32_ALLOC_FLAGS_SPARSE', - 'NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED', - 'NVOS32_ALLOC_FLAGS_USER_READ_ONLY', - 'NVOS32_ALLOC_FLAGS_USE_BEGIN_END', 'NVOS32_ALLOC_FLAGS_VIRTUAL', - 'NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY', 'NVOS32_ALLOC_FLAGS_WPR1', - 'NVOS32_ALLOC_FLAGS_WPR2', - 'NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED', - 'NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X', - 'NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC', - 'NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB', - 'NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW', - 'NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW', - 'NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z', - 'NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z', - 'NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS', - 'NVOS32_ATTR2_32BIT_POINTER_DISABLE', - 'NVOS32_ATTR2_32BIT_POINTER_ENABLE', - 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'NVOS32_ATTR2_PAGE_OFFLINING_OFF', - 'NVOS32_ATTR2_PAGE_OFFLINING_ON', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB', - 'NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT', - 'NVOS32_ATTR2_PREFER_2C_NO', 'NVOS32_ATTR2_PREFER_2C_YES', - 'NVOS32_ATTR2_PRIORITY_DEFAULT', 'NVOS32_ATTR2_PRIORITY_HIGH', - 'NVOS32_ATTR2_PRIORITY_LOW', - 'NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY', - 'NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE', - 'NVOS32_ATTR2_PROTECTION_USER_READ_ONLY', - 'NVOS32_ATTR2_PROTECTION_USER_READ_WRITE', - 'NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE', - 'NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE', - 'NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT', - 'NVOS32_ATTR2_SMMU_ON_GPU_DISABLE', - 'NVOS32_ATTR2_SMMU_ON_GPU_ENABLE', 'NVOS32_ATTR2_USE_EGM_FALSE', - 'NVOS32_ATTR2_USE_EGM_TRUE', - 'NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE', - 'NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE', - 'NVOS32_ATTR2_ZBC_DEFAULT', 'NVOS32_ATTR2_ZBC_INVALID', - 'NVOS32_ATTR2_ZBC_PREFER_NO_ZBC', 'NVOS32_ATTR2_ZBC_PREFER_ZBC', - 'NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC', - 'NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO', - 'NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES', - 'NVOS32_ATTR_AA_SAMPLES_1', 'NVOS32_ATTR_AA_SAMPLES_16', - 'NVOS32_ATTR_AA_SAMPLES_2', 'NVOS32_ATTR_AA_SAMPLES_4', - 'NVOS32_ATTR_AA_SAMPLES_4_ROTATED', - 'NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16', - 'NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8', 'NVOS32_ATTR_AA_SAMPLES_6', - 'NVOS32_ATTR_AA_SAMPLES_8', 'NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16', - 'NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32', - 'NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO', - 'NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES', - 'NVOS32_ATTR_COHERENCY_CACHED', 'NVOS32_ATTR_COHERENCY_UNCACHED', - 'NVOS32_ATTR_COHERENCY_WRITE_BACK', - 'NVOS32_ATTR_COHERENCY_WRITE_COMBINE', - 'NVOS32_ATTR_COHERENCY_WRITE_PROTECT', - 'NVOS32_ATTR_COHERENCY_WRITE_THROUGH', - 'NVOS32_ATTR_COLOR_PACKING_A8R8G8B8', - 'NVOS32_ATTR_COLOR_PACKING_X8R8G8B8', 'NVOS32_ATTR_COMPR_ANY', - 'NVOS32_ATTR_COMPR_COVG_DEFAULT', - 'NVOS32_ATTR_COMPR_COVG_PROVIDED', - 'NVOS32_ATTR_COMPR_DISABLE_PLC_ANY', 'NVOS32_ATTR_COMPR_NONE', - 'NVOS32_ATTR_COMPR_PLC_ANY', 'NVOS32_ATTR_COMPR_PLC_REQUIRED', - 'NVOS32_ATTR_COMPR_REQUIRED', 'NVOS32_ATTR_DEPTH_128', - 'NVOS32_ATTR_DEPTH_16', 'NVOS32_ATTR_DEPTH_24', - 'NVOS32_ATTR_DEPTH_32', 'NVOS32_ATTR_DEPTH_64', - 'NVOS32_ATTR_DEPTH_8', 'NVOS32_ATTR_DEPTH_UNKNOWN', - 'NVOS32_ATTR_FORMAT_BLOCK_LINEAR', - 'NVOS32_ATTR_FORMAT_HIGH_FIELD', 'NVOS32_ATTR_FORMAT_LOW_FIELD', - 'NVOS32_ATTR_FORMAT_PITCH', 'NVOS32_ATTR_FORMAT_SWIZZLED', - 'NVOS32_ATTR_LOCATION_ANY', 'NVOS32_ATTR_LOCATION_PCI', - 'NVOS32_ATTR_LOCATION_VIDMEM', 'NVOS32_ATTR_NONE', - 'NVOS32_ATTR_PAGE_SIZE_4KB', 'NVOS32_ATTR_PAGE_SIZE_BIG', - 'NVOS32_ATTR_PAGE_SIZE_DEFAULT', 'NVOS32_ATTR_PAGE_SIZE_HUGE', - 'NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS', - 'NVOS32_ATTR_PHYSICALITY_CONTIGUOUS', - 'NVOS32_ATTR_PHYSICALITY_DEFAULT', - 'NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS', 'NVOS32_ATTR_ZCULL_ANY', - 'NVOS32_ATTR_ZCULL_NONE', 'NVOS32_ATTR_ZCULL_REQUIRED', - 'NVOS32_ATTR_ZCULL_SHARED', 'NVOS32_ATTR_ZS_PACKING_S8', - 'NVOS32_ATTR_ZS_PACKING_S8Z24', 'NVOS32_ATTR_ZS_PACKING_X8Z24', - 'NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8', - 'NVOS32_ATTR_ZS_PACKING_Z16', 'NVOS32_ATTR_ZS_PACKING_Z24S8', - 'NVOS32_ATTR_ZS_PACKING_Z24X8', 'NVOS32_ATTR_ZS_PACKING_Z32', - 'NVOS32_ATTR_ZS_PACKING_Z32_X24S8', 'NVOS32_ATTR_Z_TYPE_FIXED', - 'NVOS32_ATTR_Z_TYPE_FLOAT', 'NVOS32_BLOCKINFO', - 'NVOS32_BLOCK_TYPE_FREE', 'NVOS32_DELETE_RESOURCES_ALL', - 'NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS', - 'NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR', - 'NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE', - 'NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY', - 'NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY', - 'NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR', - 'NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR', - 'NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS', - 'NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS', - 'NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD', - 'NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA', - 'NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE', - 'NVOS32_DUMP_FLAGS_TYPE_FB', - 'NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU', - 'NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR', - 'NVOS32_FUNCTION_ALLOC_SIZE', 'NVOS32_FUNCTION_ALLOC_SIZE_RANGE', - 'NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT', - 'NVOS32_FUNCTION_DUMP', 'NVOS32_FUNCTION_FREE', - 'NVOS32_FUNCTION_GET_MEM_ALIGNMENT', 'NVOS32_FUNCTION_HW_ALLOC', - 'NVOS32_FUNCTION_HW_FREE', 'NVOS32_FUNCTION_INFO', - 'NVOS32_FUNCTION_REACQUIRE_COMPR', - 'NVOS32_FUNCTION_RELEASE_COMPR', 'NVOS32_HEAP_DUMP_BLOCK', - 'NVOS32_INVALID_BLOCK_FREE_OFFSET', - 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP', - 'NVOS32_MEM_TAG_NONE', 'NVOS32_NUM_MEM_TYPES', - 'NVOS32_PARAMETERS', - 'NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_REALLOC_FLAGS_GROW_ALLOCATION', - 'NVOS32_REALLOC_FLAGS_REALLOC_DOWN', - 'NVOS32_REALLOC_FLAGS_REALLOC_UP', - 'NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION', - 'NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED', - 'NVOS32_TYPE_CURSOR', 'NVOS32_TYPE_DEPTH', 'NVOS32_TYPE_DMA', - 'NVOS32_TYPE_FONT', 'NVOS32_TYPE_IMAGE', 'NVOS32_TYPE_INSTANCE', - 'NVOS32_TYPE_NOTIFIER', 'NVOS32_TYPE_OWNER_RM', 'NVOS32_TYPE_PMA', - 'NVOS32_TYPE_PRIMARY', 'NVOS32_TYPE_RESERVED', - 'NVOS32_TYPE_SHADER_PROGRAM', 'NVOS32_TYPE_STENCIL', - 'NVOS32_TYPE_TEXTURE', 'NVOS32_TYPE_UNUSED', 'NVOS32_TYPE_VIDEO', - 'NVOS32_TYPE_ZCULL', 'NVOS33_FLAGS_ACCESS_READ_ONLY', - 'NVOS33_FLAGS_ACCESS_READ_WRITE', - 'NVOS33_FLAGS_ACCESS_WRITE_ONLY', - 'NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO', - 'NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES', - 'NVOS33_FLAGS_CACHING_TYPE_CACHED', - 'NVOS33_FLAGS_CACHING_TYPE_DEFAULT', - 'NVOS33_FLAGS_CACHING_TYPE_UNCACHED', - 'NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK', - 'NVOS33_FLAGS_CACHING_TYPE_WRITEBACK', - 'NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED', - 'NVOS33_FLAGS_FIFO_MAPPING_DEFAULT', - 'NVOS33_FLAGS_FIFO_MAPPING_ENABLE', - 'NVOS33_FLAGS_MAPPING_DEFAULT', 'NVOS33_FLAGS_MAPPING_DIRECT', - 'NVOS33_FLAGS_MAPPING_REFLECTED', - 'NVOS33_FLAGS_MAP_FIXED_DISABLE', 'NVOS33_FLAGS_MAP_FIXED_ENABLE', - 'NVOS33_FLAGS_MEM_SPACE_CLIENT', 'NVOS33_FLAGS_MEM_SPACE_USER', - 'NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE', - 'NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE', - 'NVOS33_FLAGS_PERSISTENT_DISABLE', - 'NVOS33_FLAGS_PERSISTENT_ENABLE', - 'NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE', - 'NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE', - 'NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE', - 'NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE', 'NVOS33_PARAMETERS', - 'NVOS34_PARAMETERS', 'NVOS38_ACCESS_TYPE_READ_BINARY', - 'NVOS38_ACCESS_TYPE_READ_DWORD', - 'NVOS38_ACCESS_TYPE_WRITE_BINARY', - 'NVOS38_ACCESS_TYPE_WRITE_DWORD', - 'NVOS38_MAX_REGISTRY_BINARY_LENGTH', - 'NVOS38_MAX_REGISTRY_STRING_LENGTH', 'NVOS38_PARAMETERS', - 'NVOS39_PARAMETERS', 'NVOS41_PARAMETERS', - 'NVOS46_FLAGS_32BIT_POINTER_DISABLE', - 'NVOS46_FLAGS_32BIT_POINTER_ENABLE', - 'NVOS46_FLAGS_ACCESS_READ_ONLY', 'NVOS46_FLAGS_ACCESS_READ_WRITE', - 'NVOS46_FLAGS_ACCESS_WRITE_ONLY', - 'NVOS46_FLAGS_CACHE_SNOOP_DISABLE', - 'NVOS46_FLAGS_CACHE_SNOOP_ENABLE', - 'NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE', - 'NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE', - 'NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE', - 'NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE', - 'NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE', - 'NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE', - 'NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN', - 'NVOS46_FLAGS_DMA_OFFSET_GROWS_UP', - 'NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE', - 'NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE', - 'NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE', - 'NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE', - 'NVOS46_FLAGS_KERNEL_MAPPING_ENABLE', - 'NVOS46_FLAGS_KERNEL_MAPPING_NONE', 'NVOS46_FLAGS_P2P_ENABLE_NO', - 'NVOS46_FLAGS_P2P_ENABLE_NONE', 'NVOS46_FLAGS_P2P_ENABLE_NOSLI', - 'NVOS46_FLAGS_P2P_ENABLE_SLI', 'NVOS46_FLAGS_P2P_ENABLE_YES', - 'NVOS46_FLAGS_PAGE_KIND_PHYSICAL', - 'NVOS46_FLAGS_PAGE_KIND_VIRTUAL', 'NVOS46_FLAGS_PAGE_SIZE_4KB', - 'NVOS46_FLAGS_PAGE_SIZE_512M', 'NVOS46_FLAGS_PAGE_SIZE_BIG', - 'NVOS46_FLAGS_PAGE_SIZE_BOTH', 'NVOS46_FLAGS_PAGE_SIZE_DEFAULT', - 'NVOS46_FLAGS_PAGE_SIZE_HUGE', - 'NVOS46_FLAGS_SHADER_ACCESS_DEFAULT', - 'NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY', - 'NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE', - 'NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY', - 'NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT', - 'NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT', - 'NVOS46_FLAGS_TLB_LOCK_DISABLE', 'NVOS46_FLAGS_TLB_LOCK_ENABLE', - 'NVOS46_PARAMETERS', 'NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE', - 'NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE', 'NVOS47_PARAMETERS', - 'NVOS49_PARAMETERS', 'NVOS54_FLAGS_FINN_SERIALIZED', - 'NVOS54_FLAGS_IRQL_RAISED', 'NVOS54_FLAGS_LOCK_BYPASS', - 'NVOS54_FLAGS_NONE', 'NVOS54_PARAMETERS', 'NVOS55_PARAMETERS', - 'NVOS56_PARAMETERS', 'NVOS57_PARAMETERS', 'NVOS61_PARAMETERS', - 'NVOS62_PARAMETERS', 'NVOS63_PARAMETERS', - 'NVOS64_FLAGS_FINN_SERIALIZED', 'NVOS64_FLAGS_NONE', - 'NVOS64_PARAMETERS', 'NVOS65_PARAMETERS', - 'NVOS65_PARAMETERS_VERSION_MAGIC', - 'NVOS_I2C_ACCESS_MAX_BUFFER_SIZE', 'NVOS_I2C_ACCESS_PARAMS', - 'NVOS_INCLUDED', 'NVOS_MAX_SUBDEVICES', - 'NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX', - 'NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS', - 'NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE', - 'NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION', - 'NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO', - 'NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES', - 'NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE', 'NVPOWERSTATE_PARAMETERS', - 'NVSIM01_BUS_XACT', 'NV_BSP_ALLOCATION_PARAMETERS', 'NV_CE_UTILS', - 'NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS', - 'NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE', - 'NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN', - 'NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1', - 'NV_CHANNEL_ALLOC_PARAMS', 'NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID', - 'NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS', - 'NV_CONFIDENTIAL_COMPUTE', - 'NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE', - 'NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE', - 'NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_NULL', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE', - 'NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS', - 'NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE', - 'NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE', - 'NV_CONF_COMPUTE_NONCE_SIZE', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX', - 'NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE', - 'NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED', - 'NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED', - 'NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD', - 'NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM', - 'NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE', - 'NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED', - 'NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED', - 'NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED', - 'NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM', - 'NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC', - 'NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE', - 'NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE', - 'NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE', - 'NV_CONTEXT_DMA_ALLOCATION_PARAMS', 'NV_COUNTER_COLLECTION_UNIT', - 'NV_CTRL_VASPACE_PAGE_LEVEL', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED', - 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC', - 'NV_CTXSHARE_ALLOCATION_PARAMETERS', - 'NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL', - 'NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS', - 'NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE', - 'NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE', - 'NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY', - 'NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE', - 'NV_DEVICE_ALLOCATION_FLAGS_NONE', - 'NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT', - 'NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS', - 'NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT', - 'NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE', - 'NV_DEVICE_ALLOCATION_SZNAME_MAXLEN', - 'NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES', - 'NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES', - 'NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE', - 'NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT', - 'NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE', - 'NV_DMABUF_EXPORT_MAX_HANDLES', 'NV_ESCAPE_H_INCLUDED', - 'NV_ESC_ALLOC_OS_EVENT', 'NV_ESC_ATTACH_GPUS_TO_FD', - 'NV_ESC_CARD_INFO', 'NV_ESC_CHECK_VERSION_STR', - 'NV_ESC_EXPORT_TO_DMABUF_FD', 'NV_ESC_FREE_OS_EVENT', - 'NV_ESC_IOCTL_XFER_CMD', 'NV_ESC_NUMA_INFO', - 'NV_ESC_QUERY_DEVICE_INTR', 'NV_ESC_REGISTER_FD', - 'NV_ESC_RM_ACCESS_REGISTRY', 'NV_ESC_RM_ADD_VBLANK_CALLBACK', - 'NV_ESC_RM_ALLOC', 'NV_ESC_RM_ALLOC_CONTEXT_DMA2', - 'NV_ESC_RM_ALLOC_MEMORY', 'NV_ESC_RM_ALLOC_OBJECT', - 'NV_ESC_RM_BIND_CONTEXT_DMA', 'NV_ESC_RM_CONFIG_GET', - 'NV_ESC_RM_CONFIG_GET_EX', 'NV_ESC_RM_CONFIG_SET', - 'NV_ESC_RM_CONFIG_SET_EX', 'NV_ESC_RM_CONTROL', - 'NV_ESC_RM_DUP_OBJECT', 'NV_ESC_RM_EXPORT_OBJECT_TO_FD', - 'NV_ESC_RM_FREE', 'NV_ESC_RM_GET_EVENT_DATA', - 'NV_ESC_RM_I2C_ACCESS', 'NV_ESC_RM_IDLE_CHANNELS', - 'NV_ESC_RM_IMPORT_OBJECT_FROM_FD', - 'NV_ESC_RM_LOCKLESS_DIAGNOSTIC', 'NV_ESC_RM_MAP_MEMORY', - 'NV_ESC_RM_MAP_MEMORY_DMA', 'NV_ESC_RM_SHARE', - 'NV_ESC_RM_UNMAP_MEMORY', 'NV_ESC_RM_UNMAP_MEMORY_DMA', - 'NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO', - 'NV_ESC_RM_VID_HEAP_CONTROL', 'NV_ESC_SET_NUMA_STATUS', - 'NV_ESC_STATUS_CODE', 'NV_ESC_SYS_PARAMS', - 'NV_ESC_WAIT_OPEN_COMPLETE', 'NV_EVENT_BUFFER', - 'NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS', - 'NV_GI_UUID_LEN', 'NV_GRID_LICENSED_PRODUCT_COMPUTE', - 'NV_GRID_LICENSED_PRODUCT_GAMING', - 'NV_GRID_LICENSED_PRODUCT_VAPPS', 'NV_GRID_LICENSED_PRODUCT_VPC', - 'NV_GRID_LICENSED_PRODUCT_VWS', - 'NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION', - 'NV_GRID_LICENSE_FEATURE_GAMING_EDITION', - 'NV_GRID_LICENSE_FEATURE_VAPPS_EDITION', - 'NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION', - 'NV_GRID_LICENSE_FEATURE_VPC_EDITION', - 'NV_GRID_LICENSE_INFO_MAX_LENGTH', 'NV_GR_ALLOCATION_PARAMETERS', - 'NV_HOPPER_USERMODE_A_PARAMS', 'NV_IMEX_SESSION', 'NV_IOCTL_BASE', - 'NV_IOCTL_FCT_BASE', 'NV_IOCTL_H', 'NV_IOCTL_MAGIC', - 'NV_IOCTL_NUMA_H', 'NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES', - 'NV_IOCTL_NUMA_STATUS_DISABLED', 'NV_IOCTL_NUMA_STATUS_OFFLINE', - 'NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED', - 'NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS', - 'NV_IOCTL_NUMA_STATUS_ONLINE', - 'NV_IOCTL_NUMA_STATUS_ONLINE_FAILED', - 'NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS', 'NV_IOCTL_NUMBERS_H', - 'NV_MEMORY_ALLOCATION_PARAMS', 'NV_MEMORY_DESC_PARAMS', - 'NV_MEMORY_EXPORT', 'NV_MEMORY_EXTENDED_USER', 'NV_MEMORY_FABRIC', - 'NV_MEMORY_FABRIC_IMPORTED_REF', 'NV_MEMORY_FABRIC_IMPORT_V2', - 'NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS', 'NV_MEMORY_MAPPER', - 'NV_MEMORY_MULTICAST_FABRIC', 'NV_ME_ALLOCATION_PARAMETERS', - 'NV_MSENC_ALLOCATION_PARAMETERS', - 'NV_NVJPG_ALLOCATION_PARAMETERS', 'NV_OFA_ALLOCATION_PARAMETERS', - 'NV_OS_DESC_MEMORY_ALLOCATION_PARAMS', 'NV_PFAULT', - 'NV_PFAULT_ACCESS_TYPE_ATOMIC', - 'NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC', - 'NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH', - 'NV_PFAULT_ACCESS_TYPE_PHYS_READ', - 'NV_PFAULT_ACCESS_TYPE_PHYS_WRITE', - 'NV_PFAULT_ACCESS_TYPE_PREFETCH', 'NV_PFAULT_ACCESS_TYPE_READ', - 'NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC', - 'NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG', - 'NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK', - 'NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH', - 'NV_PFAULT_ACCESS_TYPE_VIRT_READ', - 'NV_PFAULT_ACCESS_TYPE_VIRT_WRITE', 'NV_PFAULT_ACCESS_TYPE_WRITE', - 'NV_PFAULT_CLIENT_GPC_GCC', 'NV_PFAULT_CLIENT_GPC_GPCCS', - 'NV_PFAULT_CLIENT_GPC_GPM', 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_0', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_1', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_10', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_11', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_12', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_13', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_14', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_15', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_2', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_3', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_4', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_5', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_6', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_7', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_8', - 'NV_PFAULT_CLIENT_GPC_LTP_UTLB_9', 'NV_PFAULT_CLIENT_GPC_PE_0', - 'NV_PFAULT_CLIENT_GPC_PE_1', 'NV_PFAULT_CLIENT_GPC_PE_10', - 'NV_PFAULT_CLIENT_GPC_PE_11', 'NV_PFAULT_CLIENT_GPC_PE_12', - 'NV_PFAULT_CLIENT_GPC_PE_13', 'NV_PFAULT_CLIENT_GPC_PE_14', - 'NV_PFAULT_CLIENT_GPC_PE_15', 'NV_PFAULT_CLIENT_GPC_PE_16', - 'NV_PFAULT_CLIENT_GPC_PE_17', 'NV_PFAULT_CLIENT_GPC_PE_18', - 'NV_PFAULT_CLIENT_GPC_PE_19', 'NV_PFAULT_CLIENT_GPC_PE_2', - 'NV_PFAULT_CLIENT_GPC_PE_3', 'NV_PFAULT_CLIENT_GPC_PE_4', - 'NV_PFAULT_CLIENT_GPC_PE_5', 'NV_PFAULT_CLIENT_GPC_PE_6', - 'NV_PFAULT_CLIENT_GPC_PE_7', 'NV_PFAULT_CLIENT_GPC_PE_8', - 'NV_PFAULT_CLIENT_GPC_PE_9', 'NV_PFAULT_CLIENT_GPC_PROP_0', - 'NV_PFAULT_CLIENT_GPC_PROP_1', 'NV_PFAULT_CLIENT_GPC_PROP_2', - 'NV_PFAULT_CLIENT_GPC_PROP_3', 'NV_PFAULT_CLIENT_GPC_RAST', - 'NV_PFAULT_CLIENT_GPC_RGG_UTLB', 'NV_PFAULT_CLIENT_GPC_ROP_0', - 'NV_PFAULT_CLIENT_GPC_ROP_1', 'NV_PFAULT_CLIENT_GPC_ROP_2', - 'NV_PFAULT_CLIENT_GPC_ROP_3', 'NV_PFAULT_CLIENT_GPC_T1_0', - 'NV_PFAULT_CLIENT_GPC_T1_1', 'NV_PFAULT_CLIENT_GPC_T1_10', - 'NV_PFAULT_CLIENT_GPC_T1_11', 'NV_PFAULT_CLIENT_GPC_T1_12', - 'NV_PFAULT_CLIENT_GPC_T1_13', 'NV_PFAULT_CLIENT_GPC_T1_14', - 'NV_PFAULT_CLIENT_GPC_T1_15', 'NV_PFAULT_CLIENT_GPC_T1_16', - 'NV_PFAULT_CLIENT_GPC_T1_17', 'NV_PFAULT_CLIENT_GPC_T1_18', - 'NV_PFAULT_CLIENT_GPC_T1_19', 'NV_PFAULT_CLIENT_GPC_T1_2', - 'NV_PFAULT_CLIENT_GPC_T1_20', 'NV_PFAULT_CLIENT_GPC_T1_21', - 'NV_PFAULT_CLIENT_GPC_T1_22', 'NV_PFAULT_CLIENT_GPC_T1_23', - 'NV_PFAULT_CLIENT_GPC_T1_24', 'NV_PFAULT_CLIENT_GPC_T1_25', - 'NV_PFAULT_CLIENT_GPC_T1_26', 'NV_PFAULT_CLIENT_GPC_T1_27', - 'NV_PFAULT_CLIENT_GPC_T1_28', 'NV_PFAULT_CLIENT_GPC_T1_29', - 'NV_PFAULT_CLIENT_GPC_T1_3', 'NV_PFAULT_CLIENT_GPC_T1_30', - 'NV_PFAULT_CLIENT_GPC_T1_31', 'NV_PFAULT_CLIENT_GPC_T1_32', - 'NV_PFAULT_CLIENT_GPC_T1_33', 'NV_PFAULT_CLIENT_GPC_T1_34', - 'NV_PFAULT_CLIENT_GPC_T1_35', 'NV_PFAULT_CLIENT_GPC_T1_36', - 'NV_PFAULT_CLIENT_GPC_T1_37', 'NV_PFAULT_CLIENT_GPC_T1_38', - 'NV_PFAULT_CLIENT_GPC_T1_39', 'NV_PFAULT_CLIENT_GPC_T1_4', - 'NV_PFAULT_CLIENT_GPC_T1_5', 'NV_PFAULT_CLIENT_GPC_T1_6', - 'NV_PFAULT_CLIENT_GPC_T1_7', 'NV_PFAULT_CLIENT_GPC_T1_8', - 'NV_PFAULT_CLIENT_GPC_T1_9', 'NV_PFAULT_CLIENT_GPC_TPCCS_0', - 'NV_PFAULT_CLIENT_GPC_TPCCS_1', 'NV_PFAULT_CLIENT_GPC_TPCCS_10', - 'NV_PFAULT_CLIENT_GPC_TPCCS_11', 'NV_PFAULT_CLIENT_GPC_TPCCS_12', - 'NV_PFAULT_CLIENT_GPC_TPCCS_13', 'NV_PFAULT_CLIENT_GPC_TPCCS_14', - 'NV_PFAULT_CLIENT_GPC_TPCCS_15', 'NV_PFAULT_CLIENT_GPC_TPCCS_16', - 'NV_PFAULT_CLIENT_GPC_TPCCS_17', 'NV_PFAULT_CLIENT_GPC_TPCCS_18', - 'NV_PFAULT_CLIENT_GPC_TPCCS_19', 'NV_PFAULT_CLIENT_GPC_TPCCS_2', - 'NV_PFAULT_CLIENT_GPC_TPCCS_3', 'NV_PFAULT_CLIENT_GPC_TPCCS_4', - 'NV_PFAULT_CLIENT_GPC_TPCCS_5', 'NV_PFAULT_CLIENT_GPC_TPCCS_6', - 'NV_PFAULT_CLIENT_GPC_TPCCS_7', 'NV_PFAULT_CLIENT_GPC_TPCCS_8', - 'NV_PFAULT_CLIENT_GPC_TPCCS_9', 'NV_PFAULT_CLIENT_HUB_ACTRS', - 'NV_PFAULT_CLIENT_HUB_AFALCON', 'NV_PFAULT_CLIENT_HUB_CE0', - 'NV_PFAULT_CLIENT_HUB_CE1', 'NV_PFAULT_CLIENT_HUB_CE2', - 'NV_PFAULT_CLIENT_HUB_CE_SHIM', 'NV_PFAULT_CLIENT_HUB_DFALCON', - 'NV_PFAULT_CLIENT_HUB_DISPNISO', 'NV_PFAULT_CLIENT_HUB_DNISO', - 'NV_PFAULT_CLIENT_HUB_DONT_CARE', 'NV_PFAULT_CLIENT_HUB_DWBIF', - 'NV_PFAULT_CLIENT_HUB_ESC', 'NV_PFAULT_CLIENT_HUB_FBFALCON', - 'NV_PFAULT_CLIENT_HUB_FE', 'NV_PFAULT_CLIENT_HUB_FE0', - 'NV_PFAULT_CLIENT_HUB_FE1', 'NV_PFAULT_CLIENT_HUB_FE2', - 'NV_PFAULT_CLIENT_HUB_FE3', 'NV_PFAULT_CLIENT_HUB_FE4', - 'NV_PFAULT_CLIENT_HUB_FE5', 'NV_PFAULT_CLIENT_HUB_FE6', - 'NV_PFAULT_CLIENT_HUB_FE7', 'NV_PFAULT_CLIENT_HUB_FECS', - 'NV_PFAULT_CLIENT_HUB_FECS0', 'NV_PFAULT_CLIENT_HUB_FECS1', - 'NV_PFAULT_CLIENT_HUB_FECS2', 'NV_PFAULT_CLIENT_HUB_FECS3', - 'NV_PFAULT_CLIENT_HUB_FECS4', 'NV_PFAULT_CLIENT_HUB_FECS5', - 'NV_PFAULT_CLIENT_HUB_FECS6', 'NV_PFAULT_CLIENT_HUB_FECS7', - 'NV_PFAULT_CLIENT_HUB_GRCOPY', 'NV_PFAULT_CLIENT_HUB_GSP', - 'NV_PFAULT_CLIENT_HUB_HOST', 'NV_PFAULT_CLIENT_HUB_HOST_CPU', - 'NV_PFAULT_CLIENT_HUB_HOST_CPU_NB', 'NV_PFAULT_CLIENT_HUB_HSCE0', - 'NV_PFAULT_CLIENT_HUB_HSCE1', 'NV_PFAULT_CLIENT_HUB_HSCE10', - 'NV_PFAULT_CLIENT_HUB_HSCE11', 'NV_PFAULT_CLIENT_HUB_HSCE12', - 'NV_PFAULT_CLIENT_HUB_HSCE13', 'NV_PFAULT_CLIENT_HUB_HSCE14', - 'NV_PFAULT_CLIENT_HUB_HSCE15', 'NV_PFAULT_CLIENT_HUB_HSCE2', - 'NV_PFAULT_CLIENT_HUB_HSCE3', 'NV_PFAULT_CLIENT_HUB_HSCE4', - 'NV_PFAULT_CLIENT_HUB_HSCE5', 'NV_PFAULT_CLIENT_HUB_HSCE6', - 'NV_PFAULT_CLIENT_HUB_HSCE7', 'NV_PFAULT_CLIENT_HUB_HSCE8', - 'NV_PFAULT_CLIENT_HUB_HSCE9', 'NV_PFAULT_CLIENT_HUB_HSHUB', - 'NV_PFAULT_CLIENT_HUB_ISO', 'NV_PFAULT_CLIENT_HUB_MMU', - 'NV_PFAULT_CLIENT_HUB_MMU_NB', 'NV_PFAULT_CLIENT_HUB_NISO', - 'NV_PFAULT_CLIENT_HUB_NVDEC', 'NV_PFAULT_CLIENT_HUB_NVDEC0', - 'NV_PFAULT_CLIENT_HUB_NVDEC1', 'NV_PFAULT_CLIENT_HUB_NVDEC2', - 'NV_PFAULT_CLIENT_HUB_NVDEC3', 'NV_PFAULT_CLIENT_HUB_NVDEC4', - 'NV_PFAULT_CLIENT_HUB_NVENC', 'NV_PFAULT_CLIENT_HUB_NVENC0', - 'NV_PFAULT_CLIENT_HUB_NVENC1', 'NV_PFAULT_CLIENT_HUB_NVENC2', - 'NV_PFAULT_CLIENT_HUB_NVJPG0', 'NV_PFAULT_CLIENT_HUB_OFA0', - 'NV_PFAULT_CLIENT_HUB_P2P', 'NV_PFAULT_CLIENT_HUB_PD', - 'NV_PFAULT_CLIENT_HUB_PERF', 'NV_PFAULT_CLIENT_HUB_PERF0', - 'NV_PFAULT_CLIENT_HUB_PMU', 'NV_PFAULT_CLIENT_HUB_PTP_X0', - 'NV_PFAULT_CLIENT_HUB_PTP_X1', 'NV_PFAULT_CLIENT_HUB_PTP_X10', - 'NV_PFAULT_CLIENT_HUB_PTP_X11', 'NV_PFAULT_CLIENT_HUB_PTP_X12', - 'NV_PFAULT_CLIENT_HUB_PTP_X13', 'NV_PFAULT_CLIENT_HUB_PTP_X14', - 'NV_PFAULT_CLIENT_HUB_PTP_X15', 'NV_PFAULT_CLIENT_HUB_PTP_X2', - 'NV_PFAULT_CLIENT_HUB_PTP_X3', 'NV_PFAULT_CLIENT_HUB_PTP_X4', - 'NV_PFAULT_CLIENT_HUB_PTP_X5', 'NV_PFAULT_CLIENT_HUB_PTP_X6', - 'NV_PFAULT_CLIENT_HUB_PTP_X7', 'NV_PFAULT_CLIENT_HUB_PTP_X8', - 'NV_PFAULT_CLIENT_HUB_PTP_X9', 'NV_PFAULT_CLIENT_HUB_RASTERTWOD', - 'NV_PFAULT_CLIENT_HUB_SCC', 'NV_PFAULT_CLIENT_HUB_SCC_NB', - 'NV_PFAULT_CLIENT_HUB_SEC', 'NV_PFAULT_CLIENT_HUB_SKED', - 'NV_PFAULT_CLIENT_HUB_SKED0', 'NV_PFAULT_CLIENT_HUB_SKED1', - 'NV_PFAULT_CLIENT_HUB_SKED2', 'NV_PFAULT_CLIENT_HUB_SKED3', - 'NV_PFAULT_CLIENT_HUB_SKED4', 'NV_PFAULT_CLIENT_HUB_SKED5', - 'NV_PFAULT_CLIENT_HUB_SKED6', 'NV_PFAULT_CLIENT_HUB_SKED7', - 'NV_PFAULT_CLIENT_HUB_SSYNC', 'NV_PFAULT_CLIENT_HUB_VIP', - 'NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0', - 'NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1', 'NV_PFAULT_CLIENT_HUB_XV', - 'NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE', - 'NV_PFAULT_FAULT_TYPE_PDE', 'NV_PFAULT_FAULT_TYPE_PDE_SIZE', - 'NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_POISONED', - 'NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION', 'NV_PFAULT_FAULT_TYPE_PTE', - 'NV_PFAULT_FAULT_TYPE_REGION_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_RO_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK', - 'NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE', - 'NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND', - 'NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION', - 'NV_PFAULT_FAULT_TYPE_WORK_CREATION', - 'NV_PFAULT_FAULT_TYPE_WO_VIOLATION', - 'NV_PFAULT_MMU_CLIENT_TYPE_GPC', 'NV_PFAULT_MMU_CLIENT_TYPE_HUB', - 'NV_PFAULT_MMU_ENG_ID_BAR1', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN0', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN1', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN10', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN11', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN12', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN13', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN14', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN15', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN16', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN17', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN18', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN19', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN2', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN20', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN21', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN22', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN23', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN24', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN25', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN26', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN27', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN28', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN29', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN3', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN30', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN31', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN32', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN33', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN34', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN35', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN36', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN37', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN38', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN39', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN4', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN40', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN41', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN42', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN43', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN44', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN45', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN46', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN47', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN48', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN49', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN5', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN50', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN51', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN52', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN53', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN54', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN55', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN56', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN57', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN58', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN59', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN6', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN60', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN61', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN62', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN63', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN7', - 'NV_PFAULT_MMU_ENG_ID_BAR1_FN8', 'NV_PFAULT_MMU_ENG_ID_BAR1_FN9', - 'NV_PFAULT_MMU_ENG_ID_BAR2', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN0', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN1', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN10', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN11', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN12', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN13', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN14', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN15', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN16', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN17', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN18', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN19', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN2', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN20', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN21', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN22', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN23', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN24', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN25', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN26', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN27', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN28', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN29', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN3', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN30', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN31', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN32', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN33', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN34', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN35', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN36', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN37', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN38', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN39', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN4', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN40', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN41', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN42', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN43', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN44', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN45', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN46', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN47', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN48', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN49', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN5', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN50', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN51', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN52', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN53', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN54', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN55', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN56', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN57', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN58', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN59', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN6', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN60', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN61', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN62', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN63', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN7', - 'NV_PFAULT_MMU_ENG_ID_BAR2_FN8', 'NV_PFAULT_MMU_ENG_ID_BAR2_FN9', - 'NV_PFAULT_MMU_ENG_ID_CE0', 'NV_PFAULT_MMU_ENG_ID_CE1', - 'NV_PFAULT_MMU_ENG_ID_CE2', 'NV_PFAULT_MMU_ENG_ID_CE3', - 'NV_PFAULT_MMU_ENG_ID_CE4', 'NV_PFAULT_MMU_ENG_ID_CE5', - 'NV_PFAULT_MMU_ENG_ID_CE6', 'NV_PFAULT_MMU_ENG_ID_CE7', - 'NV_PFAULT_MMU_ENG_ID_CE8', 'NV_PFAULT_MMU_ENG_ID_CE9', - 'NV_PFAULT_MMU_ENG_ID_DISPLAY', 'NV_PFAULT_MMU_ENG_ID_FLA', - 'NV_PFAULT_MMU_ENG_ID_GRAPHICS', 'NV_PFAULT_MMU_ENG_ID_GRCOPY', - 'NV_PFAULT_MMU_ENG_ID_GSP', 'NV_PFAULT_MMU_ENG_ID_HOST0', - 'NV_PFAULT_MMU_ENG_ID_HOST1', 'NV_PFAULT_MMU_ENG_ID_HOST10', - 'NV_PFAULT_MMU_ENG_ID_HOST11', 'NV_PFAULT_MMU_ENG_ID_HOST12', - 'NV_PFAULT_MMU_ENG_ID_HOST13', 'NV_PFAULT_MMU_ENG_ID_HOST14', - 'NV_PFAULT_MMU_ENG_ID_HOST15', 'NV_PFAULT_MMU_ENG_ID_HOST16', - 'NV_PFAULT_MMU_ENG_ID_HOST17', 'NV_PFAULT_MMU_ENG_ID_HOST18', - 'NV_PFAULT_MMU_ENG_ID_HOST19', 'NV_PFAULT_MMU_ENG_ID_HOST2', - 'NV_PFAULT_MMU_ENG_ID_HOST20', 'NV_PFAULT_MMU_ENG_ID_HOST21', - 'NV_PFAULT_MMU_ENG_ID_HOST22', 'NV_PFAULT_MMU_ENG_ID_HOST23', - 'NV_PFAULT_MMU_ENG_ID_HOST24', 'NV_PFAULT_MMU_ENG_ID_HOST25', - 'NV_PFAULT_MMU_ENG_ID_HOST26', 'NV_PFAULT_MMU_ENG_ID_HOST27', - 'NV_PFAULT_MMU_ENG_ID_HOST28', 'NV_PFAULT_MMU_ENG_ID_HOST29', - 'NV_PFAULT_MMU_ENG_ID_HOST3', 'NV_PFAULT_MMU_ENG_ID_HOST30', - 'NV_PFAULT_MMU_ENG_ID_HOST31', 'NV_PFAULT_MMU_ENG_ID_HOST4', - 'NV_PFAULT_MMU_ENG_ID_HOST5', 'NV_PFAULT_MMU_ENG_ID_HOST6', - 'NV_PFAULT_MMU_ENG_ID_HOST7', 'NV_PFAULT_MMU_ENG_ID_HOST8', - 'NV_PFAULT_MMU_ENG_ID_HOST9', 'NV_PFAULT_MMU_ENG_ID_IFB', - 'NV_PFAULT_MMU_ENG_ID_NVDEC', 'NV_PFAULT_MMU_ENG_ID_NVDEC0', - 'NV_PFAULT_MMU_ENG_ID_NVDEC1', 'NV_PFAULT_MMU_ENG_ID_NVDEC2', - 'NV_PFAULT_MMU_ENG_ID_NVDEC3', 'NV_PFAULT_MMU_ENG_ID_NVDEC4', - 'NV_PFAULT_MMU_ENG_ID_NVENC0', 'NV_PFAULT_MMU_ENG_ID_NVENC1', - 'NV_PFAULT_MMU_ENG_ID_NVENC2', 'NV_PFAULT_MMU_ENG_ID_NVJPG0', - 'NV_PFAULT_MMU_ENG_ID_OFA0', 'NV_PFAULT_MMU_ENG_ID_PERF', - 'NV_PFAULT_MMU_ENG_ID_PHYSICAL', 'NV_PFAULT_MMU_ENG_ID_PTP', - 'NV_PFAULT_MMU_ENG_ID_PWR_PMU', 'NV_PFAULT_MMU_ENG_ID_SEC', - 'NV_PPP_ALLOCATION_PARAMETERS', 'NV_RM_API_VERSION_CMD_QUERY', - 'NV_RM_API_VERSION_CMD_RELAXED', 'NV_RM_API_VERSION_CMD_STRICT', - 'NV_RM_API_VERSION_REPLY_RECOGNIZED', - 'NV_RM_API_VERSION_REPLY_UNRECOGNIZED', - 'NV_RM_API_VERSION_STRING_LENGTH', - 'NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR', - 'NV_SEC2_ALLOCATION_PARAMETERS', 'NV_SEMAPHORE_SURFACE', - 'NV_SUBPROC_NAME_MAX_LENGTH', 'NV_SWRUNLIST_ALLOCATION_PARAMS', - 'NV_SWRUNLIST_QOS_INTR_NONE', - 'NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT', - 'NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT', - 'NV_TIMEOUT_CONTROL_PARAMETERS', - 'NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS', - 'NV_VASPACE_ALLOCATION_FLAGS_NONE', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_FLA', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_HOST', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_MAX', - 'NV_VASPACE_ALLOCATION_INDEX_GPU_NEW', - 'NV_VASPACE_ALLOCATION_PARAMETERS', - 'NV_VASPACE_BIG_PAGE_SIZE_128K', 'NV_VASPACE_BIG_PAGE_SIZE_64K', - 'NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS', - 'NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE', - 'NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE__enumvalues', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', - 'NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', - 'NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO', - 'NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO', - 'NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE', - 'NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE', - 'NV_VP_ALLOCATION_FLAGS_STATIC_UCODE', - 'NV_VP_ALLOCATION_PARAMETERS', 'Nv2080ACPIEvent', - 'Nv2080AudioHdcpRequest', 'Nv2080ClocksChangeNotification', - 'Nv2080DpIrqNotification', 'Nv2080DstateHdaCodecNotification', - 'Nv2080DstateXusbPpcNotification', 'Nv2080EccDbeNotification', - 'Nv2080GC5GpuReadyParams', 'Nv2080HdcpStatusChangeNotification', - 'Nv2080HdmiFrlRequestNotification', 'Nv2080HotplugNotification', - 'Nv2080LpwrDifrPrefetchNotification', - 'Nv2080NvlinkLnkChangeNotification', - 'Nv2080PStateChangeNotification', 'Nv2080PowerEventNotification', - 'Nv2080PrivRegAccessFaultNotification', - 'Nv2080QosIntrNotification', 'Nv2080Typedef', - 'Nv2080VrrSetTimeoutNotification', - 'Nv2080WorkloadModulationChangeNotification', - 'Nv2080XusbPpcConnectStateNotification', 'Nv20Subdevice0', - 'NvUnixEvent', 'Nvc56fControl', 'Nvc86fControl', 'Nvc96fControl', - 'PARTITIONID_INVALID', 'PASCAL_CHANNEL_GPFIFO_A', - 'PASCAL_DMA_COPY_A', 'PB_SIZE_16KB', 'PB_SIZE_32KB', - 'PB_SIZE_4KB', 'PB_SIZE_64KB', 'PB_SIZE_8KB', - 'PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE', - 'PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK', - 'PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS', - 'PNV2080_CTRL_GPU_EVICT_CTX_PARAMS', - 'PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS', - 'PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS', - 'PNV2080_CTRL_GR_CTX_BUFFER_INFO', - 'PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS', - 'PNVPOWERSTATE_PARAMETERS', 'PRM_GSP_SPDM_CMD', - 'PRM_GSP_SPDM_CMD_CC_CTRL', 'PRM_GSP_SPDM_CMD_CC_DEINIT', - 'PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL', 'PRM_GSP_SPDM_CMD_CC_INIT', - 'PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA', - 'PRM_GSP_SPDM_CMD_FIPS_SELFTEST', 'PRM_GSP_SPDM_MSG', - 'RM_GSP_SPDM_CMD', 'RM_GSP_SPDM_CMD_CC_CTRL', - 'RM_GSP_SPDM_CMD_CC_DEINIT', 'RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL', - 'RM_GSP_SPDM_CMD_CC_INIT', 'RM_GSP_SPDM_CMD_CC_INIT_RM_DATA', - 'RM_GSP_SPDM_CMD_FIPS_SELFTEST', 'RM_GSP_SPDM_CMD_ID_CC_CTRL', - 'RM_GSP_SPDM_CMD_ID_CC_DEINIT', - 'RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL', - 'RM_GSP_SPDM_CMD_ID_CC_INIT', - 'RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA', - 'RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST', - 'RM_GSP_SPDM_CMD_ID_INVALID_COMMAND', 'RM_GSP_SPDM_MSG', - 'RM_GSP_SPDM_MSG_ID_CC_CTRL', 'RM_GSP_SPDM_MSG_ID_CC_DEINIT', - 'RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL', - 'RM_GSP_SPDM_MSG_ID_CC_INIT', - 'RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA', - 'RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST', - 'RM_GSP_SPDM_MSG_ID_INVALID_COMMAND', 'RM_USER_SHARED_DATA', - 'RPC_METER_ENTRY', 'RSVD7_SIZE', 'RSVD8_SIZE', - 'RX_LNK_RX_RSP_STATUS_HW_ERR', 'RX_LNK_RX_RSP_STATUS_PRIV_ERR', - 'RX_LNK_RX_RSP_STATUS_UR_ERR', - 'SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE', 'TLC_RX_LNK', - 'TLC_TX_SYS', 'TURING_A', 'TURING_CHANNEL_GPFIFO_A', - 'TURING_COMPUTE_A', 'TURING_DMA_COPY_A', 'TURING_USERMODE_A', - 'TX_SYS_TX_RSP_STATUS_HW_ERR', 'TX_SYS_TX_RSP_STATUS_PRIV_ERR', - 'TX_SYS_TX_RSP_STATUS_UR_ERR', 'UNIFIED_NV_STATUS', - 'UVM_ADD_SESSION', 'UVM_ADD_SESSION_PARAMS', - 'UVM_ALLOC_DEVICE_P2P', 'UVM_ALLOC_DEVICE_P2P_PARAMS', - 'UVM_ALLOC_SEMAPHORE_POOL', 'UVM_ALLOC_SEMAPHORE_POOL_PARAMS', - 'UVM_ALLOW_MIGRATION_RANGE_GROUPS', - 'UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS', 'UVM_CHANNEL_RETAINER', - 'UVM_CLEAN_UP_ZOMBIE_RESOURCES', - 'UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS', - 'UVM_CLEAR_ALL_ACCESS_COUNTERS', - 'UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS', - 'UVM_COUNTERS_OFFSET_BASE', 'UVM_CREATE_EVENT_QUEUE', - 'UVM_CREATE_EVENT_QUEUE_PARAMS', 'UVM_CREATE_EXTERNAL_RANGE', - 'UVM_CREATE_EXTERNAL_RANGE_PARAMS', 'UVM_CREATE_RANGE_GROUP', - 'UVM_CREATE_RANGE_GROUP_PARAMS', 'UVM_DEBUG_ACCESS_MEMORY', - 'UVM_DEBUG_ACCESS_MEMORY_PARAMS', 'UVM_DEINITIALIZE', - 'UVM_DESTROY_RANGE_GROUP', 'UVM_DESTROY_RANGE_GROUP_PARAMS', - 'UVM_DISABLE_PEER_ACCESS', 'UVM_DISABLE_PEER_ACCESS_PARAMS', - 'UVM_DISABLE_READ_DUPLICATION', - 'UVM_DISABLE_READ_DUPLICATION_PARAMS', - 'UVM_DISABLE_SYSTEM_WIDE_ATOMICS', - 'UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS', 'UVM_ENABLE_COUNTERS', - 'UVM_ENABLE_COUNTERS_PARAMS', 'UVM_ENABLE_PEER_ACCESS', - 'UVM_ENABLE_PEER_ACCESS_PARAMS', 'UVM_ENABLE_READ_DUPLICATION', - 'UVM_ENABLE_READ_DUPLICATION_PARAMS', - 'UVM_ENABLE_SYSTEM_WIDE_ATOMICS', - 'UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS', 'UVM_EVENTS_OFFSET_BASE', - 'UVM_EVENT_CTRL', 'UVM_EVENT_CTRL_PARAMS', 'UVM_FREE', - 'UVM_FREE_PARAMS', 'UVM_GET_GPU_UUID_TABLE', - 'UVM_GET_GPU_UUID_TABLE_PARAMS', 'UVM_INITIALIZE', - 'UVM_INITIALIZE_PARAMS', 'UVM_IS_8_SUPPORTED', - 'UVM_IS_8_SUPPORTED_PARAMS', 'UVM_MAP_COUNTER', - 'UVM_MAP_COUNTER_PARAMS', 'UVM_MAP_DYNAMIC_PARALLELISM_REGION', - 'UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS', - 'UVM_MAP_EVENT_QUEUE', 'UVM_MAP_EVENT_QUEUE_PARAMS', - 'UVM_MAP_EXTERNAL_ALLOCATION', - 'UVM_MAP_EXTERNAL_ALLOCATION_PARAMS', 'UVM_MAP_EXTERNAL_SPARSE', - 'UVM_MAP_EXTERNAL_SPARSE_PARAMS', - 'UVM_MAX_COUNTERS_PER_IOCTL_CALL', - 'UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL', - 'UVM_MAX_STREAMS_PER_IOCTL_CALL', 'UVM_MEM_MAP', - 'UVM_MEM_MAP_PARAMS', 'UVM_MIGRATE', 'UVM_MIGRATE_FLAGS_ALL', - 'UVM_MIGRATE_FLAGS_TEST_ALL', 'UVM_MIGRATE_FLAG_ASYNC', - 'UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE', - 'UVM_MIGRATE_FLAG_SKIP_CPU_MAP', 'UVM_MIGRATE_PARAMS', - 'UVM_MIGRATE_RANGE_GROUP', 'UVM_MIGRATE_RANGE_GROUP_PARAMS', - 'UVM_MM_INITIALIZE', 'UVM_MM_INITIALIZE_PARAMS', - 'UVM_PAGEABLE_MEM_ACCESS', 'UVM_PAGEABLE_MEM_ACCESS_ON_GPU', - 'UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS', - 'UVM_PAGEABLE_MEM_ACCESS_PARAMS', 'UVM_POPULATE_PAGEABLE', - 'UVM_POPULATE_PAGEABLE_FLAGS_ALL', - 'UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL', - 'UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED', - 'UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK', - 'UVM_POPULATE_PAGEABLE_PARAMS', - 'UVM_PREVENT_MIGRATION_RANGE_GROUPS', - 'UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS', 'UVM_REGION_COMMIT', - 'UVM_REGION_COMMIT_PARAMS', 'UVM_REGION_DECOMMIT', - 'UVM_REGION_DECOMMIT_PARAMS', 'UVM_REGION_SET_STREAM', - 'UVM_REGION_SET_STREAM_PARAMS', 'UVM_REGISTER_CHANNEL', - 'UVM_REGISTER_CHANNEL_PARAMS', 'UVM_REGISTER_GPU', - 'UVM_REGISTER_GPU_PARAMS', 'UVM_REGISTER_GPU_VASPACE', - 'UVM_REGISTER_GPU_VASPACE_PARAMS', 'UVM_REGISTER_MPS_CLIENT', - 'UVM_REGISTER_MPS_CLIENT_PARAMS', 'UVM_REGISTER_MPS_SERVER', - 'UVM_REGISTER_MPS_SERVER_PARAMS', 'UVM_RELEASE_VA', - 'UVM_RELEASE_VA_PARAMS', 'UVM_REMOVE_EVENT_QUEUE', - 'UVM_REMOVE_EVENT_QUEUE_PARAMS', 'UVM_REMOVE_SESSION', - 'UVM_REMOVE_SESSION_PARAMS', 'UVM_RESERVE_VA', - 'UVM_RESERVE_VA_PARAMS', 'UVM_RUN_TEST', 'UVM_RUN_TEST_PARAMS', - 'UVM_SET_ACCESSED_BY', 'UVM_SET_ACCESSED_BY_PARAMS', - 'UVM_SET_PREFERRED_LOCATION', 'UVM_SET_PREFERRED_LOCATION_PARAMS', - 'UVM_SET_RANGE_GROUP', 'UVM_SET_RANGE_GROUP_PARAMS', - 'UVM_SET_STREAM_RUNNING', 'UVM_SET_STREAM_RUNNING_PARAMS', - 'UVM_SET_STREAM_STOPPED', 'UVM_SET_STREAM_STOPPED_PARAMS', - 'UVM_TOOLS_DISABLE_COUNTERS', 'UVM_TOOLS_DISABLE_COUNTERS_PARAMS', - 'UVM_TOOLS_ENABLE_COUNTERS', 'UVM_TOOLS_ENABLE_COUNTERS_PARAMS', - 'UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS', - 'UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS', - 'UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS', - 'UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS', - 'UVM_TOOLS_FLUSH_EVENTS', 'UVM_TOOLS_FLUSH_EVENTS_PARAMS', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2', - 'UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS', - 'UVM_TOOLS_INIT_EVENT_TRACKER', - 'UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS', - 'UVM_TOOLS_INIT_EVENT_TRACKER_V2', - 'UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS', - 'UVM_TOOLS_READ_PROCESS_MEMORY', - 'UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS', - 'UVM_TOOLS_SET_NOTIFICATION_THRESHOLD', - 'UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS', - 'UVM_TOOLS_WRITE_PROCESS_MEMORY', - 'UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS', 'UVM_UNMAP_EXTERNAL', - 'UVM_UNMAP_EXTERNAL_PARAMS', 'UVM_UNREGISTER_CHANNEL', - 'UVM_UNREGISTER_CHANNEL_PARAMS', 'UVM_UNREGISTER_GPU', - 'UVM_UNREGISTER_GPU_PARAMS', 'UVM_UNREGISTER_GPU_VASPACE', - 'UVM_UNREGISTER_GPU_VASPACE_PARAMS', 'UVM_UNSET_ACCESSED_BY', - 'UVM_UNSET_ACCESSED_BY_PARAMS', 'UVM_UNSET_PREFERRED_LOCATION', - 'UVM_UNSET_PREFERRED_LOCATION_PARAMS', 'UVM_VALIDATE_VA_RANGE', - 'UVM_VALIDATE_VA_RANGE_PARAMS', 'VOLTA_CHANNEL_GPFIFO_A', - 'VOLTA_USERMODE_A', 'VPR_REQUEST_PARAMS', 'VPR_STATUS_PARAMS', - '_NV_UNIX_NVOS_PARAMS_WRAPPERS_H_', '_UVM_IOCTL_H', - '_UVM_LINUX_IOCTL_H', '__CLC6C0QMD_H__', '__CLCEC0QMD_H__', - '__ga100_dev_fault_h__', '__gb100_clc96f_h__', - '__gb100_clcdc0_h__', '__gh100_clc86f_h__', - '_cl2080_notification_h_', '_cl_ampere_compute_a_h_', - '_clc56f_h_', '_clc6b5_h_', '_clc761_h_', '_clc9b5_h_', - 'blackwell_dma_copy_aControlPio', 'c__EA_ChannelPBSize', - 'c__EA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE', - 'nv_ioctl_alloc_os_event_t', 'nv_ioctl_card_info_t', - 'nv_ioctl_export_to_dma_buf_fd_t', 'nv_ioctl_free_os_event_t', - 'nv_ioctl_numa_info_t', 'nv_ioctl_nvos02_parameters_with_fd', - 'nv_ioctl_nvos33_parameters_with_fd', - 'nv_ioctl_query_device_intr', 'nv_ioctl_register_fd_t', - 'nv_ioctl_rm_api_version_t', 'nv_ioctl_set_numa_status_t', - 'nv_ioctl_status_code_t', 'nv_ioctl_sys_params_t', - 'nv_ioctl_wait_open_complete_t', 'nv_ioctl_xfer_t', - 'nv_offline_addresses_t', 'nv_pci_info_t', - 'struct_ACR_FALCON_LS_STATUS', 'struct_ACR_REGION_HANDLE', - 'struct_ACR_REGION_ID_PROP', 'struct_ACR_REQUEST_PARAMS', - 'struct_ACR_STATUS_PARAMS', 'struct_CC_AES_CRYPTOBUNDLE', - 'struct_CC_HMAC_CRYPTOBUNDLE', 'struct_CC_KMB', - 'struct_DRAM_CLK_INSTANCE', 'struct_MMU_FMT_LEVEL', - 'struct_NV0000_ALLOC_PARAMETERS', - 'struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS', - 'struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS', - 'struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS', - 'struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS', - 'struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS', - 'struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS', - 'struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS', - 'struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS', - 'struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS', - 'struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY', - 'struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS', - 'struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT', - 'struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS', - 'struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS', - 'struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS', - 'struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS', - 'struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS', - 'struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY', - 'struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS', - 'struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS', - 'struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS', - 'struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS', - 'struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS', - 'struct_NV0000_CTRL_GPU_ACTIVE_DEVICE', - 'struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS', - 'struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS', - 'struct_NV0000_CTRL_GPU_DISCOVER_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS', - 'struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS', - 'struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configEx', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_configSet', - 'struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_0_reservedProperty', - 'struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS', - 'struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS', - 'struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS', - 'struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS', - 'struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS', - 'struct_NV0000_CTRL_GPU_VIDEO_LINKS', - 'struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS', - 'struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS', - 'struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS', - 'struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS', - 'struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_0_rmObject', - 'struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS', - 'struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS', - 'struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_0', - 'struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE', - 'struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_HWBC_INFO', - 'struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_0', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS', - 'struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS', - 'struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS', - 'struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS', - 'struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS', - 'struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS', - 'struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS', - 'struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS', - 'struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS', - 'struct_NV0080_ALLOC_PARAMETERS', - 'struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS', - 'struct_NV0080_CTRL_BIF_RESET_PARAMS', - 'struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS', - 'struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2', - 'struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS', - 'struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS', - 'struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS', - 'struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT', - 'struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS', - 'struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS', - 'struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS', - 'struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo', - 'struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource', - 'struct_NV0080_CTRL_DMA_FLUSH_PARAMS', - 'struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS', - 'struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS', - 'struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK', - 'struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK', - 'struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS', - 'struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS', - 'struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS', - 'struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS', - 'struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS', - 'struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS', - 'struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS', - 'struct_NV0080_CTRL_FB_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS', - 'struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS', - 'struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS', - 'struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS', - 'struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM', - 'struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM', - 'struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS', - 'struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS', - 'struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS', - 'struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM', - 'struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS', - 'struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS', - 'struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS', - 'struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS', - 'struct_NV0080_CTRL_GR_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_GR_GET_INFO_PARAMS', - 'struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS', - 'struct_NV0080_CTRL_GR_ROUTE_INFO', - 'struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS', - 'struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS', - 'struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS', - 'struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS', - 'struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS', - 'struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS', - 'struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS', - 'struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'struct_NV2080CtrlNocatJournalDataTdrReason', - 'struct_NV2080CtrlNocatJournalInsertRecord', - 'struct_NV2080CtrlNocatJournalRclog', - 'struct_NV2080CtrlNocatJournalSetTag', - 'struct_NV2080_ALLOC_PARAMETERS', - 'struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS', - 'struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_BIOS_NBSI_REG_STRING', - 'struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_BFD_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR', - 'struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS', - 'struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO', - 'struct_NV2080_CTRL_BUS_PCI_BAR_INFO', - 'struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS', - 'struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS', - 'struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS', - 'struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS', - 'struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS', - 'struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS', - 'struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS', - 'struct_NV2080_CTRL_CE_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS', - 'struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS', - 'struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS', - 'struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS', - 'struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS', - 'struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS', - 'struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS', - 'struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS', - 'struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS', - 'struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS', - 'struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS', - 'struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS', - 'struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO', - 'struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_CLIENT_INFO', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO', - 'struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_STATS_ENTRY', - 'struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS', - 'struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO', - 'struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS', - 'struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS', - 'struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS', - 'struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS', - 'struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS', - 'struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS', - 'struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS', - 'struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS', - 'struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS', - 'struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS', - 'struct_NV2080_CTRL_CMD_RC_INFO_PARAMS', - 'struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS', - 'struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS', - 'struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS', - 'struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS', - 'struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS', - 'struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS', - 'struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO', - 'struct_NV2080_CTRL_DMA_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS', - 'struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO', - 'struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS', - 'struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS', - 'struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS', - 'struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS', - 'struct_NV2080_CTRL_EXEC_PARTITION_SPAN', - 'struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO', - 'struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_FS_INFO_QUERY', - 'struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS', - 'struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS', - 'struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS', - 'struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS', - 'struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS', - 'struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS', - 'struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS', - 'struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS', - 'struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS', - 'struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS', - 'struct_NV2080_CTRL_FB_GET_STATUS_PARAMS', - 'struct_NV2080_CTRL_FB_IS_KIND_PARAMS', - 'struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO', - 'struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS', - 'struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS', - 'struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS', - 'struct_NV2080_CTRL_FB_REMAP_ENTRY', - 'struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS', - 'struct_NV2080_CTRL_FB_SET_RRD_PARAMS', - 'struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS', - 'struct_NV2080_CTRL_FIFO_BIND_CHANNEL', - 'struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS', - 'struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO', - 'struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS', - 'struct_NV2080_CTRL_FIFO_DEVICE_ENTRY', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS', - 'struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS', - 'struct_NV2080_CTRL_FIFO_MEM_INFO', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS', - 'struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_0', - 'struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS', - 'struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS', - 'struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS', - 'struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS', - 'struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS', - 'struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS', - 'struct_NV2080_CTRL_FLA_RANGE_PARAMS', - 'struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS', - 'struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS', - 'struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS', - 'struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER', - 'struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS', - 'struct_NV2080_CTRL_GC6_ENTRY_PARAMS', - 'struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params', - 'struct_NV2080_CTRL_GC6_EXIT_PARAMS', - 'struct_NV2080_CTRL_GC6_EXIT_PARAMS_params', - 'struct_NV2080_CTRL_GC6_FLAVOR_INFO', - 'struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS', - 'struct_NV2080_CTRL_GPUMON_SAMPLE', - 'struct_NV2080_CTRL_GPUMON_SAMPLES', - 'struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG', - 'struct_NV2080_CTRL_GPU_COMPUTE_PROFILE', - 'struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS', - 'struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO', - 'struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO', - 'struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS', - 'struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS', - 'struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS', - 'struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS', - 'struct_NV2080_CTRL_GPU_FAULT_PACKET', - 'struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_GFID_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_ID_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PARTITION_INFO', - 'struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_SDM_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS', - 'struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS', - 'struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS', - 'struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS', - 'struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS', - 'struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO', - 'struct_NV2080_CTRL_GPU_PARTITION_SPAN', - 'struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS', - 'struct_NV2080_CTRL_GPU_PID_INFO', - 'struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA', - 'struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY', - 'struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS', - 'struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_REG_OP', - 'struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS', - 'struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_PARTITION_INFO', - 'struct_NV2080_CTRL_GPU_SET_POWER_PARAMS', - 'struct_NV2080_CTRL_GPU_SET_SDM_PARAMS', - 'struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS', - 'struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS', - 'struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS', - 'struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_CTX_BUFFER_INFO', - 'struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS', - 'struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS', - 'struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_0', - 'struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS', - 'struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS', - 'struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_0', - 'struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS', - 'struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS', - 'struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS', - 'struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS', - 'struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS', - 'struct_NV2080_CTRL_GR_VAT_ALARM_DATA', - 'struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC', - 'struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC', - 'struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS', - 'struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS', - 'struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS', - 'struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT', - 'struct_NV2080_CTRL_I2C_ACCESS_PARAMS', - 'struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS', - 'struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS', - 'struct_NV2080_CTRL_I2C_RW_REG_PARAMS', - 'struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BSP_CAPS', - 'struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO', - 'struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DEVICE_INFO', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_EDID_DATA', - 'struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO', - 'struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO', - 'struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GR_INFO', - 'struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY', - 'struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO', - 'struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO', - 'struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE', - 'struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO', - 'struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_MSENC_CAPS', - 'struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_NV_RANGE', - 'struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X', - 'struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X', - 'struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X', - 'struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI', - 'struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO', - 'struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_0', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER', - 'struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO', - 'struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS', - 'struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS', - 'struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS', - 'struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS', - 'struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY', - 'struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS', - 'struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS', - 'struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS', - 'struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS', - 'struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS', - 'struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY', - 'struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS', - 'struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS', - 'struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS', - 'struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS', - 'struct_NV2080_CTRL_NVENC_SW_SESSION_INFO', - 'struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO', - 'struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS', - 'struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO', - 'struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES', - 'struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS', - 'struct_NV2080_CTRL_NVLINK_DEVICE_INFO', - 'struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS', - 'struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS', - 'struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT', - 'struct_NV2080_CTRL_NVLINK_ERR_INFO', - 'struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES', - 'struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG', - 'struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO', - 'struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS', - 'struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG', - 'struct_NV2080_CTRL_NVLINK_LANE_ERROR', - 'struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR', - 'struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO', - 'struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE', - 'struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO', - 'struct_NV2080_CTRL_NVLINK_PORT_EVENT', - 'struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS', - 'struct_NV2080_CTRL_NVLINK_PRM_DATA', - 'struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS', - 'struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES', - 'struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS', - 'struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD', - 'struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS', - 'struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS', - 'struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS', - 'struct_NV2080_CTRL_PERF_BOOST_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_CLK_INFO', - 'struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS', - 'struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS', - 'struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE', - 'struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE', - 'struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS', - 'struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS', - 'struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS', - 'struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST', - 'struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS', - 'struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS', - 'struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm', - 'struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS', - 'struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS', - 'struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS', - 'struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS', - 'struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS', - 'struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS', - 'struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS', - 'struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS', - 'struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO', - 'struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS', - 'struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS', - 'struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS', - 'struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS', - 'struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS', - 'struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS', - 'struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE', - 'struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS', - 'struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS', - 'struct_NV2080_GUEST_VM_INFO', 'struct_NV2080_HOST_VGPU_DEVICE', - 'struct_NV2080_INTR_CATEGORY_SUBTREE_MAP', - 'struct_NV2080_NOCAT_JOURNAL_ENTRY', - 'struct_NV2080_NOCAT_JOURNAL_GPU_STATE', - 'struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG', - 'struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS', - 'struct_NV2080_NOCAT_JOURNAL_RECORD', - 'struct_NV2080_RAFTS_FLOORSWEEP_INFO', - 'struct_NV2080_VF_MSIX_CAPS', 'struct_NV2080_VGPU_FB_USAGE', - 'struct_NV2080_VGPU_GUEST', - 'struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS', - 'struct_NV83DE_ALLOC_PARAMETERS', - 'struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_OP', - 'struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS', - 'struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP', - 'struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY', - 'struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS', - 'struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS', - 'struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS', - 'struct_NV83DE_MMU_FAULT_INFO', - 'struct_NV83DE_SM_ERROR_STATE_REGISTERS', - 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0', - 'struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS', - 'struct_NVA06C_CTRL_GET_INFO_PARAMS', - 'struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS', - 'struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS', - 'struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS', - 'struct_NVA06C_CTRL_PREEMPT_PARAMS', - 'struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD', - 'struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS', - 'struct_NVA06C_CTRL_TIMESLICE_PARAMS', - 'struct_NVA06F_CTRL_BIND_PARAMS', - 'struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS', - 'struct_NVA081_CTRL_VGPU_INFO', - 'struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS', - 'struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS', - 'struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS', - 'struct_NVXXXX_CTRL_XXX_INFO', 'struct_NV_CHANNEL_ALLOC_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS', - 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS', - 'struct_NV_CTRL_VASPACE_PAGE_LEVEL', - 'struct_NV_MEMORY_DESC_PARAMS', 'struct_Nv2080ACPIEvent', - 'struct_Nv2080AudioHdcpRequestRec', - 'struct_Nv2080ClocksChangeNotificationRec', - 'struct_Nv2080ClocksChangeNotificationRec_timeStamp', - 'struct_Nv2080DpIrqNotificationRec', - 'struct_Nv2080DstateHdaCodecNotificationRec', - 'struct_Nv2080DstateXusbPpcNotificationRec', - 'struct_Nv2080GC5GpuReadyParams', - 'struct_Nv2080HdcpStatusChangeNotificationRec', - 'struct_Nv2080HdmiFrlRequestNotificationRec', - 'struct_Nv2080PStateChangeNotificationRec', - 'struct_Nv2080PStateChangeNotificationRec_timeStamp', - 'struct_Nv2080WorkloadModulationChangeNotificationRec', - 'struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp', - 'struct_Nv2080XusbPpcConnectStateNotificationRec', - 'struct_Nvc56fControl_struct', 'struct_Nvc86fControl_struct', - 'struct_Nvc96fControl_struct', 'struct_RM_GSP_SPDM_CMD_CC_CTRL', - 'struct_RM_GSP_SPDM_CMD_CC_DEINIT', - 'struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL', - 'struct_RM_GSP_SPDM_CMD_CC_INIT', - 'struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA', - 'struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST', 'struct_RM_GSP_SPDM_MSG', - 'struct_RPC_METER_ENTRY', 'struct_RS_ACCESS_MASK', - 'struct_RS_SHARE_POLICY', 'struct_TEGRA_IMP_IMPORT_DATA', - 'struct_VPR_REQUEST_PARAMS', 'struct_VPR_STATUS_PARAMS', - 'struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC', - 'struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE', - 'struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS', - 'struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC', - 'struct__cl2080_tag0', 'struct__clc9b5_tag0', - 'struct_c__SA_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS', - 'struct_c__SA_NVOS00_PARAMETERS', - 'struct_c__SA_NVOS02_PARAMETERS', - 'struct_c__SA_NVOS05_PARAMETERS', - 'struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK', - 'struct_c__SA_NVOS10_EVENT_KERNEL_CALLBACK_EX', - 'struct_c__SA_NVOS21_PARAMETERS', - 'struct_c__SA_NVOS2C_PARAMETERS', - 'struct_c__SA_NVOS30_PARAMETERS', 'struct_c__SA_NVOS32_BLOCKINFO', - 'struct_c__SA_NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS', - 'struct_c__SA_NVOS32_HEAP_DUMP_BLOCK', - 'struct_c__SA_NVOS32_PARAMETERS', - 'struct_c__SA_NVOS32_PARAMETERS_0_9_comprInfo', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocHintAlignment', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocOsDesc', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocSize', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocSizeRange', - 'struct_c__SA_NVOS32_PARAMETERS_0_AllocTiledPitchHeight', - 'struct_c__SA_NVOS32_PARAMETERS_0_Dump', - 'struct_c__SA_NVOS32_PARAMETERS_0_Free', - 'struct_c__SA_NVOS32_PARAMETERS_0_HwAlloc', - 'struct_c__SA_NVOS32_PARAMETERS_0_HwFree', - 'struct_c__SA_NVOS32_PARAMETERS_0_Info', - 'struct_c__SA_NVOS32_PARAMETERS_0_ReacquireCompr', - 'struct_c__SA_NVOS32_PARAMETERS_0_ReleaseCompr', - 'struct_c__SA_NVOS33_PARAMETERS', - 'struct_c__SA_NVOS34_PARAMETERS', - 'struct_c__SA_NVOS38_PARAMETERS', - 'struct_c__SA_NVOS39_PARAMETERS', - 'struct_c__SA_NVOS41_PARAMETERS', - 'struct_c__SA_NVOS46_PARAMETERS', - 'struct_c__SA_NVOS47_PARAMETERS', - 'struct_c__SA_NVOS49_PARAMETERS', - 'struct_c__SA_NVOS54_PARAMETERS', - 'struct_c__SA_NVOS55_PARAMETERS', - 'struct_c__SA_NVOS56_PARAMETERS', - 'struct_c__SA_NVOS57_PARAMETERS', - 'struct_c__SA_NVOS61_PARAMETERS', - 'struct_c__SA_NVOS62_PARAMETERS', - 'struct_c__SA_NVOS63_PARAMETERS', - 'struct_c__SA_NVOS64_PARAMETERS', - 'struct_c__SA_NVOS65_PARAMETERS', - 'struct_c__SA_NVOS_I2C_ACCESS_PARAMS', - 'struct_c__SA_NVPOWERSTATE_PARAMETERS', - 'struct_c__SA_NV_BSP_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_CONTEXT_DMA_ALLOCATION_PARAMS', - 'struct_c__SA_NV_CTXSHARE_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_GR_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_HOPPER_USERMODE_A_PARAMS', - 'struct_c__SA_NV_MEMORY_ALLOCATION_PARAMS', - 'struct_c__SA_NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS', - 'struct_c__SA_NV_ME_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_MSENC_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_NVJPG_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_OFA_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_OS_DESC_MEMORY_ALLOCATION_PARAMS', - 'struct_c__SA_NV_PPP_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_SEC2_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_SWRUNLIST_ALLOCATION_PARAMS', - 'struct_c__SA_NV_TIMEOUT_CONTROL_PARAMETERS', - 'struct_c__SA_NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS', - 'struct_c__SA_NV_VASPACE_ALLOCATION_PARAMETERS', - 'struct_c__SA_NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS', - 'struct_c__SA_NV_VP_ALLOCATION_PARAMETERS', - 'struct_c__SA_Nv2080EccDbeNotification', - 'struct_c__SA_Nv2080HotplugNotification', - 'struct_c__SA_Nv2080LpwrDifrPrefetchNotification', - 'struct_c__SA_Nv2080NvlinkLnkChangeNotification', - 'struct_c__SA_Nv2080PowerEventNotification', - 'struct_c__SA_Nv2080PrivRegAccessFaultNotification', - 'struct_c__SA_Nv2080QosIntrNotification', - 'struct_c__SA_Nv2080VrrSetTimeoutNotification', - 'struct_c__SA_NvUnixEvent', 'struct_c__SA_UVM_ADD_SESSION_PARAMS', - 'struct_c__SA_UVM_ALLOC_DEVICE_P2P_PARAMS', - 'struct_c__SA_UVM_ALLOC_SEMAPHORE_POOL_PARAMS', - 'struct_c__SA_UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS', - 'struct_c__SA_UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS', - 'struct_c__SA_UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS', - 'struct_c__SA_UVM_CREATE_EVENT_QUEUE_PARAMS', - 'struct_c__SA_UVM_CREATE_EXTERNAL_RANGE_PARAMS', - 'struct_c__SA_UVM_CREATE_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_DEBUG_ACCESS_MEMORY_PARAMS', - 'struct_c__SA_UVM_DESTROY_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_DISABLE_PEER_ACCESS_PARAMS', - 'struct_c__SA_UVM_DISABLE_READ_DUPLICATION_PARAMS', - 'struct_c__SA_UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS', - 'struct_c__SA_UVM_ENABLE_COUNTERS_PARAMS', - 'struct_c__SA_UVM_ENABLE_PEER_ACCESS_PARAMS', - 'struct_c__SA_UVM_ENABLE_READ_DUPLICATION_PARAMS', - 'struct_c__SA_UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS', - 'struct_c__SA_UVM_EVENT_CTRL_PARAMS', - 'struct_c__SA_UVM_FREE_PARAMS', - 'struct_c__SA_UVM_GET_GPU_UUID_TABLE_PARAMS', - 'struct_c__SA_UVM_INITIALIZE_PARAMS', - 'struct_c__SA_UVM_IS_8_SUPPORTED_PARAMS', - 'struct_c__SA_UVM_MAP_COUNTER_PARAMS', - 'struct_c__SA_UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS', - 'struct_c__SA_UVM_MAP_EVENT_QUEUE_PARAMS', - 'struct_c__SA_UVM_MAP_EXTERNAL_ALLOCATION_PARAMS', - 'struct_c__SA_UVM_MAP_EXTERNAL_SPARSE_PARAMS', - 'struct_c__SA_UVM_MEM_MAP_PARAMS', - 'struct_c__SA_UVM_MIGRATE_PARAMS', - 'struct_c__SA_UVM_MIGRATE_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_MM_INITIALIZE_PARAMS', - 'struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS', - 'struct_c__SA_UVM_PAGEABLE_MEM_ACCESS_PARAMS', - 'struct_c__SA_UVM_POPULATE_PAGEABLE_PARAMS', - 'struct_c__SA_UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS', - 'struct_c__SA_UVM_REGION_COMMIT_PARAMS', - 'struct_c__SA_UVM_REGION_DECOMMIT_PARAMS', - 'struct_c__SA_UVM_REGION_SET_STREAM_PARAMS', - 'struct_c__SA_UVM_REGISTER_CHANNEL_PARAMS', - 'struct_c__SA_UVM_REGISTER_GPU_PARAMS', - 'struct_c__SA_UVM_REGISTER_GPU_VASPACE_PARAMS', - 'struct_c__SA_UVM_REGISTER_MPS_CLIENT_PARAMS', - 'struct_c__SA_UVM_REGISTER_MPS_SERVER_PARAMS', - 'struct_c__SA_UVM_RELEASE_VA_PARAMS', - 'struct_c__SA_UVM_REMOVE_EVENT_QUEUE_PARAMS', - 'struct_c__SA_UVM_REMOVE_SESSION_PARAMS', - 'struct_c__SA_UVM_RESERVE_VA_PARAMS', - 'struct_c__SA_UVM_RUN_TEST_PARAMS', - 'struct_c__SA_UVM_RUN_TEST_PARAMS_multiGpu', - 'struct_c__SA_UVM_SET_ACCESSED_BY_PARAMS', - 'struct_c__SA_UVM_SET_PREFERRED_LOCATION_PARAMS', - 'struct_c__SA_UVM_SET_RANGE_GROUP_PARAMS', - 'struct_c__SA_UVM_SET_STREAM_RUNNING_PARAMS', - 'struct_c__SA_UVM_SET_STREAM_STOPPED_PARAMS', - 'struct_c__SA_UVM_TOOLS_DISABLE_COUNTERS_PARAMS', - 'struct_c__SA_UVM_TOOLS_ENABLE_COUNTERS_PARAMS', - 'struct_c__SA_UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS', - 'struct_c__SA_UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS', - 'struct_c__SA_UVM_TOOLS_FLUSH_EVENTS_PARAMS', - 'struct_c__SA_UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS', - 'struct_c__SA_UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS', - 'struct_c__SA_UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS', - 'struct_c__SA_UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS', - 'struct_c__SA_UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS', - 'struct_c__SA_UVM_UNMAP_EXTERNAL_PARAMS', - 'struct_c__SA_UVM_UNREGISTER_CHANNEL_PARAMS', - 'struct_c__SA_UVM_UNREGISTER_GPU_PARAMS', - 'struct_c__SA_UVM_UNREGISTER_GPU_VASPACE_PARAMS', - 'struct_c__SA_UVM_UNSET_ACCESSED_BY_PARAMS', - 'struct_c__SA_UVM_UNSET_PREFERRED_LOCATION_PARAMS', - 'struct_c__SA_UVM_VALIDATE_VA_RANGE_PARAMS', - 'struct_c__SA_UvmCounterConfig', - 'struct_c__SA_UvmGpuMappingAttributes', - 'struct_c__SA_nv_ioctl_nvos02_parameters_with_fd', - 'struct_c__SA_nv_ioctl_nvos33_parameters_with_fd', - 'struct_c__SA_nv_pci_info_t', 'struct_nv_ioctl_alloc_os_event', - 'struct_nv_ioctl_card_info', - 'struct_nv_ioctl_export_to_dma_buf_fd', - 'struct_nv_ioctl_free_os_event', 'struct_nv_ioctl_numa_info', - 'struct_nv_ioctl_query_device_intr', - 'struct_nv_ioctl_register_fd', 'struct_nv_ioctl_rm_api_version', - 'struct_nv_ioctl_set_numa_status', 'struct_nv_ioctl_status_code', - 'struct_nv_ioctl_sys_params', - 'struct_nv_ioctl_wait_open_complete', 'struct_nv_ioctl_xfer', - 'struct_nv_uuid', 'struct_offline_addresses', 'union_CC_KMB_0', - 'union_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data', - 'union_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam', - 'union_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data', - 'union_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data', - 'union_NV2080_CTRL_BIOS_NBSI_REG_STRING_value', - 'union_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams', - 'union_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data', - 'union_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString', - 'union_NV2080_CTRL_GPU_PID_INFO_DATA', - 'union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData', - 'union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams', - 'union_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams', - 'union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data', - 'union_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData', - 'union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE', - 'union_RM_GSP_SPDM_CMD', 'union_c__SA_NVOS32_PARAMETERS_data'] -NVCEC0_QMDV05_00_RELEASE0_ENABLE=NVCEC0_QMDV05_00_RELEASE_ENABLE(0) -NVCEC0_QMDV05_00_RELEASE1_ENABLE=NVCEC0_QMDV05_00_RELEASE_ENABLE(1) # macro -nv_status_codes = {} -NV_OK = 0x00000000 -nv_status_codes[NV_OK] = "Success" -NV_ERR_GENERIC = 0x0000FFFF -nv_status_codes[NV_ERR_GENERIC] = "Failure: Generic Error" -NV_ERR_BROKEN_FB = 0x00000001 -nv_status_codes[NV_ERR_BROKEN_FB] = "Frame-Buffer broken" -NV_ERR_BUFFER_TOO_SMALL = 0x00000002 -nv_status_codes[NV_ERR_BUFFER_TOO_SMALL] = "Buffer passed in is too small" -NV_ERR_BUSY_RETRY = 0x00000003 -nv_status_codes[NV_ERR_BUSY_RETRY] = "System is busy, retry later" -NV_ERR_CALLBACK_NOT_SCHEDULED = 0x00000004 -nv_status_codes[NV_ERR_CALLBACK_NOT_SCHEDULED] = "The requested callback API not scheduled" -NV_ERR_CARD_NOT_PRESENT = 0x00000005 -nv_status_codes[NV_ERR_CARD_NOT_PRESENT] = "Card not detected" -NV_ERR_CYCLE_DETECTED = 0x00000006 -nv_status_codes[NV_ERR_CYCLE_DETECTED] = "Call cycle detected" -NV_ERR_DMA_IN_USE = 0x00000007 -nv_status_codes[NV_ERR_DMA_IN_USE] = "Requested DMA is in use" -NV_ERR_DMA_MEM_NOT_LOCKED = 0x00000008 -nv_status_codes[NV_ERR_DMA_MEM_NOT_LOCKED] = "Requested DMA memory is not locked" -NV_ERR_DMA_MEM_NOT_UNLOCKED = 0x00000009 -nv_status_codes[NV_ERR_DMA_MEM_NOT_UNLOCKED] = "Requested DMA memory is not unlocked" -NV_ERR_DUAL_LINK_INUSE = 0x0000000A -nv_status_codes[NV_ERR_DUAL_LINK_INUSE] = "Dual-Link is in use" -NV_ERR_ECC_ERROR = 0x0000000B -nv_status_codes[NV_ERR_ECC_ERROR] = "Generic ECC error" -NV_ERR_FIFO_BAD_ACCESS = 0x0000000C -nv_status_codes[NV_ERR_FIFO_BAD_ACCESS] = "FIFO: Invalid access" -NV_ERR_FREQ_NOT_SUPPORTED = 0x0000000D -nv_status_codes[NV_ERR_FREQ_NOT_SUPPORTED] = "Requested frequency is not supported" -NV_ERR_GPU_DMA_NOT_INITIALIZED = 0x0000000E -nv_status_codes[NV_ERR_GPU_DMA_NOT_INITIALIZED] = "Requested DMA not initialized" -NV_ERR_GPU_IS_LOST = 0x0000000F -nv_status_codes[NV_ERR_GPU_IS_LOST] = "GPU lost from the bus" -NV_ERR_GPU_IN_FULLCHIP_RESET = 0x00000010 -nv_status_codes[NV_ERR_GPU_IN_FULLCHIP_RESET] = "GPU currently in full-chip reset" -NV_ERR_GPU_NOT_FULL_POWER = 0x00000011 -nv_status_codes[NV_ERR_GPU_NOT_FULL_POWER] = "GPU not in full power" -NV_ERR_GPU_UUID_NOT_FOUND = 0x00000012 -nv_status_codes[NV_ERR_GPU_UUID_NOT_FOUND] = "GPU UUID not found" -NV_ERR_HOT_SWITCH = 0x00000013 -nv_status_codes[NV_ERR_HOT_SWITCH] = "System in hot switch" -NV_ERR_I2C_ERROR = 0x00000014 -nv_status_codes[NV_ERR_I2C_ERROR] = "I2C Error" -NV_ERR_I2C_SPEED_TOO_HIGH = 0x00000015 -nv_status_codes[NV_ERR_I2C_SPEED_TOO_HIGH] = "I2C Error: Speed too high" -NV_ERR_ILLEGAL_ACTION = 0x00000016 -nv_status_codes[NV_ERR_ILLEGAL_ACTION] = "Current action is not allowed" -NV_ERR_IN_USE = 0x00000017 -nv_status_codes[NV_ERR_IN_USE] = "Generic busy error" -NV_ERR_INFLATE_COMPRESSED_DATA_FAILED = 0x00000018 -nv_status_codes[NV_ERR_INFLATE_COMPRESSED_DATA_FAILED] = "Failed to inflate compressed data" -NV_ERR_INSERT_DUPLICATE_NAME = 0x00000019 -nv_status_codes[NV_ERR_INSERT_DUPLICATE_NAME] = "Found a duplicate entry in the requested btree" -NV_ERR_INSUFFICIENT_RESOURCES = 0x0000001A -nv_status_codes[NV_ERR_INSUFFICIENT_RESOURCES] = "Ran out of a critical resource, other than memory" -NV_ERR_INSUFFICIENT_PERMISSIONS = 0x0000001B -nv_status_codes[NV_ERR_INSUFFICIENT_PERMISSIONS] = "The requester does not have sufficient permissions" -NV_ERR_INSUFFICIENT_POWER = 0x0000001C -nv_status_codes[NV_ERR_INSUFFICIENT_POWER] = "Generic Error: Low power" -NV_ERR_INVALID_ACCESS_TYPE = 0x0000001D -nv_status_codes[NV_ERR_INVALID_ACCESS_TYPE] = "This type of access is not allowed" -NV_ERR_INVALID_ADDRESS = 0x0000001E -nv_status_codes[NV_ERR_INVALID_ADDRESS] = "Address not valid" -NV_ERR_INVALID_ARGUMENT = 0x0000001F -nv_status_codes[NV_ERR_INVALID_ARGUMENT] = "Invalid argument to call" -NV_ERR_INVALID_BASE = 0x00000020 -nv_status_codes[NV_ERR_INVALID_BASE] = "Invalid base" -NV_ERR_INVALID_CHANNEL = 0x00000021 -nv_status_codes[NV_ERR_INVALID_CHANNEL] = "Given channel-id not valid" -NV_ERR_INVALID_CLASS = 0x00000022 -nv_status_codes[NV_ERR_INVALID_CLASS] = "Given class-id not valid" -NV_ERR_INVALID_CLIENT = 0x00000023 -nv_status_codes[NV_ERR_INVALID_CLIENT] = "Given client not valid" -NV_ERR_INVALID_COMMAND = 0x00000024 -nv_status_codes[NV_ERR_INVALID_COMMAND] = "Command passed is not valid" -NV_ERR_INVALID_DATA = 0x00000025 -nv_status_codes[NV_ERR_INVALID_DATA] = "Invalid data passed" -NV_ERR_INVALID_DEVICE = 0x00000026 -nv_status_codes[NV_ERR_INVALID_DEVICE] = "Current device is not valid" -NV_ERR_INVALID_DMA_SPECIFIER = 0x00000027 -nv_status_codes[NV_ERR_INVALID_DMA_SPECIFIER] = "The requested DMA specifier is not valid" -NV_ERR_INVALID_EVENT = 0x00000028 -nv_status_codes[NV_ERR_INVALID_EVENT] = "Invalid event occurred" -NV_ERR_INVALID_FLAGS = 0x00000029 -nv_status_codes[NV_ERR_INVALID_FLAGS] = "Invalid flags passed" -NV_ERR_INVALID_FUNCTION = 0x0000002A -nv_status_codes[NV_ERR_INVALID_FUNCTION] = "Called function is not valid" -NV_ERR_INVALID_HEAP = 0x0000002B -nv_status_codes[NV_ERR_INVALID_HEAP] = "Heap corrupted" -NV_ERR_INVALID_INDEX = 0x0000002C -nv_status_codes[NV_ERR_INVALID_INDEX] = "Index invalid" -NV_ERR_INVALID_IRQ_LEVEL = 0x0000002D -nv_status_codes[NV_ERR_INVALID_IRQ_LEVEL] = "Requested IRQ level is not valid" -NV_ERR_INVALID_LIMIT = 0x0000002E -nv_status_codes[NV_ERR_INVALID_LIMIT] = "Generic Error: Invalid limit" -NV_ERR_INVALID_LOCK_STATE = 0x0000002F -nv_status_codes[NV_ERR_INVALID_LOCK_STATE] = "Requested lock state not valid" -NV_ERR_INVALID_METHOD = 0x00000030 -nv_status_codes[NV_ERR_INVALID_METHOD] = "Requested method not valid" -NV_ERR_INVALID_OBJECT = 0x00000031 -nv_status_codes[NV_ERR_INVALID_OBJECT] = "Object not valid" -NV_ERR_INVALID_OBJECT_BUFFER = 0x00000032 -nv_status_codes[NV_ERR_INVALID_OBJECT_BUFFER] = "Object buffer passed is not valid" -NV_ERR_INVALID_OBJECT_HANDLE = 0x00000033 -nv_status_codes[NV_ERR_INVALID_OBJECT_HANDLE] = "Object handle is not valid" -NV_ERR_INVALID_OBJECT_NEW = 0x00000034 -nv_status_codes[NV_ERR_INVALID_OBJECT_NEW] = "New object is not valid" -NV_ERR_INVALID_OBJECT_OLD = 0x00000035 -nv_status_codes[NV_ERR_INVALID_OBJECT_OLD] = "Old object is not valid" -NV_ERR_INVALID_OBJECT_PARENT = 0x00000036 -nv_status_codes[NV_ERR_INVALID_OBJECT_PARENT] = "Object parent is not valid" -NV_ERR_INVALID_OFFSET = 0x00000037 -nv_status_codes[NV_ERR_INVALID_OFFSET] = "The offset passed is not valid" -NV_ERR_INVALID_OPERATION = 0x00000038 -nv_status_codes[NV_ERR_INVALID_OPERATION] = "Requested operation is not valid" -NV_ERR_INVALID_OWNER = 0x00000039 -nv_status_codes[NV_ERR_INVALID_OWNER] = "Owner not valid" -NV_ERR_INVALID_PARAM_STRUCT = 0x0000003A -nv_status_codes[NV_ERR_INVALID_PARAM_STRUCT] = "Invalid structure parameter" -NV_ERR_INVALID_PARAMETER = 0x0000003B -nv_status_codes[NV_ERR_INVALID_PARAMETER] = "At least one of the parameters passed is not valid" -NV_ERR_INVALID_PATH = 0x0000003C -nv_status_codes[NV_ERR_INVALID_PATH] = "The requested path is not valid" -NV_ERR_INVALID_POINTER = 0x0000003D -nv_status_codes[NV_ERR_INVALID_POINTER] = "Pointer not valid" -NV_ERR_INVALID_REGISTRY_KEY = 0x0000003E -nv_status_codes[NV_ERR_INVALID_REGISTRY_KEY] = "Found an invalid registry key" -NV_ERR_INVALID_REQUEST = 0x0000003F -nv_status_codes[NV_ERR_INVALID_REQUEST] = "Generic Error: Invalid request" -NV_ERR_INVALID_STATE = 0x00000040 -nv_status_codes[NV_ERR_INVALID_STATE] = "Generic Error: Invalid state" -NV_ERR_INVALID_STRING_LENGTH = 0x00000041 -nv_status_codes[NV_ERR_INVALID_STRING_LENGTH] = "The string length is not valid" -NV_ERR_INVALID_READ = 0x00000042 -nv_status_codes[NV_ERR_INVALID_READ] = "The requested read operation is not valid" -NV_ERR_INVALID_WRITE = 0x00000043 -nv_status_codes[NV_ERR_INVALID_WRITE] = "The requested write operation is not valid" -NV_ERR_INVALID_XLATE = 0x00000044 -nv_status_codes[NV_ERR_INVALID_XLATE] = "The requested translate operation is not valid" -NV_ERR_IRQ_NOT_FIRING = 0x00000045 -nv_status_codes[NV_ERR_IRQ_NOT_FIRING] = "Requested IRQ is not firing" -NV_ERR_IRQ_EDGE_TRIGGERED = 0x00000046 -nv_status_codes[NV_ERR_IRQ_EDGE_TRIGGERED] = "IRQ is edge triggered" -NV_ERR_MEMORY_TRAINING_FAILED = 0x00000047 -nv_status_codes[NV_ERR_MEMORY_TRAINING_FAILED] = "Failed memory training sequence" -NV_ERR_MISMATCHED_SLAVE = 0x00000048 -nv_status_codes[NV_ERR_MISMATCHED_SLAVE] = "Slave mismatch" -NV_ERR_MISMATCHED_TARGET = 0x00000049 -nv_status_codes[NV_ERR_MISMATCHED_TARGET] = "Target mismatch" -NV_ERR_MISSING_TABLE_ENTRY = 0x0000004A -nv_status_codes[NV_ERR_MISSING_TABLE_ENTRY] = "Requested entry missing not found in the table" -NV_ERR_MODULE_LOAD_FAILED = 0x0000004B -nv_status_codes[NV_ERR_MODULE_LOAD_FAILED] = "Failed to load the requested module" -NV_ERR_MORE_DATA_AVAILABLE = 0x0000004C -nv_status_codes[NV_ERR_MORE_DATA_AVAILABLE] = "There is more data available" -NV_ERR_MORE_PROCESSING_REQUIRED = 0x0000004D -nv_status_codes[NV_ERR_MORE_PROCESSING_REQUIRED] = "More processing required for the given call" -NV_ERR_MULTIPLE_MEMORY_TYPES = 0x0000004E -nv_status_codes[NV_ERR_MULTIPLE_MEMORY_TYPES] = "Multiple memory types found" -NV_ERR_NO_FREE_FIFOS = 0x0000004F -nv_status_codes[NV_ERR_NO_FREE_FIFOS] = "No more free FIFOs found" -NV_ERR_NO_INTR_PENDING = 0x00000050 -nv_status_codes[NV_ERR_NO_INTR_PENDING] = "No interrupt pending" -NV_ERR_NO_MEMORY = 0x00000051 -nv_status_codes[NV_ERR_NO_MEMORY] = "Out of memory" -NV_ERR_NO_SUCH_DOMAIN = 0x00000052 -nv_status_codes[NV_ERR_NO_SUCH_DOMAIN] = "Requested domain does not exist" -NV_ERR_NO_VALID_PATH = 0x00000053 -nv_status_codes[NV_ERR_NO_VALID_PATH] = "Caller did not specify a valid path" -NV_ERR_NOT_COMPATIBLE = 0x00000054 -nv_status_codes[NV_ERR_NOT_COMPATIBLE] = "Generic Error: Incompatible types" -NV_ERR_NOT_READY = 0x00000055 -nv_status_codes[NV_ERR_NOT_READY] = "Generic Error: Not ready" -NV_ERR_NOT_SUPPORTED = 0x00000056 -nv_status_codes[NV_ERR_NOT_SUPPORTED] = "Call not supported" -NV_ERR_OBJECT_NOT_FOUND = 0x00000057 -nv_status_codes[NV_ERR_OBJECT_NOT_FOUND] = "Requested object not found" -NV_ERR_OBJECT_TYPE_MISMATCH = 0x00000058 -nv_status_codes[NV_ERR_OBJECT_TYPE_MISMATCH] = "Specified objects do not match" -NV_ERR_OPERATING_SYSTEM = 0x00000059 -nv_status_codes[NV_ERR_OPERATING_SYSTEM] = "Generic operating system error" -NV_ERR_OTHER_DEVICE_FOUND = 0x0000005A -nv_status_codes[NV_ERR_OTHER_DEVICE_FOUND] = "Found other device instead of the requested one" -NV_ERR_OUT_OF_RANGE = 0x0000005B -nv_status_codes[NV_ERR_OUT_OF_RANGE] = "The specified value is out of bounds" -NV_ERR_OVERLAPPING_UVM_COMMIT = 0x0000005C -nv_status_codes[NV_ERR_OVERLAPPING_UVM_COMMIT] = "Overlapping unified virtual memory commit" -NV_ERR_PAGE_TABLE_NOT_AVAIL = 0x0000005D -nv_status_codes[NV_ERR_PAGE_TABLE_NOT_AVAIL] = "Requested page table not available" -NV_ERR_PID_NOT_FOUND = 0x0000005E -nv_status_codes[NV_ERR_PID_NOT_FOUND] = "Process-Id not found" -NV_ERR_PROTECTION_FAULT = 0x0000005F -nv_status_codes[NV_ERR_PROTECTION_FAULT] = "Protection fault" -NV_ERR_RC_ERROR = 0x00000060 -nv_status_codes[NV_ERR_RC_ERROR] = "Generic RC error" -NV_ERR_REJECTED_VBIOS = 0x00000061 -nv_status_codes[NV_ERR_REJECTED_VBIOS] = "Given Video BIOS rejected/invalid" -NV_ERR_RESET_REQUIRED = 0x00000062 -nv_status_codes[NV_ERR_RESET_REQUIRED] = "Reset required" -NV_ERR_STATE_IN_USE = 0x00000063 -nv_status_codes[NV_ERR_STATE_IN_USE] = "State in use" -NV_ERR_SIGNAL_PENDING = 0x00000064 -nv_status_codes[NV_ERR_SIGNAL_PENDING] = "Signal pending" -NV_ERR_TIMEOUT = 0x00000065 -nv_status_codes[NV_ERR_TIMEOUT] = "Call timed out" -NV_ERR_TIMEOUT_RETRY = 0x00000066 -nv_status_codes[NV_ERR_TIMEOUT_RETRY] = "Call timed out, please retry later" -NV_ERR_TOO_MANY_PRIMARIES = 0x00000067 -nv_status_codes[NV_ERR_TOO_MANY_PRIMARIES] = "Too many primaries" -NV_ERR_UVM_ADDRESS_IN_USE = 0x00000068 -nv_status_codes[NV_ERR_UVM_ADDRESS_IN_USE] = "Unified virtual memory requested address already in use" -NV_ERR_MAX_SESSION_LIMIT_REACHED = 0x00000069 -nv_status_codes[NV_ERR_MAX_SESSION_LIMIT_REACHED] = "Maximum number of sessions reached" -NV_ERR_LIB_RM_VERSION_MISMATCH = 0x0000006A -nv_status_codes[NV_ERR_LIB_RM_VERSION_MISMATCH] = "Library version doesn't match driver version" -NV_ERR_PRIV_SEC_VIOLATION = 0x0000006B -nv_status_codes[NV_ERR_PRIV_SEC_VIOLATION] = "Priv security violation" -NV_ERR_GPU_IN_DEBUG_MODE = 0x0000006C -nv_status_codes[NV_ERR_GPU_IN_DEBUG_MODE] = "GPU currently in debug mode" -NV_ERR_FEATURE_NOT_ENABLED = 0x0000006D -nv_status_codes[NV_ERR_FEATURE_NOT_ENABLED] = "Requested Feature functionality is not enabled" -NV_ERR_RESOURCE_LOST = 0x0000006E -nv_status_codes[NV_ERR_RESOURCE_LOST] = "Requested resource has been destroyed" -NV_ERR_PMU_NOT_READY = 0x0000006F -nv_status_codes[NV_ERR_PMU_NOT_READY] = "PMU is not ready or has not yet been initialized" -NV_ERR_FLCN_ERROR = 0x00000070 -nv_status_codes[NV_ERR_FLCN_ERROR] = "Generic falcon assert or halt" -NV_ERR_FATAL_ERROR = 0x00000071 -nv_status_codes[NV_ERR_FATAL_ERROR] = "Fatal/unrecoverable error" -NV_ERR_MEMORY_ERROR = 0x00000072 -nv_status_codes[NV_ERR_MEMORY_ERROR] = "Generic memory error" -NV_ERR_INVALID_LICENSE = 0x00000073 -nv_status_codes[NV_ERR_INVALID_LICENSE] = "License provided is rejected or invalid" -NV_ERR_NVLINK_INIT_ERROR = 0x00000074 -nv_status_codes[NV_ERR_NVLINK_INIT_ERROR] = "Nvlink Init Error" -NV_ERR_NVLINK_MINION_ERROR = 0x00000075 -nv_status_codes[NV_ERR_NVLINK_MINION_ERROR] = "Nvlink Minion Error" -NV_ERR_NVLINK_CLOCK_ERROR = 0x00000076 -nv_status_codes[NV_ERR_NVLINK_CLOCK_ERROR] = "Nvlink Clock Error" -NV_ERR_NVLINK_TRAINING_ERROR = 0x00000077 -nv_status_codes[NV_ERR_NVLINK_TRAINING_ERROR] = "Nvlink Training Error" -NV_ERR_NVLINK_CONFIGURATION_ERROR = 0x00000078 -nv_status_codes[NV_ERR_NVLINK_CONFIGURATION_ERROR] = "Nvlink Configuration Error" -NV_ERR_RISCV_ERROR = 0x00000079 -nv_status_codes[NV_ERR_RISCV_ERROR] = "Generic RISC-V assert or halt" -NV_ERR_FABRIC_MANAGER_NOT_PRESENT = 0x0000007A -nv_status_codes[NV_ERR_FABRIC_MANAGER_NOT_PRESENT] = "Fabric Manager is not loaded" -NV_ERR_ALREADY_SIGNALLED = 0x0000007B -nv_status_codes[NV_ERR_ALREADY_SIGNALLED] = "Semaphore Surface value already >= requested wait value" -NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE = 0x0000007C -nv_status_codes[NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE] = "PMU RPC error due to no queue slot available for this event" -NV_ERR_KEY_ROTATION_IN_PROGRESS = 0x0000007D -nv_status_codes[NV_ERR_KEY_ROTATION_IN_PROGRESS] = "Operation not allowed as key rotation is in progress" -NV_ERR_TEST_ONLY_CODE_NOT_ENABLED = 0x0000007E -nv_status_codes[NV_ERR_TEST_ONLY_CODE_NOT_ENABLED] = "Test-only code path not enabled" -NV_ERR_SECURE_BOOT_FAILED = 0x0000007F -nv_status_codes[NV_ERR_SECURE_BOOT_FAILED] = "GFW secure boot failed" -NV_ERR_INSUFFICIENT_ZBC_ENTRY = 0x00000080 -nv_status_codes[NV_ERR_INSUFFICIENT_ZBC_ENTRY] = "No more ZBC entry for the client" -NV_ERR_NVLINK_FABRIC_NOT_READY = 0x00000081 -nv_status_codes[NV_ERR_NVLINK_FABRIC_NOT_READY] = "Nvlink Fabric Status or Fabric Probe is not yet complete, caller needs to retry" -NV_ERR_NVLINK_FABRIC_FAILURE = 0x00000082 -nv_status_codes[NV_ERR_NVLINK_FABRIC_FAILURE] = "Nvlink Fabric Probe failed" -NV_ERR_GPU_MEMORY_ONLINING_FAILURE = 0x00000083 -nv_status_codes[NV_ERR_GPU_MEMORY_ONLINING_FAILURE] = "GPU Memory Onlining failed" -NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE = 0x00000084 -nv_status_codes[NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE] = "Reduction Manager is not available" -NV_WARN_HOT_SWITCH = 0x00010001 -nv_status_codes[NV_WARN_HOT_SWITCH] = "WARNING Hot switch" -NV_WARN_INCORRECT_PERFMON_DATA = 0x00010002 -nv_status_codes[NV_WARN_INCORRECT_PERFMON_DATA] = "WARNING Incorrect performance monitor data" -NV_WARN_MISMATCHED_SLAVE = 0x00010003 -nv_status_codes[NV_WARN_MISMATCHED_SLAVE] = "WARNING Slave mismatch" -NV_WARN_MISMATCHED_TARGET = 0x00010004 -nv_status_codes[NV_WARN_MISMATCHED_TARGET] = "WARNING Target mismatch" -NV_WARN_MORE_PROCESSING_REQUIRED = 0x00010005 -nv_status_codes[NV_WARN_MORE_PROCESSING_REQUIRED] = "WARNING More processing required for the call" -NV_WARN_NOTHING_TO_DO = 0x00010006 -nv_status_codes[NV_WARN_NOTHING_TO_DO] = "WARNING Nothing to do" -NV_WARN_NULL_OBJECT = 0x00010007 -nv_status_codes[NV_WARN_NULL_OBJECT] = "WARNING NULL object found" -NV_WARN_OUT_OF_RANGE = 0x00010008 -nv_status_codes[NV_WARN_OUT_OF_RANGE] = "WARNING value out of range" +NVC6C0_QMDV02_03_OUTER_PUT = (30, 0) +NVC6C0_QMDV02_03_OUTER_OVERFLOW = (31, 31) +NVC6C0_QMDV02_03_OUTER_GET = (62, 32) +NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW = (63, 63) +NVC6C0_QMDV02_03_INNER_GET = (94, 64) +NVC6C0_QMDV02_03_INNER_OVERFLOW = (95, 95) +NVC6C0_QMDV02_03_INNER_PUT = (126, 96) +NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW = (127, 127) +NVC6C0_QMDV02_03_QMD_GROUP_ID = (133, 128) +NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE = (134, 134) +NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135) +NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 +NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 +NVC6C0_QMDV02_03_IS_QUEUE = (136, 136) +NVC6C0_QMDV02_03_IS_QUEUE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_IS_QUEUE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137) +NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 +NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 +NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 = (138, 138) +NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 +NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 +NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 = (139, 139) +NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 +NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 +NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS = (140, 140) +NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 +NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 +NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE = (141, 141) +NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE = (142, 142) +NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE = 0x00000000 +NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID = 0x00000001 +NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY = (143, 143) +NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE = 0x00000000 +NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE = 0x00000001 +NVC6C0_QMDV02_03_QMD_RESERVED_B = (159, 144) +NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE = (184, 160) +NVC6C0_QMDV02_03_QMD_RESERVED_C = (185, 185) +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186) +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187) +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188) +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE = (189, 189) +NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE = (190, 190) +NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191) +NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME = (223, 192) +NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME = (239, 224) +NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME = (255, 240) +NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256) +NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288) +NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320) +NVC6C0_QMDV02_03_QMD_RESERVED_D = (335, 328) +NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336) +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID = (357, 352) +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358) +NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE = (366, 366) +NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367) +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE = (369, 368) +NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 +NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 +NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS = (370, 370) +NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 +NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371) +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT = (378, 378) +NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 +NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 +NVC6C0_QMDV02_03_SAMPLER_INDEX = (382, 382) +NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 +NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 +NVC6C0_QMDV02_03_CTA_RASTER_WIDTH = (415, 384) +NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT = (431, 416) +NVC6C0_QMDV02_03_QMD_RESERVED13A = (447, 432) +NVC6C0_QMDV02_03_CTA_RASTER_DEPTH = (463, 448) +NVC6C0_QMDV02_03_QMD_RESERVED14A = (479, 464) +NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER = (511, 480) +NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD = (529, 522) +NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530) +NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE = (561, 544) +NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562) +NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569) +NVC6C0_QMDV02_03_QMD_VERSION = (579, 576) +NVC6C0_QMDV02_03_QMD_MAJOR_VERSION = (583, 580) +NVC6C0_QMDV02_03_QMD_RESERVED_H = (591, 584) +NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 = (607, 592) +NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 = (623, 608) +NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 = (639, 624) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 +NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 +NVC6C0_QMDV02_03_REGISTER_COUNT_V = (656, 648) +NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657) +NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM = (671, 664) +NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER = (703, 672) +NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER = (735, 704) +NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER = (767, 736) +NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER = (775, 768) +NVC6C0_QMDV02_03_QMD_RESERVED_J = (783, 776) +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP = (790, 788) +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV02_03_QMD_RESERVED_K = (791, 791) +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT = (793, 792) +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE = (794, 794) +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE = (799, 799) +NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 +NVC6C0_QMDV02_03_RELEASE0_PAYLOAD = (831, 800) +NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER = (863, 832) +NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER = (871, 864) +NVC6C0_QMDV02_03_QMD_RESERVED_L = (879, 872) +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP = (886, 884) +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV02_03_QMD_RESERVED_M = (887, 887) +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT = (889, 888) +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE = (890, 890) +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE = (895, 895) +NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 +NVC6C0_QMDV02_03_RELEASE1_PAYLOAD = (927, 896) +NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928) +NVC6C0_QMDV02_03_QMD_RESERVED_N = (954, 952) +NVC6C0_QMDV02_03_BARRIER_COUNT = (959, 955) +NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960) +NVC6C0_QMDV02_03_REGISTER_COUNT = (991, 984) +NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992) +NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE = (1009, 1001) +NVC6C0_QMDV02_03_QMD_RESERVED_A = (1015, 1010) +NVC6C0_QMDV02_03_SASS_VERSION = (1023, 1016) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 +NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 +NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) +NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 +NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 +NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) +NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER = (1567, 1536) +NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER = (1584, 1568) +NVC6C0_QMDV02_03_QMD_RESERVED_S = (1599, 1585) +NVC6C0_QMDV02_03_HW_ONLY_INNER_GET = (1630, 1600) +NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631) +NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT = (1662, 1632) +NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE = (1663, 1663) +NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664) +NVC6C0_QMDV02_03_QMD_RESERVED_Q = (1694, 1694) +NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695) +NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 +NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 +NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696) +NVC6C0_QMDV02_03_QMD_SPARE_G = (1759, 1728) +NVC6C0_QMDV02_03_QMD_SPARE_H = (1791, 1760) +NVC6C0_QMDV02_03_QMD_SPARE_I = (1823, 1792) +NVC6C0_QMDV02_03_QMD_SPARE_J = (1855, 1824) +NVC6C0_QMDV02_03_QMD_SPARE_K = (1887, 1856) +NVC6C0_QMDV02_03_QMD_SPARE_L = (1919, 1888) +NVC6C0_QMDV02_03_QMD_SPARE_M = (1951, 1920) +NVC6C0_QMDV02_03_QMD_SPARE_N = (1983, 1952) +NVC6C0_QMDV02_03_DEBUG_ID_UPPER = (2015, 1984) +NVC6C0_QMDV02_03_DEBUG_ID_LOWER = (2047, 2016) +NVC6C0_QMDV02_04_OUTER_PUT = (30, 0) +NVC6C0_QMDV02_04_OUTER_OVERFLOW = (31, 31) +NVC6C0_QMDV02_04_OUTER_GET = (62, 32) +NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW = (63, 63) +NVC6C0_QMDV02_04_INNER_GET = (94, 64) +NVC6C0_QMDV02_04_INNER_OVERFLOW = (95, 95) +NVC6C0_QMDV02_04_INNER_PUT = (126, 96) +NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW = (127, 127) +NVC6C0_QMDV02_04_QMD_GROUP_ID = (133, 128) +NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE = (134, 134) +NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135) +NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 +NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 +NVC6C0_QMDV02_04_IS_QUEUE = (136, 136) +NVC6C0_QMDV02_04_IS_QUEUE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_IS_QUEUE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137) +NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 +NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 +NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 = (138, 138) +NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000 +NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001 +NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 = (139, 139) +NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000 +NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001 +NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS = (140, 140) +NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 +NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE = (141, 141) +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION = (144, 142) +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH = (145, 145) +NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 +NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE = (146, 146) +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION = (149, 147) +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH = (150, 150) +NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 +NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 +NVC6C0_QMDV02_04_DEPENDENCE_COUNTER = (157, 151) +NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION = (158, 158) +NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 +NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 +NVC6C0_QMDV02_04_QMD_RESERVED_B = (159, 159) +NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE = (184, 160) +NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST = (185, 185) +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186) +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187) +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188) +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE = (189, 189) +NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE = (190, 190) +NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191) +NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME = (223, 192) +NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME = (239, 224) +NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME = (255, 240) +NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256) +NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288) +NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320) +NVC6C0_QMDV02_04_QMD_RESERVED_D = (335, 328) +NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336) +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID = (357, 352) +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358) +NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE = (366, 366) +NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367) +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE = (369, 368) +NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 +NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 +NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS = (370, 370) +NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 +NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371) +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT = (378, 378) +NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 +NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 +NVC6C0_QMDV02_04_SAMPLER_INDEX = (382, 382) +NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 +NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 +NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE = (383, 383) +NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_CTA_RASTER_WIDTH = (415, 384) +NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT = (431, 416) +NVC6C0_QMDV02_04_QMD_RESERVED13A = (447, 432) +NVC6C0_QMDV02_04_CTA_RASTER_DEPTH = (463, 448) +NVC6C0_QMDV02_04_QMD_RESERVED14A = (479, 464) +NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER = (511, 480) +NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD = (529, 522) +NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530) +NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE = (561, 544) +NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562) +NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569) +NVC6C0_QMDV02_04_QMD_VERSION = (579, 576) +NVC6C0_QMDV02_04_QMD_MAJOR_VERSION = (583, 580) +NVC6C0_QMDV02_04_QMD_RESERVED_H = (591, 584) +NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 = (607, 592) +NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 = (623, 608) +NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 = (639, 624) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 +NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 +NVC6C0_QMDV02_04_REGISTER_COUNT_V = (656, 648) +NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657) +NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM = (671, 664) +NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER = (703, 672) +NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER = (735, 704) +NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER = (767, 736) +NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER = (775, 768) +NVC6C0_QMDV02_04_QMD_RESERVED_J = (783, 776) +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP = (790, 788) +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV02_04_QMD_RESERVED_K = (791, 791) +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT = (793, 792) +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE = (794, 794) +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE = (799, 799) +NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001 +NVC6C0_QMDV02_04_RELEASE0_PAYLOAD = (831, 800) +NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER = (863, 832) +NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER = (871, 864) +NVC6C0_QMDV02_04_QMD_RESERVED_L = (879, 872) +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP = (886, 884) +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV02_04_QMD_RESERVED_M = (887, 887) +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT = (889, 888) +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE = (890, 890) +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE = (895, 895) +NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001 +NVC6C0_QMDV02_04_RELEASE1_PAYLOAD = (927, 896) +NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928) +NVC6C0_QMDV02_04_QMD_RESERVED_N = (954, 952) +NVC6C0_QMDV02_04_BARRIER_COUNT = (959, 955) +NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960) +NVC6C0_QMDV02_04_QMD_RESERVED_G = (991, 984) +NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992) +NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE = (1009, 1001) +NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE = (1011, 1010) +NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 +NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 +NVC6C0_QMDV02_04_QMD_RESERVED_A = (1015, 1012) +NVC6C0_QMDV02_04_SASS_VERSION = (1023, 1016) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 +NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 +NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) +NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 +NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 +NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) +NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER = (1567, 1536) +NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER = (1584, 1568) +NVC6C0_QMDV02_04_QMD_RESERVED_S = (1599, 1585) +NVC6C0_QMDV02_04_HW_ONLY_INNER_GET = (1630, 1600) +NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631) +NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT = (1662, 1632) +NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE = (1663, 1663) +NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664) +NVC6C0_QMDV02_04_QMD_RESERVED_Q = (1694, 1694) +NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695) +NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 +NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 +NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696) +NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER = (1734, 1728) +NVC6C0_QMDV02_04_QMD_RESERVED_I = (1759, 1735) +NVC6C0_QMDV02_04_QMD_SPARE_H = (1791, 1760) +NVC6C0_QMDV02_04_QMD_SPARE_I = (1823, 1792) +NVC6C0_QMDV02_04_QMD_SPARE_J = (1855, 1824) +NVC6C0_QMDV02_04_QMD_SPARE_K = (1887, 1856) +NVC6C0_QMDV02_04_QMD_SPARE_L = (1919, 1888) +NVC6C0_QMDV02_04_QMD_SPARE_M = (1951, 1920) +NVC6C0_QMDV02_04_QMD_SPARE_N = (1983, 1952) +NVC6C0_QMDV02_04_DEBUG_ID_UPPER = (2015, 1984) +NVC6C0_QMDV02_04_DEBUG_ID_LOWER = (2047, 2016) +NVC6C0_QMDV03_00_OUTER_PUT = (30, 0) +NVC6C0_QMDV03_00_OUTER_OVERFLOW = (31, 31) +NVC6C0_QMDV03_00_OUTER_GET = (62, 32) +NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW = (63, 63) +NVC6C0_QMDV03_00_INNER_GET = (94, 64) +NVC6C0_QMDV03_00_INNER_OVERFLOW = (95, 95) +NVC6C0_QMDV03_00_INNER_PUT = (126, 96) +NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW = (127, 127) +NVC6C0_QMDV03_00_QMD_GROUP_ID = (133, 128) +NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE = (134, 134) +NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135) +NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001 +NVC6C0_QMDV03_00_IS_QUEUE = (136, 136) +NVC6C0_QMDV03_00_IS_QUEUE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_IS_QUEUE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137) +NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 +NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 +NVC6C0_QMDV03_00_QMD_RESERVED04A = (139, 138) +NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS = (140, 140) +NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 +NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 +NVC6C0_QMDV03_00_QMD_RESERVED04B = (141, 141) +NVC6C0_QMDV03_00_DEPENDENCE_COUNTER = (157, 142) +NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION = (158, 158) +NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 +NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 +NVC6C0_QMDV03_00_QMD_RESERVED04C = (159, 159) +NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE = (184, 160) +NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST = (185, 185) +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186) +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187) +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188) +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE = (189, 189) +NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE = (190, 190) +NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191) +NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME = (223, 192) +NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME = (239, 224) +NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME = (255, 240) +NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256) +NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288) +NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320) +NVC6C0_QMDV03_00_QMD_RESERVED_D = (335, 328) +NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336) +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID = (357, 352) +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358) +NVC6C0_QMDV03_00_QMD_RESERVED11A = (366, 366) +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367) +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE = (369, 368) +NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 +NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 +NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS = (370, 370) +NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 +NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371) +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_QMD_RESERVED11B = (377, 372) +NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT = (378, 378) +NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 +NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 +NVC6C0_QMDV03_00_QMD_RESERVED11C = (381, 379) +NVC6C0_QMDV03_00_SAMPLER_INDEX = (382, 382) +NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 +NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 +NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE = (383, 383) +NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_CTA_RASTER_WIDTH = (415, 384) +NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT = (431, 416) +NVC6C0_QMDV03_00_CTA_RASTER_DEPTH = (463, 448) +NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER = (511, 480) +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE = (512, 512) +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION = (515, 513) +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH = (516, 516) +NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 +NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE = (517, 517) +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION = (520, 518) +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH = (521, 521) +NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 +NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 +NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD = (529, 522) +NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530) +NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE = (561, 544) +NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (567, 562) +NVC6C0_QMDV03_00_QMD_RESERVED17A = (568, 568) +NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (574, 569) +NVC6C0_QMDV03_00_QMD_RESERVED17B = (575, 575) +NVC6C0_QMDV03_00_QMD_VERSION = (579, 576) +NVC6C0_QMDV03_00_QMD_MAJOR_VERSION = (583, 580) +NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 = (607, 592) +NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 = (623, 608) +NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 = (639, 624) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1)) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 +NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 +NVC6C0_QMDV03_00_REGISTER_COUNT_V = (656, 648) +NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (662, 657) +NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE = (663, 663) +NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM = (671, 664) +NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER = (703, 672) +NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER = (735, 704) +NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE = (759, 736) +NVC6C0_QMDV03_00_BARRIER_COUNT = (767, 763) +NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER = (799, 768) +NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER = (807, 800) +NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A = (818, 808) +NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE = (819, 819) +NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP = (822, 820) +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV03_00_RELEASE0_ENABLE = (823, 823) +NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT = (825, 824) +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE = (826, 826) +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE = (828, 827) +NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 +NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B = (829, 829) +NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE = (831, 830) +NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 +NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 +NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER = (863, 832) +NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER = (895, 864) +NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER = (927, 896) +NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER = (935, 928) +NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A = (946, 936) +NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE = (947, 947) +NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP = (950, 948) +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV03_00_RELEASE1_ENABLE = (951, 951) +NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT = (953, 952) +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE = (954, 954) +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE = (956, 955) +NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 +NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B = (957, 957) +NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE = (959, 958) +NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 +NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 +NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER = (991, 960) +NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER = (1023, 992) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64)) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64)) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64)) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000 +NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001 +NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64)) +NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64)) +NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER = (1567, 1536) +NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER = (1584, 1568) +NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE = (1623, 1600) +NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1640, 1632) +NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE = (1649, 1641) +NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE = (1651, 1650) +NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 +NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 +NVC6C0_QMDV03_00_SASS_VERSION = (1663, 1656) +NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER = (1695, 1664) +NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER = (1703, 1696) +NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A = (1714, 1704) +NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE = (1715, 1715) +NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP = (1718, 1716) +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_QMDV03_00_RELEASE2_ENABLE = (1719, 1719) +NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT = (1721, 1720) +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE = (1722, 1722) +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE = (1724, 1723) +NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002 +NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B = (1725, 1725) +NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE = (1727, 1726) +NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 +NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 +NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 +NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER = (1759, 1728) +NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER = (1791, 1760) +NVC6C0_QMDV03_00_QMD_SPARE_I = (1823, 1792) +NVC6C0_QMDV03_00_HW_ONLY_INNER_GET = (1854, 1824) +NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1855, 1855) +NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT = (1886, 1856) +NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1917, 1888) +NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1919, 1919) +NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 +NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 +NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (1951, 1920) +NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER = (1958, 1952) +NVC6C0_QMDV03_00_DEBUG_ID_UPPER = (2015, 1984) +NVC6C0_QMDV03_00_DEBUG_ID_LOWER = (2047, 2016) +NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0) +NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30) +NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31) +NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32) +NVCEC0_QMDV05_00_INNER_GET = (94, 64) +NVCEC0_QMDV05_00_INNER_OVERFLOW = (95, 95) +NVCEC0_QMDV05_00_INNER_PUT = (126, 96) +NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW = (127, 127) +NVCEC0_QMDV05_00_DEPENDENCE_COUNTER = (143, 128) +NVCEC0_QMDV05_00_QMD_GROUP_ID = (149, 144) +NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150) +NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 +NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 +NVCEC0_QMDV05_00_QMD_TYPE = (153, 151) +NVCEC0_QMDV05_00_QMD_TYPE_QUEUE = 0x00000000 +NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL = 0x00000001 +NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA = 0x00000002 +NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA = 0x00000003 +NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA = 0x00000004 +NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 +NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK = (157, 154) +NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS = (158, 158) +NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 +NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 +NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID = (159, 159) +NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE = (184, 160) +NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER = (207, 192) +NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID = (210, 208) +NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK = (218, 211) +NVCEC0_QMDV05_00_GRID_WIDTH_RESUME = (255, 224) +NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME = (271, 256) +NVCEC0_QMDV05_00_GRID_DEPTH_RESUME = (287, 272) +NVCEC0_QMDV05_00_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16)) +NVCEC0_QMDV05_00_RELEASE0_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(0) +NVCEC0_QMDV05_00_RELEASE1_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(1) +NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 +NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 +NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 +NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16)) +NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE = 0x00000000 +NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16)) +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE = (336, 336) +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION = (339, 337) +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH = (340, 340) +NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION = (341, 341) +NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 +NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST = (342, 342) +NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE = (343, 343) +NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE = (344, 344) +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION = (347, 345) +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH = (348, 348) +NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL = (349, 349) +NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 +NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350) +NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE = (351, 351) +NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CORRELATION_ID = (383, 352) +NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER = (415, 384) +NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER = (447, 416) +NVCEC0_QMDV05_00_SASS_VERSION = (455, 448) +NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT = (456, 456) +NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 +NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 +NVCEC0_QMDV05_00_SAMPLER_INDEX = (457, 457) +NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 +NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 +NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458) +NVCEC0_QMDV05_00_QMD_MINOR_VERSION = (467, 464) +NVCEC0_QMDV05_00_QMD_MAJOR_VERSION = (471, 468) +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472) +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473) +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474) +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE = (475, 475) +NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE = (476, 476) +NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477) +NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478) +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479) +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576) +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608) +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID = (621, 616) +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622) +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623) +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE = (625, 624) +NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 +NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 +NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626) +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE = (627, 627) +NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM = (635, 628) +NVCEC0_QMDV05_00_SYNC_DOMAIN_ID = (637, 636) +NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638) +NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 +NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 +NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT = (639, 639) +NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 +NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 +NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID = (671, 640) +NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID = (703, 672) +NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714) +NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM = (729, 722) +NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID = (730, 730) +NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID = (731, 731) +NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732) +NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733) +NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734) +NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735) +NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP = (743, 736) +NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP = (751, 744) +NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER = (759, 752) +NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER = (767, 760) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960) +NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992) +NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 = (1055, 1024) +NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 = (1076, 1056) +NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE = (1085, 1077) +NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE = (1087, 1086) +NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 +NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 +NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 = (1103, 1088) +NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 = (1119, 1104) +NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 = (1127, 1120) +NVCEC0_QMDV05_00_REGISTER_COUNT = (1136, 1128) +NVCEC0_QMDV05_00_BARRIER_COUNT = (1141, 1137) +NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE = (1147, 1142) +NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 = (1162, 1152) +NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (1168, 1163) +NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (1174, 1169) +NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (1180, 1175) +NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE = (1181, 1181) +NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = (1199, 1184) +NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = (1215, 1200) +NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT = (1223, 1216) +NVCEC0_QMDV05_00_GRID_WIDTH = (1279, 1248) +NVCEC0_QMDV05_00_GRID_HEIGHT = (1295, 1280) +NVCEC0_QMDV05_00_GRID_DEPTH = (1327, 1312) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1375+(i)*64), (1344+(i)*64)) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1394+(i)*64), (1376+(i)*64)) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1407+(i)*64), (1395+(i)*64)) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID = lambda i: ((1856+(i)*4), (1856+(i)*4)) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH = lambda i: ((1858+(i)*4), (1857+(i)*4)) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 +NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 +NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 +NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1859+(i)*4), (1859+(i)*4)) +NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1919, 1888) +NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1936, 1920) +NVCEC0_QMDV05_00_GPC_CGA_WIDTH = (2053, 2048) +NVCEC0_QMDV05_00_GPC_CGA_HEIGHT = (2061, 2056) +NVCEC0_QMDV05_00_GPC_CGA_DEPTH = (2069, 2064) +NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2075, 2072) +NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2079, 2076) +NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE = (2111, 2111) +NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 +NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 +NVCEC0_QMDV05_00_GPU_CGA_WIDTH = (2127, 2112) +NVCEC0_QMDV05_00_GPU_CGA_HEIGHT = (2143, 2128) +NVCEC0_QMDV05_00_GPU_CGA_DEPTH = (2159, 2144) +NVCEC0_QMDV05_00_DEBUG_ID_LOWER = (2207, 2176) +NVCEC0_QMDV05_00_DEBUG_ID_UPPER = (2239, 2208) +NVCEC0_QMDV05_00_TPC_DISABLE_MASK = lambda i: ((2271+(i)*32), (2240+(i)*32)) +NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2527, 2496) +NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2543, 2528) +NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2559, 2544) +NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2563, 2560) +NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2567, 2564) +NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (2596, 2592) +NVCEC0_QMDV05_00_HW_ONLY_INNER_GET = (2654, 2624) +NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT = (2686, 2656) +NVCEC0_QMDV05_00_OUTER_PUT = (3038, 3008) +NVCEC0_QMDV05_00_OUTER_OVERFLOW = (3039, 3039) +NVCEC0_QMDV05_00_OUTER_GET = (3070, 3040) +NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW = (3071, 3071) +NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8)) +NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8)) +NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8)) +NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32)) +NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0) +NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30) +NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31) +NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32) +NVCEC0_QMDV05_01_INNER_GET = (94, 64) +NVCEC0_QMDV05_01_INNER_OVERFLOW = (95, 95) +NVCEC0_QMDV05_01_INNER_PUT = (126, 96) +NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW = (127, 127) +NVCEC0_QMDV05_01_DEPENDENCE_COUNTER = (143, 128) +NVCEC0_QMDV05_01_QMD_GROUP_ID = (149, 144) +NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150) +NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 +NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 +NVCEC0_QMDV05_01_QMD_TYPE = (153, 151) +NVCEC0_QMDV05_01_QMD_TYPE_QUEUE = 0x00000000 +NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL = 0x00000001 +NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA = 0x00000002 +NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 +NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 +NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 +NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK = (157, 154) +NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS = (158, 158) +NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 +NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 +NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID = (159, 159) +NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE = (184, 160) +NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER = (207, 192) +NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID = (210, 208) +NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK = (218, 211) +NVCEC0_QMDV05_01_GRID_WIDTH_RESUME = (255, 224) +NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME = (271, 256) +NVCEC0_QMDV05_01_GRID_DEPTH_RESUME = (287, 272) +NVCEC0_QMDV05_01_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 +NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 +NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 +NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16)) +NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 +NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16)) +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE = (336, 336) +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION = (339, 337) +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH = (340, 340) +NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION = (341, 341) +NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST = (342, 342) +NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE = (343, 343) +NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE = (344, 344) +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION = (347, 345) +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH = (348, 348) +NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL = (349, 349) +NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 +NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350) +NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE = (351, 351) +NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CORRELATION_ID = (383, 352) +NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER = (415, 384) +NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER = (447, 416) +NVCEC0_QMDV05_01_SASS_VERSION = (455, 448) +NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT = (456, 456) +NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 +NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 +NVCEC0_QMDV05_01_SAMPLER_INDEX = (457, 457) +NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 +NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 +NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458) +NVCEC0_QMDV05_01_QMD_MINOR_VERSION = (467, 464) +NVCEC0_QMDV05_01_QMD_MAJOR_VERSION = (471, 468) +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472) +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473) +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474) +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE = (475, 475) +NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE = (476, 476) +NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477) +NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478) +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479) +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480) +NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512) +NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544) +NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576) +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608) +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID = (621, 616) +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622) +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623) +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE = (625, 624) +NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 +NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 +NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626) +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE = (627, 627) +NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM = (635, 628) +NVCEC0_QMDV05_01_SYNC_DOMAIN_ID = (637, 636) +NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638) +NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 +NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 +NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT = (639, 639) +NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 +NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 +NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID = (671, 640) +NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID = (703, 672) +NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714) +NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM = (729, 722) +NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID = (730, 730) +NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID = (731, 731) +NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732) +NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733) +NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734) +NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735) +NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP = (743, 736) +NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP = (751, 744) +NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER = (759, 752) +NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER = (767, 760) +NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4 = lambda i: ((799+(i)*416), (768+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4 = lambda i: ((820+(i)*416), (800+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE = lambda i: ((829+(i)*416), (821+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE = lambda i: ((831+(i)*416), (830+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0 = lambda i: ((847+(i)*416), (832+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1 = lambda i: ((863+(i)*416), (848+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2 = lambda i: ((871+(i)*416), (864+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT = lambda i: ((880+(i)*416), (872+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT = lambda i: ((885+(i)*416), (881+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID = lambda i: ((886+(i)*416), (886+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH = lambda i: ((888+(i)*416), (887+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST = 0x00000002 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE = lambda i: ((889+(i)*416), (889+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE = lambda i: ((895+(i)*416), (890+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7 = lambda i: ((906+(i)*416), (896+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((912+(i)*416), (907+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((918+(i)*416), (913+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((924+(i)*416), (919+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE = lambda i: ((925+(i)*416), (925+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = lambda i: ((943+(i)*416), (928+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = lambda i: ((959+(i)*416), (944+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6 = lambda i: ((991+(i)*416), (960+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6 = lambda i: ((1010+(i)*416), (992+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4 = lambda i: ((1023+(i)*416), (1011+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6 = lambda i: ((1055+(i)*416), (1024+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6 = lambda i: ((1074+(i)*416), (1056+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4 = lambda i: ((1087+(i)*416), (1075+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID = lambda i: ((1088+(i)*416), (1088+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH = lambda i: ((1090+(i)*416), (1089+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST = 0x00000002 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE = lambda i: ((1091+(i)*416), (1091+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT = lambda i: ((1099+(i)*416), (1092+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH = lambda i: ((1151+(i)*416), (1120+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT = lambda i: ((1167+(i)*416), (1152+(i)*416)) +NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH = lambda i: ((1183+(i)*416), (1168+(i)*416)) +NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8)) +NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8)) +NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8)) +NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID = lambda i,j: ((886+(i)*416+(j)*202), (886+(i)*416+(j)*202)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH = lambda i,j: ((888+(i)*416+(j)*202), (887+(i)*416+(j)*202)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST = 0x00000002 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE = lambda i,j: ((889+(i)*416+(j)*202), (889+(i)*416+(j)*202)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6 = lambda i,j: ((991+(i)*416+(j)*64), (960+(i)*416+(j)*64)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6 = lambda i,j: ((1010+(i)*416+(j)*64), (992+(i)*416+(j)*64)) +NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4 = lambda i,j: ((1023+(i)*416+(j)*64), (1011+(i)*416+(j)*64)) +NVCEC0_QMDV04_01_DEPENDENCE_COUNTER = (15, 0) +NVCEC0_QMDV04_01_QMD_GROUP_ID = (21, 16) +NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (22, 22) +NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000 +NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001 +NVCEC0_QMDV04_01_QMD_TYPE = (25, 23) +NVCEC0_QMDV04_01_QMD_TYPE_QUEUE = 0x00000000 +NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL = 0x00000001 +NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA = 0x00000002 +NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003 +NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004 +NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005 +NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID = (28, 28) +NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID = (29, 29) +NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS = (30, 30) +NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000 +NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001 +NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID = (31, 31) +NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000 +NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE = (56, 32) +NVCEC0_QMDV04_01_INNER_GET = (94, 64) +NVCEC0_QMDV04_01_INNER_OVERFLOW = (95, 95) +NVCEC0_QMDV04_01_INNER_PUT = (126, 96) +NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW = (127, 127) +NVCEC0_QMDV04_01_HW_ONLY_INNER_GET = (190, 160) +NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT = (222, 192) +NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (253, 224) +NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (254, 254) +NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000 +NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001 +NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (287, 256) +NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER = (303, 288) +NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (304, 304) +NVCEC0_QMDV04_01_RELEASE_ENABLE = lambda i: ((320+(i)*16), (320+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE = lambda i: ((322+(i)*16), (321+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002 +NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE = lambda i: ((323+(i)*16), (323+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE = lambda i: ((324+(i)*16), (324+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP = lambda i: ((327+(i)*16), (325+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT = lambda i: ((329+(i)*16), (328+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE = lambda i: ((331+(i)*16), (330+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002 +NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003 +NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B = lambda i: ((332+(i)*16), (332+(i)*16)) +NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000 +NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO = lambda i: ((335+(i)*16), (333+(i)*16)) +NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE = lambda i: ((368+(i)*5), (368+(i)*5)) +NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION = lambda i: ((371+(i)*5), (369+(i)*5)) +NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000 +NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001 +NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004 +NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH = lambda i: ((372+(i)*5), (372+(i)*5)) +NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000 +NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001 +NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION = (378, 378) +NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000 +NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001 +NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST = (379, 379) +NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000 +NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001 +NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE = (380, 380) +NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL = (381, 381) +NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000 +NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (382, 382) +NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CORRELATION_ID = (415, 384) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID = lambda i: ((416+(i)*4), (416+(i)*4)) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE = 0x00000000 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH = lambda i: ((418+(i)*4), (417+(i)*4)) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE = lambda i: ((419+(i)*4), (419+(i)*4)) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER = (479, 448) +NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER = (511, 480) +NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE = (535, 512) +NVCEC0_QMDV04_01_SASS_VERSION = (543, 536) +NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE = (567, 544) +NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT = (568, 568) +NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000 +NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001 +NVCEC0_QMDV04_01_SAMPLER_INDEX = (569, 569) +NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000 +NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001 +NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (575, 570) +NVCEC0_QMDV04_01_QMD_MINOR_VERSION = (579, 576) +NVCEC0_QMDV04_01_QMD_MAJOR_VERSION = (583, 580) +NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE = (601, 584) +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE = (602, 602) +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (603, 603) +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE = (604, 604) +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE = (605, 605) +NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE = (606, 606) +NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE = (607, 607) +NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE = (613, 608) +NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE = (619, 614) +NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (625, 620) +NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE = (626, 626) +NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (671, 640) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (696, 672) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (735, 704) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (767, 736) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960) +NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992) +NVCEC0_QMDV04_01_GRID_WIDTH = (1055, 1024) +NVCEC0_QMDV04_01_GRID_HEIGHT = (1071, 1056) +NVCEC0_QMDV04_01_GRID_DEPTH = (1103, 1088) +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (1127, 1120) +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID = (1133, 1128) +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (1134, 1134) +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (1135, 1135) +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE = (1137, 1136) +NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000 +NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001 +NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003 +NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS = (1138, 1138) +NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000 +NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE = (1139, 1139) +NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM = (1147, 1140) +NVCEC0_QMDV04_01_SYNC_DOMAIN_ID = (1149, 1148) +NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (1150, 1150) +NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000 +NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001 +NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT = (1151, 1151) +NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000 +NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001 +NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 = (1167, 1152) +NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 = (1183, 1168) +NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 = (1191, 1184) +NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT = (1199, 1192) +NVCEC0_QMDV04_01_REGISTER_COUNT = (1208, 1200) +NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE = (1210, 1210) +NVCEC0_QMDV04_01_BARRIER_COUNT = (1215, 1211) +NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER = (1247, 1216) +NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER = (1272, 1248) +NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP = (1287, 1280) +NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP = (1295, 1288) +NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER = (1303, 1296) +NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER = (1311, 1304) +NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (1319, 1312) +NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM = (1327, 1320) +NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE = (1333, 1328) +NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1375, 1344) +NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1392, 1376) +NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE = (1401, 1393) +NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE = (1403, 1402) +NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000 +NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001 +NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (1406, 1406) +NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (1407, 1407) +NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000 +NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001 +NVCEC0_QMDV04_01_GRID_WIDTH_RESUME = (1439, 1408) +NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME = (1455, 1440) +NVCEC0_QMDV04_01_GRID_DEPTH_RESUME = (1471, 1456) +NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID = (1503, 1472) +NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID = (1535, 1504) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1567+(i)*64), (1536+(i)*64)) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1586+(i)*64), (1568+(i)*64)) +NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1599+(i)*64), (1587+(i)*64)) +NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD = (2135, 2128) +NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 = (2140, 2136) +NVCEC0_QMDV04_01_GPC_CGA_WIDTH = (2149, 2144) +NVCEC0_QMDV04_01_GPC_CGA_HEIGHT = (2157, 2152) +NVCEC0_QMDV04_01_GPC_CGA_DEPTH = (2165, 2160) +NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2171, 2168) +NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2175, 2172) +NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE = (2207, 2207) +NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000 +NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001 +NVCEC0_QMDV04_01_GPU_CGA_WIDTH = (2223, 2208) +NVCEC0_QMDV04_01_GPU_CGA_HEIGHT = (2239, 2224) +NVCEC0_QMDV04_01_GPU_CGA_DEPTH = (2255, 2240) +NVCEC0_QMDV04_01_DEBUG_ID_LOWER = (2399, 2368) +NVCEC0_QMDV04_01_DEBUG_ID_UPPER = (2431, 2400) +NVCEC0_QMDV04_01_TPC_DISABLE_MASK = lambda i: ((2463+(i)*32), (2432+(i)*32)) +NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2591, 2560) +NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2607, 2592) +NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2623, 2608) +NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2627, 2624) +NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2631, 2628) +NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER = lambda i: ((2719+(i)*32), (2688+(i)*32)) +NVCEC0_QMDV04_01_OUTER_PUT = (3038, 3008) +NVCEC0_QMDV04_01_OUTER_OVERFLOW = (3039, 3039) +NVCEC0_QMDV04_01_OUTER_GET = (3070, 3040) +NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW = (3071, 3071) +NVBIT = lambda b: (1<<(b)) +NVBIT32 = lambda b: NVBIT_TYPE(b, NvU32) +NVBIT64 = lambda b: NVBIT_TYPE(b, NvU64) +NV_BITMASK32_IDX = lambda chId: (((chId) & ~(0x1F)) >> 5) +NV_BITMASK32_OFFSET = lambda chId: ((chId) & (0x1F)) +NV_BITMASK32_GET = lambda pChannelMask,chId: ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId))) +DRF_SHIFT = lambda drf: ((DRF_ISBIT(0,drf)) % 32) +DRF_SHIFT_RT = lambda drf: ((DRF_ISBIT(1,drf)) % 32) +DRF_SIZE = lambda drf: (DRF_EXTENT(drf)-DRF_BASE(drf)+1) +DRF_MASK = lambda drf: (0xFFFFFFFF>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) +DRF_SHIFTMASK = lambda drf: (DRF_MASK(drf)<<(DRF_SHIFT(drf))) +DRF_SHIFT64 = lambda drf: ((DRF_ISBIT(0,drf)) % 64) +DRF_MASK64 = lambda drf: (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64))) +DRF_SHIFTMASK64 = lambda drf: (DRF_MASK64(drf)<<(DRF_SHIFT64(drf))) +FLD_TEST_DRF_NUM64 = lambda d,r,f,n,v: (DRF_VAL64(d, r, f, (v)) == (n)) +REF_VAL64 = lambda drf,v: (((NvU64)(v)>>DRF_SHIFT64(drf))&DRF_MASK64(drf)) +REF_NUM64 = lambda drf,n: (((NvU64)(n)&DRF_MASK64(drf))<>DRF_SHIFT(drf))&DRF_MASK(drf)) +REF_NUM = lambda drf,n: (((n)&DRF_MASK(drf))<>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32)) +DRF_SHIFTMASK_MW = lambda drf: ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf))) +DRF_SIZE_MW = lambda drf: (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1) +DRF_WORD_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)/32) +DRF_WORD_MW_HIGH = lambda drf: (DRF_PICK_MW(drf,1)/32) +DRF_MASK_MW_LOW = lambda drf: (0xFFFFFFFF) +DRF_MASK_MW_HIGH = lambda drf: (0xFFFFFFFF>>(31-(DRF_EXTENT_MW(drf)))) +DRF_SHIFT_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)%32) +DRF_SHIFT_MW_HIGH = lambda drf: (0) +DRF_MERGE_SHIFT = lambda drf: ((32-((DRF_PICK_MW(drf,0)%32)))%32) +FLD_MERGE_MW = lambda drf,n,v: (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n) +FLD_IDX_MERGE_MW = lambda drf,i,n,v: (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n) +FLD_TEST_DRF_NUM_MW = lambda d,r,f,n,v: ((DRF_VAL_MW(d, r, f, (v)) == n)) +NV_TWO_N_MINUS_ONE = lambda n: (((1<<(n/2))<<((n+1)/2))-1) +LOWESTBIT = lambda x: ( (x) & (((x) - 1) ^ (x)) ) +NV_ANYSIZE_ARRAY = 1 +NV_CEIL = lambda a,b: (((a)+(b)-1)/(b)) +NV_DIV_AND_CEIL = lambda a,b: NV_CEIL(a,b) +NV_SIGN = lambda s: ((NvS8)(((s) > 0) - ((s) < 0))) +NV_ZERO_SIGN = lambda s: ((NvS8)((((s) >= 0) * 2) - 1)) +NV_UNSIGNED_ROUNDED_DIV = lambda a,b: (((a) + ((b) / 2)) / (b)) +NV_UNSIGNED_DIV_CEIL = lambda a,b: (((a) + (b - 1)) / (b)) +NV_ALIGN_DOWN = lambda v,gran: ((v) & ~((v) - (v) + (gran) - 1)) +NV_ALIGN_UP = lambda v,gran: (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1)) +NV_IS_ALIGNED = lambda v,gran: (0 == ((v) & ((gran) - 1))) +NV_BIT_GET = lambda k,x: (((x) >> (k)) & 1) +NV_ARRAY_ELEMENTS = lambda x: ((sizeof(x)/sizeof((x)[0]))) +BIT = lambda b: (1<<(b)) +NV01_NULL_OBJECT = (0x0) +NV1_NULL_OBJECT = NV01_NULL_OBJECT +NV01_ROOT = (0x0) +NV0000_ALLOC_PARAMETERS_MESSAGE_ID = (0x0000) +NV01_DEVICE_0 = (0x80) +NV0080_ALLOC_PARAMETERS_MESSAGE_ID = (0x0080) +NV20_SUBDEVICE_0 = (0x2080) +NV2080_ALLOC_PARAMETERS_MESSAGE_ID = (0x2080) +NV2080_NOTIFIERS_SW = (0) +NV2080_NOTIFIERS_HOTPLUG = (1) +NV2080_NOTIFIERS_POWER_CONNECTOR = (2) +NV2080_NOTIFIERS_THERMAL_SW = (3) +NV2080_NOTIFIERS_THERMAL_HW = (4) +NV2080_NOTIFIERS_FULL_SCREEN_CHANGE = (5) +NV2080_NOTIFIERS_EVENTBUFFER = (6) +NV2080_NOTIFIERS_DP_IRQ = (7) +NV2080_NOTIFIERS_GR_DEBUG_INTR = (8) +NV2080_NOTIFIERS_PMU_EVENT = (9) +NV2080_NOTIFIERS_PMU_COMMAND = (10) +NV2080_NOTIFIERS_TIMER = (11) +NV2080_NOTIFIERS_GRAPHICS = (12) +NV2080_NOTIFIERS_PPP = (13) +NV2080_NOTIFIERS_VLD = (14) +NV2080_NOTIFIERS_NVDEC0 = NV2080_NOTIFIERS_VLD +NV2080_NOTIFIERS_NVDEC1 = (15) +NV2080_NOTIFIERS_NVDEC2 = (16) +NV2080_NOTIFIERS_NVDEC3 = (17) +NV2080_NOTIFIERS_NVDEC4 = (18) +NV2080_NOTIFIERS_NVDEC5 = (19) +NV2080_NOTIFIERS_NVDEC6 = (20) +NV2080_NOTIFIERS_NVDEC7 = (21) +NV2080_NOTIFIERS_PDEC = (22) +NV2080_NOTIFIERS_CE0 = (23) +NV2080_NOTIFIERS_CE1 = (24) +NV2080_NOTIFIERS_CE2 = (25) +NV2080_NOTIFIERS_CE3 = (26) +NV2080_NOTIFIERS_CE4 = (27) +NV2080_NOTIFIERS_CE5 = (28) +NV2080_NOTIFIERS_CE6 = (29) +NV2080_NOTIFIERS_CE7 = (30) +NV2080_NOTIFIERS_CE8 = (31) +NV2080_NOTIFIERS_CE9 = (32) +NV2080_NOTIFIERS_PSTATE_CHANGE = (33) +NV2080_NOTIFIERS_HDCP_STATUS_CHANGE = (34) +NV2080_NOTIFIERS_FIFO_EVENT_MTHD = (35) +NV2080_NOTIFIERS_PRIV_RING_HANG = (36) +NV2080_NOTIFIERS_RC_ERROR = (37) +NV2080_NOTIFIERS_MSENC = (38) +NV2080_NOTIFIERS_NVENC0 = NV2080_NOTIFIERS_MSENC +NV2080_NOTIFIERS_NVENC1 = (39) +NV2080_NOTIFIERS_NVENC2 = (40) +NV2080_NOTIFIERS_UNUSED_0 = (41) +NV2080_NOTIFIERS_ACPI_NOTIFY = (42) +NV2080_NOTIFIERS_COOLER_DIAG_ZONE = (43) +NV2080_NOTIFIERS_THERMAL_DIAG_ZONE = (44) +NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST = (45) +NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE = (46) +NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT = (47) +NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT = (48) +NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT = (49) +NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT = (50) +NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT = (51) +NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT = (52) +NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT = (53) +NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT = (54) +NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT = (55) +NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT = (56) +NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT = (57) +NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT = (58) +NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT = (59) +NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT = (60) +NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT = (61) +NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT = (62) +NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT = (63) +NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT = (64) +NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT = (65) +NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT = (66) +NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT = (67) +NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT = (68) +NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT = (69) +NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT = (70) +NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT = (71) +NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT = (72) +NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT = (73) +NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT = (74) +NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT = (75) +NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT = (76) +NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT = (77) +NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT = (78) +NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT = (79) +NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT = (80) +NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT = (81) +NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT = (82) +NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT = (83) +NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT = (84) +NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT = (85) +NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT = (86) +NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT = (87) +NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT = (88) +NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT = (89) +NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT = (90) +NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT = (91) +NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT = (92) +NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT = (93) +NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT = (94) +NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT = (95) +NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT = (96) +NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT = (97) +NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT = (98) +NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT = (99) +NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT = (100) +NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT = (101) +NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT = (102) +NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT = (103) +NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT = (104) +NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT = (105) +NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT = (106) +NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT = (107) +NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT = (108) +NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT = (109) +NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT = (110) +NV2080_NOTIFIERS_ECC_SBE = (111) +NV2080_NOTIFIERS_ECC_DBE = (112) +NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION = (113) +NV2080_NOTIFIERS_GC5_GPU_READY = (114) +NV2080_NOTIFIERS_SEC2 = (115) +NV2080_NOTIFIERS_GC6_REFCOUNT_INC = (116) +NV2080_NOTIFIERS_GC6_REFCOUNT_DEC = (117) +NV2080_NOTIFIERS_POWER_EVENT = (118) +NV2080_NOTIFIERS_CLOCKS_CHANGE = (119) +NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE = (120) +NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT = (121) +NV2080_NOTIFIERS_RESERVED122 = (122) +NV2080_NOTIFIERS_NVLINK_ERROR_FATAL = (123) +NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT = (124) +NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED = (125) +NV2080_NOTIFIERS_NVJPG = (126) +NV2080_NOTIFIERS_NVJPEG0 = NV2080_NOTIFIERS_NVJPG +NV2080_NOTIFIERS_NVJPEG1 = (127) +NV2080_NOTIFIERS_NVJPEG2 = (128) +NV2080_NOTIFIERS_NVJPEG3 = (129) +NV2080_NOTIFIERS_NVJPEG4 = (130) +NV2080_NOTIFIERS_NVJPEG5 = (131) +NV2080_NOTIFIERS_NVJPEG6 = (132) +NV2080_NOTIFIERS_NVJPEG7 = (133) +NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE = (134) +NV2080_NOTIFIERS_RUNLIST_ACQUIRE = (135) +NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE = (136) +NV2080_NOTIFIERS_RUNLIST_IDLE = (137) +NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE = (138) +NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE = (139) +NV2080_NOTIFIERS_CTXSW_TIMEOUT = (140) +NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED = (141) +NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT = (142) +NV2080_NOTIFIERS_DSTATE_XUSB_PPC = (143) +NV2080_NOTIFIERS_FECS_CTX_SWITCH = (144) +NV2080_NOTIFIERS_XUSB_PPC_CONNECTED = (145) +NV2080_NOTIFIERS_GR0 = NV2080_NOTIFIERS_GRAPHICS +NV2080_NOTIFIERS_GR1 = (146) +NV2080_NOTIFIERS_GR2 = (147) +NV2080_NOTIFIERS_GR3 = (148) +NV2080_NOTIFIERS_GR4 = (149) +NV2080_NOTIFIERS_GR5 = (150) +NV2080_NOTIFIERS_GR6 = (151) +NV2080_NOTIFIERS_GR7 = (152) +NV2080_NOTIFIERS_OFA = (153) +NV2080_NOTIFIERS_OFA0 = NV2080_NOTIFIERS_OFA +NV2080_NOTIFIERS_DSTATE_HDA = (154) +NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL = (155) +NV2080_NOTIFIERS_POISON_ERROR_FATAL = (156) +NV2080_NOTIFIERS_UCODE_RESET = (157) +NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE = (158) +NV2080_NOTIFIERS_SMC_CONFIG_UPDATE = (159) +NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED = (160) +NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED = (161) +NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST = (162) +NV2080_NOTIFIERS_SEC_FAULT_ERROR = (163) +NV2080_NOTIFIERS_UNUSED_1 = (164) +NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP = (165) +NV2080_NOTIFIERS_CE10 = (166) +NV2080_NOTIFIERS_CE11 = (167) +NV2080_NOTIFIERS_CE12 = (168) +NV2080_NOTIFIERS_CE13 = (169) +NV2080_NOTIFIERS_CE14 = (170) +NV2080_NOTIFIERS_CE15 = (171) +NV2080_NOTIFIERS_CE16 = (172) +NV2080_NOTIFIERS_CE17 = (173) +NV2080_NOTIFIERS_CE18 = (174) +NV2080_NOTIFIERS_CE19 = (175) +NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN = (176) +NV2080_NOTIFIERS_NVPCF_EVENTS = (177) +NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST = (178) +NV2080_NOTIFIERS_VRR_SET_TIMEOUT = (179) +NV2080_NOTIFIERS_OFA1 = (180) +NV2080_NOTIFIERS_AUX_POWER_EVENT = (181) +NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE = (182) +NV2080_NOTIFIERS_NVENC3 = (183) +NV2080_NOTIFIERS_GSP_PERF_TRACE = (184) +NV2080_NOTIFIERS_INBAND_RESPONSE = (185) +NV2080_NOTIFIERS_RESERVED_186 = (186) +NV2080_NOTIFIERS_ECC_SBE_STORM = (187) +NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT = (188) +NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE = (189) +NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR = (190) +NV2080_NOTIFIERS_GPU_UNAVAILABLE = (191) +NV2080_NOTIFIERS_GPU_RECOVERY_ACTION = (192) +NV2080_NOTIFIERS_POWER_SUSPEND = (193) +NV2080_NOTIFIERS_POWER_RESUME = (194) +NV2080_NOTIFIERS_CTXSW_UCODE_ERROR = (195) +NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD = (196) +NV2080_NOTIFIERS_MAXCOUNT = (197) +NV2080_NOTIFIERS_GR_IDX = lambda x: ((x) - NV2080_NOTIFIERS_GR0) +NV2080_NOTIFIER_TYPE_IS_GR = lambda x: (((x) == NV2080_NOTIFIERS_GR0) or (((x) >= NV2080_NOTIFIERS_GR1) and ((x) <= NV2080_NOTIFIERS_GR7))) +NV2080_NOTIFIER_TYPE_IS_CE = lambda x: ((((x) >= NV2080_NOTIFIERS_CE0) and ((x) <= NV2080_NOTIFIERS_CE9)) or (((x) >= NV2080_NOTIFIERS_CE10) and ((x) <= NV2080_NOTIFIERS_CE19))) +NV2080_NOTIFIER_TYPE_IS_NVENC = lambda x: ((((x) >= NV2080_NOTIFIERS_NVENC0) and ((x) <= NV2080_NOTIFIERS_NVENC2)) or (((x) == NV2080_NOTIFIERS_NVENC3))) +NV2080_NOTIFIERS_NVDEC = lambda x: (NV2080_NOTIFIERS_NVDEC0 + (x)) +NV2080_NOTIFIERS_NVDEC_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVDEC0) +NV2080_NOTIFIER_TYPE_IS_NVDEC = lambda x: (((x) >= NV2080_NOTIFIERS_NVDEC0) and ((x) <= NV2080_NOTIFIERS_NVDEC7)) +NV2080_NOTIFIERS_NVJPEG = lambda x: (NV2080_NOTIFIERS_NVJPEG0 + (x)) +NV2080_NOTIFIERS_NVJPEG_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVJPEG0) +NV2080_NOTIFIER_TYPE_IS_NVJPEG = lambda x: (((x) >= NV2080_NOTIFIERS_NVJPEG0) and ((x) <= NV2080_NOTIFIERS_NVJPEG7)) +NV2080_NOTIFIER_TYPE_IS_OFA = lambda x: (((x) == NV2080_NOTIFIERS_OFA0) or ((x) == NV2080_NOTIFIERS_OFA1)) +NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) +NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) +NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS = (0x8000) +NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT = (0x4000) +NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE = (0x2000) +NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE = (0x1000) +NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS = (0x0000) +NV2080_ENGINE_TYPE_NULL = (0x00000000) +NV2080_ENGINE_TYPE_GRAPHICS = (0x00000001) +NV2080_ENGINE_TYPE_GR0 = NV2080_ENGINE_TYPE_GRAPHICS +NV2080_ENGINE_TYPE_GR1 = (0x00000002) +NV2080_ENGINE_TYPE_GR2 = (0x00000003) +NV2080_ENGINE_TYPE_GR3 = (0x00000004) +NV2080_ENGINE_TYPE_GR4 = (0x00000005) +NV2080_ENGINE_TYPE_GR5 = (0x00000006) +NV2080_ENGINE_TYPE_GR6 = (0x00000007) +NV2080_ENGINE_TYPE_GR7 = (0x00000008) +NV2080_ENGINE_TYPE_COPY0 = (0x00000009) +NV2080_ENGINE_TYPE_COPY1 = (0x0000000a) +NV2080_ENGINE_TYPE_COPY2 = (0x0000000b) +NV2080_ENGINE_TYPE_COPY3 = (0x0000000c) +NV2080_ENGINE_TYPE_COPY4 = (0x0000000d) +NV2080_ENGINE_TYPE_COPY5 = (0x0000000e) +NV2080_ENGINE_TYPE_COPY6 = (0x0000000f) +NV2080_ENGINE_TYPE_COPY7 = (0x00000010) +NV2080_ENGINE_TYPE_COPY8 = (0x00000011) +NV2080_ENGINE_TYPE_COPY9 = (0x00000012) +NV2080_ENGINE_TYPE_BSP = (0x00000013) +NV2080_ENGINE_TYPE_NVDEC0 = NV2080_ENGINE_TYPE_BSP +NV2080_ENGINE_TYPE_NVDEC1 = (0x00000014) +NV2080_ENGINE_TYPE_NVDEC2 = (0x00000015) +NV2080_ENGINE_TYPE_NVDEC3 = (0x00000016) +NV2080_ENGINE_TYPE_NVDEC4 = (0x00000017) +NV2080_ENGINE_TYPE_NVDEC5 = (0x00000018) +NV2080_ENGINE_TYPE_NVDEC6 = (0x00000019) +NV2080_ENGINE_TYPE_NVDEC7 = (0x0000001a) +NV2080_ENGINE_TYPE_MSENC = (0x0000001b) +NV2080_ENGINE_TYPE_NVENC0 = NV2080_ENGINE_TYPE_MSENC +NV2080_ENGINE_TYPE_NVENC1 = (0x0000001c) +NV2080_ENGINE_TYPE_NVENC2 = (0x0000001d) +NV2080_ENGINE_TYPE_VP = (0x0000001e) +NV2080_ENGINE_TYPE_ME = (0x0000001f) +NV2080_ENGINE_TYPE_PPP = (0x00000020) +NV2080_ENGINE_TYPE_MPEG = (0x00000021) +NV2080_ENGINE_TYPE_SW = (0x00000022) +NV2080_ENGINE_TYPE_CIPHER = (0x00000023) +NV2080_ENGINE_TYPE_TSEC = NV2080_ENGINE_TYPE_CIPHER +NV2080_ENGINE_TYPE_VIC = (0x00000024) +NV2080_ENGINE_TYPE_MP = (0x00000025) +NV2080_ENGINE_TYPE_SEC2 = (0x00000026) +NV2080_ENGINE_TYPE_HOST = (0x00000027) +NV2080_ENGINE_TYPE_DPU = (0x00000028) +NV2080_ENGINE_TYPE_PMU = (0x00000029) +NV2080_ENGINE_TYPE_FBFLCN = (0x0000002a) +NV2080_ENGINE_TYPE_NVJPG = (0x0000002b) +NV2080_ENGINE_TYPE_NVJPEG0 = NV2080_ENGINE_TYPE_NVJPG +NV2080_ENGINE_TYPE_NVJPEG1 = (0x0000002c) +NV2080_ENGINE_TYPE_NVJPEG2 = (0x0000002d) +NV2080_ENGINE_TYPE_NVJPEG3 = (0x0000002e) +NV2080_ENGINE_TYPE_NVJPEG4 = (0x0000002f) +NV2080_ENGINE_TYPE_NVJPEG5 = (0x00000030) +NV2080_ENGINE_TYPE_NVJPEG6 = (0x00000031) +NV2080_ENGINE_TYPE_NVJPEG7 = (0x00000032) +NV2080_ENGINE_TYPE_OFA = (0x00000033) +NV2080_ENGINE_TYPE_OFA0 = NV2080_ENGINE_TYPE_OFA +NV2080_ENGINE_TYPE_COPY10 = (0x00000034) +NV2080_ENGINE_TYPE_COPY11 = (0x00000035) +NV2080_ENGINE_TYPE_COPY12 = (0x00000036) +NV2080_ENGINE_TYPE_COPY13 = (0x00000037) +NV2080_ENGINE_TYPE_COPY14 = (0x00000038) +NV2080_ENGINE_TYPE_COPY15 = (0x00000039) +NV2080_ENGINE_TYPE_COPY16 = (0x0000003a) +NV2080_ENGINE_TYPE_COPY17 = (0x0000003b) +NV2080_ENGINE_TYPE_COPY18 = (0x0000003c) +NV2080_ENGINE_TYPE_COPY19 = (0x0000003d) +NV2080_ENGINE_TYPE_OFA1 = (0x0000003e) +NV2080_ENGINE_TYPE_NVENC3 = (0x0000003f) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 = (0x00000040) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 = (0x00000041) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 = (0x00000042) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 = (0x00000043) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 = (0x00000044) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 = (0x00000045) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 = (0x00000046) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 = (0x00000047) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 = (0x00000048) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 = (0x00000049) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 = (0x0000004a) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 = (0x0000004b) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 = (0x0000004c) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 = (0x0000004d) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 = (0x0000004e) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 = (0x0000004f) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 = (0x00000050) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 = (0x00000051) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 = (0x00000052) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 = (0x00000053) +NV2080_ENGINE_TYPE_LAST = (0x00000054) +NV2080_ENGINE_TYPE_ALLENGINES = (0xffffffff) +NV2080_ENGINE_TYPE_COPY_SIZE = 64 +NV2080_ENGINE_TYPE_NVENC_SIZE = 4 +NV2080_ENGINE_TYPE_NVJPEG_SIZE = 8 +NV2080_ENGINE_TYPE_NVDEC_SIZE = 8 +NV2080_ENGINE_TYPE_GR_SIZE = 8 +NV2080_ENGINE_TYPE_OFA_SIZE = 2 +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY = lambda i: (NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 + (i)) +NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY = lambda i: (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19)) +NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) +NV2080_ENGINE_TYPE_IS_COPY = lambda i: ((((i) >= NV2080_ENGINE_TYPE_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COPY9)) or (((i) >= NV2080_ENGINE_TYPE_COPY10) and ((i) <= NV2080_ENGINE_TYPE_COPY19))) +NV2080_ENGINE_TYPE_IS_NVENC = lambda i: ((((i) >= NV2080_ENGINE_TYPE_NVENC0) and ((i) <= NV2080_ENGINE_TYPE_NVENC2)) or (((i) == NV2080_ENGINE_TYPE_NVENC3))) +NV2080_ENGINE_TYPE_NVDEC = lambda i: (NV2080_ENGINE_TYPE_NVDEC0+(i)) +NV2080_ENGINE_TYPE_IS_NVDEC = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVDEC0) and ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) +NV2080_ENGINE_TYPE_NVDEC_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVDEC0) +NV2080_ENGINE_TYPE_NVJPEG = lambda i: (NV2080_ENGINE_TYPE_NVJPEG0+(i)) +NV2080_ENGINE_TYPE_IS_NVJPEG = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) and ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) +NV2080_ENGINE_TYPE_NVJPEG_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVJPEG0) +NV2080_ENGINE_TYPE_GR = lambda i: (NV2080_ENGINE_TYPE_GR0 + (i)) +NV2080_ENGINE_TYPE_IS_GR = lambda i: (((i) >= NV2080_ENGINE_TYPE_GR0) and ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) +NV2080_ENGINE_TYPE_GR_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_GR0) +NV2080_ENGINE_TYPE_IS_OFA = lambda i: (((i) == NV2080_ENGINE_TYPE_OFA0) or ((i) == NV2080_ENGINE_TYPE_OFA1)) +NV2080_ENGINE_TYPE_IS_VALID = lambda i: (((i) > (NV2080_ENGINE_TYPE_NULL)) and ((i) < (NV2080_ENGINE_TYPE_LAST))) +NV2080_CLIENT_TYPE_TEX = (0x00000001) +NV2080_CLIENT_TYPE_COLOR = (0x00000002) +NV2080_CLIENT_TYPE_DEPTH = (0x00000003) +NV2080_CLIENT_TYPE_DA = (0x00000004) +NV2080_CLIENT_TYPE_FE = (0x00000005) +NV2080_CLIENT_TYPE_SCC = (0x00000006) +NV2080_CLIENT_TYPE_WID = (0x00000007) +NV2080_CLIENT_TYPE_MSVLD = (0x00000008) +NV2080_CLIENT_TYPE_MSPDEC = (0x00000009) +NV2080_CLIENT_TYPE_MSPPP = (0x0000000a) +NV2080_CLIENT_TYPE_VIC = (0x0000000b) +NV2080_CLIENT_TYPE_ALLCLIENTS = (0xffffffff) +NV2080_GC5_EXIT_COMPLETE = (0x00000001) +NV2080_GC5_ENTRY_ABORTED = (0x00000002) +NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION = (0x00000000) +NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION = (0x00000001) +NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT = (0x4000) +NV2080_TYPEDEF = Nv20Subdevice0 +AMPERE_CHANNEL_GPFIFO_A = (0x0000C56F) +NVC56F_NUMBER_OF_SUBCHANNELS = (8) +NVC56F_SET_OBJECT = (0x00000000) +NVC56F_SET_OBJECT_ENGINE_SW = 0x0000001f +NVC56F_ILLEGAL = (0x00000004) +NVC56F_NOP = (0x00000008) +NVC56F_SEMAPHOREA = (0x00000010) +NVC56F_SEMAPHOREB = (0x00000014) +NVC56F_SEMAPHOREC = (0x00000018) +NVC56F_SEMAPHORED = (0x0000001C) +NVC56F_SEMAPHORED_OPERATION_ACQUIRE = 0x00000001 +NVC56F_SEMAPHORED_OPERATION_RELEASE = 0x00000002 +NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ = 0x00000004 +NVC56F_SEMAPHORED_OPERATION_ACQ_AND = 0x00000008 +NVC56F_SEMAPHORED_OPERATION_REDUCTION = 0x00000010 +NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED = 0x00000000 +NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED = 0x00000001 +NVC56F_SEMAPHORED_RELEASE_WFI_EN = 0x00000000 +NVC56F_SEMAPHORED_RELEASE_WFI_DIS = 0x00000001 +NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE = 0x00000000 +NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE = 0x00000001 +NVC56F_SEMAPHORED_REDUCTION_MIN = 0x00000000 +NVC56F_SEMAPHORED_REDUCTION_MAX = 0x00000001 +NVC56F_SEMAPHORED_REDUCTION_XOR = 0x00000002 +NVC56F_SEMAPHORED_REDUCTION_AND = 0x00000003 +NVC56F_SEMAPHORED_REDUCTION_OR = 0x00000004 +NVC56F_SEMAPHORED_REDUCTION_ADD = 0x00000005 +NVC56F_SEMAPHORED_REDUCTION_INC = 0x00000006 +NVC56F_SEMAPHORED_REDUCTION_DEC = 0x00000007 +NVC56F_SEMAPHORED_FORMAT_SIGNED = 0x00000000 +NVC56F_SEMAPHORED_FORMAT_UNSIGNED = 0x00000001 +NVC56F_NON_STALL_INTERRUPT = (0x00000020) +NVC56F_FB_FLUSH = (0x00000024) +NVC56F_MEM_OP_A = (0x00000028) +NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 +NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 +NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 +NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 +NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 +NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 +NVC56F_MEM_OP_B = (0x0000002c) +NVC56F_MEM_OP_C = (0x00000030) +NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 +NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 +NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 +NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 +NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 +NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 +NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 +NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 +NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 +NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 +NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 +NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 +NVC56F_MEM_OP_D = (0x00000034) +NVC56F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 +NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 +NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a +NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d +NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e +NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e +NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f +NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 +NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 +NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 +NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 +NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 +NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 +NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 +NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 +NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 +NVC56F_SET_REFERENCE = (0x00000050) +NVC56F_SEM_ADDR_LO = (0x0000005c) +NVC56F_SEM_ADDR_HI = (0x00000060) +NVC56F_SEM_PAYLOAD_LO = (0x00000064) +NVC56F_SEM_PAYLOAD_HI = (0x00000068) +NVC56F_SEM_EXECUTE = (0x0000006c) +NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 +NVC56F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 +NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ = 0x00000002 +NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003 +NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND = 0x00000004 +NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR = 0x00000005 +NVC56F_SEM_EXECUTE_OPERATION_REDUCTION = 0x00000006 +NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS = 0x00000000 +NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001 +NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 +NVC56F_SEM_EXECUTE_RELEASE_WFI_EN = 0x00000001 +NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 +NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT = 0x00000001 +NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000 +NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001 +NVC56F_SEM_EXECUTE_REDUCTION_IMIN = 0x00000000 +NVC56F_SEM_EXECUTE_REDUCTION_IMAX = 0x00000001 +NVC56F_SEM_EXECUTE_REDUCTION_IXOR = 0x00000002 +NVC56F_SEM_EXECUTE_REDUCTION_IAND = 0x00000003 +NVC56F_SEM_EXECUTE_REDUCTION_IOR = 0x00000004 +NVC56F_SEM_EXECUTE_REDUCTION_IADD = 0x00000005 +NVC56F_SEM_EXECUTE_REDUCTION_INC = 0x00000006 +NVC56F_SEM_EXECUTE_REDUCTION_DEC = 0x00000007 +NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000000 +NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000001 +NVC56F_WFI = (0x00000078) +NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 +NVC56F_WFI_SCOPE_CURRENT_VEID = 0x00000000 +NVC56F_WFI_SCOPE_ALL = 0x00000001 +NVC56F_YIELD = (0x00000080) +NVC56F_YIELD_OP_NOP = 0x00000000 +NVC56F_YIELD_OP_TSG = 0x00000003 +NVC56F_CLEAR_FAULTED = (0x00000084) +NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED = 0x00000000 +NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED = 0x00000001 +NVC56F_GP_ENTRY__SIZE = 8 +NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 +NVC56F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 +NVC56F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 +NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 +NVC56F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 +NVC56F_GP_ENTRY1_SYNC_WAIT = 0x00000001 +NVC56F_GP_ENTRY1_OPCODE_NOP = 0x00000000 +NVC56F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 +NVC56F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 +NVC56F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 +NVC56F_DMA_TERT_OP_GRP0_INC_METHOD = (0x00000000) +NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK = (0x00000001) +NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK = (0x00000002) +NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK = (0x00000003) +NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD = (0x00000000) +NVC56F_DMA_SEC_OP_GRP0_USE_TERT = (0x00000000) +NVC56F_DMA_SEC_OP_INC_METHOD = (0x00000001) +NVC56F_DMA_SEC_OP_GRP2_USE_TERT = (0x00000002) +NVC56F_DMA_SEC_OP_NON_INC_METHOD = (0x00000003) +NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD = (0x00000004) +NVC56F_DMA_SEC_OP_ONE_INC = (0x00000005) +NVC56F_DMA_SEC_OP_RESERVED6 = (0x00000006) +NVC56F_DMA_SEC_OP_END_PB_SEGMENT = (0x00000007) +NVC56F_DMA_INCR_OPCODE_VALUE = (0x00000001) +NVC56F_DMA_NONINCR_OPCODE_VALUE = (0x00000003) +NVC56F_DMA_ONEINCR_OPCODE_VALUE = (0x00000005) +NVC56F_DMA_NOP = (0x00000000) +NVC56F_DMA_IMMD_OPCODE_VALUE = (0x00000004) +NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000001) +NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000002) +NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000003) +NVC56F_DMA_ENDSEG_OPCODE_VALUE = (0x00000007) +NVC56F_DMA_OPCODE3_NONE = (0x00000000) +NVC56F_DMA_OPCODE_METHOD = (0x00000000) +NVC56F_DMA_OPCODE_NONINC_METHOD = (0x00000002) +HOPPER_CHANNEL_GPFIFO_A = (0x0000C86F) +NVC86F_SET_OBJECT = (0x00000000) +NVC86F_SEM_ADDR_LO = (0x0000005c) +NVC86F_SEM_ADDR_HI = (0x00000060) +NVC86F_SEM_PAYLOAD_LO = (0x00000064) +NVC86F_SEM_PAYLOAD_HI = (0x00000068) +NVC86F_SEM_EXECUTE = (0x0000006c) +NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 +NVC86F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 +NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 +NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 +NVC86F_GP_ENTRY__SIZE = 8 +NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 +NVC86F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 +NVC86F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 +NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 +NVC86F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 +NVC86F_GP_ENTRY1_SYNC_WAIT = 0x00000001 +NVC86F_GP_ENTRY1_OPCODE_NOP = 0x00000000 +NVC86F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 +NVC86F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 +NVC86F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 +NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 +NVC86F_WFI = (0x00000078) +NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000 +NVC86F_WFI_SCOPE_CURRENT_VEID = 0x00000000 +NVC86F_WFI_SCOPE_ALL = 0x00000001 +NVC86F_MEM_OP_A = (0x00000028) +NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0 +NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1 +NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2 +NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3 +NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001 +NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000 +NVC86F_MEM_OP_B = (0x0000002c) +NVC86F_MEM_OP_C = (0x00000030) +NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000 +NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001 +NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000 +NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001 +NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000 +NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001 +NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002 +NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003 +NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004 +NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6 +NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002 +NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003 +NVC86F_MEM_OP_D = (0x00000034) +NVC86F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005 +NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009 +NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a +NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION = 0x0000000b +NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d +NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e +NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e +NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f +NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010 +NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015 +NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016 +NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000 +NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001 +NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002 +NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003 +NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000 +NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001 +NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED = 0x00000000 +NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP = 0x00000001 +BLACKWELL_CHANNEL_GPFIFO_A = (0x0000C96F) +NVC96F_SET_OBJECT = (0x00000000) +NVC96F_SEM_ADDR_LO = (0x0000005c) +NVC96F_SEM_ADDR_HI = (0x00000060) +NVC96F_SEM_PAYLOAD_LO = (0x00000064) +NVC96F_SEM_PAYLOAD_HI = (0x00000068) +NVC96F_SEM_EXECUTE = (0x0000006c) +NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000 +NVC96F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001 +NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000 +NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000 +NVC96F_GP_ENTRY__SIZE = 8 +NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000 +NVC96F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001 +NVC96F_GP_ENTRY1_LEVEL_MAIN = 0x00000000 +NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001 +NVC96F_GP_ENTRY1_SYNC_PROCEED = 0x00000000 +NVC96F_GP_ENTRY1_SYNC_WAIT = 0x00000001 +NVC96F_GP_ENTRY1_OPCODE_NOP = 0x00000000 +NVC96F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001 +NVC96F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002 +NVC96F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003 +NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004 +BLACKWELL_USERMODE_A = (0xc761) +GT200_DEBUGGER = (0x83de) +NV83DE_ALLOC_PARAMETERS_MESSAGE_ID = (0x83de) +AMPERE_COMPUTE_A = 0xC6C0 +NVC6C0_SET_OBJECT = 0x0000 +NVC6C0_NO_OPERATION = 0x0100 +NVC6C0_SET_NOTIFY_A = 0x0104 +NVC6C0_SET_NOTIFY_B = 0x0108 +NVC6C0_NOTIFY = 0x010c +NVC6C0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000 +NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001 +NVC6C0_WAIT_FOR_IDLE = 0x0110 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 +NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 +NVC6C0_SEND_GO_IDLE = 0x013c +NVC6C0_PM_TRIGGER = 0x0140 +NVC6C0_PM_TRIGGER_WFI = 0x0144 +NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148 +NVC6C0_FE_ATOMIC_SEQUENCE_END = 0x014c +NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150 +NVC6C0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154 +NVC6C0_LINE_LENGTH_IN = 0x0180 +NVC6C0_LINE_COUNT = 0x0184 +NVC6C0_OFFSET_OUT_UPPER = 0x0188 +NVC6C0_OFFSET_OUT = 0x018c +NVC6C0_PITCH_OUT = 0x0190 +NVC6C0_SET_DST_BLOCK_SIZE = 0x0194 +NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = 0x00000000 +NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = 0x00000000 +NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = 0x00000001 +NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = 0x00000002 +NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = 0x00000003 +NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = 0x00000004 +NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = 0x00000005 +NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = 0x00000000 +NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = 0x00000001 +NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = 0x00000002 +NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = 0x00000003 +NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = 0x00000004 +NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = 0x00000005 +NVC6C0_SET_DST_WIDTH = 0x0198 +NVC6C0_SET_DST_HEIGHT = 0x019c +NVC6C0_SET_DST_DEPTH = 0x01a0 +NVC6C0_SET_DST_LAYER = 0x01a4 +NVC6C0_SET_DST_ORIGIN_BYTES_X = 0x01a8 +NVC6C0_SET_DST_ORIGIN_SAMPLES_Y = 0x01ac +NVC6C0_LAUNCH_DMA = 0x01b0 +NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000 +NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001 +NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000 +NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001 +NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002 +NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000 +NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001 +NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000 +NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001 +NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000 +NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001 +NVC6C0_LOAD_INLINE_DATA = 0x01b4 +NVC6C0_SET_I2M_SEMAPHORE_A = 0x01dc +NVC6C0_SET_I2M_SEMAPHORE_B = 0x01e0 +NVC6C0_SET_I2M_SEMAPHORE_C = 0x01e4 +NVC6C0_SET_SM_SCG_CONTROL = 0x01e8 +NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000 +NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001 +NVC6C0_SET_I2M_SPARE_NOOP00 = 0x01f0 +NVC6C0_SET_I2M_SPARE_NOOP01 = 0x01f4 +NVC6C0_SET_I2M_SPARE_NOOP02 = 0x01f8 +NVC6C0_SET_I2M_SPARE_NOOP03 = 0x01fc +NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200 +NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204 +NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208 +NVC6C0_PERFMON_TRANSFER = 0x0210 +NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A = 0x0214 +NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B = 0x0218 +NVC6C0_INVALIDATE_SHADER_CACHES = 0x021c +NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001 +NVC6C0_SET_RESERVED_SW_METHOD00 = 0x0220 +NVC6C0_SET_RESERVED_SW_METHOD01 = 0x0224 +NVC6C0_SET_RESERVED_SW_METHOD02 = 0x0228 +NVC6C0_SET_RESERVED_SW_METHOD03 = 0x022c +NVC6C0_SET_RESERVED_SW_METHOD04 = 0x0230 +NVC6C0_SET_RESERVED_SW_METHOD05 = 0x0234 +NVC6C0_SET_RESERVED_SW_METHOD06 = 0x0238 +NVC6C0_SET_RESERVED_SW_METHOD07 = 0x023c +NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244 +NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000 +NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001 +NVC6C0_SET_CWD_REF_COUNTER = 0x0248 +NVC6C0_SET_RESERVED_SW_METHOD08 = 0x024c +NVC6C0_SET_RESERVED_SW_METHOD09 = 0x0250 +NVC6C0_SET_RESERVED_SW_METHOD10 = 0x0254 +NVC6C0_SET_RESERVED_SW_METHOD11 = 0x0258 +NVC6C0_SET_RESERVED_SW_METHOD12 = 0x025c +NVC6C0_SET_RESERVED_SW_METHOD13 = 0x0260 +NVC6C0_SET_RESERVED_SW_METHOD14 = 0x0264 +NVC6C0_SET_RESERVED_SW_METHOD15 = 0x0268 +NVC6C0_SET_SCG_CONTROL = 0x0270 +NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = 0x00000000 +NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = 0x00000001 +NVC6C0_SET_COMPUTE_CLASS_VERSION = 0x0280 +NVC6C0_CHECK_COMPUTE_CLASS_VERSION = 0x0284 +NVC6C0_SET_QMD_VERSION = 0x0288 +NVC6C0_CHECK_QMD_VERSION = 0x0290 +NVC6C0_INVALIDATE_SKED_CACHES = 0x0298 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL = 0x029c +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0 +NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4 +NVC6C0_SCG_HYSTERESIS_CONTROL = 0x02a8 +NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE = 0x00000000 +NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE = 0x00000001 +NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE = 0x00000000 +NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE = 0x00000001 +NVC6C0_SET_CWD_SLOT_COUNT = 0x02b0 +NVC6C0_SEND_PCAS_A = 0x02b4 +NVC6C0_SEND_PCAS_B = 0x02b8 +NVC6C0_SEND_SIGNALING_PCAS_B = 0x02bc +NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000 +NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001 +NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000 +NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001 +NVC6C0_SEND_SIGNALING_PCAS2_B = 0x02c0 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009 +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A +NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B +NVC6C0_SET_SKED_CACHE_CONTROL = 0x02cc +NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000 +NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001 +NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4 +NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8 +NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec +NVC6C0_SET_SPA_VERSION = 0x0310 +NVC6C0_SET_INLINE_QMD_ADDRESS_A = 0x0318 +NVC6C0_SET_INLINE_QMD_ADDRESS_B = 0x031c +NVC6C0_LOAD_INLINE_QMD_DATA = lambda i: (0x0320+(i)*4) +NVC6C0_SET_FALCON00 = 0x0500 +NVC6C0_SET_FALCON01 = 0x0504 +NVC6C0_SET_FALCON02 = 0x0508 +NVC6C0_SET_FALCON03 = 0x050c +NVC6C0_SET_FALCON04 = 0x0510 +NVC6C0_SET_FALCON05 = 0x0514 +NVC6C0_SET_FALCON06 = 0x0518 +NVC6C0_SET_FALCON07 = 0x051c +NVC6C0_SET_FALCON08 = 0x0520 +NVC6C0_SET_FALCON09 = 0x0524 +NVC6C0_SET_FALCON10 = 0x0528 +NVC6C0_SET_FALCON11 = 0x052c +NVC6C0_SET_FALCON12 = 0x0530 +NVC6C0_SET_FALCON13 = 0x0534 +NVC6C0_SET_FALCON14 = 0x0538 +NVC6C0_SET_FALCON15 = 0x053c +NVC6C0_SET_SHADER_LOCAL_MEMORY_A = 0x0790 +NVC6C0_SET_SHADER_LOCAL_MEMORY_B = 0x0794 +NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0 +NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4 +NVC6C0_SET_SHADER_CACHE_CONTROL = 0x0d94 +NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS = lambda i: (0x0da0+(i)*4) +NVC6C0_SET_SM_TIMEOUT_INTERVAL = 0x0de4 +NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288 +NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000 +NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001 +NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8 +NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000 +NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SAMPLER_CACHE = 0x1330 +NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000 +NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001 +NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334 +NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000 +NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001 +NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338 +NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000 +NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001 +NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424 +NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000 +NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001 +NVC6C0_SET_SHADER_EXCEPTIONS = 0x1528 +NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_RENDER_ENABLE_A = 0x1550 +NVC6C0_SET_RENDER_ENABLE_B = 0x1554 +NVC6C0_SET_RENDER_ENABLE_C = 0x1558 +NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000 +NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001 +NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002 +NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003 +NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004 +NVC6C0_SET_TEX_SAMPLER_POOL_A = 0x155c +NVC6C0_SET_TEX_SAMPLER_POOL_B = 0x1560 +NVC6C0_SET_TEX_SAMPLER_POOL_C = 0x1564 +NVC6C0_SET_TEX_HEADER_POOL_A = 0x1574 +NVC6C0_SET_TEX_HEADER_POOL_B = 0x1578 +NVC6C0_SET_TEX_HEADER_POOL_C = 0x157c +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698 +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001 +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000 +NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001 +NVC6C0_SET_RENDER_ENABLE_OVERRIDE = 0x1944 +NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000 +NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001 +NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002 +NVC6C0_PIPE_NOP = 0x1a2c +NVC6C0_SET_SPARE00 = 0x1a30 +NVC6C0_SET_SPARE01 = 0x1a34 +NVC6C0_SET_SPARE02 = 0x1a38 +NVC6C0_SET_SPARE03 = 0x1a3c +NVC6C0_SET_REPORT_SEMAPHORE_A = 0x1b00 +NVC6C0_SET_REPORT_SEMAPHORE_B = 0x1b04 +NVC6C0_SET_REPORT_SEMAPHORE_C = 0x1b08 +NVC6C0_SET_REPORT_SEMAPHORE_D = 0x1b0c +NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003 +NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001 +NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001 +NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000 +NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001 +NVC6C0_SET_TRAP_HANDLER_A = 0x25f8 +NVC6C0_SET_TRAP_HANDLER_B = 0x25fc +NVC6C0_SET_BINDLESS_TEXTURE = 0x2608 +NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE = lambda i: (0x32f4+(i)*4) +NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER = lambda i: (0x3314+(i)*4) +NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334 +NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338 +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER = lambda i: (0x333c+(i)*4) +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE = lambda i: (0x335c+(i)*4) +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT = lambda i: (0x337c+(i)*4) +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A = lambda i: (0x339c+(i)*4) +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B = lambda i: (0x33bc+(i)*4) +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc +NVC6C0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0 +NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4 +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8 +NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec +NVC6C0_SET_MME_SHADOW_SCRATCH = lambda i: (0x3400+(i)*4) +BLACKWELL_COMPUTE_A = 0xCDC0 +AMPERE_DMA_COPY_A = (0x0000C6B5) +NVC6B5_NOP = (0x00000100) +NVC6B5_PM_TRIGGER = (0x00000140) +NVC6B5_SET_SEMAPHORE_A = (0x00000240) +NVC6B5_SET_SEMAPHORE_B = (0x00000244) +NVC6B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) +NVC6B5_SET_RENDER_ENABLE_A = (0x00000254) +NVC6B5_SET_RENDER_ENABLE_B = (0x00000258) +NVC6B5_SET_RENDER_ENABLE_C = (0x0000025C) +NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) +NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) +NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) +NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) +NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) +NVC6B5_SET_SRC_PHYS_MODE = (0x00000260) +NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) +NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) +NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) +NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) +NVC6B5_SET_DST_PHYS_MODE = (0x00000264) +NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) +NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) +NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) +NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) +NVC6B5_LAUNCH_DMA = (0x00000300) +NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) +NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) +NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) +NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) +NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) +NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) +NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) +NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) +NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) +NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) +NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) +NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) +NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) +NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) +NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) +NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) +NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) +NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) +NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) +NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) +NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) +NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) +NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE = (0x00000000) +NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE = (0x00000001) +NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) +NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) +NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) +NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) +NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) +NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) +NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) +NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) +NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) +NVC6B5_OFFSET_IN_UPPER = (0x00000400) +NVC6B5_OFFSET_IN_LOWER = (0x00000404) +NVC6B5_OFFSET_OUT_UPPER = (0x00000408) +NVC6B5_OFFSET_OUT_LOWER = (0x0000040C) +NVC6B5_PITCH_IN = (0x00000410) +NVC6B5_PITCH_OUT = (0x00000414) +NVC6B5_LINE_LENGTH_IN = (0x00000418) +NVC6B5_LINE_COUNT = (0x0000041C) +NVC6B5_SET_REMAP_CONST_A = (0x00000700) +NVC6B5_SET_REMAP_CONST_B = (0x00000704) +NVC6B5_SET_REMAP_COMPONENTS = (0x00000708) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) +NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) +NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) +NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) +NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) +NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) +NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) +NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) +NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) +NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) +NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) +NVC6B5_SET_DST_BLOCK_SIZE = (0x0000070C) +NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) +NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) +NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) +NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) +NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) +NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) +NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) +NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) +NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) +NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) +NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) +NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) +NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) +NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) +NVC6B5_SET_DST_WIDTH = (0x00000710) +NVC6B5_SET_DST_HEIGHT = (0x00000714) +NVC6B5_SET_DST_DEPTH = (0x00000718) +NVC6B5_SET_DST_LAYER = (0x0000071C) +NVC6B5_SET_DST_ORIGIN = (0x00000720) +NVC6B5_SET_SRC_BLOCK_SIZE = (0x00000728) +NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) +NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) +NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) +NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) +NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) +NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) +NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) +NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) +NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) +NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) +NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) +NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) +NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) +NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) +NVC6B5_SET_SRC_WIDTH = (0x0000072C) +NVC6B5_SET_SRC_HEIGHT = (0x00000730) +NVC6B5_SET_SRC_DEPTH = (0x00000734) +NVC6B5_SET_SRC_LAYER = (0x00000738) +NVC6B5_SET_SRC_ORIGIN = (0x0000073C) +NVC6B5_SRC_ORIGIN_X = (0x00000744) +NVC6B5_SRC_ORIGIN_Y = (0x00000748) +NVC6B5_DST_ORIGIN_X = (0x0000074C) +NVC6B5_DST_ORIGIN_Y = (0x00000750) +NVC6B5_PM_TRIGGER_END = (0x00001114) +BLACKWELL_DMA_COPY_A = (0x0000C9B5) +NVC9B5_NOP = (0x00000100) +NVC9B5_PM_TRIGGER = (0x00000140) +NVC9B5_SET_MONITORED_FENCE_TYPE = (0x0000021C) +NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE = (0x00000000) +NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT = (0x00000001) +NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER = (0x00000220) +NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER = (0x00000224) +NVC9B5_SET_SEMAPHORE_A = (0x00000240) +NVC9B5_SET_SEMAPHORE_B = (0x00000244) +NVC9B5_SET_SEMAPHORE_PAYLOAD = (0x00000248) +NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER = (0x0000024C) +NVC9B5_SET_RENDER_ENABLE_A = (0x00000254) +NVC9B5_SET_RENDER_ENABLE_B = (0x00000258) +NVC9B5_SET_RENDER_ENABLE_C = (0x0000025C) +NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000) +NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001) +NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002) +NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003) +NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004) +NVC9B5_SET_SRC_PHYS_MODE = (0x00000260) +NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) +NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) +NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) +NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003) +NVC9B5_SET_DST_PHYS_MODE = (0x00000264) +NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000) +NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001) +NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002) +NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003) +NVC9B5_LAUNCH_DMA = (0x00000300) +NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000) +NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001) +NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002) +NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000) +NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000) +NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP = (0x00000002) +NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002) +NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003) +NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000) +NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001) +NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002) +NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) +NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001) +NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000) +NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001) +NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000) +NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001) +NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000) +NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA = (0x00000008) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB = (0x00000009) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN = (0x0000000B) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX = (0x0000000C) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC = (0x0000000D) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD = (0x0000000E) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE = (0x0000000F) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT = (0x00000000) +NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT = (0x00000000) +NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE = (0x00000001) +NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT = (0x00000002) +NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED = (0x00000003) +NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000) +NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001) +NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000) +NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001) +NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD = (0x00000000) +NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD = (0x00000001) +NVC9B5_OFFSET_IN_UPPER = (0x00000400) +NVC9B5_OFFSET_IN_LOWER = (0x00000404) +NVC9B5_OFFSET_OUT_UPPER = (0x00000408) +NVC9B5_OFFSET_OUT_LOWER = (0x0000040C) +NVC9B5_PITCH_IN = (0x00000410) +NVC9B5_PITCH_OUT = (0x00000414) +NVC9B5_LINE_LENGTH_IN = (0x00000418) +NVC9B5_LINE_COUNT = (0x0000041C) +NVC9B5_SET_SECURE_COPY_MODE = (0x00000500) +NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT = (0x00000000) +NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT = (0x00000001) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB = (0x00000000) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM = (0x00000001) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM = (0x00000002) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM = (0x00000003) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB = (0x00000000) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM = (0x00000001) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM = (0x00000002) +NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM = (0x00000003) +NVC9B5_SET_DECRYPT_IV0 = (0x00000504) +NVC9B5_SET_DECRYPT_IV1 = (0x00000508) +NVC9B5_SET_DECRYPT_IV2 = (0x0000050C) +NVC9B5_RESERVED_SET_AESCOUNTER = (0x00000510) +NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER = (0x00000514) +NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER = (0x00000518) +NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER = (0x00000530) +NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER = (0x00000534) +NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER = (0x00000538) +NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER = (0x0000053C) +NVC9B5_SET_COMPRESSION_PARAMETERS = (0x00000580) +NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS = (0x00000000) +NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS = (0x00000001) +NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY = (0x00000000) +NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY = (0x00000001) +NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK = (0x00000002) +NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM = (0x00000003) +NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE = (0x00000004) +NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH = (0x00000005) +NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE = (0x00000000) +NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32 = (0x00000001) +NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32 = (0x00000002) +NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC = (0x00000003) +NVC9B5_SET_DECOMPRESS_OUT_LENGTH = (0x00000584) +NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER = (0x00000588) +NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER = (0x0000058C) +NVC9B5_SET_DECOMPRESS_CHECKSUM = (0x00000590) +NVC9B5_SET_MEMORY_SCRUB_PARAMETERS = (0x000006FC) +NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE = (0x00000000) +NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE = (0x00000001) +NVC9B5_SET_REMAP_CONST_A = (0x00000700) +NVC9B5_SET_REMAP_CONST_B = (0x00000704) +NVC9B5_SET_REMAP_COMPONENTS = (0x00000708) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005) +NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005) +NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005) +NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005) +NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006) +NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003) +NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003) +NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000) +NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001) +NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002) +NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003) +NVC9B5_SET_DST_BLOCK_SIZE = (0x0000070C) +NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) +NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) +NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) +NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) +NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) +NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) +NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) +NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) +NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) +NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) +NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) +NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) +NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) +NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) +NVC9B5_SET_DST_WIDTH = (0x00000710) +NVC9B5_SET_DST_HEIGHT = (0x00000714) +NVC9B5_SET_DST_DEPTH = (0x00000718) +NVC9B5_SET_DST_LAYER = (0x0000071C) +NVC9B5_SET_DST_ORIGIN = (0x00000720) +NVC9B5_SET_SRC_BLOCK_SIZE = (0x00000728) +NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000) +NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000) +NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001) +NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002) +NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003) +NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004) +NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005) +NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000) +NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001) +NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002) +NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003) +NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004) +NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005) +NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001) +NVC9B5_SET_SRC_WIDTH = (0x0000072C) +NVC9B5_SET_SRC_HEIGHT = (0x00000730) +NVC9B5_SET_SRC_DEPTH = (0x00000734) +NVC9B5_SET_SRC_LAYER = (0x00000738) +NVC9B5_SET_SRC_ORIGIN = (0x0000073C) +NVC9B5_SRC_ORIGIN_X = (0x00000744) +NVC9B5_SRC_ORIGIN_Y = (0x00000748) +NVC9B5_DST_ORIGIN_X = (0x0000074C) +NVC9B5_DST_ORIGIN_Y = (0x00000750) +NVC9B5_PM_TRIGGER_END = (0x00001114) +UVM_IOCTL_BASE = lambda i: i +UVM_RESERVE_VA = UVM_IOCTL_BASE(1) +UVM_RELEASE_VA = UVM_IOCTL_BASE(2) +UVM_REGION_COMMIT = UVM_IOCTL_BASE(3) +UVM_REGION_DECOMMIT = UVM_IOCTL_BASE(4) +UVM_REGION_SET_STREAM = UVM_IOCTL_BASE(5) +UVM_SET_STREAM_RUNNING = UVM_IOCTL_BASE(6) +UVM_MAX_STREAMS_PER_IOCTL_CALL = 32 +UVM_SET_STREAM_STOPPED = UVM_IOCTL_BASE(7) +UVM_RUN_TEST = UVM_IOCTL_BASE(9) +UVM_EVENTS_OFFSET_BASE = (1 << 63) +UVM_COUNTERS_OFFSET_BASE = (1 << 62) +UVM_ADD_SESSION = UVM_IOCTL_BASE(10) +UVM_REMOVE_SESSION = UVM_IOCTL_BASE(11) +UVM_MAX_COUNTERS_PER_IOCTL_CALL = 32 +UVM_ENABLE_COUNTERS = UVM_IOCTL_BASE(12) +UVM_MAP_COUNTER = UVM_IOCTL_BASE(13) +UVM_CREATE_EVENT_QUEUE = UVM_IOCTL_BASE(14) +UVM_REMOVE_EVENT_QUEUE = UVM_IOCTL_BASE(15) +UVM_MAP_EVENT_QUEUE = UVM_IOCTL_BASE(16) +UVM_EVENT_CTRL = UVM_IOCTL_BASE(17) +UVM_REGISTER_MPS_SERVER = UVM_IOCTL_BASE(18) +UVM_REGISTER_MPS_CLIENT = UVM_IOCTL_BASE(19) +UVM_GET_GPU_UUID_TABLE = UVM_IOCTL_BASE(20) +UVM_CREATE_RANGE_GROUP = UVM_IOCTL_BASE(23) +UVM_DESTROY_RANGE_GROUP = UVM_IOCTL_BASE(24) +UVM_REGISTER_GPU_VASPACE = UVM_IOCTL_BASE(25) +UVM_UNREGISTER_GPU_VASPACE = UVM_IOCTL_BASE(26) +UVM_REGISTER_CHANNEL = UVM_IOCTL_BASE(27) +UVM_UNREGISTER_CHANNEL = UVM_IOCTL_BASE(28) +UVM_ENABLE_PEER_ACCESS = UVM_IOCTL_BASE(29) +UVM_DISABLE_PEER_ACCESS = UVM_IOCTL_BASE(30) +UVM_SET_RANGE_GROUP = UVM_IOCTL_BASE(31) +UVM_MAP_EXTERNAL_ALLOCATION = UVM_IOCTL_BASE(33) +UVM_FREE = UVM_IOCTL_BASE(34) +UVM_MEM_MAP = UVM_IOCTL_BASE(35) +UVM_DEBUG_ACCESS_MEMORY = UVM_IOCTL_BASE(36) +UVM_REGISTER_GPU = UVM_IOCTL_BASE(37) +UVM_UNREGISTER_GPU = UVM_IOCTL_BASE(38) +UVM_PAGEABLE_MEM_ACCESS = UVM_IOCTL_BASE(39) +UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL = 32 +UVM_PREVENT_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE(40) +UVM_ALLOW_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE(41) +UVM_SET_PREFERRED_LOCATION = UVM_IOCTL_BASE(42) +UVM_UNSET_PREFERRED_LOCATION = UVM_IOCTL_BASE(43) +UVM_ENABLE_READ_DUPLICATION = UVM_IOCTL_BASE(44) +UVM_DISABLE_READ_DUPLICATION = UVM_IOCTL_BASE(45) +UVM_SET_ACCESSED_BY = UVM_IOCTL_BASE(46) +UVM_UNSET_ACCESSED_BY = UVM_IOCTL_BASE(47) +UVM_MIGRATE_FLAG_ASYNC = 0x00000001 +UVM_MIGRATE_FLAG_SKIP_CPU_MAP = 0x00000002 +UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE = 0x00000004 +UVM_MIGRATE_FLAGS_TEST_ALL = (UVM_MIGRATE_FLAG_SKIP_CPU_MAP | UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE) +UVM_MIGRATE_FLAGS_ALL = (UVM_MIGRATE_FLAG_ASYNC | UVM_MIGRATE_FLAGS_TEST_ALL) +UVM_MIGRATE = UVM_IOCTL_BASE(51) +UVM_MIGRATE_RANGE_GROUP = UVM_IOCTL_BASE(53) +UVM_ENABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE(54) +UVM_DISABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE(55) +UVM_TOOLS_INIT_EVENT_TRACKER = UVM_IOCTL_BASE(56) +UVM_TOOLS_SET_NOTIFICATION_THRESHOLD = UVM_IOCTL_BASE(57) +UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS = UVM_IOCTL_BASE(58) +UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS = UVM_IOCTL_BASE(59) +UVM_TOOLS_ENABLE_COUNTERS = UVM_IOCTL_BASE(60) +UVM_TOOLS_DISABLE_COUNTERS = UVM_IOCTL_BASE(61) +UVM_TOOLS_READ_PROCESS_MEMORY = UVM_IOCTL_BASE(62) +UVM_TOOLS_WRITE_PROCESS_MEMORY = UVM_IOCTL_BASE(63) +UVM_TOOLS_GET_PROCESSOR_UUID_TABLE = UVM_IOCTL_BASE(64) +UVM_MAP_DYNAMIC_PARALLELISM_REGION = UVM_IOCTL_BASE(65) +UVM_UNMAP_EXTERNAL = UVM_IOCTL_BASE(66) +UVM_TOOLS_FLUSH_EVENTS = UVM_IOCTL_BASE(67) +UVM_ALLOC_SEMAPHORE_POOL = UVM_IOCTL_BASE(68) +UVM_CLEAN_UP_ZOMBIE_RESOURCES = UVM_IOCTL_BASE(69) +UVM_PAGEABLE_MEM_ACCESS_ON_GPU = UVM_IOCTL_BASE(70) +UVM_POPULATE_PAGEABLE = UVM_IOCTL_BASE(71) +UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED = 0x00000001 +UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK = 0x00000002 +UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL = (UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED | UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK) +UVM_POPULATE_PAGEABLE_FLAGS_ALL = UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL +UVM_VALIDATE_VA_RANGE = UVM_IOCTL_BASE(72) +UVM_CREATE_EXTERNAL_RANGE = UVM_IOCTL_BASE(73) +UVM_MAP_EXTERNAL_SPARSE = UVM_IOCTL_BASE(74) +UVM_MM_INITIALIZE = UVM_IOCTL_BASE(75) +UVM_TOOLS_INIT_EVENT_TRACKER_V2 = UVM_IOCTL_BASE(76) +UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2 = UVM_IOCTL_BASE(77) +UVM_ALLOC_DEVICE_P2P = UVM_IOCTL_BASE(78) +UVM_CLEAR_ALL_ACCESS_COUNTERS = UVM_IOCTL_BASE(79) +UVM_IS_8_SUPPORTED = UVM_IOCTL_BASE(2047) +UVM_INITIALIZE = 0x30000001 +UVM_DEINITIALIZE = 0x30000002 +NV_PFAULT_MMU_ENG_ID_GRAPHICS = 64 +NV_PFAULT_MMU_ENG_ID_DISPLAY = 1 +NV_PFAULT_MMU_ENG_ID_GSP = 2 +NV_PFAULT_MMU_ENG_ID_IFB = 9 +NV_PFAULT_MMU_ENG_ID_FLA = 4 +NV_PFAULT_MMU_ENG_ID_BAR1 = 128 +NV_PFAULT_MMU_ENG_ID_BAR2 = 192 +NV_PFAULT_MMU_ENG_ID_SEC = 14 +NV_PFAULT_MMU_ENG_ID_PERF = 8 +NV_PFAULT_MMU_ENG_ID_NVDEC = 25 +NV_PFAULT_MMU_ENG_ID_NVDEC0 = 25 +NV_PFAULT_MMU_ENG_ID_NVDEC1 = 26 +NV_PFAULT_MMU_ENG_ID_NVDEC2 = 27 +NV_PFAULT_MMU_ENG_ID_NVDEC3 = 28 +NV_PFAULT_MMU_ENG_ID_NVDEC4 = 29 +NV_PFAULT_MMU_ENG_ID_NVJPG0 = 30 +NV_PFAULT_MMU_ENG_ID_GRCOPY = 15 +NV_PFAULT_MMU_ENG_ID_CE0 = 15 +NV_PFAULT_MMU_ENG_ID_CE1 = 16 +NV_PFAULT_MMU_ENG_ID_CE2 = 17 +NV_PFAULT_MMU_ENG_ID_CE3 = 18 +NV_PFAULT_MMU_ENG_ID_CE4 = 19 +NV_PFAULT_MMU_ENG_ID_CE5 = 20 +NV_PFAULT_MMU_ENG_ID_CE6 = 21 +NV_PFAULT_MMU_ENG_ID_CE7 = 22 +NV_PFAULT_MMU_ENG_ID_CE8 = 23 +NV_PFAULT_MMU_ENG_ID_CE9 = 24 +NV_PFAULT_MMU_ENG_ID_PWR_PMU = 6 +NV_PFAULT_MMU_ENG_ID_PTP = 3 +NV_PFAULT_MMU_ENG_ID_NVENC0 = 11 +NV_PFAULT_MMU_ENG_ID_NVENC1 = 12 +NV_PFAULT_MMU_ENG_ID_NVENC2 = 13 +NV_PFAULT_MMU_ENG_ID_OFA0 = 10 +NV_PFAULT_MMU_ENG_ID_PHYSICAL = 31 +NV_PFAULT_MMU_ENG_ID_HOST0 = 32 +NV_PFAULT_MMU_ENG_ID_HOST1 = 33 +NV_PFAULT_MMU_ENG_ID_HOST2 = 34 +NV_PFAULT_MMU_ENG_ID_HOST3 = 35 +NV_PFAULT_MMU_ENG_ID_HOST4 = 36 +NV_PFAULT_MMU_ENG_ID_HOST5 = 37 +NV_PFAULT_MMU_ENG_ID_HOST6 = 38 +NV_PFAULT_MMU_ENG_ID_HOST7 = 39 +NV_PFAULT_MMU_ENG_ID_HOST8 = 40 +NV_PFAULT_MMU_ENG_ID_HOST9 = 41 +NV_PFAULT_MMU_ENG_ID_HOST10 = 42 +NV_PFAULT_MMU_ENG_ID_HOST11 = 43 +NV_PFAULT_MMU_ENG_ID_HOST12 = 44 +NV_PFAULT_MMU_ENG_ID_HOST13 = 45 +NV_PFAULT_MMU_ENG_ID_HOST14 = 46 +NV_PFAULT_MMU_ENG_ID_HOST15 = 47 +NV_PFAULT_MMU_ENG_ID_HOST16 = 48 +NV_PFAULT_MMU_ENG_ID_HOST17 = 49 +NV_PFAULT_MMU_ENG_ID_HOST18 = 50 +NV_PFAULT_MMU_ENG_ID_HOST19 = 51 +NV_PFAULT_MMU_ENG_ID_HOST20 = 52 +NV_PFAULT_MMU_ENG_ID_HOST21 = 53 +NV_PFAULT_MMU_ENG_ID_HOST22 = 54 +NV_PFAULT_MMU_ENG_ID_HOST23 = 55 +NV_PFAULT_MMU_ENG_ID_HOST24 = 56 +NV_PFAULT_MMU_ENG_ID_HOST25 = 57 +NV_PFAULT_MMU_ENG_ID_HOST26 = 58 +NV_PFAULT_MMU_ENG_ID_HOST27 = 59 +NV_PFAULT_MMU_ENG_ID_HOST28 = 60 +NV_PFAULT_MMU_ENG_ID_HOST29 = 61 +NV_PFAULT_MMU_ENG_ID_HOST30 = 62 +NV_PFAULT_MMU_ENG_ID_HOST31 = 63 +NV_PFAULT_MMU_ENG_ID_BAR1_FN0 = 128 +NV_PFAULT_MMU_ENG_ID_BAR1_FN1 = 129 +NV_PFAULT_MMU_ENG_ID_BAR1_FN2 = 130 +NV_PFAULT_MMU_ENG_ID_BAR1_FN3 = 131 +NV_PFAULT_MMU_ENG_ID_BAR1_FN4 = 132 +NV_PFAULT_MMU_ENG_ID_BAR1_FN5 = 133 +NV_PFAULT_MMU_ENG_ID_BAR1_FN6 = 134 +NV_PFAULT_MMU_ENG_ID_BAR1_FN7 = 135 +NV_PFAULT_MMU_ENG_ID_BAR1_FN8 = 136 +NV_PFAULT_MMU_ENG_ID_BAR1_FN9 = 137 +NV_PFAULT_MMU_ENG_ID_BAR1_FN10 = 138 +NV_PFAULT_MMU_ENG_ID_BAR1_FN11 = 139 +NV_PFAULT_MMU_ENG_ID_BAR1_FN12 = 140 +NV_PFAULT_MMU_ENG_ID_BAR1_FN13 = 141 +NV_PFAULT_MMU_ENG_ID_BAR1_FN14 = 142 +NV_PFAULT_MMU_ENG_ID_BAR1_FN15 = 143 +NV_PFAULT_MMU_ENG_ID_BAR1_FN16 = 144 +NV_PFAULT_MMU_ENG_ID_BAR1_FN17 = 145 +NV_PFAULT_MMU_ENG_ID_BAR1_FN18 = 146 +NV_PFAULT_MMU_ENG_ID_BAR1_FN19 = 147 +NV_PFAULT_MMU_ENG_ID_BAR1_FN20 = 148 +NV_PFAULT_MMU_ENG_ID_BAR1_FN21 = 149 +NV_PFAULT_MMU_ENG_ID_BAR1_FN22 = 150 +NV_PFAULT_MMU_ENG_ID_BAR1_FN23 = 151 +NV_PFAULT_MMU_ENG_ID_BAR1_FN24 = 152 +NV_PFAULT_MMU_ENG_ID_BAR1_FN25 = 153 +NV_PFAULT_MMU_ENG_ID_BAR1_FN26 = 154 +NV_PFAULT_MMU_ENG_ID_BAR1_FN27 = 155 +NV_PFAULT_MMU_ENG_ID_BAR1_FN28 = 156 +NV_PFAULT_MMU_ENG_ID_BAR1_FN29 = 157 +NV_PFAULT_MMU_ENG_ID_BAR1_FN30 = 158 +NV_PFAULT_MMU_ENG_ID_BAR1_FN31 = 159 +NV_PFAULT_MMU_ENG_ID_BAR1_FN32 = 160 +NV_PFAULT_MMU_ENG_ID_BAR1_FN33 = 161 +NV_PFAULT_MMU_ENG_ID_BAR1_FN34 = 162 +NV_PFAULT_MMU_ENG_ID_BAR1_FN35 = 163 +NV_PFAULT_MMU_ENG_ID_BAR1_FN36 = 164 +NV_PFAULT_MMU_ENG_ID_BAR1_FN37 = 165 +NV_PFAULT_MMU_ENG_ID_BAR1_FN38 = 166 +NV_PFAULT_MMU_ENG_ID_BAR1_FN39 = 167 +NV_PFAULT_MMU_ENG_ID_BAR1_FN40 = 168 +NV_PFAULT_MMU_ENG_ID_BAR1_FN41 = 169 +NV_PFAULT_MMU_ENG_ID_BAR1_FN42 = 170 +NV_PFAULT_MMU_ENG_ID_BAR1_FN43 = 171 +NV_PFAULT_MMU_ENG_ID_BAR1_FN44 = 172 +NV_PFAULT_MMU_ENG_ID_BAR1_FN45 = 173 +NV_PFAULT_MMU_ENG_ID_BAR1_FN46 = 174 +NV_PFAULT_MMU_ENG_ID_BAR1_FN47 = 175 +NV_PFAULT_MMU_ENG_ID_BAR1_FN48 = 176 +NV_PFAULT_MMU_ENG_ID_BAR1_FN49 = 177 +NV_PFAULT_MMU_ENG_ID_BAR1_FN50 = 178 +NV_PFAULT_MMU_ENG_ID_BAR1_FN51 = 179 +NV_PFAULT_MMU_ENG_ID_BAR1_FN52 = 180 +NV_PFAULT_MMU_ENG_ID_BAR1_FN53 = 181 +NV_PFAULT_MMU_ENG_ID_BAR1_FN54 = 182 +NV_PFAULT_MMU_ENG_ID_BAR1_FN55 = 183 +NV_PFAULT_MMU_ENG_ID_BAR1_FN56 = 184 +NV_PFAULT_MMU_ENG_ID_BAR1_FN57 = 185 +NV_PFAULT_MMU_ENG_ID_BAR1_FN58 = 186 +NV_PFAULT_MMU_ENG_ID_BAR1_FN59 = 187 +NV_PFAULT_MMU_ENG_ID_BAR1_FN60 = 188 +NV_PFAULT_MMU_ENG_ID_BAR1_FN61 = 189 +NV_PFAULT_MMU_ENG_ID_BAR1_FN62 = 190 +NV_PFAULT_MMU_ENG_ID_BAR1_FN63 = 191 +NV_PFAULT_MMU_ENG_ID_BAR2_FN0 = 192 +NV_PFAULT_MMU_ENG_ID_BAR2_FN1 = 193 +NV_PFAULT_MMU_ENG_ID_BAR2_FN2 = 194 +NV_PFAULT_MMU_ENG_ID_BAR2_FN3 = 195 +NV_PFAULT_MMU_ENG_ID_BAR2_FN4 = 196 +NV_PFAULT_MMU_ENG_ID_BAR2_FN5 = 197 +NV_PFAULT_MMU_ENG_ID_BAR2_FN6 = 198 +NV_PFAULT_MMU_ENG_ID_BAR2_FN7 = 199 +NV_PFAULT_MMU_ENG_ID_BAR2_FN8 = 200 +NV_PFAULT_MMU_ENG_ID_BAR2_FN9 = 201 +NV_PFAULT_MMU_ENG_ID_BAR2_FN10 = 202 +NV_PFAULT_MMU_ENG_ID_BAR2_FN11 = 203 +NV_PFAULT_MMU_ENG_ID_BAR2_FN12 = 204 +NV_PFAULT_MMU_ENG_ID_BAR2_FN13 = 205 +NV_PFAULT_MMU_ENG_ID_BAR2_FN14 = 206 +NV_PFAULT_MMU_ENG_ID_BAR2_FN15 = 207 +NV_PFAULT_MMU_ENG_ID_BAR2_FN16 = 208 +NV_PFAULT_MMU_ENG_ID_BAR2_FN17 = 209 +NV_PFAULT_MMU_ENG_ID_BAR2_FN18 = 210 +NV_PFAULT_MMU_ENG_ID_BAR2_FN19 = 211 +NV_PFAULT_MMU_ENG_ID_BAR2_FN20 = 212 +NV_PFAULT_MMU_ENG_ID_BAR2_FN21 = 213 +NV_PFAULT_MMU_ENG_ID_BAR2_FN22 = 214 +NV_PFAULT_MMU_ENG_ID_BAR2_FN23 = 215 +NV_PFAULT_MMU_ENG_ID_BAR2_FN24 = 216 +NV_PFAULT_MMU_ENG_ID_BAR2_FN25 = 217 +NV_PFAULT_MMU_ENG_ID_BAR2_FN26 = 218 +NV_PFAULT_MMU_ENG_ID_BAR2_FN27 = 219 +NV_PFAULT_MMU_ENG_ID_BAR2_FN28 = 220 +NV_PFAULT_MMU_ENG_ID_BAR2_FN29 = 221 +NV_PFAULT_MMU_ENG_ID_BAR2_FN30 = 222 +NV_PFAULT_MMU_ENG_ID_BAR2_FN31 = 223 +NV_PFAULT_MMU_ENG_ID_BAR2_FN32 = 224 +NV_PFAULT_MMU_ENG_ID_BAR2_FN33 = 225 +NV_PFAULT_MMU_ENG_ID_BAR2_FN34 = 226 +NV_PFAULT_MMU_ENG_ID_BAR2_FN35 = 227 +NV_PFAULT_MMU_ENG_ID_BAR2_FN36 = 228 +NV_PFAULT_MMU_ENG_ID_BAR2_FN37 = 229 +NV_PFAULT_MMU_ENG_ID_BAR2_FN38 = 230 +NV_PFAULT_MMU_ENG_ID_BAR2_FN39 = 231 +NV_PFAULT_MMU_ENG_ID_BAR2_FN40 = 232 +NV_PFAULT_MMU_ENG_ID_BAR2_FN41 = 233 +NV_PFAULT_MMU_ENG_ID_BAR2_FN42 = 234 +NV_PFAULT_MMU_ENG_ID_BAR2_FN43 = 235 +NV_PFAULT_MMU_ENG_ID_BAR2_FN44 = 236 +NV_PFAULT_MMU_ENG_ID_BAR2_FN45 = 237 +NV_PFAULT_MMU_ENG_ID_BAR2_FN46 = 238 +NV_PFAULT_MMU_ENG_ID_BAR2_FN47 = 239 +NV_PFAULT_MMU_ENG_ID_BAR2_FN48 = 240 +NV_PFAULT_MMU_ENG_ID_BAR2_FN49 = 241 +NV_PFAULT_MMU_ENG_ID_BAR2_FN50 = 242 +NV_PFAULT_MMU_ENG_ID_BAR2_FN51 = 243 +NV_PFAULT_MMU_ENG_ID_BAR2_FN52 = 244 +NV_PFAULT_MMU_ENG_ID_BAR2_FN53 = 245 +NV_PFAULT_MMU_ENG_ID_BAR2_FN54 = 246 +NV_PFAULT_MMU_ENG_ID_BAR2_FN55 = 247 +NV_PFAULT_MMU_ENG_ID_BAR2_FN56 = 248 +NV_PFAULT_MMU_ENG_ID_BAR2_FN57 = 249 +NV_PFAULT_MMU_ENG_ID_BAR2_FN58 = 250 +NV_PFAULT_MMU_ENG_ID_BAR2_FN59 = 251 +NV_PFAULT_MMU_ENG_ID_BAR2_FN60 = 252 +NV_PFAULT_MMU_ENG_ID_BAR2_FN61 = 253 +NV_PFAULT_MMU_ENG_ID_BAR2_FN62 = 254 +NV_PFAULT_MMU_ENG_ID_BAR2_FN63 = 255 +NV_PFAULT_FAULT_TYPE_PDE = 0x00000000 +NV_PFAULT_FAULT_TYPE_PDE_SIZE = 0x00000001 +NV_PFAULT_FAULT_TYPE_PTE = 0x00000002 +NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION = 0x00000003 +NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK = 0x00000004 +NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION = 0x00000005 +NV_PFAULT_FAULT_TYPE_RO_VIOLATION = 0x00000006 +NV_PFAULT_FAULT_TYPE_WO_VIOLATION = 0x00000007 +NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION = 0x00000008 +NV_PFAULT_FAULT_TYPE_WORK_CREATION = 0x00000009 +NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE = 0x0000000a +NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE = 0x0000000b +NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND = 0x0000000c +NV_PFAULT_FAULT_TYPE_REGION_VIOLATION = 0x0000000d +NV_PFAULT_FAULT_TYPE_POISONED = 0x0000000e +NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION = 0x0000000f +NV_PFAULT_CLIENT_GPC_T1_0 = 0x00000000 +NV_PFAULT_CLIENT_GPC_T1_1 = 0x00000001 +NV_PFAULT_CLIENT_GPC_T1_2 = 0x00000002 +NV_PFAULT_CLIENT_GPC_T1_3 = 0x00000003 +NV_PFAULT_CLIENT_GPC_T1_4 = 0x00000004 +NV_PFAULT_CLIENT_GPC_T1_5 = 0x00000005 +NV_PFAULT_CLIENT_GPC_T1_6 = 0x00000006 +NV_PFAULT_CLIENT_GPC_T1_7 = 0x00000007 +NV_PFAULT_CLIENT_GPC_PE_0 = 0x00000008 +NV_PFAULT_CLIENT_GPC_PE_1 = 0x00000009 +NV_PFAULT_CLIENT_GPC_PE_2 = 0x0000000A +NV_PFAULT_CLIENT_GPC_PE_3 = 0x0000000B +NV_PFAULT_CLIENT_GPC_PE_4 = 0x0000000C +NV_PFAULT_CLIENT_GPC_PE_5 = 0x0000000D +NV_PFAULT_CLIENT_GPC_PE_6 = 0x0000000E +NV_PFAULT_CLIENT_GPC_PE_7 = 0x0000000F +NV_PFAULT_CLIENT_GPC_RAST = 0x00000010 +NV_PFAULT_CLIENT_GPC_GCC = 0x00000011 +NV_PFAULT_CLIENT_GPC_GPCCS = 0x00000012 +NV_PFAULT_CLIENT_GPC_PROP_0 = 0x00000013 +NV_PFAULT_CLIENT_GPC_PROP_1 = 0x00000014 +NV_PFAULT_CLIENT_GPC_PROP_2 = 0x00000015 +NV_PFAULT_CLIENT_GPC_PROP_3 = 0x00000016 +NV_PFAULT_CLIENT_GPC_T1_8 = 0x00000021 +NV_PFAULT_CLIENT_GPC_T1_9 = 0x00000022 +NV_PFAULT_CLIENT_GPC_T1_10 = 0x00000023 +NV_PFAULT_CLIENT_GPC_T1_11 = 0x00000024 +NV_PFAULT_CLIENT_GPC_T1_12 = 0x00000025 +NV_PFAULT_CLIENT_GPC_T1_13 = 0x00000026 +NV_PFAULT_CLIENT_GPC_T1_14 = 0x00000027 +NV_PFAULT_CLIENT_GPC_T1_15 = 0x00000028 +NV_PFAULT_CLIENT_GPC_TPCCS_0 = 0x00000029 +NV_PFAULT_CLIENT_GPC_TPCCS_1 = 0x0000002A +NV_PFAULT_CLIENT_GPC_TPCCS_2 = 0x0000002B +NV_PFAULT_CLIENT_GPC_TPCCS_3 = 0x0000002C +NV_PFAULT_CLIENT_GPC_TPCCS_4 = 0x0000002D +NV_PFAULT_CLIENT_GPC_TPCCS_5 = 0x0000002E +NV_PFAULT_CLIENT_GPC_TPCCS_6 = 0x0000002F +NV_PFAULT_CLIENT_GPC_TPCCS_7 = 0x00000030 +NV_PFAULT_CLIENT_GPC_PE_8 = 0x00000031 +NV_PFAULT_CLIENT_GPC_PE_9 = 0x00000032 +NV_PFAULT_CLIENT_GPC_TPCCS_8 = 0x00000033 +NV_PFAULT_CLIENT_GPC_TPCCS_9 = 0x00000034 +NV_PFAULT_CLIENT_GPC_T1_16 = 0x00000035 +NV_PFAULT_CLIENT_GPC_T1_17 = 0x00000036 +NV_PFAULT_CLIENT_GPC_T1_18 = 0x00000037 +NV_PFAULT_CLIENT_GPC_T1_19 = 0x00000038 +NV_PFAULT_CLIENT_GPC_PE_10 = 0x00000039 +NV_PFAULT_CLIENT_GPC_PE_11 = 0x0000003A +NV_PFAULT_CLIENT_GPC_TPCCS_10 = 0x0000003B +NV_PFAULT_CLIENT_GPC_TPCCS_11 = 0x0000003C +NV_PFAULT_CLIENT_GPC_T1_20 = 0x0000003D +NV_PFAULT_CLIENT_GPC_T1_21 = 0x0000003E +NV_PFAULT_CLIENT_GPC_T1_22 = 0x0000003F +NV_PFAULT_CLIENT_GPC_T1_23 = 0x00000040 +NV_PFAULT_CLIENT_GPC_PE_12 = 0x00000041 +NV_PFAULT_CLIENT_GPC_PE_13 = 0x00000042 +NV_PFAULT_CLIENT_GPC_TPCCS_12 = 0x00000043 +NV_PFAULT_CLIENT_GPC_TPCCS_13 = 0x00000044 +NV_PFAULT_CLIENT_GPC_T1_24 = 0x00000045 +NV_PFAULT_CLIENT_GPC_T1_25 = 0x00000046 +NV_PFAULT_CLIENT_GPC_T1_26 = 0x00000047 +NV_PFAULT_CLIENT_GPC_T1_27 = 0x00000048 +NV_PFAULT_CLIENT_GPC_PE_14 = 0x00000049 +NV_PFAULT_CLIENT_GPC_PE_15 = 0x0000004A +NV_PFAULT_CLIENT_GPC_TPCCS_14 = 0x0000004B +NV_PFAULT_CLIENT_GPC_TPCCS_15 = 0x0000004C +NV_PFAULT_CLIENT_GPC_T1_28 = 0x0000004D +NV_PFAULT_CLIENT_GPC_T1_29 = 0x0000004E +NV_PFAULT_CLIENT_GPC_T1_30 = 0x0000004F +NV_PFAULT_CLIENT_GPC_T1_31 = 0x00000050 +NV_PFAULT_CLIENT_GPC_PE_16 = 0x00000051 +NV_PFAULT_CLIENT_GPC_PE_17 = 0x00000052 +NV_PFAULT_CLIENT_GPC_TPCCS_16 = 0x00000053 +NV_PFAULT_CLIENT_GPC_TPCCS_17 = 0x00000054 +NV_PFAULT_CLIENT_GPC_T1_32 = 0x00000055 +NV_PFAULT_CLIENT_GPC_T1_33 = 0x00000056 +NV_PFAULT_CLIENT_GPC_T1_34 = 0x00000057 +NV_PFAULT_CLIENT_GPC_T1_35 = 0x00000058 +NV_PFAULT_CLIENT_GPC_PE_18 = 0x00000059 +NV_PFAULT_CLIENT_GPC_PE_19 = 0x0000005A +NV_PFAULT_CLIENT_GPC_TPCCS_18 = 0x0000005B +NV_PFAULT_CLIENT_GPC_TPCCS_19 = 0x0000005C +NV_PFAULT_CLIENT_GPC_T1_36 = 0x0000005D +NV_PFAULT_CLIENT_GPC_T1_37 = 0x0000005E +NV_PFAULT_CLIENT_GPC_T1_38 = 0x0000005F +NV_PFAULT_CLIENT_GPC_T1_39 = 0x00000060 +NV_PFAULT_CLIENT_GPC_ROP_0 = 0x00000070 +NV_PFAULT_CLIENT_GPC_ROP_1 = 0x00000071 +NV_PFAULT_CLIENT_GPC_ROP_2 = 0x00000072 +NV_PFAULT_CLIENT_GPC_ROP_3 = 0x00000073 +NV_PFAULT_CLIENT_GPC_GPM = 0x00000017 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 = 0x00000018 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 = 0x00000019 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 = 0x0000001A +NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 = 0x0000001B +NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 = 0x0000001C +NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 = 0x0000001D +NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 = 0x0000001E +NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 = 0x0000001F +NV_PFAULT_CLIENT_GPC_RGG_UTLB = 0x00000020 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 = 0x00000031 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 = 0x00000032 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 = 0x00000033 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 = 0x00000034 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 = 0x00000035 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 = 0x00000036 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 = 0x00000037 +NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 = 0x00000038 +NV_PFAULT_CLIENT_HUB_VIP = 0x00000000 +NV_PFAULT_CLIENT_HUB_CE0 = 0x00000001 +NV_PFAULT_CLIENT_HUB_CE1 = 0x00000002 +NV_PFAULT_CLIENT_HUB_DNISO = 0x00000003 +NV_PFAULT_CLIENT_HUB_DISPNISO = 0x00000003 +NV_PFAULT_CLIENT_HUB_FE0 = 0x00000004 +NV_PFAULT_CLIENT_HUB_FE = 0x00000004 +NV_PFAULT_CLIENT_HUB_FECS0 = 0x00000005 +NV_PFAULT_CLIENT_HUB_FECS = 0x00000005 +NV_PFAULT_CLIENT_HUB_HOST = 0x00000006 +NV_PFAULT_CLIENT_HUB_HOST_CPU = 0x00000007 +NV_PFAULT_CLIENT_HUB_HOST_CPU_NB = 0x00000008 +NV_PFAULT_CLIENT_HUB_ISO = 0x00000009 +NV_PFAULT_CLIENT_HUB_MMU = 0x0000000A +NV_PFAULT_CLIENT_HUB_NVDEC0 = 0x0000000B +NV_PFAULT_CLIENT_HUB_NVDEC = 0x0000000B +NV_PFAULT_CLIENT_HUB_NVENC1 = 0x0000000D +NV_PFAULT_CLIENT_HUB_NISO = 0x0000000E +NV_PFAULT_CLIENT_HUB_ACTRS = 0x0000000E +NV_PFAULT_CLIENT_HUB_P2P = 0x0000000F +NV_PFAULT_CLIENT_HUB_PD = 0x00000010 +NV_PFAULT_CLIENT_HUB_PERF0 = 0x00000011 +NV_PFAULT_CLIENT_HUB_PERF = 0x00000011 +NV_PFAULT_CLIENT_HUB_PMU = 0x00000012 +NV_PFAULT_CLIENT_HUB_RASTERTWOD = 0x00000013 +NV_PFAULT_CLIENT_HUB_SCC = 0x00000014 +NV_PFAULT_CLIENT_HUB_SCC_NB = 0x00000015 +NV_PFAULT_CLIENT_HUB_SEC = 0x00000016 +NV_PFAULT_CLIENT_HUB_SSYNC = 0x00000017 +NV_PFAULT_CLIENT_HUB_GRCOPY = 0x00000018 +NV_PFAULT_CLIENT_HUB_CE2 = 0x00000018 +NV_PFAULT_CLIENT_HUB_XV = 0x00000019 +NV_PFAULT_CLIENT_HUB_MMU_NB = 0x0000001A +NV_PFAULT_CLIENT_HUB_NVENC0 = 0x0000001B +NV_PFAULT_CLIENT_HUB_NVENC = 0x0000001B +NV_PFAULT_CLIENT_HUB_DFALCON = 0x0000001C +NV_PFAULT_CLIENT_HUB_SKED0 = 0x0000001D +NV_PFAULT_CLIENT_HUB_SKED = 0x0000001D +NV_PFAULT_CLIENT_HUB_AFALCON = 0x0000001E +NV_PFAULT_CLIENT_HUB_DONT_CARE = 0x0000001F +NV_PFAULT_CLIENT_HUB_HSCE0 = 0x00000020 +NV_PFAULT_CLIENT_HUB_HSCE1 = 0x00000021 +NV_PFAULT_CLIENT_HUB_HSCE2 = 0x00000022 +NV_PFAULT_CLIENT_HUB_HSCE3 = 0x00000023 +NV_PFAULT_CLIENT_HUB_HSCE4 = 0x00000024 +NV_PFAULT_CLIENT_HUB_HSCE5 = 0x00000025 +NV_PFAULT_CLIENT_HUB_HSCE6 = 0x00000026 +NV_PFAULT_CLIENT_HUB_HSCE7 = 0x00000027 +NV_PFAULT_CLIENT_HUB_HSCE8 = 0x00000028 +NV_PFAULT_CLIENT_HUB_HSCE9 = 0x00000029 +NV_PFAULT_CLIENT_HUB_HSHUB = 0x0000002A +NV_PFAULT_CLIENT_HUB_PTP_X0 = 0x0000002B +NV_PFAULT_CLIENT_HUB_PTP_X1 = 0x0000002C +NV_PFAULT_CLIENT_HUB_PTP_X2 = 0x0000002D +NV_PFAULT_CLIENT_HUB_PTP_X3 = 0x0000002E +NV_PFAULT_CLIENT_HUB_PTP_X4 = 0x0000002F +NV_PFAULT_CLIENT_HUB_PTP_X5 = 0x00000030 +NV_PFAULT_CLIENT_HUB_PTP_X6 = 0x00000031 +NV_PFAULT_CLIENT_HUB_PTP_X7 = 0x00000032 +NV_PFAULT_CLIENT_HUB_NVENC2 = 0x00000033 +NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 = 0x00000034 +NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 = 0x00000035 +NV_PFAULT_CLIENT_HUB_DWBIF = 0x00000036 +NV_PFAULT_CLIENT_HUB_FBFALCON = 0x00000037 +NV_PFAULT_CLIENT_HUB_CE_SHIM = 0x00000038 +NV_PFAULT_CLIENT_HUB_GSP = 0x00000039 +NV_PFAULT_CLIENT_HUB_NVDEC1 = 0x0000003A +NV_PFAULT_CLIENT_HUB_NVDEC2 = 0x0000003B +NV_PFAULT_CLIENT_HUB_NVJPG0 = 0x0000003C +NV_PFAULT_CLIENT_HUB_NVDEC3 = 0x0000003D +NV_PFAULT_CLIENT_HUB_NVDEC4 = 0x0000003E +NV_PFAULT_CLIENT_HUB_OFA0 = 0x0000003F +NV_PFAULT_CLIENT_HUB_HSCE10 = 0x00000040 +NV_PFAULT_CLIENT_HUB_HSCE11 = 0x00000041 +NV_PFAULT_CLIENT_HUB_HSCE12 = 0x00000042 +NV_PFAULT_CLIENT_HUB_HSCE13 = 0x00000043 +NV_PFAULT_CLIENT_HUB_HSCE14 = 0x00000044 +NV_PFAULT_CLIENT_HUB_HSCE15 = 0x00000045 +NV_PFAULT_CLIENT_HUB_PTP_X8 = 0x00000046 +NV_PFAULT_CLIENT_HUB_PTP_X9 = 0x00000047 +NV_PFAULT_CLIENT_HUB_PTP_X10 = 0x00000048 +NV_PFAULT_CLIENT_HUB_PTP_X11 = 0x00000049 +NV_PFAULT_CLIENT_HUB_PTP_X12 = 0x0000004A +NV_PFAULT_CLIENT_HUB_PTP_X13 = 0x0000004B +NV_PFAULT_CLIENT_HUB_PTP_X14 = 0x0000004C +NV_PFAULT_CLIENT_HUB_PTP_X15 = 0x0000004D +NV_PFAULT_CLIENT_HUB_FE1 = 0x0000004E +NV_PFAULT_CLIENT_HUB_FE2 = 0x0000004F +NV_PFAULT_CLIENT_HUB_FE3 = 0x00000050 +NV_PFAULT_CLIENT_HUB_FE4 = 0x00000051 +NV_PFAULT_CLIENT_HUB_FE5 = 0x00000052 +NV_PFAULT_CLIENT_HUB_FE6 = 0x00000053 +NV_PFAULT_CLIENT_HUB_FE7 = 0x00000054 +NV_PFAULT_CLIENT_HUB_FECS1 = 0x00000055 +NV_PFAULT_CLIENT_HUB_FECS2 = 0x00000056 +NV_PFAULT_CLIENT_HUB_FECS3 = 0x00000057 +NV_PFAULT_CLIENT_HUB_FECS4 = 0x00000058 +NV_PFAULT_CLIENT_HUB_FECS5 = 0x00000059 +NV_PFAULT_CLIENT_HUB_FECS6 = 0x0000005A +NV_PFAULT_CLIENT_HUB_FECS7 = 0x0000005B +NV_PFAULT_CLIENT_HUB_SKED1 = 0x0000005C +NV_PFAULT_CLIENT_HUB_SKED2 = 0x0000005D +NV_PFAULT_CLIENT_HUB_SKED3 = 0x0000005E +NV_PFAULT_CLIENT_HUB_SKED4 = 0x0000005F +NV_PFAULT_CLIENT_HUB_SKED5 = 0x00000060 +NV_PFAULT_CLIENT_HUB_SKED6 = 0x00000061 +NV_PFAULT_CLIENT_HUB_SKED7 = 0x00000062 +NV_PFAULT_CLIENT_HUB_ESC = 0x00000063 +NV_PFAULT_ACCESS_TYPE_READ = 0x00000000 +NV_PFAULT_ACCESS_TYPE_WRITE = 0x00000001 +NV_PFAULT_ACCESS_TYPE_ATOMIC = 0x00000002 +NV_PFAULT_ACCESS_TYPE_PREFETCH = 0x00000003 +NV_PFAULT_ACCESS_TYPE_VIRT_READ = 0x00000000 +NV_PFAULT_ACCESS_TYPE_VIRT_WRITE = 0x00000001 +NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC = 0x00000002 +NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 0x00000002 +NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH = 0x00000003 +NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 0x00000004 +NV_PFAULT_ACCESS_TYPE_PHYS_READ = 0x00000008 +NV_PFAULT_ACCESS_TYPE_PHYS_WRITE = 0x00000009 +NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC = 0x0000000a +NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH = 0x0000000b +NV_PFAULT_MMU_CLIENT_TYPE_GPC = 0x00000000 +NV_PFAULT_MMU_CLIENT_TYPE_HUB = 0x00000001 +NV_ESC_RM_ALLOC_MEMORY = 0x27 +NV_ESC_RM_ALLOC_OBJECT = 0x28 +NV_ESC_RM_FREE = 0x29 +NV_ESC_RM_CONTROL = 0x2A +NV_ESC_RM_ALLOC = 0x2B +NV_ESC_RM_CONFIG_GET = 0x32 +NV_ESC_RM_CONFIG_SET = 0x33 +NV_ESC_RM_DUP_OBJECT = 0x34 +NV_ESC_RM_SHARE = 0x35 +NV_ESC_RM_CONFIG_GET_EX = 0x37 +NV_ESC_RM_CONFIG_SET_EX = 0x38 +NV_ESC_RM_I2C_ACCESS = 0x39 +NV_ESC_RM_IDLE_CHANNELS = 0x41 +NV_ESC_RM_VID_HEAP_CONTROL = 0x4A +NV_ESC_RM_ACCESS_REGISTRY = 0x4D +NV_ESC_RM_MAP_MEMORY = 0x4E +NV_ESC_RM_UNMAP_MEMORY = 0x4F +NV_ESC_RM_GET_EVENT_DATA = 0x52 +NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54 +NV_ESC_RM_ADD_VBLANK_CALLBACK = 0x56 +NV_ESC_RM_MAP_MEMORY_DMA = 0x57 +NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58 +NV_ESC_RM_BIND_CONTEXT_DMA = 0x59 +NV_ESC_RM_EXPORT_OBJECT_TO_FD = 0x5C +NV_ESC_RM_IMPORT_OBJECT_FROM_FD = 0x5D +NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5E +NV_ESC_RM_LOCKLESS_DIAGNOSTIC = 0x5F +NV_RM_API_VERSION_STRING_LENGTH = 64 +NV_RM_API_VERSION_CMD_STRICT = 0 +NV_RM_API_VERSION_CMD_RELAXED = '1' +NV_RM_API_VERSION_CMD_QUERY = '2' +NV_RM_API_VERSION_REPLY_UNRECOGNIZED = 0 +NV_RM_API_VERSION_REPLY_RECOGNIZED = 1 +NV_DMABUF_EXPORT_MAX_HANDLES = 128 +NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = 0 +NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = 1 +NV_IOCTL_MAGIC = 'F' +NV_IOCTL_BASE = 200 +NV_ESC_CARD_INFO = (NV_IOCTL_BASE + 0) +NV_ESC_REGISTER_FD = (NV_IOCTL_BASE + 1) +NV_ESC_ALLOC_OS_EVENT = (NV_IOCTL_BASE + 6) +NV_ESC_FREE_OS_EVENT = (NV_IOCTL_BASE + 7) +NV_ESC_STATUS_CODE = (NV_IOCTL_BASE + 9) +NV_ESC_CHECK_VERSION_STR = (NV_IOCTL_BASE + 10) +NV_ESC_IOCTL_XFER_CMD = (NV_IOCTL_BASE + 11) +NV_ESC_ATTACH_GPUS_TO_FD = (NV_IOCTL_BASE + 12) +NV_ESC_QUERY_DEVICE_INTR = (NV_IOCTL_BASE + 13) +NV_ESC_SYS_PARAMS = (NV_IOCTL_BASE + 14) +NV_ESC_EXPORT_TO_DMABUF_FD = (NV_IOCTL_BASE + 17) +NV_ESC_WAIT_OPEN_COMPLETE = (NV_IOCTL_BASE + 18) +__aligned = lambda n: __attribute__((aligned(n))) +NV_ESC_NUMA_INFO = (NV_IOCTL_BASE + 15) +NV_ESC_SET_NUMA_STATUS = (NV_IOCTL_BASE + 16) +NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 +NV_IOCTL_NUMA_STATUS_DISABLED = 0 +NV_IOCTL_NUMA_STATUS_OFFLINE = 1 +NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS = 2 +NV_IOCTL_NUMA_STATUS_ONLINE = 3 +NV_IOCTL_NUMA_STATUS_ONLINE_FAILED = 4 +NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS = 5 +NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED = 6 +NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL = 0x00000000 +NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL = 0x00000001 +NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL = 0x00000002 +NVOS04_FLAGS_VPR_FALSE = 0x00000000 +NVOS04_FLAGS_VPR_TRUE = 0x00000001 +NVOS04_FLAGS_CC_SECURE_FALSE = 0x00000000 +NVOS04_FLAGS_CC_SECURE_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE = 0x00000001 +NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT = 0x00000000 +NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE = 0x00000001 +NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE = 0x00000000 +NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE = 0x00000001 +NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE = 0x00000000 +NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE = 0x00000001 +NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE = 0x00000000 +NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE = 0x00000001 +NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE = 0x00000000 +NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE = 0x00000001 +NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT = 0x00000000 +NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE = 0x00000001 +NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO = 0x00000002 +NVOS04_FLAGS_MAP_CHANNEL_FALSE = 0x00000000 +NVOS04_FLAGS_MAP_CHANNEL_TRUE = 0x00000001 +NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE = 0x00000000 +NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE = 0x00000001 +CC_CHAN_ALLOC_IV_SIZE_DWORD = 3 +CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8 +NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID = (0x906f) +FILE_DEVICE_NV = 0x00008000 +NV_IOCTL_FCT_BASE = 0x00000800 +NVOS_MAX_SUBDEVICES = 8 +UNIFIED_NV_STATUS = 1 +NVOS_STATUS = NV_STATUS +NVOS_STATUS_SUCCESS = NV_OK +NVOS_STATUS_ERROR_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT +NVOS_STATUS_ERROR_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE +NVOS_STATUS_ERROR_GENERIC = NV_ERR_GENERIC +NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER +NVOS_STATUS_ERROR_ILLEGAL_ACTION = NV_ERR_ILLEGAL_ACTION +NVOS_STATUS_ERROR_IN_USE = NV_ERR_STATE_IN_USE +NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES +NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE +NVOS_STATUS_ERROR_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT +NVOS_STATUS_ERROR_INVALID_BASE = NV_ERR_INVALID_BASE +NVOS_STATUS_ERROR_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL +NVOS_STATUS_ERROR_INVALID_CLASS = NV_ERR_INVALID_CLASS +NVOS_STATUS_ERROR_INVALID_CLIENT = NV_ERR_INVALID_CLIENT +NVOS_STATUS_ERROR_INVALID_COMMAND = NV_ERR_INVALID_COMMAND +NVOS_STATUS_ERROR_INVALID_DATA = NV_ERR_INVALID_DATA +NVOS_STATUS_ERROR_INVALID_DEVICE = NV_ERR_INVALID_DEVICE +NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER +NVOS_STATUS_ERROR_INVALID_EVENT = NV_ERR_INVALID_EVENT +NVOS_STATUS_ERROR_INVALID_FLAGS = NV_ERR_INVALID_FLAGS +NVOS_STATUS_ERROR_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION +NVOS_STATUS_ERROR_INVALID_HEAP = NV_ERR_INVALID_HEAP +NVOS_STATUS_ERROR_INVALID_INDEX = NV_ERR_INVALID_INDEX +NVOS_STATUS_ERROR_INVALID_LIMIT = NV_ERR_INVALID_LIMIT +NVOS_STATUS_ERROR_INVALID_METHOD = NV_ERR_INVALID_METHOD +NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER = NV_ERR_BUFFER_TOO_SMALL +NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT +NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE +NVOS_STATUS_ERROR_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW +NVOS_STATUS_ERROR_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD +NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT +NVOS_STATUS_ERROR_INVALID_OFFSET = NV_ERR_INVALID_OFFSET +NVOS_STATUS_ERROR_INVALID_OWNER = NV_ERR_INVALID_OWNER +NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT +NVOS_STATUS_ERROR_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER +NVOS_STATUS_ERROR_INVALID_POINTER = NV_ERR_INVALID_POINTER +NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY +NVOS_STATUS_ERROR_INVALID_STATE = NV_ERR_INVALID_STATE +NVOS_STATUS_ERROR_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH +NVOS_STATUS_ERROR_INVALID_XLATE = NV_ERR_INVALID_XLATE +NVOS_STATUS_ERROR_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING +NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES +NVOS_STATUS_ERROR_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED +NVOS_STATUS_ERROR_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM +NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH +NVOS_STATUS_ERROR_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT +NVOS_STATUS_ERROR_TIMEOUT = NV_ERR_TIMEOUT +NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES +NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED +NVOS_STATUS_ERROR_INVALID_OPERATION = NV_ERR_INVALID_OPERATION +NVOS_STATUS_ERROR_NOT_COMPATIBLE = NV_ERR_NOT_COMPATIBLE +NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED = NV_WARN_MORE_PROCESSING_REQUIRED +NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS = NV_ERR_INSUFFICIENT_PERMISSIONS +NVOS_STATUS_ERROR_TIMEOUT_RETRY = NV_ERR_TIMEOUT_RETRY +NVOS_STATUS_ERROR_NOT_READY = NV_ERR_NOT_READY +NVOS_STATUS_ERROR_GPU_IS_LOST = NV_ERR_GPU_IS_LOST +NVOS_STATUS_ERROR_IN_FULLCHIP_RESET = NV_ERR_GPU_IN_FULLCHIP_RESET +NVOS_STATUS_ERROR_INVALID_LOCK_STATE = NV_ERR_INVALID_LOCK_STATE +NVOS_STATUS_ERROR_INVALID_ADDRESS = NV_ERR_INVALID_ADDRESS +NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL = NV_ERR_INVALID_IRQ_LEVEL +NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED = NV_ERR_MEMORY_TRAINING_FAILED +NVOS_STATUS_ERROR_BUSY_RETRY = NV_ERR_BUSY_RETRY +NVOS_STATUS_ERROR_INSUFFICIENT_POWER = NV_ERR_INSUFFICIENT_POWER +NVOS_STATUS_ERROR_OBJECT_NOT_FOUND = NV_ERR_OBJECT_NOT_FOUND +NVOS_STATUS_ERROR_RESOURCE_LOST = NV_ERR_RESOURCE_LOST +NVOS_STATUS_ERROR_BUFFER_TOO_SMALL = NV_ERR_BUFFER_TOO_SMALL +NVOS_STATUS_ERROR_RESET_REQUIRED = NV_ERR_RESET_REQUIRED +NVOS_STATUS_ERROR_INVALID_REQUEST = NV_ERR_INVALID_REQUEST +NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION = NV_ERR_PRIV_SEC_VIOLATION +NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE = NV_ERR_GPU_IN_DEBUG_MODE +NVOS_STATUS_ERROR_ALREADY_SIGNALLED = NV_ERR_ALREADY_SIGNALLED +NV01_FREE = (0x00000000) +NV01_ROOT = (0x0) +NV01_ROOT_NON_PRIV = (0x00000001) +NV01_ROOT_CLIENT = (0x00000041) +NV01_ALLOC_MEMORY = (0x00000002) +NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS = (0x00000000) +NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS = (0x00000001) +NVOS02_FLAGS_LOCATION_PCI = (0x00000000) +NVOS02_FLAGS_LOCATION_VIDMEM = (0x00000002) +NVOS02_FLAGS_COHERENCY_UNCACHED = (0x00000000) +NVOS02_FLAGS_COHERENCY_CACHED = (0x00000001) +NVOS02_FLAGS_COHERENCY_WRITE_COMBINE = (0x00000002) +NVOS02_FLAGS_COHERENCY_WRITE_THROUGH = (0x00000003) +NVOS02_FLAGS_COHERENCY_WRITE_PROTECT = (0x00000004) +NVOS02_FLAGS_COHERENCY_WRITE_BACK = (0x00000005) +NVOS02_FLAGS_ALLOC_NONE = (0x00000001) +NVOS02_FLAGS_GPU_CACHEABLE_NO = (0x00000000) +NVOS02_FLAGS_GPU_CACHEABLE_YES = (0x00000001) +NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP = (0x00000000) +NVOS02_FLAGS_KERNEL_MAPPING_MAP = (0x00000001) +NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO = (0x00000000) +NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES = (0x00000001) +NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO = (0x00000000) +NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES = (0x00000001) +NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO = (0x00000000) +NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES = (0x00000001) +NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT = (0x00000000) +NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED = (0x00000001) +NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE = (0x00000001) +NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT = (0x00000000) +NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED = (0x00000001) +NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED = (0x00000002) +NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = (0x00000000) +NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = (0x00000001) +NVOS02_FLAGS_MAPPING_DEFAULT = (0x00000000) +NVOS02_FLAGS_MAPPING_NO_MAP = (0x00000001) +NVOS02_FLAGS_MAPPING_NEVER_MAP = (0x00000002) +NVOS03_FLAGS_ACCESS_READ_WRITE = (0x00000000) +NVOS03_FLAGS_ACCESS_READ_ONLY = (0x00000001) +NVOS03_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) +NVOS03_FLAGS_PREALLOCATE_DISABLE = (0x00000000) +NVOS03_FLAGS_PREALLOCATE_ENABLE = (0x00000001) +NVOS03_FLAGS_GPU_MAPPABLE_DISABLE = (0x00000000) +NVOS03_FLAGS_GPU_MAPPABLE_ENABLE = (0x00000001) +NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE = (0x00000000) +NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE = (0x00000001) +NVOS03_FLAGS_PTE_KIND_NONE = (0x00000000) +NVOS03_FLAGS_PTE_KIND_BL = (0x00000001) +NVOS03_FLAGS_PTE_KIND_PITCH = (0x00000002) +NVOS03_FLAGS_TYPE_NOTIFIER = (0x00000001) +NVOS03_FLAGS_MAPPING_NONE = (0x00000000) +NVOS03_FLAGS_MAPPING_KERNEL = (0x00000001) +NVOS03_FLAGS_CACHE_SNOOP_ENABLE = (0x00000000) +NVOS03_FLAGS_CACHE_SNOOP_DISABLE = (0x00000001) +NVOS03_FLAGS_HASH_TABLE_ENABLE = (0x00000000) +NVOS03_FLAGS_HASH_TABLE_DISABLE = (0x00000001) +NV01_ALLOC_OBJECT = (0x00000005) +NV01_EVENT_KERNEL_CALLBACK = (0x00000078) +NV01_EVENT_OS_EVENT = (0x00000079) +NV01_EVENT_WIN32_EVENT = NV01_EVENT_OS_EVENT +NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007E) +NV01_EVENT_BROADCAST = (0x80000000) +NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION = (0x40000000) +NV01_EVENT_SUBDEVICE_SPECIFIC = (0x20000000) +NV01_EVENT_WITHOUT_EVENT_DATA = (0x10000000) +NV01_EVENT_NONSTALL_INTR = (0x08000000) +NV01_EVENT_CLIENT_RM = (0x04000000) +NV04_I2C_ACCESS = (0x00000013) +NVOS_I2C_ACCESS_MAX_BUFFER_SIZE = 2048 +NVOS20_COMMAND_unused0001 = 0x0001 +NVOS20_COMMAND_unused0002 = 0x0002 +NVOS20_COMMAND_STRING_PRINT = 0x0003 +NV04_ALLOC = (0x00000015) +NVOS64_FLAGS_NONE = (0x00000000) +NVOS64_FLAGS_FINN_SERIALIZED = (0x00000001) +NVOS65_PARAMETERS_VERSION_MAGIC = 0x77FEF81E +NV04_IDLE_CHANNELS = (0x0000001E) +NVOS30_FLAGS_BEHAVIOR_SPIN = (0x00000000) +NVOS30_FLAGS_BEHAVIOR_SLEEP = (0x00000001) +NVOS30_FLAGS_BEHAVIOR_QUERY = (0x00000002) +NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK = (0x00000003) +NVOS30_FLAGS_CHANNEL_LIST = (0x00000000) +NVOS30_FLAGS_CHANNEL_SINGLE = (0x00000001) +NVOS30_FLAGS_IDLE_PUSH_BUFFER = (0x00000001) +NVOS30_FLAGS_IDLE_CACHE1 = (0x00000002) +NVOS30_FLAGS_IDLE_GRAPHICS = (0x00000004) +NVOS30_FLAGS_IDLE_MPEG = (0x00000008) +NVOS30_FLAGS_IDLE_MOTION_ESTIMATION = (0x00000010) +NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR = (0x00000020) +NVOS30_FLAGS_IDLE_MSPDEC = (0x00000020) +NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR = (0x00000040) +NVOS30_FLAGS_IDLE_MSVLD = (0x00000040) +NVOS30_FLAGS_IDLE_NVDEC0 = NVOS30_FLAGS_IDLE_MSVLD +NVOS30_FLAGS_IDLE_CIPHER_DMA = (0x00000080) +NVOS30_FLAGS_IDLE_SEC = (0x00000080) +NVOS30_FLAGS_IDLE_CALLBACKS = (0x00000100) +NVOS30_FLAGS_IDLE_MSPPP = (0x00000200) +NVOS30_FLAGS_IDLE_CE0 = (0x00000400) +NVOS30_FLAGS_IDLE_CE1 = (0x00000800) +NVOS30_FLAGS_IDLE_CE2 = (0x00001000) +NVOS30_FLAGS_IDLE_CE3 = (0x00002000) +NVOS30_FLAGS_IDLE_CE4 = (0x00004000) +NVOS30_FLAGS_IDLE_CE5 = (0x00008000) +NVOS30_FLAGS_IDLE_VIC = (0x00010000) +NVOS30_FLAGS_IDLE_MSENC = (0x00020000) +NVOS30_FLAGS_IDLE_NVENC0 = NVOS30_FLAGS_IDLE_MSENC +NVOS30_FLAGS_IDLE_NVENC1 = (0x00040000) +NVOS30_FLAGS_IDLE_NVENC2 = (0x00080000) +NVOS30_FLAGS_IDLE_NVJPG = (0x00100000) +NVOS30_FLAGS_IDLE_NVDEC1 = (0x00200000) +NVOS30_FLAGS_IDLE_NVDEC2 = (0x00400000) +NVOS30_FLAGS_IDLE_ACTIVECHANNELS = (0x00800000) +NVOS30_FLAGS_IDLE_ALL_ENGINES = (NVOS30_FLAGS_IDLE_GRAPHICS | NVOS30_FLAGS_IDLE_MPEG | NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | NVOS30_FLAGS_IDLE_CIPHER_DMA | NVOS30_FLAGS_IDLE_MSPDEC | NVOS30_FLAGS_IDLE_NVDEC0 | NVOS30_FLAGS_IDLE_SEC | NVOS30_FLAGS_IDLE_MSPPP | NVOS30_FLAGS_IDLE_CE0 | NVOS30_FLAGS_IDLE_CE1 | NVOS30_FLAGS_IDLE_CE2 | NVOS30_FLAGS_IDLE_CE3 | NVOS30_FLAGS_IDLE_CE4 | NVOS30_FLAGS_IDLE_CE5 | NVOS30_FLAGS_IDLE_NVENC0 | NVOS30_FLAGS_IDLE_NVENC1 | NVOS30_FLAGS_IDLE_NVENC2 | NVOS30_FLAGS_IDLE_VIC | NVOS30_FLAGS_IDLE_NVJPG | NVOS30_FLAGS_IDLE_NVDEC1 | NVOS30_FLAGS_IDLE_NVDEC2) +NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO = (0x00000000) +NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES = (0x00000001) +NV04_VID_HEAP_CONTROL = (0x00000020) +NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS = 0 +NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY = 1 +NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY = 2 +NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR = 3 +NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE = 4 +NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR = 5 +NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR = 6 +NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS = 7 +NVOS32_FUNCTION_ALLOC_SIZE = 2 +NVOS32_FUNCTION_FREE = 3 +NVOS32_FUNCTION_INFO = 5 +NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT = 6 +NVOS32_FUNCTION_DUMP = 11 +NVOS32_FUNCTION_ALLOC_SIZE_RANGE = 14 +NVOS32_FUNCTION_REACQUIRE_COMPR = 15 +NVOS32_FUNCTION_RELEASE_COMPR = 16 +NVOS32_FUNCTION_GET_MEM_ALIGNMENT = 18 +NVOS32_FUNCTION_HW_ALLOC = 19 +NVOS32_FUNCTION_HW_FREE = 20 +NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR = 27 +NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU = (0x00000001) +NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP = 0 +NVAL_MAX_BANKS = (4) +NVAL_MAP_DIRECTION_DOWN = 0x00000000 +NVAL_MAP_DIRECTION_UP = 0x00000001 +NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR = 1 +NVOS32_DELETE_RESOURCES_ALL = 0 +NVOS32_TYPE_IMAGE = 0 +NVOS32_TYPE_DEPTH = 1 +NVOS32_TYPE_TEXTURE = 2 +NVOS32_TYPE_VIDEO = 3 +NVOS32_TYPE_FONT = 4 +NVOS32_TYPE_CURSOR = 5 +NVOS32_TYPE_DMA = 6 +NVOS32_TYPE_INSTANCE = 7 +NVOS32_TYPE_PRIMARY = 8 +NVOS32_TYPE_ZCULL = 9 +NVOS32_TYPE_UNUSED = 10 +NVOS32_TYPE_SHADER_PROGRAM = 11 +NVOS32_TYPE_OWNER_RM = 12 +NVOS32_TYPE_NOTIFIER = 13 +NVOS32_TYPE_RESERVED = 14 +NVOS32_TYPE_PMA = 15 +NVOS32_TYPE_STENCIL = 16 +NVOS32_NUM_MEM_TYPES = 17 +NVOS32_ATTR_NONE = 0x00000000 +NVOS32_ATTR_DEPTH_UNKNOWN = 0x00000000 +NVOS32_ATTR_DEPTH_8 = 0x00000001 +NVOS32_ATTR_DEPTH_16 = 0x00000002 +NVOS32_ATTR_DEPTH_24 = 0x00000003 +NVOS32_ATTR_DEPTH_32 = 0x00000004 +NVOS32_ATTR_DEPTH_64 = 0x00000005 +NVOS32_ATTR_DEPTH_128 = 0x00000006 +NVOS32_ATTR_COMPR_COVG_DEFAULT = 0x00000000 +NVOS32_ATTR_COMPR_COVG_PROVIDED = 0x00000001 +NVOS32_ATTR_AA_SAMPLES_1 = 0x00000000 +NVOS32_ATTR_AA_SAMPLES_2 = 0x00000001 +NVOS32_ATTR_AA_SAMPLES_4 = 0x00000002 +NVOS32_ATTR_AA_SAMPLES_4_ROTATED = 0x00000003 +NVOS32_ATTR_AA_SAMPLES_6 = 0x00000004 +NVOS32_ATTR_AA_SAMPLES_8 = 0x00000005 +NVOS32_ATTR_AA_SAMPLES_16 = 0x00000006 +NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 = 0x00000007 +NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 = 0x00000008 +NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 = 0x00000009 +NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 = 0x0000000A +NVOS32_ATTR_ZCULL_NONE = 0x00000000 +NVOS32_ATTR_ZCULL_REQUIRED = 0x00000001 +NVOS32_ATTR_ZCULL_ANY = 0x00000002 +NVOS32_ATTR_ZCULL_SHARED = 0x00000003 +NVOS32_ATTR_COMPR_NONE = 0x00000000 +NVOS32_ATTR_COMPR_REQUIRED = 0x00000001 +NVOS32_ATTR_COMPR_ANY = 0x00000002 +NVOS32_ATTR_COMPR_PLC_REQUIRED = NVOS32_ATTR_COMPR_REQUIRED +NVOS32_ATTR_COMPR_PLC_ANY = NVOS32_ATTR_COMPR_ANY +NVOS32_ATTR_COMPR_DISABLE_PLC_ANY = 0x00000003 +NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO = 0x00000000 +NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES = 0x00000001 +NVOS32_ATTR_FORMAT_LOW_FIELD = 16 +NVOS32_ATTR_FORMAT_HIGH_FIELD = 17 +NVOS32_ATTR_FORMAT_PITCH = 0x00000000 +NVOS32_ATTR_FORMAT_SWIZZLED = 0x00000001 +NVOS32_ATTR_FORMAT_BLOCK_LINEAR = 0x00000002 +NVOS32_ATTR_Z_TYPE_FIXED = 0x00000000 +NVOS32_ATTR_Z_TYPE_FLOAT = 0x00000001 +NVOS32_ATTR_ZS_PACKING_S8 = 0x00000000 +NVOS32_ATTR_ZS_PACKING_Z24S8 = 0x00000000 +NVOS32_ATTR_ZS_PACKING_S8Z24 = 0x00000001 +NVOS32_ATTR_ZS_PACKING_Z32 = 0x00000002 +NVOS32_ATTR_ZS_PACKING_Z24X8 = 0x00000003 +NVOS32_ATTR_ZS_PACKING_X8Z24 = 0x00000004 +NVOS32_ATTR_ZS_PACKING_Z32_X24S8 = 0x00000005 +NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 = 0x00000006 +NVOS32_ATTR_ZS_PACKING_Z16 = 0x00000007 +NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 = 0x00000000 +NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 = 0x00000001 +NVOS32_ATTR_PAGE_SIZE_DEFAULT = 0x00000000 +NVOS32_ATTR_PAGE_SIZE_4KB = 0x00000001 +NVOS32_ATTR_PAGE_SIZE_BIG = 0x00000002 +NVOS32_ATTR_PAGE_SIZE_HUGE = 0x00000003 +NVOS32_ATTR_LOCATION_VIDMEM = 0x00000000 +NVOS32_ATTR_LOCATION_PCI = 0x00000001 +NVOS32_ATTR_LOCATION_ANY = 0x00000003 +NVOS32_ATTR_PHYSICALITY_DEFAULT = 0x00000000 +NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS = 0x00000001 +NVOS32_ATTR_PHYSICALITY_CONTIGUOUS = 0x00000002 +NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS = 0x00000003 +NVOS32_ATTR_COHERENCY_UNCACHED = 0x00000000 +NVOS32_ATTR_COHERENCY_CACHED = 0x00000001 +NVOS32_ATTR_COHERENCY_WRITE_COMBINE = 0x00000002 +NVOS32_ATTR_COHERENCY_WRITE_THROUGH = 0x00000003 +NVOS32_ATTR_COHERENCY_WRITE_PROTECT = 0x00000004 +NVOS32_ATTR_COHERENCY_WRITE_BACK = 0x00000005 +NVOS32_ATTR2_NONE = 0x00000000 +NVOS32_ATTR2_ZBC_DEFAULT = 0x00000000 +NVOS32_ATTR2_ZBC_PREFER_NO_ZBC = 0x00000001 +NVOS32_ATTR2_ZBC_PREFER_ZBC = 0x00000002 +NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC = 0x00000003 +NVOS32_ATTR2_ZBC_INVALID = 0x00000003 +NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT = 0x00000000 +NVOS32_ATTR2_GPU_CACHEABLE_YES = 0x00000001 +NVOS32_ATTR2_GPU_CACHEABLE_NO = 0x00000002 +NVOS32_ATTR2_GPU_CACHEABLE_INVALID = 0x00000003 +NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT = 0x00000000 +NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES = 0x00000001 +NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO = 0x00000002 +NVOS32_ATTR2_32BIT_POINTER_DISABLE = 0x00000000 +NVOS32_ATTR2_32BIT_POINTER_ENABLE = 0x00000001 +NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO = 0x00000000 +NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES = 0x00000001 +NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT = 0x00000000 +NVOS32_ATTR2_SMMU_ON_GPU_DISABLE = 0x00000001 +NVOS32_ATTR2_SMMU_ON_GPU_ENABLE = 0x00000002 +NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE = 0x00000000 +NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE = 0x00000001 +NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF = 0x0 +NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON = 0x1 +NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT = NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF +NVOS32_ATTR2_PRIORITY_DEFAULT = 0x0 +NVOS32_ATTR2_PRIORITY_HIGH = 0x1 +NVOS32_ATTR2_PRIORITY_LOW = 0x2 +NVOS32_ATTR2_INTERNAL_NO = 0x0 +NVOS32_ATTR2_INTERNAL_YES = 0x1 +NVOS32_ATTR2_PREFER_2C_NO = 0x00000000 +NVOS32_ATTR2_PREFER_2C_YES = 0x00000001 +NVOS32_ATTR2_NISO_DISPLAY_NO = 0x00000000 +NVOS32_ATTR2_NISO_DISPLAY_YES = 0x00000001 +NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO = 0x00000000 +NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES = 0x00000001 +NVOS32_ATTR2_ISO_NO = 0x00000000 +NVOS32_ATTR2_ISO_YES = 0x00000001 +NVOS32_ATTR2_BLACKLIST_ON = 0x00000000 +NVOS32_ATTR2_BLACKLIST_OFF = 0x00000001 +NVOS32_ATTR2_PAGE_OFFLINING_ON = 0x00000000 +NVOS32_ATTR2_PAGE_OFFLINING_OFF = 0x00000001 +NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT = 0x00000000 +NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB = 0x00000001 +NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB = 0x00000002 +NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB = 0x00000003 +NVOS32_ATTR2_PROTECTION_USER_READ_WRITE = 0x00000000 +NVOS32_ATTR2_PROTECTION_USER_READ_ONLY = 0x00000001 +NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE = 0x00000000 +NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY = 0x00000001 +NVOS32_ATTR2_USE_EGM_FALSE = 0x00000000 +NVOS32_ATTR2_USE_EGM_TRUE = 0x00000001 +NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT = 0x00000000 +NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED = 0x00000001 +NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED = 0x00000002 +NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO = 0x00000000 +NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES = 0x00000001 +NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = 0x00000000 +NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = 0x00000001 +NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT = 0x00000001 +NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP = 0x00000002 +NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN = 0x00000004 +NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE = 0x00000008 +NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE = 0x00000010 +NVOS32_ALLOC_FLAGS_BANK_HINT = 0x00000020 +NVOS32_ALLOC_FLAGS_BANK_FORCE = 0x00000040 +NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT = 0x00000080 +NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE = 0x00000100 +NVOS32_ALLOC_FLAGS_BANK_GROW_UP = 0x00000000 +NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN = 0x00000200 +NVOS32_ALLOC_FLAGS_LAZY = 0x00000400 +NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC = 0x00000800 +NVOS32_ALLOC_FLAGS_NO_SCANOUT = 0x00001000 +NVOS32_ALLOC_FLAGS_PITCH_FORCE = 0x00002000 +NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00004000 +NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED = 0x00008000 +NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM = 0x00010000 +NVOS32_ALLOC_FLAGS_USE_BEGIN_END = 0x00020000 +NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED = 0x00040000 +NVOS32_ALLOC_FLAGS_VIRTUAL = 0x00080000 +NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX = 0x00100000 +NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED = 0x00200000 +NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED = 0x00400000 +NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE = 0x00800000 +NVOS32_ALLOC_FLAGS_PROTECTED = 0x01000000 +NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP = 0x02000000 +NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE = 0x02000000 +NVOS32_ALLOC_FLAGS_SPARSE = 0x04000000 +NVOS32_ALLOC_FLAGS_USER_READ_ONLY = 0x04000000 +NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY = 0x08000000 +NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED = 0x08000000 +NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC = 0x10000000 +NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY = 0x20000000 +NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD = 0x40000000 +NVOS32_ALLOC_FLAGS_WPR1 = 0x40000000 +NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X = 0x80000000 +NVOS32_ALLOC_FLAGS_WPR2 = 0x80000000 +NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC = 0x00000001 +NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB = 0x00000004 +NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE = NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE +NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY = ( NVOS32_ALLOC_FLAGS_VIRTUAL | NVOS32_ALLOC_FLAGS_LAZY | NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | NVOS32_ALLOC_FLAGS_SPARSE | NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY ) +NVOS32_ALLOC_COMPR_COVG_SCALE = 10 +NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT = 0x00000000 +NVOS32_ALLOC_COMPR_COVG_BITS_1 = 0x00000001 +NVOS32_ALLOC_COMPR_COVG_BITS_2 = 0x00000002 +NVOS32_ALLOC_COMPR_COVG_BITS_4 = 0x00000003 +NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z = 0x00000000 +NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z = 0x00000002 +NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS = 0x00000003 +NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW = 0x00000000 +NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW = 0x00000001 +NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT = 0x00000000 +NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT = 0x00000000 +NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF = 0x00000000 +NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED = 0x00000001 +NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN = 0x00000002 +NVOS32_REALLOC_FLAGS_GROW_ALLOCATION = 0x00000000 +NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION = 0x00000001 +NVOS32_REALLOC_FLAGS_REALLOC_UP = 0x00000000 +NVOS32_REALLOC_FLAGS_REALLOC_DOWN = 0x00000002 +NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 +NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001 +NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00000001 +NVOS32_DUMP_FLAGS_TYPE_FB = 0x00000000 +NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD = 0x00000001 +NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA = 0x00000002 +NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE = 0x00000003 +NVOS32_BLOCK_TYPE_FREE = 0xFFFFFFFF +NVOS32_INVALID_BLOCK_FREE_OFFSET = 0xFFFFFFFF +NVOS32_MEM_TAG_NONE = 0x00000000 +NV04_MAP_MEMORY = (0x00000021) +NV04_MAP_MEMORY_FLAGS_NONE = (0x00000000) +NV04_MAP_MEMORY_FLAGS_USER = (0x00004000) +NVOS33_FLAGS_ACCESS_READ_WRITE = (0x00000000) +NVOS33_FLAGS_ACCESS_READ_ONLY = (0x00000001) +NVOS33_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) +NVOS33_FLAGS_PERSISTENT_DISABLE = (0x00000000) +NVOS33_FLAGS_PERSISTENT_ENABLE = (0x00000001) +NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE = (0x00000000) +NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE = (0x00000001) +NVOS33_FLAGS_MEM_SPACE_CLIENT = (0x00000000) +NVOS33_FLAGS_MEM_SPACE_USER = (0x00000001) +NVOS33_FLAGS_MAPPING_DEFAULT = (0x00000000) +NVOS33_FLAGS_MAPPING_DIRECT = (0x00000001) +NVOS33_FLAGS_MAPPING_REFLECTED = (0x00000002) +NVOS33_FLAGS_FIFO_MAPPING_DEFAULT = (0x00000000) +NVOS33_FLAGS_FIFO_MAPPING_ENABLE = (0x00000001) +NVOS33_FLAGS_MAP_FIXED_DISABLE = (0x00000000) +NVOS33_FLAGS_MAP_FIXED_ENABLE = (0x00000001) +NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE = (0x00000000) +NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE = (0x00000001) +NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE = (0x00000000) +NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE = (0x00000001) +NVOS33_FLAGS_CACHING_TYPE_CACHED = 0 +NVOS33_FLAGS_CACHING_TYPE_UNCACHED = 1 +NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED = 2 +NVOS33_FLAGS_CACHING_TYPE_WRITEBACK = 5 +NVOS33_FLAGS_CACHING_TYPE_DEFAULT = 6 +NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK = 7 +NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO = (0x00000000) +NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES = (0x00000001) +NV04_UNMAP_MEMORY = (0x00000022) +NV04_ACCESS_REGISTRY = (0x00000026) +NVOS38_ACCESS_TYPE_READ_DWORD = 1 +NVOS38_ACCESS_TYPE_WRITE_DWORD = 2 +NVOS38_ACCESS_TYPE_READ_BINARY = 6 +NVOS38_ACCESS_TYPE_WRITE_BINARY = 7 +NVOS38_MAX_REGISTRY_STRING_LENGTH = 256 +NVOS38_MAX_REGISTRY_BINARY_LENGTH = 256 +NV04_ALLOC_CONTEXT_DMA = (0x00000027) +NV04_GET_EVENT_DATA = (0x00000028) +NVSIM01_BUS_XACT = (0x0000002C) +NV04_MAP_MEMORY_DMA = (0x0000002E) +NVOS46_FLAGS_ACCESS_READ_WRITE = (0x00000000) +NVOS46_FLAGS_ACCESS_READ_ONLY = (0x00000001) +NVOS46_FLAGS_ACCESS_WRITE_ONLY = (0x00000002) +NVOS46_FLAGS_32BIT_POINTER_DISABLE = (0x00000000) +NVOS46_FLAGS_32BIT_POINTER_ENABLE = (0x00000001) +NVOS46_FLAGS_PAGE_KIND_PHYSICAL = (0x00000000) +NVOS46_FLAGS_PAGE_KIND_VIRTUAL = (0x00000001) +NVOS46_FLAGS_CACHE_SNOOP_DISABLE = (0x00000000) +NVOS46_FLAGS_CACHE_SNOOP_ENABLE = (0x00000001) +NVOS46_FLAGS_KERNEL_MAPPING_NONE = (0x00000000) +NVOS46_FLAGS_KERNEL_MAPPING_ENABLE = (0x00000001) +NVOS46_FLAGS_SHADER_ACCESS_DEFAULT = (0x00000000) +NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) +NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) +NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000003) +NVOS46_FLAGS_PAGE_SIZE_DEFAULT = (0x00000000) +NVOS46_FLAGS_PAGE_SIZE_4KB = (0x00000001) +NVOS46_FLAGS_PAGE_SIZE_BIG = (0x00000002) +NVOS46_FLAGS_PAGE_SIZE_BOTH = (0x00000003) +NVOS46_FLAGS_PAGE_SIZE_HUGE = (0x00000004) +NVOS46_FLAGS_PAGE_SIZE_512M = (0x00000005) +NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT = (0x00000000) +NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT = (0x00000001) +NVOS46_FLAGS_DMA_OFFSET_GROWS_UP = (0x00000000) +NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN = (0x00000001) +NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE = (0x00000000) +NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE = (0x00000001) +NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE = (0x00000000) +NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE = (0x00000001) +NVOS46_FLAGS_P2P_ENABLE_NO = (0x00000000) +NVOS46_FLAGS_P2P_ENABLE_YES = (0x00000001) +NVOS46_FLAGS_P2P_ENABLE_NONE = NVOS46_FLAGS_P2P_ENABLE_NO +NVOS46_FLAGS_P2P_ENABLE_SLI = NVOS46_FLAGS_P2P_ENABLE_YES +NVOS46_FLAGS_P2P_ENABLE_NOSLI = (0x00000002) +NVOS46_FLAGS_TLB_LOCK_DISABLE = (0x00000000) +NVOS46_FLAGS_TLB_LOCK_ENABLE = (0x00000001) +NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE = (0x00000000) +NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE = (0x00000001) +NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE = (0x00000000) +NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE = (0x00000001) +NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) +NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) +NV04_UNMAP_MEMORY_DMA = (0x0000002F) +NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000) +NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001) +NV04_BIND_CONTEXT_DMA = (0x00000031) +NV04_CONTROL = (0x00000036) +NVOS54_FLAGS_NONE = (0x00000000) +NVOS54_FLAGS_IRQL_RAISED = (0x00000001) +NVOS54_FLAGS_LOCK_BYPASS = (0x00000002) +NVOS54_FLAGS_FINN_SERIALIZED = (0x00000004) +NV04_DUP_OBJECT = (0x00000037) +NV04_DUP_HANDLE_FLAGS_NONE = (0x00000000) +NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE = (0x00000001) +NV04_UPDATE_DEVICE_MAPPING_INFO = (0x00000038) +NV04_SHARE = (0x0000003E) +NV_DEVICE_ALLOCATION_SZNAME_MAXLEN = 128 +NV_DEVICE_ALLOCATION_FLAGS_NONE = (0x00000000) +NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY = (0x00000001) +NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (0x00000002) +NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (0x00000004) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE = (0x00000008) +NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE = (0x00000010) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET = (0x00000020) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT = (0x00000100) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k = (0x00000200) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k = (0x00000400) +NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS = (0x00000800) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED = (0x00000040) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED = (0x00001000) +NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE = (0x00002000) +NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT = (0x00004000) +NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET = (0x00008000) +NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES = (0x00000000) +NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE = (0x00000001) +NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES = (0x00000002) +NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR = 0x00000000 +NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN = 0x00000001 +NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS = 0x00000002 +NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 = 3 +NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE = 0x1 +NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE = 0x0 +NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES = 0x00000000 +NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO = 0x00000001 +NV_SWRUNLIST_QOS_INTR_NONE = 0x00000000 +NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE = (0x00000000) +NV_VP_ALLOCATION_FLAGS_STATIC_UCODE = (0x00000001) +NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE = (0x00000002) +NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO = (0x00000000) +NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO = (0x00000001) +NV04_ADD_VBLANK_CALLBACK = (0x0000003D) +NV_VASPACE_ALLOCATION_FLAGS_NONE = (0x00000000) +NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = BIT(0) +NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = BIT(1) +NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT = BIT(2) +NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED = BIT(3) +NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS = BIT(4) +NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED = BIT(5) +NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING = BIT(6) +NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT = BIT(7) +NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS = BIT(8) +NV_VASPACE_ALLOCATION_FLAGS_IS_FLA = BIT(9) +NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL = BIT(10) +NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE = BIT(11) +NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET = BIT(12) +NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED = BIT(13) +NV_VASPACE_ALLOCATION_INDEX_GPU_NEW = 0x00 +NV_VASPACE_ALLOCATION_INDEX_GPU_HOST = 0x01 +NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL = 0x02 +NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE = 0x03 +NV_VASPACE_ALLOCATION_INDEX_GPU_FLA = 0x04 +NV_VASPACE_ALLOCATION_INDEX_GPU_MAX = 0x05 +NV_VASPACE_BIG_PAGE_SIZE_64K = (64 * 1024) +NV_VASPACE_BIG_PAGE_SIZE_128K = (128 * 1024) +NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC = (0x00000000) +NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC = (0x00000001) +NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED = (0x00000002) +NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER = (0x00000003) +NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS = (0x00000001) +NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL = (0x00000000) +NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT = (0x00000002) +NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT = (0x00000003) +NVC36F_CTRL_RESERVED = (0x00) +NVC36F_CTRL_GPFIFO = (0x01) +NVC36F_CTRL_EVENT = (0x02) +NVC36F_CTRL_INTERNAL = (0x03) +NVC36F_CTRL_CMD_NULL = (0xc36f0000) +NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0108) +NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x8) +NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES = 0x2 +NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER = (0xc36f0109) +NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID = (0x9) +NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = (0xc36f010a) +NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID = (0xA) +NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION = (0xc36f0205) +NVC36F_CTRL_CMD_EVENT_SET_TRIGGER = (0xc36f0206) +NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0301) +NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x1) +NVCB33_CTRL_RESERVED = (0x00) +NVCB33_CTRL_CONF_COMPUTE = (0x01) +NV_CONF_COMPUTE_CTRL_CMD_NULL = (0xcb330000) +NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = (0xcb330101) +NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE = 0 +NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV = 1 +NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX = 2 +NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP = 3 +NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM = 4 +NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE = 0 +NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM = 1 +NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC = 2 +NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0 +NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM = 1 +NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD = 2 +NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED = 0 +NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED = 1 +NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED = 2 +NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED = 0 +NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED = 1 +NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE = 0 +NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE = 1 +NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = (0xcb330104) +NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE = (0xcb330105) +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE = (0xcb330106) +NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE = (0xcb330107) +NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS = (0xcb330108) +NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0x8) +NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE = (0xcb330109) +NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE = 0x1000 +NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE = 0x1400 +NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID = (0x9) +NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT = (0xcb33010a) +NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE = 0x2000 +NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE = 0x1000 +NV_CONF_COMPUTE_NONCE_SIZE = 0x20 +NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID = (0xA) +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = (0xcb33010b) +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE = (0xcb33010c) +NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED = 0 +NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED = 1 +NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED = 2 +NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED = 3 +NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID = (0xC) +NVA06C_CTRL_RESERVED = (0x00) +NVA06C_CTRL_GPFIFO = (0x01) +NVA06C_CTRL_INTERNAL = (0x02) +NVA06C_CTRL_CMD_NULL = (0xa06c0000) +NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06c0101) +NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) +NVA06C_CTRL_CMD_BIND = (0xa06c0102) +NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID = (0x2) +NVA06C_CTRL_CMD_SET_TIMESLICE = (0xa06c0103) +NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x3) +NVA06C_CTRL_CMD_GET_TIMESLICE = (0xa06c0104) +NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID = (0x4) +NVA06C_CTRL_CMD_PREEMPT = (0xa06c0105) +NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID = (0x5) +NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US = (1000000) +NVA06C_CTRL_CMD_GET_INFO = (0xa06c0106) +NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID = (0x6) +NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06c0107) +NVA06C_CTRL_INTERLEAVE_LEVEL_LOW = (0x00000000) +NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM = (0x00000001) +NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH = (0x00000002) +NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x7) +NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06c0108) +NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x8) +NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE = (0xa06c0109) +NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID = (0x9) +NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = (0xa06c010a) +NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES = (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES) +NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID = (0xa) +NVA06C_CTRL_CMD_MAKE_REALTIME = (0xa06c0110) +NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID = (0x10) +NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE = (0xa06c0201) +NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) +NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE = (0xa06c0202) +NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x2) +GMMU_FMT_MAX_LEVELS = 6 +NV90F1_CTRL_RESERVED = (0x00) +NV90F1_CTRL_VASPACE = (0x01) +NV90F1_CTRL_CMD_NULL = (0x90f10000) +NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT = (0x90f10101) +NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID = (0x1) +NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO = (0x90f10102) +NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) +NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE = 0x0 +NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES = (0x90f10103) +NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID = (0x3) +NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES = (0x90f10104) +NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID = (0x4) +NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF = (0x90f10105) +NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID = (0x5) +NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES = (0x90f10106) +NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID = (0x6) +NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE = (0x90f10107) +NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID = (0x7) +NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO = (0x90f10108) +NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID = (0x8) +NV0000_CTRL_RESERVED = (0x00) +NV0000_CTRL_SYSTEM = (0x01) +NV0000_CTRL_GPU = (0x02) +NV0000_CTRL_GSYNC = (0x03) +NV0000_CTRL_DIAG = (0x04) +NV0000_CTRL_EVENT = (0x05) +NV0000_CTRL_NVD = (0x06) +NV0000_CTRL_SWINSTR = (0x07) +NV0000_CTRL_PROC = (0x09) +NV0000_CTRL_SYNC_GPU_BOOST = (0x0A) +NV0000_CTRL_GPUACCT = (0x0B) +NV0000_CTRL_VGPU = (0x0C) +NV0000_CTRL_CLIENT = (0x0D) +NV0000_CTRL_OS_WINDOWS = (0x3F) +NV0000_CTRL_OS_MACOS = (0x3E) +NV0000_CTRL_OS_UNIX = (0x3D) +NV0000_CTRL_CMD_NULL = (0x0) +NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = (0xd01) +NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID = 0x00000000 +NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM = 0x00000001 +NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM = 0x00000002 +NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM = 0x00000003 +NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC = 0x00000004 +NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO = (0xd02) +NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID = 0x00000000 +NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT = 0x00000001 +NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID = 0x00000002 +NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS = (0xd03) +NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID = (0x3) +NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = (0xd04) +NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE = (0xd05) +NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID = (0x5) +NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT = (0xd06) +NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID = (0x6) +NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES = (0xd07) +NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID = (0x7) +NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL = (0xd08) +NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID = (0x8) +NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE = (0x480) +NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x80) +NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED = (0x00000000) +NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED = (0x00000001) +NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES = (0x20000) +NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE = (0x481) +NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x81) +NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE = (0x00000000) +NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE = (0x00000001) +NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET = (0x00000002) +NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH = (0xc) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA = (0x00000001) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED = (0x00000002) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND = (0x00000003) +NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA = (0x00000004) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API = (0x00000010) +NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API = (0x00000011) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS = (0x00000020) +NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS = (0x00000021) +NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA = (0x00000100) +NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL = (0x00001000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET = (0x00002000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET = (0x00002001) +NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX = (0x00002002) +NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX = (0x00002003) +NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP = (0x00003000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM = (0x00003001) +NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM = (0x00003002) +NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA = (0x00003003) +NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA = (0x00003004) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC = (0x00004000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM = (0x00004001) +NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT = (0x00004010) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT = (0x00005000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE = (0x00005001) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE = (0x00005002) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG = (0x00005003) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP = (0x00005004) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN = (0x00005005) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL = (0x00005006) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG = (0x00005007) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP = (0x00005008) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY = (0x00005009) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM = (0x0000500A) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT = (0x0000500B) +NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT = (0x0000500C) +NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS = (0x00006000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA = (0x00007000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA = (0x00007001) +NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR = (0x0000F000) +NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC = (0x0000F00F) +NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES = (0x485) +NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX = (0x40) +NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID = (0x85) +NV0000_CTRL_CMD_DIAG_PROFILE_RPC = (0x488) +NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID = (0x88) +NV0000_CTRL_PROFILE_RPC_CMD_DISABLE = (0x00000000) +NV0000_CTRL_PROFILE_RPC_CMD_ENABLE = (0x00000001) +NV0000_CTRL_PROFILE_RPC_CMD_RESET = (0x00000002) +NV0000_CTRL_CMD_DIAG_DUMP_RPC = (0x489) +NV0000_CTRL_DIAG_RPC_MAX_ENTRIES = (100) +NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID = (0x89) +NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x501) +NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) +NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) +NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) +NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS = (0x502) +NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = (0x201) +NV0000_CTRL_GPU_MAX_ATTACHED_GPUS = 32 +NV0000_CTRL_GPU_INVALID_ID = (0xffffffff) +NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_CMD_GPU_GET_ID_INFO = (0x202) +NV0000_CTRL_GPU_MAX_SZNAME = 128 +NV0000_CTRL_NO_NUMA_NODE = (-1) +NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_SLI_STATUS_OK = (0x00000000) +NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED = (0x00000002) +NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED = (0x00000040) +NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT = (0x00000001) +NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = (0x205) +NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID = (0x5) +NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE = (0x00000000) +NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE = (0x00000001) +NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE = (0x00000000) +NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE = (0x00000001) +NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE = (0x00000000) +NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE = (0x00000001) +NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE = (0x00000000) +NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE = (0x00000001) +NV0000_CTRL_GPU_ID_INFO_SOC_FALSE = (0x00000000) +NV0000_CTRL_GPU_ID_INFO_SOC_TRUE = (0x00000001) +NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE = (0x00000000) +NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE = (0x00000001) +NV0000_CTRL_CMD_GPU_GET_INIT_STATUS = (0x203) +NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID = (0x3) +NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = (0x204) +NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = (0x214) +NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID = (0x14) +NV0000_CTRL_CMD_GPU_GET_PCI_INFO = (0x21b) +NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1B) +NV0000_CTRL_CMD_GPU_ATTACH_IDS = (0x215) +NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS = (0x0000ffff) +NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID = (0x15) +NV0000_CTRL_CMD_GPU_DETACH_IDS = (0x216) +NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS = (0x0000ffff) +NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID = (0x16) +NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS = (0x219) +NV0000_CTRL_GPU_MAX_VIDEO_LINKS = 8 +NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID = (0x19) +NV0000_CTRL_CMD_GPU_GET_SVM_SIZE = (0x240) +NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID = (0x40) +NV0000_CTRL_CMD_GPU_GET_UUID_INFO = (0x274) +NV0000_GPU_MAX_GID_LENGTH = (0x00000100) +NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID = (0x74) +NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII = (0x00000000) +NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY = (0x00000002) +NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 = (0x00000000) +NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 = (0x00000001) +NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = (0x275) +NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID = (0x75) +NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII = (0x00000000) +NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY = (0x00000002) +NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 = (0x00000000) +NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 = (0x00000001) +NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE = (0x278) +NV0000_CTRL_GPU_DRAIN_STATE_DISABLED = (0x00000000) +NV0000_CTRL_GPU_DRAIN_STATE_ENABLED = (0x00000001) +NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE = (0x00000001) +NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE = (0x00000002) +NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x78) +NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = (0x279) +NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x79) +NV0000_CTRL_CMD_GPU_DISCOVER = (0x27a) +NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = (0x27b) +NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID = (0x7B) +NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE = (0x00000001) +NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT = (0x281) +NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID = (0x81) +NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA = 0x00000175 +NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN = 6 +NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT = 5 +NV0000_CTRL_CMD_GPU_LEGACY_CONFIG = (0x282) +NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID = (0x82) +NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET = (0x00000001) +NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX = (0x00000002) +NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX = (0x00000003) +NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED = (0x00000004) +NV0000_CTRL_CMD_IDLE_CHANNELS = (0x283) +NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x83) +NV0000_CTRL_GPU_IMAGE_TYPE_GSP = (0x00000001) +NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG = (0x00000002) +NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE = (0x00000003) +NV0000_CTRL_CMD_PUSH_UCODE_IMAGE = (0x285) +NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID = (0x85) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL = (0x00) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF = (0x01) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN = (0x02) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF = (0x03) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER = (0x04) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT = (0x05) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET = (0x00) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE = (0x01) +NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU = (0x02) +NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE = (0x286) +NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x86) +NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE = (0x287) +NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x87) +NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = (0x288) +NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES = 256 +NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x88) +NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = (0x289) +NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID = (0x89) +NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = (0x290) +NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID = (0x90) +NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE = (0xb01) +NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED = (0x00000000) +NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED = (0x00000001) +NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = (0xb02) +NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO = (0xb03) +NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID = (0x3) +NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS = (0xb04) +NV0000_GPUACCT_PID_MAX_COUNT = 4000 +NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA = (0xb05) +NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID = (0x5) +NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = (0x301) +NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_GSYNC_INVALID_ID = (0xffffffff) +NV0000_CTRL_CMD_GSYNC_GET_ID_INFO = (0x302) +NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_NVD_DUMP_COMPONENT_SYS = (0x400) +NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG = (0x800) +NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED = (0xB00) +NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x601) +NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_NVD_MAX_DUMP_SIZE = (1000000) +NV0000_CTRL_CMD_NVD_GET_DUMP = (0x602) +NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) +NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT = (0x00000000) +NV0000_NVD_CPU_TIME_CLK_ID_OSTIME = (0x00000001) +NV0000_NVD_CPU_TIME_CLK_ID_TSC = (0x00000002) +NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API = (0x00000003) +NV0000_CTRL_CMD_NVD_GET_TIMESTAMP = (0x603) +NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID = (0x3) +NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO = (0x604) +NV0000_CTRL_NVD_MAX_RUNTIME_SIZES = (16) +NV0000_CTRL_NVD_SIGNATURE_SIZE = (4) +NV0000_CTRL_NVD_MAX_BUFFERS = (3840) +NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED = (0) +NV0000_CTRL_NVD_RUNTIME_SIZE_INT = (1) +NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG = (2) +NV0000_CTRL_NVD_RUNTIME_SIZE_STRING = (3) +NV0000_CTRL_NVD_RUNTIME_SIZE_PTR = (4) +NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR = (5) +NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT = (6) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE = (0x00000000) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT = (0x00000004) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE = (0x00000000) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 = (0x00000001) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 = (0x00000002) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF = (0x00000003) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO = (0x00000000) +NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES = (0x00000001) +NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO = (0x605) +NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x5) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES = (0x00000001) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES = (0x00000001) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP = (0x00000001) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES = (0x00000001) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES = (0x00000001) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE = (0x00000001) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL = (0x00000002) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO = (0x00000000) +NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES = (0x00000001) +NV0000_CTRL_CMD_NVD_GET_NVLOG = (0x606) +NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE = (4000) +NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID = (0x6) +NV0000_CTRL_CMD_NVD_GET_RCERR_RPT = (0x607) +NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES = 200 +NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST = 0 +NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS = 1 +NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS = 2 +NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS = 3 +NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY = 0x00000000 +NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED = 0x00000001 +NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG = 0x0000000f +NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST = 0x00000001 +NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST = 0x00000002 +NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID = 0x00000004 +NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID = 0x00000008 +TPC_REG_ATTR = lambda gpcId,tpcId: ((gpcId << 8) | (tpcId)) +ROP_REG_ATTR = lambda gpcId,ropId: ((gpcId << 8) | (ropId)) +SM_REG_ATTR = lambda gpcId,tpcId,smId: ((((gpcId) << 16) | ((tpcId) << 8)) | (smId)) +NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID = 0x00000000 +NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID = 0xFFFFFFFF +NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID = (0x7) +NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS = (0x608) +NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID = (0x8) +NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_CMD_SET_SUB_PROCESS_ID = (0x901) +NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION = (0x902) +NV0000_SYNC_GPU_BOOST_MAX_GROUPS = (0x10) +NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID = 0xFFFFFFFF +NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO = (0xa01) +NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE = (0xa02) +NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY = (0xa03) +NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID = (0x3) +NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = (0xa04) +NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = (0x1f0) +NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID = (0xF0) +NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = (0x101) +NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID = (0x1) +NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = (0x102) +NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY = 0xF +NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY = 0xA +NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL = 0x0 +NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL = 0x4 +NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY = 0x6 +NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY = 0x0 +NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL = 0x7 +NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL = 0xA +NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL = 0x9 +NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN = (0x00000000) +NV0000_CTRL_SYSTEM_CPU_TYPE_P5 = (0x00000001) +NV0000_CTRL_SYSTEM_CPU_TYPE_P55 = (0x00000002) +NV0000_CTRL_SYSTEM_CPU_TYPE_P6 = (0x00000003) +NV0000_CTRL_SYSTEM_CPU_TYPE_P2 = (0x00000004) +NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC = (0x00000005) +NV0000_CTRL_SYSTEM_CPU_TYPE_CELA = (0x00000006) +NV0000_CTRL_SYSTEM_CPU_TYPE_P3 = (0x00000007) +NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 = (0x00000008) +NV0000_CTRL_SYSTEM_CPU_TYPE_P4 = (0x00000009) +NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 = (0x00000010) +NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H = (0x00000011) +NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM = (0x00000012) +NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM = (0x00000013) +NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR = (0x00000014) +NV0000_CTRL_SYSTEM_CPU_TYPE_K5 = (0x00000030) +NV0000_CTRL_SYSTEM_CPU_TYPE_K6 = (0x00000031) +NV0000_CTRL_SYSTEM_CPU_TYPE_K62 = (0x00000032) +NV0000_CTRL_SYSTEM_CPU_TYPE_K63 = (0x00000033) +NV0000_CTRL_SYSTEM_CPU_TYPE_K7 = (0x00000034) +NV0000_CTRL_SYSTEM_CPU_TYPE_K8 = (0x00000035) +NV0000_CTRL_SYSTEM_CPU_TYPE_K10 = (0x00000036) +NV0000_CTRL_SYSTEM_CPU_TYPE_K11 = (0x00000037) +NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN = (0x00000038) +NV0000_CTRL_SYSTEM_CPU_TYPE_C6 = (0x00000060) +NV0000_CTRL_SYSTEM_CPU_TYPE_C62 = (0x00000061) +NV0000_CTRL_SYSTEM_CPU_TYPE_GX = (0x00000070) +NV0000_CTRL_SYSTEM_CPU_TYPE_M1 = (0x00000071) +NV0000_CTRL_SYSTEM_CPU_TYPE_M2 = (0x00000072) +NV0000_CTRL_SYSTEM_CPU_TYPE_MGX = (0x00000073) +NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE = (0x00000080) +NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 = (0x00000090) +NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 = (0x00000091) +NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 = (0x00000092) +NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN = (0x00000093) +NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN = (0xA0000000) +NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 = (0xA0000009) +NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 = (0xA000000F) +NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 = (0xA0001000) +NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 = (0xA0002000) +NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC = (0xA00FF000) +NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC = (0xA00FF001) +NV0000_CTRL_SYSTEM_CPU_CAP_MMX = (0x00000001) +NV0000_CTRL_SYSTEM_CPU_CAP_SSE = (0x00000002) +NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW = (0x00000004) +NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 = (0x00000008) +NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE = (0x00000010) +NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING = (0x00000020) +NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC = (0x00000040) +NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO = (0x00000080) +NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND = (0x00000100) +NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT = (0x00000200) +NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT = (0x00000400) +NV0000_CTRL_SYSTEM_CPU_CAP_CMOV = (0x00000800) +NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH = (0x00001000) +NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 = (0x00002000) +NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 = (0x00004000) +NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 = (0x00008000) +NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE = (0x00010000) +NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 = (0x00020000) +NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 = (0x00040000) +NV0000_CTRL_SYSTEM_CPU_CAP_AVX = (0x00080000) +NV0000_CTRL_SYSTEM_CPU_CAP_ERMS = (0x00100000) +NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO = (0x104) +NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH = (0x0000020) +NV0000_SYSTEM_CHIPSET_INVALID_ID = (0xffff) +NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO = (0x00000000) +NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES = (0x00000001) +NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT = (0x107) +NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID = (0x7) +NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES = (0x109) +NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID = (0x9) +NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST = (0x108) +NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE = (32) +NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x8) +NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT = (0x110) +NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID = (0x10) +NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE = (0x00000001) +NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE = (0x00000002) +NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID = (0x00000003) +NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK = (0x00000004) +NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED = (0x00000001) +NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC = (0x00000001) +NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED = (0x00000001) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS = (0x00000001) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF = (0x00000002) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI = (0x00000003) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL = (0x00000004) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT = (0x5) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS = (0x00000001) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF = (0x00000002) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI = (0x00000003) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL = (0x00000004) +NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT = (0x5) +NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE = (0x111) +NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID = (0x11) +NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP = (0x000000) +NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC = (0x000001) +NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA = (0x000002) +NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC = (0x000003) +NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL = (0x121) +NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE = 512 +NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET = (0x00000000) +NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET = (0x00000001) +NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID = (0x21) +NV0000_CTRL_SYSTEM_HWBC_INVALID_ID = (0xFFFFFFFF) +NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO = (0x124) +NV0000_CTRL_SYSTEM_MAX_HWBCS = (0x00000080) +NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID = (0x24) +NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL = (0x122) +NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID = (0x22) +NV0000_CTRL_CMD_SYSTEM_GPS_INVALID = (0xFFFF) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT = (0x0000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC = (0x0001) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC = (0x0002) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS = (0x0003) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS = (0x0004) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC = (0x0005) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC = (0x0006) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE = (0x0007) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE = (0x0008) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT = (0x0009) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT = (0x000A) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE = (0x000B) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE = (0x000C) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER = (0x0100) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER = (0x0101) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET = (0x0102) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET = (0x0103) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD = (0x0104) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD = (0x0105) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET = (0x0106) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET = (0x0107) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT = (0x0108) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST = (0x0109) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST = (0x010A) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE = (0x010B) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE = (0x010C) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO = (0x010D) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER = (0x0200) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA = (0x0201) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE = (0x0202) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG = (0x0203) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL = (0x0204) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN = (0x0205) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE = (0x0206) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS = (0x0210) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP = (0x0220) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA = (0x0221) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE = (0x0222) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE = (0x0240) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP = (0x0241) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN = (0x0242) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX = (0x0243) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION = (0x0244) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE = (0x0250) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE = (0x0251) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA = (0x0252) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA = (0x0253) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT = (0x0321) +NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID = (0xFFFF) +NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM = (0x0000) +NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU = lambda i: (0x0100+((i)%0x100)) +NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU = lambda i: (0x0200+((i)%0x100)) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID = (0x80000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS = (0x00000004) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC = (0x00000008) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC = (0x00000010) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB = (0x00000020) +NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL = (0x123) +NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX = (16) +NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x23) +NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = (0x127) +NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32 +NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED = 1024 +NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS = 8 +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER = 0xffffffff +NV0000_CTRL_P2P_CAPS_INDEX_READ = 0 +NV0000_CTRL_P2P_CAPS_INDEX_WRITE = 1 +NV0000_CTRL_P2P_CAPS_INDEX_NVLINK = 2 +NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS = 3 +NV0000_CTRL_P2P_CAPS_INDEX_PROP = 4 +NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK = 5 +NV0000_CTRL_P2P_CAPS_INDEX_PCI = 6 +NV0000_CTRL_P2P_CAPS_INDEX_C2C = 7 +NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 = 8 +NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9 +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0x27) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE = (0x00000001) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE = (0x00000000) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE = (0x00000001) +NV0000_P2P_CAPS_STATUS_OK = (0x00) +NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED = (0x01) +NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED = (0x02) +NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED = (0x03) +NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY = (0x04) +NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED = (0x05) +NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = (0x12b) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID = (0x2B) +NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = (0x13a) +NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID = (0x3A) +NV0000_CTRL_CMD_SYSTEM_GPS_CTRL = (0x12a) +NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID = (0x2A) +NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) +NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) +NV0000_CTRL_GPS_INPUT_SENSOR_INDEX = (0x00000000) +NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT = (0x00000000) +NV0000_CTRL_GPS_RESULT_MIN_LIMIT = (0x00000001) +NV0000_CTRL_GPS_RESULT_MAX_LIMIT = (0x00000002) +NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE = (0x00000003) +NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) +NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) +NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) +NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) +NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) +NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) +NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) +NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) +NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) +NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) +NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) +NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) +NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) +NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) +NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) +NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) +NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL = (0x00000001) +NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE = (0x00000000) +NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI = (0x0000001B) +NV0000_CTRL_GPS_INPUT_ACPI_CMD = (0x00000000) +NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN = (0x00000001) +NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 = (0x00000000) +NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 = (0x00000001) +NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) +NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) +NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) +NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ = (0x00000000) +NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) +NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) +NV0000_CTRL_GPS_INPUT_TEMP_PERIOD = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) +NV0000_CTRL_GPS_RESULT_TEMP_PERIOD = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) +NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP = (0x00000000) +NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) +NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP = (0x00000000) +NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) +NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) +NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) +NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) +NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) +NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) +NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) +NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) +NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) +NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) +NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) +NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) +NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) +NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) +NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) +NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0) +NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) +NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0) +NV0000_CTRL_GPS_CMD_TYPE_GET_PPM = (0x00000048) +NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX = (0) +NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1) +NV0000_CTRL_GPS_CMD_TYPE_SET_PPM = (0x00000049) +NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX = (0) +NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX = (2) +NV0000_CTRL_GPS_PPM_INDEX_MAXPERF = (0) +NV0000_CTRL_GPS_PPM_INDEX_BALANCED = (1) +NV0000_CTRL_GPS_PPM_INDEX_QUIET = (2) +NV0000_CTRL_GPS_PPM_INDEX_INVALID = (0xFF) +NV0000_CTRL_GPS_PPM_MASK_INVALID = (0) +NV0000_CTRL_GPS_CMD_PS_STATUS_OFF = (0) +NV0000_CTRL_GPS_CMD_PS_STATUS_ON = (1) +NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS = (0x129) +GPS_MAX_COUNTERS_PER_BLOCK = 32 +NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID = (0x29) +NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS = (0x12c) +NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2C) +NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS = (0x12e) +NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2E) +GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 +NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID = (0x2D) +NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI = (0x12d) +NV0000_CTRL_SYSTEM_PARAM_TGPU = (0x00000000) +NV0000_CTRL_SYSTEM_PARAM_PDTS = (0x00000001) +NV0000_CTRL_SYSTEM_PARAM_SFAN = (0x00000002) +NV0000_CTRL_SYSTEM_PARAM_SKNT = (0x00000003) +NV0000_CTRL_SYSTEM_PARAM_CPUE = (0x00000004) +NV0000_CTRL_SYSTEM_PARAM_TMP1 = (0x00000005) +NV0000_CTRL_SYSTEM_PARAM_TMP2 = (0x00000006) +NV0000_CTRL_SYSTEM_PARAM_CTGP = (0x00000007) +NV0000_CTRL_SYSTEM_PARAM_PPMD = (0x00000008) +NV0000_CTRL_SYSTEM_PARAM_COUNT = (0x00000009) +NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD = (0x130) +NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID = (0x30) +NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS = (0x00000000) +NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG = (0x00000001) +NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS = (0x00000002) +NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY = (0x00000003) +NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS = (0x131) +NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID = (0x31) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL = (0x00000001) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ = (0x00000002) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH = (0x00000004) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF = (0x00000010) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG = (0x00000020) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS = (0x00000040) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER = (0x00000080) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP = (0x00000100) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI = (0x00000200) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR = (0x00000400) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK = (0x00000800) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL = (0x00001000) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC = (0x00002000) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM = (0x00004000) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS = (0x00008000) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE = (0x00010000) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY = (0x00020000) +NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA = (0x12f) +NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE = 64 +NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x2F) +NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA = (0x132) +NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x32) +NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE = 256 +NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO = (0x133) +NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID = (0x33) +NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS = (0x134) +NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID = (0x34) +NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED = 0 +NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED = 1 +NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS = (0x135) +NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID = (0x35) +NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG = (0x00000001) +NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG = (0x00000002) +NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG = (0x00000004) +NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = (0x136) +NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID = (0x36) +NV0000_CTRL_VGPU_GET_VGPU_VERSION = (0x137) +NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x37) +NV0000_CTRL_VGPU_SET_VGPU_VERSION = (0x138) +NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x38) +NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID = (0x139) +NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID = (0x39) +NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO = (0x13b) +NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE = 1 +NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE = 32 +NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID = (0x48) +NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID = (0x3B) +CONTROLLER_FILTER_TYPE_EMWA = 0 +CONTROLLER_FILTER_TYPE_MOVING_MAX = 1 +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE = 2 +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE = 3 +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE = 4 +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE = 5 +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE = 6 +NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED = (0x00000000) +NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) +NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES = 1 +NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO = 0 +NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION = (0x00000200) +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED = (0x00000000) +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES = (0x00000001) +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002) +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE = (0x00000008) +NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL = (0x00000009) +NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX = (255) +NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT = (0x13c) +NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID = (0x3C) +NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO = (0x13d) +NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID = (0x3D) +NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256 +NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 = (0x13e) +NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID = (0x3E) +NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL = (0x13f) +NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID = (0x3F) +NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET = (0x00000000) +NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET = (0x00000001) +NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE = (0x00000000) +NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE = (0x00000001) +NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL = (0x140) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID = (0x40) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID = (0xFFFF) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT = (0x0000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC = (0x0001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC = (0x0002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS = (0x0003) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS = (0x0004) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC = (0x0005) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC = (0x0006) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE = (0x0007) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE = (0x0008) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT = (0x0009) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT = (0x000A) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE = (0x000B) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE = (0x000C) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER = (0x0100) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER = (0x0101) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET = (0x0102) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET = (0x0103) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD = (0x0104) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD = (0x0105) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET = (0x0106) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET = (0x0107) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT = (0x0108) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST = (0x0109) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST = (0x010A) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE = (0x010B) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE = (0x010C) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO = (0x010D) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER = (0x0200) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA = (0x0201) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE = (0x0202) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG = (0x0203) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL = (0x0204) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN = (0x0205) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE = (0x0206) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS = (0x0210) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP = (0x0220) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA = (0x0221) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE = (0x0222) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE = (0x0240) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP = (0x0241) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN = (0x0242) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX = (0x0243) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION = (0x0244) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE = (0x0250) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE = (0x0251) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA = (0x0252) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA = (0x0253) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT = (0x0321) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID = (0xFFFF) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM = (0x0000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU = lambda i: (0x0100+((i)%0x100)) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU = lambda i: (0x0200+((i)%0x100)) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID = (0x80000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS = (0x00000004) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC = (0x00000008) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC = (0x00000010) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB = (0x00000020) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS = (0x00000040) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING = (0x00000002) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT = (0x00000003) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 = (0x00000004) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 = (0x00000005) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL = (0x141) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX = (16) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x41) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL = (0x142) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID = (0x42) +NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT = (0x00000002) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT = (0x00000002) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE = (0x00000003) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT = (0x00000003) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI = (0x0000001B) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E) +NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F) +NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM = (0x00000048) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX = (0) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM = (0x00000049) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX = (0) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX = (2) +NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF = (0) +NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED = (1) +NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET = (2) +NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID = (0xFF) +NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID = (0) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF = (0) +NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON = (1) +PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK = 32 +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS = (0x146) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x46) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS = (0x147) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x47) +PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288 +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID = (0x43) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI = (0x143) +NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR = (0x00008000) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA = (0x144) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE = 64 +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x44) +NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA = (0x145) +NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x45) +NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE = (0x3d02) +NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH = (0x00000001) +NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE = (0x00000002) +NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE = (0x00000003) +NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR = (0x3d04) +NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = (0x3d05) +NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID = (0x5) +NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE = (0x00000000) +NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE = (0x00000001) +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD = (0x3d06) +NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID = (0x6) +NV0000_CTRL_CMD_OS_GET_GPU_INFO = (0x3d07) +NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO = (0x3d08) +NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE = 64 +NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID = (0x8) +NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST = (0x3d09) +NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD = (0x3d0a) +NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE = NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE +NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID = (0xA) +NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD = (0x3d0b) +NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS = 512 +NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID = (0xB) +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD = (0x3d0c) +NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS = 128 +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE = 0 +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM = 1 +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM = 2 +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC = 3 +NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC = 4 +NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID = (0xC) +NV0000_CTRL_CMD_VGPU_CREATE_DEVICE = (0xc02) +NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID = (0x2) +NV0000_CTRL_CMD_VGPU_GET_INSTANCES = (0xc03) +NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID = (0x3) +NV0000_CTRL_CMD_VGPU_DELETE_DEVICE = (0xc04) +NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID = (0x4) +NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS = (0xc05) +NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID = (0x5) +NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE = (0x206) +NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID = (0x6) +NV0080_CTRL_RESERVED = (0x00) +NV0080_CTRL_BIF = (0x01) +NV0080_CTRL_GPU = (0x02) +NV0080_CTRL_CLK = (0x10) +NV0080_CTRL_GR = (0x11) +NV0080_CTRL_CIPHER = (0x12) +NV0080_CTRL_FB = (0x13) +NV0080_CTRL_HOST = (0x14) +NV0080_CTRL_VIDEO = (0x15) +NV0080_CTRL_FIFO = (0x17) +NV0080_CTRL_DMA = (0x18) +NV0080_CTRL_PERF = (0x19) +NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0x99) +NV0080_CTRL_MSENC = (0x1B) +NV0080_CTRL_BSP = (0x1C) +NV0080_CTRL_RC = (0x1D) +NV0080_CTRL_OS_UNIX = (0x1E) +NV0080_CTRL_NVJPG = (0x1F) +NV0080_CTRL_INTERNAL = (0x20) +NV0080_CTRL_NVLINK = (0x21) +NV0080_CTRL_CMD_NULL = (0x800000) +NV0080_CTRL_CMD_BIF_RESET = (0x800102) +NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET = 0x1 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR = 0x2 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL = 0x3 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE = 0x4 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE = 0x5 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX = 0x6 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER = 0x7 +NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE = 0x8 +NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE = (0x800104) +NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID = (0x4) +NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED = 0x000000001 +NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED = 0x000000000 +NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED = 0x000000001 +NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED = 0x000000000 +NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE = (0x800105) +NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID = (0x5) +NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK = (0x800106) +NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID = (0x6) +NV0080_CTRL_CMD_BSP_GET_CAPS = (0x801c01) +NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_BSP_CAPS_TBL_SIZE = 8 +NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = (0x801c02) +NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID = (0x2) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED = (0x00000002) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 = (0x00000002) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 = (0x00000004) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED = (0x00000002) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED = (0x00000003) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE = (0x00000001) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE = (0x00000000) +NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE = (0x00000001) +NV0080_CTRL_CMD_DMA_GET_PTE_INFO = (0x801801) +NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS = 5 +NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_CMD_DMA_SET_PTE_INFO = (0x80180a) +NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS = 5 +NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID = (0xA) +NV0080_CTRL_CMD_DMA_FILL_PTE_MEM = (0x801802) +NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_CMD_DMA_FLUSH = (0x801805) +NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID = (0x5) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE = (0x00000000) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE = (0x00000001) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE = (0x00000000) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE = (0x00000001) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE = (0x00000000) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE = (0x00000001) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM = (0x00000001) +NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM = (0x00000002) +NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = (0x801806) +NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS = (16) +NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID = (0x6) +NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO = 0x1 +NV0080_CTRL_CMD_DMA_GET_PDE_INFO = (0x801809) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) +NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS = 5 +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID = (0x9) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002) +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL = 1 +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF = 2 +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER = 3 +NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH = 4 +NV0080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x80180c) +NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0xC) +NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE = (0x00000000) +NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE = (0x00000001) +NV0080_CTRL_CMD_DMA_GET_CAPS = (0x80180d) +NV0080_CTRL_DMA_CAPS_TBL_SIZE = 8 +NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID = (0xD) +NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE = (0x80180e) +NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID = (0xE) +NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX = (0xFFFFFFFFFFFFFFFF) +NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 = (0x80180f) +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID = (0x00000000) +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY = (0x00000001) +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002) +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003) +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL = 0 +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG = 1 +NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE = 2 +NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID = (0xF) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE = (0x00000000) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE = (0x00000001) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE = (0x00000000) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE = (0x00000001) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL = (0x00000000) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF = (0x00000001) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER = (0x00000002) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH = (0x00000003) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE = (0x00000000) +NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE = (0x00000001) +NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE = (0x801810) +NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID = (0x10) +NV0080_CTRL_DMA_SET_DEFAULT_VASPACE = (0x801812) +NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID = (0x12) +NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY = (0x801813) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x13) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM = (0x00000000) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH = (0x00000001) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH = (0x00000002) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE = (0x00000000) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE = (0x00000001) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE = (0x00000000) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE = (0x00000001) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE = (0x00000000) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE = (0x00000001) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE = (0x00000000) +NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE = (0x00000001) +NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY = (0x801814) +NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x14) +NV0080_CTRL_CMD_FB_GET_CAPS = (0x801301) +NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_FB_CAPS_TBL_SIZE = 3 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO = (0x801306) +NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID = (0x6) +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN = 0 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM = 1 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM = 2 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY = 0 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 = 1 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 = 2 +NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE = 3 +NV0080_CTRL_CMD_FB_GET_CAPS_V2 = (0x801307) +NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x7) +NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY = (0x801308) +NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID = (0x8) +NV0080_CTRL_CMD_FIFO_GET_CAPS = (0x801701) +NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_FIFO_CAPS_TBL_SIZE = 2 +NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = (0x801707) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS = (0x00000000) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD = (0x00000001) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO = (0x00000002) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG = (0x00000003) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE = (0x00000004) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY = (0x00000005) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION = (0x00000006) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS = (0x00000007) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL = (0x00000008) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM = (0x00000009) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT = (0x0000000a) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT = (0x0000000b) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL = (0x0000000c) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL = (0x0000000d) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB = (0x0000000e) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV = (0x0000000f) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH = (0x00000010) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB = (0x00000011) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL = (0x00000012) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB = (0x00000013) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL = (0x00000014) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL = (0x00000015) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK = (0x00000016) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT = (0x00000017) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP = (0x00000018) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP = (0x00000019) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = (0x0000001a) +NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x7) +NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS = (0x801709) +NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS = (8) +NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE = (0x80170b) +NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR = (12) +NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST = (0x80170c) +NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = (0x80170d) +NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID = (0xD) +NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE = (0x80170e) +NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0xE) +NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL = (0xffffffff) +NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES = (0x80170f) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID = (0xF) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS = (0x00000000) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS = (0x00000001) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE = (0x00000002) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE = (0x00000003) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET = (0x00000004) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT = (0x00000005) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP = (0x00000007) +NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT = (0x00000008) +NV0080_CTRL_CMD_FIFO_STOP_RUNLIST = (0x801711) +NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID = (0x11) +NV0080_CTRL_CMD_FIFO_START_RUNLIST = (0x801712) +NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID = (0x12) +NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 = (0x801713) +NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x13) +NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS = (0x801714) +NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS = 4096 +NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x14) +NV0080_CTRL_CMD_GPU_GET_CLASSLIST = (0x800201) +NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = (0x800280) +NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID = (0x80) +NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER = (0x800281) +NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID = (0x81) +NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER = (0x800282) +NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x82) +NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER = (0x800283) +NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x83) +NV0080_CTRL_CMD_GPU_SET_VIDLINK = (0x800285) +NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID = (0x85) +NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE = (0x00000000) +NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE = (0x00000001) +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS = 0 +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN = 1 +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP = 2 +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON = 0 +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN = 1 +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED = 2 +NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP = 3 +NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE = (0x800287) +NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED = (0x00000000) +NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED = (0x00000001) +NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x87) +NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = (0x800288) +NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x88) +NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = (0x800289) +NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE = (0x00000000) +NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS = (0x00000001) +NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX = (0x00000002) +NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST = (0x00000003) +NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU = NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST +NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA = (0x00000004) +NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID = (0x89) +NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028c) +NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8C) +NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028d) +NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8D) +NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT = 0 +NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE = 1 +NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE = 2 +NV0080_CTRL_CMD_GPU_GET_VGX_CAPS = (0x80028e) +NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID = (0x8E) +NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS = (0x800291) +NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID = (0x91) +NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE = 100 +NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = (0x800292) +NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID = (0x92) +NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE = (0x800293) +NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID = (0x93) +NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO = NVBIT(0) +NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS = NVBIT(1) +NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN = NVBIT(2) +NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS = (0x800294) +NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID = (0x94) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M = (1 << 6) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M = (1 << 7) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M = (1 << 8) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M = (1 << 9) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G = (1 << 10) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G = (1 << 11) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G = (1 << 12) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G = (1 << 13) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G = (1 << 14) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G = (1 << 15) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G = (1 << 16) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G = (1 << 17) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G = (1 << 18) +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M +NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G +NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID = 0x0 +NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE = (0x800296) +NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID = (0x96) +NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE = (0x800297) +NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x97) +NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE = (0x800298) +NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x98) +NV0080_CTRL_CMD_GR_GET_CAPS = (0x801102) +NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_GR_CAPS_TBL_SIZE = 23 +NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000) +NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001) +NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002) +NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003) +NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004) +NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005) +NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006) +NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007) +NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008) +NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009) +NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A) +NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B) +NV0080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C) +NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D) +NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E) +NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F) +NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010) +NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011) +NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012) +NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019) +NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C) +NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021) +NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022) +NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029) +NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B) +NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C) +NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D) +NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033) +NV0080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033) +NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034) +NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035) +NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036) +NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037) +NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038) +NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039) +NV0080_CTRL_GR_INFO_INDEX_MAX = (0x00000039) +NV0080_CTRL_GR_INFO_MAX_SIZE = (0x3a) +NV0080_CTRL_CMD_GR_GET_INFO = (0x801104) +NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x4) +NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE = (0x801107) +NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x801108) +NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x7) +NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x8) +NV0080_CTRL_CMD_GR_GET_CAPS_V2 = (0x801109) +NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x9) +NV0080_CTRL_CMD_GR_GET_INFO_V2 = (0x801110) +NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) +NV0080_CTRL_CMD_HOST_GET_CAPS = (0x801401) +NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_HOST_CAPS_TBL_SIZE = 3 +NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = (0x801402) +NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE = (0x802002) +NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE = (0x802003) +NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x3) +NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL = (0x802009) +NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x802004) +NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL = (0x802007) +NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS = (0x802008) +NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS = 200 +NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0x08) +NV0080_CTRL_CMD_MSENC_GET_CAPS = (0x801b01) +NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_MSENC_CAPS_TBL_SIZE = 4 +NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 = (0x801b02) +NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_NVJPG_CAPS_TBL_SIZE = 9 +NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 = (0x801f02) +NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2) +NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7) +NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID = (0x9) +NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = (0x801909) +NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH = (0x801e01) +NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID = (0x1) +NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE = (0x00000001) +NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE = (0x00000002) +NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED = (0x00000003) +NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO = (0x801e02) +NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_RESERVED = (0x00) +NV2080_CTRL_GPU = (0x01) +NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED = (0x81) +NV2080_CTRL_FUSE = (0x02) +NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED = (0x82) +NV2080_CTRL_EVENT = (0x03) +NV2080_CTRL_TIMER = (0x04) +NV2080_CTRL_THERMAL = (0x05) +NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED = (0xc5) +NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED = (0x85) +NV2080_CTRL_I2C = (0x06) +NV2080_CTRL_EXTI2C = (0x07) +NV2080_CTRL_BIOS = (0x08) +NV2080_CTRL_CIPHER = (0x09) +NV2080_CTRL_INTERNAL = (0x0A) +NV2080_CTRL_CLK_LEGACY_PRIVILEGED = (0xd0) +NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED = (0x90) +NV2080_CTRL_CLK = (0x10) +NV2080_CTRL_FIFO = (0x11) +NV2080_CTRL_GR = (0x12) +NV2080_CTRL_FB = (0x13) +NV2080_CTRL_MC = (0x17) +NV2080_CTRL_BUS = (0x18) +NV2080_CTRL_PERF_LEGACY_PRIVILEGED = (0xe0) +NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0xa0) +NV2080_CTRL_PERF = (0x20) +NV2080_CTRL_NVIF = (0x21) +NV2080_CTRL_RC = (0x22) +NV2080_CTRL_GPIO = (0x23) +NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED = (0xa3) +NV2080_CTRL_NVD = (0x24) +NV2080_CTRL_DMA = (0x25) +NV2080_CTRL_PMGR = (0x26) +NV2080_CTRL_PMGR_LEGACY_PRIVILEGED = (0xe6) +NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED = (0xa6) +NV2080_CTRL_POWER = (0x27) +NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED = (0xa7) +NV2080_CTRL_LPWR = (0x28) +NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED = (0xa8) +NV2080_CTRL_LPWR_LEGACY_PRIVILEGED = (0xe8) +NV2080_CTRL_ACR = (0x29) +NV2080_CTRL_CE = (0x2A) +NV2080_CTRL_SPI = (0x2B) +NV2080_CTRL_NVLINK = (0x30) +NV2080_CTRL_FLCN = (0x31) +NV2080_CTRL_VOLT = (0x32) +NV2080_CTRL_VOLT_LEGACY_PRIVILEGED = (0xf2) +NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED = (0xb2) +NV2080_CTRL_FAS = (0x33) +NV2080_CTRL_ECC = (0x34) +NV2080_CTRL_ECC_NON_PRIVILEGED = (0xb4) +NV2080_CTRL_FLA = (0x35) +NV2080_CTRL_GSP = (0x36) +NV2080_CTRL_NNE = (0x37) +NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED = (0xb7) +NV2080_CTRL_GRMGR = (0x38) +NV2080_CTRL_UCODE_FUZZER = (0x39) +NV2080_CTRL_DMABUF = (0x3A) +NV2080_CTRL_BIF = (0x3B) +NV2080_CTRL_OS_WINDOWS = (0x3F) +NV2080_CTRL_OS_MACOS = (0x3E) +NV2080_CTRL_OS_UNIX = (0x3D) +NV2080_CTRL_CMD_NULL = (0x20800000) +NV2080_CTRL_BIOS_INFO_MAX_SIZE = (0x0000000F) +NV2080_CTRL_BIOS_INFO_INDEX_REVISION = (0x00000000) +NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION = (0x00000001) +NV2080_CTRL_CMD_BIOS_GET_INFO = (0x20800802) +NV2080_CTRL_CMD_BIOS_GET_INFO_V2 = (0x20800810) +NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10) +NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH = (0x00000100) +NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII = (0x00000000) +NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE = (0x00000001) +NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH = (0x00000002) +NV2080_CTRL_BIOS_NBSI_MODULE_ROOT = (0x00000000) +NV2080_CTRL_BIOS_NBSI_MODULE_RM = (0x00000001) +NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER = (0x00000002) +NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO = (0x00000003) +NV2080_CTRL_BIOS_NBSI_MODULE_CPL = (0x00000004) +NV2080_CTRL_BIOS_NBSI_MODULE_D3D = (0x00000005) +NV2080_CTRL_BIOS_NBSI_MODULE_OGL = (0x00000006) +NV2080_CTRL_BIOS_NBSI_MODULE_PMU = (0x00000007) +NV2080_CTRL_BIOS_NBSI_MODULE_MODE = (0x00000008) +NV2080_CTRL_BIOS_NBSI_NUM_MODULES = (0x00000009) +NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN = (0x80000000) +NV2080_CTRL_BIOS_GET_NBSI_SUCCESS = (0x00000000) +NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE = (0x00000001) +NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH = (0xFFFFFFFA) +NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS = (0xFFFFFFFB) +NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE = (0xFFFFFFFC) +NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE = (0xFFFFFFFD) +NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE = (0xFFFFFFFE) +NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND = (0xFFFFFFFF) +NV2080_CTRL_CMD_BIOS_GET_NBSI = (0x20800803) +NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 = (0x2080080e) +NV2080_BIOS_GET_NBSI_MAX_RET_SIZE = (0x100) +NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ = (0x20800806) +NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID = (0x6) +GLOB_TYPE_GET_NBSI_DIR = 0xfffe +GLOB_TYPE_APITEST = 0xffff +GLOB_TYPE_GET_NBSI_ACPI_RAW = 0xfffd +NV2080_CTRL_CMD_BIOS_GET_SKU_INFO = (0x20800808) +NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_CMD_BIOS_GET_POST_TIME = (0x20800809) +NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT = (0x2080080b) +NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO = (0x00000000) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES = (0x00000001) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER = (0x00000002) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN = (0x00000003) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE = (0x00000000) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE = (0x00000001) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE = (0x00000000) +NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCI_INFO = (0x20801801) +NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_BUS_INFO_INDEX_TYPE = (0x00000000) +NV2080_CTRL_BUS_INFO_INDEX_INTLINE = (0x00000001) +NV2080_CTRL_BUS_INFO_INDEX_CAPS = (0x00000002) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS = (0x00000003) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS = (0x00000004) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS = (0x00000005) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS = (0x00000006) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS = (0x00000007) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS = (0x00000008) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS = (0x00000009) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS = (0x0000000A) +NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS = (0x0000000B) +NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS = (0x0000000C) +NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE = (0x0000000D) +NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS = (0x0000000E) +NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER = (0x0000000F) +NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER = (0x00000010) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS = (0x00000011) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS = (0x00000012) +NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE = (0x00000013) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO = (0x00000014) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER = (0x00000015) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS = (0x00000016) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS = (0x00000017) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS = (0x00000018) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT = (0x00000019) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT = (0x0000001A) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM = (0x0000001B) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS = (0x0000001C) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS = (0x0000001D) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED = (0x0000001E) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS = (0x0000001F) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR = (0x00000020) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR = (0x00000021) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR = (0x00000022) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR = (0x00000023) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS = (0x00000024) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS = (0x00000025) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS = (0x00000026) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS = (0x00000027) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR = (0x00000028) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR = (0x00000029) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR = (0x0000002A) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR = (0x0000002B) +NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER = (0x0000002C) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO = (0x0000002D) +NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE = (0x0000002E) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO = (0x0000002F) +NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO = (0x00000030) +NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO = (0x00000031) +NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI = (0x00000032) +NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE = (0x00000033) +NV2080_CTRL_BUS_INFO_INDEX_MAX = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE +NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE = (0x00000034) +NV2080_CTRL_BUS_INFO_TYPE_PCI = (0x00000001) +NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS = (0x00000003) +NV2080_CTRL_BUS_INFO_TYPE_FPCI = (0x00000004) +NV2080_CTRL_BUS_INFO_TYPE_AXI = (0x00000008) +NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH = (0x00000001) +NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS = (0x00000005) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS = (0x00000006) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 = (0x00000005) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 = (0x00000005) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 = (0x00000005) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS = (0x00000003) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS = (0x00000005) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS = (0x00000006) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 = (0x00000008) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 = (0x0000000C) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 = (0x00000010) +NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 = (0x00000020) +NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST = (0x00000008) +NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY = (0x00000010) +NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP = (0x00000004) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR = (0x00000008) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT = (0x00000010) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT = (0x00000020) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL = (0x00000040) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW = (0x00000080) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP = (0x00000100) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR = (0x00000200) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ = (0x00000400) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR = (0x00010000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP = (0x00020000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP = (0x00040000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER = (0x00080000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT = (0x00100000) +NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL = (0x00200000) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 = (0x00000002) +NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 = (0x00000003) +NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED = (0x00000000) +NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES = (0x00000001) +NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO = (0x00000000) +NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE = (0x00000000) +NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK = (0x00000001) +NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C = (0x00000002) +NV2080_CTRL_CMD_BUS_GET_INFO = (0x20801802) +NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_BUS_GET_INFO_V2 = (0x20801823) +NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x23) +NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = (0x20801803) +NV2080_CTRL_BUS_MAX_PCI_BARS = (8) +NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH = (0x20801804) +NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE = (0x00000001) +NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS = (0x00000002) +NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING = (0x00000004) +NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED = (0x20801805) +NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS = (0x00000001) +NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS = (0x00000002) +NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS = (0x00000003) +NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS = (0x00000004) +NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS = (0x00000005) +NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS = (0x00000006) +NV2080_CTRL_CMD_BUS_MAP_BAR2 = (0x20801809) +NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_BUS_UNMAP_BAR2 = (0x2080180a) +NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_CMD_BUS_VERIFY_BAR2 = (0x2080180b) +NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE = (0x20801812) +NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE = (0x00000000) +NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE = (0x00000001) +NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE = (0x00000002) +NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = (0x20801813) +NV2080_CTRL_PEX_MAX_COUNTER_TYPES = 31 +NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x13) +NV2080_CTRL_BUS_PEX_COUNTER_TYPE = 0x00000000 +NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS = 0x00000001 +NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT = 0x00000002 +NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT = 0x00000004 +NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT = 0x00000008 +NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT = 0x00000010 +NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT = 0x00000020 +NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT = 0x00000040 +NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT = 0x00000080 +NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT = 0x00000100 +NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT = 0x00000200 +NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT = 0x00000400 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS = 0x00000800 +NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT = 0x00001000 +NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT = 0x00002000 +NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT = 0x00004000 +NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT = 0x00008000 +NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT = 0x00010000 +NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT = 0x00020000 +NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT = 0x00040000 +NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT = 0x00080000 +NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT = 0x00100000 +NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT = 0x00200000 +NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT = 0x00400000 +NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT = 0x00800000 +NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT = 0x01000000 +NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT = 0x02000000 +NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT = 0x04000000 +NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT = 0x08000000 +NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT = 0x10000000 +NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT = 0x20000000 +NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT = 0x40000000 +NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS = (0x20801814) +NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x14) +NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS = (0x20801815) +NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x15) +NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS = (0x20801816) +NV2080_CTRL_PEX_MAX_LANES = 16 +NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID = (0x16) +NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE = 0x00000000 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR = 0x00000001 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR = 0x00000002 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR = 0x00000004 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR = 0x00000008 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR = 0x00000010 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW = 0x00000020 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW = 0x00000040 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR = 0x00000080 +NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR = 0x00000100 +NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY = (0x20801817) +NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x17) +NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY = (0x20801818) +NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x18) +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES = 0x00000001 +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES = 0x00000002 +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 = 0x00000004 +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 = 0x00000008 +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S = 0x00000010 +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S = 0x00000020 +NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S = 0x00000040 +NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES = 7 +NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = (0x20801819) +NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x19) +NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS = (0x20801820) +NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_BUS_GET_BFD = (0x20801821) +NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID = (0x21) +NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE = 0x00000000 +NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS = 0x00000001 +NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE = 0x00000002 +NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED = 0x00000003 +NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED = 0x00000004 +NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY = 0x00000005 +NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED = 0x00000006 +NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY = 0x00000007 +NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 = 0x00000008 +NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS = 9 +NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS = (0x20801822) +NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS = (0x20801824) +NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID = (0x24) +NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK = (0x20801825) +NV2080_CTRL_BUS_MAX_NUM_GPUS = 32 +NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID = (0x25) +NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS = (0x20801826) +NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID = (0x26) +NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE = (0x20801827) +NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID = (0x27) +NV2080_CTRL_CMD_BUS_GET_EOM_STATUS = (0x20801828) +NV2080_CTRL_BUS_MAX_NUM_LANES = 32 +NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID = (0x28) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = (0x20801829) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x29) +NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM = 0x0 +NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU = 0x1 +NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P = 0x2 +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = (0x2080182a) +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX = 2 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC = 3 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC = 4 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND = 5 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR = 6 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR = 7 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH = 8 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS = 9 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD = 10 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN = 11 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX = 12 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT = 13 +NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID = (0x2A) +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO = 0 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES = 1 +NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO = 0 +NV2080_CTRL_CMD_BUS_GET_C2C_INFO = (0x2080182b) +NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID = (0x2B) +NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU = 1 +NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU = 2 +NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS = (0x2080182c) +NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID = (0x2C) +NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING = (0x2080182e) +NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID = 0 +NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK = 1 +NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE = 2 +NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 = 3 +NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C = 4 +NV2080_SET_P2P_MAPPING_UUID_LEN = 16 +NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2E) +NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING = (0x2080182f) +NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2F) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = (0x20801830) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x30) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO = (0x00000000) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES = (0x00000001) +NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO = (0x00000000) +NV2080_CTRL_CMD_CE_GET_CAPS = (0x20802a01) +NV2080_CTRL_CE_CAPS_TBL_SIZE = 2 +NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_CE_GET_CAPS_V2 = (0x20802a03) +NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = (0x20802a02) +NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG = (0x20802a04) +NV2080_CTRL_MAX_PCES = 32 +NV2080_CTRL_MAX_GRCES = 4 +NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS = (0x20802a05) +NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE = 0xf +NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB = (0x20802a06) +NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID = (0x6) +NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS = (0x20802a07) +NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0x7) +NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE = (0x20802a08) +NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK = (0x20802a09) +NV2080_CTRL_CE_MAX_HSHUBS = 32 +NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_CE_GET_ALL_CAPS = (0x20802a0a) +NV2080_CTRL_MAX_CES = 64 +NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID = (0xa) +NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS = (0x20802a0b) +NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0xb) +NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO = (0x20802a0c) +NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID = (0xc) +NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 = (0x20802a0d) +NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID = (0xd) +NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 = (0x20802a0e) +NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID = (0xe) +NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE = (0x20802a0f) +NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID = (0xf) +NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK = (0x20802a11) +NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID = (0x11) +NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED = (0x20802a12) +NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x20802502) +NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE = (0x00000001) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE = (0x00000000) +NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE = (0x00000001) +NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE = (0x000000000) +NV2080_CTRL_DMA_INFO_INDEX_MAX = NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE +NV2080_CTRL_CMD_DMA_GET_INFO = (0x20802503) +NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES = (256) +NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD = (0x20803a01) +NV2080_CTRL_DMABUF_MAX_HANDLES = 128 +NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = (0x00000000) +NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = (0x00000001) +NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS = (0x20803400) +NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID = (0x0) +NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS = (0x20803401) +NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x20800301) +NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000) +NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001) +NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002) +NV2080_EVENT_DSTATE_XUSB_D0 = (0x00000000) +NV2080_EVENT_DSTATE_XUSB_D3 = (0x00000003) +NV2080_EVENT_DSTATE_XUSB_INVALID = (0xFFFFFFFF) +NV2080_EVENT_DSTATE_PPC_D0 = (0x00000000) +NV2080_EVENT_DSTATE_PPC_D3 = (0x00000003) +NV2080_EVENT_DSTATE_PPC_INVALID = (0xFFFFFFFF) +NV2080_CTRL_CMD_EVENT_SET_TRIGGER = (0x20800302) +NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES = (0x20800303) +NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID = (0x3) +NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED = 0 +NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING = 1 +NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR = 2 +NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY = (0x20800304) +NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI = (0x20800305) +NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION = (0x20800306) +NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID = (0x6) +NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO = (0x20800308) +NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF = (0x20800309) +NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF = (0x2080030a) +NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT = (0x00000000) +NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE = (0x00000001) +NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE = (0x00000002) +NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT = (0x00000003) +NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT = (0x00000004) +NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE = (0x00000005) +NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT = (0x00000006) +NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE = (0x00000007) +NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE = (0x00000008) +NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE = (0x00000009) +NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE = (0x0000000A) +NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH = (0x0000000B) +NV2080_CTRL_FB_INFO_INDEX_RAM_CFG = (0x0000000C) +NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE = (0x0000000D) +NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT = (0x0000000E) +NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT = (0x0000000F) +NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB = (0x0000000F) +NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB = (0x0000000F) +NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB = (0x0000000F) +NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW = (0x0000000F) +NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB = (0x00000010) +NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB = (0x00000011) +NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB = (0x00000012) +NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB = (0x00000013) +NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK = (0x00000014) +NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE = (0x00000015) +NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE = (0x00000016) +NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION = (0x00000017) +NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN = (0x00000018) +NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT = (0x00000019) +NV2080_CTRL_FB_INFO_INDEX_FBP_MASK = (0x0000001A) +NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE = (0x0000001B) +NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID = (0x0000001C) +NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE = (0x0000001D) +NV2080_CTRL_FB_INFO_INDEX_HEAP_START = (0x0000001E) +NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE = (0x0000001F) +NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE = (0x00000020) +NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T = (0x00000021) +NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT = (0x00000022) +NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT = (0x00000023) +NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE = (0x00000024) +NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE = (0x00000025) +NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE = (0x00000026) +NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE = (0x00000027) +NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED = (0x00000028) +NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE = (0x00000029) +NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT = (0x0000002A) +NV2080_CTRL_FB_INFO_INDEX_LTC_MASK = (0x0000002B) +NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED = (0x0000002C) +NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED = (0x0000002D) +NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED = (0x0000002E) +NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED = (0x0000002F) +NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE = (0x00000030) +NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT = (0x00000031) +NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB = (0x00000032) +NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB = (0x00000033) +NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB = (0x00000034) +NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE = (0x00000035) +NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB = (0x00000036) +NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK) +NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 = (0x00000037) +NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK) +NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 = (0x00000038) +NV2080_CTRL_FB_INFO_MAX_LIST_SIZE = (0x00000039) +NV2080_CTRL_FB_INFO_INDEX_MAX = (0x38) +NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN = (0x00000000) +NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM = (0x00000001) +NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 = (0x00000002) +NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 = (0x00000003) +NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 = (0x00000004) +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 = (0x00000005) +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 = (0x00000006) +NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 = (0x00000007) +NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 = (0x00000008) +NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 = (0x00000009) +NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 = (0x0000000C) +NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 = (0x0000000D) +NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 = (0x0000000E) +NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 = (0x0000000F) +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X = (0x00000010) +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 = (0x00000011) +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X = (0x00000012) +NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 = (0x00000013) +NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 = (0x00000014) +NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 = (0x00000015) +NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED = (0x00000000) +NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED = (0x00000001) +NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED = (0x00000002) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG = (0x00000001) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA = (0x00000002) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA = (0x00000003) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON = (0x00000004) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA = (0x00000005) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX = (0x00000006) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL = (0x00000007) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND = (0x00000008) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT = (0x00000009) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON = (0x0000000F) +NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN = (0xFFFFFFFF) +NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED = (0x00000000) +NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED = (0x00000001) +NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED = (0x00000002) +NV2080_CTRL_CMD_FB_GET_INFO = (0x20801301) +NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_FB_GET_INFO_V2 = (0x20801303) +NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET = (0x20801310) +NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID = (0x10) +NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED = (0x2080130c) +NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID = (0xC) +NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE = (0x00000000) +NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET = (0x00000001) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL = (0x2080130d) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO = (0x00000000) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES = (0x00000001) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO = (0x00000000) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES = (0x00000001) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO = (0x00000000) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES = (0x00000001) +NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = (0x2080130e) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES = 500 +NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY = (0x00000001) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY = (0x00000002) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO = (0x00000000) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES = (0x00000001) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO = (0x00000000) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES = (0x00000001) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY = (0x00000000) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE = (0x00000001) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO = (0x00000000) +NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES = (0x00000001) +NV2080_CTRL_CMD_FB_IS_KIND = (0x20801313) +NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID = (0x13) +NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED = (0x00000000) +NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE = (0x00000001) +NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 = (0x00000002) +NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 = (0x00000003) +NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 = (0x00000004) +NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC = (0x00000005) +NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 = (0x00000006) +NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 = (0x00000007) +NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 = (0x00000008) +NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = (0x20801315) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID = (0x15) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED = (0x00000000) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED = (0x00000001) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH = (0x00000000) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK = (0x00000001) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED = (0x00000000) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED = (0x00000001) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL = (0x00000000) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING = (0x00000001) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED = (0x00000002) +NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE = (0x00000003) +NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = (0x20801320) +NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES = 17 +NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES = 16 +NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_FB_OFFLINE_PAGES = (0x20801321) +NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES = (0x00000040) +NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS = (0xffffffffffffffff) +NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K = (0x00000000) +NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K = (0x00000001) +NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K = (0x00000002) +NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE = (0x00000002) +NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE = (0x00000004) +NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK = (0x00000000) +NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT = (0x00000001) +NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED = (0x00000002) +NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL = (0x00000003) +NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR = (0x00000004) +NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE +NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE +NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID = (0x21) +NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = (0x20801322) +NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE = 0 +NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE = 1 +NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE = 0 +NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE = 1 +NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_CMD_FB_QUERY_ACR_REGION = (0x20801325) +NV2080_CTRL_CMD_FB_ACR_CLIENT_ID = 2 +NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID = (0x25) +NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES = (0x20801326) +NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x26) +NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO = (0x20801327) +NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID = (0x27) +NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP = (0x20801328) +NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID = (0x28) +NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT = (0x20801329) +NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS = (0x2080132a) +NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS = (0x2080132b) +NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB = (0x2080132c) +NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB = (0x2080132d) +NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 = (0x20801335) +NV2080_CTRL_CMD_FB_GET_AMAP_CONF = (0x20801336) +NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID = (0x36) +NV2080_CTRL_CMD_FB_CBC_OP = (0x20801337) +NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID = (0x37) +NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION = (0x20801338) +NV2080_MAX_CTAGS_FOR_CBC_EVICTION = 0x7F +NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID = (0x38) +NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE = (0x20801339) +NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID = (0x39) +NV2080_CTRL_CMD_FB_FREE_TILE = (0x2080133a) +NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID = (0x3A) +NV2080_CTRL_CMD_FB_SETUP_VPR_REGION = (0x2080133b) +NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID = (0x3B) +NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES = (0x2080133c) +NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x3C) +NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO = (0x2080133d) +NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID = (0x3D) +NV2080_CTRL_CMD_FB_SET_RRD = (0x2080133e) +NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID = (0x3E) +NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE = (0xff) +NV2080_CTRL_CMD_FB_SET_READ_LIMIT = (0x2080133f) +NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID = (0x3F) +NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT = (0x20801340) +NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE +NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID = (0x40) +NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING = (0x20801341) +NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID = (0x41) +NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT = (0x20801342) +NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS = (4) +NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID = (0x42) +NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR = (0x20801343) +NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x43) +NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE = 0 +NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE = 1 +NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD = (0x00000002) +NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD = (0x00000003) +NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS = (0x00000200) +NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS = (0x20801344) +NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE +NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE +NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE = 0 +NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE = 1 +NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID = (0x44) +NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE = 24 +NV2080_CTRL_FB_FS_INFO_INVALID_QUERY = 0x0 +NV2080_CTRL_FB_FS_INFO_FBP_MASK = 0x1 +NV2080_CTRL_FB_FS_INFO_LTC_MASK = 0x2 +NV2080_CTRL_FB_FS_INFO_LTS_MASK = 0x3 +NV2080_CTRL_FB_FS_INFO_FBPA_MASK = 0x4 +NV2080_CTRL_FB_FS_INFO_ROP_MASK = 0x5 +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK = 0x6 +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK = 0x7 +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK = 0x8 +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK = 0x9 +NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK = 0xA +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK = 0xB +NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP = 0xC +NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK = 0xD +NV2080_CTRL_FB_FS_INFO_PAC_MASK = 0xE +NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK = 0xF +NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK = 0x10 +NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK = 0x11 +NV2080_CTRL_FB_FS_INFO_MAX_QUERIES = 120 +NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID = (0x46) +NV2080_CTRL_CMD_FB_GET_FS_INFO = (0x20801346) +NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS = (0x0) +NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW = (0x1) +NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS = (0x2) +NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW = (0x3) +NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS = (0x4) +NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID = (0x47) +NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM = (0x20801347) +NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES = (0x20801348) +NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES = 512 +NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES = 64 +NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x48) +NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID = (0x00000000) +NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE = (0x00000001) +NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO = (0x20801349) +NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM = 0 +NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM = 1 +NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE = 0 +NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE = 1 +NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE = 0 +NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE = 1 +NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID = (0x49) +NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS = (0x20801350) +NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID = (0x50) +NV2080_CTRL_CMD_FB_GET_NUMA_INFO = (0x20801351) +NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64 +NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID = (0x51) +NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = (0x20801352) +NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED = (0x00000001) +NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED = (0x00000002) +NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID = (0x52) +NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE = (0x20801353) +NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID = (0x53) +NV2080_CTRL_CMD_FB_STATS_MAX_OWNER = 200 +NV2080_CTRL_CMD_FB_STATS_GET = (0x2080132a) +NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID = (0x2A) +NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO = (0x20801354) +NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID = (0x54) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = (0x20801355) +NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED = (0x00000000) +NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED = (0x00000001) +NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID = (0x55) +NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION = (0x20801356) +NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE = (0x00000000) +NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE = (0x00000001) +NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID = (0x56) +NV2080_CTRL_CMD_FB_GET_STATUS = (0x20801357) +NV2080_CTRL_FB_STATUS_FAILED = (0x00000000) +NV2080_CTRL_FB_STATUS_READY = (0x00000001) +NV2080_CTRL_FB_STATUS_PENDING = (0x00000002) +NV2080_CTRL_FB_STATUS_NOT_APPLICABLE = (0x00000003) +NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID = (0x57) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = (0x20801358) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED = (0x00000000) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED = (0x00000001) +NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID = (0x58) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = (0x20801359) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED = (0x00000000) +NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED = (0x00000001) +NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID = (0x59) +NV2080_CTRL_CMD_SET_GPFIFO = (0x20801102) +NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS = (16) +NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_FIFO_BIND_ENGINES = (0x20801103) +NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES = (0x20801104) +NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE = (0x00000000) +NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE = (0x00000001) +NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT = (0x20801108) +NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL = (0x000000000) +NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS = (0x000000001) +NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP = (0x000000002) +NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP = (0x000000003) +NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET = (0x000000004) +NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE = (0x000000005) +NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE = (0x000000006) +NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED = (0x000000007) +NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE = (0x000000008) +NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE = (0x000000009) +NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT = (0x00000000a) +NV2080_CTRL_FIFO_INFO_INDEX_MAX = NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT +NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT = (12) +NV2080_CTRL_CMD_FIFO_GET_INFO = (0x20801109) +NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES = (256) +NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL = (0x2080110a) +NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = (0x2080110b) +NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = (64) +NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE = (0x00000000) +NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE = (0x00000001) +NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE = (0x00000000) +NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE = (0x00000001) +NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT = 0x2 +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO = (0x2080110c) +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID = (0xC) +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID = 0x00000000 +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM = 0x00000001 +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH = 0x00000002 +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH = 0x00000003 +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION = (0x2080110d) +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM = 0x00000000 +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM = 0x00000001 +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED = 0x00000000 +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED = 0X00000001 +NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED = 0X00000002 +NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN = 0 +NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER = 1 +NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT = 2 +NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 3 +NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE = 4 +NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3 +NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT = 0 +NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE = 1 +NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE = 2 +NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG = (0x2080110e) +NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT = 32 +NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS = 8 +NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES = 200 +NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE = (0x20801112) +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES = 256 +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES = 32 +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES = 16 +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA = 2 +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN = 16 +NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT = (0x20801113) +NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE = 0x00000001 +NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA = 0x00000002 +NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID = (0x13) +NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY = (0x20801115) +NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT = 0x0 +NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED = 0x1 +NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM = 0x2 +NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE = (0x00000000) +NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE = (0x00000001) +NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID = (0x15) +NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO = (0x20801116) +NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID = (0x16) +NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS = (0x20801117) +NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID = (0x17) +NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = (0x20801118) +NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID = (0x18) +NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS = (0x20801119) +NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS = 4096 +NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID = (0x19) +NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION = (0x2080111a) +NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES = (64) +NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0x1A) +NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 = (0x2080111b) +NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID = (0x1B) +NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE = (0x20801120) +NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE = (0x20801121) +NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID = (0x21) +NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS = (0x20801122) +NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG = 128 +NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO = (0x20801123) +NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID = (0x23) +NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID = (0x20801124) +NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID = (0x24) +NV2080_CTRL_CMD_FLA_RANGE = (0x20803501) +NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE = 0x00000000 +NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE = NVBIT(0) +NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY = NVBIT(1) +NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE = NVBIT(2) +NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY = NVBIT(3) +NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK = (0x20803502) +NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_FLA_GET_RANGE = (0x20803503) +NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS = (0x20803504) +NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID = (0x4) +FALCON_ID_PMU = (NV2080_ENGINE_TYPE_PMU) +FALCON_ID_DPU = (NV2080_ENGINE_TYPE_DPU) +FALCON_ID_SEC2 = (NV2080_ENGINE_TYPE_SEC2) +FALCON_ID_FBFLCN = (NV2080_ENGINE_TYPE_FBFLCN) +NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE = (0x20803101) +NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE = 0x00 +NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END = 0x01 +NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN = 0x02 +NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END = 0x03 +NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK = 0x04 +NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN = 0x05 +NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END = 0x06 +NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY = 0x07 +NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT = 0x08 +NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 = 0x09 +NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END = 0x0A +NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN = 0x0B +NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END = 0x0C +NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY = 0x0D +NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID = 0xFF +NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH = (0x20803118) +NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID = (0x18) +NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT = 0x0 +NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON = 0x1 +NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV = 0x2 +NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB = 0x3 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT = (27) +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE = (20) +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT = (28) +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE = (24) +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD = 0x0 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 = 0x1 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK = 0x2 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK = 0x3 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED = 0x4 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE = 0xF0 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT = 10 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED = 0x000000 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL = 0x000001 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT = 6 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID = 0x000 +NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL = 0x001 +NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT = 0 +NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON = 1 +NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT = 2 +NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED = 0 +NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED = 1 +NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED = 0 +NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED = 1 +NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED = 0 +NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED = 1 +NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT = (0x20) +NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES = (0x120) +NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES = (0x24) +NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO = (0x20803120) +NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET = (0x20803122) +NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET = (0x20803123) +NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID = (0x23) +NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO = (0x20803124) +NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x24) +NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = (0x20803125) +NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x25) +NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION = (0x20802300) +NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID = (0x00) +NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT = (0x20802301) +NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID = (0x01) +NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT = (0x20802302) +NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID = (0x02) +NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION = (0x20802303) +NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID = (0x03) +NV_GRID_LICENSE_INFO_MAX_LENGTH = (128) +NV_GRID_LICENSE_FEATURE_VPC_EDITION = "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +NV_GRID_LICENSE_FEATURE_VAPPS_EDITION = "GRID-Virtual-Apps,3.0" +NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION = "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +NV_GRID_LICENSE_FEATURE_GAMING_EDITION = "GRID-vGaming,8.0" +NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION = "NVIDIA-vComputeServer,9.0" +NV_GRID_LICENSED_PRODUCT_VWS = "NVIDIA RTX Virtual Workstation" +NV_GRID_LICENSED_PRODUCT_GAMING = "NVIDIA Cloud Gaming" +NV_GRID_LICENSED_PRODUCT_VPC = "NVIDIA Virtual PC" +NV_GRID_LICENSED_PRODUCT_VAPPS = "NVIDIA Virtual Applications" +NV_GRID_LICENSED_PRODUCT_COMPUTE = "NVIDIA Virtual Compute Server" +NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 = (0x00000002) +NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT = (0x00000004) +NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 = (0x00000012) +NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 = (0x00000013) +NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED = (0x0000001b) +NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS = (0x0000001f) +NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD = (0x00000022) +NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE = (0x00000025) +NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED = (0x00000027) +NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED = (0x00000028) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT = (0x00000029) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE = (0x0000002a) +NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM = (0x0000002b) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION = (0x0000002c) +NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY = (0x0000002d) +NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM = (0x0000002f) +NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY = (0x00000030) +NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE = (0x00000031) +NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED = (0x00000033) +NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED = (0x00000034) +NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED = (0x00000035) +NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY = (0x00000036) +NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY = (0x00000037) +NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY = (0x0000003a) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY = (0x0000003b) +NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU = (0x0000003c) +NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY = (0x0000003d) +NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED = (0x0000003f) +NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE = (0x00000041) +NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE = (0x00000000) +NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P = (0x00000001) +NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V = (0x00000002) +NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV = (0x00000003) +NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED = (0x00000000) +NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED = (0x00000001) +NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED = (0x00000002) +NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING = (0x00000003) +NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING = (0x00000004) +NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED = (0x00000000) +NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED = (0x00000001) +NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED = (0x00000002) +NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES = (0x00000001) +NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO = (0x00000000) +NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES = (0x00000001) +NV2080_CTRL_CMD_GPU_GET_INFO = (0x20800101) +NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_GPU_GET_INFO_V2 = (0x20800102) +NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_GPU_GET_NAME_STRING = (0x20800110) +NV2080_GPU_MAX_NAME_STRING_LENGTH = (0x0000040) +NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII = (0x00000000) +NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE = (0x00000001) +NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID = (0x10) +NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = (0x20800111) +NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID = (0x11) +NV2080_CTRL_CMD_GPU_SET_POWER = (0x20800112) +NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 = (0x00000000) +NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 = (0x00000001) +NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 = (0x00000002) +NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 = (0x00000003) +NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 = (0x00000004) +NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 = (0x00000007) +NV2080_CTRL_CMD_GPU_GET_SDM = (0x20800118) +NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID = (0x18) +NV2080_CTRL_CMD_GPU_SET_SDM = (0x20800120) +NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = (0x20800119) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID = (0x19) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE = (0x00000000) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL = (0x00000001) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL = (0x00000002) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL = (0x00000003) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL = (0x00000004) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU = (0x00000005) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER = (0x00000006) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA = (0x00000007) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL = (0x00000008) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL = (0x00000009) +NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN = (0xFFFFFFFF) +NV2080_CTRL_GPU_REG_OP_READ_32 = (0x00000000) +NV2080_CTRL_GPU_REG_OP_WRITE_32 = (0x00000001) +NV2080_CTRL_GPU_REG_OP_READ_64 = (0x00000002) +NV2080_CTRL_GPU_REG_OP_WRITE_64 = (0x00000003) +NV2080_CTRL_GPU_REG_OP_READ_08 = (0x00000004) +NV2080_CTRL_GPU_REG_OP_WRITE_08 = (0x00000005) +NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL = (0x00000000) +NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX = (0x00000001) +NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC = (0x00000002) +NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM = (0x00000004) +NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP = (0x00000008) +NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP = (0x00000010) +NV2080_CTRL_GPU_REG_OP_TYPE_FB = (0x00000020) +NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD = (0x00000040) +NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE = (0x00000080) +NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS = (0x00) +NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP = (0x01) +NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE = (0x02) +NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET = (0x04) +NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP = (0x08) +NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK = (0x10) +NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS = (0x20) +NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = (0x20800122) +NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_CMD_GPU_GET_ENGINES = (0x20800123) +NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID = (0x23) +NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = (0x20800170) +NV2080_GPU_MAX_ENGINES_LIST_SIZE = 0x54 +NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID = (0x70) +NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST = (0x20800124) +NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID = (0x24) +NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO = (0x20800125) +NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID = (0x25) +NV2080_CTRL_CMD_GPU_QUERY_MODE = (0x20800128) +NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE = (0x00000000) +NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE = (0x00000001) +NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE = (0x00000002) +NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID = (0x28) +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN = 0 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM = 1 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH = 2 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB = 3 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL = 4 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB = 5 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL = 6 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL = 7 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK = 8 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT = 9 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP = 10 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP = 11 +NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP = 12 +NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES = 16 +NV2080_CTRL_CMD_GPU_PROMOTE_CTX = (0x2080012b) +NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID = (0x2B) +NV2080_CTRL_CMD_GPU_EVICT_CTX = (0x2080012c) +NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID = (0x2C) +NV2080_CTRL_CMD_GPU_INITIALIZE_CTX = (0x2080012d) +NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID = (0x2D) +NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM = (0x00000000) +NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS = (0x00000001) +NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS = (0x00000002) +NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES = (0x00000000) +NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO = (0x00000001) +NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO = (0x00000000) +NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES = (0x00000001) +NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR = (0x2080012e) +NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = (0x2080012f) +NV2080_CTRL_GPU_ECC_UNIT_GSP = (0x0000001D) +NV2080_CTRL_GPU_ECC_UNIT_COUNT = (0x00000024) +NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED = (0x00000000) +NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW = (0x00000001) +NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE = 0 +NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE = 1 +NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE = 2 +NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID = (0x2F) +NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES = (0x20800130) +NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE = (0x00000000) +NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE = (0x00000001) +NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED = (0x00000002) +NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS = (0x00000003) +NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x30) +NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = (0x20800131) +NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x31) +NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = (0x20800133) +NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED = (0x00000000) +NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED = (0x00000001) +NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x33) +NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION = (0x20800134) +NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE = (0x00000000) +NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE = (0x00000001) +NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x34) +NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS = (0x20800136) +NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE = (0x00000000) +NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE = (0x00000001) +NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE = (0x00000002) +NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE = 0 +NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE = 1 +NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID = (0x36) +NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO = (0x20800137) +NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID = (0x37) +NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO = (0x20800138) +NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID = (0x38) +NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO = (0x20800139) +NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x39) +NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = (0x2080013f) +NV2080_GPU_MAX_MARKETING_NAME_LENGTH = (0x00000018) +NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH = (0x00000010) +NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH = (0x00000014) +NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH = (0x00000006) +NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH = (0x00000014) +NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID = (0x3F) +NV2080_CTRL_CMD_GPU_GET_ID = (0x20800142) +NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID = (0x42) +NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE = (0x20800143) +NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x43) +NV2080_CTRL_GPU_DEBUG_MODE_ENABLED = (0x00000001) +NV2080_CTRL_GPU_DEBUG_MODE_DISABLED = (0x00000002) +NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE = (0x20800144) +NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x44) +NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = (0x20800147) +NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS = (0x00000020) +NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID = (0x47) +NV2080_CTRL_CMD_GPU_GET_GID_INFO = (0x2080014a) +NV2080_GPU_MAX_GID_LENGTH = (0x000000100) +NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH = (0x000000010) +NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID = (0x4A) +NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII = (0x00000000) +NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY = (0x00000002) +NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 = (0x00000000) +NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = (0x2080014b) +NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN = 3 +NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID = (0x4B) +NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO = (0x2080014c) +NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID = (0x4C) +NV2080_CTRL_CMD_GPU_GET_IP_VERSION = (0x2080014d) +NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4D) +NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY = (0x00000001) +NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC = (0x00000002) +NV2080_CTRL_GPU_GET_IP_VERSION_PMGR = (0x00000003) +NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU = (0x00000004) +NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON = (0x00000005) +NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS = 0 +NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS = 1 +NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT = (0x20800153) +NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID = (0x53) +NV2080_CTRL_CMD_GPU_GET_ILLUM = (0x20800154) +NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID = (0x54) +NV2080_CTRL_CMD_GPU_SET_ILLUM = (0x20800155) +NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0x55) +NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = (0x20800156) +NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN = 16 +NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID = (0x56) +NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT = (0x20800157) +NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO = (0x2080015a) +NV2080_CTRL_MAX_PHYSICAL_BRIDGE = (100) +NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x5A) +NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU = (0x2080015b) +NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID = (0x5B) +NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS = (0x2080015f) +NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID = (0x5F) +NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING = (0x00000000) +NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE = (0x00000001) +NV2080_CTRL_CMD_GPU_GET_VPR_CAPS = (0x20800160) +NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID = (0x60) +NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR = (0x20800167) +NV2080_CTRL_CMD_GPU_GET_PES_INFO = (0x20800168) +NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT = 10 +NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID = (0x68) +NV2080_CTRL_CMD_GPU_GET_OEM_INFO = (0x20800169) +NV2080_GPU_MAX_OEM_INFO_LENGTH = (0x000001F8) +NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID = (0x69) +NV2080_CTRL_CMD_GPU_GET_VPR_INFO = (0x2080016b) +NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID = (0x6B) +NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY = (0x2080016c) +NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x6C) +NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS = (0x2080016d) +NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x6D) +NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES = 0x200 +NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x6E) +NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO = (0x2080016e) +NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x6F) +NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR = (0x2080016f) +NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID = (0x72) +NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT = (0x20800172) +NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID = (0x73) +NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS = (0x20800173) +NV_GI_UUID_LEN = 16 +NV2080_CTRL_GPU_PARTITION_ID_INVALID = 0xFFFFFFFF +NV2080_CTRL_GPU_MAX_PARTITIONS = 0x00000008 +NV2080_CTRL_GPU_MAX_PARTITION_IDS = 0x00000009 +NV2080_CTRL_GPU_MAX_SMC_IDS = 0x00000008 +NV2080_CTRL_GPU_MAX_GPC_PER_SMC = 0x0000000c +NV2080_CTRL_GPU_MAX_CE_PER_SMC = 0x00000008 +NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL = 0x00000000 +NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF = 0x00000001 +NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER = 0x00000002 +NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH = 0x00000003 +NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE = 4 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL = 0x00000000 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF = 0x00000001 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF = 0x00000002 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER = 0x00000003 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER = 0x00000004 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH = 0x00000005 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 = 0x00000006 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 = 0x00000007 +NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE = 8 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL = 0x00000001 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF = 0x00000002 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF = 0x00000003 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER = 0x00000004 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH = 0x00000005 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 = 0x00000006 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 = 0x00000007 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE = 0x00000000 +NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE = 8 +NV2080_CTRL_GPU_PARTITION_MAX_TYPES = 40 +NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE = 0 +NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE = 1 +NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE = 0 +NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE = 1 +NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID = (0x74) +NV2080_CTRL_CMD_GPU_SET_PARTITIONS = (0x20800174) +NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID = (0x75) +NV2080_CTRL_CMD_GPU_GET_PARTITIONS = (0x20800175) +NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION = (0x20800176) +NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID = (0x76) +NV2080_CTRL_GPU_FAULT_PACKET_SIZE = 32 +NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT = (0x20800177) +NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID = (0x77) +NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU = (0x20800178) +NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID = (0x78) +NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE = (0x20800179) +NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID = (0x79) +NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL = (0xFFFFFFFF) +NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR = (0xFFFFFFFB) +NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID = (0xFFFFFFFF) +NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR = (0xFFFFFFFB) +NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID = (0x2080017a) +NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID = (0x7A) +NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL = (0xFFFFFFFF) +NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR = (0xFFFFFFFB) +NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS = (0x2080017b) +NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x7B) +NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 0x00000001 +NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 0x00000002 +NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 0x00000004 +NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 0x00000008 +NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 0x00000010 +NV2080_GPU_NVFBC_MAX_SESSION_COUNT = 256 +NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x7C) +NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO = (0x2080017c) +NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID = (0xe6) +NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX = (0x208001e6) +NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE = (0x2080017e) +NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID = (0x7E) +NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB = 0x02000000 +NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB = 0x04000000 +NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB = 0x08000000 +NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB = 0x10000000 +NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB = 0x20000000 +NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY = (0x20800181) +NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID = (0x81) +NV2080_CTRL_CMD_GPU_GET_CACHED_INFO = (0x20800182) +NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID = (0x82) +NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE = (0x20800183) +NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY = 0 +NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF = 1 +NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG = 2 +NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0x83) +NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID = (0x85) +NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS = (0x20800185) +NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE = (0x20800188) +NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID = (0x88) +NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID = (0x8A) +NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC = (0x2080018a) +NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID = (0x8B) +NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = (0x2080018b) +NV2080_CTRL_CMD_GPU_GET_PIDS = (0x2080018d) +NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT = 950 +NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID = (0x8D) +NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS = (0x00000000) +NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST = (0x00000001) +NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE = (0x00000000) +NV2080_CTRL_GPU_PID_INFO_INDEX_MAX = NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE +NV2080_CTRL_CMD_GPU_GET_PID_INFO = (0x2080018e) +NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT = 200 +NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID = (0x8E) +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT = (0x20800192) +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID = 0 +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 = 1 +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 = 2 +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL = 3 +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE = 4 +NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID = (0x92) +NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE = 0 +NV2080_CTRL_GPU_COMPUTE_POLICY_MAX = 1 +NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x94) +NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = (0x20800195) +NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX = 32 +NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x95) +NV2080_CTRL_CMD_GPU_GET_GFID = (0x20800196) +NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID = (0x96) +NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY = (0x20800197) +NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID = (0x97) +NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST = (0x20800198) +NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID = (0x98) +NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR = (0x20800199) +NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x99) +NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES = (0x2080019b) +NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS = 0xC8 +NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID = (0x9B) +NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING = (0x2080019c) +NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID = (0x9C) +NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS = (0x2080019d) +NV2080_CTRL_REG_OPS_ARRAY_MAX = 100 +NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID = (0x9D) +NV2080_GET_P2P_CAPS_UUID_LEN = 16 +NV2080_CTRL_CMD_GET_P2P_CAPS = (0x208001a0) +NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xA0) +NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xA2) +NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES = (0x208001a2) +NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED = 0 +NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED = 1 +NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS = 2 +NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE = 3 +NV2080_GPU_FABRIC_CLUSTER_UUID_LEN = 16 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED = 0 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE = 1 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE = 2 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED = 0 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE = 1 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE = 2 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1 +NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2 +NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xA3) +NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = (0x208001a3) +NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = (0x208001a4) +GPU_PART_NUMBER_FMT = "%4X-%s-%X%X" +NV2080_MAX_CHIP_SKU_LENGTH = 0x00000004 +NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID = (0xA4) +NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP = (0x208001a5) +NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID = (0xA5) +NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS = (0x208001a6) +NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP = (0x208001a7) +NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU = (0x208001a8) +NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX = 50 +NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID = (0xA6) +NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID = (0xA7) +NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID = (0xA8) +NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET = (0x208001a9) +NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET = (0x208001aa) +NV2080_CTRL_CMD_GPU_GET_RESET_STATUS = (0x208001ab) +NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAB) +NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ac) +NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ad) +NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS = (0x208001ae) +NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAE) +NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID = (0xAF) +NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 = (0x208001af) +NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS = 0x40 +NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO = (0x208001b0) +NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID = (0xB0) +NV2080_CTRL_CMD_GPU_GET_VF_CAPS = (0x208001b1) +NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID = (0xB1) +NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = (0x208001b2) +NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID = (0xB2) +NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID = (0xe4) +NV2080_CTRL_GPU_GET_FIPS_STATUS = (0x208001e4) +NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU = 0x2 +NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU = 0xC +NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC = (0x18) +NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT = (0x1a) +NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID = (0xB3) +NV2080_CTRL_GPU_GET_RAFTS_FS_MASK = (0x208001b3) +NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY = (0x208001e5) +NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID = (0xe5) +NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK = (0x208001e7) +NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0xe7) +NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS = 0x00000001 +NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL = 0x00000002 +NV2080_GPUMON_PID_INVALID = ((NvU32)(~0)) +NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE = 0x0 +NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID = 0x1 +NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL = 0x2 +NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS = NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS +NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 +NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK +NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT +NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT +NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE +NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT +NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT +NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR +NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT +NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT +NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT +NV2080_CTRL_GR_INFO_INDEX_SM_VERSION = NV0080_CTRL_GR_INFO_INDEX_SM_VERSION +NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM +NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP +NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES +NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES +NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY +NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY +NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS +NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC +NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS +NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT +NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC +NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP +NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT +NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT +NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES +NV2080_CTRL_GR_INFO_INDEX_DUMMY = NV0080_CTRL_GR_INFO_INDEX_DUMMY +NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES +NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES +NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS +NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG +NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET +NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET +NV2080_CTRL_GR_INFO_INDEX_MAX = NV0080_CTRL_GR_INFO_INDEX_MAX +NV2080_CTRL_GR_INFO_MAX_SIZE = NV0080_CTRL_GR_INFO_MAX_SIZE +NV2080_CTRL_GR_INFO_SM_VERSION_NONE = (0x00000000) +NV2080_CTRL_GR_INFO_SM_VERSION_1_05 = (0x00000105) +NV2080_CTRL_GR_INFO_SM_VERSION_1_1 = (0x00000110) +NV2080_CTRL_GR_INFO_SM_VERSION_1_2 = (0x00000120) +NV2080_CTRL_GR_INFO_SM_VERSION_1_3 = (0x00000130) +NV2080_CTRL_GR_INFO_SM_VERSION_1_4 = (0x00000140) +NV2080_CTRL_GR_INFO_SM_VERSION_1_5 = (0x00000150) +NV2080_CTRL_GR_INFO_SM_VERSION_2_0 = (0x00000200) +NV2080_CTRL_GR_INFO_SM_VERSION_2_1 = (0x00000210) +NV2080_CTRL_GR_INFO_SM_VERSION_2_2 = (0x00000220) +NV2080_CTRL_GR_INFO_SM_VERSION_3_0 = (0x00000300) +NV2080_CTRL_GR_INFO_SM_VERSION_3_1 = (0x00000310) +NV2080_CTRL_GR_INFO_SM_VERSION_3_2 = (0x00000320) +NV2080_CTRL_GR_INFO_SM_VERSION_3_3 = (0x00000330) +NV2080_CTRL_GR_INFO_SM_VERSION_3_5 = (0x00000350) +NV2080_CTRL_GR_INFO_SM_VERSION_3_6 = (0x00000360) +NV2080_CTRL_GR_INFO_SM_VERSION_3_8 = (0x00000380) +NV2080_CTRL_GR_INFO_SM_VERSION_3_9 = (0x00000390) +NV2080_CTRL_GR_INFO_SM_VERSION_4_0 = (0x00000400) +NV2080_CTRL_GR_INFO_SM_VERSION_5_0 = (0x00000500) +NV2080_CTRL_GR_INFO_SM_VERSION_5_02 = (0x00000502) +NV2080_CTRL_GR_INFO_SM_VERSION_5_03 = (0x00000503) +NV2080_CTRL_GR_INFO_SM_VERSION_6_0 = (0x00000600) +NV2080_CTRL_GR_INFO_SM_VERSION_6_01 = (0x00000601) +NV2080_CTRL_GR_INFO_SM_VERSION_6_02 = (0x00000602) +NV2080_CTRL_GR_INFO_SM_VERSION_7_0 = (0x00000700) +NV2080_CTRL_GR_INFO_SM_VERSION_7_01 = (0x00000701) +NV2080_CTRL_GR_INFO_SM_VERSION_7_02 = (0x00000702) +NV2080_CTRL_GR_INFO_SM_VERSION_7_03 = (0x00000703) +NV2080_CTRL_GR_INFO_SM_VERSION_7_05 = (0x00000705) +NV2080_CTRL_GR_INFO_SM_VERSION_8_02 = (0x00000802) +NV2080_CTRL_GR_INFO_SM_VERSION_8_06 = (0x00000806) +NV2080_CTRL_GR_INFO_SM_VERSION_8_07 = (0x00000807) +NV2080_CTRL_GR_INFO_SM_VERSION_8_08 = (0x00000808) +NV2080_CTRL_GR_INFO_SM_VERSION_8_09 = (0x00000809) +NV2080_CTRL_GR_INFO_SM_VERSION_9_00 = (0x00000900) +NV2080_CTRL_GR_INFO_SM_VERSION_10_00 = (0x00000A00) +NV2080_CTRL_GR_INFO_SM_VERSION_10_01 = (0x00000A01) +NV2080_CTRL_GR_INFO_SM_VERSION_10_04 = (0x00000A04) +NV2080_CTRL_GR_INFO_SM_VERSION_5_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_02) +NV2080_CTRL_GR_INFO_SM_VERSION_5_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_03) +NV2080_CTRL_GR_INFO_SM_VERSION_6_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_01) +NV2080_CTRL_GR_INFO_SM_VERSION_6_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_02) +NV2080_CTRL_GR_INFO_SM_VERSION_7_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_01) +NV2080_CTRL_GR_INFO_SM_VERSION_7_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_02) +NV2080_CTRL_GR_INFO_SM_VERSION_7_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_03) +NV2080_CTRL_GR_INFO_SM_VERSION_7_5 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_05) +NV2080_CTRL_GR_INFO_SM_VERSION_8_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_02) +NV2080_CTRL_GR_INFO_SM_VERSION_8_6 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_06) +NV2080_CTRL_GR_INFO_SM_VERSION_8_7 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_07) +NV2080_CTRL_GR_INFO_SM_VERSION_8_8 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_08) +NV2080_CTRL_GR_INFO_SM_VERSION_8_9 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_09) +NV2080_CTRL_GR_INFO_SM_VERSION_9_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_9_00) +NV2080_CTRL_GR_INFO_SM_VERSION_10_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_00) +NV2080_CTRL_GR_INFO_SM_VERSION_10_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_01) +NV2080_CTRL_GR_INFO_SM_VERSION_10_4 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_04) +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE = 0x0 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE = 0x1 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE = 0x0 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE = 0x1 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE = 0x0 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE = 0x1 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE = 0x0 +NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE = 0x1 +NV2080_CTRL_CMD_GR_GET_INFO = (0x20801201) +NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE = (0x20801205) +NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL = (0x00000000) +NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW = (0x00000001) +NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER = (0x00000002) +NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = (0x20801206) +NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x6) +NV2080_CTRL_CMD_GR_CTXSW_PM_MODE = (0x20801207) +NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID = (0x7) +NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW = (0x00000000) +NV2080_CTRL_CTXSW_PM_MODE_CTXSW = (0x00000001) +NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW = (0x00000002) +NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = (0x20801208) +NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_CMD_GR_CTXSW_PM_BIND = (0x20801209) +NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND = (0x2080123a) +NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0x3A) +NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES = 128 +NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP = (0x2080120a) +NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE = (0x2080120e) +NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW = (0x00000000) +NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW = (0x00000001) +NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = (0x2080120f) +NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT = 240 +NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID = (0xF) +NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = (0x20801210) +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID = (0x10) +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE = (0x00000000) +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET = (0x00000001) +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE = (0x00000000) +NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET = (0x00000001) +NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI = (0x00000000) +NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP = (0x00000001) +NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL = (0x00000002) +NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI = (0x00000000) +NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA = (0x00000001) +NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP = (0x00000002) +NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND = (0x20801211) +NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID = (0x11) +NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE = (0x20801212) +NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_PC_SAMPLING_MODE_DISABLED = (0x00000000) +NV2080_CTRL_PC_SAMPLING_MODE_ENABLED = (0x00000001) +NV2080_CTRL_CMD_GR_GET_ROP_INFO = (0x20801213) +NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x13) +NV2080_CTRL_CMD_GR_GET_CTXSW_STATS = (0x20801215) +NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID = (0x15) +NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE = (0x00000000) +NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE = (0x00000001) +NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = (0x20801218) +NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x18) +NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT = 64 +NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO = (0x20801219) +NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x19) +NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN = 0 +NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM = 1 +NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM = 2 +NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = (0x2080121b) +NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT = 512 +NV2080_CTRL_GR_DISABLED_SM_VGPC_ID = 0xFF +NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x1B) +NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL = (0x2080121c) +NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID = (0x1C) +NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT = 10 +NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT = 10 +NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA = (0x2080121d) +NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID = (0x1D) +NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE = (0x2080121e) +NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x1E) +NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE = (0x2080121f) +NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID = (0x1F) +NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE = (0x20801220) +NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS = 64 +NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS = (0x20801221) +NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID = (0x21) +NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS = (0x20801222) +NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_CMD_GR_GET_CAPS_V2 = (0x20801227) +NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x27) +NV2080_CTRL_CMD_GR_GET_INFO_V2 = (0x20801228) +NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x28) +NV2080_CTRL_CMD_GR_GET_GPC_MASK = (0x2080122a) +NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID = (0x2A) +NV2080_CTRL_CMD_GR_GET_TPC_MASK = (0x2080122b) +NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID = (0x2B) +NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x2080122c) +NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x2C) +NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES = (0x2080122d) +NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x2D) +NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = (0x20801230) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 = (0x6) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 = (0x6) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 = (0x6) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 = (0x6) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED = (0x0) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 = (0x1) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 = (0x2) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 = (0x3) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 = (0x4) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 = (0x5) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 = (0x6) +NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x30) +NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID = (0x20801231) +NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID = (0x31) +NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK = (0x20801232) +NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID = (0x32) +NV2080_CTRL_CMD_GR_GET_PPC_MASK = (0x20801233) +NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID = (0x33) +NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC = (0x20801234) +NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID = (0x34) +NV2080_CTRL_CMD_GR_GET_CTXSW_MODES = (0x20801235) +NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x35) +NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP = (0x20801236) +NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0x36) +NV2080_CTRL_CMD_GR_GET_ZCULL_MASK = (0x20801237) +NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID = (0x37) +NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 = (0x20801238) +NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID = (0x38) +NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO = (0x20801239) +NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID = (0x39) +NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK = (0x2080123b) +NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0x3b) +NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO = (0x20803801) +NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES = 96 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE = 32 +NV2080_CTRL_GRMGR_MAX_SMC_IDS = 8 +NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID = 0 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT = 1 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP = 2 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK = 3 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK = 4 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP = 5 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK = 6 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS = 7 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK = 8 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID = 9 +NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK = 10 +NV2080_CTRL_CMD_GSP_GET_FEATURES = (0x20803601) +NV2080_GSP_MAX_BUILD_VERSION_LENGTH = (0x0000040) +NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE = (0x00000000) +NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE = (0x00000001) +NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE = (0x00000000) +NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE = (0x00000001) +NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS = (0x20803602) +NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS = (0x20803603) +NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS = (0x20803604) +NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX = 64 +NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK = (0x20804101) +NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE = (0x20804102) +NV2080_CTRL_I2C_VERSION_0 = 0x00 +NV2080_CTRL_I2C_MAX_ENTRIES = 256 +NV2080_CTRL_I2C_MAX_REG_LEN = 8 +NV2080_CTRL_I2C_MAX_ADDR_ENTRIES = 20 +NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC = (0x00000001) +NV2080_CTRL_I2C_FLAGS_PRIVILEGE = (0x00000002) +NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED = (0x00000004) +NV2080_CTRL_I2C_FLAGS_PX3540 = (0x00000010) +NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED = (0x00000008) +NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_I2C_READ_BUFFER = (0x20800601) +NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_I2C_WRITE_BUFFER = (0x20800602) +NV2080_CTRL_CMD_I2C_READ_REG = (0x20800603) +NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_I2C_WRITE_REG = (0x20800604) +NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_I2C_ACCESS = (0x20800610) +NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID = (0x10) +NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE = 0x1 +NV2080_CTRL_I2C_ACCESS_CMD_RELEASE = 0x2 +NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE = 0x3 +NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE = 0x4 +NV2080_CTRL_I2C_ACCESS_CMD_NULL = 0x5 +NV2080_CTRL_I2C_ACCESS_CMD_RESET = 0x6 +NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT = 0x11 +NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE = 0x12 +NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE = 0x13 +NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER = 0x14 +NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER = 0x15 +NV2080_CTRL_I2C_ACCESS_CMD_START = 0x17 +NV2080_CTRL_I2C_ACCESS_CMD_STOP = 0x18 +NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE = 0x20 +NV2080_CTRL_I2C_ACCESS_FLAG_START = 0x1 +NV2080_CTRL_I2C_ACCESS_FLAG_STOP = 0x2 +NV2080_CTRL_I2C_ACCESS_FLAG_ACK = 0x4 +NV2080_CTRL_I2C_ACCESS_FLAG_RAB = 0x8 +NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS = 0x10 +NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE = 0x20 +NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED = 0x40 +NV2080_CTRL_I2C_ACCESS_FLAG_RESTART = 0x80 +NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT = 0x100 +NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT = 0x200 +NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT = 0x400 +NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT = 0x800 +NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT = 0x1000 +NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC = 0x0 +NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY = 0x1 +NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY = 0x2 +NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY = 0x3 +NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY = 0x4 +NV2080_CTRL_I2C_ACCESS_PORT_1 = 0x1 +NV2080_CTRL_I2C_ACCESS_PORT_2 = 0x2 +NV2080_CTRL_I2C_ACCESS_PORT_3 = 0x3 +NV2080_CTRL_I2C_ACCESS_PORT_4 = 0x4 +NV2080_CTRL_I2C_ACCESS_PORT_5 = 0x5 +NV2080_CTRL_I2C_ACCESS_PORT_6 = 0x6 +NV2080_CTRL_I2C_ACCESS_PORT_7 = 0x7 +NV2080_CTRL_I2C_ACCESS_PORT_8 = 0x8 +NV2080_CTRL_I2C_ACCESS_PORT_9 = 0x9 +NV2080_CTRL_I2C_ACCESS_PORT_10 = 0x10 +NV2080_CTRL_I2C_ACCESS_NUM_PORTS = NV2080_CTRL_I2C_ACCESS_PORT_10 +NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS = 0x0 +NV2080_CTRL_I2C_ACCESS_STATUS_ERROR = 0x1 +NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR = 0x2 +NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY = 0x3 +NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND = 0x4 +NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING = 0x5 +NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE = (0x20800620) +NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01) +NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG = (0x20800a1c) +NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER = (0x20800a1d) +NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES = 64 +NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1D) +NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER = (0x20800a1e) +NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1E) +NV2080_CTRL_INTERNAL_GR_MAX_ENGINES = 8 +NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x20) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS = (0x20800a1f) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID = (0x1F) +NV2080_CTRL_INTERNAL_GR_MAX_SM = 240 +NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x23) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER = (0x20800a22) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x22) +NV2080_CTRL_CMD_INTERNAL_MAX_BSPS = 8 +NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS = 8 +NV2080_CTRL_INTERNAL_GR_MAX_GPC = 12 +NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT = 10 +NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x27) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS = (0x20800a26) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x26) +NV2080_CTRL_KGR_MAX_BUFFER_PTES = 128 +NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES = (0x20800a28) +NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID = (0x28) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x2B) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO = (0x20800a2a) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID = (0x2A) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2D) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO = (0x20800a2c) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2C) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2F) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO = (0x20800a2e) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2E) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x31) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS = (0x20800a30) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x30) +NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = 0x1a +NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x33) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO = (0x20800a32) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x32) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x35) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER = (0x20800a34) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x34) +NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO = (0x20800a36) +NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX = 16 +NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID = (0x36) +NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE = (0x20800a37) +NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE = (0x20800a38) +NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x37) +NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x38) +NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET = (0x20800a39) +NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET = (0x20800a3a) +NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET = (0x20800a3b) +NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x39) +NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID = (0x3A) +NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x3B) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE = (0x20800a3d) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3C) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3D) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3E) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES = (0x20800a3f) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3F) +NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES = 512 +NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE = (0x20800a40) +NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x40) +NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP = (0x20800a41) +NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE = 4096 +NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES = 4096 +NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID = (0x41) +NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x43) +NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a44) +NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x44) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a43) +NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x45) +NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR = (0x20800a46) +NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x46) +NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x47) +NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES = (0x20800a48) +NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x48) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM = (0x20800a49) +NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID = (0x49) +NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS = (0x20800a4a) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION = (0x20800a4b) +NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4B) +NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE = (0x20800a4c) +NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID = (0x4C) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR = (0x20800a4d) +NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID = (0x4D) +NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES = 60 +NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x4F) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM = (0x20800a51) +NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID = (0x51) +NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE = 4 +NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x52) +NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS = 2 +NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID = 64 +NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS = (0x20800a53) +NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID = (0x53) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO = (0x20800a54) +NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID = (0x54) +NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO = (0x20800a55) +NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID = (0x55) +NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE = (0x00000000) +NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM = (0x00000001) +NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 = (0x00000002) +NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 = (0x00000003) +NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR = (0x20800a70) +NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL = (0x20800a71) +NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID = (0x71) +NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE = (0x20800a72) +NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID = (0x72) +NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX = (0x20800a73) +NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID = (0x73) +NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING = (0x20800a74) +NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x74) +NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING = (0x20800a75) +NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x75) +NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES = (0x20800a57) +NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES = 128 +NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID = (0x57) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER = (0x20800a58) +NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID = (0x58) +NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO = (0x20800a59) +NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x59) +NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES = (0x20800a5a) +NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x5A) +NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE = (0x20800a5b) +NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID = (0x5B) +NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE = (0x20800a5c) +NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE = 128 +NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID = (0x5C) +NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR = (0x00000000) +NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK = (0x20800a98) +NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID = (0x98) +NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET = (0x20800a99) +NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID = (0x99) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES = (0x20800a5d) +NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID = (0x5D) +NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a60) +NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID = 15 +NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x60) +NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS = (0x20800a61) +NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID = (0x61) +NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES = (0x20800a63) +NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x63) +NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES = (0x20800a65) +NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x65) +NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a66) +NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x66) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a68) +NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x68) +NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a67) +NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x67) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE = (0x20800a6b) +NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE = 8 +NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID = (0x6B) +NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT = (0x20800a6a) +NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x20800a7a) +NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR = (0x20800a7c) +NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE = (0x20800a81) +NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x81) +NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X = (0x20800a9a) +NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID = (0x9A) +NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE = 0 +NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK = 1 +NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST = NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK +NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM = (0x2) +NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL = (0x20800a7e) +NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7E) +NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS = (0x20800a7f) +NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID = (0x7F) +NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO = (0x20800a80) +NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID = (0x80) +NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER = (0x20800a9b) +NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES = 256 +NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9B) +NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER = (0x20800a9c) +NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE = (0x00000000) +NV2080_CTRL_FAULT_BUFFER_REPLAYABLE = (0x00000001) +NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9d) +NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES = 3000 +NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9D) +NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9e) +NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9E) +NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER = (0x20800a9f) +NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID = (0x9F) +NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X = (0x20800aa0) +NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID = (0xA0) +NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X = (0x20800aa1) +NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID = (0xA1) +NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO = (0x20800aa2) +NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES = 8 +NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 12 +NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0xA2) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE = (0x20800aa3) +NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0xA3) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE = (0x20800aa4) +NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA4) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES = (0x20800aa5) +NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA5) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES = (0x20800aa6) +NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA6) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x20800a69) +NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x69) +NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa7) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa8) +NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE = (0x20800aa9) +NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE = (0x20800aaa) +NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE = 4 +NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA7) +NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA8) +NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA9) +NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xAA) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT = (0x20800a6c) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID = (0x6c) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL = (0x00000001) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST = (0x00000002) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST = (0x00000004) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL = (0x00000008) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN = (0x00000010) +NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL = (0x00000020) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES = (0x20800a6d) +NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO = (0x20800aac) +NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xac) +NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG = (0x20800a88) +NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID = (0x88) +NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS = (0x20800a8a) +NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE = 32 +NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID = (0x8a) +NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS = (0x20800a8b) +NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID = (0x8b) +NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID = (0x20800a8c) +NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID = (0x8c) +NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG = (0x20800a8d) +NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID = (0x8d) +NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR = (0x20800aad) +NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID = (0xae) +NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR = (0x20800aae) +NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS = (0x20800ab0) +NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID = (0xb0) +NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT = (0x20800ab1) +NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE = 32 +NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID = (0xB1) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS = (0x20800a6e) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE = (0x20800a6f) +NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID = (0x6f) +NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO = (0x20800ab2) +NV2080_CTRL_CMD_INTERNAL_CCU_MAP = (0x20800ab3) +NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX = 1 +NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID = (0xB3) +NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP = (0x20800ab4) +NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID = (0xB4) +NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS = (0x20800ab5) +NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB5) +NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS = (0x20800ab6) +NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB6) +NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS = (0x20800ab8) +NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB8) +NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO = (0x20800ab9) +NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID = (0xB9) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE = (0x20800a76) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x76) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE = (0x20800a77) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x77) +NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBB) +NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES = (0x20800aba) +NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBA) +NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE = (0x20800abd) +NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID = (0xBD) +NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT = (0x20800abe) +NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID = (0xBE) +NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS = (0x20800abf) +NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID = (0xBF) +NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS = (0x20800ac0) +NV2080_MAX_NUM_HEADS = 4 +NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID = (0xC0) +NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC = (0x20800ac1) +NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID = (0xC1) +NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES = (0x20800ac4) +NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID = (0xC4) +NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID = (0x20800ac9) +NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID = (0xC9) +NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC = (0x20800aca) +NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID = (0xCA) +NV2080_CTRL_CMD_INTERNAL_FBSR_INIT = (0x20800ac2) +NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID = (0xC2) +NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING = (0x20800ac3) +NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID = (0xC3) +NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB = (0x20800ac5) +NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID = (0xC5) +NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD = (0x20800ac6) +NV2080_CTRL_ACPI_DSM_READ_SIZE = (0x1000) +NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID = (0xC6) +NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC7) +NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL = (0x20800ac7) +NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC8) +NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL = (0x20800ac8) +NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE = (0x20800acb) +NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID = (0xCB) +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR = 0x00 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM = 0x01 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI = 0x02 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD = 0x00 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT = 0x01 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR = 0x02 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET = 0x03 +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC = (0x20800acc) +NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID = (0xCC) +NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC = (0x20800acd) +NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID = (0xCD) +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS = 0x00 +NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS = 0x01 +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE = (0x20800ace) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCE) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE = (0x20800acf) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCF) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT = (0x20800ad0) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID = (0xD0) +NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT = (0x20800ad1) +NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID = (0xD1) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE = (0x20800ad2) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID = (0xD2) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 = (0x20800ad3) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID = (0xD3) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO = (0x20800ad4) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID = (0xD4) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING = (0x20800ad5) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID = (0xD5) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE = (0x20800ad6) +NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID = (0xD6) +NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE = (0x2080a7d7) +NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID = (0xD7) +NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT = (0x20800a7b) +NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS = (0x20800ad8) +NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xD8) +NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS = (0x20800adb) +NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID = (0xDB) +NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS = (0x20800adc) +NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID = (0xDC) +NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE = (0x20800add) +NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL = (0x20800ade) +NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID = (0xDE) +NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA = (0x20800adf) +MAX_EDID_SIZE_FROM_SBIOS = 512 +NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID = (0xDF) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED = (0x20800af0) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET = (0x20800af1) +NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET = (0x20800af2) +NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF4) +NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO = (0x208001f4) +NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF5) +NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = (0x208001f5) +NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE = (0x208001f6) +NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE = (0x208001f7) +NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF8) +NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE = (0x208001f8) +NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE = (0x208001f9) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO = (0x20800af3) +NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xF3) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS = (0x20800ae1) +NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE = 3 +NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL = 0 +NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER = 1 +NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER = 2 +NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT = 3 +NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT = 6 +NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID = (0xE1) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS = (0x20800ae2) +NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID = (0xE2) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS = (0x20800ae5) +NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0xE5) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION = (0x20800ae6) +NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0xE6) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE = (0x20800ae7) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID = (0xE7) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY = (0x20800ae8) +NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID = (0xE8) +NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID = (0x20800aef) +NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID = (0xEF) +NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP = (0x20800afa) +CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES = (0x10) +NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID = (0xFA) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG = (0x20800afb) +NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFB) +NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG = (0x20800afc) +NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFC) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO = (0x20800afd) +NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID = (0xFD) +NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID = (0xFE) +NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA = (0x20800afe) +NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID = (0xFF) +NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL = (0x20800aff) +NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID = (0xE3) +NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST = 0x00 +NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST = 0x01 +NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP = 0x02 +NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = (0x208001e3) +NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID = (0xAF) +NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES = (0x20800aaf) +NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND = (0x20800ae4) +NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0xE4) +NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID = (0xE9) +NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER = (0x20800ae9) +NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY = (0x20800aea) +NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID = (0xEA) +NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID = (0xEB) +NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP = (0x20800aeb) +NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0xEC) +NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM = (0x20800aec) +NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID = (0xED) +NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR = (0x20800aed) +NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM = (0x20800a79) +NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID = (0x79) +NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID = (0x14) +NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE = (0x20800a14) +NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID = (0xEE) +NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA = (0x20800aee) +NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER = (0x20800a21) +NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x21) +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF = 0x00 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS = 0x01 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE = 0x02 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT = 0x03 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY = 0x04 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL = 0x05 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT = 0x06 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET = 0x07 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM = 0x08 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM = 0x09 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP = 0x0A +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE = 0x0B +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE = 0x0C +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS = 0x0E +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT = 0x0F +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE = 0x10 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN = 0x11 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP = 0x12 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 = 0x13 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE = 0x14 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE = 0x15 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE = 0x16 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE = 0x17 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT = 0x18 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN = 0x19 +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL = 0x1A +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 = 0x1B +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI = 0x1C +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING = 0x1D +NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID = 0xFF +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS = 0x00 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE = 0x04 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER = 0x04 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN = 0x05 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE = 0x06 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF = 0x07 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE = 0x08 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE = 0x09 +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY = 0x0A +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ = 0x0B +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN = 0x0C +NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS = 0x0D +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS = 0x00 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE = 0x04 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER = 0x04 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN = 0x05 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE = 0x06 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF = 0x07 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL = 0x08 +NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM = 0x09 +NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM = 6 +NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE = (0x7) +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE = 0x00 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE = 0x01 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE = 0x02 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE = 0x03 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE = 0x04 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE = 0x05 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE = 0x06 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE = 0x07 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT = 0x08 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT = 0x09 +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN = 0x0A +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN = 0x0B +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE = 0x0C +NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD = 0x0D +NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID = (0x24) +NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK = (0x20800a24) +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID = (0x25) +NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID = (0x20800a25) +NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID = (0x29) +NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED = (0x20800a29) +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM = 0x0 +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET = 0x1 +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID = (0x42) +NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX = (0x20800a42) +NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x4E) +NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER = (0x20800a4e) +NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x50) +NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER = (0x20800a50) +NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID = (0x20800a56) +NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE = (81) +NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID = (0x56) +NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM = 0x1 +NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER = 0x2 +NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID = (0x5F) +NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING = (0x20800a5f) +NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID = (0x62) +NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE = (0x20800a62) +NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET = (0x00000000) +NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE = (0x00000001) +NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE = (0x00000002) +NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID = (0x64) +NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY = (0x20800a64) +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID = (0x78) +NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG = (0x20800a78) +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID = (0x7D) +NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK = (0x20800a7d) +NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID = (0x82) +NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION = (0x20800a82) +NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID = (0x83) +NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY = (0x20800a83) +NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x84) +NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI = (0x20800a84) +NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE = 64 +NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID = (0x85) +NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET = (0x20800a85) +NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x86) +NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI = (0x20800a86) +NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x87) +NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO = (0x20800a87) +NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW = 6 +NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x8E) +NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO = (0x20800a8e) +NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID = (0x8F) +NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED = (0x20800a8f) +NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID = (0x90) +NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED = (0x20800a90) +NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT = (0x00000000) +NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT = (0x00000001) +NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE = (0x00000002) +NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID = (0x91) +NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS = (0x20800a91) +NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID = (0x92) +NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS = (0x20800a92) +NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID = (0x93) +NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO = (0x20800a93) +NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID = (0x94) +NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM = (0x20800a94) +NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID = (0x95) +NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS = (0x20800a95) +NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID = (0x96) +NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS = (0x20800a96) +NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97) +NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97) +NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB) +NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab) +NV2080_CTRL_CMD_LPWR_DIFR_CTRL = (0x20802801) +NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE = (0x00000001) +NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE = (0x00000002) +NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS = (0x00000003) +NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_LPWR_DIFR_SUPPORTED = (0x00000001) +NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED = (0x00000002) +NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE = (0x20802802) +NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS = (0x00000001) +NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED = (0x00000002) +NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE = (0x00000003) +NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR = (0x00000004) +NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_MC_GET_ARCH_INFO = (0x20801701) +NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X = (0xE0000023) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 = (0x00000160) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 = (0x00000170) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 = (0x00000180) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 = (0x00000190) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 = (0x000001A0) +NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 = (0x000001B0) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 = (0x00000004) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D = (0x00000005) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 = (0x00000002) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 = (0x00000004) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 = (0x00000006) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 = (0x00000008) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 = (0x00000007) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 = (0x00000002) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 = (0x00000003) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 = (0x00000004) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 = (0x00000006) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 = (0x00000007) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B = (0x0000000B) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC = (0x00000001) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 = (0x00000001) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 = (0x00000001) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 = (0x00000002) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 = (0x00000003) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 = (0x00000004) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 = (0x00000006) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 = (0x00000007) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B = (0x0000000B) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 = (0x00000002) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 = (0x00000002) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 = (0x00000003) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 = (0x00000004) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 = (0x00000005) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 = (0x00000006) +NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 = (0x00000007) +NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION = (0x00000000) +NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P = (0x00000001) +NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q = (0x00000002) +NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R = (0x00000003) +NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = (0x20801702) +NV2080_CTRL_MC_ENGINE_ID_GRAPHICS = 0x00000001 +NV2080_CTRL_MC_ENGINE_ID_ALL = 0xFFFFFFFF +NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_MC_GET_MANUFACTURER = (0x20801703) +NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP = (0x2080170c) +NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID = (0xC) +NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS = (0x2080170d) +NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES = 256 +NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE = (0x2080170e) +NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX = 32 +NV2080_INTR_TYPE_NULL = (0x00000000) +NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT = (0x00000001) +NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR = (0x00000002) +NV2080_INTR_TYPE_INFO_FAULT = (0x00000003) +NV2080_INTR_TYPE_REPLAYABLE_FAULT = (0x00000004) +NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR = (0x00000005) +NV2080_INTR_TYPE_ACCESS_CNTR = (0x00000006) +NV2080_INTR_TYPE_TMR = (0x00000007) +NV2080_INTR_TYPE_CPU_DOORBELL = (0x00000008) +NV2080_INTR_TYPE_GR0_FECS_LOG = (0x00000009) +NV2080_INTR_TYPE_GR1_FECS_LOG = (0x0000000A) +NV2080_INTR_TYPE_GR2_FECS_LOG = (0x0000000B) +NV2080_INTR_TYPE_GR3_FECS_LOG = (0x0000000C) +NV2080_INTR_TYPE_GR4_FECS_LOG = (0x0000000D) +NV2080_INTR_TYPE_GR5_FECS_LOG = (0x0000000E) +NV2080_INTR_TYPE_GR6_FECS_LOG = (0x0000000F) +NV2080_INTR_TYPE_GR7_FECS_LOG = (0x00000010) +NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x20802401) +NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_NVD_GET_DUMP = (0x20802402) +NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL = (0x20802409) +NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER = 1024 +NV2080_NOCAT_JOURNAL_MAX_STR_LEN = 65 +NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS = 10 +NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS = 32 +NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN = 0 +NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK = 1 +NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE = 2 +NV2080_NOCAT_JOURNAL_REC_TYPE_TDR = 3 +NV2080_NOCAT_JOURNAL_REC_TYPE_RC = 4 +NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT = 5 +NV2080_NOCAT_JOURNAL_REC_TYPE_ANY = 6 +NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT = (0x7) +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX = 0 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX = 1 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX = 2 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX = 3 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX = 4 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX = 5 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX = 6 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX = 7 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX = 8 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX = 9 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX = 10 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX = 11 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX = 12 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX = 13 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX = 14 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX = 15 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX = 16 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX = 17 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX = 18 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX = 19 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX = 20 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX = 21 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX = 22 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX = 23 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX = 24 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX = 25 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX = 26 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX = 27 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX = 28 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX = 29 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX = 30 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX = 31 +NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT = (0x20) +NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES = 1 +NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO = 0 +NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES = 1 +NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO = 0 +NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA = (0x2080240b) +NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY = 0 +NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON = 1 +NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG = 2 +NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG = 3 +NV2080_CTRL_NOCAT_TDR_TYPE_NONE = 0 +NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY = 1 +NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP = 2 +NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET = 3 +NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET = 4 +NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL = 5 +NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET = 6 +NV2080_CTRL_NOCAT_TDR_TYPE_TEST = 7 +NV2080_CTRL_NOCAT_TAG_CLEAR_YES = 1 +NV2080_CTRL_NOCAT_TAG_CLEAR_NO = 0 +NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD = (0x2080240c) +NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES = 1 +NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO = 0 +NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES = 1 +NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO = 0 +NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID = (0xC) +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_NVLINK_CAPS_TBL_SIZE = 2 +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID = (0x00000000) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 = (0x00000001) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 = (0x00000002) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 = (0x00000004) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 = (0x00000005) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 = (0x00000006) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 = (0x00000007) +NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 = (0x00000008) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID = (0x00000000) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 = (0x00000001) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 = (0x00000002) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 = (0x00000004) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 = (0x00000005) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 = (0x00000006) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 = (0x00000007) +NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 = (0x00000008) +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = (0x20803001) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE = (0x00000000) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI = (0x00000001) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID = (0x00000002) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE = (0x00000000) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU = (0x00000001) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU = (0x00000002) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH = (0x00000003) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA = (0x00000004) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE = (0x000000FF) +NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID = (0xFFFFFFFF) +NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE = (0x00000000) +NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE = (0x00000001) +NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE = (0x00000000) +NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT = (0x00000000) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG = (0x00000002) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE = (0x00000003) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP = (0x00000005) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY = (0x00000006) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC = (0x00000008) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX = (0x0000000a) +NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID = (0xFFFFFFFF) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 = (0x00000000) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING = (0x00000005) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE = (0x00000006) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF = (0x00000007) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST = (0x00000008) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT = (0x0000000e) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 = (0x00000000) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING = (0x00000005) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE = (0x00000006) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF = (0x00000007) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST = (0x00000008) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT = (0x0000000e) +NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_PHY_NVHS = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_PHY_GRS = (0x00000002) +NV2080_CTRL_NVLINK_STATUS_PHY_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 = (0x00000002) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 = (0x00000005) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 = (0x00000006) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 = (0x00000007) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 = (0x00000008) +NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 = (0x00000002) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 = (0x00000004) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 = (0x00000005) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 = (0x00000006) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 = (0x00000007) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 = (0x00000008) +NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE = (0x00000000) +NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK = (0x00000001) +NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT = (0x00000002) +NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE = (0x00000000) +NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID = (0x000000FF) +NV2080_CTRL_NVLINK_MAX_LINKS = 32 +NV2080_CTRL_NVLINK_MAX_ARR_SIZE = 64 +NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID = (0x00) +NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS = (0x01) +NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX = (0x02) +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = (0x20803002) +NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT = lambda intr,i: (((1 << i) & (intr)) >> i) +NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT = lambda intr,i: NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i) +NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE = (0x00000001) +NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE = (0x00000000) +NV2080_CTRL_NVLINK_TL_INTEN_TRUE = (0x00000001) +NV2080_CTRL_NVLINK_TL_INTEN_FALSE = (0x00000000) +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN = 0 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN = 1 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN = 2 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN = 3 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN = 4 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN = 5 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN = 6 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN = 7 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN = 8 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN = 9 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN = 10 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN = 12 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN = 13 +NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX = 14 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR = 0 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR = 1 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR = 2 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR = 3 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR = 4 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR = 5 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR = 6 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR = 7 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR = 8 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR = 9 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR = 10 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR = 12 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR = 13 +NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX = 14 +NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS = (0x00000000) +NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) +NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN = (0x00000005) +NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE = (0x00000006) +NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF = (0x00000007) +NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS = (0x00000000) +NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE = (0x00000004) +NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN = (0x00000005) +NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE = (0x00000006) +NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF = (0x00000007) +NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT = (0x0) +NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS = (0x1) +NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS = (0x2) +NV2080_CTRL_NVLINK_MAX_IOCTRLS = 3 +NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO = (0x20803003) +NV2080_CTRL_NVLINK_COUNTER_INVALID = 0x00000000 +NV2080_CTRL_NVLINK_COUNTER_TL_TX0 = 0x00000001 +NV2080_CTRL_NVLINK_COUNTER_TL_TX1 = 0x00000002 +NV2080_CTRL_NVLINK_COUNTER_TL_RX0 = 0x00000004 +NV2080_CTRL_NVLINK_COUNTER_TL_RX1 = 0x00000008 +NV2080_CTRL_NVLINK_LP_COUNTERS_DL = 0x00000010 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L = lambda i: (1 << (i + 8)) +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE = 4 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 = 0x00000100 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 = 0x00000200 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 = 0x00000400 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 = 0x00000800 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT = 0x00010000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L = lambda i: (1 << (i + 17)) +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE = 8 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 = 0x00020000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 = 0x00040000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 = 0x00080000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 = 0x00100000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 = 0x00200000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 = 0x00400000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 = 0x00800000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 = 0x01000000 +NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY = 0x02000000 +NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY = 0x04000000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY = 0x08000000 +NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED = 0x10000000 +NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES = 32 +NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_NVLINK_GET_COUNTERS = (0x20803004) +NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS = (0x20803005) +NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 = 0 +NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 = 1 +NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 = 2 +NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 = 3 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE = 4 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 = 4 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 = 5 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 = 6 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 = 7 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE = 8 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 = 8 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 = 9 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 = 10 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 = 11 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 = 12 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 = 13 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 = 14 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 = 15 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY = 16 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY = 17 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY = 18 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED = 19 +NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT = 20 +NV2080_CTRL_NVLINK_COUNTER_LP_DL = 21 +NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER = NV2080_CTRL_NVLINK_COUNTER_LP_DL +NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS = 22 +NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES = 23 +NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS = 24 +NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES = 25 +NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER = 26 +NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER = 27 +NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER = 28 +NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS = 29 +NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS = 30 +NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS = 31 +NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR = 32 +NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR = 33 +NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR = 34 +NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS = 35 +NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS = 36 +NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME = 37 +NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS = 38 +NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS = 39 +NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS = 40 +NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS = 41 +NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 = 42 +NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 = 43 +NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL = 44 +NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 = 45 +NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 = 46 +NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS = 47 +NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 = 48 +NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 = 49 +NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL = 50 +NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS = 51 +NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS = 52 +NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER = 53 +NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS = 54 +NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER = 55 +NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS = 56 +NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS = 57 +NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR = 58 +NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS = 59 +NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS = 60 +NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS = 61 +NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS = 62 +NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS = 63 +NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS = 64 +NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS = 65 +NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD = 66 +NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR = 67 +NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH = 68 +NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD = 69 +NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR = 70 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 = 71 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 = 72 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 = 73 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 = 74 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 = 75 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 = 76 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 = 77 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 = 78 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 = 79 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 = 80 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 = 81 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 = 82 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 = 83 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 = 84 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 = 85 +NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 = 86 +NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA = 87 +NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA = 88 +NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW = 89 +NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW = 90 +NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY = 91 +NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE = 92 +NV2080_CTRL_NVLINK_COUNTER_L1_EXIT = 93 +NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL = 94 +NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE = 95 +NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME = 96 +NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME = 97 +NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME = 98 +NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME = 99 +NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME = 100 +NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME = 101 +NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME = 102 +NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME = 103 +NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME = 104 +NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME = 105 +NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME = 106 +NV2080_CTRL_NVLINK_COUNTERS_MAX = 107 +NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS = 2 +NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ = 28 +NV2080_CTRL_NVLINK_COUNTER_V2_GROUP = lambda i: ((i) / 64) +NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x50) +NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 = (0x20803050) +NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x51) +NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 = (0x20803051) +NV2080_CTRL_CMD_NVLINK_INJECT_ERROR = (0x20803006) +NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x6) +NV2080_CTRL_NVLINK_UNIT_DL = 0x01 +NV2080_CTRL_NVLINK_UNIT_TL = 0x02 +NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 = 0x03 +NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 = 0x04 +NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 = 0x05 +NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 = 0x06 +NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 = 0x07 +NV2080_CTRL_NVLINK_UNIT_MINION = 0x08 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER = 0x00000001 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER = 0x00000002 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN = 0x00000001 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN = 0x00000001 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN = 0x00000001 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN = 0x00000001 +NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x81) +NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT = (0x20803081) +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST = 0x00000001 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR = 0x00000002 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT = 0x00000000 +NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT = 0x00000001 +NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x82) +NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT = (0x20803082) +NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES = (0x20803007) +NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID = (0x7) +NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE = (0x20803008) +NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS = (0x20803009) +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY = 0 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY = 1 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL = 2 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW = 3 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY = 4 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY = 5 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP = 6 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON = 7 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY = 8 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY = 9 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT = 10 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY = 12 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG = 13 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM = 14 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE = 15 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT = 19 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY = 0 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY = 1 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY = 4 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY = 5 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY = 8 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY = 9 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY = 20 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN = 24 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC = 25 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW = 39 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW = 40 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY = 54 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY = 55 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY = 56 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY = 57 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY = 60 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP = 61 +NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN = 62 +NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES = 63 +NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID = lambda count,supportedCounts: ( not not ((supportedCounts) & NVBIT64(count))) +NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES = (0x2080300a) +NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES = 5 +NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE = (0x2080300b) +NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_CMD_NVLINK_SETUP_EOM = (0x2080300c) +NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID = (0xC) +NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE = (0x2080300d) +NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_NVLINK_POWER_STATE_L0 = (0x00) +NV2080_CTRL_NVLINK_POWER_STATE_L1 = (0x01) +NV2080_CTRL_NVLINK_POWER_STATE_L2 = (0x02) +NV2080_CTRL_NVLINK_POWER_STATE_L3 = (0x03) +NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE = (0x2080300e) +NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR = (0x2080300f) +NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID = (0xF) +NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES = (0x20803011) +NV2080_CTRL_NVLINK_MAX_LANES = 4 +NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID = (0x11) +NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER = (0x20803012) +NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG = (0x20803013) +NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID = (0x13) +NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID = (0x14) +NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS = (0x20803014) +NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX = 0 +NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX = 1 +NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX = 2 +NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX = 3 +NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX = 4 +NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID = (0x15) +NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS = (0x20803015) +NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE = (0x20803016) +NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID = (0x16) +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS = 0 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH = 1 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER = 2 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER = 3 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT = 4 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP = 5 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME = 6 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME = 7 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME = 8 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME = 9 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME = 10 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME = 11 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME = 12 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME = 13 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME = 14 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME = 15 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS = 16 +NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID = (0x18) +NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS = (0x20803018) +NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS = (0x20803052) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT = (0x00000000) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA = (0x00000001) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR = (0x00000002) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW = (0x00000003) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE = (0x00000004) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL = (0x00000005) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL = (0x00000006) +NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID = (0x23) +NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE = (0x20803023) +NV2080_CTRL_NVLINK_MAX_LINK_COUNT = 32 +NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x28) +NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS = (0x20803028) +NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x29) +NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS = (0x20803029) +NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID = (0x38) +NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR = (0x20803038) +NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID = (0x39) +NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO = (0x20803039) +NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS = (0x2080303a) +NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID = (0x3b) +NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS = (0x2080303b) +NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID = (0x3c) +NV2080_CTRL_CMD_NVLINK_EOM_CONTROL = (0x2080303c) +NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE = 5120 +NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID = (0x3d) +NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE = (0x2080303d) +NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT = (0xFFFFFFFF) +NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3e) +NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD = (0x2080303e) +NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3f) +NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD = (0x2080303f) +NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID = (0x40) +NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA = (0x20803040) +NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID = (0x41) +NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED = (0x20803041) +NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID = (0x42) +NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK = (0x20803042) +NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID = (0x43) +NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP = (0x20803043) +NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE = 64 +NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID = (0x44) +NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS = (0x20803044) +NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID = (0x45) +NV2080_CTRL_CMD_NVLINK_CYCLE_LINK = (0x20803045) +NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID = (0x46) +NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG = (0x20803046) +NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH = 496 +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS = (0x20803047) +NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID = (0x47) +NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY = (0x20803048) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC = (0x20803053) +NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID = (0x53) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM = (0x20803054) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID = (0x54) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC = (0x20803055) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID = (0x55) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM = (0x20803056) +NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID = (0x56) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR = (0x2080305c) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID = (0x5c) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE = (0x2080305e) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID = (0x5e) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE = (0x2080305f) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID = (0x5f) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP = (0x20803061) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID = (0x61) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU = (0x20803062) +NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID = (0x62) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP = (0x20803064) +NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID = (0x64) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT = (0x20803065) +NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID = (0x65) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR = (0x20803066) +NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID = (0x66) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT = (0x20803068) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID = (0x68) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT = (0x20803069) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID = (0x69) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR = (0x2080306a) +NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID = (0x6a) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS = (0x2080306b) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID = (0x6b) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR = (0x2080306c) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID = (0x6c) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP = (0x2080306d) +NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID = (0x6d) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID = (0x2080306e) +NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID = (0x6e) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT = (0x2080306f) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID = (0x6f) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS = (0x20803070) +NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID = (0x70) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG = (0x20803071) +NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID = (0x71) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS = (0x20803072) +NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID = (0x72) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR = (0x20803073) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID = (0x73) +NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS = (0x20803074) +NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID = (0x74) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD = (0x20803075) +NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID = (0x75) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP = (0x20803076) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID = (0x76) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF = (0x20803077) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID = (0x77) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL = (0x20803078) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID = (0x78) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM = (0x20803079) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID = (0x79) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE = (0x2080307a) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID = (0x7a) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM = (0x2080307b) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID = (0x7b) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR = (0x2080307c) +NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID = (0x7c) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR = (0x2080307d) +NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID = (0x7d) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS = (0x2080307e) +NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID = (0x7e) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC = (0x2080307f) +NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID = (0x7f) +NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB = (0x20803080) +NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID = (0x80) +NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = (0x20803083) +NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID = (0x83) +NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS = 18 +NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN = (0x20803084) +NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID = (0x84) +NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT = 23 +NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE = (0x20803085) +NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID = (0x85) +NV2080_CTRL_CMD_NVLINK_SET_BW_MODE = (0x20803086) +NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID = (0x86) +NV2080_CTRL_CMD_NVLINK_GET_BW_MODE = (0x20803087) +NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID = (0x87) +NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO = (0x20803088) +NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x88) +NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR = (0x20803089) +NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID = (0x89) +NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY = (0x2080308a) +NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE = (0x2080308e) +NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8E) +NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE = (0x2080308f) +NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8F) +NV_SUBPROC_NAME_MAX_LENGTH = 100 +NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR = (0x00000000) +NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL = (0x00000001) +NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX = (0x00000002) +NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO = (0x00000000) +NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES = (0x00000001) +NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO = (0x00000000) +NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES = (0x00000001) +NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT = (0x00000000) +NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH = (0x00000001) +NV2080_CTRL_PERF_BOOST_DURATION_MAX = 3600 +NV2080_CTRL_PERF_BOOST_DURATION_INFINITE = 0xffffffff +NV2080_CTRL_CMD_PERF_BOOST = (0x2080200a) +NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW = (0x20802093) +NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID = (0x93) +NV2080_CTRL_PERF_POWER_SOURCE_AC = (0x00000000) +NV2080_CTRL_PERF_POWER_SOURCE_BATTERY = (0x00000001) +NV2080_CTRL_CMD_PERF_SET_POWERSTATE = (0x2080205b) +NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5B) +NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE = (0x20802092) +NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x92) +NV2080_CTRL_PERF_AUX_POWER_STATE_P0 = (0x00000000) +NV2080_CTRL_PERF_AUX_POWER_STATE_P1 = (0x00000001) +NV2080_CTRL_PERF_AUX_POWER_STATE_P2 = (0x00000002) +NV2080_CTRL_PERF_AUX_POWER_STATE_P3 = (0x00000003) +NV2080_CTRL_PERF_AUX_POWER_STATE_P4 = (0x00000004) +NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT = (0x00000005) +NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID = (0x6D) +NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL = (0x2080206e) +NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID = (0x6E) +NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL = (0x2080206f) +NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID = (0x6F) +NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID = (0x83) +NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL = 72 +NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 = (0x20802096) +NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID = (0x96) +NV2080_CTRL_CMD_PERF_GPU_IS_IDLE = (0x20802089) +NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID = (0x89) +NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE = (0x00000001) +NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE = (0x00000002) +NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY = (0x2080208f) +NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID = (0x8F) +NV2080_CTRL_PERF_CLK_MAX_DOMAINS = 32 +NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO = (0x20802002) +NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 = (0x2080200b) +NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT = (0x00000000) +NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK = (0x00000001) +NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE = (0x00000000) +NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP = (0x00000001) +NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF = (0x00000002) +NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE = (0x20802087) +NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x87) +NV2080_CTRL_CMD_PERF_GET_POWERSTATE = (0x2080205a) +NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5A) +NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT = (0x2080205d) +NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID = (0x5D) +NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK = (0x0000ffff) +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START = (0x00000001) +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP = (0x00000002) +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START = (0x00000003) +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP = (0x00000004) +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START = (0x00000005) +NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP = (0x00000006) +NV2080_CTRL_PERF_VIDEOEVENT_OFA_START = (0x00000007) +NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP = (0x00000008) +NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE = (0x00010000) +NV2080_CTRL_PERF_PSTATES_UNDEFINED = (0x00000000) +NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED = (0x00000000) +NV2080_CTRL_PERF_PSTATES_MIN = (0x00000001) +NV2080_CTRL_PERF_PSTATES_P0 = (0x00000001) +NV2080_CTRL_PERF_PSTATES_P1 = (0x00000002) +NV2080_CTRL_PERF_PSTATES_P2 = (0x00000004) +NV2080_CTRL_PERF_PSTATES_P3 = (0x00000008) +NV2080_CTRL_PERF_PSTATES_P4 = (0x00000010) +NV2080_CTRL_PERF_PSTATES_P5 = (0x00000020) +NV2080_CTRL_PERF_PSTATES_P6 = (0x00000040) +NV2080_CTRL_PERF_PSTATES_P7 = (0x00000080) +NV2080_CTRL_PERF_PSTATES_P8 = (0x00000100) +NV2080_CTRL_PERF_PSTATES_P9 = (0x00000200) +NV2080_CTRL_PERF_PSTATES_P10 = (0x00000400) +NV2080_CTRL_PERF_PSTATES_P11 = (0x00000800) +NV2080_CTRL_PERF_PSTATES_P12 = (0x00001000) +NV2080_CTRL_PERF_PSTATES_P13 = (0x00002000) +NV2080_CTRL_PERF_PSTATES_P14 = (0x00004000) +NV2080_CTRL_PERF_PSTATES_P15 = (0x00008000) +NV2080_CTRL_PERF_PSTATES_MAX = NV2080_CTRL_PERF_PSTATES_P15 +NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY = (0x10000) +NV2080_CTRL_PERF_PSTATES_ALL = (0xffff) +NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE = (0x20802068) +NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID = (0x68) +NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED = 0 +NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED = 1 +NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE = 2 +NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO = (0x20802609) +NV2080_CTRL_CMD_GC6_ENTRY = (0x2080270d) +NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_CMD_GC6_EXIT = (0x2080270e) +NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM = (0x20802204) +NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_CMD_RC_GET_ERROR_COUNT = (0x20802205) +NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE = (0x2000) +NV2080_CTRL_CMD_RC_GET_ERROR = (0x20802206) +NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID = (0x13) +NV2080_CTRL_CMD_RC_GET_ERROR_V2 = (0x20802213) +NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY = (0x20802207) +NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = (0x20802209) +NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE = (0x00000000) +NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED = (0x00000001) +NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING = (0x00000002) +NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED = (0x00000004) +NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG = (0x2080220a) +NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG = (0x2080220b) +NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = (0x2080220c) +NV2080_CTRL_CMD_SET_RC_RECOVERY = (0x2080220d) +NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_CMD_GET_RC_RECOVERY = (0x2080220e) +NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xE) +NV2080_CTRL_CMD_RC_RECOVERY_DISABLED = (0x00000000) +NV2080_CTRL_CMD_RC_RECOVERY_ENABLED = (0x00000001) +NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE = (0x2080220f) +NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID = (0xF) +NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN = (0x00000000) +NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END = (0x00000001) +NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS = (0x00000000) +NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL = (0x00000001) +NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = (0x20802210) +NV2080_CTRL_CMD_SET_RC_INFO = (0x20802211) +NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID = (0x11) +NV2080_CTRL_CMD_GET_RC_INFO = (0x20802212) +NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID = (0x12) +NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE = (0x00000000) +NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE = (0x00000001) +NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE = (0x00000000) +NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE = (0x00000001) +RM_GSP_SPDM_CMD_ID_CC_INIT = (0x1) +RM_GSP_SPDM_CMD_ID_CC_DEINIT = (0x2) +RM_GSP_SPDM_CMD_ID_CC_CTRL = (0x3) +RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA = (0x4) +RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL = (0x5) +RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST = (0x6) +RM_GSP_SPDM_CMD_ID_INVALID_COMMAND = (0xFF) +SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE = 0x2400 +RSVD7_SIZE = 16 +RSVD8_SIZE = 2 +CE_FIPS_SELF_TEST_DATA_SIZE = 16 +CE_FIPS_SELF_TEST_AUTH_TAG_SIZE = 16 +CE_FIPS_SELF_TEST_IV_SIZE = 12 +RM_GSP_SPDM_MSG_ID_CC_INIT = (0x1) +RM_GSP_SPDM_MSG_ID_CC_DEINIT = (0x2) +RM_GSP_SPDM_MSG_ID_CC_CTRL = (0x3) +RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA = (0x4) +RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL = (0x5) +RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST = (0x6) +RM_GSP_SPDM_MSG_ID_INVALID_COMMAND = (0xFF) +NV2080_CTRL_INTERNAL_SPDM_PARTITION = (0x20800ad9) +NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID = (0xD9) +NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT = (0x20800ada) +NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID = (0xDA) +NV2080_CTRL_CMD_TIMER_SCHEDULE = (0x20800401) +NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS = (0x00000000) +NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL = (0x00000001) +NV2080_CTRL_CMD_TIMER_CANCEL = (0x20800402) +NV2080_CTRL_CMD_TIMER_GET_TIME = (0x20800403) +NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET = (0x20800404) +NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = (0x20800406) +NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES = 16 +NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID = (0x6) +NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME = (0x00000001) +NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC = (0x00000002) +NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API = (0x00000003) +NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS = (0x00000004) +NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU = (0x00000000) +NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP = (0x00000001) +NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = (0x20800407) +NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID = (0x7) +NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT = (0x20803d01) +NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC = (0x00000001) +NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC = (0x00000002) +NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF = (0x20803d02) +NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW = (0x00000001) +NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW = (0x00000002) +NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER = (0x20803d03) +NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS = (0x20803d04) +NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER = (0x20803d05) +NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER = (0x20803d06) +NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS = (0x20803d07) +NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID = (0x7) +NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS = (0x20803d08) +NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK = (0x20804001) +NV2080_CTRL_MAX_VMMU_SEGMENTS = 384 +NV2080_GPU_MAX_ENGINES = 0x54 +NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x1) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK = (0x20804002) +NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x2) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE = (0x20804003) +NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID = (0x3) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU = (0x20804004) +NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID = (0x4) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO = (0x20804005) +NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID = (0x5) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE = (0x20804006) +NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID = (0x6) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY = (0x20804007) +NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x7) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP = (0x20804008) +NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID = (0x8) +NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN = 8 +NV2080_CTRL_MAX_GPC_COUNT = 32 +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING = (0x20804009) +NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID = (0x9) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT = (0x2080400a) +NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID = (0xA) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG = (0x2080400b) +NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID = (0xB) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES = (0x2080400c) +NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID = (0xC) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS = (0x2080400d) +NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID = (0xD) +NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE = (0x2080400e) +NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0xE) +NV83DE_CTRL_RESERVED = (0x00) +NV83DE_CTRL_GR = (0x01) +NV83DE_CTRL_FIFO = (0x02) +NV83DE_CTRL_DEBUG = (0x03) +NV83DE_CTRL_INTERNAL = (0x04) +NV83DE_CTRL_CMD_NULL = (0x83de0000) +NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE = (0x83de0301) +NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE = (0x83de0302) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG = (0x83de0307) +NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x7) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE = (0x00000001) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE = (0x00000002) +NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS = (0x00000003) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG = (0x83de0308) +NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x8) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED = (0x00000001) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED = (0x00000002) +NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = (0x83de0309) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID = (0x9) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL = (0x00000001) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP = (0x00000002) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP = (0x00000004) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT = (0x00000008) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP = (0x00000010) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED = (0x00000020) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE = (0x00000000) +NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL = (0x0000FFFF) +NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE = (0x83de030b) +NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xB) +NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = (0x83de030c) +NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL = 100 +NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0xC) +NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE = (0x83de030f) +NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xF) +NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = (0x83de0310) +NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0x10) +NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED = 1 +NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL = 1 +NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE = (0x83de0313) +NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID = (0x13) +NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM = (0x00000001) +NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT = (0x00000002) +NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING = (0x83de0314) +NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID = (0x14) +NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING = (0x00000001) +NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING = (0x00000002) +NV83DE_CTRL_CMD_DEBUG_READ_MEMORY = (0x83de0315) +NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID = (0x15) +NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY = (0x83de0316) +NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID = (0x16) +NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT = (0x83de0317) +NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID = (0x17) +NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT = (0x83de0318) +NV83DE_CTRL_CMD_DEBUG_GET_HANDLES = (0x83de0319) +NV83DE_CTRL_CMD_READ_SURFACE = (0x83de031a) +NV83DE_CTRL_CMD_WRITE_SURFACE = (0x83de031b) +MAX_ACCESS_OPS = 64 +NV83DE_CTRL_CMD_GET_MAPPINGS = (0x83de031c) +MAX_GET_MAPPINGS_OPS = 64 +NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS = (0x83de031d) +NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS = 100 +NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x1D) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG = (0x83de031f) +NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x1F) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE = (0x00000000) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE = (0x00000001) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG = (0x83de0320) +NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x20) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED = (0x00000000) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED = (0x00000001) +NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP = (0x83de0321) +NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID = (0x21) +NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER = (0x83de0322) +NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID = (0x22) +NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER = (0x83de0323) +NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID = (0x23) +NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT = (0x83de0324) +NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID = (0x24) +NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS = (0x83de0325) +NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID = (0x25) +NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY = (0x83de0326) +NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY = (0x83de0327) +MAX_ACCESS_MEMORY_OPS = 150 +NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES = 4 +NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO = (0x83de0328) +NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID = (0x28) +NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC = (0x83de0329) +NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID = (0x29) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG = (0x83de032a) +NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2A) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE = (0x00000001) +NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE = (0x00000002) +NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS = (0x00000003) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG = (0x83de032b) +NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2B) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED = (0x00000001) +NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED = (0x00000002) +NV_STATUS_LEVEL_OK = 0 +NV_STATUS_LEVEL_WARN = 1 +NV_STATUS_LEVEL_ERR = 3 +NV01_ROOT = (0x00000000) +NV1_ROOT = (0x00000000) +NV01_NULL_OBJECT = (0x00000000) +NV1_NULL_OBJECT = (0x00000000) +NV01_ROOT_NON_PRIV = (0x00000001) +NV1_ROOT_NON_PRIV = (0x00000001) +NV01_ROOT_CLIENT = (0x00000041) +FABRIC_MANAGER_SESSION = (0x0000000f) +NV0020_GPU_MANAGEMENT = (0x00000020) +NV01_DEVICE_0 = (0x00000080) +NV20_SUBDEVICE_0 = (0x00002080) +NV2081_BINAPI = (0x00002081) +NV2082_BINAPI_PRIVILEGED = (0x00002082) +NV20_SUBDEVICE_DIAG = (0x0000208f) +NV01_CONTEXT_DMA = (0x00000002) +NV01_MEMORY_SYSTEM = (0x0000003e) +NV1_MEMORY_SYSTEM = (0x0000003e) +NV01_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) +NV1_MEMORY_LOCAL_PRIVILEGED = (0x0000003f) +NV01_MEMORY_PRIVILEGED = (0x0000003f) +NV1_MEMORY_PRIVILEGED = (0x0000003f) +NV01_MEMORY_LOCAL_USER = (0x00000040) +NV1_MEMORY_LOCAL_USER = (0x00000040) +NV01_MEMORY_USER = (0x00000040) +NV1_MEMORY_USER = (0x00000040) +NV_MEMORY_EXTENDED_USER = (0x00000042) +NV01_MEMORY_VIRTUAL = (0x00000070) +NV01_MEMORY_SYSTEM_DYNAMIC = (0x00000070) +NV1_MEMORY_SYSTEM_DYNAMIC = (0x00000070) +NV_MEMORY_MAPPER = (0x000000fe) +NV01_MEMORY_LOCAL_PHYSICAL = (0x000000c2) +NV01_MEMORY_SYNCPOINT = (0x000000c3) +NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = (0x00000071) +NV01_MEMORY_DEVICELESS = (0x000090ce) +NV01_MEMORY_FRAMEBUFFER_CONSOLE = (0x00000076) +NV01_MEMORY_HW_RESOURCES = (0x000000b1) +NV01_MEMORY_LIST_SYSTEM = (0x00000081) +NV01_MEMORY_LIST_FBMEM = (0x00000082) +NV01_MEMORY_LIST_OBJECT = (0x00000083) +NV_IMEX_SESSION = (0x000000f1) +NV01_MEMORY_FLA = (0x000000f3) +NV_MEMORY_EXPORT = (0x000000e0) +NV_CE_UTILS = (0x00000050) +NV_MEMORY_FABRIC = (0x000000f8) +NV_MEMORY_FABRIC_IMPORT_V2 = (0x000000f9) +NV_MEMORY_FABRIC_IMPORTED_REF = (0x000000fb) +FABRIC_VASPACE_A = (0x000000fc) +NV_MEMORY_MULTICAST_FABRIC = (0x000000fd) +IO_VASPACE_A = (0x000000f2) +NV01_NULL = (0x00000030) +NV1_NULL = (0x00000030) +NV01_EVENT = (0x00000005) +NV1_EVENT = (0x00000005) +NV01_EVENT_KERNEL_CALLBACK = (0x00000078) +NV1_EVENT_KERNEL_CALLBACK = (0x00000078) +NV01_EVENT_OS_EVENT = (0x00000079) +NV1_EVENT_OS_EVENT = (0x00000079) +NV01_EVENT_WIN32_EVENT = (0x00000079) +NV1_EVENT_WIN32_EVENT = (0x00000079) +NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007e) +NV1_EVENT_KERNEL_CALLBACK_EX = (0x0000007e) +NV01_TIMER = (0x00000004) +NV1_TIMER = (0x00000004) +KERNEL_GRAPHICS_CONTEXT = (0x00000090) +LOCK_STRESS_OBJECT = (0x00000100) +NV50_CHANNEL_GPFIFO = (0x0000506f) +GF100_CHANNEL_GPFIFO = (0x0000906f) +KEPLER_CHANNEL_GPFIFO_A = (0x0000a06f) +UVM_CHANNEL_RETAINER = (0x0000c574) +KEPLER_CHANNEL_GPFIFO_B = (0x0000a16f) +MAXWELL_CHANNEL_GPFIFO_A = (0x0000b06f) +PASCAL_CHANNEL_GPFIFO_A = (0x0000c06f) +VOLTA_CHANNEL_GPFIFO_A = (0x0000c36f) +TURING_CHANNEL_GPFIFO_A = (0x0000c46f) +AMPERE_CHANNEL_GPFIFO_A = (0x0000c56f) +HOPPER_CHANNEL_GPFIFO_A = (0x0000c86f) +BLACKWELL_CHANNEL_GPFIFO_A = (0x0000c96f) +BLACKWELL_CHANNEL_GPFIFO_B = (0x0000ca6f) +NV04_SOFTWARE_TEST = (0x0000007d) +NV4_SOFTWARE_TEST = (0x0000007d) +NV30_GSYNC = (0x000030f1) +VOLTA_USERMODE_A = (0x0000c361) +TURING_USERMODE_A = (0x0000c461) +AMPERE_USERMODE_A = (0x0000c561) +HOPPER_USERMODE_A = (0x0000c661) +BLACKWELL_USERMODE_A = (0x0000c761) +NVC371_DISP_SF_USER = (0x0000c371) +NVC372_DISPLAY_SW = (0x0000c372) +NVC573_DISP_CAPABILITIES = (0x0000c573) +NVC673_DISP_CAPABILITIES = (0x0000c673) +NVC773_DISP_CAPABILITIES = (0x0000c773) +NVC973_DISP_CAPABILITIES = (0x0000c973) +NVCA73_DISP_CAPABILITIES = (0x0000ca73) +NV04_DISPLAY_COMMON = (0x00000073) +NV50_DEFERRED_API_CLASS = (0x00005080) +MPS_COMPUTE = (0x0000900e) +NVC570_DISPLAY = (0x0000c570) +NVC57A_CURSOR_IMM_CHANNEL_PIO = (0x0000c57a) +NVC57B_WINDOW_IMM_CHANNEL_DMA = (0x0000c57b) +NVC57D_CORE_CHANNEL_DMA = (0x0000c57d) +NVC57E_WINDOW_CHANNEL_DMA = (0x0000c57e) +NVC670_DISPLAY = (0x0000c670) +NVC671_DISP_SF_USER = (0x0000c671) +NVC67A_CURSOR_IMM_CHANNEL_PIO = (0x0000c67a) +NVC67B_WINDOW_IMM_CHANNEL_DMA = (0x0000c67b) +NVC67D_CORE_CHANNEL_DMA = (0x0000c67d) +NVC67E_WINDOW_CHANNEL_DMA = (0x0000c67e) +NVC77F_ANY_CHANNEL_DMA = (0x0000c77f) +NVC770_DISPLAY = (0x0000c770) +NVC771_DISP_SF_USER = (0x0000c771) +NVC77D_CORE_CHANNEL_DMA = (0x0000c77d) +NVC970_DISPLAY = (0x0000c970) +NVC971_DISP_SF_USER = (0x0000c971) +NVC97A_CURSOR_IMM_CHANNEL_PIO = (0x0000c97a) +NVC97B_WINDOW_IMM_CHANNEL_DMA = (0x0000c97b) +NVC97D_CORE_CHANNEL_DMA = (0x0000c97d) +NVC97E_WINDOW_CHANNEL_DMA = (0x0000c97e) +NVCA70_DISPLAY = (0x0000ca70) +NVCA71_DISP_SF_USER = (0x0000ca71) +NVCA7A_CURSOR_IMM_CHANNEL_PIO = (0x0000ca7a) +NVCA7B_WINDOW_IMM_CHANNEL_DMA = (0x0000ca7b) +NVCA7D_CORE_CHANNEL_DMA = (0x0000ca7d) +NVCA7E_WINDOW_CHANNEL_DMA = (0x0000ca7e) +NV9010_VBLANK_CALLBACK = (0x00009010) +GF100_PROFILER = (0x000090cc) +MAXWELL_PROFILER = (0x0000b0cc) +MAXWELL_PROFILER_CONTEXT = (0x0000b1cc) +MAXWELL_PROFILER_DEVICE = (0x0000b2cc) +GF100_SUBDEVICE_MASTER = (0x000090e6) +GF100_SUBDEVICE_INFOROM = (0x000090e7) +GF100_ZBC_CLEAR = (0x00009096) +GF100_DISP_SW = (0x00009072) +GF100_TIMED_SEMAPHORE_SW = (0x00009074) +G84_PERFBUFFER = (0x0000844c) +NV50_MEMORY_VIRTUAL = (0x000050a0) +NV50_P2P = (0x0000503b) +NV50_THIRD_PARTY_P2P = (0x0000503c) +FERMI_TWOD_A = (0x0000902d) +FERMI_VASPACE_A = (0x000090f1) +HOPPER_SEC2_WORK_LAUNCH_A = (0x0000cba2) +GF100_HDACODEC = (0x000090ec) +NVB8B0_VIDEO_DECODER = (0x0000b8b0) +NVC4B0_VIDEO_DECODER = (0x0000c4b0) +NVC6B0_VIDEO_DECODER = (0x0000c6b0) +NVC7B0_VIDEO_DECODER = (0x0000c7b0) +NVC9B0_VIDEO_DECODER = (0x0000c9b0) +NVCDB0_VIDEO_DECODER = (0x0000cdb0) +NVCFB0_VIDEO_DECODER = (0x0000cfb0) +NVC4B7_VIDEO_ENCODER = (0x0000c4b7) +NVB4B7_VIDEO_ENCODER = (0x0000b4b7) +NVC7B7_VIDEO_ENCODER = (0x0000c7b7) +NVC9B7_VIDEO_ENCODER = (0x0000c9b7) +NVCFB7_VIDEO_ENCODER = (0x0000cfb7) +NVB8D1_VIDEO_NVJPG = (0x0000b8d1) +NVC4D1_VIDEO_NVJPG = (0x0000c4d1) +NVC9D1_VIDEO_NVJPG = (0x0000c9d1) +NVCDD1_VIDEO_NVJPG = (0x0000cdd1) +NVCFD1_VIDEO_NVJPG = (0x0000cfd1) +NVB8FA_VIDEO_OFA = (0x0000b8fa) +NVC6FA_VIDEO_OFA = (0x0000c6fa) +NVC7FA_VIDEO_OFA = (0x0000c7fa) +NVC9FA_VIDEO_OFA = (0x0000c9fa) +NVCDFA_VIDEO_OFA = (0x0000cdfa) +NVCFFA_VIDEO_OFA = (0x0000cffa) +KEPLER_INLINE_TO_MEMORY_B = (0x0000a140) +FERMI_CONTEXT_SHARE_A = (0x00009067) +KEPLER_CHANNEL_GROUP_A = (0x0000a06c) +PASCAL_DMA_COPY_A = (0x0000c0b5) +TURING_DMA_COPY_A = (0x0000c5b5) +AMPERE_DMA_COPY_A = (0x0000c6b5) +AMPERE_DMA_COPY_B = (0x0000c7b5) +HOPPER_DMA_COPY_A = (0x0000c8b5) +BLACKWELL_DMA_COPY_A = (0x0000c9b5) +BLACKWELL_DMA_COPY_B = (0x0000cab5) +MAXWELL_DMA_COPY_A = (0x0000b0b5) +ACCESS_COUNTER_NOTIFY_BUFFER = (0x0000c365) +MMU_FAULT_BUFFER = (0x0000c369) +MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c763) +TURING_A = (0x0000c597) +TURING_COMPUTE_A = (0x0000c5c0) +AMPERE_A = (0x0000c697) +AMPERE_COMPUTE_A = (0x0000c6c0) +AMPERE_B = (0x0000c797) +AMPERE_COMPUTE_B = (0x0000c7c0) +ADA_A = (0x0000c997) +ADA_COMPUTE_A = (0x0000c9c0) +AMPERE_SMC_PARTITION_REF = (0x0000c637) +AMPERE_SMC_EXEC_PARTITION_REF = (0x0000c638) +AMPERE_SMC_CONFIG_SESSION = (0x0000c639) +NV0092_RG_LINE_CALLBACK = (0x00000092) +AMPERE_SMC_MONITOR_SESSION = (0x0000c640) +HOPPER_A = (0x0000cb97) +HOPPER_COMPUTE_A = (0x0000cbc0) +BLACKWELL_A = (0x0000cd97) +BLACKWELL_COMPUTE_A = (0x0000cdc0) +BLACKWELL_B = (0x0000ce97) +BLACKWELL_COMPUTE_B = (0x0000cec0) +BLACKWELL_INLINE_TO_MEMORY_A = (0x0000cd40) +NV40_DEBUG_BUFFER = (0x000000db) +RM_USER_SHARED_DATA = (0x000000de) +GT200_DEBUGGER = (0x000083de) +NV40_I2C = (0x0000402c) +KEPLER_DEVICE_VGPU = (0x0000a080) +NVA081_VGPU_CONFIG = (0x0000a081) +NVA084_KERNEL_HOST_VGPU_DEVICE = (0x0000a084) +NV0060_SYNC_GPU_BOOST = (0x00000060) +GP100_UVM_SW = (0x0000c076) +NVENC_SW_SESSION = (0x0000a0bc) +NV_EVENT_BUFFER = (0x000090cd) +NVFBC_SW_SESSION = (0x0000a0bd) +NV_CONFIDENTIAL_COMPUTE = (0x0000cb33) +NV_COUNTER_COLLECTION_UNIT = (0x0000cbca) +NV_SEMAPHORE_SURFACE = (0x000000da) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/nvjitlink.py b/tinygrad/runtime/autogen/nvjitlink.py new file mode 100644 index 0000000000..f2d88bae1f --- /dev/null +++ b/tinygrad/runtime/autogen/nvjitlink.py @@ -0,0 +1,89 @@ +# mypy: ignore-errors +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(find_library('nvJitLink'))) + except: pass + return None +dll = dll() + +nvJitLinkResult = CEnum(ctypes.c_uint32) +NVJITLINK_SUCCESS = nvJitLinkResult.define('NVJITLINK_SUCCESS', 0) +NVJITLINK_ERROR_UNRECOGNIZED_OPTION = nvJitLinkResult.define('NVJITLINK_ERROR_UNRECOGNIZED_OPTION', 1) +NVJITLINK_ERROR_MISSING_ARCH = nvJitLinkResult.define('NVJITLINK_ERROR_MISSING_ARCH', 2) +NVJITLINK_ERROR_INVALID_INPUT = nvJitLinkResult.define('NVJITLINK_ERROR_INVALID_INPUT', 3) +NVJITLINK_ERROR_PTX_COMPILE = nvJitLinkResult.define('NVJITLINK_ERROR_PTX_COMPILE', 4) +NVJITLINK_ERROR_NVVM_COMPILE = nvJitLinkResult.define('NVJITLINK_ERROR_NVVM_COMPILE', 5) +NVJITLINK_ERROR_INTERNAL = nvJitLinkResult.define('NVJITLINK_ERROR_INTERNAL', 6) + +nvJitLinkInputType = CEnum(ctypes.c_uint32) +NVJITLINK_INPUT_NONE = nvJitLinkInputType.define('NVJITLINK_INPUT_NONE', 0) +NVJITLINK_INPUT_CUBIN = nvJitLinkInputType.define('NVJITLINK_INPUT_CUBIN', 1) +NVJITLINK_INPUT_PTX = nvJitLinkInputType.define('NVJITLINK_INPUT_PTX', 2) +NVJITLINK_INPUT_LTOIR = nvJitLinkInputType.define('NVJITLINK_INPUT_LTOIR', 3) +NVJITLINK_INPUT_FATBIN = nvJitLinkInputType.define('NVJITLINK_INPUT_FATBIN', 4) +NVJITLINK_INPUT_OBJECT = nvJitLinkInputType.define('NVJITLINK_INPUT_OBJECT', 5) +NVJITLINK_INPUT_LIBRARY = nvJitLinkInputType.define('NVJITLINK_INPUT_LIBRARY', 6) + +class struct_nvJitLink(Struct): pass +nvJitLinkHandle = ctypes.POINTER(struct_nvJitLink) +uint32_t = ctypes.c_uint32 +# nvJitLinkResult nvJitLinkCreate(nvJitLinkHandle *handle, uint32_t numOptions, const char **options) +try: (nvJitLinkCreate:=dll.nvJitLinkCreate).restype, nvJitLinkCreate.argtypes = nvJitLinkResult, [ctypes.POINTER(nvJitLinkHandle), uint32_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkDestroy(nvJitLinkHandle *handle) +try: (nvJitLinkDestroy:=dll.nvJitLinkDestroy).restype, nvJitLinkDestroy.argtypes = nvJitLinkResult, [ctypes.POINTER(nvJitLinkHandle)] +except AttributeError: pass + +size_t = ctypes.c_uint64 +# nvJitLinkResult nvJitLinkAddData(nvJitLinkHandle handle, nvJitLinkInputType inputType, const void *data, size_t size, const char *name) +try: (nvJitLinkAddData:=dll.nvJitLinkAddData).restype, nvJitLinkAddData.argtypes = nvJitLinkResult, [nvJitLinkHandle, nvJitLinkInputType, ctypes.c_void_p, size_t, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkAddFile(nvJitLinkHandle handle, nvJitLinkInputType inputType, const char *fileName) +try: (nvJitLinkAddFile:=dll.nvJitLinkAddFile).restype, nvJitLinkAddFile.argtypes = nvJitLinkResult, [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkComplete(nvJitLinkHandle handle) +try: (nvJitLinkComplete:=dll.nvJitLinkComplete).restype, nvJitLinkComplete.argtypes = nvJitLinkResult, [nvJitLinkHandle] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetLinkedCubinSize(nvJitLinkHandle handle, size_t *size) +try: (nvJitLinkGetLinkedCubinSize:=dll.nvJitLinkGetLinkedCubinSize).restype, nvJitLinkGetLinkedCubinSize.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetLinkedCubin(nvJitLinkHandle handle, void *cubin) +try: (nvJitLinkGetLinkedCubin:=dll.nvJitLinkGetLinkedCubin).restype, nvJitLinkGetLinkedCubin.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.c_void_p] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetLinkedPtxSize(nvJitLinkHandle handle, size_t *size) +try: (nvJitLinkGetLinkedPtxSize:=dll.nvJitLinkGetLinkedPtxSize).restype, nvJitLinkGetLinkedPtxSize.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetLinkedPtx(nvJitLinkHandle handle, char *ptx) +try: (nvJitLinkGetLinkedPtx:=dll.nvJitLinkGetLinkedPtx).restype, nvJitLinkGetLinkedPtx.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetErrorLogSize(nvJitLinkHandle handle, size_t *size) +try: (nvJitLinkGetErrorLogSize:=dll.nvJitLinkGetErrorLogSize).restype, nvJitLinkGetErrorLogSize.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetErrorLog(nvJitLinkHandle handle, char *log) +try: (nvJitLinkGetErrorLog:=dll.nvJitLinkGetErrorLog).restype, nvJitLinkGetErrorLog.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetInfoLogSize(nvJitLinkHandle handle, size_t *size) +try: (nvJitLinkGetInfoLogSize:=dll.nvJitLinkGetInfoLogSize).restype, nvJitLinkGetInfoLogSize.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkGetInfoLog(nvJitLinkHandle handle, char *log) +try: (nvJitLinkGetInfoLog:=dll.nvJitLinkGetInfoLog).restype, nvJitLinkGetInfoLog.argtypes = nvJitLinkResult, [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvJitLinkResult nvJitLinkVersion(unsigned int *major, unsigned int *minor) +try: (nvJitLinkVersion:=dll.nvJitLinkVersion).restype, nvJitLinkVersion.argtypes = nvJitLinkResult, [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] +except AttributeError: pass + diff --git a/tinygrad/runtime/autogen/nvrtc.py b/tinygrad/runtime/autogen/nvrtc.py index 49253c1f93..5dfdd734f7 100644 --- a/tinygrad/runtime/autogen/nvrtc.py +++ b/tinygrad/runtime/autogen/nvrtc.py @@ -1,581 +1,113 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(find_library('nvrtc'))) + except: pass + return None +dll = dll() +nvrtcResult = CEnum(ctypes.c_uint32) +NVRTC_SUCCESS = nvrtcResult.define('NVRTC_SUCCESS', 0) +NVRTC_ERROR_OUT_OF_MEMORY = nvrtcResult.define('NVRTC_ERROR_OUT_OF_MEMORY', 1) +NVRTC_ERROR_PROGRAM_CREATION_FAILURE = nvrtcResult.define('NVRTC_ERROR_PROGRAM_CREATION_FAILURE', 2) +NVRTC_ERROR_INVALID_INPUT = nvrtcResult.define('NVRTC_ERROR_INVALID_INPUT', 3) +NVRTC_ERROR_INVALID_PROGRAM = nvrtcResult.define('NVRTC_ERROR_INVALID_PROGRAM', 4) +NVRTC_ERROR_INVALID_OPTION = nvrtcResult.define('NVRTC_ERROR_INVALID_OPTION', 5) +NVRTC_ERROR_COMPILATION = nvrtcResult.define('NVRTC_ERROR_COMPILATION', 6) +NVRTC_ERROR_BUILTIN_OPERATION_FAILURE = nvrtcResult.define('NVRTC_ERROR_BUILTIN_OPERATION_FAILURE', 7) +NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION = nvrtcResult.define('NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', 8) +NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION = nvrtcResult.define('NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', 9) +NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID = nvrtcResult.define('NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID', 10) +NVRTC_ERROR_INTERNAL_ERROR = nvrtcResult.define('NVRTC_ERROR_INTERNAL_ERROR', 11) -_libraries = {} -_libraries['libnvrtc.so'] = ctypes.CDLL(ctypes.util.find_library('nvrtc')) -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value +# const char *nvrtcGetErrorString(nvrtcResult result) +try: (nvrtcGetErrorString:=dll.nvrtcGetErrorString).restype, nvrtcGetErrorString.argtypes = ctypes.POINTER(ctypes.c_char), [nvrtcResult] +except AttributeError: pass +# nvrtcResult nvrtcVersion(int *major, int *minor) +try: (nvrtcVersion:=dll.nvrtcVersion).restype, nvrtcVersion.argtypes = nvrtcResult, [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) +# nvrtcResult nvrtcGetNumSupportedArchs(int *numArchs) +try: (nvrtcGetNumSupportedArchs:=dll.nvrtcGetNumSupportedArchs).restype, nvrtcGetNumSupportedArchs.argtypes = nvrtcResult, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass +# nvrtcResult nvrtcGetSupportedArchs(int *supportedArchs) +try: (nvrtcGetSupportedArchs:=dll.nvrtcGetSupportedArchs).restype, nvrtcGetSupportedArchs.argtypes = nvrtcResult, [ctypes.POINTER(ctypes.c_int32)] +except AttributeError: pass - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -_libraries['libnvJitLink.so'] = ctypes.CDLL(ctypes.util.find_library('nvJitLink')) -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - - -# values for enumeration 'c__EA_nvrtcResult' -c__EA_nvrtcResult__enumvalues = { - 0: 'NVRTC_SUCCESS', - 1: 'NVRTC_ERROR_OUT_OF_MEMORY', - 2: 'NVRTC_ERROR_PROGRAM_CREATION_FAILURE', - 3: 'NVRTC_ERROR_INVALID_INPUT', - 4: 'NVRTC_ERROR_INVALID_PROGRAM', - 5: 'NVRTC_ERROR_INVALID_OPTION', - 6: 'NVRTC_ERROR_COMPILATION', - 7: 'NVRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 8: 'NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 9: 'NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 10: 'NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 11: 'NVRTC_ERROR_INTERNAL_ERROR', - 12: 'NVRTC_ERROR_TIME_FILE_WRITE_FAILED', -} -NVRTC_SUCCESS = 0 -NVRTC_ERROR_OUT_OF_MEMORY = 1 -NVRTC_ERROR_PROGRAM_CREATION_FAILURE = 2 -NVRTC_ERROR_INVALID_INPUT = 3 -NVRTC_ERROR_INVALID_PROGRAM = 4 -NVRTC_ERROR_INVALID_OPTION = 5 -NVRTC_ERROR_COMPILATION = 6 -NVRTC_ERROR_BUILTIN_OPERATION_FAILURE = 7 -NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION = 8 -NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION = 9 -NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID = 10 -NVRTC_ERROR_INTERNAL_ERROR = 11 -NVRTC_ERROR_TIME_FILE_WRITE_FAILED = 12 -c__EA_nvrtcResult = ctypes.c_uint32 # enum -nvrtcResult = c__EA_nvrtcResult -nvrtcResult__enumvalues = c__EA_nvrtcResult__enumvalues -try: - nvrtcGetErrorString = _libraries['libnvrtc.so'].nvrtcGetErrorString - nvrtcGetErrorString.restype = ctypes.POINTER(ctypes.c_char) - nvrtcGetErrorString.argtypes = [nvrtcResult] -except AttributeError: - pass -try: - nvrtcVersion = _libraries['libnvrtc.so'].nvrtcVersion - nvrtcVersion.restype = nvrtcResult - nvrtcVersion.argtypes = [ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - nvrtcGetNumSupportedArchs = _libraries['libnvrtc.so'].nvrtcGetNumSupportedArchs - nvrtcGetNumSupportedArchs.restype = nvrtcResult - nvrtcGetNumSupportedArchs.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - nvrtcGetSupportedArchs = _libraries['libnvrtc.so'].nvrtcGetSupportedArchs - nvrtcGetSupportedArchs.restype = nvrtcResult - nvrtcGetSupportedArchs.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -class struct__nvrtcProgram(Structure): - pass - +class struct__nvrtcProgram(Struct): pass nvrtcProgram = ctypes.POINTER(struct__nvrtcProgram) -try: - nvrtcCreateProgram = _libraries['libnvrtc.so'].nvrtcCreateProgram - nvrtcCreateProgram.restype = nvrtcResult - nvrtcCreateProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__nvrtcProgram)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - nvrtcDestroyProgram = _libraries['libnvrtc.so'].nvrtcDestroyProgram - nvrtcDestroyProgram.restype = nvrtcResult - nvrtcDestroyProgram.argtypes = [ctypes.POINTER(ctypes.POINTER(struct__nvrtcProgram))] -except AttributeError: - pass -try: - nvrtcCompileProgram = _libraries['libnvrtc.so'].nvrtcCompileProgram - nvrtcCompileProgram.restype = nvrtcResult - nvrtcCompileProgram.argtypes = [nvrtcProgram, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - nvrtcGetPTXSize = _libraries['libnvrtc.so'].nvrtcGetPTXSize - nvrtcGetPTXSize.restype = nvrtcResult - nvrtcGetPTXSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetPTX = _libraries['libnvrtc.so'].nvrtcGetPTX - nvrtcGetPTX.restype = nvrtcResult - nvrtcGetPTX.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetCUBINSize = _libraries['libnvrtc.so'].nvrtcGetCUBINSize - nvrtcGetCUBINSize.restype = nvrtcResult - nvrtcGetCUBINSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetCUBIN = _libraries['libnvrtc.so'].nvrtcGetCUBIN - nvrtcGetCUBIN.restype = nvrtcResult - nvrtcGetCUBIN.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetNVVMSize = _libraries['libnvrtc.so'].nvrtcGetNVVMSize - nvrtcGetNVVMSize.restype = nvrtcResult - nvrtcGetNVVMSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetNVVM = _libraries['libnvrtc.so'].nvrtcGetNVVM - nvrtcGetNVVM.restype = nvrtcResult - nvrtcGetNVVM.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetLTOIRSize = _libraries['libnvrtc.so'].nvrtcGetLTOIRSize - nvrtcGetLTOIRSize.restype = nvrtcResult - nvrtcGetLTOIRSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetLTOIR = _libraries['libnvrtc.so'].nvrtcGetLTOIR - nvrtcGetLTOIR.restype = nvrtcResult - nvrtcGetLTOIR.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetOptiXIRSize = _libraries['libnvrtc.so'].nvrtcGetOptiXIRSize - nvrtcGetOptiXIRSize.restype = nvrtcResult - nvrtcGetOptiXIRSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetOptiXIR = _libraries['libnvrtc.so'].nvrtcGetOptiXIR - nvrtcGetOptiXIR.restype = nvrtcResult - nvrtcGetOptiXIR.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetProgramLogSize = _libraries['libnvrtc.so'].nvrtcGetProgramLogSize - nvrtcGetProgramLogSize.restype = nvrtcResult - nvrtcGetProgramLogSize.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvrtcGetProgramLog = _libraries['libnvrtc.so'].nvrtcGetProgramLog - nvrtcGetProgramLog.restype = nvrtcResult - nvrtcGetProgramLog.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcAddNameExpression = _libraries['libnvrtc.so'].nvrtcAddNameExpression - nvrtcAddNameExpression.restype = nvrtcResult - nvrtcAddNameExpression.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvrtcGetLoweredName = _libraries['libnvrtc.so'].nvrtcGetLoweredName - nvrtcGetLoweredName.restype = nvrtcResult - nvrtcGetLoweredName.argtypes = [nvrtcProgram, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass +# nvrtcResult nvrtcCreateProgram(nvrtcProgram *prog, const char *src, const char *name, int numHeaders, const char *const *headers, const char *const *includeNames) +try: (nvrtcCreateProgram:=dll.nvrtcCreateProgram).restype, nvrtcCreateProgram.argtypes = nvrtcResult, [ctypes.POINTER(nvrtcProgram), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass -# values for enumeration 'c__EA_nvJitLinkResult' -c__EA_nvJitLinkResult__enumvalues = { - 0: 'NVJITLINK_SUCCESS', - 1: 'NVJITLINK_ERROR_UNRECOGNIZED_OPTION', - 2: 'NVJITLINK_ERROR_MISSING_ARCH', - 3: 'NVJITLINK_ERROR_INVALID_INPUT', - 4: 'NVJITLINK_ERROR_PTX_COMPILE', - 5: 'NVJITLINK_ERROR_NVVM_COMPILE', - 6: 'NVJITLINK_ERROR_INTERNAL', - 7: 'NVJITLINK_ERROR_THREADPOOL', - 8: 'NVJITLINK_ERROR_UNRECOGNIZED_INPUT', -} -NVJITLINK_SUCCESS = 0 -NVJITLINK_ERROR_UNRECOGNIZED_OPTION = 1 -NVJITLINK_ERROR_MISSING_ARCH = 2 -NVJITLINK_ERROR_INVALID_INPUT = 3 -NVJITLINK_ERROR_PTX_COMPILE = 4 -NVJITLINK_ERROR_NVVM_COMPILE = 5 -NVJITLINK_ERROR_INTERNAL = 6 -NVJITLINK_ERROR_THREADPOOL = 7 -NVJITLINK_ERROR_UNRECOGNIZED_INPUT = 8 -c__EA_nvJitLinkResult = ctypes.c_uint32 # enum -nvJitLinkResult = c__EA_nvJitLinkResult -nvJitLinkResult__enumvalues = c__EA_nvJitLinkResult__enumvalues +# nvrtcResult nvrtcDestroyProgram(nvrtcProgram *prog) +try: (nvrtcDestroyProgram:=dll.nvrtcDestroyProgram).restype, nvrtcDestroyProgram.argtypes = nvrtcResult, [ctypes.POINTER(nvrtcProgram)] +except AttributeError: pass -# values for enumeration 'c__EA_nvJitLinkInputType' -c__EA_nvJitLinkInputType__enumvalues = { - 0: 'NVJITLINK_INPUT_NONE', - 1: 'NVJITLINK_INPUT_CUBIN', - 2: 'NVJITLINK_INPUT_PTX', - 3: 'NVJITLINK_INPUT_LTOIR', - 4: 'NVJITLINK_INPUT_FATBIN', - 5: 'NVJITLINK_INPUT_OBJECT', - 6: 'NVJITLINK_INPUT_LIBRARY', - 10: 'NVJITLINK_INPUT_ANY', -} -NVJITLINK_INPUT_NONE = 0 -NVJITLINK_INPUT_CUBIN = 1 -NVJITLINK_INPUT_PTX = 2 -NVJITLINK_INPUT_LTOIR = 3 -NVJITLINK_INPUT_FATBIN = 4 -NVJITLINK_INPUT_OBJECT = 5 -NVJITLINK_INPUT_LIBRARY = 6 -NVJITLINK_INPUT_ANY = 10 -c__EA_nvJitLinkInputType = ctypes.c_uint32 # enum -nvJitLinkInputType = c__EA_nvJitLinkInputType -nvJitLinkInputType__enumvalues = c__EA_nvJitLinkInputType__enumvalues -class struct_nvJitLink(Structure): - pass +# nvrtcResult nvrtcCompileProgram(nvrtcProgram prog, int numOptions, const char *const *options) +try: (nvrtcCompileProgram:=dll.nvrtcCompileProgram).restype, nvrtcCompileProgram.argtypes = nvrtcResult, [nvrtcProgram, ctypes.c_int32, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass -nvJitLinkHandle = ctypes.POINTER(struct_nvJitLink) -uint32_t = ctypes.c_uint32 -try: - __nvJitLinkCreate_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkCreate_12_4 - __nvJitLinkCreate_12_4.restype = nvJitLinkResult - __nvJitLinkCreate_12_4.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink)), uint32_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - nvJitLinkCreate = _libraries['libnvJitLink.so'].nvJitLinkCreate - nvJitLinkCreate.restype = nvJitLinkResult - nvJitLinkCreate.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink)), uint32_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - __nvJitLinkDestroy_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkDestroy_12_4 - __nvJitLinkDestroy_12_4.restype = nvJitLinkResult - __nvJitLinkDestroy_12_4.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink))] -except AttributeError: - pass -try: - nvJitLinkDestroy = _libraries['libnvJitLink.so'].nvJitLinkDestroy - nvJitLinkDestroy.restype = nvJitLinkResult - nvJitLinkDestroy.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_nvJitLink))] -except AttributeError: - pass size_t = ctypes.c_uint64 -try: - __nvJitLinkAddData_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkAddData_12_4 - __nvJitLinkAddData_12_4.restype = nvJitLinkResult - __nvJitLinkAddData_12_4.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkAddData = _libraries['libnvJitLink.so'].nvJitLinkAddData - nvJitLinkAddData.restype = nvJitLinkResult - nvJitLinkAddData.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkAddFile_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkAddFile_12_4 - __nvJitLinkAddFile_12_4.restype = nvJitLinkResult - __nvJitLinkAddFile_12_4.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkAddFile = _libraries['libnvJitLink.so'].nvJitLinkAddFile - nvJitLinkAddFile.restype = nvJitLinkResult - nvJitLinkAddFile.argtypes = [nvJitLinkHandle, nvJitLinkInputType, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkComplete_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkComplete_12_4 - __nvJitLinkComplete_12_4.restype = nvJitLinkResult - __nvJitLinkComplete_12_4.argtypes = [nvJitLinkHandle] -except AttributeError: - pass -try: - nvJitLinkComplete = _libraries['libnvJitLink.so'].nvJitLinkComplete - nvJitLinkComplete.restype = nvJitLinkResult - nvJitLinkComplete.argtypes = [nvJitLinkHandle] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedCubinSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedCubinSize_12_4 - __nvJitLinkGetLinkedCubinSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedCubinSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedCubinSize = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedCubinSize - nvJitLinkGetLinkedCubinSize.restype = nvJitLinkResult - nvJitLinkGetLinkedCubinSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedCubin_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedCubin_12_4 - __nvJitLinkGetLinkedCubin_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedCubin_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(None)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedCubin = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedCubin - nvJitLinkGetLinkedCubin.restype = nvJitLinkResult - nvJitLinkGetLinkedCubin.argtypes = [nvJitLinkHandle, ctypes.POINTER(None)] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedPtxSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedPtxSize_12_4 - __nvJitLinkGetLinkedPtxSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedPtxSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedPtxSize = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedPtxSize - nvJitLinkGetLinkedPtxSize.restype = nvJitLinkResult - nvJitLinkGetLinkedPtxSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetLinkedPtx_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetLinkedPtx_12_4 - __nvJitLinkGetLinkedPtx_12_4.restype = nvJitLinkResult - __nvJitLinkGetLinkedPtx_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkGetLinkedPtx = _libraries['libnvJitLink.so'].nvJitLinkGetLinkedPtx - nvJitLinkGetLinkedPtx.restype = nvJitLinkResult - nvJitLinkGetLinkedPtx.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkGetErrorLogSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetErrorLogSize_12_4 - __nvJitLinkGetErrorLogSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetErrorLogSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetErrorLogSize = _libraries['libnvJitLink.so'].nvJitLinkGetErrorLogSize - nvJitLinkGetErrorLogSize.restype = nvJitLinkResult - nvJitLinkGetErrorLogSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetErrorLog_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetErrorLog_12_4 - __nvJitLinkGetErrorLog_12_4.restype = nvJitLinkResult - __nvJitLinkGetErrorLog_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkGetErrorLog = _libraries['libnvJitLink.so'].nvJitLinkGetErrorLog - nvJitLinkGetErrorLog.restype = nvJitLinkResult - nvJitLinkGetErrorLog.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - __nvJitLinkGetInfoLogSize_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetInfoLogSize_12_4 - __nvJitLinkGetInfoLogSize_12_4.restype = nvJitLinkResult - __nvJitLinkGetInfoLogSize_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - nvJitLinkGetInfoLogSize = _libraries['libnvJitLink.so'].nvJitLinkGetInfoLogSize - nvJitLinkGetInfoLogSize.restype = nvJitLinkResult - nvJitLinkGetInfoLogSize.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - __nvJitLinkGetInfoLog_12_4 = _libraries['libnvJitLink.so'].__nvJitLinkGetInfoLog_12_4 - __nvJitLinkGetInfoLog_12_4.restype = nvJitLinkResult - __nvJitLinkGetInfoLog_12_4.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkGetInfoLog = _libraries['libnvJitLink.so'].nvJitLinkGetInfoLog - nvJitLinkGetInfoLog.restype = nvJitLinkResult - nvJitLinkGetInfoLog.argtypes = [nvJitLinkHandle, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - nvJitLinkVersion = _libraries['libnvJitLink.so'].nvJitLinkVersion - nvJitLinkVersion.restype = nvJitLinkResult - nvJitLinkVersion.argtypes = [ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -__all__ = \ - ['NVJITLINK_ERROR_INTERNAL', 'NVJITLINK_ERROR_INVALID_INPUT', - 'NVJITLINK_ERROR_MISSING_ARCH', 'NVJITLINK_ERROR_NVVM_COMPILE', - 'NVJITLINK_ERROR_PTX_COMPILE', 'NVJITLINK_ERROR_THREADPOOL', - 'NVJITLINK_ERROR_UNRECOGNIZED_INPUT', - 'NVJITLINK_ERROR_UNRECOGNIZED_OPTION', 'NVJITLINK_INPUT_ANY', - 'NVJITLINK_INPUT_CUBIN', 'NVJITLINK_INPUT_FATBIN', - 'NVJITLINK_INPUT_LIBRARY', 'NVJITLINK_INPUT_LTOIR', - 'NVJITLINK_INPUT_NONE', 'NVJITLINK_INPUT_OBJECT', - 'NVJITLINK_INPUT_PTX', 'NVJITLINK_SUCCESS', - 'NVRTC_ERROR_BUILTIN_OPERATION_FAILURE', - 'NVRTC_ERROR_COMPILATION', 'NVRTC_ERROR_INTERNAL_ERROR', - 'NVRTC_ERROR_INVALID_INPUT', 'NVRTC_ERROR_INVALID_OPTION', - 'NVRTC_ERROR_INVALID_PROGRAM', - 'NVRTC_ERROR_NAME_EXPRESSION_NOT_VALID', - 'NVRTC_ERROR_NO_LOWERED_NAMES_BEFORE_COMPILATION', - 'NVRTC_ERROR_NO_NAME_EXPRESSIONS_AFTER_COMPILATION', - 'NVRTC_ERROR_OUT_OF_MEMORY', - 'NVRTC_ERROR_PROGRAM_CREATION_FAILURE', - 'NVRTC_ERROR_TIME_FILE_WRITE_FAILED', 'NVRTC_SUCCESS', - '__nvJitLinkAddData_12_4', '__nvJitLinkAddFile_12_4', - '__nvJitLinkComplete_12_4', '__nvJitLinkCreate_12_4', - '__nvJitLinkDestroy_12_4', '__nvJitLinkGetErrorLogSize_12_4', - '__nvJitLinkGetErrorLog_12_4', '__nvJitLinkGetInfoLogSize_12_4', - '__nvJitLinkGetInfoLog_12_4', - '__nvJitLinkGetLinkedCubinSize_12_4', - '__nvJitLinkGetLinkedCubin_12_4', - '__nvJitLinkGetLinkedPtxSize_12_4', - '__nvJitLinkGetLinkedPtx_12_4', 'c__EA_nvJitLinkInputType', - 'c__EA_nvJitLinkResult', 'c__EA_nvrtcResult', 'nvJitLinkAddData', - 'nvJitLinkAddFile', 'nvJitLinkComplete', 'nvJitLinkCreate', - 'nvJitLinkDestroy', 'nvJitLinkGetErrorLog', - 'nvJitLinkGetErrorLogSize', 'nvJitLinkGetInfoLog', - 'nvJitLinkGetInfoLogSize', 'nvJitLinkGetLinkedCubin', - 'nvJitLinkGetLinkedCubinSize', 'nvJitLinkGetLinkedPtx', - 'nvJitLinkGetLinkedPtxSize', 'nvJitLinkHandle', - 'nvJitLinkInputType', 'nvJitLinkInputType__enumvalues', - 'nvJitLinkResult', 'nvJitLinkResult__enumvalues', - 'nvJitLinkVersion', 'nvrtcAddNameExpression', - 'nvrtcCompileProgram', 'nvrtcCreateProgram', - 'nvrtcDestroyProgram', 'nvrtcGetCUBIN', 'nvrtcGetCUBINSize', - 'nvrtcGetErrorString', 'nvrtcGetLTOIR', 'nvrtcGetLTOIRSize', - 'nvrtcGetLoweredName', 'nvrtcGetNVVM', 'nvrtcGetNVVMSize', - 'nvrtcGetNumSupportedArchs', 'nvrtcGetOptiXIR', - 'nvrtcGetOptiXIRSize', 'nvrtcGetPTX', 'nvrtcGetPTXSize', - 'nvrtcGetProgramLog', 'nvrtcGetProgramLogSize', - 'nvrtcGetSupportedArchs', 'nvrtcProgram', 'nvrtcResult', - 'nvrtcResult__enumvalues', 'nvrtcVersion', 'size_t', - 'struct__nvrtcProgram', 'struct_nvJitLink', 'uint32_t'] +# nvrtcResult nvrtcGetPTXSize(nvrtcProgram prog, size_t *ptxSizeRet) +try: (nvrtcGetPTXSize:=dll.nvrtcGetPTXSize).restype, nvrtcGetPTXSize.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvrtcResult nvrtcGetPTX(nvrtcProgram prog, char *ptx) +try: (nvrtcGetPTX:=dll.nvrtcGetPTX).restype, nvrtcGetPTX.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvrtcResult nvrtcGetCUBINSize(nvrtcProgram prog, size_t *cubinSizeRet) +try: (nvrtcGetCUBINSize:=dll.nvrtcGetCUBINSize).restype, nvrtcGetCUBINSize.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvrtcResult nvrtcGetCUBIN(nvrtcProgram prog, char *cubin) +try: (nvrtcGetCUBIN:=dll.nvrtcGetCUBIN).restype, nvrtcGetCUBIN.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# __attribute__((deprecated("This function will be removed in a future release. Please use nvrtcGetLTOIRSize instead"))) nvrtcResult nvrtcGetNVVMSize(nvrtcProgram prog, size_t *nvvmSizeRet) +try: (nvrtcGetNVVMSize:=dll.nvrtcGetNVVMSize).restype, nvrtcGetNVVMSize.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# __attribute__((deprecated("This function will be removed in a future release. Please use nvrtcGetLTOIR instead"))) nvrtcResult nvrtcGetNVVM(nvrtcProgram prog, char *nvvm) +try: (nvrtcGetNVVM:=dll.nvrtcGetNVVM).restype, nvrtcGetNVVM.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvrtcResult nvrtcGetLTOIRSize(nvrtcProgram prog, size_t *LTOIRSizeRet) +try: (nvrtcGetLTOIRSize:=dll.nvrtcGetLTOIRSize).restype, nvrtcGetLTOIRSize.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvrtcResult nvrtcGetLTOIR(nvrtcProgram prog, char *LTOIR) +try: (nvrtcGetLTOIR:=dll.nvrtcGetLTOIR).restype, nvrtcGetLTOIR.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvrtcResult nvrtcGetOptiXIRSize(nvrtcProgram prog, size_t *optixirSizeRet) +try: (nvrtcGetOptiXIRSize:=dll.nvrtcGetOptiXIRSize).restype, nvrtcGetOptiXIRSize.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvrtcResult nvrtcGetOptiXIR(nvrtcProgram prog, char *optixir) +try: (nvrtcGetOptiXIR:=dll.nvrtcGetOptiXIR).restype, nvrtcGetOptiXIR.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvrtcResult nvrtcGetProgramLogSize(nvrtcProgram prog, size_t *logSizeRet) +try: (nvrtcGetProgramLogSize:=dll.nvrtcGetProgramLogSize).restype, nvrtcGetProgramLogSize.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(size_t)] +except AttributeError: pass + +# nvrtcResult nvrtcGetProgramLog(nvrtcProgram prog, char *log) +try: (nvrtcGetProgramLog:=dll.nvrtcGetProgramLog).restype, nvrtcGetProgramLog.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvrtcResult nvrtcAddNameExpression(nvrtcProgram prog, const char *const name_expression) +try: (nvrtcAddNameExpression:=dll.nvrtcAddNameExpression).restype, nvrtcAddNameExpression.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# nvrtcResult nvrtcGetLoweredName(nvrtcProgram prog, const char *const name_expression, const char **lowered_name) +try: (nvrtcGetLoweredName:=dll.nvrtcGetLoweredName).restype, nvrtcGetLoweredName.argtypes = nvrtcResult, [nvrtcProgram, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] +except AttributeError: pass + +__DEPRECATED__ = lambda msg: __attribute__((deprecated(msg))) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/opencl.py b/tinygrad/runtime/autogen/opencl.py index 7c9edc01a6..28cbeb4ee4 100644 --- a/tinygrad/runtime/autogen/opencl.py +++ b/tinygrad/runtime/autogen/opencl.py @@ -1,661 +1,31 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -_libraries = {} -_libraries['libOpenCL.so.1'] = ctypes.CDLL(ctypes.util.find_library('OpenCL')) -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -__OPENCL_CL_H = True # macro -CL_NAME_VERSION_MAX_NAME_SIZE = 64 # macro -CL_SUCCESS = 0 # macro -CL_DEVICE_NOT_FOUND = -1 # macro -CL_DEVICE_NOT_AVAILABLE = -2 # macro -CL_COMPILER_NOT_AVAILABLE = -3 # macro -CL_MEM_OBJECT_ALLOCATION_FAILURE = -4 # macro -CL_OUT_OF_RESOURCES = -5 # macro -CL_OUT_OF_HOST_MEMORY = -6 # macro -CL_PROFILING_INFO_NOT_AVAILABLE = -7 # macro -CL_MEM_COPY_OVERLAP = -8 # macro -CL_IMAGE_FORMAT_MISMATCH = -9 # macro -CL_IMAGE_FORMAT_NOT_SUPPORTED = -10 # macro -CL_BUILD_PROGRAM_FAILURE = -11 # macro -CL_MAP_FAILURE = -12 # macro -CL_MISALIGNED_SUB_BUFFER_OFFSET = -13 # macro -CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST = -14 # macro -CL_COMPILE_PROGRAM_FAILURE = -15 # macro -CL_LINKER_NOT_AVAILABLE = -16 # macro -CL_LINK_PROGRAM_FAILURE = -17 # macro -CL_DEVICE_PARTITION_FAILED = -18 # macro -CL_KERNEL_ARG_INFO_NOT_AVAILABLE = -19 # macro -CL_INVALID_VALUE = -30 # macro -CL_INVALID_DEVICE_TYPE = -31 # macro -CL_INVALID_PLATFORM = -32 # macro -CL_INVALID_DEVICE = -33 # macro -CL_INVALID_CONTEXT = -34 # macro -CL_INVALID_QUEUE_PROPERTIES = -35 # macro -CL_INVALID_COMMAND_QUEUE = -36 # macro -CL_INVALID_HOST_PTR = -37 # macro -CL_INVALID_MEM_OBJECT = -38 # macro -CL_INVALID_IMAGE_FORMAT_DESCRIPTOR = -39 # macro -CL_INVALID_IMAGE_SIZE = -40 # macro -CL_INVALID_SAMPLER = -41 # macro -CL_INVALID_BINARY = -42 # macro -CL_INVALID_BUILD_OPTIONS = -43 # macro -CL_INVALID_PROGRAM = -44 # macro -CL_INVALID_PROGRAM_EXECUTABLE = -45 # macro -CL_INVALID_KERNEL_NAME = -46 # macro -CL_INVALID_KERNEL_DEFINITION = -47 # macro -CL_INVALID_KERNEL = -48 # macro -CL_INVALID_ARG_INDEX = -49 # macro -CL_INVALID_ARG_VALUE = -50 # macro -CL_INVALID_ARG_SIZE = -51 # macro -CL_INVALID_KERNEL_ARGS = -52 # macro -CL_INVALID_WORK_DIMENSION = -53 # macro -CL_INVALID_WORK_GROUP_SIZE = -54 # macro -CL_INVALID_WORK_ITEM_SIZE = -55 # macro -CL_INVALID_GLOBAL_OFFSET = -56 # macro -CL_INVALID_EVENT_WAIT_LIST = -57 # macro -CL_INVALID_EVENT = -58 # macro -CL_INVALID_OPERATION = -59 # macro -CL_INVALID_GL_OBJECT = -60 # macro -CL_INVALID_BUFFER_SIZE = -61 # macro -CL_INVALID_MIP_LEVEL = -62 # macro -CL_INVALID_GLOBAL_WORK_SIZE = -63 # macro -CL_INVALID_PROPERTY = -64 # macro -CL_INVALID_IMAGE_DESCRIPTOR = -65 # macro -CL_INVALID_COMPILER_OPTIONS = -66 # macro -CL_INVALID_LINKER_OPTIONS = -67 # macro -CL_INVALID_DEVICE_PARTITION_COUNT = -68 # macro -CL_INVALID_PIPE_SIZE = -69 # macro -CL_INVALID_DEVICE_QUEUE = -70 # macro -CL_INVALID_SPEC_ID = -71 # macro -CL_MAX_SIZE_RESTRICTION_EXCEEDED = -72 # macro -CL_FALSE = 0 # macro -CL_TRUE = 1 # macro -CL_BLOCKING = 1 # macro -CL_NON_BLOCKING = 0 # macro -CL_PLATFORM_PROFILE = 0x0900 # macro -CL_PLATFORM_VERSION = 0x0901 # macro -CL_PLATFORM_NAME = 0x0902 # macro -CL_PLATFORM_VENDOR = 0x0903 # macro -CL_PLATFORM_EXTENSIONS = 0x0904 # macro -CL_PLATFORM_HOST_TIMER_RESOLUTION = 0x0905 # macro -CL_PLATFORM_NUMERIC_VERSION = 0x0906 # macro -CL_PLATFORM_EXTENSIONS_WITH_VERSION = 0x0907 # macro -CL_DEVICE_TYPE_DEFAULT = (1<<0) # macro -CL_DEVICE_TYPE_CPU = (1<<1) # macro -CL_DEVICE_TYPE_GPU = (1<<2) # macro -CL_DEVICE_TYPE_ACCELERATOR = (1<<3) # macro -CL_DEVICE_TYPE_CUSTOM = (1<<4) # macro -CL_DEVICE_TYPE_ALL = 0xFFFFFFFF # macro -CL_DEVICE_TYPE = 0x1000 # macro -CL_DEVICE_VENDOR_ID = 0x1001 # macro -CL_DEVICE_MAX_COMPUTE_UNITS = 0x1002 # macro -CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 0x1003 # macro -CL_DEVICE_MAX_WORK_GROUP_SIZE = 0x1004 # macro -CL_DEVICE_MAX_WORK_ITEM_SIZES = 0x1005 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 0x1006 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 0x1007 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 0x1008 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 0x1009 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 0x100A # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0x100B # macro -CL_DEVICE_MAX_CLOCK_FREQUENCY = 0x100C # macro -CL_DEVICE_ADDRESS_BITS = 0x100D # macro -CL_DEVICE_MAX_READ_IMAGE_ARGS = 0x100E # macro -CL_DEVICE_MAX_WRITE_IMAGE_ARGS = 0x100F # macro -CL_DEVICE_MAX_MEM_ALLOC_SIZE = 0x1010 # macro -CL_DEVICE_IMAGE2D_MAX_WIDTH = 0x1011 # macro -CL_DEVICE_IMAGE2D_MAX_HEIGHT = 0x1012 # macro -CL_DEVICE_IMAGE3D_MAX_WIDTH = 0x1013 # macro -CL_DEVICE_IMAGE3D_MAX_HEIGHT = 0x1014 # macro -CL_DEVICE_IMAGE3D_MAX_DEPTH = 0x1015 # macro -CL_DEVICE_IMAGE_SUPPORT = 0x1016 # macro -CL_DEVICE_MAX_PARAMETER_SIZE = 0x1017 # macro -CL_DEVICE_MAX_SAMPLERS = 0x1018 # macro -CL_DEVICE_MEM_BASE_ADDR_ALIGN = 0x1019 # macro -CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 0x101A # macro -CL_DEVICE_SINGLE_FP_CONFIG = 0x101B # macro -CL_DEVICE_GLOBAL_MEM_CACHE_TYPE = 0x101C # macro -CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0x101D # macro -CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 0x101E # macro -CL_DEVICE_GLOBAL_MEM_SIZE = 0x101F # macro -CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 0x1020 # macro -CL_DEVICE_MAX_CONSTANT_ARGS = 0x1021 # macro -CL_DEVICE_LOCAL_MEM_TYPE = 0x1022 # macro -CL_DEVICE_LOCAL_MEM_SIZE = 0x1023 # macro -CL_DEVICE_ERROR_CORRECTION_SUPPORT = 0x1024 # macro -CL_DEVICE_PROFILING_TIMER_RESOLUTION = 0x1025 # macro -CL_DEVICE_ENDIAN_LITTLE = 0x1026 # macro -CL_DEVICE_AVAILABLE = 0x1027 # macro -CL_DEVICE_COMPILER_AVAILABLE = 0x1028 # macro -CL_DEVICE_EXECUTION_CAPABILITIES = 0x1029 # macro -CL_DEVICE_QUEUE_PROPERTIES = 0x102A # macro -CL_DEVICE_QUEUE_ON_HOST_PROPERTIES = 0x102A # macro -CL_DEVICE_NAME = 0x102B # macro -CL_DEVICE_VENDOR = 0x102C # macro -CL_DRIVER_VERSION = 0x102D # macro -CL_DEVICE_PROFILE = 0x102E # macro -CL_DEVICE_VERSION = 0x102F # macro -CL_DEVICE_EXTENSIONS = 0x1030 # macro -CL_DEVICE_PLATFORM = 0x1031 # macro -CL_DEVICE_DOUBLE_FP_CONFIG = 0x1032 # macro -CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF = 0x1034 # macro -CL_DEVICE_HOST_UNIFIED_MEMORY = 0x1035 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR = 0x1036 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT = 0x1037 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_INT = 0x1038 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG = 0x1039 # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT = 0x103A # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE = 0x103B # macro -CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF = 0x103C # macro -CL_DEVICE_OPENCL_C_VERSION = 0x103D # macro -CL_DEVICE_LINKER_AVAILABLE = 0x103E # macro -CL_DEVICE_BUILT_IN_KERNELS = 0x103F # macro -CL_DEVICE_IMAGE_MAX_BUFFER_SIZE = 0x1040 # macro -CL_DEVICE_IMAGE_MAX_ARRAY_SIZE = 0x1041 # macro -CL_DEVICE_PARENT_DEVICE = 0x1042 # macro -CL_DEVICE_PARTITION_MAX_SUB_DEVICES = 0x1043 # macro -CL_DEVICE_PARTITION_PROPERTIES = 0x1044 # macro -CL_DEVICE_PARTITION_AFFINITY_DOMAIN = 0x1045 # macro -CL_DEVICE_PARTITION_TYPE = 0x1046 # macro -CL_DEVICE_REFERENCE_COUNT = 0x1047 # macro -CL_DEVICE_PREFERRED_INTEROP_USER_SYNC = 0x1048 # macro -CL_DEVICE_PRINTF_BUFFER_SIZE = 0x1049 # macro -CL_DEVICE_IMAGE_PITCH_ALIGNMENT = 0x104A # macro -CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT = 0x104B # macro -CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS = 0x104C # macro -CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE = 0x104D # macro -CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES = 0x104E # macro -CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE = 0x104F # macro -CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE = 0x1050 # macro -CL_DEVICE_MAX_ON_DEVICE_QUEUES = 0x1051 # macro -CL_DEVICE_MAX_ON_DEVICE_EVENTS = 0x1052 # macro -CL_DEVICE_SVM_CAPABILITIES = 0x1053 # macro -CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE = 0x1054 # macro -CL_DEVICE_MAX_PIPE_ARGS = 0x1055 # macro -CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS = 0x1056 # macro -CL_DEVICE_PIPE_MAX_PACKET_SIZE = 0x1057 # macro -CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT = 0x1058 # macro -CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT = 0x1059 # macro -CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT = 0x105A # macro -CL_DEVICE_IL_VERSION = 0x105B # macro -CL_DEVICE_MAX_NUM_SUB_GROUPS = 0x105C # macro -CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS = 0x105D # macro -CL_DEVICE_NUMERIC_VERSION = 0x105E # macro -CL_DEVICE_EXTENSIONS_WITH_VERSION = 0x1060 # macro -CL_DEVICE_ILS_WITH_VERSION = 0x1061 # macro -CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION = 0x1062 # macro -CL_DEVICE_ATOMIC_MEMORY_CAPABILITIES = 0x1063 # macro -CL_DEVICE_ATOMIC_FENCE_CAPABILITIES = 0x1064 # macro -CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT = 0x1065 # macro -CL_DEVICE_OPENCL_C_ALL_VERSIONS = 0x1066 # macro -CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_MULTIPLE = 0x1067 # macro -CL_DEVICE_WORK_GROUP_COLLECTIVE_FUNCTIONS_SUPPORT = 0x1068 # macro -CL_DEVICE_GENERIC_ADDRESS_SPACE_SUPPORT = 0x1069 # macro -CL_DEVICE_OPENCL_C_FEATURES = 0x106F # macro -CL_DEVICE_DEVICE_ENQUEUE_CAPABILITIES = 0x1070 # macro -CL_DEVICE_PIPE_SUPPORT = 0x1071 # macro -CL_DEVICE_LATEST_CONFORMANCE_VERSION_PASSED = 0x1072 # macro -CL_FP_DENORM = (1<<0) # macro -CL_FP_INF_NAN = (1<<1) # macro -CL_FP_ROUND_TO_NEAREST = (1<<2) # macro -CL_FP_ROUND_TO_ZERO = (1<<3) # macro -CL_FP_ROUND_TO_INF = (1<<4) # macro -CL_FP_FMA = (1<<5) # macro -CL_FP_SOFT_FLOAT = (1<<6) # macro -CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT = (1<<7) # macro -CL_NONE = 0x0 # macro -CL_READ_ONLY_CACHE = 0x1 # macro -CL_READ_WRITE_CACHE = 0x2 # macro -CL_LOCAL = 0x1 # macro -CL_GLOBAL = 0x2 # macro -CL_EXEC_KERNEL = (1<<0) # macro -CL_EXEC_NATIVE_KERNEL = (1<<1) # macro -CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE = (1<<0) # macro -CL_QUEUE_PROFILING_ENABLE = (1<<1) # macro -CL_QUEUE_ON_DEVICE = (1<<2) # macro -CL_QUEUE_ON_DEVICE_DEFAULT = (1<<3) # macro -CL_CONTEXT_REFERENCE_COUNT = 0x1080 # macro -CL_CONTEXT_DEVICES = 0x1081 # macro -CL_CONTEXT_PROPERTIES = 0x1082 # macro -CL_CONTEXT_NUM_DEVICES = 0x1083 # macro -CL_CONTEXT_PLATFORM = 0x1084 # macro -CL_CONTEXT_INTEROP_USER_SYNC = 0x1085 # macro -CL_DEVICE_PARTITION_EQUALLY = 0x1086 # macro -CL_DEVICE_PARTITION_BY_COUNTS = 0x1087 # macro -CL_DEVICE_PARTITION_BY_COUNTS_LIST_END = 0x0 # macro -CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN = 0x1088 # macro -CL_DEVICE_AFFINITY_DOMAIN_NUMA = (1<<0) # macro -CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE = (1<<1) # macro -CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE = (1<<2) # macro -CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE = (1<<3) # macro -CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE = (1<<4) # macro -CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE = (1<<5) # macro -CL_DEVICE_SVM_COARSE_GRAIN_BUFFER = (1<<0) # macro -CL_DEVICE_SVM_FINE_GRAIN_BUFFER = (1<<1) # macro -CL_DEVICE_SVM_FINE_GRAIN_SYSTEM = (1<<2) # macro -CL_DEVICE_SVM_ATOMICS = (1<<3) # macro -CL_QUEUE_CONTEXT = 0x1090 # macro -CL_QUEUE_DEVICE = 0x1091 # macro -CL_QUEUE_REFERENCE_COUNT = 0x1092 # macro -CL_QUEUE_PROPERTIES = 0x1093 # macro -CL_QUEUE_SIZE = 0x1094 # macro -CL_QUEUE_DEVICE_DEFAULT = 0x1095 # macro -CL_QUEUE_PROPERTIES_ARRAY = 0x1098 # macro -CL_MEM_READ_WRITE = (1<<0) # macro -CL_MEM_WRITE_ONLY = (1<<1) # macro -CL_MEM_READ_ONLY = (1<<2) # macro -CL_MEM_USE_HOST_PTR = (1<<3) # macro -CL_MEM_ALLOC_HOST_PTR = (1<<4) # macro -CL_MEM_COPY_HOST_PTR = (1<<5) # macro -CL_MEM_HOST_WRITE_ONLY = (1<<7) # macro -CL_MEM_HOST_READ_ONLY = (1<<8) # macro -CL_MEM_HOST_NO_ACCESS = (1<<9) # macro -CL_MEM_SVM_FINE_GRAIN_BUFFER = (1<<10) # macro -CL_MEM_SVM_ATOMICS = (1<<11) # macro -CL_MEM_KERNEL_READ_AND_WRITE = (1<<12) # macro -CL_MIGRATE_MEM_OBJECT_HOST = (1<<0) # macro -CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED = (1<<1) # macro -CL_R = 0x10B0 # macro -CL_A = 0x10B1 # macro -CL_RG = 0x10B2 # macro -CL_RA = 0x10B3 # macro -CL_RGB = 0x10B4 # macro -CL_RGBA = 0x10B5 # macro -CL_BGRA = 0x10B6 # macro -CL_ARGB = 0x10B7 # macro -CL_INTENSITY = 0x10B8 # macro -CL_LUMINANCE = 0x10B9 # macro -CL_Rx = 0x10BA # macro -CL_RGx = 0x10BB # macro -CL_RGBx = 0x10BC # macro -CL_DEPTH = 0x10BD # macro -CL_sRGB = 0x10BF # macro -CL_sRGBx = 0x10C0 # macro -CL_sRGBA = 0x10C1 # macro -CL_sBGRA = 0x10C2 # macro -CL_ABGR = 0x10C3 # macro -CL_SNORM_INT8 = 0x10D0 # macro -CL_SNORM_INT16 = 0x10D1 # macro -CL_UNORM_INT8 = 0x10D2 # macro -CL_UNORM_INT16 = 0x10D3 # macro -CL_UNORM_SHORT_565 = 0x10D4 # macro -CL_UNORM_SHORT_555 = 0x10D5 # macro -CL_UNORM_INT_101010 = 0x10D6 # macro -CL_SIGNED_INT8 = 0x10D7 # macro -CL_SIGNED_INT16 = 0x10D8 # macro -CL_SIGNED_INT32 = 0x10D9 # macro -CL_UNSIGNED_INT8 = 0x10DA # macro -CL_UNSIGNED_INT16 = 0x10DB # macro -CL_UNSIGNED_INT32 = 0x10DC # macro -CL_HALF_FLOAT = 0x10DD # macro -CL_FLOAT = 0x10DE # macro -CL_UNORM_INT_101010_2 = 0x10E0 # macro -CL_MEM_OBJECT_BUFFER = 0x10F0 # macro -CL_MEM_OBJECT_IMAGE2D = 0x10F1 # macro -CL_MEM_OBJECT_IMAGE3D = 0x10F2 # macro -CL_MEM_OBJECT_IMAGE2D_ARRAY = 0x10F3 # macro -CL_MEM_OBJECT_IMAGE1D = 0x10F4 # macro -CL_MEM_OBJECT_IMAGE1D_ARRAY = 0x10F5 # macro -CL_MEM_OBJECT_IMAGE1D_BUFFER = 0x10F6 # macro -CL_MEM_OBJECT_PIPE = 0x10F7 # macro -CL_MEM_TYPE = 0x1100 # macro -CL_MEM_FLAGS = 0x1101 # macro -CL_MEM_SIZE = 0x1102 # macro -CL_MEM_HOST_PTR = 0x1103 # macro -CL_MEM_MAP_COUNT = 0x1104 # macro -CL_MEM_REFERENCE_COUNT = 0x1105 # macro -CL_MEM_CONTEXT = 0x1106 # macro -CL_MEM_ASSOCIATED_MEMOBJECT = 0x1107 # macro -CL_MEM_OFFSET = 0x1108 # macro -CL_MEM_USES_SVM_POINTER = 0x1109 # macro -CL_MEM_PROPERTIES = 0x110A # macro -CL_IMAGE_FORMAT = 0x1110 # macro -CL_IMAGE_ELEMENT_SIZE = 0x1111 # macro -CL_IMAGE_ROW_PITCH = 0x1112 # macro -CL_IMAGE_SLICE_PITCH = 0x1113 # macro -CL_IMAGE_WIDTH = 0x1114 # macro -CL_IMAGE_HEIGHT = 0x1115 # macro -CL_IMAGE_DEPTH = 0x1116 # macro -CL_IMAGE_ARRAY_SIZE = 0x1117 # macro -CL_IMAGE_BUFFER = 0x1118 # macro -CL_IMAGE_NUM_MIP_LEVELS = 0x1119 # macro -CL_IMAGE_NUM_SAMPLES = 0x111A # macro -CL_PIPE_PACKET_SIZE = 0x1120 # macro -CL_PIPE_MAX_PACKETS = 0x1121 # macro -CL_PIPE_PROPERTIES = 0x1122 # macro -CL_ADDRESS_NONE = 0x1130 # macro -CL_ADDRESS_CLAMP_TO_EDGE = 0x1131 # macro -CL_ADDRESS_CLAMP = 0x1132 # macro -CL_ADDRESS_REPEAT = 0x1133 # macro -CL_ADDRESS_MIRRORED_REPEAT = 0x1134 # macro -CL_FILTER_NEAREST = 0x1140 # macro -CL_FILTER_LINEAR = 0x1141 # macro -CL_SAMPLER_REFERENCE_COUNT = 0x1150 # macro -CL_SAMPLER_CONTEXT = 0x1151 # macro -CL_SAMPLER_NORMALIZED_COORDS = 0x1152 # macro -CL_SAMPLER_ADDRESSING_MODE = 0x1153 # macro -CL_SAMPLER_FILTER_MODE = 0x1154 # macro -CL_SAMPLER_MIP_FILTER_MODE = 0x1155 # macro -CL_SAMPLER_LOD_MIN = 0x1156 # macro -CL_SAMPLER_LOD_MAX = 0x1157 # macro -CL_SAMPLER_PROPERTIES = 0x1158 # macro -CL_MAP_READ = (1<<0) # macro -CL_MAP_WRITE = (1<<1) # macro -CL_MAP_WRITE_INVALIDATE_REGION = (1<<2) # macro -CL_PROGRAM_REFERENCE_COUNT = 0x1160 # macro -CL_PROGRAM_CONTEXT = 0x1161 # macro -CL_PROGRAM_NUM_DEVICES = 0x1162 # macro -CL_PROGRAM_DEVICES = 0x1163 # macro -CL_PROGRAM_SOURCE = 0x1164 # macro -CL_PROGRAM_BINARY_SIZES = 0x1165 # macro -CL_PROGRAM_BINARIES = 0x1166 # macro -CL_PROGRAM_NUM_KERNELS = 0x1167 # macro -CL_PROGRAM_KERNEL_NAMES = 0x1168 # macro -CL_PROGRAM_IL = 0x1169 # macro -CL_PROGRAM_SCOPE_GLOBAL_CTORS_PRESENT = 0x116A # macro -CL_PROGRAM_SCOPE_GLOBAL_DTORS_PRESENT = 0x116B # macro -CL_PROGRAM_BUILD_STATUS = 0x1181 # macro -CL_PROGRAM_BUILD_OPTIONS = 0x1182 # macro -CL_PROGRAM_BUILD_LOG = 0x1183 # macro -CL_PROGRAM_BINARY_TYPE = 0x1184 # macro -CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE = 0x1185 # macro -CL_PROGRAM_BINARY_TYPE_NONE = 0x0 # macro -CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT = 0x1 # macro -CL_PROGRAM_BINARY_TYPE_LIBRARY = 0x2 # macro -CL_PROGRAM_BINARY_TYPE_EXECUTABLE = 0x4 # macro -CL_BUILD_SUCCESS = 0 # macro -CL_BUILD_NONE = -1 # macro -CL_BUILD_ERROR = -2 # macro -CL_BUILD_IN_PROGRESS = -3 # macro -CL_KERNEL_FUNCTION_NAME = 0x1190 # macro -CL_KERNEL_NUM_ARGS = 0x1191 # macro -CL_KERNEL_REFERENCE_COUNT = 0x1192 # macro -CL_KERNEL_CONTEXT = 0x1193 # macro -CL_KERNEL_PROGRAM = 0x1194 # macro -CL_KERNEL_ATTRIBUTES = 0x1195 # macro -CL_KERNEL_ARG_ADDRESS_QUALIFIER = 0x1196 # macro -CL_KERNEL_ARG_ACCESS_QUALIFIER = 0x1197 # macro -CL_KERNEL_ARG_TYPE_NAME = 0x1198 # macro -CL_KERNEL_ARG_TYPE_QUALIFIER = 0x1199 # macro -CL_KERNEL_ARG_NAME = 0x119A # macro -CL_KERNEL_ARG_ADDRESS_GLOBAL = 0x119B # macro -CL_KERNEL_ARG_ADDRESS_LOCAL = 0x119C # macro -CL_KERNEL_ARG_ADDRESS_CONSTANT = 0x119D # macro -CL_KERNEL_ARG_ADDRESS_PRIVATE = 0x119E # macro -CL_KERNEL_ARG_ACCESS_READ_ONLY = 0x11A0 # macro -CL_KERNEL_ARG_ACCESS_WRITE_ONLY = 0x11A1 # macro -CL_KERNEL_ARG_ACCESS_READ_WRITE = 0x11A2 # macro -CL_KERNEL_ARG_ACCESS_NONE = 0x11A3 # macro -CL_KERNEL_ARG_TYPE_NONE = 0 # macro -CL_KERNEL_ARG_TYPE_CONST = (1<<0) # macro -CL_KERNEL_ARG_TYPE_RESTRICT = (1<<1) # macro -CL_KERNEL_ARG_TYPE_VOLATILE = (1<<2) # macro -CL_KERNEL_ARG_TYPE_PIPE = (1<<3) # macro -CL_KERNEL_WORK_GROUP_SIZE = 0x11B0 # macro -CL_KERNEL_COMPILE_WORK_GROUP_SIZE = 0x11B1 # macro -CL_KERNEL_LOCAL_MEM_SIZE = 0x11B2 # macro -CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE = 0x11B3 # macro -CL_KERNEL_PRIVATE_MEM_SIZE = 0x11B4 # macro -CL_KERNEL_GLOBAL_WORK_SIZE = 0x11B5 # macro -CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE = 0x2033 # macro -CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE = 0x2034 # macro -CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT = 0x11B8 # macro -CL_KERNEL_MAX_NUM_SUB_GROUPS = 0x11B9 # macro -CL_KERNEL_COMPILE_NUM_SUB_GROUPS = 0x11BA # macro -CL_KERNEL_EXEC_INFO_SVM_PTRS = 0x11B6 # macro -CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM = 0x11B7 # macro -CL_EVENT_COMMAND_QUEUE = 0x11D0 # macro -CL_EVENT_COMMAND_TYPE = 0x11D1 # macro -CL_EVENT_REFERENCE_COUNT = 0x11D2 # macro -CL_EVENT_COMMAND_EXECUTION_STATUS = 0x11D3 # macro -CL_EVENT_CONTEXT = 0x11D4 # macro -CL_COMMAND_NDRANGE_KERNEL = 0x11F0 # macro -CL_COMMAND_TASK = 0x11F1 # macro -CL_COMMAND_NATIVE_KERNEL = 0x11F2 # macro -CL_COMMAND_READ_BUFFER = 0x11F3 # macro -CL_COMMAND_WRITE_BUFFER = 0x11F4 # macro -CL_COMMAND_COPY_BUFFER = 0x11F5 # macro -CL_COMMAND_READ_IMAGE = 0x11F6 # macro -CL_COMMAND_WRITE_IMAGE = 0x11F7 # macro -CL_COMMAND_COPY_IMAGE = 0x11F8 # macro -CL_COMMAND_COPY_IMAGE_TO_BUFFER = 0x11F9 # macro -CL_COMMAND_COPY_BUFFER_TO_IMAGE = 0x11FA # macro -CL_COMMAND_MAP_BUFFER = 0x11FB # macro -CL_COMMAND_MAP_IMAGE = 0x11FC # macro -CL_COMMAND_UNMAP_MEM_OBJECT = 0x11FD # macro -CL_COMMAND_MARKER = 0x11FE # macro -CL_COMMAND_ACQUIRE_GL_OBJECTS = 0x11FF # macro -CL_COMMAND_RELEASE_GL_OBJECTS = 0x1200 # macro -CL_COMMAND_READ_BUFFER_RECT = 0x1201 # macro -CL_COMMAND_WRITE_BUFFER_RECT = 0x1202 # macro -CL_COMMAND_COPY_BUFFER_RECT = 0x1203 # macro -CL_COMMAND_USER = 0x1204 # macro -CL_COMMAND_BARRIER = 0x1205 # macro -CL_COMMAND_MIGRATE_MEM_OBJECTS = 0x1206 # macro -CL_COMMAND_FILL_BUFFER = 0x1207 # macro -CL_COMMAND_FILL_IMAGE = 0x1208 # macro -CL_COMMAND_SVM_FREE = 0x1209 # macro -CL_COMMAND_SVM_MEMCPY = 0x120A # macro -CL_COMMAND_SVM_MEMFILL = 0x120B # macro -CL_COMMAND_SVM_MAP = 0x120C # macro -CL_COMMAND_SVM_UNMAP = 0x120D # macro -CL_COMMAND_SVM_MIGRATE_MEM = 0x120E # macro -CL_COMPLETE = 0x0 # macro -CL_RUNNING = 0x1 # macro -CL_SUBMITTED = 0x2 # macro -CL_QUEUED = 0x3 # macro -CL_BUFFER_CREATE_TYPE_REGION = 0x1220 # macro -CL_PROFILING_COMMAND_QUEUED = 0x1280 # macro -CL_PROFILING_COMMAND_SUBMIT = 0x1281 # macro -CL_PROFILING_COMMAND_START = 0x1282 # macro -CL_PROFILING_COMMAND_END = 0x1283 # macro -CL_PROFILING_COMMAND_COMPLETE = 0x1284 # macro -CL_DEVICE_ATOMIC_ORDER_RELAXED = (1<<0) # macro -CL_DEVICE_ATOMIC_ORDER_ACQ_REL = (1<<1) # macro -CL_DEVICE_ATOMIC_ORDER_SEQ_CST = (1<<2) # macro -CL_DEVICE_ATOMIC_SCOPE_WORK_ITEM = (1<<3) # macro -CL_DEVICE_ATOMIC_SCOPE_WORK_GROUP = (1<<4) # macro -CL_DEVICE_ATOMIC_SCOPE_DEVICE = (1<<5) # macro -CL_DEVICE_ATOMIC_SCOPE_ALL_DEVICES = (1<<6) # macro -CL_DEVICE_QUEUE_SUPPORTED = (1<<0) # macro -CL_DEVICE_QUEUE_REPLACEABLE_DEFAULT = (1<<1) # macro -CL_KHRONOS_VENDOR_ID_CODEPLAY = 0x10004 # macro -CL_VERSION_MAJOR_BITS = (10) # macro -CL_VERSION_MINOR_BITS = (10) # macro -CL_VERSION_PATCH_BITS = (12) # macro -CL_VERSION_MAJOR_MASK = ((1<<(10))-1) # macro -CL_VERSION_MINOR_MASK = ((1<<(10))-1) # macro -CL_VERSION_PATCH_MASK = ((1<<(12))-1) # macro -def CL_VERSION_MAJOR(version): # macro - return ((version)>>((10)+(12))) -def CL_VERSION_MINOR(version): # macro - return (((version)>>(12))&((1<<(10))-1)) -def CL_VERSION_PATCH(version): # macro - return ((version)&((1<<(12))-1)) -def CL_MAKE_VERSION(major, minor, patch): # macro - return ((((major)&((1<<(10))-1))<<((10)+(12)))|(((minor)&((1<<(10))-1))<<(12))|((patch)&((1<<(12))-1))) -class struct__cl_platform_id(Structure): - pass +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(find_library('OpenCL'))) + except: pass + return None +dll = dll() +class struct__cl_platform_id(Struct): pass cl_platform_id = ctypes.POINTER(struct__cl_platform_id) -class struct__cl_device_id(Structure): - pass - +class struct__cl_device_id(Struct): pass cl_device_id = ctypes.POINTER(struct__cl_device_id) -class struct__cl_context(Structure): - pass - +class struct__cl_context(Struct): pass cl_context = ctypes.POINTER(struct__cl_context) -class struct__cl_command_queue(Structure): - pass - +class struct__cl_command_queue(Struct): pass cl_command_queue = ctypes.POINTER(struct__cl_command_queue) -class struct__cl_mem(Structure): - pass - +class struct__cl_mem(Struct): pass cl_mem = ctypes.POINTER(struct__cl_mem) -class struct__cl_program(Structure): - pass - +class struct__cl_program(Struct): pass cl_program = ctypes.POINTER(struct__cl_program) -class struct__cl_kernel(Structure): - pass - +class struct__cl_kernel(Struct): pass cl_kernel = ctypes.POINTER(struct__cl_kernel) -class struct__cl_event(Structure): - pass - +class struct__cl_event(Struct): pass cl_event = ctypes.POINTER(struct__cl_event) -class struct__cl_sampler(Structure): - pass - +class struct__cl_sampler(Struct): pass cl_sampler = ctypes.POINTER(struct__cl_sampler) cl_bool = ctypes.c_uint32 cl_bitfield = ctypes.c_uint64 @@ -711,1085 +81,963 @@ cl_device_device_enqueue_capabilities = ctypes.c_uint64 cl_khronos_vendor_id = ctypes.c_uint32 cl_mem_properties = ctypes.c_uint64 cl_version = ctypes.c_uint32 -class struct__cl_image_format(Structure): - pass - -struct__cl_image_format._pack_ = 1 # source:False +class struct__cl_image_format(Struct): pass struct__cl_image_format._fields_ = [ - ('image_channel_order', ctypes.c_uint32), - ('image_channel_data_type', ctypes.c_uint32), + ('image_channel_order', cl_channel_order), + ('image_channel_data_type', cl_channel_type), ] - cl_image_format = struct__cl_image_format -class struct__cl_image_desc(Structure): - pass - -class union__cl_image_desc_0(Union): - pass - -union__cl_image_desc_0._pack_ = 1 # source:False -union__cl_image_desc_0._fields_ = [ - ('buffer', ctypes.POINTER(struct__cl_mem)), - ('mem_object', ctypes.POINTER(struct__cl_mem)), +class struct__cl_image_desc(Struct): pass +size_t = ctypes.c_uint64 +cl_uint = ctypes.c_uint32 +class struct__cl_image_desc_0(ctypes.Union): pass +struct__cl_image_desc_0._fields_ = [ + ('buffer', cl_mem), + ('mem_object', cl_mem), ] - -struct__cl_image_desc._pack_ = 1 # source:False -struct__cl_image_desc._anonymous_ = ('_0',) +struct__cl_image_desc._anonymous_ = ['_0'] struct__cl_image_desc._fields_ = [ - ('image_type', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('image_width', ctypes.c_uint64), - ('image_height', ctypes.c_uint64), - ('image_depth', ctypes.c_uint64), - ('image_array_size', ctypes.c_uint64), - ('image_row_pitch', ctypes.c_uint64), - ('image_slice_pitch', ctypes.c_uint64), - ('num_mip_levels', ctypes.c_uint32), - ('num_samples', ctypes.c_uint32), - ('_0', union__cl_image_desc_0), + ('image_type', cl_mem_object_type), + ('image_width', size_t), + ('image_height', size_t), + ('image_depth', size_t), + ('image_array_size', size_t), + ('image_row_pitch', size_t), + ('image_slice_pitch', size_t), + ('num_mip_levels', cl_uint), + ('num_samples', cl_uint), + ('_0', struct__cl_image_desc_0), ] - cl_image_desc = struct__cl_image_desc -class struct__cl_buffer_region(Structure): - pass - -struct__cl_buffer_region._pack_ = 1 # source:False +class struct__cl_buffer_region(Struct): pass struct__cl_buffer_region._fields_ = [ - ('origin', ctypes.c_uint64), - ('size', ctypes.c_uint64), + ('origin', size_t), + ('size', size_t), ] - cl_buffer_region = struct__cl_buffer_region -class struct__cl_name_version(Structure): - pass - -struct__cl_name_version._pack_ = 1 # source:False +class struct__cl_name_version(Struct): pass struct__cl_name_version._fields_ = [ - ('version', ctypes.c_uint32), - ('name', ctypes.c_char * 64), + ('version', cl_version), + ('name', (ctypes.c_char * 64)), ] - cl_name_version = struct__cl_name_version cl_int = ctypes.c_int32 -cl_uint = ctypes.c_uint32 -try: - clGetPlatformIDs = _libraries['libOpenCL.so.1'].clGetPlatformIDs - clGetPlatformIDs.restype = cl_int - clGetPlatformIDs.argtypes = [cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_platform_id)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - clGetPlatformInfo = _libraries['libOpenCL.so.1'].clGetPlatformInfo - clGetPlatformInfo.restype = cl_int - clGetPlatformInfo.argtypes = [cl_platform_id, cl_platform_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetDeviceIDs = _libraries['libOpenCL.so.1'].clGetDeviceIDs - clGetDeviceIDs.restype = cl_int - clGetDeviceIDs.argtypes = [cl_platform_id, cl_device_type, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clGetDeviceInfo = _libraries['libOpenCL.so.1'].clGetDeviceInfo - clGetDeviceInfo.restype = cl_int - clGetDeviceInfo.argtypes = [cl_device_id, cl_device_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateSubDevices = _libraries['libOpenCL.so.1'].clCreateSubDevices - clCreateSubDevices.restype = cl_int - clCreateSubDevices.argtypes = [cl_device_id, ctypes.POINTER(ctypes.c_int64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clRetainDevice = _libraries['libOpenCL.so.1'].clRetainDevice - clRetainDevice.restype = cl_int - clRetainDevice.argtypes = [cl_device_id] -except AttributeError: - pass -try: - clReleaseDevice = _libraries['libOpenCL.so.1'].clReleaseDevice - clReleaseDevice.restype = cl_int - clReleaseDevice.argtypes = [cl_device_id] -except AttributeError: - pass -try: - clSetDefaultDeviceCommandQueue = _libraries['libOpenCL.so.1'].clSetDefaultDeviceCommandQueue - clSetDefaultDeviceCommandQueue.restype = cl_int - clSetDefaultDeviceCommandQueue.argtypes = [cl_context, cl_device_id, cl_command_queue] -except AttributeError: - pass -try: - clGetDeviceAndHostTimer = _libraries['libOpenCL.so.1'].clGetDeviceAndHostTimer - clGetDeviceAndHostTimer.restype = cl_int - clGetDeviceAndHostTimer.argtypes = [cl_device_id, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetHostTimer = _libraries['libOpenCL.so.1'].clGetHostTimer - clGetHostTimer.restype = cl_int - clGetHostTimer.argtypes = [cl_device_id, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateContext = _libraries['libOpenCL.so.1'].clCreateContext - clCreateContext.restype = cl_context - clCreateContext.argtypes = [ctypes.POINTER(ctypes.c_int64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateContextFromType = _libraries['libOpenCL.so.1'].clCreateContextFromType - clCreateContextFromType.restype = cl_context - clCreateContextFromType.argtypes = [ctypes.POINTER(ctypes.c_int64), cl_device_type, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainContext = _libraries['libOpenCL.so.1'].clRetainContext - clRetainContext.restype = cl_int - clRetainContext.argtypes = [cl_context] -except AttributeError: - pass -try: - clReleaseContext = _libraries['libOpenCL.so.1'].clReleaseContext - clReleaseContext.restype = cl_int - clReleaseContext.argtypes = [cl_context] -except AttributeError: - pass -try: - clGetContextInfo = _libraries['libOpenCL.so.1'].clGetContextInfo - clGetContextInfo.restype = cl_int - clGetContextInfo.argtypes = [cl_context, cl_context_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clSetContextDestructorCallback = _libraries['libOpenCL.so.1'].clSetContextDestructorCallback - clSetContextDestructorCallback.restype = cl_int - clSetContextDestructorCallback.argtypes = [cl_context, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_context), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clCreateCommandQueueWithProperties = _libraries['libOpenCL.so.1'].clCreateCommandQueueWithProperties - clCreateCommandQueueWithProperties.restype = cl_command_queue - clCreateCommandQueueWithProperties.argtypes = [cl_context, cl_device_id, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainCommandQueue = _libraries['libOpenCL.so.1'].clRetainCommandQueue - clRetainCommandQueue.restype = cl_int - clRetainCommandQueue.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clReleaseCommandQueue = _libraries['libOpenCL.so.1'].clReleaseCommandQueue - clReleaseCommandQueue.restype = cl_int - clReleaseCommandQueue.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clGetCommandQueueInfo = _libraries['libOpenCL.so.1'].clGetCommandQueueInfo - clGetCommandQueueInfo.restype = cl_int - clGetCommandQueueInfo.argtypes = [cl_command_queue, cl_command_queue_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateBuffer = _libraries['libOpenCL.so.1'].clCreateBuffer - clCreateBuffer.restype = cl_mem - clCreateBuffer.argtypes = [cl_context, cl_mem_flags, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateSubBuffer = _libraries['libOpenCL.so.1'].clCreateSubBuffer - clCreateSubBuffer.restype = cl_mem - clCreateSubBuffer.argtypes = [cl_mem, cl_mem_flags, cl_buffer_create_type, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateImage = _libraries['libOpenCL.so.1'].clCreateImage - clCreateImage.restype = cl_mem - clCreateImage.argtypes = [cl_context, cl_mem_flags, ctypes.POINTER(struct__cl_image_format), ctypes.POINTER(struct__cl_image_desc), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreatePipe = _libraries['libOpenCL.so.1'].clCreatePipe - clCreatePipe.restype = cl_mem - clCreatePipe.argtypes = [cl_context, cl_mem_flags, cl_uint, cl_uint, ctypes.POINTER(ctypes.c_int64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateBufferWithProperties = _libraries['libOpenCL.so.1'].clCreateBufferWithProperties - clCreateBufferWithProperties.restype = cl_mem - clCreateBufferWithProperties.argtypes = [cl_context, ctypes.POINTER(ctypes.c_uint64), cl_mem_flags, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateImageWithProperties = _libraries['libOpenCL.so.1'].clCreateImageWithProperties - clCreateImageWithProperties.restype = cl_mem - clCreateImageWithProperties.argtypes = [cl_context, ctypes.POINTER(ctypes.c_uint64), cl_mem_flags, ctypes.POINTER(struct__cl_image_format), ctypes.POINTER(struct__cl_image_desc), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainMemObject = _libraries['libOpenCL.so.1'].clRetainMemObject - clRetainMemObject.restype = cl_int - clRetainMemObject.argtypes = [cl_mem] -except AttributeError: - pass -try: - clReleaseMemObject = _libraries['libOpenCL.so.1'].clReleaseMemObject - clReleaseMemObject.restype = cl_int - clReleaseMemObject.argtypes = [cl_mem] -except AttributeError: - pass -try: - clGetSupportedImageFormats = _libraries['libOpenCL.so.1'].clGetSupportedImageFormats - clGetSupportedImageFormats.restype = cl_int - clGetSupportedImageFormats.argtypes = [cl_context, cl_mem_flags, cl_mem_object_type, cl_uint, ctypes.POINTER(struct__cl_image_format), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clGetMemObjectInfo = _libraries['libOpenCL.so.1'].clGetMemObjectInfo - clGetMemObjectInfo.restype = cl_int - clGetMemObjectInfo.argtypes = [cl_mem, cl_mem_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetImageInfo = _libraries['libOpenCL.so.1'].clGetImageInfo - clGetImageInfo.restype = cl_int - clGetImageInfo.argtypes = [cl_mem, cl_image_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetPipeInfo = _libraries['libOpenCL.so.1'].clGetPipeInfo - clGetPipeInfo.restype = cl_int - clGetPipeInfo.argtypes = [cl_mem, cl_pipe_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clSetMemObjectDestructorCallback = _libraries['libOpenCL.so.1'].clSetMemObjectDestructorCallback - clSetMemObjectDestructorCallback.restype = cl_int - clSetMemObjectDestructorCallback.argtypes = [cl_mem, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_mem), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSVMAlloc = _libraries['libOpenCL.so.1'].clSVMAlloc - clSVMAlloc.restype = ctypes.POINTER(None) - clSVMAlloc.argtypes = [cl_context, cl_svm_mem_flags, size_t, cl_uint] -except AttributeError: - pass -try: - clSVMFree = _libraries['libOpenCL.so.1'].clSVMFree - clSVMFree.restype = None - clSVMFree.argtypes = [cl_context, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clCreateSamplerWithProperties = _libraries['libOpenCL.so.1'].clCreateSamplerWithProperties - clCreateSamplerWithProperties.restype = cl_sampler - clCreateSamplerWithProperties.argtypes = [cl_context, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainSampler = _libraries['libOpenCL.so.1'].clRetainSampler - clRetainSampler.restype = cl_int - clRetainSampler.argtypes = [cl_sampler] -except AttributeError: - pass -try: - clReleaseSampler = _libraries['libOpenCL.so.1'].clReleaseSampler - clReleaseSampler.restype = cl_int - clReleaseSampler.argtypes = [cl_sampler] -except AttributeError: - pass -try: - clGetSamplerInfo = _libraries['libOpenCL.so.1'].clGetSamplerInfo - clGetSamplerInfo.restype = cl_int - clGetSamplerInfo.argtypes = [cl_sampler, cl_sampler_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateProgramWithSource = _libraries['libOpenCL.so.1'].clCreateProgramWithSource - clCreateProgramWithSource.restype = cl_program - clCreateProgramWithSource.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateProgramWithBinary = _libraries['libOpenCL.so.1'].clCreateProgramWithBinary - clCreateProgramWithBinary.restype = cl_program - clCreateProgramWithBinary.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.POINTER(ctypes.c_ubyte)), ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateProgramWithBuiltInKernels = _libraries['libOpenCL.so.1'].clCreateProgramWithBuiltInKernels - clCreateProgramWithBuiltInKernels.restype = cl_program - clCreateProgramWithBuiltInKernels.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateProgramWithIL = _libraries['libOpenCL.so.1'].clCreateProgramWithIL - clCreateProgramWithIL.restype = cl_program - clCreateProgramWithIL.argtypes = [cl_context, ctypes.POINTER(None), size_t, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainProgram = _libraries['libOpenCL.so.1'].clRetainProgram - clRetainProgram.restype = cl_int - clRetainProgram.argtypes = [cl_program] -except AttributeError: - pass -try: - clReleaseProgram = _libraries['libOpenCL.so.1'].clReleaseProgram - clReleaseProgram.restype = cl_int - clReleaseProgram.argtypes = [cl_program] -except AttributeError: - pass -try: - clBuildProgram = _libraries['libOpenCL.so.1'].clBuildProgram - clBuildProgram.restype = cl_int - clBuildProgram.argtypes = [cl_program, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clCompileProgram = _libraries['libOpenCL.so.1'].clCompileProgram - clCompileProgram.restype = cl_int - clCompileProgram.argtypes = [cl_program, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_program)), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clLinkProgram = _libraries['libOpenCL.so.1'].clLinkProgram - clLinkProgram.restype = cl_program - clLinkProgram.argtypes = [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_device_id)), ctypes.POINTER(ctypes.c_char), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_program)), ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clSetProgramReleaseCallback = _libraries['libOpenCL.so.1'].clSetProgramReleaseCallback - clSetProgramReleaseCallback.restype = cl_int - clSetProgramReleaseCallback.argtypes = [cl_program, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_program), ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSetProgramSpecializationConstant = _libraries['libOpenCL.so.1'].clSetProgramSpecializationConstant - clSetProgramSpecializationConstant.restype = cl_int - clSetProgramSpecializationConstant.argtypes = [cl_program, cl_uint, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clUnloadPlatformCompiler = _libraries['libOpenCL.so.1'].clUnloadPlatformCompiler - clUnloadPlatformCompiler.restype = cl_int - clUnloadPlatformCompiler.argtypes = [cl_platform_id] -except AttributeError: - pass -try: - clGetProgramInfo = _libraries['libOpenCL.so.1'].clGetProgramInfo - clGetProgramInfo.restype = cl_int - clGetProgramInfo.argtypes = [cl_program, cl_program_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetProgramBuildInfo = _libraries['libOpenCL.so.1'].clGetProgramBuildInfo - clGetProgramBuildInfo.restype = cl_int - clGetProgramBuildInfo.argtypes = [cl_program, cl_device_id, cl_program_build_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateKernel = _libraries['libOpenCL.so.1'].clCreateKernel - clCreateKernel.restype = cl_kernel - clCreateKernel.argtypes = [cl_program, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateKernelsInProgram = _libraries['libOpenCL.so.1'].clCreateKernelsInProgram - clCreateKernelsInProgram.restype = cl_int - clCreateKernelsInProgram.argtypes = [cl_program, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_kernel)), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - clCloneKernel = _libraries['libOpenCL.so.1'].clCloneKernel - clCloneKernel.restype = cl_kernel - clCloneKernel.argtypes = [cl_kernel, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainKernel = _libraries['libOpenCL.so.1'].clRetainKernel - clRetainKernel.restype = cl_int - clRetainKernel.argtypes = [cl_kernel] -except AttributeError: - pass -try: - clReleaseKernel = _libraries['libOpenCL.so.1'].clReleaseKernel - clReleaseKernel.restype = cl_int - clReleaseKernel.argtypes = [cl_kernel] -except AttributeError: - pass -try: - clSetKernelArg = _libraries['libOpenCL.so.1'].clSetKernelArg - clSetKernelArg.restype = cl_int - clSetKernelArg.argtypes = [cl_kernel, cl_uint, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSetKernelArgSVMPointer = _libraries['libOpenCL.so.1'].clSetKernelArgSVMPointer - clSetKernelArgSVMPointer.restype = cl_int - clSetKernelArgSVMPointer.argtypes = [cl_kernel, cl_uint, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clSetKernelExecInfo = _libraries['libOpenCL.so.1'].clSetKernelExecInfo - clSetKernelExecInfo.restype = cl_int - clSetKernelExecInfo.argtypes = [cl_kernel, cl_kernel_exec_info, size_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - clGetKernelInfo = _libraries['libOpenCL.so.1'].clGetKernelInfo - clGetKernelInfo.restype = cl_int - clGetKernelInfo.argtypes = [cl_kernel, cl_kernel_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetKernelArgInfo = _libraries['libOpenCL.so.1'].clGetKernelArgInfo - clGetKernelArgInfo.restype = cl_int - clGetKernelArgInfo.argtypes = [cl_kernel, cl_uint, cl_kernel_arg_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetKernelWorkGroupInfo = _libraries['libOpenCL.so.1'].clGetKernelWorkGroupInfo - clGetKernelWorkGroupInfo.restype = cl_int - clGetKernelWorkGroupInfo.argtypes = [cl_kernel, cl_device_id, cl_kernel_work_group_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clGetKernelSubGroupInfo = _libraries['libOpenCL.so.1'].clGetKernelSubGroupInfo - clGetKernelSubGroupInfo.restype = cl_int - clGetKernelSubGroupInfo.argtypes = [cl_kernel, cl_device_id, cl_kernel_sub_group_info, size_t, ctypes.POINTER(None), size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clWaitForEvents = _libraries['libOpenCL.so.1'].clWaitForEvents - clWaitForEvents.restype = cl_int - clWaitForEvents.argtypes = [cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clGetEventInfo = _libraries['libOpenCL.so.1'].clGetEventInfo - clGetEventInfo.restype = cl_int - clGetEventInfo.argtypes = [cl_event, cl_event_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clCreateUserEvent = _libraries['libOpenCL.so.1'].clCreateUserEvent - clCreateUserEvent.restype = cl_event - clCreateUserEvent.argtypes = [cl_context, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clRetainEvent = _libraries['libOpenCL.so.1'].clRetainEvent - clRetainEvent.restype = cl_int - clRetainEvent.argtypes = [cl_event] -except AttributeError: - pass -try: - clReleaseEvent = _libraries['libOpenCL.so.1'].clReleaseEvent - clReleaseEvent.restype = cl_int - clReleaseEvent.argtypes = [cl_event] -except AttributeError: - pass -try: - clSetUserEventStatus = _libraries['libOpenCL.so.1'].clSetUserEventStatus - clSetUserEventStatus.restype = cl_int - clSetUserEventStatus.argtypes = [cl_event, cl_int] -except AttributeError: - pass -try: - clSetEventCallback = _libraries['libOpenCL.so.1'].clSetEventCallback - clSetEventCallback.restype = cl_int - clSetEventCallback.argtypes = [cl_event, cl_int, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_event), ctypes.c_int32, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - clGetEventProfilingInfo = _libraries['libOpenCL.so.1'].clGetEventProfilingInfo - clGetEventProfilingInfo.restype = cl_int - clGetEventProfilingInfo.argtypes = [cl_event, cl_profiling_info, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - clFlush = _libraries['libOpenCL.so.1'].clFlush - clFlush.restype = cl_int - clFlush.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clFinish = _libraries['libOpenCL.so.1'].clFinish - clFinish.restype = cl_int - clFinish.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clEnqueueReadBuffer = _libraries['libOpenCL.so.1'].clEnqueueReadBuffer - clEnqueueReadBuffer.restype = cl_int - clEnqueueReadBuffer.argtypes = [cl_command_queue, cl_mem, cl_bool, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueReadBufferRect = _libraries['libOpenCL.so.1'].clEnqueueReadBufferRect - clEnqueueReadBufferRect.restype = cl_int - clEnqueueReadBufferRect.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWriteBuffer = _libraries['libOpenCL.so.1'].clEnqueueWriteBuffer - clEnqueueWriteBuffer.restype = cl_int - clEnqueueWriteBuffer.argtypes = [cl_command_queue, cl_mem, cl_bool, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWriteBufferRect = _libraries['libOpenCL.so.1'].clEnqueueWriteBufferRect - clEnqueueWriteBufferRect.restype = cl_int - clEnqueueWriteBufferRect.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueFillBuffer = _libraries['libOpenCL.so.1'].clEnqueueFillBuffer - clEnqueueFillBuffer.restype = cl_int - clEnqueueFillBuffer.argtypes = [cl_command_queue, cl_mem, ctypes.POINTER(None), size_t, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyBuffer = _libraries['libOpenCL.so.1'].clEnqueueCopyBuffer - clEnqueueCopyBuffer.restype = cl_int - clEnqueueCopyBuffer.argtypes = [cl_command_queue, cl_mem, cl_mem, size_t, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyBufferRect = _libraries['libOpenCL.so.1'].clEnqueueCopyBufferRect - clEnqueueCopyBufferRect.restype = cl_int - clEnqueueCopyBufferRect.argtypes = [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueReadImage = _libraries['libOpenCL.so.1'].clEnqueueReadImage - clEnqueueReadImage.restype = cl_int - clEnqueueReadImage.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWriteImage = _libraries['libOpenCL.so.1'].clEnqueueWriteImage - clEnqueueWriteImage.restype = cl_int - clEnqueueWriteImage.argtypes = [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, size_t, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueFillImage = _libraries['libOpenCL.so.1'].clEnqueueFillImage - clEnqueueFillImage.restype = cl_int - clEnqueueFillImage.argtypes = [cl_command_queue, cl_mem, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyImage = _libraries['libOpenCL.so.1'].clEnqueueCopyImage - clEnqueueCopyImage.restype = cl_int - clEnqueueCopyImage.argtypes = [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyImageToBuffer = _libraries['libOpenCL.so.1'].clEnqueueCopyImageToBuffer - clEnqueueCopyImageToBuffer.restype = cl_int - clEnqueueCopyImageToBuffer.argtypes = [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueCopyBufferToImage = _libraries['libOpenCL.so.1'].clEnqueueCopyBufferToImage - clEnqueueCopyBufferToImage.restype = cl_int - clEnqueueCopyBufferToImage.argtypes = [cl_command_queue, cl_mem, cl_mem, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueMapBuffer = _libraries['libOpenCL.so.1'].clEnqueueMapBuffer - clEnqueueMapBuffer.restype = ctypes.POINTER(None) - clEnqueueMapBuffer.argtypes = [cl_command_queue, cl_mem, cl_bool, cl_map_flags, size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueMapImage = _libraries['libOpenCL.so.1'].clEnqueueMapImage - clEnqueueMapImage.restype = ctypes.POINTER(None) - clEnqueueMapImage.argtypes = [cl_command_queue, cl_mem, cl_bool, cl_map_flags, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueUnmapMemObject = _libraries['libOpenCL.so.1'].clEnqueueUnmapMemObject - clEnqueueUnmapMemObject.restype = cl_int - clEnqueueUnmapMemObject.argtypes = [cl_command_queue, cl_mem, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueMigrateMemObjects = _libraries['libOpenCL.so.1'].clEnqueueMigrateMemObjects - clEnqueueMigrateMemObjects.restype = cl_int - clEnqueueMigrateMemObjects.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_mem)), cl_mem_migration_flags, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueNDRangeKernel = _libraries['libOpenCL.so.1'].clEnqueueNDRangeKernel - clEnqueueNDRangeKernel.restype = cl_int - clEnqueueNDRangeKernel.argtypes = [cl_command_queue, cl_kernel, cl_uint, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueNativeKernel = _libraries['libOpenCL.so.1'].clEnqueueNativeKernel - clEnqueueNativeKernel.restype = cl_int - clEnqueueNativeKernel.argtypes = [cl_command_queue, ctypes.CFUNCTYPE(None, ctypes.POINTER(None)), ctypes.POINTER(None), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_mem)), ctypes.POINTER(ctypes.POINTER(None)), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueMarkerWithWaitList = _libraries['libOpenCL.so.1'].clEnqueueMarkerWithWaitList - clEnqueueMarkerWithWaitList.restype = cl_int - clEnqueueMarkerWithWaitList.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueBarrierWithWaitList = _libraries['libOpenCL.so.1'].clEnqueueBarrierWithWaitList - clEnqueueBarrierWithWaitList.restype = cl_int - clEnqueueBarrierWithWaitList.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMFree = _libraries['libOpenCL.so.1'].clEnqueueSVMFree - clEnqueueSVMFree.restype = cl_int - clEnqueueSVMFree.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(None) * 0, ctypes.CFUNCTYPE(None, ctypes.POINTER(struct__cl_command_queue), ctypes.c_uint32, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(None)), ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMemcpy = _libraries['libOpenCL.so.1'].clEnqueueSVMMemcpy - clEnqueueSVMMemcpy.restype = cl_int - clEnqueueSVMMemcpy.argtypes = [cl_command_queue, cl_bool, ctypes.POINTER(None), ctypes.POINTER(None), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMemFill = _libraries['libOpenCL.so.1'].clEnqueueSVMMemFill - clEnqueueSVMMemFill.restype = cl_int - clEnqueueSVMMemFill.argtypes = [cl_command_queue, ctypes.POINTER(None), ctypes.POINTER(None), size_t, size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMap = _libraries['libOpenCL.so.1'].clEnqueueSVMMap - clEnqueueSVMMap.restype = cl_int - clEnqueueSVMMap.argtypes = [cl_command_queue, cl_bool, cl_map_flags, ctypes.POINTER(None), size_t, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMUnmap = _libraries['libOpenCL.so.1'].clEnqueueSVMUnmap - clEnqueueSVMUnmap.restype = cl_int - clEnqueueSVMUnmap.argtypes = [cl_command_queue, ctypes.POINTER(None), cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueSVMMigrateMem = _libraries['libOpenCL.so.1'].clEnqueueSVMMigrateMem - clEnqueueSVMMigrateMem.restype = cl_int - clEnqueueSVMMigrateMem.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(None)), ctypes.POINTER(ctypes.c_uint64), cl_mem_migration_flags, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clGetExtensionFunctionAddressForPlatform = _libraries['libOpenCL.so.1'].clGetExtensionFunctionAddressForPlatform - clGetExtensionFunctionAddressForPlatform.restype = ctypes.POINTER(None) - clGetExtensionFunctionAddressForPlatform.argtypes = [cl_platform_id, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - clCreateImage2D = _libraries['libOpenCL.so.1'].clCreateImage2D - clCreateImage2D.restype = cl_mem - clCreateImage2D.argtypes = [cl_context, cl_mem_flags, ctypes.POINTER(struct__cl_image_format), size_t, size_t, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateImage3D = _libraries['libOpenCL.so.1'].clCreateImage3D - clCreateImage3D.restype = cl_mem - clCreateImage3D.argtypes = [cl_context, cl_mem_flags, ctypes.POINTER(struct__cl_image_format), size_t, size_t, size_t, size_t, size_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueMarker = _libraries['libOpenCL.so.1'].clEnqueueMarker - clEnqueueMarker.restype = cl_int - clEnqueueMarker.argtypes = [cl_command_queue, ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueWaitForEvents = _libraries['libOpenCL.so.1'].clEnqueueWaitForEvents - clEnqueueWaitForEvents.restype = cl_int - clEnqueueWaitForEvents.argtypes = [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -try: - clEnqueueBarrier = _libraries['libOpenCL.so.1'].clEnqueueBarrier - clEnqueueBarrier.restype = cl_int - clEnqueueBarrier.argtypes = [cl_command_queue] -except AttributeError: - pass -try: - clUnloadCompiler = _libraries['libOpenCL.so.1'].clUnloadCompiler - clUnloadCompiler.restype = cl_int - clUnloadCompiler.argtypes = [] -except AttributeError: - pass -try: - clGetExtensionFunctionAddress = _libraries['libOpenCL.so.1'].clGetExtensionFunctionAddress - clGetExtensionFunctionAddress.restype = ctypes.POINTER(None) - clGetExtensionFunctionAddress.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - clCreateCommandQueue = _libraries['libOpenCL.so.1'].clCreateCommandQueue - clCreateCommandQueue.restype = cl_command_queue - clCreateCommandQueue.argtypes = [cl_context, cl_device_id, cl_command_queue_properties, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clCreateSampler = _libraries['libOpenCL.so.1'].clCreateSampler - clCreateSampler.restype = cl_sampler - clCreateSampler.argtypes = [cl_context, cl_bool, cl_addressing_mode, cl_filter_mode, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - clEnqueueTask = _libraries['libOpenCL.so.1'].clEnqueueTask - clEnqueueTask.restype = cl_int - clEnqueueTask.argtypes = [cl_command_queue, cl_kernel, cl_uint, ctypes.POINTER(ctypes.POINTER(struct__cl_event)), ctypes.POINTER(ctypes.POINTER(struct__cl_event))] -except AttributeError: - pass -__all__ = \ - ['CL_A', 'CL_ABGR', 'CL_ADDRESS_CLAMP', - 'CL_ADDRESS_CLAMP_TO_EDGE', 'CL_ADDRESS_MIRRORED_REPEAT', - 'CL_ADDRESS_NONE', 'CL_ADDRESS_REPEAT', 'CL_ARGB', 'CL_BGRA', - 'CL_BLOCKING', 'CL_BUFFER_CREATE_TYPE_REGION', 'CL_BUILD_ERROR', - 'CL_BUILD_IN_PROGRESS', 'CL_BUILD_NONE', - 'CL_BUILD_PROGRAM_FAILURE', 'CL_BUILD_SUCCESS', - 'CL_COMMAND_ACQUIRE_GL_OBJECTS', 'CL_COMMAND_BARRIER', - 'CL_COMMAND_COPY_BUFFER', 'CL_COMMAND_COPY_BUFFER_RECT', - 'CL_COMMAND_COPY_BUFFER_TO_IMAGE', 'CL_COMMAND_COPY_IMAGE', - 'CL_COMMAND_COPY_IMAGE_TO_BUFFER', 'CL_COMMAND_FILL_BUFFER', - 'CL_COMMAND_FILL_IMAGE', 'CL_COMMAND_MAP_BUFFER', - 'CL_COMMAND_MAP_IMAGE', 'CL_COMMAND_MARKER', - 'CL_COMMAND_MIGRATE_MEM_OBJECTS', 'CL_COMMAND_NATIVE_KERNEL', - 'CL_COMMAND_NDRANGE_KERNEL', 'CL_COMMAND_READ_BUFFER', - 'CL_COMMAND_READ_BUFFER_RECT', 'CL_COMMAND_READ_IMAGE', - 'CL_COMMAND_RELEASE_GL_OBJECTS', 'CL_COMMAND_SVM_FREE', - 'CL_COMMAND_SVM_MAP', 'CL_COMMAND_SVM_MEMCPY', - 'CL_COMMAND_SVM_MEMFILL', 'CL_COMMAND_SVM_MIGRATE_MEM', - 'CL_COMMAND_SVM_UNMAP', 'CL_COMMAND_TASK', - 'CL_COMMAND_UNMAP_MEM_OBJECT', 'CL_COMMAND_USER', - 'CL_COMMAND_WRITE_BUFFER', 'CL_COMMAND_WRITE_BUFFER_RECT', - 'CL_COMMAND_WRITE_IMAGE', 'CL_COMPILER_NOT_AVAILABLE', - 'CL_COMPILE_PROGRAM_FAILURE', 'CL_COMPLETE', 'CL_CONTEXT_DEVICES', - 'CL_CONTEXT_INTEROP_USER_SYNC', 'CL_CONTEXT_NUM_DEVICES', - 'CL_CONTEXT_PLATFORM', 'CL_CONTEXT_PROPERTIES', - 'CL_CONTEXT_REFERENCE_COUNT', 'CL_DEPTH', - 'CL_DEVICE_ADDRESS_BITS', 'CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE', - 'CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE', - 'CL_DEVICE_AFFINITY_DOMAIN_NUMA', - 'CL_DEVICE_ATOMIC_FENCE_CAPABILITIES', - 'CL_DEVICE_ATOMIC_MEMORY_CAPABILITIES', - 'CL_DEVICE_ATOMIC_ORDER_ACQ_REL', - 'CL_DEVICE_ATOMIC_ORDER_RELAXED', - 'CL_DEVICE_ATOMIC_ORDER_SEQ_CST', - 'CL_DEVICE_ATOMIC_SCOPE_ALL_DEVICES', - 'CL_DEVICE_ATOMIC_SCOPE_DEVICE', - 'CL_DEVICE_ATOMIC_SCOPE_WORK_GROUP', - 'CL_DEVICE_ATOMIC_SCOPE_WORK_ITEM', 'CL_DEVICE_AVAILABLE', - 'CL_DEVICE_BUILT_IN_KERNELS', - 'CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION', - 'CL_DEVICE_COMPILER_AVAILABLE', - 'CL_DEVICE_DEVICE_ENQUEUE_CAPABILITIES', - 'CL_DEVICE_DOUBLE_FP_CONFIG', 'CL_DEVICE_ENDIAN_LITTLE', - 'CL_DEVICE_ERROR_CORRECTION_SUPPORT', - 'CL_DEVICE_EXECUTION_CAPABILITIES', 'CL_DEVICE_EXTENSIONS', - 'CL_DEVICE_EXTENSIONS_WITH_VERSION', - 'CL_DEVICE_GENERIC_ADDRESS_SPACE_SUPPORT', - 'CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE', - 'CL_DEVICE_GLOBAL_MEM_CACHE_SIZE', - 'CL_DEVICE_GLOBAL_MEM_CACHE_TYPE', 'CL_DEVICE_GLOBAL_MEM_SIZE', - 'CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE', - 'CL_DEVICE_HOST_UNIFIED_MEMORY', 'CL_DEVICE_ILS_WITH_VERSION', - 'CL_DEVICE_IL_VERSION', 'CL_DEVICE_IMAGE2D_MAX_HEIGHT', - 'CL_DEVICE_IMAGE2D_MAX_WIDTH', 'CL_DEVICE_IMAGE3D_MAX_DEPTH', - 'CL_DEVICE_IMAGE3D_MAX_HEIGHT', 'CL_DEVICE_IMAGE3D_MAX_WIDTH', - 'CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT', - 'CL_DEVICE_IMAGE_MAX_ARRAY_SIZE', - 'CL_DEVICE_IMAGE_MAX_BUFFER_SIZE', - 'CL_DEVICE_IMAGE_PITCH_ALIGNMENT', 'CL_DEVICE_IMAGE_SUPPORT', - 'CL_DEVICE_LATEST_CONFORMANCE_VERSION_PASSED', - 'CL_DEVICE_LINKER_AVAILABLE', 'CL_DEVICE_LOCAL_MEM_SIZE', - 'CL_DEVICE_LOCAL_MEM_TYPE', 'CL_DEVICE_MAX_CLOCK_FREQUENCY', - 'CL_DEVICE_MAX_COMPUTE_UNITS', 'CL_DEVICE_MAX_CONSTANT_ARGS', - 'CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE', - 'CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE', - 'CL_DEVICE_MAX_MEM_ALLOC_SIZE', 'CL_DEVICE_MAX_NUM_SUB_GROUPS', - 'CL_DEVICE_MAX_ON_DEVICE_EVENTS', - 'CL_DEVICE_MAX_ON_DEVICE_QUEUES', 'CL_DEVICE_MAX_PARAMETER_SIZE', - 'CL_DEVICE_MAX_PIPE_ARGS', 'CL_DEVICE_MAX_READ_IMAGE_ARGS', - 'CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS', 'CL_DEVICE_MAX_SAMPLERS', - 'CL_DEVICE_MAX_WORK_GROUP_SIZE', - 'CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS', - 'CL_DEVICE_MAX_WORK_ITEM_SIZES', 'CL_DEVICE_MAX_WRITE_IMAGE_ARGS', - 'CL_DEVICE_MEM_BASE_ADDR_ALIGN', - 'CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE', 'CL_DEVICE_NAME', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_INT', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG', - 'CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT', - 'CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT', - 'CL_DEVICE_NOT_AVAILABLE', 'CL_DEVICE_NOT_FOUND', - 'CL_DEVICE_NUMERIC_VERSION', 'CL_DEVICE_OPENCL_C_ALL_VERSIONS', - 'CL_DEVICE_OPENCL_C_FEATURES', 'CL_DEVICE_OPENCL_C_VERSION', - 'CL_DEVICE_PARENT_DEVICE', 'CL_DEVICE_PARTITION_AFFINITY_DOMAIN', - 'CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN', - 'CL_DEVICE_PARTITION_BY_COUNTS', - 'CL_DEVICE_PARTITION_BY_COUNTS_LIST_END', - 'CL_DEVICE_PARTITION_EQUALLY', 'CL_DEVICE_PARTITION_FAILED', - 'CL_DEVICE_PARTITION_MAX_SUB_DEVICES', - 'CL_DEVICE_PARTITION_PROPERTIES', 'CL_DEVICE_PARTITION_TYPE', - 'CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS', - 'CL_DEVICE_PIPE_MAX_PACKET_SIZE', 'CL_DEVICE_PIPE_SUPPORT', - 'CL_DEVICE_PLATFORM', - 'CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT', - 'CL_DEVICE_PREFERRED_INTEROP_USER_SYNC', - 'CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT', - 'CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG', - 'CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT', - 'CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_MULTIPLE', - 'CL_DEVICE_PRINTF_BUFFER_SIZE', 'CL_DEVICE_PROFILE', - 'CL_DEVICE_PROFILING_TIMER_RESOLUTION', - 'CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE', - 'CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE', - 'CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES', - 'CL_DEVICE_QUEUE_ON_HOST_PROPERTIES', - 'CL_DEVICE_QUEUE_PROPERTIES', - 'CL_DEVICE_QUEUE_REPLACEABLE_DEFAULT', - 'CL_DEVICE_QUEUE_SUPPORTED', 'CL_DEVICE_REFERENCE_COUNT', - 'CL_DEVICE_SINGLE_FP_CONFIG', - 'CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS', - 'CL_DEVICE_SVM_ATOMICS', 'CL_DEVICE_SVM_CAPABILITIES', - 'CL_DEVICE_SVM_COARSE_GRAIN_BUFFER', - 'CL_DEVICE_SVM_FINE_GRAIN_BUFFER', - 'CL_DEVICE_SVM_FINE_GRAIN_SYSTEM', 'CL_DEVICE_TYPE', - 'CL_DEVICE_TYPE_ACCELERATOR', 'CL_DEVICE_TYPE_ALL', - 'CL_DEVICE_TYPE_CPU', 'CL_DEVICE_TYPE_CUSTOM', - 'CL_DEVICE_TYPE_DEFAULT', 'CL_DEVICE_TYPE_GPU', - 'CL_DEVICE_VENDOR', 'CL_DEVICE_VENDOR_ID', 'CL_DEVICE_VERSION', - 'CL_DEVICE_WORK_GROUP_COLLECTIVE_FUNCTIONS_SUPPORT', - 'CL_DRIVER_VERSION', 'CL_EVENT_COMMAND_EXECUTION_STATUS', - 'CL_EVENT_COMMAND_QUEUE', 'CL_EVENT_COMMAND_TYPE', - 'CL_EVENT_CONTEXT', 'CL_EVENT_REFERENCE_COUNT', 'CL_EXEC_KERNEL', - 'CL_EXEC_NATIVE_KERNEL', - 'CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST', 'CL_FALSE', - 'CL_FILTER_LINEAR', 'CL_FILTER_NEAREST', 'CL_FLOAT', - 'CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT', 'CL_FP_DENORM', - 'CL_FP_FMA', 'CL_FP_INF_NAN', 'CL_FP_ROUND_TO_INF', - 'CL_FP_ROUND_TO_NEAREST', 'CL_FP_ROUND_TO_ZERO', - 'CL_FP_SOFT_FLOAT', 'CL_GLOBAL', 'CL_HALF_FLOAT', - 'CL_IMAGE_ARRAY_SIZE', 'CL_IMAGE_BUFFER', 'CL_IMAGE_DEPTH', - 'CL_IMAGE_ELEMENT_SIZE', 'CL_IMAGE_FORMAT', - 'CL_IMAGE_FORMAT_MISMATCH', 'CL_IMAGE_FORMAT_NOT_SUPPORTED', - 'CL_IMAGE_HEIGHT', 'CL_IMAGE_NUM_MIP_LEVELS', - 'CL_IMAGE_NUM_SAMPLES', 'CL_IMAGE_ROW_PITCH', - 'CL_IMAGE_SLICE_PITCH', 'CL_IMAGE_WIDTH', 'CL_INTENSITY', - 'CL_INVALID_ARG_INDEX', 'CL_INVALID_ARG_SIZE', - 'CL_INVALID_ARG_VALUE', 'CL_INVALID_BINARY', - 'CL_INVALID_BUFFER_SIZE', 'CL_INVALID_BUILD_OPTIONS', - 'CL_INVALID_COMMAND_QUEUE', 'CL_INVALID_COMPILER_OPTIONS', - 'CL_INVALID_CONTEXT', 'CL_INVALID_DEVICE', - 'CL_INVALID_DEVICE_PARTITION_COUNT', 'CL_INVALID_DEVICE_QUEUE', - 'CL_INVALID_DEVICE_TYPE', 'CL_INVALID_EVENT', - 'CL_INVALID_EVENT_WAIT_LIST', 'CL_INVALID_GLOBAL_OFFSET', - 'CL_INVALID_GLOBAL_WORK_SIZE', 'CL_INVALID_GL_OBJECT', - 'CL_INVALID_HOST_PTR', 'CL_INVALID_IMAGE_DESCRIPTOR', - 'CL_INVALID_IMAGE_FORMAT_DESCRIPTOR', 'CL_INVALID_IMAGE_SIZE', - 'CL_INVALID_KERNEL', 'CL_INVALID_KERNEL_ARGS', - 'CL_INVALID_KERNEL_DEFINITION', 'CL_INVALID_KERNEL_NAME', - 'CL_INVALID_LINKER_OPTIONS', 'CL_INVALID_MEM_OBJECT', - 'CL_INVALID_MIP_LEVEL', 'CL_INVALID_OPERATION', - 'CL_INVALID_PIPE_SIZE', 'CL_INVALID_PLATFORM', - 'CL_INVALID_PROGRAM', 'CL_INVALID_PROGRAM_EXECUTABLE', - 'CL_INVALID_PROPERTY', 'CL_INVALID_QUEUE_PROPERTIES', - 'CL_INVALID_SAMPLER', 'CL_INVALID_SPEC_ID', 'CL_INVALID_VALUE', - 'CL_INVALID_WORK_DIMENSION', 'CL_INVALID_WORK_GROUP_SIZE', - 'CL_INVALID_WORK_ITEM_SIZE', 'CL_KERNEL_ARG_ACCESS_NONE', - 'CL_KERNEL_ARG_ACCESS_QUALIFIER', - 'CL_KERNEL_ARG_ACCESS_READ_ONLY', - 'CL_KERNEL_ARG_ACCESS_READ_WRITE', - 'CL_KERNEL_ARG_ACCESS_WRITE_ONLY', - 'CL_KERNEL_ARG_ADDRESS_CONSTANT', 'CL_KERNEL_ARG_ADDRESS_GLOBAL', - 'CL_KERNEL_ARG_ADDRESS_LOCAL', 'CL_KERNEL_ARG_ADDRESS_PRIVATE', - 'CL_KERNEL_ARG_ADDRESS_QUALIFIER', - 'CL_KERNEL_ARG_INFO_NOT_AVAILABLE', 'CL_KERNEL_ARG_NAME', - 'CL_KERNEL_ARG_TYPE_CONST', 'CL_KERNEL_ARG_TYPE_NAME', - 'CL_KERNEL_ARG_TYPE_NONE', 'CL_KERNEL_ARG_TYPE_PIPE', - 'CL_KERNEL_ARG_TYPE_QUALIFIER', 'CL_KERNEL_ARG_TYPE_RESTRICT', - 'CL_KERNEL_ARG_TYPE_VOLATILE', 'CL_KERNEL_ATTRIBUTES', - 'CL_KERNEL_COMPILE_NUM_SUB_GROUPS', - 'CL_KERNEL_COMPILE_WORK_GROUP_SIZE', 'CL_KERNEL_CONTEXT', - 'CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM', - 'CL_KERNEL_EXEC_INFO_SVM_PTRS', 'CL_KERNEL_FUNCTION_NAME', - 'CL_KERNEL_GLOBAL_WORK_SIZE', 'CL_KERNEL_LOCAL_MEM_SIZE', - 'CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT', - 'CL_KERNEL_MAX_NUM_SUB_GROUPS', - 'CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE', 'CL_KERNEL_NUM_ARGS', - 'CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE', - 'CL_KERNEL_PRIVATE_MEM_SIZE', 'CL_KERNEL_PROGRAM', - 'CL_KERNEL_REFERENCE_COUNT', - 'CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE', - 'CL_KERNEL_WORK_GROUP_SIZE', 'CL_KHRONOS_VENDOR_ID_CODEPLAY', - 'CL_LINKER_NOT_AVAILABLE', 'CL_LINK_PROGRAM_FAILURE', 'CL_LOCAL', - 'CL_LUMINANCE', 'CL_MAP_FAILURE', 'CL_MAP_READ', 'CL_MAP_WRITE', - 'CL_MAP_WRITE_INVALIDATE_REGION', - 'CL_MAX_SIZE_RESTRICTION_EXCEEDED', 'CL_MEM_ALLOC_HOST_PTR', - 'CL_MEM_ASSOCIATED_MEMOBJECT', 'CL_MEM_CONTEXT', - 'CL_MEM_COPY_HOST_PTR', 'CL_MEM_COPY_OVERLAP', 'CL_MEM_FLAGS', - 'CL_MEM_HOST_NO_ACCESS', 'CL_MEM_HOST_PTR', - 'CL_MEM_HOST_READ_ONLY', 'CL_MEM_HOST_WRITE_ONLY', - 'CL_MEM_KERNEL_READ_AND_WRITE', 'CL_MEM_MAP_COUNT', - 'CL_MEM_OBJECT_ALLOCATION_FAILURE', 'CL_MEM_OBJECT_BUFFER', - 'CL_MEM_OBJECT_IMAGE1D', 'CL_MEM_OBJECT_IMAGE1D_ARRAY', - 'CL_MEM_OBJECT_IMAGE1D_BUFFER', 'CL_MEM_OBJECT_IMAGE2D', - 'CL_MEM_OBJECT_IMAGE2D_ARRAY', 'CL_MEM_OBJECT_IMAGE3D', - 'CL_MEM_OBJECT_PIPE', 'CL_MEM_OFFSET', 'CL_MEM_PROPERTIES', - 'CL_MEM_READ_ONLY', 'CL_MEM_READ_WRITE', 'CL_MEM_REFERENCE_COUNT', - 'CL_MEM_SIZE', 'CL_MEM_SVM_ATOMICS', - 'CL_MEM_SVM_FINE_GRAIN_BUFFER', 'CL_MEM_TYPE', - 'CL_MEM_USES_SVM_POINTER', 'CL_MEM_USE_HOST_PTR', - 'CL_MEM_WRITE_ONLY', 'CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED', - 'CL_MIGRATE_MEM_OBJECT_HOST', 'CL_MISALIGNED_SUB_BUFFER_OFFSET', - 'CL_NAME_VERSION_MAX_NAME_SIZE', 'CL_NONE', 'CL_NON_BLOCKING', - 'CL_OUT_OF_HOST_MEMORY', 'CL_OUT_OF_RESOURCES', - 'CL_PIPE_MAX_PACKETS', 'CL_PIPE_PACKET_SIZE', - 'CL_PIPE_PROPERTIES', 'CL_PLATFORM_EXTENSIONS', - 'CL_PLATFORM_EXTENSIONS_WITH_VERSION', - 'CL_PLATFORM_HOST_TIMER_RESOLUTION', 'CL_PLATFORM_NAME', - 'CL_PLATFORM_NUMERIC_VERSION', 'CL_PLATFORM_PROFILE', - 'CL_PLATFORM_VENDOR', 'CL_PLATFORM_VERSION', - 'CL_PROFILING_COMMAND_COMPLETE', 'CL_PROFILING_COMMAND_END', - 'CL_PROFILING_COMMAND_QUEUED', 'CL_PROFILING_COMMAND_START', - 'CL_PROFILING_COMMAND_SUBMIT', 'CL_PROFILING_INFO_NOT_AVAILABLE', - 'CL_PROGRAM_BINARIES', 'CL_PROGRAM_BINARY_SIZES', - 'CL_PROGRAM_BINARY_TYPE', - 'CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT', - 'CL_PROGRAM_BINARY_TYPE_EXECUTABLE', - 'CL_PROGRAM_BINARY_TYPE_LIBRARY', 'CL_PROGRAM_BINARY_TYPE_NONE', - 'CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE', - 'CL_PROGRAM_BUILD_LOG', 'CL_PROGRAM_BUILD_OPTIONS', - 'CL_PROGRAM_BUILD_STATUS', 'CL_PROGRAM_CONTEXT', - 'CL_PROGRAM_DEVICES', 'CL_PROGRAM_IL', 'CL_PROGRAM_KERNEL_NAMES', - 'CL_PROGRAM_NUM_DEVICES', 'CL_PROGRAM_NUM_KERNELS', - 'CL_PROGRAM_REFERENCE_COUNT', - 'CL_PROGRAM_SCOPE_GLOBAL_CTORS_PRESENT', - 'CL_PROGRAM_SCOPE_GLOBAL_DTORS_PRESENT', 'CL_PROGRAM_SOURCE', - 'CL_QUEUED', 'CL_QUEUE_CONTEXT', 'CL_QUEUE_DEVICE', - 'CL_QUEUE_DEVICE_DEFAULT', 'CL_QUEUE_ON_DEVICE', - 'CL_QUEUE_ON_DEVICE_DEFAULT', - 'CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE', - 'CL_QUEUE_PROFILING_ENABLE', 'CL_QUEUE_PROPERTIES', - 'CL_QUEUE_PROPERTIES_ARRAY', 'CL_QUEUE_REFERENCE_COUNT', - 'CL_QUEUE_SIZE', 'CL_R', 'CL_RA', 'CL_READ_ONLY_CACHE', - 'CL_READ_WRITE_CACHE', 'CL_RG', 'CL_RGB', 'CL_RGBA', 'CL_RGBx', - 'CL_RGx', 'CL_RUNNING', 'CL_Rx', 'CL_SAMPLER_ADDRESSING_MODE', - 'CL_SAMPLER_CONTEXT', 'CL_SAMPLER_FILTER_MODE', - 'CL_SAMPLER_LOD_MAX', 'CL_SAMPLER_LOD_MIN', - 'CL_SAMPLER_MIP_FILTER_MODE', 'CL_SAMPLER_NORMALIZED_COORDS', - 'CL_SAMPLER_PROPERTIES', 'CL_SAMPLER_REFERENCE_COUNT', - 'CL_SIGNED_INT16', 'CL_SIGNED_INT32', 'CL_SIGNED_INT8', - 'CL_SNORM_INT16', 'CL_SNORM_INT8', 'CL_SUBMITTED', 'CL_SUCCESS', - 'CL_TRUE', 'CL_UNORM_INT16', 'CL_UNORM_INT8', - 'CL_UNORM_INT_101010', 'CL_UNORM_INT_101010_2', - 'CL_UNORM_SHORT_555', 'CL_UNORM_SHORT_565', 'CL_UNSIGNED_INT16', - 'CL_UNSIGNED_INT32', 'CL_UNSIGNED_INT8', 'CL_VERSION_MAJOR_BITS', - 'CL_VERSION_MAJOR_MASK', 'CL_VERSION_MINOR_BITS', - 'CL_VERSION_MINOR_MASK', 'CL_VERSION_PATCH_BITS', - 'CL_VERSION_PATCH_MASK', 'CL_sBGRA', 'CL_sRGB', 'CL_sRGBA', - 'CL_sRGBx', '__OPENCL_CL_H', 'clBuildProgram', 'clCloneKernel', - 'clCompileProgram', 'clCreateBuffer', - 'clCreateBufferWithProperties', 'clCreateCommandQueue', - 'clCreateCommandQueueWithProperties', 'clCreateContext', - 'clCreateContextFromType', 'clCreateImage', 'clCreateImage2D', - 'clCreateImage3D', 'clCreateImageWithProperties', - 'clCreateKernel', 'clCreateKernelsInProgram', 'clCreatePipe', - 'clCreateProgramWithBinary', 'clCreateProgramWithBuiltInKernels', - 'clCreateProgramWithIL', 'clCreateProgramWithSource', - 'clCreateSampler', 'clCreateSamplerWithProperties', - 'clCreateSubBuffer', 'clCreateSubDevices', 'clCreateUserEvent', - 'clEnqueueBarrier', 'clEnqueueBarrierWithWaitList', - 'clEnqueueCopyBuffer', 'clEnqueueCopyBufferRect', - 'clEnqueueCopyBufferToImage', 'clEnqueueCopyImage', - 'clEnqueueCopyImageToBuffer', 'clEnqueueFillBuffer', - 'clEnqueueFillImage', 'clEnqueueMapBuffer', 'clEnqueueMapImage', - 'clEnqueueMarker', 'clEnqueueMarkerWithWaitList', - 'clEnqueueMigrateMemObjects', 'clEnqueueNDRangeKernel', - 'clEnqueueNativeKernel', 'clEnqueueReadBuffer', - 'clEnqueueReadBufferRect', 'clEnqueueReadImage', - 'clEnqueueSVMFree', 'clEnqueueSVMMap', 'clEnqueueSVMMemFill', - 'clEnqueueSVMMemcpy', 'clEnqueueSVMMigrateMem', - 'clEnqueueSVMUnmap', 'clEnqueueTask', 'clEnqueueUnmapMemObject', - 'clEnqueueWaitForEvents', 'clEnqueueWriteBuffer', - 'clEnqueueWriteBufferRect', 'clEnqueueWriteImage', 'clFinish', - 'clFlush', 'clGetCommandQueueInfo', 'clGetContextInfo', - 'clGetDeviceAndHostTimer', 'clGetDeviceIDs', 'clGetDeviceInfo', - 'clGetEventInfo', 'clGetEventProfilingInfo', - 'clGetExtensionFunctionAddress', - 'clGetExtensionFunctionAddressForPlatform', 'clGetHostTimer', - 'clGetImageInfo', 'clGetKernelArgInfo', 'clGetKernelInfo', - 'clGetKernelSubGroupInfo', 'clGetKernelWorkGroupInfo', - 'clGetMemObjectInfo', 'clGetPipeInfo', 'clGetPlatformIDs', - 'clGetPlatformInfo', 'clGetProgramBuildInfo', 'clGetProgramInfo', - 'clGetSamplerInfo', 'clGetSupportedImageFormats', 'clLinkProgram', - 'clReleaseCommandQueue', 'clReleaseContext', 'clReleaseDevice', - 'clReleaseEvent', 'clReleaseKernel', 'clReleaseMemObject', - 'clReleaseProgram', 'clReleaseSampler', 'clRetainCommandQueue', - 'clRetainContext', 'clRetainDevice', 'clRetainEvent', - 'clRetainKernel', 'clRetainMemObject', 'clRetainProgram', - 'clRetainSampler', 'clSVMAlloc', 'clSVMFree', - 'clSetContextDestructorCallback', - 'clSetDefaultDeviceCommandQueue', 'clSetEventCallback', - 'clSetKernelArg', 'clSetKernelArgSVMPointer', - 'clSetKernelExecInfo', 'clSetMemObjectDestructorCallback', - 'clSetProgramReleaseCallback', - 'clSetProgramSpecializationConstant', 'clSetUserEventStatus', - 'clUnloadCompiler', 'clUnloadPlatformCompiler', 'clWaitForEvents', - 'cl_addressing_mode', 'cl_bitfield', 'cl_bool', - 'cl_buffer_create_type', 'cl_buffer_region', 'cl_build_status', - 'cl_channel_order', 'cl_channel_type', 'cl_command_queue', - 'cl_command_queue_info', 'cl_command_queue_properties', - 'cl_command_type', 'cl_context', 'cl_context_info', - 'cl_context_properties', 'cl_device_affinity_domain', - 'cl_device_atomic_capabilities', - 'cl_device_device_enqueue_capabilities', - 'cl_device_exec_capabilities', 'cl_device_fp_config', - 'cl_device_id', 'cl_device_info', 'cl_device_local_mem_type', - 'cl_device_mem_cache_type', 'cl_device_partition_property', - 'cl_device_svm_capabilities', 'cl_device_type', 'cl_event', - 'cl_event_info', 'cl_filter_mode', 'cl_image_desc', - 'cl_image_format', 'cl_image_info', 'cl_int', 'cl_kernel', - 'cl_kernel_arg_access_qualifier', - 'cl_kernel_arg_address_qualifier', 'cl_kernel_arg_info', - 'cl_kernel_arg_type_qualifier', 'cl_kernel_exec_info', - 'cl_kernel_info', 'cl_kernel_sub_group_info', - 'cl_kernel_work_group_info', 'cl_khronos_vendor_id', - 'cl_map_flags', 'cl_mem', 'cl_mem_flags', 'cl_mem_info', - 'cl_mem_migration_flags', 'cl_mem_object_type', - 'cl_mem_properties', 'cl_name_version', 'cl_pipe_info', - 'cl_pipe_properties', 'cl_platform_id', 'cl_platform_info', - 'cl_profiling_info', 'cl_program', 'cl_program_binary_type', - 'cl_program_build_info', 'cl_program_info', 'cl_properties', - 'cl_queue_properties', 'cl_sampler', 'cl_sampler_info', - 'cl_sampler_properties', 'cl_svm_mem_flags', 'cl_uint', - 'cl_version', 'size_t', 'struct__cl_buffer_region', - 'struct__cl_command_queue', 'struct__cl_context', - 'struct__cl_device_id', 'struct__cl_event', - 'struct__cl_image_desc', 'struct__cl_image_format', - 'struct__cl_kernel', 'struct__cl_mem', 'struct__cl_name_version', - 'struct__cl_platform_id', 'struct__cl_program', - 'struct__cl_sampler', 'union__cl_image_desc_0'] +# extern cl_int clGetPlatformIDs(cl_uint num_entries, cl_platform_id *platforms, cl_uint *num_platforms) +try: (clGetPlatformIDs:=dll.clGetPlatformIDs).restype, clGetPlatformIDs.argtypes = cl_int, [cl_uint, ctypes.POINTER(cl_platform_id), ctypes.POINTER(cl_uint)] +except AttributeError: pass + +# extern cl_int clGetPlatformInfo(cl_platform_id platform, cl_platform_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetPlatformInfo:=dll.clGetPlatformInfo).restype, clGetPlatformInfo.argtypes = cl_int, [cl_platform_id, cl_platform_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetDeviceIDs(cl_platform_id platform, cl_device_type device_type, cl_uint num_entries, cl_device_id *devices, cl_uint *num_devices) +try: (clGetDeviceIDs:=dll.clGetDeviceIDs).restype, clGetDeviceIDs.argtypes = cl_int, [cl_platform_id, cl_device_type, cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(cl_uint)] +except AttributeError: pass + +# extern cl_int clGetDeviceInfo(cl_device_id device, cl_device_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetDeviceInfo:=dll.clGetDeviceInfo).restype, clGetDeviceInfo.argtypes = cl_int, [cl_device_id, cl_device_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clCreateSubDevices(cl_device_id in_device, const cl_device_partition_property *properties, cl_uint num_devices, cl_device_id *out_devices, cl_uint *num_devices_ret) +try: (clCreateSubDevices:=dll.clCreateSubDevices).restype, clCreateSubDevices.argtypes = cl_int, [cl_device_id, ctypes.POINTER(cl_device_partition_property), cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(cl_uint)] +except AttributeError: pass + +# extern cl_int clRetainDevice(cl_device_id device) +try: (clRetainDevice:=dll.clRetainDevice).restype, clRetainDevice.argtypes = cl_int, [cl_device_id] +except AttributeError: pass + +# extern cl_int clReleaseDevice(cl_device_id device) +try: (clReleaseDevice:=dll.clReleaseDevice).restype, clReleaseDevice.argtypes = cl_int, [cl_device_id] +except AttributeError: pass + +# extern cl_int clSetDefaultDeviceCommandQueue(cl_context context, cl_device_id device, cl_command_queue command_queue) +try: (clSetDefaultDeviceCommandQueue:=dll.clSetDefaultDeviceCommandQueue).restype, clSetDefaultDeviceCommandQueue.argtypes = cl_int, [cl_context, cl_device_id, cl_command_queue] +except AttributeError: pass + +cl_ulong = ctypes.c_uint64 +# extern cl_int clGetDeviceAndHostTimer(cl_device_id device, cl_ulong *device_timestamp, cl_ulong *host_timestamp) +try: (clGetDeviceAndHostTimer:=dll.clGetDeviceAndHostTimer).restype, clGetDeviceAndHostTimer.argtypes = cl_int, [cl_device_id, ctypes.POINTER(cl_ulong), ctypes.POINTER(cl_ulong)] +except AttributeError: pass + +# extern cl_int clGetHostTimer(cl_device_id device, cl_ulong *host_timestamp) +try: (clGetHostTimer:=dll.clGetHostTimer).restype, clGetHostTimer.argtypes = cl_int, [cl_device_id, ctypes.POINTER(cl_ulong)] +except AttributeError: pass + +# extern cl_context clCreateContext(const cl_context_properties *properties, cl_uint num_devices, const cl_device_id *devices, void (*pfn_notify)(const char *, const void *, size_t, void *), void *user_data, cl_int *errcode_ret) +try: (clCreateContext:=dll.clCreateContext).restype, clCreateContext.argtypes = cl_context, [ctypes.POINTER(cl_context_properties), cl_uint, ctypes.POINTER(cl_device_id), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, size_t, ctypes.c_void_p), ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_context clCreateContextFromType(const cl_context_properties *properties, cl_device_type device_type, void (*pfn_notify)(const char *, const void *, size_t, void *), void *user_data, cl_int *errcode_ret) +try: (clCreateContextFromType:=dll.clCreateContextFromType).restype, clCreateContextFromType.argtypes = cl_context, [ctypes.POINTER(cl_context_properties), cl_device_type, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.c_void_p, size_t, ctypes.c_void_p), ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainContext(cl_context context) +try: (clRetainContext:=dll.clRetainContext).restype, clRetainContext.argtypes = cl_int, [cl_context] +except AttributeError: pass + +# extern cl_int clReleaseContext(cl_context context) +try: (clReleaseContext:=dll.clReleaseContext).restype, clReleaseContext.argtypes = cl_int, [cl_context] +except AttributeError: pass + +# extern cl_int clGetContextInfo(cl_context context, cl_context_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetContextInfo:=dll.clGetContextInfo).restype, clGetContextInfo.argtypes = cl_int, [cl_context, cl_context_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clSetContextDestructorCallback(cl_context context, void (*pfn_notify)(cl_context, void *), void *user_data) +try: (clSetContextDestructorCallback:=dll.clSetContextDestructorCallback).restype, clSetContextDestructorCallback.argtypes = cl_int, [cl_context, ctypes.CFUNCTYPE(None, cl_context, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# extern cl_command_queue clCreateCommandQueueWithProperties(cl_context context, cl_device_id device, const cl_queue_properties *properties, cl_int *errcode_ret) +try: (clCreateCommandQueueWithProperties:=dll.clCreateCommandQueueWithProperties).restype, clCreateCommandQueueWithProperties.argtypes = cl_command_queue, [cl_context, cl_device_id, ctypes.POINTER(cl_queue_properties), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainCommandQueue(cl_command_queue command_queue) +try: (clRetainCommandQueue:=dll.clRetainCommandQueue).restype, clRetainCommandQueue.argtypes = cl_int, [cl_command_queue] +except AttributeError: pass + +# extern cl_int clReleaseCommandQueue(cl_command_queue command_queue) +try: (clReleaseCommandQueue:=dll.clReleaseCommandQueue).restype, clReleaseCommandQueue.argtypes = cl_int, [cl_command_queue] +except AttributeError: pass + +# extern cl_int clGetCommandQueueInfo(cl_command_queue command_queue, cl_command_queue_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetCommandQueueInfo:=dll.clGetCommandQueueInfo).restype, clGetCommandQueueInfo.argtypes = cl_int, [cl_command_queue, cl_command_queue_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_mem clCreateBuffer(cl_context context, cl_mem_flags flags, size_t size, void *host_ptr, cl_int *errcode_ret) +try: (clCreateBuffer:=dll.clCreateBuffer).restype, clCreateBuffer.argtypes = cl_mem, [cl_context, cl_mem_flags, size_t, ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_mem clCreateSubBuffer(cl_mem buffer, cl_mem_flags flags, cl_buffer_create_type buffer_create_type, const void *buffer_create_info, cl_int *errcode_ret) +try: (clCreateSubBuffer:=dll.clCreateSubBuffer).restype, clCreateSubBuffer.argtypes = cl_mem, [cl_mem, cl_mem_flags, cl_buffer_create_type, ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_mem clCreateImage(cl_context context, cl_mem_flags flags, const cl_image_format *image_format, const cl_image_desc *image_desc, void *host_ptr, cl_int *errcode_ret) +try: (clCreateImage:=dll.clCreateImage).restype, clCreateImage.argtypes = cl_mem, [cl_context, cl_mem_flags, ctypes.POINTER(cl_image_format), ctypes.POINTER(cl_image_desc), ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_mem clCreatePipe(cl_context context, cl_mem_flags flags, cl_uint pipe_packet_size, cl_uint pipe_max_packets, const cl_pipe_properties *properties, cl_int *errcode_ret) +try: (clCreatePipe:=dll.clCreatePipe).restype, clCreatePipe.argtypes = cl_mem, [cl_context, cl_mem_flags, cl_uint, cl_uint, ctypes.POINTER(cl_pipe_properties), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_mem clCreateBufferWithProperties(cl_context context, const cl_mem_properties *properties, cl_mem_flags flags, size_t size, void *host_ptr, cl_int *errcode_ret) +try: (clCreateBufferWithProperties:=dll.clCreateBufferWithProperties).restype, clCreateBufferWithProperties.argtypes = cl_mem, [cl_context, ctypes.POINTER(cl_mem_properties), cl_mem_flags, size_t, ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_mem clCreateImageWithProperties(cl_context context, const cl_mem_properties *properties, cl_mem_flags flags, const cl_image_format *image_format, const cl_image_desc *image_desc, void *host_ptr, cl_int *errcode_ret) +try: (clCreateImageWithProperties:=dll.clCreateImageWithProperties).restype, clCreateImageWithProperties.argtypes = cl_mem, [cl_context, ctypes.POINTER(cl_mem_properties), cl_mem_flags, ctypes.POINTER(cl_image_format), ctypes.POINTER(cl_image_desc), ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainMemObject(cl_mem memobj) +try: (clRetainMemObject:=dll.clRetainMemObject).restype, clRetainMemObject.argtypes = cl_int, [cl_mem] +except AttributeError: pass + +# extern cl_int clReleaseMemObject(cl_mem memobj) +try: (clReleaseMemObject:=dll.clReleaseMemObject).restype, clReleaseMemObject.argtypes = cl_int, [cl_mem] +except AttributeError: pass + +# extern cl_int clGetSupportedImageFormats(cl_context context, cl_mem_flags flags, cl_mem_object_type image_type, cl_uint num_entries, cl_image_format *image_formats, cl_uint *num_image_formats) +try: (clGetSupportedImageFormats:=dll.clGetSupportedImageFormats).restype, clGetSupportedImageFormats.argtypes = cl_int, [cl_context, cl_mem_flags, cl_mem_object_type, cl_uint, ctypes.POINTER(cl_image_format), ctypes.POINTER(cl_uint)] +except AttributeError: pass + +# extern cl_int clGetMemObjectInfo(cl_mem memobj, cl_mem_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetMemObjectInfo:=dll.clGetMemObjectInfo).restype, clGetMemObjectInfo.argtypes = cl_int, [cl_mem, cl_mem_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetImageInfo(cl_mem image, cl_image_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetImageInfo:=dll.clGetImageInfo).restype, clGetImageInfo.argtypes = cl_int, [cl_mem, cl_image_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetPipeInfo(cl_mem pipe, cl_pipe_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetPipeInfo:=dll.clGetPipeInfo).restype, clGetPipeInfo.argtypes = cl_int, [cl_mem, cl_pipe_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clSetMemObjectDestructorCallback(cl_mem memobj, void (*pfn_notify)(cl_mem, void *), void *user_data) +try: (clSetMemObjectDestructorCallback:=dll.clSetMemObjectDestructorCallback).restype, clSetMemObjectDestructorCallback.argtypes = cl_int, [cl_mem, ctypes.CFUNCTYPE(None, cl_mem, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# extern void *clSVMAlloc(cl_context context, cl_svm_mem_flags flags, size_t size, cl_uint alignment) +try: (clSVMAlloc:=dll.clSVMAlloc).restype, clSVMAlloc.argtypes = ctypes.c_void_p, [cl_context, cl_svm_mem_flags, size_t, cl_uint] +except AttributeError: pass + +# extern void clSVMFree(cl_context context, void *svm_pointer) +try: (clSVMFree:=dll.clSVMFree).restype, clSVMFree.argtypes = None, [cl_context, ctypes.c_void_p] +except AttributeError: pass + +# extern cl_sampler clCreateSamplerWithProperties(cl_context context, const cl_sampler_properties *sampler_properties, cl_int *errcode_ret) +try: (clCreateSamplerWithProperties:=dll.clCreateSamplerWithProperties).restype, clCreateSamplerWithProperties.argtypes = cl_sampler, [cl_context, ctypes.POINTER(cl_sampler_properties), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainSampler(cl_sampler sampler) +try: (clRetainSampler:=dll.clRetainSampler).restype, clRetainSampler.argtypes = cl_int, [cl_sampler] +except AttributeError: pass + +# extern cl_int clReleaseSampler(cl_sampler sampler) +try: (clReleaseSampler:=dll.clReleaseSampler).restype, clReleaseSampler.argtypes = cl_int, [cl_sampler] +except AttributeError: pass + +# extern cl_int clGetSamplerInfo(cl_sampler sampler, cl_sampler_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetSamplerInfo:=dll.clGetSamplerInfo).restype, clGetSamplerInfo.argtypes = cl_int, [cl_sampler, cl_sampler_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_program clCreateProgramWithSource(cl_context context, cl_uint count, const char **strings, const size_t *lengths, cl_int *errcode_ret) +try: (clCreateProgramWithSource:=dll.clCreateProgramWithSource).restype, clCreateProgramWithSource.argtypes = cl_program, [cl_context, cl_uint, ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.POINTER(size_t), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_program clCreateProgramWithBinary(cl_context context, cl_uint num_devices, const cl_device_id *device_list, const size_t *lengths, const unsigned char **binaries, cl_int *binary_status, cl_int *errcode_ret) +try: (clCreateProgramWithBinary:=dll.clCreateProgramWithBinary).restype, clCreateProgramWithBinary.argtypes = cl_program, [cl_context, cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(size_t), ctypes.POINTER(ctypes.POINTER(ctypes.c_ubyte)), ctypes.POINTER(cl_int), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_program clCreateProgramWithBuiltInKernels(cl_context context, cl_uint num_devices, const cl_device_id *device_list, const char *kernel_names, cl_int *errcode_ret) +try: (clCreateProgramWithBuiltInKernels:=dll.clCreateProgramWithBuiltInKernels).restype, clCreateProgramWithBuiltInKernels.argtypes = cl_program, [cl_context, cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_program clCreateProgramWithIL(cl_context context, const void *il, size_t length, cl_int *errcode_ret) +try: (clCreateProgramWithIL:=dll.clCreateProgramWithIL).restype, clCreateProgramWithIL.argtypes = cl_program, [cl_context, ctypes.c_void_p, size_t, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainProgram(cl_program program) +try: (clRetainProgram:=dll.clRetainProgram).restype, clRetainProgram.argtypes = cl_int, [cl_program] +except AttributeError: pass + +# extern cl_int clReleaseProgram(cl_program program) +try: (clReleaseProgram:=dll.clReleaseProgram).restype, clReleaseProgram.argtypes = cl_int, [cl_program] +except AttributeError: pass + +# extern cl_int clBuildProgram(cl_program program, cl_uint num_devices, const cl_device_id *device_list, const char *options, void (*pfn_notify)(cl_program, void *), void *user_data) +try: (clBuildProgram:=dll.clBuildProgram).restype, clBuildProgram.argtypes = cl_int, [cl_program, cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(None, cl_program, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clCompileProgram(cl_program program, cl_uint num_devices, const cl_device_id *device_list, const char *options, cl_uint num_input_headers, const cl_program *input_headers, const char **header_include_names, void (*pfn_notify)(cl_program, void *), void *user_data) +try: (clCompileProgram:=dll.clCompileProgram).restype, clCompileProgram.argtypes = cl_int, [cl_program, cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(ctypes.c_char), cl_uint, ctypes.POINTER(cl_program), ctypes.POINTER(ctypes.POINTER(ctypes.c_char)), ctypes.CFUNCTYPE(None, cl_program, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# extern cl_program clLinkProgram(cl_context context, cl_uint num_devices, const cl_device_id *device_list, const char *options, cl_uint num_input_programs, const cl_program *input_programs, void (*pfn_notify)(cl_program, void *), void *user_data, cl_int *errcode_ret) +try: (clLinkProgram:=dll.clLinkProgram).restype, clLinkProgram.argtypes = cl_program, [cl_context, cl_uint, ctypes.POINTER(cl_device_id), ctypes.POINTER(ctypes.c_char), cl_uint, ctypes.POINTER(cl_program), ctypes.CFUNCTYPE(None, cl_program, ctypes.c_void_p), ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clSetProgramReleaseCallback(cl_program program, void (*pfn_notify)(cl_program, void *), void *user_data) __attribute__((deprecated(""))) +try: (clSetProgramReleaseCallback:=dll.clSetProgramReleaseCallback).restype, clSetProgramReleaseCallback.argtypes = cl_int, [cl_program, ctypes.CFUNCTYPE(None, cl_program, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clSetProgramSpecializationConstant(cl_program program, cl_uint spec_id, size_t spec_size, const void *spec_value) +try: (clSetProgramSpecializationConstant:=dll.clSetProgramSpecializationConstant).restype, clSetProgramSpecializationConstant.argtypes = cl_int, [cl_program, cl_uint, size_t, ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clUnloadPlatformCompiler(cl_platform_id platform) +try: (clUnloadPlatformCompiler:=dll.clUnloadPlatformCompiler).restype, clUnloadPlatformCompiler.argtypes = cl_int, [cl_platform_id] +except AttributeError: pass + +# extern cl_int clGetProgramInfo(cl_program program, cl_program_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetProgramInfo:=dll.clGetProgramInfo).restype, clGetProgramInfo.argtypes = cl_int, [cl_program, cl_program_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetProgramBuildInfo(cl_program program, cl_device_id device, cl_program_build_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetProgramBuildInfo:=dll.clGetProgramBuildInfo).restype, clGetProgramBuildInfo.argtypes = cl_int, [cl_program, cl_device_id, cl_program_build_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_kernel clCreateKernel(cl_program program, const char *kernel_name, cl_int *errcode_ret) +try: (clCreateKernel:=dll.clCreateKernel).restype, clCreateKernel.argtypes = cl_kernel, [cl_program, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clCreateKernelsInProgram(cl_program program, cl_uint num_kernels, cl_kernel *kernels, cl_uint *num_kernels_ret) +try: (clCreateKernelsInProgram:=dll.clCreateKernelsInProgram).restype, clCreateKernelsInProgram.argtypes = cl_int, [cl_program, cl_uint, ctypes.POINTER(cl_kernel), ctypes.POINTER(cl_uint)] +except AttributeError: pass + +# extern cl_kernel clCloneKernel(cl_kernel source_kernel, cl_int *errcode_ret) +try: (clCloneKernel:=dll.clCloneKernel).restype, clCloneKernel.argtypes = cl_kernel, [cl_kernel, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainKernel(cl_kernel kernel) +try: (clRetainKernel:=dll.clRetainKernel).restype, clRetainKernel.argtypes = cl_int, [cl_kernel] +except AttributeError: pass + +# extern cl_int clReleaseKernel(cl_kernel kernel) +try: (clReleaseKernel:=dll.clReleaseKernel).restype, clReleaseKernel.argtypes = cl_int, [cl_kernel] +except AttributeError: pass + +# extern cl_int clSetKernelArg(cl_kernel kernel, cl_uint arg_index, size_t arg_size, const void *arg_value) +try: (clSetKernelArg:=dll.clSetKernelArg).restype, clSetKernelArg.argtypes = cl_int, [cl_kernel, cl_uint, size_t, ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clSetKernelArgSVMPointer(cl_kernel kernel, cl_uint arg_index, const void *arg_value) +try: (clSetKernelArgSVMPointer:=dll.clSetKernelArgSVMPointer).restype, clSetKernelArgSVMPointer.argtypes = cl_int, [cl_kernel, cl_uint, ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clSetKernelExecInfo(cl_kernel kernel, cl_kernel_exec_info param_name, size_t param_value_size, const void *param_value) +try: (clSetKernelExecInfo:=dll.clSetKernelExecInfo).restype, clSetKernelExecInfo.argtypes = cl_int, [cl_kernel, cl_kernel_exec_info, size_t, ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clGetKernelInfo(cl_kernel kernel, cl_kernel_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetKernelInfo:=dll.clGetKernelInfo).restype, clGetKernelInfo.argtypes = cl_int, [cl_kernel, cl_kernel_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetKernelArgInfo(cl_kernel kernel, cl_uint arg_indx, cl_kernel_arg_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetKernelArgInfo:=dll.clGetKernelArgInfo).restype, clGetKernelArgInfo.argtypes = cl_int, [cl_kernel, cl_uint, cl_kernel_arg_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetKernelWorkGroupInfo(cl_kernel kernel, cl_device_id device, cl_kernel_work_group_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetKernelWorkGroupInfo:=dll.clGetKernelWorkGroupInfo).restype, clGetKernelWorkGroupInfo.argtypes = cl_int, [cl_kernel, cl_device_id, cl_kernel_work_group_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clGetKernelSubGroupInfo(cl_kernel kernel, cl_device_id device, cl_kernel_sub_group_info param_name, size_t input_value_size, const void *input_value, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetKernelSubGroupInfo:=dll.clGetKernelSubGroupInfo).restype, clGetKernelSubGroupInfo.argtypes = cl_int, [cl_kernel, cl_device_id, cl_kernel_sub_group_info, size_t, ctypes.c_void_p, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clWaitForEvents(cl_uint num_events, const cl_event *event_list) +try: (clWaitForEvents:=dll.clWaitForEvents).restype, clWaitForEvents.argtypes = cl_int, [cl_uint, ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clGetEventInfo(cl_event event, cl_event_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetEventInfo:=dll.clGetEventInfo).restype, clGetEventInfo.argtypes = cl_int, [cl_event, cl_event_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_event clCreateUserEvent(cl_context context, cl_int *errcode_ret) +try: (clCreateUserEvent:=dll.clCreateUserEvent).restype, clCreateUserEvent.argtypes = cl_event, [cl_context, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clRetainEvent(cl_event event) +try: (clRetainEvent:=dll.clRetainEvent).restype, clRetainEvent.argtypes = cl_int, [cl_event] +except AttributeError: pass + +# extern cl_int clReleaseEvent(cl_event event) +try: (clReleaseEvent:=dll.clReleaseEvent).restype, clReleaseEvent.argtypes = cl_int, [cl_event] +except AttributeError: pass + +# extern cl_int clSetUserEventStatus(cl_event event, cl_int execution_status) +try: (clSetUserEventStatus:=dll.clSetUserEventStatus).restype, clSetUserEventStatus.argtypes = cl_int, [cl_event, cl_int] +except AttributeError: pass + +# extern cl_int clSetEventCallback(cl_event event, cl_int command_exec_callback_type, void (*pfn_notify)(cl_event, cl_int, void *), void *user_data) +try: (clSetEventCallback:=dll.clSetEventCallback).restype, clSetEventCallback.argtypes = cl_int, [cl_event, cl_int, ctypes.CFUNCTYPE(None, cl_event, cl_int, ctypes.c_void_p), ctypes.c_void_p] +except AttributeError: pass + +# extern cl_int clGetEventProfilingInfo(cl_event event, cl_profiling_info param_name, size_t param_value_size, void *param_value, size_t *param_value_size_ret) +try: (clGetEventProfilingInfo:=dll.clGetEventProfilingInfo).restype, clGetEventProfilingInfo.argtypes = cl_int, [cl_event, cl_profiling_info, size_t, ctypes.c_void_p, ctypes.POINTER(size_t)] +except AttributeError: pass + +# extern cl_int clFlush(cl_command_queue command_queue) +try: (clFlush:=dll.clFlush).restype, clFlush.argtypes = cl_int, [cl_command_queue] +except AttributeError: pass + +# extern cl_int clFinish(cl_command_queue command_queue) +try: (clFinish:=dll.clFinish).restype, clFinish.argtypes = cl_int, [cl_command_queue] +except AttributeError: pass + +# extern cl_int clEnqueueReadBuffer(cl_command_queue command_queue, cl_mem buffer, cl_bool blocking_read, size_t offset, size_t size, void *ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueReadBuffer:=dll.clEnqueueReadBuffer).restype, clEnqueueReadBuffer.argtypes = cl_int, [cl_command_queue, cl_mem, cl_bool, size_t, size_t, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueReadBufferRect(cl_command_queue command_queue, cl_mem buffer, cl_bool blocking_read, const size_t *buffer_origin, const size_t *host_origin, const size_t *region, size_t buffer_row_pitch, size_t buffer_slice_pitch, size_t host_row_pitch, size_t host_slice_pitch, void *ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueReadBufferRect:=dll.clEnqueueReadBufferRect).restype, clEnqueueReadBufferRect.argtypes = cl_int, [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), size_t, size_t, size_t, size_t, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueWriteBuffer(cl_command_queue command_queue, cl_mem buffer, cl_bool blocking_write, size_t offset, size_t size, const void *ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueWriteBuffer:=dll.clEnqueueWriteBuffer).restype, clEnqueueWriteBuffer.argtypes = cl_int, [cl_command_queue, cl_mem, cl_bool, size_t, size_t, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueWriteBufferRect(cl_command_queue command_queue, cl_mem buffer, cl_bool blocking_write, const size_t *buffer_origin, const size_t *host_origin, const size_t *region, size_t buffer_row_pitch, size_t buffer_slice_pitch, size_t host_row_pitch, size_t host_slice_pitch, const void *ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueWriteBufferRect:=dll.clEnqueueWriteBufferRect).restype, clEnqueueWriteBufferRect.argtypes = cl_int, [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), size_t, size_t, size_t, size_t, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueFillBuffer(cl_command_queue command_queue, cl_mem buffer, const void *pattern, size_t pattern_size, size_t offset, size_t size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueFillBuffer:=dll.clEnqueueFillBuffer).restype, clEnqueueFillBuffer.argtypes = cl_int, [cl_command_queue, cl_mem, ctypes.c_void_p, size_t, size_t, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueCopyBuffer(cl_command_queue command_queue, cl_mem src_buffer, cl_mem dst_buffer, size_t src_offset, size_t dst_offset, size_t size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueCopyBuffer:=dll.clEnqueueCopyBuffer).restype, clEnqueueCopyBuffer.argtypes = cl_int, [cl_command_queue, cl_mem, cl_mem, size_t, size_t, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueCopyBufferRect(cl_command_queue command_queue, cl_mem src_buffer, cl_mem dst_buffer, const size_t *src_origin, const size_t *dst_origin, const size_t *region, size_t src_row_pitch, size_t src_slice_pitch, size_t dst_row_pitch, size_t dst_slice_pitch, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueCopyBufferRect:=dll.clEnqueueCopyBufferRect).restype, clEnqueueCopyBufferRect.argtypes = cl_int, [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), size_t, size_t, size_t, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueReadImage(cl_command_queue command_queue, cl_mem image, cl_bool blocking_read, const size_t *origin, const size_t *region, size_t row_pitch, size_t slice_pitch, void *ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueReadImage:=dll.clEnqueueReadImage).restype, clEnqueueReadImage.argtypes = cl_int, [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(size_t), ctypes.POINTER(size_t), size_t, size_t, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueWriteImage(cl_command_queue command_queue, cl_mem image, cl_bool blocking_write, const size_t *origin, const size_t *region, size_t input_row_pitch, size_t input_slice_pitch, const void *ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueWriteImage:=dll.clEnqueueWriteImage).restype, clEnqueueWriteImage.argtypes = cl_int, [cl_command_queue, cl_mem, cl_bool, ctypes.POINTER(size_t), ctypes.POINTER(size_t), size_t, size_t, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueFillImage(cl_command_queue command_queue, cl_mem image, const void *fill_color, const size_t *origin, const size_t *region, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueFillImage:=dll.clEnqueueFillImage).restype, clEnqueueFillImage.argtypes = cl_int, [cl_command_queue, cl_mem, ctypes.c_void_p, ctypes.POINTER(size_t), ctypes.POINTER(size_t), cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueCopyImage(cl_command_queue command_queue, cl_mem src_image, cl_mem dst_image, const size_t *src_origin, const size_t *dst_origin, const size_t *region, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueCopyImage:=dll.clEnqueueCopyImage).restype, clEnqueueCopyImage.argtypes = cl_int, [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueCopyImageToBuffer(cl_command_queue command_queue, cl_mem src_image, cl_mem dst_buffer, const size_t *src_origin, const size_t *region, size_t dst_offset, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueCopyImageToBuffer:=dll.clEnqueueCopyImageToBuffer).restype, clEnqueueCopyImageToBuffer.argtypes = cl_int, [cl_command_queue, cl_mem, cl_mem, ctypes.POINTER(size_t), ctypes.POINTER(size_t), size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueCopyBufferToImage(cl_command_queue command_queue, cl_mem src_buffer, cl_mem dst_image, size_t src_offset, const size_t *dst_origin, const size_t *region, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueCopyBufferToImage:=dll.clEnqueueCopyBufferToImage).restype, clEnqueueCopyBufferToImage.argtypes = cl_int, [cl_command_queue, cl_mem, cl_mem, size_t, ctypes.POINTER(size_t), ctypes.POINTER(size_t), cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern void *clEnqueueMapBuffer(cl_command_queue command_queue, cl_mem buffer, cl_bool blocking_map, cl_map_flags map_flags, size_t offset, size_t size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event, cl_int *errcode_ret) +try: (clEnqueueMapBuffer:=dll.clEnqueueMapBuffer).restype, clEnqueueMapBuffer.argtypes = ctypes.c_void_p, [cl_command_queue, cl_mem, cl_bool, cl_map_flags, size_t, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern void *clEnqueueMapImage(cl_command_queue command_queue, cl_mem image, cl_bool blocking_map, cl_map_flags map_flags, const size_t *origin, const size_t *region, size_t *image_row_pitch, size_t *image_slice_pitch, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event, cl_int *errcode_ret) +try: (clEnqueueMapImage:=dll.clEnqueueMapImage).restype, clEnqueueMapImage.argtypes = ctypes.c_void_p, [cl_command_queue, cl_mem, cl_bool, cl_map_flags, ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event), ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clEnqueueUnmapMemObject(cl_command_queue command_queue, cl_mem memobj, void *mapped_ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueUnmapMemObject:=dll.clEnqueueUnmapMemObject).restype, clEnqueueUnmapMemObject.argtypes = cl_int, [cl_command_queue, cl_mem, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueMigrateMemObjects(cl_command_queue command_queue, cl_uint num_mem_objects, const cl_mem *mem_objects, cl_mem_migration_flags flags, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueMigrateMemObjects:=dll.clEnqueueMigrateMemObjects).restype, clEnqueueMigrateMemObjects.argtypes = cl_int, [cl_command_queue, cl_uint, ctypes.POINTER(cl_mem), cl_mem_migration_flags, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueNDRangeKernel(cl_command_queue command_queue, cl_kernel kernel, cl_uint work_dim, const size_t *global_work_offset, const size_t *global_work_size, const size_t *local_work_size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueNDRangeKernel:=dll.clEnqueueNDRangeKernel).restype, clEnqueueNDRangeKernel.argtypes = cl_int, [cl_command_queue, cl_kernel, cl_uint, ctypes.POINTER(size_t), ctypes.POINTER(size_t), ctypes.POINTER(size_t), cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueNativeKernel(cl_command_queue command_queue, void (*user_func)(void *), void *args, size_t cb_args, cl_uint num_mem_objects, const cl_mem *mem_list, const void **args_mem_loc, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueNativeKernel:=dll.clEnqueueNativeKernel).restype, clEnqueueNativeKernel.argtypes = cl_int, [cl_command_queue, ctypes.CFUNCTYPE(None, ctypes.c_void_p), ctypes.c_void_p, size_t, cl_uint, ctypes.POINTER(cl_mem), ctypes.POINTER(ctypes.c_void_p), cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueMarkerWithWaitList(cl_command_queue command_queue, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueMarkerWithWaitList:=dll.clEnqueueMarkerWithWaitList).restype, clEnqueueMarkerWithWaitList.argtypes = cl_int, [cl_command_queue, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueBarrierWithWaitList(cl_command_queue command_queue, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueBarrierWithWaitList:=dll.clEnqueueBarrierWithWaitList).restype, clEnqueueBarrierWithWaitList.argtypes = cl_int, [cl_command_queue, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueSVMFree(cl_command_queue command_queue, cl_uint num_svm_pointers, void *svm_pointers[], void (*pfn_free_func)(cl_command_queue, cl_uint, void **, void *), void *user_data, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueSVMFree:=dll.clEnqueueSVMFree).restype, clEnqueueSVMFree.argtypes = cl_int, [cl_command_queue, cl_uint, (ctypes.c_void_p * 0), ctypes.CFUNCTYPE(None, cl_command_queue, cl_uint, (ctypes.c_void_p * 0), ctypes.c_void_p), ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueSVMMemcpy(cl_command_queue command_queue, cl_bool blocking_copy, void *dst_ptr, const void *src_ptr, size_t size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueSVMMemcpy:=dll.clEnqueueSVMMemcpy).restype, clEnqueueSVMMemcpy.argtypes = cl_int, [cl_command_queue, cl_bool, ctypes.c_void_p, ctypes.c_void_p, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueSVMMemFill(cl_command_queue command_queue, void *svm_ptr, const void *pattern, size_t pattern_size, size_t size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueSVMMemFill:=dll.clEnqueueSVMMemFill).restype, clEnqueueSVMMemFill.argtypes = cl_int, [cl_command_queue, ctypes.c_void_p, ctypes.c_void_p, size_t, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueSVMMap(cl_command_queue command_queue, cl_bool blocking_map, cl_map_flags flags, void *svm_ptr, size_t size, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueSVMMap:=dll.clEnqueueSVMMap).restype, clEnqueueSVMMap.argtypes = cl_int, [cl_command_queue, cl_bool, cl_map_flags, ctypes.c_void_p, size_t, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueSVMUnmap(cl_command_queue command_queue, void *svm_ptr, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueSVMUnmap:=dll.clEnqueueSVMUnmap).restype, clEnqueueSVMUnmap.argtypes = cl_int, [cl_command_queue, ctypes.c_void_p, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueSVMMigrateMem(cl_command_queue command_queue, cl_uint num_svm_pointers, const void **svm_pointers, const size_t *sizes, cl_mem_migration_flags flags, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) +try: (clEnqueueSVMMigrateMem:=dll.clEnqueueSVMMigrateMem).restype, clEnqueueSVMMigrateMem.argtypes = cl_int, [cl_command_queue, cl_uint, ctypes.POINTER(ctypes.c_void_p), ctypes.POINTER(size_t), cl_mem_migration_flags, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern void *clGetExtensionFunctionAddressForPlatform(cl_platform_id platform, const char *func_name) +try: (clGetExtensionFunctionAddressForPlatform:=dll.clGetExtensionFunctionAddressForPlatform).restype, clGetExtensionFunctionAddressForPlatform.argtypes = ctypes.c_void_p, [cl_platform_id, ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern cl_mem clCreateImage2D(cl_context context, cl_mem_flags flags, const cl_image_format *image_format, size_t image_width, size_t image_height, size_t image_row_pitch, void *host_ptr, cl_int *errcode_ret) __attribute__((deprecated(""))) +try: (clCreateImage2D:=dll.clCreateImage2D).restype, clCreateImage2D.argtypes = cl_mem, [cl_context, cl_mem_flags, ctypes.POINTER(cl_image_format), size_t, size_t, size_t, ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_mem clCreateImage3D(cl_context context, cl_mem_flags flags, const cl_image_format *image_format, size_t image_width, size_t image_height, size_t image_depth, size_t image_row_pitch, size_t image_slice_pitch, void *host_ptr, cl_int *errcode_ret) __attribute__((deprecated(""))) +try: (clCreateImage3D:=dll.clCreateImage3D).restype, clCreateImage3D.argtypes = cl_mem, [cl_context, cl_mem_flags, ctypes.POINTER(cl_image_format), size_t, size_t, size_t, size_t, size_t, ctypes.c_void_p, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clEnqueueMarker(cl_command_queue command_queue, cl_event *event) __attribute__((deprecated(""))) +try: (clEnqueueMarker:=dll.clEnqueueMarker).restype, clEnqueueMarker.argtypes = cl_int, [cl_command_queue, ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueWaitForEvents(cl_command_queue command_queue, cl_uint num_events, const cl_event *event_list) __attribute__((deprecated(""))) +try: (clEnqueueWaitForEvents:=dll.clEnqueueWaitForEvents).restype, clEnqueueWaitForEvents.argtypes = cl_int, [cl_command_queue, cl_uint, ctypes.POINTER(cl_event)] +except AttributeError: pass + +# extern cl_int clEnqueueBarrier(cl_command_queue command_queue) __attribute__((deprecated(""))) +try: (clEnqueueBarrier:=dll.clEnqueueBarrier).restype, clEnqueueBarrier.argtypes = cl_int, [cl_command_queue] +except AttributeError: pass + +# extern cl_int clUnloadCompiler(void) __attribute__((deprecated(""))) +try: (clUnloadCompiler:=dll.clUnloadCompiler).restype, clUnloadCompiler.argtypes = cl_int, [] +except AttributeError: pass + +# extern void *clGetExtensionFunctionAddress(const char *func_name) __attribute__((deprecated(""))) +try: (clGetExtensionFunctionAddress:=dll.clGetExtensionFunctionAddress).restype, clGetExtensionFunctionAddress.argtypes = ctypes.c_void_p, [ctypes.POINTER(ctypes.c_char)] +except AttributeError: pass + +# extern cl_command_queue clCreateCommandQueue(cl_context context, cl_device_id device, cl_command_queue_properties properties, cl_int *errcode_ret) __attribute__((deprecated(""))) +try: (clCreateCommandQueue:=dll.clCreateCommandQueue).restype, clCreateCommandQueue.argtypes = cl_command_queue, [cl_context, cl_device_id, cl_command_queue_properties, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_sampler clCreateSampler(cl_context context, cl_bool normalized_coords, cl_addressing_mode addressing_mode, cl_filter_mode filter_mode, cl_int *errcode_ret) __attribute__((deprecated(""))) +try: (clCreateSampler:=dll.clCreateSampler).restype, clCreateSampler.argtypes = cl_sampler, [cl_context, cl_bool, cl_addressing_mode, cl_filter_mode, ctypes.POINTER(cl_int)] +except AttributeError: pass + +# extern cl_int clEnqueueTask(cl_command_queue command_queue, cl_kernel kernel, cl_uint num_events_in_wait_list, const cl_event *event_wait_list, cl_event *event) __attribute__((deprecated(""))) +try: (clEnqueueTask:=dll.clEnqueueTask).restype, clEnqueueTask.argtypes = cl_int, [cl_command_queue, cl_kernel, cl_uint, ctypes.POINTER(cl_event), ctypes.POINTER(cl_event)] +except AttributeError: pass + +CL_NAME_VERSION_MAX_NAME_SIZE = 64 +CL_SUCCESS = 0 +CL_DEVICE_NOT_FOUND = -1 +CL_DEVICE_NOT_AVAILABLE = -2 +CL_COMPILER_NOT_AVAILABLE = -3 +CL_MEM_OBJECT_ALLOCATION_FAILURE = -4 +CL_OUT_OF_RESOURCES = -5 +CL_OUT_OF_HOST_MEMORY = -6 +CL_PROFILING_INFO_NOT_AVAILABLE = -7 +CL_MEM_COPY_OVERLAP = -8 +CL_IMAGE_FORMAT_MISMATCH = -9 +CL_IMAGE_FORMAT_NOT_SUPPORTED = -10 +CL_BUILD_PROGRAM_FAILURE = -11 +CL_MAP_FAILURE = -12 +CL_MISALIGNED_SUB_BUFFER_OFFSET = -13 +CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST = -14 +CL_COMPILE_PROGRAM_FAILURE = -15 +CL_LINKER_NOT_AVAILABLE = -16 +CL_LINK_PROGRAM_FAILURE = -17 +CL_DEVICE_PARTITION_FAILED = -18 +CL_KERNEL_ARG_INFO_NOT_AVAILABLE = -19 +CL_INVALID_VALUE = -30 +CL_INVALID_DEVICE_TYPE = -31 +CL_INVALID_PLATFORM = -32 +CL_INVALID_DEVICE = -33 +CL_INVALID_CONTEXT = -34 +CL_INVALID_QUEUE_PROPERTIES = -35 +CL_INVALID_COMMAND_QUEUE = -36 +CL_INVALID_HOST_PTR = -37 +CL_INVALID_MEM_OBJECT = -38 +CL_INVALID_IMAGE_FORMAT_DESCRIPTOR = -39 +CL_INVALID_IMAGE_SIZE = -40 +CL_INVALID_SAMPLER = -41 +CL_INVALID_BINARY = -42 +CL_INVALID_BUILD_OPTIONS = -43 +CL_INVALID_PROGRAM = -44 +CL_INVALID_PROGRAM_EXECUTABLE = -45 +CL_INVALID_KERNEL_NAME = -46 +CL_INVALID_KERNEL_DEFINITION = -47 +CL_INVALID_KERNEL = -48 +CL_INVALID_ARG_INDEX = -49 +CL_INVALID_ARG_VALUE = -50 +CL_INVALID_ARG_SIZE = -51 +CL_INVALID_KERNEL_ARGS = -52 +CL_INVALID_WORK_DIMENSION = -53 +CL_INVALID_WORK_GROUP_SIZE = -54 +CL_INVALID_WORK_ITEM_SIZE = -55 +CL_INVALID_GLOBAL_OFFSET = -56 +CL_INVALID_EVENT_WAIT_LIST = -57 +CL_INVALID_EVENT = -58 +CL_INVALID_OPERATION = -59 +CL_INVALID_GL_OBJECT = -60 +CL_INVALID_BUFFER_SIZE = -61 +CL_INVALID_MIP_LEVEL = -62 +CL_INVALID_GLOBAL_WORK_SIZE = -63 +CL_INVALID_PROPERTY = -64 +CL_INVALID_IMAGE_DESCRIPTOR = -65 +CL_INVALID_COMPILER_OPTIONS = -66 +CL_INVALID_LINKER_OPTIONS = -67 +CL_INVALID_DEVICE_PARTITION_COUNT = -68 +CL_INVALID_PIPE_SIZE = -69 +CL_INVALID_DEVICE_QUEUE = -70 +CL_INVALID_SPEC_ID = -71 +CL_MAX_SIZE_RESTRICTION_EXCEEDED = -72 +CL_FALSE = 0 +CL_TRUE = 1 +CL_BLOCKING = CL_TRUE +CL_NON_BLOCKING = CL_FALSE +CL_PLATFORM_PROFILE = 0x0900 +CL_PLATFORM_VERSION = 0x0901 +CL_PLATFORM_NAME = 0x0902 +CL_PLATFORM_VENDOR = 0x0903 +CL_PLATFORM_EXTENSIONS = 0x0904 +CL_PLATFORM_HOST_TIMER_RESOLUTION = 0x0905 +CL_PLATFORM_NUMERIC_VERSION = 0x0906 +CL_PLATFORM_EXTENSIONS_WITH_VERSION = 0x0907 +CL_DEVICE_TYPE_DEFAULT = (1 << 0) +CL_DEVICE_TYPE_CPU = (1 << 1) +CL_DEVICE_TYPE_GPU = (1 << 2) +CL_DEVICE_TYPE_ACCELERATOR = (1 << 3) +CL_DEVICE_TYPE_CUSTOM = (1 << 4) +CL_DEVICE_TYPE_ALL = 0xFFFFFFFF +CL_DEVICE_TYPE = 0x1000 +CL_DEVICE_VENDOR_ID = 0x1001 +CL_DEVICE_MAX_COMPUTE_UNITS = 0x1002 +CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 0x1003 +CL_DEVICE_MAX_WORK_GROUP_SIZE = 0x1004 +CL_DEVICE_MAX_WORK_ITEM_SIZES = 0x1005 +CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 0x1006 +CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 0x1007 +CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 0x1008 +CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 0x1009 +CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 0x100A +CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0x100B +CL_DEVICE_MAX_CLOCK_FREQUENCY = 0x100C +CL_DEVICE_ADDRESS_BITS = 0x100D +CL_DEVICE_MAX_READ_IMAGE_ARGS = 0x100E +CL_DEVICE_MAX_WRITE_IMAGE_ARGS = 0x100F +CL_DEVICE_MAX_MEM_ALLOC_SIZE = 0x1010 +CL_DEVICE_IMAGE2D_MAX_WIDTH = 0x1011 +CL_DEVICE_IMAGE2D_MAX_HEIGHT = 0x1012 +CL_DEVICE_IMAGE3D_MAX_WIDTH = 0x1013 +CL_DEVICE_IMAGE3D_MAX_HEIGHT = 0x1014 +CL_DEVICE_IMAGE3D_MAX_DEPTH = 0x1015 +CL_DEVICE_IMAGE_SUPPORT = 0x1016 +CL_DEVICE_MAX_PARAMETER_SIZE = 0x1017 +CL_DEVICE_MAX_SAMPLERS = 0x1018 +CL_DEVICE_MEM_BASE_ADDR_ALIGN = 0x1019 +CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 0x101A +CL_DEVICE_SINGLE_FP_CONFIG = 0x101B +CL_DEVICE_GLOBAL_MEM_CACHE_TYPE = 0x101C +CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0x101D +CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 0x101E +CL_DEVICE_GLOBAL_MEM_SIZE = 0x101F +CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 0x1020 +CL_DEVICE_MAX_CONSTANT_ARGS = 0x1021 +CL_DEVICE_LOCAL_MEM_TYPE = 0x1022 +CL_DEVICE_LOCAL_MEM_SIZE = 0x1023 +CL_DEVICE_ERROR_CORRECTION_SUPPORT = 0x1024 +CL_DEVICE_PROFILING_TIMER_RESOLUTION = 0x1025 +CL_DEVICE_ENDIAN_LITTLE = 0x1026 +CL_DEVICE_AVAILABLE = 0x1027 +CL_DEVICE_COMPILER_AVAILABLE = 0x1028 +CL_DEVICE_EXECUTION_CAPABILITIES = 0x1029 +CL_DEVICE_QUEUE_PROPERTIES = 0x102A +CL_DEVICE_QUEUE_ON_HOST_PROPERTIES = 0x102A +CL_DEVICE_NAME = 0x102B +CL_DEVICE_VENDOR = 0x102C +CL_DRIVER_VERSION = 0x102D +CL_DEVICE_PROFILE = 0x102E +CL_DEVICE_VERSION = 0x102F +CL_DEVICE_EXTENSIONS = 0x1030 +CL_DEVICE_PLATFORM = 0x1031 +CL_DEVICE_DOUBLE_FP_CONFIG = 0x1032 +CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF = 0x1034 +CL_DEVICE_HOST_UNIFIED_MEMORY = 0x1035 +CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR = 0x1036 +CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT = 0x1037 +CL_DEVICE_NATIVE_VECTOR_WIDTH_INT = 0x1038 +CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG = 0x1039 +CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT = 0x103A +CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE = 0x103B +CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF = 0x103C +CL_DEVICE_OPENCL_C_VERSION = 0x103D +CL_DEVICE_LINKER_AVAILABLE = 0x103E +CL_DEVICE_BUILT_IN_KERNELS = 0x103F +CL_DEVICE_IMAGE_MAX_BUFFER_SIZE = 0x1040 +CL_DEVICE_IMAGE_MAX_ARRAY_SIZE = 0x1041 +CL_DEVICE_PARENT_DEVICE = 0x1042 +CL_DEVICE_PARTITION_MAX_SUB_DEVICES = 0x1043 +CL_DEVICE_PARTITION_PROPERTIES = 0x1044 +CL_DEVICE_PARTITION_AFFINITY_DOMAIN = 0x1045 +CL_DEVICE_PARTITION_TYPE = 0x1046 +CL_DEVICE_REFERENCE_COUNT = 0x1047 +CL_DEVICE_PREFERRED_INTEROP_USER_SYNC = 0x1048 +CL_DEVICE_PRINTF_BUFFER_SIZE = 0x1049 +CL_DEVICE_IMAGE_PITCH_ALIGNMENT = 0x104A +CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT = 0x104B +CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS = 0x104C +CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE = 0x104D +CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES = 0x104E +CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE = 0x104F +CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE = 0x1050 +CL_DEVICE_MAX_ON_DEVICE_QUEUES = 0x1051 +CL_DEVICE_MAX_ON_DEVICE_EVENTS = 0x1052 +CL_DEVICE_SVM_CAPABILITIES = 0x1053 +CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE = 0x1054 +CL_DEVICE_MAX_PIPE_ARGS = 0x1055 +CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS = 0x1056 +CL_DEVICE_PIPE_MAX_PACKET_SIZE = 0x1057 +CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT = 0x1058 +CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT = 0x1059 +CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT = 0x105A +CL_DEVICE_IL_VERSION = 0x105B +CL_DEVICE_MAX_NUM_SUB_GROUPS = 0x105C +CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS = 0x105D +CL_DEVICE_NUMERIC_VERSION = 0x105E +CL_DEVICE_EXTENSIONS_WITH_VERSION = 0x1060 +CL_DEVICE_ILS_WITH_VERSION = 0x1061 +CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION = 0x1062 +CL_DEVICE_ATOMIC_MEMORY_CAPABILITIES = 0x1063 +CL_DEVICE_ATOMIC_FENCE_CAPABILITIES = 0x1064 +CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT = 0x1065 +CL_DEVICE_OPENCL_C_ALL_VERSIONS = 0x1066 +CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_MULTIPLE = 0x1067 +CL_DEVICE_WORK_GROUP_COLLECTIVE_FUNCTIONS_SUPPORT = 0x1068 +CL_DEVICE_GENERIC_ADDRESS_SPACE_SUPPORT = 0x1069 +CL_DEVICE_OPENCL_C_FEATURES = 0x106F +CL_DEVICE_DEVICE_ENQUEUE_CAPABILITIES = 0x1070 +CL_DEVICE_PIPE_SUPPORT = 0x1071 +CL_DEVICE_LATEST_CONFORMANCE_VERSION_PASSED = 0x1072 +CL_FP_DENORM = (1 << 0) +CL_FP_INF_NAN = (1 << 1) +CL_FP_ROUND_TO_NEAREST = (1 << 2) +CL_FP_ROUND_TO_ZERO = (1 << 3) +CL_FP_ROUND_TO_INF = (1 << 4) +CL_FP_FMA = (1 << 5) +CL_FP_SOFT_FLOAT = (1 << 6) +CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT = (1 << 7) +CL_NONE = 0x0 +CL_READ_ONLY_CACHE = 0x1 +CL_READ_WRITE_CACHE = 0x2 +CL_LOCAL = 0x1 +CL_GLOBAL = 0x2 +CL_EXEC_KERNEL = (1 << 0) +CL_EXEC_NATIVE_KERNEL = (1 << 1) +CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE = (1 << 0) +CL_QUEUE_PROFILING_ENABLE = (1 << 1) +CL_QUEUE_ON_DEVICE = (1 << 2) +CL_QUEUE_ON_DEVICE_DEFAULT = (1 << 3) +CL_CONTEXT_REFERENCE_COUNT = 0x1080 +CL_CONTEXT_DEVICES = 0x1081 +CL_CONTEXT_PROPERTIES = 0x1082 +CL_CONTEXT_NUM_DEVICES = 0x1083 +CL_CONTEXT_PLATFORM = 0x1084 +CL_CONTEXT_INTEROP_USER_SYNC = 0x1085 +CL_DEVICE_PARTITION_EQUALLY = 0x1086 +CL_DEVICE_PARTITION_BY_COUNTS = 0x1087 +CL_DEVICE_PARTITION_BY_COUNTS_LIST_END = 0x0 +CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN = 0x1088 +CL_DEVICE_AFFINITY_DOMAIN_NUMA = (1 << 0) +CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE = (1 << 1) +CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE = (1 << 2) +CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE = (1 << 3) +CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE = (1 << 4) +CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE = (1 << 5) +CL_DEVICE_SVM_COARSE_GRAIN_BUFFER = (1 << 0) +CL_DEVICE_SVM_FINE_GRAIN_BUFFER = (1 << 1) +CL_DEVICE_SVM_FINE_GRAIN_SYSTEM = (1 << 2) +CL_DEVICE_SVM_ATOMICS = (1 << 3) +CL_QUEUE_CONTEXT = 0x1090 +CL_QUEUE_DEVICE = 0x1091 +CL_QUEUE_REFERENCE_COUNT = 0x1092 +CL_QUEUE_PROPERTIES = 0x1093 +CL_QUEUE_SIZE = 0x1094 +CL_QUEUE_DEVICE_DEFAULT = 0x1095 +CL_QUEUE_PROPERTIES_ARRAY = 0x1098 +CL_MEM_READ_WRITE = (1 << 0) +CL_MEM_WRITE_ONLY = (1 << 1) +CL_MEM_READ_ONLY = (1 << 2) +CL_MEM_USE_HOST_PTR = (1 << 3) +CL_MEM_ALLOC_HOST_PTR = (1 << 4) +CL_MEM_COPY_HOST_PTR = (1 << 5) +CL_MEM_HOST_WRITE_ONLY = (1 << 7) +CL_MEM_HOST_READ_ONLY = (1 << 8) +CL_MEM_HOST_NO_ACCESS = (1 << 9) +CL_MEM_SVM_FINE_GRAIN_BUFFER = (1 << 10) +CL_MEM_SVM_ATOMICS = (1 << 11) +CL_MEM_KERNEL_READ_AND_WRITE = (1 << 12) +CL_MIGRATE_MEM_OBJECT_HOST = (1 << 0) +CL_MIGRATE_MEM_OBJECT_CONTENT_UNDEFINED = (1 << 1) +CL_R = 0x10B0 +CL_A = 0x10B1 +CL_RG = 0x10B2 +CL_RA = 0x10B3 +CL_RGB = 0x10B4 +CL_RGBA = 0x10B5 +CL_BGRA = 0x10B6 +CL_ARGB = 0x10B7 +CL_INTENSITY = 0x10B8 +CL_LUMINANCE = 0x10B9 +CL_Rx = 0x10BA +CL_RGx = 0x10BB +CL_RGBx = 0x10BC +CL_DEPTH = 0x10BD +CL_sRGB = 0x10BF +CL_sRGBx = 0x10C0 +CL_sRGBA = 0x10C1 +CL_sBGRA = 0x10C2 +CL_ABGR = 0x10C3 +CL_SNORM_INT8 = 0x10D0 +CL_SNORM_INT16 = 0x10D1 +CL_UNORM_INT8 = 0x10D2 +CL_UNORM_INT16 = 0x10D3 +CL_UNORM_SHORT_565 = 0x10D4 +CL_UNORM_SHORT_555 = 0x10D5 +CL_UNORM_INT_101010 = 0x10D6 +CL_SIGNED_INT8 = 0x10D7 +CL_SIGNED_INT16 = 0x10D8 +CL_SIGNED_INT32 = 0x10D9 +CL_UNSIGNED_INT8 = 0x10DA +CL_UNSIGNED_INT16 = 0x10DB +CL_UNSIGNED_INT32 = 0x10DC +CL_HALF_FLOAT = 0x10DD +CL_FLOAT = 0x10DE +CL_UNORM_INT_101010_2 = 0x10E0 +CL_MEM_OBJECT_BUFFER = 0x10F0 +CL_MEM_OBJECT_IMAGE2D = 0x10F1 +CL_MEM_OBJECT_IMAGE3D = 0x10F2 +CL_MEM_OBJECT_IMAGE2D_ARRAY = 0x10F3 +CL_MEM_OBJECT_IMAGE1D = 0x10F4 +CL_MEM_OBJECT_IMAGE1D_ARRAY = 0x10F5 +CL_MEM_OBJECT_IMAGE1D_BUFFER = 0x10F6 +CL_MEM_OBJECT_PIPE = 0x10F7 +CL_MEM_TYPE = 0x1100 +CL_MEM_FLAGS = 0x1101 +CL_MEM_SIZE = 0x1102 +CL_MEM_HOST_PTR = 0x1103 +CL_MEM_MAP_COUNT = 0x1104 +CL_MEM_REFERENCE_COUNT = 0x1105 +CL_MEM_CONTEXT = 0x1106 +CL_MEM_ASSOCIATED_MEMOBJECT = 0x1107 +CL_MEM_OFFSET = 0x1108 +CL_MEM_USES_SVM_POINTER = 0x1109 +CL_MEM_PROPERTIES = 0x110A +CL_IMAGE_FORMAT = 0x1110 +CL_IMAGE_ELEMENT_SIZE = 0x1111 +CL_IMAGE_ROW_PITCH = 0x1112 +CL_IMAGE_SLICE_PITCH = 0x1113 +CL_IMAGE_WIDTH = 0x1114 +CL_IMAGE_HEIGHT = 0x1115 +CL_IMAGE_DEPTH = 0x1116 +CL_IMAGE_ARRAY_SIZE = 0x1117 +CL_IMAGE_BUFFER = 0x1118 +CL_IMAGE_NUM_MIP_LEVELS = 0x1119 +CL_IMAGE_NUM_SAMPLES = 0x111A +CL_PIPE_PACKET_SIZE = 0x1120 +CL_PIPE_MAX_PACKETS = 0x1121 +CL_PIPE_PROPERTIES = 0x1122 +CL_ADDRESS_NONE = 0x1130 +CL_ADDRESS_CLAMP_TO_EDGE = 0x1131 +CL_ADDRESS_CLAMP = 0x1132 +CL_ADDRESS_REPEAT = 0x1133 +CL_ADDRESS_MIRRORED_REPEAT = 0x1134 +CL_FILTER_NEAREST = 0x1140 +CL_FILTER_LINEAR = 0x1141 +CL_SAMPLER_REFERENCE_COUNT = 0x1150 +CL_SAMPLER_CONTEXT = 0x1151 +CL_SAMPLER_NORMALIZED_COORDS = 0x1152 +CL_SAMPLER_ADDRESSING_MODE = 0x1153 +CL_SAMPLER_FILTER_MODE = 0x1154 +CL_SAMPLER_MIP_FILTER_MODE = 0x1155 +CL_SAMPLER_LOD_MIN = 0x1156 +CL_SAMPLER_LOD_MAX = 0x1157 +CL_SAMPLER_PROPERTIES = 0x1158 +CL_MAP_READ = (1 << 0) +CL_MAP_WRITE = (1 << 1) +CL_MAP_WRITE_INVALIDATE_REGION = (1 << 2) +CL_PROGRAM_REFERENCE_COUNT = 0x1160 +CL_PROGRAM_CONTEXT = 0x1161 +CL_PROGRAM_NUM_DEVICES = 0x1162 +CL_PROGRAM_DEVICES = 0x1163 +CL_PROGRAM_SOURCE = 0x1164 +CL_PROGRAM_BINARY_SIZES = 0x1165 +CL_PROGRAM_BINARIES = 0x1166 +CL_PROGRAM_NUM_KERNELS = 0x1167 +CL_PROGRAM_KERNEL_NAMES = 0x1168 +CL_PROGRAM_IL = 0x1169 +CL_PROGRAM_SCOPE_GLOBAL_CTORS_PRESENT = 0x116A +CL_PROGRAM_SCOPE_GLOBAL_DTORS_PRESENT = 0x116B +CL_PROGRAM_BUILD_STATUS = 0x1181 +CL_PROGRAM_BUILD_OPTIONS = 0x1182 +CL_PROGRAM_BUILD_LOG = 0x1183 +CL_PROGRAM_BINARY_TYPE = 0x1184 +CL_PROGRAM_BUILD_GLOBAL_VARIABLE_TOTAL_SIZE = 0x1185 +CL_PROGRAM_BINARY_TYPE_NONE = 0x0 +CL_PROGRAM_BINARY_TYPE_COMPILED_OBJECT = 0x1 +CL_PROGRAM_BINARY_TYPE_LIBRARY = 0x2 +CL_PROGRAM_BINARY_TYPE_EXECUTABLE = 0x4 +CL_BUILD_SUCCESS = 0 +CL_BUILD_NONE = -1 +CL_BUILD_ERROR = -2 +CL_BUILD_IN_PROGRESS = -3 +CL_KERNEL_FUNCTION_NAME = 0x1190 +CL_KERNEL_NUM_ARGS = 0x1191 +CL_KERNEL_REFERENCE_COUNT = 0x1192 +CL_KERNEL_CONTEXT = 0x1193 +CL_KERNEL_PROGRAM = 0x1194 +CL_KERNEL_ATTRIBUTES = 0x1195 +CL_KERNEL_ARG_ADDRESS_QUALIFIER = 0x1196 +CL_KERNEL_ARG_ACCESS_QUALIFIER = 0x1197 +CL_KERNEL_ARG_TYPE_NAME = 0x1198 +CL_KERNEL_ARG_TYPE_QUALIFIER = 0x1199 +CL_KERNEL_ARG_NAME = 0x119A +CL_KERNEL_ARG_ADDRESS_GLOBAL = 0x119B +CL_KERNEL_ARG_ADDRESS_LOCAL = 0x119C +CL_KERNEL_ARG_ADDRESS_CONSTANT = 0x119D +CL_KERNEL_ARG_ADDRESS_PRIVATE = 0x119E +CL_KERNEL_ARG_ACCESS_READ_ONLY = 0x11A0 +CL_KERNEL_ARG_ACCESS_WRITE_ONLY = 0x11A1 +CL_KERNEL_ARG_ACCESS_READ_WRITE = 0x11A2 +CL_KERNEL_ARG_ACCESS_NONE = 0x11A3 +CL_KERNEL_ARG_TYPE_NONE = 0 +CL_KERNEL_ARG_TYPE_CONST = (1 << 0) +CL_KERNEL_ARG_TYPE_RESTRICT = (1 << 1) +CL_KERNEL_ARG_TYPE_VOLATILE = (1 << 2) +CL_KERNEL_ARG_TYPE_PIPE = (1 << 3) +CL_KERNEL_WORK_GROUP_SIZE = 0x11B0 +CL_KERNEL_COMPILE_WORK_GROUP_SIZE = 0x11B1 +CL_KERNEL_LOCAL_MEM_SIZE = 0x11B2 +CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE = 0x11B3 +CL_KERNEL_PRIVATE_MEM_SIZE = 0x11B4 +CL_KERNEL_GLOBAL_WORK_SIZE = 0x11B5 +CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE = 0x2033 +CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE = 0x2034 +CL_KERNEL_LOCAL_SIZE_FOR_SUB_GROUP_COUNT = 0x11B8 +CL_KERNEL_MAX_NUM_SUB_GROUPS = 0x11B9 +CL_KERNEL_COMPILE_NUM_SUB_GROUPS = 0x11BA +CL_KERNEL_EXEC_INFO_SVM_PTRS = 0x11B6 +CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM = 0x11B7 +CL_EVENT_COMMAND_QUEUE = 0x11D0 +CL_EVENT_COMMAND_TYPE = 0x11D1 +CL_EVENT_REFERENCE_COUNT = 0x11D2 +CL_EVENT_COMMAND_EXECUTION_STATUS = 0x11D3 +CL_EVENT_CONTEXT = 0x11D4 +CL_COMMAND_NDRANGE_KERNEL = 0x11F0 +CL_COMMAND_TASK = 0x11F1 +CL_COMMAND_NATIVE_KERNEL = 0x11F2 +CL_COMMAND_READ_BUFFER = 0x11F3 +CL_COMMAND_WRITE_BUFFER = 0x11F4 +CL_COMMAND_COPY_BUFFER = 0x11F5 +CL_COMMAND_READ_IMAGE = 0x11F6 +CL_COMMAND_WRITE_IMAGE = 0x11F7 +CL_COMMAND_COPY_IMAGE = 0x11F8 +CL_COMMAND_COPY_IMAGE_TO_BUFFER = 0x11F9 +CL_COMMAND_COPY_BUFFER_TO_IMAGE = 0x11FA +CL_COMMAND_MAP_BUFFER = 0x11FB +CL_COMMAND_MAP_IMAGE = 0x11FC +CL_COMMAND_UNMAP_MEM_OBJECT = 0x11FD +CL_COMMAND_MARKER = 0x11FE +CL_COMMAND_ACQUIRE_GL_OBJECTS = 0x11FF +CL_COMMAND_RELEASE_GL_OBJECTS = 0x1200 +CL_COMMAND_READ_BUFFER_RECT = 0x1201 +CL_COMMAND_WRITE_BUFFER_RECT = 0x1202 +CL_COMMAND_COPY_BUFFER_RECT = 0x1203 +CL_COMMAND_USER = 0x1204 +CL_COMMAND_BARRIER = 0x1205 +CL_COMMAND_MIGRATE_MEM_OBJECTS = 0x1206 +CL_COMMAND_FILL_BUFFER = 0x1207 +CL_COMMAND_FILL_IMAGE = 0x1208 +CL_COMMAND_SVM_FREE = 0x1209 +CL_COMMAND_SVM_MEMCPY = 0x120A +CL_COMMAND_SVM_MEMFILL = 0x120B +CL_COMMAND_SVM_MAP = 0x120C +CL_COMMAND_SVM_UNMAP = 0x120D +CL_COMMAND_SVM_MIGRATE_MEM = 0x120E +CL_COMPLETE = 0x0 +CL_RUNNING = 0x1 +CL_SUBMITTED = 0x2 +CL_QUEUED = 0x3 +CL_BUFFER_CREATE_TYPE_REGION = 0x1220 +CL_PROFILING_COMMAND_QUEUED = 0x1280 +CL_PROFILING_COMMAND_SUBMIT = 0x1281 +CL_PROFILING_COMMAND_START = 0x1282 +CL_PROFILING_COMMAND_END = 0x1283 +CL_PROFILING_COMMAND_COMPLETE = 0x1284 +CL_DEVICE_ATOMIC_ORDER_RELAXED = (1 << 0) +CL_DEVICE_ATOMIC_ORDER_ACQ_REL = (1 << 1) +CL_DEVICE_ATOMIC_ORDER_SEQ_CST = (1 << 2) +CL_DEVICE_ATOMIC_SCOPE_WORK_ITEM = (1 << 3) +CL_DEVICE_ATOMIC_SCOPE_WORK_GROUP = (1 << 4) +CL_DEVICE_ATOMIC_SCOPE_DEVICE = (1 << 5) +CL_DEVICE_ATOMIC_SCOPE_ALL_DEVICES = (1 << 6) +CL_DEVICE_QUEUE_SUPPORTED = (1 << 0) +CL_DEVICE_QUEUE_REPLACEABLE_DEFAULT = (1 << 1) +CL_KHRONOS_VENDOR_ID_CODEPLAY = 0x10004 +CL_VERSION_MAJOR_BITS = (10) +CL_VERSION_MINOR_BITS = (10) +CL_VERSION_PATCH_BITS = (12) +CL_VERSION_MAJOR_MASK = ((1 << CL_VERSION_MAJOR_BITS) - 1) +CL_VERSION_MINOR_MASK = ((1 << CL_VERSION_MINOR_BITS) - 1) +CL_VERSION_PATCH_MASK = ((1 << CL_VERSION_PATCH_BITS) - 1) +CL_VERSION_MAJOR = lambda version: ((version) >> (CL_VERSION_MINOR_BITS + CL_VERSION_PATCH_BITS)) +CL_VERSION_MINOR = lambda version: (((version) >> CL_VERSION_PATCH_BITS) & CL_VERSION_MINOR_MASK) +CL_VERSION_PATCH = lambda version: ((version) & CL_VERSION_PATCH_MASK) +CL_MAKE_VERSION = lambda major,minor,patch: ((((major) & CL_VERSION_MAJOR_MASK) << (CL_VERSION_MINOR_BITS + CL_VERSION_PATCH_BITS)) | (((minor) & CL_VERSION_MINOR_MASK) << CL_VERSION_PATCH_BITS) | ((patch) & CL_VERSION_PATCH_MASK)) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/pci.py b/tinygrad/runtime/autogen/pci.py index 82ec9c13df..c356f2a768 100644 --- a/tinygrad/runtime/autogen/pci.py +++ b/tinygrad/runtime/autogen/pci.py @@ -1,1333 +1,965 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR - - - -LINUX_PCI_REGS_H = True # macro -PCI_CFG_SPACE_SIZE = 256 # macro -PCI_CFG_SPACE_EXP_SIZE = 4096 # macro -PCI_STD_HEADER_SIZEOF = 64 # macro -PCI_STD_NUM_BARS = 6 # macro -PCI_VENDOR_ID = 0x00 # macro -PCI_DEVICE_ID = 0x02 # macro -PCI_COMMAND = 0x04 # macro -PCI_COMMAND_IO = 0x1 # macro -PCI_COMMAND_MEMORY = 0x2 # macro -PCI_COMMAND_MASTER = 0x4 # macro -PCI_COMMAND_SPECIAL = 0x8 # macro -PCI_COMMAND_INVALIDATE = 0x10 # macro -PCI_COMMAND_VGA_PALETTE = 0x20 # macro -PCI_COMMAND_PARITY = 0x40 # macro -PCI_COMMAND_WAIT = 0x80 # macro -PCI_COMMAND_SERR = 0x100 # macro -PCI_COMMAND_FAST_BACK = 0x200 # macro -PCI_COMMAND_INTX_DISABLE = 0x400 # macro -PCI_STATUS = 0x06 # macro -PCI_STATUS_IMM_READY = 0x01 # macro -PCI_STATUS_INTERRUPT = 0x08 # macro -PCI_STATUS_CAP_LIST = 0x10 # macro -PCI_STATUS_66MHZ = 0x20 # macro -PCI_STATUS_UDF = 0x40 # macro -PCI_STATUS_FAST_BACK = 0x80 # macro -PCI_STATUS_PARITY = 0x100 # macro -PCI_STATUS_DEVSEL_MASK = 0x600 # macro -PCI_STATUS_DEVSEL_FAST = 0x000 # macro -PCI_STATUS_DEVSEL_MEDIUM = 0x200 # macro -PCI_STATUS_DEVSEL_SLOW = 0x400 # macro -PCI_STATUS_SIG_TARGET_ABORT = 0x800 # macro -PCI_STATUS_REC_TARGET_ABORT = 0x1000 # macro -PCI_STATUS_REC_MASTER_ABORT = 0x2000 # macro -PCI_STATUS_SIG_SYSTEM_ERROR = 0x4000 # macro -PCI_STATUS_DETECTED_PARITY = 0x8000 # macro -PCI_CLASS_REVISION = 0x08 # macro -PCI_REVISION_ID = 0x08 # macro -PCI_CLASS_PROG = 0x09 # macro -PCI_CLASS_DEVICE = 0x0a # macro -PCI_CACHE_LINE_SIZE = 0x0c # macro -PCI_LATENCY_TIMER = 0x0d # macro -PCI_HEADER_TYPE = 0x0e # macro -PCI_HEADER_TYPE_MASK = 0x7f # macro -PCI_HEADER_TYPE_NORMAL = 0 # macro -PCI_HEADER_TYPE_BRIDGE = 1 # macro -PCI_HEADER_TYPE_CARDBUS = 2 # macro -PCI_BIST = 0x0f # macro -PCI_BIST_CODE_MASK = 0x0f # macro -PCI_BIST_START = 0x40 # macro -PCI_BIST_CAPABLE = 0x80 # macro -PCI_BASE_ADDRESS_0 = 0x10 # macro -PCI_BASE_ADDRESS_1 = 0x14 # macro -PCI_BASE_ADDRESS_2 = 0x18 # macro -PCI_BASE_ADDRESS_3 = 0x1c # macro -PCI_BASE_ADDRESS_4 = 0x20 # macro -PCI_BASE_ADDRESS_5 = 0x24 # macro -PCI_BASE_ADDRESS_SPACE = 0x01 # macro -PCI_BASE_ADDRESS_SPACE_IO = 0x01 # macro -PCI_BASE_ADDRESS_SPACE_MEMORY = 0x00 # macro -PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x06 # macro -PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x00 # macro -PCI_BASE_ADDRESS_MEM_TYPE_1M = 0x02 # macro -PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x04 # macro -PCI_BASE_ADDRESS_MEM_PREFETCH = 0x08 # macro -PCI_BASE_ADDRESS_MEM_MASK = (~0x0f) # macro -PCI_BASE_ADDRESS_IO_MASK = (~0x03) # macro -PCI_CARDBUS_CIS = 0x28 # macro -PCI_SUBSYSTEM_VENDOR_ID = 0x2c # macro -PCI_SUBSYSTEM_ID = 0x2e # macro -PCI_ROM_ADDRESS = 0x30 # macro -PCI_ROM_ADDRESS_ENABLE = 0x01 # macro -PCI_ROM_ADDRESS_MASK = (~0x7ff) # macro -PCI_CAPABILITY_LIST = 0x34 # macro -PCI_INTERRUPT_LINE = 0x3c # macro -PCI_INTERRUPT_PIN = 0x3d # macro -PCI_MIN_GNT = 0x3e # macro -PCI_MAX_LAT = 0x3f # macro -PCI_PRIMARY_BUS = 0x18 # macro -PCI_SECONDARY_BUS = 0x19 # macro -PCI_SUBORDINATE_BUS = 0x1a # macro -PCI_SEC_LATENCY_TIMER = 0x1b # macro -PCI_IO_BASE = 0x1c # macro -PCI_IO_LIMIT = 0x1d # macro -PCI_IO_RANGE_TYPE_MASK = 0x0f # macro -PCI_IO_RANGE_TYPE_16 = 0x00 # macro -PCI_IO_RANGE_TYPE_32 = 0x01 # macro -PCI_IO_RANGE_MASK = (~0x0f) # macro -PCI_IO_1K_RANGE_MASK = (~0x03) # macro -PCI_SEC_STATUS = 0x1e # macro -PCI_MEMORY_BASE = 0x20 # macro -PCI_MEMORY_LIMIT = 0x22 # macro -PCI_MEMORY_RANGE_TYPE_MASK = 0x0f # macro -PCI_MEMORY_RANGE_MASK = (~0x0f) # macro -PCI_PREF_MEMORY_BASE = 0x24 # macro -PCI_PREF_MEMORY_LIMIT = 0x26 # macro -PCI_PREF_RANGE_TYPE_MASK = 0x0f # macro -PCI_PREF_RANGE_TYPE_32 = 0x00 # macro -PCI_PREF_RANGE_TYPE_64 = 0x01 # macro -PCI_PREF_RANGE_MASK = (~0x0f) # macro -PCI_PREF_BASE_UPPER32 = 0x28 # macro -PCI_PREF_LIMIT_UPPER32 = 0x2c # macro -PCI_IO_BASE_UPPER16 = 0x30 # macro -PCI_IO_LIMIT_UPPER16 = 0x32 # macro -PCI_ROM_ADDRESS1 = 0x38 # macro -PCI_BRIDGE_CONTROL = 0x3e # macro -PCI_BRIDGE_CTL_PARITY = 0x01 # macro -PCI_BRIDGE_CTL_SERR = 0x02 # macro -PCI_BRIDGE_CTL_ISA = 0x04 # macro -PCI_BRIDGE_CTL_VGA = 0x08 # macro -PCI_BRIDGE_CTL_MASTER_ABORT = 0x20 # macro -PCI_BRIDGE_CTL_BUS_RESET = 0x40 # macro -PCI_BRIDGE_CTL_FAST_BACK = 0x80 # macro -PCI_CB_CAPABILITY_LIST = 0x14 # macro -PCI_CB_SEC_STATUS = 0x16 # macro -PCI_CB_PRIMARY_BUS = 0x18 # macro -PCI_CB_CARD_BUS = 0x19 # macro -PCI_CB_SUBORDINATE_BUS = 0x1a # macro -PCI_CB_LATENCY_TIMER = 0x1b # macro -PCI_CB_MEMORY_BASE_0 = 0x1c # macro -PCI_CB_MEMORY_LIMIT_0 = 0x20 # macro -PCI_CB_MEMORY_BASE_1 = 0x24 # macro -PCI_CB_MEMORY_LIMIT_1 = 0x28 # macro -PCI_CB_IO_BASE_0 = 0x2c # macro -PCI_CB_IO_BASE_0_HI = 0x2e # macro -PCI_CB_IO_LIMIT_0 = 0x30 # macro -PCI_CB_IO_LIMIT_0_HI = 0x32 # macro -PCI_CB_IO_BASE_1 = 0x34 # macro -PCI_CB_IO_BASE_1_HI = 0x36 # macro -PCI_CB_IO_LIMIT_1 = 0x38 # macro -PCI_CB_IO_LIMIT_1_HI = 0x3a # macro -PCI_CB_IO_RANGE_MASK = (~0x03) # macro -PCI_CB_BRIDGE_CONTROL = 0x3e # macro -PCI_CB_BRIDGE_CTL_PARITY = 0x01 # macro -PCI_CB_BRIDGE_CTL_SERR = 0x02 # macro -PCI_CB_BRIDGE_CTL_ISA = 0x04 # macro -PCI_CB_BRIDGE_CTL_VGA = 0x08 # macro -PCI_CB_BRIDGE_CTL_MASTER_ABORT = 0x20 # macro -PCI_CB_BRIDGE_CTL_CB_RESET = 0x40 # macro -PCI_CB_BRIDGE_CTL_16BIT_INT = 0x80 # macro -PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 = 0x100 # macro -PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 = 0x200 # macro -PCI_CB_BRIDGE_CTL_POST_WRITES = 0x400 # macro -PCI_CB_SUBSYSTEM_VENDOR_ID = 0x40 # macro -PCI_CB_SUBSYSTEM_ID = 0x42 # macro -PCI_CB_LEGACY_MODE_BASE = 0x44 # macro -PCI_CAP_LIST_ID = 0 # macro -PCI_CAP_ID_PM = 0x01 # macro -PCI_CAP_ID_AGP = 0x02 # macro -PCI_CAP_ID_VPD = 0x03 # macro -PCI_CAP_ID_SLOTID = 0x04 # macro -PCI_CAP_ID_MSI = 0x05 # macro -PCI_CAP_ID_CHSWP = 0x06 # macro -PCI_CAP_ID_PCIX = 0x07 # macro -PCI_CAP_ID_HT = 0x08 # macro -PCI_CAP_ID_VNDR = 0x09 # macro -PCI_CAP_ID_DBG = 0x0A # macro -PCI_CAP_ID_CCRC = 0x0B # macro -PCI_CAP_ID_SHPC = 0x0C # macro -PCI_CAP_ID_SSVID = 0x0D # macro -PCI_CAP_ID_AGP3 = 0x0E # macro -PCI_CAP_ID_SECDEV = 0x0F # macro -PCI_CAP_ID_EXP = 0x10 # macro -PCI_CAP_ID_MSIX = 0x11 # macro -PCI_CAP_ID_SATA = 0x12 # macro -PCI_CAP_ID_AF = 0x13 # macro -PCI_CAP_ID_EA = 0x14 # macro -PCI_CAP_ID_MAX = 0x14 # macro -PCI_CAP_LIST_NEXT = 1 # macro -PCI_CAP_FLAGS = 2 # macro -PCI_CAP_SIZEOF = 4 # macro -PCI_PM_PMC = 2 # macro -PCI_PM_CAP_VER_MASK = 0x0007 # macro -PCI_PM_CAP_PME_CLOCK = 0x0008 # macro -PCI_PM_CAP_RESERVED = 0x0010 # macro -PCI_PM_CAP_DSI = 0x0020 # macro -PCI_PM_CAP_AUX_POWER = 0x01C0 # macro -PCI_PM_CAP_D1 = 0x0200 # macro -PCI_PM_CAP_D2 = 0x0400 # macro -PCI_PM_CAP_PME = 0x0800 # macro -PCI_PM_CAP_PME_MASK = 0xF800 # macro -PCI_PM_CAP_PME_D0 = 0x0800 # macro -PCI_PM_CAP_PME_D1 = 0x1000 # macro -PCI_PM_CAP_PME_D2 = 0x2000 # macro -PCI_PM_CAP_PME_D3hot = 0x4000 # macro -PCI_PM_CAP_PME_D3cold = 0x8000 # macro -PCI_PM_CAP_PME_SHIFT = 11 # macro -PCI_PM_CTRL = 4 # macro -PCI_PM_CTRL_STATE_MASK = 0x0003 # macro -PCI_PM_CTRL_NO_SOFT_RESET = 0x0008 # macro -PCI_PM_CTRL_PME_ENABLE = 0x0100 # macro -PCI_PM_CTRL_DATA_SEL_MASK = 0x1e00 # macro -PCI_PM_CTRL_DATA_SCALE_MASK = 0x6000 # macro -PCI_PM_CTRL_PME_STATUS = 0x8000 # macro -PCI_PM_PPB_EXTENSIONS = 6 # macro -PCI_PM_PPB_B2_B3 = 0x40 # macro -PCI_PM_BPCC_ENABLE = 0x80 # macro -PCI_PM_DATA_REGISTER = 7 # macro -PCI_PM_SIZEOF = 8 # macro -PCI_AGP_VERSION = 2 # macro -PCI_AGP_RFU = 3 # macro -PCI_AGP_STATUS = 4 # macro -PCI_AGP_STATUS_RQ_MASK = 0xff000000 # macro -PCI_AGP_STATUS_SBA = 0x0200 # macro -PCI_AGP_STATUS_64BIT = 0x0020 # macro -PCI_AGP_STATUS_FW = 0x0010 # macro -PCI_AGP_STATUS_RATE4 = 0x0004 # macro -PCI_AGP_STATUS_RATE2 = 0x0002 # macro -PCI_AGP_STATUS_RATE1 = 0x0001 # macro -PCI_AGP_COMMAND = 8 # macro -PCI_AGP_COMMAND_RQ_MASK = 0xff000000 # macro -PCI_AGP_COMMAND_SBA = 0x0200 # macro -PCI_AGP_COMMAND_AGP = 0x0100 # macro -PCI_AGP_COMMAND_64BIT = 0x0020 # macro -PCI_AGP_COMMAND_FW = 0x0010 # macro -PCI_AGP_COMMAND_RATE4 = 0x0004 # macro -PCI_AGP_COMMAND_RATE2 = 0x0002 # macro -PCI_AGP_COMMAND_RATE1 = 0x0001 # macro -PCI_AGP_SIZEOF = 12 # macro -PCI_VPD_ADDR = 2 # macro -PCI_VPD_ADDR_MASK = 0x7fff # macro -PCI_VPD_ADDR_F = 0x8000 # macro -PCI_VPD_DATA = 4 # macro -PCI_CAP_VPD_SIZEOF = 8 # macro -PCI_SID_ESR = 2 # macro -PCI_SID_ESR_NSLOTS = 0x1f # macro -PCI_SID_ESR_FIC = 0x20 # macro -PCI_SID_CHASSIS_NR = 3 # macro -PCI_MSI_FLAGS = 2 # macro -PCI_MSI_FLAGS_ENABLE = 0x0001 # macro -PCI_MSI_FLAGS_QMASK = 0x000e # macro -PCI_MSI_FLAGS_QSIZE = 0x0070 # macro -PCI_MSI_FLAGS_64BIT = 0x0080 # macro -PCI_MSI_FLAGS_MASKBIT = 0x0100 # macro -PCI_MSI_RFU = 3 # macro -PCI_MSI_ADDRESS_LO = 4 # macro -PCI_MSI_ADDRESS_HI = 8 # macro -PCI_MSI_DATA_32 = 8 # macro -PCI_MSI_MASK_32 = 12 # macro -PCI_MSI_PENDING_32 = 16 # macro -PCI_MSI_DATA_64 = 12 # macro -PCI_MSI_MASK_64 = 16 # macro -PCI_MSI_PENDING_64 = 20 # macro -PCI_MSIX_FLAGS = 2 # macro -PCI_MSIX_FLAGS_QSIZE = 0x07FF # macro -PCI_MSIX_FLAGS_MASKALL = 0x4000 # macro -PCI_MSIX_FLAGS_ENABLE = 0x8000 # macro -PCI_MSIX_TABLE = 4 # macro -PCI_MSIX_TABLE_BIR = 0x00000007 # macro -PCI_MSIX_TABLE_OFFSET = 0xfffffff8 # macro -PCI_MSIX_PBA = 8 # macro -PCI_MSIX_PBA_BIR = 0x00000007 # macro -PCI_MSIX_PBA_OFFSET = 0xfffffff8 # macro -PCI_MSIX_FLAGS_BIRMASK = 0x00000007 # macro -PCI_CAP_MSIX_SIZEOF = 12 # macro -PCI_MSIX_ENTRY_SIZE = 16 # macro -PCI_MSIX_ENTRY_LOWER_ADDR = 0 # macro -PCI_MSIX_ENTRY_UPPER_ADDR = 4 # macro -PCI_MSIX_ENTRY_DATA = 8 # macro -PCI_MSIX_ENTRY_VECTOR_CTRL = 12 # macro -PCI_MSIX_ENTRY_CTRL_MASKBIT = 0x00000001 # macro -PCI_CHSWP_CSR = 2 # macro -PCI_CHSWP_DHA = 0x01 # macro -PCI_CHSWP_EIM = 0x02 # macro -PCI_CHSWP_PIE = 0x04 # macro -PCI_CHSWP_LOO = 0x08 # macro -PCI_CHSWP_PI = 0x30 # macro -PCI_CHSWP_EXT = 0x40 # macro -PCI_CHSWP_INS = 0x80 # macro -PCI_AF_LENGTH = 2 # macro -PCI_AF_CAP = 3 # macro -PCI_AF_CAP_TP = 0x01 # macro -PCI_AF_CAP_FLR = 0x02 # macro -PCI_AF_CTRL = 4 # macro -PCI_AF_CTRL_FLR = 0x01 # macro -PCI_AF_STATUS = 5 # macro -PCI_AF_STATUS_TP = 0x01 # macro -PCI_CAP_AF_SIZEOF = 6 # macro -PCI_EA_NUM_ENT = 2 # macro -PCI_EA_NUM_ENT_MASK = 0x3f # macro -PCI_EA_FIRST_ENT = 4 # macro -PCI_EA_FIRST_ENT_BRIDGE = 8 # macro -PCI_EA_ES = 0x00000007 # macro -PCI_EA_BEI = 0x000000f0 # macro -PCI_EA_SEC_BUS_MASK = 0xff # macro -PCI_EA_SUB_BUS_MASK = 0xff00 # macro -PCI_EA_SUB_BUS_SHIFT = 8 # macro -PCI_EA_BEI_BAR0 = 0 # macro -PCI_EA_BEI_BAR5 = 5 # macro -PCI_EA_BEI_BRIDGE = 6 # macro -PCI_EA_BEI_ENI = 7 # macro -PCI_EA_BEI_ROM = 8 # macro -PCI_EA_BEI_VF_BAR0 = 9 # macro -PCI_EA_BEI_VF_BAR5 = 14 # macro -PCI_EA_BEI_RESERVED = 15 # macro -PCI_EA_PP = 0x0000ff00 # macro -PCI_EA_SP = 0x00ff0000 # macro -PCI_EA_P_MEM = 0x00 # macro -PCI_EA_P_MEM_PREFETCH = 0x01 # macro -PCI_EA_P_IO = 0x02 # macro -PCI_EA_P_VF_MEM_PREFETCH = 0x03 # macro -PCI_EA_P_VF_MEM = 0x04 # macro -PCI_EA_P_BRIDGE_MEM = 0x05 # macro -PCI_EA_P_BRIDGE_MEM_PREFETCH = 0x06 # macro -PCI_EA_P_BRIDGE_IO = 0x07 # macro -PCI_EA_P_MEM_RESERVED = 0xfd # macro -PCI_EA_P_IO_RESERVED = 0xfe # macro -PCI_EA_P_UNAVAILABLE = 0xff # macro -PCI_EA_WRITABLE = 0x40000000 # macro -PCI_EA_ENABLE = 0x80000000 # macro -PCI_EA_BASE = 4 # macro -PCI_EA_MAX_OFFSET = 8 # macro -PCI_EA_IS_64 = 0x00000002 # macro -PCI_EA_FIELD_MASK = 0xfffffffc # macro -PCI_X_CMD = 2 # macro -PCI_X_CMD_DPERR_E = 0x0001 # macro -PCI_X_CMD_ERO = 0x0002 # macro -PCI_X_CMD_READ_512 = 0x0000 # macro -PCI_X_CMD_READ_1K = 0x0004 # macro -PCI_X_CMD_READ_2K = 0x0008 # macro -PCI_X_CMD_READ_4K = 0x000c # macro -PCI_X_CMD_MAX_READ = 0x000c # macro -PCI_X_CMD_SPLIT_1 = 0x0000 # macro -PCI_X_CMD_SPLIT_2 = 0x0010 # macro -PCI_X_CMD_SPLIT_3 = 0x0020 # macro -PCI_X_CMD_SPLIT_4 = 0x0030 # macro -PCI_X_CMD_SPLIT_8 = 0x0040 # macro -PCI_X_CMD_SPLIT_12 = 0x0050 # macro -PCI_X_CMD_SPLIT_16 = 0x0060 # macro -PCI_X_CMD_SPLIT_32 = 0x0070 # macro -PCI_X_CMD_MAX_SPLIT = 0x0070 # macro -def PCI_X_CMD_VERSION(x): # macro - return (((x)>>12)&3) -PCI_X_STATUS = 4 # macro -PCI_X_STATUS_DEVFN = 0x000000ff # macro -PCI_X_STATUS_BUS = 0x0000ff00 # macro -PCI_X_STATUS_64BIT = 0x00010000 # macro -PCI_X_STATUS_133MHZ = 0x00020000 # macro -PCI_X_STATUS_SPL_DISC = 0x00040000 # macro -PCI_X_STATUS_UNX_SPL = 0x00080000 # macro -PCI_X_STATUS_COMPLEX = 0x00100000 # macro -PCI_X_STATUS_MAX_READ = 0x00600000 # macro -PCI_X_STATUS_MAX_SPLIT = 0x03800000 # macro -PCI_X_STATUS_MAX_CUM = 0x1c000000 # macro -PCI_X_STATUS_SPL_ERR = 0x20000000 # macro -PCI_X_STATUS_266MHZ = 0x40000000 # macro -PCI_X_STATUS_533MHZ = 0x80000000 # macro -PCI_X_ECC_CSR = 8 # macro -PCI_CAP_PCIX_SIZEOF_V0 = 8 # macro -PCI_CAP_PCIX_SIZEOF_V1 = 24 # macro -PCI_CAP_PCIX_SIZEOF_V2 = 24 # macro -PCI_X_BRIDGE_SSTATUS = 2 # macro -PCI_X_SSTATUS_64BIT = 0x0001 # macro -PCI_X_SSTATUS_133MHZ = 0x0002 # macro -PCI_X_SSTATUS_FREQ = 0x03c0 # macro -PCI_X_SSTATUS_VERS = 0x3000 # macro -PCI_X_SSTATUS_V1 = 0x1000 # macro -PCI_X_SSTATUS_V2 = 0x2000 # macro -PCI_X_SSTATUS_266MHZ = 0x4000 # macro -PCI_X_SSTATUS_533MHZ = 0x8000 # macro -PCI_X_BRIDGE_STATUS = 4 # macro -PCI_SSVID_VENDOR_ID = 4 # macro -PCI_SSVID_DEVICE_ID = 6 # macro -PCI_EXP_FLAGS = 2 # macro -PCI_EXP_FLAGS_VERS = 0x000f # macro -PCI_EXP_FLAGS_TYPE = 0x00f0 # macro -PCI_EXP_TYPE_ENDPOINT = 0x0 # macro -PCI_EXP_TYPE_LEG_END = 0x1 # macro -PCI_EXP_TYPE_ROOT_PORT = 0x4 # macro -PCI_EXP_TYPE_UPSTREAM = 0x5 # macro -PCI_EXP_TYPE_DOWNSTREAM = 0x6 # macro -PCI_EXP_TYPE_PCI_BRIDGE = 0x7 # macro -PCI_EXP_TYPE_PCIE_BRIDGE = 0x8 # macro -PCI_EXP_TYPE_RC_END = 0x9 # macro -PCI_EXP_TYPE_RC_EC = 0xa # macro -PCI_EXP_FLAGS_SLOT = 0x0100 # macro -PCI_EXP_FLAGS_IRQ = 0x3e00 # macro -PCI_EXP_DEVCAP = 4 # macro -PCI_EXP_DEVCAP_PAYLOAD = 0x00000007 # macro -PCI_EXP_DEVCAP_PHANTOM = 0x00000018 # macro -PCI_EXP_DEVCAP_EXT_TAG = 0x00000020 # macro -PCI_EXP_DEVCAP_L0S = 0x000001c0 # macro -PCI_EXP_DEVCAP_L1 = 0x00000e00 # macro -PCI_EXP_DEVCAP_ATN_BUT = 0x00001000 # macro -PCI_EXP_DEVCAP_ATN_IND = 0x00002000 # macro -PCI_EXP_DEVCAP_PWR_IND = 0x00004000 # macro -PCI_EXP_DEVCAP_RBER = 0x00008000 # macro -PCI_EXP_DEVCAP_PWR_VAL = 0x03fc0000 # macro -PCI_EXP_DEVCAP_PWR_SCL = 0x0c000000 # macro -PCI_EXP_DEVCAP_FLR = 0x10000000 # macro -PCI_EXP_DEVCTL = 8 # macro -PCI_EXP_DEVCTL_CERE = 0x0001 # macro -PCI_EXP_DEVCTL_NFERE = 0x0002 # macro -PCI_EXP_DEVCTL_FERE = 0x0004 # macro -PCI_EXP_DEVCTL_URRE = 0x0008 # macro -PCI_EXP_DEVCTL_RELAX_EN = 0x0010 # macro -PCI_EXP_DEVCTL_PAYLOAD = 0x00e0 # macro -PCI_EXP_DEVCTL_PAYLOAD_128B = 0x0000 # macro -PCI_EXP_DEVCTL_PAYLOAD_256B = 0x0020 # macro -PCI_EXP_DEVCTL_PAYLOAD_512B = 0x0040 # macro -PCI_EXP_DEVCTL_PAYLOAD_1024B = 0x0060 # macro -PCI_EXP_DEVCTL_PAYLOAD_2048B = 0x0080 # macro -PCI_EXP_DEVCTL_PAYLOAD_4096B = 0x00a0 # macro -PCI_EXP_DEVCTL_EXT_TAG = 0x0100 # macro -PCI_EXP_DEVCTL_PHANTOM = 0x0200 # macro -PCI_EXP_DEVCTL_AUX_PME = 0x0400 # macro -PCI_EXP_DEVCTL_NOSNOOP_EN = 0x0800 # macro -PCI_EXP_DEVCTL_READRQ = 0x7000 # macro -PCI_EXP_DEVCTL_READRQ_128B = 0x0000 # macro -PCI_EXP_DEVCTL_READRQ_256B = 0x1000 # macro -PCI_EXP_DEVCTL_READRQ_512B = 0x2000 # macro -PCI_EXP_DEVCTL_READRQ_1024B = 0x3000 # macro -PCI_EXP_DEVCTL_READRQ_2048B = 0x4000 # macro -PCI_EXP_DEVCTL_READRQ_4096B = 0x5000 # macro -PCI_EXP_DEVCTL_BCR_FLR = 0x8000 # macro -PCI_EXP_DEVSTA = 10 # macro -PCI_EXP_DEVSTA_CED = 0x0001 # macro -PCI_EXP_DEVSTA_NFED = 0x0002 # macro -PCI_EXP_DEVSTA_FED = 0x0004 # macro -PCI_EXP_DEVSTA_URD = 0x0008 # macro -PCI_EXP_DEVSTA_AUXPD = 0x0010 # macro -PCI_EXP_DEVSTA_TRPND = 0x0020 # macro -PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 = 12 # macro -PCI_EXP_LNKCAP = 12 # macro -PCI_EXP_LNKCAP_SLS = 0x0000000f # macro -PCI_EXP_LNKCAP_SLS_2_5GB = 0x00000001 # macro -PCI_EXP_LNKCAP_SLS_5_0GB = 0x00000002 # macro -PCI_EXP_LNKCAP_SLS_8_0GB = 0x00000003 # macro -PCI_EXP_LNKCAP_SLS_16_0GB = 0x00000004 # macro -PCI_EXP_LNKCAP_SLS_32_0GB = 0x00000005 # macro -PCI_EXP_LNKCAP_SLS_64_0GB = 0x00000006 # macro -PCI_EXP_LNKCAP_MLW = 0x000003f0 # macro -PCI_EXP_LNKCAP_ASPMS = 0x00000c00 # macro -PCI_EXP_LNKCAP_ASPM_L0S = 0x00000400 # macro -PCI_EXP_LNKCAP_ASPM_L1 = 0x00000800 # macro -PCI_EXP_LNKCAP_L0SEL = 0x00007000 # macro -PCI_EXP_LNKCAP_L1EL = 0x00038000 # macro -PCI_EXP_LNKCAP_CLKPM = 0x00040000 # macro -PCI_EXP_LNKCAP_SDERC = 0x00080000 # macro -PCI_EXP_LNKCAP_DLLLARC = 0x00100000 # macro -PCI_EXP_LNKCAP_LBNC = 0x00200000 # macro -PCI_EXP_LNKCAP_PN = 0xff000000 # macro -PCI_EXP_LNKCTL = 16 # macro -PCI_EXP_LNKCTL_ASPMC = 0x0003 # macro -PCI_EXP_LNKCTL_ASPM_L0S = 0x0001 # macro -PCI_EXP_LNKCTL_ASPM_L1 = 0x0002 # macro -PCI_EXP_LNKCTL_RCB = 0x0008 # macro -PCI_EXP_LNKCTL_LD = 0x0010 # macro -PCI_EXP_LNKCTL_RL = 0x0020 # macro -PCI_EXP_LNKCTL_CCC = 0x0040 # macro -PCI_EXP_LNKCTL_ES = 0x0080 # macro -PCI_EXP_LNKCTL_CLKREQ_EN = 0x0100 # macro -PCI_EXP_LNKCTL_HAWD = 0x0200 # macro -PCI_EXP_LNKCTL_LBMIE = 0x0400 # macro -PCI_EXP_LNKCTL_LABIE = 0x0800 # macro -PCI_EXP_LNKSTA = 18 # macro -PCI_EXP_LNKSTA_CLS = 0x000f # macro -PCI_EXP_LNKSTA_CLS_2_5GB = 0x0001 # macro -PCI_EXP_LNKSTA_CLS_5_0GB = 0x0002 # macro -PCI_EXP_LNKSTA_CLS_8_0GB = 0x0003 # macro -PCI_EXP_LNKSTA_CLS_16_0GB = 0x0004 # macro -PCI_EXP_LNKSTA_CLS_32_0GB = 0x0005 # macro -PCI_EXP_LNKSTA_CLS_64_0GB = 0x0006 # macro -PCI_EXP_LNKSTA_NLW = 0x03f0 # macro -PCI_EXP_LNKSTA_NLW_X1 = 0x0010 # macro -PCI_EXP_LNKSTA_NLW_X2 = 0x0020 # macro -PCI_EXP_LNKSTA_NLW_X4 = 0x0040 # macro -PCI_EXP_LNKSTA_NLW_X8 = 0x0080 # macro -PCI_EXP_LNKSTA_NLW_SHIFT = 4 # macro -PCI_EXP_LNKSTA_LT = 0x0800 # macro -PCI_EXP_LNKSTA_SLC = 0x1000 # macro -PCI_EXP_LNKSTA_DLLLA = 0x2000 # macro -PCI_EXP_LNKSTA_LBMS = 0x4000 # macro -PCI_EXP_LNKSTA_LABS = 0x8000 # macro -PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 = 20 # macro -PCI_EXP_SLTCAP = 20 # macro -PCI_EXP_SLTCAP_ABP = 0x00000001 # macro -PCI_EXP_SLTCAP_PCP = 0x00000002 # macro -PCI_EXP_SLTCAP_MRLSP = 0x00000004 # macro -PCI_EXP_SLTCAP_AIP = 0x00000008 # macro -PCI_EXP_SLTCAP_PIP = 0x00000010 # macro -PCI_EXP_SLTCAP_HPS = 0x00000020 # macro -PCI_EXP_SLTCAP_HPC = 0x00000040 # macro -PCI_EXP_SLTCAP_SPLV = 0x00007f80 # macro -PCI_EXP_SLTCAP_SPLS = 0x00018000 # macro -PCI_EXP_SLTCAP_EIP = 0x00020000 # macro -PCI_EXP_SLTCAP_NCCS = 0x00040000 # macro -PCI_EXP_SLTCAP_PSN = 0xfff80000 # macro -PCI_EXP_SLTCTL = 24 # macro -PCI_EXP_SLTCTL_ABPE = 0x0001 # macro -PCI_EXP_SLTCTL_PFDE = 0x0002 # macro -PCI_EXP_SLTCTL_MRLSCE = 0x0004 # macro -PCI_EXP_SLTCTL_PDCE = 0x0008 # macro -PCI_EXP_SLTCTL_CCIE = 0x0010 # macro -PCI_EXP_SLTCTL_HPIE = 0x0020 # macro -PCI_EXP_SLTCTL_AIC = 0x00c0 # macro -PCI_EXP_SLTCTL_ATTN_IND_SHIFT = 6 # macro -PCI_EXP_SLTCTL_ATTN_IND_ON = 0x0040 # macro -PCI_EXP_SLTCTL_ATTN_IND_BLINK = 0x0080 # macro -PCI_EXP_SLTCTL_ATTN_IND_OFF = 0x00c0 # macro -PCI_EXP_SLTCTL_PIC = 0x0300 # macro -PCI_EXP_SLTCTL_PWR_IND_ON = 0x0100 # macro -PCI_EXP_SLTCTL_PWR_IND_BLINK = 0x0200 # macro -PCI_EXP_SLTCTL_PWR_IND_OFF = 0x0300 # macro -PCI_EXP_SLTCTL_PCC = 0x0400 # macro -PCI_EXP_SLTCTL_PWR_ON = 0x0000 # macro -PCI_EXP_SLTCTL_PWR_OFF = 0x0400 # macro -PCI_EXP_SLTCTL_EIC = 0x0800 # macro -PCI_EXP_SLTCTL_DLLSCE = 0x1000 # macro -PCI_EXP_SLTCTL_IBPD_DISABLE = 0x4000 # macro -PCI_EXP_SLTSTA = 26 # macro -PCI_EXP_SLTSTA_ABP = 0x0001 # macro -PCI_EXP_SLTSTA_PFD = 0x0002 # macro -PCI_EXP_SLTSTA_MRLSC = 0x0004 # macro -PCI_EXP_SLTSTA_PDC = 0x0008 # macro -PCI_EXP_SLTSTA_CC = 0x0010 # macro -PCI_EXP_SLTSTA_MRLSS = 0x0020 # macro -PCI_EXP_SLTSTA_PDS = 0x0040 # macro -PCI_EXP_SLTSTA_EIS = 0x0080 # macro -PCI_EXP_SLTSTA_DLLSC = 0x0100 # macro -PCI_EXP_RTCTL = 28 # macro -PCI_EXP_RTCTL_SECEE = 0x0001 # macro -PCI_EXP_RTCTL_SENFEE = 0x0002 # macro -PCI_EXP_RTCTL_SEFEE = 0x0004 # macro -PCI_EXP_RTCTL_PMEIE = 0x0008 # macro -PCI_EXP_RTCTL_CRSSVE = 0x0010 # macro -PCI_EXP_RTCAP = 30 # macro -PCI_EXP_RTCAP_CRSVIS = 0x0001 # macro -PCI_EXP_RTSTA = 32 # macro -PCI_EXP_RTSTA_PME = 0x00010000 # macro -PCI_EXP_RTSTA_PENDING = 0x00020000 # macro -PCI_EXP_DEVCAP2 = 36 # macro -PCI_EXP_DEVCAP2_COMP_TMOUT_DIS = 0x00000010 # macro -PCI_EXP_DEVCAP2_ARI = 0x00000020 # macro -PCI_EXP_DEVCAP2_ATOMIC_ROUTE = 0x00000040 # macro -PCI_EXP_DEVCAP2_ATOMIC_COMP32 = 0x00000080 # macro -PCI_EXP_DEVCAP2_ATOMIC_COMP64 = 0x00000100 # macro -PCI_EXP_DEVCAP2_ATOMIC_COMP128 = 0x00000200 # macro -PCI_EXP_DEVCAP2_LTR = 0x00000800 # macro -PCI_EXP_DEVCAP2_OBFF_MASK = 0x000c0000 # macro -PCI_EXP_DEVCAP2_OBFF_MSG = 0x00040000 # macro -PCI_EXP_DEVCAP2_OBFF_WAKE = 0x00080000 # macro -PCI_EXP_DEVCAP2_EE_PREFIX = 0x00200000 # macro -PCI_EXP_DEVCTL2 = 40 # macro -PCI_EXP_DEVCTL2_COMP_TIMEOUT = 0x000f # macro -PCI_EXP_DEVCTL2_COMP_TMOUT_DIS = 0x0010 # macro -PCI_EXP_DEVCTL2_ARI = 0x0020 # macro -PCI_EXP_DEVCTL2_ATOMIC_REQ = 0x0040 # macro -PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK = 0x0080 # macro -PCI_EXP_DEVCTL2_IDO_REQ_EN = 0x0100 # macro -PCI_EXP_DEVCTL2_IDO_CMP_EN = 0x0200 # macro -PCI_EXP_DEVCTL2_LTR_EN = 0x0400 # macro -PCI_EXP_DEVCTL2_OBFF_MSGA_EN = 0x2000 # macro -PCI_EXP_DEVCTL2_OBFF_MSGB_EN = 0x4000 # macro -PCI_EXP_DEVCTL2_OBFF_WAKE_EN = 0x6000 # macro -PCI_EXP_DEVSTA2 = 42 # macro -PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 = 44 # macro -PCI_EXP_LNKCAP2 = 44 # macro -PCI_EXP_LNKCAP2_SLS_2_5GB = 0x00000002 # macro -PCI_EXP_LNKCAP2_SLS_5_0GB = 0x00000004 # macro -PCI_EXP_LNKCAP2_SLS_8_0GB = 0x00000008 # macro -PCI_EXP_LNKCAP2_SLS_16_0GB = 0x00000010 # macro -PCI_EXP_LNKCAP2_SLS_32_0GB = 0x00000020 # macro -PCI_EXP_LNKCAP2_SLS_64_0GB = 0x00000040 # macro -PCI_EXP_LNKCAP2_CROSSLINK = 0x00000100 # macro -PCI_EXP_LNKCTL2 = 48 # macro -PCI_EXP_LNKCTL2_TLS = 0x000f # macro -PCI_EXP_LNKCTL2_TLS_2_5GT = 0x0001 # macro -PCI_EXP_LNKCTL2_TLS_5_0GT = 0x0002 # macro -PCI_EXP_LNKCTL2_TLS_8_0GT = 0x0003 # macro -PCI_EXP_LNKCTL2_TLS_16_0GT = 0x0004 # macro -PCI_EXP_LNKCTL2_TLS_32_0GT = 0x0005 # macro -PCI_EXP_LNKCTL2_TLS_64_0GT = 0x0006 # macro -PCI_EXP_LNKCTL2_ENTER_COMP = 0x0010 # macro -PCI_EXP_LNKCTL2_TX_MARGIN = 0x0380 # macro -PCI_EXP_LNKCTL2_HASD = 0x0020 # macro -PCI_EXP_LNKSTA2 = 50 # macro -PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 = 52 # macro -PCI_EXP_SLTCAP2 = 52 # macro -PCI_EXP_SLTCAP2_IBPD = 0x00000001 # macro -PCI_EXP_SLTCTL2 = 56 # macro -PCI_EXP_SLTSTA2 = 58 # macro -def PCI_EXT_CAP_ID(header): # macro - return (header&0x0000ffff) -def PCI_EXT_CAP_VER(header): # macro - return ((header>>16)&0xf) -def PCI_EXT_CAP_NEXT(header): # macro - return ((header>>20)&0xffc) -PCI_EXT_CAP_ID_ERR = 0x01 # macro -PCI_EXT_CAP_ID_VC = 0x02 # macro -PCI_EXT_CAP_ID_DSN = 0x03 # macro -PCI_EXT_CAP_ID_PWR = 0x04 # macro -PCI_EXT_CAP_ID_RCLD = 0x05 # macro -PCI_EXT_CAP_ID_RCILC = 0x06 # macro -PCI_EXT_CAP_ID_RCEC = 0x07 # macro -PCI_EXT_CAP_ID_MFVC = 0x08 # macro -PCI_EXT_CAP_ID_VC9 = 0x09 # macro -PCI_EXT_CAP_ID_RCRB = 0x0A # macro -PCI_EXT_CAP_ID_VNDR = 0x0B # macro -PCI_EXT_CAP_ID_CAC = 0x0C # macro -PCI_EXT_CAP_ID_ACS = 0x0D # macro -PCI_EXT_CAP_ID_ARI = 0x0E # macro -PCI_EXT_CAP_ID_ATS = 0x0F # macro -PCI_EXT_CAP_ID_SRIOV = 0x10 # macro -PCI_EXT_CAP_ID_MRIOV = 0x11 # macro -PCI_EXT_CAP_ID_MCAST = 0x12 # macro -PCI_EXT_CAP_ID_PRI = 0x13 # macro -PCI_EXT_CAP_ID_AMD_XXX = 0x14 # macro -PCI_EXT_CAP_ID_REBAR = 0x15 # macro -PCI_EXT_CAP_ID_DPA = 0x16 # macro -PCI_EXT_CAP_ID_TPH = 0x17 # macro -PCI_EXT_CAP_ID_LTR = 0x18 # macro -PCI_EXT_CAP_ID_SECPCI = 0x19 # macro -PCI_EXT_CAP_ID_PMUX = 0x1A # macro -PCI_EXT_CAP_ID_PASID = 0x1B # macro -PCI_EXT_CAP_ID_DPC = 0x1D # macro -PCI_EXT_CAP_ID_L1SS = 0x1E # macro -PCI_EXT_CAP_ID_PTM = 0x1F # macro -PCI_EXT_CAP_ID_DVSEC = 0x23 # macro -PCI_EXT_CAP_ID_DLF = 0x25 # macro -PCI_EXT_CAP_ID_PL_16GT = 0x26 # macro -PCI_EXT_CAP_ID_MAX = 0x26 # macro -PCI_EXT_CAP_DSN_SIZEOF = 12 # macro -PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF = 40 # macro -PCI_ERR_UNCOR_STATUS = 4 # macro -PCI_ERR_UNC_UND = 0x00000001 # macro -PCI_ERR_UNC_DLP = 0x00000010 # macro -PCI_ERR_UNC_SURPDN = 0x00000020 # macro -PCI_ERR_UNC_POISON_TLP = 0x00001000 # macro -PCI_ERR_UNC_FCP = 0x00002000 # macro -PCI_ERR_UNC_COMP_TIME = 0x00004000 # macro -PCI_ERR_UNC_COMP_ABORT = 0x00008000 # macro -PCI_ERR_UNC_UNX_COMP = 0x00010000 # macro -PCI_ERR_UNC_RX_OVER = 0x00020000 # macro -PCI_ERR_UNC_MALF_TLP = 0x00040000 # macro -PCI_ERR_UNC_ECRC = 0x00080000 # macro -PCI_ERR_UNC_UNSUP = 0x00100000 # macro -PCI_ERR_UNC_ACSV = 0x00200000 # macro -PCI_ERR_UNC_INTN = 0x00400000 # macro -PCI_ERR_UNC_MCBTLP = 0x00800000 # macro -PCI_ERR_UNC_ATOMEG = 0x01000000 # macro -PCI_ERR_UNC_TLPPRE = 0x02000000 # macro -PCI_ERR_UNCOR_MASK = 8 # macro -PCI_ERR_UNCOR_SEVER = 12 # macro -PCI_ERR_COR_STATUS = 16 # macro -PCI_ERR_COR_RCVR = 0x00000001 # macro -PCI_ERR_COR_BAD_TLP = 0x00000040 # macro -PCI_ERR_COR_BAD_DLLP = 0x00000080 # macro -PCI_ERR_COR_REP_ROLL = 0x00000100 # macro -PCI_ERR_COR_REP_TIMER = 0x00001000 # macro -PCI_ERR_COR_ADV_NFAT = 0x00002000 # macro -PCI_ERR_COR_INTERNAL = 0x00004000 # macro -PCI_ERR_COR_LOG_OVER = 0x00008000 # macro -PCI_ERR_COR_MASK = 20 # macro -PCI_ERR_CAP = 24 # macro -def PCI_ERR_CAP_FEP(x): # macro - return ((x)&31) -PCI_ERR_CAP_ECRC_GENC = 0x00000020 # macro -PCI_ERR_CAP_ECRC_GENE = 0x00000040 # macro -PCI_ERR_CAP_ECRC_CHKC = 0x00000080 # macro -PCI_ERR_CAP_ECRC_CHKE = 0x00000100 # macro -PCI_ERR_HEADER_LOG = 28 # macro -PCI_ERR_ROOT_COMMAND = 44 # macro -PCI_ERR_ROOT_CMD_COR_EN = 0x00000001 # macro -PCI_ERR_ROOT_CMD_NONFATAL_EN = 0x00000002 # macro -PCI_ERR_ROOT_CMD_FATAL_EN = 0x00000004 # macro -PCI_ERR_ROOT_STATUS = 48 # macro -PCI_ERR_ROOT_COR_RCV = 0x00000001 # macro -PCI_ERR_ROOT_MULTI_COR_RCV = 0x00000002 # macro -PCI_ERR_ROOT_UNCOR_RCV = 0x00000004 # macro -PCI_ERR_ROOT_MULTI_UNCOR_RCV = 0x00000008 # macro -PCI_ERR_ROOT_FIRST_FATAL = 0x00000010 # macro -PCI_ERR_ROOT_NONFATAL_RCV = 0x00000020 # macro -PCI_ERR_ROOT_FATAL_RCV = 0x00000040 # macro -PCI_ERR_ROOT_AER_IRQ = 0xf8000000 # macro -PCI_ERR_ROOT_ERR_SRC = 52 # macro -PCI_VC_PORT_CAP1 = 4 # macro -PCI_VC_CAP1_EVCC = 0x00000007 # macro -PCI_VC_CAP1_LPEVCC = 0x00000070 # macro -PCI_VC_CAP1_ARB_SIZE = 0x00000c00 # macro -PCI_VC_PORT_CAP2 = 8 # macro -PCI_VC_CAP2_32_PHASE = 0x00000002 # macro -PCI_VC_CAP2_64_PHASE = 0x00000004 # macro -PCI_VC_CAP2_128_PHASE = 0x00000008 # macro -PCI_VC_CAP2_ARB_OFF = 0xff000000 # macro -PCI_VC_PORT_CTRL = 12 # macro -PCI_VC_PORT_CTRL_LOAD_TABLE = 0x00000001 # macro -PCI_VC_PORT_STATUS = 14 # macro -PCI_VC_PORT_STATUS_TABLE = 0x00000001 # macro -PCI_VC_RES_CAP = 16 # macro -PCI_VC_RES_CAP_32_PHASE = 0x00000002 # macro -PCI_VC_RES_CAP_64_PHASE = 0x00000004 # macro -PCI_VC_RES_CAP_128_PHASE = 0x00000008 # macro -PCI_VC_RES_CAP_128_PHASE_TB = 0x00000010 # macro -PCI_VC_RES_CAP_256_PHASE = 0x00000020 # macro -PCI_VC_RES_CAP_ARB_OFF = 0xff000000 # macro -PCI_VC_RES_CTRL = 20 # macro -PCI_VC_RES_CTRL_LOAD_TABLE = 0x00010000 # macro -PCI_VC_RES_CTRL_ARB_SELECT = 0x000e0000 # macro -PCI_VC_RES_CTRL_ID = 0x07000000 # macro -PCI_VC_RES_CTRL_ENABLE = 0x80000000 # macro -PCI_VC_RES_STATUS = 26 # macro -PCI_VC_RES_STATUS_TABLE = 0x00000001 # macro -PCI_VC_RES_STATUS_NEGO = 0x00000002 # macro -PCI_CAP_VC_BASE_SIZEOF = 0x10 # macro -PCI_CAP_VC_PER_VC_SIZEOF = 0x0C # macro -PCI_PWR_DSR = 4 # macro -PCI_PWR_DATA = 8 # macro -def PCI_PWR_DATA_BASE(x): # macro - return ((x)&0xff) -def PCI_PWR_DATA_SCALE(x): # macro - return (((x)>>8)&3) -def PCI_PWR_DATA_PM_SUB(x): # macro - return (((x)>>10)&7) -def PCI_PWR_DATA_PM_STATE(x): # macro - return (((x)>>13)&3) -def PCI_PWR_DATA_TYPE(x): # macro - return (((x)>>15)&7) -def PCI_PWR_DATA_RAIL(x): # macro - return (((x)>>18)&7) -PCI_PWR_CAP = 12 # macro -def PCI_PWR_CAP_BUDGET(x): # macro - return ((x)&1) -PCI_EXT_CAP_PWR_SIZEOF = 16 # macro -PCI_RCEC_RCIEP_BITMAP = 4 # macro -PCI_RCEC_BUSN = 8 # macro -PCI_RCEC_BUSN_REG_VER = 0x02 # macro -def PCI_RCEC_BUSN_NEXT(x): # macro - return (((x)>>8)&0xff) -def PCI_RCEC_BUSN_LAST(x): # macro - return (((x)>>16)&0xff) -PCI_VNDR_HEADER = 4 # macro -def PCI_VNDR_HEADER_ID(x): # macro - return ((x)&0xffff) -def PCI_VNDR_HEADER_REV(x): # macro - return (((x)>>16)&0xf) -def PCI_VNDR_HEADER_LEN(x): # macro - return (((x)>>20)&0xfff) -HT_3BIT_CAP_MASK = 0xE0 # macro -HT_CAPTYPE_SLAVE = 0x00 # macro -HT_CAPTYPE_HOST = 0x20 # macro -HT_5BIT_CAP_MASK = 0xF8 # macro -HT_CAPTYPE_IRQ = 0x80 # macro -HT_CAPTYPE_REMAPPING_40 = 0xA0 # macro -HT_CAPTYPE_REMAPPING_64 = 0xA2 # macro -HT_CAPTYPE_UNITID_CLUMP = 0x90 # macro -HT_CAPTYPE_EXTCONF = 0x98 # macro -HT_CAPTYPE_MSI_MAPPING = 0xA8 # macro -HT_MSI_FLAGS = 0x02 # macro -HT_MSI_FLAGS_ENABLE = 0x1 # macro -HT_MSI_FLAGS_FIXED = 0x2 # macro -HT_MSI_FIXED_ADDR = 0x00000000FEE00000 # macro -HT_MSI_ADDR_LO = 0x04 # macro -HT_MSI_ADDR_LO_MASK = 0xFFF00000 # macro -HT_MSI_ADDR_HI = 0x08 # macro -HT_CAPTYPE_DIRECT_ROUTE = 0xB0 # macro -HT_CAPTYPE_VCSET = 0xB8 # macro -HT_CAPTYPE_ERROR_RETRY = 0xC0 # macro -HT_CAPTYPE_GEN3 = 0xD0 # macro -HT_CAPTYPE_PM = 0xE0 # macro -HT_CAP_SIZEOF_LONG = 28 # macro -HT_CAP_SIZEOF_SHORT = 24 # macro -PCI_ARI_CAP = 0x04 # macro -PCI_ARI_CAP_MFVC = 0x0001 # macro -PCI_ARI_CAP_ACS = 0x0002 # macro -def PCI_ARI_CAP_NFN(x): # macro - return (((x)>>8)&0xff) -PCI_ARI_CTRL = 0x06 # macro -PCI_ARI_CTRL_MFVC = 0x0001 # macro -PCI_ARI_CTRL_ACS = 0x0002 # macro -def PCI_ARI_CTRL_FG(x): # macro - return (((x)>>4)&7) -PCI_EXT_CAP_ARI_SIZEOF = 8 # macro -PCI_ATS_CAP = 0x04 # macro -def PCI_ATS_CAP_QDEP(x): # macro - return ((x)&0x1f) -PCI_ATS_MAX_QDEP = 32 # macro -PCI_ATS_CAP_PAGE_ALIGNED = 0x0020 # macro -PCI_ATS_CTRL = 0x06 # macro -PCI_ATS_CTRL_ENABLE = 0x8000 # macro -def PCI_ATS_CTRL_STU(x): # macro - return ((x)&0x1f) -PCI_ATS_MIN_STU = 12 # macro -PCI_EXT_CAP_ATS_SIZEOF = 8 # macro -PCI_PRI_CTRL = 0x04 # macro -PCI_PRI_CTRL_ENABLE = 0x0001 # macro -PCI_PRI_CTRL_RESET = 0x0002 # macro -PCI_PRI_STATUS = 0x06 # macro -PCI_PRI_STATUS_RF = 0x0001 # macro -PCI_PRI_STATUS_UPRGI = 0x0002 # macro -PCI_PRI_STATUS_STOPPED = 0x0100 # macro -PCI_PRI_STATUS_PASID = 0x8000 # macro -PCI_PRI_MAX_REQ = 0x08 # macro -PCI_PRI_ALLOC_REQ = 0x0c # macro -PCI_EXT_CAP_PRI_SIZEOF = 16 # macro -PCI_PASID_CAP = 0x04 # macro -PCI_PASID_CAP_EXEC = 0x02 # macro -PCI_PASID_CAP_PRIV = 0x04 # macro -PCI_PASID_CTRL = 0x06 # macro -PCI_PASID_CTRL_ENABLE = 0x01 # macro -PCI_PASID_CTRL_EXEC = 0x02 # macro -PCI_PASID_CTRL_PRIV = 0x04 # macro -PCI_EXT_CAP_PASID_SIZEOF = 8 # macro -PCI_SRIOV_CAP = 0x04 # macro -PCI_SRIOV_CAP_VFM = 0x00000001 # macro -def PCI_SRIOV_CAP_INTR(x): # macro - return ((x)>>21) -PCI_SRIOV_CTRL = 0x08 # macro -PCI_SRIOV_CTRL_VFE = 0x0001 # macro -PCI_SRIOV_CTRL_VFM = 0x0002 # macro -PCI_SRIOV_CTRL_INTR = 0x0004 # macro -PCI_SRIOV_CTRL_MSE = 0x0008 # macro -PCI_SRIOV_CTRL_ARI = 0x0010 # macro -PCI_SRIOV_STATUS = 0x0a # macro -PCI_SRIOV_STATUS_VFM = 0x0001 # macro -PCI_SRIOV_INITIAL_VF = 0x0c # macro -PCI_SRIOV_TOTAL_VF = 0x0e # macro -PCI_SRIOV_NUM_VF = 0x10 # macro -PCI_SRIOV_FUNC_LINK = 0x12 # macro -PCI_SRIOV_VF_OFFSET = 0x14 # macro -PCI_SRIOV_VF_STRIDE = 0x16 # macro -PCI_SRIOV_VF_DID = 0x1a # macro -PCI_SRIOV_SUP_PGSIZE = 0x1c # macro -PCI_SRIOV_SYS_PGSIZE = 0x20 # macro -PCI_SRIOV_BAR = 0x24 # macro -PCI_SRIOV_NUM_BARS = 6 # macro -PCI_SRIOV_VFM = 0x3c # macro -def PCI_SRIOV_VFM_BIR(x): # macro - return ((x)&7) -def PCI_SRIOV_VFM_OFFSET(x): # macro - return ((x)&~7) -PCI_SRIOV_VFM_UA = 0x0 # macro -PCI_SRIOV_VFM_MI = 0x1 # macro -PCI_SRIOV_VFM_MO = 0x2 # macro -PCI_SRIOV_VFM_AV = 0x3 # macro -PCI_EXT_CAP_SRIOV_SIZEOF = 64 # macro -PCI_LTR_MAX_SNOOP_LAT = 0x4 # macro -PCI_LTR_MAX_NOSNOOP_LAT = 0x6 # macro -PCI_LTR_VALUE_MASK = 0x000003ff # macro -PCI_LTR_SCALE_MASK = 0x00001c00 # macro -PCI_LTR_SCALE_SHIFT = 10 # macro -PCI_EXT_CAP_LTR_SIZEOF = 8 # macro -PCI_ACS_CAP = 0x04 # macro -PCI_ACS_SV = 0x0001 # macro -PCI_ACS_TB = 0x0002 # macro -PCI_ACS_RR = 0x0004 # macro -PCI_ACS_CR = 0x0008 # macro -PCI_ACS_UF = 0x0010 # macro -PCI_ACS_EC = 0x0020 # macro -PCI_ACS_DT = 0x0040 # macro -PCI_ACS_EGRESS_BITS = 0x05 # macro -PCI_ACS_CTRL = 0x06 # macro -PCI_ACS_EGRESS_CTL_V = 0x08 # macro -PCI_VSEC_HDR = 4 # macro -PCI_VSEC_HDR_LEN_SHIFT = 20 # macro -PCI_SATA_REGS = 4 # macro -PCI_SATA_REGS_MASK = 0xF # macro -PCI_SATA_REGS_INLINE = 0xF # macro -PCI_SATA_SIZEOF_SHORT = 8 # macro -PCI_SATA_SIZEOF_LONG = 16 # macro -PCI_REBAR_CAP = 4 # macro -PCI_REBAR_CAP_SIZES = 0x00FFFFF0 # macro -PCI_REBAR_CTRL = 8 # macro -PCI_REBAR_CTRL_BAR_IDX = 0x00000007 # macro -PCI_REBAR_CTRL_NBAR_MASK = 0x000000E0 # macro -PCI_REBAR_CTRL_NBAR_SHIFT = 5 # macro -PCI_REBAR_CTRL_BAR_SIZE = 0x00001F00 # macro -PCI_REBAR_CTRL_BAR_SHIFT = 8 # macro -PCI_DPA_CAP = 4 # macro -PCI_DPA_CAP_SUBSTATE_MASK = 0x1F # macro -PCI_DPA_BASE_SIZEOF = 16 # macro -PCI_TPH_CAP = 4 # macro -PCI_TPH_CAP_LOC_MASK = 0x600 # macro -PCI_TPH_LOC_NONE = 0x000 # macro -PCI_TPH_LOC_CAP = 0x200 # macro -PCI_TPH_LOC_MSIX = 0x400 # macro -PCI_TPH_CAP_ST_MASK = 0x07FF0000 # macro -PCI_TPH_CAP_ST_SHIFT = 16 # macro -PCI_TPH_BASE_SIZEOF = 12 # macro -PCI_EXP_DPC_CAP = 4 # macro -PCI_EXP_DPC_IRQ = 0x001F # macro -PCI_EXP_DPC_CAP_RP_EXT = 0x0020 # macro -PCI_EXP_DPC_CAP_POISONED_TLP = 0x0040 # macro -PCI_EXP_DPC_CAP_SW_TRIGGER = 0x0080 # macro -PCI_EXP_DPC_RP_PIO_LOG_SIZE = 0x0F00 # macro -PCI_EXP_DPC_CAP_DL_ACTIVE = 0x1000 # macro -PCI_EXP_DPC_CTL = 6 # macro -PCI_EXP_DPC_CTL_EN_FATAL = 0x0001 # macro -PCI_EXP_DPC_CTL_EN_NONFATAL = 0x0002 # macro -PCI_EXP_DPC_CTL_INT_EN = 0x0008 # macro -PCI_EXP_DPC_STATUS = 8 # macro -PCI_EXP_DPC_STATUS_TRIGGER = 0x0001 # macro -PCI_EXP_DPC_STATUS_TRIGGER_RSN = 0x0006 # macro -PCI_EXP_DPC_STATUS_INTERRUPT = 0x0008 # macro -PCI_EXP_DPC_RP_BUSY = 0x0010 # macro -PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT = 0x0060 # macro -PCI_EXP_DPC_SOURCE_ID = 10 # macro -PCI_EXP_DPC_RP_PIO_STATUS = 0x0C # macro -PCI_EXP_DPC_RP_PIO_MASK = 0x10 # macro -PCI_EXP_DPC_RP_PIO_SEVERITY = 0x14 # macro -PCI_EXP_DPC_RP_PIO_SYSERROR = 0x18 # macro -PCI_EXP_DPC_RP_PIO_EXCEPTION = 0x1C # macro -PCI_EXP_DPC_RP_PIO_HEADER_LOG = 0x20 # macro -PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG = 0x30 # macro -PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG = 0x34 # macro -PCI_PTM_CAP = 0x04 # macro -PCI_PTM_CAP_REQ = 0x00000001 # macro -PCI_PTM_CAP_ROOT = 0x00000004 # macro -PCI_PTM_GRANULARITY_MASK = 0x0000FF00 # macro -PCI_PTM_CTRL = 0x08 # macro -PCI_PTM_CTRL_ENABLE = 0x00000001 # macro -PCI_PTM_CTRL_ROOT = 0x00000002 # macro -PCI_L1SS_CAP = 0x04 # macro -PCI_L1SS_CAP_PCIPM_L1_2 = 0x00000001 # macro -PCI_L1SS_CAP_PCIPM_L1_1 = 0x00000002 # macro -PCI_L1SS_CAP_ASPM_L1_2 = 0x00000004 # macro -PCI_L1SS_CAP_ASPM_L1_1 = 0x00000008 # macro -PCI_L1SS_CAP_L1_PM_SS = 0x00000010 # macro -PCI_L1SS_CAP_CM_RESTORE_TIME = 0x0000ff00 # macro -PCI_L1SS_CAP_P_PWR_ON_SCALE = 0x00030000 # macro -PCI_L1SS_CAP_P_PWR_ON_VALUE = 0x00f80000 # macro -PCI_L1SS_CTL1 = 0x08 # macro -PCI_L1SS_CTL1_PCIPM_L1_2 = 0x00000001 # macro -PCI_L1SS_CTL1_PCIPM_L1_1 = 0x00000002 # macro -PCI_L1SS_CTL1_ASPM_L1_2 = 0x00000004 # macro -PCI_L1SS_CTL1_ASPM_L1_1 = 0x00000008 # macro -PCI_L1SS_CTL1_L1_2_MASK = 0x00000005 # macro -PCI_L1SS_CTL1_L1SS_MASK = 0x0000000f # macro -PCI_L1SS_CTL1_CM_RESTORE_TIME = 0x0000ff00 # macro -PCI_L1SS_CTL1_LTR_L12_TH_VALUE = 0x03ff0000 # macro -PCI_L1SS_CTL1_LTR_L12_TH_SCALE = 0xe0000000 # macro -PCI_L1SS_CTL2 = 0x0c # macro -PCI_DVSEC_HEADER1 = 0x4 # macro -PCI_DVSEC_HEADER2 = 0x8 # macro -PCI_DLF_CAP = 0x04 # macro -PCI_DLF_EXCHANGE_ENABLE = 0x80000000 # macro -PCI_PL_16GT_LE_CTRL = 0x20 # macro -PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK = 0x0000000F # macro -PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK = 0x000000F0 # macro -PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT = 4 # macro -__all__ = \ - ['HT_3BIT_CAP_MASK', 'HT_5BIT_CAP_MASK', - 'HT_CAPTYPE_DIRECT_ROUTE', 'HT_CAPTYPE_ERROR_RETRY', - 'HT_CAPTYPE_EXTCONF', 'HT_CAPTYPE_GEN3', 'HT_CAPTYPE_HOST', - 'HT_CAPTYPE_IRQ', 'HT_CAPTYPE_MSI_MAPPING', 'HT_CAPTYPE_PM', - 'HT_CAPTYPE_REMAPPING_40', 'HT_CAPTYPE_REMAPPING_64', - 'HT_CAPTYPE_SLAVE', 'HT_CAPTYPE_UNITID_CLUMP', 'HT_CAPTYPE_VCSET', - 'HT_CAP_SIZEOF_LONG', 'HT_CAP_SIZEOF_SHORT', 'HT_MSI_ADDR_HI', - 'HT_MSI_ADDR_LO', 'HT_MSI_ADDR_LO_MASK', 'HT_MSI_FIXED_ADDR', - 'HT_MSI_FLAGS', 'HT_MSI_FLAGS_ENABLE', 'HT_MSI_FLAGS_FIXED', - 'LINUX_PCI_REGS_H', 'PCI_ACS_CAP', 'PCI_ACS_CR', 'PCI_ACS_CTRL', - 'PCI_ACS_DT', 'PCI_ACS_EC', 'PCI_ACS_EGRESS_BITS', - 'PCI_ACS_EGRESS_CTL_V', 'PCI_ACS_RR', 'PCI_ACS_SV', 'PCI_ACS_TB', - 'PCI_ACS_UF', 'PCI_AF_CAP', 'PCI_AF_CAP_FLR', 'PCI_AF_CAP_TP', - 'PCI_AF_CTRL', 'PCI_AF_CTRL_FLR', 'PCI_AF_LENGTH', - 'PCI_AF_STATUS', 'PCI_AF_STATUS_TP', 'PCI_AGP_COMMAND', - 'PCI_AGP_COMMAND_64BIT', 'PCI_AGP_COMMAND_AGP', - 'PCI_AGP_COMMAND_FW', 'PCI_AGP_COMMAND_RATE1', - 'PCI_AGP_COMMAND_RATE2', 'PCI_AGP_COMMAND_RATE4', - 'PCI_AGP_COMMAND_RQ_MASK', 'PCI_AGP_COMMAND_SBA', 'PCI_AGP_RFU', - 'PCI_AGP_SIZEOF', 'PCI_AGP_STATUS', 'PCI_AGP_STATUS_64BIT', - 'PCI_AGP_STATUS_FW', 'PCI_AGP_STATUS_RATE1', - 'PCI_AGP_STATUS_RATE2', 'PCI_AGP_STATUS_RATE4', - 'PCI_AGP_STATUS_RQ_MASK', 'PCI_AGP_STATUS_SBA', 'PCI_AGP_VERSION', - 'PCI_ARI_CAP', 'PCI_ARI_CAP_ACS', 'PCI_ARI_CAP_MFVC', - 'PCI_ARI_CTRL', 'PCI_ARI_CTRL_ACS', 'PCI_ARI_CTRL_MFVC', - 'PCI_ATS_CAP', 'PCI_ATS_CAP_PAGE_ALIGNED', 'PCI_ATS_CTRL', - 'PCI_ATS_CTRL_ENABLE', 'PCI_ATS_MAX_QDEP', 'PCI_ATS_MIN_STU', - 'PCI_BASE_ADDRESS_0', 'PCI_BASE_ADDRESS_1', 'PCI_BASE_ADDRESS_2', - 'PCI_BASE_ADDRESS_3', 'PCI_BASE_ADDRESS_4', 'PCI_BASE_ADDRESS_5', - 'PCI_BASE_ADDRESS_IO_MASK', 'PCI_BASE_ADDRESS_MEM_MASK', - 'PCI_BASE_ADDRESS_MEM_PREFETCH', 'PCI_BASE_ADDRESS_MEM_TYPE_1M', - 'PCI_BASE_ADDRESS_MEM_TYPE_32', 'PCI_BASE_ADDRESS_MEM_TYPE_64', - 'PCI_BASE_ADDRESS_MEM_TYPE_MASK', 'PCI_BASE_ADDRESS_SPACE', - 'PCI_BASE_ADDRESS_SPACE_IO', 'PCI_BASE_ADDRESS_SPACE_MEMORY', - 'PCI_BIST', 'PCI_BIST_CAPABLE', 'PCI_BIST_CODE_MASK', - 'PCI_BIST_START', 'PCI_BRIDGE_CONTROL', - 'PCI_BRIDGE_CTL_BUS_RESET', 'PCI_BRIDGE_CTL_FAST_BACK', - 'PCI_BRIDGE_CTL_ISA', 'PCI_BRIDGE_CTL_MASTER_ABORT', - 'PCI_BRIDGE_CTL_PARITY', 'PCI_BRIDGE_CTL_SERR', - 'PCI_BRIDGE_CTL_VGA', 'PCI_CACHE_LINE_SIZE', - 'PCI_CAPABILITY_LIST', 'PCI_CAP_AF_SIZEOF', - 'PCI_CAP_EXP_ENDPOINT_SIZEOF_V1', - 'PCI_CAP_EXP_ENDPOINT_SIZEOF_V2', - 'PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1', - 'PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2', 'PCI_CAP_FLAGS', - 'PCI_CAP_ID_AF', 'PCI_CAP_ID_AGP', 'PCI_CAP_ID_AGP3', - 'PCI_CAP_ID_CCRC', 'PCI_CAP_ID_CHSWP', 'PCI_CAP_ID_DBG', - 'PCI_CAP_ID_EA', 'PCI_CAP_ID_EXP', 'PCI_CAP_ID_HT', - 'PCI_CAP_ID_MAX', 'PCI_CAP_ID_MSI', 'PCI_CAP_ID_MSIX', - 'PCI_CAP_ID_PCIX', 'PCI_CAP_ID_PM', 'PCI_CAP_ID_SATA', - 'PCI_CAP_ID_SECDEV', 'PCI_CAP_ID_SHPC', 'PCI_CAP_ID_SLOTID', - 'PCI_CAP_ID_SSVID', 'PCI_CAP_ID_VNDR', 'PCI_CAP_ID_VPD', - 'PCI_CAP_LIST_ID', 'PCI_CAP_LIST_NEXT', 'PCI_CAP_MSIX_SIZEOF', - 'PCI_CAP_PCIX_SIZEOF_V0', 'PCI_CAP_PCIX_SIZEOF_V1', - 'PCI_CAP_PCIX_SIZEOF_V2', 'PCI_CAP_SIZEOF', - 'PCI_CAP_VC_BASE_SIZEOF', 'PCI_CAP_VC_PER_VC_SIZEOF', - 'PCI_CAP_VPD_SIZEOF', 'PCI_CARDBUS_CIS', 'PCI_CB_BRIDGE_CONTROL', - 'PCI_CB_BRIDGE_CTL_16BIT_INT', 'PCI_CB_BRIDGE_CTL_CB_RESET', - 'PCI_CB_BRIDGE_CTL_ISA', 'PCI_CB_BRIDGE_CTL_MASTER_ABORT', - 'PCI_CB_BRIDGE_CTL_PARITY', 'PCI_CB_BRIDGE_CTL_POST_WRITES', - 'PCI_CB_BRIDGE_CTL_PREFETCH_MEM0', - 'PCI_CB_BRIDGE_CTL_PREFETCH_MEM1', 'PCI_CB_BRIDGE_CTL_SERR', - 'PCI_CB_BRIDGE_CTL_VGA', 'PCI_CB_CAPABILITY_LIST', - 'PCI_CB_CARD_BUS', 'PCI_CB_IO_BASE_0', 'PCI_CB_IO_BASE_0_HI', - 'PCI_CB_IO_BASE_1', 'PCI_CB_IO_BASE_1_HI', 'PCI_CB_IO_LIMIT_0', - 'PCI_CB_IO_LIMIT_0_HI', 'PCI_CB_IO_LIMIT_1', - 'PCI_CB_IO_LIMIT_1_HI', 'PCI_CB_IO_RANGE_MASK', - 'PCI_CB_LATENCY_TIMER', 'PCI_CB_LEGACY_MODE_BASE', - 'PCI_CB_MEMORY_BASE_0', 'PCI_CB_MEMORY_BASE_1', - 'PCI_CB_MEMORY_LIMIT_0', 'PCI_CB_MEMORY_LIMIT_1', - 'PCI_CB_PRIMARY_BUS', 'PCI_CB_SEC_STATUS', - 'PCI_CB_SUBORDINATE_BUS', 'PCI_CB_SUBSYSTEM_ID', - 'PCI_CB_SUBSYSTEM_VENDOR_ID', 'PCI_CFG_SPACE_EXP_SIZE', - 'PCI_CFG_SPACE_SIZE', 'PCI_CHSWP_CSR', 'PCI_CHSWP_DHA', - 'PCI_CHSWP_EIM', 'PCI_CHSWP_EXT', 'PCI_CHSWP_INS', - 'PCI_CHSWP_LOO', 'PCI_CHSWP_PI', 'PCI_CHSWP_PIE', - 'PCI_CLASS_DEVICE', 'PCI_CLASS_PROG', 'PCI_CLASS_REVISION', - 'PCI_COMMAND', 'PCI_COMMAND_FAST_BACK', - 'PCI_COMMAND_INTX_DISABLE', 'PCI_COMMAND_INVALIDATE', - 'PCI_COMMAND_IO', 'PCI_COMMAND_MASTER', 'PCI_COMMAND_MEMORY', - 'PCI_COMMAND_PARITY', 'PCI_COMMAND_SERR', 'PCI_COMMAND_SPECIAL', - 'PCI_COMMAND_VGA_PALETTE', 'PCI_COMMAND_WAIT', 'PCI_DEVICE_ID', - 'PCI_DLF_CAP', 'PCI_DLF_EXCHANGE_ENABLE', 'PCI_DPA_BASE_SIZEOF', - 'PCI_DPA_CAP', 'PCI_DPA_CAP_SUBSTATE_MASK', 'PCI_DVSEC_HEADER1', - 'PCI_DVSEC_HEADER2', 'PCI_EA_BASE', 'PCI_EA_BEI', - 'PCI_EA_BEI_BAR0', 'PCI_EA_BEI_BAR5', 'PCI_EA_BEI_BRIDGE', - 'PCI_EA_BEI_ENI', 'PCI_EA_BEI_RESERVED', 'PCI_EA_BEI_ROM', - 'PCI_EA_BEI_VF_BAR0', 'PCI_EA_BEI_VF_BAR5', 'PCI_EA_ENABLE', - 'PCI_EA_ES', 'PCI_EA_FIELD_MASK', 'PCI_EA_FIRST_ENT', - 'PCI_EA_FIRST_ENT_BRIDGE', 'PCI_EA_IS_64', 'PCI_EA_MAX_OFFSET', - 'PCI_EA_NUM_ENT', 'PCI_EA_NUM_ENT_MASK', 'PCI_EA_PP', - 'PCI_EA_P_BRIDGE_IO', 'PCI_EA_P_BRIDGE_MEM', - 'PCI_EA_P_BRIDGE_MEM_PREFETCH', 'PCI_EA_P_IO', - 'PCI_EA_P_IO_RESERVED', 'PCI_EA_P_MEM', 'PCI_EA_P_MEM_PREFETCH', - 'PCI_EA_P_MEM_RESERVED', 'PCI_EA_P_UNAVAILABLE', - 'PCI_EA_P_VF_MEM', 'PCI_EA_P_VF_MEM_PREFETCH', - 'PCI_EA_SEC_BUS_MASK', 'PCI_EA_SP', 'PCI_EA_SUB_BUS_MASK', - 'PCI_EA_SUB_BUS_SHIFT', 'PCI_EA_WRITABLE', 'PCI_ERR_CAP', - 'PCI_ERR_CAP_ECRC_CHKC', 'PCI_ERR_CAP_ECRC_CHKE', - 'PCI_ERR_CAP_ECRC_GENC', 'PCI_ERR_CAP_ECRC_GENE', - 'PCI_ERR_COR_ADV_NFAT', 'PCI_ERR_COR_BAD_DLLP', - 'PCI_ERR_COR_BAD_TLP', 'PCI_ERR_COR_INTERNAL', - 'PCI_ERR_COR_LOG_OVER', 'PCI_ERR_COR_MASK', 'PCI_ERR_COR_RCVR', - 'PCI_ERR_COR_REP_ROLL', 'PCI_ERR_COR_REP_TIMER', - 'PCI_ERR_COR_STATUS', 'PCI_ERR_HEADER_LOG', - 'PCI_ERR_ROOT_AER_IRQ', 'PCI_ERR_ROOT_CMD_COR_EN', - 'PCI_ERR_ROOT_CMD_FATAL_EN', 'PCI_ERR_ROOT_CMD_NONFATAL_EN', - 'PCI_ERR_ROOT_COMMAND', 'PCI_ERR_ROOT_COR_RCV', - 'PCI_ERR_ROOT_ERR_SRC', 'PCI_ERR_ROOT_FATAL_RCV', - 'PCI_ERR_ROOT_FIRST_FATAL', 'PCI_ERR_ROOT_MULTI_COR_RCV', - 'PCI_ERR_ROOT_MULTI_UNCOR_RCV', 'PCI_ERR_ROOT_NONFATAL_RCV', - 'PCI_ERR_ROOT_STATUS', 'PCI_ERR_ROOT_UNCOR_RCV', - 'PCI_ERR_UNCOR_MASK', 'PCI_ERR_UNCOR_SEVER', - 'PCI_ERR_UNCOR_STATUS', 'PCI_ERR_UNC_ACSV', 'PCI_ERR_UNC_ATOMEG', - 'PCI_ERR_UNC_COMP_ABORT', 'PCI_ERR_UNC_COMP_TIME', - 'PCI_ERR_UNC_DLP', 'PCI_ERR_UNC_ECRC', 'PCI_ERR_UNC_FCP', - 'PCI_ERR_UNC_INTN', 'PCI_ERR_UNC_MALF_TLP', 'PCI_ERR_UNC_MCBTLP', - 'PCI_ERR_UNC_POISON_TLP', 'PCI_ERR_UNC_RX_OVER', - 'PCI_ERR_UNC_SURPDN', 'PCI_ERR_UNC_TLPPRE', 'PCI_ERR_UNC_UND', - 'PCI_ERR_UNC_UNSUP', 'PCI_ERR_UNC_UNX_COMP', 'PCI_EXP_DEVCAP', - 'PCI_EXP_DEVCAP2', 'PCI_EXP_DEVCAP2_ARI', - 'PCI_EXP_DEVCAP2_ATOMIC_COMP128', 'PCI_EXP_DEVCAP2_ATOMIC_COMP32', - 'PCI_EXP_DEVCAP2_ATOMIC_COMP64', 'PCI_EXP_DEVCAP2_ATOMIC_ROUTE', - 'PCI_EXP_DEVCAP2_COMP_TMOUT_DIS', 'PCI_EXP_DEVCAP2_EE_PREFIX', - 'PCI_EXP_DEVCAP2_LTR', 'PCI_EXP_DEVCAP2_OBFF_MASK', - 'PCI_EXP_DEVCAP2_OBFF_MSG', 'PCI_EXP_DEVCAP2_OBFF_WAKE', - 'PCI_EXP_DEVCAP_ATN_BUT', 'PCI_EXP_DEVCAP_ATN_IND', - 'PCI_EXP_DEVCAP_EXT_TAG', 'PCI_EXP_DEVCAP_FLR', - 'PCI_EXP_DEVCAP_L0S', 'PCI_EXP_DEVCAP_L1', - 'PCI_EXP_DEVCAP_PAYLOAD', 'PCI_EXP_DEVCAP_PHANTOM', - 'PCI_EXP_DEVCAP_PWR_IND', 'PCI_EXP_DEVCAP_PWR_SCL', - 'PCI_EXP_DEVCAP_PWR_VAL', 'PCI_EXP_DEVCAP_RBER', 'PCI_EXP_DEVCTL', - 'PCI_EXP_DEVCTL2', 'PCI_EXP_DEVCTL2_ARI', - 'PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK', - 'PCI_EXP_DEVCTL2_ATOMIC_REQ', 'PCI_EXP_DEVCTL2_COMP_TIMEOUT', - 'PCI_EXP_DEVCTL2_COMP_TMOUT_DIS', 'PCI_EXP_DEVCTL2_IDO_CMP_EN', - 'PCI_EXP_DEVCTL2_IDO_REQ_EN', 'PCI_EXP_DEVCTL2_LTR_EN', - 'PCI_EXP_DEVCTL2_OBFF_MSGA_EN', 'PCI_EXP_DEVCTL2_OBFF_MSGB_EN', - 'PCI_EXP_DEVCTL2_OBFF_WAKE_EN', 'PCI_EXP_DEVCTL_AUX_PME', - 'PCI_EXP_DEVCTL_BCR_FLR', 'PCI_EXP_DEVCTL_CERE', - 'PCI_EXP_DEVCTL_EXT_TAG', 'PCI_EXP_DEVCTL_FERE', - 'PCI_EXP_DEVCTL_NFERE', 'PCI_EXP_DEVCTL_NOSNOOP_EN', - 'PCI_EXP_DEVCTL_PAYLOAD', 'PCI_EXP_DEVCTL_PAYLOAD_1024B', - 'PCI_EXP_DEVCTL_PAYLOAD_128B', 'PCI_EXP_DEVCTL_PAYLOAD_2048B', - 'PCI_EXP_DEVCTL_PAYLOAD_256B', 'PCI_EXP_DEVCTL_PAYLOAD_4096B', - 'PCI_EXP_DEVCTL_PAYLOAD_512B', 'PCI_EXP_DEVCTL_PHANTOM', - 'PCI_EXP_DEVCTL_READRQ', 'PCI_EXP_DEVCTL_READRQ_1024B', - 'PCI_EXP_DEVCTL_READRQ_128B', 'PCI_EXP_DEVCTL_READRQ_2048B', - 'PCI_EXP_DEVCTL_READRQ_256B', 'PCI_EXP_DEVCTL_READRQ_4096B', - 'PCI_EXP_DEVCTL_READRQ_512B', 'PCI_EXP_DEVCTL_RELAX_EN', - 'PCI_EXP_DEVCTL_URRE', 'PCI_EXP_DEVSTA', 'PCI_EXP_DEVSTA2', - 'PCI_EXP_DEVSTA_AUXPD', 'PCI_EXP_DEVSTA_CED', - 'PCI_EXP_DEVSTA_FED', 'PCI_EXP_DEVSTA_NFED', - 'PCI_EXP_DEVSTA_TRPND', 'PCI_EXP_DEVSTA_URD', 'PCI_EXP_DPC_CAP', - 'PCI_EXP_DPC_CAP_DL_ACTIVE', 'PCI_EXP_DPC_CAP_POISONED_TLP', - 'PCI_EXP_DPC_CAP_RP_EXT', 'PCI_EXP_DPC_CAP_SW_TRIGGER', - 'PCI_EXP_DPC_CTL', 'PCI_EXP_DPC_CTL_EN_FATAL', - 'PCI_EXP_DPC_CTL_EN_NONFATAL', 'PCI_EXP_DPC_CTL_INT_EN', - 'PCI_EXP_DPC_IRQ', 'PCI_EXP_DPC_RP_BUSY', - 'PCI_EXP_DPC_RP_PIO_EXCEPTION', 'PCI_EXP_DPC_RP_PIO_HEADER_LOG', - 'PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG', 'PCI_EXP_DPC_RP_PIO_LOG_SIZE', - 'PCI_EXP_DPC_RP_PIO_MASK', 'PCI_EXP_DPC_RP_PIO_SEVERITY', - 'PCI_EXP_DPC_RP_PIO_STATUS', 'PCI_EXP_DPC_RP_PIO_SYSERROR', - 'PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG', 'PCI_EXP_DPC_SOURCE_ID', - 'PCI_EXP_DPC_STATUS', 'PCI_EXP_DPC_STATUS_INTERRUPT', - 'PCI_EXP_DPC_STATUS_TRIGGER', 'PCI_EXP_DPC_STATUS_TRIGGER_RSN', - 'PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT', 'PCI_EXP_FLAGS', - 'PCI_EXP_FLAGS_IRQ', 'PCI_EXP_FLAGS_SLOT', 'PCI_EXP_FLAGS_TYPE', - 'PCI_EXP_FLAGS_VERS', 'PCI_EXP_LNKCAP', 'PCI_EXP_LNKCAP2', - 'PCI_EXP_LNKCAP2_CROSSLINK', 'PCI_EXP_LNKCAP2_SLS_16_0GB', - 'PCI_EXP_LNKCAP2_SLS_2_5GB', 'PCI_EXP_LNKCAP2_SLS_32_0GB', - 'PCI_EXP_LNKCAP2_SLS_5_0GB', 'PCI_EXP_LNKCAP2_SLS_64_0GB', - 'PCI_EXP_LNKCAP2_SLS_8_0GB', 'PCI_EXP_LNKCAP_ASPMS', - 'PCI_EXP_LNKCAP_ASPM_L0S', 'PCI_EXP_LNKCAP_ASPM_L1', - 'PCI_EXP_LNKCAP_CLKPM', 'PCI_EXP_LNKCAP_DLLLARC', - 'PCI_EXP_LNKCAP_L0SEL', 'PCI_EXP_LNKCAP_L1EL', - 'PCI_EXP_LNKCAP_LBNC', 'PCI_EXP_LNKCAP_MLW', 'PCI_EXP_LNKCAP_PN', - 'PCI_EXP_LNKCAP_SDERC', 'PCI_EXP_LNKCAP_SLS', - 'PCI_EXP_LNKCAP_SLS_16_0GB', 'PCI_EXP_LNKCAP_SLS_2_5GB', - 'PCI_EXP_LNKCAP_SLS_32_0GB', 'PCI_EXP_LNKCAP_SLS_5_0GB', - 'PCI_EXP_LNKCAP_SLS_64_0GB', 'PCI_EXP_LNKCAP_SLS_8_0GB', - 'PCI_EXP_LNKCTL', 'PCI_EXP_LNKCTL2', 'PCI_EXP_LNKCTL2_ENTER_COMP', - 'PCI_EXP_LNKCTL2_HASD', 'PCI_EXP_LNKCTL2_TLS', - 'PCI_EXP_LNKCTL2_TLS_16_0GT', 'PCI_EXP_LNKCTL2_TLS_2_5GT', - 'PCI_EXP_LNKCTL2_TLS_32_0GT', 'PCI_EXP_LNKCTL2_TLS_5_0GT', - 'PCI_EXP_LNKCTL2_TLS_64_0GT', 'PCI_EXP_LNKCTL2_TLS_8_0GT', - 'PCI_EXP_LNKCTL2_TX_MARGIN', 'PCI_EXP_LNKCTL_ASPMC', - 'PCI_EXP_LNKCTL_ASPM_L0S', 'PCI_EXP_LNKCTL_ASPM_L1', - 'PCI_EXP_LNKCTL_CCC', 'PCI_EXP_LNKCTL_CLKREQ_EN', - 'PCI_EXP_LNKCTL_ES', 'PCI_EXP_LNKCTL_HAWD', - 'PCI_EXP_LNKCTL_LABIE', 'PCI_EXP_LNKCTL_LBMIE', - 'PCI_EXP_LNKCTL_LD', 'PCI_EXP_LNKCTL_RCB', 'PCI_EXP_LNKCTL_RL', - 'PCI_EXP_LNKSTA', 'PCI_EXP_LNKSTA2', 'PCI_EXP_LNKSTA_CLS', - 'PCI_EXP_LNKSTA_CLS_16_0GB', 'PCI_EXP_LNKSTA_CLS_2_5GB', - 'PCI_EXP_LNKSTA_CLS_32_0GB', 'PCI_EXP_LNKSTA_CLS_5_0GB', - 'PCI_EXP_LNKSTA_CLS_64_0GB', 'PCI_EXP_LNKSTA_CLS_8_0GB', - 'PCI_EXP_LNKSTA_DLLLA', 'PCI_EXP_LNKSTA_LABS', - 'PCI_EXP_LNKSTA_LBMS', 'PCI_EXP_LNKSTA_LT', 'PCI_EXP_LNKSTA_NLW', - 'PCI_EXP_LNKSTA_NLW_SHIFT', 'PCI_EXP_LNKSTA_NLW_X1', - 'PCI_EXP_LNKSTA_NLW_X2', 'PCI_EXP_LNKSTA_NLW_X4', - 'PCI_EXP_LNKSTA_NLW_X8', 'PCI_EXP_LNKSTA_SLC', 'PCI_EXP_RTCAP', - 'PCI_EXP_RTCAP_CRSVIS', 'PCI_EXP_RTCTL', 'PCI_EXP_RTCTL_CRSSVE', - 'PCI_EXP_RTCTL_PMEIE', 'PCI_EXP_RTCTL_SECEE', - 'PCI_EXP_RTCTL_SEFEE', 'PCI_EXP_RTCTL_SENFEE', 'PCI_EXP_RTSTA', - 'PCI_EXP_RTSTA_PENDING', 'PCI_EXP_RTSTA_PME', 'PCI_EXP_SLTCAP', - 'PCI_EXP_SLTCAP2', 'PCI_EXP_SLTCAP2_IBPD', 'PCI_EXP_SLTCAP_ABP', - 'PCI_EXP_SLTCAP_AIP', 'PCI_EXP_SLTCAP_EIP', 'PCI_EXP_SLTCAP_HPC', - 'PCI_EXP_SLTCAP_HPS', 'PCI_EXP_SLTCAP_MRLSP', - 'PCI_EXP_SLTCAP_NCCS', 'PCI_EXP_SLTCAP_PCP', 'PCI_EXP_SLTCAP_PIP', - 'PCI_EXP_SLTCAP_PSN', 'PCI_EXP_SLTCAP_SPLS', - 'PCI_EXP_SLTCAP_SPLV', 'PCI_EXP_SLTCTL', 'PCI_EXP_SLTCTL2', - 'PCI_EXP_SLTCTL_ABPE', 'PCI_EXP_SLTCTL_AIC', - 'PCI_EXP_SLTCTL_ATTN_IND_BLINK', 'PCI_EXP_SLTCTL_ATTN_IND_OFF', - 'PCI_EXP_SLTCTL_ATTN_IND_ON', 'PCI_EXP_SLTCTL_ATTN_IND_SHIFT', - 'PCI_EXP_SLTCTL_CCIE', 'PCI_EXP_SLTCTL_DLLSCE', - 'PCI_EXP_SLTCTL_EIC', 'PCI_EXP_SLTCTL_HPIE', - 'PCI_EXP_SLTCTL_IBPD_DISABLE', 'PCI_EXP_SLTCTL_MRLSCE', - 'PCI_EXP_SLTCTL_PCC', 'PCI_EXP_SLTCTL_PDCE', - 'PCI_EXP_SLTCTL_PFDE', 'PCI_EXP_SLTCTL_PIC', - 'PCI_EXP_SLTCTL_PWR_IND_BLINK', 'PCI_EXP_SLTCTL_PWR_IND_OFF', - 'PCI_EXP_SLTCTL_PWR_IND_ON', 'PCI_EXP_SLTCTL_PWR_OFF', - 'PCI_EXP_SLTCTL_PWR_ON', 'PCI_EXP_SLTSTA', 'PCI_EXP_SLTSTA2', - 'PCI_EXP_SLTSTA_ABP', 'PCI_EXP_SLTSTA_CC', 'PCI_EXP_SLTSTA_DLLSC', - 'PCI_EXP_SLTSTA_EIS', 'PCI_EXP_SLTSTA_MRLSC', - 'PCI_EXP_SLTSTA_MRLSS', 'PCI_EXP_SLTSTA_PDC', - 'PCI_EXP_SLTSTA_PDS', 'PCI_EXP_SLTSTA_PFD', - 'PCI_EXP_TYPE_DOWNSTREAM', 'PCI_EXP_TYPE_ENDPOINT', - 'PCI_EXP_TYPE_LEG_END', 'PCI_EXP_TYPE_PCIE_BRIDGE', - 'PCI_EXP_TYPE_PCI_BRIDGE', 'PCI_EXP_TYPE_RC_EC', - 'PCI_EXP_TYPE_RC_END', 'PCI_EXP_TYPE_ROOT_PORT', - 'PCI_EXP_TYPE_UPSTREAM', 'PCI_EXT_CAP_ARI_SIZEOF', - 'PCI_EXT_CAP_ATS_SIZEOF', 'PCI_EXT_CAP_DSN_SIZEOF', - 'PCI_EXT_CAP_ID_ACS', 'PCI_EXT_CAP_ID_AMD_XXX', - 'PCI_EXT_CAP_ID_ARI', 'PCI_EXT_CAP_ID_ATS', 'PCI_EXT_CAP_ID_CAC', - 'PCI_EXT_CAP_ID_DLF', 'PCI_EXT_CAP_ID_DPA', 'PCI_EXT_CAP_ID_DPC', - 'PCI_EXT_CAP_ID_DSN', 'PCI_EXT_CAP_ID_DVSEC', - 'PCI_EXT_CAP_ID_ERR', 'PCI_EXT_CAP_ID_L1SS', 'PCI_EXT_CAP_ID_LTR', - 'PCI_EXT_CAP_ID_MAX', 'PCI_EXT_CAP_ID_MCAST', - 'PCI_EXT_CAP_ID_MFVC', 'PCI_EXT_CAP_ID_MRIOV', - 'PCI_EXT_CAP_ID_PASID', 'PCI_EXT_CAP_ID_PL_16GT', - 'PCI_EXT_CAP_ID_PMUX', 'PCI_EXT_CAP_ID_PRI', 'PCI_EXT_CAP_ID_PTM', - 'PCI_EXT_CAP_ID_PWR', 'PCI_EXT_CAP_ID_RCEC', - 'PCI_EXT_CAP_ID_RCILC', 'PCI_EXT_CAP_ID_RCLD', - 'PCI_EXT_CAP_ID_RCRB', 'PCI_EXT_CAP_ID_REBAR', - 'PCI_EXT_CAP_ID_SECPCI', 'PCI_EXT_CAP_ID_SRIOV', - 'PCI_EXT_CAP_ID_TPH', 'PCI_EXT_CAP_ID_VC', 'PCI_EXT_CAP_ID_VC9', - 'PCI_EXT_CAP_ID_VNDR', 'PCI_EXT_CAP_LTR_SIZEOF', - 'PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF', 'PCI_EXT_CAP_PASID_SIZEOF', - 'PCI_EXT_CAP_PRI_SIZEOF', 'PCI_EXT_CAP_PWR_SIZEOF', - 'PCI_EXT_CAP_SRIOV_SIZEOF', 'PCI_HEADER_TYPE', - 'PCI_HEADER_TYPE_BRIDGE', 'PCI_HEADER_TYPE_CARDBUS', - 'PCI_HEADER_TYPE_MASK', 'PCI_HEADER_TYPE_NORMAL', - 'PCI_INTERRUPT_LINE', 'PCI_INTERRUPT_PIN', 'PCI_IO_1K_RANGE_MASK', - 'PCI_IO_BASE', 'PCI_IO_BASE_UPPER16', 'PCI_IO_LIMIT', - 'PCI_IO_LIMIT_UPPER16', 'PCI_IO_RANGE_MASK', - 'PCI_IO_RANGE_TYPE_16', 'PCI_IO_RANGE_TYPE_32', - 'PCI_IO_RANGE_TYPE_MASK', 'PCI_L1SS_CAP', - 'PCI_L1SS_CAP_ASPM_L1_1', 'PCI_L1SS_CAP_ASPM_L1_2', - 'PCI_L1SS_CAP_CM_RESTORE_TIME', 'PCI_L1SS_CAP_L1_PM_SS', - 'PCI_L1SS_CAP_PCIPM_L1_1', 'PCI_L1SS_CAP_PCIPM_L1_2', - 'PCI_L1SS_CAP_P_PWR_ON_SCALE', 'PCI_L1SS_CAP_P_PWR_ON_VALUE', - 'PCI_L1SS_CTL1', 'PCI_L1SS_CTL1_ASPM_L1_1', - 'PCI_L1SS_CTL1_ASPM_L1_2', 'PCI_L1SS_CTL1_CM_RESTORE_TIME', - 'PCI_L1SS_CTL1_L1SS_MASK', 'PCI_L1SS_CTL1_L1_2_MASK', - 'PCI_L1SS_CTL1_LTR_L12_TH_SCALE', - 'PCI_L1SS_CTL1_LTR_L12_TH_VALUE', 'PCI_L1SS_CTL1_PCIPM_L1_1', - 'PCI_L1SS_CTL1_PCIPM_L1_2', 'PCI_L1SS_CTL2', 'PCI_LATENCY_TIMER', - 'PCI_LTR_MAX_NOSNOOP_LAT', 'PCI_LTR_MAX_SNOOP_LAT', - 'PCI_LTR_SCALE_MASK', 'PCI_LTR_SCALE_SHIFT', 'PCI_LTR_VALUE_MASK', - 'PCI_MAX_LAT', 'PCI_MEMORY_BASE', 'PCI_MEMORY_LIMIT', - 'PCI_MEMORY_RANGE_MASK', 'PCI_MEMORY_RANGE_TYPE_MASK', - 'PCI_MIN_GNT', 'PCI_MSIX_ENTRY_CTRL_MASKBIT', - 'PCI_MSIX_ENTRY_DATA', 'PCI_MSIX_ENTRY_LOWER_ADDR', - 'PCI_MSIX_ENTRY_SIZE', 'PCI_MSIX_ENTRY_UPPER_ADDR', - 'PCI_MSIX_ENTRY_VECTOR_CTRL', 'PCI_MSIX_FLAGS', - 'PCI_MSIX_FLAGS_BIRMASK', 'PCI_MSIX_FLAGS_ENABLE', - 'PCI_MSIX_FLAGS_MASKALL', 'PCI_MSIX_FLAGS_QSIZE', 'PCI_MSIX_PBA', - 'PCI_MSIX_PBA_BIR', 'PCI_MSIX_PBA_OFFSET', 'PCI_MSIX_TABLE', - 'PCI_MSIX_TABLE_BIR', 'PCI_MSIX_TABLE_OFFSET', - 'PCI_MSI_ADDRESS_HI', 'PCI_MSI_ADDRESS_LO', 'PCI_MSI_DATA_32', - 'PCI_MSI_DATA_64', 'PCI_MSI_FLAGS', 'PCI_MSI_FLAGS_64BIT', - 'PCI_MSI_FLAGS_ENABLE', 'PCI_MSI_FLAGS_MASKBIT', - 'PCI_MSI_FLAGS_QMASK', 'PCI_MSI_FLAGS_QSIZE', 'PCI_MSI_MASK_32', - 'PCI_MSI_MASK_64', 'PCI_MSI_PENDING_32', 'PCI_MSI_PENDING_64', - 'PCI_MSI_RFU', 'PCI_PASID_CAP', 'PCI_PASID_CAP_EXEC', - 'PCI_PASID_CAP_PRIV', 'PCI_PASID_CTRL', 'PCI_PASID_CTRL_ENABLE', - 'PCI_PASID_CTRL_EXEC', 'PCI_PASID_CTRL_PRIV', - 'PCI_PL_16GT_LE_CTRL', 'PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK', - 'PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK', - 'PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT', 'PCI_PM_BPCC_ENABLE', - 'PCI_PM_CAP_AUX_POWER', 'PCI_PM_CAP_D1', 'PCI_PM_CAP_D2', - 'PCI_PM_CAP_DSI', 'PCI_PM_CAP_PME', 'PCI_PM_CAP_PME_CLOCK', - 'PCI_PM_CAP_PME_D0', 'PCI_PM_CAP_PME_D1', 'PCI_PM_CAP_PME_D2', - 'PCI_PM_CAP_PME_D3cold', 'PCI_PM_CAP_PME_D3hot', - 'PCI_PM_CAP_PME_MASK', 'PCI_PM_CAP_PME_SHIFT', - 'PCI_PM_CAP_RESERVED', 'PCI_PM_CAP_VER_MASK', 'PCI_PM_CTRL', - 'PCI_PM_CTRL_DATA_SCALE_MASK', 'PCI_PM_CTRL_DATA_SEL_MASK', - 'PCI_PM_CTRL_NO_SOFT_RESET', 'PCI_PM_CTRL_PME_ENABLE', - 'PCI_PM_CTRL_PME_STATUS', 'PCI_PM_CTRL_STATE_MASK', - 'PCI_PM_DATA_REGISTER', 'PCI_PM_PMC', 'PCI_PM_PPB_B2_B3', - 'PCI_PM_PPB_EXTENSIONS', 'PCI_PM_SIZEOF', 'PCI_PREF_BASE_UPPER32', - 'PCI_PREF_LIMIT_UPPER32', 'PCI_PREF_MEMORY_BASE', - 'PCI_PREF_MEMORY_LIMIT', 'PCI_PREF_RANGE_MASK', - 'PCI_PREF_RANGE_TYPE_32', 'PCI_PREF_RANGE_TYPE_64', - 'PCI_PREF_RANGE_TYPE_MASK', 'PCI_PRIMARY_BUS', - 'PCI_PRI_ALLOC_REQ', 'PCI_PRI_CTRL', 'PCI_PRI_CTRL_ENABLE', - 'PCI_PRI_CTRL_RESET', 'PCI_PRI_MAX_REQ', 'PCI_PRI_STATUS', - 'PCI_PRI_STATUS_PASID', 'PCI_PRI_STATUS_RF', - 'PCI_PRI_STATUS_STOPPED', 'PCI_PRI_STATUS_UPRGI', 'PCI_PTM_CAP', - 'PCI_PTM_CAP_REQ', 'PCI_PTM_CAP_ROOT', 'PCI_PTM_CTRL', - 'PCI_PTM_CTRL_ENABLE', 'PCI_PTM_CTRL_ROOT', - 'PCI_PTM_GRANULARITY_MASK', 'PCI_PWR_CAP', 'PCI_PWR_DATA', - 'PCI_PWR_DSR', 'PCI_RCEC_BUSN', 'PCI_RCEC_BUSN_REG_VER', - 'PCI_RCEC_RCIEP_BITMAP', 'PCI_REBAR_CAP', 'PCI_REBAR_CAP_SIZES', - 'PCI_REBAR_CTRL', 'PCI_REBAR_CTRL_BAR_IDX', - 'PCI_REBAR_CTRL_BAR_SHIFT', 'PCI_REBAR_CTRL_BAR_SIZE', - 'PCI_REBAR_CTRL_NBAR_MASK', 'PCI_REBAR_CTRL_NBAR_SHIFT', - 'PCI_REVISION_ID', 'PCI_ROM_ADDRESS', 'PCI_ROM_ADDRESS1', - 'PCI_ROM_ADDRESS_ENABLE', 'PCI_ROM_ADDRESS_MASK', 'PCI_SATA_REGS', - 'PCI_SATA_REGS_INLINE', 'PCI_SATA_REGS_MASK', - 'PCI_SATA_SIZEOF_LONG', 'PCI_SATA_SIZEOF_SHORT', - 'PCI_SECONDARY_BUS', 'PCI_SEC_LATENCY_TIMER', 'PCI_SEC_STATUS', - 'PCI_SID_CHASSIS_NR', 'PCI_SID_ESR', 'PCI_SID_ESR_FIC', - 'PCI_SID_ESR_NSLOTS', 'PCI_SRIOV_BAR', 'PCI_SRIOV_CAP', - 'PCI_SRIOV_CAP_VFM', 'PCI_SRIOV_CTRL', 'PCI_SRIOV_CTRL_ARI', - 'PCI_SRIOV_CTRL_INTR', 'PCI_SRIOV_CTRL_MSE', 'PCI_SRIOV_CTRL_VFE', - 'PCI_SRIOV_CTRL_VFM', 'PCI_SRIOV_FUNC_LINK', - 'PCI_SRIOV_INITIAL_VF', 'PCI_SRIOV_NUM_BARS', 'PCI_SRIOV_NUM_VF', - 'PCI_SRIOV_STATUS', 'PCI_SRIOV_STATUS_VFM', - 'PCI_SRIOV_SUP_PGSIZE', 'PCI_SRIOV_SYS_PGSIZE', - 'PCI_SRIOV_TOTAL_VF', 'PCI_SRIOV_VFM', 'PCI_SRIOV_VFM_AV', - 'PCI_SRIOV_VFM_MI', 'PCI_SRIOV_VFM_MO', 'PCI_SRIOV_VFM_UA', - 'PCI_SRIOV_VF_DID', 'PCI_SRIOV_VF_OFFSET', 'PCI_SRIOV_VF_STRIDE', - 'PCI_SSVID_DEVICE_ID', 'PCI_SSVID_VENDOR_ID', 'PCI_STATUS', - 'PCI_STATUS_66MHZ', 'PCI_STATUS_CAP_LIST', - 'PCI_STATUS_DETECTED_PARITY', 'PCI_STATUS_DEVSEL_FAST', - 'PCI_STATUS_DEVSEL_MASK', 'PCI_STATUS_DEVSEL_MEDIUM', - 'PCI_STATUS_DEVSEL_SLOW', 'PCI_STATUS_FAST_BACK', - 'PCI_STATUS_IMM_READY', 'PCI_STATUS_INTERRUPT', - 'PCI_STATUS_PARITY', 'PCI_STATUS_REC_MASTER_ABORT', - 'PCI_STATUS_REC_TARGET_ABORT', 'PCI_STATUS_SIG_SYSTEM_ERROR', - 'PCI_STATUS_SIG_TARGET_ABORT', 'PCI_STATUS_UDF', - 'PCI_STD_HEADER_SIZEOF', 'PCI_STD_NUM_BARS', - 'PCI_SUBORDINATE_BUS', 'PCI_SUBSYSTEM_ID', - 'PCI_SUBSYSTEM_VENDOR_ID', 'PCI_TPH_BASE_SIZEOF', 'PCI_TPH_CAP', - 'PCI_TPH_CAP_LOC_MASK', 'PCI_TPH_CAP_ST_MASK', - 'PCI_TPH_CAP_ST_SHIFT', 'PCI_TPH_LOC_CAP', 'PCI_TPH_LOC_MSIX', - 'PCI_TPH_LOC_NONE', 'PCI_VC_CAP1_ARB_SIZE', 'PCI_VC_CAP1_EVCC', - 'PCI_VC_CAP1_LPEVCC', 'PCI_VC_CAP2_128_PHASE', - 'PCI_VC_CAP2_32_PHASE', 'PCI_VC_CAP2_64_PHASE', - 'PCI_VC_CAP2_ARB_OFF', 'PCI_VC_PORT_CAP1', 'PCI_VC_PORT_CAP2', - 'PCI_VC_PORT_CTRL', 'PCI_VC_PORT_CTRL_LOAD_TABLE', - 'PCI_VC_PORT_STATUS', 'PCI_VC_PORT_STATUS_TABLE', - 'PCI_VC_RES_CAP', 'PCI_VC_RES_CAP_128_PHASE', - 'PCI_VC_RES_CAP_128_PHASE_TB', 'PCI_VC_RES_CAP_256_PHASE', - 'PCI_VC_RES_CAP_32_PHASE', 'PCI_VC_RES_CAP_64_PHASE', - 'PCI_VC_RES_CAP_ARB_OFF', 'PCI_VC_RES_CTRL', - 'PCI_VC_RES_CTRL_ARB_SELECT', 'PCI_VC_RES_CTRL_ENABLE', - 'PCI_VC_RES_CTRL_ID', 'PCI_VC_RES_CTRL_LOAD_TABLE', - 'PCI_VC_RES_STATUS', 'PCI_VC_RES_STATUS_NEGO', - 'PCI_VC_RES_STATUS_TABLE', 'PCI_VENDOR_ID', 'PCI_VNDR_HEADER', - 'PCI_VPD_ADDR', 'PCI_VPD_ADDR_F', 'PCI_VPD_ADDR_MASK', - 'PCI_VPD_DATA', 'PCI_VSEC_HDR', 'PCI_VSEC_HDR_LEN_SHIFT', - 'PCI_X_BRIDGE_SSTATUS', 'PCI_X_BRIDGE_STATUS', 'PCI_X_CMD', - 'PCI_X_CMD_DPERR_E', 'PCI_X_CMD_ERO', 'PCI_X_CMD_MAX_READ', - 'PCI_X_CMD_MAX_SPLIT', 'PCI_X_CMD_READ_1K', 'PCI_X_CMD_READ_2K', - 'PCI_X_CMD_READ_4K', 'PCI_X_CMD_READ_512', 'PCI_X_CMD_SPLIT_1', - 'PCI_X_CMD_SPLIT_12', 'PCI_X_CMD_SPLIT_16', 'PCI_X_CMD_SPLIT_2', - 'PCI_X_CMD_SPLIT_3', 'PCI_X_CMD_SPLIT_32', 'PCI_X_CMD_SPLIT_4', - 'PCI_X_CMD_SPLIT_8', 'PCI_X_ECC_CSR', 'PCI_X_SSTATUS_133MHZ', - 'PCI_X_SSTATUS_266MHZ', 'PCI_X_SSTATUS_533MHZ', - 'PCI_X_SSTATUS_64BIT', 'PCI_X_SSTATUS_FREQ', 'PCI_X_SSTATUS_V1', - 'PCI_X_SSTATUS_V2', 'PCI_X_SSTATUS_VERS', 'PCI_X_STATUS', - 'PCI_X_STATUS_133MHZ', 'PCI_X_STATUS_266MHZ', - 'PCI_X_STATUS_533MHZ', 'PCI_X_STATUS_64BIT', 'PCI_X_STATUS_BUS', - 'PCI_X_STATUS_COMPLEX', 'PCI_X_STATUS_DEVFN', - 'PCI_X_STATUS_MAX_CUM', 'PCI_X_STATUS_MAX_READ', - 'PCI_X_STATUS_MAX_SPLIT', 'PCI_X_STATUS_SPL_DISC', - 'PCI_X_STATUS_SPL_ERR', 'PCI_X_STATUS_UNX_SPL'] +PCI_CFG_SPACE_SIZE = 256 +PCI_CFG_SPACE_EXP_SIZE = 4096 +PCI_STD_HEADER_SIZEOF = 64 +PCI_STD_NUM_BARS = 6 +PCI_VENDOR_ID = 0x00 +PCI_DEVICE_ID = 0x02 +PCI_COMMAND = 0x04 +PCI_COMMAND_IO = 0x1 +PCI_COMMAND_MEMORY = 0x2 +PCI_COMMAND_MASTER = 0x4 +PCI_COMMAND_SPECIAL = 0x8 +PCI_COMMAND_INVALIDATE = 0x10 +PCI_COMMAND_VGA_PALETTE = 0x20 +PCI_COMMAND_PARITY = 0x40 +PCI_COMMAND_WAIT = 0x80 +PCI_COMMAND_SERR = 0x100 +PCI_COMMAND_FAST_BACK = 0x200 +PCI_COMMAND_INTX_DISABLE = 0x400 +PCI_STATUS = 0x06 +PCI_STATUS_IMM_READY = 0x01 +PCI_STATUS_INTERRUPT = 0x08 +PCI_STATUS_CAP_LIST = 0x10 +PCI_STATUS_66MHZ = 0x20 +PCI_STATUS_UDF = 0x40 +PCI_STATUS_FAST_BACK = 0x80 +PCI_STATUS_PARITY = 0x100 +PCI_STATUS_DEVSEL_MASK = 0x600 +PCI_STATUS_DEVSEL_FAST = 0x000 +PCI_STATUS_DEVSEL_MEDIUM = 0x200 +PCI_STATUS_DEVSEL_SLOW = 0x400 +PCI_STATUS_SIG_TARGET_ABORT = 0x800 +PCI_STATUS_REC_TARGET_ABORT = 0x1000 +PCI_STATUS_REC_MASTER_ABORT = 0x2000 +PCI_STATUS_SIG_SYSTEM_ERROR = 0x4000 +PCI_STATUS_DETECTED_PARITY = 0x8000 +PCI_CLASS_REVISION = 0x08 +PCI_REVISION_ID = 0x08 +PCI_CLASS_PROG = 0x09 +PCI_CLASS_DEVICE = 0x0a +PCI_CACHE_LINE_SIZE = 0x0c +PCI_LATENCY_TIMER = 0x0d +PCI_HEADER_TYPE = 0x0e +PCI_HEADER_TYPE_MASK = 0x7f +PCI_HEADER_TYPE_NORMAL = 0 +PCI_HEADER_TYPE_BRIDGE = 1 +PCI_HEADER_TYPE_CARDBUS = 2 +PCI_HEADER_TYPE_MFD = 0x80 +PCI_BIST = 0x0f +PCI_BIST_CODE_MASK = 0x0f +PCI_BIST_START = 0x40 +PCI_BIST_CAPABLE = 0x80 +PCI_BASE_ADDRESS_0 = 0x10 +PCI_BASE_ADDRESS_1 = 0x14 +PCI_BASE_ADDRESS_2 = 0x18 +PCI_BASE_ADDRESS_3 = 0x1c +PCI_BASE_ADDRESS_4 = 0x20 +PCI_BASE_ADDRESS_5 = 0x24 +PCI_BASE_ADDRESS_SPACE = 0x01 +PCI_BASE_ADDRESS_SPACE_IO = 0x01 +PCI_BASE_ADDRESS_SPACE_MEMORY = 0x00 +PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x06 +PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x00 +PCI_BASE_ADDRESS_MEM_TYPE_1M = 0x02 +PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x04 +PCI_BASE_ADDRESS_MEM_PREFETCH = 0x08 +PCI_BASE_ADDRESS_MEM_MASK = (~0x0f) +PCI_BASE_ADDRESS_IO_MASK = (~0x03) +PCI_CARDBUS_CIS = 0x28 +PCI_SUBSYSTEM_VENDOR_ID = 0x2c +PCI_SUBSYSTEM_ID = 0x2e +PCI_ROM_ADDRESS = 0x30 +PCI_ROM_ADDRESS_ENABLE = 0x01 +PCI_ROM_ADDRESS_MASK = (~0x7ff) +PCI_CAPABILITY_LIST = 0x34 +PCI_INTERRUPT_LINE = 0x3c +PCI_INTERRUPT_PIN = 0x3d +PCI_MIN_GNT = 0x3e +PCI_MAX_LAT = 0x3f +PCI_PRIMARY_BUS = 0x18 +PCI_SECONDARY_BUS = 0x19 +PCI_SUBORDINATE_BUS = 0x1a +PCI_SEC_LATENCY_TIMER = 0x1b +PCI_IO_BASE = 0x1c +PCI_IO_LIMIT = 0x1d +PCI_IO_RANGE_TYPE_MASK = 0x0f +PCI_IO_RANGE_TYPE_16 = 0x00 +PCI_IO_RANGE_TYPE_32 = 0x01 +PCI_IO_RANGE_MASK = (~0x0f) +PCI_IO_1K_RANGE_MASK = (~0x03) +PCI_SEC_STATUS = 0x1e +PCI_MEMORY_BASE = 0x20 +PCI_MEMORY_LIMIT = 0x22 +PCI_MEMORY_RANGE_TYPE_MASK = 0x0f +PCI_MEMORY_RANGE_MASK = (~0x0f) +PCI_PREF_MEMORY_BASE = 0x24 +PCI_PREF_MEMORY_LIMIT = 0x26 +PCI_PREF_RANGE_TYPE_MASK = 0x0f +PCI_PREF_RANGE_TYPE_32 = 0x00 +PCI_PREF_RANGE_TYPE_64 = 0x01 +PCI_PREF_RANGE_MASK = (~0x0f) +PCI_PREF_BASE_UPPER32 = 0x28 +PCI_PREF_LIMIT_UPPER32 = 0x2c +PCI_IO_BASE_UPPER16 = 0x30 +PCI_IO_LIMIT_UPPER16 = 0x32 +PCI_ROM_ADDRESS1 = 0x38 +PCI_BRIDGE_CONTROL = 0x3e +PCI_BRIDGE_CTL_PARITY = 0x01 +PCI_BRIDGE_CTL_SERR = 0x02 +PCI_BRIDGE_CTL_ISA = 0x04 +PCI_BRIDGE_CTL_VGA = 0x08 +PCI_BRIDGE_CTL_MASTER_ABORT = 0x20 +PCI_BRIDGE_CTL_BUS_RESET = 0x40 +PCI_BRIDGE_CTL_FAST_BACK = 0x80 +PCI_CB_CAPABILITY_LIST = 0x14 +PCI_CB_SEC_STATUS = 0x16 +PCI_CB_PRIMARY_BUS = 0x18 +PCI_CB_CARD_BUS = 0x19 +PCI_CB_SUBORDINATE_BUS = 0x1a +PCI_CB_LATENCY_TIMER = 0x1b +PCI_CB_MEMORY_BASE_0 = 0x1c +PCI_CB_MEMORY_LIMIT_0 = 0x20 +PCI_CB_MEMORY_BASE_1 = 0x24 +PCI_CB_MEMORY_LIMIT_1 = 0x28 +PCI_CB_IO_BASE_0 = 0x2c +PCI_CB_IO_BASE_0_HI = 0x2e +PCI_CB_IO_LIMIT_0 = 0x30 +PCI_CB_IO_LIMIT_0_HI = 0x32 +PCI_CB_IO_BASE_1 = 0x34 +PCI_CB_IO_BASE_1_HI = 0x36 +PCI_CB_IO_LIMIT_1 = 0x38 +PCI_CB_IO_LIMIT_1_HI = 0x3a +PCI_CB_IO_RANGE_MASK = (~0x03) +PCI_CB_BRIDGE_CONTROL = 0x3e +PCI_CB_BRIDGE_CTL_PARITY = 0x01 +PCI_CB_BRIDGE_CTL_SERR = 0x02 +PCI_CB_BRIDGE_CTL_ISA = 0x04 +PCI_CB_BRIDGE_CTL_VGA = 0x08 +PCI_CB_BRIDGE_CTL_MASTER_ABORT = 0x20 +PCI_CB_BRIDGE_CTL_CB_RESET = 0x40 +PCI_CB_BRIDGE_CTL_16BIT_INT = 0x80 +PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 = 0x100 +PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 = 0x200 +PCI_CB_BRIDGE_CTL_POST_WRITES = 0x400 +PCI_CB_SUBSYSTEM_VENDOR_ID = 0x40 +PCI_CB_SUBSYSTEM_ID = 0x42 +PCI_CB_LEGACY_MODE_BASE = 0x44 +PCI_CAP_LIST_ID = 0 +PCI_CAP_ID_PM = 0x01 +PCI_CAP_ID_AGP = 0x02 +PCI_CAP_ID_VPD = 0x03 +PCI_CAP_ID_SLOTID = 0x04 +PCI_CAP_ID_MSI = 0x05 +PCI_CAP_ID_CHSWP = 0x06 +PCI_CAP_ID_PCIX = 0x07 +PCI_CAP_ID_HT = 0x08 +PCI_CAP_ID_VNDR = 0x09 +PCI_CAP_ID_DBG = 0x0A +PCI_CAP_ID_CCRC = 0x0B +PCI_CAP_ID_SHPC = 0x0C +PCI_CAP_ID_SSVID = 0x0D +PCI_CAP_ID_AGP3 = 0x0E +PCI_CAP_ID_SECDEV = 0x0F +PCI_CAP_ID_EXP = 0x10 +PCI_CAP_ID_MSIX = 0x11 +PCI_CAP_ID_SATA = 0x12 +PCI_CAP_ID_AF = 0x13 +PCI_CAP_ID_EA = 0x14 +PCI_CAP_ID_MAX = PCI_CAP_ID_EA +PCI_CAP_LIST_NEXT = 1 +PCI_CAP_FLAGS = 2 +PCI_CAP_SIZEOF = 4 +PCI_PM_PMC = 2 +PCI_PM_CAP_VER_MASK = 0x0007 +PCI_PM_CAP_PME_CLOCK = 0x0008 +PCI_PM_CAP_RESERVED = 0x0010 +PCI_PM_CAP_DSI = 0x0020 +PCI_PM_CAP_AUX_POWER = 0x01C0 +PCI_PM_CAP_D1 = 0x0200 +PCI_PM_CAP_D2 = 0x0400 +PCI_PM_CAP_PME = 0x0800 +PCI_PM_CAP_PME_MASK = 0xF800 +PCI_PM_CAP_PME_D0 = 0x0800 +PCI_PM_CAP_PME_D1 = 0x1000 +PCI_PM_CAP_PME_D2 = 0x2000 +PCI_PM_CAP_PME_D3hot = 0x4000 +PCI_PM_CAP_PME_D3cold = 0x8000 +PCI_PM_CAP_PME_SHIFT = 11 +PCI_PM_CTRL = 4 +PCI_PM_CTRL_STATE_MASK = 0x0003 +PCI_PM_CTRL_NO_SOFT_RESET = 0x0008 +PCI_PM_CTRL_PME_ENABLE = 0x0100 +PCI_PM_CTRL_DATA_SEL_MASK = 0x1e00 +PCI_PM_CTRL_DATA_SCALE_MASK = 0x6000 +PCI_PM_CTRL_PME_STATUS = 0x8000 +PCI_PM_PPB_EXTENSIONS = 6 +PCI_PM_PPB_B2_B3 = 0x40 +PCI_PM_BPCC_ENABLE = 0x80 +PCI_PM_DATA_REGISTER = 7 +PCI_PM_SIZEOF = 8 +PCI_AGP_VERSION = 2 +PCI_AGP_RFU = 3 +PCI_AGP_STATUS = 4 +PCI_AGP_STATUS_RQ_MASK = 0xff000000 +PCI_AGP_STATUS_SBA = 0x0200 +PCI_AGP_STATUS_64BIT = 0x0020 +PCI_AGP_STATUS_FW = 0x0010 +PCI_AGP_STATUS_RATE4 = 0x0004 +PCI_AGP_STATUS_RATE2 = 0x0002 +PCI_AGP_STATUS_RATE1 = 0x0001 +PCI_AGP_COMMAND = 8 +PCI_AGP_COMMAND_RQ_MASK = 0xff000000 +PCI_AGP_COMMAND_SBA = 0x0200 +PCI_AGP_COMMAND_AGP = 0x0100 +PCI_AGP_COMMAND_64BIT = 0x0020 +PCI_AGP_COMMAND_FW = 0x0010 +PCI_AGP_COMMAND_RATE4 = 0x0004 +PCI_AGP_COMMAND_RATE2 = 0x0002 +PCI_AGP_COMMAND_RATE1 = 0x0001 +PCI_AGP_SIZEOF = 12 +PCI_VPD_ADDR = 2 +PCI_VPD_ADDR_MASK = 0x7fff +PCI_VPD_ADDR_F = 0x8000 +PCI_VPD_DATA = 4 +PCI_CAP_VPD_SIZEOF = 8 +PCI_SID_ESR = 2 +PCI_SID_ESR_NSLOTS = 0x1f +PCI_SID_ESR_FIC = 0x20 +PCI_SID_CHASSIS_NR = 3 +PCI_MSI_FLAGS = 0x02 +PCI_MSI_FLAGS_ENABLE = 0x0001 +PCI_MSI_FLAGS_QMASK = 0x000e +PCI_MSI_FLAGS_QSIZE = 0x0070 +PCI_MSI_FLAGS_64BIT = 0x0080 +PCI_MSI_FLAGS_MASKBIT = 0x0100 +PCI_MSI_RFU = 3 +PCI_MSI_ADDRESS_LO = 0x04 +PCI_MSI_ADDRESS_HI = 0x08 +PCI_MSI_DATA_32 = 0x08 +PCI_MSI_MASK_32 = 0x0c +PCI_MSI_PENDING_32 = 0x10 +PCI_MSI_DATA_64 = 0x0c +PCI_MSI_MASK_64 = 0x10 +PCI_MSI_PENDING_64 = 0x14 +PCI_MSIX_FLAGS = 2 +PCI_MSIX_FLAGS_QSIZE = 0x07FF +PCI_MSIX_FLAGS_MASKALL = 0x4000 +PCI_MSIX_FLAGS_ENABLE = 0x8000 +PCI_MSIX_TABLE = 4 +PCI_MSIX_TABLE_BIR = 0x00000007 +PCI_MSIX_TABLE_OFFSET = 0xfffffff8 +PCI_MSIX_PBA = 8 +PCI_MSIX_PBA_BIR = 0x00000007 +PCI_MSIX_PBA_OFFSET = 0xfffffff8 +PCI_MSIX_FLAGS_BIRMASK = PCI_MSIX_PBA_BIR +PCI_CAP_MSIX_SIZEOF = 12 +PCI_MSIX_ENTRY_SIZE = 16 +PCI_MSIX_ENTRY_LOWER_ADDR = 0x0 +PCI_MSIX_ENTRY_UPPER_ADDR = 0x4 +PCI_MSIX_ENTRY_DATA = 0x8 +PCI_MSIX_ENTRY_VECTOR_CTRL = 0xc +PCI_MSIX_ENTRY_CTRL_MASKBIT = 0x00000001 +PCI_CHSWP_CSR = 2 +PCI_CHSWP_DHA = 0x01 +PCI_CHSWP_EIM = 0x02 +PCI_CHSWP_PIE = 0x04 +PCI_CHSWP_LOO = 0x08 +PCI_CHSWP_PI = 0x30 +PCI_CHSWP_EXT = 0x40 +PCI_CHSWP_INS = 0x80 +PCI_AF_LENGTH = 2 +PCI_AF_CAP = 3 +PCI_AF_CAP_TP = 0x01 +PCI_AF_CAP_FLR = 0x02 +PCI_AF_CTRL = 4 +PCI_AF_CTRL_FLR = 0x01 +PCI_AF_STATUS = 5 +PCI_AF_STATUS_TP = 0x01 +PCI_CAP_AF_SIZEOF = 6 +PCI_EA_NUM_ENT = 2 +PCI_EA_NUM_ENT_MASK = 0x3f +PCI_EA_FIRST_ENT = 4 +PCI_EA_FIRST_ENT_BRIDGE = 8 +PCI_EA_ES = 0x00000007 +PCI_EA_BEI = 0x000000f0 +PCI_EA_SEC_BUS_MASK = 0xff +PCI_EA_SUB_BUS_MASK = 0xff00 +PCI_EA_SUB_BUS_SHIFT = 8 +PCI_EA_BEI_BAR0 = 0 +PCI_EA_BEI_BAR5 = 5 +PCI_EA_BEI_BRIDGE = 6 +PCI_EA_BEI_ENI = 7 +PCI_EA_BEI_ROM = 8 +PCI_EA_BEI_VF_BAR0 = 9 +PCI_EA_BEI_VF_BAR5 = 14 +PCI_EA_BEI_RESERVED = 15 +PCI_EA_PP = 0x0000ff00 +PCI_EA_SP = 0x00ff0000 +PCI_EA_P_MEM = 0x00 +PCI_EA_P_MEM_PREFETCH = 0x01 +PCI_EA_P_IO = 0x02 +PCI_EA_P_VF_MEM_PREFETCH = 0x03 +PCI_EA_P_VF_MEM = 0x04 +PCI_EA_P_BRIDGE_MEM = 0x05 +PCI_EA_P_BRIDGE_MEM_PREFETCH = 0x06 +PCI_EA_P_BRIDGE_IO = 0x07 +PCI_EA_P_MEM_RESERVED = 0xfd +PCI_EA_P_IO_RESERVED = 0xfe +PCI_EA_P_UNAVAILABLE = 0xff +PCI_EA_WRITABLE = 0x40000000 +PCI_EA_ENABLE = 0x80000000 +PCI_EA_BASE = 4 +PCI_EA_MAX_OFFSET = 8 +PCI_EA_IS_64 = 0x00000002 +PCI_EA_FIELD_MASK = 0xfffffffc +PCI_X_CMD = 2 +PCI_X_CMD_DPERR_E = 0x0001 +PCI_X_CMD_ERO = 0x0002 +PCI_X_CMD_READ_512 = 0x0000 +PCI_X_CMD_READ_1K = 0x0004 +PCI_X_CMD_READ_2K = 0x0008 +PCI_X_CMD_READ_4K = 0x000c +PCI_X_CMD_MAX_READ = 0x000c +PCI_X_CMD_SPLIT_1 = 0x0000 +PCI_X_CMD_SPLIT_2 = 0x0010 +PCI_X_CMD_SPLIT_3 = 0x0020 +PCI_X_CMD_SPLIT_4 = 0x0030 +PCI_X_CMD_SPLIT_8 = 0x0040 +PCI_X_CMD_SPLIT_12 = 0x0050 +PCI_X_CMD_SPLIT_16 = 0x0060 +PCI_X_CMD_SPLIT_32 = 0x0070 +PCI_X_CMD_MAX_SPLIT = 0x0070 +PCI_X_CMD_VERSION = lambda x: (((x) >> 12) & 3) +PCI_X_STATUS = 4 +PCI_X_STATUS_DEVFN = 0x000000ff +PCI_X_STATUS_BUS = 0x0000ff00 +PCI_X_STATUS_64BIT = 0x00010000 +PCI_X_STATUS_133MHZ = 0x00020000 +PCI_X_STATUS_SPL_DISC = 0x00040000 +PCI_X_STATUS_UNX_SPL = 0x00080000 +PCI_X_STATUS_COMPLEX = 0x00100000 +PCI_X_STATUS_MAX_READ = 0x00600000 +PCI_X_STATUS_MAX_SPLIT = 0x03800000 +PCI_X_STATUS_MAX_CUM = 0x1c000000 +PCI_X_STATUS_SPL_ERR = 0x20000000 +PCI_X_STATUS_266MHZ = 0x40000000 +PCI_X_STATUS_533MHZ = 0x80000000 +PCI_X_ECC_CSR = 8 +PCI_CAP_PCIX_SIZEOF_V0 = 8 +PCI_CAP_PCIX_SIZEOF_V1 = 24 +PCI_CAP_PCIX_SIZEOF_V2 = PCI_CAP_PCIX_SIZEOF_V1 +PCI_X_BRIDGE_SSTATUS = 2 +PCI_X_SSTATUS_64BIT = 0x0001 +PCI_X_SSTATUS_133MHZ = 0x0002 +PCI_X_SSTATUS_FREQ = 0x03c0 +PCI_X_SSTATUS_VERS = 0x3000 +PCI_X_SSTATUS_V1 = 0x1000 +PCI_X_SSTATUS_V2 = 0x2000 +PCI_X_SSTATUS_266MHZ = 0x4000 +PCI_X_SSTATUS_533MHZ = 0x8000 +PCI_X_BRIDGE_STATUS = 4 +PCI_SSVID_VENDOR_ID = 4 +PCI_SSVID_DEVICE_ID = 6 +PCI_EXP_FLAGS = 0x02 +PCI_EXP_FLAGS_VERS = 0x000f +PCI_EXP_FLAGS_TYPE = 0x00f0 +PCI_EXP_TYPE_ENDPOINT = 0x0 +PCI_EXP_TYPE_LEG_END = 0x1 +PCI_EXP_TYPE_ROOT_PORT = 0x4 +PCI_EXP_TYPE_UPSTREAM = 0x5 +PCI_EXP_TYPE_DOWNSTREAM = 0x6 +PCI_EXP_TYPE_PCI_BRIDGE = 0x7 +PCI_EXP_TYPE_PCIE_BRIDGE = 0x8 +PCI_EXP_TYPE_RC_END = 0x9 +PCI_EXP_TYPE_RC_EC = 0xa +PCI_EXP_FLAGS_SLOT = 0x0100 +PCI_EXP_FLAGS_IRQ = 0x3e00 +PCI_EXP_DEVCAP = 0x04 +PCI_EXP_DEVCAP_PAYLOAD = 0x00000007 +PCI_EXP_DEVCAP_PHANTOM = 0x00000018 +PCI_EXP_DEVCAP_EXT_TAG = 0x00000020 +PCI_EXP_DEVCAP_L0S = 0x000001c0 +PCI_EXP_DEVCAP_L1 = 0x00000e00 +PCI_EXP_DEVCAP_ATN_BUT = 0x00001000 +PCI_EXP_DEVCAP_ATN_IND = 0x00002000 +PCI_EXP_DEVCAP_PWR_IND = 0x00004000 +PCI_EXP_DEVCAP_RBER = 0x00008000 +PCI_EXP_DEVCAP_PWR_VAL = 0x03fc0000 +PCI_EXP_DEVCAP_PWR_SCL = 0x0c000000 +PCI_EXP_DEVCAP_FLR = 0x10000000 +PCI_EXP_DEVCTL = 0x08 +PCI_EXP_DEVCTL_CERE = 0x0001 +PCI_EXP_DEVCTL_NFERE = 0x0002 +PCI_EXP_DEVCTL_FERE = 0x0004 +PCI_EXP_DEVCTL_URRE = 0x0008 +PCI_EXP_DEVCTL_RELAX_EN = 0x0010 +PCI_EXP_DEVCTL_PAYLOAD = 0x00e0 +PCI_EXP_DEVCTL_PAYLOAD_128B = 0x0000 +PCI_EXP_DEVCTL_PAYLOAD_256B = 0x0020 +PCI_EXP_DEVCTL_PAYLOAD_512B = 0x0040 +PCI_EXP_DEVCTL_PAYLOAD_1024B = 0x0060 +PCI_EXP_DEVCTL_PAYLOAD_2048B = 0x0080 +PCI_EXP_DEVCTL_PAYLOAD_4096B = 0x00a0 +PCI_EXP_DEVCTL_EXT_TAG = 0x0100 +PCI_EXP_DEVCTL_PHANTOM = 0x0200 +PCI_EXP_DEVCTL_AUX_PME = 0x0400 +PCI_EXP_DEVCTL_NOSNOOP_EN = 0x0800 +PCI_EXP_DEVCTL_READRQ = 0x7000 +PCI_EXP_DEVCTL_READRQ_128B = 0x0000 +PCI_EXP_DEVCTL_READRQ_256B = 0x1000 +PCI_EXP_DEVCTL_READRQ_512B = 0x2000 +PCI_EXP_DEVCTL_READRQ_1024B = 0x3000 +PCI_EXP_DEVCTL_READRQ_2048B = 0x4000 +PCI_EXP_DEVCTL_READRQ_4096B = 0x5000 +PCI_EXP_DEVCTL_BCR_FLR = 0x8000 +PCI_EXP_DEVSTA = 0x0a +PCI_EXP_DEVSTA_CED = 0x0001 +PCI_EXP_DEVSTA_NFED = 0x0002 +PCI_EXP_DEVSTA_FED = 0x0004 +PCI_EXP_DEVSTA_URD = 0x0008 +PCI_EXP_DEVSTA_AUXPD = 0x0010 +PCI_EXP_DEVSTA_TRPND = 0x0020 +PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 = 12 +PCI_EXP_LNKCAP = 0x0c +PCI_EXP_LNKCAP_SLS = 0x0000000f +PCI_EXP_LNKCAP_SLS_2_5GB = 0x00000001 +PCI_EXP_LNKCAP_SLS_5_0GB = 0x00000002 +PCI_EXP_LNKCAP_SLS_8_0GB = 0x00000003 +PCI_EXP_LNKCAP_SLS_16_0GB = 0x00000004 +PCI_EXP_LNKCAP_SLS_32_0GB = 0x00000005 +PCI_EXP_LNKCAP_SLS_64_0GB = 0x00000006 +PCI_EXP_LNKCAP_MLW = 0x000003f0 +PCI_EXP_LNKCAP_ASPMS = 0x00000c00 +PCI_EXP_LNKCAP_ASPM_L0S = 0x00000400 +PCI_EXP_LNKCAP_ASPM_L1 = 0x00000800 +PCI_EXP_LNKCAP_L0SEL = 0x00007000 +PCI_EXP_LNKCAP_L1EL = 0x00038000 +PCI_EXP_LNKCAP_CLKPM = 0x00040000 +PCI_EXP_LNKCAP_SDERC = 0x00080000 +PCI_EXP_LNKCAP_DLLLARC = 0x00100000 +PCI_EXP_LNKCAP_LBNC = 0x00200000 +PCI_EXP_LNKCAP_PN = 0xff000000 +PCI_EXP_LNKCTL = 0x10 +PCI_EXP_LNKCTL_ASPMC = 0x0003 +PCI_EXP_LNKCTL_ASPM_L0S = 0x0001 +PCI_EXP_LNKCTL_ASPM_L1 = 0x0002 +PCI_EXP_LNKCTL_RCB = 0x0008 +PCI_EXP_LNKCTL_LD = 0x0010 +PCI_EXP_LNKCTL_RL = 0x0020 +PCI_EXP_LNKCTL_CCC = 0x0040 +PCI_EXP_LNKCTL_ES = 0x0080 +PCI_EXP_LNKCTL_CLKREQ_EN = 0x0100 +PCI_EXP_LNKCTL_HAWD = 0x0200 +PCI_EXP_LNKCTL_LBMIE = 0x0400 +PCI_EXP_LNKCTL_LABIE = 0x0800 +PCI_EXP_LNKSTA = 0x12 +PCI_EXP_LNKSTA_CLS = 0x000f +PCI_EXP_LNKSTA_CLS_2_5GB = 0x0001 +PCI_EXP_LNKSTA_CLS_5_0GB = 0x0002 +PCI_EXP_LNKSTA_CLS_8_0GB = 0x0003 +PCI_EXP_LNKSTA_CLS_16_0GB = 0x0004 +PCI_EXP_LNKSTA_CLS_32_0GB = 0x0005 +PCI_EXP_LNKSTA_CLS_64_0GB = 0x0006 +PCI_EXP_LNKSTA_NLW = 0x03f0 +PCI_EXP_LNKSTA_NLW_X1 = 0x0010 +PCI_EXP_LNKSTA_NLW_X2 = 0x0020 +PCI_EXP_LNKSTA_NLW_X4 = 0x0040 +PCI_EXP_LNKSTA_NLW_X8 = 0x0080 +PCI_EXP_LNKSTA_NLW_SHIFT = 4 +PCI_EXP_LNKSTA_LT = 0x0800 +PCI_EXP_LNKSTA_SLC = 0x1000 +PCI_EXP_LNKSTA_DLLLA = 0x2000 +PCI_EXP_LNKSTA_LBMS = 0x4000 +PCI_EXP_LNKSTA_LABS = 0x8000 +PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 = 20 +PCI_EXP_SLTCAP = 0x14 +PCI_EXP_SLTCAP_ABP = 0x00000001 +PCI_EXP_SLTCAP_PCP = 0x00000002 +PCI_EXP_SLTCAP_MRLSP = 0x00000004 +PCI_EXP_SLTCAP_AIP = 0x00000008 +PCI_EXP_SLTCAP_PIP = 0x00000010 +PCI_EXP_SLTCAP_HPS = 0x00000020 +PCI_EXP_SLTCAP_HPC = 0x00000040 +PCI_EXP_SLTCAP_SPLV = 0x00007f80 +PCI_EXP_SLTCAP_SPLS = 0x00018000 +PCI_EXP_SLTCAP_EIP = 0x00020000 +PCI_EXP_SLTCAP_NCCS = 0x00040000 +PCI_EXP_SLTCAP_PSN = 0xfff80000 +PCI_EXP_SLTCTL = 0x18 +PCI_EXP_SLTCTL_ABPE = 0x0001 +PCI_EXP_SLTCTL_PFDE = 0x0002 +PCI_EXP_SLTCTL_MRLSCE = 0x0004 +PCI_EXP_SLTCTL_PDCE = 0x0008 +PCI_EXP_SLTCTL_CCIE = 0x0010 +PCI_EXP_SLTCTL_HPIE = 0x0020 +PCI_EXP_SLTCTL_AIC = 0x00c0 +PCI_EXP_SLTCTL_ATTN_IND_SHIFT = 6 +PCI_EXP_SLTCTL_ATTN_IND_ON = 0x0040 +PCI_EXP_SLTCTL_ATTN_IND_BLINK = 0x0080 +PCI_EXP_SLTCTL_ATTN_IND_OFF = 0x00c0 +PCI_EXP_SLTCTL_PIC = 0x0300 +PCI_EXP_SLTCTL_PWR_IND_ON = 0x0100 +PCI_EXP_SLTCTL_PWR_IND_BLINK = 0x0200 +PCI_EXP_SLTCTL_PWR_IND_OFF = 0x0300 +PCI_EXP_SLTCTL_PCC = 0x0400 +PCI_EXP_SLTCTL_PWR_ON = 0x0000 +PCI_EXP_SLTCTL_PWR_OFF = 0x0400 +PCI_EXP_SLTCTL_EIC = 0x0800 +PCI_EXP_SLTCTL_DLLSCE = 0x1000 +PCI_EXP_SLTCTL_ASPL_DISABLE = 0x2000 +PCI_EXP_SLTCTL_IBPD_DISABLE = 0x4000 +PCI_EXP_SLTSTA = 0x1a +PCI_EXP_SLTSTA_ABP = 0x0001 +PCI_EXP_SLTSTA_PFD = 0x0002 +PCI_EXP_SLTSTA_MRLSC = 0x0004 +PCI_EXP_SLTSTA_PDC = 0x0008 +PCI_EXP_SLTSTA_CC = 0x0010 +PCI_EXP_SLTSTA_MRLSS = 0x0020 +PCI_EXP_SLTSTA_PDS = 0x0040 +PCI_EXP_SLTSTA_EIS = 0x0080 +PCI_EXP_SLTSTA_DLLSC = 0x0100 +PCI_EXP_RTCTL = 0x1c +PCI_EXP_RTCTL_SECEE = 0x0001 +PCI_EXP_RTCTL_SENFEE = 0x0002 +PCI_EXP_RTCTL_SEFEE = 0x0004 +PCI_EXP_RTCTL_PMEIE = 0x0008 +PCI_EXP_RTCTL_CRSSVE = 0x0010 +PCI_EXP_RTCAP = 0x1e +PCI_EXP_RTCAP_CRSVIS = 0x0001 +PCI_EXP_RTSTA = 0x20 +PCI_EXP_RTSTA_PME_RQ_ID = 0x0000ffff +PCI_EXP_RTSTA_PME = 0x00010000 +PCI_EXP_RTSTA_PENDING = 0x00020000 +PCI_EXP_DEVCAP2 = 0x24 +PCI_EXP_DEVCAP2_COMP_TMOUT_DIS = 0x00000010 +PCI_EXP_DEVCAP2_ARI = 0x00000020 +PCI_EXP_DEVCAP2_ATOMIC_ROUTE = 0x00000040 +PCI_EXP_DEVCAP2_ATOMIC_COMP32 = 0x00000080 +PCI_EXP_DEVCAP2_ATOMIC_COMP64 = 0x00000100 +PCI_EXP_DEVCAP2_ATOMIC_COMP128 = 0x00000200 +PCI_EXP_DEVCAP2_LTR = 0x00000800 +PCI_EXP_DEVCAP2_OBFF_MASK = 0x000c0000 +PCI_EXP_DEVCAP2_OBFF_MSG = 0x00040000 +PCI_EXP_DEVCAP2_OBFF_WAKE = 0x00080000 +PCI_EXP_DEVCAP2_EE_PREFIX = 0x00200000 +PCI_EXP_DEVCTL2 = 0x28 +PCI_EXP_DEVCTL2_COMP_TIMEOUT = 0x000f +PCI_EXP_DEVCTL2_COMP_TMOUT_DIS = 0x0010 +PCI_EXP_DEVCTL2_ARI = 0x0020 +PCI_EXP_DEVCTL2_ATOMIC_REQ = 0x0040 +PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK = 0x0080 +PCI_EXP_DEVCTL2_IDO_REQ_EN = 0x0100 +PCI_EXP_DEVCTL2_IDO_CMP_EN = 0x0200 +PCI_EXP_DEVCTL2_LTR_EN = 0x0400 +PCI_EXP_DEVCTL2_OBFF_MSGA_EN = 0x2000 +PCI_EXP_DEVCTL2_OBFF_MSGB_EN = 0x4000 +PCI_EXP_DEVCTL2_OBFF_WAKE_EN = 0x6000 +PCI_EXP_DEVSTA2 = 0x2a +PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 = 0x2c +PCI_EXP_LNKCAP2 = 0x2c +PCI_EXP_LNKCAP2_SLS_2_5GB = 0x00000002 +PCI_EXP_LNKCAP2_SLS_5_0GB = 0x00000004 +PCI_EXP_LNKCAP2_SLS_8_0GB = 0x00000008 +PCI_EXP_LNKCAP2_SLS_16_0GB = 0x00000010 +PCI_EXP_LNKCAP2_SLS_32_0GB = 0x00000020 +PCI_EXP_LNKCAP2_SLS_64_0GB = 0x00000040 +PCI_EXP_LNKCAP2_CROSSLINK = 0x00000100 +PCI_EXP_LNKCTL2 = 0x30 +PCI_EXP_LNKCTL2_TLS = 0x000f +PCI_EXP_LNKCTL2_TLS_2_5GT = 0x0001 +PCI_EXP_LNKCTL2_TLS_5_0GT = 0x0002 +PCI_EXP_LNKCTL2_TLS_8_0GT = 0x0003 +PCI_EXP_LNKCTL2_TLS_16_0GT = 0x0004 +PCI_EXP_LNKCTL2_TLS_32_0GT = 0x0005 +PCI_EXP_LNKCTL2_TLS_64_0GT = 0x0006 +PCI_EXP_LNKCTL2_ENTER_COMP = 0x0010 +PCI_EXP_LNKCTL2_TX_MARGIN = 0x0380 +PCI_EXP_LNKCTL2_HASD = 0x0020 +PCI_EXP_LNKSTA2 = 0x32 +PCI_EXP_LNKSTA2_FLIT = 0x0400 +PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 = 0x32 +PCI_EXP_SLTCAP2 = 0x34 +PCI_EXP_SLTCAP2_IBPD = 0x00000001 +PCI_EXP_SLTCTL2 = 0x38 +PCI_EXP_SLTSTA2 = 0x3a +PCI_EXT_CAP_ID = lambda header: (header & 0x0000ffff) +PCI_EXT_CAP_VER = lambda header: ((header >> 16) & 0xf) +PCI_EXT_CAP_NEXT = lambda header: ((header >> 20) & 0xffc) +PCI_EXT_CAP_ID_ERR = 0x01 +PCI_EXT_CAP_ID_VC = 0x02 +PCI_EXT_CAP_ID_DSN = 0x03 +PCI_EXT_CAP_ID_PWR = 0x04 +PCI_EXT_CAP_ID_RCLD = 0x05 +PCI_EXT_CAP_ID_RCILC = 0x06 +PCI_EXT_CAP_ID_RCEC = 0x07 +PCI_EXT_CAP_ID_MFVC = 0x08 +PCI_EXT_CAP_ID_VC9 = 0x09 +PCI_EXT_CAP_ID_RCRB = 0x0A +PCI_EXT_CAP_ID_VNDR = 0x0B +PCI_EXT_CAP_ID_CAC = 0x0C +PCI_EXT_CAP_ID_ACS = 0x0D +PCI_EXT_CAP_ID_ARI = 0x0E +PCI_EXT_CAP_ID_ATS = 0x0F +PCI_EXT_CAP_ID_SRIOV = 0x10 +PCI_EXT_CAP_ID_MRIOV = 0x11 +PCI_EXT_CAP_ID_MCAST = 0x12 +PCI_EXT_CAP_ID_PRI = 0x13 +PCI_EXT_CAP_ID_AMD_XXX = 0x14 +PCI_EXT_CAP_ID_REBAR = 0x15 +PCI_EXT_CAP_ID_DPA = 0x16 +PCI_EXT_CAP_ID_TPH = 0x17 +PCI_EXT_CAP_ID_LTR = 0x18 +PCI_EXT_CAP_ID_SECPCI = 0x19 +PCI_EXT_CAP_ID_PMUX = 0x1A +PCI_EXT_CAP_ID_PASID = 0x1B +PCI_EXT_CAP_ID_DPC = 0x1D +PCI_EXT_CAP_ID_L1SS = 0x1E +PCI_EXT_CAP_ID_PTM = 0x1F +PCI_EXT_CAP_ID_DVSEC = 0x23 +PCI_EXT_CAP_ID_DLF = 0x25 +PCI_EXT_CAP_ID_PL_16GT = 0x26 +PCI_EXT_CAP_ID_PL_32GT = 0x2A +PCI_EXT_CAP_ID_DOE = 0x2E +PCI_EXT_CAP_ID_MAX = PCI_EXT_CAP_ID_DOE +PCI_EXT_CAP_DSN_SIZEOF = 12 +PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF = 40 +PCI_ERR_UNCOR_STATUS = 0x04 +PCI_ERR_UNC_UND = 0x00000001 +PCI_ERR_UNC_DLP = 0x00000010 +PCI_ERR_UNC_SURPDN = 0x00000020 +PCI_ERR_UNC_POISON_TLP = 0x00001000 +PCI_ERR_UNC_FCP = 0x00002000 +PCI_ERR_UNC_COMP_TIME = 0x00004000 +PCI_ERR_UNC_COMP_ABORT = 0x00008000 +PCI_ERR_UNC_UNX_COMP = 0x00010000 +PCI_ERR_UNC_RX_OVER = 0x00020000 +PCI_ERR_UNC_MALF_TLP = 0x00040000 +PCI_ERR_UNC_ECRC = 0x00080000 +PCI_ERR_UNC_UNSUP = 0x00100000 +PCI_ERR_UNC_ACSV = 0x00200000 +PCI_ERR_UNC_INTN = 0x00400000 +PCI_ERR_UNC_MCBTLP = 0x00800000 +PCI_ERR_UNC_ATOMEG = 0x01000000 +PCI_ERR_UNC_TLPPRE = 0x02000000 +PCI_ERR_UNCOR_MASK = 0x08 +PCI_ERR_UNCOR_SEVER = 0x0c +PCI_ERR_COR_STATUS = 0x10 +PCI_ERR_COR_RCVR = 0x00000001 +PCI_ERR_COR_BAD_TLP = 0x00000040 +PCI_ERR_COR_BAD_DLLP = 0x00000080 +PCI_ERR_COR_REP_ROLL = 0x00000100 +PCI_ERR_COR_REP_TIMER = 0x00001000 +PCI_ERR_COR_ADV_NFAT = 0x00002000 +PCI_ERR_COR_INTERNAL = 0x00004000 +PCI_ERR_COR_LOG_OVER = 0x00008000 +PCI_ERR_COR_MASK = 0x14 +PCI_ERR_CAP = 0x18 +PCI_ERR_CAP_FEP = lambda x: ((x) & 0x1f) +PCI_ERR_CAP_ECRC_GENC = 0x00000020 +PCI_ERR_CAP_ECRC_GENE = 0x00000040 +PCI_ERR_CAP_ECRC_CHKC = 0x00000080 +PCI_ERR_CAP_ECRC_CHKE = 0x00000100 +PCI_ERR_HEADER_LOG = 0x1c +PCI_ERR_ROOT_COMMAND = 0x2c +PCI_ERR_ROOT_CMD_COR_EN = 0x00000001 +PCI_ERR_ROOT_CMD_NONFATAL_EN = 0x00000002 +PCI_ERR_ROOT_CMD_FATAL_EN = 0x00000004 +PCI_ERR_ROOT_STATUS = 0x30 +PCI_ERR_ROOT_COR_RCV = 0x00000001 +PCI_ERR_ROOT_MULTI_COR_RCV = 0x00000002 +PCI_ERR_ROOT_UNCOR_RCV = 0x00000004 +PCI_ERR_ROOT_MULTI_UNCOR_RCV = 0x00000008 +PCI_ERR_ROOT_FIRST_FATAL = 0x00000010 +PCI_ERR_ROOT_NONFATAL_RCV = 0x00000020 +PCI_ERR_ROOT_FATAL_RCV = 0x00000040 +PCI_ERR_ROOT_AER_IRQ = 0xf8000000 +PCI_ERR_ROOT_ERR_SRC = 0x34 +PCI_VC_PORT_CAP1 = 0x04 +PCI_VC_CAP1_EVCC = 0x00000007 +PCI_VC_CAP1_LPEVCC = 0x00000070 +PCI_VC_CAP1_ARB_SIZE = 0x00000c00 +PCI_VC_PORT_CAP2 = 0x08 +PCI_VC_CAP2_32_PHASE = 0x00000002 +PCI_VC_CAP2_64_PHASE = 0x00000004 +PCI_VC_CAP2_128_PHASE = 0x00000008 +PCI_VC_CAP2_ARB_OFF = 0xff000000 +PCI_VC_PORT_CTRL = 0x0c +PCI_VC_PORT_CTRL_LOAD_TABLE = 0x00000001 +PCI_VC_PORT_STATUS = 0x0e +PCI_VC_PORT_STATUS_TABLE = 0x00000001 +PCI_VC_RES_CAP = 0x10 +PCI_VC_RES_CAP_32_PHASE = 0x00000002 +PCI_VC_RES_CAP_64_PHASE = 0x00000004 +PCI_VC_RES_CAP_128_PHASE = 0x00000008 +PCI_VC_RES_CAP_128_PHASE_TB = 0x00000010 +PCI_VC_RES_CAP_256_PHASE = 0x00000020 +PCI_VC_RES_CAP_ARB_OFF = 0xff000000 +PCI_VC_RES_CTRL = 0x14 +PCI_VC_RES_CTRL_LOAD_TABLE = 0x00010000 +PCI_VC_RES_CTRL_ARB_SELECT = 0x000e0000 +PCI_VC_RES_CTRL_ID = 0x07000000 +PCI_VC_RES_CTRL_ENABLE = 0x80000000 +PCI_VC_RES_STATUS = 0x1a +PCI_VC_RES_STATUS_TABLE = 0x00000001 +PCI_VC_RES_STATUS_NEGO = 0x00000002 +PCI_CAP_VC_BASE_SIZEOF = 0x10 +PCI_CAP_VC_PER_VC_SIZEOF = 0x0c +PCI_PWR_DSR = 0x04 +PCI_PWR_DATA = 0x08 +PCI_PWR_DATA_BASE = lambda x: ((x) & 0xff) +PCI_PWR_DATA_SCALE = lambda x: (((x) >> 8) & 3) +PCI_PWR_DATA_PM_SUB = lambda x: (((x) >> 10) & 7) +PCI_PWR_DATA_PM_STATE = lambda x: (((x) >> 13) & 3) +PCI_PWR_DATA_TYPE = lambda x: (((x) >> 15) & 7) +PCI_PWR_DATA_RAIL = lambda x: (((x) >> 18) & 7) +PCI_PWR_CAP = 0x0c +PCI_PWR_CAP_BUDGET = lambda x: ((x) & 1) +PCI_EXT_CAP_PWR_SIZEOF = 0x10 +PCI_RCEC_RCIEP_BITMAP = 4 +PCI_RCEC_BUSN = 8 +PCI_RCEC_BUSN_REG_VER = 0x02 +PCI_RCEC_BUSN_NEXT = lambda x: (((x) >> 8) & 0xff) +PCI_RCEC_BUSN_LAST = lambda x: (((x) >> 16) & 0xff) +PCI_VNDR_HEADER = 4 +PCI_VNDR_HEADER_ID = lambda x: ((x) & 0xffff) +PCI_VNDR_HEADER_REV = lambda x: (((x) >> 16) & 0xf) +PCI_VNDR_HEADER_LEN = lambda x: (((x) >> 20) & 0xfff) +HT_3BIT_CAP_MASK = 0xE0 +HT_CAPTYPE_SLAVE = 0x00 +HT_CAPTYPE_HOST = 0x20 +HT_5BIT_CAP_MASK = 0xF8 +HT_CAPTYPE_IRQ = 0x80 +HT_CAPTYPE_REMAPPING_40 = 0xA0 +HT_CAPTYPE_REMAPPING_64 = 0xA2 +HT_CAPTYPE_UNITID_CLUMP = 0x90 +HT_CAPTYPE_EXTCONF = 0x98 +HT_CAPTYPE_MSI_MAPPING = 0xA8 +HT_MSI_FLAGS = 0x02 +HT_MSI_FLAGS_ENABLE = 0x1 +HT_MSI_FLAGS_FIXED = 0x2 +HT_MSI_FIXED_ADDR = 0x00000000FEE00000 +HT_MSI_ADDR_LO = 0x04 +HT_MSI_ADDR_LO_MASK = 0xFFF00000 +HT_MSI_ADDR_HI = 0x08 +HT_CAPTYPE_DIRECT_ROUTE = 0xB0 +HT_CAPTYPE_VCSET = 0xB8 +HT_CAPTYPE_ERROR_RETRY = 0xC0 +HT_CAPTYPE_GEN3 = 0xD0 +HT_CAPTYPE_PM = 0xE0 +HT_CAP_SIZEOF_LONG = 28 +HT_CAP_SIZEOF_SHORT = 24 +PCI_ARI_CAP = 0x04 +PCI_ARI_CAP_MFVC = 0x0001 +PCI_ARI_CAP_ACS = 0x0002 +PCI_ARI_CAP_NFN = lambda x: (((x) >> 8) & 0xff) +PCI_ARI_CTRL = 0x06 +PCI_ARI_CTRL_MFVC = 0x0001 +PCI_ARI_CTRL_ACS = 0x0002 +PCI_ARI_CTRL_FG = lambda x: (((x) >> 4) & 7) +PCI_EXT_CAP_ARI_SIZEOF = 8 +PCI_ATS_CAP = 0x04 +PCI_ATS_CAP_QDEP = lambda x: ((x) & 0x1f) +PCI_ATS_MAX_QDEP = 32 +PCI_ATS_CAP_PAGE_ALIGNED = 0x0020 +PCI_ATS_CTRL = 0x06 +PCI_ATS_CTRL_ENABLE = 0x8000 +PCI_ATS_CTRL_STU = lambda x: ((x) & 0x1f) +PCI_ATS_MIN_STU = 12 +PCI_EXT_CAP_ATS_SIZEOF = 8 +PCI_PRI_CTRL = 0x04 +PCI_PRI_CTRL_ENABLE = 0x0001 +PCI_PRI_CTRL_RESET = 0x0002 +PCI_PRI_STATUS = 0x06 +PCI_PRI_STATUS_RF = 0x0001 +PCI_PRI_STATUS_UPRGI = 0x0002 +PCI_PRI_STATUS_STOPPED = 0x0100 +PCI_PRI_STATUS_PASID = 0x8000 +PCI_PRI_MAX_REQ = 0x08 +PCI_PRI_ALLOC_REQ = 0x0c +PCI_EXT_CAP_PRI_SIZEOF = 16 +PCI_PASID_CAP = 0x04 +PCI_PASID_CAP_EXEC = 0x0002 +PCI_PASID_CAP_PRIV = 0x0004 +PCI_PASID_CAP_WIDTH = 0x1f00 +PCI_PASID_CTRL = 0x06 +PCI_PASID_CTRL_ENABLE = 0x0001 +PCI_PASID_CTRL_EXEC = 0x0002 +PCI_PASID_CTRL_PRIV = 0x0004 +PCI_EXT_CAP_PASID_SIZEOF = 8 +PCI_SRIOV_CAP = 0x04 +PCI_SRIOV_CAP_VFM = 0x00000001 +PCI_SRIOV_CAP_INTR = lambda x: ((x) >> 21) +PCI_SRIOV_CTRL = 0x08 +PCI_SRIOV_CTRL_VFE = 0x0001 +PCI_SRIOV_CTRL_VFM = 0x0002 +PCI_SRIOV_CTRL_INTR = 0x0004 +PCI_SRIOV_CTRL_MSE = 0x0008 +PCI_SRIOV_CTRL_ARI = 0x0010 +PCI_SRIOV_STATUS = 0x0a +PCI_SRIOV_STATUS_VFM = 0x0001 +PCI_SRIOV_INITIAL_VF = 0x0c +PCI_SRIOV_TOTAL_VF = 0x0e +PCI_SRIOV_NUM_VF = 0x10 +PCI_SRIOV_FUNC_LINK = 0x12 +PCI_SRIOV_VF_OFFSET = 0x14 +PCI_SRIOV_VF_STRIDE = 0x16 +PCI_SRIOV_VF_DID = 0x1a +PCI_SRIOV_SUP_PGSIZE = 0x1c +PCI_SRIOV_SYS_PGSIZE = 0x20 +PCI_SRIOV_BAR = 0x24 +PCI_SRIOV_NUM_BARS = 6 +PCI_SRIOV_VFM = 0x3c +PCI_SRIOV_VFM_BIR = lambda x: ((x) & 7) +PCI_SRIOV_VFM_OFFSET = lambda x: ((x) & ~7) +PCI_SRIOV_VFM_UA = 0x0 +PCI_SRIOV_VFM_MI = 0x1 +PCI_SRIOV_VFM_MO = 0x2 +PCI_SRIOV_VFM_AV = 0x3 +PCI_EXT_CAP_SRIOV_SIZEOF = 0x40 +PCI_LTR_MAX_SNOOP_LAT = 0x4 +PCI_LTR_MAX_NOSNOOP_LAT = 0x6 +PCI_LTR_VALUE_MASK = 0x000003ff +PCI_LTR_SCALE_MASK = 0x00001c00 +PCI_LTR_SCALE_SHIFT = 10 +PCI_LTR_NOSNOOP_VALUE = 0x03ff0000 +PCI_LTR_NOSNOOP_SCALE = 0x1c000000 +PCI_EXT_CAP_LTR_SIZEOF = 8 +PCI_ACS_CAP = 0x04 +PCI_ACS_SV = 0x0001 +PCI_ACS_TB = 0x0002 +PCI_ACS_RR = 0x0004 +PCI_ACS_CR = 0x0008 +PCI_ACS_UF = 0x0010 +PCI_ACS_EC = 0x0020 +PCI_ACS_DT = 0x0040 +PCI_ACS_EGRESS_BITS = 0x05 +PCI_ACS_CTRL = 0x06 +PCI_ACS_EGRESS_CTL_V = 0x08 +PCI_VSEC_HDR = 4 +PCI_VSEC_HDR_LEN_SHIFT = 20 +PCI_SATA_REGS = 4 +PCI_SATA_REGS_MASK = 0xF +PCI_SATA_REGS_INLINE = 0xF +PCI_SATA_SIZEOF_SHORT = 8 +PCI_SATA_SIZEOF_LONG = 16 +PCI_REBAR_CAP = 4 +PCI_REBAR_CAP_SIZES = 0x00FFFFF0 +PCI_REBAR_CTRL = 8 +PCI_REBAR_CTRL_BAR_IDX = 0x00000007 +PCI_REBAR_CTRL_NBAR_MASK = 0x000000E0 +PCI_REBAR_CTRL_NBAR_SHIFT = 5 +PCI_REBAR_CTRL_BAR_SIZE = 0x00001F00 +PCI_REBAR_CTRL_BAR_SHIFT = 8 +PCI_DPA_CAP = 4 +PCI_DPA_CAP_SUBSTATE_MASK = 0x1F +PCI_DPA_BASE_SIZEOF = 16 +PCI_TPH_CAP = 4 +PCI_TPH_CAP_LOC_MASK = 0x600 +PCI_TPH_LOC_NONE = 0x000 +PCI_TPH_LOC_CAP = 0x200 +PCI_TPH_LOC_MSIX = 0x400 +PCI_TPH_CAP_ST_MASK = 0x07FF0000 +PCI_TPH_CAP_ST_SHIFT = 16 +PCI_TPH_BASE_SIZEOF = 0xc +PCI_EXP_DPC_CAP = 0x04 +PCI_EXP_DPC_IRQ = 0x001F +PCI_EXP_DPC_CAP_RP_EXT = 0x0020 +PCI_EXP_DPC_CAP_POISONED_TLP = 0x0040 +PCI_EXP_DPC_CAP_SW_TRIGGER = 0x0080 +PCI_EXP_DPC_RP_PIO_LOG_SIZE = 0x0F00 +PCI_EXP_DPC_CAP_DL_ACTIVE = 0x1000 +PCI_EXP_DPC_CTL = 0x06 +PCI_EXP_DPC_CTL_EN_FATAL = 0x0001 +PCI_EXP_DPC_CTL_EN_NONFATAL = 0x0002 +PCI_EXP_DPC_CTL_INT_EN = 0x0008 +PCI_EXP_DPC_STATUS = 0x08 +PCI_EXP_DPC_STATUS_TRIGGER = 0x0001 +PCI_EXP_DPC_STATUS_TRIGGER_RSN = 0x0006 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR = 0x0000 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE = 0x0002 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE = 0x0004 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT = 0x0006 +PCI_EXP_DPC_STATUS_INTERRUPT = 0x0008 +PCI_EXP_DPC_RP_BUSY = 0x0010 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT = 0x0060 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO = 0x0000 +PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER = 0x0020 +PCI_EXP_DPC_RP_PIO_FEP = 0x1f00 +PCI_EXP_DPC_SOURCE_ID = 0x0A +PCI_EXP_DPC_RP_PIO_STATUS = 0x0C +PCI_EXP_DPC_RP_PIO_MASK = 0x10 +PCI_EXP_DPC_RP_PIO_SEVERITY = 0x14 +PCI_EXP_DPC_RP_PIO_SYSERROR = 0x18 +PCI_EXP_DPC_RP_PIO_EXCEPTION = 0x1C +PCI_EXP_DPC_RP_PIO_HEADER_LOG = 0x20 +PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG = 0x30 +PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG = 0x34 +PCI_PTM_CAP = 0x04 +PCI_PTM_CAP_REQ = 0x00000001 +PCI_PTM_CAP_RES = 0x00000002 +PCI_PTM_CAP_ROOT = 0x00000004 +PCI_PTM_GRANULARITY_MASK = 0x0000FF00 +PCI_PTM_CTRL = 0x08 +PCI_PTM_CTRL_ENABLE = 0x00000001 +PCI_PTM_CTRL_ROOT = 0x00000002 +PCI_L1SS_CAP = 0x04 +PCI_L1SS_CAP_PCIPM_L1_2 = 0x00000001 +PCI_L1SS_CAP_PCIPM_L1_1 = 0x00000002 +PCI_L1SS_CAP_ASPM_L1_2 = 0x00000004 +PCI_L1SS_CAP_ASPM_L1_1 = 0x00000008 +PCI_L1SS_CAP_L1_PM_SS = 0x00000010 +PCI_L1SS_CAP_CM_RESTORE_TIME = 0x0000ff00 +PCI_L1SS_CAP_P_PWR_ON_SCALE = 0x00030000 +PCI_L1SS_CAP_P_PWR_ON_VALUE = 0x00f80000 +PCI_L1SS_CTL1 = 0x08 +PCI_L1SS_CTL1_PCIPM_L1_2 = 0x00000001 +PCI_L1SS_CTL1_PCIPM_L1_1 = 0x00000002 +PCI_L1SS_CTL1_ASPM_L1_2 = 0x00000004 +PCI_L1SS_CTL1_ASPM_L1_1 = 0x00000008 +PCI_L1SS_CTL1_L1_2_MASK = 0x00000005 +PCI_L1SS_CTL1_L1SS_MASK = 0x0000000f +PCI_L1SS_CTL1_CM_RESTORE_TIME = 0x0000ff00 +PCI_L1SS_CTL1_LTR_L12_TH_VALUE = 0x03ff0000 +PCI_L1SS_CTL1_LTR_L12_TH_SCALE = 0xe0000000 +PCI_L1SS_CTL2 = 0x0c +PCI_L1SS_CTL2_T_PWR_ON_SCALE = 0x00000003 +PCI_L1SS_CTL2_T_PWR_ON_VALUE = 0x000000f8 +PCI_DVSEC_HEADER1 = 0x4 +PCI_DVSEC_HEADER1_VID = lambda x: ((x) & 0xffff) +PCI_DVSEC_HEADER1_REV = lambda x: (((x) >> 16) & 0xf) +PCI_DVSEC_HEADER1_LEN = lambda x: (((x) >> 20) & 0xfff) +PCI_DVSEC_HEADER2 = 0x8 +PCI_DVSEC_HEADER2_ID = lambda x: ((x) & 0xffff) +PCI_DLF_CAP = 0x04 +PCI_DLF_EXCHANGE_ENABLE = 0x80000000 +PCI_PL_16GT_LE_CTRL = 0x20 +PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK = 0x0000000F +PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK = 0x000000F0 +PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT = 4 +PCI_DOE_CAP = 0x04 +PCI_DOE_CAP_INT_SUP = 0x00000001 +PCI_DOE_CAP_INT_MSG_NUM = 0x00000ffe +PCI_DOE_CTRL = 0x08 +PCI_DOE_CTRL_ABORT = 0x00000001 +PCI_DOE_CTRL_INT_EN = 0x00000002 +PCI_DOE_CTRL_GO = 0x80000000 +PCI_DOE_STATUS = 0x0c +PCI_DOE_STATUS_BUSY = 0x00000001 +PCI_DOE_STATUS_INT_STATUS = 0x00000002 +PCI_DOE_STATUS_ERROR = 0x00000004 +PCI_DOE_STATUS_DATA_OBJECT_READY = 0x80000000 +PCI_DOE_WRITE = 0x10 +PCI_DOE_READ = 0x14 +PCI_DOE_CAP_SIZEOF = 0x18 +PCI_DOE_DATA_OBJECT_HEADER_1_VID = 0x0000ffff +PCI_DOE_DATA_OBJECT_HEADER_1_TYPE = 0x00ff0000 +PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH = 0x0003ffff +PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX = 0x000000ff +PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID = 0x0000ffff +PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL = 0x00ff0000 +PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX = 0xff000000 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/qcom_dsp.py b/tinygrad/runtime/autogen/qcom_dsp.py index 73578de828..2f7b0423b8 100644 --- a/tinygrad/runtime/autogen/qcom_dsp.py +++ b/tinygrad/runtime/autogen/qcom_dsp.py @@ -1,1741 +1,624 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - -import fcntl, functools - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, *args, **kwargs): - ret = fcntl.ioctl(__fd, (__idir<<30) | (ctypes.sizeof(made := __user_struct(*args, **kwargs))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise OSError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl, 0, ord(base) if isinstance(base, str) else base, nr, None) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = FunctionFactoryStub() # ctypes.CDLL('FIXME_STUB') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -_UAPI_LINUX_ION_H = True # macro -# ION_NUM_HEAP_IDS = (ctypes.sizeof*8) # macro -ION_FLAG_CACHED = 1 # macro -ION_FLAG_CACHED_NEEDS_SYNC = 2 # macro -ION_IOC_MAGIC = 'I' # macro +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR ion_user_handle_t = ctypes.c_int32 +enum_ion_heap_type = CEnum(ctypes.c_uint32) +ION_HEAP_TYPE_SYSTEM = enum_ion_heap_type.define('ION_HEAP_TYPE_SYSTEM', 0) +ION_HEAP_TYPE_SYSTEM_CONTIG = enum_ion_heap_type.define('ION_HEAP_TYPE_SYSTEM_CONTIG', 1) +ION_HEAP_TYPE_CARVEOUT = enum_ion_heap_type.define('ION_HEAP_TYPE_CARVEOUT', 2) +ION_HEAP_TYPE_CHUNK = enum_ion_heap_type.define('ION_HEAP_TYPE_CHUNK', 3) +ION_HEAP_TYPE_DMA = enum_ion_heap_type.define('ION_HEAP_TYPE_DMA', 4) +ION_HEAP_TYPE_CUSTOM = enum_ion_heap_type.define('ION_HEAP_TYPE_CUSTOM', 5) +ION_NUM_HEAPS = enum_ion_heap_type.define('ION_NUM_HEAPS', 16) -# values for enumeration 'ion_heap_type' -ion_heap_type__enumvalues = { - 0: 'ION_HEAP_TYPE_SYSTEM', - 1: 'ION_HEAP_TYPE_SYSTEM_CONTIG', - 2: 'ION_HEAP_TYPE_CARVEOUT', - 3: 'ION_HEAP_TYPE_CHUNK', - 4: 'ION_HEAP_TYPE_DMA', - 5: 'ION_HEAP_TYPE_CUSTOM', - 16: 'ION_NUM_HEAPS', -} -ION_HEAP_TYPE_SYSTEM = 0 -ION_HEAP_TYPE_SYSTEM_CONTIG = 1 -ION_HEAP_TYPE_CARVEOUT = 2 -ION_HEAP_TYPE_CHUNK = 3 -ION_HEAP_TYPE_DMA = 4 -ION_HEAP_TYPE_CUSTOM = 5 -ION_NUM_HEAPS = 16 -ion_heap_type = ctypes.c_uint32 # enum -ION_HEAP_SYSTEM_MASK = ((1<>16)&0x0ff) -def REMOTE_SCALARS_OUTBUFS(dwScalars): # macro - return (((dwScalars)>>8)&0x0ff) -def REMOTE_SCALARS_INHANDLES(dwScalars): # macro - return (((dwScalars)>>4)&0x0f) -def REMOTE_SCALARS_OUTHANDLES(dwScalars): # macro - return ((dwScalars)&0x0f) -def REMOTE_SCALARS_LENGTH(sc): # macro - return (REMOTE_SCALARS_INBUFS(sc)+REMOTE_SCALARS_OUTBUFS(sc)+REMOTE_SCALARS_INHANDLES(sc)+REMOTE_SCALARS_OUTHANDLES(sc)) -def REMOTE_SCALARS_MAKEX(nAttr, nMethod, nIn, nOut, noIn, noOut): # macro - return ((((nAttr)&0x7)<<29)|(((nMethod)&0x1f)<<24)|(((nIn)&0xff)<<16)|(((nOut)&0xff)<<8)|(((noIn)&0x0f)<<4)|((noOut)&0x0f)) -def REMOTE_SCALARS_MAKE(nMethod, nIn, nOut): # macro - return REMOTE_SCALARS_MAKEX(0,nMethod,nIn,nOut,0,0) -# def VERIFY_EPRINTF(format, args): # macro -# return (void)0 -# def VERIFY_IPRINTF(args): # macro -# return (void)0 -# def __STR__(x): # macro -# return #x":" -def __TOSTR__(x): # macro - return __STR__(x) -# __FILE_LINE__ = __FILE__ ":" __TOSTR__ ( __LINE__ ) # macro -# def VERIFY(err, val): # macro -# return {VERIFY_IPRINTF(__FILE__":"__TOSTR__(__LINE__)"info: calling: "#val"\n");((val)==0){(err)=(err)==0?-1:(err);VERIFY_EPRINTF(__FILE__":"__TOSTR__(__LINE__)"error: %d: "#val"\n",(err));}{VERIFY_IPRINTF(__FILE__":"__TOSTR__(__LINE__)"info: passed: "#val"\n");}\}(0) -# remote_arg64_t = remote_arg64 # macro -FASTRPC_CONTROL_LATENCY = (1) # macro -FASTRPC_CONTROL_SMMU = (2) # macro -FASTRPC_CONTROL_KALLOC = (3) # macro -class struct_remote_buf64(Structure): - pass - -struct_remote_buf64._pack_ = 1 # source:False +class struct_remote_buf64(Struct): pass +uint64_t = ctypes.c_uint64 struct_remote_buf64._fields_ = [ - ('pv', ctypes.c_uint64), - ('len', ctypes.c_uint64), + ('pv', uint64_t), + ('len', uint64_t), ] - -class struct_remote_dma_handle64(Structure): - pass - -struct_remote_dma_handle64._pack_ = 1 # source:False -struct_remote_dma_handle64._fields_ = [ - ('fd', ctypes.c_int32), - ('offset', ctypes.c_uint32), - ('len', ctypes.c_uint32), -] - -class union_remote_arg64(Union): - pass - -union_remote_arg64._pack_ = 1 # source:False -union_remote_arg64._fields_ = [ - ('buf', struct_remote_buf64), - ('dma', struct_remote_dma_handle64), - ('h', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 12), -] - -class struct_remote_buf(Structure): - pass - -struct_remote_buf._pack_ = 1 # source:False -struct_remote_buf._fields_ = [ - ('pv', ctypes.POINTER(None)), - ('len', ctypes.c_uint64), -] - -class struct_remote_dma_handle(Structure): - pass - -struct_remote_dma_handle._pack_ = 1 # source:False -struct_remote_dma_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('offset', ctypes.c_uint32), -] - -class union_remote_arg(Union): - pass - -union_remote_arg._pack_ = 1 # source:False -union_remote_arg._fields_ = [ - ('buf', struct_remote_buf), - ('dma', struct_remote_dma_handle), - ('h', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 12), -] - -class struct_fastrpc_ioctl_invoke(Structure): - pass - -struct_fastrpc_ioctl_invoke._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke._fields_ = [ - ('handle', ctypes.c_uint32), - ('sc', ctypes.c_uint32), - ('pra', ctypes.POINTER(union_remote_arg)), -] - -FASTRPC_IOCTL_INVOKE = _IOWR ( 'R' , 1 , struct_fastrpc_ioctl_invoke ) # macro (from list) -class struct_fastrpc_ioctl_invoke_fd(Structure): - pass - -struct_fastrpc_ioctl_invoke_fd._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke_fd._fields_ = [ - ('inv', struct_fastrpc_ioctl_invoke), - ('fds', ctypes.POINTER(ctypes.c_int32)), -] - -FASTRPC_IOCTL_INVOKE_FD = _IOWR ( 'R' , 4 , struct_fastrpc_ioctl_invoke_fd ) # macro (from list) -class struct_fastrpc_ioctl_invoke_attrs(Structure): - pass - -struct_fastrpc_ioctl_invoke_attrs._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke_attrs._fields_ = [ - ('inv', struct_fastrpc_ioctl_invoke), - ('fds', ctypes.POINTER(ctypes.c_int32)), - ('attrs', ctypes.POINTER(ctypes.c_uint32)), -] - -FASTRPC_IOCTL_INVOKE_ATTRS = _IOWR ( 'R' , 7 , struct_fastrpc_ioctl_invoke_attrs ) # macro (from list) -class struct_fastrpc_ioctl_invoke_crc(Structure): - pass - -struct_fastrpc_ioctl_invoke_crc._pack_ = 1 # source:False -struct_fastrpc_ioctl_invoke_crc._fields_ = [ - ('inv', struct_fastrpc_ioctl_invoke), - ('fds', ctypes.POINTER(ctypes.c_int32)), - ('attrs', ctypes.POINTER(ctypes.c_uint32)), - ('crc', ctypes.POINTER(ctypes.c_uint32)), -] - -FASTRPC_IOCTL_INVOKE_CRC = _IOWR ( 'R' , 11 , struct_fastrpc_ioctl_invoke_crc ) # macro (from list) -class struct_fastrpc_ioctl_init(Structure): - pass - -struct_fastrpc_ioctl_init._pack_ = 1 # source:False -struct_fastrpc_ioctl_init._fields_ = [ - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('file', ctypes.c_uint64), - ('filelen', ctypes.c_uint32), - ('filefd', ctypes.c_int32), - ('mem', ctypes.c_uint64), - ('memlen', ctypes.c_uint32), - ('memfd', ctypes.c_int32), -] - -FASTRPC_IOCTL_INIT = _IOWR ( 'R' , 6 , struct_fastrpc_ioctl_init ) # macro (from list) -class struct_fastrpc_ioctl_init_attrs(Structure): - pass - -struct_fastrpc_ioctl_init_attrs._pack_ = 1 # source:False -struct_fastrpc_ioctl_init_attrs._fields_ = [ - ('init', struct_fastrpc_ioctl_init), - ('attrs', ctypes.c_int32), - ('siglen', ctypes.c_uint32), -] - -FASTRPC_IOCTL_INIT_ATTRS = _IOWR ( 'R' , 10 , struct_fastrpc_ioctl_init_attrs ) # macro (from list) -class struct_fastrpc_ioctl_munmap(Structure): - pass - -struct_fastrpc_ioctl_munmap._pack_ = 1 # source:False -struct_fastrpc_ioctl_munmap._fields_ = [ - ('vaddrout', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MUNMAP = _IOWR ( 'R' , 3 , struct_fastrpc_ioctl_munmap ) # macro (from list) -class struct_fastrpc_ioctl_munmap_64(Structure): - pass - -struct_fastrpc_ioctl_munmap_64._pack_ = 1 # source:False -struct_fastrpc_ioctl_munmap_64._fields_ = [ - ('vaddrout', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MUNMAP_64 = _IOWR ( 'R' , 15 , struct_fastrpc_ioctl_munmap_64 ) # macro (from list) -class struct_fastrpc_ioctl_mmap(Structure): - pass - -struct_fastrpc_ioctl_mmap._pack_ = 1 # source:False -struct_fastrpc_ioctl_mmap._fields_ = [ - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('vaddrin', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('vaddrout', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MMAP = _IOWR ( 'R' , 2 , struct_fastrpc_ioctl_mmap ) # macro (from list) -class struct_fastrpc_ioctl_mmap_64(Structure): - pass - -struct_fastrpc_ioctl_mmap_64._pack_ = 1 # source:False -struct_fastrpc_ioctl_mmap_64._fields_ = [ - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('vaddrin', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('vaddrout', ctypes.c_uint64), -] - -FASTRPC_IOCTL_MMAP_64 = _IOWR ( 'R' , 14 , struct_fastrpc_ioctl_mmap_64 ) # macro (from list) -class struct_fastrpc_ioctl_munmap_fd(Structure): - pass - -struct_fastrpc_ioctl_munmap_fd._pack_ = 1 # source:False -struct_fastrpc_ioctl_munmap_fd._fields_ = [ - ('fd', ctypes.c_int32), - ('flags', ctypes.c_uint32), - ('va', ctypes.c_uint64), - ('len', ctypes.c_int64), -] - -FASTRPC_IOCTL_MUNMAP_FD = _IOWR ( 'R' , 13 , struct_fastrpc_ioctl_munmap_fd ) # macro (from list) -class struct_fastrpc_ioctl_perf(Structure): - pass - -struct_fastrpc_ioctl_perf._pack_ = 1 # source:False -struct_fastrpc_ioctl_perf._fields_ = [ - ('data', ctypes.c_uint64), - ('numkeys', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('keys', ctypes.c_uint64), -] - -FASTRPC_IOCTL_GETPERF = _IOWR ( 'R' , 9 , struct_fastrpc_ioctl_perf ) # macro (from list) -class struct_fastrpc_ctrl_latency(Structure): - pass - -struct_fastrpc_ctrl_latency._pack_ = 1 # source:False -struct_fastrpc_ctrl_latency._fields_ = [ - ('enable', ctypes.c_uint32), - ('level', ctypes.c_uint32), -] - -class struct_fastrpc_ctrl_smmu(Structure): - pass - -struct_fastrpc_ctrl_smmu._pack_ = 1 # source:False -struct_fastrpc_ctrl_smmu._fields_ = [ - ('sharedcb', ctypes.c_uint32), -] - -class struct_fastrpc_ctrl_kalloc(Structure): - pass - -struct_fastrpc_ctrl_kalloc._pack_ = 1 # source:False -struct_fastrpc_ctrl_kalloc._fields_ = [ - ('kalloc_support', ctypes.c_uint32), -] - -class struct_fastrpc_ioctl_control(Structure): - pass - -class union_fastrpc_ioctl_control_0(Union): - pass - -union_fastrpc_ioctl_control_0._pack_ = 1 # source:False -union_fastrpc_ioctl_control_0._fields_ = [ - ('lp', struct_fastrpc_ctrl_latency), - ('smmu', struct_fastrpc_ctrl_smmu), - ('kalloc', struct_fastrpc_ctrl_kalloc), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_fastrpc_ioctl_control._pack_ = 1 # source:False -struct_fastrpc_ioctl_control._anonymous_ = ('_0',) -struct_fastrpc_ioctl_control._fields_ = [ - ('req', ctypes.c_uint32), - ('_0', union_fastrpc_ioctl_control_0), -] - -FASTRPC_IOCTL_CONTROL = _IOWR ( 'R' , 12 , struct_fastrpc_ioctl_control ) # macro (from list) -class struct_smq_null_invoke(Structure): - pass - -struct_smq_null_invoke._pack_ = 1 # source:False -struct_smq_null_invoke._fields_ = [ - ('ctx', ctypes.c_uint64), - ('handle', ctypes.c_uint32), - ('sc', ctypes.c_uint32), -] - -class struct_smq_phy_page(Structure): - pass - -struct_smq_phy_page._pack_ = 1 # source:False -struct_smq_phy_page._fields_ = [ - ('addr', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -class struct_smq_invoke_buf(Structure): - pass - -struct_smq_invoke_buf._pack_ = 1 # source:False -struct_smq_invoke_buf._fields_ = [ - ('num', ctypes.c_int32), - ('pgidx', ctypes.c_int32), -] - -class struct_smq_invoke(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('header', struct_smq_null_invoke), - ('page', struct_smq_phy_page), - ] - -class struct_smq_msg(Structure): - pass - -struct_smq_msg._pack_ = 1 # source:False -struct_smq_msg._fields_ = [ - ('pid', ctypes.c_uint32), - ('tid', ctypes.c_uint32), - ('invoke', struct_smq_invoke), -] - -class struct_smq_invoke_rsp(Structure): - pass - -struct_smq_invoke_rsp._pack_ = 1 # source:False -struct_smq_invoke_rsp._fields_ = [ - ('ctx', ctypes.c_uint64), - ('retval', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - +class struct_remote_dma_handle64(Struct): pass uint32_t = ctypes.c_uint32 -FASTRPC_IOCTL_SETMODE = _IOWR ( 'R' , 5 , uint32_t ) # macro (from list) -FASTRPC_IOCTL_GETINFO = _IOWR ( 'R' , 8 , uint32_t ) # macro (from list) -try: - smq_invoke_buf_start = _libraries['FIXME_STUB'].smq_invoke_buf_start - smq_invoke_buf_start.restype = ctypes.POINTER(struct_smq_invoke_buf) - smq_invoke_buf_start.argtypes = [ctypes.POINTER(union_remote_arg64), uint32_t] -except AttributeError: - pass -try: - smq_phy_page_start = _libraries['FIXME_STUB'].smq_phy_page_start - smq_phy_page_start.restype = ctypes.POINTER(struct_smq_phy_page) - smq_phy_page_start.argtypes = [uint32_t, ctypes.POINTER(struct_smq_invoke_buf)] -except AttributeError: - pass -REMOTE_DEFAULT_H = True # macro -def REMOTE_SCALARS_METHOD_ATTR(dwScalars): # macro - return (((dwScalars)>>29)&0x7) -def REMOTE_SCALARS_METHOD(dwScalars): # macro - return (((dwScalars)>>24)&0x1f) -def __QAIC_REMOTE(ff): # macro - return ff -__QAIC_REMOTE_EXPORT = True # macro -__QAIC_REMOTE_ATTRIBUTE = True # macro -NUM_DOMAINS = 4 # macro -NUM_SESSIONS = 2 # macro -DOMAIN_ID_MASK = 3 # macro -DEFAULT_DOMAIN_ID = 0 # macro -ADSP_DOMAIN_ID = 0 # macro -MDSP_DOMAIN_ID = 1 # macro -SDSP_DOMAIN_ID = 2 # macro -CDSP_DOMAIN_ID = 3 # macro -ADSP_DOMAIN = "&_dom=adsp" # macro -MDSP_DOMAIN = "&_dom=mdsp" # macro -SDSP_DOMAIN = "&_dom=sdsp" # macro -CDSP_DOMAIN = "&_dom=cdsp" # macro -FASTRPC_WAKELOCK_CONTROL_SUPPORTED = 1 # macro -REMOTE_MODE_PARALLEL = 0 # macro -REMOTE_MODE_SERIAL = 1 # macro -# ITRANSPORT_PREFIX = "'\":;./\\" # macro +struct_remote_dma_handle64._fields_ = [ + ('fd', ctypes.c_int32), + ('offset', uint32_t), + ('len', uint32_t), +] +class union_remote_arg64(ctypes.Union): pass +union_remote_arg64._fields_ = [ + ('buf', struct_remote_buf64), + ('dma', struct_remote_dma_handle64), + ('h', uint32_t), +] +class struct_remote_buf(Struct): pass +struct_remote_buf._fields_ = [ + ('pv', ctypes.c_void_p), + ('len', size_t), +] +class struct_remote_dma_handle(Struct): pass +struct_remote_dma_handle._fields_ = [ + ('fd', ctypes.c_int32), + ('offset', uint32_t), +] +class union_remote_arg(ctypes.Union): pass +union_remote_arg._fields_ = [ + ('buf', struct_remote_buf), + ('dma', struct_remote_dma_handle), + ('h', uint32_t), +] +class struct_fastrpc_ioctl_invoke(Struct): pass +struct_fastrpc_ioctl_invoke._fields_ = [ + ('handle', uint32_t), + ('sc', uint32_t), + ('pra', ctypes.POINTER(union_remote_arg)), +] +class struct_fastrpc_ioctl_invoke_fd(Struct): pass +struct_fastrpc_ioctl_invoke_fd._fields_ = [ + ('inv', struct_fastrpc_ioctl_invoke), + ('fds', ctypes.POINTER(ctypes.c_int32)), +] +class struct_fastrpc_ioctl_invoke_attrs(Struct): pass +struct_fastrpc_ioctl_invoke_attrs._fields_ = [ + ('inv', struct_fastrpc_ioctl_invoke), + ('fds', ctypes.POINTER(ctypes.c_int32)), + ('attrs', ctypes.POINTER(ctypes.c_uint32)), +] +class struct_fastrpc_ioctl_invoke_crc(Struct): pass +struct_fastrpc_ioctl_invoke_crc._fields_ = [ + ('inv', struct_fastrpc_ioctl_invoke), + ('fds', ctypes.POINTER(ctypes.c_int32)), + ('attrs', ctypes.POINTER(ctypes.c_uint32)), + ('crc', ctypes.POINTER(ctypes.c_uint32)), +] +class struct_fastrpc_ioctl_init(Struct): pass +uintptr_t = ctypes.c_uint64 +int32_t = ctypes.c_int32 +struct_fastrpc_ioctl_init._fields_ = [ + ('flags', uint32_t), + ('file', uintptr_t), + ('filelen', uint32_t), + ('filefd', int32_t), + ('mem', uintptr_t), + ('memlen', uint32_t), + ('memfd', int32_t), +] +class struct_fastrpc_ioctl_init_attrs(Struct): pass +struct_fastrpc_ioctl_init_attrs._fields_ = [ + ('init', struct_fastrpc_ioctl_init), + ('attrs', ctypes.c_int32), + ('siglen', ctypes.c_uint32), +] +class struct_fastrpc_ioctl_munmap(Struct): pass +struct_fastrpc_ioctl_munmap._fields_ = [ + ('vaddrout', uintptr_t), + ('size', size_t), +] +class struct_fastrpc_ioctl_munmap_64(Struct): pass +struct_fastrpc_ioctl_munmap_64._fields_ = [ + ('vaddrout', uint64_t), + ('size', size_t), +] +class struct_fastrpc_ioctl_mmap(Struct): pass +struct_fastrpc_ioctl_mmap._fields_ = [ + ('fd', ctypes.c_int32), + ('flags', uint32_t), + ('vaddrin', uintptr_t), + ('size', size_t), + ('vaddrout', uintptr_t), +] +class struct_fastrpc_ioctl_mmap_64(Struct): pass +struct_fastrpc_ioctl_mmap_64._fields_ = [ + ('fd', ctypes.c_int32), + ('flags', uint32_t), + ('vaddrin', uint64_t), + ('size', size_t), + ('vaddrout', uint64_t), +] +class struct_fastrpc_ioctl_munmap_fd(Struct): pass +ssize_t = ctypes.c_int64 +struct_fastrpc_ioctl_munmap_fd._fields_ = [ + ('fd', ctypes.c_int32), + ('flags', uint32_t), + ('va', uintptr_t), + ('len', ssize_t), +] +class struct_fastrpc_ioctl_perf(Struct): pass +struct_fastrpc_ioctl_perf._fields_ = [ + ('data', uintptr_t), + ('numkeys', uint32_t), + ('keys', uintptr_t), +] +class struct_fastrpc_ctrl_latency(Struct): pass +struct_fastrpc_ctrl_latency._fields_ = [ + ('enable', uint32_t), + ('level', uint32_t), +] +class struct_fastrpc_ctrl_smmu(Struct): pass +struct_fastrpc_ctrl_smmu._fields_ = [ + ('sharedcb', uint32_t), +] +class struct_fastrpc_ctrl_kalloc(Struct): pass +struct_fastrpc_ctrl_kalloc._fields_ = [ + ('kalloc_support', uint32_t), +] +class struct_fastrpc_ioctl_control(Struct): pass +class struct_fastrpc_ioctl_control_0(ctypes.Union): pass +struct_fastrpc_ioctl_control_0._fields_ = [ + ('lp', struct_fastrpc_ctrl_latency), + ('smmu', struct_fastrpc_ctrl_smmu), + ('kalloc', struct_fastrpc_ctrl_kalloc), +] +struct_fastrpc_ioctl_control._anonymous_ = ['_0'] +struct_fastrpc_ioctl_control._fields_ = [ + ('req', uint32_t), + ('_0', struct_fastrpc_ioctl_control_0), +] +class struct_smq_null_invoke(Struct): pass +struct_smq_null_invoke._fields_ = [ + ('ctx', uint64_t), + ('handle', uint32_t), + ('sc', uint32_t), +] +class struct_smq_phy_page(Struct): pass +struct_smq_phy_page._fields_ = [ + ('addr', uint64_t), + ('size', uint64_t), +] +class struct_smq_invoke_buf(Struct): pass +struct_smq_invoke_buf._fields_ = [ + ('num', ctypes.c_int32), + ('pgidx', ctypes.c_int32), +] +class struct_smq_invoke(Struct): pass +struct_smq_invoke._fields_ = [ + ('header', struct_smq_null_invoke), + ('page', struct_smq_phy_page), +] +class struct_smq_msg(Struct): pass +struct_smq_msg._fields_ = [ + ('pid', uint32_t), + ('tid', uint32_t), + ('invoke', struct_smq_invoke), +] +class struct_smq_invoke_rsp(Struct): pass +struct_smq_invoke_rsp._fields_ = [ + ('ctx', uint64_t), + ('retval', ctypes.c_int32), +] remote_handle = ctypes.c_uint32 remote_handle64 = ctypes.c_uint64 fastrpc_async_jobid = ctypes.c_uint64 -class struct_c__SA_remote_buf(Structure): - pass - -struct_c__SA_remote_buf._pack_ = 1 # source:False -struct_c__SA_remote_buf._fields_ = [ - ('pv', ctypes.POINTER(None)), - ('nLen', ctypes.c_uint64), +class remote_buf(Struct): pass +remote_buf._fields_ = [ + ('pv', ctypes.c_void_p), + ('nLen', size_t), ] - -remote_buf = struct_c__SA_remote_buf -class struct_c__SA_remote_dma_handle(Structure): - pass - -struct_c__SA_remote_dma_handle._pack_ = 1 # source:False -struct_c__SA_remote_dma_handle._fields_ = [ - ('fd', ctypes.c_int32), - ('offset', ctypes.c_uint32), +class remote_dma_handle(Struct): pass +remote_dma_handle._fields_ = [ + ('fd', int32_t), + ('offset', uint32_t), ] - -remote_dma_handle = struct_c__SA_remote_dma_handle -class union_c__UA_remote_arg(Union): - pass - -union_c__UA_remote_arg._pack_ = 1 # source:False -union_c__UA_remote_arg._fields_ = [ - ('buf', remote_buf), - ('h', ctypes.c_uint32), - ('h64', ctypes.c_uint64), - ('dma', remote_dma_handle), - ('PADDING_0', ctypes.c_ubyte * 8), +class remote_arg(ctypes.Union): pass +remote_arg._fields_ = [ + ('buf', remote_buf), + ('h', remote_handle), + ('h64', remote_handle64), + ('dma', remote_dma_handle), ] +enum_fastrpc_async_notify_type = CEnum(ctypes.c_uint32) +FASTRPC_ASYNC_NO_SYNC = enum_fastrpc_async_notify_type.define('FASTRPC_ASYNC_NO_SYNC', 0) +FASTRPC_ASYNC_CALLBACK = enum_fastrpc_async_notify_type.define('FASTRPC_ASYNC_CALLBACK', 1) +FASTRPC_ASYNC_POLL = enum_fastrpc_async_notify_type.define('FASTRPC_ASYNC_POLL', 2) +FASTRPC_ASYNC_TYPE_MAX = enum_fastrpc_async_notify_type.define('FASTRPC_ASYNC_TYPE_MAX', 3) -remote_arg = union_c__UA_remote_arg -remote_arg_t = remote_arg # macro - -# values for enumeration 'fastrpc_async_notify_type' -fastrpc_async_notify_type__enumvalues = { - 0: 'FASTRPC_ASYNC_NO_SYNC', - 1: 'FASTRPC_ASYNC_CALLBACK', - 2: 'FASTRPC_ASYNC_POLL', - 3: 'FASTRPC_ASYNC_TYPE_MAX', -} -FASTRPC_ASYNC_NO_SYNC = 0 -FASTRPC_ASYNC_CALLBACK = 1 -FASTRPC_ASYNC_POLL = 2 -FASTRPC_ASYNC_TYPE_MAX = 3 -fastrpc_async_notify_type = ctypes.c_uint32 # enum -class struct_fastrpc_async_callback(Structure): - pass - -struct_fastrpc_async_callback._pack_ = 1 # source:False +class struct_fastrpc_async_callback(Struct): pass struct_fastrpc_async_callback._fields_ = [ - ('fn', ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_int32)), - ('context', ctypes.POINTER(None)), + ('fn', ctypes.CFUNCTYPE(None, fastrpc_async_jobid, ctypes.c_void_p, ctypes.c_int32)), + ('context', ctypes.c_void_p), ] - fastrpc_async_callback_t = struct_fastrpc_async_callback -class struct_fastrpc_async_descriptor(Structure): - pass - -class union_fastrpc_async_descriptor_0(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('cb', fastrpc_async_callback_t), - ] - -struct_fastrpc_async_descriptor._pack_ = 1 # source:False -struct_fastrpc_async_descriptor._anonymous_ = ('_0',) +class struct_fastrpc_async_descriptor(Struct): pass +class struct_fastrpc_async_descriptor_0(ctypes.Union): pass +struct_fastrpc_async_descriptor_0._fields_ = [ + ('cb', fastrpc_async_callback_t), +] +struct_fastrpc_async_descriptor._anonymous_ = ['_0'] struct_fastrpc_async_descriptor._fields_ = [ - ('type', fastrpc_async_notify_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('jobid', ctypes.c_uint64), - ('_0', union_fastrpc_async_descriptor_0), + ('type', enum_fastrpc_async_notify_type), + ('jobid', fastrpc_async_jobid), + ('_0', struct_fastrpc_async_descriptor_0), ] - fastrpc_async_descriptor_t = struct_fastrpc_async_descriptor +enum_fastrpc_process_type = CEnum(ctypes.c_uint32) +PROCESS_TYPE_SIGNED = enum_fastrpc_process_type.define('PROCESS_TYPE_SIGNED', 0) +PROCESS_TYPE_UNSIGNED = enum_fastrpc_process_type.define('PROCESS_TYPE_UNSIGNED', 1) -# values for enumeration 'fastrpc_process_type' -fastrpc_process_type__enumvalues = { - 0: 'PROCESS_TYPE_SIGNED', - 1: 'PROCESS_TYPE_UNSIGNED', -} -PROCESS_TYPE_SIGNED = 0 -PROCESS_TYPE_UNSIGNED = 1 -fastrpc_process_type = ctypes.c_uint32 # enum -try: - remote_handle_open = _libraries['FIXME_STUB'].remote_handle_open - remote_handle_open.restype = ctypes.c_int32 - remote_handle_open.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - remote_handle64_open = _libraries['FIXME_STUB'].remote_handle64_open - remote_handle64_open.restype = ctypes.c_int32 - remote_handle64_open.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - remote_handle_invoke = _libraries['FIXME_STUB'].remote_handle_invoke - remote_handle_invoke.restype = ctypes.c_int32 - remote_handle_invoke.argtypes = [remote_handle, uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle64_invoke = _libraries['FIXME_STUB'].remote_handle64_invoke - remote_handle64_invoke.restype = ctypes.c_int32 - remote_handle64_invoke.argtypes = [remote_handle64, uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle_invoke_async = _libraries['FIXME_STUB'].remote_handle_invoke_async - remote_handle_invoke_async.restype = ctypes.c_int32 - remote_handle_invoke_async.argtypes = [remote_handle, ctypes.POINTER(struct_fastrpc_async_descriptor), uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle64_invoke_async = _libraries['FIXME_STUB'].remote_handle64_invoke_async - remote_handle64_invoke_async.restype = ctypes.c_int32 - remote_handle64_invoke_async.argtypes = [remote_handle64, ctypes.POINTER(struct_fastrpc_async_descriptor), uint32_t, ctypes.POINTER(union_c__UA_remote_arg)] -except AttributeError: - pass -try: - remote_handle_close = _libraries['FIXME_STUB'].remote_handle_close - remote_handle_close.restype = ctypes.c_int32 - remote_handle_close.argtypes = [remote_handle] -except AttributeError: - pass -try: - remote_handle64_close = _libraries['FIXME_STUB'].remote_handle64_close - remote_handle64_close.restype = ctypes.c_int32 - remote_handle64_close.argtypes = [remote_handle64] -except AttributeError: - pass +enum_handle_control_req_id = CEnum(ctypes.c_uint32) +DSPRPC_CONTROL_LATENCY = enum_handle_control_req_id.define('DSPRPC_CONTROL_LATENCY', 1) +DSPRPC_GET_DSP_INFO = enum_handle_control_req_id.define('DSPRPC_GET_DSP_INFO', 2) +DSPRPC_CONTROL_WAKELOCK = enum_handle_control_req_id.define('DSPRPC_CONTROL_WAKELOCK', 3) +DSPRPC_GET_DOMAIN = enum_handle_control_req_id.define('DSPRPC_GET_DOMAIN', 4) -# values for enumeration 'handle_control_req_id' -handle_control_req_id__enumvalues = { - 1: 'DSPRPC_CONTROL_LATENCY', - 2: 'DSPRPC_GET_DSP_INFO', - 3: 'DSPRPC_CONTROL_WAKELOCK', - 4: 'DSPRPC_GET_DOMAIN', -} -DSPRPC_CONTROL_LATENCY = 1 -DSPRPC_GET_DSP_INFO = 2 -DSPRPC_CONTROL_WAKELOCK = 3 -DSPRPC_GET_DOMAIN = 4 -handle_control_req_id = ctypes.c_uint32 # enum +enum_remote_rpc_latency_flags = CEnum(ctypes.c_uint32) +RPC_DISABLE_QOS = enum_remote_rpc_latency_flags.define('RPC_DISABLE_QOS', 0) +RPC_PM_QOS = enum_remote_rpc_latency_flags.define('RPC_PM_QOS', 1) +RPC_ADAPTIVE_QOS = enum_remote_rpc_latency_flags.define('RPC_ADAPTIVE_QOS', 2) +RPC_POLL_QOS = enum_remote_rpc_latency_flags.define('RPC_POLL_QOS', 3) -# values for enumeration 'remote_rpc_latency_flags' -remote_rpc_latency_flags__enumvalues = { - 0: 'RPC_DISABLE_QOS', - 1: 'RPC_PM_QOS', - 2: 'RPC_ADAPTIVE_QOS', - 3: 'RPC_POLL_QOS', -} -RPC_DISABLE_QOS = 0 -RPC_PM_QOS = 1 -RPC_ADAPTIVE_QOS = 2 -RPC_POLL_QOS = 3 -remote_rpc_latency_flags = ctypes.c_uint32 # enum -remote_rpc_control_latency_t = remote_rpc_latency_flags -remote_rpc_control_latency_t__enumvalues = remote_rpc_latency_flags__enumvalues -class struct_remote_rpc_control_latency(Structure): - pass - -struct_remote_rpc_control_latency._pack_ = 1 # source:False +remote_rpc_control_latency_t = enum_remote_rpc_latency_flags +class struct_remote_rpc_control_latency(Struct): pass struct_remote_rpc_control_latency._fields_ = [ - ('enable', remote_rpc_control_latency_t), - ('latency', ctypes.c_uint32), + ('enable', remote_rpc_control_latency_t), + ('latency', uint32_t), ] +enum_remote_dsp_attributes = CEnum(ctypes.c_uint32) +DOMAIN_SUPPORT = enum_remote_dsp_attributes.define('DOMAIN_SUPPORT', 0) +UNSIGNED_PD_SUPPORT = enum_remote_dsp_attributes.define('UNSIGNED_PD_SUPPORT', 1) +HVX_SUPPORT_64B = enum_remote_dsp_attributes.define('HVX_SUPPORT_64B', 2) +HVX_SUPPORT_128B = enum_remote_dsp_attributes.define('HVX_SUPPORT_128B', 3) +VTCM_PAGE = enum_remote_dsp_attributes.define('VTCM_PAGE', 4) +VTCM_COUNT = enum_remote_dsp_attributes.define('VTCM_COUNT', 5) +ARCH_VER = enum_remote_dsp_attributes.define('ARCH_VER', 6) +HMX_SUPPORT_DEPTH = enum_remote_dsp_attributes.define('HMX_SUPPORT_DEPTH', 7) +HMX_SUPPORT_SPATIAL = enum_remote_dsp_attributes.define('HMX_SUPPORT_SPATIAL', 8) +ASYNC_FASTRPC_SUPPORT = enum_remote_dsp_attributes.define('ASYNC_FASTRPC_SUPPORT', 9) +STATUS_NOTIFICATION_SUPPORT = enum_remote_dsp_attributes.define('STATUS_NOTIFICATION_SUPPORT', 10) +FASTRPC_MAX_DSP_ATTRIBUTES = enum_remote_dsp_attributes.define('FASTRPC_MAX_DSP_ATTRIBUTES', 11) - -# values for enumeration 'remote_dsp_attributes' -remote_dsp_attributes__enumvalues = { - 0: 'DOMAIN_SUPPORT', - 1: 'UNSIGNED_PD_SUPPORT', - 2: 'HVX_SUPPORT_64B', - 3: 'HVX_SUPPORT_128B', - 4: 'VTCM_PAGE', - 5: 'VTCM_COUNT', - 6: 'ARCH_VER', - 7: 'HMX_SUPPORT_DEPTH', - 8: 'HMX_SUPPORT_SPATIAL', - 9: 'ASYNC_FASTRPC_SUPPORT', - 10: 'STATUS_NOTIFICATION_SUPPORT', - 11: 'FASTRPC_MAX_DSP_ATTRIBUTES', -} -DOMAIN_SUPPORT = 0 -UNSIGNED_PD_SUPPORT = 1 -HVX_SUPPORT_64B = 2 -HVX_SUPPORT_128B = 3 -VTCM_PAGE = 4 -VTCM_COUNT = 5 -ARCH_VER = 6 -HMX_SUPPORT_DEPTH = 7 -HMX_SUPPORT_SPATIAL = 8 -ASYNC_FASTRPC_SUPPORT = 9 -STATUS_NOTIFICATION_SUPPORT = 10 -FASTRPC_MAX_DSP_ATTRIBUTES = 11 -remote_dsp_attributes = ctypes.c_uint32 # enum -class struct_remote_dsp_capability(Structure): - pass - -struct_remote_dsp_capability._pack_ = 1 # source:False +class struct_remote_dsp_capability(Struct): pass struct_remote_dsp_capability._fields_ = [ - ('domain', ctypes.c_uint32), - ('attribute_ID', ctypes.c_uint32), - ('capability', ctypes.c_uint32), + ('domain', uint32_t), + ('attribute_ID', uint32_t), + ('capability', uint32_t), ] - fastrpc_capability = struct_remote_dsp_capability -class struct_remote_rpc_control_wakelock(Structure): - pass - -struct_remote_rpc_control_wakelock._pack_ = 1 # source:False +class struct_remote_rpc_control_wakelock(Struct): pass struct_remote_rpc_control_wakelock._fields_ = [ - ('enable', ctypes.c_uint32), + ('enable', uint32_t), ] - -class struct_remote_rpc_get_domain(Structure): - pass - -struct_remote_rpc_get_domain._pack_ = 1 # source:False +class struct_remote_rpc_get_domain(Struct): pass struct_remote_rpc_get_domain._fields_ = [ - ('domain', ctypes.c_int32), + ('domain', ctypes.c_int32), ] - remote_rpc_get_domain_t = struct_remote_rpc_get_domain -try: - remote_handle_control = _libraries['FIXME_STUB'].remote_handle_control - remote_handle_control.restype = ctypes.c_int32 - remote_handle_control.argtypes = [uint32_t, ctypes.POINTER(None), uint32_t] -except AttributeError: - pass -try: - remote_handle64_control = _libraries['FIXME_STUB'].remote_handle64_control - remote_handle64_control.restype = ctypes.c_int32 - remote_handle64_control.argtypes = [remote_handle64, uint32_t, ctypes.POINTER(None), uint32_t] -except AttributeError: - pass +enum_session_control_req_id = CEnum(ctypes.c_uint32) +FASTRPC_THREAD_PARAMS = enum_session_control_req_id.define('FASTRPC_THREAD_PARAMS', 1) +DSPRPC_CONTROL_UNSIGNED_MODULE = enum_session_control_req_id.define('DSPRPC_CONTROL_UNSIGNED_MODULE', 2) +FASTRPC_RELATIVE_THREAD_PRIORITY = enum_session_control_req_id.define('FASTRPC_RELATIVE_THREAD_PRIORITY', 4) +FASTRPC_REMOTE_PROCESS_KILL = enum_session_control_req_id.define('FASTRPC_REMOTE_PROCESS_KILL', 6) +FASTRPC_SESSION_CLOSE = enum_session_control_req_id.define('FASTRPC_SESSION_CLOSE', 7) +FASTRPC_CONTROL_PD_DUMP = enum_session_control_req_id.define('FASTRPC_CONTROL_PD_DUMP', 8) +FASTRPC_REMOTE_PROCESS_EXCEPTION = enum_session_control_req_id.define('FASTRPC_REMOTE_PROCESS_EXCEPTION', 9) +FASTRPC_REMOTE_PROCESS_TYPE = enum_session_control_req_id.define('FASTRPC_REMOTE_PROCESS_TYPE', 10) +FASTRPC_REGISTER_STATUS_NOTIFICATIONS = enum_session_control_req_id.define('FASTRPC_REGISTER_STATUS_NOTIFICATIONS', 11) -# values for enumeration 'session_control_req_id' -session_control_req_id__enumvalues = { - 1: 'FASTRPC_THREAD_PARAMS', - 2: 'DSPRPC_CONTROL_UNSIGNED_MODULE', - 4: 'FASTRPC_RELATIVE_THREAD_PRIORITY', - 6: 'FASTRPC_REMOTE_PROCESS_KILL', - 7: 'FASTRPC_SESSION_CLOSE', - 8: 'FASTRPC_CONTROL_PD_DUMP', - 9: 'FASTRPC_REMOTE_PROCESS_EXCEPTION', - 10: 'FASTRPC_REMOTE_PROCESS_TYPE', - 11: 'FASTRPC_REGISTER_STATUS_NOTIFICATIONS', -} -FASTRPC_THREAD_PARAMS = 1 -DSPRPC_CONTROL_UNSIGNED_MODULE = 2 -FASTRPC_RELATIVE_THREAD_PRIORITY = 4 -FASTRPC_REMOTE_PROCESS_KILL = 6 -FASTRPC_SESSION_CLOSE = 7 -FASTRPC_CONTROL_PD_DUMP = 8 -FASTRPC_REMOTE_PROCESS_EXCEPTION = 9 -FASTRPC_REMOTE_PROCESS_TYPE = 10 -FASTRPC_REGISTER_STATUS_NOTIFICATIONS = 11 -session_control_req_id = ctypes.c_uint32 # enum -class struct_remote_rpc_thread_params(Structure): - pass - -struct_remote_rpc_thread_params._pack_ = 1 # source:False +class struct_remote_rpc_thread_params(Struct): pass struct_remote_rpc_thread_params._fields_ = [ - ('domain', ctypes.c_int32), - ('prio', ctypes.c_int32), - ('stack_size', ctypes.c_int32), + ('domain', ctypes.c_int32), + ('prio', ctypes.c_int32), + ('stack_size', ctypes.c_int32), ] - -class struct_remote_rpc_control_unsigned_module(Structure): - pass - -struct_remote_rpc_control_unsigned_module._pack_ = 1 # source:False +class struct_remote_rpc_control_unsigned_module(Struct): pass struct_remote_rpc_control_unsigned_module._fields_ = [ - ('domain', ctypes.c_int32), - ('enable', ctypes.c_int32), + ('domain', ctypes.c_int32), + ('enable', ctypes.c_int32), ] - -class struct_remote_rpc_relative_thread_priority(Structure): - pass - -struct_remote_rpc_relative_thread_priority._pack_ = 1 # source:False +class struct_remote_rpc_relative_thread_priority(Struct): pass struct_remote_rpc_relative_thread_priority._fields_ = [ - ('domain', ctypes.c_int32), - ('relative_thread_priority', ctypes.c_int32), + ('domain', ctypes.c_int32), + ('relative_thread_priority', ctypes.c_int32), ] - -class struct_remote_rpc_process_clean_params(Structure): - pass - -struct_remote_rpc_process_clean_params._pack_ = 1 # source:False +class struct_remote_rpc_process_clean_params(Struct): pass struct_remote_rpc_process_clean_params._fields_ = [ - ('domain', ctypes.c_int32), + ('domain', ctypes.c_int32), ] - -class struct_remote_rpc_session_close(Structure): - pass - -struct_remote_rpc_session_close._pack_ = 1 # source:False +class struct_remote_rpc_session_close(Struct): pass struct_remote_rpc_session_close._fields_ = [ - ('domain', ctypes.c_int32), + ('domain', ctypes.c_int32), ] - -class struct_remote_rpc_control_pd_dump(Structure): - pass - -struct_remote_rpc_control_pd_dump._pack_ = 1 # source:False +class struct_remote_rpc_control_pd_dump(Struct): pass struct_remote_rpc_control_pd_dump._fields_ = [ - ('domain', ctypes.c_int32), - ('enable', ctypes.c_int32), + ('domain', ctypes.c_int32), + ('enable', ctypes.c_int32), ] - -class struct_remote_process_type(Structure): - pass - -struct_remote_process_type._pack_ = 1 # source:False +class struct_remote_process_type(Struct): pass struct_remote_process_type._fields_ = [ - ('domain', ctypes.c_int32), - ('process_type', ctypes.c_int32), + ('domain', ctypes.c_int32), + ('process_type', ctypes.c_int32), ] - remote_rpc_process_exception = struct_remote_rpc_process_clean_params +enum_remote_rpc_status_flags = CEnum(ctypes.c_uint32) +FASTRPC_USER_PD_UP = enum_remote_rpc_status_flags.define('FASTRPC_USER_PD_UP', 0) +FASTRPC_USER_PD_EXIT = enum_remote_rpc_status_flags.define('FASTRPC_USER_PD_EXIT', 1) +FASTRPC_USER_PD_FORCE_KILL = enum_remote_rpc_status_flags.define('FASTRPC_USER_PD_FORCE_KILL', 2) +FASTRPC_USER_PD_EXCEPTION = enum_remote_rpc_status_flags.define('FASTRPC_USER_PD_EXCEPTION', 3) +FASTRPC_DSP_SSR = enum_remote_rpc_status_flags.define('FASTRPC_DSP_SSR', 4) -# values for enumeration 'remote_rpc_status_flags' -remote_rpc_status_flags__enumvalues = { - 0: 'FASTRPC_USER_PD_UP', - 1: 'FASTRPC_USER_PD_EXIT', - 2: 'FASTRPC_USER_PD_FORCE_KILL', - 3: 'FASTRPC_USER_PD_EXCEPTION', - 4: 'FASTRPC_DSP_SSR', -} -FASTRPC_USER_PD_UP = 0 -FASTRPC_USER_PD_EXIT = 1 -FASTRPC_USER_PD_FORCE_KILL = 2 -FASTRPC_USER_PD_EXCEPTION = 3 -FASTRPC_DSP_SSR = 4 -remote_rpc_status_flags = ctypes.c_uint32 # enum -remote_rpc_status_flags_t = remote_rpc_status_flags -remote_rpc_status_flags_t__enumvalues = remote_rpc_status_flags__enumvalues -fastrpc_notif_fn_t = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, remote_rpc_status_flags) -class struct_remote_rpc_notif_register(Structure): - pass - -struct_remote_rpc_notif_register._pack_ = 1 # source:False +remote_rpc_status_flags_t = enum_remote_rpc_status_flags +fastrpc_notif_fn_t = ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.c_void_p, ctypes.c_int32, ctypes.c_int32, enum_remote_rpc_status_flags) +class struct_remote_rpc_notif_register(Struct): pass struct_remote_rpc_notif_register._fields_ = [ - ('context', ctypes.POINTER(None)), - ('domain', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('notifier_fn', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, remote_rpc_status_flags)), + ('context', ctypes.c_void_p), + ('domain', ctypes.c_int32), + ('notifier_fn', fastrpc_notif_fn_t), ] - remote_rpc_notif_register_t = struct_remote_rpc_notif_register -try: - remote_session_control = _libraries['FIXME_STUB'].remote_session_control - remote_session_control.restype = ctypes.c_int32 - remote_session_control.argtypes = [uint32_t, ctypes.POINTER(None), uint32_t] -except AttributeError: - pass -try: - remote_mmap = _libraries['FIXME_STUB'].remote_mmap - remote_mmap.restype = ctypes.c_int32 - remote_mmap.argtypes = [ctypes.c_int32, uint32_t, uint32_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - remote_munmap = _libraries['FIXME_STUB'].remote_munmap - remote_munmap.restype = ctypes.c_int32 - remote_munmap.argtypes = [uint32_t, ctypes.c_int32] -except AttributeError: - pass +enum_remote_mem_map_flags = CEnum(ctypes.c_uint32) +REMOTE_MAP_MEM_STATIC = enum_remote_mem_map_flags.define('REMOTE_MAP_MEM_STATIC', 0) +REMOTE_MAP_MAX_FLAG = enum_remote_mem_map_flags.define('REMOTE_MAP_MAX_FLAG', 1) -# values for enumeration 'remote_mem_map_flags' -remote_mem_map_flags__enumvalues = { - 0: 'REMOTE_MAP_MEM_STATIC', - 1: 'REMOTE_MAP_MAX_FLAG', -} -REMOTE_MAP_MEM_STATIC = 0 -REMOTE_MAP_MAX_FLAG = 1 -remote_mem_map_flags = ctypes.c_uint32 # enum -uint64_t = ctypes.c_uint64 -size_t = ctypes.c_uint64 -try: - remote_mem_map = _libraries['FIXME_STUB'].remote_mem_map - remote_mem_map.restype = ctypes.c_int32 - remote_mem_map.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.c_int32, uint64_t, size_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - remote_mem_unmap = _libraries['FIXME_STUB'].remote_mem_unmap - remote_mem_unmap.restype = ctypes.c_int32 - remote_mem_unmap.argtypes = [ctypes.c_int32, uint64_t, size_t] -except AttributeError: - pass +enum_remote_buf_attributes = CEnum(ctypes.c_uint32) +FASTRPC_ATTR_NON_COHERENT = enum_remote_buf_attributes.define('FASTRPC_ATTR_NON_COHERENT', 2) +FASTRPC_ATTR_COHERENT = enum_remote_buf_attributes.define('FASTRPC_ATTR_COHERENT', 4) +FASTRPC_ATTR_KEEP_MAP = enum_remote_buf_attributes.define('FASTRPC_ATTR_KEEP_MAP', 8) +FASTRPC_ATTR_NOMAP = enum_remote_buf_attributes.define('FASTRPC_ATTR_NOMAP', 16) +FASTRPC_ATTR_FORCE_NOFLUSH = enum_remote_buf_attributes.define('FASTRPC_ATTR_FORCE_NOFLUSH', 32) +FASTRPC_ATTR_FORCE_NOINVALIDATE = enum_remote_buf_attributes.define('FASTRPC_ATTR_FORCE_NOINVALIDATE', 64) +FASTRPC_ATTR_TRY_MAP_STATIC = enum_remote_buf_attributes.define('FASTRPC_ATTR_TRY_MAP_STATIC', 128) -# values for enumeration 'remote_buf_attributes' -remote_buf_attributes__enumvalues = { - 2: 'FASTRPC_ATTR_NON_COHERENT', - 4: 'FASTRPC_ATTR_COHERENT', - 8: 'FASTRPC_ATTR_KEEP_MAP', - 16: 'FASTRPC_ATTR_NOMAP', - 32: 'FASTRPC_ATTR_FORCE_NOFLUSH', - 64: 'FASTRPC_ATTR_FORCE_NOINVALIDATE', - 128: 'FASTRPC_ATTR_TRY_MAP_STATIC', -} -FASTRPC_ATTR_NON_COHERENT = 2 -FASTRPC_ATTR_COHERENT = 4 -FASTRPC_ATTR_KEEP_MAP = 8 -FASTRPC_ATTR_NOMAP = 16 -FASTRPC_ATTR_FORCE_NOFLUSH = 32 -FASTRPC_ATTR_FORCE_NOINVALIDATE = 64 -FASTRPC_ATTR_TRY_MAP_STATIC = 128 -remote_buf_attributes = ctypes.c_uint32 # enum -try: - remote_register_buf_attr = _libraries['FIXME_STUB'].remote_register_buf_attr - remote_register_buf_attr.restype = None - remote_register_buf_attr.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - remote_register_buf = _libraries['FIXME_STUB'].remote_register_buf - remote_register_buf.restype = None - remote_register_buf.argtypes = [ctypes.POINTER(None), ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - remote_register_dma_handle_attr = _libraries['FIXME_STUB'].remote_register_dma_handle_attr - remote_register_dma_handle_attr.restype = ctypes.c_int32 - remote_register_dma_handle_attr.argtypes = [ctypes.c_int32, uint32_t, uint32_t] -except AttributeError: - pass -try: - remote_register_dma_handle = _libraries['FIXME_STUB'].remote_register_dma_handle - remote_register_dma_handle.restype = ctypes.c_int32 - remote_register_dma_handle.argtypes = [ctypes.c_int32, uint32_t] -except AttributeError: - pass -try: - remote_register_fd = _libraries['FIXME_STUB'].remote_register_fd - remote_register_fd.restype = ctypes.POINTER(None) - remote_register_fd.argtypes = [ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass -try: - fastrpc_async_get_status = _libraries['FIXME_STUB'].fastrpc_async_get_status - fastrpc_async_get_status.restype = ctypes.c_int32 - fastrpc_async_get_status.argtypes = [fastrpc_async_jobid, ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - fastrpc_release_async_job = _libraries['FIXME_STUB'].fastrpc_release_async_job - fastrpc_release_async_job.restype = ctypes.c_int32 - fastrpc_release_async_job.argtypes = [fastrpc_async_jobid] -except AttributeError: - pass -try: - remote_set_mode = _libraries['FIXME_STUB'].remote_set_mode - remote_set_mode.restype = ctypes.c_int32 - remote_set_mode.argtypes = [uint32_t] -except AttributeError: - pass +enum_fastrpc_map_flags = CEnum(ctypes.c_uint32) +FASTRPC_MAP_STATIC = enum_fastrpc_map_flags.define('FASTRPC_MAP_STATIC', 0) +FASTRPC_MAP_RESERVED = enum_fastrpc_map_flags.define('FASTRPC_MAP_RESERVED', 1) +FASTRPC_MAP_FD = enum_fastrpc_map_flags.define('FASTRPC_MAP_FD', 2) +FASTRPC_MAP_FD_DELAYED = enum_fastrpc_map_flags.define('FASTRPC_MAP_FD_DELAYED', 3) +FASTRPC_MAP_MAX = enum_fastrpc_map_flags.define('FASTRPC_MAP_MAX', 4) -# values for enumeration 'fastrpc_map_flags' -fastrpc_map_flags__enumvalues = { - 0: 'FASTRPC_MAP_STATIC', - 1: 'FASTRPC_MAP_RESERVED', - 2: 'FASTRPC_MAP_FD', - 3: 'FASTRPC_MAP_FD_DELAYED', - 4: 'FASTRPC_MAP_MAX', -} -FASTRPC_MAP_STATIC = 0 -FASTRPC_MAP_RESERVED = 1 -FASTRPC_MAP_FD = 2 -FASTRPC_MAP_FD_DELAYED = 3 -FASTRPC_MAP_MAX = 4 -fastrpc_map_flags = ctypes.c_uint32 # enum -try: - fastrpc_mmap = _libraries['FIXME_STUB'].fastrpc_mmap - fastrpc_mmap.restype = ctypes.c_int32 - fastrpc_mmap.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None), ctypes.c_int32, size_t, fastrpc_map_flags] -except AttributeError: - pass -try: - fastrpc_munmap = _libraries['FIXME_STUB'].fastrpc_munmap - fastrpc_munmap.restype = ctypes.c_int32 - fastrpc_munmap.argtypes = [ctypes.c_int32, ctypes.c_int32, ctypes.POINTER(None), size_t] -except AttributeError: - pass -_APPS_STD_H = True # macro -def __QAIC_HEADER(ff): # macro - return ff -__QAIC_HEADER_EXPORT = True # macro -__QAIC_HEADER_ATTRIBUTE = True # macro -def __QAIC_IMPL(ff): # macro - return ff -__QAIC_IMPL_EXPORT = True # macro -__QAIC_IMPL_ATTRIBUTE = True # macro -__QAIC_STRING1_OBJECT_DEFINED__ = True # macro -__STRING1_OBJECT__ = True # macro -class struct__cstring1_s(Structure): - pass - -struct__cstring1_s._pack_ = 1 # source:False +class struct__cstring1_s(Struct): pass struct__cstring1_s._fields_ = [ - ('data', ctypes.POINTER(ctypes.c_char)), - ('dataLen', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('data', ctypes.POINTER(ctypes.c_char)), + ('dataLen', ctypes.c_int32), ] - _cstring1_t = struct__cstring1_s apps_std_FILE = ctypes.c_int32 +enum_apps_std_SEEK = CEnum(ctypes.c_uint32) +APPS_STD_SEEK_SET = enum_apps_std_SEEK.define('APPS_STD_SEEK_SET', 0) +APPS_STD_SEEK_CUR = enum_apps_std_SEEK.define('APPS_STD_SEEK_CUR', 1) +APPS_STD_SEEK_END = enum_apps_std_SEEK.define('APPS_STD_SEEK_END', 2) +_32BIT_PLACEHOLDER_apps_std_SEEK = enum_apps_std_SEEK.define('_32BIT_PLACEHOLDER_apps_std_SEEK', 2147483647) -# values for enumeration 'apps_std_SEEK' -apps_std_SEEK__enumvalues = { - 0: 'APPS_STD_SEEK_SET', - 1: 'APPS_STD_SEEK_CUR', - 2: 'APPS_STD_SEEK_END', - 2147483647: '_32BIT_PLACEHOLDER_apps_std_SEEK', -} -APPS_STD_SEEK_SET = 0 -APPS_STD_SEEK_CUR = 1 -APPS_STD_SEEK_END = 2 -_32BIT_PLACEHOLDER_apps_std_SEEK = 2147483647 -apps_std_SEEK = ctypes.c_uint32 # enum -class struct_apps_std_DIR(Structure): - pass - -struct_apps_std_DIR._pack_ = 1 # source:False +apps_std_SEEK = enum_apps_std_SEEK +class struct_apps_std_DIR(Struct): pass +uint64 = ctypes.c_uint64 struct_apps_std_DIR._fields_ = [ - ('handle', ctypes.c_uint64), + ('handle', uint64), ] - apps_std_DIR = struct_apps_std_DIR -class struct_apps_std_DIRENT(Structure): - pass - -struct_apps_std_DIRENT._pack_ = 1 # source:False +class struct_apps_std_DIRENT(Struct): pass struct_apps_std_DIRENT._fields_ = [ - ('ino', ctypes.c_int32), - ('name', ctypes.c_char * 255), - ('PADDING_0', ctypes.c_ubyte), + ('ino', ctypes.c_int32), + ('name', (ctypes.c_char * 255)), ] - apps_std_DIRENT = struct_apps_std_DIRENT -class struct_apps_std_STAT(Structure): - pass - -struct_apps_std_STAT._pack_ = 1 # source:False +class struct_apps_std_STAT(Struct): pass +uint32 = ctypes.c_uint32 +int64 = ctypes.c_int64 struct_apps_std_STAT._fields_ = [ - ('tsz', ctypes.c_uint64), - ('dev', ctypes.c_uint64), - ('ino', ctypes.c_uint64), - ('mode', ctypes.c_uint32), - ('nlink', ctypes.c_uint32), - ('rdev', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('atime', ctypes.c_int64), - ('atimensec', ctypes.c_int64), - ('mtime', ctypes.c_int64), - ('mtimensec', ctypes.c_int64), - ('ctime', ctypes.c_int64), - ('ctimensec', ctypes.c_int64), + ('tsz', uint64), + ('dev', uint64), + ('ino', uint64), + ('mode', uint32), + ('nlink', uint32), + ('rdev', uint64), + ('size', uint64), + ('atime', int64), + ('atimensec', int64), + ('mtime', int64), + ('mtimensec', int64), + ('ctime', int64), + ('ctimensec', int64), ] - apps_std_STAT = struct_apps_std_STAT -try: - apps_std_fopen = _libraries['FIXME_STUB'].apps_std_fopen - apps_std_fopen.restype = ctypes.c_int32 - apps_std_fopen.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_freopen = _libraries['FIXME_STUB'].apps_std_freopen - apps_std_freopen.restype = ctypes.c_int32 - apps_std_freopen.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fflush = _libraries['FIXME_STUB'].apps_std_fflush - apps_std_fflush.restype = ctypes.c_int32 - apps_std_fflush.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_fclose = _libraries['FIXME_STUB'].apps_std_fclose - apps_std_fclose.restype = ctypes.c_int32 - apps_std_fclose.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_fread = _libraries['FIXME_STUB'].apps_std_fread - apps_std_fread.restype = ctypes.c_int32 - apps_std_fread.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fwrite = _libraries['FIXME_STUB'].apps_std_fwrite - apps_std_fwrite.restype = ctypes.c_int32 - apps_std_fwrite.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fgetpos = _libraries['FIXME_STUB'].apps_std_fgetpos - apps_std_fgetpos.restype = ctypes.c_int32 - apps_std_fgetpos.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fsetpos = _libraries['FIXME_STUB'].apps_std_fsetpos - apps_std_fsetpos.restype = ctypes.c_int32 - apps_std_fsetpos.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_ftell = _libraries['FIXME_STUB'].apps_std_ftell - apps_std_ftell.restype = ctypes.c_int32 - apps_std_ftell.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fseek = _libraries['FIXME_STUB'].apps_std_fseek - apps_std_fseek.restype = ctypes.c_int32 - apps_std_fseek.argtypes = [apps_std_FILE, ctypes.c_int32, apps_std_SEEK] -except AttributeError: - pass -try: - apps_std_flen = _libraries['FIXME_STUB'].apps_std_flen - apps_std_flen.restype = ctypes.c_int32 - apps_std_flen.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - apps_std_rewind = _libraries['FIXME_STUB'].apps_std_rewind - apps_std_rewind.restype = ctypes.c_int32 - apps_std_rewind.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_feof = _libraries['FIXME_STUB'].apps_std_feof - apps_std_feof.restype = ctypes.c_int32 - apps_std_feof.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_ferror = _libraries['FIXME_STUB'].apps_std_ferror - apps_std_ferror.restype = ctypes.c_int32 - apps_std_ferror.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_clearerr = _libraries['FIXME_STUB'].apps_std_clearerr - apps_std_clearerr.restype = ctypes.c_int32 - apps_std_clearerr.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_print_string = _libraries['FIXME_STUB'].apps_std_print_string - apps_std_print_string.restype = ctypes.c_int32 - apps_std_print_string.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_getenv = _libraries['FIXME_STUB'].apps_std_getenv - apps_std_getenv.restype = ctypes.c_int32 - apps_std_getenv.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_setenv = _libraries['FIXME_STUB'].apps_std_setenv - apps_std_setenv.restype = ctypes.c_int32 - apps_std_setenv.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_unsetenv = _libraries['FIXME_STUB'].apps_std_unsetenv - apps_std_unsetenv.restype = ctypes.c_int32 - apps_std_unsetenv.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_fopen_with_env = _libraries['FIXME_STUB'].apps_std_fopen_with_env - apps_std_fopen_with_env.restype = ctypes.c_int32 - apps_std_fopen_with_env.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_fgets = _libraries['FIXME_STUB'].apps_std_fgets - apps_std_fgets.restype = ctypes.c_int32 - apps_std_fgets.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_ubyte), ctypes.c_int32, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_get_search_paths_with_env = _libraries['FIXME_STUB'].apps_std_get_search_paths_with_env - apps_std_get_search_paths_with_env.restype = ctypes.c_int32 - apps_std_get_search_paths_with_env.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct__cstring1_s), ctypes.c_int32, ctypes.POINTER(ctypes.c_uint32), ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -try: - apps_std_fileExists = _libraries['FIXME_STUB'].apps_std_fileExists - apps_std_fileExists.restype = ctypes.c_int32 - apps_std_fileExists.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_ubyte)] -except AttributeError: - pass -try: - apps_std_fsync = _libraries['FIXME_STUB'].apps_std_fsync - apps_std_fsync.restype = ctypes.c_int32 - apps_std_fsync.argtypes = [apps_std_FILE] -except AttributeError: - pass -try: - apps_std_fremove = _libraries['FIXME_STUB'].apps_std_fremove - apps_std_fremove.restype = ctypes.c_int32 - apps_std_fremove.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_fdopen_decrypt = _libraries['FIXME_STUB'].apps_std_fdopen_decrypt - apps_std_fdopen_decrypt.restype = ctypes.c_int32 - apps_std_fdopen_decrypt.argtypes = [apps_std_FILE, ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_opendir = _libraries['FIXME_STUB'].apps_std_opendir - apps_std_opendir.restype = ctypes.c_int32 - apps_std_opendir.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_apps_std_DIR)] -except AttributeError: - pass -try: - apps_std_closedir = _libraries['FIXME_STUB'].apps_std_closedir - apps_std_closedir.restype = ctypes.c_int32 - apps_std_closedir.argtypes = [ctypes.POINTER(struct_apps_std_DIR)] -except AttributeError: - pass -try: - apps_std_readdir = _libraries['FIXME_STUB'].apps_std_readdir - apps_std_readdir.restype = ctypes.c_int32 - apps_std_readdir.argtypes = [ctypes.POINTER(struct_apps_std_DIR), ctypes.POINTER(struct_apps_std_DIRENT), ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - apps_std_mkdir = _libraries['FIXME_STUB'].apps_std_mkdir - apps_std_mkdir.restype = ctypes.c_int32 - apps_std_mkdir.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_rmdir = _libraries['FIXME_STUB'].apps_std_rmdir - apps_std_rmdir.restype = ctypes.c_int32 - apps_std_rmdir.argtypes = [ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - apps_std_stat = _libraries['FIXME_STUB'].apps_std_stat - apps_std_stat.restype = ctypes.c_int32 - apps_std_stat.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_apps_std_STAT)] -except AttributeError: - pass -try: - apps_std_ftrunc = _libraries['FIXME_STUB'].apps_std_ftrunc - apps_std_ftrunc.restype = ctypes.c_int32 - apps_std_ftrunc.argtypes = [apps_std_FILE, ctypes.c_int32] -except AttributeError: - pass -try: - apps_std_frename = _libraries['FIXME_STUB'].apps_std_frename - apps_std_frename.restype = ctypes.c_int32 - apps_std_frename.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -__all__ = \ - ['ADSPRPC_SHARED_H', 'ADSP_DOMAIN', 'ADSP_DOMAIN_ID', - 'APPS_STD_SEEK_CUR', 'APPS_STD_SEEK_END', 'APPS_STD_SEEK_SET', - 'ARCH_VER', 'ASYNC_FASTRPC_SUPPORT', 'CAMERA_SECURE_CP_USAGE', - 'CDSP_DOMAIN', 'CDSP_DOMAIN_ID', 'DEFAULT_DOMAIN_ID', - 'DEVICE_NAME', 'DISPLAY_SECURE_CP_USAGE', 'DOMAIN_ID_MASK', - 'DOMAIN_SUPPORT', 'DSPRPC_CONTROL_LATENCY', - 'DSPRPC_CONTROL_UNSIGNED_MODULE', 'DSPRPC_CONTROL_WAKELOCK', - 'DSPRPC_GET_DOMAIN', 'DSPRPC_GET_DSP_INFO', - 'FASTRPC_ASYNC_CALLBACK', 'FASTRPC_ASYNC_NO_SYNC', - 'FASTRPC_ASYNC_POLL', 'FASTRPC_ASYNC_TYPE_MAX', - 'FASTRPC_ATTR_COHERENT', 'FASTRPC_ATTR_COHERENT', - 'FASTRPC_ATTR_FORCE_NOFLUSH', 'FASTRPC_ATTR_FORCE_NOINVALIDATE', - 'FASTRPC_ATTR_KEEP_MAP', 'FASTRPC_ATTR_KEEP_MAP', - 'FASTRPC_ATTR_NOMAP', 'FASTRPC_ATTR_NOMAP', - 'FASTRPC_ATTR_NON_COHERENT', 'FASTRPC_ATTR_NON_COHERENT', - 'FASTRPC_ATTR_NOVA', 'FASTRPC_ATTR_TRY_MAP_STATIC', - 'FASTRPC_CONTROL_KALLOC', 'FASTRPC_CONTROL_LATENCY', - 'FASTRPC_CONTROL_PD_DUMP', 'FASTRPC_CONTROL_SMMU', - 'FASTRPC_DSP_SSR', 'FASTRPC_GLINK_GUID', 'FASTRPC_INIT_ATTACH', - 'FASTRPC_INIT_ATTACH_SENSORS', 'FASTRPC_INIT_CREATE', - 'FASTRPC_INIT_CREATE_STATIC', 'FASTRPC_MAP_FD', - 'FASTRPC_MAP_FD_DELAYED', 'FASTRPC_MAP_MAX', - 'FASTRPC_MAP_RESERVED', 'FASTRPC_MAP_STATIC', - 'FASTRPC_MAX_DSP_ATTRIBUTES', 'FASTRPC_MODE_PARALLEL', - 'FASTRPC_MODE_PROFILE', 'FASTRPC_MODE_SERIAL', - 'FASTRPC_MODE_SESSION', 'FASTRPC_REGISTER_STATUS_NOTIFICATIONS', - 'FASTRPC_RELATIVE_THREAD_PRIORITY', - 'FASTRPC_REMOTE_PROCESS_EXCEPTION', 'FASTRPC_REMOTE_PROCESS_KILL', - 'FASTRPC_REMOTE_PROCESS_TYPE', 'FASTRPC_SESSION_CLOSE', - 'FASTRPC_SMD_GUID', 'FASTRPC_THREAD_PARAMS', - 'FASTRPC_USER_PD_EXCEPTION', 'FASTRPC_USER_PD_EXIT', - 'FASTRPC_USER_PD_FORCE_KILL', 'FASTRPC_USER_PD_UP', - 'FASTRPC_WAKELOCK_CONTROL_SUPPORTED', 'FIXED_HIGH', 'FIXED_LOW', - 'FIXED_MIDDLE', 'HMX_SUPPORT_DEPTH', 'HMX_SUPPORT_SPATIAL', - 'HVX_SUPPORT_128B', 'HVX_SUPPORT_64B', 'INVALID_HEAP_ID', - 'ION_ADSP_HEAP_ID', 'ION_ADSP_HEAP_NAME', 'ION_AUDIO_HEAP_ID', - 'ION_AUDIO_HEAP_NAME', 'ION_CAMERA_HEAP_ID', - 'ION_CAMERA_HEAP_NAME', 'ION_CP_MFC_HEAP_ID', 'ION_CP_MM_HEAP_ID', - 'ION_CP_WB_HEAP_ID', 'ION_FLAG_ALLOW_NON_CONTIG', - 'ION_FLAG_CACHED', 'ION_FLAG_CACHED_NEEDS_SYNC', - 'ION_FLAG_CP_APP', 'ION_FLAG_CP_BITSTREAM', 'ION_FLAG_CP_CAMERA', - 'ION_FLAG_CP_HLOS', 'ION_FLAG_CP_HLOS_FREE', - 'ION_FLAG_CP_NON_PIXEL', 'ION_FLAG_CP_PIXEL', - 'ION_FLAG_CP_SEC_DISPLAY', 'ION_FLAG_CP_TOUCH', - 'ION_FLAG_FORCE_CONTIGUOUS', 'ION_FLAG_POOL_FORCE_ALLOC', - 'ION_FLAG_POOL_PREFETCH', 'ION_FLAG_SECURE', - 'ION_FORCE_CONTIGUOUS', 'ION_HEAP_CARVEOUT_MASK', - 'ION_HEAP_ID_RESERVED', 'ION_HEAP_SYSTEM_CONTIG_MASK', - 'ION_HEAP_SYSTEM_MASK', 'ION_HEAP_TYPE_CARVEOUT', - 'ION_HEAP_TYPE_CHUNK', 'ION_HEAP_TYPE_CUSTOM', - 'ION_HEAP_TYPE_DMA', 'ION_HEAP_TYPE_DMA_MASK', - 'ION_HEAP_TYPE_HYP_CMA', 'ION_HEAP_TYPE_IOMMU', - 'ION_HEAP_TYPE_MSM_START', 'ION_HEAP_TYPE_SECURE_DMA', - 'ION_HEAP_TYPE_SYSTEM', 'ION_HEAP_TYPE_SYSTEM_CONTIG', - 'ION_HEAP_TYPE_SYSTEM_SECURE', 'ION_IOC_MAGIC', - 'ION_IOC_MSM_MAGIC', 'ION_IOMMU_HEAP_ID', 'ION_IOMMU_HEAP_NAME', - 'ION_KMALLOC_HEAP_NAME', 'ION_MFC_HEAP_NAME', - 'ION_MM_FIRMWARE_HEAP_ID', 'ION_MM_FIRMWARE_HEAP_NAME', - 'ION_MM_HEAP_NAME', 'ION_NUM_HEAPS', 'ION_PIL1_HEAP_ID', - 'ION_PIL1_HEAP_NAME', 'ION_PIL2_HEAP_ID', 'ION_PIL2_HEAP_NAME', - 'ION_QSECOM_HEAP_ID', 'ION_QSECOM_HEAP_NAME', 'ION_SECURE', - 'ION_SECURE_DISPLAY_HEAP_ID', 'ION_SECURE_DISPLAY_HEAP_NAME', - 'ION_SECURE_HEAP_ID', 'ION_SECURE_HEAP_NAME', 'ION_SF_HEAP_ID', - 'ION_SF_HEAP_NAME', 'ION_SYSTEM_CONTIG_HEAP_ID', - 'ION_SYSTEM_HEAP_ID', 'ION_SYSTEM_HEAP_NAME', - 'ION_VMALLOC_HEAP_NAME', 'ION_WB_HEAP_NAME', 'MAX_USAGE', - 'MDSP_DOMAIN', 'MDSP_DOMAIN_ID', 'NOT_FIXED', 'NUM_DOMAINS', - 'NUM_SESSIONS', 'PROCESS_TYPE_SIGNED', 'PROCESS_TYPE_UNSIGNED', - 'REMOTE_DEFAULT_H', 'REMOTE_MAP_MAX_FLAG', - 'REMOTE_MAP_MEM_STATIC', 'REMOTE_MODE_PARALLEL', - 'REMOTE_MODE_SERIAL', 'RPC_ADAPTIVE_QOS', 'RPC_DISABLE_QOS', - 'RPC_PM_QOS', 'RPC_POLL_QOS', 'SDSP_DOMAIN', 'SDSP_DOMAIN_ID', - 'STATUS_NOTIFICATION_SUPPORT', 'UNKNOWN', 'UNSIGNED_PD_SUPPORT', - 'VIDEO_BITSTREAM', 'VIDEO_NONPIXEL', 'VIDEO_PIXEL', 'VTCM_COUNT', - 'VTCM_PAGE', '_32BIT_PLACEHOLDER_apps_std_SEEK', '_APPS_STD_H', - '_IO', '_IOR', '_IOW', '_IOWR', '_UAPI_LINUX_ION_H', - '_UAPI_MSM_ION_H', '__QAIC_HEADER_ATTRIBUTE', - '__QAIC_HEADER_EXPORT', '__QAIC_IMPL_ATTRIBUTE', - '__QAIC_IMPL_EXPORT', '__QAIC_REMOTE_ATTRIBUTE', - '__QAIC_REMOTE_EXPORT', '__QAIC_STRING1_OBJECT_DEFINED__', - '__STRING1_OBJECT__', '_cstring1_t', 'apps_std_DIR', - 'apps_std_DIRENT', 'apps_std_FILE', 'apps_std_SEEK', - 'apps_std_STAT', 'apps_std_clearerr', 'apps_std_closedir', - 'apps_std_fclose', 'apps_std_fdopen_decrypt', 'apps_std_feof', - 'apps_std_ferror', 'apps_std_fflush', 'apps_std_fgetpos', - 'apps_std_fgets', 'apps_std_fileExists', 'apps_std_flen', - 'apps_std_fopen', 'apps_std_fopen_with_env', 'apps_std_fread', - 'apps_std_fremove', 'apps_std_frename', 'apps_std_freopen', - 'apps_std_fseek', 'apps_std_fsetpos', 'apps_std_fsync', - 'apps_std_ftell', 'apps_std_ftrunc', 'apps_std_fwrite', - 'apps_std_get_search_paths_with_env', 'apps_std_getenv', - 'apps_std_mkdir', 'apps_std_opendir', 'apps_std_print_string', - 'apps_std_readdir', 'apps_std_rewind', 'apps_std_rmdir', - 'apps_std_setenv', 'apps_std_stat', 'apps_std_unsetenv', - 'cp_mem_usage', 'fastrpc_async_callback_t', - 'fastrpc_async_descriptor_t', 'fastrpc_async_get_status', - 'fastrpc_async_jobid', 'fastrpc_async_notify_type', - 'fastrpc_capability', 'fastrpc_map_flags', 'fastrpc_mmap', - 'fastrpc_munmap', 'fastrpc_notif_fn_t', 'fastrpc_process_type', - 'fastrpc_release_async_job', 'handle_control_req_id', - 'ion_fixed_position', 'ion_heap_ids', 'ion_heap_type', - 'ion_user_handle_t', 'msm_ion_heap_types', 'remote_arg', - 'remote_arg_t', 'remote_buf', 'remote_buf_attributes', - 'remote_dma_handle', 'remote_dsp_attributes', 'remote_handle', - 'remote_handle64', 'remote_handle64_close', - 'remote_handle64_control', 'remote_handle64_invoke', - 'remote_handle64_invoke_async', 'remote_handle64_open', - 'remote_handle_close', 'remote_handle_control', - 'remote_handle_invoke', 'remote_handle_invoke_async', - 'remote_handle_open', 'remote_mem_map', 'remote_mem_map_flags', - 'remote_mem_unmap', 'remote_mmap', 'remote_munmap', - 'remote_register_buf', 'remote_register_buf_attr', - 'remote_register_dma_handle', 'remote_register_dma_handle_attr', - 'remote_register_fd', 'remote_rpc_control_latency_t', - 'remote_rpc_control_latency_t__enumvalues', - 'remote_rpc_get_domain_t', 'remote_rpc_latency_flags', - 'remote_rpc_notif_register_t', 'remote_rpc_process_exception', - 'remote_rpc_status_flags', 'remote_rpc_status_flags_t', - 'remote_rpc_status_flags_t__enumvalues', 'remote_session_control', - 'remote_set_mode', 'session_control_req_id', 'size_t', - 'smq_invoke_buf_start', 'smq_phy_page_start', - 'struct__cstring1_s', 'struct_apps_std_DIR', - 'struct_apps_std_DIRENT', 'struct_apps_std_STAT', - 'struct_c__SA_remote_buf', 'struct_c__SA_remote_dma_handle', - 'struct_fastrpc_async_callback', - 'struct_fastrpc_async_descriptor', 'struct_fastrpc_ctrl_kalloc', - 'struct_fastrpc_ctrl_latency', 'struct_fastrpc_ctrl_smmu', - 'struct_fastrpc_ioctl_control', 'struct_fastrpc_ioctl_init', - 'struct_fastrpc_ioctl_init_attrs', 'struct_fastrpc_ioctl_invoke', - 'struct_fastrpc_ioctl_invoke_attrs', - 'struct_fastrpc_ioctl_invoke_crc', - 'struct_fastrpc_ioctl_invoke_fd', 'struct_fastrpc_ioctl_mmap', - 'struct_fastrpc_ioctl_mmap_64', 'struct_fastrpc_ioctl_munmap', - 'struct_fastrpc_ioctl_munmap_64', - 'struct_fastrpc_ioctl_munmap_fd', 'struct_fastrpc_ioctl_perf', - 'struct_ion_allocation_data', 'struct_ion_custom_data', - 'struct_ion_fd_data', 'struct_ion_flush_data', - 'struct_ion_handle_data', 'struct_ion_prefetch_data', - 'struct_ion_prefetch_regions', 'struct_remote_buf', - 'struct_remote_buf64', 'struct_remote_dma_handle', - 'struct_remote_dma_handle64', 'struct_remote_dsp_capability', - 'struct_remote_process_type', 'struct_remote_rpc_control_latency', - 'struct_remote_rpc_control_pd_dump', - 'struct_remote_rpc_control_unsigned_module', - 'struct_remote_rpc_control_wakelock', - 'struct_remote_rpc_get_domain', - 'struct_remote_rpc_notif_register', - 'struct_remote_rpc_process_clean_params', - 'struct_remote_rpc_relative_thread_priority', - 'struct_remote_rpc_session_close', - 'struct_remote_rpc_thread_params', 'struct_smq_invoke', - 'struct_smq_invoke_buf', 'struct_smq_invoke_rsp', - 'struct_smq_msg', 'struct_smq_null_invoke', 'struct_smq_phy_page', - 'uint32_t', 'uint64_t', 'union_c__UA_remote_arg', - 'union_fastrpc_async_descriptor_0', - 'union_fastrpc_ioctl_control_0', 'union_remote_arg', - 'union_remote_arg64'] +ION_HEAP_SYSTEM_MASK = ((1 << ION_HEAP_TYPE_SYSTEM)) +ION_HEAP_SYSTEM_CONTIG_MASK = ((1 << ION_HEAP_TYPE_SYSTEM_CONTIG)) +ION_HEAP_CARVEOUT_MASK = ((1 << ION_HEAP_TYPE_CARVEOUT)) +ION_HEAP_TYPE_DMA_MASK = ((1 << ION_HEAP_TYPE_DMA)) +ION_FLAG_CACHED = 1 +ION_FLAG_CACHED_NEEDS_SYNC = 2 +ION_IOC_MAGIC = 'I' +ION_IOC_ALLOC = _IOWR(ION_IOC_MAGIC, 0, struct_ion_allocation_data) +ION_IOC_FREE = _IOWR(ION_IOC_MAGIC, 1, struct_ion_handle_data) +ION_IOC_MAP = _IOWR(ION_IOC_MAGIC, 2, struct_ion_fd_data) +ION_IOC_SHARE = _IOWR(ION_IOC_MAGIC, 4, struct_ion_fd_data) +ION_IOC_IMPORT = _IOWR(ION_IOC_MAGIC, 5, struct_ion_fd_data) +ION_IOC_SYNC = _IOWR(ION_IOC_MAGIC, 7, struct_ion_fd_data) +ION_IOC_CUSTOM = _IOWR(ION_IOC_MAGIC, 6, struct_ion_custom_data) +ION_IOMMU_HEAP_ID = ION_SYSTEM_HEAP_ID +ION_HEAP_TYPE_IOMMU = ION_HEAP_TYPE_SYSTEM +ION_FLAG_CP_TOUCH = (1 << 17) +ION_FLAG_CP_BITSTREAM = (1 << 18) +ION_FLAG_CP_PIXEL = (1 << 19) +ION_FLAG_CP_NON_PIXEL = (1 << 20) +ION_FLAG_CP_CAMERA = (1 << 21) +ION_FLAG_CP_HLOS = (1 << 22) +ION_FLAG_CP_HLOS_FREE = (1 << 23) +ION_FLAG_CP_SEC_DISPLAY = (1 << 25) +ION_FLAG_CP_APP = (1 << 26) +ION_FLAG_ALLOW_NON_CONTIG = (1 << 24) +ION_FLAG_SECURE = (1 << ION_HEAP_ID_RESERVED) +ION_FLAG_FORCE_CONTIGUOUS = (1 << 30) +ION_FLAG_POOL_FORCE_ALLOC = (1 << 16) +ION_FLAG_POOL_PREFETCH = (1 << 27) +ION_SECURE = ION_FLAG_SECURE +ION_FORCE_CONTIGUOUS = ION_FLAG_FORCE_CONTIGUOUS +ION_HEAP = lambda bit: (1 << (bit)) +ION_ADSP_HEAP_NAME = "adsp" +ION_SYSTEM_HEAP_NAME = "system" +ION_VMALLOC_HEAP_NAME = ION_SYSTEM_HEAP_NAME +ION_KMALLOC_HEAP_NAME = "kmalloc" +ION_AUDIO_HEAP_NAME = "audio" +ION_SF_HEAP_NAME = "sf" +ION_MM_HEAP_NAME = "mm" +ION_CAMERA_HEAP_NAME = "camera_preview" +ION_IOMMU_HEAP_NAME = "iommu" +ION_MFC_HEAP_NAME = "mfc" +ION_WB_HEAP_NAME = "wb" +ION_MM_FIRMWARE_HEAP_NAME = "mm_fw" +ION_PIL1_HEAP_NAME = "pil_1" +ION_PIL2_HEAP_NAME = "pil_2" +ION_QSECOM_HEAP_NAME = "qsecom" +ION_SECURE_HEAP_NAME = "secure_heap" +ION_SECURE_DISPLAY_HEAP_NAME = "secure_display" +ION_SET_CACHED = lambda __cache: (__cache | ION_FLAG_CACHED) +ION_SET_UNCACHED = lambda __cache: (__cache & ~ION_FLAG_CACHED) +ION_IS_CACHED = lambda __flags: ((__flags) & ION_FLAG_CACHED) +ION_IOC_MSM_MAGIC = 'M' +ION_IOC_CLEAN_CACHES = _IOWR(ION_IOC_MSM_MAGIC, 0, struct_ion_flush_data) +ION_IOC_INV_CACHES = _IOWR(ION_IOC_MSM_MAGIC, 1, struct_ion_flush_data) +ION_IOC_CLEAN_INV_CACHES = _IOWR(ION_IOC_MSM_MAGIC, 2, struct_ion_flush_data) +ION_IOC_PREFETCH = _IOWR(ION_IOC_MSM_MAGIC, 3, struct_ion_prefetch_data) +ION_IOC_DRAIN = _IOWR(ION_IOC_MSM_MAGIC, 4, struct_ion_prefetch_data) +FASTRPC_IOCTL_INVOKE = _IOWR('R', 1, struct_fastrpc_ioctl_invoke) +FASTRPC_IOCTL_MMAP = _IOWR('R', 2, struct_fastrpc_ioctl_mmap) +FASTRPC_IOCTL_MUNMAP = _IOWR('R', 3, struct_fastrpc_ioctl_munmap) +FASTRPC_IOCTL_MMAP_64 = _IOWR('R', 14, struct_fastrpc_ioctl_mmap_64) +FASTRPC_IOCTL_MUNMAP_64 = _IOWR('R', 15, struct_fastrpc_ioctl_munmap_64) +FASTRPC_IOCTL_INVOKE_FD = _IOWR('R', 4, struct_fastrpc_ioctl_invoke_fd) +FASTRPC_IOCTL_SETMODE = _IOWR('R', 5, uint32_t) +FASTRPC_IOCTL_INIT = _IOWR('R', 6, struct_fastrpc_ioctl_init) +FASTRPC_IOCTL_INVOKE_ATTRS = _IOWR('R', 7, struct_fastrpc_ioctl_invoke_attrs) +FASTRPC_IOCTL_GETINFO = _IOWR('R', 8, uint32_t) +FASTRPC_IOCTL_GETPERF = _IOWR('R', 9, struct_fastrpc_ioctl_perf) +FASTRPC_IOCTL_INIT_ATTRS = _IOWR('R', 10, struct_fastrpc_ioctl_init_attrs) +FASTRPC_IOCTL_INVOKE_CRC = _IOWR('R', 11, struct_fastrpc_ioctl_invoke_crc) +FASTRPC_IOCTL_CONTROL = _IOWR('R', 12, struct_fastrpc_ioctl_control) +FASTRPC_IOCTL_MUNMAP_FD = _IOWR('R', 13, struct_fastrpc_ioctl_munmap_fd) +FASTRPC_GLINK_GUID = "fastrpcglink-apps-dsp" +FASTRPC_SMD_GUID = "fastrpcsmd-apps-dsp" +DEVICE_NAME = "adsprpc-smd" +FASTRPC_ATTR_NOVA = 0x1 +FASTRPC_ATTR_NON_COHERENT = 0x2 +FASTRPC_ATTR_COHERENT = 0x4 +FASTRPC_ATTR_KEEP_MAP = 0x8 +FASTRPC_ATTR_NOMAP = (16) +FASTRPC_MODE_PARALLEL = 0 +FASTRPC_MODE_SERIAL = 1 +FASTRPC_MODE_PROFILE = 2 +FASTRPC_MODE_SESSION = 4 +FASTRPC_INIT_ATTACH = 0 +FASTRPC_INIT_CREATE = 1 +FASTRPC_INIT_CREATE_STATIC = 2 +FASTRPC_INIT_ATTACH_SENSORS = 3 +REMOTE_SCALARS_INBUFS = lambda sc: (((sc) >> 16) & 0x0ff) +REMOTE_SCALARS_OUTBUFS = lambda sc: (((sc) >> 8) & 0x0ff) +REMOTE_SCALARS_INHANDLES = lambda sc: (((sc) >> 4) & 0x0f) +REMOTE_SCALARS_OUTHANDLES = lambda sc: ((sc) & 0x0f) +REMOTE_SCALARS_LENGTH = lambda sc: (REMOTE_SCALARS_INBUFS(sc) + REMOTE_SCALARS_OUTBUFS(sc) + REMOTE_SCALARS_INHANDLES(sc) + REMOTE_SCALARS_OUTHANDLES(sc)) +__TOSTR__ = lambda x: __STR__(x) +remote_arg64_t = union_remote_arg64 +remote_arg_t = union_remote_arg +FASTRPC_CONTROL_LATENCY = (1) +FASTRPC_CONTROL_SMMU = (2) +FASTRPC_CONTROL_KALLOC = (3) +REMOTE_SCALARS_METHOD_ATTR = lambda dwScalars: (((dwScalars) >> 29) & 0x7) +REMOTE_SCALARS_METHOD = lambda dwScalars: (((dwScalars) >> 24) & 0x1f) +REMOTE_SCALARS_INBUFS = lambda dwScalars: (((dwScalars) >> 16) & 0x0ff) +REMOTE_SCALARS_OUTBUFS = lambda dwScalars: (((dwScalars) >> 8) & 0x0ff) +REMOTE_SCALARS_INHANDLES = lambda dwScalars: (((dwScalars) >> 4) & 0x0f) +REMOTE_SCALARS_OUTHANDLES = lambda dwScalars: ((dwScalars) & 0x0f) +REMOTE_SCALARS_MAKEX = lambda nAttr,nMethod,nIn,nOut,noIn,noOut: ((((uint32_t) (nAttr) & 0x7) << 29) | (((uint32_t) (nMethod) & 0x1f) << 24) | (((uint32_t) (nIn) & 0xff) << 16) | (((uint32_t) (nOut) & 0xff) << 8) | (((uint32_t) (noIn) & 0x0f) << 4) | ((uint32_t) (noOut) & 0x0f)) +REMOTE_SCALARS_MAKE = lambda nMethod,nIn,nOut: REMOTE_SCALARS_MAKEX(0,nMethod,nIn,nOut,0,0) +REMOTE_SCALARS_LENGTH = lambda sc: (REMOTE_SCALARS_INBUFS(sc) + REMOTE_SCALARS_OUTBUFS(sc) + REMOTE_SCALARS_INHANDLES(sc) + REMOTE_SCALARS_OUTHANDLES(sc)) +__QAIC_REMOTE = lambda ff: ff +NUM_DOMAINS = 4 +NUM_SESSIONS = 2 +DOMAIN_ID_MASK = 3 +DEFAULT_DOMAIN_ID = 0 +ADSP_DOMAIN_ID = 0 +MDSP_DOMAIN_ID = 1 +SDSP_DOMAIN_ID = 2 +CDSP_DOMAIN_ID = 3 +ADSP_DOMAIN = "&_dom=adsp" +MDSP_DOMAIN = "&_dom=mdsp" +SDSP_DOMAIN = "&_dom=sdsp" +CDSP_DOMAIN = "&_dom=cdsp" +FASTRPC_WAKELOCK_CONTROL_SUPPORTED = 1 +REMOTE_MODE_PARALLEL = 0 +REMOTE_MODE_SERIAL = 1 +ITRANSPORT_PREFIX = "'\":;./\\" +__QAIC_HEADER = lambda ff: ff +__QAIC_IMPL = lambda ff: ff \ No newline at end of file diff --git a/tinygrad/runtime/autogen/rocprof.py b/tinygrad/runtime/autogen/rocprof.py index 91ad8ce817..29aef764d9 100644 --- a/tinygrad/runtime/autogen/rocprof.py +++ b/tinygrad/runtime/autogen/rocprof.py @@ -1,669 +1,260 @@ -# pylint: skip-file # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util -PATHS_TO_TRY = [ - '/usr/local/lib/librocprof-trace-decoder.so', - '/usr/local/lib/librocprof-trace-decoder.dylib', -] -def _try_dlopen_rocprof_trace_decoder(): - library = ctypes.util.find_library("rocprof-trace-decoder") - if library: - try: return ctypes.CDLL(library) - except OSError: pass - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from ctypes.util import find_library +def dll(): + try: return ctypes.CDLL(unwrap(find_library('rocprof-trace-decoder'))) + except: pass + try: return ctypes.CDLL(unwrap('/usr/local/lib/rocprof-trace-decoder.so')) + except: pass + try: return ctypes.CDLL(unwrap('/usr/local/lib/rocprof-trace-decoder.dylib')) + except: pass return None +dll = dll() +rocprofiler_thread_trace_decoder_status_t = CEnum(ctypes.c_uint32) +ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS = rocprofiler_thread_trace_decoder_status_t.define('ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS', 0) +ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR = rocprofiler_thread_trace_decoder_status_t.define('ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR', 1) +ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES = rocprofiler_thread_trace_decoder_status_t.define('ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES', 2) +ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_ARGUMENT = rocprofiler_thread_trace_decoder_status_t.define('ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_ARGUMENT', 3) +ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_SHADER_DATA = rocprofiler_thread_trace_decoder_status_t.define('ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_SHADER_DATA', 4) +ROCPROFILER_THREAD_TRACE_DECODER_STATUS_LAST = rocprofiler_thread_trace_decoder_status_t.define('ROCPROFILER_THREAD_TRACE_DECODER_STATUS_LAST', 5) -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result +enum_rocprofiler_thread_trace_decoder_record_type_t = CEnum(ctypes.c_uint32) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_GFXIP = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_GFXIP', 0) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY', 1) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_PERFEVENT = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_PERFEVENT', 2) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE', 3) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_INFO = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_INFO', 4) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_DEBUG = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_DEBUG', 5) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_SHADERDATA = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_SHADERDATA', 6) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_REALTIME = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_REALTIME', 7) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_RT_FREQUENCY = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_RT_FREQUENCY', 8) +ROCPROFILER_THREAD_TRACE_DECODER_RECORD_LAST = enum_rocprofiler_thread_trace_decoder_record_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_RECORD_LAST', 9) - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['FIXME_STUB'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['FIXME_STUB'] = _try_dlopen_rocprof_trace_decoder() # ctypes.CDLL('FIXME_STUB') - - - -# values for enumeration 'rocprofiler_thread_trace_decoder_info_t' -rocprofiler_thread_trace_decoder_info_t__enumvalues = { - 0: 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_NONE', - 1: 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_DATA_LOST', - 2: 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_STITCH_INCOMPLETE', - 3: 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_WAVE_INCOMPLETE', - 4: 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_LAST', -} -ROCPROFILER_THREAD_TRACE_DECODER_INFO_NONE = 0 -ROCPROFILER_THREAD_TRACE_DECODER_INFO_DATA_LOST = 1 -ROCPROFILER_THREAD_TRACE_DECODER_INFO_STITCH_INCOMPLETE = 2 -ROCPROFILER_THREAD_TRACE_DECODER_INFO_WAVE_INCOMPLETE = 3 -ROCPROFILER_THREAD_TRACE_DECODER_INFO_LAST = 4 -rocprofiler_thread_trace_decoder_info_t = ctypes.c_uint32 # enum -class struct_rocprofiler_thread_trace_decoder_pc_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_pc_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_pc_t._fields_ = [ - ('address', ctypes.c_uint64), - ('code_object_id', ctypes.c_uint64), -] - -rocprofiler_thread_trace_decoder_pc_t = struct_rocprofiler_thread_trace_decoder_pc_t -class struct_rocprofiler_thread_trace_decoder_perfevent_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_perfevent_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_perfevent_t._fields_ = [ - ('time', ctypes.c_int64), - ('events0', ctypes.c_uint16), - ('events1', ctypes.c_uint16), - ('events2', ctypes.c_uint16), - ('events3', ctypes.c_uint16), - ('CU', ctypes.c_ubyte), - ('bank', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), -] - -rocprofiler_thread_trace_decoder_perfevent_t = struct_rocprofiler_thread_trace_decoder_perfevent_t -class struct_rocprofiler_thread_trace_decoder_occupancy_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_occupancy_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_occupancy_t._fields_ = [ - ('pc', rocprofiler_thread_trace_decoder_pc_t), - ('time', ctypes.c_uint64), - ('reserved', ctypes.c_ubyte), - ('cu', ctypes.c_ubyte), - ('simd', ctypes.c_ubyte), - ('wave_id', ctypes.c_ubyte), - ('start', ctypes.c_uint32, 1), - ('_rsvd', ctypes.c_uint32, 31), -] - -rocprofiler_thread_trace_decoder_occupancy_t = struct_rocprofiler_thread_trace_decoder_occupancy_t - -# values for enumeration 'rocprofiler_thread_trace_decoder_wstate_type_t' -rocprofiler_thread_trace_decoder_wstate_type_t__enumvalues = { - 0: 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EMPTY', - 1: 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_IDLE', - 2: 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EXEC', - 3: 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_WAIT', - 4: 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_STALL', - 5: 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_LAST', -} -ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EMPTY = 0 -ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_IDLE = 1 -ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EXEC = 2 -ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_WAIT = 3 -ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_STALL = 4 -ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_LAST = 5 -rocprofiler_thread_trace_decoder_wstate_type_t = ctypes.c_uint32 # enum -class struct_rocprofiler_thread_trace_decoder_wave_state_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_wave_state_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_wave_state_t._fields_ = [ - ('type', ctypes.c_int32), - ('duration', ctypes.c_int32), -] - -rocprofiler_thread_trace_decoder_wave_state_t = struct_rocprofiler_thread_trace_decoder_wave_state_t - -# values for enumeration 'rocprofiler_thread_trace_decoder_inst_category_t' -rocprofiler_thread_trace_decoder_inst_category_t__enumvalues = { - 0: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_NONE', - 1: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_SMEM', - 2: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_SALU', - 3: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_VMEM', - 4: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_FLAT', - 5: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_LDS', - 6: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_VALU', - 7: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_JUMP', - 8: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_NEXT', - 9: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_IMMED', - 10: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_CONTEXT', - 11: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_MESSAGE', - 12: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_BVH', - 13: 'ROCPROFILER_THREAD_TRACE_DECODER_INST_LAST', -} -ROCPROFILER_THREAD_TRACE_DECODER_INST_NONE = 0 -ROCPROFILER_THREAD_TRACE_DECODER_INST_SMEM = 1 -ROCPROFILER_THREAD_TRACE_DECODER_INST_SALU = 2 -ROCPROFILER_THREAD_TRACE_DECODER_INST_VMEM = 3 -ROCPROFILER_THREAD_TRACE_DECODER_INST_FLAT = 4 -ROCPROFILER_THREAD_TRACE_DECODER_INST_LDS = 5 -ROCPROFILER_THREAD_TRACE_DECODER_INST_VALU = 6 -ROCPROFILER_THREAD_TRACE_DECODER_INST_JUMP = 7 -ROCPROFILER_THREAD_TRACE_DECODER_INST_NEXT = 8 -ROCPROFILER_THREAD_TRACE_DECODER_INST_IMMED = 9 -ROCPROFILER_THREAD_TRACE_DECODER_INST_CONTEXT = 10 -ROCPROFILER_THREAD_TRACE_DECODER_INST_MESSAGE = 11 -ROCPROFILER_THREAD_TRACE_DECODER_INST_BVH = 12 -ROCPROFILER_THREAD_TRACE_DECODER_INST_LAST = 13 -rocprofiler_thread_trace_decoder_inst_category_t = ctypes.c_uint32 # enum -class struct_rocprofiler_thread_trace_decoder_inst_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_inst_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_inst_t._fields_ = [ - ('category', ctypes.c_uint32, 8), - ('stall', ctypes.c_uint32, 24), - ('duration', ctypes.c_int32), - ('time', ctypes.c_int64), - ('pc', rocprofiler_thread_trace_decoder_pc_t), -] - -rocprofiler_thread_trace_decoder_inst_t = struct_rocprofiler_thread_trace_decoder_inst_t -class struct_rocprofiler_thread_trace_decoder_wave_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_wave_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_wave_t._fields_ = [ - ('cu', ctypes.c_ubyte), - ('simd', ctypes.c_ubyte), - ('wave_id', ctypes.c_ubyte), - ('contexts', ctypes.c_ubyte), - ('_rsvd1', ctypes.c_uint32), - ('_rsvd2', ctypes.c_uint32), - ('_rsvd3', ctypes.c_uint32), - ('begin_time', ctypes.c_int64), - ('end_time', ctypes.c_int64), - ('timeline_size', ctypes.c_uint64), - ('instructions_size', ctypes.c_uint64), - ('timeline_array', ctypes.POINTER(struct_rocprofiler_thread_trace_decoder_wave_state_t)), - ('instructions_array', ctypes.POINTER(struct_rocprofiler_thread_trace_decoder_inst_t)), -] - -rocprofiler_thread_trace_decoder_wave_t = struct_rocprofiler_thread_trace_decoder_wave_t -class struct_rocprofiler_thread_trace_decoder_realtime_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_realtime_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_realtime_t._fields_ = [ - ('shader_clock', ctypes.c_int64), - ('realtime_clock', ctypes.c_uint64), - ('reserved', ctypes.c_uint64), -] - -rocprofiler_thread_trace_decoder_realtime_t = struct_rocprofiler_thread_trace_decoder_realtime_t - -# values for enumeration 'rocprofiler_thread_trace_decoder_shaderdata_flags_t' -rocprofiler_thread_trace_decoder_shaderdata_flags_t__enumvalues = { - 0: 'ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_IMM', - 1: 'ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_PRIV', -} -ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_IMM = 0 -ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_PRIV = 1 -rocprofiler_thread_trace_decoder_shaderdata_flags_t = ctypes.c_uint32 # enum -class struct_rocprofiler_thread_trace_decoder_shaderdata_t(Structure): - pass - -struct_rocprofiler_thread_trace_decoder_shaderdata_t._pack_ = 1 # source:False -struct_rocprofiler_thread_trace_decoder_shaderdata_t._fields_ = [ - ('time', ctypes.c_int64), - ('value', ctypes.c_uint64), - ('cu', ctypes.c_ubyte), - ('simd', ctypes.c_ubyte), - ('wave_id', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('reserved', ctypes.c_uint32), -] - -rocprofiler_thread_trace_decoder_shaderdata_t = struct_rocprofiler_thread_trace_decoder_shaderdata_t - -# values for enumeration 'rocprofiler_thread_trace_decoder_record_type_t' -rocprofiler_thread_trace_decoder_record_type_t__enumvalues = { - 0: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_GFXIP', - 1: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY', - 2: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_PERFEVENT', - 3: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE', - 4: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_INFO', - 5: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_DEBUG', - 6: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_SHADERDATA', - 7: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_REALTIME', - 8: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_RT_FREQUENCY', - 9: 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_LAST', -} -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_GFXIP = 0 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY = 1 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_PERFEVENT = 2 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE = 3 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_INFO = 4 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_DEBUG = 5 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_SHADERDATA = 6 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_REALTIME = 7 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_RT_FREQUENCY = 8 -ROCPROFILER_THREAD_TRACE_DECODER_RECORD_LAST = 9 -rocprofiler_thread_trace_decoder_record_type_t = ctypes.c_uint32 # enum - -# values for enumeration 'c__EA_rocprofiler_thread_trace_decoder_status_t' -c__EA_rocprofiler_thread_trace_decoder_status_t__enumvalues = { - 0: 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS', - 1: 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR', - 2: 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES', - 3: 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_ARGUMENT', - 4: 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_SHADER_DATA', - 5: 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_LAST', -} -ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS = 0 -ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR = 1 -ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES = 2 -ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_ARGUMENT = 3 -ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_SHADER_DATA = 4 -ROCPROFILER_THREAD_TRACE_DECODER_STATUS_LAST = 5 -c__EA_rocprofiler_thread_trace_decoder_status_t = ctypes.c_uint32 # enum -rocprofiler_thread_trace_decoder_status_t = c__EA_rocprofiler_thread_trace_decoder_status_t -rocprofiler_thread_trace_decoder_status_t__enumvalues = c__EA_rocprofiler_thread_trace_decoder_status_t__enumvalues -rocprof_trace_decoder_trace_callback_t = ctypes.CFUNCTYPE(c__EA_rocprofiler_thread_trace_decoder_status_t, rocprofiler_thread_trace_decoder_record_type_t, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)) -rocprof_trace_decoder_isa_callback_t = ctypes.CFUNCTYPE(c__EA_rocprofiler_thread_trace_decoder_status_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), struct_rocprofiler_thread_trace_decoder_pc_t, ctypes.POINTER(None)) -rocprof_trace_decoder_se_data_callback_t = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(ctypes.c_ubyte)), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(None)) -try: - rocprof_trace_decoder_parse_data = _libraries['FIXME_STUB'].rocprof_trace_decoder_parse_data - rocprof_trace_decoder_parse_data.restype = rocprofiler_thread_trace_decoder_status_t - rocprof_trace_decoder_parse_data.argtypes = [rocprof_trace_decoder_se_data_callback_t, rocprof_trace_decoder_trace_callback_t, rocprof_trace_decoder_isa_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - rocprof_trace_decoder_get_info_string = _libraries['FIXME_STUB'].rocprof_trace_decoder_get_info_string - rocprof_trace_decoder_get_info_string.restype = ctypes.POINTER(ctypes.c_char) - rocprof_trace_decoder_get_info_string.argtypes = [rocprofiler_thread_trace_decoder_info_t] -except AttributeError: - pass -try: - rocprof_trace_decoder_get_status_string = _libraries['FIXME_STUB'].rocprof_trace_decoder_get_status_string - rocprof_trace_decoder_get_status_string.restype = ctypes.POINTER(ctypes.c_char) - rocprof_trace_decoder_get_status_string.argtypes = [rocprofiler_thread_trace_decoder_status_t] -except AttributeError: - pass -rocprofiler_thread_trace_decoder_debug_callback_t = ctypes.CFUNCTYPE(None, ctypes.c_int64, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)) +rocprof_trace_decoder_trace_callback_t = ctypes.CFUNCTYPE(rocprofiler_thread_trace_decoder_status_t, enum_rocprofiler_thread_trace_decoder_record_type_t, ctypes.c_void_p, ctypes.c_uint64, ctypes.c_void_p) +class struct_rocprofiler_thread_trace_decoder_pc_t(Struct): pass uint64_t = ctypes.c_uint64 -try: - rocprof_trace_decoder_dump_data = _libraries['FIXME_STUB'].rocprof_trace_decoder_dump_data - rocprof_trace_decoder_dump_data.restype = rocprofiler_thread_trace_decoder_status_t - rocprof_trace_decoder_dump_data.argtypes = [ctypes.POINTER(ctypes.c_char), uint64_t, rocprofiler_thread_trace_decoder_debug_callback_t, ctypes.POINTER(None)] -except AttributeError: - pass -class union_rocprof_trace_decoder_gfx9_header_t(Union): - pass - -class struct_rocprof_trace_decoder_gfx9_header_t_0(Structure): - pass - -struct_rocprof_trace_decoder_gfx9_header_t_0._pack_ = 1 # source:False -struct_rocprof_trace_decoder_gfx9_header_t_0._fields_ = [ - ('legacy_version', ctypes.c_uint64, 13), - ('gfx9_version2', ctypes.c_uint64, 3), - ('DSIMDM', ctypes.c_uint64, 4), - ('DCU', ctypes.c_uint64, 5), - ('reserved1', ctypes.c_uint64, 1), - ('SEID', ctypes.c_uint64, 6), - ('reserved2', ctypes.c_uint64, 32), +struct_rocprofiler_thread_trace_decoder_pc_t._fields_ = [ + ('address', uint64_t), + ('code_object_id', uint64_t), ] +rocprof_trace_decoder_isa_callback_t = ctypes.CFUNCTYPE(rocprofiler_thread_trace_decoder_status_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), struct_rocprofiler_thread_trace_decoder_pc_t, ctypes.c_void_p) +rocprof_trace_decoder_se_data_callback_t = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(ctypes.c_ubyte)), ctypes.POINTER(ctypes.c_uint64), ctypes.c_void_p) +# rocprofiler_thread_trace_decoder_status_t rocprof_trace_decoder_parse_data(rocprof_trace_decoder_se_data_callback_t se_data_callback, rocprof_trace_decoder_trace_callback_t trace_callback, rocprof_trace_decoder_isa_callback_t isa_callback, void *userdata) +try: (rocprof_trace_decoder_parse_data:=dll.rocprof_trace_decoder_parse_data).restype, rocprof_trace_decoder_parse_data.argtypes = rocprofiler_thread_trace_decoder_status_t, [rocprof_trace_decoder_se_data_callback_t, rocprof_trace_decoder_trace_callback_t, rocprof_trace_decoder_isa_callback_t, ctypes.c_void_p] +except AttributeError: pass -union_rocprof_trace_decoder_gfx9_header_t._pack_ = 1 # source:False -union_rocprof_trace_decoder_gfx9_header_t._anonymous_ = ('_0',) +enum_rocprofiler_thread_trace_decoder_info_t = CEnum(ctypes.c_uint32) +ROCPROFILER_THREAD_TRACE_DECODER_INFO_NONE = enum_rocprofiler_thread_trace_decoder_info_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INFO_NONE', 0) +ROCPROFILER_THREAD_TRACE_DECODER_INFO_DATA_LOST = enum_rocprofiler_thread_trace_decoder_info_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INFO_DATA_LOST', 1) +ROCPROFILER_THREAD_TRACE_DECODER_INFO_STITCH_INCOMPLETE = enum_rocprofiler_thread_trace_decoder_info_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INFO_STITCH_INCOMPLETE', 2) +ROCPROFILER_THREAD_TRACE_DECODER_INFO_WAVE_INCOMPLETE = enum_rocprofiler_thread_trace_decoder_info_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INFO_WAVE_INCOMPLETE', 3) +ROCPROFILER_THREAD_TRACE_DECODER_INFO_LAST = enum_rocprofiler_thread_trace_decoder_info_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INFO_LAST', 4) + +rocprofiler_thread_trace_decoder_info_t = enum_rocprofiler_thread_trace_decoder_info_t +# const char *rocprof_trace_decoder_get_info_string(rocprofiler_thread_trace_decoder_info_t info) +try: (rocprof_trace_decoder_get_info_string:=dll.rocprof_trace_decoder_get_info_string).restype, rocprof_trace_decoder_get_info_string.argtypes = ctypes.POINTER(ctypes.c_char), [rocprofiler_thread_trace_decoder_info_t] +except AttributeError: pass + +# const char *rocprof_trace_decoder_get_status_string(rocprofiler_thread_trace_decoder_status_t status) +try: (rocprof_trace_decoder_get_status_string:=dll.rocprof_trace_decoder_get_status_string).restype, rocprof_trace_decoder_get_status_string.argtypes = ctypes.POINTER(ctypes.c_char), [rocprofiler_thread_trace_decoder_status_t] +except AttributeError: pass + +rocprofiler_thread_trace_decoder_debug_callback_t = ctypes.CFUNCTYPE(None, ctypes.c_int64, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char), ctypes.c_void_p) +# rocprofiler_thread_trace_decoder_status_t rocprof_trace_decoder_dump_data(const char *data, uint64_t data_size, rocprofiler_thread_trace_decoder_debug_callback_t cb, void *userdata) +try: (rocprof_trace_decoder_dump_data:=dll.rocprof_trace_decoder_dump_data).restype, rocprof_trace_decoder_dump_data.argtypes = rocprofiler_thread_trace_decoder_status_t, [ctypes.POINTER(ctypes.c_char), uint64_t, rocprofiler_thread_trace_decoder_debug_callback_t, ctypes.c_void_p] +except AttributeError: pass + +class union_rocprof_trace_decoder_gfx9_header_t(ctypes.Union): pass +class union_rocprof_trace_decoder_gfx9_header_t_0(Struct): pass +union_rocprof_trace_decoder_gfx9_header_t_0._fields_ = [ + ('legacy_version', uint64_t,13), + ('gfx9_version2', uint64_t,3), + ('DSIMDM', uint64_t,4), + ('DCU', uint64_t,5), + ('reserved1', uint64_t,1), + ('SEID', uint64_t,6), + ('reserved2', uint64_t,32), +] +union_rocprof_trace_decoder_gfx9_header_t._anonymous_ = ['_0'] union_rocprof_trace_decoder_gfx9_header_t._fields_ = [ - ('_0', struct_rocprof_trace_decoder_gfx9_header_t_0), - ('raw', ctypes.c_uint64), + ('_0', union_rocprof_trace_decoder_gfx9_header_t_0), + ('raw', uint64_t), ] - rocprof_trace_decoder_gfx9_header_t = union_rocprof_trace_decoder_gfx9_header_t -class union_rocprof_trace_decoder_instrument_enable_t(Union): - pass - -class struct_rocprof_trace_decoder_instrument_enable_t_0(Structure): - pass - -struct_rocprof_trace_decoder_instrument_enable_t_0._pack_ = 1 # source:False -struct_rocprof_trace_decoder_instrument_enable_t_0._fields_ = [ - ('char1', ctypes.c_uint32, 8), - ('char2', ctypes.c_uint32, 8), - ('char3', ctypes.c_uint32, 8), - ('char4', ctypes.c_uint32, 8), +class union_rocprof_trace_decoder_instrument_enable_t(ctypes.Union): pass +class union_rocprof_trace_decoder_instrument_enable_t_0(Struct): pass +union_rocprof_trace_decoder_instrument_enable_t_0._fields_ = [ + ('char1', ctypes.c_uint32,8), + ('char2', ctypes.c_uint32,8), + ('char3', ctypes.c_uint32,8), + ('char4', ctypes.c_uint32,8), ] - -union_rocprof_trace_decoder_instrument_enable_t._pack_ = 1 # source:False -union_rocprof_trace_decoder_instrument_enable_t._anonymous_ = ('_0',) +union_rocprof_trace_decoder_instrument_enable_t._anonymous_ = ['_0'] union_rocprof_trace_decoder_instrument_enable_t._fields_ = [ - ('_0', struct_rocprof_trace_decoder_instrument_enable_t_0), - ('u32All', ctypes.c_uint32), + ('_0', union_rocprof_trace_decoder_instrument_enable_t_0), + ('u32All', ctypes.c_uint32), ] - rocprof_trace_decoder_instrument_enable_t = union_rocprof_trace_decoder_instrument_enable_t -class union_rocprof_trace_decoder_packet_header_t(Union): - pass - -class struct_rocprof_trace_decoder_packet_header_t_0(Structure): - pass - -struct_rocprof_trace_decoder_packet_header_t_0._pack_ = 1 # source:False -struct_rocprof_trace_decoder_packet_header_t_0._fields_ = [ - ('opcode', ctypes.c_uint32, 8), - ('type', ctypes.c_uint32, 4), - ('data20', ctypes.c_uint32, 20), +class union_rocprof_trace_decoder_packet_header_t(ctypes.Union): pass +class union_rocprof_trace_decoder_packet_header_t_0(Struct): pass +union_rocprof_trace_decoder_packet_header_t_0._fields_ = [ + ('opcode', ctypes.c_uint32,8), + ('type', ctypes.c_uint32,4), + ('data20', ctypes.c_uint32,20), ] - -union_rocprof_trace_decoder_packet_header_t._pack_ = 1 # source:False -union_rocprof_trace_decoder_packet_header_t._anonymous_ = ('_0',) +union_rocprof_trace_decoder_packet_header_t._anonymous_ = ['_0'] union_rocprof_trace_decoder_packet_header_t._fields_ = [ - ('_0', struct_rocprof_trace_decoder_packet_header_t_0), - ('u32All', ctypes.c_uint32), + ('_0', union_rocprof_trace_decoder_packet_header_t_0), + ('u32All', ctypes.c_uint32), ] - rocprof_trace_decoder_packet_header_t = union_rocprof_trace_decoder_packet_header_t +enum_rocprof_trace_decoder_packet_opcode_t = CEnum(ctypes.c_uint32) +ROCPROF_TRACE_DECODER_PACKET_OPCODE_CODEOBJ = enum_rocprof_trace_decoder_packet_opcode_t.define('ROCPROF_TRACE_DECODER_PACKET_OPCODE_CODEOBJ', 4) +ROCPROF_TRACE_DECODER_PACKET_OPCODE_RT_TIMESTAMP = enum_rocprof_trace_decoder_packet_opcode_t.define('ROCPROF_TRACE_DECODER_PACKET_OPCODE_RT_TIMESTAMP', 5) +ROCPROF_TRACE_DECODER_PACKET_OPCODE_AGENT_INFO = enum_rocprof_trace_decoder_packet_opcode_t.define('ROCPROF_TRACE_DECODER_PACKET_OPCODE_AGENT_INFO', 6) -# values for enumeration 'rocprof_trace_decoder_packet_opcode_t' -rocprof_trace_decoder_packet_opcode_t__enumvalues = { - 4: 'ROCPROF_TRACE_DECODER_PACKET_OPCODE_CODEOBJ', - 5: 'ROCPROF_TRACE_DECODER_PACKET_OPCODE_RT_TIMESTAMP', - 6: 'ROCPROF_TRACE_DECODER_PACKET_OPCODE_AGENT_INFO', -} -ROCPROF_TRACE_DECODER_PACKET_OPCODE_CODEOBJ = 4 -ROCPROF_TRACE_DECODER_PACKET_OPCODE_RT_TIMESTAMP = 5 -ROCPROF_TRACE_DECODER_PACKET_OPCODE_AGENT_INFO = 6 -rocprof_trace_decoder_packet_opcode_t = ctypes.c_uint32 # enum +rocprof_trace_decoder_packet_opcode_t = enum_rocprof_trace_decoder_packet_opcode_t +enum_rocprof_trace_decoder_agent_info_type_t = CEnum(ctypes.c_uint32) +ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_RT_FREQUENCY_KHZ = enum_rocprof_trace_decoder_agent_info_type_t.define('ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_RT_FREQUENCY_KHZ', 0) +ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_COUNTER_INTERVAL = enum_rocprof_trace_decoder_agent_info_type_t.define('ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_COUNTER_INTERVAL', 1) +ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_LAST = enum_rocprof_trace_decoder_agent_info_type_t.define('ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_LAST', 2) -# values for enumeration 'rocprof_trace_decoder_agent_info_type_t' -rocprof_trace_decoder_agent_info_type_t__enumvalues = { - 0: 'ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_RT_FREQUENCY_KHZ', - 1: 'ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_COUNTER_INTERVAL', - 2: 'ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_LAST', -} -ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_RT_FREQUENCY_KHZ = 0 -ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_COUNTER_INTERVAL = 1 -ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_LAST = 2 -rocprof_trace_decoder_agent_info_type_t = ctypes.c_uint32 # enum -class union_rocprof_trace_decoder_codeobj_marker_tail_t(Union): - pass - -class struct_rocprof_trace_decoder_codeobj_marker_tail_t_0(Structure): - pass - -struct_rocprof_trace_decoder_codeobj_marker_tail_t_0._pack_ = 1 # source:False -struct_rocprof_trace_decoder_codeobj_marker_tail_t_0._fields_ = [ - ('isUnload', ctypes.c_uint32, 1), - ('bFromStart', ctypes.c_uint32, 1), - ('legacy_id', ctypes.c_uint32, 30), +rocprof_trace_decoder_agent_info_type_t = enum_rocprof_trace_decoder_agent_info_type_t +class union_rocprof_trace_decoder_codeobj_marker_tail_t(ctypes.Union): pass +class union_rocprof_trace_decoder_codeobj_marker_tail_t_0(Struct): pass +uint32_t = ctypes.c_uint32 +union_rocprof_trace_decoder_codeobj_marker_tail_t_0._fields_ = [ + ('isUnload', uint32_t,1), + ('bFromStart', uint32_t,1), + ('legacy_id', uint32_t,30), ] - -union_rocprof_trace_decoder_codeobj_marker_tail_t._pack_ = 1 # source:False -union_rocprof_trace_decoder_codeobj_marker_tail_t._anonymous_ = ('_0',) +union_rocprof_trace_decoder_codeobj_marker_tail_t._anonymous_ = ['_0'] union_rocprof_trace_decoder_codeobj_marker_tail_t._fields_ = [ - ('_0', struct_rocprof_trace_decoder_codeobj_marker_tail_t_0), - ('raw', ctypes.c_uint32), + ('_0', union_rocprof_trace_decoder_codeobj_marker_tail_t_0), + ('raw', uint32_t), ] - rocprof_trace_decoder_codeobj_marker_tail_t = union_rocprof_trace_decoder_codeobj_marker_tail_t +enum_rocprof_trace_decoder_codeobj_marker_type_t = CEnum(ctypes.c_uint32) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_TAIL = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_TAIL', 0) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_LO = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_LO', 1) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_LO = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_LO', 2) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_HI = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_HI', 3) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_HI = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_HI', 4) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_LO = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_LO', 5) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_HI = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_HI', 6) +ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_LAST = enum_rocprof_trace_decoder_codeobj_marker_type_t.define('ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_LAST', 7) -# values for enumeration 'rocprof_trace_decoder_codeobj_marker_type_t' -rocprof_trace_decoder_codeobj_marker_type_t__enumvalues = { - 0: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_TAIL', - 1: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_LO', - 2: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_LO', - 3: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_HI', - 4: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_HI', - 5: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_LO', - 6: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_HI', - 7: 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_LAST', -} -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_TAIL = 0 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_LO = 1 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_LO = 2 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_HI = 3 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_HI = 4 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_LO = 5 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_HI = 6 -ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_LAST = 7 -rocprof_trace_decoder_codeobj_marker_type_t = ctypes.c_uint32 # enum -__all__ = \ - ['ROCPROFILER_THREAD_TRACE_DECODER_INFO_DATA_LOST', - 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_LAST', - 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_NONE', - 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_STITCH_INCOMPLETE', - 'ROCPROFILER_THREAD_TRACE_DECODER_INFO_WAVE_INCOMPLETE', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_BVH', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_CONTEXT', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_FLAT', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_IMMED', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_JUMP', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_LAST', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_LDS', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_MESSAGE', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_NEXT', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_NONE', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_SALU', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_SMEM', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_VALU', - 'ROCPROFILER_THREAD_TRACE_DECODER_INST_VMEM', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_DEBUG', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_GFXIP', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_INFO', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_LAST', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_PERFEVENT', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_REALTIME', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_RT_FREQUENCY', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_SHADERDATA', - 'ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE', - 'ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_IMM', - 'ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_PRIV', - 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR', - 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_ARGUMENT', - 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_INVALID_SHADER_DATA', - 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES', - 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_LAST', - 'ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS', - 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EMPTY', - 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EXEC', - 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_IDLE', - 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_LAST', - 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_STALL', - 'ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_WAIT', - 'ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_COUNTER_INTERVAL', - 'ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_LAST', - 'ROCPROF_TRACE_DECODER_AGENT_INFO_TYPE_RT_FREQUENCY_KHZ', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_HI', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ADDR_LO', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_HI', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_ID_LO', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_LAST', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_HI', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_SIZE_LO', - 'ROCPROF_TRACE_DECODER_CODEOBJ_MARKER_TYPE_TAIL', - 'ROCPROF_TRACE_DECODER_PACKET_OPCODE_AGENT_INFO', - 'ROCPROF_TRACE_DECODER_PACKET_OPCODE_CODEOBJ', - 'ROCPROF_TRACE_DECODER_PACKET_OPCODE_RT_TIMESTAMP', - 'c__EA_rocprofiler_thread_trace_decoder_status_t', - 'rocprof_trace_decoder_agent_info_type_t', - 'rocprof_trace_decoder_codeobj_marker_tail_t', - 'rocprof_trace_decoder_codeobj_marker_type_t', - 'rocprof_trace_decoder_dump_data', - 'rocprof_trace_decoder_get_info_string', - 'rocprof_trace_decoder_get_status_string', - 'rocprof_trace_decoder_gfx9_header_t', - 'rocprof_trace_decoder_instrument_enable_t', - 'rocprof_trace_decoder_isa_callback_t', - 'rocprof_trace_decoder_packet_header_t', - 'rocprof_trace_decoder_packet_opcode_t', - 'rocprof_trace_decoder_parse_data', - 'rocprof_trace_decoder_se_data_callback_t', - 'rocprof_trace_decoder_trace_callback_t', - 'rocprofiler_thread_trace_decoder_debug_callback_t', - 'rocprofiler_thread_trace_decoder_info_t', - 'rocprofiler_thread_trace_decoder_inst_category_t', - 'rocprofiler_thread_trace_decoder_inst_t', - 'rocprofiler_thread_trace_decoder_occupancy_t', - 'rocprofiler_thread_trace_decoder_pc_t', - 'rocprofiler_thread_trace_decoder_perfevent_t', - 'rocprofiler_thread_trace_decoder_realtime_t', - 'rocprofiler_thread_trace_decoder_record_type_t', - 'rocprofiler_thread_trace_decoder_shaderdata_flags_t', - 'rocprofiler_thread_trace_decoder_shaderdata_t', - 'rocprofiler_thread_trace_decoder_status_t', - 'rocprofiler_thread_trace_decoder_status_t__enumvalues', - 'rocprofiler_thread_trace_decoder_wave_state_t', - 'rocprofiler_thread_trace_decoder_wave_t', - 'rocprofiler_thread_trace_decoder_wstate_type_t', - 'struct_rocprof_trace_decoder_codeobj_marker_tail_t_0', - 'struct_rocprof_trace_decoder_gfx9_header_t_0', - 'struct_rocprof_trace_decoder_instrument_enable_t_0', - 'struct_rocprof_trace_decoder_packet_header_t_0', - 'struct_rocprofiler_thread_trace_decoder_inst_t', - 'struct_rocprofiler_thread_trace_decoder_occupancy_t', - 'struct_rocprofiler_thread_trace_decoder_pc_t', - 'struct_rocprofiler_thread_trace_decoder_perfevent_t', - 'struct_rocprofiler_thread_trace_decoder_realtime_t', - 'struct_rocprofiler_thread_trace_decoder_shaderdata_t', - 'struct_rocprofiler_thread_trace_decoder_wave_state_t', - 'struct_rocprofiler_thread_trace_decoder_wave_t', 'uint64_t', - 'union_rocprof_trace_decoder_codeobj_marker_tail_t', - 'union_rocprof_trace_decoder_gfx9_header_t', - 'union_rocprof_trace_decoder_instrument_enable_t', - 'union_rocprof_trace_decoder_packet_header_t'] +rocprof_trace_decoder_codeobj_marker_type_t = enum_rocprof_trace_decoder_codeobj_marker_type_t +rocprofiler_thread_trace_decoder_pc_t = struct_rocprofiler_thread_trace_decoder_pc_t +class struct_rocprofiler_thread_trace_decoder_perfevent_t(Struct): pass +int64_t = ctypes.c_int64 +uint16_t = ctypes.c_uint16 +uint8_t = ctypes.c_ubyte +struct_rocprofiler_thread_trace_decoder_perfevent_t._fields_ = [ + ('time', int64_t), + ('events0', uint16_t), + ('events1', uint16_t), + ('events2', uint16_t), + ('events3', uint16_t), + ('CU', uint8_t), + ('bank', uint8_t), +] +rocprofiler_thread_trace_decoder_perfevent_t = struct_rocprofiler_thread_trace_decoder_perfevent_t +class struct_rocprofiler_thread_trace_decoder_occupancy_t(Struct): pass +struct_rocprofiler_thread_trace_decoder_occupancy_t._fields_ = [ + ('pc', rocprofiler_thread_trace_decoder_pc_t), + ('time', uint64_t), + ('reserved', uint8_t), + ('cu', uint8_t), + ('simd', uint8_t), + ('wave_id', uint8_t), + ('start', uint32_t,1), + ('_rsvd', uint32_t,31), +] +rocprofiler_thread_trace_decoder_occupancy_t = struct_rocprofiler_thread_trace_decoder_occupancy_t +enum_rocprofiler_thread_trace_decoder_wstate_type_t = CEnum(ctypes.c_uint32) +ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EMPTY = enum_rocprofiler_thread_trace_decoder_wstate_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EMPTY', 0) +ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_IDLE = enum_rocprofiler_thread_trace_decoder_wstate_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_IDLE', 1) +ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EXEC = enum_rocprofiler_thread_trace_decoder_wstate_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_EXEC', 2) +ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_WAIT = enum_rocprofiler_thread_trace_decoder_wstate_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_WAIT', 3) +ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_STALL = enum_rocprofiler_thread_trace_decoder_wstate_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_STALL', 4) +ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_LAST = enum_rocprofiler_thread_trace_decoder_wstate_type_t.define('ROCPROFILER_THREAD_TRACE_DECODER_WSTATE_LAST', 5) + +rocprofiler_thread_trace_decoder_wstate_type_t = enum_rocprofiler_thread_trace_decoder_wstate_type_t +class struct_rocprofiler_thread_trace_decoder_wave_state_t(Struct): pass +int32_t = ctypes.c_int32 +struct_rocprofiler_thread_trace_decoder_wave_state_t._fields_ = [ + ('type', int32_t), + ('duration', int32_t), +] +rocprofiler_thread_trace_decoder_wave_state_t = struct_rocprofiler_thread_trace_decoder_wave_state_t +enum_rocprofiler_thread_trace_decoder_inst_category_t = CEnum(ctypes.c_uint32) +ROCPROFILER_THREAD_TRACE_DECODER_INST_NONE = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_NONE', 0) +ROCPROFILER_THREAD_TRACE_DECODER_INST_SMEM = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_SMEM', 1) +ROCPROFILER_THREAD_TRACE_DECODER_INST_SALU = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_SALU', 2) +ROCPROFILER_THREAD_TRACE_DECODER_INST_VMEM = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_VMEM', 3) +ROCPROFILER_THREAD_TRACE_DECODER_INST_FLAT = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_FLAT', 4) +ROCPROFILER_THREAD_TRACE_DECODER_INST_LDS = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_LDS', 5) +ROCPROFILER_THREAD_TRACE_DECODER_INST_VALU = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_VALU', 6) +ROCPROFILER_THREAD_TRACE_DECODER_INST_JUMP = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_JUMP', 7) +ROCPROFILER_THREAD_TRACE_DECODER_INST_NEXT = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_NEXT', 8) +ROCPROFILER_THREAD_TRACE_DECODER_INST_IMMED = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_IMMED', 9) +ROCPROFILER_THREAD_TRACE_DECODER_INST_CONTEXT = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_CONTEXT', 10) +ROCPROFILER_THREAD_TRACE_DECODER_INST_MESSAGE = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_MESSAGE', 11) +ROCPROFILER_THREAD_TRACE_DECODER_INST_BVH = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_BVH', 12) +ROCPROFILER_THREAD_TRACE_DECODER_INST_LAST = enum_rocprofiler_thread_trace_decoder_inst_category_t.define('ROCPROFILER_THREAD_TRACE_DECODER_INST_LAST', 13) + +rocprofiler_thread_trace_decoder_inst_category_t = enum_rocprofiler_thread_trace_decoder_inst_category_t +class struct_rocprofiler_thread_trace_decoder_inst_t(Struct): pass +struct_rocprofiler_thread_trace_decoder_inst_t._fields_ = [ + ('category', uint32_t,8), + ('stall', uint32_t,24), + ('duration', int32_t), + ('time', int64_t), + ('pc', rocprofiler_thread_trace_decoder_pc_t), +] +rocprofiler_thread_trace_decoder_inst_t = struct_rocprofiler_thread_trace_decoder_inst_t +class struct_rocprofiler_thread_trace_decoder_wave_t(Struct): pass +struct_rocprofiler_thread_trace_decoder_wave_t._fields_ = [ + ('cu', uint8_t), + ('simd', uint8_t), + ('wave_id', uint8_t), + ('contexts', uint8_t), + ('_rsvd1', uint32_t), + ('_rsvd2', uint32_t), + ('_rsvd3', uint32_t), + ('begin_time', int64_t), + ('end_time', int64_t), + ('timeline_size', uint64_t), + ('instructions_size', uint64_t), + ('timeline_array', ctypes.POINTER(rocprofiler_thread_trace_decoder_wave_state_t)), + ('instructions_array', ctypes.POINTER(rocprofiler_thread_trace_decoder_inst_t)), +] +rocprofiler_thread_trace_decoder_wave_t = struct_rocprofiler_thread_trace_decoder_wave_t +class struct_rocprofiler_thread_trace_decoder_realtime_t(Struct): pass +struct_rocprofiler_thread_trace_decoder_realtime_t._fields_ = [ + ('shader_clock', int64_t), + ('realtime_clock', uint64_t), + ('reserved', uint64_t), +] +rocprofiler_thread_trace_decoder_realtime_t = struct_rocprofiler_thread_trace_decoder_realtime_t +enum_rocprofiler_thread_trace_decoder_shaderdata_flags_t = CEnum(ctypes.c_uint32) +ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_IMM = enum_rocprofiler_thread_trace_decoder_shaderdata_flags_t.define('ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_IMM', 0) +ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_PRIV = enum_rocprofiler_thread_trace_decoder_shaderdata_flags_t.define('ROCPROFILER_THREAD_TRACE_DECODER_SHADERDATA_FLAGS_PRIV', 1) + +rocprofiler_thread_trace_decoder_shaderdata_flags_t = enum_rocprofiler_thread_trace_decoder_shaderdata_flags_t +class struct_rocprofiler_thread_trace_decoder_shaderdata_t(Struct): pass +struct_rocprofiler_thread_trace_decoder_shaderdata_t._fields_ = [ + ('time', int64_t), + ('value', uint64_t), + ('cu', uint8_t), + ('simd', uint8_t), + ('wave_id', uint8_t), + ('flags', uint8_t), + ('reserved', uint32_t), +] +rocprofiler_thread_trace_decoder_shaderdata_t = struct_rocprofiler_thread_trace_decoder_shaderdata_t +rocprofiler_thread_trace_decoder_record_type_t = enum_rocprofiler_thread_trace_decoder_record_type_t diff --git a/tinygrad/runtime/autogen/sqtt.py b/tinygrad/runtime/autogen/sqtt.py index 422f736994..10cb1e8300 100644 --- a/tinygrad/runtime/autogen/sqtt.py +++ b/tinygrad/runtime/autogen/sqtt.py @@ -1,1803 +1,879 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, os - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - - - -SQTT_FILE_MAGIC_NUMBER = 0x50303042 # macro -SQTT_FILE_VERSION_MAJOR = 1 # macro -SQTT_FILE_VERSION_MINOR = 5 # macro -SQTT_GPU_NAME_MAX_SIZE = 256 # macro -SQTT_MAX_NUM_SE = 32 # macro -SQTT_SA_PER_SE = 2 # macro -SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS = 4 # macro -class struct_sqtt_data_info(Structure): - pass - -class union_sqtt_data_info_0(Union): - pass - -union_sqtt_data_info_0._pack_ = 1 # source:False -union_sqtt_data_info_0._fields_ = [ - ('gfx9_write_counter', ctypes.c_uint32), - ('gfx10_dropped_cntr', ctypes.c_uint32), +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class struct_sqtt_data_info(Struct): pass +uint32_t = ctypes.c_uint32 +class struct_sqtt_data_info_0(ctypes.Union): pass +struct_sqtt_data_info_0._fields_ = [ + ('gfx9_write_counter', uint32_t), + ('gfx10_dropped_cntr', uint32_t), ] - -struct_sqtt_data_info._pack_ = 1 # source:False -struct_sqtt_data_info._anonymous_ = ('_0',) +struct_sqtt_data_info._anonymous_ = ['_0'] struct_sqtt_data_info._fields_ = [ - ('cur_offset', ctypes.c_uint32), - ('trace_status', ctypes.c_uint32), - ('_0', union_sqtt_data_info_0), + ('cur_offset', uint32_t), + ('trace_status', uint32_t), + ('_0', struct_sqtt_data_info_0), ] - -class struct_sqtt_data_se(Structure): - pass - -struct_sqtt_data_se._pack_ = 1 # source:False +class struct_sqtt_data_se(Struct): pass struct_sqtt_data_se._fields_ = [ - ('info', struct_sqtt_data_info), - ('PADDING_0', ctypes.c_ubyte * 4), - ('data_ptr', ctypes.POINTER(None)), - ('shader_engine', ctypes.c_uint32), - ('compute_unit', ctypes.c_uint32), + ('info', struct_sqtt_data_info), + ('data_ptr', ctypes.c_void_p), + ('shader_engine', uint32_t), + ('compute_unit', uint32_t), ] +enum_sqtt_version = CEnum(ctypes.c_uint32) +SQTT_VERSION_NONE = enum_sqtt_version.define('SQTT_VERSION_NONE', 0) +SQTT_VERSION_2_2 = enum_sqtt_version.define('SQTT_VERSION_2_2', 5) +SQTT_VERSION_2_3 = enum_sqtt_version.define('SQTT_VERSION_2_3', 6) +SQTT_VERSION_2_4 = enum_sqtt_version.define('SQTT_VERSION_2_4', 7) +SQTT_VERSION_3_2 = enum_sqtt_version.define('SQTT_VERSION_3_2', 11) +SQTT_VERSION_3_3 = enum_sqtt_version.define('SQTT_VERSION_3_3', 12) +enum_sqtt_file_chunk_type = CEnum(ctypes.c_uint32) +SQTT_FILE_CHUNK_TYPE_ASIC_INFO = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_ASIC_INFO', 0) +SQTT_FILE_CHUNK_TYPE_SQTT_DESC = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_SQTT_DESC', 1) +SQTT_FILE_CHUNK_TYPE_SQTT_DATA = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_SQTT_DATA', 2) +SQTT_FILE_CHUNK_TYPE_API_INFO = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_API_INFO', 3) +SQTT_FILE_CHUNK_TYPE_RESERVED = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_RESERVED', 4) +SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS', 5) +SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION', 6) +SQTT_FILE_CHUNK_TYPE_CPU_INFO = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_CPU_INFO', 7) +SQTT_FILE_CHUNK_TYPE_SPM_DB = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_SPM_DB', 8) +SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE', 9) +SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS', 10) +SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION', 11) +SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE', 12) +SQTT_FILE_CHUNK_TYPE_COUNT = enum_sqtt_file_chunk_type.define('SQTT_FILE_CHUNK_TYPE_COUNT', 13) -# values for enumeration 'sqtt_version' -sqtt_version__enumvalues = { - 0: 'SQTT_VERSION_NONE', - 5: 'SQTT_VERSION_2_2', - 6: 'SQTT_VERSION_2_3', - 7: 'SQTT_VERSION_2_4', - 11: 'SQTT_VERSION_3_2', - 12: 'SQTT_VERSION_3_3', -} -SQTT_VERSION_NONE = 0 -SQTT_VERSION_2_2 = 5 -SQTT_VERSION_2_3 = 6 -SQTT_VERSION_2_4 = 7 -SQTT_VERSION_3_2 = 11 -SQTT_VERSION_3_3 = 12 -sqtt_version = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_file_chunk_type' -sqtt_file_chunk_type__enumvalues = { - 0: 'SQTT_FILE_CHUNK_TYPE_ASIC_INFO', - 1: 'SQTT_FILE_CHUNK_TYPE_SQTT_DESC', - 2: 'SQTT_FILE_CHUNK_TYPE_SQTT_DATA', - 3: 'SQTT_FILE_CHUNK_TYPE_API_INFO', - 4: 'SQTT_FILE_CHUNK_TYPE_RESERVED', - 5: 'SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS', - 6: 'SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION', - 7: 'SQTT_FILE_CHUNK_TYPE_CPU_INFO', - 8: 'SQTT_FILE_CHUNK_TYPE_SPM_DB', - 9: 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE', - 10: 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS', - 11: 'SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION', - 12: 'SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE', - 13: 'SQTT_FILE_CHUNK_TYPE_COUNT', -} -SQTT_FILE_CHUNK_TYPE_ASIC_INFO = 0 -SQTT_FILE_CHUNK_TYPE_SQTT_DESC = 1 -SQTT_FILE_CHUNK_TYPE_SQTT_DATA = 2 -SQTT_FILE_CHUNK_TYPE_API_INFO = 3 -SQTT_FILE_CHUNK_TYPE_RESERVED = 4 -SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS = 5 -SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION = 6 -SQTT_FILE_CHUNK_TYPE_CPU_INFO = 7 -SQTT_FILE_CHUNK_TYPE_SPM_DB = 8 -SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE = 9 -SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS = 10 -SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION = 11 -SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE = 12 -SQTT_FILE_CHUNK_TYPE_COUNT = 13 -sqtt_file_chunk_type = ctypes.c_uint32 # enum -class struct_sqtt_file_chunk_id(Structure): - pass - -struct_sqtt_file_chunk_id._pack_ = 1 # source:False +class struct_sqtt_file_chunk_id(Struct): pass +int32_t = ctypes.c_int32 struct_sqtt_file_chunk_id._fields_ = [ - ('type', ctypes.c_int32, 8), - ('index', ctypes.c_int32, 8), - ('reserved', ctypes.c_int32, 16), + ('type', int32_t,8), + ('index', int32_t,8), + ('reserved', int32_t,16), ] - -class struct_sqtt_file_chunk_header(Structure): - pass - -struct_sqtt_file_chunk_header._pack_ = 1 # source:False +class struct_sqtt_file_chunk_header(Struct): pass +uint16_t = ctypes.c_uint16 struct_sqtt_file_chunk_header._fields_ = [ - ('chunk_id', struct_sqtt_file_chunk_id), - ('minor_version', ctypes.c_uint16), - ('major_version', ctypes.c_uint16), - ('size_in_bytes', ctypes.c_int32), - ('padding', ctypes.c_int32), + ('chunk_id', struct_sqtt_file_chunk_id), + ('minor_version', uint16_t), + ('major_version', uint16_t), + ('size_in_bytes', int32_t), + ('padding', int32_t), ] - -class struct_sqtt_file_header_flags(Structure): - pass - -class union_sqtt_file_header_flags_0(Union): - pass - -class struct_sqtt_file_header_flags_0_0(Structure): - pass - -struct_sqtt_file_header_flags_0_0._pack_ = 1 # source:False +class struct_sqtt_file_header_flags(Struct): pass +class struct_sqtt_file_header_flags_0(ctypes.Union): pass +class struct_sqtt_file_header_flags_0_0(Struct): pass struct_sqtt_file_header_flags_0_0._fields_ = [ - ('is_semaphore_queue_timing_etw', ctypes.c_uint32, 1), - ('no_queue_semaphore_timestamps', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 30), + ('is_semaphore_queue_timing_etw', uint32_t,1), + ('no_queue_semaphore_timestamps', uint32_t,1), + ('reserved', uint32_t,30), ] - -union_sqtt_file_header_flags_0._pack_ = 1 # source:False -union_sqtt_file_header_flags_0._anonymous_ = ('_0',) -union_sqtt_file_header_flags_0._fields_ = [ - ('_0', struct_sqtt_file_header_flags_0_0), - ('value', ctypes.c_uint32), +struct_sqtt_file_header_flags_0._anonymous_ = ['_0'] +struct_sqtt_file_header_flags_0._fields_ = [ + ('_0', struct_sqtt_file_header_flags_0_0), + ('value', uint32_t), ] - -struct_sqtt_file_header_flags._pack_ = 1 # source:False -struct_sqtt_file_header_flags._anonymous_ = ('_0',) +struct_sqtt_file_header_flags._anonymous_ = ['_0'] struct_sqtt_file_header_flags._fields_ = [ - ('_0', union_sqtt_file_header_flags_0), + ('_0', struct_sqtt_file_header_flags_0), ] - -class struct_sqtt_file_header(Structure): - pass - -struct_sqtt_file_header._pack_ = 1 # source:False +class struct_sqtt_file_header(Struct): pass struct_sqtt_file_header._fields_ = [ - ('magic_number', ctypes.c_uint32), - ('version_major', ctypes.c_uint32), - ('version_minor', ctypes.c_uint32), - ('flags', struct_sqtt_file_header_flags), - ('chunk_offset', ctypes.c_int32), - ('second', ctypes.c_int32), - ('minute', ctypes.c_int32), - ('hour', ctypes.c_int32), - ('day_in_month', ctypes.c_int32), - ('month', ctypes.c_int32), - ('year', ctypes.c_int32), - ('day_in_week', ctypes.c_int32), - ('day_in_year', ctypes.c_int32), - ('is_daylight_savings', ctypes.c_int32), + ('magic_number', uint32_t), + ('version_major', uint32_t), + ('version_minor', uint32_t), + ('flags', struct_sqtt_file_header_flags), + ('chunk_offset', int32_t), + ('second', int32_t), + ('minute', int32_t), + ('hour', int32_t), + ('day_in_month', int32_t), + ('month', int32_t), + ('year', int32_t), + ('day_in_week', int32_t), + ('day_in_year', int32_t), + ('is_daylight_savings', int32_t), ] - -class struct_sqtt_file_chunk_cpu_info(Structure): - pass - -struct_sqtt_file_chunk_cpu_info._pack_ = 1 # source:False +class struct_sqtt_file_chunk_cpu_info(Struct): pass +uint64_t = ctypes.c_uint64 struct_sqtt_file_chunk_cpu_info._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('vendor_id', ctypes.c_uint32 * 4), - ('processor_brand', ctypes.c_uint32 * 12), - ('reserved', ctypes.c_uint32 * 2), - ('cpu_timestamp_freq', ctypes.c_uint64), - ('clock_speed', ctypes.c_uint32), - ('num_logical_cores', ctypes.c_uint32), - ('num_physical_cores', ctypes.c_uint32), - ('system_ram_size', ctypes.c_uint32), + ('header', struct_sqtt_file_chunk_header), + ('vendor_id', (uint32_t * 4)), + ('processor_brand', (uint32_t * 12)), + ('reserved', (uint32_t * 2)), + ('cpu_timestamp_freq', uint64_t), + ('clock_speed', uint32_t), + ('num_logical_cores', uint32_t), + ('num_physical_cores', uint32_t), + ('system_ram_size', uint32_t), ] +enum_sqtt_file_chunk_asic_info_flags = CEnum(ctypes.c_uint32) +SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING = enum_sqtt_file_chunk_asic_info_flags.define('SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING', 1) +SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED = enum_sqtt_file_chunk_asic_info_flags.define('SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED', 2) +enum_sqtt_gpu_type = CEnum(ctypes.c_uint32) +SQTT_GPU_TYPE_UNKNOWN = enum_sqtt_gpu_type.define('SQTT_GPU_TYPE_UNKNOWN', 0) +SQTT_GPU_TYPE_INTEGRATED = enum_sqtt_gpu_type.define('SQTT_GPU_TYPE_INTEGRATED', 1) +SQTT_GPU_TYPE_DISCRETE = enum_sqtt_gpu_type.define('SQTT_GPU_TYPE_DISCRETE', 2) +SQTT_GPU_TYPE_VIRTUAL = enum_sqtt_gpu_type.define('SQTT_GPU_TYPE_VIRTUAL', 3) -# values for enumeration 'sqtt_file_chunk_asic_info_flags' -sqtt_file_chunk_asic_info_flags__enumvalues = { - 1: 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING', - 2: 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED', -} -SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING = 1 -SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED = 2 -sqtt_file_chunk_asic_info_flags = ctypes.c_uint32 # enum +enum_sqtt_gfxip_level = CEnum(ctypes.c_uint32) +SQTT_GFXIP_LEVEL_NONE = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_NONE', 0) +SQTT_GFXIP_LEVEL_GFXIP_6 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_6', 1) +SQTT_GFXIP_LEVEL_GFXIP_7 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_7', 2) +SQTT_GFXIP_LEVEL_GFXIP_8 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_8', 3) +SQTT_GFXIP_LEVEL_GFXIP_8_1 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_8_1', 4) +SQTT_GFXIP_LEVEL_GFXIP_9 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_9', 5) +SQTT_GFXIP_LEVEL_GFXIP_10_1 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_10_1', 7) +SQTT_GFXIP_LEVEL_GFXIP_10_3 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_10_3', 9) +SQTT_GFXIP_LEVEL_GFXIP_11_0 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_11_0', 12) +SQTT_GFXIP_LEVEL_GFXIP_11_5 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_11_5', 13) +SQTT_GFXIP_LEVEL_GFXIP_12 = enum_sqtt_gfxip_level.define('SQTT_GFXIP_LEVEL_GFXIP_12', 16) -# values for enumeration 'sqtt_gpu_type' -sqtt_gpu_type__enumvalues = { - 0: 'SQTT_GPU_TYPE_UNKNOWN', - 1: 'SQTT_GPU_TYPE_INTEGRATED', - 2: 'SQTT_GPU_TYPE_DISCRETE', - 3: 'SQTT_GPU_TYPE_VIRTUAL', -} -SQTT_GPU_TYPE_UNKNOWN = 0 -SQTT_GPU_TYPE_INTEGRATED = 1 -SQTT_GPU_TYPE_DISCRETE = 2 -SQTT_GPU_TYPE_VIRTUAL = 3 -sqtt_gpu_type = ctypes.c_uint32 # enum +enum_sqtt_memory_type = CEnum(ctypes.c_uint32) +SQTT_MEMORY_TYPE_UNKNOWN = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_UNKNOWN', 0) +SQTT_MEMORY_TYPE_DDR = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_DDR', 1) +SQTT_MEMORY_TYPE_DDR2 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_DDR2', 2) +SQTT_MEMORY_TYPE_DDR3 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_DDR3', 3) +SQTT_MEMORY_TYPE_DDR4 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_DDR4', 4) +SQTT_MEMORY_TYPE_DDR5 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_DDR5', 5) +SQTT_MEMORY_TYPE_GDDR3 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_GDDR3', 16) +SQTT_MEMORY_TYPE_GDDR4 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_GDDR4', 17) +SQTT_MEMORY_TYPE_GDDR5 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_GDDR5', 18) +SQTT_MEMORY_TYPE_GDDR6 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_GDDR6', 19) +SQTT_MEMORY_TYPE_HBM = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_HBM', 32) +SQTT_MEMORY_TYPE_HBM2 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_HBM2', 33) +SQTT_MEMORY_TYPE_HBM3 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_HBM3', 34) +SQTT_MEMORY_TYPE_LPDDR4 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_LPDDR4', 48) +SQTT_MEMORY_TYPE_LPDDR5 = enum_sqtt_memory_type.define('SQTT_MEMORY_TYPE_LPDDR5', 49) -# values for enumeration 'sqtt_gfxip_level' -sqtt_gfxip_level__enumvalues = { - 0: 'SQTT_GFXIP_LEVEL_NONE', - 1: 'SQTT_GFXIP_LEVEL_GFXIP_6', - 2: 'SQTT_GFXIP_LEVEL_GFXIP_7', - 3: 'SQTT_GFXIP_LEVEL_GFXIP_8', - 4: 'SQTT_GFXIP_LEVEL_GFXIP_8_1', - 5: 'SQTT_GFXIP_LEVEL_GFXIP_9', - 7: 'SQTT_GFXIP_LEVEL_GFXIP_10_1', - 9: 'SQTT_GFXIP_LEVEL_GFXIP_10_3', - 12: 'SQTT_GFXIP_LEVEL_GFXIP_11_0', - 13: 'SQTT_GFXIP_LEVEL_GFXIP_11_5', - 16: 'SQTT_GFXIP_LEVEL_GFXIP_12', -} -SQTT_GFXIP_LEVEL_NONE = 0 -SQTT_GFXIP_LEVEL_GFXIP_6 = 1 -SQTT_GFXIP_LEVEL_GFXIP_7 = 2 -SQTT_GFXIP_LEVEL_GFXIP_8 = 3 -SQTT_GFXIP_LEVEL_GFXIP_8_1 = 4 -SQTT_GFXIP_LEVEL_GFXIP_9 = 5 -SQTT_GFXIP_LEVEL_GFXIP_10_1 = 7 -SQTT_GFXIP_LEVEL_GFXIP_10_3 = 9 -SQTT_GFXIP_LEVEL_GFXIP_11_0 = 12 -SQTT_GFXIP_LEVEL_GFXIP_11_5 = 13 -SQTT_GFXIP_LEVEL_GFXIP_12 = 16 -sqtt_gfxip_level = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_memory_type' -sqtt_memory_type__enumvalues = { - 0: 'SQTT_MEMORY_TYPE_UNKNOWN', - 1: 'SQTT_MEMORY_TYPE_DDR', - 2: 'SQTT_MEMORY_TYPE_DDR2', - 3: 'SQTT_MEMORY_TYPE_DDR3', - 4: 'SQTT_MEMORY_TYPE_DDR4', - 5: 'SQTT_MEMORY_TYPE_DDR5', - 16: 'SQTT_MEMORY_TYPE_GDDR3', - 17: 'SQTT_MEMORY_TYPE_GDDR4', - 18: 'SQTT_MEMORY_TYPE_GDDR5', - 19: 'SQTT_MEMORY_TYPE_GDDR6', - 32: 'SQTT_MEMORY_TYPE_HBM', - 33: 'SQTT_MEMORY_TYPE_HBM2', - 34: 'SQTT_MEMORY_TYPE_HBM3', - 48: 'SQTT_MEMORY_TYPE_LPDDR4', - 49: 'SQTT_MEMORY_TYPE_LPDDR5', -} -SQTT_MEMORY_TYPE_UNKNOWN = 0 -SQTT_MEMORY_TYPE_DDR = 1 -SQTT_MEMORY_TYPE_DDR2 = 2 -SQTT_MEMORY_TYPE_DDR3 = 3 -SQTT_MEMORY_TYPE_DDR4 = 4 -SQTT_MEMORY_TYPE_DDR5 = 5 -SQTT_MEMORY_TYPE_GDDR3 = 16 -SQTT_MEMORY_TYPE_GDDR4 = 17 -SQTT_MEMORY_TYPE_GDDR5 = 18 -SQTT_MEMORY_TYPE_GDDR6 = 19 -SQTT_MEMORY_TYPE_HBM = 32 -SQTT_MEMORY_TYPE_HBM2 = 33 -SQTT_MEMORY_TYPE_HBM3 = 34 -SQTT_MEMORY_TYPE_LPDDR4 = 48 -SQTT_MEMORY_TYPE_LPDDR5 = 49 -sqtt_memory_type = ctypes.c_uint32 # enum -class struct_sqtt_file_chunk_asic_info(Structure): - pass - -struct_sqtt_file_chunk_asic_info._pack_ = 1 # source:False +class struct_sqtt_file_chunk_asic_info(Struct): pass +int64_t = ctypes.c_int64 struct_sqtt_file_chunk_asic_info._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('flags', ctypes.c_uint64), - ('trace_shader_core_clock', ctypes.c_uint64), - ('trace_memory_clock', ctypes.c_uint64), - ('device_id', ctypes.c_int32), - ('device_revision_id', ctypes.c_int32), - ('vgprs_per_simd', ctypes.c_int32), - ('sgprs_per_simd', ctypes.c_int32), - ('shader_engines', ctypes.c_int32), - ('compute_unit_per_shader_engine', ctypes.c_int32), - ('simd_per_compute_unit', ctypes.c_int32), - ('wavefronts_per_simd', ctypes.c_int32), - ('minimum_vgpr_alloc', ctypes.c_int32), - ('vgpr_alloc_granularity', ctypes.c_int32), - ('minimum_sgpr_alloc', ctypes.c_int32), - ('sgpr_alloc_granularity', ctypes.c_int32), - ('hardware_contexts', ctypes.c_int32), - ('gpu_type', sqtt_gpu_type), - ('gfxip_level', sqtt_gfxip_level), - ('gpu_index', ctypes.c_int32), - ('gds_size', ctypes.c_int32), - ('gds_per_shader_engine', ctypes.c_int32), - ('ce_ram_size', ctypes.c_int32), - ('ce_ram_size_graphics', ctypes.c_int32), - ('ce_ram_size_compute', ctypes.c_int32), - ('max_number_of_dedicated_cus', ctypes.c_int32), - ('vram_size', ctypes.c_int64), - ('vram_bus_width', ctypes.c_int32), - ('l2_cache_size', ctypes.c_int32), - ('l1_cache_size', ctypes.c_int32), - ('lds_size', ctypes.c_int32), - ('gpu_name', ctypes.c_char * 256), - ('alu_per_clock', ctypes.c_float), - ('texture_per_clock', ctypes.c_float), - ('prims_per_clock', ctypes.c_float), - ('pixels_per_clock', ctypes.c_float), - ('gpu_timestamp_frequency', ctypes.c_uint64), - ('max_shader_core_clock', ctypes.c_uint64), - ('max_memory_clock', ctypes.c_uint64), - ('memory_ops_per_clock', ctypes.c_uint32), - ('memory_chip_type', sqtt_memory_type), - ('lds_granularity', ctypes.c_uint32), - ('cu_mask', ctypes.c_uint16 * 2 * 32), - ('reserved1', ctypes.c_char * 128), - ('active_pixel_packer_mask', ctypes.c_uint32 * 4), - ('reserved2', ctypes.c_char * 16), - ('gl1_cache_size', ctypes.c_uint32), - ('instruction_cache_size', ctypes.c_uint32), - ('scalar_cache_size', ctypes.c_uint32), - ('mall_cache_size', ctypes.c_uint32), - ('padding', ctypes.c_char * 4), + ('header', struct_sqtt_file_chunk_header), + ('flags', uint64_t), + ('trace_shader_core_clock', uint64_t), + ('trace_memory_clock', uint64_t), + ('device_id', int32_t), + ('device_revision_id', int32_t), + ('vgprs_per_simd', int32_t), + ('sgprs_per_simd', int32_t), + ('shader_engines', int32_t), + ('compute_unit_per_shader_engine', int32_t), + ('simd_per_compute_unit', int32_t), + ('wavefronts_per_simd', int32_t), + ('minimum_vgpr_alloc', int32_t), + ('vgpr_alloc_granularity', int32_t), + ('minimum_sgpr_alloc', int32_t), + ('sgpr_alloc_granularity', int32_t), + ('hardware_contexts', int32_t), + ('gpu_type', enum_sqtt_gpu_type), + ('gfxip_level', enum_sqtt_gfxip_level), + ('gpu_index', int32_t), + ('gds_size', int32_t), + ('gds_per_shader_engine', int32_t), + ('ce_ram_size', int32_t), + ('ce_ram_size_graphics', int32_t), + ('ce_ram_size_compute', int32_t), + ('max_number_of_dedicated_cus', int32_t), + ('vram_size', int64_t), + ('vram_bus_width', int32_t), + ('l2_cache_size', int32_t), + ('l1_cache_size', int32_t), + ('lds_size', int32_t), + ('gpu_name', (ctypes.c_char * 256)), + ('alu_per_clock', ctypes.c_float), + ('texture_per_clock', ctypes.c_float), + ('prims_per_clock', ctypes.c_float), + ('pixels_per_clock', ctypes.c_float), + ('gpu_timestamp_frequency', uint64_t), + ('max_shader_core_clock', uint64_t), + ('max_memory_clock', uint64_t), + ('memory_ops_per_clock', uint32_t), + ('memory_chip_type', enum_sqtt_memory_type), + ('lds_granularity', uint32_t), + ('cu_mask', ((uint16_t * 2) * 32)), + ('reserved1', (ctypes.c_char * 128)), + ('active_pixel_packer_mask', (uint32_t * 4)), + ('reserved2', (ctypes.c_char * 16)), + ('gl1_cache_size', uint32_t), + ('instruction_cache_size', uint32_t), + ('scalar_cache_size', uint32_t), + ('mall_cache_size', uint32_t), + ('padding', (ctypes.c_char * 4)), ] +enum_sqtt_api_type = CEnum(ctypes.c_uint32) +SQTT_API_TYPE_DIRECTX_12 = enum_sqtt_api_type.define('SQTT_API_TYPE_DIRECTX_12', 0) +SQTT_API_TYPE_VULKAN = enum_sqtt_api_type.define('SQTT_API_TYPE_VULKAN', 1) +SQTT_API_TYPE_GENERIC = enum_sqtt_api_type.define('SQTT_API_TYPE_GENERIC', 2) +SQTT_API_TYPE_OPENCL = enum_sqtt_api_type.define('SQTT_API_TYPE_OPENCL', 3) +enum_sqtt_instruction_trace_mode = CEnum(ctypes.c_uint32) +SQTT_INSTRUCTION_TRACE_DISABLED = enum_sqtt_instruction_trace_mode.define('SQTT_INSTRUCTION_TRACE_DISABLED', 0) +SQTT_INSTRUCTION_TRACE_FULL_FRAME = enum_sqtt_instruction_trace_mode.define('SQTT_INSTRUCTION_TRACE_FULL_FRAME', 1) +SQTT_INSTRUCTION_TRACE_API_PSO = enum_sqtt_instruction_trace_mode.define('SQTT_INSTRUCTION_TRACE_API_PSO', 2) -# values for enumeration 'sqtt_api_type' -sqtt_api_type__enumvalues = { - 0: 'SQTT_API_TYPE_DIRECTX_12', - 1: 'SQTT_API_TYPE_VULKAN', - 2: 'SQTT_API_TYPE_GENERIC', - 3: 'SQTT_API_TYPE_OPENCL', -} -SQTT_API_TYPE_DIRECTX_12 = 0 -SQTT_API_TYPE_VULKAN = 1 -SQTT_API_TYPE_GENERIC = 2 -SQTT_API_TYPE_OPENCL = 3 -sqtt_api_type = ctypes.c_uint32 # enum +enum_sqtt_profiling_mode = CEnum(ctypes.c_uint32) +SQTT_PROFILING_MODE_PRESENT = enum_sqtt_profiling_mode.define('SQTT_PROFILING_MODE_PRESENT', 0) +SQTT_PROFILING_MODE_USER_MARKERS = enum_sqtt_profiling_mode.define('SQTT_PROFILING_MODE_USER_MARKERS', 1) +SQTT_PROFILING_MODE_INDEX = enum_sqtt_profiling_mode.define('SQTT_PROFILING_MODE_INDEX', 2) +SQTT_PROFILING_MODE_TAG = enum_sqtt_profiling_mode.define('SQTT_PROFILING_MODE_TAG', 3) -# values for enumeration 'sqtt_instruction_trace_mode' -sqtt_instruction_trace_mode__enumvalues = { - 0: 'SQTT_INSTRUCTION_TRACE_DISABLED', - 1: 'SQTT_INSTRUCTION_TRACE_FULL_FRAME', - 2: 'SQTT_INSTRUCTION_TRACE_API_PSO', -} -SQTT_INSTRUCTION_TRACE_DISABLED = 0 -SQTT_INSTRUCTION_TRACE_FULL_FRAME = 1 -SQTT_INSTRUCTION_TRACE_API_PSO = 2 -sqtt_instruction_trace_mode = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_profiling_mode' -sqtt_profiling_mode__enumvalues = { - 0: 'SQTT_PROFILING_MODE_PRESENT', - 1: 'SQTT_PROFILING_MODE_USER_MARKERS', - 2: 'SQTT_PROFILING_MODE_INDEX', - 3: 'SQTT_PROFILING_MODE_TAG', -} -SQTT_PROFILING_MODE_PRESENT = 0 -SQTT_PROFILING_MODE_USER_MARKERS = 1 -SQTT_PROFILING_MODE_INDEX = 2 -SQTT_PROFILING_MODE_TAG = 3 -sqtt_profiling_mode = ctypes.c_uint32 # enum -class union_sqtt_profiling_mode_data(Union): - pass - -class struct_sqtt_profiling_mode_data_user_marker_profiling_data(Structure): - pass - -struct_sqtt_profiling_mode_data_user_marker_profiling_data._pack_ = 1 # source:False -struct_sqtt_profiling_mode_data_user_marker_profiling_data._fields_ = [ - ('start', ctypes.c_char * 256), - ('end', ctypes.c_char * 256), +class union_sqtt_profiling_mode_data(ctypes.Union): pass +class union_sqtt_profiling_mode_data_user_marker_profiling_data(Struct): pass +union_sqtt_profiling_mode_data_user_marker_profiling_data._fields_ = [ + ('start', (ctypes.c_char * 256)), + ('end', (ctypes.c_char * 256)), ] - -class struct_sqtt_profiling_mode_data_index_profiling_data(Structure): - pass - -struct_sqtt_profiling_mode_data_index_profiling_data._pack_ = 1 # source:False -struct_sqtt_profiling_mode_data_index_profiling_data._fields_ = [ - ('start', ctypes.c_uint32), - ('end', ctypes.c_uint32), +class union_sqtt_profiling_mode_data_index_profiling_data(Struct): pass +union_sqtt_profiling_mode_data_index_profiling_data._fields_ = [ + ('start', uint32_t), + ('end', uint32_t), ] - -class struct_sqtt_profiling_mode_data_tag_profiling_data(Structure): - pass - -struct_sqtt_profiling_mode_data_tag_profiling_data._pack_ = 1 # source:False -struct_sqtt_profiling_mode_data_tag_profiling_data._fields_ = [ - ('begin_hi', ctypes.c_uint32), - ('begin_lo', ctypes.c_uint32), - ('end_hi', ctypes.c_uint32), - ('end_lo', ctypes.c_uint32), +class union_sqtt_profiling_mode_data_tag_profiling_data(Struct): pass +union_sqtt_profiling_mode_data_tag_profiling_data._fields_ = [ + ('begin_hi', uint32_t), + ('begin_lo', uint32_t), + ('end_hi', uint32_t), + ('end_lo', uint32_t), ] - -union_sqtt_profiling_mode_data._pack_ = 1 # source:False union_sqtt_profiling_mode_data._fields_ = [ - ('user_marker_profiling_data', struct_sqtt_profiling_mode_data_user_marker_profiling_data), - ('index_profiling_data', struct_sqtt_profiling_mode_data_index_profiling_data), - ('tag_profiling_data', struct_sqtt_profiling_mode_data_tag_profiling_data), - ('PADDING_0', ctypes.c_ubyte * 496), + ('user_marker_profiling_data', union_sqtt_profiling_mode_data_user_marker_profiling_data), + ('index_profiling_data', union_sqtt_profiling_mode_data_index_profiling_data), + ('tag_profiling_data', union_sqtt_profiling_mode_data_tag_profiling_data), ] - -class union_sqtt_instruction_trace_data(Union): - pass - -class struct_sqtt_instruction_trace_data_api_pso_data(Structure): - pass - -struct_sqtt_instruction_trace_data_api_pso_data._pack_ = 1 # source:False -struct_sqtt_instruction_trace_data_api_pso_data._fields_ = [ - ('api_pso_filter', ctypes.c_uint64), +class union_sqtt_instruction_trace_data(ctypes.Union): pass +class union_sqtt_instruction_trace_data_api_pso_data(Struct): pass +union_sqtt_instruction_trace_data_api_pso_data._fields_ = [ + ('api_pso_filter', uint64_t), ] - -class struct_sqtt_instruction_trace_data_shader_engine_filter(Structure): - pass - -struct_sqtt_instruction_trace_data_shader_engine_filter._pack_ = 1 # source:False -struct_sqtt_instruction_trace_data_shader_engine_filter._fields_ = [ - ('mask', ctypes.c_uint32), +class union_sqtt_instruction_trace_data_shader_engine_filter(Struct): pass +union_sqtt_instruction_trace_data_shader_engine_filter._fields_ = [ + ('mask', uint32_t), ] - -union_sqtt_instruction_trace_data._pack_ = 1 # source:False union_sqtt_instruction_trace_data._fields_ = [ - ('api_pso_data', struct_sqtt_instruction_trace_data_api_pso_data), - ('shader_engine_filter', struct_sqtt_instruction_trace_data_shader_engine_filter), - ('PADDING_0', ctypes.c_ubyte * 4), + ('api_pso_data', union_sqtt_instruction_trace_data_api_pso_data), + ('shader_engine_filter', union_sqtt_instruction_trace_data_shader_engine_filter), ] - -class struct_sqtt_file_chunk_api_info(Structure): - pass - -struct_sqtt_file_chunk_api_info._pack_ = 1 # source:False +class struct_sqtt_file_chunk_api_info(Struct): pass struct_sqtt_file_chunk_api_info._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('api_type', sqtt_api_type), - ('major_version', ctypes.c_uint16), - ('minor_version', ctypes.c_uint16), - ('profiling_mode', sqtt_profiling_mode), - ('reserved', ctypes.c_uint32), - ('profiling_mode_data', union_sqtt_profiling_mode_data), - ('instruction_trace_mode', sqtt_instruction_trace_mode), - ('reserved2', ctypes.c_uint32), - ('instruction_trace_data', union_sqtt_instruction_trace_data), + ('header', struct_sqtt_file_chunk_header), + ('api_type', enum_sqtt_api_type), + ('major_version', uint16_t), + ('minor_version', uint16_t), + ('profiling_mode', enum_sqtt_profiling_mode), + ('reserved', uint32_t), + ('profiling_mode_data', union_sqtt_profiling_mode_data), + ('instruction_trace_mode', enum_sqtt_instruction_trace_mode), + ('reserved2', uint32_t), + ('instruction_trace_data', union_sqtt_instruction_trace_data), ] - -class struct_sqtt_code_object_database_record(Structure): - pass - -struct_sqtt_code_object_database_record._pack_ = 1 # source:False +class struct_sqtt_code_object_database_record(Struct): pass struct_sqtt_code_object_database_record._fields_ = [ - ('size', ctypes.c_uint32), + ('size', uint32_t), ] - -class struct_sqtt_file_chunk_code_object_database(Structure): - pass - -struct_sqtt_file_chunk_code_object_database._pack_ = 1 # source:False +class struct_sqtt_file_chunk_code_object_database(Struct): pass struct_sqtt_file_chunk_code_object_database._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('record_count', ctypes.c_uint32), + ('header', struct_sqtt_file_chunk_header), + ('offset', uint32_t), + ('flags', uint32_t), + ('size', uint32_t), + ('record_count', uint32_t), ] - -class struct_sqtt_code_object_loader_events_record(Structure): - pass - -struct_sqtt_code_object_loader_events_record._pack_ = 1 # source:False +class struct_sqtt_code_object_loader_events_record(Struct): pass struct_sqtt_code_object_loader_events_record._fields_ = [ - ('loader_event_type', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('base_address', ctypes.c_uint64), - ('code_object_hash', ctypes.c_uint64 * 2), - ('time_stamp', ctypes.c_uint64), + ('loader_event_type', uint32_t), + ('reserved', uint32_t), + ('base_address', uint64_t), + ('code_object_hash', (uint64_t * 2)), + ('time_stamp', uint64_t), ] - -class struct_sqtt_file_chunk_code_object_loader_events(Structure): - pass - -struct_sqtt_file_chunk_code_object_loader_events._pack_ = 1 # source:False +class struct_sqtt_file_chunk_code_object_loader_events(Struct): pass struct_sqtt_file_chunk_code_object_loader_events._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('record_size', ctypes.c_uint32), - ('record_count', ctypes.c_uint32), + ('header', struct_sqtt_file_chunk_header), + ('offset', uint32_t), + ('flags', uint32_t), + ('record_size', uint32_t), + ('record_count', uint32_t), ] - -class struct_sqtt_pso_correlation_record(Structure): - pass - -struct_sqtt_pso_correlation_record._pack_ = 1 # source:False +class struct_sqtt_pso_correlation_record(Struct): pass struct_sqtt_pso_correlation_record._fields_ = [ - ('api_pso_hash', ctypes.c_uint64), - ('pipeline_hash', ctypes.c_uint64 * 2), - ('api_level_obj_name', ctypes.c_char * 64), + ('api_pso_hash', uint64_t), + ('pipeline_hash', (uint64_t * 2)), + ('api_level_obj_name', (ctypes.c_char * 64)), ] - -class struct_sqtt_file_chunk_pso_correlation(Structure): - pass - -struct_sqtt_file_chunk_pso_correlation._pack_ = 1 # source:False +class struct_sqtt_file_chunk_pso_correlation(Struct): pass struct_sqtt_file_chunk_pso_correlation._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('record_size', ctypes.c_uint32), - ('record_count', ctypes.c_uint32), + ('header', struct_sqtt_file_chunk_header), + ('offset', uint32_t), + ('flags', uint32_t), + ('record_size', uint32_t), + ('record_count', uint32_t), ] - -class struct_sqtt_file_chunk_sqtt_desc(Structure): - pass - -class union_sqtt_file_chunk_sqtt_desc_0(Union): - pass - -class struct_sqtt_file_chunk_sqtt_desc_0_v0(Structure): - pass - -struct_sqtt_file_chunk_sqtt_desc_0_v0._pack_ = 1 # source:False +class struct_sqtt_file_chunk_sqtt_desc(Struct): pass +class struct_sqtt_file_chunk_sqtt_desc_0(ctypes.Union): pass +class struct_sqtt_file_chunk_sqtt_desc_0_v0(Struct): pass struct_sqtt_file_chunk_sqtt_desc_0_v0._fields_ = [ - ('instrumentation_version', ctypes.c_int32), + ('instrumentation_version', int32_t), ] - -class struct_sqtt_file_chunk_sqtt_desc_0_v1(Structure): - pass - -struct_sqtt_file_chunk_sqtt_desc_0_v1._pack_ = 1 # source:False +class struct_sqtt_file_chunk_sqtt_desc_0_v1(Struct): pass +int16_t = ctypes.c_int16 struct_sqtt_file_chunk_sqtt_desc_0_v1._fields_ = [ - ('instrumentation_spec_version', ctypes.c_int16), - ('instrumentation_api_version', ctypes.c_int16), - ('compute_unit_index', ctypes.c_int32), + ('instrumentation_spec_version', int16_t), + ('instrumentation_api_version', int16_t), + ('compute_unit_index', int32_t), ] - -union_sqtt_file_chunk_sqtt_desc_0._pack_ = 1 # source:False -union_sqtt_file_chunk_sqtt_desc_0._fields_ = [ - ('v0', struct_sqtt_file_chunk_sqtt_desc_0_v0), - ('v1', struct_sqtt_file_chunk_sqtt_desc_0_v1), +struct_sqtt_file_chunk_sqtt_desc_0._fields_ = [ + ('v0', struct_sqtt_file_chunk_sqtt_desc_0_v0), + ('v1', struct_sqtt_file_chunk_sqtt_desc_0_v1), ] - -struct_sqtt_file_chunk_sqtt_desc._pack_ = 1 # source:False -struct_sqtt_file_chunk_sqtt_desc._anonymous_ = ('_0',) +struct_sqtt_file_chunk_sqtt_desc._anonymous_ = ['_0'] struct_sqtt_file_chunk_sqtt_desc._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('shader_engine_index', ctypes.c_int32), - ('sqtt_version', sqtt_version), - ('_0', union_sqtt_file_chunk_sqtt_desc_0), + ('header', struct_sqtt_file_chunk_header), + ('shader_engine_index', int32_t), + ('sqtt_version', enum_sqtt_version), + ('_0', struct_sqtt_file_chunk_sqtt_desc_0), ] - -class struct_sqtt_file_chunk_sqtt_data(Structure): - pass - -struct_sqtt_file_chunk_sqtt_data._pack_ = 1 # source:False +class struct_sqtt_file_chunk_sqtt_data(Struct): pass struct_sqtt_file_chunk_sqtt_data._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('offset', ctypes.c_int32), - ('size', ctypes.c_int32), + ('header', struct_sqtt_file_chunk_header), + ('offset', int32_t), + ('size', int32_t), ] - -class struct_sqtt_file_chunk_queue_event_timings(Structure): - pass - -struct_sqtt_file_chunk_queue_event_timings._pack_ = 1 # source:False +class struct_sqtt_file_chunk_queue_event_timings(Struct): pass struct_sqtt_file_chunk_queue_event_timings._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('queue_info_table_record_count', ctypes.c_uint32), - ('queue_info_table_size', ctypes.c_uint32), - ('queue_event_table_record_count', ctypes.c_uint32), - ('queue_event_table_size', ctypes.c_uint32), + ('header', struct_sqtt_file_chunk_header), + ('queue_info_table_record_count', uint32_t), + ('queue_info_table_size', uint32_t), + ('queue_event_table_record_count', uint32_t), + ('queue_event_table_size', uint32_t), ] +enum_sqtt_queue_type = CEnum(ctypes.c_uint32) +SQTT_QUEUE_TYPE_UNKNOWN = enum_sqtt_queue_type.define('SQTT_QUEUE_TYPE_UNKNOWN', 0) +SQTT_QUEUE_TYPE_UNIVERSAL = enum_sqtt_queue_type.define('SQTT_QUEUE_TYPE_UNIVERSAL', 1) +SQTT_QUEUE_TYPE_COMPUTE = enum_sqtt_queue_type.define('SQTT_QUEUE_TYPE_COMPUTE', 2) +SQTT_QUEUE_TYPE_DMA = enum_sqtt_queue_type.define('SQTT_QUEUE_TYPE_DMA', 3) +enum_sqtt_engine_type = CEnum(ctypes.c_uint32) +SQTT_ENGINE_TYPE_UNKNOWN = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_UNKNOWN', 0) +SQTT_ENGINE_TYPE_UNIVERSAL = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_UNIVERSAL', 1) +SQTT_ENGINE_TYPE_COMPUTE = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_COMPUTE', 2) +SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE', 3) +SQTT_ENGINE_TYPE_DMA = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_DMA', 4) +SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL', 7) +SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS = enum_sqtt_engine_type.define('SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS', 8) -# values for enumeration 'sqtt_queue_type' -sqtt_queue_type__enumvalues = { - 0: 'SQTT_QUEUE_TYPE_UNKNOWN', - 1: 'SQTT_QUEUE_TYPE_UNIVERSAL', - 2: 'SQTT_QUEUE_TYPE_COMPUTE', - 3: 'SQTT_QUEUE_TYPE_DMA', -} -SQTT_QUEUE_TYPE_UNKNOWN = 0 -SQTT_QUEUE_TYPE_UNIVERSAL = 1 -SQTT_QUEUE_TYPE_COMPUTE = 2 -SQTT_QUEUE_TYPE_DMA = 3 -sqtt_queue_type = ctypes.c_uint32 # enum - -# values for enumeration 'sqtt_engine_type' -sqtt_engine_type__enumvalues = { - 0: 'SQTT_ENGINE_TYPE_UNKNOWN', - 1: 'SQTT_ENGINE_TYPE_UNIVERSAL', - 2: 'SQTT_ENGINE_TYPE_COMPUTE', - 3: 'SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE', - 4: 'SQTT_ENGINE_TYPE_DMA', - 7: 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL', - 8: 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS', -} -SQTT_ENGINE_TYPE_UNKNOWN = 0 -SQTT_ENGINE_TYPE_UNIVERSAL = 1 -SQTT_ENGINE_TYPE_COMPUTE = 2 -SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE = 3 -SQTT_ENGINE_TYPE_DMA = 4 -SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL = 7 -SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS = 8 -sqtt_engine_type = ctypes.c_uint32 # enum -class struct_sqtt_queue_hardware_info(Structure): - pass - -class union_sqtt_queue_hardware_info_0(Union): - pass - -class struct_sqtt_queue_hardware_info_0_0(Structure): - pass - -struct_sqtt_queue_hardware_info_0_0._pack_ = 1 # source:False +class struct_sqtt_queue_hardware_info(Struct): pass +class struct_sqtt_queue_hardware_info_0(ctypes.Union): pass +class struct_sqtt_queue_hardware_info_0_0(Struct): pass struct_sqtt_queue_hardware_info_0_0._fields_ = [ - ('queue_type', ctypes.c_int32, 8), - ('engine_type', ctypes.c_int32, 8), - ('reserved', ctypes.c_int32, 16), + ('queue_type', int32_t,8), + ('engine_type', int32_t,8), + ('reserved', uint32_t,16), ] - -union_sqtt_queue_hardware_info_0._pack_ = 1 # source:False -union_sqtt_queue_hardware_info_0._anonymous_ = ('_0',) -union_sqtt_queue_hardware_info_0._fields_ = [ - ('_0', struct_sqtt_queue_hardware_info_0_0), - ('value', ctypes.c_uint32), +struct_sqtt_queue_hardware_info_0._anonymous_ = ['_0'] +struct_sqtt_queue_hardware_info_0._fields_ = [ + ('_0', struct_sqtt_queue_hardware_info_0_0), + ('value', uint32_t), ] - -struct_sqtt_queue_hardware_info._pack_ = 1 # source:False -struct_sqtt_queue_hardware_info._anonymous_ = ('_0',) +struct_sqtt_queue_hardware_info._anonymous_ = ['_0'] struct_sqtt_queue_hardware_info._fields_ = [ - ('_0', union_sqtt_queue_hardware_info_0), + ('_0', struct_sqtt_queue_hardware_info_0), ] - -class struct_sqtt_queue_info_record(Structure): - pass - -struct_sqtt_queue_info_record._pack_ = 1 # source:False +class struct_sqtt_queue_info_record(Struct): pass struct_sqtt_queue_info_record._fields_ = [ - ('queue_id', ctypes.c_uint64), - ('queue_context', ctypes.c_uint64), - ('hardware_info', struct_sqtt_queue_hardware_info), - ('reserved', ctypes.c_uint32), + ('queue_id', uint64_t), + ('queue_context', uint64_t), + ('hardware_info', struct_sqtt_queue_hardware_info), + ('reserved', uint32_t), ] +enum_sqtt_queue_event_type = CEnum(ctypes.c_uint32) +SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT = enum_sqtt_queue_event_type.define('SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT', 0) +SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE = enum_sqtt_queue_event_type.define('SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE', 1) +SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE = enum_sqtt_queue_event_type.define('SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE', 2) +SQTT_QUEUE_TIMING_EVENT_PRESENT = enum_sqtt_queue_event_type.define('SQTT_QUEUE_TIMING_EVENT_PRESENT', 3) - -# values for enumeration 'sqtt_queue_event_type' -sqtt_queue_event_type__enumvalues = { - 0: 'SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT', - 1: 'SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE', - 2: 'SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE', - 3: 'SQTT_QUEUE_TIMING_EVENT_PRESENT', -} -SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT = 0 -SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE = 1 -SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE = 2 -SQTT_QUEUE_TIMING_EVENT_PRESENT = 3 -sqtt_queue_event_type = ctypes.c_uint32 # enum -class struct_sqtt_queue_event_record(Structure): - pass - -struct_sqtt_queue_event_record._pack_ = 1 # source:False +class struct_sqtt_queue_event_record(Struct): pass struct_sqtt_queue_event_record._fields_ = [ - ('event_type', sqtt_queue_event_type), - ('sqtt_cb_id', ctypes.c_uint32), - ('frame_index', ctypes.c_uint64), - ('queue_info_index', ctypes.c_uint32), - ('submit_sub_index', ctypes.c_uint32), - ('api_id', ctypes.c_uint64), - ('cpu_timestamp', ctypes.c_uint64), - ('gpu_timestamps', ctypes.c_uint64 * 2), + ('event_type', enum_sqtt_queue_event_type), + ('sqtt_cb_id', uint32_t), + ('frame_index', uint64_t), + ('queue_info_index', uint32_t), + ('submit_sub_index', uint32_t), + ('api_id', uint64_t), + ('cpu_timestamp', uint64_t), + ('gpu_timestamps', (uint64_t * 2)), ] - -class struct_sqtt_file_chunk_clock_calibration(Structure): - pass - -struct_sqtt_file_chunk_clock_calibration._pack_ = 1 # source:False +class struct_sqtt_file_chunk_clock_calibration(Struct): pass struct_sqtt_file_chunk_clock_calibration._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('cpu_timestamp', ctypes.c_uint64), - ('gpu_timestamp', ctypes.c_uint64), - ('reserved', ctypes.c_uint64), + ('header', struct_sqtt_file_chunk_header), + ('cpu_timestamp', uint64_t), + ('gpu_timestamp', uint64_t), + ('reserved', uint64_t), ] +enum_elf_gfxip_level = CEnum(ctypes.c_uint32) +EF_AMDGPU_MACH_AMDGCN_GFX801 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX801', 40) +EF_AMDGPU_MACH_AMDGCN_GFX900 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX900', 44) +EF_AMDGPU_MACH_AMDGCN_GFX1010 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX1010', 51) +EF_AMDGPU_MACH_AMDGCN_GFX1030 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX1030', 54) +EF_AMDGPU_MACH_AMDGCN_GFX1100 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX1100', 65) +EF_AMDGPU_MACH_AMDGCN_GFX1150 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX1150', 67) +EF_AMDGPU_MACH_AMDGCN_GFX1200 = enum_elf_gfxip_level.define('EF_AMDGPU_MACH_AMDGCN_GFX1200', 78) - -# values for enumeration 'elf_gfxip_level' -elf_gfxip_level__enumvalues = { - 40: 'EF_AMDGPU_MACH_AMDGCN_GFX801', - 44: 'EF_AMDGPU_MACH_AMDGCN_GFX900', - 51: 'EF_AMDGPU_MACH_AMDGCN_GFX1010', - 54: 'EF_AMDGPU_MACH_AMDGCN_GFX1030', - 65: 'EF_AMDGPU_MACH_AMDGCN_GFX1100', - 67: 'EF_AMDGPU_MACH_AMDGCN_GFX1150', - 78: 'EF_AMDGPU_MACH_AMDGCN_GFX1200', -} -EF_AMDGPU_MACH_AMDGCN_GFX801 = 40 -EF_AMDGPU_MACH_AMDGCN_GFX900 = 44 -EF_AMDGPU_MACH_AMDGCN_GFX1010 = 51 -EF_AMDGPU_MACH_AMDGCN_GFX1030 = 54 -EF_AMDGPU_MACH_AMDGCN_GFX1100 = 65 -EF_AMDGPU_MACH_AMDGCN_GFX1150 = 67 -EF_AMDGPU_MACH_AMDGCN_GFX1200 = 78 -elf_gfxip_level = ctypes.c_uint32 # enum -class struct_sqtt_file_chunk_spm_db(Structure): - pass - -struct_sqtt_file_chunk_spm_db._pack_ = 1 # source:False +class struct_sqtt_file_chunk_spm_db(Struct): pass struct_sqtt_file_chunk_spm_db._fields_ = [ - ('header', struct_sqtt_file_chunk_header), - ('flags', ctypes.c_uint32), - ('preamble_size', ctypes.c_uint32), - ('num_timestamps', ctypes.c_uint32), - ('num_spm_counter_info', ctypes.c_uint32), - ('spm_counter_info_size', ctypes.c_uint32), - ('sample_interval', ctypes.c_uint32), + ('header', struct_sqtt_file_chunk_header), + ('flags', uint32_t), + ('preamble_size', uint32_t), + ('num_timestamps', uint32_t), + ('num_spm_counter_info', uint32_t), + ('spm_counter_info_size', uint32_t), + ('sample_interval', uint32_t), ] +enum_rgp_sqtt_marker_identifier = CEnum(ctypes.c_uint32) +RGP_SQTT_MARKER_IDENTIFIER_EVENT = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_EVENT', 0) +RGP_SQTT_MARKER_IDENTIFIER_CB_START = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_CB_START', 1) +RGP_SQTT_MARKER_IDENTIFIER_CB_END = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_CB_END', 2) +RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START', 3) +RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END', 4) +RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT', 5) +RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API', 6) +RGP_SQTT_MARKER_IDENTIFIER_SYNC = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_SYNC', 7) +RGP_SQTT_MARKER_IDENTIFIER_PRESENT = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_PRESENT', 8) +RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION', 9) +RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS', 10) +RGP_SQTT_MARKER_IDENTIFIER_RESERVED2 = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_RESERVED2', 11) +RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE', 12) +RGP_SQTT_MARKER_IDENTIFIER_RESERVED4 = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_RESERVED4', 13) +RGP_SQTT_MARKER_IDENTIFIER_RESERVED5 = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_RESERVED5', 14) +RGP_SQTT_MARKER_IDENTIFIER_RESERVED6 = enum_rgp_sqtt_marker_identifier.define('RGP_SQTT_MARKER_IDENTIFIER_RESERVED6', 15) - -# values for enumeration 'rgp_sqtt_marker_identifier' -rgp_sqtt_marker_identifier__enumvalues = { - 0: 'RGP_SQTT_MARKER_IDENTIFIER_EVENT', - 1: 'RGP_SQTT_MARKER_IDENTIFIER_CB_START', - 2: 'RGP_SQTT_MARKER_IDENTIFIER_CB_END', - 3: 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START', - 4: 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END', - 5: 'RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT', - 6: 'RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API', - 7: 'RGP_SQTT_MARKER_IDENTIFIER_SYNC', - 8: 'RGP_SQTT_MARKER_IDENTIFIER_PRESENT', - 9: 'RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION', - 10: 'RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS', - 11: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED2', - 12: 'RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE', - 13: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED4', - 14: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED5', - 15: 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED6', -} -RGP_SQTT_MARKER_IDENTIFIER_EVENT = 0 -RGP_SQTT_MARKER_IDENTIFIER_CB_START = 1 -RGP_SQTT_MARKER_IDENTIFIER_CB_END = 2 -RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START = 3 -RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END = 4 -RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT = 5 -RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API = 6 -RGP_SQTT_MARKER_IDENTIFIER_SYNC = 7 -RGP_SQTT_MARKER_IDENTIFIER_PRESENT = 8 -RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION = 9 -RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS = 10 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED2 = 11 -RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE = 12 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED4 = 13 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED5 = 14 -RGP_SQTT_MARKER_IDENTIFIER_RESERVED6 = 15 -rgp_sqtt_marker_identifier = ctypes.c_uint32 # enum -class union_rgp_sqtt_marker_cb_id(Union): - pass - -class struct_rgp_sqtt_marker_cb_id_per_frame_cb_id(Structure): - pass - -struct_rgp_sqtt_marker_cb_id_per_frame_cb_id._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_id_per_frame_cb_id._fields_ = [ - ('per_frame', ctypes.c_uint32, 1), - ('frame_index', ctypes.c_uint32, 7), - ('cb_index', ctypes.c_uint32, 12), - ('reserved', ctypes.c_uint32, 12), +class union_rgp_sqtt_marker_cb_id(ctypes.Union): pass +class union_rgp_sqtt_marker_cb_id_per_frame_cb_id(Struct): pass +union_rgp_sqtt_marker_cb_id_per_frame_cb_id._fields_ = [ + ('per_frame', uint32_t,1), + ('frame_index', uint32_t,7), + ('cb_index', uint32_t,12), + ('reserved', uint32_t,12), ] - -class struct_rgp_sqtt_marker_cb_id_global_cb_id(Structure): - pass - -struct_rgp_sqtt_marker_cb_id_global_cb_id._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_id_global_cb_id._fields_ = [ - ('per_frame', ctypes.c_uint32, 1), - ('cb_index', ctypes.c_uint32, 19), - ('reserved', ctypes.c_uint32, 12), +class union_rgp_sqtt_marker_cb_id_global_cb_id(Struct): pass +union_rgp_sqtt_marker_cb_id_global_cb_id._fields_ = [ + ('per_frame', uint32_t,1), + ('cb_index', uint32_t,19), + ('reserved', uint32_t,12), ] - -union_rgp_sqtt_marker_cb_id._pack_ = 1 # source:False union_rgp_sqtt_marker_cb_id._fields_ = [ - ('per_frame_cb_id', struct_rgp_sqtt_marker_cb_id_per_frame_cb_id), - ('global_cb_id', struct_rgp_sqtt_marker_cb_id_global_cb_id), - ('all', ctypes.c_uint32), + ('per_frame_cb_id', union_rgp_sqtt_marker_cb_id_per_frame_cb_id), + ('global_cb_id', union_rgp_sqtt_marker_cb_id_global_cb_id), + ('all', uint32_t), ] - -class struct_rgp_sqtt_marker_cb_start(Structure): - pass - -class union_rgp_sqtt_marker_cb_start_0(Union): - pass - -class struct_rgp_sqtt_marker_cb_start_0_0(Structure): - pass - -struct_rgp_sqtt_marker_cb_start_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_cb_start(Struct): pass +class struct_rgp_sqtt_marker_cb_start_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_cb_start_0_0(Struct): pass struct_rgp_sqtt_marker_cb_start_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('queue', ctypes.c_uint32, 5), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('cb_id', uint32_t,20), + ('queue', uint32_t,5), ] - -union_rgp_sqtt_marker_cb_start_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_cb_start_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_cb_start_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_cb_start_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_cb_start_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_cb_start_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_cb_start_1(Union): - pass - -union_rgp_sqtt_marker_cb_start_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_1._fields_ = [ - ('device_id_low', ctypes.c_uint32), - ('dword02', ctypes.c_uint32), +class struct_rgp_sqtt_marker_cb_start_1(ctypes.Union): pass +struct_rgp_sqtt_marker_cb_start_1._fields_ = [ + ('device_id_low', uint32_t), + ('dword02', uint32_t), ] - -class union_rgp_sqtt_marker_cb_start_2(Union): - pass - -union_rgp_sqtt_marker_cb_start_2._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_2._fields_ = [ - ('device_id_high', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), +class struct_rgp_sqtt_marker_cb_start_2(ctypes.Union): pass +struct_rgp_sqtt_marker_cb_start_2._fields_ = [ + ('device_id_high', uint32_t), + ('dword03', uint32_t), ] - -class union_rgp_sqtt_marker_cb_start_3(Union): - pass - -union_rgp_sqtt_marker_cb_start_3._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_start_3._fields_ = [ - ('queue_flags', ctypes.c_uint32), - ('dword04', ctypes.c_uint32), +class struct_rgp_sqtt_marker_cb_start_3(ctypes.Union): pass +struct_rgp_sqtt_marker_cb_start_3._fields_ = [ + ('queue_flags', uint32_t), + ('dword04', uint32_t), ] - -struct_rgp_sqtt_marker_cb_start._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_start._anonymous_ = ('_0', '_1', '_2', '_3',) +struct_rgp_sqtt_marker_cb_start._anonymous_ = ['_0', '_1', '_2', '_3'] struct_rgp_sqtt_marker_cb_start._fields_ = [ - ('_0', union_rgp_sqtt_marker_cb_start_0), - ('_1', union_rgp_sqtt_marker_cb_start_1), - ('_2', union_rgp_sqtt_marker_cb_start_2), - ('_3', union_rgp_sqtt_marker_cb_start_3), + ('_0', struct_rgp_sqtt_marker_cb_start_0), + ('_1', struct_rgp_sqtt_marker_cb_start_1), + ('_2', struct_rgp_sqtt_marker_cb_start_2), + ('_3', struct_rgp_sqtt_marker_cb_start_3), ] - -class struct_rgp_sqtt_marker_cb_end(Structure): - pass - -class union_rgp_sqtt_marker_cb_end_0(Union): - pass - -class struct_rgp_sqtt_marker_cb_end_0_0(Structure): - pass - -struct_rgp_sqtt_marker_cb_end_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_cb_end(Struct): pass +class struct_rgp_sqtt_marker_cb_end_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_cb_end_0_0(Struct): pass struct_rgp_sqtt_marker_cb_end_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('reserved', ctypes.c_uint32, 5), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('cb_id', uint32_t,20), + ('reserved', uint32_t,5), ] - -union_rgp_sqtt_marker_cb_end_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_end_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_cb_end_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_cb_end_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_cb_end_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_cb_end_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_cb_end_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_cb_end_1(Union): - pass - -union_rgp_sqtt_marker_cb_end_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_end_1._fields_ = [ - ('device_id_low', ctypes.c_uint32), - ('dword02', ctypes.c_uint32), +class struct_rgp_sqtt_marker_cb_end_1(ctypes.Union): pass +struct_rgp_sqtt_marker_cb_end_1._fields_ = [ + ('device_id_low', uint32_t), + ('dword02', uint32_t), ] - -class union_rgp_sqtt_marker_cb_end_2(Union): - pass - -union_rgp_sqtt_marker_cb_end_2._pack_ = 1 # source:False -union_rgp_sqtt_marker_cb_end_2._fields_ = [ - ('device_id_high', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), +class struct_rgp_sqtt_marker_cb_end_2(ctypes.Union): pass +struct_rgp_sqtt_marker_cb_end_2._fields_ = [ + ('device_id_high', uint32_t), + ('dword03', uint32_t), ] - -struct_rgp_sqtt_marker_cb_end._pack_ = 1 # source:False -struct_rgp_sqtt_marker_cb_end._anonymous_ = ('_0', '_1', '_2',) +struct_rgp_sqtt_marker_cb_end._anonymous_ = ['_0', '_1', '_2'] struct_rgp_sqtt_marker_cb_end._fields_ = [ - ('_0', union_rgp_sqtt_marker_cb_end_0), - ('_1', union_rgp_sqtt_marker_cb_end_1), - ('_2', union_rgp_sqtt_marker_cb_end_2), + ('_0', struct_rgp_sqtt_marker_cb_end_0), + ('_1', struct_rgp_sqtt_marker_cb_end_1), + ('_2', struct_rgp_sqtt_marker_cb_end_2), ] +enum_rgp_sqtt_marker_general_api_type = CEnum(ctypes.c_uint32) +ApiCmdBindPipeline = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBindPipeline', 0) +ApiCmdBindDescriptorSets = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBindDescriptorSets', 1) +ApiCmdBindIndexBuffer = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBindIndexBuffer', 2) +ApiCmdBindVertexBuffers = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBindVertexBuffers', 3) +ApiCmdDraw = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDraw', 4) +ApiCmdDrawIndexed = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndexed', 5) +ApiCmdDrawIndirect = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndirect', 6) +ApiCmdDrawIndexedIndirect = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndexedIndirect', 7) +ApiCmdDrawIndirectCountAMD = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndirectCountAMD', 8) +ApiCmdDrawIndexedIndirectCountAMD = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndexedIndirectCountAMD', 9) +ApiCmdDispatch = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDispatch', 10) +ApiCmdDispatchIndirect = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDispatchIndirect', 11) +ApiCmdCopyBuffer = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdCopyBuffer', 12) +ApiCmdCopyImage = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdCopyImage', 13) +ApiCmdBlitImage = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBlitImage', 14) +ApiCmdCopyBufferToImage = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdCopyBufferToImage', 15) +ApiCmdCopyImageToBuffer = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdCopyImageToBuffer', 16) +ApiCmdUpdateBuffer = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdUpdateBuffer', 17) +ApiCmdFillBuffer = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdFillBuffer', 18) +ApiCmdClearColorImage = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdClearColorImage', 19) +ApiCmdClearDepthStencilImage = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdClearDepthStencilImage', 20) +ApiCmdClearAttachments = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdClearAttachments', 21) +ApiCmdResolveImage = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdResolveImage', 22) +ApiCmdWaitEvents = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdWaitEvents', 23) +ApiCmdPipelineBarrier = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdPipelineBarrier', 24) +ApiCmdBeginQuery = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBeginQuery', 25) +ApiCmdEndQuery = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdEndQuery', 26) +ApiCmdResetQueryPool = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdResetQueryPool', 27) +ApiCmdWriteTimestamp = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdWriteTimestamp', 28) +ApiCmdCopyQueryPoolResults = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdCopyQueryPoolResults', 29) +ApiCmdPushConstants = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdPushConstants', 30) +ApiCmdBeginRenderPass = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdBeginRenderPass', 31) +ApiCmdNextSubpass = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdNextSubpass', 32) +ApiCmdEndRenderPass = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdEndRenderPass', 33) +ApiCmdExecuteCommands = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdExecuteCommands', 34) +ApiCmdSetViewport = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetViewport', 35) +ApiCmdSetScissor = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetScissor', 36) +ApiCmdSetLineWidth = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetLineWidth', 37) +ApiCmdSetDepthBias = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetDepthBias', 38) +ApiCmdSetBlendConstants = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetBlendConstants', 39) +ApiCmdSetDepthBounds = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetDepthBounds', 40) +ApiCmdSetStencilCompareMask = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetStencilCompareMask', 41) +ApiCmdSetStencilWriteMask = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetStencilWriteMask', 42) +ApiCmdSetStencilReference = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdSetStencilReference', 43) +ApiCmdDrawIndirectCount = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndirectCount', 44) +ApiCmdDrawIndexedIndirectCount = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawIndexedIndirectCount', 45) +ApiCmdDrawMeshTasksEXT = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawMeshTasksEXT', 47) +ApiCmdDrawMeshTasksIndirectCountEXT = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawMeshTasksIndirectCountEXT', 48) +ApiCmdDrawMeshTasksIndirectEXT = enum_rgp_sqtt_marker_general_api_type.define('ApiCmdDrawMeshTasksIndirectEXT', 49) +ApiRayTracingSeparateCompiled = enum_rgp_sqtt_marker_general_api_type.define('ApiRayTracingSeparateCompiled', 8388608) +ApiInvalid = enum_rgp_sqtt_marker_general_api_type.define('ApiInvalid', 4294967295) - -# values for enumeration 'rgp_sqtt_marker_general_api_type' -rgp_sqtt_marker_general_api_type__enumvalues = { - 0: 'ApiCmdBindPipeline', - 1: 'ApiCmdBindDescriptorSets', - 2: 'ApiCmdBindIndexBuffer', - 3: 'ApiCmdBindVertexBuffers', - 4: 'ApiCmdDraw', - 5: 'ApiCmdDrawIndexed', - 6: 'ApiCmdDrawIndirect', - 7: 'ApiCmdDrawIndexedIndirect', - 8: 'ApiCmdDrawIndirectCountAMD', - 9: 'ApiCmdDrawIndexedIndirectCountAMD', - 10: 'ApiCmdDispatch', - 11: 'ApiCmdDispatchIndirect', - 12: 'ApiCmdCopyBuffer', - 13: 'ApiCmdCopyImage', - 14: 'ApiCmdBlitImage', - 15: 'ApiCmdCopyBufferToImage', - 16: 'ApiCmdCopyImageToBuffer', - 17: 'ApiCmdUpdateBuffer', - 18: 'ApiCmdFillBuffer', - 19: 'ApiCmdClearColorImage', - 20: 'ApiCmdClearDepthStencilImage', - 21: 'ApiCmdClearAttachments', - 22: 'ApiCmdResolveImage', - 23: 'ApiCmdWaitEvents', - 24: 'ApiCmdPipelineBarrier', - 25: 'ApiCmdBeginQuery', - 26: 'ApiCmdEndQuery', - 27: 'ApiCmdResetQueryPool', - 28: 'ApiCmdWriteTimestamp', - 29: 'ApiCmdCopyQueryPoolResults', - 30: 'ApiCmdPushConstants', - 31: 'ApiCmdBeginRenderPass', - 32: 'ApiCmdNextSubpass', - 33: 'ApiCmdEndRenderPass', - 34: 'ApiCmdExecuteCommands', - 35: 'ApiCmdSetViewport', - 36: 'ApiCmdSetScissor', - 37: 'ApiCmdSetLineWidth', - 38: 'ApiCmdSetDepthBias', - 39: 'ApiCmdSetBlendConstants', - 40: 'ApiCmdSetDepthBounds', - 41: 'ApiCmdSetStencilCompareMask', - 42: 'ApiCmdSetStencilWriteMask', - 43: 'ApiCmdSetStencilReference', - 44: 'ApiCmdDrawIndirectCount', - 45: 'ApiCmdDrawIndexedIndirectCount', - 47: 'ApiCmdDrawMeshTasksEXT', - 48: 'ApiCmdDrawMeshTasksIndirectCountEXT', - 49: 'ApiCmdDrawMeshTasksIndirectEXT', - 8388608: 'ApiRayTracingSeparateCompiled', - 4294967295: 'ApiInvalid', -} -ApiCmdBindPipeline = 0 -ApiCmdBindDescriptorSets = 1 -ApiCmdBindIndexBuffer = 2 -ApiCmdBindVertexBuffers = 3 -ApiCmdDraw = 4 -ApiCmdDrawIndexed = 5 -ApiCmdDrawIndirect = 6 -ApiCmdDrawIndexedIndirect = 7 -ApiCmdDrawIndirectCountAMD = 8 -ApiCmdDrawIndexedIndirectCountAMD = 9 -ApiCmdDispatch = 10 -ApiCmdDispatchIndirect = 11 -ApiCmdCopyBuffer = 12 -ApiCmdCopyImage = 13 -ApiCmdBlitImage = 14 -ApiCmdCopyBufferToImage = 15 -ApiCmdCopyImageToBuffer = 16 -ApiCmdUpdateBuffer = 17 -ApiCmdFillBuffer = 18 -ApiCmdClearColorImage = 19 -ApiCmdClearDepthStencilImage = 20 -ApiCmdClearAttachments = 21 -ApiCmdResolveImage = 22 -ApiCmdWaitEvents = 23 -ApiCmdPipelineBarrier = 24 -ApiCmdBeginQuery = 25 -ApiCmdEndQuery = 26 -ApiCmdResetQueryPool = 27 -ApiCmdWriteTimestamp = 28 -ApiCmdCopyQueryPoolResults = 29 -ApiCmdPushConstants = 30 -ApiCmdBeginRenderPass = 31 -ApiCmdNextSubpass = 32 -ApiCmdEndRenderPass = 33 -ApiCmdExecuteCommands = 34 -ApiCmdSetViewport = 35 -ApiCmdSetScissor = 36 -ApiCmdSetLineWidth = 37 -ApiCmdSetDepthBias = 38 -ApiCmdSetBlendConstants = 39 -ApiCmdSetDepthBounds = 40 -ApiCmdSetStencilCompareMask = 41 -ApiCmdSetStencilWriteMask = 42 -ApiCmdSetStencilReference = 43 -ApiCmdDrawIndirectCount = 44 -ApiCmdDrawIndexedIndirectCount = 45 -ApiCmdDrawMeshTasksEXT = 47 -ApiCmdDrawMeshTasksIndirectCountEXT = 48 -ApiCmdDrawMeshTasksIndirectEXT = 49 -ApiRayTracingSeparateCompiled = 8388608 -ApiInvalid = 4294967295 -rgp_sqtt_marker_general_api_type = ctypes.c_uint32 # enum -class struct_rgp_sqtt_marker_general_api(Structure): - pass - -class union_rgp_sqtt_marker_general_api_0(Union): - pass - -class struct_rgp_sqtt_marker_general_api_0_0(Structure): - pass - -struct_rgp_sqtt_marker_general_api_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_general_api(Struct): pass +class struct_rgp_sqtt_marker_general_api_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_general_api_0_0(Struct): pass struct_rgp_sqtt_marker_general_api_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('api_type', ctypes.c_uint32, 20), - ('is_end', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 4), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('api_type', uint32_t,20), + ('is_end', uint32_t,1), + ('reserved', uint32_t,4), ] - -union_rgp_sqtt_marker_general_api_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_general_api_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_general_api_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_general_api_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_general_api_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_general_api_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_general_api_0_0), + ('dword01', uint32_t), ] - -struct_rgp_sqtt_marker_general_api._pack_ = 1 # source:False -struct_rgp_sqtt_marker_general_api._anonymous_ = ('_0',) +struct_rgp_sqtt_marker_general_api._anonymous_ = ['_0'] struct_rgp_sqtt_marker_general_api._fields_ = [ - ('_0', union_rgp_sqtt_marker_general_api_0), + ('_0', struct_rgp_sqtt_marker_general_api_0), ] +enum_rgp_sqtt_marker_event_type = CEnum(ctypes.c_uint32) +EventCmdDraw = enum_rgp_sqtt_marker_event_type.define('EventCmdDraw', 0) +EventCmdDrawIndexed = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndexed', 1) +EventCmdDrawIndirect = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndirect', 2) +EventCmdDrawIndexedIndirect = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndexedIndirect', 3) +EventCmdDrawIndirectCountAMD = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndirectCountAMD', 4) +EventCmdDrawIndexedIndirectCountAMD = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndexedIndirectCountAMD', 5) +EventCmdDispatch = enum_rgp_sqtt_marker_event_type.define('EventCmdDispatch', 6) +EventCmdDispatchIndirect = enum_rgp_sqtt_marker_event_type.define('EventCmdDispatchIndirect', 7) +EventCmdCopyBuffer = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyBuffer', 8) +EventCmdCopyImage = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyImage', 9) +EventCmdBlitImage = enum_rgp_sqtt_marker_event_type.define('EventCmdBlitImage', 10) +EventCmdCopyBufferToImage = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyBufferToImage', 11) +EventCmdCopyImageToBuffer = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyImageToBuffer', 12) +EventCmdUpdateBuffer = enum_rgp_sqtt_marker_event_type.define('EventCmdUpdateBuffer', 13) +EventCmdFillBuffer = enum_rgp_sqtt_marker_event_type.define('EventCmdFillBuffer', 14) +EventCmdClearColorImage = enum_rgp_sqtt_marker_event_type.define('EventCmdClearColorImage', 15) +EventCmdClearDepthStencilImage = enum_rgp_sqtt_marker_event_type.define('EventCmdClearDepthStencilImage', 16) +EventCmdClearAttachments = enum_rgp_sqtt_marker_event_type.define('EventCmdClearAttachments', 17) +EventCmdResolveImage = enum_rgp_sqtt_marker_event_type.define('EventCmdResolveImage', 18) +EventCmdWaitEvents = enum_rgp_sqtt_marker_event_type.define('EventCmdWaitEvents', 19) +EventCmdPipelineBarrier = enum_rgp_sqtt_marker_event_type.define('EventCmdPipelineBarrier', 20) +EventCmdResetQueryPool = enum_rgp_sqtt_marker_event_type.define('EventCmdResetQueryPool', 21) +EventCmdCopyQueryPoolResults = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyQueryPoolResults', 22) +EventRenderPassColorClear = enum_rgp_sqtt_marker_event_type.define('EventRenderPassColorClear', 23) +EventRenderPassDepthStencilClear = enum_rgp_sqtt_marker_event_type.define('EventRenderPassDepthStencilClear', 24) +EventRenderPassResolve = enum_rgp_sqtt_marker_event_type.define('EventRenderPassResolve', 25) +EventInternalUnknown = enum_rgp_sqtt_marker_event_type.define('EventInternalUnknown', 26) +EventCmdDrawIndirectCount = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndirectCount', 27) +EventCmdDrawIndexedIndirectCount = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawIndexedIndirectCount', 28) +EventCmdTraceRaysKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdTraceRaysKHR', 30) +EventCmdTraceRaysIndirectKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdTraceRaysIndirectKHR', 31) +EventCmdBuildAccelerationStructuresKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdBuildAccelerationStructuresKHR', 32) +EventCmdBuildAccelerationStructuresIndirectKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdBuildAccelerationStructuresIndirectKHR', 33) +EventCmdCopyAccelerationStructureKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyAccelerationStructureKHR', 34) +EventCmdCopyAccelerationStructureToMemoryKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyAccelerationStructureToMemoryKHR', 35) +EventCmdCopyMemoryToAccelerationStructureKHR = enum_rgp_sqtt_marker_event_type.define('EventCmdCopyMemoryToAccelerationStructureKHR', 36) +EventCmdDrawMeshTasksEXT = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawMeshTasksEXT', 41) +EventCmdDrawMeshTasksIndirectCountEXT = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawMeshTasksIndirectCountEXT', 42) +EventCmdDrawMeshTasksIndirectEXT = enum_rgp_sqtt_marker_event_type.define('EventCmdDrawMeshTasksIndirectEXT', 43) +EventUnknown = enum_rgp_sqtt_marker_event_type.define('EventUnknown', 32767) +EventInvalid = enum_rgp_sqtt_marker_event_type.define('EventInvalid', 4294967295) - -# values for enumeration 'rgp_sqtt_marker_event_type' -rgp_sqtt_marker_event_type__enumvalues = { - 0: 'EventCmdDraw', - 1: 'EventCmdDrawIndexed', - 2: 'EventCmdDrawIndirect', - 3: 'EventCmdDrawIndexedIndirect', - 4: 'EventCmdDrawIndirectCountAMD', - 5: 'EventCmdDrawIndexedIndirectCountAMD', - 6: 'EventCmdDispatch', - 7: 'EventCmdDispatchIndirect', - 8: 'EventCmdCopyBuffer', - 9: 'EventCmdCopyImage', - 10: 'EventCmdBlitImage', - 11: 'EventCmdCopyBufferToImage', - 12: 'EventCmdCopyImageToBuffer', - 13: 'EventCmdUpdateBuffer', - 14: 'EventCmdFillBuffer', - 15: 'EventCmdClearColorImage', - 16: 'EventCmdClearDepthStencilImage', - 17: 'EventCmdClearAttachments', - 18: 'EventCmdResolveImage', - 19: 'EventCmdWaitEvents', - 20: 'EventCmdPipelineBarrier', - 21: 'EventCmdResetQueryPool', - 22: 'EventCmdCopyQueryPoolResults', - 23: 'EventRenderPassColorClear', - 24: 'EventRenderPassDepthStencilClear', - 25: 'EventRenderPassResolve', - 26: 'EventInternalUnknown', - 27: 'EventCmdDrawIndirectCount', - 28: 'EventCmdDrawIndexedIndirectCount', - 30: 'EventCmdTraceRaysKHR', - 31: 'EventCmdTraceRaysIndirectKHR', - 32: 'EventCmdBuildAccelerationStructuresKHR', - 33: 'EventCmdBuildAccelerationStructuresIndirectKHR', - 34: 'EventCmdCopyAccelerationStructureKHR', - 35: 'EventCmdCopyAccelerationStructureToMemoryKHR', - 36: 'EventCmdCopyMemoryToAccelerationStructureKHR', - 41: 'EventCmdDrawMeshTasksEXT', - 42: 'EventCmdDrawMeshTasksIndirectCountEXT', - 43: 'EventCmdDrawMeshTasksIndirectEXT', - 32767: 'EventUnknown', - 4294967295: 'EventInvalid', -} -EventCmdDraw = 0 -EventCmdDrawIndexed = 1 -EventCmdDrawIndirect = 2 -EventCmdDrawIndexedIndirect = 3 -EventCmdDrawIndirectCountAMD = 4 -EventCmdDrawIndexedIndirectCountAMD = 5 -EventCmdDispatch = 6 -EventCmdDispatchIndirect = 7 -EventCmdCopyBuffer = 8 -EventCmdCopyImage = 9 -EventCmdBlitImage = 10 -EventCmdCopyBufferToImage = 11 -EventCmdCopyImageToBuffer = 12 -EventCmdUpdateBuffer = 13 -EventCmdFillBuffer = 14 -EventCmdClearColorImage = 15 -EventCmdClearDepthStencilImage = 16 -EventCmdClearAttachments = 17 -EventCmdResolveImage = 18 -EventCmdWaitEvents = 19 -EventCmdPipelineBarrier = 20 -EventCmdResetQueryPool = 21 -EventCmdCopyQueryPoolResults = 22 -EventRenderPassColorClear = 23 -EventRenderPassDepthStencilClear = 24 -EventRenderPassResolve = 25 -EventInternalUnknown = 26 -EventCmdDrawIndirectCount = 27 -EventCmdDrawIndexedIndirectCount = 28 -EventCmdTraceRaysKHR = 30 -EventCmdTraceRaysIndirectKHR = 31 -EventCmdBuildAccelerationStructuresKHR = 32 -EventCmdBuildAccelerationStructuresIndirectKHR = 33 -EventCmdCopyAccelerationStructureKHR = 34 -EventCmdCopyAccelerationStructureToMemoryKHR = 35 -EventCmdCopyMemoryToAccelerationStructureKHR = 36 -EventCmdDrawMeshTasksEXT = 41 -EventCmdDrawMeshTasksIndirectCountEXT = 42 -EventCmdDrawMeshTasksIndirectEXT = 43 -EventUnknown = 32767 -EventInvalid = 4294967295 -rgp_sqtt_marker_event_type = ctypes.c_uint32 # enum -class struct_rgp_sqtt_marker_event(Structure): - pass - -class union_rgp_sqtt_marker_event_0(Union): - pass - -class struct_rgp_sqtt_marker_event_0_0(Structure): - pass - -struct_rgp_sqtt_marker_event_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_event(Struct): pass +class struct_rgp_sqtt_marker_event_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_event_0_0(Struct): pass struct_rgp_sqtt_marker_event_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('api_type', ctypes.c_uint32, 24), - ('has_thread_dims', ctypes.c_uint32, 1), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('api_type', uint32_t,24), + ('has_thread_dims', uint32_t,1), ] - -union_rgp_sqtt_marker_event_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_event_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_event_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_event_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_event_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_event_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_event_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_event_1(Union): - pass - -class struct_rgp_sqtt_marker_event_1_0(Structure): - pass - -struct_rgp_sqtt_marker_event_1_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_event_1(ctypes.Union): pass +class struct_rgp_sqtt_marker_event_1_0(Struct): pass struct_rgp_sqtt_marker_event_1_0._fields_ = [ - ('cb_id', ctypes.c_uint32, 20), - ('vertex_offset_reg_idx', ctypes.c_uint32, 4), - ('instance_offset_reg_idx', ctypes.c_uint32, 4), - ('draw_index_reg_idx', ctypes.c_uint32, 4), + ('cb_id', uint32_t,20), + ('vertex_offset_reg_idx', uint32_t,4), + ('instance_offset_reg_idx', uint32_t,4), + ('draw_index_reg_idx', uint32_t,4), ] - -union_rgp_sqtt_marker_event_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_event_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_event_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_event_1_0), - ('dword02', ctypes.c_uint32), +struct_rgp_sqtt_marker_event_1._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_event_1._fields_ = [ + ('_0', struct_rgp_sqtt_marker_event_1_0), + ('dword02', uint32_t), ] - -class union_rgp_sqtt_marker_event_2(Union): - pass - -union_rgp_sqtt_marker_event_2._pack_ = 1 # source:False -union_rgp_sqtt_marker_event_2._fields_ = [ - ('cmd_id', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), +class struct_rgp_sqtt_marker_event_2(ctypes.Union): pass +struct_rgp_sqtt_marker_event_2._fields_ = [ + ('cmd_id', uint32_t), + ('dword03', uint32_t), ] - -struct_rgp_sqtt_marker_event._pack_ = 1 # source:False -struct_rgp_sqtt_marker_event._anonymous_ = ('_0', '_1', '_2',) +struct_rgp_sqtt_marker_event._anonymous_ = ['_0', '_1', '_2'] struct_rgp_sqtt_marker_event._fields_ = [ - ('_0', union_rgp_sqtt_marker_event_0), - ('_1', union_rgp_sqtt_marker_event_1), - ('_2', union_rgp_sqtt_marker_event_2), + ('_0', struct_rgp_sqtt_marker_event_0), + ('_1', struct_rgp_sqtt_marker_event_1), + ('_2', struct_rgp_sqtt_marker_event_2), ] - -class struct_rgp_sqtt_marker_event_with_dims(Structure): - pass - -struct_rgp_sqtt_marker_event_with_dims._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_event_with_dims(Struct): pass struct_rgp_sqtt_marker_event_with_dims._fields_ = [ - ('event', struct_rgp_sqtt_marker_event), - ('thread_x', ctypes.c_uint32), - ('thread_y', ctypes.c_uint32), - ('thread_z', ctypes.c_uint32), + ('event', struct_rgp_sqtt_marker_event), + ('thread_x', uint32_t), + ('thread_y', uint32_t), + ('thread_z', uint32_t), ] - -class struct_rgp_sqtt_marker_barrier_start(Structure): - pass - -class union_rgp_sqtt_marker_barrier_start_0(Union): - pass - -class struct_rgp_sqtt_marker_barrier_start_0_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_start_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_barrier_start(Struct): pass +class struct_rgp_sqtt_marker_barrier_start_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_barrier_start_0_0(Struct): pass struct_rgp_sqtt_marker_barrier_start_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('reserved', ctypes.c_uint32, 5), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('cb_id', uint32_t,20), + ('reserved', uint32_t,5), ] - -union_rgp_sqtt_marker_barrier_start_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_start_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_start_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_start_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_barrier_start_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_barrier_start_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_barrier_start_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_barrier_start_1(Union): - pass - -class struct_rgp_sqtt_marker_barrier_start_1_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_start_1_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_barrier_start_1(ctypes.Union): pass +class struct_rgp_sqtt_marker_barrier_start_1_0(Struct): pass struct_rgp_sqtt_marker_barrier_start_1_0._fields_ = [ - ('driver_reason', ctypes.c_uint32, 31), - ('internal', ctypes.c_uint32, 1), + ('driver_reason', uint32_t,31), + ('internal', uint32_t,1), ] - -union_rgp_sqtt_marker_barrier_start_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_start_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_start_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_start_1_0), - ('dword02', ctypes.c_uint32), +struct_rgp_sqtt_marker_barrier_start_1._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_barrier_start_1._fields_ = [ + ('_0', struct_rgp_sqtt_marker_barrier_start_1_0), + ('dword02', uint32_t), ] - -struct_rgp_sqtt_marker_barrier_start._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_start._anonymous_ = ('_0', '_1',) +struct_rgp_sqtt_marker_barrier_start._anonymous_ = ['_0', '_1'] struct_rgp_sqtt_marker_barrier_start._fields_ = [ - ('_0', union_rgp_sqtt_marker_barrier_start_0), - ('_1', union_rgp_sqtt_marker_barrier_start_1), + ('_0', struct_rgp_sqtt_marker_barrier_start_0), + ('_1', struct_rgp_sqtt_marker_barrier_start_1), ] - -class struct_rgp_sqtt_marker_barrier_end(Structure): - pass - -class union_rgp_sqtt_marker_barrier_end_0(Union): - pass - -class struct_rgp_sqtt_marker_barrier_end_0_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_end_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_barrier_end(Struct): pass +class struct_rgp_sqtt_marker_barrier_end_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_barrier_end_0_0(Struct): pass struct_rgp_sqtt_marker_barrier_end_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('cb_id', ctypes.c_uint32, 20), - ('wait_on_eop_ts', ctypes.c_uint32, 1), - ('vs_partial_flush', ctypes.c_uint32, 1), - ('ps_partial_flush', ctypes.c_uint32, 1), - ('cs_partial_flush', ctypes.c_uint32, 1), - ('pfp_sync_me', ctypes.c_uint32, 1), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('cb_id', uint32_t,20), + ('wait_on_eop_ts', uint32_t,1), + ('vs_partial_flush', uint32_t,1), + ('ps_partial_flush', uint32_t,1), + ('cs_partial_flush', uint32_t,1), + ('pfp_sync_me', uint32_t,1), ] - -union_rgp_sqtt_marker_barrier_end_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_end_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_end_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_end_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_barrier_end_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_barrier_end_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_barrier_end_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_barrier_end_1(Union): - pass - -class struct_rgp_sqtt_marker_barrier_end_1_0(Structure): - pass - -struct_rgp_sqtt_marker_barrier_end_1_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_barrier_end_1(ctypes.Union): pass +class struct_rgp_sqtt_marker_barrier_end_1_0(Struct): pass struct_rgp_sqtt_marker_barrier_end_1_0._fields_ = [ - ('sync_cp_dma', ctypes.c_uint32, 1), - ('inval_tcp', ctypes.c_uint32, 1), - ('inval_sqI', ctypes.c_uint32, 1), - ('inval_sqK', ctypes.c_uint32, 1), - ('flush_tcc', ctypes.c_uint32, 1), - ('inval_tcc', ctypes.c_uint32, 1), - ('flush_cb', ctypes.c_uint32, 1), - ('inval_cb', ctypes.c_uint32, 1), - ('flush_db', ctypes.c_uint32, 1), - ('inval_db', ctypes.c_uint32, 1), - ('num_layout_transitions', ctypes.c_uint32, 16), - ('inval_gl1', ctypes.c_uint32, 1), - ('wait_on_ts', ctypes.c_uint32, 1), - ('eop_ts_bottom_of_pipe', ctypes.c_uint32, 1), - ('eos_ts_ps_done', ctypes.c_uint32, 1), - ('eos_ts_cs_done', ctypes.c_uint32, 1), - ('reserved', ctypes.c_uint32, 1), + ('sync_cp_dma', uint32_t,1), + ('inval_tcp', uint32_t,1), + ('inval_sqI', uint32_t,1), + ('inval_sqK', uint32_t,1), + ('flush_tcc', uint32_t,1), + ('inval_tcc', uint32_t,1), + ('flush_cb', uint32_t,1), + ('inval_cb', uint32_t,1), + ('flush_db', uint32_t,1), + ('inval_db', uint32_t,1), + ('num_layout_transitions', uint32_t,16), + ('inval_gl1', uint32_t,1), + ('wait_on_ts', uint32_t,1), + ('eop_ts_bottom_of_pipe', uint32_t,1), + ('eos_ts_ps_done', uint32_t,1), + ('eos_ts_cs_done', uint32_t,1), + ('reserved', uint32_t,1), ] - -union_rgp_sqtt_marker_barrier_end_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_barrier_end_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_barrier_end_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_barrier_end_1_0), - ('dword02', ctypes.c_uint32), +struct_rgp_sqtt_marker_barrier_end_1._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_barrier_end_1._fields_ = [ + ('_0', struct_rgp_sqtt_marker_barrier_end_1_0), + ('dword02', uint32_t), ] - -struct_rgp_sqtt_marker_barrier_end._pack_ = 1 # source:False -struct_rgp_sqtt_marker_barrier_end._anonymous_ = ('_0', '_1',) +struct_rgp_sqtt_marker_barrier_end._anonymous_ = ['_0', '_1'] struct_rgp_sqtt_marker_barrier_end._fields_ = [ - ('_0', union_rgp_sqtt_marker_barrier_end_0), - ('_1', union_rgp_sqtt_marker_barrier_end_1), + ('_0', struct_rgp_sqtt_marker_barrier_end_0), + ('_1', struct_rgp_sqtt_marker_barrier_end_1), ] - -class struct_rgp_sqtt_marker_layout_transition(Structure): - pass - -class union_rgp_sqtt_marker_layout_transition_0(Union): - pass - -class struct_rgp_sqtt_marker_layout_transition_0_0(Structure): - pass - -struct_rgp_sqtt_marker_layout_transition_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_layout_transition(Struct): pass +class struct_rgp_sqtt_marker_layout_transition_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_layout_transition_0_0(Struct): pass struct_rgp_sqtt_marker_layout_transition_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('depth_stencil_expand', ctypes.c_uint32, 1), - ('htile_hiz_range_expand', ctypes.c_uint32, 1), - ('depth_stencil_resummarize', ctypes.c_uint32, 1), - ('dcc_decompress', ctypes.c_uint32, 1), - ('fmask_decompress', ctypes.c_uint32, 1), - ('fast_clear_eliminate', ctypes.c_uint32, 1), - ('fmask_color_expand', ctypes.c_uint32, 1), - ('init_mask_ram', ctypes.c_uint32, 1), - ('reserved1', ctypes.c_uint32, 17), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('depth_stencil_expand', uint32_t,1), + ('htile_hiz_range_expand', uint32_t,1), + ('depth_stencil_resummarize', uint32_t,1), + ('dcc_decompress', uint32_t,1), + ('fmask_decompress', uint32_t,1), + ('fast_clear_eliminate', uint32_t,1), + ('fmask_color_expand', uint32_t,1), + ('init_mask_ram', uint32_t,1), + ('reserved1', uint32_t,17), ] - -union_rgp_sqtt_marker_layout_transition_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_layout_transition_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_layout_transition_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_layout_transition_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_layout_transition_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_layout_transition_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_layout_transition_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_layout_transition_1(Union): - pass - -class struct_rgp_sqtt_marker_layout_transition_1_0(Structure): - pass - -struct_rgp_sqtt_marker_layout_transition_1_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_layout_transition_1(ctypes.Union): pass +class struct_rgp_sqtt_marker_layout_transition_1_0(Struct): pass struct_rgp_sqtt_marker_layout_transition_1_0._fields_ = [ - ('reserved2', ctypes.c_uint32, 32), + ('reserved2', uint32_t,32), ] - -union_rgp_sqtt_marker_layout_transition_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_layout_transition_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_layout_transition_1._fields_ = [ - ('_0', struct_rgp_sqtt_marker_layout_transition_1_0), - ('dword02', ctypes.c_uint32), +struct_rgp_sqtt_marker_layout_transition_1._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_layout_transition_1._fields_ = [ + ('_0', struct_rgp_sqtt_marker_layout_transition_1_0), + ('dword02', uint32_t), ] - -struct_rgp_sqtt_marker_layout_transition._pack_ = 1 # source:False -struct_rgp_sqtt_marker_layout_transition._anonymous_ = ('_0', '_1',) +struct_rgp_sqtt_marker_layout_transition._anonymous_ = ['_0', '_1'] struct_rgp_sqtt_marker_layout_transition._fields_ = [ - ('_0', union_rgp_sqtt_marker_layout_transition_0), - ('_1', union_rgp_sqtt_marker_layout_transition_1), + ('_0', struct_rgp_sqtt_marker_layout_transition_0), + ('_1', struct_rgp_sqtt_marker_layout_transition_1), ] - -class struct_rgp_sqtt_marker_user_event(Structure): - pass - -class union_rgp_sqtt_marker_user_event_0(Union): - pass - -class struct_rgp_sqtt_marker_user_event_0_0(Structure): - pass - -struct_rgp_sqtt_marker_user_event_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_user_event(Struct): pass +class struct_rgp_sqtt_marker_user_event_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_user_event_0_0(Struct): pass struct_rgp_sqtt_marker_user_event_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('reserved0', ctypes.c_uint32, 8), - ('data_type', ctypes.c_uint32, 8), - ('reserved1', ctypes.c_uint32, 12), + ('identifier', uint32_t,4), + ('reserved0', uint32_t,8), + ('data_type', uint32_t,8), + ('reserved1', uint32_t,12), ] - -union_rgp_sqtt_marker_user_event_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_user_event_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_user_event_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_user_event_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_user_event_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_user_event_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_user_event_0_0), + ('dword01', uint32_t), ] - -struct_rgp_sqtt_marker_user_event._pack_ = 1 # source:False -struct_rgp_sqtt_marker_user_event._anonymous_ = ('_0',) +struct_rgp_sqtt_marker_user_event._anonymous_ = ['_0'] struct_rgp_sqtt_marker_user_event._fields_ = [ - ('_0', union_rgp_sqtt_marker_user_event_0), + ('_0', struct_rgp_sqtt_marker_user_event_0), ] - -class struct_rgp_sqtt_marker_user_event_with_length(Structure): - pass - -struct_rgp_sqtt_marker_user_event_with_length._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_user_event_with_length(Struct): pass struct_rgp_sqtt_marker_user_event_with_length._fields_ = [ - ('user_event', struct_rgp_sqtt_marker_user_event), - ('length', ctypes.c_uint32), + ('user_event', struct_rgp_sqtt_marker_user_event), + ('length', uint32_t), ] +enum_rgp_sqtt_marker_user_event_type = CEnum(ctypes.c_uint32) +UserEventTrigger = enum_rgp_sqtt_marker_user_event_type.define('UserEventTrigger', 0) +UserEventPop = enum_rgp_sqtt_marker_user_event_type.define('UserEventPop', 1) +UserEventPush = enum_rgp_sqtt_marker_user_event_type.define('UserEventPush', 2) +UserEventObjectName = enum_rgp_sqtt_marker_user_event_type.define('UserEventObjectName', 3) - -# values for enumeration 'rgp_sqtt_marker_user_event_type' -rgp_sqtt_marker_user_event_type__enumvalues = { - 0: 'UserEventTrigger', - 1: 'UserEventPop', - 2: 'UserEventPush', - 3: 'UserEventObjectName', -} -UserEventTrigger = 0 -UserEventPop = 1 -UserEventPush = 2 -UserEventObjectName = 3 -rgp_sqtt_marker_user_event_type = ctypes.c_uint32 # enum -class struct_rgp_sqtt_marker_pipeline_bind(Structure): - pass - -class union_rgp_sqtt_marker_pipeline_bind_0(Union): - pass - -class struct_rgp_sqtt_marker_pipeline_bind_0_0(Structure): - pass - -struct_rgp_sqtt_marker_pipeline_bind_0_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_pipeline_bind(Struct): pass +class struct_rgp_sqtt_marker_pipeline_bind_0(ctypes.Union): pass +class struct_rgp_sqtt_marker_pipeline_bind_0_0(Struct): pass struct_rgp_sqtt_marker_pipeline_bind_0_0._fields_ = [ - ('identifier', ctypes.c_uint32, 4), - ('ext_dwords', ctypes.c_uint32, 3), - ('bind_point', ctypes.c_uint32, 1), - ('cb_id', ctypes.c_uint32, 20), - ('reserved', ctypes.c_uint32, 4), + ('identifier', uint32_t,4), + ('ext_dwords', uint32_t,3), + ('bind_point', uint32_t,1), + ('cb_id', uint32_t,20), + ('reserved', uint32_t,4), ] - -union_rgp_sqtt_marker_pipeline_bind_0._pack_ = 1 # source:False -union_rgp_sqtt_marker_pipeline_bind_0._anonymous_ = ('_0',) -union_rgp_sqtt_marker_pipeline_bind_0._fields_ = [ - ('_0', struct_rgp_sqtt_marker_pipeline_bind_0_0), - ('dword01', ctypes.c_uint32), +struct_rgp_sqtt_marker_pipeline_bind_0._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_pipeline_bind_0._fields_ = [ + ('_0', struct_rgp_sqtt_marker_pipeline_bind_0_0), + ('dword01', uint32_t), ] - -class union_rgp_sqtt_marker_pipeline_bind_1(Union): - pass - -class struct_rgp_sqtt_marker_pipeline_bind_1_0(Structure): - pass - -struct_rgp_sqtt_marker_pipeline_bind_1_0._pack_ = 1 # source:False +class struct_rgp_sqtt_marker_pipeline_bind_1(ctypes.Union): pass +class struct_rgp_sqtt_marker_pipeline_bind_1_0(Struct): pass struct_rgp_sqtt_marker_pipeline_bind_1_0._fields_ = [ - ('dword02', ctypes.c_uint32), - ('dword03', ctypes.c_uint32), + ('dword02', uint32_t), + ('dword03', uint32_t), ] - -union_rgp_sqtt_marker_pipeline_bind_1._pack_ = 1 # source:False -union_rgp_sqtt_marker_pipeline_bind_1._anonymous_ = ('_0',) -union_rgp_sqtt_marker_pipeline_bind_1._fields_ = [ - ('api_pso_hash', ctypes.c_uint32 * 2), - ('_0', struct_rgp_sqtt_marker_pipeline_bind_1_0), +struct_rgp_sqtt_marker_pipeline_bind_1._anonymous_ = ['_0'] +struct_rgp_sqtt_marker_pipeline_bind_1._fields_ = [ + ('api_pso_hash', (uint32_t * 2)), + ('_0', struct_rgp_sqtt_marker_pipeline_bind_1_0), ] - -struct_rgp_sqtt_marker_pipeline_bind._pack_ = 1 # source:False -struct_rgp_sqtt_marker_pipeline_bind._anonymous_ = ('_0', '_1',) +struct_rgp_sqtt_marker_pipeline_bind._anonymous_ = ['_0', '_1'] struct_rgp_sqtt_marker_pipeline_bind._fields_ = [ - ('_0', union_rgp_sqtt_marker_pipeline_bind_0), - ('_1', union_rgp_sqtt_marker_pipeline_bind_1), + ('_0', struct_rgp_sqtt_marker_pipeline_bind_0), + ('_1', struct_rgp_sqtt_marker_pipeline_bind_1), ] - -__all__ = \ - ['ApiCmdBeginQuery', 'ApiCmdBeginRenderPass', - 'ApiCmdBindDescriptorSets', 'ApiCmdBindIndexBuffer', - 'ApiCmdBindPipeline', 'ApiCmdBindVertexBuffers', - 'ApiCmdBlitImage', 'ApiCmdClearAttachments', - 'ApiCmdClearColorImage', 'ApiCmdClearDepthStencilImage', - 'ApiCmdCopyBuffer', 'ApiCmdCopyBufferToImage', 'ApiCmdCopyImage', - 'ApiCmdCopyImageToBuffer', 'ApiCmdCopyQueryPoolResults', - 'ApiCmdDispatch', 'ApiCmdDispatchIndirect', 'ApiCmdDraw', - 'ApiCmdDrawIndexed', 'ApiCmdDrawIndexedIndirect', - 'ApiCmdDrawIndexedIndirectCount', - 'ApiCmdDrawIndexedIndirectCountAMD', 'ApiCmdDrawIndirect', - 'ApiCmdDrawIndirectCount', 'ApiCmdDrawIndirectCountAMD', - 'ApiCmdDrawMeshTasksEXT', 'ApiCmdDrawMeshTasksIndirectCountEXT', - 'ApiCmdDrawMeshTasksIndirectEXT', 'ApiCmdEndQuery', - 'ApiCmdEndRenderPass', 'ApiCmdExecuteCommands', - 'ApiCmdFillBuffer', 'ApiCmdNextSubpass', 'ApiCmdPipelineBarrier', - 'ApiCmdPushConstants', 'ApiCmdResetQueryPool', - 'ApiCmdResolveImage', 'ApiCmdSetBlendConstants', - 'ApiCmdSetDepthBias', 'ApiCmdSetDepthBounds', - 'ApiCmdSetLineWidth', 'ApiCmdSetScissor', - 'ApiCmdSetStencilCompareMask', 'ApiCmdSetStencilReference', - 'ApiCmdSetStencilWriteMask', 'ApiCmdSetViewport', - 'ApiCmdUpdateBuffer', 'ApiCmdWaitEvents', 'ApiCmdWriteTimestamp', - 'ApiInvalid', 'ApiRayTracingSeparateCompiled', - 'EF_AMDGPU_MACH_AMDGCN_GFX1010', 'EF_AMDGPU_MACH_AMDGCN_GFX1030', - 'EF_AMDGPU_MACH_AMDGCN_GFX1100', 'EF_AMDGPU_MACH_AMDGCN_GFX1150', - 'EF_AMDGPU_MACH_AMDGCN_GFX1200', 'EF_AMDGPU_MACH_AMDGCN_GFX801', - 'EF_AMDGPU_MACH_AMDGCN_GFX900', 'EventCmdBlitImage', - 'EventCmdBuildAccelerationStructuresIndirectKHR', - 'EventCmdBuildAccelerationStructuresKHR', - 'EventCmdClearAttachments', 'EventCmdClearColorImage', - 'EventCmdClearDepthStencilImage', - 'EventCmdCopyAccelerationStructureKHR', - 'EventCmdCopyAccelerationStructureToMemoryKHR', - 'EventCmdCopyBuffer', 'EventCmdCopyBufferToImage', - 'EventCmdCopyImage', 'EventCmdCopyImageToBuffer', - 'EventCmdCopyMemoryToAccelerationStructureKHR', - 'EventCmdCopyQueryPoolResults', 'EventCmdDispatch', - 'EventCmdDispatchIndirect', 'EventCmdDraw', 'EventCmdDrawIndexed', - 'EventCmdDrawIndexedIndirect', 'EventCmdDrawIndexedIndirectCount', - 'EventCmdDrawIndexedIndirectCountAMD', 'EventCmdDrawIndirect', - 'EventCmdDrawIndirectCount', 'EventCmdDrawIndirectCountAMD', - 'EventCmdDrawMeshTasksEXT', - 'EventCmdDrawMeshTasksIndirectCountEXT', - 'EventCmdDrawMeshTasksIndirectEXT', 'EventCmdFillBuffer', - 'EventCmdPipelineBarrier', 'EventCmdResetQueryPool', - 'EventCmdResolveImage', 'EventCmdTraceRaysIndirectKHR', - 'EventCmdTraceRaysKHR', 'EventCmdUpdateBuffer', - 'EventCmdWaitEvents', 'EventInternalUnknown', 'EventInvalid', - 'EventRenderPassColorClear', 'EventRenderPassDepthStencilClear', - 'EventRenderPassResolve', 'EventUnknown', - 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END', - 'RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START', - 'RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE', - 'RGP_SQTT_MARKER_IDENTIFIER_CB_END', - 'RGP_SQTT_MARKER_IDENTIFIER_CB_START', - 'RGP_SQTT_MARKER_IDENTIFIER_EVENT', - 'RGP_SQTT_MARKER_IDENTIFIER_GENERAL_API', - 'RGP_SQTT_MARKER_IDENTIFIER_LAYOUT_TRANSITION', - 'RGP_SQTT_MARKER_IDENTIFIER_PRESENT', - 'RGP_SQTT_MARKER_IDENTIFIER_RENDER_PASS', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED2', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED4', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED5', - 'RGP_SQTT_MARKER_IDENTIFIER_RESERVED6', - 'RGP_SQTT_MARKER_IDENTIFIER_SYNC', - 'RGP_SQTT_MARKER_IDENTIFIER_USER_EVENT', - 'SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS', - 'SQTT_API_TYPE_DIRECTX_12', 'SQTT_API_TYPE_GENERIC', - 'SQTT_API_TYPE_OPENCL', 'SQTT_API_TYPE_VULKAN', - 'SQTT_ENGINE_TYPE_COMPUTE', 'SQTT_ENGINE_TYPE_DMA', - 'SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE', - 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS', - 'SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL', - 'SQTT_ENGINE_TYPE_UNIVERSAL', 'SQTT_ENGINE_TYPE_UNKNOWN', - 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED', - 'SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING', - 'SQTT_FILE_CHUNK_TYPE_API_INFO', 'SQTT_FILE_CHUNK_TYPE_ASIC_INFO', - 'SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION', - 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE', - 'SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS', - 'SQTT_FILE_CHUNK_TYPE_COUNT', 'SQTT_FILE_CHUNK_TYPE_CPU_INFO', - 'SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE', - 'SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION', - 'SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS', - 'SQTT_FILE_CHUNK_TYPE_RESERVED', 'SQTT_FILE_CHUNK_TYPE_SPM_DB', - 'SQTT_FILE_CHUNK_TYPE_SQTT_DATA', - 'SQTT_FILE_CHUNK_TYPE_SQTT_DESC', 'SQTT_FILE_MAGIC_NUMBER', - 'SQTT_FILE_VERSION_MAJOR', 'SQTT_FILE_VERSION_MINOR', - 'SQTT_GFXIP_LEVEL_GFXIP_10_1', 'SQTT_GFXIP_LEVEL_GFXIP_10_3', - 'SQTT_GFXIP_LEVEL_GFXIP_11_0', 'SQTT_GFXIP_LEVEL_GFXIP_11_5', - 'SQTT_GFXIP_LEVEL_GFXIP_12', 'SQTT_GFXIP_LEVEL_GFXIP_6', - 'SQTT_GFXIP_LEVEL_GFXIP_7', 'SQTT_GFXIP_LEVEL_GFXIP_8', - 'SQTT_GFXIP_LEVEL_GFXIP_8_1', 'SQTT_GFXIP_LEVEL_GFXIP_9', - 'SQTT_GFXIP_LEVEL_NONE', 'SQTT_GPU_NAME_MAX_SIZE', - 'SQTT_GPU_TYPE_DISCRETE', 'SQTT_GPU_TYPE_INTEGRATED', - 'SQTT_GPU_TYPE_UNKNOWN', 'SQTT_GPU_TYPE_VIRTUAL', - 'SQTT_INSTRUCTION_TRACE_API_PSO', - 'SQTT_INSTRUCTION_TRACE_DISABLED', - 'SQTT_INSTRUCTION_TRACE_FULL_FRAME', 'SQTT_MAX_NUM_SE', - 'SQTT_MEMORY_TYPE_DDR', 'SQTT_MEMORY_TYPE_DDR2', - 'SQTT_MEMORY_TYPE_DDR3', 'SQTT_MEMORY_TYPE_DDR4', - 'SQTT_MEMORY_TYPE_DDR5', 'SQTT_MEMORY_TYPE_GDDR3', - 'SQTT_MEMORY_TYPE_GDDR4', 'SQTT_MEMORY_TYPE_GDDR5', - 'SQTT_MEMORY_TYPE_GDDR6', 'SQTT_MEMORY_TYPE_HBM', - 'SQTT_MEMORY_TYPE_HBM2', 'SQTT_MEMORY_TYPE_HBM3', - 'SQTT_MEMORY_TYPE_LPDDR4', 'SQTT_MEMORY_TYPE_LPDDR5', - 'SQTT_MEMORY_TYPE_UNKNOWN', 'SQTT_PROFILING_MODE_INDEX', - 'SQTT_PROFILING_MODE_PRESENT', 'SQTT_PROFILING_MODE_TAG', - 'SQTT_PROFILING_MODE_USER_MARKERS', - 'SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT', - 'SQTT_QUEUE_TIMING_EVENT_PRESENT', - 'SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE', - 'SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE', - 'SQTT_QUEUE_TYPE_COMPUTE', 'SQTT_QUEUE_TYPE_DMA', - 'SQTT_QUEUE_TYPE_UNIVERSAL', 'SQTT_QUEUE_TYPE_UNKNOWN', - 'SQTT_SA_PER_SE', 'SQTT_VERSION_2_2', 'SQTT_VERSION_2_3', - 'SQTT_VERSION_2_4', 'SQTT_VERSION_3_2', 'SQTT_VERSION_3_3', - 'SQTT_VERSION_NONE', 'UserEventObjectName', 'UserEventPop', - 'UserEventPush', 'UserEventTrigger', 'elf_gfxip_level', - 'rgp_sqtt_marker_event_type', 'rgp_sqtt_marker_general_api_type', - 'rgp_sqtt_marker_identifier', 'rgp_sqtt_marker_user_event_type', - 'sqtt_api_type', 'sqtt_engine_type', - 'sqtt_file_chunk_asic_info_flags', 'sqtt_file_chunk_type', - 'sqtt_gfxip_level', 'sqtt_gpu_type', - 'sqtt_instruction_trace_mode', 'sqtt_memory_type', - 'sqtt_profiling_mode', 'sqtt_queue_event_type', 'sqtt_queue_type', - 'sqtt_version', 'struct_rgp_sqtt_marker_barrier_end', - 'struct_rgp_sqtt_marker_barrier_end_0_0', - 'struct_rgp_sqtt_marker_barrier_end_1_0', - 'struct_rgp_sqtt_marker_barrier_start', - 'struct_rgp_sqtt_marker_barrier_start_0_0', - 'struct_rgp_sqtt_marker_barrier_start_1_0', - 'struct_rgp_sqtt_marker_cb_end', - 'struct_rgp_sqtt_marker_cb_end_0_0', - 'struct_rgp_sqtt_marker_cb_id_global_cb_id', - 'struct_rgp_sqtt_marker_cb_id_per_frame_cb_id', - 'struct_rgp_sqtt_marker_cb_start', - 'struct_rgp_sqtt_marker_cb_start_0_0', - 'struct_rgp_sqtt_marker_event', - 'struct_rgp_sqtt_marker_event_0_0', - 'struct_rgp_sqtt_marker_event_1_0', - 'struct_rgp_sqtt_marker_event_with_dims', - 'struct_rgp_sqtt_marker_general_api', - 'struct_rgp_sqtt_marker_general_api_0_0', - 'struct_rgp_sqtt_marker_layout_transition', - 'struct_rgp_sqtt_marker_layout_transition_0_0', - 'struct_rgp_sqtt_marker_layout_transition_1_0', - 'struct_rgp_sqtt_marker_pipeline_bind', - 'struct_rgp_sqtt_marker_pipeline_bind_0_0', - 'struct_rgp_sqtt_marker_pipeline_bind_1_0', - 'struct_rgp_sqtt_marker_user_event', - 'struct_rgp_sqtt_marker_user_event_0_0', - 'struct_rgp_sqtt_marker_user_event_with_length', - 'struct_sqtt_code_object_database_record', - 'struct_sqtt_code_object_loader_events_record', - 'struct_sqtt_data_info', 'struct_sqtt_data_se', - 'struct_sqtt_file_chunk_api_info', - 'struct_sqtt_file_chunk_asic_info', - 'struct_sqtt_file_chunk_clock_calibration', - 'struct_sqtt_file_chunk_code_object_database', - 'struct_sqtt_file_chunk_code_object_loader_events', - 'struct_sqtt_file_chunk_cpu_info', - 'struct_sqtt_file_chunk_header', 'struct_sqtt_file_chunk_id', - 'struct_sqtt_file_chunk_pso_correlation', - 'struct_sqtt_file_chunk_queue_event_timings', - 'struct_sqtt_file_chunk_spm_db', - 'struct_sqtt_file_chunk_sqtt_data', - 'struct_sqtt_file_chunk_sqtt_desc', - 'struct_sqtt_file_chunk_sqtt_desc_0_v0', - 'struct_sqtt_file_chunk_sqtt_desc_0_v1', - 'struct_sqtt_file_header', 'struct_sqtt_file_header_flags', - 'struct_sqtt_file_header_flags_0_0', - 'struct_sqtt_instruction_trace_data_api_pso_data', - 'struct_sqtt_instruction_trace_data_shader_engine_filter', - 'struct_sqtt_profiling_mode_data_index_profiling_data', - 'struct_sqtt_profiling_mode_data_tag_profiling_data', - 'struct_sqtt_profiling_mode_data_user_marker_profiling_data', - 'struct_sqtt_pso_correlation_record', - 'struct_sqtt_queue_event_record', - 'struct_sqtt_queue_hardware_info', - 'struct_sqtt_queue_hardware_info_0_0', - 'struct_sqtt_queue_info_record', - 'union_rgp_sqtt_marker_barrier_end_0', - 'union_rgp_sqtt_marker_barrier_end_1', - 'union_rgp_sqtt_marker_barrier_start_0', - 'union_rgp_sqtt_marker_barrier_start_1', - 'union_rgp_sqtt_marker_cb_end_0', - 'union_rgp_sqtt_marker_cb_end_1', - 'union_rgp_sqtt_marker_cb_end_2', 'union_rgp_sqtt_marker_cb_id', - 'union_rgp_sqtt_marker_cb_start_0', - 'union_rgp_sqtt_marker_cb_start_1', - 'union_rgp_sqtt_marker_cb_start_2', - 'union_rgp_sqtt_marker_cb_start_3', - 'union_rgp_sqtt_marker_event_0', 'union_rgp_sqtt_marker_event_1', - 'union_rgp_sqtt_marker_event_2', - 'union_rgp_sqtt_marker_general_api_0', - 'union_rgp_sqtt_marker_layout_transition_0', - 'union_rgp_sqtt_marker_layout_transition_1', - 'union_rgp_sqtt_marker_pipeline_bind_0', - 'union_rgp_sqtt_marker_pipeline_bind_1', - 'union_rgp_sqtt_marker_user_event_0', 'union_sqtt_data_info_0', - 'union_sqtt_file_chunk_sqtt_desc_0', - 'union_sqtt_file_header_flags_0', - 'union_sqtt_instruction_trace_data', - 'union_sqtt_profiling_mode_data', - 'union_sqtt_queue_hardware_info_0'] +SQTT_FILE_MAGIC_NUMBER = 0x50303042 +SQTT_FILE_VERSION_MAJOR = 1 +SQTT_FILE_VERSION_MINOR = 5 +SQTT_GPU_NAME_MAX_SIZE = 256 +SQTT_MAX_NUM_SE = 32 +SQTT_SA_PER_SE = 2 +SQTT_ACTIVE_PIXEL_PACKER_MASK_DWORDS = 4 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/vfio.py b/tinygrad/runtime/autogen/vfio.py index 7daa00d430..c7a5334675 100644 --- a/tinygrad/runtime/autogen/vfio.py +++ b/tinygrad/runtime/autogen/vfio.py @@ -1,893 +1,584 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# import ctypes - - -from tinygrad.runtime.support.hcq import FileIOInterface -import functools - -def _do_ioctl_io(__idir, __base, __nr, __fd:FileIOInterface, val=0, __len=0): - return __fd.ioctl((__idir<<30) | (__len<<16) | (__base<<8) | __nr, val) - -def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:FileIOInterface, __val=None, **kwargs): - ret = __fd.ioctl((__idir<<30) | (ctypes.sizeof(made := (__made or __user_struct(**kwargs)))<<16) | (__base<<8) | __nr, made) - if ret != 0: raise RuntimeError(f"ioctl returned {ret}") - return made - -def _IO(base, nr): return functools.partial(_do_ioctl_io, 0, ord(base) if isinstance(base, str) else base, nr) -def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type) -def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type) -def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type) - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - -VFIO_H = True # macro -VFIO_API_VERSION = 0 # macro -VFIO_TYPE1_IOMMU = 1 # macro -VFIO_SPAPR_TCE_IOMMU = 2 # macro -VFIO_TYPE1v2_IOMMU = 3 # macro -VFIO_DMA_CC_IOMMU = 4 # macro -VFIO_EEH = 5 # macro -VFIO_TYPE1_NESTING_IOMMU = 6 # macro -VFIO_SPAPR_TCE_v2_IOMMU = 7 # macro -VFIO_NOIOMMU_IOMMU = 8 # macro -VFIO_UNMAP_ALL = 9 # macro -VFIO_UPDATE_VADDR = 10 # macro -VFIO_TYPE = (';') # macro -VFIO_BASE = 100 # macro -VFIO_GET_API_VERSION = _IO ( ( ';' ) , 100 + 0 ) # macro (from list) -VFIO_CHECK_EXTENSION = _IO ( ( ';' ) , 100 + 1 ) # macro (from list) -VFIO_SET_IOMMU = _IO ( ( ';' ) , 100 + 2 ) # macro (from list) -VFIO_GROUP_FLAGS_VIABLE = (1<<0) # macro -VFIO_GROUP_FLAGS_CONTAINER_SET = (1<<1) # macro -VFIO_GROUP_GET_STATUS = _IO ( ( ';' ) , 100 + 3 ) # macro (from list) -VFIO_GROUP_SET_CONTAINER = _IO ( ( ';' ) , 100 + 4 ) # macro (from list) -VFIO_GROUP_UNSET_CONTAINER = _IO ( ( ';' ) , 100 + 5 ) # macro (from list) -VFIO_GROUP_GET_DEVICE_FD = _IO ( ( ';' ) , 100 + 6 ) # macro (from list) -VFIO_DEVICE_FLAGS_RESET = (1<<0) # macro -VFIO_DEVICE_FLAGS_PCI = (1<<1) # macro -VFIO_DEVICE_FLAGS_PLATFORM = (1<<2) # macro -VFIO_DEVICE_FLAGS_AMBA = (1<<3) # macro -VFIO_DEVICE_FLAGS_CCW = (1<<4) # macro -VFIO_DEVICE_FLAGS_AP = (1<<5) # macro -VFIO_DEVICE_FLAGS_FSL_MC = (1<<6) # macro -VFIO_DEVICE_FLAGS_CAPS = (1<<7) # macro -VFIO_DEVICE_GET_INFO = _IO ( ( ';' ) , 100 + 7 ) # macro (from list) -VFIO_DEVICE_API_PCI_STRING = "vfio-pci" # macro -VFIO_DEVICE_API_PLATFORM_STRING = "vfio-platform" # macro -VFIO_DEVICE_API_AMBA_STRING = "vfio-amba" # macro -VFIO_DEVICE_API_CCW_STRING = "vfio-ccw" # macro -VFIO_DEVICE_API_AP_STRING = "vfio-ap" # macro -VFIO_DEVICE_INFO_CAP_ZPCI_BASE = 1 # macro -VFIO_DEVICE_INFO_CAP_ZPCI_GROUP = 2 # macro -VFIO_DEVICE_INFO_CAP_ZPCI_UTIL = 3 # macro -VFIO_DEVICE_INFO_CAP_ZPCI_PFIP = 4 # macro -VFIO_REGION_INFO_FLAG_READ = (1<<0) # macro -VFIO_REGION_INFO_FLAG_WRITE = (1<<1) # macro -VFIO_REGION_INFO_FLAG_MMAP = (1<<2) # macro -VFIO_REGION_INFO_FLAG_CAPS = (1<<3) # macro -VFIO_DEVICE_GET_REGION_INFO = _IO ( ( ';' ) , 100 + 8 ) # macro (from list) -VFIO_REGION_INFO_CAP_SPARSE_MMAP = 1 # macro -VFIO_REGION_INFO_CAP_TYPE = 2 # macro -VFIO_REGION_TYPE_PCI_VENDOR_TYPE = (1<<31) # macro -VFIO_REGION_TYPE_PCI_VENDOR_MASK = (0xffff) # macro -VFIO_REGION_TYPE_GFX = (1) # macro -VFIO_REGION_TYPE_CCW = (2) # macro -VFIO_REGION_TYPE_MIGRATION = (3) # macro -VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION = (1) # macro -VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG = (2) # macro -VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG = (3) # macro -VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM = (1) # macro -VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD = (1) # macro -VFIO_REGION_SUBTYPE_GFX_EDID = (1) # macro -VFIO_DEVICE_GFX_LINK_STATE_UP = 1 # macro -VFIO_DEVICE_GFX_LINK_STATE_DOWN = 2 # macro -VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD = (1) # macro -VFIO_REGION_SUBTYPE_CCW_SCHIB = (2) # macro -VFIO_REGION_SUBTYPE_CCW_CRW = (3) # macro -VFIO_REGION_SUBTYPE_MIGRATION = (1) # macro -VFIO_DEVICE_STATE_STOP = (0) # macro -VFIO_DEVICE_STATE_RUNNING = (1<<0) # macro -VFIO_DEVICE_STATE_SAVING = (1<<1) # macro -VFIO_DEVICE_STATE_RESUMING = (1<<2) # macro -VFIO_DEVICE_STATE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro -# def VFIO_DEVICE_STATE_VALID(state): # macro -# return (state&(1<<2)?(state&((1<<0)|(1<<1)|(1<<2)))==(1<<2):1) -def VFIO_DEVICE_STATE_IS_ERROR(state): # macro - return ((state&((1<<0)|(1<<1)|(1<<2)))==((1<<1)|(1<<2))) -# def VFIO_DEVICE_STATE_SET_ERROR(state): # macro -# return ((state&~((1<<0)|(1<<1)|(1<<2)))|VFIO_DEVICE_SATE_SAVING|(1<<2)) -VFIO_REGION_INFO_CAP_MSIX_MAPPABLE = 3 # macro -VFIO_REGION_INFO_CAP_NVLINK2_SSATGT = 4 # macro -VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD = 5 # macro -VFIO_IRQ_INFO_EVENTFD = (1<<0) # macro -VFIO_IRQ_INFO_MASKABLE = (1<<1) # macro -VFIO_IRQ_INFO_AUTOMASKED = (1<<2) # macro -VFIO_IRQ_INFO_NORESIZE = (1<<3) # macro -VFIO_DEVICE_GET_IRQ_INFO = _IO ( ( ';' ) , 100 + 9 ) # macro (from list) -VFIO_IRQ_SET_DATA_NONE = (1<<0) # macro -VFIO_IRQ_SET_DATA_BOOL = (1<<1) # macro -VFIO_IRQ_SET_DATA_EVENTFD = (1<<2) # macro -VFIO_IRQ_SET_ACTION_MASK = (1<<3) # macro -VFIO_IRQ_SET_ACTION_UNMASK = (1<<4) # macro -VFIO_IRQ_SET_ACTION_TRIGGER = (1<<5) # macro -VFIO_DEVICE_SET_IRQS = _IO ( ( ';' ) , 100 + 10 ) # macro (from list) -VFIO_IRQ_SET_DATA_TYPE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro -VFIO_IRQ_SET_ACTION_TYPE_MASK = ((1<<3)|(1<<4)|(1<<5)) # macro -VFIO_DEVICE_RESET = _IO ( ( ';' ) , 100 + 11 ) # macro (from list) -VFIO_DEVICE_GET_PCI_HOT_RESET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) -VFIO_DEVICE_PCI_HOT_RESET = _IO ( ( ';' ) , 100 + 13 ) # macro (from list) -VFIO_GFX_PLANE_TYPE_PROBE = (1<<0) # macro -VFIO_GFX_PLANE_TYPE_DMABUF = (1<<1) # macro -VFIO_GFX_PLANE_TYPE_REGION = (1<<2) # macro -VFIO_DEVICE_QUERY_GFX_PLANE = _IO ( ( ';' ) , 100 + 14 ) # macro (from list) -VFIO_DEVICE_GET_GFX_DMABUF = _IO ( ( ';' ) , 100 + 15 ) # macro (from list) -VFIO_DEVICE_IOEVENTFD_8 = (1<<0) # macro -VFIO_DEVICE_IOEVENTFD_16 = (1<<1) # macro -VFIO_DEVICE_IOEVENTFD_32 = (1<<2) # macro -VFIO_DEVICE_IOEVENTFD_64 = (1<<3) # macro -VFIO_DEVICE_IOEVENTFD_SIZE_MASK = (0xf) # macro -VFIO_DEVICE_IOEVENTFD = _IO ( ( ';' ) , 100 + 16 ) # macro (from list) -VFIO_DEVICE_FEATURE_MASK = (0xffff) # macro -VFIO_DEVICE_FEATURE_GET = (1<<16) # macro -VFIO_DEVICE_FEATURE_SET = (1<<17) # macro -VFIO_DEVICE_FEATURE_PROBE = (1<<18) # macro -VFIO_DEVICE_FEATURE = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) -VFIO_DEVICE_FEATURE_PCI_VF_TOKEN = (0) # macro -VFIO_IOMMU_INFO_PGSIZES = (1<<0) # macro -VFIO_IOMMU_INFO_CAPS = (1<<1) # macro -VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE = 1 # macro -VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION = 2 # macro -VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL = 3 # macro -VFIO_IOMMU_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) -VFIO_DMA_MAP_FLAG_READ = (1<<0) # macro -VFIO_DMA_MAP_FLAG_WRITE = (1<<1) # macro -VFIO_DMA_MAP_FLAG_VADDR = (1<<2) # macro -VFIO_IOMMU_MAP_DMA = _IO ( ( ';' ) , 100 + 13 ) # macro (from list) -VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP = (1<<0) # macro -VFIO_DMA_UNMAP_FLAG_ALL = (1<<1) # macro -VFIO_DMA_UNMAP_FLAG_VADDR = (1<<2) # macro -VFIO_IOMMU_UNMAP_DMA = _IO ( ( ';' ) , 100 + 14 ) # macro (from list) -VFIO_IOMMU_ENABLE = _IO ( ( ';' ) , 100 + 15 ) # macro (from list) -VFIO_IOMMU_DISABLE = _IO ( ( ';' ) , 100 + 16 ) # macro (from list) -VFIO_IOMMU_DIRTY_PAGES_FLAG_START = (1<<0) # macro -VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP = (1<<1) # macro -VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP = (1<<2) # macro -VFIO_IOMMU_DIRTY_PAGES = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) -VFIO_IOMMU_SPAPR_INFO_DDW = (1<<0) # macro -VFIO_IOMMU_SPAPR_TCE_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list) -VFIO_EEH_PE_DISABLE = 0 # macro -VFIO_EEH_PE_ENABLE = 1 # macro -VFIO_EEH_PE_UNFREEZE_IO = 2 # macro -VFIO_EEH_PE_UNFREEZE_DMA = 3 # macro -VFIO_EEH_PE_GET_STATE = 4 # macro -VFIO_EEH_PE_STATE_NORMAL = 0 # macro -VFIO_EEH_PE_STATE_RESET = 1 # macro -VFIO_EEH_PE_STATE_STOPPED = 2 # macro -VFIO_EEH_PE_STATE_STOPPED_DMA = 4 # macro -VFIO_EEH_PE_STATE_UNAVAIL = 5 # macro -VFIO_EEH_PE_RESET_DEACTIVATE = 5 # macro -VFIO_EEH_PE_RESET_HOT = 6 # macro -VFIO_EEH_PE_RESET_FUNDAMENTAL = 7 # macro -VFIO_EEH_PE_CONFIGURE = 8 # macro -VFIO_EEH_PE_INJECT_ERR = 9 # macro -VFIO_EEH_PE_OP = _IO ( ( ';' ) , 100 + 21 ) # macro (from list) -VFIO_IOMMU_SPAPR_REGISTER_MEMORY = _IO ( ( ';' ) , 100 + 17 ) # macro (from list) -VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY = _IO ( ( ';' ) , 100 + 18 ) # macro (from list) -VFIO_IOMMU_SPAPR_TCE_CREATE = _IO ( ( ';' ) , 100 + 19 ) # macro (from list) -VFIO_IOMMU_SPAPR_TCE_REMOVE = _IO ( ( ';' ) , 100 + 20 ) # macro (from list) -class struct_vfio_info_cap_header(Structure): - pass - -struct_vfio_info_cap_header._pack_ = 1 # source:False +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +class struct_vfio_info_cap_header(Struct): pass +__u16 = ctypes.c_uint16 +__u32 = ctypes.c_uint32 struct_vfio_info_cap_header._fields_ = [ - ('id', ctypes.c_uint16), - ('version', ctypes.c_uint16), - ('next', ctypes.c_uint32), + ('id', ctypes.c_uint16), + ('version', ctypes.c_uint16), + ('next', ctypes.c_uint32), ] - -class struct_vfio_group_status(Structure): - pass - -struct_vfio_group_status._pack_ = 1 # source:False +class struct_vfio_group_status(Struct): pass struct_vfio_group_status._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), ] - -class struct_vfio_device_info(Structure): - pass - -struct_vfio_device_info._pack_ = 1 # source:False +class struct_vfio_device_info(Struct): pass struct_vfio_device_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('num_regions', ctypes.c_uint32), - ('num_irqs', ctypes.c_uint32), - ('cap_offset', ctypes.c_uint32), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('num_regions', ctypes.c_uint32), + ('num_irqs', ctypes.c_uint32), + ('cap_offset', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -class struct_vfio_region_info(Structure): - pass - -struct_vfio_region_info._pack_ = 1 # source:False +class struct_vfio_device_info_cap_pci_atomic_comp(Struct): pass +struct_vfio_device_info_cap_pci_atomic_comp._fields_ = [ + ('header', struct_vfio_info_cap_header), + ('flags', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), +] +class struct_vfio_region_info(Struct): pass +__u64 = ctypes.c_uint64 struct_vfio_region_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('cap_offset', ctypes.c_uint32), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('index', ctypes.c_uint32), + ('cap_offset', ctypes.c_uint32), + ('size', ctypes.c_uint64), + ('offset', ctypes.c_uint64), ] - -class struct_vfio_region_sparse_mmap_area(Structure): - pass - -struct_vfio_region_sparse_mmap_area._pack_ = 1 # source:False +class struct_vfio_region_sparse_mmap_area(Struct): pass struct_vfio_region_sparse_mmap_area._fields_ = [ - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), + ('offset', ctypes.c_uint64), + ('size', ctypes.c_uint64), ] - -class struct_vfio_region_info_cap_sparse_mmap(Structure): - pass - -struct_vfio_region_info_cap_sparse_mmap._pack_ = 1 # source:False +class struct_vfio_region_info_cap_sparse_mmap(Struct): pass struct_vfio_region_info_cap_sparse_mmap._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('nr_areas', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('areas', struct_vfio_region_sparse_mmap_area * 0), + ('header', struct_vfio_info_cap_header), + ('nr_areas', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('areas', (struct_vfio_region_sparse_mmap_area * 0)), ] - -class struct_vfio_region_info_cap_type(Structure): - pass - -struct_vfio_region_info_cap_type._pack_ = 1 # source:False +class struct_vfio_region_info_cap_type(Struct): pass struct_vfio_region_info_cap_type._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('type', ctypes.c_uint32), - ('subtype', ctypes.c_uint32), + ('header', struct_vfio_info_cap_header), + ('type', ctypes.c_uint32), + ('subtype', ctypes.c_uint32), ] - -class struct_vfio_region_gfx_edid(Structure): - pass - -struct_vfio_region_gfx_edid._pack_ = 1 # source:False +class struct_vfio_region_gfx_edid(Struct): pass struct_vfio_region_gfx_edid._fields_ = [ - ('edid_offset', ctypes.c_uint32), - ('edid_max_size', ctypes.c_uint32), - ('edid_size', ctypes.c_uint32), - ('max_xres', ctypes.c_uint32), - ('max_yres', ctypes.c_uint32), - ('link_state', ctypes.c_uint32), + ('edid_offset', ctypes.c_uint32), + ('edid_max_size', ctypes.c_uint32), + ('edid_size', ctypes.c_uint32), + ('max_xres', ctypes.c_uint32), + ('max_yres', ctypes.c_uint32), + ('link_state', ctypes.c_uint32), ] - -class struct_vfio_device_migration_info(Structure): - pass - -struct_vfio_device_migration_info._pack_ = 1 # source:False +class struct_vfio_device_migration_info(Struct): pass struct_vfio_device_migration_info._fields_ = [ - ('device_state', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('pending_bytes', ctypes.c_uint64), - ('data_offset', ctypes.c_uint64), - ('data_size', ctypes.c_uint64), + ('device_state', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('pending_bytes', ctypes.c_uint64), + ('data_offset', ctypes.c_uint64), + ('data_size', ctypes.c_uint64), ] - -class struct_vfio_region_info_cap_nvlink2_ssatgt(Structure): - pass - -struct_vfio_region_info_cap_nvlink2_ssatgt._pack_ = 1 # source:False +class struct_vfio_region_info_cap_nvlink2_ssatgt(Struct): pass struct_vfio_region_info_cap_nvlink2_ssatgt._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('tgt', ctypes.c_uint64), + ('header', struct_vfio_info_cap_header), + ('tgt', ctypes.c_uint64), ] - -class struct_vfio_region_info_cap_nvlink2_lnkspd(Structure): - pass - -struct_vfio_region_info_cap_nvlink2_lnkspd._pack_ = 1 # source:False +class struct_vfio_region_info_cap_nvlink2_lnkspd(Struct): pass struct_vfio_region_info_cap_nvlink2_lnkspd._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('link_speed', ctypes.c_uint32), - ('__pad', ctypes.c_uint32), + ('header', struct_vfio_info_cap_header), + ('link_speed', ctypes.c_uint32), + ('__pad', ctypes.c_uint32), ] - -class struct_vfio_irq_info(Structure): - pass - -struct_vfio_irq_info._pack_ = 1 # source:False +class struct_vfio_irq_info(Struct): pass struct_vfio_irq_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('count', ctypes.c_uint32), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('index', ctypes.c_uint32), + ('count', ctypes.c_uint32), ] - -class struct_vfio_irq_set(Structure): - pass - -struct_vfio_irq_set._pack_ = 1 # source:False +class struct_vfio_irq_set(Struct): pass +__u8 = ctypes.c_ubyte struct_vfio_irq_set._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('index', ctypes.c_uint32), - ('start', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('data', ctypes.c_int * 1), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('index', ctypes.c_uint32), + ('start', ctypes.c_uint32), + ('count', ctypes.c_uint32), + ('data', (ctypes.c_ubyte * 0)), ] +_anonenum0 = CEnum(ctypes.c_uint32) +VFIO_PCI_BAR0_REGION_INDEX = _anonenum0.define('VFIO_PCI_BAR0_REGION_INDEX', 0) +VFIO_PCI_BAR1_REGION_INDEX = _anonenum0.define('VFIO_PCI_BAR1_REGION_INDEX', 1) +VFIO_PCI_BAR2_REGION_INDEX = _anonenum0.define('VFIO_PCI_BAR2_REGION_INDEX', 2) +VFIO_PCI_BAR3_REGION_INDEX = _anonenum0.define('VFIO_PCI_BAR3_REGION_INDEX', 3) +VFIO_PCI_BAR4_REGION_INDEX = _anonenum0.define('VFIO_PCI_BAR4_REGION_INDEX', 4) +VFIO_PCI_BAR5_REGION_INDEX = _anonenum0.define('VFIO_PCI_BAR5_REGION_INDEX', 5) +VFIO_PCI_ROM_REGION_INDEX = _anonenum0.define('VFIO_PCI_ROM_REGION_INDEX', 6) +VFIO_PCI_CONFIG_REGION_INDEX = _anonenum0.define('VFIO_PCI_CONFIG_REGION_INDEX', 7) +VFIO_PCI_VGA_REGION_INDEX = _anonenum0.define('VFIO_PCI_VGA_REGION_INDEX', 8) +VFIO_PCI_NUM_REGIONS = _anonenum0.define('VFIO_PCI_NUM_REGIONS', 9) +_anonenum1 = CEnum(ctypes.c_uint32) +VFIO_PCI_INTX_IRQ_INDEX = _anonenum1.define('VFIO_PCI_INTX_IRQ_INDEX', 0) +VFIO_PCI_MSI_IRQ_INDEX = _anonenum1.define('VFIO_PCI_MSI_IRQ_INDEX', 1) +VFIO_PCI_MSIX_IRQ_INDEX = _anonenum1.define('VFIO_PCI_MSIX_IRQ_INDEX', 2) +VFIO_PCI_ERR_IRQ_INDEX = _anonenum1.define('VFIO_PCI_ERR_IRQ_INDEX', 3) +VFIO_PCI_REQ_IRQ_INDEX = _anonenum1.define('VFIO_PCI_REQ_IRQ_INDEX', 4) +VFIO_PCI_NUM_IRQS = _anonenum1.define('VFIO_PCI_NUM_IRQS', 5) -# values for enumeration 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX' -c__Ea_VFIO_PCI_BAR0_REGION_INDEX__enumvalues = { - 0: 'VFIO_PCI_BAR0_REGION_INDEX', - 1: 'VFIO_PCI_BAR1_REGION_INDEX', - 2: 'VFIO_PCI_BAR2_REGION_INDEX', - 3: 'VFIO_PCI_BAR3_REGION_INDEX', - 4: 'VFIO_PCI_BAR4_REGION_INDEX', - 5: 'VFIO_PCI_BAR5_REGION_INDEX', - 6: 'VFIO_PCI_ROM_REGION_INDEX', - 7: 'VFIO_PCI_CONFIG_REGION_INDEX', - 8: 'VFIO_PCI_VGA_REGION_INDEX', - 9: 'VFIO_PCI_NUM_REGIONS', -} -VFIO_PCI_BAR0_REGION_INDEX = 0 -VFIO_PCI_BAR1_REGION_INDEX = 1 -VFIO_PCI_BAR2_REGION_INDEX = 2 -VFIO_PCI_BAR3_REGION_INDEX = 3 -VFIO_PCI_BAR4_REGION_INDEX = 4 -VFIO_PCI_BAR5_REGION_INDEX = 5 -VFIO_PCI_ROM_REGION_INDEX = 6 -VFIO_PCI_CONFIG_REGION_INDEX = 7 -VFIO_PCI_VGA_REGION_INDEX = 8 -VFIO_PCI_NUM_REGIONS = 9 -c__Ea_VFIO_PCI_BAR0_REGION_INDEX = ctypes.c_uint32 # enum +_anonenum2 = CEnum(ctypes.c_uint32) +VFIO_CCW_CONFIG_REGION_INDEX = _anonenum2.define('VFIO_CCW_CONFIG_REGION_INDEX', 0) +VFIO_CCW_NUM_REGIONS = _anonenum2.define('VFIO_CCW_NUM_REGIONS', 1) -# values for enumeration 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX' -c__Ea_VFIO_PCI_INTX_IRQ_INDEX__enumvalues = { - 0: 'VFIO_PCI_INTX_IRQ_INDEX', - 1: 'VFIO_PCI_MSI_IRQ_INDEX', - 2: 'VFIO_PCI_MSIX_IRQ_INDEX', - 3: 'VFIO_PCI_ERR_IRQ_INDEX', - 4: 'VFIO_PCI_REQ_IRQ_INDEX', - 5: 'VFIO_PCI_NUM_IRQS', -} -VFIO_PCI_INTX_IRQ_INDEX = 0 -VFIO_PCI_MSI_IRQ_INDEX = 1 -VFIO_PCI_MSIX_IRQ_INDEX = 2 -VFIO_PCI_ERR_IRQ_INDEX = 3 -VFIO_PCI_REQ_IRQ_INDEX = 4 -VFIO_PCI_NUM_IRQS = 5 -c__Ea_VFIO_PCI_INTX_IRQ_INDEX = ctypes.c_uint32 # enum +_anonenum3 = CEnum(ctypes.c_uint32) +VFIO_CCW_IO_IRQ_INDEX = _anonenum3.define('VFIO_CCW_IO_IRQ_INDEX', 0) +VFIO_CCW_CRW_IRQ_INDEX = _anonenum3.define('VFIO_CCW_CRW_IRQ_INDEX', 1) +VFIO_CCW_REQ_IRQ_INDEX = _anonenum3.define('VFIO_CCW_REQ_IRQ_INDEX', 2) +VFIO_CCW_NUM_IRQS = _anonenum3.define('VFIO_CCW_NUM_IRQS', 3) -# values for enumeration 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX' -c__Ea_VFIO_CCW_CONFIG_REGION_INDEX__enumvalues = { - 0: 'VFIO_CCW_CONFIG_REGION_INDEX', - 1: 'VFIO_CCW_NUM_REGIONS', -} -VFIO_CCW_CONFIG_REGION_INDEX = 0 -VFIO_CCW_NUM_REGIONS = 1 -c__Ea_VFIO_CCW_CONFIG_REGION_INDEX = ctypes.c_uint32 # enum +_anonenum4 = CEnum(ctypes.c_uint32) +VFIO_AP_REQ_IRQ_INDEX = _anonenum4.define('VFIO_AP_REQ_IRQ_INDEX', 0) +VFIO_AP_NUM_IRQS = _anonenum4.define('VFIO_AP_NUM_IRQS', 1) -# values for enumeration 'c__Ea_VFIO_CCW_IO_IRQ_INDEX' -c__Ea_VFIO_CCW_IO_IRQ_INDEX__enumvalues = { - 0: 'VFIO_CCW_IO_IRQ_INDEX', - 1: 'VFIO_CCW_CRW_IRQ_INDEX', - 2: 'VFIO_CCW_REQ_IRQ_INDEX', - 3: 'VFIO_CCW_NUM_IRQS', -} -VFIO_CCW_IO_IRQ_INDEX = 0 -VFIO_CCW_CRW_IRQ_INDEX = 1 -VFIO_CCW_REQ_IRQ_INDEX = 2 -VFIO_CCW_NUM_IRQS = 3 -c__Ea_VFIO_CCW_IO_IRQ_INDEX = ctypes.c_uint32 # enum -class struct_vfio_pci_dependent_device(Structure): - pass - -struct_vfio_pci_dependent_device._pack_ = 1 # source:False +class struct_vfio_pci_dependent_device(Struct): pass +class struct_vfio_pci_dependent_device_0(ctypes.Union): pass +struct_vfio_pci_dependent_device_0._fields_ = [ + ('group_id', ctypes.c_uint32), + ('devid', ctypes.c_uint32), +] +struct_vfio_pci_dependent_device._anonymous_ = ['_0'] struct_vfio_pci_dependent_device._fields_ = [ - ('group_id', ctypes.c_uint32), - ('segment', ctypes.c_uint16), - ('bus', ctypes.c_ubyte), - ('devfn', ctypes.c_ubyte), + ('_0', struct_vfio_pci_dependent_device_0), + ('segment', ctypes.c_uint16), + ('bus', ctypes.c_ubyte), + ('devfn', ctypes.c_ubyte), ] - -class struct_vfio_pci_hot_reset_info(Structure): - pass - -struct_vfio_pci_hot_reset_info._pack_ = 1 # source:False +class struct_vfio_pci_hot_reset_info(Struct): pass struct_vfio_pci_hot_reset_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('devices', struct_vfio_pci_dependent_device * 0), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('count', ctypes.c_uint32), + ('devices', (struct_vfio_pci_dependent_device * 0)), ] - -class struct_vfio_pci_hot_reset(Structure): - pass - -struct_vfio_pci_hot_reset._pack_ = 1 # source:False +class struct_vfio_pci_hot_reset(Struct): pass +__s32 = ctypes.c_int32 struct_vfio_pci_hot_reset._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('count', ctypes.c_uint32), - ('group_fds', ctypes.c_int32 * 0), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('count', ctypes.c_uint32), + ('group_fds', (ctypes.c_int32 * 0)), ] - -class struct_vfio_device_gfx_plane_info(Structure): - pass - -class union_vfio_device_gfx_plane_info_0(Union): - pass - -union_vfio_device_gfx_plane_info_0._pack_ = 1 # source:False -union_vfio_device_gfx_plane_info_0._fields_ = [ - ('region_index', ctypes.c_uint32), - ('dmabuf_id', ctypes.c_uint32), +class struct_vfio_device_gfx_plane_info(Struct): pass +class struct_vfio_device_gfx_plane_info_0(ctypes.Union): pass +struct_vfio_device_gfx_plane_info_0._fields_ = [ + ('region_index', ctypes.c_uint32), + ('dmabuf_id', ctypes.c_uint32), ] - -struct_vfio_device_gfx_plane_info._pack_ = 1 # source:False -struct_vfio_device_gfx_plane_info._anonymous_ = ('_0',) +struct_vfio_device_gfx_plane_info._anonymous_ = ['_0'] struct_vfio_device_gfx_plane_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('drm_plane_type', ctypes.c_uint32), - ('drm_format', ctypes.c_uint32), - ('drm_format_mod', ctypes.c_uint64), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('stride', ctypes.c_uint32), - ('size', ctypes.c_uint32), - ('x_pos', ctypes.c_uint32), - ('y_pos', ctypes.c_uint32), - ('x_hot', ctypes.c_uint32), - ('y_hot', ctypes.c_uint32), - ('_0', union_vfio_device_gfx_plane_info_0), - ('PADDING_0', ctypes.c_ubyte * 4), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('drm_plane_type', ctypes.c_uint32), + ('drm_format', ctypes.c_uint32), + ('drm_format_mod', ctypes.c_uint64), + ('width', ctypes.c_uint32), + ('height', ctypes.c_uint32), + ('stride', ctypes.c_uint32), + ('size', ctypes.c_uint32), + ('x_pos', ctypes.c_uint32), + ('y_pos', ctypes.c_uint32), + ('x_hot', ctypes.c_uint32), + ('y_hot', ctypes.c_uint32), + ('_0', struct_vfio_device_gfx_plane_info_0), + ('reserved', ctypes.c_uint32), ] - -class struct_vfio_device_ioeventfd(Structure): - pass - -struct_vfio_device_ioeventfd._pack_ = 1 # source:False +class struct_vfio_device_ioeventfd(Struct): pass struct_vfio_device_ioeventfd._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('offset', ctypes.c_uint64), - ('data', ctypes.c_uint64), - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('offset', ctypes.c_uint64), + ('data', ctypes.c_uint64), + ('fd', ctypes.c_int32), + ('reserved', ctypes.c_uint32), ] - -class struct_vfio_device_feature(Structure): - pass - -struct_vfio_device_feature._pack_ = 1 # source:False +class struct_vfio_device_feature(Struct): pass struct_vfio_device_feature._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 0), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('data', (ctypes.c_ubyte * 0)), ] +class struct_vfio_device_bind_iommufd(Struct): pass +struct_vfio_device_bind_iommufd._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('iommufd', ctypes.c_int32), + ('out_devid', ctypes.c_uint32), +] +class struct_vfio_device_attach_iommufd_pt(Struct): pass +struct_vfio_device_attach_iommufd_pt._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('pt_id', ctypes.c_uint32), +] +class struct_vfio_device_detach_iommufd_pt(Struct): pass +struct_vfio_device_detach_iommufd_pt._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), +] +class struct_vfio_device_feature_migration(Struct): pass +struct_vfio_device_feature_migration._fields_ = [ + ('flags', ctypes.c_uint64), +] +class struct_vfio_device_feature_mig_state(Struct): pass +struct_vfio_device_feature_mig_state._fields_ = [ + ('device_state', ctypes.c_uint32), + ('data_fd', ctypes.c_int32), +] +enum_vfio_device_mig_state = CEnum(ctypes.c_uint32) +VFIO_DEVICE_STATE_ERROR = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_ERROR', 0) +VFIO_DEVICE_STATE_STOP = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_STOP', 1) +VFIO_DEVICE_STATE_RUNNING = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_RUNNING', 2) +VFIO_DEVICE_STATE_STOP_COPY = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_STOP_COPY', 3) +VFIO_DEVICE_STATE_RESUMING = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_RESUMING', 4) +VFIO_DEVICE_STATE_RUNNING_P2P = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_RUNNING_P2P', 5) +VFIO_DEVICE_STATE_PRE_COPY = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_PRE_COPY', 6) +VFIO_DEVICE_STATE_PRE_COPY_P2P = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_PRE_COPY_P2P', 7) +VFIO_DEVICE_STATE_NR = enum_vfio_device_mig_state.define('VFIO_DEVICE_STATE_NR', 8) -class struct_vfio_iommu_type1_info(Structure): - pass - -struct_vfio_iommu_type1_info._pack_ = 1 # source:False +class struct_vfio_precopy_info(Struct): pass +struct_vfio_precopy_info._fields_ = [ + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('initial_bytes', ctypes.c_uint64), + ('dirty_bytes', ctypes.c_uint64), +] +class struct_vfio_device_low_power_entry_with_wakeup(Struct): pass +struct_vfio_device_low_power_entry_with_wakeup._fields_ = [ + ('wakeup_eventfd', ctypes.c_int32), + ('reserved', ctypes.c_uint32), +] +class struct_vfio_device_feature_dma_logging_control(Struct): pass +struct_vfio_device_feature_dma_logging_control._fields_ = [ + ('page_size', ctypes.c_uint64), + ('num_ranges', ctypes.c_uint32), + ('__reserved', ctypes.c_uint32), + ('ranges', ctypes.c_uint64), +] +class struct_vfio_device_feature_dma_logging_range(Struct): pass +struct_vfio_device_feature_dma_logging_range._fields_ = [ + ('iova', ctypes.c_uint64), + ('length', ctypes.c_uint64), +] +class struct_vfio_device_feature_dma_logging_report(Struct): pass +struct_vfio_device_feature_dma_logging_report._fields_ = [ + ('iova', ctypes.c_uint64), + ('length', ctypes.c_uint64), + ('page_size', ctypes.c_uint64), + ('bitmap', ctypes.c_uint64), +] +class struct_vfio_device_feature_mig_data_size(Struct): pass +struct_vfio_device_feature_mig_data_size._fields_ = [ + ('stop_copy_length', ctypes.c_uint64), +] +class struct_vfio_device_feature_bus_master(Struct): pass +struct_vfio_device_feature_bus_master._fields_ = [ + ('op', ctypes.c_uint32), +] +class struct_vfio_iommu_type1_info(Struct): pass struct_vfio_iommu_type1_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('iova_pgsizes', ctypes.c_uint64), - ('cap_offset', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('iova_pgsizes', ctypes.c_uint64), + ('cap_offset', ctypes.c_uint32), + ('pad', ctypes.c_uint32), ] - -class struct_vfio_iova_range(Structure): - pass - -struct_vfio_iova_range._pack_ = 1 # source:False +class struct_vfio_iova_range(Struct): pass struct_vfio_iova_range._fields_ = [ - ('start', ctypes.c_uint64), - ('end', ctypes.c_uint64), + ('start', ctypes.c_uint64), + ('end', ctypes.c_uint64), ] - -class struct_vfio_iommu_type1_info_cap_iova_range(Structure): - pass - -struct_vfio_iommu_type1_info_cap_iova_range._pack_ = 1 # source:False +class struct_vfio_iommu_type1_info_cap_iova_range(Struct): pass struct_vfio_iommu_type1_info_cap_iova_range._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('nr_iovas', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('iova_ranges', struct_vfio_iova_range * 0), + ('header', struct_vfio_info_cap_header), + ('nr_iovas', ctypes.c_uint32), + ('reserved', ctypes.c_uint32), + ('iova_ranges', (struct_vfio_iova_range * 0)), ] - -class struct_vfio_iommu_type1_info_cap_migration(Structure): - pass - -struct_vfio_iommu_type1_info_cap_migration._pack_ = 1 # source:False +class struct_vfio_iommu_type1_info_cap_migration(Struct): pass struct_vfio_iommu_type1_info_cap_migration._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pgsize_bitmap', ctypes.c_uint64), - ('max_dirty_bitmap_size', ctypes.c_uint64), + ('header', struct_vfio_info_cap_header), + ('flags', ctypes.c_uint32), + ('pgsize_bitmap', ctypes.c_uint64), + ('max_dirty_bitmap_size', ctypes.c_uint64), ] - -class struct_vfio_iommu_type1_info_dma_avail(Structure): - pass - -struct_vfio_iommu_type1_info_dma_avail._pack_ = 1 # source:False +class struct_vfio_iommu_type1_info_dma_avail(Struct): pass struct_vfio_iommu_type1_info_dma_avail._fields_ = [ - ('header', struct_vfio_info_cap_header), - ('avail', ctypes.c_uint32), + ('header', struct_vfio_info_cap_header), + ('avail', ctypes.c_uint32), ] - -class struct_vfio_iommu_type1_dma_map(Structure): - pass - -struct_vfio_iommu_type1_dma_map._pack_ = 1 # source:False +class struct_vfio_iommu_type1_dma_map(Struct): pass struct_vfio_iommu_type1_dma_map._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaddr', ctypes.c_uint64), - ('iova', ctypes.c_uint64), - ('size', ctypes.c_uint64), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('vaddr', ctypes.c_uint64), + ('iova', ctypes.c_uint64), + ('size', ctypes.c_uint64), ] - -class struct_vfio_bitmap(Structure): - pass - -struct_vfio_bitmap._pack_ = 1 # source:False +class struct_vfio_bitmap(Struct): pass struct_vfio_bitmap._fields_ = [ - ('pgsize', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('data', ctypes.POINTER(ctypes.c_uint64)), + ('pgsize', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('data', ctypes.POINTER(ctypes.c_uint64)), ] - -class struct_vfio_iommu_type1_dma_unmap(Structure): - pass - -struct_vfio_iommu_type1_dma_unmap._pack_ = 1 # source:False +class struct_vfio_iommu_type1_dma_unmap(Struct): pass struct_vfio_iommu_type1_dma_unmap._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('iova', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('data', ctypes.c_ubyte * 0), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('iova', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('data', (ctypes.c_ubyte * 0)), ] - -class struct_vfio_iommu_type1_dirty_bitmap(Structure): - pass - -struct_vfio_iommu_type1_dirty_bitmap._pack_ = 1 # source:False +class struct_vfio_iommu_type1_dirty_bitmap(Struct): pass struct_vfio_iommu_type1_dirty_bitmap._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('data', ctypes.c_ubyte * 0), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('data', (ctypes.c_ubyte * 0)), ] - -class struct_vfio_iommu_type1_dirty_bitmap_get(Structure): - pass - -struct_vfio_iommu_type1_dirty_bitmap_get._pack_ = 1 # source:False +class struct_vfio_iommu_type1_dirty_bitmap_get(Struct): pass struct_vfio_iommu_type1_dirty_bitmap_get._fields_ = [ - ('iova', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('bitmap', struct_vfio_bitmap), + ('iova', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('bitmap', struct_vfio_bitmap), ] - -class struct_vfio_iommu_spapr_tce_ddw_info(Structure): - pass - -struct_vfio_iommu_spapr_tce_ddw_info._pack_ = 1 # source:False +class struct_vfio_iommu_spapr_tce_ddw_info(Struct): pass struct_vfio_iommu_spapr_tce_ddw_info._fields_ = [ - ('pgsizes', ctypes.c_uint64), - ('max_dynamic_windows_supported', ctypes.c_uint32), - ('levels', ctypes.c_uint32), + ('pgsizes', ctypes.c_uint64), + ('max_dynamic_windows_supported', ctypes.c_uint32), + ('levels', ctypes.c_uint32), ] - -class struct_vfio_iommu_spapr_tce_info(Structure): - pass - -struct_vfio_iommu_spapr_tce_info._pack_ = 1 # source:False +class struct_vfio_iommu_spapr_tce_info(Struct): pass struct_vfio_iommu_spapr_tce_info._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('dma32_window_start', ctypes.c_uint32), - ('dma32_window_size', ctypes.c_uint32), - ('ddw', struct_vfio_iommu_spapr_tce_ddw_info), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('dma32_window_start', ctypes.c_uint32), + ('dma32_window_size', ctypes.c_uint32), + ('ddw', struct_vfio_iommu_spapr_tce_ddw_info), ] - -class struct_vfio_eeh_pe_err(Structure): - pass - -struct_vfio_eeh_pe_err._pack_ = 1 # source:False +class struct_vfio_eeh_pe_err(Struct): pass struct_vfio_eeh_pe_err._fields_ = [ - ('type', ctypes.c_uint32), - ('func', ctypes.c_uint32), - ('addr', ctypes.c_uint64), - ('mask', ctypes.c_uint64), + ('type', ctypes.c_uint32), + ('func', ctypes.c_uint32), + ('addr', ctypes.c_uint64), + ('mask', ctypes.c_uint64), ] - -class struct_vfio_eeh_pe_op(Structure): - pass - -class union_vfio_eeh_pe_op_0(Union): - _pack_ = 1 # source:False - _fields_ = [ - ('err', struct_vfio_eeh_pe_err), - ] - -struct_vfio_eeh_pe_op._pack_ = 1 # source:False -struct_vfio_eeh_pe_op._anonymous_ = ('_0',) +class struct_vfio_eeh_pe_op(Struct): pass +class struct_vfio_eeh_pe_op_0(ctypes.Union): pass +struct_vfio_eeh_pe_op_0._fields_ = [ + ('err', struct_vfio_eeh_pe_err), +] +struct_vfio_eeh_pe_op._anonymous_ = ['_0'] struct_vfio_eeh_pe_op._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('op', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_0', union_vfio_eeh_pe_op_0), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('op', ctypes.c_uint32), + ('_0', struct_vfio_eeh_pe_op_0), ] - -class struct_vfio_iommu_spapr_register_memory(Structure): - pass - -struct_vfio_iommu_spapr_register_memory._pack_ = 1 # source:False +class struct_vfio_iommu_spapr_register_memory(Struct): pass struct_vfio_iommu_spapr_register_memory._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('vaddr', ctypes.c_uint64), - ('size', ctypes.c_uint64), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('vaddr', ctypes.c_uint64), + ('size', ctypes.c_uint64), ] - -class struct_vfio_iommu_spapr_tce_create(Structure): - pass - -struct_vfio_iommu_spapr_tce_create._pack_ = 1 # source:False +class struct_vfio_iommu_spapr_tce_create(Struct): pass struct_vfio_iommu_spapr_tce_create._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('page_shift', ctypes.c_uint32), - ('__resv1', ctypes.c_uint32), - ('window_size', ctypes.c_uint64), - ('levels', ctypes.c_uint32), - ('__resv2', ctypes.c_uint32), - ('start_addr', ctypes.c_uint64), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('page_shift', ctypes.c_uint32), + ('__resv1', ctypes.c_uint32), + ('window_size', ctypes.c_uint64), + ('levels', ctypes.c_uint32), + ('__resv2', ctypes.c_uint32), + ('start_addr', ctypes.c_uint64), ] - -class struct_vfio_iommu_spapr_tce_remove(Structure): - pass - -struct_vfio_iommu_spapr_tce_remove._pack_ = 1 # source:False +class struct_vfio_iommu_spapr_tce_remove(Struct): pass struct_vfio_iommu_spapr_tce_remove._fields_ = [ - ('argsz', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('start_addr', ctypes.c_uint64), + ('argsz', ctypes.c_uint32), + ('flags', ctypes.c_uint32), + ('start_addr', ctypes.c_uint64), ] - -__all__ = \ - ['VFIO_API_VERSION', 'VFIO_BASE', 'VFIO_CCW_CONFIG_REGION_INDEX', - 'VFIO_CCW_CRW_IRQ_INDEX', 'VFIO_CCW_IO_IRQ_INDEX', - 'VFIO_CCW_NUM_IRQS', 'VFIO_CCW_NUM_REGIONS', - 'VFIO_CCW_REQ_IRQ_INDEX', 'VFIO_DEVICE_API_AMBA_STRING', - 'VFIO_DEVICE_API_AP_STRING', 'VFIO_DEVICE_API_CCW_STRING', - 'VFIO_DEVICE_API_PCI_STRING', 'VFIO_DEVICE_API_PLATFORM_STRING', - 'VFIO_DEVICE_FEATURE_GET', 'VFIO_DEVICE_FEATURE_MASK', - 'VFIO_DEVICE_FEATURE_PCI_VF_TOKEN', 'VFIO_DEVICE_FEATURE_PROBE', - 'VFIO_DEVICE_FEATURE_SET', 'VFIO_DEVICE_FLAGS_AMBA', - 'VFIO_DEVICE_FLAGS_AP', 'VFIO_DEVICE_FLAGS_CAPS', - 'VFIO_DEVICE_FLAGS_CCW', 'VFIO_DEVICE_FLAGS_FSL_MC', - 'VFIO_DEVICE_FLAGS_PCI', 'VFIO_DEVICE_FLAGS_PLATFORM', - 'VFIO_DEVICE_FLAGS_RESET', 'VFIO_DEVICE_GFX_LINK_STATE_DOWN', - 'VFIO_DEVICE_GFX_LINK_STATE_UP', 'VFIO_DEVICE_INFO_CAP_ZPCI_BASE', - 'VFIO_DEVICE_INFO_CAP_ZPCI_GROUP', - 'VFIO_DEVICE_INFO_CAP_ZPCI_PFIP', - 'VFIO_DEVICE_INFO_CAP_ZPCI_UTIL', 'VFIO_DEVICE_IOEVENTFD_16', - 'VFIO_DEVICE_IOEVENTFD_32', 'VFIO_DEVICE_IOEVENTFD_64', - 'VFIO_DEVICE_IOEVENTFD_8', 'VFIO_DEVICE_IOEVENTFD_SIZE_MASK', - 'VFIO_DEVICE_STATE_MASK', 'VFIO_DEVICE_STATE_RESUMING', - 'VFIO_DEVICE_STATE_RUNNING', 'VFIO_DEVICE_STATE_SAVING', - 'VFIO_DEVICE_STATE_STOP', 'VFIO_DMA_CC_IOMMU', - 'VFIO_DMA_MAP_FLAG_READ', 'VFIO_DMA_MAP_FLAG_VADDR', - 'VFIO_DMA_MAP_FLAG_WRITE', 'VFIO_DMA_UNMAP_FLAG_ALL', - 'VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP', - 'VFIO_DMA_UNMAP_FLAG_VADDR', 'VFIO_EEH', 'VFIO_EEH_PE_CONFIGURE', - 'VFIO_EEH_PE_DISABLE', 'VFIO_EEH_PE_ENABLE', - 'VFIO_EEH_PE_GET_STATE', 'VFIO_EEH_PE_INJECT_ERR', - 'VFIO_EEH_PE_RESET_DEACTIVATE', 'VFIO_EEH_PE_RESET_FUNDAMENTAL', - 'VFIO_EEH_PE_RESET_HOT', 'VFIO_EEH_PE_STATE_NORMAL', - 'VFIO_EEH_PE_STATE_RESET', 'VFIO_EEH_PE_STATE_STOPPED', - 'VFIO_EEH_PE_STATE_STOPPED_DMA', 'VFIO_EEH_PE_STATE_UNAVAIL', - 'VFIO_EEH_PE_UNFREEZE_DMA', 'VFIO_EEH_PE_UNFREEZE_IO', - 'VFIO_GFX_PLANE_TYPE_DMABUF', 'VFIO_GFX_PLANE_TYPE_PROBE', - 'VFIO_GFX_PLANE_TYPE_REGION', 'VFIO_GROUP_FLAGS_CONTAINER_SET', - 'VFIO_GROUP_FLAGS_VIABLE', 'VFIO_H', - 'VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP', - 'VFIO_IOMMU_DIRTY_PAGES_FLAG_START', - 'VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP', 'VFIO_IOMMU_INFO_CAPS', - 'VFIO_IOMMU_INFO_PGSIZES', 'VFIO_IOMMU_SPAPR_INFO_DDW', - 'VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE', - 'VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION', - 'VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL', 'VFIO_IRQ_INFO_AUTOMASKED', - 'VFIO_IRQ_INFO_EVENTFD', 'VFIO_IRQ_INFO_MASKABLE', - 'VFIO_IRQ_INFO_NORESIZE', 'VFIO_IRQ_SET_ACTION_MASK', - 'VFIO_IRQ_SET_ACTION_TRIGGER', 'VFIO_IRQ_SET_ACTION_TYPE_MASK', - 'VFIO_IRQ_SET_ACTION_UNMASK', 'VFIO_IRQ_SET_DATA_BOOL', - 'VFIO_IRQ_SET_DATA_EVENTFD', 'VFIO_IRQ_SET_DATA_NONE', - 'VFIO_IRQ_SET_DATA_TYPE_MASK', 'VFIO_NOIOMMU_IOMMU', - 'VFIO_PCI_BAR0_REGION_INDEX', 'VFIO_PCI_BAR1_REGION_INDEX', - 'VFIO_PCI_BAR2_REGION_INDEX', 'VFIO_PCI_BAR3_REGION_INDEX', - 'VFIO_PCI_BAR4_REGION_INDEX', 'VFIO_PCI_BAR5_REGION_INDEX', - 'VFIO_PCI_CONFIG_REGION_INDEX', 'VFIO_PCI_ERR_IRQ_INDEX', - 'VFIO_PCI_INTX_IRQ_INDEX', 'VFIO_PCI_MSIX_IRQ_INDEX', - 'VFIO_PCI_MSI_IRQ_INDEX', 'VFIO_PCI_NUM_IRQS', - 'VFIO_PCI_NUM_REGIONS', 'VFIO_PCI_REQ_IRQ_INDEX', - 'VFIO_PCI_ROM_REGION_INDEX', 'VFIO_PCI_VGA_REGION_INDEX', - 'VFIO_REGION_INFO_CAP_MSIX_MAPPABLE', - 'VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD', - 'VFIO_REGION_INFO_CAP_NVLINK2_SSATGT', - 'VFIO_REGION_INFO_CAP_SPARSE_MMAP', 'VFIO_REGION_INFO_CAP_TYPE', - 'VFIO_REGION_INFO_FLAG_CAPS', 'VFIO_REGION_INFO_FLAG_MMAP', - 'VFIO_REGION_INFO_FLAG_READ', 'VFIO_REGION_INFO_FLAG_WRITE', - 'VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD', - 'VFIO_REGION_SUBTYPE_CCW_CRW', 'VFIO_REGION_SUBTYPE_CCW_SCHIB', - 'VFIO_REGION_SUBTYPE_GFX_EDID', - 'VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD', - 'VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG', - 'VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG', - 'VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION', - 'VFIO_REGION_SUBTYPE_MIGRATION', - 'VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM', 'VFIO_REGION_TYPE_CCW', - 'VFIO_REGION_TYPE_GFX', 'VFIO_REGION_TYPE_MIGRATION', - 'VFIO_REGION_TYPE_PCI_VENDOR_MASK', - 'VFIO_REGION_TYPE_PCI_VENDOR_TYPE', 'VFIO_SPAPR_TCE_IOMMU', - 'VFIO_SPAPR_TCE_v2_IOMMU', 'VFIO_TYPE', 'VFIO_TYPE1_IOMMU', - 'VFIO_TYPE1_NESTING_IOMMU', 'VFIO_TYPE1v2_IOMMU', - 'VFIO_UNMAP_ALL', 'VFIO_UPDATE_VADDR', '_IO', '_IOR', '_IOW', - '_IOWR', 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX', - 'c__Ea_VFIO_CCW_IO_IRQ_INDEX', 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX', - 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX', 'struct_vfio_bitmap', - 'struct_vfio_device_feature', 'struct_vfio_device_gfx_plane_info', - 'struct_vfio_device_info', 'struct_vfio_device_ioeventfd', - 'struct_vfio_device_migration_info', 'struct_vfio_eeh_pe_err', - 'struct_vfio_eeh_pe_op', 'struct_vfio_group_status', - 'struct_vfio_info_cap_header', - 'struct_vfio_iommu_spapr_register_memory', - 'struct_vfio_iommu_spapr_tce_create', - 'struct_vfio_iommu_spapr_tce_ddw_info', - 'struct_vfio_iommu_spapr_tce_info', - 'struct_vfio_iommu_spapr_tce_remove', - 'struct_vfio_iommu_type1_dirty_bitmap', - 'struct_vfio_iommu_type1_dirty_bitmap_get', - 'struct_vfio_iommu_type1_dma_map', - 'struct_vfio_iommu_type1_dma_unmap', - 'struct_vfio_iommu_type1_info', - 'struct_vfio_iommu_type1_info_cap_iova_range', - 'struct_vfio_iommu_type1_info_cap_migration', - 'struct_vfio_iommu_type1_info_dma_avail', - 'struct_vfio_iova_range', 'struct_vfio_irq_info', - 'struct_vfio_irq_set', 'struct_vfio_pci_dependent_device', - 'struct_vfio_pci_hot_reset', 'struct_vfio_pci_hot_reset_info', - 'struct_vfio_region_gfx_edid', 'struct_vfio_region_info', - 'struct_vfio_region_info_cap_nvlink2_lnkspd', - 'struct_vfio_region_info_cap_nvlink2_ssatgt', - 'struct_vfio_region_info_cap_sparse_mmap', - 'struct_vfio_region_info_cap_type', - 'struct_vfio_region_sparse_mmap_area', - 'union_vfio_device_gfx_plane_info_0', 'union_vfio_eeh_pe_op_0'] +VFIO_API_VERSION = 0 +VFIO_TYPE1_IOMMU = 1 +VFIO_SPAPR_TCE_IOMMU = 2 +VFIO_TYPE1v2_IOMMU = 3 +VFIO_DMA_CC_IOMMU = 4 +VFIO_EEH = 5 +VFIO_TYPE1_NESTING_IOMMU = 6 +VFIO_SPAPR_TCE_v2_IOMMU = 7 +VFIO_NOIOMMU_IOMMU = 8 +VFIO_UNMAP_ALL = 9 +VFIO_UPDATE_VADDR = 10 +VFIO_TYPE = (';') +VFIO_BASE = 100 +VFIO_GET_API_VERSION = _IO(VFIO_TYPE, VFIO_BASE + 0) +VFIO_CHECK_EXTENSION = _IO(VFIO_TYPE, VFIO_BASE + 1) +VFIO_SET_IOMMU = _IO(VFIO_TYPE, VFIO_BASE + 2) +VFIO_GROUP_FLAGS_VIABLE = (1 << 0) +VFIO_GROUP_FLAGS_CONTAINER_SET = (1 << 1) +VFIO_GROUP_GET_STATUS = _IO(VFIO_TYPE, VFIO_BASE + 3) +VFIO_GROUP_SET_CONTAINER = _IO(VFIO_TYPE, VFIO_BASE + 4) +VFIO_GROUP_UNSET_CONTAINER = _IO(VFIO_TYPE, VFIO_BASE + 5) +VFIO_GROUP_GET_DEVICE_FD = _IO(VFIO_TYPE, VFIO_BASE + 6) +VFIO_DEVICE_FLAGS_RESET = (1 << 0) +VFIO_DEVICE_FLAGS_PCI = (1 << 1) +VFIO_DEVICE_FLAGS_PLATFORM = (1 << 2) +VFIO_DEVICE_FLAGS_AMBA = (1 << 3) +VFIO_DEVICE_FLAGS_CCW = (1 << 4) +VFIO_DEVICE_FLAGS_AP = (1 << 5) +VFIO_DEVICE_FLAGS_FSL_MC = (1 << 6) +VFIO_DEVICE_FLAGS_CAPS = (1 << 7) +VFIO_DEVICE_FLAGS_CDX = (1 << 8) +VFIO_DEVICE_GET_INFO = _IO(VFIO_TYPE, VFIO_BASE + 7) +VFIO_DEVICE_API_PCI_STRING = "vfio-pci" +VFIO_DEVICE_API_PLATFORM_STRING = "vfio-platform" +VFIO_DEVICE_API_AMBA_STRING = "vfio-amba" +VFIO_DEVICE_API_CCW_STRING = "vfio-ccw" +VFIO_DEVICE_API_AP_STRING = "vfio-ap" +VFIO_DEVICE_INFO_CAP_ZPCI_BASE = 1 +VFIO_DEVICE_INFO_CAP_ZPCI_GROUP = 2 +VFIO_DEVICE_INFO_CAP_ZPCI_UTIL = 3 +VFIO_DEVICE_INFO_CAP_ZPCI_PFIP = 4 +VFIO_DEVICE_INFO_CAP_PCI_ATOMIC_COMP = 5 +VFIO_PCI_ATOMIC_COMP32 = (1 << 0) +VFIO_PCI_ATOMIC_COMP64 = (1 << 1) +VFIO_PCI_ATOMIC_COMP128 = (1 << 2) +VFIO_REGION_INFO_FLAG_READ = (1 << 0) +VFIO_REGION_INFO_FLAG_WRITE = (1 << 1) +VFIO_REGION_INFO_FLAG_MMAP = (1 << 2) +VFIO_REGION_INFO_FLAG_CAPS = (1 << 3) +VFIO_DEVICE_GET_REGION_INFO = _IO(VFIO_TYPE, VFIO_BASE + 8) +VFIO_REGION_INFO_CAP_SPARSE_MMAP = 1 +VFIO_REGION_INFO_CAP_TYPE = 2 +VFIO_REGION_TYPE_PCI_VENDOR_TYPE = (1 << 31) +VFIO_REGION_TYPE_PCI_VENDOR_MASK = (0xffff) +VFIO_REGION_TYPE_GFX = (1) +VFIO_REGION_TYPE_CCW = (2) +VFIO_REGION_TYPE_MIGRATION_DEPRECATED = (3) +VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION = (1) +VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG = (2) +VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG = (3) +VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM = (1) +VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD = (1) +VFIO_REGION_SUBTYPE_GFX_EDID = (1) +VFIO_DEVICE_GFX_LINK_STATE_UP = 1 +VFIO_DEVICE_GFX_LINK_STATE_DOWN = 2 +VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD = (1) +VFIO_REGION_SUBTYPE_CCW_SCHIB = (2) +VFIO_REGION_SUBTYPE_CCW_CRW = (3) +VFIO_REGION_SUBTYPE_MIGRATION_DEPRECATED = (1) +VFIO_DEVICE_STATE_V1_STOP = (0) +VFIO_DEVICE_STATE_V1_RUNNING = (1 << 0) +VFIO_DEVICE_STATE_V1_SAVING = (1 << 1) +VFIO_DEVICE_STATE_V1_RESUMING = (1 << 2) +VFIO_DEVICE_STATE_MASK = (VFIO_DEVICE_STATE_V1_RUNNING | VFIO_DEVICE_STATE_V1_SAVING | VFIO_DEVICE_STATE_V1_RESUMING) +VFIO_DEVICE_STATE_IS_ERROR = lambda state: ((state & VFIO_DEVICE_STATE_MASK) == (VFIO_DEVICE_STATE_V1_SAVING | VFIO_DEVICE_STATE_V1_RESUMING)) +VFIO_DEVICE_STATE_SET_ERROR = lambda state: ((state & ~VFIO_DEVICE_STATE_MASK) | VFIO_DEVICE_STATE_V1_SAVING | VFIO_DEVICE_STATE_V1_RESUMING) +VFIO_REGION_INFO_CAP_MSIX_MAPPABLE = 3 +VFIO_REGION_INFO_CAP_NVLINK2_SSATGT = 4 +VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD = 5 +VFIO_IRQ_INFO_EVENTFD = (1 << 0) +VFIO_IRQ_INFO_MASKABLE = (1 << 1) +VFIO_IRQ_INFO_AUTOMASKED = (1 << 2) +VFIO_IRQ_INFO_NORESIZE = (1 << 3) +VFIO_DEVICE_GET_IRQ_INFO = _IO(VFIO_TYPE, VFIO_BASE + 9) +VFIO_IRQ_SET_DATA_NONE = (1 << 0) +VFIO_IRQ_SET_DATA_BOOL = (1 << 1) +VFIO_IRQ_SET_DATA_EVENTFD = (1 << 2) +VFIO_IRQ_SET_ACTION_MASK = (1 << 3) +VFIO_IRQ_SET_ACTION_UNMASK = (1 << 4) +VFIO_IRQ_SET_ACTION_TRIGGER = (1 << 5) +VFIO_DEVICE_SET_IRQS = _IO(VFIO_TYPE, VFIO_BASE + 10) +VFIO_IRQ_SET_DATA_TYPE_MASK = (VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_DATA_BOOL | VFIO_IRQ_SET_DATA_EVENTFD) +VFIO_IRQ_SET_ACTION_TYPE_MASK = (VFIO_IRQ_SET_ACTION_MASK | VFIO_IRQ_SET_ACTION_UNMASK | VFIO_IRQ_SET_ACTION_TRIGGER) +VFIO_DEVICE_RESET = _IO(VFIO_TYPE, VFIO_BASE + 11) +VFIO_PCI_DEVID_OWNED = 0 +VFIO_PCI_DEVID_NOT_OWNED = -1 +VFIO_PCI_HOT_RESET_FLAG_DEV_ID = (1 << 0) +VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED = (1 << 1) +VFIO_DEVICE_GET_PCI_HOT_RESET_INFO = _IO(VFIO_TYPE, VFIO_BASE + 12) +VFIO_DEVICE_PCI_HOT_RESET = _IO(VFIO_TYPE, VFIO_BASE + 13) +VFIO_GFX_PLANE_TYPE_PROBE = (1 << 0) +VFIO_GFX_PLANE_TYPE_DMABUF = (1 << 1) +VFIO_GFX_PLANE_TYPE_REGION = (1 << 2) +VFIO_DEVICE_QUERY_GFX_PLANE = _IO(VFIO_TYPE, VFIO_BASE + 14) +VFIO_DEVICE_GET_GFX_DMABUF = _IO(VFIO_TYPE, VFIO_BASE + 15) +VFIO_DEVICE_IOEVENTFD_8 = (1 << 0) +VFIO_DEVICE_IOEVENTFD_16 = (1 << 1) +VFIO_DEVICE_IOEVENTFD_32 = (1 << 2) +VFIO_DEVICE_IOEVENTFD_64 = (1 << 3) +VFIO_DEVICE_IOEVENTFD_SIZE_MASK = (0xf) +VFIO_DEVICE_IOEVENTFD = _IO(VFIO_TYPE, VFIO_BASE + 16) +VFIO_DEVICE_FEATURE_MASK = (0xffff) +VFIO_DEVICE_FEATURE_GET = (1 << 16) +VFIO_DEVICE_FEATURE_SET = (1 << 17) +VFIO_DEVICE_FEATURE_PROBE = (1 << 18) +VFIO_DEVICE_FEATURE = _IO(VFIO_TYPE, VFIO_BASE + 17) +VFIO_DEVICE_BIND_IOMMUFD = _IO(VFIO_TYPE, VFIO_BASE + 18) +VFIO_DEVICE_ATTACH_IOMMUFD_PT = _IO(VFIO_TYPE, VFIO_BASE + 19) +VFIO_DEVICE_DETACH_IOMMUFD_PT = _IO(VFIO_TYPE, VFIO_BASE + 20) +VFIO_DEVICE_FEATURE_PCI_VF_TOKEN = (0) +VFIO_MIGRATION_STOP_COPY = (1 << 0) +VFIO_MIGRATION_P2P = (1 << 1) +VFIO_MIGRATION_PRE_COPY = (1 << 2) +VFIO_DEVICE_FEATURE_MIGRATION = 1 +VFIO_DEVICE_FEATURE_MIG_DEVICE_STATE = 2 +VFIO_MIG_GET_PRECOPY_INFO = _IO(VFIO_TYPE, VFIO_BASE + 21) +VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY = 3 +VFIO_DEVICE_FEATURE_LOW_POWER_ENTRY_WITH_WAKEUP = 4 +VFIO_DEVICE_FEATURE_LOW_POWER_EXIT = 5 +VFIO_DEVICE_FEATURE_DMA_LOGGING_START = 6 +VFIO_DEVICE_FEATURE_DMA_LOGGING_STOP = 7 +VFIO_DEVICE_FEATURE_DMA_LOGGING_REPORT = 8 +VFIO_DEVICE_FEATURE_MIG_DATA_SIZE = 9 +VFIO_DEVICE_FEATURE_CLEAR_MASTER = 0 +VFIO_DEVICE_FEATURE_SET_MASTER = 1 +VFIO_DEVICE_FEATURE_BUS_MASTER = 10 +VFIO_IOMMU_INFO_PGSIZES = (1 << 0) +VFIO_IOMMU_INFO_CAPS = (1 << 1) +VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE = 1 +VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION = 2 +VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL = 3 +VFIO_IOMMU_GET_INFO = _IO(VFIO_TYPE, VFIO_BASE + 12) +VFIO_DMA_MAP_FLAG_READ = (1 << 0) +VFIO_DMA_MAP_FLAG_WRITE = (1 << 1) +VFIO_DMA_MAP_FLAG_VADDR = (1 << 2) +VFIO_IOMMU_MAP_DMA = _IO(VFIO_TYPE, VFIO_BASE + 13) +VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP = (1 << 0) +VFIO_DMA_UNMAP_FLAG_ALL = (1 << 1) +VFIO_DMA_UNMAP_FLAG_VADDR = (1 << 2) +VFIO_IOMMU_UNMAP_DMA = _IO(VFIO_TYPE, VFIO_BASE + 14) +VFIO_IOMMU_ENABLE = _IO(VFIO_TYPE, VFIO_BASE + 15) +VFIO_IOMMU_DISABLE = _IO(VFIO_TYPE, VFIO_BASE + 16) +VFIO_IOMMU_DIRTY_PAGES_FLAG_START = (1 << 0) +VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP = (1 << 1) +VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP = (1 << 2) +VFIO_IOMMU_DIRTY_PAGES = _IO(VFIO_TYPE, VFIO_BASE + 17) +VFIO_IOMMU_SPAPR_INFO_DDW = (1 << 0) +VFIO_IOMMU_SPAPR_TCE_GET_INFO = _IO(VFIO_TYPE, VFIO_BASE + 12) +VFIO_EEH_PE_DISABLE = 0 +VFIO_EEH_PE_ENABLE = 1 +VFIO_EEH_PE_UNFREEZE_IO = 2 +VFIO_EEH_PE_UNFREEZE_DMA = 3 +VFIO_EEH_PE_GET_STATE = 4 +VFIO_EEH_PE_STATE_NORMAL = 0 +VFIO_EEH_PE_STATE_RESET = 1 +VFIO_EEH_PE_STATE_STOPPED = 2 +VFIO_EEH_PE_STATE_STOPPED_DMA = 4 +VFIO_EEH_PE_STATE_UNAVAIL = 5 +VFIO_EEH_PE_RESET_DEACTIVATE = 5 +VFIO_EEH_PE_RESET_HOT = 6 +VFIO_EEH_PE_RESET_FUNDAMENTAL = 7 +VFIO_EEH_PE_CONFIGURE = 8 +VFIO_EEH_PE_INJECT_ERR = 9 +VFIO_EEH_PE_OP = _IO(VFIO_TYPE, VFIO_BASE + 21) +VFIO_IOMMU_SPAPR_REGISTER_MEMORY = _IO(VFIO_TYPE, VFIO_BASE + 17) +VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY = _IO(VFIO_TYPE, VFIO_BASE + 18) +VFIO_IOMMU_SPAPR_TCE_CREATE = _IO(VFIO_TYPE, VFIO_BASE + 19) +VFIO_IOMMU_SPAPR_TCE_REMOVE = _IO(VFIO_TYPE, VFIO_BASE + 20) \ No newline at end of file diff --git a/tinygrad/runtime/autogen/webgpu.py b/tinygrad/runtime/autogen/webgpu.py index 7edbb99d7c..79ef194a47 100644 --- a/tinygrad/runtime/autogen/webgpu.py +++ b/tinygrad/runtime/autogen/webgpu.py @@ -1,3964 +1,2264 @@ # mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, tinygrad.runtime.support.webgpu as webgpu_support - - -class AsDictMixin: - import sys - if sys.version_info >= (3, 14): _layout_ = 'ms' - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['webgpu'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['webgpu'] = ctypes.CDLL(webgpu_support.WEBGPU_PATH) # ctypes.CDLL('webgpu') - +import ctypes +from tinygrad.helpers import unwrap +from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR +from tinygrad.runtime.support.webgpu import WEBGPU_PATH +def dll(): + try: return ctypes.CDLL(unwrap(WEBGPU_PATH)) + except: pass + return None +dll = dll() WGPUFlags = ctypes.c_uint64 WGPUBool = ctypes.c_uint32 -class struct_WGPUAdapterImpl(Structure): - pass - +class struct_WGPUAdapterImpl(Struct): pass WGPUAdapter = ctypes.POINTER(struct_WGPUAdapterImpl) -class struct_WGPUBindGroupImpl(Structure): - pass - +class struct_WGPUBindGroupImpl(Struct): pass WGPUBindGroup = ctypes.POINTER(struct_WGPUBindGroupImpl) -class struct_WGPUBindGroupLayoutImpl(Structure): - pass - +class struct_WGPUBindGroupLayoutImpl(Struct): pass WGPUBindGroupLayout = ctypes.POINTER(struct_WGPUBindGroupLayoutImpl) -class struct_WGPUBufferImpl(Structure): - pass - +class struct_WGPUBufferImpl(Struct): pass WGPUBuffer = ctypes.POINTER(struct_WGPUBufferImpl) -class struct_WGPUCommandBufferImpl(Structure): - pass - +class struct_WGPUCommandBufferImpl(Struct): pass WGPUCommandBuffer = ctypes.POINTER(struct_WGPUCommandBufferImpl) -class struct_WGPUCommandEncoderImpl(Structure): - pass - +class struct_WGPUCommandEncoderImpl(Struct): pass WGPUCommandEncoder = ctypes.POINTER(struct_WGPUCommandEncoderImpl) -class struct_WGPUComputePassEncoderImpl(Structure): - pass - +class struct_WGPUComputePassEncoderImpl(Struct): pass WGPUComputePassEncoder = ctypes.POINTER(struct_WGPUComputePassEncoderImpl) -class struct_WGPUComputePipelineImpl(Structure): - pass - +class struct_WGPUComputePipelineImpl(Struct): pass WGPUComputePipeline = ctypes.POINTER(struct_WGPUComputePipelineImpl) -class struct_WGPUDeviceImpl(Structure): - pass - +class struct_WGPUDeviceImpl(Struct): pass WGPUDevice = ctypes.POINTER(struct_WGPUDeviceImpl) -class struct_WGPUExternalTextureImpl(Structure): - pass - +class struct_WGPUExternalTextureImpl(Struct): pass WGPUExternalTexture = ctypes.POINTER(struct_WGPUExternalTextureImpl) -class struct_WGPUInstanceImpl(Structure): - pass - +class struct_WGPUInstanceImpl(Struct): pass WGPUInstance = ctypes.POINTER(struct_WGPUInstanceImpl) -class struct_WGPUPipelineLayoutImpl(Structure): - pass - +class struct_WGPUPipelineLayoutImpl(Struct): pass WGPUPipelineLayout = ctypes.POINTER(struct_WGPUPipelineLayoutImpl) -class struct_WGPUQuerySetImpl(Structure): - pass - +class struct_WGPUQuerySetImpl(Struct): pass WGPUQuerySet = ctypes.POINTER(struct_WGPUQuerySetImpl) -class struct_WGPUQueueImpl(Structure): - pass - +class struct_WGPUQueueImpl(Struct): pass WGPUQueue = ctypes.POINTER(struct_WGPUQueueImpl) -class struct_WGPURenderBundleImpl(Structure): - pass - +class struct_WGPURenderBundleImpl(Struct): pass WGPURenderBundle = ctypes.POINTER(struct_WGPURenderBundleImpl) -class struct_WGPURenderBundleEncoderImpl(Structure): - pass - +class struct_WGPURenderBundleEncoderImpl(Struct): pass WGPURenderBundleEncoder = ctypes.POINTER(struct_WGPURenderBundleEncoderImpl) -class struct_WGPURenderPassEncoderImpl(Structure): - pass - +class struct_WGPURenderPassEncoderImpl(Struct): pass WGPURenderPassEncoder = ctypes.POINTER(struct_WGPURenderPassEncoderImpl) -class struct_WGPURenderPipelineImpl(Structure): - pass - +class struct_WGPURenderPipelineImpl(Struct): pass WGPURenderPipeline = ctypes.POINTER(struct_WGPURenderPipelineImpl) -class struct_WGPUSamplerImpl(Structure): - pass - +class struct_WGPUSamplerImpl(Struct): pass WGPUSampler = ctypes.POINTER(struct_WGPUSamplerImpl) -class struct_WGPUShaderModuleImpl(Structure): - pass - +class struct_WGPUShaderModuleImpl(Struct): pass WGPUShaderModule = ctypes.POINTER(struct_WGPUShaderModuleImpl) -class struct_WGPUSharedBufferMemoryImpl(Structure): - pass - +class struct_WGPUSharedBufferMemoryImpl(Struct): pass WGPUSharedBufferMemory = ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl) -class struct_WGPUSharedFenceImpl(Structure): - pass - +class struct_WGPUSharedFenceImpl(Struct): pass WGPUSharedFence = ctypes.POINTER(struct_WGPUSharedFenceImpl) -class struct_WGPUSharedTextureMemoryImpl(Structure): - pass - +class struct_WGPUSharedTextureMemoryImpl(Struct): pass WGPUSharedTextureMemory = ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl) -class struct_WGPUSurfaceImpl(Structure): - pass - +class struct_WGPUSurfaceImpl(Struct): pass WGPUSurface = ctypes.POINTER(struct_WGPUSurfaceImpl) -class struct_WGPUTextureImpl(Structure): - pass - +class struct_WGPUTextureImpl(Struct): pass WGPUTexture = ctypes.POINTER(struct_WGPUTextureImpl) -class struct_WGPUTextureViewImpl(Structure): - pass - +class struct_WGPUTextureViewImpl(Struct): pass WGPUTextureView = ctypes.POINTER(struct_WGPUTextureViewImpl) - -# values for enumeration 'WGPUWGSLFeatureName' -WGPUWGSLFeatureName__enumvalues = { - 1: 'WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures', - 2: 'WGPUWGSLFeatureName_Packed4x8IntegerDotProduct', - 3: 'WGPUWGSLFeatureName_UnrestrictedPointerParameters', - 4: 'WGPUWGSLFeatureName_PointerCompositeAccess', - 327680: 'WGPUWGSLFeatureName_ChromiumTestingUnimplemented', - 327681: 'WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental', - 327682: 'WGPUWGSLFeatureName_ChromiumTestingExperimental', - 327683: 'WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch', - 327684: 'WGPUWGSLFeatureName_ChromiumTestingShipped', - 2147483647: 'WGPUWGSLFeatureName_Force32', -} -WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures = 1 -WGPUWGSLFeatureName_Packed4x8IntegerDotProduct = 2 -WGPUWGSLFeatureName_UnrestrictedPointerParameters = 3 -WGPUWGSLFeatureName_PointerCompositeAccess = 4 -WGPUWGSLFeatureName_ChromiumTestingUnimplemented = 327680 -WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental = 327681 -WGPUWGSLFeatureName_ChromiumTestingExperimental = 327682 -WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch = 327683 -WGPUWGSLFeatureName_ChromiumTestingShipped = 327684 -WGPUWGSLFeatureName_Force32 = 2147483647 -WGPUWGSLFeatureName = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUAdapterType' -WGPUAdapterType__enumvalues = { - 1: 'WGPUAdapterType_DiscreteGPU', - 2: 'WGPUAdapterType_IntegratedGPU', - 3: 'WGPUAdapterType_CPU', - 4: 'WGPUAdapterType_Unknown', - 2147483647: 'WGPUAdapterType_Force32', -} -WGPUAdapterType_DiscreteGPU = 1 -WGPUAdapterType_IntegratedGPU = 2 -WGPUAdapterType_CPU = 3 -WGPUAdapterType_Unknown = 4 -WGPUAdapterType_Force32 = 2147483647 -WGPUAdapterType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUAddressMode' -WGPUAddressMode__enumvalues = { - 0: 'WGPUAddressMode_Undefined', - 1: 'WGPUAddressMode_ClampToEdge', - 2: 'WGPUAddressMode_Repeat', - 3: 'WGPUAddressMode_MirrorRepeat', - 2147483647: 'WGPUAddressMode_Force32', -} -WGPUAddressMode_Undefined = 0 -WGPUAddressMode_ClampToEdge = 1 -WGPUAddressMode_Repeat = 2 -WGPUAddressMode_MirrorRepeat = 3 -WGPUAddressMode_Force32 = 2147483647 -WGPUAddressMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUAlphaMode' -WGPUAlphaMode__enumvalues = { - 1: 'WGPUAlphaMode_Opaque', - 2: 'WGPUAlphaMode_Premultiplied', - 3: 'WGPUAlphaMode_Unpremultiplied', - 2147483647: 'WGPUAlphaMode_Force32', -} -WGPUAlphaMode_Opaque = 1 -WGPUAlphaMode_Premultiplied = 2 -WGPUAlphaMode_Unpremultiplied = 3 -WGPUAlphaMode_Force32 = 2147483647 -WGPUAlphaMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBackendType' -WGPUBackendType__enumvalues = { - 0: 'WGPUBackendType_Undefined', - 1: 'WGPUBackendType_Null', - 2: 'WGPUBackendType_WebGPU', - 3: 'WGPUBackendType_D3D11', - 4: 'WGPUBackendType_D3D12', - 5: 'WGPUBackendType_Metal', - 6: 'WGPUBackendType_Vulkan', - 7: 'WGPUBackendType_OpenGL', - 8: 'WGPUBackendType_OpenGLES', - 2147483647: 'WGPUBackendType_Force32', -} -WGPUBackendType_Undefined = 0 -WGPUBackendType_Null = 1 -WGPUBackendType_WebGPU = 2 -WGPUBackendType_D3D11 = 3 -WGPUBackendType_D3D12 = 4 -WGPUBackendType_Metal = 5 -WGPUBackendType_Vulkan = 6 -WGPUBackendType_OpenGL = 7 -WGPUBackendType_OpenGLES = 8 -WGPUBackendType_Force32 = 2147483647 -WGPUBackendType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBlendFactor' -WGPUBlendFactor__enumvalues = { - 0: 'WGPUBlendFactor_Undefined', - 1: 'WGPUBlendFactor_Zero', - 2: 'WGPUBlendFactor_One', - 3: 'WGPUBlendFactor_Src', - 4: 'WGPUBlendFactor_OneMinusSrc', - 5: 'WGPUBlendFactor_SrcAlpha', - 6: 'WGPUBlendFactor_OneMinusSrcAlpha', - 7: 'WGPUBlendFactor_Dst', - 8: 'WGPUBlendFactor_OneMinusDst', - 9: 'WGPUBlendFactor_DstAlpha', - 10: 'WGPUBlendFactor_OneMinusDstAlpha', - 11: 'WGPUBlendFactor_SrcAlphaSaturated', - 12: 'WGPUBlendFactor_Constant', - 13: 'WGPUBlendFactor_OneMinusConstant', - 14: 'WGPUBlendFactor_Src1', - 15: 'WGPUBlendFactor_OneMinusSrc1', - 16: 'WGPUBlendFactor_Src1Alpha', - 17: 'WGPUBlendFactor_OneMinusSrc1Alpha', - 2147483647: 'WGPUBlendFactor_Force32', -} -WGPUBlendFactor_Undefined = 0 -WGPUBlendFactor_Zero = 1 -WGPUBlendFactor_One = 2 -WGPUBlendFactor_Src = 3 -WGPUBlendFactor_OneMinusSrc = 4 -WGPUBlendFactor_SrcAlpha = 5 -WGPUBlendFactor_OneMinusSrcAlpha = 6 -WGPUBlendFactor_Dst = 7 -WGPUBlendFactor_OneMinusDst = 8 -WGPUBlendFactor_DstAlpha = 9 -WGPUBlendFactor_OneMinusDstAlpha = 10 -WGPUBlendFactor_SrcAlphaSaturated = 11 -WGPUBlendFactor_Constant = 12 -WGPUBlendFactor_OneMinusConstant = 13 -WGPUBlendFactor_Src1 = 14 -WGPUBlendFactor_OneMinusSrc1 = 15 -WGPUBlendFactor_Src1Alpha = 16 -WGPUBlendFactor_OneMinusSrc1Alpha = 17 -WGPUBlendFactor_Force32 = 2147483647 -WGPUBlendFactor = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBlendOperation' -WGPUBlendOperation__enumvalues = { - 0: 'WGPUBlendOperation_Undefined', - 1: 'WGPUBlendOperation_Add', - 2: 'WGPUBlendOperation_Subtract', - 3: 'WGPUBlendOperation_ReverseSubtract', - 4: 'WGPUBlendOperation_Min', - 5: 'WGPUBlendOperation_Max', - 2147483647: 'WGPUBlendOperation_Force32', -} -WGPUBlendOperation_Undefined = 0 -WGPUBlendOperation_Add = 1 -WGPUBlendOperation_Subtract = 2 -WGPUBlendOperation_ReverseSubtract = 3 -WGPUBlendOperation_Min = 4 -WGPUBlendOperation_Max = 5 -WGPUBlendOperation_Force32 = 2147483647 -WGPUBlendOperation = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBufferBindingType' -WGPUBufferBindingType__enumvalues = { - 0: 'WGPUBufferBindingType_BindingNotUsed', - 1: 'WGPUBufferBindingType_Uniform', - 2: 'WGPUBufferBindingType_Storage', - 3: 'WGPUBufferBindingType_ReadOnlyStorage', - 2147483647: 'WGPUBufferBindingType_Force32', -} -WGPUBufferBindingType_BindingNotUsed = 0 -WGPUBufferBindingType_Uniform = 1 -WGPUBufferBindingType_Storage = 2 -WGPUBufferBindingType_ReadOnlyStorage = 3 -WGPUBufferBindingType_Force32 = 2147483647 -WGPUBufferBindingType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBufferMapAsyncStatus' -WGPUBufferMapAsyncStatus__enumvalues = { - 1: 'WGPUBufferMapAsyncStatus_Success', - 2: 'WGPUBufferMapAsyncStatus_InstanceDropped', - 3: 'WGPUBufferMapAsyncStatus_ValidationError', - 4: 'WGPUBufferMapAsyncStatus_Unknown', - 5: 'WGPUBufferMapAsyncStatus_DeviceLost', - 6: 'WGPUBufferMapAsyncStatus_DestroyedBeforeCallback', - 7: 'WGPUBufferMapAsyncStatus_UnmappedBeforeCallback', - 8: 'WGPUBufferMapAsyncStatus_MappingAlreadyPending', - 9: 'WGPUBufferMapAsyncStatus_OffsetOutOfRange', - 10: 'WGPUBufferMapAsyncStatus_SizeOutOfRange', - 2147483647: 'WGPUBufferMapAsyncStatus_Force32', -} -WGPUBufferMapAsyncStatus_Success = 1 -WGPUBufferMapAsyncStatus_InstanceDropped = 2 -WGPUBufferMapAsyncStatus_ValidationError = 3 -WGPUBufferMapAsyncStatus_Unknown = 4 -WGPUBufferMapAsyncStatus_DeviceLost = 5 -WGPUBufferMapAsyncStatus_DestroyedBeforeCallback = 6 -WGPUBufferMapAsyncStatus_UnmappedBeforeCallback = 7 -WGPUBufferMapAsyncStatus_MappingAlreadyPending = 8 -WGPUBufferMapAsyncStatus_OffsetOutOfRange = 9 -WGPUBufferMapAsyncStatus_SizeOutOfRange = 10 -WGPUBufferMapAsyncStatus_Force32 = 2147483647 -WGPUBufferMapAsyncStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUBufferMapState' -WGPUBufferMapState__enumvalues = { - 1: 'WGPUBufferMapState_Unmapped', - 2: 'WGPUBufferMapState_Pending', - 3: 'WGPUBufferMapState_Mapped', - 2147483647: 'WGPUBufferMapState_Force32', -} -WGPUBufferMapState_Unmapped = 1 -WGPUBufferMapState_Pending = 2 -WGPUBufferMapState_Mapped = 3 -WGPUBufferMapState_Force32 = 2147483647 -WGPUBufferMapState = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCallbackMode' -WGPUCallbackMode__enumvalues = { - 1: 'WGPUCallbackMode_WaitAnyOnly', - 2: 'WGPUCallbackMode_AllowProcessEvents', - 3: 'WGPUCallbackMode_AllowSpontaneous', - 2147483647: 'WGPUCallbackMode_Force32', -} -WGPUCallbackMode_WaitAnyOnly = 1 -WGPUCallbackMode_AllowProcessEvents = 2 -WGPUCallbackMode_AllowSpontaneous = 3 -WGPUCallbackMode_Force32 = 2147483647 -WGPUCallbackMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompareFunction' -WGPUCompareFunction__enumvalues = { - 0: 'WGPUCompareFunction_Undefined', - 1: 'WGPUCompareFunction_Never', - 2: 'WGPUCompareFunction_Less', - 3: 'WGPUCompareFunction_Equal', - 4: 'WGPUCompareFunction_LessEqual', - 5: 'WGPUCompareFunction_Greater', - 6: 'WGPUCompareFunction_NotEqual', - 7: 'WGPUCompareFunction_GreaterEqual', - 8: 'WGPUCompareFunction_Always', - 2147483647: 'WGPUCompareFunction_Force32', -} -WGPUCompareFunction_Undefined = 0 -WGPUCompareFunction_Never = 1 -WGPUCompareFunction_Less = 2 -WGPUCompareFunction_Equal = 3 -WGPUCompareFunction_LessEqual = 4 -WGPUCompareFunction_Greater = 5 -WGPUCompareFunction_NotEqual = 6 -WGPUCompareFunction_GreaterEqual = 7 -WGPUCompareFunction_Always = 8 -WGPUCompareFunction_Force32 = 2147483647 -WGPUCompareFunction = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompilationInfoRequestStatus' -WGPUCompilationInfoRequestStatus__enumvalues = { - 1: 'WGPUCompilationInfoRequestStatus_Success', - 2: 'WGPUCompilationInfoRequestStatus_InstanceDropped', - 3: 'WGPUCompilationInfoRequestStatus_Error', - 4: 'WGPUCompilationInfoRequestStatus_DeviceLost', - 5: 'WGPUCompilationInfoRequestStatus_Unknown', - 2147483647: 'WGPUCompilationInfoRequestStatus_Force32', -} -WGPUCompilationInfoRequestStatus_Success = 1 -WGPUCompilationInfoRequestStatus_InstanceDropped = 2 -WGPUCompilationInfoRequestStatus_Error = 3 -WGPUCompilationInfoRequestStatus_DeviceLost = 4 -WGPUCompilationInfoRequestStatus_Unknown = 5 -WGPUCompilationInfoRequestStatus_Force32 = 2147483647 -WGPUCompilationInfoRequestStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompilationMessageType' -WGPUCompilationMessageType__enumvalues = { - 1: 'WGPUCompilationMessageType_Error', - 2: 'WGPUCompilationMessageType_Warning', - 3: 'WGPUCompilationMessageType_Info', - 2147483647: 'WGPUCompilationMessageType_Force32', -} -WGPUCompilationMessageType_Error = 1 -WGPUCompilationMessageType_Warning = 2 -WGPUCompilationMessageType_Info = 3 -WGPUCompilationMessageType_Force32 = 2147483647 -WGPUCompilationMessageType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCompositeAlphaMode' -WGPUCompositeAlphaMode__enumvalues = { - 0: 'WGPUCompositeAlphaMode_Auto', - 1: 'WGPUCompositeAlphaMode_Opaque', - 2: 'WGPUCompositeAlphaMode_Premultiplied', - 3: 'WGPUCompositeAlphaMode_Unpremultiplied', - 4: 'WGPUCompositeAlphaMode_Inherit', - 2147483647: 'WGPUCompositeAlphaMode_Force32', -} -WGPUCompositeAlphaMode_Auto = 0 -WGPUCompositeAlphaMode_Opaque = 1 -WGPUCompositeAlphaMode_Premultiplied = 2 -WGPUCompositeAlphaMode_Unpremultiplied = 3 -WGPUCompositeAlphaMode_Inherit = 4 -WGPUCompositeAlphaMode_Force32 = 2147483647 -WGPUCompositeAlphaMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCreatePipelineAsyncStatus' -WGPUCreatePipelineAsyncStatus__enumvalues = { - 1: 'WGPUCreatePipelineAsyncStatus_Success', - 2: 'WGPUCreatePipelineAsyncStatus_InstanceDropped', - 3: 'WGPUCreatePipelineAsyncStatus_ValidationError', - 4: 'WGPUCreatePipelineAsyncStatus_InternalError', - 5: 'WGPUCreatePipelineAsyncStatus_DeviceLost', - 6: 'WGPUCreatePipelineAsyncStatus_DeviceDestroyed', - 7: 'WGPUCreatePipelineAsyncStatus_Unknown', - 2147483647: 'WGPUCreatePipelineAsyncStatus_Force32', -} -WGPUCreatePipelineAsyncStatus_Success = 1 -WGPUCreatePipelineAsyncStatus_InstanceDropped = 2 -WGPUCreatePipelineAsyncStatus_ValidationError = 3 -WGPUCreatePipelineAsyncStatus_InternalError = 4 -WGPUCreatePipelineAsyncStatus_DeviceLost = 5 -WGPUCreatePipelineAsyncStatus_DeviceDestroyed = 6 -WGPUCreatePipelineAsyncStatus_Unknown = 7 -WGPUCreatePipelineAsyncStatus_Force32 = 2147483647 -WGPUCreatePipelineAsyncStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUCullMode' -WGPUCullMode__enumvalues = { - 0: 'WGPUCullMode_Undefined', - 1: 'WGPUCullMode_None', - 2: 'WGPUCullMode_Front', - 3: 'WGPUCullMode_Back', - 2147483647: 'WGPUCullMode_Force32', -} -WGPUCullMode_Undefined = 0 -WGPUCullMode_None = 1 -WGPUCullMode_Front = 2 -WGPUCullMode_Back = 3 -WGPUCullMode_Force32 = 2147483647 -WGPUCullMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUDeviceLostReason' -WGPUDeviceLostReason__enumvalues = { - 1: 'WGPUDeviceLostReason_Unknown', - 2: 'WGPUDeviceLostReason_Destroyed', - 3: 'WGPUDeviceLostReason_InstanceDropped', - 4: 'WGPUDeviceLostReason_FailedCreation', - 2147483647: 'WGPUDeviceLostReason_Force32', -} -WGPUDeviceLostReason_Unknown = 1 -WGPUDeviceLostReason_Destroyed = 2 -WGPUDeviceLostReason_InstanceDropped = 3 -WGPUDeviceLostReason_FailedCreation = 4 -WGPUDeviceLostReason_Force32 = 2147483647 -WGPUDeviceLostReason = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUErrorFilter' -WGPUErrorFilter__enumvalues = { - 1: 'WGPUErrorFilter_Validation', - 2: 'WGPUErrorFilter_OutOfMemory', - 3: 'WGPUErrorFilter_Internal', - 2147483647: 'WGPUErrorFilter_Force32', -} -WGPUErrorFilter_Validation = 1 -WGPUErrorFilter_OutOfMemory = 2 -WGPUErrorFilter_Internal = 3 -WGPUErrorFilter_Force32 = 2147483647 -WGPUErrorFilter = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUErrorType' -WGPUErrorType__enumvalues = { - 1: 'WGPUErrorType_NoError', - 2: 'WGPUErrorType_Validation', - 3: 'WGPUErrorType_OutOfMemory', - 4: 'WGPUErrorType_Internal', - 5: 'WGPUErrorType_Unknown', - 6: 'WGPUErrorType_DeviceLost', - 2147483647: 'WGPUErrorType_Force32', -} -WGPUErrorType_NoError = 1 -WGPUErrorType_Validation = 2 -WGPUErrorType_OutOfMemory = 3 -WGPUErrorType_Internal = 4 -WGPUErrorType_Unknown = 5 -WGPUErrorType_DeviceLost = 6 -WGPUErrorType_Force32 = 2147483647 -WGPUErrorType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUExternalTextureRotation' -WGPUExternalTextureRotation__enumvalues = { - 1: 'WGPUExternalTextureRotation_Rotate0Degrees', - 2: 'WGPUExternalTextureRotation_Rotate90Degrees', - 3: 'WGPUExternalTextureRotation_Rotate180Degrees', - 4: 'WGPUExternalTextureRotation_Rotate270Degrees', - 2147483647: 'WGPUExternalTextureRotation_Force32', -} -WGPUExternalTextureRotation_Rotate0Degrees = 1 -WGPUExternalTextureRotation_Rotate90Degrees = 2 -WGPUExternalTextureRotation_Rotate180Degrees = 3 -WGPUExternalTextureRotation_Rotate270Degrees = 4 -WGPUExternalTextureRotation_Force32 = 2147483647 -WGPUExternalTextureRotation = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFeatureLevel' -WGPUFeatureLevel__enumvalues = { - 0: 'WGPUFeatureLevel_Undefined', - 1: 'WGPUFeatureLevel_Compatibility', - 2: 'WGPUFeatureLevel_Core', - 2147483647: 'WGPUFeatureLevel_Force32', -} -WGPUFeatureLevel_Undefined = 0 -WGPUFeatureLevel_Compatibility = 1 -WGPUFeatureLevel_Core = 2 -WGPUFeatureLevel_Force32 = 2147483647 -WGPUFeatureLevel = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFeatureName' -WGPUFeatureName__enumvalues = { - 1: 'WGPUFeatureName_DepthClipControl', - 2: 'WGPUFeatureName_Depth32FloatStencil8', - 3: 'WGPUFeatureName_TimestampQuery', - 4: 'WGPUFeatureName_TextureCompressionBC', - 5: 'WGPUFeatureName_TextureCompressionETC2', - 6: 'WGPUFeatureName_TextureCompressionASTC', - 7: 'WGPUFeatureName_IndirectFirstInstance', - 8: 'WGPUFeatureName_ShaderF16', - 9: 'WGPUFeatureName_RG11B10UfloatRenderable', - 10: 'WGPUFeatureName_BGRA8UnormStorage', - 11: 'WGPUFeatureName_Float32Filterable', - 12: 'WGPUFeatureName_Float32Blendable', - 13: 'WGPUFeatureName_Subgroups', - 14: 'WGPUFeatureName_SubgroupsF16', - 327680: 'WGPUFeatureName_DawnInternalUsages', - 327681: 'WGPUFeatureName_DawnMultiPlanarFormats', - 327682: 'WGPUFeatureName_DawnNative', - 327683: 'WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses', - 327684: 'WGPUFeatureName_ImplicitDeviceSynchronization', - 327685: 'WGPUFeatureName_ChromiumExperimentalImmediateData', - 327686: 'WGPUFeatureName_TransientAttachments', - 327687: 'WGPUFeatureName_MSAARenderToSingleSampled', - 327688: 'WGPUFeatureName_DualSourceBlending', - 327689: 'WGPUFeatureName_D3D11MultithreadProtected', - 327690: 'WGPUFeatureName_ANGLETextureSharing', - 327691: 'WGPUFeatureName_PixelLocalStorageCoherent', - 327692: 'WGPUFeatureName_PixelLocalStorageNonCoherent', - 327693: 'WGPUFeatureName_Unorm16TextureFormats', - 327694: 'WGPUFeatureName_Snorm16TextureFormats', - 327695: 'WGPUFeatureName_MultiPlanarFormatExtendedUsages', - 327696: 'WGPUFeatureName_MultiPlanarFormatP010', - 327697: 'WGPUFeatureName_HostMappedPointer', - 327698: 'WGPUFeatureName_MultiPlanarRenderTargets', - 327699: 'WGPUFeatureName_MultiPlanarFormatNv12a', - 327700: 'WGPUFeatureName_FramebufferFetch', - 327701: 'WGPUFeatureName_BufferMapExtendedUsages', - 327702: 'WGPUFeatureName_AdapterPropertiesMemoryHeaps', - 327703: 'WGPUFeatureName_AdapterPropertiesD3D', - 327704: 'WGPUFeatureName_AdapterPropertiesVk', - 327705: 'WGPUFeatureName_R8UnormStorage', - 327706: 'WGPUFeatureName_FormatCapabilities', - 327707: 'WGPUFeatureName_DrmFormatCapabilities', - 327708: 'WGPUFeatureName_Norm16TextureFormats', - 327709: 'WGPUFeatureName_MultiPlanarFormatNv16', - 327710: 'WGPUFeatureName_MultiPlanarFormatNv24', - 327711: 'WGPUFeatureName_MultiPlanarFormatP210', - 327712: 'WGPUFeatureName_MultiPlanarFormatP410', - 327713: 'WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation', - 327714: 'WGPUFeatureName_SharedTextureMemoryAHardwareBuffer', - 327715: 'WGPUFeatureName_SharedTextureMemoryDmaBuf', - 327716: 'WGPUFeatureName_SharedTextureMemoryOpaqueFD', - 327717: 'WGPUFeatureName_SharedTextureMemoryZirconHandle', - 327718: 'WGPUFeatureName_SharedTextureMemoryDXGISharedHandle', - 327719: 'WGPUFeatureName_SharedTextureMemoryD3D11Texture2D', - 327720: 'WGPUFeatureName_SharedTextureMemoryIOSurface', - 327721: 'WGPUFeatureName_SharedTextureMemoryEGLImage', - 327722: 'WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD', - 327723: 'WGPUFeatureName_SharedFenceSyncFD', - 327724: 'WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle', - 327725: 'WGPUFeatureName_SharedFenceDXGISharedHandle', - 327726: 'WGPUFeatureName_SharedFenceMTLSharedEvent', - 327727: 'WGPUFeatureName_SharedBufferMemoryD3D12Resource', - 327728: 'WGPUFeatureName_StaticSamplers', - 327729: 'WGPUFeatureName_YCbCrVulkanSamplers', - 327730: 'WGPUFeatureName_ShaderModuleCompilationOptions', - 327731: 'WGPUFeatureName_DawnLoadResolveTexture', - 327732: 'WGPUFeatureName_DawnPartialLoadResolveTexture', - 327733: 'WGPUFeatureName_MultiDrawIndirect', - 327734: 'WGPUFeatureName_ClipDistances', - 327735: 'WGPUFeatureName_DawnTexelCopyBufferRowAlignment', - 327736: 'WGPUFeatureName_FlexibleTextureViews', - 2147483647: 'WGPUFeatureName_Force32', -} -WGPUFeatureName_DepthClipControl = 1 -WGPUFeatureName_Depth32FloatStencil8 = 2 -WGPUFeatureName_TimestampQuery = 3 -WGPUFeatureName_TextureCompressionBC = 4 -WGPUFeatureName_TextureCompressionETC2 = 5 -WGPUFeatureName_TextureCompressionASTC = 6 -WGPUFeatureName_IndirectFirstInstance = 7 -WGPUFeatureName_ShaderF16 = 8 -WGPUFeatureName_RG11B10UfloatRenderable = 9 -WGPUFeatureName_BGRA8UnormStorage = 10 -WGPUFeatureName_Float32Filterable = 11 -WGPUFeatureName_Float32Blendable = 12 -WGPUFeatureName_Subgroups = 13 -WGPUFeatureName_SubgroupsF16 = 14 -WGPUFeatureName_DawnInternalUsages = 327680 -WGPUFeatureName_DawnMultiPlanarFormats = 327681 -WGPUFeatureName_DawnNative = 327682 -WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses = 327683 -WGPUFeatureName_ImplicitDeviceSynchronization = 327684 -WGPUFeatureName_ChromiumExperimentalImmediateData = 327685 -WGPUFeatureName_TransientAttachments = 327686 -WGPUFeatureName_MSAARenderToSingleSampled = 327687 -WGPUFeatureName_DualSourceBlending = 327688 -WGPUFeatureName_D3D11MultithreadProtected = 327689 -WGPUFeatureName_ANGLETextureSharing = 327690 -WGPUFeatureName_PixelLocalStorageCoherent = 327691 -WGPUFeatureName_PixelLocalStorageNonCoherent = 327692 -WGPUFeatureName_Unorm16TextureFormats = 327693 -WGPUFeatureName_Snorm16TextureFormats = 327694 -WGPUFeatureName_MultiPlanarFormatExtendedUsages = 327695 -WGPUFeatureName_MultiPlanarFormatP010 = 327696 -WGPUFeatureName_HostMappedPointer = 327697 -WGPUFeatureName_MultiPlanarRenderTargets = 327698 -WGPUFeatureName_MultiPlanarFormatNv12a = 327699 -WGPUFeatureName_FramebufferFetch = 327700 -WGPUFeatureName_BufferMapExtendedUsages = 327701 -WGPUFeatureName_AdapterPropertiesMemoryHeaps = 327702 -WGPUFeatureName_AdapterPropertiesD3D = 327703 -WGPUFeatureName_AdapterPropertiesVk = 327704 -WGPUFeatureName_R8UnormStorage = 327705 -WGPUFeatureName_FormatCapabilities = 327706 -WGPUFeatureName_DrmFormatCapabilities = 327707 -WGPUFeatureName_Norm16TextureFormats = 327708 -WGPUFeatureName_MultiPlanarFormatNv16 = 327709 -WGPUFeatureName_MultiPlanarFormatNv24 = 327710 -WGPUFeatureName_MultiPlanarFormatP210 = 327711 -WGPUFeatureName_MultiPlanarFormatP410 = 327712 -WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation = 327713 -WGPUFeatureName_SharedTextureMemoryAHardwareBuffer = 327714 -WGPUFeatureName_SharedTextureMemoryDmaBuf = 327715 -WGPUFeatureName_SharedTextureMemoryOpaqueFD = 327716 -WGPUFeatureName_SharedTextureMemoryZirconHandle = 327717 -WGPUFeatureName_SharedTextureMemoryDXGISharedHandle = 327718 -WGPUFeatureName_SharedTextureMemoryD3D11Texture2D = 327719 -WGPUFeatureName_SharedTextureMemoryIOSurface = 327720 -WGPUFeatureName_SharedTextureMemoryEGLImage = 327721 -WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD = 327722 -WGPUFeatureName_SharedFenceSyncFD = 327723 -WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle = 327724 -WGPUFeatureName_SharedFenceDXGISharedHandle = 327725 -WGPUFeatureName_SharedFenceMTLSharedEvent = 327726 -WGPUFeatureName_SharedBufferMemoryD3D12Resource = 327727 -WGPUFeatureName_StaticSamplers = 327728 -WGPUFeatureName_YCbCrVulkanSamplers = 327729 -WGPUFeatureName_ShaderModuleCompilationOptions = 327730 -WGPUFeatureName_DawnLoadResolveTexture = 327731 -WGPUFeatureName_DawnPartialLoadResolveTexture = 327732 -WGPUFeatureName_MultiDrawIndirect = 327733 -WGPUFeatureName_ClipDistances = 327734 -WGPUFeatureName_DawnTexelCopyBufferRowAlignment = 327735 -WGPUFeatureName_FlexibleTextureViews = 327736 -WGPUFeatureName_Force32 = 2147483647 -WGPUFeatureName = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFilterMode' -WGPUFilterMode__enumvalues = { - 0: 'WGPUFilterMode_Undefined', - 1: 'WGPUFilterMode_Nearest', - 2: 'WGPUFilterMode_Linear', - 2147483647: 'WGPUFilterMode_Force32', -} -WGPUFilterMode_Undefined = 0 -WGPUFilterMode_Nearest = 1 -WGPUFilterMode_Linear = 2 -WGPUFilterMode_Force32 = 2147483647 -WGPUFilterMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUFrontFace' -WGPUFrontFace__enumvalues = { - 0: 'WGPUFrontFace_Undefined', - 1: 'WGPUFrontFace_CCW', - 2: 'WGPUFrontFace_CW', - 2147483647: 'WGPUFrontFace_Force32', -} -WGPUFrontFace_Undefined = 0 -WGPUFrontFace_CCW = 1 -WGPUFrontFace_CW = 2 -WGPUFrontFace_Force32 = 2147483647 -WGPUFrontFace = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUIndexFormat' -WGPUIndexFormat__enumvalues = { - 0: 'WGPUIndexFormat_Undefined', - 1: 'WGPUIndexFormat_Uint16', - 2: 'WGPUIndexFormat_Uint32', - 2147483647: 'WGPUIndexFormat_Force32', -} -WGPUIndexFormat_Undefined = 0 -WGPUIndexFormat_Uint16 = 1 -WGPUIndexFormat_Uint32 = 2 -WGPUIndexFormat_Force32 = 2147483647 -WGPUIndexFormat = ctypes.c_uint32 # enum - -# values for enumeration 'WGPULoadOp' -WGPULoadOp__enumvalues = { - 0: 'WGPULoadOp_Undefined', - 1: 'WGPULoadOp_Load', - 2: 'WGPULoadOp_Clear', - 327683: 'WGPULoadOp_ExpandResolveTexture', - 2147483647: 'WGPULoadOp_Force32', -} -WGPULoadOp_Undefined = 0 -WGPULoadOp_Load = 1 -WGPULoadOp_Clear = 2 -WGPULoadOp_ExpandResolveTexture = 327683 -WGPULoadOp_Force32 = 2147483647 -WGPULoadOp = ctypes.c_uint32 # enum - -# values for enumeration 'WGPULoggingType' -WGPULoggingType__enumvalues = { - 1: 'WGPULoggingType_Verbose', - 2: 'WGPULoggingType_Info', - 3: 'WGPULoggingType_Warning', - 4: 'WGPULoggingType_Error', - 2147483647: 'WGPULoggingType_Force32', -} -WGPULoggingType_Verbose = 1 -WGPULoggingType_Info = 2 -WGPULoggingType_Warning = 3 -WGPULoggingType_Error = 4 -WGPULoggingType_Force32 = 2147483647 -WGPULoggingType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUMapAsyncStatus' -WGPUMapAsyncStatus__enumvalues = { - 1: 'WGPUMapAsyncStatus_Success', - 2: 'WGPUMapAsyncStatus_InstanceDropped', - 3: 'WGPUMapAsyncStatus_Error', - 4: 'WGPUMapAsyncStatus_Aborted', - 5: 'WGPUMapAsyncStatus_Unknown', - 2147483647: 'WGPUMapAsyncStatus_Force32', -} -WGPUMapAsyncStatus_Success = 1 -WGPUMapAsyncStatus_InstanceDropped = 2 -WGPUMapAsyncStatus_Error = 3 -WGPUMapAsyncStatus_Aborted = 4 -WGPUMapAsyncStatus_Unknown = 5 -WGPUMapAsyncStatus_Force32 = 2147483647 -WGPUMapAsyncStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUMipmapFilterMode' -WGPUMipmapFilterMode__enumvalues = { - 0: 'WGPUMipmapFilterMode_Undefined', - 1: 'WGPUMipmapFilterMode_Nearest', - 2: 'WGPUMipmapFilterMode_Linear', - 2147483647: 'WGPUMipmapFilterMode_Force32', -} -WGPUMipmapFilterMode_Undefined = 0 -WGPUMipmapFilterMode_Nearest = 1 -WGPUMipmapFilterMode_Linear = 2 -WGPUMipmapFilterMode_Force32 = 2147483647 -WGPUMipmapFilterMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUOptionalBool' -WGPUOptionalBool__enumvalues = { - 0: 'WGPUOptionalBool_False', - 1: 'WGPUOptionalBool_True', - 2: 'WGPUOptionalBool_Undefined', - 2147483647: 'WGPUOptionalBool_Force32', -} -WGPUOptionalBool_False = 0 -WGPUOptionalBool_True = 1 -WGPUOptionalBool_Undefined = 2 -WGPUOptionalBool_Force32 = 2147483647 -WGPUOptionalBool = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPopErrorScopeStatus' -WGPUPopErrorScopeStatus__enumvalues = { - 1: 'WGPUPopErrorScopeStatus_Success', - 2: 'WGPUPopErrorScopeStatus_InstanceDropped', - 2147483647: 'WGPUPopErrorScopeStatus_Force32', -} -WGPUPopErrorScopeStatus_Success = 1 -WGPUPopErrorScopeStatus_InstanceDropped = 2 -WGPUPopErrorScopeStatus_Force32 = 2147483647 -WGPUPopErrorScopeStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPowerPreference' -WGPUPowerPreference__enumvalues = { - 0: 'WGPUPowerPreference_Undefined', - 1: 'WGPUPowerPreference_LowPower', - 2: 'WGPUPowerPreference_HighPerformance', - 2147483647: 'WGPUPowerPreference_Force32', -} -WGPUPowerPreference_Undefined = 0 -WGPUPowerPreference_LowPower = 1 -WGPUPowerPreference_HighPerformance = 2 -WGPUPowerPreference_Force32 = 2147483647 -WGPUPowerPreference = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPresentMode' -WGPUPresentMode__enumvalues = { - 1: 'WGPUPresentMode_Fifo', - 2: 'WGPUPresentMode_FifoRelaxed', - 3: 'WGPUPresentMode_Immediate', - 4: 'WGPUPresentMode_Mailbox', - 2147483647: 'WGPUPresentMode_Force32', -} -WGPUPresentMode_Fifo = 1 -WGPUPresentMode_FifoRelaxed = 2 -WGPUPresentMode_Immediate = 3 -WGPUPresentMode_Mailbox = 4 -WGPUPresentMode_Force32 = 2147483647 -WGPUPresentMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUPrimitiveTopology' -WGPUPrimitiveTopology__enumvalues = { - 0: 'WGPUPrimitiveTopology_Undefined', - 1: 'WGPUPrimitiveTopology_PointList', - 2: 'WGPUPrimitiveTopology_LineList', - 3: 'WGPUPrimitiveTopology_LineStrip', - 4: 'WGPUPrimitiveTopology_TriangleList', - 5: 'WGPUPrimitiveTopology_TriangleStrip', - 2147483647: 'WGPUPrimitiveTopology_Force32', -} -WGPUPrimitiveTopology_Undefined = 0 -WGPUPrimitiveTopology_PointList = 1 -WGPUPrimitiveTopology_LineList = 2 -WGPUPrimitiveTopology_LineStrip = 3 -WGPUPrimitiveTopology_TriangleList = 4 -WGPUPrimitiveTopology_TriangleStrip = 5 -WGPUPrimitiveTopology_Force32 = 2147483647 -WGPUPrimitiveTopology = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUQueryType' -WGPUQueryType__enumvalues = { - 1: 'WGPUQueryType_Occlusion', - 2: 'WGPUQueryType_Timestamp', - 2147483647: 'WGPUQueryType_Force32', -} -WGPUQueryType_Occlusion = 1 -WGPUQueryType_Timestamp = 2 -WGPUQueryType_Force32 = 2147483647 -WGPUQueryType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUQueueWorkDoneStatus' -WGPUQueueWorkDoneStatus__enumvalues = { - 1: 'WGPUQueueWorkDoneStatus_Success', - 2: 'WGPUQueueWorkDoneStatus_InstanceDropped', - 3: 'WGPUQueueWorkDoneStatus_Error', - 4: 'WGPUQueueWorkDoneStatus_Unknown', - 5: 'WGPUQueueWorkDoneStatus_DeviceLost', - 2147483647: 'WGPUQueueWorkDoneStatus_Force32', -} -WGPUQueueWorkDoneStatus_Success = 1 -WGPUQueueWorkDoneStatus_InstanceDropped = 2 -WGPUQueueWorkDoneStatus_Error = 3 -WGPUQueueWorkDoneStatus_Unknown = 4 -WGPUQueueWorkDoneStatus_DeviceLost = 5 -WGPUQueueWorkDoneStatus_Force32 = 2147483647 -WGPUQueueWorkDoneStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPURequestAdapterStatus' -WGPURequestAdapterStatus__enumvalues = { - 1: 'WGPURequestAdapterStatus_Success', - 2: 'WGPURequestAdapterStatus_InstanceDropped', - 3: 'WGPURequestAdapterStatus_Unavailable', - 4: 'WGPURequestAdapterStatus_Error', - 5: 'WGPURequestAdapterStatus_Unknown', - 2147483647: 'WGPURequestAdapterStatus_Force32', -} -WGPURequestAdapterStatus_Success = 1 -WGPURequestAdapterStatus_InstanceDropped = 2 -WGPURequestAdapterStatus_Unavailable = 3 -WGPURequestAdapterStatus_Error = 4 -WGPURequestAdapterStatus_Unknown = 5 -WGPURequestAdapterStatus_Force32 = 2147483647 -WGPURequestAdapterStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPURequestDeviceStatus' -WGPURequestDeviceStatus__enumvalues = { - 1: 'WGPURequestDeviceStatus_Success', - 2: 'WGPURequestDeviceStatus_InstanceDropped', - 3: 'WGPURequestDeviceStatus_Error', - 4: 'WGPURequestDeviceStatus_Unknown', - 2147483647: 'WGPURequestDeviceStatus_Force32', -} -WGPURequestDeviceStatus_Success = 1 -WGPURequestDeviceStatus_InstanceDropped = 2 -WGPURequestDeviceStatus_Error = 3 -WGPURequestDeviceStatus_Unknown = 4 -WGPURequestDeviceStatus_Force32 = 2147483647 -WGPURequestDeviceStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSType' -WGPUSType__enumvalues = { - 1: 'WGPUSType_ShaderSourceSPIRV', - 2: 'WGPUSType_ShaderSourceWGSL', - 3: 'WGPUSType_RenderPassMaxDrawCount', - 4: 'WGPUSType_SurfaceSourceMetalLayer', - 5: 'WGPUSType_SurfaceSourceWindowsHWND', - 6: 'WGPUSType_SurfaceSourceXlibWindow', - 7: 'WGPUSType_SurfaceSourceWaylandSurface', - 8: 'WGPUSType_SurfaceSourceAndroidNativeWindow', - 9: 'WGPUSType_SurfaceSourceXCBWindow', - 10: 'WGPUSType_AdapterPropertiesSubgroups', - 131072: 'WGPUSType_TextureBindingViewDimensionDescriptor', - 262144: 'WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten', - 327680: 'WGPUSType_SurfaceDescriptorFromWindowsCoreWindow', - 327681: 'WGPUSType_ExternalTextureBindingEntry', - 327682: 'WGPUSType_ExternalTextureBindingLayout', - 327683: 'WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel', - 327684: 'WGPUSType_DawnTextureInternalUsageDescriptor', - 327685: 'WGPUSType_DawnEncoderInternalUsageDescriptor', - 327686: 'WGPUSType_DawnInstanceDescriptor', - 327687: 'WGPUSType_DawnCacheDeviceDescriptor', - 327688: 'WGPUSType_DawnAdapterPropertiesPowerPreference', - 327689: 'WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient', - 327690: 'WGPUSType_DawnTogglesDescriptor', - 327691: 'WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor', - 327692: 'WGPUSType_RequestAdapterOptionsLUID', - 327693: 'WGPUSType_RequestAdapterOptionsGetGLProc', - 327694: 'WGPUSType_RequestAdapterOptionsD3D11Device', - 327695: 'WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled', - 327696: 'WGPUSType_RenderPassPixelLocalStorage', - 327697: 'WGPUSType_PipelineLayoutPixelLocalStorage', - 327698: 'WGPUSType_BufferHostMappedPointer', - 327699: 'WGPUSType_DawnExperimentalSubgroupLimits', - 327700: 'WGPUSType_AdapterPropertiesMemoryHeaps', - 327701: 'WGPUSType_AdapterPropertiesD3D', - 327702: 'WGPUSType_AdapterPropertiesVk', - 327703: 'WGPUSType_DawnWireWGSLControl', - 327704: 'WGPUSType_DawnWGSLBlocklist', - 327705: 'WGPUSType_DrmFormatCapabilities', - 327706: 'WGPUSType_ShaderModuleCompilationOptions', - 327707: 'WGPUSType_ColorTargetStateExpandResolveTextureDawn', - 327708: 'WGPUSType_RenderPassDescriptorExpandResolveRect', - 327709: 'WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor', - 327710: 'WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor', - 327711: 'WGPUSType_SharedTextureMemoryDmaBufDescriptor', - 327712: 'WGPUSType_SharedTextureMemoryOpaqueFDDescriptor', - 327713: 'WGPUSType_SharedTextureMemoryZirconHandleDescriptor', - 327714: 'WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor', - 327715: 'WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor', - 327716: 'WGPUSType_SharedTextureMemoryIOSurfaceDescriptor', - 327717: 'WGPUSType_SharedTextureMemoryEGLImageDescriptor', - 327718: 'WGPUSType_SharedTextureMemoryInitializedBeginState', - 327719: 'WGPUSType_SharedTextureMemoryInitializedEndState', - 327720: 'WGPUSType_SharedTextureMemoryVkImageLayoutBeginState', - 327721: 'WGPUSType_SharedTextureMemoryVkImageLayoutEndState', - 327722: 'WGPUSType_SharedTextureMemoryD3DSwapchainBeginState', - 327723: 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor', - 327724: 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo', - 327725: 'WGPUSType_SharedFenceSyncFDDescriptor', - 327726: 'WGPUSType_SharedFenceSyncFDExportInfo', - 327727: 'WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor', - 327728: 'WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo', - 327729: 'WGPUSType_SharedFenceDXGISharedHandleDescriptor', - 327730: 'WGPUSType_SharedFenceDXGISharedHandleExportInfo', - 327731: 'WGPUSType_SharedFenceMTLSharedEventDescriptor', - 327732: 'WGPUSType_SharedFenceMTLSharedEventExportInfo', - 327733: 'WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor', - 327734: 'WGPUSType_StaticSamplerBindingLayout', - 327735: 'WGPUSType_YCbCrVkDescriptor', - 327736: 'WGPUSType_SharedTextureMemoryAHardwareBufferProperties', - 327737: 'WGPUSType_AHardwareBufferProperties', - 327738: 'WGPUSType_DawnExperimentalImmediateDataLimits', - 327739: 'WGPUSType_DawnTexelCopyBufferRowAlignmentLimits', - 2147483647: 'WGPUSType_Force32', -} -WGPUSType_ShaderSourceSPIRV = 1 -WGPUSType_ShaderSourceWGSL = 2 -WGPUSType_RenderPassMaxDrawCount = 3 -WGPUSType_SurfaceSourceMetalLayer = 4 -WGPUSType_SurfaceSourceWindowsHWND = 5 -WGPUSType_SurfaceSourceXlibWindow = 6 -WGPUSType_SurfaceSourceWaylandSurface = 7 -WGPUSType_SurfaceSourceAndroidNativeWindow = 8 -WGPUSType_SurfaceSourceXCBWindow = 9 -WGPUSType_AdapterPropertiesSubgroups = 10 -WGPUSType_TextureBindingViewDimensionDescriptor = 131072 -WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten = 262144 -WGPUSType_SurfaceDescriptorFromWindowsCoreWindow = 327680 -WGPUSType_ExternalTextureBindingEntry = 327681 -WGPUSType_ExternalTextureBindingLayout = 327682 -WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel = 327683 -WGPUSType_DawnTextureInternalUsageDescriptor = 327684 -WGPUSType_DawnEncoderInternalUsageDescriptor = 327685 -WGPUSType_DawnInstanceDescriptor = 327686 -WGPUSType_DawnCacheDeviceDescriptor = 327687 -WGPUSType_DawnAdapterPropertiesPowerPreference = 327688 -WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient = 327689 -WGPUSType_DawnTogglesDescriptor = 327690 -WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor = 327691 -WGPUSType_RequestAdapterOptionsLUID = 327692 -WGPUSType_RequestAdapterOptionsGetGLProc = 327693 -WGPUSType_RequestAdapterOptionsD3D11Device = 327694 -WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled = 327695 -WGPUSType_RenderPassPixelLocalStorage = 327696 -WGPUSType_PipelineLayoutPixelLocalStorage = 327697 -WGPUSType_BufferHostMappedPointer = 327698 -WGPUSType_DawnExperimentalSubgroupLimits = 327699 -WGPUSType_AdapterPropertiesMemoryHeaps = 327700 -WGPUSType_AdapterPropertiesD3D = 327701 -WGPUSType_AdapterPropertiesVk = 327702 -WGPUSType_DawnWireWGSLControl = 327703 -WGPUSType_DawnWGSLBlocklist = 327704 -WGPUSType_DrmFormatCapabilities = 327705 -WGPUSType_ShaderModuleCompilationOptions = 327706 -WGPUSType_ColorTargetStateExpandResolveTextureDawn = 327707 -WGPUSType_RenderPassDescriptorExpandResolveRect = 327708 -WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor = 327709 -WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor = 327710 -WGPUSType_SharedTextureMemoryDmaBufDescriptor = 327711 -WGPUSType_SharedTextureMemoryOpaqueFDDescriptor = 327712 -WGPUSType_SharedTextureMemoryZirconHandleDescriptor = 327713 -WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor = 327714 -WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor = 327715 -WGPUSType_SharedTextureMemoryIOSurfaceDescriptor = 327716 -WGPUSType_SharedTextureMemoryEGLImageDescriptor = 327717 -WGPUSType_SharedTextureMemoryInitializedBeginState = 327718 -WGPUSType_SharedTextureMemoryInitializedEndState = 327719 -WGPUSType_SharedTextureMemoryVkImageLayoutBeginState = 327720 -WGPUSType_SharedTextureMemoryVkImageLayoutEndState = 327721 -WGPUSType_SharedTextureMemoryD3DSwapchainBeginState = 327722 -WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor = 327723 -WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo = 327724 -WGPUSType_SharedFenceSyncFDDescriptor = 327725 -WGPUSType_SharedFenceSyncFDExportInfo = 327726 -WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor = 327727 -WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo = 327728 -WGPUSType_SharedFenceDXGISharedHandleDescriptor = 327729 -WGPUSType_SharedFenceDXGISharedHandleExportInfo = 327730 -WGPUSType_SharedFenceMTLSharedEventDescriptor = 327731 -WGPUSType_SharedFenceMTLSharedEventExportInfo = 327732 -WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor = 327733 -WGPUSType_StaticSamplerBindingLayout = 327734 -WGPUSType_YCbCrVkDescriptor = 327735 -WGPUSType_SharedTextureMemoryAHardwareBufferProperties = 327736 -WGPUSType_AHardwareBufferProperties = 327737 -WGPUSType_DawnExperimentalImmediateDataLimits = 327738 -WGPUSType_DawnTexelCopyBufferRowAlignmentLimits = 327739 -WGPUSType_Force32 = 2147483647 -WGPUSType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSamplerBindingType' -WGPUSamplerBindingType__enumvalues = { - 0: 'WGPUSamplerBindingType_BindingNotUsed', - 1: 'WGPUSamplerBindingType_Filtering', - 2: 'WGPUSamplerBindingType_NonFiltering', - 3: 'WGPUSamplerBindingType_Comparison', - 2147483647: 'WGPUSamplerBindingType_Force32', -} -WGPUSamplerBindingType_BindingNotUsed = 0 -WGPUSamplerBindingType_Filtering = 1 -WGPUSamplerBindingType_NonFiltering = 2 -WGPUSamplerBindingType_Comparison = 3 -WGPUSamplerBindingType_Force32 = 2147483647 -WGPUSamplerBindingType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSharedFenceType' -WGPUSharedFenceType__enumvalues = { - 1: 'WGPUSharedFenceType_VkSemaphoreOpaqueFD', - 2: 'WGPUSharedFenceType_SyncFD', - 3: 'WGPUSharedFenceType_VkSemaphoreZirconHandle', - 4: 'WGPUSharedFenceType_DXGISharedHandle', - 5: 'WGPUSharedFenceType_MTLSharedEvent', - 2147483647: 'WGPUSharedFenceType_Force32', -} -WGPUSharedFenceType_VkSemaphoreOpaqueFD = 1 -WGPUSharedFenceType_SyncFD = 2 -WGPUSharedFenceType_VkSemaphoreZirconHandle = 3 -WGPUSharedFenceType_DXGISharedHandle = 4 -WGPUSharedFenceType_MTLSharedEvent = 5 -WGPUSharedFenceType_Force32 = 2147483647 -WGPUSharedFenceType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStatus' -WGPUStatus__enumvalues = { - 1: 'WGPUStatus_Success', - 2: 'WGPUStatus_Error', - 2147483647: 'WGPUStatus_Force32', -} -WGPUStatus_Success = 1 -WGPUStatus_Error = 2 -WGPUStatus_Force32 = 2147483647 -WGPUStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStencilOperation' -WGPUStencilOperation__enumvalues = { - 0: 'WGPUStencilOperation_Undefined', - 1: 'WGPUStencilOperation_Keep', - 2: 'WGPUStencilOperation_Zero', - 3: 'WGPUStencilOperation_Replace', - 4: 'WGPUStencilOperation_Invert', - 5: 'WGPUStencilOperation_IncrementClamp', - 6: 'WGPUStencilOperation_DecrementClamp', - 7: 'WGPUStencilOperation_IncrementWrap', - 8: 'WGPUStencilOperation_DecrementWrap', - 2147483647: 'WGPUStencilOperation_Force32', -} -WGPUStencilOperation_Undefined = 0 -WGPUStencilOperation_Keep = 1 -WGPUStencilOperation_Zero = 2 -WGPUStencilOperation_Replace = 3 -WGPUStencilOperation_Invert = 4 -WGPUStencilOperation_IncrementClamp = 5 -WGPUStencilOperation_DecrementClamp = 6 -WGPUStencilOperation_IncrementWrap = 7 -WGPUStencilOperation_DecrementWrap = 8 -WGPUStencilOperation_Force32 = 2147483647 -WGPUStencilOperation = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStorageTextureAccess' -WGPUStorageTextureAccess__enumvalues = { - 0: 'WGPUStorageTextureAccess_BindingNotUsed', - 1: 'WGPUStorageTextureAccess_WriteOnly', - 2: 'WGPUStorageTextureAccess_ReadOnly', - 3: 'WGPUStorageTextureAccess_ReadWrite', - 2147483647: 'WGPUStorageTextureAccess_Force32', -} -WGPUStorageTextureAccess_BindingNotUsed = 0 -WGPUStorageTextureAccess_WriteOnly = 1 -WGPUStorageTextureAccess_ReadOnly = 2 -WGPUStorageTextureAccess_ReadWrite = 3 -WGPUStorageTextureAccess_Force32 = 2147483647 -WGPUStorageTextureAccess = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUStoreOp' -WGPUStoreOp__enumvalues = { - 0: 'WGPUStoreOp_Undefined', - 1: 'WGPUStoreOp_Store', - 2: 'WGPUStoreOp_Discard', - 2147483647: 'WGPUStoreOp_Force32', -} -WGPUStoreOp_Undefined = 0 -WGPUStoreOp_Store = 1 -WGPUStoreOp_Discard = 2 -WGPUStoreOp_Force32 = 2147483647 -WGPUStoreOp = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUSurfaceGetCurrentTextureStatus' -WGPUSurfaceGetCurrentTextureStatus__enumvalues = { - 1: 'WGPUSurfaceGetCurrentTextureStatus_Success', - 2: 'WGPUSurfaceGetCurrentTextureStatus_Timeout', - 3: 'WGPUSurfaceGetCurrentTextureStatus_Outdated', - 4: 'WGPUSurfaceGetCurrentTextureStatus_Lost', - 5: 'WGPUSurfaceGetCurrentTextureStatus_OutOfMemory', - 6: 'WGPUSurfaceGetCurrentTextureStatus_DeviceLost', - 7: 'WGPUSurfaceGetCurrentTextureStatus_Error', - 2147483647: 'WGPUSurfaceGetCurrentTextureStatus_Force32', -} -WGPUSurfaceGetCurrentTextureStatus_Success = 1 -WGPUSurfaceGetCurrentTextureStatus_Timeout = 2 -WGPUSurfaceGetCurrentTextureStatus_Outdated = 3 -WGPUSurfaceGetCurrentTextureStatus_Lost = 4 -WGPUSurfaceGetCurrentTextureStatus_OutOfMemory = 5 -WGPUSurfaceGetCurrentTextureStatus_DeviceLost = 6 -WGPUSurfaceGetCurrentTextureStatus_Error = 7 -WGPUSurfaceGetCurrentTextureStatus_Force32 = 2147483647 -WGPUSurfaceGetCurrentTextureStatus = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureAspect' -WGPUTextureAspect__enumvalues = { - 0: 'WGPUTextureAspect_Undefined', - 1: 'WGPUTextureAspect_All', - 2: 'WGPUTextureAspect_StencilOnly', - 3: 'WGPUTextureAspect_DepthOnly', - 327680: 'WGPUTextureAspect_Plane0Only', - 327681: 'WGPUTextureAspect_Plane1Only', - 327682: 'WGPUTextureAspect_Plane2Only', - 2147483647: 'WGPUTextureAspect_Force32', -} -WGPUTextureAspect_Undefined = 0 -WGPUTextureAspect_All = 1 -WGPUTextureAspect_StencilOnly = 2 -WGPUTextureAspect_DepthOnly = 3 -WGPUTextureAspect_Plane0Only = 327680 -WGPUTextureAspect_Plane1Only = 327681 -WGPUTextureAspect_Plane2Only = 327682 -WGPUTextureAspect_Force32 = 2147483647 -WGPUTextureAspect = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureDimension' -WGPUTextureDimension__enumvalues = { - 0: 'WGPUTextureDimension_Undefined', - 1: 'WGPUTextureDimension_1D', - 2: 'WGPUTextureDimension_2D', - 3: 'WGPUTextureDimension_3D', - 2147483647: 'WGPUTextureDimension_Force32', -} -WGPUTextureDimension_Undefined = 0 -WGPUTextureDimension_1D = 1 -WGPUTextureDimension_2D = 2 -WGPUTextureDimension_3D = 3 -WGPUTextureDimension_Force32 = 2147483647 -WGPUTextureDimension = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureFormat' -WGPUTextureFormat__enumvalues = { - 0: 'WGPUTextureFormat_Undefined', - 1: 'WGPUTextureFormat_R8Unorm', - 2: 'WGPUTextureFormat_R8Snorm', - 3: 'WGPUTextureFormat_R8Uint', - 4: 'WGPUTextureFormat_R8Sint', - 5: 'WGPUTextureFormat_R16Uint', - 6: 'WGPUTextureFormat_R16Sint', - 7: 'WGPUTextureFormat_R16Float', - 8: 'WGPUTextureFormat_RG8Unorm', - 9: 'WGPUTextureFormat_RG8Snorm', - 10: 'WGPUTextureFormat_RG8Uint', - 11: 'WGPUTextureFormat_RG8Sint', - 12: 'WGPUTextureFormat_R32Float', - 13: 'WGPUTextureFormat_R32Uint', - 14: 'WGPUTextureFormat_R32Sint', - 15: 'WGPUTextureFormat_RG16Uint', - 16: 'WGPUTextureFormat_RG16Sint', - 17: 'WGPUTextureFormat_RG16Float', - 18: 'WGPUTextureFormat_RGBA8Unorm', - 19: 'WGPUTextureFormat_RGBA8UnormSrgb', - 20: 'WGPUTextureFormat_RGBA8Snorm', - 21: 'WGPUTextureFormat_RGBA8Uint', - 22: 'WGPUTextureFormat_RGBA8Sint', - 23: 'WGPUTextureFormat_BGRA8Unorm', - 24: 'WGPUTextureFormat_BGRA8UnormSrgb', - 25: 'WGPUTextureFormat_RGB10A2Uint', - 26: 'WGPUTextureFormat_RGB10A2Unorm', - 27: 'WGPUTextureFormat_RG11B10Ufloat', - 28: 'WGPUTextureFormat_RGB9E5Ufloat', - 29: 'WGPUTextureFormat_RG32Float', - 30: 'WGPUTextureFormat_RG32Uint', - 31: 'WGPUTextureFormat_RG32Sint', - 32: 'WGPUTextureFormat_RGBA16Uint', - 33: 'WGPUTextureFormat_RGBA16Sint', - 34: 'WGPUTextureFormat_RGBA16Float', - 35: 'WGPUTextureFormat_RGBA32Float', - 36: 'WGPUTextureFormat_RGBA32Uint', - 37: 'WGPUTextureFormat_RGBA32Sint', - 38: 'WGPUTextureFormat_Stencil8', - 39: 'WGPUTextureFormat_Depth16Unorm', - 40: 'WGPUTextureFormat_Depth24Plus', - 41: 'WGPUTextureFormat_Depth24PlusStencil8', - 42: 'WGPUTextureFormat_Depth32Float', - 43: 'WGPUTextureFormat_Depth32FloatStencil8', - 44: 'WGPUTextureFormat_BC1RGBAUnorm', - 45: 'WGPUTextureFormat_BC1RGBAUnormSrgb', - 46: 'WGPUTextureFormat_BC2RGBAUnorm', - 47: 'WGPUTextureFormat_BC2RGBAUnormSrgb', - 48: 'WGPUTextureFormat_BC3RGBAUnorm', - 49: 'WGPUTextureFormat_BC3RGBAUnormSrgb', - 50: 'WGPUTextureFormat_BC4RUnorm', - 51: 'WGPUTextureFormat_BC4RSnorm', - 52: 'WGPUTextureFormat_BC5RGUnorm', - 53: 'WGPUTextureFormat_BC5RGSnorm', - 54: 'WGPUTextureFormat_BC6HRGBUfloat', - 55: 'WGPUTextureFormat_BC6HRGBFloat', - 56: 'WGPUTextureFormat_BC7RGBAUnorm', - 57: 'WGPUTextureFormat_BC7RGBAUnormSrgb', - 58: 'WGPUTextureFormat_ETC2RGB8Unorm', - 59: 'WGPUTextureFormat_ETC2RGB8UnormSrgb', - 60: 'WGPUTextureFormat_ETC2RGB8A1Unorm', - 61: 'WGPUTextureFormat_ETC2RGB8A1UnormSrgb', - 62: 'WGPUTextureFormat_ETC2RGBA8Unorm', - 63: 'WGPUTextureFormat_ETC2RGBA8UnormSrgb', - 64: 'WGPUTextureFormat_EACR11Unorm', - 65: 'WGPUTextureFormat_EACR11Snorm', - 66: 'WGPUTextureFormat_EACRG11Unorm', - 67: 'WGPUTextureFormat_EACRG11Snorm', - 68: 'WGPUTextureFormat_ASTC4x4Unorm', - 69: 'WGPUTextureFormat_ASTC4x4UnormSrgb', - 70: 'WGPUTextureFormat_ASTC5x4Unorm', - 71: 'WGPUTextureFormat_ASTC5x4UnormSrgb', - 72: 'WGPUTextureFormat_ASTC5x5Unorm', - 73: 'WGPUTextureFormat_ASTC5x5UnormSrgb', - 74: 'WGPUTextureFormat_ASTC6x5Unorm', - 75: 'WGPUTextureFormat_ASTC6x5UnormSrgb', - 76: 'WGPUTextureFormat_ASTC6x6Unorm', - 77: 'WGPUTextureFormat_ASTC6x6UnormSrgb', - 78: 'WGPUTextureFormat_ASTC8x5Unorm', - 79: 'WGPUTextureFormat_ASTC8x5UnormSrgb', - 80: 'WGPUTextureFormat_ASTC8x6Unorm', - 81: 'WGPUTextureFormat_ASTC8x6UnormSrgb', - 82: 'WGPUTextureFormat_ASTC8x8Unorm', - 83: 'WGPUTextureFormat_ASTC8x8UnormSrgb', - 84: 'WGPUTextureFormat_ASTC10x5Unorm', - 85: 'WGPUTextureFormat_ASTC10x5UnormSrgb', - 86: 'WGPUTextureFormat_ASTC10x6Unorm', - 87: 'WGPUTextureFormat_ASTC10x6UnormSrgb', - 88: 'WGPUTextureFormat_ASTC10x8Unorm', - 89: 'WGPUTextureFormat_ASTC10x8UnormSrgb', - 90: 'WGPUTextureFormat_ASTC10x10Unorm', - 91: 'WGPUTextureFormat_ASTC10x10UnormSrgb', - 92: 'WGPUTextureFormat_ASTC12x10Unorm', - 93: 'WGPUTextureFormat_ASTC12x10UnormSrgb', - 94: 'WGPUTextureFormat_ASTC12x12Unorm', - 95: 'WGPUTextureFormat_ASTC12x12UnormSrgb', - 327680: 'WGPUTextureFormat_R16Unorm', - 327681: 'WGPUTextureFormat_RG16Unorm', - 327682: 'WGPUTextureFormat_RGBA16Unorm', - 327683: 'WGPUTextureFormat_R16Snorm', - 327684: 'WGPUTextureFormat_RG16Snorm', - 327685: 'WGPUTextureFormat_RGBA16Snorm', - 327686: 'WGPUTextureFormat_R8BG8Biplanar420Unorm', - 327687: 'WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm', - 327688: 'WGPUTextureFormat_R8BG8A8Triplanar420Unorm', - 327689: 'WGPUTextureFormat_R8BG8Biplanar422Unorm', - 327690: 'WGPUTextureFormat_R8BG8Biplanar444Unorm', - 327691: 'WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm', - 327692: 'WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm', - 327693: 'WGPUTextureFormat_External', - 2147483647: 'WGPUTextureFormat_Force32', -} -WGPUTextureFormat_Undefined = 0 -WGPUTextureFormat_R8Unorm = 1 -WGPUTextureFormat_R8Snorm = 2 -WGPUTextureFormat_R8Uint = 3 -WGPUTextureFormat_R8Sint = 4 -WGPUTextureFormat_R16Uint = 5 -WGPUTextureFormat_R16Sint = 6 -WGPUTextureFormat_R16Float = 7 -WGPUTextureFormat_RG8Unorm = 8 -WGPUTextureFormat_RG8Snorm = 9 -WGPUTextureFormat_RG8Uint = 10 -WGPUTextureFormat_RG8Sint = 11 -WGPUTextureFormat_R32Float = 12 -WGPUTextureFormat_R32Uint = 13 -WGPUTextureFormat_R32Sint = 14 -WGPUTextureFormat_RG16Uint = 15 -WGPUTextureFormat_RG16Sint = 16 -WGPUTextureFormat_RG16Float = 17 -WGPUTextureFormat_RGBA8Unorm = 18 -WGPUTextureFormat_RGBA8UnormSrgb = 19 -WGPUTextureFormat_RGBA8Snorm = 20 -WGPUTextureFormat_RGBA8Uint = 21 -WGPUTextureFormat_RGBA8Sint = 22 -WGPUTextureFormat_BGRA8Unorm = 23 -WGPUTextureFormat_BGRA8UnormSrgb = 24 -WGPUTextureFormat_RGB10A2Uint = 25 -WGPUTextureFormat_RGB10A2Unorm = 26 -WGPUTextureFormat_RG11B10Ufloat = 27 -WGPUTextureFormat_RGB9E5Ufloat = 28 -WGPUTextureFormat_RG32Float = 29 -WGPUTextureFormat_RG32Uint = 30 -WGPUTextureFormat_RG32Sint = 31 -WGPUTextureFormat_RGBA16Uint = 32 -WGPUTextureFormat_RGBA16Sint = 33 -WGPUTextureFormat_RGBA16Float = 34 -WGPUTextureFormat_RGBA32Float = 35 -WGPUTextureFormat_RGBA32Uint = 36 -WGPUTextureFormat_RGBA32Sint = 37 -WGPUTextureFormat_Stencil8 = 38 -WGPUTextureFormat_Depth16Unorm = 39 -WGPUTextureFormat_Depth24Plus = 40 -WGPUTextureFormat_Depth24PlusStencil8 = 41 -WGPUTextureFormat_Depth32Float = 42 -WGPUTextureFormat_Depth32FloatStencil8 = 43 -WGPUTextureFormat_BC1RGBAUnorm = 44 -WGPUTextureFormat_BC1RGBAUnormSrgb = 45 -WGPUTextureFormat_BC2RGBAUnorm = 46 -WGPUTextureFormat_BC2RGBAUnormSrgb = 47 -WGPUTextureFormat_BC3RGBAUnorm = 48 -WGPUTextureFormat_BC3RGBAUnormSrgb = 49 -WGPUTextureFormat_BC4RUnorm = 50 -WGPUTextureFormat_BC4RSnorm = 51 -WGPUTextureFormat_BC5RGUnorm = 52 -WGPUTextureFormat_BC5RGSnorm = 53 -WGPUTextureFormat_BC6HRGBUfloat = 54 -WGPUTextureFormat_BC6HRGBFloat = 55 -WGPUTextureFormat_BC7RGBAUnorm = 56 -WGPUTextureFormat_BC7RGBAUnormSrgb = 57 -WGPUTextureFormat_ETC2RGB8Unorm = 58 -WGPUTextureFormat_ETC2RGB8UnormSrgb = 59 -WGPUTextureFormat_ETC2RGB8A1Unorm = 60 -WGPUTextureFormat_ETC2RGB8A1UnormSrgb = 61 -WGPUTextureFormat_ETC2RGBA8Unorm = 62 -WGPUTextureFormat_ETC2RGBA8UnormSrgb = 63 -WGPUTextureFormat_EACR11Unorm = 64 -WGPUTextureFormat_EACR11Snorm = 65 -WGPUTextureFormat_EACRG11Unorm = 66 -WGPUTextureFormat_EACRG11Snorm = 67 -WGPUTextureFormat_ASTC4x4Unorm = 68 -WGPUTextureFormat_ASTC4x4UnormSrgb = 69 -WGPUTextureFormat_ASTC5x4Unorm = 70 -WGPUTextureFormat_ASTC5x4UnormSrgb = 71 -WGPUTextureFormat_ASTC5x5Unorm = 72 -WGPUTextureFormat_ASTC5x5UnormSrgb = 73 -WGPUTextureFormat_ASTC6x5Unorm = 74 -WGPUTextureFormat_ASTC6x5UnormSrgb = 75 -WGPUTextureFormat_ASTC6x6Unorm = 76 -WGPUTextureFormat_ASTC6x6UnormSrgb = 77 -WGPUTextureFormat_ASTC8x5Unorm = 78 -WGPUTextureFormat_ASTC8x5UnormSrgb = 79 -WGPUTextureFormat_ASTC8x6Unorm = 80 -WGPUTextureFormat_ASTC8x6UnormSrgb = 81 -WGPUTextureFormat_ASTC8x8Unorm = 82 -WGPUTextureFormat_ASTC8x8UnormSrgb = 83 -WGPUTextureFormat_ASTC10x5Unorm = 84 -WGPUTextureFormat_ASTC10x5UnormSrgb = 85 -WGPUTextureFormat_ASTC10x6Unorm = 86 -WGPUTextureFormat_ASTC10x6UnormSrgb = 87 -WGPUTextureFormat_ASTC10x8Unorm = 88 -WGPUTextureFormat_ASTC10x8UnormSrgb = 89 -WGPUTextureFormat_ASTC10x10Unorm = 90 -WGPUTextureFormat_ASTC10x10UnormSrgb = 91 -WGPUTextureFormat_ASTC12x10Unorm = 92 -WGPUTextureFormat_ASTC12x10UnormSrgb = 93 -WGPUTextureFormat_ASTC12x12Unorm = 94 -WGPUTextureFormat_ASTC12x12UnormSrgb = 95 -WGPUTextureFormat_R16Unorm = 327680 -WGPUTextureFormat_RG16Unorm = 327681 -WGPUTextureFormat_RGBA16Unorm = 327682 -WGPUTextureFormat_R16Snorm = 327683 -WGPUTextureFormat_RG16Snorm = 327684 -WGPUTextureFormat_RGBA16Snorm = 327685 -WGPUTextureFormat_R8BG8Biplanar420Unorm = 327686 -WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm = 327687 -WGPUTextureFormat_R8BG8A8Triplanar420Unorm = 327688 -WGPUTextureFormat_R8BG8Biplanar422Unorm = 327689 -WGPUTextureFormat_R8BG8Biplanar444Unorm = 327690 -WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm = 327691 -WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm = 327692 -WGPUTextureFormat_External = 327693 -WGPUTextureFormat_Force32 = 2147483647 -WGPUTextureFormat = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureSampleType' -WGPUTextureSampleType__enumvalues = { - 0: 'WGPUTextureSampleType_BindingNotUsed', - 1: 'WGPUTextureSampleType_Float', - 2: 'WGPUTextureSampleType_UnfilterableFloat', - 3: 'WGPUTextureSampleType_Depth', - 4: 'WGPUTextureSampleType_Sint', - 5: 'WGPUTextureSampleType_Uint', - 2147483647: 'WGPUTextureSampleType_Force32', -} -WGPUTextureSampleType_BindingNotUsed = 0 -WGPUTextureSampleType_Float = 1 -WGPUTextureSampleType_UnfilterableFloat = 2 -WGPUTextureSampleType_Depth = 3 -WGPUTextureSampleType_Sint = 4 -WGPUTextureSampleType_Uint = 5 -WGPUTextureSampleType_Force32 = 2147483647 -WGPUTextureSampleType = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUTextureViewDimension' -WGPUTextureViewDimension__enumvalues = { - 0: 'WGPUTextureViewDimension_Undefined', - 1: 'WGPUTextureViewDimension_1D', - 2: 'WGPUTextureViewDimension_2D', - 3: 'WGPUTextureViewDimension_2DArray', - 4: 'WGPUTextureViewDimension_Cube', - 5: 'WGPUTextureViewDimension_CubeArray', - 6: 'WGPUTextureViewDimension_3D', - 2147483647: 'WGPUTextureViewDimension_Force32', -} -WGPUTextureViewDimension_Undefined = 0 -WGPUTextureViewDimension_1D = 1 -WGPUTextureViewDimension_2D = 2 -WGPUTextureViewDimension_2DArray = 3 -WGPUTextureViewDimension_Cube = 4 -WGPUTextureViewDimension_CubeArray = 5 -WGPUTextureViewDimension_3D = 6 -WGPUTextureViewDimension_Force32 = 2147483647 -WGPUTextureViewDimension = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUVertexFormat' -WGPUVertexFormat__enumvalues = { - 1: 'WGPUVertexFormat_Uint8', - 2: 'WGPUVertexFormat_Uint8x2', - 3: 'WGPUVertexFormat_Uint8x4', - 4: 'WGPUVertexFormat_Sint8', - 5: 'WGPUVertexFormat_Sint8x2', - 6: 'WGPUVertexFormat_Sint8x4', - 7: 'WGPUVertexFormat_Unorm8', - 8: 'WGPUVertexFormat_Unorm8x2', - 9: 'WGPUVertexFormat_Unorm8x4', - 10: 'WGPUVertexFormat_Snorm8', - 11: 'WGPUVertexFormat_Snorm8x2', - 12: 'WGPUVertexFormat_Snorm8x4', - 13: 'WGPUVertexFormat_Uint16', - 14: 'WGPUVertexFormat_Uint16x2', - 15: 'WGPUVertexFormat_Uint16x4', - 16: 'WGPUVertexFormat_Sint16', - 17: 'WGPUVertexFormat_Sint16x2', - 18: 'WGPUVertexFormat_Sint16x4', - 19: 'WGPUVertexFormat_Unorm16', - 20: 'WGPUVertexFormat_Unorm16x2', - 21: 'WGPUVertexFormat_Unorm16x4', - 22: 'WGPUVertexFormat_Snorm16', - 23: 'WGPUVertexFormat_Snorm16x2', - 24: 'WGPUVertexFormat_Snorm16x4', - 25: 'WGPUVertexFormat_Float16', - 26: 'WGPUVertexFormat_Float16x2', - 27: 'WGPUVertexFormat_Float16x4', - 28: 'WGPUVertexFormat_Float32', - 29: 'WGPUVertexFormat_Float32x2', - 30: 'WGPUVertexFormat_Float32x3', - 31: 'WGPUVertexFormat_Float32x4', - 32: 'WGPUVertexFormat_Uint32', - 33: 'WGPUVertexFormat_Uint32x2', - 34: 'WGPUVertexFormat_Uint32x3', - 35: 'WGPUVertexFormat_Uint32x4', - 36: 'WGPUVertexFormat_Sint32', - 37: 'WGPUVertexFormat_Sint32x2', - 38: 'WGPUVertexFormat_Sint32x3', - 39: 'WGPUVertexFormat_Sint32x4', - 40: 'WGPUVertexFormat_Unorm10_10_10_2', - 41: 'WGPUVertexFormat_Unorm8x4BGRA', - 2147483647: 'WGPUVertexFormat_Force32', -} -WGPUVertexFormat_Uint8 = 1 -WGPUVertexFormat_Uint8x2 = 2 -WGPUVertexFormat_Uint8x4 = 3 -WGPUVertexFormat_Sint8 = 4 -WGPUVertexFormat_Sint8x2 = 5 -WGPUVertexFormat_Sint8x4 = 6 -WGPUVertexFormat_Unorm8 = 7 -WGPUVertexFormat_Unorm8x2 = 8 -WGPUVertexFormat_Unorm8x4 = 9 -WGPUVertexFormat_Snorm8 = 10 -WGPUVertexFormat_Snorm8x2 = 11 -WGPUVertexFormat_Snorm8x4 = 12 -WGPUVertexFormat_Uint16 = 13 -WGPUVertexFormat_Uint16x2 = 14 -WGPUVertexFormat_Uint16x4 = 15 -WGPUVertexFormat_Sint16 = 16 -WGPUVertexFormat_Sint16x2 = 17 -WGPUVertexFormat_Sint16x4 = 18 -WGPUVertexFormat_Unorm16 = 19 -WGPUVertexFormat_Unorm16x2 = 20 -WGPUVertexFormat_Unorm16x4 = 21 -WGPUVertexFormat_Snorm16 = 22 -WGPUVertexFormat_Snorm16x2 = 23 -WGPUVertexFormat_Snorm16x4 = 24 -WGPUVertexFormat_Float16 = 25 -WGPUVertexFormat_Float16x2 = 26 -WGPUVertexFormat_Float16x4 = 27 -WGPUVertexFormat_Float32 = 28 -WGPUVertexFormat_Float32x2 = 29 -WGPUVertexFormat_Float32x3 = 30 -WGPUVertexFormat_Float32x4 = 31 -WGPUVertexFormat_Uint32 = 32 -WGPUVertexFormat_Uint32x2 = 33 -WGPUVertexFormat_Uint32x3 = 34 -WGPUVertexFormat_Uint32x4 = 35 -WGPUVertexFormat_Sint32 = 36 -WGPUVertexFormat_Sint32x2 = 37 -WGPUVertexFormat_Sint32x3 = 38 -WGPUVertexFormat_Sint32x4 = 39 -WGPUVertexFormat_Unorm10_10_10_2 = 40 -WGPUVertexFormat_Unorm8x4BGRA = 41 -WGPUVertexFormat_Force32 = 2147483647 -WGPUVertexFormat = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUVertexStepMode' -WGPUVertexStepMode__enumvalues = { - 0: 'WGPUVertexStepMode_Undefined', - 1: 'WGPUVertexStepMode_Vertex', - 2: 'WGPUVertexStepMode_Instance', - 2147483647: 'WGPUVertexStepMode_Force32', -} -WGPUVertexStepMode_Undefined = 0 -WGPUVertexStepMode_Vertex = 1 -WGPUVertexStepMode_Instance = 2 -WGPUVertexStepMode_Force32 = 2147483647 -WGPUVertexStepMode = ctypes.c_uint32 # enum - -# values for enumeration 'WGPUWaitStatus' -WGPUWaitStatus__enumvalues = { - 1: 'WGPUWaitStatus_Success', - 2: 'WGPUWaitStatus_TimedOut', - 3: 'WGPUWaitStatus_UnsupportedTimeout', - 4: 'WGPUWaitStatus_UnsupportedCount', - 5: 'WGPUWaitStatus_UnsupportedMixedSources', - 6: 'WGPUWaitStatus_Unknown', - 2147483647: 'WGPUWaitStatus_Force32', -} -WGPUWaitStatus_Success = 1 -WGPUWaitStatus_TimedOut = 2 -WGPUWaitStatus_UnsupportedTimeout = 3 -WGPUWaitStatus_UnsupportedCount = 4 -WGPUWaitStatus_UnsupportedMixedSources = 5 -WGPUWaitStatus_Unknown = 6 -WGPUWaitStatus_Force32 = 2147483647 -WGPUWaitStatus = ctypes.c_uint32 # enum -WGPUBufferUsage = ctypes.c_uint64 -WGPUBufferUsage_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUBufferUsage_MapRead = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUBufferUsage_MapWrite = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUBufferUsage_CopySrc = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUBufferUsage_CopyDst = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUBufferUsage_Index = 0x0000000000000010 # Variable ctypes.c_uint64 -WGPUBufferUsage_Vertex = 0x0000000000000020 # Variable ctypes.c_uint64 -WGPUBufferUsage_Uniform = 0x0000000000000040 # Variable ctypes.c_uint64 -WGPUBufferUsage_Storage = 0x0000000000000080 # Variable ctypes.c_uint64 -WGPUBufferUsage_Indirect = 0x0000000000000100 # Variable ctypes.c_uint64 -WGPUBufferUsage_QueryResolve = 0x0000000000000200 # Variable ctypes.c_uint64 -WGPUColorWriteMask = ctypes.c_uint64 -WGPUColorWriteMask_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Red = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Green = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Blue = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUColorWriteMask_Alpha = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUColorWriteMask_All = 0x000000000000000F # Variable ctypes.c_uint64 -WGPUHeapProperty = ctypes.c_uint64 -WGPUHeapProperty_DeviceLocal = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostVisible = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostCoherent = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostUncached = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUHeapProperty_HostCached = 0x0000000000000010 # Variable ctypes.c_uint64 -WGPUMapMode = ctypes.c_uint64 -WGPUMapMode_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUMapMode_Read = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUMapMode_Write = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUShaderStage = ctypes.c_uint64 -WGPUShaderStage_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUShaderStage_Vertex = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUShaderStage_Fragment = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUShaderStage_Compute = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUTextureUsage = ctypes.c_uint64 -WGPUTextureUsage_None = 0x0000000000000000 # Variable ctypes.c_uint64 -WGPUTextureUsage_CopySrc = 0x0000000000000001 # Variable ctypes.c_uint64 -WGPUTextureUsage_CopyDst = 0x0000000000000002 # Variable ctypes.c_uint64 -WGPUTextureUsage_TextureBinding = 0x0000000000000004 # Variable ctypes.c_uint64 -WGPUTextureUsage_StorageBinding = 0x0000000000000008 # Variable ctypes.c_uint64 -WGPUTextureUsage_RenderAttachment = 0x0000000000000010 # Variable ctypes.c_uint64 -WGPUTextureUsage_TransientAttachment = 0x0000000000000020 # Variable ctypes.c_uint64 -WGPUTextureUsage_StorageAttachment = 0x0000000000000040 # Variable ctypes.c_uint64 -WGPUBufferMapCallback = ctypes.CFUNCTYPE(None, WGPUBufferMapAsyncStatus, ctypes.POINTER(None)) -WGPUCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(None)) -class struct_WGPUCompilationInfo(Structure): - pass - -WGPUCompilationInfoCallback = ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None)) -class struct_WGPUStringView(Structure): - pass - -struct_WGPUStringView._pack_ = 1 # source:False -struct_WGPUStringView._fields_ = [ - ('data', ctypes.POINTER(ctypes.c_char)), - ('length', ctypes.c_uint64), -] - -WGPUCreateComputePipelineAsyncCallback = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPUCreateRenderPipelineAsyncCallback = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPUDawnLoadCacheDataFunction = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)) -WGPUDawnStoreCacheDataFunction = ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None)) -WGPUDeviceLostCallback = ctypes.CFUNCTYPE(None, WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUDeviceLostCallbackNew = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUErrorCallback = ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None)) -WGPULoggingCallback = ctypes.CFUNCTYPE(None, WGPULoggingType, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUPopErrorScopeCallback = ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None)) -WGPUProc = ctypes.CFUNCTYPE(None) -WGPUQueueWorkDoneCallback = ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None)) -WGPURequestAdapterCallback = ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPURequestDeviceCallback = ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None)) -WGPUBufferMapCallback2 = ctypes.CFUNCTYPE(None, WGPUMapAsyncStatus, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUCompilationInfoCallback2 = ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUCreateComputePipelineAsyncCallback2 = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUCreateRenderPipelineAsyncCallback2 = ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUDeviceLostCallback2 = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUPopErrorScopeCallback2 = ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUQueueWorkDoneCallback2 = ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPURequestAdapterCallback2 = ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPURequestDeviceCallback2 = ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -WGPUUncapturedErrorCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None)) -class struct_WGPUChainedStruct(Structure): - pass - -struct_WGPUChainedStruct._pack_ = 1 # source:False -struct_WGPUChainedStruct._fields_ = [ - ('next', ctypes.POINTER(struct_WGPUChainedStruct)), - ('sType', WGPUSType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUChainedStruct = struct_WGPUChainedStruct -class struct_WGPUChainedStructOut(Structure): - pass - -struct_WGPUChainedStructOut._pack_ = 1 # source:False -struct_WGPUChainedStructOut._fields_ = [ - ('next', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('sType', WGPUSType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUChainedStructOut = struct_WGPUChainedStructOut -class struct_WGPUBufferMapCallbackInfo2(Structure): - pass - -struct_WGPUBufferMapCallbackInfo2._pack_ = 1 # source:False -struct_WGPUBufferMapCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUMapAsyncStatus, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUBufferMapCallbackInfo2 = struct_WGPUBufferMapCallbackInfo2 -class struct_WGPUCompilationInfoCallbackInfo2(Structure): - pass - -struct_WGPUCompilationInfoCallbackInfo2._pack_ = 1 # source:False -struct_WGPUCompilationInfoCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUCompilationInfoCallbackInfo2 = struct_WGPUCompilationInfoCallbackInfo2 -class struct_WGPUCreateComputePipelineAsyncCallbackInfo2(Structure): - pass - -struct_WGPUCreateComputePipelineAsyncCallbackInfo2._pack_ = 1 # source:False -struct_WGPUCreateComputePipelineAsyncCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUCreateComputePipelineAsyncCallbackInfo2 = struct_WGPUCreateComputePipelineAsyncCallbackInfo2 -class struct_WGPUCreateRenderPipelineAsyncCallbackInfo2(Structure): - pass - -struct_WGPUCreateRenderPipelineAsyncCallbackInfo2._pack_ = 1 # source:False -struct_WGPUCreateRenderPipelineAsyncCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUCreateRenderPipelineAsyncCallbackInfo2 = struct_WGPUCreateRenderPipelineAsyncCallbackInfo2 -class struct_WGPUDeviceLostCallbackInfo2(Structure): - pass - -struct_WGPUDeviceLostCallbackInfo2._pack_ = 1 # source:False -struct_WGPUDeviceLostCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUDeviceLostCallbackInfo2 = struct_WGPUDeviceLostCallbackInfo2 -class struct_WGPUPopErrorScopeCallbackInfo2(Structure): - pass - -struct_WGPUPopErrorScopeCallbackInfo2._pack_ = 1 # source:False -struct_WGPUPopErrorScopeCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUPopErrorScopeCallbackInfo2 = struct_WGPUPopErrorScopeCallbackInfo2 -class struct_WGPUQueueWorkDoneCallbackInfo2(Structure): - pass - -struct_WGPUQueueWorkDoneCallbackInfo2._pack_ = 1 # source:False -struct_WGPUQueueWorkDoneCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUQueueWorkDoneCallbackInfo2 = struct_WGPUQueueWorkDoneCallbackInfo2 -class struct_WGPURequestAdapterCallbackInfo2(Structure): - pass - -struct_WGPURequestAdapterCallbackInfo2._pack_ = 1 # source:False -struct_WGPURequestAdapterCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPURequestAdapterCallbackInfo2 = struct_WGPURequestAdapterCallbackInfo2 -class struct_WGPURequestDeviceCallbackInfo2(Structure): - pass - -struct_WGPURequestDeviceCallbackInfo2._pack_ = 1 # source:False -struct_WGPURequestDeviceCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPURequestDeviceCallbackInfo2 = struct_WGPURequestDeviceCallbackInfo2 -class struct_WGPUUncapturedErrorCallbackInfo2(Structure): - pass - -struct_WGPUUncapturedErrorCallbackInfo2._pack_ = 1 # source:False -struct_WGPUUncapturedErrorCallbackInfo2._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None), ctypes.POINTER(None))), - ('userdata1', ctypes.POINTER(None)), - ('userdata2', ctypes.POINTER(None)), -] - -WGPUUncapturedErrorCallbackInfo2 = struct_WGPUUncapturedErrorCallbackInfo2 -class struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER(Structure): - pass - -struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER._pack_ = 1 # source:False +class struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER(Struct): pass struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER._fields_ = [ - ('unused', ctypes.c_uint32), + ('unused', WGPUBool), ] +class struct_WGPUAdapterPropertiesD3D(Struct): pass +class struct_WGPUChainedStructOut(Struct): pass +WGPUChainedStructOut = struct_WGPUChainedStructOut +enum_WGPUSType = CEnum(ctypes.c_uint32) +WGPUSType_ShaderSourceSPIRV = enum_WGPUSType.define('WGPUSType_ShaderSourceSPIRV', 1) +WGPUSType_ShaderSourceWGSL = enum_WGPUSType.define('WGPUSType_ShaderSourceWGSL', 2) +WGPUSType_RenderPassMaxDrawCount = enum_WGPUSType.define('WGPUSType_RenderPassMaxDrawCount', 3) +WGPUSType_SurfaceSourceMetalLayer = enum_WGPUSType.define('WGPUSType_SurfaceSourceMetalLayer', 4) +WGPUSType_SurfaceSourceWindowsHWND = enum_WGPUSType.define('WGPUSType_SurfaceSourceWindowsHWND', 5) +WGPUSType_SurfaceSourceXlibWindow = enum_WGPUSType.define('WGPUSType_SurfaceSourceXlibWindow', 6) +WGPUSType_SurfaceSourceWaylandSurface = enum_WGPUSType.define('WGPUSType_SurfaceSourceWaylandSurface', 7) +WGPUSType_SurfaceSourceAndroidNativeWindow = enum_WGPUSType.define('WGPUSType_SurfaceSourceAndroidNativeWindow', 8) +WGPUSType_SurfaceSourceXCBWindow = enum_WGPUSType.define('WGPUSType_SurfaceSourceXCBWindow', 9) +WGPUSType_AdapterPropertiesSubgroups = enum_WGPUSType.define('WGPUSType_AdapterPropertiesSubgroups', 10) +WGPUSType_TextureBindingViewDimensionDescriptor = enum_WGPUSType.define('WGPUSType_TextureBindingViewDimensionDescriptor', 131072) +WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten = enum_WGPUSType.define('WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten', 262144) +WGPUSType_SurfaceDescriptorFromWindowsCoreWindow = enum_WGPUSType.define('WGPUSType_SurfaceDescriptorFromWindowsCoreWindow', 327680) +WGPUSType_ExternalTextureBindingEntry = enum_WGPUSType.define('WGPUSType_ExternalTextureBindingEntry', 327681) +WGPUSType_ExternalTextureBindingLayout = enum_WGPUSType.define('WGPUSType_ExternalTextureBindingLayout', 327682) +WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel = enum_WGPUSType.define('WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel', 327683) +WGPUSType_DawnTextureInternalUsageDescriptor = enum_WGPUSType.define('WGPUSType_DawnTextureInternalUsageDescriptor', 327684) +WGPUSType_DawnEncoderInternalUsageDescriptor = enum_WGPUSType.define('WGPUSType_DawnEncoderInternalUsageDescriptor', 327685) +WGPUSType_DawnInstanceDescriptor = enum_WGPUSType.define('WGPUSType_DawnInstanceDescriptor', 327686) +WGPUSType_DawnCacheDeviceDescriptor = enum_WGPUSType.define('WGPUSType_DawnCacheDeviceDescriptor', 327687) +WGPUSType_DawnAdapterPropertiesPowerPreference = enum_WGPUSType.define('WGPUSType_DawnAdapterPropertiesPowerPreference', 327688) +WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient = enum_WGPUSType.define('WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient', 327689) +WGPUSType_DawnTogglesDescriptor = enum_WGPUSType.define('WGPUSType_DawnTogglesDescriptor', 327690) +WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor = enum_WGPUSType.define('WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor', 327691) +WGPUSType_RequestAdapterOptionsLUID = enum_WGPUSType.define('WGPUSType_RequestAdapterOptionsLUID', 327692) +WGPUSType_RequestAdapterOptionsGetGLProc = enum_WGPUSType.define('WGPUSType_RequestAdapterOptionsGetGLProc', 327693) +WGPUSType_RequestAdapterOptionsD3D11Device = enum_WGPUSType.define('WGPUSType_RequestAdapterOptionsD3D11Device', 327694) +WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled = enum_WGPUSType.define('WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled', 327695) +WGPUSType_RenderPassPixelLocalStorage = enum_WGPUSType.define('WGPUSType_RenderPassPixelLocalStorage', 327696) +WGPUSType_PipelineLayoutPixelLocalStorage = enum_WGPUSType.define('WGPUSType_PipelineLayoutPixelLocalStorage', 327697) +WGPUSType_BufferHostMappedPointer = enum_WGPUSType.define('WGPUSType_BufferHostMappedPointer', 327698) +WGPUSType_DawnExperimentalSubgroupLimits = enum_WGPUSType.define('WGPUSType_DawnExperimentalSubgroupLimits', 327699) +WGPUSType_AdapterPropertiesMemoryHeaps = enum_WGPUSType.define('WGPUSType_AdapterPropertiesMemoryHeaps', 327700) +WGPUSType_AdapterPropertiesD3D = enum_WGPUSType.define('WGPUSType_AdapterPropertiesD3D', 327701) +WGPUSType_AdapterPropertiesVk = enum_WGPUSType.define('WGPUSType_AdapterPropertiesVk', 327702) +WGPUSType_DawnWireWGSLControl = enum_WGPUSType.define('WGPUSType_DawnWireWGSLControl', 327703) +WGPUSType_DawnWGSLBlocklist = enum_WGPUSType.define('WGPUSType_DawnWGSLBlocklist', 327704) +WGPUSType_DrmFormatCapabilities = enum_WGPUSType.define('WGPUSType_DrmFormatCapabilities', 327705) +WGPUSType_ShaderModuleCompilationOptions = enum_WGPUSType.define('WGPUSType_ShaderModuleCompilationOptions', 327706) +WGPUSType_ColorTargetStateExpandResolveTextureDawn = enum_WGPUSType.define('WGPUSType_ColorTargetStateExpandResolveTextureDawn', 327707) +WGPUSType_RenderPassDescriptorExpandResolveRect = enum_WGPUSType.define('WGPUSType_RenderPassDescriptorExpandResolveRect', 327708) +WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor', 327709) +WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor', 327710) +WGPUSType_SharedTextureMemoryDmaBufDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryDmaBufDescriptor', 327711) +WGPUSType_SharedTextureMemoryOpaqueFDDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryOpaqueFDDescriptor', 327712) +WGPUSType_SharedTextureMemoryZirconHandleDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryZirconHandleDescriptor', 327713) +WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor', 327714) +WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor', 327715) +WGPUSType_SharedTextureMemoryIOSurfaceDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryIOSurfaceDescriptor', 327716) +WGPUSType_SharedTextureMemoryEGLImageDescriptor = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryEGLImageDescriptor', 327717) +WGPUSType_SharedTextureMemoryInitializedBeginState = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryInitializedBeginState', 327718) +WGPUSType_SharedTextureMemoryInitializedEndState = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryInitializedEndState', 327719) +WGPUSType_SharedTextureMemoryVkImageLayoutBeginState = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryVkImageLayoutBeginState', 327720) +WGPUSType_SharedTextureMemoryVkImageLayoutEndState = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryVkImageLayoutEndState', 327721) +WGPUSType_SharedTextureMemoryD3DSwapchainBeginState = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryD3DSwapchainBeginState', 327722) +WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor = enum_WGPUSType.define('WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor', 327723) +WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo = enum_WGPUSType.define('WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo', 327724) +WGPUSType_SharedFenceSyncFDDescriptor = enum_WGPUSType.define('WGPUSType_SharedFenceSyncFDDescriptor', 327725) +WGPUSType_SharedFenceSyncFDExportInfo = enum_WGPUSType.define('WGPUSType_SharedFenceSyncFDExportInfo', 327726) +WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor = enum_WGPUSType.define('WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor', 327727) +WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo = enum_WGPUSType.define('WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo', 327728) +WGPUSType_SharedFenceDXGISharedHandleDescriptor = enum_WGPUSType.define('WGPUSType_SharedFenceDXGISharedHandleDescriptor', 327729) +WGPUSType_SharedFenceDXGISharedHandleExportInfo = enum_WGPUSType.define('WGPUSType_SharedFenceDXGISharedHandleExportInfo', 327730) +WGPUSType_SharedFenceMTLSharedEventDescriptor = enum_WGPUSType.define('WGPUSType_SharedFenceMTLSharedEventDescriptor', 327731) +WGPUSType_SharedFenceMTLSharedEventExportInfo = enum_WGPUSType.define('WGPUSType_SharedFenceMTLSharedEventExportInfo', 327732) +WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor = enum_WGPUSType.define('WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor', 327733) +WGPUSType_StaticSamplerBindingLayout = enum_WGPUSType.define('WGPUSType_StaticSamplerBindingLayout', 327734) +WGPUSType_YCbCrVkDescriptor = enum_WGPUSType.define('WGPUSType_YCbCrVkDescriptor', 327735) +WGPUSType_SharedTextureMemoryAHardwareBufferProperties = enum_WGPUSType.define('WGPUSType_SharedTextureMemoryAHardwareBufferProperties', 327736) +WGPUSType_AHardwareBufferProperties = enum_WGPUSType.define('WGPUSType_AHardwareBufferProperties', 327737) +WGPUSType_DawnExperimentalImmediateDataLimits = enum_WGPUSType.define('WGPUSType_DawnExperimentalImmediateDataLimits', 327738) +WGPUSType_DawnTexelCopyBufferRowAlignmentLimits = enum_WGPUSType.define('WGPUSType_DawnTexelCopyBufferRowAlignmentLimits', 327739) +WGPUSType_Force32 = enum_WGPUSType.define('WGPUSType_Force32', 2147483647) -WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER = struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER -class struct_WGPUAdapterPropertiesD3D(Structure): - pass - -struct_WGPUAdapterPropertiesD3D._pack_ = 1 # source:False +WGPUSType = enum_WGPUSType +struct_WGPUChainedStructOut._fields_ = [ + ('next', ctypes.POINTER(struct_WGPUChainedStructOut)), + ('sType', WGPUSType), +] +uint32_t = ctypes.c_uint32 struct_WGPUAdapterPropertiesD3D._fields_ = [ - ('chain', WGPUChainedStructOut), - ('shaderModel', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('chain', WGPUChainedStructOut), + ('shaderModel', uint32_t), ] - -WGPUAdapterPropertiesD3D = struct_WGPUAdapterPropertiesD3D -class struct_WGPUAdapterPropertiesSubgroups(Structure): - pass - -struct_WGPUAdapterPropertiesSubgroups._pack_ = 1 # source:False +class struct_WGPUAdapterPropertiesSubgroups(Struct): pass struct_WGPUAdapterPropertiesSubgroups._fields_ = [ - ('chain', WGPUChainedStructOut), - ('subgroupMinSize', ctypes.c_uint32), - ('subgroupMaxSize', ctypes.c_uint32), + ('chain', WGPUChainedStructOut), + ('subgroupMinSize', uint32_t), + ('subgroupMaxSize', uint32_t), ] - -WGPUAdapterPropertiesSubgroups = struct_WGPUAdapterPropertiesSubgroups -class struct_WGPUAdapterPropertiesVk(Structure): - pass - -struct_WGPUAdapterPropertiesVk._pack_ = 1 # source:False +class struct_WGPUAdapterPropertiesVk(Struct): pass struct_WGPUAdapterPropertiesVk._fields_ = [ - ('chain', WGPUChainedStructOut), - ('driverVersion', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('chain', WGPUChainedStructOut), + ('driverVersion', uint32_t), ] - -WGPUAdapterPropertiesVk = struct_WGPUAdapterPropertiesVk -class struct_WGPUBindGroupEntry(Structure): - pass - -struct_WGPUBindGroupEntry._pack_ = 1 # source:False +class struct_WGPUBindGroupEntry(Struct): pass +class struct_WGPUChainedStruct(Struct): pass +WGPUChainedStruct = struct_WGPUChainedStruct +struct_WGPUChainedStruct._fields_ = [ + ('next', ctypes.POINTER(struct_WGPUChainedStruct)), + ('sType', WGPUSType), +] +uint64_t = ctypes.c_uint64 struct_WGPUBindGroupEntry._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('binding', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('buffer', ctypes.POINTER(struct_WGPUBufferImpl)), - ('offset', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('sampler', ctypes.POINTER(struct_WGPUSamplerImpl)), - ('textureView', ctypes.POINTER(struct_WGPUTextureViewImpl)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('binding', uint32_t), + ('buffer', WGPUBuffer), + ('offset', uint64_t), + ('size', uint64_t), + ('sampler', WGPUSampler), + ('textureView', WGPUTextureView), ] +class struct_WGPUBlendComponent(Struct): pass +enum_WGPUBlendOperation = CEnum(ctypes.c_uint32) +WGPUBlendOperation_Undefined = enum_WGPUBlendOperation.define('WGPUBlendOperation_Undefined', 0) +WGPUBlendOperation_Add = enum_WGPUBlendOperation.define('WGPUBlendOperation_Add', 1) +WGPUBlendOperation_Subtract = enum_WGPUBlendOperation.define('WGPUBlendOperation_Subtract', 2) +WGPUBlendOperation_ReverseSubtract = enum_WGPUBlendOperation.define('WGPUBlendOperation_ReverseSubtract', 3) +WGPUBlendOperation_Min = enum_WGPUBlendOperation.define('WGPUBlendOperation_Min', 4) +WGPUBlendOperation_Max = enum_WGPUBlendOperation.define('WGPUBlendOperation_Max', 5) +WGPUBlendOperation_Force32 = enum_WGPUBlendOperation.define('WGPUBlendOperation_Force32', 2147483647) -WGPUBindGroupEntry = struct_WGPUBindGroupEntry -class struct_WGPUBlendComponent(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('operation', WGPUBlendOperation), - ('srcFactor', WGPUBlendFactor), - ('dstFactor', WGPUBlendFactor), - ] +WGPUBlendOperation = enum_WGPUBlendOperation +enum_WGPUBlendFactor = CEnum(ctypes.c_uint32) +WGPUBlendFactor_Undefined = enum_WGPUBlendFactor.define('WGPUBlendFactor_Undefined', 0) +WGPUBlendFactor_Zero = enum_WGPUBlendFactor.define('WGPUBlendFactor_Zero', 1) +WGPUBlendFactor_One = enum_WGPUBlendFactor.define('WGPUBlendFactor_One', 2) +WGPUBlendFactor_Src = enum_WGPUBlendFactor.define('WGPUBlendFactor_Src', 3) +WGPUBlendFactor_OneMinusSrc = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusSrc', 4) +WGPUBlendFactor_SrcAlpha = enum_WGPUBlendFactor.define('WGPUBlendFactor_SrcAlpha', 5) +WGPUBlendFactor_OneMinusSrcAlpha = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusSrcAlpha', 6) +WGPUBlendFactor_Dst = enum_WGPUBlendFactor.define('WGPUBlendFactor_Dst', 7) +WGPUBlendFactor_OneMinusDst = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusDst', 8) +WGPUBlendFactor_DstAlpha = enum_WGPUBlendFactor.define('WGPUBlendFactor_DstAlpha', 9) +WGPUBlendFactor_OneMinusDstAlpha = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusDstAlpha', 10) +WGPUBlendFactor_SrcAlphaSaturated = enum_WGPUBlendFactor.define('WGPUBlendFactor_SrcAlphaSaturated', 11) +WGPUBlendFactor_Constant = enum_WGPUBlendFactor.define('WGPUBlendFactor_Constant', 12) +WGPUBlendFactor_OneMinusConstant = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusConstant', 13) +WGPUBlendFactor_Src1 = enum_WGPUBlendFactor.define('WGPUBlendFactor_Src1', 14) +WGPUBlendFactor_OneMinusSrc1 = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusSrc1', 15) +WGPUBlendFactor_Src1Alpha = enum_WGPUBlendFactor.define('WGPUBlendFactor_Src1Alpha', 16) +WGPUBlendFactor_OneMinusSrc1Alpha = enum_WGPUBlendFactor.define('WGPUBlendFactor_OneMinusSrc1Alpha', 17) +WGPUBlendFactor_Force32 = enum_WGPUBlendFactor.define('WGPUBlendFactor_Force32', 2147483647) -WGPUBlendComponent = struct_WGPUBlendComponent -class struct_WGPUBufferBindingLayout(Structure): - pass +WGPUBlendFactor = enum_WGPUBlendFactor +struct_WGPUBlendComponent._fields_ = [ + ('operation', WGPUBlendOperation), + ('srcFactor', WGPUBlendFactor), + ('dstFactor', WGPUBlendFactor), +] +class struct_WGPUBufferBindingLayout(Struct): pass +enum_WGPUBufferBindingType = CEnum(ctypes.c_uint32) +WGPUBufferBindingType_BindingNotUsed = enum_WGPUBufferBindingType.define('WGPUBufferBindingType_BindingNotUsed', 0) +WGPUBufferBindingType_Uniform = enum_WGPUBufferBindingType.define('WGPUBufferBindingType_Uniform', 1) +WGPUBufferBindingType_Storage = enum_WGPUBufferBindingType.define('WGPUBufferBindingType_Storage', 2) +WGPUBufferBindingType_ReadOnlyStorage = enum_WGPUBufferBindingType.define('WGPUBufferBindingType_ReadOnlyStorage', 3) +WGPUBufferBindingType_Force32 = enum_WGPUBufferBindingType.define('WGPUBufferBindingType_Force32', 2147483647) -struct_WGPUBufferBindingLayout._pack_ = 1 # source:False +WGPUBufferBindingType = enum_WGPUBufferBindingType struct_WGPUBufferBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('type', WGPUBufferBindingType), - ('hasDynamicOffset', ctypes.c_uint32), - ('minBindingSize', ctypes.c_uint64), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('type', WGPUBufferBindingType), + ('hasDynamicOffset', WGPUBool), + ('minBindingSize', uint64_t), ] - -WGPUBufferBindingLayout = struct_WGPUBufferBindingLayout -class struct_WGPUBufferHostMappedPointer(Structure): - pass - -struct_WGPUBufferHostMappedPointer._pack_ = 1 # source:False +class struct_WGPUBufferHostMappedPointer(Struct): pass +WGPUCallback = ctypes.CFUNCTYPE(None, ctypes.c_void_p) struct_WGPUBufferHostMappedPointer._fields_ = [ - ('chain', WGPUChainedStruct), - ('pointer', ctypes.POINTER(None)), - ('disposeCallback', ctypes.CFUNCTYPE(None, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), + ('chain', WGPUChainedStruct), + ('pointer', ctypes.c_void_p), + ('disposeCallback', WGPUCallback), + ('userdata', ctypes.c_void_p), ] +class struct_WGPUBufferMapCallbackInfo(Struct): pass +enum_WGPUCallbackMode = CEnum(ctypes.c_uint32) +WGPUCallbackMode_WaitAnyOnly = enum_WGPUCallbackMode.define('WGPUCallbackMode_WaitAnyOnly', 1) +WGPUCallbackMode_AllowProcessEvents = enum_WGPUCallbackMode.define('WGPUCallbackMode_AllowProcessEvents', 2) +WGPUCallbackMode_AllowSpontaneous = enum_WGPUCallbackMode.define('WGPUCallbackMode_AllowSpontaneous', 3) +WGPUCallbackMode_Force32 = enum_WGPUCallbackMode.define('WGPUCallbackMode_Force32', 2147483647) -WGPUBufferHostMappedPointer = struct_WGPUBufferHostMappedPointer -class struct_WGPUBufferMapCallbackInfo(Structure): - pass +WGPUCallbackMode = enum_WGPUCallbackMode +enum_WGPUBufferMapAsyncStatus = CEnum(ctypes.c_uint32) +WGPUBufferMapAsyncStatus_Success = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_Success', 1) +WGPUBufferMapAsyncStatus_InstanceDropped = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_InstanceDropped', 2) +WGPUBufferMapAsyncStatus_ValidationError = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_ValidationError', 3) +WGPUBufferMapAsyncStatus_Unknown = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_Unknown', 4) +WGPUBufferMapAsyncStatus_DeviceLost = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_DeviceLost', 5) +WGPUBufferMapAsyncStatus_DestroyedBeforeCallback = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_DestroyedBeforeCallback', 6) +WGPUBufferMapAsyncStatus_UnmappedBeforeCallback = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_UnmappedBeforeCallback', 7) +WGPUBufferMapAsyncStatus_MappingAlreadyPending = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_MappingAlreadyPending', 8) +WGPUBufferMapAsyncStatus_OffsetOutOfRange = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_OffsetOutOfRange', 9) +WGPUBufferMapAsyncStatus_SizeOutOfRange = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_SizeOutOfRange', 10) +WGPUBufferMapAsyncStatus_Force32 = enum_WGPUBufferMapAsyncStatus.define('WGPUBufferMapAsyncStatus_Force32', 2147483647) -struct_WGPUBufferMapCallbackInfo._pack_ = 1 # source:False +WGPUBufferMapCallback = ctypes.CFUNCTYPE(None, enum_WGPUBufferMapAsyncStatus, ctypes.c_void_p) struct_WGPUBufferMapCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUBufferMapAsyncStatus, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUBufferMapCallback), + ('userdata', ctypes.c_void_p), ] - -WGPUBufferMapCallbackInfo = struct_WGPUBufferMapCallbackInfo -class struct_WGPUColor(Structure): - pass - -struct_WGPUColor._pack_ = 1 # source:False +class struct_WGPUColor(Struct): pass struct_WGPUColor._fields_ = [ - ('r', ctypes.c_double), - ('g', ctypes.c_double), - ('b', ctypes.c_double), - ('a', ctypes.c_double), + ('r', ctypes.c_double), + ('g', ctypes.c_double), + ('b', ctypes.c_double), + ('a', ctypes.c_double), ] - -WGPUColor = struct_WGPUColor -class struct_WGPUColorTargetStateExpandResolveTextureDawn(Structure): - pass - -struct_WGPUColorTargetStateExpandResolveTextureDawn._pack_ = 1 # source:False +class struct_WGPUColorTargetStateExpandResolveTextureDawn(Struct): pass struct_WGPUColorTargetStateExpandResolveTextureDawn._fields_ = [ - ('chain', WGPUChainedStruct), - ('enabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUColorTargetStateExpandResolveTextureDawn = struct_WGPUColorTargetStateExpandResolveTextureDawn -class struct_WGPUCompilationInfoCallbackInfo(Structure): - pass - -struct_WGPUCompilationInfoCallbackInfo._pack_ = 1 # source:False -struct_WGPUCompilationInfoCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUCompilationInfoCallbackInfo = struct_WGPUCompilationInfoCallbackInfo -class struct_WGPUComputePassTimestampWrites(Structure): - pass - -struct_WGPUComputePassTimestampWrites._pack_ = 1 # source:False -struct_WGPUComputePassTimestampWrites._fields_ = [ - ('querySet', ctypes.POINTER(struct_WGPUQuerySetImpl)), - ('beginningOfPassWriteIndex', ctypes.c_uint32), - ('endOfPassWriteIndex', ctypes.c_uint32), -] - -WGPUComputePassTimestampWrites = struct_WGPUComputePassTimestampWrites -class struct_WGPUCopyTextureForBrowserOptions(Structure): - pass - -struct_WGPUCopyTextureForBrowserOptions._pack_ = 1 # source:False -struct_WGPUCopyTextureForBrowserOptions._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('flipY', ctypes.c_uint32), - ('needsColorSpaceConversion', ctypes.c_uint32), - ('srcAlphaMode', WGPUAlphaMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('conversionMatrix', ctypes.POINTER(ctypes.c_float)), - ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('dstAlphaMode', WGPUAlphaMode), - ('internalUsage', ctypes.c_uint32), -] - -WGPUCopyTextureForBrowserOptions = struct_WGPUCopyTextureForBrowserOptions -class struct_WGPUCreateComputePipelineAsyncCallbackInfo(Structure): - pass - -struct_WGPUCreateComputePipelineAsyncCallbackInfo._pack_ = 1 # source:False -struct_WGPUCreateComputePipelineAsyncCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUCreateComputePipelineAsyncCallbackInfo = struct_WGPUCreateComputePipelineAsyncCallbackInfo -class struct_WGPUCreateRenderPipelineAsyncCallbackInfo(Structure): - pass - -struct_WGPUCreateRenderPipelineAsyncCallbackInfo._pack_ = 1 # source:False -struct_WGPUCreateRenderPipelineAsyncCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUCreateRenderPipelineAsyncCallbackInfo = struct_WGPUCreateRenderPipelineAsyncCallbackInfo -class struct_WGPUDawnWGSLBlocklist(Structure): - pass - -struct_WGPUDawnWGSLBlocklist._pack_ = 1 # source:False -struct_WGPUDawnWGSLBlocklist._fields_ = [ - ('chain', WGPUChainedStruct), - ('blocklistedFeatureCount', ctypes.c_uint64), - ('blocklistedFeatures', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), -] - -WGPUDawnWGSLBlocklist = struct_WGPUDawnWGSLBlocklist -class struct_WGPUDawnAdapterPropertiesPowerPreference(Structure): - pass - -struct_WGPUDawnAdapterPropertiesPowerPreference._pack_ = 1 # source:False -struct_WGPUDawnAdapterPropertiesPowerPreference._fields_ = [ - ('chain', WGPUChainedStructOut), - ('powerPreference', WGPUPowerPreference), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnAdapterPropertiesPowerPreference = struct_WGPUDawnAdapterPropertiesPowerPreference -class struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient(Structure): - pass - -struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient._pack_ = 1 # source:False -struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient._fields_ = [ - ('chain', WGPUChainedStruct), - ('outOfMemory', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnBufferDescriptorErrorInfoFromWireClient = struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient -class struct_WGPUDawnEncoderInternalUsageDescriptor(Structure): - pass - -struct_WGPUDawnEncoderInternalUsageDescriptor._pack_ = 1 # source:False -struct_WGPUDawnEncoderInternalUsageDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('useInternalUsages', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnEncoderInternalUsageDescriptor = struct_WGPUDawnEncoderInternalUsageDescriptor -class struct_WGPUDawnExperimentalImmediateDataLimits(Structure): - pass - -struct_WGPUDawnExperimentalImmediateDataLimits._pack_ = 1 # source:False -struct_WGPUDawnExperimentalImmediateDataLimits._fields_ = [ - ('chain', WGPUChainedStructOut), - ('maxImmediateDataRangeByteSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnExperimentalImmediateDataLimits = struct_WGPUDawnExperimentalImmediateDataLimits -class struct_WGPUDawnExperimentalSubgroupLimits(Structure): - pass - -struct_WGPUDawnExperimentalSubgroupLimits._pack_ = 1 # source:False -struct_WGPUDawnExperimentalSubgroupLimits._fields_ = [ - ('chain', WGPUChainedStructOut), - ('minSubgroupSize', ctypes.c_uint32), - ('maxSubgroupSize', ctypes.c_uint32), -] - -WGPUDawnExperimentalSubgroupLimits = struct_WGPUDawnExperimentalSubgroupLimits -class struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled(Structure): - pass - -struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled._pack_ = 1 # source:False -struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled._fields_ = [ - ('chain', WGPUChainedStruct), - ('implicitSampleCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnRenderPassColorAttachmentRenderToSingleSampled = struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled -class struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor(Structure): - pass - -struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor._pack_ = 1 # source:False -struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('allowNonUniformDerivatives', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnShaderModuleSPIRVOptionsDescriptor = struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor -class struct_WGPUDawnTexelCopyBufferRowAlignmentLimits(Structure): - pass - -struct_WGPUDawnTexelCopyBufferRowAlignmentLimits._pack_ = 1 # source:False -struct_WGPUDawnTexelCopyBufferRowAlignmentLimits._fields_ = [ - ('chain', WGPUChainedStructOut), - ('minTexelCopyBufferRowAlignment', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnTexelCopyBufferRowAlignmentLimits = struct_WGPUDawnTexelCopyBufferRowAlignmentLimits -class struct_WGPUDawnTextureInternalUsageDescriptor(Structure): - pass - -struct_WGPUDawnTextureInternalUsageDescriptor._pack_ = 1 # source:False -struct_WGPUDawnTextureInternalUsageDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('internalUsage', ctypes.c_uint64), -] - -WGPUDawnTextureInternalUsageDescriptor = struct_WGPUDawnTextureInternalUsageDescriptor -class struct_WGPUDawnTogglesDescriptor(Structure): - pass - -struct_WGPUDawnTogglesDescriptor._pack_ = 1 # source:False -struct_WGPUDawnTogglesDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('enabledToggleCount', ctypes.c_uint64), - ('enabledToggles', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), - ('disabledToggleCount', ctypes.c_uint64), - ('disabledToggles', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), -] - -WGPUDawnTogglesDescriptor = struct_WGPUDawnTogglesDescriptor -class struct_WGPUDawnWireWGSLControl(Structure): - pass - -struct_WGPUDawnWireWGSLControl._pack_ = 1 # source:False -struct_WGPUDawnWireWGSLControl._fields_ = [ - ('chain', WGPUChainedStruct), - ('enableExperimental', ctypes.c_uint32), - ('enableUnsafe', ctypes.c_uint32), - ('enableTesting', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDawnWireWGSLControl = struct_WGPUDawnWireWGSLControl -class struct_WGPUDeviceLostCallbackInfo(Structure): - pass - -struct_WGPUDeviceLostCallbackInfo._pack_ = 1 # source:False -struct_WGPUDeviceLostCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), WGPUDeviceLostReason, struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUDeviceLostCallbackInfo = struct_WGPUDeviceLostCallbackInfo -class struct_WGPUDrmFormatProperties(Structure): - pass - -struct_WGPUDrmFormatProperties._pack_ = 1 # source:False -struct_WGPUDrmFormatProperties._fields_ = [ - ('modifier', ctypes.c_uint64), - ('modifierPlaneCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUDrmFormatProperties = struct_WGPUDrmFormatProperties -class struct_WGPUExtent2D(Structure): - pass - -struct_WGPUExtent2D._pack_ = 1 # source:False -struct_WGPUExtent2D._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), -] - -WGPUExtent2D = struct_WGPUExtent2D -class struct_WGPUExtent3D(Structure): - pass - -struct_WGPUExtent3D._pack_ = 1 # source:False -struct_WGPUExtent3D._fields_ = [ - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('depthOrArrayLayers', ctypes.c_uint32), -] - -WGPUExtent3D = struct_WGPUExtent3D -class struct_WGPUExternalTextureBindingEntry(Structure): - pass - -struct_WGPUExternalTextureBindingEntry._pack_ = 1 # source:False -struct_WGPUExternalTextureBindingEntry._fields_ = [ - ('chain', WGPUChainedStruct), - ('externalTexture', ctypes.POINTER(struct_WGPUExternalTextureImpl)), -] - -WGPUExternalTextureBindingEntry = struct_WGPUExternalTextureBindingEntry -class struct_WGPUExternalTextureBindingLayout(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStruct), - ] - -WGPUExternalTextureBindingLayout = struct_WGPUExternalTextureBindingLayout -class struct_WGPUFormatCapabilities(Structure): - pass - -struct_WGPUFormatCapabilities._pack_ = 1 # source:False -struct_WGPUFormatCapabilities._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), -] - -WGPUFormatCapabilities = struct_WGPUFormatCapabilities -class struct_WGPUFuture(Structure): - pass - -struct_WGPUFuture._pack_ = 1 # source:False -struct_WGPUFuture._fields_ = [ - ('id', ctypes.c_uint64), -] - -WGPUFuture = struct_WGPUFuture -class struct_WGPUInstanceFeatures(Structure): - pass - -struct_WGPUInstanceFeatures._pack_ = 1 # source:False -struct_WGPUInstanceFeatures._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('timedWaitAnyEnable', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('timedWaitAnyMaxCount', ctypes.c_uint64), -] - -WGPUInstanceFeatures = struct_WGPUInstanceFeatures -class struct_WGPULimits(Structure): - pass - -struct_WGPULimits._pack_ = 1 # source:False -struct_WGPULimits._fields_ = [ - ('maxTextureDimension1D', ctypes.c_uint32), - ('maxTextureDimension2D', ctypes.c_uint32), - ('maxTextureDimension3D', ctypes.c_uint32), - ('maxTextureArrayLayers', ctypes.c_uint32), - ('maxBindGroups', ctypes.c_uint32), - ('maxBindGroupsPlusVertexBuffers', ctypes.c_uint32), - ('maxBindingsPerBindGroup', ctypes.c_uint32), - ('maxDynamicUniformBuffersPerPipelineLayout', ctypes.c_uint32), - ('maxDynamicStorageBuffersPerPipelineLayout', ctypes.c_uint32), - ('maxSampledTexturesPerShaderStage', ctypes.c_uint32), - ('maxSamplersPerShaderStage', ctypes.c_uint32), - ('maxStorageBuffersPerShaderStage', ctypes.c_uint32), - ('maxStorageTexturesPerShaderStage', ctypes.c_uint32), - ('maxUniformBuffersPerShaderStage', ctypes.c_uint32), - ('maxUniformBufferBindingSize', ctypes.c_uint64), - ('maxStorageBufferBindingSize', ctypes.c_uint64), - ('minUniformBufferOffsetAlignment', ctypes.c_uint32), - ('minStorageBufferOffsetAlignment', ctypes.c_uint32), - ('maxVertexBuffers', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('maxBufferSize', ctypes.c_uint64), - ('maxVertexAttributes', ctypes.c_uint32), - ('maxVertexBufferArrayStride', ctypes.c_uint32), - ('maxInterStageShaderComponents', ctypes.c_uint32), - ('maxInterStageShaderVariables', ctypes.c_uint32), - ('maxColorAttachments', ctypes.c_uint32), - ('maxColorAttachmentBytesPerSample', ctypes.c_uint32), - ('maxComputeWorkgroupStorageSize', ctypes.c_uint32), - ('maxComputeInvocationsPerWorkgroup', ctypes.c_uint32), - ('maxComputeWorkgroupSizeX', ctypes.c_uint32), - ('maxComputeWorkgroupSizeY', ctypes.c_uint32), - ('maxComputeWorkgroupSizeZ', ctypes.c_uint32), - ('maxComputeWorkgroupsPerDimension', ctypes.c_uint32), - ('maxStorageBuffersInVertexStage', ctypes.c_uint32), - ('maxStorageTexturesInVertexStage', ctypes.c_uint32), - ('maxStorageBuffersInFragmentStage', ctypes.c_uint32), - ('maxStorageTexturesInFragmentStage', ctypes.c_uint32), -] - -WGPULimits = struct_WGPULimits -class struct_WGPUMemoryHeapInfo(Structure): - pass - -struct_WGPUMemoryHeapInfo._pack_ = 1 # source:False -struct_WGPUMemoryHeapInfo._fields_ = [ - ('properties', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -WGPUMemoryHeapInfo = struct_WGPUMemoryHeapInfo -class struct_WGPUMultisampleState(Structure): - pass - -struct_WGPUMultisampleState._pack_ = 1 # source:False -struct_WGPUMultisampleState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('count', ctypes.c_uint32), - ('mask', ctypes.c_uint32), - ('alphaToCoverageEnabled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUMultisampleState = struct_WGPUMultisampleState -class struct_WGPUOrigin2D(Structure): - pass - -struct_WGPUOrigin2D._pack_ = 1 # source:False -struct_WGPUOrigin2D._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), -] - -WGPUOrigin2D = struct_WGPUOrigin2D -class struct_WGPUOrigin3D(Structure): - pass - -struct_WGPUOrigin3D._pack_ = 1 # source:False -struct_WGPUOrigin3D._fields_ = [ - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('z', ctypes.c_uint32), -] - -WGPUOrigin3D = struct_WGPUOrigin3D -class struct_WGPUPipelineLayoutStorageAttachment(Structure): - pass - -struct_WGPUPipelineLayoutStorageAttachment._pack_ = 1 # source:False -struct_WGPUPipelineLayoutStorageAttachment._fields_ = [ - ('offset', ctypes.c_uint64), - ('format', WGPUTextureFormat), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUPipelineLayoutStorageAttachment = struct_WGPUPipelineLayoutStorageAttachment -class struct_WGPUPopErrorScopeCallbackInfo(Structure): - pass - -struct_WGPUPopErrorScopeCallbackInfo._pack_ = 1 # source:False -struct_WGPUPopErrorScopeCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUPopErrorScopeStatus, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None))), - ('oldCallback', ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUPopErrorScopeCallbackInfo = struct_WGPUPopErrorScopeCallbackInfo -class struct_WGPUPrimitiveState(Structure): - pass - -struct_WGPUPrimitiveState._pack_ = 1 # source:False -struct_WGPUPrimitiveState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('topology', WGPUPrimitiveTopology), - ('stripIndexFormat', WGPUIndexFormat), - ('frontFace', WGPUFrontFace), - ('cullMode', WGPUCullMode), - ('unclippedDepth', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUPrimitiveState = struct_WGPUPrimitiveState -class struct_WGPUQueueWorkDoneCallbackInfo(Structure): - pass - -struct_WGPUQueueWorkDoneCallbackInfo._pack_ = 1 # source:False -struct_WGPUQueueWorkDoneCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUQueueWorkDoneCallbackInfo = struct_WGPUQueueWorkDoneCallbackInfo -class struct_WGPURenderPassDepthStencilAttachment(Structure): - pass - -struct_WGPURenderPassDepthStencilAttachment._pack_ = 1 # source:False -struct_WGPURenderPassDepthStencilAttachment._fields_ = [ - ('view', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('depthLoadOp', WGPULoadOp), - ('depthStoreOp', WGPUStoreOp), - ('depthClearValue', ctypes.c_float), - ('depthReadOnly', ctypes.c_uint32), - ('stencilLoadOp', WGPULoadOp), - ('stencilStoreOp', WGPUStoreOp), - ('stencilClearValue', ctypes.c_uint32), - ('stencilReadOnly', ctypes.c_uint32), -] - -WGPURenderPassDepthStencilAttachment = struct_WGPURenderPassDepthStencilAttachment -class struct_WGPURenderPassDescriptorExpandResolveRect(Structure): - pass - -struct_WGPURenderPassDescriptorExpandResolveRect._pack_ = 1 # source:False -struct_WGPURenderPassDescriptorExpandResolveRect._fields_ = [ - ('chain', WGPUChainedStruct), - ('x', ctypes.c_uint32), - ('y', ctypes.c_uint32), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), -] - -WGPURenderPassDescriptorExpandResolveRect = struct_WGPURenderPassDescriptorExpandResolveRect -class struct_WGPURenderPassMaxDrawCount(Structure): - pass - -struct_WGPURenderPassMaxDrawCount._pack_ = 1 # source:False -struct_WGPURenderPassMaxDrawCount._fields_ = [ - ('chain', WGPUChainedStruct), - ('maxDrawCount', ctypes.c_uint64), -] - -WGPURenderPassMaxDrawCount = struct_WGPURenderPassMaxDrawCount -class struct_WGPURenderPassTimestampWrites(Structure): - pass - -struct_WGPURenderPassTimestampWrites._pack_ = 1 # source:False -struct_WGPURenderPassTimestampWrites._fields_ = [ - ('querySet', ctypes.POINTER(struct_WGPUQuerySetImpl)), - ('beginningOfPassWriteIndex', ctypes.c_uint32), - ('endOfPassWriteIndex', ctypes.c_uint32), -] - -WGPURenderPassTimestampWrites = struct_WGPURenderPassTimestampWrites -class struct_WGPURequestAdapterCallbackInfo(Structure): - pass - -struct_WGPURequestAdapterCallbackInfo._pack_ = 1 # source:False -struct_WGPURequestAdapterCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPURequestAdapterCallbackInfo = struct_WGPURequestAdapterCallbackInfo -class struct_WGPURequestAdapterOptions(Structure): - pass - -struct_WGPURequestAdapterOptions._pack_ = 1 # source:False -struct_WGPURequestAdapterOptions._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('compatibleSurface', ctypes.POINTER(struct_WGPUSurfaceImpl)), - ('featureLevel', WGPUFeatureLevel), - ('powerPreference', WGPUPowerPreference), - ('backendType', WGPUBackendType), - ('forceFallbackAdapter', ctypes.c_uint32), - ('compatibilityMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPURequestAdapterOptions = struct_WGPURequestAdapterOptions -class struct_WGPURequestDeviceCallbackInfo(Structure): - pass - -struct_WGPURequestDeviceCallbackInfo._pack_ = 1 # source:False -struct_WGPURequestDeviceCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('mode', WGPUCallbackMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('callback', ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPURequestDeviceCallbackInfo = struct_WGPURequestDeviceCallbackInfo -class struct_WGPUSamplerBindingLayout(Structure): - pass - -struct_WGPUSamplerBindingLayout._pack_ = 1 # source:False -struct_WGPUSamplerBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('type', WGPUSamplerBindingType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSamplerBindingLayout = struct_WGPUSamplerBindingLayout -class struct_WGPUShaderModuleCompilationOptions(Structure): - pass - -struct_WGPUShaderModuleCompilationOptions._pack_ = 1 # source:False -struct_WGPUShaderModuleCompilationOptions._fields_ = [ - ('chain', WGPUChainedStruct), - ('strictMath', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUShaderModuleCompilationOptions = struct_WGPUShaderModuleCompilationOptions -class struct_WGPUShaderSourceSPIRV(Structure): - pass - -struct_WGPUShaderSourceSPIRV._pack_ = 1 # source:False -struct_WGPUShaderSourceSPIRV._fields_ = [ - ('chain', WGPUChainedStruct), - ('codeSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('code', ctypes.POINTER(ctypes.c_uint32)), -] - -WGPUShaderSourceSPIRV = struct_WGPUShaderSourceSPIRV -class struct_WGPUSharedBufferMemoryBeginAccessDescriptor(Structure): - pass - -struct_WGPUSharedBufferMemoryBeginAccessDescriptor._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryBeginAccessDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('initialized', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedBufferMemoryBeginAccessDescriptor = struct_WGPUSharedBufferMemoryBeginAccessDescriptor -class struct_WGPUSharedBufferMemoryEndAccessState(Structure): - pass - -struct_WGPUSharedBufferMemoryEndAccessState._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryEndAccessState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('initialized', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedBufferMemoryEndAccessState = struct_WGPUSharedBufferMemoryEndAccessState -class struct_WGPUSharedBufferMemoryProperties(Structure): - pass - -struct_WGPUSharedBufferMemoryProperties._pack_ = 1 # source:False -struct_WGPUSharedBufferMemoryProperties._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('usage', ctypes.c_uint64), - ('size', ctypes.c_uint64), -] - -WGPUSharedBufferMemoryProperties = struct_WGPUSharedBufferMemoryProperties -class struct_WGPUSharedFenceDXGISharedHandleDescriptor(Structure): - pass - -struct_WGPUSharedFenceDXGISharedHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceDXGISharedHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.POINTER(None)), -] - -WGPUSharedFenceDXGISharedHandleDescriptor = struct_WGPUSharedFenceDXGISharedHandleDescriptor -class struct_WGPUSharedFenceDXGISharedHandleExportInfo(Structure): - pass - -struct_WGPUSharedFenceDXGISharedHandleExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceDXGISharedHandleExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.POINTER(None)), -] - -WGPUSharedFenceDXGISharedHandleExportInfo = struct_WGPUSharedFenceDXGISharedHandleExportInfo -class struct_WGPUSharedFenceMTLSharedEventDescriptor(Structure): - pass - -struct_WGPUSharedFenceMTLSharedEventDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceMTLSharedEventDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('sharedEvent', ctypes.POINTER(None)), -] - -WGPUSharedFenceMTLSharedEventDescriptor = struct_WGPUSharedFenceMTLSharedEventDescriptor -class struct_WGPUSharedFenceMTLSharedEventExportInfo(Structure): - pass - -struct_WGPUSharedFenceMTLSharedEventExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceMTLSharedEventExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('sharedEvent', ctypes.POINTER(None)), -] - -WGPUSharedFenceMTLSharedEventExportInfo = struct_WGPUSharedFenceMTLSharedEventExportInfo -class struct_WGPUSharedFenceExportInfo(Structure): - pass - -struct_WGPUSharedFenceExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceExportInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('type', WGPUSharedFenceType), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceExportInfo = struct_WGPUSharedFenceExportInfo -class struct_WGPUSharedFenceSyncFDDescriptor(Structure): - pass - -struct_WGPUSharedFenceSyncFDDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceSyncFDDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceSyncFDDescriptor = struct_WGPUSharedFenceSyncFDDescriptor -class struct_WGPUSharedFenceSyncFDExportInfo(Structure): - pass - -struct_WGPUSharedFenceSyncFDExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceSyncFDExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceSyncFDExportInfo = struct_WGPUSharedFenceSyncFDExportInfo -class struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor = struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor -class struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo = struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo -class struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreZirconHandleDescriptor = struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor -class struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo(Structure): - pass - -struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo._pack_ = 1 # source:False -struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo._fields_ = [ - ('chain', WGPUChainedStructOut), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedFenceVkSemaphoreZirconHandleExportInfo = struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo -class struct_WGPUSharedTextureMemoryD3DSwapchainBeginState(Structure): - pass - -struct_WGPUSharedTextureMemoryD3DSwapchainBeginState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryD3DSwapchainBeginState._fields_ = [ - ('chain', WGPUChainedStruct), - ('isSwapchain', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryD3DSwapchainBeginState = struct_WGPUSharedTextureMemoryD3DSwapchainBeginState -class struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.POINTER(None)), - ('useKeyedMutex', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryDXGISharedHandleDescriptor = struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor -class struct_WGPUSharedTextureMemoryEGLImageDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryEGLImageDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryEGLImageDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('image', ctypes.POINTER(None)), -] - -WGPUSharedTextureMemoryEGLImageDescriptor = struct_WGPUSharedTextureMemoryEGLImageDescriptor -class struct_WGPUSharedTextureMemoryIOSurfaceDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryIOSurfaceDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryIOSurfaceDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('ioSurface', ctypes.POINTER(None)), -] - -WGPUSharedTextureMemoryIOSurfaceDescriptor = struct_WGPUSharedTextureMemoryIOSurfaceDescriptor -class struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('handle', ctypes.POINTER(None)), - ('useExternalFormat', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryAHardwareBufferDescriptor = struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor -class struct_WGPUSharedTextureMemoryBeginAccessDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryBeginAccessDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryBeginAccessDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('concurrentRead', ctypes.c_uint32), - ('initialized', ctypes.c_uint32), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedTextureMemoryBeginAccessDescriptor = struct_WGPUSharedTextureMemoryBeginAccessDescriptor -class struct_WGPUSharedTextureMemoryDmaBufPlane(Structure): - pass - -struct_WGPUSharedTextureMemoryDmaBufPlane._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryDmaBufPlane._fields_ = [ - ('fd', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('stride', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryDmaBufPlane = struct_WGPUSharedTextureMemoryDmaBufPlane -class struct_WGPUSharedTextureMemoryEndAccessState(Structure): - pass - -struct_WGPUSharedTextureMemoryEndAccessState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryEndAccessState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('initialized', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('fenceCount', ctypes.c_uint64), - ('fences', ctypes.POINTER(ctypes.POINTER(struct_WGPUSharedFenceImpl))), - ('signaledValues', ctypes.POINTER(ctypes.c_uint64)), -] - -WGPUSharedTextureMemoryEndAccessState = struct_WGPUSharedTextureMemoryEndAccessState -class struct_WGPUSharedTextureMemoryOpaqueFDDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryOpaqueFDDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryOpaqueFDDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('vkImageCreateInfo', ctypes.POINTER(None)), - ('memoryFD', ctypes.c_int32), - ('memoryTypeIndex', ctypes.c_uint32), - ('allocationSize', ctypes.c_uint64), - ('dedicatedAllocation', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryOpaqueFDDescriptor = struct_WGPUSharedTextureMemoryOpaqueFDDescriptor -class struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('dedicatedAllocation', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor = struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor -class struct_WGPUSharedTextureMemoryVkImageLayoutBeginState(Structure): - pass - -struct_WGPUSharedTextureMemoryVkImageLayoutBeginState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryVkImageLayoutBeginState._fields_ = [ - ('chain', WGPUChainedStruct), - ('oldLayout', ctypes.c_int32), - ('newLayout', ctypes.c_int32), -] - -WGPUSharedTextureMemoryVkImageLayoutBeginState = struct_WGPUSharedTextureMemoryVkImageLayoutBeginState -class struct_WGPUSharedTextureMemoryVkImageLayoutEndState(Structure): - pass - -struct_WGPUSharedTextureMemoryVkImageLayoutEndState._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryVkImageLayoutEndState._fields_ = [ - ('chain', WGPUChainedStructOut), - ('oldLayout', ctypes.c_int32), - ('newLayout', ctypes.c_int32), -] - -WGPUSharedTextureMemoryVkImageLayoutEndState = struct_WGPUSharedTextureMemoryVkImageLayoutEndState -class struct_WGPUSharedTextureMemoryZirconHandleDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryZirconHandleDescriptor._pack_ = 1 # source:False -struct_WGPUSharedTextureMemoryZirconHandleDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('memoryFD', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('allocationSize', ctypes.c_uint64), -] - -WGPUSharedTextureMemoryZirconHandleDescriptor = struct_WGPUSharedTextureMemoryZirconHandleDescriptor -class struct_WGPUStaticSamplerBindingLayout(Structure): - pass - -struct_WGPUStaticSamplerBindingLayout._pack_ = 1 # source:False -struct_WGPUStaticSamplerBindingLayout._fields_ = [ - ('chain', WGPUChainedStruct), - ('sampler', ctypes.POINTER(struct_WGPUSamplerImpl)), - ('sampledTextureBinding', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUStaticSamplerBindingLayout = struct_WGPUStaticSamplerBindingLayout -class struct_WGPUStencilFaceState(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('compare', WGPUCompareFunction), - ('failOp', WGPUStencilOperation), - ('depthFailOp', WGPUStencilOperation), - ('passOp', WGPUStencilOperation), - ] - -WGPUStencilFaceState = struct_WGPUStencilFaceState -class struct_WGPUStorageTextureBindingLayout(Structure): - pass - -struct_WGPUStorageTextureBindingLayout._pack_ = 1 # source:False -struct_WGPUStorageTextureBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('access', WGPUStorageTextureAccess), - ('format', WGPUTextureFormat), - ('viewDimension', WGPUTextureViewDimension), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUStorageTextureBindingLayout = struct_WGPUStorageTextureBindingLayout -WGPUStringView = struct_WGPUStringView -class struct_WGPUSupportedFeatures(Structure): - pass - -struct_WGPUSupportedFeatures._pack_ = 1 # source:False -struct_WGPUSupportedFeatures._fields_ = [ - ('featureCount', ctypes.c_uint64), - ('features', ctypes.POINTER(WGPUFeatureName)), -] - -WGPUSupportedFeatures = struct_WGPUSupportedFeatures -class struct_WGPUSurfaceCapabilities(Structure): - pass - -struct_WGPUSurfaceCapabilities._pack_ = 1 # source:False -struct_WGPUSurfaceCapabilities._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('usages', ctypes.c_uint64), - ('formatCount', ctypes.c_uint64), - ('formats', ctypes.POINTER(WGPUTextureFormat)), - ('presentModeCount', ctypes.c_uint64), - ('presentModes', ctypes.POINTER(WGPUPresentMode)), - ('alphaModeCount', ctypes.c_uint64), - ('alphaModes', ctypes.POINTER(WGPUCompositeAlphaMode)), -] - -WGPUSurfaceCapabilities = struct_WGPUSurfaceCapabilities -class struct_WGPUSurfaceConfiguration(Structure): - pass - -struct_WGPUSurfaceConfiguration._pack_ = 1 # source:False -struct_WGPUSurfaceConfiguration._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('device', ctypes.POINTER(struct_WGPUDeviceImpl)), - ('format', WGPUTextureFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('usage', ctypes.c_uint64), - ('viewFormatCount', ctypes.c_uint64), - ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), - ('alphaMode', WGPUCompositeAlphaMode), - ('width', ctypes.c_uint32), - ('height', ctypes.c_uint32), - ('presentMode', WGPUPresentMode), -] - -WGPUSurfaceConfiguration = struct_WGPUSurfaceConfiguration -class struct_WGPUSurfaceDescriptorFromWindowsCoreWindow(Structure): - pass - -struct_WGPUSurfaceDescriptorFromWindowsCoreWindow._pack_ = 1 # source:False -struct_WGPUSurfaceDescriptorFromWindowsCoreWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('coreWindow', ctypes.POINTER(None)), -] - -WGPUSurfaceDescriptorFromWindowsCoreWindow = struct_WGPUSurfaceDescriptorFromWindowsCoreWindow -class struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel(Structure): - pass - -struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel._pack_ = 1 # source:False -struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel._fields_ = [ - ('chain', WGPUChainedStruct), - ('swapChainPanel', ctypes.POINTER(None)), -] - -WGPUSurfaceDescriptorFromWindowsSwapChainPanel = struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel -class struct_WGPUSurfaceSourceXCBWindow(Structure): - pass - -struct_WGPUSurfaceSourceXCBWindow._pack_ = 1 # source:False -struct_WGPUSurfaceSourceXCBWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('connection', ctypes.POINTER(None)), - ('window', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUSurfaceSourceXCBWindow = struct_WGPUSurfaceSourceXCBWindow -class struct_WGPUSurfaceSourceAndroidNativeWindow(Structure): - pass - -struct_WGPUSurfaceSourceAndroidNativeWindow._pack_ = 1 # source:False -struct_WGPUSurfaceSourceAndroidNativeWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('window', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceAndroidNativeWindow = struct_WGPUSurfaceSourceAndroidNativeWindow -class struct_WGPUSurfaceSourceMetalLayer(Structure): - pass - -struct_WGPUSurfaceSourceMetalLayer._pack_ = 1 # source:False -struct_WGPUSurfaceSourceMetalLayer._fields_ = [ - ('chain', WGPUChainedStruct), - ('layer', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceMetalLayer = struct_WGPUSurfaceSourceMetalLayer -class struct_WGPUSurfaceSourceWaylandSurface(Structure): - pass - -struct_WGPUSurfaceSourceWaylandSurface._pack_ = 1 # source:False -struct_WGPUSurfaceSourceWaylandSurface._fields_ = [ - ('chain', WGPUChainedStruct), - ('display', ctypes.POINTER(None)), - ('surface', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceWaylandSurface = struct_WGPUSurfaceSourceWaylandSurface -class struct_WGPUSurfaceSourceWindowsHWND(Structure): - pass - -struct_WGPUSurfaceSourceWindowsHWND._pack_ = 1 # source:False -struct_WGPUSurfaceSourceWindowsHWND._fields_ = [ - ('chain', WGPUChainedStruct), - ('hinstance', ctypes.POINTER(None)), - ('hwnd', ctypes.POINTER(None)), -] - -WGPUSurfaceSourceWindowsHWND = struct_WGPUSurfaceSourceWindowsHWND -class struct_WGPUSurfaceSourceXlibWindow(Structure): - pass - -struct_WGPUSurfaceSourceXlibWindow._pack_ = 1 # source:False -struct_WGPUSurfaceSourceXlibWindow._fields_ = [ - ('chain', WGPUChainedStruct), - ('display', ctypes.POINTER(None)), - ('window', ctypes.c_uint64), -] - -WGPUSurfaceSourceXlibWindow = struct_WGPUSurfaceSourceXlibWindow -class struct_WGPUSurfaceTexture(Structure): - pass - -struct_WGPUSurfaceTexture._pack_ = 1 # source:False -struct_WGPUSurfaceTexture._fields_ = [ - ('texture', ctypes.POINTER(struct_WGPUTextureImpl)), - ('suboptimal', ctypes.c_uint32), - ('status', WGPUSurfaceGetCurrentTextureStatus), -] - -WGPUSurfaceTexture = struct_WGPUSurfaceTexture -class struct_WGPUTextureBindingLayout(Structure): - pass - -struct_WGPUTextureBindingLayout._pack_ = 1 # source:False -struct_WGPUTextureBindingLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('sampleType', WGPUTextureSampleType), - ('viewDimension', WGPUTextureViewDimension), - ('multisampled', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUTextureBindingLayout = struct_WGPUTextureBindingLayout -class struct_WGPUTextureBindingViewDimensionDescriptor(Structure): - pass - -struct_WGPUTextureBindingViewDimensionDescriptor._pack_ = 1 # source:False -struct_WGPUTextureBindingViewDimensionDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('textureBindingViewDimension', WGPUTextureViewDimension), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUTextureBindingViewDimensionDescriptor = struct_WGPUTextureBindingViewDimensionDescriptor -class struct_WGPUTextureDataLayout(Structure): - pass - -struct_WGPUTextureDataLayout._pack_ = 1 # source:False -struct_WGPUTextureDataLayout._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('offset', ctypes.c_uint64), - ('bytesPerRow', ctypes.c_uint32), - ('rowsPerImage', ctypes.c_uint32), -] - -WGPUTextureDataLayout = struct_WGPUTextureDataLayout -class struct_WGPUUncapturedErrorCallbackInfo(Structure): - pass - -struct_WGPUUncapturedErrorCallbackInfo._pack_ = 1 # source:False -struct_WGPUUncapturedErrorCallbackInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('callback', ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None))), - ('userdata', ctypes.POINTER(None)), -] - -WGPUUncapturedErrorCallbackInfo = struct_WGPUUncapturedErrorCallbackInfo -class struct_WGPUVertexAttribute(Structure): - pass - -struct_WGPUVertexAttribute._pack_ = 1 # source:False -struct_WGPUVertexAttribute._fields_ = [ - ('format', WGPUVertexFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('offset', ctypes.c_uint64), - ('shaderLocation', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -WGPUVertexAttribute = struct_WGPUVertexAttribute -class struct_WGPUYCbCrVkDescriptor(Structure): - pass - -struct_WGPUYCbCrVkDescriptor._pack_ = 1 # source:False -struct_WGPUYCbCrVkDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('vkFormat', ctypes.c_uint32), - ('vkYCbCrModel', ctypes.c_uint32), - ('vkYCbCrRange', ctypes.c_uint32), - ('vkComponentSwizzleRed', ctypes.c_uint32), - ('vkComponentSwizzleGreen', ctypes.c_uint32), - ('vkComponentSwizzleBlue', ctypes.c_uint32), - ('vkComponentSwizzleAlpha', ctypes.c_uint32), - ('vkXChromaOffset', ctypes.c_uint32), - ('vkYChromaOffset', ctypes.c_uint32), - ('vkChromaFilter', WGPUFilterMode), - ('forceExplicitReconstruction', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('externalFormat', ctypes.c_uint64), -] - -WGPUYCbCrVkDescriptor = struct_WGPUYCbCrVkDescriptor -class struct_WGPUAHardwareBufferProperties(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('yCbCrInfo', WGPUYCbCrVkDescriptor), - ] - -WGPUAHardwareBufferProperties = struct_WGPUAHardwareBufferProperties -class struct_WGPUAdapterInfo(Structure): - pass - -struct_WGPUAdapterInfo._pack_ = 1 # source:False -struct_WGPUAdapterInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('vendor', WGPUStringView), - ('architecture', WGPUStringView), - ('device', WGPUStringView), - ('description', WGPUStringView), - ('backendType', WGPUBackendType), - ('adapterType', WGPUAdapterType), - ('vendorID', ctypes.c_uint32), - ('deviceID', ctypes.c_uint32), - ('compatibilityMode', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUAdapterInfo = struct_WGPUAdapterInfo -class struct_WGPUAdapterPropertiesMemoryHeaps(Structure): - pass - -struct_WGPUAdapterPropertiesMemoryHeaps._pack_ = 1 # source:False -struct_WGPUAdapterPropertiesMemoryHeaps._fields_ = [ - ('chain', WGPUChainedStructOut), - ('heapCount', ctypes.c_uint64), - ('heapInfo', ctypes.POINTER(struct_WGPUMemoryHeapInfo)), -] - -WGPUAdapterPropertiesMemoryHeaps = struct_WGPUAdapterPropertiesMemoryHeaps -class struct_WGPUBindGroupDescriptor(Structure): - pass - -struct_WGPUBindGroupDescriptor._pack_ = 1 # source:False -struct_WGPUBindGroupDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('layout', ctypes.POINTER(struct_WGPUBindGroupLayoutImpl)), - ('entryCount', ctypes.c_uint64), - ('entries', ctypes.POINTER(struct_WGPUBindGroupEntry)), -] - -WGPUBindGroupDescriptor = struct_WGPUBindGroupDescriptor -class struct_WGPUBindGroupLayoutEntry(Structure): - pass - -struct_WGPUBindGroupLayoutEntry._pack_ = 1 # source:False -struct_WGPUBindGroupLayoutEntry._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('binding', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('visibility', ctypes.c_uint64), - ('buffer', WGPUBufferBindingLayout), - ('sampler', WGPUSamplerBindingLayout), - ('texture', WGPUTextureBindingLayout), - ('storageTexture', WGPUStorageTextureBindingLayout), -] - -WGPUBindGroupLayoutEntry = struct_WGPUBindGroupLayoutEntry -class struct_WGPUBlendState(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('color', WGPUBlendComponent), - ('alpha', WGPUBlendComponent), - ] - -WGPUBlendState = struct_WGPUBlendState -class struct_WGPUBufferDescriptor(Structure): - pass - -struct_WGPUBufferDescriptor._pack_ = 1 # source:False -struct_WGPUBufferDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('usage', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('mappedAtCreation', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -WGPUBufferDescriptor = struct_WGPUBufferDescriptor -class struct_WGPUCommandBufferDescriptor(Structure): - pass - -struct_WGPUCommandBufferDescriptor._pack_ = 1 # source:False -struct_WGPUCommandBufferDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUCommandBufferDescriptor = struct_WGPUCommandBufferDescriptor -class struct_WGPUCommandEncoderDescriptor(Structure): - pass - -struct_WGPUCommandEncoderDescriptor._pack_ = 1 # source:False -struct_WGPUCommandEncoderDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), -] - -WGPUCommandEncoderDescriptor = struct_WGPUCommandEncoderDescriptor -class struct_WGPUCompilationMessage(Structure): - pass - -struct_WGPUCompilationMessage._pack_ = 1 # source:False -struct_WGPUCompilationMessage._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('message', WGPUStringView), - ('type', WGPUCompilationMessageType), - ('PADDING_0', ctypes.c_ubyte * 4), - ('lineNum', ctypes.c_uint64), - ('linePos', ctypes.c_uint64), - ('offset', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('utf16LinePos', ctypes.c_uint64), - ('utf16Offset', ctypes.c_uint64), - ('utf16Length', ctypes.c_uint64), -] - + ('chain', WGPUChainedStruct), + ('enabled', WGPUBool), +] +class struct_WGPUCompilationInfoCallbackInfo(Struct): pass +enum_WGPUCompilationInfoRequestStatus = CEnum(ctypes.c_uint32) +WGPUCompilationInfoRequestStatus_Success = enum_WGPUCompilationInfoRequestStatus.define('WGPUCompilationInfoRequestStatus_Success', 1) +WGPUCompilationInfoRequestStatus_InstanceDropped = enum_WGPUCompilationInfoRequestStatus.define('WGPUCompilationInfoRequestStatus_InstanceDropped', 2) +WGPUCompilationInfoRequestStatus_Error = enum_WGPUCompilationInfoRequestStatus.define('WGPUCompilationInfoRequestStatus_Error', 3) +WGPUCompilationInfoRequestStatus_DeviceLost = enum_WGPUCompilationInfoRequestStatus.define('WGPUCompilationInfoRequestStatus_DeviceLost', 4) +WGPUCompilationInfoRequestStatus_Unknown = enum_WGPUCompilationInfoRequestStatus.define('WGPUCompilationInfoRequestStatus_Unknown', 5) +WGPUCompilationInfoRequestStatus_Force32 = enum_WGPUCompilationInfoRequestStatus.define('WGPUCompilationInfoRequestStatus_Force32', 2147483647) + +class const_struct_WGPUCompilationInfo(Struct): pass +size_t = ctypes.c_uint64 +class struct_WGPUCompilationMessage(Struct): pass WGPUCompilationMessage = struct_WGPUCompilationMessage -class struct_WGPUComputePassDescriptor(Structure): - pass +class struct_WGPUStringView(Struct): pass +WGPUStringView = struct_WGPUStringView +struct_WGPUStringView._fields_ = [ + ('data', ctypes.POINTER(ctypes.c_char)), + ('length', size_t), +] +enum_WGPUCompilationMessageType = CEnum(ctypes.c_uint32) +WGPUCompilationMessageType_Error = enum_WGPUCompilationMessageType.define('WGPUCompilationMessageType_Error', 1) +WGPUCompilationMessageType_Warning = enum_WGPUCompilationMessageType.define('WGPUCompilationMessageType_Warning', 2) +WGPUCompilationMessageType_Info = enum_WGPUCompilationMessageType.define('WGPUCompilationMessageType_Info', 3) +WGPUCompilationMessageType_Force32 = enum_WGPUCompilationMessageType.define('WGPUCompilationMessageType_Force32', 2147483647) -struct_WGPUComputePassDescriptor._pack_ = 1 # source:False +WGPUCompilationMessageType = enum_WGPUCompilationMessageType +struct_WGPUCompilationMessage._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('message', WGPUStringView), + ('type', WGPUCompilationMessageType), + ('lineNum', uint64_t), + ('linePos', uint64_t), + ('offset', uint64_t), + ('length', uint64_t), + ('utf16LinePos', uint64_t), + ('utf16Offset', uint64_t), + ('utf16Length', uint64_t), +] +const_struct_WGPUCompilationInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('messageCount', size_t), + ('messages', ctypes.POINTER(WGPUCompilationMessage)), +] +WGPUCompilationInfoCallback = ctypes.CFUNCTYPE(None, enum_WGPUCompilationInfoRequestStatus, ctypes.POINTER(const_struct_WGPUCompilationInfo), ctypes.c_void_p) +struct_WGPUCompilationInfoCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUCompilationInfoCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUComputePassTimestampWrites(Struct): pass +struct_WGPUComputePassTimestampWrites._fields_ = [ + ('querySet', WGPUQuerySet), + ('beginningOfPassWriteIndex', uint32_t), + ('endOfPassWriteIndex', uint32_t), +] +class struct_WGPUCopyTextureForBrowserOptions(Struct): pass +enum_WGPUAlphaMode = CEnum(ctypes.c_uint32) +WGPUAlphaMode_Opaque = enum_WGPUAlphaMode.define('WGPUAlphaMode_Opaque', 1) +WGPUAlphaMode_Premultiplied = enum_WGPUAlphaMode.define('WGPUAlphaMode_Premultiplied', 2) +WGPUAlphaMode_Unpremultiplied = enum_WGPUAlphaMode.define('WGPUAlphaMode_Unpremultiplied', 3) +WGPUAlphaMode_Force32 = enum_WGPUAlphaMode.define('WGPUAlphaMode_Force32', 2147483647) + +WGPUAlphaMode = enum_WGPUAlphaMode +struct_WGPUCopyTextureForBrowserOptions._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('flipY', WGPUBool), + ('needsColorSpaceConversion', WGPUBool), + ('srcAlphaMode', WGPUAlphaMode), + ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('conversionMatrix', ctypes.POINTER(ctypes.c_float)), + ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('dstAlphaMode', WGPUAlphaMode), + ('internalUsage', WGPUBool), +] +class struct_WGPUCreateComputePipelineAsyncCallbackInfo(Struct): pass +enum_WGPUCreatePipelineAsyncStatus = CEnum(ctypes.c_uint32) +WGPUCreatePipelineAsyncStatus_Success = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_Success', 1) +WGPUCreatePipelineAsyncStatus_InstanceDropped = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_InstanceDropped', 2) +WGPUCreatePipelineAsyncStatus_ValidationError = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_ValidationError', 3) +WGPUCreatePipelineAsyncStatus_InternalError = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_InternalError', 4) +WGPUCreatePipelineAsyncStatus_DeviceLost = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_DeviceLost', 5) +WGPUCreatePipelineAsyncStatus_DeviceDestroyed = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_DeviceDestroyed', 6) +WGPUCreatePipelineAsyncStatus_Unknown = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_Unknown', 7) +WGPUCreatePipelineAsyncStatus_Force32 = enum_WGPUCreatePipelineAsyncStatus.define('WGPUCreatePipelineAsyncStatus_Force32', 2147483647) + +WGPUCreateComputePipelineAsyncCallback = ctypes.CFUNCTYPE(None, enum_WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.c_void_p) +struct_WGPUCreateComputePipelineAsyncCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUCreateComputePipelineAsyncCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUCreateRenderPipelineAsyncCallbackInfo(Struct): pass +WGPUCreateRenderPipelineAsyncCallback = ctypes.CFUNCTYPE(None, enum_WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.c_void_p) +struct_WGPUCreateRenderPipelineAsyncCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUCreateRenderPipelineAsyncCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUDawnWGSLBlocklist(Struct): pass +struct_WGPUDawnWGSLBlocklist._fields_ = [ + ('chain', WGPUChainedStruct), + ('blocklistedFeatureCount', size_t), + ('blocklistedFeatures', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), +] +class struct_WGPUDawnAdapterPropertiesPowerPreference(Struct): pass +enum_WGPUPowerPreference = CEnum(ctypes.c_uint32) +WGPUPowerPreference_Undefined = enum_WGPUPowerPreference.define('WGPUPowerPreference_Undefined', 0) +WGPUPowerPreference_LowPower = enum_WGPUPowerPreference.define('WGPUPowerPreference_LowPower', 1) +WGPUPowerPreference_HighPerformance = enum_WGPUPowerPreference.define('WGPUPowerPreference_HighPerformance', 2) +WGPUPowerPreference_Force32 = enum_WGPUPowerPreference.define('WGPUPowerPreference_Force32', 2147483647) + +WGPUPowerPreference = enum_WGPUPowerPreference +struct_WGPUDawnAdapterPropertiesPowerPreference._fields_ = [ + ('chain', WGPUChainedStructOut), + ('powerPreference', WGPUPowerPreference), +] +class struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient(Struct): pass +struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient._fields_ = [ + ('chain', WGPUChainedStruct), + ('outOfMemory', WGPUBool), +] +class struct_WGPUDawnEncoderInternalUsageDescriptor(Struct): pass +struct_WGPUDawnEncoderInternalUsageDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('useInternalUsages', WGPUBool), +] +class struct_WGPUDawnExperimentalImmediateDataLimits(Struct): pass +struct_WGPUDawnExperimentalImmediateDataLimits._fields_ = [ + ('chain', WGPUChainedStructOut), + ('maxImmediateDataRangeByteSize', uint32_t), +] +class struct_WGPUDawnExperimentalSubgroupLimits(Struct): pass +struct_WGPUDawnExperimentalSubgroupLimits._fields_ = [ + ('chain', WGPUChainedStructOut), + ('minSubgroupSize', uint32_t), + ('maxSubgroupSize', uint32_t), +] +class struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled(Struct): pass +struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled._fields_ = [ + ('chain', WGPUChainedStruct), + ('implicitSampleCount', uint32_t), +] +class struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor(Struct): pass +struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('allowNonUniformDerivatives', WGPUBool), +] +class struct_WGPUDawnTexelCopyBufferRowAlignmentLimits(Struct): pass +struct_WGPUDawnTexelCopyBufferRowAlignmentLimits._fields_ = [ + ('chain', WGPUChainedStructOut), + ('minTexelCopyBufferRowAlignment', uint32_t), +] +class struct_WGPUDawnTextureInternalUsageDescriptor(Struct): pass +WGPUTextureUsage = ctypes.c_uint64 +struct_WGPUDawnTextureInternalUsageDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('internalUsage', WGPUTextureUsage), +] +class struct_WGPUDawnTogglesDescriptor(Struct): pass +struct_WGPUDawnTogglesDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('enabledToggleCount', size_t), + ('enabledToggles', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), + ('disabledToggleCount', size_t), + ('disabledToggles', ctypes.POINTER(ctypes.POINTER(ctypes.c_char))), +] +class struct_WGPUDawnWireWGSLControl(Struct): pass +struct_WGPUDawnWireWGSLControl._fields_ = [ + ('chain', WGPUChainedStruct), + ('enableExperimental', WGPUBool), + ('enableUnsafe', WGPUBool), + ('enableTesting', WGPUBool), +] +class struct_WGPUDeviceLostCallbackInfo(Struct): pass +enum_WGPUDeviceLostReason = CEnum(ctypes.c_uint32) +WGPUDeviceLostReason_Unknown = enum_WGPUDeviceLostReason.define('WGPUDeviceLostReason_Unknown', 1) +WGPUDeviceLostReason_Destroyed = enum_WGPUDeviceLostReason.define('WGPUDeviceLostReason_Destroyed', 2) +WGPUDeviceLostReason_InstanceDropped = enum_WGPUDeviceLostReason.define('WGPUDeviceLostReason_InstanceDropped', 3) +WGPUDeviceLostReason_FailedCreation = enum_WGPUDeviceLostReason.define('WGPUDeviceLostReason_FailedCreation', 4) +WGPUDeviceLostReason_Force32 = enum_WGPUDeviceLostReason.define('WGPUDeviceLostReason_Force32', 2147483647) + +WGPUDeviceLostCallbackNew = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), enum_WGPUDeviceLostReason, struct_WGPUStringView, ctypes.c_void_p) +struct_WGPUDeviceLostCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUDeviceLostCallbackNew), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUDrmFormatProperties(Struct): pass +struct_WGPUDrmFormatProperties._fields_ = [ + ('modifier', uint64_t), + ('modifierPlaneCount', uint32_t), +] +class struct_WGPUExtent2D(Struct): pass +struct_WGPUExtent2D._fields_ = [ + ('width', uint32_t), + ('height', uint32_t), +] +class struct_WGPUExtent3D(Struct): pass +struct_WGPUExtent3D._fields_ = [ + ('width', uint32_t), + ('height', uint32_t), + ('depthOrArrayLayers', uint32_t), +] +class struct_WGPUExternalTextureBindingEntry(Struct): pass +struct_WGPUExternalTextureBindingEntry._fields_ = [ + ('chain', WGPUChainedStruct), + ('externalTexture', WGPUExternalTexture), +] +class struct_WGPUExternalTextureBindingLayout(Struct): pass +struct_WGPUExternalTextureBindingLayout._fields_ = [ + ('chain', WGPUChainedStruct), +] +class struct_WGPUFormatCapabilities(Struct): pass +struct_WGPUFormatCapabilities._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), +] +class struct_WGPUFuture(Struct): pass +struct_WGPUFuture._fields_ = [ + ('id', uint64_t), +] +class struct_WGPUInstanceFeatures(Struct): pass +struct_WGPUInstanceFeatures._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('timedWaitAnyEnable', WGPUBool), + ('timedWaitAnyMaxCount', size_t), +] +class struct_WGPULimits(Struct): pass +struct_WGPULimits._fields_ = [ + ('maxTextureDimension1D', uint32_t), + ('maxTextureDimension2D', uint32_t), + ('maxTextureDimension3D', uint32_t), + ('maxTextureArrayLayers', uint32_t), + ('maxBindGroups', uint32_t), + ('maxBindGroupsPlusVertexBuffers', uint32_t), + ('maxBindingsPerBindGroup', uint32_t), + ('maxDynamicUniformBuffersPerPipelineLayout', uint32_t), + ('maxDynamicStorageBuffersPerPipelineLayout', uint32_t), + ('maxSampledTexturesPerShaderStage', uint32_t), + ('maxSamplersPerShaderStage', uint32_t), + ('maxStorageBuffersPerShaderStage', uint32_t), + ('maxStorageTexturesPerShaderStage', uint32_t), + ('maxUniformBuffersPerShaderStage', uint32_t), + ('maxUniformBufferBindingSize', uint64_t), + ('maxStorageBufferBindingSize', uint64_t), + ('minUniformBufferOffsetAlignment', uint32_t), + ('minStorageBufferOffsetAlignment', uint32_t), + ('maxVertexBuffers', uint32_t), + ('maxBufferSize', uint64_t), + ('maxVertexAttributes', uint32_t), + ('maxVertexBufferArrayStride', uint32_t), + ('maxInterStageShaderComponents', uint32_t), + ('maxInterStageShaderVariables', uint32_t), + ('maxColorAttachments', uint32_t), + ('maxColorAttachmentBytesPerSample', uint32_t), + ('maxComputeWorkgroupStorageSize', uint32_t), + ('maxComputeInvocationsPerWorkgroup', uint32_t), + ('maxComputeWorkgroupSizeX', uint32_t), + ('maxComputeWorkgroupSizeY', uint32_t), + ('maxComputeWorkgroupSizeZ', uint32_t), + ('maxComputeWorkgroupsPerDimension', uint32_t), + ('maxStorageBuffersInVertexStage', uint32_t), + ('maxStorageTexturesInVertexStage', uint32_t), + ('maxStorageBuffersInFragmentStage', uint32_t), + ('maxStorageTexturesInFragmentStage', uint32_t), +] +class struct_WGPUMemoryHeapInfo(Struct): pass +WGPUHeapProperty = ctypes.c_uint64 +struct_WGPUMemoryHeapInfo._fields_ = [ + ('properties', WGPUHeapProperty), + ('size', uint64_t), +] +class struct_WGPUMultisampleState(Struct): pass +struct_WGPUMultisampleState._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('count', uint32_t), + ('mask', uint32_t), + ('alphaToCoverageEnabled', WGPUBool), +] +class struct_WGPUOrigin2D(Struct): pass +struct_WGPUOrigin2D._fields_ = [ + ('x', uint32_t), + ('y', uint32_t), +] +class struct_WGPUOrigin3D(Struct): pass +struct_WGPUOrigin3D._fields_ = [ + ('x', uint32_t), + ('y', uint32_t), + ('z', uint32_t), +] +class struct_WGPUPipelineLayoutStorageAttachment(Struct): pass +enum_WGPUTextureFormat = CEnum(ctypes.c_uint32) +WGPUTextureFormat_Undefined = enum_WGPUTextureFormat.define('WGPUTextureFormat_Undefined', 0) +WGPUTextureFormat_R8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8Unorm', 1) +WGPUTextureFormat_R8Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8Snorm', 2) +WGPUTextureFormat_R8Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8Uint', 3) +WGPUTextureFormat_R8Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8Sint', 4) +WGPUTextureFormat_R16Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_R16Uint', 5) +WGPUTextureFormat_R16Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_R16Sint', 6) +WGPUTextureFormat_R16Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_R16Float', 7) +WGPUTextureFormat_RG8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG8Unorm', 8) +WGPUTextureFormat_RG8Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG8Snorm', 9) +WGPUTextureFormat_RG8Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG8Uint', 10) +WGPUTextureFormat_RG8Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG8Sint', 11) +WGPUTextureFormat_R32Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_R32Float', 12) +WGPUTextureFormat_R32Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_R32Uint', 13) +WGPUTextureFormat_R32Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_R32Sint', 14) +WGPUTextureFormat_RG16Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG16Uint', 15) +WGPUTextureFormat_RG16Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG16Sint', 16) +WGPUTextureFormat_RG16Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG16Float', 17) +WGPUTextureFormat_RGBA8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA8Unorm', 18) +WGPUTextureFormat_RGBA8UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA8UnormSrgb', 19) +WGPUTextureFormat_RGBA8Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA8Snorm', 20) +WGPUTextureFormat_RGBA8Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA8Uint', 21) +WGPUTextureFormat_RGBA8Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA8Sint', 22) +WGPUTextureFormat_BGRA8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BGRA8Unorm', 23) +WGPUTextureFormat_BGRA8UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_BGRA8UnormSrgb', 24) +WGPUTextureFormat_RGB10A2Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGB10A2Uint', 25) +WGPUTextureFormat_RGB10A2Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGB10A2Unorm', 26) +WGPUTextureFormat_RG11B10Ufloat = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG11B10Ufloat', 27) +WGPUTextureFormat_RGB9E5Ufloat = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGB9E5Ufloat', 28) +WGPUTextureFormat_RG32Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG32Float', 29) +WGPUTextureFormat_RG32Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG32Uint', 30) +WGPUTextureFormat_RG32Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG32Sint', 31) +WGPUTextureFormat_RGBA16Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA16Uint', 32) +WGPUTextureFormat_RGBA16Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA16Sint', 33) +WGPUTextureFormat_RGBA16Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA16Float', 34) +WGPUTextureFormat_RGBA32Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA32Float', 35) +WGPUTextureFormat_RGBA32Uint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA32Uint', 36) +WGPUTextureFormat_RGBA32Sint = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA32Sint', 37) +WGPUTextureFormat_Stencil8 = enum_WGPUTextureFormat.define('WGPUTextureFormat_Stencil8', 38) +WGPUTextureFormat_Depth16Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_Depth16Unorm', 39) +WGPUTextureFormat_Depth24Plus = enum_WGPUTextureFormat.define('WGPUTextureFormat_Depth24Plus', 40) +WGPUTextureFormat_Depth24PlusStencil8 = enum_WGPUTextureFormat.define('WGPUTextureFormat_Depth24PlusStencil8', 41) +WGPUTextureFormat_Depth32Float = enum_WGPUTextureFormat.define('WGPUTextureFormat_Depth32Float', 42) +WGPUTextureFormat_Depth32FloatStencil8 = enum_WGPUTextureFormat.define('WGPUTextureFormat_Depth32FloatStencil8', 43) +WGPUTextureFormat_BC1RGBAUnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC1RGBAUnorm', 44) +WGPUTextureFormat_BC1RGBAUnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC1RGBAUnormSrgb', 45) +WGPUTextureFormat_BC2RGBAUnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC2RGBAUnorm', 46) +WGPUTextureFormat_BC2RGBAUnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC2RGBAUnormSrgb', 47) +WGPUTextureFormat_BC3RGBAUnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC3RGBAUnorm', 48) +WGPUTextureFormat_BC3RGBAUnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC3RGBAUnormSrgb', 49) +WGPUTextureFormat_BC4RUnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC4RUnorm', 50) +WGPUTextureFormat_BC4RSnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC4RSnorm', 51) +WGPUTextureFormat_BC5RGUnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC5RGUnorm', 52) +WGPUTextureFormat_BC5RGSnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC5RGSnorm', 53) +WGPUTextureFormat_BC6HRGBUfloat = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC6HRGBUfloat', 54) +WGPUTextureFormat_BC6HRGBFloat = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC6HRGBFloat', 55) +WGPUTextureFormat_BC7RGBAUnorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC7RGBAUnorm', 56) +WGPUTextureFormat_BC7RGBAUnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_BC7RGBAUnormSrgb', 57) +WGPUTextureFormat_ETC2RGB8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ETC2RGB8Unorm', 58) +WGPUTextureFormat_ETC2RGB8UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ETC2RGB8UnormSrgb', 59) +WGPUTextureFormat_ETC2RGB8A1Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ETC2RGB8A1Unorm', 60) +WGPUTextureFormat_ETC2RGB8A1UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ETC2RGB8A1UnormSrgb', 61) +WGPUTextureFormat_ETC2RGBA8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ETC2RGBA8Unorm', 62) +WGPUTextureFormat_ETC2RGBA8UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ETC2RGBA8UnormSrgb', 63) +WGPUTextureFormat_EACR11Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_EACR11Unorm', 64) +WGPUTextureFormat_EACR11Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_EACR11Snorm', 65) +WGPUTextureFormat_EACRG11Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_EACRG11Unorm', 66) +WGPUTextureFormat_EACRG11Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_EACRG11Snorm', 67) +WGPUTextureFormat_ASTC4x4Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC4x4Unorm', 68) +WGPUTextureFormat_ASTC4x4UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC4x4UnormSrgb', 69) +WGPUTextureFormat_ASTC5x4Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC5x4Unorm', 70) +WGPUTextureFormat_ASTC5x4UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC5x4UnormSrgb', 71) +WGPUTextureFormat_ASTC5x5Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC5x5Unorm', 72) +WGPUTextureFormat_ASTC5x5UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC5x5UnormSrgb', 73) +WGPUTextureFormat_ASTC6x5Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC6x5Unorm', 74) +WGPUTextureFormat_ASTC6x5UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC6x5UnormSrgb', 75) +WGPUTextureFormat_ASTC6x6Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC6x6Unorm', 76) +WGPUTextureFormat_ASTC6x6UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC6x6UnormSrgb', 77) +WGPUTextureFormat_ASTC8x5Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC8x5Unorm', 78) +WGPUTextureFormat_ASTC8x5UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC8x5UnormSrgb', 79) +WGPUTextureFormat_ASTC8x6Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC8x6Unorm', 80) +WGPUTextureFormat_ASTC8x6UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC8x6UnormSrgb', 81) +WGPUTextureFormat_ASTC8x8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC8x8Unorm', 82) +WGPUTextureFormat_ASTC8x8UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC8x8UnormSrgb', 83) +WGPUTextureFormat_ASTC10x5Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x5Unorm', 84) +WGPUTextureFormat_ASTC10x5UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x5UnormSrgb', 85) +WGPUTextureFormat_ASTC10x6Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x6Unorm', 86) +WGPUTextureFormat_ASTC10x6UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x6UnormSrgb', 87) +WGPUTextureFormat_ASTC10x8Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x8Unorm', 88) +WGPUTextureFormat_ASTC10x8UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x8UnormSrgb', 89) +WGPUTextureFormat_ASTC10x10Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x10Unorm', 90) +WGPUTextureFormat_ASTC10x10UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC10x10UnormSrgb', 91) +WGPUTextureFormat_ASTC12x10Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC12x10Unorm', 92) +WGPUTextureFormat_ASTC12x10UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC12x10UnormSrgb', 93) +WGPUTextureFormat_ASTC12x12Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC12x12Unorm', 94) +WGPUTextureFormat_ASTC12x12UnormSrgb = enum_WGPUTextureFormat.define('WGPUTextureFormat_ASTC12x12UnormSrgb', 95) +WGPUTextureFormat_R16Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R16Unorm', 327680) +WGPUTextureFormat_RG16Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG16Unorm', 327681) +WGPUTextureFormat_RGBA16Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA16Unorm', 327682) +WGPUTextureFormat_R16Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R16Snorm', 327683) +WGPUTextureFormat_RG16Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RG16Snorm', 327684) +WGPUTextureFormat_RGBA16Snorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_RGBA16Snorm', 327685) +WGPUTextureFormat_R8BG8Biplanar420Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8BG8Biplanar420Unorm', 327686) +WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm', 327687) +WGPUTextureFormat_R8BG8A8Triplanar420Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8BG8A8Triplanar420Unorm', 327688) +WGPUTextureFormat_R8BG8Biplanar422Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8BG8Biplanar422Unorm', 327689) +WGPUTextureFormat_R8BG8Biplanar444Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R8BG8Biplanar444Unorm', 327690) +WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm', 327691) +WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm = enum_WGPUTextureFormat.define('WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm', 327692) +WGPUTextureFormat_External = enum_WGPUTextureFormat.define('WGPUTextureFormat_External', 327693) +WGPUTextureFormat_Force32 = enum_WGPUTextureFormat.define('WGPUTextureFormat_Force32', 2147483647) + +WGPUTextureFormat = enum_WGPUTextureFormat +struct_WGPUPipelineLayoutStorageAttachment._fields_ = [ + ('offset', uint64_t), + ('format', WGPUTextureFormat), +] +class struct_WGPUPopErrorScopeCallbackInfo(Struct): pass +enum_WGPUPopErrorScopeStatus = CEnum(ctypes.c_uint32) +WGPUPopErrorScopeStatus_Success = enum_WGPUPopErrorScopeStatus.define('WGPUPopErrorScopeStatus_Success', 1) +WGPUPopErrorScopeStatus_InstanceDropped = enum_WGPUPopErrorScopeStatus.define('WGPUPopErrorScopeStatus_InstanceDropped', 2) +WGPUPopErrorScopeStatus_Force32 = enum_WGPUPopErrorScopeStatus.define('WGPUPopErrorScopeStatus_Force32', 2147483647) + +enum_WGPUErrorType = CEnum(ctypes.c_uint32) +WGPUErrorType_NoError = enum_WGPUErrorType.define('WGPUErrorType_NoError', 1) +WGPUErrorType_Validation = enum_WGPUErrorType.define('WGPUErrorType_Validation', 2) +WGPUErrorType_OutOfMemory = enum_WGPUErrorType.define('WGPUErrorType_OutOfMemory', 3) +WGPUErrorType_Internal = enum_WGPUErrorType.define('WGPUErrorType_Internal', 4) +WGPUErrorType_Unknown = enum_WGPUErrorType.define('WGPUErrorType_Unknown', 5) +WGPUErrorType_DeviceLost = enum_WGPUErrorType.define('WGPUErrorType_DeviceLost', 6) +WGPUErrorType_Force32 = enum_WGPUErrorType.define('WGPUErrorType_Force32', 2147483647) + +WGPUPopErrorScopeCallback = ctypes.CFUNCTYPE(None, enum_WGPUPopErrorScopeStatus, enum_WGPUErrorType, struct_WGPUStringView, ctypes.c_void_p) +WGPUErrorCallback = ctypes.CFUNCTYPE(None, enum_WGPUErrorType, struct_WGPUStringView, ctypes.c_void_p) +struct_WGPUPopErrorScopeCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUPopErrorScopeCallback), + ('oldCallback', WGPUErrorCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUPrimitiveState(Struct): pass +enum_WGPUPrimitiveTopology = CEnum(ctypes.c_uint32) +WGPUPrimitiveTopology_Undefined = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_Undefined', 0) +WGPUPrimitiveTopology_PointList = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_PointList', 1) +WGPUPrimitiveTopology_LineList = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_LineList', 2) +WGPUPrimitiveTopology_LineStrip = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_LineStrip', 3) +WGPUPrimitiveTopology_TriangleList = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_TriangleList', 4) +WGPUPrimitiveTopology_TriangleStrip = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_TriangleStrip', 5) +WGPUPrimitiveTopology_Force32 = enum_WGPUPrimitiveTopology.define('WGPUPrimitiveTopology_Force32', 2147483647) + +WGPUPrimitiveTopology = enum_WGPUPrimitiveTopology +enum_WGPUIndexFormat = CEnum(ctypes.c_uint32) +WGPUIndexFormat_Undefined = enum_WGPUIndexFormat.define('WGPUIndexFormat_Undefined', 0) +WGPUIndexFormat_Uint16 = enum_WGPUIndexFormat.define('WGPUIndexFormat_Uint16', 1) +WGPUIndexFormat_Uint32 = enum_WGPUIndexFormat.define('WGPUIndexFormat_Uint32', 2) +WGPUIndexFormat_Force32 = enum_WGPUIndexFormat.define('WGPUIndexFormat_Force32', 2147483647) + +WGPUIndexFormat = enum_WGPUIndexFormat +enum_WGPUFrontFace = CEnum(ctypes.c_uint32) +WGPUFrontFace_Undefined = enum_WGPUFrontFace.define('WGPUFrontFace_Undefined', 0) +WGPUFrontFace_CCW = enum_WGPUFrontFace.define('WGPUFrontFace_CCW', 1) +WGPUFrontFace_CW = enum_WGPUFrontFace.define('WGPUFrontFace_CW', 2) +WGPUFrontFace_Force32 = enum_WGPUFrontFace.define('WGPUFrontFace_Force32', 2147483647) + +WGPUFrontFace = enum_WGPUFrontFace +enum_WGPUCullMode = CEnum(ctypes.c_uint32) +WGPUCullMode_Undefined = enum_WGPUCullMode.define('WGPUCullMode_Undefined', 0) +WGPUCullMode_None = enum_WGPUCullMode.define('WGPUCullMode_None', 1) +WGPUCullMode_Front = enum_WGPUCullMode.define('WGPUCullMode_Front', 2) +WGPUCullMode_Back = enum_WGPUCullMode.define('WGPUCullMode_Back', 3) +WGPUCullMode_Force32 = enum_WGPUCullMode.define('WGPUCullMode_Force32', 2147483647) + +WGPUCullMode = enum_WGPUCullMode +struct_WGPUPrimitiveState._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('topology', WGPUPrimitiveTopology), + ('stripIndexFormat', WGPUIndexFormat), + ('frontFace', WGPUFrontFace), + ('cullMode', WGPUCullMode), + ('unclippedDepth', WGPUBool), +] +class struct_WGPUQueueWorkDoneCallbackInfo(Struct): pass +enum_WGPUQueueWorkDoneStatus = CEnum(ctypes.c_uint32) +WGPUQueueWorkDoneStatus_Success = enum_WGPUQueueWorkDoneStatus.define('WGPUQueueWorkDoneStatus_Success', 1) +WGPUQueueWorkDoneStatus_InstanceDropped = enum_WGPUQueueWorkDoneStatus.define('WGPUQueueWorkDoneStatus_InstanceDropped', 2) +WGPUQueueWorkDoneStatus_Error = enum_WGPUQueueWorkDoneStatus.define('WGPUQueueWorkDoneStatus_Error', 3) +WGPUQueueWorkDoneStatus_Unknown = enum_WGPUQueueWorkDoneStatus.define('WGPUQueueWorkDoneStatus_Unknown', 4) +WGPUQueueWorkDoneStatus_DeviceLost = enum_WGPUQueueWorkDoneStatus.define('WGPUQueueWorkDoneStatus_DeviceLost', 5) +WGPUQueueWorkDoneStatus_Force32 = enum_WGPUQueueWorkDoneStatus.define('WGPUQueueWorkDoneStatus_Force32', 2147483647) + +WGPUQueueWorkDoneCallback = ctypes.CFUNCTYPE(None, enum_WGPUQueueWorkDoneStatus, ctypes.c_void_p) +struct_WGPUQueueWorkDoneCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUQueueWorkDoneCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPURenderPassDepthStencilAttachment(Struct): pass +enum_WGPULoadOp = CEnum(ctypes.c_uint32) +WGPULoadOp_Undefined = enum_WGPULoadOp.define('WGPULoadOp_Undefined', 0) +WGPULoadOp_Load = enum_WGPULoadOp.define('WGPULoadOp_Load', 1) +WGPULoadOp_Clear = enum_WGPULoadOp.define('WGPULoadOp_Clear', 2) +WGPULoadOp_ExpandResolveTexture = enum_WGPULoadOp.define('WGPULoadOp_ExpandResolveTexture', 327683) +WGPULoadOp_Force32 = enum_WGPULoadOp.define('WGPULoadOp_Force32', 2147483647) + +WGPULoadOp = enum_WGPULoadOp +enum_WGPUStoreOp = CEnum(ctypes.c_uint32) +WGPUStoreOp_Undefined = enum_WGPUStoreOp.define('WGPUStoreOp_Undefined', 0) +WGPUStoreOp_Store = enum_WGPUStoreOp.define('WGPUStoreOp_Store', 1) +WGPUStoreOp_Discard = enum_WGPUStoreOp.define('WGPUStoreOp_Discard', 2) +WGPUStoreOp_Force32 = enum_WGPUStoreOp.define('WGPUStoreOp_Force32', 2147483647) + +WGPUStoreOp = enum_WGPUStoreOp +struct_WGPURenderPassDepthStencilAttachment._fields_ = [ + ('view', WGPUTextureView), + ('depthLoadOp', WGPULoadOp), + ('depthStoreOp', WGPUStoreOp), + ('depthClearValue', ctypes.c_float), + ('depthReadOnly', WGPUBool), + ('stencilLoadOp', WGPULoadOp), + ('stencilStoreOp', WGPUStoreOp), + ('stencilClearValue', uint32_t), + ('stencilReadOnly', WGPUBool), +] +class struct_WGPURenderPassDescriptorExpandResolveRect(Struct): pass +struct_WGPURenderPassDescriptorExpandResolveRect._fields_ = [ + ('chain', WGPUChainedStruct), + ('x', uint32_t), + ('y', uint32_t), + ('width', uint32_t), + ('height', uint32_t), +] +class struct_WGPURenderPassMaxDrawCount(Struct): pass +struct_WGPURenderPassMaxDrawCount._fields_ = [ + ('chain', WGPUChainedStruct), + ('maxDrawCount', uint64_t), +] +class struct_WGPURenderPassTimestampWrites(Struct): pass +struct_WGPURenderPassTimestampWrites._fields_ = [ + ('querySet', WGPUQuerySet), + ('beginningOfPassWriteIndex', uint32_t), + ('endOfPassWriteIndex', uint32_t), +] +class struct_WGPURequestAdapterCallbackInfo(Struct): pass +enum_WGPURequestAdapterStatus = CEnum(ctypes.c_uint32) +WGPURequestAdapterStatus_Success = enum_WGPURequestAdapterStatus.define('WGPURequestAdapterStatus_Success', 1) +WGPURequestAdapterStatus_InstanceDropped = enum_WGPURequestAdapterStatus.define('WGPURequestAdapterStatus_InstanceDropped', 2) +WGPURequestAdapterStatus_Unavailable = enum_WGPURequestAdapterStatus.define('WGPURequestAdapterStatus_Unavailable', 3) +WGPURequestAdapterStatus_Error = enum_WGPURequestAdapterStatus.define('WGPURequestAdapterStatus_Error', 4) +WGPURequestAdapterStatus_Unknown = enum_WGPURequestAdapterStatus.define('WGPURequestAdapterStatus_Unknown', 5) +WGPURequestAdapterStatus_Force32 = enum_WGPURequestAdapterStatus.define('WGPURequestAdapterStatus_Force32', 2147483647) + +WGPURequestAdapterCallback = ctypes.CFUNCTYPE(None, enum_WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.c_void_p) +struct_WGPURequestAdapterCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPURequestAdapterCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPURequestAdapterOptions(Struct): pass +enum_WGPUFeatureLevel = CEnum(ctypes.c_uint32) +WGPUFeatureLevel_Undefined = enum_WGPUFeatureLevel.define('WGPUFeatureLevel_Undefined', 0) +WGPUFeatureLevel_Compatibility = enum_WGPUFeatureLevel.define('WGPUFeatureLevel_Compatibility', 1) +WGPUFeatureLevel_Core = enum_WGPUFeatureLevel.define('WGPUFeatureLevel_Core', 2) +WGPUFeatureLevel_Force32 = enum_WGPUFeatureLevel.define('WGPUFeatureLevel_Force32', 2147483647) + +WGPUFeatureLevel = enum_WGPUFeatureLevel +enum_WGPUBackendType = CEnum(ctypes.c_uint32) +WGPUBackendType_Undefined = enum_WGPUBackendType.define('WGPUBackendType_Undefined', 0) +WGPUBackendType_Null = enum_WGPUBackendType.define('WGPUBackendType_Null', 1) +WGPUBackendType_WebGPU = enum_WGPUBackendType.define('WGPUBackendType_WebGPU', 2) +WGPUBackendType_D3D11 = enum_WGPUBackendType.define('WGPUBackendType_D3D11', 3) +WGPUBackendType_D3D12 = enum_WGPUBackendType.define('WGPUBackendType_D3D12', 4) +WGPUBackendType_Metal = enum_WGPUBackendType.define('WGPUBackendType_Metal', 5) +WGPUBackendType_Vulkan = enum_WGPUBackendType.define('WGPUBackendType_Vulkan', 6) +WGPUBackendType_OpenGL = enum_WGPUBackendType.define('WGPUBackendType_OpenGL', 7) +WGPUBackendType_OpenGLES = enum_WGPUBackendType.define('WGPUBackendType_OpenGLES', 8) +WGPUBackendType_Force32 = enum_WGPUBackendType.define('WGPUBackendType_Force32', 2147483647) + +WGPUBackendType = enum_WGPUBackendType +struct_WGPURequestAdapterOptions._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('compatibleSurface', WGPUSurface), + ('featureLevel', WGPUFeatureLevel), + ('powerPreference', WGPUPowerPreference), + ('backendType', WGPUBackendType), + ('forceFallbackAdapter', WGPUBool), + ('compatibilityMode', WGPUBool), +] +class struct_WGPURequestDeviceCallbackInfo(Struct): pass +enum_WGPURequestDeviceStatus = CEnum(ctypes.c_uint32) +WGPURequestDeviceStatus_Success = enum_WGPURequestDeviceStatus.define('WGPURequestDeviceStatus_Success', 1) +WGPURequestDeviceStatus_InstanceDropped = enum_WGPURequestDeviceStatus.define('WGPURequestDeviceStatus_InstanceDropped', 2) +WGPURequestDeviceStatus_Error = enum_WGPURequestDeviceStatus.define('WGPURequestDeviceStatus_Error', 3) +WGPURequestDeviceStatus_Unknown = enum_WGPURequestDeviceStatus.define('WGPURequestDeviceStatus_Unknown', 4) +WGPURequestDeviceStatus_Force32 = enum_WGPURequestDeviceStatus.define('WGPURequestDeviceStatus_Force32', 2147483647) + +WGPURequestDeviceCallback = ctypes.CFUNCTYPE(None, enum_WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.c_void_p) +struct_WGPURequestDeviceCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPURequestDeviceCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUSamplerBindingLayout(Struct): pass +enum_WGPUSamplerBindingType = CEnum(ctypes.c_uint32) +WGPUSamplerBindingType_BindingNotUsed = enum_WGPUSamplerBindingType.define('WGPUSamplerBindingType_BindingNotUsed', 0) +WGPUSamplerBindingType_Filtering = enum_WGPUSamplerBindingType.define('WGPUSamplerBindingType_Filtering', 1) +WGPUSamplerBindingType_NonFiltering = enum_WGPUSamplerBindingType.define('WGPUSamplerBindingType_NonFiltering', 2) +WGPUSamplerBindingType_Comparison = enum_WGPUSamplerBindingType.define('WGPUSamplerBindingType_Comparison', 3) +WGPUSamplerBindingType_Force32 = enum_WGPUSamplerBindingType.define('WGPUSamplerBindingType_Force32', 2147483647) + +WGPUSamplerBindingType = enum_WGPUSamplerBindingType +struct_WGPUSamplerBindingLayout._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('type', WGPUSamplerBindingType), +] +class struct_WGPUShaderModuleCompilationOptions(Struct): pass +struct_WGPUShaderModuleCompilationOptions._fields_ = [ + ('chain', WGPUChainedStruct), + ('strictMath', WGPUBool), +] +class struct_WGPUShaderSourceSPIRV(Struct): pass +struct_WGPUShaderSourceSPIRV._fields_ = [ + ('chain', WGPUChainedStruct), + ('codeSize', uint32_t), + ('code', ctypes.POINTER(uint32_t)), +] +class struct_WGPUSharedBufferMemoryBeginAccessDescriptor(Struct): pass +struct_WGPUSharedBufferMemoryBeginAccessDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('initialized', WGPUBool), + ('fenceCount', size_t), + ('fences', ctypes.POINTER(WGPUSharedFence)), + ('signaledValues', ctypes.POINTER(uint64_t)), +] +class struct_WGPUSharedBufferMemoryEndAccessState(Struct): pass +struct_WGPUSharedBufferMemoryEndAccessState._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('initialized', WGPUBool), + ('fenceCount', size_t), + ('fences', ctypes.POINTER(WGPUSharedFence)), + ('signaledValues', ctypes.POINTER(uint64_t)), +] +class struct_WGPUSharedBufferMemoryProperties(Struct): pass +WGPUBufferUsage = ctypes.c_uint64 +struct_WGPUSharedBufferMemoryProperties._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('usage', WGPUBufferUsage), + ('size', uint64_t), +] +class struct_WGPUSharedFenceDXGISharedHandleDescriptor(Struct): pass +struct_WGPUSharedFenceDXGISharedHandleDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('handle', ctypes.c_void_p), +] +class struct_WGPUSharedFenceDXGISharedHandleExportInfo(Struct): pass +struct_WGPUSharedFenceDXGISharedHandleExportInfo._fields_ = [ + ('chain', WGPUChainedStructOut), + ('handle', ctypes.c_void_p), +] +class struct_WGPUSharedFenceMTLSharedEventDescriptor(Struct): pass +struct_WGPUSharedFenceMTLSharedEventDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('sharedEvent', ctypes.c_void_p), +] +class struct_WGPUSharedFenceMTLSharedEventExportInfo(Struct): pass +struct_WGPUSharedFenceMTLSharedEventExportInfo._fields_ = [ + ('chain', WGPUChainedStructOut), + ('sharedEvent', ctypes.c_void_p), +] +class struct_WGPUSharedFenceExportInfo(Struct): pass +enum_WGPUSharedFenceType = CEnum(ctypes.c_uint32) +WGPUSharedFenceType_VkSemaphoreOpaqueFD = enum_WGPUSharedFenceType.define('WGPUSharedFenceType_VkSemaphoreOpaqueFD', 1) +WGPUSharedFenceType_SyncFD = enum_WGPUSharedFenceType.define('WGPUSharedFenceType_SyncFD', 2) +WGPUSharedFenceType_VkSemaphoreZirconHandle = enum_WGPUSharedFenceType.define('WGPUSharedFenceType_VkSemaphoreZirconHandle', 3) +WGPUSharedFenceType_DXGISharedHandle = enum_WGPUSharedFenceType.define('WGPUSharedFenceType_DXGISharedHandle', 4) +WGPUSharedFenceType_MTLSharedEvent = enum_WGPUSharedFenceType.define('WGPUSharedFenceType_MTLSharedEvent', 5) +WGPUSharedFenceType_Force32 = enum_WGPUSharedFenceType.define('WGPUSharedFenceType_Force32', 2147483647) + +WGPUSharedFenceType = enum_WGPUSharedFenceType +struct_WGPUSharedFenceExportInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('type', WGPUSharedFenceType), +] +class struct_WGPUSharedFenceSyncFDDescriptor(Struct): pass +struct_WGPUSharedFenceSyncFDDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('handle', ctypes.c_int32), +] +class struct_WGPUSharedFenceSyncFDExportInfo(Struct): pass +struct_WGPUSharedFenceSyncFDExportInfo._fields_ = [ + ('chain', WGPUChainedStructOut), + ('handle', ctypes.c_int32), +] +class struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor(Struct): pass +struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('handle', ctypes.c_int32), +] +class struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo(Struct): pass +struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo._fields_ = [ + ('chain', WGPUChainedStructOut), + ('handle', ctypes.c_int32), +] +class struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor(Struct): pass +struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('handle', uint32_t), +] +class struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo(Struct): pass +struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo._fields_ = [ + ('chain', WGPUChainedStructOut), + ('handle', uint32_t), +] +class struct_WGPUSharedTextureMemoryD3DSwapchainBeginState(Struct): pass +struct_WGPUSharedTextureMemoryD3DSwapchainBeginState._fields_ = [ + ('chain', WGPUChainedStruct), + ('isSwapchain', WGPUBool), +] +class struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('handle', ctypes.c_void_p), + ('useKeyedMutex', WGPUBool), +] +class struct_WGPUSharedTextureMemoryEGLImageDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryEGLImageDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('image', ctypes.c_void_p), +] +class struct_WGPUSharedTextureMemoryIOSurfaceDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryIOSurfaceDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('ioSurface', ctypes.c_void_p), +] +class struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('handle', ctypes.c_void_p), + ('useExternalFormat', WGPUBool), +] +class struct_WGPUSharedTextureMemoryBeginAccessDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryBeginAccessDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('concurrentRead', WGPUBool), + ('initialized', WGPUBool), + ('fenceCount', size_t), + ('fences', ctypes.POINTER(WGPUSharedFence)), + ('signaledValues', ctypes.POINTER(uint64_t)), +] +class struct_WGPUSharedTextureMemoryDmaBufPlane(Struct): pass +struct_WGPUSharedTextureMemoryDmaBufPlane._fields_ = [ + ('fd', ctypes.c_int32), + ('offset', uint64_t), + ('stride', uint32_t), +] +class struct_WGPUSharedTextureMemoryEndAccessState(Struct): pass +struct_WGPUSharedTextureMemoryEndAccessState._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('initialized', WGPUBool), + ('fenceCount', size_t), + ('fences', ctypes.POINTER(WGPUSharedFence)), + ('signaledValues', ctypes.POINTER(uint64_t)), +] +class struct_WGPUSharedTextureMemoryOpaqueFDDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryOpaqueFDDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('vkImageCreateInfo', ctypes.c_void_p), + ('memoryFD', ctypes.c_int32), + ('memoryTypeIndex', uint32_t), + ('allocationSize', uint64_t), + ('dedicatedAllocation', WGPUBool), +] +class struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('dedicatedAllocation', WGPUBool), +] +class struct_WGPUSharedTextureMemoryVkImageLayoutBeginState(Struct): pass +int32_t = ctypes.c_int32 +struct_WGPUSharedTextureMemoryVkImageLayoutBeginState._fields_ = [ + ('chain', WGPUChainedStruct), + ('oldLayout', int32_t), + ('newLayout', int32_t), +] +class struct_WGPUSharedTextureMemoryVkImageLayoutEndState(Struct): pass +struct_WGPUSharedTextureMemoryVkImageLayoutEndState._fields_ = [ + ('chain', WGPUChainedStructOut), + ('oldLayout', int32_t), + ('newLayout', int32_t), +] +class struct_WGPUSharedTextureMemoryZirconHandleDescriptor(Struct): pass +struct_WGPUSharedTextureMemoryZirconHandleDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('memoryFD', uint32_t), + ('allocationSize', uint64_t), +] +class struct_WGPUStaticSamplerBindingLayout(Struct): pass +struct_WGPUStaticSamplerBindingLayout._fields_ = [ + ('chain', WGPUChainedStruct), + ('sampler', WGPUSampler), + ('sampledTextureBinding', uint32_t), +] +class struct_WGPUStencilFaceState(Struct): pass +enum_WGPUCompareFunction = CEnum(ctypes.c_uint32) +WGPUCompareFunction_Undefined = enum_WGPUCompareFunction.define('WGPUCompareFunction_Undefined', 0) +WGPUCompareFunction_Never = enum_WGPUCompareFunction.define('WGPUCompareFunction_Never', 1) +WGPUCompareFunction_Less = enum_WGPUCompareFunction.define('WGPUCompareFunction_Less', 2) +WGPUCompareFunction_Equal = enum_WGPUCompareFunction.define('WGPUCompareFunction_Equal', 3) +WGPUCompareFunction_LessEqual = enum_WGPUCompareFunction.define('WGPUCompareFunction_LessEqual', 4) +WGPUCompareFunction_Greater = enum_WGPUCompareFunction.define('WGPUCompareFunction_Greater', 5) +WGPUCompareFunction_NotEqual = enum_WGPUCompareFunction.define('WGPUCompareFunction_NotEqual', 6) +WGPUCompareFunction_GreaterEqual = enum_WGPUCompareFunction.define('WGPUCompareFunction_GreaterEqual', 7) +WGPUCompareFunction_Always = enum_WGPUCompareFunction.define('WGPUCompareFunction_Always', 8) +WGPUCompareFunction_Force32 = enum_WGPUCompareFunction.define('WGPUCompareFunction_Force32', 2147483647) + +WGPUCompareFunction = enum_WGPUCompareFunction +enum_WGPUStencilOperation = CEnum(ctypes.c_uint32) +WGPUStencilOperation_Undefined = enum_WGPUStencilOperation.define('WGPUStencilOperation_Undefined', 0) +WGPUStencilOperation_Keep = enum_WGPUStencilOperation.define('WGPUStencilOperation_Keep', 1) +WGPUStencilOperation_Zero = enum_WGPUStencilOperation.define('WGPUStencilOperation_Zero', 2) +WGPUStencilOperation_Replace = enum_WGPUStencilOperation.define('WGPUStencilOperation_Replace', 3) +WGPUStencilOperation_Invert = enum_WGPUStencilOperation.define('WGPUStencilOperation_Invert', 4) +WGPUStencilOperation_IncrementClamp = enum_WGPUStencilOperation.define('WGPUStencilOperation_IncrementClamp', 5) +WGPUStencilOperation_DecrementClamp = enum_WGPUStencilOperation.define('WGPUStencilOperation_DecrementClamp', 6) +WGPUStencilOperation_IncrementWrap = enum_WGPUStencilOperation.define('WGPUStencilOperation_IncrementWrap', 7) +WGPUStencilOperation_DecrementWrap = enum_WGPUStencilOperation.define('WGPUStencilOperation_DecrementWrap', 8) +WGPUStencilOperation_Force32 = enum_WGPUStencilOperation.define('WGPUStencilOperation_Force32', 2147483647) + +WGPUStencilOperation = enum_WGPUStencilOperation +struct_WGPUStencilFaceState._fields_ = [ + ('compare', WGPUCompareFunction), + ('failOp', WGPUStencilOperation), + ('depthFailOp', WGPUStencilOperation), + ('passOp', WGPUStencilOperation), +] +class struct_WGPUStorageTextureBindingLayout(Struct): pass +enum_WGPUStorageTextureAccess = CEnum(ctypes.c_uint32) +WGPUStorageTextureAccess_BindingNotUsed = enum_WGPUStorageTextureAccess.define('WGPUStorageTextureAccess_BindingNotUsed', 0) +WGPUStorageTextureAccess_WriteOnly = enum_WGPUStorageTextureAccess.define('WGPUStorageTextureAccess_WriteOnly', 1) +WGPUStorageTextureAccess_ReadOnly = enum_WGPUStorageTextureAccess.define('WGPUStorageTextureAccess_ReadOnly', 2) +WGPUStorageTextureAccess_ReadWrite = enum_WGPUStorageTextureAccess.define('WGPUStorageTextureAccess_ReadWrite', 3) +WGPUStorageTextureAccess_Force32 = enum_WGPUStorageTextureAccess.define('WGPUStorageTextureAccess_Force32', 2147483647) + +WGPUStorageTextureAccess = enum_WGPUStorageTextureAccess +enum_WGPUTextureViewDimension = CEnum(ctypes.c_uint32) +WGPUTextureViewDimension_Undefined = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_Undefined', 0) +WGPUTextureViewDimension_1D = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_1D', 1) +WGPUTextureViewDimension_2D = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_2D', 2) +WGPUTextureViewDimension_2DArray = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_2DArray', 3) +WGPUTextureViewDimension_Cube = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_Cube', 4) +WGPUTextureViewDimension_CubeArray = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_CubeArray', 5) +WGPUTextureViewDimension_3D = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_3D', 6) +WGPUTextureViewDimension_Force32 = enum_WGPUTextureViewDimension.define('WGPUTextureViewDimension_Force32', 2147483647) + +WGPUTextureViewDimension = enum_WGPUTextureViewDimension +struct_WGPUStorageTextureBindingLayout._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('access', WGPUStorageTextureAccess), + ('format', WGPUTextureFormat), + ('viewDimension', WGPUTextureViewDimension), +] +class struct_WGPUSupportedFeatures(Struct): pass +enum_WGPUFeatureName = CEnum(ctypes.c_uint32) +WGPUFeatureName_DepthClipControl = enum_WGPUFeatureName.define('WGPUFeatureName_DepthClipControl', 1) +WGPUFeatureName_Depth32FloatStencil8 = enum_WGPUFeatureName.define('WGPUFeatureName_Depth32FloatStencil8', 2) +WGPUFeatureName_TimestampQuery = enum_WGPUFeatureName.define('WGPUFeatureName_TimestampQuery', 3) +WGPUFeatureName_TextureCompressionBC = enum_WGPUFeatureName.define('WGPUFeatureName_TextureCompressionBC', 4) +WGPUFeatureName_TextureCompressionETC2 = enum_WGPUFeatureName.define('WGPUFeatureName_TextureCompressionETC2', 5) +WGPUFeatureName_TextureCompressionASTC = enum_WGPUFeatureName.define('WGPUFeatureName_TextureCompressionASTC', 6) +WGPUFeatureName_IndirectFirstInstance = enum_WGPUFeatureName.define('WGPUFeatureName_IndirectFirstInstance', 7) +WGPUFeatureName_ShaderF16 = enum_WGPUFeatureName.define('WGPUFeatureName_ShaderF16', 8) +WGPUFeatureName_RG11B10UfloatRenderable = enum_WGPUFeatureName.define('WGPUFeatureName_RG11B10UfloatRenderable', 9) +WGPUFeatureName_BGRA8UnormStorage = enum_WGPUFeatureName.define('WGPUFeatureName_BGRA8UnormStorage', 10) +WGPUFeatureName_Float32Filterable = enum_WGPUFeatureName.define('WGPUFeatureName_Float32Filterable', 11) +WGPUFeatureName_Float32Blendable = enum_WGPUFeatureName.define('WGPUFeatureName_Float32Blendable', 12) +WGPUFeatureName_Subgroups = enum_WGPUFeatureName.define('WGPUFeatureName_Subgroups', 13) +WGPUFeatureName_SubgroupsF16 = enum_WGPUFeatureName.define('WGPUFeatureName_SubgroupsF16', 14) +WGPUFeatureName_DawnInternalUsages = enum_WGPUFeatureName.define('WGPUFeatureName_DawnInternalUsages', 327680) +WGPUFeatureName_DawnMultiPlanarFormats = enum_WGPUFeatureName.define('WGPUFeatureName_DawnMultiPlanarFormats', 327681) +WGPUFeatureName_DawnNative = enum_WGPUFeatureName.define('WGPUFeatureName_DawnNative', 327682) +WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses = enum_WGPUFeatureName.define('WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses', 327683) +WGPUFeatureName_ImplicitDeviceSynchronization = enum_WGPUFeatureName.define('WGPUFeatureName_ImplicitDeviceSynchronization', 327684) +WGPUFeatureName_ChromiumExperimentalImmediateData = enum_WGPUFeatureName.define('WGPUFeatureName_ChromiumExperimentalImmediateData', 327685) +WGPUFeatureName_TransientAttachments = enum_WGPUFeatureName.define('WGPUFeatureName_TransientAttachments', 327686) +WGPUFeatureName_MSAARenderToSingleSampled = enum_WGPUFeatureName.define('WGPUFeatureName_MSAARenderToSingleSampled', 327687) +WGPUFeatureName_DualSourceBlending = enum_WGPUFeatureName.define('WGPUFeatureName_DualSourceBlending', 327688) +WGPUFeatureName_D3D11MultithreadProtected = enum_WGPUFeatureName.define('WGPUFeatureName_D3D11MultithreadProtected', 327689) +WGPUFeatureName_ANGLETextureSharing = enum_WGPUFeatureName.define('WGPUFeatureName_ANGLETextureSharing', 327690) +WGPUFeatureName_PixelLocalStorageCoherent = enum_WGPUFeatureName.define('WGPUFeatureName_PixelLocalStorageCoherent', 327691) +WGPUFeatureName_PixelLocalStorageNonCoherent = enum_WGPUFeatureName.define('WGPUFeatureName_PixelLocalStorageNonCoherent', 327692) +WGPUFeatureName_Unorm16TextureFormats = enum_WGPUFeatureName.define('WGPUFeatureName_Unorm16TextureFormats', 327693) +WGPUFeatureName_Snorm16TextureFormats = enum_WGPUFeatureName.define('WGPUFeatureName_Snorm16TextureFormats', 327694) +WGPUFeatureName_MultiPlanarFormatExtendedUsages = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatExtendedUsages', 327695) +WGPUFeatureName_MultiPlanarFormatP010 = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatP010', 327696) +WGPUFeatureName_HostMappedPointer = enum_WGPUFeatureName.define('WGPUFeatureName_HostMappedPointer', 327697) +WGPUFeatureName_MultiPlanarRenderTargets = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarRenderTargets', 327698) +WGPUFeatureName_MultiPlanarFormatNv12a = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatNv12a', 327699) +WGPUFeatureName_FramebufferFetch = enum_WGPUFeatureName.define('WGPUFeatureName_FramebufferFetch', 327700) +WGPUFeatureName_BufferMapExtendedUsages = enum_WGPUFeatureName.define('WGPUFeatureName_BufferMapExtendedUsages', 327701) +WGPUFeatureName_AdapterPropertiesMemoryHeaps = enum_WGPUFeatureName.define('WGPUFeatureName_AdapterPropertiesMemoryHeaps', 327702) +WGPUFeatureName_AdapterPropertiesD3D = enum_WGPUFeatureName.define('WGPUFeatureName_AdapterPropertiesD3D', 327703) +WGPUFeatureName_AdapterPropertiesVk = enum_WGPUFeatureName.define('WGPUFeatureName_AdapterPropertiesVk', 327704) +WGPUFeatureName_R8UnormStorage = enum_WGPUFeatureName.define('WGPUFeatureName_R8UnormStorage', 327705) +WGPUFeatureName_FormatCapabilities = enum_WGPUFeatureName.define('WGPUFeatureName_FormatCapabilities', 327706) +WGPUFeatureName_DrmFormatCapabilities = enum_WGPUFeatureName.define('WGPUFeatureName_DrmFormatCapabilities', 327707) +WGPUFeatureName_Norm16TextureFormats = enum_WGPUFeatureName.define('WGPUFeatureName_Norm16TextureFormats', 327708) +WGPUFeatureName_MultiPlanarFormatNv16 = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatNv16', 327709) +WGPUFeatureName_MultiPlanarFormatNv24 = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatNv24', 327710) +WGPUFeatureName_MultiPlanarFormatP210 = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatP210', 327711) +WGPUFeatureName_MultiPlanarFormatP410 = enum_WGPUFeatureName.define('WGPUFeatureName_MultiPlanarFormatP410', 327712) +WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation', 327713) +WGPUFeatureName_SharedTextureMemoryAHardwareBuffer = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryAHardwareBuffer', 327714) +WGPUFeatureName_SharedTextureMemoryDmaBuf = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryDmaBuf', 327715) +WGPUFeatureName_SharedTextureMemoryOpaqueFD = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryOpaqueFD', 327716) +WGPUFeatureName_SharedTextureMemoryZirconHandle = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryZirconHandle', 327717) +WGPUFeatureName_SharedTextureMemoryDXGISharedHandle = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryDXGISharedHandle', 327718) +WGPUFeatureName_SharedTextureMemoryD3D11Texture2D = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryD3D11Texture2D', 327719) +WGPUFeatureName_SharedTextureMemoryIOSurface = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryIOSurface', 327720) +WGPUFeatureName_SharedTextureMemoryEGLImage = enum_WGPUFeatureName.define('WGPUFeatureName_SharedTextureMemoryEGLImage', 327721) +WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD = enum_WGPUFeatureName.define('WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD', 327722) +WGPUFeatureName_SharedFenceSyncFD = enum_WGPUFeatureName.define('WGPUFeatureName_SharedFenceSyncFD', 327723) +WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle = enum_WGPUFeatureName.define('WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle', 327724) +WGPUFeatureName_SharedFenceDXGISharedHandle = enum_WGPUFeatureName.define('WGPUFeatureName_SharedFenceDXGISharedHandle', 327725) +WGPUFeatureName_SharedFenceMTLSharedEvent = enum_WGPUFeatureName.define('WGPUFeatureName_SharedFenceMTLSharedEvent', 327726) +WGPUFeatureName_SharedBufferMemoryD3D12Resource = enum_WGPUFeatureName.define('WGPUFeatureName_SharedBufferMemoryD3D12Resource', 327727) +WGPUFeatureName_StaticSamplers = enum_WGPUFeatureName.define('WGPUFeatureName_StaticSamplers', 327728) +WGPUFeatureName_YCbCrVulkanSamplers = enum_WGPUFeatureName.define('WGPUFeatureName_YCbCrVulkanSamplers', 327729) +WGPUFeatureName_ShaderModuleCompilationOptions = enum_WGPUFeatureName.define('WGPUFeatureName_ShaderModuleCompilationOptions', 327730) +WGPUFeatureName_DawnLoadResolveTexture = enum_WGPUFeatureName.define('WGPUFeatureName_DawnLoadResolveTexture', 327731) +WGPUFeatureName_DawnPartialLoadResolveTexture = enum_WGPUFeatureName.define('WGPUFeatureName_DawnPartialLoadResolveTexture', 327732) +WGPUFeatureName_MultiDrawIndirect = enum_WGPUFeatureName.define('WGPUFeatureName_MultiDrawIndirect', 327733) +WGPUFeatureName_ClipDistances = enum_WGPUFeatureName.define('WGPUFeatureName_ClipDistances', 327734) +WGPUFeatureName_DawnTexelCopyBufferRowAlignment = enum_WGPUFeatureName.define('WGPUFeatureName_DawnTexelCopyBufferRowAlignment', 327735) +WGPUFeatureName_FlexibleTextureViews = enum_WGPUFeatureName.define('WGPUFeatureName_FlexibleTextureViews', 327736) +WGPUFeatureName_Force32 = enum_WGPUFeatureName.define('WGPUFeatureName_Force32', 2147483647) + +WGPUFeatureName = enum_WGPUFeatureName +struct_WGPUSupportedFeatures._fields_ = [ + ('featureCount', size_t), + ('features', ctypes.POINTER(WGPUFeatureName)), +] +class struct_WGPUSurfaceCapabilities(Struct): pass +enum_WGPUPresentMode = CEnum(ctypes.c_uint32) +WGPUPresentMode_Fifo = enum_WGPUPresentMode.define('WGPUPresentMode_Fifo', 1) +WGPUPresentMode_FifoRelaxed = enum_WGPUPresentMode.define('WGPUPresentMode_FifoRelaxed', 2) +WGPUPresentMode_Immediate = enum_WGPUPresentMode.define('WGPUPresentMode_Immediate', 3) +WGPUPresentMode_Mailbox = enum_WGPUPresentMode.define('WGPUPresentMode_Mailbox', 4) +WGPUPresentMode_Force32 = enum_WGPUPresentMode.define('WGPUPresentMode_Force32', 2147483647) + +WGPUPresentMode = enum_WGPUPresentMode +enum_WGPUCompositeAlphaMode = CEnum(ctypes.c_uint32) +WGPUCompositeAlphaMode_Auto = enum_WGPUCompositeAlphaMode.define('WGPUCompositeAlphaMode_Auto', 0) +WGPUCompositeAlphaMode_Opaque = enum_WGPUCompositeAlphaMode.define('WGPUCompositeAlphaMode_Opaque', 1) +WGPUCompositeAlphaMode_Premultiplied = enum_WGPUCompositeAlphaMode.define('WGPUCompositeAlphaMode_Premultiplied', 2) +WGPUCompositeAlphaMode_Unpremultiplied = enum_WGPUCompositeAlphaMode.define('WGPUCompositeAlphaMode_Unpremultiplied', 3) +WGPUCompositeAlphaMode_Inherit = enum_WGPUCompositeAlphaMode.define('WGPUCompositeAlphaMode_Inherit', 4) +WGPUCompositeAlphaMode_Force32 = enum_WGPUCompositeAlphaMode.define('WGPUCompositeAlphaMode_Force32', 2147483647) + +WGPUCompositeAlphaMode = enum_WGPUCompositeAlphaMode +struct_WGPUSurfaceCapabilities._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('usages', WGPUTextureUsage), + ('formatCount', size_t), + ('formats', ctypes.POINTER(WGPUTextureFormat)), + ('presentModeCount', size_t), + ('presentModes', ctypes.POINTER(WGPUPresentMode)), + ('alphaModeCount', size_t), + ('alphaModes', ctypes.POINTER(WGPUCompositeAlphaMode)), +] +class struct_WGPUSurfaceConfiguration(Struct): pass +struct_WGPUSurfaceConfiguration._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('device', WGPUDevice), + ('format', WGPUTextureFormat), + ('usage', WGPUTextureUsage), + ('viewFormatCount', size_t), + ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), + ('alphaMode', WGPUCompositeAlphaMode), + ('width', uint32_t), + ('height', uint32_t), + ('presentMode', WGPUPresentMode), +] +class struct_WGPUSurfaceDescriptorFromWindowsCoreWindow(Struct): pass +struct_WGPUSurfaceDescriptorFromWindowsCoreWindow._fields_ = [ + ('chain', WGPUChainedStruct), + ('coreWindow', ctypes.c_void_p), +] +class struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel(Struct): pass +struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel._fields_ = [ + ('chain', WGPUChainedStruct), + ('swapChainPanel', ctypes.c_void_p), +] +class struct_WGPUSurfaceSourceXCBWindow(Struct): pass +struct_WGPUSurfaceSourceXCBWindow._fields_ = [ + ('chain', WGPUChainedStruct), + ('connection', ctypes.c_void_p), + ('window', uint32_t), +] +class struct_WGPUSurfaceSourceAndroidNativeWindow(Struct): pass +struct_WGPUSurfaceSourceAndroidNativeWindow._fields_ = [ + ('chain', WGPUChainedStruct), + ('window', ctypes.c_void_p), +] +class struct_WGPUSurfaceSourceMetalLayer(Struct): pass +struct_WGPUSurfaceSourceMetalLayer._fields_ = [ + ('chain', WGPUChainedStruct), + ('layer', ctypes.c_void_p), +] +class struct_WGPUSurfaceSourceWaylandSurface(Struct): pass +struct_WGPUSurfaceSourceWaylandSurface._fields_ = [ + ('chain', WGPUChainedStruct), + ('display', ctypes.c_void_p), + ('surface', ctypes.c_void_p), +] +class struct_WGPUSurfaceSourceWindowsHWND(Struct): pass +struct_WGPUSurfaceSourceWindowsHWND._fields_ = [ + ('chain', WGPUChainedStruct), + ('hinstance', ctypes.c_void_p), + ('hwnd', ctypes.c_void_p), +] +class struct_WGPUSurfaceSourceXlibWindow(Struct): pass +struct_WGPUSurfaceSourceXlibWindow._fields_ = [ + ('chain', WGPUChainedStruct), + ('display', ctypes.c_void_p), + ('window', uint64_t), +] +class struct_WGPUSurfaceTexture(Struct): pass +enum_WGPUSurfaceGetCurrentTextureStatus = CEnum(ctypes.c_uint32) +WGPUSurfaceGetCurrentTextureStatus_Success = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_Success', 1) +WGPUSurfaceGetCurrentTextureStatus_Timeout = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_Timeout', 2) +WGPUSurfaceGetCurrentTextureStatus_Outdated = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_Outdated', 3) +WGPUSurfaceGetCurrentTextureStatus_Lost = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_Lost', 4) +WGPUSurfaceGetCurrentTextureStatus_OutOfMemory = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_OutOfMemory', 5) +WGPUSurfaceGetCurrentTextureStatus_DeviceLost = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_DeviceLost', 6) +WGPUSurfaceGetCurrentTextureStatus_Error = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_Error', 7) +WGPUSurfaceGetCurrentTextureStatus_Force32 = enum_WGPUSurfaceGetCurrentTextureStatus.define('WGPUSurfaceGetCurrentTextureStatus_Force32', 2147483647) + +WGPUSurfaceGetCurrentTextureStatus = enum_WGPUSurfaceGetCurrentTextureStatus +struct_WGPUSurfaceTexture._fields_ = [ + ('texture', WGPUTexture), + ('suboptimal', WGPUBool), + ('status', WGPUSurfaceGetCurrentTextureStatus), +] +class struct_WGPUTextureBindingLayout(Struct): pass +enum_WGPUTextureSampleType = CEnum(ctypes.c_uint32) +WGPUTextureSampleType_BindingNotUsed = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_BindingNotUsed', 0) +WGPUTextureSampleType_Float = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_Float', 1) +WGPUTextureSampleType_UnfilterableFloat = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_UnfilterableFloat', 2) +WGPUTextureSampleType_Depth = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_Depth', 3) +WGPUTextureSampleType_Sint = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_Sint', 4) +WGPUTextureSampleType_Uint = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_Uint', 5) +WGPUTextureSampleType_Force32 = enum_WGPUTextureSampleType.define('WGPUTextureSampleType_Force32', 2147483647) + +WGPUTextureSampleType = enum_WGPUTextureSampleType +struct_WGPUTextureBindingLayout._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('sampleType', WGPUTextureSampleType), + ('viewDimension', WGPUTextureViewDimension), + ('multisampled', WGPUBool), +] +class struct_WGPUTextureBindingViewDimensionDescriptor(Struct): pass +struct_WGPUTextureBindingViewDimensionDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('textureBindingViewDimension', WGPUTextureViewDimension), +] +class struct_WGPUTextureDataLayout(Struct): pass +struct_WGPUTextureDataLayout._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('offset', uint64_t), + ('bytesPerRow', uint32_t), + ('rowsPerImage', uint32_t), +] +class struct_WGPUUncapturedErrorCallbackInfo(Struct): pass +struct_WGPUUncapturedErrorCallbackInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('callback', WGPUErrorCallback), + ('userdata', ctypes.c_void_p), +] +class struct_WGPUVertexAttribute(Struct): pass +enum_WGPUVertexFormat = CEnum(ctypes.c_uint32) +WGPUVertexFormat_Uint8 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint8', 1) +WGPUVertexFormat_Uint8x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint8x2', 2) +WGPUVertexFormat_Uint8x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint8x4', 3) +WGPUVertexFormat_Sint8 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint8', 4) +WGPUVertexFormat_Sint8x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint8x2', 5) +WGPUVertexFormat_Sint8x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint8x4', 6) +WGPUVertexFormat_Unorm8 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm8', 7) +WGPUVertexFormat_Unorm8x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm8x2', 8) +WGPUVertexFormat_Unorm8x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm8x4', 9) +WGPUVertexFormat_Snorm8 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Snorm8', 10) +WGPUVertexFormat_Snorm8x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Snorm8x2', 11) +WGPUVertexFormat_Snorm8x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Snorm8x4', 12) +WGPUVertexFormat_Uint16 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint16', 13) +WGPUVertexFormat_Uint16x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint16x2', 14) +WGPUVertexFormat_Uint16x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint16x4', 15) +WGPUVertexFormat_Sint16 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint16', 16) +WGPUVertexFormat_Sint16x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint16x2', 17) +WGPUVertexFormat_Sint16x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint16x4', 18) +WGPUVertexFormat_Unorm16 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm16', 19) +WGPUVertexFormat_Unorm16x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm16x2', 20) +WGPUVertexFormat_Unorm16x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm16x4', 21) +WGPUVertexFormat_Snorm16 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Snorm16', 22) +WGPUVertexFormat_Snorm16x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Snorm16x2', 23) +WGPUVertexFormat_Snorm16x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Snorm16x4', 24) +WGPUVertexFormat_Float16 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float16', 25) +WGPUVertexFormat_Float16x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float16x2', 26) +WGPUVertexFormat_Float16x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float16x4', 27) +WGPUVertexFormat_Float32 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float32', 28) +WGPUVertexFormat_Float32x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float32x2', 29) +WGPUVertexFormat_Float32x3 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float32x3', 30) +WGPUVertexFormat_Float32x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Float32x4', 31) +WGPUVertexFormat_Uint32 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint32', 32) +WGPUVertexFormat_Uint32x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint32x2', 33) +WGPUVertexFormat_Uint32x3 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint32x3', 34) +WGPUVertexFormat_Uint32x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Uint32x4', 35) +WGPUVertexFormat_Sint32 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint32', 36) +WGPUVertexFormat_Sint32x2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint32x2', 37) +WGPUVertexFormat_Sint32x3 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint32x3', 38) +WGPUVertexFormat_Sint32x4 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Sint32x4', 39) +WGPUVertexFormat_Unorm10_10_10_2 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm10_10_10_2', 40) +WGPUVertexFormat_Unorm8x4BGRA = enum_WGPUVertexFormat.define('WGPUVertexFormat_Unorm8x4BGRA', 41) +WGPUVertexFormat_Force32 = enum_WGPUVertexFormat.define('WGPUVertexFormat_Force32', 2147483647) + +WGPUVertexFormat = enum_WGPUVertexFormat +struct_WGPUVertexAttribute._fields_ = [ + ('format', WGPUVertexFormat), + ('offset', uint64_t), + ('shaderLocation', uint32_t), +] +class struct_WGPUYCbCrVkDescriptor(Struct): pass +enum_WGPUFilterMode = CEnum(ctypes.c_uint32) +WGPUFilterMode_Undefined = enum_WGPUFilterMode.define('WGPUFilterMode_Undefined', 0) +WGPUFilterMode_Nearest = enum_WGPUFilterMode.define('WGPUFilterMode_Nearest', 1) +WGPUFilterMode_Linear = enum_WGPUFilterMode.define('WGPUFilterMode_Linear', 2) +WGPUFilterMode_Force32 = enum_WGPUFilterMode.define('WGPUFilterMode_Force32', 2147483647) + +WGPUFilterMode = enum_WGPUFilterMode +struct_WGPUYCbCrVkDescriptor._fields_ = [ + ('chain', WGPUChainedStruct), + ('vkFormat', uint32_t), + ('vkYCbCrModel', uint32_t), + ('vkYCbCrRange', uint32_t), + ('vkComponentSwizzleRed', uint32_t), + ('vkComponentSwizzleGreen', uint32_t), + ('vkComponentSwizzleBlue', uint32_t), + ('vkComponentSwizzleAlpha', uint32_t), + ('vkXChromaOffset', uint32_t), + ('vkYChromaOffset', uint32_t), + ('vkChromaFilter', WGPUFilterMode), + ('forceExplicitReconstruction', WGPUBool), + ('externalFormat', uint64_t), +] +class struct_WGPUAHardwareBufferProperties(Struct): pass +WGPUYCbCrVkDescriptor = struct_WGPUYCbCrVkDescriptor +struct_WGPUAHardwareBufferProperties._fields_ = [ + ('yCbCrInfo', WGPUYCbCrVkDescriptor), +] +class struct_WGPUAdapterInfo(Struct): pass +enum_WGPUAdapterType = CEnum(ctypes.c_uint32) +WGPUAdapterType_DiscreteGPU = enum_WGPUAdapterType.define('WGPUAdapterType_DiscreteGPU', 1) +WGPUAdapterType_IntegratedGPU = enum_WGPUAdapterType.define('WGPUAdapterType_IntegratedGPU', 2) +WGPUAdapterType_CPU = enum_WGPUAdapterType.define('WGPUAdapterType_CPU', 3) +WGPUAdapterType_Unknown = enum_WGPUAdapterType.define('WGPUAdapterType_Unknown', 4) +WGPUAdapterType_Force32 = enum_WGPUAdapterType.define('WGPUAdapterType_Force32', 2147483647) + +WGPUAdapterType = enum_WGPUAdapterType +struct_WGPUAdapterInfo._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('vendor', WGPUStringView), + ('architecture', WGPUStringView), + ('device', WGPUStringView), + ('description', WGPUStringView), + ('backendType', WGPUBackendType), + ('adapterType', WGPUAdapterType), + ('vendorID', uint32_t), + ('deviceID', uint32_t), + ('compatibilityMode', WGPUBool), +] +class struct_WGPUAdapterPropertiesMemoryHeaps(Struct): pass +WGPUMemoryHeapInfo = struct_WGPUMemoryHeapInfo +struct_WGPUAdapterPropertiesMemoryHeaps._fields_ = [ + ('chain', WGPUChainedStructOut), + ('heapCount', size_t), + ('heapInfo', ctypes.POINTER(WGPUMemoryHeapInfo)), +] +class struct_WGPUBindGroupDescriptor(Struct): pass +WGPUBindGroupEntry = struct_WGPUBindGroupEntry +struct_WGPUBindGroupDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('layout', WGPUBindGroupLayout), + ('entryCount', size_t), + ('entries', ctypes.POINTER(WGPUBindGroupEntry)), +] +class struct_WGPUBindGroupLayoutEntry(Struct): pass +WGPUShaderStage = ctypes.c_uint64 +WGPUBufferBindingLayout = struct_WGPUBufferBindingLayout +WGPUSamplerBindingLayout = struct_WGPUSamplerBindingLayout +WGPUTextureBindingLayout = struct_WGPUTextureBindingLayout +WGPUStorageTextureBindingLayout = struct_WGPUStorageTextureBindingLayout +struct_WGPUBindGroupLayoutEntry._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('binding', uint32_t), + ('visibility', WGPUShaderStage), + ('buffer', WGPUBufferBindingLayout), + ('sampler', WGPUSamplerBindingLayout), + ('texture', WGPUTextureBindingLayout), + ('storageTexture', WGPUStorageTextureBindingLayout), +] +class struct_WGPUBlendState(Struct): pass +WGPUBlendComponent = struct_WGPUBlendComponent +struct_WGPUBlendState._fields_ = [ + ('color', WGPUBlendComponent), + ('alpha', WGPUBlendComponent), +] +class struct_WGPUBufferDescriptor(Struct): pass +struct_WGPUBufferDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('usage', WGPUBufferUsage), + ('size', uint64_t), + ('mappedAtCreation', WGPUBool), +] +class struct_WGPUCommandBufferDescriptor(Struct): pass +struct_WGPUCommandBufferDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +class struct_WGPUCommandEncoderDescriptor(Struct): pass +struct_WGPUCommandEncoderDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +class struct_WGPUComputePassDescriptor(Struct): pass +WGPUComputePassTimestampWrites = struct_WGPUComputePassTimestampWrites struct_WGPUComputePassDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('timestampWrites', ctypes.POINTER(struct_WGPUComputePassTimestampWrites)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('timestampWrites', ctypes.POINTER(WGPUComputePassTimestampWrites)), ] - -WGPUComputePassDescriptor = struct_WGPUComputePassDescriptor -class struct_WGPUConstantEntry(Structure): - pass - -struct_WGPUConstantEntry._pack_ = 1 # source:False +class struct_WGPUConstantEntry(Struct): pass struct_WGPUConstantEntry._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('key', WGPUStringView), - ('value', ctypes.c_double), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('key', WGPUStringView), + ('value', ctypes.c_double), ] - -WGPUConstantEntry = struct_WGPUConstantEntry -class struct_WGPUDawnCacheDeviceDescriptor(Structure): - pass - -struct_WGPUDawnCacheDeviceDescriptor._pack_ = 1 # source:False +class struct_WGPUDawnCacheDeviceDescriptor(Struct): pass +WGPUDawnLoadCacheDataFunction = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_void_p, ctypes.c_uint64, ctypes.c_void_p, ctypes.c_uint64, ctypes.c_void_p) +WGPUDawnStoreCacheDataFunction = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_uint64, ctypes.c_void_p, ctypes.c_uint64, ctypes.c_void_p) struct_WGPUDawnCacheDeviceDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('isolationKey', WGPUStringView), - ('loadDataFunction', ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None))), - ('storeDataFunction', ctypes.CFUNCTYPE(None, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(None))), - ('functionUserdata', ctypes.POINTER(None)), + ('chain', WGPUChainedStruct), + ('isolationKey', WGPUStringView), + ('loadDataFunction', WGPUDawnLoadCacheDataFunction), + ('storeDataFunction', WGPUDawnStoreCacheDataFunction), + ('functionUserdata', ctypes.c_void_p), ] +class struct_WGPUDepthStencilState(Struct): pass +enum_WGPUOptionalBool = CEnum(ctypes.c_uint32) +WGPUOptionalBool_False = enum_WGPUOptionalBool.define('WGPUOptionalBool_False', 0) +WGPUOptionalBool_True = enum_WGPUOptionalBool.define('WGPUOptionalBool_True', 1) +WGPUOptionalBool_Undefined = enum_WGPUOptionalBool.define('WGPUOptionalBool_Undefined', 2) +WGPUOptionalBool_Force32 = enum_WGPUOptionalBool.define('WGPUOptionalBool_Force32', 2147483647) -WGPUDawnCacheDeviceDescriptor = struct_WGPUDawnCacheDeviceDescriptor -class struct_WGPUDepthStencilState(Structure): - pass - -struct_WGPUDepthStencilState._pack_ = 1 # source:False +WGPUOptionalBool = enum_WGPUOptionalBool +WGPUStencilFaceState = struct_WGPUStencilFaceState struct_WGPUDepthStencilState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('format', WGPUTextureFormat), - ('depthWriteEnabled', WGPUOptionalBool), - ('depthCompare', WGPUCompareFunction), - ('stencilFront', WGPUStencilFaceState), - ('stencilBack', WGPUStencilFaceState), - ('stencilReadMask', ctypes.c_uint32), - ('stencilWriteMask', ctypes.c_uint32), - ('depthBias', ctypes.c_int32), - ('depthBiasSlopeScale', ctypes.c_float), - ('depthBiasClamp', ctypes.c_float), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('format', WGPUTextureFormat), + ('depthWriteEnabled', WGPUOptionalBool), + ('depthCompare', WGPUCompareFunction), + ('stencilFront', WGPUStencilFaceState), + ('stencilBack', WGPUStencilFaceState), + ('stencilReadMask', uint32_t), + ('stencilWriteMask', uint32_t), + ('depthBias', int32_t), + ('depthBiasSlopeScale', ctypes.c_float), + ('depthBiasClamp', ctypes.c_float), ] - -WGPUDepthStencilState = struct_WGPUDepthStencilState -class struct_WGPUDrmFormatCapabilities(Structure): - pass - -struct_WGPUDrmFormatCapabilities._pack_ = 1 # source:False +class struct_WGPUDrmFormatCapabilities(Struct): pass +WGPUDrmFormatProperties = struct_WGPUDrmFormatProperties struct_WGPUDrmFormatCapabilities._fields_ = [ - ('chain', WGPUChainedStructOut), - ('propertiesCount', ctypes.c_uint64), - ('properties', ctypes.POINTER(struct_WGPUDrmFormatProperties)), + ('chain', WGPUChainedStructOut), + ('propertiesCount', size_t), + ('properties', ctypes.POINTER(WGPUDrmFormatProperties)), ] +class struct_WGPUExternalTextureDescriptor(Struct): pass +WGPUOrigin2D = struct_WGPUOrigin2D +WGPUExtent2D = struct_WGPUExtent2D +enum_WGPUExternalTextureRotation = CEnum(ctypes.c_uint32) +WGPUExternalTextureRotation_Rotate0Degrees = enum_WGPUExternalTextureRotation.define('WGPUExternalTextureRotation_Rotate0Degrees', 1) +WGPUExternalTextureRotation_Rotate90Degrees = enum_WGPUExternalTextureRotation.define('WGPUExternalTextureRotation_Rotate90Degrees', 2) +WGPUExternalTextureRotation_Rotate180Degrees = enum_WGPUExternalTextureRotation.define('WGPUExternalTextureRotation_Rotate180Degrees', 3) +WGPUExternalTextureRotation_Rotate270Degrees = enum_WGPUExternalTextureRotation.define('WGPUExternalTextureRotation_Rotate270Degrees', 4) +WGPUExternalTextureRotation_Force32 = enum_WGPUExternalTextureRotation.define('WGPUExternalTextureRotation_Force32', 2147483647) -WGPUDrmFormatCapabilities = struct_WGPUDrmFormatCapabilities -class struct_WGPUExternalTextureDescriptor(Structure): - pass - -struct_WGPUExternalTextureDescriptor._pack_ = 1 # source:False +WGPUExternalTextureRotation = enum_WGPUExternalTextureRotation struct_WGPUExternalTextureDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('plane0', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('plane1', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('cropOrigin', WGPUOrigin2D), - ('cropSize', WGPUExtent2D), - ('apparentSize', WGPUExtent2D), - ('doYuvToRgbConversionOnly', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('yuvToRgbConversionMatrix', ctypes.POINTER(ctypes.c_float)), - ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), - ('gamutConversionMatrix', ctypes.POINTER(ctypes.c_float)), - ('mirrored', ctypes.c_uint32), - ('rotation', WGPUExternalTextureRotation), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('plane0', WGPUTextureView), + ('plane1', WGPUTextureView), + ('cropOrigin', WGPUOrigin2D), + ('cropSize', WGPUExtent2D), + ('apparentSize', WGPUExtent2D), + ('doYuvToRgbConversionOnly', WGPUBool), + ('yuvToRgbConversionMatrix', ctypes.POINTER(ctypes.c_float)), + ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('gamutConversionMatrix', ctypes.POINTER(ctypes.c_float)), + ('mirrored', WGPUBool), + ('rotation', WGPUExternalTextureRotation), ] - -WGPUExternalTextureDescriptor = struct_WGPUExternalTextureDescriptor -class struct_WGPUFutureWaitInfo(Structure): - pass - -struct_WGPUFutureWaitInfo._pack_ = 1 # source:False +class struct_WGPUFutureWaitInfo(Struct): pass +WGPUFuture = struct_WGPUFuture struct_WGPUFutureWaitInfo._fields_ = [ - ('future', WGPUFuture), - ('completed', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('future', WGPUFuture), + ('completed', WGPUBool), ] - -WGPUFutureWaitInfo = struct_WGPUFutureWaitInfo -class struct_WGPUImageCopyBuffer(Structure): - pass - -struct_WGPUImageCopyBuffer._pack_ = 1 # source:False +class struct_WGPUImageCopyBuffer(Struct): pass +WGPUTextureDataLayout = struct_WGPUTextureDataLayout struct_WGPUImageCopyBuffer._fields_ = [ - ('layout', WGPUTextureDataLayout), - ('buffer', ctypes.POINTER(struct_WGPUBufferImpl)), + ('layout', WGPUTextureDataLayout), + ('buffer', WGPUBuffer), ] - -WGPUImageCopyBuffer = struct_WGPUImageCopyBuffer -class struct_WGPUImageCopyExternalTexture(Structure): - pass - -struct_WGPUImageCopyExternalTexture._pack_ = 1 # source:False +class struct_WGPUImageCopyExternalTexture(Struct): pass +WGPUOrigin3D = struct_WGPUOrigin3D struct_WGPUImageCopyExternalTexture._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('externalTexture', ctypes.POINTER(struct_WGPUExternalTextureImpl)), - ('origin', WGPUOrigin3D), - ('naturalSize', WGPUExtent2D), - ('PADDING_0', ctypes.c_ubyte * 4), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('externalTexture', WGPUExternalTexture), + ('origin', WGPUOrigin3D), + ('naturalSize', WGPUExtent2D), ] +class struct_WGPUImageCopyTexture(Struct): pass +enum_WGPUTextureAspect = CEnum(ctypes.c_uint32) +WGPUTextureAspect_Undefined = enum_WGPUTextureAspect.define('WGPUTextureAspect_Undefined', 0) +WGPUTextureAspect_All = enum_WGPUTextureAspect.define('WGPUTextureAspect_All', 1) +WGPUTextureAspect_StencilOnly = enum_WGPUTextureAspect.define('WGPUTextureAspect_StencilOnly', 2) +WGPUTextureAspect_DepthOnly = enum_WGPUTextureAspect.define('WGPUTextureAspect_DepthOnly', 3) +WGPUTextureAspect_Plane0Only = enum_WGPUTextureAspect.define('WGPUTextureAspect_Plane0Only', 327680) +WGPUTextureAspect_Plane1Only = enum_WGPUTextureAspect.define('WGPUTextureAspect_Plane1Only', 327681) +WGPUTextureAspect_Plane2Only = enum_WGPUTextureAspect.define('WGPUTextureAspect_Plane2Only', 327682) +WGPUTextureAspect_Force32 = enum_WGPUTextureAspect.define('WGPUTextureAspect_Force32', 2147483647) -WGPUImageCopyExternalTexture = struct_WGPUImageCopyExternalTexture -class struct_WGPUImageCopyTexture(Structure): - pass - -struct_WGPUImageCopyTexture._pack_ = 1 # source:False +WGPUTextureAspect = enum_WGPUTextureAspect struct_WGPUImageCopyTexture._fields_ = [ - ('texture', ctypes.POINTER(struct_WGPUTextureImpl)), - ('mipLevel', ctypes.c_uint32), - ('origin', WGPUOrigin3D), - ('aspect', WGPUTextureAspect), - ('PADDING_0', ctypes.c_ubyte * 4), + ('texture', WGPUTexture), + ('mipLevel', uint32_t), + ('origin', WGPUOrigin3D), + ('aspect', WGPUTextureAspect), ] - -WGPUImageCopyTexture = struct_WGPUImageCopyTexture -class struct_WGPUInstanceDescriptor(Structure): - pass - -struct_WGPUInstanceDescriptor._pack_ = 1 # source:False +class struct_WGPUInstanceDescriptor(Struct): pass +WGPUInstanceFeatures = struct_WGPUInstanceFeatures struct_WGPUInstanceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('features', WGPUInstanceFeatures), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('features', WGPUInstanceFeatures), ] - -WGPUInstanceDescriptor = struct_WGPUInstanceDescriptor -class struct_WGPUPipelineLayoutDescriptor(Structure): - pass - -struct_WGPUPipelineLayoutDescriptor._pack_ = 1 # source:False +class struct_WGPUPipelineLayoutDescriptor(Struct): pass struct_WGPUPipelineLayoutDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('bindGroupLayoutCount', ctypes.c_uint64), - ('bindGroupLayouts', ctypes.POINTER(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl))), - ('immediateDataRangeByteSize', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('bindGroupLayoutCount', size_t), + ('bindGroupLayouts', ctypes.POINTER(WGPUBindGroupLayout)), + ('immediateDataRangeByteSize', uint32_t), ] - -WGPUPipelineLayoutDescriptor = struct_WGPUPipelineLayoutDescriptor -class struct_WGPUPipelineLayoutPixelLocalStorage(Structure): - pass - -struct_WGPUPipelineLayoutPixelLocalStorage._pack_ = 1 # source:False +class struct_WGPUPipelineLayoutPixelLocalStorage(Struct): pass +WGPUPipelineLayoutStorageAttachment = struct_WGPUPipelineLayoutStorageAttachment struct_WGPUPipelineLayoutPixelLocalStorage._fields_ = [ - ('chain', WGPUChainedStruct), - ('totalPixelLocalStorageSize', ctypes.c_uint64), - ('storageAttachmentCount', ctypes.c_uint64), - ('storageAttachments', ctypes.POINTER(struct_WGPUPipelineLayoutStorageAttachment)), + ('chain', WGPUChainedStruct), + ('totalPixelLocalStorageSize', uint64_t), + ('storageAttachmentCount', size_t), + ('storageAttachments', ctypes.POINTER(WGPUPipelineLayoutStorageAttachment)), ] +class struct_WGPUQuerySetDescriptor(Struct): pass +enum_WGPUQueryType = CEnum(ctypes.c_uint32) +WGPUQueryType_Occlusion = enum_WGPUQueryType.define('WGPUQueryType_Occlusion', 1) +WGPUQueryType_Timestamp = enum_WGPUQueryType.define('WGPUQueryType_Timestamp', 2) +WGPUQueryType_Force32 = enum_WGPUQueryType.define('WGPUQueryType_Force32', 2147483647) -WGPUPipelineLayoutPixelLocalStorage = struct_WGPUPipelineLayoutPixelLocalStorage -class struct_WGPUQuerySetDescriptor(Structure): - pass - -struct_WGPUQuerySetDescriptor._pack_ = 1 # source:False +WGPUQueryType = enum_WGPUQueryType struct_WGPUQuerySetDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('type', WGPUQueryType), - ('count', ctypes.c_uint32), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('type', WGPUQueryType), + ('count', uint32_t), ] - -WGPUQuerySetDescriptor = struct_WGPUQuerySetDescriptor -class struct_WGPUQueueDescriptor(Structure): - pass - -struct_WGPUQueueDescriptor._pack_ = 1 # source:False +class struct_WGPUQueueDescriptor(Struct): pass struct_WGPUQueueDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] - -WGPUQueueDescriptor = struct_WGPUQueueDescriptor -class struct_WGPURenderBundleDescriptor(Structure): - pass - -struct_WGPURenderBundleDescriptor._pack_ = 1 # source:False +class struct_WGPURenderBundleDescriptor(Struct): pass struct_WGPURenderBundleDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] - -WGPURenderBundleDescriptor = struct_WGPURenderBundleDescriptor -class struct_WGPURenderBundleEncoderDescriptor(Structure): - pass - -struct_WGPURenderBundleEncoderDescriptor._pack_ = 1 # source:False +class struct_WGPURenderBundleEncoderDescriptor(Struct): pass struct_WGPURenderBundleEncoderDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('colorFormatCount', ctypes.c_uint64), - ('colorFormats', ctypes.POINTER(WGPUTextureFormat)), - ('depthStencilFormat', WGPUTextureFormat), - ('sampleCount', ctypes.c_uint32), - ('depthReadOnly', ctypes.c_uint32), - ('stencilReadOnly', ctypes.c_uint32), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('colorFormatCount', size_t), + ('colorFormats', ctypes.POINTER(WGPUTextureFormat)), + ('depthStencilFormat', WGPUTextureFormat), + ('sampleCount', uint32_t), + ('depthReadOnly', WGPUBool), + ('stencilReadOnly', WGPUBool), ] - -WGPURenderBundleEncoderDescriptor = struct_WGPURenderBundleEncoderDescriptor -class struct_WGPURenderPassColorAttachment(Structure): - pass - -struct_WGPURenderPassColorAttachment._pack_ = 1 # source:False +class struct_WGPURenderPassColorAttachment(Struct): pass +WGPUColor = struct_WGPUColor struct_WGPURenderPassColorAttachment._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('view', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('depthSlice', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('resolveTarget', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('loadOp', WGPULoadOp), - ('storeOp', WGPUStoreOp), - ('clearValue', WGPUColor), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('view', WGPUTextureView), + ('depthSlice', uint32_t), + ('resolveTarget', WGPUTextureView), + ('loadOp', WGPULoadOp), + ('storeOp', WGPUStoreOp), + ('clearValue', WGPUColor), ] - -WGPURenderPassColorAttachment = struct_WGPURenderPassColorAttachment -class struct_WGPURenderPassStorageAttachment(Structure): - pass - -struct_WGPURenderPassStorageAttachment._pack_ = 1 # source:False +class struct_WGPURenderPassStorageAttachment(Struct): pass struct_WGPURenderPassStorageAttachment._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('offset', ctypes.c_uint64), - ('storage', ctypes.POINTER(struct_WGPUTextureViewImpl)), - ('loadOp', WGPULoadOp), - ('storeOp', WGPUStoreOp), - ('clearValue', WGPUColor), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('offset', uint64_t), + ('storage', WGPUTextureView), + ('loadOp', WGPULoadOp), + ('storeOp', WGPUStoreOp), + ('clearValue', WGPUColor), ] - -WGPURenderPassStorageAttachment = struct_WGPURenderPassStorageAttachment -class struct_WGPURequiredLimits(Structure): - pass - -struct_WGPURequiredLimits._pack_ = 1 # source:False +class struct_WGPURequiredLimits(Struct): pass +WGPULimits = struct_WGPULimits struct_WGPURequiredLimits._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('limits', WGPULimits), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('limits', WGPULimits), ] +class struct_WGPUSamplerDescriptor(Struct): pass +enum_WGPUAddressMode = CEnum(ctypes.c_uint32) +WGPUAddressMode_Undefined = enum_WGPUAddressMode.define('WGPUAddressMode_Undefined', 0) +WGPUAddressMode_ClampToEdge = enum_WGPUAddressMode.define('WGPUAddressMode_ClampToEdge', 1) +WGPUAddressMode_Repeat = enum_WGPUAddressMode.define('WGPUAddressMode_Repeat', 2) +WGPUAddressMode_MirrorRepeat = enum_WGPUAddressMode.define('WGPUAddressMode_MirrorRepeat', 3) +WGPUAddressMode_Force32 = enum_WGPUAddressMode.define('WGPUAddressMode_Force32', 2147483647) -WGPURequiredLimits = struct_WGPURequiredLimits -class struct_WGPUSamplerDescriptor(Structure): - pass +WGPUAddressMode = enum_WGPUAddressMode +enum_WGPUMipmapFilterMode = CEnum(ctypes.c_uint32) +WGPUMipmapFilterMode_Undefined = enum_WGPUMipmapFilterMode.define('WGPUMipmapFilterMode_Undefined', 0) +WGPUMipmapFilterMode_Nearest = enum_WGPUMipmapFilterMode.define('WGPUMipmapFilterMode_Nearest', 1) +WGPUMipmapFilterMode_Linear = enum_WGPUMipmapFilterMode.define('WGPUMipmapFilterMode_Linear', 2) +WGPUMipmapFilterMode_Force32 = enum_WGPUMipmapFilterMode.define('WGPUMipmapFilterMode_Force32', 2147483647) -struct_WGPUSamplerDescriptor._pack_ = 1 # source:False +WGPUMipmapFilterMode = enum_WGPUMipmapFilterMode +uint16_t = ctypes.c_uint16 struct_WGPUSamplerDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('addressModeU', WGPUAddressMode), - ('addressModeV', WGPUAddressMode), - ('addressModeW', WGPUAddressMode), - ('magFilter', WGPUFilterMode), - ('minFilter', WGPUFilterMode), - ('mipmapFilter', WGPUMipmapFilterMode), - ('lodMinClamp', ctypes.c_float), - ('lodMaxClamp', ctypes.c_float), - ('compare', WGPUCompareFunction), - ('maxAnisotropy', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('addressModeU', WGPUAddressMode), + ('addressModeV', WGPUAddressMode), + ('addressModeW', WGPUAddressMode), + ('magFilter', WGPUFilterMode), + ('minFilter', WGPUFilterMode), + ('mipmapFilter', WGPUMipmapFilterMode), + ('lodMinClamp', ctypes.c_float), + ('lodMaxClamp', ctypes.c_float), + ('compare', WGPUCompareFunction), + ('maxAnisotropy', uint16_t), ] - -WGPUSamplerDescriptor = struct_WGPUSamplerDescriptor -class struct_WGPUShaderModuleDescriptor(Structure): - pass - -struct_WGPUShaderModuleDescriptor._pack_ = 1 # source:False +class struct_WGPUShaderModuleDescriptor(Struct): pass struct_WGPUShaderModuleDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] - -WGPUShaderModuleDescriptor = struct_WGPUShaderModuleDescriptor -class struct_WGPUShaderSourceWGSL(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStruct), - ('code', WGPUStringView), - ] - -WGPUShaderSourceWGSL = struct_WGPUShaderSourceWGSL -class struct_WGPUSharedBufferMemoryDescriptor(Structure): - pass - -struct_WGPUSharedBufferMemoryDescriptor._pack_ = 1 # source:False +class struct_WGPUShaderSourceWGSL(Struct): pass +struct_WGPUShaderSourceWGSL._fields_ = [ + ('chain', WGPUChainedStruct), + ('code', WGPUStringView), +] +class struct_WGPUSharedBufferMemoryDescriptor(Struct): pass struct_WGPUSharedBufferMemoryDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] - -WGPUSharedBufferMemoryDescriptor = struct_WGPUSharedBufferMemoryDescriptor -class struct_WGPUSharedFenceDescriptor(Structure): - pass - -struct_WGPUSharedFenceDescriptor._pack_ = 1 # source:False +class struct_WGPUSharedFenceDescriptor(Struct): pass struct_WGPUSharedFenceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] - -WGPUSharedFenceDescriptor = struct_WGPUSharedFenceDescriptor -class struct_WGPUSharedTextureMemoryAHardwareBufferProperties(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStructOut), - ('yCbCrInfo', WGPUYCbCrVkDescriptor), - ] - -WGPUSharedTextureMemoryAHardwareBufferProperties = struct_WGPUSharedTextureMemoryAHardwareBufferProperties -class struct_WGPUSharedTextureMemoryDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryDescriptor._pack_ = 1 # source:False +class struct_WGPUSharedTextureMemoryAHardwareBufferProperties(Struct): pass +struct_WGPUSharedTextureMemoryAHardwareBufferProperties._fields_ = [ + ('chain', WGPUChainedStructOut), + ('yCbCrInfo', WGPUYCbCrVkDescriptor), +] +class struct_WGPUSharedTextureMemoryDescriptor(Struct): pass struct_WGPUSharedTextureMemoryDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] - -WGPUSharedTextureMemoryDescriptor = struct_WGPUSharedTextureMemoryDescriptor -class struct_WGPUSharedTextureMemoryDmaBufDescriptor(Structure): - pass - -struct_WGPUSharedTextureMemoryDmaBufDescriptor._pack_ = 1 # source:False +class struct_WGPUSharedTextureMemoryDmaBufDescriptor(Struct): pass +WGPUExtent3D = struct_WGPUExtent3D +WGPUSharedTextureMemoryDmaBufPlane = struct_WGPUSharedTextureMemoryDmaBufPlane struct_WGPUSharedTextureMemoryDmaBufDescriptor._fields_ = [ - ('chain', WGPUChainedStruct), - ('size', WGPUExtent3D), - ('drmFormat', ctypes.c_uint32), - ('drmModifier', ctypes.c_uint64), - ('planeCount', ctypes.c_uint64), - ('planes', ctypes.POINTER(struct_WGPUSharedTextureMemoryDmaBufPlane)), + ('chain', WGPUChainedStruct), + ('size', WGPUExtent3D), + ('drmFormat', uint32_t), + ('drmModifier', uint64_t), + ('planeCount', size_t), + ('planes', ctypes.POINTER(WGPUSharedTextureMemoryDmaBufPlane)), ] - -WGPUSharedTextureMemoryDmaBufDescriptor = struct_WGPUSharedTextureMemoryDmaBufDescriptor -class struct_WGPUSharedTextureMemoryProperties(Structure): - pass - -struct_WGPUSharedTextureMemoryProperties._pack_ = 1 # source:False +class struct_WGPUSharedTextureMemoryProperties(Struct): pass struct_WGPUSharedTextureMemoryProperties._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('usage', ctypes.c_uint64), - ('size', WGPUExtent3D), - ('format', WGPUTextureFormat), + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('usage', WGPUTextureUsage), + ('size', WGPUExtent3D), + ('format', WGPUTextureFormat), ] - -WGPUSharedTextureMemoryProperties = struct_WGPUSharedTextureMemoryProperties -class struct_WGPUSupportedLimits(Structure): - pass - -struct_WGPUSupportedLimits._pack_ = 1 # source:False +class struct_WGPUSupportedLimits(Struct): pass struct_WGPUSupportedLimits._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStructOut)), - ('limits', WGPULimits), + ('nextInChain', ctypes.POINTER(WGPUChainedStructOut)), + ('limits', WGPULimits), ] - -WGPUSupportedLimits = struct_WGPUSupportedLimits -class struct_WGPUSurfaceDescriptor(Structure): - pass - -struct_WGPUSurfaceDescriptor._pack_ = 1 # source:False +class struct_WGPUSurfaceDescriptor(Struct): pass struct_WGPUSurfaceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), ] +class struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten(Struct): pass +struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten._fields_ = [ + ('chain', WGPUChainedStruct), + ('selector', WGPUStringView), +] +class struct_WGPUTextureDescriptor(Struct): pass +enum_WGPUTextureDimension = CEnum(ctypes.c_uint32) +WGPUTextureDimension_Undefined = enum_WGPUTextureDimension.define('WGPUTextureDimension_Undefined', 0) +WGPUTextureDimension_1D = enum_WGPUTextureDimension.define('WGPUTextureDimension_1D', 1) +WGPUTextureDimension_2D = enum_WGPUTextureDimension.define('WGPUTextureDimension_2D', 2) +WGPUTextureDimension_3D = enum_WGPUTextureDimension.define('WGPUTextureDimension_3D', 3) +WGPUTextureDimension_Force32 = enum_WGPUTextureDimension.define('WGPUTextureDimension_Force32', 2147483647) -WGPUSurfaceDescriptor = struct_WGPUSurfaceDescriptor -class struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('chain', WGPUChainedStruct), - ('selector', WGPUStringView), - ] - -WGPUSurfaceSourceCanvasHTMLSelector_Emscripten = struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten -class struct_WGPUTextureDescriptor(Structure): - pass - -struct_WGPUTextureDescriptor._pack_ = 1 # source:False +WGPUTextureDimension = enum_WGPUTextureDimension struct_WGPUTextureDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('usage', ctypes.c_uint64), - ('dimension', WGPUTextureDimension), - ('size', WGPUExtent3D), - ('format', WGPUTextureFormat), - ('mipLevelCount', ctypes.c_uint32), - ('sampleCount', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('viewFormatCount', ctypes.c_uint64), - ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('usage', WGPUTextureUsage), + ('dimension', WGPUTextureDimension), + ('size', WGPUExtent3D), + ('format', WGPUTextureFormat), + ('mipLevelCount', uint32_t), + ('sampleCount', uint32_t), + ('viewFormatCount', size_t), + ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), ] - -WGPUTextureDescriptor = struct_WGPUTextureDescriptor -class struct_WGPUTextureViewDescriptor(Structure): - pass - -struct_WGPUTextureViewDescriptor._pack_ = 1 # source:False +class struct_WGPUTextureViewDescriptor(Struct): pass struct_WGPUTextureViewDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('format', WGPUTextureFormat), - ('dimension', WGPUTextureViewDimension), - ('baseMipLevel', ctypes.c_uint32), - ('mipLevelCount', ctypes.c_uint32), - ('baseArrayLayer', ctypes.c_uint32), - ('arrayLayerCount', ctypes.c_uint32), - ('aspect', WGPUTextureAspect), - ('PADDING_0', ctypes.c_ubyte * 4), - ('usage', ctypes.c_uint64), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('format', WGPUTextureFormat), + ('dimension', WGPUTextureViewDimension), + ('baseMipLevel', uint32_t), + ('mipLevelCount', uint32_t), + ('baseArrayLayer', uint32_t), + ('arrayLayerCount', uint32_t), + ('aspect', WGPUTextureAspect), + ('usage', WGPUTextureUsage), ] +class struct_WGPUVertexBufferLayout(Struct): pass +enum_WGPUVertexStepMode = CEnum(ctypes.c_uint32) +WGPUVertexStepMode_Undefined = enum_WGPUVertexStepMode.define('WGPUVertexStepMode_Undefined', 0) +WGPUVertexStepMode_Vertex = enum_WGPUVertexStepMode.define('WGPUVertexStepMode_Vertex', 1) +WGPUVertexStepMode_Instance = enum_WGPUVertexStepMode.define('WGPUVertexStepMode_Instance', 2) +WGPUVertexStepMode_Force32 = enum_WGPUVertexStepMode.define('WGPUVertexStepMode_Force32', 2147483647) -WGPUTextureViewDescriptor = struct_WGPUTextureViewDescriptor -class struct_WGPUVertexBufferLayout(Structure): - pass - -struct_WGPUVertexBufferLayout._pack_ = 1 # source:False +WGPUVertexStepMode = enum_WGPUVertexStepMode +WGPUVertexAttribute = struct_WGPUVertexAttribute struct_WGPUVertexBufferLayout._fields_ = [ - ('arrayStride', ctypes.c_uint64), - ('stepMode', WGPUVertexStepMode), - ('PADDING_0', ctypes.c_ubyte * 4), - ('attributeCount', ctypes.c_uint64), - ('attributes', ctypes.POINTER(struct_WGPUVertexAttribute)), + ('arrayStride', uint64_t), + ('stepMode', WGPUVertexStepMode), + ('attributeCount', size_t), + ('attributes', ctypes.POINTER(WGPUVertexAttribute)), ] - -WGPUVertexBufferLayout = struct_WGPUVertexBufferLayout -class struct_WGPUBindGroupLayoutDescriptor(Structure): - pass - -struct_WGPUBindGroupLayoutDescriptor._pack_ = 1 # source:False +class struct_WGPUBindGroupLayoutDescriptor(Struct): pass +WGPUBindGroupLayoutEntry = struct_WGPUBindGroupLayoutEntry struct_WGPUBindGroupLayoutDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('entryCount', ctypes.c_uint64), - ('entries', ctypes.POINTER(struct_WGPUBindGroupLayoutEntry)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('entryCount', size_t), + ('entries', ctypes.POINTER(WGPUBindGroupLayoutEntry)), ] - -WGPUBindGroupLayoutDescriptor = struct_WGPUBindGroupLayoutDescriptor -class struct_WGPUColorTargetState(Structure): - pass - -struct_WGPUColorTargetState._pack_ = 1 # source:False +class struct_WGPUColorTargetState(Struct): pass +WGPUBlendState = struct_WGPUBlendState +WGPUColorWriteMask = ctypes.c_uint64 struct_WGPUColorTargetState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('format', WGPUTextureFormat), - ('PADDING_0', ctypes.c_ubyte * 4), - ('blend', ctypes.POINTER(struct_WGPUBlendState)), - ('writeMask', ctypes.c_uint64), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('format', WGPUTextureFormat), + ('blend', ctypes.POINTER(WGPUBlendState)), + ('writeMask', WGPUColorWriteMask), ] - -WGPUColorTargetState = struct_WGPUColorTargetState -struct_WGPUCompilationInfo._pack_ = 1 # source:False +class struct_WGPUCompilationInfo(Struct): pass struct_WGPUCompilationInfo._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('messageCount', ctypes.c_uint64), - ('messages', ctypes.POINTER(struct_WGPUCompilationMessage)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('messageCount', size_t), + ('messages', ctypes.POINTER(WGPUCompilationMessage)), ] - -WGPUCompilationInfo = struct_WGPUCompilationInfo -class struct_WGPUComputeState(Structure): - pass - -struct_WGPUComputeState._pack_ = 1 # source:False +class struct_WGPUComputeState(Struct): pass +WGPUConstantEntry = struct_WGPUConstantEntry struct_WGPUComputeState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('module', ctypes.POINTER(struct_WGPUShaderModuleImpl)), - ('entryPoint', WGPUStringView), - ('constantCount', ctypes.c_uint64), - ('constants', ctypes.POINTER(struct_WGPUConstantEntry)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('module', WGPUShaderModule), + ('entryPoint', WGPUStringView), + ('constantCount', size_t), + ('constants', ctypes.POINTER(WGPUConstantEntry)), +] +class struct_WGPUDeviceDescriptor(Struct): pass +WGPURequiredLimits = struct_WGPURequiredLimits +WGPUQueueDescriptor = struct_WGPUQueueDescriptor +class struct_WGPUDeviceLostCallbackInfo2(Struct): pass +WGPUDeviceLostCallbackInfo2 = struct_WGPUDeviceLostCallbackInfo2 +WGPUDeviceLostCallback2 = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), enum_WGPUDeviceLostReason, struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +struct_WGPUDeviceLostCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUDeviceLostCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +class struct_WGPUUncapturedErrorCallbackInfo2(Struct): pass +WGPUUncapturedErrorCallbackInfo2 = struct_WGPUUncapturedErrorCallbackInfo2 +WGPUUncapturedErrorCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.POINTER(struct_WGPUDeviceImpl)), enum_WGPUErrorType, struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +struct_WGPUUncapturedErrorCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('callback', WGPUUncapturedErrorCallback), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), ] - -WGPUComputeState = struct_WGPUComputeState -class struct_WGPUDeviceDescriptor(Structure): - pass - -struct_WGPUDeviceDescriptor._pack_ = 1 # source:False struct_WGPUDeviceDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('requiredFeatureCount', ctypes.c_uint64), - ('requiredFeatures', ctypes.POINTER(WGPUFeatureName)), - ('requiredLimits', ctypes.POINTER(struct_WGPURequiredLimits)), - ('defaultQueue', WGPUQueueDescriptor), - ('deviceLostCallbackInfo2', WGPUDeviceLostCallbackInfo2), - ('uncapturedErrorCallbackInfo2', WGPUUncapturedErrorCallbackInfo2), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('requiredFeatureCount', size_t), + ('requiredFeatures', ctypes.POINTER(WGPUFeatureName)), + ('requiredLimits', ctypes.POINTER(WGPURequiredLimits)), + ('defaultQueue', WGPUQueueDescriptor), + ('deviceLostCallbackInfo2', WGPUDeviceLostCallbackInfo2), + ('uncapturedErrorCallbackInfo2', WGPUUncapturedErrorCallbackInfo2), ] - -WGPUDeviceDescriptor = struct_WGPUDeviceDescriptor -class struct_WGPURenderPassDescriptor(Structure): - pass - -struct_WGPURenderPassDescriptor._pack_ = 1 # source:False +class struct_WGPURenderPassDescriptor(Struct): pass +WGPURenderPassColorAttachment = struct_WGPURenderPassColorAttachment +WGPURenderPassDepthStencilAttachment = struct_WGPURenderPassDepthStencilAttachment +WGPURenderPassTimestampWrites = struct_WGPURenderPassTimestampWrites struct_WGPURenderPassDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('colorAttachmentCount', ctypes.c_uint64), - ('colorAttachments', ctypes.POINTER(struct_WGPURenderPassColorAttachment)), - ('depthStencilAttachment', ctypes.POINTER(struct_WGPURenderPassDepthStencilAttachment)), - ('occlusionQuerySet', ctypes.POINTER(struct_WGPUQuerySetImpl)), - ('timestampWrites', ctypes.POINTER(struct_WGPURenderPassTimestampWrites)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('colorAttachmentCount', size_t), + ('colorAttachments', ctypes.POINTER(WGPURenderPassColorAttachment)), + ('depthStencilAttachment', ctypes.POINTER(WGPURenderPassDepthStencilAttachment)), + ('occlusionQuerySet', WGPUQuerySet), + ('timestampWrites', ctypes.POINTER(WGPURenderPassTimestampWrites)), ] - -WGPURenderPassDescriptor = struct_WGPURenderPassDescriptor -class struct_WGPURenderPassPixelLocalStorage(Structure): - pass - -struct_WGPURenderPassPixelLocalStorage._pack_ = 1 # source:False +class struct_WGPURenderPassPixelLocalStorage(Struct): pass +WGPURenderPassStorageAttachment = struct_WGPURenderPassStorageAttachment struct_WGPURenderPassPixelLocalStorage._fields_ = [ - ('chain', WGPUChainedStruct), - ('totalPixelLocalStorageSize', ctypes.c_uint64), - ('storageAttachmentCount', ctypes.c_uint64), - ('storageAttachments', ctypes.POINTER(struct_WGPURenderPassStorageAttachment)), + ('chain', WGPUChainedStruct), + ('totalPixelLocalStorageSize', uint64_t), + ('storageAttachmentCount', size_t), + ('storageAttachments', ctypes.POINTER(WGPURenderPassStorageAttachment)), ] - -WGPURenderPassPixelLocalStorage = struct_WGPURenderPassPixelLocalStorage -class struct_WGPUVertexState(Structure): - pass - -struct_WGPUVertexState._pack_ = 1 # source:False +class struct_WGPUVertexState(Struct): pass +WGPUVertexBufferLayout = struct_WGPUVertexBufferLayout struct_WGPUVertexState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('module', ctypes.POINTER(struct_WGPUShaderModuleImpl)), - ('entryPoint', WGPUStringView), - ('constantCount', ctypes.c_uint64), - ('constants', ctypes.POINTER(struct_WGPUConstantEntry)), - ('bufferCount', ctypes.c_uint64), - ('buffers', ctypes.POINTER(struct_WGPUVertexBufferLayout)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('module', WGPUShaderModule), + ('entryPoint', WGPUStringView), + ('constantCount', size_t), + ('constants', ctypes.POINTER(WGPUConstantEntry)), + ('bufferCount', size_t), + ('buffers', ctypes.POINTER(WGPUVertexBufferLayout)), ] - -WGPUVertexState = struct_WGPUVertexState -class struct_WGPUComputePipelineDescriptor(Structure): - pass - -struct_WGPUComputePipelineDescriptor._pack_ = 1 # source:False +class struct_WGPUComputePipelineDescriptor(Struct): pass +WGPUComputeState = struct_WGPUComputeState struct_WGPUComputePipelineDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('layout', ctypes.POINTER(struct_WGPUPipelineLayoutImpl)), - ('compute', WGPUComputeState), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('layout', WGPUPipelineLayout), + ('compute', WGPUComputeState), ] - -WGPUComputePipelineDescriptor = struct_WGPUComputePipelineDescriptor -class struct_WGPUFragmentState(Structure): - pass - -struct_WGPUFragmentState._pack_ = 1 # source:False +class struct_WGPUFragmentState(Struct): pass +WGPUColorTargetState = struct_WGPUColorTargetState struct_WGPUFragmentState._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('module', ctypes.POINTER(struct_WGPUShaderModuleImpl)), - ('entryPoint', WGPUStringView), - ('constantCount', ctypes.c_uint64), - ('constants', ctypes.POINTER(struct_WGPUConstantEntry)), - ('targetCount', ctypes.c_uint64), - ('targets', ctypes.POINTER(struct_WGPUColorTargetState)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('module', WGPUShaderModule), + ('entryPoint', WGPUStringView), + ('constantCount', size_t), + ('constants', ctypes.POINTER(WGPUConstantEntry)), + ('targetCount', size_t), + ('targets', ctypes.POINTER(WGPUColorTargetState)), ] - +class struct_WGPURenderPipelineDescriptor(Struct): pass +WGPUVertexState = struct_WGPUVertexState +WGPUPrimitiveState = struct_WGPUPrimitiveState +WGPUDepthStencilState = struct_WGPUDepthStencilState +WGPUMultisampleState = struct_WGPUMultisampleState WGPUFragmentState = struct_WGPUFragmentState -class struct_WGPURenderPipelineDescriptor(Structure): - pass - -struct_WGPURenderPipelineDescriptor._pack_ = 1 # source:False struct_WGPURenderPipelineDescriptor._fields_ = [ - ('nextInChain', ctypes.POINTER(struct_WGPUChainedStruct)), - ('label', WGPUStringView), - ('layout', ctypes.POINTER(struct_WGPUPipelineLayoutImpl)), - ('vertex', WGPUVertexState), - ('primitive', WGPUPrimitiveState), - ('depthStencil', ctypes.POINTER(struct_WGPUDepthStencilState)), - ('multisample', WGPUMultisampleState), - ('fragment', ctypes.POINTER(struct_WGPUFragmentState)), + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('layout', WGPUPipelineLayout), + ('vertex', WGPUVertexState), + ('primitive', WGPUPrimitiveState), + ('depthStencil', ctypes.POINTER(WGPUDepthStencilState)), + ('multisample', WGPUMultisampleState), + ('fragment', ctypes.POINTER(WGPUFragmentState)), ] +enum_WGPUWGSLFeatureName = CEnum(ctypes.c_uint32) +WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures', 1) +WGPUWGSLFeatureName_Packed4x8IntegerDotProduct = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_Packed4x8IntegerDotProduct', 2) +WGPUWGSLFeatureName_UnrestrictedPointerParameters = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_UnrestrictedPointerParameters', 3) +WGPUWGSLFeatureName_PointerCompositeAccess = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_PointerCompositeAccess', 4) +WGPUWGSLFeatureName_ChromiumTestingUnimplemented = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_ChromiumTestingUnimplemented', 327680) +WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental', 327681) +WGPUWGSLFeatureName_ChromiumTestingExperimental = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_ChromiumTestingExperimental', 327682) +WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch', 327683) +WGPUWGSLFeatureName_ChromiumTestingShipped = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_ChromiumTestingShipped', 327684) +WGPUWGSLFeatureName_Force32 = enum_WGPUWGSLFeatureName.define('WGPUWGSLFeatureName_Force32', 2147483647) +WGPUWGSLFeatureName = enum_WGPUWGSLFeatureName +WGPUBufferMapAsyncStatus = enum_WGPUBufferMapAsyncStatus +enum_WGPUBufferMapState = CEnum(ctypes.c_uint32) +WGPUBufferMapState_Unmapped = enum_WGPUBufferMapState.define('WGPUBufferMapState_Unmapped', 1) +WGPUBufferMapState_Pending = enum_WGPUBufferMapState.define('WGPUBufferMapState_Pending', 2) +WGPUBufferMapState_Mapped = enum_WGPUBufferMapState.define('WGPUBufferMapState_Mapped', 3) +WGPUBufferMapState_Force32 = enum_WGPUBufferMapState.define('WGPUBufferMapState_Force32', 2147483647) + +WGPUBufferMapState = enum_WGPUBufferMapState +WGPUCompilationInfoRequestStatus = enum_WGPUCompilationInfoRequestStatus +WGPUCreatePipelineAsyncStatus = enum_WGPUCreatePipelineAsyncStatus +WGPUDeviceLostReason = enum_WGPUDeviceLostReason +enum_WGPUErrorFilter = CEnum(ctypes.c_uint32) +WGPUErrorFilter_Validation = enum_WGPUErrorFilter.define('WGPUErrorFilter_Validation', 1) +WGPUErrorFilter_OutOfMemory = enum_WGPUErrorFilter.define('WGPUErrorFilter_OutOfMemory', 2) +WGPUErrorFilter_Internal = enum_WGPUErrorFilter.define('WGPUErrorFilter_Internal', 3) +WGPUErrorFilter_Force32 = enum_WGPUErrorFilter.define('WGPUErrorFilter_Force32', 2147483647) + +WGPUErrorFilter = enum_WGPUErrorFilter +WGPUErrorType = enum_WGPUErrorType +enum_WGPULoggingType = CEnum(ctypes.c_uint32) +WGPULoggingType_Verbose = enum_WGPULoggingType.define('WGPULoggingType_Verbose', 1) +WGPULoggingType_Info = enum_WGPULoggingType.define('WGPULoggingType_Info', 2) +WGPULoggingType_Warning = enum_WGPULoggingType.define('WGPULoggingType_Warning', 3) +WGPULoggingType_Error = enum_WGPULoggingType.define('WGPULoggingType_Error', 4) +WGPULoggingType_Force32 = enum_WGPULoggingType.define('WGPULoggingType_Force32', 2147483647) + +WGPULoggingType = enum_WGPULoggingType +enum_WGPUMapAsyncStatus = CEnum(ctypes.c_uint32) +WGPUMapAsyncStatus_Success = enum_WGPUMapAsyncStatus.define('WGPUMapAsyncStatus_Success', 1) +WGPUMapAsyncStatus_InstanceDropped = enum_WGPUMapAsyncStatus.define('WGPUMapAsyncStatus_InstanceDropped', 2) +WGPUMapAsyncStatus_Error = enum_WGPUMapAsyncStatus.define('WGPUMapAsyncStatus_Error', 3) +WGPUMapAsyncStatus_Aborted = enum_WGPUMapAsyncStatus.define('WGPUMapAsyncStatus_Aborted', 4) +WGPUMapAsyncStatus_Unknown = enum_WGPUMapAsyncStatus.define('WGPUMapAsyncStatus_Unknown', 5) +WGPUMapAsyncStatus_Force32 = enum_WGPUMapAsyncStatus.define('WGPUMapAsyncStatus_Force32', 2147483647) + +WGPUMapAsyncStatus = enum_WGPUMapAsyncStatus +WGPUPopErrorScopeStatus = enum_WGPUPopErrorScopeStatus +WGPUQueueWorkDoneStatus = enum_WGPUQueueWorkDoneStatus +WGPURequestAdapterStatus = enum_WGPURequestAdapterStatus +WGPURequestDeviceStatus = enum_WGPURequestDeviceStatus +enum_WGPUStatus = CEnum(ctypes.c_uint32) +WGPUStatus_Success = enum_WGPUStatus.define('WGPUStatus_Success', 1) +WGPUStatus_Error = enum_WGPUStatus.define('WGPUStatus_Error', 2) +WGPUStatus_Force32 = enum_WGPUStatus.define('WGPUStatus_Force32', 2147483647) + +WGPUStatus = enum_WGPUStatus +enum_WGPUWaitStatus = CEnum(ctypes.c_uint32) +WGPUWaitStatus_Success = enum_WGPUWaitStatus.define('WGPUWaitStatus_Success', 1) +WGPUWaitStatus_TimedOut = enum_WGPUWaitStatus.define('WGPUWaitStatus_TimedOut', 2) +WGPUWaitStatus_UnsupportedTimeout = enum_WGPUWaitStatus.define('WGPUWaitStatus_UnsupportedTimeout', 3) +WGPUWaitStatus_UnsupportedCount = enum_WGPUWaitStatus.define('WGPUWaitStatus_UnsupportedCount', 4) +WGPUWaitStatus_UnsupportedMixedSources = enum_WGPUWaitStatus.define('WGPUWaitStatus_UnsupportedMixedSources', 5) +WGPUWaitStatus_Unknown = enum_WGPUWaitStatus.define('WGPUWaitStatus_Unknown', 6) +WGPUWaitStatus_Force32 = enum_WGPUWaitStatus.define('WGPUWaitStatus_Force32', 2147483647) + +WGPUWaitStatus = enum_WGPUWaitStatus +WGPUMapMode = ctypes.c_uint64 +WGPUDeviceLostCallback = ctypes.CFUNCTYPE(None, enum_WGPUDeviceLostReason, struct_WGPUStringView, ctypes.c_void_p) +WGPULoggingCallback = ctypes.CFUNCTYPE(None, enum_WGPULoggingType, struct_WGPUStringView, ctypes.c_void_p) +WGPUProc = ctypes.CFUNCTYPE(None, ) +WGPUBufferMapCallback2 = ctypes.CFUNCTYPE(None, enum_WGPUMapAsyncStatus, struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +WGPUCompilationInfoCallback2 = ctypes.CFUNCTYPE(None, enum_WGPUCompilationInfoRequestStatus, ctypes.POINTER(const_struct_WGPUCompilationInfo), ctypes.c_void_p, ctypes.c_void_p) +WGPUCreateComputePipelineAsyncCallback2 = ctypes.CFUNCTYPE(None, enum_WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +WGPUCreateRenderPipelineAsyncCallback2 = ctypes.CFUNCTYPE(None, enum_WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +WGPUPopErrorScopeCallback2 = ctypes.CFUNCTYPE(None, enum_WGPUPopErrorScopeStatus, enum_WGPUErrorType, struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +WGPUQueueWorkDoneCallback2 = ctypes.CFUNCTYPE(None, enum_WGPUQueueWorkDoneStatus, ctypes.c_void_p, ctypes.c_void_p) +WGPURequestAdapterCallback2 = ctypes.CFUNCTYPE(None, enum_WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +WGPURequestDeviceCallback2 = ctypes.CFUNCTYPE(None, enum_WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.c_void_p, ctypes.c_void_p) +class struct_WGPUBufferMapCallbackInfo2(Struct): pass +struct_WGPUBufferMapCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUBufferMapCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPUBufferMapCallbackInfo2 = struct_WGPUBufferMapCallbackInfo2 +class struct_WGPUCompilationInfoCallbackInfo2(Struct): pass +struct_WGPUCompilationInfoCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUCompilationInfoCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPUCompilationInfoCallbackInfo2 = struct_WGPUCompilationInfoCallbackInfo2 +class struct_WGPUCreateComputePipelineAsyncCallbackInfo2(Struct): pass +struct_WGPUCreateComputePipelineAsyncCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUCreateComputePipelineAsyncCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPUCreateComputePipelineAsyncCallbackInfo2 = struct_WGPUCreateComputePipelineAsyncCallbackInfo2 +class struct_WGPUCreateRenderPipelineAsyncCallbackInfo2(Struct): pass +struct_WGPUCreateRenderPipelineAsyncCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUCreateRenderPipelineAsyncCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPUCreateRenderPipelineAsyncCallbackInfo2 = struct_WGPUCreateRenderPipelineAsyncCallbackInfo2 +class struct_WGPUPopErrorScopeCallbackInfo2(Struct): pass +struct_WGPUPopErrorScopeCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUPopErrorScopeCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPUPopErrorScopeCallbackInfo2 = struct_WGPUPopErrorScopeCallbackInfo2 +class struct_WGPUQueueWorkDoneCallbackInfo2(Struct): pass +struct_WGPUQueueWorkDoneCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPUQueueWorkDoneCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPUQueueWorkDoneCallbackInfo2 = struct_WGPUQueueWorkDoneCallbackInfo2 +class struct_WGPURequestAdapterCallbackInfo2(Struct): pass +struct_WGPURequestAdapterCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPURequestAdapterCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPURequestAdapterCallbackInfo2 = struct_WGPURequestAdapterCallbackInfo2 +class struct_WGPURequestDeviceCallbackInfo2(Struct): pass +struct_WGPURequestDeviceCallbackInfo2._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('mode', WGPUCallbackMode), + ('callback', WGPURequestDeviceCallback2), + ('userdata1', ctypes.c_void_p), + ('userdata2', ctypes.c_void_p), +] +WGPURequestDeviceCallbackInfo2 = struct_WGPURequestDeviceCallbackInfo2 +WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER = struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER +WGPUAdapterPropertiesD3D = struct_WGPUAdapterPropertiesD3D +WGPUAdapterPropertiesSubgroups = struct_WGPUAdapterPropertiesSubgroups +WGPUAdapterPropertiesVk = struct_WGPUAdapterPropertiesVk +WGPUBufferHostMappedPointer = struct_WGPUBufferHostMappedPointer +WGPUBufferMapCallbackInfo = struct_WGPUBufferMapCallbackInfo +WGPUColorTargetStateExpandResolveTextureDawn = struct_WGPUColorTargetStateExpandResolveTextureDawn +WGPUCompilationInfoCallbackInfo = struct_WGPUCompilationInfoCallbackInfo +WGPUCopyTextureForBrowserOptions = struct_WGPUCopyTextureForBrowserOptions +WGPUCreateComputePipelineAsyncCallbackInfo = struct_WGPUCreateComputePipelineAsyncCallbackInfo +WGPUCreateRenderPipelineAsyncCallbackInfo = struct_WGPUCreateRenderPipelineAsyncCallbackInfo +WGPUDawnWGSLBlocklist = struct_WGPUDawnWGSLBlocklist +WGPUDawnAdapterPropertiesPowerPreference = struct_WGPUDawnAdapterPropertiesPowerPreference +WGPUDawnBufferDescriptorErrorInfoFromWireClient = struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient +WGPUDawnEncoderInternalUsageDescriptor = struct_WGPUDawnEncoderInternalUsageDescriptor +WGPUDawnExperimentalImmediateDataLimits = struct_WGPUDawnExperimentalImmediateDataLimits +WGPUDawnExperimentalSubgroupLimits = struct_WGPUDawnExperimentalSubgroupLimits +WGPUDawnRenderPassColorAttachmentRenderToSingleSampled = struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled +WGPUDawnShaderModuleSPIRVOptionsDescriptor = struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor +WGPUDawnTexelCopyBufferRowAlignmentLimits = struct_WGPUDawnTexelCopyBufferRowAlignmentLimits +WGPUDawnTextureInternalUsageDescriptor = struct_WGPUDawnTextureInternalUsageDescriptor +WGPUDawnTogglesDescriptor = struct_WGPUDawnTogglesDescriptor +WGPUDawnWireWGSLControl = struct_WGPUDawnWireWGSLControl +WGPUDeviceLostCallbackInfo = struct_WGPUDeviceLostCallbackInfo +WGPUExternalTextureBindingEntry = struct_WGPUExternalTextureBindingEntry +WGPUExternalTextureBindingLayout = struct_WGPUExternalTextureBindingLayout +WGPUFormatCapabilities = struct_WGPUFormatCapabilities +WGPUPopErrorScopeCallbackInfo = struct_WGPUPopErrorScopeCallbackInfo +WGPUQueueWorkDoneCallbackInfo = struct_WGPUQueueWorkDoneCallbackInfo +WGPURenderPassDescriptorExpandResolveRect = struct_WGPURenderPassDescriptorExpandResolveRect +WGPURenderPassMaxDrawCount = struct_WGPURenderPassMaxDrawCount +WGPURequestAdapterCallbackInfo = struct_WGPURequestAdapterCallbackInfo +WGPURequestAdapterOptions = struct_WGPURequestAdapterOptions +WGPURequestDeviceCallbackInfo = struct_WGPURequestDeviceCallbackInfo +WGPUShaderModuleCompilationOptions = struct_WGPUShaderModuleCompilationOptions +WGPUShaderSourceSPIRV = struct_WGPUShaderSourceSPIRV +WGPUSharedBufferMemoryBeginAccessDescriptor = struct_WGPUSharedBufferMemoryBeginAccessDescriptor +WGPUSharedBufferMemoryEndAccessState = struct_WGPUSharedBufferMemoryEndAccessState +WGPUSharedBufferMemoryProperties = struct_WGPUSharedBufferMemoryProperties +WGPUSharedFenceDXGISharedHandleDescriptor = struct_WGPUSharedFenceDXGISharedHandleDescriptor +WGPUSharedFenceDXGISharedHandleExportInfo = struct_WGPUSharedFenceDXGISharedHandleExportInfo +WGPUSharedFenceMTLSharedEventDescriptor = struct_WGPUSharedFenceMTLSharedEventDescriptor +WGPUSharedFenceMTLSharedEventExportInfo = struct_WGPUSharedFenceMTLSharedEventExportInfo +WGPUSharedFenceExportInfo = struct_WGPUSharedFenceExportInfo +WGPUSharedFenceSyncFDDescriptor = struct_WGPUSharedFenceSyncFDDescriptor +WGPUSharedFenceSyncFDExportInfo = struct_WGPUSharedFenceSyncFDExportInfo +WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor = struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor +WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo = struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo +WGPUSharedFenceVkSemaphoreZirconHandleDescriptor = struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor +WGPUSharedFenceVkSemaphoreZirconHandleExportInfo = struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo +WGPUSharedTextureMemoryD3DSwapchainBeginState = struct_WGPUSharedTextureMemoryD3DSwapchainBeginState +WGPUSharedTextureMemoryDXGISharedHandleDescriptor = struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor +WGPUSharedTextureMemoryEGLImageDescriptor = struct_WGPUSharedTextureMemoryEGLImageDescriptor +WGPUSharedTextureMemoryIOSurfaceDescriptor = struct_WGPUSharedTextureMemoryIOSurfaceDescriptor +WGPUSharedTextureMemoryAHardwareBufferDescriptor = struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor +WGPUSharedTextureMemoryBeginAccessDescriptor = struct_WGPUSharedTextureMemoryBeginAccessDescriptor +WGPUSharedTextureMemoryEndAccessState = struct_WGPUSharedTextureMemoryEndAccessState +WGPUSharedTextureMemoryOpaqueFDDescriptor = struct_WGPUSharedTextureMemoryOpaqueFDDescriptor +WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor = struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor +WGPUSharedTextureMemoryVkImageLayoutBeginState = struct_WGPUSharedTextureMemoryVkImageLayoutBeginState +WGPUSharedTextureMemoryVkImageLayoutEndState = struct_WGPUSharedTextureMemoryVkImageLayoutEndState +WGPUSharedTextureMemoryZirconHandleDescriptor = struct_WGPUSharedTextureMemoryZirconHandleDescriptor +WGPUStaticSamplerBindingLayout = struct_WGPUStaticSamplerBindingLayout +WGPUSupportedFeatures = struct_WGPUSupportedFeatures +WGPUSurfaceCapabilities = struct_WGPUSurfaceCapabilities +WGPUSurfaceConfiguration = struct_WGPUSurfaceConfiguration +WGPUSurfaceDescriptorFromWindowsCoreWindow = struct_WGPUSurfaceDescriptorFromWindowsCoreWindow +WGPUSurfaceDescriptorFromWindowsSwapChainPanel = struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel +WGPUSurfaceSourceXCBWindow = struct_WGPUSurfaceSourceXCBWindow +WGPUSurfaceSourceAndroidNativeWindow = struct_WGPUSurfaceSourceAndroidNativeWindow +WGPUSurfaceSourceMetalLayer = struct_WGPUSurfaceSourceMetalLayer +WGPUSurfaceSourceWaylandSurface = struct_WGPUSurfaceSourceWaylandSurface +WGPUSurfaceSourceWindowsHWND = struct_WGPUSurfaceSourceWindowsHWND +WGPUSurfaceSourceXlibWindow = struct_WGPUSurfaceSourceXlibWindow +WGPUSurfaceTexture = struct_WGPUSurfaceTexture +WGPUTextureBindingViewDimensionDescriptor = struct_WGPUTextureBindingViewDimensionDescriptor +WGPUUncapturedErrorCallbackInfo = struct_WGPUUncapturedErrorCallbackInfo +WGPUAHardwareBufferProperties = struct_WGPUAHardwareBufferProperties +WGPUAdapterInfo = struct_WGPUAdapterInfo +WGPUAdapterPropertiesMemoryHeaps = struct_WGPUAdapterPropertiesMemoryHeaps +WGPUBindGroupDescriptor = struct_WGPUBindGroupDescriptor +WGPUBufferDescriptor = struct_WGPUBufferDescriptor +WGPUCommandBufferDescriptor = struct_WGPUCommandBufferDescriptor +WGPUCommandEncoderDescriptor = struct_WGPUCommandEncoderDescriptor +WGPUComputePassDescriptor = struct_WGPUComputePassDescriptor +WGPUDawnCacheDeviceDescriptor = struct_WGPUDawnCacheDeviceDescriptor +WGPUDrmFormatCapabilities = struct_WGPUDrmFormatCapabilities +WGPUExternalTextureDescriptor = struct_WGPUExternalTextureDescriptor +WGPUFutureWaitInfo = struct_WGPUFutureWaitInfo +WGPUImageCopyBuffer = struct_WGPUImageCopyBuffer +WGPUImageCopyExternalTexture = struct_WGPUImageCopyExternalTexture +WGPUImageCopyTexture = struct_WGPUImageCopyTexture +WGPUInstanceDescriptor = struct_WGPUInstanceDescriptor +WGPUPipelineLayoutDescriptor = struct_WGPUPipelineLayoutDescriptor +WGPUPipelineLayoutPixelLocalStorage = struct_WGPUPipelineLayoutPixelLocalStorage +WGPUQuerySetDescriptor = struct_WGPUQuerySetDescriptor +WGPURenderBundleDescriptor = struct_WGPURenderBundleDescriptor +WGPURenderBundleEncoderDescriptor = struct_WGPURenderBundleEncoderDescriptor +WGPUSamplerDescriptor = struct_WGPUSamplerDescriptor +WGPUShaderModuleDescriptor = struct_WGPUShaderModuleDescriptor +WGPUShaderSourceWGSL = struct_WGPUShaderSourceWGSL +WGPUSharedBufferMemoryDescriptor = struct_WGPUSharedBufferMemoryDescriptor +WGPUSharedFenceDescriptor = struct_WGPUSharedFenceDescriptor +WGPUSharedTextureMemoryAHardwareBufferProperties = struct_WGPUSharedTextureMemoryAHardwareBufferProperties +WGPUSharedTextureMemoryDescriptor = struct_WGPUSharedTextureMemoryDescriptor +WGPUSharedTextureMemoryDmaBufDescriptor = struct_WGPUSharedTextureMemoryDmaBufDescriptor +WGPUSharedTextureMemoryProperties = struct_WGPUSharedTextureMemoryProperties +WGPUSupportedLimits = struct_WGPUSupportedLimits +WGPUSurfaceDescriptor = struct_WGPUSurfaceDescriptor +WGPUSurfaceSourceCanvasHTMLSelector_Emscripten = struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten +WGPUTextureDescriptor = struct_WGPUTextureDescriptor +WGPUTextureViewDescriptor = struct_WGPUTextureViewDescriptor +WGPUBindGroupLayoutDescriptor = struct_WGPUBindGroupLayoutDescriptor +WGPUCompilationInfo = struct_WGPUCompilationInfo +WGPUDeviceDescriptor = struct_WGPUDeviceDescriptor +WGPURenderPassDescriptor = struct_WGPURenderPassDescriptor +WGPURenderPassPixelLocalStorage = struct_WGPURenderPassPixelLocalStorage +WGPUComputePipelineDescriptor = struct_WGPUComputePipelineDescriptor WGPURenderPipelineDescriptor = struct_WGPURenderPipelineDescriptor WGPURenderPassDescriptorMaxDrawCount = struct_WGPURenderPassMaxDrawCount WGPUShaderModuleSPIRVDescriptor = struct_WGPUShaderSourceSPIRV @@ -3972,24 +2272,40 @@ WGPUSurfaceDescriptorFromXcbWindow = struct_WGPUSurfaceSourceXCBWindow WGPUSurfaceDescriptorFromXlibWindow = struct_WGPUSurfaceSourceXlibWindow WGPUProcAdapterInfoFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUAdapterInfo) WGPUProcAdapterPropertiesMemoryHeapsFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUAdapterPropertiesMemoryHeaps) -WGPUProcCreateInstance = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPUInstanceDescriptor)) +class const_struct_WGPUInstanceDescriptor(Struct): pass +const_struct_WGPUInstanceDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('features', WGPUInstanceFeatures), +] +WGPUProcCreateInstance = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(const_struct_WGPUInstanceDescriptor)) WGPUProcDrmFormatCapabilitiesFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUDrmFormatCapabilities) -WGPUProcGetInstanceFeatures = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUInstanceFeatures)) -WGPUProcGetProcAddress = ctypes.CFUNCTYPE(ctypes.CFUNCTYPE(None), struct_WGPUStringView) +WGPUProcGetInstanceFeatures = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUInstanceFeatures)) +WGPUProcGetProcAddress = ctypes.CFUNCTYPE(ctypes.CFUNCTYPE(None, ), struct_WGPUStringView) WGPUProcSharedBufferMemoryEndAccessStateFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSharedBufferMemoryEndAccessState) WGPUProcSharedTextureMemoryEndAccessStateFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSharedTextureMemoryEndAccessState) WGPUProcSupportedFeaturesFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSupportedFeatures) WGPUProcSurfaceCapabilitiesFreeMembers = ctypes.CFUNCTYPE(None, struct_WGPUSurfaceCapabilities) -WGPUProcAdapterCreateDevice = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor)) +class const_struct_WGPUDeviceDescriptor(Struct): pass +const_struct_WGPUDeviceDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('requiredFeatureCount', size_t), + ('requiredFeatures', ctypes.POINTER(WGPUFeatureName)), + ('requiredLimits', ctypes.POINTER(WGPURequiredLimits)), + ('defaultQueue', WGPUQueueDescriptor), + ('deviceLostCallbackInfo2', WGPUDeviceLostCallbackInfo2), + ('uncapturedErrorCallbackInfo2', WGPUUncapturedErrorCallbackInfo2), +] +WGPUProcAdapterCreateDevice = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(const_struct_WGPUDeviceDescriptor)) WGPUProcAdapterGetFeatures = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSupportedFeatures)) -WGPUProcAdapterGetFormatCapabilities = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), WGPUTextureFormat, ctypes.POINTER(struct_WGPUFormatCapabilities)) -WGPUProcAdapterGetInfo = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUAdapterInfo)) +WGPUProcAdapterGetFormatCapabilities = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), enum_WGPUTextureFormat, ctypes.POINTER(struct_WGPUFormatCapabilities)) +WGPUProcAdapterGetInfo = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUAdapterInfo)) WGPUProcAdapterGetInstance = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPUAdapterImpl)) -WGPUProcAdapterGetLimits = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSupportedLimits)) -WGPUProcAdapterHasFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUAdapterImpl), WGPUFeatureName) -WGPUProcAdapterRequestDevice = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor), ctypes.CFUNCTYPE(None, WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcAdapterRequestDevice2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor), struct_WGPURequestDeviceCallbackInfo2) -WGPUProcAdapterRequestDeviceF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceDescriptor), struct_WGPURequestDeviceCallbackInfo) +WGPUProcAdapterGetLimits = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSupportedLimits)) +WGPUProcAdapterHasFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUAdapterImpl), enum_WGPUFeatureName) +WGPUProcAdapterRequestDevice = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(const_struct_WGPUDeviceDescriptor), ctypes.CFUNCTYPE(None, enum_WGPURequestDeviceStatus, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView, ctypes.c_void_p), ctypes.c_void_p) +WGPUProcAdapterRequestDevice2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(const_struct_WGPUDeviceDescriptor), struct_WGPURequestDeviceCallbackInfo2) +WGPUProcAdapterRequestDeviceF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(const_struct_WGPUDeviceDescriptor), struct_WGPURequestDeviceCallbackInfo) WGPUProcAdapterAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl)) WGPUProcAdapterRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUAdapterImpl)) WGPUProcBindGroupSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupImpl), struct_WGPUStringView) @@ -3999,12 +2315,12 @@ WGPUProcBindGroupLayoutSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_W WGPUProcBindGroupLayoutAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupLayoutImpl)) WGPUProcBindGroupLayoutRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBindGroupLayoutImpl)) WGPUProcBufferDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferGetConstMappedRange = ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcBufferGetMapState = ctypes.CFUNCTYPE(WGPUBufferMapState, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferGetMappedRange = ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) +WGPUProcBufferGetConstMappedRange = ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) +WGPUProcBufferGetMapState = ctypes.CFUNCTYPE(enum_WGPUBufferMapState, ctypes.POINTER(struct_WGPUBufferImpl)) +WGPUProcBufferGetMappedRange = ctypes.CFUNCTYPE(ctypes.c_void_p, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) WGPUProcBufferGetSize = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUBufferImpl)) WGPUProcBufferGetUsage = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUBufferImpl)) -WGPUProcBufferMapAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.CFUNCTYPE(None, WGPUBufferMapAsyncStatus, ctypes.POINTER(None)), ctypes.POINTER(None)) +WGPUProcBufferMapAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, ctypes.CFUNCTYPE(None, enum_WGPUBufferMapAsyncStatus, ctypes.c_void_p), ctypes.c_void_p) WGPUProcBufferMapAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, struct_WGPUBufferMapCallbackInfo2) WGPUProcBufferMapAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64, struct_WGPUBufferMapCallbackInfo) WGPUProcBufferSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferImpl), struct_WGPUStringView) @@ -4014,14 +2330,53 @@ WGPUProcBufferRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUBufferI WGPUProcCommandBufferSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandBufferImpl), struct_WGPUStringView) WGPUProcCommandBufferAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandBufferImpl)) WGPUProcCommandBufferRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandBufferImpl)) -WGPUProcCommandEncoderBeginComputePass = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUComputePassDescriptor)) -WGPUProcCommandEncoderBeginRenderPass = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPURenderPassDescriptor)) +class const_struct_WGPUComputePassDescriptor(Struct): pass +const_struct_WGPUComputePassDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('timestampWrites', ctypes.POINTER(WGPUComputePassTimestampWrites)), +] +WGPUProcCommandEncoderBeginComputePass = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUComputePassEncoderImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(const_struct_WGPUComputePassDescriptor)) +class const_struct_WGPURenderPassDescriptor(Struct): pass +const_struct_WGPURenderPassDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('colorAttachmentCount', size_t), + ('colorAttachments', ctypes.POINTER(WGPURenderPassColorAttachment)), + ('depthStencilAttachment', ctypes.POINTER(WGPURenderPassDepthStencilAttachment)), + ('occlusionQuerySet', WGPUQuerySet), + ('timestampWrites', ctypes.POINTER(WGPURenderPassTimestampWrites)), +] +WGPUProcCommandEncoderBeginRenderPass = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(const_struct_WGPURenderPassDescriptor)) WGPUProcCommandEncoderClearBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) WGPUProcCommandEncoderCopyBufferToBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) -WGPUProcCommandEncoderCopyBufferToTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcCommandEncoderCopyTextureToBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcCommandEncoderCopyTextureToTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)) -WGPUProcCommandEncoderFinish = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUCommandBufferImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUCommandBufferDescriptor)) +class const_struct_WGPUImageCopyBuffer(Struct): pass +const_struct_WGPUImageCopyBuffer._fields_ = [ + ('layout', WGPUTextureDataLayout), + ('buffer', WGPUBuffer), +] +class const_struct_WGPUImageCopyTexture(Struct): pass +const_struct_WGPUImageCopyTexture._fields_ = [ + ('texture', WGPUTexture), + ('mipLevel', uint32_t), + ('origin', WGPUOrigin3D), + ('aspect', WGPUTextureAspect), +] +class const_struct_WGPUExtent3D(Struct): pass +const_struct_WGPUExtent3D._fields_ = [ + ('width', uint32_t), + ('height', uint32_t), + ('depthOrArrayLayers', uint32_t), +] +WGPUProcCommandEncoderCopyBufferToTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(const_struct_WGPUImageCopyBuffer), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUExtent3D)) +WGPUProcCommandEncoderCopyTextureToBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUImageCopyBuffer), ctypes.POINTER(const_struct_WGPUExtent3D)) +WGPUProcCommandEncoderCopyTextureToTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUExtent3D)) +class const_struct_WGPUCommandBufferDescriptor(Struct): pass +const_struct_WGPUCommandBufferDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcCommandEncoderFinish = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUCommandBufferImpl), ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(const_struct_WGPUCommandBufferDescriptor)) WGPUProcCommandEncoderInjectValidationError = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), struct_WGPUStringView) WGPUProcCommandEncoderInsertDebugMarker = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl), struct_WGPUStringView) WGPUProcCommandEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUCommandEncoderImpl)) @@ -4048,51 +2403,188 @@ WGPUProcComputePipelineGetBindGroupLayout = ctypes.CFUNCTYPE(ctypes.POINTER(stru WGPUProcComputePipelineSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView) WGPUProcComputePipelineAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePipelineImpl)) WGPUProcComputePipelineRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUComputePipelineImpl)) -WGPUProcDeviceCreateBindGroup = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBindGroupDescriptor)) -WGPUProcDeviceCreateBindGroupLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBindGroupLayoutDescriptor)) -WGPUProcDeviceCreateBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBufferDescriptor)) -WGPUProcDeviceCreateCommandEncoder = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUCommandEncoderDescriptor)) -WGPUProcDeviceCreateComputePipeline = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUComputePipelineImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor)) -WGPUProcDeviceCreateComputePipelineAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor), ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcDeviceCreateComputePipelineAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor), struct_WGPUCreateComputePipelineAsyncCallbackInfo2) -WGPUProcDeviceCreateComputePipelineAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUComputePipelineDescriptor), struct_WGPUCreateComputePipelineAsyncCallbackInfo) -WGPUProcDeviceCreateErrorBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUBufferDescriptor)) +class const_struct_WGPUBindGroupDescriptor(Struct): pass +const_struct_WGPUBindGroupDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('layout', WGPUBindGroupLayout), + ('entryCount', size_t), + ('entries', ctypes.POINTER(WGPUBindGroupEntry)), +] +WGPUProcDeviceCreateBindGroup = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUBindGroupDescriptor)) +class const_struct_WGPUBindGroupLayoutDescriptor(Struct): pass +const_struct_WGPUBindGroupLayoutDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('entryCount', size_t), + ('entries', ctypes.POINTER(WGPUBindGroupLayoutEntry)), +] +WGPUProcDeviceCreateBindGroupLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBindGroupLayoutImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUBindGroupLayoutDescriptor)) +class const_struct_WGPUBufferDescriptor(Struct): pass +const_struct_WGPUBufferDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('usage', WGPUBufferUsage), + ('size', uint64_t), + ('mappedAtCreation', WGPUBool), +] +WGPUProcDeviceCreateBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUBufferDescriptor)) +class const_struct_WGPUCommandEncoderDescriptor(Struct): pass +const_struct_WGPUCommandEncoderDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcDeviceCreateCommandEncoder = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUCommandEncoderImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUCommandEncoderDescriptor)) +class const_struct_WGPUComputePipelineDescriptor(Struct): pass +const_struct_WGPUComputePipelineDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('layout', WGPUPipelineLayout), + ('compute', WGPUComputeState), +] +WGPUProcDeviceCreateComputePipeline = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUComputePipelineImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUComputePipelineDescriptor)) +WGPUProcDeviceCreateComputePipelineAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUComputePipelineDescriptor), ctypes.CFUNCTYPE(None, enum_WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPUComputePipelineImpl), struct_WGPUStringView, ctypes.c_void_p), ctypes.c_void_p) +WGPUProcDeviceCreateComputePipelineAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUComputePipelineDescriptor), struct_WGPUCreateComputePipelineAsyncCallbackInfo2) +WGPUProcDeviceCreateComputePipelineAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUComputePipelineDescriptor), struct_WGPUCreateComputePipelineAsyncCallbackInfo) +WGPUProcDeviceCreateErrorBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUBufferDescriptor)) WGPUProcDeviceCreateErrorExternalTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUExternalTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceCreateErrorShaderModule = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUShaderModuleDescriptor), struct_WGPUStringView) -WGPUProcDeviceCreateErrorTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) -WGPUProcDeviceCreateExternalTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUExternalTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUExternalTextureDescriptor)) -WGPUProcDeviceCreatePipelineLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUPipelineLayoutImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUPipelineLayoutDescriptor)) -WGPUProcDeviceCreateQuerySet = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUQuerySetDescriptor)) -WGPUProcDeviceCreateRenderBundleEncoder = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderBundleEncoderDescriptor)) -WGPUProcDeviceCreateRenderPipeline = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderPipelineImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor)) -WGPUProcDeviceCreateRenderPipelineAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor), ctypes.CFUNCTYPE(None, WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcDeviceCreateRenderPipelineAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor), struct_WGPUCreateRenderPipelineAsyncCallbackInfo2) -WGPUProcDeviceCreateRenderPipelineAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPURenderPipelineDescriptor), struct_WGPUCreateRenderPipelineAsyncCallbackInfo) -WGPUProcDeviceCreateSampler = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSamplerImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSamplerDescriptor)) -WGPUProcDeviceCreateShaderModule = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUShaderModuleDescriptor)) -WGPUProcDeviceCreateTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) +class const_struct_WGPUShaderModuleDescriptor(Struct): pass +const_struct_WGPUShaderModuleDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcDeviceCreateErrorShaderModule = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUShaderModuleDescriptor), struct_WGPUStringView) +class const_struct_WGPUTextureDescriptor(Struct): pass +const_struct_WGPUTextureDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('usage', WGPUTextureUsage), + ('dimension', WGPUTextureDimension), + ('size', WGPUExtent3D), + ('format', WGPUTextureFormat), + ('mipLevelCount', uint32_t), + ('sampleCount', uint32_t), + ('viewFormatCount', size_t), + ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), +] +WGPUProcDeviceCreateErrorTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUTextureDescriptor)) +class const_struct_WGPUExternalTextureDescriptor(Struct): pass +const_struct_WGPUExternalTextureDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('plane0', WGPUTextureView), + ('plane1', WGPUTextureView), + ('cropOrigin', WGPUOrigin2D), + ('cropSize', WGPUExtent2D), + ('apparentSize', WGPUExtent2D), + ('doYuvToRgbConversionOnly', WGPUBool), + ('yuvToRgbConversionMatrix', ctypes.POINTER(ctypes.c_float)), + ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('gamutConversionMatrix', ctypes.POINTER(ctypes.c_float)), + ('mirrored', WGPUBool), + ('rotation', WGPUExternalTextureRotation), +] +WGPUProcDeviceCreateExternalTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUExternalTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUExternalTextureDescriptor)) +class const_struct_WGPUPipelineLayoutDescriptor(Struct): pass +const_struct_WGPUPipelineLayoutDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('bindGroupLayoutCount', size_t), + ('bindGroupLayouts', ctypes.POINTER(WGPUBindGroupLayout)), + ('immediateDataRangeByteSize', uint32_t), +] +WGPUProcDeviceCreatePipelineLayout = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUPipelineLayoutImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUPipelineLayoutDescriptor)) +class const_struct_WGPUQuerySetDescriptor(Struct): pass +const_struct_WGPUQuerySetDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('type', WGPUQueryType), + ('count', uint32_t), +] +WGPUProcDeviceCreateQuerySet = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUQuerySetImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUQuerySetDescriptor)) +class const_struct_WGPURenderBundleEncoderDescriptor(Struct): pass +const_struct_WGPURenderBundleEncoderDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('colorFormatCount', size_t), + ('colorFormats', ctypes.POINTER(WGPUTextureFormat)), + ('depthStencilFormat', WGPUTextureFormat), + ('sampleCount', uint32_t), + ('depthReadOnly', WGPUBool), + ('stencilReadOnly', WGPUBool), +] +WGPUProcDeviceCreateRenderBundleEncoder = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPURenderBundleEncoderDescriptor)) +class const_struct_WGPURenderPipelineDescriptor(Struct): pass +const_struct_WGPURenderPipelineDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('layout', WGPUPipelineLayout), + ('vertex', WGPUVertexState), + ('primitive', WGPUPrimitiveState), + ('depthStencil', ctypes.POINTER(WGPUDepthStencilState)), + ('multisample', WGPUMultisampleState), + ('fragment', ctypes.POINTER(WGPUFragmentState)), +] +WGPUProcDeviceCreateRenderPipeline = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderPipelineImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPURenderPipelineDescriptor)) +WGPUProcDeviceCreateRenderPipelineAsync = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPURenderPipelineDescriptor), ctypes.CFUNCTYPE(None, enum_WGPUCreatePipelineAsyncStatus, ctypes.POINTER(struct_WGPURenderPipelineImpl), struct_WGPUStringView, ctypes.c_void_p), ctypes.c_void_p) +WGPUProcDeviceCreateRenderPipelineAsync2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPURenderPipelineDescriptor), struct_WGPUCreateRenderPipelineAsyncCallbackInfo2) +WGPUProcDeviceCreateRenderPipelineAsyncF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPURenderPipelineDescriptor), struct_WGPUCreateRenderPipelineAsyncCallbackInfo) +class const_struct_WGPUSamplerDescriptor(Struct): pass +const_struct_WGPUSamplerDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('addressModeU', WGPUAddressMode), + ('addressModeV', WGPUAddressMode), + ('addressModeW', WGPUAddressMode), + ('magFilter', WGPUFilterMode), + ('minFilter', WGPUFilterMode), + ('mipmapFilter', WGPUMipmapFilterMode), + ('lodMinClamp', ctypes.c_float), + ('lodMaxClamp', ctypes.c_float), + ('compare', WGPUCompareFunction), + ('maxAnisotropy', uint16_t), +] +WGPUProcDeviceCreateSampler = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSamplerImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUSamplerDescriptor)) +WGPUProcDeviceCreateShaderModule = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUShaderModuleDescriptor)) +WGPUProcDeviceCreateTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUTextureDescriptor)) WGPUProcDeviceDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceForceLoss = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUDeviceLostReason, struct_WGPUStringView) -WGPUProcDeviceGetAHardwareBufferProperties = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(None), ctypes.POINTER(struct_WGPUAHardwareBufferProperties)) +WGPUProcDeviceForceLoss = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), enum_WGPUDeviceLostReason, struct_WGPUStringView) +WGPUProcDeviceGetAHardwareBufferProperties = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.c_void_p, ctypes.POINTER(struct_WGPUAHardwareBufferProperties)) WGPUProcDeviceGetAdapter = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceGetAdapterInfo = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUAdapterInfo)) +WGPUProcDeviceGetAdapterInfo = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUAdapterInfo)) WGPUProcDeviceGetFeatures = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSupportedFeatures)) -WGPUProcDeviceGetLimits = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSupportedLimits)) +WGPUProcDeviceGetLimits = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSupportedLimits)) WGPUProcDeviceGetLostFuture = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl)) WGPUProcDeviceGetQueue = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceHasFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUFeatureName) -WGPUProcDeviceImportSharedBufferMemory = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryDescriptor)) -WGPUProcDeviceImportSharedFence = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedFenceImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSharedFenceDescriptor)) -WGPUProcDeviceImportSharedTextureMemory = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryDescriptor)) -WGPUProcDeviceInjectError = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUErrorType, struct_WGPUStringView) -WGPUProcDevicePopErrorScope = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.CFUNCTYPE(None, WGPUErrorType, struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) +WGPUProcDeviceHasFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUDeviceImpl), enum_WGPUFeatureName) +class const_struct_WGPUSharedBufferMemoryDescriptor(Struct): pass +const_struct_WGPUSharedBufferMemoryDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcDeviceImportSharedBufferMemory = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUSharedBufferMemoryDescriptor)) +class const_struct_WGPUSharedFenceDescriptor(Struct): pass +const_struct_WGPUSharedFenceDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcDeviceImportSharedFence = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedFenceImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUSharedFenceDescriptor)) +class const_struct_WGPUSharedTextureMemoryDescriptor(Struct): pass +const_struct_WGPUSharedTextureMemoryDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcDeviceImportSharedTextureMemory = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUSharedTextureMemoryDescriptor)) +WGPUProcDeviceInjectError = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), enum_WGPUErrorType, struct_WGPUStringView) +WGPUProcDevicePopErrorScope = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.CFUNCTYPE(None, enum_WGPUErrorType, struct_WGPUStringView, ctypes.c_void_p), ctypes.c_void_p) WGPUProcDevicePopErrorScope2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUPopErrorScopeCallbackInfo2) WGPUProcDevicePopErrorScopeF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUPopErrorScopeCallbackInfo) -WGPUProcDevicePushErrorScope = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), WGPUErrorFilter) +WGPUProcDevicePushErrorScope = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), enum_WGPUErrorFilter) WGPUProcDeviceSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), struct_WGPUStringView) -WGPUProcDeviceSetLoggingCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.CFUNCTYPE(None, WGPULoggingType, struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) +WGPUProcDeviceSetLoggingCallback = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.CFUNCTYPE(None, enum_WGPULoggingType, struct_WGPUStringView, ctypes.c_void_p), ctypes.c_void_p) WGPUProcDeviceTick = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) -WGPUProcDeviceValidateTextureDescriptor = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) +WGPUProcDeviceValidateTextureDescriptor = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl), ctypes.POINTER(const_struct_WGPUTextureDescriptor)) WGPUProcDeviceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) WGPUProcDeviceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUDeviceImpl)) WGPUProcExternalTextureDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) @@ -4101,14 +2593,29 @@ WGPUProcExternalTextureRefresh = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WG WGPUProcExternalTextureSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl), struct_WGPUStringView) WGPUProcExternalTextureAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) WGPUProcExternalTextureRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUExternalTextureImpl)) -WGPUProcInstanceCreateSurface = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPUSurfaceDescriptor)) -WGPUProcInstanceEnumerateWGSLLanguageFeatures = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(WGPUWGSLFeatureName)) -WGPUProcInstanceHasWGSLLanguageFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUInstanceImpl), WGPUWGSLFeatureName) +class const_struct_WGPUSurfaceDescriptor(Struct): pass +const_struct_WGPUSurfaceDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcInstanceCreateSurface = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(const_struct_WGPUSurfaceDescriptor)) +WGPUProcInstanceEnumerateWGSLLanguageFeatures = ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(enum_WGPUWGSLFeatureName)) +WGPUProcInstanceHasWGSLLanguageFeature = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUInstanceImpl), enum_WGPUWGSLFeatureName) WGPUProcInstanceProcessEvents = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl)) -WGPUProcInstanceRequestAdapter = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPURequestAdapterOptions), ctypes.CFUNCTYPE(None, WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.POINTER(None)), ctypes.POINTER(None)) -WGPUProcInstanceRequestAdapter2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPURequestAdapterOptions), struct_WGPURequestAdapterCallbackInfo2) -WGPUProcInstanceRequestAdapterF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(struct_WGPURequestAdapterOptions), struct_WGPURequestAdapterCallbackInfo) -WGPUProcInstanceWaitAny = ctypes.CFUNCTYPE(WGPUWaitStatus, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.c_uint64, ctypes.POINTER(struct_WGPUFutureWaitInfo), ctypes.c_uint64) +class const_struct_WGPURequestAdapterOptions(Struct): pass +const_struct_WGPURequestAdapterOptions._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('compatibleSurface', WGPUSurface), + ('featureLevel', WGPUFeatureLevel), + ('powerPreference', WGPUPowerPreference), + ('backendType', WGPUBackendType), + ('forceFallbackAdapter', WGPUBool), + ('compatibilityMode', WGPUBool), +] +WGPUProcInstanceRequestAdapter = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(const_struct_WGPURequestAdapterOptions), ctypes.CFUNCTYPE(None, enum_WGPURequestAdapterStatus, ctypes.POINTER(struct_WGPUAdapterImpl), struct_WGPUStringView, ctypes.c_void_p), ctypes.c_void_p) +WGPUProcInstanceRequestAdapter2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(const_struct_WGPURequestAdapterOptions), struct_WGPURequestAdapterCallbackInfo2) +WGPUProcInstanceRequestAdapterF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.POINTER(const_struct_WGPURequestAdapterOptions), struct_WGPURequestAdapterCallbackInfo) +WGPUProcInstanceWaitAny = ctypes.CFUNCTYPE(enum_WGPUWaitStatus, ctypes.POINTER(struct_WGPUInstanceImpl), ctypes.c_uint64, ctypes.POINTER(struct_WGPUFutureWaitInfo), ctypes.c_uint64) WGPUProcInstanceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl)) WGPUProcInstanceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUInstanceImpl)) WGPUProcPipelineLayoutSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUPipelineLayoutImpl), struct_WGPUStringView) @@ -4116,19 +2623,45 @@ WGPUProcPipelineLayoutAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPU WGPUProcPipelineLayoutRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUPipelineLayoutImpl)) WGPUProcQuerySetDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl)) WGPUProcQuerySetGetCount = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQuerySetGetType = ctypes.CFUNCTYPE(WGPUQueryType, ctypes.POINTER(struct_WGPUQuerySetImpl)) +WGPUProcQuerySetGetType = ctypes.CFUNCTYPE(enum_WGPUQueryType, ctypes.POINTER(struct_WGPUQuerySetImpl)) WGPUProcQuerySetSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl), struct_WGPUStringView) WGPUProcQuerySetAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl)) WGPUProcQuerySetRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQuerySetImpl)) -WGPUProcQueueCopyExternalTextureForBrowser = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUImageCopyExternalTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)) -WGPUProcQueueCopyTextureForBrowser = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)) -WGPUProcQueueOnSubmittedWorkDone = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.CFUNCTYPE(None, WGPUQueueWorkDoneStatus, ctypes.POINTER(None)), ctypes.POINTER(None)) +class const_struct_WGPUImageCopyExternalTexture(Struct): pass +const_struct_WGPUImageCopyExternalTexture._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('externalTexture', WGPUExternalTexture), + ('origin', WGPUOrigin3D), + ('naturalSize', WGPUExtent2D), +] +class const_struct_WGPUCopyTextureForBrowserOptions(Struct): pass +const_struct_WGPUCopyTextureForBrowserOptions._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('flipY', WGPUBool), + ('needsColorSpaceConversion', WGPUBool), + ('srcAlphaMode', WGPUAlphaMode), + ('srcTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('conversionMatrix', ctypes.POINTER(ctypes.c_float)), + ('dstTransferFunctionParameters', ctypes.POINTER(ctypes.c_float)), + ('dstAlphaMode', WGPUAlphaMode), + ('internalUsage', WGPUBool), +] +WGPUProcQueueCopyExternalTextureForBrowser = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(const_struct_WGPUImageCopyExternalTexture), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUExtent3D), ctypes.POINTER(const_struct_WGPUCopyTextureForBrowserOptions)) +WGPUProcQueueCopyTextureForBrowser = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.POINTER(const_struct_WGPUExtent3D), ctypes.POINTER(const_struct_WGPUCopyTextureForBrowserOptions)) +WGPUProcQueueOnSubmittedWorkDone = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.CFUNCTYPE(None, enum_WGPUQueueWorkDoneStatus, ctypes.c_void_p), ctypes.c_void_p) WGPUProcQueueOnSubmittedWorkDone2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUQueueImpl), struct_WGPUQueueWorkDoneCallbackInfo2) WGPUProcQueueOnSubmittedWorkDoneF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUQueueImpl), struct_WGPUQueueWorkDoneCallbackInfo) WGPUProcQueueSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), struct_WGPUStringView) WGPUProcQueueSubmit = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.POINTER(struct_WGPUCommandBufferImpl))) -WGPUProcQueueWriteBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64) -WGPUProcQueueWriteTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(None), ctypes.c_uint64, ctypes.POINTER(struct_WGPUTextureDataLayout), ctypes.POINTER(struct_WGPUExtent3D)) +WGPUProcQueueWriteBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_void_p, ctypes.c_uint64) +class const_struct_WGPUTextureDataLayout(Struct): pass +const_struct_WGPUTextureDataLayout._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('offset', uint64_t), + ('bytesPerRow', uint32_t), + ('rowsPerImage', uint32_t), +] +WGPUProcQueueWriteTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl), ctypes.POINTER(const_struct_WGPUImageCopyTexture), ctypes.c_void_p, ctypes.c_uint64, ctypes.POINTER(const_struct_WGPUTextureDataLayout), ctypes.POINTER(const_struct_WGPUExtent3D)) WGPUProcQueueAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl)) WGPUProcQueueRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUQueueImpl)) WGPUProcRenderBundleSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleImpl), struct_WGPUStringView) @@ -4138,12 +2671,17 @@ WGPUProcRenderBundleEncoderDraw = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_W WGPUProcRenderBundleEncoderDrawIndexed = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_int32, ctypes.c_uint32) WGPUProcRenderBundleEncoderDrawIndexedIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) WGPUProcRenderBundleEncoderDrawIndirect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64) -WGPUProcRenderBundleEncoderFinish = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderBundleImpl), ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPURenderBundleDescriptor)) +class const_struct_WGPURenderBundleDescriptor(Struct): pass +const_struct_WGPURenderBundleDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), +] +WGPUProcRenderBundleEncoderFinish = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPURenderBundleImpl), ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(const_struct_WGPURenderBundleDescriptor)) WGPUProcRenderBundleEncoderInsertDebugMarker = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), struct_WGPUStringView) WGPUProcRenderBundleEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl)) WGPUProcRenderBundleEncoderPushDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), struct_WGPUStringView) WGPUProcRenderBundleEncoderSetBindGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint32)) -WGPUProcRenderBundleEncoderSetIndexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), WGPUIndexFormat, ctypes.c_uint64, ctypes.c_uint64) +WGPUProcRenderBundleEncoderSetIndexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), enum_WGPUIndexFormat, ctypes.c_uint64, ctypes.c_uint64) WGPUProcRenderBundleEncoderSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), struct_WGPUStringView) WGPUProcRenderBundleEncoderSetPipeline = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.POINTER(struct_WGPURenderPipelineImpl)) WGPUProcRenderBundleEncoderSetVertexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderBundleEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBufferImpl), ctypes.c_uint64, ctypes.c_uint64) @@ -4164,8 +2702,15 @@ WGPUProcRenderPassEncoderPixelLocalStorageBarrier = ctypes.CFUNCTYPE(None, ctype WGPUProcRenderPassEncoderPopDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl)) WGPUProcRenderPassEncoderPushDebugGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), struct_WGPUStringView) WGPUProcRenderPassEncoderSetBindGroup = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.POINTER(struct_WGPUBindGroupImpl), ctypes.c_uint64, ctypes.POINTER(ctypes.c_uint32)) -WGPUProcRenderPassEncoderSetBlendConstant = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUColor)) -WGPUProcRenderPassEncoderSetIndexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), WGPUIndexFormat, ctypes.c_uint64, ctypes.c_uint64) +class const_struct_WGPUColor(Struct): pass +const_struct_WGPUColor._fields_ = [ + ('r', ctypes.c_double), + ('g', ctypes.c_double), + ('b', ctypes.c_double), + ('a', ctypes.c_double), +] +WGPUProcRenderPassEncoderSetBlendConstant = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(const_struct_WGPUColor)) +WGPUProcRenderPassEncoderSetIndexBuffer = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPUBufferImpl), enum_WGPUIndexFormat, ctypes.c_uint64, ctypes.c_uint64) WGPUProcRenderPassEncoderSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), struct_WGPUStringView) WGPUProcRenderPassEncoderSetPipeline = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.POINTER(struct_WGPURenderPipelineImpl)) WGPUProcRenderPassEncoderSetScissorRect = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPURenderPassEncoderImpl), ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32) @@ -4182,16 +2727,24 @@ WGPUProcRenderPipelineRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGP WGPUProcSamplerSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSamplerImpl), struct_WGPUStringView) WGPUProcSamplerAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSamplerImpl)) WGPUProcSamplerRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSamplerImpl)) -WGPUProcShaderModuleGetCompilationInfo = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.CFUNCTYPE(None, WGPUCompilationInfoRequestStatus, ctypes.POINTER(struct_WGPUCompilationInfo), ctypes.POINTER(None)), ctypes.POINTER(None)) +WGPUProcShaderModuleGetCompilationInfo = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl), ctypes.CFUNCTYPE(None, enum_WGPUCompilationInfoRequestStatus, ctypes.POINTER(const_struct_WGPUCompilationInfo), ctypes.c_void_p), ctypes.c_void_p) WGPUProcShaderModuleGetCompilationInfo2 = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUShaderModuleImpl), struct_WGPUCompilationInfoCallbackInfo2) WGPUProcShaderModuleGetCompilationInfoF = ctypes.CFUNCTYPE(struct_WGPUFuture, ctypes.POINTER(struct_WGPUShaderModuleImpl), struct_WGPUCompilationInfoCallbackInfo) WGPUProcShaderModuleSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl), struct_WGPUStringView) WGPUProcShaderModuleAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl)) WGPUProcShaderModuleRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUShaderModuleImpl)) -WGPUProcSharedBufferMemoryBeginAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryBeginAccessDescriptor)) -WGPUProcSharedBufferMemoryCreateBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferDescriptor)) -WGPUProcSharedBufferMemoryEndAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryEndAccessState)) -WGPUProcSharedBufferMemoryGetProperties = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryProperties)) +class const_struct_WGPUSharedBufferMemoryBeginAccessDescriptor(Struct): pass +const_struct_WGPUSharedBufferMemoryBeginAccessDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('initialized', WGPUBool), + ('fenceCount', size_t), + ('fences', ctypes.POINTER(WGPUSharedFence)), + ('signaledValues', ctypes.POINTER(uint64_t)), +] +WGPUProcSharedBufferMemoryBeginAccess = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(const_struct_WGPUSharedBufferMemoryBeginAccessDescriptor)) +WGPUProcSharedBufferMemoryCreateBuffer = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(const_struct_WGPUBufferDescriptor)) +WGPUProcSharedBufferMemoryEndAccess = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUBufferImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryEndAccessState)) +WGPUProcSharedBufferMemoryGetProperties = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), ctypes.POINTER(struct_WGPUSharedBufferMemoryProperties)) WGPUProcSharedBufferMemoryIsDeviceLost = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl)) WGPUProcSharedBufferMemorySetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl), struct_WGPUStringView) WGPUProcSharedBufferMemoryAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedBufferMemoryImpl)) @@ -4199,28 +2752,63 @@ WGPUProcSharedBufferMemoryRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct WGPUProcSharedFenceExportInfo = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedFenceImpl), ctypes.POINTER(struct_WGPUSharedFenceExportInfo)) WGPUProcSharedFenceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedFenceImpl)) WGPUProcSharedFenceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedFenceImpl)) -WGPUProcSharedTextureMemoryBeginAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryBeginAccessDescriptor)) -WGPUProcSharedTextureMemoryCreateTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureDescriptor)) -WGPUProcSharedTextureMemoryEndAccess = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryEndAccessState)) -WGPUProcSharedTextureMemoryGetProperties = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryProperties)) +class const_struct_WGPUSharedTextureMemoryBeginAccessDescriptor(Struct): pass +const_struct_WGPUSharedTextureMemoryBeginAccessDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('concurrentRead', WGPUBool), + ('initialized', WGPUBool), + ('fenceCount', size_t), + ('fences', ctypes.POINTER(WGPUSharedFence)), + ('signaledValues', ctypes.POINTER(uint64_t)), +] +WGPUProcSharedTextureMemoryBeginAccess = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(const_struct_WGPUSharedTextureMemoryBeginAccessDescriptor)) +WGPUProcSharedTextureMemoryCreateTexture = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(const_struct_WGPUTextureDescriptor)) +WGPUProcSharedTextureMemoryEndAccess = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryEndAccessState)) +WGPUProcSharedTextureMemoryGetProperties = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), ctypes.POINTER(struct_WGPUSharedTextureMemoryProperties)) WGPUProcSharedTextureMemoryIsDeviceLost = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl)) WGPUProcSharedTextureMemorySetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl), struct_WGPUStringView) WGPUProcSharedTextureMemoryAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl)) WGPUProcSharedTextureMemoryRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSharedTextureMemoryImpl)) -WGPUProcSurfaceConfigure = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUSurfaceConfiguration)) -WGPUProcSurfaceGetCapabilities = ctypes.CFUNCTYPE(WGPUStatus, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSurfaceCapabilities)) +class const_struct_WGPUSurfaceConfiguration(Struct): pass +const_struct_WGPUSurfaceConfiguration._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('device', WGPUDevice), + ('format', WGPUTextureFormat), + ('usage', WGPUTextureUsage), + ('viewFormatCount', size_t), + ('viewFormats', ctypes.POINTER(WGPUTextureFormat)), + ('alphaMode', WGPUCompositeAlphaMode), + ('width', uint32_t), + ('height', uint32_t), + ('presentMode', WGPUPresentMode), +] +WGPUProcSurfaceConfigure = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(const_struct_WGPUSurfaceConfiguration)) +WGPUProcSurfaceGetCapabilities = ctypes.CFUNCTYPE(enum_WGPUStatus, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUAdapterImpl), ctypes.POINTER(struct_WGPUSurfaceCapabilities)) WGPUProcSurfaceGetCurrentTexture = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), ctypes.POINTER(struct_WGPUSurfaceTexture)) WGPUProcSurfacePresent = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) WGPUProcSurfaceSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl), struct_WGPUStringView) WGPUProcSurfaceUnconfigure = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) WGPUProcSurfaceAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) WGPUProcSurfaceRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUSurfaceImpl)) -WGPUProcTextureCreateErrorView = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureViewImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUTextureViewDescriptor)) -WGPUProcTextureCreateView = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureViewImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(struct_WGPUTextureViewDescriptor)) +class const_struct_WGPUTextureViewDescriptor(Struct): pass +const_struct_WGPUTextureViewDescriptor._fields_ = [ + ('nextInChain', ctypes.POINTER(WGPUChainedStruct)), + ('label', WGPUStringView), + ('format', WGPUTextureFormat), + ('dimension', WGPUTextureViewDimension), + ('baseMipLevel', uint32_t), + ('mipLevelCount', uint32_t), + ('baseArrayLayer', uint32_t), + ('arrayLayerCount', uint32_t), + ('aspect', WGPUTextureAspect), + ('usage', WGPUTextureUsage), +] +WGPUProcTextureCreateErrorView = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureViewImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(const_struct_WGPUTextureViewDescriptor)) +WGPUProcTextureCreateView = ctypes.CFUNCTYPE(ctypes.POINTER(struct_WGPUTextureViewImpl), ctypes.POINTER(struct_WGPUTextureImpl), ctypes.POINTER(const_struct_WGPUTextureViewDescriptor)) WGPUProcTextureDestroy = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureImpl)) WGPUProcTextureGetDepthOrArrayLayers = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetDimension = ctypes.CFUNCTYPE(WGPUTextureDimension, ctypes.POINTER(struct_WGPUTextureImpl)) -WGPUProcTextureGetFormat = ctypes.CFUNCTYPE(WGPUTextureFormat, ctypes.POINTER(struct_WGPUTextureImpl)) +WGPUProcTextureGetDimension = ctypes.CFUNCTYPE(enum_WGPUTextureDimension, ctypes.POINTER(struct_WGPUTextureImpl)) +WGPUProcTextureGetFormat = ctypes.CFUNCTYPE(enum_WGPUTextureFormat, ctypes.POINTER(struct_WGPUTextureImpl)) WGPUProcTextureGetHeight = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) WGPUProcTextureGetMipLevelCount = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) WGPUProcTextureGetSampleCount = ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_WGPUTextureImpl)) @@ -4232,2765 +2820,1089 @@ WGPUProcTextureRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextur WGPUProcTextureViewSetLabel = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureViewImpl), struct_WGPUStringView) WGPUProcTextureViewAddRef = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureViewImpl)) WGPUProcTextureViewRelease = ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_WGPUTextureViewImpl)) -try: - wgpuAdapterInfoFreeMembers = _libraries['webgpu'].wgpuAdapterInfoFreeMembers - wgpuAdapterInfoFreeMembers.restype = None - wgpuAdapterInfoFreeMembers.argtypes = [WGPUAdapterInfo] -except AttributeError: - pass -try: - wgpuAdapterPropertiesMemoryHeapsFreeMembers = _libraries['webgpu'].wgpuAdapterPropertiesMemoryHeapsFreeMembers - wgpuAdapterPropertiesMemoryHeapsFreeMembers.restype = None - wgpuAdapterPropertiesMemoryHeapsFreeMembers.argtypes = [WGPUAdapterPropertiesMemoryHeaps] -except AttributeError: - pass -try: - wgpuCreateInstance = _libraries['webgpu'].wgpuCreateInstance - wgpuCreateInstance.restype = WGPUInstance - wgpuCreateInstance.argtypes = [ctypes.POINTER(struct_WGPUInstanceDescriptor)] -except AttributeError: - pass -try: - wgpuDrmFormatCapabilitiesFreeMembers = _libraries['webgpu'].wgpuDrmFormatCapabilitiesFreeMembers - wgpuDrmFormatCapabilitiesFreeMembers.restype = None - wgpuDrmFormatCapabilitiesFreeMembers.argtypes = [WGPUDrmFormatCapabilities] -except AttributeError: - pass -try: - wgpuGetInstanceFeatures = _libraries['webgpu'].wgpuGetInstanceFeatures - wgpuGetInstanceFeatures.restype = WGPUStatus - wgpuGetInstanceFeatures.argtypes = [ctypes.POINTER(struct_WGPUInstanceFeatures)] -except AttributeError: - pass -try: - wgpuGetProcAddress = _libraries['webgpu'].wgpuGetProcAddress - wgpuGetProcAddress.restype = WGPUProc - wgpuGetProcAddress.argtypes = [WGPUStringView] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryEndAccessStateFreeMembers = _libraries['webgpu'].wgpuSharedBufferMemoryEndAccessStateFreeMembers - wgpuSharedBufferMemoryEndAccessStateFreeMembers.restype = None - wgpuSharedBufferMemoryEndAccessStateFreeMembers.argtypes = [WGPUSharedBufferMemoryEndAccessState] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryEndAccessStateFreeMembers = _libraries['webgpu'].wgpuSharedTextureMemoryEndAccessStateFreeMembers - wgpuSharedTextureMemoryEndAccessStateFreeMembers.restype = None - wgpuSharedTextureMemoryEndAccessStateFreeMembers.argtypes = [WGPUSharedTextureMemoryEndAccessState] -except AttributeError: - pass -try: - wgpuSupportedFeaturesFreeMembers = _libraries['webgpu'].wgpuSupportedFeaturesFreeMembers - wgpuSupportedFeaturesFreeMembers.restype = None - wgpuSupportedFeaturesFreeMembers.argtypes = [WGPUSupportedFeatures] -except AttributeError: - pass -try: - wgpuSurfaceCapabilitiesFreeMembers = _libraries['webgpu'].wgpuSurfaceCapabilitiesFreeMembers - wgpuSurfaceCapabilitiesFreeMembers.restype = None - wgpuSurfaceCapabilitiesFreeMembers.argtypes = [WGPUSurfaceCapabilities] -except AttributeError: - pass -try: - wgpuAdapterCreateDevice = _libraries['webgpu'].wgpuAdapterCreateDevice - wgpuAdapterCreateDevice.restype = WGPUDevice - wgpuAdapterCreateDevice.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor)] -except AttributeError: - pass -try: - wgpuAdapterGetFeatures = _libraries['webgpu'].wgpuAdapterGetFeatures - wgpuAdapterGetFeatures.restype = None - wgpuAdapterGetFeatures.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUSupportedFeatures)] -except AttributeError: - pass -try: - wgpuAdapterGetFormatCapabilities = _libraries['webgpu'].wgpuAdapterGetFormatCapabilities - wgpuAdapterGetFormatCapabilities.restype = WGPUStatus - wgpuAdapterGetFormatCapabilities.argtypes = [WGPUAdapter, WGPUTextureFormat, ctypes.POINTER(struct_WGPUFormatCapabilities)] -except AttributeError: - pass -try: - wgpuAdapterGetInfo = _libraries['webgpu'].wgpuAdapterGetInfo - wgpuAdapterGetInfo.restype = WGPUStatus - wgpuAdapterGetInfo.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUAdapterInfo)] -except AttributeError: - pass -try: - wgpuAdapterGetInstance = _libraries['webgpu'].wgpuAdapterGetInstance - wgpuAdapterGetInstance.restype = WGPUInstance - wgpuAdapterGetInstance.argtypes = [WGPUAdapter] -except AttributeError: - pass -try: - wgpuAdapterGetLimits = _libraries['webgpu'].wgpuAdapterGetLimits - wgpuAdapterGetLimits.restype = WGPUStatus - wgpuAdapterGetLimits.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUSupportedLimits)] -except AttributeError: - pass -try: - wgpuAdapterHasFeature = _libraries['webgpu'].wgpuAdapterHasFeature - wgpuAdapterHasFeature.restype = WGPUBool - wgpuAdapterHasFeature.argtypes = [WGPUAdapter, WGPUFeatureName] -except AttributeError: - pass -try: - wgpuAdapterRequestDevice = _libraries['webgpu'].wgpuAdapterRequestDevice - wgpuAdapterRequestDevice.restype = None - wgpuAdapterRequestDevice.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor), WGPURequestDeviceCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuAdapterRequestDevice2 = _libraries['webgpu'].wgpuAdapterRequestDevice2 - wgpuAdapterRequestDevice2.restype = WGPUFuture - wgpuAdapterRequestDevice2.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor), WGPURequestDeviceCallbackInfo2] -except AttributeError: - pass -try: - wgpuAdapterRequestDeviceF = _libraries['webgpu'].wgpuAdapterRequestDeviceF - wgpuAdapterRequestDeviceF.restype = WGPUFuture - wgpuAdapterRequestDeviceF.argtypes = [WGPUAdapter, ctypes.POINTER(struct_WGPUDeviceDescriptor), WGPURequestDeviceCallbackInfo] -except AttributeError: - pass -try: - wgpuAdapterAddRef = _libraries['webgpu'].wgpuAdapterAddRef - wgpuAdapterAddRef.restype = None - wgpuAdapterAddRef.argtypes = [WGPUAdapter] -except AttributeError: - pass -try: - wgpuAdapterRelease = _libraries['webgpu'].wgpuAdapterRelease - wgpuAdapterRelease.restype = None - wgpuAdapterRelease.argtypes = [WGPUAdapter] -except AttributeError: - pass -try: - wgpuBindGroupSetLabel = _libraries['webgpu'].wgpuBindGroupSetLabel - wgpuBindGroupSetLabel.restype = None - wgpuBindGroupSetLabel.argtypes = [WGPUBindGroup, WGPUStringView] -except AttributeError: - pass -try: - wgpuBindGroupAddRef = _libraries['webgpu'].wgpuBindGroupAddRef - wgpuBindGroupAddRef.restype = None - wgpuBindGroupAddRef.argtypes = [WGPUBindGroup] -except AttributeError: - pass -try: - wgpuBindGroupRelease = _libraries['webgpu'].wgpuBindGroupRelease - wgpuBindGroupRelease.restype = None - wgpuBindGroupRelease.argtypes = [WGPUBindGroup] -except AttributeError: - pass -try: - wgpuBindGroupLayoutSetLabel = _libraries['webgpu'].wgpuBindGroupLayoutSetLabel - wgpuBindGroupLayoutSetLabel.restype = None - wgpuBindGroupLayoutSetLabel.argtypes = [WGPUBindGroupLayout, WGPUStringView] -except AttributeError: - pass -try: - wgpuBindGroupLayoutAddRef = _libraries['webgpu'].wgpuBindGroupLayoutAddRef - wgpuBindGroupLayoutAddRef.restype = None - wgpuBindGroupLayoutAddRef.argtypes = [WGPUBindGroupLayout] -except AttributeError: - pass -try: - wgpuBindGroupLayoutRelease = _libraries['webgpu'].wgpuBindGroupLayoutRelease - wgpuBindGroupLayoutRelease.restype = None - wgpuBindGroupLayoutRelease.argtypes = [WGPUBindGroupLayout] -except AttributeError: - pass -try: - wgpuBufferDestroy = _libraries['webgpu'].wgpuBufferDestroy - wgpuBufferDestroy.restype = None - wgpuBufferDestroy.argtypes = [WGPUBuffer] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - wgpuBufferGetConstMappedRange = _libraries['webgpu'].wgpuBufferGetConstMappedRange - wgpuBufferGetConstMappedRange.restype = ctypes.POINTER(None) - wgpuBufferGetConstMappedRange.argtypes = [WGPUBuffer, size_t, size_t] -except AttributeError: - pass -try: - wgpuBufferGetMapState = _libraries['webgpu'].wgpuBufferGetMapState - wgpuBufferGetMapState.restype = WGPUBufferMapState - wgpuBufferGetMapState.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferGetMappedRange = _libraries['webgpu'].wgpuBufferGetMappedRange - wgpuBufferGetMappedRange.restype = ctypes.POINTER(None) - wgpuBufferGetMappedRange.argtypes = [WGPUBuffer, size_t, size_t] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - wgpuBufferGetSize = _libraries['webgpu'].wgpuBufferGetSize - wgpuBufferGetSize.restype = uint64_t - wgpuBufferGetSize.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferGetUsage = _libraries['webgpu'].wgpuBufferGetUsage - wgpuBufferGetUsage.restype = WGPUBufferUsage - wgpuBufferGetUsage.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferMapAsync = _libraries['webgpu'].wgpuBufferMapAsync - wgpuBufferMapAsync.restype = None - wgpuBufferMapAsync.argtypes = [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuBufferMapAsync2 = _libraries['webgpu'].wgpuBufferMapAsync2 - wgpuBufferMapAsync2.restype = WGPUFuture - wgpuBufferMapAsync2.argtypes = [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallbackInfo2] -except AttributeError: - pass -try: - wgpuBufferMapAsyncF = _libraries['webgpu'].wgpuBufferMapAsyncF - wgpuBufferMapAsyncF.restype = WGPUFuture - wgpuBufferMapAsyncF.argtypes = [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallbackInfo] -except AttributeError: - pass -try: - wgpuBufferSetLabel = _libraries['webgpu'].wgpuBufferSetLabel - wgpuBufferSetLabel.restype = None - wgpuBufferSetLabel.argtypes = [WGPUBuffer, WGPUStringView] -except AttributeError: - pass -try: - wgpuBufferUnmap = _libraries['webgpu'].wgpuBufferUnmap - wgpuBufferUnmap.restype = None - wgpuBufferUnmap.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferAddRef = _libraries['webgpu'].wgpuBufferAddRef - wgpuBufferAddRef.restype = None - wgpuBufferAddRef.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuBufferRelease = _libraries['webgpu'].wgpuBufferRelease - wgpuBufferRelease.restype = None - wgpuBufferRelease.argtypes = [WGPUBuffer] -except AttributeError: - pass -try: - wgpuCommandBufferSetLabel = _libraries['webgpu'].wgpuCommandBufferSetLabel - wgpuCommandBufferSetLabel.restype = None - wgpuCommandBufferSetLabel.argtypes = [WGPUCommandBuffer, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandBufferAddRef = _libraries['webgpu'].wgpuCommandBufferAddRef - wgpuCommandBufferAddRef.restype = None - wgpuCommandBufferAddRef.argtypes = [WGPUCommandBuffer] -except AttributeError: - pass -try: - wgpuCommandBufferRelease = _libraries['webgpu'].wgpuCommandBufferRelease - wgpuCommandBufferRelease.restype = None - wgpuCommandBufferRelease.argtypes = [WGPUCommandBuffer] -except AttributeError: - pass -try: - wgpuCommandEncoderBeginComputePass = _libraries['webgpu'].wgpuCommandEncoderBeginComputePass - wgpuCommandEncoderBeginComputePass.restype = WGPUComputePassEncoder - wgpuCommandEncoderBeginComputePass.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUComputePassDescriptor)] -except AttributeError: - pass -try: - wgpuCommandEncoderBeginRenderPass = _libraries['webgpu'].wgpuCommandEncoderBeginRenderPass - wgpuCommandEncoderBeginRenderPass.restype = WGPURenderPassEncoder - wgpuCommandEncoderBeginRenderPass.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPURenderPassDescriptor)] -except AttributeError: - pass -try: - wgpuCommandEncoderClearBuffer = _libraries['webgpu'].wgpuCommandEncoderClearBuffer - wgpuCommandEncoderClearBuffer.restype = None - wgpuCommandEncoderClearBuffer.argtypes = [WGPUCommandEncoder, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyBufferToBuffer = _libraries['webgpu'].wgpuCommandEncoderCopyBufferToBuffer - wgpuCommandEncoderCopyBufferToBuffer.restype = None - wgpuCommandEncoderCopyBufferToBuffer.argtypes = [WGPUCommandEncoder, WGPUBuffer, uint64_t, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyBufferToTexture = _libraries['webgpu'].wgpuCommandEncoderCopyBufferToTexture - wgpuCommandEncoderCopyBufferToTexture.restype = None - wgpuCommandEncoderCopyBufferToTexture.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyTextureToBuffer = _libraries['webgpu'].wgpuCommandEncoderCopyTextureToBuffer - wgpuCommandEncoderCopyTextureToBuffer.restype = None - wgpuCommandEncoderCopyTextureToBuffer.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyBuffer), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuCommandEncoderCopyTextureToTexture = _libraries['webgpu'].wgpuCommandEncoderCopyTextureToTexture - wgpuCommandEncoderCopyTextureToTexture.restype = None - wgpuCommandEncoderCopyTextureToTexture.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuCommandEncoderFinish = _libraries['webgpu'].wgpuCommandEncoderFinish - wgpuCommandEncoderFinish.restype = WGPUCommandBuffer - wgpuCommandEncoderFinish.argtypes = [WGPUCommandEncoder, ctypes.POINTER(struct_WGPUCommandBufferDescriptor)] -except AttributeError: - pass -try: - wgpuCommandEncoderInjectValidationError = _libraries['webgpu'].wgpuCommandEncoderInjectValidationError - wgpuCommandEncoderInjectValidationError.restype = None - wgpuCommandEncoderInjectValidationError.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandEncoderInsertDebugMarker = _libraries['webgpu'].wgpuCommandEncoderInsertDebugMarker - wgpuCommandEncoderInsertDebugMarker.restype = None - wgpuCommandEncoderInsertDebugMarker.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandEncoderPopDebugGroup = _libraries['webgpu'].wgpuCommandEncoderPopDebugGroup - wgpuCommandEncoderPopDebugGroup.restype = None - wgpuCommandEncoderPopDebugGroup.argtypes = [WGPUCommandEncoder] -except AttributeError: - pass -try: - wgpuCommandEncoderPushDebugGroup = _libraries['webgpu'].wgpuCommandEncoderPushDebugGroup - wgpuCommandEncoderPushDebugGroup.restype = None - wgpuCommandEncoderPushDebugGroup.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -try: - wgpuCommandEncoderResolveQuerySet = _libraries['webgpu'].wgpuCommandEncoderResolveQuerySet - wgpuCommandEncoderResolveQuerySet.restype = None - wgpuCommandEncoderResolveQuerySet.argtypes = [WGPUCommandEncoder, WGPUQuerySet, uint32_t, uint32_t, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderSetLabel = _libraries['webgpu'].wgpuCommandEncoderSetLabel - wgpuCommandEncoderSetLabel.restype = None - wgpuCommandEncoderSetLabel.argtypes = [WGPUCommandEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuCommandEncoderWriteBuffer = _libraries['webgpu'].wgpuCommandEncoderWriteBuffer - wgpuCommandEncoderWriteBuffer.restype = None - wgpuCommandEncoderWriteBuffer.argtypes = [WGPUCommandEncoder, WGPUBuffer, uint64_t, ctypes.POINTER(ctypes.c_ubyte), uint64_t] -except AttributeError: - pass -try: - wgpuCommandEncoderWriteTimestamp = _libraries['webgpu'].wgpuCommandEncoderWriteTimestamp - wgpuCommandEncoderWriteTimestamp.restype = None - wgpuCommandEncoderWriteTimestamp.argtypes = [WGPUCommandEncoder, WGPUQuerySet, uint32_t] -except AttributeError: - pass -try: - wgpuCommandEncoderAddRef = _libraries['webgpu'].wgpuCommandEncoderAddRef - wgpuCommandEncoderAddRef.restype = None - wgpuCommandEncoderAddRef.argtypes = [WGPUCommandEncoder] -except AttributeError: - pass -try: - wgpuCommandEncoderRelease = _libraries['webgpu'].wgpuCommandEncoderRelease - wgpuCommandEncoderRelease.restype = None - wgpuCommandEncoderRelease.argtypes = [WGPUCommandEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderDispatchWorkgroups = _libraries['webgpu'].wgpuComputePassEncoderDispatchWorkgroups - wgpuComputePassEncoderDispatchWorkgroups.restype = None - wgpuComputePassEncoderDispatchWorkgroups.argtypes = [WGPUComputePassEncoder, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -try: - wgpuComputePassEncoderDispatchWorkgroupsIndirect = _libraries['webgpu'].wgpuComputePassEncoderDispatchWorkgroupsIndirect - wgpuComputePassEncoderDispatchWorkgroupsIndirect.restype = None - wgpuComputePassEncoderDispatchWorkgroupsIndirect.argtypes = [WGPUComputePassEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuComputePassEncoderEnd = _libraries['webgpu'].wgpuComputePassEncoderEnd - wgpuComputePassEncoderEnd.restype = None - wgpuComputePassEncoderEnd.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderInsertDebugMarker = _libraries['webgpu'].wgpuComputePassEncoderInsertDebugMarker - wgpuComputePassEncoderInsertDebugMarker.restype = None - wgpuComputePassEncoderInsertDebugMarker.argtypes = [WGPUComputePassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePassEncoderPopDebugGroup = _libraries['webgpu'].wgpuComputePassEncoderPopDebugGroup - wgpuComputePassEncoderPopDebugGroup.restype = None - wgpuComputePassEncoderPopDebugGroup.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderPushDebugGroup = _libraries['webgpu'].wgpuComputePassEncoderPushDebugGroup - wgpuComputePassEncoderPushDebugGroup.restype = None - wgpuComputePassEncoderPushDebugGroup.argtypes = [WGPUComputePassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePassEncoderSetBindGroup = _libraries['webgpu'].wgpuComputePassEncoderSetBindGroup - wgpuComputePassEncoderSetBindGroup.restype = None - wgpuComputePassEncoderSetBindGroup.argtypes = [WGPUComputePassEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - wgpuComputePassEncoderSetLabel = _libraries['webgpu'].wgpuComputePassEncoderSetLabel - wgpuComputePassEncoderSetLabel.restype = None - wgpuComputePassEncoderSetLabel.argtypes = [WGPUComputePassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePassEncoderSetPipeline = _libraries['webgpu'].wgpuComputePassEncoderSetPipeline - wgpuComputePassEncoderSetPipeline.restype = None - wgpuComputePassEncoderSetPipeline.argtypes = [WGPUComputePassEncoder, WGPUComputePipeline] -except AttributeError: - pass -try: - wgpuComputePassEncoderWriteTimestamp = _libraries['webgpu'].wgpuComputePassEncoderWriteTimestamp - wgpuComputePassEncoderWriteTimestamp.restype = None - wgpuComputePassEncoderWriteTimestamp.argtypes = [WGPUComputePassEncoder, WGPUQuerySet, uint32_t] -except AttributeError: - pass -try: - wgpuComputePassEncoderAddRef = _libraries['webgpu'].wgpuComputePassEncoderAddRef - wgpuComputePassEncoderAddRef.restype = None - wgpuComputePassEncoderAddRef.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePassEncoderRelease = _libraries['webgpu'].wgpuComputePassEncoderRelease - wgpuComputePassEncoderRelease.restype = None - wgpuComputePassEncoderRelease.argtypes = [WGPUComputePassEncoder] -except AttributeError: - pass -try: - wgpuComputePipelineGetBindGroupLayout = _libraries['webgpu'].wgpuComputePipelineGetBindGroupLayout - wgpuComputePipelineGetBindGroupLayout.restype = WGPUBindGroupLayout - wgpuComputePipelineGetBindGroupLayout.argtypes = [WGPUComputePipeline, uint32_t] -except AttributeError: - pass -try: - wgpuComputePipelineSetLabel = _libraries['webgpu'].wgpuComputePipelineSetLabel - wgpuComputePipelineSetLabel.restype = None - wgpuComputePipelineSetLabel.argtypes = [WGPUComputePipeline, WGPUStringView] -except AttributeError: - pass -try: - wgpuComputePipelineAddRef = _libraries['webgpu'].wgpuComputePipelineAddRef - wgpuComputePipelineAddRef.restype = None - wgpuComputePipelineAddRef.argtypes = [WGPUComputePipeline] -except AttributeError: - pass -try: - wgpuComputePipelineRelease = _libraries['webgpu'].wgpuComputePipelineRelease - wgpuComputePipelineRelease.restype = None - wgpuComputePipelineRelease.argtypes = [WGPUComputePipeline] -except AttributeError: - pass -try: - wgpuDeviceCreateBindGroup = _libraries['webgpu'].wgpuDeviceCreateBindGroup - wgpuDeviceCreateBindGroup.restype = WGPUBindGroup - wgpuDeviceCreateBindGroup.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBindGroupDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateBindGroupLayout = _libraries['webgpu'].wgpuDeviceCreateBindGroupLayout - wgpuDeviceCreateBindGroupLayout.restype = WGPUBindGroupLayout - wgpuDeviceCreateBindGroupLayout.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBindGroupLayoutDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateBuffer = _libraries['webgpu'].wgpuDeviceCreateBuffer - wgpuDeviceCreateBuffer.restype = WGPUBuffer - wgpuDeviceCreateBuffer.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBufferDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateCommandEncoder = _libraries['webgpu'].wgpuDeviceCreateCommandEncoder - wgpuDeviceCreateCommandEncoder.restype = WGPUCommandEncoder - wgpuDeviceCreateCommandEncoder.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUCommandEncoderDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipeline = _libraries['webgpu'].wgpuDeviceCreateComputePipeline - wgpuDeviceCreateComputePipeline.restype = WGPUComputePipeline - wgpuDeviceCreateComputePipeline.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipelineAsync = _libraries['webgpu'].wgpuDeviceCreateComputePipelineAsync - wgpuDeviceCreateComputePipelineAsync.restype = None - wgpuDeviceCreateComputePipelineAsync.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipelineAsync2 = _libraries['webgpu'].wgpuDeviceCreateComputePipelineAsync2 - wgpuDeviceCreateComputePipelineAsync2.restype = WGPUFuture - wgpuDeviceCreateComputePipelineAsync2.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallbackInfo2] -except AttributeError: - pass -try: - wgpuDeviceCreateComputePipelineAsyncF = _libraries['webgpu'].wgpuDeviceCreateComputePipelineAsyncF - wgpuDeviceCreateComputePipelineAsyncF.restype = WGPUFuture - wgpuDeviceCreateComputePipelineAsyncF.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallbackInfo] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorBuffer = _libraries['webgpu'].wgpuDeviceCreateErrorBuffer - wgpuDeviceCreateErrorBuffer.restype = WGPUBuffer - wgpuDeviceCreateErrorBuffer.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUBufferDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorExternalTexture = _libraries['webgpu'].wgpuDeviceCreateErrorExternalTexture - wgpuDeviceCreateErrorExternalTexture.restype = WGPUExternalTexture - wgpuDeviceCreateErrorExternalTexture.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorShaderModule = _libraries['webgpu'].wgpuDeviceCreateErrorShaderModule - wgpuDeviceCreateErrorShaderModule.restype = WGPUShaderModule - wgpuDeviceCreateErrorShaderModule.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUShaderModuleDescriptor), WGPUStringView] -except AttributeError: - pass -try: - wgpuDeviceCreateErrorTexture = _libraries['webgpu'].wgpuDeviceCreateErrorTexture - wgpuDeviceCreateErrorTexture.restype = WGPUTexture - wgpuDeviceCreateErrorTexture.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateExternalTexture = _libraries['webgpu'].wgpuDeviceCreateExternalTexture - wgpuDeviceCreateExternalTexture.restype = WGPUExternalTexture - wgpuDeviceCreateExternalTexture.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUExternalTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreatePipelineLayout = _libraries['webgpu'].wgpuDeviceCreatePipelineLayout - wgpuDeviceCreatePipelineLayout.restype = WGPUPipelineLayout - wgpuDeviceCreatePipelineLayout.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUPipelineLayoutDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateQuerySet = _libraries['webgpu'].wgpuDeviceCreateQuerySet - wgpuDeviceCreateQuerySet.restype = WGPUQuerySet - wgpuDeviceCreateQuerySet.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUQuerySetDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderBundleEncoder = _libraries['webgpu'].wgpuDeviceCreateRenderBundleEncoder - wgpuDeviceCreateRenderBundleEncoder.restype = WGPURenderBundleEncoder - wgpuDeviceCreateRenderBundleEncoder.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderBundleEncoderDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipeline = _libraries['webgpu'].wgpuDeviceCreateRenderPipeline - wgpuDeviceCreateRenderPipeline.restype = WGPURenderPipeline - wgpuDeviceCreateRenderPipeline.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipelineAsync = _libraries['webgpu'].wgpuDeviceCreateRenderPipelineAsync - wgpuDeviceCreateRenderPipelineAsync.restype = None - wgpuDeviceCreateRenderPipelineAsync.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipelineAsync2 = _libraries['webgpu'].wgpuDeviceCreateRenderPipelineAsync2 - wgpuDeviceCreateRenderPipelineAsync2.restype = WGPUFuture - wgpuDeviceCreateRenderPipelineAsync2.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallbackInfo2] -except AttributeError: - pass -try: - wgpuDeviceCreateRenderPipelineAsyncF = _libraries['webgpu'].wgpuDeviceCreateRenderPipelineAsyncF - wgpuDeviceCreateRenderPipelineAsyncF.restype = WGPUFuture - wgpuDeviceCreateRenderPipelineAsyncF.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallbackInfo] -except AttributeError: - pass -try: - wgpuDeviceCreateSampler = _libraries['webgpu'].wgpuDeviceCreateSampler - wgpuDeviceCreateSampler.restype = WGPUSampler - wgpuDeviceCreateSampler.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSamplerDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateShaderModule = _libraries['webgpu'].wgpuDeviceCreateShaderModule - wgpuDeviceCreateShaderModule.restype = WGPUShaderModule - wgpuDeviceCreateShaderModule.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUShaderModuleDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceCreateTexture = _libraries['webgpu'].wgpuDeviceCreateTexture - wgpuDeviceCreateTexture.restype = WGPUTexture - wgpuDeviceCreateTexture.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceDestroy = _libraries['webgpu'].wgpuDeviceDestroy - wgpuDeviceDestroy.restype = None - wgpuDeviceDestroy.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceForceLoss = _libraries['webgpu'].wgpuDeviceForceLoss - wgpuDeviceForceLoss.restype = None - wgpuDeviceForceLoss.argtypes = [WGPUDevice, WGPUDeviceLostReason, WGPUStringView] -except AttributeError: - pass -try: - wgpuDeviceGetAHardwareBufferProperties = _libraries['webgpu'].wgpuDeviceGetAHardwareBufferProperties - wgpuDeviceGetAHardwareBufferProperties.restype = WGPUStatus - wgpuDeviceGetAHardwareBufferProperties.argtypes = [WGPUDevice, ctypes.POINTER(None), ctypes.POINTER(struct_WGPUAHardwareBufferProperties)] -except AttributeError: - pass -try: - wgpuDeviceGetAdapter = _libraries['webgpu'].wgpuDeviceGetAdapter - wgpuDeviceGetAdapter.restype = WGPUAdapter - wgpuDeviceGetAdapter.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceGetAdapterInfo = _libraries['webgpu'].wgpuDeviceGetAdapterInfo - wgpuDeviceGetAdapterInfo.restype = WGPUStatus - wgpuDeviceGetAdapterInfo.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUAdapterInfo)] -except AttributeError: - pass -try: - wgpuDeviceGetFeatures = _libraries['webgpu'].wgpuDeviceGetFeatures - wgpuDeviceGetFeatures.restype = None - wgpuDeviceGetFeatures.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSupportedFeatures)] -except AttributeError: - pass -try: - wgpuDeviceGetLimits = _libraries['webgpu'].wgpuDeviceGetLimits - wgpuDeviceGetLimits.restype = WGPUStatus - wgpuDeviceGetLimits.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSupportedLimits)] -except AttributeError: - pass -try: - wgpuDeviceGetLostFuture = _libraries['webgpu'].wgpuDeviceGetLostFuture - wgpuDeviceGetLostFuture.restype = WGPUFuture - wgpuDeviceGetLostFuture.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceGetQueue = _libraries['webgpu'].wgpuDeviceGetQueue - wgpuDeviceGetQueue.restype = WGPUQueue - wgpuDeviceGetQueue.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceHasFeature = _libraries['webgpu'].wgpuDeviceHasFeature - wgpuDeviceHasFeature.restype = WGPUBool - wgpuDeviceHasFeature.argtypes = [WGPUDevice, WGPUFeatureName] -except AttributeError: - pass -try: - wgpuDeviceImportSharedBufferMemory = _libraries['webgpu'].wgpuDeviceImportSharedBufferMemory - wgpuDeviceImportSharedBufferMemory.restype = WGPUSharedBufferMemory - wgpuDeviceImportSharedBufferMemory.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSharedBufferMemoryDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceImportSharedFence = _libraries['webgpu'].wgpuDeviceImportSharedFence - wgpuDeviceImportSharedFence.restype = WGPUSharedFence - wgpuDeviceImportSharedFence.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSharedFenceDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceImportSharedTextureMemory = _libraries['webgpu'].wgpuDeviceImportSharedTextureMemory - wgpuDeviceImportSharedTextureMemory.restype = WGPUSharedTextureMemory - wgpuDeviceImportSharedTextureMemory.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUSharedTextureMemoryDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceInjectError = _libraries['webgpu'].wgpuDeviceInjectError - wgpuDeviceInjectError.restype = None - wgpuDeviceInjectError.argtypes = [WGPUDevice, WGPUErrorType, WGPUStringView] -except AttributeError: - pass -try: - wgpuDevicePopErrorScope = _libraries['webgpu'].wgpuDevicePopErrorScope - wgpuDevicePopErrorScope.restype = None - wgpuDevicePopErrorScope.argtypes = [WGPUDevice, WGPUErrorCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDevicePopErrorScope2 = _libraries['webgpu'].wgpuDevicePopErrorScope2 - wgpuDevicePopErrorScope2.restype = WGPUFuture - wgpuDevicePopErrorScope2.argtypes = [WGPUDevice, WGPUPopErrorScopeCallbackInfo2] -except AttributeError: - pass -try: - wgpuDevicePopErrorScopeF = _libraries['webgpu'].wgpuDevicePopErrorScopeF - wgpuDevicePopErrorScopeF.restype = WGPUFuture - wgpuDevicePopErrorScopeF.argtypes = [WGPUDevice, WGPUPopErrorScopeCallbackInfo] -except AttributeError: - pass -try: - wgpuDevicePushErrorScope = _libraries['webgpu'].wgpuDevicePushErrorScope - wgpuDevicePushErrorScope.restype = None - wgpuDevicePushErrorScope.argtypes = [WGPUDevice, WGPUErrorFilter] -except AttributeError: - pass -try: - wgpuDeviceSetLabel = _libraries['webgpu'].wgpuDeviceSetLabel - wgpuDeviceSetLabel.restype = None - wgpuDeviceSetLabel.argtypes = [WGPUDevice, WGPUStringView] -except AttributeError: - pass -try: - wgpuDeviceSetLoggingCallback = _libraries['webgpu'].wgpuDeviceSetLoggingCallback - wgpuDeviceSetLoggingCallback.restype = None - wgpuDeviceSetLoggingCallback.argtypes = [WGPUDevice, WGPULoggingCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuDeviceTick = _libraries['webgpu'].wgpuDeviceTick - wgpuDeviceTick.restype = None - wgpuDeviceTick.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceValidateTextureDescriptor = _libraries['webgpu'].wgpuDeviceValidateTextureDescriptor - wgpuDeviceValidateTextureDescriptor.restype = None - wgpuDeviceValidateTextureDescriptor.argtypes = [WGPUDevice, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuDeviceAddRef = _libraries['webgpu'].wgpuDeviceAddRef - wgpuDeviceAddRef.restype = None - wgpuDeviceAddRef.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuDeviceRelease = _libraries['webgpu'].wgpuDeviceRelease - wgpuDeviceRelease.restype = None - wgpuDeviceRelease.argtypes = [WGPUDevice] -except AttributeError: - pass -try: - wgpuExternalTextureDestroy = _libraries['webgpu'].wgpuExternalTextureDestroy - wgpuExternalTextureDestroy.restype = None - wgpuExternalTextureDestroy.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureExpire = _libraries['webgpu'].wgpuExternalTextureExpire - wgpuExternalTextureExpire.restype = None - wgpuExternalTextureExpire.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureRefresh = _libraries['webgpu'].wgpuExternalTextureRefresh - wgpuExternalTextureRefresh.restype = None - wgpuExternalTextureRefresh.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureSetLabel = _libraries['webgpu'].wgpuExternalTextureSetLabel - wgpuExternalTextureSetLabel.restype = None - wgpuExternalTextureSetLabel.argtypes = [WGPUExternalTexture, WGPUStringView] -except AttributeError: - pass -try: - wgpuExternalTextureAddRef = _libraries['webgpu'].wgpuExternalTextureAddRef - wgpuExternalTextureAddRef.restype = None - wgpuExternalTextureAddRef.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuExternalTextureRelease = _libraries['webgpu'].wgpuExternalTextureRelease - wgpuExternalTextureRelease.restype = None - wgpuExternalTextureRelease.argtypes = [WGPUExternalTexture] -except AttributeError: - pass -try: - wgpuInstanceCreateSurface = _libraries['webgpu'].wgpuInstanceCreateSurface - wgpuInstanceCreateSurface.restype = WGPUSurface - wgpuInstanceCreateSurface.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPUSurfaceDescriptor)] -except AttributeError: - pass -try: - wgpuInstanceEnumerateWGSLLanguageFeatures = _libraries['webgpu'].wgpuInstanceEnumerateWGSLLanguageFeatures - wgpuInstanceEnumerateWGSLLanguageFeatures.restype = size_t - wgpuInstanceEnumerateWGSLLanguageFeatures.argtypes = [WGPUInstance, ctypes.POINTER(WGPUWGSLFeatureName)] -except AttributeError: - pass -try: - wgpuInstanceHasWGSLLanguageFeature = _libraries['webgpu'].wgpuInstanceHasWGSLLanguageFeature - wgpuInstanceHasWGSLLanguageFeature.restype = WGPUBool - wgpuInstanceHasWGSLLanguageFeature.argtypes = [WGPUInstance, WGPUWGSLFeatureName] -except AttributeError: - pass -try: - wgpuInstanceProcessEvents = _libraries['webgpu'].wgpuInstanceProcessEvents - wgpuInstanceProcessEvents.restype = None - wgpuInstanceProcessEvents.argtypes = [WGPUInstance] -except AttributeError: - pass -try: - wgpuInstanceRequestAdapter = _libraries['webgpu'].wgpuInstanceRequestAdapter - wgpuInstanceRequestAdapter.restype = None - wgpuInstanceRequestAdapter.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPURequestAdapterOptions), WGPURequestAdapterCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuInstanceRequestAdapter2 = _libraries['webgpu'].wgpuInstanceRequestAdapter2 - wgpuInstanceRequestAdapter2.restype = WGPUFuture - wgpuInstanceRequestAdapter2.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPURequestAdapterOptions), WGPURequestAdapterCallbackInfo2] -except AttributeError: - pass -try: - wgpuInstanceRequestAdapterF = _libraries['webgpu'].wgpuInstanceRequestAdapterF - wgpuInstanceRequestAdapterF.restype = WGPUFuture - wgpuInstanceRequestAdapterF.argtypes = [WGPUInstance, ctypes.POINTER(struct_WGPURequestAdapterOptions), WGPURequestAdapterCallbackInfo] -except AttributeError: - pass -try: - wgpuInstanceWaitAny = _libraries['webgpu'].wgpuInstanceWaitAny - wgpuInstanceWaitAny.restype = WGPUWaitStatus - wgpuInstanceWaitAny.argtypes = [WGPUInstance, size_t, ctypes.POINTER(struct_WGPUFutureWaitInfo), uint64_t] -except AttributeError: - pass -try: - wgpuInstanceAddRef = _libraries['webgpu'].wgpuInstanceAddRef - wgpuInstanceAddRef.restype = None - wgpuInstanceAddRef.argtypes = [WGPUInstance] -except AttributeError: - pass -try: - wgpuInstanceRelease = _libraries['webgpu'].wgpuInstanceRelease - wgpuInstanceRelease.restype = None - wgpuInstanceRelease.argtypes = [WGPUInstance] -except AttributeError: - pass -try: - wgpuPipelineLayoutSetLabel = _libraries['webgpu'].wgpuPipelineLayoutSetLabel - wgpuPipelineLayoutSetLabel.restype = None - wgpuPipelineLayoutSetLabel.argtypes = [WGPUPipelineLayout, WGPUStringView] -except AttributeError: - pass -try: - wgpuPipelineLayoutAddRef = _libraries['webgpu'].wgpuPipelineLayoutAddRef - wgpuPipelineLayoutAddRef.restype = None - wgpuPipelineLayoutAddRef.argtypes = [WGPUPipelineLayout] -except AttributeError: - pass -try: - wgpuPipelineLayoutRelease = _libraries['webgpu'].wgpuPipelineLayoutRelease - wgpuPipelineLayoutRelease.restype = None - wgpuPipelineLayoutRelease.argtypes = [WGPUPipelineLayout] -except AttributeError: - pass -try: - wgpuQuerySetDestroy = _libraries['webgpu'].wgpuQuerySetDestroy - wgpuQuerySetDestroy.restype = None - wgpuQuerySetDestroy.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetGetCount = _libraries['webgpu'].wgpuQuerySetGetCount - wgpuQuerySetGetCount.restype = uint32_t - wgpuQuerySetGetCount.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetGetType = _libraries['webgpu'].wgpuQuerySetGetType - wgpuQuerySetGetType.restype = WGPUQueryType - wgpuQuerySetGetType.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetSetLabel = _libraries['webgpu'].wgpuQuerySetSetLabel - wgpuQuerySetSetLabel.restype = None - wgpuQuerySetSetLabel.argtypes = [WGPUQuerySet, WGPUStringView] -except AttributeError: - pass -try: - wgpuQuerySetAddRef = _libraries['webgpu'].wgpuQuerySetAddRef - wgpuQuerySetAddRef.restype = None - wgpuQuerySetAddRef.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQuerySetRelease = _libraries['webgpu'].wgpuQuerySetRelease - wgpuQuerySetRelease.restype = None - wgpuQuerySetRelease.argtypes = [WGPUQuerySet] -except AttributeError: - pass -try: - wgpuQueueCopyExternalTextureForBrowser = _libraries['webgpu'].wgpuQueueCopyExternalTextureForBrowser - wgpuQueueCopyExternalTextureForBrowser.restype = None - wgpuQueueCopyExternalTextureForBrowser.argtypes = [WGPUQueue, ctypes.POINTER(struct_WGPUImageCopyExternalTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)] -except AttributeError: - pass -try: - wgpuQueueCopyTextureForBrowser = _libraries['webgpu'].wgpuQueueCopyTextureForBrowser - wgpuQueueCopyTextureForBrowser.restype = None - wgpuQueueCopyTextureForBrowser.argtypes = [WGPUQueue, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(struct_WGPUExtent3D), ctypes.POINTER(struct_WGPUCopyTextureForBrowserOptions)] -except AttributeError: - pass -try: - wgpuQueueOnSubmittedWorkDone = _libraries['webgpu'].wgpuQueueOnSubmittedWorkDone - wgpuQueueOnSubmittedWorkDone.restype = None - wgpuQueueOnSubmittedWorkDone.argtypes = [WGPUQueue, WGPUQueueWorkDoneCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuQueueOnSubmittedWorkDone2 = _libraries['webgpu'].wgpuQueueOnSubmittedWorkDone2 - wgpuQueueOnSubmittedWorkDone2.restype = WGPUFuture - wgpuQueueOnSubmittedWorkDone2.argtypes = [WGPUQueue, WGPUQueueWorkDoneCallbackInfo2] -except AttributeError: - pass -try: - wgpuQueueOnSubmittedWorkDoneF = _libraries['webgpu'].wgpuQueueOnSubmittedWorkDoneF - wgpuQueueOnSubmittedWorkDoneF.restype = WGPUFuture - wgpuQueueOnSubmittedWorkDoneF.argtypes = [WGPUQueue, WGPUQueueWorkDoneCallbackInfo] -except AttributeError: - pass -try: - wgpuQueueSetLabel = _libraries['webgpu'].wgpuQueueSetLabel - wgpuQueueSetLabel.restype = None - wgpuQueueSetLabel.argtypes = [WGPUQueue, WGPUStringView] -except AttributeError: - pass -try: - wgpuQueueSubmit = _libraries['webgpu'].wgpuQueueSubmit - wgpuQueueSubmit.restype = None - wgpuQueueSubmit.argtypes = [WGPUQueue, size_t, ctypes.POINTER(ctypes.POINTER(struct_WGPUCommandBufferImpl))] -except AttributeError: - pass -try: - wgpuQueueWriteBuffer = _libraries['webgpu'].wgpuQueueWriteBuffer - wgpuQueueWriteBuffer.restype = None - wgpuQueueWriteBuffer.argtypes = [WGPUQueue, WGPUBuffer, uint64_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - wgpuQueueWriteTexture = _libraries['webgpu'].wgpuQueueWriteTexture - wgpuQueueWriteTexture.restype = None - wgpuQueueWriteTexture.argtypes = [WGPUQueue, ctypes.POINTER(struct_WGPUImageCopyTexture), ctypes.POINTER(None), size_t, ctypes.POINTER(struct_WGPUTextureDataLayout), ctypes.POINTER(struct_WGPUExtent3D)] -except AttributeError: - pass -try: - wgpuQueueAddRef = _libraries['webgpu'].wgpuQueueAddRef - wgpuQueueAddRef.restype = None - wgpuQueueAddRef.argtypes = [WGPUQueue] -except AttributeError: - pass -try: - wgpuQueueRelease = _libraries['webgpu'].wgpuQueueRelease - wgpuQueueRelease.restype = None - wgpuQueueRelease.argtypes = [WGPUQueue] -except AttributeError: - pass -try: - wgpuRenderBundleSetLabel = _libraries['webgpu'].wgpuRenderBundleSetLabel - wgpuRenderBundleSetLabel.restype = None - wgpuRenderBundleSetLabel.argtypes = [WGPURenderBundle, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleAddRef = _libraries['webgpu'].wgpuRenderBundleAddRef - wgpuRenderBundleAddRef.restype = None - wgpuRenderBundleAddRef.argtypes = [WGPURenderBundle] -except AttributeError: - pass -try: - wgpuRenderBundleRelease = _libraries['webgpu'].wgpuRenderBundleRelease - wgpuRenderBundleRelease.restype = None - wgpuRenderBundleRelease.argtypes = [WGPURenderBundle] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderDraw = _libraries['webgpu'].wgpuRenderBundleEncoderDraw - wgpuRenderBundleEncoderDraw.restype = None - wgpuRenderBundleEncoderDraw.argtypes = [WGPURenderBundleEncoder, uint32_t, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -int32_t = ctypes.c_int32 -try: - wgpuRenderBundleEncoderDrawIndexed = _libraries['webgpu'].wgpuRenderBundleEncoderDrawIndexed - wgpuRenderBundleEncoderDrawIndexed.restype = None - wgpuRenderBundleEncoderDrawIndexed.argtypes = [WGPURenderBundleEncoder, uint32_t, uint32_t, uint32_t, int32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderDrawIndexedIndirect = _libraries['webgpu'].wgpuRenderBundleEncoderDrawIndexedIndirect - wgpuRenderBundleEncoderDrawIndexedIndirect.restype = None - wgpuRenderBundleEncoderDrawIndexedIndirect.argtypes = [WGPURenderBundleEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderDrawIndirect = _libraries['webgpu'].wgpuRenderBundleEncoderDrawIndirect - wgpuRenderBundleEncoderDrawIndirect.restype = None - wgpuRenderBundleEncoderDrawIndirect.argtypes = [WGPURenderBundleEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderFinish = _libraries['webgpu'].wgpuRenderBundleEncoderFinish - wgpuRenderBundleEncoderFinish.restype = WGPURenderBundle - wgpuRenderBundleEncoderFinish.argtypes = [WGPURenderBundleEncoder, ctypes.POINTER(struct_WGPURenderBundleDescriptor)] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderInsertDebugMarker = _libraries['webgpu'].wgpuRenderBundleEncoderInsertDebugMarker - wgpuRenderBundleEncoderInsertDebugMarker.restype = None - wgpuRenderBundleEncoderInsertDebugMarker.argtypes = [WGPURenderBundleEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderPopDebugGroup = _libraries['webgpu'].wgpuRenderBundleEncoderPopDebugGroup - wgpuRenderBundleEncoderPopDebugGroup.restype = None - wgpuRenderBundleEncoderPopDebugGroup.argtypes = [WGPURenderBundleEncoder] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderPushDebugGroup = _libraries['webgpu'].wgpuRenderBundleEncoderPushDebugGroup - wgpuRenderBundleEncoderPushDebugGroup.restype = None - wgpuRenderBundleEncoderPushDebugGroup.argtypes = [WGPURenderBundleEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetBindGroup = _libraries['webgpu'].wgpuRenderBundleEncoderSetBindGroup - wgpuRenderBundleEncoderSetBindGroup.restype = None - wgpuRenderBundleEncoderSetBindGroup.argtypes = [WGPURenderBundleEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetIndexBuffer = _libraries['webgpu'].wgpuRenderBundleEncoderSetIndexBuffer - wgpuRenderBundleEncoderSetIndexBuffer.restype = None - wgpuRenderBundleEncoderSetIndexBuffer.argtypes = [WGPURenderBundleEncoder, WGPUBuffer, WGPUIndexFormat, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetLabel = _libraries['webgpu'].wgpuRenderBundleEncoderSetLabel - wgpuRenderBundleEncoderSetLabel.restype = None - wgpuRenderBundleEncoderSetLabel.argtypes = [WGPURenderBundleEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetPipeline = _libraries['webgpu'].wgpuRenderBundleEncoderSetPipeline - wgpuRenderBundleEncoderSetPipeline.restype = None - wgpuRenderBundleEncoderSetPipeline.argtypes = [WGPURenderBundleEncoder, WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderSetVertexBuffer = _libraries['webgpu'].wgpuRenderBundleEncoderSetVertexBuffer - wgpuRenderBundleEncoderSetVertexBuffer.restype = None - wgpuRenderBundleEncoderSetVertexBuffer.argtypes = [WGPURenderBundleEncoder, uint32_t, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderAddRef = _libraries['webgpu'].wgpuRenderBundleEncoderAddRef - wgpuRenderBundleEncoderAddRef.restype = None - wgpuRenderBundleEncoderAddRef.argtypes = [WGPURenderBundleEncoder] -except AttributeError: - pass -try: - wgpuRenderBundleEncoderRelease = _libraries['webgpu'].wgpuRenderBundleEncoderRelease - wgpuRenderBundleEncoderRelease.restype = None - wgpuRenderBundleEncoderRelease.argtypes = [WGPURenderBundleEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderBeginOcclusionQuery = _libraries['webgpu'].wgpuRenderPassEncoderBeginOcclusionQuery - wgpuRenderPassEncoderBeginOcclusionQuery.restype = None - wgpuRenderPassEncoderBeginOcclusionQuery.argtypes = [WGPURenderPassEncoder, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDraw = _libraries['webgpu'].wgpuRenderPassEncoderDraw - wgpuRenderPassEncoderDraw.restype = None - wgpuRenderPassEncoderDraw.argtypes = [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDrawIndexed = _libraries['webgpu'].wgpuRenderPassEncoderDrawIndexed - wgpuRenderPassEncoderDrawIndexed.restype = None - wgpuRenderPassEncoderDrawIndexed.argtypes = [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, int32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDrawIndexedIndirect = _libraries['webgpu'].wgpuRenderPassEncoderDrawIndexedIndirect - wgpuRenderPassEncoderDrawIndexedIndirect.restype = None - wgpuRenderPassEncoderDrawIndexedIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderDrawIndirect = _libraries['webgpu'].wgpuRenderPassEncoderDrawIndirect - wgpuRenderPassEncoderDrawIndirect.restype = None - wgpuRenderPassEncoderDrawIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderEnd = _libraries['webgpu'].wgpuRenderPassEncoderEnd - wgpuRenderPassEncoderEnd.restype = None - wgpuRenderPassEncoderEnd.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderEndOcclusionQuery = _libraries['webgpu'].wgpuRenderPassEncoderEndOcclusionQuery - wgpuRenderPassEncoderEndOcclusionQuery.restype = None - wgpuRenderPassEncoderEndOcclusionQuery.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderExecuteBundles = _libraries['webgpu'].wgpuRenderPassEncoderExecuteBundles - wgpuRenderPassEncoderExecuteBundles.restype = None - wgpuRenderPassEncoderExecuteBundles.argtypes = [WGPURenderPassEncoder, size_t, ctypes.POINTER(ctypes.POINTER(struct_WGPURenderBundleImpl))] -except AttributeError: - pass -try: - wgpuRenderPassEncoderInsertDebugMarker = _libraries['webgpu'].wgpuRenderPassEncoderInsertDebugMarker - wgpuRenderPassEncoderInsertDebugMarker.restype = None - wgpuRenderPassEncoderInsertDebugMarker.argtypes = [WGPURenderPassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPassEncoderMultiDrawIndexedIndirect = _libraries['webgpu'].wgpuRenderPassEncoderMultiDrawIndexedIndirect - wgpuRenderPassEncoderMultiDrawIndexedIndirect.restype = None - wgpuRenderPassEncoderMultiDrawIndexedIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t, uint32_t, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderMultiDrawIndirect = _libraries['webgpu'].wgpuRenderPassEncoderMultiDrawIndirect - wgpuRenderPassEncoderMultiDrawIndirect.restype = None - wgpuRenderPassEncoderMultiDrawIndirect.argtypes = [WGPURenderPassEncoder, WGPUBuffer, uint64_t, uint32_t, WGPUBuffer, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderPixelLocalStorageBarrier = _libraries['webgpu'].wgpuRenderPassEncoderPixelLocalStorageBarrier - wgpuRenderPassEncoderPixelLocalStorageBarrier.restype = None - wgpuRenderPassEncoderPixelLocalStorageBarrier.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderPopDebugGroup = _libraries['webgpu'].wgpuRenderPassEncoderPopDebugGroup - wgpuRenderPassEncoderPopDebugGroup.restype = None - wgpuRenderPassEncoderPopDebugGroup.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderPushDebugGroup = _libraries['webgpu'].wgpuRenderPassEncoderPushDebugGroup - wgpuRenderPassEncoderPushDebugGroup.restype = None - wgpuRenderPassEncoderPushDebugGroup.argtypes = [WGPURenderPassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetBindGroup = _libraries['webgpu'].wgpuRenderPassEncoderSetBindGroup - wgpuRenderPassEncoderSetBindGroup.restype = None - wgpuRenderPassEncoderSetBindGroup.argtypes = [WGPURenderPassEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetBlendConstant = _libraries['webgpu'].wgpuRenderPassEncoderSetBlendConstant - wgpuRenderPassEncoderSetBlendConstant.restype = None - wgpuRenderPassEncoderSetBlendConstant.argtypes = [WGPURenderPassEncoder, ctypes.POINTER(struct_WGPUColor)] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetIndexBuffer = _libraries['webgpu'].wgpuRenderPassEncoderSetIndexBuffer - wgpuRenderPassEncoderSetIndexBuffer.restype = None - wgpuRenderPassEncoderSetIndexBuffer.argtypes = [WGPURenderPassEncoder, WGPUBuffer, WGPUIndexFormat, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetLabel = _libraries['webgpu'].wgpuRenderPassEncoderSetLabel - wgpuRenderPassEncoderSetLabel.restype = None - wgpuRenderPassEncoderSetLabel.argtypes = [WGPURenderPassEncoder, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetPipeline = _libraries['webgpu'].wgpuRenderPassEncoderSetPipeline - wgpuRenderPassEncoderSetPipeline.restype = None - wgpuRenderPassEncoderSetPipeline.argtypes = [WGPURenderPassEncoder, WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetScissorRect = _libraries['webgpu'].wgpuRenderPassEncoderSetScissorRect - wgpuRenderPassEncoderSetScissorRect.restype = None - wgpuRenderPassEncoderSetScissorRect.argtypes = [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetStencilReference = _libraries['webgpu'].wgpuRenderPassEncoderSetStencilReference - wgpuRenderPassEncoderSetStencilReference.restype = None - wgpuRenderPassEncoderSetStencilReference.argtypes = [WGPURenderPassEncoder, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetVertexBuffer = _libraries['webgpu'].wgpuRenderPassEncoderSetVertexBuffer - wgpuRenderPassEncoderSetVertexBuffer.restype = None - wgpuRenderPassEncoderSetVertexBuffer.argtypes = [WGPURenderPassEncoder, uint32_t, WGPUBuffer, uint64_t, uint64_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderSetViewport = _libraries['webgpu'].wgpuRenderPassEncoderSetViewport - wgpuRenderPassEncoderSetViewport.restype = None - wgpuRenderPassEncoderSetViewport.argtypes = [WGPURenderPassEncoder, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float] -except AttributeError: - pass -try: - wgpuRenderPassEncoderWriteTimestamp = _libraries['webgpu'].wgpuRenderPassEncoderWriteTimestamp - wgpuRenderPassEncoderWriteTimestamp.restype = None - wgpuRenderPassEncoderWriteTimestamp.argtypes = [WGPURenderPassEncoder, WGPUQuerySet, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPassEncoderAddRef = _libraries['webgpu'].wgpuRenderPassEncoderAddRef - wgpuRenderPassEncoderAddRef.restype = None - wgpuRenderPassEncoderAddRef.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPassEncoderRelease = _libraries['webgpu'].wgpuRenderPassEncoderRelease - wgpuRenderPassEncoderRelease.restype = None - wgpuRenderPassEncoderRelease.argtypes = [WGPURenderPassEncoder] -except AttributeError: - pass -try: - wgpuRenderPipelineGetBindGroupLayout = _libraries['webgpu'].wgpuRenderPipelineGetBindGroupLayout - wgpuRenderPipelineGetBindGroupLayout.restype = WGPUBindGroupLayout - wgpuRenderPipelineGetBindGroupLayout.argtypes = [WGPURenderPipeline, uint32_t] -except AttributeError: - pass -try: - wgpuRenderPipelineSetLabel = _libraries['webgpu'].wgpuRenderPipelineSetLabel - wgpuRenderPipelineSetLabel.restype = None - wgpuRenderPipelineSetLabel.argtypes = [WGPURenderPipeline, WGPUStringView] -except AttributeError: - pass -try: - wgpuRenderPipelineAddRef = _libraries['webgpu'].wgpuRenderPipelineAddRef - wgpuRenderPipelineAddRef.restype = None - wgpuRenderPipelineAddRef.argtypes = [WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuRenderPipelineRelease = _libraries['webgpu'].wgpuRenderPipelineRelease - wgpuRenderPipelineRelease.restype = None - wgpuRenderPipelineRelease.argtypes = [WGPURenderPipeline] -except AttributeError: - pass -try: - wgpuSamplerSetLabel = _libraries['webgpu'].wgpuSamplerSetLabel - wgpuSamplerSetLabel.restype = None - wgpuSamplerSetLabel.argtypes = [WGPUSampler, WGPUStringView] -except AttributeError: - pass -try: - wgpuSamplerAddRef = _libraries['webgpu'].wgpuSamplerAddRef - wgpuSamplerAddRef.restype = None - wgpuSamplerAddRef.argtypes = [WGPUSampler] -except AttributeError: - pass -try: - wgpuSamplerRelease = _libraries['webgpu'].wgpuSamplerRelease - wgpuSamplerRelease.restype = None - wgpuSamplerRelease.argtypes = [WGPUSampler] -except AttributeError: - pass -try: - wgpuShaderModuleGetCompilationInfo = _libraries['webgpu'].wgpuShaderModuleGetCompilationInfo - wgpuShaderModuleGetCompilationInfo.restype = None - wgpuShaderModuleGetCompilationInfo.argtypes = [WGPUShaderModule, WGPUCompilationInfoCallback, ctypes.POINTER(None)] -except AttributeError: - pass -try: - wgpuShaderModuleGetCompilationInfo2 = _libraries['webgpu'].wgpuShaderModuleGetCompilationInfo2 - wgpuShaderModuleGetCompilationInfo2.restype = WGPUFuture - wgpuShaderModuleGetCompilationInfo2.argtypes = [WGPUShaderModule, WGPUCompilationInfoCallbackInfo2] -except AttributeError: - pass -try: - wgpuShaderModuleGetCompilationInfoF = _libraries['webgpu'].wgpuShaderModuleGetCompilationInfoF - wgpuShaderModuleGetCompilationInfoF.restype = WGPUFuture - wgpuShaderModuleGetCompilationInfoF.argtypes = [WGPUShaderModule, WGPUCompilationInfoCallbackInfo] -except AttributeError: - pass -try: - wgpuShaderModuleSetLabel = _libraries['webgpu'].wgpuShaderModuleSetLabel - wgpuShaderModuleSetLabel.restype = None - wgpuShaderModuleSetLabel.argtypes = [WGPUShaderModule, WGPUStringView] -except AttributeError: - pass -try: - wgpuShaderModuleAddRef = _libraries['webgpu'].wgpuShaderModuleAddRef - wgpuShaderModuleAddRef.restype = None - wgpuShaderModuleAddRef.argtypes = [WGPUShaderModule] -except AttributeError: - pass -try: - wgpuShaderModuleRelease = _libraries['webgpu'].wgpuShaderModuleRelease - wgpuShaderModuleRelease.restype = None - wgpuShaderModuleRelease.argtypes = [WGPUShaderModule] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryBeginAccess = _libraries['webgpu'].wgpuSharedBufferMemoryBeginAccess - wgpuSharedBufferMemoryBeginAccess.restype = WGPUStatus - wgpuSharedBufferMemoryBeginAccess.argtypes = [WGPUSharedBufferMemory, WGPUBuffer, ctypes.POINTER(struct_WGPUSharedBufferMemoryBeginAccessDescriptor)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryCreateBuffer = _libraries['webgpu'].wgpuSharedBufferMemoryCreateBuffer - wgpuSharedBufferMemoryCreateBuffer.restype = WGPUBuffer - wgpuSharedBufferMemoryCreateBuffer.argtypes = [WGPUSharedBufferMemory, ctypes.POINTER(struct_WGPUBufferDescriptor)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryEndAccess = _libraries['webgpu'].wgpuSharedBufferMemoryEndAccess - wgpuSharedBufferMemoryEndAccess.restype = WGPUStatus - wgpuSharedBufferMemoryEndAccess.argtypes = [WGPUSharedBufferMemory, WGPUBuffer, ctypes.POINTER(struct_WGPUSharedBufferMemoryEndAccessState)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryGetProperties = _libraries['webgpu'].wgpuSharedBufferMemoryGetProperties - wgpuSharedBufferMemoryGetProperties.restype = WGPUStatus - wgpuSharedBufferMemoryGetProperties.argtypes = [WGPUSharedBufferMemory, ctypes.POINTER(struct_WGPUSharedBufferMemoryProperties)] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryIsDeviceLost = _libraries['webgpu'].wgpuSharedBufferMemoryIsDeviceLost - wgpuSharedBufferMemoryIsDeviceLost.restype = WGPUBool - wgpuSharedBufferMemoryIsDeviceLost.argtypes = [WGPUSharedBufferMemory] -except AttributeError: - pass -try: - wgpuSharedBufferMemorySetLabel = _libraries['webgpu'].wgpuSharedBufferMemorySetLabel - wgpuSharedBufferMemorySetLabel.restype = None - wgpuSharedBufferMemorySetLabel.argtypes = [WGPUSharedBufferMemory, WGPUStringView] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryAddRef = _libraries['webgpu'].wgpuSharedBufferMemoryAddRef - wgpuSharedBufferMemoryAddRef.restype = None - wgpuSharedBufferMemoryAddRef.argtypes = [WGPUSharedBufferMemory] -except AttributeError: - pass -try: - wgpuSharedBufferMemoryRelease = _libraries['webgpu'].wgpuSharedBufferMemoryRelease - wgpuSharedBufferMemoryRelease.restype = None - wgpuSharedBufferMemoryRelease.argtypes = [WGPUSharedBufferMemory] -except AttributeError: - pass -try: - wgpuSharedFenceExportInfo = _libraries['webgpu'].wgpuSharedFenceExportInfo - wgpuSharedFenceExportInfo.restype = None - wgpuSharedFenceExportInfo.argtypes = [WGPUSharedFence, ctypes.POINTER(struct_WGPUSharedFenceExportInfo)] -except AttributeError: - pass -try: - wgpuSharedFenceAddRef = _libraries['webgpu'].wgpuSharedFenceAddRef - wgpuSharedFenceAddRef.restype = None - wgpuSharedFenceAddRef.argtypes = [WGPUSharedFence] -except AttributeError: - pass -try: - wgpuSharedFenceRelease = _libraries['webgpu'].wgpuSharedFenceRelease - wgpuSharedFenceRelease.restype = None - wgpuSharedFenceRelease.argtypes = [WGPUSharedFence] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryBeginAccess = _libraries['webgpu'].wgpuSharedTextureMemoryBeginAccess - wgpuSharedTextureMemoryBeginAccess.restype = WGPUStatus - wgpuSharedTextureMemoryBeginAccess.argtypes = [WGPUSharedTextureMemory, WGPUTexture, ctypes.POINTER(struct_WGPUSharedTextureMemoryBeginAccessDescriptor)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryCreateTexture = _libraries['webgpu'].wgpuSharedTextureMemoryCreateTexture - wgpuSharedTextureMemoryCreateTexture.restype = WGPUTexture - wgpuSharedTextureMemoryCreateTexture.argtypes = [WGPUSharedTextureMemory, ctypes.POINTER(struct_WGPUTextureDescriptor)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryEndAccess = _libraries['webgpu'].wgpuSharedTextureMemoryEndAccess - wgpuSharedTextureMemoryEndAccess.restype = WGPUStatus - wgpuSharedTextureMemoryEndAccess.argtypes = [WGPUSharedTextureMemory, WGPUTexture, ctypes.POINTER(struct_WGPUSharedTextureMemoryEndAccessState)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryGetProperties = _libraries['webgpu'].wgpuSharedTextureMemoryGetProperties - wgpuSharedTextureMemoryGetProperties.restype = WGPUStatus - wgpuSharedTextureMemoryGetProperties.argtypes = [WGPUSharedTextureMemory, ctypes.POINTER(struct_WGPUSharedTextureMemoryProperties)] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryIsDeviceLost = _libraries['webgpu'].wgpuSharedTextureMemoryIsDeviceLost - wgpuSharedTextureMemoryIsDeviceLost.restype = WGPUBool - wgpuSharedTextureMemoryIsDeviceLost.argtypes = [WGPUSharedTextureMemory] -except AttributeError: - pass -try: - wgpuSharedTextureMemorySetLabel = _libraries['webgpu'].wgpuSharedTextureMemorySetLabel - wgpuSharedTextureMemorySetLabel.restype = None - wgpuSharedTextureMemorySetLabel.argtypes = [WGPUSharedTextureMemory, WGPUStringView] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryAddRef = _libraries['webgpu'].wgpuSharedTextureMemoryAddRef - wgpuSharedTextureMemoryAddRef.restype = None - wgpuSharedTextureMemoryAddRef.argtypes = [WGPUSharedTextureMemory] -except AttributeError: - pass -try: - wgpuSharedTextureMemoryRelease = _libraries['webgpu'].wgpuSharedTextureMemoryRelease - wgpuSharedTextureMemoryRelease.restype = None - wgpuSharedTextureMemoryRelease.argtypes = [WGPUSharedTextureMemory] -except AttributeError: - pass -try: - wgpuSurfaceConfigure = _libraries['webgpu'].wgpuSurfaceConfigure - wgpuSurfaceConfigure.restype = None - wgpuSurfaceConfigure.argtypes = [WGPUSurface, ctypes.POINTER(struct_WGPUSurfaceConfiguration)] -except AttributeError: - pass -try: - wgpuSurfaceGetCapabilities = _libraries['webgpu'].wgpuSurfaceGetCapabilities - wgpuSurfaceGetCapabilities.restype = WGPUStatus - wgpuSurfaceGetCapabilities.argtypes = [WGPUSurface, WGPUAdapter, ctypes.POINTER(struct_WGPUSurfaceCapabilities)] -except AttributeError: - pass -try: - wgpuSurfaceGetCurrentTexture = _libraries['webgpu'].wgpuSurfaceGetCurrentTexture - wgpuSurfaceGetCurrentTexture.restype = None - wgpuSurfaceGetCurrentTexture.argtypes = [WGPUSurface, ctypes.POINTER(struct_WGPUSurfaceTexture)] -except AttributeError: - pass -try: - wgpuSurfacePresent = _libraries['webgpu'].wgpuSurfacePresent - wgpuSurfacePresent.restype = None - wgpuSurfacePresent.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuSurfaceSetLabel = _libraries['webgpu'].wgpuSurfaceSetLabel - wgpuSurfaceSetLabel.restype = None - wgpuSurfaceSetLabel.argtypes = [WGPUSurface, WGPUStringView] -except AttributeError: - pass -try: - wgpuSurfaceUnconfigure = _libraries['webgpu'].wgpuSurfaceUnconfigure - wgpuSurfaceUnconfigure.restype = None - wgpuSurfaceUnconfigure.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuSurfaceAddRef = _libraries['webgpu'].wgpuSurfaceAddRef - wgpuSurfaceAddRef.restype = None - wgpuSurfaceAddRef.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuSurfaceRelease = _libraries['webgpu'].wgpuSurfaceRelease - wgpuSurfaceRelease.restype = None - wgpuSurfaceRelease.argtypes = [WGPUSurface] -except AttributeError: - pass -try: - wgpuTextureCreateErrorView = _libraries['webgpu'].wgpuTextureCreateErrorView - wgpuTextureCreateErrorView.restype = WGPUTextureView - wgpuTextureCreateErrorView.argtypes = [WGPUTexture, ctypes.POINTER(struct_WGPUTextureViewDescriptor)] -except AttributeError: - pass -try: - wgpuTextureCreateView = _libraries['webgpu'].wgpuTextureCreateView - wgpuTextureCreateView.restype = WGPUTextureView - wgpuTextureCreateView.argtypes = [WGPUTexture, ctypes.POINTER(struct_WGPUTextureViewDescriptor)] -except AttributeError: - pass -try: - wgpuTextureDestroy = _libraries['webgpu'].wgpuTextureDestroy - wgpuTextureDestroy.restype = None - wgpuTextureDestroy.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetDepthOrArrayLayers = _libraries['webgpu'].wgpuTextureGetDepthOrArrayLayers - wgpuTextureGetDepthOrArrayLayers.restype = uint32_t - wgpuTextureGetDepthOrArrayLayers.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetDimension = _libraries['webgpu'].wgpuTextureGetDimension - wgpuTextureGetDimension.restype = WGPUTextureDimension - wgpuTextureGetDimension.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetFormat = _libraries['webgpu'].wgpuTextureGetFormat - wgpuTextureGetFormat.restype = WGPUTextureFormat - wgpuTextureGetFormat.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetHeight = _libraries['webgpu'].wgpuTextureGetHeight - wgpuTextureGetHeight.restype = uint32_t - wgpuTextureGetHeight.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetMipLevelCount = _libraries['webgpu'].wgpuTextureGetMipLevelCount - wgpuTextureGetMipLevelCount.restype = uint32_t - wgpuTextureGetMipLevelCount.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetSampleCount = _libraries['webgpu'].wgpuTextureGetSampleCount - wgpuTextureGetSampleCount.restype = uint32_t - wgpuTextureGetSampleCount.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetUsage = _libraries['webgpu'].wgpuTextureGetUsage - wgpuTextureGetUsage.restype = WGPUTextureUsage - wgpuTextureGetUsage.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureGetWidth = _libraries['webgpu'].wgpuTextureGetWidth - wgpuTextureGetWidth.restype = uint32_t - wgpuTextureGetWidth.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureSetLabel = _libraries['webgpu'].wgpuTextureSetLabel - wgpuTextureSetLabel.restype = None - wgpuTextureSetLabel.argtypes = [WGPUTexture, WGPUStringView] -except AttributeError: - pass -try: - wgpuTextureAddRef = _libraries['webgpu'].wgpuTextureAddRef - wgpuTextureAddRef.restype = None - wgpuTextureAddRef.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureRelease = _libraries['webgpu'].wgpuTextureRelease - wgpuTextureRelease.restype = None - wgpuTextureRelease.argtypes = [WGPUTexture] -except AttributeError: - pass -try: - wgpuTextureViewSetLabel = _libraries['webgpu'].wgpuTextureViewSetLabel - wgpuTextureViewSetLabel.restype = None - wgpuTextureViewSetLabel.argtypes = [WGPUTextureView, WGPUStringView] -except AttributeError: - pass -try: - wgpuTextureViewAddRef = _libraries['webgpu'].wgpuTextureViewAddRef - wgpuTextureViewAddRef.restype = None - wgpuTextureViewAddRef.argtypes = [WGPUTextureView] -except AttributeError: - pass -try: - wgpuTextureViewRelease = _libraries['webgpu'].wgpuTextureViewRelease - wgpuTextureViewRelease.restype = None - wgpuTextureViewRelease.argtypes = [WGPUTextureView] -except AttributeError: - pass -__all__ = \ - ['WGPUAHardwareBufferProperties', 'WGPUAdapter', - 'WGPUAdapterInfo', 'WGPUAdapterPropertiesD3D', - 'WGPUAdapterPropertiesMemoryHeaps', - 'WGPUAdapterPropertiesSubgroups', 'WGPUAdapterPropertiesVk', - 'WGPUAdapterType', 'WGPUAdapterType_CPU', - 'WGPUAdapterType_DiscreteGPU', 'WGPUAdapterType_Force32', - 'WGPUAdapterType_IntegratedGPU', 'WGPUAdapterType_Unknown', - 'WGPUAddressMode', 'WGPUAddressMode_ClampToEdge', - 'WGPUAddressMode_Force32', 'WGPUAddressMode_MirrorRepeat', - 'WGPUAddressMode_Repeat', 'WGPUAddressMode_Undefined', - 'WGPUAlphaMode', 'WGPUAlphaMode_Force32', 'WGPUAlphaMode_Opaque', - 'WGPUAlphaMode_Premultiplied', 'WGPUAlphaMode_Unpremultiplied', - 'WGPUBackendType', 'WGPUBackendType_D3D11', - 'WGPUBackendType_D3D12', 'WGPUBackendType_Force32', - 'WGPUBackendType_Metal', 'WGPUBackendType_Null', - 'WGPUBackendType_OpenGL', 'WGPUBackendType_OpenGLES', - 'WGPUBackendType_Undefined', 'WGPUBackendType_Vulkan', - 'WGPUBackendType_WebGPU', 'WGPUBindGroup', - 'WGPUBindGroupDescriptor', 'WGPUBindGroupEntry', - 'WGPUBindGroupLayout', 'WGPUBindGroupLayoutDescriptor', - 'WGPUBindGroupLayoutEntry', 'WGPUBlendComponent', - 'WGPUBlendFactor', 'WGPUBlendFactor_Constant', - 'WGPUBlendFactor_Dst', 'WGPUBlendFactor_DstAlpha', - 'WGPUBlendFactor_Force32', 'WGPUBlendFactor_One', - 'WGPUBlendFactor_OneMinusConstant', 'WGPUBlendFactor_OneMinusDst', - 'WGPUBlendFactor_OneMinusDstAlpha', 'WGPUBlendFactor_OneMinusSrc', - 'WGPUBlendFactor_OneMinusSrc1', - 'WGPUBlendFactor_OneMinusSrc1Alpha', - 'WGPUBlendFactor_OneMinusSrcAlpha', 'WGPUBlendFactor_Src', - 'WGPUBlendFactor_Src1', 'WGPUBlendFactor_Src1Alpha', - 'WGPUBlendFactor_SrcAlpha', 'WGPUBlendFactor_SrcAlphaSaturated', - 'WGPUBlendFactor_Undefined', 'WGPUBlendFactor_Zero', - 'WGPUBlendOperation', 'WGPUBlendOperation_Add', - 'WGPUBlendOperation_Force32', 'WGPUBlendOperation_Max', - 'WGPUBlendOperation_Min', 'WGPUBlendOperation_ReverseSubtract', - 'WGPUBlendOperation_Subtract', 'WGPUBlendOperation_Undefined', - 'WGPUBlendState', 'WGPUBool', 'WGPUBuffer', - 'WGPUBufferBindingLayout', 'WGPUBufferBindingType', - 'WGPUBufferBindingType_BindingNotUsed', - 'WGPUBufferBindingType_Force32', - 'WGPUBufferBindingType_ReadOnlyStorage', - 'WGPUBufferBindingType_Storage', 'WGPUBufferBindingType_Uniform', - 'WGPUBufferDescriptor', 'WGPUBufferHostMappedPointer', - 'WGPUBufferMapAsyncStatus', - 'WGPUBufferMapAsyncStatus_DestroyedBeforeCallback', - 'WGPUBufferMapAsyncStatus_DeviceLost', - 'WGPUBufferMapAsyncStatus_Force32', - 'WGPUBufferMapAsyncStatus_InstanceDropped', - 'WGPUBufferMapAsyncStatus_MappingAlreadyPending', - 'WGPUBufferMapAsyncStatus_OffsetOutOfRange', - 'WGPUBufferMapAsyncStatus_SizeOutOfRange', - 'WGPUBufferMapAsyncStatus_Success', - 'WGPUBufferMapAsyncStatus_Unknown', - 'WGPUBufferMapAsyncStatus_UnmappedBeforeCallback', - 'WGPUBufferMapAsyncStatus_ValidationError', - 'WGPUBufferMapCallback', 'WGPUBufferMapCallback2', - 'WGPUBufferMapCallbackInfo', 'WGPUBufferMapCallbackInfo2', - 'WGPUBufferMapState', 'WGPUBufferMapState_Force32', - 'WGPUBufferMapState_Mapped', 'WGPUBufferMapState_Pending', - 'WGPUBufferMapState_Unmapped', 'WGPUBufferUsage', - 'WGPUBufferUsage_CopyDst', 'WGPUBufferUsage_CopySrc', - 'WGPUBufferUsage_Index', 'WGPUBufferUsage_Indirect', - 'WGPUBufferUsage_MapRead', 'WGPUBufferUsage_MapWrite', - 'WGPUBufferUsage_None', 'WGPUBufferUsage_QueryResolve', - 'WGPUBufferUsage_Storage', 'WGPUBufferUsage_Uniform', - 'WGPUBufferUsage_Vertex', 'WGPUCallback', 'WGPUCallbackMode', - 'WGPUCallbackMode_AllowProcessEvents', - 'WGPUCallbackMode_AllowSpontaneous', 'WGPUCallbackMode_Force32', - 'WGPUCallbackMode_WaitAnyOnly', 'WGPUChainedStruct', - 'WGPUChainedStructOut', 'WGPUColor', 'WGPUColorTargetState', - 'WGPUColorTargetStateExpandResolveTextureDawn', - 'WGPUColorWriteMask', 'WGPUColorWriteMask_All', - 'WGPUColorWriteMask_Alpha', 'WGPUColorWriteMask_Blue', - 'WGPUColorWriteMask_Green', 'WGPUColorWriteMask_None', - 'WGPUColorWriteMask_Red', 'WGPUCommandBuffer', - 'WGPUCommandBufferDescriptor', 'WGPUCommandEncoder', - 'WGPUCommandEncoderDescriptor', 'WGPUCompareFunction', - 'WGPUCompareFunction_Always', 'WGPUCompareFunction_Equal', - 'WGPUCompareFunction_Force32', 'WGPUCompareFunction_Greater', - 'WGPUCompareFunction_GreaterEqual', 'WGPUCompareFunction_Less', - 'WGPUCompareFunction_LessEqual', 'WGPUCompareFunction_Never', - 'WGPUCompareFunction_NotEqual', 'WGPUCompareFunction_Undefined', - 'WGPUCompilationInfo', 'WGPUCompilationInfoCallback', - 'WGPUCompilationInfoCallback2', 'WGPUCompilationInfoCallbackInfo', - 'WGPUCompilationInfoCallbackInfo2', - 'WGPUCompilationInfoRequestStatus', - 'WGPUCompilationInfoRequestStatus_DeviceLost', - 'WGPUCompilationInfoRequestStatus_Error', - 'WGPUCompilationInfoRequestStatus_Force32', - 'WGPUCompilationInfoRequestStatus_InstanceDropped', - 'WGPUCompilationInfoRequestStatus_Success', - 'WGPUCompilationInfoRequestStatus_Unknown', - 'WGPUCompilationMessage', 'WGPUCompilationMessageType', - 'WGPUCompilationMessageType_Error', - 'WGPUCompilationMessageType_Force32', - 'WGPUCompilationMessageType_Info', - 'WGPUCompilationMessageType_Warning', 'WGPUCompositeAlphaMode', - 'WGPUCompositeAlphaMode_Auto', 'WGPUCompositeAlphaMode_Force32', - 'WGPUCompositeAlphaMode_Inherit', 'WGPUCompositeAlphaMode_Opaque', - 'WGPUCompositeAlphaMode_Premultiplied', - 'WGPUCompositeAlphaMode_Unpremultiplied', - 'WGPUComputePassDescriptor', 'WGPUComputePassEncoder', - 'WGPUComputePassTimestampWrites', 'WGPUComputePipeline', - 'WGPUComputePipelineDescriptor', 'WGPUComputeState', - 'WGPUConstantEntry', 'WGPUCopyTextureForBrowserOptions', - 'WGPUCreateComputePipelineAsyncCallback', - 'WGPUCreateComputePipelineAsyncCallback2', - 'WGPUCreateComputePipelineAsyncCallbackInfo', - 'WGPUCreateComputePipelineAsyncCallbackInfo2', - 'WGPUCreatePipelineAsyncStatus', - 'WGPUCreatePipelineAsyncStatus_DeviceDestroyed', - 'WGPUCreatePipelineAsyncStatus_DeviceLost', - 'WGPUCreatePipelineAsyncStatus_Force32', - 'WGPUCreatePipelineAsyncStatus_InstanceDropped', - 'WGPUCreatePipelineAsyncStatus_InternalError', - 'WGPUCreatePipelineAsyncStatus_Success', - 'WGPUCreatePipelineAsyncStatus_Unknown', - 'WGPUCreatePipelineAsyncStatus_ValidationError', - 'WGPUCreateRenderPipelineAsyncCallback', - 'WGPUCreateRenderPipelineAsyncCallback2', - 'WGPUCreateRenderPipelineAsyncCallbackInfo', - 'WGPUCreateRenderPipelineAsyncCallbackInfo2', 'WGPUCullMode', - 'WGPUCullMode_Back', 'WGPUCullMode_Force32', 'WGPUCullMode_Front', - 'WGPUCullMode_None', 'WGPUCullMode_Undefined', - 'WGPUDawnAdapterPropertiesPowerPreference', - 'WGPUDawnBufferDescriptorErrorInfoFromWireClient', - 'WGPUDawnCacheDeviceDescriptor', - 'WGPUDawnEncoderInternalUsageDescriptor', - 'WGPUDawnExperimentalImmediateDataLimits', - 'WGPUDawnExperimentalSubgroupLimits', - 'WGPUDawnLoadCacheDataFunction', - 'WGPUDawnRenderPassColorAttachmentRenderToSingleSampled', - 'WGPUDawnShaderModuleSPIRVOptionsDescriptor', - 'WGPUDawnStoreCacheDataFunction', - 'WGPUDawnTexelCopyBufferRowAlignmentLimits', - 'WGPUDawnTextureInternalUsageDescriptor', - 'WGPUDawnTogglesDescriptor', 'WGPUDawnWGSLBlocklist', - 'WGPUDawnWireWGSLControl', 'WGPUDepthStencilState', 'WGPUDevice', - 'WGPUDeviceDescriptor', 'WGPUDeviceLostCallback', - 'WGPUDeviceLostCallback2', 'WGPUDeviceLostCallbackInfo', - 'WGPUDeviceLostCallbackInfo2', 'WGPUDeviceLostCallbackNew', - 'WGPUDeviceLostReason', 'WGPUDeviceLostReason_Destroyed', - 'WGPUDeviceLostReason_FailedCreation', - 'WGPUDeviceLostReason_Force32', - 'WGPUDeviceLostReason_InstanceDropped', - 'WGPUDeviceLostReason_Unknown', 'WGPUDrmFormatCapabilities', - 'WGPUDrmFormatProperties', 'WGPUErrorCallback', 'WGPUErrorFilter', - 'WGPUErrorFilter_Force32', 'WGPUErrorFilter_Internal', - 'WGPUErrorFilter_OutOfMemory', 'WGPUErrorFilter_Validation', - 'WGPUErrorType', 'WGPUErrorType_DeviceLost', - 'WGPUErrorType_Force32', 'WGPUErrorType_Internal', - 'WGPUErrorType_NoError', 'WGPUErrorType_OutOfMemory', - 'WGPUErrorType_Unknown', 'WGPUErrorType_Validation', - 'WGPUExtent2D', 'WGPUExtent3D', 'WGPUExternalTexture', - 'WGPUExternalTextureBindingEntry', - 'WGPUExternalTextureBindingLayout', - 'WGPUExternalTextureDescriptor', 'WGPUExternalTextureRotation', - 'WGPUExternalTextureRotation_Force32', - 'WGPUExternalTextureRotation_Rotate0Degrees', - 'WGPUExternalTextureRotation_Rotate180Degrees', - 'WGPUExternalTextureRotation_Rotate270Degrees', - 'WGPUExternalTextureRotation_Rotate90Degrees', 'WGPUFeatureLevel', - 'WGPUFeatureLevel_Compatibility', 'WGPUFeatureLevel_Core', - 'WGPUFeatureLevel_Force32', 'WGPUFeatureLevel_Undefined', - 'WGPUFeatureName', 'WGPUFeatureName_ANGLETextureSharing', - 'WGPUFeatureName_AdapterPropertiesD3D', - 'WGPUFeatureName_AdapterPropertiesMemoryHeaps', - 'WGPUFeatureName_AdapterPropertiesVk', - 'WGPUFeatureName_BGRA8UnormStorage', - 'WGPUFeatureName_BufferMapExtendedUsages', - 'WGPUFeatureName_ChromiumExperimentalImmediateData', - 'WGPUFeatureName_ChromiumExperimentalTimestampQueryInsidePasses', - 'WGPUFeatureName_ClipDistances', - 'WGPUFeatureName_D3D11MultithreadProtected', - 'WGPUFeatureName_DawnInternalUsages', - 'WGPUFeatureName_DawnLoadResolveTexture', - 'WGPUFeatureName_DawnMultiPlanarFormats', - 'WGPUFeatureName_DawnNative', - 'WGPUFeatureName_DawnPartialLoadResolveTexture', - 'WGPUFeatureName_DawnTexelCopyBufferRowAlignment', - 'WGPUFeatureName_Depth32FloatStencil8', - 'WGPUFeatureName_DepthClipControl', - 'WGPUFeatureName_DrmFormatCapabilities', - 'WGPUFeatureName_DualSourceBlending', - 'WGPUFeatureName_FlexibleTextureViews', - 'WGPUFeatureName_Float32Blendable', - 'WGPUFeatureName_Float32Filterable', 'WGPUFeatureName_Force32', - 'WGPUFeatureName_FormatCapabilities', - 'WGPUFeatureName_FramebufferFetch', - 'WGPUFeatureName_HostMappedPointer', - 'WGPUFeatureName_ImplicitDeviceSynchronization', - 'WGPUFeatureName_IndirectFirstInstance', - 'WGPUFeatureName_MSAARenderToSingleSampled', - 'WGPUFeatureName_MultiDrawIndirect', - 'WGPUFeatureName_MultiPlanarFormatExtendedUsages', - 'WGPUFeatureName_MultiPlanarFormatNv12a', - 'WGPUFeatureName_MultiPlanarFormatNv16', - 'WGPUFeatureName_MultiPlanarFormatNv24', - 'WGPUFeatureName_MultiPlanarFormatP010', - 'WGPUFeatureName_MultiPlanarFormatP210', - 'WGPUFeatureName_MultiPlanarFormatP410', - 'WGPUFeatureName_MultiPlanarRenderTargets', - 'WGPUFeatureName_Norm16TextureFormats', - 'WGPUFeatureName_PixelLocalStorageCoherent', - 'WGPUFeatureName_PixelLocalStorageNonCoherent', - 'WGPUFeatureName_R8UnormStorage', - 'WGPUFeatureName_RG11B10UfloatRenderable', - 'WGPUFeatureName_ShaderF16', - 'WGPUFeatureName_ShaderModuleCompilationOptions', - 'WGPUFeatureName_SharedBufferMemoryD3D12Resource', - 'WGPUFeatureName_SharedFenceDXGISharedHandle', - 'WGPUFeatureName_SharedFenceMTLSharedEvent', - 'WGPUFeatureName_SharedFenceSyncFD', - 'WGPUFeatureName_SharedFenceVkSemaphoreOpaqueFD', - 'WGPUFeatureName_SharedFenceVkSemaphoreZirconHandle', - 'WGPUFeatureName_SharedTextureMemoryAHardwareBuffer', - 'WGPUFeatureName_SharedTextureMemoryD3D11Texture2D', - 'WGPUFeatureName_SharedTextureMemoryDXGISharedHandle', - 'WGPUFeatureName_SharedTextureMemoryDmaBuf', - 'WGPUFeatureName_SharedTextureMemoryEGLImage', - 'WGPUFeatureName_SharedTextureMemoryIOSurface', - 'WGPUFeatureName_SharedTextureMemoryOpaqueFD', - 'WGPUFeatureName_SharedTextureMemoryVkDedicatedAllocation', - 'WGPUFeatureName_SharedTextureMemoryZirconHandle', - 'WGPUFeatureName_Snorm16TextureFormats', - 'WGPUFeatureName_StaticSamplers', 'WGPUFeatureName_Subgroups', - 'WGPUFeatureName_SubgroupsF16', - 'WGPUFeatureName_TextureCompressionASTC', - 'WGPUFeatureName_TextureCompressionBC', - 'WGPUFeatureName_TextureCompressionETC2', - 'WGPUFeatureName_TimestampQuery', - 'WGPUFeatureName_TransientAttachments', - 'WGPUFeatureName_Unorm16TextureFormats', - 'WGPUFeatureName_YCbCrVulkanSamplers', 'WGPUFilterMode', - 'WGPUFilterMode_Force32', 'WGPUFilterMode_Linear', - 'WGPUFilterMode_Nearest', 'WGPUFilterMode_Undefined', 'WGPUFlags', - 'WGPUFormatCapabilities', 'WGPUFragmentState', 'WGPUFrontFace', - 'WGPUFrontFace_CCW', 'WGPUFrontFace_CW', 'WGPUFrontFace_Force32', - 'WGPUFrontFace_Undefined', 'WGPUFuture', 'WGPUFutureWaitInfo', - 'WGPUHeapProperty', 'WGPUHeapProperty_DeviceLocal', - 'WGPUHeapProperty_HostCached', 'WGPUHeapProperty_HostCoherent', - 'WGPUHeapProperty_HostUncached', 'WGPUHeapProperty_HostVisible', - 'WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER', 'WGPUImageCopyBuffer', - 'WGPUImageCopyExternalTexture', 'WGPUImageCopyTexture', - 'WGPUIndexFormat', 'WGPUIndexFormat_Force32', - 'WGPUIndexFormat_Uint16', 'WGPUIndexFormat_Uint32', - 'WGPUIndexFormat_Undefined', 'WGPUInstance', - 'WGPUInstanceDescriptor', 'WGPUInstanceFeatures', 'WGPULimits', - 'WGPULoadOp', 'WGPULoadOp_Clear', - 'WGPULoadOp_ExpandResolveTexture', 'WGPULoadOp_Force32', - 'WGPULoadOp_Load', 'WGPULoadOp_Undefined', 'WGPULoggingCallback', - 'WGPULoggingType', 'WGPULoggingType_Error', - 'WGPULoggingType_Force32', 'WGPULoggingType_Info', - 'WGPULoggingType_Verbose', 'WGPULoggingType_Warning', - 'WGPUMapAsyncStatus', 'WGPUMapAsyncStatus_Aborted', - 'WGPUMapAsyncStatus_Error', 'WGPUMapAsyncStatus_Force32', - 'WGPUMapAsyncStatus_InstanceDropped', - 'WGPUMapAsyncStatus_Success', 'WGPUMapAsyncStatus_Unknown', - 'WGPUMapMode', 'WGPUMapMode_None', 'WGPUMapMode_Read', - 'WGPUMapMode_Write', 'WGPUMemoryHeapInfo', 'WGPUMipmapFilterMode', - 'WGPUMipmapFilterMode_Force32', 'WGPUMipmapFilterMode_Linear', - 'WGPUMipmapFilterMode_Nearest', 'WGPUMipmapFilterMode_Undefined', - 'WGPUMultisampleState', 'WGPUOptionalBool', - 'WGPUOptionalBool_False', 'WGPUOptionalBool_Force32', - 'WGPUOptionalBool_True', 'WGPUOptionalBool_Undefined', - 'WGPUOrigin2D', 'WGPUOrigin3D', 'WGPUPipelineLayout', - 'WGPUPipelineLayoutDescriptor', - 'WGPUPipelineLayoutPixelLocalStorage', - 'WGPUPipelineLayoutStorageAttachment', - 'WGPUPopErrorScopeCallback', 'WGPUPopErrorScopeCallback2', - 'WGPUPopErrorScopeCallbackInfo', 'WGPUPopErrorScopeCallbackInfo2', - 'WGPUPopErrorScopeStatus', 'WGPUPopErrorScopeStatus_Force32', - 'WGPUPopErrorScopeStatus_InstanceDropped', - 'WGPUPopErrorScopeStatus_Success', 'WGPUPowerPreference', - 'WGPUPowerPreference_Force32', - 'WGPUPowerPreference_HighPerformance', - 'WGPUPowerPreference_LowPower', 'WGPUPowerPreference_Undefined', - 'WGPUPresentMode', 'WGPUPresentMode_Fifo', - 'WGPUPresentMode_FifoRelaxed', 'WGPUPresentMode_Force32', - 'WGPUPresentMode_Immediate', 'WGPUPresentMode_Mailbox', - 'WGPUPrimitiveState', 'WGPUPrimitiveTopology', - 'WGPUPrimitiveTopology_Force32', 'WGPUPrimitiveTopology_LineList', - 'WGPUPrimitiveTopology_LineStrip', - 'WGPUPrimitiveTopology_PointList', - 'WGPUPrimitiveTopology_TriangleList', - 'WGPUPrimitiveTopology_TriangleStrip', - 'WGPUPrimitiveTopology_Undefined', 'WGPUProc', - 'WGPUProcAdapterAddRef', 'WGPUProcAdapterCreateDevice', - 'WGPUProcAdapterGetFeatures', - 'WGPUProcAdapterGetFormatCapabilities', 'WGPUProcAdapterGetInfo', - 'WGPUProcAdapterGetInstance', 'WGPUProcAdapterGetLimits', - 'WGPUProcAdapterHasFeature', 'WGPUProcAdapterInfoFreeMembers', - 'WGPUProcAdapterPropertiesMemoryHeapsFreeMembers', - 'WGPUProcAdapterRelease', 'WGPUProcAdapterRequestDevice', - 'WGPUProcAdapterRequestDevice2', 'WGPUProcAdapterRequestDeviceF', - 'WGPUProcBindGroupAddRef', 'WGPUProcBindGroupLayoutAddRef', - 'WGPUProcBindGroupLayoutRelease', - 'WGPUProcBindGroupLayoutSetLabel', 'WGPUProcBindGroupRelease', - 'WGPUProcBindGroupSetLabel', 'WGPUProcBufferAddRef', - 'WGPUProcBufferDestroy', 'WGPUProcBufferGetConstMappedRange', - 'WGPUProcBufferGetMapState', 'WGPUProcBufferGetMappedRange', - 'WGPUProcBufferGetSize', 'WGPUProcBufferGetUsage', - 'WGPUProcBufferMapAsync', 'WGPUProcBufferMapAsync2', - 'WGPUProcBufferMapAsyncF', 'WGPUProcBufferRelease', - 'WGPUProcBufferSetLabel', 'WGPUProcBufferUnmap', - 'WGPUProcCommandBufferAddRef', 'WGPUProcCommandBufferRelease', - 'WGPUProcCommandBufferSetLabel', 'WGPUProcCommandEncoderAddRef', - 'WGPUProcCommandEncoderBeginComputePass', - 'WGPUProcCommandEncoderBeginRenderPass', - 'WGPUProcCommandEncoderClearBuffer', - 'WGPUProcCommandEncoderCopyBufferToBuffer', - 'WGPUProcCommandEncoderCopyBufferToTexture', - 'WGPUProcCommandEncoderCopyTextureToBuffer', - 'WGPUProcCommandEncoderCopyTextureToTexture', - 'WGPUProcCommandEncoderFinish', - 'WGPUProcCommandEncoderInjectValidationError', - 'WGPUProcCommandEncoderInsertDebugMarker', - 'WGPUProcCommandEncoderPopDebugGroup', - 'WGPUProcCommandEncoderPushDebugGroup', - 'WGPUProcCommandEncoderRelease', - 'WGPUProcCommandEncoderResolveQuerySet', - 'WGPUProcCommandEncoderSetLabel', - 'WGPUProcCommandEncoderWriteBuffer', - 'WGPUProcCommandEncoderWriteTimestamp', - 'WGPUProcComputePassEncoderAddRef', - 'WGPUProcComputePassEncoderDispatchWorkgroups', - 'WGPUProcComputePassEncoderDispatchWorkgroupsIndirect', - 'WGPUProcComputePassEncoderEnd', - 'WGPUProcComputePassEncoderInsertDebugMarker', - 'WGPUProcComputePassEncoderPopDebugGroup', - 'WGPUProcComputePassEncoderPushDebugGroup', - 'WGPUProcComputePassEncoderRelease', - 'WGPUProcComputePassEncoderSetBindGroup', - 'WGPUProcComputePassEncoderSetLabel', - 'WGPUProcComputePassEncoderSetPipeline', - 'WGPUProcComputePassEncoderWriteTimestamp', - 'WGPUProcComputePipelineAddRef', - 'WGPUProcComputePipelineGetBindGroupLayout', - 'WGPUProcComputePipelineRelease', - 'WGPUProcComputePipelineSetLabel', 'WGPUProcCreateInstance', - 'WGPUProcDeviceAddRef', 'WGPUProcDeviceCreateBindGroup', - 'WGPUProcDeviceCreateBindGroupLayout', - 'WGPUProcDeviceCreateBuffer', - 'WGPUProcDeviceCreateCommandEncoder', - 'WGPUProcDeviceCreateComputePipeline', - 'WGPUProcDeviceCreateComputePipelineAsync', - 'WGPUProcDeviceCreateComputePipelineAsync2', - 'WGPUProcDeviceCreateComputePipelineAsyncF', - 'WGPUProcDeviceCreateErrorBuffer', - 'WGPUProcDeviceCreateErrorExternalTexture', - 'WGPUProcDeviceCreateErrorShaderModule', - 'WGPUProcDeviceCreateErrorTexture', - 'WGPUProcDeviceCreateExternalTexture', - 'WGPUProcDeviceCreatePipelineLayout', - 'WGPUProcDeviceCreateQuerySet', - 'WGPUProcDeviceCreateRenderBundleEncoder', - 'WGPUProcDeviceCreateRenderPipeline', - 'WGPUProcDeviceCreateRenderPipelineAsync', - 'WGPUProcDeviceCreateRenderPipelineAsync2', - 'WGPUProcDeviceCreateRenderPipelineAsyncF', - 'WGPUProcDeviceCreateSampler', 'WGPUProcDeviceCreateShaderModule', - 'WGPUProcDeviceCreateTexture', 'WGPUProcDeviceDestroy', - 'WGPUProcDeviceForceLoss', - 'WGPUProcDeviceGetAHardwareBufferProperties', - 'WGPUProcDeviceGetAdapter', 'WGPUProcDeviceGetAdapterInfo', - 'WGPUProcDeviceGetFeatures', 'WGPUProcDeviceGetLimits', - 'WGPUProcDeviceGetLostFuture', 'WGPUProcDeviceGetQueue', - 'WGPUProcDeviceHasFeature', - 'WGPUProcDeviceImportSharedBufferMemory', - 'WGPUProcDeviceImportSharedFence', - 'WGPUProcDeviceImportSharedTextureMemory', - 'WGPUProcDeviceInjectError', 'WGPUProcDevicePopErrorScope', - 'WGPUProcDevicePopErrorScope2', 'WGPUProcDevicePopErrorScopeF', - 'WGPUProcDevicePushErrorScope', 'WGPUProcDeviceRelease', - 'WGPUProcDeviceSetLabel', 'WGPUProcDeviceSetLoggingCallback', - 'WGPUProcDeviceTick', 'WGPUProcDeviceValidateTextureDescriptor', - 'WGPUProcDrmFormatCapabilitiesFreeMembers', - 'WGPUProcExternalTextureAddRef', 'WGPUProcExternalTextureDestroy', - 'WGPUProcExternalTextureExpire', 'WGPUProcExternalTextureRefresh', - 'WGPUProcExternalTextureRelease', - 'WGPUProcExternalTextureSetLabel', 'WGPUProcGetInstanceFeatures', - 'WGPUProcGetProcAddress', 'WGPUProcInstanceAddRef', - 'WGPUProcInstanceCreateSurface', - 'WGPUProcInstanceEnumerateWGSLLanguageFeatures', - 'WGPUProcInstanceHasWGSLLanguageFeature', - 'WGPUProcInstanceProcessEvents', 'WGPUProcInstanceRelease', - 'WGPUProcInstanceRequestAdapter', - 'WGPUProcInstanceRequestAdapter2', - 'WGPUProcInstanceRequestAdapterF', 'WGPUProcInstanceWaitAny', - 'WGPUProcPipelineLayoutAddRef', 'WGPUProcPipelineLayoutRelease', - 'WGPUProcPipelineLayoutSetLabel', 'WGPUProcQuerySetAddRef', - 'WGPUProcQuerySetDestroy', 'WGPUProcQuerySetGetCount', - 'WGPUProcQuerySetGetType', 'WGPUProcQuerySetRelease', - 'WGPUProcQuerySetSetLabel', 'WGPUProcQueueAddRef', - 'WGPUProcQueueCopyExternalTextureForBrowser', - 'WGPUProcQueueCopyTextureForBrowser', - 'WGPUProcQueueOnSubmittedWorkDone', - 'WGPUProcQueueOnSubmittedWorkDone2', - 'WGPUProcQueueOnSubmittedWorkDoneF', 'WGPUProcQueueRelease', - 'WGPUProcQueueSetLabel', 'WGPUProcQueueSubmit', - 'WGPUProcQueueWriteBuffer', 'WGPUProcQueueWriteTexture', - 'WGPUProcRenderBundleAddRef', 'WGPUProcRenderBundleEncoderAddRef', - 'WGPUProcRenderBundleEncoderDraw', - 'WGPUProcRenderBundleEncoderDrawIndexed', - 'WGPUProcRenderBundleEncoderDrawIndexedIndirect', - 'WGPUProcRenderBundleEncoderDrawIndirect', - 'WGPUProcRenderBundleEncoderFinish', - 'WGPUProcRenderBundleEncoderInsertDebugMarker', - 'WGPUProcRenderBundleEncoderPopDebugGroup', - 'WGPUProcRenderBundleEncoderPushDebugGroup', - 'WGPUProcRenderBundleEncoderRelease', - 'WGPUProcRenderBundleEncoderSetBindGroup', - 'WGPUProcRenderBundleEncoderSetIndexBuffer', - 'WGPUProcRenderBundleEncoderSetLabel', - 'WGPUProcRenderBundleEncoderSetPipeline', - 'WGPUProcRenderBundleEncoderSetVertexBuffer', - 'WGPUProcRenderBundleRelease', 'WGPUProcRenderBundleSetLabel', - 'WGPUProcRenderPassEncoderAddRef', - 'WGPUProcRenderPassEncoderBeginOcclusionQuery', - 'WGPUProcRenderPassEncoderDraw', - 'WGPUProcRenderPassEncoderDrawIndexed', - 'WGPUProcRenderPassEncoderDrawIndexedIndirect', - 'WGPUProcRenderPassEncoderDrawIndirect', - 'WGPUProcRenderPassEncoderEnd', - 'WGPUProcRenderPassEncoderEndOcclusionQuery', - 'WGPUProcRenderPassEncoderExecuteBundles', - 'WGPUProcRenderPassEncoderInsertDebugMarker', - 'WGPUProcRenderPassEncoderMultiDrawIndexedIndirect', - 'WGPUProcRenderPassEncoderMultiDrawIndirect', - 'WGPUProcRenderPassEncoderPixelLocalStorageBarrier', - 'WGPUProcRenderPassEncoderPopDebugGroup', - 'WGPUProcRenderPassEncoderPushDebugGroup', - 'WGPUProcRenderPassEncoderRelease', - 'WGPUProcRenderPassEncoderSetBindGroup', - 'WGPUProcRenderPassEncoderSetBlendConstant', - 'WGPUProcRenderPassEncoderSetIndexBuffer', - 'WGPUProcRenderPassEncoderSetLabel', - 'WGPUProcRenderPassEncoderSetPipeline', - 'WGPUProcRenderPassEncoderSetScissorRect', - 'WGPUProcRenderPassEncoderSetStencilReference', - 'WGPUProcRenderPassEncoderSetVertexBuffer', - 'WGPUProcRenderPassEncoderSetViewport', - 'WGPUProcRenderPassEncoderWriteTimestamp', - 'WGPUProcRenderPipelineAddRef', - 'WGPUProcRenderPipelineGetBindGroupLayout', - 'WGPUProcRenderPipelineRelease', 'WGPUProcRenderPipelineSetLabel', - 'WGPUProcSamplerAddRef', 'WGPUProcSamplerRelease', - 'WGPUProcSamplerSetLabel', 'WGPUProcShaderModuleAddRef', - 'WGPUProcShaderModuleGetCompilationInfo', - 'WGPUProcShaderModuleGetCompilationInfo2', - 'WGPUProcShaderModuleGetCompilationInfoF', - 'WGPUProcShaderModuleRelease', 'WGPUProcShaderModuleSetLabel', - 'WGPUProcSharedBufferMemoryAddRef', - 'WGPUProcSharedBufferMemoryBeginAccess', - 'WGPUProcSharedBufferMemoryCreateBuffer', - 'WGPUProcSharedBufferMemoryEndAccess', - 'WGPUProcSharedBufferMemoryEndAccessStateFreeMembers', - 'WGPUProcSharedBufferMemoryGetProperties', - 'WGPUProcSharedBufferMemoryIsDeviceLost', - 'WGPUProcSharedBufferMemoryRelease', - 'WGPUProcSharedBufferMemorySetLabel', 'WGPUProcSharedFenceAddRef', - 'WGPUProcSharedFenceExportInfo', 'WGPUProcSharedFenceRelease', - 'WGPUProcSharedTextureMemoryAddRef', - 'WGPUProcSharedTextureMemoryBeginAccess', - 'WGPUProcSharedTextureMemoryCreateTexture', - 'WGPUProcSharedTextureMemoryEndAccess', - 'WGPUProcSharedTextureMemoryEndAccessStateFreeMembers', - 'WGPUProcSharedTextureMemoryGetProperties', - 'WGPUProcSharedTextureMemoryIsDeviceLost', - 'WGPUProcSharedTextureMemoryRelease', - 'WGPUProcSharedTextureMemorySetLabel', - 'WGPUProcSupportedFeaturesFreeMembers', 'WGPUProcSurfaceAddRef', - 'WGPUProcSurfaceCapabilitiesFreeMembers', - 'WGPUProcSurfaceConfigure', 'WGPUProcSurfaceGetCapabilities', - 'WGPUProcSurfaceGetCurrentTexture', 'WGPUProcSurfacePresent', - 'WGPUProcSurfaceRelease', 'WGPUProcSurfaceSetLabel', - 'WGPUProcSurfaceUnconfigure', 'WGPUProcTextureAddRef', - 'WGPUProcTextureCreateErrorView', 'WGPUProcTextureCreateView', - 'WGPUProcTextureDestroy', 'WGPUProcTextureGetDepthOrArrayLayers', - 'WGPUProcTextureGetDimension', 'WGPUProcTextureGetFormat', - 'WGPUProcTextureGetHeight', 'WGPUProcTextureGetMipLevelCount', - 'WGPUProcTextureGetSampleCount', 'WGPUProcTextureGetUsage', - 'WGPUProcTextureGetWidth', 'WGPUProcTextureRelease', - 'WGPUProcTextureSetLabel', 'WGPUProcTextureViewAddRef', - 'WGPUProcTextureViewRelease', 'WGPUProcTextureViewSetLabel', - 'WGPUQuerySet', 'WGPUQuerySetDescriptor', 'WGPUQueryType', - 'WGPUQueryType_Force32', 'WGPUQueryType_Occlusion', - 'WGPUQueryType_Timestamp', 'WGPUQueue', 'WGPUQueueDescriptor', - 'WGPUQueueWorkDoneCallback', 'WGPUQueueWorkDoneCallback2', - 'WGPUQueueWorkDoneCallbackInfo', 'WGPUQueueWorkDoneCallbackInfo2', - 'WGPUQueueWorkDoneStatus', 'WGPUQueueWorkDoneStatus_DeviceLost', - 'WGPUQueueWorkDoneStatus_Error', - 'WGPUQueueWorkDoneStatus_Force32', - 'WGPUQueueWorkDoneStatus_InstanceDropped', - 'WGPUQueueWorkDoneStatus_Success', - 'WGPUQueueWorkDoneStatus_Unknown', 'WGPURenderBundle', - 'WGPURenderBundleDescriptor', 'WGPURenderBundleEncoder', - 'WGPURenderBundleEncoderDescriptor', - 'WGPURenderPassColorAttachment', - 'WGPURenderPassDepthStencilAttachment', - 'WGPURenderPassDescriptor', - 'WGPURenderPassDescriptorExpandResolveRect', - 'WGPURenderPassDescriptorMaxDrawCount', 'WGPURenderPassEncoder', - 'WGPURenderPassMaxDrawCount', 'WGPURenderPassPixelLocalStorage', - 'WGPURenderPassStorageAttachment', - 'WGPURenderPassTimestampWrites', 'WGPURenderPipeline', - 'WGPURenderPipelineDescriptor', 'WGPURequestAdapterCallback', - 'WGPURequestAdapterCallback2', 'WGPURequestAdapterCallbackInfo', - 'WGPURequestAdapterCallbackInfo2', 'WGPURequestAdapterOptions', - 'WGPURequestAdapterStatus', 'WGPURequestAdapterStatus_Error', - 'WGPURequestAdapterStatus_Force32', - 'WGPURequestAdapterStatus_InstanceDropped', - 'WGPURequestAdapterStatus_Success', - 'WGPURequestAdapterStatus_Unavailable', - 'WGPURequestAdapterStatus_Unknown', 'WGPURequestDeviceCallback', - 'WGPURequestDeviceCallback2', 'WGPURequestDeviceCallbackInfo', - 'WGPURequestDeviceCallbackInfo2', 'WGPURequestDeviceStatus', - 'WGPURequestDeviceStatus_Error', - 'WGPURequestDeviceStatus_Force32', - 'WGPURequestDeviceStatus_InstanceDropped', - 'WGPURequestDeviceStatus_Success', - 'WGPURequestDeviceStatus_Unknown', 'WGPURequiredLimits', - 'WGPUSType', 'WGPUSType_AHardwareBufferProperties', - 'WGPUSType_AdapterPropertiesD3D', - 'WGPUSType_AdapterPropertiesMemoryHeaps', - 'WGPUSType_AdapterPropertiesSubgroups', - 'WGPUSType_AdapterPropertiesVk', - 'WGPUSType_BufferHostMappedPointer', - 'WGPUSType_ColorTargetStateExpandResolveTextureDawn', - 'WGPUSType_DawnAdapterPropertiesPowerPreference', - 'WGPUSType_DawnBufferDescriptorErrorInfoFromWireClient', - 'WGPUSType_DawnCacheDeviceDescriptor', - 'WGPUSType_DawnEncoderInternalUsageDescriptor', - 'WGPUSType_DawnExperimentalImmediateDataLimits', - 'WGPUSType_DawnExperimentalSubgroupLimits', - 'WGPUSType_DawnInstanceDescriptor', - 'WGPUSType_DawnRenderPassColorAttachmentRenderToSingleSampled', - 'WGPUSType_DawnShaderModuleSPIRVOptionsDescriptor', - 'WGPUSType_DawnTexelCopyBufferRowAlignmentLimits', - 'WGPUSType_DawnTextureInternalUsageDescriptor', - 'WGPUSType_DawnTogglesDescriptor', 'WGPUSType_DawnWGSLBlocklist', - 'WGPUSType_DawnWireWGSLControl', - 'WGPUSType_DrmFormatCapabilities', - 'WGPUSType_ExternalTextureBindingEntry', - 'WGPUSType_ExternalTextureBindingLayout', 'WGPUSType_Force32', - 'WGPUSType_PipelineLayoutPixelLocalStorage', - 'WGPUSType_RenderPassDescriptorExpandResolveRect', - 'WGPUSType_RenderPassMaxDrawCount', - 'WGPUSType_RenderPassPixelLocalStorage', - 'WGPUSType_RequestAdapterOptionsD3D11Device', - 'WGPUSType_RequestAdapterOptionsGetGLProc', - 'WGPUSType_RequestAdapterOptionsLUID', - 'WGPUSType_ShaderModuleCompilationOptions', - 'WGPUSType_ShaderSourceSPIRV', 'WGPUSType_ShaderSourceWGSL', - 'WGPUSType_SharedBufferMemoryD3D12ResourceDescriptor', - 'WGPUSType_SharedFenceDXGISharedHandleDescriptor', - 'WGPUSType_SharedFenceDXGISharedHandleExportInfo', - 'WGPUSType_SharedFenceMTLSharedEventDescriptor', - 'WGPUSType_SharedFenceMTLSharedEventExportInfo', - 'WGPUSType_SharedFenceSyncFDDescriptor', - 'WGPUSType_SharedFenceSyncFDExportInfo', - 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDDescriptor', - 'WGPUSType_SharedFenceVkSemaphoreOpaqueFDExportInfo', - 'WGPUSType_SharedFenceVkSemaphoreZirconHandleDescriptor', - 'WGPUSType_SharedFenceVkSemaphoreZirconHandleExportInfo', - 'WGPUSType_SharedTextureMemoryAHardwareBufferDescriptor', - 'WGPUSType_SharedTextureMemoryAHardwareBufferProperties', - 'WGPUSType_SharedTextureMemoryD3D11Texture2DDescriptor', - 'WGPUSType_SharedTextureMemoryD3DSwapchainBeginState', - 'WGPUSType_SharedTextureMemoryDXGISharedHandleDescriptor', - 'WGPUSType_SharedTextureMemoryDmaBufDescriptor', - 'WGPUSType_SharedTextureMemoryEGLImageDescriptor', - 'WGPUSType_SharedTextureMemoryIOSurfaceDescriptor', - 'WGPUSType_SharedTextureMemoryInitializedBeginState', - 'WGPUSType_SharedTextureMemoryInitializedEndState', - 'WGPUSType_SharedTextureMemoryOpaqueFDDescriptor', - 'WGPUSType_SharedTextureMemoryVkDedicatedAllocationDescriptor', - 'WGPUSType_SharedTextureMemoryVkImageLayoutBeginState', - 'WGPUSType_SharedTextureMemoryVkImageLayoutEndState', - 'WGPUSType_SharedTextureMemoryZirconHandleDescriptor', - 'WGPUSType_StaticSamplerBindingLayout', - 'WGPUSType_SurfaceDescriptorFromWindowsCoreWindow', - 'WGPUSType_SurfaceDescriptorFromWindowsSwapChainPanel', - 'WGPUSType_SurfaceSourceAndroidNativeWindow', - 'WGPUSType_SurfaceSourceCanvasHTMLSelector_Emscripten', - 'WGPUSType_SurfaceSourceMetalLayer', - 'WGPUSType_SurfaceSourceWaylandSurface', - 'WGPUSType_SurfaceSourceWindowsHWND', - 'WGPUSType_SurfaceSourceXCBWindow', - 'WGPUSType_SurfaceSourceXlibWindow', - 'WGPUSType_TextureBindingViewDimensionDescriptor', - 'WGPUSType_YCbCrVkDescriptor', 'WGPUSampler', - 'WGPUSamplerBindingLayout', 'WGPUSamplerBindingType', - 'WGPUSamplerBindingType_BindingNotUsed', - 'WGPUSamplerBindingType_Comparison', - 'WGPUSamplerBindingType_Filtering', - 'WGPUSamplerBindingType_Force32', - 'WGPUSamplerBindingType_NonFiltering', 'WGPUSamplerDescriptor', - 'WGPUShaderModule', 'WGPUShaderModuleCompilationOptions', - 'WGPUShaderModuleDescriptor', 'WGPUShaderModuleSPIRVDescriptor', - 'WGPUShaderModuleWGSLDescriptor', 'WGPUShaderSourceSPIRV', - 'WGPUShaderSourceWGSL', 'WGPUShaderStage', - 'WGPUShaderStage_Compute', 'WGPUShaderStage_Fragment', - 'WGPUShaderStage_None', 'WGPUShaderStage_Vertex', - 'WGPUSharedBufferMemory', - 'WGPUSharedBufferMemoryBeginAccessDescriptor', - 'WGPUSharedBufferMemoryDescriptor', - 'WGPUSharedBufferMemoryEndAccessState', - 'WGPUSharedBufferMemoryProperties', 'WGPUSharedFence', - 'WGPUSharedFenceDXGISharedHandleDescriptor', - 'WGPUSharedFenceDXGISharedHandleExportInfo', - 'WGPUSharedFenceDescriptor', 'WGPUSharedFenceExportInfo', - 'WGPUSharedFenceMTLSharedEventDescriptor', - 'WGPUSharedFenceMTLSharedEventExportInfo', - 'WGPUSharedFenceSyncFDDescriptor', - 'WGPUSharedFenceSyncFDExportInfo', 'WGPUSharedFenceType', - 'WGPUSharedFenceType_DXGISharedHandle', - 'WGPUSharedFenceType_Force32', - 'WGPUSharedFenceType_MTLSharedEvent', - 'WGPUSharedFenceType_SyncFD', - 'WGPUSharedFenceType_VkSemaphoreOpaqueFD', - 'WGPUSharedFenceType_VkSemaphoreZirconHandle', - 'WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor', - 'WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo', - 'WGPUSharedFenceVkSemaphoreZirconHandleDescriptor', - 'WGPUSharedFenceVkSemaphoreZirconHandleExportInfo', - 'WGPUSharedTextureMemory', - 'WGPUSharedTextureMemoryAHardwareBufferDescriptor', - 'WGPUSharedTextureMemoryAHardwareBufferProperties', - 'WGPUSharedTextureMemoryBeginAccessDescriptor', - 'WGPUSharedTextureMemoryD3DSwapchainBeginState', - 'WGPUSharedTextureMemoryDXGISharedHandleDescriptor', - 'WGPUSharedTextureMemoryDescriptor', - 'WGPUSharedTextureMemoryDmaBufDescriptor', - 'WGPUSharedTextureMemoryDmaBufPlane', - 'WGPUSharedTextureMemoryEGLImageDescriptor', - 'WGPUSharedTextureMemoryEndAccessState', - 'WGPUSharedTextureMemoryIOSurfaceDescriptor', - 'WGPUSharedTextureMemoryOpaqueFDDescriptor', - 'WGPUSharedTextureMemoryProperties', - 'WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor', - 'WGPUSharedTextureMemoryVkImageLayoutBeginState', - 'WGPUSharedTextureMemoryVkImageLayoutEndState', - 'WGPUSharedTextureMemoryZirconHandleDescriptor', - 'WGPUStaticSamplerBindingLayout', 'WGPUStatus', - 'WGPUStatus_Error', 'WGPUStatus_Force32', 'WGPUStatus_Success', - 'WGPUStencilFaceState', 'WGPUStencilOperation', - 'WGPUStencilOperation_DecrementClamp', - 'WGPUStencilOperation_DecrementWrap', - 'WGPUStencilOperation_Force32', - 'WGPUStencilOperation_IncrementClamp', - 'WGPUStencilOperation_IncrementWrap', - 'WGPUStencilOperation_Invert', 'WGPUStencilOperation_Keep', - 'WGPUStencilOperation_Replace', 'WGPUStencilOperation_Undefined', - 'WGPUStencilOperation_Zero', 'WGPUStorageTextureAccess', - 'WGPUStorageTextureAccess_BindingNotUsed', - 'WGPUStorageTextureAccess_Force32', - 'WGPUStorageTextureAccess_ReadOnly', - 'WGPUStorageTextureAccess_ReadWrite', - 'WGPUStorageTextureAccess_WriteOnly', - 'WGPUStorageTextureBindingLayout', 'WGPUStoreOp', - 'WGPUStoreOp_Discard', 'WGPUStoreOp_Force32', 'WGPUStoreOp_Store', - 'WGPUStoreOp_Undefined', 'WGPUStringView', - 'WGPUSupportedFeatures', 'WGPUSupportedLimits', 'WGPUSurface', - 'WGPUSurfaceCapabilities', 'WGPUSurfaceConfiguration', - 'WGPUSurfaceDescriptor', - 'WGPUSurfaceDescriptorFromAndroidNativeWindow', - 'WGPUSurfaceDescriptorFromCanvasHTMLSelector', - 'WGPUSurfaceDescriptorFromMetalLayer', - 'WGPUSurfaceDescriptorFromWaylandSurface', - 'WGPUSurfaceDescriptorFromWindowsCoreWindow', - 'WGPUSurfaceDescriptorFromWindowsHWND', - 'WGPUSurfaceDescriptorFromWindowsSwapChainPanel', - 'WGPUSurfaceDescriptorFromXcbWindow', - 'WGPUSurfaceDescriptorFromXlibWindow', - 'WGPUSurfaceGetCurrentTextureStatus', - 'WGPUSurfaceGetCurrentTextureStatus_DeviceLost', - 'WGPUSurfaceGetCurrentTextureStatus_Error', - 'WGPUSurfaceGetCurrentTextureStatus_Force32', - 'WGPUSurfaceGetCurrentTextureStatus_Lost', - 'WGPUSurfaceGetCurrentTextureStatus_OutOfMemory', - 'WGPUSurfaceGetCurrentTextureStatus_Outdated', - 'WGPUSurfaceGetCurrentTextureStatus_Success', - 'WGPUSurfaceGetCurrentTextureStatus_Timeout', - 'WGPUSurfaceSourceAndroidNativeWindow', - 'WGPUSurfaceSourceCanvasHTMLSelector_Emscripten', - 'WGPUSurfaceSourceMetalLayer', 'WGPUSurfaceSourceWaylandSurface', - 'WGPUSurfaceSourceWindowsHWND', 'WGPUSurfaceSourceXCBWindow', - 'WGPUSurfaceSourceXlibWindow', 'WGPUSurfaceTexture', - 'WGPUTexture', 'WGPUTextureAspect', 'WGPUTextureAspect_All', - 'WGPUTextureAspect_DepthOnly', 'WGPUTextureAspect_Force32', - 'WGPUTextureAspect_Plane0Only', 'WGPUTextureAspect_Plane1Only', - 'WGPUTextureAspect_Plane2Only', 'WGPUTextureAspect_StencilOnly', - 'WGPUTextureAspect_Undefined', 'WGPUTextureBindingLayout', - 'WGPUTextureBindingViewDimensionDescriptor', - 'WGPUTextureDataLayout', 'WGPUTextureDescriptor', - 'WGPUTextureDimension', 'WGPUTextureDimension_1D', - 'WGPUTextureDimension_2D', 'WGPUTextureDimension_3D', - 'WGPUTextureDimension_Force32', 'WGPUTextureDimension_Undefined', - 'WGPUTextureFormat', 'WGPUTextureFormat_ASTC10x10Unorm', - 'WGPUTextureFormat_ASTC10x10UnormSrgb', - 'WGPUTextureFormat_ASTC10x5Unorm', - 'WGPUTextureFormat_ASTC10x5UnormSrgb', - 'WGPUTextureFormat_ASTC10x6Unorm', - 'WGPUTextureFormat_ASTC10x6UnormSrgb', - 'WGPUTextureFormat_ASTC10x8Unorm', - 'WGPUTextureFormat_ASTC10x8UnormSrgb', - 'WGPUTextureFormat_ASTC12x10Unorm', - 'WGPUTextureFormat_ASTC12x10UnormSrgb', - 'WGPUTextureFormat_ASTC12x12Unorm', - 'WGPUTextureFormat_ASTC12x12UnormSrgb', - 'WGPUTextureFormat_ASTC4x4Unorm', - 'WGPUTextureFormat_ASTC4x4UnormSrgb', - 'WGPUTextureFormat_ASTC5x4Unorm', - 'WGPUTextureFormat_ASTC5x4UnormSrgb', - 'WGPUTextureFormat_ASTC5x5Unorm', - 'WGPUTextureFormat_ASTC5x5UnormSrgb', - 'WGPUTextureFormat_ASTC6x5Unorm', - 'WGPUTextureFormat_ASTC6x5UnormSrgb', - 'WGPUTextureFormat_ASTC6x6Unorm', - 'WGPUTextureFormat_ASTC6x6UnormSrgb', - 'WGPUTextureFormat_ASTC8x5Unorm', - 'WGPUTextureFormat_ASTC8x5UnormSrgb', - 'WGPUTextureFormat_ASTC8x6Unorm', - 'WGPUTextureFormat_ASTC8x6UnormSrgb', - 'WGPUTextureFormat_ASTC8x8Unorm', - 'WGPUTextureFormat_ASTC8x8UnormSrgb', - 'WGPUTextureFormat_BC1RGBAUnorm', - 'WGPUTextureFormat_BC1RGBAUnormSrgb', - 'WGPUTextureFormat_BC2RGBAUnorm', - 'WGPUTextureFormat_BC2RGBAUnormSrgb', - 'WGPUTextureFormat_BC3RGBAUnorm', - 'WGPUTextureFormat_BC3RGBAUnormSrgb', - 'WGPUTextureFormat_BC4RSnorm', 'WGPUTextureFormat_BC4RUnorm', - 'WGPUTextureFormat_BC5RGSnorm', 'WGPUTextureFormat_BC5RGUnorm', - 'WGPUTextureFormat_BC6HRGBFloat', - 'WGPUTextureFormat_BC6HRGBUfloat', - 'WGPUTextureFormat_BC7RGBAUnorm', - 'WGPUTextureFormat_BC7RGBAUnormSrgb', - 'WGPUTextureFormat_BGRA8Unorm', - 'WGPUTextureFormat_BGRA8UnormSrgb', - 'WGPUTextureFormat_Depth16Unorm', 'WGPUTextureFormat_Depth24Plus', - 'WGPUTextureFormat_Depth24PlusStencil8', - 'WGPUTextureFormat_Depth32Float', - 'WGPUTextureFormat_Depth32FloatStencil8', - 'WGPUTextureFormat_EACR11Snorm', 'WGPUTextureFormat_EACR11Unorm', - 'WGPUTextureFormat_EACRG11Snorm', - 'WGPUTextureFormat_EACRG11Unorm', - 'WGPUTextureFormat_ETC2RGB8A1Unorm', - 'WGPUTextureFormat_ETC2RGB8A1UnormSrgb', - 'WGPUTextureFormat_ETC2RGB8Unorm', - 'WGPUTextureFormat_ETC2RGB8UnormSrgb', - 'WGPUTextureFormat_ETC2RGBA8Unorm', - 'WGPUTextureFormat_ETC2RGBA8UnormSrgb', - 'WGPUTextureFormat_External', 'WGPUTextureFormat_Force32', - 'WGPUTextureFormat_R10X6BG10X6Biplanar420Unorm', - 'WGPUTextureFormat_R10X6BG10X6Biplanar422Unorm', - 'WGPUTextureFormat_R10X6BG10X6Biplanar444Unorm', - 'WGPUTextureFormat_R16Float', 'WGPUTextureFormat_R16Sint', - 'WGPUTextureFormat_R16Snorm', 'WGPUTextureFormat_R16Uint', - 'WGPUTextureFormat_R16Unorm', 'WGPUTextureFormat_R32Float', - 'WGPUTextureFormat_R32Sint', 'WGPUTextureFormat_R32Uint', - 'WGPUTextureFormat_R8BG8A8Triplanar420Unorm', - 'WGPUTextureFormat_R8BG8Biplanar420Unorm', - 'WGPUTextureFormat_R8BG8Biplanar422Unorm', - 'WGPUTextureFormat_R8BG8Biplanar444Unorm', - 'WGPUTextureFormat_R8Sint', 'WGPUTextureFormat_R8Snorm', - 'WGPUTextureFormat_R8Uint', 'WGPUTextureFormat_R8Unorm', - 'WGPUTextureFormat_RG11B10Ufloat', 'WGPUTextureFormat_RG16Float', - 'WGPUTextureFormat_RG16Sint', 'WGPUTextureFormat_RG16Snorm', - 'WGPUTextureFormat_RG16Uint', 'WGPUTextureFormat_RG16Unorm', - 'WGPUTextureFormat_RG32Float', 'WGPUTextureFormat_RG32Sint', - 'WGPUTextureFormat_RG32Uint', 'WGPUTextureFormat_RG8Sint', - 'WGPUTextureFormat_RG8Snorm', 'WGPUTextureFormat_RG8Uint', - 'WGPUTextureFormat_RG8Unorm', 'WGPUTextureFormat_RGB10A2Uint', - 'WGPUTextureFormat_RGB10A2Unorm', - 'WGPUTextureFormat_RGB9E5Ufloat', 'WGPUTextureFormat_RGBA16Float', - 'WGPUTextureFormat_RGBA16Sint', 'WGPUTextureFormat_RGBA16Snorm', - 'WGPUTextureFormat_RGBA16Uint', 'WGPUTextureFormat_RGBA16Unorm', - 'WGPUTextureFormat_RGBA32Float', 'WGPUTextureFormat_RGBA32Sint', - 'WGPUTextureFormat_RGBA32Uint', 'WGPUTextureFormat_RGBA8Sint', - 'WGPUTextureFormat_RGBA8Snorm', 'WGPUTextureFormat_RGBA8Uint', - 'WGPUTextureFormat_RGBA8Unorm', - 'WGPUTextureFormat_RGBA8UnormSrgb', 'WGPUTextureFormat_Stencil8', - 'WGPUTextureFormat_Undefined', 'WGPUTextureSampleType', - 'WGPUTextureSampleType_BindingNotUsed', - 'WGPUTextureSampleType_Depth', 'WGPUTextureSampleType_Float', - 'WGPUTextureSampleType_Force32', 'WGPUTextureSampleType_Sint', - 'WGPUTextureSampleType_Uint', - 'WGPUTextureSampleType_UnfilterableFloat', 'WGPUTextureUsage', - 'WGPUTextureUsage_CopyDst', 'WGPUTextureUsage_CopySrc', - 'WGPUTextureUsage_None', 'WGPUTextureUsage_RenderAttachment', - 'WGPUTextureUsage_StorageAttachment', - 'WGPUTextureUsage_StorageBinding', - 'WGPUTextureUsage_TextureBinding', - 'WGPUTextureUsage_TransientAttachment', 'WGPUTextureView', - 'WGPUTextureViewDescriptor', 'WGPUTextureViewDimension', - 'WGPUTextureViewDimension_1D', 'WGPUTextureViewDimension_2D', - 'WGPUTextureViewDimension_2DArray', 'WGPUTextureViewDimension_3D', - 'WGPUTextureViewDimension_Cube', - 'WGPUTextureViewDimension_CubeArray', - 'WGPUTextureViewDimension_Force32', - 'WGPUTextureViewDimension_Undefined', - 'WGPUUncapturedErrorCallback', 'WGPUUncapturedErrorCallbackInfo', - 'WGPUUncapturedErrorCallbackInfo2', 'WGPUVertexAttribute', - 'WGPUVertexBufferLayout', 'WGPUVertexFormat', - 'WGPUVertexFormat_Float16', 'WGPUVertexFormat_Float16x2', - 'WGPUVertexFormat_Float16x4', 'WGPUVertexFormat_Float32', - 'WGPUVertexFormat_Float32x2', 'WGPUVertexFormat_Float32x3', - 'WGPUVertexFormat_Float32x4', 'WGPUVertexFormat_Force32', - 'WGPUVertexFormat_Sint16', 'WGPUVertexFormat_Sint16x2', - 'WGPUVertexFormat_Sint16x4', 'WGPUVertexFormat_Sint32', - 'WGPUVertexFormat_Sint32x2', 'WGPUVertexFormat_Sint32x3', - 'WGPUVertexFormat_Sint32x4', 'WGPUVertexFormat_Sint8', - 'WGPUVertexFormat_Sint8x2', 'WGPUVertexFormat_Sint8x4', - 'WGPUVertexFormat_Snorm16', 'WGPUVertexFormat_Snorm16x2', - 'WGPUVertexFormat_Snorm16x4', 'WGPUVertexFormat_Snorm8', - 'WGPUVertexFormat_Snorm8x2', 'WGPUVertexFormat_Snorm8x4', - 'WGPUVertexFormat_Uint16', 'WGPUVertexFormat_Uint16x2', - 'WGPUVertexFormat_Uint16x4', 'WGPUVertexFormat_Uint32', - 'WGPUVertexFormat_Uint32x2', 'WGPUVertexFormat_Uint32x3', - 'WGPUVertexFormat_Uint32x4', 'WGPUVertexFormat_Uint8', - 'WGPUVertexFormat_Uint8x2', 'WGPUVertexFormat_Uint8x4', - 'WGPUVertexFormat_Unorm10_10_10_2', 'WGPUVertexFormat_Unorm16', - 'WGPUVertexFormat_Unorm16x2', 'WGPUVertexFormat_Unorm16x4', - 'WGPUVertexFormat_Unorm8', 'WGPUVertexFormat_Unorm8x2', - 'WGPUVertexFormat_Unorm8x4', 'WGPUVertexFormat_Unorm8x4BGRA', - 'WGPUVertexState', 'WGPUVertexStepMode', - 'WGPUVertexStepMode_Force32', 'WGPUVertexStepMode_Instance', - 'WGPUVertexStepMode_Undefined', 'WGPUVertexStepMode_Vertex', - 'WGPUWGSLFeatureName', - 'WGPUWGSLFeatureName_ChromiumTestingExperimental', - 'WGPUWGSLFeatureName_ChromiumTestingShipped', - 'WGPUWGSLFeatureName_ChromiumTestingShippedWithKillswitch', - 'WGPUWGSLFeatureName_ChromiumTestingUnimplemented', - 'WGPUWGSLFeatureName_ChromiumTestingUnsafeExperimental', - 'WGPUWGSLFeatureName_Force32', - 'WGPUWGSLFeatureName_Packed4x8IntegerDotProduct', - 'WGPUWGSLFeatureName_PointerCompositeAccess', - 'WGPUWGSLFeatureName_ReadonlyAndReadwriteStorageTextures', - 'WGPUWGSLFeatureName_UnrestrictedPointerParameters', - 'WGPUWaitStatus', 'WGPUWaitStatus_Force32', - 'WGPUWaitStatus_Success', 'WGPUWaitStatus_TimedOut', - 'WGPUWaitStatus_Unknown', 'WGPUWaitStatus_UnsupportedCount', - 'WGPUWaitStatus_UnsupportedMixedSources', - 'WGPUWaitStatus_UnsupportedTimeout', 'WGPUYCbCrVkDescriptor', - 'int32_t', 'size_t', 'struct_WGPUAHardwareBufferProperties', - 'struct_WGPUAdapterImpl', 'struct_WGPUAdapterInfo', - 'struct_WGPUAdapterPropertiesD3D', - 'struct_WGPUAdapterPropertiesMemoryHeaps', - 'struct_WGPUAdapterPropertiesSubgroups', - 'struct_WGPUAdapterPropertiesVk', - 'struct_WGPUBindGroupDescriptor', 'struct_WGPUBindGroupEntry', - 'struct_WGPUBindGroupImpl', - 'struct_WGPUBindGroupLayoutDescriptor', - 'struct_WGPUBindGroupLayoutEntry', - 'struct_WGPUBindGroupLayoutImpl', 'struct_WGPUBlendComponent', - 'struct_WGPUBlendState', 'struct_WGPUBufferBindingLayout', - 'struct_WGPUBufferDescriptor', - 'struct_WGPUBufferHostMappedPointer', 'struct_WGPUBufferImpl', - 'struct_WGPUBufferMapCallbackInfo', - 'struct_WGPUBufferMapCallbackInfo2', 'struct_WGPUChainedStruct', - 'struct_WGPUChainedStructOut', 'struct_WGPUColor', - 'struct_WGPUColorTargetState', - 'struct_WGPUColorTargetStateExpandResolveTextureDawn', - 'struct_WGPUCommandBufferDescriptor', - 'struct_WGPUCommandBufferImpl', - 'struct_WGPUCommandEncoderDescriptor', - 'struct_WGPUCommandEncoderImpl', 'struct_WGPUCompilationInfo', - 'struct_WGPUCompilationInfoCallbackInfo', - 'struct_WGPUCompilationInfoCallbackInfo2', - 'struct_WGPUCompilationMessage', - 'struct_WGPUComputePassDescriptor', - 'struct_WGPUComputePassEncoderImpl', - 'struct_WGPUComputePassTimestampWrites', - 'struct_WGPUComputePipelineDescriptor', - 'struct_WGPUComputePipelineImpl', 'struct_WGPUComputeState', - 'struct_WGPUConstantEntry', - 'struct_WGPUCopyTextureForBrowserOptions', - 'struct_WGPUCreateComputePipelineAsyncCallbackInfo', - 'struct_WGPUCreateComputePipelineAsyncCallbackInfo2', - 'struct_WGPUCreateRenderPipelineAsyncCallbackInfo', - 'struct_WGPUCreateRenderPipelineAsyncCallbackInfo2', - 'struct_WGPUDawnAdapterPropertiesPowerPreference', - 'struct_WGPUDawnBufferDescriptorErrorInfoFromWireClient', - 'struct_WGPUDawnCacheDeviceDescriptor', - 'struct_WGPUDawnEncoderInternalUsageDescriptor', - 'struct_WGPUDawnExperimentalImmediateDataLimits', - 'struct_WGPUDawnExperimentalSubgroupLimits', - 'struct_WGPUDawnRenderPassColorAttachmentRenderToSingleSampled', - 'struct_WGPUDawnShaderModuleSPIRVOptionsDescriptor', - 'struct_WGPUDawnTexelCopyBufferRowAlignmentLimits', - 'struct_WGPUDawnTextureInternalUsageDescriptor', - 'struct_WGPUDawnTogglesDescriptor', - 'struct_WGPUDawnWGSLBlocklist', 'struct_WGPUDawnWireWGSLControl', - 'struct_WGPUDepthStencilState', 'struct_WGPUDeviceDescriptor', - 'struct_WGPUDeviceImpl', 'struct_WGPUDeviceLostCallbackInfo', - 'struct_WGPUDeviceLostCallbackInfo2', - 'struct_WGPUDrmFormatCapabilities', - 'struct_WGPUDrmFormatProperties', 'struct_WGPUExtent2D', - 'struct_WGPUExtent3D', 'struct_WGPUExternalTextureBindingEntry', - 'struct_WGPUExternalTextureBindingLayout', - 'struct_WGPUExternalTextureDescriptor', - 'struct_WGPUExternalTextureImpl', 'struct_WGPUFormatCapabilities', - 'struct_WGPUFragmentState', 'struct_WGPUFuture', - 'struct_WGPUFutureWaitInfo', - 'struct_WGPUINTERNAL__HAVE_EMDAWNWEBGPU_HEADER', - 'struct_WGPUImageCopyBuffer', - 'struct_WGPUImageCopyExternalTexture', - 'struct_WGPUImageCopyTexture', 'struct_WGPUInstanceDescriptor', - 'struct_WGPUInstanceFeatures', 'struct_WGPUInstanceImpl', - 'struct_WGPULimits', 'struct_WGPUMemoryHeapInfo', - 'struct_WGPUMultisampleState', 'struct_WGPUOrigin2D', - 'struct_WGPUOrigin3D', 'struct_WGPUPipelineLayoutDescriptor', - 'struct_WGPUPipelineLayoutImpl', - 'struct_WGPUPipelineLayoutPixelLocalStorage', - 'struct_WGPUPipelineLayoutStorageAttachment', - 'struct_WGPUPopErrorScopeCallbackInfo', - 'struct_WGPUPopErrorScopeCallbackInfo2', - 'struct_WGPUPrimitiveState', 'struct_WGPUQuerySetDescriptor', - 'struct_WGPUQuerySetImpl', 'struct_WGPUQueueDescriptor', - 'struct_WGPUQueueImpl', 'struct_WGPUQueueWorkDoneCallbackInfo', - 'struct_WGPUQueueWorkDoneCallbackInfo2', - 'struct_WGPURenderBundleDescriptor', - 'struct_WGPURenderBundleEncoderDescriptor', - 'struct_WGPURenderBundleEncoderImpl', - 'struct_WGPURenderBundleImpl', - 'struct_WGPURenderPassColorAttachment', - 'struct_WGPURenderPassDepthStencilAttachment', - 'struct_WGPURenderPassDescriptor', - 'struct_WGPURenderPassDescriptorExpandResolveRect', - 'struct_WGPURenderPassEncoderImpl', - 'struct_WGPURenderPassMaxDrawCount', - 'struct_WGPURenderPassPixelLocalStorage', - 'struct_WGPURenderPassStorageAttachment', - 'struct_WGPURenderPassTimestampWrites', - 'struct_WGPURenderPipelineDescriptor', - 'struct_WGPURenderPipelineImpl', - 'struct_WGPURequestAdapterCallbackInfo', - 'struct_WGPURequestAdapterCallbackInfo2', - 'struct_WGPURequestAdapterOptions', - 'struct_WGPURequestDeviceCallbackInfo', - 'struct_WGPURequestDeviceCallbackInfo2', - 'struct_WGPURequiredLimits', 'struct_WGPUSamplerBindingLayout', - 'struct_WGPUSamplerDescriptor', 'struct_WGPUSamplerImpl', - 'struct_WGPUShaderModuleCompilationOptions', - 'struct_WGPUShaderModuleDescriptor', - 'struct_WGPUShaderModuleImpl', 'struct_WGPUShaderSourceSPIRV', - 'struct_WGPUShaderSourceWGSL', - 'struct_WGPUSharedBufferMemoryBeginAccessDescriptor', - 'struct_WGPUSharedBufferMemoryDescriptor', - 'struct_WGPUSharedBufferMemoryEndAccessState', - 'struct_WGPUSharedBufferMemoryImpl', - 'struct_WGPUSharedBufferMemoryProperties', - 'struct_WGPUSharedFenceDXGISharedHandleDescriptor', - 'struct_WGPUSharedFenceDXGISharedHandleExportInfo', - 'struct_WGPUSharedFenceDescriptor', - 'struct_WGPUSharedFenceExportInfo', 'struct_WGPUSharedFenceImpl', - 'struct_WGPUSharedFenceMTLSharedEventDescriptor', - 'struct_WGPUSharedFenceMTLSharedEventExportInfo', - 'struct_WGPUSharedFenceSyncFDDescriptor', - 'struct_WGPUSharedFenceSyncFDExportInfo', - 'struct_WGPUSharedFenceVkSemaphoreOpaqueFDDescriptor', - 'struct_WGPUSharedFenceVkSemaphoreOpaqueFDExportInfo', - 'struct_WGPUSharedFenceVkSemaphoreZirconHandleDescriptor', - 'struct_WGPUSharedFenceVkSemaphoreZirconHandleExportInfo', - 'struct_WGPUSharedTextureMemoryAHardwareBufferDescriptor', - 'struct_WGPUSharedTextureMemoryAHardwareBufferProperties', - 'struct_WGPUSharedTextureMemoryBeginAccessDescriptor', - 'struct_WGPUSharedTextureMemoryD3DSwapchainBeginState', - 'struct_WGPUSharedTextureMemoryDXGISharedHandleDescriptor', - 'struct_WGPUSharedTextureMemoryDescriptor', - 'struct_WGPUSharedTextureMemoryDmaBufDescriptor', - 'struct_WGPUSharedTextureMemoryDmaBufPlane', - 'struct_WGPUSharedTextureMemoryEGLImageDescriptor', - 'struct_WGPUSharedTextureMemoryEndAccessState', - 'struct_WGPUSharedTextureMemoryIOSurfaceDescriptor', - 'struct_WGPUSharedTextureMemoryImpl', - 'struct_WGPUSharedTextureMemoryOpaqueFDDescriptor', - 'struct_WGPUSharedTextureMemoryProperties', - 'struct_WGPUSharedTextureMemoryVkDedicatedAllocationDescriptor', - 'struct_WGPUSharedTextureMemoryVkImageLayoutBeginState', - 'struct_WGPUSharedTextureMemoryVkImageLayoutEndState', - 'struct_WGPUSharedTextureMemoryZirconHandleDescriptor', - 'struct_WGPUStaticSamplerBindingLayout', - 'struct_WGPUStencilFaceState', - 'struct_WGPUStorageTextureBindingLayout', 'struct_WGPUStringView', - 'struct_WGPUSupportedFeatures', 'struct_WGPUSupportedLimits', - 'struct_WGPUSurfaceCapabilities', - 'struct_WGPUSurfaceConfiguration', 'struct_WGPUSurfaceDescriptor', - 'struct_WGPUSurfaceDescriptorFromWindowsCoreWindow', - 'struct_WGPUSurfaceDescriptorFromWindowsSwapChainPanel', - 'struct_WGPUSurfaceImpl', - 'struct_WGPUSurfaceSourceAndroidNativeWindow', - 'struct_WGPUSurfaceSourceCanvasHTMLSelector_Emscripten', - 'struct_WGPUSurfaceSourceMetalLayer', - 'struct_WGPUSurfaceSourceWaylandSurface', - 'struct_WGPUSurfaceSourceWindowsHWND', - 'struct_WGPUSurfaceSourceXCBWindow', - 'struct_WGPUSurfaceSourceXlibWindow', 'struct_WGPUSurfaceTexture', - 'struct_WGPUTextureBindingLayout', - 'struct_WGPUTextureBindingViewDimensionDescriptor', - 'struct_WGPUTextureDataLayout', 'struct_WGPUTextureDescriptor', - 'struct_WGPUTextureImpl', 'struct_WGPUTextureViewDescriptor', - 'struct_WGPUTextureViewImpl', - 'struct_WGPUUncapturedErrorCallbackInfo', - 'struct_WGPUUncapturedErrorCallbackInfo2', - 'struct_WGPUVertexAttribute', 'struct_WGPUVertexBufferLayout', - 'struct_WGPUVertexState', 'struct_WGPUYCbCrVkDescriptor', - 'uint32_t', 'uint64_t', 'wgpuAdapterAddRef', - 'wgpuAdapterCreateDevice', 'wgpuAdapterGetFeatures', - 'wgpuAdapterGetFormatCapabilities', 'wgpuAdapterGetInfo', - 'wgpuAdapterGetInstance', 'wgpuAdapterGetLimits', - 'wgpuAdapterHasFeature', 'wgpuAdapterInfoFreeMembers', - 'wgpuAdapterPropertiesMemoryHeapsFreeMembers', - 'wgpuAdapterRelease', 'wgpuAdapterRequestDevice', - 'wgpuAdapterRequestDevice2', 'wgpuAdapterRequestDeviceF', - 'wgpuBindGroupAddRef', 'wgpuBindGroupLayoutAddRef', - 'wgpuBindGroupLayoutRelease', 'wgpuBindGroupLayoutSetLabel', - 'wgpuBindGroupRelease', 'wgpuBindGroupSetLabel', - 'wgpuBufferAddRef', 'wgpuBufferDestroy', - 'wgpuBufferGetConstMappedRange', 'wgpuBufferGetMapState', - 'wgpuBufferGetMappedRange', 'wgpuBufferGetSize', - 'wgpuBufferGetUsage', 'wgpuBufferMapAsync', 'wgpuBufferMapAsync2', - 'wgpuBufferMapAsyncF', 'wgpuBufferRelease', 'wgpuBufferSetLabel', - 'wgpuBufferUnmap', 'wgpuCommandBufferAddRef', - 'wgpuCommandBufferRelease', 'wgpuCommandBufferSetLabel', - 'wgpuCommandEncoderAddRef', 'wgpuCommandEncoderBeginComputePass', - 'wgpuCommandEncoderBeginRenderPass', - 'wgpuCommandEncoderClearBuffer', - 'wgpuCommandEncoderCopyBufferToBuffer', - 'wgpuCommandEncoderCopyBufferToTexture', - 'wgpuCommandEncoderCopyTextureToBuffer', - 'wgpuCommandEncoderCopyTextureToTexture', - 'wgpuCommandEncoderFinish', - 'wgpuCommandEncoderInjectValidationError', - 'wgpuCommandEncoderInsertDebugMarker', - 'wgpuCommandEncoderPopDebugGroup', - 'wgpuCommandEncoderPushDebugGroup', 'wgpuCommandEncoderRelease', - 'wgpuCommandEncoderResolveQuerySet', 'wgpuCommandEncoderSetLabel', - 'wgpuCommandEncoderWriteBuffer', - 'wgpuCommandEncoderWriteTimestamp', - 'wgpuComputePassEncoderAddRef', - 'wgpuComputePassEncoderDispatchWorkgroups', - 'wgpuComputePassEncoderDispatchWorkgroupsIndirect', - 'wgpuComputePassEncoderEnd', - 'wgpuComputePassEncoderInsertDebugMarker', - 'wgpuComputePassEncoderPopDebugGroup', - 'wgpuComputePassEncoderPushDebugGroup', - 'wgpuComputePassEncoderRelease', - 'wgpuComputePassEncoderSetBindGroup', - 'wgpuComputePassEncoderSetLabel', - 'wgpuComputePassEncoderSetPipeline', - 'wgpuComputePassEncoderWriteTimestamp', - 'wgpuComputePipelineAddRef', - 'wgpuComputePipelineGetBindGroupLayout', - 'wgpuComputePipelineRelease', 'wgpuComputePipelineSetLabel', - 'wgpuCreateInstance', 'wgpuDeviceAddRef', - 'wgpuDeviceCreateBindGroup', 'wgpuDeviceCreateBindGroupLayout', - 'wgpuDeviceCreateBuffer', 'wgpuDeviceCreateCommandEncoder', - 'wgpuDeviceCreateComputePipeline', - 'wgpuDeviceCreateComputePipelineAsync', - 'wgpuDeviceCreateComputePipelineAsync2', - 'wgpuDeviceCreateComputePipelineAsyncF', - 'wgpuDeviceCreateErrorBuffer', - 'wgpuDeviceCreateErrorExternalTexture', - 'wgpuDeviceCreateErrorShaderModule', - 'wgpuDeviceCreateErrorTexture', 'wgpuDeviceCreateExternalTexture', - 'wgpuDeviceCreatePipelineLayout', 'wgpuDeviceCreateQuerySet', - 'wgpuDeviceCreateRenderBundleEncoder', - 'wgpuDeviceCreateRenderPipeline', - 'wgpuDeviceCreateRenderPipelineAsync', - 'wgpuDeviceCreateRenderPipelineAsync2', - 'wgpuDeviceCreateRenderPipelineAsyncF', 'wgpuDeviceCreateSampler', - 'wgpuDeviceCreateShaderModule', 'wgpuDeviceCreateTexture', - 'wgpuDeviceDestroy', 'wgpuDeviceForceLoss', - 'wgpuDeviceGetAHardwareBufferProperties', 'wgpuDeviceGetAdapter', - 'wgpuDeviceGetAdapterInfo', 'wgpuDeviceGetFeatures', - 'wgpuDeviceGetLimits', 'wgpuDeviceGetLostFuture', - 'wgpuDeviceGetQueue', 'wgpuDeviceHasFeature', - 'wgpuDeviceImportSharedBufferMemory', - 'wgpuDeviceImportSharedFence', - 'wgpuDeviceImportSharedTextureMemory', 'wgpuDeviceInjectError', - 'wgpuDevicePopErrorScope', 'wgpuDevicePopErrorScope2', - 'wgpuDevicePopErrorScopeF', 'wgpuDevicePushErrorScope', - 'wgpuDeviceRelease', 'wgpuDeviceSetLabel', - 'wgpuDeviceSetLoggingCallback', 'wgpuDeviceTick', - 'wgpuDeviceValidateTextureDescriptor', - 'wgpuDrmFormatCapabilitiesFreeMembers', - 'wgpuExternalTextureAddRef', 'wgpuExternalTextureDestroy', - 'wgpuExternalTextureExpire', 'wgpuExternalTextureRefresh', - 'wgpuExternalTextureRelease', 'wgpuExternalTextureSetLabel', - 'wgpuGetInstanceFeatures', 'wgpuGetProcAddress', - 'wgpuInstanceAddRef', 'wgpuInstanceCreateSurface', - 'wgpuInstanceEnumerateWGSLLanguageFeatures', - 'wgpuInstanceHasWGSLLanguageFeature', 'wgpuInstanceProcessEvents', - 'wgpuInstanceRelease', 'wgpuInstanceRequestAdapter', - 'wgpuInstanceRequestAdapter2', 'wgpuInstanceRequestAdapterF', - 'wgpuInstanceWaitAny', 'wgpuPipelineLayoutAddRef', - 'wgpuPipelineLayoutRelease', 'wgpuPipelineLayoutSetLabel', - 'wgpuQuerySetAddRef', 'wgpuQuerySetDestroy', - 'wgpuQuerySetGetCount', 'wgpuQuerySetGetType', - 'wgpuQuerySetRelease', 'wgpuQuerySetSetLabel', 'wgpuQueueAddRef', - 'wgpuQueueCopyExternalTextureForBrowser', - 'wgpuQueueCopyTextureForBrowser', 'wgpuQueueOnSubmittedWorkDone', - 'wgpuQueueOnSubmittedWorkDone2', 'wgpuQueueOnSubmittedWorkDoneF', - 'wgpuQueueRelease', 'wgpuQueueSetLabel', 'wgpuQueueSubmit', - 'wgpuQueueWriteBuffer', 'wgpuQueueWriteTexture', - 'wgpuRenderBundleAddRef', 'wgpuRenderBundleEncoderAddRef', - 'wgpuRenderBundleEncoderDraw', - 'wgpuRenderBundleEncoderDrawIndexed', - 'wgpuRenderBundleEncoderDrawIndexedIndirect', - 'wgpuRenderBundleEncoderDrawIndirect', - 'wgpuRenderBundleEncoderFinish', - 'wgpuRenderBundleEncoderInsertDebugMarker', - 'wgpuRenderBundleEncoderPopDebugGroup', - 'wgpuRenderBundleEncoderPushDebugGroup', - 'wgpuRenderBundleEncoderRelease', - 'wgpuRenderBundleEncoderSetBindGroup', - 'wgpuRenderBundleEncoderSetIndexBuffer', - 'wgpuRenderBundleEncoderSetLabel', - 'wgpuRenderBundleEncoderSetPipeline', - 'wgpuRenderBundleEncoderSetVertexBuffer', - 'wgpuRenderBundleRelease', 'wgpuRenderBundleSetLabel', - 'wgpuRenderPassEncoderAddRef', - 'wgpuRenderPassEncoderBeginOcclusionQuery', - 'wgpuRenderPassEncoderDraw', 'wgpuRenderPassEncoderDrawIndexed', - 'wgpuRenderPassEncoderDrawIndexedIndirect', - 'wgpuRenderPassEncoderDrawIndirect', 'wgpuRenderPassEncoderEnd', - 'wgpuRenderPassEncoderEndOcclusionQuery', - 'wgpuRenderPassEncoderExecuteBundles', - 'wgpuRenderPassEncoderInsertDebugMarker', - 'wgpuRenderPassEncoderMultiDrawIndexedIndirect', - 'wgpuRenderPassEncoderMultiDrawIndirect', - 'wgpuRenderPassEncoderPixelLocalStorageBarrier', - 'wgpuRenderPassEncoderPopDebugGroup', - 'wgpuRenderPassEncoderPushDebugGroup', - 'wgpuRenderPassEncoderRelease', - 'wgpuRenderPassEncoderSetBindGroup', - 'wgpuRenderPassEncoderSetBlendConstant', - 'wgpuRenderPassEncoderSetIndexBuffer', - 'wgpuRenderPassEncoderSetLabel', - 'wgpuRenderPassEncoderSetPipeline', - 'wgpuRenderPassEncoderSetScissorRect', - 'wgpuRenderPassEncoderSetStencilReference', - 'wgpuRenderPassEncoderSetVertexBuffer', - 'wgpuRenderPassEncoderSetViewport', - 'wgpuRenderPassEncoderWriteTimestamp', 'wgpuRenderPipelineAddRef', - 'wgpuRenderPipelineGetBindGroupLayout', - 'wgpuRenderPipelineRelease', 'wgpuRenderPipelineSetLabel', - 'wgpuSamplerAddRef', 'wgpuSamplerRelease', 'wgpuSamplerSetLabel', - 'wgpuShaderModuleAddRef', 'wgpuShaderModuleGetCompilationInfo', - 'wgpuShaderModuleGetCompilationInfo2', - 'wgpuShaderModuleGetCompilationInfoF', 'wgpuShaderModuleRelease', - 'wgpuShaderModuleSetLabel', 'wgpuSharedBufferMemoryAddRef', - 'wgpuSharedBufferMemoryBeginAccess', - 'wgpuSharedBufferMemoryCreateBuffer', - 'wgpuSharedBufferMemoryEndAccess', - 'wgpuSharedBufferMemoryEndAccessStateFreeMembers', - 'wgpuSharedBufferMemoryGetProperties', - 'wgpuSharedBufferMemoryIsDeviceLost', - 'wgpuSharedBufferMemoryRelease', 'wgpuSharedBufferMemorySetLabel', - 'wgpuSharedFenceAddRef', 'wgpuSharedFenceExportInfo', - 'wgpuSharedFenceRelease', 'wgpuSharedTextureMemoryAddRef', - 'wgpuSharedTextureMemoryBeginAccess', - 'wgpuSharedTextureMemoryCreateTexture', - 'wgpuSharedTextureMemoryEndAccess', - 'wgpuSharedTextureMemoryEndAccessStateFreeMembers', - 'wgpuSharedTextureMemoryGetProperties', - 'wgpuSharedTextureMemoryIsDeviceLost', - 'wgpuSharedTextureMemoryRelease', - 'wgpuSharedTextureMemorySetLabel', - 'wgpuSupportedFeaturesFreeMembers', 'wgpuSurfaceAddRef', - 'wgpuSurfaceCapabilitiesFreeMembers', 'wgpuSurfaceConfigure', - 'wgpuSurfaceGetCapabilities', 'wgpuSurfaceGetCurrentTexture', - 'wgpuSurfacePresent', 'wgpuSurfaceRelease', 'wgpuSurfaceSetLabel', - 'wgpuSurfaceUnconfigure', 'wgpuTextureAddRef', - 'wgpuTextureCreateErrorView', 'wgpuTextureCreateView', - 'wgpuTextureDestroy', 'wgpuTextureGetDepthOrArrayLayers', - 'wgpuTextureGetDimension', 'wgpuTextureGetFormat', - 'wgpuTextureGetHeight', 'wgpuTextureGetMipLevelCount', - 'wgpuTextureGetSampleCount', 'wgpuTextureGetUsage', - 'wgpuTextureGetWidth', 'wgpuTextureRelease', - 'wgpuTextureSetLabel', 'wgpuTextureViewAddRef', - 'wgpuTextureViewRelease', 'wgpuTextureViewSetLabel'] +# void wgpuAdapterInfoFreeMembers(WGPUAdapterInfo value) +try: (wgpuAdapterInfoFreeMembers:=dll.wgpuAdapterInfoFreeMembers).restype, wgpuAdapterInfoFreeMembers.argtypes = None, [WGPUAdapterInfo] +except AttributeError: pass + +# void wgpuAdapterPropertiesMemoryHeapsFreeMembers(WGPUAdapterPropertiesMemoryHeaps value) +try: (wgpuAdapterPropertiesMemoryHeapsFreeMembers:=dll.wgpuAdapterPropertiesMemoryHeapsFreeMembers).restype, wgpuAdapterPropertiesMemoryHeapsFreeMembers.argtypes = None, [WGPUAdapterPropertiesMemoryHeaps] +except AttributeError: pass + +# WGPUInstance wgpuCreateInstance(const WGPUInstanceDescriptor *descriptor) +try: (wgpuCreateInstance:=dll.wgpuCreateInstance).restype, wgpuCreateInstance.argtypes = WGPUInstance, [ctypes.POINTER(WGPUInstanceDescriptor)] +except AttributeError: pass + +# void wgpuDrmFormatCapabilitiesFreeMembers(WGPUDrmFormatCapabilities value) +try: (wgpuDrmFormatCapabilitiesFreeMembers:=dll.wgpuDrmFormatCapabilitiesFreeMembers).restype, wgpuDrmFormatCapabilitiesFreeMembers.argtypes = None, [WGPUDrmFormatCapabilities] +except AttributeError: pass + +# WGPUStatus wgpuGetInstanceFeatures(WGPUInstanceFeatures *features) +try: (wgpuGetInstanceFeatures:=dll.wgpuGetInstanceFeatures).restype, wgpuGetInstanceFeatures.argtypes = WGPUStatus, [ctypes.POINTER(WGPUInstanceFeatures)] +except AttributeError: pass + +# WGPUProc wgpuGetProcAddress(WGPUStringView procName) +try: (wgpuGetProcAddress:=dll.wgpuGetProcAddress).restype, wgpuGetProcAddress.argtypes = WGPUProc, [WGPUStringView] +except AttributeError: pass + +# void wgpuSharedBufferMemoryEndAccessStateFreeMembers(WGPUSharedBufferMemoryEndAccessState value) +try: (wgpuSharedBufferMemoryEndAccessStateFreeMembers:=dll.wgpuSharedBufferMemoryEndAccessStateFreeMembers).restype, wgpuSharedBufferMemoryEndAccessStateFreeMembers.argtypes = None, [WGPUSharedBufferMemoryEndAccessState] +except AttributeError: pass + +# void wgpuSharedTextureMemoryEndAccessStateFreeMembers(WGPUSharedTextureMemoryEndAccessState value) +try: (wgpuSharedTextureMemoryEndAccessStateFreeMembers:=dll.wgpuSharedTextureMemoryEndAccessStateFreeMembers).restype, wgpuSharedTextureMemoryEndAccessStateFreeMembers.argtypes = None, [WGPUSharedTextureMemoryEndAccessState] +except AttributeError: pass + +# void wgpuSupportedFeaturesFreeMembers(WGPUSupportedFeatures value) +try: (wgpuSupportedFeaturesFreeMembers:=dll.wgpuSupportedFeaturesFreeMembers).restype, wgpuSupportedFeaturesFreeMembers.argtypes = None, [WGPUSupportedFeatures] +except AttributeError: pass + +# void wgpuSurfaceCapabilitiesFreeMembers(WGPUSurfaceCapabilities value) +try: (wgpuSurfaceCapabilitiesFreeMembers:=dll.wgpuSurfaceCapabilitiesFreeMembers).restype, wgpuSurfaceCapabilitiesFreeMembers.argtypes = None, [WGPUSurfaceCapabilities] +except AttributeError: pass + +# WGPUDevice wgpuAdapterCreateDevice(WGPUAdapter adapter, const WGPUDeviceDescriptor *descriptor) +try: (wgpuAdapterCreateDevice:=dll.wgpuAdapterCreateDevice).restype, wgpuAdapterCreateDevice.argtypes = WGPUDevice, [WGPUAdapter, ctypes.POINTER(WGPUDeviceDescriptor)] +except AttributeError: pass + +# void wgpuAdapterGetFeatures(WGPUAdapter adapter, WGPUSupportedFeatures *features) +try: (wgpuAdapterGetFeatures:=dll.wgpuAdapterGetFeatures).restype, wgpuAdapterGetFeatures.argtypes = None, [WGPUAdapter, ctypes.POINTER(WGPUSupportedFeatures)] +except AttributeError: pass + +# WGPUStatus wgpuAdapterGetFormatCapabilities(WGPUAdapter adapter, WGPUTextureFormat format, WGPUFormatCapabilities *capabilities) +try: (wgpuAdapterGetFormatCapabilities:=dll.wgpuAdapterGetFormatCapabilities).restype, wgpuAdapterGetFormatCapabilities.argtypes = WGPUStatus, [WGPUAdapter, WGPUTextureFormat, ctypes.POINTER(WGPUFormatCapabilities)] +except AttributeError: pass + +# WGPUStatus wgpuAdapterGetInfo(WGPUAdapter adapter, WGPUAdapterInfo *info) +try: (wgpuAdapterGetInfo:=dll.wgpuAdapterGetInfo).restype, wgpuAdapterGetInfo.argtypes = WGPUStatus, [WGPUAdapter, ctypes.POINTER(WGPUAdapterInfo)] +except AttributeError: pass + +# WGPUInstance wgpuAdapterGetInstance(WGPUAdapter adapter) +try: (wgpuAdapterGetInstance:=dll.wgpuAdapterGetInstance).restype, wgpuAdapterGetInstance.argtypes = WGPUInstance, [WGPUAdapter] +except AttributeError: pass + +# WGPUStatus wgpuAdapterGetLimits(WGPUAdapter adapter, WGPUSupportedLimits *limits) +try: (wgpuAdapterGetLimits:=dll.wgpuAdapterGetLimits).restype, wgpuAdapterGetLimits.argtypes = WGPUStatus, [WGPUAdapter, ctypes.POINTER(WGPUSupportedLimits)] +except AttributeError: pass + +# WGPUBool wgpuAdapterHasFeature(WGPUAdapter adapter, WGPUFeatureName feature) +try: (wgpuAdapterHasFeature:=dll.wgpuAdapterHasFeature).restype, wgpuAdapterHasFeature.argtypes = WGPUBool, [WGPUAdapter, WGPUFeatureName] +except AttributeError: pass + +# void wgpuAdapterRequestDevice(WGPUAdapter adapter, const WGPUDeviceDescriptor *descriptor, WGPURequestDeviceCallback callback, void *userdata) +try: (wgpuAdapterRequestDevice:=dll.wgpuAdapterRequestDevice).restype, wgpuAdapterRequestDevice.argtypes = None, [WGPUAdapter, ctypes.POINTER(WGPUDeviceDescriptor), WGPURequestDeviceCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuAdapterRequestDevice2(WGPUAdapter adapter, const WGPUDeviceDescriptor *options, WGPURequestDeviceCallbackInfo2 callbackInfo) +try: (wgpuAdapterRequestDevice2:=dll.wgpuAdapterRequestDevice2).restype, wgpuAdapterRequestDevice2.argtypes = WGPUFuture, [WGPUAdapter, ctypes.POINTER(WGPUDeviceDescriptor), WGPURequestDeviceCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuAdapterRequestDeviceF(WGPUAdapter adapter, const WGPUDeviceDescriptor *options, WGPURequestDeviceCallbackInfo callbackInfo) +try: (wgpuAdapterRequestDeviceF:=dll.wgpuAdapterRequestDeviceF).restype, wgpuAdapterRequestDeviceF.argtypes = WGPUFuture, [WGPUAdapter, ctypes.POINTER(WGPUDeviceDescriptor), WGPURequestDeviceCallbackInfo] +except AttributeError: pass + +# void wgpuAdapterAddRef(WGPUAdapter adapter) +try: (wgpuAdapterAddRef:=dll.wgpuAdapterAddRef).restype, wgpuAdapterAddRef.argtypes = None, [WGPUAdapter] +except AttributeError: pass + +# void wgpuAdapterRelease(WGPUAdapter adapter) +try: (wgpuAdapterRelease:=dll.wgpuAdapterRelease).restype, wgpuAdapterRelease.argtypes = None, [WGPUAdapter] +except AttributeError: pass + +# void wgpuBindGroupSetLabel(WGPUBindGroup bindGroup, WGPUStringView label) +try: (wgpuBindGroupSetLabel:=dll.wgpuBindGroupSetLabel).restype, wgpuBindGroupSetLabel.argtypes = None, [WGPUBindGroup, WGPUStringView] +except AttributeError: pass + +# void wgpuBindGroupAddRef(WGPUBindGroup bindGroup) +try: (wgpuBindGroupAddRef:=dll.wgpuBindGroupAddRef).restype, wgpuBindGroupAddRef.argtypes = None, [WGPUBindGroup] +except AttributeError: pass + +# void wgpuBindGroupRelease(WGPUBindGroup bindGroup) +try: (wgpuBindGroupRelease:=dll.wgpuBindGroupRelease).restype, wgpuBindGroupRelease.argtypes = None, [WGPUBindGroup] +except AttributeError: pass + +# void wgpuBindGroupLayoutSetLabel(WGPUBindGroupLayout bindGroupLayout, WGPUStringView label) +try: (wgpuBindGroupLayoutSetLabel:=dll.wgpuBindGroupLayoutSetLabel).restype, wgpuBindGroupLayoutSetLabel.argtypes = None, [WGPUBindGroupLayout, WGPUStringView] +except AttributeError: pass + +# void wgpuBindGroupLayoutAddRef(WGPUBindGroupLayout bindGroupLayout) +try: (wgpuBindGroupLayoutAddRef:=dll.wgpuBindGroupLayoutAddRef).restype, wgpuBindGroupLayoutAddRef.argtypes = None, [WGPUBindGroupLayout] +except AttributeError: pass + +# void wgpuBindGroupLayoutRelease(WGPUBindGroupLayout bindGroupLayout) +try: (wgpuBindGroupLayoutRelease:=dll.wgpuBindGroupLayoutRelease).restype, wgpuBindGroupLayoutRelease.argtypes = None, [WGPUBindGroupLayout] +except AttributeError: pass + +# void wgpuBufferDestroy(WGPUBuffer buffer) +try: (wgpuBufferDestroy:=dll.wgpuBufferDestroy).restype, wgpuBufferDestroy.argtypes = None, [WGPUBuffer] +except AttributeError: pass + +# const void *wgpuBufferGetConstMappedRange(WGPUBuffer buffer, size_t offset, size_t size) +try: (wgpuBufferGetConstMappedRange:=dll.wgpuBufferGetConstMappedRange).restype, wgpuBufferGetConstMappedRange.argtypes = ctypes.c_void_p, [WGPUBuffer, size_t, size_t] +except AttributeError: pass + +# WGPUBufferMapState wgpuBufferGetMapState(WGPUBuffer buffer) +try: (wgpuBufferGetMapState:=dll.wgpuBufferGetMapState).restype, wgpuBufferGetMapState.argtypes = WGPUBufferMapState, [WGPUBuffer] +except AttributeError: pass + +# void *wgpuBufferGetMappedRange(WGPUBuffer buffer, size_t offset, size_t size) +try: (wgpuBufferGetMappedRange:=dll.wgpuBufferGetMappedRange).restype, wgpuBufferGetMappedRange.argtypes = ctypes.c_void_p, [WGPUBuffer, size_t, size_t] +except AttributeError: pass + +# uint64_t wgpuBufferGetSize(WGPUBuffer buffer) +try: (wgpuBufferGetSize:=dll.wgpuBufferGetSize).restype, wgpuBufferGetSize.argtypes = uint64_t, [WGPUBuffer] +except AttributeError: pass + +# WGPUBufferUsage wgpuBufferGetUsage(WGPUBuffer buffer) +try: (wgpuBufferGetUsage:=dll.wgpuBufferGetUsage).restype, wgpuBufferGetUsage.argtypes = WGPUBufferUsage, [WGPUBuffer] +except AttributeError: pass + +# void wgpuBufferMapAsync(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallback callback, void *userdata) +try: (wgpuBufferMapAsync:=dll.wgpuBufferMapAsync).restype, wgpuBufferMapAsync.argtypes = None, [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuBufferMapAsync2(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallbackInfo2 callbackInfo) +try: (wgpuBufferMapAsync2:=dll.wgpuBufferMapAsync2).restype, wgpuBufferMapAsync2.argtypes = WGPUFuture, [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuBufferMapAsyncF(WGPUBuffer buffer, WGPUMapMode mode, size_t offset, size_t size, WGPUBufferMapCallbackInfo callbackInfo) +try: (wgpuBufferMapAsyncF:=dll.wgpuBufferMapAsyncF).restype, wgpuBufferMapAsyncF.argtypes = WGPUFuture, [WGPUBuffer, WGPUMapMode, size_t, size_t, WGPUBufferMapCallbackInfo] +except AttributeError: pass + +# void wgpuBufferSetLabel(WGPUBuffer buffer, WGPUStringView label) +try: (wgpuBufferSetLabel:=dll.wgpuBufferSetLabel).restype, wgpuBufferSetLabel.argtypes = None, [WGPUBuffer, WGPUStringView] +except AttributeError: pass + +# void wgpuBufferUnmap(WGPUBuffer buffer) +try: (wgpuBufferUnmap:=dll.wgpuBufferUnmap).restype, wgpuBufferUnmap.argtypes = None, [WGPUBuffer] +except AttributeError: pass + +# void wgpuBufferAddRef(WGPUBuffer buffer) +try: (wgpuBufferAddRef:=dll.wgpuBufferAddRef).restype, wgpuBufferAddRef.argtypes = None, [WGPUBuffer] +except AttributeError: pass + +# void wgpuBufferRelease(WGPUBuffer buffer) +try: (wgpuBufferRelease:=dll.wgpuBufferRelease).restype, wgpuBufferRelease.argtypes = None, [WGPUBuffer] +except AttributeError: pass + +# void wgpuCommandBufferSetLabel(WGPUCommandBuffer commandBuffer, WGPUStringView label) +try: (wgpuCommandBufferSetLabel:=dll.wgpuCommandBufferSetLabel).restype, wgpuCommandBufferSetLabel.argtypes = None, [WGPUCommandBuffer, WGPUStringView] +except AttributeError: pass + +# void wgpuCommandBufferAddRef(WGPUCommandBuffer commandBuffer) +try: (wgpuCommandBufferAddRef:=dll.wgpuCommandBufferAddRef).restype, wgpuCommandBufferAddRef.argtypes = None, [WGPUCommandBuffer] +except AttributeError: pass + +# void wgpuCommandBufferRelease(WGPUCommandBuffer commandBuffer) +try: (wgpuCommandBufferRelease:=dll.wgpuCommandBufferRelease).restype, wgpuCommandBufferRelease.argtypes = None, [WGPUCommandBuffer] +except AttributeError: pass + +# WGPUComputePassEncoder wgpuCommandEncoderBeginComputePass(WGPUCommandEncoder commandEncoder, const WGPUComputePassDescriptor *descriptor) +try: (wgpuCommandEncoderBeginComputePass:=dll.wgpuCommandEncoderBeginComputePass).restype, wgpuCommandEncoderBeginComputePass.argtypes = WGPUComputePassEncoder, [WGPUCommandEncoder, ctypes.POINTER(WGPUComputePassDescriptor)] +except AttributeError: pass + +# WGPURenderPassEncoder wgpuCommandEncoderBeginRenderPass(WGPUCommandEncoder commandEncoder, const WGPURenderPassDescriptor *descriptor) +try: (wgpuCommandEncoderBeginRenderPass:=dll.wgpuCommandEncoderBeginRenderPass).restype, wgpuCommandEncoderBeginRenderPass.argtypes = WGPURenderPassEncoder, [WGPUCommandEncoder, ctypes.POINTER(WGPURenderPassDescriptor)] +except AttributeError: pass + +# void wgpuCommandEncoderClearBuffer(WGPUCommandEncoder commandEncoder, WGPUBuffer buffer, uint64_t offset, uint64_t size) +try: (wgpuCommandEncoderClearBuffer:=dll.wgpuCommandEncoderClearBuffer).restype, wgpuCommandEncoderClearBuffer.argtypes = None, [WGPUCommandEncoder, WGPUBuffer, uint64_t, uint64_t] +except AttributeError: pass + +# void wgpuCommandEncoderCopyBufferToBuffer(WGPUCommandEncoder commandEncoder, WGPUBuffer source, uint64_t sourceOffset, WGPUBuffer destination, uint64_t destinationOffset, uint64_t size) +try: (wgpuCommandEncoderCopyBufferToBuffer:=dll.wgpuCommandEncoderCopyBufferToBuffer).restype, wgpuCommandEncoderCopyBufferToBuffer.argtypes = None, [WGPUCommandEncoder, WGPUBuffer, uint64_t, WGPUBuffer, uint64_t, uint64_t] +except AttributeError: pass + +# void wgpuCommandEncoderCopyBufferToTexture(WGPUCommandEncoder commandEncoder, const WGPUImageCopyBuffer *source, const WGPUImageCopyTexture *destination, const WGPUExtent3D *copySize) +try: (wgpuCommandEncoderCopyBufferToTexture:=dll.wgpuCommandEncoderCopyBufferToTexture).restype, wgpuCommandEncoderCopyBufferToTexture.argtypes = None, [WGPUCommandEncoder, ctypes.POINTER(WGPUImageCopyBuffer), ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUExtent3D)] +except AttributeError: pass + +# void wgpuCommandEncoderCopyTextureToBuffer(WGPUCommandEncoder commandEncoder, const WGPUImageCopyTexture *source, const WGPUImageCopyBuffer *destination, const WGPUExtent3D *copySize) +try: (wgpuCommandEncoderCopyTextureToBuffer:=dll.wgpuCommandEncoderCopyTextureToBuffer).restype, wgpuCommandEncoderCopyTextureToBuffer.argtypes = None, [WGPUCommandEncoder, ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUImageCopyBuffer), ctypes.POINTER(WGPUExtent3D)] +except AttributeError: pass + +# void wgpuCommandEncoderCopyTextureToTexture(WGPUCommandEncoder commandEncoder, const WGPUImageCopyTexture *source, const WGPUImageCopyTexture *destination, const WGPUExtent3D *copySize) +try: (wgpuCommandEncoderCopyTextureToTexture:=dll.wgpuCommandEncoderCopyTextureToTexture).restype, wgpuCommandEncoderCopyTextureToTexture.argtypes = None, [WGPUCommandEncoder, ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUExtent3D)] +except AttributeError: pass + +# WGPUCommandBuffer wgpuCommandEncoderFinish(WGPUCommandEncoder commandEncoder, const WGPUCommandBufferDescriptor *descriptor) +try: (wgpuCommandEncoderFinish:=dll.wgpuCommandEncoderFinish).restype, wgpuCommandEncoderFinish.argtypes = WGPUCommandBuffer, [WGPUCommandEncoder, ctypes.POINTER(WGPUCommandBufferDescriptor)] +except AttributeError: pass + +# void wgpuCommandEncoderInjectValidationError(WGPUCommandEncoder commandEncoder, WGPUStringView message) +try: (wgpuCommandEncoderInjectValidationError:=dll.wgpuCommandEncoderInjectValidationError).restype, wgpuCommandEncoderInjectValidationError.argtypes = None, [WGPUCommandEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuCommandEncoderInsertDebugMarker(WGPUCommandEncoder commandEncoder, WGPUStringView markerLabel) +try: (wgpuCommandEncoderInsertDebugMarker:=dll.wgpuCommandEncoderInsertDebugMarker).restype, wgpuCommandEncoderInsertDebugMarker.argtypes = None, [WGPUCommandEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuCommandEncoderPopDebugGroup(WGPUCommandEncoder commandEncoder) +try: (wgpuCommandEncoderPopDebugGroup:=dll.wgpuCommandEncoderPopDebugGroup).restype, wgpuCommandEncoderPopDebugGroup.argtypes = None, [WGPUCommandEncoder] +except AttributeError: pass + +# void wgpuCommandEncoderPushDebugGroup(WGPUCommandEncoder commandEncoder, WGPUStringView groupLabel) +try: (wgpuCommandEncoderPushDebugGroup:=dll.wgpuCommandEncoderPushDebugGroup).restype, wgpuCommandEncoderPushDebugGroup.argtypes = None, [WGPUCommandEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuCommandEncoderResolveQuerySet(WGPUCommandEncoder commandEncoder, WGPUQuerySet querySet, uint32_t firstQuery, uint32_t queryCount, WGPUBuffer destination, uint64_t destinationOffset) +try: (wgpuCommandEncoderResolveQuerySet:=dll.wgpuCommandEncoderResolveQuerySet).restype, wgpuCommandEncoderResolveQuerySet.argtypes = None, [WGPUCommandEncoder, WGPUQuerySet, uint32_t, uint32_t, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuCommandEncoderSetLabel(WGPUCommandEncoder commandEncoder, WGPUStringView label) +try: (wgpuCommandEncoderSetLabel:=dll.wgpuCommandEncoderSetLabel).restype, wgpuCommandEncoderSetLabel.argtypes = None, [WGPUCommandEncoder, WGPUStringView] +except AttributeError: pass + +uint8_t = ctypes.c_ubyte +# void wgpuCommandEncoderWriteBuffer(WGPUCommandEncoder commandEncoder, WGPUBuffer buffer, uint64_t bufferOffset, const uint8_t *data, uint64_t size) +try: (wgpuCommandEncoderWriteBuffer:=dll.wgpuCommandEncoderWriteBuffer).restype, wgpuCommandEncoderWriteBuffer.argtypes = None, [WGPUCommandEncoder, WGPUBuffer, uint64_t, ctypes.POINTER(uint8_t), uint64_t] +except AttributeError: pass + +# void wgpuCommandEncoderWriteTimestamp(WGPUCommandEncoder commandEncoder, WGPUQuerySet querySet, uint32_t queryIndex) +try: (wgpuCommandEncoderWriteTimestamp:=dll.wgpuCommandEncoderWriteTimestamp).restype, wgpuCommandEncoderWriteTimestamp.argtypes = None, [WGPUCommandEncoder, WGPUQuerySet, uint32_t] +except AttributeError: pass + +# void wgpuCommandEncoderAddRef(WGPUCommandEncoder commandEncoder) +try: (wgpuCommandEncoderAddRef:=dll.wgpuCommandEncoderAddRef).restype, wgpuCommandEncoderAddRef.argtypes = None, [WGPUCommandEncoder] +except AttributeError: pass + +# void wgpuCommandEncoderRelease(WGPUCommandEncoder commandEncoder) +try: (wgpuCommandEncoderRelease:=dll.wgpuCommandEncoderRelease).restype, wgpuCommandEncoderRelease.argtypes = None, [WGPUCommandEncoder] +except AttributeError: pass + +# void wgpuComputePassEncoderDispatchWorkgroups(WGPUComputePassEncoder computePassEncoder, uint32_t workgroupCountX, uint32_t workgroupCountY, uint32_t workgroupCountZ) +try: (wgpuComputePassEncoderDispatchWorkgroups:=dll.wgpuComputePassEncoderDispatchWorkgroups).restype, wgpuComputePassEncoderDispatchWorkgroups.argtypes = None, [WGPUComputePassEncoder, uint32_t, uint32_t, uint32_t] +except AttributeError: pass + +# void wgpuComputePassEncoderDispatchWorkgroupsIndirect(WGPUComputePassEncoder computePassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) +try: (wgpuComputePassEncoderDispatchWorkgroupsIndirect:=dll.wgpuComputePassEncoderDispatchWorkgroupsIndirect).restype, wgpuComputePassEncoderDispatchWorkgroupsIndirect.argtypes = None, [WGPUComputePassEncoder, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuComputePassEncoderEnd(WGPUComputePassEncoder computePassEncoder) +try: (wgpuComputePassEncoderEnd:=dll.wgpuComputePassEncoderEnd).restype, wgpuComputePassEncoderEnd.argtypes = None, [WGPUComputePassEncoder] +except AttributeError: pass + +# void wgpuComputePassEncoderInsertDebugMarker(WGPUComputePassEncoder computePassEncoder, WGPUStringView markerLabel) +try: (wgpuComputePassEncoderInsertDebugMarker:=dll.wgpuComputePassEncoderInsertDebugMarker).restype, wgpuComputePassEncoderInsertDebugMarker.argtypes = None, [WGPUComputePassEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuComputePassEncoderPopDebugGroup(WGPUComputePassEncoder computePassEncoder) +try: (wgpuComputePassEncoderPopDebugGroup:=dll.wgpuComputePassEncoderPopDebugGroup).restype, wgpuComputePassEncoderPopDebugGroup.argtypes = None, [WGPUComputePassEncoder] +except AttributeError: pass + +# void wgpuComputePassEncoderPushDebugGroup(WGPUComputePassEncoder computePassEncoder, WGPUStringView groupLabel) +try: (wgpuComputePassEncoderPushDebugGroup:=dll.wgpuComputePassEncoderPushDebugGroup).restype, wgpuComputePassEncoderPushDebugGroup.argtypes = None, [WGPUComputePassEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuComputePassEncoderSetBindGroup(WGPUComputePassEncoder computePassEncoder, uint32_t groupIndex, WGPUBindGroup group, size_t dynamicOffsetCount, const uint32_t *dynamicOffsets) +try: (wgpuComputePassEncoderSetBindGroup:=dll.wgpuComputePassEncoderSetBindGroup).restype, wgpuComputePassEncoderSetBindGroup.argtypes = None, [WGPUComputePassEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# void wgpuComputePassEncoderSetLabel(WGPUComputePassEncoder computePassEncoder, WGPUStringView label) +try: (wgpuComputePassEncoderSetLabel:=dll.wgpuComputePassEncoderSetLabel).restype, wgpuComputePassEncoderSetLabel.argtypes = None, [WGPUComputePassEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuComputePassEncoderSetPipeline(WGPUComputePassEncoder computePassEncoder, WGPUComputePipeline pipeline) +try: (wgpuComputePassEncoderSetPipeline:=dll.wgpuComputePassEncoderSetPipeline).restype, wgpuComputePassEncoderSetPipeline.argtypes = None, [WGPUComputePassEncoder, WGPUComputePipeline] +except AttributeError: pass + +# void wgpuComputePassEncoderWriteTimestamp(WGPUComputePassEncoder computePassEncoder, WGPUQuerySet querySet, uint32_t queryIndex) +try: (wgpuComputePassEncoderWriteTimestamp:=dll.wgpuComputePassEncoderWriteTimestamp).restype, wgpuComputePassEncoderWriteTimestamp.argtypes = None, [WGPUComputePassEncoder, WGPUQuerySet, uint32_t] +except AttributeError: pass + +# void wgpuComputePassEncoderAddRef(WGPUComputePassEncoder computePassEncoder) +try: (wgpuComputePassEncoderAddRef:=dll.wgpuComputePassEncoderAddRef).restype, wgpuComputePassEncoderAddRef.argtypes = None, [WGPUComputePassEncoder] +except AttributeError: pass + +# void wgpuComputePassEncoderRelease(WGPUComputePassEncoder computePassEncoder) +try: (wgpuComputePassEncoderRelease:=dll.wgpuComputePassEncoderRelease).restype, wgpuComputePassEncoderRelease.argtypes = None, [WGPUComputePassEncoder] +except AttributeError: pass + +# WGPUBindGroupLayout wgpuComputePipelineGetBindGroupLayout(WGPUComputePipeline computePipeline, uint32_t groupIndex) +try: (wgpuComputePipelineGetBindGroupLayout:=dll.wgpuComputePipelineGetBindGroupLayout).restype, wgpuComputePipelineGetBindGroupLayout.argtypes = WGPUBindGroupLayout, [WGPUComputePipeline, uint32_t] +except AttributeError: pass + +# void wgpuComputePipelineSetLabel(WGPUComputePipeline computePipeline, WGPUStringView label) +try: (wgpuComputePipelineSetLabel:=dll.wgpuComputePipelineSetLabel).restype, wgpuComputePipelineSetLabel.argtypes = None, [WGPUComputePipeline, WGPUStringView] +except AttributeError: pass + +# void wgpuComputePipelineAddRef(WGPUComputePipeline computePipeline) +try: (wgpuComputePipelineAddRef:=dll.wgpuComputePipelineAddRef).restype, wgpuComputePipelineAddRef.argtypes = None, [WGPUComputePipeline] +except AttributeError: pass + +# void wgpuComputePipelineRelease(WGPUComputePipeline computePipeline) +try: (wgpuComputePipelineRelease:=dll.wgpuComputePipelineRelease).restype, wgpuComputePipelineRelease.argtypes = None, [WGPUComputePipeline] +except AttributeError: pass + +# WGPUBindGroup wgpuDeviceCreateBindGroup(WGPUDevice device, const WGPUBindGroupDescriptor *descriptor) +try: (wgpuDeviceCreateBindGroup:=dll.wgpuDeviceCreateBindGroup).restype, wgpuDeviceCreateBindGroup.argtypes = WGPUBindGroup, [WGPUDevice, ctypes.POINTER(WGPUBindGroupDescriptor)] +except AttributeError: pass + +# WGPUBindGroupLayout wgpuDeviceCreateBindGroupLayout(WGPUDevice device, const WGPUBindGroupLayoutDescriptor *descriptor) +try: (wgpuDeviceCreateBindGroupLayout:=dll.wgpuDeviceCreateBindGroupLayout).restype, wgpuDeviceCreateBindGroupLayout.argtypes = WGPUBindGroupLayout, [WGPUDevice, ctypes.POINTER(WGPUBindGroupLayoutDescriptor)] +except AttributeError: pass + +# WGPUBuffer wgpuDeviceCreateBuffer(WGPUDevice device, const WGPUBufferDescriptor *descriptor) +try: (wgpuDeviceCreateBuffer:=dll.wgpuDeviceCreateBuffer).restype, wgpuDeviceCreateBuffer.argtypes = WGPUBuffer, [WGPUDevice, ctypes.POINTER(WGPUBufferDescriptor)] +except AttributeError: pass + +# WGPUCommandEncoder wgpuDeviceCreateCommandEncoder(WGPUDevice device, const WGPUCommandEncoderDescriptor *descriptor) +try: (wgpuDeviceCreateCommandEncoder:=dll.wgpuDeviceCreateCommandEncoder).restype, wgpuDeviceCreateCommandEncoder.argtypes = WGPUCommandEncoder, [WGPUDevice, ctypes.POINTER(WGPUCommandEncoderDescriptor)] +except AttributeError: pass + +# WGPUComputePipeline wgpuDeviceCreateComputePipeline(WGPUDevice device, const WGPUComputePipelineDescriptor *descriptor) +try: (wgpuDeviceCreateComputePipeline:=dll.wgpuDeviceCreateComputePipeline).restype, wgpuDeviceCreateComputePipeline.argtypes = WGPUComputePipeline, [WGPUDevice, ctypes.POINTER(WGPUComputePipelineDescriptor)] +except AttributeError: pass + +# void wgpuDeviceCreateComputePipelineAsync(WGPUDevice device, const WGPUComputePipelineDescriptor *descriptor, WGPUCreateComputePipelineAsyncCallback callback, void *userdata) +try: (wgpuDeviceCreateComputePipelineAsync:=dll.wgpuDeviceCreateComputePipelineAsync).restype, wgpuDeviceCreateComputePipelineAsync.argtypes = None, [WGPUDevice, ctypes.POINTER(WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuDeviceCreateComputePipelineAsync2(WGPUDevice device, const WGPUComputePipelineDescriptor *descriptor, WGPUCreateComputePipelineAsyncCallbackInfo2 callbackInfo) +try: (wgpuDeviceCreateComputePipelineAsync2:=dll.wgpuDeviceCreateComputePipelineAsync2).restype, wgpuDeviceCreateComputePipelineAsync2.argtypes = WGPUFuture, [WGPUDevice, ctypes.POINTER(WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuDeviceCreateComputePipelineAsyncF(WGPUDevice device, const WGPUComputePipelineDescriptor *descriptor, WGPUCreateComputePipelineAsyncCallbackInfo callbackInfo) +try: (wgpuDeviceCreateComputePipelineAsyncF:=dll.wgpuDeviceCreateComputePipelineAsyncF).restype, wgpuDeviceCreateComputePipelineAsyncF.argtypes = WGPUFuture, [WGPUDevice, ctypes.POINTER(WGPUComputePipelineDescriptor), WGPUCreateComputePipelineAsyncCallbackInfo] +except AttributeError: pass + +# WGPUBuffer wgpuDeviceCreateErrorBuffer(WGPUDevice device, const WGPUBufferDescriptor *descriptor) +try: (wgpuDeviceCreateErrorBuffer:=dll.wgpuDeviceCreateErrorBuffer).restype, wgpuDeviceCreateErrorBuffer.argtypes = WGPUBuffer, [WGPUDevice, ctypes.POINTER(WGPUBufferDescriptor)] +except AttributeError: pass + +# WGPUExternalTexture wgpuDeviceCreateErrorExternalTexture(WGPUDevice device) +try: (wgpuDeviceCreateErrorExternalTexture:=dll.wgpuDeviceCreateErrorExternalTexture).restype, wgpuDeviceCreateErrorExternalTexture.argtypes = WGPUExternalTexture, [WGPUDevice] +except AttributeError: pass + +# WGPUShaderModule wgpuDeviceCreateErrorShaderModule(WGPUDevice device, const WGPUShaderModuleDescriptor *descriptor, WGPUStringView errorMessage) +try: (wgpuDeviceCreateErrorShaderModule:=dll.wgpuDeviceCreateErrorShaderModule).restype, wgpuDeviceCreateErrorShaderModule.argtypes = WGPUShaderModule, [WGPUDevice, ctypes.POINTER(WGPUShaderModuleDescriptor), WGPUStringView] +except AttributeError: pass + +# WGPUTexture wgpuDeviceCreateErrorTexture(WGPUDevice device, const WGPUTextureDescriptor *descriptor) +try: (wgpuDeviceCreateErrorTexture:=dll.wgpuDeviceCreateErrorTexture).restype, wgpuDeviceCreateErrorTexture.argtypes = WGPUTexture, [WGPUDevice, ctypes.POINTER(WGPUTextureDescriptor)] +except AttributeError: pass + +# WGPUExternalTexture wgpuDeviceCreateExternalTexture(WGPUDevice device, const WGPUExternalTextureDescriptor *externalTextureDescriptor) +try: (wgpuDeviceCreateExternalTexture:=dll.wgpuDeviceCreateExternalTexture).restype, wgpuDeviceCreateExternalTexture.argtypes = WGPUExternalTexture, [WGPUDevice, ctypes.POINTER(WGPUExternalTextureDescriptor)] +except AttributeError: pass + +# WGPUPipelineLayout wgpuDeviceCreatePipelineLayout(WGPUDevice device, const WGPUPipelineLayoutDescriptor *descriptor) +try: (wgpuDeviceCreatePipelineLayout:=dll.wgpuDeviceCreatePipelineLayout).restype, wgpuDeviceCreatePipelineLayout.argtypes = WGPUPipelineLayout, [WGPUDevice, ctypes.POINTER(WGPUPipelineLayoutDescriptor)] +except AttributeError: pass + +# WGPUQuerySet wgpuDeviceCreateQuerySet(WGPUDevice device, const WGPUQuerySetDescriptor *descriptor) +try: (wgpuDeviceCreateQuerySet:=dll.wgpuDeviceCreateQuerySet).restype, wgpuDeviceCreateQuerySet.argtypes = WGPUQuerySet, [WGPUDevice, ctypes.POINTER(WGPUQuerySetDescriptor)] +except AttributeError: pass + +# WGPURenderBundleEncoder wgpuDeviceCreateRenderBundleEncoder(WGPUDevice device, const WGPURenderBundleEncoderDescriptor *descriptor) +try: (wgpuDeviceCreateRenderBundleEncoder:=dll.wgpuDeviceCreateRenderBundleEncoder).restype, wgpuDeviceCreateRenderBundleEncoder.argtypes = WGPURenderBundleEncoder, [WGPUDevice, ctypes.POINTER(WGPURenderBundleEncoderDescriptor)] +except AttributeError: pass + +# WGPURenderPipeline wgpuDeviceCreateRenderPipeline(WGPUDevice device, const WGPURenderPipelineDescriptor *descriptor) +try: (wgpuDeviceCreateRenderPipeline:=dll.wgpuDeviceCreateRenderPipeline).restype, wgpuDeviceCreateRenderPipeline.argtypes = WGPURenderPipeline, [WGPUDevice, ctypes.POINTER(WGPURenderPipelineDescriptor)] +except AttributeError: pass + +# void wgpuDeviceCreateRenderPipelineAsync(WGPUDevice device, const WGPURenderPipelineDescriptor *descriptor, WGPUCreateRenderPipelineAsyncCallback callback, void *userdata) +try: (wgpuDeviceCreateRenderPipelineAsync:=dll.wgpuDeviceCreateRenderPipelineAsync).restype, wgpuDeviceCreateRenderPipelineAsync.argtypes = None, [WGPUDevice, ctypes.POINTER(WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuDeviceCreateRenderPipelineAsync2(WGPUDevice device, const WGPURenderPipelineDescriptor *descriptor, WGPUCreateRenderPipelineAsyncCallbackInfo2 callbackInfo) +try: (wgpuDeviceCreateRenderPipelineAsync2:=dll.wgpuDeviceCreateRenderPipelineAsync2).restype, wgpuDeviceCreateRenderPipelineAsync2.argtypes = WGPUFuture, [WGPUDevice, ctypes.POINTER(WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuDeviceCreateRenderPipelineAsyncF(WGPUDevice device, const WGPURenderPipelineDescriptor *descriptor, WGPUCreateRenderPipelineAsyncCallbackInfo callbackInfo) +try: (wgpuDeviceCreateRenderPipelineAsyncF:=dll.wgpuDeviceCreateRenderPipelineAsyncF).restype, wgpuDeviceCreateRenderPipelineAsyncF.argtypes = WGPUFuture, [WGPUDevice, ctypes.POINTER(WGPURenderPipelineDescriptor), WGPUCreateRenderPipelineAsyncCallbackInfo] +except AttributeError: pass + +# WGPUSampler wgpuDeviceCreateSampler(WGPUDevice device, const WGPUSamplerDescriptor *descriptor) +try: (wgpuDeviceCreateSampler:=dll.wgpuDeviceCreateSampler).restype, wgpuDeviceCreateSampler.argtypes = WGPUSampler, [WGPUDevice, ctypes.POINTER(WGPUSamplerDescriptor)] +except AttributeError: pass + +# WGPUShaderModule wgpuDeviceCreateShaderModule(WGPUDevice device, const WGPUShaderModuleDescriptor *descriptor) +try: (wgpuDeviceCreateShaderModule:=dll.wgpuDeviceCreateShaderModule).restype, wgpuDeviceCreateShaderModule.argtypes = WGPUShaderModule, [WGPUDevice, ctypes.POINTER(WGPUShaderModuleDescriptor)] +except AttributeError: pass + +# WGPUTexture wgpuDeviceCreateTexture(WGPUDevice device, const WGPUTextureDescriptor *descriptor) +try: (wgpuDeviceCreateTexture:=dll.wgpuDeviceCreateTexture).restype, wgpuDeviceCreateTexture.argtypes = WGPUTexture, [WGPUDevice, ctypes.POINTER(WGPUTextureDescriptor)] +except AttributeError: pass + +# void wgpuDeviceDestroy(WGPUDevice device) +try: (wgpuDeviceDestroy:=dll.wgpuDeviceDestroy).restype, wgpuDeviceDestroy.argtypes = None, [WGPUDevice] +except AttributeError: pass + +# void wgpuDeviceForceLoss(WGPUDevice device, WGPUDeviceLostReason type, WGPUStringView message) +try: (wgpuDeviceForceLoss:=dll.wgpuDeviceForceLoss).restype, wgpuDeviceForceLoss.argtypes = None, [WGPUDevice, WGPUDeviceLostReason, WGPUStringView] +except AttributeError: pass + +# WGPUStatus wgpuDeviceGetAHardwareBufferProperties(WGPUDevice device, void *handle, WGPUAHardwareBufferProperties *properties) +try: (wgpuDeviceGetAHardwareBufferProperties:=dll.wgpuDeviceGetAHardwareBufferProperties).restype, wgpuDeviceGetAHardwareBufferProperties.argtypes = WGPUStatus, [WGPUDevice, ctypes.c_void_p, ctypes.POINTER(WGPUAHardwareBufferProperties)] +except AttributeError: pass + +# WGPUAdapter wgpuDeviceGetAdapter(WGPUDevice device) +try: (wgpuDeviceGetAdapter:=dll.wgpuDeviceGetAdapter).restype, wgpuDeviceGetAdapter.argtypes = WGPUAdapter, [WGPUDevice] +except AttributeError: pass + +# WGPUStatus wgpuDeviceGetAdapterInfo(WGPUDevice device, WGPUAdapterInfo *adapterInfo) +try: (wgpuDeviceGetAdapterInfo:=dll.wgpuDeviceGetAdapterInfo).restype, wgpuDeviceGetAdapterInfo.argtypes = WGPUStatus, [WGPUDevice, ctypes.POINTER(WGPUAdapterInfo)] +except AttributeError: pass + +# void wgpuDeviceGetFeatures(WGPUDevice device, WGPUSupportedFeatures *features) +try: (wgpuDeviceGetFeatures:=dll.wgpuDeviceGetFeatures).restype, wgpuDeviceGetFeatures.argtypes = None, [WGPUDevice, ctypes.POINTER(WGPUSupportedFeatures)] +except AttributeError: pass + +# WGPUStatus wgpuDeviceGetLimits(WGPUDevice device, WGPUSupportedLimits *limits) +try: (wgpuDeviceGetLimits:=dll.wgpuDeviceGetLimits).restype, wgpuDeviceGetLimits.argtypes = WGPUStatus, [WGPUDevice, ctypes.POINTER(WGPUSupportedLimits)] +except AttributeError: pass + +# WGPUFuture wgpuDeviceGetLostFuture(WGPUDevice device) +try: (wgpuDeviceGetLostFuture:=dll.wgpuDeviceGetLostFuture).restype, wgpuDeviceGetLostFuture.argtypes = WGPUFuture, [WGPUDevice] +except AttributeError: pass + +# WGPUQueue wgpuDeviceGetQueue(WGPUDevice device) +try: (wgpuDeviceGetQueue:=dll.wgpuDeviceGetQueue).restype, wgpuDeviceGetQueue.argtypes = WGPUQueue, [WGPUDevice] +except AttributeError: pass + +# WGPUBool wgpuDeviceHasFeature(WGPUDevice device, WGPUFeatureName feature) +try: (wgpuDeviceHasFeature:=dll.wgpuDeviceHasFeature).restype, wgpuDeviceHasFeature.argtypes = WGPUBool, [WGPUDevice, WGPUFeatureName] +except AttributeError: pass + +# WGPUSharedBufferMemory wgpuDeviceImportSharedBufferMemory(WGPUDevice device, const WGPUSharedBufferMemoryDescriptor *descriptor) +try: (wgpuDeviceImportSharedBufferMemory:=dll.wgpuDeviceImportSharedBufferMemory).restype, wgpuDeviceImportSharedBufferMemory.argtypes = WGPUSharedBufferMemory, [WGPUDevice, ctypes.POINTER(WGPUSharedBufferMemoryDescriptor)] +except AttributeError: pass + +# WGPUSharedFence wgpuDeviceImportSharedFence(WGPUDevice device, const WGPUSharedFenceDescriptor *descriptor) +try: (wgpuDeviceImportSharedFence:=dll.wgpuDeviceImportSharedFence).restype, wgpuDeviceImportSharedFence.argtypes = WGPUSharedFence, [WGPUDevice, ctypes.POINTER(WGPUSharedFenceDescriptor)] +except AttributeError: pass + +# WGPUSharedTextureMemory wgpuDeviceImportSharedTextureMemory(WGPUDevice device, const WGPUSharedTextureMemoryDescriptor *descriptor) +try: (wgpuDeviceImportSharedTextureMemory:=dll.wgpuDeviceImportSharedTextureMemory).restype, wgpuDeviceImportSharedTextureMemory.argtypes = WGPUSharedTextureMemory, [WGPUDevice, ctypes.POINTER(WGPUSharedTextureMemoryDescriptor)] +except AttributeError: pass + +# void wgpuDeviceInjectError(WGPUDevice device, WGPUErrorType type, WGPUStringView message) +try: (wgpuDeviceInjectError:=dll.wgpuDeviceInjectError).restype, wgpuDeviceInjectError.argtypes = None, [WGPUDevice, WGPUErrorType, WGPUStringView] +except AttributeError: pass + +# void wgpuDevicePopErrorScope(WGPUDevice device, WGPUErrorCallback oldCallback, void *userdata) +try: (wgpuDevicePopErrorScope:=dll.wgpuDevicePopErrorScope).restype, wgpuDevicePopErrorScope.argtypes = None, [WGPUDevice, WGPUErrorCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuDevicePopErrorScope2(WGPUDevice device, WGPUPopErrorScopeCallbackInfo2 callbackInfo) +try: (wgpuDevicePopErrorScope2:=dll.wgpuDevicePopErrorScope2).restype, wgpuDevicePopErrorScope2.argtypes = WGPUFuture, [WGPUDevice, WGPUPopErrorScopeCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuDevicePopErrorScopeF(WGPUDevice device, WGPUPopErrorScopeCallbackInfo callbackInfo) +try: (wgpuDevicePopErrorScopeF:=dll.wgpuDevicePopErrorScopeF).restype, wgpuDevicePopErrorScopeF.argtypes = WGPUFuture, [WGPUDevice, WGPUPopErrorScopeCallbackInfo] +except AttributeError: pass + +# void wgpuDevicePushErrorScope(WGPUDevice device, WGPUErrorFilter filter) +try: (wgpuDevicePushErrorScope:=dll.wgpuDevicePushErrorScope).restype, wgpuDevicePushErrorScope.argtypes = None, [WGPUDevice, WGPUErrorFilter] +except AttributeError: pass + +# void wgpuDeviceSetLabel(WGPUDevice device, WGPUStringView label) +try: (wgpuDeviceSetLabel:=dll.wgpuDeviceSetLabel).restype, wgpuDeviceSetLabel.argtypes = None, [WGPUDevice, WGPUStringView] +except AttributeError: pass + +# void wgpuDeviceSetLoggingCallback(WGPUDevice device, WGPULoggingCallback callback, void *userdata) +try: (wgpuDeviceSetLoggingCallback:=dll.wgpuDeviceSetLoggingCallback).restype, wgpuDeviceSetLoggingCallback.argtypes = None, [WGPUDevice, WGPULoggingCallback, ctypes.c_void_p] +except AttributeError: pass + +# void wgpuDeviceTick(WGPUDevice device) +try: (wgpuDeviceTick:=dll.wgpuDeviceTick).restype, wgpuDeviceTick.argtypes = None, [WGPUDevice] +except AttributeError: pass + +# void wgpuDeviceValidateTextureDescriptor(WGPUDevice device, const WGPUTextureDescriptor *descriptor) +try: (wgpuDeviceValidateTextureDescriptor:=dll.wgpuDeviceValidateTextureDescriptor).restype, wgpuDeviceValidateTextureDescriptor.argtypes = None, [WGPUDevice, ctypes.POINTER(WGPUTextureDescriptor)] +except AttributeError: pass + +# void wgpuDeviceAddRef(WGPUDevice device) +try: (wgpuDeviceAddRef:=dll.wgpuDeviceAddRef).restype, wgpuDeviceAddRef.argtypes = None, [WGPUDevice] +except AttributeError: pass + +# void wgpuDeviceRelease(WGPUDevice device) +try: (wgpuDeviceRelease:=dll.wgpuDeviceRelease).restype, wgpuDeviceRelease.argtypes = None, [WGPUDevice] +except AttributeError: pass + +# void wgpuExternalTextureDestroy(WGPUExternalTexture externalTexture) +try: (wgpuExternalTextureDestroy:=dll.wgpuExternalTextureDestroy).restype, wgpuExternalTextureDestroy.argtypes = None, [WGPUExternalTexture] +except AttributeError: pass + +# void wgpuExternalTextureExpire(WGPUExternalTexture externalTexture) +try: (wgpuExternalTextureExpire:=dll.wgpuExternalTextureExpire).restype, wgpuExternalTextureExpire.argtypes = None, [WGPUExternalTexture] +except AttributeError: pass + +# void wgpuExternalTextureRefresh(WGPUExternalTexture externalTexture) +try: (wgpuExternalTextureRefresh:=dll.wgpuExternalTextureRefresh).restype, wgpuExternalTextureRefresh.argtypes = None, [WGPUExternalTexture] +except AttributeError: pass + +# void wgpuExternalTextureSetLabel(WGPUExternalTexture externalTexture, WGPUStringView label) +try: (wgpuExternalTextureSetLabel:=dll.wgpuExternalTextureSetLabel).restype, wgpuExternalTextureSetLabel.argtypes = None, [WGPUExternalTexture, WGPUStringView] +except AttributeError: pass + +# void wgpuExternalTextureAddRef(WGPUExternalTexture externalTexture) +try: (wgpuExternalTextureAddRef:=dll.wgpuExternalTextureAddRef).restype, wgpuExternalTextureAddRef.argtypes = None, [WGPUExternalTexture] +except AttributeError: pass + +# void wgpuExternalTextureRelease(WGPUExternalTexture externalTexture) +try: (wgpuExternalTextureRelease:=dll.wgpuExternalTextureRelease).restype, wgpuExternalTextureRelease.argtypes = None, [WGPUExternalTexture] +except AttributeError: pass + +# WGPUSurface wgpuInstanceCreateSurface(WGPUInstance instance, const WGPUSurfaceDescriptor *descriptor) +try: (wgpuInstanceCreateSurface:=dll.wgpuInstanceCreateSurface).restype, wgpuInstanceCreateSurface.argtypes = WGPUSurface, [WGPUInstance, ctypes.POINTER(WGPUSurfaceDescriptor)] +except AttributeError: pass + +# size_t wgpuInstanceEnumerateWGSLLanguageFeatures(WGPUInstance instance, WGPUWGSLFeatureName *features) +try: (wgpuInstanceEnumerateWGSLLanguageFeatures:=dll.wgpuInstanceEnumerateWGSLLanguageFeatures).restype, wgpuInstanceEnumerateWGSLLanguageFeatures.argtypes = size_t, [WGPUInstance, ctypes.POINTER(WGPUWGSLFeatureName)] +except AttributeError: pass + +# WGPUBool wgpuInstanceHasWGSLLanguageFeature(WGPUInstance instance, WGPUWGSLFeatureName feature) +try: (wgpuInstanceHasWGSLLanguageFeature:=dll.wgpuInstanceHasWGSLLanguageFeature).restype, wgpuInstanceHasWGSLLanguageFeature.argtypes = WGPUBool, [WGPUInstance, WGPUWGSLFeatureName] +except AttributeError: pass + +# void wgpuInstanceProcessEvents(WGPUInstance instance) +try: (wgpuInstanceProcessEvents:=dll.wgpuInstanceProcessEvents).restype, wgpuInstanceProcessEvents.argtypes = None, [WGPUInstance] +except AttributeError: pass + +# void wgpuInstanceRequestAdapter(WGPUInstance instance, const WGPURequestAdapterOptions *options, WGPURequestAdapterCallback callback, void *userdata) +try: (wgpuInstanceRequestAdapter:=dll.wgpuInstanceRequestAdapter).restype, wgpuInstanceRequestAdapter.argtypes = None, [WGPUInstance, ctypes.POINTER(WGPURequestAdapterOptions), WGPURequestAdapterCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuInstanceRequestAdapter2(WGPUInstance instance, const WGPURequestAdapterOptions *options, WGPURequestAdapterCallbackInfo2 callbackInfo) +try: (wgpuInstanceRequestAdapter2:=dll.wgpuInstanceRequestAdapter2).restype, wgpuInstanceRequestAdapter2.argtypes = WGPUFuture, [WGPUInstance, ctypes.POINTER(WGPURequestAdapterOptions), WGPURequestAdapterCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuInstanceRequestAdapterF(WGPUInstance instance, const WGPURequestAdapterOptions *options, WGPURequestAdapterCallbackInfo callbackInfo) +try: (wgpuInstanceRequestAdapterF:=dll.wgpuInstanceRequestAdapterF).restype, wgpuInstanceRequestAdapterF.argtypes = WGPUFuture, [WGPUInstance, ctypes.POINTER(WGPURequestAdapterOptions), WGPURequestAdapterCallbackInfo] +except AttributeError: pass + +# WGPUWaitStatus wgpuInstanceWaitAny(WGPUInstance instance, size_t futureCount, WGPUFutureWaitInfo *futures, uint64_t timeoutNS) +try: (wgpuInstanceWaitAny:=dll.wgpuInstanceWaitAny).restype, wgpuInstanceWaitAny.argtypes = WGPUWaitStatus, [WGPUInstance, size_t, ctypes.POINTER(WGPUFutureWaitInfo), uint64_t] +except AttributeError: pass + +# void wgpuInstanceAddRef(WGPUInstance instance) +try: (wgpuInstanceAddRef:=dll.wgpuInstanceAddRef).restype, wgpuInstanceAddRef.argtypes = None, [WGPUInstance] +except AttributeError: pass + +# void wgpuInstanceRelease(WGPUInstance instance) +try: (wgpuInstanceRelease:=dll.wgpuInstanceRelease).restype, wgpuInstanceRelease.argtypes = None, [WGPUInstance] +except AttributeError: pass + +# void wgpuPipelineLayoutSetLabel(WGPUPipelineLayout pipelineLayout, WGPUStringView label) +try: (wgpuPipelineLayoutSetLabel:=dll.wgpuPipelineLayoutSetLabel).restype, wgpuPipelineLayoutSetLabel.argtypes = None, [WGPUPipelineLayout, WGPUStringView] +except AttributeError: pass + +# void wgpuPipelineLayoutAddRef(WGPUPipelineLayout pipelineLayout) +try: (wgpuPipelineLayoutAddRef:=dll.wgpuPipelineLayoutAddRef).restype, wgpuPipelineLayoutAddRef.argtypes = None, [WGPUPipelineLayout] +except AttributeError: pass + +# void wgpuPipelineLayoutRelease(WGPUPipelineLayout pipelineLayout) +try: (wgpuPipelineLayoutRelease:=dll.wgpuPipelineLayoutRelease).restype, wgpuPipelineLayoutRelease.argtypes = None, [WGPUPipelineLayout] +except AttributeError: pass + +# void wgpuQuerySetDestroy(WGPUQuerySet querySet) +try: (wgpuQuerySetDestroy:=dll.wgpuQuerySetDestroy).restype, wgpuQuerySetDestroy.argtypes = None, [WGPUQuerySet] +except AttributeError: pass + +# uint32_t wgpuQuerySetGetCount(WGPUQuerySet querySet) +try: (wgpuQuerySetGetCount:=dll.wgpuQuerySetGetCount).restype, wgpuQuerySetGetCount.argtypes = uint32_t, [WGPUQuerySet] +except AttributeError: pass + +# WGPUQueryType wgpuQuerySetGetType(WGPUQuerySet querySet) +try: (wgpuQuerySetGetType:=dll.wgpuQuerySetGetType).restype, wgpuQuerySetGetType.argtypes = WGPUQueryType, [WGPUQuerySet] +except AttributeError: pass + +# void wgpuQuerySetSetLabel(WGPUQuerySet querySet, WGPUStringView label) +try: (wgpuQuerySetSetLabel:=dll.wgpuQuerySetSetLabel).restype, wgpuQuerySetSetLabel.argtypes = None, [WGPUQuerySet, WGPUStringView] +except AttributeError: pass + +# void wgpuQuerySetAddRef(WGPUQuerySet querySet) +try: (wgpuQuerySetAddRef:=dll.wgpuQuerySetAddRef).restype, wgpuQuerySetAddRef.argtypes = None, [WGPUQuerySet] +except AttributeError: pass + +# void wgpuQuerySetRelease(WGPUQuerySet querySet) +try: (wgpuQuerySetRelease:=dll.wgpuQuerySetRelease).restype, wgpuQuerySetRelease.argtypes = None, [WGPUQuerySet] +except AttributeError: pass + +# void wgpuQueueCopyExternalTextureForBrowser(WGPUQueue queue, const WGPUImageCopyExternalTexture *source, const WGPUImageCopyTexture *destination, const WGPUExtent3D *copySize, const WGPUCopyTextureForBrowserOptions *options) +try: (wgpuQueueCopyExternalTextureForBrowser:=dll.wgpuQueueCopyExternalTextureForBrowser).restype, wgpuQueueCopyExternalTextureForBrowser.argtypes = None, [WGPUQueue, ctypes.POINTER(WGPUImageCopyExternalTexture), ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUExtent3D), ctypes.POINTER(WGPUCopyTextureForBrowserOptions)] +except AttributeError: pass + +# void wgpuQueueCopyTextureForBrowser(WGPUQueue queue, const WGPUImageCopyTexture *source, const WGPUImageCopyTexture *destination, const WGPUExtent3D *copySize, const WGPUCopyTextureForBrowserOptions *options) +try: (wgpuQueueCopyTextureForBrowser:=dll.wgpuQueueCopyTextureForBrowser).restype, wgpuQueueCopyTextureForBrowser.argtypes = None, [WGPUQueue, ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUImageCopyTexture), ctypes.POINTER(WGPUExtent3D), ctypes.POINTER(WGPUCopyTextureForBrowserOptions)] +except AttributeError: pass + +# void wgpuQueueOnSubmittedWorkDone(WGPUQueue queue, WGPUQueueWorkDoneCallback callback, void *userdata) +try: (wgpuQueueOnSubmittedWorkDone:=dll.wgpuQueueOnSubmittedWorkDone).restype, wgpuQueueOnSubmittedWorkDone.argtypes = None, [WGPUQueue, WGPUQueueWorkDoneCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuQueueOnSubmittedWorkDone2(WGPUQueue queue, WGPUQueueWorkDoneCallbackInfo2 callbackInfo) +try: (wgpuQueueOnSubmittedWorkDone2:=dll.wgpuQueueOnSubmittedWorkDone2).restype, wgpuQueueOnSubmittedWorkDone2.argtypes = WGPUFuture, [WGPUQueue, WGPUQueueWorkDoneCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuQueueOnSubmittedWorkDoneF(WGPUQueue queue, WGPUQueueWorkDoneCallbackInfo callbackInfo) +try: (wgpuQueueOnSubmittedWorkDoneF:=dll.wgpuQueueOnSubmittedWorkDoneF).restype, wgpuQueueOnSubmittedWorkDoneF.argtypes = WGPUFuture, [WGPUQueue, WGPUQueueWorkDoneCallbackInfo] +except AttributeError: pass + +# void wgpuQueueSetLabel(WGPUQueue queue, WGPUStringView label) +try: (wgpuQueueSetLabel:=dll.wgpuQueueSetLabel).restype, wgpuQueueSetLabel.argtypes = None, [WGPUQueue, WGPUStringView] +except AttributeError: pass + +# void wgpuQueueSubmit(WGPUQueue queue, size_t commandCount, const WGPUCommandBuffer *commands) +try: (wgpuQueueSubmit:=dll.wgpuQueueSubmit).restype, wgpuQueueSubmit.argtypes = None, [WGPUQueue, size_t, ctypes.POINTER(WGPUCommandBuffer)] +except AttributeError: pass + +# void wgpuQueueWriteBuffer(WGPUQueue queue, WGPUBuffer buffer, uint64_t bufferOffset, const void *data, size_t size) +try: (wgpuQueueWriteBuffer:=dll.wgpuQueueWriteBuffer).restype, wgpuQueueWriteBuffer.argtypes = None, [WGPUQueue, WGPUBuffer, uint64_t, ctypes.c_void_p, size_t] +except AttributeError: pass + +# void wgpuQueueWriteTexture(WGPUQueue queue, const WGPUImageCopyTexture *destination, const void *data, size_t dataSize, const WGPUTextureDataLayout *dataLayout, const WGPUExtent3D *writeSize) +try: (wgpuQueueWriteTexture:=dll.wgpuQueueWriteTexture).restype, wgpuQueueWriteTexture.argtypes = None, [WGPUQueue, ctypes.POINTER(WGPUImageCopyTexture), ctypes.c_void_p, size_t, ctypes.POINTER(WGPUTextureDataLayout), ctypes.POINTER(WGPUExtent3D)] +except AttributeError: pass + +# void wgpuQueueAddRef(WGPUQueue queue) +try: (wgpuQueueAddRef:=dll.wgpuQueueAddRef).restype, wgpuQueueAddRef.argtypes = None, [WGPUQueue] +except AttributeError: pass + +# void wgpuQueueRelease(WGPUQueue queue) +try: (wgpuQueueRelease:=dll.wgpuQueueRelease).restype, wgpuQueueRelease.argtypes = None, [WGPUQueue] +except AttributeError: pass + +# void wgpuRenderBundleSetLabel(WGPURenderBundle renderBundle, WGPUStringView label) +try: (wgpuRenderBundleSetLabel:=dll.wgpuRenderBundleSetLabel).restype, wgpuRenderBundleSetLabel.argtypes = None, [WGPURenderBundle, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderBundleAddRef(WGPURenderBundle renderBundle) +try: (wgpuRenderBundleAddRef:=dll.wgpuRenderBundleAddRef).restype, wgpuRenderBundleAddRef.argtypes = None, [WGPURenderBundle] +except AttributeError: pass + +# void wgpuRenderBundleRelease(WGPURenderBundle renderBundle) +try: (wgpuRenderBundleRelease:=dll.wgpuRenderBundleRelease).restype, wgpuRenderBundleRelease.argtypes = None, [WGPURenderBundle] +except AttributeError: pass + +# void wgpuRenderBundleEncoderDraw(WGPURenderBundleEncoder renderBundleEncoder, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) +try: (wgpuRenderBundleEncoderDraw:=dll.wgpuRenderBundleEncoderDraw).restype, wgpuRenderBundleEncoderDraw.argtypes = None, [WGPURenderBundleEncoder, uint32_t, uint32_t, uint32_t, uint32_t] +except AttributeError: pass + +# void wgpuRenderBundleEncoderDrawIndexed(WGPURenderBundleEncoder renderBundleEncoder, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t baseVertex, uint32_t firstInstance) +try: (wgpuRenderBundleEncoderDrawIndexed:=dll.wgpuRenderBundleEncoderDrawIndexed).restype, wgpuRenderBundleEncoderDrawIndexed.argtypes = None, [WGPURenderBundleEncoder, uint32_t, uint32_t, uint32_t, int32_t, uint32_t] +except AttributeError: pass + +# void wgpuRenderBundleEncoderDrawIndexedIndirect(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) +try: (wgpuRenderBundleEncoderDrawIndexedIndirect:=dll.wgpuRenderBundleEncoderDrawIndexedIndirect).restype, wgpuRenderBundleEncoderDrawIndexedIndirect.argtypes = None, [WGPURenderBundleEncoder, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuRenderBundleEncoderDrawIndirect(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) +try: (wgpuRenderBundleEncoderDrawIndirect:=dll.wgpuRenderBundleEncoderDrawIndirect).restype, wgpuRenderBundleEncoderDrawIndirect.argtypes = None, [WGPURenderBundleEncoder, WGPUBuffer, uint64_t] +except AttributeError: pass + +# WGPURenderBundle wgpuRenderBundleEncoderFinish(WGPURenderBundleEncoder renderBundleEncoder, const WGPURenderBundleDescriptor *descriptor) +try: (wgpuRenderBundleEncoderFinish:=dll.wgpuRenderBundleEncoderFinish).restype, wgpuRenderBundleEncoderFinish.argtypes = WGPURenderBundle, [WGPURenderBundleEncoder, ctypes.POINTER(WGPURenderBundleDescriptor)] +except AttributeError: pass + +# void wgpuRenderBundleEncoderInsertDebugMarker(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView markerLabel) +try: (wgpuRenderBundleEncoderInsertDebugMarker:=dll.wgpuRenderBundleEncoderInsertDebugMarker).restype, wgpuRenderBundleEncoderInsertDebugMarker.argtypes = None, [WGPURenderBundleEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderBundleEncoderPopDebugGroup(WGPURenderBundleEncoder renderBundleEncoder) +try: (wgpuRenderBundleEncoderPopDebugGroup:=dll.wgpuRenderBundleEncoderPopDebugGroup).restype, wgpuRenderBundleEncoderPopDebugGroup.argtypes = None, [WGPURenderBundleEncoder] +except AttributeError: pass + +# void wgpuRenderBundleEncoderPushDebugGroup(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView groupLabel) +try: (wgpuRenderBundleEncoderPushDebugGroup:=dll.wgpuRenderBundleEncoderPushDebugGroup).restype, wgpuRenderBundleEncoderPushDebugGroup.argtypes = None, [WGPURenderBundleEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderBundleEncoderSetBindGroup(WGPURenderBundleEncoder renderBundleEncoder, uint32_t groupIndex, WGPUBindGroup group, size_t dynamicOffsetCount, const uint32_t *dynamicOffsets) +try: (wgpuRenderBundleEncoderSetBindGroup:=dll.wgpuRenderBundleEncoderSetBindGroup).restype, wgpuRenderBundleEncoderSetBindGroup.argtypes = None, [WGPURenderBundleEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# void wgpuRenderBundleEncoderSetIndexBuffer(WGPURenderBundleEncoder renderBundleEncoder, WGPUBuffer buffer, WGPUIndexFormat format, uint64_t offset, uint64_t size) +try: (wgpuRenderBundleEncoderSetIndexBuffer:=dll.wgpuRenderBundleEncoderSetIndexBuffer).restype, wgpuRenderBundleEncoderSetIndexBuffer.argtypes = None, [WGPURenderBundleEncoder, WGPUBuffer, WGPUIndexFormat, uint64_t, uint64_t] +except AttributeError: pass + +# void wgpuRenderBundleEncoderSetLabel(WGPURenderBundleEncoder renderBundleEncoder, WGPUStringView label) +try: (wgpuRenderBundleEncoderSetLabel:=dll.wgpuRenderBundleEncoderSetLabel).restype, wgpuRenderBundleEncoderSetLabel.argtypes = None, [WGPURenderBundleEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderBundleEncoderSetPipeline(WGPURenderBundleEncoder renderBundleEncoder, WGPURenderPipeline pipeline) +try: (wgpuRenderBundleEncoderSetPipeline:=dll.wgpuRenderBundleEncoderSetPipeline).restype, wgpuRenderBundleEncoderSetPipeline.argtypes = None, [WGPURenderBundleEncoder, WGPURenderPipeline] +except AttributeError: pass + +# void wgpuRenderBundleEncoderSetVertexBuffer(WGPURenderBundleEncoder renderBundleEncoder, uint32_t slot, WGPUBuffer buffer, uint64_t offset, uint64_t size) +try: (wgpuRenderBundleEncoderSetVertexBuffer:=dll.wgpuRenderBundleEncoderSetVertexBuffer).restype, wgpuRenderBundleEncoderSetVertexBuffer.argtypes = None, [WGPURenderBundleEncoder, uint32_t, WGPUBuffer, uint64_t, uint64_t] +except AttributeError: pass + +# void wgpuRenderBundleEncoderAddRef(WGPURenderBundleEncoder renderBundleEncoder) +try: (wgpuRenderBundleEncoderAddRef:=dll.wgpuRenderBundleEncoderAddRef).restype, wgpuRenderBundleEncoderAddRef.argtypes = None, [WGPURenderBundleEncoder] +except AttributeError: pass + +# void wgpuRenderBundleEncoderRelease(WGPURenderBundleEncoder renderBundleEncoder) +try: (wgpuRenderBundleEncoderRelease:=dll.wgpuRenderBundleEncoderRelease).restype, wgpuRenderBundleEncoderRelease.argtypes = None, [WGPURenderBundleEncoder] +except AttributeError: pass + +# void wgpuRenderPassEncoderBeginOcclusionQuery(WGPURenderPassEncoder renderPassEncoder, uint32_t queryIndex) +try: (wgpuRenderPassEncoderBeginOcclusionQuery:=dll.wgpuRenderPassEncoderBeginOcclusionQuery).restype, wgpuRenderPassEncoderBeginOcclusionQuery.argtypes = None, [WGPURenderPassEncoder, uint32_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderDraw(WGPURenderPassEncoder renderPassEncoder, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) +try: (wgpuRenderPassEncoderDraw:=dll.wgpuRenderPassEncoderDraw).restype, wgpuRenderPassEncoderDraw.argtypes = None, [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, uint32_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderDrawIndexed(WGPURenderPassEncoder renderPassEncoder, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t baseVertex, uint32_t firstInstance) +try: (wgpuRenderPassEncoderDrawIndexed:=dll.wgpuRenderPassEncoderDrawIndexed).restype, wgpuRenderPassEncoderDrawIndexed.argtypes = None, [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, int32_t, uint32_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderDrawIndexedIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) +try: (wgpuRenderPassEncoderDrawIndexedIndirect:=dll.wgpuRenderPassEncoderDrawIndexedIndirect).restype, wgpuRenderPassEncoderDrawIndexedIndirect.argtypes = None, [WGPURenderPassEncoder, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderDrawIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset) +try: (wgpuRenderPassEncoderDrawIndirect:=dll.wgpuRenderPassEncoderDrawIndirect).restype, wgpuRenderPassEncoderDrawIndirect.argtypes = None, [WGPURenderPassEncoder, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderEnd(WGPURenderPassEncoder renderPassEncoder) +try: (wgpuRenderPassEncoderEnd:=dll.wgpuRenderPassEncoderEnd).restype, wgpuRenderPassEncoderEnd.argtypes = None, [WGPURenderPassEncoder] +except AttributeError: pass + +# void wgpuRenderPassEncoderEndOcclusionQuery(WGPURenderPassEncoder renderPassEncoder) +try: (wgpuRenderPassEncoderEndOcclusionQuery:=dll.wgpuRenderPassEncoderEndOcclusionQuery).restype, wgpuRenderPassEncoderEndOcclusionQuery.argtypes = None, [WGPURenderPassEncoder] +except AttributeError: pass + +# void wgpuRenderPassEncoderExecuteBundles(WGPURenderPassEncoder renderPassEncoder, size_t bundleCount, const WGPURenderBundle *bundles) +try: (wgpuRenderPassEncoderExecuteBundles:=dll.wgpuRenderPassEncoderExecuteBundles).restype, wgpuRenderPassEncoderExecuteBundles.argtypes = None, [WGPURenderPassEncoder, size_t, ctypes.POINTER(WGPURenderBundle)] +except AttributeError: pass + +# void wgpuRenderPassEncoderInsertDebugMarker(WGPURenderPassEncoder renderPassEncoder, WGPUStringView markerLabel) +try: (wgpuRenderPassEncoderInsertDebugMarker:=dll.wgpuRenderPassEncoderInsertDebugMarker).restype, wgpuRenderPassEncoderInsertDebugMarker.argtypes = None, [WGPURenderPassEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderPassEncoderMultiDrawIndexedIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset, uint32_t maxDrawCount, WGPUBuffer drawCountBuffer, uint64_t drawCountBufferOffset) +try: (wgpuRenderPassEncoderMultiDrawIndexedIndirect:=dll.wgpuRenderPassEncoderMultiDrawIndexedIndirect).restype, wgpuRenderPassEncoderMultiDrawIndexedIndirect.argtypes = None, [WGPURenderPassEncoder, WGPUBuffer, uint64_t, uint32_t, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderMultiDrawIndirect(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer indirectBuffer, uint64_t indirectOffset, uint32_t maxDrawCount, WGPUBuffer drawCountBuffer, uint64_t drawCountBufferOffset) +try: (wgpuRenderPassEncoderMultiDrawIndirect:=dll.wgpuRenderPassEncoderMultiDrawIndirect).restype, wgpuRenderPassEncoderMultiDrawIndirect.argtypes = None, [WGPURenderPassEncoder, WGPUBuffer, uint64_t, uint32_t, WGPUBuffer, uint64_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderPixelLocalStorageBarrier(WGPURenderPassEncoder renderPassEncoder) +try: (wgpuRenderPassEncoderPixelLocalStorageBarrier:=dll.wgpuRenderPassEncoderPixelLocalStorageBarrier).restype, wgpuRenderPassEncoderPixelLocalStorageBarrier.argtypes = None, [WGPURenderPassEncoder] +except AttributeError: pass + +# void wgpuRenderPassEncoderPopDebugGroup(WGPURenderPassEncoder renderPassEncoder) +try: (wgpuRenderPassEncoderPopDebugGroup:=dll.wgpuRenderPassEncoderPopDebugGroup).restype, wgpuRenderPassEncoderPopDebugGroup.argtypes = None, [WGPURenderPassEncoder] +except AttributeError: pass + +# void wgpuRenderPassEncoderPushDebugGroup(WGPURenderPassEncoder renderPassEncoder, WGPUStringView groupLabel) +try: (wgpuRenderPassEncoderPushDebugGroup:=dll.wgpuRenderPassEncoderPushDebugGroup).restype, wgpuRenderPassEncoderPushDebugGroup.argtypes = None, [WGPURenderPassEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetBindGroup(WGPURenderPassEncoder renderPassEncoder, uint32_t groupIndex, WGPUBindGroup group, size_t dynamicOffsetCount, const uint32_t *dynamicOffsets) +try: (wgpuRenderPassEncoderSetBindGroup:=dll.wgpuRenderPassEncoderSetBindGroup).restype, wgpuRenderPassEncoderSetBindGroup.argtypes = None, [WGPURenderPassEncoder, uint32_t, WGPUBindGroup, size_t, ctypes.POINTER(uint32_t)] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetBlendConstant(WGPURenderPassEncoder renderPassEncoder, const WGPUColor *color) +try: (wgpuRenderPassEncoderSetBlendConstant:=dll.wgpuRenderPassEncoderSetBlendConstant).restype, wgpuRenderPassEncoderSetBlendConstant.argtypes = None, [WGPURenderPassEncoder, ctypes.POINTER(WGPUColor)] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetIndexBuffer(WGPURenderPassEncoder renderPassEncoder, WGPUBuffer buffer, WGPUIndexFormat format, uint64_t offset, uint64_t size) +try: (wgpuRenderPassEncoderSetIndexBuffer:=dll.wgpuRenderPassEncoderSetIndexBuffer).restype, wgpuRenderPassEncoderSetIndexBuffer.argtypes = None, [WGPURenderPassEncoder, WGPUBuffer, WGPUIndexFormat, uint64_t, uint64_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetLabel(WGPURenderPassEncoder renderPassEncoder, WGPUStringView label) +try: (wgpuRenderPassEncoderSetLabel:=dll.wgpuRenderPassEncoderSetLabel).restype, wgpuRenderPassEncoderSetLabel.argtypes = None, [WGPURenderPassEncoder, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetPipeline(WGPURenderPassEncoder renderPassEncoder, WGPURenderPipeline pipeline) +try: (wgpuRenderPassEncoderSetPipeline:=dll.wgpuRenderPassEncoderSetPipeline).restype, wgpuRenderPassEncoderSetPipeline.argtypes = None, [WGPURenderPassEncoder, WGPURenderPipeline] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetScissorRect(WGPURenderPassEncoder renderPassEncoder, uint32_t x, uint32_t y, uint32_t width, uint32_t height) +try: (wgpuRenderPassEncoderSetScissorRect:=dll.wgpuRenderPassEncoderSetScissorRect).restype, wgpuRenderPassEncoderSetScissorRect.argtypes = None, [WGPURenderPassEncoder, uint32_t, uint32_t, uint32_t, uint32_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetStencilReference(WGPURenderPassEncoder renderPassEncoder, uint32_t reference) +try: (wgpuRenderPassEncoderSetStencilReference:=dll.wgpuRenderPassEncoderSetStencilReference).restype, wgpuRenderPassEncoderSetStencilReference.argtypes = None, [WGPURenderPassEncoder, uint32_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetVertexBuffer(WGPURenderPassEncoder renderPassEncoder, uint32_t slot, WGPUBuffer buffer, uint64_t offset, uint64_t size) +try: (wgpuRenderPassEncoderSetVertexBuffer:=dll.wgpuRenderPassEncoderSetVertexBuffer).restype, wgpuRenderPassEncoderSetVertexBuffer.argtypes = None, [WGPURenderPassEncoder, uint32_t, WGPUBuffer, uint64_t, uint64_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderSetViewport(WGPURenderPassEncoder renderPassEncoder, float x, float y, float width, float height, float minDepth, float maxDepth) +try: (wgpuRenderPassEncoderSetViewport:=dll.wgpuRenderPassEncoderSetViewport).restype, wgpuRenderPassEncoderSetViewport.argtypes = None, [WGPURenderPassEncoder, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float, ctypes.c_float] +except AttributeError: pass + +# void wgpuRenderPassEncoderWriteTimestamp(WGPURenderPassEncoder renderPassEncoder, WGPUQuerySet querySet, uint32_t queryIndex) +try: (wgpuRenderPassEncoderWriteTimestamp:=dll.wgpuRenderPassEncoderWriteTimestamp).restype, wgpuRenderPassEncoderWriteTimestamp.argtypes = None, [WGPURenderPassEncoder, WGPUQuerySet, uint32_t] +except AttributeError: pass + +# void wgpuRenderPassEncoderAddRef(WGPURenderPassEncoder renderPassEncoder) +try: (wgpuRenderPassEncoderAddRef:=dll.wgpuRenderPassEncoderAddRef).restype, wgpuRenderPassEncoderAddRef.argtypes = None, [WGPURenderPassEncoder] +except AttributeError: pass + +# void wgpuRenderPassEncoderRelease(WGPURenderPassEncoder renderPassEncoder) +try: (wgpuRenderPassEncoderRelease:=dll.wgpuRenderPassEncoderRelease).restype, wgpuRenderPassEncoderRelease.argtypes = None, [WGPURenderPassEncoder] +except AttributeError: pass + +# WGPUBindGroupLayout wgpuRenderPipelineGetBindGroupLayout(WGPURenderPipeline renderPipeline, uint32_t groupIndex) +try: (wgpuRenderPipelineGetBindGroupLayout:=dll.wgpuRenderPipelineGetBindGroupLayout).restype, wgpuRenderPipelineGetBindGroupLayout.argtypes = WGPUBindGroupLayout, [WGPURenderPipeline, uint32_t] +except AttributeError: pass + +# void wgpuRenderPipelineSetLabel(WGPURenderPipeline renderPipeline, WGPUStringView label) +try: (wgpuRenderPipelineSetLabel:=dll.wgpuRenderPipelineSetLabel).restype, wgpuRenderPipelineSetLabel.argtypes = None, [WGPURenderPipeline, WGPUStringView] +except AttributeError: pass + +# void wgpuRenderPipelineAddRef(WGPURenderPipeline renderPipeline) +try: (wgpuRenderPipelineAddRef:=dll.wgpuRenderPipelineAddRef).restype, wgpuRenderPipelineAddRef.argtypes = None, [WGPURenderPipeline] +except AttributeError: pass + +# void wgpuRenderPipelineRelease(WGPURenderPipeline renderPipeline) +try: (wgpuRenderPipelineRelease:=dll.wgpuRenderPipelineRelease).restype, wgpuRenderPipelineRelease.argtypes = None, [WGPURenderPipeline] +except AttributeError: pass + +# void wgpuSamplerSetLabel(WGPUSampler sampler, WGPUStringView label) +try: (wgpuSamplerSetLabel:=dll.wgpuSamplerSetLabel).restype, wgpuSamplerSetLabel.argtypes = None, [WGPUSampler, WGPUStringView] +except AttributeError: pass + +# void wgpuSamplerAddRef(WGPUSampler sampler) +try: (wgpuSamplerAddRef:=dll.wgpuSamplerAddRef).restype, wgpuSamplerAddRef.argtypes = None, [WGPUSampler] +except AttributeError: pass + +# void wgpuSamplerRelease(WGPUSampler sampler) +try: (wgpuSamplerRelease:=dll.wgpuSamplerRelease).restype, wgpuSamplerRelease.argtypes = None, [WGPUSampler] +except AttributeError: pass + +# void wgpuShaderModuleGetCompilationInfo(WGPUShaderModule shaderModule, WGPUCompilationInfoCallback callback, void *userdata) +try: (wgpuShaderModuleGetCompilationInfo:=dll.wgpuShaderModuleGetCompilationInfo).restype, wgpuShaderModuleGetCompilationInfo.argtypes = None, [WGPUShaderModule, WGPUCompilationInfoCallback, ctypes.c_void_p] +except AttributeError: pass + +# WGPUFuture wgpuShaderModuleGetCompilationInfo2(WGPUShaderModule shaderModule, WGPUCompilationInfoCallbackInfo2 callbackInfo) +try: (wgpuShaderModuleGetCompilationInfo2:=dll.wgpuShaderModuleGetCompilationInfo2).restype, wgpuShaderModuleGetCompilationInfo2.argtypes = WGPUFuture, [WGPUShaderModule, WGPUCompilationInfoCallbackInfo2] +except AttributeError: pass + +# WGPUFuture wgpuShaderModuleGetCompilationInfoF(WGPUShaderModule shaderModule, WGPUCompilationInfoCallbackInfo callbackInfo) +try: (wgpuShaderModuleGetCompilationInfoF:=dll.wgpuShaderModuleGetCompilationInfoF).restype, wgpuShaderModuleGetCompilationInfoF.argtypes = WGPUFuture, [WGPUShaderModule, WGPUCompilationInfoCallbackInfo] +except AttributeError: pass + +# void wgpuShaderModuleSetLabel(WGPUShaderModule shaderModule, WGPUStringView label) +try: (wgpuShaderModuleSetLabel:=dll.wgpuShaderModuleSetLabel).restype, wgpuShaderModuleSetLabel.argtypes = None, [WGPUShaderModule, WGPUStringView] +except AttributeError: pass + +# void wgpuShaderModuleAddRef(WGPUShaderModule shaderModule) +try: (wgpuShaderModuleAddRef:=dll.wgpuShaderModuleAddRef).restype, wgpuShaderModuleAddRef.argtypes = None, [WGPUShaderModule] +except AttributeError: pass + +# void wgpuShaderModuleRelease(WGPUShaderModule shaderModule) +try: (wgpuShaderModuleRelease:=dll.wgpuShaderModuleRelease).restype, wgpuShaderModuleRelease.argtypes = None, [WGPUShaderModule] +except AttributeError: pass + +# WGPUStatus wgpuSharedBufferMemoryBeginAccess(WGPUSharedBufferMemory sharedBufferMemory, WGPUBuffer buffer, const WGPUSharedBufferMemoryBeginAccessDescriptor *descriptor) +try: (wgpuSharedBufferMemoryBeginAccess:=dll.wgpuSharedBufferMemoryBeginAccess).restype, wgpuSharedBufferMemoryBeginAccess.argtypes = WGPUStatus, [WGPUSharedBufferMemory, WGPUBuffer, ctypes.POINTER(WGPUSharedBufferMemoryBeginAccessDescriptor)] +except AttributeError: pass + +# WGPUBuffer wgpuSharedBufferMemoryCreateBuffer(WGPUSharedBufferMemory sharedBufferMemory, const WGPUBufferDescriptor *descriptor) +try: (wgpuSharedBufferMemoryCreateBuffer:=dll.wgpuSharedBufferMemoryCreateBuffer).restype, wgpuSharedBufferMemoryCreateBuffer.argtypes = WGPUBuffer, [WGPUSharedBufferMemory, ctypes.POINTER(WGPUBufferDescriptor)] +except AttributeError: pass + +# WGPUStatus wgpuSharedBufferMemoryEndAccess(WGPUSharedBufferMemory sharedBufferMemory, WGPUBuffer buffer, WGPUSharedBufferMemoryEndAccessState *descriptor) +try: (wgpuSharedBufferMemoryEndAccess:=dll.wgpuSharedBufferMemoryEndAccess).restype, wgpuSharedBufferMemoryEndAccess.argtypes = WGPUStatus, [WGPUSharedBufferMemory, WGPUBuffer, ctypes.POINTER(WGPUSharedBufferMemoryEndAccessState)] +except AttributeError: pass + +# WGPUStatus wgpuSharedBufferMemoryGetProperties(WGPUSharedBufferMemory sharedBufferMemory, WGPUSharedBufferMemoryProperties *properties) +try: (wgpuSharedBufferMemoryGetProperties:=dll.wgpuSharedBufferMemoryGetProperties).restype, wgpuSharedBufferMemoryGetProperties.argtypes = WGPUStatus, [WGPUSharedBufferMemory, ctypes.POINTER(WGPUSharedBufferMemoryProperties)] +except AttributeError: pass + +# WGPUBool wgpuSharedBufferMemoryIsDeviceLost(WGPUSharedBufferMemory sharedBufferMemory) +try: (wgpuSharedBufferMemoryIsDeviceLost:=dll.wgpuSharedBufferMemoryIsDeviceLost).restype, wgpuSharedBufferMemoryIsDeviceLost.argtypes = WGPUBool, [WGPUSharedBufferMemory] +except AttributeError: pass + +# void wgpuSharedBufferMemorySetLabel(WGPUSharedBufferMemory sharedBufferMemory, WGPUStringView label) +try: (wgpuSharedBufferMemorySetLabel:=dll.wgpuSharedBufferMemorySetLabel).restype, wgpuSharedBufferMemorySetLabel.argtypes = None, [WGPUSharedBufferMemory, WGPUStringView] +except AttributeError: pass + +# void wgpuSharedBufferMemoryAddRef(WGPUSharedBufferMemory sharedBufferMemory) +try: (wgpuSharedBufferMemoryAddRef:=dll.wgpuSharedBufferMemoryAddRef).restype, wgpuSharedBufferMemoryAddRef.argtypes = None, [WGPUSharedBufferMemory] +except AttributeError: pass + +# void wgpuSharedBufferMemoryRelease(WGPUSharedBufferMemory sharedBufferMemory) +try: (wgpuSharedBufferMemoryRelease:=dll.wgpuSharedBufferMemoryRelease).restype, wgpuSharedBufferMemoryRelease.argtypes = None, [WGPUSharedBufferMemory] +except AttributeError: pass + +# void wgpuSharedFenceExportInfo(WGPUSharedFence sharedFence, WGPUSharedFenceExportInfo *info) +try: (wgpuSharedFenceExportInfo:=dll.wgpuSharedFenceExportInfo).restype, wgpuSharedFenceExportInfo.argtypes = None, [WGPUSharedFence, ctypes.POINTER(WGPUSharedFenceExportInfo)] +except AttributeError: pass + +# void wgpuSharedFenceAddRef(WGPUSharedFence sharedFence) +try: (wgpuSharedFenceAddRef:=dll.wgpuSharedFenceAddRef).restype, wgpuSharedFenceAddRef.argtypes = None, [WGPUSharedFence] +except AttributeError: pass + +# void wgpuSharedFenceRelease(WGPUSharedFence sharedFence) +try: (wgpuSharedFenceRelease:=dll.wgpuSharedFenceRelease).restype, wgpuSharedFenceRelease.argtypes = None, [WGPUSharedFence] +except AttributeError: pass + +# WGPUStatus wgpuSharedTextureMemoryBeginAccess(WGPUSharedTextureMemory sharedTextureMemory, WGPUTexture texture, const WGPUSharedTextureMemoryBeginAccessDescriptor *descriptor) +try: (wgpuSharedTextureMemoryBeginAccess:=dll.wgpuSharedTextureMemoryBeginAccess).restype, wgpuSharedTextureMemoryBeginAccess.argtypes = WGPUStatus, [WGPUSharedTextureMemory, WGPUTexture, ctypes.POINTER(WGPUSharedTextureMemoryBeginAccessDescriptor)] +except AttributeError: pass + +# WGPUTexture wgpuSharedTextureMemoryCreateTexture(WGPUSharedTextureMemory sharedTextureMemory, const WGPUTextureDescriptor *descriptor) +try: (wgpuSharedTextureMemoryCreateTexture:=dll.wgpuSharedTextureMemoryCreateTexture).restype, wgpuSharedTextureMemoryCreateTexture.argtypes = WGPUTexture, [WGPUSharedTextureMemory, ctypes.POINTER(WGPUTextureDescriptor)] +except AttributeError: pass + +# WGPUStatus wgpuSharedTextureMemoryEndAccess(WGPUSharedTextureMemory sharedTextureMemory, WGPUTexture texture, WGPUSharedTextureMemoryEndAccessState *descriptor) +try: (wgpuSharedTextureMemoryEndAccess:=dll.wgpuSharedTextureMemoryEndAccess).restype, wgpuSharedTextureMemoryEndAccess.argtypes = WGPUStatus, [WGPUSharedTextureMemory, WGPUTexture, ctypes.POINTER(WGPUSharedTextureMemoryEndAccessState)] +except AttributeError: pass + +# WGPUStatus wgpuSharedTextureMemoryGetProperties(WGPUSharedTextureMemory sharedTextureMemory, WGPUSharedTextureMemoryProperties *properties) +try: (wgpuSharedTextureMemoryGetProperties:=dll.wgpuSharedTextureMemoryGetProperties).restype, wgpuSharedTextureMemoryGetProperties.argtypes = WGPUStatus, [WGPUSharedTextureMemory, ctypes.POINTER(WGPUSharedTextureMemoryProperties)] +except AttributeError: pass + +# WGPUBool wgpuSharedTextureMemoryIsDeviceLost(WGPUSharedTextureMemory sharedTextureMemory) +try: (wgpuSharedTextureMemoryIsDeviceLost:=dll.wgpuSharedTextureMemoryIsDeviceLost).restype, wgpuSharedTextureMemoryIsDeviceLost.argtypes = WGPUBool, [WGPUSharedTextureMemory] +except AttributeError: pass + +# void wgpuSharedTextureMemorySetLabel(WGPUSharedTextureMemory sharedTextureMemory, WGPUStringView label) +try: (wgpuSharedTextureMemorySetLabel:=dll.wgpuSharedTextureMemorySetLabel).restype, wgpuSharedTextureMemorySetLabel.argtypes = None, [WGPUSharedTextureMemory, WGPUStringView] +except AttributeError: pass + +# void wgpuSharedTextureMemoryAddRef(WGPUSharedTextureMemory sharedTextureMemory) +try: (wgpuSharedTextureMemoryAddRef:=dll.wgpuSharedTextureMemoryAddRef).restype, wgpuSharedTextureMemoryAddRef.argtypes = None, [WGPUSharedTextureMemory] +except AttributeError: pass + +# void wgpuSharedTextureMemoryRelease(WGPUSharedTextureMemory sharedTextureMemory) +try: (wgpuSharedTextureMemoryRelease:=dll.wgpuSharedTextureMemoryRelease).restype, wgpuSharedTextureMemoryRelease.argtypes = None, [WGPUSharedTextureMemory] +except AttributeError: pass + +# void wgpuSurfaceConfigure(WGPUSurface surface, const WGPUSurfaceConfiguration *config) +try: (wgpuSurfaceConfigure:=dll.wgpuSurfaceConfigure).restype, wgpuSurfaceConfigure.argtypes = None, [WGPUSurface, ctypes.POINTER(WGPUSurfaceConfiguration)] +except AttributeError: pass + +# WGPUStatus wgpuSurfaceGetCapabilities(WGPUSurface surface, WGPUAdapter adapter, WGPUSurfaceCapabilities *capabilities) +try: (wgpuSurfaceGetCapabilities:=dll.wgpuSurfaceGetCapabilities).restype, wgpuSurfaceGetCapabilities.argtypes = WGPUStatus, [WGPUSurface, WGPUAdapter, ctypes.POINTER(WGPUSurfaceCapabilities)] +except AttributeError: pass + +# void wgpuSurfaceGetCurrentTexture(WGPUSurface surface, WGPUSurfaceTexture *surfaceTexture) +try: (wgpuSurfaceGetCurrentTexture:=dll.wgpuSurfaceGetCurrentTexture).restype, wgpuSurfaceGetCurrentTexture.argtypes = None, [WGPUSurface, ctypes.POINTER(WGPUSurfaceTexture)] +except AttributeError: pass + +# void wgpuSurfacePresent(WGPUSurface surface) +try: (wgpuSurfacePresent:=dll.wgpuSurfacePresent).restype, wgpuSurfacePresent.argtypes = None, [WGPUSurface] +except AttributeError: pass + +# void wgpuSurfaceSetLabel(WGPUSurface surface, WGPUStringView label) +try: (wgpuSurfaceSetLabel:=dll.wgpuSurfaceSetLabel).restype, wgpuSurfaceSetLabel.argtypes = None, [WGPUSurface, WGPUStringView] +except AttributeError: pass + +# void wgpuSurfaceUnconfigure(WGPUSurface surface) +try: (wgpuSurfaceUnconfigure:=dll.wgpuSurfaceUnconfigure).restype, wgpuSurfaceUnconfigure.argtypes = None, [WGPUSurface] +except AttributeError: pass + +# void wgpuSurfaceAddRef(WGPUSurface surface) +try: (wgpuSurfaceAddRef:=dll.wgpuSurfaceAddRef).restype, wgpuSurfaceAddRef.argtypes = None, [WGPUSurface] +except AttributeError: pass + +# void wgpuSurfaceRelease(WGPUSurface surface) +try: (wgpuSurfaceRelease:=dll.wgpuSurfaceRelease).restype, wgpuSurfaceRelease.argtypes = None, [WGPUSurface] +except AttributeError: pass + +# WGPUTextureView wgpuTextureCreateErrorView(WGPUTexture texture, const WGPUTextureViewDescriptor *descriptor) +try: (wgpuTextureCreateErrorView:=dll.wgpuTextureCreateErrorView).restype, wgpuTextureCreateErrorView.argtypes = WGPUTextureView, [WGPUTexture, ctypes.POINTER(WGPUTextureViewDescriptor)] +except AttributeError: pass + +# WGPUTextureView wgpuTextureCreateView(WGPUTexture texture, const WGPUTextureViewDescriptor *descriptor) +try: (wgpuTextureCreateView:=dll.wgpuTextureCreateView).restype, wgpuTextureCreateView.argtypes = WGPUTextureView, [WGPUTexture, ctypes.POINTER(WGPUTextureViewDescriptor)] +except AttributeError: pass + +# void wgpuTextureDestroy(WGPUTexture texture) +try: (wgpuTextureDestroy:=dll.wgpuTextureDestroy).restype, wgpuTextureDestroy.argtypes = None, [WGPUTexture] +except AttributeError: pass + +# uint32_t wgpuTextureGetDepthOrArrayLayers(WGPUTexture texture) +try: (wgpuTextureGetDepthOrArrayLayers:=dll.wgpuTextureGetDepthOrArrayLayers).restype, wgpuTextureGetDepthOrArrayLayers.argtypes = uint32_t, [WGPUTexture] +except AttributeError: pass + +# WGPUTextureDimension wgpuTextureGetDimension(WGPUTexture texture) +try: (wgpuTextureGetDimension:=dll.wgpuTextureGetDimension).restype, wgpuTextureGetDimension.argtypes = WGPUTextureDimension, [WGPUTexture] +except AttributeError: pass + +# WGPUTextureFormat wgpuTextureGetFormat(WGPUTexture texture) +try: (wgpuTextureGetFormat:=dll.wgpuTextureGetFormat).restype, wgpuTextureGetFormat.argtypes = WGPUTextureFormat, [WGPUTexture] +except AttributeError: pass + +# uint32_t wgpuTextureGetHeight(WGPUTexture texture) +try: (wgpuTextureGetHeight:=dll.wgpuTextureGetHeight).restype, wgpuTextureGetHeight.argtypes = uint32_t, [WGPUTexture] +except AttributeError: pass + +# uint32_t wgpuTextureGetMipLevelCount(WGPUTexture texture) +try: (wgpuTextureGetMipLevelCount:=dll.wgpuTextureGetMipLevelCount).restype, wgpuTextureGetMipLevelCount.argtypes = uint32_t, [WGPUTexture] +except AttributeError: pass + +# uint32_t wgpuTextureGetSampleCount(WGPUTexture texture) +try: (wgpuTextureGetSampleCount:=dll.wgpuTextureGetSampleCount).restype, wgpuTextureGetSampleCount.argtypes = uint32_t, [WGPUTexture] +except AttributeError: pass + +# WGPUTextureUsage wgpuTextureGetUsage(WGPUTexture texture) +try: (wgpuTextureGetUsage:=dll.wgpuTextureGetUsage).restype, wgpuTextureGetUsage.argtypes = WGPUTextureUsage, [WGPUTexture] +except AttributeError: pass + +# uint32_t wgpuTextureGetWidth(WGPUTexture texture) +try: (wgpuTextureGetWidth:=dll.wgpuTextureGetWidth).restype, wgpuTextureGetWidth.argtypes = uint32_t, [WGPUTexture] +except AttributeError: pass + +# void wgpuTextureSetLabel(WGPUTexture texture, WGPUStringView label) +try: (wgpuTextureSetLabel:=dll.wgpuTextureSetLabel).restype, wgpuTextureSetLabel.argtypes = None, [WGPUTexture, WGPUStringView] +except AttributeError: pass + +# void wgpuTextureAddRef(WGPUTexture texture) +try: (wgpuTextureAddRef:=dll.wgpuTextureAddRef).restype, wgpuTextureAddRef.argtypes = None, [WGPUTexture] +except AttributeError: pass + +# void wgpuTextureRelease(WGPUTexture texture) +try: (wgpuTextureRelease:=dll.wgpuTextureRelease).restype, wgpuTextureRelease.argtypes = None, [WGPUTexture] +except AttributeError: pass + +# void wgpuTextureViewSetLabel(WGPUTextureView textureView, WGPUStringView label) +try: (wgpuTextureViewSetLabel:=dll.wgpuTextureViewSetLabel).restype, wgpuTextureViewSetLabel.argtypes = None, [WGPUTextureView, WGPUStringView] +except AttributeError: pass + +# void wgpuTextureViewAddRef(WGPUTextureView textureView) +try: (wgpuTextureViewAddRef:=dll.wgpuTextureViewAddRef).restype, wgpuTextureViewAddRef.argtypes = None, [WGPUTextureView] +except AttributeError: pass + +# void wgpuTextureViewRelease(WGPUTextureView textureView) +try: (wgpuTextureViewRelease:=dll.wgpuTextureViewRelease).restype, wgpuTextureViewRelease.argtypes = None, [WGPUTextureView] +except AttributeError: pass + +WGPUBufferUsage_None = 0x0000000000000000 +WGPUBufferUsage_MapRead = 0x0000000000000001 +WGPUBufferUsage_MapWrite = 0x0000000000000002 +WGPUBufferUsage_CopySrc = 0x0000000000000004 +WGPUBufferUsage_CopyDst = 0x0000000000000008 +WGPUBufferUsage_Index = 0x0000000000000010 +WGPUBufferUsage_Vertex = 0x0000000000000020 +WGPUBufferUsage_Uniform = 0x0000000000000040 +WGPUBufferUsage_Storage = 0x0000000000000080 +WGPUBufferUsage_Indirect = 0x0000000000000100 +WGPUBufferUsage_QueryResolve = 0x0000000000000200 +WGPUColorWriteMask_None = 0x0000000000000000 +WGPUColorWriteMask_Red = 0x0000000000000001 +WGPUColorWriteMask_Green = 0x0000000000000002 +WGPUColorWriteMask_Blue = 0x0000000000000004 +WGPUColorWriteMask_Alpha = 0x0000000000000008 +WGPUColorWriteMask_All = 0x000000000000000F +WGPUHeapProperty_DeviceLocal = 0x0000000000000001 +WGPUHeapProperty_HostVisible = 0x0000000000000002 +WGPUHeapProperty_HostCoherent = 0x0000000000000004 +WGPUHeapProperty_HostUncached = 0x0000000000000008 +WGPUHeapProperty_HostCached = 0x0000000000000010 +WGPUMapMode_None = 0x0000000000000000 +WGPUMapMode_Read = 0x0000000000000001 +WGPUMapMode_Write = 0x0000000000000002 +WGPUShaderStage_None = 0x0000000000000000 +WGPUShaderStage_Vertex = 0x0000000000000001 +WGPUShaderStage_Fragment = 0x0000000000000002 +WGPUShaderStage_Compute = 0x0000000000000004 +WGPUTextureUsage_None = 0x0000000000000000 +WGPUTextureUsage_CopySrc = 0x0000000000000001 +WGPUTextureUsage_CopyDst = 0x0000000000000002 +WGPUTextureUsage_TextureBinding = 0x0000000000000004 +WGPUTextureUsage_StorageBinding = 0x0000000000000008 +WGPUTextureUsage_RenderAttachment = 0x0000000000000010 +WGPUTextureUsage_TransientAttachment = 0x0000000000000020 +WGPUTextureUsage_StorageAttachment = 0x0000000000000040 \ No newline at end of file diff --git a/tinygrad/runtime/ops_amd.py b/tinygrad/runtime/ops_amd.py index c16311a58e..d97a2f79b2 100644 --- a/tinygrad/runtime/ops_amd.py +++ b/tinygrad/runtime/ops_amd.py @@ -188,14 +188,9 @@ class AMDComputeQueue(HWQueue): ### SQTT ### def sqtt_setup_exec(self, prg, global_size): - self.sqtt_userdata(sqtt.struct_rgp_sqtt_marker_pipeline_bind( - _0=sqtt.union_rgp_sqtt_marker_pipeline_bind_0(_0=sqtt.struct_rgp_sqtt_marker_pipeline_bind_0_0( - identifier=sqtt.RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE, bind_point=(__BIND_POINT_COMPUTE:=1))), - _1=sqtt.union_rgp_sqtt_marker_pipeline_bind_1(api_pso_hash=data64_le(prg.libhash[0])))) - - self.sqtt_userdata(sqtt.struct_rgp_sqtt_marker_event( - _0=sqtt.union_rgp_sqtt_marker_event_0(_0=sqtt.struct_rgp_sqtt_marker_event_0_0(has_thread_dims=1)), - _2=sqtt.union_rgp_sqtt_marker_event_2(cmd_id=next(prg.dev.sqtt_next_cmd_id))), *global_size) + self.sqtt_userdata(sqtt.struct_rgp_sqtt_marker_pipeline_bind(identifier=sqtt.RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE, + bind_point=(__BIND_POINT_COMPUTE:=1), api_pso_hash=data64_le(prg.libhash[0]))) + self.sqtt_userdata(sqtt.struct_rgp_sqtt_marker_event(has_thread_dims=1, cmd_id=next(prg.dev.sqtt_next_cmd_id)), *global_size) se_cap = max(prod([x if isinstance(x, int) else 1 for x in global_size]) // 4, 1) // 32 for xcc in range(self.dev.xccs): diff --git a/tinygrad/runtime/ops_cuda.py b/tinygrad/runtime/ops_cuda.py index c20a6763da..8ab43cfa65 100644 --- a/tinygrad/runtime/ops_cuda.py +++ b/tinygrad/runtime/ops_cuda.py @@ -11,7 +11,7 @@ if MOCKGPU:=getenv("MOCKGPU"): from test.mockgpu.cuda import cuda # type: ignore def check(status): if status != 0: - error = ctypes.string_at(init_c_var(ctypes.POINTER(ctypes.c_char)(), lambda x: cuda.cuGetErrorString(status, ctypes.byref(x)))).decode() + error = ctypes.string_at(init_c_var(ctypes.c_char_p(), lambda x: cuda.cuGetErrorString(status, x))).decode() raise RuntimeError(f"CUDA Error {status}, {error}") def encode_args(args, vals) -> tuple[ctypes.Structure, ctypes.Array]: @@ -42,7 +42,7 @@ class CUDAProgram: status = cuda.cuModuleLoadData(ctypes.byref(self.module), lib) if status != 0: del self.module - raise RuntimeError(f"module load failed with status code {status}: {cuda.cudaError_enum__enumvalues[status]}") + raise RuntimeError(f"module load failed with status code {status}: {cuda.CUresult.get(status)}") check(cuda.cuModuleGetFunction(ctypes.byref(prg := cuda.CUfunction()), self.module, name.encode("utf-8"))) self.prg = prg if self.smem > 0: check(cuda.cuFuncSetAttribute(self.prg, cuda.CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES, self.smem)) diff --git a/tinygrad/runtime/ops_nv.py b/tinygrad/runtime/ops_nv.py index f4c0c997cf..6af489b96f 100644 --- a/tinygrad/runtime/ops_nv.py +++ b/tinygrad/runtime/ops_nv.py @@ -36,7 +36,7 @@ def uvm_ioctl(cmd, sttyp, fd:FileIOInterface, **kwargs): def make_uvm_type(): return type("NVUVM", (object,), {name.replace("UVM_", "").lower(): functools.partial(uvm_ioctl, dt, getattr(nv_gpu, name+"_PARAMS")) - for name,dt in nv_gpu.__dict__.items() if name.startswith("UVM_") and nv_gpu.__dict__.get(name+"_PARAMS")}) + for name,dt in nv_gpu.__dict__.items() if name.startswith("UVM_") and nv_gpu.__dict__.get(name+"_PARAMS")}) uvm = make_uvm_type() class QMD: @@ -436,7 +436,7 @@ class NVKIface: def _gpu_uvm_map(self, va_base, size, mem_handle, create_range=True, has_cpu_mapping=False) -> HCQBuffer: if create_range: uvm.create_external_range(self.fd_uvm, base=va_base, length=size) - attrs = (nv_gpu.struct_c__SA_UvmGpuMappingAttributes*256)(nv_gpu.struct_c__SA_UvmGpuMappingAttributes(gpuUuid=self.gpu_uuid, gpuMappingType=1)) + attrs = (nv_gpu.UvmGpuMappingAttributes*256)(nv_gpu.UvmGpuMappingAttributes(gpuUuid=self.gpu_uuid, gpuMappingType=1)) # NOTE: va_addr is set to make rawbufs compatible with HCQBuffer protocol. return HCQBuffer(va_base, size, meta=uvm.map_external_allocation(self.fd_uvm, base=va_base, length=size, rmCtrlFd=self.fd_ctl.fd, diff --git a/tinygrad/runtime/ops_qcom.py b/tinygrad/runtime/ops_qcom.py index ba14457050..dbcf6d7c27 100644 --- a/tinygrad/runtime/ops_qcom.py +++ b/tinygrad/runtime/ops_qcom.py @@ -321,13 +321,15 @@ class QCOMAllocator(HCQAllocatorBase): self.dev.synchronize() self.dev._gpu_free(opaque) +def flag(nm, val): return (val << getattr(kgsl, f"{nm}_SHIFT")) & getattr(kgsl, f"{nm}_MASK") + class QCOMDevice(HCQCompiled): def __init__(self, device:str=""): self.fd = FileIOInterface('/dev/kgsl-3d0', os.O_RDWR) self.dummy_addr = cast(int, self._gpu_alloc(0x1000).va_addr) flags = kgsl.KGSL_CONTEXT_PREAMBLE | kgsl.KGSL_CONTEXT_PWR_CONSTRAINT | kgsl.KGSL_CONTEXT_NO_FAULT_TOLERANCE | kgsl.KGSL_CONTEXT_NO_GMEM_ALLOC \ - | kgsl.KGSL_CONTEXT_PRIORITY(getenv("QCOM_PRIORITY", 8)) | kgsl.KGSL_CONTEXT_PREEMPT_STYLE(kgsl.KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN) + | flag("KGSL_CONTEXT_PRIORITY", getenv("QCOM_PRIORITY", 8)) | flag("KGSL_CONTEXT_PREEMPT_STYLE", kgsl.KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN) self.ctx = kgsl.IOCTL_KGSL_DRAWCTXT_CREATE(self.fd, flags=flags).drawctxt_id self.cmd_buf = self._gpu_alloc(16 << 20) @@ -357,8 +359,8 @@ class QCOMDevice(HCQCompiled): functools.partial(QCOMComputeQueue, self), None) def _gpu_alloc(self, size:int, flags:int=0, uncached=False, fill_zeroes=False) -> HCQBuffer: - flags |= kgsl.KGSL_MEMALIGN(alignment_hint:=12) | kgsl.KGSL_MEMFLAGS_USE_CPU_MAP - if uncached: flags |= kgsl.KGSL_CACHEMODE(kgsl.KGSL_CACHEMODE_UNCACHED) + flags |= flag("KGSL_MEMALIGN", alignment_hint:=12) | kgsl.KGSL_MEMFLAGS_USE_CPU_MAP + if uncached: flags |= flag("KGSL_CACHEMODE", kgsl.KGSL_CACHEMODE_UNCACHED) alloc = kgsl.IOCTL_KGSL_GPUOBJ_ALLOC(self.fd, size=(bosz:=round_up(size, 1< memoryview: tmp_buffer = webgpu.wgpuDeviceCreateBuffer(dev, webgpu.WGPUBufferDescriptor(size=size, usage=webgpu.WGPUBufferUsage_CopyDst | webgpu.WGPUBufferUsage_MapRead, mappedAtCreation=False)) copy_buffer_to_buffer(dev, buf, 0, tmp_buffer, 0, size) - _run(webgpu.wgpuBufferMapAsync2, webgpu.WGPUBufferMapCallbackInfo2, webgpu.WGPUBufferMapCallback2, webgpu.WGPUBufferMapAsyncStatus__enumvalues, - None, 0, tmp_buffer, webgpu.WGPUMapMode_Read, 0, size) + _run(webgpu.wgpuBufferMapAsync2, webgpu.WGPUBufferMapCallbackInfo2, webgpu.WGPUBufferMapCallback2, webgpu.WGPUBufferMapAsyncStatus, None, 0, + tmp_buffer, webgpu.WGPUMapMode_Read, 0, size) void_ptr = ctypes.cast(webgpu.wgpuBufferGetConstMappedRange(tmp_buffer, 0, size), ctypes.c_void_p) buf_copy = bytearray((ctypes.c_uint8 * size).from_address(void_ptr.value)) webgpu.wgpuBufferUnmap(tmp_buffer) @@ -140,7 +140,7 @@ class WebGPUProgram: compute_desc = webgpu.WGPUComputePipelineDescriptor(layout=pipeline_layout, compute=webgpu.WGPUComputeState(module=self.prg, entryPoint=to_wgpu_str(self.name))) pipeline_result = _run(webgpu.wgpuDeviceCreateComputePipelineAsync2, webgpu.WGPUCreateComputePipelineAsyncCallbackInfo2, - webgpu.WGPUCreateComputePipelineAsyncCallback2, webgpu.WGPUCreatePipelineAsyncStatus__enumvalues, 1, None, self.dev, compute_desc) + webgpu.WGPUCreateComputePipelineAsyncCallback2, webgpu.WGPUCreatePipelineAsyncStatus, 1, None, self.dev, compute_desc) command_encoder = webgpu.wgpuDeviceCreateCommandEncoder(self.dev, webgpu.WGPUCommandEncoderDescriptor()) comp_pass_desc = webgpu.WGPUComputePassDescriptor(nextInChain=None) @@ -195,9 +195,7 @@ class WebGpuDevice(Compiled): def __init__(self, device:str): # Requesting an adapter adapter_res = _run(webgpu.wgpuInstanceRequestAdapterF, webgpu.WGPURequestAdapterCallbackInfo, webgpu.WGPURequestAdapterCallback, - webgpu.WGPURequestAdapterStatus__enumvalues, 1, 2, instance, - - webgpu.WGPURequestAdapterOptions(powerPreference=webgpu.WGPUPowerPreference_HighPerformance, + webgpu.WGPURequestAdapterStatus, 1, 2, instance, webgpu.WGPURequestAdapterOptions(powerPreference=webgpu.WGPUPowerPreference_HighPerformance, backendType=backend_types.get(os.getenv("WEBGPU_BACKEND", ""), 0))) # Get supported features @@ -215,11 +213,11 @@ class WebGpuDevice(Compiled): # Requesting a device device_res = _run(webgpu.wgpuAdapterRequestDeviceF, webgpu.WGPURequestDeviceCallbackInfo, webgpu.WGPURequestDeviceCallback, - webgpu.WGPURequestDeviceStatus__enumvalues, 1, 2, adapter_res, dev_desc) + webgpu.WGPURequestDeviceStatus, 1, 2, adapter_res, dev_desc) super().__init__(device, WebGpuAllocator(device_res), [(WGSLRenderer, Compiler)], functools.partial(WebGPUProgram, (device_res, webgpu.WGPUFeatureName_TimestampQuery in supported))) def synchronize(self): _run(webgpu.wgpuQueueOnSubmittedWorkDone2, webgpu.WGPUQueueWorkDoneCallbackInfo2, webgpu.WGPUQueueWorkDoneCallback2, - webgpu.WGPUQueueWorkDoneStatus__enumvalues, None, None, webgpu.wgpuDeviceGetQueue(self.runtime.args[0][0])) + webgpu.WGPUQueueWorkDoneStatus, None, None, webgpu.wgpuDeviceGetQueue(self.runtime.args[0][0])) diff --git a/tinygrad/runtime/support/am/amdev.py b/tinygrad/runtime/support/am/amdev.py index 3a8efd8a8e..3ee72f3f17 100644 --- a/tinygrad/runtime/support/am/amdev.py +++ b/tinygrad/runtime/support/am/amdev.py @@ -238,8 +238,6 @@ class AMDev(PCIDevImplBase): ihdr = am.struct_ip_discovery_header.from_address(ctypes.addressof(self.bhdr) + self.bhdr.table_list[am.IP_DISCOVERY].offset) assert self.bhdr.binary_signature == am.BINARY_SIGNATURE and ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE, "discovery signatures mismatch" - # Mapping of HW IP to Discovery HW IP - hw_id_map = {am.__dict__[x]: int(y) for x,y in am.hw_id_map} self.regs_offset:dict[int, dict[int, tuple]] = collections.defaultdict(dict) self.ip_ver:dict[int, tuple[int, int, int]] = {} @@ -251,7 +249,7 @@ class AMDev(PCIDevImplBase): ip = am.struct_ip_v4.from_address(ip_offset) ba = ((ctypes.c_uint64 if ihdr.base_addr_64_bit else ctypes.c_uint32) * ip.num_base_address).from_address(ip_offset + 8) for hw_ip in range(1, am.MAX_HWIP): - if hw_ip in hw_id_map and hw_id_map[hw_ip] == ip.hw_id: + if hw_ip in am.hw_id_map and am.hw_id_map[hw_ip] == ip.hw_id: self.regs_offset[hw_ip][ip.instance_number] = tuple(list(ba)) self.ip_ver[hw_ip] = (ip.major, ip.minor, ip.revision) diff --git a/tinygrad/runtime/support/am/ip.py b/tinygrad/runtime/support/am/ip.py index 39a897d79d..594d17fe3d 100644 --- a/tinygrad/runtime/support/am/ip.py +++ b/tinygrad/runtime/support/am/ip.py @@ -427,7 +427,7 @@ class AM_PSP(AM_IP): self._wait_for_bootloader() - if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading sos component: {am.psp_fw_type__enumvalues[fw]}") + if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading sos component: {am.enum_psp_fw_type.get(fw)}") self._prep_msg1(self.adev.fw.sos_fw[fw]) self.adev.reg(f"{self.reg_pref}_36").write(self.msg1_addr >> 20) @@ -482,7 +482,7 @@ class AM_PSP(AM_IP): def _load_ip_fw_cmd(self, fw_types:list[int], fw_bytes:memoryview): self._prep_msg1(fw_bytes) for fw_type in fw_types: - if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading fw: {am.psp_gfx_fw_type__enumvalues[fw_type]}") + if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading fw: {am.enum_psp_gfx_fw_type.get(fw_type)}") cmd = am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_LOAD_IP_FW) cmd.cmd.cmd_load_ip_fw.fw_phy_addr_hi, cmd.cmd.cmd_load_ip_fw.fw_phy_addr_lo = data64(self.msg1_addr) cmd.cmd.cmd_load_ip_fw.fw_size = len(fw_bytes) diff --git a/tinygrad/runtime/support/autogen.py b/tinygrad/runtime/support/autogen.py index ff294e3956..0a62689b59 100644 --- a/tinygrad/runtime/support/autogen.py +++ b/tinygrad/runtime/support/autogen.py @@ -47,7 +47,6 @@ def gen(dll, files, args=[], prolog=[], rules=[], epilog=[], recsym=False, use_e return types[t.spelling][0] case TK.RECORD: # TODO: packed unions - # TODO: pragma pack support # check for forward declaration if t.spelling in types: types[t.spelling] = (nm:=types[t.spelling][0]), len(list(t.get_fields())) != 0 else: @@ -56,11 +55,15 @@ def gen(dll, files, args=[], prolog=[], rules=[], epilog=[], recsym=False, use_e else: types[t.spelling] = (nm:=t.spelling.replace(' ', '_').replace('::', '_')), len(list(t.get_fields())) != 0 lines.append(f"class {nm}({'Struct' if decl.kind==CK.STRUCT_DECL else 'ctypes.Union'}): pass") if typedef: lines.append(f"{typedef} = {nm}") + if (is_packed:=(CK.PACKED_ATTR in attrs(decl)) or ((N:=t.get_align()) != max([f.type.get_align() for f in t.get_fields()], default=N))): + if t.get_align() != 1: + print(f"WARNING: ignoring alignment={t.get_align()} on {t.spelling}") + is_packed = False acnt = itertools.count().__next__ ll=[" ("+((fn:=f"'_{acnt()}'")+f", {tname(f.type, nm+fn[1:-1])}" if f.is_anonymous_record_decl() else f"'{f.spelling}', "+ tname(f.type, f'{nm}_{f.spelling}'))+(f',{f.get_bitfield_width()}' if f.is_bitfield() else '')+")," for f in t.get_fields()] lines.extend(([f"{nm}._anonymous_ = ["+", ".join(f"'_{i}'" for i in range(n))+"]"] if (n:=acnt()) else [])+ - ([f"{nm}._packed_ = True"] * (CK.PACKED_ATTR in attrs(decl)))+([f"{nm}._fields_ = [",*ll,"]"] if ll else [])) + ([f"{nm}._packed_ = True"] * is_packed)+([f"{nm}._fields_ = [",*ll,"]"] if ll else [])) return nm case TK.ENUM: # TODO: C++ and GNU C have forward declared enums diff --git a/tinygrad/runtime/support/c.py b/tinygrad/runtime/support/c.py index b06692498c..7e4f199fad 100644 --- a/tinygrad/runtime/support/c.py +++ b/tinygrad/runtime/support/c.py @@ -1,10 +1,13 @@ import ctypes, functools, sys from typing import TYPE_CHECKING +from tinygrad.helpers import flatten +from _ctypes import _SimpleCData -def _do_ioctl(__idir, __base, __nr, __struct, __fd, **kwargs): +def _do_ioctl(__idir, __base, __nr, __struct, __fd, *args, __payload=None, **kwargs): import tinygrad.runtime.support.hcq as hcq, fcntl ioctl = __fd.ioctl if isinstance(__fd, hcq.FileIOInterface) else functools.partial(fcntl.ioctl, __fd) - if (rc:=ioctl((__idir<<30)|(ctypes.sizeof(out:=__struct(**kwargs))<<16)|(__base<<8)|__nr, out)): raise RuntimeError(f"ioctl returned {rc}") + if (rc:=ioctl((__idir<<30)|(ctypes.sizeof(out:=(__payload or __struct(*args, **kwargs)))<<16)|(__base<<8)|__nr, out)): + raise RuntimeError(f"ioctl returned {rc}") return out def _IO(base, nr): return functools.partial(_do_ioctl, 0, ord(base) if isinstance(base, str) else base, nr, None) @@ -50,16 +53,28 @@ else: @staticmethod def _build(cls, fields): - o = 0 - for n,t,b in [(f[0], f[1], f[2] if len(f) == 3 else 0) for f in fields]: - if b == 0: o = (o + 7) & ~7 - m = (1 << (sz:=ctypes.sizeof(t)*8 if b == 0 else b)) - 1 - def _s(self,v,m,s,b): self._data[:] = ((int.from_bytes(self._data,sys.byteorder)&~(m<>s)&m,m=m,s=o), - functools.partial(_s,m=m,s=o,b=b))) - o += sz + offset = 0 + for nm, ty, bf in [(f[0], f[1], f[2] if len(f) == 3 else 0) for f in fields]: + if bf == 0: offset = (offset + 7) & ~7 + mask = (1 << (sz:=ctypes.sizeof(ty)*8 if bf == 0 else bf)) - 1 + def fget(self, mask, off, ty): return ((int.from_bytes(self._data, sys.byteorder)>>off)&mask if issubclass(ty, _SimpleCData) else + ty.from_buffer(memoryview(self._data)[(st:=off//8):st+ctypes.sizeof(ty)])) + def fset(self, val, mask, off): self._data[:] = (((int.from_bytes(self._data, sys.byteorder) & ~(mask<= 3: - # in comgr 3 the values of enums in headers were changed: https://github.com/ROCm/llvm-project/issues/272 - import tinygrad.runtime.autogen.comgr_3 as comgr # type: ignore[no-redef] - assert comgr.AMD_COMGR_LANGUAGE_HIP == 3 -except AttributeError: pass # ignore if ROCm isn't installed + assert comgr.AMD_COMGR_LANGUAGE_HIP == 3 if major.value >= 3 else 4 +except AttributeError: assert comgr.AMD_COMGR_LANGUAGE_HIP == 3 # if rocm is not installed, use old values from tinygrad.device import Compiler, CompileError from tinygrad.runtime.support.compiler_cpu import LLVMCompiler from tinygrad.helpers import OSX, to_char_p_p diff --git a/tinygrad/runtime/support/compiler_cpu.py b/tinygrad/runtime/support/compiler_cpu.py index 04c2987180..553706f3e1 100644 --- a/tinygrad/runtime/support/compiler_cpu.py +++ b/tinygrad/runtime/support/compiler_cpu.py @@ -1,8 +1,8 @@ import ctypes, platform, sys, subprocess from tinygrad.device import Compiler -from tinygrad.helpers import OSX, getenv, capstone_flatdump, DEBUG +from tinygrad.helpers import OSX, getenv, capstone_flatdump, DEBUG, unwrap from tinygrad.runtime.support.elf import jit_loader -try: import tinygrad.runtime.autogen.llvm as llvm +try: from tinygrad.runtime.autogen import llvm except (ImportError, FileNotFoundError): llvm = None #type:ignore[assignment] class ClangJITCompiler(Compiler): @@ -24,7 +24,7 @@ class ClangJITCompiler(Compiler): def cerr(): return ctypes.pointer(ctypes.pointer(ctypes.c_char())) def expect(x, err, ret=None): - if x: raise RuntimeError(llvm.string_cast(err.contents) if not isinstance(err, str) else err) + if x: raise RuntimeError(unwrap(ctypes.cast(err.contents, ctypes.c_char_p).value).decode() if not isinstance(err, str) else err) return ret class LLVMCompiler(Compiler): @@ -50,7 +50,7 @@ class LLVMCompiler(Compiler): self.passes = b'default' self.diag_msgs: list[str] = [] - @ctypes.CFUNCTYPE(None, llvm.LLVMDiagnosticInfoRef, ctypes.c_void_p) + @llvm.LLVMDiagnosticHandler def handle_diag(diag_ref, _arg): severity = llvm.LLVMGetDiagInfoSeverity(diag_ref) msg = ctypes.string_at(llvm.LLVMGetDiagInfoDescription(diag_ref)).decode() @@ -70,7 +70,7 @@ class LLVMCompiler(Compiler): expect(llvm.LLVMRunPasses(mod, self.passes, self.target_machine, self.pbo), 'failed to run passes') if DEBUG >= 7: print(ctypes.string_at(llvm.LLVMPrintModuleToString(mod)).decode()) obj_buf = expect(llvm.LLVMTargetMachineEmitToMemoryBuffer(self.target_machine, mod, llvm.LLVMObjectFile, err:=cerr(), - ctypes.pointer(buf:=llvm.LLVMMemoryBufferRef())), err, buf) + buf:=llvm.LLVMMemoryBufferRef()), err, buf) llvm.LLVMDisposeModule(mod) obj = ctypes.string_at(llvm.LLVMGetBufferStart(obj_buf), llvm.LLVMGetBufferSize(obj_buf)) llvm.LLVMDisposeMemoryBuffer(obj_buf) diff --git a/tinygrad/runtime/support/compiler_cuda.py b/tinygrad/runtime/support/compiler_cuda.py index fb493c6ab6..c8b1b4634a 100644 --- a/tinygrad/runtime/support/compiler_cuda.py +++ b/tinygrad/runtime/support/compiler_cuda.py @@ -1,7 +1,7 @@ import subprocess, hashlib, tempfile, ctypes, re, pathlib from typing import Callable from tinygrad.helpers import to_char_p_p, colored, init_c_var, getenv, system -import tinygrad.runtime.autogen.nvrtc as nvrtc +from tinygrad.runtime.autogen import nvrtc, nvjitlink as jitlink from tinygrad.device import Compiler, CompileError CUDA_PATH = getenv("CUDA_PATH", "") @@ -17,8 +17,8 @@ def nvrtc_check(status, ctx=None): def jitlink_check(status, ctx=None): if status != 0: - err_log = _get_bytes(ctx, nvrtc.nvJitLinkGetErrorLog, nvrtc.nvJitLinkGetErrorLogSize, lambda _: None).decode() if ctx else "" - raise CompileError(f"NvJitLink Error {status}, {nvrtc.nvJitLinkResult__enumvalues.get(status, 'Unknown')}\n{err_log}") + err_log = _get_bytes(ctx, jitlink.nvJitLinkGetErrorLog, jitlink.nvJitLinkGetErrorLogSize, lambda _: None).decode() if ctx else "" + raise CompileError(f"jitlink Error {status}, {jitlink.nvJitLinkResult.get(status)}\n{err_log}") def pretty_ptx(s): # all expressions match `` and replace it with `color()` @@ -83,12 +83,12 @@ class PTXCompiler(Compiler): class NVPTXCompiler(PTXCompiler): def __init__(self, arch:str): - nvrtc_check(nvrtc.nvJitLinkVersion(ctypes.byref(ctypes.c_uint()), ctypes.byref(ctypes.c_uint()))) + nvrtc_check(jitlink.nvJitLinkVersion(ctypes.byref(ctypes.c_uint()), ctypes.byref(ctypes.c_uint()))) super().__init__(arch, cache_key="nv_ptx") def compile(self, src:str) -> bytes: - jitlink_check(nvrtc.nvJitLinkCreate(handle := nvrtc.nvJitLinkHandle(), 1, to_char_p_p([f'-arch={self.arch}'.encode()])), handle) - jitlink_check(nvrtc.nvJitLinkAddData(handle, nvrtc.NVJITLINK_INPUT_PTX, ptxsrc:=super().compile(src), len(ptxsrc), "".encode()), handle) - jitlink_check(nvrtc.nvJitLinkComplete(handle), handle) - data = _get_bytes(handle, nvrtc.nvJitLinkGetLinkedCubin, nvrtc.nvJitLinkGetLinkedCubinSize, jitlink_check) - jitlink_check(nvrtc.nvJitLinkDestroy(handle)) + jitlink_check(jitlink.nvJitLinkCreate(handle := jitlink.nvJitLinkHandle(), 1, to_char_p_p([f'-arch={self.arch}'.encode()])), handle) + jitlink_check(jitlink.nvJitLinkAddData(handle, jitlink.NVJITLINK_INPUT_PTX, ptxsrc:=super().compile(src), len(ptxsrc), "".encode()), handle) + jitlink_check(jitlink.nvJitLinkComplete(handle), handle) + data = _get_bytes(handle, jitlink.nvJitLinkGetLinkedCubin, jitlink.nvJitLinkGetLinkedCubinSize, jitlink_check) + jitlink_check(jitlink.nvJitLinkDestroy(handle)) return data diff --git a/tinygrad/runtime/support/compiler_mesa.py b/tinygrad/runtime/support/compiler_mesa.py index 62f1e40a9c..8f97e12ed4 100644 --- a/tinygrad/runtime/support/compiler_mesa.py +++ b/tinygrad/runtime/support/compiler_mesa.py @@ -1,9 +1,9 @@ import base64, ctypes, pathlib, tempfile, hashlib from tinygrad.device import Compiler from tinygrad.helpers import cpu_objdump, system -import tinygrad.runtime.autogen.mesa as mesa +from tinygrad.runtime.autogen import mesa from tinygrad.runtime.support.compiler_cpu import CPULLVMCompiler, expect, cerr -try: import tinygrad.runtime.autogen.llvm as llvm +try: from tinygrad.runtime.autogen import llvm except (ImportError, FileNotFoundError): llvm = None #type:ignore[assignment] def deserialize(enc_src, opts): diff --git a/tinygrad/runtime/support/ib.py b/tinygrad/runtime/support/ib.py index c50f8ad03c..b42ecba5ec 100644 --- a/tinygrad/runtime/support/ib.py +++ b/tinygrad/runtime/support/ib.py @@ -1,5 +1,6 @@ from __future__ import annotations -import resource, ctypes, weakref, functools, itertools, tinygrad.runtime.autogen.ib as ib +import resource, ctypes, weakref, functools, itertools +from tinygrad.runtime.autogen import ib from typing import Iterator from dataclasses import dataclass from weakref import WeakKeyDictionary @@ -141,7 +142,7 @@ class IBConn: while (wr_id in self.pending_wrids) if wr_id is not None else self.pending_wrids: if self.ctx.ctx.contents.ops.poll_cq(self.cq, _num_entries:=1, ctypes.byref(wc:=ib.struct_ibv_wc())): if wc.status != ib.IBV_WC_SUCCESS: - raise RuntimeError(f'Work Request completed with error: wr_id={wc.wr_id} status={ib.ibv_wc_status__enumvalues.get(wc.status, wc.status)}') + raise RuntimeError(f'Work Request completed with error: wr_id={wc.wr_id} status={ib.enum_ibv_wc_status.get(wc.status, wc.status)}') self.pending_wrids.remove(wc.wr_id) def rdma_write(self, sgl:list[SGE]): @@ -162,7 +163,7 @@ class IBConn: # Scatter-Gather Entry for local memory sge = ctypes.pointer(ib.struct_ibv_sge(addr=sg.src_iova+off, length=min(sg.size-off, self.ctx.port_attr.max_msg_sz), lkey=sg.src_key)) # RDMA struct for remote memory - wr = ib.union_ibv_send_wr_wr(rdma=ib.struct_ibv_send_wr_1_rdma(remote_addr=sg.dst_iova+off, rkey=sg.dst_key)) + wr = ib.struct_ibv_send_wr_wr(rdma=ib.struct_ibv_send_wr_wr_rdma(remote_addr=sg.dst_iova+off, rkey=sg.dst_key)) # Signal (with chosen work request id) if it's the last wr (first in the loop since it's reversed) wid, flags = (wr_id, ib.IBV_SEND_SIGNALED) if swr is None else (0, 0) # Create Send Request diff --git a/tinygrad/runtime/support/nv/ip.py b/tinygrad/runtime/support/nv/ip.py index 7bce6314c9..c0bf6ece8f 100644 --- a/tinygrad/runtime/support/nv/ip.py +++ b/tinygrad/runtime/support/nv/ip.py @@ -1,11 +1,10 @@ from __future__ import annotations import ctypes, time, array, struct, itertools, dataclasses from typing import cast, Any -from tinygrad.runtime.autogen.nv import nv +from tinygrad.runtime.autogen import nv, nv_gpu, pci from tinygrad.helpers import to_mv, lo32, hi32, DEBUG, round_up, round_down, mv_address, fetch, wait_cond from tinygrad.runtime.support.system import System from tinygrad.runtime.support.elf import elf_loader -from tinygrad.runtime.autogen import nv_gpu, pci @dataclasses.dataclass(frozen=True) class GRBufDesc: size:int; virt:bool; phys:bool; local:bool=False # noqa: E702 @@ -69,8 +68,8 @@ class NVRpcQueue: System.memory_barrier() if DEBUG >= 3: - rpc_names = {**nv.c__Ea_NV_VGPU_MSG_FUNCTION_NOP__enumvalues, **nv.c__Ea_NV_VGPU_MSG_EVENT_FIRST_EVENT__enumvalues} - print(f"nv {self.gsp.nvdev.devfmt}: in RPC: {rpc_names.get(hdr.function, f'ev:{hdr.function:x}')}, res:{hdr.rpc_result:#x}") + nm = nv.rpc_fns.get(hdr.function, nv.rpc_events.get(hdr.function, f'ev:{hdr.function:x}')) + print(f"nv {self.gsp.nvdev.devfmt}: in RPC: {nm}, res:{hdr.rpc_result:#x}") if hdr.rpc_result != 0: raise RuntimeError(f"RPC call {hdr.function} failed with result {hdr.rpc_result}") if hdr.function == cmd: return msg @@ -443,7 +442,7 @@ class NV_GSP(NV_IP): bufs_p = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(pageSize=res_sz, numLevelsToCopy=3, virtAddrLo=res_va, virtAddrHi=res_va + res_sz - 1) for i,pt in enumerate(self.nvdev.mm.page_tables(res_va, size=res_sz)): - bufs_p.levels[i] = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(physAddress=pt.paddr, + bufs_p.levels[i] = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level(physAddress=pt.paddr, size=self.nvdev.mm.pte_cnt[0] * 8 if i == 0 else 0x1000, pageShift=self.nvdev.mm.pte_covers[i].bit_length() - 1, aperture=1) self.rpc_rm_control(hObject=vaspace, cmd=nv_gpu.NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES, params=bufs_p)